Sharing decoupling capacitors - Page 1
Forum section: electronics / projects

author: OM222O
author_rank: Frequent Contributor
timestamp: May 16, 2019, 11:01:09 pm
content: I think I've been using too many decoupling capacitors in my designs, with each chip getting a 100nF decoupling capacitor of its own.sometimes two chips are as close to each other as physically possible, for example: an op amp and a voltage reference both powered from a 5v supply. A lot of times the chips work well even without any decoupling like Dave showed in his megatron computer video. I was wondering if two chips that are close to each other (usually SOIC-8, so very very close) can share the same 100nF decoupling cap or if I should bump it to let's say 1uF for good measure if I decide to make it shared.

author: golden_labels
author_rank: Super Contributor
timestamp: May 16, 2019, 11:37:29 pm
content: Decoupling capacitors on power lines are there not only to protect an IC against noise and trace inductance effects, but also to protect the rest of the circuit from that IC. This works both ways. As an example see separated power inputs for ADC/DAC and digital parts in microcontrollers. You are literally separating the chip from itself with a pair of decoupling capacitors, because the digital section can cause so much noise that it will affect the analog part.You may remove as many caps as you wish. It’s not like they’re strictly required for chips to work properly. All that happens, when you remove a capacitor, is going outside manufacturer’s spec.Here be dragons. Just that and nothing more. It’s a matter of risk you want to take. Can you test the circuit well enough to show it will work? Remove them. Can you accept the risk involved? Remove them. But there is no general silver bullet solution: you will need to experiment, test and understand what happens in your circuit without a cap.I am myself not believing, that I’ve said the above. For me, as a software developer aiming to write good software, the above is a blasphemy.

author: DaJMasta
author_rank: Super Contributor
timestamp: May 16, 2019, 11:43:46 pm
content: The problem is the 100nF guideline is generally for digital stuff and is only a guideline... there are instances where following it can actually cause issues, and there are instances where you can get away with a tiny fraction of the decoupling caps.So unless you expect the amp to be using its maximum slew rate a lot or sourcing a lot of current, it probably won't be generating as much noise as a fast toggling digital circuit, but since it's analog stuff which is generally going to be more effected by noise, why not "compromise" and use a couple of different values, maybe a 100nF and a 1uF, maybe a 100nF and a 10nF. Having your reference bypassed is important, and having a reservoir of charge there is probably a good idea (maybe take a look at the datasheet recommendations), and while the circuits at this node probably won't be generating much noise on their own, they will be sensitive to smaller fluctuations in supply voltage than a digital circuit, so I wouldn't skimp on the bypassing caps which help filter the rails at the point where the current is needed.Just using a single 1uF cap would mean you had a larger charge reservoir to dampen transients, but it would also mean that the impedance of the capacitor will be higher than a 100nF or smaller cap at high frequencies, so only going with a low frequency, larger value bypass cap would actually be less effective at removing high frequency noise on the power rail than a small one.

author: ataradov
author_rank: Super Contributor
timestamp: May 16, 2019, 11:44:01 pm
content: One per chip is not sufficient in many cases. You need one per power supply pin.This does not apply to slow circuits. But it starts to matter a lot on chips with PLLs and other fast logic.I would definitely at least put a footprint for one capacitor per device. You don't have to populate it if you find it unnecessary later on.

author: OM222O
author_rank: Frequent Contributor
timestamp: May 16, 2019, 11:48:45 pm
content: most of my designs are dc with very few transients, and even then not at high frequencies. the board size is pretty small too 10x6.8cm and the tracks are no longer than a few CM. I can understand why multiple ones would be required for high speed circuits but I'm assuming sharing them between chips is fine in my case?

author: ataradov
author_rank: Super Contributor
timestamp: May 16, 2019, 11:53:46 pm
content: It will probably work, whether it is fine depends on the circuit. For very slow stuff, it is probably be fine. But again, why not put a footprint and not populate if if see that it is not needed.Also by "slow" you need to understand limited slew rate, not the rate of events. If you are switching something once a second, but with a high current driver, it is still a fast circuit, that will generate transients.Even typical 400 kHz I2C drivers are reasonably "fast" in this regard to meet the requirements of the I2C specification.

author: OM222O
author_rank: Frequent Contributor
timestamp: May 17, 2019, 12:12:11 am
content: the problem is the footprint itself. the board is so tightly packed that should either drop the capacitor size to something like a 0402 which I can't solder by hand, or use a 1uF 0603 and share it between 2 - 3 devices. I know I should have purchased the enclosures after I designed the PCB, not before, but I think sacrificing a few decoupling caps can save me here since the board is mostly routed.also since you brought up I2C, I didn't use pull ups for the exact same reason (not enough space) and after checking with a scope, the edges couldn't be any more square even with the fastest mode. I'm assuming it's due to short traces which means pretty much no parasitics.

author: ataradov
author_rank: Super Contributor
timestamp: May 17, 2019, 12:50:24 am
content: Quote from: OM222O on May 17, 2019, 12:12:11 amAnd that's exactly the problem. Those square edges tend to create all sorts of ground bouncing when the chips are not properly decoupled.If you are really strapped for space, then it is a reasonable risk to take, but it is still a risk. The worst case - you will have to redesign the board a bit.

author: langwadt
author_rank: Super Contributor
timestamp: May 17, 2019, 12:58:53 am
content: Quote from: OM222O on May 17, 2019, 12:12:11 amI2C is open-drain it requires pull-ups somewhere

author: OM222O
author_rank: Frequent Contributor
timestamp: May 17, 2019, 01:05:48 am
content: the MCU has some built in, but I think they are 50k which is normally too large and fast I2C recommends something like 2k pullup, but doesn't seem to be the case on my board

author: golden_labels
author_rank: Super Contributor
timestamp: May 17, 2019, 01:29:57 am
content: Is the microcontroller THT DIP by any chance? Use a DIP socket and you get a lot of space under the chip itself.

author: Nerull
author_rank: Frequent Contributor
timestamp: May 17, 2019, 02:02:24 am
content: A perfect square wave consists of an infinite series of increasingly higher frequency sine waves. Those 'nice square edges' are a sign that your signal is, in fact, high frequency and high speed. A slow rise time will round the edges.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 17, 2019, 02:03:23 am
content: Decoupling is overblown.In a 2-layer design, you rarely have anything fast enough, or powerful enough, to require more than infrequent decoupling. When you do (switching regulators being the most common case), simply include them as part of the local subcircuit design -- don't assume an ideal skyhook is there to save you.In a multilayer design with internal planes, you may have things fast or powerful enough to require frequent bypassing. But you also have the nearly ideal interconnect that is the power plane. Bypass caps almost anywhere on the board look equivalent. It doesn't much matter where you place them. If a chip needs very serious bypassing, caps can be placed beside the pins, or on the opposite side, under the component (e.g. BGAs). For the most part, caps on the opposite side, or not connected as directly to the pins as is possible, might as well not be there -- and here I don't mean that they can be removed entirely, but that they aren't acting locally, and can move around just about anywhere. They may however be removable, depending on whatever's on the planes, and what supply impedance is required.By the way, the ideal connection to an adjacent pair of pins*, is with a pair of vias (to internal plane) on one side, and the decoupling cap on the other. This way, the pins see two impedances in parallel: the cap and the plane. You can equally well use no cap and two pairs of vias. Or two caps and no vias, except that you can't put a cap underneath a component, so...Note that a cap on the opposite side (say in a 2-layer build) is farther away than a single cap on the same side, so doesn't do much. Single caps are fine in that case.*VDD/VSS pairs are common, say with MCUs and such, for this reason -- lower ESL. There's usually a bunch of pairs spread around the chip -- all should be connected, if not to planes then to adjacent caps. Whether any given pair of pairs can be connected to a single common cap, say -- depends. (Sometimes, these pairs are temptingly close together!)...Excessive bypasses: I think it's more psychological (read: not based on electrical theory). "No one got fired buying IBM", you know? Throw in "too many" bypass caps and you have the same situation.It's not hard to analyze these networks, and justify ones' use of decoupling capacitors. Transform pin lengths, trace lengths, via lengths and component body lengths into inductances, and construct the network from the layout topology (don't forget ESR of the various capacitors). This is an easy (under an hour?) SPICE exercise, and allows you to play with virtual placements and types (i.e., vary C and ESR and see how the transient response changes; vary the topology, or the trace lengths, etc.).Or once you understand the underlying equations (it's all about poles and zeroes), it's possible to hand-wave through this and estimate what C and ESR is needed to terminate a given branch, or what topologies are easier to terminate, or can give better filtering or isolation between sections. Then SPICE it anyway for verification, then hook up a pulse generator to a real board and demonstrate it experimentally.Tim

author: OM222O
author_rank: Frequent Contributor
timestamp: May 17, 2019, 03:51:43 am
content: Quote from: golden_labels on May 17, 2019, 01:29:57 amunfortunately the board is fully SMD. MCU is in a TQFP-32 package.Also thank you for the detailed explanation TIM. very helpful.

author: OwO
author_rank: Super Contributor
timestamp: May 17, 2019, 05:12:08 am
content: On even a 4 layer board it's not possible to have an effective power plane because with the typical stackup in1 is very far from in2 (over 1mm). I stand by my advice to put decoupling caps on the bottom side right underneath the IC, because putting them on the top side obstructs routing and unless you go to 0201 there is no way you can put them closer to within 1.6mm of the IC and still be able to route out all the other pins. In a BGA the power pins can be very far from the edge, so not putting caps on the bottom is bad advice.I have done boards with Zynq and DDR3 memory on 4 layers, and in general do not use buried power planes for the purpose of decoupling. When you do have a power plane you have to stitch it at regular intervals especially close to the current sinks (noise sources). The "inductance" seen between two planes can be significant at points not close to stitching caps, and this can be seen experimentally but impossible to simulate in spice.

author: schratterulrich
author_rank: Regular Contributor
timestamp: May 17, 2019, 05:19:55 am
content: In the past I was often unsure about the right decoupling capacitors.We then introduced a software in the company that simulates the impedance of the power delivery network. That made things easier.Depending on your transient current consumption and your voltage ripple allowed you can say that e.g. 100 mOhm up to 100 MHz would be sufficient.As mentioned by Tim you can analyze the decoupling caps and planes, so I have written my own software.It's a big help for supply systems with power planes but maybe it can help in your case tooYou can find it athttps://leiterplatte.jimdo.com/pdn-sim/The result can look like thisBest RegardsUlrich

author: ogden
author_rank: Super Contributor
timestamp: May 17, 2019, 05:31:48 am
content: Quote from: T3sl4co1l on May 17, 2019, 02:03:23 amIf you consider signal integrity, then indeed. Most "2-layer" circuits will continue operation without single decoupling capacitor. On the other hand small & seemingly innocent uC without proper decoupling can trash radiated EMC tests easily.

author: Zero999
author_rank: Super Contributor
timestamp: May 17, 2019, 08:02:09 pm
content: You quite likely don't need a decoupling capacitor for every IC, especially those which sit in a steady state.I've just built a circuit with no decoupling and it works perfectly. It's a voltage reference to give 5V and 10mV out for adjusting a DC amplifier. It's very simple, just LM4040-N-2.5 and current limiting resistor, connected to an OP07 op-amp with a gain of two and a potential divider. The output voltages are trimmed by adjusting a couple of potentiometers. There is no other high speed circuitry on the board or nearby and is powered by a 15V linear power supply module, so no decoupling capacitors are required, because there is no AC in the circuit.

author: ddavidebor
author_rank: Super Contributor
timestamp: May 17, 2019, 08:12:02 pm
content: Quote from: OM222O on May 16, 2019, 11:01:09 pmIs this a commercial product that needs to pass emi testing?How many layer is your board and what stackup do you have?

author: iMo
author_rank: Super Contributor
timestamp: May 17, 2019, 08:23:03 pm
content: Decoupling is important and usually ignored. Any today's mcu has got 5ns edges. Even a blinking with an led produces transients.And even a fully quiet DC circuit can go easily weird when irradiated by an EMI.A friend of mine is running an EMC lab and even BIG players sometimes come with something which does not pass the basic test because of a missing 1cent capacitor.That would apply to the above 5V reference source too

author: ogden
author_rank: Super Contributor
timestamp: May 17, 2019, 08:32:15 pm
content: Quote from: Zero999 on May 17, 2019, 08:02:09 pmNice example. Slew rate of OP07 is 0.3 V/us. Decoupling of such a slow opamp is useless waste of capacitors

author: iMo
author_rank: Super Contributor
timestamp: May 17, 2019, 08:41:06 pm
content: Quote from: schratterulrich on May 17, 2019, 05:19:55 amI've been searching since ever after a tool which imports the Eagle PCB file and calculates impedancies/capacitancies/inductancies/resistancies of the top and bottom tracks.

author: OM222O
author_rank: Frequent Contributor
timestamp: May 17, 2019, 09:46:35 pm
content: Quote from: ddavidebor on May 17, 2019, 08:12:02 pmIt doesn't require EMI testing and it's a simple 2 layer board. I can see people are at quite a large disagreement. Some say decoupling isn't even required and some say it's not done enough / properly. I guess I have to test it by removing the caps and checking with the scope to see the differences?

author: thm_w
author_rank: Super Contributor
timestamp: May 17, 2019, 10:04:27 pm
content: Quote from: OM222O on May 17, 2019, 09:46:35 pmIt depends on the design and the requirements. A schematic or board photo might help a bit (it seems hard to see a case where you can't fit in one 0603 per IC).But your plan is a good one, measure, remove the capacitor, measure again.https://www.electronicdesign.com/boards/whats-all-muntzing-stuff-anyhow

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 17, 2019, 10:07:24 pm
content: Quote from: Zero999 on May 17, 2019, 08:02:09 pmThere is AC in the circuit whether you intend there to be or not!Run that from some longer cable for example, and the opamp is likely to oscillate. Dynamics exist whether there is an apparent (large scale) signal present or not! Thermal noise is sufficient to push a system over the edge from an initial resting position (which may accidentally be an unstable point).This, incidentally, is why it's often hard to get SPICE oscillators to start. There's no noise unless you've specifically placed noise sources. And even so, if the amplitude is below the tolerance settings, it may simply be ignored and smoothed over.And so, this is the other intent behind good decoupling -- to isolate the on-board network from the outside world. And to do this, resistance is necessary. That is why we dampen or "swamp" resonances with ESR, and often it's as simple as a 100uF electrolytic somewhere.Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 17, 2019, 10:15:29 pm
content: Quote from: OwO on May 17, 2019, 05:12:08 amHow does the absolute distance come into this?QuoteStitching?Oh, you mean bypass caps, to serve the same purpose as stitching vias in a multi-layer-ground design*? Yeah.*Which, for those that don't know, is the typical 2-layer approach. Pour ground, route everything else (including supplies), stitch grounds frequently.Most extreme example of that I've seen, think it was a Sun server, the CPU module. Absolutely fucking plastered with caps, from the VRM to the CPU. The CPU also had a lot of ceramic LGA caps on itself, as well. The effect is to make a mixed distributed-lumped transmission line with an extremely low impedance.Have to wonder if theyreallyneeded all that, or if they just didn't give a shit as far as analyzing the PDN onboard the chip itself, and hacks like phasing different regions, or what. It's my understanding, modern chips get by just fine with onboard networks, so that the external circuit only has to deliver modest changes (bandwidth in the upper 10s of MHz), and all the scary high frequency stuff is handled on die, and on the interposer. Surely the same approaches would've been applicable, but they probably didn't think it would be worth the time to analyze, considering the low quantity and massive sale price of those beasts.Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 17, 2019, 10:23:13 pm
content: Quote from: imo on May 17, 2019, 08:23:03 pmHeh.. I would dare say size is a counter indication to competence (the Peter Principle). With a low correlation, mind. Did a job with a large electrical supplier: after spending several years working on this project, their power supply still blew emissions by a huge margin. The board was basically Swiss cheese, no planes whatsoever, ground was a cluster. I tore up existing routing, optimized component placement, put in two solid planes, and reduced emissions by >20dB (depending on frequency range in question).Tim

author: Zero999
author_rank: Super Contributor
timestamp: May 17, 2019, 10:55:57 pm
content: Quote from: T3sl4co1l on May 17, 2019, 10:07:24 pmI can see your point, but it would have to be really bad for that circuit to oscillate. The construction wasn't perfect: stripboard with a 200mm twisted pair power cable and it worked perfectly.Look at lots of really old analogue circuits, note that decoupling is either scant or non-existent and they worked perfectly well. It's only become really important since digital circuits which draw high current spikes became popular. Even the old 4000 CMOS logic is normally fins with no or very little decoupling. Just put a 100nF or so on the output of the regulator and all will be well.

author: ogden
author_rank: Super Contributor
timestamp: May 17, 2019, 11:01:27 pm
content: Quote from: T3sl4co1l on May 17, 2019, 10:23:13 pmNah. Small companies have incompetent engineers as well, they just do not last long - either incompetent engineer in small company or small company riddled with incompetence. That's why you see mostly competent engineers in small companies

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 17, 2019, 11:24:07 pm
content: Quote from: ogden on May 17, 2019, 11:01:27 pmYeah; to put more nuance on it, I would suppose you could plot competence vs. company size and get a scattered mess, where there is a large variance at the low end and a smaller variance at the high end, with the general trend overall as described.Tim

author: OwO
author_rank: Super Contributor
timestamp: May 18, 2019, 02:11:00 am
content: Quote from: T3sl4co1l on May 17, 2019, 10:15:29 pmDistance between power and ground plane determines the impedance seen at a given point between the two planes that isn't very close to a decoupling cap. The simulation tool linked by schratterulrich should be able to show this.Onchip decoupling is the reason chips still work at all considering the huge bondwire inductance and the interposer wire length (for BGAs), so usually it's not critical to get down to the last mm of distance between cap and pins, hence why caps at the bottom side of the board is just as good for high speed designs (Zynq) without needing a power/gnd plane pair.

author: OM222O
author_rank: Frequent Contributor
timestamp: May 18, 2019, 04:17:31 am
content: Tim if you want an example for overkill decoupling, look at the 2080 Ti kingpin PCB:they just went to town with ceramic caps for the VRM since the pick and place was going to take care of it.

author: floobydust
author_rank: Super Contributor
timestamp: May 18, 2019, 05:09:57 am
content: Decoupling capacitors were explained in university, based on TTL gates switching and DIP packages and short PCB traces to a through-hole capacitor.TTL totem-pole shoot-through current was the main issue, and based on total inductances of the capacitor, pcb traces, DIP package, around 0.01uF was enough to stop glitches on 5V rail. Using 0.1uF was 10x needed and afforded extra insurance for larger parts like SRAM and became common practice.But on cell-phone modules +4V rail I see multiple staggered values like 10pF, 33pF, 100pF, 1nF, 10nF, 100uF on factory datasheets. TX currents to 1A on 800-1900MHz up, I guess the SRF of each decoupling capacitor needs to overlap.iPhones are well engineered this way too, check some of their schematics.

author: schratterulrich
author_rank: Regular Contributor
timestamp: May 18, 2019, 07:58:43 am
content: For critical projects we don't use 100nF caps at every IC anymore in our company. Instead we use very thin core and prepreg material with a thickness of 50µm for every power rail. The disadvantage is that we usually need 12 to 16 layers. Then we place capacitor groups around the board evenly distributed. Due to the thin core material and the very low inductance of the resulting plane pairs the caps don't need to be placed ACAP to the ICs. The values of the capacitors have to be determined with a simulation.We have very good experience with EMC and ESD with this approach.Also the routing is easier especially because we need the space around the ICs mostly for series termination resistors.Of course for boards with lower layer counts we still use conventional decoupling caps at every IC and I would strongly recommend them.It is difficult to test your design for all conditions even if it works in the lab.

author: rstofer
author_rank: Super Contributor
timestamp: May 18, 2019, 04:24:02 pm
content: Quote from: OM222O on May 17, 2019, 12:12:11 amI2C pins are open collector or open drain. Section 3.1.1 here:https://www.nxp.com/docs/en/user-guide/UM10204.pdfWhat is providing the pull-up for your test? Something is doing it and shouldn't be.

author: ataradov
author_rank: Super Contributor
timestamp: May 18, 2019, 04:53:23 pm
content: Quote from: rstofer on May 18, 2019, 04:24:02 pmHe already replied - internal pull-ups of the MCU. And they do work fine for short traces in my experience too, even though they are typically an order of magnitude higher than recommended.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 18, 2019, 08:22:58 pm
content: Quote from: OwO on May 18, 2019, 02:11:00 amAh, but that's the third variable: distance!Inductance is always proportional to a volume ratio length. Or whatever it's called. To get the resistance of a solid, you take resistivity and divide by (cross-sectional area divided by longitudinal length). Same with inductance, where the area is that of the transmission line cross section (with a geometry factor of course), and the length is the length of the line.If we consider the inductance of a via into a plane, we can look at the inductance of a cylindrical cavity resonator, where the height is very short (so we can ignore edge effects), the inner radius is the diameter of the via, and the outer diameter is an arbitrary boundary. The boundary might be a wall of nearby vias (which again, for the power planes case, are vias to bypass caps), or the edge of the board (in which case the inductance acts in series with the plane capacitance, and we have a series resonance -- this is the lumped equivalent of the first standing wave mode between the planes), or to infinity if we wish to look at the asymptotic case.We use a cylindrical model, because we're looking at waves propagating from the via radially. Of course, if we have vias placed in this plane in arbitrary locations, their radial "fields of view" will overlap, and for example the inductance between two vias will be approximately the sum of both inductances, when outer diameter = distance/2, but there will be some mutual inductance between them as well (where outer diameter > distance/2), so we could draw a more detailed diagram accordingly.When the problem is set up as such, and the integral is solved, we get a logarithmic result:L = k * mu * h * ln(D/d)(I forget exactly if there is a constant of proportionality there; it may be k = 1, and also mu = mu_r * mu_0 but we can just use mu_0 for PCB because mu_r = 1...)Putting in typical values, we expect figures close to the usual via inductance figure itself, and since it varies logarithmically with D, we aren't so worried about how far away things are, beyond some point. We do get some advantage when a capacitor can be placed at a distance less than h away from the via (on same layer), but if not (or when not required), the added inductance of the plane to other nodes is quite small.Take for example mu = 1.257 nH/mm, h = 1mm, D = 20mm and d = 0.3mm. The log is 4.2, so it's like having a 4.2mm tall via, and L = 5.3nH. Not much, comparable to a few mm of trace length!I would be quite happy doing this for an MCU, which might draw a rate of 100mA/5ns (say by toggling a full port of LEDs). Times 5.3nH, this is a peak voltage (at internal VCC) of only 106mV, a few percent out of a 3.3V supply. And indeed, I do this regularly, and the MCU has never shown aberrant behavior.We can also consider a ring of vias, or any arbitrary clustering of vias with an equivalent diameter of d, and apply this formula. (Or use this formula in reverse to solve for the equivalent diameter of that pattern, given another calculation or measurement of the inductance.) This of course demonstrates why multiple vias are valuable (a circle of vias of say d = 2mm in the same setting gives about half the inductance in the same case).Regarding mutual inductances -- crafting a lumped equivalent of a distributed structure (following a transcendental function, at that) would be very tough, so if we need detail quite on that level, we might as well just break it up into a grid and approximate it that way; hence, the analysis program above, of course.Tim

author: NorthGuy
author_rank: Super Contributor
timestamp: May 19, 2019, 04:13:32 am
content: Quote from: OM222O on May 18, 2019, 04:17:31 amIf you have millions of FETs simultaneously switching at tremendous speed, you do need lots of capacitors. And they have to be very fast and therefore small. Thus it's really hard to gather enough capacitance.

author: DaJMasta
author_rank: Super Contributor
timestamp: May 19, 2019, 07:43:14 am
content: Quote from: NorthGuy on May 19, 2019, 04:13:32 amIt's also a model that's advertised for overclocking, so they guild the lily with decoupling caps and VRM phases with the hopes that overdoing it will help keep things stable above normal clocks. They know that people who are spending for the top card with the intention of overclocking will buy based on good results they hear about, so if they can go the extra mile in their design to overcome potential overclocking limitations with a dollar of extra caps and pick and place time, it's definitely in their interest.

author: LukeW
author_rank: Frequent Contributor
timestamp: May 19, 2019, 08:27:54 am
content: A picture of your layout would be more significant than the schematic.It's all about minimising the parasitic inductance, and getting those decoupling capacitors as close as possible to the loop on the IC where the current is actually going."Electromagnetic Compatibility Engineering" (H.W Ott) has a great treatment of decoupling capacitors.

author: LukeW
author_rank: Frequent Contributor
timestamp: May 19, 2019, 08:32:42 am
content: http://www.hottconsultants.com/pdf_files/Keynote.pdf