Double precision DAC - Page 1
Forum section: electronics / projects

author: mtkaalund
author_rank: Contributor
timestamp: June 20, 2012, 01:46:04 pm
content: HeySo I was going trough the MCP4706 datasheethttp://ww1.microchip.com/downloads/en/DeviceDoc/22272C.pdfpage 68 (8.6), there is a design for using two DAC, to up the bit count of the DAC.Now I would like to hear I there is someboby that has tried this? If so, did you get the DACa + DACb precision?Is there a problem with using this design?Thanks for aswering

author: digsys
author_rank: Unknown
timestamp: June 20, 2012, 02:27:09 pm
content: It's an common "trick". One DAC is set up as X1, while the other /100 /256 or whatever, then you SUM them.The only Drawback (if you can call it that) is - your program needs to run extra calcs to work out the finalvoltage, then load each DAC sequentially. That also means there'll be a slight glitch in the output betweenthe 1st and 2nd DAC load. For 2x 10bit DACs (1024), that means a <0.1% potential glitch.Rather than making a 10/20 or 12/24 bit DAC, another option is to say - (for 10bits) make one 5.00V/1024= ~ 5mV res, and the second as a /10 /20 trim. Depending on your use - 24bits may be well into noise floor.

author: Stephen Hill
author_rank: Regular Contributor
timestamp: June 20, 2012, 02:33:39 pm
content: If you wanted to avoid the time delay glitch, could you could use a DAC with a parallel interface?

author: free_electron
author_rank: Super Contributor
timestamp: June 20, 2012, 02:45:04 pm
content: use current mode output dacs.you can just sum the currents ( tie the pins together )

author: Stephen Hill
author_rank: Regular Contributor
timestamp: June 20, 2012, 02:46:27 pm
content: You might also want to consider a MCP4921/4922. It's a dual 12bit DAC with SPI interface but the output is controlled by the LDAC pin. This allows you to set the input registers for both DACs and then set the LDAC pin low to change the outputs at the same time.

author: digsys
author_rank: Unknown
timestamp: June 20, 2012, 02:50:02 pm
content: Quote from: Stephen Hill on June 20, 2012, 02:33:39 pmYou STILL may have a "glitch" problem, as you load 2-3 output ports. IF the DAC has an update enable pin,then you're OK. OR you can can put a sort of sample and hold on the summing amp ie enable output.Many serial DACs (and parallel ones too) actually do have "load" / "update" pins or registers.Something to watch for.

author: A Hellene
author_rank: Frequent Contributor
timestamp: June 20, 2012, 05:08:23 pm
content: Do you mean, mtkaalund, that you can combine two LADA to compete with a Porsche?No, it cannot happen; especially when usingbufferedvoltage DACs that have lousy accuracy at both the low and the high ends of their code scale: This particular DAC's INL and DNL errors are not even stated for any input codes between 0.0%..2.5% and 97.5%..100% of FSR. Even if there was not such a problem (by using accurate and unbuffered voltage DACs), you would also need a resistor divider of a better than 17-bit accuracy (0.000763% or 7.63ppm!) in order tocombine the outputsof twoaccurate8-bit DACs into a 16-bit result without anymissing codes.If you want to experiment, it is alright to try. But if you need anaccurate16-DAC, why not just look at what solutions theserious manufacturershave to offer?-George

author: mtkaalund
author_rank: Contributor
timestamp: June 20, 2012, 08:54:07 pm
content: First thanks for all the answers,Quote from: A Hellene on June 20, 2012, 05:08:23 pmNot really, I was just wondering about this design. An if it was something worth to remember, but as I can deduce from the replies that the only thing worth to remember about this design, is you could use it as an trim, and you can not improve on the output precision.But again many thanks for the replies.

author: nctnico
author_rank: Super Contributor
timestamp: June 21, 2012, 12:21:04 am
content: Quote from: digsys on June 20, 2012, 02:27:09 pmIt won't work. DACs and ADCs usually have an error well beyond one LSB. All of the secondary DAC/ADC's accuracy is lost in the error of the primary DAC/ADC. There is a good reason ADCs / DACs get more expensive with increasing accuracy.

author: digsys
author_rank: Unknown
timestamp: June 21, 2012, 01:05:09 am
content: QuotePretty raw presentation. Let's break this down -As EEs, we all know about accuracy / temperature / span / drift errors. Generally a DAC is part of a feedback loop, so generally an ADC ismonitoring the output ... or maybe it's just visual, whatever. IF I add +1 STEP to my DAC, I will see +1 step output. Sure, it maybe 1-2+%span error, or 5% absolute error, BUT it will STEP the output. IF my primary DAC can only produce OUTPUT steps of SAY 1.00V for therange I need, then I HAVE to use a second DAC for FINE TRIM. Again, EVERY time I add +1 bit, I will see +1 step output, it's the law :-)My feedback circuit will sort out accuracy errors, IF required. I don't think the OP is making a 1GHz sampling scope.YES, I can sell my liver and buy a higher precision DAC, but that's NOT what the OP asked.So, the basic rule is ... I put in +1 bit, I get out +1 step, otherwise it'd (the DAC) be called a DORK or something.

author: EEVblog
author_rank: Unknown
timestamp: June 21, 2012, 01:15:19 am
content: Quote from: mtkaalund on June 20, 2012, 01:46:04 pm"precision", as in accuracy, no.Resolution, yes, it's possible, in theory. Whether or not it's worthwhile depends entirely upon the application.In practice I would think it would hardly ever be worthwhile dicking around trying to do it.Dave.

author: Rufus
author_rank: Super Contributor
timestamp: June 21, 2012, 01:55:36 am
content: Quote from: digsys on June 21, 2012, 01:05:09 amIt isn't a rule. That each input bit always makes the output go in at least the right direction is a quality of monotonic DACs and if all DACs were monotonic there wouldn't need to be a name for it.

author: Bored@Work
author_rank: Super Contributor
timestamp: June 21, 2012, 05:17:35 am
content: Monotonic DACs are prety much the norm these days. It is a bit funny when manufacturers still feel the need to mention the feature.The combination of two DACs is not new. Think of it as a combination of a pot for coarse and a second one for fine adjustment. Like you set a baseline with the coarse DAC, and then trim with the fine DAC.That doesn't make a combination of two 12 bit DACs a good 24 bit DAC as such. You get all the problems of a 24 bit DAC, plus the problems coming from combining two not exactly matching DACs, which you can't control at the same time.As for designing such a system, the datasheet has it the wrong way around. They start with the coarse part and then scale the same setup down ("pull 1/1000 down" as they call it) for the fine part. But the key to get such a combination working is to start to get the fine adjustment DAC right with respect to the properties you need (accuracy, drift, noise, etc.). Then throwing in the coarse DAC is trivial. You can trim the coarse DAC with the fine DAC, but you can't do it the other way around, so the fine DAC part first and foremost needs to deliver what you need.Also, they should have done things like connecting both DACs to on single reference, to make sure both DACs have the same relative temperature drift.Like with all datasheets, the datasheet tries to sell you more parts, not necessarily showing you the best solution.

author: ejeffrey
author_rank: Super Contributor
timestamp: June 21, 2012, 07:25:35 am
content: It is not necessary to specify monotonicity in any case, as the DNL tells you that and more.Using a coarse/fine DAC like this is going to be highly application dependent. Some applications may be well served by such a configuration, others may have substantial trouble. When in doubt, I would see if I could use a natively high resolution sigma-delta DAC where the manufacturer has taken care of the issues. If I were being super cheap and needed a high resolution setpoint but didn't need brilliant accuracy or settling time I would even consider a home-brew sigma-delta converter using a microcontroller PWM pin and a logic gate buffer.To get acceptable performance out of this configuration you need to calibrate the coarse DAC. They mention the using the fine DAC to compensate for the coarse DACs DNL, but they don't elaborate, and then give a transfer function that is uncalibrated. The worst case DNL of the 12 bit DAC is 0.75 bit. With a 1000:1 ratio, the total DNL would be 750 LSB (when the fine DAC rolls over). I can't think of any application where that would be acceptable. So you need some overlap -- the fine DAC has a range of a few LSB of the coarse DAC. If you have a lookup table for the actual output values of the coarse DAC, you can then compute the necessary value of the fine DAC to generate the requested output voltage. You can do this, but this is the point where you have to start asking very pointed questions about whether this is worth it.Another potential trap is the output noise. I don't even see an output noise specification for the built-in voltage buffer. Again, you will see the full output noise of the coarse DAC superimposed on the fine DAC output, but in this case you can't calibrate it out. The most concerning thing to me would be the low frequency noise. If the buffer has a 0.1-10 Hz noise of 10 uV, the value of a 1 uV setpoint resolution is debatable.

author: Rufus
author_rank: Super Contributor
timestamp: June 23, 2012, 01:59:10 am
content: Quote from: ejeffrey on June 21, 2012, 07:25:35 amDNL doesn't tell you that. DNL of less than one tells you it is monotonic, greater than one doesn't tell you either way.

author: nctnico
author_rank: Super Contributor
timestamp: June 23, 2012, 03:33:28 pm
content: Quote from: ejeffrey on June 21, 2012, 07:25:35 amWhich takes me back to my point: chips are designed to meet their spec and nothing more! So an 8 bit DAC's noise 'suppression' will be sufficient to meet 8 bit resolution.

author: ejeffrey
author_rank: Super Contributor
timestamp: June 23, 2012, 07:52:20 pm
content: Quote from: Rufus on June 23, 2012, 01:59:10 amA DNL more negative than -1 == non-monotonic. If the DNL is asymmetric it should be specified as e.g., +1.5/-0.5.

author: codeboy2k
author_rank: Super Contributor
timestamp: June 23, 2012, 10:58:09 pm
content: Quote from: ejeffrey on June 23, 2012, 07:52:20 pmthe problem here is that no one is fully specifying what they mean.if |DNL| <= 1 then the device is most certainly monotonic. I think this is what Rufus was referring to.if |DNL| > 1 then it doesn't tell you either way, and you have to look more closely.^^^ absolute value herein the case of asymmetries, then as ejeffrey says, it should be specified, as eg. +1.5/-0.5if the negative DNL < -1 , then it is non-monotonic.if the negative DNL is >= -1, then it is monotonic.if the positive DNL > 1, then it is still monotonic, but not-desirable.So ejeffrey's example is monotonic, but has at least one step that is more than 1 LSB, and this is thus not desirable in a DAC.a DNL specified as +0.6/-1.2 would be non-monotonic.a DNL as +0.5/-0.3 is monotonic.Often a manufacturer will specify the DNL as simply 1 LSB or ±1 LSB.In the first case you can assume they mean |DNL| = 1 LSB and therefore it is monotonic, and in the second case it's clear that they mean +1/-1 LSB, which is also the same as |DNL| = 1, therefore it is also monotonic.