GPSDO question - Page 1
Forum section: electronics / projects

author: brian_mk
author_rank: Regular Contributor
timestamp: May 22, 2023, 04:57:36 pm
content: I bought a used Racal 1998 counter (eBay of course).It has the OCXO option. I'd like to check/calibrate it.I am a retired engineer / hobbyist with a very limited budget.The counter has 9 digits, so it would be nice to check if the least sig digit is accurate.For example: 10,000,000.0 Hz to within +/- 0.1Hz. i.e about 1 in 10^8.Is that too ambitious?Naturally I started investigating GPSDOs.I could buy a Chinese one on eBay for about £150.Then I thought it might be an interesting project to try and construct something.There are a lot of designs and ideas on the internet.Some are more than I need / too complex / too expensive / too time consuming.I am not a time nut looking for ultimate precision.I don't really want to spend a lot of time / effort / expense with complex designs involving uPs & software.I have a GPS receiver with a Neo-6M salvaged from a crashed drone I found in a hedge :-)It still works and produces a 1PPM signal, so I figure I should be able to make use of it.I found this easy to understand semi-digital/semi-analogue design:-http://techlib.com/electronics/GPSstandard.htmMy questions to the experts..."Would this design meet my requirements?""Are there any obvious limitations / problems I should be aware of?"One concern is the analogue loop filter that uses a 66M Ohm resistor. Surely not good in humid conditions?

author: Gyro
author_rank: Super Contributor
timestamp: May 22, 2023, 09:54:55 pm
content: 10^8 isn't unrealistic. It's a bit close to bed time to go into detail, but irrc, with a USB serial adaptor and the appropriate S/W from the u-blox site, it's possible to set the timepulse output to anywhere between 0.25Hz and 10MHz.It won't be as stable as a full GPSDO, but should be sufficient for your accuracy needs. Note that any frequency that isn't a sub-multople for the internal 64MHz module clock will have jitter, so it is best set to 8MHz output. In practice though, I have found that the gate time of the frequency counter is sufficient to give a stable reading at 10MHz too.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: May 23, 2023, 05:38:54 am
content: Quote from: brian_mk on May 22, 2023, 04:57:36 pmA quick, simple check should be to simply measure the 1pps, any decent counter should be able to report that to 8-9 digits as Frequency and Period.As mentioned above, if you have the right GPS module, you can redefine the GPS 1pps with the right connection and SW, and it will give you an averaged correct value up to MHz.10MHz has some jitter from the 48MHz? GPS locked clock, but you will get exactly 5 cycles in 500ns, derived from exactly 24 cycles.I find thisQuoteA PLL can average that, and I saw one design where a user applied a 10MHz crystal as a very high Q ringing filter, which makes scope checks easier.There is also a lot here...https://www.eevblog.com/forum/projects/yet-another-diy-gpsdo-yes-another-one/and this approach throws different hardware at the problem, using a 10Mhz divider and leaving the 1pps untouched.https://www.edn.com/simple-gps-disciplined-10mhz-reference-uses-dual-pwms/The Author uses an external 74LV8154 32b counter, that needs many pins connected, but it does manage the 10MHz division externally to the MCU

author: brian_mk
author_rank: Regular Contributor
timestamp: May 23, 2023, 09:04:10 am
content: Quote from: Gyro on May 22, 2023, 09:54:55 pmUnfortunately the Neo-6M that I have only allows the Timepulse to be configured between 0.25Hz and 1kHz. The Neo-6T allows it to be set up to 10MHz.That means either using a phase detector at the default 1PPS or configuring the Timepulse output to 800Hz.If the Neo-6M uses a 48MHz clock, 800Hz is the highest frequency that is an integer sub multiple for optimum jitter performance.Strangely though, the link below indicates the Neo-6M uses a 26MHz crystal?https://portal.u-blox.com/s/question/0D52p00008HKDu7CAH/find-frequency-at-which-ublox-neo6m-is-working-atAnyway, the design in the link I gave in my original post uses the default 100ms wide 1PPS output.It generates a 1uS wide pulse from the 1PPS signal using a monostable. The 1us pulse is used to sample a 1MHz signal obtained by dividing the 10MHz OCXO by ten.The result is a voltage proportional to the phase difference between the OCXO and the 1PPS.This voltage is fed through an analogue active filter with a long time constant to the OCXO tuning control.It seems quite a neat and simple idea.I am wondering what the limitations might be.BTW I already have some of the cheap, ex-equipment Chinese CTI OSC5A2B02 10MHz OCXOs.They use a 5V supply, 0->4V control voltage and output a square wave with 74HC logic levels.I think they would fit in well with the design above.

author: Gyro
author_rank: Super Contributor
timestamp: May 23, 2023, 09:31:39 am
content: Quote from: brian_mk on May 22, 2023, 04:57:36 pmNow that I'm awake... I understand your desire not to get into uPs etc, even if they may lead to an overall more compact or long term stable design with holdover etc.Also being a retired engineer with limited budget, I put together a really simple GPSDO breadboard design using a basic PLL, a cheap OCXO, and an LEA-6T. These specific 6T boards were being sold really cheaply on ebay at the time for drone use (which I never did understand). The LEA-6T is specifically designed for timing purposes, slightly different firmware, two timepulse outputs rather than just the one, and, (I think) a 64MHz TCXO rather than VCXO. As I mentioned in my previous post, I was able to calibrate my counter (a Philips PM6622) with stable results just using one of the timepulse outputs of the module. My motivation for the GPSDO was really to get a nice stable jitter-free 10MHz output, and just for the hell of it. It's still a breadboard, but Idointend to finisjh it some day.I started two threads, one on the LEA-6T board, which will probably be at least of some use for the LEA-6M too, and a second thread detailing my PLL based GPSDO breadboard. The PC based configuration software that I used was u-center, available from the u-blox website.https://www.eevblog.com/forum/projects/ebay-u-blox-lea-6t-gps-module-teardown-and-initial-test/https://www.eevblog.com/forum/projects/my-u-blox-lea-6t-based-gpsdo-(very-scruffy-initial-breadboard-stage)/As far as I could establish, the GPSDO was achieving probable a couple of orders of magnitude better than the 1e-8 that you are looking for. I'm not really a metrologist either, I just wanted something 'good enough' and simple to tinker with.If you're looking for something ready made, I also suggest one of Leo Bodnar's (forum member). Programmable frequency GPSDO units...https://www.leobodnar.com/shop/. He's also in the UK.EDIT: I've just seen your above post. It's a shame the timepulse on the 6M can't be set higher. I think you would be ok with 1kHz (the high divide ratio, compared to 10MHz, would eliminate jitter). Obviously you would need a higher divide ratio from the OCXO and to play with the PLL filter.I know it's uP in the general sense, but you may want to look at a picDIV for the divider (PD4 would fit the bill)...http://www.leapsecond.com/pic/picdiv.htm. Otherwise, a (preferably synchronous) divider chain.

author: WatchfulEye
author_rank: Regular Contributor
timestamp: May 23, 2023, 10:49:26 am
content: If you set the time pulse frequency of the GPS receiver to something in the measurement range of the counter (eg. 100 Hz) and use a gate time of 20 seconds, then that should be sufficient to achieve 1e-8 accuracy. No additional hardware needed.GPS receivers have quite a lot of jitter in the time pulse due to the internal clock, and also GPS solution errors. A gate time sufficient to average this out is a good idea.

author: Gyro
author_rank: Super Contributor
timestamp: May 23, 2023, 12:37:04 pm
content: Quote from: WatchfulEye on May 23, 2023, 10:49:26 amAgreed. Calibrating to that sort of accuracy isn't the demanding requirement that it once was. GPS changed everything in terms of frequency reference traceablility. Pick a USB-Serial adapter that has the appropriate selectable output voltage and you can power the module from USB too.

author: S57UUU
author_rank: Regular Contributor
timestamp: May 23, 2023, 02:57:43 pm
content: If your GPS can output 1kHz, it should be easy to make a simple PLL for a 10MHz crystal. For example, 2X 74HC390 + 74HC4046. Such an analog loop will be too fast to be a "flywheel", and will track all of the GPS errors, but 8 digits should be easy and 9 may be achievable.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: May 23, 2023, 08:25:01 pm
content: Quote from: brian_mk on May 23, 2023, 09:04:10 am1000Hz is still an integer divider ? /60000 0r /48000 ?Quote from: brian_mk on May 23, 2023, 09:04:10 amYes, that is then locked again inside their MCU.I did see one design where they took the trouble to lock that 26MHz, which must reduce the additional corrections needed, but that involved hacking into the GPS module.Quote from: brian_mk on May 23, 2023, 09:04:10 amIt is neat and simple, the main limitation is the 'long time constant' needs to be very long for a 1us impulse every second, so the testing and parts are less friendly.If you have 1us sample windows and 1s waits, a that's 1M:1 leakage/noise to information ration.Even 1kHz helps improve that to 1000:1You may want to seek alow leakageanalog switch for the PLL aperture sampler.Addit: nailing down leakage does not seem easy, It is highly temperature dependent and they only worry about logic-level testers.I did find thishttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/854115/sn74lvc1g3157-input-leakage-currentand this seems to define low leakagehttps://datasheet.lcsc.com/lcsc/1912111437_DIOO-DIO3157ESC6_C444615.pdfand this DIO3166 is single channelhttps://www.dioo.com/diooAdmin/api/upload/img/1679364769894.pdfI wonder if the older 15V CMOS is lower leakage ? I did find a SOT25 version of a single gate CD4066 : ROHM BU4S66G2 and Toshiba TC4S66FTheir /10 design to 1MHz could also help you compare two GPS, one with a 10MHz setting and one with 1pps, as /5 or above removes the 48M:10M edge placement jitter.Quote from: brian_mk on May 23, 2023, 09:04:10 amYes.

author: MIS42N
author_rank: Frequent Contributor
timestamp: May 23, 2023, 11:52:10 pm
content: For 1 part in 10^8 the GPS module (Neo-6M) output is fine, no GPSDO required. Just make a few measurements and average. If this is an infrequent calibration then it is not worth going down the GPSDO route.A problem with most GPSDOs is it is difficult to know how accurate they are. If the GPS module is relying on minimal signal its output can instantaneously wander quite a bit. Phase locked loop designs may follow this faithfully or average fluctuations out. It is a compromise between getting a quick lock and getting a stable output. If the GPSDO gives access to the NMEA messages from the GPS module then at least the quality of the GPS signal can be determined and infer the GPSDO is accurate. An accuracy better than 1 part in 10^9 is usual but not guaranteed.I produced a basic microprocessor based design a few years agohttps://www.eevblog.com/forum/projects/budget-gpsdo-a-work-in-progress/the first version running from a 5V wall wart used two ICs (PIC16F1455 and 74HC04) and an OSC5A2B02 OCXO. It is self checking so it indicates if it is running within specification (1 part in 10^9) so gives some confidence when using the output. Although microprocessor designs involve software they can be much more informative than other designs and reduce the component count. Excluding the wall wart (which could be a surplus phone charger) and the GPS module the parts are about $20AU (less in $US).With some modification the same design wrapped in better power supplies and good GPS signals has proven to be good for accuracy of 4 parts in 10^11 (as measured by its self check feature). I have been thinking of some modifications to the PCB to drive this down further (some poor design on my part).

author: brian_mk
author_rank: Regular Contributor
timestamp: May 24, 2023, 02:10:07 pm
content: Quote from: PCB.Wiz on May 23, 2023, 08:25:01 pmAgreed - leakage was one of my concerns - both in the sampling gate and in the analogue filter.To get a long time constant, the filter uses a 66Meg resistor (actually 3x 33Meg). It would only need a small amount of moisture/dirt to throw it way out.The PCB would need slots and guard rings to try and minimise the effects.It did occur to me that if the Timepulse were changed from 1PPS to 1kHz, the design should still work without any changes.It would mean that the 1MHz signal is sampled once per millisecond rather than once per second. That would greatly reduce the effect of leakage in the sampling gate.In this case though, does the design offer any advantage over a standard 'exclusive OR' phase detector?BTW: The analogue filter circuit used is unusual.The text describes it as a 'third order filter' but it looks different to any third order LPF single op amp designs that I have seen.I have been unable to find information on how to calculate the R & C component values for a given cut off frequency.I tried simulating it in LTSpice but the results look rather odd.

author: S57UUU
author_rank: Regular Contributor
timestamp: May 24, 2023, 02:16:09 pm
content: Yes, 26000000 Hz / 1000Hz = 26000, so it will be a nice symmetric square wave.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: May 24, 2023, 08:30:27 pm
content: Quote from: brian_mk on May 24, 2023, 02:10:07 pmThe xor needs 50% duty cycle and equal frequencies on each pin.I'd choose a 7474 with schmitt pins.Quote from: brian_mk on May 24, 2023, 02:10:07 pmI'd call it second order, with differing corners.The first LPF is 10k+10k+100p, which appears fast, but that is sampled 1:1M, so actually has a time constant of ~2s, the second stage has time constant of ~31sWith the faster update PFD frequency, you could speed up those filters a little, but a long filter time does help to average things.

author: brian_mk
author_rank: Regular Contributor
timestamp: May 25, 2023, 09:30:08 am
content: Does anyone know what happens to the pulse width of the Neo-6M Timepulse signal if the frequency is re-configured?At the default 1PPS, the pulse width is 100ms.I am guessing that the pulse width is fixed for very low frequencies but changes to a 1:1 mark space ratio square wave above 10Hz?Edit: I just discovered this post from "Johnny B Good" in another thread...https://www.eevblog.com/forum/metrology/what-do-you-want-from-a-gpsdo/100/===="I mention this on account this new found interest in test and measurement kit has set me off on a seemingly never ending quest for better and more accurate gear, aka a GPSDO I can rely on and be proud of. Lately, in earlier postings here, I've been bemoaning my problems with getting a 5 volt 13MHz OCXO to phase lock against my cheap NEO-6M's 1kHz PPS (it's a make do for now substitute for the original M8N module I damaged with an injection of 12 volts into its PPS line a couple of weeks back).All this time I'd been blaming first the XOR gate phase detector circuit and then the 4046 phase detectors for not doing 'their job' and, only now between this and the previous post, discovered a rather strange fact about the PPS signal from a NEO-6M (or at least this NEO-6M) when it's programmed to output a 1ms second pulse with a 50% duty cycle (1KHz sq wave).Up until just prior to this post, I'd only ever quickly checked out the PPS and divider chain 1KHz output waveforms, preferring to monitor the 13MHz OCXO and FY6600 outputs when testing my crude PLL setup. It's only since I decided to take a much closer look in detail at the 1KHz signals going into the 4046's phase detectors, whilst monitoring the output voltage, that I've finally discovered the root cause of my crudely lashed up on prototyping bread board GPSDO test setup's failure to lock onto the GPS reference. It turns out to have been all to do with the NEO-6M's strange habit of slowly wittling away at the positive going pulse, shrinking its width until it disappears up its own backside to instantly reincarnate itself as a full fat sq wave, remaining so for the following five or so minutes before starting another cycle of shrinkage over the next 5 or so minutes.If it hadn't been for the fact that I'd upgraded the FY6600 to an OCXO clock, I doubt I'd have been able to hand adjust the tuning pot on the OCXO to keep it close enough to the leading edge of the 1KHz PPS pulse to observe such weirdness (I'm not sure the original 0.1ppm 50MHz TCXO upgrade would have been enough of an improvement to have pulled off such a stunt).It's no wonder the XOR gate failed to produce any meaningful failure behaviour let alone actually function as intended other than for relatively brief moments when it seemed to be locking in an offset fashion. The type 2 phase detector in the 4046 should have gotten round the non-square waveform issue but I'm guessing it was triggering on the trailing falling edge which would have been slowly happening at earlier and earlier times in the cycle for half of this 10 or so minute cycle before jumping back to a sq waveform for another 5 or so minute round of fun and games. No wonder it was slowly driving me round the bend these past few evenings (including midnight to 5 or 6 in the am if truth be known).Anyway, that's just a taster of the sort of process that sucks you ever deeper into the mad mad world of DIY test gear and electronic projects in general. BTW, I think, now I've got the use of the type 2 phase detector in that 4046 which doesn't rely on the waves being square, I'll have a go at reprogramming the NEO-6M to generate the narrowest pulse possible (10 microsecond, afaicr) and see how it behaves at that setting."====It indicates the pulse width of the Timepulse is separately configurable to the frequency (as low as 10uS miniumum).However, from the report above, I am a concerned about how the mark-space ratio varies over time.

author: brian_mk
author_rank: Regular Contributor
timestamp: May 25, 2023, 05:33:46 pm
content: Today I tried changing the Timepulse config to give 1kHz with a 1uS pulse width. That worked as expected.However the change doesn't appear to be saved in non-volatile memory even though I configured u-center CFG to save in BBR and FLASHThe receiver board has a button cell that measures 1.8V and is connected to the Neo V_BCKP pin.The datasheet suggests that 1.8V should be sufficient to maintain the on-chip battery backed RAM.Am I missing something?Edit:My bad. I don't think I understood the u_center interface.I assumed that if the CFG setting includes 'BBR' it would automatically cause ALL future parameter changes to be saved in battery backed RAM.It appears you have to 'Send' the CFG setup AFTER changing a bunch of parameters in order to save them.After I did that, the Timepulse change remains after power cycling the device.Being able to set the Timepulse width to 1uS means that the monostable used to generate the sampling pulse for the 1MHz signal will not be needed.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: May 25, 2023, 08:57:19 pm
content: Quote from: brian_mk on May 25, 2023, 05:33:46 pmI think you meant 1.00us?Yes, that's a great setting idea for that specific circuit.(but it may not be fully GPS unit portable ?)You could scope the phase detector to check for strange wanderings, like those reported. Maybe try heating/cooling, in case it's some correction artifact.

author: brian_mk
author_rank: Regular Contributor
timestamp: May 25, 2023, 10:01:58 pm
content: Sorry I meant 1uS. I've edited and corrected the error.

author: brian_mk
author_rank: Regular Contributor
timestamp: July 27, 2023, 11:10:45 am
content: An update on the GPSDO project.I decided to construct a hand wired prototype before making a pcb. It took some time to build but it gave me a chance to check and try a few things.It's now basically working.I found that at least two of the five used OCXOs I bought require a tuning voltage of just over 3V to lock.I think they should be about 2V when new. I guess they have drifted with age. Not a real issue.One of the CMOS op amps I intended to use as a high impedance buffer in the sample and hold oscillated at HF for some unnown reason. I had to replace it with an alternative part.A bigger problem is that I found the small 3V rechargeable lithium cell on the Neo-6M module only lasts for a couple of weeks when not powered.It powers the Battery Backed Ram which contains clock data, latest position data and module configuration.I reconfigured the device to change the 1PPS timepulse to 1kHz. However when the battery voltage drops, the signal reverts back to 1PPS.The phase detector design can operate with a 1PPS signal but it means the loop filter needs a long time constant.It would be better if I could find a way to maintain the 1kHz setting.I have read that some people use a uP to configure the device over the serial link every time it powers up. That solution seems a bit over the top.I was wondering about replacing the button cell with a higher capacity rechargeable lithium battery that would last a few months.

author: MIS42N
author_rank: Frequent Contributor
timestamp: July 27, 2023, 12:14:11 pm
content: Quote from: brian_mk on May 25, 2023, 10:01:58 pmYou really mean 1µs - capital S stands for the SI unit siemens. The s for seconds is lower case.I didn't know this until pointed out to me.Capital letter units are named after people -https://en.wikipedia.org/wiki/List_of_scientists_whose_names_are_used_as_unitsAll the rest are small except the litre (international spelling) or liter (American English spelling) which can be L or l (I do not know why).Along the same lines, quantities a million or more are capitals, less are small. So k = kilo M = mega. This allows distinguishing mΩ from MΩ (milliohm and megohm).Very pedantic.

author: MIS42N
author_rank: Frequent Contributor
timestamp: July 27, 2023, 12:51:56 pm
content: Quote from: brian_mk on July 27, 2023, 11:10:45 amI think you are hooked.You said "I don't really want to spend a lot of time / effort / expense with complex designs involving uPs & software." but are well into spending a lot of time avoiding a µP.This is a quote from someone who built my GPSDO.Quote from: de_light on October 28, 2021, 11:06:27 amThat was the first version. It cost about $20AU minus GPS unit. I addressed the sensitivity issue in the second version. I sold some kits for the second version (including the GPS unit and active antenna but not a case or 12V supply) for $45AU - about £25It does not require a modification to the GPS unit. It is self calibrating (you build it, you run it for a few hours. Nothing to tune). It tells you on an LED if it is running out of spec (1 part in 10^9 or 0.01Hz) - something that you won't find in any other GPSDO at that price.Are you sure it's worth avoiding the µP solution?P.S. I sold all the version 2 kits and don't intend to create any more. The design is published in Silicon Chip magazine May 2023.

author: brian_mk
author_rank: Regular Contributor
timestamp: July 27, 2023, 03:36:48 pm
content: The project was partly an exercise to keep myself busy since retiring. It's just a hobby.There is only so much mindless daytime TV you can watch before you turn into a brain dead zombie.It's taken longer and cost more than I expected. I could probably have bought a ready built Chinese GPSDO more cheaply but where's the fun in that?I worked as an embedded software engineer for many years, so although I could do it, I'm no longer that keen on spending my time writing code these days.As for the 's' or 'S', my eyesight is now so bad I have trouble both reading and typing. I make so many embarassing typos these days.

author: MIS42N
author_rank: Frequent Contributor
timestamp: July 28, 2023, 04:15:37 am
content: Quote from: brian_mk on July 27, 2023, 03:36:48 pmAs I thought - hooked.I had no need of a GPSDO, just seemed an interesting challenge. Kept me away from that mindless daytime TV for a few years. Now I'm looking for the next challenge (which I think is house renovation - for something completely different).I was, and still am, keen to write assembler software. The PIC processor at the heart of the GPSDO uses all 3 timers, a comparator, interrupt on change, and its UART. It handles between 40,000 and 50,000 interrupts a second from many (I think 9, I'd have to look at the code) sources. The aim was to replace components with software. The clock for the processor comes from the 10MHz OCXO, and the 1pps from the GPS module goes direct to the processor also. No external phase detector. The control voltage for the OCXO is highly filtered dithered PWM (which accounts for 40,000 interrupts) for microvolt control, so no DAC.And of course using a processor allows lots of extras - self checking, status LED, user interface (optional) to monitor in detail what happens, a limited (up to a couple of hours) history facility, more. And all that for less than $5 (about £3?). Hard to go past.

author: brian_mk
author_rank: Regular Contributor
timestamp: July 28, 2023, 04:55:47 pm
content: If I went down the uP path, would have used an ESP32. It has a DAC and you can use the WiFi to create an all singing, all-dancing web based user interface for a smartphone.I discovered why the CMOS op amp in the sample & hold & loop filter was oscillating. I used an old CA3130 from my junk box. It needed an added frequency compensation cap. The CA3130 has the advantage of an extremely high input impedance.When running with a 1PPS timepulse, the sample & hold droops by about 50mV between sampling periods. I guess this is down to the non-infinite input impedance of the op amp buffer. It relies on the loop filter to remove the phase jitter that would otherwide cause.

author: brian_mk
author_rank: Regular Contributor
timestamp: August 02, 2023, 04:46:20 pm
content: While testing the prototype I discovered something I am unable to explain...If I leave the Neo-6 timepulse interval set to the default (1 sec interval, 100msec width) and generate the 1uS sampling gate pulses using a monostable, the OCXO tuning voltage measures about 3.2V when the loop is locked.If I reconfigure the Neo-6 to give a shorter timepulse interval (e.g. 100 msec interval with a 10msec width) then the OCXO tuning voltage drops to around 2V when the loop is locked.It's still around 2V for shorter intervals and widths such as 10msec interval with a 1msec width, 1msec with a 100uS width or 1msec with a 1uS width.In the case of a 1uS width I can change a jumper such that the monostable is not used and the sampling gate is derived directly from the timepulse.That makes no difference to the OCXO tuning voltage. It remains at 2V.The difference between the two OCXO tuning voltages is worrying.The OCXO has a positive tuning control slope, so the default 1sec configuration must output a higher frequency compared to the shorter intervals and widths.Any suggestions as to what might be going on?

author: nctnico
author_rank: Super Contributor
timestamp: August 02, 2023, 07:28:17 pm
content: On the uBlox module I have used for a GPSDO design, the shorter update intervals didn't seem to work (give weird results). I never really dug into this and chalked it up to a bug. Maybe the shorter update intervals work for navigation only and disable the time synchronisation features. You'd have to ask uBlox what is going on here.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 02, 2023, 08:08:10 pm
content: Quote from: brian_mk on August 02, 2023, 04:46:20 pmWhat happens between 100ms and 1s ? Maybe graph that ?It does sound like it’s not locked properly anymore.

author: MIS42N
author_rank: Frequent Contributor
timestamp: August 02, 2023, 10:21:41 pm
content: Quote from: brian_mk on August 02, 2023, 04:46:20 pmWith the default, the system could be locking on to any frequency divisible by 10. I haven't studied the circuit in detail. The OSC5A2B02 has a specified tuning of 1ppm/V so for a 1V change in the EFC you get a 10Hz change in the output. I'd say the 3.2V locked onto 10.00001MHz.With a more frequent measurement the problem goes away (10 times a second, frequency divisible by 100 - apart from 10MHz the possibilities are outside the pulling range).

author: brian_mk
author_rank: Regular Contributor
timestamp: August 03, 2023, 10:00:55 am
content: Quote from: MIS42N on August 02, 2023, 10:21:41 pmI think you are right.I found the OSC5A2B02 datasheet was a bit unclear so I measured the tuning sensitivity myself using a Racal counter. It gives about 10Hz/Volt which agrees with the 1ppm/V figure you quoted.Although the frequency counter I am using is not calibrated, it has an internal oven and 0.1Hz resolution. I 'think' it is reasonably accurate once the oven has stabilised.When the loop is locked with 1PPS and a 3V tuning voltage, the OSC5A2B02 output frequency reads high by around 10Hz.A tuning voltage of just under 2V gives 10.0000000 MHz on the counter.So it appears that with a 1PPS timepulse, the loop is locking to 10.00001 MHz as you suggest.I am trying to figure out a way to prevent this.I may need to restrict the tuning range so that the loop is unable to pull the OCXO as far as 10Hz - although that may just prevent the loop from locking at all?In the original article, he used an OCXO with a much lower tuning sensitivity (only 0.66Hz/V).With a 5V supply than means it can only pull about +/- 1.6Hz max.He suggests a simple potential divider could be used to reduce the tuning sensitivity (although his concern was the loop transient response rather than locking to the wrong frequency).The problem with a potential divider is that the op amp that drives the tuning voltage will saturate at around 4V (It has a single 5V supply).If the voltage is halved giving a tuning sensitivity of 5Hz/V, then it will struggle to reach the 2V required for 10MHz.Maybe it needs something like a summing amp with variable gain and an adjustable dc offset?An alternative is to find a solution to the timing pulse reverting back to the 1PPS default when the rechargeable lithium battery voltage drops if the unit is left unpowered for 2 weeks.This could be the better solution because the loop works a lot faster with less droop when using a shorter pulse interval.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 03, 2023, 05:33:16 pm
content: Quote from: brian_mk on August 03, 2023, 10:00:55 amIf you are using the circuit in #1, that already has gain and offset.A (large) resistor across the66uF10uF will limit the span away from the 2.500V midpoint.

author: brian_mk
author_rank: Regular Contributor
timestamp: August 03, 2023, 09:30:06 pm
content: Quote from: PCB.Wiz on August 03, 2023, 05:33:16 pmI think you mean 10uF.I did wonder about trying something like that.Ideally the tuning voltage should be 2V at the mid point with a range of just below +/- 1V to restrict the tuning range to just under +/- 10Hz.My concern is that the loop may just get stuck at the upper or lower end of the range and never lock at all.Adding a parallel resistor would change what is currently a straightforward integrator into a 'leaky integrator'.I don't know what 'gain factor' or resistance would be required.The original design uses worryingly high value (3 x 22Meg = 66Meg) resistors in series feeding into the integrator op amp.Adding a parallel resistor may upset the loop transient response.The original designer supplied an LTSpice simulation so I should be able to check what effect it has.I have been reading up about methods of avoiding false locking in PLLs. Apparently it's a common issue.It's more of a problem with Type 1 PLLs than Type 2 PLLs such as this one.One approach might be to monitor the tuning voltage using a window comparator.If the voltage is outside the window, then inject a small positive or negative current into the integrator (using high value resistors) to bring it in range.The original design incorporates a 'slew' switch that does a similar thing manually.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 03, 2023, 10:02:05 pm
content: Quote from: brian_mk on August 03, 2023, 09:30:06 pmThat will not happen, as if it is not locked, it is phase walking, and the phase comparator will eventually head in the right direction.QuoteTypo fixed.

author: MIS42N
author_rank: Frequent Contributor
timestamp: August 03, 2023, 11:17:47 pm
content: Since I made my previous comment without looking at the circuit in post #1, I thought I'd look at the circuit.This is completely off topic, but I am so glad I went the microprocessor route. It does everything the circuit does using a microprocessor, 4 resistors, 4 capacitors, 1 LED. It was debugged using nothing more than the serial port and a multimeter.I think the OSC5A2B02 will need some sort of buffer to feed a signal to the outside world. It is designed to drive HCMOS so not happy feeding into a 50Ω lead. I used an 74HC04. One gate to buffer the OCXO output, feeding another 5 gates (which in hindsight is overkill) to put the signal into the BNC. About 2V peak to peak into 50Ω. The microprocessor clock is bled off through a 22pF cap.If there's a revised design, use less gates to feed the output (1V p-p should satisfy most requirements) and buffer the 1PPS to another BNC. Or maybe a more stable 1PPS generated by the processor.

author: brian_mk
author_rank: Regular Contributor
timestamp: August 04, 2023, 09:09:55 am
content: Quote from: MIS42N on August 03, 2023, 11:17:47 pmI am using TC4424 drivers to provide 10MHz and 1MHz square wave outputs (together with the timepulse signal) at TTL levels into 50 Ohms.I also have filtered 10MHz sine wave outputs that can drive 50 Ohms (using discrete transistors).The sine outputs are isolated using ferrite toroidal transformers to prevent ground loops.That side of things is not a problem. I just need to sort out the PLL issues...At the moment I am finding that with a 1PPS timepulse, the loop fails to pull into lock even when the tuning voltage is within 0.5V of the nominal 2V. (i.e. just a few Hz away from 10MHz).The phase detector output walks from near 0V up to just below 5V as you would expect but the tuning output from the integrator hardly moves.This is the case even after waiting several minutes.I have tried reducing the integrator resistor values to speed things up. That makes no difference to the failure to lock.The problem doesnothappen if I decrease the timepluse period from 1 sec down to a few hundred millisconds or below.Perhaps there is insufficient loop gain when the loop only receives a small 1uS pulse once per second?One thought is that it may be related to the fact I am using CA3130 CMOS op amps instead of the LMC6582 used in the original design.The CA3130 has an input current of only about 5pA but that is still considerably higher than the 80fA for the LMC6582.As the integrator uses exceptionally high value resistors, that could make a difference to the loop gain.I have ordered some LMC6582 devices to test. Unfortunately they are surface mount so I will need to mount them on DIP8 adapters.

author: Solder_Junkie
author_rank: Frequent Contributor
timestamp: August 04, 2023, 10:34:50 am
content: Brian, I too have a Racal 1998. I also have a Leo Bodnar GPSDO, which is pretty good.I currently use a dual trace scope for calibration, but fancy a TinyPFA which should make calibration a bit easier.Mirfield Electronics expects to have stock on the ‘PFA in 3 to 4 weeks. You can also re-flash their VNA to a PFA.Details of the PFA:https://www.tinydevices.org/wiki/pmwiki.php?n=TinyPFA.HomepageSJ

author: MIS42N
author_rank: Frequent Contributor
timestamp: August 04, 2023, 10:58:18 am
content: Quote from: brian_mk on August 04, 2023, 09:09:55 amThe advantage of knowing your stuff. I used the 74HC04 because I'd seen other circuits using it. It works and the old adage "if it ain't broke..." But the TC4424 looks ideal and would have saved me a bit of board space. And not expensive. Next time gadget, next time.Sorry I can't help much with the PLL side. The description of the circuit in #1 post did say a FET input op amp. But you may get around it by making the connection between the 74HC74 and the CD4016 a direct connection (why not?) and replacing the 10K resistor between the CD4016 and the op amp (their LMC6582, your CA3130) with 1K. Increase the 100pF capacitor to 2200pF to keep the time constant the same. The 74HC74 is rated to source/sink 5mA and that's the max that will flow through the 1K resistor (and only for 1µs). That will ease the need for a high impedance input, and if you are getting results with 10 PPS then the revision should work for 1PPS.You'd be able to figure out if this is a workable method by scoping the output of the op amp. If it were working properly, the output should be a fairly flat line for each second (and forget all I said). If leakage is a problem it would drift off one way or other and it would be worth trying the fix.Messing with the high value resistors may not make much difference - 5pA through 66MΩ is 0.33V which may make the phase lag or lead a bit but not enough to throw the system out. As evidenced by the fact it work with a higher sample rate.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 04, 2023, 02:56:03 pm
content: Quote from: brian_mk on August 04, 2023, 09:09:55 amYes, it looks like the filter slew rate, with the very low injection energies of 1us per second, fails to follow that faster phase walk. Looks slow to our eyes, but that is a VERY long time constant filter.If you know when itdoesstart to work, that indicates you are close, and you may be able to tune things.I did wonder about doubling the injection energy by using a XOR gate + delay RC to give a pulse on each edge, but even that still has 900ms hold-over.The fact the original design has a manual helper ‘slew’ 3 way paddle switch, suggest manual assist could be part of normal operation.

author: brian_mk
author_rank: Regular Contributor
timestamp: August 05, 2023, 01:05:40 pm
content: I was thinking about the problem early this morning while still in bed.I came up with what seems like a plausable explanation...When the two frequencies differ, the phase detector outputs a sawtooth waveform that represents the phase difference.In the idealised case, the sawtooth goes from 0V to 5V and is centered around 2.5v.At the 0V and 5V points, where the sawtooth jumps, the phase difference between the two signals reaches 2 * PI.When the sampling interval is long (i.e. once per second) the sawtooth is not linear but changes in sudden steps.When you integrate the sawtooth over a long period, the integrator output (=OCXO tuning input) remains at the midpoint i.e. 2.5V and the loop fails to lock.It will only lock if the sawtooth does not jump (i.e. the phase difference does not cross the 2 * PI threshold) before the output from the integrator has had time to respond to the ramp.The nonlinear sawtooth resulting from the long sampling interval must make this situation worse.It means the loop has a small capture range; the two frequencies have to be close to begin with.

author: MIS42N
author_rank: Frequent Contributor
timestamp: August 06, 2023, 12:16:41 am
content: I too have been thinking about that circuit. I did some calculations to see if my assumption that op amp leakage is a problem. Turns out it isn't.There is a pulse 1µs wide taking current from Q1 of the 74HC74 through 20kΩ to charge/discharge the 100pF capacitor input to pin 3 of the LM6582.The maximum voltage possible across the 20kΩ is 5V. So the maximum current possible is 5/20,000 = 250µA. For 1µs.That's equivalent to 250pA continuous into 100pF which should result in a 'jog' of more than 1V at worst case. Using an op amp with leakage of 5pA should be fine and the circuit should work.The write up says "A tuning sensitivity anywhere near this value will work fine, from as high as 1 x 10-7 per volt ...". The problem is the tuning sensitivity is much higher at 1 x 10-6per volt.I think the solution is to add an extra divide. There's nothing sacred about divide by 10. An extra divide by 2 inserted between the 74HC190 and the 74HC74 may be enough and divide by 4 almost certainly (hedging my bets here, I think 100% but nothing is guaranteed until it committed to hardware). The 1MHz output can still come from the output of the 74HC190.With an extra divide by 4, the total is divide by 40 so the system can only lock onto frequencies divisible by 40. That takes it well out of the pulling range so can only lock onto 10MHz. It also means the frequency window (the time for the PLL to lock onto the signal) is 4 times longer. The pulse width will be longer at 4µs so 4 times as much charge goes into the capacitor input to pin 3 of the op amp. Which makes any leakage problem is less important. To retain the time constant it should be increased to 470pF and the timing of the 74HC74 monostable needs increasing to 4µs.Thoughts?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 06, 2023, 12:42:53 am
content: Quote from: MIS42N on August 06, 2023, 12:16:41 amMoving away from lock-alias points seems a good idea, and you can use any division.Suitable single-package choices could be HC393, HC4520, or even a HC4060 which can AC couple to 10MHz in, but has /16 as smallest tap.HC390 is dual decade, for other non-binary divide options.Binary is ok for divides up to /128 - you just need to ensure you have exact N cycles per pps (or faster set) frame. so eg 1250 is a ok faster pps rate for moderate binary dividers.

author: brian_mk
author_rank: Regular Contributor
timestamp: August 09, 2023, 09:38:42 am
content: Update...The false locking problem no longer happens.The reason is that in my version of the circuit, the OCXO is fed from a separate 5V regulator. It includes a current sensor that detects when the OCXO reaches temperature.Until the OXCO has warmed up, the loop remains open and tuning voltage is derived from a preset trimmer.When the current sensor detects that the OCXO has reached temperature, a relay switches the tuning voltage to the loop integrator output.Previously I set the preset tuning voltage to about 3V. This resulted in the false locking problem.It was only after I tried increasing the Neo-6 timepluse interval above 1PPS I realised that the correct tuning voltage should be about 2V.Having corrected this, the loop no longer erroneously locks to 10,000,010 Hz at startup.The LMC6852 low input current dual op amps I ordered arrived. I mounted one on a DIP8 adapter and connected it in place of the two CA3130 devices.As expected it reduces the droop over the 1 second sampling interval. Otherwise it makes little difference.I am left with one problem; the acquisition range of the loop...From my observations, the loop is unable to lock when it is cycle slipping (i.e. the phase detector is crossing the 2 * PI threshold).I can get this to happen by jogging the center-off slew switch so that the tuning voltage is above or below 2V by a couple of hundred millivolts.In this state the phase detector is outputting a 1V->3V sawtooth waveform. It no longer provides a voltage proportional to the phase error.(The sawtooth is not linear but changes in steps when the 1PPS samples occur - although I don't think that this affects this issue).The integrator output is the average of the 1V->3V sawtooth and remains steady, somewhere near the middle; it does not pull the OCXO into lock.Unlike some other types of phase detector, there appears to be no offset that gradually pulls the OCXO towards the required frequency when cycle slipping is taking place.I managed to download PDF copies of a couple of PLL books: Phase Lock Basics (Egan) and Phase Lock Techniques (Gardner).Both books are full of lots of useful information including different types of PLL, loop filters, transient response etc.They discuss various 'Lock Assist' techniques that help the loop to acquire initial lock.This includes adding a slow sweep to the tuning signal, including a frequency discriminator in addition to a phase detector, open loop frequency acquisition etc.The 'open loop frequency acquisition' technique gave me an idea...My version of the circuit includes a window comparator that monitors the output from the integrator.It is used to light an LED when the tuning voltage is within about +/- 100mV of the 2V needed for 10,000,000 Hz.What if I use the window comparator to switch the startup relay and connect the OCXO tuning voltage to the preset trimmer whenever the integrator output is outside the lock range? i.e. open the loop in a similar way to what happens at startup.When I tried it, I found that the system can still get stuck in a state where, although the open loop preset tuning voltage is close to the required 2V, the phase detector output is cycle slipping and the integrator output remains stuck outside the lock range indicated by the window comparator.I am still searching for a solution.

author: MIS42N
author_rank: Frequent Contributor
timestamp: August 09, 2023, 10:31:06 am
content: Quote from: brian_mk on August 09, 2023, 09:38:42 amSo my analysis was right! Your op amps were adequate.Quote from: brian_mk on August 09, 2023, 09:38:42 amHave you dismissed the extra divide by 4 option?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 09, 2023, 08:24:42 pm
content: Did you find out what sample rate does lock ok ? Iirc it was some hundreds ms, so you are close ?As the sample rate changes, the LPF also changes slew rate, so a value tweak may be all you need.

author: brian_mk
author_rank: Regular Contributor
timestamp: August 12, 2023, 07:39:12 pm
content: I think I may have found a solution...After I realised that this type of phase detector will only work correctly when not cycle slipping, I decided to automatically steer the OCXO tuning voltage when the loop is out of lock by injecting a positive or negative slew current into the integrator.I re-configured the window comparator that monitors the integrator output as two separate comparators giving two logic signals.One indicates the tuning voltage is above the high cycle slipping threshold, the other indicates it is below the low threshold.These signals control a pair of analogue switches that switch a high value resistor to inject either a positive or negative current into the integrator and correct the error.The thresholds are set just inside the tuning voltages where cycle slipping begins.Rather than use 0v and 5v to supply the current, I am using the potential divider that provides the reference voltages for the comparators.After modifying the prototype, it appears to work as expected.It still needs more testing but it's looking hopeful (fingers crossed).I'm glad I went to the trouble of building a hand wired prototype before making a PCB.

author: brian_mk
author_rank: Regular Contributor
timestamp: October 13, 2023, 02:50:58 pm
content: A couple of pics of the finished project.It's taken longer than expected.It may look a bit old-school but I still prefer using through hole components for home constructed test equipment.I used a 20 segment bar graph istead of an analogue meter - it was easier to fit in the case.I am currently in the process of using the GPSDO to calibrate several items of test gear.So far it seems to be working well.I used a radio tuned to BBC R4 198kHz along with a signal generator with it's EXT 10 MHz input connected to the GPSDO for a quick accuracy test.