ESR of 4700uF using a Digital Scope? - Page 1
Forum section: electronics / projects

author: KerimF
author_rank: Frequent Contributor
timestamp: February 15, 2025, 08:16:57 pm
content: Hello,I need to measure the ESR of two unknown 4700uF/35V. They will be used in a balancer board for two 12V acid batteries.Do you think the attached circuit, ESR_NE555_v1.png, will work?Thank you.

author: Solder_Junkie
author_rank: Frequent Contributor
timestamp: February 15, 2025, 09:16:41 pm
content: Have you checked YouTube w2aew ESR? Alan covers the subject in considerable depth.SJ

author: KerimF
author_rank: Frequent Contributor
timestamp: February 15, 2025, 10:16:19 pm
content: Sorry, in the previous circuit, the actual Rds_on (in this example) is around 16mR (not 10mR).The ESR of the capacitor 4700uF, under test in this circuit, is 33mRFrom the two equations :Ic_max = Vc_max / (Rc + Rmos)Vc_min = Vc_max – Ic_max*RcWhere:Ic_max = 13.474 AVc_max = 667.7 mVVc_min = 217 mVRmos = 16 mRRc = 33mR (supposed unknown)We get:Rc = Rmos*(Vc_max / Vc_min - 1)Rc = 16*(667.7/217 - 1) = 33.23 mR

author: tggzzz
author_rank: Super Contributor
timestamp: February 15, 2025, 10:45:30 pm
content: Firstly, you don't need a digital scope. An analogue scope would be sufficient since it is a repetitive signal.Secondly, there is a simple technique which uses a R=50ohm signal generator and a scope, and nothing else.Connect the signal generator across the capacitor C, and select a square wave output with amplitude 0-Vsourcevolts and around 1kHz. Observe the voltage across the capacitor with the scope.The waveform willmainlybe the expected exponential RC risetime, where R is 50ohms. If necessary, adjust the frequency and voltage so that is visible.But that won't be all you can see. Where the signal generator output changes, there will be a small step voltage change Vstepbefore the expected exponential RC starts. That step is caused by the capacitor's ESR, RESR. R and RESRform a potential divider, so that the usual equation appliesVstep= Vsource* RESR/ ( R + RESR)Knowing R and Vsource, RESRcan be calculated.

author: KerimF
author_rank: Frequent Contributor
timestamp: February 16, 2025, 09:30:01 pm
content: Quote from: tggzzz on February 15, 2025, 10:45:30 pmGood remark. Thank you.Quote from: tggzzz on February 15, 2025, 10:45:30 pmThis method is good if R and RESRare comparable.If RESR<< R, like 50mR and 50R (0.1%), measurements cannot be accurate, speaking practically.====================================For instance, I did the test, I got:Vc_max = 722 mVVc_min = 170 mVAnd I had from another test:Rmos = 10 mR [MOSFET P75PN75]By applying:RESR= Rmos*(Vc_max / Vc_min - 1)RESR= 10*(722/170 - 1) = 32.5 mR [of 4700uF/35V]

author: tggzzz
author_rank: Super Contributor
timestamp: February 16, 2025, 11:17:26 pm
content: It is wrong to think of ESR as having a single correct value, just as it is wrong to think that a capacitor can be characterised by a single value for capacitance (start with dielectric absorbtion, and MLCCs losing 90% of their capacitance at the rated voltage!).Capacitors are based on complex combinations of electrostatic and ionic reactions; C and ESR are simplified models of the behaviour that are useful in many limited circumstances. Hence arriving at differing values for ESR is to be expected.Similarly, a FETs resistance is not a single value - just look at the family of VI curves.You need to justify why a potential divider "cannot be accurate" where the two resistors are "very" different.In the end, what matters is how a capacitor operates under the conditions in your circuit (and changes over time). Corollary: make your tests as similar as possible to the capacitors operating conditions.

author: KerimF
author_rank: Frequent Contributor
timestamp: February 16, 2025, 11:32:04 pm
content: Quote from: tggzzz on February 16, 2025, 11:17:26 pmThis is what I did (and will do for other conditions if necessary).

author: mawyatt
author_rank: Super Contributor
timestamp: February 17, 2025, 04:00:19 pm
content: If one has access to a modern DSO like the new low end Rigol's and Siglent's then getting a crude estimate of the capacitor ESR becomes an easy task. As mentioned, ESR is a highly dependent and variable capacitor parameter and results should be viewed with this consideration.Here we've utilized an AWG as the Pulse Source set to 1Vpp and 1VDC Offset, with a PW of 500us and frequency of 10Hz, we've also included a series resistor of 50Ω with the AWG output. The reason for these parameters is using a short PW will keep the Capacitor DUT Voltage low so not to saturate the DSO Input, the low Frequency is to allow the DUT to settle between pulses. Adding 50Ω is series with the AWG allows the AWG to "see" a 50Ω load on the Pulse Edge and also makes the math easier as one just multiplies the the voltage step on the DSO by 100 to get the equivalent DUT ESR, derivation left as a reader exerciseThe DSO uses 2 Channels, one channel (Ch3 in this case) is used to Trigger the DSO and is connected to the AWG outputbefore the 50Ω series R. Ch1 is connected to the DUT top (bottom is common ground) and has a 1X Probe setting for low voltage readings. Also as shown we've added a math channel to allow Averaging Ch1 readings for better noise performance. Cursors are used to measure the "Step" as shown at the DUT Pulse Front Edge which turns out to be due to the DUT ESR and the effective DUT ESR is simply 100Ω times time curser delta voltage reading.Here's a few measurements (we don't have any capacitors larger than 1500uF) and compared to a LCR Meter (IM3536) results at 100Hz, DSO and (LCR Meter) readings.1500uF @ 16V 45mΩ (56mΩ)1000uF @ 16V 86mΩ (108mΩ)680uF @ 35V 73mΩ (95mΩ)Anyway, an interesting and useful use of these new low end DSOs. As mentioned above one should consider results for any ESR measurements as just "ball park" values, and for more reputable results try and duplicate the electrical (and thermal) environment the DUT will experience is actual useBest

author: KerimF
author_rank: Frequent Contributor
timestamp: February 17, 2025, 06:18:26 pm
content: If I understood well, the initial current Iini= 1V / 50Ω = 20mAThe step voltage, Vstepdue to RESR= RESR* Iini= 45mΩ * 20mA = 900uVIt seems the accuracy of the modern DSOs are 100 times better than mine which is an 18-year-old DSO.

author: mawyatt
author_rank: Super Contributor
timestamp: February 17, 2025, 06:24:15 pm
content: Quote from: KerimF on February 17, 2025, 06:18:26 pmWe added a 50Ω resistor in series with the AWG as mentioned. So with the AWG source resistance of 50Ω and the 50Ω series resistance this equals a peak current of 10ma (1V/100Ω), and forms a voltage divider with the DUT ESR at the critical edge of the step voltage from the AWG.BTW for low ESR values you shouldn't use a Photo-Board like we did for this demo, hardwire things together in the DUT sense path where test current flows (thru the DUT) to reduce any parasitic wiring/setup resistances.Best

author: schmitt trigger
author_rank: Super Contributor
timestamp: February 17, 2025, 07:28:40 pm
content: Kerim;If you are planning on using the circuit on your first post, please ensure that the 555’s reset terminal is connected to VCC.The simulation may not require it, a real world circuit does.

author: mawyatt
author_rank: Super Contributor
timestamp: February 17, 2025, 09:10:04 pm
content: We found 3 of the 1500uF 16V Caps, so paralleled to get close to OP 4700uF. We increased AWG amplitude to 10Vpp to increase peak current to ~100ma, and reduced PW to 20us and 1Hz to reduce amplitude to DUT and allow more settling time, and average increased to 64.The 3 paralleled DUT Caps produce ~20mΩ ESR which agrees with single Cap ESR of 56mΩ as shown above.Anyway, appears this DSO and AWG technique can be adapted to handled smaller ESR Capacitors without additional setup components.Best