What is the impedance of 0.5mm FPC? - Page 1
Forum section: electronics / beginners

author: ssashton
author_rank: Frequent Contributor
timestamp: October 24, 2024, 06:24:40 pm
content: I'm connecting two PCBs with 0.5mm FPC and this carries I2S digital audio as well as a master clock with GND on either side of the signals. I know that typically one aims to run such signals over a 50 ohms impedance on a PCB, but snice I am stuck with the FPC in the middle, I figure it would probably reduce EMI if I can match my PCB traces and source_R to the FPC impedance, right?In practice it probably doesn't matter, but we aim for perfection!

author: TimFox
author_rank: Super Contributor
timestamp: October 24, 2024, 06:33:34 pm
content: How long is the FPC between boards, and what is the rise time of your signals?Is your FPC double sided?(It is good form to define any abbreviations on first use in a memo or question.)

author: ssashton
author_rank: Frequent Contributor
timestamp: October 24, 2024, 06:43:23 pm
content: By FPC I mean a cable like the one shown, not a flexible PCB, sorry for confusion.Length is about 5cm.

author: tooki
author_rank: Super Contributor
timestamp: October 24, 2024, 08:24:44 pm
content: Quote from: ssashton on October 24, 2024, 06:43:23 pmThose are called FFCs (flat flex cables). FPC means "flexible printed circuit" and generally refers to more complex designs.Quote from: ssashton on October 24, 2024, 06:24:40 pmThe impedance would depend on the construction of the FFC (or FPC, for that matter), especially the trace thicknesses, widths, and spacing.Standard FFCs aren't impedance-controlled, but you certainly can find controlled-impedance FFCs.

author: ssashton
author_rank: Frequent Contributor
timestamp: October 24, 2024, 09:02:27 pm
content: Thanks, I'll try to get in to the habit of calling them FFC. Everywhere I look the cables and connectors seem to be called 'FFC/FPC'.While they are not impedance controlled and neither is my stack-up, I figure there would be no harm in a rough estimate as we do for PCB dielectric constant.

author: TimFox
author_rank: Super Contributor
timestamp: October 24, 2024, 09:07:19 pm
content: 5 cm is roughly 0.3 ns (or less) electrical length, depending on the line.Repeat: what is the rise time of your signals?

author: tszaboo
author_rank: Super Contributor
timestamp: October 24, 2024, 09:13:03 pm
content: Quote from: ssashton on October 24, 2024, 06:24:40 pmNo. The source impedance of an I2S signal is almost 0 Ohm, the receiver is more than 10KOhm, and it's not impedance matched anywhere, nor should it be.There is nothing 50 Ohm about a system with I2S.

author: ssashton
author_rank: Frequent Contributor
timestamp: October 24, 2024, 09:14:17 pm
content: Even the bit clock and master clock?

author: ssashton
author_rank: Frequent Contributor
timestamp: October 24, 2024, 09:17:44 pm
content: I do not know the rise time, slew rate is configurable via the DSP driving the line, but the datasheet does not say a value other than 'low' to 'high'.

author: tszaboo
author_rank: Super Contributor
timestamp: October 24, 2024, 09:55:27 pm
content: Quote from: ssashton on October 24, 2024, 09:14:17 pmTTL or CMOS signals.Look at the specification:https://web.archive.org/web/20070221200945/http://www.nxp.com/acrobat_download/various/I2SBUS.pdf

author: ssashton
author_rank: Frequent Contributor
timestamp: October 24, 2024, 11:13:01 pm
content: I'm using an audio DSP and copied the evaluation board design that uses resistors in series with the I2S lines (near the bottom R102 and MCLK on pin 23). They seem to prefer 33R rather than 50R, perhaps to match their traces? Any insight why the designer would do this? I'm not trying to disagree with you by the way, I just want to learn.

author: ssashton
author_rank: Frequent Contributor
timestamp: October 24, 2024, 11:41:16 pm
content: Well, I suppose those resistors can simply be to buffer the driver circuit from parasitic capacitance and inductance.

author: tooki
author_rank: Super Contributor
timestamp: October 25, 2024, 04:40:03 pm
content: Most sources claim no impedance control recommendations for I2S, but onedatasheetfrom a Knowles I2S microphone says this:Quote(The same datasheet also says to refer to an application note that doesn’t exist.)

author: tszaboo
author_rank: Super Contributor
timestamp: October 25, 2024, 05:08:03 pm
content: Quote from: ssashton on October 24, 2024, 11:13:01 pmSlew rate control. Some also say "impedance matching" but the impedance is not really matched. If an impedance is matched then the output is halved, and that's not good.

author: Siwastaja
author_rank: Super Contributor
timestamp: October 25, 2024, 05:54:18 pm
content: Quote from: tszaboo on October 25, 2024, 05:08:03 pmIn source termination output voltage at the receiving end is not halved and you can still impedance-match a source terminated transmission line, nothing weird there. You are confusing two related but orthogonal terms "impedance control" and "parallel termination", latter of which indeed halves voltage amplitude.That being said, inaccurate output resistance of typical CMOS drivers used for I2S stuff means you can't have accurate impedance control. You can still get kinda-sorta control which is better than nothing. Simply assume typical output resistance of approx. 20-50 ohms and add series resistance, 33R to 47R would be very typical range. You can finetune it through prototyping but probably there is no need. Just slap in 33R or 47R in series with the driver side.Thing to remember in series terminated lines is not to do any branching. They are point-to-point lines. Signal integrity is good only at the receiver pin; remember this when scoping the signal.To OP, I did this semi impedance controlled thing for a 8-bit synchronous parallel bus running at 40MHz over some quite long (60cm) FFC cables and did Google the shit out and was able to find some numbers for 0.5mm pitch FFC with ground-signal-ground-signal arrangement and I think it was roughly around 70 Ohms. Do the research or adjust series termination by experimenting, measure waveform at receiver and adjust R to get rid of overshoot and not slow down the edge too much to cause communication issues.But the CMOS driver resistance is temperature and unit-to-unit dependent (not to talk about manufacturing tolerances of FFC cables) so if you aim for a perfect match in prototype some products might end up having some overshoot and some end up slowing down the edge. So aim for a little bit too slow, larger resistance value that is. If this is a problem for your data rate, then you need some other solution than single-ended I2S over FFC.But seeing how short you proposed FFC is I don't think there is any problem. But do have proper alternative grounding and do usesomevalue of series R or you could see significant enough overshoot to cause EMC fail.

author: ssashton
author_rank: Frequent Contributor
timestamp: October 27, 2024, 09:11:47 pm
content: Thanks for the very helpful info!