Allowable vias on 4-layer PCB - Page 1
Forum section: electronics / general

author: prasimix
author_rank: Unknown
timestamp: January 06, 2018, 08:34:32 am
content: This is possibly question many times answered, but with my searching skills I didn't find a straight answer yet: what type oftrough holeandblindvias are allowed on 4-layer design?I'm going to make my first 4-layer PCB, and came into position for the first time to think about it and immediately stuck. Here is what I presume that is possible, or better to say, a proper usage of multiple layers:Top (1) and bottom (16) layers should be used for signaling, upper middle layer (2) is GND, and lower middle layer (15) is for power. All SMT parts will be on the top layer therefore for the signal trace connecting between 1 and 16, trough hole via should go from top to bottom. But, for GND and power, I'd like to have 1-2 and 1-15 type of blind vias. In summary it should looks like this:I've checked design rules file from few PCB manufactures, and nobody offer such "freedom". In most case I can see that trough hole via (1-16) is allowed.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 06, 2018, 08:49:50 am
content: Depends on the manufacturer and how much you want to pay.4L is typically built from inside out so the next step up from fully through is L2-L3, which isn't as useful as 1-2 or 3-4.As soon as you go away from simple through vias, you're out of pooling prices and will have significant tooling costs.See the Eurocircuits manufacturing video in the production section for info on the manufacturing process

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 06, 2018, 08:51:20 am
content: You may find it cheaper to go to finer linewidth and smaller hole sizes to get the density increase

author: prasimix
author_rank: Unknown
timestamp: January 06, 2018, 08:54:30 am
content: Phew, now I understand. So for accessing power layer (3) I have to waste space on bottom layer, too. I can try to manage that with smaller hole sizes as you suggested.

author: prasimix
author_rank: Unknown
timestamp: January 06, 2018, 09:00:34 am
content: Just to summarize, the following setup should be fine for cheap manufacturing?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 06, 2018, 10:00:37 am
content: Quote from: prasimix on January 06, 2018, 09:00:34 amAIUI,the cheapest is buried 2-3, as 1-2/3-4 needs more manufacturing steps.

author: rob77
author_rank: Super Contributor
timestamp: January 06, 2018, 10:20:44 am
content: this is the cheap process you're looking for:(1+(2*15)+16)

author: prasimix
author_rank: Unknown
timestamp: January 06, 2018, 10:28:28 am
content: Ok, but I don't see any advantage of having vias between 2 and 15 that I'd like to use for GND and power. I'll try to route everything with just 0.3 mm thru holes (i.e. 1-2-15-16)

author: asmi
author_rank: Super Contributor
timestamp: January 07, 2018, 07:32:17 pm
content: If you want it cheap, forget about blind/buried vias. Use only through vias. I personally never felt the need of BB vias anyway even for fairly complicated 6 layer boards.

author: Omgitskillah
author_rank: Newbie
timestamp: January 07, 2018, 07:44:40 pm
content: Most fab houses for low volume boards probably wouldn't give you complex options for vias. Stick to blind, burried or through vias. Avoid doing combinations of blind and buried vias. Some fab houses like wellPCB could be flexible if you get to talk to them first. Otherwise, make complex designs only if you will do large board runs to cushion the cost.

author: asmi
author_rank: Super Contributor
timestamp: January 07, 2018, 07:53:54 pm
content: The thing is - in many cases it's cheaper to use 6 layers with thru-only vias than 4 layers with BB vias. Like I said above, I never ever needed them in my designs anyway. I looked at very complicated boards like iMX 6 Dual and Quad core ARM CPU boards, and none of them used BB vias. So only consider using them as a last resort, when all other options have been tried and found unusable/not practical.

author: rx8pilot
author_rank: Super Contributor
timestamp: January 07, 2018, 08:03:44 pm
content: I jump over mountains to avoid blind/buried vias because it takes longer and adds considerable cost. My next design, due next month, is likely to have them but it will only be after I have exhausted every routing option I can come up with. In that case, it is a mix of high-current multi-rail, polyphase SMPS on the same board as 6Gbps IO and DSP. 6 layers with power on one side and digital on the other with the highest density I have personally ever attempted.Outside of that nightmare....I have been able to avoid blind/buried vias.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 07, 2018, 11:35:37 pm
content: Quote from: asmi on January 07, 2018, 07:53:54 pmThe problem is that IME the first thing you run out of is space on the outer surfaces, so having blind vias between 1/2 and 3/4 means vias only take up surface pace on one side of the PCB, whereas 2 extra layers may not be much help.

author: asmi
author_rank: Super Contributor
timestamp: January 08, 2018, 02:19:54 am
content: Quote from: mikeselectricstuff on January 07, 2018, 11:35:37 pmI'm yet to see a design where there is no space on outer surfaces. Two extra layers is a HUUUGE help because they give you two times more routing channels than you have on 4 layers board, and more importantly these two extra layers are 100% available, while outer layers of 4 layer board need to share space with actual components' breakouts. So most of your routing will be internal, and outer layers will have mostly just short breakout traces to vias. This is why BGAs are becoming more popular - all breakout vias for them are physically under the part, so no surface estate is wasted. And I personally would take BGA over QFN any day because breaking out BGA is easier than big QFNs with small pitch. On my recent board I had quite a bit of troubles breaking out 0.4 mm pitch QFN-76 such that breakout area will be as small as possible (because traces are fairly hi-speed and so need to be quite wide with at least 1:1 spacing to keep crosstalk in check, and one of these traces was carrying clock signal into FPGA).Like I said - show me a 4 layer design where BB vias are required, and I will most likely find a way to route it on a 6 layer board without BB vias.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 08, 2018, 12:33:08 pm
content: Quote from: asmi on January 08, 2018, 02:19:54 amhere you go....A significant constraint was keeping within hole size and annular ring design rules for pooling services. More layers would have been almost no advantage, blind vias would have made a huge difference.

author: Neilm
author_rank: Super Contributor
timestamp: January 11, 2018, 07:56:36 pm
content: I looked at getting blind vias on my latest board - it pushed the price of the board up by over 5 times.Quote from: asmi on January 08, 2018, 02:19:54 amIn my application, I needed to have 16mm of clearance between two channels so one is on the top of the board, the other on the bottom. In the end I managed to route the high voltage stuff on just one layer so didn't need the buried vias.