How to interface a (one) logic signal from CMOS to 0-2V low/19-20V high - Page 1
Forum section: electronics / projects

author: leonababy
author_rank: Regular Contributor
timestamp: July 08, 2018, 03:46:05 am
content: I need to interface the output of a CMOS device (CD 4017 counter) operating from a 5V supply to one input of a P-channel MOS device which is operating at 20V, and it requires a "low" input of 0 to 2V, and a "high" of 19 to 20V. The PMOS device does not have input current specs that I could find in the data sheet.This signal's rise/fall time is not critical, the signal will have a continuous duty cycle of about 1/6, with the short "high" about 8 ms long.Is there an easy way to do this that someone is familiar with? I've done some Googling and haven't found anything yet. I thought of possibly an optoisolator or something similar to an open collector buffer, but this is as far as I got. I only need the one signal translated. Thank you in advance. Don

author: Bassman59
author_rank: Super Contributor
timestamp: July 08, 2018, 04:43:04 am
content: Quote from: leonababy on July 08, 2018, 03:46:05 amUse a MOSFET gate driver like EL7202?

author: mino-fm
author_rank: Regular Contributor
timestamp: July 08, 2018, 11:12:47 am
content: A cheap and simple solution: 1/2 LM358

author: Benta
author_rank: Super Contributor
timestamp: July 08, 2018, 01:31:45 pm
content: Quote from: mino-fm on July 08, 2018, 11:12:47 amI don't think the LM358 output swings high enough. But some other rail-to-rail output op amp could do the trick.

author: leonababy
author_rank: Regular Contributor
timestamp: July 08, 2018, 02:33:59 pm
content: Thank you for the replies. Might something like this work?

author: Benta
author_rank: Super Contributor
timestamp: July 08, 2018, 02:36:45 pm
content: If you place a pull down resistor on the collector of Q2 it should work.

author: leonababy
author_rank: Regular Contributor
timestamp: July 08, 2018, 02:57:10 pm
content: Quote from: Benta on July 08, 2018, 02:36:45 pmThank you. The absence of a pulldown originally caught my eye, but I forgot about it. This design came from someone who was driving VFD anodes, not an IC. I assume the PMOS input has one or two FET gates, drawing nA, so I can use a fairly high value pulldown?

author: Benta
author_rank: Super Contributor
timestamp: July 08, 2018, 03:20:22 pm
content: Sure, but don't make it too large. I'd go for something like 100 k. But play around, if it gets very large you'll have a problem with switching speed, even in the ms range.

author: leonababy
author_rank: Regular Contributor
timestamp: July 08, 2018, 03:47:24 pm
content: Thank you again for your guidance. My thought, not knowing any better and having no experience with FETs, was to hope for around 100k. The current draw and power lost in the pulldown when driving high concerns me, but at 100k it would be acceptable. I'll give it a try and see what happens.

author: mino-fm
author_rank: Regular Contributor
timestamp: July 08, 2018, 04:07:46 pm
content: QuoteA typical P-MOSFET (like IRF4905) will be off at Vgs <= -2 V. Otherwise you can add a pullup resistor (10 k) to get full 20 V "high" voltage in off-state.I think it is more important to get a fast on time (falling edge) with "low" voltage <= 1 V.

author: Benta
author_rank: Super Contributor
timestamp: July 08, 2018, 04:27:26 pm
content: Quote from: mino-fm on July 08, 2018, 04:07:46 pmThe OP talks about a P-channel MOS device, not a MOSFET. My understanding is that it's a PMOS IC, based on the logic voltages mentioned.

author: leonababy
author_rank: Regular Contributor
timestamp: July 08, 2018, 04:45:24 pm
content: No need for me to keep it a secret - it is an (antiquated) MM5316 clock chip I am driving. My only guess as to why the spec sheet does not list the input current is that the anticipated designs use mechanical switches on the inputs.

author: Benta
author_rank: Super Contributor
timestamp: July 08, 2018, 05:14:29 pm
content: MM5316? Now THAT brings back memories...

author: leonababy
author_rank: Regular Contributor
timestamp: July 08, 2018, 08:58:22 pm
content: This works like a champ, at least without connecting it to the load yet. Virtually a complete swing from 0V to 21.3V, which is what the power supply was set for at the output. The rise time was less than 10ns (I believe - I didn't check it carefully), and the fall time 24us. 24us is quite acceptable for my application and I may not try to improve it. This signal is currently too long already by a few hundred u-sec due to a zero crossing detection delay of the AC waveform at the falling edge driving both the clock chip and the 4017 circuit, and I already planned to be gate it.I read a comment somewhere that VFD's really complicate things due to the voltage needed, and the filament supply. I would agree. It's been a good way to dive back into electronics after decades away. The internet helps a lot, and this forum is an awesome resource.

author: floobydust
author_rank: Super Contributor
timestamp: July 09, 2018, 07:16:51 pm
content: National Semi MOS/LSI clock chips like MM5314, MM5316, MM5387 etc. their inputs are PMOS with internal pullup resistor. AC ref input is a Schmitt trigger without the pullup.I would use an open-collector NPN transistor to drive that, orULN2004as an IC with seven+resistors inside, for 6-15V drive.You can instead run the clock IC off 15-18V and a CD4017 would interface directly, running off the same rail.To get higher brightness (>20V) with a VFD, just bias the VFD cathode at a -ve voltage like the datasheets.Since these old clock ICs are hard to find and a bit fragile, maybe post your circuit here for us to check and avoid any calamity.