Intel/Altera - DDR3 megafunction fails in Quartus 20.1.1 - Page 1
Forum section: electronics / general

author: asmi
author_rank: Super Contributor
timestamp: February 14, 2021, 12:28:16 am
content: I've been trying to use DDR3 wizard to create a DDR3 controller, but it fails with some weird messages. Does anybody know what the hell is wrong with it?I have performed everything mentioned in this thread:https://community.intel.com/t5/Intel-Quartus-Prime-Software/DDR3-megawizard-generation-error-in-Quartus-20-1/td-p/1244332, but that didn't seem to help at allHere is error log:Code:Info: DDR3C: Variation language : VerilogInfo: DDR3C: Output directory : D:\Andrey\Projects\Altera\DECA_DDRInfo: DDR3C: Generating variation file D:\Andrey\Projects\Altera\DECA_DDR\DDR3C.vInfo: DDR3C: Generating synthesis files<html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>" for QUARTUS_SYNTH<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>"<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"Info: Generating clock pair generatorInfo: Generating altgpioInfo:Info: *****************************Info:Info: Remember to run the DDR3C_p0_pin_assignments.tclInfo: script after running Synthesis and before Fitting.Info:Info: *****************************Info:<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormallyError: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failedError: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0Error: UniPHY Sequencer Microcode CompilerError: Copyright (C) 2020 Intel Corporation. All rights reserved.Error: Info: Reading sequencer_mc/ac_rom.s ...Error: Info: Reading sequencer_mc/inst_rom.s ...Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ...Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ...Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...Error: Info: Writing sequencer/sequencer_auto.h ...Error: Info: Writing sequencer/sequencer_auto.h ...Error: Info: Writing ../sequencer_auto_h.sv ...Error: Info: Microcode compilation successfulError: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGEError: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists.Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in ..Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE "Error: child process exited abnormallyError: Cannot find sequencer/sequencer.elf<html>Error: An error occurred<br> while executing<br>"error "An error occurred""<br> (procedure "_error" line 8)<br> invoked from within<br>"_error "Cannot find $seq_file""<br> ("if" then script line 2)<br> invoked from within<br>"if {[file exists $seq_file] == 0} {<br>_error "Cannot find $seq_file"<br>}"<br> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br> invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br> invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br> ("if" then script line 2)<br> invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br>set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br> (procedure "generate_qsys_sequencer_sw" line 943)<br> invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."<br> invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."<br> ("if" else script line 2)<br> invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br>set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br> invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"<br> invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {<br>set file_name [file tail $genera..."<br> (procedure "generate_synth" line 8)<br> invoked from within<br>"generate_synth DDR3C_s0"<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"Error: Generation stopped, 1 or more modules remaining<html>Info: Done "<b>DDR3C</b>" with 7 modules, 29 filesInfo: DDR3C: Generating simulation model<html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>" for SIM_VERILOG<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>"<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"Info: Generating clock pair generatorInfo: Generating altgpio<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormallyError: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failedError: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0Error: UniPHY Sequencer Microcode CompilerError: Copyright (C) 2020 Intel Corporation. All rights reserved.Error: Info: Reading sequencer_mc/ac_rom.s ...Error: Info: Reading sequencer_mc/inst_rom.s ...Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ...Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ...Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...Error: Info: Writing sequencer/sequencer_auto.h ...Error: Info: Writing sequencer/sequencer_auto.h ...Error: Info: Writing ../sequencer_auto_h.sv ...Error: Info: Microcode compilation successfulError: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGEError: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists.Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in ..Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE "Error: child process exited abnormallyError: Cannot find sequencer/sequencer.elf<html>Error: An error occurred<br> while executing<br>"error "An error occurred""<br> (procedure "_error" line 8)<br> invoked from within<br>"_error "Cannot find $seq_file""<br> ("if" then script line 2)<br> invoked from within<br>"if {[file exists $seq_file] == 0} {<br>_error "Cannot find $seq_file"<br>}"<br> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br> invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br> invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br> ("if" then script line 2)<br> invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br>set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br> (procedure "generate_qsys_sequencer_sw" line 943)<br> invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."<br> invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."<br> ("if" else script line 2)<br> invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br>set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br> invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG"<br> invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG] {<br>set file_name [file tail $generate..."<br> (procedure "generate_verilog_sim" line 7)<br> invoked from within<br>"generate_verilog_sim DDR3C_s0"<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"Error: Generation stopped, 1 or more modules remaining<html>Info: Done "<b>DDR3C</b>" with 7 modules, 21 filesInfo: Generated simulation scripts for Modelsim in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/mentor directory.Info: Generated simulation scripts for VCS and VCS MX in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/synopsys directory.Info: Generated simulation scripts for NCSIM in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/cadence directory.Info: Generated simulation scripts for Riviera-PRO in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/aldec directory.

author: BrianHG
author_rank: Super Contributor
timestamp: February 14, 2021, 12:36:04 am
content: Add in your title that it's for the 37$ Arrow Max10 DECA board as a few here have purchased them.Also, did you receive a CD with that board?Does it have a version of Quartus on it?If so, what version & date is it?Also, at Terrasic website, is there a download for the dev board?Since they say Win7 compatible, I may take a look, but Quartus has dropped Win7 support a few years back and I do not want to install 10 variants until I find the right one.Right now, 20.1 does work on my system, but according to Intel, there is no way I can get the DDR3 or NIOS stuff working unless I upgrade to Win10.

author: asmi
author_rank: Super Contributor
timestamp: February 14, 2021, 01:00:00 am
content: This problem also appears for Cyclone V, so it's not specific to the board or FPGA. The issue is with the wizard itself.No CD came with a board, there is a CD archive on Terasic website, but there is no Quartus at all.

author: BrianHG
author_rank: Super Contributor
timestamp: February 14, 2021, 01:06:16 am
content: Yes, I get the same error, no matter the chosen FPGA, when running the DDR3 memory generator.Only Nockieboy got it to compile correctly in Q20.1.I will look at the release date of the DECA board and get that version of Quartus to see if it works.

author: asmi
author_rank: Super Contributor
timestamp: February 14, 2021, 01:13:05 am
content: Well, let's see if he or somebody else has any more ideas as to how to get it to work.So far this kind of confirms that I made a right decision to move to Xilinx parts, as there stuff just works with no muss no fuss. And it's actually a fully-featured DDR3 controller, not time-limited crap Antel offers.

author: RoGeorge
author_rank: Super Contributor
timestamp: February 14, 2021, 01:44:48 am
content: There is a CD download from Terasic, DECA_v.1.0.1_SystemCD.zip, requires a registration to download. The CD doesn't have Quartus (it is only ~150 MB), just specific files for the DECA board and demos. The user manual says about running the examples with Quartus 14, 15, or 15.1 on WinXP or Win7, certainly not the latest Quartus.Couldn't find any license.lic file for the megafunctions IPs on the Terasic CD, so I think there is no particular free license for this board, just the generic Quartus.No idea how Linux for DECA board works (there is Linux for DECA and BSP files for the main hardware), still tethered to run longer than 1 hour?¯\_(ツ)_/¯

author: asmi
author_rank: Super Contributor
timestamp: February 14, 2021, 01:58:56 am
content: Quote from: RoGeorge on February 14, 2021, 01:44:48 amLinux on FPGAs is a waste of limited FPGA resources for very little gain IMHO. And in case of Antel you also need to fork out $$ for softcore as free version is useless garbage.

author: ale500
author_rank: Frequent Contributor
timestamp: February 14, 2021, 05:26:00 pm
content: In 15.1 the DD3 Wizard works, I used it with the Bemicro CV board. But not more than that, configuring the pins and all that was where I got stuck at :/, it has dedicated pins.

author: mattselectronics
author_rank: Contributor
timestamp: March 15, 2021, 03:10:51 pm
content: Do you have the Windows Subsystem for Linux (WSL) installed, in case you are running Quartus under Windows?That did cause some issues for me in the past.As far as I know, Intel switches from Cygwin to WSL in Quartus 19.There may be issues when WSL is installed with older Quartus Version, but of coures the newer ones need it.

author: ejeffrey
author_rank: Super Contributor
timestamp: March 15, 2021, 05:21:16 pm
content: I'm seeing "file not found" messages in those errors. I have seen bugs in quartus megafunction wizards related to branding changes from altera->intel where the megafunction creates tcl scripts referencing paths with "altera" in the name but the actual file path is "intel" or vice versa.

author: asmi
author_rank: Super Contributor
timestamp: March 15, 2021, 07:25:32 pm
content: Quote from: mattselectronics on March 15, 2021, 03:10:51 pmYes I do. I tried everything I could think of, but it's still

author: mattselectronics
author_rank: Contributor
timestamp: March 15, 2021, 09:37:57 pm
content: Which version of Windows are you running?It has to have WSL and WSL needs to be installed, otherwise it won't work with the DDR3 core.Other IP-Cores might work fine.

author: mattselectronics
author_rank: Contributor
timestamp: March 15, 2021, 09:44:31 pm
content: The first error occure, when some NIOS stuff is generated. Maybe there is an issue with the NIOS in your installation.As far as I know, the the DDR3 controller contains a NIOS.At work we have the uniphy IP runnig fine with Quartus 18.1. This is the last version without WSL, so make sure it is not installed, when you try this Version.

author: asmi
author_rank: Super Contributor
timestamp: July 07, 2021, 12:39:05 am
content: OK, I finally got to the bottom of this issue. The root cause was that I was using WSL version 2. Once I added a wsl version 1 linux distro and made it default, things started working just fine.

author: mrigoprecitec
author_rank: Newbie
timestamp: August 27, 2021, 08:34:48 am
content: Hi guys!So I had the very same issue with quartus 15.0.I have dug in and found out the culprit.As you can see in my process monitor screenshot, make is calling the bash command, which leads to spawning wsl, which is obviously false, as the cygwin bash should be called.So there is the file, if you have installed to the default location: C:\altera\15.0\ip\altera\alt_mem_if\alt_mem_if_tcl_packages\gen\uniphy_gen.tclIt generates a Makefile, which is looking like this on my side:Code:MC_MACROS := -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001001010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001101010000 -DAC_ROM_MR1=0000001000000 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0010000001000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000101001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010101000 -DAC_ROM_MR1_MIRR=0000000100000 -DAC_ROM_MR2_MIRR=0010000010000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1.PHONY : allall : hex.PHONY : hexhex : elfC:/altera/15.0/quartus/../nios2eds/bin/elf2hex --base=0x10000 --end=0x137ff --create-lanes=0 --width=32 --record=4 --input=sequencer/sequencer.elf --output=../CHRC_qsys_ddr3_control_s0_sequencer_mem.hex.PHONY : elfelf : setup$(MAKE) -C sequencer_bsp clean altera_nios2_qsys_hal_driver_ASM_LIB_SRCS=HAL/src/crt0.S hal_C_LIB_SRCS=HAL/src/alt_main.c hal_C_LIB_SRCS+=HAL/src/alt_load.c altera_nios2_qsys_hal_driver_C_LIB_SRCS=HAL/src/altera_nios2_qsys_irq.c altera_nios2_qsys_hal_driver_C_LIB_SRCS+=HAL/src/alt_icache_flush_all.c altera_nios2_qsys_hal_driver_C_LIB_SRCS+=HAL/src/alt_dcache_flush_all.c$(MAKE) -C sequencer clean all altera_nios2_qsys_hal_driver_ASM_LIB_SRCS=HAL/src/crt0.S hal_C_LIB_SRCS=HAL/src/alt_main.c hal_C_LIB_SRCS+=HAL/src/alt_load.c altera_nios2_qsys_hal_driver_C_LIB_SRCS=HAL/src/altera_nios2_qsys_irq.c altera_nios2_qsys_hal_driver_C_LIB_SRCS+=HAL/src/alt_icache_flush_all.c altera_nios2_qsys_hal_driver_C_LIB_SRCS+=HAL/src/alt_dcache_flush_all.c.PHONY : setupsetup : mcifeq ($(wildcard sequencer_bsp/Makefile),)C:/altera/15.0/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGEendififeq ($(wildcard sequencer/Makefile),)C:/altera/15.0/quartus/../nios2eds/sdk2/bin/nios2-app-generate-makefile --bsp-dir sequencer_bsp --app-dir sequencer --elf-name sequencer.elf --set OBJDUMP_INCLUDE_SOURCE 1 --set APP_CFLAGS_DEFINED_SYMBOLS -DSTACK_POINTER=0x137f0 --set APP_CFLAGS_OPTIMIZATION \"-Os --param max-inline-insns-single=1000 -fno-zero-initialized-in-bss\" --set APP_CFLAGS_WARNINGS \"-Winline -Wall\" --src-files sequencer.c sequencer.h tclrpt.c tclrpt.h sequencer_auto_ac_init.c sequencer_auto_inst_init.cendif.PHONY : mcmc :ifeq ($(wildcard sequencer_mc),sequencer_mc)C:/altera/15.0/quartus/bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../CHRC_qsys_ddr3_control_s0_AC_ROM.hex -inst_rom ../CHRC_qsys_ddr3_control_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c $(MC_MACROS)endif.PHONY : guigui : setupeclipse-nios2As you see it makes a call to this file: C:/altera/15.0/quartus/../nios2eds/sdk2/bin/nios2-bspWhich on the other hand starts with the shebang:Code:#!/bin/bashSo the solution is to modify this file: C:\altera\15.0\ip\altera\alt_mem_if\alt_mem_if_tcl_packages\gen\uniphy_gen.tclBy me it is line 3776Original:Code:puts $fh "\t$qdir/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE"Modified one:Code:puts $fh "\t$qdir/bin64/cygwin/bin/bash.exe $qdir/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE"We just added the part:$qdir/bin64/cygwin/bin/bash.exeto tell the makefile it should explicitly call the shell script via the cygwin shell.I think this method could possible be applied to all versions which suffer from the same problem because of an existing wsl installation.This makes a call to the 64 bit cygwin, so if you have winx64, it should work.Shame on intel, that their official support page does not give this exact workaround:https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/emif/2018/error--cannot-find-sequencer-elf.htmlCheers!

author: Mohammed
author_rank: Newbie
timestamp: March 20, 2022, 10:43:15 pm
content: Hello!I faced the same error while generating the HDL files of HPS-based SoC design in Platform Designer (Qsys), please find software details in below:- Quartus prime standard edition 21.1- Ubuntu version 18.04- WSL 1- Windows version: 10.0.19043.1466Command shell for Nios II is working normally.Error message: "Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally"Based on your discussion above, my system should works normally, but I am still struggling with this error. Any suggestion please?

author: betocool
author_rank: Regular Contributor
timestamp: March 20, 2022, 11:04:17 pm
content: I had the same issue. I contacted the Intel forum and got this:https://www.intel.com/content/www/us/en/support/programmable/articles/000074066.htmlWorked for me.Cheers,Alberto

author: Mohammed
author_rank: Newbie
timestamp: March 21, 2022, 11:24:14 am
content: Thank you very much for your response ...Please find the Quartus project including the Qsys design (ver 21.1) in the attached file.Can anyone please try to edit it in Qsys and generate the HDL files, thank you.

author: eofz
author_rank: Newbie
timestamp: April 19, 2022, 11:04:31 am
content: Hi Mohammed,(It's a little off the subject...), but , if you are facing the error withv21.1std in Windows OS, please try this patch:https://www.intel.com/content/www/us/en/support/programmable/articles/000088789.html?wapkw=16015124034This solved my issue.Thanks,

author: vstrakh
author_rank: Contributor
timestamp: June 16, 2023, 12:50:21 pm
content: The recommendation frommrigoprecitecsaved the day.I have exactly this "troublesome" setup, few different versions of Quartus on Windows 10, so WSL 2 will be there for newer Quartus versions, while the older ones will want to use Cygwin.Patching up uniphy_gen.tcl script to explicitly call Cygwin shell fixed the problem.

author: gordwait
author_rank: Newbie
timestamp: December 05, 2023, 11:04:56 pm
content: Just dropping in here to add a note. Under the hood WSL drops a version of bash.exe in c:\windows\system32 .This trashes many editions of Quartus (including my licensed 14.1 edition) - the dram compiler breaks.Even if you completely uninstall WSL, it leaves bash.exe there, but in this case that file just prints that WSL is not installed.So, if installing WSL breaks your older Quartus tools, it's due to the new bash.exe in system32. This is why the above tip about forcing the TCL file to specifically call the cygwin edition bash will help you.In my case I completely uninstalled WSL, and renamed the file in system32 to wslbash.exe to fix my old copy of quartus.