Variable frequency motor driver based on STM32 - Page 1
Forum section: electronics / projects

author: Danijel789
author_rank: Newbie
timestamp: December 31, 2017, 03:03:57 pm
content: Hi,I'm new to ARM development so I'm struggling with generating sine PWM signals.Idea is to have variable frequency and voltage driver for asynchronous motor in scalar mode, constant V/F. Maybe after successful implementation of scalar mode I could start with vector mode, but not for now.What I'm trying to do is generate six pwm pulses from microcontroller whose will control standard six step inverter with IGBTs.So far this is what I accomplished:This is output from STM32 pins. One of questions is why is output "chopped"(maybe timer's each step?), should it be constant?Here is output from two phases from inverter. Only two because of limitations of oscilloscope channels.My questions are how should outputs from STM32 look like? Constant signal or sine PWM for each 180°.How should inverter look like, should I use IGBT drivers? Seems like it would be bit simpler with them, but I've never used it.Is output from logic analyzer correct or not?I've tried to start small ac generator with this but nothing happens, only quite buzzing. Can it be run as motor anyway?Photo of generator in attachment.Also, here is the code:Code:#include "stm32f401xe.h"int cnt1=0;int cnt2=120;int cnt3=240;void TIM1_UP_TIM10_IRQHandler(void){if(cnt1==360){cnt1=0;}if(cnt2==360){cnt2=0;}if(cnt3==360){cnt3=0;}if(cnt1>=180){TIM1-> CCER |= TIM_CCER_CC1E;TIM1-> CCER |= TIM_CCER_CC1P;TIM1-> CCER &= ~TIM_CCER_CC1NE;}if(cnt1==0){TIM1-> CCER &= ~TIM_CCER_CC1E;TIM1-> CCER |= (TIM_CCER_CC1NE);TIM1-> CCER &= ~TIM_CCER_CC1P;}if(cnt2==180){TIM1-> CCER |= TIM_CCER_CC2E;TIM1-> CCER |= TIM_CCER_CC2P;TIM1-> CCER &= ~TIM_CCER_CC2NE;}if(cnt2==0){TIM1-> CCER &= ~TIM_CCER_CC2E;TIM1-> CCER |= (TIM_CCER_CC2NE);TIM1-> CCER &= ~TIM_CCER_CC2P;}if(cnt3==180){TIM1-> CCER |= TIM_CCER_CC3E;TIM1-> CCER |= TIM_CCER_CC3P;TIM1-> CCER &= ~TIM_CCER_CC3NE;}if(cnt3==0){TIM1-> CCER &= ~TIM_CCER_CC3E;TIM1-> CCER |= (TIM_CCER_CC3NE);TIM1-> CCER &= ~TIM_CCER_CC3P;}cnt1++;cnt2++;cnt3++;// Clear status registerTIM1-> SR &= ~(TIM_SR_UIF);// Clear update interruptTIM1 -> DIER &= ~(TIM_DIER_UIE);// Again enable interruptsTIM1 -> DIER |= TIM_DIER_UIE;}int main(void){// Enable TIM1RCC-> APB2ENR |= RCC_APB2ENR_TIM1EN;// Enable GPIOA i GPIOBRCC-> AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN;// CH1GPIOA-> MODER &= ~(GPIO_MODER_MODER8_0);GPIOA-> MODER |= GPIO_MODER_MODER8_1;// CH1 NGPIOA-> MODER &= ~(GPIO_MODER_MODER7_0);GPIOA-> MODER |= GPIO_MODER_MODER7_1;// CH2GPIOA-> MODER &= ~(GPIO_MODER_MODER9_0);GPIOA-> MODER |= GPIO_MODER_MODER9_1;// CH2 NGPIOB-> MODER &= ~(GPIO_MODER_MODER0_0);GPIOB-> MODER |= GPIO_MODER_MODER0_1;// CH3GPIOA-> MODER &= ~(GPIO_MODER_MODER10_0);GPIOA-> MODER |= GPIO_MODER_MODER10_1;// CH3 NGPIOB-> MODER &= ~(GPIO_MODER_MODER1_0);GPIOB-> MODER |= GPIO_MODER_MODER1_1;GPIOA-> MODER |= GPIO_MODER_MODER3_0;GPIOA-> MODER &= ~(GPIO_MODER_MODER3_1);GPIOA-> AFR = 0x111;GPIOA-> AFR = 0x10000000;GPIOB-> AFR = 0x11;TIM1-> PSC = 0;TIM1-> ARR = 360;// Capture compare registerTIM1-> CCR1 = 180;TIM1-> CCR2 = 180;TIM1-> CCR3 = 180;// Capture compare mode register 1TIM1-> CCMR1 |= TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1PE | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2PE;// Capture compare mode register 2TIM1-> CCMR2 |= TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3PE;// Master out enableTIM1-> BDTR |= TIM_BDTR_MOE;// Counter enableTIM1-> CR1 |= TIM_CR1_CEN;TIM1-> EGR |= TIM_EGR_UG;TIM1 -> DIER |= TIM_DIER_UIE;NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0);while(1){}}I've been busting my brain for days and can't move on from here. Any help would be welcome and appreciated.Thank you.Microcontroller: ST NUCLEO-F401REIGBT: RJP4301

author: max_torque
author_rank: Super Contributor
timestamp: December 31, 2017, 03:49:26 pm
content: Google "Centre Aligned PWM"By generating 3 centre aligned pwm signals you get 6 "edges". For a zero output voltage all 3 pwms are set to 50%, and because they are all aligned, all 3 outputs sit at your zero v rail and then at your +ve rail simulataneous, so the voltage diff between the outputs is also zero.By modulating the (Google: space vector modulation) 3 pwms away from 50% you generate your sinusoidal output voltages between phases