Port pin sometimes reads wrong after slow rising input has settled - Page 1
Forum section: electronics / general

author: Circlotron
author_rank: Super Contributor
timestamp: August 17, 2022, 10:29:59 pm
content: Been using a 9S08FL micro with several port pins driven from the outside world via an RC network that gets to +5V in about 10mS. At power up there is a 50mS delay before the pin is read to make sure the RC is fully settled. Mostly it works just fine but on two occasion in maybe several hundred power ups the pin appears to be read as a low instead of a high. I know that slow moving inputs are not a good thing because there can be an uncertainty at the transition point, but the pin is read well after it has gone high. Scope has verified this. Could the slow rise cause the input buffer to be put into some kind of weird state before it gets read?

author: srb1954
author_rank: Super Contributor
timestamp: August 17, 2022, 11:12:15 pm
content: Quote from: Circlotron on August 17, 2022, 10:29:59 pmThis sounds as though it could be a metastability problem in the input logic or the input circuitry could be oscillating as the slow rising input voltage transitions through the logic threshold voltage.Some of the 9S08 chips have synchroniser circuits on the input pins, which will clock the input signal through several flip-flops to ensure that a validly timed signal is presented to the processor core. If you a have a slow rising input signal that passes through the logic threshold voltage at or about the same time as the clock signal then the flip-flop can get stuck in a metastable state where the internal circuit nodes of the flip-flop are neither in a logic 0 or logic 1 state but temporarily stuck half way in between. Eventually, the flip-flop nodes will resolve themselves to proper logic levels but that may be at the wrong logic sense compared to what it should have been.A similar situation exists if the input circuitry is oscillating during the transition through the threshold voltage. The synchroniser may again get stuck in the incorrect logic state depending on the exact timing relationship between the sampling clock and the input signal transitions.I suggest you read up the reference manual for the processor to fully understand the input circuitry structure and follow that up with some research on metastability problems. The problem of metatstability is not often covered in digital design courses but it is always a problem when clocking asynchronous signals signals into synchronous circuitry. It can't be entirely eliminated but the probability of an error can be reduced to acceptably low levels by suitable circuit design techniques.

author: Circlotron
author_rank: Super Contributor
timestamp: August 18, 2022, 12:36:37 am
content: Thanks for that srb1954. I know one proper solution would be to have a schmitt trigger between the RC and the port pin but there's not a lot of board space left so I'd much much much rather find some kind of software solution. Plus the expense of a revised board. Would it make any difference if I read the port pin multiple times and took what the majority of the read states were? Although if the synchronizing flipflops have already (erroneously) decided on a state I suppose that wouldn't make much difference. What if I momentarily configured the input to an output and back again? Would that reset the state of the synchronizing circuitry? I haven't yet found anything describing the IO circuitry in any worthwhile detail.

author: Circlotron
author_rank: Super Contributor
timestamp: August 18, 2022, 01:39:21 am
content: Maybe a fix might be to use the A/D function and read the analog voltage presented to the pin and if it's > 75% of Vdd then call it a 1, less than 25% call it a 0. If in between those limits then something else is way wrong anyway.

author: srb1954
author_rank: Super Contributor
timestamp: August 18, 2022, 02:34:21 am
content: Quote from: Circlotron on August 18, 2022, 12:36:37 amEven if the flip-flop has gone into a metastable state it should eventually resolve itself to an operational state when the node voltages on the flip-flops slowly drift back to their normal operating range. This may take some time, us or even ms, and then a few more clock cycles should restore normal synchroniser operation.I would just do a S/W fix and treat the input as though you were debouncing a noisy switch and keep taking S/W samples at several ms intervals until you see a stable, unchanging state over >3 samples.If you have the opportunity for a H/W fix then a Schmitt trigger would be a good idea to provide a fast clean input signal to the chip. Also check the supply rails to the chip are clean and well bypassed; noise on the supply rails can affect the threshold voltages of the CMOS gates and make them prone to oscillation when presented with a slow input signal.

author: pgo
author_rank: Regular Contributor
timestamp: August 18, 2022, 12:03:59 pm
content: Hi,I find the situation you describe very strange.The MC9S08Fl has digital input hysteresis of about 0.6 V (from my reading of the data sheethttps://www.nxp.com/docs/en/data-sheet/MC9S08FL16.pdf) so it is unlikely to oscillate even on a slow changing input.Metastability is also unlikely as it is associated with changes near a clocking point and realistically would only persist for a short time before being resolved (nanoseconds!) by the input pin synchronizing circuit.Are you sure the input range is not being exceeded during power cycle - maybe latchup? but I would still be skeptical.Based on my personal experience I would suspect a software problem - I have been caught with impossible situations which have eventually been tracked to a problem caused by a coding error.Check that the port is being initialized correctly every time etc.Sorry - not much to suggest other than negatives.bye

author: Circlotron
author_rank: Super Contributor
timestamp: August 18, 2022, 12:32:14 pm
content: Quote from: pgo on August 18, 2022, 12:03:59 pmThe only reference I can find to hysteresis is for the reset pin. What paragraph did you see that?

author: pgo
author_rank: Regular Contributor
timestamp: August 18, 2022, 03:31:57 pm
content: Page 12Sorry I said 0.6V - My maths isn't that good ~.3V (but the line says mV so it may mean .0003V but that seems silly).

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 19, 2022, 01:30:42 am
content: Quote from: Circlotron on August 17, 2022, 10:29:59 pmSounds unusual for any MCU.Does the pin eventually read correctly ? Or is it stuck wrong forever ?If it eventually corrects, maybe your relative delays are not what you expect ?Are any other pins driven outside the rails - you can get lateral currents in that case, which can disturb adjacent pins if they are Hi Z or Analog.You could experiment by adding code that catches the unexpected state and then dump reports a group of pins, and try some 'pin shaking' of pulse lo/hi as output for a very short time.

author: srb1954
author_rank: Super Contributor
timestamp: August 19, 2022, 03:05:53 am
content: The OP said that the RC delay was about 10ms and the pin state was read after 50ms so there was at least 5 time constants worth of settling time which should have more than ample to allow the signal to settle.

author: Siwastaja
author_rank: Super Contributor
timestamp: August 19, 2022, 05:39:05 am
content: Not metastability. Something unexpected is going on. Do yourself (and us!) a favor and collect a dataset: sample the pin once every 1ms or so, collect to a large table over hundreds of samples, and output it to UART or similar. Then we will see what is happening.If you have ADC available on that pin, configure it to analog mode and repeat the measurement (a different run) with analog voltages logged instead. You can align the two plots side-by-side.