Idiot's guide to bus termination? - Page 1
Forum section: electronics / beginners

author: Unknown
author_rank: Unknown
timestamp: July 28, 2015, 06:04:12 pm
content: I've been playing around with board layout strategies for the 6502 SBC project, and it occurred to me that this is something I may need to consider.So far, the easiest/neatest layout I could come up with was to lay out the data/address/control lines horizontally across one layer, from one end of the board to the other, in bunches so I can place the wide DIP packages over the top. The underside of the board has vertical traces tying the device pins into the bus where they need to go. So far, so good - piece of piss to route neatly and I have loads of space left over before I exceed the board area I'm willing/able to pay for.(Sorry for lack of pictures at the moment, hopefully my description is reasonably clear).Then I got to thinking "this is so simple it can't possibly be correct/good technique", so I read a bit on termination. Knowing precisely nothing about transmission line theory all I got from that was "stubs/open ended traces are bad, passive termination with resistors is also not wonderful but better than nothing".A search for active termination led me to these:http://www.ti.com/product/sn74s1051My current thinking is: Place as many of those as I need at one end of the board, have my 41612 connector at the other, and do exactly as I have been doing in the middle, and hope all will be well....Am I close? Do I even need to worry that much with CMOS parts that probably won't see more than a few MHz? I'm quite some way from the manufacturing stage at the moment but I really would like to get it right first time.

author: SeanB
author_rank: Super Contributor
timestamp: July 28, 2015, 06:28:17 pm
content: For a 6502 you really do not need to worry much about termination, provided the trace length is not too long ( around 10-15cm max) as the reflections will die down before the bus changes state. However you can add passive pull up resistors to the address lines ( around 4k7) to pull up the bus to some defined level when it is tristated during the inactive parts of the bus cycle. Best though is to have some octal bus buffers on the address lines, where you can leave them active all the time, and on the data bus where you will have to use the RW line to determine direction, so that the CPU does not have to drive long lines with it's weak low power drivers. Same on the control lines, just to increase fan out of those lines. 4 extra chips right next to the CPU, each decoupled with it's own 100n ceramic as close to the chip as possible and with a 10uF 16V low ESR electrolytic close to all 4 as well.

author: mazurov
author_rank: Frequent Contributor
timestamp: July 28, 2015, 06:34:49 pm
content: You can also add ~10 ohm resistors in series with fast signals if you have any (10 ohm resistors and/or fast signals). It is unlikely to change anything for this particular processor but you will radiate less.

author: Unknown
author_rank: Unknown
timestamp: July 28, 2015, 06:43:52 pm
content: Thanks for the info! So, 74HCT245s are needed thenI have seen that technique used a lot on older CPUs, wasn't sure if it was necessary or not for the 65C02. But, it adds next to bugger-all to the BOM and complexity. If that's all that's needed to keep things stable at a few MHz, then that's great.The purpose of the project is to have something nice to put in my "look what I can do!" portfolio when I can apply for better jobsSo, it has to 1) actually work, and 2) look the tits, with no ugly autorouted right-angles. I can wind the clock down as far as need be for it to function, but it must still look as though I have some clue what I'm doing!I'm rather hoping that the attitude of "here's what I do for fun, imagine what I'll do for a paycheck" will pay off one day... but that's a topic for another thread.

author: SeanB
author_rank: Super Contributor
timestamp: July 28, 2015, 07:02:44 pm
content: Woz did some very weird things when he designed the Apple ][', which did result in needing to make sure you had the right parts to fix it. Some would not work with LS logic from certain manufacturers due to timing issues, or you had some production line bodges of RC networks to delay signals when the parts were improved with faster switching, or you had to cut as trace then add a wire from another point to delay a signal so it would not cause a race condition. Thern again some of the bus lines had massive overloads on them, recommended load is 10 TTL inputs and some would have 20 or more inputs driven, though the saving grace was the slow timing and the NMOS outputs being able to eventually pull them to ground and to 5V in each cycle, along with most LSTTL running at a lower than max input bias current out of the input pins.If you want power hogs use standard F TTL, or plain S. Those run hot enough to be almost too hot to touch even sitting idle. Fastest is ALS, it runs faster than the first generations of ECL.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 28, 2015, 09:53:28 pm
content: Better to check on source termination, and verify any edges you need.The 6502, is that CMOS or NMOS, and how strong are the output drivers? NMOS of that era, I believe, was usually 5V supply, TTL compatible, with a fairly low fanout. And CMOS was symmetrical drive (inputs might not be TTL compatible, outputs meet/exceed TTL spec), but also quite weak.If you want to put that on an extensive bus (like a card cage), you'll have to use bus drivers / transceivers, using bus signals to drive them appropriately. The bus state signals themselves will need to be buffered of course, which may be a challenge if you want to include multi-master modes. (The usual solution is to use open-collector signals.)I wouldn't recommend using anything faster than 74HC(T). You're only inviting trouble if you use AC, F, ALS, etc. Most of the value will be wasted, anyway, because you'll probably need to series-terminate their extra-strong outputs. HC is about right with an extra 33 ohms in series, given the impedance of most traces.For layout, you'll preferably want 4 layer build, with outer layer traces around 100 ohms (typically 6-7 mil width over 10 mil prepreg). Since that costs extra, you might stick with 2 layer, in which case, try to route as much bus as possible over solid ground plane. Use somewhat heavier traces (10-20 mil), with similar or greater spacing to reduce crosstalk, and make bus crossings as well grounded as possible (when crossing a bus on one layer, try to surround single traces (or no more than a few abreast) with ground plane on the opposite layer, well stitched to the surrounding ground on both sides).When using ribbon cable, ground every other trace. The impedance of any given pair of wires is about 120 ohms (differential), and one wire against two neighboring grounds is about 50 ohms. You'll probably want to use bus drivers in front of such a cable, since it won't match to system impedance (i.e., ~100 ohms). You definitely don't want to run an entire bus in adjacent wires, because that 120 ohm figure becomes coupling and crosstalk between neighboring wires -- sure to make a mess.You can minimize or avoid a lot of trouble if you allow enough time for signals to settle before the strobe events occur. Typically, this is already provided, so the CPU (or other device) asserts an address (and optionally, data), then some clock states later, asserts the bus strobe (RD, WR, IO, direction, whatever). If you have any edge-triggered devices, you need to make sure the strobe is very clean (this is a big gotcha for newbies to SPI, which depends critically upon the clock signal). You can relax it a bit if devices are asynchronous and level-triggered only (e.g., using 74HC373s over 273/374s), so that the address/data stays stable during the strobe (which might be multiple strobes due to bounce, but it doesn't matter).You also want to have twice the total bus length (end to end and back again) less than a clock half period. Figure speed of light about 0.67c (in PCB, coax, ribbon, etc.). Close enough. This is the most powerful consideration, because at the low clock rates old machines ran at, you can simply have ribbon cable piled out of the bus and not really care, even with the impedance mismatch.Tim

author: Gyro
author_rank: Super Contributor
timestamp: July 29, 2015, 12:16:23 pm
content: QuoteReminds me of the Sinclair ZX81 where he used series resistors to avoid bus contention between the Z80 and ULA and pullup resistors to simulate NOP instructions as part of the software derived video output timing. It shows how many liberties you could take with those slow buses.... On a small board that is!

author: Unknown
author_rank: Unknown
timestamp: July 29, 2015, 12:50:56 pm
content: FWIW I'm looking at a board area of no more than 10cm*20cm, So individual trace lengths should not exceed 15cm. The plan is to use WDC's CMOS 65xx CPU/peripherals, 74HC bus drivers as recommended earlier, and a couple of ATF16V8s (because I just can't be arsed routing discrete logic address decoding, and I recently discovered Proteus can simulate them... makes life about 10% easier)T3sl4co1l, great info thereVery useful indeed and next time I do a practice layout I'll work that advice in as best I can and see how it goes. It's nice to try and understand WHY things are the way they are. There's only so much I can learn from looking at existing designs (retro computer motherboards and such) and just trying to copy it!

author: tggzzz
author_rank: Super Contributor
timestamp: July 29, 2015, 02:33:24 pm
content: Quote from: BulletMagnet83 on July 28, 2015, 06:04:12 pmClock rate is relatively unimportant. Edge rate is very important, and some modern CMOS families have sub-nanosecond edge rates.Understand thesehttp://www.edn.com/collections/4435129/Bogatin-s-Rules-of-Thumbrules of thumb. Numbers 1 and 18 are directly relevant.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 29, 2015, 03:17:15 pm
content: Quote from: BulletMagnet83 on July 29, 2015, 12:50:56 pmWhat's worse is, often they didn't give much care either... there was that computer Dave looked at some time ago (I forget if it was a Spectrum?) with two layers, no ground plane... they had to wrap the poor thing in metal shielding to meet EMC. What horrors if you actually scoped the thing? Or all the pin drivers were painfully weak and slow, and there wasn't anything to bounce.Tim

author: Moshly
author_rank: Regular Contributor
timestamp: July 29, 2015, 03:58:44 pm
content: Hi, there is a ton of info on6502.organdhttp://forum.6502.org/Also check out -> (all the bus stuff you need to know)http://wilsonminesco.com/6502primer/index.htmlLots of Commodore 8Bit schematics at -> (for circuit ideas)ftp://www.zimmers.net/pub/cbm/schematics/