Thought experiment: PCI Express Splitter - 1x16 to 2x8 - Page 1
Forum section: electronics / projects

author: faekjarz
author_rank: Regular Contributor
timestamp: February 28, 2017, 04:20:24 am
content: Hey there, beloved enginerds!I'd like to research the feasibility of a low tech conversion of a PCI Express 16x slot on a motherboard into two 8x slots. This thought experiment is about a low tech approach, i.e. electrical re-wiring only. In this scenario, there is a sufficient amount of lanes, so no lane switching (PLX) or active host bus adaptery bridge type circuitry required.An example:have two ofthose PCIe 16x extenderssever 8 lanes from the 1st one and connect them to the receptacle on the 2ndthen add power supply to the 2nd one, e.g.this specimenDone! Run two devices, with 8 lanes each, on one 16x slotDiscussion:Does one lane "know", that it is grouped together with 15 / 7 / 3... others?Can PCIe lanes, already grouped together in a finished product, be re-grouped "willy nilly"?Why could that experiment fail, will it?How about splitting 16x into 16 1-laners, same deal right?

author: DaJMasta
author_rank: Super Contributor
timestamp: February 28, 2017, 08:11:41 am
content: I don't know much about the spec, but my concerns would be:Regrouping may be possible if the lanes and the power connectors are all that are present in a connector, but it also may be defined by the BIOS/EFI, so even if you successfully physically hack it, you may have to hack some software too. The issue being at the protocol level, is there a method of just checking every individual lane for a device and dynamically grouping them? My guess is probably not, it probably needs some sort of firmware level configuration or has a dedicated pin for reading this info out or hardwiring it into a socket/board.The other concern would be signal integrity. Yeah, these extenders exist, but the reality is that you're running a whole bunch of very high speed data lines in parallel next to each other.... there will be crosstalk, there will be some degree of signal loss, and there will probably be increased EMI in the case after your mod.... whether it will make things stop working, hard to say. If you find a way to do it and go ahead with such a mod, I would definitely try forcing PCIe 1.0 standards initially, as that limits the data rate and should be less sensitive to signal degradation issues.There is probably at least some of this available looking at the PCIe specification data. It's also worth noting that there are a lot of motherboards available and you can probably find one to suit your desired configuration for a decent price.

author: TiN
author_rank: Super Contributor
timestamp: February 28, 2017, 08:38:34 am
content: You going nowhere with this, because PCIe is point to point topology. Meaning that you need to have logical "root" port connected to the device. This is handled by presence pins which connected to GPIO/PCH to tell MB BIOS to configure CPU PCIe controller as multiple separate controllers. If you split lanes physically but CPU controller still is combined larger root complex - result will be detected first device with degraded lanes (as split lanes are not connected anymore), and no device connection for second device. You also need to pass 100MHz clock signal from same platform clockgen (PCH or onboard buffer) and presence.So in short, it's too much work unless you exactly know how PCIe logic is handled in BIOS/your motherboard, which is not public and vary a lot from board to board.Why you need this?

author: Howardlong
author_rank: Super Contributor
timestamp: February 28, 2017, 08:55:45 am
content: I bought one of these for a project, but have yet to use it.https://www.amazon.co.uk/gp/product/B016C4ZOJE/ref=oh_aui_search_detailpage?ie=UTF8&psc=1You will need some electronics to do the PCIe bifurcation. There's a thread about it here:https://www.eevblog.com/forum/beginners/pcie-lane-switching/

author: faekjarz
author_rank: Regular Contributor
timestamp: February 28, 2017, 03:42:01 pm
content: Quote from: TiN on February 28, 2017, 08:38:34 amI don't reallyneedthis. It's a thought experiment, aimed at general learning and gaining market / tech intel: what type of products could be existing, at what cost. A PCIe board with two (or more) mini PCIe sockets for instance (with broken out pin headers for WLAN / WWAN activity LEDs, of course) ...haven't found one, yet. Based on my, now extended, but still limited knowledge, such a board would probably be feasible - dual mPCIe for <50€$, +~20€$ per additional mPCIe. Can't help it, i just love niche stuff like that.Quote from: Howardlong on February 28, 2017, 08:55:45 amYes, i came across those on AliExpress. Thanks for pointing out the bitfurcation issue / thread.

author: kc8apf
author_rank: Regular Contributor
timestamp: March 02, 2017, 06:29:53 pm
content: Yes, PCIe x16 can be passively bifurcated to 2 x8s. My work does it all the time. As others have mentioned, BIOS/EFI needs to know how to configure the lanes. The PCIe spec doesn't include any official way to make this happen so it requires some cooperation from the motherboard and BIOS vendors. At work, we route GPIOs to reserved pins on the x16 slot and modify our EFI to check those to decide if it should be 1 x16, 2 x8s, or 4 x4s.Sent from my K88 using Tapatalk

author: Twoflower
author_rank: Frequent Contributor
timestamp: March 02, 2017, 08:01:51 pm
content: It depends :-)First: The individual links on a PCIe are not independent. The root-complex or switch needs to collect the data from all active lanes and reorder them. Each lane sends one byte. For example if you want to transfer 16Byte on a x16 link each lane transfers one byte. While on a x8 each lane sends 2 bytes.To align the data it needs to know the number of the links and which links belong to the connection. It's correct that a x16 link must be able to go down x8, x4 and finally x1 (Note: x32 links are also specified). But this happens during the link training and both ends are aware of this. That happens either at power on. This is the reason why you can put a x1 card into a x4 slot. If I remember right, there is also some out-of-band signalling that needs to be taken care of if you split the PCIe link. But this can probably ignored as it is not widely used. You could get trouble at higher layers too (power negotiation, enumeration of the endpoints, ...). While it could be possible that some kind of auto-detection is possible I doubt that this exists.Some root-complexes in processors allow splitting the x16 into two times x8. It is used if you want to use more than one graphics card in your system. And: It needs to a) configured in the BIOS/UEFI and b) the lanes needs to be connected accordingly. In early days the 'Switching' was done by a PCB that contained the high speed lanes in two configurations. Depending the orientation of this PCB you had the electrical connections for one time x16 or two times x8. Nowadays the signals can be cheaply switched by multiplexers.If not supported, this splitting of one big PCIe into smaller ones need an active element Which even provides several x16 links connected to one x16 connection. Of course in this case you can't get full speed at the same time to each end-point. These switches are highly flexible and allow usually all kinds of splitting. But I doubt you're totally free selecting which lanes belong to which link: The individual links needs probably to be side by side to allow the switch to collect the data.