frequency counter design - Page 1
Forum section: electronics / projects

author: ealex
author_rank: Frequent Contributor
timestamp: September 29, 2015, 08:30:47 am
content: HelloI am trying to make a frequency counter from scratch - as a fpga exercise and hopefully to get something like a finished product.The design will use a Lattice XP2 fpga ( dev. on the brevia board ) for the measuring device and some sort or arm micro for everything else - UI, PC interface, etc.The high speed stuff is adapted to verilog from hamsterworks nice examples:http://hamsterworks.co.nz/mediawiki/index.php/High_Speed_Frequency_CounterI plan to have, on the same FPGA the following features:4 independent direct frequency counters - working and tested up to 400MHz, theoretically should work up to 851.789 MHz according to the place & route report2 independent reciprocal frequency counters ( period and duty) that have a reference of 200MHz derived from the input reference clock - working and tested1 counter that will be able to measure the phase for rising and falling edges using the inputs of the 2 slow counters - not yet started.SPI interface - easy to implement, in progress, waiting for testsThe main problem is the front-end, I don't know where to begin.I'm looking athttp://lea.hamradio.si/~s53mv/counter/frontends.htmlfor a starting point.Also, figure 1 fromhttp://www.westmountainradio.com/pdf/Article_Fernandes.pdfI plan to use a HMC434 as a /8 prescaler for the high speed channels and then the front-end designed by the user c4757p for the high-impedance, low frequency stuff, or copy part of the DS1052 front-end, as schematics are already available, and i might be able to understand them.I don't know how to use both front-ends on the high frequency inputs - design them as plug-able modules, but the mechanical part is way over my head.Another way is to have both of then on the PCB and have a relay switch the fpga pin from the prescaler to the comparator - single ended in this case. This will have the disadvantage of requiring 8 BNCinputs for the 4 high speed channels. 4 extra BNC's might be cheaper than the needed RF relays.Another way will be to have the high impedance module as a plug-in in front of the 50 ohm input - so it's output goes via the RF amplifier and prescaler - i don't know if it will work. Also it will require an extra connector for power supply and trigger voltage / SPI line for the ADC.Any ideas on how to start on the analog section ?I will add the verilog stuff later on today

author: dom0
author_rank: Super Contributor
timestamp: September 29, 2015, 05:24:02 pm
content: QuoteHonestly that doesn't make a lot of sense. For a frequency counter one channel is usually fine and two channels (at once, e.g. ratiometric measurements) are already quite rare to need. IMHO it would make much more sense to make it measure faster and resolve more digits in less time (e.g. by using a poly-phase reference clock and as many reference counters as you have clock phases). Also note that you can do ratiometric frequency measurements even in a one channel design, if the reference clock frequency isn't fixed to a small range by other components in the ref clock path (e.g. PLL/DLL).As for the front end, I don't know much about the RF stuff. But for lower frequencies (~0 - 50 MHz maybe) you really want a frontend that a) gives you about 1 M? || 20-40 pF input impedance b) is sensitive (few mVrms should give a reliable trigger) c) has an attenuator (because sensitivity isn't always advantageous) d) has switchable high/low pass functionality (fc, for example, 50 or 100 kHz).

author: Kleinstein
author_rank: Super Contributor
timestamp: September 29, 2015, 06:11:51 pm
content: Often a separate input is easier than an relay to switch the signal internally. Also different inputs might use different connectors. Usually there are not that many different types of input:1) high impedance (1 M 20 pF - just like a scope, so you can use the same probes), AC coupling optional2) low Z (50 Ohms) input without prescaler3) high frequency imput (50 Ohms) with prescaler, usually high sensitivity AC onlyOther special inputs may than be external or an optional module if really needed. Just leave some space and FPGS inputs in case you need another imput later. A second input might be usefull for doing start / stop measurements. So not strictly frequency counting, but more like a stopwhatch.Usually the high Z input should also have adjustable trigger level(s), attenuation, indicator LEDs and possibly other features, like filter, peak/peak measurement. Control via DAC / ADC is more likely from the µC, not the FPGA. I would not mind having the inputs on separate boards, especially those that might need a few iterations. Circuit diagramms of older HP counters are available and might be used for inspiration.I would also prefer higher resolution timing over extra conventional counters. The signal frequency the reciprocal counter must handle directly must not be that high - some kind of internal prescaler (or data decimation) can be used.

author: KJDS
author_rank: Super Contributor
timestamp: September 29, 2015, 06:55:06 pm
content: Consider one of these for the high frequency high sensitivity input.https://www.hittite.com/products/index.html/category/275

author: awallin
author_rank: Frequent Contributor
timestamp: September 29, 2015, 07:04:51 pm
content: SR620http://www.ko4bb.com/manuals/62.78.147.191/SR620_Universal_Time_Interval_Counter_Schematics.pdfp10 has the input stage I think.HP 53132Ahttp://literature.cdn.keysight.com/litweb/pdf/5989-6308EN.pdf?id=1119025page18Fluke 6690http://assets.fluke.com/manuals/6690____smeng0000.pdfp29 block diagram. schematic p157 for example.these universal counters need to measure from DC (e.g. PPS pulses) up to maybe 200MHz so making both a sensitive and wide-bandwidth input amp that is low noise might be challenging.if you tailor the input stage to one type of signal you could maybe do better.I'm interested in fpga based time-stamping counters (i.e. coarse counter + delay-line type time stamping). If anyone else wants to work on this it might be worth collaborating!

author: ealex
author_rank: Frequent Contributor
timestamp: September 29, 2015, 07:45:31 pm
content: The professional stuff looks complicated ... way over what i can manageThat many channels are too much, but i can still find useful at least 2 HF channels - playing with RF mixers for example, or PLL's.It would be easier to have 2 channels dedicated to RF stuff - 50 ohm, prescaler, etc and 2 channels with high impedance. This way i will get away without switching input stages, etc and could internally connect the 2 high impedance stages to 4 fpga pins.For the reciprocal counters - i will start reading on how to improve them - poly-phase reference clock : as rigol is doing in the DS1052 scope ? I might be able to get the PLLs to generate at least 2 phases, i don't know if more are possibleI can't imagine now a way to combine data from 2 counters that are delayed by 180 degrees - need to write it down and studyAlso, leaving unused pins available on headers will be useful.Another idea is to have the programming pins tied to the main mcu - so the fpga can be reconfigured at run-time without a jtag adapter.I will finish the control interface in the following days and start reading on front-ends and reciprocal counters.Once i have some basic working hardware i can start improving the FPGA part.

author: ealex
author_rank: Frequent Contributor
timestamp: September 29, 2015, 08:02:19 pm
content: interesting read:https://www.febo.com/pipermail/time-nuts/attachments/20071201/e7833af5/attachment.pdfandhttp://rubiola.org/pdf-slides/2012T-IFCS-Counters.pdf

author: BloodyCactus
author_rank: Frequent Contributor
timestamp: September 30, 2015, 12:32:20 pm
content: you should check out the silicon chip project;part 1http://www.siliconchip.com.au/Issue/2012/December/A+2.5GHz+12-digit+Frequency+Counter,+Pt.1?res=nonflashpart 2http://www.siliconchip.com.au/Issue/2013/January/A+2.5GHz+12-Digit+Frequency+Counter,+Pt.2?res=nonflashpart 3http://www.siliconchip.com.au/Issue/2014/July/L-o-o-o-n-g+Gating+Times+For+The+12-Digit+Counter?res=nonflash

author: ealex
author_rank: Frequent Contributor
timestamp: September 30, 2015, 01:31:21 pm
content: HelloI've managed to get the SPI interface working - i can configure the capture window and get data from the counters.I will use the "HF_frontEnd.pdf" type of front-end for the 50 ohm HF inputs.In "freqCounter - Copy.zip" you can find the current verilog design files.For the high-impedance input, i'm looking at Agilent 53132A schematic, attached as "LF_front_end.pdf"It's quite similar to the DS1052, but more complicated.A question regarding the future PCB layout - should i try to use the dedicated clock pins for the direct counter inputs ? the FPGA has ~ 7 dedicated clock inputs, on all edges. For now i'm not really taking care, and it seems it can meet the timing constraints

author: ealex
author_rank: Frequent Contributor
timestamp: October 01, 2015, 06:53:46 am
content: I forgot to attach the 2 pdf's. Fixed now.Also, after reading the Agilent documentation i realized i was over complicating stuff.A good trigger unit and some very fast and simple counter + software processing will be way more useful than some complicated counters that try to do everything.I'm starting to redesign the direct counters : 1 shot and will restart measurement only when triggered by the CPU, now they are continuously counting.

author: ealex
author_rank: Frequent Contributor
timestamp: October 01, 2015, 01:16:16 pm
content: Update:- the high speed counters are 1 shot- the cpu can trigger a new HS measurement via a specific SPI command- the status of the HS counters is available via a "status" SPI command - busy / done and overflowNext:- modify the reciprocal counters to simple up-counting units with enable and clear- create a trigger unit that will cover most of the available modes described in agilent "counter manual"http://www.leapsecond.com/pdf/an200.pdf- create a mux unit that will connect the enable / clear signals of each dumb counter to the trigger unitThis way those counters will be able to run at 400MHz, or as fast as i can make the trigger logic to run and all extra processing can be done in software

author: alank2
author_rank: Super Contributor
timestamp: October 01, 2015, 03:28:32 pm
content: For something simple, what about something like a MAX997? It says it has a propagation delay of 4.5ns, so would that mean a full cycle would take two of those for 9ns and be able to handle 111 Mhz? Could I use a pot to set the trigger level for the "IN-" and feed the signal to "IN+" ?

author: Kleinstein
author_rank: Super Contributor
timestamp: October 01, 2015, 05:11:58 pm
content: Propergation delay is not directly connected to the maximum frequency. This is just the delay of the signal. However the upper limit of about 100 MHz is reasonable, about the right order of magnitude. In principle it's signal to one side of the comperator and a ref. level to the other input. To get some hysereses 2 comparators are helpfull.However these fast comparators need some protrection / impedance converter at the input. The input is not all high impedance. So a circuit like the input stage of a scope is very helpfull here in the simple form this is a kind of source follower with a fast JFET.The linked Fluke example above is not much more.

author: ealex
author_rank: Frequent Contributor
timestamp: October 07, 2015, 07:17:54 am
content: finally had time to write and somewhat test the trigger unit.Basically it just handles all possible combinations of rising and falling edges.Each of the low speed channels can be triggered independently from any combination -> a lot of trigger detectors.I need to work on the configuration part - muxing and pushing signals between clock domains.Also, not yet added - a 'soft' reset for the trigger units, now they are only reset by the global system reset line (dedicated hardware)The fpga i have is getting crowded - most of the delays are becoming routing delays. Now the LS counters seem to run up to ~350MHz( forum admin : add .v files to the allowed list ... )