Article about one of my projects written up in EET blogosphere - Page 1
Forum section: electronics / projects

author: asgard
author_rank: Regular Contributor
timestamp: October 06, 2015, 08:35:10 pm
content: Here is a URL for the article, "Implementing a multi-peripheral controller using a tiny mixed-signal FPGA".http://www.bifrost-group.com/ee-times-designline-blog-articleImplementing a multi-peripheral controller using a tiny mixed-signal FPGA(From EE Times blog, "Programmable Logic Designline"):As you may recall from previous columns, I tend to think of Silego'sGPAK chips as being super-small mixed-signal FPGAs that you canliterally design and program in just a few minutes, and that cost only afew cents each.Well, the folks at Silego were so excited by the interest my columns generated within the Embedded.com and EETimes.com communities that they decided to offer 25 development kits for free (see Want a free Silego GPAK4 mixed-signal FPGA development kit?).The idea was that Embedded.com and EETimes.com community members would email me to excite me and delight me with descriptions of the amazing hobby or work projects they might use GPAK4 devices for, thereby convincing me that they deserved to receive one of these little beauties.Two weeks later, I sauntered into the Pleasure Dome (my office), ensconced myself in my Supreme Commander's Chair with its super-soft cuddly cushion, and selected the 25 entries that most ignited my imagination and whipped my creative juices into a frenzy (see 25 Free Silego development kits will soon be winging their way).After this, things went quiet for a while, until earlier today when I heard from one of the lucky recipients, J.R. Stoner, who is principal engineer (and self-described "chief bottle-washer") at the Bifrost Development Group.In his email, J.R enclosed the .gp4 (GPAK4) design file associated with his latest project, which is a multi-peripheral controller (click here to download a compressed ZIP file containing the .gp4 design file along with the images presented below). The schematic for the portion of the design featuring the GPAK4 chip (a 20-pin SLG46620 device) is shown below.J.R. tells me that he's verified both the digital and analog functions insimulation -- using Silego's free GreenPak Developer application -- andhe's now working on the actual hardware. The graphical interface usedto capture the design and screenshots of some of the simulation resultsare shown below.J.R. tells me that he's verified both the digital and analog functions insimulation -- using Silego's free GreenPak Developer application -- andhe's now working on the actual hardware. The graphical interface usedto capture the design and screenshots of some of the simulation resultsare shown below.[The simulation was merely to insert the input signal for the constant read out of the SPI register, or as in a previous case insertion of the A/B signals. In all cases the outputs were measured directly from the GPAK4 chip outputs.]Theory of OperationJ.R. says that the logic is related to a common XOR method of quadrature decoding, plus the input signals are synchronized to the oversampling clock. The SPI output for both the fan PWM and the quadrature up/down counter have been confirmed at the pin level. The up/down DIR selector is derived from the XOR of one of the quadrature phases (A) and the latched other phase (B).The four-input XOR is an odd-parity generator connected to both synchronized phases -- and their latched equivalents -- through the final pair of D flops. This is used to generate the FSM0 counter clock pulses, one for each of the four phase transitions per unit of the quadrature signal. The latch clock for DFF 1 is derived from the 25 kHz RC clock, so each phase transition (STEP) pulse width is 40 µs.Each time a quadrature cycle is detected, the SPI counter will increment or decrement by four, which is then read out the SPI serializer as the MSB (most-significant bit). The intention is to measure all phase transitions in the SPI counter, stripping off the two LSBs (least-significant bits) of the count, thereby reducing the sampling noise by 12dB.The /SWIN to SWOUT unit is a simple de-bouncer for the UI selector for this project.The analog-to-digital converter (ADC) reads the temp sensor, which is loaded directly into the LSB of the SPI serializer. DLY7 is a ring oscillator delay of 7.22 µs to eliminate startup glitch from the sweep count during ADC startup. And CNT8 is a period sweep counter, which is used to gate the PWM unit.Advantages of the GPAK4J.R. also says that one could envisage a simpler hardware implementation involving feeding A, B, and SWxx to the MCU's GPIO pins (of which not many are likely to be available) coupled with an external DAC circuit (which would have to be used for the thermistor). However, the GPIO pins would have to be software de-bounced, while the DAC would require yet more GPIO pins. Then separate ISR (interrupt service routines) -- or clocked polling -- would have to be written to handle the devices at a level that would consume too much time resources from the main CPU.The biggest wins in using the GPAK4 device for these functions are (a) simplification of the interfaces to a single SPI channel, (b) intrinsic de-bounce of the mechanical inputs, (c) automatic conversion of the analog thermistor signal to a 12V PWM fan, and most importantly (d) complete asynchrony between the quadrature input device and the SPI register, which provides not only an up/down counter for the encoder, but also a non-interrupt way of detecting over-temp on the thermal sensor. Also, there is significant simplification of the board layout using one itty-bitty 4mm device.

author: cobra18t
author_rank: Newbie
timestamp: December 28, 2015, 10:00:32 pm
content: I stumbled across the article about your design about a month ago. It turns out that the GPAK chips are perfect for a couple of my applications. Thanks for posting and letting other people know about these interesting devices.