Diode-connected NMOS delay circuit - Page 1
Forum section: electronics / projects

author: vcvs
author_rank: Contributor
timestamp: June 06, 2025, 08:36:57 am
content: I found the circuit below in an open source project  and do not really understand the part annotated "Delay circuit".Since Q2A is a diode-connected NMOS (always in saturation) it will behave as a voltage-controlled current source. As C3/C4 are gradually charged up, Vgs will get smaller and proportionally less current will be sourced. But what is the purpose of R5/R6? To provide a return path when the input to Q2A is low?I simulated the circuit in LTspice and the results seem to confirm my theories. But how would I calculate the time constant (which is multiple seconds)? It is not only the RC time constant but somehow a function of how Vgs changes as well.https://github.com/Summa-Cogni/Mathpad/tree/Main/hardware/pcb

author: PGPG
author_rank: Frequent Contributor
timestamp: June 06, 2025, 11:22:37 am
content: Quote from: vcvs on June 06, 2025, 08:36:57 amI don't understand this sentence. If it is connected to be diode than is diode and diode is not current source.But when I learned electronics NMOSes were practically not used so I don't feel to have them in your little finger.

author: vcvs
author_rank: Contributor
timestamp: June 06, 2025, 11:38:24 am
content: When gate and drain are tied together it guarantees operation in saturation region (corresponding to linear region for a BJT), and the drain current is proportional to Vgs

author: Peabody
author_rank: Super Contributor
timestamp: June 06, 2025, 02:08:41 pm
content: Perhaps Q2A is oriented backwards in the original circuit. It has the gate connected to the source, and that would mean it is always off. And in that case, it's just a diode, and could be replaced by a diode. Your Spice schematic has it oriented the other way.

author: PGPG
author_rank: Frequent Contributor
timestamp: June 06, 2025, 07:00:51 pm
content: Quote from: vcvs on June 06, 2025, 11:38:24 amIf diode inside Q2A is drawn correctly than its pin1 can be Drain only if it is PMOS (I never know it from symbol).But title says NMOS (and Q1A having the same symbol works like typical NMOS) so Q2A pin1 is Source not Drain.With Gate shorted with Source it works like only diode, but it was clearly said in first post:Quote from: vcvs on June 06, 2025, 08:36:57 amThis part of sentence was clear. What I didn't understood was the rest of this sentence - why having Gate connected with Source it is in saturation.

author: vcvs
author_rank: Contributor
timestamp: June 06, 2025, 07:41:39 pm
content: Yeah, that was a mistake from my side..

author: vcvs
author_rank: Contributor
timestamp: June 06, 2025, 07:45:24 pm
content: The whole reset circuitry apparently came from another project , which in its README links to an article about it . Have not had time to take a look at it yet.:https://github.com/0xCB-dev/0xCB-Helios:http://acheronproject.com/reset_article_1/reset_article_1

author: Someone
author_rank: Super Contributor
timestamp: June 06, 2025, 11:43:20 pm
content: Quote from: vcvs on June 06, 2025, 07:45:24 pmCopy paste culture has reached hardware development, panic! The dangling BOOT net was suspicious but i wasnt going to spend time trying to work it out.