PIC I/O port affecting adjacent I/O port - why? - Page 1
Forum section: electronics / beginners

author: bpb
author_rank: Newbie
timestamp: November 09, 2019, 03:05:38 pm
content: Hi,I am new to electronics and am seeing something I don't understand when trying to visualize I/O ports on a PIC microcontroller (PIC16F690).The probe on the left side of the img is connected to a PORTC I/O pin, and the probe at the bottom of the img is *not* a PORTC I/O pin (but is adjacent to one).When setting PORTC pins to logic one, I see the expected ~5V on the PORTC pin and ~0V on the adjacent pin:However, when toggling the PORTC pins, it affects the adjacent pin! What?? How??

author: dom0
author_rank: Super Contributor
timestamp: November 09, 2019, 03:09:49 pm
content: The other pin is configured as an input without pull-up, i.e. High-Z? In that case it is capacitive feedthrough to the other pin.

author: bpb
author_rank: Newbie
timestamp: November 09, 2019, 03:18:10 pm
content: Quote from: dom0 on November 09, 2019, 03:09:49 pmHere's a shot with the adjacent pin configured as an output port set to logic 0. Is this still "capacitive feedthrough"?

author: rstofer
author_rank: Super Contributor
timestamp: November 09, 2019, 03:25:58 pm
content: I don't see any decoupling capacitors on the Vcc/Gnd pins. That's a really big deal when things happen fast - like rising/falling edges.

author: dom0
author_rank: Super Contributor
timestamp: November 09, 2019, 03:40:18 pm
content: That's ringing due to the inductiveness of the ground leads of your probes and the power supply lines. Usually it looks quite a bit worse than this with a setup like you showed in the picture.

author: bpb
author_rank: Newbie
timestamp: November 09, 2019, 06:42:04 pm
content: Quote from: rstofer on November 09, 2019, 03:25:58 pmThere's a .1uF capacitor in the top left corner of the breadboard. I put it there since that was recommended in the 8-Bit PIC® Microcontroller Design Recommendations.Quote from: dom0 on November 09, 2019, 03:40:18 pmWhat do I need to learn in order to understand more about ringing? I feel like I'm missing basic understanding of fundamentals here.Removing the capacitor appears to reduce the ringing - I thought a decoupling capacitor was supposed to help reduce noise (same thing as ringing?). Without the capacitor the amplitude of the 1st overshoot bump is 0.136V lower. Removing the probe on the adjacent I/O port helps a little bit more, but nowhere near as much as removing the capacitor.

author: rstofer
author_rank: Super Contributor
timestamp: November 09, 2019, 07:00:38 pm
content: Quote from: bpb on November 09, 2019, 06:42:04 pmNow I see that little dickens! OK, that location is useless. In a perfect world, there would be a 0.1 ufd capacitor within a small fraction of an inch of the VCC and GND pins. This isn't always possible unless you do a PCB but to have it 3 inches or more of long inductive wires away from the pins isn't helping. If anything, the inductance and capacitance are forming an oscillator. Removing the capacitance stops or reduces the ringing because the capacitor was too far away to begin with.The neat thing about decoupling capacitors is that you don't have to worry about having too many. More is good! So, keep the one you have, add one as close to the pins as possible and throw a 10 ufd electrolytic across the power rails. I tend to put electrolytics at the far end of the rails but close to the entry point probably works just as well.At some point, you just give up when you come to the conclusion that breadboards are suboptimal. It's just that there isn't anything much better until you get to making a PCB and that's a lot of cost for a simple demo circuit. Which is why I buy demo boards... They have more features and the electrical problems won't exist.

author: rstofer
author_rank: Super Contributor
timestamp: November 09, 2019, 07:32:02 pm
content: Quote from: bpb on November 09, 2019, 06:42:04 pmWell, back when TTL was king, we could buy sockets that had the decoupling capacitor factory installed across the VCC and GND pins. One capacitor per package, no matter what. The modern FPGA board will have hundreds of decoupling capacitors.The current spike during switching is related to the rise time of the signal and the capacitance. Specifically, the current i = C dv/dt where the dv/dt term dominates. It is the total change in voltage divided by the time required to accomplish the change. A 5V signal switching in 10 ns is a change of 500 million volts per second. That's a HUGE number! Now multiply that by some capacitance, say .001 ufd , and you're looking at a 50 amp spike in the power supply.True, 0.001 ufd is pretty high but the idea is that high speed switching causes spikes and spikes are damped down by decoupling capacitors as their charge is used to supply that current for the spike.Inductance works the other way, it won't allow the current spike to occur in near zero time. The voltage drop across an inductor is related to the rate of change of current ('i' from above) and the inductance L (in Henries): v = L di/dt. Since the current through the capacitor is trying to change as fast as the voltage, suddenly di/dt is a big number and for any appreciable value of L, there will be a high voltage drop across the inductor - those long leads in the power supply. So, when you add capacitance to provide current to provide for the spikes, you better not add inductance because it will cancel out the capacitance. In effect...QuoteRight! The capacitance is gone so the inductance isn't creating an oscillator. Instead, there will be voltage spikes across the inductor when signals change state. But those spikes affect Vcc and could presumably be transmitted to every signal.The problem with capacitance and inductance is that there are only two ways to talk about them. We can hand-wave like I did above, recognizing that the description is close but not perfect, or we can go for the math; many hobbyists aren't up for that. If you are, you might get a lot out of the Khan Academy Electrical Engineering program. It is definitely math-centric but then so is engineering. The cool thing is that there is also a math track that covers EVERYTHING but from a math perspective, not an engineering perspective.The difference in perspective is profound: It is the reason the the University of Florida has two math tracks. One is for math majors, the other for engineers. As an engineer, I just want to use math, I don't want to derive it; I'm not looking for hidden beauty. I want a 'match', not 'the history of fire'. Hence the engineering track at Khan Academy.In the short term, add another decoupling capacitor as close to Vcc and Gnd on the chip as you can get.

author: Ian.M
author_rank: Super Contributor
timestamp: November 09, 2019, 07:44:32 pm
content: +1. To decouple a PIC (or other DIP MCU) on a breadboard adequately, get a 100nF ceramic capacitor (for their low ESR), disc ceramic if you can find one, or an epoxy dipped leaded MLCC, with long enough legs to go directly over the top*of the PIC chip between Vdd and Vss. For larger breadboard projects, add a 10uF aluminium electrolytic across the supply where it comes onto the board. The extra ESR of an electrolytic is actually helpful as it damps ringing, which can otherwise cause a severe transient over-voltage if the PSU is switched at its output or you 'hot-plug' the board supply as the inductance of the long PSU to board supply leads rings with the total decoupling capacitance on the board. Also, minimize the loop area (and thus the lead inductance) by keeping the PSU to board leads lightly twisted together.Also, *DON'T* use long wires on the breadboard for Vdd and Vss. Get some 24AWG PVC insulated tinned solid core copper wire - e.g split a few feet of good quality scrap Ethernet cable (not patchlead - that's stranded) - and cut and form minimum length jumpers for your power nets. If you are using both sets of breadboard power rails, link them across the board at *BOTH* ends of it.If you need to use a crystal for the PIC clock, get one with long enough pins to insert it directly in the breadboard directly between the OSC1 and OSC2 pins, and put its load capacitors directly to the nearest Vss pin if possible. Using jumpers in a crystal oscillator setup is a really bad idea as its likely to be the highest frequency signal on the breadboard and glitches or EMI pickup can result in extremely weird misbehaviour.Put in single bare 0.1" header pins for probe points, or use short loops of bare tinned copper wire, in adjacent holes in the same strip. Its critically important to keep the probe ground lead as short as possible and as close as possible to the PIC Vss pin (or ground pin of what ever other chip you are probing round) - signal integrity is already FUBARed by being on breadboard and by the use of a clip on ground lead, you cant afford any extra lead length adding inductance if you don't want to waste time tracking down 'phantom' ringing due to bad probing technique rather than real glitches.* For 28 pin PICs with two Vss pins, link them with a short (cut and formed to exact minimum length) ground wire directly over the top of the chip and put the cap between Vdd and the adjacent Vss pin. For 40 pin PICs with two pairs of Vdd & Vss pins, link Vdd to Vdd and Vss to Vss straight over the top of the chip and put two decoupling caps one between each pair of Vdd & Vss pins.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 09, 2019, 08:33:05 pm
content: FYI, specifically what you're seeing on the first scope shot is the capacitance between pins, mainly between adjacent positions in the solderless breadboard itself. Which is somewhere around 4pF, IIRC. This acts as a capacitance divider, from the driving pin, to the susceptible pin, to ground. The pin self-capacitance and probe capacitance act in parallel, both on the order of 5-10pF I would guess. So there's 5V into 4pF into 20pF to ground. You end up with about 1/3 to 1/8 of VCC. The measurement looks to be about 1/6th, which is pretty reasonable agreement considering the hand-waving guesses at capacitances here.There is a time constant associated with this as well, because the probe has resistance, which discharges the node slowly over time. 10MΩ across the Thevenin equivalent capacitance (all acting in parallel in this case, so ~24pF) gives a time constant of 240µs. The driven waveform is much shorter than this, so it doesn't look perceptibly sloped; if you added a delay of maybe 50µs to the loop, the slope would be perceptible, and with a delay of over 500µs, the exponential RC discharge waveform would be apparent.HTH,Tim

author: rstofer
author_rank: Super Contributor
timestamp: November 09, 2019, 08:55:35 pm
content: And the OP probably thought that hooking up a PIC on a breadboard would be easy!It turns out, nothing is easy!

author: dom0
author_rank: Super Contributor
timestamp: November 17, 2019, 04:02:58 pm
content: Quote from: rstofer on November 09, 2019, 08:55:35 pmStandard logic is considered easy to handle, but pretty much all logic you can buy makes for relatively high speed circuits. Even if you are using a 74HC flip flop toggling once per second, the flip flopitselfis still rather fast. On the other hand, 3.3 / 5 V CMOS is pretty tolerant to noise as well. So people can get away with a lot of funny things and things still (usually) work, considering that your average micro runs at 8-40 MHz. Actual analogue circuits with similar bandwidths are far less forgiving.

author: bpb
author_rank: Newbie
timestamp: November 26, 2019, 04:24:24 pm
content: Thanks to all who replied here. I suspect it will be easier when I've got some fundamentals down, but I did not suspect R, C, L to be so sensitive! This is nowhere near the digital realm where things are clocked and binary.

author: IDEngineer
author_rank: Super Contributor
timestamp: November 27, 2019, 12:11:09 am
content: Quote from: bpb on November 26, 2019, 04:24:24 pmThe faster the digital signal, the more it must be treated like analog. Fast rise/fall edges have amazing harmonic content, and we ignore it at our peril.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 27, 2019, 12:50:22 am
content: Worth noting, digital is a subset of analog. Analog is continuous voltages and currents, impedances and waves. Digital is a special case, where we make certain assumptions about levels and timing, and we can use simpler rules (combinatorial and sequential logic, with propagation delays).When those assumptions get broken, we have to take a step back and look at the analog levels again.Tim

author: gcewing
author_rank: Regular Contributor
timestamp: November 27, 2019, 01:47:17 am
content: Could be worth pointing out that a small amount of ringing on a digital signal probably isn't anything to worry about. As long as it's a lot less than the logic threshold it won't affect anything. So don't knock yourself out trying to eliminate all vestiges of ringing -- you won't be able to do that.