Routing of ESP32-C3 Wroom Module - Page 1
Forum section: electronics / general

author: girishv
author_rank: Regular Contributor
timestamp: June 29, 2024, 02:38:21 pm
content: I've been exploring the PCB layout of the ESP32-C3 module and noticed a couple of interesting points:Customized Footprint: It appears that Espressif is using a customized footprint for the thermal pad beneath the chip. While the datasheet specifies a minimum size of 3.65mm, they are using a 3mm thermal pad.Power Routing: Additionally, they seem to be routing power between the pads and the thermal pad.I'm planning to design a custom board and would appreciate any suggestions or advice on the layout. Here are my design constraints and preferences:I will be using a 4-layer board.I intend to use 0402 discrete components instead of 0201. Are there any potential issues or considerations I should be aware of with this choice?I plan to use a minimum via size of 0.3mm (hole) / 0.45mm (diameter).Additionally, I need guidance on how and where to add tuning pads for the PCB antenna. Any tips or best practices for effectively managing the power routing, thermal pad size, and antenna tuning in a custom design would be highly valued.

author: nctnico
author_rank: Super Contributor
timestamp: June 29, 2024, 02:53:31 pm
content: Did you check the hardware manual / layout guide? Espressif has thourough documentation in how to use their chips in your own design. When evaluating their design guidelines, keep in mind that Espressif likes to use PCB traces as inductors for power filtering purposes. So don't be surprised to see a long winded power trace instead of a solid copper plane; it is all part of a plan.

author: girishv
author_rank: Regular Contributor
timestamp: June 29, 2024, 04:22:37 pm
content: Quote from: nctnico on June 29, 2024, 02:53:31 pmI reviewed the hardware manual and layout guide for the ESP32-C3 module. In my exploration, I considered using the routing techniques employed in the Wroom module wherever possible. However, as previously mentioned, there are deviations from the standard conventions and guidelines.One notable example is the footprint used for the module. The actual footprint deviates from the one suggested in their documentation. This discrepancy raises concerns about compatibility and performance when designing custom boards.To illustrate this, I have attached a screenshot of the DXF file showing the actual footprint used. This visual representation highlights the differences.

author: selcuk
author_rank: Frequent Contributor
timestamp: June 29, 2024, 04:30:08 pm
content: I can recommend checking the hardware guide as suggested before.I've built a similar module but with ESP32 chip. 4-layer, min 0402 passives, 0.3mm via to keep PCB costs low. I used a custom footprint as well. A little bit different than recommended one. I hope it is helpful for your design with ESP32-C3 chip.https://www.eevblog.com/forum/oshw/esp32-ethernet-wi-fi-serial-gateway/

author: nctnico
author_rank: Super Contributor
timestamp: June 29, 2024, 04:49:53 pm
content: A QFN footprint is not super critical. Just as long as it has the same amount of thermal vias spaced evenly across the thermal pad. There are also variations due to the soldering process. In my designs I keep the pads for 0.4mm pitch QFNs narrower than specified in order to have a 0.2mm spacing between them as some solder processes have trouble when the pad spacing becomes less than 0.2mm.

author: girishv
author_rank: Regular Contributor
timestamp: June 29, 2024, 04:52:47 pm
content: Quote from: selcuk on June 29, 2024, 04:30:08 pmI have decided to follow the hardware design guidelines as suggested.Additionally, thank you very much for sharing the link to your project. I had the chance to review it, and I must say, it looks excellent and is very inspiring. Seeing your implementation has given me a lot of ideas and confidence for my own project.I appreciate your support and the valuable resources you’ve provided. Looking forward to any further suggestions you might have.

author: nctnico
author_rank: Super Contributor
timestamp: June 29, 2024, 05:07:57 pm
content: Quote from: selcuk on June 29, 2024, 04:30:08 pmI do see a potential problem with this design; it doesn't have a bandpass filter at the antenna which may cause it to fail RF out-of-band emissions due to harmonics for both CE and FCC. Espressif's hardware guide kind of explicitely mentions needing a filter (besides the antenna tuning components).

author: tooki
author_rank: Super Contributor
timestamp: June 29, 2024, 05:17:59 pm
content: I really don’t understand why anyone who isn’t already a well-funded RF expert designing a product for high-volume production would design their own board using bare ESP32 chips. The whole point of the ESP32 modules is that they’ve been properly designed, tested, and certified, so that you can integrate them without needing to get your own RF certification done. It doesn’t make sense to do your own unless you’ve got a high enough volume planned to justify the cost of one or more rounds of RF compliance testing.

author: nctnico
author_rank: Super Contributor
timestamp: June 29, 2024, 05:37:52 pm
content: Quote from: tooki on June 29, 2024, 05:17:59 pmActually the RF testing is not that much work compared to doing CE / FCC and you can do a lot of pre-compliance testing / fixing in house if you have a spectrum analyser which goes up to 13GHz. If you can outsource the testing to Asia, the costs are very reasonable. It gives you the freedom to create much more compact products using components that can be of higher quality compared to what is fitted on a module. Also availability of modules can be problematic (especially long-term).

author: girishv
author_rank: Regular Contributor
timestamp: June 29, 2024, 05:49:46 pm
content: Quote from: tooki on June 29, 2024, 05:17:59 pmI have a use case where the current ESP32-C3 modules do not meet my requirements. Specifically, I need 16MB of flash memory, but the existing modules only offer 4MB.

author: selcuk
author_rank: Frequent Contributor
timestamp: June 29, 2024, 09:25:13 pm
content: Using a band bass filter is a good idea. I can additionally recommend adding a TVS protection to the antenna. These components usually don't exist on existing modules on the market.To lower the cost and prevent the out-of-band emissions, you can use a narrowband PCB or chip antenna (not narrower than required) and impedance matching components arranged as a low pass filter. You can also arrange them as a high pass filter if you need to suppress lower frequencies. This depends on your antenna design. Of course using a chip filter is a ​guarantee.ESD test pulses have a rise time below nanoseconds. The antenna is a good entry point for such a signal. After all, its job is about receiving GHz range signals. Although the modules on the market have many certifications, they don't have an explicit protection against this. I have doubts about using a low-cost Chinese module on promising applications so making your own design is not a bad thing in terms of reliability.Flash memory was the first reason for me as well, while making my project. There are many TCP/IP libraries in the ESP-IDF tree, and you see the opportunity of using many client-server protocols, remote firmware updates, data storage etc. But you can only use basic things with a 4MB flash.

author: Sagar
author_rank: Contributor
timestamp: July 05, 2024, 07:56:30 am
content: I have designed a 6-layers board, for my home IOT requirement previous week. Because it has a lot of complexicity and I have to redesign the esp32 chip so that it can fit inside my designed baord. I used 0402 components and tried to keep the system minimal for my specific use case scenario. One more thing, Because I have some space issue I consider using VIA in PAD services, you can find some manufacturer online which do so, I have used JLCPCB for that work. I don't prefer PCB antenna because of their short range, that's why I used UFL extender.