ADC - can I avoid using a buffer for slow high impedance signal with a big cap? - Page 1
Forum section: electronics / beginners

author: daqq
author_rank: Super Contributor
timestamp: February 02, 2015, 07:29:52 pm
content: Hi guys,For a high voltage divider - 20Meg to 100k (target conversion of max 450 VDC to 2.5V range) I was hoping to avoid buffering the signal by using a big filtration cap on the divider output (~10uF) that should drive the ADC during its sampling period.My schemes were foiled by the fact that the ADC will have around 1uA or more input leakage current, which could seriously mess up the voltage.The reason I was hoping to avoid the buffer altogether was to avoid offset voltages and to be able to measure close to zero without all sorts of dual supply nasty etc.Is there any reasonable way around this? If not, could you suggest a good op amp for such an application? I'm guessing FET input?Thank you,David

author: dannyf
author_rank: Super Contributor
timestamp: February 02, 2015, 07:45:44 pm
content: Quotedepending on what you mean by "reasonable".QuoteR2R opamps.Or run them dual rail.QuoteUnlikely.

author: wraper
author_rank: Unknown
timestamp: February 02, 2015, 07:54:06 pm
content: 10 uf is useless and ultra slow and if using electrolytic can cause more leakage than ADC itself. 10n - 100n is more than enough. Just don't sample ADC too often as it is what causes noticeable input current.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 03, 2015, 11:38:06 am
content: Depending on your ADC and desired accuracy, 100k is too much. 10k is the maximum recommended for most converters. Likewise, more than 0.01uF or so won't do you any good, unless you need an extremely slow response.Tim

author: Psi
author_rank: Super Contributor
timestamp: February 03, 2015, 11:49:27 am
content: i've run a AVR ADC with 100K input impedance before and it worked ok.I only used 8bits and was sampling at ~500hz

author: tszaboo
author_rank: Super Contributor
timestamp: February 03, 2015, 09:06:57 pm
content: What voltage rails do you have, what is the ADC resolution, sampling time (exact type?). How much errors do you want to calibrate out, or how much is the desired accuracy? If you anwer these, maybe I can give you some help.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 03, 2015, 09:18:14 pm
content: Quote from: wraper on February 02, 2015, 07:54:06 pmWhy would anyone even consider using an electrolytic cap for that type of application?10uF is an 0603 ceramic these days.

author: dannyf
author_rank: Super Contributor
timestamp: February 04, 2015, 11:55:36 am
content: The effect that you are trying to utilize is "charge transfer" - which sometimes is also used to measure small capacitance.If the outboard capacitor is sufficient large, the sampling capacitor will draw just a little charges from the outboard capacitor to be fully charged up. I use 0.1u for its abundance and it is more than enough.

author: wraper
author_rank: Unknown
timestamp: February 04, 2015, 03:48:16 pm
content: Quote from: AndyC_772 on February 03, 2015, 09:18:14 pmWhy someone could not consider, especially if not using SMD parts? Question is in beginners section BTW, so considered worth to mention.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 04, 2015, 05:08:32 pm
content: The main benefit of a ceramic cap is its very much lower ESR and ESL compared to an electrolytic.A typical ADC input includes a sample-and-hold circuit, which behaves like a switch in series with a small capacitor. When the switch is closed, the capacitor is quickly charged to the voltage that's applied to the ADC pin, and when the switch is then opened again, the capacitor retains that voltage for the time it takes the ADC to perform a conversion. Hence the name, sample and hold.If the external capacitor has high ESR or ESL, then there will be a voltage drop during the time the S&H capacitor is charging, so it won't capture an accurate voltage. With a ceramic cap, this effect is much smaller than it would be with an electrolytic, because the ESR and ESL are dramatically smaller. It can also be located nearer to the input pin of the ADC, so the ESL of the wiring between the two is minimised as well.I admit that, since almost every design I do is surface mount, I tend to automatically regard a through-hole electrolytic cap as an extra manufacturing step and an additional cost, both of which have to be justified. This was arguably an oversight on my part - though if getting the best performance from an ADC is desired, using an SMT board with a proper ground plane is pretty much a pre-requisite anyway.

author: wraper
author_rank: Unknown
timestamp: February 04, 2015, 09:27:50 pm
content: Quote from: AndyC_772 on February 04, 2015, 05:08:32 pmYou are wrong about this. There is internal resistor in charging path of ADC sampling capacitor. And that usually is at least a few kiloohms. Therefore few ohms of ESR does not change anything. Actually it is better to not use a capacitor at all if signal source does have low enough impedance that sampling capacitor have enough time to charge during sampling time. Especially actual if pause between ADC sampling events is low (read duty cycle), in which case capacitor together with a signal source impedance can form a kind of voltage divider. As you can see from the picture external capacitor can be evil, not good.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 05, 2015, 12:03:00 pm
content: Fair comment; with that ADC, with its built-in input resistor, I agree the capacitor's properties wll have little or no effect.I'd still regard it as perverse to use any through-hole component on a board where performance is important, though. If you want high performance, use a surface mount PCB with a ground plane.

author: tszaboo
author_rank: Super Contributor
timestamp: February 05, 2015, 01:01:04 pm
content: Quote from: AndyC_772 on February 05, 2015, 12:03:00 pmWe still dont know whether we are looking at 6 bit or 0.001% accuracy. I guess the voltage divider is TH, at least I would consider to make it from TH, just for the robustness. The ADC filter cap should not be TH nonetheless.Quote from: wraper on February 04, 2015, 09:27:50 pmSince we dont know the ADC architecture or type, I dont know how can you make any suggestion, what to place before the ADC. Maybe the ADC needs an FDA, because it samples at 10MSPS for all we know...