LCD or OLED retrofit for PM6690 / FCA3000 / CNT-90 frequency counter - Page 1
Forum section: electronics / repair

author: Smile2016
author_rank: Regular Contributor
timestamp: November 04, 2024, 09:34:35 pm
content: Does anyone have info, solution or ideas on an LCD or OLED retrofit for PM6690 frequency counter? The original display is a 320x97 pixel graphical LCD with an LED backlight, model TM32097AGFG.

author: coromonadalix
author_rank: Super Contributor
timestamp: November 05, 2024, 01:52:49 am
content: https://www.eevblog.com/forum/testgear/new-display-for-pendulum-cnt-90-counter/its a 320*97 pixels lcd, but no one so far has the right substitute ... some saw a few things with a 320*64 ... but for sure misses 33 lines ...

author: picburner
author_rank: Frequent Contributor
timestamp: November 05, 2024, 04:18:15 am
content: Or use a 320x128 display leaving two unused black bands above and below, provided that the dimensions of the new display are compatible.In addition, you need to interpose a micro or an FPGA that converts the signals from the old display to the new one: in short, a lot of work.

author: coromonadalix
author_rank: Super Contributor
timestamp: November 05, 2024, 05:18:55 am
content: you have to check in the service manual for the pinout ... cant find anything on this model ... ?

author: Smile2016
author_rank: Regular Contributor
timestamp: November 05, 2024, 04:13:23 pm
content: The schematics can be found at this link.https://assets.fluke.com/manuals/6690____smeng0000.pdf. I’m curious if anyone has already put in the time and effort to create something similar. The biggest challenge is finding a display that fits mechanically in the available space. I agree that an FPGA or MCU might be necessary, along with extensive data capture experiments. It’s unlikely to find a display with the same driver chip, which is currently unknown...

author: coromonadalix
author_rank: Super Contributor
timestamp: November 05, 2024, 05:41:19 pm
content: best luck would be to find this lcd controller driver chip(s) and see what subs we can find

author: Smile2016
author_rank: Regular Contributor
timestamp: November 05, 2024, 06:57:13 pm
content: 320x96 pixels... this might suggest a dual 65 x 132 (192) Dot Matrix LCD Controller, such as the ST7567 ST7539 or so . It appears that only D0 to D3 are in use, while D4 to D7 are grounded, suggesting that the SPI 4-wire mode is likely selected? The option setting MD J2.6 is set to low (“L”), which could correspond to PSB being “L” in the ST7567. Time to connect a logic analyzer and verify! V1..V5 biasing is fixed and similar to ST7567 datasheet.https://www.hotlcd.com/upload/download/ST7567_V1.0a_080220.pdf

author: coromonadalix
author_rank: Super Contributor
timestamp: November 06, 2024, 03:23:14 am
content: do you have an counter dismantled and show us some pcb pictures of the original lcdic's markingsit was never shown here, just numbers ...please pleasethks

author: kilobyte
author_rank: Regular Contributor
timestamp: November 06, 2024, 09:19:57 pm
content: I don't have such a nice frequency counter but looking at the schematic the type off LCD is mostly controller less. That means it typically only has the LCD driver shift registers and an external display controller. The controller than needs to refresh it permanently like larger TFT displays with a RGB interface.So XCK is the shiftregister clock (4-8MHZ?), LP should be the Line pulse for latching and FR is the frame mark, and EIO not sure about that. LCD Drivers could be NT7701/NT7702But without seeing an actual image or some measurements its mostly guesswork.

author: Smile2016
author_rank: Regular Contributor
timestamp: November 07, 2024, 02:39:07 am
content: Quote from: coromonadalix on November 06, 2024, 03:23:14 amSure, I'll share something over the weekend.

author: Smile2016
author_rank: Regular Contributor
timestamp: November 07, 2024, 02:48:25 am
content: Quote from: kilobyte on November 06, 2024, 09:19:57 pmThat sounds like a solid hypothesis. I'll take some signal measurements and share the results.

author: Smile2016
author_rank: Regular Contributor
timestamp: November 07, 2024, 09:12:28 pm
content: some pictures..1.

author: Smile2016
author_rank: Regular Contributor
timestamp: November 07, 2024, 09:13:56 pm
content: some pictures..2.

author: Smile2016
author_rank: Regular Contributor
timestamp: November 07, 2024, 09:15:09 pm
content: some pictures..3.

author: coromonadalix
author_rank: Super Contributor
timestamp: November 08, 2024, 05:18:16 pm
content: a 2005 era lcd .... dang cant find anything on the webthe nearest i can find are 120x320 pixels something like COM33T3N71ZLC ?? spi driven ...https://www.panelook.com/COM33T3N71ZLC_Ortustech_3.3_LCM_overview_17294.htmlcan you measure diagonally and or width lenght ... thksyou do have some search possibilities here :https://www.panelook.com/modelsearch.php?op=sizehttps://www.panelook.com/modelsearch.php?op=resolution320x96 pixels search give theseshttps://www.panelook.com/resmodlist.php?resolutions[]=21150all in the +/- 4.2 to 4.9 "some are in the 2005 era, and discontinued ....

author: Smile2016
author_rank: Regular Contributor
timestamp: November 09, 2024, 01:14:59 am
content: Quote from: coromonadalix on November 08, 2024, 05:18:16 pmThe opening is roughly 124 x 39 mm, and aligns with the display's active area. The display’s full dimensions are about 135 x 51 mm, with one corner missing, for a mounting screw. From the inside, there is approximately 2 to 2.5 mm of space around the opening, except on the north and west sides, where two CoG controllers (2N, 1W) are positioned with individual FPC cables connecting to each. Display is attached to PCBa by 4 solder joints that powers the LED backlight bars.

author: Smile2016
author_rank: Regular Contributor
timestamp: November 09, 2024, 01:28:31 am
content: The only mechanically compatible display I found is a 4.58" Rectangle Bar RGB TTL TFT Display (320x960 pixels) - HD458002C40. This could potentially work with the Adafruit Qualia ESP32-S3 for TTL RGB-666 displays. However, a key limitation is the Qualia’s available I/O [they use a GPIO expander on I2C] , mainly supports one native I2C,challenges the data serialization and timing. A 1:3 scaling approach might work, with a few lines repeated to keep the aspect ratio. I’ll get the data format and clocking in more detail later. A Raspberry Pi faces similar GPIO count limitations. Reducing the RGB bit depth, to free up some IOs could help, but my software skills for modifying existing libraries are low..

author: Smile2016
author_rank: Regular Contributor
timestamp: November 09, 2024, 04:04:01 am
content: Quote from: kilobyte on November 06, 2024, 09:19:57 pmvery close ! Here are some captured wave-forms. Control signals shown are: FR, EIO, XCK, and LP. In the last 2 pictures, the signals are Data0, EIO, XCK, and LP. The clock is bursts of 80 pulses at approximately 833 kHz. The FR rate is 38.3725 Hz. Data is clocked in on the falling edge of XCK. Maybe the Qualia ESP32-S3+TFT Display - 4.58" 320x960 might still stand..

author: coromonadalix
author_rank: Super Contributor
timestamp: November 09, 2024, 11:56:53 am
content: its a matter of decoding / understanding all of this, and create the needed interface, mcu based, fpga based etc ....find an lcd who can decode that ? or if they are controller less ...there was / is some project here for the 34401a made by qu1ck ... i helped him when i had some 34401a.... and others for hp stuff ...https://www.eevblog.com/forum/testgear/hp3548-hp3457-oled-display/https://www.eevblog.com/forum/repair/hp-34401a-dmm-with-leaking-segments/https://github.com/openscopeproject/HP34401a-OLED-FW

author: Smile2016
author_rank: Regular Contributor
timestamp: November 10, 2024, 04:44:43 am
content: Quote from: coromonadalix on November 09, 2024, 11:56:53 amThis is indeed a shift register as kilobyte suggested. The data bits D1, D2, D3, and D4 are clocked in at 1.2 µs intervals (833 kHz) on the falling edge, with "D0" (the white trace) as the clock signal. Since each data sequence is 4 bits, it takes two clock pulses to form a complete byte. This explains the bursts of 80 clock pulses: (80clocks/2)×8 bits = 320 pixel rows in display. Each line/row contains 320 pixels, with pixels "ON" represented by zeros. For instance, the sequence 0x0C, 0xFF, 0xFF, ... translates to 11001111111111111111..., indicating that the 3rd and 4th pixels are ON. There are 97 lines per frame, where the green trace shows frame sync, useful for starting 1st line reading, and the blue trace marking the line latch, helpful for counting the lines. I’ve included few logic analyzer screenshots and the raw data file, which can be directly imported into Logic 2 software (available free at Saleae's download page).https://downloads.saleae.com/logic2/Logic-2.4.13-windows-x64.exe. feel free to decrypt my display !

author: kilobyte
author_rank: Regular Contributor
timestamp: November 11, 2024, 10:42:26 am
content: So using the Hexdump and Irfan View Raw Import results in the following image:Edit: Maybe an RP2040 with its programmable PIO could be able to handle such stuff, has enough RAM to keep the Data in some sort of framebuffer and update an other display. But I must admit that i never worked with the RP2040 so that is only a "feeling" seeing stuff others have done with the RP2040 and its PIO unit.

author: Smile2016
author_rank: Regular Contributor
timestamp: November 11, 2024, 04:14:07 pm
content: I’m a bit concerned about fitting the LCD, the long "bar" style is rare. The closest option has high resolution; I’ve found an RGB 565/666 parallel display with 960x320 resolution. This requires a lot of IOs, using up almost all the GPIOs on a PI2040, and it would also consume a significant amount of RAM. I’m not even sure if 262kB would be enough. PI PIO is nice but I have no idea how to use it right..The ESP32’s PSRAM is theoretically fast enough, and maybe an external shift register could handle the parallel to serial conversion to clock in the data at a reasonable speed using the native SPI on the ESP32. This would need to be faster than approximately 833kHz x 4. I’m confident the ESP32’s SPI can manage 5MHz. Again, this is just a supposition. I’m planning to get some materials in-house: PI2040, ESP32, and the display.

author: Smile2016
author_rank: Regular Contributor
timestamp: November 11, 2024, 04:15:08 pm
content: Quote from: kilobyte on November 11, 2024, 10:42:26 amimpressive !

author: morris6
author_rank: Regular Contributor
timestamp: February 21, 2025, 08:15:14 pm
content: My "two cents":The display of my CNT-90 also has the bright yellow area that is gradually spreading. This will make the instrument unreadable in the (near? / far?) future. Just like several forum members I'm searching for a replacement LCD. The idea to build an alternative that uses the 4.58 inch TFT display as suggested in this thread is interesting enough to spend some hobby time on.So far and as proof of concept I can demonstrate something working in a test setup. The 4.48 inch TFT display is connected to a small MAX10 FPGA development board. The original LCD FPC ribbons of the CNT-90 are taken out their connectors. My assembly is connected with an FFC ribbon cable to the CNT-90 front pcb J2 connector that is carrying the required signals.Although my setup has two alternating frame RAMs, one is written to while the other is in readout, screen updates are slightly more visible than with the original LCD.Also doable in white on black. This way it will be less noticeable that the screen is smaller than the opening in the front, I hope.To spend some more hobby time I would like to design a carrier pcb to replace the original LCD. It should fit with four pins to the front pcb of the CNT-90, just like the original LCD. It will need a boost converter to get 12 Volt for the backlight, the original is 5 Volt fed from one of the pins. And a short FFC ribbon to the J2 connector. The design will have to use a "solderable" FPGA. The present design uses about 134kb of block ram and 175 LE of the MAX10 that's on the little development board.Some pictures...

author: Smile2016
author_rank: Regular Contributor
timestamp: February 21, 2025, 11:31:50 pm
content: Quote from: morris6 on February 21, 2025, 08:15:14 pmWonderful! A quick look at what's available from major distributors for non-BGA versions, and the 10M04SCE144C8G caught my attention, smallest size I could find TQFP144pin ~20*20mm. The total BOM price is likely more affordable than Qualia. Congratulations !

author: morris6
author_rank: Regular Contributor
timestamp: February 22, 2025, 01:47:24 pm
content: For those forum members interested in the design some details here:I used a small development board from the German firm Trenz, a Max1000. I had it available and I used it before. For me programming works using the Quartus graphical method patching modules in a schematic "board file". I am aware that this is not the preferred method but it works for the nuts and bolts guy (me). The setup has grown into several functions:- A section to hard reset and then program the ST7701S controller of the display with the required initialisation command stream via a 9 bit serial connection. A ROM with these commands is programmed in the FPGA.- A display controller generating the synchronisation signals and reading the pixel data out of a dual ported RAM containing one frame of display data, 16384 x 4 bits. The RAM addresses are organised such that horizontal and vertical are interchanged. This is needed because the display's long side is the vertical axis as seen by the ST7701 controller. One bit of the RAM content is displayed in a 3 x 3 area of pixels on the TFT to get the correct scaling for the required 320 x 97 dots of the original monochrome LCD. The TFT display is used in simple black / white mode.- A signal decoder is interpreting the control and data signals coming from the CNT-90 MCU. Under control of this decoder the incoming 4 bits wide data bytes are written into the frame RAM.- For testing a signals generator mimicking the original control signals was added. The test uses a data frame ROM with picture data extracted from the Logic Analyser file thanks to @Smile2016, Reply # 19 session6.zip. This data ROM is programmed in the FPGA.- At the top 4 blanc lines are added and at the bottom the last dot line is repeated until the edge of the screen. This way the remaining dot lines are filled with the active frame placed in between.The setup above was working so I removed the signals generator to free up some pins of the development board and adapted it for connecting the signals of the CNT-90.After connecting to the CNT-90 it was noticeable that updates of the picture contents are visibly seen to build from left to right. So most likely the lcd controller stores the incoming data to one frame while displaying another. I think the LCDFRM signal that alternates between complete frame writes controls this proces. I have implemented this concept, with two frame RAMs, and indeed the resulting picture behaves more like the original LCD while refreshing the displayed data. Still some "buildup" is noticeable, the number area is probably erased before a new number is written. But this is also somewhat visible on the original LCD. The TFT's frame rate is about 60 / second while the original frame period is about 13 ms.Attached is a Zip file of the Quartus project as it is now. You can find here also a top.pdf that gives a picture of the schematic assembly with some comments.Interesting files:cnt90qu3.qpf : the Quartus project file to open the project... for MAX10 10M08SAU169C89top.bdf : the board filetrial0.mif : This is the memory initialization file for the ST7701S COG controller, for the init_rom.test2.mif : This file contains a frame of 4 bit wide data for the test generator test_rom, not used here anymore.Feel free to make suggestions to correct mistakes I made or misconceptions I have. And use whatever is fitting for you.Have Fun, Morrisedit: corrected original frame period number

author: Smile2016
author_rank: Regular Contributor
timestamp: February 25, 2025, 08:06:15 pm
content: Quote from: morris6 on February 21, 2025, 08:15:14 pm... all necessary signals are present on J2 FPC20. The "V0" currently serves as the "backplane" voltage for the original display and is adjustable by the instrument as "contrast," generated by the TPS61045 boost converter. According to the datasheet, for a 3.3V to 12V conversion, we can theoretically achieve up to 42mA at 12V or 34mA@15.3V (so shorting or lowering R20 and R1 is needed). R8 will be adjusted to optimize the backlight current for a mid-bias setting. I'll conduct some tests to determine if the TPS61045 can handle 40mA, although 20mA might be sufficient and could also extend the backlight LED's lifespan. If so V0 could be repurposed for the retrofit LCD BKlight. Adjusting BK light intensity would be a nice free feature...

author: morris6
author_rank: Regular Contributor
timestamp: February 26, 2025, 04:13:44 pm
content: For now, during further trials, I have the backlight on a bench supply. At 17 mA current the brightness looks "bright" enough. Your idea to use the V0 line as source for the backlight is very clever and simple, thanks.What I'm busy with is finding out why some of the content on the screen is still a bit flashing although the setup is using alternating RAMs. To investigate this I have programmed a function that compares the incoming data content frame per frame. It shows that updating the measured value on screen can take several, more than 4 or 5, frame periods. The page with statistics takes even longer: during a significant part of the one second period between updates new data are written. For me this explains the flashing. Untill someone presents a better idea or method.The original LCD, I think, is so slow that updating is hardly visible.

author: morris6
author_rank: Regular Contributor
timestamp: February 26, 2025, 08:15:04 pm
content: Screenshot: Yellow trace is changing at every new incoming frame, cyan trace is a flag that indicates different frame content compared to previous frame, reset at every new frame. This is of the display that shows in "Value" mode.

author: Smile2016
author_rank: Regular Contributor
timestamp: February 27, 2025, 09:30:35 pm
content: LCD adapter plate... here are a few pictures... any ideas or suggestions are welcome!

author: morris6
author_rank: Regular Contributor
timestamp: February 27, 2025, 09:58:32 pm
content: The FPGA setup now registers differences in frame content between incoming data frames. A difference holds the alternating of the display RAMs so the last unchanged data remains displayed. When at least 3 (this could be made 2, or 1) unchanged data frames have passed the display is updated and alternating resumes. The resulting display is really nice, no more visible erase and buildup of the measured results on the screen. Only the characters that need updating are doing so, the rest of the screen is static.Downside of the present setup is that more block RAM in the FPGA is needed.

author: morris6
author_rank: Regular Contributor
timestamp: March 02, 2025, 09:43:50 pm
content: A different setup is working as well. The comparison of frame content can also be done by simply adding all data bytes in a frame. Results are stored in two registers that are updated one by one. When different the display memory stops alternating and stays on the before last frame, waiting until frames are equal again.This new setup saves the block RAM needed for the previous compare scheme. The new scheme is, of course, not 100% reliable since accumulating byte results can be equal while the frame content is different. But it works quite well and an occasional "foul" is not fatal. It saves 128kb Block RAM and a few bucks for the FPGA chip.

author: morris6
author_rank: Regular Contributor
timestamp: March 03, 2025, 08:21:37 pm
content: Attached is a Zip file of the Quartus project as it is now. To save space in the zip the project is "cleaned", you will have to recompile. And anyway you'll have to adapt the project with your pin assignment. The compilation report gives that this design uses 226 logic elements, 163 registers and 133.376 memory bits in block RAM.This version has an INVERT pin, when this pin is connected to GND the display is black on white, like original. When connected to VCC it does white on black.This version has the display oriented so that the connecting FPC is on the left of the TFT. In fact the display is upside down here. Or, more precisely, rotated 90 degrees right considering that the long side is vertical according to the datasheet.To have the connecting FPC on the right side there have to be made some changes to the IP Parameters of inst34 src_hor_count. These are noted in comments shown in top.bdf. Also command C7 in the initialisation .mif file must be set to "reverse" in this case. And the order of the data lines must be reversed.Interesting files:top.pdf: for your convienience, it gives a picture of the schematic assembly with comments.cnt90qu5.qpf : the Quartus project file to open the project... for a Trenz MAX1000 development board with 10M08SAU169C89.top.bdf : the board file.trial0.mif : This is the memory initialisation file for the ST7701S COG controller, for the init_rom.

author: Smile2016
author_rank: Regular Contributor
timestamp: March 04, 2025, 06:38:10 am
content: A preliminary PCB real-estate study using BGA169 variant. PCB size 50*40mm

author: Smile2016
author_rank: Regular Contributor
timestamp: March 06, 2025, 05:03:46 pm
content: https://microtipsusa.com/mu_product/awl-400960t40n01/this is another compatible display available at major distributors. higher $$

author: Smile2016
author_rank: Regular Contributor
timestamp: March 28, 2025, 11:36:09 pm
content: Got my PCBs today! For the first time, something worked right out of the box. Took a bit of a gamble and used the 10M04SAU169 BGA version & it worked, re-flowed with a hot air station. Quick tip: avoid the Amazon 37$ USB Blaster V2 Download Cable (FT245 + CPLD) as Quartus won’t recognize it. Instead, any cheap FT2232H-based USB/JTAG will work if you configure the 93C66 EEPROM correctly. Let me know if anyone’s interested. Sharing some pictures—cheers! Thanks morris6 for great contribution !

author: morris6
author_rank: Regular Contributor
timestamp: March 29, 2025, 06:22:53 pm
content: Awesome, my congratulations with the board working first time, really well done.

author: Smile2016
author_rank: Regular Contributor
timestamp: March 31, 2025, 04:34:33 pm
content: unfortunately it does no longer work with Sharp microcontroller versions , newer PM6690s... some kind of Vsync is lacking...back to LOgic probe

author: morris6
author_rank: Regular Contributor
timestamp: March 31, 2025, 07:05:35 pm
content: Looking forward to see if there is a difference and what it is. Can you check that with the diagnostic page that you captured before?

author: Smile2016
author_rank: Regular Contributor
timestamp: March 31, 2025, 08:18:27 pm
content: I'm getting the setup ready, and flash the same instrument FW to make sure we have the same starting point..., ...The same firmware is compatible with both hardware revisions of the instrument. Data and its clocking appear identical, but other timing aspects seem slightly faster, with the frame rate at 4x. This might be an easy fix, or not. See attached log...

author: morris6
author_rank: Regular Contributor
timestamp: April 01, 2025, 08:33:41 pm
content: Amazing, these changes. Not so easy to adapt I’m afraid. But it’s obvious why my setup fails here…The frame signal, D5 green, now switches polarity every 12 lines. With the Triscend MCU it switches every complete frame of 97 lines between the first and second line. It looks like this signal is not used to synchronize screen content but for some LCD internal function.A complete screen now consists of 98 lines, one line without CLK pulses is added at the end of a screen.My setup uses the frame signal to detect the second line, this is not working here. The RAN pulse, D7 purple, EIO on J1 of the front pcb, looks to be originally “meant” to indicate the first line. To save on having to connect the replacement PCB with two ribbons I used the frame signal to synchronize the FPGA. A “smartass” shortcut that is punished here by Mr. Murphy.Maybe it’s possible to detect the first line by finding the one line gap in the CLK signal. Otherwise a bodge wire can be used to connect the RAN pulse from pin 19 of J3 in place of the FRM signal to pin 7 of J2.Of course several adaptations to the FPGA program are needed.To try out a solution I would have to create a simulation because I don’t have access to an instrument with Sharp MCU.

author: Smile2016
author_rank: Regular Contributor
timestamp: April 02, 2025, 04:01:33 am
content: Quote from: morris6 on April 01, 2025, 08:33:41 pmI just lifted pin J3.17 and connected pin J3.19 to the pad beneath it, with a piece of Kapton tape in between. Now I'm struggling to get a DFFlop working in Quartus - for some reason, I can only make one work when building it from scratch using NAND gates.There seems to be something else going on... maybe that "empty" 98th line?The fact that FRM and EIO are "walking", slightly frequency offset, might also explain the moiré visual interference pattern on displays driven by Sharp MCUs. Initially, I suspected the power supply or an issue with DC biasing, but FRM being in slowly moving phase relation with the rest might explain...what is looks lik is that EIO will be needed.I can confirm that using EIO instead of FRM, along with one additional line count in and an FF divider, allows the "blinky" cnt90qu3 version to work. I haven't been able to get cnt90qu5 working yet- the display remains white and occasionally shows some horizontally shifted, overlapping images.

author: zzattack
author_rank: Regular Contributor
timestamp: April 02, 2025, 07:37:29 am
content: Quote from: morris6 on April 01, 2025, 08:33:41 pmQuickly whipped mine open but it too appears a Triscend one, assuming it's about the larger IC right underneath the PSU. I'm happy to measure/test anything regardless, though my design skills aren't quite on your level.

author: morris6
author_rank: Regular Contributor
timestamp: April 02, 2025, 09:10:48 am
content: @zzattack,Thank you for the offer to assist.I will have to find some time to look into changing the setup to work with the EIO pulse. Hobby time is limited.

author: Smile2016
author_rank: Regular Contributor
timestamp: April 02, 2025, 05:08:38 pm
content: The simplest way to re-route EIO is by cutting pin J3.17 and then soldering a jumper between pads J3.17 and J3.19 (pins are next to each other). However, if you want to keep the option to revert to the original display, avoid cutting the pin and instead, use Kapton tape to isolate the J3.17 pad from the pin (see attached image).Looking deeper into the details, even in the Session 6.sal Triscend log, we can see that FR doesn’t align perfectly but remains stable enough over a full frame. This misalignment becomes more evident in Session7_SharpCPU.sal. The issue was likely overlooked due to the misleading signal name, "FR".On the other hand, EIO maintains perfect alignment across both processor types, even not identical position Sharp vs Triscend. A typical driver example is shown in the attached image.You can open .sal files using Logic 2 software from Saleae Inc., which is available for free download.

author: morris6
author_rank: Regular Contributor
timestamp: April 03, 2025, 08:16:12 pm
content: First thing was to simulate the signals of type B hardware, have these programmed now FWIW, see attached.Yellow trace is CLK, cyan is LD and magenta is the RAN or EOI pulse. Green is one of the data lines, the first two lines are black. Trigger point is on the leading edge of the RAN pulse that is valid during the first line of data.Next is to adapt the parser / controller section to the type B signals, work in progress.

author: Smile2016
author_rank: Regular Contributor
timestamp: April 04, 2025, 02:59:57 am
content: Quote from: morris6 on April 03, 2025, 08:16:12 pmQuick update: Type B hardware (Sharp CPU) is now operational and currently under testing. It uses the EOI pulse. Timing is right on the edge. The images below highlight the changes made to morris6's project.One thing still puzzles me: I couldn’t get a D flip-flop to trigger on the EOI pulse from the J2 pin as a clock input. I'll test tomorrow to see if this behaves differently with what we should call Type A hardware.both HW versions with identical FW 1.32 you can find at :https://www.eevblog.com/forum/testgear/fluke-pm6690-12-digits-frequency-counter/msg1740692/#msg1740692

author: Smile2016
author_rank: Regular Contributor
timestamp: April 04, 2025, 08:42:07 pm
content: one more finding ... USER OPT --> About --> Firmware Vx.xxs Sharp and Vx.xxt Triscenddid not try... yet ..*** IF THE FIRMWARE VERSION ENDS WITH AN "s", e.g. "V1.12s", ****** NEVER DOWNGRADE TO A FIRMWARE VERSION LESS THAN INSTALLED! ****** ****** IF SO, THE CNT-90 MAY NOT BE LOADABLE AGAIN ("BRAIN DEAD") ****** AND NEED TO BE SHIPPED TO FACTORY FOR REPAIR ***

author: morris6
author_rank: Regular Contributor
timestamp: April 15, 2025, 07:19:06 pm
content: Finally got my retrofit board assembled. The TFT is glued on the backside with a piece of double sided tape. And this assembly replaces the faulty LCD, using the original mounting points. As you see I have chosen for white on black display, this way it’s less visible that the TFT misses a bit of width left and right.Some pictures:

author: KungFuJosh
author_rank: Super Contributor
timestamp: July 22, 2025, 04:23:15 am
content: How is this project going?My screen is okay for now, but it has a suspicious dot on one side that implies I'll need this eventually.I have a CNT-90XL with 1.32sfirmware version.Thanks,Josh

author: coromonadalix
author_rank: Super Contributor
timestamp: July 22, 2025, 09:17:41 am
content: @morris6 can you drop/dim the brightnessseems pretty bright on the photo ?

author: morris6
author_rank: Regular Contributor
timestamp: July 22, 2025, 07:42:29 pm
content: @ KungFuJoshFor my CNT-90 version A hardware ( with Triscend MCU ) the project is working quite nicely. The adapted version done by Smile2016 for B hardware also works as far as I know. I don’t own an instrument with B hardware, I tried to build a simulation but that failed. I must confess I lost further interest after I assembled and mounted the designed PCB into my CNT-90.Attached is the KiCad project of my design, it should also work with the adapted version of the FPGA done by Smile2016 following his suggested modifications on the front board connector to get the EIO signal to replace the FR signal.

author: morris6
author_rank: Regular Contributor
timestamp: July 22, 2025, 07:44:12 pm
content: @ coromonadalixThe backlight of the display is taken from the V0 power for the original LCD. The voltage can vary 15 to 17.6 Volts by setting Contrast. If too bright decrease current with a somewhat larger resistor(s). The photo shows some “blooming” but in real life I think the brightness is just right.

author: KungFuJosh
author_rank: Super Contributor
timestamp: July 22, 2025, 07:49:26 pm
content: Quote from: morris6 on July 22, 2025, 07:42:29 pmThank you!I'll take it apart again and try and figure out which hardware version when I have time.I guess the S in the firmware version means Sharp = B hardware?Is the 20GHz option C in yours original, or aftermarket/DIY?Thanks,Josh

author: morris6
author_rank: Regular Contributor
timestamp: July 22, 2025, 08:24:49 pm
content: That’s what I guess as well, S firmware for the Sharp, type B hardware.The 20 GHz option is original, I guess a special for the militaries, the unit has an NSN number 6625 99 212 7932. It came partly disassembled in a rather sorry state, only one channel worked. The other main channel had the protection diodes blown. The C channel connector was missing and the 20 GHz board needed some repairs but it’s all working now as far as I can see…

author: KungFuJosh
author_rank: Super Contributor
timestamp: July 22, 2025, 08:44:54 pm
content: Quote from: morris6 on July 22, 2025, 08:24:49 pmDid/can you take any high resolution photos of the 20 GHz option? If I can't find something good available, I want to clone one.Thanks,Josh

author: morris6
author_rank: Regular Contributor
timestamp: July 23, 2025, 07:03:46 pm
content: At the time I did draw a schematic of the 20GHz option board, before my repairs. The PCB is marked Pendulum Instruments AB 4031 100 66570 - 01. For your reference the schematic is attached here.The prescaler was not functional and partly disassembled when I obtained the CNT-90. Traces of soldering on the coupling capacitors and the last divider stage HMMC3104 were looking “fishy” and indeed, no signal came out. I ended up with replacing it by a HMC365S8GE. There still was a problem as the first divider stage did not divide correctly. That chippie also proved unobtainable so I had to do some “artistic” soldering to bodge an alternative HMC494 in there, good for 18GHz.For now I only could find a photo of the result after the repair, at least it gives you an idea of what is involved to clone this board. It is mounted on two brackets over the main board. The bracket in the picture is not original, it was missing. Second photo gives a bit of an overview, it was during experiments with the TFT display retrofit.

author: KungFuJosh
author_rank: Super Contributor
timestamp: July 23, 2025, 07:19:31 pm
content: Thank you for sharing that!Hopefully, I won't need to go down the DIY route- Cojotech said he might resume product within a couple months. He has an 8GHz module that would be sufficient for my 6GHz needs.Thanks,Josh

author: bingo600
author_rank: Super Contributor
timestamp: July 25, 2025, 05:32:10 pm
content: Quote from: Smile2016 on March 28, 2025, 11:36:09 pm@Smile2016Would you care to share some details about making a:FT2232H-based USB/JTAG into a Quartus programmer (Blaster)TIA/Bingo

author: Smile2016
author_rank: Regular Contributor
timestamp: July 26, 2025, 12:15:18 am
content: @bingo600 FT2232H-based USB/JTAG design files are attached in ORCAD/ALLEGRO format + the GERBER files.For EEPROM programming, you can use MProg. don't touch PID/VID. I pre-programmed mine using the Black-cat tool.Note: When reading back with MProg, some bytes appear flipped, and the FT2232H seems to apply a CRC during the process.