Tutorial Video on Loop compensation and Simulation of a Flyback Part 1,2,3,4 - Page 1
Forum section: electronics / general

author: rbola35618
author_rank: Frequent Contributor
timestamp: December 01, 2012, 01:38:13 pm
content: Hi EEbloggers,Here is a tutorial video on how to model and set the feeback loop using a very simplified average model.I go step by step to show and demonstrate a method taught to me by my mentor Jack Alexander.I hope you find the video usefull.Feedback on the video are welcomed!Part 2:In part 2, I used the Basso's Current Mode switching model to verify Jack Alexander's Average Model. The results agree witheach other thus verifying Jack Alexander's modelPart 3;In part 3, I show how to use the Jack Alexander's model to simulated a Voltage Mode Forward Convert. I explain what a Type 2 and Type 3 Error amps are and when to use them. I go step by step in compensating a second order output filter and show how to damp a second order output filter. Also show how to use SPICE to plot the frequency response of the power supply's Output filter as well as the frequency response of the Error Amp.Questions and comments are welcome. Hope you find the video useful.Part 4 How to simulate multiple outputs.Robert

author: BravoV
author_rank: Super Contributor
timestamp: December 01, 2012, 01:52:31 pm
content: Thank you so much !

author: mazurov
author_rank: Frequent Contributor
timestamp: December 03, 2012, 05:32:15 pm
content: This is very interesting approach and works very well! I'm now trying to figure out how to apply it to the case of two fb paths like in the attachment.

author: rbola35618
author_rank: Frequent Contributor
timestamp: December 03, 2012, 06:57:06 pm
content: Hi MazurovThat is a good question. I will be doing a third video addressing questions like that. Once you have the basic AC model. You can use the model to calculate the poles and zeros instead of calculating them by hand.On the model, I used a 10 ohms resistor. On the top side of the resistor I labled it as "OUT" and on the bottom of the 10 ohms resistor I labled it as "IN".To get the response of the output filter, Move the lable "IN" to the control side of the VCCS. This will then allow you to plot the Poles and zeros of the Output Filter. Once you know what the poles and zeros are, you can match the Errors amp to match and cancel.You can also move the "OUT" label to the output of the error amp and leave the "IN" lablel on the bottom node of the 10 ohms resistor. When you do this and run the sim, you will get the Bode plot of the Error amp.I have attached the schematic of where to move the node lables to get both the Bode plot of the Output filter and Error Amp.I might be able to do the third video showing these modeling techniquesHope this helpsRobert

author: rbola35618
author_rank: Frequent Contributor
timestamp: December 03, 2012, 07:08:55 pm
content: Hi Mazurov,I now noticed that on your shematic, you are using R2 and C3 as a zero in parrallel with the R3. By adding this zero (R2 and C3) you are now using a Type 3 error amp which will have 2 poles and 2 zeros.If you are using a "Current Mode" PWM, you don't need a type 3 error amp. You only use type 3 errors amp if you need additional phase margin and typically this is used if you are using a "Voltage Mode" PWM.I will address that in the third video if I get I chance tonight.Robert

author: mazurov
author_rank: Frequent Contributor
timestamp: December 03, 2012, 07:59:03 pm
content: Looking forward to seeing the next video! :-)

author: rbola35618
author_rank: Frequent Contributor
timestamp: December 05, 2012, 05:26:35 am
content: Hi Oleg,The third video should be up soon. I found your website and I am checking it out. It very impressiveBest regards,Robert

author: rbola35618
author_rank: Frequent Contributor
timestamp: December 05, 2012, 03:11:52 pm
content: Hi EEVbloggers,I am adding part 2 and part 3 video link to keep the video links together.Part 2:In part 2, I used the Basso's Current Mode switching model to verify Jack Alexander's Average Model. The results agree witheach other thus verifying Jack Alexander's modelPart 3;In part 3, I show how to use the Jack Alexander's model to simulated a Voltage Mode Forward Convert. I explain what a Type 2 and Type 3 Error amps are and when to use them. I go step by step in compensating a second order output filter and show how to damp a second order output filter. Also show how to use SPICE to plot the frequency response of the power supply's Output filter as well as the frequency response of the Error Amp.Questions and comments are welcome. Hope you find the video useful.Robert

author: mazurov
author_rank: Frequent Contributor
timestamp: December 05, 2012, 07:13:13 pm
content: Thanks - this was very useful!My RC feedback is a little bit different - it samples before the output filter to make the loop response faster ( the output filter cutoff is at ~16Hz ). I'm reproducing your models in Ltspice and so far my results are similar. I have a question. Which PWM IC are you using in Basso model in part 1?

author: rbola35618
author_rank: Frequent Contributor
timestamp: December 05, 2012, 08:26:59 pm
content: Hi Masurov,I am using the Current Mode PWM to simulate the flyback that is shown in Video 1.Here is the Netlist of Basso's Current Mode switching PWM.Robert*Library: Models\BASSO_SWITCHED*.SUBCKT PWMCM2 3 4 6 2 5 1*$PINNAMES: COMP FB VOSC GND SENSE OUT+ PARAMS:+ REF=2.5, PERIOD=10U, DUTYMAX=0.8, RAMP=5V, VOUTHI=12V,+ ROUT=10, VHIGH=3, ISINK=15M, ISOURCE=500U,+ VLOW=100M, POLE=30, GAIN=31622, VOUTLO=100M, RATIO=0.333** Generic Model for Current Mode PWM controller* Developed by Christophe BASSO, France* PSpice compatible format* Last modified: October 25th 1996****** Generic PWM controller parameters ******** REF ; internal reference voltage* PERIOD ; switching period* DUTYMAX ; maximum duty cycle* RAMP ; ramp amplitude for compensation* VOUTHI ; driver output voltage high* VOUTLO ; driver output voltage low* ROUT ; driver output resistor***** Internal error amplifier parameters ****** VHIGH ; maximum output voltage* VLOW ; minimum output voltage* ISINK ; sink capability* ISOURCE ; source capability* POLE ; first pole in Hertz* GAIN ; DC open-loop gain (default=90dB)* RATIO ; maximum peak current at max output error level; (CM only)***********************************************XERR 10 4 3 2 ERRAMP PARAMS: VHIGH={VHIGH} ISINK={ISINK} ISOURCE={ISOURCE} ; error amplifier+ VLOW={VLOW} POLE={POLE} GAIN={GAIN}VREF 10 2 {REF} ; reference voltageELIM 500 2 VALUE = { V(3)*RATIO } ; max peak current = VOH*RATIO / RsenseXCOM 5 500 12 COMP ; limit comparatorXFFL 11 82 14 13 FFLOP ; flip-flopRDUM 13 2 1MEGVCLK 11 2 PULSE 0 5 0 1N 1N 10N {PERIOD} ; Clock set pulsesVRAMP 6 2 PULSE 0 {RAMP} 0 {PERIOD-2N} 1N 1N {PERIOD}VDUT 80 2 PULSE 0 5 {PERIOD*DUTYMAX} 1N 1N {(PERIOD-PERIOD*DUTYMAX)-2N} {PERIOD} ; max. duty cycle (=delay/period) delay=period-(tr+tf+tpuls)XOR1 11 14 81 OR2 ; Clock OR FFlopDXOR2 80 12 82 OR2 ; IMAX OR MAXduty ResetE_BOUT 15 2 VALUE = { IF ( V(81) > 3.5, {VOUTHI}, {VOUTLO} ) }ROUT 15 1 {ROUT} ; output resistor**** ERROR AMPLIFIER MODEL ****.SUBCKT ERRAMP 20 8 3 21 PARAMS: ISINK= 15M, ISOURCE=500U, VHIGH=2.8, VLOW=100M, POLE=30, GAIN=31622* + - OUT GNDRIN 20 8 8MEGCP1 11 21 {1/(6.28*(GAIN/100U)*POLE)}E1 5 21 11 21 1R9 5 2 5D14 2 13 DMODIS 13 21 {ISINK/100} ; mAQ1 21 13 16 QPMODISRC 7 3 {ISOURCE} ; uAD12 3 7 DMODD15 21 11 DCLAMPG1 21 11 20 8 100UV1 7 21 {VHIGH-0.6V}V4 3 16 {VLOW-38MV}RP1 11 21 {GAIN/100U}.MODEL QPMOD PNP.MODEL DCLAMP D (RS=10 BV=10 IBV=0.01).MODEL DMOD D (TT=1N CJO=10P).ENDS ERRAMP*$**** 2 INPUT COMPARATOR ****.SUBCKT COMP 1 2 3* + - SE_B1 4 0 VALUE = { IF ( V(1) > V(2), 5V, 0 ) }RD 4 3 100CD 3 0 10P.ENDS COMP*$**** 2 INPUT OR CIRCUIT ****.SUBCKT OR2 1 2 3E_B1 4 0 VALUE = { IF ( (V(1)>800M) | (V(2)>800M), 5V, 0 ) }RD 4 3 100CD 3 0 10P.ENDS OR2*$.SUBCKT FFLOP 6 8 2 1* S R Q Q\E_BQB 10 0 VALUE = { IF ( (V(<800M) & (V(2)>800M), 0, 5V ) }E_BQ 20 0 VALUE = { IF ( (V(6)<800M) & (V(1)>800M), 0, 5V ) }RD1 10 1 100CD1 1 0 10P IC=5RD2 20 2 100CD2 2 0 10P IC=0.ENDS FFLOP*$.ENDS PWMCM2

author: rbola35618
author_rank: Frequent Contributor
timestamp: December 05, 2012, 08:29:57 pm
content: For some strange reason, the V(eight) or v(shows up as a smiley face for the number eight. It should be node eight.RB

author: user_ivo
author_rank: Contributor
timestamp: January 01, 2013, 06:52:46 pm
content: Great Videos, very helpfull, in case of multiple output can we use the same approach to build the AC average model?

author: rbola35618
author_rank: Frequent Contributor
timestamp: January 02, 2013, 01:03:25 am
content: If you have multiple outputs you can use the same AC model. The capacitors and rload on the other outputs are converter thru the turns ratio of the transformer on the winding/output that you are closing the loop.I will add another video show how to do multiple outputs.Thanks for the feedback and question.Robert

author: user_ivo
author_rank: Contributor
timestamp: January 14, 2013, 06:45:27 pm
content: Is possible to use this model and simulate the RHPZ in case of a CCM Flyback, for what I understand this zero is not fixed in frequency and the frequency response of Flyback control to output is different. If i reduce the bandwidth of error amplifier i still possible to compensate the power supply? This could be an approach or a flyback topology is not use in this operation mode?Thanks,Ivo

author: rbola35618
author_rank: Frequent Contributor
timestamp: January 14, 2013, 10:31:46 pm
content: Hi Ivo,This model is a simple first order model for a Discontinuose Conduction Mode (DMC) flyback and does not simulate the RHPZ that is present in CCM flybacks. Basso has a model that can switch between both CCM and DCM. In compensating for the RHPZ, the rule of thumb is to set the crossover to 1/3 of the lowest RHPZ. The phase lag that the zero introduces makes compensation a little more difficult. I hope this helps you.Robert

author: user_ivo
author_rank: Contributor
timestamp: January 21, 2013, 11:44:38 am
content: "If you have multiple outputs you can use the same AC model. The capacitors and rload on the other outputs are converter thru the turns ratio of the transformer on the winding/output that you are closing the loop."By this you mean that final equivalent capacitor would be something like this:CE= (N2/N1)*Cout2+ (Nn/N1)*Coutn+ Cout1, in the case of closing the loop in out1, and he rload could we use the same formula.Thanks,Ivo

author: rbola35618
author_rank: Frequent Contributor
timestamp: January 22, 2013, 12:23:37 am
content: User_ivoYes this is correct. You can also use the ac model to extract the poles equivalent of the output filter as well as the zero. you can do this by bring the venable "in" from the bottom of the veneble reistor and place it on the input of the VSCS. This will give you the bode plot of the output filter. Then you just apply the same technique to match up the poles of the error amp to match the zero of the output filter, and match the zero of the error amp to match the pole of the output filter.Robert

author: przemo1268
author_rank: Newbie
timestamp: April 11, 2013, 07:46:15 pm
content: Hi Rbola35618,I'm trying to compensate feedback loop with usage Your method and I have a few questions. My switching power supply based on FSFA2100 device (half bridge, Fsw = 100kHz, Vin from 300 to 500 V DC (from PFC), Vout 6.5 to 13.8 V DC, Iout 15 A max). I use isolated feedback loop with optocoupler H11A817A and I have problems with correct compensation. AC Analysis shows that the system should be stable, but the real power supply don't work properly (is unstable). Well as the Transient simulation shows that the output voltage and current has oscillated (inductor working in discontinuous mode). What am I doing wrong? Does feedback loop with optocoupler should be designed differently? I have attached schematics and screens from simulations (I'm using LTSpice).Best regards, Przemo

author: rbola35618
author_rank: Frequent Contributor
timestamp: April 12, 2013, 03:08:50 am
content: Hi Przemp,Can you send the actual schematic so I can look and see if something was missed. Also, do you have a transient model? Send that as well if you have. By looking at the LT schematic, you are using voltage mode control and those are tougher to compensate. Can you send toRbola35618@aol.comIt is night time here in San Antonio Texas. I'll take a look at it tomorrow provided I can finish some stuff at work.Robert

author: rbola35618
author_rank: Frequent Contributor
timestamp: April 12, 2013, 07:27:00 pm
content: Hi Przemp,I was looking at the zip that you posted in the EEvblog. If you look at loop analysis where the opto was connected, it looks like it is stable but it not. When I first looked at this, I said it should be stable but it shows that it is not stable. Look at the right axis; it is not line up with the left axis. The gain is crossing at about 4khz. Then look at the phase at 4 KHz and you will see on the right axis that the phase is -10 degree. The phase margin should be at least 45 degrees to be considered stable. This shows instability.The model looks good. I will fix it a little bit and post here and also send you via e-mail.I am not sure if the PWM is current mode or Voltage mode. It does say that it has pulse by pulse current protection which inplies current mode. If it is current mode, then you can change the dependent source from VCVS to CCVS and remove the inductor.I just posted the attachment. I re-compensated the loop. See if these values make it stable.I hope it worksRobert Bolanos