JTAG/SWD level shifting - Page 1
Forum section: electronics / projects

author: ctrlaltmilk
author_rank: Newbie
timestamp: October 28, 2024, 04:24:40 am
content: I'm messing around with a JTAG/SWD debug probe idea I had, and I want to know if there's an "accepted" way of doing level shifting between the probe controller and debug target.From what I've seen both on an earlier thread and from other sources, the advice is to go with something like a 74LVC1T45 with a pin to control the direction rather than one that tries to do edge detection itself. What I'm mildly worried about is the number of pins; for JTAG there are 3 outputs and 1 input, while for SWD there is 1 output, 1 input, and 1 bidirectional data line.This means I'd either need to use 4 individual 1-bit level shifters, or 3 2-bit level shifters with unused bits. I'm reluctant to accept either of these options as optimal, but I can't find anything more affordable (for reference, both options end up costing about 1 USD).If anyone has advice or a cheaper option, please let me know - otherwise I'm probably just going to bite the bullet and use the 2-bit level shifters.

author: ataradov
author_rank: Super Contributor
timestamp: October 28, 2024, 05:52:15 am
content: You are forgetting reset. And you want reset to be tri-statable with an actual level sense.Otherwise, there is no better solution, you need to have shifters with bidirectional one for SWDIO line.Also, for an advanced probe it might be beneficial to tri-state all the signals when the probe is not used, since those are often multiplexed with other signals. So, whatever combination of level shifters you pick, need to have all pins bidirectional, even if you control them in groups.

author: ctrlaltmilk
author_rank: Newbie
timestamp: October 28, 2024, 06:05:54 am
content: Quote from: ataradov on October 28, 2024, 05:52:15 amWhy does reset need to be tri-state? I was planning on just using a MOSFET as a simple pulldown, since I assumed the reset line would always be pulled up on the target board.Quote from: ataradov on October 28, 2024, 05:52:15 amI know that I need a bidirectional shifter, I'm just wondering if there is some chip out there with independent directional control per bit so I wouldn't need 4 separate ICs or wasted bits.

author: ataradov
author_rank: Super Contributor
timestamp: October 28, 2024, 06:15:37 am
content: Quote from: ctrlaltmilk on October 28, 2024, 06:05:54 amYou can probably get away with a pull-down, but you still want to sense the level. Some devices will keep the reset asserted for some time after it was released externally and you need to sense that to tell when it is safe to proceed. Depending on the programming software, it may expect valid reset readback.It may be a rare use case, but if I'm working on a universal probe, I'd implement that. If budged id the main consideration, then it is probably fine to skip that.Quote from: ataradov on October 28, 2024, 05:52:15 amNot that I'm aware of. Usually people just place individual ICs per signal. 74LVCH1T45GM,132 is 17 cents @ 100 pcs. Even if you use 5 of them, it is 85 cents.And this is likely not the cheapest one, I bet there are way cheaper devices on LCSC.Here is SN74LVC1T45DBVR for 6 cents @ 150pcs -https://www.lcsc.com/product-detail/Translators-Level-Shifters_Texas-Instruments-SN74LVC1T45DBVR_C7843.htmlAnd there are a lot of similar devices at about the same price.

author: jbb
author_rank: Super Contributor
timestamp: October 28, 2024, 06:18:13 am
content: It’s for test gear, so I wouldn’t sweat it about wasted bits or using a number of small ICs. That being said, it’s good to keep the number oftypesof IC down where possible because it makes life easier for parts supply & maintenance.Extra for power electronics people: how about an electrically isolated SWD probe?

author: Postal2
author_rank: Frequent Contributor
timestamp: October 28, 2024, 06:34:46 am
content: Quote from: ctrlaltmilk on October 28, 2024, 06:05:54 amSWDIO should be considered as an I2C bus SDA signal which is very easy to level match. I usually pull SWDIO up to 3.3 via a 750 ohm resistor.

author: ataradov
author_rank: Super Contributor
timestamp: October 28, 2024, 06:36:11 am
content: Welp, Postal2 showed up and posting nonsense again.Unlike I2C, SWD is fast and level matching it requires fast bidirectional level shifters. Plus on debug probes it is multiplexed with JTAG pins, so you still need real level shifters.

author: Postal2
author_rank: Frequent Contributor
timestamp: October 28, 2024, 06:49:46 am
content: Quote from: ataradov on October 28, 2024, 06:36:11 amMaybe. Probably because I work with it and don't just talk about it.

author: ctrlaltmilk
author_rank: Newbie
timestamp: October 28, 2024, 08:12:35 am
content: Quote from: ataradov on October 28, 2024, 06:15:37 amI saw that device family on Digikey but only looked at the LVC variant, which requires pullup resistors. Thanks for the tip!Quote from: jbb on October 28, 2024, 06:18:13 amThat's a fair point - the premature optimization bug might have bitten me again. Going to stick with the 74LVCH1T45GM for now.Quote from: Postal2 on October 28, 2024, 06:34:46 amWhat I'm mostly concerned about is accidentally frying a 1.8V FPGA by backfeeding power through its I/O lines. Even through a 750ohm resistor that can't be too healthy for stuff at a low voltage...

author: Postal2
author_rank: Frequent Contributor
timestamp: October 28, 2024, 08:31:12 am
content: Quote from: ctrlaltmilk on October 28, 2024, 08:12:35 amOf course, you don't have to connect directly. Any FET translator will do, like the lsf0204.https://assets.nexperia.com/documents/data-sheet/LSF0204_Q100.pdf