EEVblog #496 - What Is An FPGA? - Page 1
Forum section: electronics / general

author: EEVblog
author_rank: Unknown
timestamp: July 19, 2013, 11:32:13 pm
content: What is an FPGA, and how does it compare to a microcontroller?A basic introduction to what Field Programmable Gate Arrays are and how they work, and the advantages and disadvantages.FPGA Stuff in Dave's Amazon store:http://bit.ly/1ayoNiV

author: synapsis
author_rank: Regular Contributor
timestamp: July 19, 2013, 11:34:00 pm
content: Excellent! Just what I was hoping to see! And just in time for dinner...Thanks Dave.

author: xrunner
author_rank: Super Contributor
timestamp: July 19, 2013, 11:42:47 pm
content: Quote from: synapsis on July 19, 2013, 11:34:00 pmAgreed. I will view this tonight!

author: JoannaK
author_rank: Frequent Contributor
timestamp: July 20, 2013, 12:46:42 am
content: Nice video.. Like the endingMore seriously.. Yeah, FPGA.s are darn complex and versatile beasts. Have done *some* tinkering but I know I don't really know a **** about them.Funny thing about fpga:s is that if you mess the code part, you may burn the chip. There's simply not enough cooling (normally at least) to allow all the lines/registers to toggle at max clock speed 100% time.What I like most is, when they combine FPGA:s with genetic evolutionary programming.

author: Zad
author_rank: Super Contributor
timestamp: July 20, 2013, 02:45:07 am
content: Nobody mention the spelling mistake at the top of the whiteboard!It reminds me of the lift in the electronic engineering building at Leeds Uni, there's a big red button on the panel that says EMERERGENCY. Glancing at it, you know it is wrong somehow, but your brain won't say what's actually wrong.

author: CrosseyeJack
author_rank: Contributor
timestamp: July 20, 2013, 03:38:07 am
content: What would you guys suggest for a noob when it comes to fpga's too just learn the basics with? A brief history, I'm used to building my own circuits, using pics/atmels in a breadboard for prototyping my own circuits and then designing and moving my projects onto their own PCBs around the micro controller. So I'm not scared to break out the soldering iron.Its not that micro controllers are no longer cutting it for me (for what I do they are more then enough right now) I'm happy with CCS C and PIC micros with my current projects, But fpga's are something I want to dip my toe (even my recent broken toe) into at some point so I'm looking for an affordable piece of kit I can use to learn with. I don't mind building something (my first ardunio was just a atmega on a breadboard) but if I can get an affordable dev kit I have no problems in doing so just as long as I can break it out and its not going to be a right royal pain in the arse converting it into its own pcb when I want to move it onto its own standalone project.Its my first post on the board so be gentle. I would love some feedback in pointing me in the right direction in getting started with FPGA's.Many thanks in advance.Dan.

author: EEVblog
author_rank: Unknown
timestamp: July 20, 2013, 03:44:09 am
content: Quote from: CrosseyeJack on July 20, 2013, 03:38:07 amThe Papilio and DE0 Nano are two dev boards under $100, Xilinx and Altera respectively.http://papilio.cc/http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=593

author: ataradov
author_rank: Super Contributor
timestamp: July 20, 2013, 04:12:59 am
content: Some pointers for people who want to start with FPGAs:1. Simulators are extremely accurate in "post place and route" mode, enough to develop the entire project without programming a chip even once. So the only real reason to buy a board is to have that cool feeling when the first LED blinks on a real hardware.2. There is an open-source simulator called iverilog (for Verilog only, obviously). It works on Win/MAC/Linux, really fast and easy to use. The benefit of using it on the initial stages is that it is possible to use your favorite IDE and not an IDE from the chip vendor, which are sort of slow and not all that great.

author: CrosseyeJack
author_rank: Contributor
timestamp: July 20, 2013, 04:29:24 am
content: Thanks Dave. Looking at them I'm tempted to just get both.While I'm more of a "lock me in a room, throw me in at the deep end and don't come out until I have at lease a hello world running" kind of guy. I do like the idea of the fall back option of the Arduino compatible Soft Processor on the Papilio. At least I would be at least to get something running on the thing :-P though I don't want to fall into the trap of just using it as an Arduino. I'll have to flip a coin to see what to get, but at the cost of each its hard not to just get both. Though I do feel myself drawn towards the Xilinx system.ataradov as for the simulator. It sounds like a good plan even if its just to see if I will put the time into it. But I've always been a physical person when it comes to electronics every since I got a 200-1 kit from Tandyhttp://www.amazon.co.uk/200-1-Electronic-Project-Lab/dp/B000LRCD6Qas a Christmas gift and ended up creating a short circuit and burning a bigger hole on the 9v spring (oh that brings back memories). So the buzz from getting an led flash goes deep :-)Thanks all. Looks like I will be ordering at least one new "toy" in the next few days :-)

author: 99tito99
author_rank: Regular Contributor
timestamp: July 20, 2013, 04:38:45 am
content: Some of the old players may find it “blablabla” but, speaking as a new player I thought it was a good intro, but what the hell do I know I’m just a newbie. Look forward to another video or two. Cheers

author: Odysseus
author_rank: Regular Contributor
timestamp: July 20, 2013, 05:28:21 am
content: One of the common practical uses of FPGAs in the industry is to emulate digital hardware that will eventually be sent off to be taped out and turned into an actual chip, especially when it needs to interface with complicated analog hardware, either externally or on the same silicon die, that is difficult to simulate accurately in tandem, with all the non-ideal, second-order effects common to any analog design.The great thing that after the HDL is written once to be tested in simulation on a computer and in emulation on an FPGA, then the exact same HDL code is used to design the final hardware. The HDL code also gets used again when your chips come back from the fab and you need to debug it's internal operation.And it gets really crazy when you're developing a device with an embedded micro-controller, many times with specialized DSP functionality. Before going to tapeout, during simulation and emulation, you can watch how every instruction you program affects every single bit inside your processor, which itself was just previously programmed in HDL and can still be adjusted. It's programming on a whole other level.And after that you get to program a compiler...

author: John Coloccia
author_rank: Super Contributor
timestamp: July 20, 2013, 05:39:07 am
content: I spent some time working with Xilinx FPGAs configured with a "soft core" and surrounding circuitry. This combination has more power and flexibility than you could imagine if you've never done such a thing. You can concentrate on getting the inputs and outputs correct with the basic design, and then work out the details of your control architecture later. This is the future of embedded engineering, if it's not already the present. It's what software engineers have been talking about for decades when they talk about "abstraction", but implemented at the hardware layer too.So you can do things like decide, more or less in the FPGA design, how you're going to divvy up things like control loops, stepper algorithms, comm channels, etc etc. All you have to do at the board level is make sure that the signals coming in and out of the FPGA are electrically compatible with your needs, and some time later you can decide on the actual implementation details. It completely blurs the traditional boundaries of software and hardware.

author: AlfBaz
author_rank: Super Contributor
timestamp: July 20, 2013, 06:08:54 am
content: It's interesting that only the surface has been scratched in this video in regards to FPGA's in that it would take another hour long video to just scratch the surface of a given HDLIf you have any programming background it's difficult at first to get your head around the "parallelism" of HDL and then deciding between behavioural and structural programming. Not to mention which language to take up, Verilog or HDL.

author: EEVblog
author_rank: Unknown
timestamp: July 20, 2013, 06:13:14 am
content: Quote from: John Coloccia on July 20, 2013, 05:39:07 amTell that to Altium, who bet the entire company on the future of FPGA's. They were wrong, and failed miserably.Even the FPGA vendors have admitted soft functions aren't the universal holy grail everyone was predicting. They are integrating more and more hard functions and processors within FPGA's.

author: ataradov
author_rank: Super Contributor
timestamp: July 20, 2013, 06:18:39 am
content: And as for not thinking which pin goes where - recently more and more microcontrollers include very advanced pin routing facilities.I think Xmega E5 has some sort of FPGA-like level of glue logic between the core and pins. I have not looked how advanced it is.Most Cortex MCUs can map peripherals to different pins.You still need to think when designing stuff.

author: EEVblog
author_rank: Unknown
timestamp: July 20, 2013, 06:22:55 am
content: Quote from: ataradov on July 20, 2013, 06:18:39 amThe Microchip 24F series have had that for a long time. It's not completely flexible, but still very usefulQuoteYes, even with FPGA's.

author: John Coloccia
author_rank: Super Contributor
timestamp: July 20, 2013, 06:57:21 am
content: Quote from: EEVblog on July 20, 2013, 06:13:14 amI'm not sure what you mean. The point of having an FPGA is the ability to create the hard functions you need on the fly. That's not to say that there isn't merit in having some dedicated, optimized circuitry to do certain operations, but that's just a refinement of the basic concept.

author: ve7xen
author_rank: Super Contributor
timestamp: July 20, 2013, 07:31:38 am
content: Quote from: John Coloccia on July 20, 2013, 06:57:21 amI think the point is that a great many designs were using the same blocks, which is not cost effective. You waste a couple 1000s of logic blocks on a softcore, but especially at the low end, what you're paying for those blocks is not competitive with an external mcu by a long shot. You get the flexibility of internal interfacing, but it's expensive and you're probably not going to do that unless you need a special interface for tight timing or whatever, instead you inflate your BOM and board size and add a micro, or add 50% to the parts cost,Putting more 'common' hard peripherals, much the same way as microcontrollers have a variety of peripheral complements, uses the expensive die space more effectively, and thus drives the cost down for things many customers are going to need anyway, and would otherwise use lots of expensive configurable logic on. Fast SERDES and the like probably aren't doable at all with the configurable logic. Makes sense to me, it's just optimizing the die usage versus what customers need. Given the complexity of even a simple FPGA, throwing a simple CPU core on there is probably not costing much, and you can help the designer eliminate an external uC or use a smaller and cheaper FPGA, while having better interface options. That sounds like an easy design win.I doubt 'pure' FPGAs are going anywhere, but adding some more onboard capability seems like a fairly obvious evolution. If lots of users are including a small microcontroller (soft or external) in their designs, why not throw one right on the die that will satisfy most of them and save them money and time.

author: Bored@Work
author_rank: Super Contributor
timestamp: July 20, 2013, 07:52:00 am
content: Quote from: John Coloccia on July 20, 2013, 06:57:21 amYou missed a lot of things. Lets take just one. Let me say it in a simplified way:FPGAs are difficult, while the average programmer is stupid.You have at one hand a need for more and more embedded programming work (e.g. for the *cough* internet *cough* of *cough* things *cough*). And on the other hand you have a proliferation of barely capable programmers. So you need tools, concepts, systems, programming languages, etc. that don't ask too much from these programmers. At least if you want to get some kind of mediocre output at all at affordable cost.FPGAs don't fit the bill for these people. And these people are the majority of what you get these days. They need guidance, not the flexibility to create functions on the fly. They need simple tools, not the mess FPGA vendors provide as their tool chains(1). They need simple concepts and dumbed-down programming languages. Do I like the proliferation of stupidy in the business? No, but that's the way it is.FPGA as the future of embedded engineering? Nop, won't happen because of a lack of embedded engineers capable of handling them.--(1) Guess why these tools are such crap? Because the vendors don't and can't invest in really skilled programmers and engineers capable of designing and writing good software.

author: elektronicks
author_rank: Contributor
timestamp: July 20, 2013, 09:16:34 am
content: "technical life gives birth to monsters" was one of the quates i remembered.fpga is an example of this monstruosity. why embeding, why making it faster ? how long do you think integrating, embeding until you reach to the final usable limit of the cosmos / universe / this space - temporal dimension and give up in front of infinity ?assholes from IBM thought ohhh.. let's make an atomic memory, each atom holding one bit - and then hires somebody to "produce" or "edit" videos like this guy going around on how science and technology will make the human life better.beeing all relative - faster and slower, bigger and smaller, discrete or integrated only means control over others is beeing passed from one group of people to another for a short period of time while they are dreaming about their accoumplishments in the field.dave playing the violin in a certain group: new modern independent high tech cutting edge online job ...with a highly stage managed and controlled smile to fit the motto: "entusiastic and passionate"ogh.. o by the way: we can't care less about how video editing takes place. it all sucks because of the above mentioned points.that puts the fpga into perspective.. and you imagine: there are some tousands, maybe hundred of tousands of engineers going to a 8 hour job thinking how the fuck we will integrate the clock because their slave masters told them to do it, otherwise they will have theirs asses kicked out.fuck electronics man.. it is all a fucking big sickness. since humans discovered semi-conductivity, the porn started.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 20, 2013, 09:27:08 am
content: Quote from: Bored@Work on July 20, 2013, 07:52:00 am..and the mistake people often make is not understanding that FPGAs are NOT about programming. HDLs are NOT programming languages.You need to approach it with the mindset of a hardware designer. An experienced hardware designer with minimal software knowledge would be way better placed to get into FPGAs than even a good software person with minimal hardware knowledge.

author: KedasProbe
author_rank: Frequent Contributor
timestamp: July 20, 2013, 09:54:38 am
content: Maybe next time you can cover the difference with CPLD (although maybe you should have started with it)

author: John Coloccia
author_rank: Super Contributor
timestamp: July 20, 2013, 10:47:49 am
content: Quote from: Bored@Work on July 20, 2013, 07:52:00 amAny EE with half a brain can handle Xilinx's design tools. I don't know what to say about your assertion that engineers are almost universally stupid. Maybe all the engineers sitting around making Chinese clones of toasters and electric bug zappers aren't the best of the best, but most of us aren't doing that, and I'll bet dollars to donuts that most of us aren't even doing consumer devices. The guys I've worked with over the years are pretty damn competent and able to do their jobs, and if you're an EE in 2013, dealing with FPGAs is something you're expected to be able to handle.re: everything else, and "HDLs are NOT programming languages".Apparently, no one seems to understand the concept of a soft core. You configure a portion of the gates on the FPGA as a general purpose processor that you can then hand off to the embedded software engineer and he can program in C/C++ (or whatever is available). The EE and SE work hand in hand to divvy up the task, configure the processors for exactly what they need with whatever co-processors they need, setup the interfaces between them, etc.So I can get 2 months into it and say, "Hey, you know what? What I could REALLY use is for you to monitor these 10 inputs, mux them, and set bit anytime one of them triggers. Filter it a bit for me too", and in a few minutes we can reconfigure the hardware to do just that. And then a week later I can say, "You know what would work better? Instead of setting a bit, please increment this word, and I'll decrement when I've serviced it.". What you have is a chip with a custom processor surrounded by custom hardware and interfaces designed by you and for you.Maybe there's 5 million theoretical reasons you can come up with why that doesn't work, yet in the real world I've done it time and time again with tremendous success. It's probably overkill for a toaster, but then again what isn't? You just have to put on your big boy pants and learn how to use a couple of simple tools, but as a pro that's what you're expected to do.re: cost and stuff like thatI suspect that most engineers and most projects are not consumer projects and the cost of an FPGA is really not all that significant. In fact, other than the work I'm doing now with my own business, I'd have to think hard if I EVER worked on a shrink wrapped consumer product, or even know anyone who has. I believe the answer is no. A friend of mine works for iRobot but he doesn't work on those cute little vacuum cleaners.

author: robrenz
author_rank: Super Contributor
timestamp: July 20, 2013, 12:49:59 pm
content: Quote from: wilfred on July 20, 2013, 12:36:49 pm+1

author: Rasz
author_rank: Super Contributor
timestamp: July 20, 2013, 12:54:37 pm
content: Quote from: John Coloccia on July 20, 2013, 10:47:49 amand here lies your problem, You suspect wrong. Market is all about optimization of cost. Altium bet on FPGAs taking over design, but FPGAs are expensive, and dedicated hardware will ALWAYS BE CHEAPER. Not to mention thanks to globalization its cheaper to hire 100 chinese/indian monkeys to code complete works of William Shakespeare than to pay living wage to 3 CS/EEs on staff.

author: EEVblog
author_rank: Unknown
timestamp: July 20, 2013, 12:57:35 pm
content: Quote from: KedasProbe on July 20, 2013, 09:54:38 amI did contemplate starting the video working from GAL's/PAL's to CPLD, to FPGA's, but figured it would ultimately take too much time. I was right, because I waffled on for 37min on just FPGA's

author: EEVblog
author_rank: Unknown
timestamp: July 20, 2013, 01:02:15 pm
content: Quote from: wilfred on July 20, 2013, 12:36:49 pmI just hit the manual exposure button on the board and then walk into frame. The white balance could be slightly off maybe (I leave it set the same for the rest of my lab shooting), but the colour of the whiteboard looks ok to me on my main monitor, but it does depend upon the monitor I use. The whiteboard is not in an ideally lit location.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 20, 2013, 01:14:21 pm
content: Quote from: EEVblog on July 20, 2013, 12:57:35 pmNot sure there's much point in this - the history and architectural detail isn't that important as HDL hides most of it - GALs are pretty much obsolete, and CPLDs can for most purposes just be thought of as much smaller, cheaper variants of FPGAs, with onboard config & core voltage regulators.

author: daqq
author_rank: Super Contributor
timestamp: July 20, 2013, 01:52:24 pm
content: Dave: Good video, thanks, the next time someone asks me the question, I'll refer them to your video.Quote from: elektronicks on July 20, 2013, 09:16:34 amWell... but... what? I mean... urm... where to start? Are you serious, or just, I don't know, hitting your head against the keyboard and looking what that does?

author: c4757p
author_rank: Super Contributor
timestamp: July 20, 2013, 01:58:55 pm
content: Quote from: elektronicks on July 20, 2013, 09:16:34 amAny chance you're from Colorado or Washington?

author: xrunner
author_rank: Super Contributor
timestamp: July 20, 2013, 02:08:38 pm
content: Quote from: elektronicks on July 20, 2013, 09:16:34 amI can't wait till we invent true A.I., so we can just tell the thing to make itself smarter by re-inventing itself over and better, and telling the resulting thing to do the same, lather - rinse - repeat, and sit back, finally having nothing of importance left for mankind to accomplish.

author: John Coloccia
author_rank: Super Contributor
timestamp: July 20, 2013, 02:15:51 pm
content: Quote from: Rasz on July 20, 2013, 12:54:37 pmThere's a reason FPGA starts keep going up. I can design one basic architecture with some basic IO on it, and then keep reusing that over and over and over and over again, just tweaking a bit here and there, adding a little here, removing a little there, etc etc. You're stuck thinking about high volume production. I'm starting to wonder if you understand how much engineering is done that DOESN'T target a high volume consumer market?For the record, I'm not trying to be argumentative here. There is just a huge amount of embedded engineering that is done where it doesn't matter one bit if a part cost $3 or $300. It is completely and utterly dwarfed by a team of engineers, billing out at $100+ an hour, for 6 months. Whatever gets you to the finish line soonest and with the greatest chance of success is by far the cheapest solution.

author: lgbeno
author_rank: Frequent Contributor
timestamp: July 20, 2013, 02:52:07 pm
content: Quote from: Rasz on July 20, 2013, 12:54:37 pmThis is almost entirely true, the only counter point that I would attempt to make is that as digital electronics move to deeper into submicron processes, a single piece of silicon needs to address bigger and bigger market with the same mask set due to the need to recover the costs associated with development. Particularly eda software, design engineers and the actual mask set. FPGAs are already flexible enough to span a very broad range of applications that may take a family of 10-20 processors to address. With that said, I still agree it will either be a long time coming or wouldn't hit mainstream.About programming model. The value proposition of fpgas to hardware guys is very clear. Trying to find a micro with 5 uarts, a can port, 50 io, ddr2 mem and hdmi video that fits your cost target might be impossible but quite trivial in an FPGA.Most true software engineers who I've worked with dislike fpgas because they don't think in HDL, they think in sequential c code and would prefer to leverage reference code from an os or open source instead of hand crafting drivers for the custom HDL you just optimized for a specific application. This is why software guys latch onto arm because it is a sophisticated, pre defined and tested ecosystem. Saves ALOT of hardware vs software finger pointing. With an FPGA you have to validate and test all of your own work, with a hard processor they have already done that (and published errata for what they missed)With all of that said, I'm a hardware guy and love FPGAs... Keep the videos coming!

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 03:24:25 pm
content: Quote from: ataradov on July 20, 2013, 04:12:59 am1) simulators are killjoy's... note more fun than seeing led's blink, especially when getting started.2)the IDe of the vendor is orders of magnitude better than the kludged together 'roll your own environment'. for 2 reasons :reason 1 : it knows the EXACT behavior of the selected fpga timingwise. something that open-sauce stuff will never be able to do as that info is proprietary and vendor dependentreason 2 : the vendors ide works 'out of the box'. download, install ,run. draw a few gates, write some lines of hdl , click 1 button and done. when entering the complicated world of FPGA's there is no need to make it even more harder by having first build your environment.

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 03:29:12 pm
content: Quote from: elektronicks on July 20, 2013, 09:16:34 amyou need to lay off the strongly activated rosin-core flux... it's wreaking havoc above your nose...

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 03:30:15 pm
content: Quote from: EEVblog on July 20, 2013, 12:57:35 pmand you forgot to erase top left the config memory that sits in a cpld. where in fpga it is external ...

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 03:34:34 pm
content: Quote from: xrunner on July 20, 2013, 02:08:38 pmscrewa AI. we need FPGA's with telepatic interfaces. here's why :- simple pcb design all you need is power and ground ( or you could stick a solar cell on the back of the package. no routing needed.- since they are telepatic they are all interconnected- since they are telepatic : no compilers, simulators and other junk needed. i simply think ' i need a spi port here and a decoder that drives a led display with pwm dimming. as i am thinking the fpga reconfigures itself ( it's telepathic so it can do immediately what iam thinking about )that's the future. and were almost 99% there. we got all the bits , it's just that damn telepatic interface ... i'll have to get back in my lab , let me grab my tinfoil hat with coathanger ( the hat collects my brainave and the coathanger emits them ) and see if i can pick em up with me DE0 board ...

author: xrunner
author_rank: Super Contributor
timestamp: July 20, 2013, 03:38:19 pm
content: Quote from: free_electron on July 20, 2013, 03:34:34 pmAh yes - TPGAs (Telepathically Programmed Gate Arrays)Seriously, the video helped me understand this device immensely - thanks Dave.

author: Winston
author_rank: Regular Contributor
timestamp: July 20, 2013, 04:16:39 pm
content: Fantastic video! Looking forward to more. Idea for a geek t-shirt - a large graphic of a human brain with "FPGA" and/or "Field Programmable Gate Array" under it.

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 04:22:35 pm
content: now, all the joking aside.FPGA's have their place in medium volume applications where the design of full custom is too expensive , and the standard stuff available is simply too cumbersome as it would make the system physically large.Another field is the area where not all criteria are known yet but design needs to start. Simply slap in an fpga and as the design evolves , adapt it. We'll deal with it later...You will find fpga's in oscilloscopes from one-hung-lo ( because they don't have the money to go full-custom) to Agilent ( if there is an afterthought they can simply release a new config pattern and expand capabilities and lifetime of a product.The idea of having soft-cores is indeed dwindling down. It is counterproductive and wastes gigantic amounts of cells in the fpga. The best solution is to take a standard microcontroller or microprocessor and pair it with an FPGA. Some fpga vendors are now offering fpga's with hard-cores ( cortex ) in em. That is the real future.I have been using microcontroller/fpga combos for a long time. Instead of screwing around trying to get the cpu to do some very difficult , because timing related, task and jump through hoops i simply offload that to the fpga.Doing this allows for fast and simple code on the cpu and fast and simple code in the fpga. A cpu has its strenghts and an fpga has its strengths. Combining the two is a win-win situation.Now, on the development front : while fpgas are internally incredibly complex in terms of interconnect and partitioning , you are almost completely shielded from that by the development tools. Even for medium to large size designs you will never have to dig into manual constrianing , timing closure and other 'nasties'. I have designs running in FPGA , clocked at 200MHz. I didn't do a single timing analysis in the entire design. I didn't even simulate it. The fpga is fast enough to cope with this. my design is partitioned so that control signals govern the passing of information between blocks. The control signals are written in such a way that they are active at least one clocktick later than the data is steady. the only tricky bit where ismulation was needed was an arbitration system and the domain crossing. those things are difficult. but if you design fully syncronous logic in 99% of the cases it will work without having to fidget with the complex bits.If you take a cheap fpga and i give you the task to do the following :Make me a LED display driver for those 14 segment displays( starburst ) that can drive a 16 character display , multiplexed, with pwm dimming , character decoder and a spi interface this may sound overwhelming.in reality the implementation is very simple and you can design block by block , try the block in a simulator , and then move to the next block.spi interface :lets assume we do a 16 bit transfer : first 8 bits hold '0000' followed by a 4 bit character address , next 8 bit hold the character code0000_1001_0110_0101 as spi transfer would mean :------ 9 6 5 : character 9 is 0x65here we go :Code:module spi(input MOSI,CLK,CE, output char[7:0], input address[3:0])reg [7:0] char0,char1,char2,char3,char4,char5,char6,char7,char8,char9 ... // we need 17 herealways @(posedge CLK)if (!CE) beginshifter[15:0] <= shifter{[14:0,MOSI}; // if CE is low : shift MOSI in to a shiftregister controlled by the CLKendelse beginif case (shifter [11:8])4'b0000 : char0 <= shifter[7:0];4'b0001 : char1 <=shifter[7:0];... do this for the 16 possible combinationsend// look ma : i just made an SPI slave device that can take in a 16 bit command word, decode it and store the data in 16 registers...// now how do we get the data out to process it internally ?// wellalways_comb begincase address[3:0]4'b0000 : char = char0;4'b0001 : char = char1;.. contine the decoder her for all 16 locationsend caseendendmodulethere you go. a block in the fpga can now randomly access the stored characterloaded through SPI...oh. wait dimming .. we had 4 empty bits right ? let use the first bit to switch between 'loading text' and setting options..if i was breadboarding this with chips this would be an 'oh fuck' moment... but since this is an fpga... piece of cake:Code:module spi(input MOSI,CLK,CE, output char[7:0], input address[3:0], output reg brightness[7:0]) // add an 8 bit output for brightnessreg [7:0] char0,char1,char2,char3,char4,char5,char6,char7,char8,char9 ... char15;always @(posedge CLK)if (!CE) beginshifter[15:0] <= shifter{[14:0,MOSI}; // if CE is low : shift MOSI in to a shiftregister controlled by the CLKendelse beginif shifter brightness <=shifter[7:0]; // if the bit is set : it's brightnesselse // if not : its characters.case (shifter [11:8])4'b0000 : char0 <= shifter[7:0];4'b0001 : char1 <=shifter[7:0];...4'b1111 : char1 <=shifter[7:0];end caseend// look ma : i just made an SPI slave device that can take in a 16 bit command word, decode it and store the data in 16 registers...// now how do we get the data out to process it internally ?// wellalways_comb begincase address[3:0]4'b0000 : char = char0;4'b0001 : char = char1;.. contine the decoder her for all 16 locationsend caseendendmodulenow, purists are going to say : you could have made an array of chars , you could have done away with the if shifter and simply made a biger case statement testing for the bit there like so:case shifter[15:8]8'b1000_0000 : brightness < ...8'b0000_0000 : char0 < ......8'b0000_1111 : char15 <...in the end it all doesnt matter. yes you could write it more compact, cleaner but the end result will be EXACTLY the same. this is different form writing software. in software: the more lines of code you plonk down the more instructions you end up with and the more clockcyles the cpu will take to execute it.in an FPGA this is NOT the case. Your brainfart gets translated in logic equations. These get expanded first , minimized and mapped in a lookup table. The end result is : 1 clocktick to do all that crap. Irrespective of how you wrote it, longwinded, elegantly, purist format, doesn't matter. The language statements all create boolean logic. if the source ended up with a very long equation , or a short one doesn't matter , after logic minimizing both will yield the same solution, simply because there is only 1 solution in the logic domain for a given problem.so now we have access to the stored characters... how do we scan them..well, a counter selecting one of them and sending it to the decoder and selecting the common line of one of the display.Code:module scanner( output reg address[3:0], output columns[15:0])always @(posedge clk) beginaddress <=address +1; // no need for other code. when we hit 1111 it will roll to 0000. basic nature of flipflop logicendalways_comb begin // make me some combinatorial crap herecolumns[15:0] == 16'd1 << address; // make only 1 bit high , bit is determined by value of 'adress'endif i now to the address lines of this module to the address lines of my spi block , the spi block will spit out the recieved characters in sequential order. at the same time my outputs select one of the column drivers in the display.all i need is a character decoderCode:module starburst (input char[7:0], output bitmap[13:0]beginalways_comb case char[7:0]8'd65 : bitmap = 11_0000_1000_1010 // bitmap for letter 'A"8'd66 : bitmap = 11_1001_1001_1001 // bitmap for letter 'B'.. and so ondefault : bitmap = 00_0000_0000_0000 // anything we didnt define : display nothingend caseendmoduleconnect the char bus together and you are done. this thing will scan the characters, decode the character into the appropriate LED bitmap , select the reight column and drive the leds'.oh.. dimming... well i leave that up to you : simply throw in a counter that gets loaded with the dimming value and counts down. if the counter is larger than dimming value : pas the bitmap , if it is lower : force the bitmap to all 0. this is imply a small block between the output of the starburst module and the real led pins.along the lines ofpwm = pwm+1if (pwm > brightness) bitmap_out = 0 else bitmap_out = bitmap...so in a few lines , each in a very simple step i have created a fairly complex bit of logic. it reads an SPI datastream , decodes instructions and data, stores it , scans the stored information , decodes that into character bitmaps , pwm's the output and drives a 16 character 14 pixel led display...that is a VERY complex thing if you were to try doing that with loose ttl or cmos chips.... the schematic alone is a nightmare. working out all the equations is a nightmare , soldering it is a nightmare.plonk down an FPGA, think a bit what you need , partition it in simple chunks, write some simple code and leave the rest to the synthesizer. it will work out all the details.do i need to do timing analysis for the bove ? hell no. That spi clock is 16Mhz. The FPGA laughs at that ...the character decoder may be large and have some trouble , but, since the display is scanned at a much slower pace you wont even see it there. you could simply throw in another latch ar inject a deadtime between character transients to mask that off.it ain't something to be scared of

author: FrankBuss
author_rank: Unknown
timestamp: July 20, 2013, 04:54:38 pm
content: Quote from: lgbeno on July 20, 2013, 02:52:07 pmI'm a software guy and I love FPGAs tooIn VHDL you can even use variables, procedures, functions and loops. But you have to keep in mind that it needs A LOT of logic units, because a loop is kind of unrolled and synthesized in parallel, same for procedures and functions. You have to sequence it with state machines from time to time, when it gets to big or when the timing requirements are not met anymore because of too long logic chains. Hardware guys don't like my VHDL code

author: lgbeno
author_rank: Frequent Contributor
timestamp: July 20, 2013, 05:47:32 pm
content: Quote from: FrankBuss on July 20, 2013, 04:54:38 pmSoftware guys who write HDL are the best!

author: TheWelly888
author_rank: Frequent Contributor
timestamp: July 20, 2013, 06:06:00 pm
content: Thanks Dave for the video. You have made the difference between FPGA and microcontrollers clear for me.I noticed the thumbs up count climbed by 13 during my viewing

author: Corporate666
author_rank: Unknown
timestamp: July 20, 2013, 06:19:21 pm
content: Quote from: free_electron on July 20, 2013, 04:22:35 pmFree_Electron is such a huge resource to this site. Loved reading the post, as always.

author: John Coloccia
author_rank: Super Contributor
timestamp: July 20, 2013, 06:20:38 pm
content: Quote from: free_electron on July 20, 2013, 04:22:35 pmEither way. I don't think the softcore is the essential feature. Pairing SOME processor with an FPGA is the essential ingredient.And as you so clearly show later on, you don't "program" the gates in an FPGA. It would actually be better to think of it as combining certain patterns that you know will translate into specific gate configurations. If you think of it as programming, you'll quickly get into trouble. Specifying it in Verilog is far more convenient than drawing out some sort of schematic language, just because it's easier to actually see exactly what's going on when it starts getting larger and complex. It's really best, though, to still think in terms of the basic building blocks that get created on the FPGA, and to simply know the common patterns off the top of your head.

author: Winston
author_rank: Regular Contributor
timestamp: July 20, 2013, 06:50:50 pm
content: Quote from: Zad on July 20, 2013, 02:45:07 amA bug or a feature of our evolutionary programmed grey matter FPGAs?

author: Winston
author_rank: Regular Contributor
timestamp: July 20, 2013, 07:09:04 pm
content: Quote from: EEVblog on July 20, 2013, 12:57:35 pmI definitely wouldn't consider it waffling. It was beautifully concise and well organized and I learned a great deal. Pleasecontinueon the subject in any direction you feel to be most productive.

author: tru
author_rank: Regular Contributor
timestamp: July 20, 2013, 07:37:37 pm
content: Nice video Dave. Softcore CPU I think for a FPGA defeats the purpose of FPGA use. What I understand (in real world terms) is that the FPGA is like a programmable DSP where you can process input signals with many operations all in parallel or due time before the signal changes, but a softcore CPU does things in sequence so one could (as many do) simply use an external ARM CPU with the FPGA.There are cases where a microcontroller (MCU) or CPU just won't be able to do the job of the FPGA, that is without it being many times faster than the input signals. A good example is the digital triggering detection in an oscilloscope of let's say for arguments sake at 100 Mega samples/s and that we don't want to miss any samples until a trigger occurred. At 100MSPS the ADC is capturing each sample at 10ns. Let's suppose we tried to use an ARM CPU and it executes instructions at 100MHz (suppose each instruction runs at 10ns), now, when the if conditional runs to check for a possible trigger it will be missing the next ADC sample of input! Even worse if you have multiple if conditions to do, more samples are missed, before the ARM even has a chance to process the first input sample!

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 07:47:59 pm
content: now , to give you another example of what is possible and within reach of everybody. a friend of mine , possibly known to some of you. his name is foto_opa. he's the guy doing those insect pictures.Retired electronics engineer, never really did anything with cpu's nor fpga during his lifetime. was kinda hesitant to roll into it. he had tried on his own but basically got nowhere. VHDL was too hard to figureout. so , on another forum i kinda pitched in and gave hime some simple examples. splitting a problem into little blocks , code them up. no overloading him with how to instatiate blocks , nor explaining how to do testbenches etc. that was for later ...Toplevel : schematic. Yes, laugh all you want. going from raw to cooked is not instantaneous it takes time. Take little steps, use stuff that is familiar. It is great to have a toplevel schematic representation that shows you how blocks are connected. Doubleclick on a block and there is the code for it. You can make nice hierarchical designs that are navigated by schematic. Very easy to understand for anyone who has ever looked at an electronics circuit. You can even plonk in any part from a collection of premade TTL chips.He bought the DE nano board and some others from terasic.You should see his photography setup. The entire system has multiple lasers that pinpoint where the insect is, he uses linear ccd's to measure reflection of light and positioning within a frame , uses another module that calclates focusing , calculates light and exposure , drives a lcd display, reads buttons. All that stuff runs without a single cpu. It is pure hard logic going flat out.to give you an idea : if the photodiodes detect reflected light from the lasers he has under a microsecond to perform the finding of the insect in the focus aperture, do the calculation , fire the shutter and the strobes.The calculations done are immense. He is sampling linear ccd's, averaging them , performing peak detection , and much more. The number of instructions needed for that on a sequential processor are in the many thousands... not a problem you way..well it is, especially if you tell that processor , you have 1 microsecond to execute this bunch of instructions... if your cpu neeeds to do 1000 instructions , and it needs 2 clockticks per instruction and it has 1 microsecond to execute them .. you need to clock it at 2 GHz ! or faster. and you havent even moved data yet ..Throw that at the little PIC or AVR and this is what will happen :it will jump out of its socket , scamper to the far corner of your circuit board , roll over on it's back , curl up it's tiny little legs and simply die...the FPGA ? all that thing does is go 'meh' ... you need to do averaging on 16 samples each 256 bits wide and perform a peak detect on them ? in 1 microsceond ? let's see. 16 samples is 1/16 of a microsecond each. Tree reducing from 256 to 1 takes 6 clocks (to find which cell has the highest value. so with 1/24 of a microsecond i can do this.. just clock me at 24 MHz and i will give you the peak of the averaged signal....that is the power of parallel processing and massive amounts of custom hardware. things a cpu takes thousands of instructions the FPGA does in a few clockticks , simply becasue it parallelizes the problem. if your cpu has no hardware multiplier on board you are stuck with emulating this with a software routine. if your fpga has no hardware multiplier , and you need one , you build one and move on...you can;t add something to a CPU that is not there ... in the FPGA ? not a problem. that's what the damn thing is for.http://www.flickr.com/photos/fotoopa_hs/this is the machine doing it :http://www.flickr.com/photos/fotoopa_hs/sets/72157627714453063/driven by a single cyclone FPGA.

author: marshallh
author_rank: Unknown
timestamp: July 20, 2013, 07:55:29 pm
content: FPGAs are very handy when you need them.They are really only suited for niche applications, but keep in mind there are a LOT of niches.I would add some things:1. Simulation - it's great if you are building a completely self contained module where you can directly constrain the inputs and outputs. Something like an internal DSP filter, framebuffer processor, etc. For interfacing with things like DDRx memory, external PHYs, glue logic, etc you are going to be forced to develop in tandem with the physical part. It's what I prefer anyway.2. Internal constraints - Low-cost fpgas ($<200-300) have Fmax limitations usually around 130-150mhz. It gets very hard to clock logic faster than that. If you have a small functional unit you could spend time pipelining and optimizing by hand (and in the case of xilnx ISE, manually placing elements sometimes) and approach 200mhz. For something more complex like a 5stage pipelined MIPS core you would be lucky to break 60-70mhz. The process of hand tuning the code/constraints/routing until you achieve your desired clock speed in that unit is called "closing timing". You will either have gap/slack in propagation delay.3. Understand the architecture of the FPGA you will be using, enough to know how your logic is getting mangled to fit in these elements. Recognize patterns in how the fitter is allocating resources. Then you can avoid writing constructs that cause excessive logic utilzation and kill your timing margin.4. Read, read, read. I see questions from people using silicon they have obviously not read any datasheets about. You may have to read 1000-1500 pages of chapters in the FPGA handbooks to fully undesrtand what you are dealing with, especially if you are designing one into a PCB.5. The mental "jump" of getting your brain to think in terms of synchronous, parallel hardware description takes time. I know people that took several years to fully grasp it. Some caught it in several months (those that were building glue logic with 74xx parts and GALs). It took me over a year to understand what it was all about.6. CPUs and FPGAs - There are some problems that can ONLY be solved with a CPU. The converse is also true. The best design is one that has BOTH a cpu and fpga in it, with each doing what they are best at. This is also USUALLY the cheapest option. Embedding a softcore in your fpga is a good way to burn logic usage, necessitate a more expensive part, and still be inferior to dedicated silicon. The only advantage is when you want augmented instruction sets. For example, would you want to write verilog that parses a FAT32 filesystem? HELL no! It can be done, with tens of interlocking FSMs. It can also be done with a couple kilobytes of compiled C code almost painlessly. And samely, doing hashes, crcs and dumb transforms are blindingly fast in logic. Complete pipelined SHA hash coming out every 1 cycle? Possible. Not so in a CPU. Once you are exposed to enough algos/concepts you'll discern where to plop each one.7. Xilinx vs Altera - let me say right out front that I greatly prefer Altera tools. Having used both vendors tools --Altera: slightly more expensive/less bleeding edge silicon. Parts are better characterized, much fewer silicon bugs that need to be worked around. Quartus II design software is very well integrated, consistent, minimal foot-shooting. Free Signaltap logic analyzer you can embed.Xilinx: slightly cheaper parts, may have faster I/O or special options. Silicon bugs are common, some are show stoppers (Virtex-5 PCIe hard IP is quite broken). For 6 series parts and below, ISE is required. ISE is a flaming pile of bug ridden crap, an amalgamation of separate software absorbed into the parent company over the past 10 years held together with duct tape. Even Xilinx reps admit it sucks. Bugs causing poor device fitting are common, early versions compiled on random seeds so you could fail timing one compile and pass the next. However for 7 series +, everything was retooled for the Vivado suite, which I hear is quite a step up, and supports more commonplace things (Like systemverilog, which ISE doesn't)I would use Altera for protos/low volume, Xilinx for high volume where the one time cost of extra pain in ISE pays off among units sold.Lattice makes FPGAs and low power CPLDs also. They bought SiliconBlue a few years ago which has tiny FPGAs that draw microamps current, and come in 0.4mm BGAs. Their upper end ECP3 line is pretty competent and well priced. Diamond design software uses external Synopsys compiler and is not as well integrated as Quartus.Actel/Microsemi make radhard/flash based parts. The tools are on par with ISE, but the parts are very cheap. You also need to buy in volume.

author: c4757p
author_rank: Super Contributor
timestamp: July 20, 2013, 08:03:09 pm
content: Quote from: marshallh on July 20, 2013, 07:55:29 pmAmen! I thought I hated working with FPGAs when we started working with Xilinx ones in school, but I'm using a Cyclone in a current project and the whole toolkit is a joy to work with.

author: FrankBuss
author_rank: Unknown
timestamp: July 20, 2013, 08:18:30 pm
content: Quote from: tru on July 20, 2013, 07:37:37 pmThe power comes from the combination of FPGAs and CPUs. In a complex system usually you have something like slow user input, controller logic, USB connection etc. Implementing this in a HDL is a waste of FPGA logic elements, because even for a simple USB device module you would need maybe a FPGA which costs $40 instead of $20 for the rest of your project, so just add an external $3 microcontroller with hardware USB and you are done.For scanning slow user input and controlling the system, a soft core might be good for the same reason. Implementing all in a HDL means that you need logic elements for each function you want to implement, and all functions are available in parallel, driven by state machines, because there is no partial reconfiguration of the FPGA (at least not for the cheaper parts). Using a simple soft core like NIOS saves lots of logic elements. Then a NIOS program can configure the functions you've implemented in the FPGA. For example you could implement a VGA generator and a multichannel audio mixer (I've done both, AES3 as audio input/output, up to 192 kHz, 128 channels in parallel) in the FPGA, and a NIOS program implements the drawing functions in the framebuffer, reads the keys or a mouse and configures the routing matrix and mixing coefficients.

author: marshallh
author_rank: Unknown
timestamp: July 20, 2013, 08:21:51 pm
content: Here are some tips I wrote for some guys working with me on a project. Some of it is specific to Verilog, some is general synchronous logic consideration.http://retroactive.be/verilog_tips.pdf

author: tru
author_rank: Regular Contributor
timestamp: July 20, 2013, 08:28:01 pm
content: Quote from: FrankBuss on July 20, 2013, 08:18:30 pmI see, good point, you're very right. I didn't want newbies to be confused with the differences of what FPGA vs microcontroller or CPU can do, people here adding in softcore muddles the comparison I think.

author: Salas
author_rank: Frequent Contributor
timestamp: July 20, 2013, 08:45:19 pm
content: Its nice how they emulate old computers on FPGA

author: FrankBuss
author_rank: Unknown
timestamp: July 20, 2013, 09:00:56 pm
content: Quote from: Salas on July 20, 2013, 08:45:19 pmCool old skool demos. It is not easy to implement a working Amiga, which plays demos correctly, because demo programmers used all the undocumented features of the hardware. Do you know that there is even a "making of" for the first "State of The Art" demo?

author: Salas
author_rank: Frequent Contributor
timestamp: July 20, 2013, 09:19:02 pm
content: Piece of history that video indeed.

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 09:30:04 pm
content: Quote from: c4757p on July 20, 2013, 08:03:09 pmthird that !the problem with xilinx is that they don't care. Their target is the medium ot large company that wants to use 'the beasts'. anyone playing at that level uses Synopsys as a frontend and uses the fusemapper as a backend. done. nobody in that playfield uses ISE.Altera does care about the low end to mid range market as that is where their bread and butter is. so they differentiate by making good tools.

author: WarSim
author_rank: Frequent Contributor
timestamp: July 20, 2013, 09:32:17 pm
content: Quote from: ataradov on July 20, 2013, 04:12:59 amI am working in an area where FPGA etc is not an option, but for some of my own projects a small fabric based solution would be very helpful. I have a little experience on the subject when GALs where new. Currently I have been waiting for and looking for a viable option.For home I have used almost every OS out there and over the decades have decided not to use Windows and have consolidated most of my computers to OS/X. Frankly I prefer not to use my time managing an OS like I had to with MS, I prefer to just have the OS work with seldom management. Before MS fanboys attack I am not interested in comparing credentials etc, I don't care how much you love your Winblows. This is my choice, deal with it.So I have been waiting a long while waiting for an OS/X hosted fabric toolchain. In the mean time I have been using other solutions like analog processing or PIC multi-processing. The down side is some projects are a bit large. No matter how you place then a dozen PICS take up allot of room.I have read the links to iverilog, it doesn't seem to be the entire tool chain. Is there a complete tool chain for OS/X yet? Better yet is there a FPGA or CPLD manufacturer that is working on an OS/X suite?

author: FrankBuss
author_rank: Unknown
timestamp: July 20, 2013, 09:39:42 pm
content: Quote from: free_electron on July 20, 2013, 09:30:04 pmXilinx has some entry level FPGAs as well, like the Spartan series, with the Spartan 3 even cheaper than comparable Cyclone chips. But I agree, ISE is more difficult to use than Quartus and once I had even a crash in the fitter for a perfect valid design, which I could only fix by adding some dummy logic. Never had such a problem with Quartus.But Quartus is also not bug free: once I had a problem where a state machine was synthesized wrongly. I needed some hours to verify that it was indeed a bug of the synthesizer, because usually you trust such tools more than your own code. But the Altera support was really good, they provided a hot-fix for it. Was an older Quartus version, something 6.x.

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 09:42:00 pm
content: @warsim : in short: NOBODY. and nobody cares. Mac's are not for engineering. period. like it or not. that's the way it is.plonk parallels on it load winxp or win7 on it and get the toolchains. It's that or stay in the dark ages.writing this on a 27 inch Mac...i use MAC for anything web, photo , and some video.Anything engineering ? windows... there's no escaping it.and Lunix is not feasable either. There are toolchains for Atera and xilinx but its endless misery getting them to work right. you need distro xyz with library blablabla ... sneeze and you may break it. The linux version work perfectly fine in managed environments for very large projects where you do an exact install as per the tool manufacturers request ( mostly RHEL .. ).For any other linux flavor: you are on your own. Fine if that is your liking to tinker more with the computer than be productive.i got FPGA's to program , not fidget with linux installs. i don't care about the Os. I care about getting the application up and running so i can be productive. Windows is still the easiest there.

author: c4757p
author_rank: Super Contributor
timestamp: July 20, 2013, 09:48:44 pm
content: Quote from: WarSim on July 20, 2013, 09:32:17 pmSorry, but that's just retarded. Stick Quartus/ISE/whatever in Parallels or dual-boot Windows or Linux. The amount of time you actually spend dealing with the software can be minimal. You don't need it to edit Verilog. You're going to try to use a dozen freaking PICs for parallel tasks because you don't like "Winblows"? I don't like it either but I can boot into it when I want to use my logic analyzer or universal programmer or any number of other things that require it. I just take one Benadryl for the allergic reaction and all is good@f_e, just my experience, but Quartus works a treat on the latest Debian with no effort.

author: John Coloccia
author_rank: Super Contributor
timestamp: July 20, 2013, 10:15:00 pm
content: Quote from: free_electron on July 20, 2013, 09:30:04 pmThat's not true. I've worked with ISE and had great success, most recently at Northrop Grumman....which counts as "large", I believe. Everyone complains about ISE, but I never found it to be particularly problematic. A bit clunky, and perhaps a bit buggy, but certainly not the steaming pile of crap people are making it out to be.

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: July 20, 2013, 10:21:09 pm
content: Quote from: free_electron on July 20, 2013, 04:22:35 pmYou must have typed it faster than speed of light :-)shifter[15:0] <= shifter{[14:0,MOSI};should beshifter[15:0] <= {shifter[14:0],MOSI};also 'encase' is a single keyword. I just could not look at broken code even if it is just to give an idea. I am a programmer as you may noticed.Most importantly I see you are using 'always_comb' which is only available in Sytemverilog. I found support for Systemverilog in tools like Xilinx ISE and Altera Quartus is spotty and inconsistent. Synopsis is the only company who's tools support Systemverilog in full, but I know that only from rumors since I never used Synopsis tools myself.I have read an article at EEE Spectrum magazine saying that FPGA developer skills will be one of the most sought after in coming years. Today I see only 2 (two) open positions related to FPGA in Toronto and they were there for ages, not sure if they are real. It did no became as popular as some anticipated. However use of FPGAs in sub millisecond stock trade systems and oil exploration had very impressive growth - they can afford it.Despite all the progress in tools developing with FPGA still very hard and expensive. Once you have HDL code and try to run it you discover that it runs at 68MHz instead of expected 210MHz, why?!? to fix it you need to dig into 2000 pages of datasheets and app notes. You find things like synthesized RTL logic has too much fanout in one place screwing your timing, then simultaneous switching if too many cells causes problem in another part of device. Then you switch device or recompile and all problems are back but in different places... nice abstraction that tools promised to provide falls apart completely.

author: Rasz
author_rank: Super Contributor
timestamp: July 20, 2013, 10:46:08 pm
content: Quote from: John Coloccia on July 20, 2013, 02:15:51 pmSo what you are saying is FPGAs are perfecty for those one off projects where cost doesnt matter? Thank you for agreeing with me

author: ElectroIrradiator
author_rank: Frequent Contributor
timestamp: July 20, 2013, 11:12:55 pm
content: Quote from: free_electron on July 20, 2013, 07:47:59 pmThat comparison doesn't sound quite right?It should be obvious that a $5 AVR or PIC 32 bit MCU isn't going to compare well to a Cyclone IV. If today your hobbyist FPGA setup is in the form of a $100 DE0-Nano board, then shouldn't you rather compare it to the likes of a *pair* of Beagle Bone Blacks, at $45 each, for computational and I/O power? A pair of those might still be far from adequate for your friend's nifty Flycatcher, but it is now a much more level playing field in the general case.Similarly, if you are doing high end DSP work with a FPGA, then I would think your basis of a bang-for-the-bucks comparison should be some of TI's dedicated DSP CPUs? Last I checked, admittedly quite a while ago, those critters screamed through the stratosphere at hypersonic speed. What they lacked in the FPGA's parallelism, they made up for with GHz range clock frequencies and VLIW architecture.

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 11:15:11 pm
content: Quote from: Alexei.Polkhanov on July 20, 2013, 10:21:09 pmFeel free ro correct typo's. i haven't sent the code throught the synth. My typing is very bad. Especially on an ipad. We need spellcheckers for verilog !Quartus supports systemverilog constructs like always_comb , always_ff and always_latch. It also allows you to declare the reg and wire in the io block as opposed as having to rewrite it in the body.Also the .notation for signal reference in instances is supportedI always use the systemverilog mode. Less typing, less typo's.Anyway, the code demo i gave shows how you partition a task in manageable chunks , and the. How you write with a few lines what it needs to do. That display driver is a fairly large block of logic , yet the creation of it takes a few minutes if you are proficient at splitting a job in pieces and making the pieces. The coding itself is minimalistic. The synth does all the hard work.That is the message i am tryingto convey: FPGA are not difficult (despite what dave claims). They are incredible fun and tremendously powerful. Don't be scared. All the 'fud' about timing closure, smoking chips, is just that. You will run i to that in very large designs. If you stay at speeds an order of magnitude below what the fpga can do you will never run into that.

author: free_electron
author_rank: Super Contributor
timestamp: July 20, 2013, 11:21:14 pm
content: Quote from: ElectroIrradiator on July 20, 2013, 11:12:55 pmYour beaglebone couldnt even poll and drive its gpio fast enough to sample the ccd inthe given timeframe. You will need to bitbang the ccd access as it is nonstandard protocol. The moment the last sample is in you have one more clocktick to spit out the result .... Even that beagle bone will curl up like the wicked witch of the west and scream'i'm melting' while curling up its tail...You cant do it with software. Simply because the number of instructions is so large and there is no time. The only option is hard logic doing it. That's what hard logic is for: to assist the cpu with things that simply take too much time. Offload that.The people at Cray have figured that out long ago. Their supercomputers are a mix of fast cpu , gpu and fpgas. If something can be done extremely fast in hard logic they map the logic in.

author: WarSim
author_rank: Frequent Contributor
timestamp: July 20, 2013, 11:34:11 pm
content: Quote from: c4757p on July 20, 2013, 09:48:44 pmI have tried various virtual machines but not Parallels, dual boot is not an option for me.I have tried several took chains and none worked completely in any virtual machine.In the past I have purchased various Windows licences but all had issues with sharing with OS/X.I have one Win7 install, but now I know I have to bring it out of sleep 1hr before I need it for all the care it needs. It is attached to my PCB mill and I have auto updates disabled but it does them anyway in the middle of jobs, if I don't spend the hour before hand. Yes I have had several others attempt fixing this and several other issues, yes fresh installs have also been tried. These are the quirky issues that I prefer not to deal with. BTW I am talking about preference not a phobia, like you seemed to assume.This is the only area of EE that my preference has caused a limitation, I really don't consider it "retarded"Besides none of these sharing options are officially supported and iffy if they will work. Therefor requires at least a $400 risk. Only way to find a working solution is response like your derogatory reply.BTW: I used "dozen" as an example, using multiple uC or processors is not unusual. The most uC was 18 and most of those where 6 pin PIC10s used as remote signal converters. Even if I used FPGAs it would still require 6 due to location requirements.So, which version of Windows and Parallels works with Quartus and Lion?

author: c4757p
author_rank: Super Contributor
timestamp: July 20, 2013, 11:52:38 pm
content: Why is dual boot not an option?The auto-update glitch is a problem that nobody else has. PEBKAC. No idea why nobody else can figure it out, but I promise you, you have the same code on your Windows disc that I have, and it doesn't do that for me...No idea which version of the software would work, but I've used Quartus in VirtualBox before and it worked fine, so I don't know why it's not working for you. Maybe some quirk these emulators have running on Mac? I don't know, I haven't had a Mac in years. Obviously running it in an emulator isn't an option if it doesn't work, but my experience hasn't shown that. Has this been a problem for anyone else?Sorry, I didn't mean for my reply to be "derogatory", I was at least partially joking! The "Benadryl" comment wasn't meant to be sarcasm, it was a concession that Winblows indeed does blow. I just don't see why you can't use it once in a while...

author: ElectroIrradiator
author_rank: Frequent Contributor
timestamp: July 21, 2013, 12:12:25 am
content: Quote from: free_electron on July 20, 2013, 11:21:14 pmI already said as much in my previous reply, the BBB may very well not fit your friends purpose. I get it, OK?My point was that you should compare the FPGA to something like a BBB (or two!), not to a sub 100 MHz AVR or PIC MCU, when deciding what will or will not fit in a MCU/SoC.The core of the AM3359 on the BBB runs at 1GHz, and the chip's EMIF can cope with 400 MHz DDR3 interfaces (800 MHz data rate). It is also able to drive a HDMI output (via a glue chip). I haven't tried to check how fast it can toggle it's GPIO pins, but it must be reasonably fast.I am sure there are still many situations, where an FPGA would run rings around the BBB. However, the boundary for when you can bitbang an interface and process data in real time has been pushed dramatically farther out, compared to using a PIC or AVR.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 21, 2013, 12:35:09 am
content: Quote from: c4757p on July 20, 2013, 11:52:38 pmThere is little need for it when there's VirtualBox, VMware, and other VM software. The main exception is when you need every bit of performance or when you're dealing with direct hardware access. Even then, there are hardware accelerated virtualization solutions, though I haven't really looked into them.I have set up the Xilinx ISE to run on Gentoo. I can't remember the last time I started up my Windows XP VM, since Linux does everything I need it to do at home.And yeah, mixed architecture is very often the way to go in complex projects. Since that involves using multiple IDEs at once, plenty of RAM and as many monitors as your PC can support are a good idea.

author: WarSim
author_rank: Frequent Contributor
timestamp: July 21, 2013, 01:08:52 am
content: Dual boot isn't an option due to how I setup my network. I want to keep my security protocol but don't want to use LAPD.I just did an search throughout the web on the FPGA and CPLD world.Looks like the Quartus web is what I should try. It's seems free but say XP/2000, hopefully it will work on Win7. I don't want to buy another licence yet. I also figured out an easy way the get my Win7 computer out of my mill for use. Just can't use my PCB or 3d printer while I use Quartus Web.Nice to see the packages are DIY friendly, all the TQFP are .5mm.Found a prices for the USB blaster was a bit dear, but found a MAX II CPLD dev kit for half the price that includes a USB blaster.In my wandering I also found some DIP CPLDs by Atmel are these any good or useful.Any one want to recommend a low range FPGA dev kit, that uses this Quartus Web software?

author: lgbeno
author_rank: Frequent Contributor
timestamp: July 21, 2013, 01:40:13 am
content: Just get the de0 nano.

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: July 21, 2013, 02:04:07 am
content: Here is my CycloneIII prototype board that I made year and a half ago. I remember I cut my finger badly while trying to drill a hole in SMT adapter to connect bottom pad of the QFP to the ground. Whole bunch of decoupling caps soldered on other side (not shown). Chip in the corner is CPLD, MAX from Altera - I killed it by reprogramming too many times. Rainbow ribbon cable toing to ADC extension board that only works at 10-15MHz due to lack of bus transeivers and poor signal integrity.Still I had much more fun with this design than with complete dev board - I can solder and un-solder things at will.

author: WarSim
author_rank: Frequent Contributor
timestamp: July 21, 2013, 05:20:30 am
content: Quote from: lgbeno on July 21, 2013, 01:40:13 amGreat I will look that one up.

author: WarSim
author_rank: Frequent Contributor
timestamp: July 21, 2013, 05:29:14 am
content: Quote from: Alexei.Polkhanov on July 21, 2013, 02:04:07 amThe dev board is to test the software setup. Once I can confirm the OS quirks are not going to get in the way. I will make an experiment board with the smallest FPGA it can support.Just because putting a project in a huge chip isn't a big enough challenge for me. The most fun I have had with PICs was figuring out how to make a 6 pin PIC10 do more with so few pins and low power. And lately put a display driver in a PIC24, when everyone I have run into says it has to be done in an FPGA or dedicated display driver IC.

author: Rubi
author_rank: Contributor
timestamp: July 21, 2013, 08:07:48 am
content: Awesome introduction.Please bring more of this stuff.http://rubines.blogspot.co.at/

author: AndyC_772
author_rank: Super Contributor
timestamp: July 21, 2013, 08:36:11 am
content: Quote from: WarSim on July 21, 2013, 01:08:52 amThe genuine Altera USB Blaster cable is stupidly expensive, but I've had no problems at all with a couple of 3rd party copies from China that cost next to nothing. Some of them also come with a handy little Cyclone II dev board that has a voltage regulator, configuration device and crystal on it, and all the FPGA pins broken out to 0.1" headers.For example:http://www.ebay.co.uk/itm/Altera-CycloneII-EP2C5T144-FPGA-Board-USB-Blaster-JTAG-/121104246158?pt=UK_Computing_Other_Computing_Networking&hash=item1c3260258e

author: Chet T16
author_rank: Frequent Contributor
timestamp: July 21, 2013, 09:00:54 am
content: My $50 saleae logic analyser clone can be configured as a USB blaster

author: jahonen
author_rank: Super Contributor
timestamp: July 21, 2013, 09:04:26 am
content: Quote from: FrankBuss on July 20, 2013, 04:54:38 pmI am a hardware/VHDL/Altera guy and I absolutely do not like the style VHDL is usually (at least what I have seen too many times in my work, so excuse my mini-rant) written.Why everybody seems to insist on writing "clk'event and clk='1'" instead of more clear function "rising_edge(clk)"? Another thing is that most (V)HDL designers seem to be fans of cryptic magic numbers expressed in most inconvenient base and use them everywhere in the code which makes it unnecessarily difficult/impossible to maintain and reuse. For example, try to change clock frequency of a design which has clock cycle counts embedded that way in the code to produce a certain timing in seconds. Another thing is that use of variables (depending on the context, variables can be a "wire" or a "reg" in verilog terms) as "local signals" in processes seem to be non-existing, which would make it easy to duplicate/reuse the process without inventing new signal names or doing other refactoring and cluttering the design.Most of the time the functions, procedures, records etc in VHDL do not actually make any more complex logic result, but they make the code much more readable and reusable if used properly.Oh, and one simple pitfall of the FPGA design is that any external asynchronous signal, i.e. a signal which has no guaranteed timing referenced to a clock which FPGA logic is internally using, must be synchronized (using a chain of DFF's) separately to the internal clock. Failing to do that can cause much head-scratching (been there, done that!), as the system might react in completely unexpected way to that. If one looks at IO structures of a MCU, there usually is this kind of structure, so with MCUs one can live happily without ever stomping on this issue.Regarding the timing stuff, TimeQuest timing analyzer is extremely useful part of Altera Quartus and is worth of getting familiar with (but you can definitely do "led-blinkers" without ever caring about it!). One should at least tell the clock frequency to it which the chip operates, so it can give a pretty good judgement if the design works or not. It can automatically derive PLL output clocks from PLL input clocks with "derive_pll_clocks" magic word in the .sdc file.And finally, the SignalTap is extremely useful and versatile, I have even used a simple FPGA board and SignalTap as an substitute for a real logic analyzer, worked just fineRegards,Janne

author: Unixon
author_rank: Frequent Contributor
timestamp: July 21, 2013, 09:15:48 am
content: No doubt, FPGAs are awesome, but one thought always comes up as this is being discussed.A hobbyist to hobbyist question:What would YOU do with an FPGA ?Something that is not there yet or even unseen and unheard of ...

author: kbecker
author_rank: Contributor
timestamp: July 21, 2013, 09:25:48 am
content: For those of you that don't like to learn VHDL or Verilog, I developed a new language that focuses on being more C-like and easier to learn. It is called PSHDL.There is also a Web UI where you can code online and get the generated code. In the near future you will also be able to simulate your code in your browser, but that currently only works in Dartium. But you can also generate C and Java Code out of it for simulation purposes.In PSHDL you still have to learn how to "program" hardware, but at least a few common mistakes that are easy to make with VHDL or Verilog are avoided.Check it out athttp://pshdl.orgor the new and much more advanced editor athttp://beta.pshdl.orgThere is also a blog and twitter to follow the development of it. The ultimate aim is to generate the Arduino for FPGAs!If you have any questions about it feel free to contact me.

author: ChrisW
author_rank: Contributor
timestamp: July 21, 2013, 09:37:38 am
content: Quote from: Unixon on July 21, 2013, 09:15:48 amHardware hacking.Developing custom drivers for things like RGB LEDS. I really want to develop my own screen capable of video playback, something which cant be done with an arduino or other bog standard MCU, they simply are not fast enough.The list goes on.But first, gotta learn to walk before I can run.-Chris

author: WarSim
author_rank: Frequent Contributor
timestamp: July 21, 2013, 10:06:08 am
content: Quote from: Chet T16 on July 21, 2013, 09:00:54 amI have one of those but I bought mine when they cost $99.00

author: MasterOfNone
author_rank: Regular Contributor
timestamp: July 21, 2013, 03:16:05 pm
content: Quote from: kbecker on July 21, 2013, 09:25:48 amI had a look at your website and I remembered doing CPLD designs using ‘Abel’ and having to handwrite state machines to do the main sequential processing.One of the problems with ‘Abel’ was that engineers really needed to know about Digital Design if they wanted to use it for things more complex than the typical Address decoding etc. One of the problems would be knowing about things like Metastability, especially if your design has multiple clocks. Looking at PSHDL (only briefly) is was wondering if it hasn’t reintroduced some of the issues which no longer seem to be a problem with current two main HDL’s.

author: AndyC_772
author_rank: Super Contributor
timestamp: July 21, 2013, 03:44:23 pm
content: Metastability: a pain in the backside if you don't really know what it is and how to work around it, but really not that big a deal once you understand the circumstances under which it can bite.I've lost count of the number of times I've written code like:Code:IF clk'event AND clk = '1' THENinteresting_signal_meta <= interesting_signal;IF interesting_signal_meta = '0' THENdo one thing...;ELSEdo some other thing...;END IF;END IF;

author: John Coloccia
author_rank: Super Contributor
timestamp: July 21, 2013, 04:01:08 pm
content: Just an FYI, clk'event and rising_edge are not equivalent. rising_edge specifically looks for a transition 0 (and other things) to 1, whereas old style just checked that clk was 1. While new designs should probably use rising_edge, if you went back and changed all of your old designs you might well run into different behavior, especially in your simulations.

author: FrankBuss
author_rank: Unknown
timestamp: July 21, 2013, 04:13:58 pm
content: Quote from: AndyC_772 on July 21, 2013, 03:44:23 pmRight, this helps for metastability. But the main problem with asynchronous external signals are setup/hold time violations. For example "interesting_signal" has value 1 and some logic driven by it uses this right after the rising clock edge, but other logic uses it half a clock cycle later and then it might be 0, which leads to interesting problems. Using an input latch as you did, helps for this too.

author: jahonen
author_rank: Super Contributor
timestamp: July 21, 2013, 04:39:35 pm
content: Quote from: AndyC_772 on July 21, 2013, 03:44:23 pmYes, that is a way around it. But standard practice (as mentioned in Howard Johnson's HSDD book) would need something like 2-3 DFF's cascade to get low enough probability for metastable event. But of course that depends on how often the input signal toggles. So in practice I have made a component which I instantiate whenever I need such a thing, and can be easily configured for different chain lengths. That contains all necessary precautions, like adding synthesis attributes for identifying such a synchronizer.Code:signal sreg : std_logic_vector(SYNC_STAGES-1 downto 0);attribute altera_attribute of sreg : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED";Of course Quartus is pretty good at figuring that synchronizer anyway, but it doesn't hurt to tell that explicitly to prevent it from touching it.Regards,Janne

author: AndyC_772
author_rank: Super Contributor
timestamp: July 21, 2013, 04:42:15 pm
content: That's the point I was trying to make... nothing in the FPGA usesinteresting_signaldirectly apart from the input to the latch. Everything else usesinteresting_signal_meta, which (we presume!) has settled to a definite 1 or 0 by the time of the clock pulse immediately after the one on which it latchesinteresting_signal.In some cases - perhaps if the clock speed is high, or the FPGA is particularly susceptible to this effect - it can be a good idea to cascade two or more latches. I know Altera give the option of 1, 2 or more synchronisation stages on their dual-port SRAMs for this reason, though I've never personally needed more than one stage.

author: MasterOfNone
author_rank: Regular Contributor
timestamp: July 21, 2013, 05:08:49 pm
content: Quote from: AndyC_772 on July 21, 2013, 04:42:15 pmI believe that if wrote something similar in PSHDL then the assignment and check condition would always be done in parallel. I think you’ll need to write you own state machines for sequential operations, and if you have multiple state machines on different clocks then things could get interesting. But I didn’t spend that much time looking at PSHDL and it probably has some elegant solutions for these types of problems.

author: PuterGeek
author_rank: Regular Contributor
timestamp: July 21, 2013, 07:38:25 pm
content: Quote from: free_electron on July 20, 2013, 07:47:59 pmROF, LMAO!

author: PuterGeek
author_rank: Regular Contributor
timestamp: July 21, 2013, 08:10:03 pm
content: Quote from: free_electron on July 20, 2013, 07:47:59 pmImpressive equipment and photos as well as a perfect example!

author: jridley
author_rank: Newbie
timestamp: July 21, 2013, 08:42:12 pm
content: coincidentally, SparkFun just released an FPGA dev board for $75 US:https://www.sparkfun.com/products/11953

author: vk6hdx
author_rank: Regular Contributor
timestamp: July 22, 2013, 07:36:47 am
content: Great video Dave, thanks!

author: jahonen
author_rank: Super Contributor
timestamp: July 22, 2013, 08:26:05 am
content: Quote from: John Coloccia on July 21, 2013, 04:01:08 pmWhile it is true that they are not exactly equivalent, but I think that for most purposes, both work just fine. But let's actually take a look what rising/falling_edge() functions contain, as the source is available from IEEE (http://standards.ieee.org/downloads/1076/1076-2008/):Code:--------------------------------------------------------------------- edge detection-------------------------------------------------------------------function rising_edge (signal s : STD_ULOGIC) return BOOLEAN isbeginreturn (s'event and (To_X01(s) = '1') and(To_X01(s'last_value) = '0'));end function rising_edge;function falling_edge (signal s : STD_ULOGIC) return BOOLEAN isbeginreturn (s'event and (To_X01(s) = '0') and(To_X01(s'last_value) = '1'));end function falling_edge;and to_x01() & cvt_to_x01():Code:--------------------------------------------------------------------function To_X01 (s : STD_ULOGIC) return X01 isbeginreturn (cvt_to_x01(s));end function To_X01;constant cvt_to_x01 : logic_x01_table := ('X', -- 'U''X', -- 'X''0', -- '0''1', -- '1''X', -- 'Z''X', -- 'W''0', -- 'L''1', -- 'H''X' -- '-');So in essence, they convert the 9-valued logic state to simpler X01-form and then do principally the same thing. So unless one uses L or H signal levels in the clock signal, both should work just fine. For example, rising_edge(clk)-function detects a transition from L to H state as a rising edge, while clk'event and clk='1' does not.Regards,Janne

author: MacAttak
author_rank: Unknown
timestamp: July 22, 2013, 04:13:04 pm
content: Quote from: jridley on July 21, 2013, 08:42:12 pmIt's a decent starter board. I have one. Slightly less capable than the DE0-Nano, but also slightly less expensive.

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: July 23, 2013, 03:45:01 am
content: Quote from: jridley on July 21, 2013, 08:42:12 pmThese are not "development boards", these are just breakout boards for Spartan or Cyclone, they may have clock source, JTAG connector, perhaps something else, but calling that a complete dev board will be little bit of stretch IMHO.Plenty other breakout boards available on Ebay. This one I think has few bypass caps missing but it is definitely saves you trouble of soldering BGAhttp://www.ebay.com/itm/EP4CE10F17C8N-EP4CE10-FPGA-ALTERA-Cyclone-IV-Evaluation-Development-Core-Board-/251247908829?pt=LH_DefaultDomain_0&hash=item3a7f8ad7ddBreakout board is one that has minimum components, power supply, clock, bypass caps but it is intended to be soldered or plugged into socket on another bigger board designed for specific application. Voltage controlled oscillator, or GSM module are other examples of breakout boards.Dev board is opposite - it meant to be used separately and extensions are added to dev board itself.Speaking of FPGA breakout boards I wish there were more of these available for prototyping especially with latest FPGAs.

author: gregariz
author_rank: Frequent Contributor
timestamp: July 23, 2013, 05:11:54 am
content: Quote from: MasterOfNone on July 21, 2013, 03:16:05 pmLast time I looked Xilinx's ISE integrated ABEL into its design flow, although they no longer actively promote it, its still perfectly usable - particularly for Hardware designers who I suspect are still the main users. Metastability is still an issue out there today with VHDL. IMO ABEL's main problem was that VHDL came along as a standardized open language while most of the HDL's back in the 80's and 90's were somewhat proprietary. By version 5 Abel was doing some pretty good stuff. Today we really only have Xilinx, Lattice and Altera who swallowed most of the smaller players long ago including DataIO. The ones they didnt swallow died.. along with their languages.

author: poorchava
author_rank: Super Contributor
timestamp: July 23, 2013, 05:53:15 am
content: FPGAs have some serious limitations. Consider the following task: there is a 48-bit counter incrementing by one every clock cycle and compared against a set value. Simple, right? Design has to have zero latency, (meaning: pipelining is not allowed.)Code:always@(posedge clk)begincounter<=counter+48'b1;if (counter==set_value) out_compare<=1;else out_compare<=0;NO.for one: most recent stuff (Virtex 7, Spartan 6 etc) have 6 input LUTs which means that comparison of two 48-bit values will be synthesized as 16 LUTs, each performing comparison of 3 bits from one value and 3 from the other, then results of those 16 LUTS are ANDed by another 3 LUTs and then this one is ANDed by another LUT. So you have 3 levels of logic which pretty much limits you to below 150 MHz. Now you add a binary counter. Synthesize that in FPGA fabric and you go like 'w00t, 40MHz'. That's because due to carry logic setup time of all your DFFs (48 of them) adds up. Ok, but there is a DSP48A1 on a Spartan6, why not use that? You can, it needs about 2 clock cycles to reload to certain value, start counting down and spit out first valid result.When you can pipeline stuff at will, you can get your 300Mhz or whatever, but when this is not and option, things start to get hard.

author: iva
author_rank: Contributor
timestamp: July 23, 2013, 05:05:06 pm
content: Quote from: Alexei.Polkhanov on July 23, 2013, 03:45:01 amI respectfully disagree but I think we're getting philosophical here.Can you start and do development using the board linked above?Well, yes you can and you don't really need much more if you don't want to.I consider a breakout board something really bare-bone which, for example, gives you easier access to high density components and doesn't need anything else.Something like this, to be clear (one of the first google image hits):

author: c4757p
author_rank: Super Contributor
timestamp: July 23, 2013, 05:10:21 pm
content: I agree. IMHO, if it has more stuff on it than just decoupling capacitors (and that's only because theymustbe in a certain location), it's not a breakout board. That looks very much like a development board to me. It even has a programmer built in. I've got a little eBay FPGA board that has just a Cyclone IV, regulators, an oscillator, and an EEPROM, and I'd even call that a dev board. Hell, Istillthink it's one even after I've disabled the crappy oscillator and unhappy, hot regulators, because it has an EEPROM and JTAG header.

author: JoeyP
author_rank: Frequent Contributor
timestamp: July 23, 2013, 06:00:51 pm
content: Quote from: marshallh on July 20, 2013, 07:55:29 pmNot sure which brand of FPGAs you refer to, but this sounds like very dated info. For years I've been doing 200-250MHz synchronous designs in Altera Cyclone and Lattice ECP family FPGAs in the sub $30 range. The silicon in these parts typically has per/element Fmax specs in the 300-400MHz+ range. Hand placement is not necessary to get desired Fmax, but I'll occasionally use it to assure off-chip timing.Regarding the difference between FPGAs and CPLDs, it's becoming a moot point. Modern "CPLDs" (e.g. Altera Max parts) are essentially tiny FPGAs with on-board configuration memory. It took a while for Altera to admit this, but even their sales reps now freely concede this point.

author: Rasz
author_rank: Super Contributor
timestamp: July 23, 2013, 06:21:04 pm
content: Quote from: JoeyP on July 23, 2013, 06:00:51 pmAre you sure about that? If they were same die FPGAs with on board flash it would be logical to give them option of loading config with jtag without flashing, afaik this is not possible (and resulted in many cplds dying while being used to learn VHDL)

author: AndyC_772
author_rank: Super Contributor
timestamp: July 23, 2013, 07:04:32 pm
content: How did you manage that? I don't think I've ever managed to damage a CPLD during debugging.

author: JoeyP
author_rank: Frequent Contributor
timestamp: July 23, 2013, 07:16:12 pm
content: Quote from: Rasz on July 23, 2013, 06:21:04 pmYes. The sales reps will even tell you so if you challenge them on it. In the old days, CPLDs had slightly different architectures from FPGAs, so there were applications where one might make sense over the other (from a pure logic point of view - excluding volatility considerations). These days, if you look at say Altera MaxV, the logic cells are virtually identical to a same-generation FPGA. They're even starting to include the other features previously limited to FPGAs such as PLLs etc. The main benefit to a CPLD these days is the non-volatility. For some applications the faster internal configuration time for these types of CPLDs vs an FPGA with external configuration (which tend to be serial, and much slower) may also be a benefit. Yes, they could certainly have chosen to include external (volatile) reconfiguration for CPLDs, but that would have blurred the line between CPLD/FPGA still further, and for the moment they seem to want to keep it distinct (probably for marketing purposes).

author: MasterOfNone
author_rank: Regular Contributor
timestamp: July 23, 2013, 07:54:45 pm
content: Quote from: gregariz on July 23, 2013, 05:11:54 amI should have said PSHDL reminded me of early versions of ABEL, since I didn’t really follow it after the Nineties. I'm not saying that early versions of ABEL were crap, it’s just that it took a lot of effort to develop designs that used multiple state machines that operated on different clocks. Using it for address decoding and generating chip selects was fine. So after briefly looking at PSHDL I was just enquiring how they have solved those problems, since it reminded me of early versions of ABEL where everything operated in parallel and you had to use state machines for sequential processing.In Verilog or VHDL you can usually do timing simulations to help identify potential problems, these tools took a lot of time and effort to develop and are tied to the FPGA device being used. I’m not sure how they were going to do this with PSHDL.Also I don’t think ABEL is still supported by Xilinx (it isn’t in 13.2) and when it was supported (v10 or v11), I’m not sure if it could be use it for anything apart from CPLD’s, but I might be wrong.Anyway I’m not claiming to be some HDL expert in any language, I was just wandering how engineers are going to develop large complex FPGA designs with PSHDL.

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: July 23, 2013, 09:25:19 pm
content: Quote from: iva on July 23, 2013, 05:05:06 pmI think that is simply called an SMT adapter. Problem with adapters is that they violate certain design rules such as proximity of decoupling capacitors to respecting pins. At least first set of caps should be close, larger caps that added to compensate for self-resonance can be moved further but it is very beneficial if you can add bypass caps on opposite side of board as close as possible to via that goes straight from the power pin. Other signal integrity issues can be introduced by SMT adapters as well. I tried to use through hole caps with one pin almost completely cut off and soldered right to the pin on opposite side of prototyping board. I had moderate success with that. I have few good photos - will post later when I will get home.

author: marshallh
author_rank: Unknown
timestamp: July 23, 2013, 09:31:23 pm
content: He's right, MAX II and MAX V cplds are sram based, config data is loaded from an EEPROM on powerup.They are only rated for about 100 program cycles.

author: c4757p
author_rank: Super Contributor
timestamp: July 23, 2013, 09:32:34 pm
content: Quote from: marshallh on July 23, 2013, 09:31:23 pmI've noticed this. Is that just a really, really conservative rating, or do they actually tend to fail after that many?

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: July 23, 2013, 09:33:20 pm
content: Quote from: Rasz on July 23, 2013, 06:21:04 pmAltera MAX V CPLD datasheet states that you can reprogram it only 100 times.

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: July 23, 2013, 09:37:17 pm
content: Quote from: c4757p on July 23, 2013, 09:32:34 pmQuartus say prgramming is successful, but nothing works - that was my personal experience

author: Rasz
author_rank: Super Contributor
timestamp: July 23, 2013, 10:42:38 pm
content: cplds also tend to be cheaper, maybe its a market segmentation and there is a programming counter like in inkjet printers

author: JoeyP
author_rank: Frequent Contributor
timestamp: July 24, 2013, 12:06:13 am
content: Quote from: Rasz on July 23, 2013, 10:42:38 pmI think it is definitely market segmentation. I believe that's why they continue to push the CPLD terminology, instead of calling them what they are - FPGAs with onboard configuration memory.I don't think they simply pop in one of their FPGA dice though, because to keep cost down they probably need to use much smaller silicon real-estate. The largest "CPLDs" are still quite a bit smaller than the smallest FPGAs (at least from Altera).As far as a programming counter, it's not consistent. Doesn't die at exactly 100 cycles, or at same count for every part. My bet is that they use a process for the EEPROM that is compatible with the logic die, so that it can all be done on a single piece of silicon - but just guessing there. It was not unusual for EEPROMs to have such limits to programming cycles in the old days, so maybe just using old (but coincidentally compatible) technology.I did some tests a while back on some modern EEPROMs rated at 1M cycles. Found they would begin to fail at anywhere from 2M to 10M cycles, and found it to be very vendor-dependent. Faster programming parts predictably fail with fewer cycles because they use higher programming voltages internally.

author: romovs
author_rank: Contributor
timestamp: July 24, 2013, 01:46:08 am
content: Quote from: Alexei.Polkhanov on July 23, 2013, 09:25:19 pmWhere did you get those tiny sticky labels?

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: July 24, 2013, 02:21:29 am
content: Quote from: romovs on July 24, 2013, 01:46:08 amI printed them on printer on self adhesive paper.

author: bitwelder
author_rank: Super Contributor
timestamp: July 24, 2013, 05:48:55 am
content: Quote from: MasterOfNone on July 23, 2013, 07:54:45 pmAbout PSHDL, just yesterday on YouTube CCCen channel they published the lecture on "Programming FPGAs with PSHDL" from SIGINT13 conference:I haven't had time to watch it yet, but usually CCC does good stuff.

author: MasterOfNone
author_rank: Regular Contributor
timestamp: July 24, 2013, 09:03:57 pm
content: Quote from: bitwelder on July 24, 2013, 05:48:55 amJust watched it and all my questions have been answered. Basically PSHDL isn’t aimed at asynchronous designs with multiple clocks, it's aimed at synchronous designs with a single clock.PSHDL is aimed at the educational/hobbyist market and it isn’t trying to replace VHDL or Verilog, its aim is to become the Arduino for FPGA’s.

author: Unknown
author_rank: Unknown
timestamp: July 25, 2013, 07:07:25 am
content: Hi everyone:)In the last FF video i criticized Dave for the boring FPGA tutorial (And yes, i still think it was boring). He answered "why don't you make own tutorial video, and show how it is done"Well, the challenge was indeed accepted. Here is the result:I am not claiming to do any competition with Dave, but is think if the video will get some positive feedback, i will do more tutorials.I am not professional and on the learning curve by myself, but is think i can teach peple a lot of basics, since i have good experience with being a tutor in real life.

author: EEgalitarian512
author_rank: Contributor
timestamp: July 25, 2013, 09:19:37 am
content: Hi Dave. Thank you so much for this video on FPGAs. If it feels right, I would heartily encourage more videos on this topic - especially from a logic design viewpoint. I am more interested in the 'schematic capture' aspect - and not so much from the programming / VHDL / Verilog side of things. I am equally interested in CPLDs - again from the schematic side.

author: Rasz
author_rank: Super Contributor
timestamp: July 25, 2013, 02:06:34 pm
content: Quote from: Citizen on July 25, 2013, 07:07:25 amThere was a problem when rendering that video, you put elevator music instead of voice track = definition of boring.

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: July 25, 2013, 05:41:20 pm
content: Quote from: Rasz on July 25, 2013, 02:06:34 pmTotally agree with that!!!

author: Unknown
author_rank: Unknown
timestamp: July 25, 2013, 06:19:43 pm
content: QuoteYour definition of boring is pretty local;)For me smooth/electro jazz (you call it elevator music) is just a not annoying background music, which keeps your brain active while not dragging any attention to itself (like in case with classical music).In my opinion, the subtitle like explanation has many advantags , especially while explaining a programming language.1. The viewer can pouse video at any time, read what i "said" and compare it with code..2. You can put additional annotations in it,text highlighting, syntax or small code examples.3. If the viewers native language is not English(which happens pretty often on youtube), it is much easier to understand such tutorials.

author: MacAttak
author_rank: Unknown
timestamp: July 26, 2013, 12:28:06 am
content: Quote from: Citizen on July 25, 2013, 07:07:25 amI started to watch it, but it was REALLY hard to follow. Reading the captions at the bottom of the video makes it impossible to see what you are actually doing in the UI above. In order to grasp it, I need to watch and read the text, then rewind and watch the same clip again while paying attention to the video itself.This really needs voiceover.BTW, one of our core services is online training videos. Not a single one uses text captioning in lieu of voiceover. There is a reason for that - when someone is watching you do something with a code editor they can't also be reading text at the same time.

author: westfw
author_rank: Super Contributor
timestamp: July 26, 2013, 05:11:44 am
content: QuoteDo you (all) think that learning about smaller PLD and FPGA-like devices is useful toward learning how to use FPGA-class chips? (I'm talking about PLD, CPLD, Silego GreenPak, or the Configurable logic that Microchip (CLC) and Atmel (XCL) have started to put on their chips.)On the one hand, it seems like these are pretty close to being single-CLB on a chip, so understanding them would be essential to understanding FPGAs. On the other hand, one doesn't design FPGAs at the CLB level, and I for one find that the massive parallelism a major chokepoint in my understanding (almost as if, having learned something about PLDs, I am hamstrung because I keep trying to think of the FPGA in those terms.)=====I have a suggested FPGA project: a multi-channel PWM controller, manipulated by SPI or some other serial interface (or, any of multiple serial interfaces - that's the sort of thing that should be relatively easy in an FPGA, right?) So, some input logic, a clock source, some 8-bit counter, 32 or so 8bit "compare registers", and some outputs. Does that seem reasonable? PLDs and most CPLDs I've looked at don't seem to be able to do it, because those compare registers end up being "buried state", rather than associated with IO pins (where most PLDs put all their flipflops.)(Of course, the other thing I run into is "Oh wait; I don't need to sort of speed provided by an FPGA; I can just do all that in software on a moderately current microcontroller. Sigh.)

author: Unknown
author_rank: Unknown
timestamp: July 26, 2013, 07:19:09 am
content: QuoteI really tried to separate caption and programming.But yes, they overlay a bit.In the next video i will separate them better:like captions first, then they disappear and programming starts.

author: ve7xen
author_rank: Super Contributor
timestamp: July 26, 2013, 07:32:03 am
content: If videos don't have a voice over, I just don't watch them. I'm not engaged and disinterested in reading unemotional, boring text.

author: AndyC_772
author_rank: Super Contributor
timestamp: July 26, 2013, 07:42:37 am
content: Quote from: westfw on July 26, 2013, 05:11:44 amI can't think of any reason why not; in principle it's trivial. I can see small CPLDs running out of registers, that's all. The logic requirement will scale linearly with the number of channels you want and the width of each counter.The hardest part - if you're worried about doing it properly - is synchronising register writes from the SPI interface to the PWM clock domain. If you're not careful about timing and metastability, you run the risk of output glitches when the host CPU writes values into your control registers. Getting it rightand avoiding this problem is a 10 minute job for an experienced designer.

author: AndyC_772
author_rank: Super Contributor
timestamp: July 26, 2013, 07:49:49 am
content: Quote from: westfw on July 26, 2013, 05:11:44 amYes, of course. I started learning Altera MAX CPLDs, using Quartus and VHDL, and now I'm filling up Cyclone IV FPGAs using the exact same language and tool chain.I tend to use FPGAs more than CPLDs these days, simply because you get so much more logic for the money. CPLDs are expensive, stupidly so given how small they are in terms of logic density, and what you can do in (say) an ARM microcontroller for less. Where I do use them, it tends to be for glue logic functions - things like dividing clocks, multiplexing TDM highways together, and address decoding... hard real-time functions for which a software approach doesn't really make sense.

author: westfw
author_rank: Super Contributor
timestamp: July 27, 2013, 05:44:34 am
content: QuoteWell, the 32*8bit PWM means at least 256bits of storage (flipflops.) If I look at something like the Xilinx Coolrunner-2 series of CPLDs, I only see one flipflop per "macrocell", and a 384-macrocell CPLD is relatively "big" (next to largest for that series, and packages in 144pin packages.) (and using the whole macrocell just for the flipflop seems very wasteful.)Am I missing something? Am I hopelessly software-minded to expect "memory" to be relatively cheap? Are there CPLDs with hardwired memory blocks?(I supposed you could theoretically do this by reprogramming the CPLD each time you change a PWM endpoint, so you'd be comparing the hypothetical counter against a "hardwired" constant implemented in the logic parts of the macrocells. But that doesn't seem right either.)

author: EEVblog
author_rank: Unknown
timestamp: July 27, 2013, 07:48:37 am
content: Quote from: ve7xen on July 26, 2013, 07:32:03 amI agree. I started watching the video, but immediately switched off once I realised there was no voiceover.

author: FrankBuss
author_rank: Unknown
timestamp: July 27, 2013, 08:45:37 am
content: Quote from: westfw on July 27, 2013, 05:44:34 amThere are some nice Lattice parts with integrated memory, like the LCMXO2-640HC, with 18 kbits block RAM, for EUR 5 at Digikey. They used to categorize it as CPLD in their webpage, but looks like now they call it FPGA. But it has some attributes of CPLDs, e.g. integrated flash memory for instant-on without the need for an external configuration device and single 3.3V operating voltage (but there are other versions with 1.2V core voltage, too). I'm using one of their MachXO2 devices for my Crazy Cartridge:http://www.crazycartridge.org

author: Majorstrain
author_rank: Contributor
timestamp: July 27, 2013, 12:23:49 pm
content: Quote from: EEVblog on July 27, 2013, 07:48:37 amYep, must admit I only made it about 30 seconds in before quitting

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 27, 2013, 01:35:42 pm
content: Quote from: FrankBuss on July 27, 2013, 08:45:37 amXO2 is a bit of an oddball ( in a nice way) in that the range spans a wide range from low-end CPLD equivalent to mid-range FPGA. Pity the range of packages has such big hole from 32 to 100 pins.

author: EEVblog
author_rank: Unknown
timestamp: July 27, 2013, 01:35:59 pm
content: Quote from: Majorstrain on July 27, 2013, 12:23:49 pmThen again, thousands of people say that about my voice!

author: ElectroIrradiator
author_rank: Frequent Contributor
timestamp: July 27, 2013, 01:39:33 pm
content: Quote from: EEVblog on July 27, 2013, 01:35:59 pmTake hearth, Dave. You are an acquired taste.At least you are a native English speaker, unlike some of the rest of us...

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 27, 2013, 01:45:16 pm
content: Quote from: westfw on July 26, 2013, 05:11:44 amI'd say probably not, or at least minimal benefit. If you start with simple designs on a medium sized device, it will compile quickly as the place/route doesn't have to work hard, and you won't be anywhere near running out of resources. All the fancy stuff on bigger devices can just be ignored until you want to use it.If you start with a CPLD, you may hit resource limits quite quickly, and struggle to make a design fit (although you may learn something from the process of changing a design to make better use of resources).Starting with CPLD may be worthwhile for very simple stuff, and cpld compile times are a lot shorter then even a very simple device in an FPGA (e.g. from experience with Lattice, 10 secs vs. 20-30 secs for a trivial FPGA design). However download times for a FPGA into internal RAM may be a little quicker than CPLD flash programming time.CPLD might also have the minor benefit that you stand more chance of understanding what the compiler is actually doing as the device is simple enough that the logic equations etc. it generates are reasonably understandable.

author: Unknown
author_rank: Unknown
timestamp: July 27, 2013, 02:59:54 pm
content: QuoteThat is right. Moreover English is not my native language, so i would better leave my videos without my voiceover, since shitty pronunciation can ruin a tutorial ( especially if it is a programming tutorial).I have seen such tutorials many times from big companies like Altera, Xilinx, Cypress etc. where a competent but foreign guy/girl from India/china/korea tries to explain things, but i just cant understand what he/she is saying. (normally i understand about 95-99% of spoken english: about 98% what Dave is saying, but i must admit only 65% of Mikes (mikeselecticsstuff), that is why i am not watching his videos)I also understand that most fanboys here expect Daves-like presentation. I will produce more FPGA tutorial in my style, better separating captions and programming.

author: MacAttak
author_rank: Unknown
timestamp: July 27, 2013, 05:12:36 pm
content: You could always try one using voiceover. Most people tend to believe their own voice and speech are considerably worse than they actually are. Even with a strong accent, you might still be just fine. You'll never know for sure until you do it.

author: Rasz
author_rank: Super Contributor
timestamp: July 28, 2013, 02:42:10 pm
content: Quote from: Citizen on July 27, 2013, 02:59:54 pmdefinition if ironybtw why is that? too much cockney?Quote from: MacAttak on July 27, 2013, 05:12:36 pmThis is very true. We are used to hear our own voice with a distortion filter of jaw bones and all the 'meat' in our head (shortest path is through the squishy stuff) - this is how we think we sound. Hearing same voice from a recording freaks us out.

author: mickpah
author_rank: Regular Contributor
timestamp: July 29, 2013, 11:26:48 am
content: HiI have been pulling a Rigol DP832 power supply apart slowly over the last week and got to the keypad. I was going to leave it thinking what could be interesting here?But lo and behold they are using a microsemi ProASIC3 FGPA as the keyboard controller. Couldn't believe it.You really need to do a teardown on these power supplies Dave, chock full of goodies. Insane amount of computing power in a linear power supply that costs just over $400 USD.microsemi also do what they call nano fgpahttp://www.microsemi.com/products/fpga-soc/fpga/igloo-overview,niche but interesting. If ever there was something called a hobbyist FPGA this might go close. well VQ128 in not BGA anyway

author: EEVblog
author_rank: Unknown
timestamp: July 29, 2013, 01:36:15 pm
content: Quote from: mickpah on July 29, 2013, 11:26:48 amYes, I need to ditch my Atten piece of rubbish.Hmm, only AU$420 + GST:http://www.eyou.com.au/product/rigol-dp832-programmable-triple-output-195-watt-power-supply-/Didn't know they were that cheap...

author: WarSim
author_rank: Frequent Contributor
timestamp: July 29, 2013, 01:42:05 pm
content: Good grief, you find these the day after I order a Spartan3E dev board and programer!

author: mickpah
author_rank: Regular Contributor
timestamp: July 29, 2013, 09:50:06 pm
content: Quote from: EEVblog on July 29, 2013, 01:36:15 pmyep where I got mine, sadly gst and shipping take it closer to $500AUD - this is one heavy beast. It has quirks and is much deeper than most units but nothing I can't live with it at that price.

author: alter Ratz
author_rank: Contributor
timestamp: October 08, 2013, 07:51:05 pm
content: Quote from: synapsis on July 19, 2013, 11:34:00 pmI also liked the FPGA blog. I was working in ASIC design (we developed the first FlexRay controller) using FPGA prototyping (ALTERA) a few years ago, which I found not to be too different from software design (which I do now). However it is quite difficult to switch ones mindset from procedural to unlimited paralellism. But when you manage to do it, it is impressive what you can do.I hope very much that Dave shoots a few followups to this blog entry.Best regards,Bernhard

author: idiotsecant
author_rank: Newbie
timestamp: October 09, 2013, 12:07:43 am
content: Dave, I swear if i'm not careful I might learn something in spite of my university.Thanks for the video.

author: kcozens
author_rank: Contributor
timestamp: October 18, 2013, 08:17:17 pm
content: Ignore those naysayers, Dave. This was a nice introduction to a very complex topic. I stayed away from FPGA's for a long time. After seeing a video by Jeri Elsworth about some inexpensive FPGA development boards I picked up a couple of Spartan 3 based boards. One was the Papilio One board that was mentioned in Jeri's video. I went with simple development boards which are little more than the FPGA as I already have a lot of parts around to connect up to a board. I didn't want a board where a lot of I/O pins are tied to onboard devices I may not need or want to use.

author: Macbeth
author_rank: Super Contributor
timestamp: November 27, 2013, 11:41:11 pm
content: Great stuff on the FPGA. I just checked out Farnell and there are very reasonably priced Lattice Kitshttp://uk.farnell.com/lattice-semiconductor/ice40lp1k-blink-evn/kit-eval-iceblink40-lp1k/dp/2253072. Cheaper than a Raspberry Pi at only £26.19+VAT each!The BGA chips alone are only £2.75 for 36 pin and £3.71 for 121 pin. Ok they will be a bugger to solder if you don't have a rework station and I guess a proper PCB and solder paste mask is essential. All that is needed is a breakout board and I guess the kit might be good enough for that at least in prototype projects.

author: Winston
author_rank: Regular Contributor
timestamp: January 03, 2014, 03:43:06 pm
content: FPGA 101 - Making awesome stuff with FPGAs

author: JoeN
author_rank: Frequent Contributor
timestamp: January 05, 2014, 09:07:46 pm
content: Quote from: Winston on January 03, 2014, 03:43:06 pmListened up to the point where the presenter admitted he didn't know why FPGA vendors choose 18 bit widths for embedded multipliers and then had to do a facepalm and turn it off.

author: kbecker
author_rank: Contributor
timestamp: January 05, 2014, 10:38:19 pm
content: Quote from: JoeN on January 05, 2014, 09:07:46 pmWell, regarding the bit width, I would be thrilled to hear your answer about it. Using 18 bit because the memory width is a multiple of 9 bit is the best answer I found so far, but still, it is rather arbitrary as you hardly want to multiply the parity bit. 16 bit would require less resources and run at a higher frequency, which may, or may not improve overall performance.

author: kbecker
author_rank: Contributor
timestamp: January 05, 2014, 10:44:18 pm
content: Quote from: MasterOfNone on July 24, 2013, 09:03:57 pmSorry for digging up things this old, but this is not correct. PSHDL does not have any limitations regarding the number of clock domains. The only limitation that is imposed artificially is that you can not simulate combinatorial loops in PSHDL. And this limitation is only there because I think most people are creating those by mistake, rather than choice. It would be possible to support it rather easily.However the common case of just having a single clock synchronous design is the case PSHDL is optimized for.There is also an updated 30C3 version of the talk:

author: JoeN
author_rank: Frequent Contributor
timestamp: January 06, 2014, 01:52:04 am
content: Quote from: kbecker on January 05, 2014, 10:38:19 pmhttp://www.altera.com/literature/hb/cyc3/cyc3_ciii51003.pdfQuote from: AlteraI will just leave it up to the reader to infer the meaning of this passage.

author: Winston
author_rank: Regular Contributor
timestamp: January 20, 2014, 01:20:44 am
content: This EEVblog video inspired me to produce this T-shirt artwork from an edited (numbers removed and flipped horizontally)public domainhuman brain drawing and afreewarefont (Digitrix) whichallows commercial use. Anyone can grab this and make T-shirts from it for sale.All I ask is that I get a free one if you do. The file will be downloaded as a PNG which has a much larger file size while loosing some fine resolution over the original BMP. If you want the original BMP, let me know and I'll email it to you:Human Brain - Field Programmable Gate Arrayhttp://i142.photobucket.com/albums/r100/EGoldstein1984/BrainFPGA_zpsb5c49699.png