SAM-D21 DMA - Page 1
Forum section: electronics / general

author: wek
author_rank: Frequent Contributor
timestamp: September 06, 2022, 09:06:35 pm
content: While discussing STM32 clones, I rudely hijacked that thread to discuss methods and merits of connecting DMA controller registers in the 32-bitters through AHB vs. APB bus.As an example of mcu with DMA registers connected through APB, Alex suggested to have a look at SAM-D21. It's a relatively low-ish-end Cortex-M0+-based mcu.And its DMA controller is an absolute BEAST!Umpteen channels, fetures galore, including CRC-on-the-fly. And, perhaps most importantnly, it is scatter-gather, with "unlimited" descriptors in the general-purpose SRAM.And that rises the obvious question (see attachment - sorry I don't know how to inline the picture to text):how does the descriptors read/write interact with other reads/writes to SRAM?Those descriptors are not tiny - they are 64 bytes i.e. 16 words, that's not entirely negligible traffic.Is there any more detailed description of this anywhere?Thanks,JW

author: ataradov
author_rank: Super Contributor
timestamp: September 06, 2022, 09:52:55 pm
content: Quote from: wek on September 06, 2022, 09:06:35 pmIt really is not. Even if you discount really bad errata, the design itself is actually bad. And it relates to the ports you point out.The DMA controller here is actually single channel by its nature. The channel switch happens by saving the current state in the write-back memory (located in the main SRAM) and loading the previously saved state.This saves silicon resources (and everything in D21 is designed for that), but results in a really bad performance in some cases.For example, if you have SPI RX and TX at the same time (as you often do), you will constantly have to switch channels back and forth resulting in a ton of SRAM access cycles and low overall performance. The maximum SPI clock this scheme can handle is 6 MHz with the system running at 48 MHz.SRAM has separate ports for different masters, but it would still affect performance in some cases.Realistically, I'd rather have 4 channels of a real DMA over this one with 12 fake channels. I don't mind descriptors in SRAM for SG operation, since you can't really avoid it.And while having real SG is good, in practice simple linked descriptors would be sufficient for most tasks, and this can be done by simple linking the channels and not using SRAM at all.

author: wek
author_rank: Frequent Contributor
timestamp: September 06, 2022, 09:59:05 pm
content: But thanks for the explanation.Jan

author: wek
author_rank: Frequent Contributor
timestamp: September 06, 2022, 10:11:59 pm
content: QuoteLike DMA in PIC32MX? (That's the only one I know which does this).Yes that sounds to be simple yet powerful enough, but the STM32 DMA does not offer even that... (maybe the new DMA in 'U5, I did not have time to check and those chips can't be bought now anyway).JW

author: ataradov
author_rank: Super Contributor
timestamp: September 06, 2022, 10:28:59 pm
content: Quote from: wek on September 06, 2022, 10:11:59 pmI'm not familiar with PIC32M devices at all. I don't like MIPS, so I never considered them for anything.Quote from: wek on September 06, 2022, 10:11:59 pmYes, traditional STM32 DMA controller is pretty weak compared to the rest of the device. You can often make use of a circular mode to solve some of the problems, but it is annoying.