Program retention in Xilinx Coolrunner II CPLDs - Page 1
Forum section: electronics / general

author: garvind25
author_rank: Regular Contributor
timestamp: September 11, 2017, 11:05:53 am
content: Hi,This is the first time I will be sing a Xilinx Coolrunner II CPLD. Hence I am confirming the following fact. Is it true that if I program a CRII CPLD, use it and then switch it off, when I switch it on after some time, does the CPLD still stay programmed ie. are CRII CPLDs non volatile as compared to SRAM based FPGAs. I am confirming this because otherwise I will most probably need to interface a EEPROM with the device while making the PCB.Thanks,Arviind Gupta

author: rstofer
author_rank: Super Contributor
timestamp: September 11, 2017, 11:36:46 am
content: Short answer: Yes, the configuration is non-volatile.Long answer: See page 12 "Power-Up Characteristics" (2) here:https://www.xilinx.com/support/documentation/data_sheets/ds090.pdfThe configuration is stored in non-volatile ram and transferred to the SRAM cells at start-up.

author: garvind25
author_rank: Regular Contributor
timestamp: September 12, 2017, 02:06:42 pm
content: Thanks for digging that out for me. Just three more things:** What is the size of the non volatile ram of the chip say for XC2C128/ XC2C256.** How do I interface a 2 pin crystal oscillator with the CPLD ICs** If I operate the VCCIO at 3.3v and want to force an I/O pin to logic '1', can I directly connect it to 3.3v or the gnd for logic '0' (say using a 3 pin SPDT switch). Or do I need to put some resistance inbetween.Thanks again,Arvind Gupta

author: rstofer
author_rank: Super Contributor
timestamp: September 12, 2017, 03:01:39 pm
content: Quote from: garvind25 on September 12, 2017, 02:06:42 pmI couldn't find anything on this. I would assume the NVRAM is big enough to hold any conceivable program and no larger. I don't imagine the NVRAM is intended for storing user programs originally written in C as we do with FPGAs.QuoteDigilent does it by using a voltage appropriate (3.3V) crystal oscillator. See page 3 (lower left corner) here:https://reference.digilentinc.com/_media/coolrunner-ii:coolrunner-ii_sch.pdfSG8002DC is a crystal oscillator.QuoteOne way is to use a pull-up resistor (10k or less) between Vcc and the pin and pull it to ground with a switch. The resistance has to be low enough to allow sufficient current to flow to keep the switch contacts clean. 1 Mohm is probably not a good idea.I don't like that approach. I am of the opinion that no solid connection, to ground or VCC, should be applied to a pin since a mistake in programming can result in a conflict (the input pin is described as output) and smoke the device. For a 3.3V system, I would put 200 Ohm resistors in series with the pin and then use the 1k pull-up arrangement with a switch to ground. All IO pins get resistors. They won't affect the operation and they help eliminate reflections caused by fast rising signals. A win-win...Digilent doesn't do that on the referenced CPLD board but they often do it on the more expensive FPGA boards. See here for a typical FPGA board:https://reference.digilentinc.com/_media/nexys4-ddr:nexys_4_ddr_sch.pdf

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: September 12, 2017, 06:39:46 pm
content: Quote from: garvind25 on September 12, 2017, 02:06:42 pmEach bit in the SRAM directly controls one of the configuration switches in the logic blocks. It is equivalent to the fuses in older PLDs or the interconnect layer in a mask-programmed chip. It's not like normal SRAM which is addressed one location at a time and puts data out on a bus.So the answer has to be - just enough bits to do every configuration switch in the chip.

author: agehall
author_rank: Frequent Contributor
timestamp: September 13, 2017, 05:14:08 am
content: SRAM? I thought it was some sort of flash that kept the config state in CPLDs.Anyhow, it's not to be thought of as ordinary memory. The size of a CPLD (and FPGAs) is measured in how much logic they can contain. The CPLD are capable of storing configuration for all the logic in the chip that can be programmed.

author: rstofer
author_rank: Super Contributor
timestamp: September 13, 2017, 06:55:32 pm
content: Quote from: agehall on September 13, 2017, 05:14:08 amSee reply #1. The configuration isstoredin non-volatile RAM (flash) but the bits are transferred to the SRAM gates at startup. So sayeth Xilinx for their CoolRunner product.

author: garvind25
author_rank: Regular Contributor
timestamp: September 21, 2017, 07:07:33 am
content: Thanks for your replies. As per the advice of rstofer on 13/9, pls. note the following:1. You have mentioned the usage of 4 pin oscillators (BTW which class of oscillators are these. I suppose crystal oscillators have 2 pins). Can I not use 2 pin oscillators for CPLDs. Have you come across any xilinx schematics for the same. I have never used these 4 pin devices hence will like to stick to the crystal oscillators.2. Regarding the use of resistors for connecting 3 pin SPDT switches, the nexys 4 schematic shows the usage of a simple 10K resistor with the IC pins. You suggested a 200 ohm resistor with the IC pin and a 1 k pull up resistor between the switch and 3v3 supply and direct connection of the other terminal of the switch with gnd. First of all, I hope my understanding is OK (if not do correct me pls.). But how will this arrangement save the IC from burning out in an event of the pin getting mis-programmed ie. getting programmed as an output pin rather than being used as an input pin? I was not able to understand the point, hence asking.Thanks and Regards,Arvind Gupta

author: FrankBuss
author_rank: Unknown
timestamp: September 21, 2017, 10:35:06 am
content: Quote from: garvind25 on September 21, 2017, 07:07:33 amUsually CPLDs don't have analog inputs or analog amplifiers. A two pin crystal needs such a device, usually microcontrollers have it integrated, like a pierce oscillator, seehttps://en.wikipedia.org/wiki/Pierce_oscillator. A "crystal oscillator" (note the difference between "crystal oscillator" and "crystal") has this all integrated: a silicium crystal and the amplifier circuit. The output is a standard digital square wave signal, which can be used for the CPLD. Make sure to connect it to some global clock input of the CPLD, as specified in the datasheet, for non-gated routing.Quote from: garvind25 on September 21, 2017, 07:07:33 amImagine you programmed your supposed input pin of the CPLD as an output. And then you switch it to GND. Then a 200 ohm series resistor would limit the current to max 3.3V/200=16mA. Still a lot, usually you don't want more than a few milliamps. You could probably use just two 4.7k resistors:If you are sure that you program any supposed input pin always right, then you can connect it without a resistor to VDDIO or GND, because at reset all pins are input as well before your configuration is loaded from flash to SRAM. But a series resistor of 10k or 4k or whatever costs 2 cents and you will really like it, if you want to debug something or have a wrong connection, and then you don't have to scratch traces on the board

author: garvind25
author_rank: Regular Contributor
timestamp: September 22, 2017, 10:59:35 am
content: Thanks for the reply Frankbuss. But I can see one small flaw in the schematic. When the switch is on, it connects the supply to gnd through a 4k7 resistor. So 0.7 mA current will be wasted through this configuration (per switch used). So do you not suppose that the following configuration will be useful (as per attached file: I dont know how to insert an image in the post ). This way VCCIO will never be connected to gnd!Thanks and Regards,Arvind Gupta

author: FrankBuss
author_rank: Unknown
timestamp: September 22, 2017, 11:18:26 am
content: Yes, this is better, if you have such a switch (they might be more expensive, or a fancy looking push-button you want to use might be just a SPST type). If it never connects VCCIO and GND when switching (break-before-make, most switches should behave like this), you can even remove R1.

author: rstofer
author_rank: Super Contributor
timestamp: September 22, 2017, 01:04:07 pm
content: Quote from: garvind25 on September 21, 2017, 07:07:33 amA 2 wire crystal is just a crystal - it doesn't oscillate by itself. Some devices, like uCs have the oscillator component built in so all you do is hang a crystal and a couple of capacitors and everything works fine. It takes 2 pins on the uC. Other devices may want an external oscillator (the 4 wire device) because they don't provide the circuitry to drive a crystal. I suspect you might want to read the datasheet for the device. The third approach is to hang a couple of inverters around the crystal and try to get a square wave that way.Just because Digilent used a crystal oscillator, which costs more than a crystal and drives up the cost, is no reason you have to do it. But it's a pretty good bet you will.QuoteWith the 200 Ohm resistor in series with the pin, there won't be enough current flow to damage the device regardless of the state of the internal logic and the external circuitry (assuming only 3.3V). On development boards, this is a huge advantage because, well, mistakes happen. Especially around here!CMOS takes so little gate current that the 200 Ohm resistor doesn't cause any appreciable voltage drop. It also helps tame reflections. I ran into a serious problem trying to hang a Compact Flash on a Spartan 3 Starter Board (that didn't include the resistors) and the only way to get the setup to work was to insert 330 Ohm resistors on every signal lead. I suppose there was another way to do this but my way worked.

author: garvind25
author_rank: Regular Contributor
timestamp: September 24, 2017, 07:50:07 am
content: OK. Just one more thing here. What is meant by reflections pls.? And does one require a 200 ohm resistor only to remove them or can any other value be used also. I was planning to simply use a 10 k resistor in series with the CPLD pins before connecting it to the pole of SPDT switches.Also I went through the datasheet of XC2C128. It mentions that there are 3 GCLK pins. I suppose I have to connect all three pins to the crystal oscillator if I want to use the entire IC resources? Do I put decaps before near every GCLK pin? Also, there is a global rst pin. Can it be left floating or should I use push button switch to connect it to 3.3 V supply for reseting the IC when required?Thanks again,Arvind Gupta

author: FrankBuss
author_rank: Unknown
timestamp: September 24, 2017, 11:04:29 am
content: Reflection happens with high frequency signals and the high frequency components when switching from low to high and high to low. For example see this document:https://www.altera.com/en_US/pdfs/literature/an/an447.pdfIt shows what happens, if you don't use a series resistor: large overshoot and undershoot voltages can happen. They recommend 33 ohm, but the higher the better. 200 ohm should no problem, if you don't need hundreds of MHz. But if your clock and your signals are all below like 1 MHz, and for short distances, you don't have to care and it would work without resistors, too. Don't know if it is possible for the CPLD you are using, but usually you can specify the drive strength of a pin (like 1mA, 5mA, 10mA). For low speed signals (< 1 MHz), you can use the lowest settings, then you don't have these overshoot signals. For short distances, like a few centimeters, you won't have problems either without a resistor.See for example my Kerberos cartridge:The traces between the Xilinx CPLD in the center and the SRAM and flash on the right side, are only 1-3 cm, so I didn't use any resistors. But the traces for the outgoing signals to the C64 at the bottom go through IC10 and IC11, which are EMI filter arrays with two integrated series resistors and one capacitors to GND for each pin in a T configuration.For switches, a 10k resistor should be ok.Each GCLK pin can be used for any clock in the CPLD, so you need to connect only one clock pin. Also usually a clock pin can be used as a normal GPIO pin as well. But if you have multiple clocks, you could connect them each to a GCLK pin. You don't put any capacitors to a GCLK pin.I think the global reset pin is the same: It allows you to use this signal inside the CPLD in your VHDL or Verilog code (or schematic entry diagram, which I don't recommend) and would require less resources when using as a reset signal, but otherwise can be left floating, at least for a XC9572 I didn't have to connect it. But the datasheet should tell you the details.

author: rstofer
author_rank: Super Contributor
timestamp: September 24, 2017, 04:16:24 pm
content: You should be able to define unused pins as INPUT with PULL-UP - that might actually be the default when a pin isn't used. Whether I used it or not, I would define the Reset input as an INPUT and use the internal PULL-UP. If I planned to connect a pushbutton, I would add an external 10k pull-up because the internal pull-up is so high there won't be enough current flowing through the switch to keep the contacts clean. Actually, I would probably prefer 1k since there won't be very much current flow into the pin.My problem with reflections was more a matter of fast rise times than frequency as the frequency was about 25 MHz. If I had been smarter, I might have tried to reduce the drive current.Even if reduced drive current would have worked, I prefer to have the current limiting resistors and many of Digilent's boards have them included by default.

author: garvind25
author_rank: Regular Contributor
timestamp: September 26, 2017, 06:20:53 am
content: OK. And yes, i forgot to ask... will quarter watt carbon film resistors do the job in this case. As per your PCB snap, you have used SMDs.Thanks and Regards,Arvind Gupta

author: rstofer
author_rank: Super Contributor
timestamp: September 26, 2017, 01:31:12 pm
content: For 3.3V logic and a 220 Ohm resistor, P = E^2 / R or 0.05 Watts and that only happens when the signal after the resistor is shorted to ground while being pulled up by the pin (or vice versa).