SDG6052X waveform memory size - Page 1
Forum section: electronics / testgear

author: suspension
author_rank: Regular Contributor
timestamp: October 29, 2024, 06:58:13 am
content: HelloI am planning to buy SDG6052X device and have a question about waveform memory. In the data sheet it says the waveform length is 2 ~ 20 Mpts. What does this mean? When does it use 2MPts and 20MPts respectively? Also any information regarding any interpolation done on phase when lookup is made is much appreciated.ThanksS

author: tautech
author_rank: Super Contributor
timestamp: October 29, 2024, 07:15:50 am
content: See:P37 2.1.7 To Set the Arbitrary Waveformhttps://int.siglent.com/u_file/download/24_08_13/SDG6000X_UserManual_UM0206X-E01C.pdf

author: egonotto
author_rank: Super Contributor
timestamp: October 29, 2024, 07:39:27 am
content: Hello,if I remember correctly, you can only use a maximum of 32 kpts in DDS mode.In TrueArb you can use up to 20 Mpts, but you only have a maximum sample rate of 300 MHz.Best regardsegonotto

author: suspension
author_rank: Regular Contributor
timestamp: October 29, 2024, 08:43:24 am
content: @tautech I checked the manual, but it is still unclear how many points they use in either mode and how they use them. I will a bit more and see.@egonotto in trueARB, is 300 the max sampling rate (MSps) or maximum bandwidth of the signal fundamental?Thanks

author: TurboTom
author_rank: Super Contributor
timestamp: October 29, 2024, 08:56:04 am
content: I verified the 20MSa at 300MSa/s in TrueArb modehere to better understand the internal topology(the "recent" specimen of the SDG6000X haven't got dedicated sample memory), yet without screenshots.A quite nice application of using a big sample file (albeit at a comparably moderate sample rate) isshown here.Performance-wise the SDG6000X is quite good, but the user interface and connectivity is mediocre at best and really shows the age of the instrument series.Decision-making can be hard...

author: tautech
author_rank: Super Contributor
timestamp: October 29, 2024, 09:16:38 am
content: Quote from: suspension on October 29, 2024, 08:43:24 amFrom the datasheet:maximumsample rate of 2.4 GSa/sand 16-bit vertical resolution.Do the maths.

author: egonotto
author_rank: Super Contributor
timestamp: October 29, 2024, 09:20:46 am
content: Quote from: suspension on October 29, 2024, 08:43:24 amHello,in TrueArb mode, 300 MHz is the maximum sampling rate. This means that at 20 Mpts you get a maximum frequency of 15 Hz.Best regardsegonotto

author: TurboTom
author_rank: Super Contributor
timestamp: October 29, 2024, 09:50:32 am
content: Quote from: tautech on October 29, 2024, 09:16:38 amTautech - this spec sheet claim is somewhat misleading! Even Texas Instruments specifies for the DAC38J82 that's getting used in the SDG6000X a maximum input data rate of 1.23 GSa/s. The DAC internally contains an interpolation engine with at least 2x interpolation required to achieve 2.4GSa/s. This works well for sine waveforms since these apparently can be generated inside the DAC (using its internal filters). But this also clearly shows that the 2.4GSa/s claim is somewhat "Sales Talk", while arbitrary wavefroms are processed at a "meagre" 300MSa/s. And this data rate can apparently be achieved via the Zynq SOC's high-speed connection to the Kintex "Sample Engine" FPGA, hence on more recent specimen of the AWG, the dedicated sample memory has been "economized"Whatsoever, the performance of the AWG is good and it meets the manufacturer's spec sheet data, one only needs to read carefully and interpret the information correctly...

author: suspension
author_rank: Regular Contributor
timestamp: October 29, 2024, 10:38:22 am
content: Quote from: tautech on October 29, 2024, 09:16:38 amhere it is.2.4 GSa/s is the output DAC update rate. Then comes the DAC interpolation which is x2. so from FPGA to DAC, the sample rate is 1.2GS/s per channel. To produce samples at that rate, FPGA should read those samples from somewhere at the same rate. There is no FPGA that cal clock at that speed for internal circuits, so probably it uses a poly-phase DDS which runs at much lower clock rate. Still, wave samples should come at this 1.2GS/s rate to produce the wave. To give this rate with a DDR ram, you need many chips and for two channels the combined data rate of the RAM should be 4915.2MB/s. I doubt the 4 RAM chips can provide that speed with latency required for the DDS. Alternatively FPGA block RAM can be used, but to hold 20MPts it require 80MB (16bit, two channels) which require super high end FPGA. Hence the confusion on how much samples are actually stored to feed the DDS fast. Probably much less than 20MPts. But if thats the case why does it need those 4 DDR RAM chips? Which seem to be missing in newest model? And then you have truARB mode which seem to run higher clock rates to create higher frequency waves which does not skip samples to make it even more confusing.

author: suspension
author_rank: Regular Contributor
timestamp: October 29, 2024, 10:39:41 am
content: Quote from: egonotto on October 29, 2024, 09:20:46 amThanks! Did you check it? 15Hz is super low frequency..

author: suspension
author_rank: Regular Contributor
timestamp: October 29, 2024, 10:50:40 am
content: Quote from: TurboTom on October 29, 2024, 09:50:32 amThis is great info! However, if I understand correctly, Zynq chip is used for the control system/UI/waveform point generation, pc communication etc. It is not in the datapath of the Kintex FPGA and DAC which are directly connected through 8 GTH lines. My guess is that the 4 DRAM chips are not needed to give the SFDR of the device. A sample memory of width N provides -6N db reduction from fundamental to the largest noise frequency. So in order to get say -80dB reduction, one need only 14bits in lookup memory (8K samples). This does not require an external DDR (block RAM is more than enough). But then, why did they have external DDR in earlier models?

author: egonotto
author_rank: Super Contributor
timestamp: October 29, 2024, 11:01:14 am
content: Hello,I just wanted to try it, but I can't get a connection from EasyWaveX to the SDG6000 and the SDS3000X HD.The SDG6000 is connected via USB, the SDS3000X HD via LAN.In TrueArb mode every point is scanned. At a maximum of 300 MHz, no more than 300,000,000 points can be scanned per second.I also wanted to try whether 20 Mpts means 20 000 000 or 20 971 520, but first I need a connection to EasyWaveX.Best regardsegonottoPS: After I installed NI-Visa I get a connection again.It is 20 971 520

author: egonotto
author_rank: Super Contributor
timestamp: October 29, 2024, 11:52:41 am
content: Hello,now I could try it. The frequency displayed is the highest frequency I could set.Best regardsegonotto

author: gf
author_rank: Super Contributor
timestamp: October 29, 2024, 12:10:43 pm
content: Quote from: suspension on October 29, 2024, 08:43:24 amIt is the maximum "virtual" sampling rate. TrueArb is not DDS. It reproduces the given wavetable 1:1 (i.e. with phase increment of 1 sample) at a virtual sample rate of your choice (maximum 300MSa/s). The resulting discrete-time signal (stream of samples) is then resampled/interpolated by the engine from the virtual sample rate to the output sample rate of 1.2 GSa/s.

author: egonotto
author_rank: Super Contributor
timestamp: October 29, 2024, 12:24:39 pm
content: Quote from: gf on October 29, 2024, 12:10:43 pmHello,Why would you resample the signal? It certainly won't get any better.Best regardsegonotto

author: gf
author_rank: Super Contributor
timestamp: October 29, 2024, 12:49:02 pm
content: Quote from: egonotto on October 29, 2024, 12:24:39 pmBecause the DAC sample rate is still fixed, and so is the reconstruction filter which must fit with the sample rate. An analog high-order reconstruction filter which is adjustable over many decades would be very difficult to realize. OTOH, an adjustable digital resampling filter is quite feasible.EDIT: However, in the sense of the Nyquist–Shannon sampling theorem, I findlinearinterpolation suboptimal, and sin(x)/x interpolation seems to be only supported by SDG7000A.

author: TurboTom
author_rank: Super Contributor
timestamp: October 29, 2024, 01:10:04 pm
content: Quote from: suspension on October 29, 2024, 10:50:40 amThat's a good question. Since the SDG6000X series had been designed more than seven years ago when Siglent just moved to the Zynq SoC plaform on their (back then) most recent products, maybe they had little experience and designed the SDG6000X better "safe than sorry" with dedicated sample memory. Only later on they may have realized that a direct sample data transfer from SoC memory through the sample engine FPGA to the DAC works okay at 1.2GBytes/s (plus overhead) to meet their instrument's specs.Standard waveforms may reside completely within the Kintex's Block RAM or may possibly be generated on-the-fly, so they can be transfered to the DAC at a higher rate.Or they may have thought of certain software extensions that may have required dedicated sample memory and that they discarded further down the line. Probably only Siglent engineers can answer this question accurately. Anyway, I think it's safe to say that it certainly went along with some cost-cutting measures from the management department...

author: egonotto
author_rank: Super Contributor
timestamp: October 29, 2024, 04:55:35 pm
content: Quote from: gf on October 29, 2024, 12:49:02 pmHello,that sounds very reasonable.I have now made a waveform with 15 times 1 and 15 times 0.If you sample it at 300 MHz you get 60 pts 1 and 60 pts 0 (regarding 1.2 GHz)But if you sample at 297.5 MHz you get 60.5 pts 1 and 60.5 pts 0.With 10 s persistence at 297.5 MHz, shouldn't you see somewhat broader edges?I don't see any difference.Best regardsegonotto

author: suspension
author_rank: Regular Contributor
timestamp: October 30, 2024, 08:22:55 am
content: Quote from: TurboTom on October 29, 2024, 01:10:04 pmI guess this is a good explanation.However I am bit unclear if the latest versions that use ZynQ use it for DDS engine or just user control/UI/connectivity? the way I see based on some photos, it looked like they have one FPGA (Kintex?) for DDS and one for embedded control which can be a ZynQ (and no DDR for Kintex). I doubt that it will be possible to transfer wave samples on the fly to DDS engine from ZynQ as this will require connectivity with two FPGA's at 2.5 x 2 GB/s which is very unlikely. Also the DDR chips associated with ZynQ are probably not capable of supporting this data rate requirements anyway. There is no point in using ZynQ block RAM to store wavedata and transfer them to Kintex on the fly as they can just be stored in Kintex blockram instead.BTW, I asked this question from Siglent and got the usual response asking me to check the data sheet.

author: gf
author_rank: Super Contributor
timestamp: October 30, 2024, 09:50:34 am
content: Quote from: suspension on October 30, 2024, 08:22:55 amIMO we must distinguish DDS and TrueArb. The DDS wavetable isn't that large, so I think it can live in the FPGA anyway. Only the TrueArb wavetable can be huge. If you consider transfer on the fly only for TrueArb wave samples, then the maximum rate is 2 x 600 MB/s (not 2.5 x 2 GB/s). RAM access for TrueArb is sequential (except at the wrap-around), which may also help.

author: Performa01
author_rank: Super Contributor
timestamp: October 30, 2024, 06:07:50 pm
content: Quote from: TurboTom on October 29, 2024, 01:10:04 pmFinally you've got to the right conclusion.In fact, that additional RAM has been a backup ("plan B") in case the direct data transfer won't be fast enough - which the HW engineers couldn't tell for sure before the prototype was functional. So, even though some early specimen (like the one sent to Shariar) had the RAM chips populated, they have never actually been used. As a consequence, they were "economized" early on.