How do you size via drill holes anyway?  - Page 1
Forum section: electronics / general

author: gnuarm
author_rank: Super Contributor
timestamp: January 26, 2021, 12:34:23 am
content: I find electronics to be fairly straightforward most of the time. It's the getting a board manufactured that I find difficult. Engineers will tell you about all manner of things you need to do to make your boards more manufacturable, sometimes contradictory. One that I've never quite gotten a handle on is specifying drill hole sizes.For unplated holes it is obvious that the specification is simply the hole size. For vias and pads it seems the specification is typically the hole size after plating and it is left to the fabricator to pick the drill diameter.So looking at a spec from a chip maker for laying out the PCB for a BGA, what are they specifying for a hole size, the finished hole or the drill size?https://www.xilinx.com/support/documentation/user_guides/ug393.pdfI ask this because it seems in the case of a 0.8 mm pitch BGA with a 10 mil hole and a 5 mil annular ring is right on the edge of the inexpensive production processes. I'm wondering if this is pushing too far?I read a reference that talks about hole "shadow" which is the hole size plus the variation in hole location from the drilling process. This document from 2001 uses 10 or 12 mils depending on panel size. They use the term Capture Pad Diameter to indicate the size of the pad which is another 4 mil. Clearance Pad Diameter defines the spacing from the specified hole center to another trace which adds 10 mils to the hole shadow.https://speedingedge.com/wp-content/uploads/anatomy-of-a-plated-hole.pdfI don't know how much the manufacturing process has improved in 20 years, I expect some at least. Anyone have more recent information?The specs for a 0.8 mm BGA mentioned above uses 20.4 mil for the via pad which is the hole shadow (for the smaller panel) without the via margin.This is why I'm asking about the drill size vs after plating size. The IPC class II spec allows for significant break out of the hole from the pad. But if the plated hole is broken out from the pad, the unplated hole will be significantly more broken out. I believe IPC is using the plated hole size since that is what you can measure non-destructively. So prior to plating the hole can be very much broken out from the pad which in the case of being in the direction of the trace connecting to the BGA pad would very likely create a problem.I'm sure IPC also has a spec on how much of the trace must be connected to the via pad. I guess I'm not clear on how to spec such a board and make sure I get a good result. Here is a drawing from the Xilinx doc with dimensions shown for 0.8 mm BGAs.http://arius.com/public/UG393_Spartan-6_FPGA_PCB_Design_Guide_pg72_0.8mm.pdf

author: NorthGuy
author_rank: Super Contributor
timestamp: January 26, 2021, 03:14:20 pm
content: Quote from: gnuarm on January 26, 2021, 12:34:23 am0.8mm is roughly 32 mil. If you want to put a trace between vias, the 32 mil distance must contain the hole + 2 annular rings + 3 trace/space widths. 10 + 2*5 = 20. So you'd need (32 - 20) / 3 = 4 mil traces. I think the process which allows 4 mil traces would not have any further surcharges for 8 mil holes compared to 10 mil.I made a 0.8mm BGA board once for PIC32MZ in OSHPark once using 10 mil holes, 17 mil vias and 5 mil traces. This violated their annular ring specs, but worked out perfectly. You certainly cannot use them for production.Few days ago, I got a board from JLCPCB with 0.8mm BGA with 8 mil holes, 18 mil vias and 4 mil traces. It worked out Ok too. The same board had 1 mm BGA where I was able to put 2 traces between pads with the same specs.I always thought that if you meet the annular ring specs, this guarantees the hole being within the ring.You can fan out three outer rows without ever putting wires between vias. Then you don't need to worry about holes.