hybridfree/eevblog-posts huggingface dataset:
TL866II Plus and Lattice GAL22V10D - Page 1
Forum section: electronics / general

author: Wawavoun
author_rank: Regular Contributor
timestamp: October 18, 2024, 02:50:32 pm
content: Hello,I bought eight Lattice GAL22V10D-15LPN. They come from China via Ebay.Using the TL866II Plus (firmware and soft up to date) with the GAL22V10D chip reference I can read the chip (its not a sign of something because it is possible to read also when the slot is empty) but at least means that there is no short between GND and VCC.As soon as I try to program with VPP 16 V any of these chip I get an overcurrent error. The programming go to end if I use VPP 13 V but then the chip is not programmed (verify error).These GAL are know to work with this programmer so may be I have got a bad or without spec setOr is there any solution to solve the problem (I think to an external power supply like for 2716 uvprom) ? But this only can work if it is compatible with the programming cycle (I dont know if VPP is continuous or pulsed).Any help will be appreciated.Best regards.Philippe

author: MadTux
author_rank: Frequent Contributor
timestamp: October 18, 2024, 08:28:41 pm
content: Get a real GAL22V10D from verified source, digikey, old stock... and if it works => Chinese fake garbage.Get a refund, only thing that works with them, make them pay more than what they earn with that fake junk!

author: Wawavoun
author_rank: Regular Contributor
timestamp: October 21, 2024, 02:01:29 pm
content: I do a test with another Lattice GAL22V10D coming from another source and the TL866II Plus programmer works well... I can read, write and verify the gal !So for sure I got a defective or fake set of gal !I am not absolutely sure of the thing but my advice is to be careful with chips that do not have a hollow dot printed near pin 1.Can somebody confirm or deny this ?Thanks and regards.Philippe

author: bson
author_rank: Unknown
timestamp: October 22, 2024, 08:38:21 pm
content: Fake, for sure.
New service to rent and trade-in FPGA, RF and AI boards! (US only)  - Page 1
Forum section: electronics / general

author: Asaad
author_rank: Contributor
timestamp: November 14, 2024, 10:14:38 pm
content: Hardware fellows, I hope this finds you well.We're starting an awesome new community to rent and trade-in your beloved AI and FPGA boards! Starting from Cupertino, serving Bay Area, CA and the US only for now. (Hopefully more countries in the future)https://www.devboardrental.com/We have all been there. Spending hundreds and even thousands of dollars on development boards to finish a project or two and learn new tricks for few months and then they end up in the hardware pile.But few months later, the next cool thing arrives, and you feel that regret and wish to yourself you have an extra $1k here and there to try this cool board -and add it to the pile- and so forth.. You end up with $10k or $15k of useless hardware collecting dust in your drawer!It doesn't have to be like this! With circular economy, we can all enjoy latest tech without breaking the bank or hurting the environment. Please let us know what do you think and which fav boards you want added to the inventory!
Xilinx/AMD Artix-7 Memory and FIFO Verilog Models - Page 1
Forum section: electronics / general

author: trossin
author_rank: Contributor
timestamp: November 18, 2024, 02:58:55 am
content: After experimenting around with the Memory and FIFO generator, I've created some base models of the RAM/ROM and synchronous/asynchronous FIFOs. I created parameterized models that can be instantiated to create different configurations that can then be simulated using an external simulator from the Vivado environment. I use Icarus for a simulator and my VcdView program to look at waves (GtkWave works as well). I see a 10x to 20x speed up in my edit/debug cycle over Vivado. Also, I don't have to re-run the simulation when adding more signals since I just use value change dumps.You can find the models, examples and documentation here:https://sites.google.com/site/tedrossin/home/electronics/xilinxamd-fpgaThe models and docs are under Common and the the examples are under Block RAM and FIFO Experiments. The Experiments have Vivado 2024.1 projects and source as well as test benches that run with Icarus or Vivado. I also include a little project that uses the serial port or some buttons to control LEDs using PWM. The words in the Basics section give some info on how to deal with the projects.I attached the PDF of instructions on how to use and create the models for a project.
Intel/Altera ROM megafunction - Page 1
Forum section: electronics / general

author: AussieBruce
author_rank: Regular Contributor
timestamp: October 07, 2024, 02:41:15 am
content: I have a need for a small amount of nonvolatile storage in a Verilog application with a Cyclone-2 FPGA. The device itself has no nonvolatile storage of course, I’m assuming that the megafunction simply writes the associated data to the separate boot EEPROM that handles the restoral of the config data on powerup, and reads it in as required. Ie: there is no additional hardware needed. Is this correct, and are there any gotchas in using this megafunction, such as write timing, that I need to be aware of?

author: Someone
author_rank: Super Contributor
timestamp: October 07, 2024, 03:13:38 am
content: Which specific megafunction, and what primitives does it map to?Generally ROMs are implemented as RAMs and loaded at configuration from data in the bitstream. There are reverse engineering efforts to allow on device access to that flow but you're getting off into pretty wild territory.

author: BrianHG
author_rank: Super Contributor
timestamp: October 07, 2024, 03:35:00 am
content: For Altera's LPM_ROM, LPM_RAM and LPM_DP_RAM, the 'init_file' allows you to define the memory contents on powerup. That content is hidden away, compressed somewhere in the bootprom when compiling your FPGA, it is out of your control.The init file can be in Altera's .mif format created by Quartus.Or it can be in intel .hex format.Tools exist which can convert 8/16 bit raw binary data files into Altera's .mif format.You cal also manually assign contents to a memory array in your Verilog source code, however, if you do not register the input address and output data, your assigned data will be synthesized as logic instead of being auto interpreted as a M4K/M9K block ram. Though, you can force a blockram attribute to your array.
RapidSilicon - what happened to "open-source" FPGAs ? - Page 1
Forum section: electronics / general

author: Hella_Wini22
author_rank: Contributor
timestamp: September 27, 2024, 02:42:28 pm
content: I remember eagerly following RapidSilicon and their vision of open-sourcing the FPGA fabric.They were busy talking about their open solutions and their first physical child Gemini devices that were to serve both as useful tools for mere mortals as well as the tech demonstrators.AND then ... nothing.But RapidSilicon is still there. Still talking about Gemini, but materials feel a bit stale.Does anyone here have experience with those and development tools ?What do they use - Yosys or something else now and how well does it work ?https://rapidsilicon.com/gemini/

author: mark03
author_rank: Frequent Contributor
timestamp: October 06, 2024, 08:48:48 pm
content: Designing custom silicon to achieve an open-source FPGA is an awfully tall order. It would make a lot more sense to convince one of the major players to open up their bitstreams and  actively support the free tools with salaried engineer hours. There might be a first-mover advantage in doing so before the others catch on.History (ARM, etc.) suggests this has more to do with groupthink and irrational risk aversion than with sound business decision-making. Opening up your devices does not preclude retaining a proprietary toolchain with premium performance. (That's the case right now with ARM and their in-house, $$$ compiler---significantly faster/smaller code than gcc or llvm/clang.) But it does generate a lot of free marketing and goodwill, as well as the possibility to "own" the next generation of engineers by winning student mindshare.I think effort would be better spent trying to educate the incumbent players than developing an almost certainly inferior product line which will appeal to almost no one outside of academia.

author: langwadt
author_rank: Super Contributor
timestamp: October 06, 2024, 08:59:52 pm
content: Quote from: mark03 on October 06, 2024, 08:48:48 pmI suspect the tools would be an as big or bigger job

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 06, 2024, 09:09:01 pm
content: Quote from: langwadt on October 06, 2024, 08:59:52 pmYes, but there's already yosys/nextpnr, that even some newer FPGA vendors use now. While not perfect, that's an option which does the job. Stll some work to be done for sure.Judging from that page:https://rapidsilicon.com/raptor/, they seem to use yosys, and other various open-source projects that already existed. But from their "marketing" material, it looks to me like they have tried to do too much.Beyond shipping actual products, which is already a big endeavour, the question is whether they address any real demand.
Pull-up/pull-down resistors - Page 1
Forum section: electronics / general

author: edba
author_rank: Contributor
timestamp: September 24, 2024, 11:29:51 am
content: Hi allWhen calculating a pull-up/pull-down resistor for any logic type you normally consider the DC operating conditions i.e. leakage current of the gate input and voltage threshold required. You also need to consider the transition time from e.g. low to high. This is so not upset the internal circuitry of the gate, cause multiple transitions and increase current consumption. But what if the inputs are to be static i.e. they will never change when powered and you just need them pulled up or down. Yes you could connect them directly to the supply, but say you want to be safe and connect through a resistor. Presumably as only one transition is required on power up, you don't really need to worry about transition time? i.e. you could use a higher value resistor to reduce current consumption from the power supply whilst having a slower transition time outside what is recommended for the gate?

author: ejeffrey
author_rank: Super Contributor
timestamp: September 25, 2024, 03:15:45 pm
content: Assuming FET inputs the input leakage current is small and almost almost always negligible. Pretty much any value will work, so just use a part already in your BOM. If pressed, I prefer lower values to avoid any chance of noise causing unwanted transitions. Honestly this is a bit superstitious, unless you do something pathologically bad that's not a serious concern.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 04, 2024, 01:44:25 pm
content: Quote from: edba on September 24, 2024, 11:29:51 amSafe from what?
Multiple MIG controllers clocking - Page 1
Forum section: electronics / general

author: rgc_
author_rank: Newbie
timestamp: September 25, 2024, 11:32:31 am
content: Hello folks,I have a board which has two independent DDR3 chips, in two separate banks.When instancing two MIG controllers, the UI gives me two ui_clk signals.Providing that both MIG controllers get their clocks from the same hardware clock, is it possible to have a single ui_clk for both? or should I clock synch the whole UI line set?Thanks/rgc
Microchip - what the heck is going on with PolarFire II ? - Page 1
Forum section: electronics / general

author: Hella_Wini22
author_rank: Contributor
timestamp: September 26, 2024, 02:40:21 pm
content: MC has been announcing it for eternity.It was supposed to be the next Big Bang in the world of both RISC-V SoC and prudent, efficient, low-power radiation tolerant FPGAs, to improve on everything and bring us IoT devices before that was even a thing.New RISC-V cores, higher bandwidth programmable matrix, faster, adaptable SERDES lines with various cutting edge PCIE protocols ( 1-lane PCIev5, 2-lane PCIev4, more PCIev3 lanes etc)And then... crickets.They've announced a mailing list that was suppossed to keep people informed about the PF-II progress, which has been DEAD SILENT from the announcement till present.There were some hints that there should be a reveal in the middle of September.Which has just passed.What's going on ?Whatever program MC eats, it immediately stalls and dies.Or maybe this is just an eye of the storm in front of big internal refactoring ?God knows their many SW stacks are deeply rotten.Not long ago they've announced Yosys support for PolarFire, which is nice step in the right direction I guess.Then we saw another step - instead of that MPLABX pile of crap, they announced VSCode modules support.Which seems awesome.Anyone with some insider knowledge here that s/he'd care to share ?Is there PFII to come out ? What about refresh of other programs, Like Igloo2 line or SmartFusion ?PolarFire II was supposed to be a big deal - kickass new RISC-V based FPGA line.Now we have friggin Efinix come from nowhere and present TWO RISC-V based lines: Titanium and Topaz.And there are also some Chinese contenders, too... 🙄But so far, not even a fart from MC. What's going on ?PolarFire isn't even the sole RISC-V player in the field now that Efinix has Titanium and Topaz lines, also a few cheap Chinese players have entered the arena... 🙄Only semi-positive thing I've hear lately about MC's FPGA program is about their support for Yosys.And even that is overwhelmed with their desperation over Libero crap, so it feels more like retreat than a win.If you are going to support open source make a good effort, invest some serious $$$ and effort into it.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: September 27, 2024, 08:01:05 am
content: They are currently only giving details about the Polarfire II if you sign an NDA with them. A release is planned next year but yeah it's taking a very long time
Flash backed LLMs on FPGA? - Page 1
Forum section: electronics / general

author: NiHaoMike
author_rank: Super Contributor
timestamp: September 23, 2024, 04:59:35 am
content: My understanding of LLMs is that there's a very large "lookup table" that's iterated through many times while it generates the output. It's normally stored in RAM which gets quite expensive on the larger models. But what about storing it on Flash instead? I see a cited reason is that SSDs are too slow and would bottleneck it, but what if you just had a FPGA with a lot of Flash chips wired to it? Those are readily available in the form of "ioDrive" SSDs, with 365GB versions going for about $32. Reprogramming one of those for LLM use would be quite a task, but would it even be technically feasible?

author: Marco
author_rank: Super Contributor
timestamp: September 23, 2024, 06:40:34 am
content: Traditional models need the entire set of parameters for each input (a dense model) but there is a lot of research showing only a small amount of parameters are relevant for an input (see for instance Turbosparse models). A dense model needs massive bandwidth to parameters to the point flash is not realistic. With dynamic sparsity in theory a parameter streaming LLM is possible, but the models are still very poorly optimized for it. The attention parameters (Q/K/V) are generally still dense and the predictors prevent good pipelining of parameter streaming and computation.As of yet no one is doing models ground up designed for local/streaming inferrence, the Turbosparse Mixtral models are the best you can get. As for research into better models, there is only Pre-Gated MoE. It's not a very active field, most models for embedded use just try to stay tiny, not dynamically sparse.
Small footprints with 'many' min 12G tranceivers - Page 1
Forum section: electronics / general

author: Aiy
author_rank: Regular Contributor
timestamp: November 01, 2024, 07:49:59 pm
content: Hi Forum,I have a quandary selecting an FPGA for a build.I'd like to leverage the advantages of modern JESD204 ADCs (5GSPS+ like for example the TI ADC08DJ5200RF ) together with an FPGA in a design, i.e. high speed serial lanes (12G+) with at least 8 lanes receive.I don't need 2000 GPIO for the LEDs in my design.. maybe I'd like to hook up 1 or 2 DDR IC for storage, and a USB 2.0 FTDI JTAG / high speed data uplink is necessary for what i'd like to do. But a small footprint FPGA with a 8+ 12G tranceivers is what I need.From what I've gathered on my lonesome, the alternatives with 8+ receiver pairs in 2024 Q4 are:AMD Artix Ultrascale+ AU10P (or up)AMD Kintex (XC7K325T or up)AMD Kintex UltrascaleAMD Kintex Ultrascale+Intel Agilex 5Microchip PolarFire (725 ball or up)...Anybody else got any any more resonable alternatives?I think that the AMD/Xilinx tools and docs are far superior to the alternatives, but I just wanted to ask if anyone have alternatives that I don't know of.Best regards,

author: asmi
author_rank: Super Contributor
timestamp: November 01, 2024, 08:37:03 pm
content: Kintex-7 has only 10G transceivers as far as I remember. New Spartan US+ are supposed to have 16.3 Gb/s transceivers too - but they are not out yet. Also watch out for package/speed grades - some packages/speed grades have lower limits on transceivers, for example the same silicon of Artix US+ can have max line speed of 16.375 Gb/s or 12.5 Gb/s depending on package.

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: November 03, 2024, 12:29:03 am
content: PolarFire FPGA MPF100T-FCG484E has 8x 12.7Gbps transceiver lanes.

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 03, 2024, 07:53:41 pm
content: Easy. Use Efinix Titanium. and quite affordable, tools are OK. big bang for your buck.Or, Spartan Ultrascale, next year.. or Xilinx Artix Ultrascale (and is shipping AU7P) , or Lattice...Microchip ?! ROFL. where is is polarfire2 LOL.what footprint size ? / Budget ? / # LEs ?
Avnet for Xilinx XC3S400A - Page 1
Forum section: electronics / general

author: ebclr
author_rank: Super Contributor
timestamp: June 10, 2024, 10:07:19 am
content: I'm looking for some info on this development board from Avnet for Xilinx XC3S400A. Do you have any tips?

author: RomDump
author_rank: Regular Contributor
timestamp: June 10, 2024, 11:58:09 am
content: Quote from: ebclr on June 10, 2024, 10:07:19 amIt's a Avnet Xilinx® Spartan®-3A Evaluation Kit. I have attached the Product Brief and User guide.

author: bingo600
author_rank: Super Contributor
timestamp: June 10, 2024, 12:07:14 pm
content: Took 5 minhttps://weble.upc.edu/asig/postgrado/digital/modulo3/curso_Febrero_2011/Avnet%20Spartan3A%20eval%20kit/user%20guide/xlx_s3a_evl_ug_rev2_112008.pdfA project ucs filehttps://github.com/hanshuebner/rekonstrukt/blob/master/vhdl/Avnet_Sp3A_Eval_081201.ucf

author: glenenglish
author_rank: Frequent Contributor
timestamp: June 12, 2024, 03:37:08 am
content: that board should be in a museum

author: ebclr
author_rank: Super Contributor
timestamp: September 20, 2024, 09:05:41 pm
content: Thank you

author: ebclr
author_rank: Super Contributor
timestamp: September 20, 2024, 09:08:48 pm
content: Thank you, But I didn't find anything helpful in your post
Xilinx DDR Controller Strange Behavior in Sim - Page 1
Forum section: electronics / general

author: mark179
author_rank: Newbie
timestamp: January 12, 2024, 06:50:11 pm
content: Hey guys, I'm having some issues with writing to a DDR controller via an AXI-MM interface. We don't have a board yet so I'm trying to get this verified in simulation.First, I loaded up the DDR Controller example design (which doesn't simulate because it's looking for some file in a folder that doesn't exist and I'm not sure where it is pointing to.Code:ERROR: failed to open /tmp/sim_tb_top.\mem_model_x16.mem.memRank.memModel.u_ddr3_x16 .open_bank_file.0.So I'm working with no sim and very little guidance on the DDR Interface, but I pull the test module connecting to this interface and put it in my design in case the thing needs to communicate to work.No matter what I do, I seem to find wready drop out after the 21st write, whether that is in a huge burst or an 8-word one. I have attached a few simulation images below to show what I mean. oqe1 shows the whole write until it fails on the third transaction, oqe2 shows the first good transaction, and oqe3 zooms in on the third bad transaction. I have temporarily routed bvalid back around to bready just to read the response in my write state, where bresp is now 2. I have absolutely no idea why the write is failing here. Any pointers to guide me in the right direction?

author: mark179
author_rank: Newbie
timestamp: January 25, 2024, 03:41:08 pm
content: So I ended up fixing this issue some time ago. I had mistakenly set awsize to 7 when it should have been 4... Changing this fixed everything!

author: korystoltenberg
author_rank: Newbie
timestamp: September 21, 2024, 10:32:00 am
content: It seems like you're having trouble with the DDR controller simulation using the AXI-MM interface. The missing file error likely points to a memory model file not being found, which is usually generated during the build process. Double-check your project setup to ensure all files are included.The wready signal dropping after 21 writes may indicate a buffer issue or back-pressure from the controller. Make sure your burst length and AXI settings align with the DDR controller's configuration.The bresp=2 error suggests an address alignment or memory mapping problem. Since you're routing bvalid to bready, ensure your simulation accurately reflects how the DDR controller works in hardware.For more insights on related to Sims and registration issues, checking out resources like [spam link removed] can provide solutions from others working with similar setups.
Where can I find 3D model of 5CEFA7F23I7N? - Page 1
Forum section: electronics / general

author: Luosi
author_rank: Newbie
timestamp: September 03, 2024, 02:38:14 am
content: When I write this article, I just find the footprint of it. I can not find its symbol and 3d model,who can tell me where to find them?https://www.emsfpga.com/news/5cefa7f23i7n-fpga-features-applications-and-datasheet

author: Someone
author_rank: Super Contributor
timestamp: September 03, 2024, 02:40:10 am
content: Why do you need a symbol and 3D model?

author: zapta
author_rank: Super Contributor
timestamp: September 08, 2024, 08:03:12 pm
content: Is this the 3d model you are looking for (see zip below)?https://grabcad.com/library/fgga484-1/files#!Also, kicad seems to have a footprint named Xilinx_FGGA484.
Digital, Java rtl sim, with vhdl and verilog support (educational only) - Page 1
Forum section: electronics / general

author: DiTBho
author_rank: Super Contributor
timestamp: August 24, 2024, 09:27:46 am
content: "Digital" is an easy-to-use digital logic designer and circuit simulator designed for educational purposes.It's on github, seehere.I've been using it for a couple of days, and for me, I have to say that for simple projects it works well and allows you to integrate external files written in vhdl (or verilog), using iterative objects such as buttons, leds, hex displays (4bit), which is nice and very handy!However, the vhdl simulation part has some issues with signals, and it's not easy to get timing diagrams, neither it's possible to comfortably use "vhdl packages" among files.It's much more enjoyable with logic gates and then to export "HDL code" than writing HDL code.Anyway, I'm reporting it, because it's worth it

author: DiTBho
author_rank: Super Contributor
timestamp: August 24, 2024, 09:29:10 am
content: (I'm using it to prepare a live demo.I could do it another way,but I want to evaluate all the alternatives)

author: DiTBho
author_rank: Super Contributor
timestamp: August 24, 2024, 09:30:17 am
content: (umm, exporting to png ... doesn't correctly workI cannot attach a decent snapshot of what I am doing)

author: c64
author_rank: Frequent Contributor
timestamp: August 25, 2024, 09:15:18 am
content: Interesting ...They support VHDL and Verilog, and can output into JEDEC file for GAL16v8 or GAL22v10.

author: DiTBho
author_rank: Super Contributor
timestamp: August 25, 2024, 11:43:42 am
content: One of the things I do find annoying with Digital is that vhdl-blocks(1)do not support packagessupport records internally to a block, but not outsideThis makes more difficult to write complex projects.Code:.____________ ___________| | | || record | std_logic_vector | record || +------------------------------------> ||____________| |___________|Since Vhdl does neither support "C-casting" nor "C-union", and since vhdl-blocks in Digital only support "std_logic_vector", you have to "serialize" a Vhdl-record into std_logic_vector, then you can wire two blocks, and then you have to "deserialize" std_logic_vector into record.(1) in Digital, in order to use Vhdl you have to use a "Vhdl-block", which points to an external Vhdl file.Vhdl-blocks can be connected with wires, wire can be std_logic (1bit) or std_logic vector (n-bit).

author: DiTBho
author_rank: Super Contributor
timestamp: August 29, 2024, 01:09:49 pm
content: I wish there was something similar but written in C and using { Moitf, GTK*, QT*, ... } graphic libraries.Java is OK, but ... well, not ideal, and I cannot have a JRE on { HPPA, MIPS32, MIPS4, POWER10, ... }
any VHDL-Geany? any beautifier? - Page 1
Forum section: electronics / general

author: DiTBho
author_rank: Super Contributor
timestamp: August 29, 2024, 01:18:09 pm
content: is there any software(1) that works like Geany works for C files?That understands where an entity, record, constant, type, subtype, ... is defined and lists it somewhere?I could implement a VHDL parser to add a similar functionality to my text editor (ncurses), but...... well... I find myself implementing too much stuff.Another wish: is there a VHDL beautifier?my two wishes for the genie of the lamp(1) possibly open source, written in C or C++, for GNU/Linuxon { MIPS32, MIPS4, POWER10, HPPA2, .. }: I cannot compile { Java, Rust, Golang ... } and I have a few technical difficulties with python

author: DiTBho
author_rank: Super Contributor
timestamp: August 29, 2024, 01:22:49 pm
content: At the moment I am randomly usingScriptumby Hdlworks.It's a binary application that runs on Windows/x86 and GNU/Linux-x86, seehere.It's nice, freeware, but well ... umm, too limited

author: Tation
author_rank: Regular Contributor
timestamp: August 29, 2024, 02:02:13 pm
content: Note that I haven't used it, but, have you tested VHDL for Professionals inside Visual Studio Code?

author: nctnico
author_rank: Super Contributor
timestamp: August 29, 2024, 06:07:29 pm
content: Quote from: Tation on August 29, 2024, 02:02:13 pmIn addition there is also Veditor, a Verilog / VHDL plugin for Eclipse which works reasonably well.

author: mfro
author_rank: Regular Contributor
timestamp: August 29, 2024, 06:16:45 pm
content: vim/gvim supports VHDL syntax highlighting andhdl_checkerthat implements the language server protocol standard
I'm confused about some simulation results, strobe confusion - Page 1
Forum section: electronics / general

author: betocool
author_rank: Regular Contributor
timestamp: August 20, 2024, 10:51:37 am
content: Hey all,I'm confused with the following situation. In a synchronous system where all signals are driven by the rising edge of a clock, the following statement:Code:if(rising_edge(clk)) thenif (psram_state = PSRAM_RST) thendelay <= delay + 1;if (delay = 35000) thendelay <= (others => '0');psram_state <= PSRAM_IDLE;read_i <= '1';data_in <= ca(to_integer(ca_cnt));ca_cnt <= ca_cnt + 1;end if;end if;would set "read_i" and all other variablesafter"delay" has been detected to be 35000... for exampleOn the same simulation, in another module of the code, I wait for "read_i" to be set to '1' to kick off a process. But what I'm seeing is that the process gets kicked off on the rising edge of the clock as well as "read_i".Code:if(rising_edge(clk_i)) thenif (psram_state = PSRAM_IDLE) thenif(read_i = '1') thenpsram_state <= PSRAM_CMD;wait_cnt <= X"00";cmd_data <= data_in;end if;end if;--- Code goes on....The main difference, the top part of the code runs in the testbench file, the second on a module that should be pure hardware. I am very very confused. That stuff used to trip me up a lot way back, and now I wonder what's happening or what I'm doing wrong.Cheers,Alberto

author: Someone
author_rank: Super Contributor
timestamp: August 20, 2024, 10:09:45 pm
content: clk != clk_iZoom right in on the simulation (assuming it is a good simulator and will show the true delta cycles)https://vhdlwhiz.com/delta-cycles-explained/

author: betocool
author_rank: Regular Contributor
timestamp: August 20, 2024, 11:54:20 pm
content: What a numpty! Yeah, ok, I didn't know that.I was assigningCode:-- Clocksclk_i <= clk;in the testbench. I changed it to clk directly and it behaves as I expected it to.Thanks man!Cheers,Alberto
VHDL: How to print out variables' value? - Page 1
Forum section: electronics / general

author: notooth
author_rank: Contributor
timestamp: August 18, 2024, 03:22:46 pm
content: Can anyone guide me print out value of an VHDL signed/unsigned variable to the screen in Vivado?

author: hamster_nz
author_rank: Super Contributor
timestamp: August 19, 2024, 08:28:49 am
content: Assuming you mean in simulation:Code:report "Sync count is " & integer'image(to_integer(sync_count));Gives:Note: Sync count is 106If you want to write a value to the serial port let me know, and I'll paste some code here.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: August 19, 2024, 10:18:58 am
content: And if it is when running the code in an FPGA, you can use in-system debugging as explained in chapter 10 and over ofthis document
Help getting started with ModelSim - Page 1
Forum section: electronics / general

author: rea5245
author_rank: Frequent Contributor
timestamp: August 17, 2024, 02:48:15 pm
content: Hi. I can't get ModelSim to simulate. It gives me a "# ** Fatal: (vsim-7019) Can't locate a C/C++ compiler for 'DPI Export Compilation'." error.I'm using ModelSim Lattice FPGA version 2023.3 on Windows. The Verilog code is just from the manual's "Basic Simulation" tutorial, and it compiles fine. There's no DPI in it. I don't even see a place in ModelSim to configure a C/C++ compiler like gcc or Visual C++. The user's manual says I need to "acquire gcc", but how would ModelSim then locate it?I'd rather it not even be looking for a C compiler, since I'm not using DPI.How can I get this working?Thank you.
Dual Data Rate on Artix7 FPGA - PSRAM interface - Page 1
Forum section: electronics / general

author: betocool
author_rank: Regular Contributor
timestamp: August 16, 2024, 03:59:58 am
content: Hey all,This is a bit of a generic question. I'm considering a DDR 8bit PSRAM chip for a board design with an Artix7-50 FPGA. The datasheet for the chip (https://www.digikey.com.au/en/products/detail/infineon-technologies/S80KS5122GABHI020/15965288) for reference.From the datasheet, the read operations occur at each rising and falling edge, the write operations are center aligned (Embarrasing, I don't seem to know how to attach images at the moment...)Basically, I'd like to know if there are any good examples on how to use both clock edges on the Artix7 series, there doesn't seem to be native support for a DDR 8-bit PSRAM from the IP blocks.Cheers,Alberto

author: glenenglish
author_rank: Frequent Contributor
timestamp: August 16, 2024, 07:58:13 am
content: Use the ODDR and IDDR primitives.Use the VHDL Generate keyword to make a n bit wide bus of primitives.for clock, you could use a 4x (quadrature) clock, or use a DCM/PLL etc to get a 90 deg phase shifted clock for data samping.

author: betocool
author_rank: Regular Contributor
timestamp: August 16, 2024, 08:44:05 am
content: Thanks!Just after I asked the question I found the ODDR and IDDR blocks, which will probably do what I need. I just ran a simulation and a proper example at a lower speed and it all seems to work well. I didn't know that I was looking for the ODDR / IDDR blocks.Cheers,Alberto
Cyrite HDL 'official': Python HDL and verification - Page 1
Forum section: electronics / general

author: laugensalm
author_rank: Regular Contributor
timestamp: August 12, 2024, 02:34:14 pm
content: Hi,I'm hereby announcing a somewhat stable release of a Docker container containing a comprehensive development ecosystem based on a Python HDL (named Cyrite HDL after some history).The underlying generator kernel was originally designed to generate signal processing pipelines the 'pythonic way', or: poor man's HLS. It then took a little swing of additional experiments to emulate MyHDL while allowing to carry along VHDL and Verilog legacy. Now it's at a stage where it's safe to play with it.The novel part: a dual execution context, basically meaning, that the same code notation is executed as native Python or transpiled to another representation (modular HDL, RTL). This opens up a new field of verification methods, which turned out efficient for modelling of complex algorithms. This might also answer some of question marks raised in this threadhttps://www.eevblog.com/forum/fpga/vunit-uvvm-osvvm-what-are-similarities-and-differences/The howto/examples repo with Jupyter notebooks:https://github.com/hackfin/cyrite.howtoHitting the Binder button will launch a Jupyter Lab 'IDE' in your browser after a while. Behind it is the mentioned Docker container which you can also run at home.Teasers:- Procedural stuff: CRC, SoC register map decoders- Pipelined vector operations- ..and verification of the above by Co-Simulation via CXXRTL (fast!) or generation of HDL testbenches- yosys, iverilog, ghdl includedPrimarely released for free, educational use (industrial FPGA targets are mostly not referred to), I'd of course love to hear about it if someone comes up with an interesting verification method. And about bugs, irregularities you might come across, too.
Open Source Verilog Package Manager - Page 1
Forum section: electronics / general

author: spec_superior
author_rank: Newbie
timestamp: August 08, 2024, 10:22:13 am
content: I'm a Stanford student who previously designed ASICs at a startup and also dabbled in FPGAs.I built a Verilog Package Manager to address some issues with IP re-use. It's basically the equivalent of pip install, because installing a top-level module automatically installs submodules, handles synthesis collateral, generates .vh headers, etc.Within 2 days of launch it received interest and feature requests from Neuralink and Samba Nova engineers. I'm trying to make this big but practical.Repo link:https://github.com/getinstachip/vpmI'd appreciate any comments or complaints on this. I'll fix each issue with a few hours. Looking for genuinely candid feedback and potential contributors. I'll answer any questions you have below too. I'll add people who are interested to a Discord server.

author: zapta
author_rank: Super Contributor
timestamp: August 09, 2024, 05:46:41 am
content: Have you considered to support a central repository similar to PyPi.org?
Do you find Efinix development tricky? - Page 1
Forum section: electronics / general

author: Boscoe
author_rank: Frequent Contributor
timestamp: July 21, 2024, 10:20:09 am
content: Hi all,I'm currently developing my second project with Efinix parts, the first project was low speed logic that really wasn't very complicated. This project involves a MIPI CSI2 RX interface, some image manipulation and output using an FT2232H. I'm finding the development of this a little tedious at the moment. All my previous experience has been with Altera and Xilinx parts with varying levels of difficulty however my tried and tested process has been to 'unit' test my blocks with behavioural simulation then synthesis and get post placement timing. If this all passes, I generally never have problems when the FPGA gets configured. I have quite a good amount of experience writing sensible Verilog now so can generally get this done within a few attempts when I break the modules down small enough. One example would be a bit and word aligner for a 16 channel LVDS image sensor interface with each channel running at 200MHz DDR.Now, with the Efinix Trion this method is really not working for me! I'm getting some quite peculiar results and very agressive optimisation making basic FPGA level verification such as USB transfer a pain in the ass to complete. It even seems to like to ignore `(* syn_keep = "true" *)` attributes!Even developing a very simple 32bit SPI interface to get some running status from the FPGA into my adjacent ESP32 took 3 weeks to get working! Something I expected and have done in an afternoon before.Has anyone else had this experience with these tools / parts?

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 21, 2024, 09:01:11 pm
content: Boscoe, do you have a good FAE ? I have found the factory is VERY responsive to synthesis / P&R issues. They want stuff fixed - I have encountered a few problems and they were stomped on quickly. Their design is out of california, and support and mfr out of Singapore (my time zone)I work through my distributer (Braemac) (I bought a few trays of Ti60-F225 ) .I have not used the older Trion. I have not had meeting IO timing difficulties in recent times on 400 MHz external DDR interfaces.Let me know how you go, if you get stuck I can take this up with the factory directly, but please do work through your distributor / FAE first.
Advanced VHDL series from scratch - Page 1
Forum section: electronics / general

author: tugbanurakgun05@gmail.com
author_rank: Newbie
timestamp: July 14, 2024, 06:29:00 pm
content: Hello friends. I started a series teaching VHDL, starting from scratch. I graduated from University this year. I may make mistakes. I'm new to this field. I'm open to your ideas. Please feel free to correct my mistakes.
TinyTapeout - Page 1
Forum section: electronics / general

author: karpouzi9
author_rank: Contributor
timestamp: September 06, 2023, 09:48:58 pm
content: It's fun!

author: Infraviolet
author_rank: Super Contributor
timestamp: September 06, 2023, 11:24:12 pm
content: I had heard of the TinyTapeout project before, but I think it only worked for purely digital input and outputs? The idea of having a custom chip design made would surely attract a lot more people if it could include analog functionalities.

author: julian1
author_rank: Frequent Contributor
timestamp: September 06, 2023, 11:39:49 pm
content: https://tinytapeout.com/hdl/important/It uses Yosys? with some custom modules/libraries?

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 07, 2023, 12:16:37 am
content: Quote from: Infraviolet on September 06, 2023, 11:24:12 pmPure digital ASICs would certainly attract many people.The problem is more with the specs they offer. They do not support gate-level synthesis, but tile-based, a bit like FPGAs, with pretty severe limitations:https://tinytapeout.com/faq/#chip-specs-for-tt01-tt02--tt0312.5kHz (!) max freq for their past shuttles, and for the coming one, they say about 50MHz. Much better, but still pretty low for the kind of stuff you'd typically want an ASIC.That's cheap though. Also, I haven't seen the exact terms regarding IP, but since they are using the Skywater PDK, I guess the same licensing applies, so your designs must be fully open-source? To be confirmed though.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: September 08, 2023, 08:21:46 am
content: Nice option

author: c64
author_rank: Frequent Contributor
timestamp: July 11, 2024, 07:58:10 am
content: Specs are much better now.I can not find any information about cost. There is price for small initial batch, and then what?
Protecting against bus contention in prototype - Page 1
Forum section: electronics / general

author: ivan747
author_rank: Super Contributor
timestamp: June 30, 2024, 04:27:01 pm
content: Hi everyone,I want to embark on a project that wil conenct an FPGA to a device parallel bidirectional bus. The bus is not clearly documented, so I am not 100% sure when the device will output data on the bus. I want to protect both the FPGA dev board and the device because they cost some money.I think resistors in series on every line is a good solution, but I don't know what value should I choose. The bus is 3.3V and its clock runs at up to 17MHz. Single data rate. I will have a ribbon cable (at least 20cm for ergonomics). So signal integrity is a factor, I think.If I go with a value that limits the current below the FPGA's rating, say 3.3mA, the resistance is 1kohm. Empirically I think that's too high of an impedance considering the ribbon cable. If I go with something like 100ohm, empirically I think it can drive the ribbon cable but I don't know if the FPGA can survive that.Is there a magical solution?

author: ataradov
author_rank: Super Contributor
timestamp: June 30, 2024, 06:49:11 pm
content: Use bus transceiver ICs between the devices. Consider them to be disposable, but generally they are more robust and 100 Ohm current limiting is sufficient.

author: xvr
author_rank: Frequent Contributor
timestamp: June 30, 2024, 07:57:33 pm
content: Get the minimum of maximum load current of FPGA output and maximul load current of target device. Then divide logic high voltage to this current. You will get resistors value.Example: 20mA of max current, 3.3V of logic 1 give 165R

author: BrianHG
author_rank: Super Contributor
timestamp: July 01, 2024, 12:10:30 am
content: I use 74xx245 on my PCB, with optional resistor packs beneath the 245 buffers so I may use either / or just by mounting the 245 or 2x 4sip parallel resistor packs since the 8 bit bus comes in and out in parallel on each side of the 245.
Lattice Avant E - Page 1
Forum section: electronics / general

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 09, 2024, 09:10:24 pm
content: Anyone got their hands on any new Avant E silicon yetDatasheets currently have lots of white space, but ES parts have made it onto DK. It looks like a useful family, like Agilex 5, broad range of agreeable features, nicely fractuable math block, serdes... decent speeds....

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 09, 2024, 09:15:35 pm
content: Nope. But this series will require a subscription for Radiant. (You'll probably get a limited license if you buy a dev board, which is Lattice's usual scheme.)

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 09, 2024, 09:34:09 pm
content: it has been indicated to me that they'll just give you the software forever if you buy a dev board, which is what most people would do if they're going to design with a > USD100 FPGA.....(my territory, mostly)The factory rep also indicated to me 'the tools have been improved, significantly'. we'll see.This probably relates to that Lattice is going into a world of 200k-600k LUT FPGAs which basic P&R tools will no longer cut it.Dev boards with serdes ports on them available soon....

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 09, 2024, 10:29:12 pm
content: Quote from: glenenglish on July 09, 2024, 09:34:09 pmYes, that's what I mentioned. The "forever", I was not sure about. But, even so, by "limited", it's my memory that the license they grant you with a dev board is valid only for the exact FPGA model that is on it, and no other in the same series. At least that's what it used to be with Versa boards. But you can check that with a rep.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 09, 2024, 10:41:41 pm
content: You find that, in general, FPGA mfrs just put up lightwight roadblocks . They dont seriously stop people from using their fpgas for the sake of some software cost or license if push comes to shove.although they say so in their literature, sure. With a good relationship with the FAE, most things are possibe. THis is different of course to buying your fpgas from digikey, you are on your own.
Where to get the system reset signal on an ICE40UP5K ? - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: June 26, 2024, 04:04:32 am
content: I am using the Upduino 3.1 ICE40UP5K-SG48ITR (PDF schematic below) with the open source tool chain (apio/yosys) and verilog. All the modules have a synchronous sys_reset input to initialize them on startup. Does the FPGA or tool chain already have a built in reset signal I can use? If not, how should I about designing my own?Currently I am using a simple timer that seems to work but would like to add a PLL and am not sure if I need to wait as well, so wonder if there is an out of the box solution or best practice.Code:`default_nettype nonemodule reset_gen (input sys_clk,output reg sys_reset);// Relying on ICE40 behavior of reseting all DFF on power on reset.reg [3:0] counter = 0;always @(posedge sys_clk) beginif (counter < 10) beginsys_reset <= 1;counter <= counter + 1;end else beginsys_reset <= 0;endendendmodule
How to simulate/testbench with IceStudio? - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: February 13, 2024, 02:51:00 am
content: I am considering using IceStudio with a ColorLight-i9-v7.2_(FT2232H) board. Does it include simulation/testing capabilities, that is, testing individual blocks, with or without a board, injecting input vectors and examining the waveforms?It does have related export capabilities (picture below) but I couldn't figure out what to do with them.Alternatively, is there a clearly better free tool that you would recommend? I like the fact that IceStudio is open source and runs also on Mac OS.

author: zapta
author_rank: Super Contributor
timestamp: June 21, 2024, 10:24:42 pm
content: A quick update, since then I switched from IceStudio to apio and all my simulation and automatic testing requirements are satisfied.These two open source products are from the same group and support the same set of boards and FPGA, where apio text based (similar concept to Platformio) while IceStudio is a GUI abstraction that uses apio.

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: June 30, 2024, 06:15:44 pm
content: I recently did a project in SystemVerilog. Very easy to shoot oneself in the foot since the language is not strict about types like VHDL.
Best tool to read Lattice LCMXO2-256HC-4SG32C - Page 1
Forum section: electronics / general

author: tbegal
author_rank: Newbie
timestamp: June 12, 2024, 12:05:01 pm
content: Could someone guide me to best affordable tool to clone Lattice FPGA LCMXO2-256HC-4SG32CNeed a read from working board the configure to new replacement

author: ataradov
author_rank: Super Contributor
timestamp: June 12, 2024, 01:46:15 pm
content: Lattice Diamond + any Lattice programmer from Aliexpress. But this will only work if they have not set protection bits and did not disable the JTAG.