Max 7000 vs ATF1508 Issue - Page 1
Forum section: electronics / general

author: jbaum81
author_rank: Newbie
timestamp: October 16, 2022, 04:27:55 pm
content: Hey all,Running into some sort of compatibility issue between a Max7000 and an ATF1508. The below listed code works perfectly on an ATF1508, however on a Max7000 I get occasional dyssynchronization between the clk8sys and clk8via signals on power up. These should normally be synchronized at 8mhz, but the clk8sys will stretch out to a 4mhz period when accessing the Yamaha 2151 sound chip. I always have stability with the ATF1508, and have stability with the Max7000 if the clocks start up synchronized.For context this the glue logic for my Commander X16 compatible computer.Any help would be appreciated, Thanks!!Code:module JB6502ATF1508PLCC(input clk,output sysClk,output viaClk,input oe,input rw,input rst,input [7:0] adrBusLo,input [7:0] adrBusHi,input [7:0] datBus,output [7:0] adrBanks,output oeLow,output clkWr,inout datDD,output raEn,output ioEn,output v0En,output v1En,output srlEn,output hr0En,output hr1En,output hr2En,output hr3En,output roEn,output ymfEn,output activity);reg [7:0] ramBank = 0;reg [7:0] romBank = 0;reg clk8sys = 0;reg clk8via = 0;reg stretch = 0;reg [1:0] stretchCnt = 0;initial beginramBank=8'h00;romBank=8'h00;clk8sys = 0;clk8via = 0;stretch = 0;stretchCnt = 0;endassign sysClk = clk8sys;assign viaClk = clk8via;assign oeLow = (oe) ? ~rw : 1'bz;assign clkWr = (oe) ? ~(~rw && sysClk) : 1'bz;assign datDD = (rw && clk8sys && adrBusHi == 8'h9f && v0En && v1En) ? 1'b0 : 1'bz;wire [7:0] _adrBanks = (adrBusHi[7:5] == 3'b101) ? ramBank : ((adrBusHi[7:6] == 2'b11) ? romBank : 8'h00);assign adrBanks = (oe) ? _adrBanks : 8'bzzzzzzzz;assign roEn = (oe) ? ~(adrBusHi[7:6] == 2'b11) : 1'bz;assign hr0En = (oe) ? ~(adrBusHi[7:5] == 3'b101 && ramBank[7:6] == 2'b00) : 1'bz;assign hr1En = (oe) ? ~(adrBusHi[7:5] == 3'b101 && ramBank[7:6] == 2'b01) : 1'bz;assign hr2En = (oe) ? ~(adrBusHi[7:5] == 3'b101 && ramBank[7:6] == 2'b10) : 1'bz;assign hr3En = (oe) ? ~(adrBusHi[7:5] == 3'b101 && ramBank[7:6] == 2'b11) : 1'bz;assign ioEn = (oe) ? ~(adrBusHi == 8'h9f && clk8sys) : 1'bz;assign v0En = (oe) ? ~(adrBusHi == 8'h9f && adrBusLo[7:4] == 4'b0000) : 1'bz;assign v1En = (oe) ? ~(adrBusHi == 8'h9f && adrBusLo[7:4] == 4'b0001) : 1'bz;assign srlEn = (oe) ? ~(adrBusHi == 8'h9f && adrBusLo[7:4] == 4'b0110 && clk8sys) : 1'bz;assign ymfEn = (oe) ? ~(adrBusHi == 8'h9f && adrBusLo[7:1] == 7'b0100000) : 1'bz;assign activity = ({adrBusHi,adrBusLo} == 16'h9f3e || {adrBusHi,adrBusLo} == 16'h9f3f) ? 1'b0 : 1'b1;assign raEn = (oe) ? ~(roEn && hr0En && hr1En && hr2En && hr3En && ioEn && clk8sys) : 1'bz;//Ram/Rom Bankingalways @(negedge sysClk) beginif (~rst) beginramBank <= 0;endelse beginif ({adrBusHi,adrBusLo} == 16'h0000 && ~rw)ramBank <= datBus;endendalways @(negedge sysClk) beginif (~rst) beginromBank <= 0;endelse beginif ({adrBusHi,adrBusLo} == 16'h0001 && ~rw) beginromBank <= datBus;endendend//Clocking and Stretchingalways @(posedge clk) beginclk8via <= !clk8via;stretchCnt <= stretchCnt+1;if (stretch && stretchCnt == 2'b11) beginif(clk8sys) beginclk8sys <= 0;endelse beginclk8sys <= 1;stretch <= 0;endend else if(!stretch) beginclk8sys <= !clk8sys;if(!clk8sys && adrBusHi == 8'h9f && adrBusLo[7:1] == 7'b0100000) beginstretch <= 1;stretchCnt <=0;endendendendmodule

author: TomS_
author_rank: Frequent Contributor
timestamp: October 18, 2022, 06:53:07 am
content: Can you show some waveforms of the clock signals, good and bad?

author: ale500
author_rank: Frequent Contributor
timestamp: October 18, 2022, 09:05:05 am
content: Counts down to 4 MHz ? no, it counts 4 clocks per half-period, i.e. to 2 MHz. Did you simulate it ?BTW, that is a very neat looking board (did you see the "community x16" ?, it only shows in the latest video). That Artix part is a total overkill compared to the ICE5UP of the original Vera, but it needs 128 k Block RAM...

author: jbaum81
author_rank: Newbie
timestamp: October 19, 2022, 07:48:38 am
content: Actually you are right, I was doing some trouble shooting with the YM2151 and forgot I left the stretch slowed to 2mhz, but that's not the problem.I have the scope put away right now so wave forms are not available, but they are really not that interesting. 2 8mhz clocks, WHEN the Max 7k powers up with both sync'd I have 100% stability, when they fire up out of phase I can't access the VIA's. The ATF1508's (6 now tested) always power up in sync and always stable.In regards to my board and the Artix 7, Thank you. And yes it's way way overkill compared to the ICE40, but that socket (and the expansion slots) give full access to the entire system bus, cpu and cpld control signals. So technically I can run any softcore with an 8 bit databus and up to a 24bit address bus. Soooo much room for activities. I actually have a Vera running a ICE40 that goes into that socket as well. The only tradeoff running the Mercury II is that it only has a 10 bit DAC, whereas the one on the ICE40 based Vera runs a 24bit DAC, of which only 16 bits are used, so I'm just dividing down and my ears can't tell the difference.

author: ale500
author_rank: Frequent Contributor
timestamp: October 19, 2022, 10:44:50 am
content: Like the FFs are not properly initialized ?, if stretch is 1 after power up then they get 180 ° out of phase, do you mean that ? or 90 ° ?.In the "Analysis and synthesis" options pane, do you have "Power up don't care" ticked or not ?"What I'd suggest is to consider the reset in the equation of stretch. <- now that I think more about this, it will bring nothing.Either that of re-resetting stretch to 0, unticking "Power up don't care" may help too if set.

author: jbaum81
author_rank: Newbie
timestamp: October 21, 2022, 08:43:16 am
content: Power up don't care didn't help, in fact it caused the system to hang on boot at about the same frequency the clock went out of sync.I was experimenting with some power up delays before I start running the clocks and went ahead and continually zero'd the registers for the stretch and both clocks during that period and it seems to have done the trick. Anyhow below is the complete code that's now running stable on the Max7k, I'll need to test it on the 1508's next, but they worked before so I doubt this would have upset them any.Code:module JB6502ATF1508PLCC(input clk,output sysClk,output viaClk,input oe,input rw,input rst,input [7:0] adrBusLo,input [7:0] adrBusHi,input [7:0] datBus,output [7:0] adrBanks,output oeLow,output clkWr,inout datDD,output raEn,output ioEn,output v0En,output v1En,output srlEn,output hr0En,output hr1En,output hr2En,output hr3En,output roEn,output ymfEn,output activity);reg [7:0] ramBank = 0;reg [7:0] romBank = 0;reg clk8sys = 0;reg clk8via = 0;reg stretch = 0;reg [1:0] stretchCnt = 0;reg [15:0] porCnt = 0;reg runClk = 0;initial beginramBank=8'h00;romBank=8'h00;clk8sys = 0;clk8via = 0;stretch = 0;stretchCnt = 0;porCnt = 0;runClk = 0;endalways @(posedge clk) beginif (!runClk) porCnt <= porCnt +1;if (porCnt == 16'hffff) runClk <= 1;endassign sysClk = clk8sys;assign viaClk = clk8via;assign oeLow = (oe) ? ~rw : 1'bz;assign clkWr = (oe) ? ~(~rw && sysClk) : 1'bz;assign datDD = (rw && clk8sys && adrBusHi == 8'h9f && v0En && v1En) ? 1'b0 : 1'bz;wire [7:0] _adrBanks = (adrBusHi[7:5] == 3'b101) ? ramBank : ((adrBusHi[7:6] == 2'b11) ? romBank : 8'h00);assign adrBanks = (oe) ? _adrBanks : 8'bzzzzzzzz;assign roEn = (oe) ? ~(adrBusHi[7:6] == 2'b11) : 1'bz;assign hr0En = (oe) ? ~(adrBusHi[7:5] == 3'b101 && ramBank[7:6] == 2'b00) : 1'bz;assign hr1En = (oe) ? ~(adrBusHi[7:5] == 3'b101 && ramBank[7:6] == 2'b01) : 1'bz;assign hr2En = (oe) ? ~(adrBusHi[7:5] == 3'b101 && ramBank[7:6] == 2'b10) : 1'bz;assign hr3En = (oe) ? ~(adrBusHi[7:5] == 3'b101 && ramBank[7:6] == 2'b11) : 1'bz;assign ioEn = (oe) ? ~(adrBusHi == 8'h9f && clk8sys) : 1'bz;assign v0En = (oe) ? ~(adrBusHi == 8'h9f && adrBusLo[7:4] == 4'b0000) : 1'bz;assign v1En = (oe) ? ~(adrBusHi == 8'h9f && adrBusLo[7:4] == 4'b0001) : 1'bz;assign srlEn = (oe) ? ~(adrBusHi == 8'h9f && adrBusLo[7:4] == 4'b0110 && clk8sys) : 1'bz;assign ymfEn = (oe) ? ~(adrBusHi == 8'h9f && adrBusLo[7:1] == 7'b0100000) : 1'bz;assign activity = ({adrBusHi,adrBusLo} == 16'h9f3e || {adrBusHi,adrBusLo} == 16'h9f3f) ? 1'b0 : 1'b1;assign raEn = (oe) ? ~(roEn && hr0En && hr1En && hr2En && hr3En && ioEn && clk8sys) : 1'bz;//Ram/Rom Bankingalways @(negedge sysClk) beginif (~rst) beginramBank <= 0;endelse beginif ({adrBusHi,adrBusLo} == 16'h0000 && ~rw)ramBank <= datBus;endendalways @(negedge sysClk) beginif (~rst) beginromBank <= 0;endelse beginif ({adrBusHi,adrBusLo} == 16'h0001 && ~rw) beginromBank <= datBus;endendend//Clocking and Stretchingalways @(posedge clk) beginif (runClk) beginclk8via <= !clk8via;stretchCnt <= stretchCnt+1;if (stretch && stretchCnt == 2'b11) beginif(clk8sys) beginclk8sys <= 0;endelse beginclk8sys <= 1;stretch <= 0;endend else if(!stretch) beginclk8sys <= !clk8sys;if(!clk8sys && adrBusHi == 8'h9f && adrBusLo[7:1] == 7'b0100000) beginstretch <= 1;stretchCnt <=0;endendend else beginclk8via <= 0;clk8sys <= 0;stretch <= 0;endendendmodule

author: ale500
author_rank: Frequent Contributor
timestamp: October 22, 2022, 08:36:06 am
content: It is still not clear what is exactly happening at startup. Stretch is either powering up set, for instance when "Power up don't care" is set (means that the power up of the MAX7000's registers do not set or reset the FFs), or getting set because the address is 9f00. Maybe the MAX 700 is very fast at powering up in contrast to the ATF which seems to consistently initialize its FFs with 0. Speculation.Another question why you do not use the reset to keep stretch negated and then from that one you generate a system reset for the CPU, VIA and so on ?. Due to these problems seems like a sensible solution, board reroute may be necessary, or some bodge wires.

author: jbaum81
author_rank: Newbie
timestamp: October 22, 2022, 03:21:50 pm
content: The System reset line is there I could technically try a few things with that as well. What's worth noting is using an 8 bit counter for the power up sequence didn't work, I ended up settling in on a 16bit counter. So with what I did do 256 clock cycles wasn't enough to get it right, I had to run a full 16 bits for the counter.