Using Logic level FETs unecessarily in synchronous Buck? - Page 1
Forum section: electronics / general

author: Faringdon
author_rank: Super Contributor
timestamp: April 10, 2024, 05:39:40 am
content: Hi, do you know why the LM5143 (Synch Buck controller) was used for this Synch Buck spec (PMP31210 ref design)of 20-58vin and 13.5Vout and 50A out?...PMP31210 Ref Design:https://www.ti.com/tool/PMP31210Surely they should have just used the same_priced LM5119 instead?The LM5143 has a max gate drive voltage of just 4.5V, meaning they are restricted to logic level FETs and their Rds(on)is much higher at the 80V rating needed.The LM5119 has a gate drive voltage up to 15V...meaning far lower Rds(on) FETs are available , and so FETs would be much cheaper.Unfortunately we dont have an official company address, and so cant ask on the ti.com forum.You would think they would advertise products in their suitable useage case, rather than in a totally unsuitable case?I mean, 58Vin Synch Buck, with 700W output, and they are using a gate drive of 4.5VWhen they could have gone with 12V gate drive forsame price solution.Maybe the SMPS is operated in sub zero temperature buildings and the extra heat dissipation is useful? -only plausible explanation.PMP31210 Ref Design:https://www.ti.com/tool/PMP31210LM5143:https://www.ti.com/product/LM5143LM5119:https://www.ti.com/product/LM5119*********************************************As you know, the only real reason to use logic level FETs in any SMPS is that your Vin is below say 7V, and you dont want to bother with a bias booster so you just put up with logic level FETs. As you know, people are not using logic level FETs because of any advantage of them. They have no advantages over "normal" threshold FETs. Especially in a synchronous buck, logic level FETs are a poor choice, because with their low gate threshold voltage, they may get spuriously turned ON by the other FET turning ON and pulsing a current spike through the drain gate capacitance. Hot logic level FETs have a ridiculously low VGS(th)......as you know, they are a very poor choice, and one that you "put up with".Not least is the fact that if you choose a logic level gate driver, then you are restricted to only logic level FETs...so you likely end up paying more for your FETs, and being more susceptible to FET nil-stocking.Also, how does a logic level hi side gate driver supply (bootstrapped) in a synch buck chip ever do "UVLO" of the driver?...as you know...it cant really do it......when VGSth is that low you cant really do it....if you have a 12V gate driver, then you can have it "UVLO out" at say 7V.Logic-level devices, also, have higher gate charge than standard-level parts of similar V(BR)DSS and RDS(on)

author: David Aurora
author_rank: Frequent Contributor
timestamp: April 10, 2024, 12:24:50 pm
content: Quote from: Faringdon on April 10, 2024, 05:39:40 amYes but we can't tell you, it's a secret.

author: jc101
author_rank: Frequent Contributor
timestamp: April 10, 2024, 04:26:09 pm
content: Quote from: Faringdon on April 10, 2024, 05:39:40 amWhat? Absolute rubbish. If you are a company you have a registered address, it is a legal requirement. Use that.Anyway, registering simply requires a postcode. Assuming you aren't a company just use, for example, WC2B 6NH, which is a bookable We Work space—perfectly justifiable to use. If they want the full address, it's Aviation House, 125 Kingsway London, WC2B 6NH.Just go and ask TI, please.

author: tggzzz
author_rank: Super Contributor
timestamp: April 11, 2024, 09:52:20 am
content: Quote from: jc101 on April 10, 2024, 04:26:09 pmMight it be that the only company "they" have is himself? Sad possibility.

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 11, 2024, 11:20:39 am
content: Quote from: Faringdon on April 10, 2024, 05:39:40 amYou misunderstand the purpose of these reference designs. It doesn't mean that TI thinks this is the best chip for the application. It just means the reference design is a good way for engineers to evaluate the chip for their application. They're trying to sell all their chips, and only putting their latest and greatest stuff in reference designs doesn't help that.Also the datasheet says the gate 5V, but can be up to 6.5V if you apply an external voltage with the VCCX pin. Still restricted in FET selection, but a big difference from 4.5V...Quote from: jc101 on April 10, 2024, 04:26:09 pmI believe he was referring to an email address/domain, not a street address. A few years ago TI decided to cull their own userbase by only allowing people with "company" email addresses create new threads.

author: Siwastaja
author_rank: Super Contributor
timestamp: April 11, 2024, 01:38:17 pm
content: As usual, Faringdon raises an excellent and relevant point and spam posters like jonpaul who never have anything constructive to say start trolling, trying to derail the thread. Reported to moderators.I always wondered what these IC designers are smoking. Maybe limiting one to 5V IC process brings some manufacturing savings, and that's viable for low-enough (<30V, maybe <40V max Vin) voltage designs, because if you look at typical Vds_max=30V MOSFET, it will conduct just fine with Vgs=4.0V, even if not advertised as "logic level" (which is quite arbitrary designation, anyway).But look at LM5143 and try to do worst-case analysis:Vcc UVLO minimum 3.2V.Subtract bootstrap diode Vf from that, say 0.4V for a schottky,High-side MOSFET now has Vgs = 2.8V. Does the high-side UVLO help? No, because,high-side UVLO = 2.4V.This chip actually will operate and drive the MOSFETs at Vgs=2.4V in the worst case and you need to design with that number! Even for a "typical" steady-state case under lab conditions, Vgs of high-side switch will be around 4.5V.Good luck trying to find MOSFETs with Vds=65V and low-enough Rds_on at Vgs=2.4V. Clearly the IC design is for MOSFETs rated to Vds_max=30V or so.I have seen parts where Vcc regulator is rated with tighter tolerances close to 6V, and UVLO closer to 5V than 3V, and this you apparently can still do with the same "5V IC process" (IC gurus might shed more light to this) getting the manufacturing cost benefits. No idea why TI doesn't do that.Now, not being Faringdon, maybe me raising the same points is acceptable: anyone has any further comments about the subject (not the OP)?

author: Siwastaja
author_rank: Super Contributor
timestamp: April 11, 2024, 01:47:27 pm
content: Quote from: mtwieg on April 11, 2024, 11:20:39 amThis won't help, because such switcher becomes a timebomb without the two UVLOs (one for Vcc, one for Vbst). In other words, you do the math for Vgs=6.5V and then find out that it actually runs at Vgs=2.5V in the field, during a power-up or power-down or some other edge condition. The MOSFET you qualified for 6.5V is probably in its worst linear range at Vgs=2.5V and power dissipation two orders of magnitude above expected. Destruction happens in tens of milliseconds.And adding those two UVLOs alongside with the external regulator becomes just ridiculous level of extra complexity; every bootstrapping half-bridge ICintegratesthe UVLOs for very good reasons. This part does too, but you can't adjust the voltage thresholds, and the factory settings are just too low. Therefore a reliable design requires redesigning half of the switcher IC around it using discretes, or accepting you have a design which just blows up in edge conditions.Or finding a sanely designed part, but that requires quite some care, looking at specs like UVLO worst case minimums, and comparing them to the MOSFET specifications, and looking at worst case current limit maximums and comparing these to your inductor saturation current... Design work ain't easy!

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 11, 2024, 02:39:48 pm
content: Overall I agree with your points regarding the UVLOs. Guessing a product manager insisted the part be capable of operating with very low Vin, without considering how that would affect higher power applications.In cases where the internal UVLO thresholds are too low for my liking, I'll implement my own UVLO on Vin. It's not exactly the same as an UVLO on the high/low side gate driver supplies, but unless you have external circuitry loading those supplies It's not necessary to directly monitor them, IMO.

author: Simon
author_rank: Unknown
timestamp: April 11, 2024, 05:29:31 pm
content: Quote from: Faringdon on April 10, 2024, 05:39:40 amHow do you know "I know"? the reason not to use logic level MOSFET that you don't know that I know is that as it turns on so easily it's difficult to turn it off. The gate drive voltage for fully on is the same as a normal MOSFET. A normal MOSFET is around 4V so with 10V on the gate it has 6V to overcome the miller plateau. When it is turned off there is less than 4V to overcome the miller plateau unless the driver sits on a negative rail. Now try using a MOSFET with 2V or less gate threshold and the asymmetry is even worse and turning it off takes even longer.Anything else that you know I know but that I don't know I know?

author: schmitt trigger
author_rank: Super Contributor
timestamp: April 11, 2024, 06:55:39 pm
content: This reminds me of Donald Rumsfeld’s "There are unknown unknowns" speech.Having said this…I believe that “do you know” is a common Faringdon’s figure of speech, similar to his use of “do you agree”.Instantly recognized.

author: Simon
author_rank: Unknown
timestamp: April 11, 2024, 08:12:33 pm
content: no it's "you know" this time.

author: Faringdon
author_rank: Super Contributor
timestamp: April 12, 2024, 05:27:28 pm
content: Thanks, also,does anyone know if there is a way to find NFETs for Synchronous Bucks?...How to search them?....As you know, a NFET for a Sync Buck must have Cgd at least 100 times less than Cgs. There is no way to search based on Cgd or Cgd/Cgs.We need them for 17-32VIN, 13V5 OUT, 30A out, and for 17-58Vin, 13v5 out and 50A out.Do 4V5 NFETs have more or less likelihood of having Cgs/Cgd >100? (as opposed to 10V drive fets)

author: Simon
author_rank: Unknown
timestamp: April 12, 2024, 06:40:21 pm
content: Quote from: Faringdon on April 12, 2024, 05:27:28 pmNo I didn't know that! what matters is the gate charge required to turn it on. There are also figures I believe for the charge required to get the gate to different voltages. Basically cheap means crap as always so that is one way to weed unsuitable ones out.in my experience the more current the MOSFET can carry the more gate charge, I can't remember how voltage tends to affect the specs. Basically I have noticed this trend which is common in life and engineering. If you multiply together all of the specs and the price you will probably end up with the the same number. in engineering we call this trade offs. If you want better characteristics in one respect you will either have to accept another characteristic not being as good or a substantial price increase.

author: temperance
author_rank: Super Contributor
timestamp: April 12, 2024, 11:47:21 pm
content: QuoteCan you clarify where you find that rule?

author: Faringdon
author_rank: Super Contributor
timestamp: April 13, 2024, 01:54:45 am
content: Thanks, i am trying to re-find the app note.But it makes sense as then less current coming through CGD and charging up CGS...as you know its a capacitive divider....so CGD will take much more of the voltage instead of CGS , which is wanted when the fet is off and itsCGS[...EDIT "VGS"] is required to be zero.

author: JPortici
author_rank: Super Contributor
timestamp: April 13, 2024, 06:01:05 am
content: Treez's word salads always make me raise my eyebrows.I wonder if the 65V is because they use the same process of some automotive parts? (Max voltage for LIN Transceivers...) (Edit: they DO have a -Q1 part..)Anywayi would agreethat mosfet selection with these constraints is hard but not impossible. Since infineon's logic level mosfets have become so expensive, and because i DO have a couple of applications that require logic level mosfets with more than 100V Vds (no driver as switching speed is not critical) in the past 5 years i've been using nexperia's PSMN series of mosfets for many tasks.Every couple of years the specific partnumber becomes either impossible to find or the price has increased to crazy expensive level, but at this point they have released other partnumbers in the series that might be even better (lower RDS on) sometimes they have mosfets that are conducting enough even with 3V3 at the gate, but that is more hit-and-miss.

author: Simon
author_rank: Unknown
timestamp: April 13, 2024, 08:55:24 am
content: Lower channel resistance also leads to higher capacitanceQuote from: Faringdon on April 13, 2024, 01:54:45 amNo, look for the gate charge spec. I don't pretend to be an expert but I suspect that a datasheet not giving the gate charge at a certain supply voltage may have something to hide.You can of course simply buy samples and test them, simply charge and discharge the gate and monitor the charge discharge time with a scope. If the capacitance of the scope probe is too high and affects the reading either do a dry run with just the probe. Another way is to test the very thing that the gate charge requirement affect, how hot does the MOSFET get.

author: Faringdon
author_rank: Super Contributor
timestamp: April 13, 2024, 03:37:00 pm
content: Thanks...So yes, indeed Cgd must be << Cgs. But as Simon kindly reminds, if the d(Vgd/dt) is high then Cgd appears to be higher since Cgd(apparent) = i.(d(Vgd)/dt). So yes, its not just Cgd that we must look at...but Qgd. And we must review Qgd at the actual Vin. The higher that the Buck's Vin is...the lower must be the ratio of Cgd/Cgs.In the attached sim we see how the ringed capacitor being lower reduces the spurious turn-on of the low side FET.And of course, tying in with the top post......Logic level FETs are much more susceptible to this spurious turn-on, simply because their Vgs(th) is so much lower. And when logic level FETs are used in Synch Bucks with Vin's > 30v, then things just get worse and worse.Basically if you are doing a Synch Buck with Vin > 30V, then you really want to be throwing logic level FETs into the Bin. They are way tosusceptible to spurious turn ON when the top side FET turns ON.But we simply dont see this said anywhere in App Notes...because the semico's want to flog their highly_invested_in Logic Level FETs.

author: Simon
author_rank: Unknown
timestamp: April 13, 2024, 04:00:04 pm
content: when the manufacturer has given you the gate charge at a certain drain voltage they have negated the need to look at the parasitic capacitances as those are for you to estimate the charge you need but as the manufacturer tells you the charge it's a more reliable spec than the capacitance.

author: temperance
author_rank: Super Contributor
timestamp: April 13, 2024, 04:11:16 pm
content: QuoteThat's all fine. But statements like "As you knowCgs must be 100 times Cgd" make no sense. There are a lot more parameters involved and app notes explaining this and other relevant matters concerning sync buck like structures in detail are available from almost every MOSFET manufacturer.Edit: An old but still relevant book on MOSFET can be found here:https://archive.org/details/bitsavers_siliconixdixMOSPOWERApplications_38092918An app note with a more detailed explanation about MOSFET self turn on:https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00074.pdf?did=59473

author: Faringdon
author_rank: Super Contributor
timestamp: April 13, 2024, 04:31:47 pm
content: QuoteThanks , yes, but what about the DMT8012LPS FET datasheet, which gives you Qgd at 40V...but supposing you are using it up to 58Vin? You cant do Q=CV because C varies with voltage in FETs.Also, incidentally, this FET datasheet gives Qgs at 40V, but Qgs is pretty constant no matter what is the Vin of the synch Buck.For "Qgs", the datasheet should give Vgs as the condition...but it does not.They give QGS=6nC which corresponds to VGS = 3.1V, but it would not be used with VGS that low.DMT8012LPShttps://www.diodes.com/assets/Datasheets/DMT8012LPS.pdfQuoteAnd a big thankyou to Temperance, because Temperance has provided an App Note which states exactly what was put forward in the top post...so you have kindly found the App Note that i had been seeking......the app note, on page 18 states....Selecting MOSFETs with a high Vth and a low Cgd is of primary importance....noting that they actually state "Cgd" rather than "Qgd".

author: Faringdon
author_rank: Super Contributor
timestamp: April 14, 2024, 12:23:34 pm
content: Its noteable that ti.com have two reference designs of synch bucks, which violate the "Qgd/Qgs < 1 rule".PMP10260 uses BUK7Y6R0-60EX for bottom FEThttps://www.ti.com/tool/PMP10260PMP20818 uses CSD18534Q5A as bottom FEThttps://www.ti.com/tool/PMP20818?keyMatch=PMP20818..Both of these use bottom FETs with Qgd/Qgs > 1BUK7Y6R0-60EXhttps://assets.nexperia.com/documents/data-sheet/BUK7Y6R0-60E.pdfCSD18534Q5Ahttps://www.ti.com/lit/ds/symlink/csd18534q5a.pdf?ts=1713045698403&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FCSD18534Q5A%253FkeyMatch%253DCSD18534Q5A

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 14, 2024, 03:45:26 pm
content: Quote from: Faringdon on April 13, 2024, 03:37:00 pmThis is absolutely not a requirement. AFAIK the majority of power MOSFETs do not satisfy this spec, but they end up working fine anyways (so long as your switching speed is under control). It's only recently that FETs with Qgd<Qgs have become available (mainly GaN FETs). Of course you can make any FET meet this spec by adding your own Cgs externally...Quote from: Faringdon on April 13, 2024, 04:31:47 pmThe charge ratio is what actually matters, not the capacitance ratio. The "rule" is based on the following worst-case scenario:1. Vgs and Vds are both initially zero (therefore zero charge everywhere)2. Vds instantaneously rises to some voltage VDS.3. This injects charge into the gate via Cgd. In this infinitely short time, the gate driver cannot absorb any of this charge.4. If the injected charge from the drain exceeds the part's rated Qgs, then the FET will turn on, leading to problems.The nonlinearity of the capacitances is irrelevant to the outcome in this situation (only the nonlinearity of Qgd vs VDS matters). That's why the "rule" is Qgd<Qgs, not in terms of capacitance.Quote from: Faringdon on April 13, 2024, 04:31:47 pmYes, most datasheets give plots of Coss/Crss vs Vds, but not Qoss/Qgd. In the past I've estimated Q by piecewise integration of the Coss/Crss curves.

author: Faringdon
author_rank: Super Contributor
timestamp: April 14, 2024, 04:33:34 pm
content: QuoteThanks, yes, this is sometimes the case, but as the below doc says, it doesnt always work...(pages 7 and 8 )https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00074.pdf?did=59473QuoteThanks, when you say this, are you referring to logic fets or "normal vgs(th)" fets?I suspect "Normal fets with "Qgd/Qgs > 1" will be OK...but logic fets not ok......a logic fet can have a VGS(th) of just 0.9V, and the spurious turn on is well possibleQuoteI believe that was a typo, (you put it correct at top of your kindly supplied post) as you know Qgs>Qgd is required.QuoteThanks, as you know, The "Qgd/Qgs < 1" spec is especially essential for synch buck fets which are logic level, and it would be great if digikey could incorporate "Qgd/Qgs" for its search engine.At the moment it takes ages to find and cost_compare logic level fets for synch buck useage.

author: Siwastaja
author_rank: Super Contributor
timestamp: April 15, 2024, 08:22:35 am
content: Quote from: Faringdon on April 14, 2024, 04:33:34 pmAs you can add Qgs externally, ratio is not important. What's more important is Qgd itself - the lower the better. And this is something suppliers do list, so just sort by Qgd.

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 15, 2024, 12:25:02 pm
content: Quote from: Faringdon on April 14, 2024, 04:33:34 pmThey bring up a good point that adding Cgs alone may cause more harm than good. If they also increase dead time then the added Cgs will have the intended effect.QuoteQgs is the charge required to bring Vgs from zero to Vth, so it inherently accounts for Vth.Quote from: Siwastaja on April 15, 2024, 08:22:35 amAgreed. Hypothetically, if a vendor offered a MOSFET with zero gate capacitance, then that wouldn't really make it worse, since you can always add capacitance yourself to increase Qgs. But one cannot reduce Qgd, so that's the parameter you should really be selecting.

author: Faringdon
author_rank: Super Contributor
timestamp: April 15, 2024, 05:35:09 pm
content: QuoteThanks, as you know, the majority of synch buck controllers offer no facility to vary the dead times. And usually, the dead time is horrendously small...usually 15 to 40ns, so indeed, adding the external Cgs capacitor would usually not be a good fix.Indeed, it is amazing that the dead times are made so ridiculously short...since most people will have a logic level "freewheel" fet in the synch buck...and they will implement its drive with a series "ON" resistor, and a diode'd "OFF" resistor.....but since a hot logic level fet can be fully enhanced with just 0.5v on its gate...the "diode turn off" circuit will not work very well...and so indeed, the lower "freewheel" fet is likely to be ON when the top fet turns on.......smoke or overheating resulting.......so the whole thing is a bit of a shambles.I bet that most synch bucks that are out there, with vin > 24V, would truthfully be more efficient if they simply threw away the lower "freewheeling fet" and put in a low voltage Schottky instead.Also, its noteable that Qgd/Qgs must be <1, though during spurious turn on in sync bucks, the lower FET actually has its gate shorted to ground by the driver, (and via any series resistance which would be low value)....so in fact, it makes you wonder why "Qgd/Qgs < 1" really applies in real life?Another point, is that if you are using Normal threshold (not logic level) fet drive, and have a PNP turn off snubber right on the fet gate, then its going to be virtually impossible to get the shoot-through condition due to Qgd/Qgs>1.However, this is not the case with logic level fets, since the PNP turn off wouldnt be of much use with the gate threshold being so low...the PNP woudlnt be able to turn on enough and in time.

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 17, 2024, 11:47:45 am
content: Quote from: Faringdon on April 15, 2024, 05:35:09 pmDeadtime can be adjusted with R/C/D components on the gates. In Toshiba's example, if they made the same changes to the top side FET's gate circuitry, and added turn-off diodes on both gate resistors, then that would likely eliminate cross conduction entirely. Even when Vth is <1V, the turn-off diodes still allow you to tune the dead time.

author: Faringdon
author_rank: Super Contributor
timestamp: April 17, 2024, 07:09:14 pm
content: Thanks, and as discussed, i am wondering if all this "Qgd/Qgs<1" thing is just a hoax...because when the lower FET is held off, the Cgs is shorted out by the gate driver.Its difficult to see how the lower FET gate can be brought up to the ON threshold when the driver is shorting it to ground?Perhaps the spurious on-coming is brought about by something else?...possibly v poor layout placing an stray inductance in the gate drive?Unless their is significant stray L in the gate drive loop, i just cant see how spurious ON turning of the lower FET can be caused by the "Qgd/Qgs<1" philosophy?

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 18, 2024, 04:29:44 am
content: Quote from: Faringdon on April 17, 2024, 07:09:14 pmIt's what one would call a sufficient, but not necessary, condition.QuoteThe Qgd<Qgs condition guarantees no turn-on even if the driver has very high impedance.Another example of a sufficient (but not necessary) condition is Vth/Rg>Cgd*d(Vds)/dt. This guarantees no turn-on even if Cgs and Qgs are zero. In a more realistic scenario, Qgs is nonzero and Rg is not infinite, so both these conditions can be relaxed. You could try unifying them into one rule, but it would be quite messy.