[Constraints 18-5210] No constraints selected for write. - Page 1
Forum section: electronics / general

author: Digitalio
author_rank: Contributor
timestamp: May 25, 2020, 04:02:43 pm
content: I'm getting this warning when running synthesis:Code:[Constraints 18-5210] No constraints selected for write.Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.My constraint file is marked as the target file, but the problem remains. Any ideas how to fix it?

author: rstofer
author_rank: Super Contributor
timestamp: May 26, 2020, 02:08:46 pm
content: Assuming Vivado...What do you have in the constraints tree of Project Manager?Here, I have LC3.xdc as the constraints fileI have attached LC3.xdc as an example.This constraints file came from Digilent and I am using quite a bit of IO for the project. Stuff I don't care about was deleted.

author: Digitalio
author_rank: Contributor
timestamp: May 26, 2020, 04:58:18 pm
content: Quote from: rstofer on May 26, 2020, 02:08:46 pmYes, it's Vivado 2019.2.1It seems that the contents of the constraints file doesn't matter at all, as I'm getting same message when opening the Wavegen example that came with Vivado.

author: SiliconWizard
author_rank: Super Contributor
timestamp: May 26, 2020, 05:01:53 pm
content: Not very keen on Vivado, and the error message doesn't look utterly helpful, but could it be that some of your files/directories are read-only?

author: rstofer
author_rank: Super Contributor
timestamp: May 26, 2020, 05:33:58 pm
content: Quote from: Digitalio link=topic=243275.msg3080644#msg3080644My constraint file is marked as the target file[/quote

author: Digitalio
author_rank: Contributor
timestamp: May 26, 2020, 06:05:04 pm
content: Apparently, it's a known bug in Vivado and they are going to fix it in 2020.1https://forums.xilinx.com/t5/Implementation/Vivado-warning-Constraints-18-5210-No-constraints-selected-for/m-p/1065023/highlight/true#M27192

author: rstofer
author_rank: Super Contributor
timestamp: May 26, 2020, 07:50:39 pm
content: And yet, not every user sees the error. A little later down in the thread they mention errors in the .xdc file causing Vivado to ignore the file.I have never seen the error but I use the Digilent .xdc files and remove stuff I don't need. I don't actually create an .xdc file from scratch.

author: rstofer
author_rank: Super Contributor
timestamp: May 26, 2020, 08:05:35 pm
content: Why not start a new project and follow the path from the document above? When you get to the .vhd file(s), you can copy in the ones you have from wherever they are or, better, start over with your PORT blocks matching the .xdc file. It's probably better to match a known good .xdc than to get overly creative.In the case of the Nexys 4 DDR board, the clock signal has the unfortunate name CLK100MHZ in the .xdc file. I can use that in my .vhd files or I can alias it to 'clk' after I bring it in through the PORT block or I can change the .xdc file to ClkIn which I did above.Code:[font=courier]## Clock signal#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];Just change the two lines substituting your clock name for CLK100MHzOf course, this is for the Nexys4 DDR, you may not be using that board.

author: Digitalio
author_rank: Contributor
timestamp: May 26, 2020, 09:07:02 pm
content: Quote from: rstofer on May 26, 2020, 07:50:39 pmI'm getting this error even in example projects supplied by Xilinx.

author: Digitalio
author_rank: Contributor
timestamp: May 27, 2020, 01:26:39 am
content: Quote from: rstofer on May 26, 2020, 08:05:35 pmI already did that. Apparently, this message is only a warning. At least, the code works properly on the physical device.

author: rstofer
author_rank: Super Contributor
timestamp: May 27, 2020, 02:39:02 am
content: I'm still at version 2019.2 I guess I won't upgrade!