Help analyzing Logic-functions of ISA-card - Page 1
Forum section: electronics / beginners

author: L.R Johansson
author_rank: Contributor
timestamp: February 11, 2020, 10:07:09 am
content: Hey everyone.I've got a problem that requires some input from more experienced people in order to guide me to the solution.Background:I've got a temp-job with a tech-company that does scientific testing.I got the job through an internship, by pitching an idea on how to update/replace an ageing industrial analysis platform,using emulators and a custom computer-build.If I pull it off, there's a good possibility my internship will turn into a full-fledged job.The job: Gamma-spectrometer Measuring SystemReplace the ageing legacy-platform while maintaining use of current software systems and sensor-equipment as much as possible, to keep costs down. The resulting solution will only be used for in-house production.Problem:The computer uses a custom I/O-card to communicate with the test-equipment, and the accompanying DoS-based software.The documentation is very limited, and the company that sold the equipment has become a competitor - so, according to company policy, we cannot under any circumstance contact them, to get info on the system.The equipment is about 25 years old, and the people that were around for the installation have retired, AND since everything is still in vital use, I cannot disturb the equipment to any significant degree – I can’t disassemble the PC and remove the card, or dig around much in the OS/Software, for risk of endangering production.I also cannot simply give up, and suggest they replace everything – because current systems come all-in-one, a single unit that gives you measurements, et c. No need for proprietary cards or even a connected PC, and it would be delivered by an external company – i.e, that would mean NO JOB for me.What I need help with:Reverse-Engineering / Analyzing the logic-functions and signal-standards of this ISA-card(with nothing but photos of the card, and what little other information is available. I have started reverse-engineering of the card, but as I decided to do so within Altium Designer, progress has been slow, since the program is an absolute pain-in-the-ass to work with.)Comparing the functions with a suitable modern replacement-card - obviously, since we're dealing with ISA, the signal-levels will be 5V, so I've tried to take that into account - the chip on my replacement test-card is 5V tolerant. But is it enough if the chip can take 5V? Is it logical to assume the other components have been specced for this energy-level?Speculation:Since most of the implementation utilizes standard logic, would it be possible to replace the PCXT-card with any sort of configurable GPIO 8255-card, as long as it can be adressed in the same ranges?Would it be plausible to utilize a third-party driver to grant direct access for an Emulator (running the Legacy-software) to initialize the replacement-card?I.e, we would be utilizing a process similar to VMware's LPT-passthrough.Any and all help greatly appreciated. = )Cheers!System makeup:Unit 1NaI-crystalPhotoMultiplierResistor-arrayHigh-voltage SourceUnit 2OP-amp10-bit ADCDb-25 cableUnit 3PC/XT I/O cardPC internal busMeasuring-programNotes:10-bit ADC, with 1024 channels. The OP-amp and ADC are in Eurocard form-factor.System-overview from manual:-- PC specifications --Hardware:BIOS: Award v. 4.50PGOS: Win95 4.00.950C (IE 5 5.00.2314.1003)MB: Asustek P/I-P55T2P4 rev 2.1CPU: P1 133 mhzRAM: 64 mb EdoSCSI: Cristie Parallel Port controller (n/a?)COM1: In use - 9600 bit/s, FIFO-buffer, adr: 3F8 - 3FF, irq: 4COM2: In use - 9600 bit/s, 2F8 - 2FF , irq 3LPT1: In use - adr: 38C - 38E, irq 7LPT2: (n/a?) 378 - 37F, irq (n/a)LPT3: (n/a?) 278 - 27F, irq (n/a)FDD: sony mpf520-1, 3,5 tum 1.44mbCD: Creative 24xfde (CD2422E)HDD: Conner CFS1275A, ideKBM: Microsoft mouse (intellipoint software?)PER1: Gameport JoystickPER2: MPU-401, adr: 330 - 331, irq: 9SC: Aztech Sound Galaxy Washington 16 (n/a?)NIC: smc Ethernet 8416bt (i/o 240, irq 11) isaPSU: Mapower PP-200T 210wSoftware:Screenshots:Bios Start-up sequence- Initialize PNPhttps://www.eevblog.com/forum/beginners/help-analyzing-logic-functions-of-isa-card/?action=dlattach;attach=926002- Update ESCDhttps://www.eevblog.com/forum/beginners/help-analyzing-logic-functions-of-isa-card/?action=dlattach;attach=926006Device manager- Portshttps://www.eevblog.com/forum/beginners/help-analyzing-logic-functions-of-isa-card/?action=dlattach;attach=926010Hardware:-ADC-19 different IC packages, more than 50 resistors, approximately 50 capacitors.Photos of ADC:https://imgur.com/gallery/lSV7pzWReverse-engineer of ADC:PCB-layoutADC-schematic-I/O-card-PC/XT bus (8-bit ISA)Designed 1987 – judging from the age of some of the program-files.Manufactured around 1995-96 – judging from the date-codes on some of the IC-packagesInstalled into production 1997.Mostly Philips and Toshiba IC's - at the heart sits an8255Cmos-Clone,running in MODE 0- general purpose I/O.Two-layer PCB, with traces on both sides - only the top layer is populated.Connects via a Db-25 port – using a standard LPT-cable. (the pin-out is unique however)Does not utilize TSR-drivers, for DoS or Win9x functionality – but is instead initialized directly via a Setup.exe and a Measure.exeThe PC/XT card can, via the jumpers, be set to communicate over theadress-range 300 h - 3FC h.Utilizes twoIRQ's: 5 and 2- one for the ADC, and one for Interrupt Latency. (possibly in order to make the CPU wait for the ADC)Photos of the card:https://imgur.com/gallery/OxxyL9uCard-illustration from Manual:Pin-out of DB-25 on the card:Mapping of ISA-connector:Active Components:1x Toshiba TMP82C55AP-2(CMOS Programmable Peripheral Interface – clone of intel i8255)1x Toshiba 74HC133AP(CMOS 13-input NAND gate)1x Philips 74HC245N(Octal bus transceiver; 3-state)1x Philips 74HC125N(Quad buffer/line driver; 3-state)1x Philips HEF 4013BP(Dual D-type flip-flops)2x Philips 74HC04N(hex-inverter)1x Harris (intersil) CD4572UBE(CMOS hex-gate, 4 INVerters, 1 NAND, 1 NOR)1x Texas Instruments SN74LS292N (34746YK)(Programmable Frequency Divider and Digital Timer)Nine packages in total.See datasheet-compilation:https://safenote.co/r/5e4288ec92ea53@42679961Reverse-Engineered Circuit-board layout:All layersTop layerBottom LayerLogic-diagram:

author: daqq
author_rank: Super Contributor
timestamp: February 11, 2020, 10:21:08 am
content: So, the PC is chewing the raw data from the ADC and acting as an MCA? Interesting setup, generally the MCA is a standalone device. But it could be done I guess for slow enough pulse rates.QuoteThe 8255 is an IO extender, nothing more. There is nothing else on the card that suggest any sort of intelligence on the card. The rest seems like address decoding logic.Note that it's not necessarily aparallel port IO card- they could have used a custom cable/pinout. In the dark age of computing this was fairly common. As such you may have a completely different pinout and logic, so you might not be able to use a generic parallel port converter.

author: johnkenyon
author_rank: Regular Contributor
timestamp: February 11, 2020, 10:41:52 am
content: My money is on the 8255 using mode 1 operation (strobed unidirectional i/o), or mode 2 operation (bidirectional).Either way, you need to figure out how the 8255 is wired to the connector (sounds like you have looked at this already), and find out how the 8255 is being setup and used.Unless you can tie the 8255 "driver software" as a discrete executable file, my gut feeling is that you need to use a logic analyser to see what is happening - once you have figured out which ports (if any) are being used for strobe operation, and have consulted the 8255 datasheet, it should be clear what needs to be monitored.

author: L.R Johansson
author_rank: Contributor
timestamp: February 11, 2020, 10:43:50 am
content: Quote from: daqq on February 11, 2020, 10:21:08 amCheers for having a look, friend.Actually, I measured both ends of the cable with a DMM, and it's a standard Db25 cable, everything is connected straight - Pin 1 to pin 1, pin 12 to pin 12, et c. So, the cable at least, is standard.As for the signal-protocol... that's the big 100$ question.EDIT:I've added a link with the datasheets to the components in the first post, which can also be seen here:See datasheet-compilation:https://safenote.co/r/5e4288ec92ea53@42679961

author: dexters_lab
author_rank: Unknown
timestamp: February 11, 2020, 11:16:42 am
content: Interesting project, i'll throw my thoughts in but they are generally following the opinions of the other folks posting...Yes that does look like a pretty standard parallel adaptor, quite common in the XT/AT era for interfacing into other stuff. If it's running on old hardware i'd be interested to know what other cards are in the system, like video and super-io cards if it's not integrated onto the motherboard.The interface card will be pretty simple affair to communicate with the ADC. You mention the ADC has a resolution of 1024 so you should find 10 parallel lines from the interface to the ADC. I'd be tempted to take the top of the ADC to see how complex it is and try and figure out if the PC software polls the ADC for data or if the ADC loads the value onto the interface and signals that there is data ready.My guess it's the latter, an incoming pulse from the detector is digitized to a 10 bit pulse height, the ADC loads the value onto the output and signals data is ready, the PC software reads the value and clears the state ready for the next pulse.A logic analyser is the way forward here, go through the connector on both ends, first find all the grounds then identify the 10 data lines, get them in the right order and then work on the remaining control/clock signals, seeing them on a logic analyser in sync with the data will be the best option.

author: daqq
author_rank: Super Contributor
timestamp: February 11, 2020, 12:12:45 pm
content: QuoteThe cable, yes, that might be a standard 1:1 connection, the question is about the actual pinout on the device - there's nothing stopping them from using a non-standard layout. As in it does not have to be an LPT compatible connection at all. Slapping a logic analyzer or taking at the very least a few more pictures of the guts is a must. At this point you simply do not have enough information to assume either way.

author: joeqsmith
author_rank: Super Contributor
timestamp: February 11, 2020, 01:06:48 pm
content: Quote from: L.R Johansson on February 11, 2020, 10:07:09 amThere may be a bigger lesson here than just electronics.Even if you had the old hardware design, you would need to design new hardware and write software for it and somehow test it without having a system. I'm a risk taker and would start working when everyone else goes home and live with the consequences. It may be a lot of unpaid overtime. You may damage their one and only working system, costing the company big $$$. They may never allow you to work there again. I like these odds...

author: up8051
author_rank: Frequent Contributor
timestamp: February 11, 2020, 01:18:08 pm
content: Why did you blur the markings on the card (upper-right corner)?Maybe they would help identify the card.

author: Cerebus
author_rank: Super Contributor
timestamp: February 11, 2020, 02:16:34 pm
content: Yup, figure out the pinout of the DB25 as best you can and slap a logic analyser on there and see what you get.I have a suspicion that the 'parallel port card' is a fully custom jobby - I don't ever recall seeing any pukka parallel port cards with SIL resistor packs by the connector like this has. Those look like termination resistors to me. But it's been a long time since I've seen a standalone LPT card so I may just be blowing smoke and perhaps the better ones included proper termination.The danger here is that, although you've got very standard parts there that were used to drum up all sorts of parallel interfaces in their day, this may not look anything like a standard LPT parallel port to the software. If it does look like a standard LPT card to the software then you're laughing, if it doesn't you've got a rather messy job on your hands fabricobbling something that's going to look right to the software and that physically interfaces with the ADC and whatever system you're going to run that software on.

author: L.R Johansson
author_rank: Contributor
timestamp: February 11, 2020, 02:28:15 pm
content: Quote from: johnkenyon on February 11, 2020, 10:41:52 amYeah, my money is on Mode 1 - strobed unidirectional. Mainly because, I just realized, that when the program is called, you don't actually tell it to start - you just tell it the scale to use, and for how long to measure - so, it's possible that the ADC never gets a GO-signal, but rather, it measures & sends signals continously, and the software then just filters the pulses.And it SHOULD be possible to tie it to a single .exe-file! : D The program is composed out of mainly two .exes (measure and setup), some bin-files and a few dat-files.Running the program "Strings" on it, one finds unicode-text that mentions the Microsoft Run-time Library 1992, and MSEM87 - I go with the assumption that this means it's written in Microsoft C, or Visual C or what-have-you, and it uses the libraries for DOS, versions 5.0 and 7.0. (released in '87 and '92 respectively)Quote from: dexters_lab on February 11, 2020, 11:16:42 amAh yes, the specs of the original system - that was my first thoughts as well - I've collected the information manually, since I'm not allowed to load ANY new software onto the computer, nor connect ANY new hardware. (a logic analyzer is likely to not be allowed... but I can always ask. Any suggestions on what type of unit?)BIOS: Award v. 4.50PGOS: Win95 4.00.950C (IE 5 5.00.2314.1003)MB: Asustek P/I-P55T2P4 rev 2.1CPU: P1 133 mhzRAM: 64 mb EdoSCSI: Cristie Parallel Port controller (n/a?)COM1: In use - 9600 bit/s, FIFO-buffer, adr: 3F8 - 3FF, irq: 4COM2: In use - 9600 bit/s, 2F8 - 2FF , irq 3LPT1: In use - adr: 38C - 38E, irq 7LPT2: (n/a?) 378 - 37F, irq (n/a)LPT3: (n/a?) 278 - 27F, irq (n/a)FDD: sony mpf520-1, 3,5 tum 1.44mbCD: Creative 24xfde (CD2422E)HDD: Conner CFS1275A, ideKBM: Microsoft mouse (intellipoint software?)PER1: Gameport JoystickPER2: MPU-401, adr: 330 - 331, irq: 9SC: Aztech Sound Galaxy Washington 16 (n/a?)NIC: smc Ethernet 8416bt (i/o 240, irq 11) isaPSU: Mapower PP-200T 210wI am adding screenshots of the Bios startup sequence and the Windows Device Manager as well.Quote from: dexters_lab on February 11, 2020, 11:16:42 amI thought about that as well, but I was shot down there - no unnecessary moving or screwing about with the equipment will be allowed. I was forced to ground every part of the entire setup with a bunch of copper-wires before they even let me open up the PC-chassis! >_<Quote from: dexters_lab on February 11, 2020, 11:16:42 amYou have some good instincts! Re-reading the manual for the program, this is what I think as well. I actually have a lot more pictures of the actual card, including some of the back-plane (shot with a mirror, since I'm not allowed to even physically TOUCH the ISA-card) I'm going to do my best to get back to drawing out some connection diagrams here, so we can move forward.This thread, and you guys help, is just what I need to get back to the reverse-engineering! =)

author: L.R Johansson
author_rank: Contributor
timestamp: February 11, 2020, 02:56:36 pm
content: Quote from: daqq on February 11, 2020, 12:12:45 pmThis is true, and I have gone back and forth on this several times - eventually, I figured I *had* to try something, as time is running out. (been at it for almost two months)But you're right, the pinout, the actual 'protocol'/method wherein the card receives data, may not actually be anything standard.Quote from: joeqsmith on February 11, 2020, 01:06:48 pmHaha! Yeah... Not sure if you're only being sarcastic, or if you recognize some parts of your own young self in me? Your assessment is correct though - I am a risk-taker - I have treatment-resistant ADHD though, so it comes with the territory. I'd totally stay when everyone else goes home, but they won't let me, for security reasons. : [This may indeed cost me every shot at this - but then, I don't have much to lose either - I've been unemployed for some time, before I got the former temp-job at this place. (not in IT or electronics)Anyways, I'm not the type to shy away, nor give up easily! Rock on, my dude!

author: johnkenyon
author_rank: Regular Contributor
timestamp: February 11, 2020, 03:06:26 pm
content: Quote from: L.R Johansson on February 11, 2020, 02:28:15 pmAhh - the joys of dealing with a nervous customer, who has a "one of a kind bit of kit".You have now left "hard" engineering and entered the world of "soft" people skills...My advice:Talk and actively listen - ask them what they are worried about.Make it clear that you have common objectives.If the customer makes suggestions are made which increase the risk, don't be afraid to push back with the line of "sorry your kit is too important/valuable/"other button pushing word" to do that".This includes any "lets leave it", with it's attendant risk that the kit fails anyway, and you don't have a functioning setup to reverse engineer.If you want to connect a logic analyser, you are going to have look at the risks involved, and address/mitigate them.Do this before you make any proposal and get buy in.You need to be the biggest pessimist on the planet - think of anything that could go wrongTwo things you could do to mitigate:Reverse engineer a schematic for the ISA card, and obtain spares.This will show which components are connected to the outside world, and are most likely to be damaged. (my money is on the devices sat in sockets).Then source replacement components, noting that if you have spares, you will almost certainly never need them...Avoid having a birds nest when you connect the logic analyser.A mass of cables hanging off the back of a 25 way connector will have them worried.Build a breakout board - a PCB or stripboard with a DB25F at one end, and a DB25M at the other wired one to one. In the space inbetween mount clearly numbered pins to allow you to connect the logic analyser without the danger of adjacent connectors shorting out. Use this together with a short cable to "break in" to the PC-Amplifier connection:like this<--new cable--< <-Breakout board-< <-Existing cable-<<[ADC amplifier]hope this helps/jk

author: Cerebus
author_rank: Super Contributor
timestamp: February 11, 2020, 03:15:22 pm
content: Quote from: johnkenyon on February 11, 2020, 03:06:26 pmThe easy way to do this is to use IDC DB25 connectors on a length of ribbon cable. You can either have a 3rd breakout DB25 on the cable or just fan out the ribbon cable to a breakout board.

author: daqq
author_rank: Super Contributor
timestamp: February 11, 2020, 03:44:52 pm
content: OK, well, without actual access to at least a few minutes of the data by means of a proper LA, or at the very least some more internal reverse engineering you are doomed. Sorry.You can guess, but that's about it. What's worse, if you connect it to a parallel port adapter and it's not a proper fit, best case it just doesn't work, worst case, you break the ADC device by means of some short circuit.Given the level of access you currently have (look at it from afar and take one picture) I'm not sure what they are hoping you can accomplish.You can, however, probably acomplish the task (or at least postpone it) by buying an industrial MB that has a legacy ISA slot (https://www.ibase.com.tw/english/ProductDetail/EmbeddedComputing/MB970orhttps://www.voice-boards.com/product/computer-isa-intel-core-4u/, there are others). They are fairly rare and likely to be expensive. It's not elegant, Cthulhu knows if it will work.

author: TerraHertz
author_rank: Super Contributor
timestamp: February 11, 2020, 03:50:18 pm
content: What a shame they won't let you pull the ISA card, to take decent square-on photos of the front and back. Preferably with the 40-pin chip out of its socket too, if the socket is the open-frame type that lets you see tracks underneath.With those photos you should be able to tell which pins on the D25 are ground (and maybe power?) If they are different to the standard ground pins of a parallel card, that would tell you it's non-standard. Google IBM PC parallel port pinouts.One curious thing about that card - the mix of 74LS and 74HC. Many amateur designers assume these have compatible logic levels, but they don't. The H output of 74LS (without pullups) is very marginal for the H threshold of 74HC. The result of doing it without pullups is usually quite flakey system operation. Such circuits should use 74HCT logic - it has TTL compatible input thresholds.I see that HC245 octal buffer is connected directly to the PC data bus. Apparently no pullups since those R-packs seem to be associated with the D25 port. Surprised it works at all.Another nube giveaway, is the use of poly-caps as power rail caps, rather than ceramics. Someone didn't understand HF impedance differences with differing cap constructions.Ah! I should have spotted this - the above points say the card is definitely not any kind of standard parallel port. It was a custom design by someone with little electronics experience. A physicist?Do I understand your system operation correctly?The NI (Thalium doped!) scintilator crystal and photomultiplier tube, produces varying size&duration analog pulses depending on the energy of detected gamma rays.The AtoD section digitizes that signal, and quantifies the pulse magnitudes into 1024 accumulating bins. Whether the bin accummulators are in the ADC unit or software in the PC - unknown. I'd guess the latter. So the ISA parallel interface card is receiving either realtime digitized pulse waveform, or quantized pulse magnitudes, or scans of a bin array in the ADC unit. It all ends up as particle energy vs pulse count graphs on screen.Your aim is to clone the existing system but on modern hardware - something with PCI or PCIe slots, or maybe USB. Replacing the ADC module (maybe) but definitely the ISA interface card? While keeping all or most of the existing software? But you aren't allowed to touch the ISA card at all, let alone dissect it to reverse engineer the circuit, or run a logic analyzer examination of what it and the software do to with each other.That card won't be the only hardware dependency of the software. It will also be driving very archaic graphics cards, and that's going to need fixing too.Hard work.By the way there is another approach to particle spectroscopy on PCs. Feeding the Scintillator tube signal into a standard PC sound input to digitize it, then analyzing the waveform in software to derive pulse strengths, ending up with the same kind of spectrum plots. Some links:google "PRA and Fitzpeaks software" --> lots of useful linkshttp://tech.groups.yahoo.com/group/GammaSpectrometry/message/1007http://zomobo.net/Gamma_spectroscopyhttp://www.theremino.com/en/blog/gamma-spectrometry/The Theremino_MCA while being completely Freeware and OpenSource is a true multi-channel-laboratory Analyzer.Also these HP App notes:AN 73 Calibration of a Gamma Ray SpectrometerAN 139 Stabilizing Gamma-Ray Spectrometer Systemshttp://everist.org/archives/scans/RAR-books/HP_AppNote_73_RAR-book.jpghttp://everist.org/archives/scans/RAR-books/HP_AppNote_139_RAR-book.jpg

author: rrinker
author_rank: Super Contributor
timestamp: February 11, 2020, 04:36:36 pm
content: Reproducing the old card would be easy - if you could get a decent view of it to see the traces on both sides. Much can be guessed at by comparing the ISA bus pinout and the data sheets for the glue logic as well as the 8255. This is almost what I did way back in the day - there was a company selling multiple IO line ISA cards with one or more 8255s in them, but their catalog page had one photo that was just a bit too clear - I was able to see the parts used for the decode logic, and then using knowledge of the gate arrangement of those chips plus what the 8255 wanted, I was able to draw a schematic for a circuit that did the exact same thing. I never did end up building it, as the more modern way is to use a multi-drop serial bus like RS485 and have multiple interface cards with fewer bits of I/O distributed around instead of running bundles of 50 pair to one central massive I/O card.Your MUCH bigger problem will be to replicate the software. Without source code, and with no real idea of just how much processing it actually is doing - others have mentioned this as well - is the interface card getting values, or raw data? Is the PC then just processing data and organizing it for reporting, or is it doing the actual processing of raw data?WHat's funny is the spec of the PC sounds like the machines we were building for customers in the early 90's. Same motherboard and CPU, and optical drive. It's what I was using at home at the time even.

author: free_electron
author_rank: Super Contributor
timestamp: February 11, 2020, 05:09:47 pm
content: Looks like a bog standard implementation of an i/o card based on a 8255.my 2 cents : most of the logic (74xx series) is for address decoding and bus buffering (the 74xx245).300 h - 31FC h is the so called 'experimental range'. This was reserved for products under development and there is a 'gap' in the bios ANd in even modern operating systems. as far as i know You can always read/write to those locations without requiring a kernel mode driver. The I/O operations are never blocked for that i/o block. Note that this is NOT a memory location but a separate I/O block of adresses.Note that what you have there is NOT an ISA card ! ISA cards are 16 bits and have the wider connector. Yours is only using the 8 bit.This card has 4 control lines for bus cycles RD and WR are used for IO while MEMRD and MEMWR are used for RAM. Even though the bus has 20 address lines (A0 to A19) only the lowest 10 (A0 to A9) are used in the I/O range (the AEN signal notifies you) . I/O is limited to the range 0x00 to 0x3FF ( so only 10 bits .. 0x3FF on a 20 bit address bus is = 0000 0000 0011 1111 1111 ). The logic implemented in the bus controller will not toggle the IORD IOWR or CS lines for any memory location other than that block. so there is no need to decode the other address lines, nothing can reside there anyway. Since the experimental range is 300x to 31f you also don't need looking at the lowest 5 bits (a5 to a0). so the decoder only needs to trap A9 to A5. if that is 0011 000x xxxx then you are in the experimental range . you then map the 8255 into one of the 31 possible address given by A4 to A0. ( see diagram below. the first decoder detects if we are in experimental range and controls the 'INRANGE' signal.This signal is combined with IORD and IOWR to set the 74245 in the right direction.The lowest 2 address lines go to the 8255. it has 4 registers. all the secondary decoder has to do is figure out which subrange the 8255 will be mapped to : 0300 to 0302 , 0303 to 0307 , 0308 to 030B , 030C to 030F, 0310 to 0312 , 0313 to 0317 , 0318 to 031B , 010C to 010F. so the secondary decoder only looks at A4 to A3.It looks like your board has more jumpers so they could map beyond the experimental range. That is typically not done as it could step in printer ports ...There are many examples of 8255 style io cards floating around and various electronics magazines used to roll their own in the 80's and 90's.the 8255 in itself is pretty stupid. it has 3 8-bit ports. one is a bit special as it can be used as a handshake control for the other two.In your implementation the only thiNg that looks out of the ordinary is the presence of that counter and some cmos (4000 series) logic.. it is highly uncommon to find that in an otherwise ttl based system. the counter is probably used to do some timing kerjiggery.That being said : all you care about is the stuff attached to the I/O pins of the 8255 ( ports a b and c ). any logic sitting between the XT bus and the 8255 is of NO interest to you as that will be bog standard. so focus on that.Since the 8255 can not generate interrupts there is no potential headache there either.Now here is part 2 : even the modern PCI bus has provisions to acces the ISA range of io locations. you can still build a PCI or PXI express card that requires no drivers and maps logic to the old XT/ISA io regions. The modern computer hardware automatically reroutes all io functionality to those ports.http://www.neutronusa.com/prod.cfm/1221720/glb?gclid=CjwKCAiAvonyBRB7EiwAadauqcf99Ue6sw8mMtcNNIuubXFAIXNFLtnx5IrhJDTPu1iwNNHKlmSqfBoCmOQQAvD_BwEThat card should be able to do it.this board gives you the 24 pins of the 8255. all you would need to do is recreate the portion of logic that sits between the 8255 and the db25 connector on your board.My gut feeling is there you will find some 4xxx logic and that counter. If you replicate that and hook it up to an 8255 PCI card your existing driver should work fine. (you will need to run the card config program once to tell it where to 'map' . like setting virtual jumpers ). After that the whole I/O shebang is transparent. the software does not know this whole block is running over pci.

author: Gyro
author_rank: Super Contributor
timestamp: February 11, 2020, 07:18:44 pm
content: Agreed. Given that the 8 bit ISA bus to 8255 interface and decode logic is know and bog standard, it's only the stuff above the 8255 - the 4000 series logic and associated bits that needs working out. That should be possible to trace out fairly easily with a with a pad and pencil without powering the card.I'm sure we can help with interpreting the result.P.S. One thing that I can see might be an issue is S/W timing. I've had problems in the past (actually with a parallel port plotter driver - not mine!) where the S/W was using loops etc. to establish timings, which of course became far too fast on a more modern PC. Bad implementation of course but it happened. That's the point where it might be necessary to do a comparison of 'before' and 'after' interface timings.

author: johnkenyon
author_rank: Regular Contributor
timestamp: February 12, 2020, 10:53:59 am
content: Quote from: Gyro on February 11, 2020, 07:18:44 pmWhat about HW timing?The LS292 is a programmable divider, clocked from somewhere, - this might be providing some kind of clock for incoming data.Now there's no crystal or module on that board, so where's the clock source and could it vary depending on how the southbridge on the motherboard is configured...?

author: free_electron
author_rank: Super Contributor
timestamp: February 12, 2020, 02:59:35 pm
content: the Xt connector has a two clock signals. one is is basically the bus clock, anywhere from 4.77Mhz to 12Mhz . The other one is a fixed 14.318-something.the bus clock takes 4 ticks for an access cycle. i suspect they use that counter to create a dedicated 'pump clock'.for example write data to 8255 port a. (register 0 , a1=0 , a0=0. ) the little bit of glue logic detects that and resets the counter. we know the data will appear on the output of the 8255 one clocktick later. so we let the counter count to 2 ( to let the data stabilize ) the moment bit 1 of the counter flips form 0 to 1 that point is passed. This signal is used as the 'pump clock'. the same signal locks the counter ( stops the counter ) ( or maybe they lock it at count 3.Such a construction is used to avoid needing a control signal on the 8255 that the software needs to toggle. It is enough to write to a specific location to have that pin create a delayed toggle that falls within a bus access cycle. so i can write as hard as i can to that register without ever risking a timing issue. the pump clock is derived from the register access and skewed in respect with the operation , but still lands within a bus cycle. this is sometimes called peristaltic clocking. Used to transfer clock domains in asics and fpga's. oldest trick in the book. Your data travels with a derived clock of the access cycle.They could be using that to stream read form the convertor as well. if i 'read' from one of the 8255 ports , this pump clock generates a pulse to start the a/d convertor. By the next bus cycle new data will be present so all i have to do is read again. no need for software created handshakes. i can read as fast or as slow as i want. every read guarantees me new data.Using pumps clock your system becomes detached form software and hardware timing issues. it is now a stream that runs in sync with the bus speed. the RD / WR signals are always 4 clockticks long so you can do 4 things per cycle.they could even decode the output of that counter to create several 'events'.for examplecounter = 0 : start conversion signalcounter =1 : wait time for conversioncounter = 2 : latch output data and perform nulling of the a/dcounter = 3 : halt counter.

author: MarkMLl
author_rank: Frequent Contributor
timestamp: February 13, 2020, 07:30:40 pm
content: I'm not sure whether this is even remotely useful, but it reminds me of a digital output module fitted to a Tek storage scope which had a similar 25-way connector with TTL signals in parallel (i.e. whatever it looked like it wasn't an RS232 serial port and wasn't a Centronics-style parallel). I think that the lesson is that for stuff that old it's pretty unlikely to be anything other than a proprietary pinout+protocol, Hell in those days you usually needed a posse of gender benders and patch boxes to connect two serial ports together.MarkMLl

author: L.R Johansson
author_rank: Contributor
timestamp: February 21, 2020, 09:12:28 pm
content: Uuunghh!!My ADHD is making it exceedingly hard to reply properly to this thread - but rest assured, the work continues, with you guys AWESOME tips taken into account! = ) I've learned a bit of Altium now, so I've got the basic board mostly laid out now, just have to connect the components.I'll try and smack out what I've drawn out soon, so stay tuned!Oh.. btw, my work-place decided my work so far was impressive enough that they've HIRED ME!It's only for 3 months, but it's far, far better than unemployment.

author: eliocor
author_rank: Unknown
timestamp: February 22, 2020, 12:34:51 am
content: If you can't access the ISA board, I hope you can at least make a copy of the following files:- config.sys- autoexec.batonce done you can identify what program/drivers are loaded during the startup.I have a rather good experience in disassembling DOS/Windows programs (please do not ask why!) and it is easy to identify the I/O ports accessed by the program/device driver.This will help to identify the mode in which the 8255 is set and what registers are read to download the data from the MCA.Please (if possible) copy/transcribe/dump/photo the contents of those two files and publish them: I will tell what to do next.P.S.: reverse engineering of SW is permitted in Europe just to solve problems like this!

author: free_electron
author_rank: Super Contributor
timestamp: February 24, 2020, 10:32:02 pm
content: you may not hae to reverse engineer the drivers. if you ise a pci-x version of the 8255 card it will open the correct 03xx io gap. the existing driver will work. PCI is transparent for tis kind of old school I/O the hardware translates eveything. you can even hook it to the LPCI (low pin count interface ) like used for TPM stuff. basically ISA over a 6 wire bus

author: eliocor
author_rank: Unknown
timestamp: February 25, 2020, 12:16:07 am
content: IFhis board works at the prototype address range: from what I know, this is unknown....

author: james_s
author_rank: Super Contributor
timestamp: February 25, 2020, 03:38:56 am
content: Reverse engineering the card ought to be fairly trivial, I built a 8255 based IO card when I was probably 12 or 13, there is not much to it.The software side is going to be a lot harder, but I think I would make up an adapter to sit between the card and the equipment to connect a logic analyzer and start capturing data while the thing is running. If you know what the operator is having the machine do you can start analyzing the data and reverse engineer the communication. It's likely something fairly simple.

author: coldfiremc
author_rank: Regular Contributor
timestamp: February 25, 2020, 05:42:54 am
content: That board is almost pure software driven. Load a debugger and dissasemble/intercept the out and in opcodes that go for those I/O addresses. You can even be a smartass guy and put some microcontroller, or even an Arduino to "hear" what's happening in another ISA slot, to then store it or put into a serial port, without strictly dissasemble. A book like "ISA system Architecture" from Mindshare, could help you with the bus timing. Then, that will be enough to find out what is the 8255 doing. Isn't a great deal, is just an I/O blockbuilder device.There are some FPGA based boards for PCI that do the same, with almost no software changes. I don't know if some of those boards need some kind of extra initialization. Check for Measurement Computing PCI-DIO. It has a 37pin DSUB output. You can buy a 37 pin connector and reorder connections yourself.

author: free_electron
author_rank: Super Contributor
timestamp: February 25, 2020, 02:16:39 pm
content: Quote from: eliocor on February 25, 2020, 12:16:07 amfirst post : The PC/XT card can, via the jumpers, be set to communicate over the adress-range 300 h - 3FC h.so : yes.

author: L.R Johansson
author_rank: Contributor
timestamp: March 04, 2020, 04:29:20 pm
content: Hi again! Since last time we all spoke, I've been hard at work, learning Altium, and reverse-engineering the card.I've got some new pictures to reveal! I've updated the first post with them, and down below you can see the actual PDF of Circuit and Logic -diagrams.What do you think, lads?I've got most of it mapped out, and there's a few things I'm curious about:1. On the 8255, Pin 13 and 16 have been wired together, which means that he's not running port C in either one 8-bit config, or two 4-bit configs, but one SIX (6) bit config?? Am I getting that right?2. SN74LS292N have pins 15 (input C), 14(input D) and 10 (input A) wired together, as well as pins 1 and 2, which means that out of a total of five available programming input ports, he has reduced it to only two. What is the significance of this, if any?Any input and feedback is, as always, welcome.EDIT: I notice that I misinterpreted how the Source and Ground weave in and out of the front and the back... quite the short-circuit! But I've corrected that now. Stay tuned for the more improved diagram this evening!PCXT.pdf(650.38 kB - downloaded 114 times.)

author: L.R Johansson
author_rank: Contributor
timestamp: March 12, 2020, 04:07:06 pm
content: Things are still happening! I'm going to be presenting a preliminary pinout tomorrow.It's not looking too good when it comes to my hypothesis that it's acting as an LPT-port though... Stay tuned for an almost complete connection diagram.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: March 16, 2020, 01:48:56 pm
content: Edit: This thread is too confusing for me and I'll refrain from further engagement.I'm not sure if trying to design a card for a very obsolete bus is a good way to turn your intern ship into a regular job.Best system for the job is probably some industrial grade PC with a standard data acquisition card.The added value for you would be to design some signalling conditioning electronics and maybe some interface software in the PC.A "standard industrial PC" with a "standard data acquisition card" may seem boring, but there is lots of stuff out there and the choice is not trivial. It can make or break the project.There are also semi custom solutions. For example, have a look at Mesa[urlhttps://duckduckgo.com/html?q=mesa+io+card] The Mesa cards are popular with LinuxCNC (which is why I know of them) Some of them use an FPGA for the bus interface (PC104 (maybe also PCI) and can be combined with some frontend of your own design.Think about this:Do you really want to design an 8-bit ISA card for an 15+ year old PC which probably should have been scrapped and replaced already if it has any important role in the company. Is it even possible to buy a replacement PC with the same connector?Another important question that is not clear to me is if this is a one-off or if the goal is to sell these things in the future..

author: Cerebus
author_rank: Super Contributor
timestamp: March 16, 2020, 02:41:12 pm
content: Quote from: Doctorandus_P on March 16, 2020, 01:48:56 pmHe's not "trying to design a card for a very obsolete bus", he's trying to reverse engineer it so that he understands the interface with the 'experiment' and the interface with the software that comes with it. This is so he can ultimately replace the whole 'computer bit' with something more modern but running the same software (possibly in emulation) and, implicitly, do it to keep a legacy instrument working with a more reliable back end.If you read the very first message in the thread, all the information is there to explain that and also to answer your other questions/assumptions.

author: L.R Johansson
author_rank: Contributor
timestamp: March 17, 2020, 04:21:24 pm
content: All right, this is what I've got so far:The pin-out does not correspond to either the pin-out used for LPT-ports for printing, nor does it seem to be a Synchronous Serial Port. Anybody here who recognize this sort of pin-out?I've tried to trace the lines to the best of my ability, and I've gotten quite far, but there are still a few things that vex me - the biggest issue being that I can't figure out where the lines out of the 8255 that are not connected in the back, but shrouded underneath the IC, are connected to - the same goes for the LS292 - most of the connections are on the top-side, and shrouded under IC's.You whom have the greater experience, where should the missing lines logically go?Link to PDF-export:https://www.eevblog.com/forum/beginners/help-analyzing-logic-functions-of-isa-card/?action=dlattach;attach=950988

author: MarkMLl
author_rank: Frequent Contributor
timestamp: March 17, 2020, 05:22:31 pm
content: You definitely deserve extra points for your research on the serial connector, not only did the RS232 standard include clocks for serial operation but there were actually pins for a low-speed fallback (typically, half duplex if the modem decided it couldn't do full duplex). Unfortunately it's not relevant, since if you were looking at a serial port you'd have found the drivers to provide the full-spec +-12V swing.Having determined that it's not a parallel printer ("Centronics") port, my opinion is that so many people used that connector for proprietary purposes that you're wasting your time trying to find a close match. I've seen it used for everything from SCSI to direct-access to a DSO's A/D converters, for EPROM programmers... literally for so many things that my recollection of them is by now just a blur.Focus on trying to work out the functionality of the unidentified pins, and what the software does with them. If necessary investigate emulation solutions which might be hackable to trace data on the I/O ports, which might be easier than using a logic analyser.MarkMLl

author: ace1903
author_rank: Regular Contributor
timestamp: March 18, 2020, 10:31:35 am
content: Sometimes it is worth checking what is in the box on the other side of the cable.Take pictures, look at the system from a system level. If it is ADC, which model it is, how many control signalsare needed for it, important timings etc... Then you can make emulation board(with the same adc or some micro to emulate it) and focus on designing ISA board to cover your use case.I believe that ISA CARD and connector is from some provider and not some custom one. Maybe you need only a couple of signals from that connector.If I were you I would focus to modify some FTDI board (FT245 based, do not remember well which one was for parallel port emulation) to do the job of the that ISA card and laterto make modern copy of that whole system.

author: L.R Johansson
author_rank: Contributor
timestamp: March 27, 2020, 01:20:27 pm
content: RIGHT!It's time to really dig in, and try and analyze everyones advice properly - take in what it could mean, and really do some PROPER replies to everyone, whom I am very greatful for taking their time to look into this.Quote from: daqq on February 11, 2020, 10:21:08 amYour warning has quite good and correct! This is most definitively not a standard Parallel port - the pin-out is completely customized. Do you have any thoughts on the pin-out I managed to scrape together?Quote from: johnkenyon on February 11, 2020, 10:41:52 amI think I've got most of the connections figured out now - wired up almost everything of the 8255, but there's a few lines missing, that I'm not sure about... The most problematic is the connection of the Jumper-headers and the IRQ-lines on the ISA/PCXT -port.I'm also finding it rather difficult to focus enough to think in terms of the logic-processes the schematic actually results in. hrrrm!*mutters and scratches head*My current analysis is that the 8255 is set to Mode 2 - Bidirectional. This matches some similar setups I've found online - but I may of course be wrong. Could you perhaps have a look at my latest files and give your assessment?QuoteDo you know of any examples of schematics or software that utilizes the Strobe operation? Would certainly make it easier for me to wrap my head around what it should look like.Quote from: dexters_lab on February 11, 2020, 11:16:42 amActually, looking through the pin-out I managed to make, it seems as if I've found 11 ELEVEN parallel lines going to the ADC! : O What on Earth could the extra line be for? Strobe-operation? Or is it one of those cases of you needing an extra line in order to get true, effective 10-bit resolution?Btw, I've convinced my boss to let me take the top off of the ADC / OP-AMP -box (scheduled for next week), so soon there might be some illumination on this subject...Quote from: up8051 on February 11, 2020, 01:18:08 pmSorry for not explaining earlier - that's because of inter-company and external politics. My boss has forbidden me to contact the company that designed the card. (we actually know who they are) Because they have become our competitors, I can't risk writing out the real name of the card, et c, for fear of alerting a potential engineer still working for the company.(unlikely, really, from the list of employees I see online - I'm guessing the original people have all retired there, as well. But I can't risk it.)

author: L.R Johansson
author_rank: Contributor
timestamp: April 07, 2020, 08:38:43 am
content: Hey everyone - here's another update, and this time around, I intend to revamp the whole thread, so that things are more focused and with clearer reference-materials, so as to make my ramblings more understandable.In the meantime I'm considering a PC/104 board with an I/O-module as the replacements for the PC-portion of the system:--PC/104 Mainboard--Versalogic BayCatVL-EPM-31ECPhttps://www.versalogic.com/product/baycat/--I/O-module--TracerDIO 5VIOhttps://apexembeddedsystems.com/collections/digital-i-o/products/tracer-dio-5vioThe Tracer contains double 8255's and three 8254's, along with several I/O-headers and support for adress 300h and IRQ 2 and 5. (current system's adress configuration) Now, the Baycat, alas, does not support adress 300h, but I think I saw a couple of others within the range of the software, and it doesn't support IRQ 2, BUT..! Since I don't actually need all that much IO, I figure I can just reconfigure the adress and borrow from some other ports.(baycats bios seems quite neat actually - tons of options for configuration and fpga-modes)The only thing is that I haven't quite figured out yet if triple 8254 counter/timers are sufficient to really replace the decoder-logic on the existing Card - because I haven't been able to focus on completing the Functional Diagram / Logic Schematic, since the various LAST FEW wires that I haven't been able to figure out, causes a mental block for me.What's your take, gentlemen?

author: alanambrose
author_rank: Frequent Contributor
timestamp: April 07, 2020, 12:52:51 pm
content: Hi,Just to says thanks for your problem exposition and describing the steps you've taken so far. I have a similar problem with an old ISA card that I would like to replace, so I'm following the detail closely here.Alan

author: L.R Johansson
author_rank: Contributor
timestamp: April 14, 2020, 01:58:48 pm
content: Ey, guys... I've managed to get most of it done now - but there are a few connections that continue to vex me. Can someone have a look and give their opinion on where the last few lines should, logically, go?I'm updating the first post btw - adding my latest findings.Quote from: johnkenyon on February 12, 2020, 10:53:59 amIt's using HW timing - I've mapped most of the visible connections on both top and bottom, and it appears as if LS292 gets its clocks from:DB25 (pin 9) -> CLK1ISA (B30) -> CLK2DB25 pin 9 is of course then connected straight to the ADC. I managed to get permission for opening the ADC, so I've got a couple of images I'm going to post soon.ADC components:----------------------------IC1Texas Instruments TL071CP(Low-Noise JFET-Input Operational Amplifier)IC2Texas Instruments TL071CP(Low-Noise JFET-Input Operational Amplifier)IC3National Semiconductor LM311N(voltage comparator)IC4National Semiconductor LM339N(Low-Power Low-Offset Voltage Quad Comparator)ICxTexas Instruments TL074CN(Quad Low-Noise JFET-Input General-Purpose Operational Amplifier)IC5Philips 74HC74N(Dual D-type flip-flop with set and reset; positive edge-trigger)IC6National Semiconductor LM311N(voltage comparator)IC7National Semiconductor LM311N(voltage comparator)IC8Philips 74HC74N(Dual D-type flip-flop with set and reset; positive edge-trigger)IC9IC10Philips 74HC74N(Dual D-type flip-flop with set and reset; positive edge-trigger)IC11Philips 74HC74N(Dual D-type flip-flop with set and reset; positive edge-trigger)IC12IC13Philips 74HC08N(Quad 2-input AND gate)IC14Philips 74HC367N(Hex buffer/line driver; 3-state)IC15Texas Instruments SN74HC590AM(8-Bit Binary Counter With 3-State Output Register)IC16Philips PC74HC00P(Quad 2-input NAND gate)IC17Texas Instruments NE555P(Precision Timer)IC18SG 51PH(Crystal Oscillator) 50.000 MhzIC19Texas Instruments LM340T5(fixed positive voltage regulator )

author: free_electron
author_rank: Super Contributor
timestamp: April 15, 2020, 02:27:01 pm
content: so it looks like they built their own dual slope integrator ( lm311 is sort of a giveaway )you'll find that the 590 counter outputs go to the 8255 8 bit ports. Possible some of the 7474 flipflops are used to make additional bits.That means that the ramp up and down is under control of the PC and most likely the 292 counter on the ISA card handles the cycle.If they would just have used a ICL7109 ...

author: L.R Johansson
author_rank: Contributor
timestamp: April 25, 2020, 09:30:18 am
content: Hey everyone - I've done a major update of the first post - hopefully it's much clearer and informing now, featuring most of the info I have compiled, in one neat place.My employer has just had a rather stern talk with me, since the project is obviously taking longer than expected - I really need for deliver, and soon, or there shall be repercussions for not just me, but the entire company.So... if anyone can help me decide on a fitting DAQ-card, that would be amazing. I feel I'm closer than ever at the moment, but there are still a few, few things missing. Perhaps next week will see the Logic Analyzer come into play, and provide us with the final missing pieces.Quote from: ace1903 on March 18, 2020, 10:31:35 amThose are some good ideas, mate, cheers. I've added a ton of images of the ADC btw, alas, the model-number cannot be discerned, it does follow the same naming-convention as the company though, in part, so it might still be a custom-job of theirs.If you have the time, I'd love it if you could take a look and give your opinion on it:https://imgur.com/gallery/lSV7pzWQuote from: free_electron on April 15, 2020, 02:27:01 pmAlthough it's difficult to make out, at this moment, I do think you're right about the 590 counter. I've uploaded a Block diagram btw - could you by chance have a look at it and give me your thoughts on the logic?I'm going to update it soon, with what description I can wrangle out of the ADC reverse-engineer I'm attempting at the moment.EDIT:Here's what I've got so far, regarding the ADC:(images are clickable)

author: L.R Johansson
author_rank: Contributor
timestamp: May 11, 2020, 02:54:52 pm
content: Right, first post has been updated, and more info has been added.I feel as if we're really, really close right now... Recently, agreatgentleman on these forums helped me to disassemble the measuring-program, and through that disassembly we learnt that the 8255 must be running in:MODE 0 - GPIO!I've put quite a bit of time into reverse-engineering and studying the ADC, but I've hit a couple of snags on the road... If someone could have a look at my simplified diagram, and tell me where it goes wrong, then that would be great.(the red arrows indicate where something is messed up)Let’s assume (running SETUP.EXE) that:- Board I/O address is 0x300 (address of ADC interface)- Board interrupt number is 5- Latency / Wait State interrupt level is 2Running MEASURE.EXE, the following happens during the setup/configuration of the program:- SETUP.BIN is read: first 80 bytes are discarded; next 40 bytes (containing setup data) are read.- ADC interrupt and Latency interrupt are set accordingly to SETUP configuration.During program execution, when an interrupt is fired by the ADC interface board:- 8255APORT Bis read (MSB)- 8255APORT Ais read (LSB)- The two readings are combined in one 16 bit integer value- If value == 0 or value >= [a predefined number*] then acquisition is thrown away, otherwise histogram values are updated*background radiation reference- 0x9B [1001-1011] is written on the 8255A Control Register (I/O mode)- Program exits from interruptIn some other parts of the program (not exactly sure when it is executed) the following group of values are written to the 8255A Control register:- 0xB6 [1011-0110]:I/O mode- 0x0F [0000-1111]: BSR mode- 0x0D [0000-1101]: BSR mode- 0x0C [0000-1100]: BSR mode- 0xB6 [1011-0110]:I/O mode- 0x09 [0000-1001]: BSR mode- 0x0E [0000-1110]: BSR mode- 0x0C [0000-1100]: BSR modeEDIT:The images are blurry from the upload-provider... use the attachments instead.

author: L.R Johansson
author_rank: Contributor
timestamp: May 21, 2020, 05:01:30 pm
content: My brain is currently turning into partially cooked Carne Asada, but I've spent the most of the day going over various ways to do voltage-translation for FPGA's, and various small-ish FPGA's that should be suitable for this.Here's my preliminary BOM:1x FPGA (Lattice LFE5U-25F-6BG256I)1x PCIe x1 connector1x DB2510x On Semi 7WB3125MUTAG(there are 19 IO-lines coming in at 5V's, and the FPGA uses a 1.1v VCC, so 20 voltage translators - actually, I probably only need 10)I suppose I'm going to need some extra caps and resistors as well, yeah?Do I need to compensate for parasitic capacitances and do Impedance-matching as well?Btw, tomorrow is my last day as an employee, so it seems as if I rather FAILED at this project. : o I'll continue to try and solve it off-site though - I can't simply give up!This here project is going on my CV, so I gotta' make it good.

author: alanambrose
author_rank: Frequent Contributor
timestamp: May 22, 2020, 06:27:36 pm
content: >>> Btw, tomorrow is my last day as an employee, so it seems as if I rather FAILED at this project. : o I'll continue to try and solve it off-site though - I can't simply give up!Actually I think you're being too hard on yourself.Just as most projects are never 'finished', because you can always think of some improvements, nearly every single 'fail' has lots and lots of great benefits.In particular:+ both you and your employer have learned a lot and moved the project down the road a great deal.+ you've documented what you've learned and that will give someone else a great start if your employer decide to continue to pursue it.+ often counting an option out (say too unreliable a method or too costly to implement or 'simply doesn't work') is a very valuable piece of info that you couldn't find out without doing the detail work.+ your progress has given your employer a sense of the overall level of resource that will be necessary to solve the problem if they decide to pursue it.+ that resource estimate is a key piece of information for them to help them to weigh up their strategic options ... in turn to achieve whatever the overall business objective was.+ it sounds like you enjoyed the challenge.I suspect that your employer will actually be pretty pleased - they should be.On a different subject - do you need an fpga (this is all fairly slow speed) or will a simple micro do the job?Alan

author: L.R Johansson
author_rank: Contributor
timestamp: June 15, 2020, 08:19:22 pm
content: Quote from: alanambrose on May 22, 2020, 06:27:36 pmCheers for the kind words mate, after some more reflections and talks with people I have come to the conclusion that you are more or less correct - there are things I can improve for my next project, but I did a pretty good job after all.Meanwhile, work has CONTINUED on this whole thing! ^^ I've been updating the circuit-layout and completing the conversion to KiCad, along with adding some enhancements, that I hope will improve the function of the IO-card.Improvements:-----------------------------+Added Ferrite-beads to the 8255, to filter out interference+Replaced all TTL components with CMOS+Upgraded where possible all CMOS to Advanced High-Speed CMOS+Upgraded the DB25 to a filtered one+Added a pull-up resistor-pack to the 74245+Replaced all Metal-film capacitors with high quality ceramics+Added a 1 MOhm ground-resistor (need to add a chassis-wire too)+Capacitors added to uhh... I'll edit it in later.+Replaced jumper-headers with Switches (for convenience)Btw, I hope what I've actually added to the 74245 would be regarded as a pull-up resistor? What with the +5v flowing to the first pin on the pack.I'll add my new schematics later.EDIT:Right, so I have convened with my former employer and we have agreed to finish the project as such - there is now a catastophe-plan in place, new schematics and supplies of parts - my part is then at an end - time to move on, and do a new project - for my upcoming CV.Probably going to give a Video-card a shot, methinks.