Crosstalk analysis, Altium vs. the World - Page 1
Forum section: electronics / general

author: guillep2k
author_rank: Contributor
timestamp: May 16, 2016, 03:53:39 pm
content: This is something I've asked some time ago in the stackexchange community but nobody could answer properly. I hope it's OK to repost the problem here.I am trying to understand the real-world effect of crosstalk between nets, and I find I cannot match the data from abstract calculators (like Saturn's PCB toolkit and others) and the Altium crosstalk analysis.For argument's sake I've made a dummy PCB project in Altium in which I purposedly placed the components very far away from each other and the tracks very close together (to maximize the crosstalk). See a picture of my PCB here:It's a four-layer PCB with 1 oz. (35µm) copper on all layers, stacked like: signal, FR4 (0.3mm), GND, FR4 (0.85mm), VDD, FR4 (0.3mm), signal. VDD is 3.3V.The analyzed tracks (SPI from MCU in the lower left corner to a memory on the upper right corner) are 0.15 mm. wide and have a 0.15 mm. gap between them.Of course one shouldn't design boards that way. I should have so much trouble with a board like this.So I used Saturn PCB Design's PCB Toolkit (a free tool) to calculate how bad my crosstalk should be:Saturn PCB reports 2.64V of crosstalk for a nominal 3ns rise/fall time. My signals should be completely destroyed with such big a crosstalk.I tried using Altium for the same analysis (a much more complete tool). I've applied the IBIS model to the CPU and generic IC (LV) models for the other two chips. Then I ran the analysis and got no errors. Here it is:My surprise came when I generated a crosstalk analysis between the lines from the SPI group (SPI+CSEL), marking CSEL as victim and MOSI/MISO as attackers:As you can see, Altium's analysis gives a much more optimistic data of the crosstalk, amounting to mere +/- 75 mV, instead of 2.64V I've expected.Elsewhere I've read that Saturn PCB calculation has the wrong picture to illustrate the parameters, and the (S) parameter should be the distance between track centers and not between track edges. That would rise the distance from 0.15 mm. in my first calculation to 0.30 mm. Although the crosstalk is milder, the new data is not significantly closer to Altium's analysis:So I am clearly missing something here. First, what would the right value for Saturn PCB's (S) parameter be? 0.15 or 0.30? And more importantly, why Altium gives us values that are orders of magnitude lower than Saturn's? What am I doing wrong?Please find the Altium project and it's generated output (schematics, Gerbers, etc.) for referencehere(about 1.6MB).Thanks for your help!

author: John_ITIC
author_rank: Frequent Contributor
timestamp: May 16, 2016, 05:58:39 pm
content: In general, you'll get tens of mV of crosstalk, never volts. Altium is correct, the other tool is wrong. I don't have time to research causes but from my various work with Altium and Hyperlynx, the mV figures seem reasonable.

author: nctnico
author_rank: Super Contributor
timestamp: May 16, 2016, 06:58:16 pm
content: If I have to guess I'd say the Saturn tool isn't including the impedance of the output drivers in the calculation.

author: guillep2k
author_rank: Contributor
timestamp: May 16, 2016, 07:52:01 pm
content: The thing is, most formulas I've found to calculate crosstalk in papers or web sites are like the following:Xtalk = 1 / ( 1 + (D/H)² )(That's what Saturn's PCB does, by the way; also EEweb'sonline calculator)None of them take the driver's strength into account!! So, how good is a formula that can't be used in real life!?I get it, Altium (as expected) got it right. But, somehow the others must make some sense in a context that just I fail to see.

author: nctnico
author_rank: Super Contributor
timestamp: May 16, 2016, 09:48:52 pm
content: I think you'll need to take the original formulas which calculate the capacitive and inductive coupling between the traces, figure out the impedance at a maximum frequency (from the rise time) and then use the driver and receiver impedances to calculate how much current will flow and the resulting voltages. IMHO crosstalk currents can also be a problem if they are large enough to stress an input or output of a chip beyond the limits.