Xilinx Transceivers - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 12, 2021, 06:55:49 am
content: Hi,I'm new into transceivers and as my first project I want to start with Artix7 parts. do we have a good tutorial on how to config and use them, I want to experiment with the simplest protocols or even a simple custom one, for education.Any Hints highly appreciated.

author: asmi
author_rank: Super Contributor
timestamp: August 12, 2021, 06:42:30 pm
content: Begin by reading the book "High-Speed Serial I/O Made Simple". it's written by Xilinx and is an excellent introduction into multi-gigabit serial interfaces, even if it's a little old. It can be freely downloaded here:https://www.xilinx.com/publications/archives/books/serialio.pdfOnce you've read and understood the book, proceed to reading UG482. That should occupy you for a good week at least. Don't skimp on this, it is critical to fully understand how this stuff works before you go on to actually using them. After you finish this reading, you will know where to go next.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 12, 2021, 08:47:53 pm
content: Big thumbs up, actually my final goal is to transmit some data (Video and some control data) over coaxpress with chips from microchip, since they are very reasonably priced

author: asmi
author_rank: Super Contributor
timestamp: August 12, 2021, 09:27:30 pm
content: Quote from: ali_asadzadeh on August 12, 2021, 08:47:53 pmThe book I linked above is largely vendor-agnostic, though it does contain a section about their (now long obsolete) RocketIO transceivers. It does a great job in covering both the motivation for why serial interfaces are better than parallel ones, as well as the basics of serial connectivity like framing, line encoding, scrambling, control characters, what is comma and how it's used, etc. Seriously, once you digest it well, you will know enough to design your own simple protocol over serial connection. And the cool thing is that you can start playing with them using regular FPGAs, infact the low speed will actually be beneficial because you can just see the actual signal on a scope without selling your kidney to get one. Once you are comfortable with low-speed single ended connections, you can step up into LVDS or something similar (TMDS is great for 7 series), this will allow you to achieve a line rate of 1 Gbps or even slightly higher. Or you can step up all the way to MGTs, Artix-7 can reach up to 6.6 Gbps per channel on speed grade 2 and 3. These MGTs are complex due to their flexibility, but Xilinx did a good job to encapsulate it into their transceiver wizard, which allows pre-configuring them for certain well-known protocols.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 13, 2021, 08:36:17 am
content: Thanks, I'm reading the book now

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 16, 2021, 05:44:10 am
content: I have read the "High-Speed Serial I/O Made Simple" book, Now starting to read the UG482.But I wonder how the clock recovery actually works, Do you have any Idea? I know it's internal to the core and I should not bother it, But I'm curious how do they done it?Also about scrambling and unscrambling, any Idea or algorithm about that too, do we have some verilog code about doing just that too, so I can understand it better.Is there any opensource code on how to do MGT's on low speed wire?

author: asmi
author_rank: Super Contributor
timestamp: August 16, 2021, 01:05:54 pm
content: Quote from: ali_asadzadeh on August 16, 2021, 05:44:10 amThere is some explanation in UG482.Quote from: ali_asadzadeh on August 16, 2021, 05:44:10 amScrambling is specific to protocols, typically it's some sort of LFSR, so refer to a particular protocol's specification for more details. As for example, you can check out DisplayPort scrambler implementation, for example here:https://github.com/hamsternz/DisplayPort_VerilogDisplayPort version 1.2 specification is freely available from VESA website. There is an example implementation of it in C in the spec, which might be easier for you to read and understand.Quote from: ali_asadzadeh on August 16, 2021, 05:44:10 amI don't know of any, but you can use SERDES inside 7 series devices to get a first level approximation. One major difference is that SERDES does not have clock recovery circuits, so you will have to pass the clock along (or use some sort of oversampling to recover data, there is an appnote from Xilinx on how to do that), but you can emulate pretty much anything else.The thing about MGTs is that they have not only the maximum line rate, but also the minimum one, and they are typically specced at 500 Mbps, which is way too fast for affordable scopes. Which is why I recommend rolling out your own lower-speed emulations. If you mimic MGT's fabric interface with your emulation, porting it later over to MGTs will be much easier. Or you can do it all in simulation with MGTs right from the get go - as line speed does not matter for sims.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 17, 2021, 05:33:38 am
content: Thanks,QuoteDo we have a open source solution for lower-speed in here? or should I start from scratch? if I should start from scratch, I do not know how to implement many things like clock recovery.I have a 350MHz analog scope only

author: hamster_nz
author_rank: Super Contributor
timestamp: August 18, 2021, 10:39:56 am
content: Quote from: ali_asadzadeh on August 16, 2021, 05:44:10 amWell, my DisplayPort experimental code athttps://github.com/hamsternz/DisplayPort_Verilogdoesn't use IP blocks, and it uses a scrambler. It's really ugly.The details of how a scrambler works is pretty neat. Look for "self-synchronizing scrambler" inhttps://en.wikipedia.org/wiki/Scrambler

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 18, 2021, 04:25:59 pm
content: Thanks hamster_nz for the links,I think the key to recover the clock is to be able to adjust clock phases precisely, Something in the range of 12 to 16 bit with in a clock period, I think maybe it's the same tech that they have used in hi-res timers inside TI or STM32 parts to make Insane PWM resolution!In Both cases of Transceivers and Hi-res timers I have no Idea how they have done it or how they could add phase delays in the clocks,Does any one have any Idea about making clock phases?

author: hamster_nz
author_rank: Super Contributor
timestamp: August 18, 2021, 10:50:45 pm
content: Quote from: ali_asadzadeh on August 18, 2021, 04:25:59 pmMy rough (miss-)understanding is...- initially the receiver is clocked from the reference clock.- Bit transitions in the incoming data stream are converted to pulses, using a small delay and an XOR gate.- These pulses are used to steer a PLL, until the PLL is phase-locked with the pulses.- Once the PLL is locked to the pulses generated from the data stream, the receiver is clock-switched to the PLL clock.- Everything then works swimmingly well, until you don't have any incoming signal transitions and the PLL unlocks.- You then you have to reset everything and start again.Or at least that is enough of a mental model to use the high speed receiver.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 19, 2021, 07:18:53 am
content: Thanks, I have some new Ideas too, 1ns pulses would travel about 15cm in Copper over PCB, so maybe by using some N or P or other type of semiconductor they manage to slow the propagation delay in them and just tap in different locations to get different phases! is this Idea possible?