replacing eight 32K x 8 SRAMs with two 64K x 16 SRAMs - Page 1
Forum section: electronics / beginners

author: wichers
author_rank: Newbie
timestamp: August 24, 2024, 09:19:56 am
content: Due to dimension constraints I'm looking into simplifying my design (486 cache module) the current design consists of eight 32K x 8 SRAMs and is known to be working (see old_design.png).In my proposal I replace the eight 32K x 8 SRAMs with two 64K x 16 SRAMs in combination with an OR gate (see new_design.png).What's your advice? Will this work?

author: David Hess
author_rank: Super Contributor
timestamp: August 24, 2024, 11:23:34 am
content: I do not see how that can work as shown. The original design uses two 32-bit wide banks, but the replacement appears to be configured as two 16-bit wide banks. Is the 486 being switched to fetch 16 bits at a time?

author: squadchannel
author_rank: Frequent Contributor
timestamp: August 24, 2024, 01:34:35 pm
content: I don't think it will work.It probably recognizes 2 banks, but only 512KB (half) per bank. I think it is necessary to use BLE and BHE well.I have designed EDO-RAM for 486 before and it was very difficult. You need to have a flexible mind.I tried to think of a combination, but it writes to the same memory bank when there is a WE0 request and when there is a WE1 request. I think it is no good.

author: Benta
author_rank: Super Contributor
timestamp: August 24, 2024, 08:39:31 pm
content: Learn how to use buses in KiCAD. I'm not going to track labels. You might as well have posted a spreadsheet.

author: bson
author_rank: Unknown
timestamp: August 26, 2024, 06:16:43 pm
content: The WE# CSn# etc signals are active low, so if you want to OR them as negative logic you should use an AND gate (74AHCT08).I'd strongly suggest using 74AHCT logic with a 5V supply instead of 74F... much nicer and better in almost every way. Seehttps://www.ti.com/lit/ug/scla013d/scla013d.pdf. It won't have the drive capability of 74F, but this doesn't matter as all you're driving is a couple of CMOS inputs on the RAM chips.You can't replace Bank A with one 16-bit chip and Bank B with another, because the original banks are 32 bits wide.For reads, byte selects don't matter; this is why the original design simply has two OE#'s, one per bank, and the sole reason for this is so they don't try to both drive the bus at the same time since they're both 32 bit.The various WE# signals are byte lane selects for writes.Since each RAM now contains two banks you need to map these these to the chips' LBE# and HBE#.If we consider RAM A (U12), the low half (D0-15) it should have:LBE# = RDL16# & WE0#HBE# = RDL16# & WE1#Where RDL16# indicates a read cycle to the low half.Similarly, RAM B (U14) needs:LBE# = RDH16# & WE2#HBE# = RDH16# & WE3#So, you need a 74AHCT08 quad AND gate.Now, since reads don't use byte lane controls, it's pretty straightforward:RDL16# = RDH16# = CEOA# & CEOB#Which unfortunately requires a fifth AND gate. If you use SMD/SMT then there's a 74AHC(T)1G08 part in SOT-23-5.So, to summarize:OEAB# = CEOA# & CEOB#U12 OE# = OEAB#U14 OE# = OEAB#U12 LBE# = OEAB# & WE0#U12 HBE# = OEAB# & WE1#U14 LBE# = OEAB# & WE2#U14 HBE# = OEAB# & WE3#Does this make sense?

author: wichers
author_rank: Newbie
timestamp: August 28, 2024, 02:47:16 pm
content: Thank you so much for studying my question and your extensive reply and advice. It makes sense, I'm going to try if I can test/breadboard this before I design it.Thanks again.Alexander

author: bson
author_rank: Unknown
timestamp: August 28, 2024, 05:04:36 pm
content: I also realize you may need to generate CE# for U12 and U14, similarly to the OE#, where their common CE# = CEA# & CEB#. If there is nothing else on the bus though you can probably tie them to ground.