Does a 32Ksps 24 bit ADC traces need to be traced matched? - Page 1
Forum section: electronics / projects

author: drakejest
author_rank: Regular Contributor
timestamp: October 09, 2020, 12:25:11 am
content: I have a 32Ksps Delta-Sigma ADCADS131m08. Due to space constraints i can only traces matched to +-1mm accuracy. can i get away with this ? Basing on itsevaluation moduleits not traced matchedI use a 4 layer stack with the adc, filters, and connector on the top layer with a gnd fill, a solid gnd plane on 2nd layer, signal traces on the 3rd layer, and gnd plane on 4th layer. The adc is on an isolated section so it the only thing on that section.

author: Cerebus
author_rank: Super Contributor
timestamp: October 09, 2020, 02:07:08 am
content: One matches traces to match signal time of arrival, to avoid so called 'timing skew'.Signals on a PCB are going to propagate at some significant proportion of the speed of light. Quite what proportion is going to depend on the exact PCB material used, the exact layout and so on. But considering a simple trace on typical FR4 PCB material the propagation velocity is about half the speed of light, or about 150 million meters per second. At that speed a 1mm difference will mean a signal arrival time difference of 0.001/150x10^s seconds or around 6-7 picoseconds. Compare this to your sample timing of 31.25 microseconds. As the former is roughly 5 million times smaller than the latter, I think you can conclude that 1mm (or 6-7 ps) difference matters about as much as a fart in the face of a hurricane.If you want to limit skew to 0.1% of your sample time (an arbitrary choice), you'll have to match your traces to within 4.68 meters of each other. So, unless you're using a huge, huge, huge circuit board you should be able to get away with any reasonable layout. Which is another way of saying that you don't evenbeginto worry about trace length matching until you're talking about very high frequency circuits, 100s of MHz and above.I don't wish to be unkind, but your wanting to match trace lengths on circuit where it is grossly inappropriate is classic'cargo cult'territory. You've heard that matching trace lengths is somehow 'good' and you're imitating behaviour without understanding its cause or reason. You might want to step back and take another look at what you're doing and make sure that you understand the reasoning behind the design choices you've made and double check that you aren't including other features without understanding why they're there. You wouldn't hurt your circuit by trace length matching, but I don't know what else you've done based on imitation rather than understanding. One of those unknown things could well make your design either not work, or possibly even disappear in an expensive release od smoke.

author: drakejest
author_rank: Regular Contributor
timestamp: October 09, 2020, 02:55:05 am
content: This is my very first adc design and through reading so many materials by know (be it good and bad) i must have picked it up somehow. Thank you very much for clarifying things up.I do still have something i am wondering about, dont sigma delta adc sample at a much higher rate because it has to sum them up so it becomes 1 sample (apologies could not find what the value is for this IC, im not sure if Fmod=8MHz is the one if so then its still insignificant). In your opinion what frequencies should i start worrying about trace matching, is there a rule of thumb for this ?

author: ledtester
author_rank: Super Contributor
timestamp: October 09, 2020, 08:38:49 am
content: QuoteOn page 18 of the datasheet:https://www.ti.com/lit/ds/symlink/ads131m08.pdfthe table "OSR Settings and Data Rates for Nominal Master Clock Frequencies" gives you the over-sampling ratio (OSR). Examination of the entries shows that the input sampling rate is f_MOD which is f_CLK / 2.

author: Cerebus
author_rank: Super Contributor
timestamp: October 09, 2020, 09:15:27 am
content: Although a sigma-delta ADC oversamples, your signal of interest isn't at the oversampling rate, your signal of interest is still what it is. You're trying to handle a 16kHz signal by sampling it at 32Ksps, you're still interested in the 16kHz signal. That the ADC uses a much higher sampling rate internally doesn't alter the fact that the signal you are trying process/reproduce is at 16 kHz. It's a non-problem.As to the rest, start worrying when you can calculate what will cause you a problem.If you're designing a synchronous digital system, then your setup and hold times, along with your clock rate, will tell you the interval in which signals have to arrive to appear to have arrived together once they've been clocked into registers. Use that interval to determine how much skew between signals you can tolerate. If a certain amount of skew would violate your setup and hold timings, then match signals to better than that. There can't be a rule of thumb here because for a slow logic family your setup and hold times will be long perhaps even in microseconds, for the fastest logic families you're talking in terms of 10s of picoseconds.The same logic doesn't work for analogue signals, there the criteria vary more according to what you're doing. Until you're at the stage where you can translate your target specifications into a skew specification then just consider the effective wave length along your PCB, based on a rough estimate of signals travelling at 150 million meters per second. So a 150MHz signal will have a 1 meter wavelength, 300 MHz 50 cm and so on. If the wavelength looks significant compared to the physical size of your circuit, you probably need to consider track lengths. If the wavelength is much greater than the physical size of your circuit then you can make the simplifying assumption that as soon as it changes at one place on the board it changes at all places on the board. If you can't make that simplifying assumption, then is the time to consider physical layout as part of your circuit design. Depending on the exact nature of what you're doing a critical figure for track length matching might be 0.1% of your shortest wavelength, or it might be as lax as half a wavelength.There's a second figure to watch out for here. As soon as any signal has a wavelength on the same order as thewhole lengthof the track or cable it is travelling along you will need to start considering that track or cable as a transmission line and actually account for the way the signal propagates along that track or cable. If the track/cable is 'short' relative to the signal wavelength, say 1/10 or less of the wavelength you can usually largely ignore propagation issues. As soon as you are at or near a 1/4 wavelength cable/track then propagation characteristics become critical and youwillexperience phenomena that can stop you in your tracks if you don't understand them.

author: chintal
author_rank: Newbie
timestamp: October 09, 2020, 04:00:38 pm
content: While I am sure there are some exotic outliers, I don't think there is any situation where a 32ksps ADC will require length matched traces. Given this is your first ADC based design, I'm pretty sure you're nowhere near one of those exotic outliers.More importantly, however, and as has been pointed out, in your effort to length-match traces, it is very likely you have taken measures which otherwise degrade ADC performance. Getting 18+ usable bits out of a 24bit ADC is not entirely trivial. The things you should be focusing on are:Ground separation (between analog and digital circuits)Good, clean return paths for both. Usually through separate and non-overlapping ground planes for analog and digital circuitsMake sure to connect the two grounds only at a single point, as close to the ADC as possibleKeep all digital signals as far away from the analog as you can. Don't just put in a thin, there-for-the-sake-of-it analog ground planeTry to branch power off from your main power supply as quickly as possible to generate the power supply for your ADC, and don't take it from somewhere close to your MCU or such. You don't want noise from your controller to infect the power your ADC is gettingThe way datasheets and guides are written, as yes, what I have written here too, you may be tempted to treat the ADC's "Digital power" as the same as your controller's. It is not. You will have three distinct power regions for a robust design :the controller's regular noisy digital powerpower for the ADC's digital circuitspower for the ADC's analog circuitsThese last two supplies are actually the same supplies, but routed in such a way as to prevent noise from the digital side coupling to the analog side. This is done by having separate non-overlapping planes in the vicinity of the ADC and the "Analog power" heavily decoupled to produce the "Digital power".To get the most resolution from your ADC, you might want to isolate the controller power from the ADC power. In my experience, it makes a noticeable difference to do that with any ADC over 16bit resolution.

author: ejeffrey
author_rank: Super Contributor
timestamp: October 09, 2020, 04:40:34 pm
content: Length matching is not important in this application but signal routing in general likely is. I am also not clear what you are talking about matching: the + and - of individual differential inputs or matching the lengths between channels.You still want to route differential signals close to each other and far from other signals in order to get the best common mode rejection of noise. So the traces should naturally be close to the same length simply by virtue of following the same path. However at bends the trace on the outside of the bend will naturally be longer. Adding a "hook" to the shorter trace to balance the lengths is not necessary and potentially counter productive.If you mean matching the lengths between multiple channels, that doesn't matter at all and you should not try to do that. Keep each signal pair routed as a clean differential signal that goes as directly as possible while staying away from sources of potential interference. You definitely don't want to add meanders to balance them. They will not help, and if done poorly might make things worse.

author: KaneTW
author_rank: Frequent Contributor
timestamp: October 09, 2020, 04:57:59 pm
content: Depending on the application, the length isn't important -- but the resistance is. Especially when you're using this to measure RTDs, a couple milliohms here or there and put you out of your desired accuracy spec.They do need to be differential, and CMRR drops sharply with resistance mismatches. Realistically you're going to be limited by resistance mismatches in the input filter.Length matching multiple channels isn't needed; the offset will be calibrated out.

author: KT88
author_rank: Frequent Contributor
timestamp: October 09, 2020, 09:49:22 pm
content: You want to make sure you have the same impedance on each input. Any imbalance would lead to a phenomenon known as mode conversion. If the common mode noise picked up by both input traces and connected parts you will get a slightly different voltage drop across the impedances. This results in an unwanted differential signal that will be superimposed with your signal of interest. A good approach for a newbie to high-res ADCs is to get inspired by eval boards or reference designs. Ideally that of the part you are about to use. But cross checking with other parts - even from other manufacturers helps to spot the challenges.CheersAndreas

author: babysitter
author_rank: Frequent Contributor
timestamp: October 13, 2020, 07:06:30 am
content: There is in my opinion just little concern for wavey stuff on these lines, except for interfering signals. So it doesn't hurt to do it right.However, routing the signals close to each other and thru the same number of contacts, wires and vias makes sense thermal emf wise.