Address decoding+AND/OR  plane stuffs of control memory? - Page 1
Forum section: electronics / beginners

author: shivajikobardan
author_rank: Contributor
timestamp: September 06, 2025, 10:37:44 am
content: A little bit context: I have studied Thomas L Floyd's digital fundamentals book(partly, I did not do all the exercises as I was self studying). Now, I entered Computer Organization and Architecture. I was fine through the first few chapters on computer arithmetic stuffs, basic instruction set architecture type stuffs.However once I reached datapath design and specially control unit design, I cannot understand much.I am trying to figure how the control unit as designed by Wilke's is going to work.Here is the diagram:I went back to Floyd and studied about memory devices(advanced). so I think I can think something. Basically,- Fetch microinstruction from location- Decode it and execute itThis is what we want from control memory and that block diagram shown above.For fetching instructions, we pass the address of the first microinstruction to CMAR. Confusion-01: What is Mux doing here? Aren't mux used when there is multiple inputs and one to be selected? I can guess that this is about first address vs next address as determined by the address field. At first you select the external address and for the rest of the operation, you just select the next.The address in CMAR is in 3 bits. Meaning it can select 8 memory locations.Assume CMAR=100100101 will be passed via those not gates and buffers.Now what fact does the decoder uses in order to activate the control line?There are those black dots. Why are they there? What function are they trying to implement. I have lots of questions but I will end it here. I hope to seek some recommendations on textbooks I should pursue for "datapath and control unit" design so that I can accomplish this COA task.Note: Social medias are banned in Nepal, so I might be hyperactive here in eevblog, I hope that is Ok.

author: paulca
author_rank: Super Contributor
timestamp: September 06, 2025, 11:26:54 am
content: I think "conceptually" all the box shows is a memory chip.You have a 3 bit address (and "S" whatever it is).You have 9 bit words.8 words.These are interpreted 6 control lines and 3 'address bits'.If you watch, hopefully you can watch, Ben Eater's 8 bit breadboard computer, in particular his videos on the control unit design, you will note how he uses an EPROM for more or less what is in that box. His design differs for the CMAR and MUX, he uses a counter register which is preloaded with the instruction "control address" and self increments through the micro-instructions.I expect the control unit in the excerpt is appending the "next CMAR" address based on the current one, making them not just linear, but self referencing. This would in opposition to using a counter register, like a "sub program counter" like Ben does.cWord {control lines nextCWord }

author: shivajikobardan
author_rank: Contributor
timestamp: September 06, 2025, 11:40:37 am
content: youtube is banned since today. so I might not be able to as VPNs are very costly specially for video watching purposes.However books are there.

author: paulca
author_rank: Super Contributor
timestamp: September 06, 2025, 11:43:17 am
content: https://eater.net/8bit/controlThere is a schematic.

author: radiogeek381
author_rank: Regular Contributor
timestamp: September 08, 2025, 12:30:01 am
content: It is probably best _not_ to think of this as a memory. This is a PLAYes, it looks like a ROM, but in general these structures don't necessarily populate all the possible codes - there may be fewer than 2^N AND gates in the AND plane.The way to read the schematic:Let's number the CMAR outputs K2, K1, K0 in that order, from left to right.Let's number the AND gates A0, A1 ... A7 in that order, from top to bottom.Finally label the OR gates by the labels C5, C4, ... C0, a2, a1, a0 at the top of the drawing.OK. The AND plane is a decoder, but that's a special case here -- it didn't have to be, and most certainly won't be for wider control inputs (K0....).In the early days of PLAs - before they were called that -- those dots were diodes. They allowed a voltage level to propagate from the output of the buffer or inverter on K0 to a single wire to implement a (in this case) wired AND. So think of the dot as making a connection from Kx to the input of one or more AND gates. But when you see a horizontal wire going into A7 with dots on columns K0, K1, and K2 you should think "This connects K0 to one input of A7, K1 to another, and K2 to a third." The dots don't allow a path from K0 to K1 as they would if they signified a direct connection. The corresponding Ax output will become TRUE if all of the dots on its input wire are over Kx or !Kx lines that are TRUE.So now we get to the outputs of the AND plane. The dots here implement an OR function. That is, Cx will be true if ANY of the A0...A7 outputs with a dot on Cx's wire are true.For example. Let's say that we've got K<2:0> = 110. (K2 =1) That will make the output of the second AND gate from the bottom (A6) true.Following the A6 wire from left to right, we see it touches C4, C3, and a0 (little 'a'0). That is so because there are dots connecting A6 to the wires going into the OR gates for C4, C3, and a0. So if K<2:0> = 110, then only C4, C3, and a0 will be TRUE.The block labeled "S" driven by A3 is likely a 1:2 demux. This is an easy way for instruction decoders to test a flag (it would be the wire coming in from the top) and use the flag to influence the next selection. It also kinda adds an extra bit to the decoder if you bend your mind a bit.As I said, a bazillion years ago, when dinosaurs roamed the earth, those dots were implemented with diodes, and the gates with a couple of transistors each.In the era of NMOS, PMOS, and dynamic logic in CMOS, the dots were implemented with FETs. The primary advantage to this scheme was that the layout designers would put down transistors as if every junction had a dot. But only those places where they wanted a dot would get hooked to the corresponding transistor. This allowed almost all of the layout to be done and checked early, before the logic had been verified. (It also allowed feature changes without ripping up a lot of control logic.)I'm not sure how these would be implemented today. Modern high performance CMOS processes limit the use of dynamic logic to very very special areas, and automated place and route has likely diminished the advantages of PLAs.