Clock generation issue - Page 1
Forum section: electronics / projects

author: Tarmo
author_rank: Unknown
timestamp: April 19, 2014, 07:19:41 pm
content: I'm currently designing a circuit where the main IC's PLL requires a crystal oscillator or external clock signal with either 36.4MHz or 37.8MHz (+- 100ppm). Looking through Farnell, Mouser, Digikey etc. I couldn't find any crystal with the required frequencies.So I started thinking about using some sort of programmable oscillator. According to the datasheet using external clock input has some requirements:Signal can be sinusoidal or square waveWith square wave input and an AC coupling cap of 1uF the maximum amplitude is 400mVppWith sine wave input and an AC coupling cap of 1uF the amplitude can be in range of 300mVpp to 900mVppHas anyone suggestions on how to clock that bastard of an IC?

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: April 19, 2014, 10:04:37 pm
content: Weird clock frequency. I wonder where it came from? Your IC datasheet may give you some clue on why it is chosen. If it is a multiple of some common frequency then I would expect it to be specified with 3 digits like 32.768MHz. You can buy programmable oscillator with that frequency - I think DigiKey can do it for you - just go to "Programmable Oscillators" section and provide frequency with your order.If your source clock is 20MHz then to get 36.4 or (36.428571 MHz exactly) you need to use multiplication factor of 51 and division factor of 28 - I used ALTPLL Wizard in Quartus II (Design tool for Altera FPGA). Then you are off by 0.002 MHZ and that makes me wonder again - WHY?Please share what IC is this.

author: Tarmo
author_rank: Unknown
timestamp: April 19, 2014, 10:37:18 pm
content: The IC is Silicon Labs Si4777 broadcast receiver and HD Radio tuner (https://www.silabs.com/products/audio/digital-radio/pages/si477x.aspx)

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: April 20, 2014, 12:59:56 am
content: I see ... so 650 kHz sampling rate = 36.4 MHz / 56 and so on.Sounds like you need to get one of those crystals listed in datasheet. Strangely, you are right - I found that none are available from major suppliers.Maybe you can try something like Si570 - it is programmable from I2C so no need to buy $500 programmer for it, which make sense if you only going to make single prototype.

author: dannyf
author_rank: Super Contributor
timestamp: April 20, 2014, 02:08:54 am
content: QuoteTypically done via a mcu - they are typically i2c or spi interfaced.CDCE913 and its family from TI are fairly popular. I have used some from ONSemi as well.

author: retrolefty
author_rank: Super Contributor
timestamp: April 20, 2014, 02:13:32 am
content: If you have a u controller in the design you might want to consider a low cost DDS module. I've used one to be the 'tuneable' local oscillator for a home brew 40 meter CW receiver using a rotary quadrature encoder to adjust the frequency. If you only require a fixed frequency the u controller load would be very small as it would just to part of the initialization phase. I think it took just two digital output pins (clock and data) in it's serial interface mode.http://www.ebay.com/itm/New-AD9850-module-modest-capacity-AD9851-DDS-Function-Generator-up-to-40MHZ-/130724738518?pt=LH_DefaultDomain_0&hash=item1e6fcd35d6

author: Alexei.Polkhanov
author_rank: Frequent Contributor
timestamp: April 20, 2014, 04:53:27 am
content: Quote from: dannyf on April 20, 2014, 02:08:54 amCDCE913 is 3 times cheaper than Si570 but it requires an external crystal to drive it. It is still cheaper solution alltogether, but with extra components. Also CDCE913 has pulling range of 120 ppm - I am not sure if that makes it a fit to drive Tarmo's design or not since Si4777 requires 100 ppm max?

author: codeboy2k
author_rank: Super Contributor
timestamp: April 20, 2014, 06:13:16 am
content: Quote from: Alexei.Polkhanov on April 20, 2014, 04:53:27 amI think the CDCE913 can work here. It doesn't need an external crystal. If there is an MCU in the design already then it can use a clock output from the MCU to drive the PLL --- it takes an LVCMOS input.The 120ppm pull range (I read 150 ppm??) is for the internal VCXO. OP won't need this and can use the external LVCMOS input and the M/N fraction will easily get him one of the three frequencies needed by the si4777 (36.4 MHz, 37.8 MHz or 37.209375 MHz ) with 0 ppm error. The error will be whatever the source is... if it's a crystal source it will be about 50-100ppm anyways. But the PLL will get it to the exact frequency with 0 ppm error i.e. it won't add any additional error

author: Tarmo
author_rank: Unknown
timestamp: April 20, 2014, 08:56:41 am
content: Firstly, yes the desin will have an microcontroller of some sortThe CDCE913 seems suitable for the job. Only one question remains about the signal level, the datasheet specifies that the input should me 400mVpp AC coupled. The output of CDCE913 is either 3.3 or 2.5V depending on the supply voltage.

author: codeboy2k
author_rank: Super Contributor
timestamp: April 20, 2014, 04:05:33 pm
content: You only need a voltage divider at the output of the clock gen PLL.The CDCE913 has a low enough output impedance at around 270 to 330 ohms, it can source 10-12mA at 3.3V.The hard part is finding the input impedance of the Si4777 RCLK pin. I didn't see it readily on the datasheet. It's possibly a FET input to a NOT gate or something, which means its going to be a relatively high-impedance.So you can start out by assuming it's high enough to not matter , and calculate a voltage divider from 3.3V to around 400mV. So, my calculations show that Rtop= 102k and Rbot= 14k gets you close enough to 400mV without going over even if the input impedance of the Si4777 clock input is anywhere between 100k to 10M (355mV at 100k and 398mV at 10Meg) . Then AC couple it to the input with a 1uF cap. The divider will sink about 30uA from the clockgen, but the RCLK input probably only needs about 400nA of that (400uV p-p @ 1Meg input impedance = 400nA, @100k = 3.6uA )