USB-UART circuit - trying to understand ESD/EMI - Page 1
Forum section: electronics / projects

author: Christe4nM
author_rank: Unknown
timestamp: January 15, 2014, 02:43:42 pm
content: Hey all,I’m creating a small breakout board for an FT230XS USB to simple UART bridge IC. Instead of going for a straight and simple approach I took the occasion to dive a bit into circuit protection, ESD and EMI considerations. Unfortunately there is so much information to be found that I’m a bit lost on what is really necessary and most of allwhy.1) FTDI recomends a 27R in both D+ and D- data lines as well as 47pF to ground. I cannot find the reasoning behind this, since other sources suggest that you shouldn’t do anything to alter the impedance. The latter should be 90R differential. So why is this?2) If it's for filtering, then why are the caps placed closest to the connector instead of the resistors?3) Several sources recommend a ferrite bead in the USB_VBUS line, close to the USB connector. It should be resistive into at least 1GHz and between 47R and 1000R at 1MHz. Am I right to conclude this is for EMI reasons?4) Here I get confused: some sources make a difference between the signal ground (Pin5 on the USB connector) and the shielding ground. They place an R and/or a C between either, and TI even recommends a ferrite bead of 10R to 50R @ 1Mhz and resistive into 1GHz. Can anyone please explain why this is?5) Has the former anything to do with the bare copper ground strips surrounding some PCBs? Why are they there? EMI reasons, or as some say ESD reasons? From what I get they should be connected to chassis ground and there should be a minimum clearance to the signal and ground/power plane copper. Also there should always be an opening in the “ring”.6) There should only be one connection from signal to chassis ground right? Where do you make that one? There are several sources placing capacitors from signal ground to chassis ground. How does that work in the picture of above things?7) Finally, something completely different: the USB spec says that there should be ?10uF of capacitance on the USB_VBUS. Now, how do you decide the value of your main input capacitor? Why choose 4.7uF over 6.8uF or 3.3uF?Please shoot / comment anything you can find in my circuit. I’d like to get from copying datasheets and recommended layouts to understandingwhythey are recommended, so I can get to know what I’m doing.Thanks a lot.Sources:FTDI230X DatasheetFTDI Hardware Design GuidelinesIntel - HS USB Design GuidelinesTexas Instruments - USB 2.0 Board Design and Layout Guidelines

author: purloined_sirloin
author_rank: Newbie
timestamp: January 15, 2014, 10:05:49 pm
content: I'll do my best to answer your questions. Hopefully I don't steer you too far in the wrong direction.1) The 27ohm resistors and the 47pF caps form a filter. These effectively slow the rise time on these lines, reducing EMI. The resistors are kept low to avoid loading down the output of the USB IC.2) This is again related to the EMI filter created by the caps and resistors. Perhaps someone else can better explain the reasoning behind this.3) Yes, the ferrite bead is again another EMI filter. The ferrite bead and the 10nF cap in the attached schematic are to reduce conducted and radiated emissions on the VBUS line. These emissions are reduced further by the decoupling caps that should be placed near the IC.4) The purpose of decoupling the shield ground from your signal ground is to avoid excessive noise from your shield being coupled into your circuit. Power systems can be a bit noisy, and it's best to avoid bringing this excessive noise into your circuit.5) The bare copper you see on the outer edge of some boards is there for ESD purposes. When a board is handled, the typical place to grab it is the outer edge. This creates a contact point for a human or a machine, to bring the overall system to the same potential, reducing the change of an inadvertent discharge into a more sensitive component. This ESD ground should be separate from system ground, and typically is brought to an external pin that, if designed right, is the very first pin to make contact when plugging the device into something else, reducing the risk of discharge from other sensitive lines.6) Hopefully someone else can give a better guideline for this.7) I don't really know the reason behind the recommendation of 10uF of capacitance, though I'd assume this is based on reducing emissions on VBUS. I would imagine proper decoupling of your ICs would be more critical than trying to maintain 10uF of capacitance on this bus.As far as your circuit goes, it may help to improve your decoupling of VCC on the FT230x. Typical recommendations are to have several caps of different sizes as close to the pin as possible. 4.7uF, 100nF, 10nF, in parallel. Keep the distance from the pin to the caps short, to reduce the inductance of the trace.

author: purloined_sirloin
author_rank: Newbie
timestamp: January 16, 2014, 03:12:37 am
content: Sorry, had a brain cramp apparently.In regards to #2, its partially an ESD protection device as well. The cap will shunt some of the current to ground. That is why it's placed near the connector, and not the IC.

author: poorchava
author_rank: Super Contributor
timestamp: January 16, 2014, 12:01:04 pm
content: I doubt that 27R & 47pF will make any difference against ESD. Human Body Model test uses 150pF capacitor that is coupled to the DUT via 330ohm resistor. It's a common practice to use capacitors on the input for ESD protection, but typically nanofarad range values are used. V=q/C, so to reduce peak voltage by factor of 10, the input capacitor should be in the order of 1300pF, for the factor of 100, ~15nF.since that is a quite high speed data line, big capacitors are not a good idea. For ESD protection I'd use a TVS array of some sort. This link may be helpful:http://www.digikey.com/classic/documentredirector.aspx?doc=http://www.digikey.com/Web%20Export/Supplier%20Content/Wurth_732/PDF/Wurth_The_Protection_of_USB_20_Applications.pdf&curr=USD

author: luky315
author_rank: Regular Contributor
timestamp: January 16, 2014, 03:33:05 pm
content: 27Ohm can make a huge difference because they "help" the internal ESD-protection. 10Ohm in series roughly double the ESD-rating of the protected (CMOS) Device.And never forget that a resistor is never only a resistor. It has capacitive and inductive parasitics which in this case can be good.

author: Christe4nM
author_rank: Unknown
timestamp: January 16, 2014, 06:19:22 pm
content: Thanks purlioned_sirloin, poorchava and luky315 for tuning in, your replies helped me along while diving into it a bit further. I think I’ve got most of my questions answered. Here’s the summary:PowerThis USB device can be considered a ‘downstream device’ since it is either bus powered or self powered but not supplying power to VBUS. As such the ‘upstream device’ powering the bus should have over-current protection applied. However the USB specification says that the input capacitance / impedance of any downstream circuit should never exceed 10uF in parallel with 44R. The reason is inrush current. If greater capacitance is desired it should be behind a soft start circuit.Current draw of any USB device may not exceed 100mA when connecting, recovering from bus suspend or idle modes. Maximum current draw while operation is not to exceed 500mA. (Exceptions not taken into account). The inrush current may never drop the supply voltage by more than 330mV, and apparently this is one frequent reason for designs failing USB compliance test.This leaves my question of how to decide a capacitor value in general (not limited to USB): say you can choose any bulk capacitance you want. What are the deciding factors of going for 220uF, or 4.7 uF or any value. I know about decoupling capacitors and RC circuits and how to choose value / impedance there. But bulk capacitors have always eluded me. I think I will take this question into a separate topic though.Data line capacitance and resistorsIn answer to my questions 1) and 2): these are for edge rate limiting. According to FTDI’s hardware design guide these cannot be too large, otherwise the driver will increase current strength effectively defeating the intent of adding the capacitance. FTDI states their value between 0 and 47pF NP0/C0G depending on chip used and USB Full Speed or High speed. This capacitance differs from termination capacitance in that the latter is behind the termination resistors as seen from the connector.The resistors are for line termination. USB data+ and data- should be routed as a differential pair with 90R impedance. To achieve 45R single ended termination a little series resistance must be added to the termination resistance in the chip itself.Question: does anybody know if FTDI states the input impedance of the Data+ and Data- pins of their chips anywhere. I’ve been through their datasheets, but that value seems to be lacking in every single one I’ve seen. Unless I’m really overlooking something?EMIPresuming that the upstream (powering) USB device is correctly designed for EMI, and the cable is adequately shielded, there are three things to be taken into account.1) Edge rate, which can be limited with a little capacitance to signal GND at each data line.2) VBUS ripple and noise. Either coupled from the cable into the circuit or from the circuit into the cable. This is the reason for a ferrite bead in the VBUS line. A 10nF capacitance to signal or ‘voltage’ GND directly at the connector, before the ferrite bead should provide some extra filtering. The 100nF directly after the ferrite is for the same reason. This ferrite should be resistive into the GHz range. It’s value at 100MHz can be anywhere between 47R and 1k, depending on current.Question: how do you decide on ferrite bead value?3) Shielding noise. Since the USB cable’s shield can pick up noise, this should not be able to enter the subsequent circuit. Therefore it is recommended to separate cable and connector shield from the signal ground by means of either a capacitance, a ferrite bead or 0R DC path. It is advised to place footprints for either. The ferrite must again be resistive into the GHz range with 100MHz resistance between 10R and 50RESDBasically every application note and article shows a transient suppression diode directly following the USB connector. It’s capacitance must be taken into account for the data line capacitance. There are many TVS diodes available specifically for USB. TE Connectivity, Würth, NXP, LittelFuse, you name it and they’ve got a few.Well, I’m off to alter my circuit a bit with this in the back of my headExtra source:Guidelines for full-speed USB on NXP's LPC microcontrollersIntel EMI Design Guidelines for USB Components

author: fcb
author_rank: Super Contributor
timestamp: January 17, 2014, 11:52:05 am
content: Have you looked at the FT230X 'reference' design / dev. board.http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_UMFT230XA.pdfAlso, these aren't expensive and give you a pretty good point to start a design (I use them for proto's and the FT230X in a couple of products).

author: Christe4nM
author_rank: Unknown
timestamp: January 23, 2014, 08:25:02 pm
content: Well I've had some time to change my schematics and lay out a board. I deliberately went for a 4 layer stackup as I recon any design I'll do in the future incorporating USB will go on a 4 layer PCB. My idea is to order the board at OSHpark and experiment a bit with (not) populating parts to see what the difference in the time and spectrum is.One thing I'm not to thrilled about is the SLEEP# trace going over the gap between the voltage planes. However since that signal will only change in USB suspend mode and is only connected to a pull-up I thought it wasn't a big deal.If any of you'd take a look and comment you have my thanks in advance.@fcb. I didn't even think about that until I read your post. However I'm not after a quick FT230X board, but want to do the design myself. Those reference designs are usually minimalisticly done.Attachments:1) Revised schematic2) PCB Top layer (+ components and silkscreen)3) PCB L3 (power) and L4 (Bottom). They overlap for about 90% I think4) 3D view

author: fcb
author_rank: Super Contributor
timestamp: January 23, 2014, 09:58:37 pm
content: Quote from: Christe4nM on January 23, 2014, 08:25:02 pmYup. That's the point.

author: Russ.Dill@gmail.com
author_rank: Contributor
timestamp: January 23, 2014, 11:12:15 pm
content: This a a full speed (12Mbps) device. You can get away with murder on this layout.

author: free_electron
author_rank: Super Contributor
timestamp: January 24, 2014, 02:19:12 am
content: you got some of the idea's right, some wrong and then there is 'fuzz' generated in this topic as well…[1) FTDI recomends a 27R in both D+ and D- data lines as well as 47pF to ground. I cannot find the reasoning behind this, since other sources suggest that you shouldn’t do anything to alter the impedance. The latter should be 90R differential. So why is this?this rounds off the edges and eliminates overshoot and ringing caused by the cabling. the resistors should be around 12 to 27 ohm. making the resistors larger will give problems with drive strength and may cause the driver to pump up the strength making the problems worse again.using too large capacitors will round off the edges too much and close the eye creating bit errors.Quotebecause it is the cable causing the problem. the long usb cable is a lumped network that has inductance (amongst others) this causes the problems. putting the filtering at the connector prevents it from radiating all over your system. filter the signal as close as possible to the connector.Quotethis is to block conducted EMI. the power coming form the computer may be 'noisy'. this can be a very wideband signal. putting a ferrite bead at the connector stops this conducted emi from entering your system where it could become radiated emiQuotethis one is a bit more complex to explain. USB has a 4 wires + a shield. d+ and d- are the data pair , vbus and GND are the power and power return. the shield runs around those.The shield is a solid foil wrapped around the data pair and power pairthe data pair is a twisted pair (for anything faster than low speed) . the power and ground pair is plain , but can be twisted. the two bundles are then again wrapped in a metallised foil with a leader wire and or braided outer jacket.here is what is going on : the braided out jacket is only connected to the metal sleeve. if you take a USB cable ( a real one) there should be no electrical connection between the metal sleeve and the ground pin. the metal sleeves on both ends are connected together through the braid.ther eis two things at play :1 : EMI : the power (red wire) has a return path (black wire) so all electrons going in red , return in black. this allows you to do common mode filtering on the power rails.2) ESD : any 'zap' striking the cable will flow into the braided shield and be deviated to the sleeve of the connector.on both ends this sleeve should be connected to the power earth or chassis earth. yo do want to maintain a DC operating point of zero between ground and the sleeve so you put a ferrite bead between the power ground and the sleeve ground.the sleeve ground is to be electrically connected to the metal chassis in the computer and the device. there should be a galvanic connection to the ground pin of the power plug.this is a bit difficult ot describe in words.. i will try to make a small video to explain how this works and what the principles are. i believe i posted a drawing once here on the forum that shows the current loops.Quoteboth. the bare copper ring is to attract ESD zaps. the ring shoudl be positioned at the cirumference and be void of soldermask or silkscreen. this ring works if a plastic case with vents is used. during esd testing arcs may shoot into the shell and will be attrackted by this bare earth ring. it is important that this ring is connected galvanically to building ground. there should be no AC connection between this ring and the system ground. ( aferrite bead between them blocks the AC but lets DC pass. arcs are very high rise time events so they are blocked by the ferrite bead and the energy is forced to be disperesed in the chassis ground and will not enter system ground. again this is hard to explain in words. we need a drawing … )Quoteas close as possible to the connectors and the chassis bonding point.If you use a plastic that is non metallised then the bonding point is irellevant. the connection should be at the connectors.if you use a meatlassed plastic case or metallic case then you need ot see where the bond screw will be. you want to put the ferritse close to the bond screw to block the energy there.Quotenot true. the PERCEIVED capacitance should be max 10uF at plugin. this is to reduce the charging peak when a device is being plugged. you need to look at the peak currents. a 10uf ceramic cap will draw a much largerinrush current than a 10uf electrolytic one.general commentsyour common mode choke needs to sit BEFORE the diode protection circuitry.now you have connector - diode bridge - common mode choke. it should be connecotr , common mode choke , diode bridge.now, you are throwing in too much stuff. the common mode chokes typically do a good job of protecting the datalines.i would advise agains havng and the coke and the diode protector and the series resisors + caps. that is overdoing it and you will cause bit errors, especially at full speed.i typically use a usb6b protection device where you run the pins through the body. it has enough stray capacitance to filter the edges and it will absorb esd events without problems.it is IMPORTANT that there isa local decoupling cap between the USB6B power and ground rail !the ESD energy needs to be able to be shunted , otherwise it will inject into the power rail and may cause a single-upset event there.i will try to explain this in a small video.i changed your schematic- FB1 shoud NOT be there. you need DC and Ac connection on the gnd there. this is your system ground. it is the CHASSIS grond (comong form pin 6) that needs to be blocked on AC toward the system ground so FB3 is the correct position.you dont need the 4k and c11. c11 may be needed if you have very large ESD pulses that get into your system. but this will kill EMI…. ( C11 undoes the blocking provided by FB3 … )i drawn a cap between pin 5 and pin 2 of the usb 6b. this one should be placed directly there before being connected to ground.do NOT place this cap on the bottom layer !!! and do not use any vias in the connections from cap to devicesee my layout suggestion the ground via should be where i have drawn it. this via feeds the ground for your system.doing it this way forces esd currents through the 100nf before it can hit the system ground.

author: jmaja
author_rank: Frequent Contributor
timestamp: January 25, 2014, 07:40:54 am
content: Quote from: free_electron on January 24, 2014, 02:19:12 amFB1 was between 47pF and 100nF capacitors to GND. What's the difference between these two caps in ESD events (without FB1). How does the current divide between the caps and TVS diodes? Aren't the TVS diodes enough by themselves?Then I have a separate question related to EMC. How should GND and chassis (mains earth) be dealt with in a system which needs to have floating GND, VCC and datalines. It is powered by floating DC from remote supply and has RS422 connection (optoisolated on the other end). The device is inside an aluminium enclosore, which is bolted to earth. The whole PCB is isolated from the enclosure. Obviously there can't be any FB between GND, but should there be caps or big resistors?

author: Christe4nM
author_rank: Unknown
timestamp: January 25, 2014, 06:07:03 pm
content: Vincent, thanks for tuning in. A quick reply trying to get my head around it.Quote from: free_electron on January 24, 2014, 02:19:12 amYep, I think you meanthisone. I tried to take your info from that post into my design. Apparently I didn't get it right yet. In that picture you actually show a cap in parallel with 4k7. I'm a bit confused as to when to choose which configuration for what reasons. Could you maybe elaborate a bit?How do you choose the value for the cap? Is voltage rating at 1kV adequate?Quote from: free_electron on January 24, 2014, 02:19:12 amIn your post linked above (the one with the ESD zap figure) you mention the CM choke. On the other hand the Intel appnote says to leave it out unless really needed for EMI compliance. So to choke or not to choke?Quote from: free_electron on January 24, 2014, 02:19:12 amWow, I realize that I actually have no idea how to choose a (bulk) cap in value, and type (also beyond this USB circuit) Maybe I should open another topic for that but maybe you would want to point me in the right direction? I do know about voltage derating, impedance curves, inductance at high frequencies (e.g. why a 100n bypass cap does nothing at high frequency circuits). However how to decide on a 'simple' bulk capacitor either local or 'global' I just don't really know.

author: stefanh
author_rank: Contributor
timestamp: June 16, 2015, 06:35:59 am
content: This is the official FTDI app note which shows the placewment of ESD devices.http://www.ftdichip.com/Support/Documents/AppNotes/AN_146_USB_Hardware_Design_Guidelines_for_FTDI_ICs.pdfThis app note also shows that the placement of the common mode choke and ESD devices.http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 16, 2015, 11:42:44 am
content: Ugh...Ground everything. If you can't DC/galvanically ground it, use caps for RF grounding. If line-to-ground isolation is required, use Y1 type capacitors. That's what they're there for.I wince every time I see a ferrite bead in a ground path. Almost all of the time, itwillfully makes the signal worse. It's one of the worst mistakes, and so often repeated because no one ever gets a chance to test it. There's an awful lot of misinformation about EMC.BTW, common mode filtering is somewhere between "nearly useless" and "impossible" on USB, because of two things:1. There is no common mode terminating impedance. The receiver is fully open circuit, by design.2. The USB standardrequiresnormal-mode (unbalanced) symbols for line negotiation (start of packet, etc.).Because of 1., you can't get any attenuation, even from a very large value CMC, because there's no terminating impedance. Because of 2., even if you achieve good common mode filtering, you fuck up the start-of-packet symbols, and the whole thing breaks.The 27 ohm resistors (actual value varies by manufacturer and process, from zero external required, up to 47 ohms or so) serve to terminate the line. USB is a source terminated topology, only. The pin drivers (for up to Full Speed configuration) are standard boring 3.3V CMOS pin drivers, with an Rds(on) equivalent around 30 ohms (with a fairly wide error band, because of IC process inconsistency). The rest has to be taken up by external resistors, which are accurate enough to ensure a good enough match.So, the capacitors are not there to address line ringing -- in fact, the resistors are. Indeed, USB is perfectly capable of driving lines of an electrical length much longer than the baud rate (i.e., the next symbol is entering the cable before the previous symbol(s) have reached (and potentially reflected off) the far end!). This is made possible by source termination.The additional resistance does, however, afford some opportunity to filter, so that some RFI can be attenuated. The minimum analog bandwidth required for USB 1.1-compatible (Full Speed) is about 30MHz. A pi filter is preferable, but inconvenient from discretes, so not usually used. (A "CR" filter is undesirable because the line-facing capacitors (if present on both ends) merely bottle up the higher frequency energy without dissipating it; and an "RC" filter is undesirable because the direct C loading on the transmitter causes more peak supply current without achieving much filtering. A "CRC" (pi) filter is a modest compromise between both cases, and works the best in both directions.)The capacitance has no impact on the ESD rating. Two reasons: 1. IEC 61000-4-2 uses a 150pF capacitor charged to rated voltage; a 47pF capacitor could only achieve a 25% reduction in peak, which isn't much (it's still friggin'kilovolts.. and now it's from a total 200pF, so what have you even accomplished?), and 2. whatever ends up clamping the pulse (IC protection diodes, TVS device, device breakdown, arc through air..), will be a dynamic impedancemuchlower than the effective reactance of the capacitor, so that tiny capacitor still won't do anything. Once it charges to that breakdown voltage (10V? 100V? 1000V?), all the rest of the current (still pretty much the full ~10A peak!) goes into the clamp.There are data line "filter and TVS" components available, which handle both of these very nicely.For High Speed (USB 2.0), you don't have as many options, because the analog bandwidth is large (>200MHz) and the tolerable capacitance is small. Merely providing ESD protection is a challenge. High speed interfaces therefore need even more emphasis on strong grounding and shielding practice!The best method for wiring USB is:- Place the shielded connector directly over ground plane- Ground all shield and grounding pins available- Bypass +5V to GND with 0.1uF or more- Optional: follow the +5V with a FB, or better, a series ~1uH inductor, to the remainder of circuit- Use a bypass with modest, known ESR. This should match to the anticipated line and/or filter inductance, if possible (ESR ~= sqrt(L/C)). Value is not important, a few uF would do. It should also be a surge-tolerant type, e.g., ceramic + resistor or electrolytic, not tantalum (though tantalum are often seen in this application anyway).- If on the USB Host side, a power controller should be used, to limit load current to 500mA and provide an electronic fuse (thermal limit - auto retry - fault detect - etc.) function.- Data lines should be run into a CRC+TVS filter/protector. If you're feeling cheap, you can leave it to the USB IC itself, using the specified resistors and nothing else. If resistors are specified, don't skip them.What this does:- Any common mode noise on the cable, as a whole, is conductedoveryour device's ground. This is extremely important to understand. It isnot feasible to attempt to attenuate (with CMCs) the high voltage and wide bandwidth of ESD or EFT type interference.It must be weathered by your device, shunted around it on a solid ground plane, or better, around a solid metal case (which is why they usually provide contact fingers on the connector housings).- Any common mode noisewithinthe cable, e.g., between +5V/GND and shield, is shunted to ground at your circuit.There ain't no common mode if we just reflect all that shit back to the source!That's also why it's important to have the +5V filtered near the connector.- Any common mode noise left over, on the data pair, is whatever you're stuck with. If it exceeds the logic input threshold of the receiver (i.e., VCC/2, give or take), you're screwed. Hopefully, by shunting to ground everything near the pair (which has been coupled to the pair for, well, the entire length of the cable), we can at least have some hope of keeping that noise voltage as low as possible.- Any other signals in your circuit are fine (well, unless they go out on cables too, but that's the point in the first place). How? The ground plane acts like a Faraday cage. The enclosureisone (if present). Traces intertwined with, and referenced to, the ground plane, are very much safer than anything hanging out on a wire!If your circuit needs to be isolated from chassis and/or safety ground: fine. But you can't escape the RFI grounding.And anyway, what are you talking about? If you're talking to USB,you aren't freaking grounded!Youcannottalk USB without being on common ground! The interface IC must have VCC/GND at the same potential, AC and DC.If therestof your circuit needs to be isolated, it's up to you how you want to address that -- optoisolators on a simpler protocol (UART/SPI?), logic isolators (opto, magnetic or capacitive?), or go heavy weight on the USB itself (e.g., ADUM3160). Whatever you do, the stuff around the connector still needs its own local shielding and ground plane layout.If you wanted isolation, and a high speed data interface, you should've chosen something like Ethernet, which is transformer coupled. If your alternative is putting isolators on everything... it may still be worthwhile to just, go all the way back to the drawing board, and redo all your signaling concepts. Huge PITA I know, but you can't argue with electromagnetism; such is the price of ignorance. It happens.--------Related trivia: how much unshielded length makes a difference? It only takes an inch.Think of it this way.Suppose you have a cable, which has a 1kV pulse induced upon it. (It might be from nearby ESD, it might be switching noise from motors, it might be that damned Chinese SMPS that has no filtering whatsoever. Whatever it is, it's out there, and you need to think about what it can do.) The pulse is fast (~nanoseconds), and propagates along the cable at the speed of light. The common mode impedance of the cable is in the 50-200 ohm range (depending on height over ground plane). It's a high impedance -- you can't just stack up ferrite beads, because they're maybe 100s of ohms at a time. You'll smear out the pulse, but not eliminate it.The signals inside the cable don't know what's going on outside the cable. Common mode signals travel along a shielded cable, independent of the internal voltage differences -- that's why shielding works.Now the cable, and the pulse, enter your circuit. Suppose your circuit uses a panel-mounted USB connector. It's mounted in plastic, and not grounded to the enclosure. A cable goes back to a 1x5 pin header on the main board (this could be a PC motherboard!). That cable hardness is also shielded up to the header, but where the wires enter the header, the shield separates from the signal lines.One inch of unshielded length.What's the inductance of that inch? Maybe 20nH.No more than about half of that is going to be mutual with the data lines. Mutual inductance saves you, because anywhere the fields around the wires are held in common (like, within a shield!), they're all none-the-wiser.How much voltage drop are we talking? A ~ns pulse has broad bandwidth, but specifically for IEC 61000-4-3 (electrical fast transients), the risetime is 5ns and the pulse width is 50ns, so it has energy up into the low 100s of MHz. Let's say for argument's sake it peaks at 500V and 50MHz (the rest of the 1kV peak is made up of other frequencies nearby, which "sharpen" the 50MHz peak, and flatten it out into a single pulse rather than disperse repeating waves).At 50MHz, 20nH has a reactance of 6.3 ohms. We have the characteristic impedance of the cable, dividing into 6.3 ohms, or about (500V) * 6.3 / (100 + 6.3) = 30V. That's 30V generated across that one inch of shield wire.That's 30V that'snotgenerated across the data pair. Our USB receiver is on a 3.3V supply, and its logic thresholds are around 1.5V at best.Oh fuck.You can't add a ferrite bead here -- if you put it around the whole cable, you're trying to block ~kV, which is futile. If you put it around the data pair, you have no common mode terminating impedance to work against -- again nothing. If you put it around the shield wire, you increase the 20nH to ~1uH or more, which is obviously much much worse!If the data lines are "between" the power and ground (say the pinout goes +5V, D+, D-, GND, SHIELD), you can get some advantage from AC-grounding the supply pins. This is why bypass and direct grounding of those helps. You gain the mutual inductance of those wires against the data pair, so now your uncoupled inductance might be only 10nH, or 5nH even. But it's still not zero, it's not perfectly shielded. But at least you might've increased the EFT tolerance from a pitiful 200V, to 300 or even 500V. It's not passing 1kV, but it's a start.For extra credit: imagine what happens if the interference is a high peak power 900MHz or 1.2GHz radio (it might be only ~10V induced on the cable, but the frequency is higher!), and the USB receiver is High Speed (little to no filtering).Tim

author: ironcurtain
author_rank: Regular Contributor
timestamp: June 18, 2015, 01:59:11 am
content: Subscribed!I'm designing a RF/EMI friendly USB hub for SDR purposes and this has quite some interesting tidbits. I don't want to hijack the thread, though.