Advanced FPGA design resources - Page 1
Forum section: electronics / general

author: filssavi
author_rank: Frequent Contributor
timestamp: March 14, 2017, 05:19:47 pm
content: Hi since I'm planning on using an fpga for my next project, I'd like to learn about commonly used Digital/FPGA architectures/techniques.I'm familiar with the basics of digital design, pipelining etc, but i'm finding myself often searching for solution to what are pretty common problems, like for example configurable dynamic routing from multiple I/O's to a specific block inside the FPGA.what are your advices for books/papers or otherwhise learning material

author: rstofer
author_rank: Super Contributor
timestamp: March 14, 2017, 06:07:51 pm
content: Xilinx has a massive library.I just picked this document by searching Google for 'xilinx routing':https://www.xilinx.com/support/documentation/white_papers/wp381_V6_Routing_Optimization.pdfYour topic is way above my paygrade. I let Xilinx figure out the routing. The only time I care about placement is when I need to know where specific BlockRAMs are located. This only comes up when I want to use data2mem to create an initialization file.https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/data2mem.pdf

author: hamster_nz
author_rank: Super Contributor
timestamp: March 14, 2017, 08:59:32 pm
content: I have never found a good understandable resource for learning Timing constraints - which should remove any need to manually route anything except the most exacting of designs.I know the words, I understand the concepts, but I just don't get it.If you find one, let me know.Mike

author: laugensalm
author_rank: Regular Contributor
timestamp: March 16, 2017, 03:37:50 pm
content: Hi,I found the Synopsys Suite (coming with Lattice Diamond) quite helpful in identifying problems. There's also a user guide on timing constraints with Synplify Pro which I found helpful. For the hard cases though, you'll have to get down to the actual FPGA technology elements and find your way using fuzzy knowledge. I found - at least here in Europe - that the experts in those fields like to sell courses rather than books.So, my advice would be: Just start playing and use to tools to find out what's actually happening "inside". In most cases, you won't hit the roof with timing issues anyway, unless you're doing video I/O or Gigabit communication.

author: nctnico
author_rank: Super Contributor
timestamp: March 16, 2017, 03:46:06 pm
content: Quote from: filssavi on March 14, 2017, 05:19:47 pmJust write VHDL and let the synthesizer deal with it. Based on the FPGA's architecture it will decide the best option. Xilinx has a manual which describes the way VHDL constructs are translated into FPGA primitives and thus provides hints on how to create VHDL which translates to the most efficient solution. I really wouldn't go into placing primitives myself because that is tedious and probably won't make the design any better.

author: mrflibble
author_rank: Super Contributor
timestamp: March 17, 2017, 06:57:53 am
content: Quote from: hamster_nz on March 14, 2017, 08:59:32 pmThe "Timing closure user guide" (UG612) from xilinx is reasonably doable. I'll admit that it is no tutorial, but all the required bits are in it.Anyways, the main thing is:- for every clock domain you make a rule (just a 1-liner) that says that all flip-flops in this domain should obey setup/hold requirements for that clock.- for every dual flip-flop synchronizer between clock domains put a TIMING IGNORE on it, because meta-stability,weeeey!If you don't have fancier clock domain crossings or multi cycle paths in a pipeline or ddr memory or something, then that's about it really.As soon as you want anything more, the xilinxness of the software starts to surface. It is soooo easy to make a small mistake in syntax ora mistake in how you thought you should specify a flip-flop's location in the hierarchy. You thought you correctly specified the target flip-flops that you want to constrain...No huge error messages, so all is well, right? WRONG! It will gleefully and silently ignore your constraint on that non-existing signal. So now your actual signalis unconstrained and the place & route is totally free to fsck things up for you.During the learning curve I've flushed quite a few hours just because of that.Basically what I am trying to say is this: Assume that EVERY single constraint you specified went horribly wrong. After place& route go over the entire timing report, and check anddouble check if you can findallthe signals that you tried to constrain. And after you've done that a few times and get sick of it you write a perl script to check things for you.Or nowadays that would be a python script.As for the OP's mention of"pretty common problems, like for example configurable dynamic routing"... Mmmh, if you really do mean dynamic reconfiguration, then I would saythat doesn't really qualify as all that common. The number of designs without dynamic reconfiguration far outnumber those with. It's not exactly rocket science, but if you just startedmessing with FPGA's I'd steer clear of dynamic reconfiguration for the first few projects.But if you insist, just google "xilinx dynamic reconfiguration" or "xilinx partial reconfiguration" to check ifthat indeed is what you want to use.And I fully agree with nctnico's comment (minus a small typo). Just write Verilog and let the synthesizer deal with it.

author: nctnico
author_rank: Super Contributor
timestamp: March 17, 2017, 07:28:20 am
content: Quote from: mrflibble on March 17, 2017, 06:57:53 amNo, that is not it. You will need timing constraints on the input pins to the flip-flops and from the flipflops to the output pins. If you leave these out you can get in a whole lot of trouble because a signal may be routed through a whole lot of FPGA fabric before reaching the flipflop or output. Xilinx also allows to specify setup and hold times which can make life a whole lot easier especially on a device which has adjustable delays in the IOBs (Input Output Block).

author: mrflibble
author_rank: Super Contributor
timestamp: March 17, 2017, 08:01:10 am
content: Quote from: nctnico on March 17, 2017, 07:28:20 amNow you just spoiled a perfectly fine attempt at encouraging the new-to-fpga's guy.I also neglected to mention things like IODELAY2 (hence the "or ddr memory or something") or messing with PLL's that should start properly but don't just because, ... or or or. Anyways, I stick with my original statement, 100% with the logic evaluation of the "if"'s in there. For the cases you mention the"If you don't have fancier etc."clause resolves to false, hence you donot"not need more", so for that case you may or may not need more. No need to make things more complicated than it needs to be for a first project.And you will indeed need IOB's for the IO pins, but those are placement constraints and IO standard directives. And for a simple design the timings on the IOs are taken care of by the boring uninspiring list of 2 items. Synchronizers, since it's simple, robust, and you can get away with it due to the low IO speed in the simple project. And after it's synchronized it's in whatever boring clock domain, in which it stays with the boring not-super-performant but decent logic that only requires the boring onliner for the FFs in that clock domain. I thought we were talking about the timing part of the constraints, since those (IMO) are usually the trickiest part of constraints for a given design.If you use DDR FFs or a serdes, then you'll definitely need more constraints, no argument there. And totally agreed on the adjustable IOB delays making life a lot easier. Heh, I just realized that those delays are calibrated by (if I remember correctly) a ring oscilllator. Which incidentally is also what is used during dynamic reconfiguration. So now we are thematically back full circle to the OP.PS: I just realized I just should have said"yeah, you are right. If more complicated then more complicated". Oh well, that's one for next time.I blame this coffee!

author: Daixiwen
author_rank: Frequent Contributor
timestamp: March 17, 2017, 08:15:51 am
content: For information about timing constraints of Intel/Altera FPGA designs there is this unofficial guide which I find more practical than the official user guide:http://www.alterawiki.com/wiki/TimeQuest_User_Guide