BGA on JLC 4L - Page 1
Forum section: electronics / general

author: ResistorsAreFutile
author_rank: Newbie
timestamp: May 31, 2020, 08:46:15 pm
content: Hi everyone,In the past I've designed and built several boards using FPGAs in QFP packages without problems, but many of the newer parts are BGA only so I've been looking to use BGAs in future.I normally use JLC for fabbing PCBs so my question is, is it possible to break out a 1.0mm or 0.8mm BGA on JLC's 4L process? I've seen references to people doing this, but JLC's quoted minimum 0.54mm pad to track gap would appear to make it impossible. Or am I misreading their capabilities?Thanks!

author: JLCPCB Official
author_rank: Regular Contributor
timestamp: June 01, 2020, 08:55:52 am
content: For 1/2 layers and 4/6 layers, the minimum distance between BGA is 0.127mm. And minimum pad to trace space is 0.127mm so you can breakout 1.0mm or 0.8mm BGA without problems,

author: Yansi
author_rank: Super Contributor
timestamp: June 01, 2020, 09:18:16 am
content: I wrote them an email about this exact thing, as the 0.54mm being incorrect.On 21.5.2020 I got an response (from Mr. Patrick He) that they repair it ASAP, and it seems it did not happen since.He wrote me following:QuoteWhich I am still not sure what does that mean exactly.Also, their new spec of via-to-track 0.254mm seems suspiciously strange, as I have in the past manufactured PCBs violating this rule. PCBs always manufactured to spec with no issues.Seems like when they updated their webdesign, someone did a LOT of mistakes copying the numbers.

author: Yansi
author_rank: Super Contributor
timestamp: June 01, 2020, 09:33:32 am
content: I think that both of these numbers are incorrect and I am also waiting for them to correct these.Both of these new specs definitely prevent you from using a 0.8 pitched BGA, and probably even 1mm pitched one.According to my current DRC file, via-to-track should be 6mil (0.127mm) or better, not the current (10mil) 0.254mm.And pad-to wire should also be definitely 6mil or better.Otherwise you could barely run a 6mil trace in between SOIC pads!

author: asmi
author_rank: Super Contributor
timestamp: June 01, 2020, 12:23:43 pm
content: Check the project in my signature. It's an open source 4 layer FPGA board specifically designed for JLCPCB 4 layer process, it's got 1 mm pitch FPGA with 0.8 mm pitch DDR2 memory onboard. I've assembled the board to confirm that everything works, and it does work 100%.

author: Yansi
author_rank: Super Contributor
timestamp: June 01, 2020, 01:55:08 pm
content: I am also sure 0.8 and 1.0 BGAs can be done with JCL, I have seen it done before and I have myself used such DRC rules that allow it on previous pcbs.What I want is them (JLCPCB) to either correct their DRC values on their new web page or clarify, if they in fact lowered the precision by that much.

author: ResistorsAreFutile
author_rank: Newbie
timestamp: June 01, 2020, 09:06:44 pm
content: Yes, that .54mm figure really should be corrected. It's extremely confusing.Big thanks for the help, everyone. Looks like I'll be spending some time doing BGA fanouts...

author: JLCPCB Official
author_rank: Regular Contributor
timestamp: June 03, 2020, 05:48:17 am
content: Hello All ;Please to consider the reply posted by the JLCPCB team here.We will update the values ASAP.For the moment, the minimum clearance for multi-layer PCB when using BGA is 0.127mm spacing pad to track and 0.127mm pad to pad.SOLVED

author: c64
author_rank: Frequent Contributor
timestamp: June 08, 2020, 01:04:25 am
content: Quote from: JLCPCB Official on June 03, 2020, 05:48:17 amWhat about trace width and spacing? JLCPCB says 5mil for all boards herehttps://jlcpcb.com/capabilities/CapabilitiesAnd here they say 3.5milhttps://cart.jlcpcb.com/impedanceHere they saywww.sz-jlc.com5mil for 2 layers and 3.5mil for multilayer. I assumewww.sz-jlc.comand JLCPCB is the same factory?

author: JLCPCB Official
author_rank: Regular Contributor
timestamp: June 09, 2020, 03:16:27 am
content: yes, we are ONE company, which JLCPCB aims to provide service for the foreign market. However, the parameter settings are the same, 3.5 mil for multiple layers, 5 mil for 2 layers, no difference, we will update the detail soon. You know us very well,. Nice catch!