FPGA register file warnings, not connecting MSB + bonus question - Page 1
Forum section: electronics / general

author: pigtwo
author_rank: Regular Contributor
timestamp: July 06, 2013, 03:55:54 am
content: Hello everyone!I've just started learning about FPGA's and I bought a Nexys 2 board( has a Spartan-3E ) and now I'm a little stuck.I'm going through one of the exercises in my book and the basic idea is this: There are 4 seven segment displays but you want to display more data on them by having the values scroll by(IE if you want to display the number '123456', the display would read '1234' then '2345', '3456','4561', ect). I want to be able to change the direction it scrolls, pause it, and change the data that is scrolling. I tried to do this by setting up a register file, then having an index(or address) iterate through the register file while shifting everything to the left/right.I have the 7-seg multiplexing tested so I know that works. The first problem is that I get a few warnings:Code:WARNING:Xst:647 - Input <wrAddress<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:2677 - Node <nextIndex_2> of sequential type is unconnected in block <scroller>.WARNING:Xst:2677 - Node <index_2> of sequential type is unconnected in block <scroller>.WARNING:PhysDesignRules:367 - The signal <wrAddress<2>_IBUF> is incomplete. Thesignal does not drive any load pins in the design.WARNING:Par:288 - The signal wrAddress<2>_IBUF has no load. PAR will not attempt to route this signal.WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /clock site pair. The clock component <stop_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y10>. The IO component <stop> isplaced at site <IPAD68>. This will not allow the use of the fast path between the IO and the Clock buffer. This isnormally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <stop.PAD> allowing your design tocontinue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this overrideis highly discouraged as it may lead to very poor timing results. It is recommended that this error condition becorrected in the design.WARNING:Route:455 - CLK Net:counter<24> may have excessive skew becauseWARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.WARNING:PhysDesignRules:367 - The signal <wrAddress<2>_IBUF> is incomplete. Thesignal does not drive any load pins in the design.From what I can tell it thinks that the MSB of wrAddress(the address used to write to the register file) is never used. Upon looking at the RTL schematic, the register file is only given a 2-bit address when it should be getting a 3-bit address. All of this is confirmed when I actually run it on the board. The part where I use wrAddress is near the bottom in the default portion of the case.I'm not sure why it's not connecting the MSB of wrAddress. Here's the code. I tried to comment it as much as possible but I'm still very new so I'm not sure what is the best way to comment an HDL.Code:`timescale 1ns / 1psmodule scroller(input wire clk, stop, direction, write,input wire [2:0] wrAddress,input wire [3:0] value,output wire [7:0] sseg,output wire [3:0] an);// Internal defintionsreg [3:0] regFile[2:0]; // Holds the datareg [2:0] index;// Index for the datareg [2:0] nextIndex;// I don't now why this needs to be a regreg [24:0] counter;// Used to create a slower clock ratewire [24:0] counterNext;wire slowClk;reg enable;// Enables movementwire enableNext;reg [3:0] reg0, reg1, reg2, reg3; // Registers that will be displayed// Get a slower clockalways @( posedge clk )begincounter <= counterNext;endassign counterNext = counter + 1;assign slowClk = counter;// Make index increment/decrementalways @( posedge slowClk )beginindex <= nextIndex;endalways @( posedge clk )beginif ( direction )nextIndex = index + 1;elsenextIndex = index - 1;end// Make button act as a JK flip-flopalways @( posedge stop )beginenable <= enableNext;endassign enableNext = !enable;// Make the numbers move left or rightalways @( posedge clk )begincase ( {enable, write} )2'b00:begin// Disabled and NOT writingreg0 <= reg0;reg1 <= reg1;reg2 <= reg2;reg3 <= reg3;end2'b10:begin// Enabled and NOT writingif ( direction )beginreg0 <= reg1;reg1 <= reg2;reg2 <= reg3;reg3 <= regFile;endelsebeginreg3 <= reg2;reg2 <= reg1;reg1 <= reg0;reg0 <= regFile[index - 4]; // Four is subtacted from the index to get it to correct location when moving in the other directionendenddefault:begin// Enabled and writing/Disabled and writingregFile <= value;endendcaseend// Display regsdisplay_mux unit1(.clk(clk), .d0(reg0), .d1(reg1), .d2(reg2), .d3(reg3), .an(an), .sseg(sseg), .reset(1'b0));endmoduleBouns: Another problem I am having on it is that instead of displaying '1234' and rotating that around, it displays '1111', '2222','3333', ect.Any help would be really appreciated. I know how annoying it is to look though other, especially new, people's code.Also, if you see anything stupid I'm doing feel free to tell me. I'm still very fuzzy on a lot of things.

author: codeboy2k
author_rank: Super Contributor
timestamp: July 06, 2013, 07:59:30 am
content: >> WARNING:Xst:647 - Input <wrAddress<2>> is never used.. because this line below definesregFileas an array of registers, each register is 4-bits wide (the [3:0] part) and there are 3 elements in the array (the [2:0] part)reg [3:0] regFile[2:0]; // Holds the dataThose numbers in the array size specify a [maximum:minimum] for the array, and not a size in bits like for reg.And now, because there are just 3 elements in the array, when you write this line here :regFile <= value;you are coercing the 3-bit wrAddress to an integer for addressing the array of 3 elements, so it only needs the lower 2 bits for that. Thus wrAddress<2> is not needed and not used.This automatic type coercion is one of the things I don't like about Verilog, and it's easy to make mistakes like this. VHDL wouldn't let you make this kind of mistake.For an array of 8 4-bit registers, make that:reg [3:0] regFile[7:0]; // Holds the dataThis gives you regFile, regFile, regFile, ...., regFile

author: pigtwo
author_rank: Regular Contributor
timestamp: July 06, 2013, 04:04:28 pm
content: Ah thank you! I'm not sure why I thought you would define the number of address bits instead of the number of registers.

author: free_electron
author_rank: Super Contributor
timestamp: July 06, 2013, 05:46:40 pm
content: Quote from: pigtwo on July 06, 2013, 03:55:54 am

author: pigtwo
author_rank: Regular Contributor
timestamp: July 06, 2013, 06:33:34 pm
content: Thanks free_electron, that actually clears up a lot. For some reason I didn't think you could just go:Code:counter <= counter + 1;That makes it a lot easier to write.

author: mrflibble
author_rank: Super Contributor
timestamp: July 06, 2013, 11:10:31 pm
content: While we're at it ...Code:counter <= counter +1'd1; // prevent useless size mismatch warningAnd I noticed this:Code:// Get a slower clockalways @( posedge clk )begincounter <= counterNext;endTogether with the ever popularCLOCK_DEDICATED_ROUTEthat tells me you are using this counter to generate a slower clock. You might as well get out of that bad habit right now, and NOT use logic outputs (your counter output in this case) as a clock signal.Either use a DCM/PLL to generate a divided clock, or use clock enables. Plus as extra bonus points, when you use clock enables you don't have to worry about multiple clock domains...