Select input using buttons.  - Page 1
Forum section: electronics / beginners

author: SmurfKiller
author_rank: Contributor
timestamp: April 27, 2017, 05:34:42 pm
content: Hi all, I was trying to find a way to use push buttons to select an input. Its for a clock circuit for a 8-bit computer i am building, being i computer science student, i though it would be a great way to get deeper into the inner workings of a PCSo, i have a clock generated by a 555 timer, and a manual clock button. How would i go about using 1 or 2 buttons to toggle which clock i would like to use?I have tried to google around, but i don't think i am using the best search terms, i just keep finding information on audio input selectors, which seem a little complicated for what i am trying to achieve.Any advice or examples would be greatly appreciated, or a nudge in the right directionThanks.

author: ironmonkey
author_rank: Contributor
timestamp: April 27, 2017, 06:04:19 pm
content: Maybe are you looking for something like this? :

author: SmurfKiller
author_rank: Contributor
timestamp: April 27, 2017, 06:30:35 pm
content: Yeah, i was looking at something like that.. But i was thinking something more along the lines of a "soft latch" sort of thing, so using buttons not switches. Hope that makes sense.

author: james_s
author_rank: Super Contributor
timestamp: April 27, 2017, 06:39:46 pm
content: You can make latches out of flip flops, then use the outputs of those to gate your clock signals.

author: ironmonkey
author_rank: Contributor
timestamp: April 27, 2017, 06:40:00 pm
content: Then in that case use a jk as a divider by 2. Feed the jk clock with your clock selection pulser and feed one AND input with the Q output instead of the swithch-resistor. Do so with the another AND replacing the switch resistor input with the negated QEnviado desde mi MotoG3 mediante Tapatalk

author: Kleinstein
author_rank: Super Contributor
timestamp: April 27, 2017, 06:46:32 pm
content: Mechanical switches usually need debouncing before using them as a clock or for a toggle flipflop.

author: SmurfKiller
author_rank: Contributor
timestamp: April 27, 2017, 06:56:52 pm
content: Quote from: ironmonkey on April 27, 2017, 06:40:00 pmAh yeah, Cool. Thanks

author: ironmonkey
author_rank: Contributor
timestamp: April 27, 2017, 07:20:57 pm
content: Quote from: Kleinstein on April 27, 2017, 06:46:32 pmYou are completly right. I just put the draft as a bare starting point, but you are right and in a real circuit it should be adressedEnviado desde mi MotoG3 mediante Tapatalk

author: james_s
author_rank: Super Contributor
timestamp: April 27, 2017, 07:27:16 pm
content: In many cases a capacitor between the input and ground is sufficient for debouncing but YMMV.

author: android
author_rank: Regular Contributor
timestamp: April 27, 2017, 10:07:42 pm
content: Ben Eater has produced a well explained video on just this topic. The rest of the playlist is quite interesting too...https://youtu.be/WCwJNnx36Rk

author: SmurfKiller
author_rank: Contributor
timestamp: April 28, 2017, 08:23:40 am
content: Watched Ben Eater's videos, and came up with this. although with the not gates, i was going to use transistors, seems kind of wasteful using a 7404 and only using 2 inverters on it.

author: Zero999
author_rank: Super Contributor
timestamp: April 28, 2017, 06:08:31 pm
content: If all that's needed is to switch between two clock sources, then how about a quad NAND gate, a pull-down resistor and a switch?What's the maximum clock frequency?Quote from: ironmonkey on April 27, 2017, 06:04:19 pmWouldn't it be simpler to just use a switch and no logic gates?I can see that this might not be acceptable is if the leads to the switch are too long for the clock rise/fall time, but if the switch is on the board or has short leads, I don't see the problem.

author: radiogeek381
author_rank: Regular Contributor
timestamp: April 29, 2017, 01:02:53 am
content: Quote from: SmurfKiller on April 28, 2017, 08:23:40 amThis is the best solution I've seen so far. But it still has problems.In general, switching between clock sources in a synchronous digital system is more complicated than it looks. You have three simplifying factors in your applicationThe clocks are relatively slowOne of the clocks is only active when it is selectedNobody gets hurt if this goes pear-shaped.But, let's pretend that we really really need to do this "right."The circuit in the quote has a problem. (And this is why switching between clocks is hard.)Assume that we've been in the mode where "MANUAL CLOCK" is selected. In this case the Q output of the JK flop is HIGH and the !Q output is LOW. The two outputs are "complementary" but their values really can't be counted on in the brief interval around teh rising edge of the "CLOCK" signal. All real digital elements have some delay between input and output. In particular, flipflops not only have a delay between CLOCK edge and Q/!Q outputs, but the delay from clock to Q is not necessarily the same as the delay between clock and !Q.So the first problem with the circuit is that for a brief time Q and !Q could both be HIGH, making the clock OUTPUT the OR of "MANUAL CLOCK" and "CLOCK".Q and !Q could also both be low, making the OUTPUT LOW.Assume that we are in MANUAL CLOCK mode. Note what happens to the output when we change to CLOCK mode.At some time before the rising edge of CLOCK, we set MANUAL_CLOCK to LOW, ENABLE_MANUAL_CLOCK to LOW, and ENABLE_CLOCK to HIGHOUTPUT is LOWThe CLOCK rises, and a smidge later Q goes LOW and !Q goes HIGH.OUTPUT is HIGH, since it is now "connected" via the 2 input MUX to CLOCK.Great, we're now running in "clock mode".Now for the fun.Before the rising edge of CLOCK, set MANUAL_CLOCK to LOW, ENABLE_CLOCK to LOW, and ENABLE_MANUAL_CLOCK to HIGH.At the rising edge of CLOCK, the rising edge will propagate through the 2 input mux to the output. OUTPUT will rise to HIGH.Sometime, a few nS later, Q and !Q will assume their values (HIGH and LOW) and select MANUAL_CLOCK which is LOW.OUTPUT will fall to LOW (as it is the result of selecting MANUAL_CLOCK on the input).The OUTPUT pulse will be what is called in the trade, a "runt". It may not be wide enough for downstream logic to consider it a legitimate clock pulse. Latches may or may not latch. Edge triggered flip flops may or may not see the clock."Ah ha!" I hear you say, "This is not a problem if I ensure that MANUAL_CLOCK is high when I switch over!"Well, it is a problem. Remember that interval where we can't really be sure what Q and !Q are doing? Where they may not be complementary? In that case, we may see the OUTPUT go from LOW to HIGH to LOW to HIGH again. We may see one or two edges. This is the kind of thing that can drive folks nuts. And it is why competent professional logic designers are very very careful about clock switching.The clock selector in the quote would not be suitable for a product. It might not be suitable for a prototype.Assuming you only use rising-edge triggered flip-flops, a safe scheme could be implemented with a state machine of 3 or 4 states. The logic in this state machine would be triggered off the FALLING edge of the CLOCK signal and control the two input MUX. The states would be something like "SELECT_OSC" "SELECT_MAN" and "TRANSITION". In the TRANSITION state, neither clock input would be selected and the OUTPUT would be LOW. Even here, there is a race between the transition of the outputs from this state machine and the falling edge of CLOCK. It can be managed, but on its own is an interesting education in why real logic design is more than just truth tables.If you were to build the state machine, the transition diagram might look like this:Current StateInputNext StateSELECT_OSCNOT ENABLE_CLOCKTRANSITIONSELECT_OSCENABLE_CLOCKSELECT_OSCSELECT_MANNOT ENABLE_CLOCKSELECT_MANSELECT_MANENABLE_CLOCKTRANSITIONTRANSITIONNOT MANUAL_CLOCK and NOT ENABLE_CLOCKSELECT_MANTRANSITIONNOT MANUAL_CLOCK and ENABLE_CLOCKSELECT_OSCTRANSITIONMANUAL_CLOCKTRANSITIONOUTPUT = (CLOCK and SELECT_OSC) or (MAN and SELECT_MAN)For best results, it doesn't pay to be too clever in state assignments. If I were doing this, I'd use two D flops. SELECT_MAN would be the Q output of one flop. SELECT_OSC would be the Q output of the other flop. TRANSITION would be represented by both Q outputs false. Both Q outputs true would be the invalid state. The initial state is TRANSITION.As I said, to make this work, the state machine has to be clocked on the FALLING edge of CLOCK. This is subject to some obscure clock-skew problems if you aren't careful about wire length in the various branches of the CLOCK tree, but it is reasonably bullet resistant.Designing an 8 bit processor with SSI is a really neat bucket o' learning. Good luck.Design with SSI is something of a passing art, as much of logic design now is done via synthesis tools and high level descriptions rather than old-fashioned logic and circuit design. However, if you really really want to understand the SSI mindset, I can highly recommend "An Engineering Approach to Digital Design" by William Fletcher. I read it at the beginning of my career and TA'd the processor design course at Carnegie Mellon that used it, circa 1982.