FPGA Algorithm Projects - Page 1
Forum section: electronics / general

author: LeoTech
author_rank: Regular Contributor
timestamp: June 18, 2019, 01:06:31 pm
content: Hello member(s),In short: I'm looking for a couple of project ideas involving algorithms on FPGAs, any ideas?My experience with FPGAs and HDLs in general is more or less limited - besides a few simple 'hallo world' projects - to implementing the SAP1 and SAP2 CPU architecture, my own custom 'from-scratch' CPU design and an implementation of Booths Algorithm. I have a Cyclone V development board and have done all of my projects in verilog. I wouldn't say that I'm an expert in verilog, but I'm more or less fluent - I don't really have to Google anymore.During my summer break, besides enjoying the weather, relaxing and travelling, my plan is to design a new and improved CPU from scratch and 'build' it in verilog. Before I do that however, I want to complete a couple more projects concerning algorithms.I'm looking for algorithms that are rather simpel, like Booths Algorithm, that I can implement in verilog and preferably use in my further CPU designs as well - hardware acceleration type of things.Any advice and/or ideas?(Btw, as far as my math knowledge goes, I am only in High School, meaning that some algorithms that I have tried my hands on failed, because I didn't understand the math completely and therefore didn't really know how to implement them - just a heads up)Leo

author: tggzzz
author_rank: Super Contributor
timestamp: June 18, 2019, 01:33:08 pm
content: My suggestion is to get as far away from software and processors as possible, since FPGAs are useful for far more than that.A traditional first project would be a traffic lights controller. That will force you to think in terms of finite state machines implemeted in hardware rather than software.The complexity can be extended indefinitely to include three way junctions, pedestrians etc. You can also add in complexity to do with how thingsfailrather than how they work.Extending the functionality will probably cause the design to become an unmaintainable/unextendable mess. That will naturally lead you to consider how you should (with hindsight) have structured the design and structured the implementation. That will set you up well for more difficult future projects.Don't worry about creating a mess. The important thing is to select a project that will stretch you, and to work out how you would do better next time. When you come to have job interviews, all that will be very interesting to the interviewer, and will demonstrate that you are a thoughtful engineer rather than just a time-server.

author: radiolistener
author_rank: Super Contributor
timestamp: July 13, 2019, 11:27:43 am
content: you can implement NCO (numerically controlled oscillator), then you can mix it with ADC input and implement FIR filter and audio demodulator. You will get SDR receiver

author: OwO
author_rank: Super Contributor
timestamp: July 13, 2019, 01:22:02 pm
content: My first project on an FPGA was implementing a parallel, pipelined SHA256 calculator. I managed to achieve the same hash rate and area as existing bitcoin miner implementations for that board. I implemented the algorithm straight from the description on wikipedia.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 13, 2019, 03:23:39 pm
content: A good area to go into is advanced PWM and PDM algorithms, that are not available in most microcontrollers. That really becomes useful for power inverters and motor drives, where there can be significant efficiency advantages over classical PWM.Quote from: tggzzz on June 18, 2019, 01:33:08 pmThat was my first "real" project in digital logic class. I remember how the lights appeared to change faster if a countdown display is added, even though I know the actual timing has not changed at all. That reminded me of how some traffic lights in China have the countdown displays and then I wondered why aren't those more common.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 13, 2019, 03:54:37 pm
content: Quote from: NiHaoMike on July 13, 2019, 03:23:39 pmYeah. This is a known fact in UI development. Progress indicators help people find the waiting more acceptable. Without any progress indicator, you're psychologically bound to think whatever task is running is stuck, which makes us feel uncomfortable and even helpless.The fact that those displays are not more common is maybe due to safety considerations. I'm just guessing here, but I would say that a fraction of people, especially in some cultures, would tend to start their car when the countdown is close to 0, whereas if there is absolutely no indication of when the lights are going to go green, they have no choice but wait till they change, or take a bigger risk. Then there is also obivously the added cost of those displays...

author: rstofer
author_rank: Super Contributor
timestamp: July 14, 2019, 04:02:00 pm
content: Quote from: NiHaoMike on July 13, 2019, 03:23:39 pmIn Germany, there is a Yellow "Get Ready To Go" light between red and green. Kind of like a drag strip. Red->Yellow->GO!http://www.auguszt.de/english/VZ/zeichen4.htmA simple traffic signal was used as an example in Digital Research's Macro Assembler manual. Macros abstracted the process from the underlying code. It wasn't an all-encompassing design but it was pretty clever as a learning tool. I did a lighting control system that covered 4 buildings and about a million square feet (or more) all from a central 8080 machine coded in Fortran. The data tables were created with macros. This was around '78 or so...If one were to build a traffic signal, one task would be to detect all anomalous outputs and divert to 'All Lights Flashing Red' output. That could be an ugly logic expression for a complex intersection.Step up the game! Consider synchronized lights on major thoroughfares thru a city center. How to keep the traffic flowing? How about posting a recommended speed? Both of these exist in the real world!I would rather do a CPU. As an end product, I would have a drop-in core for other projects.