Lattice iCE 40 FPGA distorted clock signal - Page 1
Forum section: electronics / general

author: raff5184
author_rank: Regular Contributor
timestamp: November 05, 2019, 04:07:59 pm
content: Hi all,I am generating SPI signals with a Lattice iCE 40 FPGA Eval Board. My clock (36 MHz) and chip select signals look very distorted as in the attached picture.If you look carefully the clock signal goes below groundIs this ok? What could be the cause? Has anyone experienced something similar?

author: Ice-Tea
author_rank: Super Contributor
timestamp: November 05, 2019, 04:33:31 pm
content: Perhaps first of all you need to look at your probing technique? What are you using as a ground lead and how?

author: AndyC_772
author_rank: Super Contributor
timestamp: November 05, 2019, 05:20:14 pm
content: Completely normal, if you're not using a probe with a sufficiently short ground spike. If you're using the standard croc clip lead, which adds a few inches' worth of inductance to your ground connection, then that's exactly the sort of poor signal integrity and crosstalk you can expect.With your probe's accessory kit there should be a short ground spike made of spring steel. Remove the croc clip lead, install this on your probe tip, and try again with the tip of the spike touching a ground point somewhere within, say, 10mm of the signal you're looking to probe.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 06, 2019, 07:19:41 pm
content: Yep. Improper grounding. Apart from the distortion, you'll notice the significant crosstalk.Although the most likely culprit here is grounding, also check your probes' bandwidth. A 36 MHz digital clock signal requires significant bandwidth to be displayed appropriately.As a rule of thumb, I use the following:- The typical rise time (s) with a bandwidth of BW (Hz) is ~ 0.35/BW;- I consider a decent rise time for a digital signal to be max. 1/10 of the pulse width; for a 50% duty cycle clock, that would be 1/20 of its period;From the above we can infer: BW >= 7.FclockSo, for a 36 MHz digital clock, that would require a bandwidth >= 252 MHzSure you can acquire such signal with a lower bandwidth, but then it won't look anything close to a square wave.

author: raff5184
author_rank: Regular Contributor
timestamp: November 07, 2019, 03:48:12 am
content: Hi, thanks all. Yes I am using a standard lab oscilloscope probe, with the small hook tip for the signal and crock for the ground.. but I don't think I have the small tip you suggested for the ground. Would a short thin wire do the job? However I'll try and let you guys know

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 07, 2019, 03:51:48 am
content: Yes, you can do this with a paper clip, properly formed.Ferrite beads clipped onto the probe cable also help, though they tend to shift the frequency of the apparent error signal more than get rid of it altogether; this can at least help you separate what's real from what's measurement error.A higher bandwidth scope would help, too, but I suppose that'll be a harder thing to get(?).Tim

author: raff5184
author_rank: Regular Contributor
timestamp: November 07, 2019, 02:29:35 pm
content: Quote from: SiliconWizard on November 06, 2019, 07:19:41 pmin fact my oscilloscope has a BW of 200MHzQuote from: T3sl4co1l on November 07, 2019, 03:51:48 amYou're right, not an option at the momentOk I used a simple piece of wire and the result is much cleaner. But I still need to measure one line at the time to avoid cross talk and other artifacts. I guess the clock is showed distorted probably because of the BW of my scope