Pull up on the output of an LS series IC - Page 1
Forum section: electronics / beginners

author: fabiodl
author_rank: Frequent Contributor
timestamp: August 10, 2022, 08:38:16 am
content: Just a confirmation on the role of R19 inthis schematic.Is it to assure that the transistor Q1 is off when the output 1 of IC6 is logically high, but on a voltage low enough to have Q1 still conduct?Shouldn't the values of R18/R19 be swapped to assure that when the output is 2V?

author: retiredfeline
author_rank: Frequent Contributor
timestamp: August 10, 2022, 09:28:37 am
content: If you look at the totem-pole output of the LS02 you will see that there is no current path to ground when the output is logic 1. So R19 is to ensure rapid switch off by draining any base charge to the +ve rail.

author: MrAl
author_rank: Super Contributor
timestamp: August 10, 2022, 12:25:00 pm
content: Quote from: retiredfeline on August 10, 2022, 09:28:37 amHi,That's the same impression i get when i consider the max output of the LS02 gate for a logic high.The combination of 4.7 and 1k like that only raises the output by about 0.26 volts, which does not seem like enough. To turn that transistor completely off, the base voltage has to be close the +Vcc. If the supply is 5v that would mean the base should be about 4.7 volts as a minimum i would say. Any higher and the transistor will begin to conduct.The other thing though is that you have to ensure that the transistor can turn on fully too, and if you swap the two resistors the only resistor that can turn it on would be the 4.7k so that would be a reduction in base emitter current of about 1/5 what it was, roughly, plus the 1k would pull it up a lot so there's a chance that it may not turn on at all which is also not good.What you could do is assume the output of the gate goes from 0.5v for a low to 3.5v for a high and go from there. Unfortunately we dont know the load at the collector of the transistor so it's a bit impossible to specify any exact values for the two resistors that would ensure both proper turn on and proper turn off. If you can find that information that would help. If it is around 1ma then we probably dont have to worry too much, but if it has to power a small LED then we'd have to think a little more. It may be necessary to place a silicon diode in series with the emitter of that transistor, and then the output would look more like a logic high anyway once we get the resistor values right.Swapping values may just barely allow the transistor to turn on, but changing the values a bit could be better, and of course adding that diode would ensure proper operation with the right resistor values.Maybe swap but also change the 4.7k to a smaller value, like 3.9k or maybe 3.3k.We can get more exact if you like.

author: retiredfeline
author_rank: Frequent Contributor
timestamp: August 10, 2022, 01:11:18 pm
content: You have to do your calculations on the basis that Vbe is around 0.6V when the transistor is on so the two resistors do not form a pure voltage divider but one that's loaded by the be junction. The base current will be about 4.4/1k minus 0.6/4.7k. BJTs are current amplifiers. It's a mistake to consider voltages only.As for the 2V or 2.4V for logic 1, this is the voltage required to turn off the current coming from a LS gate input to be considered logic 1. It doesn't mean the totem-pole will rise to this voltage. Although there is a limit to which it can rise without a pull-up due to the upper part of the totem pole. Do this experiment: put a pull-up (within the limit of 10 LS loads) on a totem-pole output and take it to logic 1. You will find that it will rise to 5V because the bottom transistor is turned off, and current will not flow back into the top transistor.

author: David Hess
author_rank: Super Contributor
timestamp: August 10, 2022, 11:36:35 pm
content: Quote from: fabiodl on August 10, 2022, 08:38:16 amTTL outputs, including LS, only actively rise to the supply voltage minus two Vbe junctions, or about 3.8 volts, which would not be enough to guarantee that Q1 turns off reliably, so R19 pulls the output up to the +5 volt supply.QuoteI would have placed the pull-up resistor directly at the output of the LS gate, but the way shown is arguably better.

author: MrAl
author_rank: Super Contributor
timestamp: August 11, 2022, 01:55:40 am
content: Hello again,Here are some calculations that illustrate the problems with the circuit and how they can be corrected. The main idea is that the transistor has to turn fully on and fully off with the respective gate output voltage limitations.Starting with the two equations for the circuit which includes the two resistors,the logic gate output Vout, and the transistor base emitter voltages:VbeH=(Vcc*R2)/(R2+R1)-(VoutH*R2)/(R2+R1)VbeL=(Vcc*R2)/(R2+R1)-(VoutL*R2)/(R2+R1)where VbeH is Vbe when the logic gate output is high at the voltage VoutH, andwhere VbeL is the 'target' Vbe when the logic gate output is low at the voltage VoutL.R1 is the resistor connected to the output of the gate, R2 is the other resistorshown as 4.7k on the schematic as it is now (R19).We assume Vcc=5 volts. We assume VoutH=3.5 volts and VoutL=0.5 volts which istypical for a logic gate output.First we can set Vcc=5,VoutH=3.5,VoutL=0.5 and get:VbeH=(1.5*R2)/(R2+R1)VbeL=(4.5*R2)/(R2+R1)Now we see that if VbeL was equal to 3 times VbeH, these two would be exactly the same,and that would also be a decent ratio for the on/off Vbe voltages. So this would meanwe set VbeL=3*VbeL in those two and of course get:VbeH=(1.5*R2)/(R2+R1)3*VbeL=(4.5*R2)/(R2+R1)and now we can concentrate on the first equation:VbeH=(1.5*R2)/(R2+R1)Since we have two unknowns and only one equation, we have to pick one value and solve for the other.If we choose R1=1-R2 we can solve for ratios instead of actual values and so we end up with:VbeH=1.5*R2and now solving for R2 we get:R2=(2*VbeH)/3Now if we set VbeH=0.3 volts for the turn off Vbe, we get:R2=0.2and since R1=1-R2 then:R1=0.8keeping in mind these are ratios. Taking them both together:[0.8,0.2]and multiplying by 5000, we get:R1=4000 and R2=1000.Inserting these back into the original equations we get:VbeH=0.3 and VbeL=0.9and that seems good. Note however the actual VbeL will be lower but all we need to do is make sure it is lower than about 0.75, but not as close as say 0.8 due to temperature variations.The only thing left now is to calculate the expected base current.Since when turned on Vbe is 0.9 volts and the output of the gate is 0.5 volts,the voltage across R1 is 5-0.9-0.5=3.6 volts, which means the base currentis 0.9 milliamps. It will actually be higher because of the actual Vbe voltage so that is good.If we expect the transistor to remain in saturation, we can only draw about9 milliamps from the collector, so we'd have to see if the load requirementwould match that criterion. If it is just a logic output, it probably willbe ok, but if it has to drive anything significant we'd have to reexamine.The actual current will be a little higher because of the actual Vbe voltage when turned 'on'.The question that comes up of course is does 1k and 4.7k work instead of1k and 4k. The answer is that they might, but the turn on Vbe voltagewould be just barely enough and may either limit the collector outputcurrent too much or may not even turn it on enough at all.It's simple enough to calculate, just use those values in the first setof equations instead of the newly calculated values. Doing that wefind that the turn on Vbe is barely enough, if it works at all.

author: retiredfeline
author_rank: Frequent Contributor
timestamp: August 11, 2022, 04:36:44 am
content: You could have simplified all that by applying Thevenin's Theorem.

author: fabiodl
author_rank: Frequent Contributor
timestamp: August 11, 2022, 07:01:25 am
content: Quote from: MrAl on August 10, 2022, 12:25:00 pmIt's around 300 ohms.This resistor from the output of a logic gateandthis additional logic gate input

author: MrAl
author_rank: Super Contributor
timestamp: August 11, 2022, 08:56:45 am
content: Quote from: fabiodl on August 11, 2022, 07:01:25 amHello again,Ok then the transistor should have a Beta of around 20 then when in saturation or near that, and it probably will if you use a modern transistor.

author: Peabody
author_rank: Super Contributor
timestamp: August 11, 2022, 03:12:25 pm
content: It seems to me that the LS02's output can't sink current when it's high, so only the 1K resistor is needed - as a base resistor for when the LS02 goes low. When high, the output is essentially sourced from Vcc through a resistor and two diodes. If there's no path to ground, then no current can flow through the transistor base, and the transistor will be off. It will turn on only if the LS02 output goes low. When the LS02 is high, it would be pulled up to 4.4V through the emitter of the PNP if the 4.7K is not present. If it is present, then the output will be pulled up to 5V. But no current will flow in either case, and the transistor will be off. The 4.7K does affect the transistor turn-on and turn-off times, but I think that's all it does.

author: David Hess
author_rank: Super Contributor
timestamp: August 12, 2022, 12:38:52 am
content: Quote from: Peabody on August 11, 2022, 03:12:25 pmI am just shooting from the hip here. There is some leakage current through the schottky diodes used as Baker clamps in the LS process. The bottom transistor's schottky leakage gets multiplied by its current gain overwhelming the leakage from the top baker clamp diode. The top transistor is in cutoff so does not amplify its Baker clamp leakage.QuoteBut I agree that the 4.7 kilohm resistor has the greatest effect on the turn-off time and leakage of the transistor itself. It should be included with any transistor switch which is not actively pulled off.

author: MrAl
author_rank: Super Contributor
timestamp: August 12, 2022, 10:41:58 am
content: Quote from: Peabody on August 11, 2022, 03:12:25 pmHello there,You would think that the emitter of an NPN transistor with the emitter 'pulled up' to +5v would have to go to at least close to +5v (or above), but a spice simulation shows the output to be 3.4v with no pullup and 3.48v with a 1k pullup. So there may be something else at work internal to the LS02 that we cant see on the data sheet.It could also be that the spice model is not that accurate, and to find out we would have to measure the output with a 1k resistor pullup using an actual real life gate package.Of course for these tests we ground both inputs so the output is a logic high.I used 3.5v in my calculations because that is a typical output for the high state.

author: tggzzz
author_rank: Super Contributor
timestamp: August 12, 2022, 10:59:35 am
content: Quote from: MrAl on August 12, 2022, 10:41:58 amThose voltages are absolutely standard and to be expected: look at the data sheet and the Vohparameter limits. It only has to be >2.0V, since that is the Vihof an LSTTL input connected to the output.Other TTL families of similar vintage have similar parameter limits. CMOS 74 logic (e.g.74ACxxx) with the same pinout has the symmetrical output voltage that is familiar in modern logic families, and that can drive LSTTL inputs directly. But the asymmetric 74LS outputs cannot drive 74AC inputs; if you want to do that, you have to use 74ACT devices, where teh T indicates the input parameters are compatible with TTL outputs.

author: Peabody
author_rank: Super Contributor
timestamp: August 12, 2022, 05:46:30 pm
content: I breadboarded this part of the circuit using a 74LS32, 1K and 4.7K resistors, a 2N3906, and a 100R collector resistor as the load. Here's what I got:Code:LS Output State High Low1K and 4.7K-----------Vcc 5.11V 5.10VLS out voltage 5.11V 228mVBase voltage 5.11V 4.17VCollector voltage 0V 4.74VCollector current 0mA 48.9mA1K only-------Vcc 5.11V 5.10VLS out voltage 4.59V 227mVBase voltage 4.59V 4.16VCollector voltage 0V 4.80VCollector current 0mA 49.1mAThe LS32 had a date code of 8016, so barely broken in. Anyway, this shows you have to have base current to get collector current. And when the LS output is high, it can't sink any current, and the transistor will stay off - with or without the 4.7K pullup.

author: retiredfeline
author_rank: Frequent Contributor
timestamp: August 13, 2022, 03:27:51 am
content: The one thing that's surprising is the Vbe of the transistor when hard on, about 1V. I suppose it's possible. Could you measure between b and e if you still have the breadboard set up?

author: MrAl
author_rank: Super Contributor
timestamp: August 13, 2022, 08:17:03 am
content: Quote from: Peabody on August 12, 2022, 05:46:30 pmHello,That's nice of you to do that test.There is something that does not look right though with the measurements.That is, the data suggests that with a 5.7k pullup the output of the LS is 5.11v but with a 1k pullup it's only 4.59 volts. Is that correct?Maybe you could post the schematic. in the mean time, i'll try this test with the spice model too.If that data is correct as i understand the circuit, then the spice model is a bit inaccurate in some respects. It could be that the company that made the spice models (2 different simulators) did not expect anyone to connect a pullup on the output of an LS gate. That also brings up the question should we actually be using a pullup on a gate that does not have an open collector output.It would be great if we could find an internal diagram that is not overly simplified too.So if you could post a small schematic that would be good.Nice of you to do the test this is all we can do sometimes; perform some real life tests.

author: Peabody
author_rank: Super Contributor
timestamp: August 13, 2022, 03:10:14 pm
content: Quote from: retiredfeline on August 13, 2022, 03:27:51 amI don't still have it set up, but perhaps someone else could give it a try. You're thinking Vbe should be lower?

author: retiredfeline
author_rank: Frequent Contributor
timestamp: August 13, 2022, 03:37:06 pm
content: Yes, normally when the transistor is on, Vbe is in the range 0.6 - 0.8 V. Well, the datasheet says about 0.95V at Ic = 50mA and Ib = 5mA so I guess that's ok.https://www.onsemi.com/pdf/datasheet/pzt3906-d.pdf

author: Peabody
author_rank: Super Contributor
timestamp: August 13, 2022, 03:52:02 pm
content: Quote from: MrAl on August 13, 2022, 08:17:03 amIt's not a 1K pullup. The 1K goes to the base of the PNP. The 4.7K goes from the base to Vcc. I'll attach a schematic. It's the same circuit as the original post.With the 4.7K in place, since there is nothing to sink current, the LS output voltage will just be Vcc. Without the 4.7K, the voltage is simply the one-diode drop across E-B when there's no load. The resulting voltage is higher than the LS would produce on its own if nothing were connected to it, so the nominal LS output voltage when high is irrelevant.I should say that in fact the 4.7K probably should be directly connected to the LS output, not to the other side of the 1K resistor. As it is, you have a voltage divider at the base, which normally you would not want. But it probably doesn't matter in this case.QuoteI would expect the Spice model to produce the same result. As for the pullup question, I'll repeat what I said earlier that unless it is needed to speed up transistor turn-off, or slow down turn-on, I don't think the pullup does anything useful. I know that many here would always use a base-emitter resistor to bias the transistor off, but I don't do that, and don't think it's needed. If would be different for a mosfet, but these are bipolars. In any case, if it's not needed for speed adjustment, then it could be a much higher value, like 100K.

author: gamalot
author_rank: Super Contributor
timestamp: August 13, 2022, 04:47:08 pm
content: You don't need the pull-up resistor R19 here, the totem-pole output stage of the 74LS device ensures that Q1 will be turned on and off properly.

author: MrAl
author_rank: Super Contributor
timestamp: August 13, 2022, 05:56:20 pm
content: Quote from: Peabody on August 13, 2022, 03:52:02 pmHello again,Yes that's interesting because the raw transistor model would do that too.But i suspect that the design point should be more like 3.5 volts, as that is what they specify. I dont know the reason for that though, but i do know that in the raw transistor model it would take a resistor around 500 Ohms to get the output to go to 3.4 volts or there about.So it is unclear why the spice model is not showing what you are measuring but it does show what the data sheet specifies. I'd have to look deeper into this issue but not sure i will have that much time and dedicate that much energy into it :-)This wouldnt be the first time this happened though, there are specs that are not spec'd on some data sheets and you dont find that out until the breadboard phase of the design.

author: Peabody
author_rank: Super Contributor
timestamp: August 13, 2022, 10:45:40 pm
content: Quote from: MrAl on August 13, 2022, 05:56:20 pmI don't understand what you're referring to. Do what too? 500 ohms placed where? 3.4V under what conditions? Who specifies 3.5V for what? The original schematic in post #1 has Vcc at 5V, which is what you would need for 74LS. Are we talking about two different circuits?QuoteCould you be more specific? Which measurement are you referring to? What does the spice model say?

author: retiredfeline
author_rank: Frequent Contributor
timestamp: August 13, 2022, 11:21:46 pm
content: I don't understand that obsession with 3.5 V and simulation. Just looking at the totem-pole circuit it's can be seen that when the output is logic high, it'seffectivelyopen circuit because current can't flowout ofthe top transistor, so the pull up makes transistor base rise to the 5V rail. The 3.5 V (3.6, 3.7 whatever) would happen if there were a load to ground due to the 2 diode drops. But there isn't a path to ground because the lower transistor is off.If the transistor load is something like a bulb then turn-off time doesn't matter. Then if the transistor is perfect you don't need a pull-up. But in case you encounter a slightly leaky cb junction, the pull-up ensures that the transistor will never be partly on.

author: gamalot
author_rank: Super Contributor
timestamp: August 14, 2022, 04:51:08 am
content: Quote from: retiredfeline on August 13, 2022, 11:21:46 pmIf you think the leakage current of transistor Q1 needs to be considered, then you should not think that the output stage of the LS02 is completely open circuit.The OP's circuit diagram is incomplete, I found where the /JOYSEL signal goes, it is connected to a 2.2K pull-down resistor and the input of a 74LS32 logic gate.So in this specific application, removing the pull-up resistor R19 from the base of Q1 will not cause any problems.

author: fabiodl
author_rank: Frequent Contributor
timestamp: August 14, 2022, 08:42:18 am
content: Quote from: gamalot on August 14, 2022, 04:51:08 amThanks!

author: MrAl
author_rank: Super Contributor
timestamp: August 14, 2022, 10:13:26 am
content: Quote from: retiredfeline on August 13, 2022, 11:21:46 pmHi,The 'obsession' is due to the fact that we would like to see spice models work as close as possible to the real life parts they model. If they dont, it becomes a concern and thus a new model can be made to better mimic the behavior of the real life part. It's not as much to do with this particular circuit as it is with future circuits where we would like to be able to model the significant behaviors as well as possible.

author: MrAl
author_rank: Super Contributor
timestamp: August 14, 2022, 10:26:57 am
content: Quote from: Peabody on August 13, 2022, 10:45:40 pmHi,Yeah sure.First, if the spice model shows a 3.5v output (approximately) even with a 1k pullup when the output is high and you or i measure 4.9v with a 1k pullup then there is something missing about the spice model and that says that it cant be used for any circuit that is atypical of a regular logic circuit.Second, if we model the device with discrete spice NPN transistors, we see a behavior more typical of what you or i would measure in real life, and in order to meet the specs of the data sheet or the full spice model we would for example have to connect a 520 Ohm resistor from the output of the gate to ground. That resistor would draw enough current to mimic the behavior of the original spice models. It's only to show that it seems a bit ironic that when we use the internal transistor diagram we dont get the data sheet behavior unless we sink some current to ground, and it would be somewhat significant for an LS type gate output.So the first point is more important, the second is just a comparative analysis of what we should have an what it takes to match the data sheet and spice models.The catch though is that these gates were made for connecting to other gates, which means they would be subject to the constraints that the input impedance of the next gate would present. Strange though, using the discrete transistor model shows near zero current to ground with a high logic level input.So the conclusion is that the spice model is lacking.The next test we would have to do is check the fall time of the output when the output is pulled up by perhaps 4.7k. Since the fall of the output would have to go through a larger transition from H to L it will take a little longer to get to 0.5v which would be enough for the next gate. How much we can probably estimate based on the current fall time. This doesnt seem to be a big concern with this particular circuit however. It would only possibly matter in future designs we wanted to test mathematically or in a spice environment.

author: Peabody
author_rank: Super Contributor
timestamp: August 14, 2022, 02:45:22 pm
content: Could you please post the spice schematics your comments are based on? It doesn't sound like you are modeling the same circuit as the one I breadboarded, which didn't have a 1K pullup at all.

author: retiredfeline
author_rank: Frequent Contributor
timestamp: August 14, 2022, 03:05:08 pm
content: It's a worry when you pluck a figure like 3.5 V from the datasheet and treat as an operating point. When the breadboarded circuit behaves just like you can predict from the schematic of the totem pole circuit and not the Spice model then you have to ask yourself if the model or the initial conditions are correct for the situation.3.5 - 3.7 V isn't some kind of value the LS output "tries to maintain". In the presence of no path to ground and a path from 5 V via the transistor and base resistors, it will go higher as the practical test by Peabody shows. Entirely predictable, without the benefit of simulation.And there is nothing wrong with using a gate T-P output this way to drive a transistor. You just have to operate below the sinking capacity of the gate (10 LS unit loads). But open collector outputs are still needed when the high side is greater than 5V or greater current sinking is needed.

author: MrAl
author_rank: Super Contributor
timestamp: August 14, 2022, 09:43:55 pm
content: Quote from: Peabody on August 14, 2022, 02:45:22 pmHi again,That's the first thing i checked and was disappointed that there was no schematic just some commands likeyou would use for a diode, and some timing.Here's the entire thing and notice that it says 7402 not 74LS02 but it was picked from their listing for 74LS02:.SUBCKT 7402 1A 1B 1Y+ optional: DPWR=$G_DPWR DGND=$G_DGND+ params: MNTYMXDLY=0 IO_LEVEL=0U1 nor(2) DPWR DGND+ 1A 1B 1Y+ DLY_02 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}.model DLY_02 ugate (tplhTY=12ns tplhMX=22ns tphlTY=8ns tphlMX=15ns).ENDS 7402Maybe we can get a better model.Here's another but it's almost the same thing:* Quad 2-Input Nor Gates** The TTL Logic Data Book, 1988, TI Pages 2-13 to 2-17* bss 2/3/94*.SUBCKT 74LS02 1A 1B 1Y+ optional: DPWR=$G_DPWR DGND=$G_DGND+ params: MNTYMXDLY=0 IO_LEVEL=0U1 nor(2) DPWR DGND+ 1A 1B 1Y+ DLY_LS02 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}.model DLY_LS02 ugate (tplhTY=10ns tplhMX=15ns tphlTY=10ns tphlMX=15ns).ENDS 74LS02

author: Peabody
author_rank: Super Contributor
timestamp: August 15, 2022, 01:33:11 am
content: Sorry, but I'm not able to follow what you're doing. So I'm going to bow out of the conversation, and hope that the OP has found an answer to his question.

author: fabiodl
author_rank: Frequent Contributor
timestamp: August 15, 2022, 07:29:42 am
content: Quote from: Peabody on August 12, 2022, 05:46:30 pmI'd say this is a pretty clear answer, thanks!

author: MrAl
author_rank: Super Contributor
timestamp: August 15, 2022, 09:58:30 pm
content: Quote from: Peabody on August 15, 2022, 01:33:11 amHi,Ha ha, i dont blame you. The only thing i was trying to do is establish that the models do not match the measured data, nothing difficult about that. Neither the spice models nor the internal diagrams match anything we measure.The actual models are internal to spice also so we cant see them. We could try to find them on the web i guess but it's really not needed here i think.It's more of a general area of interest for example see here:https://electronics.stackexchange.com/questions/518248/ltspice-how-to-simulate-real-ttl-gatesSo it's a known issue.In the past i had data books that talked about using CMOS gates in analog applications.

author: tggzzz
author_rank: Super Contributor
timestamp: August 15, 2022, 10:45:49 pm
content: I'm not a fan of stack space. In discourages deep understanding of fundamentals, preferring to concentrate on superficial trivia such as which squirdle to you fettle to turn the drowpty green in WizzBang v3.87.One example of that is in the article referenced, which contains "If you build a mixed analog digital circuit then you need to have models of real TTL or CMOS gates which have realistic current characteristics, sensing thresholds, etc.".That's just wrong.What you need to have is an understanding of the specification of what isand isn'tguaranteed. Then you use that todesign(not simulate) circuits that are insensitive to what isn't guaranteed.All simulations are erroneous, but in some limited circumstance some are useful. Only understanding can help delineate those circumstances.In the context of LSTTL logic output voltages, any output above 2V is a valid logic 1 level, and below 0.8V is a logic 0 level. Some outputs can and do legitimately have regular "AC noise" superimposed on a constant voltage level. Circuits have to be insensitive to that.The pictures below show anunloadedLSTTL output, 1V/div vertically, 0.5µs/div and 5µs/div horizontally.The logic 0 level is pretty clean (unless there's groundbounce) it usually is since it is the totem pole output's Vcesat.The logic 1 level always well exceeds 2V by a surprisingly large amount. During +ve transition it gets to 2.2V fast, then takes 1µs ambling up to >4V. Nobody would have any cause for complaint about the 0.6Vp-p"noise on the output".

author: MrAl
author_rank: Super Contributor
timestamp: August 16, 2022, 07:47:59 am
content: Hello,Superficial trivia?You serious?I dont think so. Some data books made by the manufacturers themselves contain information like this. That came about because they found out that designers were using digital parts like gates in analog applications like oscillators and even straight up amplifiers yet there were no specs for these parts that could relate to those kinds of applications.You seem to be the only one spewing superficial trivia i suggest you stop.

author: tggzzz
author_rank: Super Contributor
timestamp: August 16, 2022, 08:27:11 am
content: Quote from: MrAl on August 16, 2022, 07:47:59 amI presume the context of you comment is my post. Your response is unnecessarily vituperative, and indicates you didn't read/understand what I wrote. The "superficial nonsense" refers to posts on stackspacein general, and is a consequence of the site design, moderation, and users. I stand by that statement.I gave specific reasons for my objecting to a statement in a post on stackexchange. You have ignored the reasons and invented an irrelevant strawman argument.Isn't it obvious that if something is specified in the data sheet by the manufacturer then you can rely on it. If not, then you can't.Simulation (as proposed in this thread) based on unknowns gets you precisely nowhere. The only option is to characterise a manufacturer's device, and hope the next instance behaves similarly. You have to repeat that with different manufacturers and hope the manufacturer doesn't change the fabrication process.BTW, I am quite familiar with using logic gates in analogue circuits. Ifirsttime was in 1979, to build a bandpass filter with a Q of ~4000 using 10% capacitors. I used the principles I found in a 1957 paper from Bell Labs. There is, by design, absolutely no way stackexchange could be useful for that kind of discovery.

author: MrAl
author_rank: Super Contributor
timestamp: August 16, 2022, 05:36:49 pm
content: Ok no problem.I suggested that one post just as an illustration, one other person looking for info on using logic devices for analog circuits.I see you were active in the past as was I. It was really nice in those days with the bigger parts and wider spaced leads.

author: tggzzz
author_rank: Super Contributor
timestamp: August 16, 2022, 07:27:58 pm
content: Quote from: MrAl on August 16, 2022, 05:36:49 pmProbing can indeed be a pain, but I now prefer making things with SMD components - smaller, lower inductance, no holes, sane pinouts unlike standard TTL and pinout compatible derivatives.But not BGAs, though!

author: David Hess
author_rank: Super Contributor
timestamp: August 17, 2022, 01:55:34 am
content: Quote from: retiredfeline on August 13, 2022, 11:21:46 pmWith low power schottky logic, those are not just transistors; they have schottky diode Baker clamps which will contribute more leakage than the transistors.One might get away without the pull-up resistor to shut off the discrete common-emitter high side PNP, but it is not something I would rely on if the application requires the PNP to be truly off.

author: MrAl
author_rank: Super Contributor
timestamp: August 17, 2022, 05:28:49 am
content: Quote from: tggzzz on August 16, 2022, 07:27:58 pmOh yes the larger SMD components arent too bad and yes no holes that's really nice.But dont say "BGAs" around me that's a four letter curse word (ha ha).

author: MrAl
author_rank: Super Contributor
timestamp: August 17, 2022, 05:30:24 am
content: Quote from: David Hess on August 17, 2022, 01:55:34 amHi,I have to agree with that id be afraid not to use at least some value pullup just to make sure. Apparently the designer of that circuit felt the same way.

author: Peabody
author_rank: Super Contributor
timestamp: August 17, 2022, 02:42:28 pm
content: Quote from: David Hess on August 17, 2022, 01:55:34 amIt seems that any leakage in the transistors or Baker clamps would simply increase the voltage at the output, which would turn the PNP even further off. There has to be current leaking to ground to partially turn on the transistor. But your credentials are much better than mine (I don't have any), so I'm sure you must be right. And I have to admit that I occasionally see pullup and pulldown resistors on bipolar bases in other circuits. But I've never used them, with no regrets so far.How would you go about calculating the value of the pullup in this case? Is 4.7K the right value? How do you know? Would 1Meg work?

author: David Hess
author_rank: Super Contributor
timestamp: August 17, 2022, 05:04:54 pm
content: Quote from: Peabody on August 17, 2022, 02:42:28 pmThe nominal recommended pull-up value for LSTTL with one load is 18 kilohms. (1) For standard TTL it is 4 kilohms.The pull-up just needs to cancel any leakage so it could be much larger, but I would probably make it 10 times the recommended value, so 180 kilohms. If turn-off speed is important, then it should be much lower in value.(1) Page 5-5 of the Texas Instruments TTL Data Book.