Low noise 0.01Hz-1+MHz amplifier project - Page 1
Forum section: electronics / projects

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 10, 2023, 06:49:16 pm
content: I have been working on a low noise preamplifier that is suitable for characterizing very low level signals riding on a significant DC bias voltage. I am planning on putting the KiCAD project files up on Github, and I'll post a link to the repo when I do. I have primarily used it for characterizing noise of voltage references, but it should be applicable to various other low-level AC amplification tasks. The input stage uses a 23uF/100M HP filter (Fc = 69 uHz) and a composite amplifier made from 16 paralleled JFE2140s and an OPA140 operating at a fixed gain of 501. The tail current of each JFET pair is 800 uA, and the differential amplifier input stage uses a cascode + inverted cascode topology. Active biasing of the inverted cascode ensures that the OPA140 inputs stay close to ground. This input stage gives a wideband noise density of about 0.62 nV/rtHz with a 1/f corner of a few Hz. Noise from 0.1-10Hz is 2.78 nVRMS (16.7 nV p-p), and noise from 0.01-10 Hz is 3.18 nVRMS (19.1 nV p-p).The unit is powered by 4x21700 Li-ion cells on a separate board with a BMS for balanced charging, etc., as well as an integrated charger based on the BQ24618 to give a full charge in about 2.5 h. The current draw with shorted inputs is ~30mA, so battery life is >100h. The enclosure is a Hammond 1457N1601 (~160x100x50 mm) with PCBs for the front and rear panels (the battery charger is on the inside of the rear panel).A few other points about the design:-The basic signal train is: Input HP filter -> A1, G=501 -> HP filter -> Gain stage (G=20/200) -> HP filter -> Buffer -> LP Filters -> SW -> Output-Input capacitance is about 100 pF (though see point below), which is primarily from the PCB itself. This will be reduced in a future revision.-A series 330R + 470pF from input to ground was required to damp out oscillations with certain op-amp buffered inputs. This will be connected via relay in a future revision, but increasing the impedance of the feedback network for the input stage should help as well.-There are three bandwidth options for LP filtering - wideband goes to about 2.5 MHz (-3dB), and there are two fourth-order Butterworth filters in Sallen-Key topology for low pass filtering to 10 kHz and 10 Hz.-There are two HP filter cutoff points, 0.01 and 0.1 Hz, as well as a "settle" mode which shorts the output of both HP filters to GND with MMBF4117 JFETs.-Gain is switchable (60, 80, and 100 dB). The 100 dB gain setting has limited utility because signals and amplified at full bandwidth prior to the LP filters, so it saturates easily. I will add some pre-filtering in a future revision to improve dynamic range for such cases. The 60dB gain setting uses a 9k/1k divider prior to the first (non-input) HP filter.-There are window comparators to detect saturation before both HP filters. These trigger 555 timers that drive warning LEDs on the front panel.-The capacitors for the input HP filter are a pair of Kemet C4AQLLW5120A34K polypropylene capacitors. These had the best leakage and DA of the suitably low-profile capacitors I tested, and I don't believe selection will be required for bias voltages of 25V or less, but they are definitely not specified for the >2TOhm parallel resistance I observed in the samples I tested.I have attached some photos of the project and a pdf of the schematic for the amplifier board.Edit: Here's the link to the github repo:https://github.com/curtisseizert/LowFreqLNA/tree/main

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 10, 2023, 06:59:55 pm
content: More photos due to the size limit.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 10, 2023, 07:06:37 pm
content: Also, here are a few VSD plots at 0.01-10Hz bandwidth for the amplifier itself and some a voltage reference. These were captured with a 3458a sampling at 50 SPS. I think all used 1.5M samples.

author: moffy
author_rank: Super Contributor
timestamp: October 10, 2023, 07:52:28 pm
content: An excellent low noise amplifier, particularly impressive is the 1/f performance. That is a laboratory grade instrument, and having recently dabbled with some low noise circuits requires a lot of attention to detail. Kudos also for making it public.

author: TimFox
author_rank: Super Contributor
timestamp: October 10, 2023, 08:46:25 pm
content: Nice work, especially for low "excess", "pink", or "1/f" noise.Could you regraph the data with a log scale for the noise voltage density?

author: jbb
author_rank: Super Contributor
timestamp: October 10, 2023, 11:09:00 pm
content: Oooh, that's a lot of JFETsAnd someverynice curves!I have a question about the innards of the input amplifier.My assumptions:There's a JFET diff pair and cascode stage (Q26) which looks very sensibleQ27 is a current mirror, which - I think?? - is normally used for converting a the differential current from the cascode into asingle-endedoutput currentThen there's a cascode stage using Q28 to get those currents into R70, R73.U13A and Q29 seem to be a servo for controlling Q28.1, Q28.2 biasing...R70, R73 convert JEFT amplifier currents into voltages for handoff to U14The Q26 cascode input biasing looks interesting. Is it done that way to help with input common mode rejection?Does that servo with U13A behave nicely? Does it tend to peg at full rail and rely on the "100k bodged in at source of Q29"? Does it tend to split the current into R70 and R73?I was thinking that a simpler option might be to replace Q27, Q28, U13A with a folded cascode (as is apparently common in CMOS opamps)?. Never mind: realised that R70, R73 would need to be a lot smaller (e.g. 1k) to handle the bias current.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 11, 2023, 12:10:52 am
content: Thanks both for the kind words.Here are some more VSD plots and some previous ones replotted on log/log scales. I did not bother replotting the 6k04 J-N Noise calibration plot because it is flat. The new ones were digitized on an Analog Discovery Pro. The first two show noise and frequency response for inputs grounded through 0R and 6k04, respectively. I cut the graph off on the left at 1 kHz for the sake of getting a smoother curve. The third plot is the noise floor with the 10kHz LP filter on log/log axes to show the 1/f corner. It seems to be a bit higher frequency than I have seen it in the past, which may be from the frontend of the ADP3450. The fourth is the noise floor from 0.01-10Hz on log/log axes, and the final one is a handful of ADR1000-based 10V references. I don't know why the green trace has such a low flicker noise slope, but I have run it twice to confirm.This amplifier is actually a fair bit worse for 1/f noise than a previous revision with an identical input stage. I suspect it is from the JFETs on this one being salvaged from previous prototypes, since I used new ones for that version. I can't find the capture I took to plot the VSD for the previous version, so I'll have to put it back together and run it for posterity.The wideband VSD plot is indicative of the frequency response I saw during testing using the network analyzer function of the ADP3450. The response showed 0.1 dB flatness to ~250 kHz and a -3 dB point of 2.5 MHz with no gain peaking.

author: David Hess
author_rank: Super Contributor
timestamp: October 11, 2023, 12:44:35 am
content: When I originally saw the title, I thought I was going to suggest checking out the design of the Tektronix 7A22, but you have things well in hand.With a differential input stage, why not make the input fully differential? Then external common mode noise could be rejected also, although it would require a different scheme for AC coupling, probably including bootstrapping.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 11, 2023, 01:05:52 am
content: I'll save you the trouble of building the LTSpice schematic - I have attached it. I measured the parasitic capacitance from various nodes to GND and added those as well. Note that you'll need to either download the TI models and change the names (they use things like OPAx140, etc., which mildly annoys me, so I change the .lib files) or try a similar ADI part. I think the ADA4622 would be closest for the OPA140, or perhaps the ADA4627. There are a pair of antiparallel diodes across the op amp inputs in the LTSpice model to get it to behave better. This model very accurately reproduces the behavior of the actual circuit.The diff pair JFETs are run at a drain-source voltage of about 1.2V (enforced by the cascode) to minimize gate leakage and power dissipation in the JFETs. Minimizing power dissipation is crucial to avoid thermal gradients that can masquerade as 1/f noise. The loads for each leg are formed by the emitter-degenerated current mirror (Q27). This gives reasonably high impedance with moderate voltage drop. The inverted cascode (Q28) keeps the outputs from the diff pair within the common mode range for the op amp. JFET input op amps require a fair bit of headroom from the positive rail for their inputs. The OPA140 requires 3.5V, and 2.5V-3.5V headroom is very common. Omitting the inverted cascode would really restrict the choice of op amps for the input stage. U13A is indeed a servo for biasing the inverted cascode. The 100k source resistor I bodged in to connect Q29 to the positive rail is to reduce the gain of the servo to keep it from oscillating with certain inputs. I have simulated versions where the cascode Q26 is omitted because I would have preferred to leave it out, but it is necessary to maintain phase margin, especially with inductive-seeming inputs (including certain configurations of OPA2205, which I really like).The servo isn't really necessary for CMRR - the cascode Q26 would be sufficient for that. I am sure it doesn't hurt, but CMRR isn't really too big a concern when operating at such high gains. The input common mode range for the input stage is only about +/- 8 mV. One thing I failed to realize when I initially designed this is how important the impedance of the feedback network is. At the point where the loop gain of the hybrid amplifier reaches 0 dB, the output impedance of the OPA140 is non-zero and rising. This is probably more important for stability than f_t of the feedback leg of the JFET pairs (based on some napkin math, it should be about 63 MHz at this tail current). So at a high enough impedance of the feedback network, the large input capacitance of the 16 paralleled JFETs would form a pole with the feedback network, which would degrade phase margin, leading to instability. With a 2k49 || 15 pF - 4R99 divider, the phase margin is comfortably above 60 degrees, even with some moderately inductive inputs.The most challenging aspect of designing this was not the noise, it was making sure it wouldn't oscillate. Also the layout of all those JFETs was a PITA. Thanks for noticing the servo. I thought it was a clever little trick.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 11, 2023, 01:16:19 am
content: David - I had considered that, and I may in the future, but I was at a point with this project where it needed to be usable without a redesign of the input stage. Common mode noise is definitely one of the more problematic things when using the current design, and I have resorted to using batteries to power DUTs if I want to keep noise to a minimum.

author: David Hess
author_rank: Super Contributor
timestamp: October 11, 2023, 02:15:29 am
content: Quote from: CurtisSeizert on October 11, 2023, 01:16:19 amI have done the same thing and also directly connected the DUT to the amplifier input without a cable.In practice when comparing single ended designs, which should have a 3dB advantage in noise, to differential designs, the common mode rejection of a differential design makes more than a 3dB difference when typical probe connections were used.One problem with a differential input design is how to handle AC coupling. If AC coupling is used at the inputs, then where the low frequency transition band does not match, common mode noise will be converted into a differential mode signal. Tektronix's solution for this was to DC couple the inputs and apply a precision DC reference to one input.One method I have used is to use DC coupling at the inputs and then apply AC coupling at the differential to single ended conversion stage with a servo amplifier. I am not sure why Tektronix did not do it this way. Either method requires the inputs to have a common mode range which includes the DC component of the signal, which will mean bootstrapping the input amplifier adding even more complexity. The 7A13 achieved a +/-10 volt input range this way, and the 7A22 managed +/-1 volts, which does not seem impressive but that was at 10 microvolts/division or an amplification of 100,000. Typical oscilloscope inputs back then had a common mode range of perhaps +/-100 millivolts.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 11, 2023, 05:45:36 am
content: David - thanks for getting me to think about this again. It may be possible to adapt the input stage to have differential inputs without too much hassle. I simulated a possible scheme in LTSpice, which I attached. The AC coupling caps are small for ease of simulation. This would require the sources of the JFETs on each leg to be paralleled, but that should be feasible with the JFE2140. I have found parts from the same order to have low Vgs spreads (~30 mV for 20 parts) at the drain currents that I have tested. In this amplifier, integrator U4 modulates the base voltage of loads Q8 and Q7 to keep the output common mode voltage near the source voltage of the input diff pair. This reduces dissipation in feedback resistors R5 and R6 and helps CM rejection at low frequency. Some tweaking can probably improve this further. The differential outputs can be fed into a subtractor and HP filtered as a single ended signal. Also, this should have similar noise as the single ended version.I will need to try some things and do a more thorough stability analysis before laying out the board. I may even be able to fit it in the same box.

author: magic
author_rank: Super Contributor
timestamp: October 11, 2023, 08:03:39 am
content: Wouldn't a bipolar opamp work just as well in place of OPA140, without all the superfluous complexity?The usual reason for shunning BJT is their base current and noise, but I think contribution of a relatively low current IC input stage would be negligible compared to all the noise you are already adding with bipolar cascodes and current mirrors conducting full JFET current.Regarding input pair load impedance, it only needs to be high enough to overcome voltage noise of the integrator opamp. A few volts dropped across ordinary passive resistors might be enough if the opamp is a quiet one, and again, going bipolar could help.That's my $0.02. You have built a fairly impressive beast, nevertheless.editYMMV, but I have downloaded your sim, replaced OPA140 with LT1007 and simply removed the mirror. V(onoise) is almost right on top of V(j1)+V(j2)+V(r6).edit editBut bandwidth is reduced for some reason. Also, I realized that the input stage is still effectively loaded by 10kΩ rather than merely 330Ω due to the folded cascode. And removing the latter broke the simulation for some reason, I have no time to investigate right now.

author: David Hess
author_rank: Super Contributor
timestamp: October 11, 2023, 01:59:27 pm
content: Quote from: CurtisSeizert on October 11, 2023, 05:45:36 amTake a look at how the Tektronix AM502 differential amplifier works, as well as true instrumentation amplifiers, as opposed to the "3 operational amplifier" type instrumentation amplifiers which essentially have two differential pairs in series further increasing noise. The Tektronix 7A13 and 7A22 are less relevant because they have differential outputs and never do the differential to single ended conversion, but the AM502 does.QuoteMy comment about noise compared single ended to differential designs. Yours is a differential design with a single ended input which is also sometimes used in oscilloscopes for I think balance reasons. (1) Yours should have identical noise to a fully differential design even though it only has one input.Quote from: magic on October 11, 2023, 08:03:39 amThe source impedance at the OPA140 inputs is 10 kilohms, so an LT1007 is not optimal, and bipolar parts which are optimal like the LT1001 or LT1012 are much slower, and even the LT1007 is not that fast. Of course the load resistors for the cascode could be lowered in value, but the OPA140 is pretty low noise, better than an LT1012 and competitive with an LT1007 except at low frequencies, and the JFET input gives a nice boost to bandwidth and slew rate.Why use a folded cascode at all, especially in an AC coupled design? The supply voltages are pretty low and the best operational amplifiers do not have rail-to-rail inputs.(1) The Tektronix 475 or 475A or both do this, but I am not sure why. It might have something to do with hybrid construction. Oscilloscopes usually do it to support an offset input, but the 475/475A lack that.

author: magic
author_rank: Super Contributor
timestamp: October 11, 2023, 02:34:13 pm
content: The only thing that matters is current noise divided by transconductance of the JFETs, and voltage noise divided by 10kΩ and further divided by transconductance of the JFETs. If you want to be pedantic, selection for 10kΩ source impedance is wrong too because the optimal value of 10kΩ is infinity so it should be corrected and then an opamp selected for that.But, thankfully, integrator noise is not something that needs to be optimized, it's something that only needs to be good enough. LT1007 is good enough. Why LT1007? Because it's one of the first things that pop up in LTspice that's good enough. I downloaded TI OPA210 model and it simulates just as well as LT1007, while having twice the GBW of OPA140. And wider CMIR.I don't think that OP is tied to JFET opamps. Particularly if there is already a bunch of BJTs in the same circuit, happily pumping their base current noise into the same JFETs.

author: magic
author_rank: Super Contributor
timestamp: October 12, 2023, 10:55:56 am
content: A more serious attempt at simplifying the input stage attached.My motivation is not just obsession with minimalism, although that too, but also a practical concern about base current noise of all those discrete transistors. Your measurements still indicate a few dB of flicker noise not accounted for by simulation, and besides thermal effects and maybe excess noise of resistors, these transistors are among chief suspects in my opinion.This opinion is backed by simulation experiments, where high current noise opamps like LT1028, AD797 or OPA211 notably increased simulated flicker noise of this amplifier, unlike OP140. Given that some of the discrete transistors operate at an order of magnitude higher base current, even if they are less "1/f noise prone" than the monolithic transistors, perhaps due to larger geometry, I think it's not unreasonable that they could be contributing meaningfully to overall input referred noise of the amplifier.The folded cascode is removed easily by switching to an IC with higher common mode input range. Old OPA2134 simulated OK, despite higher flicker noise. Removal of the 10kΩ resistors increases voltage gain of the differential pair, which gain greatly reduces harm from the integrator's voltage noise. Numerous bipolar parts also simulated well, such as LT1468. Perhaps even NE5534, but I have no models of its low frequency current noise.The current mirror is a more interesting target for elimination, because it operates at much higher current. Unfortunately, this means giving up a lot of voltage gain, raising sensitivity to voltage noise. I don't think there currently exists a single FET opamp suitable for such job, but OP27 types and OPA210 appear workable. Among those, OP37/LT1037 are the fastest that came to my mind. Removal of the mirror permits increase of load resistors from 330Ω to 470Ω.edit: Actually, plugging OP140 into the circuit below (with dedicated higher supply voltage) gives only mild flicker noise deterioration, still better than real world measurements of your build. So not sure why I believed otherwise, but modern JFET opamps could be marginally viable noise-wise without current mirror. But CMIR is an issue.This leaves us with the first cascode, which you want to include for inductive source stability. I'm out of ideas now; its noise could be reduced by darlingtonization (also the current mirror's, by the way) but this eats into the available voltage headroom, precluding the use of OP37. So this is it for now.Regarding plots below,- green is the overall input referred noise- blue is the contribution of parts that can't reasonably be removed- red shows the shape of overall closed loop signal gain

author: David Hess
author_rank: Super Contributor
timestamp: October 12, 2023, 01:50:24 pm
content: Quote from: magic on October 12, 2023, 10:55:56 amBroadband noise depends on the base spreading resistance which depends on the transistor's construction and layout. Integrated transistors can have absurdly low base spreading resistance and associated noise and this was a feature of parts like the LM395 and MAT series. Discrete transistors like the Zetex (now Diode Incorporated) Super E-Line also have very low base spreading resistance and therefor low noise. There is not much information on it, but I suspect ring and perforated emitter transistors also have low base spreading resistance.Transistors with low base spreading resistance and therefor low noise have higher 1/f noise corners but this is because their broadband noise is lower and not because of higher flicker noise. Beyond processing and surface effects, I do not know what contributes to flicker noise. My guess is that low base spreading resistance also leads to lower levels of flicker noise.http://www.dicks-website.eu/low_noise_amp_part3/part3.htmlQuoteJust thinking out loud, but why have load resistances at all? Why not drive the VAS directly, at the inverting input, from the output of the current mirror? Then the operational amplifier's common mode voltage can be fixed at a convenient level.QuoteThe first cascode also controls the drain voltage which has advantages.Does the first cascode, or current mirror, contribute significant noise anyway?

author: MiDi
author_rank: Frequent Contributor
timestamp: October 12, 2023, 02:35:04 pm
content: Quote from: CurtisSeizert on October 10, 2023, 07:06:37 pmWhat a nice project!How was the 3458A configured?Did something similar for an ULF-ULNA prototype - spoiler attached

author: magic
author_rank: Super Contributor
timestamp: October 12, 2023, 04:34:18 pm
content: Quote from: David Hess on October 12, 2023, 01:50:24 pmI'm sure it reduces conversion of base current noise into base-emitter voltage noise.Where exactly the 1/f base current noise itself comes from, I frankly don't know.Quote from: David Hess on October 12, 2023, 01:50:24 pmThis is poor measurement technique, because it passes base current noise through a mere 100μF. Horowitz&Hill used many mF in analogous tests.You would expect this ideal transistor below to have flat noise over frequency, but not if you treat it like that. Similarly, a real transistor with 1/f current noise will appear to have 1/f² voltage noise in that setup, and you can see steeper than 1/f slopes in a few specimens there.Quote from: David Hess on October 12, 2023, 01:50:24 pmYou would have to ask Toshiba if it's significant, I don't have the numbers for these transistors.Sticking to the "Vbe voltage noise" plus "Ib current noise" model, both contribute noise to current mirrors. Vbe voltage noise can be suppressed by degeneration, but Ib current noise simply flows into one or another branch of the differential amplifier, completely uncontrolled. Ditto for cascodes. Ultimate effect is exactly the same as with base current of an opamp connected to the same node, so my logic is simply that these transistors running at 6mA collector current are unlikely to be much more benign that some AD797 or such.Using bipolar current mirror followed by a JFET opamp "to avoid bipolar current noise" is plain and simple cheating. You are dealing with bipolars either way, you have current noise either way, might as well acknowledge this fact and select rationally the least evil bipolar solution.That being said, replacing a current mirror with resistors opens another can of worms, which is resistor excess noise. Unfortunately, I'm not familiar with real world magnitude of that effect, if somebody thinks I'm barking at the wrong tree please correct me. Maybe reducing mirror degeneration would be more productive, for example.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 12, 2023, 05:04:38 pm
content: The input current noise is not just the current noise originating from the input transistor. There is also noise in the current source at the differential stage.Normally the noise of the cacode and current mirror transistors is not that relevant - it is often more the resistors at the current mirror that can be relevant and as it is about current noise larger resistors are better. The 330 Ohm resistors have more noise than most BJTs operated at some 6 mA.For the resistor excess noise it depends on the resistor type. Some are more noisy than others and the datasheets may not give much help as the values given may well be test limits and for the whole resistance range. Usually wire wound are considered nearly noise free and thin film type better than thick film, though it really depends. E.g. I found noticable (~-35 dB noise index) excess noise for PTF56 type thin film THT resistors not better than some thick film ones I had at hand. One the other end for Susumu RR type SMD ones I could not detect excess noise with my setup ( < -50dB noise index). Even the PTF56 resistors are likely OK: maybe comparable 1/f noise to the BJTs but likely less than the JFETs.

author: TimFox
author_rank: Super Contributor
timestamp: October 12, 2023, 05:21:18 pm
content: Note that the relevant noise terms are "noise current and noise voltage referred to the input".The physical noise generators are all over the circuit, but using the gain from the input node to the actual generators allows them to be referred to the input for useful calculations.

author: magic
author_rank: Super Contributor
timestamp: October 12, 2023, 07:43:35 pm
content: Quote from: magic on October 12, 2023, 04:34:18 pmActually, Toshiba gives certain numbers.At 10Hz, HN4A51J datasheet shows 12dB noise figure at 6mA for circa 1800Ω source impedance.Johnson is 5.4nV/rtHz and 12dB more is 21.6nV.Subtracting Johnson, 21nV/rtHz is left. Voltage noise of the transistor is negligible, sub-1nV.Dividing 21nV by 1800Ω (ignoring base spreading resistance) gives ~11pA/rtHz.Repeating the calculation for 1kHz yields 2.2pA/rtHz, and this is consistent with expected shot noise of 15μA base current.So 10Hz is well below the 1/f corner, and 0.01Hz is likely to be almost 32x more: 0.35nA/rtHz.For the NPN we get 3000Ω, 9pA/rtHz at 10Hz and estimated 0.3nA/rtHz at 0.01Hz.Total noise from both pairs is 0.65nA/rtHz. Dividing by 80mS transconductance of the diff pair gives 8.1nV/rtHz equivalent input noise voltage.This is more than contribution of the JFETs at 0.01Hz (per the datasheet and SPICE model).It's a pessimistic estimate, assuming exactly 1/f distribution below 10Hz. Perhaps real world is slightly better, but maybe not much better.Or did I screw up the calculations?I believe I originally got this procedure from The Art of Electronics, and it sounds sensible. I mean, the part about converting NF plots to inand en; the extrapolation to 0.01Hz is a separate matter.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 12, 2023, 08:57:25 pm
content: The calculations sounds OK, though maybe the extrapolation to 0.01 Hz being a bit tricky with the JFETs.The choice of the BJTs does not look that good. The HN4A51 and HN4C51 are not really made for that much current. Noise wise they are best used with more like 0.1 to 0.5 mA, especially for low frequencies.

author: David Hess
author_rank: Super Contributor
timestamp: October 13, 2023, 12:57:41 am
content: Quote from: magic on October 12, 2023, 04:34:18 pmI know where the voltage part comes from. Carriers get trapped in defects causing Vbe to shift, much like the source of popcorn noise, however each defect contributes a very small jump in Vbe for a variable time. Adding up all of the variable times yields the 1/f voltage noise curve.Something similar must be happening to generate the 1/f current noise, maybe having to do with the potential the electrons must jump, like with shot noise?Popcorn noise comes from a single major defect trapping charge causing a large jump, or sometimes a very small number of large defects, and seems to be associated with surface (or interface?) defects. Surface defects can be traced back to improper processing or contamination.The above at least is my understanding as there are few available sources on the subject of flicker noise in transistors. The voltage noise, current noise, and the effects of base spreading resistance are much better described.QuoteI assume the author was interested in audio applications where flicker noise is less of a concern, and he did say he was not interested in flicker noise.QuoteThe current mirror resistors are definitely a source, and must be kept low in value, but would not be required if matched transistors were used.

author: TimFox
author_rank: Super Contributor
timestamp: October 13, 2023, 03:14:58 am
content: Actually, "flicker noise" (pink noise or 1/f noise) is more important at lower frequencies, often below 100 Hz in the audio band.

author: magic
author_rank: Super Contributor
timestamp: October 13, 2023, 04:46:50 am
content: Quote from: David Hess on October 13, 2023, 12:57:41 amDegeneration is required for suppression of the effects of voltage noise of mirror transistors. Everybody degenerates current mirrors . IC designers do it all the time. Mainstream audio design books talk about it.The 330Ω chosen in the design here is actually about the right value, slightly more effective than 100Ω and decidedly better than 33Ω or less. Even 1Ω makes a significant difference, but 1mΩ finally doesn't seem to matter. I seem to recall that the figure of merit is voltage across the resistor (fairly high at 6mA bias) divided by thermal voltage.Note that this is broadband noise only. Real transistors also contribute hell knows how much 1/f, but Toshiba's lousy models don't show it.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 13, 2023, 10:00:04 am
content: The current mirror degeneration resistors contribute some noise, but less noise with larger resistance as it is about the noise current. Larger resistors however need more voltage headroom (higher supply) and with really high voltage drop the excess noise of the resistors can be an issue with some types of resistor. So it can be worth using at least thin film types, ideally a low noise one.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 13, 2023, 04:07:06 pm
content: Quote from: Kleinstein on October 12, 2023, 08:57:25 pmThese may not be the best parts, but among dual bipolar transistors they are almost uniquely easy to lay out for current mirrors and cascodes in diff amps. All the SOT363 duals are a PITA. The SSM2212 is not too bad, but it costs about 20x more, is bigger, and doesn't seem like it would improve things much. It would also only be applicable to the cascode stage. ADIs matched transistors are nice but also ridiculously expensive.I am convinced the excess flicker noise in this relative to simulations is a consequence of me using JFETs harvested from earlier prototypes. I will plug in the board from the previous revision today and run a capture so I can share the FFT from that, which is somewhat better than the simulated noise. I shorted the AC coupling capacitor in that as well, so the noise of the 100M resistor does not come into play. By the way, that HP filter is responsible for about 9 nV/rtHz at 0.01 Hz, and the -3dB point in the captures I showed is also 0.01 Hz. As such, the diff pair contribution is also about 9 nV/rtHz. This sets a limit to the effectiveness of optimization of the diff pair without setting f_c of the input HP filter lower, but with a gain of 501 and supply voltages as they are, this limits the input voltage that won't rail the first stage due to the finite parallel resistance of the caps.I am sympathetic to Magic's point of view that a simpler input stage would be better. Also, reducing the gain of the input stage diff pair to the minimum necessary to ensure the op amp's noise is not a major contributor to system noise would definitely make compensation easier and allow operating the input stage at somewhat lower gain. I also agree with David that a fully differential input stage would be better for practical probing situations, not just those where the inputs are shorted by a relay on the board itself. I will try to get the Github repo up today and link it and include the FFT of the other amplifier tomorrow.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 13, 2023, 09:03:08 pm
content: Quote from: magic on October 12, 2023, 07:43:35 pmI believe the current noises are uncorrelated. I modeled the current noise of one of the cascode transistors as a current source in LTSpice. With an amplitude of 0.3nA for AC analysis, V(out)/501 * sqrt(2) gave 5.8nV, which would of course equate to 5.8 nV/rtHz RTI. That indeed would be significant and would be comparable to the JFETs at that frequency. That current noise, incidentally, is converted to voltage noise with an effective transimpedance gain of 1733 Ohms at the base of the cascode transistors, which I have brought out of the shield with a test point. The voltage gain of noise at the noninverting input at that node is approximately unity. I may try to see how much this matters by probing that point, but I will need to build a second LNA to do so effectively.With regards to sources of excess noise over the simulation, when I initially assembled the board, I did not wrap foil tape around the capacitors, and the drain of an MMBF4117 was connected to the input node, with its gate reversed biased to the negative rail (-4V3). Under these conditions, the noise at 0.01 Hz was in the neighborhood of 20-25 nV/rtHz, My recollection is that removing the 4117s and putting copper foil on the input and first HP filter capacitor had approximately equal impacts on LF noise [Edit: looking over previous data, most of this was from the MMBF4117s, and the foil was for stability - the cap after the first stage appeared to radiate to the 2x12uF AC coupling caps, causing positive feedback]. Moreover, the input JFETs are absolutely not biased close to their zero tempco point, which would require a tail current of about 14 mA * 16 JFET pairs. I haven't done a temperature sweep to see what the input Vos temp co is, but for a first pass calculation, let's say the datasheet figure holds for the drain currents in this design and that the tempcos are symmetrically distributed around zero. This would mean the Vos temco is around 425 nV/K, though it is likely worse, because both of those assumptions are likely false and would tend to underestimate it. The 0.01-1 Hz RMS noise (i.e., that more in frequency ranges where thermal fluctuations happen) is 2.2 nVRMS. As such, temperature fluctuations around 5mK (RMS) over 0.01-1 Hz would likely be sufficient to explain all the noise, assuming the estimated Vos TC is close, not just that which is in excess of the simulation. This is not too difficult to achieve, but such thermal variations only need to account for part of the measured noise, and the TC is probably worse than my back-of-the-envelope calculation. There are also, of course, parasitic thermocouples, which are a bit difficult to quantify but are still undoubtedly important. I have generally taken long captures in a steel box. This isn't critical for short measurements, but it helps avoid things that lead to "noise" such as touching the case while wearing socks, wearing socks in the vicinity of the amplifier, opening the door too quickly, etc. I believe this sensitivity is mostly a consequence of the big PP caps acting as antennas.I have attached a preliminary VSD plot from the previous version of the amplifier. In this case, the 1/f corner is around 1 Hz. The non-inverting input of the first stage is shorted to ground here rather than through capacitors to isolate the effect of the input amplifier. The input stages are the same for the two versions, with two minor exceptions that I know to be inconsequential. The load resistors are 33k in this rather than 10k, and there is no resistor at the source of the PMOS that biases the folded cascode. Layout of the input stages is identical other than the routing of the traces for the input gates of the first stage. The main change was incorporation of the PP capacitors. Previously, I used paralleled 470nF C0G capacitors in place of all of these. In retrospect, the choice of the C0Gs for the HP filters other than the AC coupling one was probably a good choice. The bottom of the input stage is also shielded in this design. Both use BMI-S-230 shields, which have a solid cap rather than a perforated one. With the large AC coupling caps, I no longer had sufficient clearance for the bottom shield without redesigning the BMS board, so I had to remove it, and I had to switch to somewhat smaller shields that only have perforated covers. Also, as I have previously mentioned, the JFETs in this one were new and the ones in the current version had been salvaged. In any event I have not figured out the reason why this is so much better than the current version, but it is also notably better than the simulation. In all likelihood, the BJTs used in this design were adjacent on the reel to those used in the previous one. I'll get a longer capture of the noise floor for this design and add it to this response tomorrow.Edit: As mentioned in a later post, I not longer believe the NSD shown in this post to be valid, so please disregard it.

author: moffy
author_rank: Super Contributor
timestamp: October 14, 2023, 05:15:30 am
content: I have thought that some RF transistor pairs would make good low noise transistors for the audio range because they need a low Rb to be effective at RF e.g.https://au.mouser.com/datasheet/2/302/BFU520Y-3138076.pdfCan anyone elucidate as to whether that assumption is correct or false?

author: magic
author_rank: Super Contributor
timestamp: October 14, 2023, 07:03:53 am
content: Quote from: CurtisSeizert on October 13, 2023, 09:03:08 pmThat's quite sensitive.Regarding offset and drift distribution, in theory they should be symmetric around zero if the internal layout of the chip is symmetric. But the datasheet shows shifted distribution of offset voltage, so it's right to be suspicious about drift as well. What can break such regular asymmetry is installing half of the chips rotated 180° to swap the sides, which you seem to have done already. It could be better to use checkerboard pattern, or any other where the "center of mass" of each group is exactly in the same point.Another potential source of offset and drift is base current of the mirror, but I haven't tried calculating if its influence is worth worrying about.Quote from: CurtisSeizert on October 13, 2023, 09:03:08 pmThis looks very good and given what we believe about significance of the BJTs, it seems to imply their current noise may be better than worst case estimates.

author: moffy
author_rank: Super Contributor
timestamp: October 14, 2023, 10:19:48 am
content: I don't know how how accurate the BFU520D model is or how well my circuit is for testing but here is the result.

author: Roehrenonkel
author_rank: Frequent Contributor
timestamp: October 14, 2023, 10:40:32 am
content: Hi moffy,Quote from: moffy on October 14, 2023, 05:15:30 amYes that's true. I've seen a lot of MC-PrePreamps (Phono) with HF-transistors.Rb (internal) is contributing much to the noise.Best regards

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: October 14, 2023, 02:20:57 pm
content: Quote from: magic on October 14, 2023, 07:03:53 amI have found that TI sometimes turns Vos TC values into absolute values in their datasheets, and I believe their usual practice for typical values is to report typical as one standard deviation from the mean. They explain this in the OPAx205, and other, datasheets. Unfortunately, this leaves one to wonder what the typical value actually refers to in some cases. For the delta_VGS they have a histogram that does show it not to be centered around zero. For the pinout at least, the clamping diodes break rotational symmetry. I considered doing a checkerboard pattern, but in the end I was too lazy. Some of the FETs are turned in such a way as to minimize the trace length to the gates of the inverting input and keep parasitic capacitance to a minimum for stability. The first stage output centers around 280 mV with no signal, so the Vos of the amplifier as about 560 uV. This is remarkably close to the simulated value (about 250 mV), so a large part of the offset may be base current from the mirror transistors. Changing the emitter degeneration resistor to 332 for the diode-connected transistor would get pretty close to compensating this without recourse to additional bodgery. At a drain current of 400 uA, the mean delta_VGS is probably closer to zero, based both on the datasheet graph of delta_VGS vs drain current and my own testing of 42 of these at a drain current of 500 uA. At this lower drain current, the mean delta VGS was 139 uV, so I expect most of the offset is due to mirror base current. Regarding the TC, I can say anecdotally it is better at higher drain currents (as assessed by warm up drift), but I don't remember if this was symmetrical, and I did not record the values before they settled.As promised, here is a better FFT comparing the noise floor spectra for the two revisions. I mentioned the relevant changes in my previous post. I added some more data I had gathered. The orange and green spectra were taken from captures on my 34465A using the front panel digitize function. They were also taken with 30k loads on the folded cascode. I wouldn't put a lot of stock in the low frequency part of the green trace at the moment; it isn't consistent a lot of the behavior I have seen, and I would need to repeat it with a longer capture to confirm an effect. These spectra contradict some of the earlier things I said about shielding and the influence of the input HP filter, which I must have remembered incorrectly. I will edit my previous posts to fix this. I spent a good deal of time trying to track down the source of the excess LF noise in this revision, but some of that effort was not very well organized. I have made the general observation that the previous amplifier is less prone to oscillation, and it is definitely less sensitive to environmental stimuli, like touching the case. The spectrum in my previous post was just the amplifier sitting out on the bench. No additional shielding necessary. I put it in a box for the longer capture because it takes a long time to run.Edit: I don't believe the NSD trace for the "Previous Revision" amplifier noise floor to be correct due to sporadic behavior when trying to confirm the gain. Any conclusions from those data in this post should be considered suspect as well.

author: NWerner
author_rank: Contributor
timestamp: November 14, 2023, 09:33:57 pm
content: Could you explain/speculate how it is possible to obtain much lower "frequency knee" as compared to the datasheet where the knee occurs at the vicinity of 10Hz? It always was my understanding that (broadband) noise is very well characterized by datasheet values. But maybe the situation for 1/f noise is different?!Are these graphs limited by test equipment or there some aspect of the design I am completely missing?Thanks a lot for making this really cool project publicNoman

author: Kleinstein
author_rank: Super Contributor
timestamp: November 14, 2023, 09:47:47 pm
content: The actual LF noise powerformance can vary quite a bit between parts, while the white noise part is usually much more consistent. There can also be small process changes that may improve things - they would counteract if it gets worse, but hardly if the get better. So there is a chance later part can get slightly better.Another point with the LF noise is that thermal effects can be a part of it also in the tests for the data sheets. A good thermal design (sometimes also by pure luck) and symetry in using multiple parts in parallel can help. When it comes to thermal effects a symmetric layout can make 4 FETs combined much less sensitive to thermal effects.

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: November 15, 2023, 01:32:20 am
content: If you hide the 1/f noise under enough white broadband noise,you can push the 1/f corner arbitrarily low. All in all, that is noreason for joy. The corner frequency as such is no real value,it depends on the absolute amplitudes, too.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 15, 2023, 09:22:55 pm
content: I apologize - the measurements I took for the "Previous revision" amplifier (the one with the very low 1/f knee) are suspect, and I don't believe them to be correct. I will make the appropriate annotations to the prior posts where I mentioned that.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 15, 2023, 11:05:08 pm
content: I built a second one of these amplifiers, this time using a 2k49/4R99 divider (rather than 1k/2R) for the input stage. This was indeed beneficial for stability. The noise floor from this second amplifier was a bit higher as a result (640 pV/rtHz rather than 600), but the LF noise was indistinguishable. I also changed one of the load resistors from 330R to 332R and rotated half of the JFE2140s in a checkerboard pattern to account for the non-zero average Vos and VosTC (Credit to Magic for this suggestion). I have tested this second amplifier extensively and I'm pretty confident in its performance, especially since it is so close to that of the first one. There is one thing to note that I realized during this testing. The -3dB point for the 0.01 Hz HP filter is actually about 12.2 mHz rather than 10 mHz. This is because I had originally designed the filters with 4.7 uF capacitors, where a 4.7uF/10Meg HP filter would be comfortably below 10 mHz, so it would not be a big issue. I did not update this resistor when I changed to 2.2 uF capacitors. The usual measurements with LF use a first order high pass, so I will move the Fc of the first high pass filter down far enough that it remains first order in the region of interest (>10 mHz). By the way, the 0.01-10 Hz filter envelope I attached looks like there is some passband ripple, but I wouldn't put too much stock in this. With a 2 mHz starting frequency for that sweep, it was necessary to reduce the averaging, etc. to a minimum to keep the sweep inside of a day. With the 0.1 - 10 Hz Bode plot, I used more averaging and there was no passband ripple. The measured THD varied inversely with gain for the 0.01-10 Hz plot, so I am guessing there was some interfering signal that couldn't be rejected well with the measurement parameters for such a LF sweep.Also, I dug into the current noise line of reasoning, and I am a bit confused. If someone can point out errors in my reasoning, that would be helpful. Here's how I am thinking about this: I believe the cascode situation is analogous to the AoE3 chapter 8 section about current noise in the BJT current source, which also uses a common base configuration. The gos of the paralleled JFETs is large compared to r_e of the npn, so there should be no emitter current noise (at the limit of high beta). There should be current noise at the base, of course, which would appear as voltage noise at low frequency due to the dynamic impedance of the 3 series diodes used to set the bias of the cascode. With the 28k7 resistor to Vcc in the schematics, the current running through those puts the dynamic impedance around 1.7k, but this voltage noise would be applied to the bases of both transistors, and would be rejected as common mode noise. To see if the this current noise was actually causing problems, I swapped the 28k7 resistor for a 7k68 resistor, bringing the dynamic impedance down to 350 Ohms (simulation). This had no impact on the noise of the amplifier. Also, shouldn't the shot noise be proportional to Ic/sqrt(beta) rather than Ib?If the Toshiba model is not reflecting the 1/f character of the voltage noise of the transistor, which they definitely are not - it is a flat NSD with their model, the 1/f corner would still need to be >1 kHz for this to impact the amplifier, assuming their model for the broadband noise density is accurate.Ultimately, I think the divergence of the LF noise from what was predicted in the simulation is more likely a consequence of inaccuracies of the SPICE model TI put out for the JFE2140. This wouldn't even be the only error in their model - they have VTOTC as 0.45m, which is definitely not accurate. Their values of VTOTC and BETATCE do not make it possible to achieve zero tempco biasing in simulation, though my measurements of actual parts puts the zero tempco Vgs around 320 mV, which is around the 0.6V higher than VgsOff that one would expect for JFETs in general.Edit: Added the Bode plots I mentioned.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 15, 2023, 11:36:21 pm
content: For the shot noise Ic/sqrt(beta) and Ib should be the same - this is how beta is defined. Usually the difference between the large signal and small signal numbers is not that relevant.The gos / re argument applies to the votlage noise and current noise * base resistor. However the current noise at the base also means there is a corresponding current at the emitter or collector. So the current noise would still matter relative to gm.It is a bit unusual that the current noise is supposed to get so bad with the toshiba part at higher current. This may be a thermal effect, that could be different with a lower CE votlage or layout.The models for 1/f noise are often not very accurate.

author: magic
author_rank: Super Contributor
timestamp: November 16, 2023, 05:04:34 pm
content: I believe current noise can be modeled as a random AC current between base and emitter.The base side is not a big issue - it flows into the base bias circuit which isn't very high impedance (I presume), it's common mode if both cascode transistors share the bias circuit, and it only results in drain voltage variation which modulates drain current by the relatively low drain output admittance.The emitter side is an issue - it simply flows into the drain, it's not correlated between the two sides, feedback loop counters it by a differential input voltage variation equaling noise current divided by differential pair transconductance. Same for noise current from mirror transistors, opamps and anything else connected with the drains.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 16, 2023, 09:06:14 pm
content: I believe I understand now. The section in AoE I was reading (Ch. 8.3 I think) is worded in an (uncharacteristically) obtuse manner, but ultimately by KCL that base current's gotta go somewhere (as Kleinstein pointed out), which I lost sight of as I got lost in the weeds. From a quick simulation, the RTI contribution of the base current noise to the noise of the stage as a whole is about i_n * 19.2 Ohms (from modeling one transistor and multiplying the result by sqrt(2)). It may actually be as bad as the worst case analysis of 0.35 nA/rtHz - the ~9.5 nV/rtHz in the spectra is actually around 15 nV/rtHz if you consider the filter envelope. Getting rid of that noise source would bring it down to 13.2 nV/rtHz at 10 mHz. I feel like the best way to deal with this is to just rig up a test jig and run the experiment. I'll probably do a simple long tailed pair approach due to the low frequency requirement and because I can adapt something I've already built. If it's bad, I could pop another JFE2140 in (with appropriate biasing modifications) instead of the NPN pair in a revision.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 16, 2023, 09:38:40 pm
content: There is not need to use JFETs for the cascode. There are considerably better NPN transistors when it comes the the current noise. The HN4C51 is just not made for so much current. Alone using less current per transistor may improve things quite a bit.If this is not enough darlington transistors would be an option too, with naturally less base current.

author: magic
author_rank: Super Contributor
timestamp: November 16, 2023, 11:26:39 pm
content: I think you could measure exact current noise of an individual BJT in a fairly simple test jig: ground the collector, ground the base through 1kΩ, pull 6mA from the emitter. Measure emitter voltage noise with your AC coupled LNA.Since we expect tens to hundreds pA/rtHz, the resistor will make it same number nV/rtHz, comfortably above its own Johnson noise, transistor's voltage noise and the noise floor of the LNA.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 17, 2023, 06:17:54 am
content: Quote from: magic on November 16, 2023, 11:26:39 pmGood point. I might as well put the LNA to work. I rigged it up, and I'll take some spectra tomorrow.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 18, 2023, 08:01:55 am
content: So I built up the test jig using one half of an HN4C51J (E2 and C2 open). The collector was connected to the positive terminal of a 9V battery, and the emitter was connected to the negative terminal through a 1k395 resistor. The base was tied to the collector via a 6k745 resistor, and V_noise was taken between the emitter and collector. In operation, Ie was 5.967 mA, Ib was 22 uA (beta = 266). To get the voltage noise at 10 mHz, I extrapolated back using (averaged) numbers at 0.1 and 1 Hz (255 and 85.2 nV/rt Hz, respectively). The amplitude goes as 1/(f^0.48) over this range. This gives 765 nV/rtHz at 10 mHz, which equates to 113 pA/rtHz or a NF of 37.2 dB. I assumed here that the voltage noise of the transistor itself was negligible here, which is probably reasonable given that Rs >> r_bb + r_e.Applying this to the LNA input stage, using the quick calculation of i_n * 19.2 Ohms, 113 pA/rtHz would give 2.1 nV/rtHz RTI, or a 1% contribution to amplifier noise for both cascode transistors. As to the source of the discrepancy with Magic's calculations, with this configuration the 10 Hz NF is 8.6 dB with ~6.8k, vs. maybe 15 dB in the datasheet (Toshiba uses a common emitter amplifier with Vce 6V).

author: magic
author_rank: Super Contributor
timestamp: November 19, 2023, 09:34:11 am
content: Interesting result and a nice transistor.1/f corner is a decade lower than specified by Toshiba. 12pA/rtHz at 1Hz is only 10dB above OP37/LT1037, despite 50x higher collector current. It seems that good discretes can have a meaningful advantage over IC opamps in this area.So it's still unclear where the unexpected noise comes from? I suppose you don't know what setup TI used to produce the datasheet figures?editWhat software are you using to produce these plots? I'm trying to do some noise measurements and already wrote an Octave/Matlab script for it, but I'm not 100% confident in my DSP skills so it would help me to compare against known-good solutions.

author: David Hess
author_rank: Super Contributor
timestamp: November 19, 2023, 04:13:32 pm
content: Quote from: magic on November 19, 2023, 09:34:11 amPrecision parts like the OP07/LT1001 and OP37/LT1037 implement input bias current compensation so they have much higher input current noise than their input bias current would indicate. For a fair comparison, use a precision part that lacks input bias current cancellation like the LT1006, or make the comparison with an integrated monolithic part like the LM395 or MAT series transistors.I never really looked into it, but maybe the added noise from the input bias current cancellation is less than the added noise of using a balancing resistor on the non-inverting input. Operational amplifiers that have input bias current cancellation do *not* benefit from balanced source resistance to reduce offset, although having a balanced impedance at the inputs reduces noise *if* the input bias current noises are correlated which is the case with some parts. The LT1028/LT1128 are like this so I suspect the LT1027/LT1037 and entire LT line are also.

author: eleguy
author_rank: Regular Contributor
timestamp: November 19, 2023, 04:34:05 pm
content: This is clearly not a "budget" project but good work overall! I did not fully yet check the (github) schematics but at least PSU section could need some attention from the protection point of view that you have nicely started. MBR0540 V_RRM(min) is rated 40V but the caps are 35V and at least LT30402 absolutely max is only 22V. MBR0520 - which could be safer call - has same footprint (if I remember correctly). Well, one could play certainly even safer with some other brand Schottky.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 19, 2023, 04:37:18 pm
content: The input current noise specs for some OP-amps is also strange. E.g. for the OP27 and quite a few other they assume anti correlated noise. The correlated part is not included and uncorrelated is underestimated in the measurement they descirbe for the specs. So the actual noise specs can be worst.There are more sources to the current noise in an OP-amp than just the input transistors. The current source to drive the long tailed part is such a source that produces correlated current noise. The comparison of an OP-amp to just 1 transistor is not really fair.The other point is the different current level - in the LNA the transistor operates at a high current, well outside the sweet spot for the transistor.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 19, 2023, 11:09:18 pm
content: Quote from: magic on November 19, 2023, 09:34:11 amI just use python - scipy for the FFT and matplotlib for the plots. Pandas for the csv stuff. Here is the code, but it is not pretty. I am ashamed to admit I usually just edit the display_spectrum function as needed. I have noticed that there is some dependence on how the lower end of the spectrum looks for different values of nperseg with the signal.welch function. It may be more accurate to make it correspond to more than two periods for the lowest frequency, but this is a good compromise between resolution at the low end and jaggedness at the top end. Also, the range of csv formats it accepts is pathetic. I don't know how to make that part better and I haven't really had the motivation to learn. Nonetheless, when I have checked this against datasheet plots or the implementation in Waveforms (for the ADP3450), it is reproduces them well. The Digilent spectrum analyzer seems to give a gain error of -12% very consistently, but when I export the time domain data from the scope and analyze it in python it gives accurate values of NSD, so it's not that the front end is out of calibration. I don't know why this is, so I only really use that FFT implementation if the absolute values don't matter.Code:import pandas as pdfrom scipy import signalimport numpy as npimport matplotlib.pyplot as pltclass Wave:df = []timeseries = []gain = 1sfreq = 0timestep = 0vsd_smoothed = []freq_smoothed = []interval = 0vsd_check = []freq_check = []#voltnames and secnames are given as lists to enable matching with variously labeled#and formatted input datavoltnames = ["v", "volt", "volts","voltage"]secnames = ["s", "sec", "seconds", "t", "time"]def __init__(self):self.fft = pd.DataFrame(columns = ("psd", "vsd", "freq", "dBc"), dtype = float)def readCSV(self, filename):self.df = pd.read_csv(filename, skipinitialspace = True, usecols = lambda x: x.lower() in self.voltnames) #Populate dataframe from csvself.df = self.df.assign(nV = self.df.mul(10**9)/self.gain) #convert volts to nVself.df = self.df.rename(columns={self.df.columns: "V"}, errors="raise") #update column labelself.timeseries = pd.read_csv(filename, skipinitialspace= True, usecols = lambda x: x.lower() in self.secnames, nrows=1000) #Get limited timeseries dataif self.timeseries.size > 0:step = self.timeseries.diff()[self.timeseries.columns].mean() #calculate the average difference between timesself.set_timestep(step) #set timestepdef save_trace_to_csv(self, filename):self.df.to_csv(path_or_buf = filename, columns = ["V"])def save_fft_to_csv(self, filename):self.df.to_csv(path_or_buf = filename, columns = ["vsd", "freq"])def set_timestep(self, timestep):self.timestep = timestepself.sfreq = 1/self.timestepdef set_gain(self, gain):self.gain = gaindef set_sfreq(self, sfreq):if sfreq <= 0:print("Error: Invalid Frequency")return 1else:self.sfreq = sfreqself.timestep = 1/self.sfreqreturn 0def calc_fft(self, f_low):if self.df.size == 0 or self.timestep == 0:return 1nperseg = 2*(1/(f_low*self.timestep))self.fft["freq"], self.fft["psd"] = signal.welch(self.df["nV"], fs=self.sfreq, nperseg = nperseg, window="hamming", average="median")self.fft["vsd"] = np.sqrt(self.fft["psd"])def calc_rms(self, f_low, f_high):i = int(0)rms = float(0)freq_step = self.fft["freq"] - self.fft["freq"]while self.fft["freq"] < f_low:i += 1while self.fft["freq"] <= f_high:i += 1rms += self.fft["psd"]*freq_stepreturn np.sqrt(rms)def carrier_dens(self):return max(self.fft["vsd"])def display_spectrum(self, title=None):plt.figure(dpi=600)plt.plot(self.fft["freq"], self.fft["vsd"])plt.xscale("log")plt.yscale("log")#plt.ylim(top=10,bottom=0.1)plt.xlim(left=9,right=18)plt.xlabel('frequency ')plt.ylabel('Linear spectrum [nV/rt Hz]')plt.grid(visible=True, which="both", axis="both")plt.title(title)plt.show()def average_readings(self, numavg):self.timestep = self.timestep*numavgfor i in range(0, int(len(self.df["nV"])/numavg-1)):avg = 0for j in range(0, numavg):avg += self.df["nV"][i*numavg + j]self.df["nV"] = avg/numavgavg = 0def plot_tdomain(self, time_start, time_stop, title):time = []nv = []lastpt = int(time_stop/self.timestep)firstpt = int(time_start/self.timestep)for i in range(firstpt, lastpt):time.append((i-firstpt)*self.timestep)nv.append(self.df["nV"])i += 1plt.figure(dpi=600)plt.plot(time, nv)plt.ylim(top=510,bottom=480)#plt.xlim(left=0,right=time)plt.xlabel('Time (s)')plt.ylabel('nV')plt.grid(visible=True, which="both", axis="both")plt.title(title)plt.show()ppnoise = max(nv) - min(nv)print("Peak to peak noise (nV): ", ppnoise)w = Wave()w.set_gain(10000)w.readCSV("Experiments\HN4C51_6k745_Rs_50SPS_128kSa.csv")w.set_sfreq(50)w.calc_fft(0.01)TI has a datasheet figure about how they measure the AC parameters, including NSD. I took a screenshot and attached it.As for the noise sources, I have not checked the PNP duals (HN4A51). The current noise from that could be problematic. However, this is otherwise a very good transistor for current mirrors because it has as high an Early voltage as any small-signal PNP transistor I am aware of.I took some more spectra for the HN4C51, and I was able to get a NF of about 2.5 dB with Rs = 1 (Ie had dropped to 5.68 mA at that point from battery discharge), so I played around with the model a little bit to get it to better reflect what I had seen. The one below reproduces the noise spectrum with Rs = 6k745 very well, but it is a bit too optimistic with the 1/f noise at Rs = 1R00. I added a value for KF and increased RB to 35. I added AF=1, which is the default value, though my calculation of the 1/f slope suggested 0.95. But the limited data I was working with, it seemed a bit shaky to reject the null hypothesis there. I wouldn't take this as gospel, but Toshiba hasn't gone to the trouble, so here we are. To be fair to Toshiba, the KF parameter is used in none of the BJT models included with LTSpice. The default value is zero, so none should show 1/f noise. I tested a few to check this, and all had flat NSD at low frequency.Code:.MODEL HN4C51 NPN(+ LEVEL = 1+ Kf = 0.0085f+ Af = 1+ IS = 1e-013+ BF = 350+ NF = 1+ VAF = 276.3+ IKF = 0.26+ ISE = 1.37E-012+ NE = 1.8+ BR = 2.3+ NR = 1+ VAR = 100+ IKR = 10+ ISC = 2e-010+ NC = 1.6+ NK = 0.58+ RE = 0.2+ RB = 35+ RC = 0.12+ CJE = 1.435E-011+ VJE = 0.75+ MJE = 0.33+ CJC = 5.714e-012+ VJC = 0.74498+ MJC = 0.22504+ FC = 0.5+ TF = 4.6e-010+ XTF = 10+ VTF = 5+ ITF = 0.1+ PTF = 0+ TR = 10E-09+ EG = 1.11+ XTB = 1.4+ XTI = 4+ TRC1 = 0.01+ TNOM = 25)I think the major discrepancy between the simulation and reality is due to TI's model being too optimistic. With this bare-bones common source amplifier in LTSpice to check the noise (and compare with datasheet values), The 1/f corner is about 3 Hz, and the NSD at 100 mHz is only 6 nV/rtHz. Compare that to the datasheet noise spectral densities, where the 1/f corner is closer to 20 Hz. Simply editing the value of KF in their model from 0.2e-18 to 2e-18 actually gets you pretty close to the datasheet, but those spectra are too pessimistic. If you plug values into my LTSpice model, you can get an upper bound on KF of 0.5e-18 based on comparison to my data, and with two of these amplifiers built and tested (with indistinguishable 1/f noise), that is averaging 32 pairs of JFETs. That said, the noise figure of the JFETs in this topology is the matter at hand, so it is probably best to build something up to test it with less uncertainty. Perhaps rigging up one as a follower with a drain current of 400 uA would do the trick - the NF should be ~9 dB through the whole spectrum (a bit less because of Rg above the 1/f corner) and there's no issue of calibrating the gain.Edit: Attached screencaps of the LTSpice simulation and the datasheet noise spectra.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 19, 2023, 11:57:26 pm
content: Quote from: eleguy on November 19, 2023, 04:34:05 pmMuch obliged for the review - I was hoping to get more criticism of elements outside the input stage. This is a hobby for me, so I don't really know all the industry best practices for power protection. The least safe part of the whole thing is definitely the battery. If the clips go on crooked, as they sometimes do, there is a possibility of shorting two cells together when you are popping one in or out. I have dealt with this on the current design with polyimide tape on the suspect ones, but this is not ideal. Keystone makes another variant for 21700 batteries that is plastic with leaf-spring type contacts, but they cost like $7 each in small quantities.I don't know if a BQ77915 is appropriate as the only level of battery protection. Most of the decisions in that board were aimed at minimizing battery drain current while it is off. This necessitated a somewhat elaborate scheme for pulling the PRES pin high if the power switch is on or it is plugged in. I actually used a non-latching relay for the plugged in part because I had run out of patience for designing the nuts and bolts elements.The charge cycle is actually terminated by OVP from the BQ77915, which was not my intention when I designed it. I need to investigate this because it is annoying, but it doesn't seem to be due to an overvoltage event on any of the cells or the pack as a whole.This maybe wouldn't be obvious to someone who hasn't made one (and destroyed a battery board), but there should be a polyfuse or something on the GND connection to protect against accidentally shorting the shield frame to some other point on the battery board (BATT- was the culprit for me). In a future revision, the connection with the charger board (the rear panel) will be board-to-board so it doesn't rely on a wire harness to hold it in place. I will still use the Molex microfit connectors for that, so there is a positive lock.I had not considered a lot of power rail protection to be necessary other than battery reverse polarity protection. The Schottky diodes are there in case one power rail fails or a regulator goes into OCP so the -4V3 rail does not pull the +5V4 rail far enough below GND to cause immediate trouble. I hadn't thought of them for possible overvoltage protection, but that may be worthwhile for instances like testing the board with a bench supply. I think I might need Zeners there though (in addition), because the LP2985 won't suffer more than 18V. The 35V Ta caps on the inputs are probably overkill. With 12V Zeners, I could just use more of the 47uF/16V molded Ta caps I use elsewhere.

author: David Hess
author_rank: Super Contributor
timestamp: November 20, 2023, 01:56:50 am
content: Quote from: CurtisSeizert on November 19, 2023, 11:09:18 pmThe RBW (resolution bandwidth) of the measurement needs to be used to adjust the measurement to nV/SqrtHz. This varies with FFT bin width and window function.

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: November 20, 2023, 06:14:06 pm
content: I always had these stability problems with the negative real part of the amplifier input impedance and tried to avoid feedback. Since gm goes with the square root of the drain current, I fed the source from a CCS with large electrolytics to force AC GND, much like the test circuit above. That was a complete disaster; on the output I could see nearly every electron that defected through the capacitor.Oscons were worst; they created a noise corner in the 10s of KHz, and it was steeper than 1/f. I admit they were quite old. My FFT analyzer thanked with ADC overflows. Nippon Chemical high voltage ALU electrolytics were much better but still unusable. The only thing that kinda worked was a wet slug tantalum by AVX 4700u / 25V for ~ €100. At maybe half a volt of working voltage. Sprague ask for twice the price, btw. The corner was still at 30 Hz or so. These wet slug tantalums show a series resistance in strong contrast to the price.cheers, Gerhard

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 20, 2023, 07:21:31 pm
content: Preliminary data from the JFE2140 test shows I may have been wrong about the model. The 1/f corner of these things is insanely low, like a decade below what you would come up with from looking at the datasheet NSD curves. I am rerunning the calibration curves with more points to get decent looking curves down to 10 mHz, but I have attached the preliminary results, but approach these with some caution until I rerun the noise floor calibration and the 240R calibration. I have also attached the schematic of the test jig. Getting good LF spectra with this required me to put a towel and some foam insulation over the metal shielding box the whole setup was placed in. Within the shielding box, I put some lint-free wipes and a digikey bag over the JFET itself. The whole box had to be closed for about an hour before it would really settle. The Vgs tempco at this drain current is very significant compared to the noise of the JFET.I think the degradation of the SNR of the LNA at low frequencies tells the story here - Magic and Kleinstein were right that the input stage is leaving a fair amount on the table below 1 Hz. This was an effect I saw in preliminary captures as well without targeting low frequencies, so this is not a fluke result. Also, I am confident in the accuracy of the data coming from this test setup, but I think that results like these warrant some additional checks, probably with n>1 for DUTs. This will take some time as each capture is 6 hours and settling is pretty significant on top of that. Also, it seems like TI is really burying the lede in the biggest way possible by reporting the NSDs they do in the datasheet and having their model give a truer representation of the exceptionally low 1/f corner of the JFET pair. Also, I don't have the spectrum saved, but the wideband noise is right where we would expect (with noise floor correction of the LNA) - 1.6 nV/rtHz.Edit: Reattached the spectrum.

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: November 20, 2023, 09:30:28 pm
content: That's unfair. 33 People have seen the Noise Spectrum Density, and I get "404 - attachment not found"Edit: yes, it is re-attached, thanks!

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 21, 2023, 11:54:25 pm
content: My results with better spectra for noise floor subtraction remained consistent with the ones I reported before. I attached the NSD down to 10 mHz. Recall, though, that the HP filter envelope gives somewhat greater than 3 dB attenuation at 10 mHz, hence the change in slope. As a verification of the technique for subtracting the noise floor of the instrument at relatively low SNR, I repeated the procedure with the internal 240R noise reference. It was 291 K during the capture, so the NSD should be flat at 1.97 nV/rtHz. For readability, I did some smoothing with splines (scipy.interpolate), but I kept this to a minimum and made sure that the result accurately captured the unsmoothed curves. There is an uptick in SNR for the JFE2140 at very low frequency, but I don't think that is increased noise of the JFE2140 near 10 mHz. It is probably an artifact of trying to measure single digit nVRMS noise for a Vgs with close to a 2 mV/K tempco. I may use a differential source follower measurement to cancel most of this temperature coefficient and give me 3 dB more SNR for future tests. By the way, the source resistor (12k) here is large enough to keep the follower close enough to unity gain for what we are doing - with gm of 4 mS, the voltage gain is 0.98.As for design modifications of the amplifier that would not degrade the inherently low 1/f noise of the JFET pair, I am testing deletion of the current mirror right now. The current mirror actually gives very little increase in gain for the differential pair stage, and when you think about it, this makes a lot of sense. Any increase in the load impedance for the differential pair loads the emitters of the folded cascode, and when that load impedance is >>r_e, the effect approximately cancels. From simulations, the differential gain was 61.49 dB without the current mirror and 64.02 dB with them in. If you need that 2.5 dB back, which you don't, all you need to do is increase the load resistors for the folded cascode. This is doable because without the current mirror the phase margin is much better - about 90 degrees at a gain of 500 (it was about 65 degrees before, from memory). The point of this was to get rid of the current noise from the mirror, but even if that does not turn out to be the case the design is better without it.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 22, 2023, 06:24:16 am
content: Deleting the current mirror did the trick. I appreciate the help on improving the design.

author: David Hess
author_rank: Super Contributor
timestamp: November 22, 2023, 07:11:41 am
content: Quote from: CurtisSeizert on November 22, 2023, 06:24:16 amDo you mean that you removed the current mirror at the output of the folded cascode?Quote from: CurtisSeizert on November 21, 2023, 11:54:25 pmRemoving the current mirror halves the transconductance. Does this alone explain the better phase margin?For ICs removing the current mirror also removes its parasitic capacitances, however this does not apply in a discrete design.The reduction in transconductance, removal of parasitic capacitances, and lower noise explain why high performance operational amplifiers typically do without a current mirror on the first stage. I now wonder why a current mirror would be used at all; does it have any advantage?

author: magic
author_rank: Super Contributor
timestamp: November 22, 2023, 09:36:00 am
content: It is my recollection that there was no mirror under the folded cascode, only resistors. Current mirror was used to load the JFET pair.It's curious that 3dB improvement near 0.1Hz is better than predictions based on measured HN4C51J base current noise. Maybe the complementary PNPs are noisier, or maybe the mirror had other problems too. One suspicious thing about it is the asymmetry of both base currents flowing into one drain; this not only causes offset but also makes the mirror sensitive to β drift (for any conceivable reason, perhaps temperature fluctuations, perhaps caused by LTP bias drift).OPA627uses Darlington drivers (running on lean bias themselves) to merge individual mirror transistor base currents back into their corresponding collector currents.Combination of current mirror and folded cascode can be redundant indeed - the FC already sets a constant voltage across drain resistors and hence constant current too. It only needs to be ensured that input resistance of FC emitters is order of magnitude lower than the value of drain resistors for more than 90% of drain AC current to enter the cascode. Since FC operating current can be set lower than the differential pair's, high load resistance and gain become practical.From noise perspective, folded cascode looks like a differential pair - its base current noise flows (from emitters) into the drains, its differential voltage noise is impressed (by emitters) on drain resistors. Stability concerns aside, I would expect best results when folded cascode bias is adjusted for optimum noise figure with given drain resistors, particularly minding low frequencies. Possibly a well tuned implementation could outperform bipolar IC opamps, which was my own suggestion a few weeks ago. Not sure if a monolithic PNP pair would be advantageous, but there is a theoretical concern about asymmetric Vbe drift modulating drain resistor currents differentially.Lastly, the folded cascode could replace the main cascode in its role of determining drain voltage and reducing drain voltage swings and Miller effect (the likely reason why adding the main cascode reportedly improved stability). However, it must be said that as long as the FC operates at lower current than the diff pair, its emitters will never have as low input resistance as a straight cascode and hence Miller elimination may be less effective. And I suspect some modifications could be necessary to the biasing and folded cascode servo circuitry.editA random idea: use a current mirror, bias folded cascode bases to constant voltage, use the servo opamp to control current mirror bases instead.Expected outcome:1. Asymmetry of mirror base current is eliminated, it all flows into the opamp.2. Base current noise remains a concern (appears at the drains by subtraction from collector currents).3. Impedance seen by folded cascode emitters increases, decreasing any effect their Vbe drift or mismatch may have.Depending on whether mirror current noise or other factors are dominant, this may be better or it may be worse

author: Kleinstein
author_rank: Super Contributor
timestamp: November 22, 2023, 03:45:16 pm
content: The main point of the current mirror is to combine the differential signals to one current signal to use compensation with a mittler capacitor or similar. It is a nice way to get the sampe current on both sides.With the OP-amp as a kind of differential integrator one does not really need the current mirror.On the other side a well designed current mirror (low noise transistors and not too small emitter resistors - the larger the resistors the lower the noise, but also more voltage needed) the noise from the current mirror should be small compared to the JFET or other differential stage noise. Similar the kascode tansistors add a tiny bit of noise, but normally not significant. Usually it is not so much the transistors at the current mirror but the emitter resistors that add some noise, though still smaller than the main input transistor pair. Alternative forms like folded kascode or 2nd differential stage would also need similar resistors - it is only for high frequencies that an inductor can be a real option.In this case it looks like the HN4C51 transistors are not really low noise at the high current, at least not from the graph in the datasheet.

author: magic
author_rank: Super Contributor
timestamp: November 22, 2023, 04:42:37 pm
content: Quote from: David Hess on November 22, 2023, 07:11:41 amQuite several modern TI opamps have active loading shown on simplified schematics: OPA827, OPA140, OPA209, OPA210, OPA211. These schematics certainly hide a lot (look at OPA627), but I doubt that they lie about active loading.Possible benefits include:- higher 1st stage output impedance and less sensitivity to 2nd stage voltage noise or nonlinearity- increased overall open loop gain at low frequencies and DC- lower voltage drop and wider common mode input range- a transistor pair may take less area than long resistorsAll except the last may be relevant to discrete amplifiers.

author: David Hess
author_rank: Super Contributor
timestamp: November 22, 2023, 05:02:00 pm
content: Quote from: magic on November 22, 2023, 04:42:37 pmSince open loop gain at low frequencies is limited by thermal feedback, I wonder if active loads matter here anymore. Once thermal feedback is accounted for, then it might matter.The space saving would certainly matter for a gain cell type of application (324/358) where area (price) is everything.Precision bipolar designs include input bias current cancellation which raises the input noise current anyway, so added noise from the current mirror would matter less.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: November 22, 2023, 08:34:48 pm
content: Quote from: David Hess on November 22, 2023, 07:11:41 amThe current mirror I deleted was Q27 in the attached screenshot of the schematic. The current mirror was vestigial, like an appendix; it was necessary for high gain in the design iterations before inclusion of the folded cascode, and I kind of took its presence for granted after that. I don't think it has any advantages - the 3dB gain difference is recoverable by increasing the loads on the collectors of the folded cascode, and the gain is high enough as it is. I haven't really dug into why the phase margin is better yet because I have been busy taking captures and cleaning up the messes I have made setting up these experiments.I think it is probably better to keep the current mirror out and keep the folded cascode if current noise is a concern, but I may be wrong about this. Any base current, as Kleinstein has reminded me, is emitter current that is not flowing through the collector, so if there's another pair of BJTs (other than the normal cascode) in the design, it would be best to have them running at a lower collector current, as the folded cascode does.I have used the HN4C51 model I posted in simulations, both with and without a non-zero value of KF. With the value I had (0.0085f), the cascode pair contributes some amount to the noise of the input (at 10 mHz, it goes from about 6.6 to 7.2 nV/rtHz). With this new configuration, I can still use the SNR with noise of a JFE21140 (pair) measured with the LNA as an indication of how much it is feasible to improve the RTI noise, but with the mirror deletion, it seems we are pretty close to the point of diminishing returns at very low frequency. There is only so much capacitance that will fit on the board and only so large a value for the resistor used to GND the gate side of the AC coupling filter that is feasible to use without sacrificing settling time.Quote from: Kleinstein on November 22, 2023, 03:45:16 pmIn my hands, and in the configuration I tested, the part I looked at was very low noise at high current. With 1R00 base resistance (essentially diode connected at that point), the noise spectrum I took with the LNA (prior to deleting the current mirror) was about 3dB up from the noise floor all the way down to 100 mHz. I did not take a really long capture to get good data down to 10 mHz, but it seemed like that trend would continue. That is pretty quiet as long as you keep the source impedance low, but it is not as good as predicted from the model I posted. I would need to read more about the Gummel-Poon BJT noise model to get a better fit for both.I don't know much about semiconductor design, but from what I do know, it seems that using active loads to keep on-die resistors small would matter a lot. The ADA4625 has a reasonably detailed circuit diagram (at least by comparison to what is usually disclosed in a datasheet), and they mention using passive loads for the first stage, but it is not clear how large they are. They aren't using a real cascode in this case, so there would be a limit as to how large the loads could be and still increase the gain, assuming that gos for their input pair is not remarkably high.