[IC] Thick gate oxide on 1.8V CMOS - Page 1
Forum section: electronics / projects

author: blueskull
author_rank: Unknown
timestamp: March 09, 2021, 11:12:48 am
content: Here is a tricky case. I have here a process that can either be a 1.8V-only process or a 5V+HV process.Normally, for a mixed voltage CMOS process you have a mask layer to define thick gate oxide (gox), so for 5V Vgs devices (5V Vds FETs and HV FETs), you apply this mask and have a thicker gox, and for 1.8V Vgs devices you cut a hole on this mask have a thinner gox.In my case, a strange process can only have one gox thickness, so either I go 1.8V only, or I go 5V only.Apparently for mixed signal circuits 1.8V Vgs is not an option, let alone HV circuits, so I have to apply thick gox over the entire chip.Now, I wonder, how will the 1.8V (L=0.18um) FETs perform with 5V thick gox? I know it will be considerably slower as overdrive is lower (thin gox Vth=0.5V, thick gox Vth=0.9V, at 1.8V VDD, overdrive reduces from 1.8V-0.5V=1.3V to 1.8V-0.9V=0.9V), but will it work in the first place, and how slower will it be? I expect to re-K the std cell library, but before that I just want to know if it is worth the time.Running 5V CMOS with 5V gox is also not an option as 5V FETs are also larger (L=0.6um vs L=0.18um for 1.8V), so that will cost me much more die area for what I want to make. It is a last resort, but I highly prefer against that.FYI, changing to another fab is an option, just an expensive one. This current fab has a low cost, low performance (enough for me) HV drain extended FET process that costs zero additional mask, while a higher performance, industry standard LDMOS process supplied by the competing fab requires 7 additional masks, plus some other bits here and there, in total I would have needed 10 more masks, and that means I need to swallow an extra $12k cost plus tax.

author: mawyatt
author_rank: Super Contributor
timestamp: March 09, 2021, 02:55:32 pm
content: Must be a very old and large feature size process, we were used to paying ~$100K per mask many years ago!! There were generally over 38 masks too!!Our experience was that the faster minimum feature size MOS device in the process did not support the higher voltages, these higher voltage MOS devices not only had a thicker oxide but also had a minimum length much longer than the minimum process feature size. You should be able to get an idea of the MOS behavior by looking at the model the foundry uses for the standard MOS offering, adjust this model with the thicker oxide, and run some simple simulations, or ask if they have a TCAD model (semiconductor process & device behavior) for the MOS devices, where you could look at the effects of the thicker oxide.You might be able to get an idea of the expected behavior by placing a series cap with the gate of the thinner oxide device, this cap should be sized to make the series equivalent capacitance as "seen" into the gate from the series cap have the same capacitance as the device would if it had the thicker oxide. Caution, I've never tried this, so just thinking this might help give an idea of what to expect.BTW if you are using this IC design for anything that has the MOS devices acting as bilaterial switches where current can flow either way the older BSIM CMOS models have a flaw in the ON channel conductance computations wrt to the current flow. The result is a pessimistic estimate of the ON channel linearity wrt the odd order distortions.Anyway, good luck with your IC design.Best,

author: exe
author_rank: Unknown
timestamp: March 09, 2021, 03:09:17 pm
content: Would be producing two different dies for different voltages an option? Is it possible to make the high-voltage part using external discrete components?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: March 09, 2021, 03:39:38 pm
content: blueskull, Not any info on what you are doing, but sharing the lab prices and info would definitely help here, as you have a track record of finding excellent deals or parts.

author: mawyatt
author_rank: Super Contributor
timestamp: March 09, 2021, 05:21:48 pm
content: Quote from: blueskull on March 09, 2021, 03:52:05 pmThis was a problem we discovered with BSIM4 way back, and discussed with the Berkley folks behind the model. It turns out the BSIM4 can't handle the drain and source interchanging when the channel current reverses because the computations are based upon Gate, Source and Drain voltages wrt each other, like Vgs for example. The model just used an absolute value function to deal with the D & S reversal, this causes a discontinuity in the derivative of the channel transconductance. A model "fix" was developed by a Cornell PhD student, now a prof at Colombia, it was external model terminal circuitry but can't remember the details. Berkley came up with a clever model "fix" for later models like BSIM6, where the terminal voltages weren't referenced to each other but to the substrate, this elegantly solved the problem without computational overhead like a physics based model (PSP for example). I don't know if the BSIM4 model was "fixed", but understand that it is not an issue in BSIM6.Wow, those are some great prices for a mask costs and MPR!!Best,

author: mawyatt
author_rank: Super Contributor
timestamp: March 09, 2021, 06:09:32 pm
content: Quote from: blueskull on March 09, 2021, 04:04:08 pmLong ago we developed a integration of a GaN depletion mode device with a Silicon bipolar or CMOS device, it was called the "GaNsistor", which later lead to a Silicon MESFET depletion mode versionIntended for RF and switching applications, it had GaN output, and Silicon input characteristics. Soon after we developed a kind of Power DAC utilizing this concept, we called Direct Digital to Antenna or DD2A, for creating RF and Microwave power TX signals directly at the antenna port with a digital input interface. This lead to a clever implementation in a DARPA program where the DD2A was used in multiple instances in a traveling wave Power Amplifier replacing the usual power amps with DD2As.Many years later we filed for the fundamental patents on the GaNsistor and DD2A (7939857 & 7903016). Interestingly my former employer has elected not to pursue the multiple infringements of these patents, likely due to the short term mentality of present day management since litigation would take a number of years to pursue. I never got any support for these developments (like much of my prior work), and had to do all the research, design & chip layout on my own, but did utilize a MPW run so all rights went to companyAnyway, good luck with the design and having Cadence available you'll find a a big asset....one of the best IC CAD tools available. Ken Kundert original Spectre is the best time domain simulator I've encountered, the look-ahead algorithms and such have a unique ability to find subtle nuances in complex circuits that others likely would step over and miss, very powerful simulation tool for IC design.Best,

author: Mazo
author_rank: Regular Contributor
timestamp: March 09, 2021, 06:55:47 pm
content: Just my not really educated opinion,but interested in the topic:My first thought was the thicker gate oxide will decrease the output resistance of the devices(goss,ro,whatever floats your boat).(Increased channel-length modulation/smth else/combination of effects?)Did some fast googling around,found this:http://cpb.iphy.ac.cn/article/2015/cpb_24_4_047302.htmlScroll to figure 4,at first look seems my suspicions are atleast in the right direction.Not really sure if it is entirely relevant.

author: Medved
author_rank: Contributor
timestamp: March 09, 2021, 07:02:48 pm
content: Quote from: blueskull on March 09, 2021, 11:12:48 amYou can not use 5V thick gate oxide for a 0.18um long channel device. It is just physically impossible to manufacture (it is by far not limited by just the lito accuracy). Plus the DRC should not allow it to you.The minimum length for 5V would be somewhere in the 0.5.. 0.7um ballpark, check your design manual for the process you want to use.And of course, you can not use the 0.18um 1.8V libraries (digital, IO,...), just because the short gate length devices can not be manufactured with the thick tox.So going just a single oxide option is indeed a money saver on the masks (and processing costs, plus it usually gives better yield and reliability), but your die will definitely be bigger and maybe even take longer to design (because some blocks won't be available in ready made libraries), but that is the trade off calculation you have to make yourself...