Confused: Can FPGA measure less than 0.1ns delay between digital pulses? - Page 1
Forum section: electronics / general

author: Tufts
author_rank: Newbie
timestamp: August 01, 2023, 04:31:07 pm
content: Hello! I am a beginner of FPGA and want to learn can I build FIR-like structures in FPGA to process multi-channels of high speed pulse train and detect less than 0.1ns delay between each pulse?I found the Intel Agilex 9/Stratix 10 AX can perform direct analog RF signal conversion for multiple analog input and output channels at groundbreaking rates as fast as 12 gigasamples/sec (Gsps) over sixteen channels, and 64 Gsps over as many as eight channels. However, the internal clock rate is much less (only 1000MHz at most for Stratix 10). I am confused why the built-in RF ADC and DAC in Stratix 10 are claimed to operate as fast as 64 Gsps with 36 GHz of input bandwidth? If the internal clock rate is only 1GHz, how do FPGA logic cells process 10s of GHz output data from the built-in ADC/DAC?I think I am confused about the Clock speed, Max IO speed and the Max Sampling speed of FPGA. Can any one give me some advices? Thank you very much!

author: ejeffrey
author_rank: Super Contributor
timestamp: August 01, 2023, 04:53:51 pm
content: I'm not familiar with the Intel AgileX RF products but there are two ways that FPGAs work with data converter sample rates faster than the core clock.The first is simply handling multiple samples in parallel. If you process 10 samples per clock cycle, you can run the data converters at 10x the core clock.The second is digital downconversion. So if you have an ADC running at 8 GSps, but the only signal you care about is in a narrow band at (say) 2.5 GHz the ADC may have dedicated logic (not part of the FPGA fabric and able to run at higher clock) able to frequency translate that down to < 500 MHz, low-pass filter the data, then downsample to a lower sample rate. And for high speed upconverters the reverse: interpolate the data to a higher sample rate, then frequency upconvert it to the desired output frequency. There are also multi-band systems that can run multiple up/downconversionThese chips very likely use a combination of both of these techniques.

author: Tufts
author_rank: Newbie
timestamp: August 01, 2023, 06:39:53 pm
content: Thanks for the reply. Then probably Intel is calculating ADC speed by multiplying the number of input channels and speed of a single channel.My following question is, what if I want to process asingle channeldigital signal with 100ps time resolution directly by FPGA? Is it possible if the internal clock frequency is only 1GHz?

author: AK6DN
author_rank: Regular Contributor
timestamp: August 01, 2023, 07:20:52 pm
content: Quote from: Tufts on August 01, 2023, 06:39:53 pmYes, that is aggregate input data bandwidth over all the channels.WRT the 100ps time resolution detection, forget about it. You cannot control layout of circuitry to such timing accuracy. Even in an asic and manual layout it would be difficult.And of course it is not possible to sample data at 100ps accuracy given a 1000ps system clock. Best you could do is a 12bit (or whatever) sample each 1000ps or more.Your quest for 100ps processing on an FPGA is like chasing the pot of gold at the end of a rainbow.

author: dmendesf
author_rank: Frequent Contributor
timestamp: August 01, 2023, 10:36:26 pm
content: To measure small time differences in digital signals you need a Time to Digital Converter (TDC). It's a circuit you can shoehorn into an FPGA (there's plenty of prior art) but you can also buy custom chips to do it (some better, some worse). You don't get the amplitude of the signal, just the phase/time difference, but usually that's what you really want when someone start talking about sub-ns signals.

author: radiolistener
author_rank: Super Contributor
timestamp: August 01, 2023, 10:53:55 pm
content: Yes, you can do it with TDC (Time to Digital Conversion), but it needs calibration of your TDC design with precise measurement devices, because results will depends on exact FPGA chips and exact elements of FPGA used for your TDS, so it will depends on synthesis and used FPGA chip.In other words, when you know exact propagation delay between elements in your TDC implementation, you can calculate measurement interval between pulses more precisely.

author: ejeffrey
author_rank: Super Contributor
timestamp: August 01, 2023, 11:11:09 pm
content: Quote from: Tufts on August 01, 2023, 06:39:53 pmNo, they have an ADC that samples at 64 GS/s, but you receive multiple samples on every clock cycle. For instance, assuming that there is no decimation. you might have a 500 MHz FPGA core clock, and on each clock cycle you receive 128 samples. However, each of those samples represents a different point in time, approximately 15 picoseconds apart. On the next clock cycle you get another 128 samples, again representing 128 points in time. Its your job to process these samples appropriately.You aren't really clear about your goal, but this is likely vastly overkill for what you want to do. I haven't seen any pricing or even a product table for the agilex 9 products, but I'd guess they range from $10K to $100k, maybe higher.Time to digital converters can be much simpler, it's a well studied technique and can be done with relatively simple hardware. There are also off the shelf instruments that will do it.Depending on your application it also may be possible to abuse the high speed transceivers in more pedestrian FPGAs for this purpose. Those are digital IO channels that operate in the 10-50 gigabit/s range on FPGAs that cost from a few hundred dollars to a few thousand. They are intended for applications like 10+ gigabit ethernet, and are generally expected to be AC coupled with signals that have a certain minimum rate of transitions, but you can use them for other purposes if you know how to work around their limitations.

author: TimCambridge
author_rank: Regular Contributor
timestamp: August 02, 2023, 12:17:28 am
content: white-rabbit.web.cern.ch

author: Someone
author_rank: Super Contributor
timestamp: August 02, 2023, 02:23:16 am
content: Quote from: AK6DN on August 01, 2023, 07:20:52 pmAs several posters above have pointed to, TDC is a fairly mature (if obscure) use of FPGA's and willeasilyget to 100ps. Single digit ps still not hard or requiring expensive parts.True it's not a primitive or off the shelf IP block that is ready and easy to use, but thats the case of many interesting/valuable uses of FPGAs.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 02, 2023, 05:48:59 am
content: Quote from: Tufts on August 01, 2023, 04:31:07 pmIf we take your 1GHz clock as an example, imagine you have 10 channels, each clocked at 1GHz, but phase shifted by 100ps each.You can now resolve to 100ps.If your pulse-train is repetitive, and stable, not single shot, (eg like an echo) you can also do what sampling oscilloscopes do : sample over many pulses at 'walking' or random phase delays.

author: Tufts
author_rank: Newbie
timestamp: August 02, 2023, 01:49:53 pm
content: Quote from: ejeffrey on August 01, 2023, 11:11:09 pmThanks! In this case, I have the following questions:1. Instead of using the built in ADC/DAC, can I just split a single channel digital pulse train into 128 paths in FPGA directly and program each path to be driven by different clocks with 15ps phase shift?2. If the answer is yes to the 1st question, is it possible to generate those 128 clocks by shifting one internal 500MHz clock with delay chain that is composed by 15ps delay units?3. Or, can I use PLL on FPGA to generate high speed clock (say 10GHz) from the low speed internal clock and use that generated clock to drive logic units?

author: BrianHG
author_rank: Super Contributor
timestamp: August 02, 2023, 07:20:40 pm
content: What is a pulse train? It sounds like a digital signal. If so, why do you need an ADC?I'm not sure anything useful can be said without every spec of nuance of knowledge about what your are trying to do. 0.1ns or 100ps requires some serious understanding of what you are trying to do since even the trace length and capacitive load of each IO pin on an FPGA will throw everything out of whack without some seriously expensive PCB CAD, simulation tools and special PCB substrates developed with multiple specialist engineers. IE, try to pass your 5-10GHz analog signal to multiple inputs and expect results other than garbage data.

author: Tufts
author_rank: Newbie
timestamp: August 02, 2023, 07:42:22 pm
content: Quote from: BrianHG on August 02, 2023, 07:20:40 pmYou are right, I do not need ADC. The input signals are just random digital pulses with various arrival time in sub-nanosecond. I want to detect the time difference between any adjacent pulses.For sub-ns detection, can I use PLL on FPGA to generate high speed clock (say 10GHz) from the low speed internal clock and use that generated clock to drive logic units?

author: asmi
author_rank: Super Contributor
timestamp: August 02, 2023, 07:50:35 pm
content: Quote from: Tufts on August 02, 2023, 07:42:22 pmNo FPGA can drive logic anywhere near that, infact "just" 1GHz is already too much even for the more expensive FPGAs out there. The best you can hope for is 500-600-700 MHz for internal logic. IO logic can be driven faster, but not by order of magnidute faster.

author: Marco
author_rank: Super Contributor
timestamp: August 02, 2023, 08:00:51 pm
content: I don't understand why FPGA manufacturers are so coy about TDCs. Academia spending thousands upon thousands of manhours manhandling inaccurate layout to get TDCs is such a waste of efforts, just make it a standard macro. The manufacturers are in an infinitely better situation to implement it.PS. or is it an export control thing?

author: BrianHG
author_rank: Super Contributor
timestamp: August 02, 2023, 08:35:06 pm
content: Quote from: Tufts on August 02, 2023, 07:42:22 pmSo, I don't get it, Why don't you use a single 10gbps serial input with a fixed dunb clock, no protocols, just a digital input running at 1:16 and calculate what you want from your serial input at 1/16 the data rate on the internal 16 bit bus.Note you most likely can run the internals at 1:20 for a 500MHz core clock, or, 1:32 with a 312.5mhz clock.What you need to do is read the FPGA handbook section on high speed serial transceiver sections about how to use their transceiver megafunction. Usually, the lower-end transceivers which run on every pin use the system PLL for the IO pin and a divided ratio for the internal logic. They usually run only up to 800mbps or 1gbs. The multi GHZ grade high speed transceivers will usually only need the system PLL at 312.5 or 500 or 1ghz while they have their own internal sub-pll sampling at 10gbs while their megafunction's output will be parallel data on the slower main PLL 312.5/500/1000mhz clock.Note this means you have created a 10ghz 1bit input sampler. You parallel output bus will only have a new bit every 100ps spread throughout the parallel data running in a continuous circle every system clock.

author: AK6DN
author_rank: Regular Contributor
timestamp: August 02, 2023, 08:39:29 pm
content: Quote from: Marco on August 02, 2023, 08:00:51 pmOr maybe just buy an existing product that does the function and be done with it ...https://www.sciosense.com/products/time-to-digital-converters/tdc-gpx-high-end-time-to-digital-converter/https://www.sciosense.com/products/time-to-digital-converters/tdc-gpx2-time-to-digital-converter/10ps resolution over multiple channelsUse this part for the front end 'analog' processing and then do all the digital signal processing in an attached FPGA.

author: tszaboo
author_rank: Super Contributor
timestamp: August 02, 2023, 09:05:47 pm
content: Quote from: Marco on August 02, 2023, 08:00:51 pmIt's because they get the FPGA boards for free. It's part of the course, and seems logical (pun intended). And for most projects its an expensive solution looking for a problem.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 02, 2023, 09:16:20 pm
content: Quote from: Tufts on August 02, 2023, 07:42:22 pmIf you have a good enough FPGA, yes, you can use the fast serial IO modes, but that does not give you hardware time capture directly.You need to post process to look at the data patterns, and count bits, to decide time differences.Do you generate a trigger pulse, and what capture range do you need, shortest to longest dT ?

author: BrianHG
author_rank: Super Contributor
timestamp: August 02, 2023, 09:23:36 pm
content: Quote from: PCB.Wiz on August 02, 2023, 09:16:20 pmNo trigger needed once you already are counting bits from any point to any other point.Also a trigger cannot be used in the dumbest serial sampler, especially is the source isn't some sort of clocked synchronous or patterned data with a deliberate synchronous structure.

author: dietert1
author_rank: Super Contributor
timestamp: August 02, 2023, 09:35:14 pm
content: On monday i received an EMail from AD. Quote:AD9084: Apollo MxFE™ Quad, 16-Bit, 28 GSPS RF DAC and Quad, 12-Bit, 20 GSPS RF ADC with On-Chip DSPAD9084 is a quad, direct RF sampling converter with an integrated DAC and ADC. The 16-bit, 28 GSPS DAC offers instantaneous bandwidths as high as 8 GHz while directly sampling and synthesizing frequencies up to 18 GHz. The on-chip digital signal processing (DSP) offers a real-time FFT sniffer, a full-rate programmable FIR filter, a 128-tap complex FIR filter, fast-hopping NCOs, DDCs/DUCs, and a fractional sample rate converter.Hard to believe but these parts seem to be coming. Of course with a quad 20 GSPS ADC you can build what the OP proposed. They also advertise support parts like PLL clock generators and low noise amplifiers to be used for wireless applications. We got a Lecroy SDA with four channel 20 GHz sampling (8 bit). Its risetime of about 50 psec is enough to measure channel to channel delays to about 100 psec.Regards, Dieter

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 02, 2023, 09:52:20 pm
content: Quote from: Tufts on August 01, 2023, 06:39:53 pmThat is what all digital scopes do.

author: dietert1
author_rank: Super Contributor
timestamp: August 03, 2023, 04:43:08 am
content: Quote from: SiliconWizard on August 02, 2023, 09:52:20 pmNo, our Lecroy SDA does 20 Gsps on all four channels at the same time and their current Labmaster scopes do 160 Gsps per channel. The AD 9084 announcement i mentioned will have an output data interface with 24 lanes of 20 Gbps, so it will run two 12 bit ADCs at 20 Gsps each. For the intended application one may need an ADC for noise reasons. Even a TDC is an integrator plus an ADC.Regards, Dieter

author: nctnico
author_rank: Super Contributor
timestamp: August 03, 2023, 07:43:42 am
content: A 10Gbit/s serdes will do what the op needs but typically there are not many of these on an fpga. And some research needs to be done whether the serdes supports sending / receiving raw data.

author: Marco
author_rank: Super Contributor
timestamp: August 03, 2023, 02:21:55 pm
content: Quote from: AK6DN on August 02, 2023, 08:39:29 pmSince they only need 100 ps, the TDC7200 seems a little more affordable.

author: Someone
author_rank: Super Contributor
timestamp: August 03, 2023, 11:35:01 pm
content: Quote from: dietert1 on August 03, 2023, 04:43:08 amThe link from the ADC to the acquisition logic/hardware might be narrow + fast enough to do word sequential, but what about the acquisition memory? or the processing? or display?The quote above is correct, pretty much all digital scopes parallel the sample stream so it can be handled several words at a time with a more sane clock speed.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 04, 2023, 04:00:08 am
content: Yep, don't know which exact model Dieter has, but this Lecroy scope series with 20Gsps ADCs can still aggregate several ADC channels to get 80Gsps or more (depending on version.)

author: Marco
author_rank: Super Contributor
timestamp: August 04, 2023, 01:17:56 pm
content: Using a couple 10s of k$ oscilloscope to do what an under a dollar PIC can do is a bit inelegant.

author: dietert1
author_rank: Super Contributor
timestamp: August 04, 2023, 04:17:40 pm
content: Quote from: Marco on August 04, 2023, 01:17:56 pmWhen trying to implement some kind of metering one needs standards. A serious engineer won't look what he can do with a certain FPGA or MCU, but get a scope capable of doing that measurement in order to establish a standard. Once the problem is understood you can work on a commercial solution. Somehow this thread started with the second step. That's the confusion part.Regards, Dieter

author: Marco
author_rank: Super Contributor
timestamp: August 04, 2023, 05:37:12 pm
content: https://www.edn.com/use-time-domain-reflectometry-tdr-for-low-cost-liquid-level-measurement-part-iii/Now I'm not suggesting using the CTMU, because it's not entirely trivial to use, it's just the cheapest option. There are integrated TDC options still nearly 3 orders of magnitude cheaper than that scope, it's a bit silly to bring up GSps ADCs/scopes to measure a delay.

author: marcopolo
author_rank: Regular Contributor
timestamp: August 07, 2023, 10:59:30 am
content: Are there any ARM MCUs with the equivalent of Microchip's CTMU?https://www.microchip.com/stellent/groups/SiteComm_sg/documents/DeviceDoc/en542792.pdf

author: ingenuwork
author_rank: Newbie
timestamp: August 10, 2023, 12:37:15 pm
content: I had tried to detect very small phrase(about 0.01deg) defference between two sine wave at the frequency of 200kHz, at begining I tried to use a Zero-Cross-detect circuit to do the job but failed, that's because only one singal point on the sine wave is used . and then I used a 1Gps DSO to take thousands of the wave samples, and the use the cross-power mathletics to calculate, and get a much more precise result. I think is about 0.05deg deviation.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: August 10, 2023, 07:39:29 pm
content: Seems like a job for a lock-in amplifier.

author: nimish
author_rank: Regular Contributor
timestamp: August 14, 2023, 05:48:39 pm
content: Yes, use a delay line/DLL based TDC. Bunch of papers on this. Same way an STM32G474 can place PWM edges at ~100ps.https://www.st.com/resource/en/product_training/STM32G4-WDG_TIMERS-High_Resolution_Timer_HRTIM.pdfCERN has some open HDL for it. But a TDC chip is like $5 and a lot less hassle.

author: dietert1
author_rank: Super Contributor
timestamp: August 15, 2023, 06:04:19 am
content: The linked paper explains that the 32 tap DLL in the STM32G4-HRTIM can be calibrated up to 170 MHz. So the finest time division is 184 psec. And it can be used for PWM generation but not for capture.If this were about RF, one could use it to make a standard for phase measurement.Anybody has some test results with the PIC CTMU? I didn't see anything about it's noise when trying below nsec resolution timing measurements. In addition to jitter one would expect some noise from the TDC conversion. I mean, when you try to measure a 10 usec delay at a resolution of 100 psec, the usual 12 bit ADC won't do that and a 16 bit ADC isn't enough either.Regards, Dieter

author: nimish
author_rank: Regular Contributor
timestamp: August 16, 2023, 01:17:56 am
content: Quote from: dietert1 on August 15, 2023, 06:04:19 amThe point isn't to copy that app note but to realize that the technique is scalable to whatever resolution you can get with gate delays and your DLL. The trick is, of course, to only bother with fine measurement when it matters at the very last cycle and otherwise count long periods using a much coarser clock -- this is ye olde Nutt interpolation (as if this really needed a name!)Here's one I found after googling "FPGA TDC":https://ohwr.org/project/tdc-core/wikis/home~50ps over 250ms but like all of these needs calibration over PVT