SoC+fpga, over AXI, AMBA bus - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: February 02, 2016, 07:39:55 pm
content: I just like to hear what do you think about AXI, and what is your experience with linux (if the SoC, e.g. ARM-core based, can run linux)

author: legacy
author_rank: Super Contributor
timestamp: February 02, 2016, 07:43:00 pm
content: just to provide an example from the real worldthe DE1 board has the SoC===AXI===fpga working scheme

author: legacy
author_rank: Super Contributor
timestamp: February 02, 2016, 07:45:26 pm
content: Quoteedit:I addthisslideshow

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 06:06:57 am
content: Quote from: legacy on February 02, 2016, 07:39:55 pmWell designed bus. Other than this, what else to say? It is a bus and it serves its stated purpose.Quote from: legacy on February 02, 2016, 07:39:55 pmIt just works, and there are really no other options for general purpose applications.

author: legacy
author_rank: Super Contributor
timestamp: February 03, 2016, 06:22:53 am
content: Quote from: ataradov on February 03, 2016, 06:06:57 amhow good is the linux support? and what is the most used application scenario?I have noted that DE1 is using and providing a custom solution, and so it's done by a lot of FPGA+SoC productsQuote from: ataradov on February 03, 2016, 06:06:57 amwell, it depends, in my case, if I can have the last word in the design, and if I can avoid a SoC like the one used in DE1, I'd rather use the shared-ram approach (between a CPU and an fpga), which is completely different

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 06:24:17 am
content: Quote from: legacy on February 03, 2016, 06:20:30 amThe bus itself does not need to be supported by the OS. It just works. Depending on the design there can be some configuration registers exposed, but they are mostly non-essential and default configuration should work just fine.Quote from: legacy on February 03, 2016, 06:20:30 amIf you don't need to run Linux, then don't. I don't see a problem here.

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 06:26:28 am
content: I don't think AXI is designed to be exposed on external pins. There are way to many signals for that. It is a SoC system interconnect bus.Typically for communication with  outside devices, you want to put AXI-APB bridge and make your device APB-compliant. APB bus is much simpler and can be exposed reasonably well.And the brilliance of AXI is that it knows how to handle those slow bridges efficiently without stalling everything.

author: legacy
author_rank: Super Contributor
timestamp: February 03, 2016, 06:34:14 am
content: no doubt, but it is used to connect an fpga to a SoC, or two SoCs togetherthe point is: when linux is involved, I do not believe it has a good support, as I can't see a stable working schemeand each vendor seems to add his custom supportand so I'd like to hear about practical experiences: because I have to choose IF to use it, or notwhich implies if to stay with SoC+FPGA (more specifically cloning the De1), or not

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 06:38:09 am
content: Quote from: legacy on February 03, 2016, 06:34:14 amCan you show an actual example?Quote from: legacy on February 03, 2016, 06:34:14 amI don't understand. AXI is completely transparent to Linux. It is like saying that Linux does not support capacitors in your power supply. Linux just does not care.Quote from: legacy on February 03, 2016, 06:34:14 amAgain, examples? AXI is a specification. Some things there are optional, but you can't add new things and still call it AXI.Quote from: legacy on February 03, 2016, 06:34:14 amDE1 is a dev. kit. It can run many projects, which one you are talking about?

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 06:43:20 am
content: Also, if you are talking about DE1-SoC board, then ARM core there is implemented inside an FPGA and you don't really have a choice on what bus to support. Cortex-A9 has AXI sticking out of it and that's your only option.As I already pointed out, you can put AXI-APB bridge and make your peripheral to support whatever protocol you feel like, but Cortex-A9 will only talk AXI.

author: legacy
author_rank: Super Contributor
timestamp: February 03, 2016, 08:16:43 am
content: Quote from: ataradov on February 03, 2016, 06:38:09 amsay, dedicated kernel modules

author: legacy
author_rank: Super Contributor
timestamp: February 03, 2016, 08:18:44 am
content: Quote from: ataradov on February 03, 2016, 06:38:09 amwe (my team and I) are evaluating the possibility to use the De1 kit as starting point for a few new products: say, it's currently in use as "prototype"

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 08:18:57 am
content: Quote from: legacy on February 03, 2016, 08:16:43 amI still don't get it. You can have modules for peripherals that sit on a bus. There is no need for a bus module. What it will do exactly?

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 08:21:36 am
content: Quote from: legacy on February 03, 2016, 08:18:44 amIf you are not doing some super high bandwidth applications, chances are, you won't have to touch AXI at all.

author: legacy
author_rank: Super Contributor
timestamp: February 03, 2016, 08:54:17 am
content: excellent

author: Kilrah
author_rank: Unknown
timestamp: February 03, 2016, 09:15:44 am
content: Quote from: legacy on February 03, 2016, 06:34:14 amNo, it is purely internal to one single chip. Your DE1 board does not connect an SoC to an FPGA, it doesn't even have an SoC next to the FPGA...It only has an FPGA,within whichyou can create an SoC by implementing a processor and peripherals into it. If that processor uses an AXI bus to talk to its peripherals then so be it, but it's not something you need to actually care about from a software point of view. Your peripherals will expose memory-mapped registers that you access through a given address, the fact this goes through an AXI bus is transparent, it's just how the hardware does things.

author: legacy
author_rank: Super Contributor
timestamp: February 03, 2016, 09:33:30 am
content: Quote from: Kilrah on February 03, 2016, 09:15:44 amthings likedrivers/amba/bus, and I see patches for De1

author: legacy
author_rank: Super Contributor
timestamp: February 03, 2016, 09:47:45 am
content: Quote from: Kilrah on February 03, 2016, 09:15:44 amyes, it's clear to me, I had forgotten to specify, but I meant "internally", the ARM core is inside the chip, which also contains the fpga, and you can have (in the theory) two SoC plus an FPGA inside the same chip, e.g. two arm cores, plus their peripherals, both of them connected to a fpga over the AMBA busso, internally, the SoC is connected to the FPGA over the AMBA bus

author: miguelvp
author_rank: Super Contributor
timestamp: February 03, 2016, 10:00:30 am
content: It doesn't help that Terasic reuses their names, for example there is also the DE0-Nano SoC with dual A9 ARM hard cores on it.Not to be confused with the DE0-Nano with no hard cores.

author: langwadt
author_rank: Super Contributor
timestamp: February 03, 2016, 11:13:57 am
content: Quote from: ataradov on February 03, 2016, 06:06:57 amwell designed except for one big thing; there is no timeoutif you try to access a register on the axi bus that doesn't respond, e.g. you haven't configured the programmable logicthe only way out is a hardware reset

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 04:35:00 pm
content: Quote from: langwadt on February 03, 2016, 11:13:57 amIf you try to shoot yourself, you will die. Don't access unimplemented registers.

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 05:12:36 pm
content: Quote from: legacy on February 03, 2016, 09:33:30 amThis is mostly a way to organize devices. It is purely software stuff, it does not interact with actual hardware.And I think it is a legacy thing (no pun intended), its functionality is replaced by device tree.

author: langwadt
author_rank: Super Contributor
timestamp: February 03, 2016, 06:49:16 pm
content: Quote from: ataradov on February 03, 2016, 04:35:00 pmsimple enough to say, when the only way to tell is to point the gun at your head and pull the triggerfor example; something simple like loading a different configuration for the programmable logic will require that you kill all programs and unload all drivers that might access the axi bus to that logicbecause any access while reconfiguring will end in a lockup that you can only get out off with a hard reset

author: langwadt
author_rank: Super Contributor
timestamp: February 03, 2016, 06:54:06 pm
content: Quote from: ataradov on February 03, 2016, 05:12:36 pmthe devicetree just tells what drivers to load and how to configure them

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 06:59:43 pm
content: Quote from: langwadt on February 03, 2016, 06:49:16 pmOtherwise you will have to write all your software to be able to deal with timeouts. From a programmer point of view, they will have to look like some value (0?) is returned for reads and writes that go nowhere. That is unless you want to handle exceptions.All of this is a hell for a programmer. It is much easier to stop accessing locations before they disappear.Also, ARM implementation of AXI allows you to connect a default slave that handles all unhanded request. Just use that if your implementation allows it.

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 07:01:27 pm
content: Quote from: langwadt on February 03, 2016, 06:54:06 pmYep, and this "driver" is just an old way of doing the same. It is only used by a few unsupported boards to specify hardcoded hardware configuration.

author: langwadt
author_rank: Super Contributor
timestamp: February 03, 2016, 07:23:52 pm
content: Quote from: ataradov on February 03, 2016, 06:59:43 pmI'd much rated handle a crashed program/driver or exceptions, than a system that hang until someone hits the reset buttonQuote from: ataradov on February 03, 2016, 06:59:43 pmI disagreeQuote from: ataradov on February 03, 2016, 06:59:43 pmit won't help the problem is not unhanded request it is transactions that never finish

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 07:27:29 pm
content: Quote from: langwadt on February 03, 2016, 07:23:52 pmWhat do you mean? If your software makes a request that is not handled by any of thew real slaves, this default slave takes over and completes the transaction.Of your are saying that your slave disappears right in the middle of the transaction? I don't think this bus is designed to handle this level of dynamic reconfiguration. I don't think any existing bus can do this. That's just stupid to expect that slave can disappear in the middle of the transaction.

author: langwadt
author_rank: Super Contributor
timestamp: February 03, 2016, 09:38:12 pm
content: Quote from: ataradov on February 03, 2016, 07:27:29 pmif the slave disappears during a transaction or isn't there when a transaction is started the systemend up in a a dead lock. Once a master has set xVALID it must wait for xREADYdynamic reconfiguration is entirely reasonable in a system with configurable logic.A bus that crashes the whole system waiting forever on something that ought to take microsecondsis silly

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2016, 09:53:31 pm
content: Quote from: langwadt on February 03, 2016, 09:38:12 pmYou do whatever you want of course, but don't blame the bus that it does no handle devices disappearing in the middle of transaction. That's just bad system design and there is no need to over complicate the bus logic for things that will never happen in actual real life.

author: langwadt
author_rank: Super Contributor
timestamp: February 03, 2016, 10:17:45 pm
content: Quote from: ataradov on February 03, 2016, 09:53:31 pmthat's like saying why bother with protected memory or exceptions it is never going to happen inreal life and if it does it is just bad system design

author: legacy
author_rank: Super Contributor
timestamp: February 10, 2016, 11:15:56 am
content: not brilliant, but it's extremely good,thislink shows a bit of the magic under the hood: Exploring the Arrow SoCKit Part III - Controlling FPGA from Software

author: legacy
author_rank: Super Contributor
timestamp: February 20, 2016, 08:01:29 am
content: Design and Implementation of AMBA-AHB&APB bridge memory controller by VHDL

author: legacy
author_rank: Super Contributor
timestamp: February 20, 2016, 09:01:00 am
content: what is the equivalent of De1 in the Xilinx world ? (SoC/ARM + FPGA, with a bus-bridge in the middle)

author: ataradov
author_rank: Super Contributor
timestamp: February 20, 2016, 09:03:22 am
content: Any board based on Zynq. Prices vary a lot, so pick whatever fits your bill.

author: legacy
author_rank: Super Contributor
timestamp: February 20, 2016, 09:06:06 am
content: yes, I meant within the same price as De1, and … is itthisone ?

author: ataradov
author_rank: Super Contributor
timestamp: February 20, 2016, 09:08:37 am
content: http://zedboard.org/is one of the most famous. There are many variations with wide rage of prices. Community support is there.The cheapest one is actually a board from Adapteva, but their site seems to be down at the moment.

author: Kilrah
author_rank: Unknown
timestamp: February 20, 2016, 09:35:23 am
content: I've got a Zybo, and waiting for my snickerdoodle.https://www.crowdsupply.com/krtkl/snickerdoodleStill in preproduction, but it'll be a very cheap entry price.

author: legacy
author_rank: Super Contributor
timestamp: February 20, 2016, 10:29:58 am
content: https://www.crowdsupply.com/krtkl/snickerdoodle]snickerdoodleseems good