Pulse timing, Any idea where to find the figure schematics for this? Broken URLs - Page 1
Forum section: electronics / projects

author: Infraviolet
author_rank: Super Contributor
timestamp: October 21, 2021, 04:16:50 am
content: https://www.edn.com/circuit-converts-pulse-width-to-voltage/I've been reading about a pulse-width to DC voltage timing circuit and wanted to find more, but the links seem broken on that page, the pdf it links to doesn't exist any more, and any attempts at converting the page for printing also fail to get the images.Any chance anyone is aware of that same circuit design elsewhere and can give me a link?Links to other examples for how to convert a pulse length to a DC voltage, and do so with a sample of just a single pulse which could arrive at non-uniform interval times, would be appreciated if not. I'm interested in pulses of 0.01 to 0.5 ms pulses, and for any of them comparing to a known time and giving a DC output dependent on how much longer the actual pulse is than the ideal (where differences could be down to 0.1% of pusle length). I know the lazy way would be to have a clocked microcontroller just timing between pulse rise and fall, subtract in software away the expected length, then send an output to a I2C DAC chip, but I'd like to try learning some more electrically based rather than software methods.Thank you

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 21, 2021, 05:49:14 am
content: Yeah EDN sucks, and they broke most of their links a long time ago anyway.Seems there's a copy here (likely a dubious matter, but it's their responsibility not ours..):https://www.radiolocman.com/shem/schematics.html?di=532995It's just an integrator with reset, a S&H to follow it, and a series of switches to make it do the thing.Note that the level will decay slowly over time, between samples; charge is stored on C1 while the input is low, I think, and C2 when high. The use of CMOS switches and FET type op-amps makes this reasonable up to pretty fair duty cycles (like, using PP, PPS or C0G capacitors, and for less than 0.1% droop, a duty cycle below 1/1000 is probably fine, but maybe not 1/millions). For unlimited time between samples, better to also use the pulse to interrupt an MCU and run an ADC sample, thus preserving the information forever as digital bits free from analog decay. (Or, you know, anything made of equivalent logic, but the MCU is likely the most handy/accessible/compact solution. Minimal hardware would be something like, a parallel-output ADC with bus latch; those are bulky, and uncommon these days.)Note also that minimum pulse widths must be observed; there will be some error in propagation time between switches (especially the one configured as an inverter gate), and the switches can only discharge/set the capacitors as fast as their resistance and switching times allow.The mismatches should tend to manifest as nonzero intercept errors (charge injection, etc.), so can be subtracted out with a calibration step. Check that it doesn't vary with supply voltage or operating temperature, or if so, add those to the calibration table.You do have the advantage that, resolution is perfectly continuous -- limited instead by noise performance (sampling aperture basically), and whatever other sources of interference might apply. Whereas measuring your pulses with a typical MCU might give 7-16 bits accuracy, depending on hardware and clock speed. Which, the upper end of that is pretty good honestly, but if you're constrained for other reasons (very cheap MCU?) you'll be stuck by low clock rate, and an analog method might not even be that impractical, in a real-world application. (It likely won't be fantastic in current consumption, though -- op-amps of reasonable speed (say >10MHz GBW?) tend to consume a few mA. But this could be mitigated in a number of ways, too.)Tim

author: Infraviolet
author_rank: Super Contributor
timestamp: October 21, 2021, 08:37:16 am
content: Thank you for the link, and your extra noets are really helpful too.