Help understanding TI schematics.  Battery balance circuit.   - Page 1
Forum section: electronics / projects

author: viper
author_rank: Regular Contributor
timestamp: October 07, 2025, 05:05:17 am
content: Have attached a couple files. I've spent some time just trying to understand what TI did here. Primarily, I'd like to run this gear but I have to carefully evaluate failure modes and because unless there is an error, the balance stage would be stuck on if the balancer smokes. Those are N and P depletion FETs?And that is where bigger questions come in how in the world do the gate drives work? All I see is VDD with an odd path to ground. I'm certain I am looking wrong, but the schematic has confused me. Basically I'm trying to better understand how and when the gate states will change, and what happens if certain components fail. Just shooting for a fail-safe design. By the appearance, it would seem if FETs are still working, if the IC fails, this would default to a 'constant balance' condition? Honestly hung on that because balancing would depend on the logic. Pretty much don't understand their block diag! Help?

author: jwet
author_rank: Frequent Contributor
timestamp: October 07, 2025, 03:39:16 pm
content: I'll give this a try-The two FET's are enhancement mode N&P. Q2, the lower one, is an NMOS, Q1, the upper is a PMOS. The VCB output is like a standard CMOS output. When its high, the low FET is ON, when its low, the upper is on. The load is Rcb in both cases going through one or the other FET's. The logic block with the hysteresis turns on one or the other FET's (or none) on a cycle dependent on the Cd cap. The left comps and and the hyst divider determine which battery V is larger and turn on the appropriate FET to discharge it. It can flip flop back and forth and then do nothing when they're in the hysterisis band.The failure mode you can walk through for each component but it will come down to a fault where one or the other FET's is on drawing current through the Rcb. Some of these fault might require more than 1 fault. The balancing currents are not very large usually so worst case, you'll kill your battery in some time- not super dire.There is another class of balancers that use capacitors to take charge off the high battery and put in on the other cell. They are nominally more efficient and kind of elegant, they tend to be slower. Maxim made some of these. Since there is no DC path, unless a caps short the fault is just no balancing.You can add a bit of redundancy but having an additional enable switch, etc. If you rate things conservatively, keep ESD and surges out, the original should be extremely reliable.

author: viper
author_rank: Regular Contributor
timestamp: October 07, 2025, 04:39:57 pm
content: Quote from: jwet on October 07, 2025, 03:39:16 pmMan I SUPER appreciate your reply! I had to pick this up this morning with a fresh brain because this fried me yesterday. I TOTALLY forgot that P fets need a neg Vgs. To confirm, you believe the diagram is in error and those are enhancement type, not depletion as shown? There is a note under it that clearly mentions that Rclamp is to ensure the fets stay off and if they were depletion, a Vgs of 0V would ensure they are on, not off.Yeah, I hear you on active balancing. Certainly more efficient ways but this is part of a solar charge design in which there is power to burn. On a normal day, charge completion could happen in 24min or less, leaving the system mostly off the rest of the day.I would probably be in the region of 100mA for the balance resistor. Subject to change with some testing.

author: jwet
author_rank: Frequent Contributor
timestamp: October 07, 2025, 05:18:00 pm
content: Use thanks button.I don't know what you mean on depletion mode. The parts can be enhanced or floating- the resistor pull the gate up or down respective to turn them off in the floating case.Use a higher power R (derate) for balance R so if it gets stuck on, it won't burn up, etc.

author: viper
author_rank: Regular Contributor
timestamp: October 07, 2025, 06:12:38 pm
content: Quote from: jwet on October 07, 2025, 05:18:00 pmI was referencing the symbols in the diagram. They are depletion fets, correct? two solid bars rather than the 3 dashes for enhancement mode?Yes, I agree on the balance resistor. I was thinking about breaking that into two parallel components. Wire wound, over sized.

author: jwet
author_rank: Frequent Contributor
timestamp: October 08, 2025, 12:16:48 am
content: Wow Viper, I might have known that once but that brain cell died!Depletion mode mosfet's are incredibly rare these days. I wouldn't go by the schematic symbol anyway - they are standard enhancement mode with deceptive schematic symbols. Good catch.As for the R- use a thru hole device with a doubled rating and keep it off the board.