Precision constant current source - Page 1
Forum section: electronics / projects

author: Trafi1415
author_rank: Newbie
timestamp: October 07, 2017, 03:38:01 pm
content: I am designing and also hopefully building a current source mostly for learning purposes. Actually I got the idea when I thought that a precission current source would be an elegant way to study the effects of voltage bias on capacitance of ceramic caps. Because du/dt=I/C, I should be able to study the effect by plotting the time derivative of the voltage over a cap as a function of the voltage while I am charging it with the constant current source. I have come up with a following schematic for the task:My plan is to achieve a range of 100 nA to 100 uA by changing the Iref from 1.5 mV to 1.5 V. I guess the requirements for the bandwidth of the system depend on how small capacitances I am willing to measure. I figured out that if I want to measure capacitances as small as 15 pF the du/dt with the 100 nA current will be about 6.7 kV/s, so if I want the current to settle to the reference value within for example the first volt that would call for a bandwidth a bit higher than 0.35/(1V/6.7 kV/s)=2.3 kHz according to the BW = 0.35/rise time rule of thumb? I guess it would help if I could have the U2 to be very slow so the U1 wouldn't have to be that fast to still be fast enough to not cause the system to become unstable.I have now simulated the current control part without the U1 in LTspice to study the stability and step response and I have found couple of problems. First of all the step response overshoots indicating a lack of phase margin? Too bad I don't really know how to compensate a loop like this and the literature and app notes I have gone through so far have not helped. Below is the simulation results of both AC and DC analysis. They agree to each other but still I am a bit pessimistic whether I have done the AC analysis correctly. I tried to reduce the loop gain a bit by putting a voltage divider to the output of U2 but that was not clearly enough. I guess I could also make the sensing resistor smaller but then the offset voltage and signal to noise ratio could become a problem at the 100 nA level? I am grateful for any hints and corrections and I will of course post any subsequent progress including schematics etc.The DC analysis.The AC analysis.

author: wedgetail
author_rank: Contributor
timestamp: October 08, 2017, 04:48:24 am
content: I am very rusty on my step response analysis. If you have overshoot does this not mean that the loop is not fast enough? Since you are modelling what about a capacitor over R2? What change does this make to the response?Not sure about running U2 open loop, may be asking for trouble. If you want to try and reduce loop gain try adding your gain reducing the standard way, Rf/Ri, a feedback resistor and series resistor to the - input, the gain in U2 is then Rf/Ri. try a gain of approximately 30 to start withThis combination opens your design to some interesting experiments with proportional, integral and derivative control.The more I look at it it seems to me that you have too much gain in the loop. I am curious why do you have the Q1 and associated resistors? What happens if you leave them out ? This would allow you to slow the loop and experiment with the gain in the inverting amplifier U2.

author: mathias
author_rank: Regular Contributor
timestamp: October 08, 2017, 05:37:34 am
content: I suggest you remove the NPN transistor. It add gains when you don't need it (op amp does supply more than enough), and can only cause issues.

author: Trafi1415
author_rank: Newbie
timestamp: October 08, 2017, 08:09:20 am
content: Quote from: wedgetail on October 08, 2017, 04:48:24 amYes I guess you could say that the loop is not fast enough. As far as I understand the reason for that is that the loop gain is still positive when the second pole of the op amp starts to affect the phase of the loop gain. I tried simulating all sorts of capacitors from 1pF to 10 uF in parallel to R2 but they had very little effect. I have also played alot with the resistor sizes but they too seem to have very little effect. I think that next I have to try different op amps.Quote from: wedgetail on October 08, 2017, 04:48:24 amThat would be very nice but wouldn't that ruin my input impedance? Since I am aiming for 100 nA level the bias current and input impedance of the current sensing is quite crucial and the resistors required for typical Rf/Ri configuration would be unpractically large.The reason for having the Q1 in the loop is to make higher voltage measurements possible. I am not sure if I understood correctly what kind of topologies you were suggesting but if I want to be able to charge a capacitor to say 150 VDC then I definitely need some sort of level shifting and I do not know how to achieve that with just the op amp.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 08, 2017, 10:08:11 am
content: The NPN transistor is a problem, because of it's gain. In addition the gain will be nonlinear and there is a chance to get it stuck in saturation. If you need it for voltage shifting one could consider a base configuration. This is usually faster and as it is non inverting the non inverting input would be towards ground. Thus is would get easier to ad compensation to OP2 without directly effecting the input.For stability it is usually a good idea to have a resistor at the MOSFETs source and BJT emitter. This give a local FB for current control and reduces the gain.For a large current range it might be a good idea to change the resistor that does the V_C conversion as needed.Anyway, I see some problems with this circuit: the DUT is kind of floating. This makes it difficult to use shielded cables and to measure the voltage one the DUT. Capacitance from the lower side of the DUT towards ground would make the control loop even less stable.

author: Damianos
author_rank: Frequent Contributor
timestamp: October 08, 2017, 02:23:33 pm
content: If I understand correctly, in the initial schematic the load is seeming as floating. If this is the case, wouldn't be easier to use only one Op-Amp driving a N-channel FET and reading the voltage of a resistor in series with the source? The load would be connected from the positive supply to the drain.

author: Trafi1415
author_rank: Newbie
timestamp: October 08, 2017, 02:30:01 pm
content: Thanks a lot Kleinstein! I am not sure if this is anything like what you tried to describe but I got the step response to look a lot more stable by making the changes you suggested.Quote from: Damianos on October 08, 2017, 02:23:33 pmBasically yes but wouldn't the current flowing in and out of the drain-gate and gate-source capacitances ruin the measurements?

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: October 08, 2017, 02:52:26 pm
content: Hi,Let me offer a different way of measuring the effect of bias voltage on ceramic capacitors.The circuit uses a 555 timer. Instead of connecting the timing capacitor to ground, it is connected to an adjustable bias supply.The frequency or period of the oscillation can be used to determine the capacitance.LTspice ModelTheQ=(Cnom * 1.08*X)-(0.4*Cnom * X * (X/Vmax))is used to define a capacitor that varies with the voltage across it. As shown the formula gives 108% of the value at zero bias decreasing by 40% at the nominal voltage (essentially X5R).meas directives are used to measure the 555 period and frequency between the 2nd and 3rd rising edges of the 555 output.LTspice resultsI have attached the model.Note:I have not built this circuit. I was planning on building it with a small micro and a DAC controlled power bias supply to plot C versus V (bias).Regards,Jay_Diddy_B

author: Kleinstein
author_rank: Super Contributor
timestamp: October 08, 2017, 03:14:50 pm
content: The classical constant current sink circuit would have errors due to the capacitance at the FET, so it is not a good choice at the very low level for AC currents. The nasty part is that these capacitors are not linear.However the current circuit would have trouble if the DUT impedance gets to high at high frequency - thus something like large resistors or inductors. Any parasitic capacitance at the non inv. input of the OP could be a problem and require the control loop to be relatively slow. So one might have to adjust R8 together with R3. It can be ok for a capacitive DUT though.The shown circuit is about what I though, except without R2. Likely some of the resistors R1 and R6 in the control path should be lower in value - with current values it is relatively slow. Not sure the choice of the OP is a good one.The more usual way to measure the capacitance as a function of DC bias would be to have DC and AC voltage superimposed and measure the current with a kind of TIA/charge amplifier. This can be done a rather moderate frequencies (e.g. 1 KHz range).

author: Damianos
author_rank: Frequent Contributor
timestamp: October 08, 2017, 05:40:27 pm
content: Quote from: Trafi1415 on October 08, 2017, 02:30:01 pmYou are right (as also mentioned by Kleinstein), I overlooked the switching characteristics of the thing, because I used it in "steady state" cases, with long settling times.I cannot remember where I have seen that, but there was an application note, in which instead of pulsing the reference voltage, they used a switch in parallel with the load. I didn't tried it, so I have not any relative notes.

author: Trafi1415
author_rank: Newbie
timestamp: October 08, 2017, 07:35:24 pm
content: Jay_Diddy_B: That seems like a convenient way to achieve the task and it would surely be more robust than what I have planned. However, as mentioned earlier I am doing this mostly to learn about designing precision circuits and the capacitance measurement was just one use case.Kleinstein: You are right about the speed. It is too slow at the moment to be able to deal with small capacitances. Would you like to elaborate a bit on the op amp thing? I thought the one I had chosen was quite suitable because of the low bias and offset specs and also the low bandwidth. In current configuration the op amp is not the bandwidth limiting factor since with the current choice of resistors the bandwidth seems to be less than kHz.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 08, 2017, 07:55:57 pm
content: The circuit looks more like a slow switching circuit, than an analog circuit. What you're missing is: understanding of bounded inputs and outputs.For every output that spans a range, make sure every input that connects to it, uses the same range. (It's like fitting together pipes of the same size.)For linear stages (both the BJT and MOSFET stages here are intended to be linear, I think), the input and output ranges should also be proportional. That is, a linear relationship between output and input: a linear amplifier.To connect an output to an input with a smaller span, use a resistor divider -- an attenuator -- to reduce the output's range. Or, change the circuit to increase its input range.To go the opposite direction, you need an amplifier. After all, all linear amplifiers are simply the application of this principle: small input range, wide output range, linear relationship.So what to do with a transistor? You're already using the first option -- but the reason I've flagged it, is because the transistor itself is sloppy. The input voltage range of a BJT is approximately 0.5 to 0.7V. The offset is larger than the span, and the offset drifts considerably with temperature. More importantly: the gain is wildly variable, so that the input and output ranges of the transistor stage do not match up very well (i.e., it's not proportional, not linear).The nonlinearity is a double killer: it makes your op-amp work harder to find the right operating point, and it changes how fast it responds (loop gain). If the response is faster than it can handle, it overshoots, and you get ringing in the step response, or worse, oscillation.The solution is to add voltage in series with the B-E voltage, that acts to increase the input range, and linearize the output range. In other words: merely an emitter resistor. Emitter degeneration.Emitter voltage also acts to increase Vce(sat), i.e., how far the transistor can pull down. In other words, it restricts the output range -- the lower margin rises from GND to VCC * R(emitter) / (R(emitter) + R(collector)). So you can't go hog wild with this, depending on output requirements.Accordingly, emitter degeneration reduces the gain, but that's a good thing here: you just need a level shift operation!What's the minimum amount of degeneration that matters? You can model the BJT as an ideal (infinite gain) amplifier with built in emitter resistance: the value is r_e = 26mV / Ic. Yes, it depends on collector current -- that's where the nonlinearity comes from. (26mV is the average thermal voltage, Vth = k_B * T / q. T is absolute temperature, hence there's a tempco here, too -- different from, but related to, the Vbe tempco.)As for the MOSFET, source degeneration works precisely the same way, with the same benefit. Typical values are larger than for BJTs, because Vgs(th) is larger than Vbe, and overall gain is less. (On the upside, the linearity is better, so you need relatively less source resistance.)Could you do even better? Sure -- you could wire an op-amp with the MOSFET, using feedback on the source resistance, ensuring it delivers exactly the right current in the first place. This basically shifts all your circuit around, but leaves you with a high side IREF signal, which is annoying. A solution to this: use another current sink to deliver a current which drops V(IREF) across a resistor. That current sink can also use an op-amp, so that no error is introduced in the whole signal path. Now you can have ground referenced reference and load, which is nice.What else? Inevitably, the current sink will have some output capacitance, which means when the supply voltage changes suddenly, so too does V(IREF). In other words, at high frequencies, the PSRR (power supply rejection ratio) is ass. This can, in turn, be dealt with by using a differential current sink, so that two currents are transmitted to the high/floating side, and the difference taken: if they have the same capacitance, then sudden changes produce no difference, greatly improving PSRR. Downside: more circuit complexity.Hope this helps,Tim

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: October 08, 2017, 08:23:54 pm
content: Hi,Here is another idea for you. Three similar circuits, all use a current mirror. In the first circuit the current mirror is open loop. In the second circuit the current loop is closed. In the third circuit the current in the capacitor under test is fed into a virtual ground.The idea is that you pulse the current source and then measure the voltage of steps.C = I x t / dVyou derive the function of C versus VYou need a mechanism to discharge the caps.Model attached.Regards,Jay_Diddy_B

author: Benta
author_rank: Super Contributor
timestamp: October 08, 2017, 08:40:36 pm
content: The OP wants to create a current source in the nA to uA range. Fine.In that case, using a MOSFET is doomed from the start. Drain-source leakage is already in the uA range.You need a bipolar pass element.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 08, 2017, 09:35:55 pm
content: Quote from: Benta on October 08, 2017, 08:40:36 pmBSS84 has ~nA leakage, typical.(The datasheet may not specify this, because it takes time to measure.)Edit: offhand, I have a BSS84 at 12V (DS, Vgs = 0) showing 0.000V into 10M, or less than 0.1nA.Tim

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: October 08, 2017, 09:45:09 pm
content: Hi,I can make a modification to my proposed circuit to deal with leakage currents. I have essentially made the current source class A by introducing a current sink M4. The current sink does not need to be precise, because the op-amp is controlling the difference between the source M2 and the sink M4.The interesting thing about this configuration is that you can connect a scope probe 10 Mfrom VC_3 to ground and it doesn't impact the capacitor current.This probably isn't the right op-amp for the job. It was chosen to illustrate the concept.Here I show the circuit operating at 10uA down to 200pA:The results are:Model is attached.Regards,Jay_Diddy_B

author: Benta
author_rank: Super Contributor
timestamp: October 08, 2017, 10:00:44 pm
content: Quote from: T3sl4co1l on October 08, 2017, 09:35:55 pmFrom the BSS84 datasheet (NXP):Drain leakage current (max.):-40 V, TJ+25 C: -100 nA-50 V, TJ+25 C: -10 uA-50 V, TJ+125 C: -60 uAI believe in using datasheets. And I believe in using worst case ratings when designing, they never let me down. Multimeters sometimes do.

author: David Hess
author_rank: Super Contributor
timestamp: October 08, 2017, 11:05:47 pm
content: Long ago I built something like what you are suggesting for measuring the curve of inductance saturation. It worked great for a brute force design which required solving a quadratic equation to make a measurement but I would be more subtle today.The bandwidth and slew rate requirements are low so stick the capacitor under test inside the feedback loop of an operational amplifier to make an integrator. Now the output is low impedance under all conditions making it easy to measure and the current source sees a constant voltage. The current into the virtual ground may be provided as a current or more likely as a voltage through a resistor which isolates the driving capacitance.The integrator is reset either by using it within a simple function generator or by driving a reverse current into the input. This avoids having to deal with a switch across the test capacitor although with care, this could be done as well.Instead of switching the transistor current source, use a diode bridge to switch the current as shown below. Now the current sources operate continuously and the bridge diodes provide low capacitance switching.If I wanted something a little easier to interpret than differentiating the output of the ramp, then I would do what Jay_Diddy_B suggested with the capacitor grounded at one end into an adjustable voltage as part of an oscillator. Now the oscillation frequency is proportional to capacitance.

author: CD4007UB
author_rank: Contributor
timestamp: October 09, 2017, 12:11:46 am
content: Quote from: Trafi1415 on October 07, 2017, 03:38:01 pmHave you considered using a (modified) Howland current source? This is the design that is often used for precison current sources - see TI app note AN-1515 (snoa474a). You need to use a good-quality difference amplifier (e.g., INA105) and a wide-band FET-input op amp (e.g., OPA602) in the feedback loop.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: October 09, 2017, 12:15:15 am
content: Hi David and the group,Some great advice from David.The circuit that I have is an integrator with M1 - M4 providing level shifting and gain.If I use a high voltage op-amp, the LTC6090 is well suited for this application.Link:http://www.linear.com/product/LTC6090I have this LTspice model:I have added a second op-amp as a clamp to limit the voltage on the capacitor under test.I have attached this model.Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: October 09, 2017, 12:55:44 am
content: Quote from: CD4007UB on October 09, 2017, 12:11:46 amHi,Here is a model for the Howland Current Source version. I have added U2 to see the maximum voltage on the capacitor under test.And here are the results from the model.I have attached the model.Regards,Jay_Diddy_B

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 09, 2017, 01:02:47 am
content: Quote from: Benta on October 08, 2017, 10:00:44 pmIf this were a design for production, that's absolutely prudent!However, it is also important to understand the typical ratings of parts, and the parameter spread.This is a very "typical" application. It's a one-off for testing components, and the parts can be characterized. (Indeed, they can be characterized during the calibration step.) I just characterized a part over three orders of magnitude better than the datasheet -- what does that tell you about the datasheet values? They are very loose, and like I said, for jellybean parts, it's all about testing speed!You can go look for low leakage MOSFETs, but you will pay extra for them -- for exactly this reason. Often times, a "low leakage" part is simply a 100% jellybean part that's gone through extra testing. You're not paying for selection -- the yield for that test might be nearly 100% -- you're paying for testing!Others to check out: RF transistor B-C junctions versus picoampere diodes; ceramic caps shorting at extreme voltages (e.g., a 6.3V part failing at 120V); etc.On a related, but actually intentional, note: RF transistors are NOT rated based on Vceo/Vcbo, but on the maximum DC voltage that should be used in a typical (inductive loaded) application. In other words, old schooldesign centerratings. They typically break down at 2.5 times this rating.Lots of gotchas out there.Tim

author: Trafi1415
author_rank: Newbie
timestamp: October 09, 2017, 02:30:00 pm
content: Thanks a lot everybody! I still need some time to digest all of your advice and circuits but I really like especially the improved version of the current mirror using circuit of Jay_Diddy_P and also the Howland current source. Since the main goal was to learn new stuff it seems like this is already a succesfull project even though the use case I had thought of has been criticized quite a lot. I still think that it could be a decent way to do the bias effect measurement for large amount of caps on a large voltage range especially if the scope could be configured in xy mode where the x-channel would be the voltage over the cap and the y-channel would be the derivative using scope math on the x-channel. Too bad I just checked that in my rigol you can't use math in xy-mode so there goes that.Luckily, whether the initial idea was stupid or not is not crucial and I'm going to build some of those circuits anyway.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 09, 2017, 02:46:38 pm
content: For that particular case, I simply charge the part with a CCS or resistor -- it doesn't much matter, as long as the V(I) and jig capacitance are known. Then I derive C(V) in a spreadsheet.Example:STP19NM50N drain capacitance charging slope, with 97.8k resistor from 514V. From that, I derived this capacitance curve:Note the large discrepancy from the datasheet's purported curve -- beware!If you're buying ceramic capacitors, the manufacturer usually has the C(V) curve ... somewhere. Sometimes it's linked from the distributor's database, or in the part's primary datasheet (Samsung capacitors are usually good about this). Others have it in a separate document (check the manufacturer's website), or on a (usually online accessible or downloadable) proprietary database you have to go look up (Kemet, Murata).If you're salvaging ceramic capacitors, a very loose, hand-waving test can be performed: connect a squarewave generator (50 ohm source impedance) to a large film capacitor to the capacitor-under-test. Connect a large value resistor (100k+) to the CUT and bias this with a variable supply. Monitor the generator's waveform with an oscilloscope. The square wave will be rounded over according to the RC time constant, where C is the total of the film capacitor in series with the CUT. On the scope, measure risetime, or just eyeball it, even. First measure risetime at bias = 0. Then raise bias, and note when risetime is 70% of its initial value. This is the -3dB point, more or less the useful operating range of the capacitor. (You can still make use of the capacitor at higher bias levels, if you can deal with the ever shrinking capacitance that remains.)Even simpler, if you have a squarewave generator with adjustable output DC bias, over a range that's useful for testing (say, 10V or more, for testing 6.3V capacitors pulled from computer hardware), you don't need the film cap and bias supply.Tim

author: Trafi1415
author_rank: Newbie
timestamp: October 12, 2017, 06:36:43 pm
content: Thanks for the tips Tim.I don't think I am going to breadboard these things but I will rather order prototype PCBs so I can also learn also about proper PCB design of precision circuits. The only problem is that the PCB design fixes the op amp pinout so I would like some comments on my op amp choices and error budget design. Also if there are any obivious gotchas about the layout I should know right away I would be glad to hear but I'll also post the layouts before ordering.For the Howland circuit I think the LTC6090 is a no brainer because of the voltage range. However should I take it in the TSSOP18 package with guard pins or do they matter here? I googled about this and found an ap note AN1258 from Microchip. It suggests that the leakage resistance of nearby traces on a clean PCB at low humidity would be around 1000 Gohm and about 1 Gigaohm in high humidity and contaminated PCB. I guess if I keep the PCB clean it wont be a problem to use the so-8 package?For the op amp in the current mirror based circuit I tried to do actual calculations about error budget. Lets say I am aiming for a 1 % accuracy. I can use 0.1 % rated resistor for the current measurement so this leaves me 0.9 % of error margin for other components. If I only had offset voltage based errors that would mean I could allow an offset voltage of 100 nA*0.9%*100 kohm= 90uV since the measuring resistor is 100 kohm? Then if I only had bias based errors I could allow for a bias current of 90 uV/R5=40 nA? Now I can look at op amps with maximum offset below 90 uV and maximum bias under 40 nA and when I find a promising one I need to check that the combined error doesn't exceed the error budget? Another point is that I need the op amp to have a voltage supply and output swing high enough to be able to drive the mosfet that is setting the current. Am I completely lost here or is this anywhere near how it's done?I used the wonderfull search tool of digikey and stumbled upon OP07 and OP177 from analog devices and LT6011 from Linear Technology. The LT6011 is a double op amp but I think I could use the other op amp for example to buffer the output of the current mirror for measurements.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 13, 2017, 12:24:28 am
content: Guard traces aren't important here, nor are fancy op-amps. A CMOS or JFET amp will do fine!I'd go with SO-8 (dual) because nobody's going to screw up the pinout and it's easy to solder.Tim

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: October 13, 2017, 01:50:57 am
content: Hi,I chose the LT6090 for the Howland current source and the op-amp circuits based on its:High voltage capability (140V)Low input bias current (50pA)The S8E package will be fine in this application, you do not need the guard traces.Note that this part has an exposed pad, the pad is connected to the negative supply.This circuit can use a standard CMOS or JFET op-amp. The high voltage capability comes from the level shifting transistors. The op-amp should have low input bias current.Regards,Jay_Diddy_B

author: mbless
author_rank: Regular Contributor
timestamp: October 14, 2017, 01:09:50 pm
content: I made a current source earlier this year with the intention of sharing with the community but later decided against it. Since it appears to be similar to what you want to do, I'll go ahead and share it. It works like a constant-current load so you can hook up devices with different burden voltages and not have worry about it. The set point currents are from 500mA to 10nA, but those are customizable given the PCB layout. I wanted it to be accurate out of the box, so I used high-tolerance resistors aiming for current tolerances less than 0.1% for most of the ranges. The measured unit met the tolerances except for the nAs, likely due to my measurement setup.I posted all of the documentation on Github here:iSource_Precision-Current-Source. I attached the schematic, glamour shots, and a plot of designed vs. measured tolerance here. I still have 2 more bare PCBs and enough parts to assemble another unit if anyone is interested.

author: JohnPen
author_rank: Regular Contributor
timestamp: January 19, 2018, 10:04:51 am
content: Hi mbless Do you still have a bare PCB available for your Precision Current Source? If so I would like to purchase one. I am located in the UK so international postage would be involved. Hopefully you have a PayPal a/c to facilitate the payment process.Thanks,John

author: mbless
author_rank: Regular Contributor
timestamp: January 19, 2018, 01:42:32 pm
content: Quote from: JohnPen on January 19, 2018, 10:04:51 amPM sent. I have 2 bare PCBs and an assembled unit I can sell.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 19, 2018, 07:19:06 pm
content: First question that comes to mind, does your current source need to be bipolar or not (meaning do you want to be able to source and sink or just source/or sink current)? I assume you don't necessarily need bipolar if all you want is charging a capacitor.Just a quick first note: you should provide some way of discharging the capacitor if you want to do any kind of automated measurement. An NMOS transistor should do the trick to shunt the capacitor to ground.Speaking of ground, you can tie one pin of the capacitor to ground and the other to your current source.As others have suggested, the improved Howland pump is certainly one way to go.You may find it hard to get a linear voltage-to-current conversion on the whole 100nA-100µA range. This is quite a dynamic range especially for low currents. You may not care much though, if you can calibrate it for a few discrete levels.You may find more ideas in:http://www.linear.com/designtools/currentsense/19-current_control.pdf