Potential DIY Oscilloscope project, screen refresh rate? - Page 1
Forum section: electronics / projects

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 21, 2019, 09:31:47 am
content: Hi all,I'm tempted by a DIY oscilloscope project as I'm enjoy high speed data, analogue circuits and Verilog (and I want a good affordable rackmount scope). I've been searching for existing scope projects and found a few but none completed because, I assume, they are difficult. I want to do a single channel USB scope at 1GHz. The way I see it, is a scope could be quite easy (relative to an off the shelf product) to design and make as long as you're happy with sending images of the waveform over the USB. My question from this post is asking is this enough compared to sending all of the data to the PC? 1GB/s of data is a lot and way too much for a human to comprehend. We could do some waveform overlaying in those images to get a higher psuedo refresh rate, again done in the FPGA. Perhaps sending multiple arrays and letting the PC print as many as possible to the screen could also be an option. Ethernet could also be a nice option on FPGAs.Just trying to get some understanding of the requirements before I attempt something like this.PS. Does anyone have references or schematics to existing analogue front end designs?Thanks

author: David Hess
author_rank: Super Contributor
timestamp: April 21, 2019, 06:22:32 pm
content: Quote from: Boscoe on April 21, 2019, 09:31:47 amI have a similar project going but more as a stand alone instrument and what you suggest is exactly what I am pursuing but for a different reasons. DPOs (digital phosphor oscilloscopes) achieved very high waveform acquisition rates by accumulating a histogram in real time and displaying it at the screen refresh rate. If it is done correctly, then the histogram faithfully represents the statistical contents of the input. I am more interested in minimum blind time and maintaining the maximum sample rate under all conditions.The alternative, which most DSOs use, is to capture into a long sample record (megabytes these days) and generate the display record in post processing which has the advantages of retaining the original acquisition for further processing and leveraging the high performance available in commodity CPUs without custom hardware.The histogram method is more suitable for USB instrumentation because there is no way USB can keep up with high sample rates.Both methods could be done simultaneously. With USB, the hardware generated histogram could be displayed in real time and the original acquisition made available as needed.QuoteTektronix and HP oscilloscopes designed before about 1990 are fully documented and their service manuals are a treasure trove of circuit design information.TheTektronix Circuit Conceptsbooks have a lot of what you need. Check out Vertical Amplifier Circuits especially.Chapter 7 of The Art and Science of Analog Circuit Design by Jim Williams, Signal Conditioning in Oscilloscopes and the Spirit of Invention by Steve Roach, may be the most recent discussion about what you are asking about although it deals with the high impedance side which is only applicable up to about 500 MHz. If you want 1 GHz of bandwidth, then low impedance circuit design is required.Chapter 14 of Analog Circuit Design, Art, Science, and Personalities by Jim Williams, Good Engineering and Fast Vertical Amplifiers by John Addis, will be helpful if you want such high bandwidths and is more applicable to low impedance high bandwidth circuits.

author: rhb
author_rank: Super Contributor
timestamp: April 21, 2019, 06:58:42 pm
content: FWIW I am engaged in a 2-3 year effort to write a FOSS DSO FW stack for Zynq and Cyclone V based COTS DSOs. Intent is to just replace the crappy FW on COTS instruments. However, it will be readily usable on a custom design.While progress seems almost glacial, in fact I'm making significant headway. But there is a lot of infrastructure to develop. In addition, my background is oil exploration seismic which while a lot more sophisticated than what the EE community does, it quite different. Seismic can take a week to process 10 TB of data on 20-30,000 CPU cores. That is not practical for EE applications of DSP.Historically the AFE of a scope is a major problem. Tek kept the design equations as a trade secret for many years. IThe big issue is component heating on a fast step. Front end alignment of a fast scope is a long, iterative process.I strongly recommend reading the service manuals for the Tek 465, 475 and 485. They explain every circuit segment in the instrument in exquisite detail and are an absolute joy to read. Tek at its best.David is absolutely correct that the way to handle the data is to construct a histogram in XY and then sample that at 60 Hz for the display.Persistence, presenting the histogram of the last N sweeps is hard. I still don't know how to do that without requiring excessive resources.Component tolerance spread in the AFE is best handled by a DSP filter in the FPGA.

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 21, 2019, 08:28:29 pm
content: Quote from: David Hess on April 21, 2019, 06:22:32 pmI'm curious, what are you reasons for making one?I like the idea of the histogram, this makes sense. I'm going to do some reading about this.Just found a pdf of The Art and Science of Analog Circuit Design, I like the style it's written in. That is a great chapter, just read through it. Hardcore analogue electronics! I seriously need to brush up. I feel so many electronic engineers know their way around a microcontroller but analogue electronics is the real deal!I'll add Good Engineering and Fast Vertical Amplifiers to my reading list, too.I will clarify I'm looking for a 1GHz sample rate so 300MHz of bandwidth would be about right.I would love a method to implement a front ens with opamps but the real killer is the voltage and noise performance, bandwidth is not easy there either. I think I might cheat and restrict the input range to something like +/-100V. I think that would cover the vast majority of my projects.

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 21, 2019, 08:32:22 pm
content: Quote from: rhb on April 21, 2019, 06:58:42 pmSorry, I have been in electronics for 10 years and have no idea what FOSS and COTS is. English please!Congratulations on your progress, the project sounds very interesting. It always makes sense to do it properly once. If others can benefit, that's fantastic.I am finding the AFE the hardest part, I will check out your suggestions, thank you.I think I will collate my findings and create some kind of reference on my website. I think a scope AFE standard schematic could be very useful and portable.

author: rhb
author_rank: Super Contributor
timestamp: April 21, 2019, 09:03:51 pm
content: Sorry.FOSS = Free Open Source SoftwareCOTS = Commercial Off The ShelfThe hard part of an AFE is the anti-alias filter design. I've been thinking a lot about that the last month or so. I *think* I have a formulation for finding the optimal filter profile, but am still considering the matter. Good step response is the primary motivation.The fundamental problem is you need -6 dB per bit at Nyquist to prevent aliasing. That's not too hard for 8 bits, but for 12 or 14 bits using something like an HMCAD1520 ADC it's a rather high order analog filter. Making those with production line reproducibility is not easy. The general solution is to oversample, apply a DSP filter in the FPGA and then decimate.

author: David Hess
author_rank: Super Contributor
timestamp: April 21, 2019, 09:38:11 pm
content: Quote from: Boscoe on April 21, 2019, 08:28:29 pmNobody else does in a low cost instrument and instead relies on marketing gimmicks like excessively long record length.QuoteOh, so not so high in bandwidth. 300 MHz is right in the range where a high impedance input is feasible so that chapter will directly apply to what you are doing if you decide to make it high impedance.QuoteNoise is only an issue in the stages before and including the first amplification stage.The problem with both voltage and current feedback operational amplifiers is that shunt feedback is not conducive to good transient response, none of them are really fast enough (at least for a 300 MHz design), and they have terrible overload recovery.Something like an OPA860 operational transconductance amplifier should work better if you prefer IC based gain stages; it is where I would start if I did not want to mess around with RF transistors. Texas Instruments makes some ASICs which are suitable for oscilloscope gain stages; lots of low end oscilloscopes use them.

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 21, 2019, 09:40:55 pm
content: Quote from: rhb on April 21, 2019, 09:03:51 pmAhhh, got you!The number of hard parts of the AFE is getting bigger!I didn't know about that criteria for the aliasing, do you gave a source? I'd like to read into to that.Hmmm, I don't like the idea of the oversampling. That's a lot of expensive ADC going to waste.Do you have any of your work public in some kind of repository?

author: rhb
author_rank: Super Contributor
timestamp: April 22, 2019, 12:06:58 am
content: I don't have anything online except what I write here or another forum. I greatly prefer this one.The aliasing problem is treated in the first chapter of any book on DSP, however, the practical details of the filter are not.Each pole of a low pass filter provides a -6 dB reduction in amplitude per octave. So to reduce signal at Nyquist below the threshold of a single bit you need -6 dB per ADC bit. However, that requires that the corner frequency of the low pass filter be 1/2 of Nyquist. In general OEMs do not want to spend that much on the ADC, so they compromise and make the filter -3 dB per bit, sometimes less. They then apply an FIR low pass filter using an FPGA to suppress the portion of the spectrum where the aliased energy appears.That would be OK if they did not use a boxcar aka brickwall band pass or something very close to it. This results in the horrible ringing that you see on a step on even expensive DSOs from Keysight and others. Steep edges in frequency produce ringing in the time domain. There is no way to avoid it.To make matters worse, all the DSOs I've tested use a symmetric sinc(t) interpolator. What is known in seismic processing as a "zero phase" operator. The correct interpolator is minimum phase or maximally flat phase as the EE community calls it. The use of a zero phase interpolator results in spurious artifacts preceding a step. The Instek GDS2000E only applies the interpolator in vector mode. The Owon XDS2012A always applies a zero phase sinc(t) even in dot mode.25 shows a 100 ps pulse from one of Leo Bodnar's BNC units which is available with an impulse output by request. The display is in dot mode and there is no ringing before the impulse. 26 shows the ringing before the impulse created by using a zero phase interpolator instead of minimum phase when vector mode is turned on. It should be noted that the impulse has a duration which is less than the 1 ns sample rate of the DSO.There is a widespread misunderstanding that an impulse which falls between samples will be missed. As can be seen here, that is not correct. An impulse of infinitessimal duration has a constant amplitude bandwidth that extends from DC to infinite frequency. So whatever frequencies fall in the BW of the AFE *will* be presented without regard to the time of the impulse in relationship to the sampling.One can, in fact, sample at 10-20% of Nyquist sampling without aliasing using a technique called "compressive sensing". The idea originates with the work of David Donoho and Emmanuel Candes and has become very important for speeding up MRI acquisition to enable things like functional MRI studies. The mathematical details are very difficult, but fortunately, actual application is no harder than using an FFT. However, the amount of computation required is not insignificant.A compressive sensing DSO was constructed at Georgia Tech as part of the work for a PhD granted in 2014. The fundamental requirement for compressive sensing is that the sampling times be uncorrelated. They must seem to be random over the duration of the record.

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 22, 2019, 08:20:30 am
content: Quote from: rhb on April 22, 2019, 12:06:58 amBy the looks of it, excessive phase distortion is inevitable in the input filter. Perhaps with a bit more budget (large FPGA) with could use a FIR to correct for the phase in the input filter rather than supressing the frequency response like you mention (seems like craziness, that). Just doing a few calcs, you'd need at least a 256 tap filter to correct for an 8th order input filter. That's a lot of taps for 1GHz SPS.I did findhttps://download.atlantis-press.com/article/23421.pdfhowever. It's a paper for a high speed parallel FIR. I have implemented large FIRs on FPGAs before in an audio DSP project. It was a 2048 tap beast using block RAM for the 32bit coefs with a shared multiplier running at 200MHz.

author: rhb
author_rank: Super Contributor
timestamp: April 22, 2019, 01:52:34 pm
content: The Fourier transform of a boxcar in frequency is a sinc(t). The only way to eliminate the ringing in time is to not have a sharp edge. In seismic work cosine taper edges are typical, but the filter is being specified and applied in the frequency domain. The usual specification is a trapezoid, f0, f1, f2, f3. The actual implementation commonly uses a cosine taper for the slopes of the trapezoid. Filters to flatten the spectrum such as the classic Wiener prediction error filter are designed differently.All the work is being done on recorded data. So it's a lot easier to do basic stuff. Of course, when you want to create a 3D image from 10 TB of data, it gets rather more demanding. At a very basic level each sample in the output volume requires a mathematical summation of a 150K-500K input samples. That is a week or two with tens of thousands of CPU cores.Good phase response is not particularly a problem so long as one is able to accept the latency. That's a problem in audio, but not in a DSO.I'd appreciate an explanation of your estimate of the number of taps. That's a lot of zeros in the transfer function. I've been reading "VLSI Digital Signal Processing Systems" by K.K. Parhi and "FPGA-based Implementation of signal Processing Systems" by Roger Woods et al to help me make the transition from DSP in recorded time to DSP in real time. Aside from having very different constraints, the terminology in the seismic and EE communities is completely different.Thomas H. Lee presents an example of an analog maximally flat phase low pass filter in "Planar Microwave Engineering" so I don't see any serious obstacle other than the mathematics of the Fourier transform.The Gaussian taper pass band edge gets a lot of lip service in EE, but rather less use. However, sech(x) is symmetric in time and frequency, so it is a good candidate for consideration,If you are using regular sampling, a low pass anti-alias filter is an absolute necessity. The aliasing arises because the Fourier transform of a spike series is a spike series. If the sampling is sufficiently random, then the transform of the sampling interval is a spike in frequency and aliasing doesn't occur.I spent most of my time from 2013 to 2016 studying compressive sensing. In the process I read "A Mathematical Introduction to Compressive Sensing" by Foucart and Rauhut twice and "A Wavelet Tour of Signal Processing" by Mallat once.followed by the original papers by Candes, Donoho, Tanner et al. In total about 3000 pages of the most complex mathematics I've ever read. I had to read F&R twice bacause I really needed the mathematical foundations presented by Mallat. Subsequently as a consequence of some papers by Donoho I read quite a bit from "Convex Polytopes" by Grunbaum and "Lectures on Polytopes" by Ziegler to gain a better understanding of a fast algorithm for solving Ax=y using an L1 norm.I plan to revisit all that at some point, but I need to master the FPGA implementation of FIR and IIR filters at high clock rates first. I've bought a Tek 11801 and four 20 GHz dual channel, 13 ps rise time sampling heads so I can measure bit skew rather than rely on Vivado and Quartus to calculate it correctly. Just constructing an 8 line fixture with lines matched to a few ps is going to be a challenge.The HMCAD1520 offers 8, 12 and 14 bit sampling at different clock rates, so filtering that in an FPGA real estate efficient manner is going to be a challenge. An additional requirement is arbitrary, user specified filter pipeline as the LeCroy offers. So I will be attempting to use the partial reconfiguration feature of the Zynq line.My current focus is the FPGA input to DDR section. I am investigating the anti-alias filter aspect to the extent that I must know what the signal passband looks like to do the post ADC processing, but I'm not going past the filter shape into the details of the actual analog filter implementation, attenuator responses, etc. I'm trying to eat an elephant, so I'm taking it one bite at a time.It appears that we share a common interest with enough overlap in skill sets to be able to communicate, but with many critical skills the other lacks. So I'm hopeful we can collaborate on making this happen sooner rather than later.I have a large DSP library going back to the "The Interpolation, Extrapolation and Smoothing of Stationary Time Series" by Norbert Wiener which is where DSP starts and was trained by a member of Wiener's Geophysical Analysis Group. Of all the books, I think "An Introduction to Digital Signal Processing" by John H. Karl is probably the best general presentation. The classic text is "Geophysical Signal Analysis" by Robinson and Treitel, the most prominent members of Wiener's GAG. They literally wrote the book on DSP in the 50's and 60's in the form of a series of professional papers which were published as "The Robinson and Treitel Reader" by Seismograph Service Corporation. "Geophysical Signal Analysis" is those papers reworked into a book. R&T focuses quite a lot on the problem of water layer reverberation as that was the driving application in seismic work. Hence, my suggestion of Karl instead.In closing, the screen refresh rate is limited by the display. Even at 120 Hz that's an eternity compared to the data sample rates.

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 22, 2019, 04:18:47 pm
content: Quote from: rhb on April 22, 2019, 01:52:34 pmI have to admit, most of this is going over my head. With regards to the phase response, is this not import to maintain coherent rising edges? Isn't it the latency we're not concerned about?QuoteThis reading is very impressive. I hope I get to spend this much time learning at some point. I'll be sure to visit "Planar Microwave Engineering" soon. I really regret not taking that DSP course at uni!QuoteAlthough having only done a skim read, the paper in my previous post covers it all I believe. In my experience with FPGAs, you'll save yourself a lot of time and grey hair by designing and simulating the circuit before committing to debugging hardware.QuoteThat ADC does look like a great candidate, seems to be everything rolled into one and at a good price, too. I was looking at the TI solutions. They have a 12bit 1GSPS part for arounf £300, £85 is much better!DDR deserialisers are a done deal from the likes of Xilinx and Altera. Make sure you have done your homework and designed a good PCB then you can simply go through the DDR wizard. Yes, there is a lot of work here and I understand what you mean, I'm also trying to understand this aspect.I'd be more than happy to collaborate although the amount of time I'll be able to commit would be erratic at best.Is this a physical library? I'd love to get the chance to read some of these topics.

author: rhb
author_rank: Super Contributor
timestamp: April 22, 2019, 05:13:39 pm
content: Linear phase is exactly the desired waveform shape with a constant delay. Most of your problems with what I wrote are I'm a geophysicist and I use the terminology of mathematicians as that's what the people I learned from were taught. You're used to the EE description which is what is currently baffling me.I recently received an autobiography Wiener wrote. I've only glanced at it, but it looks as if it will be fun to read.Hands down the best reference on classic Wiener-Shannon DSP is "Random Data" by Bendat and Piersol. However, it is strictly a math book. If you're doing work with recorded data it's perfect. If you're doing real time there is a *lot* more to learn.I bought Parhi because Woods et al referenced it so much. It is fantastic. It goes into great detail about all the various ways you can lay out parallel and serial filter implementations. I can't recommend it more highly. I plan to implement and test all the various topologies on the Zynq & Cyclone V and compare Vivado and Quartus timings to what I measure. Lee is wonderful to read. I also ordered his other book and a copy of "Microwave Engineering" by Pozar. There are a couple more EM texts I am considering, but I want to review what I already have first.I'd *much* rather have access to all the data worldwide of a super major oil company so I could analyze and model sedimentary rock properties for the whole world. But I can't get that, so this is the next best thing that I could find. I'll be 66 shortly. I've got to be learning something new. So I'm pursuing a DIY PhD in EE. No real point to it except to have fun. Fortunately, 1990 era test gear is fairly cheap. So I now have a lab that would have cost $200K+ for less than $15K. Of course, the best part is I'm in charge and I can do anything my attention deficit disorder points me at.It is a physical 5000+ volume library. I just got rid of 500 lbs of old journals to make more room for books. It's one of the great pleasures of my life. I can walk in the library, pull 3-4 books off the shelf and find almost any answer. It's all on commercial library shelving in what was the 2 car garage. I've never had occasion to use them, but I have the full 5 volume set of the CalTech Bateman Manuscript Project edited by Erdelyi et al. It's the ne plus ultra of integral tables. Cited by everyone, but almost pure unobtainium. And quite a few other classic monographs that are almost impossible to get a hold of. It has cost me the price of a good house, but I've also made a lot of money by being the person who knew the answer on Monday morning to a question posed in a meeting late on Friday. Usually with only a few hours effort to hunt through the library for the solution. It presented such an illusion of brilliance on my part I took to saying, "Obviously your have me confused with someone who knows what he is doing."The wonderful thing about real books is how fast you can skim through them and how much you can locate from physical memory that something is in a certain book in the 1st third at the bottom of the RH page.

author: ebastler
author_rank: Super Contributor
timestamp: April 22, 2019, 05:31:30 pm
content: Quote from: Boscoe on April 21, 2019, 09:31:47 amA lot of good and interesting discussion above, but I think nobody has commented on this aspect yet:I would strongly advise to design a two-channel unit. There are so many applications where the relationship between two signals matters: Be it phase relationship in the analog domain, or correlations between digital signals. Havingmorethan two channels is mostly a convenience (with rare exceptions). But having only a single channel is severely limiting in my experience. There's a reason why, well back in the age of analog scopes, single-channel units have become almost extinct!

author: Mechatrommer
author_rank: Super Contributor
timestamp: April 22, 2019, 06:19:42 pm
content: Quote from: rhb on April 22, 2019, 12:06:58 amso, now we have foundation to sample 1GHz BW signal (highest harmonics of possibly distorted signal disintegrity, not mere 1GHz pure sine) at 100MSps rate, 10GHz at 1GSps etc etc... it must be cheap! than whats currently offered by constant time interval Nyquist sampling rate technique. my question... where is it now? or whats the progress (current in mass production maybe?) after this 5 years, i cant wait.

author: rhb
author_rank: Super Contributor
timestamp: April 22, 2019, 06:51:01 pm
content: I plan to work on it eventually, but I'm starting with the basic regular sampling model.The big issue with compressive sensing is the CPU power needed. It's significant. It's certainly usable for a very high BW one shot, but that may be all at the moment. and you might have to wait 20 minutes to see your trace.I have not read any of the literature since 2016. The initial MRI implementations were taking several hours to process the data which led to an intense amount of work to speed that up. I know that they were able to get large speedups, but don't recall the details. And not the faintest inkling of whether they would meet the speed requirements of a fast DSO.Donoho originated the concept and provided the mathematical proof in 2004. It took 10 years for someone to do a DSO implementation for a PhD project. So 2024 seems a reasonable time frame for a COTS version.I would love to have someone to discuss this with, but even the mathematicians I know turn pale when they look at the math. I know one Stanford PhD who is familiar with the math, but he doesn't want to deal with it unless he's getting paid $$$. The other couple of people I know are bound by confidentiality agreements and can't talk about it in significant detail. When you consider that it's 1-2 years of work to learn the subject starting from the level of a Stanford PhD in geophysics, that puts the bill for developing internal company expertise at $500K. So not sharing is not surprising.My understanding of the mathematics is that to get 10 GHz of BW at 1 GSa/s average sample rate requires a clock resolution of well under 100 ps in addition to solving an NP-hard problem. However, it's not that bad in practice. Donoho proved in September 2004 that the L1 solution to Ax=y where x is sparse can be solved in L1 time. But you still need the clock resolution so far as I can tell.He later made a connection to regular polytopes in N dimensional space. As the number of dimensions increases, the probability of any particular point lying on the convex hull approaches 1. So there is the potential for a very fast algorithm derived from computational geometry.

author: David Hess
author_rank: Super Contributor
timestamp: April 22, 2019, 10:18:39 pm
content: Rhb and I disagree about the aliasing in digital storage oscilloscopes. The typical Gaussian or Bessel response of -6dB/octave is eminently feasible and almost universally used except somewhere above 500 MHz where it becomes prohibitive to implement. This results in noticeable pulse distortion for bandwidth limited edges with sample rates of only 2.5 times but the added distortion is not too much greater than the expected transient response error anyway. If no reconstruction is used, then it is usually not even noticed at slower sweep speeds. A relatively easy way to avoid this if it will be a problem is to increase the sample rate to x5 or x10 where the added reconstruction error is likely *smaller* than the residual error in transient response. (1)Anti-alias filters are typically not used but equalization to preserve linear phase is. At lower frequencies, say 200 MHz and lower, nothing special is required except linear phase response in the passband which is easy enough. At higher frequencies, increasingly complex equalization and circuit topologies are required to get the needed Ft out of each stage and provide a linear phase response which results in a multi-pole response and faster roll-off.(1) In my experience, the error in unnoticeable under the most demanding conditions in 100 MHz instruments operating at 1 GS/s which was typically provided almost 30 years ago through ETS. That would be about 15 dB of attenuation at the Nyquist frequency.

author: rhb
author_rank: Super Contributor
timestamp: April 22, 2019, 11:15:19 pm
content: I'm sorry, but I've been doing oil industry DSP since 1982. We were doing DSP long before anyone else. Enders Robinson hand digitized seismic data in 1952. He then went on to apply the first Wiener prediction error aka deconvolution aka FIR filter with a desk calculator. If what you are saying is accurate, then the EEs responsible should be shot and dumped in a ditch. Preferably before they reproduce.Anti-alias filters are an absolute requirement no matter what the sample rate. Harry Nyquist of Bell Labs published a paper on the aliasing issue in 1928. Nyquist was no slouch. Some patent attorneys at Bell Labs commissioned a study to determine why certain scientists had more patents than others. The common factor? They regularly had breakfast or lunch with Nyquist in the company cafeteria (Sedra & Smith, "Microelectronics Circuits" 7th ed, p 875 citing "The Idea Factory" by Jon Gertner).There is no way you can guarantee that you do not have unexpected noise above Nyquist. Any decent intro to DSP discusses aliasing in the first chapter. ETS works *if and only if* the signal is band limited. Shannon is responsible for that result.I have yet to see *any* DSO with a Gaussian or Bessel step response. The Keysight MSOX3104T and the R&S RTM3104 certainly do not have them. R&S makes a claim to have them but the RTM3K does not. I had thought that for $20K I could buy one. I now know better. That's why I'm going to the ridiculous level of time and expense to develop FOSS DSO FW. I'm not happy and I am so unhappy I intend to do something about it.

author: Mechatrommer
author_rank: Super Contributor
timestamp: April 22, 2019, 11:55:43 pm
content: Quote from: rhb on April 22, 2019, 11:15:19 pmwell it looks like you have to wait for another decade(s) until the processing power catches up to speed up your 20 minutes mathematical calculation. or you can device parallel computation for it for FPGA/DSP implementation, or embed it in somesort of genetic algorithm, or... derive simplified formulation for it for practical application in single cored cpu level, much like how people derived FFT from DFT from real FT, or much like how the expert group came up with their jpeg standard from complex wavelet formulation. either way will require pHD grade study and time to do.i dont have detail knowledge about this stuffs, i myself can get easily pale pale when looking at the math esp when there is SET formulation, but i do enjoy reading those at surface level. but the way i see it, compressive sensing is not much difference from other compression method be it lossy or lossless, everything have their trade off, computation power in this case. since it manipulates (or "assumes") thesparcityof a signal, it is possible imho to capture from a full BW data and remove any noise (higher spectral) elements from the recorded data, much like how jpeg is created from raw 8 bit data of bitmaps. ie when reconstructed back, those will be loss (lossy) or will need heavier computation to regain whats left behind (higher elements, little loss). but be aware even lossless jpeg cant compress as much as lossy one, for densed data (matrix) it might not even possible (negative effect or inverse/larger size) for the compression to be applied at all, but then, by some "assumption" about the signal, any unecessary information (noise or higher BW signal) maybe ruled out (lossy), there is no free lunch however, ymmv.

author: rhb
author_rank: Super Contributor
timestamp: April 23, 2019, 01:25:38 am
content: TANSTAFLIt should be noted that algorithmic developments generally outperform hardware improvements.If you need to recover a long single shot waveform with a BW of 1 THZ, just on sheer data volume, compressive sensing becomes important enough to endure the processing delay.Compressive sensing is inherently lossy. It is expecting a certain level of uncorrelated noise. That is rejected because it is not coherent from sample to sample. However, there are a *lot* of variations depending upon your data and objectives.So far as I'm concerned, the work of Donoho and Candes is the greatest advance in applied mathematics since Wiener and Shannon. That may not mean much unless you spent your entire professional career applying the work of Wiener and Shannon. But it's a *really* big deal to me.

author: David Hess
author_rank: Super Contributor
timestamp: April 23, 2019, 02:15:24 am
content: Quote from: rhb on April 22, 2019, 11:15:19 pmThe requirements for seismology are not the requirements for general purpose time domain instruments.QuoteSampling instruments lack anti-alias filters. They even generally lack amplifiers before the sampling stage because they would compromise the passband and transition band response. Most instruments intended for use in the time domain lack anti-alias filters; they just get in the way.QuoteThere is an interesting observation to make about that. For reasons I do not understand, modern DSOs tend to implement bandwidth limiting early in the signal chain instead of after the variable gain amplifier. I wonder if aliased noise contributes to their high noise levels?QuoteThat is only true if triggering occurs after digitization. Modern DSOs which lack analog triggering effectively lack ETS. (1) They mostly make up for it with high real time sample rates.QuoteOlder Keysight instruments had a Gaussian or Bessel step response. There is a discussion thread here somewhere where people measured and reported the amplitude response of their DSOs and I think every one was a Gaussian or Bessel response. The admittedly old DSOs I have all have a Gaussian response unless bandwidth limiting is engaged in which case it becomes a single pole Bessel response or somewhere in between.Older and modern higher frequency oscilloscopes and DSOs often have a maximally flat response but this is simply because a Gaussian or Bessel response is not practical and it has advantages in the applications they are more likely to be used for or at least that is what Keysight argues. Modern instrument correct this frequency and phase response in the digital domain but I wonder when that started.The only example I know of where high order filter was used in a DSO is an odd example from Tektronix. Their last differential comparator was 150 MHz and included 4 pole 100 MHz and 20 MHz bandwidth filters. I suspect now that this was done for noise reduction purposes because the design of a differential comparator gives it almost 10 times the noise of a comparable singled ended input. The preceding instrument may have had a 2 pole 5 MHz bandwidth filter for the same reason.(1) There are at least two ways, centroid timing and transition midpoint timing, to implement triggering in the digital domain without that limitation however both still involve a comparison in the analog domain. I think some frequency counters use this method for very high measurement rates. I suspect some high end DSOs which support ETS and the fastest waveform acquisition rates may do it.

author: Scrts
author_rank: Frequent Contributor
timestamp: April 23, 2019, 02:49:16 am
content: Just FYI:https://twitter.com/azonenbergcheck his FREESAMPLE and glscopeclient.

author: rhb
author_rank: Super Contributor
timestamp: April 23, 2019, 02:09:24 pm
content: Quote from: David Hess on April 23, 2019, 02:15:24 amQuite correct, seismic is *much* more demanding. Not only must the signal be sampled adequately in time, it must also be sampled adequately in space. The acquisition is 32 bit floating point and the contract specifications are many pages and specify everything short of the phase of the moon. A single marine survey costs upwards of $10 million to acquire and possibly as much to process. For time lapse (4D) work, the new survey is required to place the receivers and sources within a meter or two of the previous shoot. Typical spacing inline is 6.25 m. Crossline is larger to keep the streamers from getting tangled up. The boats tow 6 or more streamers.The waveform fidelity of the best DSO on the market today would not have met seismic requirements 40 years ago.QuoteIndeed. However, sampling scopes are *very* limited in what they can do. But what they can do is very cool. I just bought an SD-32 head yesterday.QuoteHow could that happen? It suppresses the aliasable signal before it is amplified. Are the variable gain amplifiers that noisy? I'd expect that the OEMs are relying on the GBW product of the amplifier for part of the anti-alias filtering roll off.QuoteI am relying on Shannon's analysis in my statement. The EE community has clearly abused Shannon quite a bit more than I would ever dare.I don't agree with you assertion about triggering for ETS after the ADC, but I'll defer that discussion until I start implementing the DSP chain on the FPGA.QuoteI'd like to see the step responses from a reliable fast edge.My expectations of scope step responses are based on the Tek 465 generation. When I observed a 7% overshoot and 430 ps rise time on the MSOX3104T I went to read the datasheet. Keysight calculated rise time for the lower end models of the MSOX3K as 0.35/BW, but for the 1 GHz model it was 0.45/BW. I was horrified. That is sleazy marketing.

author: David Hess
author_rank: Super Contributor
timestamp: April 24, 2019, 06:44:41 pm
content: Quote from: rhb on April 23, 2019, 02:09:24 pmThe amplifiers are not that well controlled and the bandwidth limiting tends to be very early in the signal chain now at least on the instruments I have seen details for. Noise from the full bandwidth of the earlier stages after bandwidth limiting is present and aliases into the measurement.This might explain why some old DSOs have much lower displayed noise than modern "low noise" instruments despite lacking index graded displays.Maybe this is done deliberately to support high resolution mode. Applying a clean ramp to the input of those old DSOs and using averaging will clearly display the differential non-linearity of the ADC because the noise is so low. Not only can you see the ADC steps, but they are close to a textbook example when averaging from 8 to 16 bits should result in a smooth line. As you might expect, in sample mode and no input, adjusting the offset/position control clearly shows peak-to-peak noise barely greater than 1 bit.QuoteI could make that measurement but only on an old DSO (because that is all I have at the moment) and it would show the exact response that a 465 would show. I just do not have anything newer for lack of a need and I am as disappointed with modern DSOs as apparently you are. After doing some evaluations, I decided that a 20+ year old DSO was better.QuoteMine are also and a Tektronix 2232 delivers exactly that. So did the 100 MHz Rigol DSOs when I tested them just before the DS1000Z series came out. (1)The results of your 1 GHz Keysight DSO are exactly what I would expect from a maximally flat design which is common somewhere above 500 MHz simply because a single pole roll-off or Gaussian response is not practical. I gather than this bothered enough people that Keysight and Tektronix released application notes discussing it and why it is not a disadvantage.Older high bandwidth analog oscilloscopes faced this problem as well and in at least one case, the Tektronix 7704A, the instrument was available with a 200 MHz Guassian response or 250 MHz maximally flat response althoughthe 250 MHz response looks pretty good to me(bottom of page).(1) Knowing what I know now about Rigol's design practices, my testing would include bandwidth and rise time measurements at different signal levels but I am not used to carrying a set of RF attenuators with me.