Can you have too much GND? - Page 1
Forum section: electronics / beginners

author: Saimoun
author_rank: Frequent Contributor
timestamp: June 21, 2022, 02:22:34 pm
content: HiThis thought came to me after watching one of Phil's videos:And I thought - yes you probably do not *need* any GND on top and bottom layers since you have the innerlayers right 0.2mm next to it.Though, is there any reason why you would *not* have a GND plane somewhere? I heard stories like if you have a bit of your ground plane that is only connected to one end it could act like an antenna and pick up noise, which could then spread to the rest of the GND of the circuit.Other than that I cannot see any reason why not having a GND plane everywhere. Even manufacturing-wise since the copper is etched away, leaving the GND plane just means less etchingWhat do you guys think?CheersSimonPS: the real question is, can you get high on GND? ... sorry I had to say it

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 21, 2022, 03:05:38 pm
content: It makes little difference because the coupling between surface traces is small, ca. 10% at minimum width/space. So, trace impedance is reduced by about this amount for surrounding ground pour (coplanar waveguide with ground), and likewise for radiation (effectively somewhat less cross section exposed on the PCB face). Less for wider of course, so, a given trace doesn't couple much into the GND (which is irrelevant anyway with via fence shorting out what coupling may occur, i.e., coupling into top GND with respect to inner plane GND), but GND couples into the trace by about this much hence the impedance reduction.Meanwhile, it's a big pain managing all the positions of components (top and bottom, even) and via stitching, so it's little advantage for a lot of work. It may be worthwhile when every little bit counts, like for precision RF circuits.For EMI purposes, the components standing proud of the PCB surface plane means you're only getting a couple dB this way, anyway; those still need to be shielded (assuming they're carrying signals similar to the traces in question, so that this is relevant, of course), hence when RF needs it, it's going to go with a shield can anyway.You could gain more EMI advantage by shifting most traces to inner layers (stripline), but this really kinda needs 6 layers so you can have contiguous GNDs with stitching, to fill in the negative space left by component pads and vias in the outer GND pours. And it costs more vias, and maybe you'd prefer blind vias to save on routing space between all the numerous signal and stitching vias; so, still more costs depending on how dense you need it, and bandwidth and shielding requirements.Tim

author: Saimoun
author_rank: Frequent Contributor
timestamp: June 22, 2022, 05:52:53 am
content: Thanks for the reply Tim.Makes sense about the 10%, because the surface exposed is so small (basically the "trace height" of 1-2oz).Quote from: T3sl4co1l on June 21, 2022, 03:05:38 pmWhat do you mean? For Phil's design I just thought taking the current design, and making a GND pour on top and bottom layer. That takes 5 seconds at most?(there are already vias stitching his two internal GND planes which will stich the ones on the top and bottom - maybe one can spend 5 minutes adding a few more).But if I summarize your answer to my question (which was "is there any reasons not to have a GND plane"):* it can be a lot of work for very little effect (especially for 4-layer design with inner GND pane already)* but no other reason (i.e. nothing "bad" will ever happen from too much GND)can you confirm?And what about for a 2-layer design?Thanks!Simon

author: Berni
author_rank: Super Contributor
timestamp: June 22, 2022, 06:02:00 am
content: Filling everything with a ground fill is good for high speed.Where it might be a bad idea is when you are concerned about parasitic capacitance or picoamp leakages in sensitive analog circuits.However engineering is rarely so black and white. While having a ground fill everywhere is good, it has to also be connected somewhere. This means placing vias to ground those surface islands of ground fill. For good low impedance RF connection just one via is not going to cut it. Doing that will indeed create a antenna with a center frequency dependent on the shape of your fill patch. You need to actually peeper these fills with vias all over to give it a good connection back to the internal ground plane and make sure no long stub on a fill turns into a LC tank circuit. Doing this turns the power plane inside into swiss cheese even more (this plane is also critical for high speed)So while ground filling ALL THE THINGS (insert meme here) is not a bad idea, it does bring some tradeoffs.For 2 layer designs you have nowhere else to put the ground fill so you do often see it done there.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 22, 2022, 11:16:57 am
content: Quote from: simonlasnier on June 22, 2022, 05:52:53 amAh, but will the stitches be random compared to the added ground fills? Will they happen to capture inside corners (peninsulas), long spans, islands? Stitching inner copper is easy, nothing's routed there (assuming, anyway; haven't watched the video, if you have some highlights to check out?). Which, is an odd thing to do for 4 layers, but I'm guessing he chose to route power because it's just a connector board?Remember the coupling. By adding copper, you're under some obligation to pin it down as well, lest you make resonators that couple to traces, and then modify the signal quality and EMC of the design.Say you have two traces running between two connectors opposed on the board, left to right say. They're parallel, separated by pin pitch say 0.1", and you pour ground over them. Ground fills inbetween, and connects around the pads -- there's plenty of space between the pads to connect back to the bulk of the GND. But you're left with this extra-wide trace of GND, between the two traces. At low frequencies, that's fine, good even as it shunts E-field, reducing capacitive coupling between traces. (Which might be useful for a 2-layer board, and might be negligible for 4-layer because the trace separation is many times the height above inner plane.)At high frequencies, on par with the length of the traces, however, you get, well, whatever impedance is connected at either end, and transmission line lengths spanning the middle. Which are coupled loosely to a third lower-Z TL inbetween. If the connectors are terminated, then we don't need to worry about SWR on the traces and the only interesting part will be resonance of the GND trace, which will be a 1/2 wave (shorted both ends) stub. Or folded dipole if you like. And being that it's relatively wide, it should have relatively strong coupling to radiation. And being that it's edge coupled, it should have a fairly high Q, i.e. gently driven by the surrounding traces. So if one of those traces is excited with, let's say this board is 4" wide so the 1/2 wave mode is resonant around 1.05GHz -- there's still more considerations to go into this, but it may indeed happen that there's a tall, narrow peak in emissions around this frequency, or it fails susceptibility around this frequency. This also causes a notch to the frequency response along a given trace, and a peak to the coupling between traces -- the high Q of the 1/2 wave stub resonator allows it to couple much more strongly, near resonance, into those traces.Whereas with stitching vias, this errant GND trace can be stuck down until, say, 20GHz+ which shouldn't be relevant at all to a circuit made on FR4.Maybe this isn't the greatest example, because most people don't run high-speed digital comms over 0.1" headers, and even when they do, they don't separate the traces to allow GND to fill between them (e.g. LVDS pairs). (And even then, a trace between a differential pair sees only common mode, which should be small from such sources.) But for illustration purposes, any island, peninsula, isthmus, trace -- can have some impedance at high frequencies, affecting signal quality somewhat, or at worst, becoming an antenna at some resonant frequency. Those frequencies will usually be high enough you won't excite them with say CMOS logic signals, but various kinds of LVDS are expected to run that fast. (And notice that differential trace pairs aren't twisted; they couple asymmetrically into whatever's beside them. So an LVDS pair routed beside a poorly-pinned GND structure can trigger such behavior. Granted it's even weaker, it's only coupling into half the differential pair -- the nearest trace -- but that's still something.)So that's why I don't like to pour GND indiscriminately: it takes time to stitch, while giving very little improvement.And keep in mind the knock-on costs as well: it's one thing to pour and stitch an existing design. You might not spot all the points of interest (inside corners etc.), but you can do a pretty good job of it. Now change the design, move around a bunch of components and traces. Will you remember to inspect all the changed areas? As traces cut and reroute, the pour's topology changes; you may need* to remove redundant vias, and add more in somewhat unexpected areas. Basically, you're spending a lot of time, AGAIN, verifying the stitching, after already doing it once. And again and again as revs accumulate.*"Need" in the sense of keeping it consistent. There's very little actual cost of extra vias stitching across a 3-layer-GND situation like this, but do mind they still cause voids in the VCC plane. And I suppose maybe you'll save a few millicents in production, but unless you're getting really carried away I don't think they really care on a proto basis.QuoteFor 2-layer boards, it is the ONLY way to get a plane. So it is, for almost all intents and purposes, mandatory!Consider this rule of thumb: you want about half the layers dedicated to planes.On 4-layer, with SMT components filling one or both sides, routing naturally is drawn to those layers. Great. (Also, maybe you could do bottom plane with top-only placement, but then the copper density would be unbalanced, which may cause warpage.) So, inner planes are a natural fit, and good symmetry, and there's two of them so you can do GND and VCC and save a lot of routing trouble as well as get good grounding and supply impedance.And so on for higher layers. Like for 6, maybe you're still fine with the two planes, and just want to add two layers of routing, sandwiched neatly between planes, well shielded. Or do the no-outer-routing design, all connections by vias to inner layers. That should be enough to do the job pretty easily. And there's not really a balanced way to do 3 planes over 6 layers, and 4 would be too many (but, again, you can pour and stitch outer copper if you like, and if you have the room to stitch it). For multiples of 4, half and half planes and signals works out well. And of those planes, probably about half should be GND, and the rest can be VCCs.But what do you do for fewer layers? If you're doing single side placement, you can place top, pour bottom, and use a minimum of routing on the bottom -- only just enough to cross traces over where needed. Copper density won't match real well though. So you might fill the top with GND pour after all, and stitch it, and while that's going on, you save some GND routing which is nice I guess. You have no room for pouring VCC -- it must be routed.Then, say layer you need to move some components to the bottom side, or add more and you're out of space on top. Well, if you can find some blank area to place them -- sure. Now you have no choice but to slice up the bottom pour, and the design starts to look symmetrical, in that top and bottom GNDs both have a lot of voids. As long as those voids don't overlap (there's always GND above or below a component or trace), and where they are, they are small and the perimeter is kept minimal and well stitched (i.e.: trace intersections must void through both GNDs, so stitch around the intersection with at least 3 vias to keep the resulting thru-void minimal), you'll still have good grounding (as good as can be had in this format, anyway).Basically what ends up happening is, because there's GND top and bottom, but partial, but supporting each other, it's like creating one average plane in the middle of the board. So you've effectively achieved your "half layers GND" quota, while routing/placing on both sides.Mind, you don't actually get very much density from both sided placement, on a 2-layer board: you require GND pour under/over every component and trace/bus, so components tend to alternate sides, and buses tend to swirl around them, connecting radially and avoiding tangentially around any given area. (If you can manage a coherent directional bias over the whole design, that's fine -- i.e. top vertical, bottom horizontal. Which is also easy to tell the autorouter to do, and that's an easy way to get a starting route to clean up. What you'll tend to find, in more optimized layouts, is a swirl of traces around major components, as many connections come into them, and others must circle around. There's a certain intersecting-complementary-field-lines quality to it, or a sort of van Gogh style if you like.) You need probably about the same board area dedicated to routing as component footprints themselves. And that sounds suspiciously like the case for single-side placement, so indeed you don't usually gain much from two-sided placement on 2-layer designs. That said, small/incidental components like termination/bias resistors, bypass caps, etc. can be gainfully placed on the bottom, under respective (larger) components, saving top-side placement and routing area while having very little impact on bottom-side GND fill.As example, here's a render of one of my densest 2-layer builds:Schematic:https://www.seventransistorlabs.com/Images/LimitingFuseSch.pngAs you can see, it's mostly top-side placement and routing, and mostly works out pretty well, except for the tangle of bottom routing beside the STOP button / under Q6 area. And you can see, well, they're hard to see with tenting, but, there's plenty of via stitching still -- in strategic areas only, no room for a stitching grid -- near GND pads, inside corners, high current paths, and there's even room for a thermal pour under the power transistor.Tim

author: Saimoun
author_rank: Frequent Contributor
timestamp: June 22, 2022, 12:53:10 pm
content: Thank you Berni, yes that makes sense@Tim: it's funny when I started writing here I used to understand about 50% of your answers. I can literally measure my improvements as I understand more and more - I am definitely at a good 90% now!!Thanks again for the long and detailed answer - which surely will also help others at some pointAnd thanks for sharing the pictures and the schematic!Makes sense about what you said with a GND pour between two traces. Also matches with what Berni is saying.Quote from: T3sl4co1l on June 22, 2022, 11:16:57 amYea my bad for saying it was no work, when I myself literally spend a lot of time checking every single stitching via at every revisionThough I think my OCD also make it way longer than it should beAnd as for a 2-layer design, what I tend to do is try not to cut the pour on a very "long" line if I can? For example I recently realized that if you have 2 traces (different nets) joining each other like a T, and a via in the middle, just moving that via a little bit (which most of the time is possible) will be enough for the GND not to be cut between the two traces. See the attached example.Also very interesting to see where and how many stitching vias you put - I probably tend to go overboard and put tons everywhere. For my low-speed board which is probably not a necessity anyways

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 22, 2022, 04:00:05 pm
content: You're welcome, I appreciate it.For an intersection like that, two is probably fine -- notice the red copper wraps around the via nearby, so there's a short loop between the two bottom vias, and the blue copper is shorted across in the gap between via and horizontal trace. I'd be fine with two vias here. The top via is almost certainly redundant, but of course it isn't hurting anything being there.Tim

author: Terry Bites
author_rank: Super Contributor
timestamp: June 22, 2022, 04:28:13 pm
content: Keep as much as you can without compromising performance. All that etched copper is toxic waste that polutes the planet.Dont just chuck it down the drain folks.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 22, 2022, 04:56:19 pm
content: Etchant is recycled you know..? Who flushes industrial quantities of valuable metals...Tim