Divide by 2 with D-type Flip-Flop - Page 1
Forum section: electronics / beginners

author: Loz Collins
author_rank: Newbie
timestamp: April 06, 2025, 11:59:08 am
content: Hi All,Looking to use a D-type Flip-Flop to divide a clock output pin by 2, not sure though what specs are needed, and the parametric search on the mouser/digikeys give hundreds of matches.The clock we are trying to divide is a single pin with 40, 42, and 44 MHz outputs, 3.3V square wave. The output required is exactly half the frequency at the same amplitude, i.e. 20, 21, and 22 MHz square wave with low of 0V and high of 3.3V. The frequency of the input signal changes with the mode of the product selected, and the required new signal is always half the frequency of the input. Load current (output of the divide by 2 component) will be maybe 50mA.The circuit needs to be small so looking for a single gate component that is hand solderable on a small run PCB, a 5 or 6 pin SOT23 would be ideal.The specs on the mouser/digikey listings show nS, not MHz, what rating would be needed for it to work reliably at out highest frequency of 44 MHz in / 22 MHz out?Thanks to anyone that can help. OK with the tech stuff - I'm a sparky who dabbles in electronics - but at a lower frequency, we normally top out at 50Hz but go to 100KW and beyond .

author: m k
author_rank: Super Contributor
timestamp: April 06, 2025, 12:29:33 pm
content: I'm sure those texts have more info than just ns and a number.What that info is?Possible times are at least rise time and propagation delay.

author: themadhippy
author_rank: Super Contributor
timestamp: April 06, 2025, 12:41:10 pm
content: QuoteA simple sum converts between the two, (1/frequency in hertz =time in seconds ) the awkward bit is getting all the zeros in the right palace

author: tggzzz
author_rank: Super Contributor
timestamp: April 06, 2025, 12:42:32 pm
content: It is "ns" not "nS", i.e. seconds not Siemens/mhos.You connect the Qbar output to the D input, or put an inverter between the Q output and D input.The maximum clock frequency is determined by the maximum Ck->Qbar (or Ck->Q+inverter) propagation delays plus the D input setup time.The amplitude is defined by the Vcc and the logic family.50mA is a relatively high load which will require buffers. Those are unlikely to influence the maximum frequency, but will increase the propagation delay between Ck and that output.

author: RoGeorge
author_rank: Super Contributor
timestamp: April 06, 2025, 12:44:02 pm
content: Read the datasheet of the ones you selected. You should find MHz in the datasheet. Any fast enough D type FF should do it. I would look for the AHC type.From memory, I think a 74AHC74 would cover it. Usually comes with 2 FF in the same chip, might be a version of single FF per IC, but I didn't search. Double check the max clock frequency with the datasheet of the exact part you want to order.

author: Peabody
author_rank: Super Contributor
timestamp: April 06, 2025, 02:19:28 pm
content: If it's not a State secret, can you say what kind of circuit needs 15mA at 44MHz?

author: BillyO
author_rank: Super Contributor
timestamp: April 06, 2025, 03:17:44 pm
content: Quote from: Loz Collins on April 06, 2025, 11:59:08 amWow, that is quite a lot. What is the load?

author: TimFox
author_rank: Super Contributor
timestamp: April 06, 2025, 04:26:56 pm
content: The first such device that appears on a Google search, SN74LVC1G79 :https://www.ti.com/lit/ds/symlink/sn74lvc1g79.pdf?HQS=dis-dk-null-digikeymode-dsf-pf-null-wwe&ts=1743956601678&ref_url=https%253A%252F%252Fwww.ti.com%252Fgeneral%252Fdocs%252Fsuppproductinfo.tsp%253FdistId%253D10%2526gotoUrl%253Dhttps%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74lvc1g79On page 6, sections 6.6 and 6.7, at Vcc = 3.3 V, the maximum frequency is 160 MHz.That device only has Q output, but I didn't search farther.

author: tggzzz
author_rank: Super Contributor
timestamp: April 06, 2025, 05:11:08 pm
content: Quote from: TimFox on April 06, 2025, 04:26:56 pmPropagation delay 4ns, setup time 1.3ns, need an external inverter (e.g. 74lvc1g04) 3.3ns for 15pF load. Hence minimum period is 4+1.3+3.3=8.6ns, or ~115MHz. Use other gates to drive the load!

author: PGPG
author_rank: Frequent Contributor
timestamp: April 06, 2025, 08:14:02 pm
content: Quote from: TimFox on April 06, 2025, 04:26:56 pmLVC1G80 has not Q output.

author: TimFox
author_rank: Super Contributor
timestamp: April 06, 2025, 08:21:58 pm
content: Similar specs, with only Not-Q output, for max frequency = 160 MHz.At 3.3 V, maximum output current is 24 mA.