Schematic review and thoughts on power up state - Page 1
Forum section: electronics / general

author: paulca
author_rank: Super Contributor
timestamp: July 15, 2025, 09:31:38 am
content: Its the address logic for a simple Z80 CPU board ( CPU, RAM, ROM, CLK, address logic and an IO header )The full schematic is attached as PDF if you need it. Most of it is based on a working "V1" example with fixed memory mapping. So while it does show the odd, 1 in 20 "false boot" do doesn't have perfect power on behaviour either, this one presents more challenges with the dynamic address logic.Address logic:The lower 16k of memory is pagable. Using 3 dynamic address bits and ROM/RAM select bit, a 4 bit config word is used to page any of the 16 possible 16k memory pages in place of that 0x0000-0x4000 block. Including duplicates.The upper 48k is mapped directly to RAM at the same physical address.The challenge is having something consistent in the "PAGE_REG" config word at power on. There can be no software support here. It has to exploit or hide from the logic oscilations until it settles, using whatever it can find which is stable.So I tried to fiddle with RC circuits, negative pulse generators and while some of them might work, I chose to get heavy handed and installed a full "init" register, tied directly to the only signal on the board that is stable at power on. RESET.RESET is held low by an RC circuit for long enough for the board to reach steady state AND have the Z80 clock running for a 100 cycles or so. Only then does RESET rise to a HIGH and release the board.So it doesn't matter how much garbage "PAGE_REG" loads or in fact how many times the flip flop bounces. It will be in a "RESET LOW" state just before RESET HIGH, and the PAGE_REG_SELECT will be at a known HIGH at that point.This is intented to protect that INIT_PAGE_REG being active until software intervenes with a write to PAGE_REG causing the OE's to swap. And remain swapped until RESET.Anyone spot any other obvious blunders that I haven't yet?The challenge honestly is testing it on breadboards will be a challenge. Just the address logic mind. I have a PCB for teh rest of the core I can "borrow".

author: paulca
author_rank: Super Contributor
timestamp: July 15, 2025, 09:39:47 am
content: I usually delete and redo layouts 2 or 3 times before settling.For laugh, here's the first.... and no, there is nowhere for the decoupling caps to go!

author: asmi
author_rank: Super Contributor
timestamp: July 21, 2025, 03:51:59 pm
content: Quote from: paulca on July 15, 2025, 09:39:47 amI see a ton of space for decoupling caps on the bottom side underneath devices.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: July 21, 2025, 03:57:22 pm
content: I forgot my Z80 stuff over the years, but I do know some KiCad...You made a list with connecting local to global labels in the upper left corner, and this is not really needed. In KiCad, if a global label is mentioned on the same page as a local label (with the same name) then they merge into the same net. Therefore, just making a column with the global labels is enough. This saves you both some work and paper space.

author: paulca
author_rank: Super Contributor
timestamp: July 21, 2025, 08:22:45 pm
content: Quote from: asmi on July 21, 2025, 03:51:59 pmDark side. Of course!Quote from: Doctorandus_P on July 21, 2025, 03:57:22 pmYea I fought a bit with it and hierarchical sheets and just stopped when it started working. So there is probably unnecessary bits.

author: paulca
author_rank: Super Contributor
timestamp: July 21, 2025, 08:24:54 pm
content: I'm not entirely sure I want to suffer testing and debugging this. I think it might stretch beyond "fun".What might be more fun is to use a CPLD instead. And as it's hobby I can just through a big old 48QFN FPGA in there and not have a mux about with 74 logicmux about... that's bad. Even for me.