Young player - Ground fill question - Page 1
Forum section: electronics / general

author: UHF
author_rank: Contributor
timestamp: February 06, 2020, 10:12:10 am
content: Hello, I have a double-sided pcb with signal traces on both sides, a mixture of digital and analogue. I've got it routed, do I put a ground fill on just one side, both or ground on one side and 3V3 on the other (for fun?!) I'm a 'young player' (48 actually...) and it's my first pcb.Many thanks.

author: fcb
author_rank: Super Contributor
timestamp: February 06, 2020, 10:33:04 am
content: I put ground fill on both sides and then staple them together with via’s. There are exceptions of course, but generally this strategy works for me.

author: UHF
author_rank: Contributor
timestamp: February 06, 2020, 10:42:04 am
content: Ok, thanks very much.

author: Howardlong
author_rank: Super Contributor
timestamp: February 06, 2020, 10:53:08 am
content: Quote from: fcb on February 06, 2020, 10:33:04 amIMHO good rule of thumb advice, this alone will save you from a few return trips to the EMC house. My other rules of thumb are: physically segregate your board between analogue signal areas and digital signal areas, especially high speed digital signals and those with fast edges. Use ~33 ohm damping resistors on digital line outputs.Using flood fill is also more environmentally friendly!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 06, 2020, 01:27:09 pm
content: Filling with GND and VDD sounds good at first, but the problem is you have slots and gaps between regions of those conductors.You can very easily route at DC this way, and that's fine. But, real, interesting circuits are not just DC.The problem arises when you have AC currents drawn between those gaps and regions. They act like inductors and capacitors, and you get all sorts of radio frequency noise inside the circuit, and outside it too (emissions). And susceptible the other way, like, such a circuit might be particularly vulnerable to ESD because you don't know which path the ESD current will be shunted through. It may just find a sneak path through a chip!So the better way overall, is to pour one net on both sides, and solve the gaps by stitching with vias. Typically, vias are placed near crossing traces, on peninsulas and islands, and periodically along boundaries. If you aren't doing precision or RF work, the spacing doesn't need to be very close -- an inch or two will suffice. Concentrate on features more than general density.Try to have ground poured on at least one side, over as much of the board area as possible. Anywhere traces overlap or cross, there's a hole in both pours. Obviously, don't run traces in parallel on both layers, at least for very much distance. Prefer to group long runs into buses on one layer.Vias are cheap, don't be afraid to use them!If you are doing precision RF work, you'll often employ via fences around relevant traces. The spacing is driven by the amount of error at a given frequency, so of course, if the error must be smaller, or the frequency goes higher, the spacing goes down.For the generalization, figure on about half the layers, in a multilayer board, being dedicated to supplies connected with large pours.Typical 4-layer stackup, the middle two are GND and VDD.On 2-layer, you effectively create one average layer of GND by stitching pieces of both layers together, and this performs basically just as good as a 4-layer board of the same density. (You can just place things closer together on 4L because you aren't wasting space on ground fill and trace routing.)6 layers, you could have three planes, but symmetry is preferred (unbalanced copper areas can warp the board) so it's often used as "4 layer plus", more routing layers offering easier routing or better signal quality.8 layers, you can have for example 2 x GND, VDD_IO and VDD_PERIPH say. Which might be, like, an FPGA routing to memory on one supply, also routing say PCIe lanes on the other supply, in the same place so you can't just stitch one supply around the other.This and up, is probably well outside your scope, but you get the idea. Prioritize supplies by region, usage and requirement (local, lots of VDD pin count, low noise, high current?), and trace-route whatever's left.So of course on 2-layer, following this scheme, VDD has to be hand routed, and you should prefer more bypass caps as a result -- because again, trace length is inductance, so you don't want to have too much between components, and you also don't want too much length between bypass caps, because they can resonate with each other as well. More generally, there's PDN (power distribution network) analysis, a topic unto itself, but a simple takeaway is, it's better to have bypass caps more or less regularly spaced, than to have long naked trace lengths with big caps at the end. Point-to-point routing can be better than star routing a supply. (But hey, it depends, widely. You can SPICE it, if nothing else!)Tim

author: UHF
author_rank: Contributor
timestamp: February 07, 2020, 03:29:01 am
content: Thanks very much, some very useful discourse for everyone. My pcb has USB, a load of pots (32) going into a couple of 4067 Muxs, an SPI display, audio out, plus MIDI. The USB is near the edge of the board and goes into a MCU. Noise going into the MUXs and then the MCU is probably the biggest concern but it gets turned into a 7-bit value. I think it'll be ok. The next question I'll have will be about the capacitive touch buttons on the front panel pcb, but I'll save that for later. Thanks again.

author: Howardlong
author_rank: Super Contributor
timestamp: February 07, 2020, 08:27:51 am
content: Quote from: UHF on February 07, 2020, 03:29:01 amMake sure you have enough ESD protection on your USB port, and properly couple the USB shield: the shield should not go directly to device GND. Typically I use a 4.7nF in parallel with a 1Mohm from the shield to device ground.

author: fcb
author_rank: Super Contributor
timestamp: February 07, 2020, 09:23:47 am
content: Depending on the pot values (10K might be OK) and the speed at which you are scanning the 4067, you might want to put a buffer opamp (mcp6001 or similar) on the mux output of each of the 4067s.If you are scanning quickly, you’ll see a noticeable ‘dip’ when the microcontroller adc samples the pot when you get to the mid values, especially if a the previously sampled pot was at one end of its travel.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 07, 2020, 02:05:35 pm
content: Quote from: Howardlong on February 07, 2020, 08:27:51 amThen to where should it go?The puny cap doesn't do shit.This is generally bad, in fact the worst possible advice, FYI. It's a possibility when there is a metal enclosure that can be used as a quiet primary ground. I see it way too often applied in situations where it's just flat out wrong.FWIW, the USB docs themselves -- which are open and public -- discuss several EMC situations, and best practices for them. I believe the history of this "advice" is one of those cases, that has been repeated and distorted far too often by appnotes and amateurs alike, having lost all reference to what case it actually applies to.Tim

author: nctnico
author_rank: Super Contributor
timestamp: February 07, 2020, 06:42:45 pm
content: Quote from: T3sl4co1l on February 07, 2020, 02:05:35 pmI agree. Have all shields connected to a common ground which should also be the device ground. IMHO the biggest trick is to make sure to not have HF currents flowing through the ground which means you need to filter the power supply of the USB device so all the HF current is contained within the device. Filtering at the host side helps too ofcourse.Last year I had to EMC-debug a board which had a seperate ground for the ethernet section. What a nightmare... Getting everything connected to a single plane including the RJ45 shield solved most of the emissions.

author: fcb
author_rank: Super Contributor
timestamp: February 08, 2020, 06:16:46 pm
content: Understanding loop area is probably the most important single thing w.r.t. EMCI tend to use double-sided ground plane for USB screen and ground, 27R/33pF on data lines and small ferrite bead and cap filter on +VUSB. Also keep any USB IC close to the socket (it helps that I use FTDI parts in most designs rather than the micro's on-board USB).Near field probes are unbelievably useful before hitting the labs.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 09, 2020, 03:11:21 am
content: Quote from: nctnico on February 07, 2020, 06:42:45 pmYes, yes, yes.

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: February 09, 2020, 03:33:39 am
content: There is a dependency on the voltage also. For high voltages (e.g. 110V) , it may be safer not to pour the ground as it can reduce the clearance & creepage distance and cause arcing. For low voltage, low frequency circuits it hardly matters. You could pour ground in the remaining space. Ensure that there are no floating islands.For RF circuits, always a ground plane is needed for the RF traces. Pouring the remaining ground is also tricky as you may want to control the return currents to flow on the ground plane rather than on the remaining poured ground.