PSU PCB layout advise - Page 1
Forum section: electronics / beginners

author: VEGETA
author_rank: Super Contributor
timestamp: October 07, 2025, 06:25:04 pm
content: Hello,I had to use a bigger power module (IRM-30-15) instead of the smaller (IRM-20-15) which made me need a lot more space.Therefore, I now have to use double sided assembly.Top layer is basically the power module itself + CLC filter after it (to clean its output) + some through hole connectors and switches.Bottom layer is where all SMT parts are, which are basically everything else. 4 buck regulators and some misc. parts.I drew a rough drawing for the path of power which all would be routed on bottom layer and I want an advise if it can be better.The power module internal pcb itself is a bit up so it won't have any EMI effect on the board.Green drawing is main power source (power module through clc filter) which goes to the input of all buck regulators. of course it will be a polygon pour and so on but all i need to know if there is a better way.pcb is 4 layers where layers 1, 2, and 3 are all ground pour with layer 4 (bottom) being power routing. many ground vias will be added as well.thanks

author: temperance
author_rank: Super Contributor
timestamp: October 07, 2025, 08:35:03 pm
content: You probably don't need the CLC filter on the input. The IRM modules contain enough filtering, including some ferrite beads on the output.You can remove the bottom cover pretty easy to inspect its internals.Edit: I'm seeing a bunch of ceramic capacitors. Check the capacitance derating of those.

author: VEGETA
author_rank: Super Contributor
timestamp: October 07, 2025, 08:40:53 pm
content: Quote from: temperance on October 07, 2025, 08:35:03 pmwell, i got nice results without the clc filter but still it makes things better. without it i believe it was 150-200mv p-p (a friend measured it) and I remember having a better reading... still CLC here is cheap enough and will make sure the input to the buck regulators is super clean... especially if there are some low freq. ripple caused by the load or so.my main issue in this topic is about the layout and suggested routing. what do you think?

author: temperance
author_rank: Super Contributor
timestamp: October 08, 2025, 08:46:18 am
content: QuoteYou encircled the global currents loops and the PCB is a four layer board. That's fine. But the fine details are in the layout around the buck regulators.

author: Psi
author_rank: Super Contributor
timestamp: October 08, 2025, 08:57:40 am
content: Quote from: temperance on October 07, 2025, 08:35:03 pm+1 to this. Bias voltage / temp changes / tolerance.And make sure the critical caps are documented/flagged so someone in the future can't just swap that part for a cheaper one that has the same voltage/capacitance without considering the full implications.It's easy to end up running without enough input/output capacitance margin without knowing about it.If you're lucky it blows up during the design process and you fix it, if you're unlucky it fails after it's in the field.

author: VEGETA
author_rank: Super Contributor
timestamp: October 08, 2025, 09:33:28 am
content: Quotewell, the current going to one direction then to the other direction is my biggest concern.Having 3 layers of solid ground (especially 2 internals) i guess can make it ok, can you confirm this?anything else I can do?I previously got fantastic result with exactly these components and the layout for the buck... I will redo it again and tailor it to this layout now. switch node is very tiny and short, using copper pours for switching node and output to caps...etc.the previous design i got final output ripple to be < 5mv P-P at full load with no noise spikes. I want to get the same or better this time.Quotethat was all taken care of and tested to be working perfectly fine in the previous prototype.all this new prototype will do is upgrading the power module to 30W for better thermals + the new layout I asked for.looking forward to your advise on the layout.thanks for all

author: VEGETA
author_rank: Super Contributor
timestamp: October 08, 2025, 09:46:38 am
content: I attached a rough drawing of the currents for the 3 buck regulators (the 4th one is going off the board).it does not look that bad, what do you think?The current will all return from the "output connector gnd" pins and will go to the "main gnd" pin.since there are solid ground layers, will it be going smoothly without doing circles?I know since switching frequency is 1.2 MHz, the return current will be directly under the ongoing current itself or as close to that as possible.I plan to put more GND vias in the areas between the buck regulators, will this make it better or worse or no effect? thermals should be good enough with current amount of vias but i am concerned more in making the return ground current path as good as possible.I searched online but could not find a definitive answer to the question about making closely spaced ground stitching vias being good or bad for ground return current. meaning, a solid uninterrupted copper areas of internal ground plains is better than having multiple vias stitching all ground plains together?sorry for long posts

author: temperance
author_rank: Super Contributor
timestamp: October 08, 2025, 09:14:00 pm
content: QuoteI think you are overthinking this. On a 4 layer board, the return path loopareais anyhow small. You also don't need that many vias. The power supply loop area will increase anyhow when you connect this to another board. A spacing of 10 mm between vias to connect planes together spread out over the planes will do fine.With this tool you can calculate via properties such as inductance, resistance, thermal resistance,...https://saturnpcb.com/saturn-pcb-toolkit/Regarding using planes to connect switching nodes: switching node to plane capacitance should be kept small. Unless the traces act as a heat sink, a better solution is to use traces not wider than required.

author: VEGETA
author_rank: Super Contributor
timestamp: October 08, 2025, 10:05:48 pm
content: Quotesmall being the area itself in my board? because it is small.I do have enough vias already as I mentioned, just wanted to know which is the correct or better choice... leave space in ground plains or use dense via areas?Quoteno, i won't use an internal plain to connect switching node. it will be connected using very short traces\pours in the same layer without any vias to anywhere. there will be direct ground plains under it like usual.the pours I use is just to cover the SMT regulator pin and the SMT inductor pad, nothing bigger and no heatsinking required for it.as for saturn pcb tool, i had it before and used it but i feel this question is not related to it. i know it can show me a via has this or that current capability but this is not an issue for me. i want to know if leaving gnd copper area without stitching vias is better or putting vias? i believe via inductance will play a part but will it for example negatively affect return current path? I searched but could not find an answer.

author: temperance
author_rank: Super Contributor
timestamp: October 08, 2025, 11:55:35 pm
content: Plane stitching.A general rule is to space stitching vias at intervals less than λ/10 to λ/20 of the wavelength. Let's say the highest frequency is 20 MHz (it is probably less than that). In free air, the λ is 15 m. On a PCB with a dielectric constant of 4.2, the λ becomes 15 / sqrt(4.2)= 7.3 m; One tenth of that is 73 cm.So the density in this case is not defined by the maximum frequency but how currents return. That is, for high frequencies the patch of the least inductance. That's why calculating via inductance can provide you some insight into what you need.Let's assume the buck regulator GND pin connects to an internal plane with 1 via. Assume the via inductance is about 1.5 nH and the buck regulator switch switches from 0 A to 2 A in 10 ns. From this we can calculate the voltage across the single GND via:du= L x di/dtdu= 1.5 nH x 2 A / 10 nsdu= +/- 300 mVSome of this noise across the via is visible on the output of the buck regulator because the noise couples through the inductor stray capacitance.The remainder of the PCB is just DC. Some via stitching with a spacing of 10 mm will do.Edit:There is an other thing to watch out for. The ceramic capacitor might provide very good decoupling. But in combination with some stray inductance, like wires between the power and the load, your power supply output decouping will form a very high Q LC circuit. So now every time the load demands current, the power output will temporarely oscillate.The cure for such "problems" is to place a low (Read: quality high ESR) capacitor in parallel with the ceramic capacitors. The value of the low quality capacitor must be at least five times larger than ceramic capacitor bank capacitance.

author: VEGETA
author_rank: Super Contributor
timestamp: October 09, 2025, 07:37:43 am
content: Quotehow did you arrive at 20 MHz or is it assumed?my switchers are just 1.2 MHz and one of them (low power one) is 2.1 MHz.so in your example if placing stitching vias at more than 73 cm its going to be a problem?Quotein my previous prototypes I used multiple vias very close to the buck regulator gnd pins and many near and around the inductor... also, many of them very close to output caps ground pads. the final output ripple was < 5mv p-p with and without max load. it worked very cold too.so there i used multiple vias which made total inductance very small?Quotehmm the pcb itself is very tiny so there won't be multiple parts or sections. stitching vias will be close to everything but more focused near ground pads of output caps and so on.Quotethe previously mentioned total noise and ripple figure of just 5mv p-p at full load was measured with using the wiring harness.the wiring harness uses AWG16 thick wires, measured drop voltage is very tiny if any. its length is just 15 cm, will it be a problem? i mean if there is an oscillation it should have affected the output ripple right? but instead i saw totally flat and normal output ripple, very small too.QuoteI know having a big electrolytic capacitor with high ESR can dampen stuff but i used TI switchers which are tailored to use very low ESR caps, and do not want elec caps in my design. also, the switchers have a limit to the output capacitance of around 100uF which I currently achieved (with ceramics derating), so can't add more caps.another thing I did is putting slightly higher ESR input cap which are high quality tantalum polymer caps from panasonic. it is 15uF with about 100mOhms, combined with the low esr ceramic input caps can yield a good result. do not know if it actually dampens stuff but still good to have overall for more stable capacitance and quality build.___So even if the output voltage ripple at full load is very good, can oscillation happen? how to detect it? I have OWON USB scope and now upgraded to DHO804.___looks like the topic got expanded as usual.but we maybe reached a conclusion that for buck regulator ground pin it is best to have multiple close vias to ground plain to minimize inductance. however, still not sure about return current from load through ground pins through ground plains if it helps having many vias everywhere or leaving some copper pour space without vias in its path.

author: temperance
author_rank: Super Contributor
timestamp: October 09, 2025, 02:01:25 pm
content: QuoteHarmonics of the switching waveform.QuoteYes, especially if you have cables attached to a power supply with only ceramic capacitors on the output. That's why I suggest adding a high ESR capacitor in parallel with the existing MLCC caps to dampen the LC network formed between the cables and the MLCC capacitors. (I didn't state to remove the MLCC and use only a high ESR capacitor, as you deduced from what I wrote.)

author: VEGETA
author_rank: Super Contributor
timestamp: October 09, 2025, 08:56:43 pm
content: Quotethe switcher i use tells it is ok with just ceramics and low esr caps, does not require higher esr caps. also, it has capacitance limit which should not be exceeded. adding the required elec. cap will far exceed the limit.how to detect such behavior using the scope?

author: temperance
author_rank: Super Contributor
timestamp: October 11, 2025, 09:32:09 am
content: QuoteI think you didn't understand what I wrote about the capacitors. For the second time: you need low ESR caps on the output. The high ESR caps in parallel with the low ESR are required to dampen resonances caused by inductance connected to those low high quality factor ESR capacitors.You asked to explain how to measure that: it is a simply an LC circuit.

author: VEGETA
author_rank: Super Contributor
timestamp: October 11, 2025, 11:16:44 am
content: Quote from: temperance on October 11, 2025, 09:32:09 amwell, i did understand but also i re-checked the datasheet and design guideline of the switchers i use and found that they did not recommend any damping on the output capacitors. Their internal controller is designed to work with very low esr caps and still produce stable and low ripple no oscillation output.the inductor i am using is 2.2u and the total capacitance with derating of ceramics is roughly 90-100 uF, also followed design recommendation to have feedforward capacitor.I understand that what you explained is that since i am using 2.2uH and 100uF output filter with all 100uF are very low ESR caps... I need to use something like 300uF capacitor with high esr like for example 3-5 ohms in order to have a nice stable output at all loads. correct?however, the switcher datasheet and design guideline (TI DCAP3) do not recommend exceeding that 90-100uF capacitance by any means (even with Cff), which means putting another 330uF is not gonna work.I previously mentioned that I did test such converter circuit and worked fine, checked the final output on the scope for various loads and still very good without any sign of oscillation. ripple and noise is also nice. no ringing or similar nasty stuff.However, many years ago i made a power supply which is not using such modern switchers, it was not done correctly and it produced humming noise which is a clear sign of oscillation. i solved it by putting a big chinese no-name brand electrolytic capacitor which is guaranteed to be high esr. thus what you said is accurate in such a situation for sure.Aside from all above, will the suggested layout do any harm? any better choice?