Direct-mapped Cache - Valid Bit? - Page 1
Forum section: electronics / projects

author: NorthernWing
author_rank: Contributor
timestamp: November 15, 2021, 05:50:23 pm
content: Been refreshing myself on digital logic again, writing a basic cache controller for the main memory on a soft processor core I've been putting together.Let's say we have a system that operates on 16-bit words with a direct-mapped write-through cache. Each cache line is two words, giving us a 32-bit memory bus. Here's the specific setup:Memory size: 2Mb (64k x 32)Cache size: 32kb (1024 x 32) -> 39kb (1024 x 39) with Tag/Valid...from which we get:Incoming memory address breaks down into: TAG[16:11], INDEX[10:1], OFFSETCache line breaks down into: VALID, TAG[37:32], WORD1[31:16], WORD0[15:0]Now, everything I'm reading refers to theValidbit being necessary for detecting cache hits. I would agree with that if this were a ROM, but software should never be attempting to read a word from RAM unless that address has already been written to. I would think that the only thing necessary to check that the data cached at an index is valid is that the tag at that index matches the memory request. Does the hardwareValidbit serve any purpose here other than stopping runtime errors in software from reading an address before it's been initialized?

author: ataradov
author_rank: Super Contributor
timestamp: November 15, 2021, 06:25:29 pm
content: You are assuming that the cache is always enabled. Some writes to SRAM could have happened before it was enabled. If your cache is hardwired to be always enabled, then it will always be valid, of course.You can also use some reserved TAG value that corresponds to a non-cacheable region for the validity.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 15, 2021, 06:35:37 pm
content: Note that if this is read/write cache, you'll need a 'dirty' flag too. Otherwise that won't work.Of course a 'valid' flag is useful only while the corresponding entry in the cache hasn't been used yet. I think you're assuming here that the memory itself can't have valid content before being written to through the cache. If this assumption holds, then you're right. It wouldn't matter whether a given read gets you a random value from the uninitialized cache line, or read from the uninitialized memory, stored into the cache line, and then read from there.But in many real systems, the memory itself can be written to outside of the cache system. If that is the case, your approach of not using a valid flag will fail. For instance, I've implemented a soft core with cache and SDRAM. The SDRAM content can be written to independently of the CPU core - I can for instance write its content directly from USB - so I definitely need a 'valid' flag for my caches. Another typical case is if you implement some kind of DMA.

author: ataradov
author_rank: Super Contributor
timestamp: November 15, 2021, 06:40:05 pm
content: If it is a write-through cache, then no dirty bit is required, SRAM is always in sync.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 15, 2021, 06:54:40 pm
content: Quote from: ataradov on November 15, 2021, 06:40:05 pmRight.