How to calculate fanout_latency for set_clock_gate_latency ? - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: November 18, 2020, 06:36:02 am
content: Could anyone advise how to calculate the values for-fanout_latencyusing the following examples ?Example AExample BExample C

author: promach
author_rank: Frequent Contributor
timestamp: November 18, 2020, 10:28:36 am
content: Problem solved. See the following :dc_shell> man set_clock_gate_latency2. Synopsys Commands Command Referenceset_clock_gate_latencyNAMEset_clock_gate_latencySpecifies clock network latency values to be used for clock-gat-ing cells, as a function of clock domain, clock-gating stage andfanout.SYNTAXstatus set_clock_gate_latency[-clock clock_list][-overwrite]-stage cg_stage-fanout_latency cg_fanout_list[-transitive_fanout]Data Typesclock_list listcg_stage integercg_fanout_list stringARGUMENTS-clock clock_listSpecifies that the latency must be applied with respect to thespecified clocks. If the -clock option is not specified, thelatency is applied with respect to all clock domains to whichthe clock-gating cell belongs.-overwriteSpecifies that clock latency values previously set on clock-gat-ing cells should be overwritten.-stage cg_stageSpecifies the clock-gating stage to which the clock latency datafrom the fanout range is applied. Registers are considered asstage 0.-fanout_latency cg_fanout_listSpecifies the list of clock-gating cells fanout and clocklatency values; for example, {1-5 0.9, 6-20 0.5, 21-inf 0.3}. Afanout of 1 to 5 has a latency of 0.9; a fanout of 21 or largerhas a latency of 0.3. If the same latency value is wanted forthe entire fanout range, it can be specified as {1-inf 0.9}.-transitive_fanoutSpecifies that transitive fanout should be used instead ofdirect fanout when annotating clock gate latency. Direct fanoutis the default.DESCRIPTIONThe set_clock_gate_latency command allows you to specify clock networklatency values for clock-gating cells, as a function of clock domain,clock-gating stage, and fanout. These latency values are annotated onthe clock pins of clock-gating cells when running the compile_ultracommand, or when running the apply_clock_gate_latency command.The clock-gate latency settings specified using theset_clock_gate_latency command are stored as an attribute on the sourceport of each specified clock. Invoke this command after defining allclocks of the design. These stored latency values are annotated on theclock pins of clock-gating cells by means of one of the following pro-cesses:o Using the apply_clock_gate_latency command, which applies latency onany existing clock-gating cellso During compile_ultra command, which applies latency on any existingclock-gating cells or those inserted or modified during the compileNOTE: The stages of the clock gating network are numbered from 0 forthe register stage number and increasing toward the clock source. Forexample, in a four stage clock gating tree, Stage 0 drives registerclocks directly, and Stage 3 is the clock gating cell with its inputdirectly connected to the clock source.Use the set_clock_gate_latency command to specify the latency for gatedregisters by specifying the command for stage 0. By definition stage 0has no fanout, so use the following syntax:prompt> set_clock_gate_latency -stage 0 -fanout_latency \{ 1-inf value }When clock latency settings are provided for stage 0, the values areannotated on the output pin (enabled clock pin) of each clock-gatingcell that is directly driving gated registers. If no clock latency isset for stage 0, but a clock latency has been set on the clock objectby using set_clock_latency command, then this value is used for clocklatency. For ungated registers, the latency is propagated by the timerfrom the clock object latency.You can use the -clock and -overwrite options with the -stage 0 option.Use the -transitive_fanout option to calculate latency value based uponthe transitive fanout of a clock-gating cell instead of the directfanout. The transitive fanout of a clock-gating cell is defined as thetotal number of all driven leaf registers. The registers driven by astage 1 clock-gating cell, ICG_1, are counted as part of the transitivefanout of the stage 2 clock-gating cell, ICG_2, that drives ICG_1. Bydefinition:stage 2 transitive fanout >= stage 1 transitive fanoutNOTE: Transitive fanout only counts registers, unlike the direct fanoutwhich counts both registers and driven clock-gating cells.When the -transitive_fanout option is used for the first time, a fanoutmode is set, and this is indicated by the PWR-916 information message.You cannot mix fanout modes of the set_clock_gate_latency command,where some instances use the -transitive_fanout option and others donot. If you want to switch between fanout modes, use thereset_clock_gate_latency command.If you specify fanout ranges in the cg_fanout_list and you do not coverall values from 1 to inf, the fanout ranges with missing latency infor-mation are filled by the tool with the smallest latency value from theadjacent ranges.In a clock tree, latency values are lowest for cells closest to the topof the tree (clock source). Transitive fanout values are highest forcells at the source and decrease toward the registers. Therefore, spec-ified clock latency values must decrease with respect to fanout rangesotherwise a PWR-742 warning message is generated.If clock latency settings are not specified for a certain clock-gatingstage and a clock-gating cell within this stage exists, the latency ispropagated from the driving clock-gating cell or from clock objectlatency, and a warning message is issued. These actions are performedduring the annotation process:apply_clock_gate_latency or compile_ultra command.If specified clock latency values do not decrease with respect to clockgating stages, the PWR-744 warning message is generated. This check isdisabled if the -transitive_fanout option is used. In addition, if aninconsistent clock latency annotation is detected when running theapply_clock_gate_latency or compile_ultra command, the tool attempts tofix it by assuming the smallest value from the clock latencies anno-tated on gated clock-gating cells or registers. This ensures thatclock latencies are monotonically increasing values in the path goingfrom the clock source to the gated registers. The following actionscan be performed by the tool to achieve this:o If clock-gating cell A is directly driving one or more registers,and some clock latency settings have been provided for the timing ofthese gated registers (by using value 0 for the -stage option ofset_clock_gate_latency command or by propagation of latency specifiedfor clock object), and the latency annotated on cell A is higher thanthe latency provided for gated registers, then the latency on clock-gating cell A is overwritten with the latency provided for gated reg-isters. If this fix is done, the PWR-746 warning message is gener-ated.o If clock-gating cell A is driving another clock-gating cell B, andthe clock latency set on A is higher than the one set on B, the toolresolves it by overwriting the clock latency on A with the value seton B. If this fix is done, the PWR-746 warning message is generated.To remove the settings specified using set_clock_gate_latency, use thereset_clock_gate_latency command.If the variable power_cg_physically_aware_cg is enabled, then the anno-tation of latency values from set_clock_gate_latency is disabled.Multicorner-Multimode SupportThis command is scenario dependent and affects the current scenarioonly.The actual clock latency annotation performed during the execution ofthe compile_ultra or apply_clock_gate_latency commands is done for allthe scenarios for which a clock latency value is available.EXAMPLESThe following example specifies the clock latency values for the com-plete fanout range of clock-gating cells for stages 1, 2, and 3. Thislatency data applies to the clock-gating cells whose clock pins belongsto clock clk1.prompt> set_clock_gate_latency -clock [get_clocks clk1] -stage 1 \-fanout_latency {1-30 2.1, 31-100 1.7, 101-inf 1.1}prompt> set_clock_gate_latency -clock [get_clocks clk1] -stage 2 \-fanout_latency {1-5 0.9, 6-20 0.5, 21-inf 0.3}prompt> set_clock_gate_latency -clock [get_clocks clk1] -stage 3 \-fanout_latency {1-10 0.28, 11-inf 0.11}In the following example, fanout ranges specified in the-fanout_latency cg_fanout_list do not cover all values from 1 to inf.In this case, the tool assumes a clock latency value of 1.7 to beapplied to fanout range 11-30 and a clock latency of 1.1 for fanoutshigher than 80.prompt> set_clock_gate_latency -stage 1 \-fanout_latency {1-10 2.1, 31-80 1.7, 101-300 1.1}The following example shows how to specify and annotate different clocklatency values using the transitive fanout.prompt> set_clock_gate_latency -clock [get_clocks clk1] -stage 1 \-fanout_latency {1-30 2.1, 31-100 1.7, 101-inf 1.1} \-transitive_fanoutprompt> set_clock_gate_latency -clock [get_clocks clk1] -stage 2 \-fanout_latency {1-5 0.9, 6-20 0.5, 21-inf 0.3} \-transitive_fanoutThe following example shows how to specify and annotate different clocklatency values for different multicorner-multimode scenarios.prompt> current_scenario sc1prompt> set_clock_gate_latency -stage 1 \-fanout_latency {1-inf 0.11}prompt> current_scenario sc2prompt> set_clock_gate_latency -stage 1 \-fanout_latency {1-inf 0.15}prompt> compile_ultra -gate_clockSEE ALSOapply_clock_gate_latency(2)power_cg_physically_aware_cg(3)remove_clock_latency(2)report_clock_gating(2)reset_clock_gate_latency(2)set_clock_latency(2)