Clock divider /2, Gal22v10B and wincupl - Page 1
Forum section: electronics / general

author: lk
author_rank: Regular Contributor
timestamp: December 13, 2017, 07:57:07 pm
content: Greetings,Im tinkering with a 6502 computer, that i have working but i wanted to see if i could replace the logic ICS with a PLD, which for the most part was not problem(NAND and inverters), however i have 74HC74, that halves the clock of the system, and i simply cannot figure out how to implement some sort of divider or counter, that i can use to reduce the clock, the only tool i have available is wincupl.I have looked at the examples, but as the features of different parts affect what you can do, i have a hard time figuring out how to crack this nut.Below is the nonworking code, i basically dont know what im doing:) as soon i move past very basic logic.Is it possible to implement a counter/divider that could halve my clock input?Code:Name test ;PartNo 00 ;Date 12/13/2017 ;Revision 01 ;Designer Newbie ;Company Lasse ;Assembly None ;Location ;Device g22v10 ;/* *************** INPUT PINS *********************/PIN 1 = phi2 ;PIN 2 = RW ;PIN 3 = A14 ;PIN 4 = A15 ;PIN 5 = RWINVinput;PIN 15 = R;PIN 11 = S;/* *************** OUTPUT PINS *********************/PIN 19 = topaddressactivelow;PIN 18 = outputenable;PIN 17 = writeenable;PIN 16 = rwinvoutput;PIN 14 = Q;rwinvoutput = !RW;topaddressactivelow = !( A14 & A15);outputenable = !( phi2 & RW );writeenable = !( phi2 & RWINVinput);Q.D = Q.AR;Here is a picture of the device i want to use, mainly because i have it and it was cheaphttps://photos.app.goo.gl/951yMkD2UiyEEvC03-lasse

author: joeqsmith
author_rank: Super Contributor
timestamp: December 13, 2017, 09:18:57 pm
content: Nice! I used the 22V10 on the 6801 computer that runs the transient generator, just because.PALASM is free and will run under DOSBOX as well. I tried using CUPL when PALASM would no longer run with Windows NT. I remember finding several bugs in it and eventually pitched it. I switched to the Lattice tools which work very well but I am not sure if they offer a free version.

author: edavid
author_rank: Super Contributor
timestamp: December 13, 2017, 09:39:30 pm
content: I don't have WinCUPL installed, but I don't know why you are trying to use AR. Shouldn't it be something like Q.D = !Q ?

author: joeqsmith
author_rank: Super Contributor
timestamp: December 13, 2017, 10:15:36 pm
content: Quote from: edavid on December 13, 2017, 09:39:30 pmLooking at my old CUPL projects, I believe you are correct.CUPL(WM): Universal Compiler for Programmable LogicVersion 4.8aCopyright (c) 1983, 1996 Logical Devices, Inc.4MHZ.d = !4MHZ ;

author: lk
author_rank: Regular Contributor
timestamp: December 14, 2017, 03:58:23 pm
content: Hi joeqsmith and edavid,I changedQ.D = !CLK;However i have no idea how to get that signal to show up on a pin, when i simulate in proteus, i can see that the Q pin starts high, but the slowly drains to gnd.I have zero idea what im doinghttps://photos.app.goo.gl/951yMkD2UiyEEvC03Code:Name test ;PartNo 00 ;Date 12/13/2017 ;Revision 01 ;Designer Newbie ;Company Lasse ;Assembly None ;Location ;Device g22v10 ;/* *************** INPUT PINS *********************/PIN 1 = CLK ;PIN 2 = RW ;PIN 3 = A14 ;PIN 4 = A15 ;PIN 5 = RWINVinput;PIN 11 = S;/* *************** OUTPUT PINS *********************/PIN 19 = topaddressactivelow;PIN 18 = outputenable;PIN 17 = writeenable;PIN 16 = rwinvoutput;PIN 14 = Q;PIN 15 = CLKOUT;rwinvoutput = !RW;topaddressactivelow = !( A14 & A15);outputenable = !( CLK & RW );writeenable = !( CLK & RWINVinput);Q.D = !CLK;

author: edavid
author_rank: Super Contributor
timestamp: December 14, 2017, 04:37:39 pm
content: Quote from: lk on December 14, 2017, 03:58:23 pmTry:Q.D = !Q;

author: lk
author_rank: Regular Contributor
timestamp: December 14, 2017, 05:21:27 pm
content: Thank you , edavidthat worked-lasse