Decoupling caps - Page 1
Forum section: electronics / beginners

author: Bluestreak66
author_rank: Regular Contributor
timestamp: June 30, 2013, 06:48:18 am
content: How do you determine the number and value of decoupling caps to use around a processor? Does operating frequency determine this? If the core voltage supply is lower noise are less required? Can you have too many?

author: Unknown
author_rank: Unknown
timestamp: June 30, 2013, 06:53:36 am
content: From what I'm reading, choosing the correct value is kind of an art. A small value are better at dealing with small transients, but a large value means that there's a lot of parasitic inductance, which has its own problems. This might be helpful:http://forum.allaboutcircuits.com/showthread.php?t=6333

author: millerb
author_rank: Regular Contributor
timestamp: June 30, 2013, 07:20:09 am
content: I start off by scouring the datasheet for the proc to see what's in their application examples, if they exit. Then I dig through the application design literature the manufacturer provides for guidance. A lot companies put out literature of what they consider best practices for this topic. I also look at any available demo boards for the part which usually include a schematic and bill of materials. More often than not I end up copying a good chunk of the reference boards, that's what they're there for.

author: Bluestreak66
author_rank: Regular Contributor
timestamp: June 30, 2013, 07:51:52 am
content: Quote from: millerb on June 30, 2013, 07:20:09 amThats normally what I would do is just copy the reference design. But There is only one design and hasn't been a whole lot of custom boards build with it. I'm questioning whether I could get by using less caps and a clearer core supply. What is used in the reference design is what looks to be a single phase synchronous buck converter driving 4 mosfets. If I used a 3 phase converter I think I could have less noise and have better transient response. I wouldn't even be questioning it but @ 11 decoupling caps per chip and 16 asics that's 176 caps all in all it will be over 200 caps just to support the asics. Not only is that alot of caps to place by hand I'm limited to 1000 pins in Diptrace and Im almost at the limit without even haveing the power supply placed.Heres the reference design.https://github.com/BitSyncom/avalon-ref/blob/master/PDF/SCH/hash_chip.pdf

author: SeanB
author_rank: Super Contributor
timestamp: June 30, 2013, 10:23:20 am
content: Looks like you need all of them. You might want to look then at making the board in 2 parts and possibly using a connector on them. You probably could cut 16 caps by making a common reset circuit for all of the processors and use a single logic level reset generator to provide a common reset. That will make it more reliable as well.

author: Bluestreak66
author_rank: Regular Contributor
timestamp: June 30, 2013, 11:12:10 am
content: What makes you say I need the same amount of decoupling cap as in that design? Thank for the heads up on the reset circuit I had though about a single reset circuit but thats as far as i got. I dont want to split the board up its already spit up. It was originally a 32 asic board now its 16 with i2c communication between them.

author: SeanB
author_rank: Super Contributor
timestamp: June 30, 2013, 12:22:33 pm
content: You probably could share caps between power rails if they are the same voltage and go into pins next to each other, but then you would have to place a 10uF or so bulk capacitor per package as well, which would be needed in any case.

author: Bluestreak66
author_rank: Regular Contributor
timestamp: June 30, 2013, 03:37:42 pm
content: What would happen if I used a copper pour around the chips tied to 1.2v? Would that make a difference on the number or placement? Would this have any negative affects?

author: Bluestreak66
author_rank: Regular Contributor
timestamp: June 30, 2013, 03:53:28 pm
content: I have these in groups of four within 5mm of each other. If i placed a copper pour tied to 1.2v core voltage and used 4 .47uF cap per chip around the outside of the group and say two larger 10uf in the center of the group would this work? I know its just a guessing game right now because with out a physical board and checking with a scope its going to be impossible to say for sure, but I figure someone surely has done this before and could share some insight. Just some additional info these chips they run at 300mhz and I can adjust the frequency 10% up or down also they draw about 1.8 amps each @ 1.2v core voltage. The power supply I have selected will be rated with about 20% overhead and I can adjust the switching frequency.

author: AndyC_772
author_rank: Super Contributor
timestamp: June 30, 2013, 04:44:59 pm
content: It's virtually impossible to work out the optimal number and size of decoupling capacitors for a design. There are hugely expensive simulation tools out there which can do it - or at least, which can work out how effective your chosen decoupling strategy is likely to be once you've laid out the PCB - but tools like that are most suited to boards where the BoM cost is absolutely critical (think PC motherboards) or where reliability is absolutely crucial and development cost is unconstrained (military, communications backbone, possibly medical).The important factors which determine how effective decoupling needs to be are the noise margin available (both functional and EMC), and the frequency content of the current drawn by the device being decoupled.That frequency content doesn't really depend on the operating frequency of the device, it depends on the speed with which the device switches on each clock edge. You could run a microprocessor at 1 Hz and it could still draw a current pulse lasting 1ns on each edge, and would therefore still require decoupling that's effective up at 1 GHz. This is something many people fail to truly understand and appreciate - it's the edge rate (ie. Volts per second or Amps per second) that matters, not the number of edges per second.As a rough rule of thumb, which you probably already know, one decoupling capacitor per power pin is a good place to start - but that's only the starting point. If you have power pins that are very close together (say, 5mm apart or less), then there's not much point in trying to squeeze in two capacitors - you can probably save one.What limits the effectiveness of a decoupling capacitor is the series inductance between the cap and the silicon die that it's supposed to be supporting - and bear in mind always that it's the whole loop that matters (ie. including the ground connection), not just the distance between the cap's positive terminal and the VCC pin.The mistake I see most often is that a decoupling cap is placed on the board in a reasonable place, somewhere near the VCC and GND pins of a chip, but it's then routed with a track several mm long to a single via which then goes into the power or ground plane. Somewhere else, another via connects the chip to that same plane. This is a terrible way to route a decoupling capacitor, and yet I see it time after time after time. Often people get away with it because an IC just isn't that demanding - but that doesn't mean to say there isn't a great deal of room for improvement.Much better is to place the via right next to the capacitor pad, so the trace all but disappears. There may be PCB manufacturing rules that limit just how close it's possible to get, but make sure your pad-to-via spacing is right up against that rule, and push back on it to get even closer if you can... it's worth paying a bit more on the PCB if you get a design that actually works.If you can't get a capacitor right next to the IC pin, don't route between the two with a trace, use the power or ground plane. For any distance longer than a couple of mm, the plane is always the lowest inductance way to join two points on a PCB. Put in a via between the cap and the IC as close to the cap as you can, and connect the IC pin with a via as close to the IC pin as you can but on the same side as the cap. This keeps the total routed distance as short as possible, and ensures that it's the plane which spans the distance and not a trace.A PCB trace has an inductance of about 1nH per mm. Work out the impedance of this at, say, 100 MHz, and compare it to the impedance of an ideal 10nF decoupling capacitor at the same frequency. You may be surprised at just how significant even 1mm of trace turns out to be. Don't forget that if you have 1mm between each capacitor pad and the plane (including the distance through the via!) then that's already 2mm.What you'll work out is that the trace inductance absolutely kills the performance of the cap at higher frequencies, so keep it to an absolute minimum. For example, two traces are better than one, so use two separate vias to connect a single capacitor pad to its power plane - the effect is almost as good as having two capacitors. Better yet is to place a small copper flood around each capacitor pad and peg it into the plane with as many vias as will fit. If it starts to look like an RF circuit then that's perfect. It *is* an RF circuit.Keep the capacitors as physically small as possible. It's often said that lower value caps work better at higher frequencies than higher value ones, but this is a bit of a misconception; lower value caps can be made physically smaller, so they have less parasitic series inductance of their own, and that's why they work better - not because of the lower capacitance but because of their smaller size.For this reason, two identically sized caps will perform similarly even if, say, one is 100nF and the other is 10nF. (Slight complication - they'll resonate at different frequencies, so their effectivenessin a given circuitmay differ - but as a rule, adding different values of decoupling cap just increases the chance that you'll create an unwelcome resonance and have a problem at a particular frequency. I almost always just use 100nF 0402 caps unless it's prescribed that I do otherwise).

author: KJDS
author_rank: Super Contributor
timestamp: June 30, 2013, 05:55:34 pm
content: I like that summery, however the one point I'd like to pick up on is that every military project I've ever worked on has always been far more squeezed of development cash than any of the commercial or space projects I've done. It's the one sector that i try and avoid working on, unless it's a particularly interesting project.

author: Marco
author_rank: Super Contributor
timestamp: June 30, 2013, 05:58:18 pm
content: I wonder if the future will be just to bury a high permittivity ceramic directly in the PCB between the main power and ground plane.

author: AndyC_772
author_rank: Super Contributor
timestamp: June 30, 2013, 06:29:32 pm
content: Quote from: Marco on June 30, 2013, 05:58:18 pmWhat I omitted to mention was that it's the plane-to-plane capacitance which is the only effective decoupling you have at frequencies of, say, 200 MHz+.Decoupling capacitors attached to the pins of ICs are important, but they're only effective across quite a limited frequency band. Below that band (say, < 1 Mhz), look to use much larger bulk capacitors - 10uF or larger, ceramic or tantalum caps scattered across the board. From a few hundred MHz upwards, it's the PCB itself that provides the only useful decoupling you have - and the inductance of the IC's lead frame will still limit its effectiveness. This is one reason why BGAs are so much better for high speed ICs than QFP, and is why some ICs (PC processors spring to mind) incorporate decoupling capacitors as part of the package itself.