74HC series D type FF outputting spikes? - Page 1
Forum section: electronics / beginners

author: AlfBaz
author_rank: Super Contributor
timestamp: May 09, 2013, 01:12:26 am
content: On a bread board I have an oscillator who's output I want to turn into a complementary pair of signals. To do this I run it through a 74HC74 dual D type flip flop.The osc output wasn't going quite to zero (~~ 0.8V) still below a Vil of 1.35@4.5Vcc but just to be sure I sourced the signal from a signal gen and it still does it.The osc output goes to the FF's clk input, set and clear are held high (inactive) and Q' is connected to D. Q' and Q then provide a f/2 complementary output. Sounds simple enough but what I'm seeing on Q and Q' are spikes where the +ve and -ve transitions should be.I have checked rise, fall, setup and hold times off the '74 specs and on the bread board and everything seems to be in order.If I lower the supply voltage (it's supposed to be good to 6V) to around 4.2V the output comes good (square waves). Also if a load the outputs it also comes good.According to the datasheet the outputs have a totem pole arrangement with P and N channel mosfetsIs this just cmos logic 101, though shalt not have outputs open cct?Just wondering if anyone can explain what's going on and why

author: David_AVD
author_rank: Super Contributor
timestamp: May 09, 2013, 01:34:15 am
content: Got a bypass cap right across the Vdd-Vss pins?

author: Rufus
author_rank: Super Contributor
timestamp: May 09, 2013, 01:35:49 am
content: Hard to say.Slow clock rise time making it sensitive to noise and liable to clock twice.Coupling from output to clock making it clock twice.Poor supply decoupling.If you are driving something with the output spikes on the output can cause FFs to flip.Unused inputs should not be floating even on the unused half of the chip.If dropping the supply fixes it something is marginal so poking around with a scope probe or wet finger might reveal what is sensitive.

author: envisionelec
author_rank: Frequent Contributor
timestamp: May 09, 2013, 01:38:39 am
content: Is your measurement ground connection at the same potential as the IC?

author: AlfBaz
author_rank: Super Contributor
timestamp: May 09, 2013, 01:50:47 am
content: Quote from: David_AVD on May 09, 2013, 01:34:15 amNoWill try it and get back later on tonightQuote from: Rufus on May 09, 2013, 01:35:49 amI'll have to double check those. I remember seeing that my clock transition times where way better than Q/Q' (max 500ns), but this may be causing the coupling you speak ofQuotesee aboveQuoteIts happening with the outputs unloadedQuoteThat did cross my mind and have tied unused inputs to their appropriate levelsQuotelol, that's what led me to find out that loaded outputs fixed the problem

author: AlfBaz
author_rank: Super Contributor
timestamp: May 09, 2013, 01:51:56 am
content: Quote from: envisionelec on May 09, 2013, 01:38:39 amyes

author: AlfBaz
author_rank: Super Contributor
timestamp: May 09, 2013, 02:25:40 am
content: Stuck a 0.1uF ceramic across Vdd Vss and its now good up to 5.5V supplyThank you all for the quick replies

author: David_AVD
author_rank: Super Contributor
timestamp: May 09, 2013, 02:28:06 am
content: Excellent news. Never underestimate the effects of missing decoupling capacitors.

author: AlfBaz
author_rank: Super Contributor
timestamp: May 09, 2013, 02:33:32 am
content: Quote from: David_AVD on May 09, 2013, 02:28:06 amYeah, or be to eager to try something out and forget the fundamentals

author: David_AVD
author_rank: Super Contributor
timestamp: May 09, 2013, 05:16:18 am
content: Quote from: AlfBaz on May 09, 2013, 02:33:32 amAh, we've all been there.