It keeps blowing up! - Page 1
Forum section: electronics / projects

author: Powermax
author_rank: Regular Contributor
timestamp: November 22, 2020, 12:18:53 am
content: Here is a quick 1 minute video of my latest Tesla Coil project. Unfortunately it is still popping when running in Continuous Wave, and especially when drawing a short arc. I think the reason is over-current in the MOSFET's, although immediatly following that failure the MOSFET heatsinks were still cool to the touch and the FETs only warm, so I don't know!Is it possible for MOSFETs to fail due to over-current without the junction getting too hot?The project for the H bridge can be found here:https://github.com/power-max/universal-half-bridgeNote that there are some changes that I am looking to implement:Bring the hi-side and lo-side MOSFET closer togetherBring the driver closer to the FETsIncrease trace widths for everythingexposed copper for soldering copper bar for increased current handlingmaybe several parallel MOSFETs (2 or 3 pair) to reduce conduction losses and increase current capabilityAs it stands from what I could measure the voltage of the gate waveform was pretty clean, and the voltage across the drain-source of either FET looked fine, my diode clamps do a good job of clamping the voltage to remain within bounds of the supply voltage, with only around 5V overshoot.

author: uer166
author_rank: Super Contributor
timestamp: November 22, 2020, 12:37:35 am
content: Post scope shots of Vds, Vgs, and (if you can, Id). Both rising, falling edges, and the initial start up from nothing to full load.With no scope traces it's hard to impossible to root cause. Also, how do you know the junction doesn't get hot? The case temperature lags, and the junction can melt well before anything reaches the case temp.

author: bob91343
author_rank: Super Contributor
timestamp: November 22, 2020, 03:11:43 am
content: Most of the failures in transistors seem to involve local heat such that the outside never gets warm. It's a matter of fusing of a lead inside the unit.

author: james_s
author_rank: Super Contributor
timestamp: November 22, 2020, 04:00:15 am
content: Mosfets can fail instantly if any parameter goes outside of the SOA. Your sustained average current may be well within the ratings but you can still have a peak current that is beyond what they can tolerate even for an instant.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: November 22, 2020, 09:32:36 pm
content: Those transistors go out quite violently @01:31.That is not just some kind of over current condition. I suspect you go over the maximum drain voltage and the FET goes into avalanche with no current limit.For such things PCB layout can be quite important, as tracks work as inductors at high di/dt values and if clamping components are too far away they don't work properly.Similarly, if the GND is not real solid or carefully laid out, the source can be lifted locally and exceed the 20V Gate voltage, which then destroys it, shorts the FET which then causes the rest of the fireworks.

author: Wolfram
author_rank: Frequent Contributor
timestamp: November 22, 2020, 10:57:12 pm
content: What switching devices are you using at the moment? How are you generating the switching control signal?Provided that you're certain there are no problems in your gate driver, there are a few remaining options.One of them is exceeding the maximum safe dV/dt or dI/dt during forced reverse diode recovery. If you ever lose zero-voltage-switching (either due to the drive frequency being below the instantaneous resonant frequency, or the loaded Q of the secondary being insufficient to commutate the switching node voltage during your dead-time), latchup can happen and lead to instant destruction.What dead time and leading phase angle do you presently run with? If you cannot guarantee ZVS under all circumstances, you can either bypass the internal FET diodes with a series schottky and a parallel fast diode, slow down the turn-on enough to never exceed the diode specifications, or swap the FETs for ones that have more robust reverse diodes. Modern superjunction devices, particularly the Infineon CFD7 series are good here, though they're usually only available in higher voltage ratings. The same goes for SiC MOSFETS and Silicon IGBTs, though look out for the high turn-off losses that can be problematic with the latter, especially at higher switching frequencies.Edit: As suggested by others already, it's hard to draw any conclusions without measurements. Oscilloscope shots of the switching node voltage and the load current would be a good starting point, especially with ground arcs. The usual precautions when scoping mains-connected equipment apply.

author: Powermax
author_rank: Regular Contributor
timestamp: November 23, 2020, 07:29:52 pm
content: Thanks for all the input everyone! I posted this not so much as a question (since Ialready asked about this a while back) but more just to share my excitement that it's at least sort of working at rectified mains! I did post a big update on that thread but that thread kinda died so I don't think many people saw it. To follow up on the questions / advice here:QuoteI'm usingHY1920PMOSFET, which is rated for 70A at 100*C, in a half bridge arrangement. It is driven using a 4A/4A IRS2186 but through a 6 ohm resistor to soften the switch on and off, in attempt to limit dv/dt and di/dt (soft switched)QuoteYup! I am in fact operating above and below resonance (Phase Locked Loop tracks the feedback, audio frequency modulated for clear audio). I knew this could cause voltage overshoots which I mitigated with ultrafast 4ns diodes and low ESL MLCC capacitors on both fets (the low-side diode near the hi-side FET) to really clamp any voltage overshoot to a local MLCC capacitor through the flyback diode.But you bring up dv/dt and di/dt. And this may actually very well be the issue. I did add a 1nF capacitor in series with 5 ohm resistor to slow this down, as per DiodeGoneWild's circuit. The gate drive is also through a 6 ohm resistor. However since this was a cludgy afterthought it was placed on the screw lugs and is not as close to the MOSFET drain and source as it probably should be.I might also try not joining the source and drain together immediately, but carrying both connections separately to the coil. Would this help the matter? The increased inductance might limit di/dt, and the diode clamp I have can ensure voltages on the drain and source don't exceed 200V.Reason I don't think voltage kills my FETs is because:* Failure is just as frequent at 50VDC as it is at 170VDC, though I need to draw a much shorter arc at 50VDC to get the circuit to die. (makes sense, less input voltage, less output voltage)* Failure is more frequent if MOSFETs are not cooled adequately. Although in my fail video the MOSFET heatsinks and FETs themselves felt cold. It didn't run for long. (maybe the junction did not have enough time to sink the heat?)* The primary current is usually at a peak when the MOSFETs fail, but last time I actually measured it, it was around 50A peak when run continuous duty (over-current possibly?)

author: Powermax
author_rank: Regular Contributor
timestamp: November 23, 2020, 08:22:14 pm
content: Quote from: Doctorandus_P on November 22, 2020, 09:32:36 pmIt actually was the PCB trace itself that VAPORIZED rather than the FETMight post a closeup pic of that when I'm back home. The FET fails short circuit, the current from the MLCC capacitors and bulk storage electrolytic is then dumped into the other conducting FET (shoot-through) and both FETs die instantly. At lower voltages from a regulated supply (which has a much faster short circuit protection than a 20A mechanical household circuit breaker) sometimes one of the FETs will survive. but with rectified and filtered mains, usually all the silicon chips on the PCB die.Yeah I took a lot of care to make sure the Vgs(max) of the top and bottom fet is not exceeded, by closing the current loop for both FETs with a flyback diode and a massive 400nF bank of MLCC capacitors, and kept those traces thick and the loop area as tight as the components footprints would allow. It was successful because I did not observe much if any overshoot running at 50VDC even without an additional snubber, which I added later as an afterthought because I suspect dv/dt is causing latchup inside the MOSFETs (triggering the parasitic BJT) I might need to try more snubbing and incorporate that in my new PCB layout.

author: Powermax
author_rank: Regular Contributor
timestamp: November 23, 2020, 08:24:38 pm
content: Quote from: uer166 on November 22, 2020, 12:37:35 amI did measure a few things, when I looked at the drain-source waveform on the scope, it was pretty square with only 5V of overshoot running on 50VDC and 100VDC. I have posted some of these measurments on Imgur/reddit a while back, I'll need to dig them back up and repost them here. I did not measure at 170VDC as shown in my fail video (yes I know I show 2 meanwell supplies, but most of the video of operating is half or full bridge rectified mains lol) However at the terminal lug there is considerable more ringing at many dozens of MHz, due to trace inductance from the FETs.Quote from: bob91343 on November 22, 2020, 03:11:43 amThis is my suspicion, too. I am working on a new H bridge that places 3 of these HY1920P FETs in parallel. (Gates, Drains, and Sources shorted together) I might separate the gates with separate gate resistors though, will need to read up on how to do it right.Quote from: james_s on November 22, 2020, 04:00:15 amAh yes, the SOA. I took a closer look at it, and it could very well be peak currents going outside of the SOA, I did measure 90A peaks with a current transformer when operated in interrupted mode, though it seems lower under sustained continuous wave operation, although it does increase noticeably if I dead short circuit the output, which is odd. I guess because of the lower Coupling, the primary rejects H field and causes the Q factor to shoot up? The coil does seem to run most reliably with just a breakout shooting out of the topload. If I don't include a breakout point I get too much voltage on the topload and destructive arcing between primary and secondary.

author: trobbins
author_rank: Frequent Contributor
timestamp: November 24, 2020, 12:24:09 am
content: As well as a general video, perhaps a new thread should start with direct links to a system and FET pcb schematics and FET pcb layout (in pdf form for general viewing), and test waveforms that are probed direct at the FET.Is the gate drive IC on that proto board, or on the FET pcb ?

author: james_s
author_rank: Super Contributor
timestamp: November 24, 2020, 02:10:41 am
content: Quote from: Doctorandus_P on November 22, 2020, 09:32:36 pmThey usually do go out violently when they're in a bridge. One of them fails shorted, this causes a shoot through condition when the other one turns on which causes that one to fail, and then you have a direct short across the DC bus and something grenades.

author: uer166
author_rank: Super Contributor
timestamp: November 24, 2020, 03:27:13 am
content: Quote from: Powermax on November 23, 2020, 07:29:52 pmYou mean to say, you're not measuring it in real-time as part of normal operation? If that is so, you can expect your FETs (and everything else around them) to blow up on the turn-on transient, as well as randomly due to varying load conditions.Unless you have either current-mode control, or at least a fast overcurrent protection embedded in the power stage, it's a waste of everyone's time.

author: Powermax
author_rank: Regular Contributor
timestamp: November 25, 2020, 05:40:01 pm
content: Quote from: uer166 on November 24, 2020, 03:27:13 amNo, I was not able to measure it while running with a full bridge converter because there's no isolation between high voltage primary and low voltage controller. They share a common ground (a result of using a half bridge converter IC w/o optocouplers) I could change the design to use a GDT instead but I wanted this half bridge PCB to be used for other projects as well (LLC converter, flyback driver, motor driver, etc). And the current transformer output is also part of the design -- it is the feedback into the input of a CD4046 and is therefore not isolated from ground. Connecting the ground clip to anything on the low voltage side would result in a short circuit.The control loop converges to the resonant frequency directly, although not always perfectly, as the phase locked loop is using proportional controller and the phase comparator requires there to always be a small phase offset, which causes it to run slightly above or below resonance depending on the tuning, propagation delays, and phasing. So I measured current when I wanted to see if that was resulting in the MOSFET failures. The current varies a lot depending how the system is configured, tuned, and the environmental factors like the length of the arc being drawn. I will probably make this into a series of videos from beginning and design discussion through to testing it and what I've learned.

author: Wolfram
author_rank: Frequent Contributor
timestamp: November 25, 2020, 06:10:14 pm
content: If you already have a primary current transformer for the PLL, it's pretty easy to add an overcurrent comparator that latches the gate drivers in a disabled state in the event that excessive primary current is detected. Due to the unpredictability of the load impedance (which is the variable capacitance and resistance of a chaotic arc load). You can either detect anomalous load current and act on it, or overdimension everything greatly and live with lower performance than otherwise possible. You have neither at the moment, which is likely the reason it keeps blowing up. You've saved the cost of the overcurrent comparator ten times over the first time it acts and protects your switches. I've designed a wide variety of power conversion circuits, and hardware overcurrent protection is one of the few things which is non-negotiable. I still keep a box of exploded transistors to remind me of the times before I figured this out.Edit: What are the upper and lower VCO frequencies that can be commanded by your phase detector? What is the primary resonant frequency?Are you using the type II phase detector built into the 4046? This one has some issues with driving resonant loads, as any missing or extra pulse on the phase comparator input can get the state machine into a mode where it slams the VCO to either end of the range. The problem is that this phase detector has more than a cycle of memory, so in the case of a missing pulse it will speed up the VCO to compensate for the missing cycle. But this is impossible under normal circumstances as the primary current and VCO output are frequency-locked together by definition; the current is a result of the voltage with a nominal phase shift of +- 90 degrees, depending on the frequency. This is assuming that primary-secondary coupling is reasonably low.

author: uer166
author_rank: Super Contributor
timestamp: November 25, 2020, 09:19:46 pm
content: I remember that one time my fault overcurrent flip-flop kept tripping, but I wasn't measuring any current through the FETs. So, I disabled it, thinking that something was wrong with it. Nope! Was bad probing, the FETs immediately blew up due to a control issue, and the overcurrent was indeed real

author: jbb
author_rank: Super Contributor
timestamp: November 25, 2020, 10:34:07 pm
content: Have you considered reverse recovery of the opposing MOSFET body diode? That can generate large current spikes during switch turn on.You’re driving a (semi)resonant load - hopefully in the inductive region which helps with softer switching - but can you sometimes move into the capacitive region? Eg under short circuit conditions?

author: jbb
author_rank: Super Contributor
timestamp: November 25, 2020, 10:52:03 pm
content: Oh yes. I thoroughly recommend isolated gate drivers (Silicon Labs, Analog Devices, Texas Instruments and more make them).Even if your control system is on the same ground and you don’t ‘need’ the isolation for functionality, it’s really good to have that isolation so MOSFET failures don’t then blow up your control system via the gate drivers.

author: Powermax
author_rank: Regular Contributor
timestamp: November 29, 2020, 01:10:07 am
content: What do you guys think of my revised H bridge design? Pictures of PCB uploaded here.now have 2 MOSFETs in parallel, 4 in total. This updated PCB brings in the MOSFETs much closer to the driver, closing the loops as much as possible and used thicker traces to minimize any series inductance with the gate drive. I also added a BJT in a SOT23 package to discharge the gate quicker with a series resistor to soften the turn-on, since turn-on does not have to be hard switched as the turn-off does. (for ZVS drive, turn-on times are not as critical). I also added a snubber network and kept the diode clamps. The MOSFETs can be bent downwards an mounted to a solid copper heatsink. May need to use the alumina insulators I got. (and I must say, I'm quite proud of the funky design of it)

author: uer166
author_rank: Super Contributor
timestamp: November 30, 2020, 11:57:20 pm
content: You'd usually want individual gate resistors to avoid oscillation between the gates due to small differences in capacitance/inductance.Active miller clamp seems unnecessary and might complicate timing.I don't see a disable pin on the gate driver that would be handy for:The overcurrent protection/sensor in the FET current path which also seems to missEdit1: D1/D2 seems unnecessary, you already have 2 sets of body diodes to clamp to bus. If those are not enough, the FETs are much too undersized.I think you will see very similar random failures with this new design based on lack of hardware overcurrent protection, effort into that would pay off quickly IMO.

author: Powermax
author_rank: Regular Contributor
timestamp: December 01, 2020, 01:44:23 am
content: I will implement current limit also, but the PCB is just the H bridge driver stage, the part that is fairly static and unlikely to change in my design moving forward.Thanks for the suggestion to use separate gate resistors, I kinda suspected that but for getting to fit in the smallest area possible I omitted that and TVS clamp diodes. (I did several iterations ago have problems with gate being punctured) I might hack in this resistor as a matter of course on the next revision. (this board has been submitted for manufacture).D1/D2 are redundant, and now the FET's are closer together it probably isn't as important. But before, when there was a non-negligible inductance between the Lo and Hi side FET, the diode and MLCC cap ensures the local FET Vds is clamped, with the minimum current loop area achievable. Even with all that, I still see overshoots in excess of 5V when I was running it off isolated DC supply.