Precision voltage divider on LTspice group - Page 1
Forum section: electronics / general

author: IconicPCB
author_rank: Super Contributor
timestamp: May 13, 2020, 01:35:26 am
content: Just ran across an interesting discussion. Precision Voltage Divide: "...After attempting to locate models for some CD4000 logic we've decided to quickly try and create something that would show the MOS output effects as well as the resistor tolerance effects on a voltage divider based upon a CMOS FF. No serious effort has been applied, and LTspice was run with default parameters.The files have been uploaded as well as a few photos of the output results.The general idea, which was patented long ago (5030848) and won EDN Design Idea of the Year back somewhere in the 80s, is to use an ordinary CMOS Flip-Flop as a Voltage Divider, as well as the usual frequency divider. By using just two unmatched resistors, and a capacitor, with a CMOS FF it's possible to achieve ppm levels of precision almost independent of the resistor divider values. The resistors R1 and R2 are connected to the FF Q and Qbar outputs, and the capacitor C shunts the other resistors ends which are connected together, and called Vout. Neglecting FF timing and output characteristics Vout = Vdd(R2/(R1 +R2))/2, then on the next clock Vout = Vdd(R1/(R1 + R2))/2, C averages the result to precisely Vdd/2 independent of R1 or R2. The output characteristics of the FF have a small effect, as does the timing. If R1 and R2 are >> than the output Rp and Rn values (NMOS & PMOS Ron), then Rp and Rn have little effect, if the clock period is much longer than any FF timing skew (which causes duty cycle to slightly deviate from ideal 50%), then this has little effect. Interestingly a little circuit analysis shows the result with Rp and Rn included, Vout = (Vdd/2)( R1 + R2 +2Rn)/(R1 + R2 + Rn +Rp), thus is Rn= Rp then again Vout = Vdd/2.Separate MOS fets were employed to help model the output effects, a standard model FF was used and scaled to 10 volts with two VCVS for Q and Qbar. Additional RC filter (R5 & C2) was added to help average the output fro display. Simulations were done using replica circuits, that used R1 = R2 = 100K, R1 & R2 differ by 1%, then 10% and finally by -50%. The results show the voltages converging to the anticipated Vdd/2 or 5.00000 volts. Another run was done with all equal resistors at 100K (0% error) but varying the output MOS fet Ron from ~6 ohms, to 1 ohm, 0.1 ohm and 10m ohm. The fets and FF were just models available from the standard LTspice library, so nothing special...."

author: David Hess
author_rank: Super Contributor
timestamp: May 13, 2020, 03:18:50 pm
content: The simpler alternative is a capacitive charge pump like with the LTC1043 which has no dependence on output filtering or duty cycle.

author: Magnificent Bastard
author_rank: Regular Contributor
timestamp: May 13, 2020, 03:22:14 pm
content: Quote from: IconicPCB on May 13, 2020, 01:35:26 amCould you please provide a link to the "LTspice Group" thread (since there are MANY groups with many threads).

author: notfaded1
author_rank: Frequent Contributor
timestamp: May 13, 2020, 07:04:23 pm
content: He may be talking about:https://groups.io/g/LTspice/Bill

author: Andreas
author_rank: Super Contributor
timestamp: May 13, 2020, 07:28:21 pm
content: Hello,although the idea is good,Quote from: IconicPCB on May 13, 2020, 01:35:26 ampractically this will never happen.At 10V VDD Rp and Rn are around 250 Ohms. Even if according to the data sheet they are kept equal due to process variations a difference of 10-30% is very likely. so ~50 Ohms difference.R1 and R2 are unlikely much above 100k (otherwise the leakage of the capacitor and the input bias current of the following chopper amplifier will create larger errors) so we have a relation of 50 Ohms error (difference) to 100K giving around 500 ppm.And the resistance is also temperature dependant. (Factor 2 increase for 100 deg C temperature increase).The output boosters create probably larger charge injection (is this modeled in LTSPICE too ?)I for my part will prefer the LTC1043 which has a much lower output impedance (~1K) and specified charge injection.with best regardsAndreas

author: David Hess
author_rank: Super Contributor
timestamp: May 13, 2020, 09:37:03 pm
content: The same result is produced if a single output drives an RC filter. The improvement from using both outputs to drive a divider comes from less output ripple which depends on the matching of the resistance.An LTC1043 only has to deal with charge injection and leakage.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 14, 2020, 09:31:49 am
content: The error due to charge injection, leakage and parasitic capacitance is large enough that one does not get an accurate 1:2 divider, just a very stable one close to 50% with maybe some offset.Swapping the sides of the resistive divider should be closer to the ideal 50% ratio, but the switch resistance is a real problem and depending on the implementation the resistance would change with voltage. For a not too high voltage one could consider using extra switches to carry the current. This could reduce the effect of the switch resistance by something like a factor of 100, at the price of more circuit and extra switches for a higher voltage.There are switches with a lower resistance than 250 Ohms, if one does not directly used the flipflops. This increases the effort, but seem feasible.As there is little ripple, the switching frequency can be rather low.

author: David Hess
author_rank: Super Contributor
timestamp: May 14, 2020, 03:44:39 pm
content: But the LTC1043 output is not influence by duty cycle or switch resistance.I wonder though how improvement could be made over the performance of an LTC1043 implementation which we already know is in the single ppm range. The LTC1043 already implements cancellation of charge injection internally.

author: mawyatt
author_rank: Super Contributor
timestamp: November 05, 2022, 09:36:09 pm
content: "Just ran across an interesting discussion. Precision Voltage Divide"That was us, didn't see this until now, sorry for the late reply. This was our prior work from way back in the late 70s and into the 80s.To answer a couple comments:"The simpler alternative is a capacitive charge pump like with the LTC1043 which has no dependence on output filtering or duty cycle."Our original work preceded the founding of Linear Technology, and the Flying Capacitor had it's own special issues like requiring two large external capacitors, dielectric absorption, leakage and was much more complex "inside" the chip (charge balancing and such) than a simply couple resistors, buffers and FF. Neither solution was prefect tho, but better than those large and expensive Vishay resistors. We used these Flying Caps when they became available later around ~80 for synchronous demods tho, they worked very well in this application."practically this will never happen.At 10V VDD Rp and Rn are around 250 Ohms. Even if according to the data sheet they are kept equal due to process variations a difference of 10-30% is very likely. so ~50 Ohms difference."It did happen and worked quite well indeed, we used this technique many decades ago and even in some custom CMOS chips!!The higher voltage CD buffered logic is rather high output Z, but paralleling up buffers or using discrete P and NMOS devices really helps with Rds ON effects. Take a look at the old 74AC logic for lower under 6 volt use, it's output Ron is around 20 ohms, parallel a couple of these buffers up and you are under 10 ohms, then add a single series low value R with the CMOS VSS to ground to help match the Rds ON of the P and NMOS devices, makes it very easy to achieve almost perfect divide by 2. I'm sure there are many very low output Z CMOS drivers that could be employed.Don't know the long term drift effects but haven't heard any issues of the stuff designed back in the 70s and 80s with these techniques, and other analog type CMOS use (we started using the very early RCA CD4000 series CMOS for all sorts of analog use back then, for lower voltage we used the 74HC and AC CMOS for analog use.Anyway, sorry for not spotting this thread earlier.Best,

author: Andreas
author_rank: Super Contributor
timestamp: November 06, 2022, 05:48:41 pm
content: Quote from: mawyatt on November 05, 2022, 09:36:09 pmDo you have some numbers?at least over Temperature?for the LTC1043 over room temperature +/- 15 deg C it is mainly only the offset drift of the following buffer amplifier.https://www.eevblog.com/forum/metrology/t-c-measurements-on-precision-resistors/msg528192/#msg528192with best regardsAndreas

author: mawyatt
author_rank: Super Contributor
timestamp: November 06, 2022, 06:24:41 pm
content: Quote from: Andreas on November 06, 2022, 05:48:41 pmThat was over 40 years ago, recall it held up well over the military temp range for what we utilized these circuits for. We even used this concept within custom chips with on-chip SiCr resistors and custom CMOS back then. When we developed the first capacitive ratioed DACs and ADCs (used capacitive DACs in SAR ADC), we soon abandoned any resistive approaches, and much later were allowed to publish and patent the concept. Much of our early career leaking information (publishing) was forbidden (for obvious reasons on the projects we worked), and much later were allowed to publish some limited information. Please remember here in US, filing for a patent becomes public domain, so one must weight the effects of filing vs. just keeping the information secured.Anyway, if someone (hint, you guys with those nice HP3458s) was really interested it shouldn't be difficult to construct a prototype and let in run for a year or so. Wager that the results will be quite good over time!!Best,

author: Andreas
author_rank: Super Contributor
timestamp: November 06, 2022, 06:42:15 pm
content: Hello,I think that the cirquit behaves well over time. (similar to LTC1043)I have more concerns over temperature and clock frequency variations.Do you remember the typical clock frequencies used? more like 1 kHz or more near 100 kHz?with best regardsAndreas

author: Kleinstein
author_rank: Super Contributor
timestamp: November 06, 2022, 07:02:36 pm
content: The 2 resistor and FF circuit usually does not need a high clock frequency. The residual AC amplitude is rather small, depending on the resistor mismatch. So while there is not much direct effect on the DC, it can still pay off to start with relatively equal resistors. The frequency depends on the filter used. So 1 kHz looks reasonable.The LTC1043 circuit should not care very much about dielectric absortion, but parasitic capacitance can have an effect. 1 ppm of 1 µF is only 1 pF. The good thing is that the parasitic capacitance is usually also resonable stable.

author: mawyatt
author_rank: Super Contributor
timestamp: November 06, 2022, 07:08:34 pm
content: Recall we used low clocks, probably 1KHz, 100Hz or lower. One detailed source of error is the asymmetry of the resistor switching, which with a small differential resistor error can contribute to the output error. Another is the difference in switching edge details as the CMOS switch transitions from one state to the other. Both of these error sources improve with a slower clock where the period to edge time is very large.We don't have a proper lab here (partly in an open room), where things move around, large temperature and humidity shifts, people walking round, active WiFi near by, cell phones and so on. So attempting any kind of serious measurement over time is not practical.Getting a low Rds ON pair of FETs for a discrete inverter is the best means to reduce the effects of switch resistance. One could even do this with mechanical switches as mentioned if desired, but doesn't seem like a practical use (switch fatigue and so on) vs. a solid state solution.Anyway, hope this helps.Best,

author: mawyatt
author_rank: Super Contributor
timestamp: November 06, 2022, 08:39:19 pm
content: Just pulled up our old DMM test circuit that we used to get a quick look at DC, and AC rms values. This uses a CMOS divider chain (CD4060) from a 8MHz crystal with a pair of P and NMOS discrete FETs (BSS84 & 2N7002) as a buffer to chop up a 5 volt reference (ADR4550) with ~50% duty cycle. This has been running 100% on the time for the past few years, and just took a quick measurement of the 5 volt reference and the divide by two buffered output which is a squarewave of 0 to 5 volts. We LPF the buffer with a 100K and 10uF film cap, before making the measurement.Using our new KS3465A we get:5.0002412VDC and 2.5001231VDC for the squarewave which is about 1ppm of ideal 1/2.Anyway, this doesn't prove much other than the CMOS analog switching seems to hold up well and shouldn't be discarded as an option for various uses. This is exactly why we began using CMOS type logic for many analog functions back when RCA first introduced the CD4000 logic family. Fondly recall some very knowledgable special "customers" asking why we had all this CMOS logic scattered around in the precision analog sections of our designsBest,

author: Kleinstein
author_rank: Super Contributor
timestamp: November 06, 2022, 09:15:56 pm
content: CMOS logic can do quite some analog magic. Even some meters use them: the HP3456 uses some MC14049 for ref. switching in the ADC. The 3458 uses some HC14 for the fine slopes in the ADC. The 34401 and Fluke 8845 use 74HC4053 in the ADC.If really needed, one can do an approximate correction of the switch resistance with a 2 nd set of switches that provide most of the current from a higher (like 1.5 times) voltage. Fluke does this in the many of there calibrators.

author: PartialDischarge
author_rank: Super Contributor
timestamp: November 07, 2022, 08:33:01 am
content: This reminds me of the ADvantest TR6142 DC voltage source which used a PWM scheme, top left portion of the circuit: