modern TTL/Logic-gate/74xx - Page 1
Forum section: electronics / beginners

author: ker2x
author_rank: Regular Contributor
timestamp: October 07, 2019, 04:50:42 pm
content: Friendly greetings !I'm a beginner with hardware project (my last circuit board was 30 years ago), and "slightly" obsessed with CPU design, Compiler design, OS development, ... (well, i'm an IT engineer).I'm currently designing, in software, my own cpu, emulator, os, assembler, BASIC. (in fortran, because that's how i roll (i may switch to C/C++/C# for the compiler)).of course i want to do it in hardware too, because why not ? (well, that would require to switch to a 8 bit CPU but i don't mind).I played with FPGA, but it's too much of a pain, i just don't get it. (beside, VHDL look like ADA and i have a massive PTSD with ADA.)I will, of course, implement the design in logisim first, then on a circuit board emulator, then, hopefully, in hardware.And i totally want to design the PCB, it will be 99% of the fun for me.However, i checked a lot of video, tutorials, sources, etc... and it's all good old 74xx, massive chips with 2 or 4 gates.Are there modern highly integrated surface mounted TTL chips ? (with dozens of gate per chips)I don't want to solder it, i'll just send the files to a PCB Prototyping Company (JLCPCB & co) so SMT is the way to go (much cheaper, right ?).Is there a list ? a reference website ? a reliable source ? I want at least a rough idea of the kind of chipset i can use, read the datasheets, etc.I'll design the cpu based on the available hardware (i also have a 32 bits design in progress but it will be 100% emulated in software and pretty much impossible to replicate in hardware (eg: complex number ALU))I'm super early in the process, i'm just exploring the whole stuff in order to get the idea of what's ahead. Thanks to eevblog i have a rough idea of how difficult it is to complete a full project.I considered, since many years, to do easier projects but there are no other project that interest me. Believe me, i tried. But nope, CPU or bust !I may do a "modular" CPU just so i can create multiple PCB and if i fail i'll just have to redesign a single PCB (with less chips) instead of the probably expensive full CPU for every countless mistake i'll make.Thank you !Super important PS :- It's useless to tell me to give up, even if you're 100% sure that i'll fail : just let me enjoy the process and the magic smoke. i'll still learn anyway.- When i write "cpu" : it will be a working computer. But i'll just use whatever microcontroller available for the non-cpu part of the computer (eg : a pic board, arduino, raspberry pi, or even an fpga with an soft-cpu ip core... anything easily programmable with serial<->usb communication and enough I/O). And it will be easier that way to test the "sub-pcb" piece by piece (i do have an oscilloscope and logic analyzer if needed)

author: oPossum
author_rank: Super Contributor
timestamp: October 07, 2019, 04:58:44 pm
content: Quote from: ker2x on October 07, 2019, 04:50:42 pmI think this is as close as you will get to that...https://www.microchip.com/ParamChartSearch/chart.aspx?branchID=30024

author: ker2x
author_rank: Regular Contributor
timestamp: October 07, 2019, 05:09:15 pm
content: I'll just add some bonus question here :Thanks to my painful experience with FPGA i have a rough idea of the importance and difficulty of timing.I'm planning to have massive safety margin and make the cpu run super slowly, i'll be happy with a few KHz (or is it too much already ?)And thanks to the multi-board design it will have absurdly long trace (and potentially EM sensitive wire too) so high clock speed (1+ Mhz) is probably impossible anywayBonus question N°1 : But being slow come with problems too, it seems. how slow can it be ?The only thing i know is that some type of ram need to be refreshed and that's it.I have ZERO idea of the potential problems that can come with a slow clock.So any random tought about it are much welcome.Bonus question N°2 : Can i just use my whatever-glue-microcontroller to handle the clock ? (Since i'll have one for sure to emulate the non-cpu part of the computer)Bonus question N°3 : the memory isn't technically part of the CPU (except the registers), should i use, by design, an hardware memory chip or let the microcontroller emulate it ?thank you, twice. (i don't know how to say 3x in english, sorry, thrice ?)

author: ker2x
author_rank: Regular Contributor
timestamp: October 07, 2019, 05:12:21 pm
content: Quote from: oPossum on October 07, 2019, 04:58:44 pmThank you for the quick reply. But it's a list of PLD chips, it's even worse than FPGA in my book.There is now way around it ? i have to use either very low density 74xx OR a PLD/FPGA ? Nothing in-between ?EDIT : i might be too harsh with the CPLD, there isn't anything worse than an FPGA.

author: magic
author_rank: Super Contributor
timestamp: October 07, 2019, 05:18:34 pm
content: There are some more complex 74 series ICs like complete flip-flops, multiplexers, decoders. I have even seen some vintage 74-something ALU-on-chip. Wikipedia has a list of hundreds of 74 series parts, but beware that many are unobtaininum and/or have never been made in CMOS.

author: schmitt trigger
author_rank: Super Contributor
timestamp: October 07, 2019, 05:39:28 pm
content: You will find 74HCxx series of chips in SMT format, although some of the more obscure functions are no longer supported.Designing a simple microcontroller with 74HC chips is doable. Many years ago, an acquaintance of mine actually built one, although it goes without saying, it was very rudimentary.He actually had a lot of fun doing it, and gained a lot of respect for the people who actually design microcontrollers

author: ker2x
author_rank: Regular Contributor
timestamp: October 07, 2019, 05:50:56 pm
content: By the way, the "modular" cpu idea come from the MegaProcessor :

author: ker2x
author_rank: Regular Contributor
timestamp: October 07, 2019, 06:12:58 pm
content: Quote from: magic on October 07, 2019, 05:18:34 pmYeah, i don't want it to be "retro" 74xx. Expensive, unavailable, won't be able to have a PCB company populate the board with their machine.That's why i'm looking for modern gate chips.I checked mouser.fr for logic gate and found tons and tons of stuff :https://www.mouser.fr/Semiconductors/Integrated-Circuits-ICs/Logic-ICs/Logic-Gates/_/N-6j787But a beginner like me would have to reads hundred and hundreds of datasheets in order to find something that look like something i want.Of course i'll have to read many datasheets for fine picking the exact parts but just this website give me 4875 results for "logic gate" and it's just too overwhelming.I may end up looking at something totally overkill, or much more expensive that it should, or super specialized that won't even work on my loose tolerance design... and not even notice the fine print that tell me that there is no way it will works on my project.

author: ker2x
author_rank: Regular Contributor
timestamp: October 07, 2019, 06:37:14 pm
content: My last hope would be to use an EEPROM, it totally works and it's 100% available. But a totally different design and project.This is why i need to consider the hardware first.Sorry, i'll stop spamming now. It's evening and a bit tired after a full day of database nightmare. ("What are you talking about ? this server was trashed a long time ago" "mmm, nope, i'm logged in and it appears it ran flawlessly since 2009 until now")

author: magic
author_rank: Super Contributor
timestamp: October 07, 2019, 06:39:15 pm
content: The one chip ALU you can probably forget, but many 74 series stuff is still being made, no problem. I think Mouser has the ability to restrict search to particular families like 74HC so you could see what's available using Wikipedia as quick part number decoder. FFs, counters, decoders, muxes, buffers you will get for sure and that alone may reduce component count quite a bit compared to bare logic gates.

author: ker2x
author_rank: Regular Contributor
timestamp: October 07, 2019, 06:54:34 pm
content: Quote from: magic on October 07, 2019, 06:39:15 pmHa thank you ! I tried to restrict to "74" and "SMD/SMC", expecting to have the full 74xx range but it only returned 10 result and all of them were diode.Yeah, i don't want to buy an ALU, it would defeat the purpose of the project. If i just wanted a cpu i could just buy one for much cheaper than building one with logic gateI see some toshiba part... didn't they go bankrupt decades ago ?Nexperia seems to be specialized in automotive so i'll probably forget about it.SMT do some parts.Most chips seems to come from "ON Semiconductor" so i'll just go with that. i guess ? And they provide the ECAD Model, which is a must have.

author: rstofer
author_rank: Super Contributor
timestamp: October 07, 2019, 07:36:19 pm
content: Search the Internet for 'LC-3' a very nice RISC design that isn't necessarily implemented in hardware but the project does include the microcode worksheet and a full-blown transition diagram. There is a related book by Patt and Patel that describes everything you need to know about logic and system design. The project comes with a C compiler and an assembler.https://www.amazon.com/Introduction-Computing-Systems-Gates-Beyond/dp/0072467509There is also a newer version of LC-3 known as LC-3b which is based on byte addressing instead of 16 bit word addressing.Here is some documentation on the LC-3b project:http://users.ece.utexas.edu/~patt/05f.360N/handouts/360n.appC.pdfSimilar documents are out on the web for the original LC-3 project.When you block out your TTL, count the number of wire-wraps. Heck, just count the number for a 16 bit register and then realize that I can declare such a register with one line of code and manipulate it in a small 'process' for things like load and clear. I can even do an add '1' in case I am implementing the Program Counter. Maybe 10 lines of code...The LC-3 CPU state machine uses 1000 lines of VHDL plus another 400 for things like registers and memory while the UART and Baud Rate Generator add another 400 or so. So, for about 2000 lines of code I didn't have to wire-wrap a single device. I didn't need to buy chips and sockets, all I needed was an FPGA board.Now, I went all-in on the FPGA board because I like peripherals like 7 segment displays, LEDs, switches and buttons. But that's just me!https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/In theory, I could add enough hardware to include networking but that's a little above my skill level. At a minimum, I would be using a LOT of Xilinx IP to do such a thing.Duplicating the LC-3 project is probably not interesting to you as you have your own design concepts. But the thing is, when you hit a design wall, it's pretty cheap to rip out VHDL and do it over. Not so simple with wire-wrap. HINT: Write a program that has some kind of datastructure for your netlist. The idea is to print out a wire-wrap list by level that will put the wire ends on the same level. There would usually be just a first level list and a second level list. You would do this because it is easier to disassemble. At most, you remove 3 wires. If you wrapped the wire as a daisy chain, you could possibly have to remove the entire chain to make one little fix.I took an IBM 1130 and all of its peripherals and stuffed it into an FPGA about the size of a postage stamp. It runs all of the factory software, unchanged. And it runs at 50 MHz instead of 400 kHz and if I wanted to spend a little more time on the project, it would probably run at 100 MHz It's about 10,000 lines of code as I recall but there is a lot of code tied up in the line printer, card reader, bouncing ball typewriter, keyboard, disk subsystem, DMA system and, of course, the 1627 drum plotter. FPGAs are amazing! So was the 1130 when I was wandering through undergrad:http://ibm1130.org/Of course I'm going to champion FPGAs! It's like having a dumpster full of logic just waiting for a design.Typical transition schedule for FPGAs: Blink an LED then build a CPU. Not much in the middle...

author: edavid
author_rank: Super Contributor
timestamp: October 07, 2019, 07:46:33 pm
content: Your questions are really confusing.1. There are still many standard logic ICs available in various CMOS versions. For a good introduction, see the TI website:http://www.ti.com/logic-circuit/support-training.html2. There are many homebrew CPUs built out of MSI logic ICs instead of simple gates. For examples see:https://www.homebrewcpuring.org/3. There is indeed a big difference between CPLDs and FPGAs: CPLDs can be programmed via schematic capture. So even if you don't want to learn an HDL, you could still consider CPLDs.4. If you just hate VHDL, you should look at Verilog, which is not Ada like.

author: magic
author_rank: Super Contributor
timestamp: October 07, 2019, 07:55:26 pm
content: I did say: 74HCOr maybe 74LVC, that's a newer one.

author: rstofer
author_rank: Super Contributor
timestamp: October 07, 2019, 07:56:56 pm
content: Another fun way to design CPUs is with microcoded design and the old AM2900 series logic. There are still AM2901 (4 bit slice) on eBay for reasonable prices. It would take a bit of research to find all the proper chips but there aren't many different devices in the family Plus you need some kind of flash for the microcode. Full-on EPROM might be a little prohibitive in the early stages. I took a class on these devices many years ago and we designed an 8086 replacement without too much difficulty.The standard text is "Bit Slice Microprocessor Design" by Mick and Brickhttps://www.alibris.com/booksearch?keyword=bit+slice+microprocessor+designExtra credit for writing a meta-assembler for defining the microcode and filling in the very wide ROM word. Usually, every control signal, anywhere in the machine, has a bit position in the microcode word. That's why they get very wide, very fast.Note that the LC-3 project I referenced above uses a microcoded design and the word is about 35 bits wide. Pretty narrow as microcode goes.Even if you use discrete logic, I would still recommend a microcoded control unit. It is so much easier to make changes (and additions) when the only thing that changes is some bit in a word.

author: rstofer
author_rank: Super Contributor
timestamp: October 07, 2019, 08:13:42 pm
content: Quote from: edavid on October 07, 2019, 07:46:33 pmA strongly typed language, like VHDL, seems very helpful for newcomers. If the code compiles, there is a good chance the hardware will run. It isn't always true but it is true more often than not. If the code doesn't work and there is a finite state machine involved, I am willing to bet that one of the output signals doesn't have a default value. There are many painful reasons that I know this! If there is even a hint that a latch has been created, there is an error in the code. Pretty simple rule: No latches allowed!I have made several half-hearted attempts to understand Verilog and I just haven't caught on. Of course, given that I know a bit about VHDL, I don't need to know anything about Verilog for my hobby projects.What's to know? You need to be able to write an equation for combinatorial logic. Then add in a MUX and Demux, again combinatorial. Add in a clocked register and use it as a counter. Make a more complicated register process that accepts command inputs to load, clear or add 1. Don't forget a NOP command because the register will be clocked on every rising edge but is not expected to change just willy-nilly. This is a very useful construct for a program counter.Now the big one: Learn how to code a finite state machine including default values. That's really about it. Of course, the devil's in connecting these primitive gadgets together to make something useful. But, really, there are only a few constructs used over and over. Get it right once and then copy-and-paste (conceptually).Really, once you have an FSA working, the rest is just details. Some FSAs will be quite lengthy (like the LC-3 project, 64 states, some unused) others will have just a few states. But the code is the same! You have a clocked 'next state' process and a combinatorial process where the work gets done. I don't prefer the single clocked process model for an FSA.Find a project, see how it is coded and then just copy-and-paste! It just isn't that difficult. Get something to work and keep expanding.OpenCores.org has a lot of projects. Some simple, some complex. Download something and look at it.

author: ledtester
author_rank: Super Contributor
timestamp: October 08, 2019, 02:53:19 am
content: You can also just use EPROMS:

author: hamster_nz
author_rank: Super Contributor
timestamp: October 08, 2019, 03:40:30 am
content: If I was to descend into such madness it would be with a reel of 74AHC1G79 and 74AHC1G00 (about US$0.10 and US$0.07 each in qty 1,000), on two layer boards.Would probably do 95mm x 95mm PCBs (if I could find a suitable way to mount them) to keep PCB costs down. I would have a generic PCB with footprints but flying wires for prototyping, and as design settles down / is tested then move to custom PCBs. The PCBs would always have a few spare footprints for bodges, of course.Have no idea how I would do a backplane. A generic PCB design to hold connectors and supply power, and then use point-to-point wiring?https://assets.nexperia.com/documents/data-sheet/74AHC_AHCT1G79.pdfhttps://assets.nexperia.com/documents/data-sheet/74AHC_AHCT1G00.pdf... however, you can bet that I would use a S/W tool to simulate everything first, and then possibly layout the PCBs, or at least generate a netlist file for KiCad.And go full agile with a CD/CI pipeline..

author: ker2x
author_rank: Regular Contributor
timestamp: October 08, 2019, 05:59:58 am
content: Thank you all for the answers !@hamster_nz : While it's technically possible to use only NAND gate, i will not descend that deep into madness. I'm planning to use all kind of gates. About agile, i wasn't aware that it was also a thing in electronic, i'll take a look.@ledtester : yes, i did mention using eeprom (but it would be a totally different project that originally planned)@rstofer : i don't want to use FPGA for this. i may end up using one, but if i do it will be for the non-cpu part of the computer. and my original plan is to use a microcontroller for this, not an FPGA.@rstofer : i never heard about AM2900. But it seems to be very old. I want to use part that are still in production and usable by a PCB company for their pick & place machine.@magic : sorry, my answer was a bit confusing and forgot to mention that i did indeed understood that you wrote "74HC", i'll take a look at LVC too.@edavid : yes, i know this webring, i love it. I'll take a look again at CPLD. For me it was just an underpowered cheaper FPGA but it looks like i misunderstood.@rstofer : yes, i have a few books. i have a scan of "digital computer electronics" (it's a 70's book). I'll take a look at the other book you suggested. I don't know about the ibm 1130. But i'm a big fan of the IBM 7090, i have a the emulator installed and i wrote some Fortran II code for it. I *almost* considered rewriting an emulator for it but gave up on the idea since i already have a working emulator (in Delphi ...) so i gave up on the idea. It's such a massive beast ... And everything is in BCD, not a big fan.

author: james_s
author_rank: Super Contributor
timestamp: October 08, 2019, 06:07:11 am
content: If you don't like VHDL you could try the other popular HDL, Verilog. I'm not aware of much in the way of complex logic chips that are around anymore, 74xx is still handy now and then for a few gates or a counter but for anything more complex everyone just uses CPLDs or FPGAs. I started doing FPGA development several years ago and while it took me a while to get over the initial learning curve I don't find it all that hard now. The difficult part is designing the logic, describing it in VHDL is straightforward.

author: ker2x
author_rank: Regular Contributor
timestamp: October 08, 2019, 06:41:40 am
content: I'll address this whole FPGA issue :I could do it if i really wanted to and *had* to do it. I write fortran (and other languages) as a hobby. I write SQL as part of my job. I obviously can do ASM too. (since i'm designing a cpu and emulator in software).I could do VHDL/Verilog. i just don't want to, don't wanna, nope, no way, eww, poop.Doing it with an FPGA would be like writing a emulator in a language i hate. And i'm already busy writing one in a language i love.And how am i supposed to fail in electronic if all i have to do is to buy an FPGA dev board and write code ?It's not 100% out of the way. I may end up using one despite my best effort to avoid it. But if i do :- it will be for the non-cpu part of the computer- it will be because using a microcontroller for the non-cpu part of the computer didn't work the way i expected for unforeseeable reasons.- it will be because i couldn't test a submodule of the cpu with the microcontroller.- it will be because i want to. As of today : i don't.I will take a look at (C)PLD however, because i apparently misunderstood what it was.Later, because i just watched the clock and i was supposed to be at work 12mn ago. oops.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 08, 2019, 06:55:27 am
content: The agile snark was a bit of a joke... Everything is going 'agile' .But it could actually be possible to do, as you will have quite a few mundane tasks that could be automated along the way from design to hardware.

author: rstofer
author_rank: Super Contributor
timestamp: October 08, 2019, 03:26:44 pm
content: There's another way to architect an FPGA CPU that is almost never seen in the wild: Build up a library of 74xx(x) blocks. Then 'wire' the blocks together just like you would do it on a wire-wrap board. Build modules for 7400, 7402, 7404, 7408, 7474, 74181, 74182 and all the others that come up. This is a terrific way to use logic chips as the design elements rather than more conventional FSAs and the other constructs. It would be a very interesting design! Elegant and unique!You can design the 74181 block in behavioral code (specify the inputs, outputs and function) or model it with lower level logic chips from the datasheet block diagram. I might do that in a later pass but behavioral code would be my first choice. But it would be as simple as substituting one file for another and recompiling to change to the more detailed design.I would still lay out a microcode word and use microcode for the control unit. Among other things, the typical large FSA isn't needed and although we know that, in the end, the FSA will look a lot like a microcoded solution, one big difference is that the FSA will probably use 'one-hot' encoding so an FSA with 100 states will have a 'state' and 'next_state' vector width of 100 bits. We don't want that for our microcode word width so many fields will be encoded like MUX select bits. Three bits select 1 of 8 mutually exclusive values rather than having 8 signals going to AND gates.In real hardware, it is common to use tri-state bus drivers to send signals from registers to some bus. This doesn't tend to work very well for FPGAs so we have to implement MUXes. Turns out the synthesis tool will do that by magic if you try to define tri-state drivers.Everything that needs to happen and the sequence of events is contained in microcode.Not too many people remember but IBM invented the 8" floppy. Why? To load the microcode for the IBM360.https://en.wikipedia.org/wiki/History_of_the_floppy_diskFor the meta-assembler, and you would probably need one, you define a word width. Then you define 'fields' within the word (or define the word as a collection of fields). Perhaps 3 bits are allocated to the selection input to an 8 input MUX, something like that. Further, you define default values for each field so that each line of microcode doesn't have to define every field, many of which are not involved with the current operation.Each line of 'code' defines values for the fields at a particular memory location in the microcode. Extra credit for macros. Maybe use the C preprocessor? There's a simple Python program in here, screaming to get out! But, really, it simply MUST be written in Fortran. Characters and strings are such a PITA for Fortran! We had to rewrite IBM's Commercial Subroutine Package for the IBM1130 to get some speed out of business applications, circa 1970, and the main thrust was string manipulation.In the end, you wind up defining every bit in every word in the microcode store.Now, the microcode wants to be alterable and not totally compiled in to the VHDL.Hit up hamster_nzfor his code on reading BlockRAM values from a hex file during the Implementation phase rather than way back at Synthesis. I don't recall where I found it but I used it for my LC-3 project.Extra credit if you use an SD card to hold the microcode and can come up with a simple way to read the file during boot. Heck, IBM did it way back in the late '60s.ETA: Once you have the FPGA version working, it would be pretty trivial to use the same blocks to design/build real hardware. Think of the FPGA as a high end simulation.

author: rstofer
author_rank: Super Contributor
timestamp: October 08, 2019, 04:08:41 pm
content: Quote from: ker2x on October 08, 2019, 06:41:40 amIt is common for programmers of procedural code to look at Verilog and VHDL as just another language. It is, and it isn't. Yes, they are both languages but... They're describing hardware, massively parallel hardware!Eventually the programmers come to realize that every single line of code in a 10,000 line project is executing in parallel. Signals 3 levels deeper are still changing state, massive things are happening on each clock pulse. Just handing data off from one module to another has timing implications if the processes are clocked (one clock delay is typical, sometimes 2 if crossing a clock domain). It is up to the designer to keep track of the timing of every signal in the design. In bits and pieces, true, but everything is happening in parallel.There is nothing in the world of procedural code that comes anywhere near to being as massively parallel as writing in an HDL. What ? A CPU has 4 cores and 2 threads per core? 8 things going on at a time? That's trivial! In HDL I can have thousands of independent processes all running in parallel, happily moving information from place to place. Got FreeRTOS running? Great! But it's still just serializing.Hardware design is the ultimate game! But sometimes it just isn't practical to build things with discrete chips. My personal limit for wire-wrapping is about 100 chips, a very modest CPU depending on how the registers are implemented. That's a LOT of chips but beyond that point my attention span falters. My scratched out logic designs just aren't formal enough. Documentation becomes more important than wire-wrap and it becomes more work than play.

author: ker2x
author_rank: Regular Contributor
timestamp: October 08, 2019, 04:11:26 pm
content: FPGA again ?... ok, ok. you guys win, i'll consider it.And i kinda like the idea of implementing the whole serie of 74xx, just for the fun of it.Even if i'm not really sure if it make sense, but common sense doesn't matter in this kind of projectI think i need a drink. cheers !

author: ker2x
author_rank: Regular Contributor
timestamp: October 08, 2019, 04:18:44 pm
content: Quote from: rstofer on October 08, 2019, 04:08:41 pmI'm aware, that's what got me interested in FPGA in the past, years ago, until i realized it wasn't fun at allI'm a big fan of developing using pipelines, with one threads per pipeline. But still, it's much different than coding FPGA for sure.The learning curve of fpga remind me of this meme :https://aws1.discourse-cdn.com/eveonline/original/2X/9/9a395dad41a3cccfecd1346e6bc4aa48beb14442.jpg

author: rstofer
author_rank: Super Contributor
timestamp: October 08, 2019, 05:41:41 pm
content: Of course I like hardware, that was my major in grad school back in '75..'76, when the 8080 was king.One of the problems I have with learning new skills is that unless I have a project with an end goal, I won't stick with it. I have tried several video series on C++ and Python and I get into it for a short while but burn out quickly. The reason is two-fold: First, I don't have an immediate need for the skill and, more important, the tutorials tell me what to do and how to do it but they don't tell me why I would want to do it. Just because everything is an object, why should I code THIS project using THAT process when I can just do it in C or Fortran?I would imagine that learning an HDL would be the same kind of thing. Unless there is an immediate goal and adequate tutorials, why bother? Frankly, it would be boring.How about one last experiment before trashing HDLs forever? Use Vivado to create a 74181 (and, for extra credit, a 74182 carry generator). That's all. Keep it simple, just 4 bits wide. Now run the simulator (which I have never used) and see if it will do all the operations required. I have no idea how to create the test bench that provides inputs to the device but from what I have seen, it doesn't look hard. Somebody around here can help with that.Since this is just combinatorial logic, I would just use toggle switches for the inputs and LEDs for the output.I could choose to write the code using the logic diagrams on the Internet or just use a CASE statement. Likely I would use a CASE statement based on the M input and under each branch, I would have a CASE statement for each of the 16 functions. I might break up the Arithmetic CASE statement into two further CASEs based on the Carry input. That would make the function quite clear.http://www.righto.com/2017/03/inside-vintage-74181-alu-chip-how-it.htmlHere's a defined goal - get an ALU to work! Once done, this is the most logically complex part of a CPU and it works!

author: schratterulrich
author_rank: Regular Contributor
timestamp: October 08, 2019, 06:11:47 pm
content: Hello ker2x,if you decide to build your project with discrete logic, you should really think carefully about which logic family you are using.We have used LVC logic in the past to buffer a parallel RGB display interface for example. It was a typical case for unnecessarily fast logic with all the drawbacks. We used series termination resistors on all nets and of course impedance defined traces. But as we had to route the bus thru a ribbon cable we caught some EMC radiation problems.Finally we had to redesign the board due to EMC issues.We then investigated different logic families and decided to use the 74AUP family. We could eliminate the series termination resistors and got very clean signal edges. Also the EMC radiation problem was gone.some advantages of AUPmuch shorter propagation delay than 74HClow power consumption"very good signal integrity"; relativ slow transition rate; ouput impedance near to 50 Ohmsome disadvantages of AUPonly in single/dual gate packagessupply voltage < 3.6 Von the other sideProblems with too fast logic:- signal reflections if not properly terminatedseehttp://www.ti.com/lit/an/sdya010/sdya010.pdffor some information on unterminated signal waveforms of older logic families.- GND-Bounce / VCC sagseehttp://www.ti.com/lit/an/szza038b/szza038b.pdf- higher requirements for decoupling / power distributionin short don't use LVC if not absolutely required for propagation delay

author: james_s
author_rank: Super Contributor
timestamp: October 08, 2019, 07:09:08 pm
content: Quote from: rstofer on October 08, 2019, 04:08:41 pmI don't even like to think of HDL as anything "executing" because it's really not. HDL is not a program, the instructions aren't executing, they're describing hardware using a language that superficially resembles a program.If you have a line like:A <= B AND C;That's not an instruction to execute an operation on variables, it's an instruction that says "wire signals B and C to the inputs of a two-input AND gate and connect the output to signal A". Once this gate has been "wired up" it will do its thing, it doesn't have to wait for an instruction to execute in a loop, the instruction described how to wire up the hardware.Existing programming experience can be more hindrance than help when learning HDL because it's so hard to get out of that mentality of writing a program and start viewing it as describing hardware.

author: ledtester
author_rank: Super Contributor
timestamp: October 08, 2019, 08:31:51 pm
content: If you don't want to learn a VHDL-like language, may I suggest:https://clash-lang.org/There's even a tutorial on how to go about building a CPU with it:https://yager.io/CPU/CPU1.html

author: ebclr
author_rank: Super Contributor
timestamp: October 08, 2019, 09:16:20 pm
content: You may have many hundreds of 74 series chips, on an FPGA, without writing a single VHL line, only drawing the schematics,

author: hamster_nz
author_rank: Super Contributor
timestamp: October 08, 2019, 10:03:36 pm
content: Quote from: ebclr on October 08, 2019, 09:16:20 pmHundreds? Nah, many thousands!I once worked out that the small FPGA was equivalent to a breadboard the size of a garage, and a (then) large but still obtainable one was equivalent to a basketball-court sized breadboard - complete with 100s of impossibly accurate wire-running gnomes.The problem with schematic entry is the additional information required. Rather than "C <= A AND B", where A B and C are 8-bit wide buses, you have the following data to manage:This is an AND gate "AND_1", at (x,y) with rotation of (r), and connections called A, B and CA run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).B run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).C run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).his is an AND gate "AND_2", at (x,y) with rotation of (r), and connections called A, B and CA run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).B run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).C run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).his is an AND gate "AND_3", at (x,y) with rotation of (r), and connections called A, B and CA run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).B run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).C run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).....and so on for eight gates required to AND two 8-bit values.So rather than a few lines of HDL you end up with maybe 120 to 300 bits of data (all the 'x's and 'y's and 'r' and names and labels) that have to be managed manually - sure most of these are mouse clicks and moves, but it still is a lot of information that has nothing to do with the actual function of the design, only it's presentation to the designer.If drawing schematics is your thing, than this might scratch your itch and keep you busy on a rainy day, but it is too much like doodling in the margins of a notebook...But by all means start with schematic entry - you will quickly get frustrated by it you will want the "better way" that a higher level symbolic representation offers.

author: ebclr
author_rank: Super Contributor
timestamp: October 09, 2019, 12:40:44 am
content: I for sure do the HDL way, but the OP wana buy and solder chips, this will be better than that

author: rstofer
author_rank: Super Contributor
timestamp: October 09, 2019, 02:47:37 am
content: It may be worth the time to block out the design and count the chips and interconnects.

author: ker2x
author_rank: Regular Contributor
timestamp: October 09, 2019, 06:10:21 am
content: Quote from: rstofer on October 09, 2019, 02:47:37 amThis is the first time i try an "hardware first" project on my own.Before drawing any schematic i needed to know what was available (without doing any dumpster diving to recycle old 74xx chips).The problem of 74xx availability have been solved (74HC chips from On Semiconductor), they're not the cheapest option but they exist.I find it funny that some Atmel ATTINY cost less than a quad OR gate.But the cost isn't a factor anyway, the value of the finished product will never worth the money and i'm okay with it, as long as i don't have to invest tons of money upfront (and there is no need for it).Even if i bought an absurdly overkill Zynq or Artix-7 fully featured dev board.But since the whole 74xx problem have been solved everyone is telling me to use an FPGA instead.I may be stuborn, but not stupid (hopefully?) and you know more about electronic than i do and ever will.The design will depend on the capabilities of the hardware.If i did it out of logic gate, the CPU would have been a subset of a 6502 + UART.On an modern FPGA i could have a full 6502 or Z80 (it have been done countless time) and still end up using only a few % of an entry level fpga (spartan, artix).It's been only a day so i can't decide what to do yet.BUT, i have an idea(of course i may change my mind again)The original plan was :- build the cpu using logic gate- emulate the rest of the computer, and test the subcomponent of the CPU, using a microcontrollerThe new plan may look like this :- Buy a fully featured fpga dev board (a entry-level one, not one with RF transceiver and 8x 10G ethernet, they are super expensive and useless to me)- Learn and use this fpga, instead of a microcontroller, for the testing and emulation of the non cpu part of the computer.- Once done, build the cpu out of logic gate, or build it in-FPGA. Or both.I have yet to decide if i use an FPGA or a (C)PLD, as i mentioned earlier i misunderstood what a (C)PLD was and therefore know nothing about it.By the way, i'm pretty sure there will be a massive problem interfacing FPGA and 74xx, right ?noise, impedence, timing, voltage, younameit ?

author: ker2x
author_rank: Regular Contributor
timestamp: October 09, 2019, 06:19:33 am
content: Quote from: ker2x on October 09, 2019, 06:10:21 amHuh... this sentence may lead to a grave misunderstanding.It's not like i woke up monday morning and decided to do this.It's been on my mind since much more time than that and i already have some 100% software project in progress.And i played with developing interpreters, OS, computer design, since a long time.

author: ker2x
author_rank: Regular Contributor
timestamp: October 09, 2019, 11:27:17 am
content: Would you suggest a zynq or an artix ?i probably have no use for the ARM core but... just asking.edit : i forgot that their website was an absolute nightmare in the past and didn't get any better.

author: rstofer
author_rank: Super Contributor
timestamp: October 09, 2019, 03:06:25 pm
content: Are you aware of the Ben Eater project?https://eater.net/8bitI worked on that for a while until I lost interest in making breadboard jumpers. Nevertheless, it's a pretty cool project and demonstrates quite nicely how a CPU actually works.As I said earlier, this is my favorite board:https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/Given the 100T version, I can fit a 64k word 16 bit RISC processor in there with the following utilizationBlockRAM 24% <--- there's quite a bit of BlockRAM left for things like disk buffers and suchIO 25% <--- I am using a lot of IO to drive the gadgets on the board but I can only do that onceLUTs 1% <--- the fundamental logic blocksFFs 1% <--- flip flopsBUFG 3% <--- used for clock nets. I didn't deliberately instantiate any BUFGs in this designIn other words, a fairly complete RISC processor (the LC3 project) rolls around like a BB in a Bowling Alley. I can add features like disk IO and never put a dent in the use of LUTs and FFs. This thing is a virtual dumpster full of chips.ETA:Suppose I do decide to add an SD card. I could build the controller in logic or I could plunk down another RISC core (with much less BlockRAM) and write the driver in C. All I would need to do is add a DMA system to share the BlockRAM between the main RISC core and the SD controller. I might even be able to use the dual-port feature of the BlockRAM and keep the CPU on one side and all of the IO devices on the other side. This means the DMA controller/channels are on just one side of the BlockRAM and the CPU can run uninterrupted by memory collisions. I could also instantiate a Xilinx core and use their tools to port an entire network stack. And STILL the main CPU could run uninterrupted. And I haven't even gotten to the bit about using the DDR as static RAM with code provided by Digilent.I have a lot of FPGA boards (for a hobbyist) and most of them feature a lot of gadgets. I don't really like the naked boards because development is slowed while I hack in some LEDs and displays. I consider the gadgets as far more important than the chip itself.I don't have a Zynq board and I haven't found a need for one, yet. Obviously, using the ARM core to drive all the IO devices for a low end RISC core makes no sense at all. Just buy a Raspberry Pi 4 and be done with it. One day I may find a reason for that board and, sure enough, one will wind up on my bench in a few days.Artix 7 seems to be the chip of choice at the moment. Older versions (Spartan II, Spartan 3 and up to Spartan 6, I believe) need to use ISE 14.7 as the toolchain and this is obsolete and not really supported. It is far better to pick a chip that is supported by Vivado. Within a family, BlockRAM is the biggest discriminator. You need all the BlockRAM you can get. If the incremental cost isn't a show stopper, get the biggest device available.I didn't mention any of the non-Xilinx vendors. I simply don't have any experience with them.

author: ker2x
author_rank: Regular Contributor
timestamp: October 09, 2019, 03:58:38 pm
content: Quote from: rstofer on October 09, 2019, 03:06:25 pmYes, i follow his youtube channel

author: ker2x
author_rank: Regular Contributor
timestamp: October 09, 2019, 04:23:33 pm
content: Quote from: rstofer on October 09, 2019, 03:06:25 pmPerfect, it was in my wish-list already so i just ordered it.I'll receive it in 2 or 3 days.The other one in my wishlist was this onehttps://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/Cheaper, smaller fpga, no DDR, no audio.About DDR, i had a board with DDR, it seamed to be really difficult to use.Digilent have a github repo with this :https://github.com/Digilent/Nexys4DDRi hope it's what i think it is

author: rstofer
author_rank: Super Contributor
timestamp: October 09, 2019, 04:46:02 pm
content: I have that Basys board as well. It's pretty nice but the 35T device is a lot smaller than the 100T device. I hope you selected the 100T variant rather than the much smaller (in terms of BlockRAM) 50T device. Bigger is better - always!ETA: You will find the DDR component under Additional Resources on the original Nexys 4 DDR board page:https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/startI think this is going to take a bit of studying. I have never used it.

author: ker2x
author_rank: Regular Contributor
timestamp: October 09, 2019, 05:17:01 pm
content: Quote from: rstofer on October 09, 2019, 04:46:02 pmOf course

author: rstofer
author_rank: Super Contributor
timestamp: October 09, 2019, 05:24:00 pm
content: Quote from: ker2x on October 09, 2019, 04:23:33 pmWell, I guess that settles the chip vs FPGA question! I think you'll like the board. You need to install Vivado and then follow the Yellow Brick Road at Digilent to install their board files. This is an important step. You don't want to design to the chip level, you want to design for the board so, when you create a project, you will select the Boards tab and find your board in the list. Installing the files is easy to do but it is a really big deal!So, while you wait, you might as well install Vivado and the Digilent files. I have forgotten whether you need to install the Digilent Adept software but you might as well. Once everything is tied together, board programming is seamless via Digilent's USB->JTAG device. Seamless was always important to me, I really never liked using JTAG dongles even if they did work from time to time.The USB gadget also appears as a UART - this is really handy since almost every CPU project will want to talk to a PC.As you no doubt found out, there are a lot of resources for this board (and its predecessor, the Nexys 4 DDR) at Digilent. It might be worth looking around for tutorial projects.When I program a project into the board, I program only the FPGA, not the platform flash. That way, on power up, I get the crawling snake, not the remnants of some program I was previously working on.

author: ker2x
author_rank: Regular Contributor
timestamp: October 09, 2019, 05:34:09 pm
content: I realize there might be a problem :https://www.amazon.fr/gp/product/B0714MKJ4H/1) the digilent product description on amazon.fr are garbage (on all their product)2) the picture show a nexys A73) the title say Nexys 4 DDR, which is discontinuedBoth board are nearly identical according to digilent. I can't even find the difference.I'm wondering what product i'll getThe description also say Nexys 4 DDR.Well, if they are the same, i don't mind. If there is a difference i don't like i can send it back saying the picture was wrong and the description unreadable.The wiki say : "The only difference between the Nexys A7 and Nexys 4 DDR is the addition of the Nexys A7-50T variant of the Nexys A7, which has a smaller gate array. The Nexys A7-100T variant is functionally identical to the Nexys 4 DDR."

author: ker2x
author_rank: Regular Contributor
timestamp: October 09, 2019, 05:45:18 pm
content: Quote from: rstofer on October 09, 2019, 05:24:00 pmI started installing vivado even before ordering the cardIt pretty much settle the chip/fpga but not so much.I still have the option to design the cpu on chip but : i probably won't, and i'll implement everything in fpga before doing an eventual chip version. There is a VGA port after all, i MUST use itThis board probably doesn't have enough I/O for interfacing with a homebrew CPU anyway. I could buy, later, a cheap nano board with no accessories, only the fpga and tons of I/O if i really want it. Something like this :https://store.digilentinc.com/cmod-a7-breadboardable-artix-7-fpga-module/But i learned my lesson. i have a board like this (with a Spartan-6) and it's NOT a good way to learn

author: rstofer
author_rank: Super Contributor
timestamp: October 09, 2019, 06:38:42 pm
content: I liked the older Spartan 3 Starter Board with 3 ea 50 pin edge connectors. I used one connector for a logic analyzer interface (32 channels) and the one on the right for a Compact Flash board. That LA is the only way I ever got the system to work. The Vivado ILA will do it even better!https://store.digilentinc.com/spartan-3-board-retired/I eventually migrated my IBM 1130 to a Nexys 2 board. It's very expensive for what it is but at least it had an edge connector for the Compact Flash board (and a 4 channel FTDI UART<->USB board). This was back when the Nexys 2 was the top of the line...https://store.digilentinc.com/nexys-2-spartan-3e-fpga-trainer-board-retired-see-nexys-4-ddr/https://www.digikey.com/product-detail/en/ftdi-future-technology-devices-international-ltd/FT4232H-MINI-MODULE/768-1031-ND/2027253I built a logic analyzer out of the small version of the Starter Board:https://www.sump.org/projects/analyzer/PacMan is built on another Nexys 2 board just because I had it sitting around. The T80 core (Z80) at OpenCores.org is excellent for retro arcade games (that used a Z80) and for running CP/M on a Compact Flash.https://opencores.org/projects/t80There are 6502 cores at OpenCores.org Among others:https://opencores.org/projects/cpu6502_true_cycle

author: james_s
author_rank: Super Contributor
timestamp: October 09, 2019, 09:47:40 pm
content: Quote from: ker2x on October 09, 2019, 06:10:21 amIt's because they're a niche specialty part today, AVR microcontrollers are sold by the many millions, 74xx parts are probably at least an order of magnitude smaller market.

author: rstofer
author_rank: Super Contributor
timestamp: October 10, 2019, 06:48:38 pm
content: That Gadgetory site has a lot of component kits for the tutorials by PyroEDUhttp://www.pyroelectro.com/edu/https://gadgetory.com/index.php?route=product/category&path=66This might be a very acceptable learning program which, by being more up to date, is somewhat easier to approach. There are lab examples using the component kits from Gadgetory along with DVDs for each of the major sections (I don't know if they are just duplicates of the YouTube videos).I have only watched about 1-1/2 videos but I'm reasonably impressed. A beginner would be a long way down the path after completing this series.Lab examples are probably the best way to learn electronics.I'm going to spend a bit more time on this site!

author: jmelson
author_rank: Super Contributor
timestamp: October 10, 2019, 06:54:32 pm
content: Quote from: ker2x on October 07, 2019, 05:09:15 pmWell, I don't do "cutting edge" projects where I need to get every last ns out of an FPGA. On the other hand, I did do a project where we had a bunch of 32-bit counters running at 150 MHz on a Spartan 3AN FPGA, which is a pretty old part. No problem whatsoever getting that to compile and work.So, any place I need about 3 - 10 TTL chips worth of stuff, I use either a 9500XL or CoolRunner II CPLD from Xilinx, for about $1 - 2 each. For more than about 10 TTL chips equivalent, I use a small Spartan 3A for about $13. Basically, if it simulates, it works, period! And, if it doesn't simulate, it is because I am lousy at writing VHDL.Jon

author: rstofer
author_rank: Super Contributor
timestamp: October 10, 2019, 08:54:39 pm
content: Whether an HDL or a procedural language, the only way to really get a handle on it is to write it.This book (free) will help:http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdfPage 93 is where the Finite State Machine coding really starts. Note where the author pre-assigns the output. Page 95, first bullet, explains why. This is a CRITICAL concept!

author: james_s
author_rank: Super Contributor
timestamp: October 11, 2019, 04:59:54 am
content: Quote from: ker2x on October 09, 2019, 05:17:01 pmI actually prefer smaller FPGAs in most cases. I can fit an entire 8 bit computer in a $12 Cyclone II dev board and compile it in under a minute. I have a DE2-115 with a much larger Cyclone IV and it takes several times longer to compile the same design. Lots of middle ground too, but I actually sold off my biggest FPGA boards some time back when I realized I was never using them, the midsized FPGAs are more than adequate for my biggest projects and anything larger is just slower to compile and more effort to work with. I use the smallest ones the most and the biggest ones the least.

author: rstofer
author_rank: Super Contributor
timestamp: October 11, 2019, 05:42:41 am
content: I built up a workstation with an I7-7700K, 32GB of fast RAM and a 1TB SSD just because Vivado is such a slug. On this machine, compilations are at least reasonable. Way back, with Win 98 and a much slower processor, building a project could take 20 minutes or more. I realize this isn't anywhere near the record but it exceeds my short attention span. Compiling with 8 threads is helpful!I just started fooling around with Quartus for a CPLD using my laptop and it runs pretty quick for a simple project. About 5 seconds for a project that just sets an output bit to '1'. Of course, the chip is tiny with just 32 macrocells. How long could it possibly take?For no particular reason, I have decided to work through this program:http://www.pyroelectro.com/edu/fpga/Hint for those who follow: When the author says install Quartus 13.0 SP1, don't get adventuresome and try for a more current version. It won't support the Max 3000A series chip which is the basis for the tutorials. There's a reason I know this!The board, USB Blaster and associated bits and pieces is only about $50, delivered, and the Blaster will work on a range of Altera devices. I'm not much of a fan of JTAG programming but maybe things have improved over the last 10 years or so since I last used a JTAG dongle.https://gadgetory.com/index.php?route=product/product&path=66&product_id=126The reason I like the larger FPGAs isn't so much for the logic, it's for the BlockRAM. There is never enough BlockRAM...

author: wilfred
author_rank: Super Contributor
timestamp: October 11, 2019, 06:23:11 am
content: Wow it didn't take long for the thread to move off TTL and onto FPGA.

author: ker2x
author_rank: Regular Contributor
timestamp: October 11, 2019, 01:02:31 pm
content: Quote from: wilfred on October 11, 2019, 06:23:11 ami know, right ?

author: rstofer
author_rank: Super Contributor
timestamp: October 11, 2019, 04:17:16 pm
content: Quote from: ker2x on October 11, 2019, 01:02:31 pmSorry about that!The thing is, I like digital systems. I REALLY like digital systems and I can't build them from discrete components because the circuit boards would get massive and plentiful and I'm just not into wire-wrapping like I was when I was younger. But when I was younger, I didn't have access to FPGAs.I remember when I started using the Spartan 3 Starter Board with 1 MILLION logic gates. That is a very modest chip by today's standards but think about what you can do with a MILLION gates! That might be similar to somewhere between 10,000 and 100,000 chips. Did I mention I don't have to wire-wrap them? Can you even imagine wire-wrapping 10,000 chips? A minimum of 14 wire-wraps per chip? Probably closer to an average of 30? 3 million connections? Insane!I can easily envision a CPU that would use up the logic in that Spartan 3. Maybe some kind of pipelined RISC processor with an expansive instruction set. Logic tends to bloom when we add in multilevel caches and multiple cores. My IBM1130 project uses about 30% of the logic and just about all of the BlockRAM.For folks who want to play in the digital domain, FPGAs are the way to do it. A single line of code creates a 32 bit register, not 8 wire-wrapped 4-bit D flops and bus drivers or muxes to steer the outputs.

author: The Senate
author_rank: Newbie
timestamp: October 11, 2019, 04:39:11 pm
content: The old multi function peripheral chips they used in 8 bit computers come to mind since they still make some of them. For example the 6522 VIA has 2 16 bit timers, an 8 bit shift register, and 2 8 bit parallel I/Os.Each of the CPUs had there own group of peripheral ICs made to complement them. Some are still manufactured like the 65XX family in DIP and SMD form.http://www.cpu-world.com/Support/index.html

author: rstofer
author_rank: Super Contributor
timestamp: October 11, 2019, 05:12:09 pm
content: RC2014.co.uk seems to have an inexhaustible source of Z80 and related peripherals. I have at least 3 of his systems (I tend to lose count of this kind of thing) and they are quite fun. I especially like the Full Monty version running CP/M.

author: james_s
author_rank: Super Contributor
timestamp: October 11, 2019, 05:36:20 pm
content: Quote from: wilfred on October 11, 2019, 06:23:11 amWell the OP said they didn't want to hunt around or salvage old obsolete logic chips, so CPLD/FPGA is the natural thing to come up when the other viable option is shut down. The 74xx series is 40-50 years old, the fact that so many of them are still available today at all is a minor miracle. I use the DIP parts to repair vintage gear but I can't imagine there are many going into new designs.

author: wilfred
author_rank: Super Contributor
timestamp: October 12, 2019, 12:36:46 am
content: Quote from: james_s on October 11, 2019, 05:36:20 pmIt's an impossible ask to prevent threads diverting off the original topic but in the beginners section people should exercise restraint.

author: ker2x
author_rank: Regular Contributor
timestamp: October 12, 2019, 02:06:01 am
content: Quote from: wilfred on October 12, 2019, 12:36:46 amIn this particular case, it probably was for the best.And my original question has been answered anyway. As a beginner, i very much appreciate the additional informations since i ended up buying a FPGA board (a proper one actually made for beginners, this time)

author: ker2x
author_rank: Regular Contributor
timestamp: October 16, 2019, 04:40:06 pm
content: I received my board, it's a Nexys A7 with an Artix-7 100T