Isolating an open-drain output to allow higher voltage pull-up - Page 1
Forum section: electronics / beginners

author: eddie1
author_rank: Contributor
timestamp: November 17, 2019, 03:02:50 am
content: I have an open-drain output off a PIC. The output will be connected to an external device, which could potentially pull it up to as much as 12V, but more likely 3.3V. This particular PIC part (PIC16LF18324) has an absolute max voltage rating of VDD+0.3V, and I intend to run the PIC at 1.8V, so either 3.3V or 12V will exceed the rating. I need to find a way to isolate the output in a way that will allow it to be pulled up beyond the PIC's limits.The idea I came up with is to change the MCU output to push-pull and connect an N-channel logic-level MOSFET (rated to handle the pull-up voltage) between the MCU pin and the external device. The gate would be connected to the MCU pin, the drain would be connected to the external device, and the source would be connected to ground. I think the result would be that when the MCU pin is logic high, the drain (connected to the external device) would be pulled to ground, and when the MCU pin is logic low, the drain would be floating (and pulled up by the external device). The PIC output is already at 50% duty cycle, so the output inversion isn't an issue (and if it was, the PIC output could be inverted anyway). This sounds to my inexperienced self like it should work, but I wanted to see if there is a more proper way to accomplish this.Thanks!

author: Ian.M
author_rank: Super Contributor
timestamp: November 17, 2019, 05:14:33 am
content: Yes, that idea works and is probably the cleanest way to handle it. You'll need a N-MOSFET with a gate threshold voltage under 1V to ensure your 1.8V logic '1' level is enough drive to turn it fully on. If there's any chance of an inductive load, even just the inductance of long wires, you may want to add a 25V Zener across the MOSFET, cathode to drain (and use a MOSFET rated for at least 30V Vds) to clamp any back-EMF at switch-off.

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: November 17, 2019, 07:43:42 am
content: Make sure you add a pull-down resistor of about 100K at the gate of the NMOS. This is to ensure that the gate does not float upon power up, before the MCU programs those pins as outputs and start to drive them. This is a good design practice in addition to the diode as stated above.

author: Ian.M
author_rank: Super Contributor
timestamp: November 17, 2019, 12:38:35 pm
content: The need for a pull-down resistor depends on the load. Its essential for all power MOSFETs and high current loads as leakage current into a floating gate could take the MOSFET into its linear region and burn it up fairly rapidly.However if the MOSFET is only used for logic level shifting and the load cant pass enough current to cause significant dissipation in the MOSFET even worst case with half the load supply voltage across it, and the load can tolerate an invalid logic level during startup, you may be able to get away without a gate pull-down.

author: eddie1
author_rank: Contributor
timestamp: November 17, 2019, 10:08:37 pm
content: Thank you both!MOSFET shopping is a bit of a pain. Digi-Key's normally excellent parametric search can only go so far when different manufacturers use different conditions for their ratings (e.g. some Vgs(th) are at 250uA, some at 1mA, and everywhere in between).Is my understanding here correct: obviously a low enough Vgs(th) at the appropriate current level, high enough Vdss, and high enough continuous current rating (which need not be that high, just enough for a typical external pull-up) are must-haves; but beyond that, lower gate charge and lower input capacitance are better for lowering power consumption and making it easier to drive with an MCU, but not terribly important in this application (not worth paying significantly more for)? The absolute max switching speed for this open drain signal would probably be about 2000 Hz (likely lower, but being conservative here).And thank you for the ideas of the Zener and pull-down resistor. The Zener sounds like a good idea because long wires are a possibility (6" is probably typical, but potentially 12" or longer could be connected). I'm not sure if the pull-down resistor is necessary though -- junk output during the few-millisecond startup period shouldn't be an issue, and (correct me if I'm wrong) I don't think this is particularly high current. I figure even in an absolute worst case where an external device uses a very low 1k pull-up (which seems unlikely in itself) and pulls up to 12V (which also seems unlikely; it's allowed but I can't imagine the utility of pulling up beyond a 3.3V or 5V logic level), that's 12mA, but the output is floating 50% of the time, so it's really 6mA.Actually, that raises another question: what's the best way of protecting against a scenario where the OD output is directly connected to a positive voltage without a resistor (whether by some kind of hardware failure or just error), which would create a short circuit during the 50% of the time when the OD output is grounded? Would a low-value resistor (maybe 2.2k) between the drain and the external connection work, or is there a better way? (Sorry for the dumb questions. This is my first project actually playing with electronics at a hardware level, beyond, say, simply assembling a PC. I think I've figured out some of the basics, but I know there's a lot I don't know and I'm not even particularly confident in my ability with the basics!)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 17, 2019, 10:14:41 pm
content: Yes, you can cascade the pin into a transistor. You can also cascode it, which maintains the pin characteristic (open drain) while increasing its voltage range.Cascode just means to connect the drain (i.e., the pin) to the source of another transistor, whose gate is tied to "ground". (An AC ground, so GND and VDD both count. Specifically, you'd use an enhancement mode transistor with gate to VDD, or depletion mode with gate to GND.)The cascade option inverts the signal (which is pretty trivial to deal with on an MCU), but can offer higher current as well as voltage ratings. The cascode option is limited to the same current range as the pin (i.e., 20mA or thereabouts).Quote from: eddie1 on November 17, 2019, 10:08:37 pmDon't worry about shopping for Vgs(th). Shop for logic level. A <= 1.8V logic level capable transistor is what you need here.A small and cheap one offhand,https://www.mouser.com/ProductDetail/ROHM-Semiconductor/RUM001L02T2CL?qs=%2Fha2pyFaduhJHoduUO5nMbSxMhNujPujgvgxGxQDdo0%3DQuoteShort circuit protection, easy answer: use a protected switch, with logic-level input.I don't know of any offhand that are 1.8V compatible, so you probably need to do the level shift trick (whether with a logic IC, or transistor and pullup), then the switch.Example:https://www.mouser.com/ProductDetail/Infineon-Technologies/BSP75N?qs=sGAEpiMZZMuCmTIBzycWfNaB4tqdZgjBJuUOEMjhlQI%3DYou can make your own through various means, but it's more parts, and probably won't be as cheap or reliable.Tim

author: eddie1
author_rank: Contributor
timestamp: November 17, 2019, 11:29:10 pm
content: Quote from: T3sl4co1l on November 17, 2019, 10:14:41 pmThanks! I like this idea because retaining the OD output on the PIC would add flexibility if a user (I'm going to open source this) wanted to omit the MOSFET, if they knew whatever external device they're connecting to would not pull up beyond the VDD+0.3 rating. The inverted output makes no difference since the output is already at 50% duty cycle.There are a few things I don't understand though. First, to verify my understanding is correct: using an enhancement mode N-MOSFET, the gate would be connected to VDD (1.8V in this case), the drain (I'm assuming) would be the new high-voltage-capable OD output, and the source would be connected to the MCU pin.When the MCU pin is pulled to ground, wouldn't the drain and source (which would be the MCU pin that the MCU is pulling to ground) be connected? If the drain is connected to an external device with, say, a 3.3V pull-up, the MCU pin is going to have to sink that current. How does this avoid the voltage limitation of the MCU pin?Also, if the MCU pin is OD, that means the source would be floating sometimes (half the time in this case). Is there the same problem with this as there is with a floating gate?Quote from: T3sl4co1l on November 17, 2019, 10:14:41 pmI'll add this to my Digi-Key shopping cart (DK also stocks the part). I'm accumulating items for my next delivery and will order tomorrow right before the shipping cutoff time.I was looking in the single MOSFET category which doesn't have a parametric option for logic level; Vgs(th) looks like the only way to search for that. It looks like the MOSFET array category at Digi-Key does have specific feature options for logic-level gate though.Quote from: T3sl4co1l on November 17, 2019, 10:14:41 pmWith the cascode option, would it be OK to rely on the current clamping mechanism that I think the PIC has on its GPIO pins (will verify first)? The short circuit thing should never happen; I brought that up as a "just in case" failsafe because I know MOSFETs can fail violently when pushed beyond spec.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 17, 2019, 11:55:08 pm
content: Quote from: eddie1 on November 17, 2019, 11:29:10 pmCorrect.QuoteThis avoids the limitation, because the drain and source aren't unconditionally connected. The transistor still transists.Note that, as the MCU pin turns off, source voltage rises -- pulled up by drain current. Which means Vgs is falling, which means at some point, drain current will also fall. When it falls below cutoff, the source stops rising, and the transistor is off.You could add a small G-S pullup to ensure a valid logic level, true. The source isn't quite floating, as it's guaranteed between VDD-Vgs(th) and VDD+0.5 or so. Which is likely a valid logic level to the PIC as well, if that matters.Which if you aren't aware -- it can be helpful to bias unused input pins to valid levels, or set them as outputs. Every logic input pin has a pair of transistors sensing that voltage, and if the voltage is inbetween valid logic thresholds, it can do annoying things, like draw more supply current (which might only be ~uA, but that can be significant in a battery powered device), or do weird instability things (oscillate, be sensitive to interference?). So it can be nice to have some pullup even if the pin level isn't otherwise important.Some MCUs may have output-only pins, or input stages that can be completely disconnected, where this may not apply. Usually they are of the above (GPIO) type.QuoteYes, if that's a thing it does then the current will be passed on perfectly through the cascode. Just make sure the power dissipation is acceptable and it should survive.Which, if it's not -- you can implement other current limiting very simply in this configuration. Introduce a resistor between pin and source. Now the transistor can deliver an absolute maximum of (VDD-Vgs(on)) / Rs, with a saturation voltage around VDD-Vgs(on).Note I say Vgs(on) instead of Vgs(th), because the "on" condition is at whatever Id is flowing; Vgs(th) is specified at, whatever it says, 50uA or the like. Use the transfer curve (Id as a function of Vgs) to estimate this.This is better with BJTs, because you can make the offset voltage smaller, a Vbe (~0.7V) or even less.Put another way: the current-limiting resistor is in series with the load, at low currents. So some saturation voltage is eaten up by it.When I'm not pressed for layout space, I like to use BJTs like so:For open-drain (well, open-collector in this case), you'd the bottom half, getting rid of R89, 90, 96 and Q7.This also shows some EMI filtering and ESD protection. I find the FB + C does a nice job of smoothing out the rough edges from the logic signal, while the diode clamps ESD.Some resistance between the ESD clamp and logic pin is generally recommended. Here, the base resistors provide that, so the driving source is well protected. The BJTs themselves can be pulled beyond the rails a fair ways without damage, they'll just zener into the emitter resistors.A similar circuit using MOSFETs, you'd probably use directly grounded sources (rather than source degeneration resistors), and set the gate voltage carefully instead (e.g. a MOSFET current mirror -- bloody difficult to do with discrete transistors, basically an IC-only trick). In that case the body diodes serve as additional clamping, and maybe 10-100 ohms would be recommended, between the ESD diode and transistors.If you don't necessarily have a higher voltage supply (as is the case for open-drain signals), use a zener or (unidirectional) TVS from GND to OUT, instead of the double diode.Tim

author: eddie1
author_rank: Contributor
timestamp: November 18, 2019, 03:07:43 am
content: Quote from: T3sl4co1l on November 17, 2019, 11:55:08 pmThanks! I know this isn't really the perfect MOSFET for the purpose, but I have an FQP30N06L so I decided to breadboard test it. (I'm still going to order from Digi-Key tomorrow.) I've attached an oscilloscope (Analog Discovery 2) screenshot. Channel 1 is connected to the MOSFET drain (with a 10k pull-up to VDD, which is 1.8V here), and channel 2 is connected directly to the MCU pin so I can see what voltage appears there. With the 1.8V pull-up, I see a max of about 1.3V on the MCU pin. When I get a more appropriate MOSFET I'll test it with a 12V pull-up. Right now I'm just using the Analog Discovery's built-in DC power supply which can only provide one positive output, and only up to 5V.Quote from: T3sl4co1l on November 17, 2019, 11:55:08 pmYep. On the PIC I set them as digital inputs driven low, which is Microchip's recommendation in every PIC data sheet I've looked at (including for the PIC16LF18324 I'm using).Quote from: T3sl4co1l on November 17, 2019, 11:55:08 pmI'm sure it's dependent on the specific MOSFET, but it looks like (at least with the FQP30N06L) there might even be enough resistance already to prevent the kind of short that would (literally) blow the MOSFET. I tested it by connecting the drain directly to 1.8V, and total power consumption (which includes the MCU, which draws under 500 nA for the Timer0 output while in sleep mode; good job, Microchip!) only went up to a little over 1 mA.