Understanding the IR2110 half bridge driver - Page 1
Forum section: electronics / beginners

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: April 05, 2019, 02:55:51 pm
content: I want to use the IR2110 to drive a half bridge the bridge voltage would be around 100V.The mosfet gate drive voltage (Vcc) is 15V.I would not want to use the bootstrap capacitor here. So just want to understand what external voltage level should I provide to the Vb pin.And is it okay to have that voltage source referenced to the COM / VSS pin.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 05, 2019, 04:48:08 pm
content: The bootstrap source goes between Vb and Vs, where the bootstrap capacitor would go.Why not bootstrap? Intermittent or slow switching?Tim

author: MagicSmoker
author_rank: Super Contributor
timestamp: April 05, 2019, 05:14:08 pm
content: Quote from: ZeroResistance on April 05, 2019, 02:55:51 pmI really don't like bootstrap driver ICs and haven't used one in years, but, in general, you can supply Vboot directly and dispense with the diode and capacitor charge pump as long as you use an isolated power supply to do so. Note, however, that once you've gone to the trouble of using an isolated supply you might as well go all the way and make a proper floating high side driver.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: April 05, 2019, 05:48:20 pm
content: Quote from: MagicSmoker on April 05, 2019, 05:14:08 pm1. So, the supply has to isolated?? I did miss that.2. Like you said you don't like the bootstrap driver IC's which one's do you prefer and can you provide a few part numbers.3. What is a proper floating high side driver?

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: April 05, 2019, 05:50:50 pm
content: Quote from: T3sl4co1l on April 05, 2019, 04:48:08 pmYes, its kind of intermittent, Is there any way to simulate a IR2110, LTSpice perhaps??

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 05, 2019, 06:23:04 pm
content: There might be a model for it somewhere, I don't know. What are you trying to simulate? Likely you only need a very limited set of features, that can be even more easily simulated on paper?Tim

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: April 05, 2019, 06:49:31 pm
content: Quote from: T3sl4co1l on April 05, 2019, 06:23:04 pmFound them athttp://bordodynov.ltwiki.org/I want to cross check the behavior of the circuit just to get an approximation if it works, its a simple half bridge driver. But I would like to check the rise times and fall times at the gate and the peak gate charge current?Also regarding "MagicSmoker" suggested regarding an isolated driver or a proper floating high side driver, Any idea what he was trying to suggest?

author: jmelson
author_rank: Super Contributor
timestamp: April 05, 2019, 06:56:36 pm
content: Quote from: ZeroResistance on April 05, 2019, 05:48:20 pmYes, it has to be an isolated, floating supply for every half-bridge (if you have multiple).The only way to avoid this is to use a push-pull driver and a transformer, with a separate winding for each high-side driver/transistor.Watch out for capacitance, as the half-bridge common point swings pretty fast.Jon

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: April 05, 2019, 07:14:54 pm
content: Quote from: jmelson on April 05, 2019, 06:56:36 pmRegarding the push-pull driver are you hinting at a discrete driver or a chip? and the capacitance at the common node I will look up on that!!

author: jmelson
author_rank: Super Contributor
timestamp: April 05, 2019, 10:13:02 pm
content: Quote from: ZeroResistance on April 05, 2019, 07:14:54 pmA long time ago I made a full-bridge driver that needed a high-side bias supply. I used a little pot-core transformer with 4 windings.For convenience, I used quadrifilar wire (4 isolated strands glued together.) It was 80 turns, I think. I used an CD4069 hex inverter, with 3 stages driving each end of the primary. 2 secondary windings powered the high-side drivers, and the last powered a high-side current sense circuit. Well, everything was fine until the output transistors were running. It turned out the interwinding capacitance was blowing out the CMOS gates. Getting rid of the quadrifilar wire and putting the primary on a separate zone of the bobbin fixed that.So, you can do this, either discrete or chip, and the CD4069 was probably NOT the best choice. Unless you actually need to deliver 100% on time for the high side transistor, I don't see what the issue is with the bootstrap scheme.Jon

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 06, 2019, 06:45:07 am
content: Quote from: ZeroResistance on April 05, 2019, 06:49:31 pmHow accurately do you want to know these parameters?What transistor do you want to drive? How fast (t_r/t_f and Fsw)?Estimating gate rise/fall is very easy. Take Qg(tot), divide by Vgs(on) (typically 10V) to get Cg(eff). Combine Cg(eff) with R_G + (driver's R_out) to get the gate drive time constant. The rise or fall time will be about twice this. About half of which is likely during the Miller step. (Driver R_out isn't specified, but you can guess it's around R_out = V_bs / Io(pk), or ~6Ω here.)More precisely, take the RMS sum of this time constant plus the rise/fall time of the driver itself, since it's not perfectly fast of course. This is around 25ns for a 1nF load (equivalent to a ~10nC gate). It's not obvious how much faster it is for smaller loads. (That's a 6ns time constant which would give a ~12ns risetime, so the driver risetime may be closer to 20ns.)Any more precise than this, and you are -- actually, even at this level of precision -- you are fully at the mercy of component variation. The driver's rise time spread (due to manufacturing and environmental variations) is probably something like 15-35ns. The transistor is probably something like, for example, 24 to 56nC, with 43nC typical, or whatever. The exact figure varies with drain voltage, too. The error due to properly accounting for nonlinearities in the circuit (the driver isn't actually a constant 6 ohms at all output voltages; the transistor gate's capacitance varies with voltage) is comparable.For a graphical version, you can basically draw a typical gate waveform, and scale the axes proportional to these numbers.Is this satisfactory?SPICE simulation is good for getting a feel about more complicated behavior, like circuit parasitics; but that's a more advanced topic and requires understanding where to put parasitics in, and of what values. It's also just as sensitive to the quality of the models used; even manufacturers themselves don't always get them right. The only solution is to test and compare. Putting together a good model takes a lot of care!Tim

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: April 06, 2019, 09:03:17 am
content: Quote from: T3sl4co1l on April 06, 2019, 06:45:07 amThis is mind mindbogglingly amazing!!You never cease to amaze me T3sl4co1lI'd like to hear your story, regarding you journey to master your trade, if you have a blog or something pls do share.BTW I was looking to drive various configurations of Half bridge one is the standard one, and one is with dual supply, how would you drive the mosfets in a dual supply Half bridge configuration, they would need transformer drive , correct?

author: MagicSmoker
author_rank: Super Contributor
timestamp: April 06, 2019, 11:09:05 am
content: Quote from: ZeroResistance on April 05, 2019, 05:48:20 pm1. To turn on a MOSFET (or IGBT) you need to drive its gate with a voltage about 10V higher than its source (or emitter), but the source/emitter of the upper (or "high side") switch is not referenced to ground (or common) unless the lower switch is on, and when the lower switch is on the upper switch must be off. So, you either have to use an isolated power supply for the upper switch, or a bootstrap driver IC like the IR2110.2. I generally roll my own gate driver circuits using a variety of approaches depending on power level, how high an isolation voltage is required, etc., but for a beginner I would recommend using an isolated gate driver IC like made by Silicon Labs* or Analog Devices' ADuM series, etc., and one or two small 1W - 2W potted dc/dc converter modules for supplying isolated power to the upper and, optionally (though highly recommended) lower switch gate drivers. Note that while you don't technically need an isolated supply for the lower switch, using one anyway allows you to fully isolate the control and power handling sides of your circuit which vastly improves the reliability, noise-immunity and safety; note that none of these advantages accrue from using a bootstrap driver.3. See above.* - e.g., Silicon Labs Si8232https://www.mouser.com/ProductDetail/Silicon-Labs/SI8232BB-D-IS?qs=sGAEpiMZZMvQcoNRkxSQkmAXKPf7n2%252BxDWshxPYbuYg%3D

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: April 06, 2019, 05:10:38 pm
content: Quote from: T3sl4co1l on April 06, 2019, 06:45:07 amWhy do we take Vgs(on) here instead of the actual gate driver supply voltage?. I mean if we are providing the gate driver a supply of 15V should we still consider Vgs(on) of typ. 10 for the above calculation?

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: April 06, 2019, 05:56:43 pm
content: Quote from: T3sl4co1l on April 06, 2019, 06:45:07 amJust looking into the math here.Time const = 6nsDriver rise time = 25nsRMS sum = sqrt((25^2 + 6^2)/2)= sqrt((625 + 36)/2)= sqrt(330.5)= 18.18ns rise timeWould this be correct instead of the above mentioned ~12ns rise time

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 06, 2019, 07:37:21 pm
content: Quote from: ZeroResistance on April 06, 2019, 05:10:38 pmBecause that's what the parameter was measured at.You should indeed prefer the equivalent under your conditions. For this, you might consider the gate charge curve instead. Downside: that's a typical plot, not max.The extra voltage adds charge above the Miller step, where capacitance is constant (Vds ~= 0), so the change will not be considerable.Presumably, you can take the max value, and scale it by the same amount. Say there's 40nC (typ) at 10V, and 52nC at 15V. Say max (at 10V) is rated 64nC. We then guess max at 15V is (64/40) times 52nC.Using max charge is relevant to power supply consumption and dissipation (the charge is drawn straight from the supply, and dissipated through the driver's resistance, and R_G). Driving a 64nC gate at 200kHz requires 0.064uC * 0.2MHz = 0.0128A (micro cancels with mega), or 12.8mA. The resistances dissipate that much times the supply, or 12.8mA * 10V or whatever. (There's a 1/2 in there when you calculate the energy lost in charging a capacitor through a resistor -- however, that energy comes right back out again, so the energy over a full cycle is one times. Easy!)You should probably use typical, or maybe even minimum (if given), charge, for rise time calculations, since that affects the next phase of design: parasitics in the switching loop. You want the sqrt(switching loop stray inductance * junction capacitance) (mostly transistor Coss, or including diode Cjo for the buck/boost case) to be much less than the rise time, otherwise it is likely to resonate and generate voltage spikes and emissions.Often, this conflict is unavoidable, and then damping or snubbing is necessary.Quote from: ZeroResistance on April 06, 2019, 09:03:17 amThanks. Was never one for blogging, but I did write webpages back in the day,https://www.seventransistorlabs.com/tmoranwms/Electronics.htmlwhich is chronologically about highschool to college days (unfortunately I didn't date most of the pages, so you'll have to guess when anything was written).Newer pages are on my main site, like some projects herehttps://www.seventransistorlabs.com/Projects.html. The calculators are particularly useful. I haven't added any pages in a while, unfortunately...QuoteUse a bootstrap driver referenced to the lowest supply. If you need ground-referenced logic, add digital isolators or level shifters there.Unfortunately,no onemakes a bootstrap gate driver that goes negative. I guess it wouldn't be bootstrap anymore either, so that figures. It could maybe be solved with a synchronous diode, to mimic a bootstrap diode but upside down. Else, there's the full isolator circuit, which is a whole lot more bother, and is also a different market segment. (There are some AD and TI isolators with integrated DC-DC converters that would be very attractive here.)Quote from: MagicSmoker on April 06, 2019, 11:09:05 amIn other words, like this. Note that SiLabs parts aren't rated for DC consistency, or at least none last I checked. The trick with all of these devices (gate drivers and digital isolators), is they only communicate in pulses. There's a latch on the high side, and it's set or reset when a rising or falling edge is received. If no edge is received but noise upsets the state, now you have opposite logic states across the isolator until the input makes a complete cycle. The ADuM parts claim to use a ~10s µs refresh, with a default dead-line condition if no pulses are detected (a missing pulse detector). I'm not sure about the TI parts.This makes me leery of SiLabs parts (and maybe TI) for lower frequency, non-error-tolerant applications (like gate drives), but the others seem okay.Incidentally, if using optoisolators, be very careful of the isolation dV/dt and voltage step ratings. 6N136 for example is often rated very differently from others (lots of V/us, but at a step of like 5V, of course it's not going to do anything!). SFH6345 is the preferred equivalent: basically a 6N136 with better shielding and no base pin connection (which is where most of the dV/dt coupling occurs). Integrated logic receivers (like 6N137 and various HCPL and other devices) are usually pretty good. If you want a more integrated device, there are optos with full size MOSFET (and IGBT!) drivers included.And by IGBT, I mean, higher voltage rating, lots of amps output, options for external drive transistors (so there's actually two smaller gate drivers inside, to drive those, to drive the IGBT), desat protection (fault feedback), soft shutdown and so on. The full featured part I think is like $10/ea -- but this is a hell of a lot cheaper, and smaller, than rolling all of that yourself. It's a good deal!Anyway, I digress;Quote from: ZeroResistance on April 06, 2019, 05:56:43 pmOops, I should say vector sum, if that's meaningful. Or RMSsumas opposed to RMSmean. So really, just RS. Or RSS. Not RMS.In short, rise times stack (a filter chain is always slower than its component parts), but they don't add arithmetically.For loads over 1nF equivalent, it's probably fine to use just the RC time constant, and ignore the driver intrinsic speed (which will be much smaller than the time constant).Tim

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: April 07, 2019, 06:08:10 am
content: Quote from: T3sl4co1l on April 06, 2019, 07:37:21 pmMany thanks for the extended reply and the links provided.So, how does one calculate the vector sum or rss?The IRF540 has a Qg(tot) of 71nC, so that gives it a C(eff) of ~7nF at Vgs(on) of 10V. So in this case is it fine to ignore the driver speed?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 07, 2019, 06:21:13 am
content: Just sqrt(a^2 + b^2 + ...). The Pythagorean distance, if they were dimensions.Yeah, ~7nF is enough not to worry about it.Tim