Effective mobility in MOSFET - Page 1
Forum section: electronics / beginners

author: bonzer
author_rank: Regular Contributor
timestamp: July 20, 2019, 01:06:23 pm
content: Hello everyone! Please help me to understand how to find the mobility that we use in current equation of a MOSFET when dealing in detail with microelectronics for example: I have an nMOS with the p type "well" (I'm not sure about the term) that has Boron atoms in a concentration NB and Gate, Drain terminals drugged by Phosphorus atoms.As the free carriers (electrons in this case) inside the channel move through Boron, then I have to look at the mobility as function of Boron concentration right? (so it's useless for me to know the type of dopant used for gate and drain terminals, I could care less about the phosphorus ?) . I mean, what I try to do is to understand how properly use this graph to find the mobility (look at the attachment)

author: bson
author_rank: Unknown
timestamp: July 20, 2019, 04:44:52 pm
content: I would assume that majority carrier (electrons out of the n-doped terminals) mobility in the channel (p-doped with boron in your example) is the mobility that matters. But there may well be a marginal minority carrier lack of mobility (holes being less mobile than electrons) that might slightly degrade overall small-signal mobility around the quiescent/operating point (assuming saturation mode). I'm just guessing though.

author: bonzer
author_rank: Regular Contributor
timestamp: July 20, 2019, 06:00:00 pm
content: The problem is that if we assume I'm right and what is rappresented in the graph is the mean through which carriers flow, then it looks kinda strange because the mobility inside Boron (and therefore of electrons) is from the graph slower than that inside Phosphorus (of holes) which would not be true because electrons are usually faster than holes.

author: rfeecs
author_rank: Frequent Contributor
timestamp: July 20, 2019, 09:09:53 pm
content: Your plot is not the mobility "inside Boron". It is a plot of mobility inside Silicon, doped with either Arsenic, Boron or Phosphorus.Here is a similar plot:from here:https://ecee.colorado.edu/~bart/book/book/chapter2/ch2_7.htmFor an NMOS FET, use the electron mobility.

author: bonzer
author_rank: Regular Contributor
timestamp: July 20, 2019, 09:45:13 pm
content: Thanks for the answer. Well I knew that we were talking about dopants I just wanted to focus on my real doubt. I anyway almost got it with your help. Now what I understand is that it's the mobility of electrons within the phosphorus-doped silicon, or holes within the boron-doped silicon. And that makes sense with the values.But in an nMOS I have electrons from phosphorus moving through p-type because the n-channel is built inside the p-type body (made for example of boron-doped silicon) and this confuses me.How to deal with that? How to find the mobility? Inside current formula they indicate for nMOS mu_n , and I suppose because they want electrons mobility through the channel, but what is the concentration? Is it of the dopant of the body? If that's the case then where do I find the electrons mobility inside Boron - it's an acceptor so it has to do with holes mobility and not electrons.

author: rfeecs
author_rank: Frequent Contributor
timestamp: July 20, 2019, 11:53:27 pm
content: My naive thinking is that the mobility is limited by scattering, or sort of bumping into something in the channel. From the above reference:QuoteSo for NMOS, I would use the electron mobility curve and the total donor + acceptor density in the channel. You may have a p well in an n substrate, so in that case add both doping levels together.

author: bson
author_rank: Unknown
timestamp: July 21, 2019, 05:34:52 pm
content: There are of course all kinds of effects, and I'm sure minority mobility factors into one or more of them in some way. I don't think any of them factor into µ though, as that's used for all kinds of basic relationships, like Id, that the various effects then apply to. It makes best sense to me that µ is purely electron mobility in the channel for NFETs and hole mobility in the channel for PFETs; in other words, it needs to be a process-specific constant independent of geometry. (Geometry being factored separately.) If you look at the equations for Ids, it is proportional to µ regardless of whether in linear or saturation mode; this couldn't be true if it weren't simply a constant value for majority mobility in the channel.

author: Wimberleytech
author_rank: Super Contributor
timestamp: July 21, 2019, 09:51:44 pm
content: Quote from: bonzer on July 20, 2019, 01:06:23 pmI am going to try to answer your question in multiple parts. Here is the first."Equation of a MOSFET"Which equation are you talking about? There are many. It is more proper to think of the "equations" as "models" for a MOSFET. SPICE (from Cadence, etc.) probably supports 40 or so models (I have not looked in a while). The simplest model is the well-known Schichman-Hodges model. It is the simple square-law model where mobility is constant. A very crude model but useful for hand calculations. It does not account for the fact that mobility is not constant in the channel due to velocity saturation and other things. The next level of complexity in the SPICE world is the Frohman-Grove model (essentially the Level-2 model). It does a better job of providing parameters to model mobility variation due to terminal conditions. Then there is the Level-3 empirical model and it goes on and on. The bottom line: trying to get a precise value for mobility at zero field (which is what plots such as this are giving you) is kinda useless. Well, maybe not useless if you appreciate (up front) that for a given set of terminal conditions, you will not get the current you expect from the simple model. The simple equations can give a great deal of insight into how a circuit works and which levers you need to move to make it perform better.

author: Wimberleytech
author_rank: Super Contributor
timestamp: July 21, 2019, 10:05:43 pm
content: Quote from: bonzer on July 20, 2019, 01:06:23 pmThis plot does not apply to the operation of an MOS transistor--don't use it for that. This plot can be used to determine the conductivity of doped silicon (e.g., a p+ doped resistor). Mobility of the channel of an MOS transistor is the mobility of the "inverted" silicon. It is much lower. Typical mobilities for Nch and Pch long-channel transistors modeled with the Level-1 model are 600 and 300 respectively (cms/V-s).

author: Wimberleytech
author_rank: Super Contributor
timestamp: July 21, 2019, 10:10:30 pm
content: Quote from: bson on July 21, 2019, 05:34:52 pmIf you were to take a transistor and measure IDS vs VDS and VGS in saturation...and then curve fit to come up with a number for mobility, you will find that the mobility extracted does not give a very good IDS in the so-called "linear" region (I prefer "non-saturation" region).

author: bonzer
author_rank: Regular Contributor
timestamp: July 24, 2019, 01:01:55 pm
content: Quote from: Wimberleytech on July 21, 2019, 10:05:43 pmThanks for your response. You got me, my doubt is right here. Yes, I understand you at this point, I've already seen that at the end it's lower.I've never heard about this concept of inverted silicon. But what I know is that I've seen somewhere that they used as approximation in this case for the mosfet mobility, the mobility from the graph in case it's nMOS: "mu_n" this way: mu_mos = 0.5*mu_n(NA). So in an nMOS for istance it can be approximated to half of the mobility from the graph of the electrons inside phosphorus doped silicon at the concentration NA of the boron that we have in the bulk. (assuming that there's only boron doping in the silicon and no n-pre-doping).But what's the origin of this stuff? It kinda surprised me. Have you ever heard about this approximation? If yes, is it always valid?

author: Wimberleytech
author_rank: Super Contributor
timestamp: July 24, 2019, 02:13:39 pm
content: QuoteSorry, sloppy language on my part. I should have said "inversion layer" which is the conductive region below the gate that forms once the the gate-source voltage is greater than the threshold voltage (even this is an approximation).

author: Wimberleytech
author_rank: Super Contributor
timestamp: July 24, 2019, 02:20:15 pm
content: QuoteNo, I have never heard of this approximation and would be interested to see your reference where it is cited.The reason mobility is different in the inversion layer versus bulk silicon is similar to the difference in your mobility driving the autobahn vs. a narrow dirt road. The inversion layer is very thin whereas bulk silicon is the wide open spaces!!

author: bonzer
author_rank: Regular Contributor
timestamp: July 24, 2019, 05:37:33 pm
content: Oh thanks for the explanation, now I got it! Unfortunately I have no reference because this was one of some exercises that a (italian) university professor solved.

author: Wimberleytech
author_rank: Super Contributor
timestamp: July 24, 2019, 06:42:37 pm
content: Quote from: bonzer on July 24, 2019, 05:37:33 pmYou are welcome...happy to answer questions about this topic!!