hybridfree/eevblog-posts huggingface dataset:
Switch between two inouts - Page 1
Forum section: electronics / general

author: Prehistoricman
author_rank: Regular Contributor
timestamp: February 25, 2020, 04:47:04 am
content: I'm writing a PS/2 mouse driver and I would like to be able to switch the input signals, CLK and DATA, between a legit PS/2 port and a PS/2-USB bridge.Into the top module I have both sets of signals defined, and my switch between USB and PS/2:Code:inout PS2_CLK, PS2_DATA;inout USB_CLK, USB_DATA;input SW15;And these are connected to a mouse transceiver module that has a single pair of inouts for data and clk.My naïve first attempt was this:Code:MouseTransceiver mt (.RESET(RESET),.CLK(CLK),.CLK_MOUSE(SW15 ? PS2_CLK : USB_CLK),.DATA_MOUSE(SW15 ? PS2_DATA : USB_DATA),...But this solution gives me multi-driven nets. I don't know how to write what I'm looking for.

author: ataradov
author_rank: Super Contributor
timestamp: February 25, 2020, 05:09:05 am
content: I don't think it is possible to do that in FPGA.All inout stuff must happen in the pin driver on the top level.So MouseTransceiver must have input, output and direction controls for both sides. And they will turn into inout signal later.

author: Prehistoricman
author_rank: Regular Contributor
timestamp: February 25, 2020, 05:55:18 am
content: Quote from: ataradov on February 25, 2020, 05:09:05 amAha. So in the top module I'd had something combinational deciding, based on the data direction and switch, which signals to route.This is what I came up with (it works):Code:assign CLK_MOUSE_IN = SW15 ? PS2_CLK : USB_CLK;assign DATA_MOUSE_IN = SW15 ? PS2_DATA : USB_DATA;//Disable USB outputs if SW15 assertedassign USB_CLK = SW15 ? 1'bZ : (CLK_MOUSE_OUT ? 1'b0 : 1'bZ);assign USB_DATA = SW15 ? 1'bZ : (DATA_MOUSE_OUT_EN ? DATA_MOUSE_OUT : 1'bZ);//Disable PS/2 outputs if SW15 not assertedassign PS2_CLK = ~SW15 ? 1'bZ : (CLK_MOUSE_OUT ? 1'b0 : 1'bZ);assign PS2_DATA = ~SW15 ? 1'bZ : (DATA_MOUSE_OUT_EN ? DATA_MOUSE_OUT : 1'bZ);It's unfortunate that I can't get this functionality with the inouts in the transceiver module. Do you know if that kind of thing would be possible in SystemVerilog or VHDL?

author: ataradov
author_rank: Super Contributor
timestamp: February 25, 2020, 05:57:37 am
content: It is not about the language. It is impossible in the FPGA fabric itself. Tri-state in-out signals only exist in the I/O cells. The rest of the logic must have defined direction.
Beginner reg question - Page 1
Forum section: electronics / general

author: TheGreatNed
author_rank: Contributor
timestamp: February 24, 2020, 11:02:07 pm
content: Hi,If I read and write to a simple reg on the same rising clock edge, is the read value guaranteed to be the old data?I.e:Code:reg[15:0] myreg = 0;...always @ (posedge clk)beginoutput_reg <= myreg;myreg <= myreg + 1;endoutput_reg is guaranteed to be the non-incremented (old) value, right?

author: ejeffrey
author_rank: Super Contributor
timestamp: February 24, 2020, 11:05:08 pm
content: Yes and this is true regardless of the order of the statements as long as you use non-blocking assignment i.e. <=. You should always use non blocking assignments in a clocked block.

author: TheGreatNed
author_rank: Contributor
timestamp: February 25, 2020, 01:45:18 am
content: Quote from: ejeffrey on February 24, 2020, 11:05:08 pmthank you
Altera to Xilinx - Page 1
Forum section: electronics / general

author: blacksheeplogic
author_rank: Frequent Contributor
timestamp: February 24, 2020, 10:37:22 pm
content: I have a few personal projects using the Altera Cyclone V SOC with my own custom Linux kernel + device driver. I don't expect many problems building a kernel and updating the device driver but I'm not sure about the switch from Quartus, and in particular Platform Builder since I have quite a bit of custom QSYS modules written (mostly mm slaves). It's been 5-6 years since I last touched ISE as well.Any thoughts on the difficulty or experience moving from Altera Cyclone V SOC over to using a Xilinx Zynq?

author: RoGeorge
author_rank: Super Contributor
timestamp: February 24, 2020, 11:41:49 pm
content: It is not ISE any more, now it is called Xilinx Vivado, and was completely rewritten, not just an ISE cosmetization. Vivado is not backwards compatible with ISE, for example constraints are now written in Tcl.However, the main steps remains the same between Quartus and Vivado. No idea how easy or ugly will be to port a complex project from Cyclone to Zynq.
Basic Clock and PLL Question -- reading datasheets - Page 1
Forum section: electronics / general

author: TheGreatNed
author_rank: Contributor
timestamp: February 20, 2020, 11:42:02 pm
content: Hello good FPGA people,I have a Cyclone 4 dev kit with a 50MHz default clock as defined in the .sdc file. I'm using a PLL IP block to get a 125MHz output. Question 1: Can I simply feed this clock to my design instead of the 50mhz one and expect all the registers to work normally? (basically free speed?)I'm wondering how fast I can go based on the below datasheets (I'm using a EP4CGX150 with speed grade 'C7')^This datasheet seems to say I can use the embedded multiplier and memory blocks at up to 437.5MHz (without consequence?)... but what about the everyday gates/registers/LUTs?^This datasheet seems to say that the input to any PLL can be <=450MHz, and the output "to global clock" can also be <=450mhz. What things do i need to consider if i dial up my core clock right to 450mhz via a pll?Thanks

author: hamster_nz
author_rank: Super Contributor
timestamp: February 21, 2020, 12:32:46 am
content: Your timing report will tell you if your logic is too complex for the desired clock rate. If you have correctly constrained your incoming clock to 20 ns, the tools will usually work out all derived timing constraints (8 ns for the 125MHz logic).Datasheet timing show the performance of the individual resources (FFs/LUTs/PLL...), and not the performance of the overall system built from those resources. You will have the timing requirements of the resources, plus additional 'routing' delays due to the connections between parts.125MHz isn't that fast for a Cycleon IV FPGA - It will most likely work OK unless it has lots of logic.

author: TheGreatNed
author_rank: Contributor
timestamp: February 21, 2020, 04:29:38 pm
content: So what does the 437.5mhz number mean exactly in the above datasheet?Do I need to add an entry in my SDC file telling quartus about my 125mhz PLL and where its going?

author: NorthGuy
author_rank: Super Contributor
timestamp: February 21, 2020, 06:42:59 pm
content: Quote from: TheGreatNed on February 21, 2020, 04:29:38 pmIt means that if you feed a clock signal above 437.5 MHz to the clock distribution system, they cannot guarantee that the clock distribution system will work on every device even if the voltage and temperature are within the specified range.Besides the clock distribution system, there are are things inside FPGA which have their own timing characteristics. You need to make sure that your design doesn't violate any of them. Generally, it is difficult to design something that works at the highest clock frequency. Designing for 200 MHz clock is easier.

author: TheGreatNed
author_rank: Contributor
timestamp: February 22, 2020, 12:10:05 am
content: Awesome, thank youit seems that "derive_pll_clocks" is all that is required in the SDC file to inform the compiler of my 125mhz clock. Easy enough
Understanding Skid Buffer Mechanism - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: February 17, 2020, 02:39:16 am
content: I have some questions abouthttp://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html1) Why is skid buffer designed to be2-entries FIFOinstead of just 1-entry FIFO ?Quote2) Quoted from the article , whytwo cycles to start, and two cycles to stop?

author: OwO
author_rank: Super Contributor
timestamp: February 17, 2020, 03:19:43 am
content: You could make a 1 entry skid buffer:https://zipcpu.com/blog/2019/05/22/skidbuffer.htmlbut as the skid buffer itself adds a slow mux to the datapath you need one more register to achieve good timings

author: promach
author_rank: Frequent Contributor
timestamp: February 17, 2020, 03:34:24 am
content: QuoteWhat do you exactly mean byslow mux?QuoteIn the zipcpu blog article you linked above, whythe outgoing stall signal (i.e. !o_ready) can only be a registered signal?

author: OwO
author_rank: Super Contributor
timestamp: February 17, 2020, 07:27:55 am
content: On an FPGA the mux adds one LUT to the data path and adds delay. It's not the LUT that's slow, it's routing the signal from unrelated logic that is possibly far away, so you will want to register it first before doing anything.Ideally all outgoing and incoming signals should be registered for best performance.

author: promach
author_rank: Frequent Contributor
timestamp: February 18, 2020, 06:22:23 am
content: However, it seems like skid buffer is way too over-simplication of my situation withexternal memory.Note thatRREADY of AXI master is asserted low for more than few clock cycles which could be due to interconnect priority arbitration or due to destination cache storage is fullTherefore, skid buffer which could just store two entries might not be enough.But I suspect that skid buffer itself provides negative feedback signal to ARVALID of AXI master ?Please correct me if wrong
AXI arvalid signal - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: February 05, 2020, 03:21:57 am
content: I have question aboutAXI arvalid signal used for interfacing with DDR axi controller in Zynq.if I do not removei_axi_arready, I will have deadlock issue.If I removei_axi_arready, I will have issue arising from DDR periodic mechanism such as auto-refresh.What could I do ?Someone told me the following which I do not understand:VALID signal needs to be set (initially) independent of READY signal, and then only ever adjusted if !(VALID && !READY)Code:always @(posedge clk)beginif(reset) o_axi_arvalid <= 0;// AXI specification: A3.3.1 Dependencies between channel handshake signal// the VALID signal of the AXI interface sending information must not be dependent on// the READY signal of the AXI interface receiving that information// this is to prevent deadlock// since AXI slave could waits for i_axi_arvalid to be true before setting o_axi_arready true.// Note: VALID cannot be dependent upon READY, but READY can be dependent upon VALID// VALID signal needs to be set (initially) independent of READY signal,// and then only ever adjusted if !(VALID && !READY)else o_axi_arvalid <= /*i_axi_arready &&*/ (!cache_is_full);end

author: promach
author_rank: Frequent Contributor
timestamp: February 24, 2020, 03:08:40 am
content: Which waveform follows AXI spec ?

author: langwadt
author_rank: Super Contributor
timestamp: February 25, 2020, 12:05:46 am
content: what deadlock issues?

author: promach
author_rank: Frequent Contributor
timestamp: February 25, 2020, 03:02:53 am
content: Code:else o_axi_arvalid <= /*i_axi_arready &&*/ (ddr_address_range_is_valid) && o_axi_rready;Thedeadlock issuehad been solved. Please correct me if wrong.But why myAXI codingstill failAXI Protocol Checker IP for error bits 59 and 78And just for information, AXI Protocol Checker IP raised the errors for both AXI interfaces even when RREADY and ARREADY signals are asserted high (free-flow AXI bus without any barriers)In other words, the AXI code is not AXI-compliant in the simplest test scenario.
Unable to download iCEcube2 from Lattice - Page 1
Forum section: electronics / general

author: sporadic
author_rank: Regular Contributor
timestamp: February 09, 2020, 02:54:58 pm
content: There are no download links showing on Lattice's product website for iCEcube2, and their support page is errors out for me so I can't contact them. I found a link to the download (http://www.latticesemi.com/view_document?document_id=52183), but that errors out too. Anyone know of anywhere else I can download it or is it working for anyone else? Their free license generator still works so that's not an issue.thanks,-shelby

author: aheid
author_rank: Regular Contributor
timestamp: February 09, 2020, 06:18:29 pm
content: Not sure if it's related, but I got a lot of server errors today on pages I've accessed successfully earlier this week. So maybe they're doing some server maintenance or one of their servers is acting up.

author: Dmeads
author_rank: Regular Contributor
timestamp: February 16, 2020, 08:15:35 am
content: worked just now for melattice IceCube rocks!
Which FPGA does Siglent SDG2000x has? - Page 1
Forum section: electronics / general

author: RoadRunner
author_rank: Frequent Contributor
timestamp: February 27, 2020, 03:47:58 pm
content: I just watched dave's teardown of siglent SDG2000x. I am wondering which FPGA does this signal gen has? Dave mentions it may be some Altera/Intel , Does any one has any idea about the exact part?Any help will be appreciated.Regards
Xilinx Video Series - Page 1
Forum section: electronics / general

author: asmi
author_rank: Super Contributor
timestamp: January 24, 2020, 10:42:33 pm
content: I came across this series of posts, and to me they seem like a great set of tutorials on how to deal with video data inside FPGAs, which include some debugging techniques. Link:https://forums.xilinx.com/t5/Video/Xilinx-Video-Series/td-p/849583

author: Dmeads
author_rank: Regular Contributor
timestamp: January 29, 2020, 06:11:23 am
content: Sweet thanks for sharing! I have wanted to start with video applications for a while now!
lattice  batch compilation - Page 1
Forum section: electronics / general

author: fabiodl
author_rank: Frequent Contributor
timestamp: February 07, 2020, 04:32:01 am
content: I need to batch compile a project composed of multiple verilog files.For simplicity,assume there is a top module in file top.v instantiatian sub (declared in sub.v).ispflow does not allow to specify multiple files. If the -i option is specified multiple times the following error id given:Error: Input File already enteredConversely, if only the top module file is specified, Synopsys Verilog Compiler fails with the following errorReference to undefined module subWhat is the correct way to do a batch compilation?

author: fabiodl
author_rank: Frequent Contributor
timestamp: February 10, 2020, 10:20:17 am
content: if someone has the same need, I found out that it is possible to use c:/ispLEVER_Classic2_0/lse/bin/nt/synthesis.exe to crate ad edf file, and then provide such file to ispflow.The output jed however missed the usercode, and diamond programmer fails in verifying it. it is necessary to add UH00000000* at the end of the jed file.
Xilinx Impact 10.1 incorrectly identifying SpartanII FPGA as VirtexE - Page 1
Forum section: electronics / general

author: vincei
author_rank: Contributor
timestamp: January 23, 2020, 12:34:24 am
content: I have a collection of boards that have a Xilinx SpartanII X2S300E FPGA on them. I built a board that allows me to get to the device using JTAG, however, in IMPACT when I scan the JTAG chain it is reporting the devices as a Virtex XCV300e. I don't know whether this will be an issue going forward or whether it is a known none issue? I would have expected that these are quite different devices so misidentifying them would not be good karma.Anyone got any ideas? Should I not worry about this? I note that strapped mode pins M0, M1 and M2 as reported by IMPACT match how the FPGA is strapped in the boards circuit diagram.I've attached screen grabs of the device on the board and the output from impact.NB. I believe 10.1 is the last version of ISE that supports Spartan II which I absolutely need to work with this board.Thanks!Vince

author: laugensalm
author_rank: Regular Contributor
timestamp: January 23, 2020, 09:51:16 am
content: If I recall correctly, they have gotten the same JTAG ID by accident.But it's been many years...I might be wrong, and can't verify.

author: rstofer
author_rank: Super Contributor
timestamp: January 23, 2020, 05:43:54 pm
content: The very first Google response is from Xilinx:https://www.xilinx.com/support/answers/12995.htmlApparently, everything will work out fine.

author: vincei
author_rank: Contributor
timestamp: January 23, 2020, 07:31:27 pm
content: LOL. My mistake was searching with the actual part numbers. Then again I didn't use Google to search.Thanks for the info,Cheers,Vince

author: vincei
author_rank: Contributor
timestamp: January 23, 2020, 07:32:46 pm
content: Quote from: laugensalm on January 23, 2020, 09:51:16 amThanks. Yeah, it's amazing when you look back and realise this is stuff from 15 years ago. Time flies!-Vince
Gigabit Ethernet Example code - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 17, 2020, 12:38:49 pm
content: Hi,I'm kinda newbie into the FPGA world, I have done some basic stuff like USART, SPI etc..Now I want to use a Gigabit Ethernet core on spartan 6. I have found this one in opencores.orghttps://opencores.org/projects/ethernet_tri_modeI want to know if there is any example for this one or any other open core one, what PHY should I use (or I just can use any GMII PHY I can find)? any Example or path to learn this thing would be highly appreciated.

author: hamster_nz
author_rank: Super Contributor
timestamp: January 18, 2020, 12:05:04 am
content: I wrote this for the PHY on the Digilent Nexys Video:https://github.com/hamsternz/FPGA_GigabitTx

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 18, 2020, 07:17:06 am
content: Thanks for sharing!Does it use thehttps://opencores.org/projects/ethernet_tri_modecore?

author: hamster_nz
author_rank: Super Contributor
timestamp: January 18, 2020, 07:48:43 am
content: Quote from: ali_asadzadeh on January 18, 2020, 07:17:06 amNo

author: laugensalm
author_rank: Regular Contributor
timestamp: January 18, 2020, 06:34:25 pm
content: I'd throw in that one:https://github.com/yol/ethernet_mac/It's VHDL though. But generic enough to run on Xilinx/Lattice, etc.There are also some more exotic implementations using Forth driven stack machines, like this one:https://excamera.com/files/j1.pdf. Some inspiration you might also get from the Lattice EVDK reference Gbit streaming reference design.If you're used to standard uC DMA approaches, you can get a pretty good performance with the above core plus a DMA auto buffer packet FIFO, as described here:https://section5.ch/index.php/2017/05/10/dma-autobuffering-techniques/.With the GMII interface you're on the safe side with plenty of matching PHYs, only RGMII was found to be a bit tricky with regard to DDR capable I/O. So if you're routing your own board, you might want to cross check with existing refdesigns.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 18, 2020, 07:21:43 pm
content: Thanks for sharing, I want to test and see some UPD or TCP packet sending and receiving too.
What caused high spikes in FPGA market in 2000 - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: January 11, 2020, 05:35:15 am
content: HiI was looking at stock of Xilinx and Lattice Semiconductor and saw both had pretty high spikes in their stock value around 2000-2001. I was a wee little lad at the time and wondering what caused this jump?Thanks!-Dom

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 11, 2020, 05:42:25 am
content: It was a Dotcom boom, nothing else. I got my USA entry as software dev to work in finance industry for this boom as many others at that era.Basically someone wrote a software to increase amount of participants in stock game may be thousand fold. The internet happened. The computerization reached the investment game and millions of retiring boomers with money. That is just mass effect. Nothing to do specifically with any tech company. It was as if someone poured a WD-40 on old steam engine and things went crazy. It is force of nature, there is no single individual to attribute the success of what happened in 2000.

author: TomS_
author_rank: Frequent Contributor
timestamp: January 11, 2020, 10:57:35 pm
content: The period is certainly coincidental with (the end of) the dot com boom. It peaked and crashed in the early 2000's.Anything tech was sizzling hot property back then.
External 10Gb/s 25Gb/s ethernet phys? - Page 1
Forum section: electronics / general

author: nctnico
author_rank: Super Contributor
timestamp: January 02, 2020, 10:15:53 am
content: I'm doing some research on supporting 10Gb/s and 25Gb/s links on an FPGA. Especially 25Gb/s becomes very expensive so I'm thinking about using an external which interfaces between an SFP port and the FPGA. Is anyone aware of suitable phys for this purpose? I already looked a bit around on Marvell's and Broadcom's websites but didn't manage to spot a device which seems suitable.

author: Rerouter
author_rank: Super Contributor
timestamp: January 02, 2020, 10:25:19 am
content: I have limited knowledge but can I ask what about marvell and broadcom make them unsuitable,e.g looks like marvelss meet what your asking forhttps://www.marvell.com/transceivers/alaska-x-gbe/There is also microsemihttps://www.microsemi.com/product-directory/10g-ethernet-phys/3924-vsc8491#overviewThere is lots of discussion of options for this kind of stuff on the xilinx forums,There are modules that are meant to be fairly plug and playhttps://www.xilinx.com/products/boards-and-kits/1-3y8uy5.htmlThere are other forums discussing that you can use the marvel chips with only there public datasheets, so I assume the NDA crap is what has you on edge?

author: nctnico
author_rank: Super Contributor
timestamp: January 02, 2020, 10:35:07 am
content: Thanks for your input! It is not that I want to avoid Marvell but NDA is a PITA indeed and I rather avoid that. Broadcom seems more like a challenge to get datasheets from especially when the volumes aren't that high. I didn't look at Microsemi yet and didn't check the Xilinx fora as well so those are good pointers.

author: asmi
author_rank: Super Contributor
timestamp: January 02, 2020, 01:20:20 pm
content: 10G is directly supported by Kintex transceivers (TRAP ALERT - watch out for right package/speed grade combination!).On a PHY side, take a look at VSC8491 chip from Microsemi, or VSC8489 for dual-10G PHY. Hint - since Microsemi has been acquired by Microchip, search for that chip on Microchip's site instead of Microsemi's one - this way you can download full datasheets without any of Microsemi's registration crap.
FPGA Delta-sigma modulator IP - Page 1
Forum section: electronics / general

author: insert
author_rank: Newbie
timestamp: December 25, 2019, 08:02:00 pm
content: Hi All! This is my first topic hereI need PCM2SDM(DSD512) converter, now i use Spartan-6 on my devboard with 8ch DSD DAC.I2S S\R = 192K, NoiseFloor (S/N) <= -140dbMay be somebody have experience or examples.
FPGA with two DDR2/3 PHY and free dev tools - Page 1
Forum section: electronics / general

author: Boscoe
author_rank: Frequent Contributor
timestamp: December 21, 2019, 11:10:30 am
content: Hi all,I’ve been looking through the Xilinx and Intel websites trying to find an FPGA as above. I have two data streams in my project would rather not have to design a build a method for them to share the same memory. Anyone know of any parts? A dev board with reference design would be magic!ThanksBoscoe

author: apblog
author_rank: Regular Contributor
timestamp: December 23, 2019, 08:23:47 am
content: I can't help you with your actual question.But it's super easy to share 1 DDR controller between two or more IP blocks. With Xilinx, I would use a Zynq that has a hard memory controller, and connect to it with an AXI DMA IP block, 1 for each stream.You can do the same thing in Artix too, with the Memory Interface Generator.

author: asmi
author_rank: Super Contributor
timestamp: December 23, 2019, 05:05:52 pm
content: Seriously? Using Zynq with all complexities that it brings, only for memory controller?To OP: 7 series FPGAs from Xilinx allow implementing any number of independent DDR2/3 controllers - as long as you have enough IO pins to physically implement interfaces.

author: nctnico
author_rank: Super Contributor
timestamp: December 23, 2019, 06:11:20 pm
content: Quote from: Boscoe on December 21, 2019, 11:10:30 amOn Spartan6 you can have multiple memory interfaces to the same memory which then get multiplexed onto the physical interface towards the memory. Works like a charm. Do keep in mind that DDR memory has some variable latency so you'll need some (FIFO) buffering if you want to store a continuous stream of data.Another option is to use an internal adres/data bus which has the memory mapped into a certain area. The bus arbiters can then take care of concurrent data transfers to and from the memory. In one of my designs I used 2 memory interfaces and mapped the same memory into the memory map twice at different addresses. This allows for two devices to access the memory simultaneously without giving up any flexibility.

author: apblog
author_rank: Regular Contributor
timestamp: December 23, 2019, 10:36:06 pm
content: *deleted*
Schematic of the circuit for XILINX XCVU13P VIRTEX. - Page 1
Forum section: electronics / general

author: TRYPTYK Group
author_rank: Newbie
timestamp: December 23, 2019, 09:17:53 am
content: I'm making a project of the PCB board for XILINX XCVU13P VIRTEX.I need a schematic of the circuit for XILINX XCVU13P VIRTEX.Thank you for your help.

author: rstofer
author_rank: Super Contributor
timestamp: December 23, 2019, 03:56:44 pm
content: Start here:https://www.xilinx.com/support.html#documentationGoogle turns up some of the documentation with a simple search by part number.
I am looking for a Pearson who will design the board PCB for FPGA.  - Page 1
Forum section: electronics / general

author: TRYPTYK Group
author_rank: Newbie
timestamp: December 09, 2019, 09:37:37 pm
content: Hello,I am looking for a Pearson who will design the board PCB for FPGA xilinx.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 10, 2019, 06:47:04 am
content: I can do it for you, send me a pm with the design details
[SOLVED] ZynqMP boot Linux from MMC - Page 1
Forum section: electronics / general

author: gvz
author_rank: Contributor
timestamp: December 03, 2019, 03:06:17 pm
content: Hello,I am using an UltraZed EG SOM with IO Carrier board, and I am trying to configure Linux from MMC.This board have 2 SD/MMC controllers: controller #0 is connected to MMC, while controller #1 is connected to SD card.Xilinx's UG114 does not explains what is the correct PetaLinux configuration to boot from MMC, however petalinux-config allows to boot from SD card.So I can boot from SD card, but I don't know how to configure u-boot from MMC.Do someone has achieved such a configuration and can give an hint to solve this problem ?Thanks,g.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: December 03, 2019, 03:20:58 pm
content: Have you talked to the engineers at Avnet? This sort of stuff should be in the device documentation. And, if not, the support engineers should be able to quickly answer this question.

author: gvz
author_rank: Contributor
timestamp: December 03, 2019, 08:59:52 pm
content: Quote from: colorado.rob on December 03, 2019, 03:20:58 pmYeah. UG1137 sectioneMMC18 Boot Modegot the solution.Make an SD image with petalinux, boot it, make partitions of eMMC (FAT and ext4), copy rootfs to MMC's EXT4 partition and SD FAT partition files, basically BOOT.bin and image.ub to MMC's FAT partition.I also used an uEnv.txt file into the MMC FAT partition to set root=/dev/mmcblk0p2 into the u-boot's bootargs environment variable.Regards.s.
How to change slew rate in quartus pin planner? - Page 1
Forum section: electronics / general

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 20, 2019, 04:04:52 am
content: So I was checkingV/ns profiles to see how fast these outputs switch and the lvl 2 is too high for my needs, I will either choose 0 or 1, now the only problem is that I cant seem to change it.How does one usually access these settings besides the drop down menu? Wich is stuck at 2 for some reason...Beautiful.

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 20, 2019, 04:32:31 am
content: can I ask help to somebody via pm? Instead of making these noob posts...is skype still a thing?

author: AndyC_772
author_rank: Super Contributor
timestamp: November 20, 2019, 06:55:45 am
content: If the slew rate is indeed something that can be changed on the device you're using - and I'm not sure whether there are multiple options on every device family - then I'd do it via the assignment editor. The pin planner is newer, and certainly a convenient way to drag & drop pin allocations, but it doesn't include all the options available.Which part are you using in your design?

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 20, 2019, 04:56:27 pm
content: You are right, changing from 10m08sce144c8g ( the cheapest of the 08) to 10m16sce144c8g I now see the option in the menu.This probably means, that I should avoid this chip, since .5ns rise time will cause ringing on a 1.6 inch trace, and possiby damage.

author: AndyC_772
author_rank: Super Contributor
timestamp: November 20, 2019, 05:10:01 pm
content: I'd be very surprised if any effect associated with a trace that short causes damage to anything. Without a detailed simulation using an IBIS model, I'm not sure how you'd know what ringing might exist on it in any case.Personally I'd just enable series termination in the assignment editor, or put a 33R resistor next to the pin, and not lose any sleep over it at all.

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 20, 2019, 07:35:35 pm
content: Yeah... I guess. It would be stupid to spend 37$ more just to not have to put termination resistors.But... I dont really know what I need in terms of luts, yet. still much work to be done to figure that out.Maybe the 16 is what I will need.

author: Giaime
author_rank: Regular Contributor
timestamp: November 29, 2019, 02:12:12 pm
content: Quote from: lawrence11 on November 20, 2019, 04:04:52 amYep, that's misleading. The drive strenght (thus the slow rate) can be alternatively selected by changing the I/O standard. LVCMOS is 2mA max, LVTTL is 8mA.

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 29, 2019, 11:00:23 pm
content: isnt lvc +-24 mA?
Lattice ispLever - Page 1
Forum section: electronics / general

author: vincei
author_rank: Contributor
timestamp: November 28, 2019, 01:07:35 pm
content: I created an account on Lattice.com to download ispLever to move a design I have from ABEL/Pals to Lattice 22v10 Gal's. I am not able to download the software after many days. Does anyone know if there's an alternate download site?-VinceThis is the error I've been getting for several days nowThe page or resource you have attempted to access requires a valid account. While most accounts are quickly created, some require further processing. Please be aware that it may take up to two business days for your account to fully activate. We apologize for the inconvenience. If you continue to have access issues after two business days please contact

author: rstofer
author_rank: Super Contributor
timestamp: November 28, 2019, 02:55:27 pm
content: Have you contacted Lattice? Maybe after the holiday...I created an account and downloaded ICEcube2 a couple of days ago and it went through quickly.

author: vincei
author_rank: Contributor
timestamp: November 28, 2019, 03:52:13 pm
content: Hi Rstofer,No, not yet. I created the account on Monday evening. I'll try again tomorrow and if it still isn't working I'll give them a call on Monday.Thanks!Vince
Quartus / QSYS - WSL - Page 1
Forum section: electronics / general

author: blacksheeplogic
author_rank: Frequent Contributor
timestamp: January 25, 2020, 04:05:56 am
content: Spent the morning making a small change in QSYS (should have been small anyway) but regeneration a QSYS project failed.1. RLDRAM II Memory ControllerYou may experience the above error when generating a UniPHY-based memory controller. The error occurs because one of the system environment variables 'TEMP' points to a network drive and not a local drive.OK, don't remember that being a problem but whatever... Edit the ENV's and reboot....2. EMIFError compilation of the sequencer microcode when generating the External Memory Interface UniPHY IPThis issue occurs when the PC Windows Subsystem for Linux parameter is enabled and a bash.exe process is seen in Windows Task ManagerThis problem is scheduled to be fixed in a future version of the Intel Quartus Prime software.Quartus 19 Lite is only available on Linux.Another reboot latter + a morning wasted rebuilding the QSYS and Quartus project it compiles.
Beginner Altera DE1-SoC Audio Equalizer - Page 1
Forum section: electronics / general

author: Xazch
author_rank: Newbie
timestamp: November 21, 2019, 03:28:08 am
content: Hey all,Is anyone here knowledge able on how to setup a DE1 SoC Signal processor? I've had a difficult time understanding how and where to start i feel the documentation is very scarce and on where i should start. it looks like a Qsys system would work best for this type of application.So far i only have impulse response for each of my signals i created in matlab that would convolude with the audio source to remove the frequency from the signal. this would be done with one of the switches on the dev board.my professor for signal processing suggested i do that and transfer it to vhdl.would anyone have some advice on how i should start?

author: Berni
author_rank: Super Contributor
timestamp: November 21, 2019, 06:31:38 am
content: Start by learning VHDL or Verilog as you will need it.The IP library in Quartus has a lot of DSP blocks such as FIR or IIR filters to make the most common types of filters. But you will still need to code the logic for interfacing the ADC/DAC to the FPGA to feed data trough the filter block.If you never used Quartus before first make a few simple projects like LED blinkers, or sound generation.

author: hamster_nz
author_rank: Super Contributor
timestamp: November 21, 2019, 06:49:44 am
content: I know this is most likely a heresy, but get yourself a Digilent PMOD I2S2. It has a dumb I2S ADC and an equally dumb I2S DAC. Just send clocks and bits at them and signals happen. It is only line level, but perfect for testing this sort of stuff.With one of these you can skip the complexity of using the processor to configure the onboard codec before it will even make a sound, and can focus on your DSP tasks.Once you get that working then look at moving to using the onboard codec.PM me - I have spare PCBs for a multiple 3.5mm stereo jacks to pin headers test jig that I think will be most helpful for your testing. Send me your email and you can see if it will be of use. Far, far better than cutting cables open.Nothing sounds as bad as misaligned audio - full noise at 0db, So used a scope or a tiny powered speaker rather than earbuds for testing. Save your hearing for later....
Microchip Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC - Page 1
Forum section: electronics / general

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: December 14, 2019, 06:21:54 pm
content: Announced the other day. PolarFire FPGA with hard 64-bit quad-core processor. Seems like an interesting device architecture. ...thoughts?https://www.microchip.com/en/pressreleasepage/microchip-unveils-PolarFire-SoC-early-access-program

author: lawrence11
author_rank: Frequent Contributor
timestamp: December 14, 2019, 10:24:21 pm
content: Pretty insane.

author: brucehoult
author_rank: Super Contributor
timestamp: December 14, 2019, 10:46:45 pm
content: At the summit they were showing off a board with both a Polarfire FPGA and an FU540 SoC as a dev system until they get the FPGAs with the FU540 actually inside them. They didn't say when or who would be able to get one, or the price.

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: December 14, 2019, 11:40:08 pm
content: Quote from: EverydayMuffin on December 14, 2019, 06:21:54 pmI will wait until they announce what the development tools will cost before getting excited. It seems they are offering micro-semi's Libero software with 60 day evaluation licence, and a conditional table of supported/unsupported chips. Who needs that shit. Sell chips and give away the software already.https://www.microsemi.com/product-directory/design-resources/1711-licensing

author: asmi
author_rank: Super Contributor
timestamp: December 15, 2019, 06:57:09 pm
content: I would love to play with this chip if it will be hobbyist-friendly - both physically (affordable price, reasonable ball pitch package), and from software standpoint.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: December 16, 2019, 06:09:33 pm
content: Quote from: asmi on December 15, 2019, 06:57:09 pmTotally with you. Polarfire FPGAs are attractive because their SoCs typically have much better power consumption characteristics than the big vendors. But their dev boards and software were expensive, as was their IP.Work with the Yosys folks and let me generate a bitstream with open source tools. Spend your development resources providing a good UI to integrate these tools.

author: asmi
author_rank: Super Contributor
timestamp: December 16, 2019, 09:05:42 pm
content: Quote from: colorado.rob on December 16, 2019, 06:09:33 pmI prefer using vendor tools because they are just better than any OS stuff I've seen at the moment. My point is there has to be a free version of tools which is good enough to actually use the chip to the full extent - meaning no BS like "you can use these HW blocks, but not these ones". It's OK to have paid versions of software, similarly I have no problems with paid IP as long as these purchases are not required to fully utilize the chip.
Fast Arbiters for On-Chip Network Switches - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: November 09, 2019, 12:24:04 pm
content: ForFast Arbiters for On-Chip Network Switches, what is the difference between Proposed-I and Proposed-II topologies ?

author: tggzzz
author_rank: Super Contributor
timestamp: November 09, 2019, 12:38:49 pm
content: What do you want us to do? Copy out the answer given on p668 of your reference?

author: promach
author_rank: Frequent Contributor
timestamp: November 11, 2019, 04:09:16 pm
content: Look at Figure 7 of the paper. Proposed II approach is faster than Proposed I approach
Quartus Prime (Time Quest) Difficulty Generating Report - Page 1
Forum section: electronics / general

author: TeddyPython
author_rank: Contributor
timestamp: November 09, 2019, 02:53:47 pm
content: Hi, I'm looking to investigate the setup times for a design I have. However, despite following AN 775 as best I as I can, I am not generating any outputs from my design. Instead all I see are two Data ports which I haven't declared myself in my design...Here is the pin planner - it shows these extra pins, but also my own data ports.Furthermore here are my declared ports in my top level file.Code:module bertfront(input clk,input inbitstream,input [1:0] control,// start,  resetoutput outbitstream,output reg ledstatus,output reg [31:0] totalbits,output reg [31:0] incorrectbits);Can anyone shed some light as to why I'm not seeing my own data ports in the timing analysis? If you need any more code I would be happy to share the entire project.
Lattice iCECube2 E2055 Error while doing placement of the design - Page 1
Forum section: electronics / general

author: raff5184
author_rank: Regular Contributor
timestamp: November 21, 2019, 04:43:34 pm
content: Hi,I am using Lattice iCECube2 to generate the Bitmap file for the iCE5LP4k FPGA, WLC36 type. I'm having a hard time trying to simply setting up an output pin.In myTopLevel.vCode:module Top_level (myOut);output myOut;assign myOut = 2'b10;...endmoduleAnd in the.pcfconstraint file I set the output pin C1Code:set_io myOut C1And I first have this warningW2806: Disabling output for IO myOut_pad since its DOUT0, DOUT1 and OUTPUTENABLE pins are dangling. Changed its output pintype to output disable (0000)followed by the errors:Error during automatic placementI2723: placment information file is dumped at : C:/lscc/iCEcube2.2017.08/sbt_backend/Projects/virgin_code/virgin_code_Implmnt\sbt\outputs\placer\Top_level.pcfI2709: Tool unable to complete IOPlacement for the designE2055: Error while doing placement of the design

author: iMo
author_rank: Super Contributor
timestamp: November 21, 2019, 05:29:10 pm
content: Quote from: raff5184 on November 21, 2019, 04:43:34 pmThe myOut is only 1bit wide..Try withassign myOut = 1'b1;orassign myOut = 1'b0;

author: raff5184
author_rank: Regular Contributor
timestamp: November 21, 2019, 06:02:38 pm
content: My bad, that was a typo, but yes, I have 1 bit only
A3PN060 & Libero IDE - Page 1
Forum section: electronics / general

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: November 04, 2019, 03:10:13 am
content: Hi TeamI found an old A3PN060 based dev board that I want to have a crack at. But I am having a bit of trouble with the first step which is to get the IDE working (in this case Libero IDE)I registered on Microsemi and tried to get the latest IDE (v9.2) fromhere, but when I click "Download Libero IDE v9.2 for Windows" it says "There was an error looking up the file you requested, LiberoIDEv92_WIN". Next I turned to searching online but I can't even find an installer for an older version of the IDE. I am guessing the website is a bit flaky because Microsemi (who acquired Actel) have recently been acquired by MicrochipSo with all that said, would you guys:Know of an alternative place to download the Libero IDE (v9.2 or v8.6 preferably)?Be able to recommend an alternative IDE that could work with the A3PN060?

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: November 04, 2019, 02:13:49 pm
content: For a ProASIC3 device (like your A3PN060) you can use Libero SoC v11.9 which is available onwww.microsemi.com.Libero IDE supports Antifuse and legacy flash devices.Libero SoC v11.9 supports RTG4, IGLOO2, SmartFusion2, SmartFusion, IGLOO, ProASIC3, RT ProASIC3 and FusionLibero SoC v12.0 supports PolarFire, RTG4, IGLOO2 and SmartFusion2Guide on how to install Libero SoC 11 here:https://www.epsglobal.com/about-eps-global/blog/june-2018/getting-started-with-libero-soc

author: Bassman59
author_rank: Super Contributor
timestamp: November 05, 2019, 04:53:11 pm
content: Quote from: EverydayMuffin on November 04, 2019, 02:13:49 pmYup, all of the above is correct.I've found the Libero IDE to be rather maddening, so instead of using it I run Synplify standalone and then run the Designer place-and-route standalone too.

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: November 06, 2019, 01:20:46 am
content: Quote from: EverydayMuffin on November 04, 2019, 02:13:49 pmThanks for that write-up, really helps put things in perspectiveQuote from: Bassman59 on November 05, 2019, 04:53:11 pmAm in process of getting a Synplify trial to see how that compares

author: Bassman59
author_rank: Super Contributor
timestamp: November 06, 2019, 04:52:17 pm
content: Quote from: ANTALIFE on November 06, 2019, 01:20:46 amNot necessary -- Libero ships with Synplify Pro (that targets only the Actel/Microsemi parts). After installing Libero you'll see it in your Start Menu -> Microsemi Libero SoC 11.9 -> Synopsys directory.Also included in that version of Synplify is the Identify debugger, basically their version of ChipScope.
Implementing Carry Look Ahead Adder - Page 1
Forum section: electronics / general

author: renzoms
author_rank: Regular Contributor
timestamp: October 26, 2019, 03:10:12 am
content: This code works. The purpose of the code is so you can see I have an original 8-bit carry-look ahead adder Verilog file.The images of my textbook, that I purchased, given advice on reddit, are so you can see where the text from which I am not understanding where certain gate delays of a second level carry-lookahead adder are...The next exercise is to produce a second level carry-lookahead adder. The goal is 4 of these 8-bit carry-lookahead adders (CLA) to produce a 32-bit CLA. I know this CLA is four gate delays. The text claims the options are a ripple-carry design, or a second level CLA. *So the ripple-carry design would add 3 more gate delays for c8, c16, and c24 to ripple. So if c32 was important, a 4th gate delay (When is it important? I just use it for overflow detection, and it would be important in the case where I make this into a 64-bit adder). So the 32-bit adder should take should take 4 gate delays, plus 3 or 4 gate delays, plus 1 more for an XOR addition/subtraction control. 8 or 9 gate delays. Please correct me if I'm wrong.So the second level carry-look ahead adder uses G and P. G is a two level AND-OR. And P is an AND gate. The equation is c8 = G + Pc. Pc requires one more AND gate. Here we are at two gate delays. Finally G + Pc requires an OR gate so all of the carry bits are generated in three gate delays. So compared to our ripple-carry CLAs, which required four gate delays to produce carryout of the MSB, and then had to ripple, the second-level carry-lookahead adder requires 3 gate delays. The second level carry-lookahead adder is simultaneously processed as the CLA so the critical path delay is 4 gate delays, -- ok I need help here. The text says "Using this scheme, it takes two more gate delays to produce the carry signals c8, c16, c24, c32 than the time needed to generate the G and P functions. Therefore, since G and P require three gate delays, c8, c16, c24, and c32 are available after five gate delays." Where are these two more gate delays? And I need help here. The text says "The time needed to add 32-bit numbers involves these five gate delays plus two more to produce the internal carries in blocks 1, 2, and 3" Where are these two gate delays?For my own sake: There are 4 gate delays to produce the sum bit and all carrybits within block 0, 1, 2, and 3. There are three gate delays to produce c8.A whole different concern after those concerns: doesn't c8 ripple in Figure 3.17? It takes three gates to produce it and then it ripples for a total of four gate delays?

author: rstofer
author_rank: Super Contributor
timestamp: October 26, 2019, 09:08:50 pm
content: Have you looked at the logic for the 74181 and 7418 devices?Also, around page 43 here:https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdfEach FPGA design has a somewhat different slice design and Xilinx has optimized theirs with the carry chain. I don't know what others have done.
Programming a .mcs flash file to Spartan 6 FPGA using Bus Pirate - Page 1
Forum section: electronics / general

author: kishores
author_rank: Newbie
timestamp: October 26, 2019, 06:05:29 am
content: Hi ,I am using a Spartan 6 devlelopment boardhttps://allaboutfpga.com/product/edge-spartan-6-fpga-development-board/. The board has good interfaces .Unfortunately , i damaged the programming JTAG micro-usb port . Luckily , the JTAG pins are exposed . So I am planning to use Xilinx ISE to covert a .bit file to .xsvf and then use Bus Pirate + xsvf player to load programs into FPGA .My problem is how do I load mcs files to on-board flash using Bus pirate . Is it possible ? Do I write FPGA code for it to read from jtag or serial lines and dump the content to flash ? How can I make it work without Xilinx Boundary Scan ?

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: October 26, 2019, 08:45:58 am
content: Triedhttp://dangerousprototypes.com/docs/Bus_Pirate_JTAG_XSVF_player?

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 26, 2019, 02:20:30 pm
content: Quote from: kishores on October 26, 2019, 06:05:29 amI haven't seen the schematic of this board, but I'll be assuming the Flash is just a standard SPI flash that isn't (and couldn't be) on the JTAG chain. You'll need to configure the FPGA first with some kind of "executive" to then be able to program the Flash chip (through the FPGA). This is exactly what you suspected.There is a way of doing this from ISE, as long as your JTAG probe is supported by ISE (Impact). Look up the online doc.If you want (or have no choice) to do it outside of ISE, take a look at this:https://github.com/quartiq/bscan_spi_bitstreams(I've used this with OpenOCD and that works fine.)