ADC and serial circuit improvement advice - Page 1
Forum section: electronics / projects

author: blazini36
author_rank: Regular Contributor
timestamp: August 17, 2019, 05:08:24 pm
content: I've been whipping up some prototype circuits for an FPGA dev board I've been working with. One is using resistor dividers to scale the expected input voltage to the 4.095 volt input range for a 12bit ADC. The other is an RS 422 transceiver circuit. I'm no Electronics wiz but for the most part these seem to work well but could use some improvement.The ADC circuit works well, the scaling is good for 4 channels to receive a 0-5v input range and the other 4 channels to receive 0-10v. The only issue I have here is noise, the resistor dividers make the inputs quite noisy. I can mitigate this in software with a time based filter but if I can get things a bit better on the board. Are caps between the voltage divider and ADC inputs the way to go? A cap on each ADC channel is a bit of an annoyance plus I'm a bit worried about slowing down the rate of change, but if it's the way to go it's the way to go.The other is an RS422 differential transceiver connected to 2 FPGA pins. I can't do well to test this in place at the moment because there is firmware issues with the RS422 portion of the FPGA programming, I do want to get it right on the next prototype PCB though. Biggest thing I'm concerned with at the moment is the transistor used as a level shifter on the Rx output. VCC to the transceiver is 5v for 5v outputs on the Tx output but the RX output to the FPGA needs to be level shifted down to 3.3v for the FPGA pin tolerance. Just curious if this is implemented correctly.

author: iMo
author_rank: Super Contributor
timestamp: August 17, 2019, 05:30:11 pm
content: What ADC do you use there?

author: David Hess
author_rank: Super Contributor
timestamp: August 17, 2019, 08:45:07 pm
content: Real world signals tend to be pretty noisy so the noise from the input attenuator is usually insignificant. Settling time can be an issue depending on desired resolution.Often the input is integrated over a whole number of power line cycles to reject power line noise which limits the sample rate to 50 or 60 Hz maximum and this can be used to select an RC time constant for input filtering. Higher speed systems use lower impedances and shielded cables.

author: blazini36
author_rank: Regular Contributor
timestamp: August 17, 2019, 09:03:58 pm
content: Quote from: imo on August 17, 2019, 05:30:11 pmThe dev board is a DE10 nano which uses a LTC2308 according to the datasheet

author: iMo
author_rank: Super Contributor
timestamp: August 18, 2019, 12:44:24 pm
content: Since it is a 12bit ADC only, the 10k/15k resistors (their thermal noise contribution could be something like 14uV rms in the 500kHz BW, while ADC's 1LSB=610uV) do not contribute to the noise much, imho.Most probably it is the grounding of the dividers generating the noise, or something like that (generally wiring - ie. no "star" gnd configuration, long wires, loops, etc.)..

author: Kleinstein
author_rank: Super Contributor
timestamp: August 18, 2019, 01:15:31 pm
content: The LTC2308 is only 12 Bit - but a rather accurate and fast (500ksps and some 250 ns sampling) 12 Bit ADC. The inputs use relatively large S&H caps (some 55 pF), so that they like a low impedance source (e.g. 100 Ohms). So it is not easy to use just dividers at the input. One may have to accept some compromises, like limited speed or relatively low impedance.Just the relatively high impedance divider would add noise aliasing and will limit the settling speed and changing channel as it would take relatively long (e.g. some 15 x 500 ns and thus much longer than the 250 ns sampling time) to charge the sampling cap fully.A small cap tends to make things one worse.The RS422 part level translation does not look right. Going from a 5 V signal to a 3.3 V signal could work with a simple resistive divider (e.g. 1 K and 1.5 K). For just RS422 this may be fast enough.

author: Rerouter
author_rank: Super Contributor
timestamp: August 18, 2019, 01:17:06 pm
content: The question is how is your "DGND" used, if it comes from the connector, to the ADC and then elsewhere it should be fine, as any offsets will then be referenced to the ADC, equally that divider should also connect to ground at the ADC, as a divider works both ways, it cuts down the signal, but it also allows a divided amount of ground noise to couple in to your measurement and a smaller amount to your input signalEqually how is your power supply situation, I find it odd that this ADC does not have a PSRR specification, it may be particuarly sensitive to any power supply noise

author: blazini36
author_rank: Regular Contributor
timestamp: August 18, 2019, 03:45:49 pm
content: Quote from: Rerouter on August 18, 2019, 01:17:06 pmThere's no special ground consideration. I labelled it DGND when I started laying out the board but flip flopped as to whether I was going to use the ADC at all. The ground is flood planed on a 2 sided PCB with a whole lot of vias. I use decoupling caps on all IC VCC's but I didn't get too creative with grounds.The dev board provides the 3.3v reference and is supplied with 5v from an LM22679 for a wide input voltage range. That circuit is similar to the datasheet example. I could fairly easily split the ground from the ADC connector assuming there's some sort of analog ground consideration on the dev board (no schematic). I'm not terribly concerned with the ADC, I just figure if I can make a couple of small improvements before I get more prototypes fabbed why not.

author: blazini36
author_rank: Regular Contributor
timestamp: August 18, 2019, 04:25:25 pm
content: Quote from: Kleinstein on August 18, 2019, 01:15:31 pmIt works in simulation as the receiver output drives the drain high or low, quite possible it's not the best way to do it. link speed is 2.5mbaud. Thought about a resistor divider but was worried about it affecting speed.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 18, 2019, 06:20:36 pm
content: In the level translator the mosfet works like an ideal diode, possibly just from the substrate diode (depending on the sample, the mosfet may not conduct with 3.3 V gate voltage). So this can be fast going H to L, but it is slow going L to H. So just a divider can be about as fast.

author: blazini36
author_rank: Regular Contributor
timestamp: August 18, 2019, 09:15:21 pm
content: Quote from: Kleinstein on August 18, 2019, 06:20:36 pmI could use a divider, it's easier. What do you think about level shifting with a double inverter? Something like thishttp://www.ti.com/lit/ds/symlink/sn74lvc2g04.pdf1A would be the input for the receiver output, 1Y is the inverted output to to 2A, then 2Y is the final output to the GPIO FPGA pin @ Vcc of 3.3v. Seems that is should switch in each direction at 10ns.

author: blazini36
author_rank: Regular Contributor
timestamp: August 19, 2019, 04:16:51 pm
content: Any thoughts on this one?

author: Kleinstein
author_rank: Super Contributor
timestamp: August 19, 2019, 04:44:32 pm
content: The double inverter should work too. When going to an FPGA one usually does not care about the polarity - so a single inverter would be enough.