MOSFET Simulation and Calculation Mismatch - Page 1
Forum section: electronics / projects

author: Alaezae
author_rank: Contributor
timestamp: July 09, 2025, 05:34:39 am
content: TL;DR: Trying to find optimal MOSFET for half-bridge driver. I evaluated theoretical power dissipation through a set of FETs which do not match simulated values at all. I'm looking for tips or any experience.Hello,I am working on a project where I'd like to design a half-bridge FET driver for a motor control application. I created a spreadsheet to evaluate performance between different FETs. Specifically, I am looking to minimize power dissipation to limit overall board size (e.g. smaller heatsink) and increase power efficiency. I am having some issues matching the calculated power dissipation and simulated variables.I pulled all the dissipation calculations from two TI app notes on the subject. See the main app note:https://www.ti.com/lit/ml/slua618a/slua618a.pdf?ts=1750255353680and an appendix:https://www.ti.com/lit/ml/slup170/slup170.pdf?ts=1751995729328. Based on the calculations presented there, the switching/conduction/gate drive losses will be functions of...1.) Transfer capacitances (i.e. Cgd, Cds, & Cgd which can be found from datasheet capacitances -- See appendix)2.) Vgs vs Id curve -- Determines more accurate transconductance value which is used to find Miller Plateau3.) Gate drive resistance, gate mesh resistance, total gate charge -- determines length of turn-on, thereby finding time in linear region.4.) Rds,ON, determines conduction loss5.) Maximum Load current and worst-case load voltageI've added these all to a spreadsheet and run the calculations from those app notes (see app notes for details, they're pretty clear...). I won't share the entire spreadsheet here, but I'm including a picture of the power calculations and potential devices. I decided to use the IAUC120N04S6L008 because it had one of the lowest power losses for an acceptable price.I pulled a model from online and imported into LTSpice. I mocked up a half-bridge driver with the model and simulated with the expected conditions. I'm noticing that the power loss through the FET is much higher than the calculated values. With only a single FET (I know the model below has three FETs in parallel per H/L side of half-bridge, but I started with a single FET), I was seeing dissipation up to ~175W! That is several orders of magnitude larger than predicted (600 mW) for that FET!The things I'm noticing:Voltage isn't 28V across load even with 98% duty cycleShoot through is not an issue. I can see the gate drive and see that there is some dead time between turn-on. Also, the sim fails in that caseCurrent through load stabilizes at around 11ADissipating ~70W/FET with 3 parallel devicesI don't have a very accurate load model. I'm not really sure about the finalized impedance.What I tried:Bootstrapping: Connect source of H-side to drive negative. No effect on power.Change gate resistances and drive voltage. Slightly decreased loss, but not appreciablyAdded trace length impedances. Thought it might have something to do excess/lack of damping on inputsChanging solver. This was less of a power fix and more just to get the model to work. Switched to Gear method and reduced abstolI didn't change anything here, but could the impedances be mismatched to the point where a significant portion of power is reflected? Is there a way to correct that?Any tips on the simulation? This is the first time I've attempted to empirically find a drive transistor (e.g., not just pulling a random IRFXXX from my junk bin). Is there anything obvious I'm doing wrong? Please let me know if I can provide more information.Target Params: Iout = 19A, Vdc=28V, f_sw = 40kHzThank you!

author: PCB.Wiz
author_rank: Super Contributor
timestamp: July 09, 2025, 07:58:58 pm
content: The upper fet has high on power because you do not use bootstrap gate drive.Look at high side gate drivers, for how they drive the gate above Vdd