Why are CPUs the size that they are? - Page 1
Forum section: electronics / beginners

author: LoveLaika
author_rank: Frequent Contributor
timestamp: October 06, 2021, 10:15:09 pm
content: The thought just occurred to me: why are CPU sizes more or less the same physically? With Moore's law, as the years went by, you could double the number of transistors in a CPU (well, it's leveling off now, but that's another debate). However, the size has remained more or less the same, the small square form factor used in CPUs. I mean, sure, I suppose Xeon processors may be a bit bigger than what you expect from a regular desktop CPU, but is it just mainly standardization between motherboards and/or heat? Why don't we make larger CPUs that would allow for more transistors and/or better heat efficiency (or is that not achievable when running at GHz clock speeds)?

author: SL4P
author_rank: Super Contributor
timestamp: October 06, 2021, 11:02:11 pm
content: Power/heat dissipation, the number of pins and reliable connections…Consider the migration from 0.1” through hole - to finer pitches, then surface mount… finer pitches, and finally BGA.Yes the chips could get bigger, but that bring lower silicon yields, larger boards, more copper, shipping weight, reduced clock & signal propagation and a host of physics I’ve never heard of.Remember most ‘finished’ product manufacturing now has almost zero human intervention, so the manufacturing lines can be smaller, tightly integrated == lower cost to operate, even though they’re damned expensive to set up.

author: Jwillis
author_rank: Super Contributor
timestamp: October 06, 2021, 11:02:39 pm
content: Case size hasn't changed much but the die sizes have. The die size on earlier CPUs are smaller than new ones .

author: fordem
author_rank: Regular Contributor
timestamp: October 07, 2021, 12:48:00 am
content: Quote from: LoveLaika on October 06, 2021, 10:15:09 pmI really don't know where you got this idea from, but it's totally out of whack with reality - just yesterday one of my coworkers dropped a Lenovo ThinkCenter "Nano" on my desk - it's about the size of a slot 1 Pentium II without the heatsinks - and just so you understand where I'm coming from - the Nano is a complete computer system, CPU, RAM, SSD et al - the slot 1 Pentium II still needs a system board and everything else to make it functional.I'm posting this from a Thinkpad with a CPU about the size of a postage stamp, compare that to a Pentium III that's about 2" x 2".Even as CPUs have gotten more powerful, they have gotten smaller, a lot more powerful and a lot smaller.One last comment - the first computer system I worked with was powered by an NCR 605 GPMC (General Purpose Mini Computer) - the 16 bit CPU was on four 11" x 14" plug-in cards, and that did not include the memory interface, memory or any I/O

author: David Hess
author_rank: Super Contributor
timestamp: October 07, 2021, 03:34:15 am
content: Quote from: LoveLaika on October 06, 2021, 10:15:09 pmCPU sizes, both the CPU dies and packages, have never been of a uniform size; they vary wildly. And larger CPU dies have a cost premium because there are fewer dies on a wafer but a fixed number of defects so yields are lower.For small CPU dies, cost may be dominated by packaging meaning the number of pins, and the size of small dies may be dominated by the area taken by pads.

author: gcewing
author_rank: Regular Contributor
timestamp: October 07, 2021, 05:50:33 am
content: The size of any packaged chip is determined mainly by the number of connections -- the actual piece of silicon inside is usually much smaller. And packages have gotten smaller for a given number of pins over the years. A 68000 in a 64-pin DIP package was huge compared to a modern CPU with hundreds of pins in a BGA package.The area of the silicon does increase with the number of transistors, although it's not linear due to improvements in technology making the transistors smaller.

author: radiolistener
author_rank: Super Contributor
timestamp: October 08, 2021, 10:51:12 pm
content: I hear that CPU core size is limited by wave propagation speed.If you move some computational block on longer distance it's performance will be limited with transmission line length. In other words if you place some block of core on a long distance from other block, it will needs too long time to deliver data back and forth between these blocks, so it will reduce performance of entire core.But you can place several cores on the same die, because core speed is already limited with external bus performance.

author: golden_labels
author_rank: Super Contributor
timestamp: October 08, 2021, 11:57:33 pm
content: I will let the pictures speak for themselves.

author: David Hess
author_rank: Super Contributor
timestamp: October 09, 2021, 02:50:40 am
content: Quote from: radiolistener on October 08, 2021, 10:51:12 pmThat is sometimes the case. The combined propagation and wiring delay place an upper limit on speed, but in denser processes so does power density. Transistors in high power function units are actually spaced out to increase area to lower thermal resistance so they can be clocked faster but since this raises area, it makes the chip more expensive. Function units which can take maximum advantage of transistor density are relatively low power, like cache.QuoteCore speed is limited by the load-to-use latency of the pipeline divided by the cache access time, which is why out-of-order CPUs can operate at higher clock speeds than in-order CPUs; they have higher load-to-use latency while cache access time is fixed.

author: TimFox
author_rank: Super Contributor
timestamp: October 09, 2021, 03:20:46 am
content: At a transmission line velocity factor of 10% (absurdly low), the propagation speed would be about 1 nsec per inch.

author: radiolistener
author_rank: Super Contributor
timestamp: October 09, 2021, 04:39:12 am
content: TimFoxCyclone IV FPGA has about the same size as a usual CPU. It has 4 PLL, each are physically located at their own corner of die. The documentation says that such count and physical location of PLL modules is required in order to reduce clock propagation delay across die, because die size is too large to clock some gate from PLL on other side of die. The max stable PLL output is about 450 MHz.CPU uses frequencies 4 GHz and more, such clock has a period 0.25 ns, so this is not a surprise that such frequency requires strong distance limitations between CPU core blocks in order to keep high speed. At so high frequency it also very sensitive to phase delay alignment between each data line of the high speed parallel bus.Even at 200-400 MHz you're needs to be very careful with electrical length of each data line of the bus and take into account propagation delay, but CPU working at crazy 4 GHz frequency and consists a lot of very complicated logic. And there is also limitation with power dissipation and rise time. So it's just fantastic how they designed it...

author: TimFox
author_rank: Super Contributor
timestamp: October 09, 2021, 02:02:16 pm
content: What is the actual transmission line propagation velocity in typical monolithic CPU construction? I just threw out 10% for a quantitative estimate.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 09, 2021, 04:10:15 pm
content: IBM made monster multi-die assemblies for a long time. Density is limited by interconnects: only so many chips can be on a single ceramic substrate, which needs a massive heatsink on one side and a massive multipin connector on the other. You could put a few of these side by side, but eventually need to connect to power supplies, bus interfaces, peripherals, etc. so that space tends to form the core/backbone of the machine, and everything clusters around it, including all the CPUs integrated to it.By "limited" here, I mean that it scales poorly: if you want a bigger machine, it's going to take more interconnections than CPUs, as the number goes up; it doesn't grow linearly, but as a power law. What power, depends on how tightly integrated you want the cores to be -- if any one should have immediate communication to any other, there's O(N^2) connections (edges in the graph).Area of silicon chips is limited by process yield and thermal expansion. Even with reasonably well matched expansion rates (special ceramics and alloys), it also needs a low enough defect rate that much of the area is usable -- multicore CPUs have enough that they may disable whole cores that are defective, selling the chip as a lower cost variant rather than scrapping it. That limit is around an inch, and will likely remain so for a long time. Thus we should expect computing power grows ultimately by vertical stacking (3D chips; we already have modest height stacks in multi-die assemblies, often with thru-silicon vias (TSV), often for integrating RAM, Flash and CPU together in one SoC), or laterally by integrating multiple cores/machines (which has also been true for a long time, supercomputers are cluster based).Tim

author: radiolistener
author_rank: Super Contributor
timestamp: October 09, 2021, 05:29:53 pm
content: Quote from: TimFox on October 09, 2021, 02:02:16 pmI think what is more important is a phase delay between two different signals clocked from the same clock source. If these signals come from opposite sides of die, you can easily catch too high phase delay between signals and clock source. And timing constraint will be break. So it will add limitation on signal routes across die. In some cases you will not be able to route some signals due to break timing constraints and as result you will be unable to connect two blocks on a long distance from each other. Higher working frequency leads to a more strong limitations for a distance.In order to bypass such limitation you will needs to reduce clock frequency or use separate clock domain with synchronization between clock domains to avoid metastability issues. In both cases performance will be reduced.

author: David Hess
author_rank: Super Contributor
timestamp: October 09, 2021, 05:31:06 pm
content: Quote from: T3sl4co1l on October 09, 2021, 04:10:15 pmThe largest chips are limited by reticle size, if the customer will pay for it. I think Bob Colwell said the first Itanium hit the reticle limit.QuoteRegular structures like cache can include spare rows and columns to repair defects, which partially explains its popularly on large chips; it does not decrease yield. I have read that the original AMD Barton, which doubled cache size, had poor yields because of lack of redundancy in the cache.

author: TimFox
author_rank: Super Contributor
timestamp: October 09, 2021, 07:12:10 pm
content: Quote from: radiolistener on October 09, 2021, 05:29:53 pmYes, the propagation velocity impacts on important quantities such as phase delay and break timing. To relate this to dimensions, one needs to know the transmission-line propagation velocity value.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 09, 2021, 11:29:03 pm
content: Quote from: TimFox on October 09, 2021, 07:12:10 pmAnd the propagation usually sucks terribly (RC transmission lines), limiting bandwidth and dispersion based on route length and repeaters (logic buffers every so often). Although modest Q is available on the upper metal layers, I think? (Certainly enough they can do tricks like transmission lines and inductors on RF ICs, not sure offhand the applicability with ASICs.)Tim

author: LoveLaika
author_rank: Frequent Contributor
timestamp: October 10, 2021, 12:28:04 am
content: I may be foolish for asking, but are TL effects here important due to the distance within the chip and the effect from really close signals? The relative distance within a chip doesn't seem large, but when confined in such a space with tons of other fast propagating signals, it feels like we're delving more into deep physics territory

author: Capernicus
author_rank: Frequent Contributor
timestamp: October 10, 2021, 12:44:33 am
content: I think they make really small cpus cause they are stingy bastards.Just add 300 cuda cores and $$$ goes up for no apparent reason.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 10, 2021, 12:45:25 am
content: It's only a few cm, but the edges are 10s of ps so it adds up.Tim

author: wizard69
author_rank: Super Contributor
timestamp: October 10, 2021, 05:25:57 pm
content: Why are they the size they are? The simple answer is economics.However I think you are really missing some important elements. For one the shrinking process sizes means you literally have not CPU's but SoC's these days.Then you have the reality of connecting the chip to the physical world. A chip has to be big enough in perimeter to allow wire bonding for all of the I/O and power signals. That can be a huge factor that depends upon many things. in the end you need a pad or via per signal even if the chip is part of a stack. In other words to be useful a chip either needs to talk to another chip or to aboard that wires up multiple chips. There are a limited number of ways to get those signals from one piece of silicon to another and they all use "space".Beyond all of that I'm not sure you are aware of all the different sizes of CPU's shipping these days. Many are small and a few are huge, for the mainstream though it comes down to what it takes to be competitive. Go too big die size wise and you are too expensive, go too small and your performance isn't competitive, for the mainstream.