3 stages power amplifier project - Page 1
Forum section: electronics / projects

author: Lucky-Luka
author_rank: Unknown
timestamp: December 18, 2019, 09:10:37 pm
content: Hi allI do have a school project to do: a 3 stages power amplifier circuit.+-16V power supply+- 175mV input signal swing corresponding to +- 14V output swing. (closed loop voltage gain = 80).open loop gain of the 3 stages ampli = 2450resistive load >= 10ohmamplifier input resistence >= 10kohmbandwidth >=80 kHzphase margin 80°efficiency >=60%THD <=1%I have to use only transistors listed in the ltspice database.That's why I had to choose 2N3055 (npn) and D45H11 (pnp): the only ones capable of dealing with 10W power dissipation (I've read that from their datasheets).I've started the project from the output stage.Class AB output stage using a Vbe multiplier as biasing and a current mirror (current source as first attempt).I just wanted to see if I could get it right... Something went wrong... Obviously...I gave it a 14V sinusoidal input with -1.3 DC offset and I hoped to see sinusoidal 14V oscillating around 0V as vo.I got a distorted sinusoidal waveform oscillating around -280 mV.How can I fix that? What am I doing wrong?Any suggestions is appreciated.Cheers

author: Zero999
author_rank: Super Contributor
timestamp: December 18, 2019, 10:07:07 pm
content: No this doesn't have an open loop gain of 2450. It's a unity gain power stage.Connecting the base of Q4 to 0V via V4 like that is messing the biasing up. Look at Q4's base current!Try AC coupling the input, via a suitable capacitor and a potential divider to bias the output stage, rather than a constant current source.When you add the other stages, which can be DC coupled, you'll discover that negative feedback will cause Q4's base will sit at two base-emitter drops below 0V.

author: Lucky-Luka
author_rank: Unknown
timestamp: December 18, 2019, 10:20:58 pm
content: Quote from: Zero999 on December 18, 2019, 10:07:07 pmI wasn't clear.That is the 3 stages circuit open loop gain.Quote from: Zero999 on December 18, 2019, 10:07:07 pmI think I have done as Sedra/Smith shows...Quote from: Zero999 on December 18, 2019, 10:07:07 pmHow can I do that?

author: Zero999
author_rank: Super Contributor
timestamp: December 18, 2019, 10:31:08 pm
content: There is nothing wrong with using a constant current source, but it won't work with the input biased around 0V like that. The circuit is designed to be used in the feedback loop of a voltage amplifier which will set the DC bias point to the required voltage using negative feedback.There are other problems. The VBEmultiplier should have 4 base-emitter voltage drops, not two, to bias the output transistors on. The output transistors need emitter ballast resistors to stabilise the operating current, otherwise it won't work in real life, even if you can get it to work in a simulator.EDIT:Oh, I missed the -1.3V in the input voltage, but it's not good enough. VBEcan't be predicted that accurately.

author: magic
author_rank: Super Contributor
timestamp: December 18, 2019, 10:46:18 pm
content: This should work as a unity gain buffer with some offset between Vin and Vout, nothing fundamentally wrong with it. The offset should indeed be about two diode drops, but this stage is underbiased so it may do weird things as of now.Crank up the Vbe multiplier until you get some reasonable idle current through both emitters. Adjust V4 again for zero output, don't blindly assume that 1300mV is the exact number you need because it's not and it depends on transistor type and idle currents.

author: dmills
author_rank: Super Contributor
timestamp: December 18, 2019, 11:22:40 pm
content: Also, Sedra/Smith is vastly inferior to Cordell or Self on this particular subject, use the right books.Add about 0.33 ohms in the emitter leads of the final power devices, and a few tens of ohms between the emitters of the driver transistors (Helps the horrifically slow finals turn off).Given the general crapness of the '3055, I might be tempted to go for an EF triple just to try go get the load on the Vas down to something more reasonable, even if you are going for an EF Vas, but with 14V required on a 16V rail that is a bit tricky, might have to use a CFP instead.Wind up the bias until you have about 30mV across one of the emitter resistors.

author: Zero999
author_rank: Super Contributor
timestamp: December 18, 2019, 11:35:56 pm
content: I've tweaked the VBEmultiplier until the bias current in the output stage was reasonable.I determined the correct DC bias voltage to add to the input by temporally adding an op-amp in the feedback loop and connecting its input to 0V.And put the result into the DC field of V4.

author: dmills
author_rank: Super Contributor
timestamp: December 19, 2019, 01:31:34 am
content: There is something deeply wrong with LT spices model of at least some of those transistors, because for shits and giggles I drew a fairly conventional power amp, and at a gain of 80, the miserable thing was stable with NO compensation cap at all!Now granted a gain of 80 is more then slightly problematic if you want 80kHz BW with that choice of output sand, so I dropped the gain to 20, still allegedly stable.... Just seems very, very unlikely.Playing with it, I don't think the obvious EF output stage is easily going to get you there, not quite enough voltage headroom by the time you include the emitter resistors and the current source/Vas transistors. I suspect you are going to need to bite the bullet and design with the load in the collector circuit.Your spec is also seriously incomplete, open loop gain at what frequency? THD at what frequency? Is 80kHz full power bandwidth or something more reasonable, what is the slew rate requirement? That efficiency is at full power output?Are cascoded jfets allowed for the input pair? Makes hitting that 10k input Z a bit easier.By three stage I assume the lecturer means input LTP, Vas and output stage?

author: magic
author_rank: Super Contributor
timestamp: December 19, 2019, 08:24:55 am
content: Quote from: Zero999 on December 18, 2019, 11:35:56 pmYou could get just about the same result by tying the input to ground and then subtracting the output voltage that appearsQuote from: dmills on December 19, 2019, 01:31:34 amI don't think you need to cascode jfets just to make them work. And besides, OP has no spec on noise and offset voltage so what's the problem with BJT

author: Zero999
author_rank: Super Contributor
timestamp: December 19, 2019, 09:40:28 am
content: Quote from: magic on December 19, 2019, 08:24:55 amThat would be much easier wouldn't it. I always have to do things the hard way.

author: dmills
author_rank: Super Contributor
timestamp: December 19, 2019, 03:22:55 pm
content: Quote from: magic on December 19, 2019, 08:24:55 amYea, used to designs with WAY higher supply rails where the cascode really helps with the available choice of fet.I was instinctively sweating the output offset, but your right there is only half a spec.Also, whats with the weirdly low open loop gain? Assuming that is a DC value I would expect something about three orders of magnitude higher, but then I likes my current mirror loads and emitter follower Vas.Regards, Dan.

author: Lucky-Luka
author_rank: Unknown
timestamp: December 19, 2019, 09:38:29 pm
content: Quote from: dmills on December 18, 2019, 11:22:40 pmDo you see this slowness in the simulation?Keep in mind that this is just a simulation project for an analog electronics course at the university and that this is my first project of a power amplifier. I know that you are telling me how to make it perform better in real life but I just needed to keep it as simple as possible to accomplish the task needed.Quote from: dmills on December 18, 2019, 11:22:40 pmCan I say that I haven't understood anything?Quote from: dmills on December 18, 2019, 11:22:40 pmWhy 30mV?Thanks

author: Lucky-Luka
author_rank: Unknown
timestamp: December 19, 2019, 09:47:47 pm
content: Quote from: dmills on December 19, 2019, 01:31:34 amI have to checkQuote from: dmills on December 19, 2019, 01:31:34 amNot specifiedQuote from: dmills on December 19, 2019, 01:31:34 amNot specifiedQuote from: dmills on December 19, 2019, 01:31:34 amYesQuote from: dmills on December 19, 2019, 01:31:34 amNo, since the subject wasn't touched during the course.Quote from: dmills on December 19, 2019, 01:31:34 amDifferential pair + CE + EF

author: dmills
author_rank: Super Contributor
timestamp: December 19, 2019, 10:11:37 pm
content: Get thee to a library, borrow a copy of "Designing audio power amplifiers" by Bob Cordell, or "Design of audio power amplifiers" by Douglas Self.Everything you need to know is there.Given the craptacular choice of BJTs offered in LtSpice I might be very temped to do the parallel thing to get sufficient current rating and power dissipation out of some of the smaller but less 'historical' parts they actually offer.

author: Lucky-Luka
author_rank: Unknown
timestamp: December 19, 2019, 10:35:52 pm
content: Quote from: Zero999 on December 18, 2019, 11:35:56 pmHave you noticed my bias current was way too high?Which is a reasonable value? You have more or less 35mA. Is there a rule of thumb?After that current is decided, did you choose the right voltage across the Vbe multiplier?Thanks

author: dmills
author_rank: Super Contributor
timestamp: December 19, 2019, 11:13:25 pm
content: 100mA or thereabouts in the finals typically.You will find setting this MUCH easier if you add at least 0.1 ohm of emitter resistors to the output transistors first...

author: Lucky-Luka
author_rank: Unknown
timestamp: December 20, 2019, 08:23:32 pm
content: Quote from: dmills on December 19, 2019, 11:13:25 pmLess than that is acceptable?More distortion will appear?

author: magic
author_rank: Super Contributor
timestamp: December 21, 2019, 10:54:08 am
content: Try itIt depends on circuit. It also depends on output level, whether it falls in the A or B part of class AB. Popular wisdom has it that it isn't even as much about current as about some special value of voltage drop across the emitter resistors, regardless of their value, I think somebody has already posted about it here.

author: dmills
author_rank: Super Contributor
timestamp: December 21, 2019, 05:44:35 pm
content: The trick is trying to minimise the change in transconductance as you go from both devices active to just one, but it is a detail.

author: Lucky-Luka
author_rank: Unknown
timestamp: December 23, 2019, 09:34:07 pm
content: 1)Why a current mirror (the one that Zero999 set at 1mA) in this stage is better than a resistor? Is it just because I can have more input impedence and so the gain stage can work better?2)To incresce the bias current of the output stage do I have to increse the current mirror AND the voltage across the Vbe multiplier? I can properly understand the relation between those two factors.

author: magic
author_rank: Super Contributor
timestamp: December 23, 2019, 11:49:19 pm
content: Try to figure out a resistor value which will work equally well within 1V of each railFurthermore, more impedance here → more open loop gain. Less distortion too, because operating current of the VAS doesn't vary as much with output voltage.

author: Lucky-Luka
author_rank: Unknown
timestamp: December 23, 2019, 11:55:50 pm
content: Quote from: magic on December 23, 2019, 11:49:19 pmI know that for you the answer is obvious but not for meYou mean that resistor doesn't exist?

author: Lucky-Luka
author_rank: Unknown
timestamp: December 25, 2019, 04:56:54 pm
content: Hi allThe voltage across the Vbe multiplier determines the quiescent current of Q1 and Q3, right?How can I decide the right current of the current mirror? It has to be greater than the base current of Q2 when maximum current is flowing in Q1 (14V/10ohm=1.4A) so that even Q5 can work properly (right?), but how much greater?Happy holidays

author: magic
author_rank: Super Contributor
timestamp: December 25, 2019, 10:22:21 pm
content: A few mA is common. Can't go too high or the VAS transistor will overheat, can't go too low or it will fail to drive the output stage or produce distortion if it is barely sufficient. Increasing too much also seems to cause distortion, perhaps due to falling output impedance of the VAS and its active load.Experiment until you get the performance you want.

author: Lucky-Luka
author_rank: Unknown
timestamp: December 27, 2019, 09:45:02 pm
content: After the last stage was done (more or less) I've tried to add a CE stage.Something went wrong maybe.The currents on the output resistors changed.What is going on and what should I do?Q2 base current should be it's collector current (same value as in the stage without CE) divided by Q2 beta right?I fear this relation alone isn't enough in order to find the right I1...

author: Zero999
author_rank: Super Contributor
timestamp: December 27, 2019, 11:16:22 pm
content: Your circuit is far too dependant on the hFEof Q2 to be stable. Every time you change something slightly, the voltage gain of Q2 will change and mess everything up.

author: Lucky-Luka
author_rank: Unknown
timestamp: December 27, 2019, 11:19:32 pm
content: I still have to implement the input stage and the final feedback.I was adding a stage after the other as I was told to do.I was looking for a method to do that in the right way.

author: magic
author_rank: Super Contributor
timestamp: December 28, 2019, 08:33:58 am
content: I1 is right because the output is centered at zero.If you want to see more output power, increase V4 amplitude of course.