Buck loop stability tuning - Page 1
Forum section: electronics / projects

author: zphaze
author_rank: Contributor
timestamp: April 16, 2024, 05:44:24 pm
content: Hi,I'm using LM63460 to create a buck with a high Vin range 3V-36V and also very different load conditions (from 0.1A to 5A).Using the .xlsm given by TI it's relatively easy to tune the whole thing.Here's a screenshot :What I'd like to know is if the local minimum in phase near 2000Hz is a problem. Could this create ringing?Technically I would think with an open loop gain A near 40dB it wouldn't affect much but I prefer asking in case.I can always raise the feedforward capacitor and bump the output capacitance to a value higher, but would prefer not to if not necessary as this adds additional issue with space on the circuit board.I'm tuning for 0.1A as it is the most bothersome.

author: dietert1
author_rank: Super Contributor
timestamp: April 16, 2024, 08:00:28 pm
content: First you could define limits for ringing. But then the simulation doesn't tell either. I would make the circuit and look at it with a scope to find out whether it is working satisfactory with varying load (pulse generator or so).Probably you want multiple output capacitors of different capacity parallel to each other in order to reduce RF ripple. 110 uF can be one 100 uF MLCC plus a 10 uF MLCC. At 2.2 MHz one cap may not be enough. Also a 100 uF MLCC can be as low as 50 uF with 5 V DC.And one could try some peaking network parallel to the 100K feedback resistor.Regards, Dieter

author: zphaze
author_rank: Contributor
timestamp: April 16, 2024, 09:02:24 pm
content: Quote from: dietert1 on April 16, 2024, 08:00:28 pmYes, may be not clear in the excel schematic but the CFF capacitor is destined to be parallel with the RFB resistor.Not a network though.Indeed for the capacitor derating I wondered if I'd be better using some low ESR alu electrolytics in parallel with some ceramics to further lower ESR.But still, my main "worry" is that the phase margin is a little bit too close to 180° near 2kHz.The phase margin, strictly speaking, is okay though, but should I not take a risk and already bump capacitance higher and eliminate this to make at least everything higher than 45° before the crossover frequency?

author: dietert1
author_rank: Super Contributor
timestamp: April 16, 2024, 09:37:59 pm
content: The Pololu buck converters i have been using for making TEC ovens have six output caps: one 180 uF electrolyte and two larger MLCCs (maybe one 47 uF, one 10 uF). On the bottom there are three smaller MLCCs arranged as a lumped line, maybe 1 uF each. The inductor is 6.8 uH nominal and the converter is meant for up to 3.2 A output.Their 5 V, 5 A version would be D36V50F5 and it has 15 output capacitors - among them a 330uF polymer electrolyte. The inductor is 2.2 uH. Images online.

author: jonpaul
author_rank: Super Contributor
timestamp: April 17, 2024, 11:06:24 am
content: Bonjour, do you know about secorder sstems control theory, poles, zeros, and phase margin?TI specs and app notes should give all info needed. Did you study it?Suggest to use Use worst case designVin = min/maxIout = min/maxFor each of the 4 scenarios, calc load, R adj Vin, make bode plots and extract worst case phase margin.Adjust compensation feedback to achieve a critical damped or overdamped response.Normally change of the load capacitor is sufficient.Faster to built it and test on the bench.Bon chanceJon

author: zphaze
author_rank: Contributor
timestamp: April 17, 2024, 02:48:09 pm
content: Yes I'm familiar with all the stability theory.I'm indeed planning for the worst case scenario using the tool.However, my core question still is somewhat unanswered : Can I get ringing at 2khz (from the posted bode plot screenshot in the original post)?Granted I have 40dB gain at this frequency, I would assume theoritically that if somewhat at this frequency the phase becomes -180° because of some tolerance issue,I would get somewhatA = -A(omega)/(1+Beta(omega)*-A(omega)) ~= 1/Beta(omega)And thus would still achieve stability, but something might escape me here hence why I ask, to be certain.

author: jonpaul
author_rank: Super Contributor
timestamp: April 17, 2024, 03:42:47 pm
content: stability is determined by phase margin, WC 45 deg.j

author: mag_therm
author_rank: Frequent Contributor
timestamp: April 17, 2024, 04:44:20 pm
content: Your "easy" plot result shows the phase margin way less than "good engineering" of 45 degrees.Did the addition of "UseCFF" (you selected 56 pF) convert the compensation to type 3?Did you try to optimize by moving the Zeros 1 &2 to the left?I would predict that there will be very few on an internet forum who can answer your "core question" without a lot of work.Can you create a transient time simulation model?I did frequency domain and transient time models in qucs for my type 3 converters last year, and I know they take a lot of work, especially the numerical transient.Finally my Ref book by Gupta & Hasdorff said in 1970 about transient response:"........the higher order systems will offer greater difficulty in estimating peak time, overshoot and settling time.Numerical calculations and plots by digital computer, of course will remove this difficulty..."

author: zphaze
author_rank: Contributor
timestamp: April 18, 2024, 12:19:57 am
content: Well, I suppose I got my answer somewhat. If you guys don't readily see issues I guess I wasn't too far from what I thought was about right for a start.Phase margin is >60° and gain is high for smaller phase values, so I guess I'll take this as "good enough" and go ahead.I'll still plan for added capacitance in case of unexpected/stronger derating.As for the transient model I don't have models from TI for this controller so I'll stick to the bode plots for now.Simulation makes thing easier I'm 100% with you on that.UseCFF adds a pole and a zero obviously, so I would suppose its 3rd order at least.