A frequency locked loop - Page 1
Forum section: electronics / projects

author: GK
author_rank: Super Contributor
timestamp: May 14, 2014, 01:52:29 am
content: In control loop analysis a phase detector for a PLL can be modelled as an integrator with gain; it has a pole frequency of zero Hz with some gain figure at DC. This characteristic is implicit in the conversion from frequency to phase.As a negative feedback system, the PLL control loop has an implicit 180 degrees of phase inversion. The phase detector, being an integrator, therefore contributes an additional 90 degrees of phase shift, leaving the designer with 90 degrees of phase margin before having to consider the loop filter.There are two basic approaches to the necessary loop filter of a PLL. The most basic is a single pole low pass filter. The pole frequency of the filter must be set sufficiently high so that its phase contribution cannot accumulate to the full 90 degrees prior to the unity loop gain intercept frequency of the closed control loop. If the pole frequency is set too low, the total phase shift around the loop will come too close to 360 degrees, making control loop oscillation inevitable.It is for this reason the simple single pole filter generally offers poor performance. If the designer naively sets the pole frequency too low in the hope to adequately suppress the crap coming from his phase detector, he unwittingly uses up his available phase margin and winds up with an oscillating control loop.The second most basic approach to loop filter design is a low pass with a zero. This is typically a basic RC filter with a resistor in series with the capacitor, thus providing the zero frequency. With this kind of filter, the pole frequency can be set much lower, affording better suppression of switching artefacts from the phase detector. In this design case the full 360 degrees of phase shift can be allowed to accumulate prior to the unity loop gain intercept frequency, so long as the zero frequency is set sufficiently low such that the total phase shift is throttled back a sufficient degree, yielding a satisfactory phase margin prior to the intercept. Such control loop dynamics are analogous to two-pole compensation in linear amplifier design.Anyone who has done any serious control loop analysis and design for phase locked loops, and has juggled the above mentioned pole and zero parameters for the most optimal overall performance, will be painfully aware of the limitations imposed by that necessary zero.No matter low much one tries to lower the pole frequency in a trade off between transient response and the suppression of phase detector artefacts, the resultant zero frequency that is necessary to return an acceptable phase margin delivers an intractable plateau to the ultimate attenuation afforded by the loop filter.I have a PLL application where loop settling time isn’t particularly important, but sideband and spurious PLL artefact performance is. Tradition PLL techniques will not do.My idea is eliminate the phase detector by using a proportional frequency detector. This will essentially be a frequency counter coupled to a high resolution DAC. The frequency detector will generate an output voltage that is directly proportional to the frequency difference between its two inputs (f ref and F vco). Just for crude example; -12mV DC if the frequency difference is -12Hz and +213mV DC if the frequency difference is +213Hz.A “frequency detector” along these lines is insensitive to phase, and, unlike the traditional phase detector, does not have the implicit transfer characteristic of an integrator. This is the whole idea. It opens up a great deal of design freedom as the loop phase shift prior to applying the loop filter is just the implicit 180 degrees, rather than 270 degrees. With the need for a compensatory zero eliminated, this means that loop filter can just be either a single pole low pass filter or an integrator. The loop filter provides dominant pole compensation and the pole frequency can be set arbitrarily low, without limitation.Switching artefacts from the frequency detectors DAC can therefore be reduced to virtually any arbitrarily low level; the only trade off to the degree of attenuation to control loop spurs being control loop settling time.Such a system would not be “phase locked” but rather “frequency locked”, and more analogous in its fundamental operation to a basic servo control loop rather than a traditional PLL.For my application this appears a fundamentally sound solution, but I can’t imagine that no one else has considered concept already. Can anyone cite any prior art, control theory analysis or real world applications?

author: moffy
author_rank: Super Contributor
timestamp: May 14, 2014, 02:50:53 am
content: It is fairly common, just Google "frequency locked loop"(fll).A manufacturers version:http://www.wolfsonmicro.com/documents/uploads/misc/en/WAN0209.pdf

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 14, 2014, 03:28:56 am
content: I'd just use a crude analog detector (possibly ratio, or even slope detector, if narrow band; else, an F-to-V, or pulse generator and filter) to get the crude frequency, then AC couple that into the loop. It's like derivative in a PID system, but rather than the inevitable phase shift of a filter, you magically gain 90 degrees due to physics, making it insensitive to the phase detector's jitter and stuff.At least, one would hope. Do keep in mind that F-to-V is an inherently slow process, and at best, can only be performed at a moderate fraction of the actual frequency (no more than double -- assuming the duty cycle is constant).An example of a per-cycle detector would be an "integrate, sample-and-hold, reset" process. Or alternately, a switched capacitor filter, at synchronous or harmonic operating frequency.In the digital domain, whether you sample as little as a half cycle, or collect a massive series and perform a Fourier or Hilbert transform on the mess, the same is true.The sample rate, delay or filter implies or implements, at best, a pole near the operating frequency.Tim

author: GK
author_rank: Super Contributor
timestamp: May 14, 2014, 04:12:22 am
content: Quote from: T3sl4co1l on May 14, 2014, 03:28:56 amAn analogue detector is completely out of the question as it that wouldn't have the frequency stability and precision required by several orders of magnitude.Quote from: T3sl4co1l on May 14, 2014, 03:28:56 amNot at all if you count during the period (or x10 or x20 or whatever periods) with a much higher frequency clock.Still not as fast as a pure phase detector, but how many PLL/FLL designs have control loop dynamics not removed from the phase/frequency detector operating frequency by at least an order of magnitude, if not several?

author: GK
author_rank: Super Contributor
timestamp: May 14, 2014, 04:12:51 am
content: Quote from: moffy on May 14, 2014, 02:50:53 amThanks.

author: ejeffrey
author_rank: Super Contributor
timestamp: May 14, 2014, 05:23:44 am
content: Quote from: GK on May 14, 2014, 01:52:29 amSince frequency is just the time derivative of phase, how is this different than using a regular phase detector, but instead of using a PI or high-gain lowpass filter as the feedback loop, using a wide band proportional error amplifier? That is, why does it matter if the phase detector or the loop filter is doing the integration? It seems like the loop gain plot should look the same in either case. The total phase shift would be 270 degrees at low frequency until the unwanted phase shift of the amplifier started accumulating, which would be by design after the loop gain falls to below 1. In the same way it would not be phase locked because without the second integrator, the phase detector would have to be putting out a non-zero average signal to be amplified and sent to the VCO.

author: GK
author_rank: Super Contributor
timestamp: May 14, 2014, 05:44:09 am
content: Quote from: ejeffrey on May 14, 2014, 05:23:44 amA loop filter is required for reasons other than defining the loop gain and phase. But given the relationship between frequency and phase I think you make a point against my conception of a non-integrating detector.

author: babysitter
author_rank: Frequent Contributor
timestamp: May 14, 2014, 08:28:38 am
content: Have a look also at the DAFC, which iirc is also a kind of frequency-locked loop.If you need the clean signal only for a short time, what about opening the control loop and feeding the VCO with a stable voltage that is equivalent to the last valid tuning voltage ? only the oscillator drift and the control voltage noise will appear then...

author: GK
author_rank: Super Contributor
timestamp: May 14, 2014, 01:30:05 pm
content: Your sample and hold idea sounds like a clever one, but I'm still intrigued for now by the FLL idea, particularly the theory of operation of that Wolfson FLL linked to by moffy.This excerpt from the datasheet is particular pertinent:QuoteNote that the description that they give on the design (well in that particular case digitally programmable) flexibility of the loop filter characteristic for the express purpose of enhanced reference frequency suppression over a conventional PLL is exact what I am after.However what they do not explain is exactly WHY their filter system would not be compatible or work just the same with a normal phase detector rather than a specialized frequency detector, which would otherwise make their part a PLL rather than an FLL.Is their control loop based on a frequency detector rather than a phase detector because a frequency detector gives greater freedom in applying the loop filter along the lines that I originally proposed/imagined in my opening post? Perhaps I am not completely barking up the wrong tree?

author: G0HZU
author_rank: Super Contributor
timestamp: May 14, 2014, 10:11:13 pm
content: QuoteIt sounds like an interesting project. Maybe it would help people give advice if you posted up what frequency band you are planning to synthesise signals for.However, maybe I'm missing a trick here but the above system sounds like it won't work well at all... My main concern about your proposed FLL system is that I think it will suffer from an effective dead spot in the detector characteristic because of the response time of the DAC and the counter. But then I'm not sure what tech you are using for either of these blocks so I may be missing something fundamental here...i.e. is your VCO at a low frequency and naturally very stable? eg a crystal oscillator?I don't have any FLL design experience but I've got a lot of experience in designing high performance single loop PLLs (or at least I had a lot of experience designing them back in 1990-2003) This was for use in EW/ECM/ESM gear in the GHz region and the usual design goals threw up the conflicts you mentioned in your first post. i.e. there was a need for smallish step sizes but also low noise, low power, small size, very low spurious and fast tuning. Various offbeat alternative technologies were considered back then but we always went back to the classic PLL because of the size/power/weight limits.However, you might be interested in ways that HP used combined PLL+FLL technology in the 1980s to get very low close to carrier phase noise. They used a traditional PLL plus a very stable FM discriminator/delay line to produce a noise cancellation system (i.e. the FM discriminator produced the noise cancellation signal) to get the close to carrier noise very low indeed.Usually A PLL+FLL would use a highly stable 'discriminator' and the output of the low noise FM discriminator (when locked) will effectively deliver the mush and noise from the carrier and this can be craftily fed back as a cancellation signalI'd imagine there are various HP patents kicking about on the web about this old discriminator based noise cancellation technique. But this is really aimed at FLL+PLLs operating up at VHF/UHF and it is big, complex and expensive.I had a look at the Wolfsonmicro link about the FLL they designed and wasn't too impressed by the lack of any performance data. The main claim (over a PLL) seems to be versatility in setting the loop bandwidth digitally but modern PLL chips can be programmed with numerous phase detector gain settings anyway. Maybe I'm getting old and sceptical but I (so far) don't see any realistic value added by the FLL in that PDF. I only skimmed it but I was left with the feeling that I'd read something written by a marketeer trying to sell me something unique (but probably flawed)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 14, 2014, 11:33:19 pm
content: Quote from: GK on May 14, 2014, 04:12:22 amRead my post in detail: I suggested it for AC compensation only. Long term stability provided by the PLL guarantees stability and precision.Exactly the same as using gyro (rate) and accelerometer (static) sensors for stabilizing motion and flight platforms.QuoteEven if you count with a million times higher clock rate, you still only get one count every half cycle, which is what I was getting at. (Did I just write it wrong? Was it too vague?) Which represents a poleon the order ofthe input frequency (i.e., give or take some factor).QuoteIf you want it as fast as possible, you can use a sampling approach to remove ripple and reduce phase shift, pushing bandwidth closer to the operating frequency; but never to, or past. Note that analog sample-and-hold is precisely equivalent to digital sampling of a counter register, no need to invoke a specific example of both.This applies to any sort of single-input* frequency transducer.*A two variable transducer can produce instantaneous results, in the same way that a mechanical differentiator (i.e., dashpot) attached to a mechanical shaft produces a constant torque proportional to rotation rate, more-or-less instantaneous to the angular velocity. The electrical equivalent requires two linearly independent, continuous signals: preferably, quadrature sine waves. Triangles would work too, but squares certainly cannot. (By the same token, any phase detector which uses square waves in its method cannot detect anything happening between edges, and therefore is restricted to the same sampling-equivalent limit.)Tim

author: G0HZU
author_rank: Super Contributor
timestamp: May 17, 2014, 12:54:13 am
content: It's difficult to suggest what will and what won't work because there isn't enough info about the basic spec requirements for the proposed FLL/PLL.I'm now guessing it's probably something along the lines of a finely trimmed VCXO where settling time isn't an issue but there has to be really low noise and low spurious.Maybe it also has to be trimmable in very fine (fully synthesised) steps. It would be difficult to achieve this with a basic single loop PLL and so maybe this is why the counter/DAC/FLL approach has been proposed?In the past I've designed hybrid DDS/PLL local oscillators to achieve a similar thing for some receivers but it's very hard to get rid of all spurious terms on all frequencies. If I've guessed the requirements correctly then I can now kind of see how this would work if it all has to happen quite slowly. Therefore the counter/DAC deadspot probably won't be the problem I first thought it would be?

author: moffy
author_rank: Super Contributor
timestamp: May 19, 2014, 05:24:19 am
content: You might also be interested in this:http://www.semtech.com/images/datasheet/xe8000_tn_09_locked_loop.pdfThe Digital Frequency Locked Loop.

author: jimmc
author_rank: Frequent Contributor
timestamp: May 19, 2014, 10:41:32 pm
content: Sorry I've nothing to say about frequency locked loops, but have you missed something about PLLs?Quote from: GK on May 14, 2014, 01:52:29 amVery true, but you could add that once the unity gain intercept has been reached the phase shift can be allowed to rise again without compromising loop stability, thus further poles may be added so long as the are placed well above the intercept frequency. There is no ' intractable plateau', just a series of compromises.QuoteIf, for instance, your unity gain frequency (Fo) was 1/100 times the comparison frequency then adding a two pole active filter with a cut-of frequency at 10Fo and a damping factor of 0.5 will only add a few degrees of phase shift at the unity gain frequency but will attenuate the comparison frequency by almost 40dB.Jim

author: moffy
author_rank: Super Contributor
timestamp: May 20, 2014, 11:44:55 pm
content: PLL locking behaviour is highly non linear! You can only do linear analysis after the loop has locked, not before. Spurious frequency locking is a significant issue with PLL, so using a Frequency discriminator first can be a very good idea depending on the application.

author: jimmc
author_rank: Frequent Contributor
timestamp: May 21, 2014, 10:30:50 pm
content: Quote from: moffy on May 20, 2014, 11:44:55 pmGood point, ensuring that the loop is stable once locked does not mean that it will acquire lock in the first place. External help may be necessary in some cases.Where they can be used, dual (or quad) flip-flop phase comparators (eg CD4046 phase comp 2) provide inherent frequency discrimination to steer the PLL to the correct locking point.Jim

author: GK
author_rank: Super Contributor
timestamp: May 22, 2014, 05:10:05 am
content: Quote from: jimmc on May 19, 2014, 10:41:32 pmYes, you can always add another low pass pole for filtering purposes at a frequency that is high enough (above the unity loop gain frequency (UGLF)) so that it contibutes negligible additional degredation to the phase magin. This is in fact often done right at the VCO control input.However that is NOT what I was talking about. I need the additional filtering well below the ULGF. If you juggle the filter pole/zero frequencies below the ULGF for a compromise between phase margin and phase detector artefact supression you very much do reach an "intractable plateau" as far as maximum achievable supression < the ULGF goes.I've solved my design hurdel anyway, using a uC as a slow sampling frequency detector which achieves precicely the aim I detailed in my opening post (which I am not sure that everyone who replied actually bothered to understand). I have a full 180 degrees of phase margin to play with prior to filtering/servoing, rather than 90 degrees. My frequency-locked reference sidebands are now below the -135dB noise floor, which was not possible with a traditional phase locked loop.It's a sampled system in which the control loop is actually "open" >95% of the time.As for the application, despite protestations to the contrary, that's completely irrelevant.

author: GK
author_rank: Super Contributor
timestamp: May 22, 2014, 05:18:41 am
content: Quote from: T3sl4co1l on May 14, 2014, 11:33:19 pmI specifically wrote in my opening post that I DONT need "it as fast as possible".

author: ejeffrey
author_rank: Super Contributor
timestamp: May 22, 2014, 05:30:20 am
content: Quote from: GK on May 22, 2014, 05:10:05 amSome specificity on what you were expecting would have been really useful. Not the application, but what you want your P/FLL to do. Anyway, glad you got it working.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 22, 2014, 05:42:53 am
content: Quote from: GK on May 22, 2014, 05:18:41 amWell someone was talking about high frequency poles and phase margin and all. Seems to me they go hand in hand...If speed is not an issue, you can always dominant-pole the fuck out of it until the cows come home. Then (give or take the necessary zero for loop stability), your noise performance (until very close in) is that of the oscillator alone, adjusted only slowly by the PLL. Same thing as what you've just done with the slow sampling (give or take the PLL/FLL difference and phase margin), except the sampling occurs transiently. There is literally nothing DSP can do that analog can't. (Some things are easier yes, like when you have a lot of memory to push around, as opposed to needing a thousand inductors and capacitors of arbitrary value. But the fundamental equations are largely equivalent. In this case, the slow sampling is largely equivalent to a single pole at an equivalent frequency, an easy substitution.)Tim

author: GK
author_rank: Super Contributor
timestamp: May 22, 2014, 05:51:49 am
content: Quote from: T3sl4co1l on May 22, 2014, 05:42:53 amIt is completely pointless to "dominant-pole the fuck out of it". The zero required for stability puts an intractable limit to the maximum attenuation.That's the whole f%$#ing problem that I was at pains to articulate in my opening post. Furthermore, while I've stated that my control loops settling time isn't particularly important, I did not say that the ULGF could be lowered without limit. I have explored the limits and to reiterate for hopefully the last time, I require greater than typically achievable filter attenuation levels < the ULGF.Quote from: T3sl4co1l on May 22, 2014, 05:42:53 amNo it isn't, not by a long shot.

author: G0HZU
author_rank: Super Contributor
timestamp: May 22, 2014, 04:42:53 pm
content: QuoteGood to hear you got it workingCan you post up the relative improvement you saw between your FLL and the best the PLL could achieve? I'd be interested to know the fundamental frequency and the noise response you managed to achieve. I'm always interested in alternatives to a basic PLL.I had similar design issues (wrt sideband energy) back in the 1990s with various PLL chips from the main manufacturers. I managed to solve my problem with high ref sidebands by introducing my own discrete charge pump circuit onto the raw outputs of the PFD from the PLL chip. I managed to arrange/optimise the circuit such that there was strong cancellation of the ref freq energy from the PFD when the loop was locked. At the time it made a huge difference to a couple of our synthesiser designs. It could also be programmed digitally to allow the pump current to be altered dynamically. These days some of this type of functionality is built into modern PLL chips but my old circuit allowed fine optimisation of the components in the charge pump to minimise sideband energy.I found a paper from HP that outlined their PLL + FLL noise cancellation system from the 1980s. I outlined this advanced and clever technique of theirs back in my first post. This requires a very complex circuit but the plot below shows how well they managed to cancel the close to carrier phase noise with this system.This is for a 1GHz fundamental frequency and they managed to optimise the noise at 20kHz offset down to about -142dBc/Hz using the FLL discriminator to provide the cancellation signal. Mode 1 is the standard PLL and the other two modes use the discriminator based noise cancelling technique. Impressive!

author: G0HZU
author_rank: Super Contributor
timestamp: May 22, 2014, 08:49:58 pm
content: Quote from: ejeffrey on May 22, 2014, 05:30:20 amAgreed...Generally, it's nice to at least know some basic requirements as in frequency range and steps etc etc. is it RF or AF?I can remember evaluating old Plessey (and Motorola?) chips back in the 1990s as possible contenders for our more demanding synthesiser requirements. On paper, these looked really good with dual phase detectors. The idea is that the conventional PFD phase detector only works up until the loop is roughly locked. Then the fine (sampling) detector kicks in offering high detector gain and far lower sideband energy.The key selling point back then was lower filtering requirements to achieve low sideband spuriousHowever, we were able to design discrete circuits that performed better.I had a rummage through my stash of ancient synthesiser chips from about 25yrs ago and found these old Plessey chips. eg the 8821. I think these have the dual detector mode of operation. The point is that not all PLL chips are equal in terms of phase detector and spurious performance.