How to "isolate" FSK signal riding on DC-offset - Page 1
Forum section: electronics / projects

author: H.O
author_rank: Frequent Contributor
timestamp: October 10, 2025, 08:38:41 am
content: Hi,I'm embarrassingly rusty with analog stuff these days, give me a hand please :-)I have a FSK-signal (~1.6/3.2kHz, 6Vp-p) riding on a 35VDC bus. Or rather, it's "hanging" below the 35VDC-bus so the signal swings between 29 and 35VDC approximately. The bus is idle at 35VDC with "packets" of data being delivered with various delays between them (and varying length).I need to "isolate" the FSK-signal from the DC-offset and have it swingroughlysymmetrical around ground for the purpose of feeding into the Zero-cross detect module on a PIC18F57Q43 in order to measure the period of the AC waveform. The code was developed using a waveform generator and it seems to do what I needas long as I give it a proper signal- that's where I'm struggling at the moment.I have 1uF capacitor in series with the signal. This does (obviously) remove the 35VDC but the resulting signal idles at ground and swings to -6V instead of +/-3V. Not what I need.Adding a pullup-resistor to 3.3V makes it sort of symmetrical (enough for my purposes) but now, the DC-offset drifts and towards the end of a "message" the signal is almost swinging between ground and 6V instead of symmetrical around ground which obviously messes with the measurements. Not what I want.I probably could manage putting some overcomplicated contraption with OP-amp buffering, level shifters and stuff together. Not really what I want.I feel I must be overlooking the easy solution here.I'd appreciate any ideas, pointers and so on, thanks!Oh, and BTW, putting the scope probe on the ZCD input doesn't reveal anything due to how that peripheral works. The voltage on the pin is kept constant.

author: iMo
author_rank: Super Contributor
timestamp: October 10, 2025, 09:26:50 am
content: ..for example..

author: tooki
author_rank: Super Contributor
timestamp: October 10, 2025, 11:01:09 am
content: Using the ZCD just seems like a weird approach.(Also, did you actually use the design procedure in the datasheet to come up with your component values, or did you just wing it?)Anyway, leaving the ZCD behind:Couldn’t you use a resistor divider to reduce the signal to under 3.3V (e.g. divide by 11), then use one of the comparators already present in your MCU? 6V/11 ≈ 0.55V, which should be well within the comparator’s capabilities.Suppose we divide by 12 to give some headroom in case something goes wrong, and to make the math easier I’ll pretend the input actually goes to 36V (which I suspect there’s a good chance it actually is supposed to be).An 11k/1k resistor divider gives us exactly the 1/12 ratio we need.Vmax = 36V/12 = 3VVmin = (36V-6V)/12 = 2.5V(Also, 3.3V*12=39.6V, so this gives extra protection to the MCU input in case of spikes on the line.)So let’s set a threshold of 2.75V, the midpoint of the signal amplitude.Vref = 2.75V = 3.3V*(R2/R1+R2)ergo: 2.75V/3.3V = R2/(R1+R2) = 0.833So let’s use 18k for R1 and 82k for R2, giving us 0.820.82 * 3.3V = 2.706V actual VrefNow you can use interrupts on the comparator to generate your measurements.

author: H.O
author_rank: Frequent Contributor
timestamp: October 10, 2025, 11:12:58 am
content: Thanks iMo! But there must be more to it than that.In your simulation you're applying a constant AC-signal, correct? What happens at the ZCD node when the input-signal idles at 35VDC with short bursts of the signal?I've tried exactly your circuit but with or without the pulldown the resulting signal idles at GND and swings to negative, which was the reason I tried adding the pullup.Because the input signal idles at 35VDC the cap gets "biased" to that voltage. The cap/resistor node is effectively at ground. When the signal comes along it pulls charge out of the capacitor making the cap/resistor node go more or less below ground. Since the input signal never swings above the "idle voltage" of 35V the "output signal" never swings above ground. At least that's what I believe is happening.tooki,As for the capacitor value I winged it. For the resistor value (15k) I calculated it using the ZCD current source maximum current as per the datasheet.Many ways to skin a cat I say. The zero-cross detector is also available in the PIC, just like the comparators and at first I thought that would be the simplest way to do it, just slap a capacitor ther to remove the DC and add the appropriate resistor. Two components, just as with the comparator solution.Now, in reality, it might not be that easy and choosing another aproach might be needed. I already have the code working with ZCD though, so that would need to be redone.

author: tooki
author_rank: Super Contributor
timestamp: October 10, 2025, 02:16:58 pm
content: Quote from: H.O on October 10, 2025, 11:12:58 amWhy don’t you try calculating the cap and resistor values per the datasheet, then?!Quote from: H.O on October 10, 2025, 11:12:58 amWould it not simply be a matter of 1. configuring the comparator, and 2. using the comparator as the interrupt source instead of the ZCD?

author: H.O
author_rank: Frequent Contributor
timestamp: October 10, 2025, 03:44:47 pm
content: Quote from: tooki on October 10, 2025, 02:16:58 pmBecause I don't see how the value of the capacitor has anything to do with the problem. If I'm wrong I'd appreciate if you could enlighten me.The way I understand it is that the capacitor can help "move" the "trigger point" closer to the actual zero-crossing instead of around 0.8V. The impedance of the cap+resistor must be high enough to not overdrive the current source on the input. In my case the resistor handles that requirment on its own and I'm fine with triggering at 0.8Vif I could have the signal swing around ground.Again, if I misunderstood please let me know.Anyway, looks like I might have to switch to a comparator. It's not ideal though because even though the voltage is 35V at the moment it drops when more devices are placed on the bus so the threshold would need to be adjusted.Quote from: tooki on October 10, 2025, 11:01:09 amWell, the very first application they (source)list for ZCD peripheral is A/C period measurement - which is exactly what I'm trying to do. It's also a peripheral I hadn't worked with before so it was a learning experience.

author: 2N3055
author_rank: Super Contributor
timestamp: October 10, 2025, 04:21:06 pm
content: You need full divider to set voltage after C. And one resistor in series with capacitor to make amplitude smaller.

author: H.O
author_rank: Frequent Contributor
timestamp: October 10, 2025, 05:39:45 pm
content: Thanks, 2N3055 but again the input signal isn't symetrical around 32 or 35V or whatever.It sits "silent" at 35-36VDC for "long" periods of time and the signal swings "down" from there. I want to "move it" so it swings roughly symetrical around ground. It seems it wasn't that easy after all - makes me feel less think :-)

author: Benta
author_rank: Super Contributor
timestamp: October 10, 2025, 06:26:21 pm
content: The classical way is to extract the FSK (or ASK, whatever) signal by using a "signal/data slicer". This app note from AD shows the idea:https://www.analog.com/en/resources/technical-articles/data-slicing-techniques-for-uhf-ask-receivers.html(Fig. 4).Then you have a digital signal that can be shifted to whatever DC level you want.

author: langwadt
author_rank: Super Contributor
timestamp: October 10, 2025, 07:50:09 pm
content: in the "what I want" you have 35V be GND when when there is no signal and 35V be 3.3V when there is signal how can it be both?

author: 2N3055
author_rank: Super Contributor
timestamp: October 10, 2025, 07:51:54 pm
content: Quote from: H.O on October 10, 2025, 05:39:45 pmWell it is also a question of RC constants..This one swings around 1.7 V so you can use microcontroller's internal comparator if it has one. For a 3.3V micro.

author: shabaz
author_rank: Frequent Contributor
timestamp: October 10, 2025, 07:54:46 pm
content: I don't fully understand the issue or why the solutions didn't work, but I've never tried to use a microcontroller for zero-cross for demodulation.Here are two suggestions. For the first, maybe an alternative way is to move the problem to solve and just demodulate directly outside of the microcontroller. You have enough of a signal to feed it into a low-cost CD4046B chip. Just DC block with a series capacitor, and configure it for detecting one of the two tones. Then you'll have an unmodulated signal that can be fed into a microcontroller with little effort (probably just a couple of resistors as a potential divider) and simplifies the code too. Note: I've never tried at these low frequencies, I have tried higher frequencies with the CD4046B.The precise DC or AC voltages are irrelevant, so it could be fairly robust although dependent on passive component values. This assumes it's normal FSK, and that detection of just one tone is sufficient. You trade coding complexity versus components with this approach.For the second possible approach, you could use a P-channel MOSFET, which would be reliant on switching the full voltage (35V or whatever), based on that signal voltage. You'd end up with a more normal ground-referenced signal, regardless of the full voltage, provided that the signal voltage Vp-p is large enough to exceed Vgs. Then you can use a potential divider or other circuit, to feed that into the microcontroller, and configure your zero-cross accordingly (e.g. looks like Microchip devices have a ZCPINV adjustment - I don't use microchip parts so I don't know the detail). This second method is reliant on having access to the full voltage (so the MOSFET can switch it), I don't know if that is the case or not. If it wasn't the case, then it could be created using a capacitor and a schottky diode, admittedly a bit ugly, but should work at least. I don't see why zero cross is being considered, since even a normal interrupt could be used based on edge detect, and then that makes the problem disappear regarding a signal below ground being needed to feed as an input to the microcontroller.

author: MariuszD
author_rank: Regular Contributor
timestamp: October 10, 2025, 08:20:50 pm
content: Google: DC restoration circuit

author: H.O
author_rank: Frequent Contributor
timestamp: October 10, 2025, 08:45:35 pm
content: Quote from: langwadt on October 10, 2025, 07:50:09 pmNo, "what I want" shows (or meant to show) the signal at GND when idle and then swinging +/-3V around GND.To all,Again, I opted for the ZCD because it looked to be exactly what I needed. "All I had to do" (I thought) was to DC-block the signal with a simple capacitor - thatobviouslydidn't work due to the nature of the signal (I believe).Never worked with 4046 or other PLLs but as can be seen in the scope screenshot there's sometimes not even a full period of each frequency, I don't know if a PLL is able to lock onto that which is another reason I went the digital route, considering it's such low frequenices.I'm working on converting hardware and code to comparator instead, this was all a big waste of time.Quote from: shabaz on October 10, 2025, 07:54:46 pmSorry, I don't quite follow what you're trying to describe with the P-channel... would like to though if it would solve the original problem which is to remove all DC-offset from the signal shown in Reply#7, making it swing around GND.Quote from: MariuszD on October 10, 2025, 08:20:50 pmHmm, that looks to do the oposite of what I want. I have a signal with a DC-offset that I want to remove.Thank you all, ditching the ZCD for now.

author: langwadt
author_rank: Super Contributor
timestamp: October 10, 2025, 09:09:10 pm
content: Quote from: H.O on October 10, 2025, 08:45:35 pmyes so you want 35V to be 0V when idle and the same 35V be +3V when not idle

author: shabaz
author_rank: Frequent Contributor
timestamp: October 10, 2025, 09:29:05 pm
content: Quote from: H.O on October 10, 2025, 08:45:35 pmI was thinking something like the attached circuit, to achieve a normal logic level signal, so that there's no zero crossing (i.e. just normal GPIO or interrupt could be used). Thezenerschottky diode is only there if there is no separate +35V DC source, it makes an approximate +35V supply for the MOSFET. The two resistors on the right are a potential divider to scale down to 3.3V or whatever the microcontroller requires, and should be able to cope with the +35V level being lower, depending on the logic threshold range. It also doesn't really care if the 6Vp-p is lower, provided it's still sufficient to turn the MOSFET on. The output is inverted, but that's not noticeable for FSK.The circuit might need a few more components here and there for reliability, but I think it should function (or could be made to function).If the source signal is not stable (for instance, very varying input) I think the external FSK decoder (CD4046B) might be worth considering (but may depend on the overhead of good passive components - I don't know, I've only tried it once for FSK at a much higher frequency).EDIT: Corrected the diode type from Zener to Schottky.

author: H.O
author_rank: Frequent Contributor
timestamp: October 10, 2025, 09:38:51 pm
content: Quote from: langwadt on October 10, 2025, 09:09:10 pmYes, you're right! That IS in fact exactly what I want.When you put it that way it's quite clear that it really isn't as easy as throwing a few passives at it. :-) Thanks!

author: H.O
author_rank: Frequent Contributor
timestamp: October 10, 2025, 09:50:05 pm
content: @ shabazThank you, much appreciated! Will try the comparator approach first since I'm halfway there already.One thing though, the signal is sinusoidal and not digital but a schmitt-trigger input or external gate should clean that up nicely.

author: makebit
author_rank: Unknown
timestamp: October 10, 2025, 09:51:48 pm
content: Here is a good way, LTspice sim and PNG

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 11, 2025, 12:06:13 pm
content: Try the pullup resistor but add clamping diodes to restrict the signal to +-3V?

author: Ian.M
author_rank: Super Contributor
timestamp: October 11, 2025, 12:58:57 pm
content: Hmmm. Here's an understandable powerline FSK modulator for LTspice simulation (only), that's parameterised. Change its characteristics by editing the multi .param statement at the bottom of the modulator box. There's a RC filter (Re,Ce) with time constant of 1/20 of thebit timeperiod of the mark frequencyto shape the envelope to avoid unrealistic dV/dt at the start and end of the data packet Change the bit pattern by editing the PWL source just above it. Each bit in the PWL is of the form:+1nlevel+{tbit}level. 0V is space, 1V is mark, and 0.5 V is idle (no carrier).I've also designed a somewhat excessive 'HiFi' downshifter for the carrier, which brings it down to 0-3V, (assuming 6V pk-pk) using aLT6015'Over the Top' OPAMP as a differential amplifier with gain 0.5, and that also auto-adjusts for powerline voltage. D2 roughly compensates for the drop in D1 so it doesn't clip the negative peaks. N.B. Use close tolerance resistors or the CMRR will be poor.However Analog Devices (ex Linear Technology) parts are notably expensive, so even if you want to gild the Lily, you should probably look at other manufacturers for OPAMPs with a common mode range well above their positive supply.Incidentally, the reason the capacitor fed PIC ZCD module didn't do what you wanted was its internal current sources that servo the ZCD pin to keep it between the rails with its designed DC coupled input signal. As the PIC doesn't have a negative supply, their net effect on an AC coupled signal is to cause it to drift positive. You would need to DC restore after the coupling capacitor by clamping the peaks to +3V to get the input swing approximately centered on zero.Edit: corrected envelope time constant description.

author: makebit
author_rank: Unknown
timestamp: October 11, 2025, 03:19:47 pm
content: OP is whichever proposed demod circuit allowed to look very capacitive to the power line?...if you see my circuit from post #18, it doesnt look very capacitive to the powerline, so it doesnt interfere with the operation of some of the powerline modulator circuits....for example the one of the form that i generally show in post #18 above

author: H.O
author_rank: Frequent Contributor
timestamp: October 11, 2025, 09:20:43 pm
content: Thank you guys. I don't know what sort of loading is acceptable. This isn't something that's ever going into production or anything, it's a reverse engineering effort trying to figure out HOW the devices on this specific bus communicates.For the time being the comparator solution seems to work (but so did the ZCD until it got exposed to the real life signal). We'll see.