how to route codec (ADC/DAC), analog pins not all on one side - Page 1
Forum section: electronics / projects

author: loki42
author_rank: Frequent Contributor
timestamp: October 21, 2019, 07:27:15 am
content: So I'm attempting to route codec (PCM3168A) and if you look at figure 64 in the data sheet the layout example is rather minimal. The input and output digital interface is on the left and right sides of the chip and the analog input and output are on the top and bottom. This appears to make it almost impossible for me to not cross digital and analog traces. I'm rather worried about introducing digital noise into the inputs and outputs. Should I basically cut around the digital section with the ground plane keep out and then route the one sides digital traces under the component? Then nothing needs to cross the digital / analog plane boundary. My current layout has traces crossing and noise performance isn't near spec. 3.3 and 5 v are coming from separate LDOs, VCOM is buffered and I'm following the data sheet for bypassing.Are there any layout examples for a similar chip? The example board from TI isn't handy.

author: capt bullshot
author_rank: Super Contributor
timestamp: October 21, 2019, 07:56:14 am
content: Just don't split AGND and DGND, use one solid GND plane for everything (your whole board). Use the series resistors as indicated pg. 51 of the datasheet, these mitigate digital noise. Best placement of them would be at the respective signal source pin. Keep the other digital stuff (as indicated control MCU) slow (e.g. set the pin drivers of the MCU to their slowest working edge drive mode), and / or use series resistors too here. Otherwise, don't mix up analog and digital circuitry in your layout, and don't route digital traces (except the ones required for operation of the codec) through the analog part. Laws of physics take care now to keep the digital noise away from the analog though you don't split the plane.

author: loki42
author_rank: Frequent Contributor
timestamp: October 21, 2019, 01:34:48 pm
content: Sounds good. Is there a way I should route the two i2s signals around the respective analog in and out? Is under the part the right approach or should I cross them? I.e. the d out and d in are both going to the MCU.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 21, 2019, 01:39:35 pm
content: With a 4-layer board, you could just route the digital signals on the top layer, and the analog on the bottom, or conversely. There would be a solid ground plane (inner layer) between them.

author: capt bullshot
author_rank: Super Contributor
timestamp: October 21, 2019, 01:43:38 pm
content: Depends on how many layers your board has. The codec has a thermal pad, so you can't lay any traces on the top layer (I'd recommend against this anyway), and you shall not split the ground plane under the device, so you can't place traces to the layer carrying the plane, so often there's the only choice to route them outside. If you have enough layers, place a GND plane layer between the chip and these traces. I2C is rather slow and often used for initialisation of the codec, so you should have an eye on your software when it uses these lines, preferably keep them quit and in idle (high) state when playing or recording sound.Edit: Crossing the analog signals with the I2C signals on another layer most probably is the better way than routing the I2C all around the analog part. Avoid looping digital signals around the analog circuitry.Edit 2: Keep your power supplies to the codec clean. Not the 5V analog only but also the digital 3.3V. Sometimes a seperate linear regulator for these voltages helps, sometimes LC or RC filtering. Be careful with LC filtering, add enough damping to keep it from ringing. If there's a single (or very few) chip digital circuitry with little noisy digital I/O, one might get away with the proper usage of ceramic bypass caps on a common voltage rail.

author: loki42
author_rank: Frequent Contributor
timestamp: October 21, 2019, 10:27:48 pm
content: The 3.3 and 5 v power is from separate LDOs / converters. 2 layer board. I'm not that worried about the I2C lines but the very high speed and always in use I2S TDM lines. D out and d in.

author: capt bullshot
author_rank: Super Contributor
timestamp: October 22, 2019, 06:01:37 am
content: With 2 layers it's very important to have a as solid as possible GND plane, don't slit the plane by traces, I guess this will turn out rather difficult to layout - depends on the complexity of your circuit. At least four layers might be the better choice. A commonly used technique is to pour GND on both sides of the PCB and stitch it with vias to bridge slits in the pours (as a last step of finishing the layout). Before you pour the GND, make sure every GND Pin is connected by as short and as wide as possible traces.Ideally, the I2S Clk and Data lines operate synchronously to the sampling rate, so their noise gets attenuated by their high frequency nature and the comb filter effect of synchronous sampling. Anyway, the series resistors indicated in the data sheet should mitigate their interference with the analog circuitry. You'd still have to take care of the rest of the digital circuitry to avoid coupling into the analog part, a clumsy placed digital signal, supply or GND trace can ruin your day here as well as not sufficient or ringing decoupling capacitors on the digital side.Edit: With a 2 layer setup, if well thought, it can be useful to split the GND plane to keep digital (lower frequency) currents away from the analog part. Higher freqency currents are kept away by physics, since their return path follows the trace. Beware, you must not cross the slit with any higher speed signal including supplies, and the codec chip would sit over the connection point of the split plane. You need very careful decoupling of the supplies (make the current path over the split high impedance) to keep noise from coupling over the split.

author: loki42
author_rank: Frequent Contributor
timestamp: October 22, 2019, 07:49:28 am
content: Here's the current layout for the codec, the current one i'm testing is the same as this but with vias covering the EPAD. I've just removed the TI recommended vias from the EPAD if I want to route through there. So the stuff in the blue box is the digital section of the codec. I've seen confusing advice on if MCLK should be treated as digital. It's very high frequency so I assumed yes. You can see some of the outs are routed around EPAD. I wanted to check if not crossing the digital lines would help. It doesn't make any difference. The input and output signals are differential.I'm thinking of routing the right side digital stuff under the part and making the digital stuff surrounded by slots. I'm following the design for terminating resistors. I'm confused if the ones for WCLK and BCLK need to be close to the part though, as I'm routing BCLK and WCLK to both sides of the part from a single terminating resistor. With the codec on the join approach I'm not sure how to do that with this chip. I'm also confused about how you'd route power in the case.

author: capt bullshot
author_rank: Super Contributor
timestamp: October 22, 2019, 08:41:41 am
content: This layout does look no good to me. First of all, do not route anything between the pads and the thermal pad. Then use the thermal pad as a central GND for the codec chip, route all GND pins directly to the thermal pad. Connect the thermal pad to the GND plane using a convenient amount of vias. Since it's a thermal pad intended to sink some heat, place the vias evenly spaced over the entire area. Place the decoupling caps in a way that both ends of the caps are very shortly (no vias) routed to the corresponding GND and Vxx pins of the codec. Connect the GND ends of the capacitors to the GND plane. Do this as the very first step in your layout. Then route all the signals around the caps, move them slightly if necessary, but do not open the direct connections to GND and Vxx.Place the analog stuff e.g. west of the codec and the digital stuff east (or any other suitable orientation). There will be some analog or digital lines left that must be routed around the chip, the only way to avoid this would be an at least 4 layer board. If you must route digital lines around the chip, don't split the plane in a way that these traces cross the slit, 90% of the use cases it's better to not split the plane at all. If you place slits in the plane, don't cross the slits with any signal (including Power supply traces and GND / shield of external connectors that might form a loop of any kind). Best way to handle shields of external connectors is to solidly bond them to a solid GND plane.Anyway, from that small piece of layout show, I'd recommend using a 4 layer board, it's way more easier then to provide the solid GND plane. Still pour copper GND on the other layers if useful and achievable.

author: mengfei
author_rank: Regular Contributor
timestamp: October 22, 2019, 09:05:32 am
content: Nope on that routing.if your really stucked with 2 layer, you could Fan out, add vias then place some of those SMD's directly below U4Bypass caps as close as possible to supply pin & shorted gnd return.Follow the recommended layout of the vendor for better results as they have done a lot of test, trial & error runs on those parts.

author: loki42
author_rank: Frequent Contributor
timestamp: October 23, 2019, 08:18:42 am
content: Here's the updated routing, I've switched to 4 layers and the ground isn't split. I am a bit confused about what to do with the power plan given all the different voltages I've got. Otherwise if there's any other feedback I'd love to hear it. I'm crossing all the analog differential output signals at one place with the digital signals. I'm still a bit worried about where the digital signals being routed near the 5VA power.I think I have placed the decoupling caps as suggested but I'm not sure if you mean something else. If there's any other advice on getting closer to the full performance (though I know 24 bit is tough!) of the codec I'd love to know.

author: mrjoda
author_rank: Regular Contributor
timestamp: October 23, 2019, 08:33:03 am
content: Hi,avoid the acute angles, it's called Acid traps (google some PCB layout guidelines). I do not like the routing of 3V3VA to oscillator. I would not share one capacitor and one trace with power pad of chip. Otherwise it looks better than in previous case.There are many other things that should be improved, like grounding vias for example, loop reducing and etc.

author: loki42
author_rank: Frequent Contributor
timestamp: October 23, 2019, 09:21:23 am
content: I'm not sure what you mean by the 3V3VA to oscillator, there are 3 caps there. I've made the power traces planes on a separate layer though I'm not sure if that's a good idea as the multiple different power planes will be over a single ground plane. Not sure if that's better or worse than just running traces.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 23, 2019, 12:40:41 pm
content: There are a bit too many vias in this thermal pad IMO. This could cause definite soldering issues, unless the vias are plugged, which would be costly and unnecessary here. Just a thought. A thermal pad is not swiss cheese either.

author: loki42
author_rank: Frequent Contributor
timestamp: October 23, 2019, 02:08:04 pm
content: That's just the default footprint from TI. I'll reduce the number. Their paste layer is a bit weird too. The recommend just one big aperture.Any advice on the 3.3 / 5v / 5v analog power planes? Should I run the split power planes or use traces?

author: capt bullshot
author_rank: Super Contributor
timestamp: October 23, 2019, 03:41:42 pm
content: If there's more than 2 or 3 power rails that you can't divide into planes with a few simple sketches, I do prefer to run traces as wide and as short as possible, then pour copper of the respective potential around the traces, with the result similar to planes (little non-copper area left). Your component placement should keep the components running off a particular rail together, so in the end result it'll look like a split power plane. Keep the goal in your mind: GND and supply distribution shall be low impedance.Regarding the thermal pad paste: One big aperture may work, often an array of 4 to 9 equally spaced apertures is used to improve production yield - ask your EMS for best results and experience.

author: thm_w
author_rank: Super Contributor
timestamp: October 24, 2019, 12:07:57 am
content: Routing looks so much better now.Quote from: mrjoda on October 23, 2019, 08:33:03 amDoesn't matter.For the 3v3, there are three caps in that area, probably not ideal but will work.Although if that purple line is the 3v3 power trace going off, I would fatten that a bit, no reason to have power trace so thin.

author: loki42
author_rank: Frequent Contributor
timestamp: October 24, 2019, 12:31:10 am
content: Do you mean the acid traps stuff doesn't matter? I've seen a few people say it hasn't been an issue for a decade or two.What would be ideal for the 3v3 cap wise? Oh and there are planes where ever there are power traces so I've made that trace big now to make that more obvious, as @capt bullshot suggested.I'm not sure if I need to use anything more snazzy than an LM358 to buffer VCOM. I given it's buffering the reference any noise in there will couple directly but I'm not sure if the level with no gain is an issue.

author: mengfei
author_rank: Regular Contributor
timestamp: October 24, 2019, 01:28:42 am
content: what's with the weird traces? like those below U4 which should have all been straight?what software are you using? if possible get supply directly from the supply line like the last output cap & not share all on a single rail "IF" possibleacid traps are corners where chemicals can be well trappedyour lucky you can work with multi layer boards while I'm still doing single side boards for SMPS, PTH + SMD's

author: loki42
author_rank: Frequent Contributor
timestamp: October 24, 2019, 01:51:51 am
content: The ones under U4 just become the ground plane, if you look at the image with the planes.

author: mengfei
author_rank: Regular Contributor
timestamp: October 24, 2019, 02:53:21 am
content: Quote from: loki42 on October 24, 2019, 01:51:51 amI meant the traces going inside U4 pins, why are they crooked? & some other traces have weird routing too, did you use auto route?

author: loki42
author_rank: Frequent Contributor
timestamp: October 24, 2019, 03:10:48 am
content: no but I did use the push / shove router and did move a few things. Is there any performance issue with this or is it aesthetic?Should I look for a buffer with lower noise than the LM358 or will it be low enough to not be an issue buffering VCOM. Should I worry about low frequency return paths passing under the oscillator?

author: capt bullshot
author_rank: Super Contributor
timestamp: October 24, 2019, 05:27:20 am
content: Quote from: loki42 on October 24, 2019, 12:31:10 amDepends on your circuit. If VCOM isn't loaded (e.g. used like the example circuits), you don't need a buffer at all. If VCOM is loaded by anything that can cause current flowing into and out of the LM358 (any kind of AC), the result will be terrible. If you have a nice and steady DC load, you might get away with proper filtering.The crooking mentioned is an aesthetic issue and surely has no impact on the performance.Acid traps shouldn't be an issue with a modern fabricated PCB. Anyway, I do avoid acute angles, crooking etc. since it makes the layout look ugly to an experienced eye and it'll easily get judged as a pointless beginners work that wouldn't work anyway. If you do it for your own and don't showcase it and it works, aesthetics don't matter.

author: loki42
author_rank: Frequent Contributor
timestamp: October 24, 2019, 05:50:10 am
content: I'm not sure how much load is unloaded, they are used to bias the op amps through 1 M resistors. It'll be around 25 uA total. I could get rid of that by switching to dual supplies.

author: capt bullshot
author_rank: Super Contributor
timestamp: October 24, 2019, 06:14:22 am
content: 1M resistors in the analog signal path isn't particular low noise anyway ... Biasing a "+" input of an OPAMP could be considered "no load", depends on the OPAMP, but the bias node itself would still have to be low impedance for AC. Your issue might not only be layout related.

author: loki42
author_rank: Frequent Contributor
timestamp: October 24, 2019, 07:00:02 am
content: The inputs need to be high impedance. I've got for an op amp with low current noise (though this seems really hard to work out from some data sheets... ) If I ran into the op amp + input and used dual supply voltages would that mean lower noise? The op amp is 0.6 fA/√Hz and the Johnson noise would be 127 nV / √Hz for the resistor I think? I think that means that the resistor noise would dominate?

author: capt bullshot
author_rank: Super Contributor
timestamp: October 24, 2019, 07:27:30 am
content: If the resistor is n series with the input and dominaters the node impedance, yes, I'd agree.Anyway, high impedance input doesn't neccessarily mean there must be a high value resistor placed in series with the signal input, it's the node impedance connected to that input that is relevant.It's a bit fishing in the dark without schematic and application relevant information (e.g. what is the signal source and its requirements / properties). Can't tell if dual supply helps without context.Many applications have been successfully solved before, and once you've found such often it's adviseable to follow that path.

author: loki42
author_rank: Frequent Contributor
timestamp: October 24, 2019, 07:31:51 am
content: The resistor isn't in series. It's biasing from the VCOM. I simulated it LT spice and the noise contribution from the resistor appears quite low.

author: capt bullshot
author_rank: Super Contributor
timestamp: October 24, 2019, 07:33:38 am
content: For analysis of the root cause of the noise, it might be helpful if you're able to feed the ADC output samples into all kind of visual display (long and short term waveform display, spectrum display / FFT). This could help you to judge if the noise originates from a white noise source, or is rather correlated to digital noise of your system.QuoteShould be OK then.

author: thm_w
author_rank: Super Contributor
timestamp: October 25, 2019, 12:55:28 am
content: Quote from: loki42 on October 24, 2019, 12:31:10 amSorry for being confusing:- Yes acid traps stuff does not matter, at all.- 3 3v3 caps is fine, I was responding to single via that mrjoda pointed out is not "ideal", but probably going to be OK.VCOM, I don't know enough to comment.

author: loki42
author_rank: Frequent Contributor
timestamp: November 04, 2019, 03:40:16 am
content: So I've got the 4 layer version, assembled it and tested it!It's worse. Much worse. The 2 layer board with the big splits in the ground planes and the weird routing outperforms it on noise considerably. I was really hoping the 4 layer board would be better but it has not. I'm attempting to work out why it's worse. The output stage is noisy, even though schematic wise that part of the design has not changed. The differences are, it's 4 layers and doesn't have any splits / slots in the ground plane. The previous design had a slot in the ground plane separating the analog side from the digital.

author: capt bullshot
author_rank: Super Contributor
timestamp: November 04, 2019, 06:30:55 am
content: Sorry for pointing you into this direction (non-split GND plane), I didn't expect things to get worse. I'm still interested in the root cause.

author: loki42
author_rank: Frequent Contributor
timestamp: November 04, 2019, 07:42:09 am
content: all good, it was interesting to try! Though I've got no idea how to improve it, given I don't really understand what's going on.Basically the process was: I wanted to change how on/off switching worked (bypass). Before it was done with relays which are big and expensive, have annoying switching noise and very high current usage. I switched to CMOS switching. It works well, but to do so I moved a bunch of stuff around. The new layout was much noisier than the relay based one, though all I'd done was add the CMOS switches, and move the op amps lower on the PCB (changing their return paths to be closer to the oscillator).Obviously I assumed the CMOS switch was the problem and bypassed that, replacing it with bus wires. No improvement. When the switch was there, no noise in bypass mode when signal is still going through the CMOS but not the op amps. The CMOS in/out is biased with VCOM so maybe the additional current there is degrading the buffer performance. Otherwise I think it has to be the different op amp location, though I'm not sure how easily It'll be for me to change that and fit everything in.I then asked here and got the layout advice, so changed that to 4 layer, redid all the codec routing etc, no slots etc. That made the 4 layer board the worst of the 3, much to my disappointment. I've tried different (much lower noise) op amps for the VCOM buffer with no noticeable change in performance.Noise is about 130 mV p to p. Relay version was 75 mV and my target would be 50 mV. I understands the number will change quite a bit depending on oscilloscope settings / bandwidth etc, but for a rough idea. I've attached the schematics for the switch and output buffer section in case the problem isn't purely layout as well as the whole layout. This is the 4 layer version, digital on the south west, analog north east. Previously there was a slot in the hatched red area between the codec and digital stuff.The cyan lines show my thoughts on what the dominant low frequency return paths for currents are. The PCB is for audio so noise below 20 khz is the main worry. Op amps used to be where the switches are now, and relays were near where op amps are.

author: capt bullshot
author_rank: Super Contributor
timestamp: November 04, 2019, 08:57:40 am
content: First thoughts:Did you try decoupling the VCOMAD and VCOMDA rails using a large (10uF ballpark) capacitor?For a 5V single supply analog circuitry design, I'd establish one single virtual GND at VCC/2, heavily bypassed to GND and VCC, and use this for everything (like the GND in a dual supply design).What happens to the noise level if you "disable" (maybe pull reset or vhatever does the) your digital stuff?The MCP6004 doesn't look exactly like a typical audio OpAmp to me, but I think that's the least thing to be concerned of now, regarding the quite high pp noise level.

author: loki42
author_rank: Frequent Contributor
timestamp: November 04, 2019, 02:50:57 pm
content: I was using TL074 as well, i've tried both. I tried the MCP6004 for the lower current noise, but I might have misread the datasheet...It looks like it's got much lower current noise, and the the impedance I'm running at that should dominate over the voltage noise, I think? Either way it doesn't seem to be the main issue.With the virtual ground how do you then bias for the codec? The inputs need to be biased to VCOMAD right?I can try more decoupling on the VCOMAD / VCOMDA rails. They both have 10 uF caps on them then smaller caps near where they are used. The 10 uF are ceramic.

author: capt bullshot
author_rank: Super Contributor
timestamp: November 04, 2019, 04:24:30 pm
content: Quote from: loki42 on November 04, 2019, 02:50:57 pmAgree, I believe it's not the main issue now. Don't look at the input noise specs alone, check CMRR / PSRR and your supply rail too. A noisy supply voltage can spoil your amps performance. 50mV peak-to-peak noise looks pretty hefty for audio stuff, should be way lower, so I believe there's more issues to your circuit than the layout and the choice of OpAmp alone.QuoteThe codec has differential inputs, the typical bias required is VCC/2 when DC coupling is used. So any voltage near enough to VCC/2 can be used to bias the inputs and the OpAmp circuits.QuoteThe datasheet suggests to use electrolytics. That may have two reasons:- In 2008, 10uF ceramics weren't that commonly available, so they just specified electrolytic- The circuit needs some ESR here, the ESR of a ceramic cap is too small and causes oscillationRegarding your ouput amplifier circuit: The input impedance is lower than the minimum allowed value regarding the datasheet - this might be an issue, though I don't think of a noise issue, rather limiting the max. amplitude.There's no CMRR or PSRR specified for the codec, so you want really clean power supply rails - did you check the analog VCC rail for noise, and does this noise correlate with the output noise?More ideas:What is the output noise if the output is digitally muted (digital processing outputs a continuous stream of zeros, not the processed input)?Remove the codec from the PCB, and replace it by bridge wires (codec input to codec output), then check the noise of the analog circuitry alone.

author: loki42
author_rank: Frequent Contributor
timestamp: November 05, 2019, 06:11:57 am
content: MCP6004 PSRR 86 CMRR 76 Noise current 0.6 fA noise voltage 28 nVTL074 PSRR 86 CMRR 86 Noise current 0.01pA noise voltage 15 nVSO the CMRR could be an issue, but i've tested with the TL074 as well.What's the utility of using VCOM vs just a VCC/2 then for bias? No need for the extra resistors? If it's saving some resistors but needs an extra dual op amp as a buffer that sounds like I'm doing it wrong.Output noise is identical when muted. The relay based circuit had very low output noise.I'll try electrolytics there, I didn't think of ESR and wanted to save space.The VCC rail is going through an LDO and ferrite bead. The ferrite might not be filtering right as I do find using beads correctly a bit confusing. The power section is identical for the previous relay based version though, that didn't have the output noise issues. the VCC rails do have quite a bit of noise on them though. I'm not sure how much is too much, but it's around 85mv p p & RMS of 27mv. Maybe the new type of switching is causing the LDO to work harder? Previously the relay was running of the 3v3 supply and the CMOS switches are on the 5V.The codec is a bit fiddly to desolder and solder back on so I'll try the other options first...

author: capt bullshot
author_rank: Super Contributor
timestamp: November 05, 2019, 06:58:22 am
content: Quote from: loki42 on November 05, 2019, 06:11:57 amPSRR and CMRR decrease with increasing frequency, some manufacturers put diagrams of CMRR and PSRR vs. frequency into their datasheets. Anyway, ATM I believe the culprit is somewhere else, though some optimization might be achievable here once the root cause is fixed.QuoteYes, it saves the resistors, handy if you don't need to buffer the voltage.QuoteSo it's related to the DAC part and the increase came with the analog MUX. I wouldn't expect any significant PSRR from a 4053 type analog switchQuoteThe noise on the supply rail is way too high for any kind of audio circuitry, single digit mV or even less is what you want. Even for a digital rail I'd consider this too high. I'd guess this couples through the DAC part of the codec.Ferrite beads have little to no effect within the audio frequency range, usually they show significant damping from single digit MHz upwards. An LDO might not be sufficient to dampen switch mode supply noise, some LDOs have really poor PSRR above some 100Hz. RC or RLC filtering the LDO input can help here, or use a rather expensive LDO that has a good PSRR for higher frequencies. SMPS noise can couple through GND into analog circuitry, too.

author: loki42
author_rank: Frequent Contributor
timestamp: November 07, 2019, 01:00:17 am
content: I think the actual number of the noise measurements are probably gibberish. The differences in levels between the two units probably is useful though. I'm checking that with oscilloscope probes so I'm getting a ton of extra noises.The LDO I'm using is a MCP1802, it's described as high PSRR (70dB @ 10kHz)the SMPS is TPS562200DDCR, which on the TI power designer sim has 25 mv p to p ripple

author: capt bullshot
author_rank: Super Contributor
timestamp: November 07, 2019, 06:58:19 am
content: Quote from: loki42 on November 07, 2019, 01:00:17 amIf you can, check the noise with the switcher disabled, otherwise same setup.QuoteLooks OK in the first place, the LDO appears to have a quite poor input step / transient response at a few 100kHz, so I still could imagine the switching frequency (not the ripple, but rather the switching transients) passing through. One should see a significant difference with the switcher disabled then. Otherwise, 650kHz / 25mV is rather easy to filter, but one must be careful to avoid interference propagated through GND and external wiring (maybe add a common mode choke to the power input)Anyway, I'm starting to run out of ideas now ...

author: loki42
author_rank: Frequent Contributor
timestamp: November 07, 2019, 07:49:22 am
content: I just tested with all the switches removed and the noise performance is better. It's interesting because the switches sound fine when in bypass mode, when the signal is still going through them but not the codec, but when they are on and the codec is on then it's quite bad. I wonder if it's anything to do with the enable signal to the switches? That is coming from the digital side of the board right around. This was also the case with the relays though, but in the case the line was only high for a few milliseconds.I did change one other thing between this version and the previous relay based boards, which is that I switched to a different oscillator, from the same company as it was cheaper and had slightly better stats, but was in a larger footprint.

author: loki42
author_rank: Frequent Contributor
timestamp: November 07, 2019, 08:00:29 am
content: Oh and I tried a resistor voltage divider instead of VCOM and it sounded really distorted. I wonder if that was an issue with the bias resistors or something else, or just that it exposes the noise in the 5VA supply more.

author: capt bullshot
author_rank: Super Contributor
timestamp: November 07, 2019, 01:13:30 pm
content: Quote from: loki42 on November 07, 2019, 07:49:22 amYes, digital outputs can couple digital VCC noise into analog parts, they're rather low impedance coupled to the respective GND or VDD rail of the micro. So any noise that's on the digital supply will appear on the digital outputs. If the signal is low speed, this is rather easy to mitigate by an RC filter (in case GND to filter against is clean).DId you properly bypass (large cap to GND) your resistive divider instead of VCOM, did you measure if the divider output deviates from ideal midpoint due to loading? Excessive common mode voltage could lead to clipping of the differential signal, im my imagination this would sound distorted. WIthout bypassing, the resistive divider forwards AVCC noise to that virtual GND, that's why one bypasses this.

author: loki42
author_rank: Frequent Contributor
timestamp: November 12, 2019, 12:21:09 am
content: I did bypass the resistive divider (47 uF) and the output seemed sensible, though I didn't measure how different it was to VCOM.I do have an apology though... so I still had worse noise with no switches in but I've now realised what the issue was. The negative output from the DAC wasn't properly soldered and actually wasn't connected, so the differential output wasn't doing it's thing, thus the significant noise introduction. I now have about the same noise as the relay version. So basically it's all good. I'm not sure how I missed that the pin wasn't soldered correctly!I'm not sure if the move to 4 layer was needed but things are working well, I am contemplating cleaning the AVCC rail more to remove the switcher noise but I'm not sure how important this is. I've seen some inductors with similar milliohm rating to the ferrite bead so maybe I should swap that out to create an LC filter designed to remove the switcher frequency? It's 650 kHz so far from the audio spectrum, so I'm not sure how much filtering it out will improve performance.

author: capt bullshot
author_rank: Super Contributor
timestamp: November 12, 2019, 07:17:13 am
content: Quote from: loki42 on November 12, 2019, 12:21:09 amLOL, stuff like this just happens. I remember having spoiled a whole day of hardware debugging because I didn't notice the scope probe was set to 1:1 instead of 10:1. Fixed that with tape as soon as discovered, then bought better quality 10:1 (non-switchable) probes.QuoteDepends. Switching noise on power rails can affect ADCs / DACs in rather subtle ways, I had a design using a slow ouput rate 24 Bit delta/sigma converter that was seriously affected by supply ripple way above the passband. The ripple coupled into the comparator node that was operating at high frequency and very sensitive threshold (that's the nature of delta/sigma conversion). Most probably, the outside amplifiers operating in the analog audio frequency range are less sensitive to 650kHz switching ripple.

author: loki42
author_rank: Frequent Contributor
timestamp: November 12, 2019, 08:04:52 am
content: Yeah, I thought there might be interaction with the higher internal frequencies of the delta sigma codec. Do you think it's worth adding an LC filter? I've been looking and some 1uH 8.5mOhm inductors that are pretty cheap and would be minimal extra cost. That's similar power loss compared to the ferrite bead and I assume I'd be able to replace it with the LC filter. The annoying bit is the low value resistor for dampening.

author: capt bullshot
author_rank: Super Contributor
timestamp: November 12, 2019, 08:26:58 am
content: Regarding LC filtering, I always preferred RC filtering with maybe an additional L. LC alone or even a ferrite bead can cause ugly ringing, making things worse. I'd go to include significant resistive damping in the filter. If your circuit allows for the voltage drop, start with 10R (in series to the inductor or instead the inductor), a some 10uF ceramic can achieve a lot then. And check the switching regulator doesn't go into "low power" modes, causing heavy lower frequency ripple.

author: loki42
author_rank: Frequent Contributor
timestamp: November 12, 2019, 08:41:37 am
content: The circuit can't cope with that level of voltage drop. I've just been looking at circuits like :https://www.analog.com/en/technical-articles/switching-regulator-noise-reduction-with-an-LC-Filter.htmlA Pi style filter looks pretty straight forward and the component count is low. Though I'm not sure how to select what the cut off frequency should be. I assume for filtering DC you just want it as low as possible for a given component cost. 1uH and 2 10uF seem to give me a 25khz cutoff frequency unless I'm calculating that wrong. I've been reading through :http://www.ti.com/lit/an/snva538/snva538.pdfas well.

author: capt bullshot
author_rank: Super Contributor
timestamp: November 12, 2019, 10:51:10 am
content: Analog (and former LT) has some quite useful application notes. To me, the hint "place a filter at the input of your buck regulator too" looks more useful than all the formulas from the TI paper. Corner frequency of the filters doesn't matter too much, as long as it low enough to attenuate the lowest frequency ripple (beware of "pulse-skipping eco-mode" and the like) that occurs in practice - for this reason I like high frequency switchers like the one you used. Anyway, if you do LC filtering, add damping (e.g. ESR of non-ceramic capacitors, high-loss inductance or real resistors in series or parallel with the reactive components).