i am looking for an easy vhdl RISC SoC - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: June 19, 2014, 07:58:11 am
content: hi guysi have looked at open cores org but i haven't find nothing that matches with my constraints- easy ( i do not have resources/time to look at big project, also i am not so skilled about HDL)- written in vhdl code (i do not have any tool for verilog, systemC, etc)- full SoC, CPU plus {RAM, UART, TIMER}- toolchain supported (i need to program it in C)- RISC oriented (with/without pipeline implementation)could you suggest me something ?

author: hamster_nz
author_rank: Super Contributor
timestamp: June 19, 2014, 08:08:40 am
content: Have a look at the zpuino project.http://www.alvie.com/zpuino/

author: legacy
author_rank: Super Contributor
timestamp: June 19, 2014, 12:44:23 pm
content: already seen, but1) it is not RISC, it is stack machine2) it is too much big with a lot of things arranged into a complex tree3) it is board oriented, especially for Xilinx Spartan3e, which means the bram has been planned and arranged into b24 format, which is not portable and which requires Xilinx tools in order to load an elf inside the bram4) i not like the project at alli am looking for something simpler and smaller, MIPS_I for example

author: miguelvp
author_rank: Super Contributor
timestamp: June 19, 2014, 05:41:21 pm
content: OpenRisc 1000 at open cores, but it's verilogSoft core from ARM but unless you are a student it's probably cost prohibited but I have not inquire to the cost so it's an unknown (cortex-m0 through m3 I think).Not sure if in VHDL or VerilogThere are some dev kits for under $1000 I think around $600 and not sure what kind of license they supplyGoogle Cortex-M0 soft coreThere is an ARM core on open cores but it's in beta and not sure of what it has.or get an SoC FPGA based dev kit like this one for $200http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=836If you are going to require a RISC processor why not get an FPGA that already has it built in?

author: free_electron
author_rank: Super Contributor
timestamp: June 19, 2014, 06:03:49 pm
content: Quotedepends on your definition of easy. an SOC is a very complex device. a core is a simple device . flick an 8051 in there.Quotewhaddayamean i don't have tools ? synopsys , modelsim , quartus, ISE all are language agnostic. it doesn't matter if using VHDL or Verilog.Quotethat's not a Soc (not according to my definition. it only starts being an soc once it has DMA , MMU , FPU , MAC, SATA, USB, and a crapload of other stuff on board.. .. grab a 8051 core. has ram ,uarts, timers, gpio. all you want. it is a pure harvard machine. easy to work with. well known core, tons of tools and compilers.Quote8051 works fine. plenty of c compilers for itQuoteoregano systems has a pipelined 8051 core. as for RISC. why do you want half arsed processors with only 5 instructions where you have to do all the work. the more instructions the better.This smells like homework. "Must be risc, Must be VHDL , Must be C, MUST be pipelined" , because these are the requirements of the course... not because the application demands these features.

author: legacy
author_rank: Super Contributor
timestamp: June 19, 2014, 11:49:47 pm
content: Quote from: free_electron on June 19, 2014, 06:03:49 pmeasy means- no cache- no MMU- no DMA- no strange features that increase the complexity of the wholeQuotebecause- i have "VHDL studio" (it is a tool, simulator), it accepts only VHDL- my Tina license for HDL accepts only VHDL (i have not enough money to buy the Verilog license)- i both VHDL design book, i do not have any Verilog Book- i know VHDL, i am learning VerilogQuoteSoC stands for System On Chip, a minimal System is composed by- CPU- RAM/ROM (where it boots and executes application (.text), and where it load/store data (.data))- something to interact with it, usually a serial port (uart plus RS232 of FTI-uart-to-usb)that is minimal SoC, than you can add- DMA- FPU- MMU- LAN- SATA- USB- LCD (like HD44780- LCD LVDS (like the laptop one)- GPIO- a crapload of other stuff on boardQuote8051- It is not RISC, it is CISC- it may be pipelined- it may be fast (like Dallas 80C400, or more faster)- it is not a Von Neumann machine, data and code are leaving on separated spaces (except than if you mix PSEN with rd/wr, i don't know if it is still possible when the flash is inside the Chip)- It is supported by SDCC, gcc and llvm are not able to compile for it.- Also it is 8bit, i'd like pure 32bit machine.Quotea MIPS32 core may be fantastic: a lot of instructions and possibilities (i think)Quotebecause i want it that way, it's for hobby learning purpose, i know MIPS very well (i know ARM for the most, i worked with nxp LPC2888 realizing an arm prototype board), but the greatest part of what i have read, studied and understood has the contents of a lot of MIPS skills (the book "See the MIPS run", for example, or the experience with the "MIPS INC Atlas board") and now for my hobby i have limited amount of time.I mean i could learn 8051 and toy with it on fpga (if i found a good 8051-SoC in VHDL), but i do not know 8051 in details, i have toyed with Dallas Tini-Java (which is 80C390, '51 core), but it was 2001 and i have no tools and skills for it.

author: hamster_nz
author_rank: Super Contributor
timestamp: June 19, 2014, 11:51:44 pm
content: Quote from: free_electron on June 19, 2014, 06:03:49 pmI guess the original poster believes that writing a complete pipelined RISC core, creating periherals, verifying it and building C toolchain support is a trivial task, it should take no more than a handful of VHDL files. On top of that it doesn't need to leverage any of underlying FPGA features to work efficiently.If I was to rephrase his requirements in software terms he might see how unrealistic they are:I want a small cross-platfrom OS, requirements are:- easy ( i do not have resources/time to look at big project, also i am not so skilled about C)- written in C code- full networking stack, SCSI I/O stack and GUI- hardware independant - must work on any CPU- Should be POSIX complient, and RTOS would be nice- Performance equivilent to LinuxI've had a look at Linux, but it doesn't support my target CPU, and the codebase is too large.

author: legacy
author_rank: Super Contributor
timestamp: June 19, 2014, 11:52:33 pm
content: Quote from: miguelvp on June 19, 2014, 05:41:21 pmI have seen it, it's too much complex for me =PI have Spartan3e-500 board, with only 500Kgatesthe OR1K is a bit big for such an FPGAI have seen System09, that is 6809 + uart + timer + VDUthat's not so complex, it fits well on my spartan3eit also has a gcc port, but … it is CISC 8bit

author: legacy
author_rank: Super Contributor
timestamp: June 20, 2014, 12:07:28 am
content: Quote from: hamster_nz on June 19, 2014, 11:51:44 pmI am skilled about C and asm (m68k, mips, arm)but i have no resources/time to look at big projectsi am trying to plan activities for my free time, and i have fixed slots of free timesomething like 10 hours/week,plus sometimes an extra during weekendQuote from: hamster_nz on June 19, 2014, 11:51:44 pmyes, i know C, i do not know ADAbut i know pascaland i wrote a bare board interpreter which looks like pascalobviously it's a toy, an homework, but it's funQuote from: hamster_nz on June 19, 2014, 11:51:44 pmnot interested about this, i have put ucOS/2 on an LXP ARM nodethat's for a job task, it has taken me a lot of time, but i had fun(also, the most important things, i was payed for it) so it's fine "that's all folks"Quote from: hamster_nz on June 19, 2014, 11:51:44 pmwell, a bit of C code may be ported from/to my other projectsi hope the 20% at leastQuote from: hamster_nz on June 19, 2014, 11:51:44 pmnot requiredQuote from: hamster_nz on June 19, 2014, 11:51:44 pmRTOS ? nahh, i already had fun with ucos/2 and VxWorks at job(writing drivers and helping other to fix things)i do not want to see any RTOS in my hobby free timeQuote from: hamster_nz on June 19, 2014, 11:51:44 pmi got a Raspberry for it, i do not need anything else, and i do not want to put linux to anything elsemy laptop has already gentoo on, i am already fine with linuxQuote from: hamster_nz on June 19, 2014, 11:51:44 pm

author: miguelvp
author_rank: Super Contributor
timestamp: June 20, 2014, 12:30:24 am
content: Just leaving this here since you didn't reply about the arm soft core:http://www.arm.com/support/university/ip/index.phpA student's report using this:http://web.fi.uba.ar/~pmartos/publicaciones/SPL2011_Cortex-M0ImplementationOnAXilinxFPGA.pdfARMs version of that paper (about the same but not sure which one is the final version)http://www.arm.com/files/pdf/SASE2011_ImplementingTheCortexM0DesignStartProcessorInALowEndFPGA.pdfStill your best bet would be one of those combined FPGA/SoC chips that at least Altera is producing (as linked on my previous post), not sure about Xilinx.

author: legacy
author_rank: Super Contributor
timestamp: June 20, 2014, 12:11:09 pm
content: yes, ARM is RISC, it is 32bit machine, it is great for my purpose !i have only Xilinx chip/devboards, so i will look for FPGA/SoC knocking at Xilinx's doorsgreat, thank you for the ARM link!

author: joelby
author_rank: Frequent Contributor
timestamp: June 21, 2014, 01:48:49 am
content: Andrew Zonenberg has written a MIPS-1 compatible core:https://code.google.com/p/utica-softcore/. He's also working on an updated version (apparently not yet released to the public) that can be targeted with mips-linux-gnu GCC - perhaps this one can too? Verilog, though.

author: Rory
author_rank: Frequent Contributor
timestamp: June 21, 2014, 02:12:34 am
content: I'm surprised no-one has mentioned the Cypress PSoC.

author: nctnico
author_rank: Super Contributor
timestamp: June 21, 2014, 06:32:46 am
content: If you are using a Xilinx FPGA you can use ISE which has support for Verilog. I'm currently working on a project which uses the Lattice Mico32 core which is written in Verilog.

author: legacy
author_rank: Super Contributor
timestamp: June 21, 2014, 10:29:52 am
content: Quote from: Rory on June 21, 2014, 02:12:34 amtell me more

author: legacy
author_rank: Super Contributor
timestamp: June 21, 2014, 10:31:25 am
content: Quote from: joelby on June 21, 2014, 01:48:49 amamazing, i have written a bit of MIPS-1 code (40% in assembly) so it could be fun

author: legacy
author_rank: Super Contributor
timestamp: June 21, 2014, 10:35:31 am
content: Quote from: nctnico on June 21, 2014, 06:32:46 amNever used it, i am curious. Have you got a minimal working SoC ?About Verilog, yes, ISE can handled it, but … my Tina HDL license is for VHDL onlyi am used to study HDL with TINA HDL plus VHDL Studioconsider that i am skilled about C/Asm but i am a quite new about HDLand that's my hobby's purpose: something to aim for, having fun

author: Codemonkey
author_rank: Regular Contributor
timestamp: June 21, 2014, 10:59:11 am
content: Why restrict yourself to whatever Tina can support ? Why not just use for example Quartus from Altera and use the free copy of Modelsim that they provide ? You can use whatever language you want then.

author: Rory
author_rank: Frequent Contributor
timestamp: June 21, 2014, 05:44:17 pm
content: Quote from: legacy on June 21, 2014, 10:29:52 amThis is what I'm playing with right now:Cypress PSoC 5LP series:http://www.cypress.com/psoc5lp/

author: nctnico
author_rank: Super Contributor
timestamp: June 21, 2014, 07:05:43 pm
content: Quote from: legacy on June 21, 2014, 10:35:31 amYes. I have UART, SPI, I2C and GPIO. But there are many more modules available. It is steep climb though fully understand how to connect everything using the Wishbone bus using crossbars.

author: legacy
author_rank: Super Contributor
timestamp: June 22, 2014, 03:21:52 pm
content: Quote from: nctnico on June 21, 2014, 07:05:43 pmyeah, the crossbar instead of the classical bus (used in ASIC CPU system), very amazing idea!]which project, in particular, are you talking about ? I mean any public repo available ?

author: nctnico
author_rank: Super Contributor
timestamp: June 22, 2014, 04:29:05 pm
content: The project I have been working on is based on this open source project from CERN:http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core

author: legacy
author_rank: Super Contributor
timestamp: June 23, 2014, 03:03:49 pm
content: very very nice, i like it a lot, thank you for the link =)