Simple PCB review - Page 1
Forum section: electronics / beginners

author: Saimoun
author_rank: Frequent Contributor
timestamp: January 02, 2021, 09:35:05 pm
content: HiHappy New Year everybody!I hope this is ok - I'm not sure if a lot of people ask for this but I'd love to have some feedback on my PCB designhttps://oshwlab.com/ToneArtSound/prototypeThank you!Simon

author: tarun172
author_rank: Regular Contributor
timestamp: January 03, 2021, 05:07:15 pm
content: Couple of comments,1. Did you run a DFM check? I can see some silkscreen and trace violations.2. I also see you used necking technique for a trace closer to R16. Can you explain?3. Are all footprint per IPC?4. Consider 4 layer board vs 2 layer board.5. I see you added a lot of test points. That is good. Consider labelling key test points using silkscreen.Regards,Tarun S

author: Saimoun
author_rank: Frequent Contributor
timestamp: January 03, 2021, 08:47:42 pm
content: Thank you for the reply Tarun!1. no, only a DRC check. I did not know about DFM thanks for the tip - investigating it now2. yes that is to avoid tumbstoning on the small 0402 resistors, so I reduce the large traces coming in to 12 mil (which is my "standard" trace width).3. I am using EasyEDA, which is in tight collaboration with JLCPCB and LCSC, all the footprints are coming directly from their library. Not sure if they follow the IPC standards though, and I do intend of having the PCB made and assembled (later) by other companies than JLCPCB.4. Fair point, but in this case I doubt it is necessary - you can see I am barely using the bottom layer5. ok

author: S. Petrukhin
author_rank: Super Contributor
timestamp: January 03, 2021, 09:13:00 pm
content: Why are a large number of vias randomly scattered?

author: ucanel
author_rank: Regular Contributor
timestamp: January 03, 2021, 09:20:03 pm
content: If it works it is good but if you want next level:If not necessary do not use that much vias.If possible use same size vias.If possible use same component size.If it is possible do not use smaller than 0805.If possible do not squeeze your components togethermake a room and it could be possible to hand solder them,you may need to do some changes so it may became handy.Some of your tracks are going in to holes with weird angles.Some of your pads tracks and holes are so close to each other there are room for not to do that.You may add more symmetry to thecomponent placement, tracks, vias etc. that is not a must but everyone know what it is

author: Syntax Error
author_rank: Frequent Contributor
timestamp: January 03, 2021, 09:29:50 pm
content: Nice design. Some thoughts.I agree with the other guys, you've a lot of vias swarming around the component ground pins. Remember, ground pins are usually plated through (like a big via) and connect to the copper ground plane.The track out of pin-2-U7 makes an odd curve?For design consistency, add a fiducial marker on the edge. Just in case your board is ever seen by a pick-and-place machine.And pehaps add some other silk layer decals, such as the CE, RoHS and WEEE logos? And your projects domain name.

author: Saimoun
author_rank: Frequent Contributor
timestamp: January 04, 2021, 12:34:24 pm
content: Thank you all for your replies this is very helpfulI was hoping to get some comments on the vias - my thoughts were:* I generally read everywhere that the more vias the better - hence having vias scattered through the whole board--> in the "unimportant" areas they are more or less 150mil apart--> I added (loads) more next to the ground pads/pins* I know ground pins are like one big via - but it's only one via though, so I thought I'll add more* I only have 2 sizes, 12/24 mil and 18/32 mil (hole/plating)And actually I also added an extra via on the +3V3 track, just below R38, since this is the source current for U7 which is the 7seg display driver.Anyways I get the idea I think - please tell me if I am wrong but I think these are still valid, I just maybe went a bit overboardOn another subject, I really put a lot of thoughts into the GND paths, and made sure I had a direct connection on the top layer when I could - that is why some of the tracks are slightly moved from their "ideal" position.For example the track going to pin-3-U7 goes to the bottom plane instead of going directly so that the pin-4-U7 (which is GND) has a direct connection to the bypass caps.Same story with the track going into pin-8-U1, it is to have a better GND connection from U3 (LDO) to the bypass caps and to the MCU's ground.And @Syntax Error the odd curve on pin-2-U7, is to be able to put some vias on both sides of pin-4-U7 (gnd pin as mentioned above).Again I appreciate any comment, and I know I have not given so much information about the board generally, so mainly I was posting in case there was something that hit the eye (like the vias)

author: Saimoun
author_rank: Frequent Contributor
timestamp: January 04, 2021, 02:30:12 pm
content: And @Syntax Error I forgot to answer about fiducial markers - JLCPCB explicitely says not to add them they will do it themselves, and I'm hoping that if I end up manufacturing the board in large quantities somewhere else they will take care of that tooSame with tooling holes.

author: S. Petrukhin
author_rank: Super Contributor
timestamp: January 04, 2021, 05:52:37 pm
content: There is a special tool for placing vias - it does it more smoothly.