Low power 24bit ADC project - Page 1
Forum section: electronics / projects

author: davegravy
author_rank: Regular Contributor
timestamp: February 12, 2022, 05:36:48 pm
content: My end goal is for a very low power sound level logging device with precision and dynamic range comparable to industry standards for sound level meters. My requirements for SNR I think can be pretty relaxed (really something like 30dB should be fine), much more important will be dynamic range. For now I'm focused on the ADC component and later will work on the mic and interface circuitry.I started out initially planning to use the LTC2500-32 (threadhere) but abandoned this for the LTC2512-24 since it has a similar integrated decimation filter and I decided I really only need about 18-19 ENOB.First prototype is assembled and connected to my NUCLEO-U5 (STM32) board via SPI and I started getting my first sample readings out of it recently. This was way more work than I expected but an interesting learning experience in microcontrollers, DMA, TIMs etc.Attaching some of the design files.I based the design fairly closely on theevaluation board design, using the same low-noise power supplies for VDD and +3.3V. I used a slightly noisier but lower current power supply for +5V VRef.I don't have the analog driver input circuit assembled yet as I'm still waiting for parts, so the ADC inputs are just floating currently, but the design at least uses the same LTC6363 low noise differential op amp as the eval board, and a similar matched resistor network IC.For ADC clock I went with thiscrystal oscillator ICat 8.192MHz, run through a decade clock divider to give a 819.2kHz MCLK to the ADC. I prioritized low power for this part since as I understand high phase noise will impact SNR but not dynamic range. This unit had the best phase noise in its power class, I'm not sure how it compares to using a clock generated straight from STM32U5.For now I am running tests by using short lengths of hookup wire to jumper the analog IN+ and IN- to GND or VREF or feeding these inputs from a function generator to observe performance.The first head-scratcher is that there seems to be quite an offset voltage. A 2.50V (half of VREF which is 5V) input should give a 0 code but I seem to need an input of 2.32V to achieve this. 180mV offset error seems like a lot. I confirmed VREF is 5.00V and the VREF supply is about as close to the ADC chip as it could physically be so I can't imagine there's 360mV loss from trace resistance.Any ideas?With the inputs floating the (AC coupled) noise floor is about -87dBFS (about 110uV RMS) which isn't very good but hopefully will improve once they're terminated.Thoughts on the design/project in general?

author: Kleinstein
author_rank: Super Contributor
timestamp: February 12, 2022, 08:15:39 pm
content: I would be a bis suspicious with a 3.3 V supply to the ADC and a 5 V reference. Most chips don't like a votlage higher than the supply.The ADC has differential input and thus zero would be with both inputs at the same voltage. The point of getting half the signal range would be more a question about an gain error.The performance with floating inputs does not really matter. Chances are one would pic up lots of hum and also get signal from charge injection at the input. The more realistic test is with shorted inputs.The clock from the STM32 would habe a bit more jitter. How much depends on the PLL. Ideally there would be no PLL and than likely resonable low jitter. A integer PLL multiplier ratio could also still be OK, if the supply to the µC is clean.

author: davegravy
author_rank: Regular Contributor
timestamp: February 12, 2022, 08:49:54 pm
content: Quote from: Kleinstein on February 12, 2022, 08:15:39 pmI took another look through the datasheet and don't see any constraints about this mentioned. If I'm not mistaken the eval board offers VREF up to 5V, OVDD switchable with a jumper between 2.5V and 3.3V, and VDD fixed at 2.5V. If none of the supplies are able to exceed VREF is it not safe to assume it's designed to operate this way?Quote from: Kleinstein on February 12, 2022, 08:15:39 pmYes you're right. I need to carefully control each input independently and take measurements this way. Bridging the two input pins with the end of a wire (but the pair still floats) I get a non-zero code, about +150,000 (decimal).

author: Kleinstein
author_rank: Super Contributor
timestamp: February 12, 2022, 09:52:32 pm
content: The data-sheet has specs and typical curves for 5 V ref and 2.5 V supply. So this should be OK. They may actually some of the circuitry from the ref. For some reason the ref input takes quite some current.The floating common mode voltage may still not be that good. With internal charge pumping it may even drift out of the common mode range.

author: davegravy
author_rank: Regular Contributor
timestamp: February 13, 2022, 01:57:18 am
content: OK, I think something is definitely wrong.IN+ 2.500V, IN- 2.5V00 => 261E3IN+ 2.342V, IN- 2.500V => 0IN+ 5.00V, IN- 0.00V => 4.4E6IN+ 0.00V, IN- 5.00V => -3.8E6The most revealing thing was that keeping IN+ fixed and making a big sudden (step) adjustments to IN- made no difference to the ADC output, except for a very brief transient (single sample or two). See attached screen capture resulting from IN- stepping from 0V to 5V (x axis is sample #).So it seems the IN- pin is stuck to around 2.34V. Any guesses what might cause this? Bad solder joint? Overheated IC during reflow soldering?Any suggestions for how to troubleshoot this?

author: Marco
author_rank: Super Contributor
timestamp: February 13, 2022, 02:18:22 am
content: What does the IN- pin measure with a multimeter?

author: davegravy
author_rank: Regular Contributor
timestamp: February 13, 2022, 02:24:34 am
content: Quote from: Marco on February 13, 2022, 02:18:22 amWell I can easily measure a test point on the PCB that's (supposed to be) connected to the pin, but that gives expected voltages. To measure the pin itself may be tricky. It's a DFN package and 0.5mm pitch, my multimeter probes are far to blunt to get a read. I may have to fashion a probe out of something very thin and pointy.

author: jmelson
author_rank: Super Contributor
timestamp: February 13, 2022, 02:47:50 am
content: I have some "tip jacks" that fit on the probe tips. I solder sewing needles to the end of the jacks, so I can snap them onto the ends of the probes. These work well for probing tiny leads and pads.Jon

author: davegravy
author_rank: Regular Contributor
timestamp: February 13, 2022, 02:57:36 am
content: Quote from: jmelson on February 13, 2022, 02:47:50 amHad a similar idea and just soldered a wire to a sewing needle and alligator clipped to my probe. I'll have to look into these "tip jacks" and fashion something better for next time.Anyways I think while probing I may have bridged the pad and the pin because I saw a sustained -8.31E6 code for a few seconds on my monitor. Not quite -8.388E6 but hey, we're in the ballpark now.Haven't done much PCB rework but my first inclination is to put a tiny bit of solder paste close as I can to that pin and run the hot air station over it. Seems like something I'd end up fighting with if I tried with an iron.

author: davegravy
author_rank: Regular Contributor
timestamp: February 13, 2022, 04:15:49 am
content: Alright, well that wasn't so bad. Added some paste and hot air and things look much better now.With inputs shorted and held at 3V, taking an RMS of the codes I now get 10 which I believe translates to a dynamic range of 115.4dB. This is with downsampling of 32x, and the datasheet claimed performance in this configuration is 117dB. I'm happy with that!I expect noise will be dominated by the analog driver and I'll drop some DR when I add it, but this is a good starting point.One thing I need to wrap my head around is that I still don't quite get the full range with 0V,5V inputs. I hit the threshold of clipping if I input 0V, 5.042V or -0.042V, 5V.

author: davegravy
author_rank: Regular Contributor
timestamp: February 25, 2022, 01:33:04 am
content: OK so I think I goofed on my power calculation. I expected I'd designed a circuit that should consume roughly 50mW but having built and measured it, it's over 3x that: 160mW.Having combed through the datasheets I clearly misunderstood the LTC6363 power calc and also the regulator's dependence on load current.I'm curious to know how people would approach cutting down the power consumption. Here is the breakdown of my design based on datasheets:ADC driver (LTC6363): 71.0mW2.5V Regulator (LT1763-2.5): 34.7mWADC (LTC2512-24): 23.7mW6.2V Regulator (LT1763): 14.3mWMaster Clock (ECS-2520MVLC): 5.9mW5V VREF (ADR4550): 5.6mW3.3V Regulator (LT1763-3.3): 3.7mWThe measured dynamic range is beyond what I really need: 115dB, whereas I can live with 105-110. I suspect the LTC6363 is overkill in terms of performance as it has a pretty high GBP for this which is an audio frequency application. I'm eyeing alternatives for the ADC driver, like a pair ofADA4084s that hopefully can bring down the power a bit.I figure I can half the clock rate of the ADC to save about 25mW (10mW from the ADC, 15mW from the 2.5V regulator which supplies it). I can reduce the decimation factor from 16x to 8x so my sample rate remains unchanged, only sacrificing a few dB of dynamic range.It's only 6mW but I'm not sure I really need the crystal oscillator since I could generate the clock from my MCU. I went with the external oscillator since it had decent seeming phase noise, but I really don't have tight SNR requirements... only dynamic range.I'm a little unsure what to do with the power section - for this prototype I am supplying all the regulators from my bench bipolar supply: +7.4V and -2V, but the next revision I'd like to power from a Li battery and adjust the power section accordingly. I'll need to generate a negative rail somehow, and I'll need to step up from the Li cell voltage to get a +6.2V, +5V and +3.3V rail. Should I step up only to supply these regulators and run +2.5V and the -1.2V regulation direct from the battery?Any suggestions/comments are welcome.

author: oz2cpu
author_rank: Frequent Contributor
timestamp: February 25, 2022, 08:39:34 am
content: your ADC looks very interesting, LTC2512 but is not available anywhereso by that, not a good idea for a new design ??

author: davegravy
author_rank: Regular Contributor
timestamp: February 25, 2022, 01:30:29 pm
content: Quote from: oz2cpu on February 25, 2022, 08:39:34 amYes it was available when I started months ago but is not anymore. I bought a few units to prototype with. It's not a commercial project (yet) just a fun learning project so I'm ok building only a few.

author: moffy
author_rank: Super Contributor
timestamp: February 25, 2022, 11:38:34 pm
content: Mouser has 9, LTC1512's available, as of this time, so it looks like they are trickling out.

author: davegravy
author_rank: Regular Contributor
timestamp: February 26, 2022, 12:47:26 am
content: OK I'm backtracking on my earlier statement. The LTC6363 should be closer to 14mW in my design than the 70mW I mentioned in my recent post. This is based on LTSpice modelling (model attached).I think the datasheet dissipation calc assums the load resistor is connected to ground, whereas in my case there's a filter capacitor blocking current. If the load current to the LTC6363 is that much lower, the losses from the LT1763 regulator serving it should also be considerably lower.Adjusting for both these I'm now trying to account for about 70mW of the 160mW I measured.I tried some experiments:I slowly lowered the voltage on my +ive bench supply and watched the current. It stayed constant at ~20mA until I got to about 3V at which point it ramped down fairly linearly with voltage.With +ive supply back at 7.4V I disconnected the -ive supply and watched the +ive supply current drop sharply from 20mA to 16mA.I'm not sure if either of these point to what is dominating the power consumption.I did take some temperature measurements of all the ICs with my IR gun and the +6.2V LT1763 was ever so slightly warmer than everything else.

author: davegravy
author_rank: Regular Contributor
timestamp: February 26, 2022, 01:27:53 am
content: In hindsight I should have added jumpers to switch power to ICs for on/off power testing. Next time.I accidently left the SHDN pin unconnected on the oscillator so I was able to turn off MCLK which dropped the current on the 7.4V rail by 11mA. So 80mW is shared between the clock circuitry and the ADC (and losses from the regs feeding them). The clock circuitry should be negligible, but from the datasheet, at a clock rate of 800KSPS the ADC should only draw ~25mW. So I'm at a loss how to account for this.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 26, 2022, 09:47:29 am
content: The regulators used are linear regulators and thus the calculation is better done with the current. If the chips takes current from a low voltage this also causes the power loss in the regultators.The LT6363 is supposed to need some 1.7 mA. With a significant voltage at the input there would also be additional current though the feedback resistors.The power for the LT2512 seems to be calculated for 2.5 V supply and possibly also 2.5 reference. A 3.3 supply and 5 V ref would increase the supply current. Removing the clock from the ADC would essentially shut down the ADC and reduce the ADC supply current to near zero.The 25 mW for the ADC at 800 kSPS would be some 10 mA at 2.5 V and still 10 mA at 7.4 V.

author: davegravy
author_rank: Regular Contributor
timestamp: February 26, 2022, 02:38:49 pm
content: Quote from: Kleinstein on February 26, 2022, 09:47:29 amThanks Kleinstein. From the LT1763 regulator datasheet is a formula for worst-case power dissipation:QuoteThis is what I've been using to estimate the losses in the regulators. The GND pin currents are very small for the scenarios I have so the 1st term dominates. The biggest power draw is the 2.5V supply because the ADC's VDD draws considerable current (7mA) and 2.5V is considerably less than the main supply (7.5V).I think this is the same as you're saying, but just checking. An improvement would be to connect the 2.5V regulator directly to a Li battery terminals (3.7V nominal) since then the (Vin-Vout) term would be much lower, right?Quote from: Kleinstein on February 26, 2022, 09:47:29 am1.7mA @ 7.5V is only 12.75mW, and unless I'm not understanding something the losses from the feedback and input resistors should be negligible since I chose 10kOhm values for them.Quote from: Kleinstein on February 26, 2022, 09:47:29 amFor the LT2512-24 I calculated like this:P(VDD): 7mA @ 2.5V = 17.5mWP(OVDD): 0.8mA @ 3.3V = 2.6mWP(REF): 0.8mA @ 5V = 4mWI think I'm going to try desoldering the LT6363 today to confirm its impact on power consumption.

author: davegravy
author_rank: Regular Contributor
timestamp: February 26, 2022, 11:07:32 pm
content: In preparation for desoldering the LT6363 I re-measured current coming from my bench supply and was confused to measure only 100mW - what had been 160mW (21mA @ 7.5V) yesterday. The only difference I think was that my MCU (Nucleo board) was connected via the various header pins today.I disconnected the MCU and I saw the current start to wander - over about a minute it climbed to 21mA. Touching the header pins with my fingers the current started to wander wildly from 13mA to 21mA. I grounded all the pins that are ADC inputs (SCKA, SCKB, SEL0, SEL1, RDLA, RDLB) and the current stabilized at 13.2mA.I'm not sure why, none of the levels of these pins should have any bearing on power consumption.

author: davegravy
author_rank: Regular Contributor
timestamp: February 27, 2022, 12:14:28 am
content: Next problem.The prototype seems to have a good noise floor as long as there's no interference sources near it. Look what happens when I place my cellphone about 5cm away from the PCB (about 5 seconds into the video):https://youtu.be/jYUJAb9frMoThe Y axis is volts, there's a peak over 1mV! This is with the input grounded.Questions/thoughts:My prototype is connected to the MCU by ~20cm long dupont wires. Should I be concerned with this? I can likely shorten them a bit if it's likely to help but to really shorten them I'd need to put the MCU on the PCB with the ADC (spin a new board revision)It would be good to rule out sections of the design as sources of susceptibility. I can easily disconnect the analog front-end circuitry from the ADC by desoldering a couple of resistors (R25 and R26). If the problem vanishes after this then I should focus on the analog circuitry.My board layout has some ground plane stitching - does it look dense enough? I didn't do any fencing around analog traces, should I have?I have some ground "islands" on the top layer with only one via. Are these likely to be a big problem and how can I confirm if they are?Any ides what could be a problem with my design, or how to troubleshoot? I'm attaching my Eagle files since I expect PCB layout could be a problem.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 27, 2022, 09:13:30 am
content: With CMOS inputs an intermediate votlage level can cause quite some extra supply current (up to the 10s of mA). So CMOS input should not be left open. Even just a logic level at the low end (e.g. 3 V to a 74HCT... powered with 5V) can increase the supply current.The layout would mainly effect EMI and maybe DC precision. It would need to be really bad to see an effect in the supply current. Also audio band noise should not be effected that much. One should still keep an eye on EMI.A single via to a ground island should normally be enough, unless the island is really large.For the board is could help to also show the layout / schematics in a common readable format (e.g. PDF or PNG).

author: davegravy
author_rank: Regular Contributor
timestamp: February 27, 2022, 04:42:54 pm
content: I think I understand the power consumption now. It's not as good as I want but I now know how to improve it next iteration.I'm still unsure about EMI, it's an issue because I want to add a cellular module to the project in the future and need the ADC to be immune from transmissions in these frequency ranges.Attached are .PNGs of the board layers. A PDF of the schematic is in my first post on this thread (note that I have now assembled the full board so disregard the yellow square).Are there any problems with this layout that might cause EMI susceptibility?FWIW the interference disappears when the phone is on airplane mode, so it's not from switching regulators or other RF sources in the phone.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 27, 2022, 07:15:28 pm
content: The board itself looks OK, as far as I can see. However there are a lot of in and out connections and these have little filtering. So the cabeling can have quite some effect. Especially the µC part can carry quite some RF signal from the RF module. Some common mode filtering could help there, but it would be a bit tricky with so many lines.

author: davegravy
author_rank: Regular Contributor
timestamp: February 27, 2022, 07:31:29 pm
content: Quote from: Kleinstein on February 27, 2022, 07:15:28 pmThanks for reviewing.Your note about cabling is interesting as I had just discovered that placing my phone adjacent the power leads from the bench supply to the PCB causes similar levels of noise. Ferrite beads on the supply lines could possibly help then?It sounds like co-locating the MCU on the board may also help resolve this.I tried ON/OFF testing with the various radios on my phone and it seems turning off bluetooth makes the biggest improvement, followed by LTE, with Wifi having no apparent impact. With all 3 disabled there was still some noise, so some radio is not easily disable-able without airplane mode on my phone.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 27, 2022, 08:55:16 pm
content: Ferrites one the lines going in and out can help. In some cases it can happen that ferrites can also make things worse. If not made really good, EMI can be a bit unpredictable - it may or may not help, depending on the exact frequency.Usually bluetooth is rather low power, and a mobile phone is way higher power. So the phone is normally the more tricky part.Having the µC on the same PCB would definitely help, though direct connectors may also be OK. From what I have seen in the schematics, there is not mach absorbtion in the 3.3. V rail. Ideally the clock would have additional filtering in the supply (Ferrite and/or a resistors in 10 ohms range).For lowerst power it would more likely be the µC clock anyway and usually no extra divider. Clock jister should not be that critical for this application.

author: davegravy
author_rank: Regular Contributor
timestamp: February 27, 2022, 11:38:29 pm
content: Quote from: Kleinstein on February 27, 2022, 08:55:16 pmSo probably I should plan some pads for ferrite beads on all the lines in/out as well as IC supply pins on the next revision. If I don't need them I can always replace with 0ohm resistors.Something likehttps://www.murata.com/en-us/api/pdfdownloadapi?cate=cgsubChipFerriBead&partno=BLM15GG471SN1%23looks like it's fairly broadband around 2100Ghz which is my LTE band. Even 700Mhz and 2.4Ghz have reasonably high impedance.Maybe I'll add a shield as well.I read that lower valued decoupling capacitors on IC supply pins, in parallel with the usual values can help with EMI. Is there some truth to this?

author: Kleinstein
author_rank: Super Contributor
timestamp: February 28, 2022, 09:21:48 am
content: The combination of multiple cap for decoupling is a tricky topic. A main reason for using low value caps was the physical size: for the very high frequencies 1 nF close by helps more than 100 nF further away. However modern MLCCs got quite small and even 100 nF can be rather close to the chip. Another point is that 2 capacitors in paraellel can form a resonant circuit and this way increse the impedance at some frequencies. So it would be definitely a good idea to also have some lossy elements (e.g. series resistors / ferrites / electrolytic caps). I personally like to have also low value (e.g. 10 ohms) series resistors in the supplies to dampen possible resonances on the supplies and also have a defined series impedance in the filtering function of the decoupling. For higher current a ferrite and parallel resistor can be an option.I don't think that the power supply decoupling is effecting the sensitivity to external EMI very much. This is more a point effecting emissions.The RF interference from a phone signal is more through the inputs.To some degree the supply decoupling may also effect the linearity of the ADC, but I don't think this is a major concern here.

author: mawyatt
author_rank: Super Contributor
timestamp: February 28, 2022, 04:07:55 pm
content: A very simple "thought experiment" that can help with supply decoupling:1) If you stand on the chip and "look" to the supply input you should "see" a low impedance at all frequencies of interest (>10X max clock frequency). You want the chip to be able to pull as much current as needed right from the supply pin, thus good local decoupling @ frequency is required.2) If you stand on the power supply and "look" to the load you should "see" a moderate impedance, especially true for a switchmode supply. You don't want the supply dumping lots of dynamic current into the load if possible, this causes high dynamic fields and dynamic IR drops which wreak havoc with sensitive circuits. When the supply "sees" a moderate load impedance, this limits the dynamic currents and mitigates these dynamic effects.So what does this mean?1) The chip should have good close by (physically & electrically) decoupling. Example, small ceramic SMD cap close to chip, and larger SMD cap within a few mm. If RF/MW signals are involved, the close in SMD should be 0402 or 0603 ~100pF, and other SMD cap 0603 or 0805 ~1000pF, for other applications usually a 0603 or 0805 1000pF ~ 0.01uF close in and further away a 0805 or 1206 0.1uF ~ 10uF suffices.2) If the load can handle a small voltage drop usually a series resistive PS input works well, otherwise an inductive input is required. Ferrite beads help for higher frequencies and are lossy (good), but have limited inductive reactance, whereas surface mount inductors can offer higher inductances. Using beads, series inductance and even series resistance together are often employed where sensitive circuits are involved (especially with SMPS).For low frequency ripple (mains 100/120Hz) are usually best handled with larger electrolytic capacitors which service all the chip loads on the PCB.Best,