PCB stacking - Page 1
Forum section: electronics / beginners

author: sdouble
author_rank: Frequent Contributor
timestamp: July 04, 2014, 08:59:08 pm
content: Here is a most probably simple question.I need to design very high gain charge sensitive preamplifiers.My question is about the PCB material itself . I'm rather sensitive to parasitics caps in that design and try to minimize them in my next production.I have a 4 layers PCB : all components on the top layer , them ground plane and power planes.I moved from a basic fr4 to Rogers 4003c. In the mean time the spacibg between the 1st and the sexond layer got reduced. from 2 layers of prepreg 7628 (ie 0.35 mm in total) to 1 layer of 0.2 mm of ro4003c.my limited knowledge tends to make me suppose that i gonna be in a worse situation (with respect to parasitic cap) with the ro4003c due to the thinner material.Any suggestion ?thanks in advance.Ju

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 05, 2014, 12:40:25 am
content: Not necessarily. I have no idea what your layout looks like.Why not cut out ground planes under sensitive nodes, and bootstrap the input so it doesn't matter?Tim

author: sdouble
author_rank: Frequent Contributor
timestamp: July 05, 2014, 05:07:49 am
content: Dear Tim,I have a sensitive loop which is pretty long. I didn't consider cutting out ground/power planes under the full loop. The use of a ground plane would not make sense any more I guess.This board is rather sensitive to e.m perturbations. I'm sensing signal of 1000 to 5000 electrons.cheers

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 05, 2014, 05:31:54 am
content: That's quite sensitive.Try to miniaturize it as best you can (0402 or even smaller size SMT components?), and put the whole thing inside a solid metal shield.Tim

author: sdouble
author_rank: Frequent Contributor
timestamp: July 05, 2014, 07:03:26 am
content: 0603 is what i'm using for all passive but decoupling/filtering caps. SOT23 for the active elements

author: Neilm
author_rank: Super Contributor
timestamp: July 05, 2014, 05:17:20 pm
content: At the levels you are talking about, the conductivity of the FR4 could have significant effects as well. Ensure that all sensitive tracks are guarded properly - I have seen surface leakage on PCBs cause issues with sensitive measurements. (Once bitten..)

author: sdouble
author_rank: Frequent Contributor
timestamp: July 05, 2014, 11:39:29 pm
content: As I mentioned, i'm quitting the FR4 to go for Ro 4003c.My basic idea was to reduce the parasitic capacitance.My main question was :I'm moving from 2 layers of prepreg (2 x 0.170 mm) to 1 layer of Ro 4003c (0.2 mm) between the upper layer to the ground plane.I was not sure that this was the best choice.Coud you comment on : "all sensitive tracks are guarded properly" ?

author: matkar
author_rank: Regular Contributor
timestamp: July 06, 2014, 07:18:24 am
content: Quote from: sdouble on July 05, 2014, 11:39:29 pmLook at an example on the attached picture. You will notice a tin plated track going around some pins. Its purpose is to prevent leakage to the high impedance net from the surrounding nets by connecting the guard track to ground.

author: sdouble
author_rank: Frequent Contributor
timestamp: July 06, 2014, 07:44:01 am
content: oops, this i didn't do.Btw, my pcbs look better than that one

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 06, 2014, 07:45:38 am
content: Depending on bandwidth and leakage, such measures (and also the Rogers laminate, and so on) may not may not be useful.Tim

author: sdouble
author_rank: Frequent Contributor
timestamp: July 06, 2014, 07:58:21 am
content: We are dealing with relatively low bandwidth here. The signal rise time is 25 ns.i have a bandpass filter around 5 MHz to reduce noise. I know that working at lower frequency would help but i need to cope with pile-up meaning that i need that short shaping time.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 06, 2014, 12:04:36 pm
content: If bandwidth is relatively narrow, neither capacitance nor leakage should have any effect; set it up as an RF bridge, or amplifier, or something like that.Tim

author: sdouble
author_rank: Frequent Contributor
timestamp: July 06, 2014, 02:26:23 pm
content: my charge sensitive amplifier is basically an integrator with a j-fet as a 1st stage. the cap in the feedback loop is only 0.3 pf meaning that all parasitic cap play a very significant role.