Replacing two 32k EPROM with one 64k  - Page 1
Forum section: electronics / beginners

author: Mp3
author_rank: Frequent Contributor
timestamp: March 06, 2021, 10:19:07 am
content: I've been looking into the easiest way to adapt a re-programmable 64k x 8 EEPROM in place of two 32k x 8 EPROM, so I can reprogram the chip many times with different versions of code. My plan is to put the lower bit EPROM code in the lower 32k and the upper bit EPROM code in the upper 32k.If i'm not mistaken, I could put a 28C512 (so i can easily reprogram it) in the socket for the lower bit EPROM, attach a pair of diodes to the CE pin, then connect each diode to the CE socket on both chip sockets, and then what I believe is a ground wire for the empty socket. Then I think it should be able to access the upper 32kb via the upper EPROM socket.I hope i'm not completely off base, I've been trying to see how some others approached a similar task and ended up trying to figure out what was being done here. It seems to me both these projects are aimed towards the same ultimate goal I am looking to accomplish:http://bitchin100.com/wiki/index.php?title=M100ROMhttp://www.boobip.com/hardware/64kb-eprom/64kb-eprom-installationI'm not looking to do bank switching, just to consolidate the whole system program into one physical chip so it's less effort for me to pop it out and test some new code.I apologize, I've done as much research as I can on this laptop charge. I won't be able to keep researching on this until tomorrow.

author: retiredfeline
author_rank: Frequent Contributor
timestamp: March 06, 2021, 12:23:40 pm
content: Some details of where you intend to install this, and a schematic of your proposed modification would be helpful. It's also not clear from your description whether the 32k ROMs are mapped in one at a given time, or the two form a total of 64k accessible all the time.The 64k EPROM will have an A15 pin. What do you intend to do with this?

author: CJay
author_rank: Super Contributor
timestamp: March 06, 2021, 01:35:39 pm
content: Should be fine as long as there are enough address lines routed to the chip socket.If not then you'll need to deal with A15 as well as CE, that's VPP on the 32K EPROM so it's likely to be tied high

author: David Hess
author_rank: Super Contributor
timestamp: March 06, 2021, 05:55:43 pm
content: The chip select signals for the 32k EPROMs will need to be combined to make a chip select for the larger EPROM and also decoded into the high address bit although that is easy unless timing margin prevents it.

author: Martian Tech
author_rank: Regular Contributor
timestamp: March 07, 2021, 04:09:48 am
content: Not clear what you mean by Lower and Upper bit EPROM code - Are the current EPROMs configured as 64Kx8 or 32Kx16? If it's the latter, you're going to have problems trying to do what you want.

author: Mp3
author_rank: Frequent Contributor
timestamp: March 07, 2021, 04:58:30 am
content: Thanks all for the help!!Quote from: Martian Tech on March 07, 2021, 04:09:48 amHonestly I'm not 100% sure how the ROMs are configured, and I have the schematics on hand but I'm not smart enough to know how to determine what kind of memory arrangement that indicates. What I do know is only one of the two ROMs is addressed at a time, and on the schematic both the CE and OE pins are tied together on both 32K EPROM.If it's 32Kx16 then I believe I could increase my part count but decrease my overall cost to make this device by using the 64Kx16 93C46B-I/MS which is only 27 cents a piece and interfacing it with a SPI to Parallel adapter and use the top half of each 64K space.... hmm....I thought at first the code was split up into lower bits and upper bits, but now i'm not so sure, since as far as I understand only one of the two EPROMs are utilized at a time, they may not be arranged in a lower/upper configuration.

author: retiredfeline
author_rank: Frequent Contributor
timestamp: March 07, 2021, 05:07:58 am
content: Quote from: Mp3 on March 07, 2021, 04:58:30 amThis probably means that one pair is driven by A15 and the other by ~A15. If the bus is really 8 bits wide.

author: Mp3
author_rank: Frequent Contributor
timestamp: March 07, 2021, 05:43:18 am
content: Quote from: retiredfeline on March 07, 2021, 05:07:58 amCool thank you. The CPU is an 8031, so I can't imagine it being more complex than 8 bits. There are two 2764 EPROMs I haven't determined the purpose of yet. I don't think they're necessary to my project, though. I'll check back in once I have a schematic worked out.

author: wizard69
author_rank: Super Contributor
timestamp: March 07, 2021, 02:59:43 pm
content: Quote from: Mp3 on March 07, 2021, 04:58:30 amIt sounds like this could be a 16 bit wide implementation if so you are going to have a hard time. You apparently have a schematic, this should tell you right away what and how it is interfacing.QuoteWhy bother with this if you don't know the basics about how the circuit works? Your posts are very confusing to be honest. What does SPI have to do with your original question?

author: CJay
author_rank: Super Contributor
timestamp: March 07, 2021, 05:42:43 pm
content: It's an 8031, an 8 bit CPU, highly unlikely to be a 16 bit databus unless there's something the OP isn't telling us.

author: Mp3
author_rank: Frequent Contributor
timestamp: March 07, 2021, 10:03:18 pm
content: Quote from: wizard69 on March 07, 2021, 02:59:43 pmUnfortunately, I've spent some time researching bit addressing but I really have no ideawhatI'm looking for in the schematic. Since it's an 8031 and so old I would be really surprised if it was 16 bit, so I assumed it's 8, but I understand it could also be an 8 bit data bus with a 16 bit address. What I was able to gather from my research is that an 8 bit address bus would only go up to A10 and a 16 bit address bus would go up to A15, so I might be working with a 16 bit address bus.If anyone wants to help me check, please look on page 15 ofthis PDFfor the relevant circuit. (Page 15 of the PDF, the page is marked 13 on the page itself)QuoteI apologize for getting too far ahead of myself.My goal - once I figure out how to split the signals properly so I can use one larger EEPROM instead of two 32K ROMs - is to make a little device with USB connectivity that I can use to reflash the EEPROM with a program I'm writing. Surface mount SPI EEPROM are very cheap and readily available, whereas buying old used parallel EEPROMs would be a lot more costly, subject to availability on the used market, and more importantly wouldn't allow me to finish my project of being easily interfaced with a PC.I figured if I could get a simple 64K ROM tested and working in place of the two original 32K ROMs, then I would know how to break out the signals, and I could go ahead with building my project with an understanding of how the device uses the address lines.I apologize for keeping so many of the details "hushed" but I was worried I'd make the thread too hard to follow if I added all that in initially. I won't have any trouble building the circuit to reprogram the SPI chip and interfacing with USB, but I still don't have a grasp of how or why one could use a single larger ROM in place of two smaller ROMs (and how to properly attach that one ROM to both sockets).(Edit: Fixed quote tags I had broken)

author: retiredfeline
author_rank: Frequent Contributor
timestamp: March 07, 2021, 10:08:31 pm
content: 8031 is a ROM-less 8051 so 8 bit data bus and 16 bit address bus. You can use 8051 documentation. However the lower 8 bits of the address bus are shared with the data bus by multiplexing.A quick glance at page 15 shows that the two EPROMs have ~CS enabled by the same line from the FPGA and are connected to different buses so you probably can't combine them in one EPROM. Why do you want to combine them anyway? Just happen to have a 64kB one in your spares box? Couldn't you use two 32kB EEPROMs or even two 64kB EEPROMs if they are cheaper, by giving up half the capacity?Also it doesn't look like those EPROMs contain code, maybe audio samples or something. The code would be on another EPROM.

author: Mp3
author_rank: Frequent Contributor
timestamp: March 07, 2021, 11:03:40 pm
content: Quote from: retiredfeline on March 07, 2021, 10:08:31 pmThanks again for the help. It was more of a "can I do it" thing than having any practical reason to do it.Yeah I am hoping to replace the contents of those pcm data roms.I'll take some time to throw a schematic together using two distinct EEPROMs and have them wired up like normal.The OS EPROM is its own 32K ROM so it's easy enough to use a suitable EEPROM from my parts bin until I get any modified system code stable.For the sake of me understanding what is going on.....Since they are linked with ~CS, but not on the same bus, then that's how one knows it's not addressed like 32k x 16?

author: retiredfeline
author_rank: Frequent Contributor
timestamp: March 07, 2021, 11:12:33 pm
content: Quote from: Mp3 on March 07, 2021, 11:03:40 pmThey might or might not. Have to work through the schematic.

author: srb1954
author_rank: Super Contributor
timestamp: March 07, 2021, 11:18:53 pm
content: Quote from: Mp3 on March 07, 2021, 10:03:18 pmIt is not very clear from your post which EPROMs you are trying to substitute. It is not helped by the schematic being very poorly laid and incredibly difficult to follow.If you look at the 8031 processor, which is definitely an 8-bit processor, there appears to be only one 32k x 8 EPROM attached to this chip, I6. This is the only EPROM attached to the PSEN line of the 8031 so it constitutes the entire program code for the 8031; none of the other EPROMs contain any of the 8031 program code.The other 32k x 8 EPROMs, I18 and I24, are not attached to the 8031 data bus but must be associated with I9, maybe some sort of DSP chip. If you look closely at the labels on the EPROM data pins they are different between the 2 chips so they are configured in a 32k x 16 configuration and can't be replaced by a single 64k x 8 chip.Regarding the 93C46 chip this is a 64wordby 16 chip with a serial data interface - 1024 times smaller that what you have stated and totally inappropriate to interface to the parallel busses of this design.Finally, you would get much better responses to your queries if you clearly stated at the outset what you are trying to achieve rather than leaving the other forum members having to do detective work figuring out your intentions.

author: Martian Tech
author_rank: Regular Contributor
timestamp: March 08, 2021, 03:23:21 am
content: I'm looking at the block diagram on page 5 of the pdf file. I see in the SYN-57 section "Wave Memory 32KB x 2 ROM" and the outputs of those feed "OSC 1" and "OSC 2" buffer registers, which in turn are fed to their own separate 8-bit DACs. Are these the EPROMs in question? Looking at the data outputs of these in the circuit diagram on page 13, D0-D7 go to different places on each chip (I18 and I24). So if you wanted to replace those two chips with a single chip, you'd have to be able to tie those output lines together. It looks like the addresses presented to both chips is the same (WA0-WA14). Chip select and output enable are connected in parallel for both ROMs, so it does look like they are both being read at once (i.e., it's 32K x 16).Note that the outputs of I24 go to another EPROM, I35, and the outputs of that chip are3 added to the outputs of I18 in the adder chips I25 & I30. Which means beyond a doubt the outputs of I18 and I24 need to be valid at the same time - there's no intermediate latch that would hold one output (say on one clock phase) while waiting for the other output to be generated (say on an alternate clock phase).