PCB Top and Bottom pour - GND and VCC - Page 1
Forum section: electronics / projects

author: elcrni
author_rank: Regular Contributor
timestamp: March 20, 2021, 11:09:35 pm
content: hi guys,I've been working on a custom PCB design for the past few weeks, months long hobby project for decoding and analysing atomic clock radio signal and displaying various data on 7 segment displays. PCB is going to be cca 35x40cm. Now i've been using EAGLE for a couple of years now but nothing of this size and so many MAX7219 ICs, and as i am close to finish the PCB design, i am not sure about the top/bottom pour... so the question is: should i/can i have one layer as GND pour and another as VCC (+5V) and would that be a smart idea... not sure about interference with MAX7219 lines, noise or whatever else, OR should i go with 2x GND layer and then just route the 5V signal where needed (needed on a lot of places on PCB)Is it a usual routine/common practice to have GND and Voltage pours as 2 layers or i should always use GND on both.Most of the components are SMD so there will be lots of vias anyway, which ever way i go on this one.Many thanks for any help,Alek

author: tszaboo
author_rank: Super Contributor
timestamp: March 20, 2021, 11:46:58 pm
content: You can do it either way, it's not going to make too much difference.The usual way to handle this is to use 4 layer boards, with inner planes dedicated to power and ground.Why this is expensive for 1-2 boards, in quantity, this increases PCB price by about 50%, so a 2 EUR board becomes 3 EUR. And it passes EMC testing unlike the 2 layers boards.Just keep in mind that eagle is a terrible software, and it won't give you any warning if you have a pour that's disconnected or hair thin.So route both signals everywhere, with tracks. Then pour it.When I do two layer boards (rarely) I keep most racks on top, and GND fill the bottom and Top. Route VCC with 1mm track. I jump the track to top whenever I can, and try to avoid having long tracks on bottom. So rather have 6 or 8 via in the track than a slit GND plane.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 21, 2021, 03:05:08 am
content: Tl;dr no.You should generally have about half the layers in the design, dedicated to planes. You can use fewer at higher layer counts, when modest crosstalk is not an issue (e.g., most digital comms, but not precision RF).So, for a 4-layer board, since the outer layers have stuff placed on them (assuming a typical mostly-SMT design), you won't get much coverage there, so inner layers it is. And there are two inner layers, so you can do GND and one VCC (divided up between domains however you like).For a 2-layer board, you can only afford one.But it's worse than that, because even if you have single sided placement (all components on top), you inevitably must resolve crossings by switching traces to the bottom side, for at least a short length. This creates a slot in the bottom pour.And if we pour on top, we'll have even less density due to all the components and routing already there.So what to do?If we pour both, and add stitching vias between top and bottom, around any crossing, or around any span where there's a slot in the respective layers, and avoid routing on both layers in a given location as much as possible: we can keep the loop length to a minimum. That is, the loop of ground surrounding any given point, on any given route.We can make an observation: anywhere two traces cross (or a trace under a row of component pads, etc.), there is a void straight through both pours. The negative space in both, is overlapping. In the case of two traces crossing, the best we can do is three or four vias in the corners beside the intersection, keeping the loop size down to trace width + 2*clearance. We should strive to minimize this loop area.If we poured VCC and GND, we would find we inevitably need numerous connections (jumper traces) to both, from pins orphaned by other connections. The impedance, from any given point to this combined reference plane, will be higher. Bypass is easy enough at least, caps can be placed anywhere the two pours overlap -- but getting to them is the problem, and to get low impedance at a component, you're probably still going to need local bypass anyway. (One of the advantages of 2+ planes, is being able to eliminate some bypass caps. Appnotes try to play it safe, they won't recommend this -- but it is very reasonable option, when one takes the time to consider the power distribution network (PDN).) But worst of all, we don't have an alternate layer to stitch against:every single trace, on either layer, is a complete and utter void in that entire plane.Ideally perhaps we would place a bypass cap at every crossing -- but that will get obnoxious very quickly, not to mention expensive. We should only need a bypass for every power pin say, or group thereof. Perhaps we would stitch by using two vias and a jumper track on the opposite layer -- but this is very fragile, not to mention tedious. (This is a good alternative in locations where it's the best option, but it's probably a bad idea to design a whole board this way. Let alone maintain such a design.) Whereas stitching vias can sometimes be handled by EDA tool alone!So I recommend to route a 2-layer board as ground both sides, and the layer affinity can vary with area. So, preferably most components and routing is on the top, but bottom routing or placement is perfectly acceptable as long as it's stitched as well as the top side placement is; and as long as both are as exclusive as possible (no overlap). VCC should be routed point-to-point as any other signal, with point-of-use bypass, and other PDN considerations as applicable. (A point-to-point chain topology will generally approximate a lumped-equivalent transmission line network, which is easily terminated with some resistance at one or both ends. We don't want to draw DC current with those terminations, so an R+C is used. Typically an electrolytic or tantalum capacitor with nominal ESR, or a ceramic with the ESR added in series as a separate resistor.)Tim

author: elcrni
author_rank: Regular Contributor
timestamp: March 21, 2021, 11:37:14 am
content: Many thanks for your help guys.@tim, thanks for extensive explanation, some parts are not really clear to me as i am not an engineer but i think i understand the gist of it.Now, i did not mention that my board is 2 layer, as most of my other boards, there was simply no need for 4 layers, or at least i thought there was no need.4 layers production cost does increase the cost but i would rather have it done at a higher cost properly than waste money on 2 layers and have something that may or may not work.Also, one perhaps important thing i did not mention is that i am using embedded Arduino2560 board so that makes it easier as not too many traces and paths on the PCBbellow is my board design, i still need to add one more component but this is basically it. Board render at the top shows the top layer where all components are placed, therminals, 7-segment displays and a few LEDs are more or less the only things going through both layers.To my untrained eye, this still seems doable on 2 layer board, but perhaps only one layer as GND or both as GND and then VCC routed as any other signal.once again many thanks for help.Alek

author: tszaboo
author_rank: Super Contributor
timestamp: March 21, 2021, 12:08:27 pm
content: Quote from: elcrni on March 21, 2021, 11:37:14 amOh, it is going to work. Very likely it is going to work.The issue is this:There is a huge difference between1) something barely working and2) something properly designed.1) will work with one specific power supply, if you don't have noisy CCFL lighting, and will disturb channel 1 on the radio.Large portion of the open source designs online are 1). And they dont get properly tested. And you need a lot more knowledge to make something proper, than something work.

author: elcrni
author_rank: Regular Contributor
timestamp: March 21, 2021, 12:22:08 pm
content: Quote from: tszaboo on March 21, 2021, 12:08:27 pmThanks for your reply!Unfortunately, since i am not an engineer and will never be one, and since this is a hobby, i am afraid i will never be able to design circuits properly or up to high standard by any measures :-)I am a bit of a perfectionist and i do want/like to do things better or at least up to some standard, whatever i do, thus asking questions and trying to learn as much as my free time allows, but again if i am investing time in something i would very much like to make it as best as possible.Many thanks,Alek

author: Siwastaja
author_rank: Super Contributor
timestamp: March 21, 2021, 12:40:57 pm
content: It is true that designing on 4 layers is far easier if you have the same design complexity. 2 layers is cheaper to manufacture but takes longer (and requires more skill) to design if you are interested in signal integrity.If you are a bit of perfectionist and don'tneedto save cost, nothing wrong ordering a 4-layer PCB. Route on the top and bottom. Then you are left with basically three viable options:1) mid layers are GND and GND.Power is routed on top or bottom.2) mid layers are GND and Vcc.Separate power routing is not needed. Decouple the GND and Vcc planes with capacitors sprinkled all over; Vcc works as an AC reference plane as well as GND. Note, the layer doesn't need to be completely one net. If your design has multiple supplies, you can segment the plane.3) mid layers are GND and routing.You still have a full ground plane which is great, and a third layer for routing, which is handy especially with two-sided SMD load eating up routing space in top and bot.Do note though that either top or bottom ends up without a closeby reference plane, instead interfering with the third routing layer. For low-to-medium speed*, a few trace crossings usually isn't disastrous, but there will be some crosstalk.I often end up with a hybrid; i.e., mostly use the inner layers as planes, but then in case of a difficult routing, I "borrow" a plane a bit and run a trace of two there. You can't do that with brain turned off; you need to look at what traces cross and understand there will be crosstalk if/when that happens. Doing limited distances helps, so that the layer is still mostly a plane, with only short tracks with no critical signals on the next layer at the same spot.*) speed refers to the signal edge rate. A microcontroller digital IO pin can have quite fast edge even if you switch just once a day. Some have configurable IO speed; if not, adding some 47ohm series resistors at the driving end helps.

author: elcrni
author_rank: Regular Contributor
timestamp: March 21, 2021, 01:08:32 pm
content: Thanks guys, really appreciate your help.Since the cost increase for 4 layers is not a disaster, i will go with 4 layer design.NowQuote from: tszaboo on March 21, 2021, 12:08:27 pmbelieve it or not, this design works without any issues for a year now, on BREADBOARD :-))) and showing a rats nest of wires would give a heart attack to a professional.Idea here was to finally get the design onto a PCB thinking i would eliminate most of the issues with loose wire connections etc.@SiwastajaMany thanks for a nice explanation. As i would rather avoid sprinkling caps across the board, perhaps i will chose 2 GN planes in the middle and then route signals and VCC on remaining 2 planes.ORCould i go with GND as top layer (that way close to many components on top layer) and the route signals and VCC on remaining 3 lines. Would this effect anything in ways different than having a GND in one of the inner layers and then route on remaining 3 layes?Many thanks,Alek

author: Siwastaja
author_rank: Super Contributor
timestamp: March 21, 2021, 01:28:04 pm
content: You need to "sprinkle" those capacitors anyway, regardless of whether the power distribution network is a full plane, or a tree of traces on a routing layer. Basically one per IC pin is typical. Of course you can do with fewer of them, it's just a simple rule-of-thumb.Analysing power distribution networks rigorously gets quite complex.You can use top or bottom as a ground plane if you want to, but if it's an uninterrupted plane, then you can't place SMD components there. Using mid layers as reference planes (ground or Vcc) leaves both top and bottom free for mixture of placing components and routing.Routing in the same layer as the (SMD) components means significant reduction in vias because you often go with a trace from a component to another, you don't want to hop layers all the time for no reason.Component placement is important. With proper placement, you minimize the need for long tracks and vias, a good SMD design "flows" naturally from component pad to another component pad with just enough distance to make building (possibly debugging) it easy, but no more.

author: elcrni
author_rank: Regular Contributor
timestamp: March 21, 2021, 01:52:43 pm
content: Thanks Siwastaja!Maybe there has been a misunderstanding about caps, i already do have caps on every IC, if you look closely i have 2 caps per IC (plus ISET resistor), one ceramic 100nF and tantalum 10uF for decoupling, same goes for Atmega328 MCU.Quote from: Siwastaja on March 21, 2021, 01:28:04 pmYes, this makes perfect sense, so top/bottom routing and inner layer or both for GND.Many thanks,Alek

author: elcrni
author_rank: Regular Contributor
timestamp: March 21, 2021, 02:06:57 pm
content: just finished a test autoroute, seems like awful lot of vias and routs dont make a lot of sense either.Trying to understand why did it choose bottom plane for routing MAX7219 IC to Through hole 7-segment displays, thus creating lots of vias, when this could have been done without any vias on top plane...

author: mvs
author_rank: Frequent Contributor
timestamp: March 21, 2021, 02:27:06 pm
content: Quote from: elcrni on March 20, 2021, 11:09:35 pmOn 2 layer PCBs one side is usually used for prevalent horizontal signal routing, another side for prevalent vertical signal routing. GND plane is on both layers stitched together with vias.MAX7219 are quite noisy chips, so place more different decoupling caps near them. You do not need to populate them all right away.Ferrite bead in series with supply may reduce EMI aswell.You may also want to reduce slew rate of SPI interface by adding low value resistors in series.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 21, 2021, 02:41:17 pm
content: You may want to hand-route some things first. Short, simple connections (nets with few pins, say 2 or 3) are unlikely to conflict with anything. SPI bus is probably next. It should be routed together (to keep delays similar), and yes as mentioned, every pin driver should have a source termination resistor at it. If the MCU is the only source, then there; if you're getting MISO back from various devices, or there is multi-mastering, then that too.Then auto-route everything else. Take note of where it's generated lots of vias, and try to untangle and simplify things. If you see a lot of nets crossing your SPI bus, consider swapping its layer locally to allow them to pass -- this can save vias and routing congestion, and the bus doesn't care about passing through a few extra vias.Nets routing between local areas, if there are any other than SPI -- try to clean these up, maybe make a routing grid they follow, as if highways and on/off ramps where crossing. Probably, that much detail isn't needed, just that it may be helpful to think in those terms while teasing apart the mess created by the autorouter.Also, since you've settled on 4 layers, go through and check every power and ground pin -- the autorouter won't always make these as concise as they can be. Don't be afraid to use vias liberally, you can keep noise down by keeping trace and via length down, and not sharing vias/traces with multiple power pins. (It's fine to share, like, a run of adjacent pins on a given device, that often shows up when there's a fixed pull-up/down pin beside a power pin. Inputs don't count. Sharing two adjacent, or nearby anyway, power pins, isn't usually a big deal either, though there are reasons why they might be preferred on separate vias.)Tim

author: elcrni
author_rank: Regular Contributor
timestamp: March 21, 2021, 03:24:58 pm
content: thanks guys!Quote from: mvs on March 21, 2021, 02:27:06 pmShould this be placed once in SPI line, ie from MCU to the first MAX IC or between each MAX IC as well?For all 3 SPI lines? Resistor value?@T3sl4co1l,Yes, i always hand route some lines first and then do extensive cleanup after autoroute. Autoroute is there just to save some manual labor i guess.Thanks,Alek

author: mvs
author_rank: Frequent Contributor
timestamp: March 21, 2021, 03:57:05 pm
content: Quote from: elcrni on March 21, 2021, 03:24:58 pmIt should be placed on all used outputs: MOSI, CLK, LOAD of your MCU and DOUT of all MAX7219 except the last one in the chain.Value depends on the desired edge speed. MAX7219 has its own memory and does not require much of SPI bandwidth, so you can reduce SPI speed to 100KHz or even less and use 100-330 Ohm for termination.

author: elcrni
author_rank: Regular Contributor
timestamp: March 21, 2021, 04:07:56 pm
content: Quote from: mvs on March 21, 2021, 03:57:05 pmThats great, thank you!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 21, 2021, 04:19:41 pm
content: Quote from: elcrni on March 21, 2021, 03:24:58 pmOn each pin driver (output), by the pin. Location matters!Tim

author: phil from seattle
author_rank: Super Contributor
timestamp: March 21, 2021, 05:36:20 pm
content: Hand vs auto routing. For beginners, it is tempting to rely on autorouting. The results are well less than pleasing though. And the Eagle autorouter (unless significantly improved over V7.7) is pretty bad. I found that if the Eagle AR can get to 100% on a board, hand routing it isn't that hard. If you are at all serious, hand routing is a must. For your board, I think hand routing will not be that hard - 2L or 4L. Try routing the power lines by hand first, then the comm lines (I2C, it seems) and see what the AR does after that. But, I think you will be better served by pushing forward with hand routing.Eagle is not a bad choice. I used it for 20+ years with good results. But always hand routed. I switched to Kicad a bit less than a year ago, and won't be going back. The "push" routing feature makes hand routing a lot easier. Basically as you route a trace, it pushes the other ones to make room so you aren't constantly rerouting/moving other traces. It about doubled my hand routing speed and reduced the strain I felt with Eagle. I'd recommend moving to Kicad though maybe not for this project. If helps that Kicad has no strings attached like Eagle does. And if you are getting boards assembled in china, Kicad's CAM beats Eagle's, hands down.

author: elcrni
author_rank: Regular Contributor
timestamp: March 21, 2021, 05:44:44 pm
content: Thanks Phil from Seattle!Yes, for this one it will be china, i tried them for the first time a month ago and was quite surprised by results, but went with "premium quality" so that may have helped as well.Again yes, seems like it will be most hand routing on this one.One question now, since LOAD and CLOCK lines from MCU to MAX7219 are common, do i have to run these two from MAX00 to MAX07 or i can make shortcuts, for example MAX7219 number 07 (last in chain) is quite close to MCU, can i just run LOAD and CLOCK straight to last MAX or does it for any reason need to follow the path from MAX00 to MAX07?Another question, this is my first time working with MAX7219 SMT mount, i've notice "tRestrict" layer preventing me to access pins on top plane so i need extra vias to go under the IC and then exit to top plane again... can i remove this restrict in footprint and just access the pins without vias?Once again, huge THANKS to all of you, i have learned a lot today!Alek

author: mvs
author_rank: Frequent Contributor
timestamp: March 21, 2021, 07:23:14 pm
content: Quote from: elcrni on March 21, 2021, 05:44:44 pmWith reduced slew rate and SPI clock speed you can route your traces as you like. It is definitely not a high speed design.Even if you run SPI at max speed (4-5MHz clock or 250-200ns clock period on AVR MCUs) it should be ok.

author: phil from seattle
author_rank: Super Contributor
timestamp: March 21, 2021, 10:39:51 pm
content: Quote from: elcrni on March 21, 2021, 05:44:44 pmI don't see anything in the datasheet about a restriction. Eagle IC footprints often have a somewhat dubious origin. In the words of Ronny Reagan, Trust but Verify. And, I would trust the datasheet over an Eagle footprint every time.As long as we are on the IC footprint topic, always dry test your board layout with real ICs to make sure your footprints are correct. This has saved me several times. And, conversely, not doing so has caused me a wasted PCB run (money and, more importantly, time).

author: Siwastaja
author_rank: Super Contributor
timestamp: March 22, 2021, 07:41:09 am
content: Just don't autoroute. Just no.

author: elcrni
author_rank: Regular Contributor
timestamp: March 22, 2021, 09:09:18 am
content: hi guys,Thanks for the help.Quote from: mvs on March 21, 2021, 07:23:14 pmThanks!Quote from: phil from seattle on March 21, 2021, 10:39:51 pmYeah, i could not find anything in the datasheet but though it could be some rule or something i am not aware of.As for the dry fit, hah, i though i was the only one printing a PCB/footprint onto paper and dry fitting :-)Now onto the autoroute. How i did it so far is i would autoroute everything and then extensively touch up all traces up to a point where i'd adjust every single trace on the board. Autorouter in my mind was there to decide if and how many vias etc, but judging by your comments, a monkey could do better. This got me thinking last night, if i am adjusting every single or most of the traces, why not try and hand trace everything from the start, as many of you suggested. At the start this was a bit scary thought but after an hour i did some 25% of the board routed. Ok, it was relatively easy for first traces as there were no path crossing yet but i was happy with how it went. did some more reading and found an interesting article with basic set of rules (https://www.signalintegrityjournal.com/blogs/12-fundamentals/post/1207-seven-habits-of-successful-2-layer-board-designers) basically everything has been more or less said here on this post but the article is a sort of a summary with a few photos to illustrate. Turns out i was making mistakes with overkill trace widths among other things.there are still a couple more things i am not sure about:1. What has a higher priority to go straight without vias, signal (SPI, MAX7219 to display...) or power? If signal is crossing the power, should i place vias on the signal, or it doesnt matter?2. Is there a quick way to stitch GND planes so i do not have to place 2 rows 6-8 vias each row, one by one? or i could go with just one row 4-6 vias?Thanks again for helping me out with this. I think i am ready for my first, half-decent board routing :-)Will report back how it went shortly.Alek

author: exe
author_rank: Unknown
timestamp: March 22, 2021, 10:29:26 am
content: Quote from: T3sl4co1l on March 21, 2021, 04:19:41 pmOh, wow, finally I see discussion on this topic. The idea to put a resistor to "slow down" digital signals came to me a few years ago, but I never seen anybody doing it. Is this a viable solution? I've only seen once mentioned in one TI or LT datasheet to put 10-33 Ohm resistors on spi lines. I wonder if I can put more, like 100 or 500 Ohm provided I don't need much bandwidth?There are two objections to do so:1) noise immunity, for me it's hard to say if 500 Ohm drive is a problem and what's typical hysteresis on input pins of ICs. (Why 500 Ohms? I did an experiment, 1K resistors were good-enough to drive an isolator at data rate of 8 kbit or so, so 500 Ohms should have provided some margin in that case).2) The one I came recently. I heard (including in AoE) that slow transient can cause a shoot-through. Like in this doc:https://e2e.ti.com/support/logic/f/logic-forum/737694/faq-how-does-a-slow-or-floating-input-affect-a-cmos-device. Is this still a thing? I've only seen max rise time specification a couple of times. Most of the time I see "min rise time" specification, which I'm not sure why is there, but I don't care as my signals are slow.How I came up with this idea: I played around with digital isolators from aliexpress and I was checking their specs (they are kinda expensive from distributors, so I decided to take the risk for my pet project, it's not for isolation from mains, it's to separate channels on lab power supply, so kinda not critical for safety). I noticed a lot of ringing when using even moderately long wire on a breadboard. I was able to remove ringing with a resistor.

author: Siwastaja
author_rank: Super Contributor
timestamp: March 22, 2021, 01:02:35 pm
content: Quote from: exe on March 22, 2021, 10:29:26 amOf course, it's being done all the time everywhere. Maybe you have wrong keywords?In any case, the term is "series termination", but such term would be used only when the R is tuned for quite "optimal response", you could say; this happens when the total driver impedance (CMOS IO pin Rds_on + external resistor) matches the characteristic impedance of the transmission line, which is by the geometry of the line (basically the ratio of the track width to the track distance from the reference (return path) plane). With exact matching, reflections are eliminated (but the signal is only valid at the receiver pin). If you use too little R, you see reflections and overshooting voltage.You can also use too much R by purpose...Quote... which will obviously still kill the reflections, but this will indeed slow down the edge. When R starts going well beyond the transmission line impedance, it's likely easiest to analyse as simple RC circuit, C being the parasitic capacitance of the receiver pin and the track itself.QuoteIt's quite obvious increasing the driver impedance by adding more R in series reduces noise immunity. If your target is to significantly slow down the transitions, you need to use high values of R because the C is very small (by design; the IC manufacturers don't want to slow you down). Solution: use larger C! Larger C in itself filters noise, and it also allows a smaller R to be used.It's not unheard of to increase the robustness against noise by limiting the bandwidth of plain old single-ended voltage based digital signaling by RC filtering. I have done that successfully many times. Something like a 100 ohms, 470pF for RC=470ns works way better than 2.2kOhm, 20pF (parasitic C only) for the same RC time constant.QuoteBasically all modern CMOS digital logic input pins have a bit of hysteresis - not as much as proper "schmitt trigger" inputs, but enough so that slowly changing input signals do not become noise disasters, let alone cause large shoot-through currents. For example, microcontroller pins typically accept any arbitrary DC voltage within the rails for unlimited time - because the pins are shared with ADC, anyway. A very limited version of the "shoot through" happens, though; the inputs do consume more current at the intermediate state (which is why the digital input circuitry can be programmatically disabled), but nowhere near to cause any damage; this is usually only significant in low-power (battery-operated) applications, or when this small extra loading distorts a high-impedance analog signal.

author: cheeseit
author_rank: Regular Contributor
timestamp: March 22, 2021, 02:44:49 pm
content: Some great tips here!And ditto for the dry fit, this can indeed be a time/money saver. When needed, ie. the board has to fit into something or clear something above or below the board in an enclosure, I'll print a transparency.

author: elcrni
author_rank: Regular Contributor
timestamp: March 22, 2021, 07:04:42 pm
content: ok, i am now well into hand routing and i like it. feel a bit lost and desperate in some moments but i think its going ok.I have intentionally started this on as 2 layer thinking it would be a great practice. both layers GND pour but i am trying my best to use bottom layer for short tracks only, by doing so not sure this what i have looks ok. couple of things:1. I have one main 5V connection and draw branches/traces from there, BUT at some point 've started "branching" from some of the main "branches"... is that ok?2. trying my best to keep the cross-unders as short as possible but have a feeling i will have a lot of those by the end of this adventure.3. i like things well organized (i am suspecting a mild OCD is well underway) and no matter how much i try to have traces as neat as possible, i have a feeling i am getting lost and will end with a mess.Many thanks,Alek

author: phil from seattle
author_rank: Super Contributor
timestamp: March 23, 2021, 05:48:20 am
content: For a 2L board, I generally route power first. Try routing it around the outside of the board so you aren't "cutting" the layer in half. A power via isn't a problem unless there is a lot of current.Also, I play with component placement a lot to try and minimize the number of crossing air wires. This is where I would sometimes use the eagle autorouter to just get a sense of how complex it is. Make all your corners 45 degrees - 2 45s is better than 1 90.The place to try and avoid vias is in your highest speed lines. You will get a reflection. But your design isn't that high speed in the first place.Try to have a trace enter a pad at a right angle. Maybe that makes me an old timer but I do try to avoid "acid traps" even though they aren't an issue any more. If nothing else, it looks better to me.

author: JohanH
author_rank: Frequent Contributor
timestamp: March 23, 2021, 10:25:36 am
content: Quote from: phil from seattle on March 23, 2021, 05:48:20 amPlease don't say something is better without telling why. 45 degrees corners save some trace lengths of course. But if you need to make 90 degrees corners it is perfectly fine. But plainly stating that 45 is better than 90is a myth.

author: mvs
author_rank: Frequent Contributor
timestamp: March 23, 2021, 10:46:17 am
content: Forget about 45° and 90°, topological routing is a next thing.https://en.wikipedia.org/wiki/TopoR

author: jmw
author_rank: Frequent Contributor
timestamp: March 23, 2021, 04:13:45 pm
content: Quote from: T3sl4co1l on March 21, 2021, 03:05:08 amTim, could you elaborate here? VCC gets routed point-to-point, so between each component the trace is basically an inductance, and the bypass caps are shunt capacitance in a lumped transmission line. How would you choose the termination impedance at the end?

author: JohanH
author_rank: Frequent Contributor
timestamp: March 23, 2021, 06:02:04 pm
content: Quote from: mvs on March 23, 2021, 10:46:17 amI guess it is time for EDAs to take next step. Computing power today is so much better, so no need to limit to 45°. Any angled corner (45°, 90° or whatever) anyway got the impedance wrong (traditionally mitigated by mitre/miter corners). But sorry for off-topic.

author: exe
author_rank: Unknown
timestamp: March 23, 2021, 06:07:43 pm
content: As I understand, the distance between signal layer and ground plane makes a big difference. Does it me mean smaller distance is always better? Asking because at jlcpcb I can choose between 0.2mm and 0.1mm prepreg options. I suspect in some cases extra capacitance to ground can be bad. Like, current feedback amplifiers are sensitive to stray capacitances.

author: elcrni
author_rank: Regular Contributor
timestamp: March 23, 2021, 06:08:59 pm
content: Thanks everyone!Next PCB preview attached. This is getting more and more out of my hands, most of the traces i am happy with but perhaps most important ones (SPI) are looking like a plate of spaghetti, i just cant avoid vias.... which further got me reading a lot more about signal integrity which the got me back to the start of this topic where it was explained that basically SPI is too slow to worry about signal integrity...I still have to stich GND planes and sprinkle GND vias around as that seems to be the big issue with MAX7219 ICs.so, i know i am repeating the question but would all these vias on SPI affect anything?On the second image is my working prototype, and when i say working, i mean it runs without any glitches on any of 15 MAX7219 displays, for almost a year now. Pardon my wiring :-) what started as a prototype ended up as working piece.Many thanks,Alek

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 23, 2021, 06:09:40 pm
content: Quote from: jmw on March 23, 2021, 04:13:45 pmSure. The effective impedance is sqrt(L/C), where L is the average trace inductance and C is the average bypass cap. It helps that these be similar (small variance to the average), as large excursions from the average will give weird peakiness to the frequency response -- as a result, the terminations may not be the expected values, or may not work as well as desired.At the end of such a chain, the impedance will be high -- effectively all the inductances act in series and all the capacitances act in parallel, making a resonant tank with shunt C and series L, and this is easily terminated with a shunt R. We wouldn't use R alone of course, as that would be quite wasteful; we use an R+C where the C is several times larger than the total C of that branch.At a node where several such chains join up, the impedance will be low -- effectively all the inductances and their capacitances act in series. Shunt R+C is ineffective at this point. Series R||L can be used (sized by the same rule as above, solving for L of course) instead, or a large series L followed by shunt R + large C. The latter is good when extra filtering is desired -- since, why waste an inductor on a stupid R||L that's only ever going to be a few ohms or whatever.Note that large, very low ESR capacitors serve the same function as a star node: low impedance, so everything hanging off it can resonate against that anchor point. Like having a bunch of wobbly sticks tied to a heavy mass, the mass barely moves while everything can flap in the breeze.Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 23, 2021, 06:29:20 pm
content: Quote from: elcrni on March 23, 2021, 06:08:59 pmAgain, vias are fine. The things that jump out to me are:- At the Arduino: this is fine, the top three traces on the bottom layer are clearly better dodging that bus of LEDs. Well, arguably I guess. As long as their bottom-left ends make room away from the next two or three traces on the bottom, bottom ground can pour around them.- The 5V trace, from the, I don't have a clue what it is, there aren't designators on here, at least that are visible at this scale -- from the terminal block, there's a large enclosed area between the two traces dropping down to supply two chip resistors. This makes an island of ground on the top side, which has to be stitched around to connect effectively. Easier to just pull the 5V route down by the resistors, eliminating that island, and now stitching only has to be either side of that row of resistors, and connector (BRIGHTNESS CONTROL SWITCH?), no problem.- Similar may be for the, whatever they are, the two smaller 4-digit displays bottom-center, currently unrouted -- those two traces dog-legging to the bottom-left may be better paired with the other two going up, saving you from enclosing the whole display area with another ground island.- Also, those driver chips could stand to be rotated or flipped, probably.- And if those dogleg traces are part of the SPI bus, then, a better route for the bus might be: Arduino, big display, bottom pair of small displays, left pair of small displays, dot matrix, top left displays and matrices, top center large matrix, top right matrix and display, center right large matrix, right matrices, etc. Oh, or are those displays and matrices paired, maybe it's better to chain them in some logical or physical order. Or if you have the serial chain all planned out, just route it back and forth, it's a mess that's what layout is for, resolving connections and you have a ton of space to do that with, it's fine.It's hard to tell what's going on without being able to see net names on everything, so I'm making assumptions and keeping it somewhat general here.Tim

author: phil from seattle
author_rank: Super Contributor
timestamp: March 23, 2021, 06:40:34 pm
content: Quote from: jukk on March 23, 2021, 10:25:36 amshorter trace length. At higher frequencies, less reflections. and, they just look better. Yes, better EDAs might help but we are talking Eagle here.As long as we are here, why don't you help the OP rather than critiquing people who are helping.

author: elcrni
author_rank: Regular Contributor
timestamp: March 23, 2021, 06:48:19 pm
content: Quote from: T3sl4co1l on March 23, 2021, 06:29:20 pmMany thanks Tim.You're pretty much spot on on all net names and your observations are well worth thinking about.I have 2 chains of 8 MAX chips but as you said, numbering order is all messed up at the moment. I had it that way on my prototype and now just brought the same chain order to a PCB.There are for sure better combinations than the order i have now, not sure if i should start over and just later change the order in the code.a quick sketch of how tracing could be much easier and better. on 2L board, i am sure i can not avoid vias on SPI but what i have at the moment seems like a mess. Also, ICs a hard to acces with 3 traces for SPI, i can either put vias on SPI or later put many more vias on IC to display traces.Many thanks,Alek

author: elcrni
author_rank: Regular Contributor
timestamp: March 23, 2021, 08:00:24 pm
content: Quote from: T3sl4co1l on March 23, 2021, 06:29:20 pmYes, i had the serial chain planned out in prototype and i would pretty much like to keep it as it is, even though it may not be logical or physical order. I did route it back and forth but can not escape the feeling that i have created a mess on SPI traces and that i may have undesirable effects with the board.I do have a lot of available space, most if not all traces have only GND below and with some further stitching, should be ok i guess.Thanks,Alek

author: elcrni
author_rank: Regular Contributor
timestamp: March 24, 2021, 08:55:43 am
content: it seems i have forgotten to mention perhaps the most important thing about my SPI, as i am NOT using hardware SPI on arduino but random pins ("software bitbang") and "LedControl" library that does not require hardware SPI.I have measured CLOCK speed on a designated digital pin and i got 46kHz, so this would basically make those resistors on SPI lines redundant? or i still need those? I have 2 chains, 8 MAX7219 ICs each (as that seems to be max with LedControl).Also, fastest display change interval is 1 second.This in return gives me the choice to shift the pins i now have for SPI to other set of pins, so i can avoid the mess with traces going from Arduino at this moment.Thanks,Alek

author: exe
author_rank: Unknown
timestamp: March 24, 2021, 10:42:10 am
content: Quote from: elcrni on March 24, 2021, 08:55:43 amIt's not about signal fundamental frequency, it's about raise and fall times of the signal, signal levels and peak current. A 1Hz signal is perfectly capable of creating lots of interference at each cycle. Perfect square wave has infinite number of harmonics.

author: cheeseit
author_rank: Regular Contributor
timestamp: March 24, 2021, 10:15:12 pm
content: Quote from: elcrni on March 24, 2021, 08:55:43 amI regularly move microcontroller peripherals, inputs and outputs to other pins while laying out a board to simplify routing. One thing is doing the schematic and assigning functions to pins, another is doing the layout and I don't have the experience nor smarts to predict the optimal pins for a given function before doing the layout on a modestly complex board. Same thing with logic chips. I'd think this is common practice.Schematic to breadboard, write code and get things working. Then I start on the board layout and modify the schematic, breadboard and code to aid placement and routing following best practices as I know them. Lather, rinse, repeat.

author: elcrni
author_rank: Regular Contributor
timestamp: March 25, 2021, 10:15:54 am
content: Many thanks everyone for all the help!Mo board is almost ready to hit production, going through the last round of checks to make sure everything is where it should be.now thinking i would add Schmitt trigger for my encoder and perhaps switches, even though i do have RC filters on all of them, and not that i really need Schmitt as everything is working as it should without it, but thought i may include it in this design to test it and perhaps evaluate for future projects.The thing i was wondering about is the location od Schmitt I, does it matter? Does it need to be close to Encoder/switches or MCU?oh and another one, i have 2 MAX7219 ICs that only drive one 4 digit display, so i have unused pins, do these need to be terminated in any way or to just leave them unconnected?Will post my finished layout later today once everything is ready.Many thanks,Alek