High Speed Parallel In Serial Out Shift Register? - Page 1
Forum section: electronics / general

author: Stephen Hill
author_rank: Regular Contributor
timestamp: July 13, 2012, 10:52:35 am
content: Hi,Does anyone know of any high speed - 100Mhz to 500Mhz - PISO Shift Registers?The fastest I have managed to find so far is around 90Mhz at 5V but most seems to be no more than 45Mhz and even less at lower voltages.Any suggestions would be very much appreciated.Many ThanksStephen

author: deephaven
author_rank: Frequent Contributor
timestamp: July 13, 2012, 11:43:28 am
content: Quote from: Stephen Hill on July 13, 2012, 10:52:35 amIs 3 GHz fast enough? ECL devices can go at that speed:http://www.onsemi.com/PowerSolutions/product.do?id=MC100EP142Other than that, an FPGA but that might be an overkill for your particular needs.

author: jahonen
author_rank: Super Contributor
timestamp: July 13, 2012, 11:44:37 am
content: That sounds much like (P)ECL stuff. However, PECL might be not very convenient to use due to different logic levels and very high static power consumption. You might want also look at CPLDs or FPGAs too.Regards,Janne

author: hlavac
author_rank: Frequent Contributor
timestamp: July 13, 2012, 11:46:42 am
content: That is a bit too fast for 5V logic... It will have to run at lower voltage to get to such speeds.Easiest way is probably to use some CPLD.Of maybe 7.5ns speed grade GAL20V8 if you can still get a programmer for that.nah that will be too slow

author: hlavac
author_rank: Frequent Contributor
timestamp: July 13, 2012, 11:58:55 am
content: ThisCPLDcan do 500MHz and is not very expensive.

author: Stephen Hill
author_rank: Regular Contributor
timestamp: July 13, 2012, 12:37:01 pm
content: The OnSemi part looks nice but availability doesn't look good. (At least not in the UK).That CPLD might just be what I was looking for. Although it will make development a little longer (software), it gives me room to add features to my project later, if I choose.Thanks for all of the suggestions.CheersStephen

author: Stephen Hill
author_rank: Regular Contributor
timestamp: July 13, 2012, 12:59:45 pm
content: Just seen that LatticeSemi do a small dev board for this series of CPLD:http://uk.farnell.com/lattice-semiconductor/lcmxo2280c-m-evn/kit-development-machxo-mini/dp/1702036

author: hlavac
author_rank: Frequent Contributor
timestamp: July 13, 2012, 02:03:27 pm
content: Yeah but that is pretty expensive.You can have full FPGA board for much less than that -DE0 Nano

author: Stephen Hill
author_rank: Regular Contributor
timestamp: July 13, 2012, 02:32:39 pm
content: I'm not so sure. I might be paying more for my dev board, but the chips themselves are relatively inexpensive < 20 GBP in QFP.FPGA's are generally more expensive. The FPGA used in that dev board is 42 GBP and only available in a BGA package.I don't mind paying more in the development process if the production process is cheap(er).

author: Stephen Hill
author_rank: Regular Contributor
timestamp: July 13, 2012, 02:34:09 pm
content: Although that is a nice looking dev board. I like the acrylic top

author: codeboy2k
author_rank: Super Contributor
timestamp: July 13, 2012, 05:01:58 pm
content: The MachXO CPLD from Lattice really is quite a nice CPLD, and some devices have features that you might only find on a FPGA, like clock PLLs and multi-voltage I/Os. They have some hard IP built in if you need it, like i2c, and can do an ADC in soft IP.I've been playing with the dev board and I will probably use it in a future design.

author: Stephen Hill
author_rank: Regular Contributor
timestamp: July 13, 2012, 06:58:01 pm
content: Quote from: codeboy2k on July 13, 2012, 05:01:58 pmWhat are their software development tools like?

author: free_electron
author_rank: Super Contributor
timestamp: July 15, 2012, 05:26:41 am
content: Cypress has some that hit 1.4 Gb/s. parallel in serial out. they contain full bidirectional paths. LVttl or LVDS signalling.typically used for video transport (SMPTE)10 bits parallel in under control of a clock. the other side spits out the 10 bit data + clocklook for 'cypress hotlink'