Google Coral M.2 on non-x86 GNU/Linux SBC - Page 1
Forum section: electronics / general

author: DiTBho
author_rank: Super Contributor
timestamp: April 01, 2023, 04:32:16 pm
content: The Google coral M.2 Accelerator is a small ASIC designed by Google that accelerates Tensor Flow Lite models in a power efficient manner.It's available in an M.2 module/E-key that includes two Edge TPU ML accelerators, each with their own PCIe Gen2 x1 interface.- - -anyone?any experience?- - -tempted to buy one for my new MIPS/EL SBC

author: DiTBho
author_rank: Super Contributor
timestamp: April 01, 2023, 04:58:12 pm
content: Some Python examples,here(get started)

author: DiTBho
author_rank: Super Contributor
timestamp: April 03, 2023, 08:52:35 am
content: Required software components?heremore information on building libraries, misc and kernel drivers, to run inference on the Edge TPUHardware, any constraints? Sure, being a strong interrupt driven co-processor, whichever SBC you choose,MSI-Xis required by the Edge TPU Silicon Engine over PCIe, otherwise without it there's no way to get interrupts and therefore no way to know when operations have completed.I see, 64 bit is also required as a hard constraint - won't this work on a MIPS32? Do you need MIPS64?(I think it has to do with large buffers allocated on the stack)

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 03, 2023, 08:43:02 pm
content: What do you want to do with it?

author: DiTBho
author_rank: Super Contributor
timestamp: April 04, 2023, 11:28:32 am
content: world domination .... something

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 04, 2023, 06:44:57 pm
content: Quote from: DiTBho on April 04, 2023, 11:28:32 amGood luck, you have a lot of competition out there already.

author: DiTBho
author_rank: Super Contributor
timestamp: April 05, 2023, 11:11:11 am
content: Quote from: SiliconWizard on April 04, 2023, 06:44:57 pmyeah, already too many people laugh, you have to exercise to laugh louder

author: DiTBho
author_rank: Super Contributor
timestamp: April 05, 2023, 11:29:55 am
content: first crazy app: Imagine having your super secret router inside a full metal case in your camping tent, at a hacker camp meeting - do you really believe that your router disk is securely protected by an internal contact button as simple "tamper proof sensor?Do you think it is better secured with a bicycle chain lock?Do you feel it is better secured with 5 Kg of locks?last time in the nearby tent they showed how to open all kinds of locksTPUs rely on computer vision and visual deep learning at the edge, so your router can actually "see" who (a human being, but not you!!!) is looking around its metal case and run defensive algorithms(1)(1) send me a message on my Smartphone "Mayday Mayday, this is your router talking, stop hitting on the cos-player girl dressed as TombRider or Trinity or Captain Marvel (input from your taste profile) and get right back to the tent before the hackers crack my rootfs with tons of Trojan horses and all kind of root*hit !!!"Planned for: next summer!

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 05, 2023, 06:59:30 pm
content: Quote from: DiTBho on April 05, 2023, 11:11:11 amI would have posted a video about a real event rather than fictional to illustrate the point, but that probably wouldn't please moderation.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 05, 2023, 07:00:20 pm
content: Quote from: DiTBho on April 05, 2023, 11:29:55 amOK.

author: DiTBho
author_rank: Super Contributor
timestamp: April 05, 2023, 09:47:46 pm
content: Quote from: SiliconWizard on April 05, 2023, 06:59:30 pmI don't have a video handy yet, but I'll probably record something.Anyway, aside from the *playful aspect*, these things are made for catching bugs.For example, two years ago, no one had noticed a terrifying bug on the PCI of a Linux/MIPS router until I had the sick idea of trying to get some weird PCI card to work.

author: DiTBho
author_rank: Super Contributor
timestamp: April 08, 2023, 12:06:40 pm
content: QuoteWhile it's usually easy with x86-SBC, with MIPS and PowerPC SBC it's not easy to tell immediately if it's supported or not.For MikroTik's hw things, Yesterday I opened a Ticket to speak directly with someone

author: brucehoult
author_rank: Super Contributor
timestamp: April 08, 2023, 01:07:33 pm
content: Note the "not supported" and "doesn't work" are very different things.Quite a few Arm and RISC-V SBCs have M.2 but it's usually M-key for SSDs. Some have an E-key for Wifi/BT, but the ones I've looked at only have 1 PCIe lane to them and the Coral needs 2.

author: DiTBho
author_rank: Super Contributor
timestamp: April 08, 2023, 01:37:39 pm
content: Good point.Which restricts the usable set.

author: DiTBho
author_rank: Super Contributor
timestamp: April 08, 2023, 01:44:52 pm
content: Quote from: brucehoult on April 08, 2023, 01:07:33 pmWith bug-fixing(2) I meant - doesn't work *even* if it's supposed(1) supported(3).(1) because so declared by its documentation(2) the most shocking discovery happened with the RSP, since the first bug was the documentation: it said nothing except "PCI 2.1 compliant", so I assumed "full PCI compliant" whereas it was rather "only partially implemented", and that's the annoying part with a lot of SBCs around and modern technology.(3) with the latest router the documentation didn't say you have to "clear a bit in the controller" before issuing a PCI request, so the SBC was randomly pushing junk into memory with a probability of one in every million IOp of disaster - > took weeks to figure out what was wrong

author: DiTBho
author_rank: Super Contributor
timestamp: April 08, 2023, 06:59:56 pm
content: There are three version of Google Coral accelerators for SBCMini PCIe Accelerator,datasheetM.2 Accelerator A+E key,datasheetM.2 Accelerator B+M key,datasheetB+M is confusing, sinceKey B = sATAKey M = PCIe x2Key B+M = sATA or PCIeso why key B?!?also, the datasheet saysQuoteso, is it 1 lane?!?

author: DiTBho
author_rank: Super Contributor
timestamp: April 08, 2023, 07:02:37 pm
content: Key A = PCIe x2 and/or USBKey E = PCIe x2 and/or USBKey A + E = PCIe x2 and/or USB, but it depends on the internal wiring of the motherboard=> more confusing => to be avoided if it's possible!

author: MrMobodies
author_rank: Super Contributor
timestamp: April 08, 2023, 07:18:43 pm
content: https://coral.ai/static/files/Coral-M2-datasheet.pdfQuoteExcellent.Looks to me like a nice little toy to play with.

author: DiTBho
author_rank: Super Contributor
timestamp: April 16, 2023, 08:58:50 am
content: so, after a lot of personal research, most non-x86 SBCs don't have MSI support over PCIeit's really frustrating, datasheets don't even mention any detail about the PCIe.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 16, 2023, 07:28:35 pm
content: Can it implement GPT-4 though?

author: nctnico
author_rank: Super Contributor
timestamp: April 16, 2023, 09:57:54 pm
content: Quote from: DiTBho on April 01, 2023, 04:32:16 pmThis works just fine on Arm64 platforms.

author: DiTBho
author_rank: Super Contributor
timestamp: April 17, 2023, 12:25:51 am
content: Quote from: nctnico on April 16, 2023, 09:57:54 pm64bit armwhich SBC? with m.2? with miniPCIe?

author: ejeffrey
author_rank: Super Contributor
timestamp: April 17, 2023, 02:31:34 am
content: Quote from: DiTBho on April 16, 2023, 08:58:50 amReally? How does that even work?

author: DiTBho
author_rank: Super Contributor
timestamp: April 17, 2023, 12:05:42 pm
content: Quote from: ejeffrey on April 17, 2023, 02:31:34 amworks but without MSI support.

author: ejeffrey
author_rank: Super Contributor
timestamp: April 17, 2023, 08:04:20 pm
content: Quote from: DiTBho on April 17, 2023, 12:05:42 pmMy point was: MSI(-X) is the only way to do interrupts on PCIe. There are PCI interrupt emulation messages, but it's all MSI based. So either that means it has no interrupts at all, or it means something different than what I understand. It's hard for me to see how a PCIe bus that doesn't support interrupts either meaningfully implements PCIe or supports much of anything.

author: DiTBho
author_rank: Super Contributor
timestamp: April 17, 2023, 08:25:10 pm
content: Quote from: ejeffrey on April 17, 2023, 08:04:20 pmso, according to your reasoning then every single bunch that offers miniPCIe PCIe should also offer MSIMessage Signalled Interrupts are analternative in-band methodof signalling an interrupt, using special in-band messages to replace traditional out-of-band assertion of dedicated interrupt lines.Supportedin PCI bus since its v2.2later available PCI Express bus, but not always present in every SoC PCIein some non-PCI architecturesJust to re-check again, I contacted the MediaTek' technical supportQuote

author: nctnico
author_rank: Super Contributor
timestamp: April 17, 2023, 08:34:48 pm
content: Quote from: DiTBho on April 17, 2023, 12:25:51 amWith my self designed SBCs using iMX8 SoC or Jetson TX2 module. Both have M.2 slot and PCIe.

author: DiTBho
author_rank: Super Contributor
timestamp: April 17, 2023, 10:34:12 pm
content: Quote from: nctnico on April 17, 2023, 08:34:48 pmimpressedwhat about the software side in the userland?standard SDK from Google (so, python-based) and standard kernel drivers? as described by them?or something hacked/customized?and, may I ask for what is the TPU used for?

author: ejeffrey
author_rank: Super Contributor
timestamp: April 19, 2023, 07:02:26 pm
content: Quote from: DiTBho on April 17, 2023, 08:25:10 pmNo, this is wrong. MSI is optional in parallel PCI but mandatory in PCIe. PCIe has no out-of-band interrupt signalling mechanism at all. Go ahead and check: the connector pinout has no interrupt pins. The conventional PCI out of band interrupts (INTA, INTB, INTC, and INTD) are implemented as dedicated messages in PCIe. This is mostly necessary to allow PCI to PCIe bridges, native PCIe devices would not normally use them.Note that MSI and MSI-X are different. MSI-X allowed more interrupts and multiple interrupt destinations to allow more flexible interrupt routing in multi-processor systems. I don't know when MSI-X became mandatory, it's possible that early PCIe versions did not have mandatory support for MSI-X.It's also possible that there is some confusion between the interrupt signalling mechanism (which is always MSI in PCie) and how the host interrupt controller lets you configure things. I'm not familiar with the host and OS level configuration.

author: DiTBho
author_rank: Super Contributor
timestamp: April 20, 2023, 03:04:07 pm
content: Quote from: ejeffrey on April 19, 2023, 07:02:26 pmah, ok, now I got it, thank you for your clarificationThat's probably what they meant when they replied:MSI yes by defaultMSI-X not supported in ePCI v1.1Now I have to understand why and if the Google Coral strictly really needs MSI-X instead of MSI.Then I will have to re-check the Linux kernel support for Mediatek MIPS SoCs

author: ejeffrey
author_rank: Super Contributor
timestamp: April 20, 2023, 06:07:39 pm
content: My understanding of the way this works:MSI: each endpoint (bus/device/function) gets a single unique memory address. It writes to that address to signal an interrupt. The interrupt number (up to 32) is part of the message payload.MSI-X: each endpoint is given multiple unique memory addresses, one per requested interrupt. Also, more interrupts are supported (up to 2048)Message routing is only based on the address not the data. So a given device using MSI can only send interrupt messages to a single group of cores. MSI-X uses distinct addresses for each interrupt source so they can be more easily routed to a particular processor/core.This is all at the PCIe transaction level. You also need to consider the capabilities of your platform interrupt controller. I guess (I'm not sure) it's also possible that a given platform interrupt controller doesn't support that many interrupts and just combines them into one per device. If a platform does this but your device driver isn't written to gracefully handle this situation then it won't work even if the interrupt signalling is MSI-X. Again, I could be wrong about this, I don't know much about how platform interrupt controllers or the device driver architecture works, I'm more familiar with the PCIe transaction layer.