Decoupling capacitors on a modern graphics card - Page 1
Forum section: electronics / projects

author: rs20
author_rank: Super Contributor
timestamp: September 19, 2020, 07:01:31 am
content: There's already athread about the new RTX 3000 series graphics cardsfrom a product perspective, but in all the hype, it can be surprising to recall that these are "simply" ICs that do massively parallel+specialized computation. And as such, they need power (hundreds of watts) and decoupling.(Credit: images taken from "Tear-Down: NVIDIA RTX 3080 Founders Edition Disassembly - A Lot Fewer Screws" on youtube.)I know this isn't massively out of the ordinary compared to modern phones etc, but I do love the sheer variety of sizes and types of capacitor in these photos - I feel like I can see at least 6 different package sizes across the front and back of the board. I love how they're scattered all over the place.Anyway, I don't have a question or anything, just thought some folks might find it interesting.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 19, 2020, 08:16:00 am
content: Weird, what's up with the pads in the middle of the non-pop polymer chip footprints? Are they making them in LGA styles now?Maybe it's just an alternate placement for some ceramic chips there.Would love to see a cross section of the PCB. Lots of layers, lots of planes. Would be a bit of a waste of a new one of those though...I wonder at what point it becomes economical to use dielectric-loaded PCB layers. They've got a few thousand capacitors on there, I would guess. Well, apparently this still isn't to that point... (Embedded or carbon-ink resistors too, for terminations and such. That was an IBM thing, among others, don't know that it's ever been used on PC gear though.)Tim

author: rs20
author_rank: Super Contributor
timestamp: September 26, 2020, 01:49:36 pm
content: Quote from: T3sl4co1l on September 19, 2020, 08:16:00 amEDIT: I should have guessed, there's already athread about this.Well, you have no idea how relevant this question has become. In a fascinating twist, it seems NVidia might have been a little too permissive in allowing board partners to use the big, cheap polymer caps instead of ceramic chip arrays:And apparently this is a leading theory for why some cards (which all?/often? happen to use the polymer caps all in 6 positions) become unstable in certain light workloads that permit peakier loading of the CPU (which leads to higher clock frequencies). And so now decoupling capacitors have become a front-and-centre topic in the gaming hardware community:link+ countless YouTube videos that I won't bother linking. Never thought I'd see YouTube commenter gamers saying they'll insist on cards with MLCCs only!Quote from: T3sl4co1l on September 19, 2020, 08:16:00 amI thought the space between layers, while thin by any normal definition, are so thick compared to the layers in an MLCC that that'd not add up to much. But I suppose the huge area, plus the fact that the ESR/ESL is practically exactly zero, could be helpful.BTW, I always appreciate your messages so much Tim!

author: David Hess
author_rank: Super Contributor
timestamp: September 26, 2020, 04:43:24 pm
content: Quote from: rs20 on September 26, 2020, 01:49:36 pmIncreasing the dielectric constant and thinning the layer also lowers the power plane impedance. The effect is significant but costly, but at some point the resulting product is so expensive that doing this is free.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 26, 2020, 09:41:01 pm
content: QuoteIt doesn't take much to make a big difference. You always have bulk capacitors anyway. The reason to add hundreds of small value capacitors is to get low inductance and distributed capacitance. Because each of those capacitors has inductance from the package and vias they make less efficient use of their capacitance than interplanar capacitance. So if you can do it, using very thin laminate to get moderate interplanar capacitance can replace a bunch of surface mount capacitors even if those capacitors have a much larger capacitance on paper (i.e., at low frequency). You don't actually care about the low frequency behavior because you have bulk capacitance for that.

author: dmills
author_rank: Super Contributor
timestamp: September 26, 2020, 11:07:19 pm
content: I priced out doing the planar dielectric thing once, workable if the volume is big enough or if you are doing a cost no object design, but the PC accessory space is (even at the high end) basically cost constrained.That big enough volume is effing huge BTW, might make sense on motherboards or something, but high end gamer graphics is niche, 0402 caps are cheap and chip shooters are fast.That said, modern prepregs are getting down to the point that some effect can be had even with standard materials.Surprised to see polymer (generally a bulk cap technology) right under the die, usually those go an inch or so away for thermal reasons if nothing else.That said, the chip carrier itself has the really HF caps on it, and this is surprisingly effective, I have a xilinx design that uses a part that does this and you can get away with fuck all decoupling compared to a part with all the caps on the PCB.

author: wraper
author_rank: Unknown
timestamp: September 26, 2020, 11:26:34 pm
content: Quote from: dmills on September 26, 2020, 11:07:19 pmThey are placed under GPU and CPU quite often, usually right under the die. In mid to high end Nvidia graphics cards they are used more often than not.

author: iteratee
author_rank: Contributor
timestamp: September 27, 2020, 06:20:17 am
content: I didn't fully realize until quite recently how large the effect of capacitor value alone on self-resonant frequency can be. Crap caps with a bunch of tiny values in parallel can be better than fewer high quality higher valued caps provided you can get enough value close to the bypassed component. I now try to simulate series inductance and parallel capacitence, not just DC ESR if I think it's critical (but it seriously complicates spice sims to the point usual convergence hacks just don't work, especially if you're already modeling transmission lines. Maybe I need to look into integrating field solvers and more sophistocated tools.)I've seen some manufacturing wider, shorter MLCCs rather than the usual long orientation in order to reduce inductance of the metal layers.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 27, 2020, 06:30:38 am
content: Note that SRF isn't, in itself, a very interesting parameter. It does not signify any sudden change in characteristics. It's just a point after which the impedance starts going up; before SRF it was going down. What matters is getting low enough impedance, and this is achievable on the both sides of SRF. Too little capacitance means impedance is high at low frequencies. Too much inductance means impedance is high at high frequencies. Thus, maximizing C and minimizing L is the design target. At some point in the low-freq side, regulator feedback loop takes over, limiting the amount of C needed. At some point in the high-freq side, power plane capacitance and on-chip bypassing takes over, relaxing the requirement for minimizing L, so there is little need to go to strange capacitor geometries or sizes below 0402.

author: iteratee
author_rank: Contributor
timestamp: September 27, 2020, 06:52:58 am
content: Quote from: Siwastaja on September 27, 2020, 06:30:38 amYes that's a dilema. Stick a less-than perfect active component in front of an ideal cap (capacitence multiplier etc) and compromize performance at some point on the high freq. side. Compensate by putting a less-than-perfect capacitor in front of that and predictable compromize ensues... and of course even if perfect, the feedback loop gets nerfed by the capacitive load plus added compromizes for loop stability.This makes me wish for a regulator that's faster than my caps, but it would leave me longing for faster caps.