CPLD / FPGA for a GPSDO? - Page 1
Forum section: electronics / general

author: cap4096
author_rank: Contributor
timestamp: February 23, 2025, 11:15:36 pm
content: Hi!I plan to create a project aiming at generating a stable 10Mhz signal as a start.I plan do create a GPSDO that can be used as base for other interesting stuff.The goal is to:* Learn VHDL* Have a useful 10Mhz clock reference.When that works:* Implement a frequency conter* Implement a frequency generator.The main idea is to create a board with a CPU + CPLD / FPGA + GPS.The board will have connectors for extension boards for other porjects as mentioned above.Do you have any suggestion what CPLD or FPGA to use? From the beginning I thought that aCPLD would be the easiest but it might be wrong. Any helpful ideas are welcome.

author: hamster_nz
author_rank: Super Contributor
timestamp: February 24, 2025, 02:37:14 am
content: Right by my desk is my current project:- a SIT5155 20MHz "Super TCXO" (don't blame me, that is what the manufacture calls it), Pull range about +/- 6ppm.- a MAX5125 14-bit DAC- in PMOD form factor.I've got it hooked to a low-end Artix-7 35T dev board, along with a very cheap u-Blox Neo-7m GPS module supplying PPS.Brief summary if the design- 20MHz from VCXO is fed through a PLL to get 200MHz- the 200MHz is used to count the PPS signal, then error is sent through a CDC to 100MHz clock domain (100MHz is not source from the VCXO)- A PI controller to discipline the VCXO - runs as a high-gain 'P'-only loop for the first 8 updates and gets very close, then switches to PI mode.- A few bits of logic to display state on the LEDs, selected by switches.Code:+--------------------------------------------+------+-------+------------+-----------+-------+| Site Type | Used | Fixed | Prohibited | Available | Util% |+--------------------------------------------+------+-------+------------+-----------+-------+| Slice | 103 | 0 | 0 | 8150 | 1.26 || SLICEL | 73 | 0 | | | || SLICEM | 30 | 0 | | | || LUT as Logic | 229 | 0 | 0 | 20800 | 1.10 || using O5 output only | 0 | | | | || using O6 output only | 204 | | | | || using O5 and O6 | 25 | | | | || LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 || LUT as Distributed RAM | 0 | 0 | | | || LUT as Shift Register | 0 | 0 | | | || Slice Registers | 386 | 0 | 0 | 41600 | 0.93 || Register driven from within the Slice | 206 | | | | || Register driven from outside the Slice | 180 | | | | || LUT in front of the register is unused | 134 | | | | || LUT in front of the register is used | 46 | | | | || Unique Control Sets | 15 | | 0 | 8150 | 0.18 |+--------------------------------------------+------+-------+------------+-----------+-------+A frequency lock is no problem, but locking phase is more challenging. The ~50ns jitter in the GPS PPS signal is currently upsetting phase lock, with some low ~0.1Hz oscillation that winds up over time, so I'm doing a bit more analysis.

author: hamster_nz
author_rank: Super Contributor
timestamp: February 24, 2025, 04:25:09 am
content: Here's a screenshot of the jitter in the PPS signalI'm triggering off of the PPS, so it looks like the 1MHz signal has the jitter, but it's the other way around...

author: PCB.Wiz
author_rank: Super Contributor
timestamp: February 24, 2025, 08:39:10 am
content: Quote from: cap4096 on February 23, 2025, 11:15:36 pmFor that you do not really need any PLD/FPGA, but a good DAC could be useful?A part like the Pi PICO can manage the measurement and phase checking, up to a quite decent 150Mhz+ PLL clocks, and some MCUs have config logic.A FPGA that was well above that ballpark, could be interesting, if you really want to add cost.

author: cap4096
author_rank: Contributor
timestamp: February 24, 2025, 12:01:44 pm
content: You could say that the main purpose of this project is to learn VHDL / Verilog and still get something useful out of it. It is more about education than a creating a product that has the lowest possible cost.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: February 24, 2025, 09:08:31 pm
content: Quote from: cap4096 on February 24, 2025, 12:01:44 pmThen I'd suggest work backwards from vendors & others evaluation boards. Get a toolchain and board you are comfortable with.You do not need many flipflops, so a moderate CPLD can do, but FPGAs are better VHDL pathways and tend to have better PLLs.eg I see Digikey haveDigiKey Part Number 1597-102991314-ND Manufacturer Seeed Technology Co., Ltd SIPEED TANG NANO FPGA BOARD $13.04, but no stock.Aliexpress have various low cost FPGA modules.The simplest GPSDO take 1pps from a default GPS module and compare with a 10MHz divided edge.Some use a long time constant analog PLL, so do not need a MCU at all.The update rate of that system is rather slow, but it is simple. You can use phase information to improve the lock time.You do not evenhaveto divide 10Mhz to 1Hz, if your 1pps captures a simple single 8 bit counter (like 74HC590), you get 25.6ppm full scale, which is enough to make lock direction decisions from.Most GPS modules can change the 1pps, so some designs increase that speed to give a faster update rate.The jitter noise floor is usually set by the GPS, which is where a higher capture clock speed has appeal. It's nice to be able to 'see' that jitter.Addit: a couple of candidates at lcschttps://www.lcsc.com/product-detail/Development-Boards-Kits_LCSC-boards-ColorEasyPico2-RP2350_C42924268.htmlPi PICO 2350 $6.01https://www.lcsc.com/product-detail/Development-Boards-Kits_LCSC-boards-LCKFB-LJPI-FPGA-G1_C41421753.html$19.74 20k gate FPGA and 120MHz MCU and Debug/jtag loader PCB and cables.Just add a DAC ?

author: iMo
author_rank: Super Contributor
timestamp: February 26, 2025, 11:15:31 am
content: I made it with the smallest ice40lp384 fpga and the stm32 bluepill (Miller XOR design, including a reciprocal counter in it) in past.PS: I would not use a PLL generated clock (ie the clock in 2040/2350 or in any other mcu) for that kind of designs..

author: PCB.Wiz
author_rank: Super Contributor
timestamp: February 26, 2025, 07:45:45 pm
content: Quote from: iMo on February 26, 2025, 11:15:31 amI'm not sure such a PLL blanket exclusion makes sense ?Certainly, you would not have a MCU/FPGA pll in the frequency reference side, but in the measurement side it would be ok.The ideal 2350 would have a VCTCXO, but the standard 'some ppm' crystal can be used for measurement, with a little care.You would use the PIO to build a dual reciprocal totaling counter, that measures 1pps and 10MHz refsimultaneously, which nulls any ppm drift/jitter on the MCU side.(certainly to much lower than the GPS correction jitter)The same approach would also be used on a FPGA, as the low cost modules also lack high performance clocks.It's hard to avoid PLLs in modern MCU, but I would side step the FLLs that count-lock a fast RC osc to a 32kHz crystal.Example work :https://www.eevblog.com/forum/projects/pico-frequency-counter-using-rp2040/msg4151122/