Signal Integrity on a 2 Layer PCB - Page 1
Forum section: electronics / projects

author: ivonenand
author_rank: Contributor
timestamp: June 06, 2015, 11:43:37 am
content: Hi guys,I've done a few designs on four and six layer PCBs (with DDR3 and similar stuff) and I know the basics of signal integrity. Now I'm doing a 2 layer PCB design and I don't really know which high-speed rules I need to follow and which I don't have to.I have a microcontroller and a SPI flash on the 2 layer PCB. The PCB is a standard 1.55mm FR4 with 35um copper. I would like the SPI to be able to run at 50MHz. My question is, can I run a trace under a SPI signal, or must there always be a solid ground beneath the SPI traces, like with multi layer high speed PCBs? Would that have an impact on the speed at which the SPI can run, or it wouldn't matter since the board doesn't have impedance matching anyway?Regards,Ivo

author: nctnico
author_rank: Super Contributor
timestamp: June 06, 2015, 01:11:56 pm
content: I'd use series 33 Ohm resistors in the lines (at the driver side) to dampen ringing and make sure there is a solid ground plane under the SPI lines or at least ground planes stitched together on the top and bottom which form a low impedance return path. Keeping the traces as short as possible also helps a lot.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 06, 2015, 01:26:03 pm
content: How long is the trace? What are the pin characteristics (can it actually drive at 50MHz?)?Consider the board in its virgin state, full copper both sides. Now run a trace. You must remove clearance around the trace, so that the same-side pour becomes divided around the trace. This makes a coplanar waveguide structure. As long as the top and bottom grounds are well stitched with vias (every couple cm or so?), the impedance will be reasonable. Typical trace width and clearance (say 10 mil / 0.25mm) gives an impedance around 100 ohms.The pin driver might be 20-60 ohms already, so an additional 40-80 ohms in series with the driving pin should give reasonable source-terminated results, even for long traces.Consider the intersection of two traces. Each is surrounded by split plane on the same side, and full plane on the other side. Obviously, they must cross on opposite sides. So one crosses over the split from the other, and likewise. Place vias near the intersection, to stitch over that crossing and minimize induced voltage between the plane splits.Consider traces routed beneath an IC. The IC footprint contains a row of pads which necessarily is not solid ground. Traces running underneath therefore are "unsupported" by ground, and need more stitching (if possible). If there are many traces already routed on the top side, there may not be any ground near any of them, which is a bad condition: this gives a high impedance to ground (locally), and high crosstalk (a greater proportion of the impedance of a given trace is due to the impedance to its neighbors).Generally speaking, where you have the intersection of top side footprints or routing, and bottom side traces, you should minimize the un-grounded area that is formed by the negative space of those objects. Groups of traces can be arranged in a bus, and buses made to cross at right angles, to maximize grounded area and minimize crosstalk between buses (but this will also maximize crosstalk within a bus, so be careful).All of these factors only matter for frequency components with wavelength on the order of the length of the features. If the pin rise time is greater than 1ns, and un-grounded lengths are less than 5cm or so, then very little of that ramp will end up coupled between traces, or show up as humpy-spiky impedance mismatch effects.Tim

author: John_ITIC
author_rank: Frequent Contributor
timestamp: June 07, 2015, 11:35:58 pm
content: As long as any reflections caused by impedance mismatch dies out before the signal is clocked you can ignore signal integrity. For a low-cost or hobby board that runs signals in the 50 MHz range I would not worry too much about signal integrity.To answer your question; if the SPI signal return ground has to take a detour such that it cannot run right under the original SPI signal then you will introduce a longer return path and increase the loop inductance of the path. This will somewhat degrade the SI but I would bet you that at 50 MHz it is not too much to worry about.I would route the board as good as I possibly can using the PCB technology limitations imposed, simulate the SI on the various nets and see whether there are any paths that need to be adjusted. Trying to mentally cover all the bases is simply impractical.

author: tggzzz
author_rank: Super Contributor
timestamp: June 08, 2015, 12:55:16 am
content: Quote from: ivonenand on June 06, 2015, 11:43:37 amThe frequency is irrelevant. All that matters is the transition time and the length of the traces. If the transition time is greater than 6 times the propagation time (assume 0.66*300e6 m/s), then it should appear as a lumped circuit not as a transmission line.

author: John_ITIC
author_rank: Frequent Contributor
timestamp: June 08, 2015, 04:44:05 am
content: Quote from: tggzzz on June 08, 2015, 12:55:16 amIn practice the frequency IS relevant because if the reflections caused by the high frequency content in the fast rise/fall times have died out before the next clock cycle arrives the reflections are benign. knowing this may avoid over-design in terms of proper transmission line design and termination when using not-so fast clock frequency.

author: tggzzz
author_rank: Super Contributor
timestamp: June 08, 2015, 08:25:43 am
content: Quote from: John_ITIC on June 08, 2015, 04:44:05 amYou are confusing cause and (visible) effect.In addition, there are two problems with that:even if you only have a 10kHz clock then the logic will still be capable of responding "incorrectly" to the non-standard transients at clock/signal edgesdepending on their amplitude and time delay, the transitions may well be causing signal/clock voltages outside the inputs or outputs specified voltage range. Depending on the logic family, that can cause subtle logic errors and/or premature device aging (typically through exceeding the maximum current though clamp diodes)So, while it may be most easilyvisibleon fast clock signals, problems occur at transitions - and the transition time vs line length is what counts.

author: John_ITIC
author_rank: Frequent Contributor
timestamp: June 08, 2015, 05:54:57 pm
content: Quote from: tggzzz on June 08, 2015, 08:25:43 amNo, I'm not confused. All I'm saying is that if the reflections have died out such that the signal is at the correct and valid state before it is needed (i.e. before the clock comes along) then the reflections on the data signals between the active clock edges do not matter. Note that in the SPI example, the clock signal must not have reflections that causes double-clocking or the like. And, of course, Maximum and minimum input voltages should not be exceeded but that is largely handled by clamping diodes on modern devices.So in short, for hobby projects I would not worry too much about SI on a 50 MHz SPI bus. For a professional project, I would simulate the SI after implementing the non-terminated design. If sim results show reflections then I would worry about spending time on designing in proper terminations etc.

author: tggzzz
author_rank: Super Contributor
timestamp: June 08, 2015, 06:04:18 pm
content: Quote from: John_ITIC on June 08, 2015, 05:54:57 pmAnd such double-clocking, if any, is not related to the clock frequency.Similar issues could, of course, arise where signals are not synchronised to any clock.QuoteAt which point we're back to my previous point about logic family, track geometry and premature aging.Note that older logic families are likely to have slower transition times and therefore be less prone to reflections in the first place.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 08, 2015, 11:15:21 pm
content: Since we're talking SPI specifically, the hazard is entirely CLK. Data reflections can probably be completely ignored, as long as the run isn't grotesquely long (meters). SPI devices can often be clocked by runt pulses in the 100MHz+ equivalent range, certainly high speed capable devices. The clocking is very likely to be incomplete and glitchy, leading to incorrect data or corrupted internal states.Therefore, regardless of overall clock speed, clean signal quality on the SCK pin is a requirement.Tim

author: John_ITIC
author_rank: Frequent Contributor
timestamp: June 09, 2015, 12:10:16 am
content: Quote from: ivonenand on June 06, 2015, 11:43:37 amSo to answer the original question; no, crossing power plane splits will not cause trouble for a slow signal like SPI. As concluded by others, I would take some care to properly terminate the clock signal - that's about it.