Gain Problem in subharmonic upconv mixer  - Page 1
Forum section: electronics / rf-microwave

author: bandw
author_rank: Newbie
timestamp: March 15, 2018, 02:16:47 pm
content: i am trying to design a 2 x subharmonic upconvertor mixer.LO=-15dbm @ 32.5 ghzRF= -30dbm @ 25 ghzIF = 40 Ghzi am not getting any gain...? why ?also i have the problem of RF feed through.. i understand it would feed through due to single balanced nature of the toplogy , but its higher power than the required IF.lower stage is LO and upper is RF/mixer...all the ports are properly matched

author: bandw
author_rank: Newbie
timestamp: March 15, 2018, 02:18:19 pm
content: Quote from: bandw on March 15, 2018, 02:16:47 pm

author: whollender
author_rank: Regular Contributor
timestamp: March 15, 2018, 04:27:12 pm
content: I'm not surprised your getting so much feedthrough with no filtering on the output.I'm not really familiar with this topology, but I'd guess that you're not hitting the LO inputs hard enough to switch, so you're effectively just amplifying the RF.

author: bandw
author_rank: Newbie
timestamp: March 15, 2018, 05:29:57 pm
content: Thankyou for your reply.all the ports were impedece matched.. so i thought filter should not be required.. anywaysI have designed the output filter.. but since IF bandwidth is 40-50 Ghz .. and RF 20-35 Ghz ...quite near to IF..the filter comes out to be of 12 order for good operation.. i had not connected it to the output.. but yes when i do ..i get good RF rejection.. below 100dbm..but my main concern is the IF conversion gain... the IF is too loo..i dont understand why i am not getting gain.. .. all the transistors biased in active forward.. near to transit frequency.. and 13db smalll signal (s21) central frequency (for both lo and Rf..) gainthe toplogy.. is simple actualy.. the lower part is LO doubler kinda but in subharmonic mode.. .. and the upper is simple mixer. ...and IF=2LO-RF... and all the ports are impedence matched.i am not sure ,, how much more i can pust the Lo power.. (attached)with filter in place ..and rf=-30dbm and lo=0dbm (find output spectrum attached)

author: whollender
author_rank: Regular Contributor
timestamp: March 15, 2018, 06:10:44 pm
content: Again, I'm not totally familiar with this topology, but it looks to me that if your LO is in the small signal regime for the lower diff pair, then the bias current to the upper pair won't change. In that case, you just have a differential gain stage for your RF input, which explains the ~10dB of gain you're showing in your second plot.If you hit the bottom pair with a high power LO, however, then you'll end up pulling pulses of current through the upper pair, with two pulses for each LO cycle (hence the x2 operation). That will then multiply the RF signal, and you'll get your 2xLO - RF signal.

author: bandw
author_rank: Newbie
timestamp: March 16, 2018, 04:40:50 pm
content: Thankyou for your reply..i think you are right.. the lower portion ... a common collector push push dobler is not biased properly...after reading through some papers i came to know that i need to bias it in CLASS B operation...i have never done that kind of biasing.. after seracing a lot on the web also,, there is not some good biasing info available..can you please tell me ..if upper portion needs 8mA individually( total 16mA) .. and if Vbe=900mV.. and Beta=450 .. what should be the collector ,emmiter and base voltage or base current for CLASS B operation.?. .. where exactly do i need to bias it ? on the graph of Ic vs Vce .. do i need to bias it at the knee voltage just before Ic saturates.. or .. near cut off.. ?

author: whollender
author_rank: Regular Contributor
timestamp: March 16, 2018, 04:57:10 pm
content: You would want to bias the transistors close to cut-off, because each should be off for at least one half of the LO cycle.It seems to me that this would work well with no real bias voltage on the base of the bottom pair. This means that each transistor would only conduct during the positive half cycle that it sees on its base.This means that your DC results will not show any bias current, but you can figure out the top pairs bias conditions with one of the bottom transistors forced high to approximate what will happen when it's driven high by the LO.