I need a sanity check on a memory copy circuit. - Page 1
Forum section: electronics / projects

author: MarkS
author_rank: Unknown
timestamp: August 12, 2023, 07:54:43 pm
content: I'm working on a simple 80x30 character VGA circuit to be used on my various retro computer projects. In my never ending quest to be a masochist, I'm designing a memory copy circuit to copy the font bitmap from "slow" (55ns) Flash to fast 10ns SRAM without the use of a microcontroller. This will run once on power up. This has actually been a very fun and enjoyable rabbit hole to go down. I *think* my logic is sound and this *should* work, but I have some lingering doubts. I'm basically relying on the propagation rate and stability of the 4-input AND gates to bring the relevant control lines high and hold them there until power off.As I have it laid out, the 555 timer holds the 74xx4040 timer in a reset state for 3ms to allow for the rest of the circuit to stabilize. It then drops the reset line and the counter counts through the 12-bit address range. The control lines are pulled low though R3. It's zero Ohms in the schematic due to me not knowing what value it should be. My intent is to prototype this circuit and determine it's value through experimentation. With the control lines low, the bitmap is placed on the data bus, byte by byte, and copied to the SRAM. U5, U6 and U11 are there to isolate the counter and Flash from the circuit when the AND gates go high. The latches, U7 and U8, are to hold the AND gates high when the address bus reaches 0xFFFFFF. At this point, the Flash is disabled, the counter is blocked from the circuit and the SRAM is placed into read only mode via its WE pin.I think this should work. Is there anything I should consider in this circuit or any problems that immediately jump out?

author: MK14
author_rank: Super Contributor
timestamp: August 12, 2023, 09:07:23 pm
content: I apparently see possible problems. But I could be mistaken.Examples:What are you expecting to pull diode D2, down to ground (D1 would block any attempt to do so)?Leaving the write line, always enabled while you sequence through all the addresses, may cause data corruption, because of logic switch transitions, race hazards and things like that. It needs to be properly controlled, and switched off (disabled), after the write, otherwise transitioning address lines, could corrupt all sorts of addresses, as they switch.I don't particularly like your diode logic arrangement. With its extra voltage drops, and other possible issues. Why not just use other logic gates and things, like the rest of the circuit?

author: MarkS
author_rank: Unknown
timestamp: August 12, 2023, 09:12:11 pm
content: Quote from: MK14 on August 12, 2023, 09:07:23 pmD1 prevents the 555's output from being back fed when the control line is held high via the AND gates (not sure this is necessary) and D2 prevents the 555 from driving the control lines high during power up. They are very low drop out diodes, around 200~mV each.The write signal issue may be problematic. I'll have to dig into the datasheet. I could gate it to the 10 MHz crystal. Hmm...

author: MK14
author_rank: Super Contributor
timestamp: August 12, 2023, 09:25:03 pm
content: Quote from: MarkS on August 12, 2023, 09:12:11 pmI agree, I misinterpreted, the diode situation.With such a fast SRAM, at 10ns, it could easily react to counting transitions on the counters, and other logic transition/delay effects. So, I'd be surprised, if it worked as shown.I'd expect, as you said, possibly connected to a clock, such as the 10MHz, if it leaves enough time overall, per cycle. To enable the write, give it enough time to reliably get and store the information at that address. Then disable the write, give it enough time to register, then allow the next clock pulse to advance the address counters again.I.e. Write should not be enabled, until the address lines have had enough time to fully stabilise and reach the SRAM (otherwise the wrong address could be written to/corrupted), then enable the write, for long enough. Finally remove the write enable signal, to ensure the next address line transitions, don't cause any corruption.It is tricky to describe it in words, but I hope you get the idea.

author: MarkS
author_rank: Unknown
timestamp: August 12, 2023, 09:46:55 pm
content: Quote from: MK14 on August 12, 2023, 09:25:03 pmNo problem. I figured there would be questions as to their use.Quote from: MK14 on August 12, 2023, 09:25:03 pmI may swap out the transceivers for latches. This would stabilize the counter output as well as provide the same blocking functionality of the transceivers. The counter is run via a 10 MHz crystal. This is 10x slower that the SRAM access time and 1.8x (?) slower than the access time of the Flash. I think I can fix this with aNOROR gate... Give me a bit...Quote from: MK14 on August 12, 2023, 09:25:03 pmI completely understand you and thank you!

author: MarkS
author_rank: Unknown
timestamp: August 12, 2023, 10:01:24 pm
content: I think this might do it... (Download to view full size)

author: Benta
author_rank: Super Contributor
timestamp: August 12, 2023, 10:04:52 pm
content: The first thing to throw in the garbage is the 4040 counter. NEVER use ripple counters for this kind of thing. You'll have runt pulses all over the place.Only synchronous counters, please (yes, it'll probably increase the device count).When that's fixed, show us the design again.

author: MarkS
author_rank: Unknown
timestamp: August 12, 2023, 10:08:46 pm
content: Quote from: Benta on August 12, 2023, 10:04:52 pmI've been debating that. I like the simplicity of the single chip, but I think you're right.

author: Benta
author_rank: Super Contributor
timestamp: August 12, 2023, 10:23:27 pm
content: The 74HC590 with CCLK and RCLK tied together might save the situation. Yes, two ICs instead of one, I know.

author: MarkS
author_rank: Unknown
timestamp: August 12, 2023, 11:09:40 pm
content: Quote from: Benta on August 12, 2023, 10:23:27 pmThat's an asynchronous counter. What's the difference between that and a synchronous counter?

author: Benta
author_rank: Super Contributor
timestamp: August 12, 2023, 11:46:51 pm
content: Quote from: MarkS on August 12, 2023, 11:09:40 pmGood question and to the point.The 74HC590 is a "bastard" that's no better than the 74HC4040 as a counter.But it has an output register that (when used correctly) makes it behave like a synchronous counter.The fully pure synchronous solution would be using 74HC161/3 or 74HC191/3, but that would take three ICs instead of two.

author: MarkS
author_rank: Unknown
timestamp: August 13, 2023, 12:05:43 am
content: Quote from: Benta on August 12, 2023, 11:46:51 pmIf that's the case, wouldn't the 4040 with latches on the outputs work the same?

author: Benta
author_rank: Super Contributor
timestamp: August 13, 2023, 12:08:16 am
content: Quote from: MarkS on August 13, 2023, 12:05:43 amYes it would.

author: MarkS
author_rank: Unknown
timestamp: August 13, 2023, 12:10:06 am
content: Quote from: Benta on August 13, 2023, 12:08:16 amThat's what I did in the revised schematic I uploaded. I replaces the 245's with latches. They separate the counter from the rest of the circuit when I need them to and stabilize the counter's outputs.

author: Benta
author_rank: Super Contributor
timestamp: August 13, 2023, 12:23:45 am
content: OK, that's a good approach. I'm not able to comment on your schematics directly, as they're unreadale (far too low resolution).Two suggestions:Use PDFs, they scale better.Use buses. Makes the schematic more readable, but that's secondary.

author: MarkS
author_rank: Unknown
timestamp: August 13, 2023, 12:24:53 am
content: Quote from: Benta on August 13, 2023, 12:23:45 amIt's the forum software. If you download the image, it will be perfectly clear. The forum will not show it full sized for some reason.

author: Benta
author_rank: Super Contributor
timestamp: August 13, 2023, 12:42:30 am
content: Yep, downloaded it and can read it now.Soo....4040 + 2x 373. Could also be 3x 161/191. Or 2x 590.Said differently:16-pin + 2x 20-pin. Or 3x 16-pin. Or 2x 16-pin plus "stop count" logic.That's just the address counter.I haven't looked at the rest yet.

author: MarkS
author_rank: Unknown
timestamp: August 13, 2023, 01:50:56 am
content: Quote from: Benta on August 13, 2023, 12:42:30 amYes, you're right. I have to do a major redesign anyway, so I might as well use the two 590's. And, I'm changing over to buses. No idea why I didn't do that in the first place!

author: MarkS
author_rank: Unknown
timestamp: August 13, 2023, 03:17:57 am
content: I think this may work.

author: MK14
author_rank: Super Contributor
timestamp: August 13, 2023, 03:54:35 am
content: Quote from: MarkS on August 13, 2023, 03:17:57 amUnless I'm missing something. I can't see anything, on the new layout, after diodes D1 and D2, to reliably and quickly pull the pins they connect to (output and chip enables, etc), to ground, when necessary.I don't think, at a somewhat quick glance, the 10MHz clock, would be slow enough to allow for reliably meeting some of the datasheet timing specifications. E.g. The flash seems to be 55ns, but 10MHz, is (100ns for a complete high and low cycle) 50ns between transitions.At a quick glance, 50ns also seems too short a time, to allow the counters and logic, to work, reliably to the datasheet specifications. Layout, wiring method, (stray capacitance), exact models of chip (including manufacturer), etc, also can change the final timings.Consider that in the worst case, it will have to (carry) ripple through all 8 flip flops, get into the latches and then go through the output buffers.Although at a glance the maximum clock frequencies may look promising (not that promising really). If I understand things correctly, you need it to do everything, in just one half, of the clock frequency, so it is ready for the SRAM to register those addresses, in the second half of the clock cycle.I've stopped my analysis, for now. But I'm also worried about the gate for the write enable. There could be glitches (and other types) of effects, as the address lines change. I hope not.There are ways of making it, so that more reliable control of that write enable pin (although you seem to have improved it, in your circuit), with little or no risk of glitches and such issues.Edit: Also, when the first counter uses its carry out (RCO), to clock the second counter, there will be a significantly longer (perhaps around 50ns), overall extra delay. Which needs to be taken into account, when choosing the maximum (safe) clock frequency, for the configuration, you have supplied.

author: gnuarm
author_rank: Super Contributor
timestamp: August 13, 2023, 05:39:15 am
content: Quote from: Benta on August 12, 2023, 10:04:52 pmThere is absolutely nothing wrong with using ripple counters. In fact, if you are decoding a terminal state to reset the counter, it will never mistrigger. To understand why, you have to consider that all false states it will run through, will be lower values than the state being detected. In the end, this is actually a big advantage when designing with SSI/MSI logic.But this entire design seems overly complex. It would seem this is one of those, "I insist on using ancient technology" designs. I don't see how this can even be useful, since the data from the RAM and the Flash connect to nothing else in the universe. This can't even be a design that connects to another schematic page by signal names, because the data bus signals have no specified names.

author: gnuarm
author_rank: Super Contributor
timestamp: August 13, 2023, 05:54:25 am
content: Quote from: MarkS on August 12, 2023, 11:09:40 pmIn a synchronous counter, the clock signal goes to all the FFs in the counter and each FF is controlled by logic.In an asynchronous counter, the clock only goes to the least significant counter, and the falling edge of the output of that counter triggers the next counter. So the outputs will change one at a time, like a ripple running up the line.The only real difference is that the synchronous counter has a shorter settling time (everything else being the same). The async counter requires a delay for each output stage that is changing. If you don't care about the time, there's not much difference in use except for one case. You can decode any value of the asynch ripple counter with random logic to reset the counter, and it will never glitch.This can be done with the synch counter as well, but it can produce glitches if any other logic is using this same signal. Except for a few special cases, outputs of synchronous counters must only be used in synchronous logic.

author: gnuarm
author_rank: Super Contributor
timestamp: August 13, 2023, 06:36:26 am
content: Quote from: MarkS on August 13, 2023, 12:10:06 amYou don't need to stabilize the counter outputs through FFs. The HC4040 counter you've selected is rather slow. The delay from the input clock to the last output changing is (at 5V and 25°C) 250 ns max. That's two and a half cycles of a 10 MHz clock!!!I can't follow the logic behind the latches and gates. You can do this with zero latches, one small counter and just a few gates to produce the timing signals required.The small counter can run only using the lowest 3 bits. You will need to use a counter that is a bit faster than HC logic, or you need to slow your clock. Q2 can be used to allow for the 4040 counter to settle and to clock it. The 4040 counter is active on the falling edge, so counts 0 to 3 are "idle time". You need a signal for the WE- on the AS7C256A RAM. That can be decoded as Q2 high and Q1 low. This will need to be run through a FF, such as a '74 part, a register, not a latch. This register will delay the WE- signal by one master clock, so it will be active at count 5 and 6.Your 4040 counter will still need to be decoded to stop the circuit, or... you can add a FF at the beginning of the counting chain as the lsb, and use output Q11 on the counter as the DONE flag. Heck, this can be a bit in the small counter! This STOP signal will feed the enable on the small counter to stop it counting and let the circuit operate normally, whatever that is. Oh, the 555 timer can be replaced by a simple capacitor and pull up resistor like you have on the reset to the 555 timer. Run it through a logic gate with a Schmitt trigger input like a 74HC14, to give a clean edge.So, instead of the dozen or so chips you have, you need an oscillator, the reset gate, the small counter, the big counter a couple of FFs and gates... did I miss anything?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 13, 2023, 07:11:25 am
content: Why so many buffers?I would just connect the two memory IC's directly to each other and toggle a few control lines with a microcontroller. Maybe keep only the 4040 if the uC does not have enough I/O pins. With an uC it's so easy to change how the circuit works and manage timing.Then I read your text:Quote from: MarkS on August 12, 2023, 07:54:43 pmIn that case, just keep on flogging yourself until your circuit starts working.There are simulators for digital logic that also help with timing verification.

author: gnuarm
author_rank: Super Contributor
timestamp: August 13, 2023, 07:30:02 am
content: Quote from: Doctorandus_P on August 13, 2023, 07:11:25 amUsing a simulation to verify timing is a terrible idea. They really are not remotely designed for that... unless you mean timing of clocking on the wrong edge of a pulse.

author: electronsandstuff
author_rank: Newbie
timestamp: August 13, 2023, 11:14:59 am
content: 100% fine to use a ripple counter directly for the addressing here and you don't need to make the thing synchronous.What you do is strobe the memory write out of phase with the address clock. That way the address lines are stable when the data-transfer occurs. Just beware that the sum of all of the ripple stage delays will put an upper limit to the maximum clock rate.Honestly, this isreallybasic stuff.You don't need all of that decoding to detect FFF either - just terminate on overflow.And if you must insist on keeping the FFF decoding, you DO NOT need a F^%$ING DFF on every address input line. You de-glitch with a SINGLE DFF at the output of the decoder.Again, this isreallybasic stuff.No slight on you as you appear to be a newbie, but some of the "engineering" advice you've been given here is eye-rolling.

author: Benta
author_rank: Super Contributor
timestamp: August 13, 2023, 11:33:23 am
content: Quote from: gnuarm on August 13, 2023, 06:36:26 amOr in this case 25 totally random accesses to the SRAM. I don't want to think about what it contains after that.

author: MK14
author_rank: Super Contributor
timestamp: August 13, 2023, 11:38:30 am
content: Quote from: Benta on August 13, 2023, 11:33:23 amIts contents will be fine, as long as the write enable pin(s) are kept disabled (high), during these signal transitions.

author: gnuarm
author_rank: Super Contributor
timestamp: August 13, 2023, 02:05:40 pm
content: Quote from: Benta on August 13, 2023, 11:33:23 amYou don't seem to understand the RAM only writes when WE- is low. The WE- signal must be timed when the RAM address is stable. There is no way around this, so it's surprising you don't understand it. Or maybe you didn't actually read my post thoroughly. It's not easy to describe a schematic.

author: Benta
author_rank: Super Contributor
timestamp: August 13, 2023, 06:32:49 pm
content: Quote from: gnuarm on August 13, 2023, 02:05:40 pmDon't worry about my understanding. I know exactly how a SRAM works.Like I wrote, I haven't looked at the rest of the circuit.And I hate ripple counters. They introduce unexpected problems and issues that are easily prevented using synchronous design. They were designed in a time when CMOS technology was at a 10 um (TTL more like 20 um) node and every transistor took up significant space on the die.No longer the case.

author: gnuarm
author_rank: Super Contributor
timestamp: August 13, 2023, 08:55:46 pm
content: Quote from: Benta on August 13, 2023, 06:32:49 pmYou can wave your arms all day about ripple counters, but other than being slow, they present no issues that synch counters don't also have. You keep making these claims, but never back them up with any examples. So, I have no reason to believe you, nor does anyone else, especially after your comment on the RAM.This is simple enough. Please just explain to us what the problems are with using ripple counters.

author: Benta
author_rank: Super Contributor
timestamp: August 13, 2023, 09:57:47 pm
content: Tone down, this is not Twitter/X or Truth Social.If you like using ripple counters, fine. Do it. Not my problem.But if you like to know how to do it right, it'll cost you around $30:https://www.amazon.com/Engineering-Approach-Digital-Design/dp/B001947XOCI can post designs here until I'm blue in the face, but your 'tude tells me it wouldn't help.

author: MarkS
author_rank: Unknown
timestamp: August 14, 2023, 12:07:36 am
content: Please stop the argument. Nothing is gained from it. I'm working on a redesign and will post shortly.

author: gnuarm
author_rank: Super Contributor
timestamp: August 14, 2023, 12:11:36 am
content: Quote from: Benta on August 13, 2023, 09:57:47 pmThe only 'tude, is about the fact that you can't support your claims. I understand. Once you make a wrong statement, it's hard to admit it.

author: MarkS
author_rank: Unknown
timestamp: August 14, 2023, 01:17:07 am
content: Quote from: MarkS on August 14, 2023, 12:07:36 am

author: BrianHG
author_rank: Super Contributor
timestamp: August 14, 2023, 01:28:49 am
content: if you know how to program a PIC microcontroler, get a 40Mhz or 80Mhz pic to replace your 555 and bolean logic.A simple assembly code will get you 10MHz counting performance with the mid-tier 3$-4$ PIC microcontrolers.IE, the pic should reset your 4040s/590s, count them, provide a clock cycle delay to allow the 4040's/590s->source ram output data valid outputs to stabilize and then use another output for driving the write enable.A spare IO ports on the PIC can feed the upper MSB address of your source and destination memory, separately, so you can copy 1 bank to another. You will also be able to copy in the other direction with just an additional trace.A tiny code written in assembly should do it and you can software count the addresses you want to copy, selectively choosing the start and end address depending when you software choose to assert the WE.Debounced buttons and LED display can tell you when the copy is done.Also, you can time for eprom writes and check the data bus for write verify.Also, unless you are running with and translating different VCC voltage levels, all you need is the PIC and a pair of 74HC4040s, none of the other buffers 245/374/574 are needed. Direct wiring is permitted.

author: BrianHG
author_rank: Super Contributor
timestamp: August 14, 2023, 01:51:35 am
content: Note that if you use a PIC with enough IO ports, or even one with a 16bit IO port, you can skip the counters as well.

author: gnuarm
author_rank: Super Contributor
timestamp: August 14, 2023, 02:00:36 am
content: One point I haven't see mentioned at all, is that there is no access to either the RAM or the PROM from outside this circuit. Without that, it is of no value. The details of how that circuit works, will likely have a major impact on this circuit.

author: MarkS
author_rank: Unknown
timestamp: August 14, 2023, 03:42:09 am
content: Quote from: gnuarm on August 14, 2023, 02:00:36 amThis is a subcircuit of a larger VGA board I'm working on. The address and data lines of the SRAM will have connections on the completed board.

author: gnuarm
author_rank: Super Contributor
timestamp: August 14, 2023, 04:37:49 am
content: Quote from: MarkS on August 14, 2023, 03:42:09 amSo anything touching the SRAM will need to be connected through tri-state buffers, no?

author: tychob
author_rank: Contributor
timestamp: August 14, 2023, 09:31:02 am
content: Quote from: BrianHG on August 14, 2023, 01:28:49 amQuote from: MarkS on August 12, 2023, 07:54:43 pmNot using a microcontroller was a requirement for the circuit. Likely out of desire for the process rather than just whatever circuit would deliver the end result fastest, as for most cases in retrocomputing, you could deliver the system faster, cheaper and more capably by emulating on a cheap SBC like a pi. Which then wouldn't need a circuit like this at all as you would just emulate the video output.

author: BrianHG
author_rank: Super Contributor
timestamp: August 14, 2023, 03:08:31 pm
content: The 555 is still a weird solution for dealing with high speed digital logic.Still not sure what the copy is for as the ram you have is so fast, it can be shared between 2 busses simultaneously.Also, true dual-port static ram also exist.

author: tychob
author_rank: Contributor
timestamp: August 14, 2023, 04:01:08 pm
content: Quote from: BrianHG on August 14, 2023, 03:08:31 pmThe copy is to get the data into fast ram. The data lives in the flash, which is slower.

author: MarkS
author_rank: Unknown
timestamp: August 14, 2023, 05:55:26 pm
content: Quote from: tychob on August 14, 2023, 04:01:08 pmThis!Quote from: BrianHG on August 14, 2023, 03:08:31 pmThe 555 WAS used to create a short delay to freeze the timer while the memory stabilized. I've removed it in the current revision.Dual port RAM exists, but 1.) that's not the issue and 2.) they are UNGODLY expensive!Quote from: tychob on August 14, 2023, 09:31:02 amYes! You get it! This is about the journey, not the destination. I'm not adverse to microcontrollers and have used them extensively in the past. The thing is, if I use one, I know what the firmware is doing, but not what the actual chip is doing. I can implement this entire circuit in about a dozen or so lines of code. But, I know how to program microcontrollers and interfacing with them is rather easy. I've learned TONS just with this post alone!

author: MarkS
author_rank: Unknown
timestamp: August 14, 2023, 07:53:48 pm
content: Quote from: gnuarm on August 14, 2023, 04:37:49 amPossibly. I'm not at that point yet. In fact, this is the very first and only part of the VGA circuit I've designed.

author: gnuarm
author_rank: Super Contributor
timestamp: August 15, 2023, 02:18:22 am
content: Quote from: BrianHG on August 14, 2023, 03:08:31 pmWhile dual ported RAM exists, it gets rather expensive.I agree that the 555 timer is an odd bird, but more so, it's a result of poor thinking. This circuit has to proceed through a number of states. The 555 timer is not needed for that. It seems the OP is of the opinion, that like some analog circuits, digital circuits need time after powering up to "settle". That's what the 555 timer is doing. Then he compounds the error by using diodes in place of a logic gate.This design is a result of thinking about a tiny piece of the design at one time and adding a chip or two to solve the issue at hand, lather, rinse, repeat.I don't really know what devices are allowed in this design and which are prohibited. We have insufficient info to actually design a circuit, because a large piece of the circuit is missing, along with the requirements for that piece.It's hard to design in a vacuum. Maybe one day, we will find out what this circuit really needs to do.

author: MarkS
author_rank: Unknown
timestamp: August 15, 2023, 02:21:30 am
content: New design. I've been working on a LED matrix display circuit to show the RAM contents (for prototyping purposes), so pardon the delay. I realized that wasn't pertinent to the discussion, so here's the copy circuit.The major changes are obvious. I reduced the oscillator to 1 MHz which is plenty to account for memory timings and at 1 MHz, not accounting for propagation delay, the total time for the copy would be measured in microseconds. That's plenty fast. The single 74xx4040 has been replaced with two 590's. This had the added benefit of simplifying the control logic. Now, when the counter goes from 0xFFFFFF to 0x0000001, a D-flip flop is triggered which shuts off the timers and flash. The SRAM WE pin is connected to the clock. This is so that when the counter is counting (high clock pulse), the WE pin is high, ensuring enough time for the address to stabilize. When the clock goes low, the timer holds it's value and the WE pin enables the SRAM to write the data on the data bus. Note: I just realized that I need to gate the clock signal to the WE pin so that WE is held high once the copy is complete...Overall, much cleaner and far more simplified.

author: MarkS
author_rank: Unknown
timestamp: August 15, 2023, 02:34:38 am
content: Quote from: gnuarm on August 15, 2023, 02:18:22 amSorry about that. It's really simple. The VGA controller I'm designing will emulate an old school text based terminal. This SRAM chip will contain all of the character bitmaps and will be accessed by the VGA circuitry to convert the character stored in the system accessible "video" (really character) memory into a screen image. This SRAM chip will be isolated from the system bus. The addressing of this chip is such that the first 8 bits of the address correspond to the ASCII character and the last 4 bits correspond to the 16 rows of bitmap data for that character. The byte placed on the data bus will be the image data (1-bit per pixel) for that row.My reasons for posting this subcircuit was simply to make sure that it would work and to make any corrections to the design. To that end, thank you all for the assist!

author: Kim Christensen
author_rank: Super Contributor
timestamp: August 15, 2023, 03:57:52 am
content: Quote from: MarkS on August 15, 2023, 02:21:30 amCouple of thoughts:Is the Q output of the 74LVC1G79 guaranteed to be low on power on? I don't see anything in the datasheet about that.You've tied OE of the as7c256 low... This means the RAM's data buss lines will be outputs whenever WR goes high. This will cause buss contention with the EPROM chip during the copy phase.You'll also need pullup resistors on the data buss lines once you tie the OE pin of the as7c256 high.

author: gnuarm
author_rank: Super Contributor
timestamp: August 15, 2023, 04:34:07 am
content: I can't see any value in commenting further on the present design, because it is incomplete. The design has to provide a means of external access for normal operation. Trying to work out the detail timing of this circuit is pointless, since the other interface will greatly impact both the design and the timing.The OP needs to recognize this and learn how to do design work, rather than just sticking chips together.This is what I was talking about in a previous post. What he is doing right now, is painting himself into a corner, again, and again, starting over each time.

author: MarkS
author_rank: Unknown
timestamp: August 15, 2023, 06:27:23 pm
content: Quote from: Kim Christensen on August 15, 2023, 03:57:52 amThat is the purpose of the pull down resistor R1, although ignore it's value. I copied another resistor and didn't change the value.Quote from: Kim Christensen on August 15, 2023, 03:57:52 amOh, good catch! I totally missed that! That would have been a nasty bug to find and fix!Quote from: Kim Christensen on August 15, 2023, 03:57:52 amWhy exactly?Quote from: gnuarm on August 15, 2023, 04:34:07 amYou're not wrong, but that is also not helpful. You're trying to figure out the timing of the whole VGA circuit, and while I can understand that, once the copy is complete the SRAM is disconnected from this circuit and connected to the VGA circuit. While this is running, the VGA circuit will be disabled. Point being, we can focus on the timing requirements of this circuit separately from the entire VGA circuit. Yes, the SRAM will need timing and interfacing done. But not here. If you don't want to help, that is your prerogative. Perhaps you can better explain to me your concerns. It's obvious I'm a novice. Maybe I'm not understanding your concerns?

author: Kim Christensen
author_rank: Super Contributor
timestamp: August 15, 2023, 06:53:07 pm
content: Quote from: MarkS on August 15, 2023, 06:27:23 pmThat won't work. The Q output of the 74LVC1G79 will override the pull down resistor upon power on. Q will be undefined. But don't take it from me:Read this TI guru FAQ/forum post.QuoteBecause when the RAM's CE & OE pins go high, it's data lines change to high impedance mode (floating). Your EPROM data outputs will also be high impedance at the end of copy when it's OE & CE go high. Then the data buss lines will be floating hi-Z. This is because you can have multiple devices on a bidirectional data buss and can only have one talker (outputs) at a time. Kind of a normal old-school data buss configuration to have pull ups.

author: gnuarm
author_rank: Super Contributor
timestamp: August 15, 2023, 07:25:23 pm
content: Quote from: MarkS on August 15, 2023, 06:27:23 pmIt's not helpful, because you don't understand the implications. When you try to attach this circuit to the rest of the design, this circuit will need to change significantly.I would suggest that you design the VGA circuit, with the knowledge that you will need to initialize this small portion of the RAM. It is very likely, that you can find a way to initialize the RAM with little interference. In fact, I have an idea in mind, that might involve nearly no additional logic at all. But that can't be determined, until the rest of the circuit is known.In essence, I think you are putting the cart before the horse. Or maybe you should at least design the cart and horse together.QuoteI know what you are doing. Keep in mind that you are looking at the building one brick at a time. I have designed similar circuits and can see the entire building at once, because I already know the pieces. I can't say just which pieces you plan to use, but I'm very familiar with them all.To be honest, seeing what you are doing, no, I'm not very inclined to help. I would be interested in helping you design something, but not when you choose to make things much more difficult than they need to be. Look at the circuit you started with, and what you have now. This is such an improvement.When you try to integrate this with the VGA circuit, you will be in a position to see similar improvements to the design as a whole. Why help you do it the hard way now, when it will mostly be tossed out later?

author: gnuarm
author_rank: Super Contributor
timestamp: August 15, 2023, 07:32:11 pm
content: Quote from: Kim Christensen on August 15, 2023, 06:53:07 pmIn reality there is no reason to add pull up resistors. If the bus will be used pretty constantly, the bus will not "float" to some indeterminate level. It will remain at its previous state for some significant time. In the old days of TTL, one needed to not let TTL inputs float, but I don't believe there is any TTL here.In the real design, once the initialization is complete, the VGA circuit will take over, and the data bus can be driven full time. This, unless I don't understand the circuit, is the character generator. It is written to once and always read after that. So, no floating bus anyway. Even a few microseconds of not being driven won't be sufficient time for the level to change.

author: Kim Christensen
author_rank: Super Contributor
timestamp: August 15, 2023, 07:44:54 pm
content: Quote from: gnuarm on August 15, 2023, 07:32:11 pmIf it was TTL, I wouldn't "worry" at all. But it's actually worse, because it's CMOS. But you're right about the busy buss. As long as it stays busy (which it will when he's done) all will be OK. But as it stands, the buss very quickly becomes idle at the end of the mem copy. I can't comment on what hemightbuild. Only about what he has shown so far.

author: gnuarm
author_rank: Super Contributor
timestamp: August 15, 2023, 08:07:07 pm
content: Quote from: Kim Christensen on August 15, 2023, 07:44:54 pmTTL could get into goofy states when allowed to float. CMOS has the issue of high shoot through current if floating to the threshold, but with so little leakage current, that takes significant time.As to what happens when the initialization circuit is complete, that's not my problem. That's up to some other designer who is working on the VGA circuit.It's been years since I worked in this sort of environment, where specs are sliced and diced and the design fragment is thrown over the wall when complete. It's only been in Dilbert cartoons where they do this sort of stuff.

author: MarkS
author_rank: Unknown
timestamp: August 15, 2023, 08:42:40 pm
content: Quote from: Kim Christensen on August 15, 2023, 06:53:07 pmThis was extraordinarily helpful. I was not aware that this was an issue with flip flops. Changing this to a 74xx74, setting the PRE pin high and the CLR pin from low to high via a simple RC circuit will ensure a low output at startup.

author: MarkS
author_rank: Unknown
timestamp: August 15, 2023, 08:50:24 pm
content: Quote from: gnuarm on August 15, 2023, 07:25:23 pmWhich only came about due to the help I've received here. I've learned a lot and am grateful. This may not be the easiest or most efficient way to do this, but breaking down into parts is easier on me mentally. Regardless, right or wrong, this is what I chose for this circuit and is where I'm at. I'll tackle the challenges that pop up due to this as they come.

author: tychob
author_rank: Contributor
timestamp: August 15, 2023, 09:29:55 pm
content: Quote from: gnuarm on August 15, 2023, 08:07:07 pmTI have an app note on this:https://www.ti.com/lit/an/scba004e/scba004e.pdf(section 4, Bus control). So long you have a reasonable sized bus and it is never idle for more than a couple of hundred ns, then you are fine without them. If you have idle periods longer than a couple of hundred nanoseconds (exact numbers and formula are in the app note), then they recommend some form of active control, such as pullups. But they also seem to assume a leakage current of 50mA, even with CMOS and I'm not sure of the timing involved here.

author: Kim Christensen
author_rank: Super Contributor
timestamp: August 15, 2023, 10:02:18 pm
content: Quote from: tychob on August 15, 2023, 09:29:55 pmGood document for the OP to read.Looks like a typo. They really meant50uAas you can see from the formula in that example:

author: gnuarm
author_rank: Super Contributor
timestamp: August 15, 2023, 10:28:46 pm
content: Quote from: tychob on August 15, 2023, 09:29:55 pmNot sure what "leakage" you are talking about. Each TTL family is different, but the input sources some amount of current, typically uA. So to pull the input to ground takes a small amount of current. The input is pulled up through a BE junction and resistor with other current flowing through it. To pull the input to ground takes some mA or so. 50 mA is a huge current relative to any of these.With CMOS, there is virtually no input current, other than needing to charge the parasitic capacitance of the input. The only problem I am aware of, is when the input sits at the threshold voltage, which turns on both a pull up and a pull down transistor, resulting in current flowing from power to ground. This can be large enough that it overheats and damages the device. Since there is no current flowing into or out of the input, the voltage on the input will not change, other than very, very slowly. If the input is floating for some us or even ms, it should not be an issue. Many busses have significant undriven periods.

author: tychob
author_rank: Contributor
timestamp: August 16, 2023, 10:14:29 am
content: Quote from: gnuarm on August 15, 2023, 10:28:46 pmBy leakage, I'm referring to the leakage of current onto the bus from the input when all transceivers are supposed to be disconnected.Rereading it, the milliamp is a typo in the english description. They actually use 50 uA for the maths, which comes out at 320ns to charge 0.8V, because of the relatively low amount of gate capacitance. Now 50uA is probably still on the conservative side for leakage per device, but it depends how reliable you want to be. Alternatively if I pull the numbers from the 74HC299 datasheet I have open, it gives a gate capacitance of 10pF, maximum Z state leakage of 5uA and input leakage of 1uA. So ignoring the line capacitance, that gives you 1.3us that you are guaranteed to stay in a valid value, before the bus potentially floats out of being valid.

author: gnuarm
author_rank: Super Contributor
timestamp: August 16, 2023, 01:50:39 pm
content: Quote from: tychob on August 16, 2023, 10:14:29 amI looked at the app note and they provide no source for the 50 uA number. That must be some TTL family or some very odd CMOS family. I would suggest you find the data sheet for the parts you are using. Your real world capacitance can include the traces, outputs and loads. It's unlikely to be only 10 pF.

author: tychob
author_rank: Contributor
timestamp: August 16, 2023, 02:22:53 pm
content: Quote from: gnuarm on August 16, 2023, 01:50:39 pmOne of the points of the appnote is you can get a good idea of how close you are to needing active control by looking at the average ratio of capacitance to leakage. So its not 10pF for the whole bus, its 10pF per load. But the 50uA is very generous by an order of magnitude. For the 74HC299 because I have the numbers for that: 5uA/20pF for an output, 1uA/10pF for an input. add a generous 5" of bus trace at 2pF per inch per input/output and thats a best case (the bus is dominated by loads, and we can ignore output drivers) average of 1uA/20pf, for 0.05 V/us. Which gives you 16us to raise by 0.8V. Thats still 2 orders of magnitude away from ms bus idle time. Do you have a suggestion of a different part to run the numbers for?

author: MarkS
author_rank: Unknown
timestamp: August 16, 2023, 04:52:28 pm
content: If it could even possibly help with stability and/or longevity, I have no issue adding a SIP pull up resistor. I was just wondering why it was recommended, not challenging the recommendation.

author: MK14
author_rank: Super Contributor
timestamp: August 16, 2023, 05:00:41 pm
content: Quote from: MarkS on August 16, 2023, 04:52:28 pmA quick, dirty and not 100% accurate explanation, is that logic devices (especially CMOS ones), have internal transistors which either pull the voltage up to Vcc (5V in your case) or down to ground.But if it ever sees a voltage, approximately half-way, between the logic states (to one or more of its inputs), and stays at that voltage. It can cause 'shoot-through' (not necessarily proper shoot through, as they may be only weakly or partly turned on), where one transistor pulls it up to Vcc/5V, the other pulls it down to ground and they electrically fight each other (a sort of short-circuit).That can cause a fair bit of current (or lots, if you like), latch-up (in rather old devices these days), and other issues. At best the circuit may not work as intended, or worse case, can be damaged/destroyed.Edit: Added simple picture, of an overly simplified logic gate. Imagine both the top and bottom transistors, have been activated, by an input voltage, half way between the power rail and ground.