Digital Oscilloscope Design with FPGA - Page 1
Forum section: electronics / general

author: selcuk
author_rank: Frequent Contributor
timestamp: October 09, 2024, 07:00:50 am
content: Hi All,I'm planning to design a multichannel digital oscilloscope having a bandwidth of about 50 MHz. Sampling rate can be 50 MS/s. I'm thinking about using ADC, FPGA and SDRAM to take and keep the samples and a MCU to process and send them to network or screen. I can use ESP32, Raspberry Pi or similar on the network side but I need some guidance on the FPGA and SDRAM part.I've searched the forum for FPGAs having a good performance to price ratio. Many members recommended brands such as Efinix, Lattice and Gowin. There are others as well.For example Efinix have Trion series. T13 and T20 have built-in flash and LQFP footprints are available. They are easier for me to prototype. May I use these or equivalents for this project?I have an Ubuntu system as the development environment. The Efinix IDE is compatible with Linux and there are IP cores for SDRAM usage. Do these IP cores free to use for the given FPGA family?And there is a development kit which includes T20 and SDRAM together:https://www.efinixinc.com/products-devkits-triont20.htmlThat IDE doesn't have a simulator. Should I look for other brands which have a simulator on their IDEs?ADCs have some registers and one needs to initialize them to properly use the ADC. Should an FPGA include a soft MCU core to do this kind of job? Do above FPGAs have the capability of having soft MCU, ADC, SDRAM interfaces at the same time?

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 09, 2024, 08:06:15 am
content: For a bandwidth of 50MHz you need a sampling rate of at least 4 times that. The minimum would be 2 according to Nyquist, but modern scopes sample a lot higher then that.An easier option in my opinion is to buy a Hantek DSO2C10 and write your own FPGA configuration and MCU firmware for it. It uses a Gowin FPGA for which the IDE is also available on Linux.

author: selcuk
author_rank: Frequent Contributor
timestamp: October 09, 2024, 09:08:13 am
content: I can use the 50 MS/s rate to keep things simple and decrease the usable bandwidth lower than 50 MHz. I have oscilloscopes at the office and this is not for my own usage. This is for a project so I'm doing it from scratch.I followed the link in your signature. Thanks for sharing. It seems that these oscilloscope series are using GW2AR-18 FPGAs for 1 GS/s. It includes the SDRAM as well. It is more than enough for me. But it is a little bit expensive. I can look for cheaper alternatives.

author: macaba
author_rank: Regular Contributor
timestamp: October 09, 2024, 09:33:57 am
content: Nyquist only applies to a specific measurement scenario.In other scenarios, having 150MHz AFE bandwidth for 50MS/s ADC is fine.In further scenarios, having 5MHz AFE bandwidth for 50MS/s ADC is fine.For oscilloscope specification, we should probably talk about rise time, not bandwidth...

author: rstofer
author_rank: Super Contributor
timestamp: October 09, 2024, 07:23:01 pm
content: The schematics for Digilent's Analog Discovery 2 are readily available but the device is obsolete:https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guideI didn't find the schematics for Analog Discovery 3

author: Someone
author_rank: Super Contributor
timestamp: October 09, 2024, 09:18:35 pm
content: Quote from: selcuk on October 09, 2024, 09:08:13 amThere are unlikely to be cheaper alternatives than a volume produced off the shelf model.The open source freedom crowd cant compete:https://www.crowdsupply.com/scopefun/open-source-instrumentation

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 09, 2024, 09:34:09 pm
content: For FPGAs, depends on what you intend to do on it. If it's just for handling acquisition (ADC + SDRAM) with no particular processing, and you have an external MCU/MPU to handle communication and/or any UI if it has any, then almost any "entry-level" FPGA would do, at these frequencies.Now if you want to implement everything in one FPGA, including some UI, plus USB (/Ethernet/...) communication, you'll need something much beefier, and likely implementing some soft core in it, or using one of these hybrid FPGAs like the Zynq.

author: radiolistener
author_rank: Super Contributor
timestamp: October 09, 2024, 11:06:15 pm
content: Quote from: selcuk on October 09, 2024, 07:00:50 amFor 50 MHz analog bandwidth you need sample rate at least 500 MS/s, otherwise it will be hard to implement anti-aliasing low pass filter and keep it's slope within ADC Nyquist bandwidth which is Fs/2.In practice, to adequately reconstruct a waveform, the sampling rate must be at least three times higher than the maximum signal bandwidth. This is because the Nyquist bandwidth assumes you're working with a cosine wave. However, in reality, the signal phase is always shifted for a random period, and you could be dealing with a sine wave instead. In such cases, two points per period are insufficient to reconstruct the waveform.With 50 MS/s you can expect good result for 1-5 MHz analog bandwidth.Quote from: selcuk on October 09, 2024, 07:00:50 amNo, you can configure it from host CPU by sending commands to FPGA to write ADC registers and it will do it. Another way is to control ADC registers directly from CPU/MCU and transfer high speed ADC stream to FPGA.

author: RoGeorge
author_rank: Super Contributor
timestamp: October 10, 2024, 04:46:29 am
content: Bold project, subscribed.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 10, 2024, 05:53:58 am
content: Quote from: Someone on October 09, 2024, 09:18:35 pmI second that. Depending on the number of channels the cost for the front end plus ADC will drive it up based on the wanted specification.Sure a simple modular design with an ADC, FPGA and MCU board can be cheaper than the Hantek but won't be very good.You will have to design a front end to handle a wide range of input voltages and the step response needs to be good enough to support the wanted bandwidth. The frequency response needs to be as flat as possible and have a reasonably sharp cutoff to avoid aliasing when sampling.Then you need to choose a good ADC for the job and select a FPGA with enough pins to handle the sampling of all the channels and interface fast enough with the MCU for displaying.There is also the choice of how to handle triggering. Implementing a good trigger setup in the FPGA might not be that easy as you think. Another option is to go for analog triggering, but the requires a DAC to set the level and an extra digital input on the FPGA to start the sampling process.There is a lot more to it then just slapping some components together before you have something decent.

author: tom66
author_rank: Super Contributor
timestamp: October 10, 2024, 09:02:40 am
content: Have a look at a project I did several years ago to teach FPGA and complex embedded systems design to myself.https://github.com/tom66/scopy_hardwarehttps://github.com/tom66/scopy-fpga1GSa/s single channel oscilloscope with Zynq FPGA/SoC and Raspberry Pi CM3 for user interface

author: asmi
author_rank: Super Contributor
timestamp: October 10, 2024, 08:07:35 pm
content: Commercial viability aside, this can be a good learning project as it includes many aspects of modern embedded designs - custom hardware via FPGA, user interface (just about any FPGA can drive an LCD RGB interface, most semi-modern ones can do LVDS or more modern MIPI/HDMI/DP), embedded Linux development (if design includes suitable AP), and of course a lot of math and parallel processing which can be offloaded into FPGA.

author: David Hess
author_rank: Super Contributor
timestamp: October 10, 2024, 11:24:35 pm
content: Quote from: radiolistener on October 09, 2024, 11:06:15 pmMost DSOs do not implement anti-alias filtering because it would alter their impulse response with sample rate. The exception are much higher bandwidth high end DSOs, 500 MHz and higher, which tailor their passband for flatter response.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 10, 2024, 11:42:50 pm
content: Quote from: David Hess on October 10, 2024, 11:24:35 pmYep. Which is why making most DSOs alias is very, very easy.

author: Someone
author_rank: Super Contributor
timestamp: October 11, 2024, 12:05:41 am
content: Quote from: asmi on October 10, 2024, 08:07:35 pmI think people consistently underestimate the scope of work required. Just to get some basic scope like functionality is not a few weeks work and as you say requires skill across many diverse areas (few people are competent in all those fields).

author: BrianHG
author_rank: Super Contributor
timestamp: October 11, 2024, 12:58:15 am
content: I was thinking of doing the same thing.Note that I did create my DDR3 controller which has full 1.8 gigabytes per second per ram chip bandwidth.It has a multiport cached controller with 16 DMA access read write channels.I also created a multi-window HDMI out VGA sub-system which is compatible with my DDR3 controller.Also, for the old 8-bit GPU project with Nockieboy, I created the accelerated 2D line drawing algorithms required to connect the sample points which is also compatible with my DDR3 controller.These items took 2 years to put together and debug. If you are starting an Oscilloscope from scratch, if you are not good with coding these things, and forget sluggish obsolete SDRAM, expect you might get something cheap going in ~9months, but to polish things up, expect 2 years of work. (Unless you will be doing this as your 9am-5pm 5 day a week job and you are well versed in FPGA and everything else...)Example DDR3 work:https://github.com/BrianHGinc/BrianHG-DDR3-ControllerExample drawing Geometry engine:https://github.com/BrianHGinc/GPU_GEOMETRY_Testbench

author: asmi
author_rank: Super Contributor
timestamp: October 11, 2024, 03:18:27 am
content: Quote from: Someone on October 11, 2024, 12:05:41 amThat's why I said it's a good learning project for those who don't have commitment issues. Or, once the basics are there, one can hack around whatever area he is interested in. And even with the basics, if you choose components wisely, you can get a lot of bits and pieces in the open online - for example, if you use certain ADCs, you can "borrow" example FPGA code provided by manufacturer to get the data into the system, or with Zynq you get Linux pretty much out of box with a fair amount of resources online on how to arrange communications with custom modules in PL. I seem to recall reading that with MPSoCs you can even get Wayland going without too much trouble, paving the way for advanced GUI libraries like Qt. Or you can just ditch the whole on-scope GUI thing and implement a web interface instead, which - again, once you get Linux going, you can leverage all the latest and greatest buzzwords of the web development without too much trouble. Stuff like DMA controllers, LCD RGB interface driver, DDRx memory controllers are also covered for free by say AMD/Xilinx, so one can focus on the actual custom application logic as opposed to infrastructure components.The only problem is that a decent ADC alone (say something like HMCAD1520) would run well into $100+ territory, and FPGA+AP (or Zynq SoC) would also be at least in the same ballpark (if not more). So aspiring engineer will need to have quite deep pockets, as just BOM cost for a single board could easily end up north of $500, and I don't see how this can be made into a big enough volume product to get better deals for these devices.One can go lower-end, but at that point the practical utility of such a device would be very questionable, and so the motivation to actually complete such project would diminish. I think at this time 100 MHz BW and 200Msps/channel is the very minimum for most people's everyday scope. If I were to have some more spare time, I'd price this out just out of curiousity, but I like said, I still expect it to be a multiple $100's.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 11, 2024, 07:24:06 am
content: Quote from: Someone on October 11, 2024, 12:05:41 amI can vouch for this. And that is why I suggested using the Hantek DSO2C10 as a hardware platform for doing the development. Sure that takes away the fun of designing the hardware, but the OP mentioned using either ESP32 or Raspberry PI for the processing side. The latter indicates using a module, already diminishing the hardware development.Even though I had previous experience with FPGA development (Xilinx XC3000 series of the 1990's) I had to go through a learning curve again to code in verilog to make a waveform generator. Took it's time even though I'm a pensionado.Quote from: asmi on October 11, 2024, 03:18:27 amTrue, there is a lot of support for the "standard" parts of building an oscilloscope, but still requires learning how to use them. Using Linux itself in embedded does takes it time in getting to know how things need to be done. When you are not familiar with Linux at all, like many Windows users, it is not that simple as you make it out to be.Quote from: asmi on October 11, 2024, 03:18:27 amThe OP stated that the Hantek DSO2C10 is already to expensive for him, so any decent setup will be too.Quote from: asmi on October 11, 2024, 03:18:27 amI agree, even with low specification it will still add up. Don't know what things cost in Turkey, but even when buying from Aliexpress getting all the needed modules to make something standalone is going to cost at least near a 100 euro.

author: tom66
author_rank: Super Contributor
timestamp: October 11, 2024, 09:34:42 am
content: FWIW on costs - I spent roughly $2000 on the hardware for my scope project. I had some support from a member on here (who has made themselves known) but for the rest, I thought of it as an investment in myself. An FPGA development course would have cost as much if not more. This took longer but it was far more fun to have a mostly working project at the end of it. Also, it likely got me my current job with 2x higher salary. So in that sense it definitely paid dividends. I would suggest OP try to do it if they feel capable. It is a very interesting project to attempt. Will you have a working 'scope at the end of it? Probably not. But you will learn a huge amount. And that's very hard to put a price on.I would personally suggest the Zynq just to avoid having to implement your own DDR3 controller with MIG or something like Brian's controller. They can be quite finicky to get working. A Zynq can run in baremetal and prove the memory works fine with a 20 line C program.

author: asmi
author_rank: Super Contributor
timestamp: October 11, 2024, 12:11:12 pm
content: Quote from: tom66 on October 11, 2024, 09:34:42 amThat's exactly what I meant when I said it's a good learning project. It's an investment into yourself, as such project in resume would definitely add a few points as it shows that you have enough dedication for such a long term project, which is becoming all more important nowadays as it places you a class above those "twitter brains" with tiny attention span, it also demostrates that you can do R&D independently and achieve results.

author: David Hess
author_rank: Super Contributor
timestamp: October 11, 2024, 03:33:27 pm
content: Quote from: Someone on October 11, 2024, 12:05:41 amThe project duplicates the architecture of the earliest DSOs like the 2232 except for equivalent time sampling, which could be added easily enough with a duplicate channel processed to produce acentroid timing time to digital counter, so no additional hardware design is required for equivalent time sampling except for a comparator and pulse shaper.Digitize into a fast acquisition memory until triggered, and then fill remaining acquisition memory. This could all be part of the FPGA. Stop digitizing and transfer acquisition record into processor memory. Process the record to produce the display record. Restart acquisition. It will not have a fast acquisition rate, but it will be faster than those old 2232 type DSOs and they are very usable.

author: David Hess
author_rank: Super Contributor
timestamp: October 11, 2024, 05:31:41 pm
content: Quote from: SiliconWizard on October 10, 2024, 11:42:50 pmI prefer not having the bandwidth and impulse response change with sample rate. An oscilloscope is primarily a time domain instrument, so sample rate should be compared to transition time rather than bandwidth. 100 MHz implies a 3.5 nanosecond transition time, while 50 MS/s is a point every 20 nanoseconds, a definite mismatch, but at least those points are on a real waveform. A more suitable transition time of 20 nanoseconds results in a bandwidth of 17.5 MHz with a single-pole rolloff, but this is far from your recommendation of a 5 time or higher sample rate.My slowest DSO is a 2230 at 100 MHz and 20 MS/s and in practical use, aliasing is never a problem even without peak detection or equivalent time sampling. When taking advantage of its full bandwidth, equivalent time sampling yields up to 2 GS/s, but I prefer that to having sinc interpolation and anti-aliasing making up a waveform which may or may not exist.Why does this matter? Lets say an automatic measurement is made of an amplitude related characteristic of the signal. The process is to generate a histogram of the signal and extract measurements from the histogram. If anti-aliasing is included, then the histogram will change with sample rate changing the measurements even though the signal has not changed. The most accurate measurement is made when no anti-aliasing is implemented.

author: Someone
author_rank: Super Contributor
timestamp: October 11, 2024, 09:27:47 pm
content: Quote from: David Hess on October 11, 2024, 03:33:27 pmFor that minimal scope of work, I still don't think many people could put it together in less than 4 weeks or so. Even using dev boards rather than designing a PCB (OP is not clear on that).Trying to reduce cost aggressively (as the OP is) adds a whole extra pile of work.

author: BrianHG
author_rank: Super Contributor
timestamp: October 12, 2024, 02:19:53 am
content: For a stupid scope, forget the ram.Get an FPGA with over 128kb block ram which can run in 4 port mode.This makes a display 512x256, 256 shade levels. (or 64k which equals 512x256, 4bit, 16 shades of grey)Use the memory as your display and render direct to ram, reading, then adding that point to generate the artificial phosphor effect.When displaying, use 1 of the 4 ports and create a gamma LUT for the persistence contrast effect.Use another 1 of the 4 ports to decay the old pixels if it is not being charged by the sampler input.You want simple stupid, here it is.

author: selcuk
author_rank: Frequent Contributor
timestamp: October 12, 2024, 04:31:24 pm
content: Thank you all for your responses and time. I've looked to the projects and example products shared by @pcprogrammer, @rstofer, @Someone, @tom66, @asmi and @BrianHG. As far as I understand, these are the FPGAs used for this example set: GW2AR-18, Xilinx Artix-7 XC7A35T, Spartan XC6SLX16-1L, Zynq, Spartan XC7S50. I can understand that these are verified candidates for this type of project, but their price range is between $50-$60 and $100 and above. The prices of the oscilloscopes are fine. Hantek DSO2C10 is $220+VAT here. I think it is affordable. But I'm planning to place these components on a PCB, so I'm more concerned about the price of the FPGA chip itself. The development board on the first message is for getting used to the FPGA development. I may need one to understand the basic steps for using FPGA + RAM.I'm planning to use @SiliconWizard and @radiolistener's advices and keep the functionality of the FPGA minimum, and use the external MCU to do all the signal processing, ADC configuration, management of user and communication interfaces. No soft MCUs will be inside the FPGA. Then, is it possible to use a $5-$10 FPGA for this? I believe I need to implement the trigger functions into the FPGA, since MCU doesn't know about the trigger time unless it is already triggered. Very basic triggers like falling under a level and rising above a level. No need for triggering after receiving SPI chip select or I2C start bit etc.For the analog bandwidth, it is okay for me to have rounded corners for i.e. 20 MHz square wave signal. That is understandable with a relatively low sample speed. But thank you for pointing that out.I believe DDR3 is very fast with respect to my expectations from the project. I thought about SDRAM because the chips on the market have footprints other than BGA. And I already searched for ready-made cores like below:https://www.efinixinc.com/support/ip/sdram-controller.phphttps://opencores.org/projects?expanded=Memory%20coreI don't have experience with FPGAs, so I may not be able to build a fully featured oscilloscope at this point. The emphasize is on analog part, very primitive sampling with FPGA and RAM, and getting a waveform on MCU. No need for the screen at first iteration.Is it possible to have about 8 Megabytes or preferably more RAM inside entry level FPGAs? As RAM blocks or LUTs (if they are different things)?A side note about buying things here. The max order amount is 30 EUR to get the goods out of the customs. So I don't normally order a scope or expensive development kit from Aliexpress myself. Prototype PCBs are okay since they cost around $10-$20.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 12, 2024, 05:12:27 pm
content: Maybe the Tang nano 20K FPGA board. It might be pushing the price limit, but it uses the Gowin GW2AR-18, so 8MB of memory comes within it.https://nl.aliexpress.com/item/1005007706453661.htmlSmaller FPGA's without a lot of internal memory are of course cheaper, but to connect external memory you need more IO pins, so a bigger package is needed.Most FPGA's have BRAM (block ram), which is fast but in the smaller cheap ones gives maybe at best 1Mbit or so.

author: tom66
author_rank: Super Contributor
timestamp: October 12, 2024, 10:08:06 pm
content: FPGAs with large internal RAM like the GOWIN device are usually PSRAM or DRAM embedded, this is okay but you do have to do quite a bit more work to manage a memory like this. Whereas BlockRAM only needs clock, wr_en and data at the right time, and usually has max 1-2 cycle latency so writing a state machine to stuff data in is pretty simple.IMHO if your goal is lowest cost and only 50MSa/s, bin the FPGA altogether and do it in a fast MCU, like one of these (80MSa/s ADC with built in DMA):https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc4300-arm-cortex-m4-m0/32-bit-arm-cortex-m4-plus-2-x-m0-mcu-282-kb-sram-ethernet-two-hs-usbs-80-msps-12-bit-adc-configurable-peripherals:LPC4370FET100Triggering could probably be done using an analog comparator or, not had a look but an ADC that fast may just have an edge trigger based on digital data built in...

author: selcuk
author_rank: Frequent Contributor
timestamp: October 13, 2024, 09:47:47 am
content: Quote from: pcprogrammer on October 12, 2024, 05:12:27 pmThis manufacturer has many options for Gowin boards. Using this board on top of my PCB can be cheaper than buying Gowin FPGA.

author: selcuk
author_rank: Frequent Contributor
timestamp: October 13, 2024, 09:58:34 am
content: Quote from: tom66 on October 12, 2024, 10:08:06 pmThis was the first plan. Not this particular MCU but something equivalent. Then I thought it would be a better project with an FPGA.

author: sslupsky
author_rank: Contributor
timestamp: February 20, 2025, 12:01:47 am
content: Have a look at this project. It is open source and maybe you can fork it or make some improvements. It uses an FPGA but all the digital signal processing is done on a TB/PCIe connected computer so there is no local SDRAM. I attempted to convince the maintainer to include a footprint for SDRAM on the PCB but I was unsuccessful.https://github.com/EEVengers/ThunderScope