ADVANTEST R9211B - Page 1
Forum section: electronics / repair

author: stfjohn
author_rank: Regular Contributor
timestamp: July 24, 2024, 10:27:49 am
content: Hi everyone. My Advantest R9211B FFT analyzer suddenly presents this message when turned on: "Fatal Switch - illegal state 0 in main - not installed!" . Can anyone help me?Thanks.

author: m k
author_rank: Super Contributor
timestamp: July 31, 2024, 07:41:34 pm
content: Just a guessDifferent models have different options that are so close to each others that there are switches selecting what is present.Now one of those switches has failed, so wrong option is indicated.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 02, 2024, 02:31:06 pm
content: Thanks for your input. Unfortunately the device doesn't just not install an option: it just doesn't work! That message appears on the monitor and everything stays off!

author: m k
author_rank: Super Contributor
timestamp: August 03, 2024, 02:43:35 pm
content: Hardware option.Since one switch has a wrong value it doesn't recognize its guts.During a boot procedure it tries to initialize all parts it has.Wrong switch value indicates that it includes a part X.But initialization fails because the actual part is Y.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 05, 2024, 09:36:49 am
content: Ok. Since I don't have the wiring diagrams (I asked Advantest, but they told me they are not available to provide them, not even for payment.... 40 year old device: will it be a state affair? Mah!!), what can I do concretely?

author: m k
author_rank: Super Contributor
timestamp: August 05, 2024, 10:57:05 am
content: You open it and start guessing.Few pictures wont do any harm.You can also try deciphering the message.Not installed is clear.Fatal switch can be a hardware thing, but combined with "illegal state 0 in main" it can be a software thing.Hardware switch is simple.Software switch, a parameter of main() resulting state 0, that is illegal, can be trickier.But first thing first.The machine must have all necessary voltages present.Reseating all pinheader style connectors are not bad either.Socketed chips can also be pushed up a bit by their sockets and so should be bushed back in.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 05, 2024, 12:24:29 pm
content: The voltages are all present. I have already deoxidized all the connectors present and the sockets of the various chips (It's the first thing I did..). Unfortunately I really believe that it is a software switch, because the only hardware switch present works perfectly.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 05, 2024, 02:16:51 pm
content: Here screen image...

author: m k
author_rank: Super Contributor
timestamp: August 05, 2024, 04:04:02 pm
content: Now the message is different, you missed the underline, it's important.So the main program has a parameter that is not allowed to be zero.Unfortunately it doesn't say what is not installed.But it clearly is a failed initialization of something.Maybe connections at the back can give out some boot info.Next you can check that all modules actually have their voltages.There can be local regulators.Bad capacitor can also pull down a small regulator, or prevent reset signal going off.Top side bulky elcos are easy, but they can also be very evasive if popped from under side.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 06, 2024, 09:39:56 am
content: I tried removing the cards of the 3 options present: the result does not change. I think I can see a couple of reed relays on the motherboard: I will try to disassemble everything (which is quite complicated...) to see what components they are. The voltages indicated on the various printed circuits are correct, however.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 06, 2024, 03:01:11 pm
content: Here some pictures of the motherboard.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 06, 2024, 03:03:29 pm
content: Idem.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 06, 2024, 03:06:02 pm
content: The battery is good!

author: m k
author_rank: Super Contributor
timestamp: August 06, 2024, 05:51:19 pm
content: It needs more permanent memory.Can't see what the gold top is, NS32 something?Upper side is floppy and CRT.Lower left has keyboard, controller has also an LCD style display part, beside it is 8k ROM. it's not enough.Lower right is GPIB stuff.Center square is not visible, but not needed either.Center triplet under CPU is so center that the thing probably wouldn't display anything if there is a fault.Since keyboard controller has that display part it can put out very primitive stuff, if implemented.How is that lower left connected, both connectors in use?In front of front euro connector are bus terminals.Is there anything displayed if you operate the machine without any of to end side bus cards?It should be possible to put any card to any slot, but who knows.You can try different combinations.Start filling from crystal end, if possible.LS244 2nd left from upper crystal has some texture issues, some picture stuff only?Those used to be less robust back then.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 07, 2024, 08:39:29 am
content: Thanks again for your kindness. The golden part is NS32081D-10J. The central square is TMS32025GBL. The Eprom board (Mitsubishi M5M27C101k-2) is connected to the J9 connector at the bottom left: 16 in total. The switch on the board in question works well. I tried to move the various contacts: normally 2 and 5 are ON. Putting them all OFF also makes the writing on the screen disappear, which reappears by putting 5 in the ON position. I tried to remove and put back all the boards, but nothing changes. Removing the Eprom board, however, all the LEDs on the front light up and everything remains still, obviously... In fact the LS244 and also the 74157 underneath seem a bit shabby...Best regards.

author: m k
author_rank: Super Contributor
timestamp: August 07, 2024, 07:19:33 pm
content: LS244 is 4+4 bus driver, F157 is 2to1 x4 data selector, easily connected together.8 bus connectors are also easily 4+4.But those chips are also constantly in use, so easily picking up some wear over time.Good to know that missing ROM card has some visible effects.Means that it's at least partially present and available.So the gold top is a Floating Point Unit.Its location is a bit odd, something like not central.Is a connector above it in use?Topmost bus connector seems to be different.(is there a better name for eurocard connector)Between it and next connector are more bus drivers.Maybe ROM card and this topmost is a minimal installation.Possibly some switch changes are also needed for that.Very difficult to continue if only info is that earlier text or not.I'm quite sure some primitive console type boot info is available somewhere.Back has some trigger connectors above GPIB, are they from J19?There is another pinheader set near by, maybe J17, is it in use?It's not far from JTAG.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 08, 2024, 10:27:39 am
content: The connector above NS32081 is used to connect the optional printer. A (working) stabilizer board is connected to bus J8 which supplies power (+15V -15V -24V) to all bus below. J17 connects a video output on the back. J19 connects SMPLG CLK and TRIG inputs and outputs, always on the back.I ordered the LS244 and F157 ICs. I will try to replace them.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 12, 2024, 10:06:22 am
content: I changed the LS244 and 74157 ICs, but, unfortunately, nothing changed: always the same message on the CRT.

author: squadchannel
author_rank: Frequent Contributor
timestamp: August 12, 2024, 04:03:47 pm
content: There is a lack of information on R9211 on the Internet. (Advantest is also reluctant to actively publicize resources)Currently, a maintenance manual is listed on eBay. It can be called a service manual as it also has schematics.Can you purchase it and scan the PDF for future use?eBay auction: #116111410582

author: m k
author_rank: Super Contributor
timestamp: August 12, 2024, 05:01:31 pm
content: Would you donate a part of cost?

author: stfjohn
author_rank: Regular Contributor
timestamp: August 13, 2024, 09:27:31 am
content: I don't see any service manuals with wiring diagrams on eBay! Only operating manuals! These can be downloaded easily from the Internet!

author: stfjohn
author_rank: Regular Contributor
timestamp: August 13, 2024, 09:43:19 am
content: Sorry, I saw: in reality it is the R9211 not the R9211B: the power supply diagram already does not match: the 9211B uses switching power supplies: I would not want the rest to be different!

author: squadchannel
author_rank: Frequent Contributor
timestamp: August 13, 2024, 11:53:34 am
content: Quote from: stfjohn on August 13, 2024, 09:43:19 amReally? In the second image, the title of the figure includes the letter "B".changed? hmmm...

author: stfjohn
author_rank: Regular Contributor
timestamp: August 13, 2024, 12:35:01 pm
content: My device has n. 3 switching power supply "Nemic Lambda" !

author: m k
author_rank: Super Contributor
timestamp: August 13, 2024, 06:27:43 pm
content: Since power is different all other parts can be so also.You should contact the seller and ask some more pictures, component layouts should be enough.Seems that letter versions are from the beginning, but actual timing is still a bit hazy.One brochure includes 4 versions and F is missing.If F is newer, SMPS can come with it, and be fitted to all machines later, for what ever reason.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 14, 2024, 09:57:49 am
content: I asked the seller and this is the answer:"this is the original Maintenance Manual for the R9211 Analyzer.The pictures are only an abstract.It is quite complete."QUITE"....

author: stfjohn
author_rank: Regular Contributor
timestamp: August 14, 2024, 11:54:48 am
content: From the seller:"I will not send any pictures of further schematics due to legal rights.What I can do is to send pictures from the table of contents...And again: this is the only official maintenance manual which Advantest ever released. You will find no other source.The manual handels the following R9211 types: A/B/C/E/FThere is only an excerpt of all schematics inside not all! To my knowledge there is no existent repair manual with all schematics available and never was.And again to make it clean:This manual is the Maintenance Manual NOT the a Repair Manual!"

author: squadchannel
author_rank: Frequent Contributor
timestamp: August 14, 2024, 12:10:02 pm
content: Quote from: stfjohn on August 14, 2024, 11:54:48 amAny test equipment since the 1990s that has gone digital is no longer basically a repair manual.Anyway, as “B” is specified, I think it is a valid manual.Since no one understands this error, I guess the only way to find out is to buy the manual.

author: m k
author_rank: Super Contributor
timestamp: August 14, 2024, 04:15:32 pm
content: Quote from: stfjohn on August 14, 2024, 11:54:48 amAn indication that the manual is partly a field maintenance manual.It may include a mainboard schematics, maybe that SMPS also.But bus cards, I doubt.Maybe they followed HP route.If so then some extra boot info is probably present.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 16, 2024, 10:36:42 am
content: I bought the manual in question. Let's hope it's of some use....

author: stfjohn
author_rank: Regular Contributor
timestamp: August 23, 2024, 04:05:10 pm
content: The manual arrived. Unfortunately it contains no diagrams except block diagrams. This is the only one of any interest, in my opinion.

author: m k
author_rank: Super Contributor
timestamp: August 24, 2024, 07:15:53 am
content: So you have few more or even more difficult routes.Maybe easiest is to get a 68k hardware monitor and check how program flows.One other could be a two channel timer or something like that to check how chip selects go, after every switch on you can guess what CS was later and so on.Reverse engineering the whole software is of course also a route.Block diagrams can be close to schematics, but there must be plenty and detailed ones.If the above block diagram is a guide you can assume that the program bus is operational.It also means that you can verify initialization of all of those upper side chips.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 24, 2024, 03:48:29 pm
content: Forgive my ignorance on this matter: where can I find a 68K hardware monitor and how should I use it to check the program flow?

author: m k
author_rank: Super Contributor
timestamp: August 24, 2024, 04:31:25 pm
content: Maybe it is no more.Back in the day had a thing where special socket was put in between the CPU and its original socket.The special socket was hooked to the monitoring machine and it did what was wanted or needed to figure out what was happening.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 26, 2024, 01:51:30 pm
content: How can I verify initialization of all of upper side chip?

author: m k
author_rank: Super Contributor
timestamp: August 27, 2024, 06:26:35 am
content: You can start by scoping GPIB data lines.If there is life you can expect some boot info.Next you can scope all possible chip select signals, maybe you are lucky and only few appears.Skip memories, they are tested or not and passed enough.All parts don't need any actual initializing, but they still must, or should be found.If you want to verify what is really happening you need to figure out what is coming and going.For that one possibility is a logic analyzer, but it is much work for little gain.And you still need to check all programming manuals to find out what all those things mean, and then find out that the program is actually doing exactly what it is suppose to do.The block diagram indicates that there's only one pair of bus drivers, so data part is fine since CRT has meaningful text, that must go through the data part of the program bus.All other parts are unknown, but can you decipher anything from the text on screen.Maybe you should start from the assumed end.One can assume that checking ROMs is so easy that it is done and failure would be indicated differently.But if it happens to be so that lower part of the block diagram parts are getting attention does it mean that upper part is already done and ok.TI DSP is a normal part so that is easy, but Advantest bus controller is trickier.1st left memory block of the lower part of the block diagram, is it MEMCRT?If so then check their _OE(16) pins, they are 8x memory chips left from bus connectors.If _OE doesn't go down those memories are not used and text on screen is directly written to CRT controller.If so then it's possible that the text on screen is not present in ROM in normal ASCII text form.But this or that reading ROMs out is always beneficial.In case you don't have a gear for that near by, don't use too much effort, it doesn't help you in near future.In case you have hard times accessing pins when the machine is in one piece check those IC pin minigrabbers.Some scopes have multiple triggers, if you want to figure out the initializing order of chips.Simple dual D-flop circuit will do it also, there CS signal flips the other flop's set or reset, adding few LEDs is not a bad idea.Then you just flip pairs to find out what is always later.Chip select signals are multiplexed.So following the trace back you should find from where it is coming, it is not a multi use signal, if not for multiple equal chips, like memory chips.The problem can be also that multiplexer.Checking (de)multiplexers and multi line transceivers can be tricky.For that you may need a logic analyzer, and 8 bits is not very wide.I'd probably skip MCU stuff, few latches and D-flops with LEDs are much more versatile for single purpose.But there are so few peripheral program bus chips that you'd probably be fine with cheap 8 bit USB thingy.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 28, 2024, 09:41:11 am
content: I connected the GPIB socket to the computer, but no sign of life! Question: if the initial software is not installed, could it be a problem with the PROM - EPROM bank?

author: m k
author_rank: Super Contributor
timestamp: August 29, 2024, 06:57:49 pm
content: Yes, but it's also possible that this part is not yet activated.You can test the chip _CE pin 3, if it doesn't go down the chip is not accessed at all.If there is some activity the chip is possibly initialized, but program is not sending anything.You can also ask its ID.CRT controller HD63484 _CS pin 5, you know it's active.Maybe it is more easily accessible and can be traced backwards, if you want blindly change some chips.I don't think that displayed text is from so early that only CRT is accessed.How long is Diag Soft Level 0 description, can you put up some pictures?I seem to have hard times understanding what can be originating a displayed text like that, if it's not on purpose.It's like from a place where it is not suppose to happen and therefore not really being informative at all.What kind of programming the machine has, is it always the same and in ROM?The displayed text is similar to a software that has some unexpected part missing, like a wrong DLL with a missing function.But static ROM image is very easy to verify.Lower right corner of a ROM card of block diagram, is that marking a battery?If that 128k RAM should have a program its integrity is also very easy to check and so shouldn't be a source for that displayed text.Can you find any special resetting procedures from that manual?

author: stfjohn
author_rank: Regular Contributor
timestamp: August 30, 2024, 09:54:59 am
content: The manual is 99% dedicated to the analog parts and power supply. The rest assumes that the self test works! Consequently the troubleshooting instructions absolutely do not provide for the initial program not to be installed! The manual is practically useless! The only other image of some interest is the one I attach now. No reset indication! What Diag Soft Level 0 description?

author: stfjohn
author_rank: Regular Contributor
timestamp: August 30, 2024, 02:52:44 pm
content: There is no battery in the ROM board. Perhaps the symbol indicates the electrolytic capacitor present

author: m k
author_rank: Super Contributor
timestamp: August 30, 2024, 03:19:38 pm
content: Yes, probably a capacitor, just a left side of bottom part missing.Diag Soft Level 0 is mentioned in your earlier logic 1 picture.Its description should be just before that pictured page, section 3.2, maybe it's so brief that you've missed it.68k CPU has a memory mapped I/O.Means that it doesn't have any dedicated I/O instruction like x86 has.68k has 24 bit address bus, or 23, it's always a word.So highest bit defines data bus, you can check how it goes.Then there is this that defines 0101 of highest nibble.It can be one or two circuits, one is easy, just a chip with separated enable pin.Next is this 111x nibble for I/O, all of this can also be a single PAL chip.You can also forget those and concentrate to address bus directly.If highest bit is active all the program bus should be done, per the text in logic 1 picture.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 30, 2024, 03:31:08 pm
content: The section 3.2 is an analog portion.There is no battery in the ROM board. Perhaps the symbol indicates the electrolytic capacitor present.I noticed that one of the two LEDs present (D10) is not lit during operation (the LED in question is connected to p. 13 of the nearby 74F138 integrated circuit), while D3 is lit (probably indicating the presence of 12V voltage).

author: m k
author_rank: Super Contributor
timestamp: August 31, 2024, 11:31:09 am
content: Beside the LED D3 are TP1 and TP8, can you follow where they go?I'm still after that boot info.Can you find those other test points and diodes?During the design process all numbers have at least been somewhere.There seem to be many of those 138 3to8 chips.Stacking them goes so that higher one is only an enable for the next level.I/O area division in earlier picture indicates 3to8 chips.Beside the 74F138 of D10 is 74F08.Second order after 5 for I/O can be simple 4 input AND, or 3x 2 input AND.Since 5E and 5F are both for I/O the last bit can be ignored.If the LED D10 is indicating something special, like it most likely is, it can be for 3rd section of I/O area, then it would be 2 after 5F.But is there something so special that an indicator LED is added, and just one for very sudden access.For work area RAM the LED can be a preselector, so 010x of 2nd highest nibble, then it would include nibble addresses 4 and 5.It can be even so that a watchdog something is written to addresses that blinks the LED and indicates that the software is not stuck or running away.

author: stfjohn
author_rank: Regular Contributor
timestamp: August 31, 2024, 01:12:26 pm
content: TP1 goes directly to the GPIB connector; TP8 connects to p.2 of the TL7700 IC (4+4 pins) immediately behind the GPIB connector.

author: m k
author_rank: Super Contributor
timestamp: August 31, 2024, 05:53:35 pm
content: TL7700 is a voltage supervisor, so no boot info from there.In theory a GPIB control pin could be an async serial connection, but that's a quite a bit of a theory.Starting 68k goes so that first address is zero.So you can scope its address bus directly and tell how things go.For I/O check a 4 channel scope is enough.A23 and A22 to check it's less than 8 but more than 3.A19 and A18 to check it's more than x8, so after E2PROM.Conditional trigger wouldn't be bad either.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 02, 2024, 02:31:03 pm
content: The only signs of life I see on the 68000 are the clock 10 Mhz at p. 15 and the signal 1 Mhz at p. 20.

author: m k
author_rank: Super Contributor
timestamp: September 02, 2024, 05:24:12 pm
content: The CPU is probably halted, pin 17 is down, if so then address and data are in high impedance state, so no more info from there.But you can use it as an external trigger, if you can see few moments in history.Even better if you can use it as a stopper.Since the thing most likely does the same after every boot you are fine with dual channel scope.Just stop collecting when halt goes down and check how those address lines were.You may need to boot several times, but that is a small burden.You can also build a simple circuit, single chip latch will do.Pin 6 is address strobe, active low, address comes first and then _AS goes low.So LS374 and output LEDs can be 8 bit status indicator and store the last partial address.You also know that CRT controller is accessed, so something must blink or it doesn't work.More complex it will become if you need to trace back unknown addresses, then this USB dongle logic analyzer is much easier.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 04, 2024, 01:53:18 pm
content: I was loaned a logic analyzer...Photo #1 pod 0 = P. 1 (68HC000) (the remaining pins to follow).Photo #2 pod 0 = P. 16 (68HC000) (the remaining pins to follow).Photo #3 pod 0 = P. 50 (68HC000) (the remaining pins to follow).Photo #4 pod 0 = P. 33 (68HC000) (the remaining pins to follow).

author: m k
author_rank: Super Contributor
timestamp: September 05, 2024, 06:06:54 am
content: Picture 2 02 must be E pin 20, so pins 24 and 25 are down, interrupt is active.Addresses A1-3 defines the interrupt, then other addresses are high, so that moment is history.Pin 26 is high, so CPU is in supervisor mode and serving interrupts.Picture 1 14 is clearly a clock, next is up so it's not GND.07 is down, it can be _LDS and so 16 bit data operations.A bit after center 08 goes down few times, those can be write cycles, same time data seems to be 0000.A bit before center picture 2 has other supervisor data cycle, there data seems to be also 0000.But the earlier cycle is read, so maybe there the CPU tries to clear the interrupt but fails.Incoming data can be buffered.Earlier block diagram indicates that only DMA controller is buffered, but those buffers should be drawn differently.Maybe some other parts are completely missing.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 05, 2024, 04:09:09 pm
content: I'm afraid there's very little that can be done unfortunately....

author: m k
author_rank: Super Contributor
timestamp: September 05, 2024, 05:52:29 pm
content: There are many things that can be done, even more if you can keep the logic analyzer a bit longer.But everything is more or less time consuming, more if you're not familiar with what is happening.Connect the analyzer to 16 highest addresses and put trigger to A22.If nothing happens you cam assume that no I/O is accessed.Change trigger to A23, if earlier was nothing maybe here is something, something is generating interrupts anyway.If A22 and A23 are both off only thing left is DMA controller.You can also sync to CLK, pin 15 and possibly get a longer set of readings.

author: m k
author_rank: Super Contributor
timestamp: September 06, 2024, 06:56:25 am
content: Dang, I forgot the CRT controller, it's of course active and address space is used.So iffirstonly address is there something is missing.CRT controller can't be thefirstonly one, if it is then the machine doesn't know that something is wrong.Assumption is that nothing generate interrupts without activation by the software.But fault can obviously do its own things.Other approach can be chip selects and similar pins of all I/O chips.Then you can have easier trigger and lower amount of needed data.Include _IPL0-2 and A1-4 pins for interrupts.Earliest trigger is problematic, maybe a preselector 3to8 chip of those chip selects, that you must find out by tracing some of those pins.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 07, 2024, 10:01:27 am
content: Forgive my ignorance on the subject (I deal with linear electronics applied to audio): what are the highest addresses (to which pins should I connect the logic analyzer)? Thanks.

author: m k
author_rank: Super Contributor
timestamp: September 07, 2024, 06:40:40 pm
content: Since we now know that interrupt is happening we can try to go back from there.Though it's also possible that the interrupt is exactly as it should be.Since interrupt itself is pretty short it's not very easy to follow, but we can predict that before that interrupt the processor has accessed the chip.It usually goes so that chip that can do interrupts is reset interrupts off, so processor must activate it first.Since we know the memory map we can leap to before any I/O chip access, easiest it is to follow how program is forwarding.Highest CPU addresses A23-20 defines the highest nibble, that is all we need for knowing that I/O is accessed.Next six addresses A19-16 and A15-14 are for sanity check, that the address is actually what it should be.(0101 111x 00)After that we can start wondering what chip is accessed.But since there is text on the screen we know that CRT controller is accessed, so we can assume that all those addresses are fine.So only A22 is needed for triggering.We can continue assuming, so A16 is needed and so are A13-10.So finally only 6 pins, plenty left for other things then.(51, 44, 41-38)Pin 9 for read/_write is always nice to know.Rest can be pins 24-32 for interrupt process.So first trig A22.Then maybe pin 25 or 24, those go down for interrupt, in your earlier picture those were both down, but it can be from multiple interrupt requests.After that you can check how different pictures combine.When bottom 4 are the same you know it's the same spot.If you can use conditional triggers you can try combining different address pins from the earlier memory map picture.My guess is that only 1st set of I/O map will do interrupts.What are 3rd set of I/O map names?RDRECS8245BRDRETRDBGTSOFTRST

author: m k
author_rank: Super Contributor
timestamp: September 09, 2024, 10:20:29 am
content: Some other things to try if analyzer is about to be returned.If the machine has an output possibility you can also try dumping results out for later use.Low left is keyboard controller and its ROM.The controller chip can generate an interrupt when key is pressed.So 82C79 pins to the analyzer4, 10, 11 IRQ, _RD and _WR12-19 data21, 22 A0 and _CSIf clock sync needs a POD pin there are two leftovers.You can also change the last pin of the earlier message for clock, if needed.Two leftovers can be used for _IPL0 and _IPL1 of the CPU, if possible.In the earlier picture both signals are down, so if both are connected and only one goes down we know that interrupts are more than one.You can of course test them one at the time also.First trig IRQ pin 4.If IRQ happens you should see the data when _CS and _RD are down.One possibility is that there is an interrupt, but data is 00, so no key.The interrupt pin goes down when data is read and stays down if no more data is available.RTC chip above the keyboard controller seems to have a some sort of an interrupt something, but use of that function is not very probable.Same with the keyboard controller, but maybe a bit more probable, polling a keyboard is quite usual also.A square chips near the buzzer and one left from 12V input are D71054.Is the one a bit down from 12V input also the same?That chip is a counter/timer and can generate many kind of interrupts.Pins 9, 18 and 26 as OUTn, it seems to be 8254 clone, mentioned in 3rd block of I/O chips.But since its function is what it is there is little use for reading it after it generates an interrupt.So its outputs are merely for triggers and not probable for generating that text on screen, at least alone.But that is a pretty simple chip so checking how it's programmed is not complex, though doing that with a logic analyzer has some nuances.Since you're usually just letting the analyzing flow you can't expect that you can see much during single pass.Those chips are also far apart, so maybe POD wires are too short.1st I/O block5E00xx *CSDMAC5E04xx *FPUSEL5E08xx *FPUPOL5E0Cxx *CSFDC5E00xx *CSGPIB5E04xx *FDCDMAFPUPOL can indicate that floating point results are polled, it also has a bidirectional completion signal _SPC for possible interrupt.FDC is probably for the later use, same with GPIB.2nd I/O block5F00xx *CS82795F04xx *CS8254A5F08xx *CSRTC5F0Cxx *RTC1CLC5F10xx *BZON5F14xx *INTCLR5F18xx *MODESETBZON can be one timer, INTCLR and MODESET can be what ever.3rd I/O block5F20xx *RDRE5F24xx *CS8245B5F2Cxx *RDRET5F30xx *RDRGT5F38xx *SOFTRST28 and 34 lines are missing, it can mean that the access area is wider.Maybe all of those are for timer chips.A bit tricky to test, legs are closer and one is on the other side.Maybe you can follow traces backwards.Use the setting from the earlier massage and leave the last 4 pins out.One of those free POD pins can go to CPU clock and other three to _CS pins of timers.For reading timer chip programmings you need at least 8 data and 2 address pins, chip select and write signals.That's 12 pins, so chip selects from other chips and clock is 3, still 1 free.There data bits can be connected to CPU, but it can use the whole bus and write two timers at once, so maybe not.So best practice is to read directly from the chip and one at the time.For DMA controller you can also use that earlier message setting.Use last pin for clock and other address pins for DMAC _BEC0-2, pins 29-27.Since DMAC interrupt is different you can't see what happens, but you should see its general I/O access shortly after interrupt happens.What has happened must be read out from its registers, so many pins are needed.But you can also guess the happening from Bus Exception Control signals.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 10, 2024, 10:47:54 am
content: Be patient: to do all these measurements, I have to reassemble the motherboard on the chassis each time and can therefore only measure from underneath the printed circuit board, soldering pin strips onto the components to connect the logic analyzer! All this soldering and unsoldering will soon lead to me having to throw everything away! However, I can keep the analyzer (an old H.P. 1651A) for a while longer. Let's see what I can do....

author: m k
author_rank: Super Contributor
timestamp: September 10, 2024, 03:31:53 pm
content: Dang!But props for the commitment.I'm using UTP cat5 Ethernet wall cable wires for many things, it's a single core thing.Good for the analyzer, and not a simple one.So 32 channels, I think you can have all necessary info from a single connection set.I'm putting stuff up so that you don't need to roll your thumbs.Or to do too many wrong things after wrong tips, so no hurry.So 32 channels,first 16 pins from #53.Next 82C79 _CS and IRQ pins 22 and 4, to check that access actually goes there.Next 68450 _CS, _IRQ and _BEC0-2 pins 17, 21 and 29-27.Next _CS pin 31 of all 3 timer chips.So 2 + 5 + 3 more, six to go.Next 32801 _SPC, ST0 and ST1, pins 21-23, for a sanity check, maybe it's sending its own.Next CPU CLK, _HALT and _RESET, pins 15, 17 and 18.Halt and reset can be dropped out when it's clear that they are not obstructing anything.You can also use a POD clock of course.Timing.CPU clock first, you can add more triggers when you know what is happening.For example if interrupt happens and it is cleared away you can skip everything up to that point.Page 8-12 of the Reference Manual has an example.I'm not familiar with the analyzer, must read some.Maybe somebody around can give some insights.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 12, 2024, 03:48:33 pm
content: Here are the scans in the exact sequence you requested in your last post. (Trigger A22)Photo 1: pod zero pin 53; pod 1 pin 52 etc. to follow.Photo 2: pod zero pin 22 (82C79) etc. to follow according to the exact sequence of your last post.

author: m k
author_rank: Super Contributor
timestamp: September 12, 2024, 06:51:16 pm
content: Sorry, my bad, #53 was reply #53.But no panic, plenty of info from 53 and down.It can be even better than the intended one.Second picture POD 2 00 and 01 are ok.CPU _HALT and _RESET, POD 2 10 and 11 are also ok.But I'm not sure what are POD 2 02-08.There should be 5 pins from DMAC, 3 pins from time chips and 3 pins from FPU.So CPU CLK should be POD 2 13.Those 3 pins above clock are not very timer like, so my guess is 32081 FPU.But no panic here either, we can put that aside.POD 1 00, is constantly down and 04 is constantly up, so GND and Vcc.Means that 01 is CPU A23 and flipping, so address is at least 8x xx xx.POD 1 binary addresses from the left.0000 0000 1001 00 = 00900100 0000 1001 00 = 4090 short0100 0000 1001 00 = 4090 short1100 1100 1101 11 = CCD31100 1100 1101 11 = CCD3and repeatingShort pulses can be something else.So what option is that CC?Then my second bad, those FPU pins are not accurate, I mixed ST0 and ST1.Did you use name or number order?Correct is _SPC 21, ST1 22 and ST0 23.But anyway, if CPU is accessing that FPU and I/O map is correct something is not right.If the FPU is doing its own the earlier CC address can be a result from that and so nothing real.Can you easily remove that FPU chip in one piece?If you have a real solder sucker in hand you may also try disconnecting the _SPC pin only.It happens so that you suck the through hole empty and position the pin in the middle of the empty hole.You can of course use some insulation aids, but that disconnecting used to be pretty easy back then.Just push the pin with something towards its body and if its hole is clean enough the pin is disconnected in no time.You seem to have POD 2 12-15 free.Maybe FPU has something, so connect its D0, D2, D6 and D7, pins 11, 9, 5 and 4 to free POD pins.If status D0 is set there is an error.You can also trace _SPC signal backwards.It goes through something before it reaches the CPU.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 13, 2024, 11:09:41 am
content: Last scan:Pod 0 on p. 22 (82C79)Pod 1 on p. 4 (82C79)Pod 2 on p. 17 (68450)Pod 3 on p. 21 (68450)Pod 4 on p. 29 (68450)Pod 5 on p. 27 (68450)Pod 6 on p. 31 (68450)Pod 7 on p. 19 (32081)Pod 8 on p. 20 (32081)Pod 9 on p. 21 (32081)Pod 10 on p. 17 (CPU)Pod 11 on p. 18 (CPU)Pod 12 on p. 11 (32081)Pod 13 on p. 9 (32081)Pod 14 on p. 5 (32081)Pod 15 on p. 4 (32081)

author: m k
author_rank: Super Contributor
timestamp: September 13, 2024, 02:09:27 pm
content: Something went a bit off again, I think it's better to make a new setting.Earlier can also be from very beginning where very basic tests are on the run.It's also possible that some of the add-on cards are using the FPU.Though Not likely.First use a multimeter and check CPU and FPU data connections.Are next pairs connected?CPU D0 pin 5 and FPU D0 pin 11CPU D1 pin 4 and FPU D1 pin 10CPU D8 pin 61 and FPU D8 pin 3CPU D15 pin 54 and FPU D15 pin 16Earlier block diagram indicates that they are, it's very possibly so also.My guess is that they are not, somewhere is a transceiver in between.Leave POD 1 CPU addresses as they are.Change POD pins from CPU 53 to 9 and 49 to 22.Then POD 2.Change POD pin from DMAC 31 to 28andPOD pins from FPU 20 to 22 and 19 to 23.Move POD 2 10 to CPU _IPL0 pin 25andPOD 2 11 to CPU _IPL1 pin 24.Trig to POD 2 09, FPU _SPC pin 21 going low.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 14, 2024, 02:02:43 pm
content: The connections between CPU and FPU (5-11 4-10 61-3 54-16) are perfect.Unfortunately I can't get Pod 2 to work on the logic analyzer (I suspect it doesn't work at all!).... Only Pod 1 works!

author: m k
author_rank: Super Contributor
timestamp: September 14, 2024, 06:50:07 pm
content: Ok, 16 channels then, not a problem, just few hops more.Since FPU is active we'll continue from there.Directly connected data lines are good, no need to wonder anything.POD 00 68000 51 (A22)POD 01 68000 44 (A16)POD 02 68000 41 (A13)POD 03 68000 40 (A12)POD 04 68000 39 (A11)POD 05 68000 38 (A10)POD 06 68000 24 (_IPL1)POD 07 68000 25 (_IPL0)POD 08 68000 9 (R/_W)POD 09 68000 22 (_BERR)POD 10 32081 23 (ST0)POD 11 32081 22 (ST1)POD 12 32081 21 (_SPC)POD 13 68450 11 (_DTACK)POD 14 68450 29 (_BEC0)POD 15 68450 61 (_UAS)Trig again to POD 12 going low.DMAC _BEC0 was missing last time.If it goes down the DMAC will halt.Earlier CCxxxx address can be high data for DMAC.For that DMAC _UAS must go down.Rest are for FPU and its doings.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 16, 2024, 10:40:26 am
content: here is the latest scan according to your instructions.

author: m k
author_rank: Super Contributor
timestamp: September 16, 2024, 04:52:13 pm
content: Recheck POD 10, 11 and 12.Your earlier foto 2 indicates that POD 07 there and POD 12 here are the same.We must be sure that _SPC pin is the one that we think it is.Keep all connections and change trigger to POD 07 going down.That way you should see when interrupt is actually happening.Then it's also possible that you can see the address triggering it.POD pins 00 to 05 indicates that I/O address is 5F1Cxx.MODESET is 5F18xx and after that is nothing, maybe address decoder has a problem.Bottom left of block diagram has a data bus arbiter PAL chip, it connects to DSP and add-on bus controller.If we take that as a guide we have similar PAL chips conveniently around the main board.You can start checking how those PAL16L8A chips are connected, first half and pin 11 are for input, so 10 inputs, that's addresses 23 and down to 14, not enough.High part of I/O is always 0101 111x so something can easily code that separately, conveniently PAL16L8A has 7 output AND matrix.That possible high part chip could also code other I/O address spaces, actually all from work area RAM and E2PROM to 1M DRAM area, and so is not wasted at all.It also means that one input pin that is not CPU address must be connected between all 5E/5F I/O area PAL chips as a source from high order address coder.One possibility is also that there are two PAL chips for high order bits, for design practicalities.But addresses up from A10 must be there or no final I/O selections.So can you find CPU high address pins connected to input side of PAL chips?

author: stfjohn
author_rank: Regular Contributor
timestamp: September 17, 2024, 10:51:54 am
content: Trigger at pod 07.

author: m k
author_rank: Super Contributor
timestamp: September 17, 2024, 06:25:13 pm
content: If you still have that manual take new memory map picture, but from I/O descriptions only.I'm not sure and don't understand few lines.Internal printer is clear, so only upper triplet is needed.Since addressing style is unknown we don't know, but can guess that earlier address 5F1Cxx shouldn't be there.That indicates a program error.Previous set indicated that there are no bus errors.Few earlier sets indicated that only FPU is accessed, now that seems to be different.So FPU, DMAC and keyboard are actually all off.Now address is 5F08xx, so RTC.For what is actually happening we don't have enough POD pins.So we need that address coding system revealed.Something activates those interrupt lines, no doubt, so something is accessed.We know that CRTC is accessed, there's text on screen, but its interrupt behavior is unknown.Now address indicates RTC, but actual _IPL0 drop is missing.Keep POD connections up to 08, CPU R/_W is a good sanity check.Same POD 07 trigger.ChangePOD 09 62421 15POD 10 62421 2POD 11 71054 31 U52POD 12 71054 31 U67POD 13 71054 31 U86POD 14 71054 19 U86POD 15 71054 20 U86

author: stfjohn
author_rank: Regular Contributor
timestamp: September 18, 2024, 08:22:43 am
content: Sorry, I didn't understand the links to 71054...

author: m k
author_rank: Super Contributor
timestamp: September 18, 2024, 11:01:33 am
content: D71054s are those square chips near 12V connector and one above a buzzer.Pin 1 is marked and numbering is normal counter clockwise.So 31 is 3rd last of 3rd side.Last is component number.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 18, 2024, 01:01:08 pm
content: I knew this: but why pods 11 , 12 , 13 on pin 31?

author: m k
author_rank: Super Contributor
timestamp: September 18, 2024, 04:10:28 pm
content: 3 different chips so 3 chip select signals.Last 2 are A0 and A1.Assumption is that all 3 chips have same address signals, but CPU side connection is unknown.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 19, 2024, 12:34:29 pm
content: I'm not sure about the last connection (pod 15) because from the copper side it is really difficult to establish the exact connection to pin 20 of the U86.

author: m k
author_rank: Super Contributor
timestamp: September 19, 2024, 02:39:45 pm
content: No problem, we can forget them.PODs 09 to 13 are up all the time and same time POD 08 goes down.So there is a write cycle and assumed address is 5F34xx, so no chips are selected.Whether that address is right or wrong is not relevant this time.I/O map doesn't include 5F34xx, but 5F30xx is there, that's one bit off.Those steady state address lines have been bugging me all the time, but that alone is not a reason for anything.I'll start rereading old stuff and checking what old pictures are telling now.You can start doing that address line decoder thingy.First some general chip stuff.Externally controlled chips are many times intended to be stacked.Means that all but very few equal control signals are connected together between chips.The one that isn't is chip select or chip enable or something like that, other can be something like output enable.If there are multiple of those special signals they are usually for speed or narrowing needed other signals.One example is a ROM chip, being read only make it simple.First chip enable is asserted and chip start accepting addresses, many chips can do so simultaneously.Then becomes a read moment, for that a chip has an output enable pin.So all chips can be read through one data bus just by asserting individual output enable signals.Usually that goes so that all chips have same address pins connected and chip selects come through high order address decoder, maybe 3to8 line chip.3to8 line chip is fine until wider decoding is needed, 7 address pins is already 16 3to8 line chips.(74xx138, 74xx137, 74xx131)So if you can't see those chips all around this case is probably different.4to16 line chip would be 24 pin 74xx154 or 74xx159 and those are not present.68000 CPU has still few extras, since it's a 16 bit machine accessing 8 bit peripherals.Means that data bus can be mixed.So for now your job is simple, just check which address pins are shorted to where.If 3to8 line chips are only few concentrate to PAL chips.If you can find connections you can continue to the other side of those chips.That address decoder must connect the actual destination chip also.You can also start backwards, but I don't know what the 8245B is, from 3rd set of I/O addresses.Other possibility is that previous 5F1Cxx, but that is also difficult.And most likely more or less all must be clear one day.If many address decoders are needed they are also chained, higher order codes the lower ones.So if you find high address lines from one decoder that is possibly the only one.68450 DMAC _CS is 17.82C79 keyboard controller _CS is 22.62421 RTC has two _CS pins 15 and 2.X2864 E2PROM _CS is 20.D71054 timer _CS is 31.HD63265 FDC _CS is 10.HD63484 CRTC _CS is 5.TMS9914 GPIB _CE is 3.NS32081 FPU _SPC is 31.

author: m k
author_rank: Super Contributor
timestamp: September 20, 2024, 08:08:12 am
content: When those connection searches start irritating too much you can do some analyzing.Leave POD 00 to 05 as they are.POD 06 63484 5 _CS CRTCPOD 07 71054 31 _CS U52 timerPOD 08 71054 31 _CS U67 timerPOD 09 71054 31 _CS U86 timerPOD 10 68450 17 _CS DMACPOD 11 62421 2 _CS0 RTCPOD 12 62421 15 _CS1 RTCPOD 13 32081 21 _SPC FPUPOD 14 8279 22 _CS KBCPOD 15 9914 3 _CE GPIBTrig POD 06 to 15 going down, one by one.We know that CRTC goes down, all others are unknown.Estimation is that many wont go down.Normally only one is allowed to go down at the time.Here both RTC pins can go down simultaneously.Some other pairs are also theoretically possible.

author: m k
author_rank: Super Contributor
timestamp: September 21, 2024, 12:31:17 pm
content: I'll continue with the idea that motherboard is fine and problem is a wrong program and so a bad ROM chip or its access.So your third task, check how data lines go, that's easier since there are less variations.Compared to others DMAC is different, it has full data bus.So you only need to check how few pins from its 2nd side goes, pins 33 to 36 should do.Block diagram has those buffers between DMAC and CPU buses.xx244 is 8 bits to one direction.xx245 is 8 bits to both directions.Those 2 block diagram blocks right of DMAC.They are also both double wide, it's 16 bits wide bus.So probably logic chips between CPU and DMAC.Then between DSP chip and euro-connectors are three logic pairs.xx175 xx245xx244 xx374xx374 xx245xx374 is 8 bit latch.xx175 is 4 D-flops with Q and _Q outputs, it's possibly QD block diagram block above Advantest chip.Chips above and right of TC514256 4 bit data RAMs are most likely for their control.xx157 is 4x 2to1 line multiplexer.MB81C78 8k x8 static RAM is pictured in between DSP and bidirectional buffers, left side can go up, but can't reach the CPU.xx138 left from D10 LED can be address decoder for those RAMs.You can generally skip all these other side parts, but keep them in mind.The whole board is made by same folks and they will follow their principles.68000 has a system for 8 bit data, it also has a system for 8 bit data of high side of its data bus that is internally moved to low side.Based on block diagram picture you should find all those upper narrow data peripheral chips connected to somewhere in CPU data line.

author: m k
author_rank: Super Contributor
timestamp: September 21, 2024, 05:46:14 pm
content: Don't worry about multiple replies.I'm just sitting here feet up and watching pictures, and poking the keyboard when something comes up.5F1Cxx ?5F08xx *CSRTC5F34xx ?It seems that I've all the time seen that CRT controller is somewhere in the I/O map as a CRTC, somehow I've mixed it with Real Time Controller.So actually 8245B is a CRT controller, but the old one, so it is no more and current one can be very different, or it obviously is very different, but how different its I/O map is, we don't know.So address 5F34xx can be very legit.82C79 KBC, RTC, X2864 E2PROM and program module, those are clearly a group.I/O map indicates that one D71054 timer is also part of it.*BZON is easily a buzzer and can be controlled by 1/3 timer of the chip near by.*INTCLR is tricky, or maybe not, maybe it's for the connector near by, INTensity ControLleR perhaps.Counter chip is bidirectional, so max 4 addresses can be for 1 counter chip.If that style is used then connections can be coded through something instead of its A0 and A1 directly to CPU address lines.Upper edge of ROM module has some logic chips.xx00 is 4x 2 input NANDxx240 is 8 bit buffer/driver, same as xx244.xx138 is 3to8 line decoder.xx02 is 4x 2 input NORxx139 is 2x 2to4 line decoder.The module has also 3x 32 pin connector and all of those logic chips are not needed for memory access.So memory part is different, but DIP switches can be a part of the group.xx240 is also very suitable for those DIP switches, resistor network also.On the other hand many traces go directly past that chip, maybe it's just an angle of a picture.2nd part is clearly for DIP switched, 1st one not so sure.Top right of the ROM module picture is connector J2.It's clearly connecting something near those DIP switches up or down.If those DIP switches are a MODESET there must be a 5F18xx coded to that xx240.Whole address contains 16 bits, that's too much, but last 8 or 9 is easy.Since I/O map is divided as it is, it's more likely only 8 bits.---- ---- 0001 1000 xxxx xxxxVariations are many, either gates first or decoders first.If both xx240 parts are uses 2x 2to4 line is spot on, that's also spot on for ROM chips.If decoders are last then final address polarity doesn't matter.xx02 pins 8 and 11 are shorted, it's clearly narrowing something.If address coding is more predefined, like is rational if motherboard parts are included, the rest may be as narrow as 2 or 3 bits.Then single decoder chip would be enough.If MODESET is 8 bits wide with only 1 address, xx240 enable pins 1 and 19 are connected.Output is 3-state, so no other latches are needed.More than 1 MODESET address would be better, then sanity check is also possible with unused data bits.And if that is the case then also 5F1Cxx address can be a completely legit thing.Possibility is also that 3rd I/O map set is totally legit.8245B CRT controller has the whole 8 bits wide access area in use.If so then those 2 right side timer chips are pretty unknown.3rd I/O map set has those RD things.Only block diagram missing part is front panel encoder, but it's totally elsewhere and very simple.Back panel has many input and output clocks, but all of those unknowns are RD, like read and so for input, or it can be Rear Data and so address 5F34xx is back as unknown.*SOFTRST can be the upper timer on the right.There are many things that can trigger it, like those clock chips.So it can be a watchdog.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 23, 2024, 11:22:56 am
content: How do I figure out which is pin 5 of the 63484 from the copper side of the circuit board?

author: m k
author_rank: Super Contributor
timestamp: September 23, 2024, 02:20:34 pm
content: The "dot" in the middle of the upper edge is index, so position 1 is above it.Then normally counter clockwise, so 4th left is 5 and last is 9.Seems that you must measure where that pin goes.E,I read that there are also non standard sockets.Real or not, better do a measurement.Standard goes so that last pin of a side has no pair and outer is smaller, but pin 1 moves to inner side when pin count goes low enough.For 68 pins outer row of 1st side is for odd numbers, so 5 is 3rd from the end.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 24, 2024, 02:48:59 pm
content: here is the scan as per your last post.

author: m k
author_rank: Super Contributor
timestamp: September 24, 2024, 06:03:21 pm
content: That's a completely sane picture.No chip is selected because address is 5F1Cxx and that position is empty.So for now your problem seems to be a program error.But maybe we can gain something from those _CS pins.So change trigger one by one to POD 06 to 15 going low.If it's triggered take a picture.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 25, 2024, 11:23:25 am
content: Trigger pod 06, 07, 08 : nothing changed.

author: m k
author_rank: Super Contributor
timestamp: September 25, 2024, 06:15:20 pm
content: Pictures are rational and real I/O map seems to be quite different, so a pictured one can be only a principle map and for now program error is no more.But now you must explain a bit how you made those pictures.I was expecting that _CS POD line going down is visible.We also know that CRT controller is accessed, so its _CS line goes down, but now it's missing.Pictured addresses5E00xx POD 13 32081 21 _SPC FPU5E04xx 5E08xx 5E0Cxx5E10xx 5E14xx 5E18xx 5E1Cxx5E20xx POD 11 62421 2 _CS0 RTC5E24xx5E28xx POD 12 62421 15 _CS1 RTC5E2Cxx POD 14 8279 22 _CS KBC5E30xx 5E34xx5E38xx POD 09 71054 31 _CS U86 timer5E3Cxx5F00xx5F04xx POD 15 9914 3 _CE GPIB5F08xx5F0Cxx POD 10 68450 17 _CS DMACMissingPOD 06 63484 5 _CS CRTCPOD 07 71054 31 _CS U52 timerPOD 08 71054 31 _CS U67 timer

author: stfjohn
author_rank: Regular Contributor
timestamp: September 26, 2024, 11:46:14 am
content: I took the measurements exactly as you suggested. The only doubt is that pin 5 of the 63484 is not the one in the photo where I soldered the strip...

author: m k
author_rank: Super Contributor
timestamp: September 26, 2024, 02:37:11 pm
content: I'd put it to same position.So for now a guess is that "no change" is CRTC.Earlier stuff,picture of reply #78, how was that triggered?Lower part of ROM module, leave it if it's difficult,connector side has probably some RAM chips, but other end has also something, more RAM chips or something else?So I've been seeing things again.ROM board J2, instead of up or down it's obviously connecting a pin of external something.Can you easily connect a POD pin to ROM board HC240 pins 19 and 1?It's for finding MODESET, just leave it if it's too complicated.Can you scroll analyzer screen left and right, can you see somewhere that _CS POD pin goes down?Few logic chip IDs needed.Don't do it if you can't do it without dismantling the current setup, not that important.1 left of DMAC and 5 under it, 1 is clear, rightmost seems to be 139.1 right of FPU and 2 under it.7 around a bottom right corner, the bigger one seems to be 74F something, but maybe not.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 26, 2024, 03:13:14 pm
content: I did the scans again anyway, because I noticed that, for each trigger pod, the scan varies at least 4 times before stabilizing.

author: m k
author_rank: Super Contributor
timestamp: September 26, 2024, 05:23:49 pm
content: Change trace mode to single.You must get pictures where _CS POD signal goes down like POD 06.Now we know for sure that this 5E10xx address is for CRTC, all others are unknown.Addresses are possibly real, but they can't be connected if triggering POD signal is not going down.There can be other addresses that have happened before or after trigger and are now in picture.All pictures that are aborted are probably not triggered.Others have the actual happening somewhere else, possibly later in data.

author: m k
author_rank: Super Contributor
timestamp: September 27, 2024, 07:21:42 am
content: Quote from: stfjohn on September 26, 2024, 03:13:14 pmOk, my bad, I didn't nag enough.I forgot your background and assumed that you've used external trigger.Digital signals are not defined by repetition, that's for next level.There are no practical settling time either, every moment counts.For low frequency things like this these moments are transitions, so change of level either up or down.There is of course a transition delay, but that's it, after that the same thing can't happen again before that same transition happens.So it's either rising edge or falling edge, usually only one, but 68k CPU can use both.CPU R/_W pin defines writing when it goes low, so falling edge.Read doesn't happen when level goes up, it's defined elsewhere.Those read and write moments are part of cycles, there are also many other cycles.Before those actual read and write operations have meaning there must be an object.That object must also have time to adapt, transition delay again.Same with all parts around that happening, like buses.Cycle includes all of those moments, one cycle lasts many clock pulses.Generally cycle must end before next can start.Since R/_W pin defines writing it can also define its end by going up.That is a normal procedure, down is starting and up is ending for generally everything of falling edge things.Inside a cycle are different periods.It is said that certain time period the thing is valid, like data in write cycle.So at some point when R/_W pin is down the data must be present, address also.Since everything are based on clock pulses and everything can't happen at once there is a propagation delay.That's sort of a settling time, but not for a signal, it's settling of different parts of a circuit and can last more than one clock pulse.For that datasheets have cycle timing pictures.When chip is accessed it is first selected.There can be many chips selected at once, but then occupied bus must support that.Usually address bus is for many and data bus for one, in our case I/O address bus is also for one.Chip can also be valid only when it is selected, so when _CS pin is down, underline means active low.

author: m k
author_rank: Super Contributor
timestamp: September 27, 2024, 07:28:24 am
content: Quote from: stfjohn on September 26, 2024, 03:13:14 pmOur POD 00 to 05 are 6 address pins of 23, so there is an assumption that those 6 can indicate enough.Your latest set of pictures have POD 06 going down, that moment is only moment when that chip is selected.So address pins of that period are for that POD 06 chip.All other addresses, before and after, are for something else.Bright side is that those pictures have also many other chip select lines.So if none goes down the address is also for none.Down side is that 6 address pins of 23 can't tell much without that chip select line.But we have other pictures and there is a pattern.My guess is that those wide up, short down and wide up again sets are real, and if CPU R/_W pin is connected it is just like it was earlier when it was connected.POD 06 5E10xx 63484 5 _CS CRTCPOD 07 ---- 71054 31 _CS U52 timerPOD 08 ---- 71054 31 _CS U67 timerPOD 09 ---- 71054 31 _CS U86 timerPOD 10 *** 68450 17 _CS DMACPOD 11 *** 62421 2 _CS0 RTCPOD 12 *** 62421 15 _CS1 RTCPOD 13 ---- 32081 21 _SPC FPUPOD 14 ---- 8279 22 _CS KBCPOD 15 *** 9914 3 _CE GPIBDash line pictures are aborted, so no trigger.Asterisk line means that somewhere in the data that _CS POD pin goes down and there is an address for that chip.Chip select of floppy controller is not connected.Same with stuff like MODESET.something else in a picture, none of abovePOD 09 5F1CxxPOD 11 5E30xx *POD 12 5E2CxxPOD 13 5E30xx *something else in earlier set of pictures, none of abovePOD 09 5E38xx *POD 10 5F0CxxPOD 11 5E20xxPOD 12 5E28xxPOD 13 5E00xxPOD 14 5E2CxxPOD 15 5F04xxsomething else in even earlier picturesR/_W signal present and writing5F1Cxx5F08xx5F34xx* different timing

author: stfjohn
author_rank: Regular Contributor
timestamp: September 27, 2024, 03:29:53 pm
content: I redid everything using the ext output trigger of the HP 1651A and with single acquisition. However, each time, I get different scans... I don't know!

author: m k
author_rank: Super Contributor
timestamp: September 27, 2024, 06:01:49 pm
content: Change POD 06, connect it to CPU R/_W pin 9.Then do POD 07 to 15 once more.Maybe those differently timed signals are also addresses.If new POD 06 goes down under them we know they are.You can also scroll left and right to see different settings.Then put analyzer a side for a moment, leave test pins as they are, if there is no harm, and pull motherboard out, or not if you're already familiar enough for measuring the under side.No need to get stuck with the analyzer, but don't give it away if you can keep it.Then start finding motherboard traces, that's at least more exact science.Concentrate to high addresses of CPU first, A22 down to A20, pins 51, 50 and 48.Check if you can find a connection, reply #74 has some chip stuff.PAL chip pins 1 to 9 and 11 are inputs, CPU addresses can be connected there.3to8 line 74138 pins 1, 2 and 3 are inputs, that's other promising target for CPU addresses.Next level goes so that previous chip's output is next chip's output enable, for 74138 that's pins 4, 5 and 6.If you find a connection between 2 logic chips you can start finding lower CPU addresses from the receiving chip.Since some I/O area addresses are not used there can be gaps all the way, that would be a partial addressing where many addresses mean the same thing and nothing unusual.There can be also a single gate coding those unused address pins, since 74138 has 3 enable pins that's even a probable design, but 1 must come from the higher level 74138.If finding traces start irritating update those unknown chips from end of reply #83.It's likely that one logic chip is not in order, so you possibly need to find it anyway.I'll check if I can see the light in analyzer manual.Seems that the current setup is 16 timing and 16 state channels.We can possibly see more if we use 32 state channels.With luck we can then forward the program step by step and finally see exactly what and where is the problem.Since many I/O chips are 8 bits wide we can drop half of CPU data bus off and use freed pins as _CS pins and then use them as stepping stones for software hops.Pictured addresses, not for triggering _CS pins.POD 06 5F04xxPOD 07 5F0CxxPOD 08 5E14xx *POD 09 5E10xx * no CRTC _CSPOD 10 5E2CxxPOD 11 5F30xxPOD 12POD 13 5E38xx *POD 14 5E34xx *POD 15 5E28xx ** different timingE,Very early picture 3 and POD 11 of reply #84 have similar happenings.Maybe 5E30xx has something to do with the problem.

author: m k
author_rank: Super Contributor
timestamp: September 28, 2024, 07:34:36 am
content: Triggering.From Timing Trace menu you can check your triggers.Then Find Edge box under a label has a dollar sign if trigger is set.Disable wrong ones by changing the pop up to period signs.Then set the correct one to down arrow, select done and a dollar sign appears.Trigger is now set.Next you hit Run, soft boot the machine and hope the best.If trigger is found before booting you can skip it.Address is above the moment when triggered signal is down.If soft booting is not possible the trigger may need a triggering delay.Every _CS signals go up when problem machine start operating, so there shouldn't be any unwanted falling edges.E,triggering signal can't stay down.It being down means that address and data bus are occupied.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 30, 2024, 01:51:51 pm
content: Sorry: even with the trigger set as you suggested, then connecting the logic analyzer's trigger output to the various pods (obviously varying the trigger setting from one pod to another), I still get different readings every time I turn on the Advantest!

author: stfjohn
author_rank: Regular Contributor
timestamp: September 30, 2024, 03:38:17 pm
content: This is the first trigger that I then enabled on pod 06. Then I enabled, one at a time, the triggers on the other pods towards the right.

author: stfjohn
author_rank: Regular Contributor
timestamp: September 30, 2024, 03:42:43 pm
content: (trigger pod 15)

author: m k
author_rank: Super Contributor
timestamp: September 30, 2024, 05:02:34 pm
content: Something is not right.Your picture of Timing Trace Specification is also different than expected.I thought there will be only one edge specifying position.Your Timing Trace Specifications picture has only POD 1, like the whole POD.I don't know what that means, maybe something earlier is needed but not defined.Maybe something you did cleared some other things.One more time then.First Timing Format Specifications, press Format key.There you connect physical POD pins to labels.Every physical pin should be assigned to one label.So finally you have signs stepping left and down.I understand Timing Trace Specifications from the Getting Started manual so that you have a physical pin position for its label marked with down arrow.So the arrow in your earlier picture should be for POD 1 06, but your picture doesn't have individual pins at all.Maybe the manual I'm reading is for different software version.If your Timing Trace is still the same with only POD 1 selection available and Timing Format was all set then no need to do new pictures.But if you changed Timing Format then you can try again.Timing Trace like you have is completely rational, but resulting waveforms are not.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 01, 2024, 09:36:43 am
content: Is this the correct procedure?

author: m k
author_rank: Super Contributor
timestamp: October 01, 2024, 10:00:42 am
content: No.Only rightmost pin to 1st label.Then 2nd pin from right to label B, 3rd pin from right to label C and so on.Now your pictures are so that all physical pins are connected to POD 1.So POD 1 row is picturing all waveforms on top of each others and other rows are empty.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 01, 2024, 04:07:50 pm
content: And now?But, in the "trace" screen, going to "edge", I can no longer get the dollar symbol!

author: m k
author_rank: Super Contributor
timestamp: October 01, 2024, 05:39:09 pm
content: Reference Manual is not clear.Add one more label and assign all bits to it, like the original POD 1 was.Can you use that as a trigger source, like you did earlier?If not then start over, put trigger source to 1st POD 1, like it was and add individual labels after it, so that finally you have 17 labels, POD 1 with all pins and 0 to 15 individual pin assignments.Can you then use triggers, like earlier when it worked?

author: stfjohn
author_rank: Regular Contributor
timestamp: October 02, 2024, 02:49:00 pm
content: I checked with the oscilloscope: whatever combination I use, at the "ext trigger" output of the logic analyzer, there is no signal! I have a doubt: I have always connected the "clock" pin of the analyzer probe to pin 15 of the CPU: is this a correct procedure?

author: m k
author_rank: Super Contributor
timestamp: October 02, 2024, 05:40:20 pm
content: First one other thing,I/O map picture has *5E04xx FPUSEL and *5E08xx FP[V/Y]POL.Maybe latter is polarity something.Since clock is clearly working, no overly short pulses, keep it.Trigger is different, I don't really understand how this machine operates behind the scenes.Getting Started Manual section 5 is for Timing Analyzer.There page 5-6 has a picture of 2 defined labels, page 5-8 has defined 1 edge.After that it does Run and after that it shows a Timing Waveforms display and all waveforms are the same.There label is named RAS but display is RAS 00 for all rows.After that it changes the 2nd label to CAS and display is CAS 00, can't say what that 00 is.So you should be able to do the same and change all rows to their individual pins that you have assigned earlier.After that your picture should be so that all labels are different, triggered to 1st label and rest are what they are.If you have not assigned any pins to other labels they all should be the same, up or down.Your picture should also be so that triggered situation is center of the screen.If you now want different waveforms you do new Run, or scroll around to see what other things have happened.One difference between manual pictures and your earlier waveform pictures.Manual picture has 'to trig' fields on the upper section, so maybe your trigger has never actually been there.Above Then Find Edge field is Present For fields.There must be something, > 30ns is fine.It means that triggering level must stay longer than 30ns before it is accepted as a trigger.External trigger input is for Armed by field of Timing Trace window and BNC Input selection there.Don't know how it operates, maybe it's for general start of data collection since its other selection is Run.I also remember from somewhere that some analyzers are tricky, maybe this is one of them.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 03, 2024, 02:19:15 pm
content: I managed to get the dollar sign on all the labels, but the result doesn't seem to change...

author: m k
author_rank: Super Contributor
timestamp: October 03, 2024, 03:54:22 pm
content: I don't really understand what I'm seeing.POD 06 pin 9 CPU can be rational, it can be the first time R/_W goes down after reset.Seems that you must add that other POD and make it a State Analyzer.But anyway, only one trigger should be active at the time.Turn Markers on to see what you have.Overall timing is also something that it shouldn't.There are some close to 50MHz pulses and the CPU is 10MHz thing.Change Time/Div to 1000ns and do POD 06 pin 9 CPU picture again.Then just press Run and take another picture of what you got.First picture is from the very beginning and second from random position later.Maybe we can learn something from their differences.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 04, 2024, 04:09:02 pm
content: It's impossible: now the analyzer reads only 8 channels! The self test says that everything is fine, but evidently it is not so! I don't understand anything anymore! In any case the readings are always different every time I turn on the Advantest!

author: m k
author_rank: Super Contributor
timestamp: October 04, 2024, 05:28:40 pm
content: Then we go back.Earlier pictures have POD 1 and numbers after that.That latter part must mean connected POD pins.When you named those other labels you didn't add that "all" text, so it is internally created.Means that if you have more than a single bit assigned to the label the machine add rows for all bits automatically.So I think your 1st picture of reply #92 is right and so is reply #95.Means that all bits to POD 1 and all other labels to trash.After "POD 1" is "00" text, the latter must be a connected bit.Next 'B' label has "all" text, no idea why the ending is not "01" that "POD 1 00" line indicates.Go to System Configuration menu, maybe you can put the machine back to its initial state.You have Analyzer 1 and 2, if both are on turn other one off.Then change the Type of the active one to State.Then select some other menu, stuff there are what they are, that's not important.Then go back to System Configuration menu and change the active analyzer to Timing.If you then go to Timing Format you should have a default settings.Maybe that is already like you had in reply #92, but without those extra labels.Next you can go to Timing Trace menu, POD pin 00 is right and 15 left.So for triggering POD pin 06 you select 7th from right.Next you should be in Timing waveforms display with original POD 1 lines.Turn markers on, you should have only one trigger available.Markers mean that you can check times between O and X, so no use for us.Now you can tap Run and check what happens.If waveforms are fine then fine, if not then go back to Timing Trace menu and take the trigger off.Tap Run again and now the picture should be like it originally was.Seems that the trigger must be delayed, so maybe that state analyzer side of the machine is needed.One other possibility is to have a counter/timer, feed it with a clock pulse and flip external trigger when certain amount of pulses have happened.Why's that.Since all signals seem to pulse very early we must find means to delay the trigger so much that this first phase is gone.For that we can use external trigger input, but I don't know where to connect it.With state analyzer we can arm the timing analyzer part starting when high address lines (A23 to A20) have a state 5 (0101).Assumption here is that when I/O is accessed first time the system has reached its normal operating phase.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 06, 2024, 11:43:19 am
content: Ok. The fact remains that, by enabling labels, the plotted channels are always only 8, while before all 16 were plotted!

author: m k
author_rank: Super Contributor
timestamp: October 06, 2024, 03:40:09 pm
content: Those extra labels were clearly a wrong idea.What you get if you change Time/Div to 1000ns, 1us or what ever it is?Without any triggers the machine collects data from the Run moment as long as it has memory.With luck you can see some _CS pins going down.It goes so that you turn Advantest on and after a short moment tap Run from HP.Then you scroll left and right, and find something or not.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 07, 2024, 03:52:30 pm
content: last scan...

author: m k
author_rank: Super Contributor
timestamp: October 07, 2024, 06:33:38 pm
content: None of those pictures make any sense.I can't even guess what there could be, other than HP doing its own.Timing Trace menu has a field Find Pattern.Put there xxx1.Now you should have a trigger delay, but I'm not sure.What you get if trigger is POD 06 going down?It should be so that trigger enable start waiting address 5E0xxx.(5E0xxx, 5E4xxx, 5E8xxx, 5ECxxx)if you change Find Pattern to xxx3 the enabling address is 5F0xxx.Both cases then trigger first write after that address.Most likely there are more than one write, so you should see a sane address and possibly one _CS.There can be more, so scroll around.E,wrong address space.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 08, 2024, 10:26:39 am
content: With the configuration you suggested I don't get any scans.

author: m k
author_rank: Super Contributor
timestamp: October 08, 2024, 06:14:53 pm
content: Pretty clean.Change Pattern back to xxxx and remove all triggers.Put Advantest on and wait text on screen.Then tap Run.If picture is stillemptytotally different than original pictures go to System Configuration menu and change Analyzer.Maybe POD 1/Analyzer 1 connection has a problem.You must turn active analyzer off first if you want to use POD 1 with Analyzer 2.If POD 1 and Analyzer 2 is not possible change to POD 2.If POD 2 and Analyzer 2 is ok try POD 2 with Analyzer 1, if possible.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 09, 2024, 03:44:54 pm
content: I've tried every possible combination, but I always get more or less the same image.

author: m k
author_rank: Super Contributor
timestamp: October 09, 2024, 07:14:32 pm
content: If you compare this last one and first of reply #107 you'll see that generally they are the same, but details are different.Even that both are supposed to be from the equal moment.I'd say that HP is doing its own.So are we now swapping the repair project?It can be a simple contact thing.We know it worked.

author: m k
author_rank: Super Contributor
timestamp: October 10, 2024, 10:03:56 am
content: Previous empty waveforms display informs that the machine can possibly read what is coming in.All pins are more or less the same, so Pattern xxx1 is never happening.No error messages from the machine, so problem is more likely close to PODs.The service manual I found online doesn't have schematics, but power supply voltages seems to be there.Maybe one voltage for PODs is missing, or has lost its filter capacitor.Other "easier" possibility is a POD clock.Seems that Timing format uses internal 100MHz clock, maybe it's bad.Change Analyzers to State format, then POD clock can be selected without a doubt.Connect POD clock to CPU CLK pin 15 and POD 01 to CPU E pin 20, it's 1/10 of CPU CLK, 40/60 up/down duty cycle.Leave other POD pins as they are.Put Search Pattern as 0000 tap Run and turn Advantest on.If POD is working you should see an empty display, POD 00 A22, POD 06 R/_W and any _CS pin can't be all down.If display has a rational data the lowest byte should have that 40/60 pattern first and later it's more scrambled.If display has 0000 and FFFF with some hiccups the error is still present, but POD clock is also present.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 10, 2024, 03:03:04 pm
content: Here last images,

author: m k
author_rank: Super Contributor
timestamp: October 10, 2024, 05:17:46 pm
content: So POD clock is there, but POD pins are not rational.Address bits are right and _CS pins left.So result is the same as Timing display, style is a bit different since clock is 1/10 of internal Timing clock.CPU pin E is free rolling, so it should be visible somewhere.Means that HP PODs are not operational anymore.POD input is registered, so that part is operational, but actual POD data is just noise.If you want to go forward with the HP you must open it.Since all combinations are the same there is a good possibility that a supply voltage near PODs has given up.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 11, 2024, 11:13:27 pm
content: I opened the logic analyzer and checked the voltages as per the service manual: they are all perfect! Furthermore, the analyzer passes all the self tests correctly except for pod 2 (which, for some strange reason, is not checked...).

author: m k
author_rank: Super Contributor
timestamp: October 12, 2024, 11:12:53 am
content: Next you need to check that needed voltages reach the Pod.Page 4-6 of Service Manual has a Pod Threshold adjustment.Check that its voltage is rational.You can also do one more POD signal test.Turn Advantest on and wait for the text, no booting, just tap Run when needed.Put Analyzer Type Timing and leave all POD pins as they are.Change Timing Format from TTL to User-defined and put threshold away from 1.6V, that is a TTL level.When threshold is low enough your Waveforms display should start putting out random up and down levels.When threshold is high enough all POD pins should show straight line of low level.If POD pins continue showing all up or down, like before you know that the picture is not from POD pins.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 13, 2024, 10:13:56 am
content: Here voltages checked. All right!

author: m k
author_rank: Super Contributor
timestamp: October 13, 2024, 01:34:25 pm
content: Leave Format as User-defined and take test pictures when threshold is 1.6V, 6V and 0.4V.If 1.6V picture is what it should be others are not needed.If all are the same you can start looking in the machine and figuring out where those POD signals go.When Advantest is on you can scope POD 01, it's that 1/10 of CPU clock and 40/60 duty cycle, should be different than others.Check also that IDC connector pins of the machine and POD are as they should.Maybe somewhere is a cracked solder.It's also possible that GND between machines has a connection problem.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 14, 2024, 09:44:13 am
content: Pod Clock at pin 15 CPUPod 01 at pin 20 CPU

author: m k
author_rank: Super Contributor
timestamp: October 14, 2024, 07:08:54 pm
content: My bad, insufficient instructions.But we are advancing, the machine seems to be operational again.POD 01 is 1000ns per cycle as it should.Go back to situation of the first picture and start connecting POD pins from 15 and up one by one like they were and tap Run after every added pin.POD 01 shouldn't change and whether POD clock is connected or not shouldn't matter.So is POD 01 still cycling after all from below are connected?POD 07 71054 31 _CS U52 timerPOD 08 71054 31 _CS U67 timerPOD 09 71054 31 _CS U86 timerPOD 10 68450 17 _CS DMACPOD 11 62421 2 _CS0 RTCPOD 12 62421 15 _CS1 RTCPOD 13 32081 21 _SPC FPUPOD 14 8279 22 _CS KBCPOD 15 9914 3 _CE GPIB

author: stfjohn
author_rank: Regular Contributor
timestamp: October 15, 2024, 10:51:24 am
content: Following the procedure you indicated, all pods from 15 to 07 go down, and pod 01 still cycling.

author: m k
author_rank: Super Contributor
timestamp: October 15, 2024, 12:22:39 pm
content: Excellent, but no idea what has happened.If you have opened the HP, keep the cover off, it may have a heat issue.If cover is still on the problem can be a connection issue anywhere and come back anytime.ConnectPOD 06 68000 9 (R/_W)Tap Run and if POD 06 is pulsing disconnect POD 01.If POD 06 is not pulsing move POD 01 connection to POD 06.Pulsing is your sanity check, that the situation is still ok.Next connect addresses from below, one by one again and tapping Run after every adding.Can you still see pulsing after all are connected?POD 00 68000 51 (A22)POD 01 68000 44 (A16)POD 02 68000 41 (A13)POD 03 68000 40 (A12)POD 04 68000 39 (A11)POD 05 68000 38 (A10)If everything is still ok do that earlier Pattern thing.Go to Timing Trace menu and change Find Pattern to xxx1.Tap Run, what you get?Picture can be empty and it is not necessary a fault.If picture is empty boot Advantest, what you get?If picture is not empty change Pattern and tap Run.Continue changing Pattern until you get an empty picture.Patternsxxx3xxx5xxx7xxx9xxxBxxxDxxxFWhen picture is empty boot Advantest, what you get?Maybe better take a photo even if picture is not empty, it may have some new info.Different Patterns represent different states of POD pins 01 to 03, POD pin 00 is always high.POD pins 04 and 05 can't be included, POD pins 06 to 07 are disturbing since they are part of the rightmost 'x' of the Pattern.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 15, 2024, 03:42:14 pm
content: Photo 1: pod 6 instead of pod 1 (CPU pin 20).Photo 2: connected addresses from pod 00 to pod 05.With Find Pattern XXX1 the image is empty (waiting for trigger).Photo 3: starting Advantest.Photo 4 - 5 - 6 - 7: changing the various patterns and always restarting Advantest, otherwise the image remains empty.

author: m k
author_rank: Super Contributor
timestamp: October 15, 2024, 05:49:36 pm
content: Check POD 12, there seems to be something wrong.If it's clearly connected swap PODs 06 and 12.Tap Run, what you get?POD 12 should be cycling and POD 06 being high.If POD 06, the old 12 remains low we have a problem.It means that _CS1 of RTC is messing its access, but it has not have a problem earlier, so that shouldn't happen.Change Time/Div to 1000ns and do different Patterns again, but leave first and last out.Scroll right and left to see if you can see POD higher than 05 going down, other than 12, 11 or 08.If Pattern generates a picture like Foto 3 or 7 try again.Maybe happening is random enough that Pattern doesn't happen every time before things settle.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 16, 2024, 11:15:38 am
content: photo 1: pod 12 and 06 as before.photo 2: pod 12 and 06 swapped.photo 3: various patterns (always restarting Advantest, otherwise the message "waiting for trigger" appears and the image is blank.

author: m k
author_rank: Super Contributor
timestamp: October 16, 2024, 07:16:50 pm
content: Maybe you should get an extension cord with a power switch for Advantest.R9211 B/C Operating Manual page 3-9 has After Turning the Power ON.There after PROM check is FPU check, few steps before that is Timer check.Timer is not exact but FPU is.One can assume that PROM check is before anything appears on screen, but that's finally just guessing.FPU check then is so exact that finding it can be some kind of a goal, but we don't know exactly when it should happen.Other goal can be finding when CPU's _ILP0 and _ILP1 are going down.But since POD 12 is what it is we must treat it as a cause.POD 05 of foto 3 is also odd, but maybe it's a coincidence.Sokeep POD 00 to 05.POD 06 68000 25 _ILP0 CPUPOD 07 62421 15 _CS1 RTCPOD 08 71054 31 _CS U67 timerPOD 09 71054 31 _CS U86 timerPOD 10 68450 17 _CS DMACPOD 11 62421 2 _CS0 RTCPOD 12 71054 31 _CS U52 timerPOD 13 32081 21 _SPC FPUPOD 14 8279 22 _CS KBCPOD 15 9914 3 _CE GPIBFind Patternsxx4xxx5xxx6xxx7xTap Run and boot Advantest, what you get?If nothing is found continue with Find Patterns from below.All pictures are possibly giving more information, but PODs 06 and 07 are a priority, so you can stop when those are found.Alternatively scroll around and try to find any other than 11 or 08 of POD 06 to 15 going down.Below Find Patterns are based on what has happened earlier.Means that all of those "possible" addresses have been present, but dropping _CS pins are missing, despite POD 08 and 11.xxC1 (5E00xx)xxC5 (5E20xx)xxC9 (5E10xx)xxCD (5E30xx) POD 08 goes downxxCF (5F30xx)xxD3 (5F08xx) POD 11 goes downxxD5 (5E28xx)xxD7 (5F28xx)xxDD (5E38xx)xxE3 (5F04xx)xxE9 (5E14xx)xxED (5E34xx)xxF1 (5E0Cxx)xxF3 (5F0Cxx)xxF5 (5F2Cxx)xxFB (5F1Cxx)

author: stfjohn
author_rank: Regular Contributor
timestamp: October 17, 2024, 01:21:55 pm
content: With all the combinations you suggested, I always get a blank image with the words "waiting for trigger".

author: m k
author_rank: Super Contributor
timestamp: October 17, 2024, 02:17:32 pm
content: After booting Advantest also?

author: m k
author_rank: Super Contributor
timestamp: October 17, 2024, 04:42:33 pm
content: Keep POD 00 to 05 again.POD 06 32081 21 _SPC FPUPOD 07 71054 31 _CS U52 timerPOD 08 71054 31 _CS U67 timerPOD 09 68000 15 CLK CPUPOD 10 62421 2 _CS0 RTCPOD 11 62421 15 _CS1 RTCPOD 12 68000 17 _HALT CPUPOD 13 68000 25 _ILP0 CPUPOD 14 68000 24 _ILP1 CPUPOD 15 68000 18 _RESET CPUFind pattern 6xxxTap Run, picture should be empty.Boot Advantest, what you get?Try connecting wires to CPU pins 17 and 18, and using those for resetting the machine by grounding both wires simultaneously.Needed time is around 150 clock cycles, so not very long, but much more gentle than on/off switch.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 18, 2024, 10:56:40 am
content: I always get a blank image with the words "waiting for trigger"!

author: m k
author_rank: Super Contributor
timestamp: October 18, 2024, 11:12:37 am
content: Change Find pattern to 9xxx and try again.If you still get empty screen change Find pattern back to xxxx and tap Run.Now you should be back in "normal" waveforms.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 18, 2024, 11:35:17 am
content: With pattern 9XXX image 1.Without selecting any pattern, when Advantest boots, the image is always empty. Pressing run after Advantest starts, I get image 2.

author: m k
author_rank: Super Contributor
timestamp: October 18, 2024, 12:54:35 pm
content: Do it again without image 2, but after image 1 press Run again.What you see?Are you still using Advantest's power switch?E,wrong image.Problem with image 1 is that it has no clock signal.Other is that IPL signals are down and nothing has happened yet.You can also try changing Time/Div to so long that you can see something changing after POD 15 go up and both being in same picture.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 18, 2024, 04:42:06 pm
content: If I press Run again, I see image 1 again.

author: m k
author_rank: Super Contributor
timestamp: October 19, 2024, 10:41:48 am
content: Your machines just don't stop surprising.Do it again, but wait Advantest putting text on screen.If text on screen is not instant count how long its appearing take.Then press Run again.Do you lose that Advantest text on screen?If you do how long before it reappears, close to same as the first time?If text on screen is instant or close to it scope CPU pin 15.Is there a cycling pause when you press Run?Maybe HP is acting up.If CPU pin 15 cycling is pausing or text on screen disappears check +5V.At least FPU pin 24 and RTC pin 18, maybe also 74F161 chips left of crystals.Scope them when pressing Run.None of those peculiar signals are CPU based.PODs 09, 11, 13 and 14, FPU has done it earlier, IPL source is unknown.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 21, 2024, 09:24:41 am
content: The text on the screen appears approximately 3 seconds after the device is turned on and remains fixed on the screen: it does not disappear!

author: m k
author_rank: Super Contributor
timestamp: October 21, 2024, 10:24:49 am
content: That is good.So extra reset and missing clock can be HP something.Maybe second picture is an HP replicate, maybe your two Runs were too close and HP treated them as one.Overload is also possible, but signals are a bit odd.Overloaded pin can affect others, but result is still odd.ChangePOD 06 32081 15 _RST FPUPOD 07 82C79 9 RESET KBCPOD 08 63265 7 _RESET FDCand do image 1 and double Run again, wait with second Run until text appears.If resetting is real all of those above three should act near POD 15, PODs 06 and 08 going down and POD 07 going up.If something is pulling something else then POD 07 can stay down.If POD internals are 8+8 pins and one side is overloading then PODs 06 and 08 can act differently.It's also possible that PODs 06 and 08 are acting differently on purpose, but that means an extra and not really needed Advantest circuit somewhere.Next do the same image 1 and double Run again twice, but use Find Patterns xx8x and 9x4x.Find Pattern xx8x means that reset operation is starting and 9x4x that it's ending.There PODs 04 and 05 are also included, but assumption is that they are both down, as they should be.Then do image 1 and double Run third time using Find Pattern xx4x.Find Patterns xx4x and xx8x have only one pin up, so with bad luck you'll get an unstable random picture.If that happens just try again few times.

author: m k
author_rank: Super Contributor
timestamp: October 21, 2024, 12:39:41 pm
content: Small change.Find Patterns xx4x and 9x4x are most likely working properly.So Advantest off first.Advantest off -> Run -> Advantest on -> wait text -> Run again

author: stfjohn
author_rank: Regular Contributor
timestamp: October 23, 2024, 10:27:44 am
content: Following your procedure the usual message "waiting for trigger" appears. When the Advantest is turned off, image 1 (pattern XX8X) appears.With pattern 9X4X, following your procedure, Image 2 appears.With pattern XX4X, following your procedure, Image 3 appears.

author: m k
author_rank: Super Contributor
timestamp: October 23, 2024, 03:25:10 pm
content: I think we can now make an educated guess that _IPLs are stuck down, PODs 13 and 14.If you like you can try image 2 and 3 again, change Time/Div period to be so long that you can see some changes other than POD 09.But try Find Patterns Bxxx, Dxxx and Fxxx, no matter the procedure.If Interrupt Priority Lines are down all the time you'll get empty pictures, or random noise.So if pictures are empty start finding _IPL0 and _IPL1 traces.It's also possible that they are not connected, but that's not very likely.PAL chips are good source candidates.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 23, 2024, 03:54:09 pm
content: Changing the period does not show anything new.With patterns BXXX DXXX FXXX the image is empty.How do I find the _IPL0 and _IPL1 traces?

author: m k
author_rank: Super Contributor
timestamp: October 23, 2024, 08:09:42 pm
content: You can disconnect POD 09 and try finding something new again.There you must also have Timing Trace Acquisition mode Transitional, wrong mode is Traditional.Transitional means that only changes are saved, so disconnecting POD 09 will give more space and possibly more Waveforms time.Finding traces is a hard guessing work, or easy with some luck.CPU pins 25, 24 and 23, find their connections, in that order, last is less important.And then possibly connections of input side of those new sources.You need a decent short circuit tester, regular multimeter is fine if its beeper is fast enough.Too slow beeper and you must check the reading.Even if beeper is fast you must still check that all beeps are really shorts.It's possible that other connections are so close to short that beeper is activated.It's also a fineline PCB so small flashlight is not bad.Means that two traces go between CPU pins, so you may need to check closer how the trace is actually connected.Keep also in mind that a trace can go around something and come back while being under a chip all the time.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 28, 2024, 03:58:39 pm
content: I'm trying, but it's like looking for a needle in a haystack! The pcb is multilayer (more than two layers), so the flashlight is of little use!

author: m k
author_rank: Super Contributor
timestamp: October 28, 2024, 05:16:57 pm
content: It's guessing then.Left of CPU is quartet of chips.LS164 serial to parallel is interesting, but probably not for this case.HC148 is 8to3 lines priority encoder, its likely buddy is old style LS07 OC driver.If so then HC148 output pins 9,7 and 6 can be connected to LS07 input(A) pins and output(Y) pins to CPU IPL pins 25, 24 and 23.Since LS07 style is open collector there must be pull-up resistors.I remember that those IPL pins have been up in some picture, but I'm not sure.Faulty resistor network is not uncommon either.Open collector here can mean that some other direction is also connected to those CPU pins, but all of them must be also open collector style and near by gates are clearly totem-pole style.It's also possible that some controller chips have open collector interrupt lines, so they can connect directly.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 30, 2024, 10:26:24 am
content: From what I can see from the copper side of the PCB, the connections would be as follows:CPU pin 25 connected to HC148 pin 9.CPU pin 24 connected to HC148 pin 10.

author: m k
author_rank: Super Contributor
timestamp: October 30, 2024, 11:11:39 am
content: Is pin 9 a corner pin?CPU _HALT(17) and _RESET(18) are bidirectional, so good destinations for open collector drivers.If so then input side of the pair can be shorted and go to *SOFTRST output of a timer chip.(just something for possible future use)

author: stfjohn
author_rank: Regular Contributor
timestamp: October 30, 2024, 11:29:02 am
content: Yes: corner pin.

author: m k
author_rank: Super Contributor
timestamp: October 30, 2024, 01:21:22 pm
content: Pin 10 is input 0, so it's coming from somewhere else also.DMAC _IRQ pin is 21, is it connected there?KBC _IRQ is pin 4, is it connected to some other input of HC148?

author: m k
author_rank: Super Contributor
timestamp: October 30, 2024, 01:38:25 pm
content: Floppy controller _IRQ is pin 23 and CRTC _IRQ pin 12.Try searching those also from HC148 inputs.71054 timer chips have three possibilities, pins 10, 18 and 26.Some of those can also be connected to HC148 inputs.There are also some others, but their positions are not so straight.One is FPU, but its bidirectional pin has something in between.

author: stfjohn
author_rank: Regular Contributor
timestamp: October 30, 2024, 03:40:56 pm
content: DMAC_IRQ (pin 21) is not connected to HC148. Sorry, can you be more clear about the other ICs?

author: m k
author_rank: Super Contributor
timestamp: October 30, 2024, 07:09:53 pm
content: Possible other connected _IRQ pins.63484 CRTC 1263265 FDC 2382C79 KBC 49914 GPIB 971054 U52 1071054 U67 1071054 U86 1071054 U52 1871054 U67 1871054 U86 1871054 U52 2671054 U67 2671054 U86 26HC148 pin 14, can you find it from LS164 input pins 1, 2, 8 or 9?Are any LS07 input or output side pins shorted to other pins of the same side?Are any LS07 output pins connected to HC148 input pins?

author: stfjohn
author_rank: Regular Contributor
timestamp: November 04, 2024, 02:39:46 pm
content: The only pin I managed to check is the 9914 GPIB 9 which is connected to pin 15 of the HC148. To check all the others I have to disassemble the Main Board again and it will take me a bit of time (currently I'm busy with work unfortunately).

author: m k
author_rank: Super Contributor
timestamp: November 04, 2024, 05:56:12 pm
content: I thought you've already dismantled it.Leave top side for later.Pin 15 of HC148 is also output.Is it possible that the pin is actually 2 from the other side of the chip?That would be pretty much spot on.One other thing I've possibly forgotten.Are those CPU pins 25 and 24 shorted to ground?PAL chip left of CPU.Can you find its 1 to 11 pins connected to CPU high address pins 52 down to 44 in any way?If so then can you find same connections from PAL chip right of CPU?One possibility is that one PAL chip is not coding I/O addresses correctly and that's why there are so few _CS signals and 'not installed' on screen.Downside with that is that it has nothing to do with interrupts, unless the same PAL is also coding those interrupts.So check also if you can find those CPU pins 25 and 24 from that left PAL chip.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 08, 2024, 11:30:44 am
content: Sorry, but I'm out of town for work: as soon as I get back I'll let you know. Thanks.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 09, 2024, 11:49:35 am
content: I disassembled the main board again. Connections checked:9914 GPIB oin 9 connected HC148 pin 271054 U52 pin 19 connected HC 148 pin 1671054 U86 pin 19 connected HC 148 pin 1671054 U67 pin 25 connected HC 148 pin 16No connections LS164 pins 1 , 2 , 8 , 9LS07 pin 7 connected HC148 pin 10LS07 pin 10 connected HC148 pin 11LS07 pin 14 connected HC148 pin 16

author: m k
author_rank: Super Contributor
timestamp: November 09, 2024, 04:32:23 pm
content: Since it's now available take couple new pictures for unknown chips.Low left corner area and area right from add-on connectors between power connector and GPIB controller.If you like take few pictures from the under side also.Any of your added connectors blocking something is not a problem.These pictures are not for any exact connection stuff, just something that can possibly reveal some designer's thoughts.Areas of interest are HC138 chips between CPU and DMAC, crystal surroundings and logic section of left side.Then recheck.HC148 is 16 pin chip and LS07 has 14 pins.Is HC148 pin 10, one pin away from corner, connected to LS07 corner pin, end of left side of its top side?Are previous timer chips pins 19 and 25 connected also to LS07 top right corner pin of its top side?

author: stfjohn
author_rank: Regular Contributor
timestamp: November 10, 2024, 11:54:05 am
content: Pin 10 HC148 connected to pin 7 LS07 and pin 7 LS164.Pin 19 U52, pin 19 U86 , pin 25 U67 connected to pin 14 LS07.

author: m k
author_rank: Super Contributor
timestamp: November 10, 2024, 02:46:59 pm
content: For sanity check test how other HC148 pins are connected to ground, to pin 7 of LS07 and pin 8 of HC148.HC148 pin 11 function means that pin 9 goes low when pin 11 goes low, but pin 10 operates differently.Means that pins 9 and 10 shorted to ground by the same situation is not very high.So it has been visible since reply #47.Then reply #146 connects it and now this last stint verifies the cause.CPU pin 24 or its signal source seems to be shorted to ground.Means that interrupt is always on, it shouldn't be, HC148 pin 11 going low is never going forward.Next you must find the source of that short.Easy start is to pull PAL chips out, start from left of CPU.Then when chip is off measure CPU pin 24 to ground.If ground connection disappears you've found the cause.If PAL chips are not the cause remove HC148.If short is still there you can try desoldering CPU pins 24 and 25.When pin holes are empty you should be able to position pins so that they are floating.If you succeed you can test floating pins to ground, if connection is still there CPU is the cause.E,you can also cut the CPU leg just above the PCB and bend it up a bit.If it wasn't the cause you just add a stump of wire and connect the leg back.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 11, 2024, 09:17:07 am
content: CPU pins 24 and 25 are not grounded!

author: m k
author_rank: Super Contributor
timestamp: November 11, 2024, 10:56:55 am
content: Quote from: stfjohn on October 30, 2024, 10:26:24 amQuote from: stfjohn on November 10, 2024, 11:54:05 amWhich one is wrong?

author: stfjohn
author_rank: Regular Contributor
timestamp: November 11, 2024, 02:58:11 pm
content: Sorry: CPU pin 25 conncted HC148 pin 9!

author: m k
author_rank: Super Contributor
timestamp: November 11, 2024, 03:25:32 pm
content: Can you find where HC148 pins 6 and 7 are connected?Possibly to CPU 24 and 23.E,check also LS07 pin 10 connection to other even numbered pins of the same chip.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 12, 2024, 10:31:32 am
content: HC148 pin 6 connected to CPU pin 23HC148 pin 7 connected to CPU pin 24LS07 pin 10 connected to HC148 pin 11

author: m k
author_rank: Super Contributor
timestamp: November 12, 2024, 01:04:01 pm
content: LS07 pin 10 is not rational if there are no other connections.It's old DIL package because other versions are limited, so its function is essential, for what ever reason.Only rational reason is its open collector output style, means that many output signals can be connected together.It's also possible that leftover drivers are used elsewhere, when main function is to connect bidirectional CPU pins.Can you find other LS07 even numbered pins from HC148 pins 1 to 5, 12 or 13?Is HC148 pin 13 shorted to ground?

author: stfjohn
author_rank: Regular Contributor
timestamp: November 13, 2024, 11:34:44 am
content: LS07 pin 14 connected to HC148 pin 4.Hc148 pin 13 not grounded.

author: m k
author_rank: Super Contributor
timestamp: November 13, 2024, 03:14:55 pm
content: Try to find from where HC148 pin 13 is coming.It's the pin putting CPU pins 24 and 23 down, our suspected problem situation.LS07 outputs must have pull-up resistors, check that they are present.Between pin 14 and other even numbered pins is similar ohms value.Try also find where LS164 output pins 3 to 6 and 10 to 13 are going.If the chip operation is normal serial to parallel thing all of those pins go side by side to somewhere.It's also possible that only one goes anywhere, like to HC148 pin 1, 3, 12 or 13.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 14, 2024, 03:06:20 pm
content: HC148 pin 123 connected to central pin R35 (4 x 472 J). R35 pin 1 (black marked) connected to Pal U58 pin 20.

author: m k
author_rank: Super Contributor
timestamp: November 14, 2024, 06:00:10 pm
content: That fits, pin 2 goes to 9914 pin 9(reply #156) that is OD(Open Drain), same as Open Collector for TTL.R35 is a resistor network, leftmost is a common pin, it has its own PCB marked square, so that you know which way it must be installed.Other four pins are 4700 ohm resistors to that common pin.So from common pin to any other pin you must be able to measure close to 4700 ohms.If one pin has much different value you can start thinking what is its cause.Too high means that the resistor is not there and too low means that somewhere is a possible short to +5V.Since our assumed problem is constant interrupt we are searching the situation where that pull-up resistor is missing.But if that incoming interrupt Priority Line comes through some other component it's possible that the situation turns around and we should search something that is constantly up.Luckily both sides of HC148 are active low, means that we are searching something that is constantly down.And since we have two CPU lines down we are mainly searching sources for HC148 pins 11, 12 and 13.Pin 11 goes to LS07 pin 10, so it needs a pull-up resistor for sure, one candidate is R36 right of R35.To be a symmetric design three resistors connect to those high side input pins of HC148.And those high side input pins connect to high side of output pins of LS07, pins 12, 10 and 8, but be methodical and check lower output pins also, pins 6, 4 and 2.So how are those HC148 pins 11, 12 and 13, their pull-up resistors and their signal sources?

author: stfjohn
author_rank: Regular Contributor
timestamp: November 16, 2024, 10:34:51 am
content: The only connections I can locate are:HC148 pin 11 connected to R35 pin 2;HC148 pin 12 connected to R35 pin 4;HC148 pin 13 connected to R35 pin 3;I can't locate anything else unfortunately...

author: m k
author_rank: Super Contributor
timestamp: November 16, 2024, 04:46:09 pm
content: I misread reply #168, so the actual pin is 13 and not 1, 2 and 3.Below are two cases, Totem Pole and Open Collector/Open Drain.Can you find any connections?Timers can use both levels, 82C79 KBC 4 is always active high.So KBC is different and timers can be so also, but not necessarily.If LS164 outputs are not clearly serial to parallel outputs one output can be KBC IRQ, it goes so that LS164 is delaying the actual IRQ request.Leftmost timer can be there also, but its internals can do delaying much easier.The whole thing is a bit far fetched, but can you find from where LS164 pins 1 and 2 are coming?Keep in mind that your probes are also not necessarily connecting every time.Some legs can have something transparent covering and insulating them, pads also.So check that you can short probes over a component pin or other measuring point you're going to use.Some components are still unknown.A chip beside PAL chip and under 32081 FPU on 3rd picture of reply #158.4th picture of reply #158 has few fuzzy ones, a chip between RTC and F169, and chips above and right of leftmost F240.If you like taking new pictures instead of naming them, use different camera angle.All camera angles are bad for some directions and very good for some others.Take also couple pictures from the other/under side of the PCB.One location is those four chips left of CPU.Use two different camera angles, maybe a bit from left and right.Main goal is to record how HC148 and LS07 are connected, others are secondary.Other location is area below FPU and printer connector, areas below near by HC138, timer and PAL chip should also be visible.Use two different camera angles again.TP source63265 FDC 2371054 U52 1071054 U67 1071054 U86 1071054 U52 1871054 U67 1871054 U86 1871054 U52 2671054 U67 2671054 U86 26TP destinationLS07 pin 11HC148 pin 1HC148 pin 3OC/OD source63450 DMAC 2163484 CRTC 12OC/OD destinationHC148 pin 12HC148 pin 13

author: stfjohn
author_rank: Regular Contributor
timestamp: November 18, 2024, 10:40:30 am
content: LS164 pin 1 is connected to C34 which, on the other side, is connected to HC138 pin 8.LS164 pin 2 is connected to R34 pin 1.

author: m k
author_rank: Super Contributor
timestamp: November 18, 2024, 01:37:31 pm
content: So the capacitor is delaying pin 1 going up.That can be a time delay for reset or any general hysteresis control of what ever.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 19, 2024, 02:50:24 pm
content: Photos.

author: m k
author_rank: Super Contributor
timestamp: November 19, 2024, 03:00:48 pm
content: With those belly up pictures from left of CPU we can try to combine partially transparent ones from under and over, but that's secondary, so don't try to match them to what we already have.More important is to have them.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 20, 2024, 11:03:55 am
content: Sorry, but I didn't understand your answer...

author: m k
author_rank: Super Contributor
timestamp: November 20, 2024, 01:00:36 pm
content: Yes, after checking those previous pictures that became obvious.For other/under side pictures I mean the side where those currently pictured components are not.It used to be a solder side, but now there's solder everywhere.Top side, the side with CPU and stuff is for vertical traces.(PCB text is correctly oriented)Bottom/under side is for horizontal traces.Combining both pictures and making them partially transparent by software we can possibly see better how traces go.You can do the same with physical board, but it's quite big, so it's a bit difficult and can lead to dizziness.There you put the PCB on it edge and look both sides by swinging your body, the PCB or both.Small flashlight is a good assistant, with it you can concentrate you view better.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 21, 2024, 02:50:51 pm
content: I did some tests, but it doesn't show much...

author: drhex
author_rank: Regular Contributor
timestamp: November 21, 2024, 07:33:56 pm
content: What Mark is saying is take a pic of the board from both sides and overlay them so you can see the traces on both sides at once. Makes it easy to follow signals. You can do some jiggery pokery with photoshop or similar to reduce the images to the traces.

author: m k
author_rank: Super Contributor
timestamp: November 21, 2024, 08:20:19 pm
content: First picture, bottom side trace closest to PCB edge, from HC148 pin 13 pad towards CPU.I can't see it connecting.Another case, 2 + 3 pads near CPU, where topmost connects to HC148 pin 13.Lowest of the right triplet, bottom side trace connects to HC148 pin 7, I can't see it connecting to anywhere.Maybe there is too much light.First picture and R35 pin 3.Left of pad above it is trace from above somewhere that turns to the pin, that trace is probably from the topmost of 2 + 3 pads.Bottom side picture has white line blocking the view, but seems that nothing is connecting there from under the white line.Top side picture has clear connection to lower right corner of the pad, but so seems to be to upper left corner.Is the upper left corner connection real?HC148 pin 13 must still connect to somewhere else, but everything seems to be a dead end.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 22, 2024, 11:27:32 am
content: The problem with the motherboard is that it is multilayer (not just double-sided!) and therefore it becomes extremely difficult to locate the connections!

author: m k
author_rank: Super Contributor
timestamp: November 22, 2024, 07:22:55 pm
content: You can make assumptions, like hidden part of straight line.It's also a fact that none of those pads are without a reason.But generally and without any luck it is very difficult.Are there 4k7 ohms between R35 pins 1 and 3?You can concentrate to HC148 pin 13, sooner or later its source must be found.Bottom side has nothing, but check its connections to all pads around.One other possibility is to try other signals that are sort of related.LS07 pins 2, 4 and 6 are shorted and go to CPU.Check where they go, CPU pins 10 to 13 are good candidates.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 25, 2024, 03:43:35 pm
content: I checked practically everything: yes, there are 4.7 Kohm between pin 1 and pin 3 of R35.Pin 13 of Hc148 is connected only to pin 3 of R35 and nothing else!Pins 2-4-6 of LS07 are connected to pin 10 of the CPU.

author: m k
author_rank: Super Contributor
timestamp: November 25, 2024, 08:55:23 pm
content: Ok, then we accept that source for HC148 pin 13 is R35 pin 3 and interrupt priority level 3 is not used.But interrupt priority level 3 is active, all the time.Do the same search to HC148 pin 12.If you can't find it going anywhere else but R35 pin 4, change HC148, assemble the machine and see what it does.Maybe you should change HC148 anyway.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 26, 2024, 03:47:45 pm
content: Also pin 12 of HC148 is only connected to R35 and nothing else.I will try to replace HC148, but I have little hope...

author: m k
author_rank: Super Contributor
timestamp: November 26, 2024, 05:59:09 pm
content: Have you checked pin 13 connection to GND, is it shorted?Take a picture when it's off, then you never forget what is under it.Pin 12 as a spare also is a good sign.It sort of strengthens the probability that pin 13 really is a spare and that turns it probable that HC148 is the problem.Interrupt level we have means that pin 13 is low, being pulled up and nothing more means it permanently is not.The I/O map we have, with very old 8245B CRTC controller indicates that the PCB is a new design.So HC148 just missing few traces from initial design is very plausible.So only practical reason why the problem is not HC148 is that there is a secret trace to somewhere or the problem is the other end of interrupt lines, the CPU.If you like you can test CPU by cutting those legs near PCB level or make them float otherwise.You can also lift HC148 pins 7 and 9, then only interrupt level 4 is possible, it should make a difference if the chip is a problem.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 27, 2024, 04:17:44 pm
content: I disconnected pins 7 and 9 of the HC148. I disconnected pins 24 and 25 of the CPU. I reassembled the device. The result is that the self test starts (Photo 1), but, at the end, the same message reappears (Photo 2). Then I re-soldered pins 24 and 25 of the CPU, leaving pins 7 and 9 of the HC148 disconnected: the result is that, once the self test is finished, it tells me "all pass", but, immediately after, the message in photo no. 3 appears. I tried to disconnect the CD player, but nothing changes.

author: m k
author_rank: Super Contributor
timestamp: November 28, 2024, 08:24:22 am
content: First and second pictures mean that interrupt Level is random, CPU pins 25 and 24 are off.So you were lucky that you got the result you got, something good for a change.When CPU pins are back and HC148 pins off only interrupt level 4 line is active, IPL2 pin 23.Last picture, something prevents random interrupts and self test can continue.(when TTL output drives CMOS input it may be necessary to use a pull-up resistor, TTL high is not enough for CMOS)Then finally normal operation tries to start but fails.Assuming'code = 8' privilege violation'pc' program counter'sr' status register'usp' user stack pointer'D' data'C' codePrivilege violation, software does something it is not allowed to do.It can be either way, disk access creates a wrong situation or something else creates a false disk situation.When HC148 pins are off and interrupt level is less than 4 nothing happens, all CPU side pins stay up.When interrupt level is higher than 3 the result is level 4, the only active line goes down.Fingers crossed that HC148 is the only fault.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 28, 2024, 11:20:46 am
content: I ordered the HC148 chip: as soon as it arrives, I will disassemble everything again, replace it, and see what happens. In the meantime, thanks for your precious and competent availability.

author: m k
author_rank: Super Contributor
timestamp: November 29, 2024, 09:22:43 am
content: No problem.Seems that you're about to get it back to business in less than 148 days.I'm sure the next time is much faster, hope that never comes.

author: stfjohn
author_rank: Regular Contributor
timestamp: November 29, 2024, 04:29:08 pm
content: I replaced the HC148 and... everything started working again! I would like to find a way to repay you for your patience, competence and availability: how can I do it, Mark?

author: m k
author_rank: Super Contributor
timestamp: November 29, 2024, 07:03:48 pm
content: You just did.You had stamina to go through it, so now the collective can learn and hope that next case is easier.E,Code:HC148 pin 1 toHC148 pin 2 to 9914 GPIB pin 9HC148 pin 3 toHC148 pin 4 to +5VHC148 pin 6 to CPU pin 23HC148 pin 7 to CPU pin 24HC148 pin 9 to CPU pin 25HC148 pin 10 to GNDHC148 pin 11 to LS07 pin 10to R35 pin 2 pull-up 4k7HC148 pin 12 toto R35 pin 4 pull-up 4k7HC148 pin 13 toto R35 pin 3 pull-up 4k771054 U52 pin 19 to +5V71054 U86 pin 19 to +5V71054 U67 pin 25 to +5VPOD 06 5E10xx 63484 5 _CS CRTCPOD 07 ------ 71054 31 _CS U52 timerPOD 08 5E30xx 71054 31 _CS U67 timerPOD 09 ------ 71054 31 _CS U86 timerPOD 10 ------ 68450 17 _CS DMACPOD 11 5F08xx 62421 2 _CS0 RTCPOD 12 ------ 62421 15 _CS1 RTCPOD 13 ------ 32081 21 _SPC FPUPOD 14 ------ 8279 22 _CS KBCPOD 15 ------ 9914 3 _CE GPIB

author: stfjohn
author_rank: Regular Contributor
timestamp: November 30, 2024, 11:49:21 am
content: Many thanks again.

author: stfjohn
author_rank: Regular Contributor
timestamp: December 01, 2024, 05:03:37 pm
content: Very useful #192! Thanks.