VHDL; State machines and syntax! - Page 1
Forum section: electronics / beginners

author: McPete
author_rank: Regular Contributor
timestamp: February 23, 2012, 11:41:32 am
content: Hey all,Another quick question on VHDL. I have a series of IF statements controlling a state machine's transition through states. Several are timed. What I've used sucessfully in the past is;QuoteWhat I'm trying to do this time is this;(Errors highlighted in red)Quote'Error (10500): VHDL syntax error at PTMFSM.vhd(40) near text ";"; expecting ":=", or "<=" 'Where am I going wrong here?Thanks!

author: TerminalJack505
author_rank: Super Contributor
timestamp: February 23, 2012, 12:22:23 pm
content: It looks like you have an extra 'THEN'.QuoteI'm guessing you meant to say this...Code:IF (STATE = S0) THENIF (CLK100h'EVENT AND CLK100h = '1') THEN(tint30 <= tint30 + 1);IF (tint30 = 3000) THENSTATE <= S1;END IF;END IF;END IF;Edited to add:By the way, you're pushing your luck by using signals that way. The tint30 signal should probably be a variable. A signal isn't guaranteed to be updated immediately--only after the process completes. So the value that you're checking against in the statement following the assignment won't necessarily be the value you just incremented the counter to.You probably won't get burned by that code since tint30 is just a counter but it's still bad form.

author: slateraptor
author_rank: Frequent Contributor
timestamp: February 23, 2012, 01:25:34 pm
content: Previous comment amended. Your FSM is bad form in general; consider revising in the order 1) check for rising edge, 2) determine current state, 3) execute statements for applicable state.Quote from: TerminalJack505 on February 23, 2012, 12:22:23 pm

author: Blofeld
author_rank: Regular Contributor
timestamp: February 23, 2012, 03:54:43 pm
content: Just found this free VHDL introduction today:www.freerangefactory.org/dl/free_range_vhdl.pdfPerhaps if you are unsure about some concepts it may help to take a look at it.

author: TerminalJack505
author_rank: Super Contributor
timestamp: February 23, 2012, 04:37:49 pm
content: Quote from: Blofeld on February 23, 2012, 03:54:43 pmThat's a really nice book. Especially for the price!Thanks for pointing it out.

author: McPete
author_rank: Regular Contributor
timestamp: February 23, 2012, 09:42:54 pm
content: Hi All,Thanks for the pointers!It's been a "teach yourself with little to no guidance" experience for me with VHDL, so it's good to get some experienced advice.With regard to variables, should I be declaring STATE (currently defined as a "TYPE") as a variable too?Thanks!

author: TerminalJack505
author_rank: Super Contributor
timestamp: February 23, 2012, 10:03:13 pm
content: Quote from: McPete on February 23, 2012, 09:42:54 pmNo, it probably isn't necessary to declare STATE as a variable. You will typically want to use signals rather than variables, when possible.Here's a table from one of the books I have that summarizes when to use signals or variables...SIGNALVARIABLEUtilityRepresents circuit interconnects (wires.)Represents local information.ScopeCan be global (seen by entire code.)Local (visible only inside the corresponding PROCESS, FUNCTION, or PROCEDURE.)BehaviorUpdate is not immediate in sequential code (new value generally only available at the conclusion of the PROCESS, FUNCTION or PROCEDURE.)Updated immediately (new value can be used in the next line of code.)UsageIn a PACKAGE, ENTITY, or ARCHITECHTURE. In an ENTITY, all PORTS are SIGNALS by default.Only in sequential code, that is, in a PROCESS, FUNCTION, or PROCEDURE.

author: McPete
author_rank: Regular Contributor
timestamp: March 01, 2012, 09:01:18 am
content: Thanks all, I've cleared all my errors surrounding syntax now.... I'm even getting my CASE statements to work!However, I'm now getting errors from each line of each state progression setup, where I reference STATE directly.I've declared STATUS as a TYPE, and then associated it with a signal, STATE, as follows;TYPE STATUS IS (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, SA, SB, SC, SD); -- All avalible states of FSMSIGNAL STATE: STATUS;The error Quartus is giving me is;"Error (10514): VHDL aggregate error at PTMFSM.vhd(51): can't determine type of aggregate -- found 0 possible types"What precisely does that mean?Thanks!P.

author: electrode
author_rank: Regular Contributor
timestamp: March 01, 2012, 09:41:15 am
content: While my VHDL may be crusty, that certainly looks correct. I even dug up an old project of mine and your code is identical to mine for the declarations (other than naming, of course).My guess is the problem lies elsewhere in your code, perhaps with an illegal assignment to your signal.

author: TerminalJack505
author_rank: Super Contributor
timestamp: March 01, 2012, 03:49:07 pm
content: Those two lines of code look okay. What's at (and around) line 51? It looks like that's the line it has a problem with.

author: McPete
author_rank: Regular Contributor
timestamp: March 03, 2012, 08:40:21 am
content: Just came back to it with fresh eyes.... I had this;51: IF (STATE <= S1)Instead of this;IF (STATE = S1)Silly newbie mistake!