Getting started Altera Flex 10K questions from FPGA newby - Page 1
Forum section: electronics / general

author: CJay
author_rank: Super Contributor
timestamp: November 01, 2019, 08:55:23 am
content: In an fit of idiocy, I've decided I'd like to have a play with FPGAs, another thing to add to the never shrinking pile of projects.I'm quite out of my depth so far, it's been a bit of a mission to even find a pinout for the chips I have (sorted now)I've got, courtesy of another member, a pile of quite nice looking boards with an Altera Flex 10K20 chip, a NTSC/PAL video encoder and a fair bit of fast static RAM that seems to be arranged as one 512KB block and three separate 128KB blocks (I'm assuming it was one block per primary colour) as well as an odd USB interface chip.While they're not ideal as a dev board (pins not broken out to headers or proto area) they have some excellent attributes, they were free (Important), have a JTAG socket and an FPGA that's potentially removable and re-usable if I design my own board (the chips list at $110 each, surely wrong?).I'm aware that I can get Quartus 2, it's huge so suggestions of alternatives for Windows or Linux are welcome.I'm also aware that the FPGA is static RAM based so I can upload my efforts to it but for them to be retained through power cycle I need a config memory.The boards all have a socket for such a memory, they've currently got EPC1441 chips installed which I believe aren't reprogrammable and are now obsolete so that's a bit of an issue, do I *have* to use the EPC series chips or are there other chips I could use (preferably reprogrammable and cheap)?Is this a case of 'I wouldn't start from here' or does this have mileage?

author: BrianHG
author_rank: Super Contributor
timestamp: November 01, 2019, 09:45:04 am
content: As what you have is free, note that there are now Max10k FPGA starting at 6$ which have more than a Flex 10K20 and the flex10k series is discontinued. This doesn't mean you still cant do things with the Flex10k, however, you will need to use an older version of Quartus, like over 5 years old or so...Which dev board do you have?Note that the Max10 FPGAs have their bootprom built in, so, with them, if you move these FPGA from their dev board, they will retain everything.I am not sure about the really old EPC1441, however, with Altera's newer bootproms for CycloneII and above FPGAs are flash instead of OTP, and they are function compatible with standard serial SPI NOR flash IC. Though, the smallest one today being something like 16mb instead of 440kb, the larger ones used to work with any CycloneII or above FPGA in my designs. I can't guarantee the same about the Flex10k, you would need to try one out, and at around 1-2$ at digikey, and some custom wiring, it may work.

author: CJay
author_rank: Super Contributor
timestamp: November 01, 2019, 10:10:52 am
content: Thanks Brian, one of the attractions of the Flex 10K is the 5V tolerance and a workable package for me (no BGA facilities here) but I'm open to suggestions, the 5V tolerance isn't an essential.The boards aren't a dev board, they're a custom application that was begging to be re-used somehow, I may just harvest the SRAM and a few other bits if they're useless, suggestions for a MAX10 dev board that's dirt cheap or is it simple to roll my own and use one of the cheap PCB services and hand assemble?(Note, I'm not tied to Altera, it's what I have, happy to move to whatever works/gives most bang per buck)

author: BrianHG
author_rank: Super Contributor
timestamp: November 01, 2019, 10:53:10 am
content: Quote from: CJay on November 01, 2019, 10:10:52 amI mentioned the Max10 since it does come in 144pin TQFP and has the built in flash like a PLD with the size of an FPGA. In fact, you can select the 6$on up to 50$ which all are pin-pin compatible. It also only requires a single supply and has PLLs with DDR2/3 capable IO. Sadly, it is only 3.3v or less, though, in the past I have used series resistorts and clamping diodes to interface with 5v TTL.IE, the 6$ Max10 is large enough to replicate an entire Atari 400, that's with it's own internal ram, internal 6502 core, internal graphics and sound processor. With a single external ram chip you can make a top of the line 8 bit computer, or even a 24/32bit 2D video card with a simple 3D geometry engine. I always wanted to use the 50$ version of the chip with a high quality 3 channel ADC to make a high quality XY+Z plotting oscilloscope with DVI output to replicate old analog scopes, all in one chip I could sell.

author: CJay
author_rank: Super Contributor
timestamp: November 01, 2019, 11:38:43 am
content: Quote from: BrianHG on November 01, 2019, 10:53:10 amWow, yes, that sounds like a lot of power for $6, way more than I'll use but why not have it for that price.One of the problems for a beginner like me is the scale of these things, knowing how the figures translate into relatable hardware is really useful, I doubt I'll ever tax it to it's limits (unless I just end up writing hugely inefficient stuff).Is there FOSS toolchain for the Altera or is it all Intel proprietary?

author: BrianHG
author_rank: Super Contributor
timestamp: November 01, 2019, 11:53:48 am
content: I've only used Altera/Intel tool chain, so, I cannot say if others exist. However, I do program my FPGAs mostly in verilog, so, I know my code can be mostly ported to Xilinx, or Lattice, or eventually an Asic.As for the Atari 400, what I meant to say was it would be a equivilant to a 400Mhz Atari 400/800/130xe, but with scan doubled DVI output.

author: RoGeorge
author_rank: Super Contributor
timestamp: November 01, 2019, 12:12:50 pm
content: No FOSS for FPGA toolchains, in general.There are some attempts (i.e. Icestorm and Symbiflow), but those work only for a very few particular FPGA models, and not sure if all the chip features are supported, most probably not.FPGA toolchains are usually very big, but they offer the possibility to download only what is necessary for a particular chip, if you know what to download and install. Also, each FPGA manufacturer has its own toolchain. Even so, with huge proprietary toolchains, sometimes only a few family chips are supported by a certain toolchain, e.g. Xilinx ISE supports SPARTAN family of FPGA s, while Xilinx Vivado supports only FPGA chips from the Series 7 family, Spartan 2 is supported only by Xilinx ISE 10.1 or lower, etc.AFAIK any FPGA producers will have a free version for their toolchain, with less capabilities and less IPs available.If you are looking for low price chips, you may want to see the FPGAs produced by GOWIN. There are devboards at $5 or less.If you want US FPGAs, on Aliexpress you can find devboard with very powerful and very expensive chips for a fraction of the FPGA price alone (e.g. a complete devboard with genuine Xilinx Kintex 7, Virtex 7 an UltraScale for $200..300, when the chip alone is usually in the $kilo range, and with license for Xilinx Vivado, probably the license is not genuine, but the chips are genuinehttps://www.eevblog.com/forum/fpga/a-xilinx-kintex-7-board-on-aliexpress/).

author: AndyC_772
author_rank: Super Contributor
timestamp: November 01, 2019, 12:44:32 pm
content: Quote from: CJay on November 01, 2019, 11:38:43 amThe problem with any attempt at a FOSS tool chain for FPGAs is timing.Vendors' tools include a timing model of the die, which includes best and worst case timing delays for each path, guaranteed across all combinations of voltage, temperature and sample-to-sample process variation. It's derived from in-depth knowledge of the silicon layout and fabrication process, and devices which come out of the fab not meeting this spec are rejected.Probably the single most important part of placing and routing the logic in an FPGA is ensuring that it will meet timing. Logic which is functionally "correct" can, and will, fail to operate correctly in an FPGA if timing margins are not met, and it's simply not possible to verify that they are met unless that timing model is available to check against.A design which doesn't meet timing could work perfectly well on the desk of one developer, but fall over as soon as the chip gets warm, or the design is loaded onto another example of the same part.Bear in mind also that the design must meet hold time as well as setup time requirements, and these are independent of clock frequency. You can't make a design that fails to meet hold time requirements start working just by reducing the clock speed; it won't operate reliably at ANY speed.I've not seen this point addressed by anyone involved in the development and use of FOSS software for FPGAs, and that's alarming.

author: AndyC_772
author_rank: Super Contributor
timestamp: November 01, 2019, 12:51:14 pm
content: FLEX 10K is a very old family, I wouldn't bother with them if I were you.One very cheap and simple way into FPGA testing would be one of these:https://www.ebay.co.uk/itm/ALTERA-FPGA-Cyslonell-EP2C5T144-Minimum-System-Learning-Development-Board/202789948478I've used these in one-off projects before; they have a flash memory device on them (unlikely to be a real EPCS1 at the price, but that's OK).FWIW I never use the Altera serial configuration Flash devices any more. The prices on them are just plain ridiculous. Instead I just configure them from a microcontroller (look up 'passive serial' mode, it's quite a simple download protocol), and buy a micro with more Flash than I might otherwise have needed.

author: CJay
author_rank: Super Contributor
timestamp: November 01, 2019, 02:19:58 pm
content: Gah, so much choice...I've gone and ordered this as a present to myself:https://www.aliexpress.com/item/32813736111.html?spm=a2g1y.12024536.productList_35413438.subject_1And until that arrives I'll play with the Flex 10K boards I have, see if I can't get my head around at least the concept of them.

author: BrianHG
author_rank: Super Contributor
timestamp: November 01, 2019, 11:53:22 pm
content: Quote from: CJay on November 01, 2019, 02:19:58 pmWith that dev-board and a 2 channel ADC, you can achieve an XY plotting scope of 512x256 @ 4 shaded of phosphor grey. With a little trickery, maybe 512x320 @4, or, 512x256 @ 8 shades or grey. Such a verilog code would only be around 2-3 pages if you use a really fast ADC since the output would be dots and you would want them to merger into lines. (You are limited here since you will be using all the internal ram inside the FPGA, and there ain't much)Oversampling a slow ADC to synthesize/software draw those line in-between the dots would eat up another 1-2 pages of code and create a headache, but really good as an extended learning exercise.

author: BrianHG
author_rank: Super Contributor
timestamp: November 02, 2019, 12:07:48 am
content: Quote from: CJay on November 01, 2019, 02:19:58 pmMAKE SURE you have a good virus scanner before reading any of the development files from China!A good one. I use Microsoft security essentials and it always finds them...

author: CJay
author_rank: Super Contributor
timestamp: November 02, 2019, 10:49:43 am
content: Quote from: BrianHG on November 02, 2019, 12:07:48 amThe included disks usually go straight into the bin if the dev environemnt is available from manufacturer but on the odd occasion they are needed, I have MS Essentials and also access to enterprise AV stuff at work on standalone machines so I'm as confident as one can ever be that I'm relatively safe.As for application of the board, well I've been reading Nockieboy's thread and while I admit it's gone far over my heads in some places, my application would be similar only I'd be targeting VGA output, not HDMI.I realise the chip I've chosen is probably wildly over specced for that but it's cheap and it's on a decent enough looking dev board that has potential for lots of future projects so why not.I can always move it to a smaller device later...

author: FlyingDutch
author_rank: Regular Contributor
timestamp: November 02, 2019, 12:06:19 pm
content: Hello,maybe you will have been interested in such board called "Maximator":http://maximator-fpga.org/This board is based on modern Altera MAX10 FPGA (8K logic elements and 378 kb RAM user memory). It has JTAG programer interface. There are built-in VGA and HDMI outputs. GPIOs have 5V level logic compatibility. There are also 6 channels ADC on-board. There are schematics and manuals available for free. To "program" it you can use free "Quartus" synthessis software (made by Intel/Altera). There are also expander module with interesting I/O modules. There are many examples of project with this board. It cost 49 EURos.I bought it 2 years ago in order to start with Intel/Altera FPGAs, I former used only Xilinx FPGAs (I started learning FPGAs with Xilinx products).You can made many interesting project with ease - there is good documentation and examples. You can experiment on this board with "NIOS II" software CPU. Disadvantage is relatively low number of I/os and lack of additional (external) RAM.Kind Regards

author: BrianHG
author_rank: Super Contributor
timestamp: November 03, 2019, 04:43:48 am
content: Quote from: CJay on November 02, 2019, 10:49:43 amI just posted a large visual illustration and explanation of what the compiler is doing with the Verilog code here:https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg2767312/#msg2767312I've chosen Verilog because of it's similarities with regular C code, and C code sub routine modules. What I posted was not instructions on Verilog programming, but a snippet example of what the Verilog FPGA compiler is actually trying to generate on the FPGA. It helps visualize at a basic level the difference between Verilog and C. It shows how the FPGA's flipflop registers are wired based of the lines written.

author: CJay
author_rank: Super Contributor
timestamp: November 07, 2019, 11:56:13 am
content: Following that thread with interest as it's broadly similar to my immediate objective, I'm simultaneously trying to understand the code in it but not be influenced by it so I can work my own 'thing' out, if that makes any sense?I had been struggling to get out of the mindset which I'd developed from years of programming embedded micros and was reading it as a program instead of independent blocks, now it's making more sense as a collection of 'code' that works concurrently and indeed may not even talk to other blocks...

author: BrianHG
author_rank: Super Contributor
timestamp: November 07, 2019, 12:34:52 pm
content: Quote from: CJay on November 07, 2019, 11:56:13 amYour getting there / the idea.The lines of code do not follow in order like instructions in a 'C' program. Some simplification:------------------------------------------always @(posedge clk) beginEvery equation written inside this always which uses a:'a<=(equation) ;'where the 'a' is a register are all 'D' flipflops which are all synchronously clocked by the positive edge of the input 'clk'the '<=' is known as a blocking function. It means the the destination 'a' register is clocked by the positive edge of the 'clk' input instead of a simple '=' where 'a' would be treated as a simple integer, immediate in value, unclocked, no D-flipflop, just the raw and/or/xor gates to generate the mathematical equation.end-----------------------------------------If this case, the equation may contain the outputs and inputs of any other registers going through boolean operations and even regular math like add, subtract and multiply, as well as bit shifts.Inside that always block, you may have 100s of such equations, all triggered in parallel every positive edge of 'clk'.Next, the 'if' statement:------------------------------------------always @(posedge clk) beginif (adr_input == 2) begin'a <= (equation) ;'endend-----------------------------------------The difference here is that all the clocked register flipflops inside the 'IF's 'begin' and 'end' basically are D flipflops with a 'clock enable' input. They are always being clocked like all the other flipflops inside the 'always @(posedge clk)' except the boolean equation inside the 'IF' statement generates a set of logic which feeds any and all 'a <= (equation) ;' D filpflops clock enable' port inside that IF's begin and end.To see how you can wire something so simple like a 4 tap low pass filter:-------------------------------------input wire [7:0] input data;reg [7:0] tap1, tap2, tap3 ;output reg [7:0] output_data;always @(posedge clk) begintap1 <= input_data;tap2 <= tap1;tap3 <= tap2;output_data <= (input_data + tap1 + tap2 + tap3) >> 2 ;end------------------------------------Now there are better ways to write this, but here is a simple example. The order in which I typed these lines into my verilog code doesn't matter at all. What you are looking at is how the D flipflops are wired together.At every single clock, a new 8 bit byte is loaded into tap1, while tap1's old bye is loaded into tap2. And while this is all happening, the current input with tap1 through tap3's old byte are all summed together, with a sum shifted by 2 bits into the output_data's register flipflops 'D' inputs. So if your clock is 200Mhz, you are also getting 200 million output_data's a second.You are looking at a text description on how to wired a breadboard with a bunch of D flipflops all clocked in parallel, with a set of logic gate doing the math to feed the D inputs. Any of the register names you use in the math expression take their values from those D flipflop's 'Q' outputs which wont change again until the next clock.