ATSAM C21: Different pins at different voltage levels? possible? - Page 1
Forum section: electronics / general

author: JPortici
author_rank: Super Contributor
timestamp: March 15, 2017, 10:34:04 am
content: Hi. going on developing with the ATSAMC21One thing i noticed is that in table 7-1 PORT Function Multiplexingthere are group of pins (clusters, as the datasheet call them) that have different entries on the "supply" coloumn.One cluster has VDDANA for supplyAnother cluster has VDDIOA Third cluster has VDDIO (but on a different pin.Does this mean that i can operate the three clusters at three different voltage levels? I didn't find anything in the datasheet that would support or deny this. The only thing i found mentioned in the datasheet wasQuoteBeing able to save on voltage translators would be VERY neat (a really space constrained application)

author: ataradov
author_rank: Super Contributor
timestamp: March 15, 2017, 06:10:30 pm
content: No, you can't do that. The reason clusters are called out is to balance the load, because there is a load limit per pin and per cluster.But all I/O voltages must be the same.

author: JPortici
author_rank: Super Contributor
timestamp: March 15, 2017, 06:13:31 pm
content: thank you for crushing my hopes.good thing i can always switch to a smaller package (for passives)

author: westfw
author_rank: Super Contributor
timestamp: March 16, 2017, 12:26:52 am
content: Quotehuh. I wonder how difficult that would be to implement (on the chip)? It WOULD make some things easier, and the chip is already doing level translation from Vddcore to Vddio, anyway...

author: ataradov
author_rank: Super Contributor
timestamp: March 16, 2017, 12:34:18 am
content: It is doable, since FPGA banks can have different power supplies.It is very much possible that it will work even on SAM devices. But it is not allowed by the datasheet, so you are on your own. If you have a chip to spare - try and see what happensIt may be less practical than expected, since mapping of pins to clusters is pretty limiting.

author: ataradov
author_rank: Super Contributor
timestamp: March 16, 2017, 12:44:25 am
content: Ok, I took a plain SAMC21 in TQFP64 package, and all VDDIO seem to be connected internally on the die. They all have 4 to 9 Ohm resistance to each other. But VDDANA seems to be on its own.So separate VDDIOs are not happening on this device, but separate VDDANA may work. But again, at your own risk.

author: JPortici
author_rank: Super Contributor
timestamp: March 16, 2017, 05:50:47 am
content: i'll quote the datasheet againQuotei think i don't want to risk.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 16, 2017, 09:01:48 am
content: I suspect many MCUs are designed with banks of pins referenced to nearby power pins. If there's no continuity between the various VDDs, it could very well be the case that they can be operated independently, or at least to some modest extent (like, give or take a diode drop, possibly limited by some obscure chain of diode drops between banks).It wouldn't be something you would want to depend upon in production.More likely, most chips have them all shorted together, but "short" is a relative term; the resistance would be due to die metallization, and could be some ohms. This is advantageous to VDDANA, where some filtering can be applied, without allowing the voltage to differ by much. This is also advantageous to power management, where the current from a set of pins will largely flow from the nearby power pins, not the other side of the chip.In any case, if there are quirky edge case possibilities for the supplies, manufacturers are certainly not interested in supporting them, so you're best off following the plain vanilla setup. You can "ohm out" the pins yourself and put together a hack that takes advantage of what you've found, but I wouldn't recommend doing it for any more than a curiosity.Tim