SPI trace length - Page 1
Forum section: electronics / beginners

author: rakeshm55
author_rank: Regular Contributor
timestamp: June 19, 2018, 04:27:42 am
content: Hi,Is there a limit for trace length for SPI (Single ended) thumb rule ??My requirement is to take it off-board ie from Module ---> Motherboard---->ModuleI have referred to following articlewww.ti.com/lit/an/slla142/slla142.pdfIt suggest (<30cm) for single ended trace length for high speed operation.As a thumb rule At what trace lenths should i used differential drivers (LVDS,RS485) etc for SPI interface

author: ataradov
author_rank: Super Contributor
timestamp: June 19, 2018, 04:53:51 am
content: I had a board with 1 master and 8 slaves with the board length about 30 cm and slaves attached to the bus along the length. It worked at 12 MHz, but was unstable at 16 MHz. The bus capacitance was too high for the MCU pins to drive it. A stronger single-ended driver might have worked better.

author: rakeshm55
author_rank: Regular Contributor
timestamp: June 19, 2018, 05:19:24 am
content: My understanding is that SPI is used for commnication within a Board (Controller to Controller).When taken off-Board say to read a remote ADC wont there be a design guideline suggesting approximatetrace length supported for single ended transmission.Or is it just governed by the drive strength and capacitance of the trace.

author: ataradov
author_rank: Super Contributor
timestamp: June 19, 2018, 05:29:07 am
content: Just the drive strength and capacitance. At some point setup times are not met since it takes time to charge the capacitance of the trace. You can take care of some of that with proper bus termination and all that stuff. At some point you need to consider your bus to be a transmission line and apply the rules accordingly.And I suspect that in my case it would work fine at 16 MHz if it was not for a Christmas tree-like placement of the slaves on the bus.

author: rakeshm55
author_rank: Regular Contributor
timestamp: June 19, 2018, 05:33:48 am
content: So what will be worst case capacitance for per unit length of PCB trace??

author: ataradov
author_rank: Super Contributor
timestamp: June 19, 2018, 05:35:11 am
content: I have no idea. In practice, it is easier to just make a simple demo board and try.Differential drivers on their own won't help, you will still have to deal with the transmission line matching.

author: David Hess
author_rank: Super Contributor
timestamp: June 19, 2018, 10:26:50 am
content: 30cm is about right. The series resistance of a CMOS logic output and capacitance of the transmission line limits the rise and fall times to about 3ns. Two way propagation delay through the transmission line is about 0.1ns/cm so 3ns/(0.1ns/cm) is 30cm. Beyond this and the receiver will have trouble seeing edges which linger between logic levels.If you limit the bandwidth further by adding series resistance at the driver, then the distance can be extended but at some point the slower rise and fall times will cause problems at the receiver. This would be appropriate for a low power design.The other easy option is to drive the lines directly with a minimum of series resistance but add parallel AC termination at the receiver. This is a lot harder on the driver which will need to source 20mA or more on signal edges.The differential solution is appropriate for operation at high speeds and lower power and where ground noise between the driver and receiver is significant.In the analog world double termination might be used but it has a problem with digital signals because it divides the signal at the receiver in two and logic inputs do not like that. Usually parallel termination in one form or another like parallel AC termination discussed above is used instead.

author: dmills
author_rank: Super Contributor
timestamp: June 19, 2018, 10:58:35 am
content: Note that source termination only really works properly on point to point links, anything that is multidrop really needs parallel termination at the far end.This is because the source termination relies on absorbing the reflected wave at the source so any devices midway along the line see both an incident and a reflected edge.I would note that it is NOT the clock rate that matters here, but the edge rate, slow down the edges and you can work over longer distances, but may have degraded noise immunity because each edge spends longer close to threshold, overly fast drivers are not your friends.Regards, Dan.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 19, 2018, 01:02:12 pm
content: Yes and no.Yes without termination and other signal quality considerations, see above.With signal quality considerations, you are still limited by the round-trip distance delaying returning data (MISO). Data is set up on one clock edge and sampled on the other, so you have a half cycle limit. Example, at 10MHz, velocity factor 0.67 (regular coax), the limit is 10 meters. (At slower rates, you probably have some more signal quality considerations -- due to losses in the long line. At 100m, you may want a regenerator (buffer) in the middle.)No with considerations: SPI can be extended arbitrarily, by driving a transmission line (using coax for single-ended transmission, or e.g. RS-422 transmitters and receivers for twisted pair), and inserting a regenerator and synchronizer periodically.Note that RS-422 can be used seamlessly as a cable signaling standard, with big wins for signal quality. Expect to pick up many volts of interference on a long cable run. RS-422 receivers have over 7V of common mode range, whereas straight logic has hardly a volt of noise immunity.Hmm, a synchronizer should still incur a cycle delay, lest it imply violating the speed of light. You get a half cycle of allowance built in, but beyond that... Eh, I'd have to draw a diagram to see what's missing.In any case, whatever delay MISO has at the end, you need to account for that on the receiver. You may want to build a custom receiver (i.e., just a 74HC595) with delayed clock action to recover the data properly. Then you'd be reading data back from a GPIO port, rather than the SPI register. Small change, on most platforms, I think.As you can see, "possible" isn't necessarily "practical". You're better off with a proper long-distance standard over, say, tens of meters. For embedded stuff, if it doesn't need to go fast, asynchronous serial is fine (particularly over RS-485, very popular in industry). CANbus is great, very reliable (error checking and recovery is baked into the hardware). Ethernet is powerful, though it has a lot of overhead; much of that is provided in hardware on the more powerful MCUs, which have more than enough power to handle the higher level protocols as well.Tim

author: rstofer
author_rank: Super Contributor
timestamp: June 19, 2018, 02:57:17 pm
content: How fast is fast? I'd hate to think we're talking about 1 MHz and below at 1 foot of trace.I'm running a 6" cable (unterminated) between an FPGA and an LPC1768 at around 12.5 MHz and there has never been a problem. There are 200 Ohm series resistors on the FPGA board to protect the pins and eliminate reflections. 3.3V logic...

author: David Hess
author_rank: Super Contributor
timestamp: June 20, 2018, 01:57:54 am
content: Quote from: rstofer on June 19, 2018, 02:57:17 pm1 foot is about 1.5 nanoseconds so no problem with most unterminated CMOS. This is the length where fast CMOS starts to have problems which you can see on a fast oscilloscope.Quote6 inches is 0.75 nanoseconds so even less of a problem especially with 200 ohm series resistors limiting rise and fall time.