Flags in verilog/cross talk between modules - Page 1
Forum section: electronics / general

author: gauravmp
author_rank: Regular Contributor
timestamp: August 10, 2016, 12:29:32 pm
content: Hi,I have multiple modules and a top level module in verilog and I plan on used these subsidiary modules like functions in c when you program a microcontroller. Could someone tell me an easy way to have a state machine run within a subsidiary module an 'x' number of times with a command from the top level module?I've thought about it and I wanted to implement something like a flag that would go off in the top level module with the flag port being accessed by the subsidiary module thus reacting to it. However, I've reached a roadblock and i have not figured out how to give that flag.Any help would be appreciated.Thanks,Gaurav

author: rstofer
author_rank: Super Contributor
timestamp: August 10, 2016, 02:11:50 pm
content: Load a counter? The sub module looks at the counter and makes one pass per count?

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: August 10, 2016, 04:29:26 pm
content: Post your code. That'll help us help you.

author: gauravmp
author_rank: Regular Contributor
timestamp: August 11, 2016, 02:55:52 pm
content: Thanks for your replies. Here's my code for UART:module uart(clk,tx,data,send_req, //this would be high for one clock periodsent,tx_busy,//debugging purposestransmit_flag,state,tick,count);input clk;input data;input send_req;output count;output tick;output state;output transmit_flag;output tx;output sent;output tx_busy;reg[14:0] count;reg[3:0] state;reg muxbit;reg[7:0] tx_data;reg start;reg transmit_flag;reg tx_busy;reg sent;wire[7:0] data;wire tick;initialbegin/*sent <= 0;*/transmit_flag <= 0;tx_busy <= 0;count <= 0;end//baud rate generator:always @(posedge clk)begincount<=count+1;if(count == 5208)count <= 0;endassign tick = (count==5208);//manager//always @(posedge clk)//begin// if((send_req)&(~tx_busy))// begin// tx_data <= data;// transmit_flag <= transmit_flag + 1;// end// if(done)//end//transmissionalways @(posedge tick)beginif((send_req)&(~tx_busy))begintx_data <= data;transmit_flag <= transmit_flag + 1;endcase(state)4'b0000: beginsent <= 0;if(transmit_flag)begintx_busy <= 1;transmit_flag <= transmit_flag - 1;state <= 4'b0100;endend4'b0100: begin state <= 4'b1000; end // start4'b1000: state <= 4'b1001; // bit 04'b1001: state <= 4'b1010; // bit 14'b1010: state <= 4'b1011; // bit 24'b1011: state <= 4'b1100; // bit 34'b1100: state <= 4'b1101; // bit 44'b1101: state <= 4'b1110; // bit 54'b1110: state <= 4'b1111; // bit 64'b1111: state <= 4'b0001; // bit 74'b0001: begin state <= 4'b0000; tx_busy <= 0; sent <= 1; end// stop1default: state <= 4'b0000;endcaseendalways @(state[2:0])case(state[2:0])0: muxbit <= tx_data;1: muxbit <= tx_data;2: muxbit <= tx_data;3: muxbit <= tx_data;4: muxbit <= tx_data;5: muxbit <= tx_data;6: muxbit <= tx_data;7: muxbit <= tx_data;endcase// combine start, data, and stop bits togetherassign tx = (state<4) | (state & muxbit);endmoduleA signal send_req from the top level module will activate it. Sure, but I want to change it so I could control this module to be executed just once or an x number of times.Any help would be appreciated.

author: antti
author_rank: Contributor
timestamp: August 11, 2016, 05:43:32 pm
content: RULE #1 FPGAs do not EXECUTE the code you writeRULE #2 FPGAs do not EXECUTE the code you writeRULE #3 FPGAs do not EXECUTE the code you writeFGPAs implement the HARDWARE you DESCRIBEand this hardware you have DESCRIBED does exactly what you described what it should do.you should understand this first, then you can ask questions properlyFPGAs are like magic, they become whatever you want them to be, you just have to know how to describe your wish.verilog is one of the languges you can use to describe your wishes.