Sigma-Delta ADC Layout, Signal Integrity - Page 1
Forum section: electronics / projects

author: w00t
author_rank: Newbie
timestamp: August 26, 2020, 12:51:50 am
content: I am laying out an ADuM7701 isolated sigma-delta modulator ADC. This will run around 20MHz and I'm concerned about noise affecting my analog measurements.I've attached photos of the schematic and my layout attempt. This will be a 6-8 layer PCB with both PWR and GND planes connected directly to their respective vias. Note that the analog side (left) is isolated from the digital side (right). The pads are test points for a scope probe tip to directly fit in. Some design rationale for the decoupling cap layout includes:- I added multiple vias per 5V/GND to decrease loop inductance. I kept the opposing current vias (5V/GND) close together, and same current direction vias (GND/GND, 5V/5V) apart to reduce mutual inductance.- The tracks from each ground pin to each decoupling cap ground provide a low inductance path from each PWR pin to GND pin for the IC.I'm not sure if the 5V via placement (one at the pin, one at the decoupling cap) makes sense. The idea is related to this StackExchange thread which doesn't seem to have a consensus on via placement -https://electronics.stackexchange.com/questions/15135/decoupling-caps-pcb-layout.Also, will the in-line test points affect my digital signal integrity at 20MHz? I may need pretty long trace lengths, I have source or termination impedance matching resistors on each digital line, and plan on doing impedance controlled routing.Any criticism appreciated, thanks!

author: KT88
author_rank: Frequent Contributor
timestamp: August 26, 2020, 07:15:29 am
content: Two things need to be adressed here - The ADC and the power supply / isolation technology related challenges:1. Having anything other than the ADC related GND (GND_ISO_IPM12) as the ground plane for the ADC is a recipe for desaster.Any difference between GND_ISO_IPM12 and GND_I_V will couple into the ADC input. It directly challenges the CMRR of the analog input - especially with no common-mode filter for the analog signal - you only implemented a differential mode filter with C11 which serves as an AAF.The remedy for that problem is to use the GND_ISO_IPM12 potential sa the ground plane for the whole analog input circuit.In addition to to C11 you add a capactor of (usually) 1/10 the differential mode capacitance to GND_ISO_IPM12 from VIN+ and VIN- (directly at C11).A testpoint won't be an issue if you add another one to VIN-. It is crutial to have the exact same impedances for VIN+ and VIN-. If not, you will experience mode conversion which even bypasses your AAF. That causes the whole frequecy spectrum from DC to orange light to interfere with your input signal....Aiming for perfect symmetry helps...2. The isolation is done with chip scale air core transformers that opreate at very high frequency. This generates both common mode- and differential mode noise. This requires to be very careful with bypassing of the power supply. Thin traces like in your layout won't work at all... You need wide traces for the supply.The GND pins on both sides get a via with a preferably wider hole to it's ground plane located in the layer directly below it. The decoupling cap(s) is placed as close as possible to VDD and again connected to it's ground plane.I prefer to use small, same size, same value capacitors in parallel to get to the desired decoulpling capacitance - in your case probably 2x 4.7uF in 0603.CheersAndreas

author: Jeroen3
author_rank: Super Contributor
timestamp: August 26, 2020, 07:30:33 am
content: This package allows to use the following decoupling strategy using 1206 caps.There probably are downsides to running traces under caps, but I think it's fine. It will add like less than half a pf to the trace. Should be fine.

author: KT88
author_rank: Frequent Contributor
timestamp: August 26, 2020, 07:03:11 pm
content: The isolation transformers are driven at very high frequencies with quite some current. Although the designers probably have done a thoruogh frequency planning to avoid self disturbances, the RF magnetic- and electric fields could well interfere with the filter and the input circiutry of the IC when the amplidude of the disturbance gets high enough. In the arrangement with the 1206-cap you get a considerably large loop area causing both strong manetic fiels as well as inferiour decoupling. If you run a C-shaped,wide trace below the package the current ripple runs well underneath the package traces thus maintaing the smallest possible loop area without hampering the creepage distance.The only case I would consider the 1206 approach would be if isolation requirements don't allow vias to appear on the bottom side because cost constraints don't allow the use of blind vias...

author: w00t
author_rank: Newbie
timestamp: August 26, 2020, 08:11:04 pm
content: Thank you for the detailed feedback, I tried again and have attached the new layout. Some of the nets are renamed, but it's the same idea.1.About common-mode noise - this is an ADC powered by a floating PSU measuring phase current at the output of a half-bridge inverter. I can't use a common ground between the analog and digital sides because there are multiple ADCs on multiple inverter legs that all communicate with the same FPGA. Instead, I could implement a common-mode filter like in the second attached photo.2.I added symmetrical testpoints on the analog (left) side. The analog inputs are now a differential pair and they are currently as symmetrical as possible.I used fills instead of thin traces for power out of convenience. The vias can do ~2A each from the Saturn PCB calculator, and most of the current will be supplied by the capacitors anyways. Would the air core transformers draw a ton of current?3.I tried the 1206 layout method. Why is it worse decoupling and larger loop area? It seems like the loop between PWR and GND of the IC is smaller.

author: KT88
author_rank: Frequent Contributor
timestamp: August 26, 2020, 09:23:41 pm
content: The second image shows what I mean concerning the input filter. As mentioned a good starting point for the capacitance ratio is Cdiff=10Ccm. This helps to avoid mode coversion due to tolerances of Ccm.I still don't like the bypassing though. You will get a bout 3at 100MHz that way and roughly 30 \$\Omega\$at 1Ghz. This is based on a quick LTSpice simulation of a 10uF / 1206 capacitor model in series with 5nH. I even didn't account for the inductance within the package. As the spectral content of the tranformer driver goes well beyond 100MHz at a couple of mAs you will challenge the PSRR of the ADC quite a bit. The PSRR and CMRR plots in the DS go only up to 1MHz. Usually these values drop significantly above 10MHz...The smaller 100 nF cap wont't help you because it is has such high trace inductance in series that it possibly will only make it worse by conributing a resonant peak where it hurts...The attached image is a cut-out of an image of the EVAL-ADuM7701.