No output for NPWM generation on SAMD20 (No ASF) - Page 1
Forum section: electronics / general

author: matthew_zammit
author_rank: Newbie
timestamp: March 06, 2018, 08:05:57 pm
content: Hi, I've been at this for quite some time now. I'm trying to generate a simple PWM using the NPWM wavegen mode but I get no output. I've tried using interrupts and it works fine but I need to use hardware generated PWM since CPU resources are crucial.My suspicion is that the multiplexing pin configuration is wrong on my side. Below is the Timer initialization function.//PB30 -- Tc0 Pwm outputvoid init_LED_Driver(){//PWM INPUT PIN INITREG_PORT_DIRSET1 = PORT_PB30;PORT->Group.PINCFG.reg |= PORT_PINCFG_PMUXEN; //| PORT_PINCFG_DRVSTR PERIPHERAL MULTIPLEXING FOR ADC_INPUT -- uncomment for increased o/p drive strengthPORT->Group.PMUX.reg |= PORT_PMUX_PMUXE_E; // ENABLE TC0/WO/*Set the GENDIV.DIV TO DECIMAL 0and configure the settings to GCL3*/REG_GCLK_GENDIV = GCLK_GENDIV_ID_GCLK3 | GCLK_GENDIV_DIV(0);while(GCLK->STATUS.bit.SYNCBUSY); // WAIT FOR SNCHRONIZATION OF CLKS AFTER RESET/*DIVIDE GCLK2 BY 2^(GENDIV.DIV+1)CLOCKED BY 32.768KHZ inTERNAL OSCILLATOR -- ACCURACY NOT THAT IMPORTANTgclK O/P FREQ = 16.3KHZ*/REG_GCLK_GENCTRL = GCLK_GENCTRL_DIVSEL | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC32K | GCLK_GENCTRL_ID_GCLK3;while(GCLK->STATUS.bit.SYNCBUSY); // WAIT FOR SNCHRONIZATION OF CLKS AFTER RESET// Configure ClocksREG_GCLK_CLKCTRL = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_TC0_TC1;REG_PM_APBCMASK |= PM_APBCMASK_TC0; // Enable TC0 APB clock BUS// Configure TC0 (8 bit counter by default)// Run in standby// Normal PWM generationREG_TC0_CTRLA |= TC_CTRLA_MODE_COUNT8 | TC_CTRLA_PRESCALER_DIV1 | TC_CTRLA_RUNSTDBY | TC_CTRLA_WAVEGEN_NPWM | TC_CTRLA_PRESCSYNC_GCLK;while(TC0->COUNT8.STATUS.bit.SYNCBUSY); // Wait for sync// Get continUous read request from clockREG_TC0_READREQ |= TC_READREQ_RCONT | TC_READREQ_RREQ;while(TC0->COUNT8.STATUS.bit.SYNCBUSY); // Wait for sync//This register controls the period -- 100HZREG_TC0_COUNT8_PER = 164;while(TC0->COUNT8.STATUS.bit.SYNCBUSY); // Wait for sync//This register controls the duty cycle -- 50%REG_TC0_COUNT8_CC0 = 82;while(TC0->COUNT8.STATUS.bit.SYNCBUSY); // Wait for sync// Enable TC3REG_TC0_CTRLA |= TC_CTRLA_ENABLE;while (TC0->COUNT8.STATUS.bit.SYNCBUSY); // wait for TC0 to be enabled}Thanks in advance

author: ataradov
author_rank: Super Contributor
timestamp: March 06, 2018, 08:41:06 pm
content: TC0/WO is on MUX F, not E.

author: matthew_zammit
author_rank: Newbie
timestamp: March 06, 2018, 09:04:36 pm
content: Wow that was actually it. Weird that the datasheet from Atmel's website doesn't tell you this tho. Keil provides a more proof read datasheet for anyone using SAMD microcontrollers.Thanks

author: ataradov
author_rank: Super Contributor
timestamp: March 06, 2018, 09:07:03 pm
content: What do you mean it does not? How do you think I got this information? Columns for E and F are both allocated for TC, but they are clearly different.Also, the latest datasheets are on Microchip site, I'm not sure what is published on Atmel site.

author: matthew_zammit
author_rank: Newbie
timestamp: March 06, 2018, 11:53:09 pm
content: I've attached the two mentioned datasheets for the same alleged SAMD20

author: ataradov
author_rank: Super Contributor
timestamp: March 06, 2018, 11:55:05 pm
content: Well, they don't seem to update the atmel.com. Anyway, it is better to look for datasheets on microchip.com.

author: ajb
author_rank: Super Contributor
timestamp: March 07, 2018, 01:03:18 am
content: The datasheet currently on Microchip's website is correct (and has already been updated to match Microchip's document style). The one you have must be an old version.