PIC controller and high speed signals - Page 1
Forum section: electronics / projects

author: DavidDLC
author_rank: Frequent Contributor
timestamp: May 05, 2012, 06:53:51 am
content: I want to make a project to decode serial signals with clock frequencies around 50 MHz or maybe more.Does anybody knows a good PIC microcontroller to achieve this task ?David.

author: cyberfish
author_rank: Regular Contributor
timestamp: May 05, 2012, 07:05:09 am
content: To do bit-banging at 50MHz, the PIC will probably have to run at about 200MHz instruction clock, or 800MHz CPU clock.Even a very fast microcontroller like a STM32F4 (200 MHz Cortex-M4) will struggle to keep up.At this frequency, programmable logic (FPGA) probably makes more sense.

author: DavidDLC
author_rank: Frequent Contributor
timestamp: May 05, 2012, 07:14:44 am
content: Thanks for the answer, do you know a development board and the programmer ?David.

author: cyberfish
author_rank: Regular Contributor
timestamp: May 05, 2012, 07:17:52 am
content: For FPGAs? I don't really know. Last time I checked they are all very expensive.I always designed my own FPGA boards. Could be much cheaper depending on your PCB design experience.For programmers, I've been using a clone from ebay. Works perfectly and it's about 1/3 the price of the real thing.

author: DavidDLC
author_rank: Frequent Contributor
timestamp: May 05, 2012, 07:43:30 am
content: Cyberfish thanks again, what FPGA do you use, I'm may be able to do the board design.David.

author: cyberfish
author_rank: Regular Contributor
timestamp: May 05, 2012, 07:45:27 am
content: I have used Spartan-3AN. It's pretty convenient since it's available in TQFP (hand-solderable), and only needs 2 supply rails, so doable on a 2 layer board. I believe Spartan-6 is similar.AFAIK, all Altera chips require 3 voltage rails, which means you'll need 4 layers minimum.

author: cyberfish
author_rank: Regular Contributor
timestamp: May 05, 2012, 07:52:30 am
content: Oh and if you want higher density in TQFP (higher density chips from Altera and Xilinx are only available in BGA), Lattice has some nice chips. I've always wanted to try the LatticeXP, but never got around to.

author: Psi
author_rank: Super Contributor
timestamp: May 05, 2012, 07:59:25 am
content: I've never used them but i've seen dual microcontroller+FPGA in a single package.Atmel have some and probably others too.But for easy of development an FPGA dev board like others have suggested is probably the best option.

author: deephaven
author_rank: Frequent Contributor
timestamp: May 05, 2012, 09:24:15 am
content: I would recommend an Altera EPM570T100C5

author: nctnico
author_rank: Super Contributor
timestamp: May 05, 2012, 08:08:26 pm
content: Don't rule out CPLD devices! They are often easier to use because they retain their programming, offer more predictable timing, are cheaper and run on one commonly available voltage. I really like to use the XC9500XL series from Xilinx for simple (*) things. They are supported by the latest version of Xilinx' free Webpack software.(*) I used one for for rescaling an interlaced video output onto a 640x480 TFT display.

author: free_electron
author_rank: Super Contributor
timestamp: May 05, 2012, 08:22:43 pm
content: buy a devkit from terasic. there is a 50$ one that has programmer and a reasonalby big CPLD on board. everything you need to get started.you cant make a board like that yourself (6 layers and BGA device... ) not at that pricepoint...there are cplds and fpga in tqfp packages , but even there you very quickly need 4 layers..

author: nctnico
author_rank: Super Contributor
timestamp: May 05, 2012, 09:07:50 pm
content: Quote from: free_electron on May 05, 2012, 08:22:43 pmNonsense. You can even use veroboard for a CPLD in a PLCC package:http://imageshack.us/photo/my-images/815/p1010808z.jpg/For the TFT rescaler I mentioned before I used a double sided PCB where I used one layer as a ground plane. It basically is a single sided PCB design so it is easy to etch by yourself (see picture below for another example)! A CPLD allows the pins to be assigned freely therefore you can arrange the pins so you never need a via. Needing only one power supply allows to put a copper pour underneath the CPLD. Even on a 2 layer board you can have excellent power supply bypassing.

author: free_electron
author_rank: Super Contributor
timestamp: May 06, 2012, 02:08:51 am
content: i said TQFP , not PLCC .. in PLCC there are slim pickins. you are lucky to get 128 flipflops ( like a EPM7128 in PLCC84 ) i don't even consider those anymore since they are way more expensive than a MAX II and offer very little logic for their price.

author: DavidDLC
author_rank: Frequent Contributor
timestamp: May 06, 2012, 07:38:30 am
content: Quote from: free_electron on May 05, 2012, 08:22:43 pmWhich devkit will be able to decode signals with a clock freq of 50 MHz ?David.

author: cyberfish
author_rank: Regular Contributor
timestamp: May 06, 2012, 08:13:12 am
content: I have done TQFP FPGAs (Spartan-3AN) on 2 layer, using almost all the IOs, and still have fairly good decoupling. Definitely possible.

author: nctnico
author_rank: Super Contributor
timestamp: May 06, 2012, 10:15:40 am
content: Quote from: free_electron on May 06, 2012, 02:08:51 amSame story. I just don't have a picture from a similar design using a TQFP device.

author: joelby
author_rank: Frequent Contributor
timestamp: May 06, 2012, 11:12:20 am
content: I maintain a list of cheap FPGA development boards athttp://tristesse.org/FPGA/CheapFPGADevelopmentBoards. I'm most familiar with Xilinx parts, for which I'd recommend the Digilent Nexys2, Nexys3 or Atlys, all of which have some sort of high speed I/O connector with lots of grounds, which Is highly recommended if you're working with high speed signals.

author: free_electron
author_rank: Super Contributor
timestamp: May 06, 2012, 01:52:10 pm
content: Yes you can get away with double sided , and i have done that too , but it becomes a mess.. 4 layer is perfectly fine, even seedstudio can make you 4 layer boards now for cheap.Ts wants to capture signals at 50MHz ... I'd say go 4 layer ... For the sake if signal integrity alone ...