SWD-CAN bus bridge by STM32 - Page 1
Forum section: electronics / general

author: BUTTHEAD
author_rank: Newbie
timestamp: March 06, 2019, 06:54:30 pm
content: Hi! I want to design SWD-CAN bridge to program and debug STM32 devices via CAN. The bootloader is not suitable because it can upgrade firmware to CPU, but not allow tracking. I need something like ST-LINK, but with CAN interface.My idea: the board have, simplifying, 2 CPU: 1 - main CPU, which do base program, and 2 - CPU, which can reprogram main CPU and wath for additional information (safety function). CPU#2 receive frames via CAN bus by predefined protocol, hold its in memory , check for errors, and then (if no errors found), load it to CPU#1 via SWD. User can look for program using STM Studio or something else. There are no need in printf (something).But I did not find nor description of SWD for Cortex M3, nor code examples of making SWD master.

author: ataradov
author_rank: Super Contributor
timestamp: March 06, 2019, 07:10:30 pm
content: Here is example of one MCU programming anther MCUhttps://github.com/ataradov/embedded-swdIt is for Microchip parts, so you would have to change stuff in the dap_target.c to match your STM device. The DAP part will be universal.There is not a single document that describes everything about SWD. The low level protocol (physical signalling and the DAP part) is described in the ARM documentation. This will give you access to the MCU as master on the bus.After that you need to access the flash controller to perform the actual programming. And this is covered by the ST user manuals for specific devices.

author: BUTTHEAD
author_rank: Newbie
timestamp: March 06, 2019, 07:49:12 pm
content: Thanks a lot!QuoteI have found this document:ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2https://static.docs.arm.com/ihi0031/c/IHI0031C_debug_interface_as.pdfIt is good start?QuoteI am look this code, and find that, for exampleCode:#define DHCSR 0xe000edf0And, according this:http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/CEGCJAHJ.htmlThe DHCSR:is a 32-bit read/write registeraddress is 0xE000EDF0Is this defines common for all Cortex M3 based parts?Code:dap_write_word(DHCSR, 0xa05f0003);Debug Key. 0xA05F must be written whenever this register is written.Set C_HALT, C_DEBUGEN

author: ataradov
author_rank: Super Contributor
timestamp: March 06, 2019, 07:53:34 pm
content: Quote from: BUTTHEAD on March 06, 2019, 07:49:12 pmYes, this will contain most of the stuff you need.Quote from: BUTTHEAD on March 06, 2019, 07:49:12 pmYes, DHCSR, DEMCR and AIRCR are common for all parts, and the values written should be the same too.

author: BUTTHEAD
author_rank: Newbie
timestamp: March 06, 2019, 10:05:56 pm
content: And some more questions:Code:dap_write_word(NVMCTRL_CTRLB, 0);Is it command for flash controller to enable write operation?And what isCode:#define DSU_DID 0x41002118?Is I need for beginning find the same registers on desired MCU?Code:uart_puts("\r\nDSU_DID = ");uint32_t dsu_did = dap_read_word(0x41002118/*DSU_DID*/);uart_puthex(dsu_did, 8);uart_puts("\r\n");Here something on address 0x41002118 read and put to uart. In same way it can be readed any adress (variable or hardware register)?Also I am not properly understand, how to access to SWD port.

author: ataradov
author_rank: Super Contributor
timestamp: March 06, 2019, 10:10:42 pm
content: Quote from: BUTTHEAD on March 06, 2019, 10:05:56 pmThis is the MCU-specific stuff. This part will be completely different for ST. DSU_DID is a device identification register, and CTRLB configures some stuff for the flash controller in the Microchip SAM D21.Quote from: BUTTHEAD on March 06, 2019, 10:05:56 pmYes. dap_read_word() and dap_write_word() let you read/write any location inside the MCU memory map. You can toggle the pins, send UART characters, and generally do whatever CPU core can normally do. Debugger in this case just takes over the core (hence all those commands to halt the core).Quote from: BUTTHEAD on March 06, 2019, 10:05:56 pmWhat exactly do you mean by "access"?

author: BUTTHEAD
author_rank: Newbie
timestamp: March 06, 2019, 10:16:32 pm
content: Code:What exactly do you mean by "access"?How to toggle this pins on master device by specification? Is it software implementation of SWD state machine?

author: ataradov
author_rank: Super Contributor
timestamp: March 06, 2019, 10:19:29 pm
content: Quote from: BUTTHEAD on March 06, 2019, 10:16:32 pmYes, it is purely software thing. That's exactly what code in dap.c does. You can take it as is. All you need to do is re-implement functions for toggling the actual pins for your master in dap_config.h.

author: BUTTHEAD
author_rank: Newbie
timestamp: March 08, 2019, 09:44:11 pm
content: According ST reference manual:QuoteAnd, according Debug Interface Architecture:QuoteSo, is I need to implement reading this register in function dap_target_select()?Secondary,QuoteIf I need to only watch by some variable, it is no need to halt core, or I must do this anyway?

author: ataradov
author_rank: Super Contributor
timestamp: March 08, 2019, 09:47:17 pm
content: No, this is already done in the dap_reset_link().You don't have to halt the core if you don't actually program the flash. You can read/write any registers you like while the core is running. You need to stop the core if you are writing the flash to avoid potential code execution from the same area you are about to write.

author: BUTTHEAD
author_rank: Newbie
timestamp: March 08, 2019, 09:58:39 pm
content: I found it. As I understand, theCode:dap_swj_sequence((7 + 2 + 7 + 1) * 8, buf);need to the DP has switched from JTAG to SWD. Correct?

author: ataradov
author_rank: Super Contributor
timestamp: March 08, 2019, 10:00:36 pm
content: Quote from: BUTTHEAD on March 08, 2019, 09:58:39 pmYes, exactly. It is a standard sequence mentioned somewhere in ARM documents.

author: Tamashny
author_rank: Newbie
timestamp: March 26, 2025, 07:28:08 am
content: Hi, BUTTHEAD!Have you succesed with this task or you have not?