Interfacing cheap DDR-SDRAM with 8-bit controller via software on 2-layer PCB - Page 1
Forum section: electronics / general

author: soFPG
author_rank: Frequent Contributor
timestamp: March 16, 2019, 06:40:26 pm
content: Hi,I once thought about extending the RAM capabilities of a microcontroller I was using by adding an external SRAM-chip, which could be interfaced by a serial protocol (e.g. SPI / I²C).Sadly, these external SRAMs with serial protocol are quite expensive and only reasonably priced until around 1Mbit.I then took a look at Aliexpress, and they sell5Pieces of DDR-SDRAM (32Mbyte x 16Bit) for a little bit over2$(https://www.aliexpress.com/item/5pcs-lot-HY5DU121622CTP-D43-HY5DU121622CTP-DDR64M-SDRAM-TSSOP-66/32954967053.html).Of course, interfacing SDRAM is a lot (a lot) more complex than using already built in SPI / I²C.But I was wondering, especially because these SDRAM-Chips are comming in a solderable TSSOP package, if interfacing this chips could be done not only on a 2-layer PCB but also without any hardware support from a microcontroller, only via pin toggling?This may sound crazy - but it seems like an interesting project to me.

author: nctnico
author_rank: Super Contributor
timestamp: March 16, 2019, 07:21:53 pm
content: No. Look at the datasheet. The minimum time for TCK is 10ns which is 100MHz for the slowest versions.

author: soFPG
author_rank: Frequent Contributor
timestamp: March 16, 2019, 07:33:39 pm
content: Okay, I didn't know there is a minimum clock frequency.What about this one (https://4donline.ihs.com/images/VipMasterIC/IC/ISSI/ISSI-S-A0001634248/ISSI-S-A0001634248-1.pdf- page 18). It doesn't define a maximum vor tck_2 and tck_3?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: March 16, 2019, 08:10:19 pm
content: SDR SDRAM is pretty easy, things get quite a bit more complex for DDR

author: soFPG
author_rank: Frequent Contributor
timestamp: March 16, 2019, 08:41:17 pm
content: QuoteI actually found a lot of SDR SDRAM DIMM modules on ebay for as low as 3$, and they come with 8 memory ICsDo you have any information on how to get started with SDR SDRAM? Is it important to exactly match the trace length for data and adress lanes?What about the capacitance? For example, I found this description for an old SDR SDRAM chip in one of those ebay dimm modules (see attachments).Do I have to add 50pf capacitor and 250Ohm resistor for each output line? And how should I keep these strict capacitance rules for input (2pF - 3.5pF) and output (4pf - 6.5pf)? How much capacitance does a 6mil trace has?All these questions

author: edavid
author_rank: Super Contributor
timestamp: March 16, 2019, 08:50:49 pm
content: You are misreading the datasheet.1. The chip will meet its timing specs with the specified load. If there is less load, it will be a little faster.2. The other specs are saying what the capacitance of the chip pins is. You use this to design your drive circuits and PCB traces.Maybe you would be better off working your way up from SRAMs, which are also pretty cheap, e.g. HM628512 512Kbyte for less than $1.

author: soFPG
author_rank: Frequent Contributor
timestamp: March 16, 2019, 09:02:22 pm
content: QuoteOkay, thanks for your reply.Is there something I should pay particular attention while making the PCB?Although the data sheet specifies certain guidelines, how important are these in practice? I would imagine that some do not have to be kept very accurate (for example, the exact same tracelength).

author: Axk
author_rank: Regular Contributor
timestamp: March 16, 2019, 09:22:42 pm
content: I recently did a 2 layer "shield" board for an Altera Cyclone IV dev board with a 128Mbit Micron SDR SDRAM chip as a frame buffer for a camera module and outputting that to a VGA port.I didn't do any trace length matching and it works fine at 100MHz in my case (see the attachment).As to controlling the SDRAM in my case it was just a simple frame buffer with long sequential reads and writes and no refresh because it re-writes the same rows repeatedly all the time.Still this rudimentary controller took quite some time to design in Verilog (granted I didn't have any experience with logic design).I don't know how you would do it in software because it's all strict timing, but probably it's possible.Doing a general-purpose SDRAM controller for a processor would be an order of magnitude more complicated then my frame buffer one.So I think you need a processor that has some SDRAM support, doing it on your own would be quite difficult (a couple of months of work at least).

author: soFPG
author_rank: Frequent Contributor
timestamp: March 16, 2019, 09:27:28 pm
content: QuoteMaybe I am wrong, but take this datasheet: (page 17-18;https://pdf1.alldatasheet.com/datasheet-pdf/view/98999/INFINEON/HYB39S64160BT-8.html).For almost all of the timings there isn't even a max rating defined, so am I wrong with the assumption that there aren't really any stressfull timings besides the 4096 refreshes in 64ms?

author: Axk
author_rank: Regular Contributor
timestamp: March 16, 2019, 09:39:22 pm
content: QuoteYes, I think you're right, if you don't need good throughput then it only has minimum timings and everything is synchronous with the clock.And it should be easier to implement in software then FPGA, and it's probably already implemented by someone.But still I would look for an existing implementation unless you want to learn the details of SDRAM interfacing.

author: soFPG
author_rank: Frequent Contributor
timestamp: March 16, 2019, 09:51:18 pm
content: "unless you want to learn the details of SDRAM interfacing."That is exactly the reason why I am doing all this.Do you have any idea if there should be capacitors / resistors used for the address or data lines? Or any special circutry? I honestly do not see anything special on your layout

author: magic
author_rank: Super Contributor
timestamp: March 16, 2019, 09:53:59 pm
content: It's been done.http://dmitry.gr/?r=05.Projects&proj=07.%20Linux%20on%208bit

author: Axk
author_rank: Regular Contributor
timestamp: March 16, 2019, 10:01:17 pm
content: QuoteI didn't use any, the headers on the board go straight to the FPGA on the FPGA board.The only capacitors I have are bypass caps.I do have a pullup on CKE but it's not connected in my case because I ran out of FPGA board header pins (it still worked without driving CKE low in the beginning of the initialization).

author: Rasz
author_rank: Super Contributor
timestamp: March 17, 2019, 12:47:21 am
content: seems relevanthttps://hackaday.io/project/4159-sdramthing45-logic-analyzerhttps://hackaday.io/project/10119-sdramthingzero-133mss-32-bit-logic-analyzer

author: TimCambridge
author_rank: Regular Contributor
timestamp: March 17, 2019, 02:29:20 am
content: HyperRAM? Only seems to be available in BGA, but it's a pretty tolerant 0.8mm ball spacing.

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: March 17, 2019, 10:03:34 am
content: Interfacing SDR is pretty straightforward. I think the PCB layout is not that critical, because you won't be driving it at max speed.I've seen a few cobbled together projects, and they do no more than wire the relevant pins to the micro, the rest is done in software. I have seen more COTS shields with DRAM, haven't seen any for SDR.I think I might design a board for these $2 chips...

author: soFPG
author_rank: Frequent Contributor
timestamp: March 17, 2019, 10:09:23 am
content: I know this makes me look like a guy who can't decide what he wants to build next, but I actually found asynchronous DRAM from Samsung in one of my drawers for old hardware. It comes in DIP and is located on an old graphics card, this is the datasheet (https://pdf1.alldatasheet.com/datasheet-pdf/view/125858/SAMSUNG/KM44C256B.html).There are two of those on the graphics card, so I get true 256Kbyte if I combine the 4 datalines of each one to 8.Does anyone know if there is something particularly special about async. DRAM and how to interface it? I see next to no caps and resistors around the RAM and also no length matching routes.

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: March 17, 2019, 10:13:42 am
content: Quote from: nctnico on March 16, 2019, 07:21:53 pmI don't get that.A minimum time implies a maximum frequency. A maximum time would imply a minimum frequency. There is no max time specified in the datasheet, therefore there is no minimum frequency.The "minimum" requirement for any type of dynamic RAM is the refresh frequency.

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: March 17, 2019, 10:24:40 am
content: Quote from: soFPG on March 17, 2019, 10:09:23 amI don't believe there is anything special. The only thing might be voltage levels, KM44C256 is a 5V part, you didn't say what MCU you are using.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: March 17, 2019, 10:43:28 am
content: Quote from: soFPG on March 16, 2019, 08:41:17 pmit's been a few years, but ISTR the Micron datasheets were particularly good. Speeds are low enough that length matching, trace capacitance etc. isn't an issue, and logic levels are standard 3.3v CMOS.

author: soFPG
author_rank: Frequent Contributor
timestamp: March 17, 2019, 11:04:58 am
content: QuoteThanks for the hint. I planned to use an EFM8LB1, which is a VDD_max = 4.2v (recommended 3.3V) 8-Bit MCU.The datasheet of the KM44C256B notes, that supply voltage ranges from 4.5 - 5.5Vbutan input-signal is already considered "High" at a minimum of 2.4V, so 3.3V from the GPIOs of the EFM8 should be enough to write data into the RAM.My only question would be - what happens the other way around (reading data from the RAM)? The GPIO pins of the EFM8LB1 are not 5V tolerant - do I need some kind of level shifter (or resistive divider)?Edit: It looks like there is this genious IC calledTXB0108which does bidirectional voltage translation and auto-detects the direction! It does that for 8-pins, so that is exactly the amount of pins I need (2 x 4-bit Databus) - solved (I guess)

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: March 17, 2019, 12:10:32 pm
content: Quote from: soFPG on March 17, 2019, 11:04:58 amI would avoid TXB type in this application, the auto-detect comes at a cost, and the rise/fall times may not be good enough. I've had problems with them, for low speed bit toggling they are probably OK. I would look at 74LVX4245 which are more suited for this type of application.https://www.mouser.co.uk/ProductDetail/ON-Semiconductor-Fairchild/74LVX4245MTCX?qs=sGAEpiMZZMs9F6aVvY09bui9XcwUuHpCXyVGlsWFsAo%3D

author: TimCambridge
author_rank: Regular Contributor
timestamp: March 17, 2019, 12:59:30 pm
content: Quote from: donotdespisethesnake on March 17, 2019, 10:13:42 amThe OP meant maximum period/minimum frequency. Mobile variants don't have this minimum frequency requirement.

author: NorthGuy
author_rank: Super Contributor
timestamp: March 17, 2019, 01:32:03 pm
content: Only fast DDRs, such as DDR3, require minimum speed (that is frequency cannot be lower than certain point), but even these have DLL-Off mode which can be as slow as you wish (if you can refresh it fast enough, of course).

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: March 17, 2019, 02:00:09 pm
content: QuoteUnless you really, really need bidirectionality, steer clear of these - they have high output impedance and can oscillate of there is much capacitance on them.

author: soFPG
author_rank: Frequent Contributor
timestamp: March 17, 2019, 02:40:07 pm
content: QuoteOkay, I used the 74LVX4245 in my design as you recommended.QuoteDo you know if the same is true for the 74LVX4245?I created a basic first schematic, it would be really nice if someone could take a brief look and tell me if there is something terribly wrong.The only thing I am worried about for the moment is, that at startup the address pins of the EFM8 are not set as GPIO output and could therefore be damaged if the DRAM outputs 5V (for some weird reason).Is that a legitimate concern?

author: soFPG
author_rank: Frequent Contributor
timestamp: March 20, 2019, 07:10:17 am
content: I would be very happy to receive any feedback to the schematic I posted above ☺

author: hamster_nz
author_rank: Super Contributor
timestamp: March 20, 2019, 07:27:50 am
content: I think some may be missing the obvious problem with SDRAM, that they need a refresh cycle, and you have to do them if you want your data to persist.At fast clock speeds the overhead of (say) 10 cycles every 8us is very low maybe a few %At 1MHz it is impossible to run SDRAM as you can't issues refresh quick enough, and it eats up all your bus bandwidth.This is a gross oversimplification, but you should get the idea - it is not practical until you start hitting around 10MHz or so because of the inherent nature of the technology.There is some "cellular dram" that hides the refresh internally. I've used it on a few old FPGA boards. That might work. See if you can find the part number used on the Digilent Nexys 2 FPGA dev board.

author: Siwastaja
author_rank: Super Contributor
timestamp: March 20, 2019, 08:25:24 am
content: Layout:Use a ground plane on the bottom; minimize number of tracks on it. Whenever you absolutely need a track there, try to arrange a piece of contiguous ground plane on the top, at the same place, and stitch the ground pieces together with vias on both side of the tracks. Follow the path of return currents of your data/address/clock/control lines; these run from the GND pins of your memory chip / MCU, possibly through vias, to your ground plane. On a 2-layer design, it's never perfect, and it's OK. But do take a careful look, a beginner can easily make a mistake (e.g., gap in the ground plane due to other traces; no stitching) which costsmany inchesof extra length for the return current, which can cause problems.Refresh:Note that while the datasheets tend to specify refresh times such as 64ms, this guarantees functionality in worst-case operating conditions (specifically, highest allowed temperature). If your device is your personal one-off and you know it's not going to ever operate near the maximum temperature, and it's not a life-critical system, by all means extend this time if it makes your life easier. I have personally made some tests at room temperature to see that actual data loss starts to happen between 5 and 10 minutes of no refreshing. A few second interval (instead of 64ms) is almost always safe if you leave some 30-40 degC margin to the highest operating temperature.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: March 20, 2019, 10:11:44 am
content: Quote from: Siwastaja on March 20, 2019, 08:25:24 amOn the flip side, don't just do refresh whenever the memory is idle as power consumption in refresh mode is very high & the chips can get really hot!

author: amyk
author_rank: Super Contributor
timestamp: March 20, 2019, 12:10:17 pm
content: Quote from: Siwastaja on March 20, 2019, 08:25:24 amIn a different context, some others tried to characterise this, and found that it varies widely:https://cacm.acm.org/magazines/2009/5/24652-lest-we-remember/fulltext(see figure 2)

author: soFPG
author_rank: Frequent Contributor
timestamp: March 20, 2019, 08:41:37 pm
content: Why are the replies from @amyk, @mikeselectricstuff and @Siwastaja so different from @hamster_nz?If I have interpreted your answers correctly, my schematic does not contain any mistakes?The only thing I should be carefull about is routing the PCB?Edit: I don't get why clockrates <= 1MHz would be a problem, async. DRAM was used like 40 years ago, and CPUs at that time ran at a max. of 2MHz

author: hamster_nz
author_rank: Super Contributor
timestamp: March 20, 2019, 09:33:38 pm
content: Quote from: soFPG on March 20, 2019, 08:41:37 pmI did some more research, and bothered to look at a data sheet for MT48LC4M16. I once wrote a SDRAM controller for this part, but that was a long time ago.To work in spec you have to refresh all 4096 rows every 64ms, so you need to issue an auto refresh once every 15.625us. Each refresh command takes two cycles.Looking at Figure 40 & 46, a single word read, with auto pre-charge takes 6 clock cycles, and a single write with auto pre-charge takes 7.If running on a fixed schedule of a read or write memory access followed by a refresh you will get one memory operation+autorefresh every 9 cycles. To be in spec, those 9 cycles need to happen every 16us, giving a minimum feasible clock rate of about 0.562MHz, and a memory bandwidth of 64k single-words transactions per second.Of course you can use bigger burst transfers to increase your bandwidth, but that will also require an increase the minimum clock speed.You could also clock slower if you issued multiple refresh cycles back to back, with the minimum being 8092 clocks every 64ms. (about 8us/0.125MHz) but that leaves no cycles to actually access the memory!

author: asmi
author_rank: Super Contributor
timestamp: March 21, 2019, 02:45:00 am
content: Quote from: soFPG on March 20, 2019, 08:41:37 pmAsync DRAM is long dead as far as I know.Also - here is what Micron has to say on DLL disabled mode for their DDR3 chips (you have to disable DLL to be able to drive these chips at low frequencies):QuoteTranslation for inexperienced datasheet readers: "DO NOT USE THIS MODE, we don't know - nor do we really care - how will it behave in this mode, hence we can't guarantee anything.".As for this solution - I personally think it's insane. Why would you even need a lot of RAM with 8 bitters? I struggle to come up with any more-or-less realistic scenario when it could be useful. The two advantages 8 bitters have over 32bit ARMs - simplicity and low power - both disappear in this case. So why not pick some ARM Cortex MCU with built-in SDRAM controller instead?

author: soFPG
author_rank: Frequent Contributor
timestamp: March 21, 2019, 06:31:20 am
content: QuoteI don't use that one. As you can see in my schematic. Sorry that I've changed my way in the middle of the post, which has apparently led to confusion.QuoteI may say you didn't read the complete thread. I am using async DRAM (KM44C256B).QuoteI won't use it on the same µC. This EFM8 is just controlling the DRAM, refreshing it, reading & writing the data from / to the RAM it is getting via SPI from another 8-bit controller. It should basically behave like SPI SRAM to another controller.QuoteI do not know why you bring DDR3 into play now.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: March 21, 2019, 05:51:35 pm
content: QuoteWow. Are those chips still available? I am surprised those were not made obsolete decades ago.

author: soFPG
author_rank: Frequent Contributor
timestamp: March 21, 2019, 07:25:09 pm
content: QuoteI don't think they are still in production, but you can get those from old hardware. I just found an old graphics card (OTI067 from Oak Tech) in my cellar. It has 4 of these DRAM chips soldered onto the PCB. Two are in DIP and the other two are in SOJ-Package.

author: blacksheeplogic
author_rank: Frequent Contributor
timestamp: March 21, 2019, 08:25:04 pm
content: Quote from: Siwastaja on March 20, 2019, 08:25:24 amI worked on a HPC case where the application could spend many seconds not going back out to main memory (they had optimized for the cache size). Error Correction did flag the occasional corruption of a bit due to an interesting bug in refreshing. I don't think the contents of memory is an area you want to be introducing risk, it took a lot of effort with a significant cost associated to figure this problem out not to mention the problems addressing the client confidence these type of issues cause.

author: asmi
author_rank: Super Contributor
timestamp: March 21, 2019, 08:26:13 pm
content: Quote from: soFPG on March 21, 2019, 06:31:20 amThe title says DDR SDRAM, not sure what does async DRAM hava to do with this.Quote from: soFPG on March 21, 2019, 06:31:20 amAre there any EFM8's with enough IO pins for that? Normally I'd say this is a job for FPGA.Still I'm at loss as to why would you need a lot of super-slow RAM. Can you give some details on the intended application?Quote from: soFPG on March 21, 2019, 06:31:20 amBelieve or not, DDR3 is a type of DDR SDRAM.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: March 22, 2019, 02:14:21 pm
content: Don't forget there are some quite large SPI SRAMs available cheaply :https://lcsc.com/product-detail/RAM_Lyontek-Inc-LY68L6400SLIT_C261881.htmlhttps://lcsc.com/product-detail/RAM_VTI7064MSME_C139966.html

author: colorado.rob
author_rank: Frequent Contributor
timestamp: March 22, 2019, 03:19:38 pm
content: After reading this thread, this has nothing to do with finding the most efficient solution. No one looking at a solution involving reclaiming obsolete chips from old video cards cares about that. I suspect that OP is building a Rube Goldberg electronic device for his own amusement & edification. Or maybe he's just trolling this forum.

author: Scrts
author_rank: Frequent Contributor
timestamp: March 22, 2019, 05:01:44 pm
content: There are also PSRAMs, which are easy to interface to small micros as well.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 22, 2019, 07:59:01 pm
content: Quote from: soFPG on March 16, 2019, 06:40:26 pmSee above links for SO8 packaged QuadSPI SDRAM (PSRAM) LY68L6400SLIT VTI7064 & alsohttps://www.electrodragon.com/product/2pcs-ipus-ips6404-iot-ram/That PSRAM still has refresh rules, but has a much lower pin count, and has hidden refresh that can make the MCU task simpler.You can connect 2, or 4 of these, depending on if you need 8 or 16b interfaces.

author: soFPG
author_rank: Frequent Contributor
timestamp: March 22, 2019, 09:52:19 pm
content: QuoteIt's quite common that the topic shifts into different directions as different opinions come up on the way.QuoteWell, I successfully made a schematic with one. It has 28 GPIOs, which apparently is enough.QuoteBelieve me or not, to interface DDR3 is, as you may already know, in a completely different ballpark compared to SDR-SDRAM.QuoteI always looked at mousers parametric search and it never came up with such cheap SRAMQuoteI sure do, I don't see what is wrong with doing things which are fun?QuoteThanks, as I already mentioned, I only used mouser parametric search and it never came up with such RAM (or I didn't look closely enough).Honestly, I am just really excited to use almost 30 year old hardware and try to get it back to life.

author: Axk
author_rank: Regular Contributor
timestamp: March 22, 2019, 11:35:49 pm
content: Are these SPI SRAM chips cheaper than parallel ones because they are slow?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 22, 2019, 11:41:55 pm
content: Quote from: Axk on March 22, 2019, 11:35:49 pmNot entirely, the other saving, is they are not static SRAM memories, but are DRAMS, with refresh (in some cases 'hidden') and that imposes rules on their use.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 22, 2019, 11:44:35 pm
content: Quote from: soFPG on March 22, 2019, 09:52:19 pmMouser do not stock all partsThey do have Static 4MBit SRAMS now, in SO8, which is a boost in the previously std speeds of just 20MHz.SRAM 4Mb 512Kx8 45MHz Serial SRAM ITA single PCB layout could accept either these SRAMs, or the PSRAMs listed above.

author: legacy
author_rank: Super Contributor
timestamp: March 23, 2019, 12:27:15 pm
content: Quote from: Scrts on March 22, 2019, 05:01:44 pmwhat is PSRAM? and can you give me an example?thanks

author: asmi
author_rank: Super Contributor
timestamp: March 23, 2019, 01:34:51 pm
content: Quote from: legacy on March 23, 2019, 12:27:15 pmPseudo-Static RAM. It's DRAM with integrated controller, so to outside world it appears as SRAM.Example

author: legacy
author_rank: Super Contributor
timestamp: March 23, 2019, 01:56:31 pm
content: wow, that's really comfortableis there any chip not in BGA package?

author: asmi
author_rank: Super Contributor
timestamp: March 23, 2019, 02:25:49 pm
content: Quote from: legacy on March 23, 2019, 01:56:31 pmYepAlthough those in BGA packages have pitch of 0.75 mm, so they don't require any advanced PCB technology and can be easily broken out, for example, on JLCPCB's 4 layer boards. BGAs are also more compact and cheaper. There is no need to be afraid of BGAs anymore with 4 layer board prices at $30 for 10 boards. The components you place on them will probably cost more than boards themselves.

author: fchk
author_rank: Frequent Contributor
timestamp: March 23, 2019, 02:53:16 pm
content: Quote from: soFPG on March 22, 2019, 09:52:19 pmSeem reasonable to me.If you should choose to make something real usefull, take that:https://www.microchip.com/wwwproducts/en/PIC32MZ1064DAG176640k SRAM within the processor32MB DDR2-DRAM within the package0.5mm TQFP, can be soldered by hand with little practiceAnd plenty of computing power for 13$.fchk

author: Scrts
author_rank: Frequent Contributor
timestamp: March 26, 2019, 01:22:04 pm
content: Quote from: legacy on March 23, 2019, 01:56:31 pmDigikey -> Search: "PSRAM"https://www.digikey.ca/product-detail/en/issi-integrated-silicon-solution-inc/IS66WV51216EBLL-55TLI/706-1427-5-ND/5320130