USB Device for reading some data from FPGA - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 07, 2025, 08:24:52 pm
content: Hi,I want to read some ADC samples form an Artix 7 FPGA @ USB2.0 Speeds, I want your input advise on Selecting a Part, I have ch32v307 part in my mind, any recommendation or advise?

author: Aiy
author_rank: Regular Contributor
timestamp: June 07, 2025, 08:33:31 pm
content: Hi,What kind of throughput are you looking to get?Even with a dedicated USB IC, it has some limitations in terms of throughput (one differential pair, 480Mbit)In my experience, there is some variability between vendors, like: FTDI, Infineon FX2LP, UTMI/ULPI..I have been excited about a combination like these two hdl libraries put together:https://jorisvr.nl/article/usb-serialhttps://github.com/timvideos/HDMI2USB-numato-opsis-sample-code/tree/master/comms/ulpi/vr5-ulpi2utmiTo achieve a byte-interface with standard (windows) drivers.Best regards,

author: ataradov
author_rank: Super Contributor
timestamp: June 07, 2025, 09:01:59 pm
content: FX2LP is a decent option, although starting to get dated. All the new stuff they release is in really hard to use packages.I would also look at CH569. It has USB3, but you can just use USB2 part. It also has fully handshaked fast parallel bus specifically made for interaction with FPGAs.How do you plan on getting the data into ch32v307?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 07, 2025, 09:39:05 pm
content: QuoteI'm thinking of Using the FMC Bus.QuoteI like this part too, But it's pricier than ch32v307 and I do not need USB3 speed, at most I need 60Mbs, But maybe the experience could come handy in next project.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 08, 2025, 08:45:41 am
content: Do you suggest any repo about FMC Slave in an FPGA?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 09, 2025, 08:55:52 am
content: I have found something unusual, the FMC FSMC_NADV which is for Latching Data/Address is the same pin as the USB High Speed pin, so I think I should choose something else, do you have any Idea what I can do that would be DMA compatible and can sustain at least 60Mbps?

author: hgl10
author_rank: Contributor
timestamp: June 09, 2025, 09:31:26 am
content: CH32V305? it's smaller and cheaper. use spi? the solution will be much simpler. the spi goes up to 72MHz. I have used CH32V305GBU6 as a USB HS to SPI bridge. I have tested up to 32Mbps (1MHz 32bit adc data continuous upload) and it works very good. i think it can go up higher to 64Mbps but i have not tested.

author: hgl10
author_rank: Contributor
timestamp: June 09, 2025, 09:51:25 am
content: wch just announced CH32H417 (Dual core 400MHz/144MHz and USB 3.0 PHY). may be the chip will be out in a few weeks? It seems like a huge upgrade compared with CH569. It is better documented and i think it will be cheaper.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 09, 2025, 09:59:22 am
content: QuoteThe project dead time is very short, So I should probably stick to CH32V307, Maybe 16Bit GPIO, along side the external clock Timer Triggered DMA would be the answer. But I'm open to options that have done before.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 09, 2025, 10:01:43 am
content: QuoteCan you test it @64Mbps. also CH32V305 is similar to CH32V307, is it possible for you to share your MCU code?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 09, 2025, 10:37:41 am
content: I have downloaed the new Datasheet from the chips, There is a new Remap function for the FSMC_NADV pin, but it saysQuoteMy chip Lot No is 31101FC20 so I think the chips are older and do not support it

author: langwadt
author_rank: Super Contributor
timestamp: June 09, 2025, 11:52:56 am
content: ft2232h and something like this:https://github.com/ultraembedded/core_ftdi_bridgeone 8bit@60MHz "fifo" on one port and jtag on the otherschematic something like this,https://numato.com/help/wp-content/uploads/2023/07/mimas-a7-mini-board_V5.0_Sch.pdf

author: hgl10
author_rank: Contributor
timestamp: June 09, 2025, 03:06:50 pm
content: Quote from: ali_asadzadeh on June 09, 2025, 10:01:43 amNow I am too busy with another project, I will test 64Mbps when I have time. It's a internal project for my company, I dont think I can share the code. Sorry.There is another possible solution. Use two spi. It will double the bandwidth (CH32V30x has two DMA). It will be useful if your data has two channels, for example: two ADC streaming.I must say I really like the CH32V305GBU6. For a general purpose MCU with HS USB PHY, it is cheap and super tiny. The SDK code is not ideal but it has a lot of examples and it works, and the WCH forum is very responsive (I am a chinese, maybe it's more easy for me to ask questions on the forum).

author: hgl10
author_rank: Contributor
timestamp: June 09, 2025, 03:29:23 pm
content: I have also tried FX2LP many days ago. The chip is indeed old but it works great. The code I tested is based on ataradov's usb sniffer (https://github.com/ataradov/usb-sniffer). ataradov's code quality is really awesome. I remembered I got more than 300Mbps with libusb on windows (maybe need more ram buffer on the FPGA side for higher throughput).

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 09, 2025, 03:53:43 pm
content: Quote from: langwadt on June 09, 2025, 11:52:56 amYes, I wonder why nobody else mentioned a FTDI part yet. This sounded like an obvious solution. Use a FT232H (only one channel) if you don't need the extra JTAG, it's cheaper.And you have a well working driver on Windows, whereas with another solution, you'll usually have to fiddle, which is ok if this is just a personal or in-house project, more of an issue if this is gonna be a product.And you'll have to write firmware for the MCU if it's MCU-based.Cost-wise, a CH32V317 and a FT232H will be approximately the same, but depends on where you buy them of course. LCSC tends to have elevated prices for FTDI parts.OTOH, if having a MCU can be useful for other tasks, a CH32V317 will work just fine, using the FSMC peripheral or any other that fits your requirements. I like this chip.Note that the CH32V305 is cheaper but IIRC, it doesn't have a FSMC peripheral (TBC).WCH have dedicated USB interface chips as well, but the only HS one is the CH378, which seems to be only made to implement USB mass storage devices.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 09, 2025, 05:50:36 pm
content: Guys thanks for the feedback, I think I would stick to CH32V307 or CH32V305 parts, since I have chips in my hands and I have the CH32V307 devkit too, so I will probably go with CH32V307, I have tested CH32V307 SPI and it speed reaches 72Mhz regarding the older version chips too.I have tried to use the FullDuplex_HardNSS Example In HOST mode and I probed the pins with scope, I can see the clock and Data to reach 72MHz, But the SS pin does nothing, is the example code correct?Here is the codeCode:void SPI_FullDuplex_Init(void){GPIO_InitTypeDef GPIO_InitStructure = {0};SPI_InitTypeDef SPI_InitStructure = {0};RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_SPI1, ENABLE);GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;GPIO_Init(GPIOA, &GPIO_InitStructure);GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;GPIO_Init(GPIOA, &GPIO_InitStructure);GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;GPIO_Init(GPIOA, &GPIO_InitStructure);GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;GPIO_Init(GPIOA, &GPIO_InitStructure);SPI_SSOutputCmd(SPI1, ENABLE);SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;SPI_InitStructure.SPI_Mode = SPI_Mode_Master;SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_LSB;SPI_InitStructure.SPI_CRCPolynomial = 7;SPI_Init(SPI1, &SPI_InitStructure);SPI_Cmd(SPI1, ENABLE);}int main(void){SystemCoreClockUpdate();Delay_Init();USART_Printf_Init(460800);SPI_FullDuplex_Init();while(1){if(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) != RESET){SPI_I2S_SendData(SPI1, TxData);}if(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) != RESET){RxData = SPI_I2S_ReceiveData(SPI1);}}Do you know what's going on wrong about the SS pin, Also I have tested the DMA and it works, But the SS pin does nothing either.

author: hgl10
author_rank: Contributor
timestamp: June 10, 2025, 01:11:11 am
content: Quote from: ali_asadzadeh on June 09, 2025, 05:50:36 pmOld bug. SS pin cannot auto high and low with the spi frame. I think STM32F103 has the same bug? so SS pin in hardware mode is almost useless.use gpio for nSS in software mode. use Timer to generate pwm as nSS and trigger DMA (SPI TX) at the same time. It's easy and precise.And if you want high throughput, remember to use DMA.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 10, 2025, 01:24:06 am
content: I meant CH32V307 instead of CH32V317 of course (had the latter in mind as I checked it out recently, it's basically the same but with a 100M Ethernet PHY).I suggest looking at the FSMC interface as I mentioned earlier, rather than SPI. It'll allow much faster transfer (parallel), should be trivial to implement in FPGA too. Unless you're limited in the number of available pins.

author: hgl10
author_rank: Contributor
timestamp: June 10, 2025, 03:35:44 am
content: Quote from: SiliconWizard on June 09, 2025, 03:53:43 pmWCH have CH347. It is dedicated USB HS bridge chip (USB HS to SPI/JTAG/I2C/UART etc). Openfpgaloader supports it (https://trabucayre.github.io/openFPGALoader/compatibility/cable.html) for FPGA download using JTAG.wuxx has a repo for it: USB-HS-Bridge (https://github.com/wuxx/USB-HS-Bridge). they sell great quality PCB boards on taobao.

author: laugensalm
author_rank: Regular Contributor
timestamp: June 10, 2025, 08:11:39 am
content: Just on a sidenote: The FX2 family was announced end of life around 09/2024, if I recall right. This was unfortunate, and the migration to FX3 a real PITA, unless you skip the ThreadX overhead. FTDI has proven to maintain some more continuity the last 20 years. There is also firmware for some of the CH32 that can emulate a FTDI, but I haven't tested the FIFO throughput.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 10, 2025, 08:23:25 am
content: QuoteThanks for the input, I have used it with dma like thisCode:SPI_I2S_DMACmd( SPI1, SPI_I2S_DMAReq_Tx, ENABLE );SPI_I2S_DMACmd( SPI1, SPI_I2S_DMAReq_Rx, ENABLE );And it works, But the SS pin problem remains, could you share the Timer to generate pwm as nSS and trigger DMA (SPI TX) at the same time code?QuoteAs mention earlier, the FSMC have pin conflict with USBH pins.

author: hgl10
author_rank: Contributor
timestamp: June 10, 2025, 09:40:51 am
content: Quote from: ali_asadzadeh on June 10, 2025, 08:23:25 am1. I think ch32v307 should work as a spi slave, and FPGA as the master.2. PWM as nSS is simple. just use any timer pwm output as nSS, change the duty to match the spi frame. you may need logic analyzer to do it.3. nSS is unnecessary. you may need an start indicator or sync method to avoid mcu start receive SPI in middle of a SPI frame, but I dont think nSS is necessary. just ignore it (software mode) or leave it to gnd.4. timer trigger DMA is unnecessary here if you use spi slave mode. Single "SPI_I2S_DMACmd( SPI1, SPI_I2S_DMAReq_Rx, ENABLE );" is enough.

author: ataradov
author_rank: Super Contributor
timestamp: June 10, 2025, 02:09:55 pm
content: Quote from: laugensalm on June 10, 2025, 08:11:39 amThere are at least 2 compatible re-implementations that have been consistently available for a number of years. There is no way I'm migrating to FX3 of any of their products when WCH parts exist.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 10, 2025, 02:35:56 pm
content: Quote from: ali_asadzadeh on June 09, 2025, 08:55:52 amFrom what I read in the datasheet, when using USB HS, this function can be routed to another pin (PD2).And FSMC_NADV is for latching adresses from what I can tell, but I think you can use FMSC without even an address bus if you just want to implement a parallel bus for FIFO-like access, so I don't think FSMC_NADV is even required for this.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 10, 2025, 02:41:11 pm
content: Quote from: ataradov on June 10, 2025, 02:09:55 pmWCH MCUs are great replacements and with way better performance than the 48 MHz 8051 the FX2 has, and no need for 8-bit compilers... (eek)Regarding USB SS, the CH569 looks good but I don't like a lot the fact that the USB SS controller seems undocumented and WCH only provides a binary blob (library) to access it, no source code, no register documented... Apparently, ditto for its integrated SerDes.The FX3 is for USB SS, it would make no sense to use it if you only need USB HS. It's pretty expensive.WCH are about to release a new MCU with USB SS (CH32H417?), looks pretty cool. I hope it'll come with more documentation than the CH569 for the USB part.

author: ataradov
author_rank: Super Contributor
timestamp: June 10, 2025, 03:00:49 pm
content: WCH documentation is their weakest point, for sure. It would be nice to get away from 8051, but for now FX2 is the most robust and well known generic device. FTDI ICs are close, but they don't let you configure descriptors however you like, which may be limiting.SS is pretty hard to use anyway. I'm waiting for ICs with internal switches (which are not Infenion). I mostly like CH569 for the real FPGA interface. No need to parallel SPI ports and abuse memory interfaces.

author: hgl10
author_rank: Contributor
timestamp: June 11, 2025, 09:45:55 am
content: Quote from: ali_asadzadeh on June 09, 2025, 10:01:43 amI've tested it @64Mbps (16bit SPI works at 72MHz send @ 4MHz interval). it seems OK. I streamed the data through USB for 20 seconds without any error.I've only use two wries: SCK and MOSI. ch32v305 as the slave and FPGA as the master. make sure CH32V305 ready first.in case libusb may not get data fast enough, use large ring buffer and dma load for USB. Go check "CH32V307EVT\EVT\EXAM\USB\USBHS\DEVICE\CH372Device" example code.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 11, 2025, 10:57:02 am
content: QuoteThanks for the input, it would be very helpful if you could show some code snippets, also I'm interested in your other answer regarding using another timer PWM as DMA trigger and nss pin signal, if you could show some code snippet for that it would help too.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 11, 2025, 11:01:57 am
content: QuoteDo you have any code snippet for suing CH569, it's an interesting part, or do you suggest any repo on GitHub?

author: hgl10
author_rank: Contributor
timestamp: June 11, 2025, 02:20:35 pm
content: Quote from: ali_asadzadeh on June 11, 2025, 10:57:02 amOK. I'll make a small SPI master example with timer triggered DMA and PWM as nSS in the coming days when I have the time. But you actually dont need any of this when using spi slave. They are useful when working as spi master.USB side, I think you should adapt from WCH's example (CH372Device), it'll be more easy for you to get start. It already has ring buffer for large data streaming and it uses DEF_UEP_DMA_LOAD. Default DEF_Ring_Buffer_Max_Blks is 16, you should make it as large as possible.Code:/* Ringbuffer define */// make DEF_Ring_Buffer_Max_Blks as large as possible#define DEF_Ring_Buffer_Max_Blks 56#define DEF_RING_BUFFER_SIZE (DEF_Ring_Buffer_Max_Blks*DEF_USBD_HS_PACK_SIZE)// the next line is in the while loop in main.c:ret = USBHS_Endp_DataUp(DEF_UEP1, &Data_Buffer[(RingBuffer_Comm.DealPtr) * DEF_USBD_HS_PACK_SIZE], RingBuffer_Comm.PackLen[RingBuffer_Comm.DealPtr], DEF_UEP_DMA_LOAD);I know a CH569 project on github called hydra (https://github.com/hydrausb3), it's rebuild from ground up without using WCH's SDK. They do seem elegant, but I haven't used it in real project, you may need to evaluate it yourself.CH32 series has much better documentation than CH569. Though CH32H417 is not out yet, it has already give all registers' definition for USBSS in the CH32H417RM.pdf (but no register level doc for UHSIF yet). And CH569 has no USBSS register level definition after so many years. So I have high hopes for CH32H417.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 11, 2025, 02:38:02 pm
content: Yes, as I mentioned, some peripherals are just left undocumented and supported only via binary blobs by WCH. I'm certain this isn't just that they forgot about it or didn't have time. It's intentional. The most likely reason is that these are third-party IPs and they have no legal right to provide any documentation about them. That's very common, unfortunately, for some classes of IPs such as USB and radio stuff.I ran into something similar just with USB HS for DWC2 controllers. Synopsys controls documentation in a very, very strict manner. I'm convinced this is the same for the USB SS controller in the CH569.I don't know if they have used the same USB SS IP for the CH32H417. If they documented it, I suspect not. But we'll see.

author: ataradov
author_rank: Super Contributor
timestamp: June 11, 2025, 02:49:21 pm
content: Quote from: SiliconWizard on June 11, 2025, 02:38:02 pmChinese version of the reference manual for this chip is out. USB SS is "documented" as well as everything else - there are tables of registers, but no functional description text of any kind. At least those tables have somewhat detailed text, so it might be possible to figure it out. It is certainly better than nothing.

author: hgl10
author_rank: Contributor
timestamp: June 11, 2025, 03:33:08 pm
content: Quote from: SiliconWizard on June 11, 2025, 02:38:02 pmI think it's unfair to say that to WCH. At least they are really trying to detailed all registers for CH32 series. CH32V30x's usb library is not a blob, they provide all c code in EVT examples. CH32H417's USBSS examples are already out and they are .h and .c files. CH569 is old and I think they maybe never get register level docs. manpower is transfered to newer chips.QuoteCH32H417's RM is not as detailed as CH32V307, it takes time. maybe it's easier to figure it out combined with the EVT example source they provide.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 11, 2025, 04:28:31 pm
content: Did you really read what I wrote?There is nothing unfair about it whatsoever. On the contrary, I explicitely said that whatever is left completely undocumented is likely for IP reasons. Of course, that's just an hypothesis: the root reason may just be that writing documentation for the USB SS controller is too big an endeavor, but the fact they didn't release source code for it either is to me a relatively clear sign.All vendors do it. You won't find any documentation, or very limited documentation for some IPs such as USB 3.0 SS and radio in general in most reference manuals of most vendors. Just the way it is because they are bound by the IP license. I gave the DWC2 IP as another example. Many vendors use it on their MCUs/SoCs, but most give no documentation or very little, because they just can't. You need an NDA with Synopsys.Interestingly, the only vendor I know so far that documents the DWC2 controller at least to a significant extent is ST. I don't know if they got express authorization from Synopsys to do this, if they had to pay more expensive licenses for that, or whatnot.This is also a very well known issue with radio IPs which are often undocumented as well and usable only via binary blobs.Yes, WCH provide documentation and source code for their USB controllers (FS & HS), but I specifically mentioned the one in the CH569 which is USB 3.0 SS, undocumented and no source code, just a binary library. Ditto for their SerDes controller. And from experience with most other vendors, I think the most likely cause is that they are just not allowed to because this isn't a in-house designed IP (or if it is, they want to protect it for the time being). That's all there is to what I said.Now since they have at least given register definitions for the USB SS controller in their future CH32H417, I questioned whether the reason is that it may be a different IP than for the CH569. Maybe it is, maybe not. But if they provide only register definitions with no details on operation and no source code (again: we'll see), good luck. Yes, someone has reverse-engineered the USB SS controller in the CH569 (as someone mentioned earlier), but that's a pretty big project.

author: KE5FX
author_rank: Super Contributor
timestamp: June 11, 2025, 05:09:35 pm
content: Quote from: ataradov on June 10, 2025, 02:09:55 pmWCH doesn't make a form-fit-function compatible replacement for the FX2LP, as far as I know. Is that still the case?Somebody has got to make one. Dropping those parts abruptly was not OK for Infineon to do. Alotof active products still use it.

author: ataradov
author_rank: Super Contributor
timestamp: June 11, 2025, 06:55:11 pm
content: Quote from: KE5FX on June 11, 2025, 05:09:35 pmNot from WCH, no. FX2LP is a weird device, there is no real point in replicating it there are much better things you can do.There are a couple fully compatible clones (not from WCH) and that is enough. It is still used in a lot of things that is enough to sustain that demand for a while.Chinese clones of my USB Sniffer use them and they work just like original with no visible performance degradation.The part number for the clone is CBM9002A.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 11, 2025, 07:07:07 pm
content: Where did you find the RM for the CH32H417?I ran into this repo, which doesn't look like it's official from WCH, so maybe a leak?It only has the datasheet in it, not the RM.There is the SDK (which may be preliminary) and there is a project for USB SS, with apparently source code. So, that's good news compared to the CH569.https://github.com/SoCXin/CH32H417/tree/main/EVT/EXAM/USBSS/DEVICE/CH372DeviceIt oddly has references to the CH372, though, which from what I can tell on WCH website, is a full-speed interface chip.

author: ataradov
author_rank: Super Contributor
timestamp: June 11, 2025, 07:07:59 pm
content: The official Chinese site -https://www.wch.cn/products/CH32H417.htmlThere is an RM and design documentation for the EK with Keil projects for all the peripherals including USB SS.I'm really annoyed that they only put USB-A socket on the EK bypassing all the messy SS muxing. I'd rather see a practical reference design.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 11, 2025, 07:12:18 pm
content: Ah, thanks. Having a look.I think I get what those references to the CH372 chip means: their example project emulates a CH372 with the USB SS controller for the H417. This is something WCH are used to do. In SDKs for their other MCUs, they also often provide USB examples with emulations for their dedicated inferface chips.I'm now curious how much it will cost. Could be a real game-changer.

author: hgl10
author_rank: Contributor
timestamp: June 12, 2025, 01:18:47 am
content: Quote from: SiliconWizard on June 11, 2025, 04:28:31 pmI seem to misinterpret your words. Sorry for the distraction.ch32v series have a good history documenting all their peripherals. we'll see if that holds true for CH32H417.

author: hgl10
author_rank: Contributor
timestamp: June 12, 2025, 09:52:53 am
content: Quote from: ali_asadzadeh on June 11, 2025, 10:57:02 amDMA/SPI has delay, if you use only one timer, you cannot really match nSS and SPI frame for such high SPI speed. I use two chained timers to add latency to nSS. the pic bellow is captured by logic analyzer.The full main.c based on WCH sdk:Code:#include "debug.h"#include "string.h"// SPI DMA test (CPU @ 144MHz)// SPI is driven by timer 2 at 4MHz (4MHz * 16bit = 64Mbps)// SPI: PA5(SCK), PA7(MOSI)// nSS: use PC8 (TIM3_CH3), PWM as NSS// hgl10@20250612#define Size 4000volatile uint16_t TxData = { 0 };volatile uint16_t RxData;void spi_init(void){GPIO_InitTypeDef GPIO_InitStructure={0};SPI_InitTypeDef SPI_InitStructure={0};RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_SPI1, ENABLE );GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_7;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;GPIO_Init( GPIOA, &GPIO_InitStructure );SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;SPI_InitStructure.SPI_Mode = SPI_Mode_Master;SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;SPI_InitStructure.SPI_CRCPolynomial = 7;SPI_Init( SPI1, &SPI_InitStructure );// DO NOT enable SPI_I2S_DMAReq_Tx// SPI_I2S_DMACmd( SPI1, SPI_I2S_DMAReq_Tx, ENABLE );// SPI_I2S_DMACmd( SPI1, SPI_I2S_DMAReq_Rx, ENABLE );SPI_Cmd( SPI1, ENABLE );}void DMA_Tx_Init( DMA_Channel_TypeDef* DMA_CHx, u32 ppadr, u32 memadr, u16 bufsize){DMA_InitTypeDef DMA_InitStructure={0};RCC_AHBPeriphClockCmd( RCC_AHBPeriph_DMA1, ENABLE );DMA_DeInit(DMA_CHx);DMA_InitStructure.DMA_PeripheralBaseAddr = ppadr;DMA_InitStructure.DMA_MemoryBaseAddr = memadr;DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;DMA_InitStructure.DMA_BufferSize = bufsize;DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;DMA_Init( DMA_CHx, &DMA_InitStructure );}// TIM2 trigger TIM3// TIM2 update event trigger DMA to send SPI// TIM3 is triggered by TIM2 TIM_TRGOSource_OC1Ref signal.// PC8(TIM3_CH3) work as nCSvoid tim_pwm_init(u16 psc, u16 arr){TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure={0};RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3, ENABLE);// PC8 as TIM3_CH3RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);TIM_TimeBaseInitStructure.TIM_Period = arr-1;TIM_TimeBaseInitStructure.TIM_Prescaler = psc;TIM_TimeBaseInit(TIM2, &TIM_TimeBaseInitStructure);TIM_TimeBaseInit(TIM3, &TIM_TimeBaseInitStructure);// TIM2的TIM_TRGOSource_OC1Ref触发TIM3// 此处不使用UPDATE信号，可以自由控制nCS延迟的时间TIM_OCInitTypeDef TIM_OCInitStructure={0};TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;// 不需要输出，只作为触发信号TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable;TIM_OCInitStructure.TIM_Pulse = 1;TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;TIM_OC1Init(TIM2, &TIM_OCInitStructure);TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Enable);// configure PWM as nSS (PC8: TIM3_CH3):GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);GPIO_InitTypeDef GPIO_InitStructure={0};GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;GPIO_Init(GPIOC, &GPIO_InitStructure);TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;// use TIM_Pulse to change nCS widthTIM_OCInitStructure.TIM_Pulse = 2;TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;TIM_OC3Init(TIM3, &TIM_OCInitStructure);TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Enable);TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_OC1Ref);TIM_SelectInputTrigger(TIM3, TIM_TS_ITR1);TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Reset);}int main(void){SystemCoreClockUpdate();Delay_Init();for (int i = 0; i < Size; i++) {TxData = i;}spi_init();tim_pwm_init(0, 36);// enable TIM2 update DMA requestTIM_DMACmd(TIM2, TIM_DMA_Update, ENABLE);DMA_Tx_Init( DMA1_Channel2, (u32)&SPI1->DATAR, (u32)TxData, Size );DMA_Cmd( DMA1_Channel2, ENABLE );TIM_Cmd(TIM3, ENABLE);TIM_Cmd(TIM2, ENABLE);while(1){}}

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 12, 2025, 11:18:51 am
content: QuoteHuge Thanks for sharing, I hope I see more post from you on the forum.QuoteThanks for the Link, the part seems relay interesting and I already purchased 20 units, I hope someone on the forum would shed some lights up on us.QuoteYour pic lights a bulb in my head, that why not use ch32V307 along a low cost FPGA/CPLD to make a fast enough and low cost Logic analyzer.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 12, 2025, 11:41:39 am
content: QuoteIt's a very interesting part, adding missing futures from the ch32V line up, like QSPI in memory mapped mode to have more flash and a FMC to support SDRAM and LTDC controller, I think it has come to destroy the STM32H line up, I hope they would price it under 2$

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 04, 2025, 09:50:21 am
content: Guys do we have any availability regarding CH32H417, Do we have any price estimates or release date?

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 04, 2025, 03:41:31 pm
content: Quote from: ali_asadzadeh on June 12, 2025, 11:41:39 amWell, the CH32V307 does not support QSPI IIRC, but it does support a memory interface which can be used with external Flash and PSRAM chips. It's not QSPI, so supports only a 8-bit and 16-bit data bus. That's less convenient, but Flash and PSRAM chips in 8- or 16-bit do exist and as a bonus, you'll get higher throughput.I actually have in my pile of projects the idea of making a board with a CH32V307 + 8- or 16-bit PSRAM (often called "hyperram" I think) and an Ethernet gigabit PHY. Sounds neat.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 05, 2025, 07:00:08 pm
content: QuoteMake a thread for that, but I think CH32H417 is near, since the mounriver has been updated for the support for the chip recently.

author: berke
author_rank: Frequent Contributor
timestamp: October 09, 2025, 12:41:39 pm
content: Quote from: langwadt on June 09, 2025, 11:52:56 amNote that the FTDI chip outputs a continuous 60 MHz clock but you get to emit data only when the chip requests it from you by lowering /TXE. It does that depending on the timing of the USB bulk in packets. If you're capturing real-time data you will need large buffers, larger if your host is slow or loaded or if there are other things on the same USB bus creating traffic.With 16 kB of buffers I get reliable acquisition at 15 MB/s (120 Mb/s) if I put the FT2232H on a dedicated port with no other devices.