Adjust data relative to clock - Page 1
Forum section: electronics / projects

author: ataradov
author_rank: Super Contributor
timestamp: January 15, 2020, 11:13:08 pm
content: I'm looking for ideas for a vague project, so things are not well defined.Basically I have a parallel bus that has 1-8 data signals and one clock signal. The frequency of the clock signal is 10-100 MHz. The data is going to be received by the FPGA.The problem is that due to routing and wiring, the signals may be slightly misaligned, between themselves and the clock.The goal is to have a way to slightly shift the clock by a few ns in a few steps. For now let's assume that the signals are aligned, but the clock is shifted, since shifting the clock may provide a way to find a common sampling point between the signals.Additional issue is that it may be a DDR clock, so the data is sampled on both the rising and falling edges. So whatever method is used, it must preserve the duty cycle.But one thing that may help is that clock is constantly running, so the actual delay may be a few ms + a few ns. It will make no difference to the end result.And the accuracy of the delay and its variability from device to device or even from power cycle to power cycle does not matter. The correct delay will be calibrated every time to get reliable reception of a known test pattern.I know some FPGAs have capabilities to shift the clock, but for now I would like to plan on using the external circuitry so that my choice of FPGAs is not limited by this factor.I have some ideas of forcing a chain of inverts inside the FPGA, but I have never tried anything like this, so I don't know if this will be close to working.Any ideas for external circuitry are welcome. Complexity and price are factors. So $20 delay lines are out of the question.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 15, 2020, 11:37:21 pm
content: There are digital clock fanning chips with 5 bit resolution for absolute delay or more. Ad9513. Unless that what you meant by $20 delay line.

author: ataradov
author_rank: Super Contributor
timestamp: January 15, 2020, 11:40:35 pm
content: Quote from: unitedatoms on January 15, 2020, 11:37:21 pmYes, that's exactly what I mean. AD9513 is $8.6 in 500 qty.The solution I'm looking for is something in the realm of varicap and buffered RC delay. I'm looking for something under $1, basically no matter how dodgy it may appear, as long as it works.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 15, 2020, 11:50:38 pm
content: For 2 bit resolution there is polyphase filterLooks like just a gate with single input, two complimentary outputs, L C and 4 Schmitt gates can work as digital equivalent.https://wiki.analog.com/university/courses/electronics/comms-lab-polyphase-filter

author: james_s
author_rank: Super Contributor
timestamp: January 16, 2020, 12:41:32 am
content: Seems like doing this sort of thing in an fpga typically involves using a faster internal clock in the FPGA, then you can use that to drive a counter or flip flop that samples the incoming clock and applies a slight delay.

author: ataradov
author_rank: Super Contributor
timestamp: January 16, 2020, 12:45:47 am
content: Nobody over-samples 100 MHz clock. That is not going to work reliably at all. Or you will need a way more expensive FPGA, and even then it is still questionable.

author: David Hess
author_rank: Super Contributor
timestamp: January 19, 2020, 07:59:29 pm
content: Quote from: ataradov on January 15, 2020, 11:40:35 pmThat can work but to get negative delay, the delay has to start at 1 or a whole number of cycles.A common way is to phase lock an oscillator to the clock signal and then adjust the phase by adding an offset to the output of the phase comparator.

author: ataradov
author_rank: Super Contributor
timestamp: January 19, 2020, 08:10:55 pm
content: Quote from: David Hess on January 19, 2020, 07:59:29 pmNegative delay is not a problem. There is no correspondence of the specific clock cycle to the data. The clock is continuous and if there is no data to be sent, data lines are just stuffed with dummy data. So to get negative delay we just need to overflow into the next cycle.Quote from: David Hess on January 19, 2020, 07:59:29 pmOne thing that gives me pause with generating secondary clocks is that data is sampled on both edges. I do expect duty cycle of the original clock to be close to 50%, but who knows, especially at high frequency. Secondary oscillator will definitely "fix" the duty cycle.

author: Yansi
author_rank: Super Contributor
timestamp: January 19, 2020, 09:03:19 pm
content: Quote from: ataradov on January 16, 2020, 12:45:47 ammind your language... Here they've been oversampling even 420Mbps serial streams x4.https://www.xilinx.com/support/documentation/application_notes/xapp224.pdfYet it was I guess working pretty well.Note: Varactor controller RC delay is crap, forget it. Way too much jitter. Better solution would be to start from scratch and fix the problem (clock misalignment) in the first place, instead of trying to come around it.

author: Benta
author_rank: Super Contributor
timestamp: January 19, 2020, 10:23:59 pm
content: Check these out:https://www.onsemi.com/products/clock-timing/clock-data-distribution/skew-management

author: David Hess
author_rank: Super Contributor
timestamp: January 20, 2020, 04:53:15 am
content: Quote from: ataradov on January 19, 2020, 08:10:55 pmIt is not difficult to add another analog control loop which measures the input duty cycle and adjusts the output duty cycle to match. Usually this is done to make a precision variable duty cycle.

author: OwO
author_rank: Super Contributor
timestamp: January 20, 2020, 06:12:49 am
content: PCB delay lines + $0.1 RF switches (mxd8641 etc) might do the job. 4 sp4t switches and some PCB traces can implement 16 delay steps. Ignore the frequency ratings in the datasheet; these switches can all operate down to DC for low voltage signals, but check whether 3.3V can pass without getting clamped.

author: langwadt
author_rank: Super Contributor
timestamp: January 20, 2020, 08:40:00 pm
content: Quote from: OwO on January 20, 2020, 06:12:49 amsure but it'll need a very long delay line, because once you add stuff and a clock buffer you are already behind and need atleast half a cycle delay to catch up (assuming 50/50 duty)

author: ogden
author_rank: Super Contributor
timestamp: January 20, 2020, 08:52:54 pm
content: Quote from: ataradov on January 15, 2020, 11:13:08 pmWhole idea of doing clock skew management outside FPGA is wrong. After all (both) leading FPGA camps offer proven solutions, just copy/paste them.

author: edavid
author_rank: Super Contributor
timestamp: January 20, 2020, 09:04:46 pm
content: Quote from: OwO on January 20, 2020, 06:12:49 amSince it's a digital delay, there's no need to use analog switches. He could use a digital mux or just extra FPGA inputs. A gate chain can be used to get more delay in a smaller space.For high resolution tweaking, use a gate chain, but adjust the supply voltage to vary the delay. (This may also need level shifters.)

author: Yansi
author_rank: Super Contributor
timestamp: January 20, 2020, 09:14:37 pm
content: Quote from: edavid on January 20, 2020, 09:04:46 pmcan be used to get delay and also jitter as a bonus, can't it?

author: ataradov
author_rank: Super Contributor
timestamp: January 20, 2020, 09:16:16 pm
content: At this point I will have to just try a few things and see what works and what does not.

author: ogden
author_rank: Super Contributor
timestamp: January 21, 2020, 03:57:09 am
content: Quote from: ataradov on January 20, 2020, 09:16:16 pmYes indeed, yet you have to do better than "just try". You need to properly characterize your solution in whole temperature and component tolerance ranges - to avoid picking edge solution which may possibly fail when you least expect it.

author: ataradov
author_rank: Super Contributor
timestamp: January 21, 2020, 04:03:45 am
content: Temperature is not as much of a factor, this stuff is going to be operated by humans. I don't care if it fails at -40 C or +85 C. Operators will fail much faster.I also don't care as much for slow drifts. As long as things stay more or less stable for a few minutes to a few hours at a time, I'm fine.As long as I get a few distinct sampling points from different settings, it should work.

author: OwO
author_rank: Super Contributor
timestamp: January 21, 2020, 04:14:49 am
content: I would say analog switches (or better, RF switches) are preferred because they introduce the least jitter as the signal path is passive. The RF switches I mentioned have very low insertion loss at these frequencies, so no clock buffering is needed (assuming the delay lines are not too lossy).Length of delay lines will be the biggest problem, especially at lower frequencies and if you want to roll over into the next cycle. You need around 16cm for 1ns of delay. If this is a 4 layer board you can have very thin 50ohm traces, but also consider using a non-50ohm Z0. The dominant loss contributor of the RF switches at low frequencies is the series resistance (the shunt capacitance is 100-200 femtofarads and can be ignored), so using a high Z0 will also reduce loss. On a 2 layer board (1.0mm thick) I would use 0.2mm traces which are 120ohm.

author: KE5FX
author_rank: Super Contributor
timestamp: January 21, 2020, 04:23:43 am
content: What's wrong with an IDELAY element?

author: ogden
author_rank: Super Contributor
timestamp: January 21, 2020, 04:26:13 am
content: Quote from: ataradov on January 21, 2020, 04:03:45 amSometimes just 30 degrees (10..40oC) is enough to bust overconfident engineers.Quote from: KE5FX on January 21, 2020, 04:23:43 amThere's no excitement of invention

author: ataradov
author_rank: Super Contributor
timestamp: January 21, 2020, 04:28:11 am
content: Quote from: KE5FX on January 21, 2020, 04:23:43 amAbsence of such thing in Lattice LCMXO2, which is currently a target FPGA.

author: ogden
author_rank: Super Contributor
timestamp: January 21, 2020, 04:31:47 am
content: Quote from: ataradov on January 21, 2020, 04:28:11 amOh... Is it so that Lattice do not offer *any* kind of I/O delay management? Seems like they do, (Technical Note TN1131, apr 2007) just LC series is not in the list of said tech note.

author: ataradov
author_rank: Super Contributor
timestamp: January 21, 2020, 04:34:06 am
content: Quote from: ogden on January 21, 2020, 04:31:47 amI have not looked in the details.Again, I know the answer "just use dedicated resources". There is no need to repeat it.I was specifically looking for alternative solutions.

author: ogden
author_rank: Super Contributor
timestamp: January 21, 2020, 04:37:17 am
content: Quote from: ataradov on January 21, 2020, 04:34:06 amLOL. Dont' you think that sometimes reason why you receive answer you already know is... lack of *working* alternative solutions?

author: ataradov
author_rank: Super Contributor
timestamp: January 21, 2020, 04:40:59 am
content: I've got all the answers I needed.

author: BrianHG
author_rank: Super Contributor
timestamp: January 21, 2020, 05:13:24 am
content: Quote from: ataradov on January 15, 2020, 11:13:08 pmSome potential all inside FPGA software only alternate ideas:If you said that the source data clock is coming at 1 frequency, or, it may be within a narrower range like 75 to 100 MHz, then is would be easy for the cheapest FPGA to sample either 8 or 16 sub phases and you may use logic to determine which phases see the correct data pattern and select the optimum center tuned phase which has no errors. This would most likely eat up 2 PLLs.However, expecting the PLL to self tune and lock between 10 and 100MHz isn't possible unless you program a frequency counter and dynamically configure the PLLs to track the source clock. However, if that source clock freely flies all around, you will not keep up.If your FPGA is specifying that external clock's frequency, IE tuning a sampler, or it can receive an input setting a 'band', ie 10-20Mhz, 20-40Mhz, 40-70Mhz, 70-100MHz, this makes setting up the FPGA PLL easier.Doing this right means understanding the FPGA fabric input cells and knowledge of the PLL's capabilities in using multiple output phases and for each input pin, setting 8 fast input register and clocking each on positive and negative cycles of the 4 source PLL phases giving you 8 parallel streams sampled at 8 parallel points along the source clock. You will need to run 8 copies of you test pattern recognition software to select which stream bits aren't corrupt.With this, you will most likely loose the duty cycle of you source clock input, but, you get an auto select-able different clock phase for each input bit.The other method, this one samples all data bits in parallel, is just dynamically tune the FPGAs PLL output phase relative to the source clock and determine the best latching time. With this method, and 2 plls, you may lock one on the rising edge and the other on the falling edge giving you a programmable duty cycle locking points. This also means only having 1 or 2 sample streams to analyze instead of 8 in my first example which would allow single individual bit sampling.

author: jmelson
author_rank: Super Contributor
timestamp: January 21, 2020, 09:17:57 pm
content: Quote from: ataradov on January 15, 2020, 11:13:08 pmEven Xilinx Spartan 3 had IO functions that can shift the I/O clock on a per-pin basis. I don't know how far you can shift it, but I think a few ns is possible.Just dig into the datasheet for the details.Jon