EEVblog #1081 - Are Bypass Capacitors REALLY needed? - Page 1
Forum section: electronics / general

author: EEVblog
author_rank: Unknown
timestamp: May 04, 2018, 10:25:16 pm
content: Can a product work without ANY bypass capacitors?Dave finds out by "Muntzing" the Gigatron TTL computer.Lots of talk on bypassing, grounding, probing, signal fidelity, ground loops and noise and crosstalk.

author: rs20
author_rank: Super Contributor
timestamp: May 05, 2018, 12:02:23 am
content: Very interesting video, really enjoyed it! However, I have to say that the glitches at 14:38 are being blown out of proportion a bit.I'm sure you're aware that output signals from complex asynchronous circuits (sometime even single ICs) can flip-flop more than once in response to a change to an input due to that input signal branching out and then recombining with various different delays inside the circuit. The classic example being an AND gate and an inverter set up to output A & (!A). Although that circuit is obviously always supposed to output False/0V, it can end up outputting a brief glitch/runt pulse on the rising edge on A because the inverter has a little delay, so it briefly outputs newA & (!oldA). Asynchronous adders (like e.g. 74HC283) are a classic source of this "issue".So with that in mind, I think it's inaccurate to say that any runt pulses you see are "obviously caused by grounding issues". Because even though grounding issues or decoupling can create or worsen this phenomenon, this phenomenon can occur in theoretically perfectly well-grounded and decoupled systems.It's also an omission to make it sound like this phenomenon is a definite sign of a problem that must be fixed. The nasty edge at 16:25 is almost certainly not intentional. However, it's probably not a problem at all because a subsequent part of the circuit will belatched. As long your signal finishes its BS wiggles or "second bites of the cherry"beforea subsequent latch samples the signal, those wiggles are perfectly inconsequential (aside from wasting power and worsening emissions).More specifically, it would be a real shame if a newbie saw runt pulses in their own circuit and then concluded that they should add decoupling caps until the runt pulses go away, when not only might decoupling caps never solve the problem, but the problem isn't even a problem at all!Could be a cool video idea to discuss actually; would have a similar vibe to this video.

author: TK
author_rank: Super Contributor
timestamp: May 05, 2018, 01:46:13 am
content: Alan (W2AEW) related video on decoupling and filtering capacitors:

author: Cerebus
author_rank: Super Contributor
timestamp: May 05, 2018, 02:31:00 am
content: Quote from: wilfred on May 05, 2018, 12:59:54 amAspartof the background to this, I don't think that it's an accident that an old ceramic through hole 100nF, or poly 100nF, neatly and snugly fits across the end of a 0.3" DIP package.Often on things where I've had cause to actually calculate (or select on test) bypass caps, less than 100nF has often been fine but I've gone with 100nF any way as (1) It's safe, (2) It's one less value to add to the BOM - it's a lot cheaper to buy a huge number of 100nF caps relative to a few 22nF, 47nF, 56nF etc. The only time bigger bypass caps than strictly necessary will bite you in the backside is if you manage to hit an impedance sour spot (as in the opposite to a sweet spot) where your frequency of interest is at or above the cap's self resonant frequency.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 05, 2018, 04:29:53 am
content: FYI, this is how you calculate a bypass cap:1. Isolate the IC in question. This avoids discussing the PDN (power distribution network) as a whole.Isolation is provided by a relatively large value inductor, followed by a bulk cap with ESR matched to the inductor.This gives a subnet impedance that peaks at the resonant frequency 1 / (2*pi*sqrt(L*C). The resonant impedance is sqrt(L/C), which is also what the ESR is chosen as. The peak Q is around 1, and so the impedance peak is close to sqrt(L/C) as well.2. Consider the loads on the IC.For CMOS logic, the normal DC load is minuscule. Pullups are generally weak. LEDs are weak to heavy (depending on value). Transmitters driving terminated lines are heavy. Whatever the load current is, consider the effect of all outputs switching on or off at the same time, in whatever worst-case pattern the circuit is capable of. This is a load step transient.3. Consider the shoot-through of the IC.This is normally not a big deal for TTL, CD4000 or 74HC families. The latter may be on the order of 10mA for a few ns. Punchier families, like 74AC, LVC and so on, can draw much more, up to 100mA for a few ns (or less).4. Consider the supply voltage ripple that is allowable.For general purposes, 5% is probably fine. Even 10%. That is, 0.5Vpk out of a 5V supply. If you need stable, low-jitter timing, you may need 1% or less ripple. (You may also need additional isolation -- not just bypass, but a local LC filter to keep supply noise away from a critical part.)5. Put it all together.We can use a charge argument to find how much capacitance is necessary to deal with shoot-through. Even for 74AC, at 5V supply, 1% ripple, the shoot-through is only 100mA * 2ns = 0.2nC. Since Q/V = C, and delta V = 0.05V, only 4nF is required.For load step conditions, we need to calculate the AC impedance of the supply. How much is required? Simple: if the worst-case step change is 20mA, and delta V = 0.05V, then we need |Z| < (50mV / 20mA) = 2.5Ω.Notice that we cannot get to a single capacitor value from here. We have an impedance, but no frequency. The frequency is "all" -- we need a resistance!We can only get a resistance to the IC, by using a regulated DC supply, an inductor with DCR < 2.5Ω, and a bulk capacitor with ESR < 2.5Ω. The inductor value is chosen to be smaller than R^2 * C, so that ESR dominates at higher frequencies.6. What else?Notice this ignores stray inductance.In a real circuit, the characteristic impedance of traces, component bodies, vias, pins, etc. is modest, in the ballpark of 100 ohms. All transmission line structures, no matter how short, have stray inductance, proportional to the length and the characteristic impedance.It's important to note these simple facts about transmission lines -- because this way, you can determine, for any layout, what stray inductances to expect, by using trace width formulas / calculators. It's also important because, if you go out of your way to make a pathologically low impedance -- like a super wide trace -- that you can expect not just somewhat lower inductance from it, butproportionally lower!**But not actually proportional, because of end effects. It's proportional when the length is much longer than the width. A single via dropping into a 5cm wide trace, isn't going to spread out instantly, it's effectively got rings of wider and wider traces around it until they reach full width.When we include these stray inductances in the circuit, we have to include their voltage drops. For the load step condition, the rise time factors in: for a 20mA, 1ns load step, and the same 1% ripple, we need L = delta V * t_r / delta I = (50mV) * (1ns) / (20mA) = 2.5nH maximum. That's just a few mm of trace length -- indeed, just a few mm ofpin length-- it is the loop from GND, through the bypass cap, to VCC, through the chip, back to ground, that contains the relevant total inductance. For such a demanding application, you canonlysolve it this way: use a 74LVC1Gxx surface mount part (or the equivalent TinyLogic), use an 0603 SMT chip cap right beside it, and flood around and beneath the components with ground plane. This probably won't quite achieve 2.5nH total, but it will be as close as you can get.In this way, we canimmediatelyrule out certain possibilities, like 74AC in DIP packages -- the risetime isn't quite as sharp as 74LVC, but the gulp is huge, and you physically cannot achieve a 1% ripple factor at the device, due to packaging alone!7. So what?If you aren't performing this analysis -- at best, you're lazy. At worst, you're irresponsible!There can be no simpler rule of thumb here: any simplification must miss critical information, like stray inductance. The result would be fragile under, not even pathological cases, simply cases where the assumptions (used to make that simplification) are broken.For the regular case of 0.1uF (approx. 50mΩ ESR) caps, yes, they should be placed as close to the IC as possible, that's fine; but the spacing between caps matters. If we space them such that the stray inductance is larger than, say, 50nH, we may have impedance peaks high enough to be problematic (i.e., Q ~ 15, Zpeak ~ 10Ω). This is only a couple inches of trace length!One final note: notice I haven't made any reference to self-resonance here. SRF ismeaningless. The behavior of the circuit depends on the properties of all components involved. What is meaningful, is the properties: ESR and ESL, stray inductance, all that. We could use the SRF to solve for ESL (an 0.1uF with SRF at 10MHz has ~2nH ESL), but we can also just as well assume it by physical properties (length, namely), and get close enough for hand-waving's sake!Tim

author: EEVblog
author_rank: Unknown
timestamp: May 05, 2018, 08:42:51 am
content: Quote from: rs20 on May 05, 2018, 12:02:23 amWell yes, and that's a whole other several hour long video if you wanted to cover every such scenario.It'slikelythat some of the ground stuff I was seeing was caused by the lack of bypassing, and saying "runt pulse" probably wasn't the best term to use here. It was a just a quick look to see if I could anything.

author: EEVblog
author_rank: Unknown
timestamp: May 05, 2018, 08:46:10 am
content: Quote from: T3sl4co1l on May 05, 2018, 04:29:53 amThat's a bit of a stretch.Come on, seriously, even you aren't going to do this for most general designs.

author: EEVblog
author_rank: Unknown
timestamp: May 05, 2018, 08:53:51 am
content: Quote from: wilfred on May 05, 2018, 12:59:54 amIt's the same reason why 10k is the rule of thumb pull-up resistor.a) Nice round valueb) You'll have a ton of them in the junk binc) High enough not to use too much power, and low enough to make it fairly "solid".100n is the standard for similar reasons, but add in that it was one of the highest value ceramic caps back in the day and still cheap and readily available. Generally the higher value bypass cap is, the better, package and connection being equal.So 100nF was the highest value that was cheap and available, and basically still is.Even today you wouldn't use 1uF or 10u ceramics everywhere for bypassing because as they are more expensive, you'd save those for bulk bypassing or cases of big current gulping devices like FPGA cores.QuoteYes, the value doesn't make much difference.

author: SL4P
author_rank: Super Contributor
timestamp: May 05, 2018, 09:04:25 am
content: How about the bypass caps muting the effect of near-fieldinducedtransients - not necessarily sourced from the board under test...?

author: Fungus
author_rank: Super Contributor
timestamp: May 05, 2018, 01:14:50 pm
content: QuoteNot enough oscilloscopes?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 05, 2018, 03:35:20 pm
content: Quote from: EEVblog on May 05, 2018, 08:46:10 amIt only takes a few minutes to inspect a route, towards the end of layout, and determine if more capacitors are needed (or fewer!), and what kinds.Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 05, 2018, 03:39:40 pm
content: Quote from: SL4P on May 05, 2018, 09:04:25 amOr making them worse?All about loop area between ground, trace and load. Nice thing about ground plane is it serves as a shield, even though, geometrically speaking, it is beneath the traces.As far as minimizing loop area, keeping the low impedance connections (i.e., bypass caps) near the load, does generally tend to have this benefit.Tim

author: SL4P
author_rank: Super Contributor
timestamp: May 05, 2018, 04:33:11 pm
content: Good points,

author: bsdphk
author_rank: Regular Contributor
timestamp: May 05, 2018, 04:55:51 pm
content: Is the Gigatron really built with "real" TTL, as in "7400", or is it one of the subsequent more advanced technologies like LS or ALS ?The "one bypass per chip" rule-of-thump came to be because the original TTL chips sufferer "shoot-through" when their output stage changes state.For a brief moment, measured in (fractions of) nanoseconds, both the top and the bottom transistor conduct at the same time, essentially shorting the +5V rail to GND.This was a major part of both the power-consumption, speed-limit and EMI nightmare of the original TTL family chips.Avoiding shoot-through was the major part of the "LS-revolution" which generally does fine with two layers of the PCB acting as bypass capacitor.However, in large, dense and fast designs, bypass caps may still be required, typically near the chips which drive the largest nets/loads.If you want to follow this video up: Put a scope on the supply current of a 7400, 74S00, 74H00, 74(A)LS00 and 74C00 with a MHz-range signal, and watch the difference.

author: tszaboo
author_rank: Super Contributor
timestamp: May 05, 2018, 06:54:57 pm
content: Quote from: bsdphk on May 05, 2018, 04:55:51 pmIt is using 74HCT according to their website.

author: insine
author_rank: Contributor
timestamp: May 05, 2018, 08:57:26 pm
content: Dave, maybe you could do the same with Raspberry Pi?Might be interesting.

author: ataradov
author_rank: Super Contributor
timestamp: May 05, 2018, 09:08:49 pm
content: It was common to see Russian BK-0010 computers without any bypass capacitors, since they were cut by precious metal scrappers. And they absolutely did not work. Some would kind of boot, but will glitch in finny ways. The significant part was probably SDRAM. Those memory chips from the 80s are huge power hogs, and power line becomes just a mess without bypassing.I've also seen modern MCUs fail without sufficient bypassing. Those things fail in a bit less obvious ways, so the method "remove until it fails" is not going to work, or investment in testing will cover any savings on capacitors. So the method "at least one capacitor per power pin" remains valid.

author: MisterDiodes
author_rank: Frequent Contributor
timestamp: May 06, 2018, 04:42:16 pm
content: Dave,Interesting test on the Gigatron, but you don't want to give the impression that bypass aren't needed. They are. Part of why you add bypass caps is to keep the local chips operating correctly, but you're also looking at noise immunity to external EMI coming INTO the board, as well as radiated EMI from the board - acorss all operating temps. We've seen several examples where a board lockup was occurring say when the nearby soldering iron was at idle, clicking on and off...and solving the problem on the PCB in question with more robust and wideband bypassing. Another example would be when you're at EMI testing and realize you can solve a radiated emissions problem with a few more bypass caps at a better location (basically adds no cost to the BOM) vs adding another ferrite or shield. It happens. Just depends on the situation.Generally when testing a CPU system for adequate bypassiing you'd be running some sort of memory randomized stress test that includes lots of random events, memory writes, I/O access, various timing loops, exercise all current loops, etc. And you let that run for a while - days and weeks if required.I'm wondering of the Gigatron would still do the Mandlebrot set to completion without any bypass caps for example. It might, since it's really not super high speed...but it might glitch too.Just running a simple loop on the Gigatron and declaring bypass caps aren't required is maybe not the very best example. But thanks for the videos!RE: Size of bypass caps: Use what is necessary - and you'll find that out during board testing. 100nF per power pin set is common starting value, but especially around FPGA's faster CPU's etc. you see a more wide band approach where you'll need say a 10uF tant, a few 1uF, then maybe some 100nF, 10nF and maybe some 100pF etc. around the chip pad layout. Possibly even a ferrite bead or two. The manufacturer of the chip will usually give some guidelines or look at the reference circuit etc.Faster ECL / I2C / SPI / LVDS / etc bus chips are typically a little more sensitive to proper power bypassing too - in addition to proper signal line termination of course.There is nothing more annoying tracking down some sort of random, intermittent or "once a week" failure or board lockup that was due to some PCB designer trying to be cheap on the bypass caps. Especially when you're in software development on a new device and you can't tell if that last crash glitch was software...or hardware related? Ugggh.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 06, 2018, 06:37:18 pm
content: I had that, back when I breadboarded a Z80:With it running a text scrolling routine, it was fine. Then I added a chiptune program (running from the timer and interrupt), and it might go a week before freezing. Hmm. Then I added a bit-bang LFSR (noise generator), and it might go hours, it might go days, of run time.As you can(?) see, it's well bypassed: one every chip or two, plus extras between rails and along the side. I never saw a change in stability by adding or moving caps.The problem is not supply quality, but signal quality. No ground plane. Well, no good plane. The black binding post is connected to the metal backing plate (I ground off the paint on the back side), but it has a long wire tying it in. Probably anywhere a lot of signals (address and/or data) are changing simultaneously, a lot of displacement current is shoved into the plate (and neighboring traces), and everything hiccups. Double-tapping a clock would be a pretty obvious problem, there may be poorly resolved timing issues as well (Z80s usually go together with classic parallel bus chips very easily, I'd have to review the thing in detail to see what the shortest critical time is). Whatever it was, it was a CPU crash, maybe bad power, maybe invalid opcode, maybe infinite loop (I don't think there was any bus activity, but I don't think I ever scoped it). Could even be signal bounce upsetting the CPU, because ESD diodes. Oh, and that was an NMOS (dynamic) version CPU, so it's not happy with an out-of-whack clock.So as you can see from this example, having a solid ground plane is a far higher priority. I shudder to think of the olden days where TTL was routed on two-layer boards, with power buses (VCC and GND) interleaved in rows beneath the chips, and signals spanning between rows -- what an EMC nightmare! The poor things probably required a shield (a ground plane!) just to operate, let alone meet emissions.But don't take my word for it. We should be so lucky as to work in a field where everything can be calculated, often with handy (and still reasonably accurate) shortcuts. Everything can be measured, often with just a scope. Develop the intuition for yourself, and reinforce it frequently with measurement.Tim

author: David Hess
author_rank: Super Contributor
timestamp: May 06, 2018, 10:23:57 pm
content: Quote from: wilfred on May 05, 2018, 12:59:54 am100nF is larger than required for any reasonably small package and still within the "cheap" part of the capacitance in a single part.QuoteWhen dealing with SSI (small scale integration), 2200pF is often plenty. If you pessimistically figure 4 outputs driving 27pF each simultaneously, then driving 108pF total output capacitance will drop the supply voltage by 5% with a 2200pF of decoupling close to the package.QuoteAt least with SSI and MSI, it is more about how many outputs are driving how much capacitance and what supply voltage bounce is acceptable. Transition time also matters and this is often carefully controlled; with slow transition times like you will find with slower logic, the decoupling requirements are lower. In my example above, I was pessimistic about transition times.The rules are different for large ICs.QuoteWith TTL? Almost certainly. I typically use 0.01uF for SSI packages but if the price difference between 0.1uF and 0.01uF is insignificant, then there may be no reason to use the smaller part. I don't think I have ever designed in anything smaller than 0.01uF because there is no cost savings, however ...One design I saw had odd but standard values of 5% film capacitors used for decoupling. The idea was to use the capacitance and series inductance of the package and layout to notch out specific frequencies for improved EMI compliance. I do not remember if that was part of the original design or changed later.

author: jnissen
author_rank: Regular Contributor
timestamp: May 07, 2018, 09:16:28 pm
content: Dave, I'm surprised you were looking at signals for a power integrity marker. Sure you can see some effect but why not probe the power lines as that will be the real "signal" that will be affected. I tend to use low impedance rigid coax for these measurements directly into 50 ohms at the scope. The 50 ohm load of the scope is going to seem like a rather high impedance probe compared to the supply impedance. Then you use the trigger levels to find the peak offending drop out or ground bounce. Using a high impedance probe for supply investigations can often pick up more noise due to the fact the loop area typically increases. The rigid coax also acts somewhat of a low pass filter with the 50 ohm load and input capacitance. BTW - do this only on scopes that can handle the peak to peak input voltage while in 50 ohm mode.One other note: At 30:50 in the video you mentioned these were "real little things happening in the circuit".I'll assume you know exactly why your getting the knee in the signal. That is the transmission line and the knee in the signal is telling you you probed closer to the source side of the transmission line as opposed to the destination. Surely you recall your t-line fundamentals from school? May be a good video discussion to go over as seeing signal integrity in the real world often drives home the theoretical learning of signal propagation fundamentals.

author: KE5FX
author_rank: Super Contributor
timestamp: May 07, 2018, 10:02:18 pm
content: Quote from: jnissen on May 07, 2018, 09:16:28 pmAbsolutely. Vddisa signal.I ran a few experiments the other day with aslightly more modern CMOS part:Yes, you can get away with less bypassing than the manufacturer recommends. Usually a helluva lot less. But: (1) 'Mad Man' Muntz didn't need to explain himself to the FCC; and (2) do you feel lucky, punk?

author: David Hess
author_rank: Super Contributor
timestamp: May 07, 2018, 10:27:54 pm
content: Quote from: jnissen on May 07, 2018, 09:16:28 pmThere is nothing to prevent using a high impedance probe with a coaxial connection and when done properly, they will return results similar to a low-z probe when making this measurement. This is one of the rare cases where the larger capacitive load of a passive probe does not matter.A larger problem is relying on any ground with a single ended probe because ground bounce is a real problem. Low voltage differential probes are ideal for this application.If you do use a single ended probe of any kind, do an additional measurement with the probe tip and ground connected at the ground point you have selected. The ground bounce and common mode noise may be so great that further measurements without a better probing technique are useless.

author: ignator
author_rank: Regular Contributor
timestamp: May 08, 2018, 04:17:46 am
content: My experience with decoupling capacitors was for compliance to radiated emissions in avionic products. Sitting in a screen room, I always found the need of more capacitors. And it's the wrong place to be adding them in. It was always difficult to get engineers to place them correctly in the layout so that the IC was drawing charge from the bypass capacitor, and not the connected power and ground plane. PCB designers would just scatter them around with no special routing technique (although I've seen schematics where the capacitors are all shown in a array block on a page, and the designer placed them that way on the board).As clock speeds morphed from 6Mhz (start of my career) to 100Mhz (retirement) and beyond, multiple capacitors were needed. A large one for the major charge source, and smaller ones for the high frequency charge movement. If you look at the problem as charge transfer, every time an output driver toggles, and this driver has to charge the board capacitance to the connected gates, and these gates all have input capacitance, and the IC is maybe an octal part, my game plan was to calculate the total load capacitance, and design in a decoupling capacitor of 5-10x that load capacitance. To properly connect the part, the power had to be routed to the decoupling capacitors first, then large low inductance traces to the power pins of the IC. The idea was to make the decoupling capacitor the source for the charge, and not the power planes. And that was always hard to get the PCB designer to do, as they liked to turn on autoroute. If you could effectively keep the RF charge noise from making it to the power supply, compliance to radiated emission limit line could occur.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 08, 2018, 06:34:13 am
content: Quote from: ignator on May 08, 2018, 04:17:46 amBetter to laugh than to cry at such things...QuoteFWIW, not the best plan: power planes are better capacitors than the components are!Indeed, bypassing planes, one needs to be careful that the bypasses themselves don't make things worse. A plane is typically a few nF (obviously, depends on size and thickness) of nearly-ideal capacitance, with a modest Q at most frequencies (>20?), and every connection to it incurs at least a few nH because of via and body length. So, of course -- use the same analysis as ever: check R, L and C and make sure it's dampened!Incidentally, PCB-level bypass becomes impossible above maybe 100MHz, so you shouldn't get overly worried about supply impedance up there. Anything that needs that kind of power bandwidth, must have onboard bypasses. FPGAs and CPUs typically have wide-format SMT chips, or LGAs even (checkerboard pattern connections on the caps -- lots of interdigitation!), built into their packages. The interposer, whether made of fiberglass or ceramic, is much finer pitch than anything we would pay for on the size of a PCB, so can deal with much higher frequencies. This continues onto the chip itself, where the top two metal layers (say) might be a checkerboard pattern, giving maybe a whole nF or more of local bypass.On that note, you can assume such a load has some ESL (pins and routing), then R || C. The R is more or less the DC load resistance (logic gates have a resistive characteristic), and the C is whatever all the junctions and bypasses total (so, it could be many nF, even some uF for VCORE on big CPUs). Don't forget to consider this in your analysis!Tim

author: David Hess
author_rank: Super Contributor
timestamp: May 08, 2018, 11:41:59 am
content: Quote from: T3sl4co1l on May 08, 2018, 06:34:13 amI reserve crying for when purchasing and management replace the parallel capacitors shown in the schematic with a single expensive non-standard value of the same total size.Some schematics have a separate page showing power distribution to the various circuits and packages along with the associated decoupling capacitors.

author: ignator
author_rank: Regular Contributor
timestamp: May 08, 2018, 09:14:06 pm
content: Quote from: T3sl4co1l onTodayat 01:34:13 amYes, I agree about board capacitance being much better then bulk capacitors, but the bulk caps provided the large charge transfer energy, and the board cap provided the high frequency decoupling.We did have a few designs that had resonance problems, where parallel capacitors intrinsic inductance made a tank circuit. Made a real head scratcher when the emission plot got worse when doing the emission corrections.There was a design from the airdata computer that had a clever special board capacitor layed out for each component. The EE called it the "Island of Quiet". This was isolated from the power plane directly under the part, and then stitched in the large charge source capacitors around the edge of this Island. The island was connected to the power plane with only one controlled connection, the intent to create a small inductor. His problem was keeping the processor noise out of the A/D converter. You can lift their pressure transducer a few inches off the bench, and see LSBs counting up, and absolutely no LSB jumping about. This also enabled compliance to radiated HIRF of 200-600V/m over the frequency range (memory 1MHz to 16GHz).

author: EEVblog
author_rank: Unknown
timestamp: May 09, 2018, 12:28:27 am
content: Quote from: ignator on May 08, 2018, 09:14:06 pmI included links in my original post to IBM research on power plane capacitance and adding distributed bypass caps, screen cap was in the video. Very interesting stuff.

author: EEVblog
author_rank: Unknown
timestamp: May 09, 2018, 12:31:37 am
content: Quote from: jnissen on May 07, 2018, 09:16:28 pmOf course, and that's was what I was alluding to. Those reflections are present in the circuit at the probed point, that's actually happening to the signal on the board at that point, it's not the probe causing that.I wasn't going to go down that rabbit hole, the video was already way longer than I wanted it to be.

author: engineer_in_shorts
author_rank: Regular Contributor
timestamp: May 09, 2018, 09:03:13 pm
content: Think about the time period of muntzing and tube TV sets. The only way to construct circuits was hand build circuit point-to-point, there maaaaaay have been PCB. But anyway point-to-point or PCB, the cost saving of removing a part was not just the component but also the construction cost.These days automated SMT is accessible for even very small volume batches of PCB builds, so if you need to put one part (e.g 100nf) there is almost zero cost to 10 more. At least for passives.Is bypass caps even a big part of 1950s tube TV set construction? I suspect there are also other parts that can be removed but without side cutters. For example resistors to soften start-up currents.

author: KE5FX
author_rank: Super Contributor
timestamp: May 09, 2018, 09:55:08 pm
content: Quote from: engineer_in_shorts on May 09, 2018, 09:03:13 pmSure. If you have a ton of gain, maybe as many as four or five consecutive IF stages, you'd better have a ton of decoupling, or your B+ bus will turn into a feedback path.But do you need bypass caps oneveryscreen grid? Wellllll.... no, probably not.It's really the exact same question. Remember, as far as the business world is concerned, engineering is the art of building a bridge that will barely stand up, a TV that works most of the time, a car that will fail 6 days after its warranty expires, or a computer that needs constant babysitting by expensive service personnel in natty blue suits.

author: f4eru
author_rank: Super Contributor
timestamp: May 09, 2018, 10:44:33 pm
content: That was an interesting experiment !A few remarks though :- Dave should have looked at the 5V line with the scope input in AC coupling- Linear Regulators can often get unstable when removing the bypassing, especially modern ones, so you could have a crash not due to signal integrity- some ICs fom that era have internal bypass caps, bonded directly to the side of the die. A ceramic packaged 6502 I openned recently had one.https://psearch.en.murata.com/capacitor/lineup/gma/- modern fast ICs are much much worse from the current hits banging on the supply lines, and from the smaller noise margin of the logic levels.

author: temperance
author_rank: Super Contributor
timestamp: May 09, 2018, 11:28:36 pm
content: Hello,@14:32there is no problem. The bus is being pulled up because nothing is driving the bus and the next value on the bus is clearly a zero. It's less visible if the next value is a one. Nu bypass cap will change that.@31:00:Nothing special here. WHat you see is a transmission line being driven. The flat portion in that signal indicates that the device being driven is changing it's state. It's actually sloping a little down because the driver output resistance is changing while the bus is being driven. Bypass capacitors aren't going to help you. Cooling the board will make this transitions more flat. The "unstable" high signals will improve too when the board is cooled. But they are stable enough to not cause any problems. It's the GND which requires attention because the noise margin is much lower for zero's. And that's also why TTL level IC's use active low chip selects. For CMOS levels it doesn't matter because the noise margin is symmetric.Perhaps you can try an AM radio next to board while removing the capacitors one by one. Maybe you'll be able to hear the difference.Regards

author: free_electron
author_rank: Super Contributor
timestamp: May 14, 2018, 06:41:45 pm
content: Of course you can design without requiring bypass caps.the Cray -1 had nearly no bypass caps. and that thing is enormous. the design used carefully balanced differential signalling that caused no dynamic load on the power rail ( when one pathway went from 0-1 another went from 1 to 0 so the total current consumption was quasi-static) The voltage rails had virtually no ripple as they used rotary converters to make 400Hz AC that was then rectified. There is very little amplitude ripple on a 400hz rectified supply with a constant load.another common mistake these days is 'sprinkling' 100nf caps. 100nf worked as long as the clock does not go above roughly 50 MHz , once you start switching faster than that a 100nF doesn't do a whole lot anymore and you need to drop to 10nF and below.It is all about handling dynamic load transients. if you have a bunch of logic all banging away at the same time your supply sees tremendous load changes. That's why complex systems use clock dithering and spread spectrum. It avoids massive load jumps.It is VERY hard to make a power supply that can cope with fast transients. AN old quadcore pentium could go from a few ampere to 80 ampere in a few microseconds. that made power supplies hell to design.Now they use special regulators on-board that communicate with the core. The core knows when it will bang the supply and they stage the regulators in sync with the core operations.To give you an idea : A processor for tablets talks to its power chip at an update rate of 3 million ops... just to regulate the 1.2 volt core supply rail. the core lets the regulator know if it is going to increase or decrease consumption

author: KE5FX
author_rank: Super Contributor
timestamp: May 14, 2018, 09:02:52 pm
content: Quote from: free_electron on May 14, 2018, 06:41:45 pmAbsolutely. Everybody who does this stuff needs to take a few hours during their next pilgrimage to the Bay Area and check out the Crays exhibited at the Computer History Museum in Mountain View. That style of wiring is useful to hundreds of MHz, they didn't even push it to its limits.QuoteThat, not so much. 100 nf is actually a good minimum value for bypassing in many cases. Textbooks may say one thing, but actual measurements will show that smaller values are often of minimal benefit, and can actually make matters worse. See the link in my post earlier in the thread.The thing about a large-value ceramic cap is that electrically, it looks like a whole lot of smaller ones in parallel. Use large value capsin small packagesand you can ignore most of the scary stories out there.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 14, 2018, 09:38:09 pm
content: Quote from: KE5FX on May 14, 2018, 09:02:52 pmExactly, the impedance of a 10uF cap in 0603 is identical to the impedance of a 10nF 0603, above 50MHz (in the ESL asymptote).Tim

author: free_electron
author_rank: Super Contributor
timestamp: May 15, 2018, 03:29:58 pm
content: Quote from: KE5FX on May 14, 2018, 09:02:52 pmNot true ! as the frequency increases the plates furthest away from the pcb perform less and less.An mlcc is indeed a stack of plates much like a stack of paper sheets. For very high frequency ripple , such as found in very fast processor cores ( >1GHz clockspeed ) the sheets at the bottom have a shorter electrical length than the plates at the top.That is why we have structures such as vertical caps ( where the plates are vertical as opposed to horizontal. don't flip the part 90 degrees ! it is the same part but during taping they make sure the parts sits with the plates vertical. this can be ordered from certain vendors like samsung) and things like X2Y capshttp://speedingedge.com/PDF-Files/X2Y%20vs%200402%20081605.pdfin an X2Y cap the current is forced THROUGH the capacitor.http://www.x2y.com/bypass.htmThis requires proper PCB layout. Simply flooding planes does not work with X2Y caps. power goes in one pin and comes out the other pin. These things are 4 terminal devicesonce you start dealing with fast transients such as found in multicore processors , big FPGA's and GPU's you can't escape such things anymore. there is very little margin on a 0.9 volt main rail...

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 15, 2018, 04:00:13 pm
content: Quote from: free_electron on May 15, 2018, 03:29:58 pmMore importantly, the end caps shield the inside and further-away surfaces, due to skin effect. Skin effect still applies, whether that current is flowing in a dielectric or not!*(*It wouldn't, actually, not in an ideal dielectric. But barium titanate is hardly an ideal dielectric: it's quite lossy even at modest frequencies, giving rise to skin effect in the same way that metal resistivity does. The skin depth will be different, of course.)Fortunately, the plates at the top aren't contributing anything, since we're talking frequencies where the capacitive reactance has long since saturated compared to circuit impedance (i.e., over a few MHz for large values). So the RF path length and impedance only continues to drop (until such point where ESL takes over, of course).QuoteAlthough that's how they show them used, flooding planes...On that note, there was the Proadlizer filter/caps they used on the PS3,https://www.nec.com/en/global/techrep/journal/g06/n05/pdf/t060514.pdfbut it seems they didn't catch on, and soon went out of stock as that generation of game consoles ceased production.QuoteTheir (X2Y's) documentation is wholly unconvincing, and the single source, plus increased cost, seals the deal: you can do much better on all fronts with two or more 0402s or 0603s.Or conventional cap arrays, if you like -- alternating +/- along each side of a quad 1206 will do better still!Tim

author: free_electron
author_rank: Super Contributor
timestamp: May 15, 2018, 06:02:42 pm
content: Quote from: T3sl4co1l on May 15, 2018, 04:00:13 pmThey don't really cost much more and you can get away with one or two as opposed to 40 dust caps. very important to shove them under a 1500 pin BGA ...For really advanced stuff : embedded capacitor foil in the PCB. The prepreg between power and gnd planes is replaced by a capacitor foil. Works wonders !and for really tricky stuff : simply embed passives inside the PCB. Cavities are milled inside the board and conventional ceramic caps are bonded using thermoset conductive paste. you don't see the components form the outside. This is used to embed bulk capacitance (>1uF) you can't do with the capacitive foil. Sprinkle 2u2 or 4u7 4v 0201 directly under the regulator pads.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 15, 2018, 07:15:22 pm
content: Quote from: free_electron on May 15, 2018, 06:02:42 pmOne or two?! You'll excuse me if I shout bullshit without the eye diagrams to back that up.QuoteYou cost-no-object boys get to have all the fun. Sigh...Tim

author: KE5FX
author_rank: Super Contributor
timestamp: May 15, 2018, 10:20:49 pm
content: Quote from: free_electron on May 15, 2018, 03:29:58 pmMake some measurements, and get back to us.Hint: measurements made by people selling fancy capacitors tend to look different from the ones you make yourself. Only the audiophiles have a keener sense of marketing than those folks do.E.g., let's see some plots of 0402s versus 0306s. I have some of the latter around here, but haven't had time to poke at them yet.

author: free_electron
author_rank: Super Contributor
timestamp: May 15, 2018, 10:44:33 pm
content: Quote from: T3sl4co1l on May 15, 2018, 07:15:22 pmembedded capacitance foil is cheaper than all the loose parts + assembly time. it saves board real estate, reduces routing complexity and the end product is cheaper.

author: srce
author_rank: Regular Contributor
timestamp: May 16, 2018, 07:19:56 pm
content: Quote from: EEVblog on May 09, 2018, 12:31:37 amAlas, I didn't learn about t-lines at school, but did come across this myself a couple of weeks ago.. I wrote the following for another forum, which may be of interest to some.I was looking at similarly distorted waveform on the output of a 22.5MHz oscillator on a PCB I'd knocked up:Here's a photo showing the oscillator and the traces to the ICs it fans out to and where on the header, close to the oscillator, I was probing.Thinking that at just 22.5MHz, it's a relatively low frequency signal, I didn't pay too much attention to its routing. I was more interested in having modular PCBs so I could experiment with different parts. These are pretty small PCBs, so the total distance from the oscillator output pin, through the header and to the furthest input pin on the AND gate IC is just 35mm. That didn't seem too far.Alas, my intuition is often wrong. So let's sim it. To begin with, we need to understand the geometry of the PCB and the trace. This is a two layer PCB, with a ground plane at the bottom and the signal trace on the top - a microstrip. Here's a cross section:The propagation speed of an electrical signal through a top-layer PCB microstrip, can be calculated with:Here, c is the speed of light, and Er is the relative permittivity (or dielectric constant) of the PCB substrate. For this PCB, I'm using FR-4 material for the substrate, so this value is around 4.5. The scaling of Er by 0.475 and adding 0.67, accounts for the fact that the FR-4 substrate is only below the microstrip and we have air above. If this were a four layer PCB and our microstrip was on one of the inner layers, we'd need a different formula.Code:er=4.5; % relative permittivity of dielectric for FR4eeff = 0.475*er+0.67; % effective permittivity for top layer microstrip (substrate material is only on one side)c=3e8; % speed of lightvp_mps=c/sqrt(eeff); % speed in m/svp_mmpns=1e3*vp_mps*1e-9 % speed in mm/nstpd=1000/vp_mmpns % propagation delay in ps/mmSo in 1ns, a signal will travel around 180mm. This means it takes 35/180=195ps for a signal to travel from the oscillator to the AND gate IC.If the clock were a 22.5MHz sine wave, then its rise time would be 1/22.5e6/2=22ns. However, it is actually closer to a square wave with a rise time of 600ps, so approximately .35/.6 = 600MHz bandwidth. In the former case, the rise time is much greater (112x) than the propagation delay, in the latter, it's fairly close (3x). Let's run a spice sim to see why this relative difference is important.In order to tell our spice simulator how to simulate this, we need to create a transmission line model, based on the above microstrip geometry:Code:.model top_trace u level=3 plev=1 elev=1 nl=1+ th=1.378mil ht=63mil kd=4.5 dlev=1+ wd=12mil.endWe can then create a schematic in spice that consists of a voltage source, followed by the transmission line model, and then a 4pF capacitor to simulate the input pin capacitance of the IC at the end of microstrip. I've split the transmission line model in to 8 equal parts, so we can probe at different points to see what is going on along the line.Rather than immediately trying to model the oscillator's actual output and real trace length, we can start with a simplified example. We can look at how a single 600MHz sine wave pulse (the highest frequency component in the square wave) would propagate down an 800mm microstrip (a very big PCB!).We can see the voltages at different points along the line in the top 8 waveforms, with the bottom 8 waveforms showing the current at the same points. We can see that because we have a capacitor at the end of the microstrip, the pulse is reflected back. When the reflection initially occurs, we can see the current reverse direction (it becomes negative), then we can see it lead voltage. The simulated round trip time is around 9.6ns. The speed was therefore 2*800mm/9.6n = 167mm/ns, which is close to the estimated value above (The formulas used by spice will be more accurate than the approximation above).If we decrease the length of the microstrip to 400mm, we can see that the wave is reflected back sooner, as it has less distance to travel.If we decrease the length again to 80mm (so that the round trip time is 2*80/167=0.95ns), we can see the reflected pulse is constructively interfering with the initial pulse. The pulse shape observed depends upon where exactly along the trace you probe:If we reduce the length to 8mm (with a roundtrip time of 2*8/167=95ps), the reflections are so fast, that they don't distort the waveform:So we can see that if the round trip time is greater than about 1/6th of the rise time, the reflections are going to distort what we see with a probe. And the distortion observed will depend where along the trace we probe.We can then change the voltage source in the schematic to create a square wave closer to what the oscillator outputs, to see if we can see something similar as was seen with the real oscilloscope, in order to validate our model.And that looks pretty similar. If we then shorten the microstrip length, the distortion disappears.So, as most probably already knew, we need to start worrying about reflections when the round trip time is greater than about 1/8th of rise time and keep the traces as short as possible.

author: Phoenix
author_rank: Frequent Contributor
timestamp: May 30, 2018, 12:25:37 am
content: I thought I'd share my latest EMC radiated emissions results from a 7? year old product Ive inherited and doing a 3G -> LTE upgrade on. The main microcontroller (4.912MHz) had insufficient decoupling capacitors causing it to fail radiated emissions. The oscilloscope also showed about 60mVp-p of high frequency ring on the 3.3V rail near the uC.Red/Green - Original electronics, insufficient decoupling, not sure how this even passed, probably subtle changes in manufacturing. Note the high power narrow band spikes that are at harmonics of the main uC clock. If you look at peak 1 in red the quasi-peak is basically the same as the peak indicating the noise is also constant.Blue - With proper decoupling near each IC power pin. No narrowband spikes, now passes CISPR32 with about 5dB margin.Are bypass capacitors really required? Yes.