DIY Ultra-Low current calibrator(I=C * dV/dt concept) - Page 1
Forum section: electronics / general

author: shodan@micron
author_rank: Contributor
timestamp: January 15, 2021, 12:40:18 am
content: void

author: Kleinstein
author_rank: Super Contributor
timestamp: January 15, 2021, 10:02:17 am
content: I don't hink one would need such fine control over the ramp speed with a DDS clock. The µC timing resolution should be sufficient with the relatively low update rate of < 10 kHz. As there is already some DNL error from the ADC, the exact timing when the codes change is not that critical. If needed the update time could be set by a numerical oscillator (similar to DDS - just 1 bit output). The error from added jitter is way smaller than the DNL error of the DAC.The OPA140 is a nice OP, hower mainly for high impedance signals. For low impedance signals at low frequency there are better choices - 1/f noise if the OP would be a concern. Anyway this is more like a detail.One should condider combining much if the filter function with the DAC output. I would consider a lower filter frquency (more like 1 Hz) if possibly. If needed the initial settling of the filter could be corrected, by a modifed ramp shape at the start.It may make sense to divide down the ramp voltage for the lowest range - this would reduce the cycle time, but would reduce ADC errors and give an additional way for a consistancy check.It seems to be goo practice to also measure that ramp voltage with a good external DMM.

author: bsw_m
author_rank: Frequent Contributor
timestamp: January 15, 2021, 10:39:38 am
content: Some words about low current standard in VNIIM.As I known this standard was developed by VNIIM and manufactured by MNIPI.As I known RAMP generator using 2 PWM DAC, one DAC working with constant update speed other DAC forming VREF for it.The architecture of this RAMP generator is very similar to that of the NK4-1 standard, but with some improvement, like digital feedback for resulting RAMP.The big difference is hidden in the differentiators. And their air capacitors on sapphire insulators. But unfortunately, I know almost no details.Please treat this information with caution, as it is inconsistent with the information published in the article.As far as I know, the analog integrator to form the RAMP was used quite a long time ago (back in the 70's), in very old calibrators like EK1-6.Also some information about the standard used in VNIIM, I think you can learn from the works of Pavlov O.M.On this post:https://www.eevblog.com/forum/metrology/nk4-1-low-current-and-high-resistance-calibrator-(made-in-belarus)/msg3277576/#msg3277576I'm share article about calibrators and standard's, but this article in Russian.

author: KT88
author_rank: Frequent Contributor
timestamp: January 15, 2021, 12:09:31 pm
content: Using a DDS is a very powerful approach to dial through orders of magnitude of currents at a very high resolution.Errors of the DAC would just add some noise to the current - but only below 1ppm (the AD5790 guaratees <1ppm, the DAC1101A <4ppm).Cool approach!CheersAndreas

author: fcb
author_rank: Super Contributor
timestamp: January 15, 2021, 12:24:21 pm
content: Nice work. Have you built the precision capacitor yet?

author: Anders Petersson
author_rank: Regular Contributor
timestamp: January 15, 2021, 01:40:50 pm
content: Interesting. I wonder what the BOM cost will be.Won't the leads to the DUT add capacitance that will throw off the accuracy? Or would the C capacitor have many orders larger capacitance?

author: Kleinstein
author_rank: Super Contributor
timestamp: January 15, 2021, 02:19:36 pm
content: The main exnsive parts would be the DAC and maybe the reference. For the reference it would be mainly about low noise, not so much about long term stability.The DDS and timing part looks a bit complicated, but is not really expensive, even if overkill for the use. For the start NCO control (can be doen in SW in the µC) should be sufficient.One may get away with BOM costs in the $100 -$200 range. For the start a cheaper DAC may be an option. The range setting capacitor for the output would need to be a relatively special, stable part - like a air capacitor with saphire spacers, maybe adjustable with calculable capacitance. So this would be extra. Larger ranges (like 1 pA) could use stable commercial caps.The current source would be made to work with relatively low impedance targets (e.g. TIA type electrometers). Cable capacitance would not direct effect the result - it would add to possible noise however.The relevant capacitance is from the ramp to the DUT input, so like a 2 port capacitor with a grounded shield. To keep the capacitance small and avoid leakage one would still keep "cables" short, or avoid them all together. So something like a shielded capacitor directly at the plug to the DUT with something like a normal BNC or SMA input for the ramp signal. The precision ramp generator can than be separte.Another point one has to keep in mind is that dirft and noise at the receiving end TIA amplfier would add to the ramp and thus the noise. The low current amplifiers tend to be a little noisy and also show some drift - so one does not have to overdo it with the noise of the ramp.

author: NWerner
author_rank: Contributor
timestamp: January 15, 2021, 08:07:17 pm
content: DAC11001A has a rather largish voltage output range.Maybe one can take advantage of this:From a first look glance at the datasheet it seems beneficial touse higher voltage reference span instead of averaging references.As far as I understand the DDS-approach looks very cool indeed.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 15, 2021, 10:34:59 pm
content: Filling the capacitor with a known gas is a 2 sided thing: it helps against effects to the humidiy on air dielectric constant. However this is usually not a large effect. So not so sure it would be really needed.The downside is that one add a possible pressure effect from the air pressure causing mechanical stress in the outer walls. An air tight seal would also need some special care and make low electrical leakage more dificult.It may be enough to flush the capacitor with some 99% nitrogen with still a capilary open to air.Not sure it is feasble to build the capacitor in a way, so that one can calculate the capacitance with suficient accuracy from the dimensions. This may not work for the absolute value, but at least for the change in capacitance when adjusting the spacing.It somewhat depends on the level pf precision aimed for.

author: doktor pyta
author_rank: Frequent Contributor
timestamp: January 19, 2021, 08:10:02 am
content: Only first order lowpass filter with 100ms time constant?Correct me if I'm wrong but the ADC will change it's output approx. 14 times per second considering 30min ramp. There will be a glitch every time the code is changing.

author: fcb
author_rank: Super Contributor
timestamp: January 19, 2021, 09:29:39 am
content: There's quite a nice DC accurate LPF used in Fluke and Datron calibrators.Here's a snippet from the 5500, D6 board. It's input are a pair of PWM DAC's.I've seen as high as 7th order (with more caps etc..)

author: Kleinstein
author_rank: Super Contributor
timestamp: January 19, 2021, 12:21:02 pm
content: The DDS part should still have a good low pass filter at the output to remove aliases, even if only a square wave is needed. One may cut a few corners by setting the frequency limit a little lower than normal, but I would still use a simple form of the usual elliptic LC filters, maybe 5 th order or so.I don't think one would need the extra buffers for the reference, just 2 OPs to drive the DAC should be OK. Here more conventional BJT based OPs should be better than the JFET type OPA140. So more like OPA207 or AD867x.The low pass filter for the reference could have the low side of the filter cap to the negative reference for the DAC. With would give an x2 multiplier for the capacitance essentially for free.Some division makes sense, but I doubt it makes sense to divider more than /100. Even there the voltage would be rather low and noise would become an issue. Remember that it is not just the noise of the triangle generator, but also the noise of the DUT input that matters. The high impedance input amplifiers at the TIAs usually have quite some noise. So for small currents it is way better to reduce the capacitance than reduce the voltage. One may even consider the opposite way of a times 10 gain to extend the range covered by a single capacitor.It may make sense to have the option to switch the filter after the DAC. This way one may also use the generator at higher frequencies (maybe up to some 10 Hz) to generate a much larger current for calibration purposes. For the slow slopes the slow filter should be good, but for a fast case it would be more like 10 kHz upper limit that would be appropriate.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 19, 2021, 07:58:03 pm
content: Without any filter one would get a step function and thus the current would turn into a series of spikes in the extreme. So one still needs some kind of reconstruction filter. It may not need to be that low, but something like 1/10 the minimal usefull sampling frequency would be nice. Beside the LSB steps, there is also some extra ripple from the DNL error - the steps are not all the same size, but more like 50% variable. In addition there are fast ( µs range) switching spikes from the DAC. The Filter would average out the uneven step size over a few steps.The DAC steps start as some 19 µV / sqrt(12) noise amplitude over the BW set by the sampling frequency. With 100 pF cap this would a lot of current noise.Chances are one may need more than a 1st order filter, though the cross over may not need to be so low.To a first approximation one could correct for the fitler effect on the initial part of the ramp. In steady state (e.g. after a few seconds) the fitler would cause more a fixed delay and not more added error.The TA part usually also constains some fitlering and would anyway need quite some time to settle.A simple 2 nd oder Sallen key filter may be also possible, combined with the buffer after the DAC. So it would be only 1 OP wired as buffer - so no more errors than the buffer.

author: KT88
author_rank: Frequent Contributor
timestamp: January 19, 2021, 09:33:07 pm
content: There is probably no need for an LPF at all. First, the step related noise is deterministic/periodic - if needed, post filtering of the sampled data would likely be sufficient, if needed at all.The sampling time could be set slightly delayed to allow for settling of the EUT output - that way step related noise won't show up at all. The only artifact that might be noticed could be a slight offset.Edit: this assumes synchronized sampling...CheersAndreas

author: Kleinstein
author_rank: Super Contributor
timestamp: January 20, 2021, 08:13:06 am
content: The general idea for the filter looks interesting. Instead of a low pass this would be a kind of band stop filter. In principle this could reduce the effect due to DA of the capacitors - however this would need C10 also to be a low DA type, like PP, definitely not a X7R which is crazy nonlinear and temperature dependent. I have not done a detailed calculation - one may get away with a polyester (e.g. MKS) type capacitor.The electrometer input has low pass character, but the capacitors acts as differentiator and thus acts as the opposite of a 1st order low pass.The current towards C8 and C9 (in the old circuit without C10 U5B) would be constant with a constant ramp. So this would only shift the ramp by a constant voltage or time, but would not effect the ramp rate itself. It would only be the initial part (some second) after change of slope, where it would really effect the signal. In this range the low pass character of the DUT would not allow accurate readings anyway.Reading the DUT in perfect sync with the source may not be possible in most cases, at least not with modern instruments that include the ADC part. In these cases one would only have the option to synchronize the ramp generator to the DUT at the cost of more jitter from different update times.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 23, 2021, 05:18:23 pm
content: The DDS part should really have at least some low pass filterig for the sine wave (e.g at least a capacitor to ground) otherwise there would be quite some jitter, hardly better than the quantization from the clock. Without a filter the DSS part may not help.

author: iMo
author_rank: Super Contributor
timestamp: January 23, 2021, 05:43:20 pm
content: Or you may use AD9833 it can output a square..

author: Kleinstein
author_rank: Super Contributor
timestamp: January 23, 2021, 06:15:35 pm
content: The square ouput of the AD9833 is no better than the clock, it is just the MSB going to the DAC. To get additional timing resolution beyound 1 clock cyle it needs a reconstruction filter.

author: iMo
author_rank: Super Contributor
timestamp: January 23, 2021, 06:59:03 pm
content: Quote from: Kleinstein on January 23, 2021, 06:15:35 pmThe square output's frequency has the DDS frequency granularity..If you set 123456,7Hz you get 123456,7Hz sine, or, 123456,7Hz square..The 9833 is 28bit freq word only, however..

author: Kleinstein
author_rank: Super Contributor
timestamp: January 23, 2021, 07:33:09 pm
content: The square output has the fine frequency steps of the NCO, but it is still limited to quantization in the time domain to clock cycles. So one would still see the fine frequency steps, but with jitter. The same (or better - due to a higher clock) cold be acieved directly from the µC with a NCO in software with ouput via a PLL channel. It can still be good enough (at least for slower ramps), as the DAC accuracy (DNL error) is limited anyway.

author: MegaVolt
author_rank: Frequent Contributor
timestamp: January 24, 2021, 07:24:11 pm
content: Quote from: shodan@micron on January 23, 2021, 08:25:05 pmWhere can I read the details?

author: Kleinstein
author_rank: Super Contributor
timestamp: January 25, 2021, 09:16:16 am
content: When used at only low temperature difference, there is no need (and it only reduces the efficiency) to use a high current close to the nominal power. It would be better to use only a small fraction of the rated current / voltage of the TC. So I am not so sure the given TEC is a good choice. I would more like go fo a TEC made for higher voltage (e.g. 12 V or even 24 V if you can find one) and have a lower supply voltage (e.g. 12 V at most and maybe even only 5 V).A TEC for temperature stabilization always has the trouble that there is quite some heat conduction path through the TEC. So it would help to have an element not too powerful. This is especially true with a part to stabilize that is low power, like a capacitor. Small elements are relatively rare and often only low voltage.Depending on the environment (humidity) it may be better to use a small oven to get a temperature slightly above room temperature. This has the positive side effect to lower the RH and this can help with surface leakage, though bulk leakage currents may go up.

author: Vgkid
author_rank: Super Contributor
timestamp: January 27, 2021, 06:14:13 am
content: @ Shodan:Have you used that Maxim TEC controller before ?It looks like a pretty neat part.

author: Vgkid
author_rank: Super Contributor
timestamp: January 27, 2021, 08:09:34 am
content: I look forward to seeing the results.

author: seebeck
author_rank: Contributor
timestamp: January 27, 2021, 10:56:04 am
content: Hi fcb，You have the schematic diagram for FLUKE 5500A? Could you please share it to me.. Thanks a lot!With best regards.From Seebeck

author: fcb
author_rank: Super Contributor
timestamp: January 27, 2021, 11:01:19 am
content: Quote from: seebeck on January 27, 2021, 10:56:04 amhttp://www.ko4bb.com/getsimple/index.php?id=download&file=Fluke/Fluke_5500A_Multi-Product_Calibrator_Service_Manual.pdf

author: Kean
author_rank: Unknown
timestamp: January 31, 2021, 12:27:48 pm
content: Thanks for posting those design files. I'm interesteding in building one of these as it is hard to get a decent TEC controller for an affordable price in Australia.I should probably first dig through my collection of auction scores/debris to make sure I don't already have a TEC controller gathering dust (I know I have a bunch of laser diodes in there).

author: Kleinstein
author_rank: Super Contributor
timestamp: February 01, 2021, 07:06:04 pm
content: There is quite some ringing in the power. I would guess C12 or R7 should get a little larger, as the time constant C12*R7 = 1 s in the regulator is relatively short, while there is quite some distance from the TEC to the sensor and thus possibly some delay. The rule of thumb rules for adjustment want the time constant in the regulator somewhat faster (e.g. factor 2-4) than the delay from the actuator to the sensor.

author: antintedo
author_rank: Contributor
timestamp: February 02, 2021, 10:42:41 am
content: Ambitious project, I'm really looking forward to the homebrew capacitance standard.One note: 34410A trigger jitter specs are much worse than short term ADEV of OCXO in the GPSDO. Is it going to be good enough? You might need a sample and hold circuit to fully utilize the GPSDO.

author: maat
author_rank: Regular Contributor
timestamp: February 05, 2021, 01:59:48 am
content: Quote from: shodan@micron on February 04, 2021, 10:54:04 pmCan you plot both graphs on different axes? It is a little hard so see the tempco.

author: fcb
author_rank: Super Contributor
timestamp: February 28, 2021, 12:48:26 pm
content: That's bad luck. Wishing you a UF4006.

author: Vgkid
author_rank: Super Contributor
timestamp: June 25, 2021, 12:12:39 pm
content: Looking forward to the next updates.

author: Echo88
author_rank: Frequent Contributor
timestamp: June 26, 2021, 10:02:00 am
content: I hope your triboelectric measurements will bring you satisfaction.

author: fcb
author_rank: Super Contributor
timestamp: June 26, 2021, 12:23:38 pm
content: Are you expecting alot of vibration in your calibration setup?

author: fcb
author_rank: Super Contributor
timestamp: June 26, 2021, 01:55:01 pm
content: Did you conduct a test with the AVK-6?

author: Kleinstein
author_rank: Super Contributor
timestamp: June 26, 2021, 03:40:49 pm
content: The real world use would not see much vibrations, but there is stress to the cables at lower frequency from moving the cables. The hope is that low sensitivity at the relatively fast vibration frequency would also mean less coupling at the lower frequencies. Measuring at much lower frequencies gets more complicated and time consuming. So it makes sense to do at least the initial tests with the higher frequency.Quote from: shodan@micron on June 26, 2021, 03:26:11 pmFor more sensitivity one could us a secons channel to measure the excitation and than do cross correlation (look at the signal like a lock-in). With enough time one can detect very tiny signals (aA range) this way. It is not noise but coupling the test is looking for.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 26, 2021, 03:48:10 pm
content: Touching the cables gives a mechanical effect, but also some temperature change. There is also possibly pyroelectricity.

author: bsw_m
author_rank: Frequent Contributor
timestamp: June 26, 2021, 04:00:25 pm
content: Dirty simple bumping test for AVK-6 (there is no store in my city where such high-performance vibrating test devices are sold)On video: measuring the 100MOhm dut (MRH resistor 100MOhm ±0.1%) wired by AVK to my V7-54/2 DMM.Please note: little instability in the least significant bit is not due to cable noise - this is the noise of the meter.

author: RoGeorge
author_rank: Super Contributor
timestamp: June 26, 2021, 04:51:53 pm
content: To get a nice clean trace and filter out the noise, a microphone or a piezo transducer attached to the workbench can be used in order to get a strong and clean signal of the vibrations. This signal is used on a second channel to synchronize the oscilloscope, then set the acquisition mode on 'average'.The average between consecutive traces combined with a clean sync signal will turn the oscilloscope into an improvised lock-in amplifier, and get rid of all the noise.The naming of the trace average might vary between oscilloscope manufacturers. The averaging mode must be the one that averages between many consecutive traces, not between consecutive ADC samples.The results can be quite spectacular (not a precision measurement, but has screen captures with and without averaging):https://www.eevblog.com/forum/projects/oscilloscope-with-trace-averaging-as-a-lock-in-amplifier-(rigol-ds1054z)/

author: bsw_m
author_rank: Frequent Contributor
timestamp: June 26, 2021, 06:53:22 pm
content: Quote from: shodan@micron on June 26, 2021, 03:26:11 pmI would like to draw your attention to the fact that this cable was also used by MNIPI for its nanovoltmeters.

author: fcb
author_rank: Super Contributor
timestamp: June 26, 2021, 07:23:52 pm
content: Don't suppose there is a source of this AVK-6 in the West??

author: Kleinstein
author_rank: Super Contributor
timestamp: July 03, 2021, 09:27:33 am
content: For such a test I would prefer doing the test with votlage steps in both directs instead of subtracting a seprate measured leakage / bias current.For a check it would also be good to also vary the parameters on the test, like different voltages and maybe different charging times. The caps look like they are specitied at 1 kHz and not some 0.25 Hz or lower as in the test. The difference (e.g. due to dielectric absorption) should not be large though.