CLock Gating | DFLL | GCLK on SamD21 - Page 1
Forum section: electronics / general

author: eddie0x7c3
author_rank: Newbie
timestamp: March 30, 2016, 03:35:03 am
content: So if my understanding is correct from the code below, which i know is excessively modulated but i just wanted to take it one step at a time and understand what i was doinganyways...Code:void update_freq(){init_clock_source();init_generic_clocks();init_FDLL48();init_generick_clock0();}void init_clock_source(){//enable clock source and configure with start up time , standby , amplitude//enable pins for use with crystal , enable the crystal , then enable the outputSYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ENABLE;SYSCTRL->XOSC32K.reg|= SYSCTRL_XOSC32K_STARTUP(5) | SYSCTRL_XOSC32K_AAMPEN | SYSCTRL_XOSC32K_EN32K | SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_ENABLE ;while((REG_SYSCTRL_PCLKSR & (SYSCTRL_PCLKSR_XOSC32KRDY)) == 0); // check system clock status register for clock to be ready}void init_generic_clocks(){//1 division at generator 1GCLK->GENDIV.reg = GCLK_GENDIV_DIV(1) | GCLK_GENDIV_ID(1);//enable | 32khz source | genrator 1GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(1);//enable | gen 1 | dfll48mGCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(1) | GCLK_CLKCTRL_ID_DFLL48;}void init_FDLL48 (){//enable dfllSYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE ;SYSCTRL->DFLLMUL.reg = (SYSCTRL_DFLLMUL_FSTEP(10)) | (SYSCTRL_DFLLMUL_CSTEP(5)) | (SYSCTRL_DFLLMUL_MUL(1465));SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE;while((REG_SYSCTRL_PCLKSR & (SYSCTRL_PCLKSR_DFLLLCKC)) == 0);NVMCTRL->CTRLB.reg |= (NVMCTRL_CTRLB_RWS(1));}void init_generick_clock0 (){GCLK->GENDIV.reg = GCLK_GENDIV_DIV(1) | GCLK_GENDIV_ID(0) ;GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(0) ;GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN(0) | GCLK_CLKCTRL_CLKEN | ;}my question concerns mainly the last functionand the overall function of the GCLK1. The "ID" bits in GENDiv and GENCTRL refer to the Clock i am configuring except in CLKCTRL it refers to the final output peripheral , with the exception of DFLL48 to loop back around...2. In the last function the code does not specify an "output" ID in CLKCTRL ? so generick clock 0 in this case is the one with 48mhz output...?3. Does it have to be Generick CLock 0?4. To apply this 48mhz to a peripheral would i configure a generick clock with generator 0 as the source? or DFll48?5.and why is the PORT not an option in the ID section for CLKCTRLAlso what does coarse and fine step do to the DFLL?

author: ataradov
author_rank: Super Contributor
timestamp: March 30, 2016, 03:51:51 am
content: Quote from: eddie0x7c3 on March 30, 2016, 03:35:03 amThe question is not clear. In both cases they refer to GCLK Generator ID (value 0-7). It is basically the same thing as if there were 8 sets of registers (which would be better, IMO).Quote from: eddie0x7c3 on March 30, 2016, 03:35:03 amIt sure doses. You are making GCLK0 output 48MHz taken from DFLL.Quote from: eddie0x7c3 on March 30, 2016, 03:35:03 amIt can be any GCLK you like.Quote from: eddie0x7c3 on March 30, 2016, 03:35:03 amYou do something like this:Code:GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(TC0_GCLK_ID) | GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);This enables clock for TC0 (and TC1, since all timers are doubled up).Basically in a peripheral you specify GCLK1 that you configured previously.Quote from: eddie0x7c3 on March 30, 2016, 03:35:03 amPorts are always clocked, I guess, but I'm not sure with what clock. More reading of the DS is required.Quote from: eddie0x7c3 on March 30, 2016, 03:35:03 amCoarse is used to get initial lock and then frequency is fine tuned with fine steps.

author: ataradov
author_rank: Super Contributor
timestamp: March 30, 2016, 03:55:16 am
content: Here is info on the PORT:QuoteAnd the main clock is derived from GCLK 0. So port is always clocked and does not need additional configuration.

author: eddie0x7c3
author_rank: Newbie
timestamp: March 30, 2016, 04:10:47 am
content: Quote from: ataradov on March 30, 2016, 03:51:51 amBut the ID bits in GCLK are not configured in the last function... thats why i say the the ID bits in the other registeres refers to the generator your configuring but in the CLKTRL register ID does NOT refer to the generator your configuring , otherwise why would the not be set in the last function? I think in the CLKCTRL the GEN bits refer to the generator your configuring and ID refers to where its going to be output. At least thats what it seems like to me , becauseID options are all peripherals in CLKCTRL , while in the other registers the ID bit options are all Generators

author: ataradov
author_rank: Super Contributor
timestamp: March 30, 2016, 04:35:21 am
content: Quote from: eddie0x7c3 on March 30, 2016, 04:10:47 amIn CLKCTRL register ID field is the ID of the peripheral and GEN is the ID of the GCLK you want this peripheral to be clocked from.

author: eddie0x7c3
author_rank: Newbie
timestamp: March 30, 2016, 04:49:07 am
content: Quote from: ataradov on March 30, 2016, 04:35:21 amGotcha! and in the subsequent registers the ID bits refer to this GCLK in the GEN ID bits

author: ataradov
author_rank: Super Contributor
timestamp: March 30, 2016, 04:53:07 am
content: ID refers to the main thing you are configuring.In case of GENCTRL and GENDIV you are applying settings to the GCLK itself, so ID there is ID of the GCLK.In case of CLKTRL you are configuring a peripheral (this register should really be located in each peripheral), so ID refers to a peripheral.That clock configuration is very confusing at the beginning, but once you figure it out, it is so hard to go back to parts with fixed clocking scheme.