Power Delivery + JTAG Design for FPGA - Page 1
Forum section: electronics / general

author: spaghetti
author_rank: Newbie
timestamp: July 06, 2023, 03:52:37 pm
content: Hey all!This is my first foray into FPGA board design and unfortunately I do not have anyone experienced at hand to ask these doubts, so excuse any questions that might have obvious answers.I am designing a board based on the Artix7 FPGA, which will be mainly powered via an external 5V supply. This power rail goes to a quad-buck converter that then provides all the other essential rails needed by the FPGA.However, I also plan to add a microUSB --> FT2232Hx --> JTAG to be able to program the FPGA via USB.Question 1: In order to avoid powering the board from both sources at the same time, I plan to add a jumper to select the source (Ext or USB). Is there a better way to solve this issue so only one source ever gets preference (ideally ext 5V)?Question 2: In the event where I need to program the board while being connected to the external rail, the FT2232H does allow this. For that it needs to be connected as per the reference design in Figure 6.4 on page 53. That looks fairly straightforward, but could someone with any experience explain the exact functioning of pin 59 as PWRSAV#? I am confused by the statement "Also this configuration uses the pin BCBUS7, so this assumes that MPSSE mode is not selected."https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdfQuestion 3: I also plan to provide JTAG pins for external programmers to interface with the FPGA directly. For this I have a Digilent HS2 handy, which has a +3V3 VDD signal inbuilt. What would be a good scheme to connect this via headers directly, without the power going off to the output of the buck converter?Coming from MCU designs, FPGA design and documentation has me sweating all day. Thanks in advance for any help, and apologies for any banal questions!

author: asmi
author_rank: Super Contributor
timestamp: July 06, 2023, 04:34:56 pm
content: You can take a look at the project in my signature to get an idea of what it takes to implement such a board (the project uses Spartan-7, but it's pretty much the same for Artix-7). However it does not include USB programmer circuit because I already have an HS3 programmer and I wanted to make design as simple as possible.As far as USB power, you can implement a self-powered design which will not consume any current from USB +5V rail (beyond some trivial current used for VBUS sensing via voltage divider). Take a look at FT2232 datasheet, it contains an example of self-powered schematics.

author: langwadt
author_rank: Super Contributor
timestamp: July 06, 2023, 07:10:36 pm
content: https://numato.com/help/wp-content/uploads/2019/05/mimas-a7-mini-board_Sch_V4.0.pdf

author: spaghetti
author_rank: Newbie
timestamp: July 07, 2023, 01:31:15 pm
content: Quote from: asmi on July 06, 2023, 04:34:56 pmThanks for the direction. It has definitely helped in verifying my design with what you did, and I guess I will go down the programmer only route. Gotta check with the higher-ups!

author: spaghetti
author_rank: Newbie
timestamp: July 07, 2023, 01:33:39 pm
content: Quote from: langwadt on July 06, 2023, 07:10:36 pmOh damn looks like you found the smoking gun! I was going through some Digilent dev board schematics and unfortunately they do not release their USB-UART connections. Glad you found one with almost everything of the core stuff I need! Thanks!

author: asmi
author_rank: Super Contributor
timestamp: July 07, 2023, 02:12:13 pm
content: Quote from: spaghetti on July 07, 2023, 01:33:39 pmNote that in this schematics FTDI chip is not wired for USB-JTAG interface. I've recently designed a small board which would act like a HS3 "on steroids" - there is a JTAG interface, and a UART interface, each of them can work with different Vccio. I've attached a schematics if you are curious, the board has been assembled and it actually works - at least for FPGAs, didn't check with Zynqs yet. Note that this design contain two voltage level translators (one for JTAG and another one for UART), if your use Vccio of 3.3 V, then you don't need it. As a side effect, these voltage translators provide for some isolation - USB side of module is USB-powered, but "receiving" side of voltage translators is powered by connected boards. There is also some extra stuff for my experiments, which you won't need in the final design. I also use a USB-C connector which I think is a preferred option for new designs in this day and age.

author: spaghetti
author_rank: Newbie
timestamp: July 07, 2023, 02:54:36 pm
content: Quote from: asmi on July 07, 2023, 02:12:13 pmI am using an Artix 7 XC7A35T for my board, so I don't need the Zynq pins. And all my peripherals run at +3V3. However, that is indeed a nice way to handle level shifting, especially if I plan to do external I2C comms with Arduinos or something.My schematic (attached) is almost similar to yours in the way I am using the ports. Curiosity, what is the use of the FT_POR_B and FT_JTAG_CONN signals and how do they interface between the PC and FPGA? Also I believe FT_SRST_B is used only on Zynq SOCs, so I'm ignoring this pin for now.

author: asmi
author_rank: Super Contributor
timestamp: July 07, 2023, 03:45:53 pm
content: Quote from: spaghetti on July 07, 2023, 02:54:36 pmFT_POR_B and FT_SRST_B were wired for Zynqs - I wasn't sure which one of them is to be used for Zynq reset, so I wired them both across a jumper (JR1 in my schematics), so that I can connect either one of them to a JTAG header. FT_JTAG_CONN indicates when USB is connected to PC, I use it to enable voltage translators through inverter gate - this ensures voltage translators pins are are tristated when USB is not connected so that they won't interfere with any other JTAG programmer I might want to use. I found this information here (note that there they use FT2232H pin numbers, while I use FT2232H-56Q, which has a different pinout):https://support.xilinx.com/s/question/0D54U000064Zgo6SAC/does-xilinx-ftdi-eeprom-code-support-the-reset-needed-by-zynq?language=en_US

author: spaghetti
author_rank: Newbie
timestamp: July 07, 2023, 06:09:40 pm
content: QuoteInteresting approach. I have added it to my design since I do plan to provide parallel JTAG pins! I believe the FT_JTAG_CONN pin be set to go high when connected to power, then going through the inverter -> buffer logic? Or is it active high by default?

author: asmi
author_rank: Super Contributor
timestamp: July 07, 2023, 06:39:45 pm
content: Quote from: spaghetti on July 07, 2023, 06:09:40 pmAs per my testing, it goes high when Vivado Hardware Manager "opens" a connection, and it's low otherwise, so in my case I keep voltage shifters tristated unless someone actually attempts to use a connection for programming/debugging. I had to use an interter because "Output Enable" signals on voltage shifters I use are active-low, I use multi-function logic gate IC 74LVC1G97GM instead of a simple inverter for the purposes of stock efficiency - since it's a multi-function IC, I can configure it for different logical functions in different designs while stocking just a single part, and not stock various gates individually.

author: langwadt
author_rank: Super Contributor
timestamp: July 07, 2023, 07:49:14 pm
content: Quote from: asmi on July 07, 2023, 02:12:13 pmit is wired for jtag via usb on port B and sync fifo on port A, there's a couple of switches so when you insert a jtag adapter it takes over the jtag interfacebut since jtag is on port B won't work with the Xilinx tools just by programming the FTDI with a Digilent eeprom

author: asmi
author_rank: Super Contributor
timestamp: July 07, 2023, 08:28:49 pm
content: Quote from: langwadt on July 07, 2023, 07:49:14 pmThere is no need to steal Digilent's EEPROM anymore as Xilinx has releases an official tool which can program EEPROM such that Vivado/Vitis would recognize and work with it. Which is what I've done for the board mentioned above.

author: langwadt
author_rank: Super Contributor
timestamp: July 07, 2023, 08:37:47 pm
content: Quote from: asmi on July 07, 2023, 08:28:49 pmsure, but afaict the HW connections are the same port A for JTAG