Status of unprogrammed FPGA - Page 1
Forum section: electronics / general

author: mriPaul
author_rank: Contributor
timestamp: April 28, 2020, 04:30:12 pm
content: I have a Deo Nano SoC Developer's board. It is connected to another device using a PCB. The developer's board has 72 GPIOs and about 20 pins are talking to the other device. To be safe, I set all pins initially to open state and added a flag value such as the following using VHDL code:gpio_0_inout(0) <= 'Z'; -- SCK(0) when flag = 3 else 'Z';It puts a pin in a high impedance state. I do this for all pins so I know the initial state and to avoid "back powering" other devices if they are not powered.What is the state of the pins when the Deo Nano SoC is powered before I load a program?

author: nctnico
author_rank: Super Contributor
timestamp: April 28, 2020, 04:46:36 pm
content: Quote from: mriPaul on April 28, 2020, 04:30:12 pmIf this is your goal you need special buffers (in seperate chips) or check the datasheet to see whether the pins can be used for this situation.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 28, 2020, 04:58:43 pm
content: Quote from: mriPaul on April 28, 2020, 04:30:12 pmMaybe someone here knows, but otherwise you should check out the datasheet of the FPGA that's used on this board. It should be stated in there.I think it's common on many FPGAs that most IOs be in high impedance upon power on/configuration, but I can't guarantee this to be true for ALL.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 29, 2020, 01:51:15 am
content: From 11-2 ofhttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdfQuoteNot siure about Cyclone IV, but on other vendors/parts the bitstream generation phase has options to set the state of unused I/O pins, which defaults to input with a weak pull-up on Xilinx, IIRC.This is so the input buffers on unused pins are not left floating in the breeze.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: April 29, 2020, 07:31:29 am
content: Yes you can set the state of the unused pins after configuration in Quartus, and by default they are in tristate with a weak pull-up.

author: AndyC_772
author_rank: Super Contributor
timestamp: April 29, 2020, 10:13:20 am
content: Note also that assigning them 'Z' in your code really does mean high impedance, ie. the internal pull-up is disabled and the pin will float (unless you explicitly enable the weak pull-up in the assignment editor, IIRC).IIRC Altera actually recommend setting unused pins as outputs driving low.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 29, 2020, 01:27:45 pm
content: Note that it really depends on each vendor...For Xilinx you can refer to this:https://forums.xilinx.com/t5/Design-Entry/Unassigned-Pin-Behavior/td-p/34114So, the default for unused pins in your design is they get pulled down. No need to do anything explicitly.Also note that if the default behavior at power on for a particular FPGA is a weak pull-up, pins may be able to power other components connected to them through the pull-ups (with granted a very low current), which is unlikely to cause any damage but could cause weird behaviors with some components that are very low power.

author: amyk
author_rank: Super Contributor
timestamp: April 30, 2020, 12:14:31 am
content: Quote from: SiliconWizard on April 29, 2020, 01:27:45 pmUnless there is no top ESD diode, you can always "backfeed" through an I/O.

author: NorthGuy
author_rank: Super Contributor
timestamp: May 08, 2020, 11:43:02 pm
content: I know Xilinx FPGAs have a special pin which either disables or enables pull-ups on unconfigured FPGA. Of course, once you configure it, everything depends on your design.

author: asmi
author_rank: Super Contributor
timestamp: May 09, 2020, 03:12:08 am
content: Quote from: NorthGuy on May 08, 2020, 11:43:02 pmYep, PUDC_B pin. For configured state, there is a bitstream option which allows setting a state of unused IOBs - could be pulldown, pullup, or none/floating.

author: filssavi
author_rank: Frequent Contributor
timestamp: May 09, 2020, 06:07:25 am
content: It’s been a while since I used the DE0 but before programming the pins are all pulled to 1 by a weak pull-up,and there is no ready way to change that, this is also the default for intel and lattice as said before with Xilinx there is a pin, depending upon its voltage the others are pulled up or down at boot, however this is by far the exception and not the rule, also usually the dev boards don’t make it easy to change setting (no jumpers or solder bridges, usually just a non descript 0402 resistor somewhere)This is a big trap for first time users, that are used to IC’s with sane defaults (everything off or tristate unless I say so)The reason this is done is for power consumption, using all pins to ground default will increase it considerably (somewhere in the range of 2x to 5x IIRC) I don’t know why for sure but my theory is that there is more internal leakage current when the pin is at 0 than otherwise

author: OwO
author_rank: Super Contributor
timestamp: May 09, 2020, 06:49:01 am
content: Something to do with PMOS having higher leakage because more area is needed to get the same on resistance?

author: filssavi
author_rank: Frequent Contributor
timestamp: May 09, 2020, 07:52:51 am
content: Quote from: OwO on May 09, 2020, 06:49:01 amYea that sounds very plausible , especially with the same driving voltage