Hantek 4032L firmware update - Page 1
Forum section: electronics / testgear

author: abyrvalg
author_rank: Frequent Contributor
timestamp: April 17, 2018, 01:25:48 am
content: There were rumours about updates of Hantek 4032L LA firmware, so I've contacted Hantek support and was surprised: an FPGA update dated 2 March 2018 fixing some bugs and finally activating the advertised but never seen external clocking featureThey are not releasing it to their public download area for some unknown reason, so it is here:https://nofile.io/f/tpFav7m6NZU/Hantek4032L+FPGA+Update.zipBut Hantek wouldn't be Hantek if everything were so simpleTheir updater tool (the tool itself, FPGA bitstream is ok if you manage to write it to flash) doesn't work on old LA units (or on all units? I know two more 4032 users and it didn't worked for them too).It shows a progress bar, says "OK" at the end, but nothing gets written (the old LA's current FX2 fw doesn't support the flash r/w commands sent by the updater, but it ignores the errors happily).So, cooperating with another happy 4032L owner we've cooked our own tools:- C/Libusb version:https://github.com/andy9a9/fx2eeprom- Python/native Hantek driver version:https://github.com/flowswitch/ht4032l-python- Various FPGA bitstream versions collection:https://nofile.io/f/wHDvptqc84x/la4032_fpga.7zPlease report if you find the original updater working on your unit (so it says ok AND you really get extclk feature working, or fpga_get_ver.py shows some changes).

author: Daruosha
author_rank: Regular Contributor
timestamp: May 21, 2018, 05:26:52 am
content: I was looking for the latest firmware version and well... Thanks for the sharing it. I managed to update the firmware of my unit using the Hantek tool then checked the actual version with fpga_get_ver.py script and it was 4304, so I assume the Hantek tool worked fine.However, How can I use the LA itself in the state-analysis mode? I couldn't find any option or setting in the official software and sigrok doesn't have that at all (AFAIK).

author: Daruosha
author_rank: Regular Contributor
timestamp: May 24, 2018, 11:29:57 pm
content: Quote from: Daruosha on May 21, 2018, 05:26:52 amWell, since no one replied and I found if you set the sample rate option to CLKA or CLKB in the official software, the LA samples at the rising clock edges, tried it and worked expectedly. However it's not been mentioned in the manual or any other placed.I bought this LA, mainly due to PulseView support, however the triggering options (data triggering, pulse with duration and etc..) are not supported in the current version of PulseView and also there's no way of search through decoded packets. Still far better than the official software (which support all the advanced triggering options, but such a massive PITA).I'm thinking of starting a new project based on PulseView and add all the hardware triggering options for Hantek 4032L and publish it on github, if anyone is interested in the project, I'd appreciate heir help.

author: maginnovision
author_rank: Super Contributor
timestamp: May 25, 2018, 05:05:06 am
content: There are other problems with PulseView too. I could NOT get it to pull 32 channels over 5m samples depth without crashing. That's a huge limitation even beyond losing the triggers and sampling on the clock. I think you and I have the same idea, do it ourselves. Luckily for me the hantek software will work for now since I'm just looking at parallel busses. Everything else I use my MSO.

author: Daruosha
author_rank: Regular Contributor
timestamp: May 25, 2018, 03:07:06 pm
content: I can download full 50M sample for all 32 channels in PulseView (not the full 64M) with no crash or any problem, however the download rate of data is a pit painful. Are you using the latest PulseView version and 4032L firmware?

author: maginnovision
author_rank: Super Contributor
timestamp: May 25, 2018, 05:05:09 pm
content: That's interesting. I used the firmware and constantly updated to the newest version over 2 weeks. Perhaps it was unrelated to the data itself and more the decoders. 2 16bit parallel decoders. I'm not sure. It ended up taking hours longer than necessary to see what I was looking for but I was able to get it done. Next time I have use for it if I have the same issue I'll prob bably throw something together with fltk and the hantek source code.

author: abraxa
author_rank: Frequent Contributor
timestamp: May 25, 2018, 08:06:11 pm
content: Quote from: maginnovision on May 25, 2018, 05:05:06 amBugs that aren't reported can't be fixedBesides, it's open source, so contributions are always welcome.

author: maginnovision
author_rank: Super Contributor
timestamp: May 25, 2018, 09:03:54 pm
content: I've looked at the bug list though and personally felt too often there were more complaints about windows bugs than solutions. As far as contributing... My previous work trying to contribute to open source projects was more work than work I get paid for with no reward. I'd rather save myself the frustration and annoyance and write my own limited scope program that does what I need it to do if and when the time comes. Leave the open source work to the people who enjoy it.

author: abyrvalg
author_rank: Frequent Contributor
timestamp: May 26, 2018, 12:53:15 am
content: Quote from: abraxa on May 25, 2018, 08:06:11 pmOne short story: I wrote the first version of thishttps://sigrok.org/wiki/Hantek_4032Lpage back in 2013, was full of enthusiasm to have fun implementing a Sigrok driver, but after finding out the procedure to build a windows version of PulseView I've told "fsck this" and went investing an $99 to DSLogic instead

author: Andy99
author_rank: Contributor
timestamp: May 26, 2018, 07:02:12 am
content: Hi,I am glad, that you are interested in this device integration too. I am one of the developers, which made last upstream 4032's changes in sigrok. Integration is still ongoing. There are some changes, which have not been merged yet.- increase speed- samples getting- thresholdsYou have talked about SCLKs, yes it's on TODO list. Any help is appreciated. We can create some 4032l slack group for knowledge sharing.

author: Daruosha
author_rank: Regular Contributor
timestamp: May 26, 2018, 07:35:15 am
content: Quote from: Andy99 on May 26, 2018, 07:02:12 amI'm in. Where do you suggest to start?

author: Daruosha
author_rank: Regular Contributor
timestamp: May 26, 2018, 10:48:44 am
content: Quote from: Andy99 on May 26, 2018, 07:02:12 amAndy, your mailbox is full, I cannot send reply your PM.

author: Andy99
author_rank: Contributor
timestamp: May 26, 2018, 01:05:38 pm
content: Quote from: Daruosha on May 26, 2018, 10:48:44 amsorry.. cleaned

author: Andy99
author_rank: Contributor
timestamp: June 07, 2018, 05:29:58 pm
content: Hi,my previously mentioned changes + external clocks have been merged into sigrok&PV masters. I guess, that they should by available in nightly buildshttps://sigrok.org/wiki/Downloads.If there are some issues, just let me know.

author: maginnovision
author_rank: Super Contributor
timestamp: June 08, 2018, 03:19:02 pm
content: Hey Andy,The changes look good but clocking from external sources is less useful when the timebase doesn't update accordingly. I was looking but didn't see where you would be able to change that. I had some other issues I could let you know about but I won't have time to use it and figure out what they were tor maybe 2 or 3 days.

author: Andy99
author_rank: Contributor
timestamp: June 08, 2018, 05:36:35 pm
content: Quote from: maginnovision on June 08, 2018, 03:19:02 pmHi maginnovision,Just for the notice, external clock isnotavailable for FPGA version 0. You can check FPGA version number with used argument "-l 5" eg. "sigrok-cli -l 5 -d hantek-4032l --show". You will see message like: "FPGA version:0x0". For upgrading, you can use one of the tool mentioned in the first post.Anyway, just let me know, if there are some issues.

author: maginnovision
author_rank: Super Contributor
timestamp: June 08, 2018, 07:18:00 pm
content: Quote from: Andy99 on June 08, 2018, 05:36:35 pmRight. The external clocking did work however the timebase wasn't based on the external clock, but the standard sample rate/sample depth. So instead of the real time of 10 seconds, it showed 18ms. I was also unable to correct it because I couldn't set the clockrate to the correct frequency.

author: Andy99
author_rank: Contributor
timestamp: June 08, 2018, 07:45:23 pm
content: Quote from: maginnovision on June 08, 2018, 07:18:00 pmWhich version of FPGA do you have on your device? Did you enable external clock over check-box in device settings? Could you please share your measurements/picture?Of course, when external clock is enabled, sample-rate is ignored.

author: maginnovision
author_rank: Super Contributor
timestamp: June 08, 2018, 09:11:33 pm
content: Quote from: Andy99 on June 08, 2018, 07:45:23 pmIt lists version as 0x4304. I did enable external clocking and based on how the DUT functions I'd say it was doing it right. So here is the screenshot. I have it clocking on both edges of the clock line which I displayed for ease of demonstration. You can see it does appear to clock data in correctly. However at the top you can see that is shows there is only 10nS between samples. This clock is only 1.77Mhz though. So it displays timestamps as if it's sampling at 100Mhz, but it's actually only 3.54Mhz.

author: abyrvalg
author_rank: Frequent Contributor
timestamp: June 09, 2018, 07:52:47 am
content: This works as expected - the time base in extclk mode is “one (possibly variable) period of your clock”, which can be anything - like gated clock or async strobe or a signal from a button that you press randomly. For sure it is possible to add some sw-defined time base, but it will be fake for nonperiodic clocks.What is your idea how it should look?There are no timestamps from hardware, in extclk mode it just captures the next sample at selected clk edges.

author: maginnovision
author_rank: Super Contributor
timestamp: June 09, 2018, 08:03:30 pm
content: My idea would be to have the time represent real time. Even doing state analysis I'd like to have an idea of when I'm seeing while debugging problems in a large sample of data. Otherwise it's only useful for small problems due to the lack of complex triggering.

author: Andy99
author_rank: Contributor
timestamp: June 09, 2018, 08:36:13 pm
content: Quote from: maginnovision on June 09, 2018, 08:03:30 pmFrom the picture can see, that you have chosen 100MHz as sample-rate, even if extclk is used. Maybe PV is using this value for data plotting. So you can try another value from list.

author: abyrvalg
author_rank: Frequent Contributor
timestamp: June 10, 2018, 10:27:15 am
content: I't impossible to have real time reference with external clock on this hardware/firmware. When you switch to external clock it becomes the time reference for the acquisition process, no other clocks to relate it to. The big machines like TLA7xx use some other fast internal clock to timestamp the events I guess.The only (dirty) solution for 4032L is to choose a "soft" timebase close to your clock as Andy99 says. Or use internal clocking.Regarding the triggers: the firmware supports a bit more complex ones (as in original software), adding them to Sigrok is a work in progress now.

author: Andy99
author_rank: Contributor
timestamp: August 10, 2018, 06:46:56 am
content: Now the mainline version of PV has option to enter custom value of frequency when external clock mode is enabled.

author: Icchan
author_rank: Regular Contributor
timestamp: December 19, 2019, 12:43:12 am
content: The download link in the opening post is dead, has anyone uploaded it to anywhere more permanent or is it perhaps included in the Sigrok in some shape or form?

author: Andy99
author_rank: Contributor
timestamp: January 06, 2020, 11:43:05 am
content: Quote from: Icchan on December 19, 2019, 12:43:12 amWhich link you mean, github or sigrok?Github links are working and sigrok could be found herehttps://sigrok.org/wiki/Downloads.

author: Icchan
author_rank: Regular Contributor
timestamp: January 26, 2020, 10:54:44 pm
content: This link... maybe I missed something?https://nofile.io/f/tpFav7m6NZU/Hantek4032L+FPGA+Update.zip

author: tinhead
author_rank: Super Contributor
timestamp: January 29, 2020, 03:17:50 pm
content: maybe this can help?https://github.com/flowswitch/ht4032l-fw

author: Gyorgy Albert
author_rank: Contributor
timestamp: May 02, 2025, 12:08:23 pm
content: Hello everyone,It is a quite old topic, I know, but hopefully I can get some help.I have a Hantek 4032L, which I used for some relatively simple tasks. The original Hantek software is buggy, but for my previous applications it was usable. I also used the Sigrok version successfully.Now I would like to use the advanced/complex triggering functionality, and I cannot figure out how this should work. It is completely undocumented in their user manual, and my trials doesn’t have any positive results for the time delayed triggering. Of course, I wrote to Hantek, but they didn’t answered.The edge trigger and data range trigger is working. Also the so called “relative trigger“ works (when the data matches, it triggers). But I didn’t find behavioral difference between the previous/current/next settings. No difference, whatever I am selecting.But the delayed trigger doesn’t work at all. Neither in the simple trigger mode neither in the advanced/complex mode. If I activate it, the analyzer is looping forever looking for the triggering conditions which never happens. Previously I set the data range only, so it worked definitely and there is/was a match, and with the time delayed trigger there should be a time shift only.My unit has the firmware version 0x4304, so as I know it is the latest.I would really appreciate if one fellow owner, who has experience with the advanced/complex mode can enlighten me. In Sigrok it was planned to be included the advanced/complex triggering, but it seems it was not implemented till now. And I didn’t find any references about how it should work.Thanks in advance,George/Gyorgy