Trying to transfer I/Q data, from softrock digitally to a PC. - Page 1
Forum section: electronics / beginners

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: December 23, 2015, 05:35:53 pm
content: So I want to sample 500Khz of bandwidth at a time from a SoftRock Lite II, to the PC. I don't like the data limitations of a sound card as an ADC and want to see the full 80m (3.5-4.0mhz) Band to a PC. I dont really care how it gets there whether it be a USB to serial converter or something like an FX-2 hi speed USB chip. I just want to be able to sample the whole 500Khz in Quadrature and then get that in to SDR software.My issue is I dont understand the best way to do this, I see a lot of designs using FPGA's and im not quite in that realm. Im looking to use a Micro Controller and some sort of hi speed ADC. The hackRF is able to send 20mhz of I/Q data via usb without and FPGA, so I know 500khz is possible and shouldnt need the same crazy requirements as a hackRF. For example the Propeller along with FTDI chip can run at 2Mbaud would those speeds be appropriate for 500Khz of data? Im thinking something like a cypress FX-2 is overkill, I don't know 8051 cores either. Im willing to learn to use the 8051 if the FX-2 is what is required but im trying to keep it simple.My idea is to use the softrock as the tayloe front end for a portable 80M FFT/Waterfall, with a plug on the side allowing you to plug it in to the PC and sample 3.5mhz to 4.0mhz at a time with standard software including SDR#/GNU-Radio etc. The reason I chose the soft-rock is I am trying to build my first SDR and keep things simple. This project is not really about understanding Tayloe or Phasing detection or any of that stuff it is about understanding the Analog to Digital and PC pipe required by SDR's.I would like to make my own SDR using an LT5599 IQ modulator along with an Analog Devices I/Q Sampling chip or custom tayloe design, and aParallellaboard but this is a much simpler starting point.

author: Kalvin
author_rank: Super Contributor
timestamp: December 23, 2015, 06:00:29 pm
content: Just an idea: TI Launchpad with ARM Cortex M4F core, Ethernet interface and 2Ms/s 12-bit ADC. Pushing the ADC-samples to the PC using UDP protocol should be quite simple.http://www.ti.com/ww/en/launchpad/launchpads-connected.html#tabs

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: December 23, 2015, 06:21:12 pm
content: That looks like a good path... but what Im tying to understand is the speed thing is 2Ms enough and if so how do we figure that out? Same with baud rate to PC. Obviously Ethernet is a better pipe then USB 2 and will definitely work, but how do you figure out the smallest usable pipe?I guess using something like the TI board or the Parallella is actually easier, because they can both do super hi speed sampling and have high speed interfaces to the PC already there. In the case of the Paralllella you have the zynq's FPGA fabric along with the 16 core chipset which makes it perfect for a portable SDR as it can crunch some DSP, and run common Linux apps at the same time. But I guess I am trying to figure this out on a less integrated more low level basis first.Although I will be giving that TI board a look, I have only used STM32, so there will be a small curve there but that launchpad looks perfect for a TON on faster mixed signal projects.

author: Kalvin
author_rank: Super Contributor
timestamp: December 23, 2015, 06:36:51 pm
content: Sampling the 500kHz I/Q-signals require two ADCs, each sampling at least 500kHz: sampling at 1MHz per ADC is thus sufficient. Just make sure that your anti-aliasing filters provide sufficient attenuation at 1MHz and higher frequencies. That may be the challenge there. Also, the I and Q filters may not be identical and you may need to do some signal processing in order to correct the phase and amplitude differences if needed.I tried to find a Launchpad kit with a DSP, a faster ADC and an Ethernet connection but it seems that there is none (or I just missed that). Getting a faster ADC will make your anti-aliasing filter design a bit easier as you can sample using higher rate ("oversampling") and then decimate the signals for lower sample rate just before you push them to the PC.

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: December 23, 2015, 07:09:01 pm
content: Ok so here is where I get confused this is my go to ADC for most projectshttp://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdfIt is only 100ksps max, and I would guess 50ksps when used in two channel configuration. This is always enough for sensor, or voltage data etc... so how does that translate to bandwidth? Does 100kspms mean 100khz of sample data at a time? So if I were to use this ADC (this all hypothetical not a plan) I would have to pipe it I and Q which would each sample at 50ksps, but I would only truly want to sample 25ksps on each channel giving me 25khz of bandwidth to the PC? Is that right?So a 2Ms ADC will give me 1mhz of bandwidth on I and Q which is double the bandwidth needed on each channel? I then want use maybe a 3 pole lp (at 500khz or 1mhz?) on each channel to get my 500Khz I and Q, then the rest is handled by DSP via SDR software on PC. But how does this 2mhz, or 2Ms of data convert to a baud rate if I were to transfer via serial? Is a 2Mbaud connection big enough?

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: December 23, 2015, 07:18:36 pm
content: Im acually familiar with the PSoC, I see some projects using them with the softrock. I think a PSoC4 will cover the whole band at 10 bits with some oversampling, the 12 bit sar is 1Ms.

author: Howardlong
author_rank: Super Contributor
timestamp: December 23, 2015, 08:13:00 pm
content: If you use a single adc with a single sample and hold (common in MCUs), you will need to introduce a half sample delay in one of the chanels. A few MCUs have multiple adcs or multiple sample and holds. If your analog chops are up to it, you could use an all pass filter to introduce the half sample delay, but by far te preference is for dual sample and holds in front of the adc(s). Hand making your own a reasonably performing sample and hold is actually quite hard, whereas making a crap one is a piece of piss!You'll also need some form of anti alias filter: the benefit of usng audio codecs is that they have low pass FIR filters for anti aliasing already on chip leaving you needing little more than a resistor and capacitor on each channel.

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: December 23, 2015, 08:36:33 pm
content: Well I would definitely be using 2 channel ADC, the PSoC 4 line 1Ms @ 12 bits, can be split in to 16 channels. Im not sure how much speed goes up at 10 and 8 bits. I was kind of thinking a dedicated ADC chip though. I dont anticipate to many problems with hardware analog filters, I just want to figure out how to pipe the analog data in to the PC fast enough and then add support in an open driver like the ossmocom stuff. After I figure out all that I will be wingding the bandwidth and using a totally different RF front end than the soft rock whether that be a a tuner chip or a custom product detector.Like I said I just need to make sure ADC speed works the way I stated above as far as 1Ms means 1Mhz of data and how data rates relate to chuncks of analog data.Ive also been looking at thisAlinco HandHeldwith I-Q output, so this knowledge would be applicable to getting wide bandwidth out of it in to the PC. Ive been doing a lot of research on SDR and it seems like the missing link for me is how to pipe large chunk of the I-Q to the PC, and understand what the minimal speeds are for the wanted bandwidth.

author: Howardlong
author_rank: Super Contributor
timestamp: December 23, 2015, 08:39:59 pm
content: Is that two adcs or one adc with two multiplexed input channels? There's a big difference! You need to be able to simultaneously sample the I and Q channels.

author: Kalvin
author_rank: Super Contributor
timestamp: December 23, 2015, 08:42:47 pm
content: Quote from: rwgast_lowlevellogicdesin on December 23, 2015, 07:09:01 pmSampling rate: The sampling rate must be at least twice the bandwidth of the signal. For example, if your signal's bandwidth is 50kHz you have to sample it at least 100 kHz. In practice you would want to sample it at least at 150 kHz - 200 kHz because your anti-alising low-pass filter will have a finite transition band. So, if you sample at 150kHz your anti-aliasing filter should pass all the signals below 50kHz and it should have quite high attenuation at 75kHz which means that you need to have high order low-pass filter. If you sample at 200kHz, your anti-aliasing filter should pass all the signals below 50kHz and it should have quite high attenuation at 100kHz. Thus, increasing your sample rate will make constructing the anti-aliasing low-pass filter a bit easier. After sampling, you can then decimate the sampled signal in order to reduce computation requirements.When you are sampling an I/Q-signal, your sample rate has to be at least equal to the bandwidth. For example, if your I/Q-signal bandwidth is 50kHz you have to sample it at least at 50 kHz. In practice you would want to sample at least 1.5 - 2 times the minimum sample rate because of the same reasons as said above.If your ADC is 12-bits and it samples at 2Ms/s, it will produce 12 bits *2Ms/s = 24Mbits/s. Which is pretty high, but doable using 480Mbit/s USB or 100Mbit/s Ethernet.Ps. Those TI chips have two 12-bit ADCs which should be suitable for simultaneous sampling of the I and Q signals.

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: December 23, 2015, 08:50:15 pm
content: Ahhh I didn't realize that a multiplexed ADC was so much different that two ADC's like the TI chip. Bits * Sample Bandwidth thats what I was getting at, kind of what I thought but was not sure. But if your oversampling is there any reason to send all that data to the PC cant you just use the MCU to do a little bit of DSP and then send only the 500khz of samples wanted?

author: Kalvin
author_rank: Super Contributor
timestamp: December 23, 2015, 08:55:36 pm
content: Quote from: rwgast_lowlevellogicdesin on December 23, 2015, 08:50:15 pmYes, that is called decimation ie. performing an extra low-pass filtering in digital signal processing domain, and then reducing the sample rate.

author: Howardlong
author_rank: Super Contributor
timestamp: December 23, 2015, 09:01:44 pm
content: Be careful not to underestimate the effort needed in the analogue domain to make reasonable anti aliasing filters if you are expecting to extract information close to the Nyquist limit. You will need reasonably matched high order analog filters made with real parts. Silly things like choosing the right dielectric for the filter caps becomes important (eg temp coefficient).Although I don't think it'll be a problem for your application as you're probably only interested in narrow band signals, but for full band demodulation keep in mind the non-linear phase introduced by sharp anti aliasing filters.Most I/Q phase and gain mismatch can be calibrated out in software reasonably easily, as long as it's not frequency dependent.Sometimes it's just easier to oversample using simple analogue filters and then introduce the more serious filtering in the digital domain.

author: Kalvin
author_rank: Super Contributor
timestamp: December 23, 2015, 09:16:51 pm
content: You should also pay attention to ADC resolution (ie. receiver sensitivity) vs. bandwidth. When you double the bandwidth, you need one extra bit for the ADC in order to keep the receiver's sensitivity the same. For example, the receiver with a 12-bit ADC and a 500kHz bandwidth will be roughly equal to a receiver with an 8-bit ADC using 48kHz bandwidth. Or stated another way around: If you have a receiver with a 12-bit ADC and 48kHz bandwidth, its sensitivity will be reduced to an 8-bit ADC when you increase the bandwidth to 500kHz.

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: December 23, 2015, 10:19:36 pm
content: Well I would really like to do is use two single channel 16bit ADC's @ 2Ms, that would work pretty well for 500Khz as far as dynamic range and oversampling, then build the analog filters and maybe do some decimation on the mcu, to keep the data rate to PC lower. But if one chooses this path what about the pipe from the ADC to MCU, will spi even cut it here I guess spi isnt the issue as much as the MCUs capability to pipe data that fast?I guess this is where built in ADC's are useful, would running 1 PSoC4 for I and one for Q make things much harder? I mean would you be able to keep the data synced or would everything get messed up?

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: December 23, 2015, 10:30:55 pm
content: This looks good, not 16 bits but 10 is ok.. I would rather have the easiest package to work with but I cant even find a decent QFP high speed ADC.http://www.linear.com/product/LTC2286#overview

author: Howardlong
author_rank: Super Contributor
timestamp: December 23, 2015, 10:38:29 pm
content: SPI is close to a viable limit for that sample rate and bit depth. ISTR TI do a 3Msa/s SPI adc with about 14 bits of resolution.Discrete ADCs are generally parallel much above that rate.The PIC32MZ EF range have six simultaneous sampling ADCs on chip that can be interleaved if necessary. Each adc maxes out at about 3MSa/s. Don't be tempted by the earlier PIC32MZ EC, the adc on those chips is useless, check out the errata.The NXP LPC4370 has a whopping 80MSa/s adc on chip but regrettably only one sample and hold. I wrote a medium wave (AM) receiver for it, plugging the antenna into the adc input without any external hardware downconversion, the I and Q was derived in code. There's a video of it here...