CMOS Input pullup/pulldown (current drain considerations) - Page 1
Forum section: electronics / beginners

author: grantb5
author_rank: Regular Contributor
timestamp: December 13, 2017, 10:49:38 pm
content: Okay, now with pictures. Here is an SRAM that is bank-switched using a physical switch (half and half obviously). Can be SPST, SPDT whatever works. I have tossed a few resistors at it because the content needs to be saved during power down ("standby") and I want to minimize current draw. The backup battery is a coin cell.I look at any 62256 or 6264 data sheet and I get the following calculations for creating a high or low input. I haven't done this before, so I could be totally out to lunch here:Pull Down: Vil/Iil = .8v/2uA = 400kPull Up: Vih/Iih = 2.2v/2uA = 1.1Meg(* - there is no IIL or IIH in the data sheet. It just says IIL input leakage current)Note: I can't really change much in the microcontroller circuit or reset circuit, etc. The switch is moved when the main unit power is off and the SRAM is in standby.So, are these resistors going to help? Does it make sense to connect the high side of the switch to regular 5v?

author: danadak
author_rank: Super Contributor
timestamp: December 14, 2017, 01:35:17 am
content: The whole idea is for the switch to achive logic levels, andthats its internal R x leakage will not exceed the logic statetrying to be achieved. So you dont need R's.But I assume when in standby you have to terminate the inputto a valid level related to coin cell operation ? Is the 5V presentwhen coin cell is backing up ?If 5V disappears then any input switching has to be to coin cellrail. But when 5V reappears your pullup value has to go to highestrail. That can be handled with diodes.You might consider a R to ground at input, and a SPST switch frominput to + rail. R would be simple. Calc to absorb leakage and thendrop or Vin << .8 V for TTL. So switch open R pulls to ground,closed swicth pulls input to V+rail.Lastly does switch need to be debounced so a clean signal occurson input ? If sohttp://www.eng.utah.edu/~cs5780/debouncing.pdfRegards, Dana.

author: grantb5
author_rank: Regular Contributor
timestamp: December 14, 2017, 04:00:49 am
content: Thanks for the reply. First off, the switch in inside the unit and the unit will be powered down to change it from one position to the other. So, no debouncing is needed but thanks for being so thorough.Back to the big headache. The signal in the schematic marked Vbat is a diode junction of the battery and the system +5v. This powers the SRAM. So my switch (pullup) can be pulled to Vbat instead of +5v if you think that's better.* I was just worried that when the unit is off the Vbat signal might drain somehow through the A14 line via the switch to ground or the other way to Vbat or +5v, whatever I used. I'm really confused here.GB* - The reason I reached for +5v instead of Vbat is that when looking at the bigger circuit, all the other address lines come from an 8031 type CPU. When powered down, the CPU is off too (it's powered by +5v that is 0v in the powered down state). This is where I'm confused. All the other address lines on that SRAM will be low because the CPU is off. So the SRAM is in standby but A0 to A13 are low. During this time my A14 will be low if the switch is low. Or if the switch is high it can be high if I use Vbat or low if I use +5vDC.

author: danadak
author_rank: Super Contributor
timestamp: December 14, 2017, 10:44:27 am
content: QuoteAre you sure that the 8051 that is off states clearly in datasheet that its outputsare driving low ? "Normally" that would imply the output state is undefined, HiZ, andonly pulldowns would guarantee that.Yes on pull to Vbat.Regards, Dana.

author: grantb5
author_rank: Regular Contributor
timestamp: December 14, 2017, 02:12:28 pm
content: Thanks again for your input and sorry, I didn't mean "driving" low. I just meant that with all the decoding circuitry, EPROM, I/O etc that is connected to it, when the mains power is off, the address lines are low. So when off, everything is off except the CMOS SRAM since it's powered by VBAT. And that device is in standby (a small transistor circuit keeps it's chip select not selected).And just to make it clear in my mind, you are saying directly to Vbat? No need for a pullup?

author: danadak
author_rank: Super Contributor
timestamp: December 14, 2017, 02:26:11 pm
content: Vbat > Switch > R > Gnd, junction of R and Switch to address input.Rpulldown <= .8V ? Ileakage. .8V used if input TTL, if CMOS use datasheetfor logic zero input definition, worst case Vdd (Vbat).Regards, Dana.

author: grantb5
author_rank: Regular Contributor
timestamp: December 17, 2017, 05:11:57 pm
content: Quote from: danadak on December 14, 2017, 02:26:11 pmThanks again for your input. Are you thinking a SPDT on the address input so that it switches between straight Vbat on one side and on the other to the resistor-to-ground? If I use SPST then in one position the VBat will always drain through the resistor 24 hours a day (when the unit is off).Code:.-------U-------.VBAT--.----------| Vcc || | || || || | SRAM| || SPDT |/--------| Axx (highest addr line)| || |< |< R |< |||=== GND=

author: SeanB
author_rank: Super Contributor
timestamp: December 17, 2017, 08:00:16 pm
content: I would be more worried about /cs being pulled low during no power, and overwriting a random location or ))H when power is off, or permanently selecting the RAM and keeping it in a high power state. You need to have an open collector /cs, with a pull up resistor to Vbatt ( around 1k will be fine if the battery is float charged during operation) or you will need to add a separate CMOS NAND gate to the circuit to have the chip selects disabled when Vcc is low and thus power is off. Otherwise use a Maxim power watchdog chip, which has both the logic, gating and battery switching plus a input for a second backup battery all in one simple chip. there even is a socket that has this chip integrated into it along with the battery as well, look for the ramified socket, used to be made by Dallas Semiconductor.

author: grantb5
author_rank: Regular Contributor
timestamp: December 17, 2017, 08:06:53 pm
content: Thanks. This is a retrofit into an existing unit. All that you describe has been handled already and has worked well for 30-something years I guess. It's an electronic musical instrument from the 80's. I'm just trying to expand/bank the SRAM via a switch. The unit can be powered off when the switch-over occurs. So really all I want to do is minimize affects on the battery (3v coin cell, not rechargeable).