Power ON sequence for CPU - Page 1
Forum section: electronics / beginners

author: Jane
author_rank: Frequent Contributor
timestamp: October 26, 2020, 09:18:57 pm
content: Voltage Power ON sequence is needed for CPU to start. I can measure the voltages according to the Power ON Sequence diagram that I enclosed .But if there is one voltage present does it mean thatall previousvoltages must be also present?E.g. If there is VREG_S2 present must there be also VREG_S7,GPIO4 (MODE for BBYP and VREG_S4 ?Or must I measure all voltages to check if there are present?

author: ledtester
author_rank: Super Contributor
timestamp: October 27, 2020, 02:33:42 am
content: My guess is that a proper power up sequence will bring up the voltages in the order and with the lifetimes indicated by the chart.Therefore, if VREG_S2 is present you may assume that the earlier voltages are also present.On the flip side, if you are responsible for the power up sequence you should not bring up VREG_S2 until the previous voltages have been established.Note that on shutdown the BBCLK1 signal continues operation until VREG_L5 is shut down. I read this as a guarantee that the BBCLK1 signal will continue operation even when rails such as VREG_L11, VREG_L12, etc. are shut down.

author: perieanuo
author_rank: Frequent Contributor
timestamp: October 27, 2020, 08:03:37 am
content: hi,just keep reset pin enough activated and put the filtering caps according to uC/dsp datasheet. and carefully examine the quartz implementationoverthinking this matter is not worth the time. you'll need to validate/debug the pcb anyway.regards, pierre

author: fourtytwo42
author_rank: Super Contributor
timestamp: October 27, 2020, 09:50:30 am
content: Looks horrible to me, I would avoid using a chip with such a pedantic spec if possible (what is it ?).Otherwise use Schottky diodes between rails to ensure against poor sequencing and lower voltage rails powered by LDO's etc from higher ones, this is normally sufficient for most sensibly specified chips

author: Siwastaja
author_rank: Super Contributor
timestamp: October 27, 2020, 09:59:54 am
content: It sometimes happen that an overly autistic engineer is left loose to describe whatever they want, "just in case", in datasheet. They don't always understand the consequences for the buyer of said chip.In such cases, the designer needs to be practical; being pedantic often prevents the usage of such chip at all, or totally blows the design BOM and time-to-market, if such power sequencing requirements are followed.This is no different to those cases where the min/max values given in analog ICs prevent the IC to be used at all, for any purpose, if the designer tries to be pedantic. Some switch mode converter IC comes into mind with bootstrap UVLO minimum guaranteed value being clearly below the required Vg to turn on theintergratedMOSFET for reliable Rds_on required for even nearly the rated current; i.e., it can't be used at all following the specs!Often, the only sensible choice is to decide using the chip outside the specified ratings, and test if it works. This always carries a risk; designing overly complex power sequencing electronics likely carries a bigger risk, though. Using another product is sometimes, but not always possible, and sometimes an IC with some ridiculous datasheet farce can beotherwisevery good and would be such waste to use some other, possibly inferior part, if the poor parts of the datasheet can be just ignored (of course, taking an informed risk while doing so).If the manufacturer has some recommended typical power control IC which generates all those voltages with proper sequencies, use it. Ask them about it. If they don't understand what you are talking about, the chances are, no one is following said specification. One good source of actual information is see how they did it themselves with the evaluation board (which hopefully exists).

author: BBBbbb
author_rank: Unknown
timestamp: October 27, 2020, 12:25:15 pm
content: Nice diagram, but based on a quick glance you don't need to power up everything (e.g. VREG_L11 if you're not using SD/MMC). Second BBCLK1 is basically limited by the settling time of the OCX from the moment you turn on VREG_L5, not by the in between sequence of powerup.What you need and don't need, you'd probably need to go through the datasheet and you're project specifics, and do an according powerup sequence in your code. The graph could be a guide or maybe a specific sequence that comes within vendor's code.But if you're testing, general answer would be - absolutely no guarantee that if one of the "later" voltages is present , previous one is present as well.To know that for sure for a specific case you'd have to dig deeper in the data sheet and see if some voltage is a functional precondition for the measured one, and/or the powerup sequence (in code) aborts if one fails...

author: m k
author_rank: Super Contributor
timestamp: October 27, 2020, 01:56:36 pm
content: Quote from: Jane on October 26, 2020, 09:18:57 pmWithout much thinking about functions of those signals I read it so that internal signals or outputs will be available in that order and inputs or external ones start being meninful.So +1 for ledtester.

author: Jane
author_rank: Frequent Contributor
timestamp: October 27, 2020, 06:12:49 pm
content: Thank you for replies and explanation, particularlly big thanks to ledtester