usb verilog softcore questions - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: August 07, 2020, 02:17:12 am
content: 1. For this usb implementation :https://github.com/avakar/usbcorev/, could anyone explain why thetwo variables belowactually transmit some "state machine status"-related data ??Code:assign tx_j = j;assign tx_se0 = se0;2. May I know ifhttps://github.com/osresearch/up5k/tree/master/usbis just a USB controller code OR USB-to-UART code ? Besides, I do not see any formal or simulation testbench.

author: ataradov
author_rank: Super Contributor
timestamp: August 07, 2020, 02:31:31 am
content: 1. They are outputs from this module indicating when top level needs to set J or SE0 state on the bus. I'm not sure what do you mean by "why". That's part of the USB logic. In some states you need to set specific values on the bus.2. usb_uart is a top module. It has raw USB DP/DM pins on one end and UART RX/TX data on the other end.

author: promach
author_rank: Frequent Contributor
timestamp: August 07, 2020, 08:41:32 am
content: When I try to write a testbench for the up5k usb_uart coding, Why do I have so many declaration errors ??Quoteusb_tb.vCode:module usb_tb();reg clk, clk_48mhz;reg reset;wire pin_usbp, pin_usbn;wire pin_pu;wire [7:0] rx_data;wire rx_strobe;reg [7:0] tx_data;reg tx_strobe;assign pin_usbp = tx_strobe ? tx_data : 1'bz;assign pin_usbn = tx_strobe ? !tx_data : 1'bz;usb_uart dut(.clk(clk),.clk_48mhz(clk_48mhz),.reset(reset),.pin_usbp(pin_usbp),.pin_usbn(pin_usbn),.pin_pu(pin_pu),.rx_data(rx_data),.rx_strobe(rx_strobe),.tx_data(tx_data),.tx_strobe(tx_strobe))initial begin$dumpfile("usb_tb.vcd");$dumpvars(1);endinitialbeginclk = 0;clk_48mhz = 0;reset = 0;tx_data = 0;tx_strobe = 1;@(posedge clk);tx_data = 1;@(posedge clk);tx_data = 2;@(posedge clk);tx_data = 3;#50 $finish;endalways #5 clk = ! clk;always #10 clk_48mhz = ! clk_48mhz;endmodule

author: ataradov
author_rank: Super Contributor
timestamp: August 07, 2020, 04:44:39 pm
content: The multiple declarations is because they are using includes all over the place, so you only need to specify one top file to the iverilog, it will pick up the rest of the files though includes.In your TB this part:Code:assign pin_usbp = tx_strobe ? tx_data : 1'bz;assign pin_usbn = tx_strobe ? !tx_data : 1'bz;is nonsense. tx_strobe is the UART signals and tx_data is 8-bit parallel signal.pin_usbp and pin_usbn are already direct connections to the USB pins.You also don't have semicolon after the module instantiation.

author: promach
author_rank: Frequent Contributor
timestamp: August 07, 2020, 05:26:18 pm
content: Quotefrom the quoted output above, it seems that I still have the same error even with a single instance of "../util.v"I have added a semicolon after the dut module instantiation.How would you handle an "inout" signal inside verilog testbench since both "pin_usbp" and "pin_usbn" are "inout" signals ?

author: ataradov
author_rank: Super Contributor
timestamp: August 07, 2020, 05:46:51 pm
content: The errors in util.v may be related to limitations of iverilog. You may need to rewrite relevant code in a compatible way. You may need to just move this function inside every module that uses it.Bidirectional signals are not easy to work with. It is much easier to look at what signal controls the direction of the pin inside the hierarchy and use that.But also, are you really going to simulate the whole behaviour of the host controller? This is not trivial at all.

author: promach
author_rank: Frequent Contributor
timestamp: August 08, 2020, 03:17:19 am
content: QuoteI do not understand why "vvp" stops forever at simulation time tick of 0th clock tick ??usb_tb.v: simulation testbenchCode:module usb_tb();reg clk, clk_48mhz;reg reset;wire pin_usbp, pin_usbn;wire pin_pu;wire [7:0] rx_data;wire rx_strobe;reg [7:0] tx_data;reg tx_strobe;assign pin_usbp = tx_strobe ? tx_data : 1'bz;assign pin_usbn = tx_strobe ? !tx_data : 1'bz;usb_uart dut(.clk(clk),.clk_48mhz(clk_48mhz),.reset(reset),.pin_usbp(pin_usbp),.pin_usbn(pin_usbn),.pin_pu(pin_pu),.rx_data(rx_data),.rx_strobe(rx_strobe),.tx_data(tx_data),.tx_strobe(tx_strobe));initial begin$dumpfile("usb_tb.vcd");$dumpvars(1);endinitialbeginclk = 0;clk_48mhz = 0;reset = 0;tx_data = 0;tx_strobe = 1;@(posedge clk);tx_data = 1;@(posedge clk);tx_data = 2;@(posedge clk);tx_data = 3;#50 $finish;endalways #5 clk = !clk;always #10 clk_48mhz = !clk_48mhz;endmodule

author: ataradov
author_rank: Super Contributor
timestamp: August 08, 2020, 03:23:00 am
content: Your TB still makes no sense.But also may need something like "`timescale 1ns / 1ps" at the beginning of a file.

author: promach
author_rank: Frequent Contributor
timestamp: August 08, 2020, 07:57:42 am
content: Seehttps://github.com/osresearch/up5k/issues/1

author: ataradov
author_rank: Super Contributor
timestamp: August 08, 2020, 08:02:57 am
content: Your TB still makes no sense. Why are you insisting on this stuff:Code:assign pin_usbp = pin_pu ? tx_strobe : rx_strobe;assign pin_usbn = pin_pu ? ~tx_strobe : ~rx_strobe;Why are you connecting serial side signals to the USB pins?

author: promach
author_rank: Frequent Contributor
timestamp: August 08, 2020, 09:52:24 am
content: How should I handle the testbench stimulus for these 2 usb signals ?Generate real-time usb signals using libusb software library ?Code:inout pin_usbp,inout pin_usbn,

author: ataradov
author_rank: Super Contributor
timestamp: August 08, 2020, 06:08:12 pm
content: Yes, you need to implement a hot part of the USB specification. It is not trivial at all, even if just for simulation. It is really not worth it.For your test right now try to not connect them at all. There may be some loops because of the way you are doing it, and vvp may get confused.

author: promach
author_rank: Frequent Contributor
timestamp: August 09, 2020, 01:40:14 am
content: QuoteWhat can I do to get past "vvp" if I do not generate USB traffic stimulus for the simulation testbench ?

author: ataradov
author_rank: Super Contributor
timestamp: August 09, 2020, 01:42:02 am
content: Assume that the USB core works correctly and only simulate your part working with the serial interface. Basically make a dummy IP with just the serial interface and control that from the TB avoiding the whole USB simulation.What do you want from that simulation? If you want to see how the core works internally, then there is no way to avoid simulating the host.

author: promach
author_rank: Frequent Contributor
timestamp: August 09, 2020, 08:34:33 am
content: QuoteWhat do you exactly mean by "dummy IP with just the serial interface" ?I suppose I still need to handle "pin_usbp" and "pin_usbn" ?One other issue is a failedtiming analysiswith the original code

author: ataradov
author_rank: Super Contributor
timestamp: August 09, 2020, 08:41:11 am
content: Again, what is your goal with this simulation? If you want to debug the core itself, then the only option is to create a corresponding host model (at least behavioral).Otherwise, if you just want to test your own logic that uses this USB IP, just create a block that only has rx_data, rx_strobe, tx_data and tx_strobe. This is enough to test integration of the USB IP with your system.Open source tools for ice40 known to suck at timing. They don't really have a way to input any timing constraints and optimize the design for that. So your only hope is to run it with different seeds and hope that one of the random placements ends up being good enough.

author: promach
author_rank: Frequent Contributor
timestamp: August 10, 2020, 08:03:16 am
content: How exactly isthis testbenchused in a loopback manner ?

author: ataradov
author_rank: Super Contributor
timestamp: August 10, 2020, 08:09:20 am
content: This is not a test bench. It is still a code that describes a loopback on the serial side. So any characters you type into the COM-port will be sent back to the same port.This still needs USB connection and run on a real hardware.

author: promach
author_rank: Frequent Contributor
timestamp: August 12, 2020, 07:25:31 am
content: Who have a real-time captured USB2.0 (D+ and D-) waveform in vcd format ?

author: ataradov
author_rank: Super Contributor
timestamp: August 12, 2020, 07:36:49 am
content: What do you want to do with is? A simple capture will not help a lot for a test bench. USB protocol is reasonably complicated that you need to actively react to the bust state, not just playback pre-recorded signals.This site has a reasonably good explanation of the signalling on the bus and token and packet formatshttp://www.usbmadesimple.co.uk/ums_3.htm(all parts are a good read, not just this one).I'm not aware of any pre-recorded log files that would show full transactions.

author: promach
author_rank: Frequent Contributor
timestamp: August 13, 2020, 08:51:44 am
content: QuoteI can usethese sigrok-compatible log signals filesHowever, analyzing the following decoded USB signals would really take some time.

author: ataradov
author_rank: Super Contributor
timestamp: August 13, 2020, 04:40:51 pm
content: Well, yes, as I said making a test bench for the USB host is not a trivial task. It is probably comparable in complexity to making the USB device core itself.The only thing that makes it simpler is that TB does not need to be synthesizeable. But in reality it is not much.