Routing Hyperram :( - Page 1
Forum section: electronics / projects

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: July 10, 2023, 08:59:36 pm
content: So I'm trying to put together an STM32H7B0 (280MHz CPU, fast GPIO, but minimal flash) with a couple of hyperbus parts (one flash, one RAM). I've been reading the recommendationsfrom Infineonabout their parts and it has a nice layout where everything stays on the top-layer and all is sweetness and light.ST, not so much...One of Infineon's recommendations is that CK and CK# differ in length by +/- 10 mils - which is about one of the squares on that image, but CK# and CK are on different sides of the chip! Couple that with data lines that criss-cross and ... yeah.So I do have layers. The Infineon recommendations are that if you use vias on any DQ* line, use them on all the DQ* lines. I could see this working if I use different layers handle the criss-crossing of signals and avoid routing DQ* on the top layer at all. Before I dive into doing that, anyone got any better ideas ?Full transparency - there are other balls for some of these signals, and it may be possible to get them closer together, but if you want to use the LTDC and SDMMC as well, this seems to severely restrict the layout.

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: July 11, 2023, 05:17:30 am
content: Replying to myself. I'm not mad, honest. It's just the voices...Aaanyway. Doing it by always having one transition to a single inner layer and back (always the same layer) seems to be my best shot. I don't think the routing looks particularly pretty, but it doesn't look terrible either, to my unpractised eye. I think I've managed to hit the signal length constraints:All the DQs and RWDS are within 6 mil of each otherCK and CK# are routed differentially and are within 3 mils of each other and in the same range to the DQ'sCS# and RESET# are easily in spec.and the signal-separation recommendations - well, wherever the reality of a forest of BGA balls doesn't trump things, anyway. On to the next one...

author: ArdWar
author_rank: Frequent Contributor
timestamp: July 11, 2023, 05:25:11 am
content: Looking at a glance I think it's meant to be routed the other way around. Granted ST isn't exactly the most logical with their pin placement.

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: July 11, 2023, 05:35:13 am
content: I actually rotated it 90 degrees in the latest incarnation. It’s still not possible to get everything on the top layer, but that could be a compromise from the usage of the ST chip - there’s only 5 pins not being used from 176. As I said, it’s not terrible, it’s just that other manufacturers seem to make a bit more effort to make life easier.

author: Berni
author_rank: Super Contributor
timestamp: July 11, 2023, 06:01:23 am
content: Yeah ST always tends to use nonsense pinputs on STMsAt least you got your pins on the same side of the chip. I had chips where the memory buses data and address lines ware spread across 3 sides of the chip, all mixed up with no particular order. Even after swapping around the bits on the bus (For some RAM chips you can do that) to make routing easier it was still a huge mess.The one STM that has sensible RAM pinout is the new linux capable MP1 since it has DDR3 memory and there are dedicated pins for it on one side of the chip (They can't even be used as GPIO)