Intel replaces their NIOS II soft core in their FPGAs with 5x faster NIOS V RISC - Page 1
Forum section: electronics / general

author: brucehoult
author_rank: Super Contributor
timestamp: October 04, 2021, 10:21:32 pm
content: RV32IA. 5 stage pipeline.Nios II/e: 0.107 DMIPS/MHz, 400 MHz FmaxNios V/m: 0.462 DMIPS/MHz, 566 MHz FmaxBoth on the same Intel Agilex FPGANios V/g applications processor soft core (i.e. Linux capable) coming later.No mention of the relative resource usage. Maybe the II/e is a lot smaller?You've of course been able to use open source RISC-V soft cores for several years. Vexriscv is a popular one which has several configurations, all faster than the 0.462 DMIPS/MHz quoted for Nios V/m (figures for Cyclone V):352 ALMs: 0.52 DMIPS/MHz RV32I492 ALMs: 0.82 DMIPS/MHz add datapath bypass933 ALMs: 1.21 DMIPS/MHz add single-cycle barrel shifter and debug and M extension.https://www.intel.com/content/www/us/en/products/details/fpga/nios-processor/v.html

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: October 04, 2021, 10:50:13 pm
content: Is there any open soft core which is optimized to target Xilinx 6-input lut and 18 bit memory?

author: srce
author_rank: Regular Contributor
timestamp: October 04, 2021, 10:53:39 pm
content: Shouldn't the comparison be with nios ii/f?

author: brucehoult
author_rank: Super Contributor
timestamp: October 04, 2021, 11:07:38 pm
content: Quote from: chickenHeadKnob on October 04, 2021, 10:50:13 pmOptimised for what? Size? Speed? Speed/resources?Vexriscv is hard to beat for speed/resources at a variety of trade-off points. I mentioned just a few of them. SeRV is optimised for tiny size at the expense of speed (it is bit-serial).

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 04, 2021, 11:40:29 pm
content: I don't know those Agilex FPGAs yet... those Fmax seem very impressive.In terms of performance, yes, speaking of Vexriscv, the 0.462 DMIPS/MHz figure is lower than that of the VexRiscv in the smallest configuration (0.52 DMIPS/Mhz). I don't know what Fmax it would reach on the Agilex. But the NIOS V doesn't seem all that impressive. Sure it's much better than the Nios II, which is not surprising...I'm pretty sure Intel won't be the only one making the switch to RISC-V for soft cores. The days of every vendor having their own soft processors are probably counted.

author: brucehoult
author_rank: Super Contributor
timestamp: October 04, 2021, 11:45:55 pm
content: The news here is of course Intel supporting RISC-V and it no doubt integrating nicely with their design tools and other IP.Microsemi started offering supported RISC-V soft cores in their FPGAs several years ago, and started shipping FPGAs with 600+ MHz RISC-V 64 bit hard cores about 12 months ago.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 04, 2021, 11:46:20 pm
content: Quote from: brucehoult on October 04, 2021, 11:07:38 pmYeah. Xilinx has the Microblaze soft core, which you would think was "optimized" for the Xilinx architecture. To answer chickenHeadKnob's question, if it can be answered.That said, it's very possible that a simple RISC-V soft core would both take up less FPGA resource and reach higher Fmax on a given Xilinx FPGA series.As I just said above... I'm curious what the other vendors will do. Both Xilinx and Lattice have their own soft cores (Microblaze and LatticeMico), will they switch to RISC-V? (At this point, I actually doubt that they would not.)

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: October 05, 2021, 12:59:34 am
content: Quote from: brucehoult on October 04, 2021, 11:07:38 pmOver all I have not been too interested in soft cores because a better choice is to lash an external microcontroller known to me to the fpga. However just recently I have been comparing J1a stack machine mecrisp-ice which people have running on various Lattice ice chips to the pico-blaze official Xilinx 8 bit core. I like some features of the J1a. Particularly the 16 bit arithmetic and small verilog specification, and imagine how it could be customized to run on older spartan 6 fpga's to compete with picoblaze. Mostly I have been playing with changing the instruction word size to 18 bits and adding instructions+ 4 registers. My question was prompted by noticing picoblaze is well suited for spartan 6 min-resource not speed. At the same time the ISA is not that appealing.Back in ye olden days the IBM360/370 machines had something called I/O channel processors, which if I recall correctly were simply glorified DMA controllers and they fell short of being Turing complete. They would function to reduce the interrupt load and serve up complete packets or filled buffers to the main processor.I can see the same utility as being useful in an fpga that passes whole buffers to an external mcu via spi but with more flexibility than those I/O channel processors. So the application area I am interested in are lowest resource consumption giving a softcore that is pleasant to code in assembly. No high level language needed.I did look at Claire (nee Clifford) Wolf's picoRV32 but came away feeling that any Risc V implementation would be overkill for what I wanted. I don't need 32 bit arithmetic or registers. Also the load/store model of any risc processor doesn't really match the application. I want to take advantage of as much parallelism as is feasible on a small fpga by accessing bram blocks on independent buses and don't require external memory at all. The J1a doesn't fit the application exactly either but it is so small and malleable it attracts me.picoRV32:https://github.com/cliffordwolf/picorv32mecrisp-ice:https://github.com/zuloloxi/mecrisp-icemecrisp-ice-upduino:https://github.com/igor-m/UPduino-Mecrisp-Ice-15kB

author: hamster_nz
author_rank: Super Contributor
timestamp: October 06, 2021, 10:05:37 pm
content: Quote from: chickenHeadKnob on October 04, 2021, 10:50:13 pmA 6-input LUT (well, the underlying 1x32bit dual-ported RAM block) maps nicely to the RV32I register file requirements. Of course this is all out the window if you have register renaming and so on.Optimizing for block memory resources is more about right-sizing caches and so on.

author: brucehoult
author_rank: Super Contributor
timestamp: October 06, 2021, 10:41:03 pm
content: Quote from: hamster_nz on October 06, 2021, 10:05:37 pmA small VexRISCV configuration gets 0.52 DMIPS/MHz (10% higher than Nios V/m) not only without register renaming, but without datapath bypass (so it stalls if one instruction uses the result of the previous one), with a 1 bit per cycle shifter, without multiply or divide, without branch prediction, without return address cache.Doing all the above except register renaming and OoO gets you to 1.6 DMIPS/MHz (1.7 for 64 bit) (e.g. FE310 or K210 or FU540). Longan Nano is 1.4 -- pretty close.