A circuit to clean up a noisy zero crossing detection output - Page 1
Forum section: electronics / projects

author: Etesla
author_rank: Regular Contributor
timestamp: June 27, 2019, 06:14:59 pm
content: Here's the situation. I have a high speed comparator (LT1713) with the negative input tied to ground, the positive input tied to a 300 mV pk - pk sin wave at 150 khz, and the rails at +- 5V. It is for zero crossing detection on the sin wave. Ideally, this would provide me with a 50% square wave at 150 khz on the output of the comparator. Due to noise, bad grounding, and my own incompetence, however, the output of the comparator has many edges where there should only be one. I decided that to solve this problem, I would add some sort of noise immunity circuit after the comparator. The circuit I am imagining is sort of like a 'you are only allowed to change states after you have already been in one state for 'X' microseconds'. I want it to react to the 'first' rising edge it sees, as well as the 'first' falling edge. I imagine this sort of a timed hysteresis circuit should be fairly common, but my research has given me nothing so far. Anyone know what sort of circuit has this functionality?Here's a picture in case my words didn't work:

author: ejeffrey
author_rank: Super Contributor
timestamp: June 27, 2019, 06:21:22 pm
content: The normal way to do this is a Schmitt trigger. Just a resistor from the output to the positive input to add a bit of hysteresis. It is just voltage based not time based.

author: Etesla
author_rank: Regular Contributor
timestamp: June 27, 2019, 06:25:57 pm
content: Right, but doing that in a way that effectively cleans up my signal would also add a delay. I need the final output to switch on exactly the FIRST instance of the sin wave going above 0V, and the FIRST instance of the sin wave going below 0V...

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 27, 2019, 06:31:35 pm
content: You could clean that up digitally by just ignoring transitions that are shorter than a given amount of time (depending on your application). Akin to debouncing.

author: Marco
author_rank: Super Contributor
timestamp: June 27, 2019, 06:42:09 pm
content: Usedynamic hysteresis, ie. use a capacitor instead of a resistor to feedback Q to the positive input. It will prevent the output oscillation, but it won't change the trigger point (assuming the RC time is << 1/f).Of course the noise will still cause jitter ...

author: Etesla
author_rank: Regular Contributor
timestamp: June 27, 2019, 06:57:08 pm
content: Marco, you got it. I just figured this out in LTspice, glad to know it has a name. Thank you so much, to me its the perfect solution because I don't need to do another revision on the PCBJust in case anyone finds this thread, heres the LTspice file I was messing with if anyone wants to probe it out

author: David Hess
author_rank: Super Contributor
timestamp: June 28, 2019, 08:09:35 am
content: Another trick I might use is that since the result should be a square wave with 50% duty cycle, adjust the comparator's reference (common) to make it so by comparing the average of the output to what its median value should be and adjusting the comparison voltage. This would be combined with AC hysteresis.

author: pardo-bsso
author_rank: Frequent Contributor
timestamp: June 29, 2019, 01:32:41 pm
content: This also:https://www.edn.com/design/power-management/4410475/A-circuit-for-mains-synchronization-has-two-separate-outputs-for-each-half-period

author: joeqsmith
author_rank: Super Contributor
timestamp: June 29, 2019, 04:33:00 pm
content: Been there.There are some pretty good papers on this subject if you use Google search. Here are a few.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 29, 2019, 10:46:49 pm
content: You're asking the wrong question in part; which makes this an X-Y problem, but in a conveniently short form (most likely).Namely-- you're getting digital noise, because your analog input is noisy (or the comparator is unstable for a variety of reasons). Why not filter that first?It is avery good ideato useonly as much bandwidth as you need.This doesn't mean you need filters at every single stage of your system; for any given chain of stages (say of amplifiers), it's okay to filter...usually the input, but the output may need filtering due to noise picked up in those stages.What delineates a "chain of stages" is, when they're linear. This is a required assumption: ignoring noise, any combination of linear stages and filters can be placed in any order, with no effect on the overall response.Where you need a nonlinear function (like a radio mixer, or a digital converter like a comparator or ADC), that assumption is broken, and filtering matters more. In addition to separating signal and noise, there are harmonics and IMD and reflections and whatnot that nonlinear stages are prone to generate, which you may need to filter out between functions.So, that's a very high level setup, but it simplifies in your case down to simply, whatever the input circuit is (filtering, limiting/protection, buffering, amplification), whatever it's attached to (the comparator), and wherever that goes (what's the digital signal being used for, how much time delay can it tolerate, etc.).You can indeed make a timed-lockout comparator; more generally, you can make a variety of digital filters, which can to some extent patch up noise like you see here. But it's not a good general approach, because in the digital domain you have no idea whether the input is noise around zero crossing and therefore should be ignored, or if it's actually the signal going bonkers and you should probably respond to it somehow! Those are factors that you really need to handle in the analog domain, or at least with more digital bits, or a much higher sample rate and dithering.A typical solution is sampling the digital value periodically, incrementing or decrementing an accumulator with saturating arithmetic, and setting the final output only when the accumulator value is above or below a threshold. That is (in C),Code:#define MAXVAL 7#define RISING_THRESHOLD 5#define FALLING_THRESHOLD 2...bool input, output = 0;int accum = 0;...// input is 0 or 1 (limit or mask accordingly)accum += input * 2 - 1;if (accum < 0) accum = 0; else if (accum > MAXVAL) accum = MAXVAL;if (accum > RISING_THRESHOLD) output = 1; else if (accum <= FALLING_THRESHOLD) output = 0;Note that this has a delay of RISING_THRESHOLD samples going up and MAXVAL - FALLING_THRESHOLD going down, with hysteresis of RISING_THRESHOLD - FALLING_THRESHOLD.The implementation of this in logic is better (just throw it in a few FPGA cells), and doesn't cost any CPU cycles to compute of course. Wouldn't recommend making it in discrete logic; the analog timed version (digital input as constant current charging a capacitor; window comparator and flip-flop sets output) will be easier.As for what you originally asked for (a timed holdoff) -- that can be made in very much the same way. You want to, let's see (excuse me as I synthesize on the fly) -- probably an R-S f/f for output, and R/S pulses are generated when the input and output differ in state, but masked by an AND gate tied to a monostable.Or for an analog solution, you could have some maximum input rise/fall time requirement, then detect the current flowing through an analog switch; the current is rectified so a trigger is generated for either polarity. The switch feeds a small capacitor, so when the input changes state, a current pulse is drawn, and this triggers a timer which controls the switch. So the switch opens and the capacitor retains state while the timer runs. Downside: the output oscillates at (2/delay) frequency if the input is chattering at the moment the timer runs out.Tim