Missing row labels in BGA package datasheets? Why? - Page 1
Forum section: electronics / general

author: MarkS
author_rank: Unknown
timestamp: February 04, 2017, 05:59:12 pm
content: I'm working on a GUI-based utility to speed up the creation of complex parts in KiCAD (I am aware of KiPart, hence the "GUI-based"). Anyway, I downloaded the largest BGA datasheet I could find for eventual testing. I found a Xilinx UltraScale FPGA with 2892 balls. What I noticed is that on the row/column grid, the labels 'I', 'O', 'Q', 'S', 'X' and 'Y' are missing and this also goes for when the labels double, so, for example, 'AO' is missing. Checking other datasheets for other parts from other manufacturers turns up the same results.What I need to know is why this is, and if it is a standard, can I be directed to said standard? Is there ever a time where this will not be the case? I wasn't expecting this and it will complicate GUI creation a bit. I need to make absolutely sure that the GUI will match any datasheet on this issue.

author: dmills
author_rank: Super Contributor
timestamp: February 04, 2017, 06:23:08 pm
content: Same reason car number plates don't use the letters I,O,Q.... Far too easy to mistake them for numbers.I would assume this is a JEDEC standard, but do not know which one.Note that BGA packages with some balls missing are very much a thing, look at DDR memory packages for examples of this particular source of 'fun', you will need to support this.73 Dan.

author: Cubdriver
author_rank: Unknown
timestamp: February 04, 2017, 06:26:14 pm
content: I don't know if it's a standard, but would guess that I, O, Q and S are not used because they're too similar in shape to 1, 0, 0 and 5, respectively, and could be misread. X and Y perhaps because they're commonly used for axis labels and/or variables.-Pat

author: MarkS
author_rank: Unknown
timestamp: February 04, 2017, 06:27:34 pm
content: Quote from: dmills on February 04, 2017, 06:23:08 pmQuote from: Cubdriver on February 04, 2017, 06:26:14 pmThat makes sense.Quote from: dmills on February 04, 2017, 06:23:08 pmMost definitely. I was aware of this and am planning on a way for the user to quickly select and discard missing balls/pins/pads (whatever).

author: MarkS
author_rank: Unknown
timestamp: February 05, 2017, 07:02:48 pm
content: One more question. With SIP, DIP and quad packages everything is referred to as a "pin". Does this naming convention still apply to ball grid, pin grid and land grid array packages? Is the grid position "J5" referred to as pin "J5" or ball/pin/pad/land "J5"?

author: Sehyung
author_rank: Newbie
timestamp: January 29, 2021, 01:55:28 pm
content: I had a same question and found JEDEC standard that describe the conventions and leave here for anyone who had the same curiosity.https://www.jedec.org/sites/default/files/docs/SPP-010.pdf

author: gnuarm
author_rank: Super Contributor
timestamp: January 29, 2021, 08:56:12 pm
content: Quote from: MarkS on February 05, 2017, 07:02:48 pmYour tool is not defining the part, it is defining a footprint, no? I would call them pads.Is the tool going to provide any breakout assistance? I am new to KiCAD, so I'm not familiar with how breakout could be improved or facilitated. One of my issues with my current layout tool is FPGAs are happy to allow pin swapping. But if you route a signal from both ends to find it is easier to swap two pins (or more), make the changes in schematic and import it to the layout tool and the traces are ripped up so you have to start those routes over. If the breakout was somehow part of the footprint this might be more simple.

author: gnuarm
author_rank: Super Contributor
timestamp: January 29, 2021, 08:57:03 pm
content: Quote from: Sehyung on January 29, 2021, 01:55:28 pmCan you provide your login information?

author: nctnico
author_rank: Super Contributor
timestamp: January 29, 2021, 09:13:25 pm
content: Quote from: gnuarm on January 29, 2021, 08:56:12 pmI don't think it is a good idea to make the breakout part of the footprint. First the size of the via is determined by what the PCB manufacturer can produce. Some like a bigger anular ring, others like a larger hole. Second if a pin isn't connected a via just takes space which can be put to better use. The CAD tool I use links a BGA breakout to the part at the design stage of the board.

author: amyk
author_rank: Super Contributor
timestamp: January 30, 2021, 05:33:58 am
content: Quote from: MarkS on February 05, 2017, 07:02:48 pmWith a PGA they are obviously still pins, but with BGA and LGA, not so much --- if you really want to be generic, call it a contact.