Question on DDS chips. Specifically AD9833 - Page 1
Forum section: electronics / projects

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: November 25, 2015, 09:30:30 pm
content: I have a few AD9833 chips laying around and I need some sign waves...Data SheetIm a bit hazzy on the reference clock and how it effects the DDS, it wants a 5v TTL clock from what I understand. So first of all if I had a a lower voltage clock say an Si5351 or a 3.3v tcxo, is it acceptable to boost the clock with a transistor/fet or opamp, if so would I want to use something like a low noise jfet or does it not matter?Im under the impression that the higher the clock the faster the sine wave output... the data sheet says to use a 25mhz xtal to get the full 12.5mhz if Im interpreting it right. I know that DDS arent usually good up to 100% of there output so what if I were to use a higher speed oscillator, would this have any effect?

author: jt
author_rank: Regular Contributor
timestamp: November 26, 2015, 06:53:02 am
content: Its been a few years since I worked with that part, but from memory there isn't a strict noise/jitter requirement on the reference clock. Essentially the nosier the reference, the more phase jitter on your output sine wave. So it is up to you (and your application) to decide what is acceptable. Same applies to your considerations in regard to boosting the clock voltage. If you don't have strict phase noise requirements, I would just use a digital logic level-shifter to go from 3.3V to 5V (a 12.5MHz TTL clock is no different than any low/mid frequency digital signal).There should be a relation somewhere in the data sheet that tells you what the maximum output frequency is and what clock reference is needed to achieve it. If you try to "overclock" it I can't say what will happen. If you are worried about spectral purity of the sine wave, general practice is to add a anti-imaging filter (fancy name for a low-pass-filter on the output of a DAC). This will attenuate the high frequency components caused by the discrete steps in the digital to analog conversion. This can be as simple as a first order RC circuit or as complicated as an op-amp based nth-order filter depending on the spectral purity you desire.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 26, 2015, 06:42:53 pm
content: The logical device to go from 3.3 V to 5 V signal level is a 74HCT04 or similar logic gate. This could also be one of the smaller chips with just 1 or two gates.The DDS itself produces some jitter, so the reference frequency does not have to be extremely low jitter. The AD9833 is also more like low end - there are better chips if a really low jitter signal is needed.Usually the filter following the DDS chip is a passive LC filter - frequenices are just to high to practically use active filters and LC filters are relatively easy in this range. One should have a resonable qualitiy filter unless one is only interrested in rather low frequencies (e.g. < 100 kHz). The practical upper limit is more like clock / 3 or 8 MHz for the AD9833.

author: dannyf
author_rank: Super Contributor
timestamp: November 26, 2015, 08:35:32 pm
content: QuoteReading the datasheet will help you reaffirm that understanding.

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: November 27, 2015, 04:46:10 pm
content: Well I have read it and I have no idea what happens if you feed a higher clock rate than 25mhz in to it. Problem is I dont have a 25mhz oscillator around, or xtal. Ive been thinking about just waiting till my si5351 arrives in the mail and seeing what happens to it when I go above a 25mhz clock.This is totally off but Im thinking about getting an AD9851 board from ebay to do filter testing with. But that brings up two questions, I know the DDS can sweep when wired in parallel mode, but does anyone know if the Chinese boards break all the pins out to do this? Secondly when testing a filter would a which is better a zener noise source or a broadband zener noise source made with some microwave grade diodes, and why?

author: Kleinstein
author_rank: Super Contributor
timestamp: November 27, 2015, 08:23:25 pm
content: Measuring filters with noise versus a sine sweep are different due to the time available for the filter to settle. It depends on the filter / system which way is better:The sine sweep can give lots of power to the filter and thus allows low noise, especially in ranges where the filter dampens a lot. On the downside the sweep measures the frequenies one at a time - so it may take a long time to wait for the filter to settle. With high Q filters this may lead to artefacts. Its esepcially bad for hight Q and relatively low frequeny (e.g. 32 kHz crystal).It also depends one the frequency range of interest - if only a small range is needed, the swepp may not be that slow. The noise method essentially allways measures the whole range.Testing a filter with noise also needs a kind of spectrum analyser for measurement. This can be ADC + µC/DSP to take full advantage. A classical analyser will measure one at a time and thus give away the main advantage. The sweep can use simpler hardware for detection, though at low frequencys (e.g. < about 1 MHz) the ADC / µC combination is very viable.You can also do sweeps in serial mode. Just the speed is lower (e.g. 1/8 the speed limit).

author: TLengr
author_rank: Contributor
timestamp: November 28, 2015, 12:04:37 am
content: I am currently working on a project using both an AD9833 and AD9851 DDS. Either can be operated from a 3.3V supply. With the AD9851 you must throttle back the REF clock to 125MHz maximum. There is no clock frequency reduction specified for the AD9833. If you have a 3.3V, 25MHz clock signal available it should work OK. I'd not recommend overclocking. An evaluation board (clone) can be purchased on ebay for about $9.00 that has a AD9833 along with the 25MHz clock and low pass filter on board – a good way to go.The MCLK frequency (25MHz typical for AD9833) determines the rate that a sine look up table is read by the DDS. This is also the rate at which the DAC is updated. According to Nyquist sampling theory, it takes a minimum of two samples per cycle to construct the output signal. Thus a 25MHz sample rate could construct up to a 12.5 MHz signal. In practice, a designer often reduces the maximum frequency output to about 40% or less of the sample clock (MCLK) frequency. The output signal is passed through an anti-aliasing low pass filter to tidy it up a bit before it is used.I know of two different AD9851 boards available on ebay. Both of these breakout parallel data lines D0-D7. Good luck on your project.