Unused transceiver TX channels in Arria 10 device may degrade over time - Page 1
Forum section: electronics / general

author: hamster_nz
author_rank: Super Contributor
timestamp: March 23, 2018, 08:04:54 am
content: Via @whitequark on Twitter...QuoteFull KB article athttps://www.altera.com/support/support-resources/knowledge-base/solutions/rd06092016_720.htmlWill be of most interest to development board users, who might not use the transceivers for long periods of time, and then need to use them.No clear indications as to what or why...

author: BrianHG
author_rank: Super Contributor
timestamp: March 23, 2018, 08:57:56 am
content: What the hell? Quartus with Arria 10 support requires a subscription. Once you stop paying, you cannot upgrade Quartus. So, if I was happy with Quartus 15, stopped paying Altera that yearly fee, now all my Arria 10 devices will keep on degrading, new designs or old, unless I fork over Altera another 4k$ US so I may compile in the latest Quartus prime.Then again, 1 Arria 10 FPGA goes anywhere from 300$ to 5K$. But still, if I am no longer making PCBs, and I want to preserve my existing Arria 10s, I must pay Altera 4k$.

author: EEVblog
author_rank: Unknown
timestamp: March 23, 2018, 10:50:32 am
content: I haven't checked the datasheet, but these things usually run into the 10's GS/s, bleeding edge stuff totally reliant upon the bleeding edge process technology. Probably the geometries are so small now that there is some form of surface migration/contamination/ *insert other issue* that degrades the performance characteristics.At least they are readily admitting it and even building it into the software warnings. In which case it must be almost a guaranteed and predictable level of degradation.

author: BrianHG
author_rank: Super Contributor
timestamp: March 23, 2018, 12:44:27 pm
content: Quote from: EEVblog on March 23, 2018, 10:50:32 amThis is what Altera says in the quote:QuoteThat deterioration most likely has been found to happen when they leave the un-used transceivers in a specific IO voltage mode, or dedicated macrocell configuration for the pins in question when the IO is not used or defined. Perhaps there is a bug in the silicon when leaving the cells in their default unused state which draws current on the mosfets at the pin or internal LVDs transceivers.Again, as altera says, recompile your design in Quartus Prime software version 16.0.1 or later and the problem ceases. Most likely, they configure the IO never to be in that discovered bugged long term deteriorating state.

author: Scrts
author_rank: Frequent Contributor
timestamp: March 23, 2018, 02:25:53 pm
content: It sounds like if someone would sue them, then Quartus v16.0.1 subscription would become free or they'd have to come up with a tool to fix the issue

author: hamster_nz
author_rank: Super Contributor
timestamp: March 23, 2018, 09:49:55 pm
content: Only thing I can find on the web is that it is due to BTI (Bias Temperature Instability).QuoteHere is an interesting chapter on CMOS reliablity:http://www.springer.com/cda/content/document/cda_downloaddocument/9781461461623-c2.pdf?SGWID=0-0-45-1376227-p174706113Neat things like "Purple plague", and pictures of electromigration damage.

author: amyk
author_rank: Super Contributor
timestamp: March 24, 2018, 02:46:54 am
content: I find it more than a little coincidental that Altera is now owned by Intel, who has experienced at least twosimilarproblems...It should be reasonably easy to figure out the difference, just compile with the older version, then 16.0.1, and compare...

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: March 24, 2018, 05:51:19 am
content: From an article in EEtimes:"One reason why Altera is attractive to Intel is that Altera is already using Intel's fab to create its latest generation FPGAs and SoCs; Arria 10 FPGAs and SoCsare being implemented using TSMC's 20nm process, while Stratix 10 FPGAs and SoCs are leveraging Intel’s 14 nm Tri-Gate process (see Altera & Intel toCollaborate on Multi-Die 14nm FPGAs). Furthermore, Altera is also using Intel's state-of-the-art packaging technologies."So Arria come from TSMC fabs, things that make you say Hmm!Article:https://www.eetimes.com/document.asp?doc_id=1326736

author: daveshah
author_rank: Unknown
timestamp: March 24, 2018, 09:59:05 am
content: I would be interested to see if this could affect any commercial products. It sounds like it only manifests itself if transceivers were previously not used at all in the bitstream and then used. The only case where that sounds like an issue is where a firmware update enables transceivers that weren't previously used, or devices which load a different bitstream for different configurations.It sounds like it doesn't manifest itself if transceivers are in the bitstream but soft disabled, which would be a much bigger problem e.g. if you start using a previously unused SFP/SDI/whatever port.

author: iMo
author_rank: Super Contributor
timestamp: March 24, 2018, 01:38:20 pm
content: It could be the Aria is using flash cells for keeping the config bits of the TX channels, which may forget the setting much faster than expected (ie while running the chip at higher temperatures). Therefore you have to refresh the cells with a new bitstream from time to time

author: NorthGuy
author_rank: Super Contributor
timestamp: March 24, 2018, 03:54:14 pm
content: Quote from: BrianHG on March 23, 2018, 08:57:56 amYou can instantiate transceivers in your old designs and configure them as needed. This is free. You only need to wait until the information comes up on what settings are needed to avoid aging.

author: Beamin
author_rank: Super Contributor
timestamp: March 24, 2018, 11:12:49 pm
content: So the silicon in the chip wears out?