ATMEL's CUPL language for their CPLD range of chips, what do you think. - Page 1
Forum section: electronics / general

author: commie
author_rank: Frequent Contributor
timestamp: October 06, 2015, 10:12:35 pm
content: Well, a couple of years ago I decided to get involved in CPLD's, I chose Atmel's range over XILINIX.Atmel supply you with a language called cupl and XILINIX supply you with ABEL they are very similair.Now it turns out XILINIX have discontinued the xc9536 and the xc9572 chips and they are not 5V but 3.3V. So, fortunately I chose Atmel, as all their parts range are still available at Mouser.The thing is though, CUPL is very buggy making it's usage time comsuming, but if like me you put up with it and learn what you can do with it.Is there anybody here using cupl language?

author: ataradov
author_rank: Super Contributor
timestamp: October 06, 2015, 10:43:33 pm
content: The only reason Atmel maintains FPGAs is contractual obligations. As soon as contracts expire, they will be gone in a jiffy.Don't do any new designs using them.

author: JoeN
author_rank: Frequent Contributor
timestamp: October 07, 2015, 07:03:45 am
content: Quote from: ataradov on October 06, 2015, 10:43:33 pmThat's what I thought. They seem to have about 0.0000001% of the market. It looks like they have not introduced a new IC in about 10 years. How did they get into this bind?

author: xtech
author_rank: Regular Contributor
timestamp: October 07, 2015, 07:18:25 am
content: XC95xx parts are 5V but XC95xxXL requires 3.3V (but inputs are 5V tollerant). Don't waste time for ABEL/CUPL, you can use VHDL what will be good if you are planning to switch in the future for FPGAs or larger CPLDs. I'm using also some old Lattice GALs - they are cheap and can be programmed in VHDL too (free IDE from Lattice). Programming GALs is a little problem - support in chinese programmers like TL866 is dubious (especially for GAL22V10, bigger are not supported) but the is always old good Galblast - requires old computer with 16-bit (I've not managed to run it on XP/7) but I've prepared USB bridge for Galblast hw with Arduino and simple command line app for 32-bit Windows.XC95xx (not XL) are still available for low money on aliexpress for example (but in tqfp housings, good they are not refurbished like GAls there)

author: coppice
author_rank: Super Contributor
timestamp: October 07, 2015, 07:29:18 am
content: Quote from: JoeN on October 07, 2015, 07:03:45 amWhy do you see it as a bind? Markets change. You only get into a bind if you don't change with them.

author: commie
author_rank: Frequent Contributor
timestamp: October 07, 2015, 10:04:03 am
content: Quote from: JoeN on October 07, 2015, 07:03:45 amQuestion is, how do improve on the current range?, they are all flash programmable making them very flexible. The ATF1504 costs about £2.50 in qty of 25, however the ATF1508 (128 macrocell plcc68) jumps to a staggering £9.00 per chip and the plcc64 adapter, for my programmer, costs a further £250.00.

author: ehughes
author_rank: Frequent Contributor
timestamp: October 07, 2015, 12:26:09 pm
content: CUPL and ABEL are both ancient.All the real vendors use Verilog or VHDL.The Atmel parts are an extreme dead end.Look into Lattice and Microsemi as well. They have some stuff at the CPLD end as well.

author: Kalvin
author_rank: Super Contributor
timestamp: October 07, 2015, 01:24:49 pm
content: I would look at the small Flash-based FPGA devices. For example, you can get a small-size FPGA in less than $2:http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas-that-small/Digikey prices for different iCE40-series FPGAs:http://www.digikey.com/product-search/en/integrated-circuits-ics/embedded-fpgas-field-programmable-gate-array/2556262?k=iCE40No 5V tolerant I/O? Just add a cheap voltage level translator to each pin which requires 5V tolerant input or needs to be able to drive 5V output.There are available cheap quad logic level translators which are bidirectional and can detect the direction automagically.

author: ataradov
author_rank: Super Contributor
timestamp: October 07, 2015, 03:33:31 pm
content: Quote from: JoeN on October 07, 2015, 07:03:45 amIt is normal to guarantee products for 9-12 years for general public and 20+ years for military and space industry.

author: poorchava
author_rank: Super Contributor
timestamp: October 07, 2015, 04:03:34 pm
content: Add automotive to that - 20 years part availability contracts are a normal thing.Sent from my HTC One M8s using Tapatalk.

author: commie
author_rank: Frequent Contributor
timestamp: October 07, 2015, 04:36:10 pm
content: Well, is Verilog or VHDL free to download or what? Take the industry standard devices like 16V8 and 22V10, does Lattice or any other vendor sell these two devices at reasonable price in a pdil20 and pdil24 footprint respectively and are they 5V operable?. If you answer no to my last question then I'm afraid Atmel fits my criteria for the time being.

author: ataradov
author_rank: Super Contributor
timestamp: October 07, 2015, 04:40:51 pm
content: For what chip? There is no generic Verilog or VHDL, all tools come only from a chip maker.

author: commie
author_rank: Frequent Contributor
timestamp: October 07, 2015, 04:56:10 pm
content: Quote from: ataradov on October 07, 2015, 04:40:51 pmHmmmm....,I see, so once you have made your choice and learned their version of VHDL language, then you are locked in to the chip vendor, right?

author: ataradov
author_rank: Super Contributor
timestamp: October 07, 2015, 04:59:16 pm
content: VHDL is common for all, but tools that can interpret VHDL and compile it down to a hardware configuration file are vendor specific, of course.

author: westfw
author_rank: Super Contributor
timestamp: October 07, 2015, 05:16:09 pm
content: QuoteEven for small (GAL18v10-sized) PALs? I didn't know you could do that!

author: joeqsmith
author_rank: Super Contributor
timestamp: October 07, 2015, 05:25:44 pm
content: Quote from: commie on October 06, 2015, 10:12:35 pmWhen PALASM stopped working with Windows NT, I tried CUPL. At the time Logical Devices owned them. It was a nightmare. I switched to the Lattice tools. They, like many others were using Synplify at the time for their synthesis tool.How many of you are still using a third party synthesis tool? What about third party simulation tools?

author: ataradov
author_rank: Super Contributor
timestamp: October 07, 2015, 05:32:42 pm
content: Quote from: westfw on October 07, 2015, 05:16:09 pmI don't know much about very simple devices. There is no technical reason why you can't use VHDL, but I don't know if manufacturers bothered to implement it.For simple devices it will basically be instantiation of the available blocks and manual connections between them. I doubt you could use actual code.

author: commie
author_rank: Frequent Contributor
timestamp: October 07, 2015, 05:37:17 pm
content: Quote from: Kalvin on October 07, 2015, 01:24:49 pmYes indeed you can but it is totally unusable in its single state, to use these devices you will need a chip vendors 'breakout' or evaluation board costing about $50.There are already enough electronics technology to keep the feed going for the next 100 years, thing is the stack is growing ever larger with time so sooner or later something should filter through.I want pdil only.

author: commie
author_rank: Frequent Contributor
timestamp: October 07, 2015, 05:44:31 pm
content: Quote from: joeqsmith on October 07, 2015, 05:25:44 pmYep I agree, but free to download and use., but what else would you use to program a 16V8 or 22V10?

author: helius
author_rank: Super Contributor
timestamp: October 07, 2015, 06:07:15 pm
content: Quote from: ataradov on October 07, 2015, 05:32:42 pm"Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 Verilog as its Hardware Description Languages (HDL) for design entry. Then, it synthesizes and optimizes the entered design, and outputs a JEDEC or Intel® hex file for the desired PLD or CPLD (see Figure 1)."It appears to synthesize GAL configurations from behavioral architectures. Cypress sold it in the '90s.

author: Kalvin
author_rank: Super Contributor
timestamp: October 07, 2015, 06:19:09 pm
content: Quote from: commie on October 07, 2015, 05:37:17 pmNot necessarily, as there are open source tools and very inexpensive open-hardware development boards:http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/I haven't used those tools, so I cannot say how mature those are and what devices are currently supported.Actually, you do not need to buy chip vendor breakout boards or programmers, as quite a few cheap chinese programmers are available at eBay for different FPGA-devices. However, one needs to be vary careful that the cheap gadget is really compatible with the tools and the target FPGA device.The Verilog and/or VHDL compilers are available for free from the FPGA device vendors.

author: joeqsmith
author_rank: Super Contributor
timestamp: October 07, 2015, 09:59:35 pm
content: Quote from: commie on October 07, 2015, 05:44:31 pmDang, when I got CUPL, it was a paid program. PALASM was free. But again, I switched to the Lattice tools which supported the 22V10. I actually just did a design with a 22V10 for the fun of it. DOSBOX had a problem with PALASM but I was able to get the old Lattice tools to work.

author: John_ITIC
author_rank: Frequent Contributor
timestamp: October 07, 2015, 10:16:41 pm
content: Quote from: commie on October 06, 2015, 10:12:35 pmWell, of course, CUPL was intended for PALs and GALs, where the devices were so simple that one could describe the functionality via simple combinational logic equations. Manual logic minimization via Karnaugh maps was very common. Very simple state machines could also be created. Like other posters said, if targeting CPLDs or FPGAs then I don't see any need to use CUPL. New tools are much more productive; Verilog supports low-level logic description via combinational statements but also higher-level behavioral language constructs, which gets more done in less time, no need to manually do logic minimizations because the tool does this automatically.Important: CUPL also does not analyze timing automatically like modern tools. Concepts like Static Timing Analysis (STA) is vital to actually get any design working in an FPGA. Anything but the very simplest CPLD design should also use proper timing analysis.Finally; I actually used CUPL about 10 years ago when I created the below dump-switch PCI card. Anything more complex than that project (i.e. CPLD) should use the CPLD vendor's modern toolset.http://www.summitsoftconsulting.com/DumpSwitchCard.htm

author: Bassman59
author_rank: Super Contributor
timestamp: October 07, 2015, 10:43:48 pm
content: Quote from: helius on October 07, 2015, 06:07:15 pmThat "subset" of VHDL was limited to VHDL-87 syntax and it was very limited indeed, to the point of being unusable.

author: Bassman59
author_rank: Super Contributor
timestamp: October 07, 2015, 10:47:30 pm
content: Quote from: joeqsmith on October 07, 2015, 05:25:44 pmWe use vendor-provided synthesis tools, so for Xilinx it's ISE (haven't done a Vivado design yet) and for Altera it's the Quartus II. Microsemi (Actel) provides a version of Synplify Pro which targets only their devices.We have a VHDL-only license for Aldec Active-HDL. I'm doing something that targets an Altera device and its gigabit serializers, and the models are System Verilog, so I am using the ModelSim Altera for that.

author: Bassman59
author_rank: Super Contributor
timestamp: October 07, 2015, 10:49:01 pm
content: Quote from: JoeN on October 07, 2015, 07:03:45 amThey saw that they couldn't compete with Altera and Xilinx and Lattice, and they didn't have anything specialist (rad-hard) like Microsemi, so they chose to stick with their core competency (processors, flash memory).

author: Bassman59
author_rank: Super Contributor
timestamp: October 07, 2015, 10:52:23 pm
content: Quote from: commie on October 07, 2015, 04:56:10 pmThe languages are standardized. How well the vendors support the latest features of the languages in their tools is an issue, but for most designs it really doesn't matter.What locks you into a chip vendor is when you choose to use the specialist hardware features of the chips, such as gigabit SERDES, clock management (PLL/DLL) and certain I/O features. In most cases those blocks are instantiated from a library, not inferred, so making code portable to another family is a challenge.

author: uwezi
author_rank: Unknown
timestamp: October 07, 2015, 11:06:26 pm
content: Quote from: xtech on October 07, 2015, 07:18:25 amThanks, that was interesting! I still have quite a few vintage NOS and salvaged GALs lying around, but could not find any way to put them back into some use. You write that the support in the support in the TL8xx programmers is dubious - in which way?I always found it annoying that Lattice kept their programming interface a secret - at least for private consumers. But I had built and used the Elrad(?) programmer on the parallel port at least for some projects, while I still had a DOS computer with a printer port... I suppose it should be possible to revive that one as well.Are you willing to share your Arduino-interface?

author: JoeN
author_rank: Frequent Contributor
timestamp: October 07, 2015, 11:08:38 pm
content: Quote from: coppice on October 07, 2015, 07:29:18 amI only meant to say they are in a bind on this one product line (PLDs). They seem to be doing fine on microcontrollers, touch, and even small memories.

author: artag
author_rank: Super Contributor
timestamp: October 08, 2015, 12:57:16 am
content: No, they've somewhat lost it. They can make ARMs cheaper than they can make AVRs. I don't know why that is - perhaps they don't scale well to modern processes, or perhaps their hands are tied by some IP issues.So Cypress and Dialog were arguing over who was going to take them over. That wouldn't have happened if they were healthy. It will be interesting to see what Dialog do with them.

author: Kalvin
author_rank: Super Contributor
timestamp: October 08, 2015, 06:45:27 am
content: Quote from: blueskull on October 08, 2015, 01:39:30 amThanks for correction! You are absolutely right. I didn't go through the datasheet carefully enough and assumed it to be Flash-based. The ice40 has an on-chip, one-time-programmable configuration memory (NVCM) which can be used to store the FPGA configuration once the device is ready for production. Thus, when the device powers up, it will load the configuration from the on-chip NVCM. However, the device can also boot from an external, standard SPI flash/eeprom which is very handy during development. The third option is to use the microcontroller to provide the configuration bitstream instead of the SPI flash/eeprom which allows in-the-field FPGA configuration updates. The iCE40LP, iCE40HX, iCE40 Ultra and iCE40 UltraLite devices can read only one bitstream from the external SPI flash/eeprom. The iCE40LP and iCE40HX devices can select one out of four bistreams stored in the external SPI flash/eeprom depending on the state of the two I/O-pins during the power-up.http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/IK/iCE40ProgrammingandConfiguration.pdf?document_id=46502Some manufacturers offer real Flash-based devices, which can be programmed multiple times and which do not require external memory of microcontroller to store the configuration bitstream.

author: helius
author_rank: Super Contributor
timestamp: October 08, 2015, 07:04:51 am
content: Quote from: Kalvin on October 08, 2015, 06:45:27 amBesides Microsemi (née Actel) which are they?

author: Kalvin
author_rank: Super Contributor
timestamp: October 08, 2015, 07:23:51 am
content: Quote from: helius on October 08, 2015, 07:04:51 amAltera MAX10 and MAX V FPGA/CPLD families seems to be Flash-based.

author: Kalvin
author_rank: Super Contributor
timestamp: October 08, 2015, 12:20:17 pm
content: Quote from: blueskull on October 08, 2015, 11:52:40 amAltera MAX 10 has on-chip configuration Flash in addition to User accessable Flash blocks, according to the family datasheet. Some devices have even two configuration block to allow live configuration update. As far as I can read the datasheet, the devices are not hot at power-up, ie. it takes a few milliseconds from the device to read its on-chip configuration Flash and configure its logic fabric, and this needs to be taken into account on the system design.Altera's solution is quite similar to Xlinx's and others SRAM-based logic fabrics, except that the device contains one-time-programmable configuration memory, but it can also boot from the external SPI Flash memory similar to Xilinx and others.Microsemi's Proasic3, Igloo and Fusion devices are hot at power-up AFAIK ie. the device configuration is stored at the logic elements thus eliminating those a few milliseconds and the device is ready to rock&roll as soon asi it will be powered up.