I Just Managed to Use STM32 SPI Hardware nSS - Page 1
Forum section: electronics / general

author: Siwastaja
author_rank: Super Contributor
timestamp: October 10, 2020, 04:54:12 pm
content: A miracle has happened:For the first time ever, I was able to successfully utilize the hardware nSS management mode on STM32 SPI peripheral.Use case is STM32H7 being a master for an SPI slave with fixed 32-bit word width, with only single-word packet length, one device per SPI bus.Code that works:Code:#define SPI_CR1_OFF 0#define SPI_CR1_ON 1UL#define SPI_CR1_START (SPI_CR1_ON | 1UL<<9)RCC->APB1LENR |= 1UL<<14 /*SPI2*/;SPI2->TSIZE = 1;SPI2->CFG1 =0b110UL<<28 /*bus clk/128*/ |0UL<<5 /*Fifo threshold 1 word*/ |0b11111UL /*32-bit word*/;SPI2->CFG2 =1UL<<31 /*control IOs also when disabled*/ |1UL<<30 /*nSS inactive pulses between words*/ |1UL<<29 /*nSS output enable*/ |0UL<<25 /*CPOL*/ |0UL<<24 /*CPHA*/ |1UL<<22 /*master*/ |0b1111UL<<4 /*inter-word idle at maximum. actual triggering by ISR, should never need this*/ |0b0000UL<<0 /*extra delay after nSS is activated, before data is clocked*/;IO_ALTFUNC(GPIOB, 12, 5);IO_ALTFUNC(GPIOB, 13, 5);IO_ALTFUNC(GPIOB, 14, 5);IO_ALTFUNC(GPIOB, 15, 5);SPI2->CR1 = SPI_CR1_ON;while(1){SPI2->TXDR = 0xACDCABBA;SPI2->CR1 = SPI_CR1_START;delay_ms(10);uint32_t d = SPI2->RXDR;SPI2->IFCR = 0xffffffff; // clearing status flags is important, the peripheral dies otherwise.}This being said, maybe I will still see it fail one way or another after being triggered from an ISR...

author: Yansi
author_rank: Super Contributor
timestamp: October 10, 2020, 04:58:14 pm
content: Childsplay I'd say. Now try a slave mode with continuous clock and try at 10+ MHz.(Jeeez, if you think SPI on STM32 is too weird, try nRF52 from Nordic. Now that is some deep shit at times, like not being able to read single byte on SPI and having this bug on the chip for 5 fucking revisions).//Edit: This is a joke, I hate the SPI implementation on STM32 as everyone else. But there is much more to the SPI slave operation as written above. Got to scrap a whole project due to a stupid limitation of the SPI slave behavior. //

author: Cerebus
author_rank: Super Contributor
timestamp: October 10, 2020, 05:09:45 pm
content: Quote from: Siwastaja on October 10, 2020, 04:54:12 pmYeah, I'm not sure that I'm going to believe this until I see the logic analyser traces and a certificate signed by your parents and both sets of your grandparents that you didn't cheat.I've got some SPI code that works perfectly doing 16 bit transfers on an F411, port the same thing to a G474 (setting the equivalent, but different register bits) and ... nothing, nada, zip.At the moment I've got them both sitting side by side in front of me, the G474 ignored for the last two days in the hope that putting it on the naughty step looking at the F411 working and getting all my attention will teach it a lesson.

author: Kjelt
author_rank: Super Contributor
timestamp: October 10, 2020, 11:06:44 pm
content: Always check the errata sheet, would be nice if they gave an solution.

author: Cerebus
author_rank: Super Contributor
timestamp: October 10, 2020, 11:35:57 pm
content: Quote from: Kjelt on October 10, 2020, 11:06:44 pmIt's reached the point with STM32 parts and their reputation that I now read the errata sheetbeforethe reference manual.I wish they'd roll the errata into revisions of the reference manuals, it'd save a lot of time.

author: jnz
author_rank: Frequent Contributor
timestamp: October 11, 2020, 03:26:25 am
content: Quote from: Kjelt on October 10, 2020, 11:06:44 pmMicrochip as bad as they are at something does nice erratas usually. With workarounds.The idea that they’ve gotten good at them out of probable necessity is a separate issue.

author: Harjit
author_rank: Regular Contributor
timestamp: October 11, 2020, 05:01:21 pm
content: Quote from: Yansi on October 10, 2020, 04:58:14 pmOn the STM32, I had to do a master in Bidirectional mode at 10MHz. I cannot believe they have receive free running! I cannot for the life of me understand why they didn't put a byte counter (heck, even a bit/clock counter would have been fine). If I needed to receive N bytes, I ended up doing DMA for N-1 and then in the DMA interrupt, turning off the SPI receive. The SPI receive completes the current transfer. I had to make that interrupt the highest priority in the system. Worked quite well but such a waste of effort.Please tell me about the nRF52. I have to do a project using the SPI port on the nRF52832.Thanks in advance.

author: Yansi
author_rank: Super Contributor
timestamp: October 11, 2020, 05:20:16 pm
content: I have once wanted to interface a high speed sigma-delta ADC to an STM32F446 I think it was. The ADC had up to 32 MHz synchronous serial interface, which had a continuous clock output from the ADC, synced by the chip-select where the most interesting sample data were pushed. But it was impossible to do, due to stupid limitation of the SPI peripheral, wanting me a bullshit setup times for the NSS signal. Like way longer, than single SCK period if I remember correctly. The project got scrapped due to this. Unable to read from the ADC. I could read it, but the limit was what, like 6 MHz? Above that the NSS timing would get violated and the SPI returned crap data. Probably my bad, thinking SPI should be a synchronous logic, capable of sensible NSS setup times, even in slave mode! But nope.What I was referring to is errata I think number 58 on the nRF52. It is there for five freakin revisions of the chip design.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: October 12, 2020, 04:08:26 pm
content: Quote from: Siwastaja on October 10, 2020, 04:54:12 pmThat's good news. I'll give it a try on my STM32H743 board. I didn't bother trying it when I ported my driver from STM32F7 because it's never worked on any STM32 parts I've used, so I just assumed they'd continue to screw it up.

author: HB9EVI
author_rank: Frequent Contributor
timestamp: October 12, 2020, 05:50:41 pm
content: I had no problem running the STM32F030 as master using NSS hardware control; but, hell, it just doesn't work the same way on a STM32F103, even tough the reference manual shows exactly the same text; obviously I should start to read the errata more often - thanks anyway for the hint!