High frustration levels trying to make a non-restoring sequential divider - Page 1
Forum section: electronics / general

author: Dukov Ahzrukhal
author_rank: Regular Contributor
timestamp: June 11, 2025, 07:53:55 am
content: Hello everyone, For both work and hobby purposes I have been trying to understand how non-restoring dividers work, but despite my best efforts I have failed to create a working one.I have a design which seems to always produce the correct quotient, but will fail to produce the correct remainder for certain inputs.I have consulted 3 books on the subject: Computer Arithmetic: Algorithms and Hardware Designs (Behrooz Parhami) (mostly useless), Introduction to Arithmetic for Digital Systems Designers (Shlomo Waser and Michael J. Flynn) (the most useful), Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems (Jean-Pierre Deschamps, Gery J.A. Bioul, and Gustavo D. Sutter) (hard to follow, lacks implementation details). Maybe I'm just not so smart, but I have failed to turn the information in these books into actual usable code...I will attach my full code and testbench here (the testbench is a mess, sorry). The interesting case is 255 / 255, which produces the wrong remainder 251If someone can point out where I went wrong I would greatly appreciate it, thanks in advance

author: zapta
author_rank: Super Contributor
timestamp: June 11, 2025, 05:22:11 pm
content: Does this help?https://chatgpt.com/share/6849bb0f-f4f8-8000-b433-8684fc4da3a2

author: Dukov Ahzrukhal
author_rank: Regular Contributor
timestamp: June 11, 2025, 09:45:11 pm
content: I was super skeptical to say the least, but I tried it anyway and to my great surprise it does at least appear to workThe case of 255 / 255 is now producing the correct result, and so are most of the other cases I checked. But there is still a bug, both the original and the new version are failing for the case 255 / 249. Both produce 7 for the quotient, the original version produces 143 as the remainder, and the ChatGPT version produces 0 as the remainder. This seems like a more interesting and severe bugI will attach the ChatGPT "enhanced" version here.

author: suzhiming
author_rank: Contributor
timestamp: June 12, 2025, 12:18:27 am
content: https://bbs.21ic.com/icview-3034864-1-1.htmlThis idea

author: Maister
author_rank: Contributor
timestamp: June 13, 2025, 10:23:27 pm
content: Hey there!I tried to make sense of your verilog code but I am not a verilog guy and could not comprehend what was going onBut I looked up the algorithm and implemented it myself in VHDL.First, I got the same strange errors with 255 / 255 as you got.After trying many different combination with signed / unsigned representation of the numbers and revising the algorithm I got it to work!Here are the things that are important to get right and I did wrong in my first attempts:you have to check the sign bit of R before you shift R:Q (I did that always afterwards in my first attempts)then save that sign bit and shift R:Q oncenow do the R=R+B or R=R-B depending on the sign bit before shiftingto decide on Q(0)='1' or Q(0)='0' you need to now check the sign bit of R again!Another thing to point out that worked for me, was extending the remainder and the divisor by one MSB and treating them as signed. All other internal signals were treated as unsigned.Inputs to the design are assumed to be unsigned 8-bit.Your verilog code tries to do this decision making in a combinational block in a manner that I do not understand. Maybe it right but just missing the extra sign bit checking.The website I got the correct algorithm from is:https://www.geeksforgeeks.org/non-restoring-division-unsigned-integer/.If you want to play around with my design and the testbenches, here is the link to my playground in EDAplayground of that design:https://www.edaplayground.com/x/pnGe.You will be able to see the 2 testbenches I have as well as the actual design.First testbench checks for 255 / 255 and 2nd testbench actually tests for all the possible 65536 combinations of dividing two 8-bit numbers and automatically checks them for errors.If you do not want to login or create an account on EDAPlayground, here is the command for GHDL that I used to run the simulation (GHDL 3.0.0):Code:ghdl -i design.vhd testbench2.vhd testbench.vhd && ghdl -m '-fsynopsys' tb_non_restoring_divider2 && ghdl -r tb_non_restoring_divider2 '--stop-time=20ms'Again, this is all in VHDL (sorry :O) but this is what I am most confident in coding with.Sorry again, I also mixed signals and variables in the design making it even harder for a verilog person to understand whats going on (I guess) but that is the easiest way for me to get the algorithm right.(Remember: signales are updated once the process finishes its current iteration and variables are being updated immediately, which is key in gettig the algorithm right.)I used only synthesizeable VHDL in the design.Attached you will find the design and the two testbenches.Btw.: When I let GhatGPT write the VHDL code for that algorithm for me, it gets the algorithm wrong as well! It's version only checks the sign bit once after shifting!CheersPatrick

author: Dukov Ahzrukhal
author_rank: Regular Contributor
timestamp: June 14, 2025, 09:02:01 am
content: Wow, this is great, thank you so much! VHDL is a bit hard to read for me but I can surely figure it out. I will try to fix my verilog code when I get a chance and post it here, just in case someone else needs it in verilogGood job getting the algorithm to work

author: Dukov Ahzrukhal
author_rank: Regular Contributor
timestamp: June 16, 2025, 10:12:33 pm
content: It took me some time because I got very busy, but I managed to translate the solution from Maister form VHDL to Verilog. I was also able to fix the "work" version of the divider... Since it is only working because of this thread I don't think anyone will mind if I post it here. I have not yet managed to fix the original code that I posted. I will spend some more time trying and post it here if I get it to work, it might be more optimized once I clean it up.I will also post the translated code from Maister here. Thanks again for the help!