Getting started with pic18f4520 but circuit not working - Page 1
Forum section: electronics / beginners

author: cold-steel
author_rank: Newbie
timestamp: June 09, 2019, 10:09:06 pm
content: i am trying to get an led to turn on using a pic micro controller but it wont turn on. the wired thing is i didn't get an error when i uploaded my code to the pic. there might be a problem with the code but i have a feeling there is something wrong with my circuit. im using pickit3 and mplabx btw. im powering everything with 4 AA batteries 3 of them aren't full but their combined voltage is around 5.5v.

author: oPossum
author_rank: Super Contributor
timestamp: June 09, 2019, 10:26:42 pm
content: You have it configured for an external oscillator that does not exit. See page 23 of DS39631E.There are no 100 nF caps on the power supply to the MCU.

author: MarkF
author_rank: Super Contributor
timestamp: June 09, 2019, 10:45:56 pm
content: As mentioned, you need to configure for internal clock.You should also have Watchdog Timer=OFF, Brownout=OFF and Master Clear=OFF unless you want to use them.In addition, you did not set the internal clock frequency.Here is an example "Blinky" program.Configuration bits set with MPLAB X config window.Code:/** File: main.c**/// PIC18F4520 Configuration Bit Settings// CONFIG1H#pragma config OSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)// CONFIG2L#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)#pragma config BOREN = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)#pragma config BORV = 3 // Brown Out Reset Voltage bits (Minimum setting)// CONFIG2H#pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)// CONFIG3H#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)#pragma config MCLRE = OFF // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)// CONFIG4L#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))// CONFIG5L#pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) not code-protected)#pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) not code-protected)#pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) not code-protected)#pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) not code-protected)// CONFIG5H#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)// CONFIG6L#pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) not write-protected)#pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) not write-protected)#pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) not write-protected)#pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) not write-protected)// CONFIG6H#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)// CONFIG7L#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)#pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)#pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)// CONFIG7H#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)// #pragma config statements should precede project file includes.<xc.h>_XTAL_FREQ 8000000Lvoid main(void) {OSCCON=0x72; // Select internal oscillator @ 8MHzTRISA=0b11111111; // Set Port A direction bitsTRISB=0b11111111; // Set Port B direction bitsTRISC=0b11111111; // Set Port C direction bitsTRISD=0b00000000; // Set Port D direction bitsINTCON2bits.nRBPU=1; // Port B pull-ups disabledADCON0=0; // A/D converter offADCON1=0x0f; // All digital inputswhile (1) {LATD = 0xff;__delay_ms(1000);LATD = 0x00;__delay_ms(1000);}}

author: malagas_on_fire
author_rank: Frequent Contributor
timestamp: June 09, 2019, 11:19:07 pm
content: Also be sure to wait to OSCON internal to stabilize :Here is an excert from a code that is running on a personal project.Code:OSCCON = 0x72; //8MHz clockwhile(!OSCCONbits.IOFS); //wait for osc stableit is a simple while loop to check the flag. IOFS,, meaning the internal oscilattor is good to go. It is a step of init of this oscilllator mentioned on the datasheetLink to the project:https://www.eevblog.com/forum/beginners/lm35-resistance-is-futile/msg1935424/#msg1935424Edit:Datasheet reference:Page 312.7.1 - OSCILLATOR CONTROL REGISTER"The IOFS bit indicates when the internal oscillator block has stabi-lized and is providing the device clock in RC Clockmodes."

author: CJay
author_rank: Super Contributor
timestamp: June 10, 2019, 09:41:09 am
content: As others have said, you have external oscillator configured but no external oscillator on the breadboard.MarkF kindly provided code which enables the Internal oscillator but didn't explain how the code was generated.MPLABX has a handy feature which allows you to automatically generate code to set the configuration bits (the following code is just the default settings for the last chip I wrote for, don't copy it)Code:// PIC18F45K20 Configuration Bit Settings// 'C' source line config statements// CONFIG1H#pragma config FOSC = RCIO6 // Oscillator Selection bits (External RC oscillator, port function on RA6)#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)// CONFIG2L#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))#pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)// CONFIG2H#pragma config WDTEN = ON // Watchdog Timer Enable bit (WDT is always enabled. SWDTEN bit has no effect)#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)// CONFIG3H#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)#pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)#pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.)#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)// CONFIG4L#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))// CONFIG5L#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)// CONFIG5H#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)// CONFIG6L#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)// CONFIG6H#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)// CONFIG7L#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)// CONFIG7H#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)// #pragma config statements should precede project file includes.// Use project enums instead of for ON and OFF.<xc.h>

author: cold-steel
author_rank: Newbie
timestamp: June 10, 2019, 10:25:30 pm
content: thanks a lot ill try that now

author: cold-steel
author_rank: Newbie
timestamp: June 11, 2019, 01:50:21 am
content: this is the first time i was on this forum and this was extreamly healpful.thanks a lot for the help i had a few other problems which i was able to figure out once i knew where to start. thanks alot guys.