LPC-bus chip at less than 33MHz - Page 1
Forum section: electronics / projects

author: RoGeorge
author_rank: Super Contributor
timestamp: April 20, 2024, 07:26:35 am
content: I have a scrapped motherboard with anIT8705Fsuper IO chip (LPC bus)and I would like to reuse that chip in a microcontroller project. However, the LPC bus is specified for 33MHz (the typical PCI clock in a motherboard), while I want to bit-bang the clock and data from a microcontroller, at a much lower rate.Intel defined a while ago thespecificationsfor the LPC interface (Low Pin Count). It's a 4 wires bus with 2 more wires for signaling, so 6 pins minimum instead of the full width of a typical address + data bus of the CPU. LPC also supports IRQ and DMA over its 4 data lines.LPC was meant for low bandwidth PC peripherals, like LPT, COM, GPIO, sensors, FDD, etc. Usually all these peripherals are integrated in a single chip called Super IO, the one shown at the bottom of this Wikipedia pic:The LPC bus has a dedicated line for a 33MHz clock (the typical PCI clock). Since the LPC transfers are made synchronous, it should work at lower clocks, too. The PCI standards specify the PCI clock can be paused indefinitely, so I guess all PCI driven chips has to be entirely static, and thus, they should not care at all about the actual clock frequency. But I'm not sure if this will work in practice.Anybody tried to bitbang LPC bus chips at a much lower speed, or seen such a hack elsewhere?

author: moffy
author_rank: Super Contributor
timestamp: April 20, 2024, 09:05:48 am
content: One thing I would be concerned about is if the 33MHz is the main clock for the chip. If so the peripheral clocks would be derived from that and it would mess up their timings e.g. the UART baud rates. A synchronous bus like that sounds like it would need an FPGA between the micro and the interface chip, but then I haven't worked with this bus before.

author: RoGeorge
author_rank: Super Contributor
timestamp: April 20, 2024, 11:12:04 am
content: Good point, I was just looking into that. The 33MHz PCI clock can be paused by the PCI bus (has something to do with low power regimes and such), so the super IO chip uses yet another input 24 or 48MHz, from where it derives all the peripheral clocks.On the motherboard, there is indeed a quartz near the chip (24.576MHz), yet the quartz seems to be connected to the smaller chip near the the super IO chip (the small chip right underneath the crystal). That is the sound codec (ALC201A), and it needs precisely 24.576MHz to generate the right sampling rate for the sound DAC/ADC.Side note, the ALC201A is not connected to the LPC bus, the sound codec is using I2S (connected to the motherboards' southbridge chip).I was planning to harvest them together anyway, the super IO and sound codec (to make a Raspberry Pi hat). My RPi doesn't have a proper sound codec, it uses some PWM sound generated by the RPi chipset, BCM2835, an ALC201A would be a nice addition, if I manage to drive it from the RPi. If it works, that will add a ton of features and GPIOs for a RPi.I hope the super IO and the sound codec share that 24.576MHz clock, but didn't verify yet. If not, I'll have to add a 24MHz oscillator for the super IO peripherals clocking.Regarding chips harvesting from the scrapped motherboard, I'm tempted to saw away (or to just try to cut it with a pair of scissors made for cutting metal sheets), rather then just desoldering everything then manually rewire all as a RPi hat. Seems like a bad idea, but it will spare a ton of work. The problem is how to cut through the PCI connectors.Any other advice or idea for harvesting the chips from the MB?

author: NiHaoMike
author_rank: Super Contributor
timestamp: April 20, 2024, 12:13:21 pm
content: It would be easier to replicate the functionality with a Raspberry Pi Pico connected by USB.

author: moffy
author_rank: Super Contributor
timestamp: April 20, 2024, 12:16:13 pm
content: This might be of interest, someone built an LPC bus sniffer for an x86 motherboard using a raspberry pi pico:https://github.com/MrGreensWorkshop/RasPiPicoSDK-PicoBiosPostCodeReader

author: RoGeorge
author_rank: Super Contributor
timestamp: April 29, 2024, 08:12:53 am
content: Turns out I was overly optimistic.After reading the datasheets:- the sound CODEC (ALC201A) is not I2S, but AC-Link (AC'97). At least it works at 3.3V (same as the RPi IOs), but it needs 5V, too, for its audio out. There is a 78L05 onboard (to reduce the digital noises that might be on the +5V digital power) so the sound chip will need 3.3V and a 12V, too, for the 78L05, or maybe a charge pump voltage doubler to get 10V from 5V. ALC201A has its local quartz oscillator, so the audio data clock must be 12.288MHz (half of the 24.576MHz quartz).- the super IO chip (IT8705F) is working at 5V (the PCI bus of that motherboard, from where the chip was cut out, was at 5V), not at 3.3V, like Raspberry PI, so it will need bidirectional level shifters (the LPC bus has 4 data lines and 2 control signals minimum). The 24.576MHz clock from the sound chip is for the ALC201A only, so the super IO chip IT8705F will need its own 24MHz / 5V clock.