How to simulate and model external inputs/outputs in LTSpice and other apps? - Page 1
Forum section: electronics / beginners

author: YurkshireLad
author_rank: Frequent Contributor
timestamp: March 10, 2021, 12:13:05 am
content: I built the schematic shown in this image:https://projetsdiy.fr/data/uploads/2018/06/esp8266-capacitor-wakeup-circuit-npn-transistor-1030x578.pngWhich is from this article:https://diyprojects.io/esp8266-deep-sleep-mode-test-wake-pir-motion-detector/#.YEBIoo4zbIUThe schematic provides a means of waking the ESP8266 from a deep sleep when there is motion on the PIR sensor or the configured sleep period ends, e.g.:Code:ESP.deepSleep(TIMER_INTERVAL, WAKE_RF_DEFAULT);I made a modification to the schematic so that once woken, the ESP8266 could monitor the PIR sensor and wait for it show no motion. At which point it would put itself back into a deep sleep. I've attached a screenshot of the new version, which I modeled in circuitjs.I have the attached schematic built on my breadboard and it works as I expect it to.I thought it would be an interesting experiment to model and simulate it using KiCad, EasyEDA or LTSPice. I guess the long term goal is to also design the PCB in one of these apps, but I won't send the result out to be built. This is just me learning and experimenting.I think I can probably model it in any of these apps, but I'm not sure how I would simulate the pins and the PIR sensor. My first attempt used a couple of voltage switches in LTSpice, but this didn't seem like the best solution.I want to simulate pin D2 (output) being set high when the sleep period ends and the ESP8266 is woken from its sleep. I also want to simulate the PIR sensor. What is the best way to model these?I hope that made sense - it's a bit of a rambling post. It looks like I forgot to select the resistor values before I grabbed the screenshot of my schematic. Oops!Thanks

author: Ian.M
author_rank: Super Contributor
timestamp: March 10, 2021, 01:01:07 am
content: For most purposes, a CMOS output pin 'looks' like a voltage source, with internal resistance. Simply choose appropriate high and low levels internal resistance and risetime, and in LTspice, model it as a pulse or PWL source. PWL can use an external PWL file if you need a complex signal. Worst case, if that's not good enough(e.g. because you need to model the assymetric on resistance, or need to model the output stage supply current), you can use appropriate models for the high and low side output MOSFETs for that logic family, and simply drive the gates with the inverse of the required output signal.For open drain or open collector outputs, if its a really simple expression in time, you may be able to get away with a behavioral resistor. In most cases you can probably use a controlled switch- I favor CSW (current controlled switch) because its simpler to wire up with no wiring required between CSW and the voltage source passing its control current. See details and Cswitch.asc exampleOtherwise if that's not good enough, you need a model for the output transistor, and inverted gate/base drive for it.

author: YurkshireLad
author_rank: Frequent Contributor
timestamp: March 10, 2021, 01:07:33 am
content: Thanks - you've given me a lot to think and read about.

author: Ian.M
author_rank: Super Contributor
timestamp: March 10, 2021, 01:17:12 am
content: Note you can also use LTspices A device logic gate and flipflop primitives + behavioral voltage sources controlled by if expressions testing other signals to implement arbitrarily complex sequential logic if you need to simulate a MCU output pin that reacts to other inputs.Each gate that's an input to the logic block or that follows a gate with non-zero propagation delay needs a Tripdt set to force LTspice to consider its transition accurately, and flipflops that have feedback, or that feed another flipflop on the same clock, need both Tripdt and propagation delay Td. The final gate should have Vhigh set appropriately and Rout (or Rhigh and Rlow, but that slows the sim), and Ref set to 0.5 so its threshold is compatible with the 1V default levels of the A device gates.See LTspice(R): Circuit Elements: A. Special Functions in the help file.