LCD prj for Altera Cyclon IV do I need to add input/output ports in bsf how - Page 1
Forum section: electronics / general

author: barnea10
author_rank: Newbie
timestamp: February 05, 2023, 02:58:49 pm
content: hiI use Quartus II 13.1 (64-bit) Web Edition with kit of Altera Cyclon IV and opened an example project for LCD displayin verilog.I opened the project, the code opened (attached)compilation pass ok,and I opened the bsf design file that shows the block and atthe inputs and outputs appear Xso I thought I should add input port and output port and also ALTPLL for CLKhow ever where I try to insert a port but It is not workingwhat am I missing ?thanks !Code:module lcd(clk, rs, rw, en,dat);input clk;output [7:0] dat;output rs,rw,en;//tri en;reg e;reg [7:0] dat;reg rs;reg [15:0] counter;reg [4:0] current,next;reg clkr;reg [1:0] cnt;parameter set0=4'h0;parameter set1=4'h1;parameter set2=4'h2;parameter set3=4'h3;parameter dat0=4'h4;parameter dat1=4'h5;parameter dat2=4'h6;parameter dat3=4'h7;parameter dat4=4'h8;parameter dat5=4'h9;parameter dat6=4'hA;parameter dat7=4'hB;parameter dat8=4'hC;parameter dat9=4'hD;parameter dat10=4'hE;parameter dat11=5'h10;parameter nul=4'hF;always @(posedge clk)begincounter=counter+1;if(counter==16'h000f)clkr=~clkr;endalways @(posedge clkr)begincurrent=next;case(current)set0: begin rs<=0; dat<=8'h30; next<=set1; endset1: begin rs<=0; dat<=8'h0c; next<=set2; endset2: begin rs<=0; dat<=8'h6; next<=set3; endset3: begin rs<=0; dat<=8'h1; next<=dat0; enddat0: begin rs<=1; dat<="H"; next<=dat1; enddat1: begin rs<=1; dat<="E"; next<=dat2; enddat2: begin rs<=1; dat<="L"; next<=dat3; enddat3: begin rs<=1; dat<="L"; next<=dat4; enddat4: begin rs<=1; dat<="O"; next<=dat5; enddat5: begin rs<=1; dat<=" "; next<=dat6; enddat6: begin rs<=1; dat<="W"; next<=dat7; enddat7: begin rs<=1; dat<="O"; next<=dat8; enddat8: begin rs<=1; dat<="R"; next<=dat9; enddat9: begin rs<=1; dat<="L"; next<=dat10; enddat10: begin rs<=1; dat<="D"; next<=dat11; enddat11: begin rs<=1; dat<="!"; next<=nul; endnul: begin rs<=0; dat<=8'h00;if(cnt!=2'h2)begine<=0;next<=set0;cnt<=cnt+1;endelsebegin next<=nul; e<=1;endenddefault: next=set0;endcaseendassign en=clkr|e;assign rw=0;endmodule

author: BrianHG
author_rank: Super Contributor
timestamp: February 07, 2023, 08:46:10 pm
content: Is this LCD module your top heiarchy in your project?Using this 'really' old style Verilog port definitions, you still need to declare each port name which wires to the outside world by placing it's name inside the 'module xxx( ... )' brackets. Then continue to define if it is an 'output, input, or bidir', then next you may also force some to be a direct register, or wire....If this is your first Verilog code, then it might be appropriate to learn from scratch slightly more modern port definition practices.As for on Quartus, if you are using the block-diagram feature and the 'generated symbol' you have shown us, then yes, adding and wiring an'output', 'input', or 'bidir'pin to your symbol is recommended to allow connections to FPGA pins, or another larger parent sheet or schematic.I would personally forgo any block diagram schematics and stick to strictly verilog source files and tell Quartus which source file is the top hierarchy whose module's (port names) will become available to assign to FPGA pins after analysis and synthesis.

author: c64
author_rank: Frequent Contributor
timestamp: February 07, 2023, 10:34:11 pm
content: What is top entity of the project? If it's verilog file, you don't need to add ports.If it's bdf, you need to add ports from the toolbar. You say it's not working. What happens when you try to add them?

author: barnea10
author_rank: Newbie
timestamp: February 12, 2023, 08:31:58 pm
content: thanksits Verilog, ill check again