Why a LDO with three output capacitors. - Page 1
Forum section: electronics / beginners

author: Tonn
author_rank: Contributor
timestamp: December 28, 2017, 03:09:02 pm
content: Hi,I'm studying a schematic that has a LDO (LP5907) with three output capacitors: 1uF, 100n and 10n.The capacitors are of the same type (ceramic, X7R) and mounted next to each other.The schematic is about a low noise design.The 1uF capacitor is straight from the LP5907 datasheet.Why the other two capacitors?Thanks.

author: RoGeorge
author_rank: Super Contributor
timestamp: December 28, 2017, 03:15:54 pm
content: The other two smaller ones are for reducing the ripple at high frequencies.Bigger capacitors tend to have bigger Equivalent Series Resistance, so at high frequency a big capacitor will have an ESR comparable or even bigger than the expected Xc. Smaller capacitors tend to have lower ESR at higher frequencies.Also, putting more than one capacitor in parallel will reduce the total ESR when compared with only one bigger capacitor.

author: AndyC_772
author_rank: Super Contributor
timestamp: December 28, 2017, 03:19:38 pm
content: The standard answer is that using multiple capacitors gives better noise suppression across a wider range of frequencies. Each one has a minimum impedance (limited by its parasitic inductance) at a different frequency.What is often overlooked, though, is that the parasitic inductance depends on physical package size, so for example, a 1uF 0603 capacitor has very similar inductance to a 100nF 0603 capacitor. This means that the 1uF cap actually has lower total impedance at *every* frequency than the 100nF, and so using a 100nF cap in parallel with it is pointless.Using multiple caps in parallel is only really beneficial if the smaller value ones are physically much smaller than the larger values *and* they are all routed into a solid power plane, without adding so much extra trace and via inductance that the benefit is lost.A single capacitor with a small plane around it, and several vias into the power and ground planes, indicates a skilled board designer who understands what is actually going on. Several capacitors of different values, each connected by a few mm of track into a single via, points to a designer with only half a clue.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 28, 2017, 03:42:22 pm
content: Superstition.If you do the PDN simulation, you'll find the peak PDN impedance is worse than for a single ceramic plus bulk cap.Tim

author: Yansi
author_rank: Super Contributor
timestamp: December 28, 2017, 03:50:27 pm
content: As this example of skilled designer. (Itisshould have been a 2GHz mixer)Note the decoupling caps. (Skilled designers may note even more interesting stuff on that board)

author: mikerj
author_rank: Super Contributor
timestamp: December 28, 2017, 03:54:24 pm
content: Quote from: AndyC_772 on December 28, 2017, 03:19:38 pmThat's not totally true. Often a smaller value cap can have a lower impedance at frequencies above the series resonant frequency of the larger value cap.

author: stmdude
author_rank: Frequent Contributor
timestamp: December 29, 2017, 09:38:54 am
content: Dave did a video on this about a year ago.

author: yl3akb
author_rank: Regular Contributor
timestamp: December 29, 2017, 09:59:28 am
content: What about unintentional parallel resonance circuit (which is high impedance!!), which you may get with inductance of large cap + small value cap?

author: bd139
author_rank: Super Contributor
timestamp: December 29, 2017, 10:37:45 am
content: I can see a design error on that board. First to see it wins nothing

author: bd139
author_rank: Super Contributor
timestamp: December 29, 2017, 10:53:44 am
content: MLCC mechanical stress + no edge via stitching (hello capacitor). you win nothingI found the latter one by mistake on a board I spun about two weeks ago. Resulted in a nice VHF oscillator. Does anyone know a canonical checklist of RF design gotchas to run a board against?

author: max_torque
author_rank: Super Contributor
timestamp: December 29, 2017, 12:36:01 pm
content: Just for the sake of playing devils advocate, let me add an opposing view!For most electronics designers, the resource that is most limited and also carries the highest cost is their time. Unless you are making 100,000's of a device, then the extra cost of a few nF smc caps is literally irrelevant, compared to the extra cost in engineering and validating a unique "low component count" type design.So, multiple caps after an LDO has been used tens of thousands of times before, and proven to work, by simply repeating that, you are most likely to produce a system that works first time without any significant issue. Sure, it might not be as low ripple or low noise as it could be. It might cost a few cents more than it could, but in general, it works, and means the designer can spend there time on the things that DO matter in that device!In the vast, vast majority of cases, where the LDO is powering a load that is not that fussy to it's source, then an extra cap or two isn't going to affect the operation of that device. If you had the time, you could when the device is first prototyped, carry out a suite of tests to see if those extra caps were needed, but even the time to (robustly) do that, in most cases, would be better spent elsewhere.....

author: Yansi
author_rank: Super Contributor
timestamp: December 29, 2017, 01:00:27 pm
content: Quote from: bd139 on December 29, 2017, 10:53:44 amYeah, the designer must have been high on some very good material.

author: b_force
author_rank: Super Contributor
timestamp: December 29, 2017, 01:06:21 pm
content: Sometimes it also just works better on the PCB in terms size.Another thing could be costs, or just the fact that you have these small ones in your design anyway.

author: mjkuwp
author_rank: Unknown
timestamp: December 29, 2017, 01:17:28 pm
content: http://www.hottconsultants.com/techtips/decoupling.htmlQuoteHenry Ott

author: ConKbot
author_rank: Super Contributor
timestamp: December 29, 2017, 01:49:00 pm
content: Quote from: T3sl4co1l on December 28, 2017, 03:42:22 pmThis. Just had an eye opening session in LTspice yesterday after getting the numbers for parasitics of the caps put in. Sure that 100p cap will have a nice low impedance dip at high frequency, but it's gonna throw a peak in at a lower frequency. If its amplitude is enough to matter depends on the rest of the curve.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 29, 2017, 04:46:15 pm
content: Quote from: ConKbot on December 29, 2017, 01:49:00 pmYup!This is more or less the 2nd order equivalent model from Dave's video (counting order as 0 = just capacitors, 1 = capacitors with inductors between them, 2 = capacitors modeled with ESR+ESL, 3 = including dissipation and loss, coupling between inductances, etc.):What Dave misses is that impedances are complex valued, so when putting two together, one above and one below SRF, the two components are actually acting as an inductor and capacitor and therefore you get a parallel resonance.Adding trace inductances isn't necessary to show the effect, but it's a more realistic result.Instead, if we use just two capacitors, one of which has ESR added (or we use a lossy type like a tantalum*), the result is much better:*Polymer and tantalum caps are available in all sorts of ESRs, from very low to very high. Most polymers cluster at lower ESRs, while most tantalums cluster around a fractional ohm; but whichever type you're shopping for, understand that the ESR is a critical component parameter, and you have your choice of it from either family. And if you don't like either, you can always add a resistor to a ceramic -- no shame in that, though it does increase the ESL somewhat.Instead of having a worst-case impedance of 2 ohms at 20MHz, this has a worst-case impedance of 1 ohms (or 0dB) at low frequencies, getting better as frequency rises, until ESL takes over.Huh, the scale changed, that's weird. The asymptote is also higher: it passes 2 ohms at about 50MHz, instead of 200MHz. This is effectively L2 + L6, don't know why I had made L6 larger in the latter case. That perhaps represents a somewhat lazy condition, where there's a few more mm of trace length between 0.1uF cap and load. Rest assured, for a comparable layout (i.e., distance between pin and bypass cap, same trace width), the asymptote is the same -- it's just a straight proportion of length.Tim

author: Tonn
author_rank: Contributor
timestamp: January 01, 2018, 01:36:29 pm
content: Being the OP I have been following all the answers.Everyone thanks very much for so much and really helpful information. I'm impressed with the level of expertise.My current step is to pick up LTSpice to study all this.Best wishes for 2018.Tonn