Finding fault in combinational logic circuit - Page 1
Forum section: electronics / general

author: galvanix
author_rank: Contributor
timestamp: December 03, 2017, 10:49:28 am
content: Hello!I am currently working on a university project for which I have a state machine with some state transition logic.One of the requirements of this project is to do a manual schematic entry of the FSM state transition logic.In order to make my life a tad bit easier, I wrote a Verilog test bench that applied all possible inputs to the behavioral description of the state transition logic and then recorded the corresponding outputs.I used that data to define a logic function inLogic Fridayvia the CSV import.Unfortunately my state vector is 6 bits long as I have 54 states to represent. Including flags from the ALU and a reset and load signal my total number of inputs is 10 bits and I am outputting 6 bits.This means I have 1024 possible input combinations.Discarding half of the times where the reset signal is high that still leaves 512 combinations that have to be checked.The way I'm currently verifying the schematic entry version is to simply use the schematic view of my FSM logic in the previously mentioned test bench andlooking at the input and output bit patterns for the behavioral and schematic version by viewing the differences between the two resulting text files in a text editor.You can view both files and their differences on GitHub:https://github.com/g4lvanix/sse-eevblog/commit/bb008412cc44cc3f9f2b6238bbb35deea1285844?diff=splitIn my case I have a couple of repeating combinations where one of the bits is incorrect.Is there a systematic way to figure out where in the schematic things are going awry?The schematic is rather large with 114 gates and I have no idea how to properly debug such issues systematically.I have attached the schematic just so you know what I'm looking at and why I need an efficient way of debugging this issue.Any help is greatly appreciated!galvanix

author: rstofer
author_rank: Super Contributor
timestamp: December 03, 2017, 04:20:04 pm
content: Not related to your specific problem but have you thought about using synchronous set/reset of the state flops to force a particular state during 'reset'. From what I read of your description, this cuts out half of the states.I took one look at the logic tree and gave up. As a practical matter there are far too many levels. And, of course, there isn't any delineation of logic blocks. Sooner or later, you need to decode each state in a 'one-hot' configuration. That would be a block of logic with 6 inputs and 64 outputs (not all used). In an FPGA, we would just let the tool use 'one-hot' because word width doesn't matter much. In a discrete implementation, 58 extra bits of memory is a big deal. But if half the states disappear when 'reset' is removed then full decoding as a logic block might seem workable.I kind of like this description of a (mini) RISC machine:http://people.cs.georgetown.edu/~squier/Teaching/HardwareFundamentals/LC3-trunk/docs/LC3-uArch-PPappendC.pdf

author: galvanix
author_rank: Contributor
timestamp: December 04, 2017, 09:02:04 pm
content: Quote from: rstofer on December 03, 2017, 04:20:04 pmI have tried that and alas it does not simplify the logic at all.I would love to use an implementation like shown in figure C.4 of on 571 in that PDF you linked. It would make the whole thing trivially easy to implement.Unfortunately as we don't have any RAM or ROM cells available in our course library this would be implemented as a behavioral description which I already have.I'll try talking the TA and see what they say. Maybe they'll agree that debugging something like that is too hard and let me use a behavioral description instead.Thank you!

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: December 05, 2017, 06:31:48 pm
content: Quote from: galvanix on December 03, 2017, 10:49:28 amHow did you develop this schematic? Can you show it to us?

author: galvanix
author_rank: Contributor
timestamp: December 05, 2017, 07:47:23 pm
content: Quote from: Bruce Abbott on December 05, 2017, 06:31:48 pmI basically created a verbatim copy of the schematic shown in the first post in Cadence using the logic cells provided by the PDK we're using.