Why not CMOS? - Page 1
Forum section: electronics / general

author: Rick Law
author_rank: Super Contributor
timestamp: January 29, 2022, 02:55:29 am
content: With flash and EE-PROM both have wearing down issue when written frequently, I would imagine CMOS memory module of similar capacity with button battery would be very popular for storing stuff like settings, configurations and such.Why isn't CMOS memory module over the place? What is the draw back that I am not aware of?

author: TerraHertz
author_rank: Super Contributor
timestamp: January 29, 2022, 03:10:20 am
content: Reasons:Cost of the battery, and board space for it.Need to implement power-fail data protection (if using standard CMOS RAM, which doesn't include that.)But most importantly, probably the primary reason in corporate minds:CMOS RAM plus easily replacable, no-leak coin cell, does not meet corporate 'planned obsolescence' objectives. They don't want to sell hardware that users can keep operational forever. They want to make and sell stuff that dies after some years, so the user has to buy a new one.Limited lifetime flash memory is perfect for that. Since few users can diagnose and replace dead SMD chips. Especially if it held the firmware as well as config data.

author: james_s
author_rank: Super Contributor
timestamp: January 29, 2022, 03:50:50 am
content: Nonsense, the reason is cost, and the fact that battery backed RAM has a battery to fail. It is a common thing for people to modify older equipment to eliminate the battery and replace the memory device with flash or FRAM. Batteries are problematic, a large number of arcade and pinball PCBs have been damaged or destroyed by leaking batteries. Also capacity is a factor, flash chips hold much more data than CMOS SRAM.

author: ejeffrey
author_rank: Super Contributor
timestamp: January 29, 2022, 04:54:15 am
content: Standard flash chips have more than enough endurance for those applications. Wear just isn't an issue in the vast majority of applications.In addition to the points james_s makes, replaceable batteries suck if the stored information is important because it gets lost when the battery dies or while you replace it. If the data is important enough to store maybe it's too important to lose.

author: David Hess
author_rank: Super Contributor
timestamp: January 29, 2022, 05:27:59 am
content: Battery backed up CMOS SRAM has been used in various applications in place of EEPROM. In a low performance design, the CMOS SRAM could even be the main memory for the CPU. Serial access SRAM is also available which is intended for this sort of application.

author: Kim Christensen
author_rank: Super Contributor
timestamp: January 29, 2022, 05:50:48 am
content: Back in the day that was the way to do it. But as others have said, modern flash is a far better choice.If needed, a product could write to volatile RAM, sense when power has been removed, and have a capacitor to keep it running long enough to commit the data to flash.Pic of an obsolete NVRAM chip with built in battery:https://datasheets.maximintegrated.com/en/ds/DS1225Y.pdf

author: srb1954
author_rank: Super Contributor
timestamp: January 29, 2022, 09:08:02 am
content: Quote from: TerraHertz on January 29, 2022, 03:10:20 amThey had the planned obsolescence objectives pretty well sorted back in the days when they used NiCd batteries for CMOS backup. The NiCds could be relied upon to leak and destroy large areas of a PCB forcing the scrapping of many pieces of equipment.Unfortunately the introduction of the RoHS rules put paid to that little scheme effectively banning NiCds due to their cadmium content.

author: Ian.M
author_rank: Super Contributor
timestamp: January 29, 2022, 10:51:17 am
content: CMOS SRAM typically uses six*MOSFETs per memory cell. FLASH uses one MOSFET, with a regular gate stacked on top of the floating gate that stores the charge that holds the state. Additionally more than one bit can be stored per FLASH cell (MLC FLASH) by treating the stored charge as an analog quantity and decoding it via a fast two or three bit ADC in the on-chip sense amplifiers.Therefore FLASH wins over SRAM of the same generation technology, as it typically offers an order of magnitude more memory density.* Its possible to only use four, using polysilicon pullups at the expense of static power consumption.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 29, 2022, 02:55:37 pm
content: Incidentally, several other NVRAM technologies are also limited in density. FeRAM can't be smaller than a ferroelectric domain, feature size ~100nm IIRC. So the density is comparable to SRAM (at feature size from a couple fab generations ago). But this also means it's suitable to add onto existing coarse-scale chips like MCUs (e.g., TI's line of MSP430s with FeRAM).And, I forget what other technologies are current and practical, and how well they scale? (PRAM, MRAM, etc.)The issues of Flash are largely solved by using metric fucktons of it. With wear leveling and a few gigs to spare, who cares how many writes it can take, if you just need a few megs? (Assuming this is a smaller scale application of course. SRAMs can't be made very big, like, you're never going to get an SD card of it. You'd normally only use NVRAM for some persistent settings and stuff, totaling maybe, like, a few megs, on something like a whole-ass PC? Idunno, what would you store that's not on fixed storage (HDD of whatever sort)..?)As for persistent storage, HDDs and whatnot, it's always been a matter of wear and longevity; no HD lasts forever, whether that's due to failure of the media, electronics, or corruption caused by software. Backups and regular replacement are just SOP. You can get lucky, sure, there are half-century old HDDs with good data on them still spinning -- but it's the exception rather than the rule, and they also hold a truly negligible fraction of the data preserved nowadays (MB vs. TB in a single unit!).Tim

author: mawyatt
author_rank: Super Contributor
timestamp: January 29, 2022, 03:56:27 pm
content: Whatever happened to the HP/AG research into the "Memristor"Best,

author: Siwastaja
author_rank: Super Contributor
timestamp: January 29, 2022, 05:29:10 pm
content: Battery-backed SRAM is still a thing. Thanks to EEPROM and flash, not as much as it used to be, but still.Reason is simple: many applications require real-time clock. To have that, you need to run 32.768kHz crystal and clock at least a few dozen logic gates and registers to keep time, and this will require significant enough power to require a battery cell. Total solution cost and PCB area is already significant.Once you have all that, adding a kilobyte of SRAM comes for almost free, relatively speaking. Both from price and power perspective.This battery-backed RAM is available in many microcontrollers that come with RTC peripheral.Even simple external RTC chips come with a few user accessible registers if not kilobytes of RAM.Writing to flash quickly at powerdown is problematic. Erase cycles take time and power beyond the capability of small electrolytic or MLCC capacitors. Battery-backed SRAM is trouble-free, at least until the battery finally is drained and then it becomes a trouble generator.

author: PlainName
author_rank: Super Contributor
timestamp: January 29, 2022, 09:42:17 pm
content: I have a programmable mains timer which uses a tiny NiCd cell to maintain memory. So long as it's plugged into the mains once a year or something it's fine. Worst case, you shove it in a drawer for so long that the battery actually runs flat, but then you just leave it plugged into the mains for a few hours to recharge, and then you can hide it down the back of the sofa for another year.Flash is OK, but look at Tesla - writing to flash like it was SRAM with the result that cars were borked after not very long at all. You'd think the designers would know what they're doing, but apparently some of them had never heard of flash wearing out. Result: they were made to recall 158,000 cars to fix...

author: Benta
author_rank: Super Contributor
timestamp: January 29, 2022, 10:19:56 pm
content: Quote from: Siwastaja on January 29, 2022, 05:29:10 pmAbsolutely true.But a cost factor also came into play: the EU RoHS directive.This banned built-in NiCd cells in RTC/RAM modules (like Dallas used to offer), so a separate cell holder clip is also needed.

author: Rick Law
author_rank: Super Contributor
timestamp: January 29, 2022, 10:37:13 pm
content: Quote from: TerraHertz on January 29, 2022, 03:10:20 amI use a cheapo $15 USD B3603 digitally controlled CC/CV as my bench supply. The thing still "works" except it will no no longer store calibration data. It still "works" only in the sense that if I ignore the build-in display and use external DMM for V/I display. After testing it every way I can think of, my conclusion is that the EEPROM or flash base calibration data storage failed.That is what made me think why not CMOS to begin with. If only the calibration storage hasn't fail...I had a few of them. I am now using another B3603 purchased around the same time. Perhaps "planned obsolescence" is exactly the reason... I could replace the MCU, but then I would need to bring the firmware over. Yeah, not a thing user can easily do. I am keeping that failed one for part. I got my money's worth out of it even with "planned obsolescence", but still, it is such a garbage-creation unnecessary waste.

author: retiredfeline
author_rank: Frequent Contributor
timestamp: January 29, 2022, 10:41:23 pm
content: Quote from: Benta on January 29, 2022, 10:19:56 pmI have some of those ancient things. They are lithium cells and non-rechargeable.

author: David Hess
author_rank: Super Contributor
timestamp: January 30, 2022, 03:02:07 am
content: Quote from: Ian.M on January 29, 2022, 10:51:17 amThat is an apples to oranges comparison because the Flash memory you are describing does not qualify as RAM in the same sense of random access memory that SRAM does. EEPROM qualifies though and is much more comparable to SRAM.SRAM could be preferred to EEPROM, and by extension all Flash memory types, for performance and endurance reasons.

author: Kim Christensen
author_rank: Super Contributor
timestamp: January 30, 2022, 05:11:52 am
content: Quote from: Rick Law on January 29, 2022, 10:37:13 pmSounds like a bad design or something. I mean, how often would it need to update the calibration data anyway? Usually the only time it would write to the flash would be when you put it in calibration mode and ran through the calibration procedure. Otherwise, it's just reads the Cal data from the flash which doesn't cause wear...

author: Rick Law
author_rank: Super Contributor
timestamp: January 30, 2022, 06:02:14 am
content: Quote from: Kim Christensen on January 30, 2022, 05:11:52 amBad design - I imagine so as well. It has other quirks to make me think the design isn't great. It however did the CC/CV very nice.It also stores output settings so it can reboot and auto restart the output to prior setting, so there is more EEProm/Flash writes than just calibration. Even with that, I am very doubtful I changed the output voltage or current limit thousands of times to wear out the non-volatile memory (EEProm or flash) in about 4 to 5 years.I will see how long my replacement lasts. For a cheapo, I considered it very durable at 4 to 5 years of regular use.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 30, 2022, 02:13:31 pm
content: I guess no one's extracted/RE'd the original to tell, but there appears to be a replacement:https://github.com/baruch/b3603Question, is the setting persistent, i.e. you set it to 5V 1A, turn it off, come back the next day it's still on 5V 1A? If so, then that's probably wearing NV memory.Tim

author: Siwastaja
author_rank: Super Contributor
timestamp: January 30, 2022, 04:51:37 pm
content: Quote from: Rick Law on January 30, 2022, 06:02:14 amFlash works perfectly for storing calibration data. It has to store the firmware, anyway. The very same flash technology then stores calibration data. If the flash fails, you are doomed anyway. But longevity of MCU internal flash is very well tested and though out, it's many many decades at very least if not over a century. There are very little failures in early flash-based MCUs from the 1990's, OTOH nearly 100% of battery based SRAM from the same era have died already. If the SRAM holds factory calibration or other vital data, the units are bricked.Battery-based SRAM storage is at least an order of magnitude more finicky, easier to get wrong, and even with everything done right, will die in 10-20 years.Your unit just failed, because crappy design can always fail for whatever reason. Changing to fundamentally more unreliable technology will only make it even less reliable.

author: Bassman59
author_rank: Super Contributor
timestamp: January 31, 2022, 04:11:10 am
content: Quote from: Kim Christensen on January 29, 2022, 05:50:48 amDallas also made the DS5000T, which was an 8051 that used battery-backed SRAM as the program memory. You could also write to the program memory with a PC serial port which was handy back when the alternative in the late 1990s was a windowed EPROM.It was specified to keep the program valid for at least ten years without power applied, and longer if the system was powered up.I inherited a project that used this part back in 1997. It worked as expected. I probably should have asked the expected lifetime of the instrument that used the part, as by now the battery is surely dead.

author: Berni
author_rank: Super Contributor
timestamp: January 31, 2022, 06:37:17 am
content: Batteries are horrible, please don't start putting them into products again.There are non rechargeable cells that once dead render the entire product dead while rechargeable cells have way less capacity while still eventually wearing out and going dead, sometimes even leaking toxic corrosive goo over the board. Okay rechargeable cells can actually live a long happy life, but that is only in a favorable environment of stable temperature and regular consistent use, yet not all products gets used like that (leaving them over discharged can kill).There is test equipment out there using these battery backed Dallas SRAM chips, some of it holds valuable calibration data or even firmware that you really don't want to loose so you have to keep replacing them and keep a backup.So what to use instead?EEPROM and NOR Flash can actually live a really long time as long as you are not constantly writing large amount of data every second of every day.But what if i need to write 10KB every 100ms?Then just buy some FRAM memory. It writes really fast compared to Flash and has so much write endurance that you might as well treat it like it is SRAM. The thing is that FRAM is more expensive than the cheap high capacity NAND flash that factories are pumping out by the ton for SSDs, memory cards, phones etc.. This kind of flash memory is the crappiest flash out there (it focuses on maximum density) and due to its low cost ends up becoming the main storage memory of embedded systems. Since the embedded system already has lots of flash memory they will tend to also use the same memory chip for configuration. If you are careless with your Linux image then you can end up with the OS writing a lot of unnecessary garbage in flash while running. This not only wears the flash much quicker but can sometimes even cause the filesystem to crap itself on a hard power loss, bricking the device.

author: harerod
author_rank: Frequent Contributor
timestamp: January 31, 2022, 06:11:54 pm
content: Quote from: Siwastaja on January 29, 2022, 05:29:10 pmFULLACK, let me add real quick: The backup battery only needs to deliver power, while all other power is off. I have done designs which can use either a supercap or a CR2032. The latter is cheaper during production and holds more charge, the former may result in a longer design life/service cycle.https://en.wikipedia.org/wiki/SupercapacitorEdit 220201: Let me share a story from the glorious days of battery buffered SRAM. We are writing the year 1998. The straddle carrier drivers of a certain Irish port went on strike. To emphasize their demands, they pulled the buffer batteries from all the Siemens S5 PLC's and threw them away. These PLC's were the brains of those machines, located in a locked cabinet in the driver's cabin. Their memory held program data and machine specific calibration data. I can't remember how many machines were standing around, dead in their tracks, blocking access to the container stack. Hunks of 56t of steel, 14m high, 6m wide, 13m long. Some poor bastard had to get out to each one, climb up with a handy 13kg mobile programming device and set things up again. Guess how I know. (The attached pictures were taken at other ports.)

author: tom66
author_rank: Super Contributor
timestamp: February 01, 2022, 09:39:35 am
content: Quote from: TerraHertz on January 29, 2022, 03:10:20 amNonsense. See test equipment with Dallas battery-backed CMOS modules that die after 20 years. Yet you would never call that "planned obsolescence"The real reason is flash memory is cheaper than RAM+battery connector+battery.Plus good flash memory (most is good now) can last longer than any battery-backed CMOS ever did. Decades, even if written once a day with wear levelling. And likely 100 years if never written after factory init.

author: Bassman59
author_rank: Super Contributor
timestamp: February 01, 2022, 03:53:20 pm
content: Quote from: Berni on January 31, 2022, 06:37:17 amWe use FRAM for non-volatile parameter and calibration storage and it's dead simple to manage and ultra reliable.As for "expensive," I suppose that it's cheaper than a battery-backed SRAM and its lifetime exceeds ours

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 01, 2022, 04:30:46 pm
content: Quote from: Siwastaja on January 29, 2022, 05:29:10 pmAnother use of battery-backed RAM that's going the way of the dodo is on RAID disk controllers. These typically have several GB of RAM that's used as a cache. If the power fails, all of the dirty data still in the cache will not be written to the disk(s) and this can lead to data loss and filesystem corruption. The traditional solution was to put a battery (NiCad at first, then NiMH, and then Li) on the controller and use it keep the RAM powered until power was restored, after which the contents of cache would be written to the disk(s). When I was at LSI working on MegaRAID controllers, we typically sized the batteries to power the cache RAM over a three-day weekend (which we considered the worst case). These batteries were much bigger than a coin cell, and were a major headache for operators of big data centers because the batteries would have to be replaced every few years.The solution to the battery replacement problem was to move to a new approach where the battery is replaced by a supercapacitor and FLASH. The supercap stores enough charge to power the board for around 30 seconds, which is enough time to write all of cache RAM to FLASH. After that the controller could stay powered down indefinitely without losing data. When power is eventually restored, the controller will write the contents of the FLASH to the disk(s).

author: Ian.M
author_rank: Super Contributor
timestamp: February 01, 2022, 04:31:29 pm
content: FRAM has its own issues - reads are destructive i.e. during or after every read cycle the on-chip controller *MUST* re-write the location to preserve the contents. If power glitches during a read cycle or drops out of spec, you can expect data corruption. e.g.https://www.eevblog.com/forum/projects/the-other-downside-to-fram/

author: David Hess
author_rank: Super Contributor
timestamp: February 01, 2022, 09:49:49 pm
content: Quote from: Sal Ammoniac on February 01, 2022, 04:30:46 pmBefore Flash memory existed we hadSONOSwhich is what I used to replace the Dallas NVSRAMs in my Tektronix 2440 DSO. It consists of a SRAM array in parallel with an EEPROM array and when power is lost, the entire SRAM array is copied into the EEPROM array in one step.https://www.infineon.com/cms/en/product/memories/nvsram-non-volatile-sram/

author: David Hess
author_rank: Super Contributor
timestamp: February 01, 2022, 09:50:51 pm
content: Quote from: Ian.M on February 01, 2022, 04:31:29 pmAnd FRAM requires a precharge cycle on every read so it is not always a direct replacement for JEDEC SRAM.

author: james_s
author_rank: Super Contributor
timestamp: February 03, 2022, 09:46:27 pm
content: Quote from: David Hess on February 01, 2022, 09:50:51 pmThat's the issue I ran into. On a hardware level it is a direct replacement, but the software must be designed to meet the specific needs of FRAM.

author: coppice
author_rank: Super Contributor
timestamp: February 03, 2022, 10:02:43 pm
content: Quote from: Ian.M on February 01, 2022, 04:31:29 pmEvery FRAM device I know of has elaborate "anti-tearing" hardware inside, to ensure no read or write cycle ever starts unless there is enough energy on chip to complete it. This is designed and tested to deal with extreme EMI induced noise, as well as the power simply turning off. So, if you ever get corruption of an FRAM's contents, which you are certain was not due to the rest of your system doing dodgy writes when the power isn't clean, complain to the vendor.

author: David Hess
author_rank: Super Contributor
timestamp: February 03, 2022, 10:09:50 pm
content: Quote from: james_s on February 03, 2022, 09:46:27 pmI would not call it a software issue. In practice it means that at the hardware level, -CS (chip select) must be toggled between every read access which is what activates precharge on a FRAM. On a SRAM there is no such requirement and in some systems, continuous reads are done without togging chip select so those will not work with FRAM.

author: Benta
author_rank: Super Contributor
timestamp: February 03, 2022, 10:28:28 pm
content: Quote from: David Hess on February 01, 2022, 09:49:49 pmSONOS blahblah. Infineon marketing.The nvSRAM was made by ZMD (later ZMDI, acquired by Infineon at some point). Brilliant parts. IIRC, a US company was following the same idea, but I don't recall the name.That Infineon presents itself as the great inventor here is laughable.

author: srb1954
author_rank: Super Contributor
timestamp: February 03, 2022, 11:35:32 pm
content: Quote from: Benta on February 03, 2022, 10:28:28 pmXicor had a chip, the XC22C12, that did this function nearly 30 years ago. It was quite small at only 1kbits but would still have been useful in many small systems.

author: Berni
author_rank: Super Contributor
timestamp: February 04, 2022, 06:42:20 am
content: We have FRAM chips that work like SRAM these days, like the Cypress CY15B102N:https://www.infineon.com/dgdl/Infineon-CY15B102N_2-Mbit_(128K_X_16)_Automotive_F-RAM_Memory-DataSheet-v05_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecf917749edPage 8 of the datasheet clearly mentions it as being a SRAM drop in replacement by using what they call "Page read" mode with no limitation of actually staying within a page or column, but you can increase the speed if you access it in the way the FRAM finds it convenient.Not like parallel bus FRAM is all that relevant these days. Modern designs use MCUs that have everything they need inside so running a async memory bus on a PCB has fallen out of fashion due to the huge number of pins and board space it requires. So if you are going to use FRAM these days it will likely be SPI or QSPI interface. It still runs plenty fast (you can get 500Mbit/s from 133MHz QSPI) while they act pretty much like SPI SRAM where you can just start writing/reading at any location and keep going until the end of the memory area.This detail is only really a factor in retrofitting battery backed SRAM with FRAM. I did replace all the battery backed SRAM chips with FRAM in a HP 3458A and it ran great, but in some of the other gear just sticking in FRAM indeed does not work due to how the CS is used and how fast the memory is running.

author: james_s
author_rank: Super Contributor
timestamp: February 05, 2022, 08:25:48 pm
content: Quote from: David Hess on February 03, 2022, 10:09:50 pmAll of that is determined by software, at least in the systems I've seen. It would be easy enough to write the firmware to toggle the CS line between every access.

author: David Hess
author_rank: Super Contributor
timestamp: February 06, 2022, 12:16:35 am
content: Quote from: james_s on February 05, 2022, 08:25:48 pmI have never seen a system that allows firmware to change that behavior. Decoding the high part of the address in hardware produces the chip select signal so repeated accesses to the same chip may or may not toggle chip select depending on exactly how the decoding is implemented. Some systems always toggle chip select between accesses and some do not when sequential accesses are to the same chip.What software could do is perform a read to a different chip between accesses to the FRAM, but this would fail for multiword accesses which would just have to be disallowed.None of this matters in a legacy application. Either it works or it doesn't because nobody is going to be modifying the firmware to fix it.

author: Berni
author_rank: Super Contributor
timestamp: February 06, 2022, 08:29:51 am
content: Yeah for system that use a parallel interface SRAM chip are typically legacy ones that have the CPU sitting directly on the memory bus, using that bus as its main memory. Some CPUs can do the CS correctly some cant. Lots can likely be fooled into doing it by inserting an read instruction from somewhere else in memory as the data bus is typically the same number of bits as the native word size of the CPU. What would be problematic is trying to run code from this FRAM as its impossible to avoid reading it in sequence.That being said the FRAM chip i mentioned above does not need the CS to be toggled in order to work. You just get a speed penalty of running at about 1/3 full speed if you use like like SRAM. Even with that speed penalty this particular chip can run at 10MHz so still fast enough for most such legacy systems.

author: cortex_m0
author_rank: Regular Contributor
timestamp: February 06, 2022, 01:33:48 pm
content: I worked on a product a few years ago that had ~200 bytes of configuration, plus some diagnostic logging, stored in an EEPROM (CAT24 type).The EEPROM chip was rated 1 million erase/write cycles. Presumably that's actually per page, but let's assume it's for the whole chip. At 1 write cycle every hour, that's 114 years of continuous operation.So as long as the firmware isn't treating a memory like that as a scratchpad, the limited write cycles are not a problem.

author: PlainName
author_rank: Super Contributor
timestamp: February 06, 2022, 02:11:28 pm
content: QuoteEveryone seems to quote something similar to this, but the fact is it's misleading. If you're using the storage to save config on shutdown, you're not doing one write cycle at all but however many bytes/pages/whatever your config takes up.QuoteThis is the crux of it, and Tesla shows that even competent professionals get it wrong sometimes. Not to mention:QuoteOh boy! That kind of thing is just asking to wear out a chip in next to no time. When things go wrong you tend to get lots and lots of the same error sprayed at your logging console. OK, you say, it's not going to be the same as debug info, but on the other hand there isn't going to be a developer sitting there to pull the plug when it starts shouting, just some user who perhaps helpfully will be turning it off and on rapidly.I am not saying it's always like that (and, indeed, you sound like yours was as designed), but these are areas that tend to catch developers out until after they realise they've made a mistake, which is generally a bit late.

author: David Hess
author_rank: Super Contributor
timestamp: February 06, 2022, 03:46:53 pm
content: Quote from: Berni on February 06, 2022, 08:29:51 amThe JEDEC specifications for parallel access memory do not require toggling the chip select line between accesses. Common FRAMs violate this so they are not JEDEC compliant. This only became a problem when FRAM became available.QuoteExcept for 8-bit processors, most of the legacy systems I have seen have a data bus width smaller than the CPU word length so routinely generate multiple memory cycles for the same access.QuoteIt has a 90 nanosecond worst case access time after an address change initiated pre-charge so should work fine in most legacy JEDEC SRAM replacement applications.

author: cortex_m0
author_rank: Regular Contributor
timestamp: February 06, 2022, 04:56:49 pm
content: Quote from: dunkemhigh on February 06, 2022, 02:11:28 pmTesla wouldn't be my first example for a company which puts quality first... as a long-time Chrysler owner, it must take serious ignorance of the matter tofall below Fiat-Chryslerin initial quality metrics.Tesla was using eMMC, which has several orders of magnitude fewer rated write cycles - perhaps 1000 to 5000 depending on the manufacturer and density. Doing one write per hour to eMMC is very different - under the same rules of estimation I used above, eMMC would last less than one year.

author: PlainName
author_rank: Super Contributor
timestamp: February 06, 2022, 05:13:08 pm
content: fair enough