I'm going to try FPGA for the first time - question - Page 1
Forum section: electronics / general

author: alank2
author_rank: Super Contributor
timestamp: July 25, 2016, 06:35:12 pm
content: I've seen the example project at Grant Searle's site here:http://searle.hostei.com/grant/Multicomp/index.htmlAnd I'm going to order this here:https://www.amazon.com/RioRand-EP2C5T144-Altera-Cyclone-Development/dp/B00LEMKR92#Askhttps://www.amazon.com/gp/product/B00IRODADK/ref=ox_sc_act_title_1?ie=UTF8&psc=1&smid=A240XKQA2DV1DPQuestion #1 - once you program this with the USB blaster, does it stay? If you power cycle it, will it remember the way it was programmed?Question #2 - I've been watching some VHDL tutorials on YouTube. Is VHDL a language designed to prevent someone from having to lay out the gates manually? Much like C is to assember, VHDL is to the gates themselves?Any other ideas or tips for someone just starting out with FPGA? I'm familiar with AVR's...

author: rstofer
author_rank: Super Contributor
timestamp: July 25, 2016, 06:42:14 pm
content: 1) There is an EPROM on board so, yes, the program should be retained. BUT... You will probably be given a map of the JTAG chain and you get to choose which device (EPROM or FPGA) you wish to program. During development it is common to just program the FPGA because you don't care if you lose the program and it is generally faster to program. You program the EPROM when you want to save the program.2) Verilog and VHDL are both hardware descriptive languages. They describe hardware, that's all. For some toolchains you can still do schematic entry. That tends to take a long time...I like to think of VHDL as a Pascal like approach to hardware description. To me, Verilog is more like C.

author: Neilm
author_rank: Super Contributor
timestamp: July 25, 2016, 06:53:07 pm
content: Schematic entry and VHDL/Verilog will be synthesised (think compiled but it isn't) into logic terms. These are then fitted into the FPGA by the place and route procedures.I would tend to avoid schematic entry as this is usually locked to the suppliers tool chain, so if you change supplier you have to re-enter the logic from scratch. With VHDL and Verilog you just change any manufacturer specific commands and re synthesize.

author: rstofer
author_rank: Super Contributor
timestamp: July 25, 2016, 06:53:35 pm
content: One thing to think about: Put a 330 Ohm resistor in series with every pin you bring off the board. Such a low resistance on an output probably won't impact external circuitry, especially if it is CMOS but the resistor will protect the FPGA pin should you accidentally short an output.

author: alank2
author_rank: Super Contributor
timestamp: July 25, 2016, 07:06:27 pm
content: Are FPGA's pretty touchy to a short? I've used AVR's for years and never killed a pin though I have shorted an output a few times for sure.

author: rstofer
author_rank: Super Contributor
timestamp: July 25, 2016, 08:45:59 pm
content: Well, the boards tend to cost a lot (a whole lot more than the one at Amazon) and I certainly wouldn't want to let the magic smoke out. Most of the newer Digilent boards have the resistors on every pin leaving the board (at the PMOD connectors).Are they more sensitive than AVRs? I have no idea. For the cost of some resistors, I hope to avoid the question.Digilent isn't totally consistent: They don't do it here:https://reference.digilentinc.com/_media/cmod_a7/cmod_a7_sch.pdfThey do it here (using 200 ohm resistors):https://reference.digilentinc.com/_media/basys3:basys3_sch.pdf

author: hamster_nz
author_rank: Super Contributor
timestamp: July 25, 2016, 08:51:48 pm
content: I've accidentally shorted unprotected pins many times, with no ill effect. The outputs are current limited to about 50mA (at least for those I have tested). They seem to be pretty robust for the performance that they offer.However some of that robustness might come from the power supplies being used. Most of the boards have pretty advanced regulators on them which can shut down quickly, I imaging it might be very different if it was being powered by a 10A PSU...

author: Kilrah
author_rank: Unknown
timestamp: July 25, 2016, 09:05:32 pm
content: Quote from: rstofer on July 25, 2016, 08:45:59 pmDigilent offer both "Standard PMOD" that has the resistors and "Hi-speed PMOD" on which signals are routed as differential pairs and don't have the protection resistors so as not to disturb high speed signals.QuoteQuote

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 25, 2016, 11:09:54 pm
content: As an FPGA beginner myself, here are my thoughts. First, going for the cheapest board available, unless you're a starving student, is rarely a good idea. I suggest you consider a board from a more established vendor with a few more built-in peripherals and I/O devices. You'll pay more, but you'll have more options and better quality. Look at Digilent and Terasic -- they both make quality boards that are well-supported.It's best, too, to go with a board with a recent FPGA. Some cheap boards use older FPGAs that have limited support. Same goes for the tools. For example, Xilinx no longer updates their ISE software--they've moved on to Vivado. Unfortunately, Vivado doesn't support the Spartan series, so you need at least an Artix.As far as choosing an HDL, you can't really go wrong with either Verilog or VHDL. VHDL is more Ada-like while Verilog is more like C. Verilog is easier to learn, but VHDL has better type checking and won't let you make mistakes as easily as Verilog will. I myself prefer Verilog as I like its more concise syntax better. With either of these, you typically don't lay out gates directly--the synthesis tool does that. You describe the functionality of the circuit at a higher level. For example, the Verilog statement c <= a + b; will infer an adder and place it into your design--you don't have to specify the adder at the gate level. Whichever HDL you choose keep in mind that these arenotprogramming languages--these are languages used to describe hardware. If you try to write algorithmic code in Verilog or VHDL like you would in C, you're going to find yourself in a world of hurt. Your designs will be inefficient and probably won't even synthesize.

author: alank2
author_rank: Super Contributor
timestamp: July 26, 2016, 02:29:04 am
content: Do you get a choice between VHDL and Verilog? Or is that choice made by which brand FPGA you select?

author: george.b
author_rank: Frequent Contributor
timestamp: July 26, 2016, 02:35:36 am
content: Quote from: alank2 on July 26, 2016, 02:29:04 amYou can choose alright, it's not a brand thing.

author: Kilrah
author_rank: Unknown
timestamp: July 26, 2016, 08:05:47 am
content: Every manufacturer's software I've seen can take and use/generate both VHDL and verilog.I agree with going with a recent device and tools if you want to learn something that you can put to use efficiently afterwards. Obviously the advantage of that board is that it's exactly what the creator of the project you're interested in has used so you might be able to get it working faster and wih less effort than if porting it to another board - BUT that is not a given, since in this world it can be a bigger pain to port things between 2 different development tool versions than different hardware...

author: pix3l
author_rank: Regular Contributor
timestamp: July 26, 2016, 08:29:03 am
content: I've used Lattice FPGAs which can be programmed (or described ;-) in both Verilog and VHDL

author: Buriedcode
author_rank: Super Contributor
timestamp: July 26, 2016, 12:54:46 pm
content: The board you linked is similar to one I have, which is a bare basic FPGA, with config memory, all IO's broken out, and 128MBbit SDRAM. You'll notice it has two 10-way IDC headers, one is for JTAG - directly configuring the FPGA, and one is for AS - programming the configuration device. If you use the JTAG one, it'l configure the FPGA but won't remember configuration on power-up, it will instead read the onboard config chip. This is handy for development because as far as I am aware, there is no limit as to how many times you can do this. If you want the configuration to be permanent - so it 'remembers' your design, and loads it in on power up, you'll want to plug your USB blaster into the other header 'AS' (active serial) which puts the config in non-volatile memory.As others have said, whilst a nice bare board is probably all you need, it does make life difficult, especially if you're just starting out, because you could make a very complicated design... but how would you know it works? You'll need to hook up outputs, LED's, display, dedicated serial output etc.. and inputs like buttons, otherwise it is essentially a 'black box' that gives you no real indication of what its doing and whether your design is functional. Some bells and whistles aren't really needed, many go overboard with multiple displays, VGA out (which is actually quite handy) endless switches etc..Also, with FPGA's as you probably know, whilst there are dedicated functions on some pins, for the most part, you have to manually assign each pin in your design. If you have a few LED's, and a button, fine, but as soon as you start adding things like external memory, buses, assigning pins gets old real fast. You can import assignments into Quartus but even then you have to manually assign the pins at first and manually export. So if you can find a board that is widely used, there will be multiple example projects, assignment files (so you can load in a file for that board and it knows what is connected to what) and support. I highly recommended you get something like the DE-0 nano:http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=593There are many example projects to get you started, both in VHDL and verilog, and all the support files (assignments). It will save you a lot of time, at the expense of possibly shielding you from some of the donkey-work involved. But at least it lets you focus on writing HDL. Don't make the mistake I did and start of with a very cheap board. It'll be functional, but you'll spend just as much time checking pinouts with a multimeter and hooking up external boards as you will developing modules.Edit: Forgot to say back in uni we used VHDL and used it for some later projects of my own. I switched to verilog because frankly, it *is* C-like, but it isn't really 'code', its a hardware description language, you can't think of it as 'C', more a C-syntax-like-way of describing behavior. It also seems to have better support in Quartus for simulation, but only in specific areas that you probably won't use anyway.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 26, 2016, 01:05:45 pm
content: Quote from: Buriedcode on July 26, 2016, 12:54:46 pmThe normal development flow is to program the FPGA RAM during development, for speed. In some cases ( e.g. lattice EC) it is possible to use the same programming header to program external flash - the programming software first loads a simple bit file into the FPGA which maps the programming port pins to the serial flash device, to allow access through the FPGA I don't know if Xilinx or Altera support this on any of their devices.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 26, 2016, 05:15:56 pm
content: Quote from: mikeselectricstuff on July 26, 2016, 01:05:45 pmThis is exactly how it works for Xilinix FPGAs too.

author: alank2
author_rank: Super Contributor
timestamp: July 26, 2016, 06:38:03 pm
content: Is the U3 on the backside of the board the EEPROM for holding the program then?

author: bingo600
author_rank: Super Contributor
timestamp: July 26, 2016, 07:44:10 pm
content: Alan i did this course -Using a mix of MAX240 board , the same fpga board as you , and a S3Ehttp://www.pyroelectro.com/edu/fpga/http://www.pyroelectro.com/forums/viewforum.php?f=26It was nice to get experience with VHDLI'm using Altera Quartus 13.0sp1 - Anything newer didn't have support for the older CPLD's/Bingo

author: alank2
author_rank: Super Contributor
timestamp: July 26, 2016, 07:56:05 pm
content: Hi Bingo!Quote from: bingo600 on July 26, 2016, 07:44:10 pmAre these free? They look pretty nice.Quote from: bingo600 on July 26, 2016, 07:44:10 pmThis is the version that Grant's site talks about as well - I need to download it but it is many GB!Thanks,Alan

author: bingo600
author_rank: Super Contributor
timestamp: July 26, 2016, 07:59:56 pm
content: Yepp the course is free , and Chris would prob. review your ansvers if you posted them.I did upload my solution to most of the homework to.Ohh this VHDL book is free :http://freerangefactory.org/http://freerangefactory.org/books_tuts.htmlhttp://www.gstitt.ece.ufl.edu/courses/eel4712/labs/free_range_vhdl.pdfFun .....The first time i have ever "compiled" my own book , to get the latest editionhttps://github.com/fabriziotappero/Free-Range-VHDL-book/Bingo

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 26, 2016, 08:23:43 pm
content: Quote from: bingo600 on July 26, 2016, 07:59:56 pmThis is one of the best books for learning VHDL. Highly recommended.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 26, 2016, 09:30:08 pm
content: Had a quick skim through that book & there is at least one aspect that is not explained well.It repeatedly describes statements in a process block as being sequential, implying sequential in time - the author even admits he can't quite get his head round this.What they are is a list of statements in order of increasingpriority, not time. Once I understood that, things became a lot clearer.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 26, 2016, 10:57:40 pm
content: Quote from: mikeselectricstuff on July 26, 2016, 09:30:08 pmThis is why a lot of good programmers have a hard time understanding HDLs and FPGAs -- they're stuck in a mindset where everything happens sequentially one step at a time.

author: rstofer
author_rank: Super Contributor
timestamp: July 26, 2016, 11:13:35 pm
content: Quote from: mikeselectricstuff on July 26, 2016, 09:30:08 pmYes, subsequent assignments refine prior assignments in a kind of priority scheme. But that's just one aspect. Consider the following clocked process where the assignments result in a sequence (ignore syntax):process(clk, In)A <= In;B <= A;C <= B;Out <= C;end process;Assume A,B,C & D are '0' and when you walk through 4 clocks, you will see the value of 'In' "sequentially" walk toward 'Out'. I see this type of code used quite often in Verilog and not so much in VHDL. Maybe I'm not looking hard enough.

author: hamster_nz
author_rank: Super Contributor
timestamp: July 26, 2016, 11:33:40 pm
content: Quote from: rstofer on July 26, 2016, 11:13:35 pmIt does show up in VHDL a bit. I've come to the conclusion that pretty much everything that can be re-written to "hide" this behavior should be, if only for the sanity of a newbie or when running step-by-step simulations.So your example of:Code:process(clk, In)beginif rising_edge(clk) thenA <= In;B <= A;C <= B;Out <= C;end if;end process;Is better described as:Code:process(clk, In)beginif rising_edge(clk) thenOut <= C;C <= B;B <= A;A <= In;end if;end process;Even though the end result is identical.For my code, I have a style of "where possible, never access a signal after it is assigned a new value, and if you do, put a "-- initial value" comment, just to let the reader know it is not the one that has just been assigned".Some people find this annoying and point out "but that is not how HDLs work! that is what makes it different from software! If they don't know about delayed assignment then they shouldn't be here".My reply is usually "Meh".

author: rstofer
author_rank: Super Contributor
timestamp: July 27, 2016, 12:15:21 am
content: Quote from: hamster_nz on July 26, 2016, 11:33:40 pmWell, it confused me the first time I saw it so I am on the lookout for similar code. It tends to mess with my thinking.The other thing that is important for newcomers is to make sure they have default values for signals manipulated within a state machine. I put them all right at the top and I try very hard to keep the list current as I move along. Lacking a default value WILL bite them in the butt.

author: alank2
author_rank: Super Contributor
timestamp: July 27, 2016, 12:17:03 am
content: I remember reading about different types of processes -was it implicit vs. explicit? One type was parallel and the other was more of sequential, is this right?

author: ale500
author_rank: Frequent Contributor
timestamp: July 27, 2016, 04:56:18 am
content: The order doesn't matter during synthesis, but it does during simulation because simulation is done sequentially.Don't forget simulation !, yes, you can synthesize and test that way your code, but you can also simulate your design and have a look at the waveforms. All these free fpga-suites come with a simulator, ModelSim or Active-HDL or something else. I use icarus verilog and works quite well but one should not forget that parts of the language cannot be synthesized !There are a number of gotchas you have to be aware of:The simulator lets you use the whole language, for instance $display, to show a formatted string, very nice for debugging, but you can't synthesize $display.You can (verilog) set to a register more than one in the simulation (buggy code), but the synthesizer will tell you that you are assigning more than once, something that is not possible with real hw !What I do is I use an editor and write the code, the testbench, simulate it with icarus verilog and use synpylfy (part of Lattice's Diamond software, I use mostly Lattice parts) to check for code that can be synthesized. Sometimes I simulate with Active-HDL (also part of Lattice's Suite). I find using icarus verilog fast and comfortable.Some people use Quartus and simulate there with ModelSim, your choice, it also works, read the manuals, it is a steep learning curve.If you already did the leds blink, and the 7 segment display show what you want, try reading some buttons, doing debounce, a simple UART, and so on. Leave the processors for later, specially the ones you may want to develop yourself. Start small, 4 bit processors can be very useful in showing how complicated finite state machines can control the outside worldHave fun !

author: Buriedcode
author_rank: Super Contributor
timestamp: July 27, 2016, 10:56:06 am
content: Quote from: mikeselectricstuff on July 26, 2016, 01:05:45 pmIndeed, and I prefer it that way. The board the OP linked used an older cyclone II, one that I'm using. It's about a decade old, but is still good enough for learning FPGA specifics, like using RAM blocks and developing SOC (NIOS II processor for Altera). Because of its age, it still can use the 'active serial' format of configuration, as well as JTAG, and I believe it can program the configuration device via the FPGA, via JTAG, but most basic boards I have seen don't use this facility, and just use separate headers for each one, rather than a chain. I guess this is for an easy life - this header for developing, this header for 'permenant'/.I think the newer Altera devices (as well as Xilinx, and lattice) have many more options with regard to configuration, some using generic flash rather than a config memory specific to devices, and have to be configured using the FPGA's built-in hardware.So, apologies if I confused matters, it wasn't a general thing about FPGA's, but rather specific to the cyclone II boards that are still all over ebay.

author: Bassman59
author_rank: Super Contributor
timestamp: July 27, 2016, 11:55:51 pm
content: Quote from: alank2 on July 27, 2016, 12:17:03 amThe two different types of processes are combinatorial and synchronous. The difference is that the latter is sensitive only to a clock edge, and as such the only signals you'll see on its sensitivity list are the clock and perhaps an asynchronous reset. The process suspends until a transition on the clock is seen, and the inside the process a test for the specific edge of the clock is made. That is, anif rising_edge(clk) thenstatement is the first line in the process (unless there's the async reset). Then it continues, evaluating each assignment and scheduling the left-hand side signals for assignment. The values of each signal on the right-hand side of each assignment statement is captured at the moment the process is triggered. And since you are using signal assignments, the signals on the left-hand sides of each assignment statement aren't updated until after all of the evaluations is complete. This is why theA <= B; B <= C; C <= D;pipeline works as it does and not like a newbie might expect. At the end of the process, the assignment targets update and the process suspends until the next clock edge.When you have multiple synchronous processes using the same clock, they are handled as if you've written one big process. Mind the rule that you generally cannot assign to a signal in more than one process and you won't run into problems.For a combinatorial process, you must put on the sensitivity list all of the signals which "wake up" the process. That means that anything that's on the right-hand side of an assignment must be in the sensitivity list. (Modern VHDL-2008 allows a catch-all in place of listing each of the signals).In both cases, then, the process suspends -- basically, waits -- until a transition is seen on any of the signals in the sensitivity list. Then the process awakens, the state of every signal on the right-hand side of all assignments is captured, and each of the statements in the process are evaluated in order.Once all assignments are evaluated and the signals updated, the process suspends, waiting for the next sensitivity list transition.There is an interesting variation on the process. You do not need to put any signals on the sensitivity list. In this case, the process wakes up immediately and starts evaluating and scheduling (but not completing) assignments. What happens when it gets to the last assignment? Easy, the process just goes back to the top. But -- time hasn't advanced, so the assignments you did the first time through the process are overwritten. Your simulator will complain about an infinite loop or some such error, and your synthesizer will perhaps throw a rod, too. You need to add a statement (or statements) which advances the time. You do that with await on foo;statement (wait until foo changes),wait until foo = '1';statement (wait until foo is assigned '1'), await until rising_edge(clk);statement (wait for a clock edge), or perhaps await for 100 ns;statement. You can do any of these sorts of waits in a test bench. For synthesizable code, obviously thewait for 100 ns;statement can't be used at all, and there are limits to how the other waits can be used. So for synthesizable code, it's best to stick with the first two idioms.

author: rstofer
author_rank: Super Contributor
timestamp: July 28, 2016, 12:46:06 am
content: It's important to point out that all of the above applies to simulation only (mostly). Synthesis doesn't care a whit about sensitivity lists (although it will mention missing signals) and logic gates are not waiting around for a process to kick off. Gates do their thing, clocks toggle D flops and everything moves on - in lock step.Until Vivado, it wasn't possible for me to use a simulator. I could have changed to Verilog and used one of the open source simulators but I figured I would just put that on back burner. For 12 years, I have used a simulator only once and then with Vivado for a simple circuit just to see how I should write a test bench.Simulation isn't hardware and I really don't care what the simulator thinks. I program the FPGA and let it tell me what it really thinks. A logic analyzer is critical. The new internal logic analyzer that comes with Vivado is very slick and even non-commercial users can use it! But, the logic analyzer is testing hardware, it is not a simulation. The fact that it is internal means I don't need to find an extra 32 pins to connect to a logic analyzer. Of course, it is also possible to port the logic analyzer code inside the project if I don't mind giving up the BlockRAM (or use SRAM if it is available).When I read books about Verilog and VHDL, I get disgruntled by the amount of stuff they put in the code that only works for simulation. It's like they're designing to simulate, not synthesize.

author: rstofer
author_rank: Super Contributor
timestamp: July 28, 2016, 12:52:03 am
content: One of the best reasons for synthesizing textbook examples is to look at the schematic view. You can see exactly how your logic will be implemented. Every signal, gate and flop will be shown. But it's really only useful for very small circuits. When you get to an FSA with 100 states and several thousand lines of code, it get really difficult to find what you are looking for.But for a new users, it's important to see how the synthesizer sets up muxes, ALUs, FSAs and so on. Simple ones...

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 28, 2016, 12:57:36 am
content: Quote from: Bassman59 on July 27, 2016, 11:55:51 pmThis may be true for simulation, but the way you describe it is not how hardware works when you synthesize VHDL or Verilog and program an FPGA. You make it sound like something is running a process and sequencing though a list of assignments that suspends from time to time. This isn't really how it works in hardware. The hardware is implemented with flip-flops, muxes, look-up tables, adders, etc., and while some of them may be clocked by a clock signal (the FFs), everything is happening all at once, although some things only change on a clock edge (such as FF outputs).

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 28, 2016, 02:09:30 am
content: Quote from: rstofer on July 28, 2016, 12:46:06 amDo you know of a good tutorial or video that describes how to use the Vivado internal logic analyzer?

author: rstofer
author_rank: Super Contributor
timestamp: July 28, 2016, 04:43:07 am
content: I don't know of a video but if you find one, post a link.Open IP Catalog and search for ila - you will see an entry for Debug & Verification -> Debug -> ILA (Integrated Logic Analyzer). Double click and follow the yellow brick road filling in forms.Vivado will add a bunch of constraints to the file (23 in my case) and when you program the device the ILA window will pop up. Use one of the 'trigger' buttons to get a 'logic analyzer' display.That is the sum total of my knowledge and it sure isn't much.

author: hamster_nz
author_rank: Super Contributor
timestamp: July 28, 2016, 05:05:27 am
content: I second using the build with an IP block route (rather than the "add probes after implementation" route that is also supported).The biggest advantage for this is that your source-level signal names are used, not some randomly generated internal net names. Also, as an IP block is used, the connection of the signal to the IP block prevents them from being optimized away (or at least adds static values), but in the 'add probes after implementation' route you can't find them because they are not there to find!Anyhow, this is an example of using a ILA IP block from VHDL - just remember that the more features you add to it, the larger the IP block and the slower the build will be!Code:COMPONENT ila_0PORT (clk : IN STD_LOGIC;probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);probe5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));END COMPONENT ;...i_ila_0: ila_0 port map (clk => clk,probe0(0) => ip_extracted_data_valid,probe1 => ip_extracted_data,probe2(0) => ip_extracted_data_valid,probe3(0) => tcp_hdr_valid,probe4(0) => tcp_extracted_data_valid,probe5 => tcp_extracted_data);

author: alank2
author_rank: Super Contributor
timestamp: July 28, 2016, 03:34:47 pm
content: Thanks for all the excellent information - this thread has been fantastic.I've got a few more questions:#1 - I see some fpga boards on eBay with only one programming header though they have an eeprom still. How would you program the FPGA vs. EEPROM on those?#2 - In general, how powerful are the I/O's as far a current?#3 - I've went through Grant's tutorial and it will compile and produce a POF and SOF file. Why is the POF so much larger?#4 - If I click on RTL or GATE sim, it says "You did not specify an EDA simulation tool". I thought it installed something called MultiSim for that perhaps. Any tips on how to get by this error? Will it show me a schematic of gates when I do?Thanks!

author: rstofer
author_rank: Super Contributor
timestamp: July 28, 2016, 04:28:22 pm
content: Quote from: alank2 on July 28, 2016, 03:34:47 pmJTAG works on a chain. There can be a LOT of devices on the chain and the programming software selects which device actually gets programmed. It has always been that way. The idea of two programming headers seems bizarre. There's something else going on besides JTAG...QuoteCheck a datasheet, it varies all over the place depending on what you want the pin to do. Look on page 14 here:http://www.xilinx.com/support/documentation/data_sheets/ds099.pdfI can't help with the other two questions. For some reason, I can't deduce what software you are using.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 28, 2016, 05:09:48 pm
content: Quote from: rstofer on July 28, 2016, 04:28:22 pmYes - like he said, access to a SPI flash memory, which doesn't talk JTAG

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 28, 2016, 08:15:14 pm
content: Quote from: alank2 on July 28, 2016, 03:34:47 pmSome FPGA tools (for example Xilinx's Vivado) will download a short bit of logic to the FPGA that knows how to interface with an external FLASH or EEPROM chip and then use that to program the memory.

author: Bassman59
author_rank: Super Contributor
timestamp: July 28, 2016, 08:51:08 pm
content: Quote from: Sal Ammoniac on July 28, 2016, 12:57:36 amI understand what happens when the synthesizer works on the code: you get flip-flops and muxes and gates and all that. That's why it's called a Hardware Description Language. And I was pretty sure someone would chime in and say, "sensitivity lists are ignored by the synthesizer." Which is true.But the point is that you should simulate and verify your code for logical correctness before you start thinking about implementation, and if you want your simulation to match synthesis results (and you do), then the simple rules about sensitivity lists and coding-for-synthesis style need to be followed.The FPGA designer needs to understand both simulation and synthesis. Using ChipScope for in-circuit debug is very useful, but having the simulations done beforehand means that you spend less time in that debug process.

author: Someone
author_rank: Super Contributor
timestamp: July 29, 2016, 12:09:24 am
content: Quote from: Bassman59 on July 28, 2016, 08:51:08 pmISE will happily make latches (and map them to latch primitives) if you leave some signals of a combinatorial statement out of the sensitivity list, so its not ignored. The typical "solution" is to have a soft rule that all sensitivity lists should be either a single clock edge:@ (posedge Clock)or the catch all combinatorial:@ (*)I'll leave the long arguments about async resets for another thread...Quote from: Bassman59 on July 28, 2016, 08:51:08 pmFor trivial projects the compile cycle may be so fast that working direct to hardware is quicker, and occasionally you see someone partition down a design to just the part they are debugging to build ity quicker. But I'd agree most of the verification and debugging is quicker and easier in simulation.

author: rstofer
author_rank: Super Contributor
timestamp: July 29, 2016, 04:50:58 am
content: In terms of simulation, I just couldn't get my head around trying to use it to debug a 300k gate equivalent project with multiple IO devices all connected to SRAM through a DMA channel. No SRAM, no data. No IO devices, no DMA activity, no IO for the CPU.Certainly, small blocks could be tested individually. Things like the USARTS, perhaps the DMA (although it is trivial), maybe some pieces of the IO structure. But simulating the entire CPU with 70 odd one-hot encoded states seemed daunting. In fact, it seemed like it would take more effort to write the test bench than just doing the Place & Route and running on real hardware with a logic analyzer.Maybe there's something in the simulation process that makes all the work worthwhile but I sure didn't see it.I view simulation with the same disdain I reserve for single-stepping through microprocessor code. I can get more debugging information with well placed printf()s than I'll ever get walking through the code for various values. It simply takes too long.Now, with the Integrtated Logic Analyzer included with Vivado, I can probe exactly the portion of the circuit I am concerned with. I can 'trigger' on a signal or event related specifically to the problem at hand. I don't have to wander through hundreds of lines of code hoping to find an error.I don't recall the exact problem but I remember trying to find a bug in the processor when one particular statement in the monitor code was being executed. This was hundreds of assembly language instrucions in from cold start. I added breakpoint capability to the hardware along with a single step capability and, voila', finding the problem was simple. Still time consuming but relatively straightforward. The monitor code was loaded from compact flash and the problem showed up during execution.

author: Kilrah
author_rank: Unknown
timestamp: July 29, 2016, 08:02:43 am
content: Yeah simulation of an entire system with I/O is impossible and there are better tools for it, but in the same way testing a purely internal component (an address decoder or whatever) with an ILA would be a pain, you'd have to create other parts just to test it, those parts may have their own bugs that could fool your results... while it's a piece of cake to verify it by simulation.The idea of simulation is to test every small component so that you're sure it will work once integrated in a bigger system rather than biting you in the rear when you try to debug code and the issue is actually a logic fault in the CPU.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 29, 2016, 02:27:16 pm
content: Quote from: rstofer on July 29, 2016, 04:50:58 amCompanies like Intel have hundreds (perhaps thousands) of engineers who specialize in validation of new chip designs before they hit the fab. These guys do it all day long and probably have very specialized tools to make their job easier.What makes this worthwhile is the high cost of making masks and having prototype chips fabbed. Make a few mistakes causing multiple spins and you've easily burned through several million dollars.

author: alank2
author_rank: Super Contributor
timestamp: July 29, 2016, 02:49:50 pm
content: Quote from: rstofer on July 28, 2016, 04:28:22 pmI am using Quartus II 13.0 SP1. It said something about MultiSIM... I would love to be able to see what it synthesizes somehow, especially when I start with a very small project like a simple clock or flip flop.

author: Kalvin
author_rank: Super Contributor
timestamp: July 29, 2016, 02:53:02 pm
content: Quote from: Sal Ammoniac on July 29, 2016, 02:27:16 pmSome companies use multiple high density FPGAs to emulate the ASIC and algorithms before it goes to production. The emulation speed may be only 1/10th or less of the actual ASIC, but the speed may be still a lot faster compared to a simulation running on a computer. Also some preliminary hardware testing can be performed, within the constrained speed, of course. Investing on high-density FPGAs (Like the highest-density Xilinx Virtex) costing tens of thousands of dollars each is well justified if one can get the working ASIC without any respins.

author: rstofer
author_rank: Super Contributor
timestamp: July 29, 2016, 03:17:52 pm
content: Quote from: alank2 on July 29, 2016, 02:49:50 pmI think MultiSIM is the simulator. I don't know how to get the logic diagrams in Quartus but see if Tools -> RTL Viewer works. Or try Google... I am fairly certain that the feature exists.

author: Kilrah
author_rank: Unknown
timestamp: July 29, 2016, 03:19:13 pm
content: A while ago someone posted a video of Nvidia's labs. They indeed had a hardware emulator, which apparently consisted of... a room full of racks full of high-density FPGAs, with a PCIe card sticking out at the end that is plugged into the test PC

author: Kalvin
author_rank: Super Contributor
timestamp: July 29, 2016, 03:32:28 pm
content: Quote from: Kilrah on July 29, 2016, 03:19:13 pmThanks. I guess this is the video:

author: alank2
author_rank: Super Contributor
timestamp: July 29, 2016, 03:59:24 pm
content: Quote from: rstofer on July 29, 2016, 03:17:52 pmI agree that MultiSIM is the simualtor - I saw that mentioned a few times, just don't know how to get it to load.The Tools -> RTL Viewer WORKS though - thank you!

author: spudboy488
author_rank: Regular Contributor
timestamp: July 29, 2016, 05:45:26 pm
content: It's Modelsim -https://www.altera.com/products/design-software/model---simulation/modelsim-altera-software.html

author: rstofer
author_rank: Super Contributor
timestamp: July 29, 2016, 05:49:44 pm
content: Quote from: alank2 on July 29, 2016, 03:59:24 pmIn the past, the simulator wasn't included in the free software. That's why I have never used one - I didn't have it! With Vivado, I do. But I still haven't come to grips with using it.ETA: If you get one of those books that starts out with simple logic circuits and works up, it is very helpful to look at the schematic. Just so you know what is actually being created...

author: Kilrah
author_rank: Unknown
timestamp: July 29, 2016, 06:12:31 pm
content: Quote from: rstofer on July 29, 2016, 05:49:44 pmOne of the good things to know is that a caveat of HDLs is that it's easy to create unwanted latches - so the first thing to look for in the schematic is that you don't see any flip-flops in places where you don't explicitly want some!

author: alank2
author_rank: Super Contributor
timestamp: July 29, 2016, 06:28:54 pm
content: Quote from: rstofer on July 29, 2016, 05:49:44 pmMaybe that is why I can't run it - I am using the free web edition...

author: rstofer
author_rank: Super Contributor
timestamp: July 30, 2016, 01:31:49 am
content: Quote from: alank2 on July 29, 2016, 06:28:54 pmGoogle around about it. It wasn't included with the free Xilinx WebPack ISE. Happily (maybe) it is included with the free version of Vivado.

author: alank2
author_rank: Super Contributor
timestamp: July 30, 2016, 02:19:22 am
content: I'm feeling pretty good tonight about accomplishing something! I was able to get Grant's awesome CP/M example up and running on the board I ordered and finally today after getting an SD (not SDHC!) memory card, I got it working, formatted with his tool, and running CP/M great.Just to see if I could - I got out my Saleae and starting tracing what the VHDL for the SD card controller was doing and began to try to tweak it for SDHC operation. This page was invaluable as was looking at his initialization code in C:http://elm-chan.org/docs/mmc/mmc_e.htmlOnce I implemented the CMD8 and modified the result part of the VHDL to process the extra 4 bytes it returned, I got the initialization sequence to work. After that it was just changing the addressing from byte to LBA and the SDHC now also works!My next plan will be to attempt to make a single VHDL that detects which type SD/SDHC and deals with each appropriately...Thanks for all the good information and help in this thread!

author: Someone
author_rank: Super Contributor
timestamp: July 30, 2016, 02:31:09 am
content: Quote from: rstofer on July 30, 2016, 01:31:49 amXilinx ISE has included a simulator for a long time, they switched from a bundled modelsim package to their iSim clone around 2010?? Its not great but it works and the price is right (free).

author: rstofer
author_rank: Super Contributor
timestamp: July 30, 2016, 04:45:05 pm
content: Quote from: alank2 on July 30, 2016, 02:19:22 amHow about a link for the Grant project? I'd like to see what it entails.About 12 years ago, I used the Opencores T80 core (Z80) to implement CP/M. I used a compact flash device to implement the full complement of maximum sized disks. I actually started out to use the T80 to implement PacMan but got sidetracked. Later on, I got PacMan running on another board but, alas, we don't have room for a table style video game. Maybe now that we have moved to a bigger place...I also implemented an IBM 1130 computer, still using the compact flash device because it has a simple parallel interface (and it's fast!). I have had it running for several years now.

author: Kilrah
author_rank: Unknown
timestamp: July 30, 2016, 04:55:29 pm
content: First post of this topic...

author: Buriedcode
author_rank: Super Contributor
timestamp: July 30, 2016, 05:54:34 pm
content: As an alternative to modelsim in quartus (there's a free version, but can be a pain to set up) you can use quartus simulator for waveforms that allows relatively straight forward stimulus of inputs - clock, high, low, arbitrary value for buses etc..Just create a new 'University program VWF' file, add the nodes you want to see and any inputs can be edited for states, transitions, clocks, then 'simulation -> run functional simulation'. Be sure to change the setting in simulation >options to 'Quartus II simulator'. I've been using that and its pretty quick and handy for fairly basic tasks. For qsys stuff I tend to use signaltap II to probe the bus and signals to/from peripherals. It's the only way I could get acustom master to read from the SDRAM controller - by looking at how the NIOS II did it.

author: bingo600
author_rank: Super Contributor
timestamp: August 01, 2016, 07:41:58 am
content: Quote from: alank2 on July 30, 2016, 02:19:22 amAlan could you upload a "diff file" for the SDHC part ?/Bingo

author: alank2
author_rank: Super Contributor
timestamp: August 01, 2016, 12:12:15 pm
content: Bingo, I'm working on a removable system right now for it. I can PM you the SDHC fixed disk version, or if you want to wait a couple of days, I'll have a 4 drive version where you can mount a virtual diskette in any drive. The virtual diskette can be up to your size in the SD card - for example - my 4GB card has 470 virtual 8MB diskettes. I've created a mount utility to manage mounting diskettes and it even has a way to mount by name using a file with number,name mappings:I'm hoping to try my hand at modifying where the OS loads to and can move it up making another 3K of program space next.Code:A>mountDiskette Mount Tool 1.00.Drive A: contains diskette 0 (SYSTEM).Drive B: contains diskette 1 (PASCAL).Drive C: contains diskette 2 (BDS_C).Drive D: contains diskette 3.So you could use:MOUNT B: PASCALorMOUNT C: WORDSTARorMOUNT D: 200Thanks,Alan

author: mubes
author_rank: Regular Contributor
timestamp: August 01, 2016, 12:16:22 pm
content: Back to the OPs' original Q; All this FPGA getting started talk whetted my appetite, so with three weeks vacation coming up I've finally taken the plunge...some thirty years after playing with GALs in University and thinking they were pretty cool. A poke around eBay led me to this, which is in the UK;http://www.ebay.co.uk/itm/Altera-Cyclone-IV-FPGA-Learning-Board-EP4CE6E22C8N-and-USB-Blaster-Programmer-/121897534832...there are cheaper sources for it in China, but it'll come quicker from up the road. Any comments on it? Be nice, I already clicked Buy Now. I realise the uncommitted I/O is limited, but 8 bit VGA, some LEDs, switches, a buzzer and some other bits will be well above my competence level for quite some time I should think.DAVE

author: Buriedcode
author_rank: Super Contributor
timestamp: August 01, 2016, 01:31:01 pm
content: That board should have everything you need to get started. Hopefully it'll come with a disk with example projects on it, and pin assignment files so you won't have to manually assign the pins for the memory. I actually have that board in my watch list.The only downsides I see are the lack of external IO - thats not much of a problem except when you start to have lots of interfaces, and the medium gate count. The EP4CE6 is the smallest device in the cyclone IV family, with ~6700 LE's, 270kbits of embedded memory (thats actually more than enough for most applications). If you're planning on using alteras microcontroller design, it will eat into the LE's quite a bit, but should still leave enough for custom applications - 6000 LE's is a LOT of logic, especially if you use the embedded dedicated memory blocks for large shift registers and FIFO's, then each LE will be used for actual logic.https://www.altera.com/en_US/pdfs/literature/hb/cyclone-iv/cyiv-51001.pdfI'm not sure I would use the VGA port, but a VGA controller is an excellent starter project (still working on mine!). All in all its rather basic, but *far* better than a bare board with just regulators and a programmer - some buttons and LED's even just a few are always handy for test outputs and just seeing 'whats happening' - something you really need to learn more complex HDL.

author: bingo600
author_rank: Super Contributor
timestamp: August 01, 2016, 02:40:43 pm
content: Quote from: alank2 on August 01, 2016, 12:12:15 pmAlan i'll just wait (thanx)/Bingo

author: mubes
author_rank: Regular Contributor
timestamp: August 01, 2016, 03:01:26 pm
content: @Buriedcode; there is a disk that comes with it, and I found some schematics at;https://svn.mavipet.sk/svn/fpga_tests/HW/ZRtech/...the PCB layouts seem to match what I can see in the pics. Only thing I wish it had is a SD card interface, so I guess that's where some of that uncommitted I/O will be going. The VGA port was indeed my idea for a starter project...we'll see how that goes!RegardsDAVE

author: mac.6
author_rank: Regular Contributor
timestamp: August 01, 2016, 08:54:29 pm
content: Quote from: Kilrah on July 29, 2016, 03:19:13 pmI didn't saw the GPU hardware labs while I was at Nvidia, but I worked on Tegra 4i fpga, it was a very big PCB with 8 (up to 10) big virtex (5 and 6 mixed) on it. It was running quite fast compared to Cadence dedicated simulators. The only drawback with this kind of fpga is that they are not always 100% timing accurate.

author: alank2
author_rank: Super Contributor
timestamp: August 02, 2016, 03:07:49 pm
content: What do files with .cmp and/or .qip accomplish?I can compile the VHDL without them and I don't get any errors.example cmp:Code:component CGABoldRomPORT(address: IN STD_LOGIC_VECTOR (10 DOWNTO 0);clock: IN STD_LOGIC := '1';q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));end component;example qip:Code:set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"set_global_assignment -name IP_TOOL_VERSION "13.0"set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "CGABoldRom.vhd"]set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "CGABoldRom.cmp"]