Voltage divider: from schematic to PCB layout - Page 1
Forum section: electronics / general

author: newtekuser
author_rank: Frequent Contributor
timestamp: February 26, 2024, 04:32:40 am
content: On the resistor divider setup in the schematic attached, KiCAD allows me to connect R2 and R3 with pin5 in any of the configurations from the screenshots below. If I connect the tracks according to the schematic, I go with the third option from my last screenshot, but gut feeling tells me it's not the proper way of connecting tracks mid-point.Can someone please confirm which form is acceptable/standard practice and which one is the proper way of connecting this resistor voltage divider (first, second, or third)?Thanks in advance!

author: wraper
author_rank: Unknown
timestamp: February 26, 2024, 04:46:15 am
content: Neither look good and layout provides very poor cooling for the IC. You should provide a larger snippet of the layout since voltage divider does not live in a vacuum. All of the layout is important, in particular how you arrange everything and from where to tap for feedback.

author: WillTurner
author_rank: Regular Contributor
timestamp: February 26, 2024, 05:57:50 am
content: I think you are worrying about something very minor in the larger scheme of things! There might be some design areas like precision electronics where you would be worrying about star-grounds and stuff, or like the previous poster said, power dissipation. I don't think these special areas will affect your design at this point.So, what we are talking about is stylistic variation? I wonder whether there are documents out there telling us what design styles are acceptable. On the other hand, you can try different things, come up with your own unique style, use some common sense, and most of all ... have funEdit: Also, I can see that you put a fair bit of work into your post. More than enough detail there for me to understand the issue.

author: newtekuser
author_rank: Frequent Contributor
timestamp: February 26, 2024, 06:16:08 am
content: Thanks all! So all three choices will work in terms of a functional circuit? Aesthetically I prefer the first two over the last one with the mid point track connection.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 26, 2024, 06:40:54 am
content: Yes as said above, the rest of the layout, which we don't see, is more important than this. Usually.I'll just add a small something though, while we're at it, about feedback for regulators, in particular switching regulators. When using high resistance values (which is your case here), the feedback potential will be susceptible to external noise.First, make sure such high values are *required* (for instance, for power consumption reasons if your design is very-low power), otherwise consider decreasing these values significantly. If power consumption requirements allow, dividing them by up to a 10 factor would not be a bad idea.After that, the layout part *may* itself matter, and not for aesthetic reasons. The proximity of the feedback resistors with the inductor, for instance, with these high values, may cause accuracy or stabiliy issues in the output voltage.Where does your +5V rail come from? If it may be noisy, then coupling to the feedback input could be an issue, and if you can't again decrease the value of the feedback resistors, routing the +5V trace differently and having some ground filling between it and the feedback input resistor (R3) may help.Long story short: the 3 alternatives you showed would not make any difference, but there's still a couple of things to say about feedback voltages. Just my 2 cents.

author: newtekuser
author_rank: Frequent Contributor
timestamp: February 26, 2024, 06:55:52 am
content: Quote from: SiliconWizard on February 26, 2024, 06:40:54 amThank you SiliconWizard! I'm attaching the PCB layout to this thread as well, it should answer some of your questions. Please feel free to offer any suggestions and thank big thank you!I did recently earlier today about downsizing the resistors and will be looking at that.

author: selcuk
author_rank: Frequent Contributor
timestamp: February 26, 2024, 07:31:46 am
content: PCB layout is fine. I don't see issues. But if I were you, I would-Make top and bottom pours as ground plane and use many vias to connect them.-Make ground current loops and switching current loops smaller.-Connect tracks to the regulator IC from the short edges of the pads. And use track widths no more than pad width itself. There are round dot shaped coppers on pads as if you connected them in a hurry. You may increase the track width after exiting the IC pads.

author: woody
author_rank: Frequent Contributor
timestamp: February 26, 2024, 04:54:05 pm
content: Quote from: selcuk on February 26, 2024, 07:31:46 amI like to use copper pours to connect small pads to larger tracks. (And yes, I realize that might be a bit OCD

author: wraper
author_rank: Unknown
timestamp: February 26, 2024, 05:26:05 pm
content: Quote from: selcuk on February 26, 2024, 07:31:46 amIt will work due to MC34063 being slow but it's not fine, layout is poor. For example routing narrow inductor trace through pin 7 makes no sense as it's a sense pin. Nor wiggling trace from pin 1. Component arrangement is no good and copper fill on top makes more harm than good, especially for the output.

author: wraper
author_rank: Unknown
timestamp: February 26, 2024, 05:46:20 pm
content: Also while on a first glance there is no particular recommendation for cooling SO-8 package in the datasheet,I assume that lead frame under the silicon die likely is a whole with GND pin 4,so for better cooling, it should be soldered to GND copper fill with no thermal reliefs. Especially considering that MC34063 is very inefficient for such boost application from low voltage.EDIT: I broke one apart out of curiosity and it's just a lead frame with all separate pins. Still making GND flood under IC would be better than 5V.

author: newtekuser
author_rank: Frequent Contributor
timestamp: February 26, 2024, 07:22:13 pm
content: Quote from: wraper on February 26, 2024, 05:26:05 pmThanks for the feedback!Can you please elaborate on the sense pin connection?The traces to the inductor are unnecessary long but that's due to the footprint chosen as it won't let me route tracks through it. I'll have to see if I can find another suitable footprint.About copper fills, do you recommend using bus traces instead to run power, or should I have smaller copper pours and connect all power traces to them?LE: I did resize the copper fills a bit in my latest screenshot, modified the inductor and diode footprints and re-routed the tracks to them a bit

author: woody
author_rank: Frequent Contributor
timestamp: February 27, 2024, 08:25:30 am
content: Some things I would do different:- The extra GND connection on both connectors with the via to the GND plane is not necessary. The thermals to GND on the other side are sufficient. And (another OCD thingy) I would try to make the same pin number on both connectors carry the same signal. So f.i. pin 1 to GND and pin 2 to power on both the in and out connectors.- The disadvantage of using copper fills for power tracks here is that you end up with copper peninsulas like under D1. I don't like that, as my experience is that if something goes wrong during manufacturing it often is with these artifacts. So in this case I would run (fat) tracks for the power and not use fills. The downside being that you lose more copper during manufacturing, which is an environmental issue.- Move the track for L1 to pin 7 more to the middle of the IC. If you have the space, use it.Please don't take my word as gospel; lots of these decisions are trade offs and I'm learning every time I send off a PCB

author: newtekuser
author_rank: Frequent Contributor
timestamp: February 27, 2024, 06:47:09 pm
content: Quote from: woody on February 27, 2024, 08:25:30 amDo power tracks not act like antennas and create noise vs copper fills? (especially if dealing with long traces)Also, what potential issues related to manufacturing were you referring to with respect to using copper fills?

author: bson
author_rank: Unknown
timestamp: February 27, 2024, 07:38:14 pm
content: I'd personally just go with the example layout or something very close to it:You can see how in the example the Vin and Vout segments are completely separate, on different ends of the board, and only connected to the rest with pads. This is to prevent coupling between them. The ground is then poured on the opposite side and connected using vias. There's no point arbitrarily pouring and stitching ground on both sides, and the larger Vin/Vout are poured, the more likely you are to get parasitic coupling for no benefit. Just nice thick traces will do the job just fine, using components large enough to not require necking and while providing a nice gap. Note the gaps provided by 0.33Ω, L1, and R2. CT can be physically smaller.(BTW, D1 is a Schottky diode, you flipped it making it into the symbol for a zener.)

author: woody
author_rank: Frequent Contributor
timestamp: February 27, 2024, 08:00:54 pm
content: Manufacturing PCB's uses chemicals to etch away copper. This process is of course tightly controlled but there is always a risk of etching too much or too little. Most of the time this works flawless. But if your PCB contains design items that are near or at the minimum specs for track width, track to track distance, track to hole, via to copper fill etc, these design items might be the first to go wrong. Copper fills create these 'lose ends'. At least in my EDA tool. Toying with clearances and minimum widths usually creates problems elsewhere in the PCB.As an example a problem I had in a 4-layer PCB I made last year. Quite a big (and therefore, expensive) board. I had 3 prototypes made and one of these boards tested a short between GND and the U-FO net. As the rest of the U-FO track was in sight on top and bottom layers, the only place left for the short was between an inner GND plane that had these nice 'fingers' (see Short.jpg) around 12 vias in the U-FO net. All well within the specs of the manufacturer, but still a short. And unrepairable.By creating a keep-out layer around the U-Fo net I got rid of the fingers. (See Alternative.jpg) In the next order of 12 boards none had the previous problem. No idea if this fix was the solution, but I like to think soAnyway, YMMV, as always.