Help finding a small and low cost programable logic IC. - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: November 22, 2023, 03:23:31 am
content: I am looking for a programmable logic IC (FPGA, PLD, CPLD, etc) for a hobby project. Any suggestions will be greatly appreciated.1. Runs on 3.3v.2. Does not require additional ICs (LDOs, FLASH, etc).3. Contains the non volatile memory (vs soft programming on boot).3. Has an internal clock generator.4. Free design tools.5. Low cost programmer.6. Low cost IC, and available in unit quantities.7. Preference for a small package with a few I/O pins.8. Logic complexity is minimal.9. Security and code protection not an issue.10. OTP is also OK.11. Power consumption is not an issue.Alternatively I could use a fast MCU, with a tiny program, but it needs to have a fast clock, e.g. 100+ MHZ. The RP2040 could be a good fit, especially with its PIO, but it requires an external flash.

author: ataradov
author_rank: Super Contributor
timestamp: November 22, 2023, 03:32:47 am
content: What is "Logic complexity is minimal"? How minimal? You need to provide at least an idea of what that logic would be doing.I'm personally a fan of MachXO2 FPGAs. HC series runs from a single voltage and they have internal flash. They are available down to QFN32 packages.

author: zapta
author_rank: Super Contributor
timestamp: November 22, 2023, 05:37:29 am
content: Quote from: ataradov on November 22, 2023, 03:32:47 amI don't know how to quantify it but really simple, to a point that every FPGA should be able to handle the complexity.As for the MachX02, are you referring to these?https://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdfOne of the requirements is to have an internal clock generators (the higher the better, e.g. preferably > 20Mhz). Looking at table 1-1, the XO2-256 XO2-640, do not have PLLs. Does it mean that they don't have generators? What about the ones with PLLs such as XO2-1200 (32 QFN), does this imply that they have a clock generator?Also, what solftware and what low cost programmer can I use to design and program respectivly?

author: ataradov
author_rank: Super Contributor
timestamp: November 22, 2023, 05:51:19 am
content: Quote from: zapta on November 22, 2023, 05:37:29 amRead "On-chip Oscillator" section. It has internal oscillator that is configurable from ~2 MHz to 133 MHz.Quote from: zapta on November 22, 2023, 05:37:29 amLattice Diamond for the software and some cheap knock-off programmer from aliexpress. This onehttps://www.aliexpress.us/item/3256802957528698.htmlor any other version, they are all basically the same.And if you just want programming without any advanced debug features (not that you will get many on a low end device anyway), then you can use any hardware supported by OpenOCD and OpenOCD. This can be as cheap as $5 for Pi Pico.

author: zapta
author_rank: Super Contributor
timestamp: November 22, 2023, 06:03:30 am
content: Thanks Alex. The internal oscilator is exactly what I need, so since PLL is not needed I can go with this onehttps://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/LCMXO2-256HC-4SG32C/3232671I presume that the programmer is in circuit which is also good.Do you happen to have a schematic of a simple breadboard that shows the basic connections, power, ground, JTAG, and anything else that is needed to support this FPGA?

author: ataradov
author_rank: Super Contributor
timestamp: November 22, 2023, 06:07:06 am
content: Here is a breakout board for the 100-pin versionhttps://github.com/ataradov/breakout-boards/blob/master/lcmxo256c/lcmxo256c_bb.pdf.Although this one will be closerhttps://github.com/ataradov/breakout-boards/blob/master/lcmxo2-2000hc/lcmxo2-2000hc_bb.pdf. The first one is for a MachXO without 2.

author: zapta
author_rank: Super Contributor
timestamp: November 22, 2023, 06:21:33 am
content: Thanks Alex. This is very useful. It matches very well all my requirements, and I think I have enough to continue.Also found an open source breakout board a few years ago. TinyFPGA AX1.https://www.crowdsupply.com/tinyfpga/tinyfpga-ax-bx#productshttps://github.com/tinyfpga/TinyFPGA-A-Series

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 22, 2023, 07:55:30 am
content: Quote from: zapta on November 22, 2023, 03:23:31 amThere are also GreenPAK Silego (now renesas) parts.https://www.mouser.com/c/semiconductors/programmable-logic-ics/spld-simple-programmable-logic-devices/?m=Renesas%20ElectronicsTheir older smaller ones are OTP and new larger ones are EEPROM. i2c program.These are minimal macrocell/register parts, not super fast.Renesas have also made press release noises a while ago, (17 Nov 2021 ) about ForgeFPGA ( starting SLG47910 in QFN24?) which seems a long time coming ?No prices or stock showing ? Some app notes appear early 2023.

author: ataradov
author_rank: Super Contributor
timestamp: November 22, 2023, 08:00:25 am
content: Those SPLD devices are really strange. They have a ton of families with minimal differences. Sometimes it is hard to even tell what the difference is. And then there is no superset device that actually has enough logic to do something useful. They seem to be programmable devices, but the only things you can program are things that would have been implemented in a hard logic anyway.The only advantage is that they publish full register map and don't need tools to configure.And the ForgeFPGA are vaporware.

author: zapta
author_rank: Super Contributor
timestamp: November 22, 2023, 08:38:07 am
content: Looks very interesting. For example, the one below. A pile of assorted analog and digital functionality at a very good price. Do you know what tools they provide to design with them? I wonder what abstraction the tools provide.https://www.mouser.com/ProductDetail/Renesas-Dialog/SLG46824V?qs=%252B6g0mu59x7IaPPlOrptPew%3D%3DEDIT: The I2C programming is a plus because they can be updated by the MCU and I presume that the programming data is not too large.EDIT: I think this is the design software. Very interesting.https://www.renesas.com/us/en/software-tool/go-configure-software-hub#overview

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 22, 2023, 08:58:43 am
content: Quote from: ataradov on November 22, 2023, 03:32:47 amI second that. Another benefit of the internal flash is the 'very' fast startup time (at least compared to anything using an external flash chip).

author: brucehoult
author_rank: Super Contributor
timestamp: November 22, 2023, 09:17:11 am
content: Quote from: zapta on November 22, 2023, 06:21:33 am100 pins!!What happened to "7. Preference for a small package with a few I/O pins." ?idk, maybe 100 pins is small for an FPGA but it's huge for a microcontroller!

author: iMo
author_rank: Super Contributor
timestamp: November 22, 2023, 09:19:08 am
content: I messed a lot with the iCE40UP5k, it works nice.. Latest exercise I did - running a risc-v with 128kB internal spram memory (plus 15kB of internal bram). Two free dev chains, btw.Small package, internal oscillator, low cost programmer (ie the FT232H).

author: ataradov
author_rank: Super Contributor
timestamp: November 22, 2023, 03:08:47 pm
content: Quote from: brucehoult on November 22, 2023, 09:17:11 amWe are discussing 32-pin version here.

author: ataradov
author_rank: Super Contributor
timestamp: November 22, 2023, 03:15:25 pm
content: Quote from: zapta on November 22, 2023, 08:38:07 amIf you looks closer, it is not a whole lot of logic. There is barely anything useful you can do with it.

author: zapta
author_rank: Super Contributor
timestamp: November 22, 2023, 03:55:00 pm
content: Quote from: brucehoult on November 22, 2023, 09:17:11 am32 pins, 5x5mm. Small enough and I can be soldered by hobbyists.https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/LCMXO2-256HC-4SG32C/3232671

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 22, 2023, 07:15:30 pm
content: Quote from: zapta on November 22, 2023, 08:38:07 amYes, they have many carefully placed muxes, so there are limits on what can be connected to what.The reprogrammable parts report this very small config memory :Quotefirst 2k bits are RAM loading, for development, second 2k bits are the NVM.For comparison, if I check SPLDs, which have a more cross-point design, a 16v8 has ~ 2k fuse bits, a 22V10 has ~6k and a ATF750 has ~14k, and ATF1502 (32 macrocells, 44 pins) has ~17k

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 22, 2023, 07:21:31 pm
content: Quote from: zapta on November 22, 2023, 03:55:00 pmYes, and lattice also do a 1200 part in QFN32 too. I've not checked if they are pin compatible.LCMXO2-1200HC-6SG32C

author: ataradov
author_rank: Super Contributor
timestamp: November 22, 2023, 07:48:26 pm
content: I would really like to see a practical thing done with Dialog SPLDs that is not power supply sequencing, which is what they are basically designed for. I may be lacking imagination, but they seem to be so limited.

author: zapta
author_rank: Super Contributor
timestamp: November 22, 2023, 08:58:35 pm
content: I installed the design software. It's graphical design, similar to labview. Looking at youtube for example, there is no much GreenPak related content that is not from Renesas. Not sure how widely it's used.https://www.renesas.com/us/en/software-tool/go-configure-software-hub#overviewEDIT: The GreenPak serial debugger / programmer, is not available.https://www.digikey.com/en/products/detail/renesas-electronics-corporation/SLG4DVKGSD/16254311?s=N4IgTCBcDaIOICcCmSB2AFAggaQAQGUkEBLAQwBtcARJAIwFcBzRokAXQF8g

author: ataradov
author_rank: Super Contributor
timestamp: November 22, 2023, 09:03:13 pm
content: GreenPak is a trademark from Silego, which was acquired by Dialog, which was acquired by Renesas just a couple years ago. So, majority of stuff you see is still from Dialog.I personally have never seen them used in any real product. I assume they go into some obscure server motherboards or something like this.Their stats on use numbers are also convoluted, since "GreenPAK" applies to a wide rage of products, and SPLDs are just a minor subset of them. I expect fixed function devices to be more popular here.I've got a few devices, since I like the idea of having a register map, so I will make a breakout board and try it out. But I really don't see practical applications for that. May be playing with them a bit will inspire something.I would really like to see ForgeFPGA become real. They actually look interesting.

author: zapta
author_rank: Super Contributor
timestamp: November 22, 2023, 09:15:18 pm
content: I couldn't find their serial debugger/programmer.https://www.digikey.com/en/products/detail/renesas-electronics-corporation/SLG4DVKGSD/16254311?s=N4IgTCBcDaIOICcCmSB2AFAggaQAQGUkEBLAQwBtcARJAIwFcBzRokAXQF8gI guess that straightforward I2C programming will also work but no integration with the development environment for debugging.

author: ataradov
author_rank: Super Contributor
timestamp: November 22, 2023, 09:30:16 pm
content: I'm not sure how useful the debugger would be. You can read all the states of everything over I2C, so you can do some manual debugging, but I'd expect it to be easy enough to configure without needing to debug.Sure, it is 2K bits, but a lot of them end up being unused, since they represent all possible multiplexing options. It does not seem to be particularly more complicated than a typical clock tree configuration in a high-end MCU.In any case, the only reason I personally even remotely interested in them is the open documentation and ability to configure them without tools. So, I have not even tried to look at how their tools work.

author: zapta
author_rank: Super Contributor
timestamp: November 23, 2023, 05:53:28 am
content: Quote from: ataradov on November 22, 2023, 09:03:13 pmThey have here hundreds of samples designs, each with an application note and the design file.https://www.renesas.com/us/en/products/programmable-mixed-signal-asic-ip-products/greenpak-programmable-mixed-signal-products/greenpak-applications#documentsHere is one example, definitly not just power supply sequencing related.https://www.renesas.com/us/en/document/apn/cm-351-true-white-noise-generator-pink-and-brown-noise-outputs?r=1570646

author: ataradov
author_rank: Super Contributor
timestamp: November 23, 2023, 06:35:41 am
content: I meant practical designs. An actual consumer product where engineering decision was made that this device is better than other options.I looked though some of those appnotes and more than ever I'm confused by the variety of the devices with limited set of functional units. There is an appnode of 8-bit I2C ADC that had to use two SPLDs because one had ADC and another had necessary comms. There is no way this is practical in a real commercial application.Most of that stuff can be done with MCUs. SPLDs are 30 cents in quantity, so this is a huge plus over MCUs (especially if we only consider western brands).

author: zapta
author_rank: Super Contributor
timestamp: November 23, 2023, 07:47:13 am
content: It may be the best solution for my immediate use case of adding addressing functionality to SPI nodes. The SLG46620for example has an SPI serial to parallel cell which I may be able to use. Or just create something myself with a few D FF cells. But I still have a lot to figure out.https://www.eevblog.com/forum/projects/are-there-spi-multiplexer-ics/

author: zapta
author_rank: Super Contributor
timestamp: November 24, 2023, 06:25:14 am
content: I was able to fit the design in a SLG46826G. These ICs can be handy. So far I just simulated it. Don't have the ICs yet.Thanks for the recomendation.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 24, 2023, 08:22:58 am
content: Quote from: zapta on November 22, 2023, 03:23:31 amHow minimal ?Many of the more recent PICs have some CLC (configurable logic cell) peripherals, in total equivalent to about half a GAL16V8, which can take inputs from most internal peripherals as well as external signals.These devices typically also can map any peripheral I/O ( including the CLC) to any pin, which can give some additional software-controlled logic functionality.If the CLC logic does what you want, something like, for example, the PIC16F15325 satisfies all your other requirements and more. If you want a more powerful processor onboard, then many of the PIC32MM range have CLC peripherals.All you need is some code to initialise the CLC registers - if you just need logic functionality you can then go to sleep and the hardware will act like a small PLD.Edit - looking at your logic diagram, a PIC with 4 CLC peripherals should be able to do that.I've used them for things like combining SPI and PWM peripherals to drive WS2812 LEDs.Some of the PIC32MM devices also DMA, which can also do some near-hardware functionality when used creatively.Most PIC8 and PIC32MM devices with CLCs have a choice of 4 packages - DIP,SO,SSOP and DFN/QFN

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 24, 2023, 09:05:03 am
content: Quote from: brucehoult on November 22, 2023, 09:17:11 amThere is at least one MachXo2 device in a 32 pin QFN

author: zapta
author_rank: Super Contributor
timestamp: November 24, 2023, 05:20:04 pm
content: Thanks Mike.1. How do I filter/list the PICs that have CLCs? I don't see it listed in Digikey's parametric search.2. Do all CLCs, in all PIC models, have the same functionality and the difference is just in the number of CLS each PIC module has?3. How does the design of the CLC is done, does Microchip provides any tools?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 24, 2023, 10:29:51 pm
content: Unfortunately Microchip have made their parametric search rather broken these daysFor 8-bit you can select CLCshttps://www.microchip.com/content/mchp/en-us/parametric-search.html/717Select "chart view- all specifications" and CLCs are one of the specsUnfortunately the 32-bit selector does not include a CLC parameterI think all the PIC32MM series have CLCs, 32MX not, don't know about others, but it's usually on the first page of the datasheetCLC Functionality is similar between parts, though permutations of available inputs for each CLC vary between parts.There are some design tools for the CLC within Microchip's Code Configurator but I've not used them, I just set up the control registers manually - the logic is simple enough to do this.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 24, 2023, 10:35:42 pm
content: These diagrams show typical CLC functionality. The CLCIns are from various internal peripherals and external pins, and vary by part.

author: zapta
author_rank: Super Contributor
timestamp: November 24, 2023, 10:40:25 pm
content: I like this clear documentation of the 8 logic function. With the GreenPak SPLD you need to reverse engineer it yourself. ;-)I will take a look. I think I could also do it with the RP2040's PIOs but it requires external flash.

author: c64
author_rank: Frequent Contributor
timestamp: November 24, 2023, 11:07:33 pm
content: I can not find any programmers for GreenPak SPLD. Everywhere no stock. Can NVM be programmed over i2c? Or is where any clones or open source programmers?

author: c64
author_rank: Frequent Contributor
timestamp: November 24, 2023, 11:11:29 pm
content: Quote from: ataradov on November 22, 2023, 07:48:26 pmCan use them if you need a little bit of glue logic. As a cheaper alternative to CPLD or 16v8 / 22v10

author: zapta
author_rank: Super Contributor
timestamp: November 25, 2023, 12:03:43 am
content: I couldn't find the SLG4DVKGSD programmer debugger. Waiting for it.There is an open spec for the programming via I2c herehttps://www.renesas.com/us/en/document/mat/system-programming-guide-slg468246?r=1572991. It may be applied only to the specified ICS. The design software exports a 256B bin data that can be programmed this way.There are also all kind of open source hardware and software resources on github related to programming. For example this onehttps://github.com/okada-tetsuya/gpakutil.or this onehttps://github.com/TiNredmc/GreenProbe

author: ataradov
author_rank: Super Contributor
timestamp: November 25, 2023, 12:38:43 am
content: Quote from: c64 on November 24, 2023, 11:07:33 pmThis is also a strange part here. Some of the parts have OTP NVM with no described programming algorithm. Others have EEPROM and the programming is no harder than any I2C EEPROM.I'm guessing newer devices are EEPROM based, but it is hard to tell.SLG46620, for example does not even have I2C interface and the programming voltage is 7.5 V, so it looks like it is based around true OTP memory and would need separate out of system programmer.SLG46826G is super easy and no programmer is required. You can either program SRAM directly or write configuration to the EEPROM.

author: c64
author_rank: Frequent Contributor
timestamp: November 25, 2023, 01:00:48 am
content: Quote from: zapta on November 25, 2023, 12:03:43 amAnd it will only work with i2c devices, correct?

author: julian1
author_rank: Frequent Contributor
timestamp: November 25, 2023, 02:35:16 am
content: To follow up Ataradov, p128- of the manual looks to give the needed info to program the LG46826,> Write access to the NVM is possible by setting A3 A2 A1 A0 to “0000”, which allows serial write data for a single page only.https://au.mouser.com/datasheet/2/698/REN_SLG46826_ds_3v18_DST_20230226-3075827.pdfSomeone did the work to support verilog and yosys, although the project doesn't look very activehttps://github.com/azonenberg/openfpga/tree/master/tests/greenpak4/slg46620vhttps://siliconexposed.blogspot.com/2016/05/open-verilog-flow-for-silego-greenpak4.html

author: zapta
author_rank: Super Contributor
timestamp: November 25, 2023, 03:10:36 am
content: I am aware of only three devices that has I2C basded programming: SLG46824, SLG46826, and SLG47004. I think the rest are one time programmed and require 7.5 volt for programming. (If I got it correctly).I consider getting one of these two USB/I2c adapters to program the from a python program. Is it a reasonable choice? (on the PC side they look like FTDI serial port so no need for drivers).https://www.amazon.com/gp/product/B07P2H8V7Whttps://www.amazon.com/gp/product/B0844Z6M83

author: ataradov
author_rank: Super Contributor
timestamp: November 25, 2023, 03:21:01 am
content: They probably would work, but I don't immediately see what is used for the actual I2C IC. You may want to check that you can find documentation for that.

author: zapta
author_rank: Super Contributor
timestamp: November 25, 2023, 03:23:36 am
content: Quote from: julian1 on November 25, 2023, 02:35:16 amDoes this mean that in-circuit programming of multiple devices on the same I2C bus is not possible?

author: ataradov
author_rank: Super Contributor
timestamp: November 25, 2023, 03:25:27 am
content: Nope, the address is fixed, there is no selection. One part at a time only.The address has programmable part, but all factory fresh devices would have that programmed to the same value.

author: zapta
author_rank: Super Contributor
timestamp: November 25, 2023, 03:26:29 am
content: I think that they have an MCU that bridges between serial and I2c, with a proprietary, but open, serial protocol. The goal is to avoid the hassle of USB/I2C system drivers.

author: zapta
author_rank: Super Contributor
timestamp: November 25, 2023, 03:28:40 am
content: I see, the I2C address selection is not for the programming but for runtime, if using the I2C device for the application. Makes sense since there is no configuration at programming time.

author: ataradov
author_rank: Super Contributor
timestamp: November 25, 2023, 03:31:32 am
content: Documentation says that control code (variable part of the address) can be set by IO5, IO4, IO3, and IO2, or by the register bits. But at the same time, it looks like the default is fixed to 0001.And yes, your screenshot shows the default state of the device. All factory devices would have the address 0001xxx.

author: zapta
author_rank: Super Contributor
timestamp: November 25, 2023, 03:39:35 am
content: The design tool allows to select which bits of the I2C address come from external pins. Usefulif you want to have multiple instances of the same design on the same bus.

author: ataradov
author_rank: Super Contributor
timestamp: November 25, 2023, 03:41:28 am
content: But you would have to program them outside of the board, or figure out some way to power only one device at a time.

author: zapta
author_rank: Super Contributor
timestamp: November 25, 2023, 04:19:44 am
content: If I don't use the I2C cell in my application, I can have the SDA and SCL pins free and program with a clip line this onehttps://www.aliexpress.us/item/3256801223264694.htmlOr, if I do want to program multiple in circuit and by the main MCU, I can add another device that will distribute the SCL. That is, I2c controlled SPLD that either routs the SCL just to one of N for outputs, for programming , or to all of them in normal application run run mode.I tried to think of a daisy chain configuration that doesn't require an additional device but hasn't found anything yet.

author: ataradov
author_rank: Super Contributor
timestamp: November 25, 2023, 04:45:01 am
content: You can't easily distribute SCL, since slave device may hold it low to clock stretch.

author: zapta
author_rank: Super Contributor
timestamp: November 25, 2023, 05:43:03 am
content: That's a good point. Some devices do stretch. I searched the SLG46826's datasheet for 'stretch' and didn't find any reference. Still trying to understand this device.It's similar to using a ISO1541 where the SCL is unidirectional.

author: zapta
author_rank: Super Contributor
timestamp: November 29, 2023, 04:53:56 am
content: Quote from: ataradov on November 25, 2023, 03:41:28 amThe in-circuit programming doc mentions explicitly the possibility of using these 4 bit code to program multiple devices connected to the same I2C bus "This gives the User flexibility on the chip level addressing of this device and other devices on the same I2C bus"https://www.renesas.com/us/en/document/mat/system-programming-guide-slg468246Let's say that there are N <= 16 devices, each hard wired on the PCB for a different code (via IO2,3,4,5). If each of the devices is programed to use the code from the IO pins then the rest is solved. Let's say that we just assembled the board and the devices are at factory default, using the 0001 code from the register. The master can send a write command that will flip those 4 bits to use the code from IO pins. All devices will ack in parallel (open drain) and will flip those bits. From this point, each has a unique code.BTW, the master can be the on-board MCU or an external I2c adapter via a programming connector.I haven't tried it yet, just speculating based on the documentation.

author: ataradov
author_rank: Super Contributor
timestamp: November 29, 2023, 05:12:16 am
content: This might work, assuming devices operate with the same timing and don't clock stretch. It is probably better to program the SRAM registers first, then program the EEPROM individually.

author: zapta
author_rank: Super Contributor
timestamp: December 04, 2023, 03:03:16 pm
content: Quote from: c64 on November 24, 2023, 11:07:33 pmDigikey has one in stock. Even if it will got away, the lead time is only two weeks, so you can order now.https://www.digikey.com/en/products/detail/renesas-electronics-corporation/SLG4DVKGSD/16254311?s=N4IgTCBcDaIMoBkDiAWAIgNQNJLmkAugL5A

author: zapta
author_rank: Super Contributor
timestamp: December 04, 2023, 03:08:44 pm
content: Quote from: ataradov on November 29, 2023, 05:12:16 amI asked about it in the Renesas forums. The answer I got so far from a use is that the SCL multi programming devices is input only and thus no stretching. I haven't verified it yet with the datasheet.Any use of I2C clock stretching should be mentioned explicitly IMO since they require the master(s) and any bus interface to support it.https://community.renesas.com/analog-products/f/greenpak-greenfet/32620/do-greenpak-devices-use-i2c-clock-stretching?ReplySortBy=CreatedDate&ReplySortOrder=Ascending

author: ataradov
author_rank: Super Contributor
timestamp: December 04, 2023, 04:07:04 pm
content: Clock stretching is a natural feature of the I2C. It is unfortunate that people still keep making broken hardware that does not support it, even though it is easy to implement. And most masters do support it, since it comes free with the collision detection. If your master does not do that, well, it is very broken.But this is fine. For hobby use nobody cares.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: December 04, 2023, 04:09:31 pm
content: It would be rare for a memory interface to use clock stretching, that’s usually only seen in small MCU’s that handle one byte as slaves.Some use fixed times, and others use ACK polling, for the ‘some ms’ pgm/ erase times.

author: ataradov
author_rank: Super Contributor
timestamp: December 04, 2023, 04:18:23 pm
content: Just to clarify, I meant that it is natural for the masters. Slaves are perfectly fine with input-only behavior. Obviously, it i better to get it documented, since it would allow parallel operation like it required here.In this case, it looks like for programming operations you have to introduce delays yourself. The page programming takes 20 ms, and there are no status bits for that. Erase also takes 20 ms, but there is a status bit. Not sure if device would allow reading of that bit wile operation is ongoing though.I have boards on a way SLG46824, we'll see how all that works.

author: zapta
author_rank: Super Contributor
timestamp: December 04, 2023, 05:24:56 pm
content: If anybody is interested, I designed these SMD adapters for breadboarding. Ordered them from JLCPCB but haven't tested them yet. I order 0.8mm boards and cut with aviation snips, or strong scissors. It costs as low as $3.5 for 5 boards shipped to the US.https://github.com/zapta/GreenPAKs/tree/main/smd_adapters/JLCPCB

author: zapta
author_rank: Super Contributor
timestamp: December 04, 2023, 05:30:54 pm
content: Some devices such as the ADS1261 just require to master to clock an extra dummy byte to have sufficient time to prepare the response.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 04, 2023, 10:16:42 pm
content: Quote from: PCB.Wiz on December 04, 2023, 04:09:31 pmWell, while clock stretching can be done without in a lot of cases indeed - not a big fan of the principle myself for reasons I explained before, namely that holding the bus to wait for some operation to complete is not a great idea if the bus is shared by a number of devices, but can be efficient in some specific cases - any master implementation not handling clock stretching properly is a borked implementation. So, I agree with ataradov here.

author: c64
author_rank: Frequent Contributor
timestamp: December 04, 2023, 10:47:30 pm
content: Not related to i2c discussion, but. I'm looking at the SLG46824 datasheet... For timing characteristics they only specify typicals at 25°C. How can you design anything like this?

author: zapta
author_rank: Super Contributor
timestamp: December 04, 2023, 11:06:00 pm
content: Quote from: ataradov on December 04, 2023, 04:07:04 pmOk, let's assume worst case where (1) the GreenPAKs use clock stretching while programming and (2) each one may stretch for a different period. What will happen if we write to a few of them in parallel, to initialize the 'use I2C address from external pins' settings, such that each gets its own unique address?I would think that the master will send 8 bits, some devices will stretch, and when the longest one ends the stretching, the master will send the 9th clock and everything will resume as normal. In other words, the parallel write will succeed even with stretching.Am I missing something?(I don't think that they use stretching but this is a just-in-case mental excersize).

author: woofy
author_rank: Frequent Contributor
timestamp: December 05, 2023, 11:10:46 am
content: Writing to multiple slaves in parallel is not part of the I2C specification. How could you ever know if one of the devices NAK'd out?

author: zapta
author_rank: Super Contributor
timestamp: December 05, 2023, 02:31:59 pm
content: The context here is a very specific use case of initializing virgin greenpaks to have them switching to the individual addresses assigned to them by the PCB wiring. If one failed to write, it will not be found at its designated address.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 05, 2023, 09:14:41 pm
content: I understand, but clearly this is an out-of-spec use. How will you assign them individual addresses in this way?

author: ataradov
author_rank: Super Contributor
timestamp: December 05, 2023, 09:21:59 pm
content: I expect that to work. Those devices have configuration bits where they would take part of the address from the pins. So you have to upload the same firmware on all of them. That firmware would enable individual address assignment from the pins. Then on the board strap the pins to different values.Even writing to the EEPROM should work, since it looks like it just takes 16 byte page at a time and the write starts after the stop bit. And it is on you to wait for the write time, since there are no flags you can poll for. So, they are write-only device when it comes to programming anyway.The downside, you are going to lose use of pins, which are already pretty limited.

author: zapta
author_rank: Super Contributor
timestamp: December 09, 2023, 10:13:11 pm
content: I had today the my first program, a 1Hz blinky, running on an actual chip. ;-)

author: c64
author_rank: Frequent Contributor
timestamp: December 09, 2023, 10:54:30 pm
content: How did you program it?

author: zapta
author_rank: Super Contributor
timestamp: December 09, 2023, 11:33:57 pm
content: I got a 1695-SLG4DVKGSD-ND from Digikey this week. They had two in stock and I ordered one. They say that the lead time is two weeks if you order now. Also ordered thishttps://www.amazon.com/dp/B0844Z6M83so I can write my own flasher in Python.https://www.digikey.com/en/products/detail/renesas-electronics-corporation/SLG4DVKGSD/16254311?s=N4IgTCBcDaIIwDYCcBWAtAZQDIHEAsAIgGoDSOGBaAcgSALoC%2BQA

author: ataradov
author_rank: Super Contributor
timestamp: December 09, 2023, 11:54:22 pm
content: I've just assembled my board. I have an on-board MCU for programming/interfacing. But I want to go hard mode and not use vendor tools and make a Python script to configure the registers. This will likely be a project for the holidays though.I want to prepare to the time when ForgeFPGA are released. It would be cool to play with their independent configuration too.

author: zapta
author_rank: Super Contributor
timestamp: December 10, 2023, 02:42:46 am
content: Quote from: ataradov on December 09, 2023, 11:54:22 pmCan this be done with an of the shelf board such as Pi Pico? If so, with a compatible python API on pypi.org, this can be a great open source tool for the community. People just buy a Pico board, flush the binary (no tools require) and have GreenPAK programmer with high level python library that can be pip installed.

author: ataradov
author_rank: Super Contributor
timestamp: December 10, 2023, 02:54:26 am
content: The Python script would generate 256 bytes of the firmware. It will not do any of the actual programing. I assume it would end up portable enough to run on the Pico.But this workflow does not make sense. It is easier to generate the binary and then separately program it using whatever tools. In my case I don't even care to program it into the EEPROM, I just want dynamically configurable device.My initial though was to actually just make a C header with all the defines for the device. The firmware is then easily generated in run-time. And I still might do that, but Python first for simplicity.

author: zapta
author_rank: Super Contributor
timestamp: December 10, 2023, 04:21:34 am
content: I see, I thought you are talking about the programming aspect.How do you plan to generate the 256 configuration bytes. What will be the input to that program or how will the desired behavior will be defined?

author: ataradov
author_rank: Super Contributor
timestamp: December 10, 2023, 04:44:13 am
content: The same way you configure regular peripherals in the MCUs - a bunch of definitions for the configuration options and their possible values. With Python you can organize HDL-like structure, but I don't know if it is really necessary. There is not a whole lot of logic to configure there.Literally half the configuration bits are I/O settings and matrix interconnect. There are a lot of bits, but once you know what you want, a lot of them don't matter, so the actual functional part of the configuration is pretty small.

author: zapta
author_rank: Super Contributor
timestamp: December 10, 2023, 05:16:25 am
content: Would be interesting to see how the definition of the simple Blinky will look like with your 'language'.https://github.com/zapta/GreenPAKs/tree/main/blinkyBTW, the design tool can create a project (including schematic) from the 256 configuration bytes it reads from a device. You can use it for example to run the Renesas validation rules on the configurations that you generate, or to run simulation over it. I find the simulations helpful in understanding the various blocks with very fast exploration cycles.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: December 10, 2023, 08:40:44 pm
content: Quote from: ataradov on December 10, 2023, 04:44:13 amBe interesting to follow that.The smaller CPLD from Philips/ atmel / altera used fitters, that swallow Berkley TT2 files, and create a fit report and a JED fuse image file.

author: zapta
author_rank: Super Contributor
timestamp: December 11, 2023, 05:21:46 am
content: The abstraction in the Dialog design tool is minimal and is limited to a cell boundary. You chose a specific cell, select one of its variant configurations (e.g. LATCH vs LUT) and it shows you just the that subset of the cell functionality.With your own definition language, in addition to fitting you can add cross cell abstractions, such as a LUT with more than one output, or a register with more than one bits. It all depends how much smart you want to add to the tool.BTW, i managed today to program with a generic I2C interface. I plan to expand it to a more useful API and tool that support automation of multiple devices in-circuit programming.https://github.com/zapta/GreenPAKs/blob/main/tool/test.pyhttps://github.com/zapta/GreenPAKs/blob/main/tool/greenpack_i2c_driver.py

author: FlyingDutch
author_rank: Regular Contributor
timestamp: December 11, 2023, 09:44:38 am
content: Hello,I designed FPGA board based on Gowin FPA (GW1N-LV9LQ144). This device has a 8640 LUts and 6480 Flip-Flops. The development board is well quipped with peripheral circuit. Below is image of this boardThere are 64 pins of GPIOs leaded out on headers (16 differential pairs). High speed and differential signals traces are designed with length matching.This board is cheap.It has:1) 8 LEDs2) 5 switches3) 8 DIP-Switches4) VGA output5) uSD card socket6) Audio output7) 3 Golpin headers - 64 pins8 MB of PSRAM9) USB FTDI built-in programmer10) 32 Mbit external FlashRegards

author: zapta
author_rank: Super Contributor
timestamp: December 11, 2023, 04:10:16 pm
content: Thanks FlyingDutch. Very nice board indeed.My goal was to have an inexpensive and minimalist IC that doesn't require external components, and I was able to fit my design into a GreenPAK SPLD.https://github.com/zapta/GreenPAKs/tree/main/addressable_spi

author: c64
author_rank: Frequent Contributor
timestamp: December 11, 2023, 11:03:21 pm
content: Quote from: zapta on December 11, 2023, 05:21:46 amI don't think you can make anything useful. Only just for the sake of "hacking"

author: c64
author_rank: Frequent Contributor
timestamp: December 11, 2023, 11:07:10 pm
content: Quote from: zapta on December 11, 2023, 04:10:16 pmWhy you didn't route MOSI and CLK directly to the slaves?

author: ataradov
author_rank: Super Contributor
timestamp: December 11, 2023, 11:10:11 pm
content: I definitely don't plan on doing anything advanced, just give you the ability to configure things in a better way than calculating the register values directly. There is no point in trying to be smart for a device with 20 LUT+FFs.I started looking in details at the configuration, and the datasheet is not fully complete. For the LUT/DFF + CNT/DLY blocks, they list a fixed set of "supported" bit configurations, but they don't fully breakout the logic of mapping from the set of bits to the mux/demux control signals. Some of that is possible to guess, but other parts are not obvious. It would be easy enough to guess or figure out in practice, but it is strange that they did not document it, given the amount of information already provided.

author: zapta
author_rank: Super Contributor
timestamp: December 11, 2023, 11:57:04 pm
content: For a few reasons1. It reduces the SPI bus load. Especially if it you build a hierarchical tree.2. It's nicer to debug a device this way.3. It's optional since the user can use the original CLK and MOSI.I consider to route also MISO signal. Especially for reason #1.

author: c64
author_rank: Frequent Contributor
timestamp: December 12, 2023, 02:15:08 am
content: Quote from: ataradov on December 11, 2023, 11:10:11 pmDid you look at both logic diagrams and register definitions?They probably expected everyone to to use the GUI tool

author: c64
author_rank: Frequent Contributor
timestamp: December 12, 2023, 02:18:58 am
content: Quote from: ataradov on December 11, 2023, 11:10:11 pmWould be nice if someone wrote a Verilog/VHDL compilerOr even something simple like CUPL

author: ataradov
author_rank: Super Contributor
timestamp: December 12, 2023, 02:35:00 am
content: Quote from: c64 on December 12, 2023, 02:15:08 amYes, I did. And it is not like documentation missing, it is all there is you just use specified bit patterns. You just can get more flexibility by treating things as separate controls.The diagrams are not entirely representative of the full logic. If you look at Figure 31, for example, the first column of multiplexers has two input per mux and one control signal. But this signal is not a specific single bit, it is not even a common signal for all of them. It is a separate signal for each mux, which is derived from registers [1341:1340] and [1338:1337].It would be a very Verilog limited compiler. To the point of being useless. It is a lot of work for absolutely no benefit. The interconnecting logic is very simple, so all you will have is just instantiations of those 20 modules with direct writes between them.

author: c64
author_rank: Frequent Contributor
timestamp: December 12, 2023, 03:10:37 am
content: Quote from: ataradov on December 12, 2023, 02:35:00 amYes you are right. There is another hidden LUT between [1341,1340,1338,1337] and control signals. To save few bits of NVM I guess.

author: ataradov
author_rank: Super Contributor
timestamp: December 12, 2023, 10:17:46 pm
content: It looks like the first mistake found. In the description of "Single 4-bit LUT" and "Single DFF w RST and SET" (bits 1280 - 1286), the enumerated values are not correct. The first one is "0000000", the second one is shown as "0010000". The exact order of the bits is not well documented, but the rest of the table shows third bit from the right to select LUT vs DFF (bit 1282), which also matches the diagram. In this case it looks like the value "0010000" is bit reversed. In practice "0000100" selects DFF, which matches the reset of the table.

author: ataradov
author_rank: Super Contributor
timestamp: December 12, 2023, 10:24:24 pm
content: Also, this thing is somewhat easy to debug. It has a virtual 8-bit port that can be written from I2C and it can be routed to any inputs of the blocks. And outputs of all blocks are also available. So, there is not even a need to connect anything to the pins to test functionality, I just provide inputs from the Python script.

author: c64
author_rank: Frequent Contributor
timestamp: December 13, 2023, 01:25:31 am
content: Quote from: ataradov on December 12, 2023, 10:17:46 pmCan you select this exact option from GUI?

author: ataradov
author_rank: Super Contributor
timestamp: December 13, 2023, 01:33:57 am
content: I don't want to. I don't want to download that IDE unless I absolutely have to.There is a clear structure to those bits, and this one is absolutely swapped. The bits in the table are in order 1286-1280. This way it makes sense for the diagram. But it does not looks like there is a lot more functionality that can be extracted from arbitrary configurations. I don't know why they needed it to be that convoluted. Arbitrary and uniform selection of inputs would be so much better.

author: c64
author_rank: Frequent Contributor
timestamp: December 13, 2023, 07:15:25 am
content: Quote from: ataradov on December 12, 2023, 10:17:46 pmOrder of bits is specified in the table as below, so 1282 supposed to be third bit from theleft1286128512821284128312811280

author: ataradov
author_rank: Super Contributor
timestamp: December 13, 2023, 07:31:32 am
content: This order is entirely incorrect. Here is a more combined (LUT/DFF is marked with *) and better arranged table.The pairs (1286 1285) (1284 1283) (1281 1280) make a lot of sense and match the diagrams. There is not a lot of extra decoding going on, just some reuse of bits.Code:# 1286 1285 1284 1283 1282 1281 1280# 00 00 0 00 - 4-bit LUT : DLY_IN - LOWIn3 - AIn2 - BIn1 - CIn0 - D# 00 10 0 00 - DFF : DLY_IN - LOWDi - AnSET - BnRST - CCLK - D# 00 00 0 01 - CNT/DLY : DLY_IN - DUP - AKEEP - BEXT_CLK- CDLY_OUT - L/D#DinSETnRSTCLK# 00 00 * 10 - CNT/DLY -> L/D : DLY_IN - AIn3 - DLY_OUTIn2 - BIn1 - CIn0 - D# 01 00 * 10 - CNT/DLY -> L/D : DLY_IN - AIn3 - DLY_OUTIn2 - In1 - CIn0 - DEXT_CLK - B# 10 00 * 10 - CNT/DLY -> L/D : DLY_IN - AIn3 - DLY_OUTIn2 - BIn1 - In0 - DEXT_CLK - C# 00 01 * 10 - CNT/DLY -> L/D : DLY_IN - BIn3 - AIn2 - DLY_OUTIn1 - CIn0 - D# 10 01 * 10 - CNT/DLY -> L/D : DLY_IN - BIn3 - AIn2 - DLY_OUTIn1 - In0 - DEXT_CLK - C# 00 10 * 10 - CNT/DLY -> L/D : DLY_IN - CIn3 - AIn2 - BIn1 - DLY_OUTIn0 - D# 01 10 * 10 - CNT/DLY -> L/D : DLY_IN - CIn3 - AIn2 - In1 - DLY_OUTIn0 - DEXT_CLK - B# 00 11 * 10 - CNT/DLY -> L/D : DLY_IN - DIn3 - AIn2 - BIn1 - CIn0 - DLY_OUT# 01 11 * 10 - CNT/DLY -> L/D : DLY_IN - DIn3 - AIn2 - In1 - CIn0 - DLY_OUTEXT_CLK - B# 10 11 * 10 - CNT/DLY -> L/D : DLY_IN - DIn3 - AIn2 - BIn1 - In0 - DLY_OUTEXT_CLK - C# 00 00 * 11 - L/D -> CNT/DLY : DLY_IN - L/D_OIn3 - AIn2 - BIn1 - CIn0 - D# 01 00 * 11 - L/D -> CNT/DLY : DLY_IN - L/D_OIn3 - AIn2 - In1 - CIn0 - DEXT_CLK - B# 10 00 * 11 - L/D -> CNT/DLY : DLY_IN - L/D_OIn3 - AIn2 - BIn1 - In0 - DEXT_CLK - CIn all cases bit 1282 is third from the right, except for the second line.

author: zapta
author_rank: Super Contributor
timestamp: December 13, 2023, 03:41:35 pm
content: Which IC are you using?Also, why don't you want to load the design tool, for security reasons? It can be very useful to what you are doing, showing the bits interactively as you configure the cells.

author: ataradov
author_rank: Super Contributor
timestamp: December 13, 2023, 04:00:46 pm
content: Quote from: zapta on December 13, 2023, 03:41:35 pmSLG46826.Quote from: zapta on December 13, 2023, 03:41:35 pmThere is no fun in doing that. I have no practical use for this device other than to have fun figuring it out on a low level.

author: zapta
author_rank: Super Contributor
timestamp: December 13, 2023, 08:08:07 pm
content: It will be useful for the community if you can document what you find. Adding insight on top of the official documents.

author: c64
author_rank: Frequent Contributor
timestamp: December 14, 2023, 07:57:55 am
content: Quote from: ataradov on December 13, 2023, 07:31:32 amI checked with whatever GUI generates. Looks like whoever made this table, first few entries they documented correctly, and for the rest they forgot about bit 1282, and documented as if all bits are in descending order. Or maybe it was two different personsWhat is the moral of this story? When you document this kind of stuff, it must be generated automatically, and from the same data as the software.

author: ataradov
author_rank: Super Contributor
timestamp: December 15, 2023, 04:39:44 am
content: I've been working though the document, describing this thing as a huge Python dictionary. It is actually quite hilarious, and I wonder if it is intentional. Not a single description of those multi-function blocks is correct. Most have binary values moved around. One has them correct, but the bit indexes are wrong.The other digital blocks are more or less ok, but the analog blocks are mental. There are bits that are mentioned in the table and never in the rest of the datasheet. And overall descriptions do not match the diagrams.The datasheet is really bad all around. For such a simple thing, it is one of the worst I read in a long time.

author: zapta
author_rank: Super Contributor
timestamp: December 15, 2023, 04:54:25 am
content: If you like, you can report the errors herehttps://community.renesas.com/analog-products/f/greenpak-greenfet. They do expose the bits in the designer and even provide a tool to compare two sets of configuration bits, which means that the bits are exposed to the user and are expected to be correct.The datasheet is indeed not clear, even if not getting into the configuration bits. I explore through trial and error in the design tool, using simulations. I presume that most of their users use the design tool, don't get into the bits, and get hand holding from the vendor when needed.

author: ataradov
author_rank: Super Contributor
timestamp: December 16, 2023, 11:16:41 pm
content: Ok, I'm done with this for now. I'm attaching the files in case anyone interested. The working blinky example:Code:i2c.addr = 1 # defaultosc0.power = alwaysosc0.matrix = offosc0.pre_div = 8osc0.div1 = 1osc0.out1 = enablecnt_dly_1.clk_src = osc0cnt_dly_1.dly_in = lowcnt_dly_1.data = 128cnt_dly_1.fn_edge = rising_edge_resetcnt_dly_1.sync = 2dfflut2_0.in0 = dff_1lut2_0.in1 = dff_1lut2_0.lut = nanddff_1.clk = cnt_dly_1dff_1.d = lut2_0io14.input_mode = digital_schmittio14.pull_value = 10Kio14.pull_mode = uplut2_3.in0 = dff_1lut2_3.in1 = io14lut2_3.lut = andio6.output_mode = push_pull_2xio6.output = lut2_3io6.output_oe = enableio3.output_mode = push_pull_2xio3.output = osc0_1io3.output_oe = enableThe source clock is 2048 Hz OSC0 pre-divided by 8. It then further divided by cnt_dly_1 by 128. It then goes to the DFF_1 clock and the data input is the inverted output. Note that the same could have been achieved by specifying "dff_1.dff_output = qb" and connecting the output to the input directly. I used lut2_0 as an inverter to show more logic. The output is IO6. It is further gated by IO14 input, again to show more stuff. The 2048 Hz is also output on IO3.I have not verified all the bit values, so there are likely some mistakes. And it is also likely that some bits can be better grouped/described. But this all will be obvious with use. At least now there is a computer-readable description of the part, which can be used to generate C defines, for example to allow run-time dynamic configuration from the host MCU.Error checking is very minimal. Conflicting resource use is detected on the bit/register level. If two blocks demand the same bit to be set to different values, then something is conflicting. I have no doubt it is possible to intentionally create situation that is not detected by this system.But for now I've had my fun and I want to work on other stuff. Now that I know how this part works, I'll keep it in mind and may be it will come in handy in some project.Also, can anyone attach any generated binary from the IDE? The last 16 bytes on the blank part seem to contain some information. I wonder what IDE puts there. In my experiments I have not tried to reprogram those bits and just left them as is. They are reserved in the datasheet.

author: zapta
author_rank: Super Contributor
timestamp: December 17, 2023, 06:07:46 pm
content: Very elegant code. What USB/I2C adapter are you using?I loaded the bits your test generates to the design tool and got the view below. The rules checks went well except for comments about the comparators which are not connected by included in the design. Not sure what this means in the SPLD, maybe they are powered on, even though they are not used?When I disabled the comparators in the design tool and exported the NVM bits, I god the diff shown in the second screenshot below. The last page of the NVM is not user writeable so not sure what the design tool put in those bits and what bits the SPLD returns when reading these bits.

author: zapta
author_rank: Super Contributor
timestamp: December 17, 2023, 06:18:20 pm
content: ...The second screenshot below is the diagram from your bits after hiding the comparators and rearranging blocks.The first one is after converting the NAND to an INVERTER.

author: ataradov
author_rank: Super Contributor
timestamp: December 17, 2023, 06:19:58 pm
content: Those bits are entirely undocumented. The whole last part of the memory map is reserved. A blank device has this in the last 16 bytes "40 16 11 27 22 18 10 10 10 00 b8 00 00 00 00 a5". I have no idea what that is, so I can't meaningfully generate this value. In my experiments I just left those bytes as is. In my experiments I saw no issues with those comparators being "enabled". It might affect power consumption or something like that, but I don't think it matters for functionality.I use a custom adapter based on SAM D11. I just hacked up an existing VCP project to interpret the commands and translate them to I2C. I have it mounted on the same breakout board, so I don't have to worry about separate adapters.

author: zapta
author_rank: Super Contributor
timestamp: December 17, 2023, 06:36:44 pm
content: According to the in-circuit programming guide, the last 16 bytes are also not user writable, so it doesn't matter what you put there. It's possible that the design tools uses it for its own purpose. I just write pages 0-14 and verify them by reading back.

author: ataradov
author_rank: Super Contributor
timestamp: December 17, 2023, 07:14:28 pm
content: Ok, but the bits in your diff are in that page. So, it looks like the tool uses them to store project settings rather than actual data. So you can import the binary back and get correct things enabled, but the programming tool will ignore that.

author: zapta
author_rank: Super Contributor
timestamp: December 23, 2023, 06:42:22 am
content: I changed the USB/I2C adapter and hit this errata where writing to the erase register doesn't ack. Added code to clear the error and continue.https://www.renesas.com/us/en/document/dve/slg46824-errata?language=enI am now programming with a plain Raspberry Pi PICO that acts as a USB/I2C adapter, instead of the of the shelf I2cDriver Mini.

author: zapta
author_rank: Super Contributor
timestamp: December 24, 2023, 09:31:25 pm
content: Posted my code as two pypi packages here:https://pypi.org/project/greenpak// An API do read/write/program greenpak devices via I2C.https://pypi.org/project/i2c-adapter// Rasberry Pico based USB to I2C adapter.In the future will extend the greenpak driver to support also other USB/I2C adapters.

author: zapta
author_rank: Super Contributor
timestamp: January 05, 2024, 03:53:01 am
content: Here is an example with the in-circuit initial address assignment. The control codes page may be at different NVM addresses in different device type, hence the programming is done for each device type independently.. Writing the control code page for one type creates a side affect on the other types that were not assigned yet, but this is fixed once they move to their real address and are reprogrammed from scratch.https://greenpak.readthedocs.io/en/latest/#assigning-initial-addresses