Why use a Bypass Capacitor for EACH IC in the circuit? - Page 1
Forum section: electronics / beginners

author: Falcon69
author_rank: Super Contributor
timestamp: September 09, 2014, 04:12:38 am
content: Okay, so I did a quick search on this subject, but didn't really understand why.Here's what's going on.I read that on each IC on the circuit board, it is a good idea to put a 0.1uF cap on each IC that is placed on the circuit board (some IC's, like the 555 timer, actually require several caps, and at different values). This cap should have traces as short as possible connected to the ground and power of each IC. From what I read, it has something to do with filtering out the AC signals and/or noise in the power rail going to each IC. This also includes all logic chips, even the 4000 series (which in my case, I am using several of these in a current design I'm working on). But, on a circuit that only operates on DC (like a vehicle battery), are they needed?The recommendation for placing these caps, are drawn in box A, but, Isn't that the same as what is in Box B? And if that's the case, why not just make it like box C? (see pictures) Making it like box C will save on components and board space, will it not? Is there really a significant of a difference?I also read that some chips won't even work (or work screwy) if there are no caps. This might explain why a previous circuit I couldn't get working on the breadboard, if that statement was true. I had no caps on the IC's. Those chips were also series 4000 logic.

author: Falcon69
author_rank: Super Contributor
timestamp: September 09, 2014, 04:14:55 am
content: Oh, I also wanted to ask, why, on the series 4000 chips, if a cap is suppose to be connected to the Vcc and GND with traces as short as possible, then, for example, why isn't the GND and Vcc on the same side of the chip? Instead of Vcc and Y.

author: Dago
author_rank: Frequent Contributor
timestamp: September 09, 2014, 04:39:55 am
content: Quote from: Falcon69 on September 09, 2014, 04:14:55 amThere is currently a similar topic about decoupling caps on this forum, check it out.But in a nutshell the capacitor has to be as close as possible to the power pins because when the chip draws a fast current pulse (such as when its digital output switches state) the decoupling capacitor supplies all the power because the inductance to the power supply is massive at the frequency that the current pulse is.Decoupling caps are always a part of a good design. You might get away without them but the issues you can run in to without them can be quite difficult to debug so it is not worth the risk (considering the capacitors cost a couple of cents or something).

author: Falcon69
author_rank: Super Contributor
timestamp: September 09, 2014, 04:42:45 am
content: Oh, decoupling and Bypass mean the same thing? Did not know that.So what issues could arise? For example, with the 4000 series chips?

author: Dago
author_rank: Frequent Contributor
timestamp: September 09, 2014, 04:57:03 am
content: Quote from: Falcon69 on September 09, 2014, 04:42:45 amYup decoupling and bypass caps are the same thing.The issues can very widely, the effective result with low decoupling is the same as very shortly cutting (or lowering) the supply voltage for the chip when it is operating. This can cause it to latch up, go in to a wrong state, think its inputs are in a different state than they really are etc.

author: Falcon69
author_rank: Super Contributor
timestamp: September 09, 2014, 05:00:04 am
content: Then that WOULD explain why I couldn't get any of the logic gates to work properly in a previous circuit on the breadboard, but in simulation (using falstad's circuit simulator) it worked fine.On chips, like dual transistors or dual mosfets, i don't need a decoupling/bypass cap on it, right? Just on the digital circuits, like the 4017, 555, 4000 series chips?

author: eetech00
author_rank: Regular Contributor
timestamp: September 09, 2014, 05:08:30 am
content: HiWithout bypass caps, the IC's behavior may not be reliable because the chips are extremely sensitive to voltage fluctuations, either from the power supply or spurious sources, and it can cause input levels or output levels to change unexpectedly, causing erratic circuit behavior. Its best practice to place a 0.1u cap as close as possible to each IC supply pin. This is true for any CMOS IC device, including the 4000 series..eT

author: Falcon69
author_rank: Super Contributor
timestamp: September 09, 2014, 05:18:41 am
content: okay.In one of my circuits, I have a CD4017 and a 555 Timer close together. Can I use just one 0.1uF cap between them, or still better for them to have their own? I ask because Pin 13 and Pin 8 of the CD4017 need to be connected,along with pin 1 of the 555 timer. Since the CD4017 is on the left and the 555 is on the right (of the circuit board), i could just put a single cap between the two IC's.Included a pic what I'm talking about.

author: Dago
author_rank: Frequent Contributor
timestamp: September 09, 2014, 05:42:19 am
content: Quote from: Falcon69 on September 09, 2014, 05:18:41 amIf the pins are really (physically) close to each other you can use one single cap for them. But in my opinion it is a good practice to learn to use one cap for one supply pin (then you don't have to worry about it).One thing to take in to account is that you always have to remember to also keep the impedance between the decoupling capacitor and the ground low as well, otherwise the decoupling capacitor is not as effective. This is usually achieved by having a solid ground plane on the bottom layer. You can think of it so that every track that is running on top of ground has low impedance (=because the inductance is low when the conductors are close to each other). If there are gaps in the ground then the current has to "go around them" which increases inductance (and thus impedance). A ground plane is not most likely needed for breadboarded 4000 series logic but just wanted to clear that up as well.With digital logic basically the rise- and falltimes of the signals dictate what kind of design you need. The faster the risetimes the more critical the layout becomes. 4000 series is slow so it is a good choice in that sense.

author: Falcon69
author_rank: Super Contributor
timestamp: September 09, 2014, 05:49:22 am
content: SO, make the whole bottom (second layer) all ground, forget about copper pours, and use thermal pads for the via's that go from top to bottom (second layer) to connect to the ground? There will still be areas where the current has to go around, for traces I'll have to route on the bottom (second layer) because of now room on the top. Should I try and leave those traces with further distance from ground? Like, if I'm using a 0.2mm trace make a 0.3mm space between it and the ground pour? I've basically been leaving 0.2mm space between a trace and the trace next to it, more if that trace runs along a main power or ground trace.I just need to figure out how to do that in diptrace. Lately, I've been just running traces, then use Copper Pour to fill the large spaces, but I don't connect any vias or ground planes to it.

author: tautech
author_rank: Super Contributor
timestamp: September 09, 2014, 05:51:51 am
content: I like to think that because switching transitions are in the nS range and some chips can supply mA's that the decoupling cap not only helps supply the current, it also "decouples" the supply rail from some induced supply spikes generated within the IC at switching.And because of this decoupling caps should be included foreach & everyIC IMO.Tell me if this is not a correct assumption?

author: Falcon69
author_rank: Super Contributor
timestamp: September 09, 2014, 06:14:58 am
content: so, caps are mostly there to offset the voltage spike that could form because of the turn off/turn on characteristics of a switch or transistors going from the on to the off state, or vice versus?Figured it out, in Diptrace, you pour the copper pour, and then can select to with net to connect it too. So it looks like I can just run traces as normal, then when done, pour the copper and connect it to my ground net.I have a question on that however. In my current design, I will have several positive and ground rails. I will be running two of the step-up step down dc-dc converters bought from Ebay. But, because they only allow up to 3A each, I'll need to run two, so I was going to make it so one supplies the left LED's I will be using, and the second DC-DC converter would run the right LED's, which will supply the left and rightof the circuit with power and ground based off those separately. Then, I will have a main supply voltage that goes to a 7805 and then 5volts to supply all the IC's. Ultimately, I'd like to design one that takes the 12.8 volts from the vehicle, and convets it to 13.43 volts needed for the LED's. The Led's take 246mA each, and there will be 16 of them that operate at 12.8 volts, however, because each LED goes through a mosFET and a transistor, I will need 13.43 volts supplied to offset the voltage drop through those components so the LED's receive the full 12.8volts. But, I don't know how yet to make a single DC-DC SEPIC converter that delivers at the very least, 4.25A (preferable more, since 4.25A is the max the circuit actually runs at when everything is turned on). I want it Step-Up/Step-Down (SEPIC) because if the vehicle battery drops below or above the 12.8 voltage (which i'm sure it will), the circuit will still see the 13.43volts, thus LED"s see 12.8 continuous supply.So, with that said, How would I separate the copper pour to work that way? Or do I just make all the grounds connect to the copper pour on the bottom? Maybe I don't need to separate the grounds at all?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 09, 2014, 07:19:37 am
content: 1. The structure of a CMOS gate (or several bits inside the TLC555, which is a CMOS version of the eponymous one) inherently shorts out the supply for that short period of time when the input is between logic thresholds. This draws a current spike from the supply. How much? CD4000 series logic is good for maybe 10-20mA short circuit, so that's about the worst it can do. (It's worse if all outputs are transitioning at once, which is more likely to happen with counters, bus latches, etc.) CD4000 switches in the 100-200ns range, so you have a current spike that rises and falls over about that time.So, supposing you need to keep the supply voltage within 10% or thereabouts during switching, you can calculate the minimum capacitance required.The fundamental capacitor equation:I = C * dV/dtSo, C = (20mA) * N * (100ns) / (1.2V) = 1.667nF * NWhere N is the number of outputs switching at once (worst case, count all the output pins on all the ICs in your circuit, unless you know better e.g. some are tied off), 20mA is the current spike per pin, 100ns is the duration, and 1.2V is 10% of a 12V supply.0.1uF is cheap enough, so you can pepper them everywhere and not really care.<infomercial>But That's Not All!</infomercial>Supplies are generally inductive, due to trace length and stuff. So you have to consider, not just the first-line defenses (the bypass cap right at the chip), but the stuff feeding it, too. A few inches of ordinary trace will have around 50-100nH inductance, which will resonate with a 0.1uF capacitor at F = 1 / (2*pi*sqrt(L*C)) = 1.6-2.3MHz, and that resonance has an impedance of Z = sqrt(L/C) = 0.7-1 ohms.More generally, you want a supply with much less than (1.2V) / (0.02A) = 60 ohms per output pin, so a resonant impedance of 1 ohm sounds pretty reasonable, even for a few chips worth of logic (and yes, that would include wiring them all together, because that impedance is roughly characteristic of anywhere in this example supply circuit).But resonance doesn't sound too good. We need to make sure that stays damped, which means having a resistance attached to it somewhere, on the order of 0.7-1 ohms. Best solution? If suitable, a tantalum capacitor of several times larger capacitance (i.e., >0.47uF) and ESR around an ohm. Electrolytics are lossy too, but they're not nearly as stable. If tantalum isn't suitable (many reasons: current or voltage surges, high temperature, high reliability requirement, reduction of conflict minerals usage... etc.), then you can use a ceramic cap of the same value in series with an actual resistor.Following this example, the impedance remains in the ~1 ohm range anywhere within, say, four inches of a bypass cap (assuming your VDD routing isn't just spaghetti). At which point, you want to put down another, and so on.Once you get a chain, you get something of a lowpass filter circuit, or even a transmission line. These structures don't attenuate very well, in fact they love to keep signals moving. Which might be even worse, because you can have noise from one end of the circuit transmitted neatly to the other end where it's screwing up something unrelated! The trick to filters or transmission lines is -- like with the simple resonance case -- damping. In particular, you want to do it more towards the ends (source and end), since the waves will tend to slip along through the middle. The noise at any given point will be fairly even (not really dropping off as it goes), so if you need low noise at the end, either filter it there, or filter it at the source. (Or both!) Good filtering needs inductors, low-ESR caps (ceramic?) to get good attenuation, and enough bulk capacitance to -- guess what, keep the inductors from resonating! Same formulas apply.2. Among your examples, (A) is not even the preferred case -- not quite. Because it implies power enters from opposite sides, which means somewhere, there's a big huge loop going back to the supply. In the Olde Dayes, huge logic cards stuffed with TTL were the norm, often routed with VCC coming in the top, GND leaving the bottom, and signals all over the place inbetween. Bypass caps were spread liberally among the chips, so internal operation was fine, but because of the huge loops formed between rows of logic, the signal quality wasn't always that great. And often, these things gave off massive RFI from those loops! (Why did it work at all? TTL is slow -- the fastest computers probably topped out at a few MHz. It took that many nanoseconds for signals to settle, on top of chains of logic delays.)So, connecting this with my first point... local bypass is a good start, but at frequencies below resonance, that power supply loop is still just a loop of wire. So it'll be a bad antenna for lower frequencies, and that can induce noise in other loopy signal traces, give off noise and so on.What's the ideal case? Route VCC and GND together as a pair. Or, if you use a ground plane method, you've always got the pair -- as long as that ground isn't disturbed by traces cutting through it and all. (If it is, stitch it back together with vias to traces or pours on the opposite layer. Traces that are on opposite layers should be made to cross rather than run parallel -- make sure there's always some ground around every bunch of traces.) The same goes for signals, of course, which is why ground planes are so darned handy. Signals carry current (often, as much transient current as the supply), so they need to be well supported by ground nearby.Also, referring to your cases B and C, perhaps you've got a hint of why they aren't identical now?By the way...No SPICE simulator is 'smart' enough to know that those caps are different: in that sense, you are absolutely, positively, 100% correct, the caps are identical. They're also completely superfluous -- any connection (node or net) is considered exactly zero resistance and inductance, as are sources (unless defined otherwise -- beware LTSpice's built-in Rs, Ls parameters!). So, you never have to bypass supplies if it's in a simulation -- the sim voltage source is literally better than anything on Earth, because it's a model, a nonphysical approximation of reality. It is your responsibility, as the engineer driving the simulation model, to build something representative. The simulator just churns numbers, it doesn't know anything else (and once you realize these things, you'll be thankful it doesn't!).3. Why not pins being close? IC designers are dumb. Or something. I don't know.The high-falootin' series do actually use adjacent pins (1 and 14 in a SOIC-14, say, or maybe the middle pins), as do very large parts (even the Z80-CPU (DIP40) has power in the middle -- okay, not easy to put a through-hole cap across those pins, but it's something, right?).More recent examples might be, say, an ATmega324P -- in DIP40, with VDD/GND paired in the middle of the same side, not on opposite sides.Just about everything SMD over 20 pins has multiple supply pins, which are usually connected internally, but through high resistance die connections, and you don't want to force the poor chip to draw its current spikes through that. So you need to connect all common pins together with copper, and often, bypass them locally as well (since we're dealing with stuff a lot faster and punchier than old fashioned CD4000 logic!). Chips with multiple supplies (e.g., VCORE, VCCIO, maybe multiple banks, etc.) obviously don't internally connect the different supplies, but this can be handy sometimes: it's SOP to use different IO banks of an FPGA for different voltage domains -- each bank has its own VCCIOs.4. As for your converters and switches and stuff, why would you have multiple grounds? It sounds like, not only will they end up the same node (logically speaking, though not necessarily electrically so), but youneedthem shorted together, in order to drive common signals (MOSFET switches?) around them! The supplies should probably remain separate (so the DC-DC converters don't try to fight, as far as which one thinks their output voltage should be..), but if LEDs are the only loads, it won't matter much how they're routed (don't they just go straight to the LEDs, don't even need to touch the board?).Tim

author: Falcon69
author_rank: Super Contributor
timestamp: September 09, 2014, 07:48:21 am
content: Thanks Tim!So, you mentioned putting a 1ohm resistor in series with the caps? Would those go between the cap and ground, or the supply and cap? or does it not matter? You mentioned a tantulam capacitor of 0.47uF would be better than a ceramic 0.1uF capacitor to use for each IC? The tantulam caps are very expensive compared to the ceramic, and, for the same value, the size is bigger (0805 vs 0603). So, based on cost and size, I'd rather use the ceramic. Also, the tantulum caps i see, the lowest for an 0805 case at 10%, 25v, the ESR is 15ohms, you mentioned 1ohm. The Ceramic Caps aren't listing any ESR value. So do you mean with the Ceramic, I would need a 0.7-1.0 ohm resistor in series with those, whereas if I used a Tantulum Capacitor, I wouldn't need a Resistor in series? So, in other words, something like this....Tantulum 0.47orCeramic 0.1uF + Resistor 1.0 ohmFor this circuit, I'm only working with mosFETS, Logic Gates (CMOS 4000 series), Decade Counter, 555 Timer, and Transistors. I wouldn't be using anything highly advanced like Micro-Controllers, etc, as my level of knowledge is not even close to that advanced.If I don't make my board have solid copper pour on the second layer (bottom side) for the ground, then I need to run the ground parallel with the supply on the top side (or bottom, whichever)? You also mentioned that if the ground was on the bottom, instead of running parallel, i need to run the supply lines on top across the ground traces on the bottom? If It's a copper pour, does it matter?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 09, 2014, 11:58:58 pm
content: Quote from: Falcon69 on September 09, 2014, 07:48:21 amDoesn't matter, series is series.QuoteNo, in addition to. Using 0.1u per chip could potentially be worse, if it causes resonances.You could use a 0.1 + 1 ohm (or something like that) for most purposes, but this won't get you the lowest supply impedance -- obviously, it's got an ohm in series! The C1 || (R + C2) structure is intended to give lossiness at the crossover frequency (so it doesn't resonate much) while giving good bypass at high frequencies.QuoteYes, for these values, ceramic would be preferable. (A bigger circuit would benefit more from tantalum, by having a much larger power circuit, and thus needing a larger bulk capacitor, which will then have more appropriate ESR.)Ceramics don't usually list ESR, but either in the datasheet, or in supplementary information (appnotes, online database?), or in a database program you have to download and install (e.g., TDK's S.E.A.T.), something equivalent should be available somewhere. If ESR isn't explicitly stated, you can approximate it from the Z vs. F curve; the minima is where C cancels with ESL, leaving just ESR. (This point is also usually the ESR minima; ESR is somewhat higher at other frequencies, due to dielectric dissipation or skin effect.)It's usually safe to assume ESR is under 0.1 ohm, even for fairly small values. Big ones are in the 10mohm range or even less.QuoteStill with the 0.1uF in parallel with that, yes. So, the savings of tantalum (if the value chosen has the appropriate ESR value) is that it has the resistor inside, so you don't have to waste more space adding one yourself.QuoteIf you don't use ground plane/pour, you at least want the power and ground routed together. Top over bottom (in parallel, same location, adjacent layers) is slightly better than side-by-side. Use traces as wide as you can afford (more ground means more ground plane effect!).Opposite side crossing was in regards to signals or power crossing other signals or power; with ground all around, there is no 'crossing ground'. If you don't have ground pour to surround your signals with, you still want them as close as possible to whatever ground traces are present.Tim

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 01:15:08 am
content: Okay, just so I understandHere are some pics.I just did a quick draw up of a CD4017 in a TSSOP-16 package, 0.1uF 16v X7R 10% Ceramic Capacitor in a 0603 package ($0.06), 1ohm 1/4w 1% Resistor in a 0603 package ($0.26), and a 0.47uF 35v 13ohm 10ohm ESR 20% Tantalum Capacitor in a 1206 package ($0.14).So, if rhis is correct, it will cost an additional $0.46 per IC. I will have 9 total IC's (logic Gates/Timer) on my circuit. So it looks like $4.14 more to build this circuit. Pretty Costly (prices from Mouser for 1 each), but if this is the correct way of doing things, It needs to be done I guess.So, have I understand what you have said, and will these values work fine? All the IC's will be supplied via a 7805 5V regulator.The top lead going off the board (this is just for understanding a single chip fyi), is the Vcc or goes to the output of the 7805.The bottom lead going off the board is the ground going to the ground of the entire circuit. (Someone mentioned to just tie all the grounds together, making the bottom layer a ground plane.) The copper pour on top is not connected to any net. It's just there to fill in gaps. I hate looking at bare boards, so I do a copper pour as you see. Would it be better to do like I did on the bottom and connect it to the power? I have 3 different power sources. Might be abit difficult.

author: sacherjj
author_rank: Frequent Contributor
timestamp: September 10, 2014, 01:37:01 am
content: On Digikey, I'm seeing 0603 1 ohms resistors for $0.45 for 100. $2.01 gets you 1000.0603 0u1 caps $0.86/100.You have to realize that passives get really cheap, really fast. If you are buying them, just don't buy less than 100. You are paying more for the people's time picking the part than your part.

author: eetech00
author_rank: Regular Contributor
timestamp: September 10, 2014, 02:54:17 am
content: HiI noticed on your copper pour that an "Island" exist. That is...an area of the copper pour that is not connected to any signal.Islands can actually act as antennas, so should be removed or re-poured after adjusting the component placement. When completed, the entire pour should be connected to ground.So...the idea is to minimize emi and signal reflections by using a copper pour to help produce a capacitive coupling effect that helps reduce noise. There a many schools of thought on how to do this, but generally, for a 2 layer board, you place signal and power traces on the top layer, and ground (plane) on bottom layer.For a 2 layer board:1. Try to keep +supply voltages traces on one side (top) and create a ground plane on bottom.2. Try to keep all signal traces on the top side. Routing signal traces on the bottom side is ok, but should be kept to a minimum. Keep all traces as short as possible.When routing traces, follow this order:1. Route all +supply traces first, on top side, keeping traces as short as possible.Sometimes routing on bottom is necessary to avoid long traces. But avoid it if possible.2. Route all critical signal traces. Route on top, minimize on bottom.3. Route all remaining signal traces. Route on top, minimize on bottom.4. Create ground pour(plane) last, bottom side only.You might have go through a few iterations of these steps before its complete.After completing each routing step above, I would also perform a DRC (Design Rule Check) to be sure of no errors. Perform a DRC after each step, fix errors, then repeat.Good luckeT

author: eetech00
author_rank: Regular Contributor
timestamp: September 10, 2014, 03:12:42 am
content: Quote from: Falcon69 on September 09, 2014, 05:18:41 amHi againI would use a dedicated cap for each IC, just because the caps are so inexpensive, and it will provide some flexibility when placing the components on the board (the devices don't have to be close together because they don't have to share a cap). Also, if you use dedicated caps, then you don't have to worry about a Device being bypassed properly.Also, I noticed in other replies to your post, different comments on how to use caps to bypass. But, for your circuit, in my humble opinion, a single 0.1uf ceramic cap at each IC supply pin should do.Good luck..eT

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 03:47:41 am
content: Thank You for the tips eetech00I will try and do as you mentioned, however, there are so many transistors/mosfets on my circuit, and resistors, it's going to be impossible to route all the signal and power on the top of the board. In order to keep the board size small, I'll need to do alot of routing underneath as well. But, doing a copper pour on the bottom shouldn't be a problem.When I pour the copper on the bottom, what space should I have between my traces? Right now, I have it set at 0.25mm.

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 03:52:27 am
content: oh, so if I pour the top as well, i need to connect that to ground and any islands formed to ground as well? Putting a simple static via to connect top and bottom will be good enough for that?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 10, 2014, 04:51:37 am
content: You only need a few of the damping R+C (or tantalum C with its internal ESR) in the whole circuit, not one per chip. The 0.1 per chip (ceramic / low ESR) still applies (though you can generally relax that requirement to "0.1 per region", meaning, all chips within a certain trace length from the capacitor, say an inch or two).If you have small islands, you should probably just arrange traces so they don't form (or set design rules to remove islands under say 200 mil length, or however it is done). Larger islands, and peninsulas and such, should be stitched with vias to the opposite side pour. Islands aren't worth much if they have only one via, because current cannot flow up, across and out of them; small islands aren't worth using more than one via on (and so should probably be pushed out by rearranging the bounding traces), but larger ones you should put vias in the corners, so that current can flow across.Trace width and spacing are usually 6/6 mil minimum; check with your intended supplier. Personally, I wouldn't go under 10/10 mil for cheap Chinese boards. At that spacing, you will need design rule exceptions for TSSOPs, which require finer pad-to-pad gaps.Tim

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 06:16:48 am
content: Ive had boards made before with traces down to 0.15mm, The pcb manufacture I have doing them, do a good job, SO not worried about that. I was more worried about arcing. I read somewhere, though I dont remember where, that if traces are too close together, arcing can occur. Or even noise and false triggers of components.So, if I keep them at least 0.15mm apart, I should be okay? Does that even go for a signal trace that is 0.2mm wide, next to a power trace that is 0.95mm wide for example?So, If I place the 555 and CD4017 together, I can use cer.cap and res for each, and use one tant.cap for those two IC's. Then for the 7 logic gates, I can put those close together and use a cer.cap and res for each and one tant.cap for them? Would that be sufficient enough to handle any noise that could occur?

author: eetech00
author_rank: Regular Contributor
timestamp: September 10, 2014, 06:50:13 am
content: Quote from: Falcon69 on September 10, 2014, 03:47:41 amYour board fab house usually have a set of design rules you can use to set minimum spacings. 0.25mm is probably OK (thats the spacing I use), but check with your board fab house.eT

author: eetech00
author_rank: Regular Contributor
timestamp: September 10, 2014, 07:10:47 am
content: Quote from: Falcon69 on September 10, 2014, 03:52:27 amThat indicates that you haven't left enough space for the pour to "fill" between tracks to maintain pour continuity. Remove the pour, try nudging the components a little, then try adding the pour again until you get rid of the islands. It usually takes a few iterations before your get rid of most, or all, of them. Any remaining ones should be removed because they don't serve any purpose.Good PCB software will place Thermals, or vias, where it needs them to maintain signal continuity while honoring the design rules. Be sure to assign the signal to the pour before creating the pour, that way the software will make use of existing pin pads to make connections and know to place thermals or vias. When routing traces, be aware to leave space for the pour to fill between pads and traces.eT

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 07:16:11 am
content: I manually route everything. I tried using Dip Trace's automatic routing, and it really does suck. So I manually route everything, however, takes me several days :/

author: eetech00
author_rank: Regular Contributor
timestamp: September 10, 2014, 07:27:44 am
content: Quote from: Falcon69 on September 10, 2014, 06:16:48 amI don't think you don't need to worry about arching at the voltage levels you working with.QuoteThat spacing seems a little narrow. I'd use 0.010" or 0.012".QuoteYou really should follow best practice and use a cap for each IC supply pin.eT

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 07:34:04 am
content: there will be a 1ohm resistor in series with a 0.1uF ceramic cap on each supply pin of the IC's, I was talking about the added 0.47uF Tantalum Capacitor. Tim mentioned I don't need to put that on every IC, if they are close together.And yes, I am placing traces at least 0.25mm apart. I was just saying that the fab house can go down to o.15mm.Ya, i didn't think I needed to worry about the arcing, seeing how the circuit won't see more then 13.43volts, idea. Max amps with everything on is just under 6A.

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 07:35:37 am
content: Oh, another question. The 555 Timer has a supply pin 8, and a reset pin 4 that both connect to the supply. So, would I need a cap/res on the pin 4 as well? Or just tie it together with pin 8

author: Dago
author_rank: Frequent Contributor
timestamp: September 10, 2014, 07:39:48 am
content: Quote from: Falcon69 on September 10, 2014, 07:35:37 am8 is the supply pin and 4 (reset) is just a signal pin. You only need a cap for the supply pin. The reset pin draws neglible amount of current so it does not need decoupling.

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 07:54:54 am
content: awesome, thank you.Also, the connection to the bypass caps.I should not have any vias, or any other connection between the supply pins and the caps, (or resistor, in the case of ground pin) correct? so It should look like the picture?FYI, 555 Timer and CD4017 Decade Counter shown.

author: eetech00
author_rank: Regular Contributor
timestamp: September 10, 2014, 01:11:54 pm
content: QuoteI don't see any thermals.All ground connections should have thermal pads connecting each to the ground pour.eT

author: DanielS
author_rank: Frequent Contributor
timestamp: September 10, 2014, 05:54:36 pm
content: Quote from: Falcon69 on September 10, 2014, 07:34:04 amThe resistor is there simply to make the ceramic cap behave like a lossy tantalum so if you put a tantalum in there, there should be no need to make the ceramic lossy anymore.For high-speed chips with tons of parallel IOs and internal clocked logic (like FPGAs), you would not want to put resistors in the supply decoupling since the edge currents could cause the supply rails and ground to bounce below operating voltage. The lossy decoupling is something you add on top of normal (low-impedance) decoupling if you need to dampen noise, ringing and other junk.

author: Bassman59
author_rank: Super Contributor
timestamp: September 10, 2014, 06:28:06 pm
content: Quote from: Falcon69 on September 10, 2014, 07:35:37 amThe reason the reset pin is tied to the supply is to ensure that the reset isn't asserted (it's not being used).The only pins that need bypassing are the power supplies.

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 08:08:25 pm
content: I thought when using vias to connect the grounds of pins to the ground plane (copper Pour) on the bottom, you don;t use thermals. Only thermals for through hole parts that connect to ground, or for SMD pads that connect to ground for SMD parts that are on the bottom, if any.Okay, so since I am only using simple 4000 series logic chips, a single 0.1uF capacitor should be good enough? No need to run a resistor in series and/or a tantalum in parallel with them? That would save alot of board space.Oh, the reset pin, it just does not float or tied to ground?

author: tautech
author_rank: Super Contributor
timestamp: September 10, 2014, 08:32:07 pm
content: A reset pin is normally high or low only. Datasheet will advise. Sometimes their function is involved in the Truth Table.IMO and experience only 0.1 uF is needed per IC, although the wealth of experience that has been offered in this thread should not go unheeded.One of the most elegant replies IMO was fromeetech00:Without bypass caps, the IC's behavior may not be reliable because the chips are extremely sensitive to voltage fluctuations, either from the power supply or spurious sources, and it can causeinput levels or output levels to change unexpectedly, causing erratic circuit behavior.Itsbest practiceto place a 0.1u cap as close as possible to each IC supply pin. This is true for any CMOS IC device, including the 4000 series..This sums it up well.

author: DanielS
author_rank: Frequent Contributor
timestamp: September 10, 2014, 09:17:00 pm
content: Quote from: Falcon69 on September 10, 2014, 08:08:25 pmA single decoupling capacitor close to each chip's power pin(s) should be more than enough for simple logic gates. You can always plan a few extra footprints just in case. If you have long power traces, you will still need a larger decoupling capacitor every now and then to cancel the power trace's inductance and smooth out lower frequency junk.That reminds me of a 8088 motherboard I had many years ago with tons of 74-series chips arranged in rows and comb-style power distribution. It had large electrolytics on the comb's spine (board/zone-wide decoupling for low frequencies and power supply wiring), smaller electrolytics or tantalum at the end of each tooth (row of 5-10 ICs) and then the local decoupling ceramic cap for each chip.As for floating pins, you usually do not want to leave inputs hanging since that can cause unpredictable operation. For example, if you do nothing with unused parts of a 74xx04 logic inverter IC and many other discrete logic gates, the unused parts can go into oscillation so you want to tie all unused inputs to either power or ground to force them in a known and stable state.

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 09:41:54 pm
content: Understand,So, how long of a trace are we talking here for the power supply and need of a tantalum? In Diptrace, It tells me the length of EACH trace I click on. Kinda a nice feature.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 10, 2014, 11:43:46 pm
content: Quote from: eetech00 on September 10, 2014, 01:11:54 pmI never use thermals on vias connecting to polys, except when I know they may be used as test points. 'Cuz... thermals are to make soldering easier -- indeed, thermals only make everything else about the via worseI also usually tent them, which just makes the ground look sexier. Occasionally it makes nearby soldering easier, but that's not a big deal.It's always a good idea to leave a few extra-sized, un-tented, thermal'd vias in various nets (such as supply and ground) for those occasions when you do want to tie wires down, though.Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 10, 2014, 11:45:00 pm
content: Quote from: Falcon69 on September 10, 2014, 09:41:54 pmQuote from: T3sl4co1l on September 10, 2014, 04:51:37 am

author: Falcon69
author_rank: Super Contributor
timestamp: September 10, 2014, 11:49:48 pm
content: Okay, so maybe two per board. My board size is about 2x4 inches. So maybe I can put one at the beginning of the supply line and at the end of it (the last chip) and call it good?

author: tautech
author_rank: Super Contributor
timestamp: September 11, 2014, 12:01:27 am
content: Quote from: Falcon69 on September 10, 2014, 11:49:48 pmAlternatively place only the pads for now, populate the PCB, power it up and monitor the PSU rails with a scope and then decide if the extra "targeted" decoupling is necessary.

author: Falcon69
author_rank: Super Contributor
timestamp: September 11, 2014, 12:10:26 am
content: Well, I dont own a scope, or even know how to use one, let alone what too look for if I did own one. But, for now, I'll place the footprint for the added tantalum capacitors and when the boards come in and I get everything soldered up, I'll test it. If it doesn't work right, I'll add the Tantalum or take them to school and see if I can use their equipment to test.

author: DanielS
author_rank: Frequent Contributor
timestamp: September 11, 2014, 12:18:09 am
content: Quote from: Falcon69 on September 10, 2014, 09:41:54 pmThere is no universal answer to that or decoupling in general: the exact amount and type of decoupling that is necessary is application-specific. If you want exact numbers, you need to calculate the spectrum content of your outputs' rising and falling edge, the capacitance of their output traces, the inductance of their power supply, the capacitance of the input buffer at the end of the traces, equivalent lumped capacitance of internal circuits, other trace and via inductances, etc.. Once you know the exact current spectrum of the noise you need to cope with and the levels you need to get it down to, you select your capacitor mix accordingly. This selection may require considering the capacitors' own parasitic inductance on top of everything else.The 100nF per power pin figure is simply a convenient and relatively inexpensive starting point that works most of the time when you do not wish to do the math for something that should be trivial.You can always plan for extra footprints to put tantalum caps or MLCCs on just in case, measure supply noise on those pads and then decide what you might need to add there if anything. If supply noise/ripple remains well within the chips' requirements, you do not need to add anything on those extra pads. As someone else said in some other PCB thread: always plan for extra stuff - pads don't cost you anything.

author: Falcon69
author_rank: Super Contributor
timestamp: September 11, 2014, 12:23:40 am
content: okay Daniel.Sounds like a lot of math to deal with. I'm learning alot though, and that's what matters most to me.I appreciate everyone's input and knowledge. I've added the 1ohm resistor and 0.1uF ceramic (cheaper then adding a single tantalum) to each supply pin of the IC's. I will add in a footprint for an extra 0.47uF tantalum capacitor at the beginning and end of the Supply line, just in case I need to add those later. The cost of adding the extra footprints is pretty much pennies, if that, in cost of manufacturing boards, but could save the cost of manufacturing NEW boards later to add them.Thanks Everyone!Jason

author: eetech00
author_rank: Regular Contributor
timestamp: September 11, 2014, 02:21:38 am
content: Quote from: Falcon69 on September 10, 2014, 08:08:25 pmHiYes...that is correct. Thermals, generally, are only for pins (surface mount or thu hole) that must be soldered to a pour. My comment was meant to be a general FYI. I couldn't tell if the board you presented was a finished board, going to be re-worked, or whatever. But your thinking is basically correct.eT

author: Falcon69
author_rank: Super Contributor
timestamp: September 11, 2014, 02:33:44 am
content: That board was just a mock-up of what I was thinking for the placement of the bypass capacitors for a circuit I am currently trying to draw up.Having to manually route all the traces takes me a long time. My current design has something like 150 transistors/mosfets, 200 resistors, and about 15 IC (4000 series logic gates).I'm sure I'm over thinking my design and that a microcontroller would eliminate ALOT of those components, but I don't have the knowledge level for microprocessors yet.I'll post up a pick when I get it finished.

author: Falcon69
author_rank: Super Contributor
timestamp: September 17, 2014, 02:04:20 am
content: Well, I think It is done.The black circles are where the Cap and resistor are for bypass. One side of a 0.1uF cap is connected to the ground of the copper plane with two vias and then connected to the ground pin of the IC Chip. The other end of the cap is connected to a resistor (1ohm, or zero ohm if resistor not needed), and the other end of the resistor connected to supply and the +5v input of the IC Chip. The Red circles are the 0.47uF Tantalum Capacitors. One next to the +5v regulator and near the end of the last IC chip along the +5v supply line.How's it look?Sadly, I will need to use two jumper wires on the bottom side. Everything was just WAY to tight. The board is about 49mm x 118mm. 16 outputs to a 2-way LED Assemblies. 4 Inputs for control. Each fused and then a main power/ground input. The jumper headers are if I want to add an external Buck/Boost to each Left or Right inputs of LED's (8 Left, 8 Right LED outputs).

author: eetech00
author_rank: Regular Contributor
timestamp: September 17, 2014, 03:08:48 am
content: hiKeep in mind the image resolution is not very good, and without a schematic, I make the following comments without knowing much about what the circuit does, or any special signal/power requirements.but IMO...1. Seems to be a lot of unnecessary trace bends.2. Did you experiment using a ground pour on top side as well?3. Vias look a little large but difficult to tell from the image.4. Should be a clearance, from any trace or via, to edge of board.eT

author: Falcon69
author_rank: Super Contributor
timestamp: September 17, 2014, 03:14:35 am
content: trace bends are there to try and maximize the copper pour on the bottomI haven't poured a top ground, and probably won't, unless you or others advise me to do so.Vias are 0.7mm outer 0.35 inner. The manufacture I will use says they can do 0.6mm/0.3mm Should I reduce them to that? I just though that the bigger I went, the better the copper/tin/whatever will flow and make a good via.Clearance between traces and everywhere else is no less then 0.2mm. (that's for copper pour to traces, holes, etc. Everywhere else it is no less then 0.28mm)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 17, 2014, 08:16:14 am
content: What's all that stuff up along the top and bottom sides? Those look like they need power too!Tim

author: Falcon69
author_rank: Super Contributor
timestamp: September 17, 2014, 08:22:48 am
content: The throughhole pads on the top and bottom are for the LED assemblies. They have 3 wires for the. Ground, Park, and Brake. They are connected through the transistors/Mosfets for switching purposes and latching.The ones on the side are for Left/Right turn signal, Park, and Brake inputs, and the top one is for the main power and ground in. The very top, where the jump headers are, is so I can connect (if needed) two external Buck/Boost regulators if I cant get the correct voltage to the LED's through the mosfets and transistors. I am not sure if the battery power from the vehicle is good enough.But, for this thread, I'm mainly just interested in if the Bypass Capacitors are placed correctly. I tried to put them as close as I could to the power/ground inputs of the IC's.

author: eetech00
author_rank: Regular Contributor
timestamp: September 18, 2014, 12:31:37 am
content: Quote from: Falcon69 on September 17, 2014, 08:22:48 amHiSo....I'm sure others, as well as myself, would like to help but, without making assumptions, how are we supposed to know which pins are power and ground?Also, as a suggestion, for this kind of board, place a ground pour on both sides to eliminate ground traces and some via's...eT