Annular Rings Basic Question - Page 1
Forum section: electronics / general

author: TinyMirrors
author_rank: Contributor
timestamp: August 21, 2019, 03:46:55 pm
content: For vias, are annular rings only for the layers which you would like to connect? Can I leave zero ring for layers that which the via is simply passing through? If this is true, can I remove the annular ring for layers the via doesn't connect? Such as bringing power from a power plane. Can I just use the annular ring on the layers that connect the power and remove the ring on all other layers?For example, routing a signal from the top layer to layer 3, would layer 2 and the bottom layer need a ring as well? I have no idea what happens in the manufacturing of boards for this.I'm trying to route a bga for the first time, and I've never thought about what annular rings on vias are actually for. If I leave them, I don't have room to route. It seems like Altium lets you choose the annular ring size per layer.I'm trying to route a 0.8mm xilinx fpga bga with 4mil traces and 0.2mm vias. I'm not using all pins. I need a 6 mil annular ring by manufacture's spec.Thanks for the help guys!

author: nctnico
author_rank: Super Contributor
timestamp: August 23, 2019, 12:08:15 am
content: Yes, you can leave the annular rings on the unconnected layers. You'll probably need to create several different vias for the via fanout structure.

author: langwadt
author_rank: Super Contributor
timestamp: August 23, 2019, 12:19:59 am
content: afaiu some PCB manufacturers do remove it automatically because it improves yield, but if you can convince your tool to do it you get more space for routingI believe the technical term is "non-functional pads"

author: nctnico
author_rank: Super Contributor
timestamp: August 23, 2019, 11:44:38 am
content: Quote from: langwadt on August 23, 2019, 12:19:59 amSome CAD packages can remove these pads during post-processing. For high speed signals it is better that there are no pads on the non-connected layers however you (usually) can't do without the pads on the outer layers. And deletion during post-processing doesn't help during board design because you'll get DRC errors. Personally I rather solve DRC errors than ignoring them.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 23, 2019, 02:48:56 pm
content: Annular rings on inner layers are usually thinner than on outter layers (most PCB software do that by default, and it's adjustable), but I don't know if you can really set them to zero?Not completely sure this would be doable from a manufacturing POV. Your thoughts?

author: nctnico
author_rank: Super Contributor
timestamp: August 23, 2019, 03:42:34 pm
content: Quote from: SiliconWizard on August 23, 2019, 02:48:56 pmA via without inner pads is like a normal plated through hole. Remember the holes get drilled plated after all the layers have been pressed together (*). So if there is no pad on a layer the hole still get plated through and through.The annular ring is a minimum pad size (and usually they have to be bigger on the inner layers) to make sure the hole in the pad is fully surrounded by copper so the chance the plating makes a connection is maximal.* With burried vias the production process is slightly different but the idea still applies.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 23, 2019, 08:22:48 pm
content: Well, obviously, whether the vias are through-hole, buried or blind, they will at least require an annular ring on each end layer, otherwise they are not vias. For blind or buried, that's already at least one inner layer.