Boost converter output calculations WRT efficiency - Page 1
Forum section: electronics / beginners

author: pyrohaz
author_rank: Regular Contributor
timestamp: August 20, 2014, 02:31:23 pm
content: Hi all,I'm teaching myself a bit about boost converters and one of the main things I'm wondering is if I'm correctly calculating the output conditions with respect to efficiency. The way I'm currently doing it is:Work out maximum power stored in Inductor (IL*VL), multiply this by efficiency (as a decimal between 0 and 1) then that is the theoretical maximum output power you can get wrt efficiency. It might sound a little simple what I'm asking so I'll do an example:Input voltage 10vMax inductor current 1ATotal "stored power" (I know thats wrong as power = energy/time but I dont know the correct term) = 10WEfficiency = 80%Total "convertible power" = 10*0.8 = 8WI want an output voltage of say 20v therefore to calculate my maximum output current, at an efficiency of 80%, I can get 8/20 = 0.4A.Is this the correct way of calculating this sort of thing? Obviously, lumped into that "efficiency" value is the use of ideal components etc.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 20, 2014, 11:21:41 pm
content: So you're trying to do what now?It sounds like you're just throwing coefficients together and praying that something useful will come out...The reactive power in the inductor has no bearing on (DC) power transfer; in the extreme case, a very high frequency can use an arbitrarily small inductor, and therefore reactive power (stored energy) can be arbitrarily small.Actually, I guess from your examples, you're just looking for the volts/amps/watts budgets on the input and output sides? That's pure conservation of energy, no invocation of inductors required (it applies to inductive converters, capacitive charge pumps...steam engines...you name it). Vin * Iin * Eff = Vout * Iout. Nothing more than ratios.A much more interesting question would be, how to derive that efficiency figure in the first place...Tim

author: pyrohaz
author_rank: Regular Contributor
timestamp: August 21, 2014, 08:12:22 am
content: That's very true! Sorry, I didn't give a very good explanation in my initial question. Let me expand on what I'm currently looking to do:So I'm literally simulating the simplest boost converter topology in LTSpice. A mosfet, a square wave voltage source, an inductor and a diode. I've got the inductor wired to when the mosfet is on, V+ is present across the inductor. I have a custom diode model in parallel with the mosfet, cathode to ground, anode to the point connecting the mosfet and inductor. The forward voltage of this diode is set to the output voltage that I'm using in my equation. Using a mosfet with a 1m ohm on resistance and placing the efficiency value in my equation to ~99%, the output current (at the VF of the diode) peaks at the value that I calculate. What I'm wondering I suppose is where is the relation to the output current/voltage of the boost converter to the input waveform parameters to the mosfet. Obviously in reality, a load won't be a non linear step from near infinite to ~0ohm resistance at the voltage you want. With a resistor as the load, how can one predict what voltages and currents will be present? If an inductor has 10A flowing through it, with a diode with a negligible VFwd (lets assume idea at 0 for now), will a 10 ohm resistor have 10A flowing through producing 1000v when the current through the inductor is interrupted and will the voltage across the resistor exponentially decrease until the voltage is equal to V+ (once again, neglecting diode VFwd and inductor ESR). I'm just trying to clear myself up with a bit of theory here!I'll include an image of the first simulation I did so you can hopefully visualise my idea! In the picture, you can see that after the diode current falls to zero, there is some sinusoidal oscillations. Is this due to the inductor forming a resonant tank with the mosfet capacitances and slowly draining off the energy stored?Harris

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 21, 2014, 12:07:34 pm
content: Well, you do it piece by piece, of course!Signals move at finite rates. (They also have all continuous derivatives, but we can cheat and use just one continuous derivative.) So, initially, drain voltage is 10V, and gate voltage is 0. Now a step comes along and gate voltage starts rising. Actually, gate current starts rising, and voltage begins to swing -- the gate capacitances charge, which includes Cgd, which is important, because when Vgs passes Vgs(th), Vds starts falling, and Cgd has to charge by Vgs(final) + Vdd, not just Vgs. This occurs during the linear range, when drain current is rising and drain voltage is falling.You can calculate how long the turn-on event takes. If your gate driver is an ideal Thevenin equivalent, with a perfect speed driver, some total series resistance (usually the driver resistance, plus a small external resistor, plus the MOSFET's internal gate spreading resistance), and the gate charges like a capacitor, then the 0-63% rise time is t=RC. The 10-90% will be more like 2RC. The gate doesn't charge like a capacitor, because it's all kinds of nonlinear, but as long as you don't care too deeply about the exact waveform (it won't be an exponential ramp), the time will be representative. Oh, and what to use for C? Certainly not the figure they give at Vds = Vgs = 0V or whatever. No, you want the charge equivalent. So look at Qg(tot) / Vgs(on). Maybe it's 48nC at 10V, so call it 4.8nF for the average/effective capacitance.Actual rise/fall time at the drain will be shorter, because most of the voltage change occurs during the Miller plateau when Cgd is charging.Now that you know turn-on time (roughly), you can calculate turn-on energy.Switching on into an empty inductor DCM (discontinuous) or BCM (boundary conduction mode), current stays low during turn-on, so the energy dissipated is essentially Cgd + Cds. You can guess the equivalent energy (E = 0.5 * C * Vds(off)^2), or it's occasionally specified in the datasheet (equivalent capacitance, energy related; or drain charge / energy versus voltage).While the transistor is on, current rises approximately linearly with time (assumes Vds stays low and Vdd stays constant). The conduction power dissipation is then a rising parabola, because P = I^2 * R and I = t * Vdd / L. Recalling calculus, the area of a triangle is (1/2) * w * h; the area of a parabolic section is simply 1/3 instead. So, the conduction power is (1/3) * D * Rds(on) * Ipk^2 (for duty cycle = D).When the transistor turns off, first the gate voltage falls a bit, then drain voltage starts rising. Drain current remains near Ipk. Cgd is charging (in the reverse) here, and you get another Miller plateau. Once drain voltage gets clamped by the diode, drain current finally falls (the diode grabs all the inductor current) and the transistor turns off. During this transient, drain voltage rises roughly linearly (not actually, because again, capacitance isn't linear), while drain current remains constant. In the second phase, drain voltage remains constant while drain current falls. So, power loss is a triangle of height Vout * Ipk and width t_off, or a turn-off energy of (1/2) * Vout * Ipk * t_off.While the transistor is off, leakage can safely be ignored. If you have two transistors in an inverter (instead of one plus a diode), you can get hard switching when the opposite transistor turns on. The fast dV/dt gets coupled by Cgd into the gate, which can cause it to turn on momentarily (needless to say, the losses can be huge, because the inverter is momentarily shorting itself out). This isn't a common problem with MOSFETs, but it can be with IGBTs. The easiest solution is some negative bias in the 'off' state (usually +15/-5V drive, instead of +10/0 or whatever).So, add up all the power losses, and for the energies, multiply by switching frequency to get their contribution to power. Sum it all up and that's your switch loss.If you're operating in CCM (continuous current mode), the inductor current will be nonzero by the time the transistor switches on again. The diode will still be conducting, so the transistor is going to yank it off in hard switching. There are a couple of things to keep in mind during this transient, such as loop inductance (between transistor, diode and load capacitor), gate voltage dV/dt (the transistor has transconductance, which sets dI/dt, which controls diode recovery speed and peak current). In any case, the result is much the same as during turn-off, except that Ipk is I_L(min) plus diode recovery current. If you're using a schottky diode, you don't have to worry about reverse recovery, but the junction capacitance is much higher, which can cause problems all its own (it still looks like reverse recovery, though not with the extra delay time in there).Overall system losses also include the diode (you can assume it has a constant Vf, so the power is 0.5 * Ipk * Vf * (1-D) at duty cycle D), inductor (conduction losses and, if possible, eddy current and core losses -- an inductor specified for DC only, will probably run 10-100% hotter under switching conditions!), capacitors (ESR -- calculate like transistor conduction losses, but for the other half of the waveform) and anything else nearby (current sense resistors, damper / snubber components, maybe a fraction of a watt for the control circuitry, etc.).If you have a good simulation (your example is obviously not a good realistic one), you can also measure the loss in various components. But do make sure it's a very precise simulation (lower RELTOL and other TOLs, smaller maximum timestep, higher order integration methods) because SPICE is generally very bad at calculating rapidly changing parameters, and getting the sums and differences correct over time (very broadly, if you calculate Pin, Pout, and all the losses inbetween, Pin = Pout + Ploss will only be true within a factor of RELTOL, or probably much worse).Tim

author: pyrohaz
author_rank: Regular Contributor
timestamp: August 22, 2014, 08:10:31 am
content: Quote from: T3sl4co1l on August 21, 2014, 12:07:34 pmWow! Thats one heck of a lot to take in. So with regards to the gate capacitances, as the capacitance is voltage dependent, would this explain why I see a sort of "step" at Vgs(th) in the drive waveform if I add a smallish series resistor?Ok so for this example, I'm going to use the IRFP240 mosfet. With a specified "Total Gate Charge" of 70nC at 10v, using the standard Q=CV, its equivalent to charging a 7nF capacitor. I'm assuming I have to use I = C dV/dt to calculate the maximum current with respect to rise time. What is a good estimation of rise time? In the data sheet, there is a rise time parameter though I assume that this is the fastest rate at which the mosfet can respond to a rising waveform? Regardless, if I choose this value, at 51ns, I should be looking at a peak current of 7e-9*10/51e-9 = 1.37A. Is it ever a good idea to have asymmetrical rise and fall specifications? The "rise time" is specified at 51ns though the fall time is 36ns. Obviously, I'm going to want to reduce this to as small as possible so I can minimise switching losses so for a fall current, I should be looking at 7e-9*-10/36e-9 = -1.94A, right?Just as a quick sanity check, when you say switching current into an inductor, the current stays low during turn on, is this just because the turn on time is miniscule compared to the time at which current starts to flow significantly through an inductor?I'm starting to understand more so what you're saying with respect to the losses. Could you point me to where I could find a graph of the non linear capacitances vs Vgs? I'm intrigued is all!Harris

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 22, 2014, 09:12:12 am
content: Quote from: pyrohaz on August 22, 2014, 08:10:31 amYes; and the step is still there whether you used a resistor or not, because there's always resistance somewhere, whether you can see it or not.QuoteIf you had a function of C in terms of voltage (because C(V) isn't constant), and the relation of V to I (is the driver resistive, or...), and you want to solve the differential equation I(t) = C(V) * d/dt (V(I)), then yes, you could use that equation.But you don't need to know what I(t) or V(t) is, as long as the average is right. So you can wave your hands and say, okay, C isn't constant, but it averages to so-and-so, so it's going to look more-or-less like a resistor (assuming the driver and all comes to some average resistance), and it's going to be more-or-less charged by a couple RC time constants.When you SPICE something, if your models are good (incorporating C(V) and V(I) and so on), you are, in fact, iteratively computing the solution to this differential equation (among many others in the overall circuit). It should be no surprise that SPICE is such an inefficient (but, when used well, fairly accurate) tool!QuoteNo.Note the R_G spec on that parameter.I've noticed Fairchild MOSFETs (at least the modest to smaller ones) often specify 25 ohms, which really means they used a standard 50 ohm function generator, into a 50 ohm (parallel termination) resistor. The Thevenin equivalent at point-of-load is 25 ohms, so they just hang G-S on there, hook up a typical load (supply + resistor) to D-S, and scope it. The time is measured at the drain voltage, so it does not account for how hard the transistor saturates (after the Miller plateau, gate voltage continues to rise, and Rds(on) falls to its rated value), or capacitive effects (Cds is inseparable from the measurement, so it is impossible to measure the actual channel current I_ds during switching).As for asymmetry, if Vgs(th) is towards one end of the drive voltage (say, 3V out of a 0-10V waveform), it's not hard to guess which slope will have the slower edge! Logic level MOSFETs are even more exaggerated for the same reason.If R_g is specified (internal gate spreading resistance), you can approximate the theoretical response time of the transistor: simply Rg * Qg / Vgs(on). This isn't quite true, because parts of the die closest to the gate bondwire will turn on first, and at high frequencies, those parts will dissipate much switching loss; while parts further away will be turning on and off much more slowly, and will dissipate conduction losses, like, all the time. For most power transistors, this is up in the MHz, where they can kinda-sorta be used as linear amplifiers, but switching as such, straight out. (Proper RF transistors are well suited to linear operation, because they are designed for minimal capacitance, pretty high Rds(on) because they aren't switching, and low gate spreading resistance for high frequency response.)QuoteNot obvious -- you often *want* the transistor to switch slightly slowly. The loop inductance of the switching circuit (between transistor, diode and load capacitor), combined with junction capacitance (of the transistor when switching off, or of the diode when switching on), forms a resonant circuit which leads to excessive peak current or voltage during switching. The reason it is broadly proscribed to "minimize loop inductance" is because, if you get the inductance low enough, the impedance Z = sqrt(L/C) has a chance to be small enough that voltage spikes don't cause problems (peak switching current shows up as peak overshoot voltage, and vice versa, with Vpk/Ipk ~= Z), and the time constant t ~= sqrt(LC) being shorter than the switching time means there isn't enough harmonic energy to excite that resonance.Unfortunately, modern transistors are always faster than that, so if you do drive them hard, you're guaranteed to have problems. Should it be any accident, then, that this documenthttp://www.ti.com/lit/an/slpa010/slpa010.pdfmanifestly fails to achieve its claimed goal of reducing or eliminating that ringing?Moral of the story, don't attempt to eliminate inductance, don't turn a blind eye and assume it's negligible; because you can't, and it never is. Instead, optimize junction capacitance and loop inductance -- yes, even by adding explicit capacitors or inductors to the circuit. These elements do store some energy, which factors directly into switching losses (a capacitor stores energy with the change in voltage: E = (1/2) * C * V^2; an inductor with current: E = (1/2) * L * I^2). The losses usually need to be absorbed by damping resistors, but they can also be recycled using "lossless" (quasi-resonant) snubbers or other methods. The advantage is, rather than burning a huge gulp of switching loss, you take a slightly smaller hit on the snubber, which is now dissipating it in a dumb resistor or something, and not your precious transistors -- which are now more efficient, or cheaper devices, or can deliver more current for the same losses.QuoteYes. If you want to get more detailed, you can draw I(t) = L * int(V dt) during the switching event, but it's usually going to be well less than 10% of anything important, so can be ignored during that time.QuoteYes, the Qg vs. Vgs plot in the datasheet shows this: the reciprocal slope dV/dQ is the capacitance. For the drain, you can look at capacitance vs. Vds (at Vgs = 0), and note how Cdg changes strongly as well as Cds.The huge capacitance at low voltages (under 10 or 20V usually) means that most of the Miller plateau actually occurs at low voltages, which actually helps a bit with switching losses, and can serve a snubbing effect, to some extent (namely, as the voltage rockets downward toward 0V, the rising capacitance acts to cushion it, and it rings less than if capacitance were the constant average value).Tim