High Bandwidth Current Injector for Impedance measurements - Page 1
Forum section: electronics / projects

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 20, 2020, 11:47:44 pm
content: Hi,I recently shared two projects on the Test Equipment section of the forum. Both are for performing measurements on power supplies.The first one is a PSRR Injector that is used to measure a power supply's ripple rejection ratio.This project can be found here:https://www.eevblog.com/forum/testgear/psrr-injector/msg3025318/#msg3025318I also shared some information on the correct way to use an injection transformer for measuring the closed loop response of a power supply in this thread:https://www.eevblog.com/forum/testgear/injection-transformers-bode-plots-application/msg3021218/#msg3021218This is a similar project. It is the construction of a high frequency current injection device that can be used to measure the impedance of capacitor or Power Distribution Networks.There are commercial products like the PicoTest J2112A that are designed for this application.This is a DIY solution that doesn't use any exotic parts.The target specification is 50MHz of bandwidth (-3dB)LTspice SimulationLike many of my projects I started with LTspice.Here is the model:Circuit descriptionQ2 is a fixed current source.Q1,Q2 and Q4 are a current sink that is modulated by the input signal.Q5 is a transistor operated in common base. This is a speed up trick, reduces the collector base voltage variations on Q1, Q2 and Q4.The modulated current flows through L1, C2 and R6 to the output. L1 is not a real component but included to represent the wiring inductance between the injector and the device been tested.There is a monitor port that allows the current to be monitored. The scaling is around 1mV/1mAModelling in the Frequency DomainThe LTspice predicts a -3dB bandwidth of 70MHz.Transient ResponseThe model is showing rise and fall times of around 10nsTo be continued …Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 20, 2020, 11:59:50 pm
content: Hi,Here is the real schematic:Board DesignThis is the other side of the board:To be continued …Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 21, 2020, 12:06:11 am
content: Hi,Here are some pictures of a prototype.Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 21, 2020, 12:56:29 am
content: Hi,Testing with an HP3325BThe rise and fall times of the HP3325B are around 10ns.The Tektronix P6022 current probe has a published BW of 120MHz.This is what the output of the current injector looks like when been driven by the HP3325A at 5MHz:The input was 1V p-p the output is 80mA p-pThe HP3325A is not really fast enough to test this circuit.Testing with HP8112A Pulse GeneratorThe HP8112A has 5ns rise and fall times.This shows the current waveform measured with a Tektronix P6022 current probe with the input driven by the HP8112A pulse generator.Rise TimeThis is the rise time at 10ns /divFall timeThe fall time at 10ns / divThe circuit is performing very well. It probably exceed the ability of the Tektronix P6022 current probe.Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 21, 2020, 05:27:34 pm
content: Hi,I continued working on the Current Injector.The components in the attenuator for the monitor port were installed. This network gives a 30resistance at the emitter of Q4 and output impedance of 50The combined result is a monitor signal that is 1mV/mATesting Monitor OutputThe upper trace is the monitor output. The lower trace is the output current measured with a Tektronix P6022 probe.ApplicationI am going to share one application of the current injector.The current injector input is connected to the source of a network analyzer.Channel R is connected to the monitor output of the current injector.The current output is connected to a 1resistor with a very short twisted cable.Channel A of the VNA is connected across the resistor with a 50cable.1 Ohm ResistorA 1 Ohm resistor consisting of three 3resistors connected in parallel is used as a standard.The VNA configured to display channel A / Channel RThis is voltage / CurrentThis is the result. It is very flat but increases above about 50MHz.This result is normalized on the VNA.The VNA is now calibrated in dBMeasuring a capacitorA capacitor is connected in a similar way to the resistor.Here is the graph:The marker is indicating -9.21dBat 100kHz-9.21dB= 0.346C= 1/(2 x Pi x F x Xc)C= 4.6uFAt the minimum the impedance is -46dB-46dB=5mThis is the ESR of the capacitorWith cursor at 20MHz the impedance is -17.3dB-17.3dB= 136mL = Xl / 2 x Pi x FL = 1.08nHThis illustrates how the current injector can be used to characterise a ceramic capacitor.Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 22, 2020, 12:57:45 am
content: Hi,Here is another measurement that can be performed with the Current Injector.I have added a Bias Injector to the setup:Here is a picture of the Bias Injector:Impedance MeasurementI measured the impedance at 0V bias and I measured -8.53dBat 100kHz-8.53 dBat 100kHz = 4.24 uFI set the Bias voltage to 40V, this is a 50V capacitor, I measured -0.8dB-0.8dBat 100kHz = 1.74uFThe capacitance has been reduced by 59% by the bias voltage.Notice how the self resonant frequency moves to a higher frequency and the inductance of the capacitor is unchanged by the bias voltage.Regards,Jay_Diddy_B

author: schmitt trigger
author_rank: Super Contributor
timestamp: April 22, 2020, 01:10:50 am
content: Very, very impressive project.Thanks for sharing.

author: 16bitanalogue
author_rank: Regular Contributor
timestamp: April 22, 2020, 04:34:30 pm
content: A couple of comments:1. This is a good DIY solution to measure passives. +/-10% is good enough as I typically want to be in the ballpark (sanity check).2. There are several bumps in the transient response - this would indicate low phase margin, but this behavior is not observed on the voltage waveform. Are we exceeding the capability of the current probe? This is me really asking for less of a 'ripply' response.3. Can you provide some additional insight into the purpose of Q5 'speed up trick'? Is the intent to keep Q1, Q2, Q4 to share equally?4. Are you comfortable of sharing the LTSpice circuit and the KiCAD files? I need to start dipping my foot into KiCAD myself - transitioning from Eagle.I can compile a BOM and ultimately compare costs to PicoTest.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 22, 2020, 05:25:09 pm
content: The combination of Q1-3 + Q5 is a normal cascode circuit, nothing so unusual. It lets the collectors of Q1-3 see a low impedance for high speed. Just the choice of Q5 is odd to me: the MJE182 does not look like especially fast. My choice would be more like BD135, 2N2219, 2N3019.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 22, 2020, 06:32:33 pm
content: Quote from: 16bitanalogue on April 22, 2020, 04:34:30 pmIn the transient response the ripple could be coming from the source. It is pretty hard to make a square wave pulse with 5ns rise and fall times.The frequency response on the VNA is flat. This suggests that there aren't any resonances in the circuit.Quote from: 16bitanalogue on April 22, 2020, 04:34:30 pmThere are some major differences in performance:1) The circuit presented here is AC coupled so the maximum output voltage depends on the coupling capacitor in the output.2) Because it is AC coupled it can safely be used when testing LDOs because it can't cause over voltages.3) It has a HF -3dB bandwidth beyond 50MHz. The PicoTest product isuseable to 40MHzit is actually about -15dB at 40MHzQuote from: Kleinstein on April 22, 2020, 05:25:09 pmThis is correct Q5 is operating in common base.The datasheet specification of the FT for the MJE182 is 50MHzIn this application the current gain is unity, so the BW=FTI can't find FT on the BD135 datasheets from ST and ON-Semi.(I suspect that they are similar to the MJE182, if not the same transistors)The 2N3866 might be a good choice, but I am reluctant to use it because of the large number of fakes.It is hard enough confirming the performance at 50MHz ….Regards,Jay_Diddy_B

author: Kleinstein
author_rank: Super Contributor
timestamp: April 22, 2020, 07:50:52 pm
content: In a Phillips datasheet for the BD135 they give 190 MHz as typical fT. The BD135 is also a little lower current than the MJE182, so likely not the same chip. If the power is not too high the 2n2219 (250 MHz fT) could also work well - I would not expect to many fakes there.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 23, 2020, 02:03:41 am
content: Hi group,I tried this BD135 in the circuit, it made very little difference.I am not sure of the manufacturer.Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 23, 2020, 02:11:16 am
content: Hi,I did get some improvement by shortening the leads and twisting better.BeforeAfterNote that the frequency sweep has been extended to 200MHzNew WiringThis is how the connection was made for the improved result.LTspice SimulationThe wiring inductance was stepped from 5nH to 200nHThe limitation is the wiring inductance, not the transistors.Regards,Jay_Diddy_B

author: Wolfgang
author_rank: Super Contributor
timestamp: April 26, 2020, 01:41:39 pm
content: Very true. The fastest transistors will only lead to oscillations, a pragmatic design with moderate top frequency but robust and stable is better.If you must have ultra fast edges think of an RF design directly attached to the load and using RF design rules.What are your trying to measure ?

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 26, 2020, 04:40:42 pm
content: Quote from: Wolfgang on April 26, 2020, 01:41:39 pmHi,The use of current injectors has been proposed, (by people that sell them) for evaluating the closed loop performance of power supplies where the top of the divider is not accessible and the there is no other suitable injection point.I am not sure about the usefulness of this application. The reason is that this test is the frequency domain version of a stepped load current test. If the power supply is well damped you can't tell too much about the loop from the transient load test except that it is stable. If the power supply has a small phase margin you might be able to tell more.ExampleIf I set the LTspice to measure the output impedance of the power supply, which has a known crossover frequency of 80kHz and phase margin of 85 DegreesI get this resultAt 10 MHz, the power supply has no influence, we are measuring 0.5which is the ESR of the output capacitor.At lower frequencies the control loop is reducing the output impedance.I can't see how you learn about the phase margin from the output impedance graph.Parallel Decoupling CapacitorsMeasuring the effectiveness of decoupling capacitors is a good application for this type of current injector.We often see multiple values of decoupling capacitors in parallel and explained like this:It is not quite as simple as this.I tested a 4.7uF capacitor on its own:and 4.7uF capacitor in parallel with a 470nF capacitor:Theses are the measured results:The bright trace is the 4.7uF capacitor.The dim trace is the parallel combination.Note:there is a range of frequencies around 5MHz, where the parallel combination has higher impedance.At frequencies around 20MHz the impedance is half for the parallel combination. There are two ESLs (1nH each) in parallel.This is a good application for the high frequency current injector.Regards,Jay_Diddy_B

author: 16bitanalogue
author_rank: Regular Contributor
timestamp: April 26, 2020, 10:29:59 pm
content: Hello Jay_Diddy,Back some years ago, I would access stability of linear amplifiers solely by the rate-of-closure method with the closed loop gain graph superimposed on the open-loop gain graph. This is fairly simple to do because the feedback node is available, most op-amps can be modeled as a linear second order system; e.g., one, low frequency dominant pole and a high frequency pole with a nice 20dB/dec role off.For Power supplies, feedback node is not available. Some adjustable options may have an external divider, but that is still not the feedback node of the error amplifier.Frankly, in my limited experience with DCDC converters, the closed loop method is predominantly used in industry. The gain-phase is closed loop and the load step/release in the time domain helps correlate or perhaps better stated as "back up" the frequency response in closed loop.Picotest has an application note on using the output impedance and Q of the response over frequency. I believe the purpose when measuring output impedance over frequency, one wishes to find the Q of the response and this is related to phase margin. Picotest pushes this as non-invasive measurement technique and frankly would be very helpful with customer designs when trying to determine stability in a production prototype or released system. Who wants to cut traces, which one may not even have access to in a 10 layer board, when one can measure output impedance.I am simple person so Bode and load transients are my tools. When I grow up, I will try the output impedance method and/or Nyquist.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 27, 2020, 01:32:38 am
content: Quote from: 16bitanalogue on April 26, 2020, 10:29:59 pmThis is really my point. If you have a power supply that that has a very dominant single pole, it doesn't have a measurable Q so you can't determine very much about the stability.If you have a two pole system, the smaller the phase margin, the higher the Q and easier it is to determine stability with the current injector. But that isn't a good design anyway.I am interested in trying to measure the stability non-invasively. I will try one day …Regards,Jay_Diddy_B

author: 16bitanalogue
author_rank: Regular Contributor
timestamp: April 27, 2020, 01:46:04 am
content: Quote from: Jay_Diddy_B on April 27, 2020, 01:32:38 amI'm speaking from ignorance, but most DCDC converters that I have seen (buck, boost topologies mostly) are more complex than your textbook 2nd order linear system. There are multiple poles and zeros in the type 2 and especially type 3 compensator. I don't believe these types of designs could be modeled by a single dominant pole. My guess is this is where the current injector shines with the non-invasive measurement.I still have trouble with the Bode 100 - trying to find a suitable signal level that 1) does not overdrive the feedback network at 'HF', and 2) large enough to overcome noise.

author: Wolfgang
author_rank: Super Contributor
timestamp: April 27, 2020, 08:56:18 am
content: Hi,two comments about this:- the NISM method is, strictly mathematically speaking, *only* correct if you have a second-order system, i.e. *one* dominant pole.Picotests has mentioned this (not very prominently) in their product description. Complex multipole systems - watch out- for a system with strong resonances, its very normal that a sweep with a constant power level drives your system into nonlinearitiesin the vicinities of the resonances. It makes sense to run a sweep with non-constant power levels of the frequency range. A lot of VNAscan do that, what I know the Bode100 too (ask Omicron). A smart trick for stubborn systems is to use a flat noise source and thenmeasure the frequency response by an FFT.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 27, 2020, 01:40:47 pm
content: Hi,Using information that I found here:https://www.picotest.com/images/download/non-invasive-assessment-of-voltage-regulator-phase-margin.pdfI constructed a small signal model of a typical current mode switching power supply.Included in the model:A transconductance to represent the output stageA transconductance to represent the error amplifierA delay to simulate that the switching supply control is a sampled at the switching frequencyThe power supply is two polesThe output transconductance and the output capacitor is one pole.The Error amplifier is the second pole.There is a zero in the error amplifier to obtain stability.The error amplifier is 'stepped' to generate power supplies with different phase margins.This is the invasive model. The loop gain can be measured from the error amplifier input to the output voltage divider.These are the familiar Bode plots showing the bandwidth and phase as the error amplifier is stepped.NISM ModelThe is the NISM model. The model is set to measure output impedance.There are .meas statements to measure the phase margin according to the reference above.There are two methods. One is based on a simplified curve fit. The other is more accurate.These are the impedance curves.ResultsYou can see the differences between the techniques.There is reasonable accuracy for Q greater than 0.8The more complex calculation should be used for Q<0.8 or phase margin greater than 60 degrees.Note:This is all theoretical, it doesn't consider the challenges of measuring small signals in a noisy environment.I have attached the LTspice model.Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 27, 2020, 02:07:24 pm
content: Hi,Let us look at the same power supply with a transient load step:The power supply is arranged to step through the same error amplifier settings in the time domain.ResultsObservation if the phase margin is less than 70 degrees to you can estimate the phase margin by looking at the transient response.If the phase margin is greater than 70 degrees, all you can determine is that the phase margin is greater than 70 degrees.Regards,Jay_Diddy_B

author: Wolfgang
author_rank: Super Contributor
timestamp: April 27, 2020, 02:13:24 pm
content: in a few words: NISM: No good pole, no phase margin. Too many close poles/zeros: guesswork.

author: 16bitanalogue
author_rank: Regular Contributor
timestamp: April 27, 2020, 02:32:24 pm
content: Quote from: Wolfgang on April 27, 2020, 08:56:18 amCan you point out where Picotest subtly suggests this? It has been a long time, but if someone were to ask me to describe a linear second order system - I would pull from my op-amp knowledge base. A single, low frequency dominant pole around 10-100Hz and a single high frequency pole (perhaps 2) that is located after unity gain cutoff. The response would be your nice 20dB/dec roll off in gain.When I review error amp (compensator) design in DCDC converters, I always see multiple pole/zero pairs throughout the bandwidth. Can you elaborate?

author: Wolfgang
author_rank: Super Contributor
timestamp: April 27, 2020, 02:46:30 pm
content: IIRC, the method works on Q(Tg), i.e. the stepness of phase change at a pole.As long the poles are well apart, and steep enough, OK. If not - see above.IIRC, Sandler said the method is exact for 2nd order systems (which is correct). In return, it is *not* exact for higher order.For really low impedance stuff, time domain techniques could be useful. Make a steep current step and watch the response.I am notoriously sceptical of linear approaches in multiloop regulators. If just one of the loops gets nonlinear or saturated,the whole theory falls apart. From a step response you dont have this problem.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 27, 2020, 03:57:15 pm
content: Hi,If I further simplify the model by:1) Removing the load resistor2) Removing the ESR in the output capacitorThis make the output transconductance amplifier a pure integrator.3) Remove the delay in the switching circuit. The delay only cause phase shift, no change in amplitude.4) remove the noise filter in the error amplifier.There is now two poles and one zero left in the loop.The result of doing this:The two results now agree exactly.This confirms the comment from Sandler, shared by Wolfgang:Quote from: Wolfgang on April 27, 2020, 02:46:30 pmRegards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 27, 2020, 04:05:50 pm
content: Quote from: 16bitanalogue on April 27, 2020, 02:32:24 pmThis topic should really be discussed in at least three different contexts:1) Current Mode switching power supplies. They have the general form that I have a have modelledDominated by the output transconductance and output capacitanceDominated by the error amplifierModified by ESR zero,Modified by noise filtering poles.Most modern switching power supplies use this topology2) Voltage mode circuitsThese generally need the type III compensator to deal with the double pole in the output filter.Output Filter - Double PoleError amplifier - low frequency pole, multiple zeros, HF pole for noise reductionESR zeroetc.3) Various LDO designs…Regards,Jay_Diddy_B

author: Wolfgang
author_rank: Super Contributor
timestamp: April 27, 2020, 04:06:10 pm
content: ... and now, to test the limits, make a complex regulator with several poles and see how close the method gets.My prediction: If you find a single strong "dominant" pole, it works OK, if not, it produces nonsense.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 27, 2020, 04:18:28 pm
content: Hi,This Bode plot shows how predicable the behaviour of the 2 Pole, 1 Zero circuit is:(When I did this it reminded me of 35 years ago, when we used LOG LOG paper and straight line approximations to do loop design)It is basically head towards 0dB on a two pole slope, at frequency X turn left take a 1 pole slope and continue heading across 0dB …Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 27, 2020, 04:31:20 pm
content: Quote from: Wolfgang on April 27, 2020, 04:06:10 pmIn addition to this there is the issue of signal amplitudes:The power supply that I am simulating is based on a 6A monolithic regulator.The output impedance is 50mSo if the injector can inject 10mA RMSWe have a signal size of 500uV RMS at the peak, 350uV RMS at the -3dB points.( I know my HP3577A can operate with 10 Hz bandwidth to shutout other signals)Has anybody seen this technique being used with switching regulators?Jay_Diddy_B

author: Wolfgang
author_rank: Super Contributor
timestamp: April 27, 2020, 04:41:36 pm
content: For multi-Amp devices your injected current is way too small. What about ca. 10% of the load current ?Then you can expect to see something sticking out of the noise.To the extremes, if you have an FPGA with several 10Amps at 1.1V you really need to bang the part with some Amps to see an effect.The injector must be almost soldered into the circuit to avoid parasitic inductances (every nanohenry counts).

author: 16bitanalogue
author_rank: Regular Contributor
timestamp: April 27, 2020, 05:07:08 pm
content: Quote from: Jay_Diddy_B on April 27, 2020, 04:05:50 pmThanks for the download. Converter design is still new to me, and I am certain there is a paper (along with hallway discussions) that go into details about where to place the poles and zeros. I presume since most designs implement current control mode and if (presuming) the poles zero design rule of thumb is that they are placed far enough apart then the Q(Tg) method is 'expected' to work. It's one of those boundary assumptions that is not spoken about and is locked up in Tribal Knowledge for those who live and breathe converter design.I was at a company where the topology was a voltage control mode, multi-level converter for battery charging. Spoiler Alert - shit didn't work (lots of problems). Now I get to work with simpler designs - standard bucks and boosts and the majority of the topologies are current control mode, Type II transconductance compensator.

author: wa8pzl
author_rank: Newbie
timestamp: July 12, 2024, 07:32:08 pm
content: I had some boards burned for this project, results not as pretty as the OP's, but can confirm that the capacitance, ESL and ESR measurements work.