sovled: STM32G0 backup registers - guaranteed to be zero at initial power on? - Page 1
Forum section: electronics / general

author: incf
author_rank: Frequent Contributor
timestamp: July 07, 2025, 05:08:04 pm
content: Suppose I have a STM32G0 series MCU that has its VBAT pin connected to VDD.My particular model of 'G0 has 5x 32bit backup registers in the RTC domain.I've noticed that the value of the backup registers often appears to be all zeros from a true cold bootup (<10mV across VDD).Does anyone know if the backup registers are guaranteed to have a value of zero when power is initially applied?In my testing, the backup registers tend to retain their values to VDD values at least as low as 600mV (the residual left in the decoupling capacitors after several minutes of sitting disconnected, which is well below the power on reset voltage).I'm not quite sure if they implement some sort of reset or if the backup SRAM cells are just designed in such a way that they greatly prefer to settle to a value of 0 rather than 1 at power on.

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: July 07, 2025, 05:42:50 pm
content: As long as you have initialized the RTC to some year (not 0), you can monitor the RTC_ICSR register to see if the INITS bit is set or not.Just check it when you start up.

author: voltsandjolts
author_rank: Unknown
timestamp: July 07, 2025, 06:03:29 pm
content: guaranteed = false;if (datasheet says it's guaranteed) {guaranteed = true;}

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 07, 2025, 06:49:49 pm
content: The datasheet is not where to look in this case - ST datasheets give little details - but the reference manual.I think you're in luck, because it suggests that a RTC domain reset will reset the backup registers (along with the RTC registers). A RTC domain reset happens if both VDD and VBAT fall below the minimum threshold (see DS for values).Backup registers are also linked to the Tamper detection feature and so can be configured to be reset if a tamper condition is detected.Note that while the fact a tamper condition can reset (clear) the backup registers is documented, the RM says that a "RTC domain reset" (which is what seems to be what you're interested in) "affects" the backup registers. It doesn't explicitely say that it clears them. But I can only infer that's what will happen from how the whole RTC domain works. So, I'd say I'm 90% confident in that the backup registers will get cleared when VCC and VBAT drop below a certain threshold, but I can't guarantee it 100%.You can read the RM and see if you find more explicit info that what I saw (RM0454).

author: incf
author_rank: Frequent Contributor
timestamp: July 07, 2025, 07:34:32 pm
content: Quote from: SiliconWizard on July 07, 2025, 06:49:49 pmThat's what I'm getting at.The hardware power on reset triggers below about 1.8V.But, I've observed that the backup registers persist their values with power removed for several minutes (ie. with 0.6V residual left on VDD due to some decoupling capacitors). And I've observed that short circuiting VDD such that VDD<10mV results in the registers "seeming" to always initialize to all zeros.To me, it seems as if maybe there is no hardware reset affecting the backup registers. Just some unusually well behaved SRAM cells that maybe are not guaranteed to always initialize to a known value.I'm hoping someone has some insight into how exactly ST managed to pull off putting together silicon with this sort of (good?) behavior.If I recall correctly, on other older models of STM32 the backup registers often contained random values.

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: July 07, 2025, 08:44:30 pm
content: The reference manual guarantees that the RTC Domain Reset value is 0x00000000Now how do you detect the RTC Domain Reset? Like I mentioned before the easiest way to do this is use the bit provided in the RTC initialization/control/status register.When the INITS bit is set you have not reset the backup registers and their values are valid even if it is 0. If the INITS bit is 0 the domain has reset and the value is 0 and invalid.Once the calendar has been set this bit will remain set during system resets and only reset when the backup domain resets. (or the year is set to 0)

author: incf
author_rank: Frequent Contributor
timestamp: July 07, 2025, 09:10:38 pm
content: Quote from: Pseudobyte on July 07, 2025, 08:44:30 pmThank youI missed that.I also confused myself by mistakenly thinking that my system was triggering the conditions necessary to reset the backup domain, which lead me to wrongly conclude that it didn't affect those registers, but I was wrong.Turns out reset only occurs if both VDD triggers a POR and (unpublished spec) VDD and/or VBAT drops to some very low value like 10mV.That solves my question.

author: wek
author_rank: Frequent Contributor
timestamp: July 08, 2025, 01:46:25 pm
content: In 'G0 (and in fact most STM32 up to the era of 'G0), backup domain reset requires VBAT to drop below somewhere between 100mV and 700mV,readthe respective errata.JW

author: peter-h
author_rank: Super Contributor
timestamp: July 08, 2025, 02:51:08 pm
content: Not sure if this the same issue but AFAIK there is no way to tell if Vbat got too low and the RTC time got corrupted.In my last project, a magic 32 bit number is stored during factory init in one of the RTC domain RAM locations and, if found corrupted, the RTC is re-initialised. It seems to work reliably enough.

author: incf
author_rank: Frequent Contributor
timestamp: July 08, 2025, 03:36:27 pm
content: It is very much related, I think

author: peter-h
author_rank: Super Contributor
timestamp: July 09, 2025, 03:59:50 am
content: So is there some way to reliably tell RTC corruption/loss on a 32F417?If a way was ever published, it was well hidden at the time

author: incf
author_rank: Frequent Contributor
timestamp: July 09, 2025, 10:36:43 am
content: Quote from: peter-h on July 09, 2025, 03:59:50 amone could compute a CRC checksum of all of the control/status/time registers once per minute, or once per second

author: peter-h
author_rank: Super Contributor
timestamp: July 09, 2025, 04:38:08 pm
content: I don't get how that would work. Say you use a supercap, life about 4 days (my testing with a 0.22F cap) and you power up the box after 3-4 days. You really have no way of knowing if the RTC had stopped in the meantime.It is like the time in GPS NMEA data. No way to validate it, other than sanity checks e.g. year>2024, mins and secs 0-59, etc.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 09, 2025, 08:22:02 pm
content: Well, assuming the RTC registers and backup registers behave similarly, which sounds reasonable as they are both part of the RTC domain and likely identical in terms of silicon, you can store some data in the backup registers, including a CRC of this data. If at power-on, the CRC is wrong, that means the backup registers haven't retained their value and it's in turn reasonable to assume that the RTC registers do not contain valid values either. This may not be 100% foolproof, but worth doing IMO. Now, sure, maybe the value of the registers themselves is retained much longer (so at a much lower voltage) than the RTC oscillator operates, so even a valid CRC could be misleading, but OTOH, a bad CRC would mean with a good probability that the RTC date/time can't be trusted.

author: peter-h
author_rank: Super Contributor
timestamp: July 10, 2025, 06:30:31 am
content: Yes that is what I did - store 0xaa55aa55 or some such.It is obviously not a guarantee because bits are bound to decay at slightly different times against a slowly falling Vbat, bit it should be ok in practice because the customer's situation is likely to be either a box with a totally dead battery/supercap, or a good one. A supercap also lasts at most a few days on these 1uA-drawing chips, which is much less time than your product is going to sit on your shelf before it gets shipped.

author: uer166
author_rank: Super Contributor
timestamp: July 11, 2025, 01:53:17 am
content: Somewhat related: what happens to an interrupted backup domain register write (for example undervoltage reset). Or just a plain external nRST assert.Does it run to completion or nothing happens? Or does data get corrupted.