Vivado pre synthesis sim works but post has logic removed making it not work! - Page 1
Forum section: electronics / general

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 07, 2016, 09:59:05 pm
content: So i'm trying to complete a project in Vivado but finding it difficult. I have used Quartus in the past.I have some HDL that sims correctly in behavioral simulation but once it has been synthesized by Vivado I get warnings saying nearly 100 registers haven't been and thus removed but now it doesn't work! In behavioral sim I look at the registers being removed by synthesis and they indeed being used. I have posted a question on the Xilinx forums but they are awfully slow. I wonder if anyone here has any suggestions?The code is partially written to interface with an image sensor and the part being tested is the serial update of the registers. I have a couple of state machines - one for the SPI clocking the data out and another to assign the write data to the SPI module and create pulses to start the SPI state machine. In the behavioral sim everything seems to work however in post synth sim the SPI module seems never to be reached. I've gone through the reports in Vivado trying to track down which register might not be being reached (timing error) but as there's little information there it's very difficult. Also, look at the pre synth sim I have been careful to add basic extra clock cycles to accommodate for that sort of thing. Basically I'm left scratching my head! Code below.I have also simed the modules individually and they work fine.Any help would be awesome! ThanksCode:[Synth 8-3332] Sequential element (sclk_en_reg) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (spi_data_reg) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (state_reg) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\data_stage_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\int_spi_data_reg ) is unused and will be removed from module spi_16bit.[Synth 8-3332] Sequential element (\trans_state_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\spi_data_reg_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.[Synth 8-3332] Sequential element (\ibis_regs_reg ) is unused and will be removed from module ibis_reg_update.

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 07, 2016, 10:03:11 pm
content: CodeCode:/*A module to update the registers in the ibis4_6600 image sensor.Now need to:- add a facilty to create custom register values based on the 'config_data'.- add busy line.*/module ibis_reg_update (//clock and resetinput logicclk_200M, nrst,//Input data capture and latchinput logic [31:0]config_data,input logicconfig_latch,//SPI connectionsoutput logicspi_data = 0, spi_clk = 0, reg_clk = 0,//Status outputoutput logicbusy);/*Variables correspoding to the IBIS4 config registers.Defaults set for 30fps video at 640x480 pixels.*/logic[11:0]ibis_regs = '{//Default valueReg NameAddrNotes12'b000000000000,//reg_sequencer00All normal12'b000111100000,//reg_nrof_pixels01480pixels12'b001010000000,//reg_nrof_lines02640 lines12'b000000000000,//reg_int_time03Not done \/ \/12'b000000000011,//reg_delay0412'b000000000000,//reg_x_reg0512'b000000000000,//reg_y_reg0612'b000000000000,//reg_img_core_reg0712'b000000010000,//reg_amp_reg0812'b000000000000,//reg_dac_raw_reg0912'b000000000000,//reg_dac_fine_reg1012'b000000000000,//reg_dac_dark_reg1112'b000000000000//reg_adc_reg12};logic[3:0]reg_addr = 0;logic[7:0]clock_div = 0;logicstart_pulse, reg_upd_clk = 0, spi_latch, spi_busy;logic[1:0]trans_state = 0;logic[15:0]spi_data_reg = 0, reg_upd_counter = 0;//Generate 10MHz 'reg_upd_clk'always_ff @ (posedge clk_200M or negedge nrst)begin//Resetif(nrst == 0)beginreg_upd_clk = 0;clock_div = 0;end//Generate clockelsebeginif(clock_div == 9)beginreg_upd_clk <= ~reg_upd_clk;clock_div <= 0;endelse clock_div++;endend//Latch the 'config_data' into the current memeoryalways_ff @ (posedge config_latch)beginif(config_data == 0)begin//Default valueReg NameAddrNotesibis_regs =12'b000000000000;//reg_sequencer00All normalibis_regs =12'b000111100000;//reg_nrof_pixels01480pixelsibis_regs =12'b001010000000;//reg_nrof_lines02640 linesibis_regs =12'b000000000000;//reg_int_time03Not done \/ \/ibis_regs =12'b000000000011;//reg_delay04ibis_regs =12'b000000000000;//reg_x_reg05ibis_regs =12'b000000000000;//reg_y_reg06ibis_regs =12'b000000000000;//reg_img_core_reg07ibis_regs =12'b000000010000;//reg_amp_reg08ibis_regs =12'b000000000000;//reg_dac_raw_reg09ibis_regs = 12'b000000000000;//reg_dac_fine_reg10ibis_regs = 12'b000000000000;//reg_dac_dark_reg11ibis_regs = 12'b000000000000;//reg_adc_reg12endend//Start the register update sequencealways_ff @ (negedge reg_upd_clk or negedge nrst)begin//Resetif(nrst == 0)begintrans_state = 0;reg_upd_counter = 0;spi_latch = 0;reg_clk = 0;reg_addr = 0;end//Runelsebegincase(trans_state)//Wait for the start pulse to start the transmission0: beginif(start_pulse == 1) trans_state = 1;end1: begin//Reset the counter after 25 clock cyclesif(reg_upd_counter == 25)beginreg_upd_counter <= 0;endelsebegin//increment the counterreg_upd_counter++;case(reg_upd_counter)1:beginspi_data_reg[15:12] <= reg_addr;spi_data_reg[11:0]<= ibis_regs;end2:begin//Start the SPI transmission for 'reg_addr'.spi_latch <= 1;end5:beginspi_latch <= 0;end23: begin//Latch the data int othe image sensor with 'reg_clk'.reg_clk <= 1;end24: begin//Repeat 13 times incrementing 'reg_addr' each time.reg_clk <= 0;if(reg_addr == 12)begintrans_state <= 0;reg_addr <= 0;endelsebeginreg_addr++;endendendcaseendendendcaseendendpulse_gengen0(.in_edge(config_latch), .clk(reg_upd_clk), .out_pulse(start_pulse));spi_16bit spi0(.clk_200M(clk_200M), .nrst(nrst),.data_in(spi_data_reg),.data_latch(spi_latch),.spi_sclk(spi_clk),.spi_data(spi_data),.busy(spi_busy));assign busy = spi_busy | trans_state;endmoduleCode:/*A regular SPI hardware module to send a 16bit number at 10MHz with a 200MHz master clock.*/module spi_16bit(//Input controlinput logicclk_200M, nrst,//Input datainput logic [15:0] data_in,input logicdata_latch,//Output pinsoutput logicspi_sclk = 0,spi_data = 0,busy);/*Generate the 10MHz SCLK*/logic [3:0]clk_divider = 0;logicint_spi_clk = 0;always_ff @ (posedge clk_200M or negedge nrst)begin//Resetif(nrst == 0)beginclk_divider = 0;end//Normal Operationelsebeginif(clk_divider == 9)beginclk_divider = 0;int_spi_clk = ~int_spi_clk;endelsebeginclk_divider++;endendend/*Send the data out on the spi pin*/logic [15:0]int_spi_data;logicstate = 0, sclk_en = 0;logic [15:0]data_stage = 16;assign busy = state;//Capture the input data on the rising edge of 'data_latch'always_ff @ (posedge data_latch or negedge nrst)beginif(nrst == 0)beginint_spi_data = 0;endelsebeginint_spi_data = data_in;endendalways_combbeginif(sclk_en == 1)spi_sclk = int_spi_clk;else spi_sclk = 0;end//Generates a starting pulse for the data transmissionpulse_gengen0(.in_edge(data_latch), .clk(int_spi_clk), .out_pulse(output_pulse));//Clock the data outalways_ff @ (negedge int_spi_clk or negedge nrst)beginif(nrst == 0)beginstate = 0;sclk_en = 0;data_stage = 16;endelsebegincase(state)0: beginif(output_pulse == 1)beginstate = 1;endend1: beginif(data_stage == 0)beginstate <= 0;sclk_en <= 0;data_stage <= 16;endelsebeginsclk_en <= 1;spi_data <= int_spi_data[data_stage - 1];data_stage--;endendendcaseendendendmoduleCode:/*Pulse generator creates a pulse of 'n' number of 'clk' cycles.*/module pulse_gen(//Inputsinput logic in_edge,clk,//Outputoutput logic out_pulse);regr1 = 0, r2 = 0, r3 = 0, r4 = 0;always_ff @ (posedge clk)beginr1 <= in_edge; // first stage of 2-stage synchronizerr2 <= r1; // second stage of 2-stage synchronizerr3 <= r2; // edge detector memoryr4 <= r3;endassign out_pulse = r2 & ~r4;endmodule

author: filssavi
author_rank: Frequent Contributor
timestamp: April 07, 2016, 10:46:49 pm
content: Usually when vivado removes logic (registers but not only) he does that because as the code is written they will never switchI had your same issue as you before and the main problem is that in behavioural mode the simulator executes pretty much anything you throw at it (even if it isn't synthetizable), synth is a lot more picky about the codeSo I think that register deletion per se is not the cause, it is indeed the effect, the true problem lurks somewhere in your code

author: rstofer
author_rank: Super Contributor
timestamp: April 08, 2016, 01:38:30 pm
content: Does your logic ultimately wind up at a pin? If not, it's removed and everything that provides logic to create that signal, all the way up the chain, is removed as well. There can be layers and layers of logic that ultimately wiggle MOSI (for example) but if MOSI isn't assigned to a pin, it's all removed.Something like that...

author: 6thimage
author_rank: Regular Contributor
timestamp: April 08, 2016, 02:13:12 pm
content: Have you read the entirety of the synthesis report? Whenever logic is being removed, the synthesis tool will give a reason, it might only be one line (i.e. an enable line being constantly low for a module will result in the entire module being removed). I have quickly thrown your 3 files into vivado and got this under the cross boundary optimisation section in the synthesis report (line 163 and 164 from vivado 2015.4):Code:WARNING: [Synth 8-3917] design ibis_reg_update has port spi_data driven by constant 0WARNING: [Synth 8-3917] design ibis_reg_update has port spi_clk driven by constant 0If you change (in ibis_reg_update)Code:output logic spi_data = 0, spi_clk = 0, reg_clk = 0,toCode:output logic spi_data, spi_clk, reg_clk = 0,this warning is not generated and the utilisation goes from 89 LUTs and 62 registers to 104 LUTS and 82 registers (artix-7). Whether this fixes your problem is something else (I haven't had much of a chance to use system verilog yet, as I'm currently working with spartan 6 devices).Also, you generate clocks from logic, which is generally not a good idea. It is much better to have an enable signal for a higher speed clock. So instead of creating the spi clock by dividing the input clk by 10, make it so that it produces an enable pulse every 10 clocks that only lasts one clock. It will improve the timing characteristics of the design and will probably require less resources. Additionally, with the intelligent clock gating in most synthesis tools, it will consume less dynamic power.I'm also surprised thatCode:always_ff @ (posedge config_latch)works, as config_latch will be treated as a clock, which is unlikely to be what you want and could cause metastability (if config_latch is not synchronous with your other clocks).

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 11, 2016, 02:37:31 pm
content: Quote from: rstofer on April 08, 2016, 01:38:30 pmIt does and doesn't work I'm afraid.

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 11, 2016, 02:40:29 pm
content: Quote from: 6thimage on April 08, 2016, 02:13:12 pmThanks for your reply - it's helpful.The thing is even when in simulation of just the spa module it still doesn't work and baffles me! I have rewritten the module to somethings a lot more wordy but very explicit. Now the SCLK is output in the simulation however the SDATA is not! Even when the pins are driven as constants through the state machine it still doesn't work!Code:/*A regular SPI hardware module to send a 16bit number at 10MHz with a 200MHz master clock.*/module spi_16bit(//Input controlinput logicclk_200M, nrst,//Input datainput logic [15:0] data_in,input logicdata_latch,//Output pinsoutput logicspi_sclk,spi_data,busy);/*Generate the 10MHz SCLK*/logic [3:0]clk_divider = 0;logicint_spi_clk = 0;always_ff @ (posedge clk_200M or negedge nrst)begin//Resetif(nrst == 0)beginclk_divider = 0;end//Normal Operationelsebeginif(clk_divider == 4)beginclk_divider = 0;int_spi_clk = ~int_spi_clk;endelsebeginclk_divider++;endendend/*Send the data out on the spi pin*/logic [15:0]int_spi_data = 0;logic [5:0]state = 0;//Capture the input data on the rising edge of 'data_latch'always_ff @ (posedge data_latch or negedge nrst)beginif(nrst == 0)beginint_spi_data = 0;endelsebeginint_spi_data = data_in;endend//Generates a starting pulse for the data transmissionpulse_gengen0(.in_edge(data_latch), .clk(int_spi_clk), .out_pulse(output_pulse));//Clock the data outalways_ff @ (negedge int_spi_clk or negedge nrst)beginif(nrst == 0)beginstate = 0;endelsebegincase(state)0: beginif(output_pulse == 1)beginstate <= 1;busy <= 1;endelsebeginbusy <= 0;spi_sclk <= 0;endend//15th bit in the data1: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end2: beginspi_sclk <= 1;state++;end//14th bit in the data3: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end4: beginspi_sclk <= 1;state++;end//13th bit in the data5: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end6: beginspi_sclk <= 1;state++;end//12th bit in the data7: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end8: beginspi_sclk <= 1;state++;end//11th bit in the data9: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end10: beginspi_sclk <= 1;state++;end//10th bit in the data11: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end12: beginspi_sclk <= 1;state++;end//9th bit in the data13: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end14: beginspi_sclk <= 1;state++;end//8th bit in the data15: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end16: beginspi_sclk <= 1;state++;end//7th bit in the data17: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end18: beginspi_sclk <= 1;state++;end//6th bit in the data19: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end20: beginspi_sclk <= 1;state++;end//5th bit in the data21: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end22: beginspi_sclk <= 1;state++;end//4th bit in the data23: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end24: beginspi_sclk <= 1;state++;end//3rd bit in the data25: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end26: beginspi_sclk <= 1;state++;end//2nd bit in the data27: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end28: beginspi_sclk <= 1;state++;end//1st bit in the data29: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end30: beginspi_sclk <= 1;state++;end//0th bit in the data31: beginspi_data <= int_spi_data;spi_sclk <= 0;state++;end32: beginspi_sclk <= 1;state <= 0;endendcaseendendendmodule

author: Boscoe
author_rank: Frequent Contributor
timestamp: April 11, 2016, 02:43:32 pm
content: PS I tried changing the initial values assign the silk and data signals but it didn't work.Attached is the output of the sim for the above code.

author: kfnight
author_rank: Regular Contributor
timestamp: April 11, 2016, 09:42:17 pm
content: This probably won't fix your problem, but your flip-flops are using a combination of blocking and non-blocking assignments. Usually non-blocking assignments are used exclusively within flip-flips. So code like thisCode://Generate 10MHz 'reg_upd_clk'always_ff @ (posedge clk_200M or negedge nrst)begin//Resetif(nrst == 0)beginreg_upd_clk = 0;clock_div = 0;end//Generate clockelsebeginif(clock_div == 9)beginreg_upd_clk <= ~reg_upd_clk;clock_div <= 0;endelse clock_div++;endendshould be likeCode://Generate 10MHz 'reg_upd_clk'always_ff @ (posedge clk_200M or negedge nrst)begin//Resetif(nrst == 0)beginreg_upd_clk <= 0;clock_div <= 0;end//Generate clockelsebeginif(clock_div == 9)beginreg_upd_clk <= ~reg_upd_clk;clock_div <= 0;endelse//clock_div++;clock_div <= clock_div + 1;endendThis also highlights a SystemVerilog gotcha. The C-style increment and decrement operators behave as blocking assignments, so clock_div++ is equivalent to clock_div = clock_div + 1.