Hole edge to solder mask edge clearance for tented vias - Page 1
Forum section: electronics / general

author: ajb
author_rank: Super Contributor
timestamp: February 13, 2015, 08:46:42 pm
content: Anyone have any recommendations on how much clearance is required between the edge of a via hole and the edge of the soldermask for reliable tenting? Essentially I'm wondering how close to a pad I can put a tented via before having to worry about solder thieving. Obviously the design clearance will need to take into account the manufacturer's mask alignment tolerance, but once that's accounted for, how much clearance is required to ensure good adhesion of the mask? Is it sufficient to go by the manufacturer's minimum mask width?

author: free_electron
author_rank: Super Contributor
timestamp: February 13, 2015, 08:53:16 pm
content: if the via is completely tented : the minimum annular ring + the minimum solder mask aperture.they guarantee a drill strike on the via pad , but not necessarily on the center. so the annular ring protects them for off-center strikes.worst case they strike so the drill edge touches the pad edge. ( if they go over the board is rejected )in this case the registration offset of the mask is too tight and solder could leak in.so by adding the minium solder mask aperture in such a case you still have the minimum solder mask aperture to protect you

author: ajb
author_rank: Super Contributor
timestamp: February 13, 2015, 09:12:15 pm
content: Good point, I hadn't even thought of drill hit tolerance. That's a pretty clear guideline, thanks.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 14, 2015, 04:50:38 am
content: Tenting? I always set it to zero (in Altium, tag the "tented on X side"), which wholly removes the solder mask opening.Such vias will sometimes have goo stuck in them, partially (stuck to the inside) or sometimes with small vias (<= 10 mil), fully (plugged).I'm not aware that there's any advantage to setting the solder mask aperture to anything in particular. If you want to guarantee nothing gets stuck in the hole, you'd have to apply: hole radius + hole uncertainty + mask uncertainty = min mask opening radius. Which is typically 3+3 mil, or an extra 12 mil diameter -- as you're working with two of the worst dimensional alignments of the PCB fab. That's more than the minimum annular ring, so such a via need not necessarily be "tented" as such, at all!Such an approach would help a little on larger vias, where you are able to conserve some space between nearby solderable surfaces -- a via between two connected pads, for instance (a solder wicking hazard). But I still don't think it's advantageous over a fully tented via, which should be unsolderable right up to the edge of the hole, and insulated until within a few mil of the edge.Tim

author: free_electron
author_rank: Super Contributor
timestamp: February 14, 2015, 06:00:33 am
content: @Tesla : that's not the question. he's essentially asking what is the minimum amount of soldermask between a pad and a via. since the hole in the via , worst case, touches the edge of the via pad itself the minimum distance must be set to the minimum soldermask sliver. that is what i am explaining.as for tenting : it depends what masking material is used. Dryfilm can handle larger via openings than liquid soldermask.the risk with liquid soldermask is that only 'one side' of the via is open and the other side painted shut. during final wash, post soldering, contamination can trap in a via that is open only on one end leading to failure at a later point in time. ( for exampl CAF formation due to surface contamination in the hole) a via should either be completely open both sides, or completely closed both sides. half open is problematic.if a fully exposed via ( no mask whatsoever) is not desirable you 'encroach' the via by setting the soldermask over the via to viapad- via drill size (basically the annular ring if the via) . this guarantees an open end. even if the strike is off centre. the via drill is always much larger than the annular ring. (NEVER make a 50 mil pad with a 6 mil drill in it.) the annular ring must be smaller than the drill. the max allowable aspect ratio is 50/50 so a 50 mil pad cannot have a drill smaller than 25 mil in it.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 15, 2015, 01:57:17 am
content: Now I'm double confused...What does aspect ratio (in terms of pad diameter / hole diameter) have to do with a via? If I make a via in the middle of a ground plane, with no thermals, is that not an essentially unlimited ratio?Trapped crud is always a bad idea, though. Flux, residue, moisture, whatever. Bad for soldering (trapped gas causing pockets in via-in-pad joints) and reliability (CAF and such).Tim

author: free_electron
author_rank: Super Contributor
timestamp: February 15, 2015, 04:00:54 am
content: Quote from: T3sl4co1l on February 15, 2015, 01:57:17 amOf course it doesn't matter on inner layers.It matters on the outer layers. damn , i can't remember what the issue was. It's got something to do with soldermask over such a structure and the type of soldermask used, could have been even coverlay. You can have any aspect ratio provided the via is left 'open' (not covered in mask).But if you cover it. ... darn it.. can't remember. i need to go look for it. it was an article in a magazine. There was a rule of thumb that said there should be less copper around the hole than the diameter of the hole. but only for some specific conditions. so the advice was to not do it as default rule to keep you out of trouble.damnit . it bugs me now that i can't remember the 'why'. i don't like doing things 'because we asay so'. i always want to know the why , and now i can't remember... grrr.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 15, 2015, 04:12:53 am
content: I meant for outer layers... should've been specific.Might've been something about stress/tearing failures? But as I recall, that's pretty much considered a solved issue, by manufacturing process. And that's according to some oldish IPC books. And applies more to connections to inner layers (e.g., omit unconnected rings on inner layers) than to anything on the surface.Tim