Creating a better delay/dead-time circuit - Page 1
Forum section: electronics / projects

author: seancsnm
author_rank: Regular Contributor
timestamp: March 01, 2020, 07:18:19 pm
content: So I'm working on a half-bridge N-channel FET drive circuit. I'm looking at using the LMG1205 gate driver (https://www.digikey.com/product-detail/en/texas-instruments/LMG1205YFXR/296-48589-1-ND/8567633) to drive some GaN FETs. However, this driver doesn't have built-in dead-time control between the turn-off and turn-on of the two FETs in the half-bridge. Being able to precisely control dead-time is rather important to optimize efficiency, signal distortion, and to avoid shoot-through between the FETs. So that leaves me a couple options - 1) ignore this issue, and hope it's "good enough" for my needs; 2) switch to a different gate driver that has built-in control; 3) build a dead-time control circuit.I decided to try to roll my own dead-time circuit and came up with the circuit shown in the attachment. It uses inverting logic gates along with an AND logic gate. The input, "Sig", is a PWM signal running at around 500 kHz. A first delay is created using an RC circuit that is used to create a delayed trigger on an inverter. This inverted, delayed signal is used as the inverting, low-side gate driver input after it gets delayed by another set of gates that provide a constant delay. The top branch of the circuit continues, creating another delay, gets inverted, and gets ANDed with the original drive signal to create the high-side gate drive circuit. With this circuit, the time constant of the left-most RC set creates a delay between the falling edge of YH and the rising edge of YL. Similarly, the right-most RC pair sets the delay between the YL falling edge and the YH rising edge.In theory, it works very nicely. In practice, I'm not so sure. These gates aren't designed as comparators and while the minimum turn-on voltage is specified, the maximum is not. I'm worried about the consistency of these devices during operation with temperature variation. The numbers just aren't specified. For now, I'm only doing prototyping so adding a few pots to set the time constant after assembly is no big deal. So my question is, are there suggestions for improving this circuit's performance over temperature, PSU variation, and other conditions that may affect it's performance? I think that if the delay times are able to be maintained within a few nanoseconds that would be adequate for what I'm doing. I have considered using comparators rather than gates, but the faster ones are quite a bit more expensive ($3-4 vs. $0.30-$0.40) so I'd like to avoid using them if possible. I'm gonna put together a portion of this circuit on the bench today and maybe it'll work very well, but in the mean time, feedback is very welcome!Edit 1: I guess TI has an evaluation module that includes a dead-time circuit that I missed before:http://www.ti.com/tool/LMG1205HBEVM?jktype=tools_softwareIt's quite a bit simpler and appears to achieve the same effect with diodes. The falling edge of each signal is delayed with an RC circuit while the rising edge is more or less the same due to the diode. I'll likely just go with this circuit for my design.

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 02, 2020, 04:35:33 pm
content: For a simple dead-time circuit I needed to drive a small class-D amplifier (a half bridge), I did the following (much simpler):I was relying on just a single resistor and the input capacitance of the gates to generate the "delayed" signal. Then OR and AND combinations give the two driving signals.Certainly the dead-time itself was not very accurate, but the input capacitance of the gates has actually less variability than a small external capacitor. It was good enough for my requirements.

author: seancsnm
author_rank: Regular Contributor
timestamp: March 03, 2020, 07:05:22 am
content: Interesting. I think this could also work if an additional resistor is added to allow individual adjustment of each edge. Removing the caps may also be a good idea... It certainly looks more elegant.

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 03, 2020, 02:38:48 pm
content: Whatever approach you end up with, you can reuse the idea that you can easily get your HI and LO signals with AND'ing and OR'ing the switching signal with a delayed version of it.Note that you should preferably use gates with schmitt trigger inputs for that, as delaying a logic signal with an "RC" filter will slow edges down and with non-schmitt trigger inputs, that will increase power consumption significantly (and may yield unwanted states while transitioning). The AUP series has schmitt trigger inputs on all gates AFAIR. Select your gates appropriately.

author: Evan.Cornell
author_rank: Regular Contributor
timestamp: March 03, 2020, 02:48:34 pm
content: Take a look at PE29102 from pSemi / Murata. Meant for GaN FET driving, but has resistor-settable dead time control.https://www.psemi.com/pdf/datasheets/pe29102ds.pdf.Not a super-great package for DIY stuff though.

author: David Hess
author_rank: Super Contributor
timestamp: March 03, 2020, 10:22:36 pm
content: One way to do dead time control is to use a pair of comparators to measure the output voltage of each driver and delay the other transistor until the current one has switched. This compensates for the relatively heavy capacitive load presented by the MOSFETs and automatically adjusts. If the MOSFET threshold voltage is slightly higher than CMOS logic, then this can take the form of a pair of cross coupled OR gates.Or use a pair of comparators after the digital outputs are driven through fixed RC delays and adjust the comparator threshold.Or use the cross-coupled OR gates mentioned above with RC delays on their outputs. This was common in the past with fixed frequency inverters.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 03, 2020, 11:18:23 pm
content: Don't worry about inputs and thresholds, the edge rates aren't ridiculously slow here. You will want to choose something accurate enough (both in input threshold (as if) and in consistent/repeatable propagation delay) that it doesn't need adjustment in the final assembly.Keep in mind that you can trade sloppy timing with some impedance in the bridge. Zero or even negative delay is tolerable when the bridge loop inductance is designed properly (and snubbed).Tim