Verilog Floating Point Clock Divider Release. - Page 1
Forum section: electronics / general

author: BrianHG
author_rank: Super Contributor
timestamp: August 09, 2022, 11:48:48 pm
content: **************************************************************************************************BHG_FP_clk_divider.v V1.3, Feb 02, 2025.v1.3 - Corrected the PPM calculation + added 1 bit to the M divider counter for the occasional requirement.(Thanks to 'dennowiggle' for catching the bugs)Get the latest version here:v1.3 source on github**************************************************************************************************BHG_FP_clk_divider.v V1.2, August 10, 2022.Floating point clock divider/synthesizer.24.16 (m.n) bit floating point clock divider. (Actually it is a fixed point fractional divider.)1.2a - Added a protection for when the integer divider has less than 2 bits.1.2b - Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters.1.1 - Fixed a bug with some Modelsim versions where its 'Compile/Compile Options/Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.1.0 - Initial release.Written by Brian Guralnick.https://github.com/BrianHGinc/Verilog-Floating-Point-Clock-DividerProvide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider will generate a clock at the specified CLK_OUT_HZ parameter. The module will output a 50:50 duty cycle clock plus two single clk_in cycle pulsed outputs, one at the rise of the clk_out, and another at the fall of clk_out.*** The module will generate a report of the synthesized output clock specs in your FPGA vendor compiler's message processing window during compile. The report will contain the resulting frequency down to the 0.01Hz, calculated PPM error and jitter spec.To simulate this project in Modelsim:1) Run Modelsim all by itself. You do not need your FPGA compiler studio.2) Select 'File / Change Directory' and choose this project's folder.3) In the transcript, type: 'do setup_fpd.do'. (DONE!)4) To re-compile and simulate again, type: 'do run_fpd.do'. (DONE!)For public use. Just be fair and give credit where it is due.**************************************************************************************************Example Modelsim screenshot of simulating a full second:(USE_FLOATING_DIVIDE=1,CLK_IN_HZ=100000000,CLK_OUT_HZ=3579545)(USE_FLOATING_DIVIDE=0,CLK_IN_HZ=100000000,CLK_OUT_HZ=3579545)Example Quartus screenshot of compilation report with LUT/LR:(USE_FLOATING_DIVIDE=1,CLK_IN_HZ=148500000,CLK_OUT_HZ=3072000 = Audio I2S sclk for 48Khz sound)(USE_FLOATING_DIVIDE=0,CLK_IN_HZ=148500000,CLK_OUT_HZ=3072000 = Audio I2S sclk for 48Khz sound)Looking at the 'Frequency error PPM' alone shows the value in this code.Remember, most consumer grade crystals are around +/-50ppm tolerant.If you require a single or multiple fractional clocks when you only have a single source clock, or want your FPGA compiler to only deal with one master clock domain using my clock divider's pulse outputs as 'enable logic', this code will fit the bill.

author: BrianHG
author_rank: Super Contributor
timestamp: August 10, 2022, 12:53:03 am
content: *** Note *** I just changed the '13.16 (m.n)' divider to '24.16 (m.n)'. Just re-download the source.IE: If you have a 450MHz clock, you can now divide down to below a 1 KHz clock. My code automatically trims unused bits for smaller divides, or divides with even fractions.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 10, 2022, 09:04:08 am
content: BrianHG Thanks for sharingI tried to simulate the design in modelsim and it complains about it,Quote

author: BrianHG
author_rank: Super Contributor
timestamp: August 10, 2022, 11:49:54 am
content: Quote from: ali_asadzadeh on August 10, 2022, 09:04:08 amThanks, there are 2 ways to fix this:1) In Modelsim, In menu 'Compile / Compile Options / Language Syntax':Switch from 'Use Verilog 2001' to 'Default'.2) In my source code 'BHG_FP_clk_divider_tb.v', move line 36 to line 28.Thank you for pointing this out. I will patch my Github with option #2 as it will allow Modelsim to work with both language syntax setting in Modelsim. However, 'Use Verilog 2001' also blocks SystemVerilog support.

author: BrianHG
author_rank: Super Contributor
timestamp: August 10, 2022, 12:12:37 pm
content: New version 1.1 released:* v1.1 Patches a simulation bug where Modelsim's 'Compile / Compile Options / Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.The 'BHG_FP_CLK_DIVIDER_v1.1.zip' is now attached to in opening thread.

author: BrianHG
author_rank: Super Contributor
timestamp: August 11, 2022, 02:09:38 am
content: v1.2 released. Revision history:1.2a - Added a protection for when the integer divider has less than 2 bits.1.2b - Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters.1.1 - Fixed a bug with some Modelsim versions where its 'Compile/Compile Options/Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.1.0 - Initial release.Example new 'inoperable parameters' error when compiling:Code:# Loading work.BHG_FP_clk_divider_tb# Loading work.BHG_FP_clk_divider## XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX# XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX# XXXXX XXXXX# XXXXX BHG_FP_clk_divider.v inoperable parameter error. XXXXX# XXXXX https://github.com/BrianHGinc XXXXX# XXXXX XXXXX# XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX# XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX# XXXXX XXXXX# XXXXX BHG_FP_clk_divider.v can only generate an output clock at least 1/2 the source clock frequency. XXXXX# XXXXX XXXXX# XXXXX Your current set parameters: XXXXX# XXXXX XXXXX# XXXXX .INPUT_CLK_HZ = 100000000 Hz. XXXXX# XXXXX .OUTPUT_CLK_HZ = 50000001 Hz. XXXXX# XXXXX XXXXX# XXXXX .OUTPUT_CLK_HZ must be less than or equal to .INPUT_CLK_HZ/2 for BHG_FP_clk_divider.v to function. XXXXX# XXXXX XXXXX# XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX# ** Warning: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX# Time: 0 ps Scope: BHG_FP_clk_divider_tb.FPD.genblk1 File: BHG_FP_clk_divider.v Line: 70# ** Error: Assertion error.# Time: 0 ps Scope: BHG_FP_clk_divider_tb.FPD.genblk1 File: BHG_FP_clk_divider.v Line: 71# ** Note: $stop : BHG_FP_clk_divider.v(72)# Time: 0 ps Iteration: 0 Region: /BHG_FP_clk_divider_tb/FPD/genblk1# Break in VlGenerateBlock genblk1 at BHG_FP_clk_divider.v line 72Download new source 'BHG_FP_CLK_DIVIDER_v1.2.zip' in the opening post of this thread.

author: BrianHG
author_rank: Super Contributor
timestamp: February 02, 2025, 11:10:51 pm
content: BHG_FP_clk_divider.v V1.3, Feb 02, 2025.v1.3 - Corrected the PPM calculation + added 1 bit to the M divider counter for the occasional requirement.(Thanks to 'dennowiggle' for catching the bugs)Get the latest version here:v1.3 source on github