Another Newb Question Regarding Logic Gate, Unused Out/In - Page 1
Forum section: electronics / beginners

author: Falcon69
author_rank: Super Contributor
timestamp: March 22, 2016, 05:09:38 pm
content: So, I looked up the parts.a 4 gate chip is actually cheaper then a 2 gate chip, in QFN. And the QFN is smaller then the TSSOP8 package.So, my question is, Can I use the QFN, and not even connect the inputs/outputs of two of the gates? Or must they all the inputs be tied to ground and output tied to ground via resistor?These are 74HC CMOS chips.Thanks in advance

author: Ian.M
author_rank: Super Contributor
timestamp: March 22, 2016, 05:12:57 pm
content: Unused inputs must be tied to a valid logic level and outputs left unconnected.

author: Falcon69
author_rank: Super Contributor
timestamp: March 22, 2016, 05:24:06 pm
content: okay, if I tie inputs to GND, do I need a resistor on them?

author: SeanB
author_rank: Super Contributor
timestamp: March 22, 2016, 06:06:20 pm
content: Preferably, any resistor from 1k to 100k will do, not too critical. Just there in case of ESD so there is no gate current flow through internal diodes, and also if the ground pin is not connected. If you use a resistor per input then you have an option to add a single pad on each output, so that you can have a pair of inverters if you need to have an extra inverter or buffer.

author: Falcon69
author_rank: Super Contributor
timestamp: March 22, 2016, 06:10:50 pm
content: ? Hmm, not schmitt trigger though?That's a Thought, I have several inverters on the circuit. I could eliminate some by doing that.

author: Falcon69
author_rank: Super Contributor
timestamp: March 22, 2016, 06:13:55 pm
content: Since there is no switch going to the inverter (then to one of the gate inputs), just a jumper that is configured before the circuit is powered, would I even need a schmitt triggered for debounce?If Not, then this AND GATE schematic, how would I do as you say, to make it into an inverter?Since I only need two gates of the 4 gates in the chip, there's two of these circuits available.

author: Ian.M
author_rank: Super Contributor
timestamp: March 22, 2016, 06:14:28 pm
content: CMOS logic inputs can be tied direct to either supply rail. Old-skool real bipolar TTL needed a pullup resistor to limit the current as direct connection to Vcc could cause catastrophic failure due to input transistor E-B junction Zener breakdown if any spikes on Vcc exceeded 5.5V.However its strongly recommended at least when prototyping to make hard ties to Vdd or Vss individually cuttable with an Xacto knife so if you find you've goofed and need to patch in an extra gate, you can use the spares, which would be impossible if they are tied directly to a ground under the chip.

author: MK14
author_rank: Super Contributor
timestamp: March 22, 2016, 06:44:55 pm
content: Quote from: Falcon69 on March 22, 2016, 06:13:55 pmAn "AND" or "OR" gate, CAN'T be made (easily, ignoring semi-crazy tricks) into an inverter.You would need to use "inverted" gate logic.Such as a NAND, NOR, exclusive OR gate, EXCLUSIVE NOR gate.

author: Falcon69
author_rank: Super Contributor
timestamp: March 22, 2016, 06:49:45 pm
content: cool, I will try and work with that. Looks like with my current circuit, a NAND gate is a no go, however, a NOR Gate looks idea.