UWB Receiver Noise flour - Page 1
Forum section: electronics / rf-microwave

author: Georgi
author_rank: Contributor
timestamp: April 09, 2016, 08:28:01 am
content: Had a discussion with a colleague of mine about how to calculate the noise floor at the UWB Receiver, and decided to post the question here, since I am not exactly sure how the sensitivity of the UWB receiver can be calculated.Suppose we have a UWB signal at center frequency 6.5 GHz with a bandwidth of 900MHz. As far as I know if we have a modulation scheme, at which the signal does not go under the noise we can calculate the noise floor at the receiver roughly like this : -174 dBm/hz + 10*log(900Mhz) which gives us a noise floor of around -84 dBm. I don't think that is the correct way to calculate the noise floor when it comes to DSSS Modulation scheme (which is used in UWB) though, because at the UWB systems the signal is brought deliberately under the noise floor at the transmitter and then extracted at the receiver by correlating the signal with a pulse sequence (known both from transmitter and receiver).Am I right here, or am I missing something and my assumption is not correct ?I have done some channel measurements with a UWB-system and seen that the SNR was always negative (which is to be expected since the signal goes under the noise floor). And I measured signal levels of about -100 dbm. The communication between receiver and transmitter was still functioning, although there was some CRC-Erros and some frames were damaged, but not much. The data sheet of the chip, that I am using (Chip- DW 1000 by Decawave) also says that at -100dbm the communication between receiver and transmitter should be possible, though with some higher error probability. Since the measurements are done with the Decawave software which calculates the SNR and RSL parameters from the frame preambles, I was not so sure if I can trust these measurements.Anyway this post turned out way longer than I intended it to be, so I will stop hereGeorgi

author: chris_leyson
author_rank: Super Contributor
timestamp: April 09, 2016, 11:20:06 am
content: Hi Georgi, I think your assumption is correct, you are getting some processing gain from the DSSS demodulator. If for example the chip rate is 100 times the bit rate, then by definition, the processing gain equals chip rate/bit rate, equals 10log(100)dB or 20dB. The received psuedo noise, PN, sequence correlates in the receiver to give data bits whereas AWGN doesn't correlate. Perhaps, and I'm thinking aloud, the receiver bandwith, or I should say receiver equivalent noise bandwith is determined more by the correlator rather than the front end RF bandwidth. Also, if the DSSS modulator is BPSK then you would get 3dB gain because both sidebands are identical and the AWGN isn't. I know I have over simplified things, processing gain is only part of the equation.

author: Georgi
author_rank: Contributor
timestamp: April 09, 2016, 12:00:15 pm
content: Hi Chris,thanks for the response, i completely forgot about the process gain at the DSSS demodulator, (and I read about it in a book just a few weeks ago). This chip has BPSK modulation scheme, so the 3 db Gain is also there.Georgi