Decoupling capacitors and perceived wisdom - Page 1
Forum section: electronics / general

author: Howardlong
author_rank: Super Contributor
timestamp: August 31, 2025, 06:15:34 am
content: This video questions the legitimacy and perceived wisdom of using parallel decoupling caps of order-of-magnitude different values to deal with their intrinsic resonances turned up on my feed a couple of days ago.The TL;DR is to forget using, say, a 1nF plus 100nF, and just use two 100nF (with several caveats, of course).Of course, it's horses for courses, but my takeaway was... even more engineering work!Meanwhile, I'll continue to use, as a starting point, the datasheet recommendations and vendor reference designs.It reminded me of the perceived wisdom 15 years or so ago of using split ground planes to separate analogue and digital grounds in mixed signal designs, covered here

author: iMo
author_rank: Super Contributor
timestamp: August 31, 2025, 07:08:37 am
content: Afaik ADI, for example, since ever recommended 3 capacitors with 2 orders of magnitude apart (like 1n, 100n, 10u)..PS: Btw., I have never ever heard about the wisdom on using parallel decoupling caps of "order-of-magnitude different values"..Quote

author: ConKbot
author_rank: Super Contributor
timestamp: August 31, 2025, 08:28:30 am
content: Working with SMT caps it's pretty cut and dry, your package size and layout sets parasitic introduce, so what does a 10n or 1n 0201 get me that a 100n 0201 doesn't? On the far side of the resonance they all converge on the same upwards impedance slope. So unless you're putting the resonance right on a specific frequency to eat it, the high frequency performance is similar.

author: tom66
author_rank: Super Contributor
timestamp: August 31, 2025, 08:42:36 am
content: There are some small changes in impedance for 100nF vs 1uF 0402 ceramic capacitor. This is because the 1uF capacitor is constructed differently. But in general I do not see much need for going with, say, 10nF in the same package. Best to stick with nearly or actually the largest capacitor value you can get in the package and then maybe a 100n-470nF in parallel in case that one has too high ESL. If you look at the charts from cap manufacturers like Murata there is a small difference in high frequency impedance between caps of different value in the same package, although usually it is quite subtle. Even better might be going 0402 1uF plus 0201 100nF, but not everyone wants to use 0201.

author: Howardlong
author_rank: Super Contributor
timestamp: August 31, 2025, 09:12:00 am
content: Quote from: iMo on August 31, 2025, 07:08:37 amOK, then "orders-of-magnitude". Happy now?I think you're missing the point, the video is suggestingNOTdoing that.

author: Howardlong
author_rank: Super Contributor
timestamp: August 31, 2025, 09:17:56 am
content: Quote from: ConKbot on August 31, 2025, 08:28:30 amYes, so the point is that blindly using, for example, a 1nF || 100nF for decoupling was probably often just a rule-of-thumb box ticking exercise.That won't stop me using the vendor-recommended suggestions as a starting point, though.

author: nctnico
author_rank: Super Contributor
timestamp: August 31, 2025, 09:22:04 am
content: Quote from: Howardlong on August 31, 2025, 09:12:00 amThe measurement method in his video is wrong because it doesn't represent a real PCB layout with all it's additional parasitics and package interconnects. Look for PDN impedance matching. The last time this topic came up I dug a little bit deeper and came across a much better explaination as to why using different valuesISbetter in the end. Many people look at the real impedance only. But what about the imaginary axis? What happens at a reasonance peak in terms of phase shifts? Especially when the resonance frequency is concentrated at one frequency. You are basically dealing with HF here. For best RF performance, you want to keep the PDN impedance flat and hence you'll (very likely) need multiple different values in a real world design. Chip manufacturers know this and that is why you'll see that all of them provide lists with values to use for decoupling capacitors for high speed digital parts so designers without simulation software at least have a decent chance of getting the PDN impedance right.This article shows the basics of having a flat PDN impedance:https://www.signalintegrityjournal.com/articles/1715-optimizing-power-distribution-networks-for-flat-impedanceHowever, I think it will be extremely hard to apply this concept to a more complex circuit where a single supply rail powers many chips each with their own distribution network and internal decoupling.

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: August 31, 2025, 09:34:05 am
content: http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdfOMG. I wrote that in 2007.Where is my bottle of Gerontol-forte??Gerhard

author: NE666
author_rank: Frequent Contributor
timestamp: August 31, 2025, 10:12:58 am
content: I'm not qualified to wade in on the actual video and question at hand however, I did have this YT contributor's "A Critical Resistor Pitfall" video amongst my suggestions only a week or so ago, and it was clear even to me that his presented theory of ohmic heating causing the noise he was seeing wasn't going to stand up to scrutiny.

author: wraper
author_rank: Unknown
timestamp: August 31, 2025, 10:19:41 am
content: Different capacitances are only worth it if they are of different dimensions. Otherwise there is virtually no benefit from using smaller capacitance as they have roughly the same inductance for particular package size regardless of capacitance.

author: Howardlong
author_rank: Super Contributor
timestamp: August 31, 2025, 10:23:57 am
content: Quote from: Gerhard_dk4xp on August 31, 2025, 09:34:05 amYou were ahead of your time ;-)How much was a 100 uF 6.3V ceramic multilayer 1208 in 2007 I wonder? Bleeding edge stuff!Tantalums seem to have gone the way of the dodo since then, presumably down to a combination of MTBF, failure mode, cost, and ecological impact.

author: tom66
author_rank: Super Contributor
timestamp: August 31, 2025, 10:44:00 am
content: Quote from: Howardlong on August 31, 2025, 10:23:57 amIt's funny looking at boards made, say, just 15 years ago and seeing them littered with tantalum and electrolytic capacitors now, and looking at boards made today and seeing just MLCC. There are a few factors that made it possible. One was ceramic capacitors getting better (higher energy density, lower cost), sure, but another was that you just needlesscapacitance now, with faster switch mode power supply controllers for instance, with fast switching rates meaning that less energy is stored per cycle and faster control loops meaning they can respond more quickly to a load or input change. Tantalums were really compromised in multiple ways, having reliability issues at high temperature and voltage, a propensity to combust if abused, and limited temperature range unless you paid for premium devices. MLCC has its own issues, DC bias being a particular pain for some larger caps, but they are a lot better than tantalums for 99% of applications.

author: Howardlong
author_rank: Super Contributor
timestamp: August 31, 2025, 11:37:53 am
content: Quote from: tom66 on August 31, 2025, 10:44:00 amAdd aging to the list for class II and III MLCCs too.

author: David Hess
author_rank: Super Contributor
timestamp: August 31, 2025, 01:51:28 pm
content: Many years ago I had a wideband, 144 MHz to 1.2 GHz, power coupling capacitor application with 12 x 1206 size SMD capacitors in parallel in a transmission line environment, so there was zero lead length. (1) 12 x 0.1 microfarad capacitors failed with excessive loss at high frequencies, while 4 x 0.1, 4 x 0.01, and 4 x 0.001 worked.I do not know how to reconcile this with the advice about not staggering the capacitance values. It seem like having a 50 ohm impedance would be a better situation for parallel capacitors of the same value than the much lower impedance of a PDN.(1) Axial leaded parts could have been used since the leads would form the transmission line, but surface mount parts were actually easier for assembly.

author: Howardlong
author_rank: Super Contributor
timestamp: August 31, 2025, 04:40:11 pm
content: Quote from: David Hess on August 31, 2025, 01:51:28 pmThat was my first thought regarding the video's practical demonstrations: there was an assumption made that the power rails are 50 ohm terminated, when in fact it's far more complex than that, including non-linearities and complex impedances. I'm not discounting everything he's saying, far from it: I found it interesting, but more as a food-for-thought than encouraging me to fundamentally re-think my strategy of seeing what the data sheets suggest, and how the vendors' reference designs do it as starting points.

author: PlainName
author_rank: Super Contributor
timestamp: August 31, 2025, 05:07:43 pm
content: Quote from: wraper on August 31, 2025, 10:19:41 amThe chart shows the different capacitances give lowest impedance at different frequencies. Isn't that what you want?Edit: I misunderstood the thrust of the charts, but am now enlightened.

author: Nominal Animal
author_rank: Super Contributor
timestamp: August 31, 2025, 05:32:59 pm
content: What I'd like to know, is whether I should try to minimize supply pin to capacitor distance, or say the loop length/area from supply pin to capacitor to ground pin, and why.Simple theory says that supply pin to capacitor distance, because the ground end of the capacitor only needs the ground potential reference to work, with theoretically no current at all. But what say other practical considerations?The above diagrams showing how package size affects the minimum impedance point is just such a practical consideration. Similarly, when one uses two or more capacitors of different sizes, constructions, or dielectrics, their interaction (and nonzero ESR and ESL) often creates a new impedance maximum at high frequencies (above where the two minima would be separately). In the case of current microcontrollers running at tens or hundreds of MHz, that new maximum can hit the internal switching rate (clock frequency), making the pair less effective than the bigger capacitance one would be alone. Many of you know these effects much better than I do; I only know it can happen. But it does show that one should never trust theory blindly, always check.

author: DimitriP
author_rank: Super Contributor
timestamp: August 31, 2025, 06:29:26 pm
content: Quote from: Howardlong on August 31, 2025, 04:40:11 pmTo paraphrase ...."it's 50 ohms somewhere"

author: Someone
author_rank: Super Contributor
timestamp: August 31, 2025, 11:49:56 pm
content: Quote from: David Hess on August 31, 2025, 01:51:28 pmYou have the explanation right in the post, DF vs frequency. Were the 1n parts the same material (and voltage rating) as the 100n?

author: David Hess
author_rank: Super Contributor
timestamp: September 01, 2025, 12:41:06 am
content: Quote from: Someone on August 31, 2025, 11:49:56 pmThis was a power application, up to 50 watts, so I started with a design which was a best effort short of using RF rated capacitors within the mechanical considerations. The capacitors were all common C0G parts of the same voltage rating, probably 100 volts, and the same series and package size.I started with 12 x 0.1 microfarads because it did seem like the low inductance, especially with transmission line construction, would work fine at the highest frequencies. It did not and there was a unacceptable SWR mismatch. Dividing the capacitors between 0.1, 0.01, and 0.001 microfarads lowered losses to below 0.5 dB. If that had not worked, then I would have used surface mount RF capacitors.

author: iMo
author_rank: Super Contributor
timestamp: September 01, 2025, 05:38:32 am
content: We want this, afaik. Also the slopes in the picture differ from the ideal situation, capacitors have self resonance peaks there, etc. But still the recommendation to have 3 caps 2 decades apart (starting with the lowest capacitance closest to the device you decouple) when dealing with fast or RF circuits is worth the effort, imho.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 01, 2025, 06:21:23 am
content: Quote from: iMo on September 01, 2025, 05:38:32 amBut that is what you don't get when paralleling actual capacitors of different values. It looks like that if you look at their curves in isolation and overlap them mentally, but that's only because they havedifferent absolute Y axis. What you actually get it as shown by wraper.

author: Someone
author_rank: Super Contributor
timestamp: September 01, 2025, 07:40:31 am
content: Quote from: David Hess on September 01, 2025, 12:41:06 amI just pulled up some example series of 1206 C0G parts across that range. The parasitic inductances (package dominated) were all consistent with minimal resonance, but as predicted the DF is found to be lower for the smaller parts. So quite a different mechanism than the people chasing lowest |Z| by using diversity in parallel.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 01, 2025, 08:32:16 am
content: Also see:https://www.eevblog.com/forum/projects/good-practice-for-mlcc-power-by-pass-capacitor/msg5588349/#msg5588349https://www.eevblog.com/forum/beginners/trouble-finding-100uf-ceramic-capacitors-do-they-exist/msg5582751/#msg5582751

author: tggzzz
author_rank: Super Contributor
timestamp: September 01, 2025, 08:59:58 am
content: Quote from: wraper on August 31, 2025, 10:19:41 amHence 0306 capacitors as well as 0603: shorter and wider both reduce inductance.Fromhttps://datasheets.kyocera-avx.com/LICC.pdf

author: Siwastaja
author_rank: Super Contributor
timestamp: September 01, 2025, 09:16:24 am
content: Quote from: tggzzz on September 01, 2025, 08:59:58 amYeah. Remember though that manufacturers (obviously) measure them in isolation: to minimize any stray L on the measurement. When used in a real layout, the difference becomes smaller, somewhat underwhelming. Traditional packages like 0201, 0402 and 0603 remain immensely popular because they work well enough, and eventually it does not matter whether you pass EMC with 6.8dB or 6.9dB of margin.

author: tggzzz
author_rank: Super Contributor
timestamp: September 01, 2025, 09:35:54 am
content: Quote from: Siwastaja on September 01, 2025, 09:16:24 amAgreed, and the reference indicates the package isn't the whole story.Rules of thumb should be treated as that and no more. Learn why something works in some conditions, plus the limits of the conditions. If those conditions apply to you then try following the rule of thumb and measure the results.

author: w42i
author_rank: Contributor
timestamp: September 01, 2025, 11:31:27 am
content: Some interesting discussion of this topic can be found in  (in German, don't know if an English edition exists). When capacitors with different capacitances and SRF are paralleled, you also get parallel resonances between them which can cause increased impedance due to peaking at high frequencies like already discussed in this thread.When two caps of the same type (actually, the requirement is L1*C1=L2*C2, where L1, and L2 are the caps' inductances) are paralleled, a zero of the impedance cancels the pole so the parallel-resonance problem does not exist. The calculation for 2 paralleled caps is not too complicated to carry out and prove this. In practice, even two caps of the same type are not exactly the same. However, I didn't perform a sensitivity analysis.Now, you could add a controlled resistance to make the ESR a little higher, which often is not a problem and thereby reduce the parallel resonance peak, but this requires quite some design effort.A consequence of this analysis and the fact that the ESL is mostly defined by the package size and PCB connections is to just use the highest capacitance in an appropriate package size (this depends on the application and assembly capabilities). For higher capacitances, just parallel more of the same type. According to  bulk electrolytics parallel to MLCCs are usually not a problem due to the much lower Q.Of course, this does not take problems with self heating as discussed above in the thread and maybe other constraints into account.Having said that, I have yet to encounter a circuit where the parallel resonance of caps has prevented it from working, but is still a good to have it on the radar and knowing what you're doing is usually a good approach.: EMV: Störungssicherer Aufbau elektronischer Schaltungen, Joachim Franz, Springer, 2013, ISBN 978-3-8348-1781-5

author: David Hess
author_rank: Super Contributor
timestamp: September 01, 2025, 06:46:31 pm
content: Quote from: Someone on September 01, 2025, 07:40:31 amDo you mean smaller parts as in lower capacitance? I used all 1206 parts to make assembly easier. RF chip capacitors would have been an order of magnitude more expensive.Increasing dissipation with higher frequency explains it, but ultimately does it matter whether separate parallel values are used to make up for significant ESL or increasing dissipation?When I did this, I did not find performance curves versus frequency for common surface mount capacitors, despite deliberately searching for them. Looking now I still do not see them in the individual datasheets.

author: TimFox
author_rank: Super Contributor
timestamp: September 01, 2025, 07:15:54 pm
content: Quote from: w42i on September 01, 2025, 11:31:27 amAn example from my experience with unwanted effects of parallel resonance in capacitors.Maybe 30 years ago at work, we breadboarded a circuit using a common-source JFET driving a transimpedance stage (low input impedance) for use at 64 MHz. There were several JFETs with one RF choke feeding the drains, capacitively coupled into the next stage, a transimpedance amp designed for fast photodiodes.Each JFET had a biasing resistor in its source and a 1 Megohm gate resistor. The circuit selected one or two FETs into the next stage by switching the other end of the source resistor to -15 V. Each FET source was bypassed to ground through two (oops) parallel capacitors. I think there was a small source-degeneration resistor to stabilize the gain.Anyway, in one iteration of the breadboard (2 layer PCB, through-hole parts), we had more output signal at 64 MHz with the source current off than the too-low output with the source current enabled. It turned out that the two caps together parallel-resonated at 64 MHz (smaller cap with inductance of the larger cap at that frequency).A simple fix replaced the two caps with a carefully chosen single cap.

author: Someone
author_rank: Super Contributor
timestamp: September 02, 2025, 12:15:45 am
content: Quote from: David Hess on September 01, 2025, 06:46:31 pmYes, I looked up your specific example of 1206 C0G, 100n 10n 1n and found |Z| vs freq and DF vs frequency (extended data outside the datasheets, go to the manufacturers and hunt through their data libraries).It does matter why the result was different, when people are arguing here that the reduced |Z| is what is needed. But your application was needing DF, while the |Z| would have been almost identical between the all 100n and 100n 10n 1n split. The data Ive seen suggests you would have had lower loss with 100n and something like 4n7, and the 1n were probably doing little.

author: hans
author_rank: Super Contributor
timestamp: September 02, 2025, 07:22:51 am
content: With respect to "this is not a real PDN analysis":See 18:41 (powered vs unpowered network)The control loop of a voltage regulator will keep the impedance low at its control loop frequency. Anything higher is filled in with ceramics. A unpowered VNA measurement is a valid choice for the frequency band of interest. As Gerhard_dk4xp showed in his document, Alu capacitors basically don't do 'anything' when it comes to HF decoupling.The resonances and anti-resonances of several capacitor values can create frequency bands of high PDN impedance. I stopped following this advice many many years ago.Why do we still use 100nF at all? Its a nice round value, but its also a value that was applied as a rule of thumb from dozens of years ago. As Hans Rosenberg showed, a larger or smaller capacitor in the same package does not have a substantial different ESL. Why don't we simply pick the largest value capacitor available in a certain package size, granted the dielectric, voltage rating, cost etc. are compatible? E.g. a 100nF capacitor will cost <1ct, a 1uF capacitor may cost ~1ct, while the PNP machine of my board house costs 3ct. A 3.5ct vs 4ct capacitor is no substantial difference in cost.Iirc, this is also discussed in this video:(Skip to conclusion around 54:20 if this video is otherwise too long)Basically, there are many 'rules of thumb' in EE that have little ground in modern electronics. 40 years ago, 100nF capacitors were the best you can get, while nowadays there is little reason to choose them.I'm really interested to see video material on split ground planes for this reason as well. I have no data to back it up, but I would like toseewhat difference it makes when the same design and rest of layout is made with/without a split ground plane. Is this also a matter of outdated knowledge or not? Unfortunately, this would require A/B testing to test convincingly. Simply stating "do this" could be reasoned for every hypothesis, fairy tale or not. Unfortunately I don't see someone doing a full A/B test on a custom PCB design anytime soon.

author: Marco
author_rank: Super Contributor
timestamp: September 02, 2025, 10:25:45 am
content: Quote from: hans on September 02, 2025, 07:22:51 amWhat if they construct them with connections to the foil at the full width of the pad? Wouldn't that bring them down the footprint determined impedance? Or do the electrolyte kinetics have an inductive effect?

author: tggzzz
author_rank: Super Contributor
timestamp: September 02, 2025, 10:54:12 am
content: Quote from: Marco on September 02, 2025, 10:25:45 am0306 vs 0603?

author: Siwastaja
author_rank: Super Contributor
timestamp: September 02, 2025, 11:13:28 am
content: Quote from: Marco on September 02, 2025, 10:25:45 amNo. Electrolytics have of course more ESR than MLCC's due to said kinetics - which also shifts the whole impedance curve up - but otherwise than that, small electrolytes totally do contribute to HF (whatever is meant by that). Of course a 1uF in 0402 placed right next to power pin completely swamps it at, say, 100MHz, or 200MHz. But if you compare a small, e.g. d=5mm electrolytic vs. a poorly placed 1206 MLCC, they are again roughly similar in ESL. But the ESR alone for such small alu elcap is significant. And if you use larger alu elcap with less ESR, then it will have more ESL, at very least from non-optimal placement.I ran lab exercises at uni where students soldered discrete buck and boost converter, gate driven from a function generator. During developing of that exercise, I experimented with added parallel MLCC, but did not see any practical difference on oscilloscope screen - even when edge rates were in range of reciprocal of 30-70MHz, obviously way beyond the SRF of the single large electrolytic (some 25V 1000µF) we ended up using for simplicity of soldering. Obviously, these designs would not pass EMC, and say, at 500MHz I'm sure the electrolytic does absolutely nothing, but I'm saying all this because the SRF is a very misinterpreted parameter usually. It does not mean any kind of sudden stop of a capacitor acting as a capacitor.

author: tszaboo
author_rank: Super Contributor
timestamp: September 02, 2025, 11:37:05 am
content: Quote from: wraper on August 31, 2025, 10:19:41 amThis is very true, and mostly spot on. And I agree with you.I say mostly, because there is sometimes reason to get different values in the same package.Let's take a look at actual curves:So at the resonant frequency, the ESR is 2-5 times lower than the theoretical curves you posted. If you have a system that works at a certain frequency, or it needs to "shunt out" a certain frequency, like a harmonics, than you might need to use specific value bypassing.Think of a GSM modem, that works at 900 MHz. You want to have a low PDN impedance at this frequency because it's going to radiate, and not in a good way. So you place a capacitor, like 47pF, or 39pF on the power supply ,that will have it's self resonance right about there. 900MHz is going to be lower, but 800MHz for example higher, and it doesn't matter, noise is not generated there. Follow the application notes and the manufacturer's recommendation. And ignore open source sources, where the testing criteria was that "it works".

author: Siwastaja
author_rank: Super Contributor
timestamp: September 02, 2025, 12:08:43 pm
content: Quote from: tszaboo on September 02, 2025, 11:37:05 amJust remember that capacitance tolerance - and even layout tolerance to some extent - affects where this SRF dip lands. So going for the dip is, I would say, a sophisticated hack, not the generic design principle.And then it's definitely not 1nF, 10nF, 100nF in parallel, but a single specific special value - C0G type with tight tolerance specified - which was evaluated by prototyping (so it'sunlikelythe correct value would be exactly 1nF, for example; could be like 680pF).So always do careful tolerance analysis and leave extra margin when "going for the dip".

author: hans
author_rank: Super Contributor
timestamp: September 02, 2025, 04:12:19 pm
content: It all depends on the requirements. Analog and digital are not the same. RF is its own challenge.Digital is quite resilient to noise (it can't possibly be so poisonous to what it creates itself). For analog one can often rely on PSRR given the relatively low frequency, but not always.RF often has circuits with relatively low PSRR. Perhaps there are also RF chokes, baluns, etc. that want to see a resistive impedance looking into the PDN at its frequency of operation. This may be a reason to choose a capacitor in combination with current loop design in layout that operates at the SRF.The SRF is just a property of the capacitor, the layout will influence it as well. But for digital and probably most analog circuits, a |Z| that is sufficiently low prevents large voltage ripples for the current peaks that circuit will draw.

author: David Hess
author_rank: Super Contributor
timestamp: September 02, 2025, 04:37:45 pm
content: Many years ago I saw a through-hole switching power supply design that a security company made where I was told that the decoupling capacitor values were selected to notch the harmonics. I recognized the capacitors as the 5% stacked polyester film capacitors that Panasonic made because I used them also. Back then they were less expensive than C0G ceramic parts.

author: tom66
author_rank: Super Contributor
timestamp: September 02, 2025, 04:39:55 pm
content: One subtle issue with choosing the wrong capacitor for a decoupling solution is excessive bit error rate on high speed interfaces. For instance DDR3 memory sets the Vth based on Vdd/2 typically, and this reference is derived by a low noise circuit (commonly a voltage divider with a cap to ground, sometimes a dedicated reference). If your drivers on your SoC device are sagging under load due to inadequate capacitance then they may not provide acceptably wide eye around this Vth. That is one example of significant variation in a digital circuit -- digital becomes a bit analog, especially when long-ish transmission lines off-chip are involved.

author: nctnico
author_rank: Super Contributor
timestamp: September 02, 2025, 05:27:20 pm
content: Quote from: hans on September 02, 2025, 04:12:19 pmI disagree. Analog, digital and RF are all the same. Especially in modern designs with memory running at 1.6GHz, several Gbit/s USB / PCIe, 10Gbit/s ethernet, etc. That is pure RF design! And power supply decoupling is in the same boat. And keeping |Z| sufficiently low isn't a guarantee the power supply system is working correctly.This is an interesting article on how a power supply system can start to oscillate:https://www.signalintegrityjournal.com/articles/788-target-impedance-limitations-and-rogue-wave-assessments-on-pdn-performanceThe author calles this effect rogue waves.In the author's view (there are many more articles he wrote about power distribution) low |Z| is not the only parameter, the other important one is keeping Q low. The latter is probably also why staggered values end up being used. With the same value piled up, you'll likely get a high Q peak at some frequency while with staggered values the peak may not exist or there may be multiple, lower Q peaks. Keep in mind that the entire power supply system from the voltage regulator (with large MLCC bulk capacitors) up to the capacitors on the chip's die have an influence on the PDN behaviour. So optimising PDN behaviour requires a hollistic approach instead of looking at individual parts.At the moment I'm looking at an FPGA for a high speed design. In the hardware design manual, the manufacturer is very specific about the decoupling capacitors to use:This is not by chance or rule-of-thumb. These values have been obtained by analysis of the chip, package and circuit board layout. So if you adhere to the design guidelines and power supply routing examples, you'll very likely end up with a design which is pretty close to optimal given the design constraints.Another way of looking at a PDN is a bunch of cascaded low-pass elliptic LC filters. With LC filters it is important to drive & load these with their specific impedance. If not, your filter response will be completely off.

author: tggzzz
author_rank: Super Contributor
timestamp: September 02, 2025, 05:41:58 pm
content: Quote from: tom66 on September 02, 2025, 04:39:55 pmThe signals are analogue waveforms up to the point at which they are interpreted as a digital signal.Anything that disturbs the analogue waveforms (e.g. noise, crosstalk, reflections) or quantiser (e.g. ground bounce, threshold voltage, power supply variations) can cause the analogue signal to be incorrectly quantised into a digital signal.RF or not? Hells teeth, desktop computers have been doingarithmetic computationsin the FM band since the late 80s!As others have pointed out, it is mandatory to RTFDS and RTFAN, and often to simply copy them.

author: tszaboo
author_rank: Super Contributor
timestamp: September 02, 2025, 10:24:52 pm
content: Quote from: nctnico on September 02, 2025, 05:27:20 pmBut then, you can pace a 100 Ohm resistor on the power supply of an opamp, and it's going to happily work without any issue, maybe it even has lower output noise. And for other analog, you might need to split the ground, otherwise your 50A trace will cause all kinds of issues all across your board. And for RF, 5% reflection from a part could be absolutely terrible, while nobody cares for the same reflections in a DDR memory interface. "It's just some ringing". It's never this simple, the design requirements are not the same.Quote from: nctnico on September 02, 2025, 05:27:20 pmI would say it's never the goal. Nobody really cares about the PDN. What you care about is eg. passing EMC, fulfilling design requirements, or having the right error rate on a communication interfaces.

author: hans
author_rank: Super Contributor
timestamp: September 02, 2025, 11:02:31 pm
content: Quote from: nctnico on September 02, 2025, 05:27:20 pmFPGAs are one of the most well documented parts for this purpose, because designing with these parts depends a lot on the chip floorplan and switching activity. Some customers will need to be able to verify their own custom design.If you want to get any accurate power figures of a modern FPGA, you basically need to have your core design finished, with switching activity stimulus supplied, and only with this information a proprietary tool will spit out the most accurate figures of power supply requirements. Indeed, there is no rule of thumb, but there is also no omniscient appnote that will do this work for you.The datasheet for this PolarFire FPGA specifically says:QuoteOr in other words: exceed these specs, verify substitutions. The 2nd table from your list is described as "Recommended Decoupling Capacitors For PolarFire Devices". There are still some values missing, which means that all designs require some amount of substitution or eyeballing, still.But, at least they provide a good starting point that educates the designer how to find out more.Other chips may not be so well off. There are also plenty of appnotes out there for MCUs, MPUs, etc. that use the "100nF on every VDD" whilst supplying no information about the on-chip decoupling measures, the ripple specifications, layout, etc. Yet still the processor is switching at the best part of a GHz and comes in a LQFP-64 package I could even shove into a breadboard when I solder it to an universal breakout board (bad idea).Or as an example: I looked up the reference board design for a SX1272 Lora transceiver. And indeed as @tszaboo says: they have a 100nF+47pF capacitor on the PA rail. However, to my surprise, the reference board shows 100nF close to the IC pins and 47pF near the balun (whilst they are still placed next to each other).The datasheet just says: "do what is suggested in the reference design". I find this incredibly frustrating to gain more understanding.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 02, 2025, 11:45:51 pm
content: Quote from: hans on September 02, 2025, 11:02:31 pmThis is the exact trap I might fall in: 4.7µF X7R in 0805 plus 100nF X7R in 0603 on the 3.3V or 5V VCC of a MCU that has significant ripple from switching at 480 MHz (high-speed USB 2.0). My gut feeling says the resonance peak in impedance due to the properties of the pair is suspiciously close to that 480 MHz, but don't have the software or hardware tools to check. I might very well do much better with just a 1µF X7R in 0603 really close to the VCC pin, and ignore datasheet suggestions.And I still haven't gotten a single reply on whether it suffices to minimize the VCC-to-bypass capacitor distance, or whether one should consider the bypass-to-ground distance also, in practice.

author: nctnico
author_rank: Super Contributor
timestamp: September 03, 2025, 12:27:48 am
content: Quote from: Nominal Animal on September 02, 2025, 11:45:51 pmWhat you overlook is that the chip itself also has decoupling. Look at the graph on the left which is from the article I linked to early on in the thread. Roughly frequencies over tens of MHz are decoupled by on-die / in package capacitors. When in doubt, follow the manufacturer's advice and look at their reference design. It is not in their interest to publish reference designs which don't work. I'm not saying you can't do better but you can also do much worse.QuoteKeep loop inductance as small as possible. Current going into a chip, also comes out of it somewhere. On a two layer board without ground plane this means keeping both traces short. On a board with a power and ground plane I keep the supply pin closest to the capacitor as the ground plane has the lowest inductance. But this is also governed by routing constraints. A capacitor sideways along a chip is a big hurdle to get traces routed towards it.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 03, 2025, 04:38:14 am
content: Quote from: nctnico on September 03, 2025, 12:27:48 amCapacitors are charge storage elements. All current that came out from it came in from the same end, just earlier. When used for supply bypassing for typical ICs, there is basically no current passing through the other end of the capacitor: it suffices that it stays at the stable ground reference potential. Due to ground bounce and similar changes in the exact potential, and non-ideal capacitors with real-world limitations, there can be some small currents in practice, but they're related more to noise from external sources than supply bypassing. This is what the simple theory says, anyway.The entire loop, from IC VCC pin to capacitor to IC GND pin, of course can couple to external electromagnetic fields, and thus inject noise to the IC, which means that reducing the loop area reduces the possibility of noise coupling from external sources to this particular IC. The other way, as a source of conducted and radiated emissions due to this IC, it is really only from the VCC pin to the capacitor to the supply, with the other half being the GND pin to the supply; there is no need for the return current from the IC to go via the capacitor GND end, it'll go the route that yields the least impedance instead.To me, this says that when it comes to the capacitor, you should place the VCC end as close to the VCC pin as possible, but the other end only needs a stable GND voltage reference. For loops, the supply to IC to supply is the main one to worry about, with the loop from the IC VCC pin to supply cap to IC GND pin being of secondary concern.Now, you (nctnico) claim that it is the IC VCC pin to capacitor to IC GND pin loop area that one should minimize (because one is to minimize its inductance). Why is that? Why is that inductance more important than the aforementioned pin distance? I'm not even sure if that inductance directly contributes to the PDN impedance, again because the IC current does not take that path, only a part of it, as far as I can tell. In practice, I'm sure in most circuits the actual current loop is very similar to the aforementioned loop over the capacitor, which is why the results oftencorrelate, even though the actualcauseis different, i.e. the full supply loop.And I just don't buy "because I say so", no matter who "I" is or what their credentials or experience is. I'm after the actual reasons here.I'm pretty sure this is an important and uncomfortable question, with no immediately clear answer, because this is exactly the kind of stuff that most are used to deal with using practical approximations and rules of thumb, instead of thinking about the underlying actual reasons.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 03, 2025, 05:19:10 am
content: Quote from: Nominal Animal on September 02, 2025, 11:45:51 pmFinally, the circuit does not understand what is called "ground" - so the loop area matters. Often we just go from capacitor GND, with a via, to ground plane, with another via, to MCU GND pin - which isn't a big problem in 4-layer because the prepreg is thin so the distance is short anyway. Draw a few examples, and you'll probably notice that placing the capacitor as close to the Vcc pin as possible also tends to minimize the whole loop; if the ground plane and vias to it are sufficient, that is.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 03, 2025, 05:23:01 am
content: Quote from: nctnico on September 03, 2025, 12:27:48 amYes. Basically, capacitance of all the non-switching transistors offers distributed capacitance across the whole chip. This is necessary because there always will be stray inductance from IC metal layers (power traces), from bond wires (if applicable), and finally the things we are discussing here (PCB layout + capacitor construction). Therefore, chips must be designed to work properly (and pass EMC) with certain amount of external inductance - consequently, it makes no sense to go to extreme lengths of surpassing what "everyone" does. This also means that appnotes do not necessarily describe the optimum design - just good enough.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 03, 2025, 06:01:35 am
content: Quote from: Siwastaja on September 03, 2025, 05:19:10 amBy "ground", I was referring to the potential at the so-called GND pin on that IC, and at the power supply return, nothing more.As long as the other end of the capacitor has that same potential, and it does not vary at short timescales,no current flows in or out of the capacitor end at that potential. The capacitor is not part of a current loop — no current flowsacrossthe capacitor, only across the end that has a varying potential on it —, so why would the area of some loop dictated by the capacitor be significant? Other than as a source for coupled noise from elsewhere, that is.Thus far, everything I've gotten as a response reads like "this is how we have always modeled it", not an explanation one could construct a model out of.I knew this was a difficult question, because the answer is nothowone does it, butwhy; and that requires understanding why you use the models you do, and if you don't know, the question will feel very offensive. I'm trying to not offend anyone here, just to find out why.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 03, 2025, 06:10:50 am
content: Quote from: Nominal Animal on September 03, 2025, 06:01:35 amBut of course current flows through the capacitor. Otherwise it would be unnecessary. The whole purpose of the capacitor is that it can supply the current peaks the IC needs quickly, with least amount of inductance slowing down dI/dt.And because current flows, potentials (measured between any two points) change. We try to minimize that potential change, by minimizing impedance. Yes, this means that even the ground plane is not at equal potential.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 03, 2025, 06:17:25 am
content: Quote from: Siwastaja on September 03, 2025, 06:10:50 amNo. A capacitor stores charge; the movement of charges is the current; and the cause for the movement of charges is a change in the potential.In a very real, very physically exact sense, the currententersorexitsthe (multilayer) capacitor on the end where the voltage potential varies. The current flow is dictated by the time derivative of the voltage potential across the whole capacitor. When one end of a capacitor is held at a constant potential — constant meaning no change in the kind of short intervals we are talking about — there is no current flowing to or from that end of the capacitor.Edit: Someone with the test equipment needed could test this in practice, by using two current-sense resistors before and after a capacitor, and a single-ended signal generator connected to one end, the other end to the common "0V" or "GND" reference potential, and some (much larger) load resistor in parallel with the resistor-capacitor-resistor assembly. You should see the signal only on the sense resistor directly connected to the signal generator, with the voltage on the sense resistor on the other side of the capacitor being basically the "0V" reference potential. I fully admit I could have the physics of capacitors wrong, being unable to verify this in practice for myself. Practice always trumps theory.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 03, 2025, 07:21:15 am
content: Let me reply to myself.Electrically, an ideal capacitor is modeled as passing current \$I = C \frac{d \, V(t)}{d \, t}\$ (through both ends of the capacitor), i.e. directly proportional to the rate of change of the voltage across the capacitor. Physically, this is indeed best modeled as charges passing through both ends of the capacitor.So, me claiming that no current passes on the other end of the capacitor is utter bullshit.The current that passes on either ends of the capacitor is the same: the difference between the current drawn by the IC, and the current draw seen by the supply. The capacitance is not actually a constant, but depends on the voltage, and the inductance (or impedance, rather) of the circuit it forms with the IC. To maximize the effective capacitance, one usually needs to minimize the inductance. For a simple conductor, the loop area is the simplest approximation to its self-inductance. This is what leads to the rule of minimizing IC-and-capacitor loop area to maximize capacitor effectiveness in keeping the IC supply voltage stable.

author: Someone
author_rank: Super Contributor
timestamp: September 03, 2025, 07:46:02 am
content: Quote from: Nominal Animal on September 03, 2025, 06:17:25 amA capacitor is a two terminal device, current must flow through it for it to have any effect at all. As Siwastaja says, if there is no current interacting with the capacitor it can be removed with no effect.

author: nctnico
author_rank: Super Contributor
timestamp: September 03, 2025, 09:40:57 am
content: Quote from: hans on September 02, 2025, 11:02:31 pmSorry, but I don't see where the values are missing. They list 10 capacitors in the placement table and 10 capacitors in the parts table. When there is no number in the placement table, the value is not to be used. There are more tables where different parts are used depending on package size (and PCB width / distance parameters).QuoteMost if not all modern (high speed) microcontrollers have internal regulators. So the sensitive power integrity is handled inside the package entirely. The I/O section is about the only functional group powered by the external supply. This makes the decoupling requirements not so strict which is good as many microcontrollers end up on 2 layer or even single layer boards.

author: mawyatt
author_rank: Super Contributor
timestamp: September 03, 2025, 12:54:31 pm
content: Quote from: nctnico on September 03, 2025, 09:40:57 amBack in the days when we were still involved in IC design, the SoC chips were designed with distributed LDO regulators scattered throughout the chip to help with the internal on-chip PDN. These LDOs were designed with specific external capacitors at specific electrical distances to the external voltages and grounds. We even developed and patented (7728565, Non-Invasive Load Current Sensing in LDO) special on-chip LDOs that allowed internal/external dynamic IC load monitoring without introducing any effects on the LDO or load. For special noise sensitive functions such as on-chip VCOs, Amplifiers, and DLLs which require low supply noise, we developed and patented a special Low Noise LDO (8692529) which had a unique architecture for noise decoupling based upon a Super-Source-Follower (BTW Intel copied/independently (?) developed this....long story discovered at ISSCC a decade ago).Best

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 03, 2025, 01:56:04 pm
content: Quote from: Someone on September 03, 2025, 07:46:02 amAh, this is one of these tricky matters. Dave actually talked about it in a now old video:For the practical purpose of designing electronic circuits, the subtlety usually doesn't matter too much, but it's still an interesting point.In a related vein, you can also have a look at this long thread:https://www.eevblog.com/forum/chat/veritasium-(yt)-the-big-misconception-about-electricity/

author: jnk0le
author_rank: Regular Contributor
timestamp: September 03, 2025, 07:37:01 pm
content: So, when the vendor says:QuoteIt's best to ignore it, and use one larger cap instead. (or 2x 100n)Because those smaller caps are only increasing the noise.

author: nctnico
author_rank: Super Contributor
timestamp: September 03, 2025, 09:10:19 pm
content: No, do NOT ignore the manufacturer's recommendation. They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design and that resulted in the recommended values. Without measuring, you can't say what using different values will do.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 03, 2025, 10:43:48 pm
content: In case anyone wonders about it, I was applying theelectrostaticmodel — as in, what happens when you have two isolated charged conductors and bring them to contact — to decoupling capacitors. The no-current part is based on perfect dielectric model. It is not at all what happens when a capacitor is part of an electrical circuit (and indeed the links SiliconWizard included discuss thecorrectmodel).It is a good example of what happens when you apply the wrong physical model to the situation. (Extremely embarrassing to me, sure, but it happens.)Quote from: nctnico on September 03, 2025, 09:10:19 pmThe obvious errors found in datasheets indicates "very likely have done" is quite optimistic. It may be so in some specific manufacturers' specific product lines, but I'm much less convinced it is true in general. For many cheaper microcontrollers, decoupling capacitor recommendations seem to be based on some random engineer saying "I tried 100nF and it seems to work, so let's recommend that in the datasheet".For things like DC-DC switchmode controllers, I'm sure the supply decoupling is much more carefully investigated, and one should not ignore manufacturer recommendations. Some datasheet even contain tables listing various combinations of decoupling capacitor values and inductor values, with manufacturer recommedation "grading" (IIRC, TI uses "++", "+", and empty for not recommended).

author: Someone
author_rank: Super Contributor
timestamp: September 03, 2025, 10:44:24 pm
content: Quote from: SiliconWizard on September 03, 2025, 01:56:04 pmokay you can do all your electronics simulations and understanding through FEM and field solvers. The practical models that are used successfully for the majority of circuits (including RF) are two terminal and do not include any of those effects.PS linking to a video as an explanation without saying what in it is supporting in your claim is a waste of everyones time.If a capacitor did not have current passing through it, then it could be removed without any effect. Still applies even in the EM field solutions. So you’ve only added noise and confusion.

author: Someone
author_rank: Super Contributor
timestamp: September 03, 2025, 10:52:32 pm
content: Quote from: Nominal Animal on September 03, 2025, 10:43:48 pmCurrent cannot enter and exit a single terminal without an equal and opposite current appearing elsewhere. You’d be throwing away the basic underlying assumptions of field or lumped models. The free energy nut recently trying to claim otherwise was roundly laughed at for trying to say they had a way around all currents are continuous loops summing to zero.There are no clever word games or reframing to fix that. Your use of the term current is fundamentally wrong.

author: TimFox
author_rank: Super Contributor
timestamp: September 03, 2025, 11:05:14 pm
content: In circuits with capacitors, there is "displacement current" inside the ideal capacitor, and "conduction current" in the two leads.Displacement current is a feature of thepolarizationwithin the capacitor, which gives the capacitor more capacitance than an equal geometry with vacuum between the plates.This is similar to the increase of inductance when a permeable material (paramagnetic or ferromagnetic), capable of magnetic polarization, is introduced into the coil.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 03, 2025, 11:53:56 pm
content: Quote from: Someone on September 03, 2025, 10:52:32 pmOnly if you are talking about an electric circuit, in the context where Kirchhoff's current law applies. Physically, current is just the rate of net charge flowing through some cross section.Consider an ESD event, for example. Say, two hollow conductive spheres in vacuum with different charges coming into contact.At the contact point a current will flow until the charge density across the entire conductive surface has equalized. There is only this single current.For electric and electronic circuits, we apply a different model to describe systems involving non-static electricity, specifically Kirchhoff's circuit laws. To remind everyone,The algebraic sum of currents in a network of conductors meeting at a point is zero.The directed sum of the potential differences (voltages) around any closed loop is zero.These only apply to circuits (and not to e.g. ESD events), and at frequencies where the wavelength is much longer than the circuit length. Beyond that, one has to go directly to Maxwell–Heaviside equations describing classical electromagnetism. To properly describe transmission lines, we apply telegrapher's equations (transmission line model); and at even higher frequencies, waveguides (again based on Maxwell–Heaviside equations).Quote from: Someone on September 03, 2025, 10:52:32 pmIf you look at any physics textbook or even the Art of Electronics, you'll see they use "current" with the exact same definition I have.I used the wrong model and approach, the electrostatic one, instead of electric circuit models. Yes, that was stupid of me, and a fundamental error, but one of applying the wrong model to the problem at hand, not a "clever word game" or "reframing".

author: Someone
author_rank: Super Contributor
timestamp: September 04, 2025, 12:12:13 am
content: Quote from: Nominal Animal on September 03, 2025, 11:53:56 pmThread is talking about practical capacitors and how to select/use them. Trying to walk off into mental games of superconducting ideal conductors in lossless voidsisreframing (after the fact, it was never clear) and trying to be “clever”.You claimed this was practical in your opening arguments:Quote from: Nominal Animal on September 03, 2025, 06:17:25 amWe have righty pointed out this is incorrect by using clear arguments falsifying your claims. But instead its now reframed as “but but but in some other context which was never mentioned previously the concept could technically be correct in some abstract way”. Thats word games.Currents have to flow in zero sum circulation. Basic underlying physical laws. They cannot appear in isolation.Lets go with an Oxford definition of electrostatic:QuoteThere is no current in an electrostatic model! Perhaps keep redefining things until you randomly find something which is true? You sound like the free energy nuts at this point.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 04, 2025, 01:00:17 am
content: Quote from: Someone on September 04, 2025, 12:12:13 amYou obviously missed me pointing out I was wrong in#52. Perhaps the concept of someone admitting they were wrong before anyone else noticed or commented on it is utterly alien to you?

author: Someone
author_rank: Super Contributor
timestamp: September 04, 2025, 01:25:27 am
content: Quote from: Nominal Animal on September 04, 2025, 01:00:17 amBut you’re still arguing something something something wall of text ? ? ?ESD and lightning discharges do have a closed loop of current.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 04, 2025, 02:02:53 am
content: Quote from: Someone on September 04, 2025, 01:25:27 amJust add me to your ignore list, please. It's not like you ever contribute anything useful anyway.Quote from: Someone on September 04, 2025, 01:25:27 amNope.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 04, 2025, 03:36:22 am
content: Quote from: Nominal Animal on September 02, 2025, 11:45:51 pmWhat you are about is the whole loop, so the Vcc and ground leads to the capacitor are equally important. For high frequency the capacitor itself might as well be a solid block of metal.The details depend a bit on your pcb stack up. For high density boards with thin dielectric, the plane inductance is tiny. So you just want get down to the power/ground planes as quickly as possible. If you can use via in pad that keeps the loop area the smallest. If that doesn't work, put the vias as close as possible and to the side of the capacitor rather than above and below. Once you have food via placement for both the component leads and the bypass capacitor the location of the bypass capacitor itself hardly matters.For something like a 4 or 6 layer board the plane inductance might be higher so you want to try to keep the bypass capacitors closer to the power pins.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 04, 2025, 03:56:44 am
content: Quote from: Nominal Animal on September 03, 2025, 06:17:25 amFor the purposes of electronic circuit design you can essentially 100% of the time consider only the total current as the coulomb current plus the displacement current. In that case "current always flows in loops" is an iron clad law of nature, and it's always true not just on average but at every instant. You are of course free to not do this, and only define free charge movement as "current" but you are making your life unnecessarily difficult, and for no real benefit.In this mode of analysis it's correct to say current flows through the capacitor. This works really well with lumped element circuit models (although it is far more general than that). If you have a current imbalance, say more charge entering the left plate than leaving the right, that creates a net charge and therefore an electric field. Those electric field lines have to go somewhere, usually to the nearest ground plane. Electric field between two metal conductors is just a capacitor. So now we turn the problem of handling unbalanced current flow into a realizing that it's just a parasitic capacitance.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 04, 2025, 05:59:45 am
content: Quote from: nctnico on September 03, 2025, 09:10:19 pmYou wishSome may have. In reality, example circuits are usually just "good enough". Heck, it is completely normal that application examples are not even working properly.Quote from: jnk0le on September 03, 2025, 07:37:01 pmI would ignore it by default, and adjust if necessary.I don't think it isthatcommon to accidentally cause serious enough resonances to make this "2-3 different capacitor values" concept perform significantlyworse. It is still nevertheless a stupid thing to do by default: it increases your BOM cost andis not useful. Unless you count "following manufacturer recommendation" as a positive. It might be, depending on how bureaucratic your organization is, and how much trust is placed on you as an engineer.This whole capacitor thing is typical example of cargo cult. Those capacitors are placed and recommended because others have done it. And it works, just like adding a capacitor made of cardboard works. When the designs work and pass, it is easy to keep recommending. This is also why we need a little bit of courage of stop doing that.

author: tggzzz
author_rank: Super Contributor
timestamp: September 04, 2025, 08:37:52 am
content: Quote from: Siwastaja on September 04, 2025, 05:59:45 amAs with everything, you have to judge why the information was produced. I was once asked to create digital logic simulation models, and the client didn't want to think about acceptance tests. They just wanted the be able to present them as a "yes we have it" tickbox to their clients. I declined their moneyFor bog-standard opamp circuits they may well not have tested the schematic.For RF circuits where the datasheet or application notes contain a schematic and PCB layout, something close to that has probably been tested.For RF and complex digital evaluation boards with schematics and PCB layout, it is wise to pay very careful attention.

author: nctnico
author_rank: Super Contributor
timestamp: September 04, 2025, 09:08:28 am
content: Quote from: Siwastaja on September 04, 2025, 05:59:45 amWhere is your evidence? And don't point to the video linked to in the first post. It is a school book example of simplifying a model to the point where it is completely wrong.All of the designs I did with high speed parts where it is clear that the manufacturer did PDN simulation and testing, end up using different values. None of the materials written by real experts I have come across state that using single or different values is always right or wrong. Those materials only say: simulate & measure (which makes most sense to me). IOW: you can't go around and claiming to ignore manufacturer recommendations as a general advice as you can't know whether your suggestion is an improvement or makes things worse.

author: Howardlong
author_rank: Super Contributor
timestamp: September 04, 2025, 09:36:57 am
content: Quote from: Siwastaja on September 04, 2025, 05:59:45 amWhile this may well be the case, good luck getting meaningful vendor support if you drift away from their published recommendations!I'm with @nctnico on this, the first port of call is the vendor's own datasheet recommendations and published reference designs IMHO. And yes, the datasheet recommendations and reference designs do often differ, in which case probably the reference design is the starting point.

author: nctnico
author_rank: Super Contributor
timestamp: September 04, 2025, 09:39:24 am
content: Quote from: Nominal Animal on September 03, 2025, 10:43:48 pmAnd how do you get to the conclusion it is random? I can understand that 100nf looks like a historically grown standard without much merit. But you also need to consider that because 100nf is standard for decoupling capacitors, chips might be designed specifically to have a 100nf decoupling capacitor externally. But these are still assumptions. Usually there is a lot more information to be found beyond the datasheet. For starters in the application notes and many manufacturers have support staff which helps to answer more in depth questions.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 04, 2025, 04:53:06 pm
content: Paralleling several small SMD caps in similar packages rarely makes any sense as they have a very similar parasitic inductance and ultra-low ESR. At worst, that can cause more issues than good due to multiple resonant frequencies (as shown in the video), but in many cases, it has few downsides but practically no benefit.After that, there are many specific cases (that's called engineering), but seeing, say, a modest MCU with VDD pins bypassed with a 1 µF ceramic and 100 nF ceramic in the same package or barely larger for the 1 µF (say 0603 for the 1 µF and 0402 for the 100 nF), that makes almost no sense. Might help if you're very tight on routing though, to allow the smaller cap as close to the pin as possible. So, yeah, sometimes it may not seem to make any electrical sense just based on the schematic, but considering the PCB layout, it may.Bottom line is, if you half know why you do things, you're better off than just using cargo cult approaches. Shocker.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 04, 2025, 06:15:07 pm
content: Quote from: nctnico on September 04, 2025, 09:08:28 amNowhere, of course. Let me rephrase: This capacitor thing islargelycargo cult.We couldproveindividual design examples as either better or worse case-by case. Say, build two prototypes, test analog performance, go to EMC lab. A lot of work, and maybe 10-20k€ for each case. Then we could collect statistics for the general trend. Even more work. Neither of us is willing to provide such proof.I totally agree with you that some specific circuit examples probablydowork better with exact parts list as given, than simply replacing everything with 0402 1µF. The following traits increase the probability that this is the case:* Special IC with critical high-frequency performance* Exact capacitor part numbers given, not just values* Capacitor values are not in multiples of ten, but more "weird" values, such as 68nF and 1uF, and not 10n || 100n || 1uIt is possible some reference design went "for the dip" as I call it. Maybe, say, PLL on FPGA is sensitive to excess impedance at some exact frequency.Then again, for something like an FPGA, I also suspect that choosing different oscillator frequency, or different PLL configurations, affect the exact frequency where most bypassing is needed. In such cases the capacitors should be adjusted, too. If going "for the dip", that is. And as I said, careful tuning is required and component tolerances are risky. I claim this is best done on a prototype looking at say eye diagram, spectrum analyzer screen, or at EMC lab, soldering alternative components until exact best spot performance is found, and keeping track of exact part number used, making sure to use parts with best possible tolerances and stability - basically meaning C0G if at all possible. Consider the effect of MLCC aging on capacitance value, and thus SRF, on X7R! For a robust design, you would try to take this aging into account, and aim for the correct side of the dip, so that it does not soon drift out of the required value range.I redefine my claim that if we pick 100 random designs from perfectly randomized appnotes, datasheets and other professional literature which show usage of three different ceramic capacitance values in parallel, 95 are cargo cult: where this strategy has no benefit whatsoever, and possibly in significant (10-20?) of them, is seriously detrimental to analog/radio performance or EMC.We need to distinguish between generic wide-bandwidth bypassing, and utilizing SRF dips for narrow-band bypassing. Two different things. The common "wisdom" that by combining enough capacitor values you "cover the entire band" is seriously misled, and caused simply by looking at impedance graphs in isolation without realizing they have different Y axis. See reply #20 for an example of the typical misconception.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 04, 2025, 09:38:35 pm
content: Quote from: nctnico on September 04, 2025, 09:39:24 amI did not write the capacitor value or recommendation is random, I wrote that for many cheaper microcontrollers, the recommendations seem to be written by arandom engineerspending minimal effort on it. But the question "conclusion based on what" is a valid, good one.First, let's start with a counterexample: Microchip PIC16F152 series. Not only does it have specific recommendations in the datasheet, it also explains why, and when to add further decoupling and bulk capacitance. It is the detail, options, and reasoning behind the recommendations that makes it seem reliable and very useful even to a hobbyist like myself.Next, an actual example of suspicious recommendation:Silicon Labs EFM80BB50series, which says precisely"1 μF and 0.1 μF bypass capacitors required for the power pins placed as close to the pins as possible."That's it. Considering the core runs at about 50 MHz at 5V drawing about 3.3mA, that recommendation just does not make sense. Rather, it sounds like that is what they always use when testing the design, and haven't characterized the power delivery network any further. Put simply, to me it sounds like "do it this way because we haven't even considered anything else nor measured anything".If I were to use the EFM80BB50, I'd look elsewhere for guidance on the supply bypassing. The imperative statement is too obtuse to be taken as serious design advice or good engineering practice.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 04, 2025, 11:54:50 pm
content: Quote from: SiliconWizard on September 04, 2025, 04:53:06 pmMultiple capacitors in parallel can help because parallel inductors reduce the impedance. What doesn't (usually) make sense is to use different capacitance values, but a totally reasonable process is:1) pick the smallest package you are comfortable with (say 0402)2) Pick the highest value capacitor you can get in that package cheaply3) Use as many instances in parallel as you need to get the desired impedance4) If needed have a bank of bulk capacitors somewhere on the PCB with enough capacitance and low enough ESR for the entire PCB.Resonances can be a problem so _if_ you parallel capacitors it's something you should at least think about.Now, IC packages pins have inductance too. In many cases it's comparable to the inductance of a capacitor. That's why high power digital devices have lots of power and ground pins. So it's a good bet that you *rarely* need more decoupling capacitors than power pins.QuoteI'm not sure about that. It's good to understand the underlying mechanism, but it's actually extremely difficult to solve what you *really* need. It's hard to design, hard to simulate, and hard to measure. Sometimes there is no way around it, but following simple rules of thumb like "add one 100 nF capacitor per power pin" is usually overkill, and sometimes insufficient, but a lot of times you can just do that and not worry about it. It's rarely the best thing you can do, but it's often good enough.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 05, 2025, 12:59:46 am
content: This PDF log of experiments with decoupling capacitorsby Gerhard Hoffmann in 2007 shows the parallel different-valued capacitor antiresonance issues nicely. See e.g. page 6, using 22µF 0805 and 100nF 0402 with plenty of vias to ground plane, on a 50Ω stripline, so there is some inductance also in the decoupling loop. The one on page 18 with a 20-pin DIP socket with some (tantal?) cap diagonally shows how adding a 0805 100nF creates a clear antiresonance peak where you'd expect the dip to be.

author: thm_w
author_rank: Super Contributor
timestamp: September 05, 2025, 01:26:13 am
content: Quote from: nctnico on September 04, 2025, 09:08:28 amYou said yourself on die capacitors deal with anything >10MHz, Bogatin says the same. So why would 1nF or 10nF make any difference? Maybe FPGA is a special case that has poor on die decoupling?The vast majority of designs use basic parts, and have these cult recommendations, so its fairly clear they were not extensively analyzed. Exceptions can exist.https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values

author: Siwastaja
author_rank: Super Contributor
timestamp: September 05, 2025, 07:16:10 am
content: Quote from: ejeffrey on September 04, 2025, 11:54:50 pmYes! If you put 100n || 10n || 1n in parallel, you will see slight improvement in HF for each added capacitor, sure. But this is indeed because of the paralleled inductances (assuming, you can find good spot in the layout for each capacitor): you get the same overall HF performance with 100n || 100n || 100n, plus as an added benefit, better bypassing at lower frequencies.So sprinklinga lot of capacitorsall over the place is generally a good idea: just like sprinkling vias, but you don't normally want different values on the same bus to do that.Practically though, it might be that only one of the capacitors is at the optimum placement. If the added ones have extra inductance from layout, then they provide diminishing returns. And herein lies the danger of the cargo cult solution: say you use 100n || 10n || 1n in parallel. You easily think that the 1n is the one that must be placed at the "best spot" because it bypasses "highest frequencies". Wrong! 100n bypasses high frequency just as well. Put that closest. If you then need to use 10n or 1n to "satisfy recommendations" (could be as well cardboard capacitors), place them further away. Cardboard would be better, avoiding risk of resonances, but I don't know how often that risk realizes.And if you really have that case that you need 1µ for wide-band bypassing and a 330pF C0G for handling a specific problem frequency, then... they both need to be at optimum locations.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 05, 2025, 07:19:54 am
content: Quote from: Nominal Animal on September 05, 2025, 12:59:46 amWow! That's a pretty serious price to pay for the "superior" "recommended" "solution".

author: tggzzz
author_rank: Super Contributor
timestamp: September 05, 2025, 07:54:12 am
content: Quote from: Nominal Animal on September 05, 2025, 12:59:46 amThat cap-in-a-socket was, from memory of 45 years ago, a simple ceramic.Back then it was often LSTTL on a 2 layer board, and the one-cap-per IC was novel and controversial and often omitted, and that could result in marginal operation. In such cases those sockets could be retrofitted without respinning the PCB, a major advantage when using red-blue rubylith tape for the layout.I'd be interested in seeing the effectiveness of a similar concept, the Rogers Micro-Q capacitors. They too fitted under ICs but didn't need a socket and had a construction much more like a transmission line or groundplane. Difficult to find pictures now, but see US patent 4734819

author: Siwastaja
author_rank: Super Contributor
timestamp: September 05, 2025, 08:14:04 am
content: This is the generic (simplified) concept: three impedance curves, each havesame total C, each havesame package sizeRed: single large capacitorGreen: Multiple same capacitors with same total capacitance as redBlue: Multiple different value capacitors with same total capacitance

author: nctnico
author_rank: Super Contributor
timestamp: September 05, 2025, 08:16:54 am
content: Quote from: Nominal Animal on September 05, 2025, 12:59:46 amThe problem with this experiment is that it is not a representative model of how capacitors are mounted on the board in a real circuit. So the results are not representative. You need to (at least) include trace inductance, via inductance, model the source (regulator) and load (chip(s) ) as well in order to get valid results. The impedances are so low that the circuit board itself forms a component as well. So you can't leave the circuit board out. The creator of the video linked to in the first post fell into the same trap. As I wrote before: A PDN network looks more like a bunch of cascaded elliptic, low-pass LC filters. These filters are quite sensitive to component values and need proper input and output impedance matching.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 05, 2025, 08:45:39 am
content: Quote from: nctnico on September 05, 2025, 08:16:54 amBut somehow one should blindly trust a data sheet where the statement "1 μF and 0.1 μF bypass capacitors required for the power pins placed as close to the pins as possible" is all that is said about PDN/decoupling capacitors?Yeah, no. I think your opinion on this is nonsensical and defenseless.

author: nctnico
author_rank: Super Contributor
timestamp: September 05, 2025, 08:48:41 am
content: Quote from: thm_w on September 05, 2025, 01:26:13 amQuote from the article:Do not be lulled into thinking that three different values of capacitors is a robust strategy, or that three capacitors all the same value is more robust. Without a system level analysis, they both may be equally acceptable, equally marginal, or fail from the same faults.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 05, 2025, 09:39:11 am
content: Quote from: nctnico on September 05, 2025, 08:16:54 amOf course, but example schematics that just show paralleled different values are useless, because as this experiment demonstrates, the layout is important, and when using different capacitor values in parallel then it'seven more importantbecause with different values of C, parasitic L easily drives it into resonance as shown (page 6 vs 7). You have probably worked with some very good and well thought out recommendations which include part numbers and layout guidance. But that is the rare exception, unfortunately.

author: tszaboo
author_rank: Super Contributor
timestamp: September 05, 2025, 11:12:24 am
content: Quote from: nctnico on September 05, 2025, 08:16:54 amNominal Animal: It's an interesting experiment, and I saved it for future reference. Thanks for posting it.nctnico: I fully agree with you. PDN is not a transmission line, you typically have an entire plane or split plane for a power supply. There will be distributed capacitance in the several pF region in, with the inductance of almost nothing.Plus what might be a bigger issue is that there wasn't any DC applied to the capacitors.Best is to test with the real device. Connect a power rail probe and a high speed scope, look at the noise in the time domain, look for dips that would violate minimum voltage specifications. And look with a FFT in frequency domain for typical noise figures, and how to get rid of them with the soldering iron. At least having several different size capacitors with different footprints give options.Shoul dI even bring up ferrite beads? More oil on the flam?

author: Siwastaja
author_rank: Super Contributor
timestamp: September 05, 2025, 11:31:24 am
content: Quote from: tszaboo on September 05, 2025, 11:12:24 amYeah. Power planes are another widely misunderstood things. You have it correctly here but the devils in the details: several pF (not more) with inductance of "almost nothing". This means just the vicinity of the power pin; only that power plane contributes. This is also why wide power tracks (think segmented plane) are as good as full planes. The further you go from the power pin, the more inductance - physical loop distance - you again have, the fact it's a plane doesn't make it any more magical.You could model the plane as a transmission line, but then you would also need to magically couple to the component leg with the whole width of the plane. Not possible.In other words, calculating plane capacitance for a full large PCB - resulting much larger number than a few pF - and then thinking that this is available to the IC power pin, is incorrect.

author: nctnico
author_rank: Super Contributor
timestamp: September 05, 2025, 07:45:02 pm
content: Yep. Powerplanes or large copper sections are not a golden bullet. I've seen designs go wrong due to too high DC resistance or decoupling not being close to a pin. I'll admit that these where demanding designs though (high speed chips drawing several amps).

author: thm_w
author_rank: Super Contributor
timestamp: September 05, 2025, 10:06:38 pm
content: Quote from: Siwastaja on September 05, 2025, 08:14:04 amlol, you could have used the image from link above:Quote from: nctnico on September 05, 2025, 08:48:41 amSure, so what they are likely saying is there are exceptions as well. But in the vast majority of cases, its done for no good reason, and performance would be better if you follow Bogatins recommendations instead, if you are not able or willing to do any analysis.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 06, 2025, 12:32:34 am
content: Quote from: tszaboo on September 05, 2025, 11:12:24 amOh, absolutely. For an MCU, try to stress the core and the peripherals some, too, not just let it sit idle in reset.But, what doyoudo in the schematic and design phase, when the only thing theIC datasheetsays about power delivery and bypassing is"1 μF and 0.1 μF bypass capacitors required for the power pins placed as close to the pins as possible", for an IC with a 50 MHz clock, 5V supply, and a 3.3mA active current draw?I would not trust that datasheet regardless of what nctnico says. Instead, if I wasn't just a hobbyist but doing this stuff professionally, I'd do minimal test board(s), and measure as you described, and experiment with a few standard capacitor types (C0G/NP0 and X7R) and values (100nF to 4.7µF) in different sizes (preferably on separate boards, using standard/optimal footprints for each size), to see how the ripple and noise is affected; maybe make a second PCB based on the first especially if multiple caps are needed, then make an informed guess based on the measurements. Testing would also show if one can get bitten by the parallel antiresonance peaks when using different-valued capacitors.Are there other ways to go about it? I do know ofFast Field Solversthat one can use to find the inductance and capacitance of conductor topologies, so if the datasheet or design mentions key frequencies, one could at least get into the ballpark, and compare different layouts to find out their properties (self-inductance in particular for IC decoupling capacitor loops). But that's more like checking beforehand which kind of PCB layout might be most useful for the real-world testing.

author: nctnico
author_rank: Super Contributor
timestamp: September 06, 2025, 06:10:16 pm
content: Quote from: Nominal Animal on September 06, 2025, 12:32:34 amWell, that is not what I wrote exactly. What I wrote was that the manufacturer's information (datasheets, application notes, reference designs and support) is the first port of call. I looked at the reference design of the EFM8BB50 but that doesn't instill much confidence either. The project doesn't even have a decent bill-of-materials which is a red flag where it comes to the qualifications of the person who did the reference design. But this could be a generic Altium problem. I've seen other engineers struggling with getting a decent BOM from Altium.So with the EFM8BB50 you are left with three options: ask Silabs what the deal is with decoupling. If that doesn't result in a satisfying answer, then either use a different part with complete specs or measure it yourself. Keep in mind that measuring it yourself takes time and pushes the engineering costs up making a different part, which has been properly specced, possibly cheaper to use.QuoteThat is overkill as it would take very carefull setting up of the circuit board model. And after a cursory look it doesn't seem like that software is very useable as-is for PCB layouts. Higher end CAD packages have impedance simulations build in though and doing AC and DC PDN analysis are expensive extra options.Doing DC analysis using open source tools is pretty tedious already. Robert Feranec published a video a few years ago:However, it never hurts to play with a field solver like Sonnet lite. I have done some interesting simulations with it using lumped parts on microstripline circuits (filters in the 300MHz to 1GHz range). It certainly gives you a good understanding of how high frequencies interact with a board layout as Sonnect can plot the current densities in the board changing along with the frequency.More hands on: you can follow the trial & error approach suggested by tszaboo; add places for extra capacitors to the design and measure the result. It is easier to not populate parts on a board compared to adding extra parts as a bodge. Having something like a Nano-VNA (lowest cost solution) could be useful but I don't know if the performance is decent enough in the 100kHz to 20MHz range. The articles I linked to earlier give a decent approach on how to determine the required decoupling capacitor if you start without any decoupling capacitors and do VNA measurements. For a relatively simple circuit consisting of a microcontrollers and some auxilary chips powered by the same supply, this should be doable.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 06, 2025, 06:57:59 pm
content: Quote from: nctnico on September 06, 2025, 06:10:16 pmGenerally a good idea, but don't go overboard with this. If adding extra footprints compromises the layout otherwise, e.g. by moving capacitors out of best spots, or wasting area otherwise usable for more vias (e.g. two per footprint instead of one), then the cure was worse than the disease - and worse, cure was premature, often there is no disease. But sure, whenever adding extra footprints is relatively easy and with no compromise, do it.For something like usual microcontrollers, just following the modern, well-understood best practices - one contiguous ground plane, 1uF 0402 bypassing as close as power pins as humanly possible; enough ground vias and stitching layers together - nearly guarantees EMC pass. Any EMC problems are going to be elsewhere. External interfaces, ESD, and so on. Maybe switch mode converters. An MCU fails immunity or emissions only if the layout or bypassing isseriouslybotched.

author: Marco
author_rank: Super Contributor
timestamp: September 06, 2025, 07:16:41 pm
content: If embedded capacitance materials were to become multilayer, all the decoupling capacitors could go away.As long as PCB manufacturing uses laser drilling and epoxy filling, I don't see why it couldn't be done. Laser drill the vias a little larger, epoxy fill the holes, then redrill the right size. You'll drill through some of the stitches keeping the capacitor stack properly connected, but those will be vastly redundant.

author: TimFox
author_rank: Super Contributor
timestamp: September 06, 2025, 07:27:01 pm
content: "Muntzing" is a technique, dating back to vacuum-tube TV receivers, of removing components until the circuit stops working.The original application was screen bypass capacitors at the tube sockets of the IF amplifiers, which could be snipped off in real time with an insulated pair of diagonal cutters.Eliminating a screen bypass capacitor reduced the gain of that stage.Peases's historical description:https://www.electronicdesign.com/technologies/industrial/boards/article/21771148/whats-all-this-muntzing-stuff-anyhow

author: nctnico
author_rank: Super Contributor
timestamp: September 06, 2025, 10:27:27 pm
content: Quote from: Siwastaja on September 06, 2025, 06:57:59 pmIME, EMC is least of the concerns where it comes to proper decoupling. The primary function of decoupling is reducing ripple on the supply lines in order to reduce noise in sensitive analog circuits and to keep the supply voltage within tolerances so a device operates reliable. Sure, a poorly decoupled digital or HF circuit can be prone to emitting more radiation but the biggest problem is likely that it won't work very well.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 07, 2025, 04:11:29 am
content: Quote from: nctnico on September 06, 2025, 06:10:16 pmIt is how I read your position, causing the argument. You see, we are in full agreement that"the manufacturer's information (datasheets, application notes, reference designs and support) is the first port of call". It definitely is! The problem is that for many MCU's, the datasheets and so on are just as lacking as for SiLabs EFM8BB50.The disagreement happened because of your statements like"No, do NOT ignore the manufacturer's recommendation. They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design and that resulted in the recommended values."just do not match the quality of information in datasheets of many of the (cheaper end) microcontrollers I use and consider using, the EFM8BB50 just being a typical example. Your statement definitely applies to e.g.Microchip PIC16F152 series datasheet(section 4, starting at PDF page 18), which describes the PDN in quite useful detail with practical advice and guidance easy to understand even for a hobbyist; but in my experience, among the cheaper microcontrollers, it is a rare good example, and not the norm at all.Quote from: nctnico on September 06, 2025, 06:10:16 pmTrue, although I do suspect it would be possible to do a KiCad plug-in to export the PCB gerbers and vias — the basic geometry, in other words —, but the IC part (including legs for SMD and TH packages) would be simplified to a jumper wire. For comparative testing of options that would suffice, but it would not have any predictive power wrt. coupled, conducted, or radiated EMI. The reason I mention Fast Field Solvers, is because I have an extensive simulator development background, prefer using Open Source because of being just a hobbyist and having no budget to spare (but not ideologically opposed at all, even though Tux is my mascot), and this kind of stuff is much more familiar to me than EDA or CAD software, especially the high-end professional EDA/CAD stuff.Quote from: nctnico on September 06, 2025, 06:10:16 pmAh, I didn't realize. I should have expected that.I also haven't used the E. M. Workbench, the FreeCAD-based interface to some of the Fast Field Solvers, yet.Quote from: nctnico on September 06, 2025, 06:10:16 pmAbsolutely, and for the small microcontrollers with poor documentation, alsocheap enougheven with a few test/experimental PCBs, as long as one has a decent (not that expensive) network analyzer, or even an oscilloscope with careful measurements (x1 probing for ripple/spectrum, x10 for noise/peaks) undestanding the effect of the probe capacitance, inductance, and input impedance.All this just leads to one being very suspicious when first looking up a possible new MCU one might want to use. Again, the MCUs with poorly documented and likely un-characterized PDNs do seem to mostly rely on cargo-cultthrow these capacitors at it and it'll be golden"design principle", which easily leads hobbyists astray, and may even become an attitude one does not even notice enough to question... so even for hobbyists, knowing how to verify and do it better, would definitely be useful.