Streaming coherent hi-speed ADC's to PC? USB3 or Some other interface? - Page 1
Forum section: electronics / projects

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: September 17, 2020, 09:17:29 pm
content: I want to build an SDR with multiple coherent hi bandwidth RX channels and few TX channels too, and I want to be able to output the raw IQ stream straight to a PC running GNU-Radio as the board will be used mostly for experimentation and learning about RF-Science, arrays, beamforming etc.I want to use twoAnalog Devices LTC2217ADC's (single channel 16bit 105msps) and twoTI ADC3243ADC's (Dual Channel 80MSPS) to create two 50MHz channels and four 20MHz channels. So that comes to a total of 270MSPS when sampling all six channels at full bandwidth.Now im not sure I am doing my math right but 16 and 14 bit ADCs will both create 2 bytes of data per sample so that would be 540,000,000 bytes per second or 540MB/s or 4.32Gb/s, right? So that is way to much for Gb Ethernet, and just under the limit for USB3? It seems like a Cypress USB FX3 would just cut it, but from what I have read with other projects using the USB FX3 it seems like its hard to get over 200MB/s, and one guy made an SDR from an LTC2217 105MSPS ADC and an FX3, he told me he has had real issues getting over 30mhz of bandwidth due to the FX3. An FPGA is a better idea anyways because I'm going to need 6 LVDS interfaces for the ADCs and DACs, but im not sure if USB3 is the best answer ive read a lot of its speed issues have to do with the way the pc connects the PCIe lanes to the USB3 hub, so maybe the FX3 chip isnt even the culprit with speed issues. Since coherence between all ports is an issue I dont think using multiple Gb Ethernet ports is a good idea?

author: thm_w
author_rank: Super Contributor
timestamp: September 18, 2020, 12:08:53 am
content: Quote from: rwgast_lowlevellogicdesin on September 17, 2020, 09:17:29 pmYou can timestamp/number the packets then re-assemble on the PC side right.

author: jbb
author_rank: Super Contributor
timestamp: September 18, 2020, 12:39:20 am
content: That’s a lot of data for the PC to process.10G USB3 might work? Never gone that high...Could you do some preprocessing in FPGA? They’re great for this sort of thing; fast processing of high speed inputs. Some fancy ADCs now come out with digital frequency mixers, filtering and decimation built in. Maybe you could do some of that on the FPGA and send back I/Q samples at a lower rate?For coherent receiving like beamforming the FPGA might be great; PC sets parameters and FPGA spits out processed samples after applying the beamforming algorithm.

author: NiHaoMike
author_rank: Super Contributor
timestamp: September 18, 2020, 03:19:39 am
content: A PCIe FPGA would give you loads of bandwidth, albeit not cheap. SQRL Acorn is one of the cheaper ones, but it's designed for compute and doesn't give a whole lot of I/Os. Might be able to connect it to another (cheaper, without PCIe) FPGA board over LVDS and still end up cheaper than a PCIe FPGA board with more I/Os.It's also possible to do SDR processing using a GPU.

author: magic
author_rank: Super Contributor
timestamp: September 18, 2020, 05:55:55 am
content: Maybe you could find some 10G Ethernet interface to hook up with FPGA? No idea about that stuff...

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: September 18, 2020, 07:31:47 pm
content: Yes I had thought about doing a lot of processing on the fpga side, but the thing is I want to be able to access the raw data with gnu radio which needs iq data to work with. I looked in to pcie, the issue is I want to keep the price around 600 or less, even going cheaper on the ADCs, pcie is going to get exspensive and after what I've spent on the ADCs and gear for prototyping I cant afford a 500 dollar plus dev kit with pcie.I have two other ideas that could work, besides timestamping 5 gigabit ethernet ports (that could work but is just not elegant at all), I'm just not sure how feasible they are, having NO fpga experince. The first would be to compress the data stream, but I'm afraid that might add to much latency especially for any RF expermentation that is highly determenstic on top of adding complexity to the timing of any digital stuff, but I'm no compression expert either. Secondly and maybe a better solution if the new zynq/soc style fpga's are capable of this maybe I could run GNU Radio right on the ARM core. I'm assuming the FPGA can move that much ADC data to the cpu core in real time since there connected togather in the silicon?

author: NiHaoMike
author_rank: Super Contributor
timestamp: September 18, 2020, 11:58:31 pm
content: Quote from: rwgast_lowlevellogicdesin on September 18, 2020, 07:31:47 pmSQRL Acorn has PCIe X4 and costs $60 or so, depending on what deal you can get. There's enough I/O to implement 4 LVDS pairs, which will most likely have to connect to another FPGA (a smaller, cheaper one that doesn't have PCIe) since I'm not aware of any ADCs with such narrow buses.QuoteIt's going to be a steep learning curve that requires a very different mindset from "conventional" programming. My experience with FPGA programming so far is that it's a great direction to go with great rewards along the way, but don't expect it to be easy just because a pretty girl showed you the way.

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: September 19, 2020, 05:21:55 pm
content: Arent you able to do most things in an FPGA using vendor ip blocks? I mean I'm just trying to push data from adcs to a pc, later I would like to do dsp on the fpga and a lot of other fancy stuff but in the beginning it's all about piping those lvds streams to the pc

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: September 21, 2020, 12:17:28 am
content: Well after doing a lot more research on things it looks like what I want is doable using 10gb ethernet as suggested, or usb 3.1. But not only will all this bandwidth make the SDR more expensive (mostly due to cost of an fpga that can handle the data) but will require the user to have monster PC. Really the whole point of this is to get low noise high dynamic range RX with coherency for beam forming, inferometry, noise cancelling etc. I think I'm gonna just get some cheaper quad channel ADCs with simultaneous sampling and one wideband lower res adc for use as more of a band scope monitor.I do have a question about these high speed simataneous sampling adcs though. So if the adc is spec'd at say 20msps dual channel, is that 20msps shared meaning you basically have two ADCs sampling at 10msps or are both channels sampling at 20msps? I've read data sheets for simataneous sampling ADCs from TI,LT,Maxim and AD and none of them say anything about bandwidth sharing. I'm guessing since the ADCs arent interleaved sampling you get max sample rate on all channels.. but I could be wrong?

author: jbb
author_rank: Super Contributor
timestamp: September 21, 2020, 02:18:41 am
content: Well, less bandwidth leads to less noise and less money.Beware the marketing department. That first page of the data sheet can be very carefully phrased. Simultaneous sampling is probably exactly what you want but some ADCs are switchable (eg turn 4 ch @ 100 MS/s into 2 Ch & 200 MS/s with interleaving) which can lead to misleading advertising copy on the front page (ie “4 Ch 100/200 MS/s”)Typically I’d say check the diagrams in the data sheet; firstly to see what analog input goes where and secondly the details on output data format (they can’t shade the truth here or it won’t work).You’d probably get good results by saying “I’m thinking about part XYZ, I think that does 4 Ch 20 MS/s, can someone help me check that’s right?”

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: September 21, 2020, 03:36:06 am
content: Well I'm specifically interested in this quad channel 5msps adc, as long as I can simultaneously sample 2.5mhz at the same time on all four channels.

author: jbb
author_rank: Super Contributor
timestamp: September 21, 2020, 04:42:31 am
content: Err, do you want 2.5MHz useable bandwidth? As a practical matter, you can’t practically get 2.5MHz bandwidth with a 5 MS/s ADC; you’ll need an anti alias filter.

author: rwgast_lowlevellogicdesin
author_rank: Frequent Contributor
timestamp: September 21, 2020, 07:29:38 pm
content: Why is that? Nyquist stayed you need 2x the sample rate 5,000,000S/s divided by 2 is is 2,500,000 or 2.5MHz? Of course I'll need a lp filter and and fir/iir filter for aliasing/decimation. Then gps lock four pll's with four mixers to simultaneously and coherently tune four 2.5MHz chunks between 0-6ghz down to four 0-2.5MHz to feed through the filters in to each ADC. Next it will probably get sent to an fpga for the fir/iir. Next if power couplers are used to connect multi channels togather the fpga can stitch the data togather to create higher bandwidth single data streams. After the stitching occurs if needed, each channels stream will get time stamped then sent off to the PC.This only works if the ADC I linked to can sample all four channels at 5MS/s at the same time I'm pretty sure it does but I'm not buying a 50 dollar ADC unless I'm sure.... I already spent 200 on the two LTC2217s and I'm not even sure I'll use them now...

author: jbb
author_rank: Super Contributor
timestamp: September 22, 2020, 01:37:58 am
content: Nyquist was of course correct. However, as a practical matter it doesn’t work that way.Let’s consider a 5 MS/s ADC. Feed in signal at 2.499 MHz and you’ll get a signal at 2.499 MHz out. Great.Now imagine there is some unwanted signal at 2.501 MHz. That will be sampled with aliasing and come out at at 2.499 MHz: the same as your signal of interest. You can’t tell them apart.You could try to build an analog filter to pass the 2.499 MHz signal and get rid of the 2.501MHz signal, but that won’t be easy!As a practical matter, the rule of thumb if you want full reconstruction is to sample at 5x - 10x the frequency of interest. This gives you some margin.E.g. for 20 MS/s sampling rate, Nyquist bandwidth is 10MHz.So a 2.499 MHz input produces 2.499 MHz output as expected.A 2.501 MHz input produces 2.501 MHz output which can plausibly be filtered off digitally.It’s only once you get up to 17.501 MHz that the alias frequency gets back down to 2.499 MHz and can’t be separated from the desired signal.This leaves much more elbow room for the analog anti alias filter to work.

author: BrianHG
author_rank: Super Contributor
timestamp: September 22, 2020, 02:03:57 am
content: I don't get it, if you are willing to use 2 sets of FPGAs, 1 for samplers and 1 for com to PC, why not over-sample in the first FPGA, and digitally filter & downsample. This is child's play for FPGA. In fact, why not just place your entire SDR frontend in the FPGA and slow down your com speed to a fraction of your current rate.

author: AD0ES
author_rank: Newbie
timestamp: January 26, 2023, 05:36:14 pm
content: I am doing something similar as an offshoot of the project mentioned in Reply #3Whats your current project status?