LTspice / newbie question - Page 1
Forum section: electronics / beginners

author: 3n2323
author_rank: Contributor
timestamp: April 24, 2012, 05:16:29 pm
content: i was playing with LTspice, and got the following that i don't understand...this was the circuit i used:the waves looked like this:simulation command is "transient".the bottom part of the collector wave went below that of the base, i'm thinking the transistor should go to saturation mode, and the bottom part of the collector wave should be flattened out, but it was not, LTspice drew the complete curve.questions are:should the transistor go into satuation or not?what is invlolved in here, did i setup the run wrong?

author: Kremmen
author_rank: Super Contributor
timestamp: April 24, 2012, 06:20:32 pm
content: Nothing wrong here, at least what you are asking is OK if a bit non-obvious. Take a look in almost any BJT datasheet and you will find the value for VCEsat i.e. collector-emitter saturation voltage. It is typically something like 0.2xx volts and can be as low as .1 volts (i just tested an opto circuit where the optotransistor has .100 VCE when driven to saturation). So the VCE naturally goes well under VBE when saturated.Edit: Just for the heck of it i ran the same circuit in NI Multisim. With exactly the same result as expected so nothing wrong in your circuit.

author: 3n2323
author_rank: Contributor
timestamp: April 25, 2012, 12:38:06 am
content: Quote from: Kremmen on April 24, 2012, 06:20:32 pmthank you very much for the help Kremmen, beautiful pictures as well!i was thinking this way... suppose we:take Vc to mean, voltage at collector relative to ground, andtake Vb to mean, voltage at base relative to ground, andthe condition for saturation is, when Vc < Vb, in other words, base-collector junction is forward biased.then, when the collector curve goes below that of the base, that's when Vc is < Vb, the transistor should go into saturation, and no longer respond to signal -> constant -> flattened out at the bottom of the curve.but it is not, i couldn't figure out why,why LTspice Multisim are right, andwhy i'm wrong.please help me finding out where i made a mistake in my reasoning, thank you Kremmen and all!

author: IanB
author_rank: Super Contributor
timestamp: April 25, 2012, 01:49:40 am
content: In your circuit, the lowest value the collector voltage could reach is the ground reference, or 0 V. But in the case you simulated, the collector voltage reaches a minimum value of 2.7 V, which is far, far higher than 0 V. Therefore there is no possible reason for the bottom of the collector voltage to be flattened. It would only be flattened if you reduced the bias voltage on the base of the transistor to a much lower voltage.As it stands, you need to consider VCE(sat) of the transistor. Suppose VCE(sat) is 0.2 V. Then the lowest collector voltage would be 0.2 V (since the emitter is close to 0 V assuming C3 has a low impedance at the frequency of interest). Your minimum collector voltage of 2.7 V is very much higher than 0.2 V, so you are in no danger at all of saturating.

author: Kremmen
author_rank: Super Contributor
timestamp: April 25, 2012, 06:04:16 am
content: Quote from: 3n2323 on April 25, 2012, 12:38:06 amThanks, my pleasureQuoteOK, this is easy. If you look at the curves at the point where the signal at the base maxes and VC is at minimum, you will see that it is still over 3 volts higher than VE. Since VCEsat is typically about 2 volts or thereabouts, it means that the transistor is_not_ in saturation and there is no reason why the waveform should be distorted. But increase the signal level just a little and you will see it going into saturation and then the bottom will be flattened of course.Don't be confused by the relative voltages between base and collector, they don't define saturation in themselves. The indication of achieving saturation is the VCE reaching the component specific minimum possible value. It doesn't happen (quite yet) in this circuit.

author: 3n2323
author_rank: Contributor
timestamp: April 25, 2012, 06:54:25 pm
content: Quote from: Kremmen on April 25, 2012, 06:04:16 amthank you Kremmen, i got your point!you are saying having base-collector forward biased is merely a necessary conditon for saturation, but not a sufficient one. every book i read talks about the three operating modes, and all emphasis is on the "base-collector forward biased" condition. Vce is played down, and only mentiioned as an "oh by the way".anyways, following your suggestion, i tried it out again with a 5V input signal.it clipped like crasy. 5V, just to get the whole collector curve in the picture.in this picture, the transistor climbed out of saturation when the signal decreased to below Vc and. it went into saturation when the signal increased to above Vc, but then saturation will not necessarily happen, only when the signal kept increasing to where Vc would decrease to where Vce~=0.2V, will saturation be realized. so the saturation determining condition is really just Vce~=0.2V, and the base-collector forward biased condition is only getting the transistor heading that way with no guarantee of saturation. did i get it right this time?now, there is no abrupt transistion from normal operating mode to saturation mode, correct? if so, the two edges in this picture should still be part of the output sine wave, instead of abrupt theoretical straight vertical lines, correct?also, the bottome edge of the output wave form has an upward bulging to it. it is in phase with the signal, so it can't the transistor is still trying to amplify. why the bulge, the transistor is in saturation there, it shouldn't have any response to the signal, what is it doing there?

author: TerminalJack505
author_rank: Super Contributor
timestamp: April 25, 2012, 07:47:41 pm
content: QuoteThe bulge is due to the transistor being in the saturation region.This graph will (hopefully) make things clearer.During normal amplification the transistor's Vce is sliding back and forth on the 'load line.' If you go too far to either end you will either clip at Vcc or go into saturation.Notice what happens during saturation. Vce no longer stays on the load line. Vce basically "climbs up" that left-hand slope. This is due to the current (the Y-axis) increasing but Vce is also increasing. This is what accounts for the bulge.

author: Kremmen
author_rank: Super Contributor
timestamp: April 25, 2012, 08:42:36 pm
content: Quote from: 3n2323 on April 25, 2012, 06:54:25 pmIn saturation the base is biased above both emitter and collector that is true. The fact is however that until Vc is driven to the hard limit the device will still respond to changes in base current. I don't know if there is an "official" distinction between the saturation region as defined by comparing the voltage biases vs achieving the minimum possible Vc but for me the latter is the true saturation state. This by the way is a necessary condition to achieve minimum dissipation losses in switching applications, for obvious reason. Could be my mindset comes from there but still i would say that the device is not really saturated while it responds to changes in control input i.e. base current.The bulge in your righteously overdriven 2nd example was adequately explained above i hope.

author: 3n2323
author_rank: Contributor
timestamp: April 30, 2012, 01:53:06 pm
content: Quote from: TerminalJack505 on April 25, 2012, 07:47:41 pmthank you TerminalJack505!it took me a while thinking about this, sorry for the delayed response.i'm assruming the following, please point it out if i got it wrong somewhere:- the transistor won't be in saturation before Vc makes Vce = Vce(sat).- as soon as Vc makes Vce > Vce(sat), the transistor will climb out of saturation.- plus, the two end points of the bulge, both lower then the peak of the bulge, are the points where Vce = Vce(sat), i.e. that's where the transistor goes into and comes out of saturation.now, when Vc bulges up, then Vce > Vce(sat), why wouldn't the transistor come out of saturation right there?is the requirement of coming out of saturation Vc > Vce(sat) plus the transistor is operating on the loadline?if so, the bulge is actually the transistor sliding up the shoulder of one single Ib line, from the intersection of that Ib line and the loadline, and then back along that shoulder to the intersection, and from there on it is out of saturation and woldd be operating on the loadline again?

author: 3n2323
author_rank: Contributor
timestamp: April 30, 2012, 02:02:02 pm
content: Quote from: Kremmen on April 25, 2012, 08:42:36 pmalright, that's cool!Vc is low at saturation for sure, minimum power dissipation would also mean Ic is low as well. is this generally true comparing to active mode?and, is it true that in switching applications, we usually don't have an emitter resistor, in order to get the lowest Vc possible?

author: Kremmen
author_rank: Super Contributor
timestamp: April 30, 2012, 02:20:40 pm
content: Well i may have but it a bit loosely. You naturally achieve minimum power dissipation when there is no current at all but that is not too useful in practice.Recalling that P=UI or P=I^2R, for a given current that you want to pass through a switch you want to minimize the U (or the Vce of a BJT to be exact) or the R of the conducting channel for a MOSFET.So you want to drive both BJTs and FETs into _hard_ saturation to minimize the power dissipation of the device. For a BJT it means you drive sufficient base current to achieve the minimum possible Vce, not just that Vbe > Vce which is considered entry into the saturation region. For a FET it is the same thing: sufficient Vgs to fully open the main channel so that increasing Vgs does not further reduce the channel resistance any more. This is when both devices are fully saturated and you get the minimum power loss dissipation.The next step is to devise circuits where you can avoid hard switching and instead operate the device in a soft-switching mode. But that is another discussion for another day.

author: TerminalJack505
author_rank: Super Contributor
timestamp: April 30, 2012, 05:17:00 pm
content: QuoteThis is exactly what is happening. The graph (which seems to have disappeared) is a little confusing since the load line extends straight into the saturation region. The transistor can never actually get into this region. The best it can do is slide up and down the left hand "saturation line."It will climb up the saturation line when the transistor is in saturation and more base current is applied. This is due to the fact that more base current cause more collector current to flow which--due to saturation--causes Vce to rise.As the current decreases when the transistor is in saturation it will slide back down the saturation line. Once it reaches the point where the load line intersects the saturation line the transistor will fall out of saturation and operate on the load line.

author: 3n2323
author_rank: Contributor
timestamp: April 30, 2012, 08:36:17 pm
content: Quote from: TerminalJack505 on April 30, 2012, 05:17:00 pmman, this is great, most interesting, and solved the saturation mistery for me, i totally got you!PROBLEM TERMINATED, thank you very much TerminalJack505, you the man on this! better than many professors and books with good reviews, although you may very well be a professor too."disappearing picture" is no problem at all, i went to the original URL and it's there. many books have this IV-charateristic/load-line graph drawn in a very confusing way, where they would shade the saturation and the cutoff regions and extend the loadline into them, leaving me, the newbie, wondering about how the transistor would jump around in those regions.one follow up question though, why the following won't happen, and the transistor has to go into saturation?Vc = Ve, orVc < Veis this because the two junctions involved in a transistor act here like a voltage divider so that the above conditions would be absurd, or because of device physics? or asking from another angle, what determines Vce(sat) ~= 0.2V? voltage drops across the two junctions can only account for ~1.4V, is there something else, or it is something totally different?

author: 3n2323
author_rank: Contributor
timestamp: April 30, 2012, 08:57:14 pm
content: Quote from: IanB on April 25, 2012, 01:49:40 amthank you IanB for your help! now with the help from TerminalJack505, i could finally understand what you are saying.so Vc can never reach 0.0V, the lowest it can get to is Ve+Vce(sat), correct?it follows that the usual way of putting the Q-point at Vcc/2 is only a rough estimate; to be exactly centered, the Q-point needs to be at [Vcc - Ve - Vce(sat)]/2, correct?

author: TerminalJack505
author_rank: Super Contributor
timestamp: April 30, 2012, 08:59:03 pm
content: QuoteWell, it should be fairly obvious that Vc can't be less than Ve. Even if you shorted out the collector and emitter with a wire Vc couldn't fall below Ve. In that particular case Vc = Ve.Now, so far what determines Vce(sat), that's something I can't answer off the to of my head. Like you say, it is likely a matter of device physics. I'm guilty of not really paying enough attention to the physical aspects and treating electronic components as abstract models, I'm afraid.Someone in this forum likely knows. It probably has something to do with losses due to recombination.

author: 3n2323
author_rank: Contributor
timestamp: May 07, 2012, 12:06:21 pm
content: [quote author=TerminalJack505 link=topic=8055.msg108077#msg108077 date=1335819543...Well, it should be fairly obvious that Vc can't be less than Ve. Even if you shorted out the collector and emitter with a wire Vc couldn't fall below Ve. In that particular case Vc = Ve....haha, duh!can i continue this thread? i found a new case of a BJT in saturaton.or should i open a new thread? any one cares?

author: TerminalJack505
author_rank: Super Contributor
timestamp: May 07, 2012, 01:38:21 pm
content: You should probably start a new topic.