To Flood or Not to Flood Multi-Layer PCB Internal Signal Layers - Page 1
Forum section: electronics / general

author: gfoundry
author_rank: Newbie
timestamp: November 22, 2018, 07:26:59 pm
content: I do realize this is similar to the following post:https://www.eevblog.com/forum/projects/do-you-flood-your-pcbs/msg675048/#msg675048However that post was targeted more for simple 2-layer PCBs. My question is I'm looking for industry expertise on the following question.If you have a multi-layer PCB with X number of internal signal layers, upon routing completion of those layers and into DFM review:Do you Flood or Not Flood the "open" areas of these internal signal layers with copper?Assume designs of 8-layers and above... (10 to 14 being typical for our designs)

author: asmi
author_rank: Super Contributor
timestamp: November 22, 2018, 08:36:23 pm
content: The answer is "it depends". Signal layers' ground fills need to stay away from impedance controlled traces as nearby ground will change their impedance. Other than that it can be a good idea as fill factor can affect final prepreg thickness - again this is important for impedance controlled boards. But normally PCB fab will handle it as impedance difference is usually less than typical 10% tolerance for CI. But this will be important if you have very high-speed traces (multi-gigabit ones) as you will need tighter impedance tolerance.

author: AndyC_772
author_rank: Super Contributor
timestamp: November 22, 2018, 09:09:03 pm
content: It's not entirely clear why there would be any significant 'open' areas in a multi-layer board like that. What's the driving factor behind the layer count? Is there one particular BGA that needs all those layers to escape it properly?I don't personally flood tracking layers without a very good reason. You end up with a lot of little disconnected shapes which end up getting removed anyway, and it's not at all clear that the bits left serve a useful purpose.If there's a lot of empty space on certain layers, your PCB manufacturer may want to add thieving to ensure uniform plating. If that's the case, for the sake of consistency between suppliers, I always prefer to make the changes in the original artwork rather than ever letting a manufacturer make their own changes.If it's a controlled impedance board, tell the manufacturer the target impedance, and let them make adjustments to the stack-up and trace width to achieve that impedance. This means you don't have to worry about slight changes in board thickness and layer spacing; the impedance is achieved 'closed-loop' with the manufacturer being responsible for the end result you want to achieve.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 23, 2018, 03:13:14 am
content: No. Except for very special cases, no.In ordinary cases, myriad islands and stubs will be formed, which will resonate at random frequencies. While these frequencies may be in the low GHz, it's still a bunch of stuff that is not needed. And, as mentioned, it affects the characteristic impedance, when you do need that in a critical design.If it should be needed, the burden is adding enough vias -- through as many layers as are being paired up for it, if not a plain thru-via process -- to nail down the ends and spans of those islands and stubs. It takes a lot of work, adding stitching vias -- even if there are functions to facilitate it in some tools, it's still more geometry that you are responsible to inspect, and place and move as needed.On a 4 or 6 layer board, you're more likely to have thru-vias, which makes a terrible burden as far as trying to place stitching vias between components and traces on all layers.I suppose you're more likely to have multiple drill pairs on 8+ layers, in which case you can make some simplifications at least, but you also have that many more layers to deal with...Tim

author: fchk
author_rank: Frequent Contributor
timestamp: January 03, 2019, 08:50:44 pm
content: Quote from: gfoundry on November 22, 2018, 07:26:59 pmMaybe.1. Layer stackup must be symmetric. This includes the average copper density. If one layer has very litte copper but the mirror layer is a full plane this might cause manufacturing problems.2. Even copper distribution: I'm unsure if there might be a problem if one half of a board has a very high copper density and the other half has a very low one.In doubt ask your PCB manufacturer.

author: nctnico
author_rank: Super Contributor
timestamp: January 04, 2019, 10:30:29 pm
content: I agree with fchk. A board with an uneven copper distribution is harder to produce than a board which has a lot of copper on it. I also like to have as much ground in a PCB as possible but yes, stitching it all together takes extra work.

author: free_electron
author_rank: Super Contributor
timestamp: January 06, 2019, 05:10:48 pm
content: if you can electrically connect : flood ( taking in account all clearance rules ! impedance, voltage etc )if you can not electrically connect : apply a copper thieving structure.you want to balance the copper to avoid etching issues

author: nctnico
author_rank: Super Contributor
timestamp: January 12, 2019, 05:57:35 pm
content: I'd be careful when using copper thieving. These will act as resonators at high enougn frequencies and they'll add least form a capacitor. Most of the capacitance of a copper patch on a PCB comes from the fringe fields and not the surface area.

author: vealmike
author_rank: Regular Contributor
timestamp: January 14, 2019, 02:09:10 pm
content: So far, everyone has given correct answers. But they are all contradictory!On any layer, differences in copper density across the PCB can result in different etching speeds as the chemical composition of the etch changes. Your PCB manufacturer should fix this by stirring the etch solution. This is a problem for the PCB manufacturer, not the PCB designer.There's a similar problem with electroplating. Current density in the plating solution will vary according to Cu density on the board.Within a multi-layer board, copper on layers should be symmetrical about the board centre. If you don't do this, you're essentially creating a bi-metal spring. The temperature coefficient of expansion for the heavy Cu side will be greater than that for the sparse Cu side and the PCB will warp when you pop it through the oven.Thieving lands are an acceptable way of fixing these issues. They can be used around high speed traces but you must be careful.

author: free_electron
author_rank: Super Contributor
timestamp: January 15, 2019, 04:53:59 pm
content: Quote from: nctnico on January 12, 2019, 05:57:35 pmcorrect.the structure should use non-overlapping copper stubs.but ideally you should flood ground. And even then, if you have a long finger sticking out : tack a ground via in it on the far side ...Even planes can radiated at the edge of a pcb. ( the power/fround pair is essentially a dipole antenna at the side of the board.) stick a few decoupling caps at the edge of the boards to shunt the RF energy. , or make a ground ring on the outer layers and stitch via's through the board.