2CH 50MHz AWG based on AD9102 - Page 1
Forum section: electronics / projects

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: May 26, 2017, 05:46:01 pm
content: --- WARNING ---While I have built and tested many features of this design it is after all a prototype in the true sense of the word. The SMP and digital 3V3 supplies are not enough, I messed up the Ethernet interface and several other issues exist in the linked documents below. Please do not use these as reference designs. You have been warned.--- On with the show ---Hi All,I decided a year back to make my own AWG based on the AD9102. The main aim was to explore a few things that I had not had much exposure to in my professional career such as differential clocking and signaling.So what is it? A 2 channel arbitrary wave form generator with 10Hz steps from DC to 50MHz. I really wanted to go down to DC for some digital rf immunity tests I want to do later (even though buying a commercial ARB would have taken less time and money). It has two inputs. The first is for an external 10MHz reference source that can be used to drive the DAC's or to calibrate the on board VCXO or optional (read more expensive) OCXO. The second input is dedicated to frequency counting. Positive and Negative rails of switching power supply are trim-able via digital pots as is the XO.My original rant regarding assembly of the board is here.https://www.eevblog.com/forum/projects/brain-mud/msg1213672/Now that I have gotten past a few hurdles in this design I thought I would share schematics and some thoughts on the project. I'll drip feed stuff on this thread as I make more progress, and am happy to answer questions or take feedback.When starting out I thought "hey! why is so little information available on the web for this chip? Surely many other DIY'ers have beaten this thing to death already" The best I can make out it's 4 years old at least.Well the best I can figure is the documentation is appalling with numerous errors and contradictions. I think it is best summed up with this poor engineers experience.https://ez.analog.com/thread/35554Another reason may be the limited SRAM size of 4096 samples or the differential signaling?The best I can tell the datasheet has still not been updated. So I might have been put off unless I was ignorant of that information before I had already committed to doing the design, and here I am and happy to say it's been worthwhile.The AD9102 is the single channel version of the four channel AD9106. It has a 14bit resolution with a max clock of 180MHz giving the best case 90MHz square wave output. My design aims for the weird and hard to accurately achieve 167776160 Hz to give the 10Hz steps. However as the PLL on board can be reconfigured by the MCU you can set it up for anything you like. In fact when I first got it running the PLL was at 20MHz and generating a good looking sine wave with no problem.The chip has a few interesting things going for it. First it has a dedicated sine waves generator, a dedicated triangle wave generator, sudo random noise generator (who cares), constant DC output set to the 14 bit resolution (again who cares), 4096x14bit SRAM for DDS. The cool stuff happens with the mux section where the sine wave can be amplitude modulated with SRAM patterns or Frequency modulated.My design runs on the ATSAM4E16 Cortex M4 has RS232, Ethernet and USB (borrowed with thanks from the Atmel reference designs) and is running FreeRTOS.The current status of the project is as follows.1) Board powers up and does not catch on fire - check2) PLL locks to desired frequency - check.3) Clock distribution good - check4) SPI can talk to all chips - check5) AD9102 outputs sine wave up to 50MHz - check but it's suffering due to low number of samples at that frequency.6) AD9102 outputs SRAM AWF - check.Each output is amplified (x15) with a single THS3091 current feedback opamp converting the differential signal to single ended. Probably overkill but I was swooned by it's slew of 7300 V/us.When I first powered the device I realized my switching supply, that provides the +- 15 rails for the opamps, was more like +-18 (well outside my digipots ability to fix) so I substituted some resistors giving me about +-10Volts for reference going forward.Some basic tests with the DDS on the AD9102 give me <4ns full scale rise time. For this test the output is 50 Ohm an to a 50 Ohm load at the scope over 50 Ohm coax.. did I say 50 Ohm? The peek to peek voltage of all wave forms is 5.68V and remains flat from 100KHz up to 50MHz so I'm quite pleased with that (about 25dBm constant over the range. I'll improve on that once I nail down the SMP supply voltages.What is notable from my design is the distinct lack of a user interface. Currently that it being performed by the serial port, I might look at touch screen this and that in the future but it's not the primary focus at this stage. I just want to get a good DAC.As the only tool I have available is a 100MHz DSO I'm not able to provide any harmonics around the output signal quality and I already know they are not so hot because I have a noisy negative rail that I'm hoping to fix by replacing the suspected damaged components this weekend.. and if that does not fix it I'll be desperately posting for help hereHere is my list of things to do for the second spin of the board and things I'm not sure about.The MASW-007107 RF Switch is a lot cheaper. I put it on the boardand then noticed insertion loss goes sky high below 2GHz. So Igot scared and just went back to the HMC544A that has a flat lossto DC. Having said that we really do need exceptional performance at10MHz???Do we really need the MCU clock syncronised with the ADCs?If not then perhaps remove the AD9514 in place of the twooutputs of the LMX2582. The LMX alone has a far better jitterperformance at 47fs RMS @ 1.8GHz. The AD9514 states 225fs jitter.So I'm probably just making things worse by using it.Use BGA parts for the CPDL and ATSAM4E to save HEAPS of PCB space.Actually calculate and have a buffer for power budget. 3.3 Digital isalready exceeding it's 500mA limit and still working.. Amazing.Put a low pass filter on the DAC outputs.. the wave form will have step noise without it.Seeing as we have so much spare space and pins on the CPDL perhaps we could replace all the glue logic on the board with that as it's all currentlyco-located in or around the same area anyway.Should have put this first but just to torture those who can not read a full postThe schematics are not 100% tested and probably do contain lots of bugs that I have not yet tested. I've plastered a large and hard to ignore note to that effect on the first page of the schematic.Thanks, that's all for now.

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: May 27, 2017, 10:21:24 am
content: Here is my most basic startup sequence to get the AD9102 outputting a sine wave from the DDS. This is a key step in validating your master clock input is working and the chips on the board the correct way up.For reference thedata sheet is hereFor the clocking three interface examples are given on page 20. LVDS or PECL differential clocks or a single ended CMOS driver. I went with PECL, and anyway the datasheet is not clear on what are considered "low frequencies" where the CMOS version would work, if I had to guess I would say no more then 20MHz? No idea.My clock is coming from theAD9514distribution chip. It's has three channels. Out 0 goes to AD9102 Ch0, Out1 to Ch1, and Out2 to the MCU divide by nine. My original idea was to have the MCU clock synchronized to the DAC clocks but think I wont bother with that so much now. Anyway the AD9102 clock feeds are set as LVPECL 410mV. The AD9514 is a bit mind bending to configure as it has 11 control lines each with four possible states, I left a non placed zero ohm resister for S1 in case I needed to bump up the LVPECL from 410mV to 790mV but as it's working is not needed.OK the clock is sorted lets get to the AD9102 registers and the sine wave.The SPI interface on reset is a standard 4 wire job MSB first R/W flag, 15 address bits and 16 data bits. If you read a few registers you will start to get your first impression of how wrong a datasheet can be with lots of reset values being incorrect including some reserved bits. So for that reason I played it safe and just made it a rule to read / modify / write every register using masks to ensure I did not alter any bits I'm not supposed to.Not relevant for the sine wave but hands-up who can tell me how many bits long each sample is in SRAM and where in the 16 bit register you should put it. I'll even tell you where to look end of Table 14 page 27. If you answered 12 and 0 then you could not be blamed SRAM_DATA should read top line SRAM_DATA[15:8] and bottom SRAM_DATA[7:2].It's clear lots of reserved registers are for the AD9106 four channel version, but not all are.Onward.After power up do a hardware reset for fun, take a guess at how long you should hold the reset line low because the datasheet will not tell you.Ensure pattern generation is not running. For this disable the trigger line and clear RUN (bit 0) in PAT_STATUS (0x001E).Next configure DACRSET as I'm using the on board RSET resistor - that determines our full scale current at the output - so set DAC_RSET_EN [bit 15] and DAC_RSET = 0 [4:0] in DACRSET .In WAV_CONFIG  we select our PRESORE_SEL [5:4] = 0x3 for DDS output, and WAVE_SEL [1:0] = 1 for basic Prestored waveformSet DAC_DIG_GAIN[15:4]=0x400 in DAC_DGAIN this is for a gain of 1. The chip defaults to gain zero so if this is not set nothing will come out.Next is the two tuning word registers DDS_TW32  for 16 bits MSB and DDS_TW1  for 8 bits LSB that sets the actual desired DDS frequency generated. The actual frequency is given on page 23 as DDS_TW × fCLK/2^24 so depends on your clock. Lets just go for a 180MHz source clock and 5MHz output gives TW32 = 0x0750 TW1 = 0x0075.That's it all that's left it to run and trigger.Again in PAT_STATUS set the RUN bit, and then pull the trigger line low and hey presto a 5MHz sine wave. I neglected to mention an important concept of Shadow Registers, they are meant to allow you to make modifications while the pattern generator is running. From the datasheet.QuoteAt any rate the example for the sine wave I gave above will work from boot, but changing the tuning words on the fly seems like it can't be done without stopping and starting the pattern generator, although I'm yet to confirm that. Also the fact that I do not need to perform a ram update to get a basic sine wave at boot tends to contradict the description of how shadow registers work already.

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: May 27, 2017, 10:52:26 am
content: Attached for convenience are the register definitions for the AD9102. I have been correcting inaccuracies in the data sheet as I go but as it's not fully exercised yet I will update the attachment if and when I find any errors.The relevant helper functions for the read / modify / write are given below.Here is an example usage.Code:r = drv_ad9102_open(0, DACRSET);drv_ad9102_bit_set(DAC_RSET_EN);drv_ad9102_val_set(DAC_RSET_MSK, DAC_RSET_IDX, 0x0000);drv_ad9102_close();Code:uint8_t active_channel;uint16_t active_reg;uint16_t active_val;uint16_t drv_ad9102_open(uint8_t channel, uint16_t reg){if(channel==0) {active_channel = DRV_SPI_AD9102_CH0;} else {active_channel = DRV_SPI_AD9102_CH1;}active_reg = reg;active_val = drv_spi_read_single(active_channel, reg);return active_val;}void drv_ad9102_close(void){drv_spi_write_single(active_channel, active_reg, active_val);active_channel = 0xFF;active_reg = 0xFFFF;}void drv_ad9102_bit_set(uint16_t bitmask){active_val |= bitmask;}void drv_ad9102_bit_clr(uint16_t bitmask){active_val &= ~bitmask;}uint16_t drv_ad9102_bit_read(uint16_t bitmask){return active_val & bitmask;}void drv_ad9102_val_set(uint16_t bitmask, uint8_t idx, uint16_t val){active_val &= ~bitmask;// out with the old.active_val |= (val << idx) & bitmask; // in with the new.}uint16_t drv_ad9102_val_read(uint16_t bitmask, uint8_t idx){return (active_val & bitmask) >> idx;}[edit 1] Found an error of my own making. START_ADDR_IDX and STOP_ADDR_IDX were 5 and should be 4. Corrected in rev1 of header attached.

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: May 27, 2017, 02:28:10 pm
content: Square wave from SRAM just two full scale samples. Input frequency is 167776160 Hz, 83.9MHz out. I'm at the limits of my scope bandwidth here with 0.35 / 100MHz rise time so I'll not be able to see if it settles flat on the tops and bottoms like it does at lower frequencies.First picture is terminated in to 50Ohm.Second image is unterminated.

author: bloguetronica
author_rank: Frequent Contributor
timestamp: January 16, 2018, 12:29:02 pm
content: Nice board! The sine waves don't seem bad, but the frequency is sure to be on the limit for a 180MSPS DDS, even if you are using Sin(x)/X compensation (I bet you are).As for datasheet inacuracies, I've had two experiences such as yours, one regarding the AD9854 (corrected on Rev. C, after I opened a case), and another one on the AD9833/AD9834 (opened a case recently, but I'm still waiting for the correction to be made. Anyways, the error was pretty much the same. Where it is:- SCK idles high between write operations (CPOL = 0)- Data is valid on the SCK falling edge (CPHA = 1)It should be:- SCK idles high between write operations (CPOL = 0)- Data is valid on the SCK falling edge (CPHA = 1)Anyway, I don't mean to hijack this post. I'm curious to see the schematic.Kind regards, Samuel Lourenço

author: ogden
author_rank: Super Contributor
timestamp: January 16, 2018, 02:14:15 pm
content: I wonder why your AWG have no low-pass LC filter between DDS and output amp?

author: bloguetronica
author_rank: Frequent Contributor
timestamp: January 16, 2018, 05:23:25 pm
content: Quote from: ogden on January 16, 2018, 02:14:15 pmGood point ogden. By the looks of the PCB, it didn't seem to have any kind of filter after the DDS, but the schematic confirms it.David, I would recommend you to have a high order Chebyshev filter (Butterworth is better, since the group delay is limited, but you need tighter tolerance components). I would recommend a 0.01dB flat Chebyshev, 5th order, at least. Fc should be set to no more than 1/3rd of your sampling rate.Kind regards, Samuel Lourenço

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: January 17, 2018, 05:59:24 am
content: @bloguetronica : That must be an extremely subtle error in the AD9833/AD9834 datasheet, I still can't see itYour not hijacking the thread at all, in fact it's been dead for some time and I welcome the comments. The schematic was posted at the top of this thread but I've attached a newer revision of the schematics... the only change is a correctly wired Ethernet portThe other major issue I am yet to fix is the power supply, I did not design enough current in to it to drive both outputs at full tilt so the negative waves were being clipped.Sin(x)/X perhaps on the scope I can not recall if it was enabled but probably was, it's not a feature of the AD9102.@ogden and @bloguetronica : I did design a filter to go on the outputs but ditched it before I got the first spin of the board. The main reason for ditching it was I became concerned about the phase relationship between the two channels. if I wanted for instance I wanted 12MHz on one and 4MHz on the other then I presumed I could never get them to cross zero at the same point. Or just an expression of my misunderstanding on the topic. So figured if I built the thing I could play around with the filters later.I do need one.. to quote Primer "It's fine. It's fine. Just remember to put it back, okay? Your emissions went up like 300 percent."

author: ogden
author_rank: Super Contributor
timestamp: January 17, 2018, 01:44:01 pm
content: Quote from: David Chamberlain on January 17, 2018, 05:59:24 amFor 2 channel generator you shall have phase control for each channel anyway. This will allow you to tune phase as you wish or even do phase error calibration/correction. 4 and 12MHz is far enough from filter cutoff frequency which supposedly is slightly above 50MHz, thus phase error at given frequencies could be not that bad as you think, especially if you use quality components. Anyway it is good idea to run montecarlo simulation for flter in question and see - expected phase error spread is acceptable for you or not.QuoteYou definitely want to place filter *before* amplifier, so "add filters later" means more or less new board

author: bloguetronica
author_rank: Frequent Contributor
timestamp: January 18, 2018, 12:10:11 pm
content: David,Expect a lot of waste bandwidth, and not just because of the filter. I though that the AD9102 that Sin(x)/x envelope compensation, sometimes called sinc compensation. If it hasn't, expect a roll-off due the implicit Sin(x)/x envelope of the DAC, which will affect the higher frequencies. Of course this is not to be confused with the Sin(x)/x interpolation of the oscilloscope, which is a different subject.For instance, for a 80MSMS function generator I've designed, that had a 23MHz 5th order 0.01dB Chebyshev filter in it, I've got a 8MHz sine with a 0.1dB attenuation. Thus, in your project, expect to have 16MHz maximum with acceptable attenuation, and that is for sine waves. For more complex waves, you'll have the higher harmonics suppressed by the filter, or at least affected by the DAC Sin(x)/x envelope.As for the filter, it is better for you to implement a 50\$\Omega\$ matched filter. If the AD9102 DAC only accepts 200\$\Omega\$, you'll have to put a buffer between the AD9102 DAC and filter. You can also design a 200\$\Omega\$ matched filter, but for the kind of frequencies you want, the capacitances are small and parasitics may be a very significant factor. Doing your final amplification/buffering after the filter is a must.Kind regards, Samuel Lourenço

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: January 26, 2018, 11:46:49 pm
content: Hi, I redesigned the front end by basically following the example in the THS3091 spec sheet. I noticed this is the same topology used in some Siglent Arb as done by DaveI included the recommended 60MHz 5th order Chebyshev LPF. It gives -40dB @ 170MHz (the DAC clock) I don't know what I was expecting but perhaps a sharper roll off OR does this look about typical? I'll try increasing the order.Note this filter is 250Ohms. If I change it to 50Ohms (40.12464pF, 173.07nH, 83.67864p, 173.07nH, 40.12464pF) I get identical Frequency response to the one below.And these are not cheap, my opamp budget just increased to AU$38 per channel!!!!

author: duak
author_rank: Super Contributor
timestamp: January 27, 2018, 03:15:01 am
content: Arbitrary Waveform Generators usually have Bessell type reconstruction filters to preserve the phase relationships between the higher order harmonics. If they aren't, the ultimate shape of the waveform will be affected especially near faster transitions. Unfortunately, it takes a higher order Bessell filter to do the job of the Chebyshev.Outside of the transition region around the corner frequency all low pass filters are the same: 20 dB per decade ultimate rolloff per filter order. This appears to be a 5th order filter so it'll be 100 dB down at 10X its corner frequency. By diddling with locations of the various poles and zeroes the transition characteristics can be changed. Compare the frequency response of this filter with a 5th order Bessell and you should see what I mean. Note also that the Chebyshev has some amplitude ripple around the corner frequency. BTW, a Chebyshev filter with 0 amplitude ripple is a Butterworth.If you are able to design and build a filter with arbitrary input and output impedances, there can be an advantage in having a low input impedance, say 100 ohms, and a higher output impedance, say 1000 ohms, there will be less voltage loss thru the filter within the passband. ie., if both input and output impedances were 100 ohms, the output voltage would at best be half that of the input.Hope this makes sense,Best o' luck

author: imidis
author_rank: Frequent Contributor
timestamp: January 27, 2018, 03:35:24 am
content: Hi, just want to add some encouragement. I was just thinking I wonder if anyone has thought of taking this on. It seems doable, but a bit of effort! Don't give up!

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: January 27, 2018, 05:47:53 am
content: Quote from: duak on January 27, 2018, 03:15:01 amNo kidding, I just did a quick test to show this. But I'm not seeing a drastic improvement in the phase between the two.Thanks for the idea about increasing the output impedance I will give that a try also.For any one interested the simulator is TI's TINA I would prefer to be using LT Spice but the opamp models are only available for TINA. The filter calculator is AADE -http://w1hue.org/filter.htmlGreen trace is the Chebyshev

author: duak
author_rank: Super Contributor
timestamp: January 27, 2018, 06:57:01 pm
content: David, try doing a time domain simulation by putting in various input waveforms such as pulse, square, triangle and ramp to see how the filters respond.Cheers,

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: January 27, 2018, 09:42:53 pm
content: Quote from: duak on January 27, 2018, 06:57:01 pmThanks duak, I think I see it now.Square wave with 1ns edges , otherwise same filter schematic as my last post.

author: xaxaxa
author_rank: Regular Contributor
timestamp: January 28, 2018, 06:07:49 am
content: Quote from: David Chamberlain on January 27, 2018, 09:42:53 pmThat overshoot is more a consequence of the filter being sharper than due to the phase of the filter; in other words the chebyshev filter is "working as intended" - an ideal brick wall linear phase filter would produce that overshoot as well, since you can think of an ideal LPF as convolving the input signal with a sinc function.

author: duak
author_rank: Super Contributor
timestamp: January 28, 2018, 06:44:30 pm
content: Yep, as David's time domain responses show, the Bessel filter is still not perfect. The Gaussian filter apparently eliminates all overshoot but I've never designed one and don't know how easy it would be to realize for this application. On the other hand, elliptic filters incorporating zeroes can give some additional attenuation at some frequencies while sacrificing attenuation at others. This sort of happens anyway because the L's and C's aren't perfect and have self resonances.If memory serves the Stanford Research DS345 30 MHz synthesizer has two types of reconstruction filters. One for sine and one for arbitrary - I suppose each is tuned to give the best response for the waveform. Since the amplitude of the waveform is controllable it could be adjusted in sine mode to compensate for any passband amplitude ripple.I remember using one in 1990 or so and was quite impressed at how much it could do and how well it worked for its price and size. I looked into building one but didn't get past the understanding how it works phase.

author: bloguetronica
author_rank: Frequent Contributor
timestamp: February 13, 2018, 01:51:26 pm
content: Hi,Forgot to mention. If you are doing an arbitrary function generator, or if you expect to produce some steep signals (square waves, step ramps, etc), you are better of with an high order Bessel filter (say, 7th order or even 9th order). I think I've mislead you with my example, because my function generator only produces sine and triangle waves. Actually, the images attached shows the step response I get when forcing it to produce a square wave (by setting the AD9834 frequency to zero and by changing the phase between 90 and 270 degrees). Mind that this is a 0.01bB Chebyshev aligned filter (the closest to Butterworth), so it could be worse.Thus, any other filter except Bessel will produce an overshooting step response. Elliptic filters are even worse, Butterworth filters are simply not worth it, as you'll probably end up with a Chebyshev filter (kind of) if you use practical values. So, you could do a Bessel 9th order filter. Mind that the roll-off starts very early with this kind of filter, so an high order is a must.Kind regards, Samuel Lourenço

author: bloguetronica
author_rank: Frequent Contributor
timestamp: February 13, 2018, 03:47:37 pm
content: I've done a quick simulation, and I've seen that the Bessel is a disgrace. Not only it starts to roll-off very early, but the attenuation is very poor. I think the best compromise is a 7th, or better, a 9th order Butterworth filter.I should remark that the 5th order Chebyshev filter that I used was a bit lacking, but it was the one possible due to the lack of space on the PCB. Ideally, it should be a 7th order Chebyshev (0.01dB).See the results here:http://www.wa4dsy.net/cgi-bin/lc_filter3?FilterResponse=Lowpass&poles=9&cutoff=60&funits=MHZ&Z=50Kind regards, Samuel Lourenço

author: bloguetronica
author_rank: Frequent Contributor
timestamp: February 13, 2018, 05:18:05 pm
content: Hi,Did a simulation of two potential filters that you might be interested in. I'm using one of these on my AD9102 based AWG (in phase of prospection). The first one is 7th order Chebyshev aligned filter (0.01dB), that has the cutoff frequency defined to approx. 53MHz (the cutoff frequency of this kind of filters corresponds to the ripple amplitude, this it is considered to be -0.01dB and not -3dB). The second is a Butterworth aligned filter, with its cutoff frequency set to 55MHz (I'm choosing this one).See the results of the partsim simulation attached. I still didn't dared to simulate a Bessel aligned filter, but I guess it would be interesting too.Kind regards, Samuel Lourenço

author: bloguetronica
author_rank: Frequent Contributor
timestamp: February 13, 2018, 09:19:59 pm
content: Hi,Simulated a Bessel filter with a 55MHz cut-off. The results are quite horrible. You can see the PDF attached (ignore the Butterworth part, since the values were changed to meet Bessel filter specs as per this link:http://www.wa4dsy.net/cgi-bin/lc_filter3?FilterResponse=Lowpass&poles=9&cutoff=55&funits=MHZ&Z=50).You can use it as well as any other filter, but mind that the the attenuation at 16MHz is significant. This is even worse that the DAC envelope.Kind regards, Samuel Lourenço

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: February 14, 2018, 10:00:30 am
content: @bloguetronica, thanks for the effort, simulations and ideas. I'll get a chance to look more closely over the weekend.So you've also done a AD9102 AWG? I would be very keen to get any feedback from you on the chip itself. Despite the higher sample rate it's quite a different and perhaps less versatile chip than the AD9834.

author: bloguetronica
author_rank: Frequent Contributor
timestamp: February 14, 2018, 12:01:01 pm
content: Hi David,I've done one based on the AD9834, but I'm yet to do one based on the AD9102. However, the datasheet of the last raises many questions. For example, having a 200resistor, what would be the minimum and maximum voltages to be expected on the waveform. I'm looking for a module on eBay, but found none yet.Kind regards, Samuel Lourenço

author: Tueftler
author_rank: Contributor
timestamp: April 11, 2018, 05:20:42 am
content: Hi all,I am jumping into this interesting thread. Before losing myself in the complexity and pitfalls of the AD9102 / AD9106, I would be very grateful if you could share your experience with me and estimate if it is possible to generate an amplitude modulated signal for the following purpose?For a multi-channel detection system with digital lock-in realization, I need a programmable sine wave amplitude modulation for a programmable sine wave carrier signal with the following ranges:f_m = 1 kHz ... 1 MHzf_c = 200 kHz ... 10 MHzDoes this chip really save time and complexity over a standard high-speed DAC?In general, I see the following 3 possible solutions (with 1+2 being fully on-board solutions):1) AD9102 / AD9106 (for amplitude modulated signal?) + single-ended buffer + low pass filter + VGA (for programmable amplitude: 10 mV ... 1 V) + bias tee (for DC component) + buffer2) AD9707 (DAC, 175 MSPS, 14 parallel bits) + single-ended buffer + low pass filter + buffer3) Dual channel laboratory waveform generator (Agilent or HP or...) + coaxial frequency mixer with coaxial output to board + on-board bias tee (for DC component) + buffer ... + sync from waveform generator to the on-board FPGA (for the digital lock-in mixing)I see the following points:1) Pro: Few FPGA I/Os needed. Contra: A lot of additional components needed, elaborative programming2) Pro: Fewer components needed? DC + amplitude modulated carrier frequency can be directly programmed? Contra: Maybe jitter problems, maybe stressing the FPGA bandwidth, a lot of I/Os needed3) Pro: Pure sine waves, fast design, only one I/O needed for synchronization. Contra: No on-board solution, synchronization with wave generator maybe not ideal for the digital lock-in mixing on the FPGAFor which solution would you vote for?

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 11, 2018, 07:08:35 am
content: The AD9102 will not let you mix an analog modulation signal you would need an external mixer rendering the chip pointless.If you want to do ASK then you can use the on board SRAM patterns to modulate the DDS, keep in mind the pattern memory is only 4096 words before you have to refresh it but you can probably achieve that while it's running because of the shadow registers - BUT I have not yet tested this. (it's about 200us to refresh the entire memory space in Double SPI Write mode.)Another alternative is to program the output gain for each symbol as long as you didn't need a very fast baud rate.Probably missing the point as I do not know what "digital lock-in mixing" is, but if you have access to all that lab equipment.. why not just use the lab equipment?

author: Tueftler
author_rank: Contributor
timestamp: April 11, 2018, 08:06:20 am
content: Thanks for the quick answer!Well, the board will be used in different laboratories/environments. The installation would be much easier if everything would be "on-board". But, yeah, the convenience on the setup/installation side would probably be paid by a lot of inconvenience in the circuit design and low sine wave quality if using the AD9102/AD9106 or the DAC AD9707…Another expression for digital "lock-in amplifier" would be a digital "I/O demodulator". In principle I want do in the digital domain what the AD8339 would do in the analog domain. Here you find a short description of the digital implementation of an I/O demodulator (or lock-in amplifier in other words):https://www.nutaq.com/blog/digital-iq-demodulator-high-speed-adcand here a more detailed description:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5530615/pdf/Beilstein_J_Nanotechnol-08-1407.pdf(see Figure 3). My question here is whether it is possible to synchronize the 1 MHz (max.) modulation signal coming from the laboratory sine wave generator with the FPGA (that has a max. 200 MHz I/O clock rate) with, let's say, 1 ns accuracy in the phase?Can't I simply program the SRAM with exactly one period or a multiple of one period of a sine function? I thought the chip automatically executes the SRAM in a loop? For example: One period of a sine wave in the SRAM would result in a modulation frequency = base frequency of DAC sine wave / 4096. 4 periods of sine waves in the SRAM would result in a modulation frequency = base frequency of DAC sine wave / 1024 and so on… ?

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 11, 2018, 08:45:35 am
content: Quote from: Tueftler on April 11, 2018, 08:06:20 amSilly me yes.. See Table 31: PATTERN_PERIOD you can set this to what ever you like within the total pattern memory size and it will repeat forever.Keep in mind as everything (DDS and Pattern) clocks are derived from the master fclk you will probably want to adjust that down a bit. For example the max 180MHz input resolution of the tuning word is 10.73Hz making it hard to get spot on 10 and 1MHz, so for this reason I (and others) use a PLL derived 167772160Hz master clock for (10Hz steps output). If you don't mind only having 16 samples in your carrier ( and I'm guessing you will )

author: ogden
author_rank: Super Contributor
timestamp: April 11, 2018, 08:55:03 am
content: Quote from: Tueftler on April 11, 2018, 08:06:20 amFPGA? To achieve what exactly? - Sync to sine of external signal generator? GeezIf you plan to introduce FPGA then better just build whole DDS out of it - with IQ digital modulators, proper baseband IQ inputs and so on.QuoteYou can. But this is how you generate arbitrary waveforms, not modulate. In case you want basic FM or AM modulation then AD9102 is capable enough, just carefully read datasheet. To modulate - you use SRAM to store AM or FM modulation patterns (datasheet page #1):SRAM data can include directly generated stored waveforms,amplitude modulation patterns applied to DDS outputs, or DDSfrequency tuning words.An internal pattern control state machine lets the user programthe pattern period for the DAC as well the start delay within thepattern period for the signal output on the DAC .

author: bloguetronica
author_rank: Frequent Contributor
timestamp: April 11, 2018, 01:12:49 pm
content: Hi,I wonder if the memory depth is enough to store any waveform with decent resolution. The 4096 x 14 bit RAM seems to be very small. I haven't made my experiences yet with this chip, since the datasheet leaves a lot to be covered. All I know is:- You can set the "gain" internally. Actually, you set the waveform amplitude by changing the bit information before the DAC. As a consequence, you will loose lots of resolution for the lower amplitudes. But after all it is a 14bit DAC, so, there is no need to add an external amplitude controller (but you can do this by setting the FS current externally, perhaps by using a DAC and a opamp - I did it for the AD9834 and it worked, so I think a similar scheme would work here).- You can set the offset internally. Again, the AD9102's DAC offers plenty of resolution. Besides, an external offset would complicate things a notch.What I don't know:- What would be the amplitude of the generated signals;- Which load resistors should be used;- Why the gain can be doubled? Can't we just calibrate the FS and the internal resistors to compensate any decreased gain?- Can I use an LVDS capable oscillator directly attached (instead of using a clock distribution chip)? Can it be a 200MHz part (due to the lack of 160MHz and 180MHz parts)?Sadly, the datasheet is too terse. No example circuits. No application notes. The AD9102/AD9106 development board schematic doesn't help, either.On another tone, I hope to see this project coming into fruition.Kind regards, Samuel Lourenço

author: Tueftler
author_rank: Contributor
timestamp: April 12, 2018, 01:42:48 am
content: David and Samuel,Thanks a lot for your opinion on the AD9102 / AD9106. So, let me try to summarize the possible frequency ranges for amplitude modulation:Let's assume a clock of 200 MHz is possible. Then, I can generate a variable excitation frequency f_ex:200 kHz < f_c < 10 MHz, with delta_f_ex= 12 Hz and samples/sine_period >= 20.And, assuming the RAM increment is clocked with the master clock (right?), I can generate a variable modulation frequency f_m:50 kHz < f_m < 1 MHz, with delta_f_m = 50 kHz and samples/sine_period >= 20.Can I get smaller modulation frequencies than 50 kHz by using a different clock than the master clock to increment the RAM, or can I add frequency dividers to the master clock for the RAM?Can I set the start delay START_DLY to 0, or will there always be a delay (which would lead to awful phase noise)?ogden,You are right, it sounds like it doesn't really make senseLet me give you a bit more information about the purpose of the board. Then it might make sense.The digital I/Q demodulation is just needed to lock-in to the modulated sensor excitation. So, I am NOT doing a I/Q MODulation at all. I am just using the I/Q DEMODulation technique to build a sophisticated lock-in amplifier. (this has, in principle, be done before:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5530615/pdf/Beilstein_J_Nanotechnol-08-1407.pdf). In short, sensor engineers make use of a communication technique. Let me quickly explain what the board is going to do:Several diode sensors are excited with a high frequency (let's say f_ex=10 MHz). In order to reduce the bandwidth for the amplifiers, the excitation frequency is modulated with a lower frequency (let's say with f_m=1 MHz). The modulated sensor current gets amplified (by a TIA) into a voltage, low pass filtered and then digitalized. Now, this digitalized modulated signal voltage (1 MHz) carries itself the sensor DC/AC-signal (DC to 50 kHz). And, in order to extract this signal, I need a demodulator, ideally an I/Q demodulator, so that I can get the amplitude and possible time-variant phase shifts of the sensor signal. Please note that in this case, the modulated frequency f_m=1 MHz is actually the carrier frequency, and the DC/AC sensor signal which is modulated on top of the modulated frequency, needs to me demodulated. I hope that makes sense?Now, the FPGA (Opal Kelly - XEM7310) has only 128 I/Os (each with max. 200 MHz clock) and these need to communicate with 4 ADCs (AD9649 or LTC1750, each with 14 parallel bits and 80 MS/s) and with several high-speed controllable multiplexers. So, at the end there are only few I/Os left and maybe few data transfer capacities. But let’s assume that the FPGA can drive an additional high-speed DAC.A standard high-speed DAC such as the AD9707 (175 MS/s, 14 parallel bits) would produce almost the same result as the AD9102/AD9106? Only the digitally modulated lower-frequency sine wave would be generated with higher precision, but the data needs to be written non-stop to the high-speed DAC at 200 MHz.One way to get a better sampling rate with the 200 MHz clock rate would be to use the highly sophisticated high-speed DAC AD9172 (12600 MS/s with only a 200 MHz clock realized with on-chip frequency multiplier). But, this would probably require much more elaborative engineering than the AD9102/AD9106.So, maybe the simplest way to produce pure modulated frequencies is to use two off-board sine wave generators connected to an off-board frequency mixer whose output is connected to the board to a bias tee (for DC sensor excitation) and then to the the diode sensors. And, the modulation sine wave (max. 1 MHz) needs to be synchronized with the FPGA, in order to generate a phase-constant digital sine wave (with a lock-up table or so) for the digital I/Q demodulation.Buuuuuuuuut, I see the problem now: THE SYNCHRONIZATION. I cannot simply take the sync-out of one of the sine wave generators and connect it to the FPGA because the clock (200 MHz) is fixed, right? And, the sine wave generators that we have in the lab only have a sync-out, but no sync-in. So, for a 1 MHz sine wave (with a 1 MHz clock output of the wave generator) and a 200 MHz clock of the FPGA I would get a phase error of 1/200=0.5 %, correct? This is too much for a high precision I/Q demodulation, right? Any clever ideas what I can do? (Measuring the phase shift between the clocks and transforming into an offset for the digital sine wave generation would probably be faaar to complicated…)A compromise solution could be: Generating the modulation wave (=carrier frquency for digital I/Q demodulation, 1 kHz - 1 MHz) on the board with the DAC AD9707 or the AD9102/AD9106, and mixing it with an external excitation sine wave (max. 10 Mhz or evtl. more) via an on-board active mixer? (PS: I don't like compromises)What's your suggestion?Kind regards,Jörn

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 12, 2018, 08:54:20 am
content: Quote from: Tueftler on April 12, 2018, 01:42:48 amAD9102 MAX CLKIN is 180MHz (Table 3, page 4) if you try 200MHz no one can predict what is going to happen, something I should perhaps try.HOLD (Table 30, page 32) is the master clock prescaller for pattern memory your thinking of but it's only 4 bits wide with 0 = /1There is no secondary clock input that can drive the pattern memory.AD have a design GUI for this chip that allows you to configure many aspects with a mouse and save the configuration register file for direct upload to the AD9102/AD9106.. It helped me a lot understanding the internal flow.https://wiki.analog.com/resources/eval/dpg/eval-ad9106[ link at the end 'Download the AD9106 Update' ][ default installs to C:\Program Files (x86)\Analog Devices\HSDAC\AD9106\AD9102\AD9102_SPI.exe]If you need 100% certified answers from the horses mouth I would suggest posting a question to the AD Engineer Zone under DSP. I've seen questions here result in actual AD product engineers doing some real hard yards (running test scenarios.) so while the provided datasheet may be crap the support service here seems really good.https://ez.analog.com/search.jspa?q=AD9102 Actually while I'm at it I've often wondered what motivates AD to make a chip like this? It's not like any serious ARB manufacture is going to base their design around it (quality is not fantastic, bandwidth too low, price too high) AND silicon manufactures don't normally make chips just to keep hobbyist like me happy??? I'm wondering it it were just made as a bit of a demo chip?

author: ogden
author_rank: Super Contributor
timestamp: April 12, 2018, 09:49:33 am
content: Quote from: Tueftler on April 12, 2018, 01:42:48 amThen get another board or design one yourself. For me telling that I/O of particular board is limiting factor in "digital lock-in amplifier" project you describe, does not makes sense.QuoteMy facepalm was about fact that FPGA can doexactlywhat AD9102 does, givingsame or even better resultsrendering AD9102 superflous in the system where you use FPGA, especially if you are doing advanced stuff like phase sync, thus have capable enough FPGA which is so in case of XEM7310.Further reading:https://www.xilinx.com/products/intellectual-property/dds_compiler.htmlQuoteUsehttp://www.ti.com/product/dac5672instead.There's moreQuoteNo. Even at 5MHz sampling frequency you can sychronize 1MHz DDS phase to any imaginable precision.It's quite basic DSP. (No, I am not going to explain DSP topics here because I am not DSP expert anyways.)QuoteWhy do you need external modulation and excitation generators? Put them all in the FPGA!

author: Tueftler
author_rank: Contributor
timestamp: April 13, 2018, 01:03:10 am
content: QuoteQuoteI see a big advantage of the AD9102 / AD9106 over convential DACs, such as AD9707 or dac5672 for sine wave generation:It is simply the fact that the AD9102 has a look-up table of the sinus function already on the chip. So you just need ONE clock to drive the chip, whereas you need at least 15 I/Os to drive a DAC with 14 parallel bits. The second point is that the FPGA is "relieved" with the AD9102 because the voltage data is already written on the chip, whereas it needs to be written non-stop with to a standard DAC.A SOLUTION could be a DAC that allows to serially pre-write an array of voltages (in form of a look-up table) which is then just triggered with the clock. Does that exist??QuoteI don't see any advantage of the dac5672 over the AD9707 or even over the AD9172. Can you please teach me what is the advantage in your eyes?QuoteWell I need 4x16 I/Os for the 4 high-speed ADC converters and about 32 I/Os for high-speed multiplexer and switches (maybe more) and some for synchronisation with other boards. So there are few I/Os left. For a DAC I would need another 16 I/Os, however for the AD9102 I would need only 2-3 I/Os (clock and serial data transfer).QuoteHow to put them in the FPGA? I would always need a DAC to generate the analog sine wave for the sensor excitation. As i mentioned, For a standard 14bit-DAC, I would need more than 16 I/Os, for the AD9102 I would need only 2-3 I/Os and for an external sine wave generation I would need only one I/O for synchronisation?QuoteHow would that work? I took classes in DSP and know a bit about it. But the problem here is that both clocks (the one of the external sine generator and the one of the FPGA) are fixed...

author: ogden
author_rank: Super Contributor
timestamp: April 13, 2018, 09:42:11 am
content: Quote from: Tueftler on April 13, 2018, 01:03:10 amRight. Let's save precious FPGA resources which you are not using anyway.QuoteDAC5672 (2x DAC) = 275 MSPS, AD9707 (1xDAC) = 175 MSPS.Mouser, qty1:AD9172 = $342.43AD9707 = $16.88 * 2 = $33.76AD9102 = $23.31 * 2 = $46.62DAC5672 = $25.94I clearly see the difference, do you?QuoteYou have freaking FPGA and you are saving pins by introducing external DDS, in result getting phase sync difficulties which shall be somehow solved. - I do not get it. That FPGA on XEM7310 have 170 i/os. If not enough - get FGG484 package with 250 I/O's.QuoteI understood that signal going out of DDS is for sensor excitation. It is not? Could you please provide block diagram of what you are building?QuoteContact your DSP teacher and ask for refund? - Because he did teach you nothing.

author: Tueftler
author_rank: Contributor
timestamp: April 15, 2018, 12:35:00 am
content: QuoteSee attached figure 1 for the global circuit and figure 2 for the digital lock-in (I/Q demodulation) implementation on the FPGA (adapted from J.Beilstein).QuoteThe 200 MHz master clock of the FPGA is limiting any way. And money is not a limiting factor for this project. But, thanks for bringing up the DAC5672, I found another cool feature. That is the interleaved mode, in which only one of both DACs need to be connected to the FPGA. That way I save I/O resources, but a 100 MHz clock for a 10 MHz sine wave is probalby not good enough.So, all comes back to the AD9102 / AD9106. And, a simple idea came to my mind: I can use one channel for the high frequency wave and the second channel for the modulation wave and than connect them with a frequency mixer. In this way I don't need the modulation function of the chip.I think the AD9102 is not just a hobby-chip. It seems to be really usefull for high-end implementations where you have limited I/Os and want to unburden the FPGA processor.By the way, if the AD9102 had a clock multiplier, then it would be a perfect chip!By the way, from the total of 126 I/Os of the Opal Kelly XEM7310, about 64 I/Os are used for the ADCs, and more than 32 I/Os are used for the multiplexer and synchronization.QuoteHe teached me more than you, so farI was reading now the Artix-7 datasheet, the heart piece of the Opal Kelly XEM7310. I think the points "Mixed-Mode Clock Manager and Phase-Locked Loop" and "MMCM Additional Programmable Features" on page 8 are important for the synchronization. But, it's not getting very clear to me. Is the phase-shift timing increment the value I am looking for to calculate the accuracy of the clock synchronization? At 1600 MHz, the phase-shift timing increment is 11.2 ps. How much is it at 200 MHz?Another question: Which ADC would you take for high SNR and a variable sample rate from 1 MSPS (or lower) to 50 MSPS (or higher)?1x Quad ADS5263http://www.ti.com/lit/ds/symlink/ads5263.pdf2x Dual ADS62P49http://www.ti.com/lit/ds/symlink/ads62p49.pdf2x Dual LTC2145-14http://www.analog.com/media/en/technical-documentation/data-sheets/21454314fa.pdf2x Dual LTC2285http://www.analog.com/media/en/technical-documentation/data-sheets/2285fb.pdf4x Single LTC1750http://www.analog.com/media/en/technical-documentation/data-sheets/1750f.pdf1x Quad AD9259http://www.analog.com/media/en/technical-documentation/data-sheets/AD9259.pdf2x Dual AD9648http://www.analog.com/media/en/technical-documentation/data-sheets/AD9648.pdf4x Single AD9649http://www.analog.com/media/en/technical-documentation/data-sheets/AD9649.pdfIF receiver AD6655

author: ogden
author_rank: Super Contributor
timestamp: April 15, 2018, 08:43:20 am
content: Quote from: Tueftler on April 15, 2018, 12:35:00 amI am not here to teach you DSP basics, sorry. I can show the path and direction, but you shall walk it yourself.QuoteDDS output frequency is not tuned by changing it's sample frequency. What you shall recall from your DSP classes - how DDS works or just how sine is generated in discrete DSP. How you can generate 1MHz and 1.1MHz sine on DSP which is running at 100MHz or 101MHz, w/o changing clock of DSP core and it's DAC.QuoteDefine "high SNR", in dB. Why do you need vary ADC sample rate in FPGA application?!

author: Tueftler
author_rank: Contributor
timestamp: April 15, 2018, 09:13:28 am
content: QuoteHow can I generate a sine wave from a clock without a DAC or without PWM? Waiiiit, I think I am getting your hint now! I could simply put an AND gate and a filter behind the 100 MHz and 101 MHz clocks and, voilá, there is the PWM generated sine wave. Nice one!However, both clocks must be perfectly synchronous with an accuracy of 1 Hz or better to produce extremly low phase noise and phase drift, which is mandatory for high-SNR I/Q demodulation (see my circuit). How realistic is that?

author: ogden
author_rank: Super Contributor
timestamp: April 15, 2018, 09:20:28 am
content: Quote from: Tueftler on April 15, 2018, 09:13:28 amIt's not nice. It's dumb. - In case of DSP application which have FPGA and DAC. I asked "how DDS works or just how sine is generated in discrete DSP" and you answer - PLL + PWMQuoteVery realistic, but not using PLL of FPGA.You would want to run DSP core and ADC/DAC from fixed frequency clock of stable crystal oscillator. All the (DDS output) frequency manipulations shall be done in DSP digital domain, not by, for gods sake, changing DSP/ADC clock!

author: Tueftler
author_rank: Contributor
timestamp: April 15, 2018, 11:17:08 pm
content: QuoteI think you are losing the red line. The discussion was about producing a sine wave WITHOUT a DAC (the Opal Kelly FPGA XEM7310 does NOT have a DAC on board).QuoteOkay, let me teach you! If you only have DSP but no DAC, then you have in principle only TWO solutions for generating a sinewave:A) Extreme low-pass filtering of the square wave (clock) --> very inefficient and it is almost impossible to get a very clean sine waveB) More elegant: PWM (Puls Width Modulation) and filtering --> gives you a much cleaner sine wave, but still not perfectAny better CONSTRUCTIVE suggestion?QuoteSo, we are back to the DAC (+FPGA) solution. Here I see three options:1) DAC with serial data input --> too slow! Max. possible sine wave frequency is "clock rate / nr. of bits / 2" (here: 200 MHz / 14 / 2 < 1 MHz)2) DAC (AD9707 / DAC5672) with parallel digital input bits for signal synthesis as fast as half the clock rate of the FPGA (here: 200 MHz / 2)3) DAC and DDS (AD9102 / AD9106) --> only one clock from the FPGA necessary to increment the on-chip register where the sine wave is savedFor sine wave generation, solution 3) is more elegant than solutions 2) as the data transfer from the FPGA to the DAC is reduced by >1500 % !!This leads to the conclusion that the AD9102 / AD9106 is indeed a really USEFUL chip, especially for professional applications!However, this could be further improved. First, more flexibility would be added if the user was able to save any arbitrary wave form to the DAC chip via serial port, which is then incremented via external clock. Second, an on-chip frequency multiplier would enable synthesizing frequencies larger than the clock rate. Does such a chip exist???MfG Björn

author: ogden
author_rank: Super Contributor
timestamp: April 15, 2018, 11:33:25 pm
content: Quote from: Tueftler on April 15, 2018, 11:17:08 pmWell, I missed that you talked about DAC's just for fun and want to generate low phase noise signals using synthesized clock of FPGA and PWM. Sorry:Quote from: Tueftler on April 13, 2018, 01:03:10 amQuoteThank you for your lesson.QuoteFPGA DDS core + DACQuoteThis is not how DDS works, but whatever. Good luck, have fun.

author: Tueftler
author_rank: Contributor
timestamp: April 16, 2018, 06:35:13 am
content: I am coming to 4 possible implementations to generate the 10 MHz sine wave, amplitude modulated with another sine wave (1 kHz ... 1 MHz):1) High-speed DAC (AD9707) with 14 parallel bits (200 MHz clock), directly writing the modulated sine wave to the DAC including a DC-offset (without frequency mixing) + 4th-order Butterworth LPF2) High-speed Dual DAC (AD9717 / DAC5672) in interleaved mode with 14 parallel bits (100 MHz clock), one at 10 MHz, the other at 1 kHz + 2x 4th-order Butterworth LPF + frequency mixer at LPF-outputs + bias tee to add DC-offset3) 2x AD9102 (180 MHz clock), one at 10 MHz, the other at 1 kHz + 2x 4th-order Butterworth LPF + frequency mixer at LPF-outputs + bias tee to add DC-offset4) 2x DDS (AD9913 / AD9958) (200 MHz clock), one at 10 MHz, the other at 1 kHz + 2x 4th-order Butterworth LPF + 2x AD8330 for gain (amplitude) + frequency mixer at LPF-outputs + bias tee to add DC-offsetWhat gives the best result in terms of phase noise while not being too complicated (the price is secondary)?

author: ogden
author_rank: Super Contributor
timestamp: April 22, 2018, 08:54:42 am
content: Quote from: Tueftler on April 16, 2018, 06:35:13 amWhy use two DACs + external mixer if you can simply mix two signals in the DSP and use single DAC to output modulated signal.

author: parasole
author_rank: Contributor
timestamp: November 28, 2018, 10:59:10 am
content: Looks like the original topic was pretty much haked...David, would be interested to hear about your progress... did you produce any working firmware?

author: bloguetronica
author_rank: Frequent Contributor
timestamp: December 16, 2018, 02:10:25 pm
content: Quote from: parasole on November 28, 2018, 10:59:10 amI concur. The latest discussion does not have anything to do with the topic. I'm only interested in David's project, because I want do do some experiments with the AD9102. It is a good chip for a DIY AWG. The main plus to me, besides the good enough sampling rate, is the LUT that you can change to any waveform that you wish. Plus, you can change the amplitude and the offset without resorting to external circuitry. The weak points are the small RAM and the terse datasheet.David, any progress?Kind regards, Samuel Lourenço

author: croma641
author_rank: Regular Contributor
timestamp: July 23, 2020, 10:24:23 pm
content: Found this complete ad9102 function generrator:https://github.com/Frauschi/Funktionsgenerator

author: Aleksander Kawęczyński
author_rank: Newbie
timestamp: September 21, 2020, 06:14:16 pm
content: Hello,I have tried to build a workbench function generator on that chip. Unfortunately, the IC has many bugs in the design, and the datasheet also is not very well written.The biggest problem, that forces me to resign from using AD9102 is lack of possibility to control the output frequency of the arbitrary function stored in internal RAM.Let me summarize the problems:There is no information in the datasheet, that you need to put decoupling cap on the CLDO pin, even if they mention it on other LDO related pins. Lack of that capacitor causes instability of the whole chip.Can't control frequency of the sawtooth/triangle wave with the tunning wordPseudorandom signal luks like square wave with low amplitude and random period. Not even close to the white noise.Can't control frequency of the arbitrary function, despite datasheet suggesting, that it is possible (DDS_MSB_EN bit in DDS_CONFIG register)No clear information about the SPI mode, that you should use (Mode 0)12-bit internal SRAM, despite that DAC is 14-bit and the datasheet suggest also 14-bit RAM.I hate that chip.