First 4 Layer PCB: Traces on each layer a good idea? - Page 1
Forum section: electronics / beginners

author: soFPG
author_rank: Frequent Contributor
timestamp: July 22, 2020, 07:15:52 am
content: I am currently designing my first 4 layer PCB and I am not really sure how things are done.The project comprises a switching buck converter, an 8-bit uC, Lattice MachXO2-FPGA (32 pins) and a low end image sensor (BGA with 20 balls).The main reason why I need 4 layers is the smaller track width from JLCPCB (routing the BGA is not possible with 5mil traces). Otherwise, this could probably be done in 2 layers.So, this is my layer stack:1: Traces + GND plane (but mostly traces)2: Traces + VCC plane3: Traces + GND plane4: Traces + GND plane (but mostly traces)Does this sound like a good idea?

author: EEVblog
author_rank: Unknown
timestamp: July 22, 2020, 07:41:51 am
content: Yep, that's a typical stackup.As a general SMD routing rule you try and route everything you can on the top layer and then the rest is ground and power. Misc traces go on the bottom layer.4 layers is a luxury here, but as you say, needed for the tighter trace width tolerance for a chosen manufacturing service.

author: Wilksey
author_rank: Super Contributor
timestamp: July 22, 2020, 08:16:08 am
content: Yes, that stackup is fine, sometimes you can switch the GND and VCC plane so layer 2 is GND, but in your case it wouldn't matter.I would say keep the inner layers clear so you have a continuous GND + VCC plane, route main signals at the top, and others that won't fit at the bottom, but try and keep all clocks, power etc "sensitive signals" to the top if you can.If you have top and bottom fill of GND make sure you drop enough VIAs to stitch the planes together, don't go crazy and pepper the board with them though!I've done this for years and most of my production boards work fine and pass EMC (I say most as those were the ones I was allowed to finish, but that's another story!).

author: OwO
author_rank: Super Contributor
timestamp: July 22, 2020, 08:24:29 am
content: Better stackup would be:1 - traces + ground fill2 - solid ground plane, no traces3 - traces + ground fill4 - traces + ground fillYou want at least one completely solid plane because otherwise you need to analyze the stitching on the entire board to ensure no unintentional slots.Power planes are useless on 4 layers, and decoupling is best done by placing a large valued MLCC directly below every power pin on each IC.On a 4 layer board the planes are very distant, and so stitching is extremely important! With a power plane you need a capacitor at every stitching point, and the stitching is very imperfect because of the via distance to the capacitor.

author: EEVblog
author_rank: Unknown
timestamp: July 22, 2020, 10:26:28 am
content: Quote from: OwO on July 22, 2020, 08:24:29 amBefore the OP runs off and changes it, look at OwO's profile text that says "RF Engineer"The OP isn't even remotely close to needing anything like that.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 22, 2020, 10:42:16 am
content: Thanks everyone for such detailed and helpful repliesQuoteWhat is the theory behind that?QuoteHaha, yes. Highest frequency is 24MHz input clock for the image sensor.QuoteI don't know yet, but I could imagine that additional power traces (which is the consequence for not having a separate power plane) would clutter the top layer?

author: OwO
author_rank: Super Contributor
timestamp: July 22, 2020, 11:01:07 am
content: Quote from: soFPG on July 22, 2020, 10:42:16 amA power plane can't be shorted to ground of course, so capacitors are needed to stitch them to ground.FPGAs typically require many supplies, so you have many power networks to route. You can simply route them on the layer where your power plane would have been. You can use a local Vccint plane in the area under the FPGA, but remember it has no decoupling capability (on 4 layers) and you WILL need a capacitor for every single Vccint ball. On 4 layers the "power plane decoupling" that others here talk about so much does not really exist, and under the BGA all the planes are like cheese - each via creates a big hole in it, which means there is very little left of the inter-plane capacitance. The "power plane" under the FPGA is just a network of some thin traces and must be treated like such.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 22, 2020, 11:30:26 am
content: Power plane is questionable - in the typical 4-layer prototype process, it offers quite little plane capacitance. So despite being plane, it acts similarly to a thick power trace. You need bypass caps anyway. And as OwO demonstrates, where the plane matters (right under the components), it's pierced by the vias and isn't much of a "plane" anyway.So, routing power as thick traces, or local fills where this is easier, leaves you more routing opportunities in the same layer as you don't need to "waste" a full layer for power fill.For example, if there are no power pins on one edge of the FPGA, you can use a partial fill on the "power" layer, and then use the same layer for routing from the pins on the side with no power pins.Try to do all routing (signals and power) on 3 layers so that you can leave one layer for a complete GND plane. If you really must have 4 layers for routing, do only short routes on that one layer, so that there are no large gaps on the ground fill. Having only small gaps means via stitching is non-critical. The rest 3 layers can be routed full of traces, then.This "full ground" layer would usually be next to the top layer. So this will be your "I'm not touching this unless I feel like I have to cheat, and then I'll touch itjust a little bit" layer.Finally remember, more layers means everything should be getting easier. With a 2-layer design, you could be really struggling to get good loops for return currents. With 4 layers, if you can dedicate one layer to full GND that is, you don't need to think about this much at all, you always have access to the optimal path through a via; and you STILL have 3 layers left to do whatever routing, 2 of which aren't even hindered by the top-layer component placement. This should allow quite complex routing work already.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 22, 2020, 01:08:32 pm
content: Wow, seriously, this is so helpful!I tried routing the critical paths yesterday and it just looked awful (probably also had some component placement issues) so I thought I need some help with this and un-routed everything.I think I can start a second approach now

author: tooki
author_rank: Super Contributor
timestamp: July 22, 2020, 04:40:39 pm
content: What about dual supplies for op-amps? Is to better to dedicate a layer to each rail? Or just do a power layer with traces? Or something else? Is there even any potential advantage to doing a 4-layer board for things like audio? (And if so, what’d be the best stack-up, in terms of performance and noise rejection?)

author: Bassman59
author_rank: Super Contributor
timestamp: July 22, 2020, 06:48:40 pm
content: Quote from: tooki on July 22, 2020, 04:40:39 pmAnalog audio is easily done on two-layer boards, with a bottom ground plane and traces on top. The rails are just traces, though parts placement helps ensure that your power trace routing is rational. Certainly jump to the bottom layer for traces as needed.For something like an ADC/DAC board with analog and digital, four layers makes your life a lot easier. Top and bottom are for traces, layer 2 is a ground plane, and layer 3 is for power. For your power layer you can put pours for the rails where you need them.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 22, 2020, 08:14:53 pm
content: Any opinions on this? Tips & tricks are very much appreciated.No ground planes yet. Traces on Layer 1, 3 and 4.

author: tooki
author_rank: Super Contributor
timestamp: July 22, 2020, 09:40:50 pm
content: Quote from: Bassman59 on July 22, 2020, 06:48:40 pmOk cool, thanks! The 2-layer as you described is pretty much what I’ve been doing. If/when I get to the mixed boards like you describe, I’ll keep that in mind.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 22, 2020, 10:59:08 pm
content: Well, highest frequency will be on the order of 100-400MHz, maybe more, depending on the slew rate of pin drivers.Maximum frequency IS NOT the fundamental frequency of a given signal, it is defined by the risetime of the edge.Tim

author: EEVblog
author_rank: Unknown
timestamp: July 23, 2020, 02:33:22 am
content: Quote from: OwO on July 22, 2020, 11:01:07 amThis is a tiny piss-ant FPGA, it hardly needs belt'n'braces decoupling.Official Lattice recommendations:https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/PT/PowerDecouplingandBypassFilteringforProgrammableDevices.ashx?document_id=83740.1uF per device pin + a bulk 1uF/10uF nearby.The chip only has 2 VCC power pins on a single rail.This is bread and butter stuff, no need to consider anything fancy at all.I'd have a single 1uF bypass cap for the entire chip. Maybe a 2nd one for the IO power pins.

author: EEVblog
author_rank: Unknown
timestamp: July 23, 2020, 02:35:04 am
content: Quote from: soFPG on July 22, 2020, 08:14:53 pmThose bypass caps are all wrong. The traces are way too long. It's like you places them in the wrong rotation around the chip and then just routed them because that's what it said to do.EDIT: Oops, I mistook the image sensor for the FPGA. The FPGA is a QFP and the image sensor is the BGA. So I was talking about the image sensor bypass caps here.I might record a 2nd channel video reviewing this, as I think this layout could lead to some good discussion.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 23, 2020, 08:48:11 am
content: QuoteThank you. Now after looking at it again I notice that those traces are indeed very long and that the placement is bad.I'll try that again.QuoteYes, it's a Lattice MachXO2-1200.QuoteOkay, I forgot that 1uF.QuoteI almost forgot that. I was told the same statement before in another post. Furthermore, the fast rise times of FPGAs could lead to some problems on the receiver side (e.g. the image sensor).One mentioned solution was to use ferrite beads for each pin (if I remember correctly). I don't know if this is really necessary here.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 23, 2020, 02:21:04 pm
content: Ferrite beads for short, on-board signals aren't so important. Can be a very good idea for off-board signals though. Even breadboarding SPI over 50cm leads can find problems with signal quality. YMMV.Tim

author: Siwastaja
author_rank: Super Contributor
timestamp: July 23, 2020, 06:03:03 pm
content: I'd change to a smaller passive case size. Are those 0805 or what? The difference between the image sensor/FPGA parts and their decoupling caps is just massive. If you can handle soldering the small chips, you can definitely handle soldering 0402 caps. Then you can get them closer, right next to the pins. Larger parts usually don't fit close, forcing you to do longer routing, which is bad for power integrity, and also wastes routing space and makes routing more difficult.More balanced part sizes (i.e., use small passives with small ICs) makes the layout work easier and the result will be better as well.Use the largest C is smallest package per pin, do not add another ceramic for "bulk". If you want additional bulk, then use a considerably larger high-ESR type, like a tantalum or electrolytic.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 23, 2020, 09:57:56 pm
content: Yes, those are 0805 caps (and resistors). The time I started designing my own PCBs I bought a bunch of 0805 components and I honestly don't want to waste them.QuoteI don't know much about PCB design theory but I have a hard time imagining that 2mm shorter traces (at most) would make a drastic difference.QuoteOkay, thank you for that hint. Do you have information about why that is?

author: EEVblog
author_rank: Unknown
timestamp: July 24, 2020, 02:35:54 am
content: I have shot a video on this with layout comments, editing now...

author: EEVblog
author_rank: Unknown
timestamp: July 24, 2020, 06:03:20 am
content: Video just for you!

author: Siwastaja
author_rank: Super Contributor
timestamp: July 24, 2020, 07:00:13 am
content: Quote from: soFPG on July 23, 2020, 09:57:56 pmYou are designing in FPGAs and image sensors, in range of $10, and you are concerned about literally $0.001 parts?Don't worry, you will use your 0805 parts eventually in prototyping and projects where larger case sizes make sense.Do yourself a favour and buy a large bag of 0402 caps for <=5V power decoupling, you are going to use themin every project. 0.1uF is the classical choice but I'd suggest get a larger value, it doesn't hurt and may help if you have some special cases where a lot of IOs switch with high edge rates; or if you want to satisfy the higher total capacitance suggestion on some datasheets without using multiple different values in parallel. Contrary to common misbelief, there is no downside, having a larger C doesn't make it a "lower frequency capacitor", the decoupling capability at high frequencies is only defined by the case size, the smaller the better. It only gets worse when you go such high C values that parts are not available in the small case size anymore.QuoteWell, likely not that much, in the end. Bond wires add some 1-2mm as well so there is on-chip decoupling. It likely works just fine. But think about it that way, the chip is designed to decouple above about 100MHz internally, to cope with the inevitable ~5mm loop area (bond wires, capacitor package size, routing to that cap). Now if you add excess 2*2mm the manufacturer didn't expect, you have almost doubled the inductance the chip was designed to work with.I would do it properly, to remove or reduce the unknowns. You will have to debug things anyway and it's easier if you can trust the power source. FPGAs and image sensors likely have higher edge rates than some PIC microcontrollers, so decoupling is more critical.If using larger parts further awayhelpedyour design, I would accept the reduced power integrity as a tradeoff; maybe a stupid one, but a tradeoff anyway. But my point is, using smaller parts closer to each other will make your routing actuallyeasier, leaving more space for routing the signals, so it's a win-win. The only downside is handsoldering, but seeing you are expecting to be able to solder the small pitch image sensor and the large pin count QFP FPGA, 0402 passives are totally piece of cake.QuoteTo avoid resonances between different values of high Q factor capacitors, and, well, because there is no benefit but there is added complexity (and added line in BOM). See the recent threadhttps://www.eevblog.com/forum/projects/power-decoupling-myths/If you want to ensure that you satisfy the total capacitance requirement, just increase the C. So for example, if the manufacturer recommends 10x 0.1uF + 1x1uF = total of 2uF, instead use 10x0.22uF or 10x0.47uF or even 10x1uF. In the smallest case you can get so that they perform well on high frequencies. Now you satisfy the requirement for the capacitance, and it will be lower inductance than if you had placed a large capacitor on a fairly random place (they never specify nearwhich pinsyou should put that large cap), and you avoid resonances between the caps, and you saved a component, some board area, and a BOM line!

author: soFPG
author_rank: Frequent Contributor
timestamp: July 24, 2020, 08:57:23 am
content: QuoteThank you so much! I can't believe that's actually happeningThis helps me tremendously as I am just starting to get into more serious PCB layouts.

author: EEVblog
author_rank: Unknown
timestamp: July 24, 2020, 11:57:13 pm
content: Quote from: Siwastaja on July 24, 2020, 07:00:13 amNot such a great blanket idea. 0402's are harder to place and inspect by both hand and machine.0402 is the size where you have to have 0402 specific assembly machines (with good yield), and that can often rule out a lot of cheaper assembly houses, cheaper older production lines, backyard operators etc.I'd only use 0402 if you have to for density reasons. 0603 and 0805 for everything else.

author: EEVblog
author_rank: Unknown
timestamp: July 24, 2020, 11:58:14 pm
content: Quote from: soFPG on July 24, 2020, 08:57:23 amGlad to help. Thanks for the example.I have plenty of other PCB layout videos as well.

author: langwadt
author_rank: Super Contributor
timestamp: July 25, 2020, 12:31:07 am
content: Quote from: EEVblog on July 23, 2020, 02:35:04 amI often start layout with placement of components using a temporary netlist where the bypass caps are connected to the right pins butno connection to power, that way it much easier to see from the rast nets where the bypass caps should be

author: Siwastaja
author_rank: Super Contributor
timestamp: July 25, 2020, 06:10:42 am
content: Quote from: EEVblog on July 24, 2020, 11:57:13 pmThis advice is from 2005, maybe 2010.Today you would struggle to find an assembly house that has any problems whatsoever placing 0402. If you do find such (for example: a very large scale Chinese fab specialized in very low-tech, large numbers manufacturing), they definitely can't place either the FPGA or the image sensor, so the point is completely moot.I use 0402 everywhere by default, and this includes placement-by-tweezers and home reflow.Nowadays 0201 is the "decision point" which may limit the choice of fab and prevent using some cheapest ones, like 0402 was a decade ago.Again, layout-wise it's important to use a passive size so that a passive that connects between two device pins does not span the width of 10 device pins, blocking all nearby routing. Not only for minimized loops, but also to simplify routing work.0201 would be optimal for 0.5mm pitch devices, you could place them right next to the two pins without creating any obstacles for other routing, but 0201 is a bit tricky and iffy from the cheap assembly viewpoint, hence 0402.Many devices like FPGAs and high pin count fast MCUs easily require a bypass cap every 15-20 pins on a 0.5mm QFP. If you use 0805 on that, the bypass caps take all the space along the edges, and you need to route almost all IO through vias to other layers because the top layer is blocked. Or you need to place the bypass caps on the bottom layer, an extra assembly step when 0402 caps would simply be next to the pins.

author: Rudolph Riedel
author_rank: Regular Contributor
timestamp: July 25, 2020, 07:52:36 am
content: Just saw the video. :-)Is that a CH340 for the USB/UART converter?I would use a FT230X.Not only for the smaller package and to get rid of the crystal but also for quality.Alternatively maybe the CP2102N.

author: -gb-
author_rank: Contributor
timestamp: July 25, 2020, 10:01:21 am
content: Greetings from Germany,could you upload the Schematic please? I would give it a try.Oh and generally:How about a little forum-layout-contest?Dave defines the components and uploads a schematic. Then everyone can try and afterward it will be discussed. Oh and it would be possible to define different design-goals. One can optimize for area, price, lower layercount, handsolderability, ...

author: Neilm
author_rank: Super Contributor
timestamp: July 25, 2020, 03:27:38 pm
content: Quote from: EEVblog on July 24, 2020, 11:57:13 pmIf you are designing for large scale manufacturing you may not have a huge choice - I have found over the last few years that even 0603 are becoming expensive as manufacturers are concentrating on the smaller packages making 0603 harder to get. This is really noticable if you use 1206 reistors for power / voltage requirement.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 25, 2020, 09:25:33 pm
content: QuoteYes.QuoteThere are other variants of the CH340 series which also don't need an external crystal. Not so sure what you mean by "quality". CH340 ICs are used in a lot of Arduino clones for programming (so at least there is some kind of reliability).I am using the CH340G variant as I have it laying around and I don't want to buy new ICs if there really is no point besides "Nice to Have".QuoteHiQuoteUnfortunately, I am using Wuerth Electronic's Altium libraries for some of the parts and I don't know if I am allowed to re-distribute them.If I am thinking about how much it would cost to hire an expert PCB designer per hour to help you with your PCB project (actually I don't know but it would probably be several hundred $) it becomes even more apparent how much value the video from Dave has (for me)!

author: -gb-
author_rank: Contributor
timestamp: July 25, 2020, 10:20:07 pm
content: QuoteOK, but a Screenshot from the Schematic would also help. I just want to try how much this board can be optimised and if it can be done as a 2 layer board.One point Dave did not discuss is the dcdc, the traces in the area look a bit too thin.

author: asmi
author_rank: Super Contributor
timestamp: July 26, 2020, 02:06:17 am
content: Quote from: EEVblog on July 24, 2020, 11:57:13 pmThat is absolutely not true nowadays. Maybe it was so a decade ago, like was said above, but these days 0402 is the default size for pretty much everywhere, except where other packages are required for one reason or another. And $200 stereo microscope makes manual placement of these a non-issue, unless you have really shaky hands. Heck I even place and solder 0201s manually, and even though it's kind of PITA compared to 0402, they have some important advantages which makes them indispensable in some cases.

author: asmi
author_rank: Super Contributor
timestamp: July 26, 2020, 02:13:56 am
content: To OP: Remember this once and for all times - 4 layer board has TWO signal layers, not three or four. You can snake a slow trace or two on a power plane layer in a pinch, but otherwise these two should be left alone for power/ground.Also - get you priorities right. First you place everything, then you route important traces first, and power is never an important trace (because you have power/ground planes, so all it takes is to drop a via, and you're done). Bypass caps have to be as small as you dare, and placed as close as you can to the power pins. The capacitance value of these caps is not that important, the package size is everything!0402 passives can be bought at LCSC for like 5-10$ per reel of 10k components, so they are effectively free.

author: winniethepooh_icu
author_rank: Contributor
timestamp: July 26, 2020, 03:28:34 am
content: Quote from: EEVblog on July 22, 2020, 10:26:28 amYou are absolutely incorrect. The words "buck converter" in Owo's post should have been a clue.Don't discourage people from exploring the right way to do something by posing as an expert in something which you are not.

author: james_s
author_rank: Super Contributor
timestamp: July 26, 2020, 05:15:03 am
content: Quote from: EEVblog on July 24, 2020, 11:57:13 pmI've accidentally bought 0402 parts a few times and they're indeed tiny. You sneeze and they fly off the table never to be seen again. Trying to assemble by hand is like trying to solder a grain of sugar to the board. 0603 is a nice size though, still compact but not so small that you can't pick it up with tweezers or see what it is without a magnifier.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 26, 2020, 08:39:22 am
content: Quote from: -gb- on July 25, 2020, 10:20:07 pmIt can be quite certainly done with 2 layers. But as I have said, JLCPCB's 2 layer process doesn't allow for thin enough traces to route the BGA.Quote5$ for each value doesn't sound free to me. Also, there is no way I'll use 10k components.Why is everyone getting crazy about 0402 components if it makes norealdifference?P.S: I already bought 0603 LEDs because I ran out of 0805 onesQuoteI got contradicting answers at the beginning, this is why I routed it like that in the first place.

author: mariush
author_rank: Super Contributor
timestamp: July 26, 2020, 09:04:04 am
content: Was the switching regulator really necessary in the first place?How much current is the macho2 consuming? I see the camera sensor say up to 20mA, the microcontroller should be something like a few mA, if I were to guess that fpga shouldn't eat more than 100-250mA or so.Seems like you could have managed just fine with a 250-800ma ldo on the board, bringing 5v down to 2.8v will not be really efficient but do you really care? you'll just have half a watt or something like that wasted as heat ... you have plenty of pcb space to dissipate that heat.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 26, 2020, 09:06:48 am
content: No, probably not. But this is one of the things I want to test with this board. I plan to eventually use larger FPGAs and I want to have a working switching power supply when I start with that design.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 26, 2020, 09:23:44 am
content: Quote from: asmi on July 26, 2020, 02:13:56 amTrue, but OTOH, if you don't need controlled impedance on all routing layers, and don't have high-speed edge rates, you can treat it as three signal layers. Then you have only one pair where the ground layer is "right next" allowing impedances between 50-100 ohms without massively thick traces, and 2 of the signal layers are "lower speed" layers, with the respective ground layer quite far away. But it's still just about a millimeter or so; these "slow" layers are then equivalent to what you have in the sole signal layer of the plain old double layer design when you use one side as a ground plane; quite good actually!This 3 signal layers, 1 ground layer is still massively better than trying to have some clever routing on all 4 layers, accidentally (or purposefully) chopping up the sole ground plane.And it so happens, you tend to come up with all sorts of low-speed control signals, once you have already routed most of the board. Oh, that power supply enable signal! Oh, and that gate driver enable! What about this status LED and we needed one more pushbutton we forgot completely. Input battery voltage must be measured for safe auto-shutdown, forgot about that one. Oh and that I2C temperature sensor we completely forgot to route.Borrowing the 3rd layer for that routing is sometimes a time-saver.So if the budget prevents a 6-layer board, and the designer (or beginner, in this case) struggles doing the routing on just 2 layers of the 4-layer board, I would not hesitate to recommend borrowing the third one for routing. Of course, for critical high-speed signals, be extra sure there is a plane right next to these signals (not 1mm away) and use calculator tools to determine the trace width to get the required impedance, even approximately.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 26, 2020, 09:37:32 am
content: Quote from: soFPG on July 26, 2020, 08:39:22 amYou really need onlyone valuefor 99% of the bypass work. 0402, at least 100nF, can be up to 1uF, X7R or at least X5R, 10V is OK. You can buy just some 500pcs, but 10000pcs may cost the same or $1 more, it depends.This will be the part you will sprinkle everywhere, no need to buy many different sizes. If you come up with some IC which requires larger capacitance for some reason, you can just put a few in parallel. You have a simple and predictable BOM, and the fewest number of different components to stockpile! And you don't forget to buy the bypass caps for the project if you always use the same part.Your existing part collections with many different sizes of 0805 parts are not wasted, they are useful for everything else than basic <=5V IC bypassing, where you need different sizes. Here, you need fairly low number of each size, so no stockpiling full reels.Similarly, you may want to have one "generic pull-up/pull-down resistor" 0402 10kOhm or so, and one "generic series termination resistor" 0402 47ohms or so. These are parts you may end up using in quite large numbers, depending on what you are doing.QuoteBut it makes awhole lotof difference, as explained carefully.Dave giving very outdated and thus wrong advice sidetracked this discussion, and every time part size is discussed, someone who has problems handling small parts pops up. It's a meaningless argument; the only one who can definitely answer that is yourself. Try it. Give it a few good shots.If you can't handle 0402 parts (most can), that's understandable, but you should give it a shot because it will make everything just easier for you, and the result will be better as well. The smaller parts you can handle, the easier the routing given some final size constraints and electrical constraints, and the bigger selection of components, especially modern ICs that make design work much easier by solving problems for you, are available.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 26, 2020, 09:44:52 am
content: QuoteOn the previous page, you said:QuoteQuoteI want to hear the answers. Sorry if my reply sounded rude. It was just based on your reply a day ago.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 26, 2020, 09:48:17 am
content: Read the rest. I replied that I expect your layout to perform likely "good enough" power integrity and EMC wise even with the 0805 caps with nonoptimal routing, but you increase your margins by doing better work, and what's most important,you make your own life easierwith a smaller part, routed closer. You will see it at the latest when you have a QFP, you place the caps on the top layer, and you have first placed those caps, and then start to route the rest of the signals going to the QFP! Try it with different cap sizes.The key is, your design does not suck, but there is still room for improvement. Hence you get comments about things that are not super-critical but are still meaningful.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 26, 2020, 09:57:53 am
content: Thank you, it's just hard for me to bring all the different information from different people together. Some are saying, 0805 is okay, others are saying 0402 is necessary. Some are saying you have to have a power plane on a 4 layer board, others say it's not necessary.I get the point that routing is easier with smaller parts. I guess I have to read a book about that.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 26, 2020, 10:02:11 am
content: When in doubt, try things out. Yes it will take more time, but you will get a better understanding.Getting completely accurate and totally non-conflicting information would be nice, but it's impossible because there is no single correct solution to everything. Everything depends on something.

author: EEVblog
author_rank: Unknown
timestamp: July 26, 2020, 11:12:10 am
content: Quote from: Siwastaja on July 26, 2020, 09:23:44 amYes, that is quite common to do. Same with other layer counts like 6 to 8, 8 to 10, etc. Just lay what signals you need to on the power plane layer and then flood fill the plane in as the last step.

author: EEVblog
author_rank: Unknown
timestamp: July 26, 2020, 11:15:03 am
content: Quote from: soFPG on July 26, 2020, 09:57:53 amAnyone who is saying you need 0402 bypass caps for this design is not being practical, that is demonstrably wrong advice.QuoteAgain, not necessary for this design. But there is no need to route signals on the power plane in this design, you have a ton of room.

author: EEVblog
author_rank: Unknown
timestamp: July 26, 2020, 11:18:00 am
content: Quote from: Siwastaja on July 26, 2020, 09:37:32 amWhat part of my advice was "outdated and wrong"?Youdo not need 0402 for this design. 0805 bypass caps will work just fine. I'd bet a large sum of money on it.I'm not saying don't use 0402 parts, I'm just saying that youdon't have to.

author: EEVblog
author_rank: Unknown
timestamp: July 26, 2020, 11:19:35 am
content: Quote from: mariush on July 26, 2020, 09:04:04 amYes, I would also be questioning the need for that.EDIT: Ah, read your reply. Fair enough.

author: balage
author_rank: Regular Contributor
timestamp: July 26, 2020, 11:36:00 am
content: Dave noticed why big crystal is put on the PCB. Actually I am now designing a PCB on which (almost) everything is SMD. Trying to make as dense as I can.But I have not found a 4,096MHz crystal only the regular low profile one. Maybe soFPG didn't as well. Maybe size depend on the freq.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 26, 2020, 12:00:04 pm
content: Quote from: EEVblog on July 26, 2020, 11:18:00 amThe claim that assembly would cost more, or you would need to find a specific assembly house to do the job, is wrong. This is not the case anymore, haven't been for years. Obviously, $1000 DIY P&P machines may have problems doing it reliably, but the same machines struggle with doing even 0603 or 0.5mm QFP reliably, or work at all without glitches, so are pretty useless.The claim that 0402 is difficult in prototyping is not wrong per se, just quite iffy because most people I have dealt with (many beginners), especially younger people, have absolutely no problem after the initial shock; it's highly personal. One needs to ignore the Internet comments on this specific matter, and honestly try before deciding for themselves.Obviously, you are correct that youcando the job with 0805. You can do it with 1206 or even THT disc ceramics, very likely. You can also do it with 01005 parts. 0805 being "practical" in this case, I almost disagree. It's quite far from being a good match. It's acceptable, yes.As we already have a design which does not have any show-stopper problems, it should be obvious we are discussing optimizing the design so that the future designs can be even better - better being quicker time-to-market, lower cost, less EMI, larger power integrity margins, etc. The capacitor package size hence is not critical. I thought this would be obvious.Small components tend to pay off even if miniatyrization isn't strictly needed, because more often than not, you arestilllimited to a certain fixed maximum dimension, and saving space on frustrating necessary but "extra" parts like bypass caps, pullup/series resistors or point-of-load voltage regulators saves that space for other things. My initial prototypes often have many tightly packed modular areas, with empty area inbetween, so I can move the modular sections for the final product without having to reroute half of the board as would be the case if I had filled the board evenly with maximum size of components for "easy assembly". And it's quite typical a few modifications or additions come up, so it's nice to have some real estate free at that point.So well yeah, if I have a massive D2PAK 100A FET, having a 1210 cap next to itmakes sense; I likely need large capacitance there, and the component sizes are balanced.But if I have a 0.5mm pitch BGA, say an imager chip or an FPGA or modern MCU, I definitely do not put a 1210 cap next to it, nor do I use a D2PAK voltage regulator to supply 10mA of 3.3V for it, I use the smallest regulator package I can deal with without extra cost / extra struggle, and currently that is 0.5mm pitch parts, and 0402 for passives.

author: tooki
author_rank: Super Contributor
timestamp: July 26, 2020, 12:12:18 pm
content: Quote from: balage on July 26, 2020, 11:36:00 amThen you didn’t look very hard. Digi-Key alone has 14 different 4.096MHz SMD crystals in stock right now.(Note that Dave didn’t say it was big, he just said it was odd that it wasn’t SMD.)

author: EEVblog
author_rank: Unknown
timestamp: July 26, 2020, 01:41:00 pm
content: Quote from: Siwastaja on July 26, 2020, 12:00:04 pmI know for afactthat places that do hand assembling (very useful for small and or quick turn runs) often charge more for 0402's as they are more fiddly.I also know for afactthat many assembly houses will ask for more spare 0402 parts over larger ones due to a larger loss rate.I also know for afactthat many assembly houses will have older lines that can do 0402's but they hit higher loss targets with 0603 and above.Just because you are not dealing with these places does not mean they do not exist.QuoteEnd of discussion.QuoteGlad you agree.QuoteIt is obvious.QuoteThe 0.5mm pitch BGAis requiredfor technical reasons. Matching tiny size 0402 capsmay not berequired for technical reasons. if you don't have a required technical reason and you just want to use 0402 "just because", then knock yourself out. But don't say it's wrong or "outdated" to use larger parts in this case when clearly there is no obsolete technical requirement to do so.

author: dietert1
author_rank: Super Contributor
timestamp: July 26, 2020, 02:00:10 pm
content: Some years ago for a board shrink we replaced a conventional 6 MHz crystal from EPSON in a 6 x 3 mm can by a much smaller 4 MHz Murata ceramic resonator. Those are usually much better than their specification and perfect for many applications. I remember in my research i also found a Swiss company offering very small 4 MHz crystals (true crystals) with a different resonance mode, but that was a specialty product and expensive in comparison.Regards, Dieter

author: asmi
author_rank: Super Contributor
timestamp: July 26, 2020, 02:01:44 pm
content: Quote from: EEVblog on July 26, 2020, 01:41:00 pmEasy. Just don't use these ancient places, so they will upgrade or die. There are plenty of others who don't do this shit.

author: asmi
author_rank: Super Contributor
timestamp: July 26, 2020, 02:07:44 pm
content: Quote from: Siwastaja on July 26, 2020, 09:23:44 amThe problem with that approach is not only the lack of ground plane, but also close proximity of 3rd and 4th layers (prepreg typically is very thin), which leads to broadside coupling and consequently serious crosstalk. This is especially so since FPGA IO cells typically have very sharp edges (because they are designed for high speed).Also, since OP is saying this project is a testing ground for higher-end design, it's best to learn the right way of doing things right from the get go. Doing this shit for hi-speed is going to bite you in no time flat.

author: balage
author_rank: Regular Contributor
timestamp: July 26, 2020, 02:33:04 pm
content: Quote from: tooki on July 26, 2020, 12:12:18 pmHere they all need the same footprint area:https://www.digikey.com/products/en/crystals-oscillators-resonators/crystals/171?k=&pkeyword=&sv=0&sf=0&FV=69%7C409393%2Cmu4.096MHz%7C2150%2C-8%7C171&quantity=&ColumnSort=0&page=1&stock=1&pageSize=25So blueskull has the truth; the frequency limits the size:Quote from: blueskull on July 26, 2020, 11:42:54 am

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 26, 2020, 05:19:03 pm
content: I have no problem finding watch crystals in even smaller packages...Tim

author: tooki
author_rank: Super Contributor
timestamp: July 26, 2020, 06:02:42 pm
content: Quote from: balage on July 26, 2020, 02:33:04 pmAs I said right in my reply to you:Dave did not comment on the size of the crystal.He commented on it being through-hole and not SMD. SMD ≠ smaller!!! (SMD is often smaller, but it’s no requirement.)

author: asmi
author_rank: Super Contributor
timestamp: July 26, 2020, 06:18:53 pm
content: Quote from: tooki on July 26, 2020, 06:02:42 pmI would add that in most cases crystal can be replaced by MEMS oscillator, which are much smaller, so their higher price will be offset by PCB area savings in tight designs. This is especially so for 6+ layer boards, as they get rather pricey with size increase, so there is a strong incentive to pack things as tight as possible. Yet another reason to choose 0402 over larger packages

author: Mattylad
author_rank: Regular Contributor
timestamp: July 26, 2020, 09:46:53 pm
content: It's been a few years and apart from what Dave has said:If those capacitors are MLCC and they are at the edge of the board then they are at risk of being cracked during handling, especially if the board is clipped into a plastic molding.Moving them further away from the edge and being perpendicular to the most likely direction of flexing is better.The caps/resistors above 33 IC on the right - what the hecks going on there?Your tracks are going through too close to the opposing nets pad, if you have to go through the middle of a components pads (and you often do not on this board) then at least go through the middle.I guess we all look forward to the next version after you have taken all the comments into consideration.

author: EEVblog
author_rank: Unknown
timestamp: July 27, 2020, 12:08:08 am
content: Quote from: asmi on July 26, 2020, 02:01:44 pmAncient?You do know that even the most modern PnP machines have heads that have an 0402 threshold, right?https://www.hawkerrichardson.com.au/images/resources/Electronic_Production_Equipment/Surface_Mount_Machines/SEBMB16400-00_ZTAR_E.pdfCertain lines might already be set up for the larger component heads etc.And because these machines are huge investment, there are still tons of older machines that potentially give better yield for parts larger than 0402.At least it's potentiallysomething to consider.And there is nothing at all "ancient" about hand assembly for short runs.Again, if you have no technical or other requirement to go 0402, why do so? "Just because"? Ok, knock yourself out.

author: -gb-
author_rank: Contributor
timestamp: July 27, 2020, 02:20:55 am
content: Greetings again. So i gave it a try. I needed just one trace on another layer. Layer 2 is GND, Layer 3 in 2V8.Yes, right i did not length-match but ... the whole pcb is 2" x 1" large, the traces from the Imagesensor are <<5 cm which is < 200 ps. In comparison the Clock is 24 MHz max.All passives are 0603 except the 1uF (0805), the two 22uF (0805) and the inductor (1210). The crystal is now smd 3.2mm x 2.5mm.Very thin traces were only used when necessary.Good night from Germany/Bavaria.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 27, 2020, 03:46:31 am
content: Quote from: -gb- on July 27, 2020, 02:20:55 amGood effort!The long trace wrapping around the SOIC pad, I think I would've just routed straight line; two vias added, who cares, shorter trace length.I think the bypassing and vias I would've done slightly differently, just more consistently really I think -- the QFN20? is fantastic, lots of grounds and vias and bypass caps right there. The FPGA, the top-right pins (the two mismatched caps) have lots of vias, more than needed really, but well bypassed and tied to plane. The other four bypasses (or pairs) are weaker, with only 1-3 vias each.Hrm, I guess it hasn't been mentioned yet, but a TVS on the USB would be a good idea -- deals with hot-plugging the +5V, which the bypass cap can multiply and may not be the healthiest for the regulator or whatever's wired to the header. Can be a pass-thru type that includes filtering, series resistance and pull-up/downs for the USB pair too (if the USB interface needs it; obviously not in this case(?)), or just the one diode.Of course ESD protection, and series resistors, should be placed on the FPGA-to-header traces, if employing this degree of hardening. Maybe ferrite beads or other filtering too, suitable for application. Not really important until it becomes a quantity product, in which case those headers might disappear anyway.The nearly single layer layout gives an even more interesting potential, that it could be 2-layer; again the JLC limitation pops up, but there are other and better fabs out there, come on...In that case, the 2.8V can be routed point-to-point on the bottom (mostly), and theamplebypass caps will cover things just fine. One or two lossy bulk caps should be added at the end of the 2.8V route, to terminate the PDN. Top and bottom ground poured and stitched.Also with a 2-layer design, I think I might prefer to put more signals on the bottom side, at least just for escape -- that way the top copper, and +2.8V, can have better access to power pins. The added trace length is inconsequential.Alternately, or, probably jointly, really: bypass caps can be removed, for example the bottom three VCC pins on the FPGA can probably all run from the same subnet with just one cap shared between them, and similarly for the top group. The supply ripple would increase only marginally (unless I'm very wrong with my guess at current draw of these chips!), and that can be dealt with, externally, by putting extra filtering around the I/O (USB and headers?). A cost optimization that's rare enough in production, but likely doable if it were to come up.0402s (or smaller) would of course also come up in production, and yeah, anyone who's going to charge more to assemble cheaper components, they just don't win the quote, duh.Also, er... the lack of designators (silk), which makes talking about this rather difficult!(Unless that was just turned off for clarity? Except kinda not, y'know?, but whatever.)Tim

author: james_s
author_rank: Super Contributor
timestamp: July 27, 2020, 04:01:10 am
content: Quote from: EEVblog on July 27, 2020, 12:08:08 amThere is another factor worth considering, at least for decoupling applications. It is reasonably well known that MLCC capacitors lose capacitance when there is DC across them and I recall reading that this is largely dependent on physical size. A physically smaller capacitor will lose more capacitance than a larger one, all else being equal.

author: KE5FX
author_rank: Super Contributor
timestamp: July 27, 2020, 04:07:42 am
content: Quote from: EEVblog on July 27, 2020, 12:08:08 amWhen component shortages hit the MLCC sector, as they did over the last couple of years, the manufacturers focus on smaller parts that their customers use in volume. 0603 MLCCs were getting very hard to find for a while, never mind 1206 and 0805.The truth is that there are more MLCC form factors than the market really requires. 0603 should probably just go away. 0402 occupies a sweet spot between size, performance, and cost.And yes, any assembly house that can't deal with 0402, or that charges more for doing so, isn't worth considering under any circumstances.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 27, 2020, 08:47:13 am
content: QuoteJLCPCB is pretty much the cheapest with the best capabilities. The only other one with slightly better tolerances is WellPCB but they would charge 30$ for 5 pieces + expensive DHL shipping to Germany.No reason why I wouldn't choose 4L JLCPCB for 5€ + 5€ shipping.QuoteThanks, very good layout. I guess I need (a lot) more practice. But what I probably should have mentioned is the M12 mount for a lens which makes placement of components slightly more complicated.

author: -gb-
author_rank: Contributor
timestamp: July 27, 2020, 10:12:45 am
content: QuoteIndeed, practice can and should only be replaced by more practice.QuoteDo you have a link for the footprint? With double-sided-load the board can be shrinked to the size of the lense mount + headers and usb. I would try an area-optimised version.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 27, 2020, 12:38:09 pm
content: Only in Altium Design Format. Don't know how easy it is to convert to Eagle.

author: asmi
author_rank: Super Contributor
timestamp: July 27, 2020, 05:05:55 pm
content: Quote from: EEVblog on July 27, 2020, 12:08:08 amI do hand assembly myself, and have exactly zero problems manually placing/soldering 0402s. My recent customer's board had over 200 of 0402s, and I didn't have any troubles with assembling it manually. It was on a larger side, but typically my board would have 100-150 of 0402s and even some 0201s for FPGA decoupling. Once you practice a bit (and with right equipment), they are just as easy to place as any other parts.Quote from: EEVblog on July 27, 2020, 12:08:08 amI go for 0402 because 1) they are cheap, 2) they occupy small PCB area, and 3) they are great for decoupling. By now I have quite an extensive inventory of various 0402 parts, as I buy them by reels (because of 1.). I only go for larger package 1) when value/voltage rating is too large for 0402, 2) when resistor's power dissipation exceeds what 0402 can handle, and 3) when I know in advance I will need to repeatedly desolder-resolder parts during bring up (like feedback resistors for DC-DC converters) - this is because 0603 and larger usually have markings on them, while 0402 almost never have it. In case of 3) I use 0805 just because I happen to have 1% resistor kits of that size with a ton of different values, which I bought a long time ago. If it wouldn't be for that, I'd probably go for 0603 now - again, for markings.

author: -gb-
author_rank: Contributor
timestamp: July 27, 2020, 06:16:07 pm
content: Hello again (-:QuoteDone.- passives 0402 mostly- removed planes under the inductor- doublesided load- 0.9" x 0.6"- changed the usb IC to CP2102N- removed some Rs and Cs in the case where two supply pins are next to each other, used larger cap values instead (100n -> 1u).- sensor on underside, with mount shown. center of the sensor area is in the center of the pcb/M12 lense mount. see:http://www.zokete.com/storages/images/files/GC0307%20CSP%20SPEC%201.6.pdfFeel free to use and discuss.

author: asmi
author_rank: Super Contributor
timestamp: July 28, 2020, 12:40:11 am
content: Quote from: -gb- on July 27, 2020, 06:16:07 pmYou will probably want to pull USB connector closer to the edge so that the line marked "PCB Edge" would actually be on the edge. Otherwise looks good to me on a first sight.

author: EEVblog
author_rank: Unknown
timestamp: July 28, 2020, 03:08:24 am
content: Quote from: -gb- on July 27, 2020, 06:16:07 pmWhy go to double sided load?Sure, if you need the form factor or electrical requirements, fine. But you didn't seem to need it before, so why now?Fine if it's a one-off or low volume run of course, not big deal. But you usually don't just go to double sided load for no reason.

author: EEVblog
author_rank: Unknown
timestamp: July 28, 2020, 03:16:18 am
content: Quote from: asmi on July 27, 2020, 05:05:55 pmAssembly houses that offer hand assembly services have highly optimised time/cost processes and will often charge a premium for 0402 parts.Why? Because they have actually run the metrics and got the data on how long it takes. Smaller parts are more fiddly and take more time.Look, I'm not anti-0402 or saying that it's not easy, I'm just pointing outfactsas I have seen in the industry, and youmaywant to consider that when choosing 0402 parts.Again, just because others have not encountered this does not mean there is nopotentialpenalty for going to 0402 parts.And saying "well, just don't use those companies that charge more for them" is entirely missing the point that such cost differences exist for practical reasons.Assembly companies are infamous for doing whatever you want and secretly hiding the cost from you. They won't tell you you are secretly paying a premium for 0402 parts, or that piss-poor panel layout, or *insert any other production related thing here*.

author: asmi
author_rank: Super Contributor
timestamp: July 28, 2020, 03:52:22 am
content: Quote from: EEVblog on July 28, 2020, 03:16:18 amAs long as the quote's bottom line is in line with what I think it should be, and it's within my project's budget - I'm OK with that and don't really care to read them justifying each and every cent in the quote. I don't race to the bottom with my products, so I don't need to shave every cent off the production cost, the quality is more important that price (up to the point of course). Pretty much all of my boards are at least 4 layers, with 6 layers being the most popular, so PCB area savings provided by miniaturization are important, which is why Ipreferparts in BGA packages (as long as ball pitch is reasonably large to not require HDI) over QFPs (because latter are much larger, sometimes over 2x size, for example in my latest project I chose to use STM32H7 in BGA240+25 package as opposed to QFN208, because latter is exactly 4 times the area - 28x28 vs 14x14). Same reason I don't even think about limiting myself to a single-sided loads. I also order my production boards at WellPCB as opposed to JLCPBC, because while being a bit more expensive, they providemuchbetter PCB quality.But perhaps I'm in a minority here, because most of my boards are rather expensive, with BOM costs of a single board being in the 100s of dollars, sometimes quite a few 100s actually, encroaching on 1000$. For example, if you take a look at the FPGA board project in my signature - that is a very simple project by my standards, and quite inefficient in terms of PCB area utilization - because I designed it for hand assembly by people who perhaps are not as experienced with hand assembly as I am, and I wanted to keep full cost under $100 for PCB production + 1 hand assembled board. BTW if you are looking for material for your next PCB review - I would love if you review that board, as I'm always looking forward for constructive criticism and ways to improve. It's an open source and open HW project, so everyone is free to use it however they see fit.

author: EEVblog
author_rank: Unknown
timestamp: July 28, 2020, 04:23:32 am
content: Quote from: asmi on July 28, 2020, 03:52:22 amWhat board are you referring to?

author: asmi
author_rank: Super Contributor
timestamp: July 28, 2020, 04:49:12 am
content: Quote from: EEVblog on July 28, 2020, 04:23:32 amhttps://www.eevblog.com/forum/fpga/custom-spartan-7-board-for-beginners/Description, some photos and links to Github repos are in that post.

author: -gb-
author_rank: Contributor
timestamp: July 28, 2020, 09:30:23 am
content: QuoteI don't want anything. But when i pull it to the marking, then a bit will look over the pcb edge. This is OK when the PCB goes inside a housing.QuoteTotally right. As said, i don't need anything, it is not my project i just had time to spare and tried an area optimised version. I am no professional and only do hobby projects which i handsolder with hot air. Double sided load saves me money with smaller PCB area. With handsoldering you can do many things you wouldn't do in production, unplugges Vias in pads e.g. for even higher component density.

author: asmi
author_rank: Super Contributor
timestamp: July 28, 2020, 01:53:22 pm
content: Quote from: -gb- on July 28, 2020, 09:30:23 amThese USB connectors often have a "lip" that is supposed to hang on the the side of a board, helping to prevent user from ripping connector out when inserting the cable. Look at this one for example:https://www.snapeda.com/parts/10118193-0001LF/Amphenol%20FCI/view-part/?ref=digikeyIf you take a look at the 3D model you will see what I mean.

author: poorchava
author_rank: Super Contributor
timestamp: August 06, 2020, 12:47:18 am
content: Buck converter:-layout is just bad. Large loops, long & thin traces between the chip and the inductor. Pleas do yourself a favor and follow the guidelines from the chip datasheet.USB interface:-use a smaller crystal. That crystal is probably 12MHz for USB. U can easily find that in a 2.5x3.2mm package. Or just ditch the CH340 (that's what I assume it is) and use something like FT230X. It's available in a 16-pin QFN package and doesn't require a crystal at all. Also, the CH340 are worse than FTDI when it comes to high speed transmission. I could push FT230XQ up to about 2.5mbit, whereas CH340 craps out just about 1mbit.general:-use smaller passives. Those look like 0805. I mean come on, it's not 19th century. Go for 0402. You have small packages in there anyway, so that shouldn't be any problem-fpga decoupling caps are routed in sub-optimal fashion. The power supply and ground lines should "fly through" a capacitor and then into the chip. If you have a ground plane, then just place a cap near the pins and a groundplane via on the opposite side of the cap, than the FPGA