Xilinx VPSS MicroBlaze Example - Page 1
Forum section: electronics / general

author: Mario87
author_rank: Frequent Contributor
timestamp: June 15, 2022, 08:57:08 pm
content: Hi all,I am looking for a Microblaze (or at least some kind of Vitis) example project for the Xilinx Video Processing Sub-System.Really what I am looking for is something like this video with the sample code...If you skip to 8:20 in the video you will see that there is a menu which allows you to simply set the output resolution / scaling, that is all I am needing for now.I have a test pattern generator running as part of the block design and I have implemented the IP cores for VPSS, MicroBlaze, MIG_7 memory controller, etc. Now I just need an example MicroBlaze code to do the above.Any suggestions?

author: kmike
author_rank: Regular Contributor
timestamp: June 16, 2022, 10:52:46 am
content: Hi,you can find some example code in the xilinx directories:C:\Xilinx\Vitis\2020.2\data\embeddedsw\XilinxProcessorIPLib\drivers\vprocss_v2_8\examplesReplace 2020.2 and vprocss_v2_8 with your versionsbr,mike

author: Mario87
author_rank: Frequent Contributor
timestamp: June 16, 2022, 08:50:50 pm
content: Thanks, but not really much in there that suits from what I can see, however someone on the Xilinx forum pointed me towards the Video Series Blog...https://support.xilinx.com/s/question/0D52E00006hpsS0SAI/xilinx-video-series-and-blog-postsIt looks like "Video Series 29" is closest to what I need. I have downloaded the files but when I try to build the SW project I kept getting errors about missing headers.I added the "Includes" to the header file sources in the Xilinx Vitis directory, but now when I try and build I keep getting errors like the ones below and I don't know what to do to fix it, any suggestions?Code:../src/app_hdmi.c:111:15: error: 'XPAR_AXI_VDMA_0_BASEADDR' undeclared (first use in this function); did you mean 'XPAR_AXIVDMA_0_BASEADDR'?../src/app_hdmi.c:260:26: error: 'XPAR_CLK_WIZ_0_BASEADDR' undeclared (first use in this function); did you mean 'XPAR_GPIO_0_BASEADDR'?../src/app_hdmi.c:451:51: error: 'XPAR_V_TPG_0_DEVICE_ID' undeclared (first use in this function); did you mean 'XPAR_XV_CSC_0_DEVICE_ID'?../src/app_hdmi.c:459:46: error: 'XPAR_V_TC_0_DEVICE_ID' undeclared (first use in this function); did you mean 'XPAR_XV_CSC_0_DEVICE_ID'?I just want to get this build working so I can use it as a template to modify and suit my own needs. Any help greatly appreciated!

author: kmike
author_rank: Regular Contributor
timestamp: June 17, 2022, 05:26:21 am
content: Are you using the example "hardware" in your project or your own?Are you using vivado 2019, like in the example?br,mike

author: Mario87
author_rank: Frequent Contributor
timestamp: June 20, 2022, 08:05:17 pm
content: Hi, not I am not using the example HW, however my HW is VERY similar to what is on page 69 of the product guide (link below), as such I thought it would maybe be best to use the example code described in there from page 71 onwards. Only difference is I have an AXI traffic gen connected to the TPG to output a fixed pattern at fixed resolution, so I commented out the code for all the TPG stuff in the example and went to build it but not I keep getting the error "unknown type name Xperiph" and I am not sure why when that's part of the example code that relates to things like the VTC which I do have and I also have connected in the same way as them.The Vitis side of Xilinx stuff is really not my strong suite, embedded C and all that, especially their implementation of it.https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/v_proc_ss/v2_3/pg231-v-proc-ss.pdf