Can anyone check my work? It is my first PCB design. - Page 1
Forum section: electronics / beginners

author: trumpet205
author_rank: Contributor
timestamp: January 20, 2015, 03:18:12 am
content: I'm not sure if I posted in the right section, if not please move my thread to the correct section.A brief introduction: I have never messed with PCB or anything in my life. I know very little when it comes to electric engineering. For the past couple months I wanted to do modifications on my game consoles (I'm a retro gamers). The modification I have in mind is a digital audio mod, specifically these two:http://gamesx.com/wiki/doku.php?id=av:saturn_sp_difhttp://gamesx.com/wiki/doku.php?id=av:dreamcastdaThe instruction is very straight forward, but rather than using 2 breakout boards per console (for hex inverter and CS8406) I decided why not make things look neat by coming up with a single board.Here is the design for both consoles that I come up with:VCC is +5.0VC1 is a 1uF 16V ceramic capacitorC2 and C3 both use 0.1uf 16V ceramic capacitorSJ1 (the solder jumper) is for whether to use separate RESET input (used in Saturn), or tie it to +5.0V (used in Dreamcast)I'm using SN74ALS04BDR as my hex inverter (for both inverting EMPH and buffering SPDIF/TXP output).And here is the board layout that I come up with:So I need some inputs from this community. Have I committed any mistake in this PCB design?

author: Skimask
author_rank: Super Contributor
timestamp: January 20, 2015, 04:55:45 am
content: 1- Used the autorouter.

author: trumpet205
author_rank: Contributor
timestamp: January 20, 2015, 06:13:08 am
content: Quote from: Skimask on January 20, 2015, 04:55:45 amI did use the autorouter on this. Was there anything wrong with the tracing?

author: IconicPCB
author_rank: Super Contributor
timestamp: January 20, 2015, 06:29:22 am
content: another fine example of an invisible board

author: trumpet205
author_rank: Contributor
timestamp: January 20, 2015, 06:37:52 am
content: Quote from: IconicPCB on January 20, 2015, 06:29:22 amPlease elaborate.

author: Unknown
author_rank: Unknown
timestamp: January 20, 2015, 06:51:41 am
content: He might mean this: When I look at the first post in Firefox, I don't see any image of or link to a board. It's possibly a bug in FF or due to adblock / some other plugin, since the image link is there in the HTML.I only noticed this because I read the post & looked at the pic on my phone earlier.edit: I get a broken image in Safari on OSX too - but it works for me on my iPhone. Go figure...

author: trumpet205
author_rank: Contributor
timestamp: January 20, 2015, 07:10:50 am
content: Quote from: Tac Eht Xilef on January 20, 2015, 06:51:41 amI re-uploaded the image. Can you see it now?

author: alterbaron
author_rank: Contributor
timestamp: January 20, 2015, 07:30:41 am
content: Yep. Wasn't showing before, but it is now.

author: tautech
author_rank: Super Contributor
timestamp: January 20, 2015, 07:48:23 am
content: It's god awful.....Traces on top of each otherTraces that join pads at anglesRight angle bends in traces.Can any components be flipped for better routing? eg SDIN & ISCLKLayout & routing is not a 5 minute process and a novice might take a day or two to make a presentable job of your board.Check out Daves tutorial on PCB layout:http://www.eevblog.com/wiki/index.php?title=Online_Electronics_Tutorials_and_BooksGet some old PCB's and study them, power paths, signal paths and component layout

author: Unknown
author_rank: Unknown
timestamp: January 20, 2015, 08:15:52 am
content: Yes, all that.It's hard without knowing how wedded you are to that board size & connection pad layout, but you can probably:Move C1 down near the Gnd & Vcc pads - it's purpose is bulk smoothing, so put it near the power input pads/pins.C2 & C3 should be as close as possible to the power pins of their respective ICs; ideally in-line with Vcc & Gnd (i.e. not off on a little branch of their own). Yes, it can be difficult for something like 74 logic with power on diagonally-opposite pins, but...... remember you can have a ground plane. Use it. Route everything but Gnd manually, then see if the autorouter can handle it. Look out for orphaned polygons.(As an aside, your schematic doesnt show Vcc/Gnd to the 7404. I realise it's probably connected on the unshown unused 1/4, but it makes it a bit harder to double-check - and you're the one who's going to be kicking themselves after you've waited 2 weeks to get 10 boards back from China and discover you forgot to power the logic...)Layout may be easier / neater if you rotate the 7404 by 90 or 180 degrees. Same for the CS8406; it may be easier if it was rotated 90 degrees & moved up to the top edge of the board.At the sort of speeds this will be running at, it wouldn't hurt to devote 1 side to gnd plane.I meant it about manually routing signal & Vcc before letting the autorouter fill the ground plane.edit: Oh, and there's absolutely no reason to use minimal trace size; it's just asking for problems. They're what, SOIC packages? That suggests your traces are 8 thou or so. Bump them up to 16thou...

author: Skimask
author_rank: Super Contributor
timestamp: January 21, 2015, 03:45:08 am
content: And the 4th gate of the 7404 is left wide open. Nice place for some good noise making floating gate oscillation sort of stuff.Not good.Tie up loose ends.

author: trumpet205
author_rank: Contributor
timestamp: January 21, 2015, 10:39:29 pm
content: Thank you tautech, Tac Eht Xilef, and Skimask. That's very informative reply. I do have some questions though,* Is there any downside of trace coming at an angle to the pads?* How do I tie up unused gates of hex inverter? Do I simply connect them to VCC and GND respectively?* When you say devote one plane to GND, do you mean filling unused area with copper and tie it to GND? I did do that on my first design, but it did not show up on the picture.I actually re-do the board design again, this time manually routed it. The board came out larger than I expected because of increased trace width,GND is not routed yet.

author: tautech
author_rank: Super Contributor
timestamp: January 22, 2015, 12:06:17 am
content: Much better.There is still more you could do.I like VCC to be a wider trace and therefore easy to identify, The same apploes to any power trace IMO.The fork in the trace for C3 is not required. Run the trace from near GND straight across and drop a branch trace to C3.I prefer not to run traces through pads, but instead put the pad just off the trace and bring a short trace to the pad. Of course at the last component at the end of a trace just run into it.Everybody has a different style, some for good reason like "PCB tombstoning". Google it.Don't forget to save revisions, they are good to refer back to sometimes.

author: Unknown
author_rank: Unknown
timestamp: January 22, 2015, 07:12:14 am
content: Yeah, much better. There's some stuff you could do better, and I'd do it differently - but remember that 99% of the time there's no absolute optimum way of laying out a board. It'll always be a compromise between the electrical requirements (e.g. minimising trace resistance/inductance/capacitance), device pinouts (e.g. the 7404 with +ve & gnd on diagonally-opposite pins), assembly method & ease of assembly (e.g. leaving space to hand solder parts), and a certain degree of aesthetics (does it lookright&good?).For a bare-bummed newbie it's not a bad effort; the best thing you can probably do right now is accept your first effort is never going to be perfect, tidy it up a bit according to the suggestions in this thread, make some boards, and see for yourself how it looks & works in real life.As for your specific questions:"Is there any downside of trace coming at an angle to the pads?" - that's a can of worms right there! Some say the acute angle forms a 'trap' when etching & leads to potential undercutting/overetching at that point. Can't say I've seen it myself, and it's unlikely to make a difference with 16mil tracks (but it's another good reason to keep away from the minimum track size)."How do I tie up unused gates of hex inverter? Do I simply connect them to VCC and GND respectively?" - Again, another slightly contentious question! Some people prefer to tie the unused inputs high or low, some prefer to tie the outputs, and some prefer to tie both the inputs & outputs as appropriate (e.g. inverter input high & output low, or vice-versa). IIRC the 7404 has internal pull-ups on its outputs, so personally I'd tie unused inputs low (pulling them high will only increase power consumption & chip dissipation slightly) and leave it at that."When you say devote one plane to GND, do you mean filling unused area with copper and tie it to GND?" - Yep. You've got a double-sided board there, with most tracks on the top & few (& getting fewer!) tracks on the bottom. Devote the whole bottom layer to a ground plane (a couple of tracks won't matter as long as you don't cut it up into pieces), and use vias to tie the ground pins & fill to the bottom."I actually re-do the board design again, this time manually routed it. The board came out larger than I expected because of increased trace width" - 16 or even 20 mil trace width shouldn't make any difference on a board with those components & little complexity. It's probably a sign your layout isn't anywhere near optimal, or you've not quite got a good sense of the scale involved (or your Eagle design rule clearances are way OTT!).Quick suggestions off the top of my head:As mentioned, I'd make the bottom side primarily a ground plane with vias through to the top.I'd run Vcc as a 'rail' up the RH side & around the top (& yes, make it thicker), with spurs off to the decoupling caps & power pins of IC1 & 2. Yes, it might be bad practice in many cases; no, I don't think this is one of those cases, the layout advantages outweight any potential disadvantages, and it'll be no worse than it is now.Move the trace running from 7404 pin 2 to CS8406 pin 3 - though it's probably safe, it does cut awful close to pin 1 for no real reason.It looks like you're not stuck with a specific pad layout, so I'd make the row at the bottom EMPH - ILRCK - ISCLK - SDIN, and move OMCK up to the top adjacent to it's CS8406 pin. That'll allow you to re-route tracks & get rid of a lot of the general untidyness around there, and save 1 unnecessary trip to the far side of the board and back again.Consider rearranging things so you can rotate SJ1 180 degrees (e.g. move the RESET pad up to the bottom of the CS8406 near SPDIF). That'll do more to tidy things up down around there, and you'll remove another unnecessary trip to the dark side...Hope that helps

author: Unknown
author_rank: Unknown
timestamp: January 22, 2015, 12:01:39 pm
content: Noticed I had the CS8406 in Eagle, so while I was waiting for dinner I quickly copied your circuit & had a play.No guarantees I copied it correctly, but I think I got it right. I swapped gates B & C with D & E to make the layout work better. Bottom layer is all Gnd plane. I would've improved few things but my pizza arrivedI also noticed that some of the CS8406 connections look a bit odd - e.g. should VL3+ & VL4+ be tied to Gnd? - but it's your circuit, you check itThe dimensions are in inches. Feel free to make it smaller...

author: katzohki
author_rank: Frequent Contributor
timestamp: January 22, 2015, 03:52:57 pm
content: These pads (VCC, GND, etc), it looks like you're going to solder directly to these right? Might want to keep them all nicely aligned on one board edge and away from any components (probably good enough spacing except the couple capacitors). You could go with through-hole solder points to make it easier for the novice to solder, assuming you're going to give this to other people to use.

author: trumpet205
author_rank: Contributor
timestamp: January 22, 2015, 11:32:35 pm
content: Tac Eht Xilef:Wow that's a very clean design. I still have a long way to go.As for VL3+ and VL4+ (pin 20 & 27), those pins become HWCK0 and HWCK1 when CS8406 is in hardware mode (pin 24 tied to VCC). You tie pin 20 and 27 to VCC or GND to control OMCK clock ratio.I double checked CS8406 datasheet, the connection is correct.katzohki:This is just something I want to do in spare time. I haven't really thinking about making boards for other people. I chose SMD wirepad because I want a flat surfaces on the bottom.

author: tautech
author_rank: Super Contributor
timestamp: January 22, 2015, 11:58:06 pm
content: Quote from: trumpet205 on January 22, 2015, 11:32:35 pmYou'll be lucky if you are ever 100% happy with the finished product, especially as they get more complex.Sometimes layout is a compromise once you have the basics right.I've spent weeks(spare time) on a PCB, although I try to do as much as possible single sided.Often a wire link or a TH component can make the difference to get the routing to work.SMD has both pro's & cons for routing, but is it my device preference when possible.Good to see you "taking it all in", study any PCB critique threads that you can find and soak it all up.

author: Unknown
author_rank: Unknown
timestamp: January 23, 2015, 03:24:05 am
content: Quote from: trumpet205 on January 22, 2015, 11:32:35 pmThanks, I'm no expert. And don't underestimate your own efforts; it's really just my revision of your earlier layouts. The big key was re-arranging the gates.That said, I'm not entirely happy with it & would do more before turning it into a board. For a start, the grounding could be a lot better - the tail end of C2 should really have a direct route on a single polygon to 7404 pin 7 (not through a couple of vias, though it'd be OK to use vias to tiethatpolygon to the bottom Gnd), and I'd have to look at the datasheet for the CS8406 to see what the 'real' Vcc & Gnd pins were with an eye to the same thing for C3.Quote from: trumpet205 on January 22, 2015, 11:32:35 pmThat's fair enough (& sorry if I came across a bit harsh when mentioning it). I didn't look at the datasheet at all, it was just that some of the pin names vs Vcc / Gnd connections seemed a bit odd.Quote from: tautech on January 22, 2015, 11:58:06 pm^ This x 10 ^.

author: trumpet205
author_rank: Contributor
timestamp: January 23, 2015, 04:02:41 am
content: Not at all, you weren't hash at all.Actual GND on CS8406 is pin 22, while VCC is on both pin 6 and 23. According to the datasheet of CS8406, pin 6 is digital power supply input while pin 23 is logic power supply input.Page 29:http://www.cirrus.com/en/pubs/proDatasheet/CS8406_F6.pdf

author: peter.mitchell
author_rank: Super Contributor
timestamp: January 23, 2015, 04:25:55 am
content: You should avoid connecting pins together directly between the pins, instead coming out the end of the pins. This way when assembling, solder won't want to bridge between the pins. Sure, the pins are meant to be connected to each other, but can you remember the pinout of every IC in your layouts? Probably not so you'll often try to remove the bridge without needing to, and it also looks ugly to see solder bridges.Example;I understand that this is a polygon pour with thermal reliefs but it still stands.

author: Unknown
author_rank: Unknown
timestamp: January 23, 2015, 05:06:31 am
content: Quote from: peter.mitchell on January 23, 2015, 04:25:55 amFWIW that's my mistake, not the OP's; and yeah, you're right, I agree 100% for exactly the same reasons.In my defence I spent 15 minutes, maybe 20 minutes on it tops - including copying the schematic

author: trumpet205
author_rank: Contributor
timestamp: January 24, 2015, 06:51:28 pm
content: Final touch up:* Bottom layer is all ground.* Changed capacitor size from 1206 to 0805* Added C4 to decouple pin #6, since CS8406 has two power input pins.* Added chamfer and teardrop.Anything else I should do?

author: tautech
author_rank: Super Contributor
timestamp: January 24, 2015, 07:50:37 pm
content: Quite good now, a few things to reduce grief for later....Many PCB design packages have a "neck down" rule for traces to pads for SMD.This helps reduce the chance the chance of solder bridging.If a solder mask layer is used, you need not worry.For the same reason move traces 9 & 10 under "04" to middle of the IC.I keep in the back of my mind in layout and routing....leave a job that is easy to trace and follow for those that might have to troubleshoot you board.Often with a small PCB. you will hand solder components for assembly, think about the order of soldering, (sensitive components last) and ensure there is enough clearance to get you iron in.In a simple board when you have room like yours, NO under component Vias.That can be a hard call I know, but try if you can.Traces to pins 31 & 32 could be outside if C3 was moved.Rework VCC, GND, C1 these could could be a bit neater.....All this said, you now see how it can go on & on & on & on....Any more is nit picking and things you will discover for youself as boards get more complex & dense.Well done.

author: WattsUp
author_rank: Regular Contributor
timestamp: January 24, 2015, 08:27:05 pm
content: Is it not better to bend a trace at two 45 degree stages than one right angle?Edit: sorry I posted after seeing your first revision and for some reason my wifi has not been working correctly

author: trumpet205
author_rank: Contributor
timestamp: January 24, 2015, 10:53:58 pm
content: One question, for C1 I'm thinking about using 4.7 uF as opposed to 1.0 uF. There really isn't a lot of info about how much capacitance for bulk capacitor that I can find over the Internet. All I gathered so far is that making sure bulk capacitance is greater than sum of all decouple capacitance.

author: tautech
author_rank: Super Contributor
timestamp: January 25, 2015, 01:20:01 am
content: Quote from: trumpet205 on January 24, 2015, 10:53:58 pmAsk yourself: what is it for?To support the PSU and prevent rail voltage sag close to where the power is consumed.Any fast switching uses chunks of current and the bulk cap helps provide it locally.Decoupling caps are intended to restrict that switching generated noise getting back to the power rails and affecting other components.Put 1000 uF in if you are so inclined.

author: Unknown
author_rank: Unknown
timestamp: January 25, 2015, 07:36:45 am
content: Nice job. That's one to be proud of! Better than mine, that's for sure.Good call on adding C4.As for upping C1 ... well, I look at it this way: it's designed to go into other equipment which may have unknown design requirements/constraints e.g. sequencing of power rails vs each other / signals. So I'd try to keep bulk capacitance to a reasonable minimum that'll do the job locally, and 1uF doesn't seem out of place for a circuit drawing (at a guess) <50mA peak.The rest, I think, is stuff best learned by experiencing the little things that make manufacture / assembling / troubleshooting harder than it needs to be. Though it certainly doesn't hurt to be told about them now.