Entry level FPGA engineer interviw questions feedback.  - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: January 29, 2020, 06:19:47 am
content: Hi all,I compiled a bunch of FPGA interview questions from reddit and youtube. The following document is my best answers in the moment with no google searching (just brain use haha). I would love some feedback if you have the chance.number 16 asks to create a simple state machine. I used verilog because It is what i am most familiar with. It took me about 25 min to write and simulate the RTL and the testbench with comments. I could probaly do it in 18 if i wasnt tiredCode:// Can you code a simple state machine?// I will use Verilog.`timescale 1ns / 1psmodule SM(input clk,input [1:0] some_input,output [1:0] some_output);reg [1:0] STATE; // state of machinereg [1:0] output_0 = 2'b00; // various outputsreg [1:0] output_1 = 2'b01;reg [1:0] output_2 = 2'b10;reg [1:0] r_some_output = 0; // register to hold output (assign later)localparam STATE_0 = 0; // stateslocalparam STATE_1 = 1;localparam STATE_2 = 2;always @ (posedge clk)begincase(STATE)STATE_0 : beginif (some_input == 0)beginr_some_output <= output_0; // change outputsSTATE <= STATE_1; // change stateendelse // else remain in same stateSTATE <= STATE_0;end // STATE_0STATE_1 : beginif (some_input == 1)beginr_some_output <= output_1; // change outputsSTATE <= STATE_2; // change stateendelseSTATE <= STATE_1;end // STATE_1STATE_2 : beginif (some_input == 2)beginr_some_output <= output_2; // change outputs but stay in state 2endelseSTATE <= STATE_2;end // STATE_2default : beginSTATE <= STATE_0;end // defaultendcase // case(STATE)end // always blockassign some_output = r_some_output;endmodule////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////`timescale 1ns / 1psmodule tb;reg clk;reg [1:0] some_input;wire [1:0] some_output;always #5 clk = ~clk; // create clock signalSM uut(clk,some_input,some_output);initialbegin$dumpfile("test.vcd");$dumpvars(0,uut);clk = 0;some_input = 2'b00; // move through various inputs to change states.#20some_input = 2'b01;#20some_input = 2'b11;#20$finish;end //initialendmodule

author: hamster_nz
author_rank: Super Contributor
timestamp: January 29, 2020, 09:42:20 pm
content: > 8 ). What is Metastability, what is it caused by, and how do you avoid it (in a FPGA)?Answer is very vague... I like the answer to 14 much better. The answer needs to have "asynchronous input" in it somewhere, and "setup/hold time violation" in it. Clock domain crossing don't 'cause' it, it is just where it can happen. A good clock domain crossing design solves metastability issues..> 10). What is the difference between a Melee and a Moore machineYou need to work in this one. It is one of those concepts that "egg heads" like to push. In practice it is academic - a bit like "behavioral" vs "structural" designs.> 12) Name some latches.I don't that "NAND", "NOR" are are latch types.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 29, 2020, 09:57:04 pm
content: For Moore/Mealy, you can read this, which is short and to the point:https://en.wikipedia.org/wiki/Mealy_machineMany people writing HDL code these days don't really care about how to call their FSMs, but those will usually fall within one category or the other.

author: Dmeads
author_rank: Regular Contributor
timestamp: January 30, 2020, 04:12:16 am
content: Thanks sounds like I got some things to to work on