hybridfree/eevblog-posts huggingface dataset:
GOWIN FPGAs now in stock at Mouser - Page 1
Forum section: electronics / general

author: dmendesf
author_rank: Frequent Contributor
timestamp: July 30, 2020, 10:05:02 pm
content: Enjoy:https://br.mouser.com/GOWIN-Semiconductor/Semiconductors/Programmable-Logic-ICs/_/N-3oh8v?P=1y7ff8h
Converting table files (.tbl) to vector waveform files (.vwf) for simulation. - Page 1
Forum section: electronics / general

author: echotwozero
author_rank: Newbie
timestamp: July 22, 2020, 12:33:55 pm
content: Hello everyone,I am migrating an old MAXPLUS II design to Quartus II. I could transferthe schematic files and the design is ready, but not able to migrate thesimulation vectors to be compatible with modelsim. I have .scf(simulation channel files), .vec (vector files) and .tbl files and Iwant to know if any of them somehow can be converted to .vwf (vectorwaveform file) to be used in modelsim simulation.Kindly provide any information / lead me to resources that you know.Thank you very much in advance!
Net 'myled' does not have a driver? - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 09, 2020, 12:30:08 pm
content: This is some very simple Code for a gowin FPGA,Do you know why I got this warring at synthesize output?Code:module Top(input clk,output led);reg [23:0] CNT = 0;reg myled = 1'b1;always @(posedge clk) beginCNT <= CNT + 1'b1;if(CNT == 25000000) beginmyled <= !myled;CNT <= 0;endendassign led = myled;endmoduleQuoteSo the output pin would not drive the LED

author: asmi
author_rank: Super Contributor
timestamp: July 09, 2020, 01:05:30 pm
content: Not all FPGAs have ability to pre-set flip-flops during configuration, which is why it's recommended to have explicit reset sequence unless you target devices which are known to have such functionality.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 09, 2020, 01:10:22 pm
content: QuoteHow?You mean by saying like thisCode:module Top(input clk,output reg led);Gowin EDA complains about this type of code

author: FenTiger
author_rank: Regular Contributor
timestamp: July 09, 2020, 01:10:38 pm
content: Quote from: ali_asadzadeh on July 09, 2020, 12:30:08 pmIf CNT can range from 0 to 16,777,215 decimal...Quote from: ali_asadzadeh on July 09, 2020, 12:30:08 pm...then the if here is always false, and the only statement which assigns to myled can never happen.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 09, 2020, 01:11:55 pm
content: QuoteHow? I do not have any additional IO in my PCB for Reset.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 09, 2020, 01:26:50 pm
content: QuoteThis was the problem, I changed the CNT size toCode:reg [24:0] CNT = 0;Now it's working.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 09, 2020, 01:29:03 pm
content: QuoteThis works too, with the change in CNT size,But this type of declaration would throw another warning tooCode:WARN (EX3628) : Redeclaration of ansi port 'led' is not allowedBut the code works on the FPGA

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 09, 2020, 01:45:50 pm
content: Here is another example, Testing baudrate generationThe output LED is always 0The Top ModuleCode:module Top(input clk,output led);BaudGenerator #(.Baud(2)) myBaudGen (.i_clk(clk),.o_baudTick(led));endmoduleBaudGenerator ModuleCode:module BaudGenerator#(parameter Baud = 9600, //Default Baud rateparameter sysClk = 25000000) //System frequency(input i_clk,output reg o_baudTick);localparam [23:0] c_baudAddValue = (16777216.0 * Baud * 4.0) / sysClk;//reg [23:0] c_baudAddValue = (16777216.0 * Baud * 4.0) / sysClk;reg [23:0] r_baudCnt = 0;reg [1:0] r_baudEdge = 0;always @(posedge i_clk ) beginr_baudCnt <= r_baudCnt + c_baudAddValue;r_baudEdge = r_baudEdge;r_baudEdge= r_baudCnt;o_baudTick <= 0;if (r_baudEdge == 1'b0 && r_baudEdge == 1'b1) begino_baudTick <= 1'b1;endendendmodule

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 11, 2020, 07:15:12 am
content: QuoteThanks, Just show me your code
How do I write VHDL that can keep up with a 6.6Gb/s GTP? - Page 1
Forum section: electronics / general

author: dnhkng
author_rank: Contributor
timestamp: July 01, 2020, 06:19:03 pm
content: I'm pretty new to FPGA, but one thing I don't get is how the FPGA can keep up with high-speed serial.I had some designs I couldn't get to even 150MHz, and if the deserializer is reading bytes for a 6.6Gb/s stream, that's not fast enough to process the incoming information.Am I missing something?

author: filssavi
author_rank: Frequent Contributor
timestamp: July 01, 2020, 06:27:29 pm
content: I never used the GTPs, however I guess you want to use hard SERDES blocks to do convert the stream to as wide as possible, 10/30 bytes I guess, and then do stuff in parallel, otherwise it is just like drinking from a firehoseIf the transmissions are bursty You might also get away with pushing everything to a Ram block and then do processing slowly

author: AndyC_772
author_rank: Super Contributor
timestamp: July 01, 2020, 06:32:56 pm
content: Hard wired SERDES blocks. The FPGA ismostlyconfigurable logic, which is versatile but relatively slow, but also includes optimised, hard wired circuits for common logic functions such as multiplying numbers, dual port RAM, and in this case, parallel-to-serial conversion.As far as your logic is concerned, a 6 GHz "serial" interface could actually look like a 32 bit parallel interface clocked at around 200 MHz, which within the confines of the FPGA die, is more manageable.

author: Bassman59
author_rank: Super Contributor
timestamp: July 01, 2020, 06:55:36 pm
content: Quote from: dnhkng on July 01, 2020, 06:19:03 pmThe deserializer is a hard block in the FPGA, and you access it in your code by instantiating a library element.The output of the deserializer is parallel data words of some given length that is dependent on how the deserializer is configured. That parallel bus runs at a fraction of the rate of the gigabit data stream, and should be manageable in your larger FPGA design.Also, I don't think they'd put such a high-speed deserializer in the FPGA if the fabric itself couldn't handle the deserialized data.

author: dnhkng
author_rank: Contributor
timestamp: July 01, 2020, 07:48:51 pm
content: Thanks, I think it makes sense now!
FPGA ide, currently using quartis 2 - Page 1
Forum section: electronics / general

author: prophoss
author_rank: Contributor
timestamp: June 30, 2020, 10:08:12 pm
content: I am currently using quartis 2 ver. 13 to program my cyclone 4 chip. It took a bit of doing to learn how to do all that.Having said that, I was wondering if there was a way to use another text editor other than the one provided? I could use VS Code and then copy and paste and if I could synthesis the code in VS Code I would pretty happy with that, but that doesn't seem quite so easy.I tried to find a way to change the quartis text editor to a darker background but there doesn't seem to be a way to do that. There is just a lot about VS Code that I like and that I wish I could use in quartis. That made wonder what other IDEs work with ALTERA chips or at least synthesis code from the IDE instead of having to copy paste then synthesis? I am not hung up on any one way but would prefer not to have to re-learn yet another tool-chain.

author: rstofer
author_rank: Super Contributor
timestamp: June 30, 2020, 10:15:17 pm
content: Edit with Visual Studio Code.What does Quartus do when a file is edited outside the IDE. Many IDEs will detect that and offer to load the revised copy. Otherwise, close the project, do your edit and then just reopen the project. Some combination will work...

author: BrianHG
author_rank: Super Contributor
timestamp: June 30, 2020, 10:16:53 pm
content: You do not need to use Quartus's text editor to edit HDL code. The source code files are in your project directory and they are normal ascii text just like a .txt file. If you other editor doesn't generate any funny characters or save in a binary .doc, .docx, .odt, .rtf, then you can use it directly on the files. And then you just need to compile in Quartus.There exist other HDL ascii text editors which will also properly colorize the mnemonic. Google Verilog VHDL text editors.You do not need to exit Quartus when externally editing. After you make a 'save', Quartus will automatically detect the change when you re-compile your project.

author: prophoss
author_rank: Contributor
timestamp: July 01, 2020, 12:50:03 am
content: I had not thought of that. I will start the file in quartis then edit it in VS Code. That doesn't sound to bad at all, thanks y'all!

author: prophoss
author_rank: Contributor
timestamp: July 01, 2020, 01:12:33 am
content: I finally hit the right wording on google and found how to use notepad ++ as the default text editor for quartis 2!Thought I'd post the link just in case someone else needs it.https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06122006_699.html#:~:text=To%20direct%20the%20Quartus%C2%AE,editor%20you%20want%20to%20use.
Using code to remove bounce - Page 1
Forum section: electronics / general

author: mriPaul
author_rank: Contributor
timestamp: June 22, 2020, 12:34:50 am
content: I am using VHDL to read encoder pulses on an FPGA. Currently, I detect the change in the two pins and wait a set time for the any bouncing to stop and repeat. It just occurred to me that instead of waiting for my PC817 to settle, I read the change and change the inputs to outputs driven to the what the change was for a short time to shunt away the bounce. Is that common practice..bad practice?

author: cruff
author_rank: Regular Contributor
timestamp: June 22, 2020, 01:28:16 am
content: Do I understand you to say you are thinking of switching the FPGA I/O pin reading the encoder pins to an output in an attempt to force the pin bounce to stop? That won't work, and may damage the pin driver in the FPGA.

author: wraper
author_rank: Unknown
timestamp: June 22, 2020, 01:42:43 am
content: You should not wait for bouncing to stop. It's a very flawed way how to do it, and regretfully implemented in many devices. Bouncing may never stop completely and you will get missed pulses. Much more robust way is add/substract counter with state transition when you get more of one state than another state with some hysteresis. Say you count from 0 to 20 with readings done with certain intervals of time. When counter gets to min or max, you detect a state change. Also you can consider that contact is closed basically instantly without waiting bouncing to stop at all (as there is no bounce at all when contact is open), and only debounce a transition to open state.QuoteThat's some stupid nonsense. It won't fix the bounce and only abuses both FPGA and encoder.
Tasks in Verilog on Clock edges - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: June 18, 2020, 06:01:17 am
content: Hi,I am trying to create a task to toggle a register on the negative edge of a clk;I used a task (i dont think functions can model sequential stuff?) that has some syntax errors, but I don't know what im doing wrong. Also, once the task is coded right, how do I call it in my initial block?Code:`timescale 1ns / 1psmodule tb;reg A,B,C,D,E,K;reg COMPLS6 = 0; // RDreg SBYTECLK = 0;always #2 SBYTECLK = ~SBYTECLK;encoder_5b6b uut(A,B,C,D,E,K,COMPLS6,SBYTECLK);task DISP;input SBYTECLK;beginalways @ (negedge SBYTECLK) // reverse RDCOMPLS6 = ~COMPLS6;endendtask;initialbegin // test all possible 4-0, 0-4, 1-3, 3-1, and 2-2 one-zero combos$dumpfile("dump.vcd");$dumpvars(0,uut);SBYTECLK = 0;K = 0;// Data onlyDISP(); // START RD @ 0 (-1);A = 1;B = 0;C = 0;D = 0;E = 0;#4A = 1;B = 1;C = 1;D = 0;E = 0;#4$finish;endendmodule

author: ejeffrey
author_rank: Super Contributor
timestamp: June 20, 2020, 08:34:29 pm
content: You can't use always inside a task, but you can call a task from inside an always or initial block. It certainly wouldn't make sense in this situation as you then would have always inside an initial block. This should probably be a module or maybe just a loop.You call a task with normal "function call" syntax.
Spartan-6 CCLK switching to 50 MHz -- why?! - Page 1
Forum section: electronics / general

author: ebastler
author_rank: Super Contributor
timestamp: June 20, 2020, 09:10:10 am
content: I'm encountering yet another Spartan-6 mystery... Bringing up my first self-designed FPGA board, after various earlier projects which used off-the-shelf boards from Numato. I can configure it nicely via JTAG, using the iMPACT software. iMPACT also states that indirect programming of an attached SPI flash ROM is successful. (Although it makes me slightly suspicious that the progress indicator only goes up to 25% during the programming; is that normal behavior?)But the FPGA is not able to configure itself from flash when I power-cycle it; DONE won't go high. Looking at the CCLK and data lines with a scope, I see that there is plausible traffic -- but the CCLK, after about 800 cycles at 1 MHz, switches up to 50 MHz!I don't think I asked for that; please see the Bitgen settings in the attached screenshot. Any idea what is happening here?Signal integrity is often mentioned as a likely culprit for configuration issues. I have indeed omitted any termination resistors on the CCLK and data lines, due to space contraints. But this is a very compact layout, with a 15 mm long CCLK trace and < 20 mm data traces. The signals look perfect at the slow 1 MHz rate, and even seem to keep up at 50 MHz. Adding improvised kind-of-termination resistors to the CCLK and flash data output lines doesn't change anything either. So I don't think compromised signal integrity is the cause.The behaviour is fully reproducible, always occuring at the same time (after about 800 µs of 1 MHz clock pulses), and on two separate boards I have populated. I assume the 800 µs time is when the FPGA is meant to switch from its conservative startup CCLK (is that expected to be 1 MHz?) to the clock rate defined in the Bitgen properties. But where does it get the idea to select 50 MHz?!Many thanks for your ideas!

author: skip
author_rank: Contributor
timestamp: June 20, 2020, 07:06:35 pm
content: My guess is that the Configrate is read from the SPI flash during the early part of the configuration. If your flash isn't being read correctly at 2 Mhz (all 1's perhaps?) the clock rate will change to what it read.Are you using an officially supported SPI chip? If not that could also be the problem (3 byte addressing vrs 4 byte for example).Good Luck!
Creating a simple testbench - Page 1
Forum section: electronics / general

author: Digitalio
author_rank: Contributor
timestamp: May 27, 2020, 05:45:40 pm
content: My current attempt to create a testbench for a led blinker module:Code:`timescale 1ns / 100psmodule Clock();reg sysclk = 0;initial beginforever begin#10 sysclk = ~sysclk;endendLedTest ledTest(sysclk, led_0);endmoduleAm I doing it properly?

author: ale500
author_rank: Frequent Contributor
timestamp: May 28, 2020, 08:03:28 pm
content: It should create a clock with a period of 20 ns. But what is led_0 ?Without knowing what led blink does and what led_0 is, it may be enough or not.The idea of the testbench is to exercise the logic, the fsm and so on. To try corner cases. To see if the given module does what you think it does, it can do more too.I'd recommend you always define all your signals. You can also use following directive`default_nettype noneto force undefined signals to not have a default "wire [0:0]" definition, it helps finding some mistakes, specially when you forgot that the wire may need to be wider than 1 bit !.

author: Digitalio
author_rank: Contributor
timestamp: May 28, 2020, 08:47:08 pm
content: Quote from: ale500 on May 28, 2020, 08:03:28 pmThanks, good idea. Strangely, with this directive on Vivado shows a hint in the editor, but still compiles the code without any warning. I wonder if it's possible to make it fail synthesis in this case?

author: Dmeads
author_rank: Regular Contributor
timestamp: June 13, 2020, 05:00:28 am
content: Try this?Code:`timescale 1ns / 100ps`default_nettype nonemodule Clock;reg sysclk; // you got the input rightwire led_0; // the outputs from your LedTest module need to be listed as wiresalways #10 sysclk = ~sysclk; // exactly the same as "forever," just less words :)LedTest uut(sysclk, led_0); // the uut stands for Unit Under Test, and can just help you keep track of which module you're simulatinginitialbeginsysclk = 0; // intialize sysclk to 0 just like you did, just in a different place#200 // how many nanoseconds you want the sim to run, if want to run for 1000ns, change to "#1000"$finish; // tell simulator to finishend // end initialendmodule // Clock
[Vivado] Strange timing of the simulation run - Page 1
Forum section: electronics / general

author: Digitalio
author_rank: Contributor
timestamp: May 30, 2020, 05:16:56 pm
content: When I execute a command to run simulation for 1 second, Vivado runs it for 10 seconds instead (by the time shown in the simulation timeline window). Any ideas why this may be happening?
Looking for docs for Pico E-102 board. - Page 1
Forum section: electronics / general

author: amx
author_rank: Contributor
timestamp: May 17, 2020, 06:30:02 am
content: Hi, everyone!May be anybody has any docs about the Pico E-102 board?On the internet, I found only one document related to this board, but this is just a prospect.Thank you, Regards!

author: tggzzz
author_rank: Super Contributor
timestamp: May 17, 2020, 06:58:50 am
content: You'll find the answer here:here.
Failed coverage in NoC coding - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: May 16, 2020, 03:36:47 am
content: Whyhttps://github.com/promach/noc/blob/development/spidergon_top.v#L344failed ?Code:always @(posedge clk) cover(data_packet_contains_header);
need help to understand a .py script - Page 1
Forum section: electronics / general

author: CaptDon
author_rank: Super Contributor
timestamp: May 10, 2020, 09:36:56 pm
content: I have a 4meg x 8 flash device in an oscilloscope. In another forumfrom a thread over 2 years old a fellow posted a .py script to updatethe flash device. The script is only 1.82k. I own several differentprogramming units that can handle the flash device, but don't understandhow to get the script to interface to the programmer and flash device.I have posted the script. Any help would be appreciated!! Sorry thisis new to me, I have not worked with PyThon before. Thanks!!

author: FenTiger
author_rank: Regular Contributor
timestamp: May 10, 2020, 09:44:04 pm
content: From a quick look, the script doesn't interface to the programmer at all - you have to do that manually.The sequence looks likeRead the contents of the Flash somehow, into a file on your computer.Run the script, giving it the name of the Flash dump file.Write the newly-modified Flash dump file back into the memory somehow.That is, the script only modifies a dump file; you need to get it out of, and back into, the hardware another way.

author: CaptDon
author_rank: Super Contributor
timestamp: May 10, 2020, 10:21:37 pm
content: Thanks!!! That clears it up for me. I can download the flash device to a filesuch as dump.bin, then run the script in python on the file (after havingbacked up the unmodified file in case this all comes crashing down) andthen burn the newly modified dump.bin back into the flash device.Sounds good and now I understand. What a bugger that the flash deviceis a 48 pin SMT!!! Wow, I hate fine pitched SMD devices!! Too many waysto mess up!Again, many thanks!!
Don't know what adapter I need - Page 1
Forum section: electronics / general

author: msuffidy
author_rank: Frequent Contributor
timestamp: May 04, 2020, 06:21:18 am
content: A few days ago I found some for free development kits on the local internet. The kits actually have everything mostly you need but it is missing the power adapter for an old Altera Cyclone (1) board. By searching I saw someone selling one on EBAY that mentioned a 9Volt DC adapter. I have a schematic and a dv meter so I think I can tell what polarity the plug is, but I am not sure of what voltage/amps it has to be. I see on the schematic the plug goes into a chip called a SP6134 and has later a 5V and 3.3V output. Any info on this? Like are all cyclone 1 boards 9V and is like 100ma a good amperage? I don't know if it even works or will self destruct how it was configured. Also I got a Infineon XC800 usb thing and a M16C kit.This board looks identical to this one:

author: msuffidy
author_rank: Frequent Contributor
timestamp: May 05, 2020, 03:39:56 pm
content: Can this be used to somehow solve for the input voltage?

author: msuffidy
author_rank: Frequent Contributor
timestamp: May 05, 2020, 04:51:43 pm
content: Thanks for the info there!
Part selection advice (SDRAM + VGA controller) - Page 1
Forum section: electronics / general

author: Entropia
author_rank: Regular Contributor
timestamp: May 01, 2020, 04:12:33 pm
content: Hey guys. I have a small hobby project in which I want to draw graphics on a VGA monitor and also need many megabytes of RAM (also to serve as frame buffer for VGA). I've been playing with FPGAs in the university some 15 years ago (Xilinx Spartan-3E if memory serves) but have no experience since then. What would be a good choice in terms of part for my hobby project? Pin count needs to be pretty high since SDRAMs usually have 16- or 32-bit interfaces and the VGA part would also require 26 or so pins for 8-bit color with sync signals. Interface to the rest of the system has not been defined yet but something like QSPI is probably what would work for me pretty good.I would appreciate hand-solderable parts but if small dev boards are available that would also work. Thanks.

author: up8051
author_rank: Frequent Contributor
timestamp: May 01, 2020, 05:22:18 pm
content: Quote from: Entropia on May 01, 2020, 04:12:33 pmHow many RAM you need?You can use for example inexpensive module from Arrow with Altera Cyclone:https://www.arrow.com/en/products/cyc1000/arrow-development-tools(64Mbit RAM).You also can look at Gowin FPGA with buid in PSRAM/SDRAM (LittleBee Series).If you prefer Xilinx:https://numato.com/product/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdramAnd many others ...

author: asmi
author_rank: Super Contributor
timestamp: May 01, 2020, 06:17:08 pm
content: Take a look at the project in my signature. That board has HDMI port instead of VGA, but since it's open source, you can modify it to include the port. You can install up to 256 Mbytes of memory running at 333 MHz, giving you up to 10656 Mbit/s of bandwidth, which is enough to double-buffer 720p video in real time.

author: Entropia
author_rank: Regular Contributor
timestamp: May 02, 2020, 10:42:45 am
content: Thanks for the suggestions. asmi's Spartan 7 board looks like a promising start to me!
Looking for Easy-ABEL v4.x documentation (PAL, GAL) - Page 1
Forum section: electronics / general

author: marcopolo
author_rank: Regular Contributor
timestamp: April 11, 2020, 04:00:38 pm
content: Hi,Does anyone have a copy of EZ-ABEL v4.x documentation?Software available here:https://vetusware.com/download/ABEL%204/?id=13430Thanks,Marc

author: marcopolo
author_rank: Regular Contributor
timestamp: April 22, 2020, 01:41:38 pm
content: FYI, I tested this software with PAL20X10A et PALCE22V20 (used on a real board, not simulation), it work's fine

author: NivagSwerdna
author_rank: Super Contributor
timestamp: April 23, 2020, 09:59:32 am
content: I seem to have a design despite having only read selective pages of the documentation!One thing that I don't quite understand is why some of my outputs end up being negated but for some bizarre reason it has come up with a combination that actually works in my circumstances.I tinkered with istype 'pos' and 'neg' but the behaviour seems to stay the same. I should probably read some additional pages one day.

author: marcopolo
author_rank: Regular Contributor
timestamp: April 23, 2020, 10:53:13 am
content: The documents I found about ABEL are here:http://marc.retronik.fr/PLD-FPGA/ABEL/A useful book: Digital design using ABELSyntax from examples like ADDRESS = [A15..A12] is not supported by EZ-ABEL 4.30 but ADDRESS = [A15, A14, A13, A12] is OKIf you find other documents, tell me and I will add them.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: April 24, 2020, 08:42:47 am
content: I managed to get my design done with very little effort. (It was only combinatorial)I found...Code:To maintain the correct pin behavior, using detailed equations, one additionallanguage element is required: a ‘buffer’ attribute (or its complement, an ‘invert’attribute). The ‘buffer’ attribute ensures that the final implementation in a device hasno inversion between the specified D-type flip-flop and the output pin associated withQ1. For example, add the following to the declarations section:Q1 pin istype ‘buffer’;https://www.eit.lth.se/fileadmin/eit/courses/edi021/PDF_files/lattice/abel_design_manual.pdfIt's funny how all those things you learnt at college.... e.g. product terms.... seem to be accessible from the deep recesses of your brain when you need them. ABEL seems simple and appropriate... I really should have made a bit more effort and tried VHDL but I'll save that for another day.

author: marcopolo
author_rank: Regular Contributor
timestamp: April 24, 2020, 10:14:38 am
content: Thanks for the information.I added here your pdf (without the 35 pages about ispDesignExpert):http://marc.retronik.fr/PLD-FPGA/ABEL/LATTICE_ABEL_Design_Manual.pdfI don't think VHDL is appropriate for simple designs with PAL or GAL.Marc
Lattice UltraPlus timing constraint help.. - Page 1
Forum section: electronics / general

author: dpariseau
author_rank: Newbie
timestamp: April 05, 2020, 09:05:33 pm
content: I have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior. I'm pretty sure it's due to timing constraint issues (at present I have no timing constraints implemented). I'm new to specifying those and so it's a bit daunting to figure out how to resolve these issues.a) If anyone can point me to a good resource that shows how to arrive at what constraints are needed in a design that would be great. The syntax and details of implementing the constraints are readily available it's knowing what constraints to specify that's at issue...b) If anyone has "significant" experience with doing this and wants to make some extra cash looking over my design and helping me work out the constraints to resolve my issues I'd be happy to pay for the help.c) If anyone has any other ideas that might help, I'm open to them.Thanks,Dave.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 22, 2020, 06:58:25 pm
content: Even without explicit timing constraints, the tools will evaluate timing and give you the estimated max frequency at which your design can safely run. Did you take a look at this?Then, not knowing anything about your design, one thing I can say is that "marginal behavior", if you're certain 1/ that you don't exceed the above max frequency and 2/ that your design is at least behaviorally correct (did you simulate it?), is often due to clock domain crossing issues. If you're not explicitely using two different (and unsynchronized) clocks in your design, the most probable culprit would be that there is some input signal that is asynchronous to your clock, and that you're not correctly resynchronizing before "using" it (metastability issues). So we don't know squat about your design, but here's some food for thought.
Kemei FPGA? - Page 1
Forum section: electronics / general

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: May 13, 2020, 09:24:09 am
content: My new hair clippers arrived yesterday, May 12th. They were ordered April 9th on eBay so that was over a month and I needed the hair cut when I ordered them.So, you say,does this have to do with FPGAs?Well, it's clear from the pictures on eBay that these hair clippers have an FPGA in them (see picture), I wonder what sort it is? I am joking guys, I don't really think that this monster chip is inside my hair clippers but the picture was genuinely taken from the eBay post for the clippers I bought.

author: rstofer
author_rank: Super Contributor
timestamp: May 13, 2020, 01:13:28 pm
content: I got a similar setup on the 8th of May and went to work with the #3 comb (about 3/8"). The 10mm comb should be about the same. It came out pretty well, all things considered.All of which has nothing to do with FPGAs but that is a cool picture.
using FPGA: Is this possible? - Page 1
Forum section: electronics / general

author: lawrence11
author_rank: Frequent Contributor
timestamp: April 19, 2020, 03:13:39 pm
content: Having a hard time getting an understandable answer from books.Is this possible? Before I order my PCB.

author: AndyC_772
author_rank: Super Contributor
timestamp: April 19, 2020, 08:31:13 pm
content: What's your concern?It looks like a very simple use case for a single PLL. Is there something specific you're thinking of as to why it might not work?

author: langwadt
author_rank: Super Contributor
timestamp: April 19, 2020, 09:30:57 pm
content: don't make a pcb for an FPGA before you have tried most of your design and pinout in the FPGA tool, that is just a recipe for gettingbitten by some hidden limitation of what pins can do what

author: oPossum
author_rank: Super Contributor
timestamp: April 19, 2020, 09:39:05 pm
content: Download Quartus, create the PLL block, connect the pins and build the bitstream. If you can do that, then there is a good chance it will actually work.I think writing at least some of the Verilog/VHDL before commiting to a PCB would be a good idea.
SIPO shift reg circuit to verilog - Page 1
Forum section: electronics / general

author: Daxxin
author_rank: Regular Contributor
timestamp: April 04, 2020, 09:34:44 am
content: need to convert this schematic in verilog possibly for altera cpld who can help me pls

author: cruff
author_rank: Regular Contributor
timestamp: April 04, 2020, 12:53:49 pm
content: First step is to obtain the datasheet for the 4094 shift registers. Based on the description in the data sheet, implement an 8 bit shift register that matches the described behavior of the 4094, then hook them up with the appropriate connections.

author: TomS_
author_rank: Frequent Contributor
timestamp: April 06, 2020, 05:18:37 am
content: Quote from: Daxxin on April 04, 2020, 09:34:44 amThere are many many examples of shift registers available on the Internet, and some even come as examples with the vendors software.As a learning exercise it is always a good idea to try implementing something, and then ask for help if you get stuck. A shift register is stupidly easy to implement.

author: rstofer
author_rank: Super Contributor
timestamp: April 06, 2020, 05:09:09 pm
content: Spend a lot of quality time with the datasheet:http://www.ti.com/lit/ds/symlink/cd4094b.pdfLook at the Truth Table and note1) regardless of the state of Strobe, output QS is set equal to Q7 on every rising edge of the clock - make this an always block on the rising edge of the clock2) Note that QS' is set to Q7 on every falling edge of the clock - make this an always block on the falling edge of the clockSo far, we have covered lines 1,2,3, part of 5 and all of 63) Create an always block on rising edge of clock. If strobe = 1 then Q <= Q[6 downto 0] & DataIn (sort of VHDL like, I don't do Verilog). Basically, you are shifting the 7 least significant bits left and concatenating the incoming data bit whether 0 or 1.NOTE: We're going to get messed up here, bits are number 0..7 in the FPGA, not 1..8 so Q7 is actually Q, not Q. I would rewrite the Truth Table using 0..7. Be very careful!You can forget about the OC (Open Circuit) conditions, you can't do 3 state logic inside an FPGA (generally), only on pins leaving the chip. If the signals need to be MUXd on a bus, you will need to create a MUX or one will be inferred anyway.The way I see this device is as 3 always blocks or perhaps a single always block with conditionals for either edge. I think the 3 block solution is more intuitive but disjointed.One block for QS, another for QS' and a final block for the shifter.Something like this...

author: rstofer
author_rank: Super Contributor
timestamp: April 06, 2020, 05:13:48 pm
content: Once you have a module for the CD4094, you just need to plunk down two instances, add in an inverter (a Verilog ~) and wire things together.
Mystery FPGA - Page 1
Forum section: electronics / general

author: Rado123
author_rank: Newbie
timestamp: January 25, 2020, 11:43:30 pm
content: I bought a LINSN RV908M32 board on AliExpress. It seems there are at least two variants differing in the white power connector and in the orientation of JP2 (the other white connector). I was expecting a Xilinx Spartan 6 (XC6SLX16) at the hart of the board. But to my big surprise there is a mystery IC at the place where the Spartan 6 is supposed to be. Unfortunately the device has no further identifying marks besides a long number.I am not even sure that this is an FPGA. But it has the same footprint (FT256) and seems to load its configuration from the SPI-Flash.The JTAG IDCODE is 0x00014C35 and the first bytes of the SPI-Flash are01 08 8c 8c ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff cc 55 aa 33 f0 00 00 06 00 01 4c 35 2b bd c2 00.Who can identify this mystery IC or could give any further details?

author: Rado123
author_rank: Newbie
timestamp: February 02, 2020, 11:21:26 am
content: I found some hints:https://github.com/mmicko/prjtang/blob/master/docs/architecture/bitstream_format.rstIDCODE and Bitstreamformat match. It is an Anlogic FPGA.Model: eagle_20

author: ebastler
author_rank: Super Contributor
timestamp: February 02, 2020, 02:11:58 pm
content: There's a bit of discussion and some links in this thread:https://www.eevblog.com/forum/microcontrollers/chinese-fpgas-sold-by-lcsc-have-anyone-tried-them/

author: oramasdj
author_rank: Newbie
timestamp: March 21, 2020, 08:16:05 am
content: Hi my friend i need help, I bought 8 rv908m32 receiving cards but unfortunatelly I damaged 3 of them due to a failure on the 5v dc voltaje, Hi I need the bin file for rv908m32 please Im desperated, and if there is a way to reflash it by usb to rs232? due to dc voltaje failure while the rcg file was sending, Now when I turn on, the receiver card cant test the panels with the test button and there is no comunication trought the ts802d sending board, and there is no bliking green led anymore. 3 cards are bad due to bad rcg file sending.
Is it safe to swap these FPGAs? - Page 1
Forum section: electronics / general

author: giosif
author_rank: Frequent Contributor
timestamp: March 19, 2020, 09:41:07 pm
content: Hi,Apologies for the basic question (just a noob here), but I am looking to confirm if it is safe to swap a Xilinx XC3030A FPGA (complete marking below) with an identical replacement.XC3030APC84BKI9725A2004896AWith my little understanding of FPGAs and going through the datasheet, it looks like this FPGA doesn't have a local ROM, so I gather it should be safe to replace, but can someone please confirm?Thanks!

author: Scrts
author_rank: Frequent Contributor
timestamp: March 20, 2020, 12:56:55 am
content: I am not sure about this old FPGA, but you should also check speed grade. Other than that - should be no problems.
Pro design vs amateur design question (large schematic inside) - Page 1
Forum section: electronics / general

author: TheGreatNed
author_rank: Contributor
timestamp: March 24, 2020, 08:16:38 pm
content: Hello,Here is the Vivado-packaged testbench for their simple block ram device:There is the Block Ram Stimulator block (BMG_STIM_GEN) and the block ram itself (BMG_PORT), and a verifier block (CHECKER) (This is the raw RTL, I added nothing)I am very surprised at the complexity of this RTL layout -- just to simulate a simple block ram!1. There are these SYNC registers everywhere. Between every module, and seemingly a large amount to somehow synchronize the resets. Why not just feed the global reset to everything without these registers? Is this the kind of thing required for running this at high speed?2. I see these NOT gates on the clock input. Is this just a delay? What is the purpose?3. To stimulate the address they use a mux and a shifter, not sure why not just a counter.Is this actually how the pros do it?Or is this some thing generated by a tcl script that a human wouldn't write by hand?Thank you!!!!!!!

author: FenTiger
author_rank: Regular Contributor
timestamp: March 26, 2020, 05:26:48 pm
content: Quote from: TheGreatNed on March 24, 2020, 08:16:38 pmThe IBUF is an input buffer, attached to a package pin. The BUFG is a "global" buffer, which can drive the high fanout routing resources used for clocks.I'm not sure why there isn't an input buffer of some sort on the RESET line too.
Want to borrow a FPGA devboard? (in Chch, NZ). - Page 1
Forum section: electronics / general

author: hamster_nz
author_rank: Super Contributor
timestamp: March 19, 2020, 12:47:48 am
content: FPGA devboards are great at consuming hobby time without the need any external resources, other than a PC or laptop and Internet access to get the toolchains. You could spend many, many days learning the tech.I've got more boards than I can use, so if anybody is in Christchurch NZ and wants to fiddle with FPGA boards while in a possible "Enforced Staycation" feel free to send me a DM, and I might be able to get a devboard into your letterbox for you to work on, with the expectation it returns sometime in the future.I'll even answer any qns you might have, if I can.If you are in NZ but not Chch, still drop me a DM, but you will need to work out some way to pay me for courier costs (e.g. PayPal).
Logic for WVALID and AWVALID in AXI Master - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: March 16, 2020, 07:46:46 am
content: Forthis AXI master coding, how do I guaranteeAW* payloads are sent first, followed by W* payloadswithout violatingAXI protocol (a master must not wait for AWREADY to be asserted before driving WVALID)?Code:always @(posedge clk)beginif(reset)begino_axi_wvalid <= 0;endelse if(!(o_axi_wvalid && !i_axi_wready))begin// Note that both o_axi_awsize , o_axi_awlen are of hardware constants, so no multiply hardware// since this is for testing, WDATA just uses some values up to the total size of the write address space// see https://i.imgur.com/LBO9pQz.png in which AW* payloads are sent first, followed by W* payloads// Note: a master must not wait for AWREADY to be asserted before driving WVALIDo_axi_wvalid <= (o_axi_wlast) ? 0 :(o_axi_wdata < (o_axi_awsize*o_axi_awlen)) && o_axi_awvalid;endend

author: asmi
author_rank: Super Contributor
timestamp: March 16, 2020, 05:13:02 pm
content: Not sure I understand the question. Typically you will have separate states of your FSM for AW and W stages. The way it's supposed to work is as follows: you place the data on a bus and assert *VALID signal. Then you keep this data until *READY is also high (AXI mandates than once you set your *VALID signal, you are not allowed to change anything on a bus until transfer occurs), then you advance your FSM to W state (AXI states that transfer only happens when both *VALID and *READY signals are high on the same clock edge). You've got to remember than when you set some signal via non-blocking assignment, it will only become "visible" to receiver on the next clock edge, so you can't check *READY signal at a time you're asserting *VALID and assume it will be the same on a next clock edge, when the transfer actually occurs.Also - for the last transfer in a burst you've got to assert both *VALID and *LAST signals.Finally, if you use Vivado, I highly recommend to use AXI Verification IP as it both helps to stimulate your AXI bus interfaces using very simple SV code, as well as to verify that transactions your module is performing are AXI-compliant (it will halt the simulation if it observes any activity on any AXI channel that is not compliant to the specification).

author: promach
author_rank: Frequent Contributor
timestamp: March 17, 2020, 01:45:01 am
content: In thepc_status error bit location, is it bit #32 because in the following simulation waveform, BVALID is never asserted high during the time when pc_status error bit #32 is asserted ?

author: promach
author_rank: Frequent Contributor
timestamp: March 17, 2020, 03:33:55 pm
content: Ok, I have solved the above pc_status AXI_ERRS_BRESP_WLAST error.Now, I have anentirely different pc_status AXI_ERRM_WSTRB issue.QuoteWhat does it mean byThe information on the low-order address lines must be consistent with the information on the byte lane strobes.?
[Solved]Cannot download Quartus II web edition - Page 1
Forum section: electronics / general

author: chris_leyson
author_rank: Super Contributor
timestamp: March 14, 2020, 12:03:12 pm
content: I'm trying to download Quartus II web edition 13.1 and the links on the Intel download page don't go anywhere just return javascriptvoid(0). Is the download site broken ?This seems to workdownload.altera.com/akdlm/software/acdsinst/13.1/162/ib_tar/Quartus-web-13.1.0.162-windows.tar
Looking For ViewDraw - Page 1
Forum section: electronics / general

author: SimonR
author_rank: Regular Contributor
timestamp: March 10, 2020, 03:40:13 pm
content: My colleague has to modify a very old xilinx project that was built using Viewdraw.As is the way of these things we have source file backups but not the application.Does anyone know where we can find a copy ViewDraw 4.1 or higher or ViewWorks possibly with install disks

author: joeqsmith
author_rank: Super Contributor
timestamp: March 10, 2020, 05:12:53 pm
content: If they are trying to design in a new part using an HDL and only need the schematics in order to port the design, I may be able to help.

author: SimonR
author_rank: Regular Contributor
timestamp: March 11, 2020, 09:45:08 am
content: Thanks,As far as I know they are hoping to modify an existing design.I'll pass on your offer of help.
Internal Oscillator on a Altera Max V using Quartus - Page 1
Forum section: electronics / general

author: Munch
author_rank: Newbie
timestamp: March 03, 2020, 02:50:04 pm
content: Good Afternoon All,Long time EEVBlog and Forums follower, but first time poster.I have recently been working on a project where i specked a CPLD. I have used CPLD's before, always Altera and using Quartus. The program that I am running on the CPLD sets some address lines to I2C devices depending on which slot the card has been installed into on the backplane of my product. Now when I was choosing the CPLD I got suckered into the Internal Oscillator feature of a MAX V CPLD and didn't add any external oscillator hardware to my board, a move that I am know regretting massively.I think that I have now been able to implement the Internal Oscillator function, the code compiles, however I don't seem to be able to produce a programming file. Weather the code actually works is another matter.Would someone be able to look at my project and point me in the right direction. Attached is a archived version of the project. I have been using Quartus II v10.1.If this is not the best place to ask CPLD related Altera/intel questions, can anyone point me towards a better place. The Intel forums are pretty useless.RegardsM

author: Daixiwen
author_rank: Frequent Contributor
timestamp: March 05, 2020, 07:56:46 am
content: I have Quartus II 11.1, but I could open and compile your project without any problem and it did generate a programming file.Just make sure you use the "Start Compilation" button, next to the stop sign, and not the "Start Analysis & Synthesis" one.Then if you go in the reports > Assembler > Generated files you will find a list with the output files and where they are.Quote from: Munch on March 03, 2020, 02:50:04 pmThis is the correct place AFAIK. And yes, Intel completely botched the forums, I haven't been there in months

author: Munch
author_rank: Newbie
timestamp: March 06, 2020, 08:49:49 am
content: Hi Daixiwen,Thanks for your support. I too re-setup the project in Quartus Prime 18.1, compiled and it all worked perfectly.
Recording data and using it in a verilog testbench - Page 1
Forum section: electronics / general

author: TheGreatNed
author_rank: Contributor
timestamp: February 27, 2020, 07:00:44 pm
content: Hi,Is it possible to record 10 cycles of a waveform (say 10000 samples) coming into my adc and then save that data for simulation purposes? I'd love to be able to simulate some dsp functions with modelsim (or maybe there's a more appropriate simulator). I'm using quartus prime.Thank you

author: ale500
author_rank: Frequent Contributor
timestamp: February 27, 2020, 07:27:46 pm
content: Yes, of course.Recording the waveform to a text file shouldn't present much of a problem as long as you have a way to get the data to the pc.Reading the data from verilog can be done by using $fread (works a bit like fscanf), or directly into a register array using $readmemh or $readmemb.here there is a minimal description of the available functions:https://www.hdlworks.com/hdl_corner/verilog_ref/items/SystemFileTasks.htm. I'm sure there is also some examples in fpga4fun.

author: TheGreatNed
author_rank: Contributor
timestamp: February 28, 2020, 02:03:39 am
content: Ahh ok, I need to get a memory or hex file of my 10000 samples on pc somehow.What would your preference be in getting the data on the pc? Based on your recommendation I guess I could try to store the data in block ram (need 10000 * 14bits = 17,500 bytes), then send the data over a UART link to a computer. Then i could simply copy the data right out of the terminal into a text file. Is this a good approach?Or is there some magic I could do by using a nios ii processor somehow?

author: ale500
author_rank: Frequent Contributor
timestamp: February 28, 2020, 04:10:32 pm
content: If you get the data via UART, then the dump from the terminal program could be used after some "conditioning", like number formatting. I'd assume that the ADC is connected to "something" you can use to record the waveform, even an oscilloscope could help if it has something like a USB port and enough sample memory. Here you may have to elaborate a bit how you generate the signal and how you capture it. For test purposes, you can just generate the waveform in the pc with a program/script. Once the algorithms work, you can switch to work on the real signal.

author: ejeffrey
author_rank: Super Contributor
timestamp: February 28, 2020, 05:02:40 pm
content: You can use signal tap or the in system memory editor to upload and download waveforms.