JFET biasing and Vds - Page 1
Forum section: electronics / beginners

author: devttys0
author_rank: Contributor
timestamp: April 06, 2015, 01:52:07 am
content: I’m following along with chapter 19 of “Principles of Electronics” from talkingelectronics.com (http://www.talkingelectronics.com/Download%20eBooks/Principles%20of%20electronics/CH-19.pdf), which discusses JFETs, but I’m a bit confused about the required value of Vds when biasing the JFET.TL;DR: when biasing a JFET, how do you know the minimum Vds voltage needed in order to remain in the saturation region?Specifically, example 19.16 (page 522) has me puzzled. The example is to calculate the appropriate drain and source resistors for a self-biased, common-source n-channel JFET circuit. The stated JFET parameters are Idss = 15mA and Vgs(off) = -8V. The example then proceeds to bias the source voltage at 2.35V and the drain voltage at 6V (6V was chosen in the example because it is 1/2 of Vdd).That part is pretty simple, but earlier on in this chapter (p. 513-514) it stated that the Vds(sat) (“pinch-off”) voltage for a JFET is equal in magnitude to Vgs(off), but of the opposite sign. So in this case, that would make Vds(sat) 8V, while the circuit’s Vds is biased to only 6-2.35 = 3.65V.Wouldn’t that put the JFET in the ohmic region, rather than the desired saturation region? I feel like I’m missing something very simple here.I know from looking at some "typical" JFET output characteristic curves that Vds(sat) decreases as Vgs becomes more negative, so maybe that’s why Vds can be much lower than what I expected? But if that’s the case, how do you calculate what your minimum Vds should be for a given Vgs in order to remain in the saturation region?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 06, 2015, 03:37:21 am
content: Are... we talking about the same PDFs here? Because I don't see a "16" on page 522, and I don't see 15mA or -8V anywhere.The trick is Fig 19.8. Which is horribly cartoony, so let's look at a *real* one instead!https://www.fairchildsemi.com/datasheets/MM/MMBFJ112.pdfFig.3 (Id vs. Vds for given Vgs). See how at Vgs=0, it, well... it's off the graph unfortunately. But it should level off around 2V, because Vgs(off) = -2V. At Vgs = -1V, it's leveled off around 1V. And at -1.4V, it's around 0.6V... (it looks like 0.4V even, but it's hard to say at this resolution).The current saturation voltage* decreases with Vgs; indeed it's Vdg which defines that point.You didn't mention what Vgs the example is/should be biased for; if it's near pinchoff, it may very well be in the current saturation region. But if it's just "grid leak biased" (resistor from gate to ground, signal coupled in via capacitor), there simply isn't enough supply voltage in the circuit, regardless, and as you note -- it must be in the ohmic region somewhere. Which isn't necessarily a bad thing, but that will reduce voltage gain (not usually desirable), output resistance (maybe not entirely bad?), and make it a whole lot more complicated to solve for the biasing conditions (because now source current depends on drain voltage, which depends on G-S voltage, which depends on... oh boy..).(*I want to be specific and always use "current saturation" when referring to the constant-current region of JFETs, because inevery single other device in existence, saturation has referred to voltage saturation (the JFET ohmic region). Why, and WHO, decided to come up with this bit of madness... I have no idea.)Tim

author: devttys0
author_rank: Contributor
timestamp: April 06, 2015, 01:13:41 pm
content: QuoteYes, example 19.16 is at the very top of page 522 (note I'm going off the page numbers printed in the top left corner of the page); but no matter, your answer was just what I needed! Looking at a real Id vs Vgs graph was a big help!QuoteYes, the example just ties the gate to ground via a large resistor, so it is definitely operating in the ohmic region. In fairness, I think the example was just to show how to solve the equations, as it isn't a very practical example (it assumes well-defined Vgs(off) and Idss parameters, there are no requirements for gain, output impedance, etc). But still, even after 15 or so examples, the Vds requirements hadn't really been addressed, so this cleared up a lot for me, thanks!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 07, 2015, 04:17:49 am
content: I was looking at "552" for some reason