4 layers and power plane. - Page 1
Forum section: electronics / projects

author: kvresto
author_rank: Regular Contributor
timestamp: May 04, 2015, 09:21:35 am
content: I Everyone.I have a project which is a 4 layer design, and I plan to connect the output of a 3.3V reg to the power plane layer. This layer measures 123mm x 88mm, and I was wondering are there any issues with doing this, for example anything to do with noise, filtering, regulation, routing etc? I'm sure this gets done all the time, but can I assume this will work without issues the first time?CheersKvresto.

author: dmills
author_rank: Super Contributor
timestamp: May 04, 2015, 11:19:20 am
content: Way more often then not it will be fine.It helps to scatter a few deliberately lossy decoupling caps around (in addition to the rather too good MLCCs), either small elcos, tants (But massively over rate the voltage on them if going here), or say 10uF X7R with a ohm or so of series resistor, just to damp any resonances.Of course if you are doing something with really high sped serdes and enormous FPGAs then it takes rather more thinking about, but for general stuff it usually just works.Regards, Dan.

author: kvresto
author_rank: Regular Contributor
timestamp: May 05, 2015, 12:01:11 am
content: Great, thanks dmills.

author: yramgu
author_rank: Contributor
timestamp: May 05, 2015, 07:32:54 pm
content: If you're going for 4 layers make sure the outer layers are GND planes, so they can act as efficient shields. Put the 3V rail on an inner layer

author: kvresto
author_rank: Regular Contributor
timestamp: May 06, 2015, 11:23:18 pm
content: Thanks yramgu.top=trackssecond=gndthird=powerbottom=tracksDo you recommend I place a ground layer also on the top and/or bottom as well as the second layer? Will there be any noise or other issues doing this?kvresto

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 06, 2015, 11:46:17 pm
content: I've had some truly noisy situations, and NEVER had a single confirmed upset to onboard digital signals, using the above stackup.Inner signal layers can provide better shielding for extremely sensitive signals (RF, analog), but for almost absolutely everything else, it's only a nuisance, both for routing (all your components are on the outside, anyway -- unless you pay $$$^3 for embedded R/C parts!) and testing/rework (where'd all your traces and vias go? oh that's right, D'OH!).And even then, it's not *too* much help, because components are still on the surface, so their pins (and whatever inner workings couple through the package) are still radiating externally, necessitating shield cans and glue-on ferrite plates and stuff.There is one more reason for buried anything: somewhat improved corrosion resistance, and reverse engineering pain. I believe there are mil specs suggesting this approach -- *every* single SMT pad connects immediately to a via (preferably tented/plugged), and *all* the routing is done inside, except maybe for only the most adjacent surface routes. Multiple power planes might be used, in a high layer stackup ($$, but not as bad as the gold dipped rad-hard parts you'd be using in such an assembly anyway).Post-golden-age Tek equipment shows this pattern, like their TDSxxx series. Largely 1206 SMT, SOIC and PLCC. Grid placement rules, lots of clearance, lots of rows. This method doesn't even save space over THT assemblies (comparing, say, the component density of 475 era boards), but that's what they did.I wouldn't suggest following such practices for modern assemblies, especially if you need testing and rework capability.Tim

author: kjs
author_rank: Regular Contributor
timestamp: May 06, 2015, 11:54:55 pm
content: Quote from: dmills on May 04, 2015, 11:19:20 amwe found X5R 1uF 0402 (Taiyo Yuden, Murata, Panasonic, Samsung) capacitors (10V - up to 5V- and 16V -up to 10V) to be excellent for such use (w/o series resistors). They have relatively low series resonance but not very pronounced and act as excellent bypass into the GHz range.For higher voltages the Taiyo Yuden 1uF 0603 50V are excellent too.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: May 07, 2015, 12:37:44 am
content: Quote from: T3sl4co1l on May 06, 2015, 11:46:17 pmHDI is the only way to build cell phones. Pretty much everything is routed on the inside.http://www.hdihandbook.com/

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 07, 2015, 01:56:02 am
content: Quote from: Alex Eisenhut on May 07, 2015, 12:37:44 amGeez, what a useless website; one would hope they at least make some definitions inside the text itself (assuming you were more than lukewarm enough to consider purchasing such a thing). None of the descriptions (not even summaries, really) even say what "HDI" is.This looks much more informative,http://www.ttmtech.com/products/prod_hdi.aspxbut seems to encompass only fine pitch/scale methods and filled vias, not whether or not internal signals are desirable or necessary. It's true that you won't get much signal routing on the outside, due to sheer component density, but that's a consequence of the density, a form factor driven requirement, not an electrical or environmental thing?Tim

author: kjs
author_rank: Regular Contributor
timestamp: May 07, 2015, 01:59:56 am
content: for cellphones everything is cost and shielding is expensive. That's why they shield the stuff inside the board. What helps them is that the screens get larger and larger (phone size) and the integration is very high.

author: yramgu
author_rank: Contributor
timestamp: May 07, 2015, 07:47:06 am
content: QuoteSpot on, I work in RFAlthough I disagree that it's a nuisance for routing and debugging; i do that everyday. We usually design on 4 layers with the following configuration:Top = GND+tracks (the lesser the better)Inner 1 = power + tracksInner 2 =power + tracksBottom = GND + tracks (the lesser the better)("Mobile Phone" routing really is an extreme case)The agressive signals such as clocks are routed on the inner layers. And yes, we do this mainly to protect analog signals from the digital ones. With today's chips, it's very difficult to upset a digital signal, but very easy to upset an analog one.The other main reason to try and shield agressive signals is radio standards, which are VERY time and money-consuming. But if this is a DIY project, this is of no concern.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: May 07, 2015, 11:13:31 am
content: Quote from: kjs on May 07, 2015, 01:59:56 amShielding has nothing to do with it, they're still covered in RF cans, it's that there is no other way to build something that dense at that size if you're doing boring old dog bones and via escapes and what not.