Are These Blind  Vias Manufacturable in My 12 -Layer Stackup? - Page 1
Forum section: electronics / projects

author: electronx
author_rank: Regular Contributor
timestamp: April 25, 2025, 04:25:26 pm
content: Hi everyone,I'm working on a 12-layer PCB and created this stackup with various buried vias. At this stage, the via transitions were placed somewhat arbitrarily—mainly to simulate complex routing scenarios.Now I'm wondering:1. Are the via structures in this stackup **manufacturable**, or are there violations that would make fabrication difficult or impossible?2. Is there any rule or best practice that via transitions should follow a **symmetric or structured pattern** across the stackup?3. Does the **lack of symmetry** in via planning (e.g., transitions likeThru 1:12Blind 1:3Blind 3:12Blind 1:5Blind 5:12Blind 1:10Blind 10:12Blind 1:2Blind 11:12Blind 7:12Blind 1:4Blind 6:12Blind 4:12Blind 1:7) create reliability or production issues?4. Do manufacturers typically require **consistent and well-defined via zones** (e.g., L1–L2 for blind, L2–L3 for buried, etc.) throughout the board?5. Would this stackup be considered acceptable by most high-end fabs, or should I redesign it with more standardized via pairs?Attached is the stackup diagramhere is nvidia dev board stack up the production cost is 4000 dollarsi wonder if there is a difference between my stackup design and its production

author: Kurets
author_rank: Regular Contributor
timestamp: April 25, 2025, 05:56:46 pm
content: With exception of outer layer microvias, buried vias require a kind of sub-board design. During manufacturing they are typically drilled through and plated before laminating the next layer. The stackup of Nvidia looks to use this in the centre and then they have overlapping layers with blind "outer to L1" followed by laminating a new outer layer, new vias, rinse and repeat.Your stackup is not manufacturable as there is no way to perform drill, plate, laminate in a realistic sequential fashion.

author: electronx
author_rank: Regular Contributor
timestamp: April 25, 2025, 07:17:47 pm
content: Are you saying that in this case I can only use burried via?

author: electronx
author_rank: Regular Contributor
timestamp: April 26, 2025, 09:49:24 am
content: I talked to the manufacturersthey said it is possible with" any layer pcb " "ELIC"3600 dollars for 5 pcb , which means a price of 750 dollars per pcb

author: BadeBhaiya
author_rank: Regular Contributor
timestamp: April 26, 2025, 10:40:37 am
content: I think using stacked microvias may help here. My microvias only go one layer down at a time. If i have to go lower, i use another microvia and stack itThe fab we use never complains about it, so I'm guessing it's fine?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: April 26, 2025, 11:48:44 am
content: The NVidia stackup looks like a core, layers added in pairs (top and bottom) then drilled through, and micro via's added before the rinse and reapeat.Another (I think common) way of producing PCB's is to first make two or more (multi layer) PCB's (with only though via's) and then laminate them together.Arbitrary via stackup can be made with LTCC (and also many layers) but I have no idea of the cost. Complex via stackup is (I guess) at no extra cost for LTCC, because it is inherent in the LTCC process.I'm a bit surprised that your PCB stackup can even be manufactured, but then again, nearly anything can be done these days, as long as someone is willing to pay enough for it. A few years ago I read a story about a PCB designer that goes out hunting for PCB's and then makes an offer for re-routing the PCB. One of the examples was something like, "reduce a 12 layer PCB to 8 layers, while maintaining signal integrity & EMC requirements etc", and he offered to do that for EUR 12k. The company found his price ridiculous and laughed at him. A few days later that company did some internal calculations on their production costs. They called him back and he got the job.Maybe cost is not such a big issue for the prototyping stage. But what happens after that? How many of these PCB's do you expect to make?I would not even attempt to start to make a 12 layer PCB without first doing some more research about recommended layer stackups and relative costs. Optimizing for production costs is a very important part of engineering in the first place.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: April 26, 2025, 12:08:58 pm
content: I did a bit of reading about ELIC (Every Layer Inter Connect). A.k.a HDI (High Density Interconnect). It's easy to find references of it's capabilities and how wonderful it is, but in the 20 minutes I put into it, I did not find a good readup of how the actual manufacturing process works.I did find one reference that claims that IPC discourages all though via's for ELIC, those are apparently a reliability issue. I also found some online ordering forms, where HDI is a simple checkbox, so you can do some comparisons yourself.

author: electronx
author_rank: Regular Contributor
timestamp: April 26, 2025, 12:20:06 pm
content: Generally, they do not want stackup termination for the planes on both sides of the core layer, so we see stacked microvias in the form of.I am making an image processing computer for an industrial system,My solution is to make the number of layers 12 and make both sides of the core gndso if necessary I will make it 5+4n+5 soif necessary I can convert it to the format that ipc wants2+n+23+n+34+n+45+n+5its how ipc wantsWhen I examined the nvidia stackup, I saw transitions fromlayer 1 to layer 4layer 4 to layer 7 (cannot go directly to layer 6 because it includes core)layer 7 to layer 6However, ipc does not want the stacked structure to be more than 3 planes in this hdi design.--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

author: Doctorandus_P
author_rank: Super Contributor
timestamp: April 26, 2025, 12:46:53 pm
content: Just curious: Why do you even want to make a 12 layer PCB? Do you really need that density, or is it a lack of experience or do you want to reduce design time? Maybe other reasons?

author: electronx
author_rank: Regular Contributor
timestamp: April 26, 2025, 12:50:32 pm
content: a design that includes mipi csi and pcie gen4 x16 , MGBE ethernet , besides there are plenty of usb 3.1 and the bga pins are quite close to other pads (700 pin for only one bga)(pcie and mipi csi vias intersect)+ I don't like splitting signal lines, I prefer point to point if possible.At this stage, it is more important that the product works functionally.If we want to finish the design made by nvidia in 10 layers in about 1 month, I think I should raid this (ım only one in that project)If someone can do it in a month, I really bow down to them.The cost is currently under $1000, so it is not a problem for the prototype, it is sufficient to work,more complex structures will be added after the workif I find time, I can reduce the number of layers with signal simulations for a cheaper priceIf you have different thoughts please let me know,

author: electronx
author_rank: Regular Contributor
timestamp: April 26, 2025, 01:12:08 pm
content: One of pcbway's previous recommended design rules (I think they can produce anylayer pcbs now)If this is not required for anyler pcb (via can start on top of the core), I can easily drop to 10 layers.

author: electronx
author_rank: Regular Contributor
timestamp: July 29, 2025, 09:23:24 am
content: Good news, it in production I learned all steps and ı talked with a lot manufacturer ,if u need to know something you guys can ask me . Best regards

author: Doctorandus_P
author_rank: Super Contributor
timestamp: July 29, 2025, 04:32:34 pm
content: In the mean time, I've also read a bit about ELIC (AnyLayerInterconnect), but industry is apparently setting on the name HDI (HighDensityInterconnect) One of the remarks was to avoid stacking too many micro via's on top of each other. Not because of manufacturing problems, but because of the reliability of the finished PCB. Apparently the high stacks have a tendency to develop cracks, either due to mechanical stress, or thermal cycling.

author: electronx
author_rank: Regular Contributor
timestamp: August 01, 2025, 05:13:36 am
content: In any layer PCB, the core material thickness should be under 0.1 mm because laser drilling of this size requires this. This is called any layer. If you use a thicker core, you need to drill a minimum 0.15 mm mechanical through hole. These are 4+2+4 HDI boards with a 4-step configuration. This structure is more expensive than ELIC. Yes, IPC doesn't require you to use more than three stacked vias in a row, but I've seen nine-stacked vias in cross-sections on iPhones, all of which are ELIC. Considering that these phones are constantly moving and vibrating, it's clear that they're not compatible with IPC.