toslink (s/pdif) mixer - Page 1
Forum section: electronics / projects

author: duck
author_rank: Newbie
timestamp: July 13, 2018, 07:31:03 pm
content: Hi! I have an (apparently) unique problem where I would like to mix togheter three optical audio signals (s/pdif over toslink connector) in that such a device is not made by anyone. The closest thing I've seen is the Roland M-1000 which is a multi-thousand dollar device, discontinued and rare as hen's teeth. What I DON'T want is a switch (even if it's automatic).Now it seems to me that this should be a fairly simple thing to put together if you target the lowest spec of s/pdif (48kHz stereo sound), using toslink optical decoders and a DSP to mix them into a single optical encoder, but I have zero knowledge of how to put a circuit together. I know that s/pdif signals cannot be mixed without decoding because of some clock property, but if you first decode them into a PCM stream it should be no problem?So my question is, does this seem like a thing that could be done to you? Would someone be interested in helping me design it? Volume control or anything like dolby decoding is not necessary (but would be a nice bonus).duck

author: In Vacuo Veritas
author_rank: Frequent Contributor
timestamp: July 13, 2018, 07:41:41 pm
content: It could be done, but it's 2018, why are you still using this stuff?Ask yourself *why* it's a unique problem, anyone with the problem probably moved to something better decades ago.Just buy three of these and call it a day.https://www.amazon.com/Digital-Optical-Coaxial-Toslink-Converter/dp/B01FJJXGZW

author: sokoloff
author_rank: Super Contributor
timestamp: July 13, 2018, 07:49:14 pm
content: Three of those doesn't do what OP is asking about without adding an analog mixer (and, depending on the use case, another stereo A/D convertor).

author: dmills
author_rank: Super Contributor
timestamp: July 13, 2018, 07:58:57 pm
content: Are the three sources locked to a common word clock?If not you will want at least two ASRCs (Maybe three is you want to lock the output to an externally applied word clock, sometimes rather handy), feels more like a good application for a very small Spartan 7 or similar rather then a micro.You could I suppose do it with external hardware ASRC (Crystal semi or TI being the obvious vendors), or even something like a SHARC (But watch the cost of the toolchain), but meh, a small FPGA is the natural approach IMHO.Regards, Dan.

author: duck
author_rank: Newbie
timestamp: July 13, 2018, 08:04:05 pm
content: Quote from: dmills on July 13, 2018, 07:58:57 pmThe sources are entirely independent, and I can't lock them to a clock, think consumer devices.I don't know what an ASRC is, can you expand?I suppose a FPGA could do it, but it could do anything after all :-) Are DSP type chips for mixing not a thing?

author: dmills
author_rank: Super Contributor
timestamp: July 13, 2018, 08:17:22 pm
content: ASRC = Asynchronous Sample Rate Converter.Magic that takes an input having a more or less arbitrary sample rate and sample phase and produces an output locked to a reference, they are really just banks of polyphase filters and a rate estimator, but to a first approximation, magic will do.Sure DSPs exist, as I say a Sharc could do it trivially, and some even have banks of ASRCs built in, but the cost of the AD tools will kill you.Regards, Dan.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 13, 2018, 08:20:23 pm
content: If the sources are nearly the same sample rate (but not exactly), you could just buffer at least N-1 inputs and duplicate or drop samples when the signal is near zero for some number of samples.

author: duck
author_rank: Newbie
timestamp: July 13, 2018, 08:26:18 pm
content: Well I'm glad you seem to think that my idea isn't completely unworkable at least :-)

author: Doctorandus_P
author_rank: Super Contributor
timestamp: July 13, 2018, 09:50:01 pm
content: Have you thought about a small pc with a bunch of USB sound cards?

author: Marco
author_rank: Super Contributor
timestamp: July 13, 2018, 10:38:52 pm
content: Quote from: blueskull on July 13, 2018, 08:53:42 pmOnly for your 24 bits golden earsFor people with 16 bit ears you can do ita lot cheaper.

author: David Hess
author_rank: Super Contributor
timestamp: July 14, 2018, 12:49:50 am
content: The difficulty of implementing ASRC for a single project would lead me to using 3 audio DACs, analog mixing, and 1 audio ADC to produce a single digital output.

author: AndyC_772
author_rank: Super Contributor
timestamp: July 14, 2018, 08:12:04 am
content: I'd go with dropping or duplicating samples. I've done this before and simply cannot hear it at all when it happens.Personally I'd use a small FPGA to decode the SPDIF streams, add the samples together, then re-encode. Maybe add a PIC with an ADC if you want volume knobs.Doing it this way is relatively straightforward for an experienced engineer, but sadly not really a beginner's project.If you need a simpler solution that you can buy off the shelf, I'd go with 3x DACs, a few resistors, and an ADC.

author: Bassman59
author_rank: Super Contributor
timestamp: July 14, 2018, 06:11:45 pm
content: Quote from: duck on July 13, 2018, 07:31:03 pmThis is quite possibly an application for an XMOS part! They offer code for S/PDIF receive and transmit as well as ASRC.

author: hamster_nz
author_rank: Super Contributor
timestamp: July 16, 2018, 11:43:43 am
content: I've been thinking about this off and onIf everything is taken to a common intermediate sample rate first, and then you resample that stream at different phases then things are not too hard.To take 44.1kS/s or 48kS/sand convert to 100,800 S/s it is about 10M MACs (Multiply Accumulates) per channel per second. (96kS/s streams would would take twice as many)Then resampling those streams at a different clock phases (based on the input clock) would be another 10M MAC per channel per second.The mixing of the multiple streams now that they are on a common clock would be trivial.Sample rate conversion to the output rate (would be another 10M MACs per second or so.End-to-end latency would be around 200 samples - approx 5ms or so.For an 8 stereo channels mixed into one stereo channel would need about 340,000.000 MAC operations per second - reachable with most DSP or FPGA hardware

author: Boscoe
author_rank: Frequent Contributor
timestamp: July 16, 2018, 01:51:18 pm
content: This is very trivial on an FPGA with some jelly bean logic to do the SPDIF to TTL conversion. You could use 3/4 WM8804s if you don't want to have to do the SPDIF to TTL to PCM conversion (I wouldn't blame you). Very easy to write a sample rate detector and a some logic to drop samples. The samples then go into a simple, small FIFO. You generate an output clock based on the input clocks from one of the WM8804, sample the three FIFOs create the average and chuck it out on I2S.

author: EdHayes3
author_rank: Newbie
timestamp: January 18, 2021, 04:06:29 am
content: What was your solution to this toslink mixer dilemma?

author: ehughes
author_rank: Frequent Contributor
timestamp: January 21, 2021, 02:18:11 pm
content: The Analog Devices SigmaDSP's have lots of ASRC's built in. The programming tool is quite friendly. You may need a few SPDIF/AES3 to I2C Receivers (SigmalDSP only has 1 SPDIF reciever) to get to some parallel I2S streams but you would probably have the mixer built in 5 minutes w/ the SigmaDSP tool.https://www.analog.com/en/products/adau1467.htmlThey are design to self boot (No External MCU needed) and have ADC inputs for your controls. It will be about 10x less expensive than an FPGA and the programming/development time will be very quick. It will probably take you more time to get the AES3/SPDIF receivers wired in.

author: Eusebius
author_rank: Newbie
timestamp: April 30, 2021, 12:14:11 am
content: Anyone interested in such a device, yet?

author: Smokey
author_rank: Super Contributor
timestamp: December 07, 2022, 04:46:37 am
content: Quote from: Eusebius on April 30, 2021, 12:14:11 amI could use it if it existed. My luck it would be out of stock like every other part I want to use these days.

author: jonpaul
author_rank: Super Contributor
timestamp: December 07, 2022, 04:43:01 pm
content: do it in analog3x TOS-link >>>3 x DACsVoilà 3 analog signals.Mix as desired.ADC >> TOS-link if desired.Problem solved!JonPS TOS-link is Obselete the optos are hard to find.Never good quality, we use AES 3id or AES/EBU

author: Nominal Animal
author_rank: Super Contributor
timestamp: December 08, 2022, 11:30:33 am
content: Cirrus Logic CS8422chip can receive S/PDIF and AES3 input and do sample rate conversion to a master clock (and even recover the original sample clock), so three of those; and a small FPGA, for example an iCE40 (I likeOlimex dev boards) running at 32×3.072 = 98.304 MHz, or a microcontroller running at a suitable multiple of 3.072 MHz so it can use e.g. its SPI MOSI pin with a 3.072 MHz clock to generate the outgoing S/PDIF data stream, ought to work.Upside is that those CS8422 chips are quite capable, so things like sample depth (20 or 24 bit) or sample rate (44100 Hz or 48000 Hz) would be no problem.Downside is those CS8422 chips cost about 18€ apiece at Mouser (but they are in stock). Mouser does also have TOTX1350(F) transmitters (11€ apiece) and TORX1355(F) receivers (14€ apiece) in stock. Just the main components would cost over 100 euros, and that's excluding the microcontroller or FPGA or any passives needed. Ouch.Cliff manufactures/'d compatible Toslink transmitters and receivers that for example Conrad sells for 3.70€ (FCR684208T transmitter) and 4.80€ (FC684208R receiver) apiece. TME has some OTJ-5 FCR684205T transmitters in stock for 1.71€ apiece (!) and some ORJ-3 FCR6842032R receivers for 3€ apiece, so those can be found at a more reasonable price. Micro-semiconductor.com claims they have CS8422 in 32QFN in stock for under $5 apiece, but for orders under $1000, shipping will cost $60-$110.A DIY approach therefore looks doable at a reasonable budget, and quite possibly with features not found even in the pro equipment, but would be quite an interesting project and not a small undertaking.With a fast FPGA clocked from a multiple of 3.072 MHz with all S/PDIF sources using 48 kHz sample rates, one ought to be able to do it all within the FPGA. Keeping track of the differential Manchester code (biphase mark code) cycle length in FPGA clocks, one should be able to determine the clock drift.One could use a modest-sized FIFO queue of samples, and when the drift exceeds a full sample, do a fixed-size one-sample expansion or contraction resampling within the buffer. It isn't as perfect as continuous FFT-based resampling, but I bet the distortion caused can be low enough to be within the inherent noise levels. It's the 44.1kHz to 48kHz resampling that is annoying, because it's essentially a 147→160 sample conversion.An alternate option would be to just do continuous resampling using cubic interpolation, so that each output sample is determined by four input samples, per channel. Using Hermite splines, the response is pretty good (with aliasing well below 40dB), so the actual audio quality should be good to acceptable; just perhaps not "excellent". Sinc interpolation would give much better results – in theory,perfect–, but the normalized sinc function needed is quite computationally heavy and extends far (needs many samples); especially compared to cubic Hermite splines, which are just third degree polynomials.

author: cncjerry
author_rank: Unknown
timestamp: December 10, 2022, 04:47:39 pm
content: There's a company, wondom(sic) that makes little dsp modules, including one with a 14xx series audio dsp . more than one has dual channel audio input from I2C. Coupled with, and I always get the name wrong, AD's visual dsp, dsp studio, or something like that, visual studio? you can roll your own in a few hours. Their modules work well, cheap, and are used in lots of powered speakers. I have a dozen of them. I think the 14xx series has 4 stereo i2c inputs or 8 channels, can't remember, could be wrong. You need a crystal semi receiver to go from spid/f to i2c but after that, you have full control with the 14xx and the dsp software.