PCIexpress  Topology - reduce root complex - Page 1
Forum section: electronics / projects

author: rakeshm55
author_rank: Regular Contributor
timestamp: June 11, 2018, 04:35:17 am
content: Hi,I have a PCI express scheme as shown in Image attached.In this there are two Root Complex (RC) one in Module A and other in Module B communicating point to point. My requirement is to have communication between1. Module A to B and vice versa2. Module B to C and vice versa3. Module A to C and Vice VersaSince Module A to C there is no PCIe path(Due to unavailability of PCI core/power of PCI core already there are 4), I plan to go with a Synchronous McBSP interface. Here the speed is limited to 50Mbps.There are two modes of operation one in which data is transmitted form Module A to Module B gets processed and then transmitted to Module C or Vice Versa.Another is data Transmitted from Module A to Module C Bypassing Module B(Currently McBSP). Speed of McBSP and PCIe there is an asymmetry.Is there any means by which I could establish Communication between Module A and Module C via existing PCIe paths? ie Module A and Module C could communicate directly with Module B just forwarding.Please advice

author: Berni
author_rank: Super Contributor
timestamp: June 11, 2018, 05:11:11 am
content: There is not enough information in the post to say that. You have not said what any of these devices are and if you are writing the software for them or not.From the fact that you are using McBSP i would say that one of those devices is a TI OMAP processor

author: rakeshm55
author_rank: Regular Contributor
timestamp: June 11, 2018, 05:18:55 am
content: Module B I have not decided. S/w for Module B not in my control. Module A and Module C under control. Module B s/w guidelines could be given.For Module A it will be either a Sitara or Keystone (A15 + DSP ) coreFor Module C it will be a 7 series FPGA with PCIe Hard IPLinux will be ported to Module A (A15) ARM core.

author: Berni
author_rank: Super Contributor
timestamp: June 11, 2018, 05:58:58 am
content: In that case you simply specify that inside module B that you want the PCIe bus going out of it to be memory mapped on the map of the PCIe bus coming in.That way you can have a specific address range on the bottom bus of module B where any write or read operation to it is simply forwarded to the top PCIe bus. That gets you communication one way and to get the other way you probably have to do polling unless you can wire some interrupt line back from C to A.

author: rakeshm55
author_rank: Regular Contributor
timestamp: June 11, 2018, 09:04:18 am
content: So does that allow for Module B to initiate data to Module C independent of Module A??Will the nature of Root Complex in Module B change to End point ?? Or will it remain as root complex.

author: Berni
author_rank: Super Contributor
timestamp: June 11, 2018, 10:11:37 am
content: This is the reason why having polling or a interrupt signal is useful. This way the processor can initiate communication in reverse by making read requests whenever module C wants to get data out.You can get a PCIe device to initiate a transfer by having it do a DMA access but this is more complicated and that device in between has to be smart enough to correctly route them trough.