EEVblog #897 - Radiation Effects On Space Electronics - Page 1
Forum section: electronics / general

author: EEVblog
author_rank: Unknown
timestamp: July 06, 2016, 12:56:05 am
content: Dave talks with Karsten Becker from PT Scientists about radiation in space and it's effect on electronics and the design challenges involved for space probes, satellites, and cubesats.The Van Allen belt and types of cosmic radiation.What are "radiation hardened" components?What are "Space Grade" components?

author: MK14
author_rank: Super Contributor
timestamp: July 06, 2016, 02:03:16 am
content: Thanks, I really enjoyed that video.I knew radiation and cosmic rays could adversely affect electronics while operating. But did not realize that it could actually damage/destroy them, as with living things.He is a very interesting person to interview/chat with.

author: EEVblog
author_rank: Unknown
timestamp: July 06, 2016, 02:27:25 am
content: Quote from: MK14 on July 06, 2016, 02:03:16 amYes, we chatted for hours about all sorts of stuff, I have a lot more material.

author: Brumby
author_rank: Unknown
timestamp: July 06, 2016, 03:18:57 am
content: Did you work out Tantalum? (@ 8:55)

author: MK14
author_rank: Super Contributor
timestamp: July 06, 2016, 11:02:51 am
content: Quote from: Brumby on July 06, 2016, 03:18:57 amI thought he was trying to say "Titanium" ?A bit of searching seems to confirm the possibility that it was Titanium to protect Electronics.QuoteSource:http://www.nasa.gov/mission_pages/juno/news/juno20100712.htmlEDIT:On the other hand, it could be Tantalum.http://pelagiaresearchlibrary.com/advances-in-applied-science/vol3-iss1/AASR-2012-3-1-446-451.pdf

author: Brumby
author_rank: Unknown
timestamp: July 06, 2016, 12:40:06 pm
content: I listened to the sounds being spoken and figured it out in a couple of seconds...What was said was 'Tan -tal- um'. We normally say it as 'Tanta - lum'I checked (Google is your friend) and found tantalum is also used in radiation shielding - which confirmed my original interpretation.

author: MK14
author_rank: Super Contributor
timestamp: July 06, 2016, 12:54:25 pm
content: Quote from: Brumby on July 06, 2016, 12:40:06 pmI agree Tantalum can be used in radiation shielding.I can believe he was trying to say Tantalum OR Titanium, I'm NOT sure which it was (from listening to it).Sometimes it sounds like "Tantalum", and at other times "Titanium", the human brain is funny when it becomes biased.EDITED: Corrected.

author: Brumby
author_rank: Unknown
timestamp: July 06, 2016, 01:12:56 pm
content: I'm pretty sure the last syllable was 'lum' - beginning with an 'L'.Dave should have a periodic table at hand, the you could get Karsten to point at the element.

author: MK14
author_rank: Super Contributor
timestamp: July 06, 2016, 01:20:54 pm
content: Quote from: Brumby on July 06, 2016, 01:12:56 pmThe first time he says it, it DOES sound like Tantalum, I agree.But then Dave seems to say "Titanium"Then he (Karsten) says something which also sounds more like Titanium (but said wrong).So maybe Dave's "Titanium", confused him or something and it was Tantalum.

author: Mike_H
author_rank: Newbie
timestamp: July 06, 2016, 02:56:00 pm
content: I am not a big poster, but that was a great video - very enjoyable.ThanksMike

author: nwvlab
author_rank: Regular Contributor
timestamp: July 06, 2016, 03:12:24 pm
content: Mh, I do not perfectly agree with the engineer.Even if the total ionizing dose (TID) effects should not depend on the feature size (gate length), one should take into account that as the gate length scales down, the gate dielectric thickness scales down too (therefore TID effects are at least technology-node dependent). And the TID effects on ultra-thin oxides are extremely different to those on thin or thick oxides. For instance, if the oxide thickness is below 3nm, charge trapping in the gate oxide (which causes threshold voltage variation) is suppressed, because trapped charges (mainly holes in SiO2. Electrons could be trapped in other dielectris) are quickly neutralized by tunneling, as they are (at most) only 1.5nm apart from the gate or the channel interface (with a such thin barrier, the quantum tunneling rate is extraordinarily high).Furthermore let's think about Flash memories. The smaller the floating gate, the smaller the dose you require to neutralize a critical amount of stored charge. As the feature size scales down, they could become more and more sensitive. Also radiation induced-leakage currents impacts on the data retention and they depend on the dielectric thickness.

author: jnissen
author_rank: Regular Contributor
timestamp: July 06, 2016, 03:23:00 pm
content: Space grade components are most assuredly designed from the start with energetic particle emission in mind. I have done a number of ASIC's that have flown on all sorts of high altitude aircraft and some spacecraft. There are many "tricks" involved with these designs and in most all cases you design an active region with good well ties and shapes that promote easy current flow paths back to the substrate. If a substrate less (SOI, SOS) design then you can effectively eliminate bipolar type structures (lateral devices are still present) so this significantly improves the performance out of the gate.In all cases good testing regimes, and yes lots of paperwork, is required to validate the intended performance. Rarely do you take off the shelf components and just "hope" they work well in an energetic environment!BTW - The comments above on feature size is not a prediction of performance is partially true. Normally as feature sizes shrink the gate oxide and critical dimensions all shrink so you expect to see thinner oxides and dielectrics. Clearly the author has some background in non-volatile memory storage in energetic environments. That is a very tricky design field indeed.

author: apis
author_rank: Super Contributor
timestamp: July 06, 2016, 07:54:47 pm
content: Very interestinglooking forward to the teardown!(yeah, he definitely said tantalum)

author: Howardlong
author_rank: Super Contributor
timestamp: July 06, 2016, 08:37:27 pm
content: Tantalum and aluminium sandwiches are commonly suggested after some experimental work was done a couple of decades ago.It also depends on which order they are applied as to how good the shielding capabilities are.Typically just the tops of the chips have the shielding applied, rather than the whole space frame to mitigate weight but what about the bottom? The board can be designed so chips are placed back to back top and bottom.What this doesn't deal with are secondary radiation effects, although it does mitigate them to some degree.Regarding space radiation effects, the point is to accept that it's notif, it'swhenit happens.

author: MK14
author_rank: Super Contributor
timestamp: July 06, 2016, 09:52:09 pm
content: Quote from: apis on July 06, 2016, 07:54:47 pmQuote from: Howardlong on July 06, 2016, 08:37:27 pmThanks, everyone and sorry for any confusion on my part.Ok, Tantalum it is.Somehow I thought Tantalum was a weak/brittle insulator material (like Mica). Probably because of Tantalum electrolytic capacitors. Many capacitors seem to be named after the main insulator, used in their construction.I suppose standard electrolytic's, can be called aluminium capacitors, so I should have realized that electrolytic's are named after the CONDUCTOR, rather than the insulator, material. (Apparently). A bit weird (the naming scheme).EDIT: But I suppose it probably is the INSULATOR as well, as it is probably chemically transformed to be an insulator as well, I guess.

author: Brumby
author_rank: Unknown
timestamp: July 06, 2016, 11:14:37 pm
content: Quote from: nwvlab on July 06, 2016, 03:12:24 pmI'm inclined to agree with the engineer who is actually building stuff for space...Also, as you scale down, I concede it is quite possible that gates, etc. may require a smaller dose to be affected .... but the critical zones will be a much smaller target for the radiation to strike.

author: EEVblog
author_rank: Unknown
timestamp: July 07, 2016, 03:46:36 am
content: Quote from: MK14 on July 06, 2016, 01:20:54 pmI thought he said Titanium

author: EEVblog
author_rank: Unknown
timestamp: July 07, 2016, 03:48:08 am
content: Quote from: Mike_H on July 06, 2016, 02:56:00 pmThanks glad you liked it.

author: Howardlong
author_rank: Super Contributor
timestamp: July 07, 2016, 06:09:13 am
content: Another area of great interest is tin whiskers. There have been spacecraft losses from this.There was an EEVBlog video some time ago about this but I've never been able to find it.We use full fat solder, but for COTS parts they are still unleaded. You can treat the exposed pins, it's not something I've every done though.

author: EEVblog
author_rank: Unknown
timestamp: July 07, 2016, 06:47:41 am
content: Quote from: Howardlong on July 07, 2016, 06:09:13 amForgot to ask that!But for an 11 day mission, shouldn't be a problem.QuoteYes, I recorded an entire 3 hour lecture on tin whiskers. I got permission to show some footage from it provided "I didn't show the whole thing"Turns out they spat the dummy at my 20-30min video edit or whatever it was, claiming I was costing them hundreds of dollars forevery view!I keys getting panic emails every 10 minutes as they watched the view counter go up until I took it down

author: nwvlab
author_rank: Regular Contributor
timestamp: July 07, 2016, 09:02:10 am
content: Quote from: Brumby on July 06, 2016, 11:14:37 pmI did for some years radiation testing on non-volatile memories. Beside there is a huge amount work in the literature on radiation effects on devices (see for instance IEEE Transaction on Nuclear Science).Quote from: Brumby on July 06, 2016, 11:14:37 pmActually, I didn't say: "IN GENERAL, the smaller the size, the larger the TID effects". On the contrary, I showed two opposite examples for which you can't say that there is no TID effects depedence on the technology node.In particular:1) Some degradation mechanisms (in this case, I was referring to radiation induced trapped charge in the oxide, which causes a threshold voltage variation) do actually depend on the gate oxide thickness (which, in turn, depends on the technology node). In particular, for ultra-thin gate oxides, the (semi-permanent) threshold voltage variation is a negligible mechanism, as there is no enough energy barrier width to prevent a quick charge neutralization by quantum tunneling. Therfore. in this example, the smaller the technology node, the smaller the permanent threshold voltage variations effects.2) However, for non-volatile memories, things might go in the opposite direction. For instance radiation induced leakage currents permanently degrade the retention capability. It is true that, if you have a thinner oxide, radiation has a smaller probability of creating a defect inside it (merely because you have a smaller volume in which radiation can interact). However, once a defect is created, the leakage current due to trap-assisted tunneling exponentially (and not only linearly) depends on the oxide thickness and, of course, on the trap position. Keep also in mind that the number of stored electrons scales with the technology node (for technology node around 90nm you have about 1000 electrons/bit. Therefore with smaller technology nodes you have less charge and higher chance of critically high leakage currents). The radiation-induced prompt charge loss also depends on many factors, which are technology node-dependent.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 07, 2016, 09:16:25 am
content: Tantalum metal is a rather heavy hard material, but still a little ductile. So you can bend the foil, but not to often. So it's more similar to steel. Way more expensive, but at least you can buy the foil as a standard product. The high atomic weight (not much lower than lead or gold) helps for shielding, so titanium would not make much sense except for mechanical strength at low weight.

author: apis
author_rank: Super Contributor
timestamp: July 07, 2016, 09:44:20 pm
content: Did Karsten say there was mostly protons in the Van Allen belt? If so couldn't you shield the craft by polarizing the hull? Or with magnets...

author: Howardlong
author_rank: Super Contributor
timestamp: July 07, 2016, 10:16:09 pm
content: The inner van Allen belt is the proton belt. The amount of radiation it'll be exposed to from the van Allen belts in the few orbits before it heads to the moon will be minimal.Magnets are used on spacecraft, particularly Earth satellites: it's a used as free means of attitude adjustment.The amount and type of radiation a spacecraft is exposed to depends on a number of factors, including the orbital parameters and the time in the solar cycle that the spacecraft is operating.

author: retrolefty
author_rank: Super Contributor
timestamp: July 08, 2016, 01:58:59 am
content: Quote from: Kleinstein on July 07, 2016, 09:16:25 amTantalum or titanium I think more info/facts would be useful on this. I just read this on Huffington post, but of course they could get it wrong also:Quotehttp://www.huffingtonpost.com/entry/juno-jupiter-mission-nasa_us_577d4954e4b0a629c1ab94d2?yptr=yahoo

author: Howardlong
author_rank: Super Contributor
timestamp: July 08, 2016, 05:46:18 pm
content: In the context of what was being discussed, I am certain it is tantalum as, together with aluminium, made as a sandwich this mitigates against radiation by both absorbing and dispersing.Sometimes there are other elemental metals in the laminate, but they are layered from high atomic number to low atomic number, and sometimes known as graded Z. I don't pretend to understand how it works, but rightly or wrongly I've always likened it to light entering a differing refractive indices and dispersing as a result. The sandwich itself is placed directly on the chip package.As I mentioned before, this has been happening for years, I think I was first made aware of the practice about 15 years ago at a conference.

author: R005T3r
author_rank: Frequent Contributor
timestamp: July 08, 2016, 06:04:54 pm
content: I knew that Erbium was used to adsorb neutrons, but tantalum as a shielding?

author: Howardlong
author_rank: Super Contributor
timestamp: July 08, 2016, 06:14:07 pm
content: As I mentioned, look up "Graded-Z shielding".

author: BobC
author_rank: Unknown
timestamp: July 08, 2016, 07:33:29 pm
content: Most radiation test regimens start with lifetime dose estimation, generally done by storing the chip next to a radioactive source for a while. You will want to test with the chip running with a load equivalent to that expected for the mission.The real fun comes when testing SEEs (Single Event Effects). For that, you need to actually deposit the equivalent energy present in the regions you care about.There are lots of beamlines available that will accelerate electrons and (more rarely) protons to relativistic speeds, but these machines can't get anywhere close to cosmic ray energies. When you need massive energy and you can't add more speed, then you need to hurl larger atoms (well, ions).The problem with large ions is they lack the penetration depth of lighter particles: Ions slow down almost instantly. The good news is that chips are thin, and hitting them straight on provides excellent test conditions. Except the chip's epoxy package is in the way: This means the chips have to be "de-lidded" to expose the silicon (often using friendly stuff like "fuming nitric acid") before putting it in the beamline.Beamlines that toss heavy ions are tough to find, and even harder to get time on. The Brookhaven National Laboratory (BNL) on Long Island has the Tandem Van de Graff facility that uses submarine-size Van de Graff generators to accelerate heavy ions to relativistic speeds using only electric fields (most other accelerators rely more on magnetic fields).This testing must be done in a vacuum, so most of your time is spent doing setup and tear-down, with less time actually bombarding the part. So it is vital to ensure that no time in the beam is wasted: You don't want your part to have a fatal failure early on, so you start with lighter (but still heavy) ions at lower energies and ramp up from there. But you need to ramp quickly to get into the desired energy realms, so very careful experiment design is critical.Since we are slamming the chip to generate SEEs, the experimental setup must be extremely good at recovering from them, preferably far better than the recovery methods planned for the actual mission. And it must recover quickly, to avoid wasting beam time.So what you do is first prepare multiple systems to go in the beamline vacuum chamber, preferably at least two at a time. I did two at a time, configured to monitor each other. Both systems initially boot into "test" mode. The first one to get hit will cycle its power, which is seen by the other system and causes it to switch to "monitoring" mode.The chamber contains a stage that permits X-Y translation and at least one axis of tilt. So once the chamber is closed, pumped down, and exposed to the beamline, we start with the stage oriented parallel to the beam until the beamline operator tells us that our selected ion is being streamed at the specified energy and flux (particle rate), at which time we tilt the stage to be normal to the beam. Then we adjust X-Y until we start seeing hits. (There is a beamline laser spotter, but it can be difficult to see through the vacuum chamber view ports.)The test-mode software has to know two things: 1) How to detect that a hit has occurred, and 2) how to order a power cycle. Detection is done by continuously scanning flash for changes (a simple checksum suffices), and continuously writing patterns to RAM and checking them.To do this as simply and as quickly as possible and still have the software be reliable, it is best to try to get the program to run using only the instruction cache and the available registers. And that typically means writing in assembler, and still taking every possible algorithmic shortcut.Once you get hit, the power cycle must be fast, and the chip must be discharged as quickly as possible. It's not enough to simply turn off the power supply: It is critical that VCC is pulled to ground with a very low impedance. The simplest approach is to have a load resistor in parallel with the system, but quite often even that isn't fast enough. Even a SPDT relay is often too slow. The problem isn't the power supply: It's getting the residual electrical energy out of the chip.But putting an FET across the supply output will be plenty fast. A nice, big, fat FFT (BFFET) with extremely low RdsOn and a tolerance for high current spikes. But even with the BFFET, it is important to guard against ground-bounce, which can reverse-bias your chip and cause damage unrelated to the SEEs (went to the School of Hard Knocks to learn this one).It is a thing of beauty when it all comes together in the vacuum chamber. In my case, I was piggybacking on another beamline customer, and could only use the beamline when they weren't. For some reason they felt sleep was important (wimps), so I had lots of time in the wee hours for my runs, in addition to helping them with their runs.But the best fun is when you get back and start analyzing the data. Each SEE is characterized and timestamped, and logged with the beamline configuration. That data is fed to a program (well, a spreadsheet in our case) to determine how well the chip can be expected to perform in our expected space environment(s).I forgot to mention that we were testing COTS parts, literally purchased from the stock of a commercial electronics parts distributor. How did we select our processor? A foreign silicon manufacturer had been making some amazingly good rad-hard parts, but none of those parts were what we needed. But they also made a couple lines of microcontrollers that would work fine for us. So we learned what production lines were used to make the rad-hard parts, then found out which of their processors were made on those lines, and finally selected the one from that list that worked best for us.We also learned that all rad-hard chips also have excellent thermal performance specifications (they need to), so the only thing special about the processor we purchased was that we got the "automotive" temperature range.When all the data was analyzed, we calculated the expected processor lifetime and SEE rate were both WELL within our needs. Years of useful life, when we needed only months. But we still went with redundant processors, and still bought a tiny number of rad-hard gates for the voting logic.Just in case we made a mistake in our math.

author: Howardlong
author_rank: Super Contributor
timestamp: July 08, 2016, 08:55:27 pm
content: There are radioactive sources and radioactive sources. One problem of trying to characterise behaviour is that the source(s) need to be representative of the environment the unit will end up in. For example, using a Cobalt 60 source is all well and good, but how well does its radiation makeup represent the target environment?This is one reason there are some Gumstix going up onto the ISS to see how they manage in a real environment, and I assume how they compare to terrestrial models.

author: jeffg
author_rank: Newbie
timestamp: July 13, 2016, 04:52:02 am
content: Well, he gets a lot of it right. But some things are confused.Where you are, does matter. LEO is a walk in the park. MEO and HEO are problematic over longer term. Planetary space is highly problematic even for short periods (the primary reason we haven't had a manned mission to Mars is the chances of instant death from a solar flare or certain cancer due to radiation is in double-digit probability).Total Dose is ionizing radiation including X-rays, Gamma Rays, protons and ions (which hit things and produce Bremstralung X-rays and Gamma Rays - which is why these are the common theme for damage). The energy is primarily deposited into materials by "photon interaction at ionizing energy levels". The materials define how that happens (so there's a Rad(Si) absorption characteristic you integrate over).Total dose are not primarily due to interfering with doping but interacting with oxides or dielectrics contacting the semiconductor. Radiation can induce high energy "charge" injection into oxides by creating defects which trap charge. The traps get charged and then cause channels to turn on (in MOS) or form parasitic channels where they never existed or were intended (anything else). So there are unintended current paths and leakage currents created that result in degradation of performance not intended in the chip circuits. Enough damage/leakage and analog circuits debias and digital circuit shift their logic thresholds. The net result - circuits stop working.Single Event is primarily highly ionized heavy ions (e.g. Fe+8, Au+9, etc.) that are traveling at relativistic speeds. Also includes are x-ray and gamma ray pulses from the Sun and supernova. These carry and deposit INSANE amounts of energy into a small space. In semiconductors they can produce >1000x more hole-electron pairs than normal exist during normal device operation. Obviously this disrupts "normal" device operation pretty seriously.Shielding for total dose actually increases total dose when you have cosmic ray single-event. There is a process called "spallation" that occurs when the ion hits an atom in your shield (higher Z in the shield makes the spallation worse). Spallation products include protons and ions and they get generated 10:1 to 1000:1 from a single cosmic ray ion, and they "manifest" on the other side of the shielding.This is part of why shielding is limited in effectiveness. Strictly if it weren't for single-event, more is better but doubling thickness only halves the shielding: it's exponentially diminishing returns and thus it never goes to zero. Ironically you have shielded for external dose but increased the interactions for cosmic rays to create increased internal total dose created inside and after the shielding! Nature is devious! Spallation in the semiconductor can interact with doping but generally the dose rate is too small to affect end-of-life failure.He's talking about Ta (tantalum) field shielding. It has higher Z (atomic weight) than aluminum but a density similar to Al so it's attractive for space weight budgets. Spallation and weight limits shielding practicality.It's NOT paperwork or testing for radiation hardening - this is wrong for high hardness. Usually ICs need to be designed specifically for maximum hardening (anything over 1 MRad). From transistor design up to layout design rules are different. Radiation tolerant and low dose hardened (e.g. 10 KRad - 500 KRad), can be "binned out" with testing.But there are fundamental problems with ever using binning for reliability (which radiation effects is a subset of) - it's generally a dangerous strategy: you can't "test to reliability" - you can only "design to reliability". Testing is part of assuring the design will be reliably but the cause-and-effect only goes in one direction. This is generally true of all reliability, not just radiation effects. Military electronic has a long history of Epic Fail when people tried to reverse the arrow of causation in this regard.Ironically feature size often improves single-event hardness because the target cross-section volume is smaller for each device BUT you get more transistors which can be upset. So you still need error correction or reset/watch-dogging. Single event often triggers a parasitic SCR/Diac that exists in a bulk CMOS substrate/well structure, which results in latch-up. SOI, FinFETs, etc. can address this also but there are usually major cost penalties that often make bulk CMOS a better choice (with the right design).DRAM is super sensitive because you are storing (tiny) charge but it's charge that radiation is spuriously introducing at random into the IC circuitry. This is why you go with SRAM if you want super hardened memory.There's also neutron damage but they only come from nuclear weapons.Only neutron and some spallation product radiation cause a great deal of doping disruption.A good reference intro is Messenger & Ashhttps://books.google.com/books/about/The_effects_of_radiation_on_electronic_s.html?id=aQFTAAAAMAAJAlso IEEE NSREC papers over the last 50 years. The conference is fun also.http://www.nsrec.comWhen you design the system, you start with a mission lifetime, you use software like what he describes to estimate the accumulated radiation dose of various types for various orbital paths and injections, and then that has to balance with the hardness you achieve with part specification and shielding. You typical start with a "10 year life" and then you consider anything beyond that "a gift" but anything less is within your radiation dose budget.I used to do radiation effects testing for DOD satellites/systems. The Co-60 source we used was 2000 Rads/second btw. Being involved in this actually got me started with testing with stuff like SMUs and LCR meters and deeper into device physics. You have to work at the device level to understand radiation effects and design for hardness.

author: Howardlong
author_rank: Super Contributor
timestamp: July 13, 2016, 05:27:01 am
content: Awesome second post jeffg!

author: nwvlab
author_rank: Regular Contributor
timestamp: July 20, 2016, 07:35:27 pm
content: Quote from: jeffg on July 13, 2016, 04:52:02 amWith ultra-thin gate oxides (<5nm), most of the charge trapping occur in thick oxides regions (e.g. the STI regions). Besides that, we found also that radiation damages the Si/SiO2 interface (creating fast and border traps). These will increase the subthreshold swing, which, in turn, can either increase the effective threshold voltage or increase the off-state leakage current (or both).Also, the dose rate is a concern for some devices, and its effect might be counter-intuitive. Surprisingly, initially it was found that some integrated BJTs were "very" robust against TID. Then, people started to analyse the effects of lower dose rates. They discovered the so called enhanced low dose rate sensitivity (ELDRS), which literally killed them.

author: hkBattousai
author_rank: Regular Contributor
timestamp: December 16, 2017, 03:10:44 pm
content: Can you give the address of the website about that space simulation software mentioned in the video?

author: Howardlong
author_rank: Super Contributor
timestamp: December 17, 2017, 12:32:22 pm
content: Quote from: hkBattousai on December 16, 2017, 03:10:44 pmTry looking up SPENVIS and CREME96. I am not current on this, the last time I used these models was some years ago through a web interface. Also note that there are two primary effects to note, long term total ionising dose (TID), and short term single event effects (SEE). There are also space weather effects to consider which can markedly change according to relative time within the sunspot cycle: I think SPENVIS deals with this, not sure about CREME96.

author: Neomys Sapiens
author_rank: Super Contributor
timestamp: December 17, 2017, 03:37:19 pm
content: Quote from: MK14 on July 06, 2016, 11:02:51 amInteresting authorship on this paper!