Analog adjusting feedback of sync DC/DC - Page 1
Forum section: electronics / projects

author: Katanara
author_rank: Contributor
timestamp: January 02, 2023, 01:44:26 pm
content: Hello! I'm going to apply ADP2384 in a combined scheme DC/DC + LDO. It is required to give a minimum supply voltage from dc/dc for adequate efficiency. LT1084 is used as an LDO.I referred to this topic. And I took out the scheme from there separately.https://www.eevblog.com/forum/projects/pre-regulator-inspired-by-linear-an30-fig-46/You can clearly see how the fast PNP transistor controls the feedback current of DC/DC. I was assembling this earlier and this worked nice. But I need more modern sync step-down like IR38063 or ADP2384.For a while I act with IR38063 via I2C, but now I have only ADP2384. There is a need to get a fully analog adjustment of its feedback. I tried to do this with IR38063 and 2N3906, but output voltage was periodicaly leaping on load. Why? Could this method work with SYNC dc/dc?Now I am designing a new board (on ADP2384) with several supposing options of this adjustment. I also want to try the DAC as voltage regulator in the feedback. The second picture shows how exactly I intend to do it. But the pure analog method is more interesting.I would like to expand the horizons of possible solutions. Surely there are many of them. Vactrol? Transistor cell? Or one PNP should to work?Thanks for your attention!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 02, 2023, 09:35:36 pm
content: If the LDO output is fixed, why not fix the buck too? Or did you have something else in mind than the schematic?In general, the problem with this kind of approach is getting higher loop gain and phase shift, turning the loop unstable. The BJT may also be nonlinear, making things chaotic in addition to unstable. (The high emitter degeneration and low ratio between Rc and Re does reduce most of that.)Is the postreg needed at all? Almost always the SMPS can simply be better filtered; and the LDO fixes nothing about common mode noise issues.Tim

author: Katanara
author_rank: Contributor
timestamp: January 02, 2023, 09:49:50 pm
content: Yeah, sorry. I should've started with this. My real scheme is different. LDO is not fixed. It's adjusting by DAC. The main point is to control the current on the load.I've attached below LDO's part of scheme (without transistor, because DC/DC part is dropped here).If we could talk ONLY about this scheme, then an increase in efficiency is required here, so there is a question about dc/dc feedback .

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 03, 2023, 12:57:18 am
content: Note that the reg simply acts as a voltage follower. When it's self biased, the 1.25V reference is dropped across the top divider resistor, the same current (minus a small ADJ pin current, ~120uA max) flows through the bottom resistor, and hence an adjustable output voltage is obtained.But with an op-amp driving it, it can simply tie directly to ADJ. Maybe with a diode or two to clamp it from being overdriven (relative to the output) on step change?The SMPS can also be driven open loop the same way, probably at expense of one more op-amp (so use a dual?), and give or take what happens in overcurrent conditions (preferably the SMPS browns out first, so the reg doesn't dissipate much?).Incidentally, LT108x is not an "L"DO. I guess any linear regulator is being called that nowadays, but the original distinction was dropout < 1.2V or so: compare LM317 (the OG, Darlington output stage, ~2V dropout) to LM1117 (Sziklai output stage, ~1.1V) to, well, most any other  LDO (common-emitter PNP or common-source PMOS output, arbitrarily low dropout). The downside is the open-collector/drain output is particularly sensitive to load impedance with respect to stability, so they've been notoriously hard to design and use. Modern devices are generally well behaved, and stable with low-ESR ceramic bypass, but it's still a good idea to check (namely, for GND pin current in dropout, and ESR + C locus of stability). Several archaic parts are still available, that one should be aware (or weary) of when making a selection.Which is also relevant here: wasting ~1.5V on a postreg is a huge cost compared to a modern LDO, and one of those is likely still costly compared to just filtering the thing properly in the first place.And in the cases where you really need exceptional filtering, just any regulator will not do; there are specialty LDOs with high cutoff frequencies, claiming ca. 80dB attenuation even at 1MHz. Or a capacitor multiplier or something like that, particularly when the DC output isn't so critical but AC is.Tim

author: Katanara
author_rank: Contributor
timestamp: January 03, 2023, 01:07:34 pm
content: Quote from: T3sl4co1l on January 03, 2023, 12:57:18 amCould you please suggest an alternative of 1084? The maximal output current is desirable in the range of 4-5A. Usually "Very"LDO or "Ultra"LDO are applicable in schemes of low input and output voltages (1.5-5V), but I need a guaranteed range of 3-12V on output load.LT1084 is also has several important properties. The line regulation is 0.015% and the load regulation is 0.1%. So accuracy is importrant too. If we take some modern, then it shouldn't be coarser than these characteristics.I would really appreciate it!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 03, 2023, 08:08:14 pm
content: What output noise do you require?Tim

author: Katanara
author_rank: Contributor
timestamp: January 03, 2023, 08:35:33 pm
content: Better less as posible.In fact, I chose the fast step-down switch as the supply to reg because the load has sensitive to low frequencies. But LDO (desirable) should have good noise and PSRR characteristics.

author: Someone
author_rank: Super Contributor
timestamp: January 03, 2023, 09:38:07 pm
content: Quote from: T3sl4co1l on January 03, 2023, 08:08:14 pmAmong the other constraints and desires that would inform any power design.But as you are wont to do a passive (and slightly lossy) filter is probably more than enough to meet most noise requirements. 0.1% noise is fairly routine on the output of a buck, 0.01% not impossible,beforeadding additional filtering.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 04, 2023, 12:19:15 am
content: Like, we can discuss "least possible" -- impressively low margins arepossible. But we quickly get into questions of practicality and budget. If you want it to be adjustable, does that mean we can't use batteries anymore, or can we just use a tapped battery still? (Batteries, at least certain types, are generally quite calm sources.) Can it be done with superconductors in a cryostat (regulate it with a Josephson junction if you like, for extremely precise control)? That gets into the nV range pretty easily. But "ease" is relative, and you'll be paying a good couple kilodollars to even begin to build gear like that.With respect to bandwidth, I'm not so sure about; these methods tend to be DC or at best LF applications (like metrology). Even at such low temperatures, and even for quite low source impedances, it doesn't take much bandwidth to exceed some ~nV of noise, so it may not be a very important matter in that case, going beyond LF that is.Conversely, if the bandwidth is some ~kHz still, but at a center frequency of MHz or GHz, that's quite easy to measure, achieving 10s or 100s of nV with an RF amp near room temperature.But if you can't even measure that, nor have anything that would be powered by it that could reasonablyinfersuch levels of noise (e.g. a radio that would read ~uV or ~mV of supply noise as interference) .... how could it matter? When would you even know the noise is "low enough"?For many applications, "low enough" is 100s of mV. Seemingly quite nasty supplies can be perfectly effective!"As low as possible", is a feat of cutting-edge engineering, or fundamental chemistry or physics; "lowenough", now that's an engineering proposition!For reference, I've built a SW receiver with a SMPS running it; a shield box and a few extra LCs were more than adequate filtering to remove it from the receiver's noise floor. Numerous articles of test equipment use SMPS for main power and point-of-load (PoL) DC-DC for running FPGAs, ASICs, MCUs, ADCs, preamps, converters, etc. Not to mention all the potential signal noise in such systems: there's digital logic of 100s mV or more, often in the low GHz, going on alongside the sensitive analog stuff. But by careful design, the two are well separated, and near-theoretical noise floors can be had.Tim