Do the 480MHz STM chips present bigger EMC issues over the 168/180MHz ones? - Page 1
Forum section: electronics / general

author: peter-h
author_rank: Super Contributor
timestamp: October 12, 2023, 03:23:20 pm
content: For example the H7 compared to the 32F4.Ideally not because the fast clock is on-chip only and the chip should not radiate significantly.But there will be 480MHz modulation on Icc.

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 12, 2023, 03:38:02 pm
content: I don't think so? Placing decoupling caps very close to STM32 VDD plus a 100MHZ choke should filter it all.

author: peter-h
author_rank: Super Contributor
timestamp: October 12, 2023, 04:01:17 pm
content: The choke is not shown on any STM dev board circuits I've seen... Interesting!That also implies that instead of connecting all VCC and GND pins directly to the two planes using very short tracks, and having ceramics spread around under the CPU, you join all the VCC pins together, join all the GND pins together, put caps across those two wires, and have a choke from the VCC wire to the VCC plane. I'd say that is pretty unusual.

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 12, 2023, 04:20:08 pm
content: Not really? It's only few mA, the choke will prevent the HF from reaching large VDD traces. 5mm trace will hardly radiate anything.

author: temperance
author_rank: Super Contributor
timestamp: October 12, 2023, 04:28:54 pm
content: A lot of people spend a lot of time placing decoupling caps as close to the chip as possible, counting every micro meter. Although not a bad idea, a few mm more or less is not that important.Why: compare a 100pin TQFP with a 144 pin TQFP for example. You can't place the decoupling closer to the chip than the length of the bond wires.Don't use ferrite beads when not required. They resonate with high Q MLCC capacitors.

author: peter-h
author_rank: Super Contributor
timestamp: October 13, 2023, 06:54:08 am
content: I would be interested in hearing from anyone who actually got an H7 based product through CE xxxxx.

author: iMo
author_rank: Super Contributor
timestamp: October 13, 2023, 08:39:50 am
content: Look at the schematics (the "service manuals" are easy do download for all TRXses) of modern HAM radio transceivers, for example.Those are packed with FPGAs and up to ~400MHz MCUs today, they have to be low EMI because they are sensitive Receivers per-se, and they have to be EMC certified..Ie. my ~20y old small sized IC-7000 has got 2x 400MHzBlueBlackfin DSPs/MCUs inside, afaik.

author: AVI-crak
author_rank: Regular Contributor
timestamp: October 13, 2023, 08:43:17 am
content: The 480MHz frequency is not a problem. This is all inside the chip, at low supply voltage, with large internal structural capacitance and large external filtering capacitance. There is zero external interference.Peripheral contacts, on the other hand, are pain and suffering.STM has a staff of stoned specialists who assign peripheral pins in a completely random way. For example, QSPI - high frequencies, and evenly scattered pins. The clock loops are of the highest class, the board can be heard on an SDR receiver hundreds of meters away.

author: hans
author_rank: Super Contributor
timestamp: October 13, 2023, 09:20:09 am
content: The SRF of a 100nF cap is only a few tens of MHz (20-40MHz). After that its inductive (hundreds of pF).. just as the bondwire (up to 1nH) and the leadframe (which increases dramatically going from a 64LQFP 216MHz F7 to a 176LQFP 550MHz H7). So I suspect most of the HF decoupling is performed on-chip.Unlikely FPGAs, I've not seen any recommendations for power delivery networks to STM32s that use lower value caps than 100nF.Yeah, the I/O on these STM32H7s are atrocious. I've wired up USB HS, 2x OCTOSPI and SDMMC on a H725 in 176LQFP, and it was all over the place literally. IIRC the usb HS ULPI bus was all on 1 side, except for 2 LSB or MSB bits, which were on the other side of the package.Likewise, the OCTOSPI bus is scattered all around. It may have 4 nibble ports that you can multiplex around to set up the 2 OCTOSPI buses, .. it was still not easy to route.Luckily 6 layer boards are not that much more expensive than 4 layers these days.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 13, 2023, 10:24:15 am
content: Quote from: DavidAlfa on October 12, 2023, 03:38:02 pmFor example, how would you propose to deal with emissions that are radiated along GPIO pins?Consider the equivalent circuit:(Core switching at 480MHz + harmonics) --- on-chip capacitance --- residual noise through VDD and GND pinsjointly--- board VDD/GND plane.GPIOs connect to internal VDD/GND somewhere on the "on-chip capacitance" node. The package pins, wire bonds, etc. introduce some impedance between this reference plane and the PCB reference plane. There will be some common mode appearing on every pin, even if (especially if!) they are assigned static VDD/GND (or Hi-Z, through output stage capacitance).There is also some spreading resistance on die (probably pretty low, they use either multiple metal layers, or solid planes at least, to keep resistance and inductance low, and capacitance high), so we might further expect some variation between GPIOs. That is, if you measure the noise between a given pair of GPIOs both set low (or high, or even set opposite for that matter), how much will depend on whether they're in the same IO bank, or not, or on entirely opposite sides of the chip.The exact pin to board impedance will matter some, too, of course. Since that contributes to the gradient voltage across the die.In any case:the AC voltage drop on the supply and ground pins provides a route for common-mode emissions through all other pins of the chip.Now, VDDCORE won't be VDD pins directly. It is on slower, simpler chips, but, well, being slower they also have less harmonic emission for example. These, use an onboard 1.2V or whatever regulator (sometimes a bulk capacitor is required on an exposed pin; I don't recall offhand which STM32s do, if any), so there's additional opportunity for bypassing (i.e. internal VCOREandinternal VDD have onboard capacitance available to them). Moreover, the 480MHz signals are routed within the core area, and only fractions thereof are routed to the actual IO banks, and GPIO pins in turn. Generally the core is, well, at the core (center), and IOs are dotted around the edge. The high voltage IO domain doesn't switch as fast (fractional to several ns), so there will be less harmonic content, though the signal level of course is higher too.And further details still, which will both provide further opportunity for emission, and further reduction in level; the full picture is the sum of all contributions. I'm only roughly assuming a few of them in the above here. But this is all just to say -- it's not something you can sprinkle ferrite beads over and say "done".Or, to put it another and much simpler way: what's so goddamned special about VDD, it's CMOS, it's the same upside-down isn't it? Anything we should filter VDD to, we should equally well filter GND to. Why not?Well, we again get a hint from VCORE being a thing; there must be level translators inbetween supply domains, and they've presumably defined a common ground (substrate), which therefore makes that GND more special than one VDD or the other. Maybe not to the external circuit (PCB) if core is entirely internal (all we see externally is the overall chip reference plane, whatever that is -- presumably somewhere intermediate between GND and VDD). Or, any ICs with defined input thresholds, independent of supply (not sure about logic families, but many interface ICs have e.g. a TTL/LVCMOS input threshold for any operating VCC/VDD), they might be using a common-source NMOS to define that threshold, in which case noise margin would be worsened with GND filtering, i.e., GND is a particularly privileged node in that case.So we probably don't want to filter ground, or at least very much, and in general. Perhaps there are special cases where we would. But we still update our perspective based on such thought experiments. We might figure that, if we need low jitter for example, we should probably just try not to do very much else with a given IC (anything that would draw interfering currents through its supply/GND pins and thus contribute to time error in logic thresholds); or for especially low radiation, we probably want to add filtering to any output pins, maybe inputs too.Which is fairly trivial as advice goes, as you don't really want naked GPIOs touching connectors, but some RFI filtering and ESD protection usually, and that confers improvement in both immunity and emission.But if we're talking 480MHz and harmonics, there's not much we can do about that at board level, about the chip itself -- given that it's a significant fraction of a wavelength across. For that, we are at the mercy of whatever the emission limit is, and how well attenuated those signals are between CPU core and pins.Which, observationally, no one is having a tremendous problem with this, so it seems we can expect they've done a reasonable job on-chip. But keep in mind what that means:commercial levelsare probably fine. Do pay attention if a project has exceptional limits, say an extra 20dB stricter or worse. Shielding will most likely be necessary in that case; perhaps as simple as a ferrite plate over the chip, perhaps a metal can, perhaps a metal enclosure altogether.Which also means we can relax our circuit design, at least a bit, at least with respect to this particular concern (fast internal clocks). Sprinkling ferrite beads indiscriminately is as likely to make things worse as better; but just following a normal orderly, plane-based design process is likely to result in good success, and at least a fine starting point for further reduction if necessary (like, having a reference plane to attach shields to).Tim

author: peter-h
author_rank: Super Contributor
timestamp: October 13, 2023, 10:54:19 am
content: Very interesting and useful stuff - thank you all.I've been doing "design for EMC" for about 40 years. All kinds of hacks get used. Often you get just one spike which is above the limit and then often putting a few-pF cap on one PCB track pushes that down just far enough.The famous Clive Sinclair used to get some of his stuff through EMC by sticking a piece of paper (with metal foil on the other side) on the back of the PCB.In a previous life I used to spray plastic cases with zinc on the inside. That was very effective but not cheap.And then there is the clock didther feature (this is a F437)which seems to produce a dramatic improvement, although I wonder if the 2% (maximum possible) frequency deviation messes up ETH or USB. The appnotehttps://www.st.com/resource/en/application_note/an4850-stm32-mcus-spreadspectrum-clock-generation-principles-properties-and-implementation-stmicroelectronics.pdftalks about messing up ADC DAC and timers.None of this is 480MHz-specific of course.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: October 13, 2023, 12:48:12 pm
content: I think not mentioned yet (TLDR) The core of these chips runs on a very low voltage (around 1V) and they have on chip voltage regulators, which further reduces the chance of 480MHz EMI getting out though the power pins. Peripherals are on peripheral buses, which typically run at lower frequencies, and pins have adjustable drive strength. Compared to that, the clock frequency itself is of minor concern. It is even generated on chip by PLL's.

author: peter-h
author_rank: Super Contributor
timestamp: October 15, 2023, 05:34:34 am
content: I suspect the main EMC issue with these ETH+USB chips is not the CPU but the ETH PHY related stuff which involves a 50MHz clock coming out, and if the 480MHz chips have a faster slew rate on that you may have a problem. I always route the PHY (LAN8742) really close to the CPU.I found this with Xilinx FPGAs many years ago. Later versions of thesamedevice ran much faster.Also a lot of designs broke, unless you did it right and used a common clock net, but that's another story

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 15, 2023, 07:44:37 pm
content: Yes, the internal clocking of a chip is rarely going to be an issue, but the slew rate of external signals, certainly.Note that you can adjust the slew rate of GPIOs on many MCUs (and FPGAs) - STM calls that the "speed" of the GPIO. In general, do not select the highest speed (highest slew rate) for GPIOs unless this is actually *needed*.

author: temperance
author_rank: Super Contributor
timestamp: October 17, 2023, 11:24:20 pm
content: QuoteThat's not a decoupling problem but a loop area / edge rate problem.Those "new" micro's switch extremely fast and even the shortest connection will show some ringing. Therefore high speed signals must be damped by means of some series resistors located at the source.QuoteThe difference between high and low speed is actually the wrong term for what you really get. The output stages in low speed is one buffer. The same output in high speed mode is 2 or more buffers in parallel. As such the speed doesn't change that much between low and high speed settings when the load has a low stray capacitance. (or just any modern IC) Series resistors do a much better job at controlling the edges.QuoteThat's why I'm a suspicious about the EMC performance of some STM32G devices with only one GND pin. Maybe they used multiple bond wires in parallel. I don't have any PCB with those. But if I get a dev board it will be the first thing to check.

author: uer166
author_rank: Super Contributor
timestamp: October 18, 2023, 12:17:51 am
content: In my experience the STM32 "speed" setting controls the edge just fine (regardless of how it's implemented internally). I've seen over 20dB difference in a radiated scan when pins were set to very fast vs slow. No series resistors. I mean think about it: with a CMOS output, having 1 buffer vs a bunch in parallel is exactly equivalent to adding a series resistor, since the output impedance increases.

author: temperance
author_rank: Super Contributor
timestamp: October 18, 2023, 01:14:25 am
content: QuoteI understand that. But even at low lowest speeds the output drive capability can be too high for a high speed SPI bus. Because of that I usually add some external resistors for flexibility. (I'm not developing mass production devices and a resistor costs nothing.)QuoteI will try that next time when I get a chance to play around.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 18, 2023, 04:18:23 am
content: Quote from: temperance on October 17, 2023, 11:24:20 pmIt depends. If the V/I ratings are varying then yes. There are also speed controls, presumably by way of Miller effect plus driver strength, rather than output/buffer strength itself.I think FPGA pins are more flexible, obviously when LVDS and others types are available, but also in drive strength and speed; MCUs tend not to be quite as flexible; they're largely going to be LVCMOS if anything, or wholly different (analog functions).Actually I don't know, maybe application CPUs have that kind of flexibility, but it's maybe less common you'll be using alternate pin functions on those as you need most of the pins for Flash, RAM and peripherals (most of which will be special purpose i.e. HDMI, Ethernet, PCIe, etc.). Shrug.Tim

author: temperance
author_rank: Super Contributor
timestamp: October 18, 2023, 07:42:01 am
content: QuoteThat's what I thought they would be doing when the manual states low...high speed in three steps for the STM series. The correct description would be an output with adjustable drive strength.

author: wek
author_rank: Frequent Contributor
timestamp: October 21, 2023, 08:36:08 am
content: Quote from: T3sl4co1l on October 18, 2023, 04:18:23 amAre yousure?JW

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 21, 2023, 12:40:41 pm
content: Yes, I am sure.Are the V/I ratings varying?Then yes!Mind, I was speaking generally, not specifically about any particular STM. I don't know enough about them to know if theyalluse (output) drive strength control. So I wasn't going to make such a statement, that would be foolish.I also didn't bring up an example I'm aware of (AVR since XMEGA or so) because that's outside the scope of this thread (STM).CheersTim

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 21, 2023, 07:09:10 pm
content: Quote from: uer166 on October 18, 2023, 12:17:51 amYes. The most common approach is just to parallel more or fewer transistors internally. It does decrease or increase Rdson ultimately, so for all practical purposes it *does* limit slew rate, unless the load had no capacitance at all, which just does not exist in real life. Whether it limits it enough for a particular case in terms of EMC does of course all depend on your circuit and requirements.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: October 22, 2023, 12:14:50 pm
content: Output transistors are (I think) much bigger then all the other on die transistors. So to me it seems more logical to control some miller capacitance to adjust the speed of the output transistor.But it should be easy to measure too, by putting a "heavy" DC load (20mA?) on the pin. If multiple transistors are paralleled, then the output voltage "fault" should change depending on the speed setting, while with a miller type circuit would stay the same.