Sequential power up circuit - tell me what you think - Page 1
Forum section: electronics / projects

author: poorchava
author_rank: Super Contributor
timestamp: May 17, 2012, 09:14:43 am
content: So for some time I've been designing a stepper motor driver board to use in my CNC mill and maybe sell a few pieces to friends. The core of this design is TB6560AHQ integrated controller+chopper+powerstage IC. Whole circuit is basically an application schematic from the datasheet with few very minor tweaks.Now the core problem: this chip is widely used in popular cheap chinese 3/4/5 axis cnc drivers which you can buy from ebay starting at around $50. Apart from having some serious design flaws coming mainly from cost-cutting these boards have nasty habit of causing damage to the main IC. Based on the materials found all over the net it's reasonable to think that most of the failures come from improper powering up sequence. The IC has separate power supply pins for powerstages (up to 35V recommended) and for logic supply (standard 4.5-5.5V). It's explicitly stated in the datasheet that power stage supply should be turned on AFTER logic supply is stable and turned off in exactly opposite sequence (ie. power stages may never have supply voltage applied without control logic powered up). What most boards do is just power logic from powerstage supply through linear regulator (like lm317). This of course introduces some delay and can cause the forbidden conditions mentioned above. I wanted to make my design as robust as possible, so I came up with something like this:Bypoorchavaat 2012-05-17How is this supposed to work: when you power up the device, supply voltage ramps up (because of large filtering caps in the supply), voltage is not applied to the powerstage because the MOSFET gate is pulled up to the source potential. The voltage rises to the point, where regulator outputs proper 5V. Roughly at this point the npn bjt is turned on (4.3V zener + Vbe of bjt are roughly 5V or and some conduction occurs at around 4.8V). When this happend MOSFET gate is pulled low by the bjt. Since mosfets usually withstand maximum gate-source voltage of around 20V, I've added a 15V zener to ensure that gate insulation breakdown doesn't occur. In short: this circuit ensures that power is applied to the IC only after there is sufficient logic supply voltage.On the top of that the project is very cost-aware and pcb-real-estate-aware (i want to stuff all this + whole TB6560 circuit) onto itead 5x5cm pcb). The component selection justifications:-MOSFET was chosen because of sufficient power and voltage rating. I wanted to use something in SO8 or TSOP6 package, but these packages have much lower power dissipation which requires much lower Rdson and as a result they cost much more.-bzx84 series zeners because they are cheap, widely available and power rating doesn't matter much-lm317ld because of small footprint (so8), high input voltage (I-O differential up to 40V) and sufficient current capability (main IC logic draws less than 10mA). S08 packages are also cheapest ones.-bc847 because they have sufficient parameters, small footprint and because of got like 0.5k of those at homeThe question goes: do you see any obvious design flaws or things to fix?

author: Kremmen
author_rank: Super Contributor
timestamp: May 17, 2012, 12:47:54 pm
content: Looks like that could do it.The zener in the BJT base circuit could be a bit iffy. Probably it works but the voltage margin is small and you have to be careful that the base current is sufficient to drive the transistor enough to pull the fet gate low enough to open that and drive it to saturation.Can i offer an alternative idea: why not use an old fashioned relay. P channel fets have worse Rdson than N channel ones, and they all suck compared to a good relay. A delayed turn-on is dead simple to arrange by connecting a thyristor in series with the relay coil and triggering it with a simple RC timer and zener in the gate connection.I attached a simple schematic which is actually a 1-phase power transformer inrush current limiter. The 2 rightmost legs in the circuit form the RC delay + thyristor trigger. By adapting the circuit to release in correct sequnece that might be one way to do what you want.

author: Bored@Work
author_rank: Super Contributor
timestamp: May 17, 2012, 01:53:11 pm
content: Why not let the professionals handle it?http://www.linear.com/product/LTC2924

author: Kremmen
author_rank: Super Contributor
timestamp: May 17, 2012, 02:52:59 pm
content: Maybe because those sequencers are intended for totally different applications, like powering up FPGAs, microcontrollers and suchlike. Their design decisions are aimed at totally different voltage levels, like 1 to 5 volts and there is no assurance that they would be suitable for controlling a motor power circuit. Maybe, but i wouldn't bother. The end result would be no better than what you can accomplish by a few simple, easily understood components.

author: chrome
author_rank: Regular Contributor
timestamp: May 17, 2012, 03:03:02 pm
content: And I bet the price will be a lot higher too, seems to need a lot more parts too.

author: poorchava
author_rank: Super Contributor
timestamp: May 17, 2012, 03:17:52 pm
content: Relay would've been a good solution but it has one big disadvantage as compared to MOSFET: size. I've actually changed the idea to different mosfet: Vishay Siliconix SI4447ADY-T1-Ge3. They exibit Rdson of 45 miliohms @ Vgs=-10V. This translates to 1.125W of power dissipation at Id of 5A. Package can handle 1.6W even in bad conditions. Cost is also very low: about $0.60.Also relay probably has slower reaction time, higher cost and wears out mechanically (although modern ones can handle millions of cycles so this is probably not an issue)The thing I'm worried is about is that this pcb will heat up to around 40-50 *C, which will definitely alter tripping voltage of the zener diode (IIRC voltage increases) so this may cause transistor to turn off, which will cause mosfet to turn off which will lead to unstable operation or even oscillation (OR i can call it a feature and use as overtemperature protection).I think there's no other solution than to actually cuild this thing up and check (according to simulation in LTSpice it works)

author: Bored@Work
author_rank: Super Contributor
timestamp: May 17, 2012, 09:19:44 pm
content: You failed to recognize that his solution barely meets part of his own requirement:Quote from: poorchava on May 17, 2012, 09:14:43 am

author: Kremmen
author_rank: Super Contributor
timestamp: May 18, 2012, 05:45:55 am
content: Quote from: BoredAtWork on May 17, 2012, 09:19:44 pmWhich is why i included the words: "By adapting the circuit to release in correct sequnece  that might be one way to do what you want. " My circuit was not a power sequencing one in the same sense, so it was built to different requirements. It was meant to be just an example of the simple delay, not a ready made solution.

author: poorchava
author_rank: Super Contributor
timestamp: May 18, 2012, 09:14:40 am
content: Quote from: BoredAtWork on May 17, 2012, 09:19:44 pmIn simulations when voltage on the logic input falls below 4.8V the bjt no longer pulls the mosfet gate low and power stage supply is being cut-off by mosfet. This is ok, because IC is specified to function properly from 4.5V. I'm worried, that inpractive this may become unstable and I'm pretty sure it will need some tweaking

author: TerminalJack505
author_rank: Super Contributor
timestamp: May 19, 2012, 01:49:01 am
content: Here's another way of going about it using comparators. This circuit will introduce a delay (dependent upon Vlogic) as well as enable/disable Vpowerstage based on the level of Vsupply.The comparators are powered from the 5V rail. This could be a drawback as compared to your circuit.The two comparators and the 2.5V reference can be found on a single IC. (TSM109, for example.) Also, the two pairs of resistors/transistors on the comparators' outputs can be replaced with a single NAND gate with an open drain/collector output. (Assuming you can find one that can handle the 35V pull-up.)The simulation covers a power-up and power-down sequence. I didn't bother modeling the dependency of the 5V rail (Vlogic) on Vsupply. Note that Venable is the signal that would drive the MOSFET's gate in your circuit.R3 and C1 determine the delay on the 5V rail. This is about 70ms with the values shown. The 2.2 uF cap can be found in 1206 ceramic packages to reduce space.R1 and R2 determine the Vsupply voltage below which the MOSFET is disabled. (~23V, with the values shown.)

author: TerminalJack505
author_rank: Super Contributor
timestamp: May 19, 2012, 08:18:35 pm
content: Here's another idea. This one is a variation on your circuit using a TL431.

author: TerminalJack505
author_rank: Super Contributor
timestamp: May 20, 2012, 06:23:57 am
content: I didn't like the power-down characteristics of that last circuit. So here's another that's a mix of the first two. It uses two TL431s in a NAND structure.Nice thing about the TL431s is that they're really cheap.In case you're wondering, I kind of adopted your requirements to play around.

author: poorchava
author_rank: Super Contributor
timestamp: May 20, 2012, 10:00:05 pm
content: Ok, so the PCBs are off to itead studios. We gonna see if it works. Last time it took them 3 weeks to deliver my order.

author: TerminalJack505
author_rank: Super Contributor
timestamp: May 21, 2012, 08:31:19 pm
content: Let us know how it works out. I simulated your circuit as well and--in the simulator--it behaved pretty well. I'm just curious how it will behave in real life.

author: poorchava
author_rank: Super Contributor
timestamp: May 22, 2012, 07:51:32 pm
content: I'm sure that I'll have to do some trial-and-error adjustments. Especially that I didn't even try to find exact SPICE model for the mosfet, so expecially gate charge/discharge time may vary. Also the one I chose is quite usable as a logicl-level mosfet with capable of -6.1A of drain current @ Vgs of -4,5V (Rds=0.062R), so some reasonable conduction will occur earlier.When fiddling with component values I found out that circuit timing is quite sensitive to values of gate pullup resistor, RC filter before the zener and resistor in series with collector of npn. I only hope that these values won't vary to much between different batches of zeners and transistors.

author: poorchava
author_rank: Super Contributor
timestamp: June 14, 2012, 01:23:15 pm
content: Ok, so the circuit is assembled. It behaves just as expected:this is how the power-up sequence works. Didn't record power-down yet (i was really late in the night when I've finished putting it together)Blue trace is voltage after the p-mos and yellow one is logic supply from regulator.