hybridfree/eevblog-posts huggingface dataset:
FPGA development board with MIPI - Page 1
Forum section: electronics / general

author: learnfromfailures
author_rank: Contributor
timestamp: January 14, 2024, 01:15:10 am
content: I searched online for a less expensive dev board that can have MIPI CSI-2 to USB 3.0 functionality with Xilinx FPGA. Most of the development boards start at $275 or up. I thought I should build one since I have an FPGA board design background. I'm planning to keep the cost close to $100. So far with the HW it is a feasible target. The board will also have I2C, SPI, UART ports, and other GPIOs. I needed this board for my project but happy to release it in the public domain. I'm not sure if I should add more features that can make it into a more generic development board. Any thoughts?

author: coromonadalix
author_rank: Super Contributor
timestamp: January 14, 2024, 04:05:47 am
content: start with the obvious need, and when you have a working prototype, add 1 feature at the time ...when you add too many things at once, your coding may become a mess and new stuff may or could break the other ...and for sure it may or could go beyond your target pricingmy 2 cents

author: Scrts
author_rank: Frequent Contributor
timestamp: January 16, 2024, 08:01:58 pm
content: Is there any point to have such board ifInfineon/Cypress EZ-USB CX3exists andalso a devkit?This is solely for cost purposes? So you will deliver a working FPGA image for this? Or we will need to do it ourselves just to save $299-$100=$199?

author: glenenglish
author_rank: Frequent Contributor
timestamp: January 16, 2024, 10:57:29 pm
content: what's the main reason for the cost limit ?help me understand. I might be able to recommend something more appropriate.A big xilinx dev board is only $2000.Otherwise, I would suggest a MIPI M or J 484 board for a Ti180 from Efinix, about USD800 I think. cheap. and good .

author: learnfromfailures
author_rank: Contributor
timestamp: January 19, 2024, 01:15:21 am
content: Quote from: Scrts on January 16, 2024, 08:01:58 pmThere are so many development boards out there. I didn't find any with Spartan 7, USB-c 3.0, and mipi interface close to the 100-dollar range. Something like these boards1)https://shop.ztex.de/product_info.php?products_id=102(this one cost around 500 Euro)2)https://www2.hdl.co.jp/en/ft600-series-m/edx-009-m1.html(1000 USD)QuoteNeeded it for my own project but I'm happy to release it in the public domain. The low cost was natural since I'm not using CX3 chip. I will pick an external Camera module (5-12 megapixels) that can be purchased separately.QuoteI will deliver the FPGA config image and for MIPI you can use Vivado DSI IP. For USB 2.0 to JTAG FPGA, I will write code for the FT2232 chip.

author: learnfromfailures
author_rank: Contributor
timestamp: January 19, 2024, 01:17:35 am
content: Quote from: glenenglish on January 16, 2024, 10:57:29 pmI'm on a budget and I can't really go over that for my own project. So I'm trying to keep the board cost close to 100.
CPLD passthrough in ISE - Page 1
Forum section: electronics / general

author: _pat_
author_rank: Contributor
timestamp: January 16, 2024, 04:00:30 pm
content: Hello All!Please forgive me if this is obvious.... but....Whilst trying to debug some hardware which uses a 9500XL series CPLD as (among other things) an address / CS decoder to allow a single SPI controller to access more devices than is inherently possible with a microcontroller on its own, a situation arose where I wanted to remove the address decoding and only ever drive one chip's select :The combinatorial logic thus went from something like :Code:CS3 <= NOT ( (NOT A0) AND A1 AND (NOT CS) );to simply :Code:CS3 <= CS;This results in both the CS3 and CS pins on the device being unconnected and ISE complaining about LOC constraints for CS3. It seems to be identifying that, without any logic in the path, the two nets are the same and it seems to be deleting one of them during the optimisation, thus leaving them unconnected (but it is not treated as an error). Interposing "any" logic that cannot be optimised out does restore the connectivity. But despite trying various attributes I have yet to find any way to persuade ISE that it should take a signal directly from an IBUF to an OBUF.I'm not sure if this is as one might expect or if it is incorrect behaviour by ISE. It might make much more sense with a non-top-level module, after all if the input and output signals are the same then why bother going through the module at all, why not just route the "output" through the fabric "directly" but for top level there is no higher level fabric to pick up the actual output.Open to suggestions to persuade ISE to connect an IBUF to an OBUF rather than optimise a net away breaking connectivity.Cheers,Pat.
First design with FPGA, DDR4 and Hyperlynx SI simulation - Page 1
Forum section: electronics / general

author: chipeater
author_rank: Contributor
timestamp: January 08, 2024, 05:09:23 am
content: Hello,For the first time, I'm designing a board with not only an SoC ( Xilinx XCZU4EV-2SFVC784I ), but also DDR4 and fast signals.I have the Siemens Hyperlynx simulation tool at my disposal but the results seem strange to me.2 DDR4 chips are connected to the logic part of the SoC and 4 DDR4 chips are connected to the system part. ( All 6 chips are identical ).When I simulate the logic part, the IBIS model of the FPGA pins is as follows: DWC_D5MQ4_34 or DWC_D5MQ4_34ODT40 depending on whether we're reading or writing.On the other hand, when I simulate the system part, the IBIS model for the SoC is as follows: HP_POD12_DCI_F_OUT.The layout constraints for the router are the same for both sections (DDR4 logic part and system part) in terms of single-ended and differential impedances.And yet, I get the best results by selecting ODT40 for the logic part on the DDR4 side, whereas for the system part, I have to choose ODT120 (almost the same result as with ODT240).With ODT40 I have 100% fail in data write, problem of exceeding limits in max slew rate and max slew rate 2.Question:Does it seem normal to you to have to select 120R ODTs when the data bus is routed to respect a single ended impedance of 40R +-10%?Or are you thinking more of a Hyperlynx tool configuration problem on my side?Thank you very much for your help
Original SiLego Mixed Signal FPGA Legacy- Old Software? - Page 1
Forum section: electronics / general

author: jwet
author_rank: Frequent Contributor
timestamp: February 09, 2024, 04:46:12 pm
content: In mining some of the dark spaces of my lab storage, I ran across 5 Original SiLego development boards and a half reel of SLG46200V devices, an 8 pin device with a DAC, ADC, counters, a couple comparators, oscillators and a bunch of LUT's. The dev board and the software was quite well done- drag and drop interface of circuit blocks. The dev board is also well done other than having a Male USB A sticking out of its side. It had pots, switches, test points and LED's that made goofing around really easy- fun. I used these on some projects and got a bit obsessed with them. I bought the 5 boards and reel of parts from a University Lab Instructor off ebay. Shame to throw this all away.These parts are obsolete and SiLego has changed hands a couple of times (Dialog to Renasas). They still make similar devices but my devices aren't made any longer and my dev board isn't supported. Does anyone have the old software (circa 2015?) that works with these old boards and parts. I just want to goof around with them. Any help or leads appreciated. I've looked in some forums with no luck. Replacing what I have with all the latest, greatest would be a few hundred...Thanks in Advance.

author: jwet
author_rank: Frequent Contributor
timestamp: February 11, 2024, 02:37:37 am
content: SOLVEDHidden in plain sight on Renesas page for SiLego, "Legacy Software"- supports old devices and tools.
Verilog Assign Logic to Wire Array? - Page 1
Forum section: electronics / general

author: hal9001
author_rank: Regular Contributor
timestamp: December 23, 2023, 07:54:47 am
content: I have 3 wire arrays like thiswire [3:0] a;wire [3:0] b;wire [3:0] c;I want c=a & b, c=a & b, c=a & b, c=a & b. Instead of assigning each wire manually is there a one line way to assign the logic?Cheers!

author: ataradov
author_rank: Super Contributor
timestamp: December 23, 2023, 08:05:49 am
content: c = a & b; would do that.

author: hal9001
author_rank: Regular Contributor
timestamp: December 23, 2023, 08:37:55 am
content: Quote from: ataradov on December 23, 2023, 08:05:49 amThanks
Need documentation for bittware XUP-VVP - Page 1
Forum section: electronics / general

author: zephen
author_rank: Newbie
timestamp: October 12, 2023, 06:24:53 pm
content: A company I work with apparently didn't read this post:https://www.eevblog.com/forum/fpga/used-bittware-board/So I'm in a similar situation. They bought an XUP-VVP on ebay, and Bittware apparently considers it a legacy product, and won't support it.Anything would help. Constraint file, clock frequencies, whatever.TIA

author: Cute
author_rank: Newbie
timestamp: December 16, 2023, 10:19:57 pm
content: Hi, I think I have everything you need, you can DM me if you want.
Pango Micro FPGAs? - Page 1
Forum section: electronics / general

author: dawnclaude
author_rank: Contributor
timestamp: January 07, 2022, 03:18:16 pm
content: Just saw couple of boards featuring these FPGAs on the Alinx amazon store page. Has anyone here had experience with this stuff?https://www.pangomicro.com/

author: dawnclaude
author_rank: Contributor
timestamp: January 09, 2022, 04:26:23 pm
content: Unfortunately all I know is what Google can translate from their webpage. As I said saw couple of dev boards on theAlinx Amazon store. Though you will need to scroll down a bit.$79 for gigabit ethernet, HDMI and 12k LUTs doesn't sound too badbut need more information especially about vendor tools

author: client
author_rank: Contributor
timestamp: December 29, 2023, 08:50:52 am
content: those devices were designed by a famous company in China named ZiGuang micro, which is highly reliable and many of those have been used in industry fields,even in the aerospace fields

author: brucehoult
author_rank: Super Contributor
timestamp: December 29, 2023, 10:01:52 am
content: Quote from: client on December 29, 2023, 08:50:52 amHow would you say they compare to GOWIN, who have some interesting looking devices recently? e.g. the Zynq-like devices with RISC-V hard cores and up to 138k LEs

author: client
author_rank: Contributor
timestamp: January 02, 2024, 10:54:53 am
content: ZiGuang's technology is far ahead of Gaoyun, but perhaps some kind of Gaoyun's devices are cheaper. Ziguang micro even has some chips that is similar to /can replace Zynq series.
FPGA SPI Timer, help needed - Page 1
Forum section: electronics / general

author: Alakis
author_rank: Newbie
timestamp: December 15, 2023, 01:44:11 pm
content: I am trying to design an FPGA timer using SPI data as input. It is supposed to send data to different timer buffers to set its parameters. During debugging I noticed that when DATA_READY is set HIGH all Data bits are undefined, I've attached the vivado project to this post. If anyone has any insights on what's wrong with the code please let me know!
Tindie.com & Micro-Nova order frustration (it finally arrived!) - Page 1
Forum section: electronics / general

author: davep238
author_rank: Contributor
timestamp: December 04, 2023, 10:04:22 pm
content: I placed an order on Tindie.com on October 24, for a Micro-Nova Mercury-2 FPGA board and baseboard. Tindie immediately charged my credit card. I don't know why I just didn't order directly from Micro-Nova. I still haven't received my order. Tindie has not responded to my emails. I've had frequent emails with Micro-Nova, but it takes 2 - 3 days to get a reply. Supposedly they sent my order on November 21 via USPS, but apparently the post office lost it. Micro-Nova said they may send me another board, but so far, have not. I just emailed them to send me another board (via UPS or FedEx). I've kept my emails with Micro-Nova cordial, but I've run out of patience.The board is for a hobby project, so there's no hard deadline. I have ordered a Digilent CMOD-A7 as a backup.Any suggestions of what else I can do, would be appreciated.-Dave Pollum

author: davep238
author_rank: Contributor
timestamp: December 09, 2023, 03:35:32 pm
content: I finally convinced Micro-Nova to resend the Mercury-2 FPGA board and Mercury baseboard, which they did on Tuesday Dec 5. It was sent via UPS, from Michigan. I received it on Friday Dec 8. Finally! What an ordeal. No more bleeping post office!Ordering from Tindie was a mistake as it added at least 8 days.BTW, I ordered a Digilent CMOD A7-35T (from Digilent) on Friday Dec 1 (25% off), and it arrived on Wednesday Dec 6. It shipped from Taiwan. Yaah FedEx!

author: uer166
author_rank: Super Contributor
timestamp: December 14, 2023, 04:43:42 am
content: I also had issues with Tindie, but honestly it's still pretty good for for finding weird custom boards.
Two basic GreenPAK SLG46826 SPLD questions - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: December 10, 2023, 12:10:04 am
content: I am playing with simple SPLD design using Renesas SLG46826 and have a couple of questions. All the files of my example are herehttps://github.com/zapta/GreenPAKs/tree/main/blinky.1. Let's say I add a 4 pin connector for in-circuit programming using an external programmer, with pins GND, SDA, SCK, and VCC. Do I need to have on my board pullup/down resistors for the SDA and SCK signals and can I leave them floating? When I experiment with an actual chip, the SLG4DVKGSD programmer provides the necessary pullups when I connect it, the programming goes through with no problem, and the chip works.2. In my design I am using a counter cell that has two inputs, clock and reset. The clock is connected to a clock signal and the reset is left unconnected (as visualized in the design software, I don't know what is actually programmed). The simulation and the actual chip work and the Rule Checker of the Renesas design software doesn't complain. Is it safe to leave it 'unconnected' in the design?

author: c64
author_rank: Frequent Contributor
timestamp: December 10, 2023, 12:42:23 am
content: Quote from: zapta on December 10, 2023, 12:10:04 amMy guess is if nothing is connected, 000000 will be programmed, which means ground (if you look at Connection Matrix section)
GreenPAK SPLD blinky? - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: December 09, 2023, 08:56:42 am
content: I am trying to design a minimalist 1Hz blinky circuit using a SLG46826G GreenPAK SPLD. OSC0 does support 1HZ using its pre and post dividers but that clock cannot be routed to an output pin. Instead, I had to use a 2Hz clock and a counter that divides it by 2 and passes it to an output pin. Am I missing something? Is there a simpler 1Hz blinky?The design files and timing diagram are herehttps://github.com/zapta/GreenPAKs/tree/main/blinky

author: c64
author_rank: Frequent Contributor
timestamp: December 09, 2023, 10:52:27 pm
content: Output pin can only be connected to The Matrix. And oscillators have only two of the outputs (green ones) going into The Matrix. The orange ones can only go to the clock input of a counter (and maybe clock input of something else, I didn't read entire datasheet)So, looks like it's the easiest way to do it.P.S. All of the above is just my understanding, after reading datasheets and playing a bit with their software.
Need help writing to XDMA - Page 1
Forum section: electronics / general

author: notooth
author_rank: Contributor
timestamp: November 26, 2023, 03:46:58 pm
content: I sent 32 bit data from a pointer on host to a 256 bit width XDMA h2c. I expected to send it in 1 clock cycle, but it sent in 2 clock cycles. Can anyone help?
Need decode the 8B10B data sequence of 1.3Gbps speed within Lattice FPGA LFE-5UM - Page 1
Forum section: electronics / general

author: namyelus
author_rank: Newbie
timestamp: November 23, 2023, 11:16:51 am
content: Hello All Community,I'm currently working on a project involving decoding UFS (Universal Flash Storage) output signals using an FPGA. My setup includes an oscilloscope to monitor the UFS input/output signals and the FPGA's decoded output. I've encountered an issue where error bits are present in the FPGA's decoded output. The oscilloscope waveform reveals that the FPGA's signal processing speed is not reaching the required 1.3Gbps.To address this, I've made software and firmware updates but have not replaced the FPGA hardware. During testing, I discovered a potential solution: synchronizing the FPGA's PLL (Phase-Locked Loop) output with the UFS input/output frequency might resolve the issue.The PLL output frequency is largely influenced by its source signal. Currently, there are two clock signals on the FPGA board (200MHz and 52MHz), which I plan to replace. My next step is to calculate a suitable operating frequency and order a new crystal oscillator accordingly.After replacing the crystal, I aim to complete the UFS input/output in High-Speed (HS) mode within one week..Here's where I need your expertise:How can I best synchronize the FPGA's PLL output with the UFS input/output frequency to reach the desired 1.3Gbps?What considerations should I take into account when calculating the new operating frequency for the PLL?Are there any potential pitfalls or common mistakes I should be aware of when replacing the crystal oscillator on the FPGA board?Any insights or suggestions from the community would be greatly appreciated!Thank you in advance for your help!
Replacing a Color Prom on a Donkey Kong Jr Arcade with a GAL22v10 - Page 1
Forum section: electronics / general

author: RiddledTV
author_rank: Newbie
timestamp: November 21, 2023, 03:47:13 pm
content: Goal: replace an 82s129 Bipolar PROM from a Donkey Kong Jr with a GAL G22v10.Footprint and pin outs of the GAL does NOT need to match the order of the PROM, as it already has more pins so I will be building an adapter PCB.I was able to complete the equations and compile everything in WinCupl and get the correct outputs.Now I would like to mimic the Chip Enable (active low) feature of the PROM. The prom actually has 2 CE pins, but in my application they are tied together, so I only need one CE.I see in the documentation that the G22v10 has a tristate output feature, but I can't seem to find an example or documentation that shows how to implement the High-Z state.My Question: How can I create the appropriate code so that when the CE is HIGH, the output pins are all "HIGH-Z" state.Attached is my sample code

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 21, 2023, 04:19:02 pm
content: Quote from: RiddledTV on November 21, 2023, 03:47:13 pmoutputname.oe=!ce

author: woofy
author_rank: Frequent Contributor
timestamp: November 21, 2023, 04:20:49 pm
content: I can't test it, but from page 2-10 of the WinCUPL User’s Manual:Outputx.OE = !InputCE

author: RiddledTV
author_rank: Newbie
timestamp: November 21, 2023, 07:02:52 pm
content: Thanks for your quick responses... I'm doing my best to understand. Do I just add another statement after the output equation like this?Code:/* *************** INPUT PINS *********************/PIN 1 = CE/* *************** OUTPUT PINS *********************/PIN 23 = OUT1 ; /* supports 8 OR terms */PIN 22 = OUT2 ; /* supports 10 OR terms */OUT1 = !B & !A# F & D & !A# !E & !D & C & !A# F & E & !C & !A# !G & F & C & !A# !G & !E & D & C & B & A# !G & !F & E & !C & B & A;OUT1.OE = !CE;

author: RiddledTV
author_rank: Newbie
timestamp: November 21, 2023, 07:19:01 pm
content: It seems to compile like that. Thanks for your help. I'll follow up if that does not work as hoped.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 21, 2023, 07:46:16 pm
content: Quote from: RiddledTV on November 21, 2023, 07:02:52 pmyes
No pulse in CLK test points - Page 1
Forum section: electronics / general

author: Farah
author_rank: Contributor
timestamp: November 18, 2023, 11:21:04 am
content: I have a downhole tool. This tool supports a DSP board and an auxiliary DSP board. The operation of the tool is normal without any problems. Even as long as the tool inside the oven reaches 90 degrees, its performance is not a problem. But when the tool is turned off by the user, it will not turn on again until it cools down. In one of the DSP boards at the test point (TMS320F2812), clkin can be seen on the scope, and at the same time there is no clkout, and it is the opposite in the other board. Although this board is functioning properly before shutting down, does this have anything to do with the overheating problem?
ATF15XX Dev DK2 example file PLDs  etc - Page 1
Forum section: electronics / general

author: JimboJack
author_rank: Regular Contributor
timestamp: November 06, 2023, 01:27:50 am
content: morning,Hi ,I have ATF15XX-DK3 board and learning simple CPLD design for a small project in 5.0V vintage land same as me. I wonder if anyone has the example files or copy of the ISO CDROM of the previous release of the board the ATF15XX-DK2 as these examples are in PLD format as the old documentation states part example i can then start to cross compare and learn were as the ATF15XX-DK3 single example file is in VHDL from their website , therefore you need to licence up the prochip 5.01 to compile simple example were wincupl is currently free , 'everyone shakes head slowly ' I know, just wonder if anyone in the bottom of the draw has these files handychecked internet archive, searched the web to no avail. yes can use quartus 13.0 sp1 but want to see the PLD file , not many examples to learn from.thks allJames

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 06, 2023, 05:22:08 am
content: For simple designs, you are likely best to stick with WinCUPL.The CPLDs are not complex parts, and sometimes you need mapping control, easier in CUPL than VHDL.You can run CUPL command line, with any favourite text editor.There is some info here, including using Altera flows and POF2JED to target ATF15xx pldshttps://github.com/peterzieba/5Vpldon the various pathways to develop.

author: JimboJack
author_rank: Regular Contributor
timestamp: November 06, 2023, 09:34:55 pm
content: thks

author: Beta_vulgaris
author_rank: Regular Contributor
timestamp: November 08, 2023, 07:22:39 am
content: You can download ProChip on Microchip website:https://ww1.microchip.com/downloads/en/DeviceDoc/ProChip5.0.1.zip, install it and changelc_checkoutfunction to ALWAYS return zero in lmgr*.dll. I have posted it before.

author: TomS_
author_rank: Frequent Contributor
timestamp: November 10, 2023, 07:36:03 pm
content: Here's an example of an ATF1502AS in which I implemented a shift register for a project of mine. A CPU writes a byte to it and it shifts it out into some LED drivers.https://github.com/tomstorey/Z80_clock/blob/master/CPLD/z80_clk_shiftreg/Z80_CLK_SHIFTREG.pldIt's a fairly simple example but it's a working example.After this I tried implementing a CRTC for a VGA like graphics card but gave up and switched to Quartus and Verilog and had much more success - Quartus could fit sooo much more in than I could.I still use WinCUPL for developing GALs but for CPLDs I moved on to better tools. Hope that helps.

author: JimboJack
author_rank: Regular Contributor
timestamp: November 10, 2023, 08:13:33 pm
content: thks allwith the other examples listing above, inside prochip 5.0.1 had examples of PLD coding , quartus as well i head to my cave and experiment.
Renesas SLG46826 GreenPAK SPLD, what are the three memory regions used for? - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: December 09, 2023, 02:05:20 am
content: The SLG46826G has three memory regions, each with 2048 bits. What each region is used for and what are the difference between them. I do understand how a set of 2048 bits configures the devices but am not sure why three areas instead of one.https://www.mouser.com/datasheet/2/698/REN_SLG46826_ds_3v18_DST_20230226-3075827.pdf

author: ataradov
author_rank: Super Contributor
timestamp: December 09, 2023, 02:30:13 am
content: First is the actual SRAM configuration, it is loaded from the second on power up or programmed manually from I2C. Second is the persistent configuration storage. Third is just a spare EEPROM, can be used as a regular EEPROM to store arbitrary data. It is not used by the device itself for anything.

author: zapta
author_rank: Super Contributor
timestamp: December 09, 2023, 02:44:16 am
content: Thanks Alex, this is very clear.
xilinx Z7 (7Z045) control chip warms up quickly at boot time - Page 1
Forum section: electronics / general

author: maozheng110
author_rank: Newbie
timestamp: November 05, 2023, 12:50:55 pm
content: 1, xilinx Z7 (7Z045) PS side mounted DDR, Z7 and DDR die is sealed together as system in package, now the low temperature -40 °, PS side mounted DDR initialization error, rise to -20 can be initialized, currently want to let the chip in the BOOT to let the chip heat up the temperature of the DDR, let the chip in the boot heat up, while the boot constantly detect the temperature of the internal temperature diode, rise to a certain temperature before initializing the DDR. boot constantly detect the temperature of the internal temperature diode temperature, rise to a certain temperature before the initialization of the DDR, please advise whether this method is feasible, whether at the same time so that the PL side can load the configuration or constraints after the special bit file, so that the FPGA is also hot, I feel that it is necessary to use all the resources than the normal run full performance is still hot, similar to the kind of internal error heating!2、How to let zynq PL load bit file without PS

author: FlyingDutch
author_rank: Regular Contributor
timestamp: November 05, 2023, 01:27:55 pm
content: Hello @maozheng110,maybe this link will be helpful:https://www.harald-rosenfeldt.de/2017/12/27/zynq-run-fpga-without-ps-and-sdk/Best Regards
FPGA Bluetooth Project - Page 1
Forum section: electronics / general

author: Razvan1203
author_rank: Newbie
timestamp: November 03, 2023, 11:33:01 am
content: Hello. I want to make a project involving Nexys A7 100T with the Pmod BLE Module attached to it. And separately I want to use an ultrasonic sensor (positioned at the gate outside), which measures the distance to it and transmits the data over bluetooth to my FPGA board.For this project, which bluetooth module to use additionally near the sensor outside? Which bluetooth module is compatible to Pmod BLE Module?And how can I make the circuit at the gate outside?I really need any kind of advice. Thanks in advance!

author: Maister
author_rank: Contributor
timestamp: November 03, 2023, 09:18:33 pm
content: Hi,there are some Arduino board with built-in BLE like thehttps://store.arduino.cc/products/arduino-nano-33-ble.There us also a conprehensive library for BLE on Arduino:https://www.arduino.cc/reference/en/libraries/arduinoble/.I would connect your ultrasonic distance sensor to that Arduino and transmit the data over BLE.I assume you have one of those HC-SR04 sensors. You can read about how to get their data with an Arduino here:https://howtomechatronics.com/tutorials/arduino/ultrasonic-sensor-hc-sr04/.Additionally I found some of my old code for an Arduino to interface to one of those sensors and print over uart:Code:const int SENSOR_MAX_RANGE = 300;int trigger = 5;int echo = 2;unsigned long duration = 0;unsigned long distance = 0;void setup() {Serial.begin(9600);pinMode(trigger, OUTPUT);pinMode(echo, INPUT);}void loop() {digitalWrite(trigger, LOW);delay(1);digitalWrite(trigger, HIGH);delayMicroseconds(11);digitalWrite(trigger, LOW);duration = pulseIn(echo, HIGH);distance = duration/58;if (distance > SENSOR_MAX_RANGE || distance <= 0){Serial.println("Out of sensor range!");} else {Serial.println("Distance to object: " + String(distance) + " cm");}delay(100);}I don't know enough about BLE that I cannot say for sure that the BLE Arduino is able to send data to the BLE Pmod. But I would assume it should work.BR;Patrick
Pmod BLE Module with MCU - Page 1
Forum section: electronics / general

author: Razvan1203
author_rank: Newbie
timestamp: November 03, 2023, 11:31:45 am
content: Hello everyone! Does the Pmod BLE Module work with Arduino/MSP430 or any other MCU? If I need a bluetooth project involving an FPGA project on the one hand and a MCU on the other hand, is it possible to use two Pmod BLE Modules ?Thanks in advance.

author: Maister
author_rank: Contributor
timestamp: November 03, 2023, 01:20:47 pm
content: Hido you mean the "Pmod BLE" by Digilent ?That one is controlled via a uart, so almost any MCU can interface with that (any that has a HW UART or is able to implement a soft UART). If I am not mistaken that holds true for almost every arduino board. Just keep in mind that he Pmod BLE by Digilent is working with 3.3V logic. The MCU has to have this I/O voltage as well. Else you need a level shifter.Yes, you can use multiple Pmod BLE Moduls in your project but they will appear with different MAC addresses.You could also interface the MCU with the FPGA and ust only one as host with your Pmod BLE.BR;Patrick
BGA Confusion - Page 1
Forum section: electronics / general

author: guenther_jena
author_rank: Newbie
timestamp: October 16, 2023, 09:45:16 pm
content: Started working on a design using the Lattice ECP5. Looking at the device LFE5U-25 there are package options with BGA (0.8mm pin-to-pin distance) having 256 or 381 pins. Looking at the available IO pins, I would've guessed the more available pins the more IO pins the chips will have (but probably not growing proportional for reasons). But the number of IO pins are the same for the 256 and 381 pin BGA - why does the bigger package even exist?See on page 11 here in the datasheet:https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/ECP5/FPGA-DS-02012-1-9-ECP5-ECP5G-Family-Data-Sheet.ashx?document_id=50461.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 16, 2023, 10:00:07 pm
content: Footprint compatible with a larger/smaller part?Thermal consideration?Cost? (low pinout part in lower cost packaging for low I/O use cases).

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 16, 2023, 10:49:07 pm
content: Pin-out compatibility is the most likely reason, for an easy upgrade/downgrade from the -12 to the -45 variant for the 256-pin package. For the 381-pin package, it's from the -12 to -25 (not up to -45, probably for marketing reasons).I haven't looked at the footprints to see if the 256 BGA and 381 BGA have common pins (so a common footprint could be used).Thermal reasons could play a role maybe, just look at the number of IOs between the 256, 285, 381 and even 554 BGA. The very large 554 BGA has few IOs relatively.But otherwise it's often just subtle marketing decisions.

author: Someone
author_rank: Super Contributor
timestamp: October 17, 2023, 04:34:36 am
content: 256 caBGA (14 x 14 mm) no parts with transceivers381 caBGA (17 x 17 mm) smallest parts with full transceiver count (identical IO count to 256 caBGA parts)Pretty common for FPGAs
FPGA Nexys A7 100T Board with PMOD ESP32 - Page 1
Forum section: electronics / general

author: Razvan1203
author_rank: Newbie
timestamp: October 27, 2023, 11:17:01 am
content: Hello everyone! I'm working on my bachelor's project and my wish is to create something interesting and interactive involving my FPGA Board (Nexys A7 100T).My idea is to attach the PMOD ESP32 module to the board and interact with a camera and other sensors via bluetooth/wireless communication in order to create a security system. And I'm not sure how can I achieve this...what camera to use and how can I make this communication works ? I will take into consideration any idea or advice.Thank you in advance!
inout with physical pins in Verilog - Page 1
Forum section: electronics / general

author: ivan747
author_rank: Super Contributor
timestamp: October 18, 2023, 09:10:40 pm
content: Hi everyone,I am on Quartus Prime and assigned a pin to a inout in the assignment editor. Just to be 100% sure (I don't want to fry my dev board):When I set this inout to 1'bz is the pin automatically setup as an input?For microcontrollers you normally have two separate registers: one for pin direction and one for the output value when the direction is set to output. But on FPGAs it looks like there is no separate register controlling direction (in the code). This is why I ask.

author: ataradov
author_rank: Super Contributor
timestamp: October 18, 2023, 09:28:14 pm
content: Yes, and you have the same semantics as in the MCUs. Typically if you want the pin to be bidirectional,you would do something likeCode:assign io_pin = oe_w ? value : 1'bz;The pin is always available as an input, you are just enabling or disabling the output driver and setting the driven level.Also, some FPGA tools do require separate explicit control for the direction. Efinix is one example for this.

author: langwadt
author_rank: Super Contributor
timestamp: October 18, 2023, 09:30:46 pm
content: Quote from: ivan747 on October 18, 2023, 09:10:40 pmyes an inout pin assigned Z will be input, the alternative is manually instatiating a tristate output buffer and then control the tristate enable

author: asmi
author_rank: Super Contributor
timestamp: October 18, 2023, 10:36:22 pm
content: Most tools will instantiate an IO buffer automatically once they see instruction like the one provided byataradov, but if you need more control over the buffer (for example enabling/disabling ODT if it's available), you will need to manually instantiate the corresponding primitive. These are usually described in detail in documentation for your FPGA family.

author: ivan747
author_rank: Super Contributor
timestamp: October 24, 2023, 12:01:28 am
content: Thank you everyone. I can confirm the IO is working as expected, no damage.
PMIC for Z7020 - Page 1
Forum section: electronics / general

author: abpreen14
author_rank: Newbie
timestamp: October 09, 2023, 01:06:53 pm
content: Hi,I am kind of working on variant of plutoSDR,I am replacing the z7010 with z7020 and AD9363 with AD9361. My board size is 55x40mm, So real estate is premium.Looking for a single PMIC to power DDR3L 512MB and z7020.Current Design uses bunch of TLV62130( 4 IC's) and TPS7A8101(3 IC's)

author: asmi
author_rank: Super Contributor
timestamp: October 09, 2023, 05:18:09 pm
content: Take a look at tps65400. It's a quad-channel buck, which can provide all rails a typical design requires - 1 V, 1.35/1.5 V, 1.8 V and 3.3 V. If you want even more compact solution, consider using four MPM3632C modules - they contain integrated inductors so they take very little PCB space.

author: nimish
author_rank: Regular Contributor
timestamp: October 19, 2023, 01:52:39 am
content: Quote from: asmi on October 09, 2023, 05:18:09 pmI like the MPM54304 -- all 4 in one module w/ inductors (!) but no PMBus.

author: asmi
author_rank: Super Contributor
timestamp: October 19, 2023, 03:21:50 am
content: Quote from: nimish on October 19, 2023, 01:52:39 amYeah that looks interesting too, but it looks like it's going to require some kind of system controller MCU to program voltages if I understood it correctly from the quick glance at the datasheet.

author: Evan.Cornell
author_rank: Regular Contributor
timestamp: October 19, 2023, 12:31:00 pm
content: Maybe MMPF0100?https://community.nxp.com/t5/i-MX-Processors/MMPF0100-PMIC-VTT-Rail/m-p/602806

author: langwadt
author_rank: Super Contributor
timestamp: October 19, 2023, 01:32:34 pm
content: Quote from: asmi on October 19, 2023, 03:21:50 amafaict only "0000 Suffix Code", looks like the other suffixes are just 0.6V references and external dividers, each suffix with slightly different startup delays/order
Has somebody tried TCL scripts with "Gowin EDA" (Gowin FPGA Designer) - Page 1
Forum section: electronics / general

author: FlyingDutch
author_rank: Regular Contributor
timestamp: November 05, 2023, 03:07:00 pm
content: Hello Forum,I would like to ask if someone tried TCL scripts with "Gowin EDA" (Gowin software for FPGA designing). Gowin documentation says that Gowin software supports TCL commands (see paragraph 8 ):http://cdn.gowinsemi.com.cn/SUG100E.pdfI am wondering if someone tried to use TCL scripts with "Gowin EDA" projects? Especially I am interested in using TCL scripts from Vivado - I would like to ask if someone tried to adapt Vivado scripts to "Gowin EDA" software?Update:I tried today TCL in version 1.9.9Beta6 (under Linux OS) and TCL generally is not working, I tried TCL both from "TCL console" (command gw_sh) and in TCL console in "Gowin EDA" (GUI). Even such basic TCL commends as "create_project" or "add_files" are not working.Maybe somebody has different expierience with TCL in "Gowin EDA" and can share it.Best RegardsThanks in advance and regards
help on choice programmer JTAG - Page 1
Forum section: electronics / general

author: GGMM
author_rank: Frequent Contributor
timestamp: September 30, 2023, 06:27:39 pm
content: hello,I’m trying to repair a Rigol 1052E oscilloscopeThere is a lot of reading about it and I have no history of what was done on it. I think a 100mhz update had to be attempted and failed, blocking the boot.There is a lot of reading on this subject (I also put some posts).What I would like to know is what kind of JTAG programmer it takes to program (also read the content) the S29GLO64 circuit.Knowing that I do not want to put a fortune in a programmer and that in fact I would only use it once without being sure of the result.May you give me some examples that are suitable from the site Ali....s. I am a bit lost in all the models.Thanks for your help.

author: laugensalm
author_rank: Regular Contributor
timestamp: October 02, 2023, 11:18:29 am
content: Hi,I assume you're trying to get at the Blackfin code (not the FPGA side of things, thus?). I have an old DS1102, I believe they were based on the same cores with different peripherals, though.The easy way used to be ICEbear JTAG (discontinued), you might get lucky with other FT2232H based solutions and lots of messy hacking around OpenOCD or urjtag.
why I get BAD PACKET ERROR? - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 21, 2023, 12:25:42 pm
content: Hi,I have designed a new PCB for Xilinx Kintex Device (XC7K325T-3FFG900I), Power supplies are ok, and every single rail is in spec like 1.0V , 1.2V , 1.5V, 1.8V, 2.5V & 3.3V, and I have tested each power rail with a constant current load that I have that can sink 3A from each rail, also the powers are sequenced the right way and scope shows the correct sequencing, the programming cable finds the chip correctly, I have written a simple counter that would toggle a led, when I program the device the done would not go high, the hole board uses around 1.3 wat's of power and every device on the board is at room temperature and seems ok,The content of status register before programmingQuoteThe content of status register after programmingQuoteThe only change is a BAD PACKET ERROR flag? Do you have any Idea what might be wrong or causing the problem?

author: FlyingDutch
author_rank: Regular Contributor
timestamp: October 22, 2023, 06:55:58 am
content: Hello @ali_asadzadeh,if you attach a schematics and PCB board design it would be easier to find potential causes of issues.Best Regards

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 22, 2023, 10:19:46 am
content: I have removed the series resistors (33 ohm) in JTAG line and now it's working
FPGA bargain on Ebay - Page 1
Forum section: electronics / general

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: September 28, 2023, 07:55:40 am
content: PCB with 4x Stratix V FPGAs listed at over 10K on Digikey for $75 - seems a pity to scrap for gold, though might need paid version of tools.https://www.ebay.com/itm/134726118367

author: deepfryed
author_rank: Unknown
timestamp: September 28, 2023, 08:08:57 am
content: and "new never used", shame for it to end up in a scrap pile

author: RoGeorge
author_rank: Super Contributor
timestamp: October 02, 2023, 08:09:08 am
content: For production might not worth, but for students/makers/hobbyists who do not care about the provenience of the .lic files, and also have the time to reverse engineer the PCB, $75 is a bargain.The only thing that might be a showstopper is when the FPGA is a pre-engineering sample. These are usually distributed in very small number to big OEM contractors only, so the OEM can develop their own products based on a not yet launched FPGA. Such samples have "incomplete" silicon, good to load/test HDL designs, but they are not fully working, for example they don't have the IO pins connected, or things like that.Since the ebay lists many boards, those are most probably fully working FPGAs.
How to pipeline DSP48 input? - Page 1
Forum section: electronics / general

author: notooth
author_rank: Contributor
timestamp: September 18, 2023, 11:02:05 pm
content: I got this warning in Vivado. Can anyone tell me how to fix?Quote

author: asmi
author_rank: Super Contributor
timestamp: September 18, 2023, 11:31:19 pm
content: Add pipeline registers in front of/to the output of DSP?

author: notooth
author_rank: Contributor
timestamp: September 18, 2023, 11:37:09 pm
content: Yes, I think so.

author: hamster_nz
author_rank: Super Contributor
timestamp: September 19, 2023, 12:01:16 am
content: If the design meets timing, then don't bother.Otherwise add a set of pipelining registers to what is being multiplied, and cross fingers that the tools match the pattern and pull the pipelining registers into the DSP block.

author: notooth
author_rank: Contributor
timestamp: September 19, 2023, 12:12:12 am
content: The design failed timing. Can you send me a tutorial or an example of non-pipelining registers and pipelining registers?

author: hamster_nz
author_rank: Super Contributor
timestamp: September 19, 2023, 02:10:09 am
content: You might find useful examples in "Vivado Design Suite User Guide Synthesis" or maybe "XST User Guide for Virtex-6,Spartan-6, and 7 Series Devices"https://docs.xilinx.com/v/u/2017.4-English/ug901-vivado-synthesishttps://docs.xilinx.com/v/u/en-US/xst_v6s6But the shortest explanation is to store the inputs for the multiplication in registers, and then use the contents of the registers for the multiply.Code:process(clk)beginif rising_edge(clk) thenresult <= regA * RegB;-- Input registersregA <= inputAregB <= inputB;end if;end if;

author: notooth
author_rank: Contributor
timestamp: September 19, 2023, 02:39:58 am
content: There is no multiplication in my module:Code:module add_tlast (output reg sa_tlast_out = 0,input aclk);always @(posedge aclk) beginsa_tlast_out = 1;endendmodule

author: hamster_nz
author_rank: Super Contributor
timestamp: September 19, 2023, 05:57:11 am
content: Perhaps then the multiplier is in a different module?The one that uses this module's output?

author: hamster_nz
author_rank: Super Contributor
timestamp: September 19, 2023, 06:40:54 am
content: Oh, also note: IIRC you can't have an initial value for the DSP48 interal registers. If you do set an initial value it will prevent the register from being pushed into the DSP block.
Cannot get data from BRAM IP - Page 1
Forum section: electronics / general

author: notooth
author_rank: Contributor
timestamp: September 16, 2023, 02:41:02 am
content: I tried to read data from a XILINX BRAM block by setting an address to `addrb` port, but it did not return the data. Can anyone help? I attached the timing and configurations of the BRAM IP.

author: vstrakh
author_rank: Contributor
timestamp: September 17, 2023, 09:52:24 am
content: What do you mean by "it did not return the data".According to simulation pic you make three writes through port A. Definitely writing address 0 and address 2, and we can only guess the address 1, since is not readable without zooming into the waveform.The port B only reads out changes done on address 0 and address 1. The changes at location 0 done through port A properly lags on port B output. And we don't know what did you write (if you wrote anything at all) at location 1, so it appears that the value read from the location 1 happens to be equal to the value written earlier to location 0.At least zoom in to see addresses/values in each clock where the 'wea' signal is non-zero.
IBIS model for DDR4 memory  - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: September 09, 2023, 08:37:47 pm
content: Hi,I am looking for the IBIS model of the following memory devices. How can I get IBIS models for these memory devices.Micron MT40A512M16LY-062E AIT:E: DRAM DDR4 8G 512MX16 FBGAMicron MT40A1G8SA-062E AUT:E: DRAM DDR4 8G 1GX8 FBGAMicron MT53D512M32D2DS-046 AAT:D: DRAM LPDDR4 16G 512MX32
Interfacing AD9625 with FPGA  - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: September 15, 2023, 12:48:56 pm
content: Hi, I am wondering if we can interface AD9625 with Kintex UltraScale FPGA with GTH. The output data from AD9625 is 8 lane differential through JESD204B interface. The GTH in Kintex UltaScale can operates up to 16 Gbps. Are these GTH good enough to receive data from AD9625?

author: Scrts
author_rank: Frequent Contributor
timestamp: September 15, 2023, 08:16:51 pm
content: Just FYI:https://support.xilinx.com/s/article/66509?language=en_US
Program Cyclone IV with USB blaster from arm64 linux - Page 1
Forum section: electronics / general

author: radiolistener
author_rank: Super Contributor
timestamp: September 04, 2023, 11:03:57 am
content: I want to upload gateware from *.sof file to Cyclone IV board with JTAG from arm64 linux using USB Blaster.I already have precompiled *.sof files, so there is no need to install Quartus and compile *.sof file.What I want is just to upload selected *.sof file into Cyclone IV. Like it can be done from Quartus Programmer under Windows.It can be useful, because allows to do thing from Raspberry Pi machine to not power on desktop PC...Is there any tool for arm64 linux which allows to do it?

author: betocool
author_rank: Regular Contributor
timestamp: September 04, 2023, 11:08:29 am
content: You could try compiling OpenFPGALoader for arm64, I have it running on an Intel Linux machine:https://trabucayre.github.io/openFPGALoader/Don't know if it works.Some other people have good experiences with OpenOCD, but that didn't work for me at all.Cheers,Alberto

author: bingo600
author_rank: Super Contributor
timestamp: September 04, 2023, 03:17:20 pm
content: Not sure ...But maybe the oldjam-staplcould do it (was designed to be lightweight)https://github.com/margro/jam-staplhttps://github.com/kontron/altera-staplOther examplehttps://github.com/htlabnet/Jam_STAPL_for_Arduino/Bingo
Chiptunes! A Dual YM2149 PSG Audio core for BoxLambda. - Page 1
Forum section: electronics / general

author: epsilon537
author_rank: Newbie
timestamp: August 19, 2023, 12:03:59 pm
content: I integrated BrianHG's and Nockieboy's YM2149_PSG_system core (https://github.com/nockieboy/YM2149_PSG_system) to my retro-computer project, BoxLambda (https://epsilon537.github.io/boxlambda/).I wrote a Blog post about it:https://epsilon537.github.io/boxlambda/dual-ym2149-audio-core/Thanks to Nockieboy and BrianHG for making this core available.
Xilinx ISE Ceil and Floor Can't Synthesize But Can Simulate? - Page 1
Forum section: electronics / general

author: hal9001
author_rank: Regular Contributor
timestamp: August 17, 2023, 12:04:32 pm
content: Im using Xilinx ISE 14.7 for Spartan 3A project. I want to use $ceil and $floor to calculate parameters in my verilog file.Test bench simulates without error.Synthesize gives this errorCode:ERROR:HDLCompilers:26 - unexpected token: '$ceil'ERROR:HDLCompilers:26 - expecting ';', found ')'ERROR:HDLCompilers:26 - unexpected token: '$floor'ERROR:HDLCompilers:26 - expecting ';', found ')'The code isCode:parameter NUMBER = 2.5;parameter integer CEIL_NUMBER= $ceil(NUMBER );parameter integer FLOOR_NUMBER= $floor(NUMBER );Is there a work around?Cheers