Is this ground plane broken? - Page 1
Forum section: electronics / projects

author: c64
author_rank: Frequent Contributor
timestamp: November 29, 2020, 04:23:12 am
content: Signal in question is marked with arrow.The bottom plane (blue) is ground.The pin on the bottom is ground pin.

author: c64
author_rank: Frequent Contributor
timestamp: November 29, 2020, 04:32:04 am
content: My guess is plane not broken in option 1, but broken in option 2.Current flows from signal pin to die, then to ground pin.In option 1 it will always flow above the ground plane, even if it needs to cross the vertical trace.Is it correct?

author: tmadness
author_rank: Regular Contributor
timestamp: November 29, 2020, 04:53:05 am
content: Well you dont have a trace cutting across the break on the red layer so "technically" you are not breaking the ground plane. Is it still a good idea? no, I personally avoid 2 layer designs where I can. design #1 should be fine

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 29, 2020, 06:01:00 am
content: Right, neither matters as shown because nothing is crossing the region in question.Add some supply pins perhaps, or escape other signals in various directions, maybe it would matter.Edit: I just realized the one pin is grounded. So yes, the ground return currents would prefer to flow as indicated, and have to loop around the slot in the right hand case.Or maybe it still doesn't matter. I don't mind gaps of that size, for general purpose digital logic -- up to say, most LVCMOS stuff (MCUs, 74LVC logic, etc.), and assuming the application isn't particularly critical (precision timing, low EMI). Still, avoid frustrating supply currents in this way.Whereas for high speeds, you'll probably be using differential routing and 4 layers anyway, in which case getting a solid ground under the route is much easier.Which can maybe still be done on 2 layers, assuming the footprint can be escaped (rules out almost all BGAs, and even a lot of QFNs and QFPs), component placement works out (also a big ask), and the impedance is flexible (it will be higher due to the larger signal-to-ground height; a higher termination resistance is then required, which will give lower bandwidth due to pin capacitances).Or for power switching circuits, you may or may not need 4 layers for fanout or placement, but the low inductance paths afforded by unbroken planes and pours is mandatory.Ed 2: here's an example of 2-layer routing of fairly fast circuitry (~80MHz), but still LVCMOS level. It is fairly noisy up close, but the gaps are short and away from connectors, avoiding common mode (mainly conducted) emissions. Notice the stitching vias, jogged crossings to allow some stitching under buses, and lightly grouped bottom side traces crossing under the first row of pins.https://www.seventransistorlabs.com/Images/DisplayCtrl_SDRAM_TopBottom.pnghttps://www.seventransistorlabs.com/Images/DisplayCtrl_SDRAM_Top.pnghttps://www.seventransistorlabs.com/Images/DisplayCtrl_SDRAM_Bottom.pngTim

author: c64
author_rank: Frequent Contributor
timestamp: November 29, 2020, 06:51:03 am
content: It will be LVCMOS, no issues with escaping the footprint at all. Clock speed will be between 100 and 150 MHz.

author: Andreas
author_rank: Super Contributor
timestamp: November 29, 2020, 08:20:35 am
content: Quote from: c64 on November 29, 2020, 04:32:04 amHello,you also have to regard the current back to the source.And you have to regard the fact that closely neighboured signal ground pairs have a significant lower inductivity (factor 3-5) than a widely opened loop (antenna).So option 2 hinders the back flowing current in GND plane (which would normally concentrate below the signal line) to take the way with the smallest loop area.So yes: the ground plane is broken and will lead to excessive RF radiation. (approximately proportional to the loop area before and after cutting the plane).with best regardsAndreas

author: ConKbot
author_rank: Super Contributor
timestamp: November 29, 2020, 03:41:15 pm
content: Depends on the frequency content of the signal. For a 9600 baud UART with an appropriately tame slew rate, no. For a 200 mbps single ended signal, yes, where it transfers, can't say off the top of my head. But it's still not good practice regardless, and still going to add impedance to the current loop. Decoupling caps need to be incorporated for a more complete picture of the AC current paths, along with an idea of frequencies involved to say if it matters or not.The classic, not very helpful "it depends".

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 29, 2020, 08:46:38 pm
content: Quote from: ConKbot on November 29, 2020, 03:41:15 pmNote that, if both are internal to an MCU say, the pins are likely to have the same output characteristics (or the capability to do so anyway), so even your 9600 baud signals will have the same edge rate as the 200Mbps stream. The emitted EMI will be on average, proportionally lower by the clock frequency (i.e., 200M/9.6k times), but the peak value will be the same (same edge rate and height).Often, MCUs have a programmable slew rate or drive strength option, and this should be set accordingly, to break the above assumption. Or conversely, if the default level is slow, you may find you have trouble driving fast signals -- in either case, it's worth checking!Tim

author: KT88
author_rank: Frequent Contributor
timestamp: November 30, 2020, 01:21:54 pm
content: For DC everybody knows that the current flows the path of the lowest resistance.When it comes to AC especially at higher frequencis current flows the path of the lowest impedance. The lowest impedance is found as close to the signal trace as possible - directly under the trace (smallest possible loop area). If there is an obstacle in the return path, the return current is forced around the obstacle. This acts as an inductor with all it's properties as reducing the edge rate, resonaces (ringing) and of course RF emissions as well as susceptability to RF.In case you only have a few signals, it might be still manageble to make sure that no obstacles are blocking the current return path. But this includes already bypass capacitors as ConKbot mentioned.Partitioning and placement could also help to get away with a two-layer PCB design.In all other cases it almost everytime causes trouble if you slot the groundplane.CheersAndreas