Yet another constant current load -updated! - Page 1
Forum section: electronics / projects

author: PeterF
author_rank: Contributor
timestamp: September 17, 2012, 06:19:59 pm
content: Hi everyone! Just joined this forum, been following the blog for quite some time...I recently started designing a rather modest constant current load at work, with an aim to achieve a few hundreds of watts.After quickly reading through a few posts about similar designs here, I decided to go for a chopper stabilized OP, and chose the following one:TC7650CPAhttp://ww1.microchip.com/downloads/en/devicedoc/21463b.pdfI also grabbed a few of these, with the hope to use perhaps 4 of these:IRFP4568PBFhttp://www.irf.com/product-info/datasheets/data/irfp4568pbf.pdfTo the issue:The attached schematic shows the setup which is causing me an issue. When trying to set 1 Volt (and 1 Amp), I get about 1.6 V and 1.6 Amp. (The positive input to the OP is 1 Volt, and the negative is 1.6 Volts)When I raise (V2) the load voltage up to above 10 Volts, the current goes down to the set value.I have read a couple of similar posts here, but I couldn't really find any relevant help.I am not sure where to begin to sort out my problem, so could anyone point me to which parameters and effects that might be causing this result I am observing?Thanks in advancePeter

author: krish2487
author_rank: Frequent Contributor
timestamp: September 17, 2012, 07:36:40 pm
content: Just a stone in the dark but i "think" that the op-amp is being driven into hard saturation.From what i read in the datasheet of the TC7650 i think because the opamp supply voltage is greater than the load's voltage, the recovery time of the op-amp might be the culprit. i m guessing somthing to do with the mosfet acting as a variable resistor and the Vds and Vgs thingy.given in "output clamp"(its 2 in the morning and i m sleepy and drooly over my keyboard, but either i am totally wrong and/or i am not able to connect the dots properly wrt the output clamp and your peculiar problem)as i said, i "think" and i m not 100% sure.

author: AndyC_772
author_rank: Super Contributor
timestamp: September 17, 2012, 07:47:16 pm
content: The op-amp must be saturated if the input voltages are significantly different.It seems like an odd choice of op-amp. I'd choose something simple, low cost and with rail-to-rail input & output. Something like LMV358, perhaps.What's the voltage on the output of the op-amp when the circuit is erroneously delivering 1.6A?

author: PeterF
author_rank: Contributor
timestamp: September 17, 2012, 07:54:58 pm
content: krish2487: Thanks for your reply.AndyC_772: The output of the OP-amp was measured to about 6.X Volts I believe (I can run tests tomorrow when I get back to work) in this state.Is it just me, or does the OP not seem to be saturated, or can it still have been saturated even though its output is well below 12V?Perhaps I can pick another OP, I have a few of these now though and would love to be able to use them (or at least fully learn why NOT to use them)

author: AndyC_772
author_rank: Super Contributor
timestamp: September 17, 2012, 08:47:49 pm
content: Seems odd, maybe the problem is with the FET. Is it worth just double checking that it's connected correctly?Plenty of op-amps saturate well below their positive supplies, but I don't think I've ever seen one that needs that much headroom. Something's not right there.

author: PeterF
author_rank: Contributor
timestamp: September 17, 2012, 09:01:51 pm
content: Yes, I thought it was very odd too.. I have previously rechecked the connection, and even wired up a second identical system to be sure the OP wasn't broken or something..I can try to explain the problem a bit more:When running with 4 Volt load, everything works like a charm up to about 0.3V/0.3A. Then this behaviour of the negative input going above the positive starts appearing. This increases more and more, and I didn't dare running it for a longer period with more than 1 Amp set ( and 1.6 Amp actually drawn ).And then, when I increase the voltage slowly, the difference between V- and V+ decreases, where somewhere around 10-12 Volts I believe, the thing works as one would expect.. I can then go up to 20-30 Volts with no problem, drawing 1 Amp..

author: PA4TIM
author_rank: Super Contributor
timestamp: September 17, 2012, 10:34:29 pm
content: Your schematic sucks ( sorry to be so bold but I can not make it sound better)This is a very beefy MOSFET with a huge gate capacity. You do not use a fetdriver or even a resistor with speedup cap. This will be hard for a normal opamp but you choose a chopper ?The opamp is an instrumentation chopper amp. These are not made to source lots of current and drive capacitive loads. A very strange choise. You use a chopper because it zeros very well but that FET does not do a thing under 4 Vgs so a chopper has no advantage here.The opamp sees 1V on the plus input and zero at the negative. It throws its output high to compensate but to get 1A through the FET and 1V over the load, the FET Vgs must be for instance 6V ( see the graphs for the precise voltage). But the gate capacity causes a big delay and the chopper does not stop rising before both inputs are equal and so he goes upto his rail before the current is 1A. He then saturates. Chopperamps are great in saturating and staying locked up. ( see datasheet part 3.6 and up)I made a powersupplys and a dynamic load using BRFP256, so the small brothers. I had to use two opamps parallel to get enough drive. A chopper delivers just a few mA, most times a lot less as a normal opamp. Put a power opamp beteeen the chopper output and the mosfet. Place a resistor with speedup cap, use a snubbernetwork at the gate and ferite to damp oscillations. ( have you looked if it is not just oscilating, I had something similair when i designed a fan refulator with opamp and mosfet, the scope showed it started oscillating from a certain setting)

author: PeterF
author_rank: Contributor
timestamp: September 18, 2012, 07:25:31 am
content: Thanks alot for your reply PA4TIM!Be as bold as you like, makes learning faster!I know that the thought behind my component choices was poor, I just wanted something to play around with while learning and fine-tuning my design.I measured the output of the OP, and yes of course, it was oscillating wildly! Between 4-8 Volts to be more precise.Does this oscillation indicate that the OP is too slow driving the MOSFET, and which would be the simplest and neatest solution to this issue? (other than replacing the OP, which I may end up doing anyhow..)I found another set of OP-amps lying around;Fairchild KA258http://www.farnell.com/datasheets/3634.pdfI might hook one of these up instead to see difference. Since I will be powering my design with 12V, rail-to-rail isn't really my biggest concern.. What I really want is a minimal offset and drift, from what I've understood..Thanks again for all the help, haven't really worked with any "real" analog electronics since school, but this is where the fun's at!

author: PA4TIM
author_rank: Super Contributor
timestamp: September 18, 2012, 08:15:33 am
content: Your welcome, I never learned electronics at scool so I gues you have a headstartThe oscillating is rather complex. Especcially with choppers while they oscillate inside by nature. Oscillating in opamp schematics has to do with phase delay and gain. 180 degrees delay and unity gain at a certain frequency makes that it starts oscillating. Every RC combination, for instance the Rout ot the opamp and the gate capacity form RC networks and so phaseshifts.Your design must have enough Phase margin as it is called. If you want to know more about it look for laplace transfornmation, bodeplots and poles and zeros. But that is very, very complex stuff. I know the principle but my math is not good enough to do the transformation (i have done it recently for a smps compensation network and it took me hours and then I found out I started with the wrong value) but by playing with resistors and capacitors , and as Bob Pease calls it, banging the output with a squarewave, I most times find a way.You can start to insert a resistor (10-100 Ohm between output and gate, and a speedup cap over it to compensate for gate capacity ) this will give a phaseshift and most times is enough to stop the oscillaions. Bob Pease gives some other solutions of RC compensation networks in his book troubleshouting analog circuits. on inputs, bewteen inputs, from in to output ect. You must shift the phase.But what you are doing now is trying to use a Ferrari in the Paris-Dakar rally (or Baya race) or using a Mack truck as a golfcart. A chopper amp is a rather extreme device, a FET like this, with upto 20nF gate capacity too, but then on the opposite scale of extremes. Choppers are used to amplify micro signals, I? just using a few to make a voltage reference and because it must be able to drive shielded cables to a KV divider, and buffer the output of the KV I insert OPA277 and LM1010 as buffers. Choppers are not made deliver 4 to 20V to the current hungry gate a power mosfet.Zero offset and drift are not important here. The tempco of the FET is probably many times bigger then the output drift of the worst opamp, the offset of the worst opamp will not make enough volts to drive the FET open. So even a 741 will do.one thing you can try is inserting a normal opamp as follower between the chopper and the gate. The inverting input of the chopper stays at the source. the other opamp is just there to source the power the chopper can not deliver.The drift, offset ect are not important but because the chopper still regulates that it will not become worse (if that makes you feel better)

author: Rerouter
author_rank: Super Contributor
timestamp: September 18, 2012, 08:22:09 am
content: actually one of the better things you can do is add a resistor between the op amp output and mosfet gate, most op amps dont like directly driving capacitive loads, and this can set it up to oscillate like your experiencing,

author: PeterF
author_rank: Contributor
timestamp: September 18, 2012, 09:19:42 am
content: I tried adding a resistor of various magnitudes, but it only amplified or modified the effect, didn't make any noticable improvement.. Any scientific details regarding the choice/effect of this resistor?I am considering trying my simpler OP amp instead, but I still want to figure out what these oscillations are due to and how to fix them.Edit: I also tried adding the 2nd OP (the one I mentioned above) as a output buffer, but this only amplified the effect.Once again, I really appreciate your help!

author: toli
author_rank: Frequent Contributor
timestamp: September 18, 2012, 09:20:17 am
content: I think adding a resistor in series to the gate won't solve the issue without any other modifications. Adding this resistor will limit the maximum current out of the op-amp, but it won't increase the phase margin (it might actually make it worse as the increased resistance lowers the frequency of the pole caused by the input capacitance of the FET).To increase the phase margin you should add both the resistor mentioned, and an additional capacitor in the feedback path between the output of the op-amp and the inverting input. This will increase the feedback at higher frequencies, and will make the loop stable.Because of the low resistance in parallel with the inverting terminal (1ohm), the capacitor will probably have to be quite large (might even be in the uF range). A solution to that problem can be adding an additional high value (say 1K) resistor between the 1ohm resistor and the inverting input of the op-amp. This will allow the use of a much lower capacitance (10-100nF would be a good place to start probably), and won't demand high currents out of the op-amp's output.Edit: Just noticed you've replied while I was writing my post. Try what I've suggested, hopefully it'll solve the issue.Edit2: In response to what you've added - using a second op-amp as a buffer won't help. It adds and additional 90degree or so of phase which only escalates the problem. The second op-amp (being a follower with B=1) will actually be stable, but the outer loop won't be stable unless you add some route for high frequency feedback.

author: Noize
author_rank: Regular Contributor
timestamp: September 18, 2012, 10:22:13 am
content: Add 2 100nF bypass caps to the op amp power rails. One to connect from +ve pin to ground and one to connect from -ve pin to ground. As close to opamp as possible.If you haven't got bypass caps attached then there is a very good possibility that this is causing the oscillation.Use only one cap if its not bipolar supply. Obviously

author: PeterF
author_rank: Contributor
timestamp: September 18, 2012, 10:40:47 am
content: Success!!toli: I followed your advice, and it worked perfectly! I have a perfectly stable output current now, throughout the range. Lovely!This is very interesting stuff, and I would really like to read up a bit on this. Found an old book with stability calculations regarding feedback stability.I am still not entirely sure what may have caused my oscillations, but the issue is very much solved now! Thanks alot everyone who contributed, I will continue working on my design and I'll post some info and specs when I've somewhat finalized this project!

author: toli
author_rank: Frequent Contributor
timestamp: September 18, 2012, 10:48:22 am
content: Glad to hear it workedThe problem is that you must allow sufficient phase margin. By loading it with the high capacitance of the FET you've created an additional pole in the loop (at f=1/(2*pi*Rout_opamp*Cin_fet)) this in turn added an additional phase shift of around 90 degrees as well, leaving no phase margin. By adding the resistor + capacitor you've allowed an alternate path for high frequency through that network, so the phase from the output of the op-amp back to its input has been lowered to below 135 degrees (you usually want at least 45 degrees of phase margin, so a phase of up to 135 degrees).

author: PeterF
author_rank: Contributor
timestamp: September 18, 2012, 10:52:37 am
content: Yes, yes, it all makes sense now! This is great, I was afraid I would never have the time to finish this project properly (this is just a side-project I'm building to have in our lab at work), but now I can finally go on to design the whole system knowing that this part works.Thanks once more!

author: PeterF
author_rank: Contributor
timestamp: September 28, 2012, 09:34:29 pm
content: Update:When running at 10+ Amps and 10+ Volts, I noticed that I still experienced oscillations.. So this time, I did some more detailed simulations and noticed that the previous fix only gave me about 30-40 phase margin.. I added C2 (any better suggestions? bandwith isn't really an issue here I guess(?), so I thought it was fine) which gave me almost 100 degrees of phase margin..Haven't had the time to test the stability with this new fix yet.Other features I've added so far:Paralleled three of these, and with the heatsink and fan that I plan to use in my box, I can manage about 150W for quite some time.Hooked up an Arduino and a LCD which is displaying temperature and current. The arduino will shut the current down at a certain temperature as well.Added reverse polarity protection with a P-MOS (this instrument will sit in a lab where engineers of different schools may enter, there is a chance that someone will hook it up the wrong way). Haven't hooked this up yet.Added pre-charging of the NMOS when 12V is hooked up. Without this, when the load is attached to the NMOS, a current surge occurs. With 50+ volts, this surge was quite a few amps. The value in the schematic might be off, need to check it. It works well any how.

author: toli
author_rank: Frequent Contributor
timestamp: September 28, 2012, 10:20:33 pm
content: Are you sure the issue is the phase margin?If it is, to lower the BW of the circuit (which should also increase the phase margin) all you need to do is increase C1/R3 time constant. You can increase R1 as well just in case the op-amp has very limited output current capability and the output is being limited by the maximum current. Try doubling the value, say 220R and 2.2K. Before doing that read the rest of my post.Adding C2 should actually make it worse, much worse. What you did is put the inverting input terminal of the op-amp at AC ground, instead of increasing the FB at high frequencies you've reduced it.If I were you I'd check if increasing the supply rail from 12V to 15-20V makes a difference. To drive 10A into a 1R resistor you need 10V, add VGS to that and the output should probably be in the 14-15V area. That's more than you have at the supply node. 10V might also be very close to the maximum VCM at the input on a 12V supply. You can try replacing the 1R with 0.47R or 0.5R (2 1R resistors in parallel), this will make the current twice as much as the voltage, but it'll lower the voltage requirement.

author: PeterF
author_rank: Contributor
timestamp: September 29, 2012, 04:13:43 pm
content: Thanks for your reply!I am getting similar behavior to what I had before, only at higher currents now, so I'm assuming it's the margin again..Also when simulating (with a tad different components though) I am getting a phase margin of just about 30 degrees (see picture).Yes of course when simulating again, my solution did about no difference at all.. I lowered R3 to about 100 to get sufficient margin, but this should make for a solution I believe, still have to try it out next week.I don't think the supply rail is the issue, because when I talked about 10+ Amps, this was spread out on three units, so each would be at about 3.3 Amps. My config is limited to 12 amps in total now, so 4 amps/each, which should be fine with my 12 volt rail.Ideally I would have liked to use lower resistors, but since we had a bunch of 50W 1R lying around, I figured I'd make use of them.Thanks once again for your help, I'll post some pictures and measurements when I've had some more time next week.

author: toli
author_rank: Frequent Contributor
timestamp: September 29, 2012, 06:18:27 pm
content: 1. Are you using 3 resistors of 1R in parallel (which would make it 0.33R), or all 3 FET's share the 1R resistor?2. I'm not sure how you are measuring the phase margin, but to do this the right way you need to make a few changes to the circuit. To measure the phase margin (which has to do with the phase of the loop gain and not of the closed loop) you should set the input signal to zero, and insert a test source within the loop. Then measure the ratio of voltages at the nodes of this source.Thisis one of the first things that came up on google.

author: PeterF
author_rank: Contributor
timestamp: September 30, 2012, 12:50:21 pm
content: 1. I am using 3 FET's which have 1R each. Three FET's, three resistors.2. The way I measure phase margin in LTspice:- I disconnect the feedback from the negative input to the OP and call this U2.- I ground the negative input- I run an AC analysis, sweeping the frequency between values seen in the above picture.- I then display V(u2)/V(u1) which should allow analysis of the feedbackloop multiplied with the OP's raw gain (I'm a bit off with the technical terms here, since I'm reading this from a swedish book)Edit: I'm not used to SPice, so I'd gladly receive any feedback (pun intended?) if there seems to be something fishy with my simulationEdit2: Can't you see my attachment in my previous post? It shows how I ran the simulation

author: toli
author_rank: Frequent Contributor
timestamp: September 30, 2012, 12:52:37 pm
content: Hi Peter,I guess there's a problem with the attachmentAnyway, it isn't of much importance, as long as you are sure you're measuring the phase margin the right way it's ok.Keep us posted once you've replaced the resistors to increase the phase margin.

author: PeterF
author_rank: Contributor
timestamp: October 01, 2012, 08:52:00 am
content: For all currents and voltages that I so far was able to test with (up to 30V, 6 Amps) the following changes have fixed the stability issues:* Changed R3 to 68 Ohm* Increased R1 to 1k OhmYet to come is finding out how adding my PMOS polarity switch circuit will affect the stabilitySo far it seems to work great, thanks for your help!

author: PeterF
author_rank: Contributor
timestamp: October 02, 2012, 03:14:04 pm
content: Tested the polarity circuit (Pmos, zener and a 10k R), and measured some ripple when connecting the load the wrong way.Measured about 1V P-P (-0.5V -> 0.5V) ripple on the negative input on the OP. Not sure if this is good enough, or if it could damage the OP and I should find a way to remedy this effect.