Help - Selecting microcontroller for high sample rate - Page 1
Forum section: electronics / general

author: jappie
author_rank: Newbie
timestamp: December 05, 2018, 10:51:19 pm
content: Hi,New here (not sure if this should go into the newbie section), and i need some help!I've taken on a project that out of my comfort zone and i have trouble selecting a microcontroller that can handle that data throughput.issue:4x 16bit ADC @ 1MSPS (ad7980, or similar. using 3-wire spi)Continues sampling, into buffers (4* 640 data points) threshold trigger on 1 buffer.Then offloading to other micro (open to changing that) , for data processing.Ive looked at DMA (mainy stm32 on the lower Mhz scale), i am just lost.Can you guys help me select a microcontroller? (maybe even FPGA)Jappie

author: rstofer
author_rank: Super Contributor
timestamp: December 06, 2018, 12:51:41 am
content: The FPGA could process all the ADCs in parallel into BlockRAM and the data could be downloaded by any scheme you want but I would use USB serial. In fact, I would buy a board that had a USB serial port on it. Most do because they use the port for programming the platform flash (which, in turns, programs the FPGA at startup).Your total data is fairly small, a serial stream at 115,200 baud wouldn't be bad at all.I'm not sure you can find a uC board with 4 hardware SPI channels. Maybe something in the STM lineup. The problem with that is that STM development boards tend to use a lot of pins for other things precluding the use of the peripheral you actually want. I also don't know how you synchronize 4 channels with a uC.I like the FPGA approach. I'm not sure what you are doing about sending trigger patterns or if that is a constant. If it gets very involved, you don't want to do it in HDL. You would want to drop in a soft core and write some code in C.

author: lucazader
author_rank: Regular Contributor
timestamp: December 06, 2018, 01:57:48 am
content: There are quite a few STM processors in the F4 range that have 4 (or more) spi channels.The F411CC for example. 5 SPI chanels, all can be hooked up to a DMA for fast and very low overhead transfers.Alternately:If you can do with 0.9MSPS you could go for one of the STM32H7 series.They include a 16-bit adc with up to 20 channels that runs at 3.6MSPS@16-bit or 4MSPS@14-bit.They that is a super simple setup where you can setup the ADC to do continuous transfers using DMA, and just read the memory when you need!

author: MasterT
author_rank: Frequent Contributor
timestamp: December 06, 2018, 02:14:13 am
content: Figure 41. Chain Mode with Busy Indicator Connection Diagramhttps://www.analog.com/media/en/technical-documentation/data-sheets/ad7980.pdfMay be 1 or 2 SPI would be sufficient.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 06, 2018, 02:40:59 am
content: The easiest way is to find an MCU with buit-in ADCs.For 4 AD7980 you'll need 4 SPI modules which can run at about 20 MHz. Not all MCUs can go that fast, so you'll need to pick ones that can. You also can chain your ADCs, so other options are 2 SPI modules at about 40 MHz or one SPI module at 80 MHz. You also need the corresponding number of DMA channels. That's it. Not quite sure why you would need a second MCU.The biggest problem with MCU is to synchronize everything. Your ADC requires acquisition pulses from MCU, which have to be synchronized with SPI. You can produce the pulses with PWM. You also may need to produce some gaps between SPI bytes, which may be difficult to do with DMA. How easy it is to accomplish the perfect synchronization (or if it is possible at all) depends on the peculiarities of the specific MCU and you probably need to read datasheet very carefully or do some experiments to see how well can you synchronize your SPI with acquisition pulses.Of course, it's all very easy to do in FPGA - it has enough pins and speed to do ether of the three speed variants, and it'll take only few hours to program.

author: rstofer
author_rank: Super Contributor
timestamp: December 06, 2018, 02:55:36 am
content: Quote from: MasterT on December 06, 2018, 02:14:13 amEven 1 channel would be fine because the conversion for all units is controlled by a single digital output from the uC. There are no 'programming' commands so chaining the devices together makes all the sense in the world.

author: MasterT
author_rank: Frequent Contributor
timestamp: December 06, 2018, 03:16:06 am
content: Quote from: rstofer on December 06, 2018, 02:55:36 amI was thinking two SPI if OP needs 1 MHz sampling rate sharp, than SPI clock jumps up >64 MHz, and I don't know any uCPU that could handle such high rate. Wait, seems stm32H7 could get 150 Mb/s, but non of F3, F4 or F7.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: December 06, 2018, 04:56:19 am
content: Quote from: jappie on December 05, 2018, 10:51:19 pmWhere does all this ultimately end up ? 4 * 640 points, sounds like a simple scope ?As already mentioned, 1 MSPS is not particularly fast, so a MCU's ADC's might get close.If you do need external ADCs for noise/speed/location reasons, then a small FPGA with good RAM may be ideal for you.The Lattice iCE40UP5K-SG48I has a decent 128kBytes SRAM, and comes in a QFN48 package - it could do any manner of SPI-ADC buffering.google findsMore standard breakout board ICE40UP5K-B-EVNMore compact version HM01B0-UPD-EVNBoth boards include FT2232H, so you have a 12MBd PC link, if you need that too.

author: rstofer
author_rank: Super Contributor
timestamp: December 06, 2018, 07:14:05 am
content: Quote from: MasterT on December 06, 2018, 03:16:06 amNumber crunching will clearly be required. The maximum clock rate will just about handle 4 devices on one SPI channel. But... What about the rest of the latency? DMA requests, SPI overhead, framing requirements and so on. While we're on the subject, can an IO line really toggle at 1 MHz to start the samples? Is that signal going to come from a timer? We have just 1 uS to start the conversion What is the limit of the uC SPI clock.As it turns out, the AD7980 has a cycle time of 1.2 uS or 833 kHz. It can't do 1 Msps. See tcyc on page 6 of the datasheet.I like the idea of a single conversion start signal for multiple ADCs. Bringing the data in via 4 separate SPI gadgets makes sense and using 4 DMA channels also makes sense. What I don't know is the maximum data rate for the DMA channels (assuming all 4 go ready at the same time).As I said, somebody is going to need to do some number crunching.One thing that hasn't been discussed is whether the data is sampled in burst mode where 640 samples are taken and the process stops for some long period of time or is the sampling continuous and attempting to capture 4 @ 640 samples for some large number of iterations. This matters with the USB->Serial approach if the data capture is done in an FPGA. I don't know what the maximum throughput is for the USB->Serial channel. More numbers...I think I would lay the timing out in a spreadsheet along one line. Use a column for each step of the process. Finally, add up the row and see if the 1 Msps requirement is met.

author: lucazader
author_rank: Regular Contributor
timestamp: December 06, 2018, 08:07:07 am
content: Quote from: rstofer on December 06, 2018, 07:14:05 amAbsolutely. Even basic STM32F0's can do this. If you jump up into the F4/7/H7 range you can probably expect to toggle an i/o at 40MHz.Quote from: rstofer on December 06, 2018, 07:14:05 amQuite a lot of simple micros can do 15MHz +, a lot of mid range ones can do 40MHz.A single chip solution like the STM32H7 Series with two built in 3.6MSPS 16-bit adc with up to 20 channels each should be quite adequate as a simpler one chip does all solution.(i had earlier though it was only one, however now i realise there are two that can both operate at 3.6MSPS, you should be able to read 4 channels at up to 1.8MSPS @16-bit, )With the ADC's in DMA reception mode, all the processor will have to do is read the raw conversion data out of memory and do the math on it.Which the H7 should be more than capable of, 400MHZ core with hardware single and double floating point units.Then depending on the data rate required to a host, either use the inbuilt USB FS device in Virtual com port mode. Or if higher data-rates are required, hook up an external USB HS PHY.Now so as i am not seeming biased to stm products (they are just what I use day to day!) here are a couple of other options:PIC24FJ128GC006 - 2x differential 16-bit adc's @1MSPS, and a 10MSPS 12-bit 50 channel ADC. quite a bit slower processor speed (32MHz)ATSAM4E16C - 2x 16-bit @ 1MSPSLPC55S6x - new, not much info but seems to have a 16 bit 1MSPS adc, not sure on channels etc.

author: hans
author_rank: Super Contributor
timestamp: December 06, 2018, 08:23:50 am
content: Quote from: rstofer on December 06, 2018, 07:14:05 amFor 1.71V < VIO < 3.3V.For 3.3V < VIO < 5V the tcyc value is 1us.I don't think the DMA on the internal memory bus is going to be a problem. I guess any MCU that wants to take a look at 4MSPS of ADC data is going to be 100MHz++, so eating a multifold of 4 million cycles per second from the shared memory bus is not going to kill the MCU's performance. It could slow things though, it can highly depend which SRAM blocks you map the DMA buffers onto. The STM32 parts, for example, have TCM memory that is inaccessible from DMA etc. so that the CPUalwayshas a RAM access without contention. Of course the firmware has to be written such that it mainly uses TCM memory (linker file settings).I also wouldn't go to serial, that is a bus from the stone age when it comes to these higher information throughputs. I would rather look at USB2.0HS(either integrated into MCU or using a parallel memory-style connection), or 100Mbit Ethernet (added bonus: electrical isolation). The latter is particularly easy with modern MCUs, because many high-speed parts have integrated ethernet MACs and only need a 2$ phy and a 5$ connector. But it's perhaps less easy to connect to a PC, as it needs to go over the network (less "discovery")

author: jappie
author_rank: Newbie
timestamp: December 06, 2018, 08:39:43 am
content: Quote from: PCB.Wiz on December 06, 2018, 04:56:19 amIn the end the buffers are used for cross correlation and then a algorithm that does dispensation compensation and localisation.But the idea is that this processing can happen at a later time, and the buffered data can be stored on a sd-card.The external ADC where chosen for noise.

author: lucazader
author_rank: Regular Contributor
timestamp: December 06, 2018, 08:42:04 am
content: Actually just found that the STMM32H750 value line series has 3 of the 3.6MSPS 16-bit adc's. And they can also differential or single ended capable.Along with 1MB of ram, it does have comparatively small flash of 128KB though.And it's in stock at digikey for $7.32@1qty and is less than $4.66@540qtyThat is less than 1/3 the price of a single AD7980 (on digikey for $15.73@500qty and $19.98@1qty.Seems like a bit of a no-brainer to me unless I am missing something..?Please correct me if I am wrong

author: tggzzz
author_rank: Super Contributor
timestamp: December 06, 2018, 09:14:57 am
content: Quote from: jappie on December 05, 2018, 10:51:19 pmYou should also consider all theother activitiesthat the controller might need to do at the same time as sampling the data. With all but one microprocessor family, any other activity could "get in the way" of the sampling. Such unpredictability is a prime reason for offloading sampling and first level processing to FPGAs or other hardware.The only processor family that does not suffer from that problem is the XMOS xCORE family. It dedicates one of many cores to each input channel, has "FPGA-like" I/O with times guaranteed to a 250MHz/4ns clock, and excellent multicore communications.The IDE willguarantee exactloop times, so you canpredictwhether your design will keep up with the input. With all other processors you have tomeasure, and hope you have caught the worst case in your meaurement.Buy the xCORE processors and dev boards at DigiKey. The IDE is free and the timing guarantees can, of course, be tested without hardware

author: jappie
author_rank: Newbie
timestamp: December 06, 2018, 11:27:19 am
content: Quote from: rstofer on December 06, 2018, 07:14:05 amHmm the "featured" Throughput: 1 MSPS, is kinda misleading.

author: MasterT
author_rank: Frequent Contributor
timestamp: December 06, 2018, 01:35:09 pm
content: Quote from: jappie on December 06, 2018, 11:27:19 amDMA shouldn't be a problem. Recently, I've done a few experiments with nucleo-F303re board ( less than $14 CAD).It has 4 adc ( stm32F303re there only one has 4, that I know), capable to sample 5 msps each at 12-bits resolution.DMA throughput becomes an issue if all adc running at full speed, doing 20 msps in total. Than I could not get 12-bits, board does 20 with lower 8-bits resolution. And about 16 msps at 12-bits.uCPU is 72 MHz.Though I'd expect SPI->DMA throughput close to 45 mega 16b words on something like stm32F446 core running at 180 MHz.

author: tggzzz
author_rank: Super Contributor
timestamp: December 06, 2018, 01:49:28 pm
content: Quote from: jappie on December 06, 2018, 08:39:43 amHave you considered shoving it up a USB link or over ethernet as fast as those links allow?A classic use-case for the xCORE processors is to have some cores dedidcated to the USB/ethernet, and others to your specific i/o devices.

author: rstofer
author_rank: Super Contributor
timestamp: December 06, 2018, 03:05:45 pm
content: Do the samples have to be correlated in time? I wouldn't be surprised if they do.A single ADC with multiple channels, even if very fast, won't sample two or more signals simultaneously.

author: splin
author_rank: Frequent Contributor
timestamp: December 06, 2018, 05:48:36 pm
content: Quote from: lucazader on December 06, 2018, 08:42:04 amOk, I don't mind correcting youThe STM32H7 has 12-bit ADCs. Higher resolutions are achieved by oversampling which is done in H/W by averaging. To get 16 bit resolution you need to average at least 16 samples so the maximum sampling rate would be 225kSPS.To match the AD7980 noise performance you might need to average rather more than 16 samples depending on the noise characteristics of the STM32H7 ADC (which is only specified at 12bits and 2MSPS so presumably it will be worse at 3.6MSPS). If the noise is correlated to any degree then the amount of improvement with oversampling will be less than predicted by the usual 1 bit improvement in noise performance by averaging 4 samples (ie. 4X oversampling).

author: splin
author_rank: Frequent Contributor
timestamp: December 06, 2018, 05:54:42 pm
content: Quote from: rstofer on December 06, 2018, 07:14:05 amIt can do 1MSPS - the reduced rate is if VIO < 2.3V or < 3.3V, depending on temperature. See tcyc on page5of the datasheet. Ooops - just noticed that hans already pointed this out, but it looks like jappie also missed the correction!

author: mark03
author_rank: Frequent Contributor
timestamp: December 06, 2018, 07:16:42 pm
content: Quote from: splin on December 06, 2018, 05:48:36 pmTo obtain 16 bits of resolution, you need to downsample by >= 256x, not 16x. Each factor of four gives you one bit, in the best case, if the noise is white and the signal is sufficiently dithered. Also, the simple averaging provided by most MCUs is not really proper downsampling; it is a very loose low-pass filter (sinc^1) followed by the decimate-by-N stage. Better would be something like the DFSDM peripheral on some STM32 MCUs.

author: mark03
author_rank: Frequent Contributor
timestamp: December 06, 2018, 07:18:35 pm
content: Don't forget that you can run the MCU SPI peripherals in slave mode and orchestrate the timing/synchronization using MCU timers, if that makes life easier.

author: splin
author_rank: Frequent Contributor
timestamp: December 06, 2018, 11:01:48 pm
content: Quote from: splin on December 06, 2018, 05:48:36 pmMea culpa - you were right. Which is odd as I bought the STM32H743 Nucleo card for the express purpose of testing the 16-bit ADC performance (but not had time to do it yet)!They are specified as 16 bits at 3.6MSPS with noise performance of 13.5 ENOBs at 2MSPS. So oversampling will be required to match the AD7980 noise performance.

author: splin
author_rank: Frequent Contributor
timestamp: December 06, 2018, 11:33:04 pm
content: Quote from: mark03 on December 06, 2018, 07:16:42 pmNo, averaging 16 samples will give 4 extra bits of resolution but it will only reduce the noise by 2 bits (assuming there is sufficient dither and the noise is Guassian and uncorrelated).QuoteIt is 'proper' downsampling. 'Better' depends on what you are trying to achieve. There are many different digital filter types that could be used with varying tradeoffs including complexity, BW, sharpness, flatness, group delay etc. Averaging and decimation doesn't have a sharp rolloff but it the *optimum* filter in some cases. From page 6.6 of "Mixed Signal and DSP Design Techniques, 2002" by Walter Kester:https://www.analog.com/media/en/training-seminars/design-handbooks/MixedSignal_Sect6.pdfQuoteThe 'better' filters, eg. SINC3, have longer settling times which is a particular problem for multiplexed systems.

author: mark03
author_rank: Frequent Contributor
timestamp: December 06, 2018, 11:36:22 pm
content: Quote from: splin on December 06, 2018, 11:01:48 pmThat is still amazing for an MCU ADC, and one of my favorite things about STM32. Even the ~ 11 ENOB @ 5 MSPS in the STM32L4 is better than most.I think the H7 series also has the DFSDM with built-in connection to the ADC. This lets you downsample by up to 80x in one go (sinc^3 CIC filter).

author: mark03
author_rank: Frequent Contributor
timestamp: December 06, 2018, 11:55:38 pm
content: Quote from: splin on December 06, 2018, 11:33:04 pmSemantics. By this definition you could simply left-shift each sample by four bits and thereby gain your four extra bits of resolution. I think most people would understand an increase in resolution to imply an increase in SNR (by the same amount).QuoteOk, "better" in the sense of being a closer approximation to the textbook downsampler with a brick-wall LPF. Certainly there are other issues to consider, as you point out.

author: splin
author_rank: Frequent Contributor
timestamp: December 07, 2018, 01:53:11 am
content: Quote from: mark03 on December 06, 2018, 11:55:38 pmSemantics are important. Resolution is independant of accuracy and noise. By your argument, the STM32H7 ADC should be called a 13.5bit ADC and the AD7980 as 15bit. That may be a useful way to classify ADCs but it isn't the one that is conventially used. Virtually all ADCs have rather less ENOBs than their marketing resolution. The LTC2500-32 is called a 32 bit ADC but its best specified resolution is approx 24bits.OTOH, some lower resoution ADCs have better intrinsic noise performance than their nominal resolution which means that ENOB will increase by 1 bit for each 2x oversampling (with usual dither, noise characteristics disclaimer). This arises because an ADC can sold with different resolutions, at varying prices by configuring each part's resolution during manufacturing. This can be done on artificial criteria - eg. based on market demands for each resolution, or based on selection on test whereby only the best performing devices are sold as the highest resolution parts.And since you metioned the STM32H7's DFSDM then take a look at how ST show how resolution varies with oversampling ratio (FOSR) and filter type in the attached.QuoteOr to put it another way, not better - different. Which is why some ADCs have a a variety of digital filters built in to allow designers to select the 'best' one for their application.

author: Bassman59
author_rank: Super Contributor
timestamp: December 07, 2018, 04:49:30 pm
content: Quote from: jappie on December 05, 2018, 10:51:19 pmI'd do it all in a small FPGA. Depending on your data processing requirements, you can do that in the FPGA as well.