1.5 to 3 MHz frequency doubler circuit - Page 1
Forum section: electronics / projects

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 27, 2018, 02:00:04 pm
content: I have a design where a Cypress BLE module feeds I2S audio data to a TAS5755M TI Amplifier. The problem is that the Amp needs an extra clock signal called MCLK of 3.072 MHz and it needs to be a doubled, synched multiple the I2S SCLK signal of 1.536 MHz. I built a circuit like this...https://www.maximintegrated.com/en/app-notes/index.mvp/id/3327But there's a lot of jitter and variations on the mark-space ratio on the output so it's very unreliable and only works occasionally.I thought it would be simple to build a PLL circuit set up as a doubler with 1.536MHz in and 3.072 MHz out but all the ICs I've looked at have a minimum output frequency that's too low (I looked at the 74HC4046a and the PT7C4511).Can anyone here suggest an IC or circuit that will meet my needs? My operating voltage is 3.3V.Thanks in advance.

author: jpb
author_rank: Super Contributor
timestamp: December 27, 2018, 02:27:04 pm
content: I'm not a great expert but I thought the 4046 was happy producing kHz. The example in "The Art of Electronics" is using it go go from 60Hz to 61.44 kHz. So I'm surprised it can't do 3.072 MHz as being "too low".

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 27, 2018, 02:43:28 pm
content: Thanks for the suggestion.Maybe there's a 4046 family member that will work but the CD4046B won't run properly at 3.3V and the max Fout is <3 MHz. The 74HC4046A has a min VCO Fcenter of 12MHz - this is all from memory over my recent research so I may have made mistakes. I'm at sea on a cruise in the S Atlantic and the Internet is a bit slow.

author: soldar
author_rank: Super Contributor
timestamp: December 27, 2018, 03:01:58 pm
content: Quote from: Gandalf_Sr on December 27, 2018, 02:00:04 pmThat circuit should work. Is the power supply to the comparator absolutely stable and filtered? If the input is a nicely cut rectangular signal then jitter should not be an issue and the circuit, should not have much jitter.The duty cycle issue is different. The easiest way to have a 50% duty cycle is to start with double the frequency and then divide by two.

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 27, 2018, 03:22:18 pm
content: I stuck with having to double as I can't get to the 3.072 MHz signal that presumably exists inside the Cypress BLE module (I asked). I just posted in TI's e2e forum although it only went through on my 4th try - I have problems with that forum even when I'm on a light-speed connection, doing it over the ship's zoom satellite connection is almost impossible.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 27, 2018, 03:50:38 pm
content: This simple circuit doubler has the benefit of getting you a synchronized clock. But the duty cycle of the output clock entirely depends on the delay block formed by R1/C1 and the comparator.Have you adjusted R1 and C1 accordingly?

author: Benta
author_rank: Super Contributor
timestamp: December 27, 2018, 04:15:01 pm
content: The comparator is unnecessary and just helps Maxim sell a device. An RC delay into a Schmitt trigger and then into the XOR is enough. You'll need to play around with the RC values.

author: MasterT
author_rank: Frequent Contributor
timestamp: December 27, 2018, 04:24:29 pm
content: Dispute with what maxim-IC is recommend, I'd use differentiator RC circuitshttp://www.circuit-finder.com/categories/digital/377/frequency-doubler-with-4011

author: edavid
author_rank: Super Contributor
timestamp: December 27, 2018, 04:25:35 pm
content: Quote from: Gandalf_Sr on December 27, 2018, 02:43:28 pmThe datasheet headline reads:QuoteThat means they guarantee it will go that high, not that it can't go lower. There is no minimum VCO frequency.That said, if you have access to toroid cores, you could build a simple full wave doubler circuit out of a transformer and a couple of diodes. They work much better than XOR gate doublers.

author: Benta
author_rank: Super Contributor
timestamp: December 27, 2018, 04:30:04 pm
content: Quote from: MasterT on December 27, 2018, 04:24:29 pmThat circuit won't give you control over the output duty cycle, but rather deliver spikes at double frequency.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 27, 2018, 04:50:03 pm
content: Quote from: Benta on December 27, 2018, 04:15:01 pmTrue. Note that if you use a 74AUP1G86 (single gate XOR), it has schmitt trigger inputs, so no additional component is necessary.Of course an RC delay is not that stable, especially temperature-wise, so you'll inevitably get some drift of the duty cycle, but that should be ok for the op's application.

author: ogden
author_rank: Super Contributor
timestamp: December 27, 2018, 05:02:57 pm
content: Quote from: Gandalf_Sr on December 27, 2018, 02:00:04 pmYou needtuned LC tankmultiplier likehttp://electriciantraining.tpub.com/14181/css/Frequency-Multiplication-95.htm, fast comparator and divide by two flip-flop to generate 1x clock back from multiplied one

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 28, 2018, 09:34:29 am
content: Wow, great responses guys, thanksI have played with the R1 C1 values but, as has been predicted, the results can drift or be inconsistent.Now I have several choices to look at:1. Use a 74AUP1G86 XOR logic IC with Schmitt trigger inputs1. Use a 74HC4046A PLL IC which will need a divide by 2 circuit for the feedback loop, probably just a JK flip flop2. Use a tuned LC tank multiplier but won't that produce a sine wave output?I'm discarding the transformer rectifier option as too expensive and large.I will order components for all 3 and test each one.Thanks again.

author: ogden
author_rank: Super Contributor
timestamp: December 28, 2018, 09:40:59 am
content: Quote from: Gandalf_Sr on December 28, 2018, 09:34:29 amYes. That's why comparator was mentioned - to convert sine to square wave.

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 28, 2018, 09:47:19 am
content: Quote from: ogden on December 28, 2018, 09:40:59 amSorry, not fully awake yet

author: Wolfgang
author_rank: Super Contributor
timestamp: December 28, 2018, 02:58:13 pm
content: Quote from: Gandalf_Sr on December 27, 2018, 02:00:04 pmThe jitter free solution is a balanced doubler, like here (you need to scroll down a bit):https://electronicprojectsforfun.wordpress.com/a-clean-23cm-signal-source/The advantage of a balanced doubler is best signal quality with very low jitter and cancellation of harmonics.You need to adapt the circuit to 3.3V. If you need a digital output, a Schmitt trigger could be added at the output.

author: ogden
author_rank: Super Contributor
timestamp: December 28, 2018, 03:05:53 pm
content: Quote from: Wolfgang on December 28, 2018, 02:58:13 pmURL does not look right.

author: Wolfgang
author_rank: Super Contributor
timestamp: December 28, 2018, 03:30:51 pm
content: Thanks, I fixed it.

author: edavid
author_rank: Super Contributor
timestamp: December 28, 2018, 04:05:12 pm
content: Quote from: Gandalf_Sr on December 28, 2018, 09:34:29 amA T37-2 core, a few inches of wire, and a couple of diodes are expensive and large?

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 28, 2018, 04:30:31 pm
content: Quote from: Gandalf_Sr on December 28, 2018, 09:34:29 amTo get a much more precise and stable delay, you could also use a digital delay line instead of this RC circuit. Then the XOR gate doesn't need schmitt trigger inputs either.Examples are DS1100L or DS1110L.https://www.maximintegrated.com/en/products/digital/clock-generation-distribution/DS1100L.htmlNot quite cheap but for a few bucks more (around $5 in small quantities), this will be a whole lot better.

author: MasterT
author_rank: Frequent Contributor
timestamp: December 29, 2018, 12:59:50 am
content: Quote from: Benta on December 27, 2018, 04:30:04 pmHave you checked a link? There is time/pulse diagrams, duty circle is manageable over R1C1 & R2C2 adjustment.

author: ogden
author_rank: Super Contributor
timestamp: December 29, 2018, 01:16:48 am
content: Quote from: Wolfgang on December 28, 2018, 02:58:13 pmOMFG! Everything about your universal signal source device is so... sexy. Many shall learn from you. I admire your attention to tiniest details down to "no improvements left" point.

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 29, 2018, 09:19:54 am
content: Thanks for the further input guys. The balanced doubler looks beautiful but it (seems) uses 2 transformers. Part of the original requirement is that the doubled frequency is aligned with the input frequency; won't the transformers add phase shifts as the signal passes through them?Also, the roll-your-own approach is problematic, I'd much rather build with off-the-shelf components.If I can make the PLL device work down to 3.072 MHz it should be fine if I add a comparator or Schmitt trigger on the output but it seems like overkill - I wonder why the TAS5755M is so fussy about the I2S input signal; maybe it needs a register change to affect the way it responds to a bad clock input that becomes OK?[S. American Cruise Update] At sea today, going round Cape Horn tomorrow, and Ushuaia the day after that - been lucky with great weather so far. Wildlife is amazing: penguins, flamingoes, parrots, owls, and sea lions to name but a few. Will get close to 60 degrees South at some point.

author: Wolfgang
author_rank: Super Contributor
timestamp: December 29, 2018, 10:31:55 am
content: Hi,if you insist on stock components you can use Mini Circuits transformers instead of the Balun cores. The rest are stock inductors and capacitors.To phase align the doubled frequency to the fundamental, just divide the digital output by two (74HC74).

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 29, 2018, 10:50:24 am
content: The need for the doubled frequency comes because the TAS5755M amplifier needs an I2S master clock (MCLK) signal that is not provided by the normal I2S signal lineup which provides a serial clock (SCLK), serial data (SDAT), and L/R or word clock (WCLK). So there's data that's aligned with the SCLK clock and my requirement is for a MCLK clock that's double the SCLK but also phase aligned with it, I am pretty sure that I can't use a generated SCLK to feed into the BT module to make it use that clock for generating the I2S signals. Although it's a powerful Amp, the TAS5755M has proved annoying in this respect; the previous design used the same BT module with an Analog Devices SSM3582 Amp that's less powerful but which doesn't need the MCLK clock - the decision to move to the TAS5755M Amp was to get more power output but the MCLK signal and overcoming all its quirks has been a pain in the posterior.

author: Wolfgang
author_rank: Super Contributor
timestamp: December 29, 2018, 11:00:16 am
content: If you need to phase align with the original signal you can use a phase shifter before digitizing.Another idea is a PLL, which does the same with more jitter.

author: Buriedcode
author_rank: Super Contributor
timestamp: December 29, 2018, 04:58:54 pm
content: According to the datasheet, the amplifier can use its internal oscillator, which I assume is phase locked to the SCLK input:QuoteWith an SCLK of 1.536MHz you either have a sample rate of 24kHz with 64 SCLK periods per frame, or more likely 48kHz with only 32 sclk's per frame. It seems the amplifier can accept this, so I'm not sure you really need a frequency doubler. It *should* have its own internal 24.576MHz clock running from a PLL.The amplifier looks quite impressive, I might pick one up to play with - has a number of advanced features!

author: dmendesf
author_rank: Frequent Contributor
timestamp: December 29, 2018, 09:34:01 pm
content: Look for 74hct9046. It's a newer version of 4046 with a few bugs ironed out. I've used it to generate > 15MHz signals, although the design equations don't work very well at this frequency and some trial and error is mandatory.

author: edavid
author_rank: Super Contributor
timestamp: December 29, 2018, 10:32:16 pm
content: Quote from: dmendesf on December 29, 2018, 09:34:01 pmOP is running his circuit at 3.3V, so the 74HCT9046 would not work. (Also, the improvements don't matter for his application.)

author: langwadt
author_rank: Super Contributor
timestamp: December 29, 2018, 11:05:05 pm
content: Quote from: Buriedcode on December 29, 2018, 04:58:54 pmI looked at the datasheet and is clear as mud on how the it should be clocked, but afaict it will mute the output if it isn't clockedjust right

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 30, 2018, 01:15:01 pm
content: Quote from: langwadt on December 29, 2018, 11:05:05 pmI have to disagree, I think mud is way clearer than the datasheet. In my case the Amp was giving me no sound and no error indications (by reading the I2C error register). After a month, TI eventually gave help on their e2e forum (after I'd reached out via my contacts in TI) but that was when it was revealed that what I needed was a MCLK at double the SCLK. Seriously TI, from a designer seeking help perspective, you may as well have moved to another planet - maybe you did?To save me some time (I'm on a cruise ship about 100 miles NE from Cape Horn and internet is a bit slow here), can anyone point me to a schematic for the 74HC4046A used with an external divider that will run at 3.3V?

author: Benta
author_rank: Super Contributor
timestamp: December 30, 2018, 04:57:59 pm
content: Quote from: Gandalf_Sr on December 30, 2018, 01:15:01 pmHere you go (written by a friend of mine):

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 30, 2018, 11:00:29 pm
content: Wow, thanksNow 'all' I have to do is remember how to do Laplace transforms.

author: Benta
author_rank: Super Contributor
timestamp: December 30, 2018, 11:28:56 pm
content: Quote from: Gandalf_Sr on December 30, 2018, 11:00:29 pmNot necessary, already done for you. Use the "practical example" section.However, you have a different task: with the relatively high frequency from the PFD, you'll need to find an opamp that:- has at least 25 MHz GBW- has rail-to-rail inputs and outputs- is unity-gain stable- will operate at 3.3 V

author: edavid
author_rank: Super Contributor
timestamp: December 31, 2018, 03:52:53 am
content: Quote from: Benta on December 30, 2018, 11:28:56 pmFor 2X multiplication of a constant frequency clock, you don't need (or want) a Type 2 loop. The XOR phase detector and a simple passive filter will work fine.

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: December 31, 2018, 09:50:23 am
content: The cost difference between an Op Amp and a D-Type flip flop is unimportant but the flip flop (say a 74HC174) has a 13 nS delay which is significant given the periodic time for the 3.072 MHz output is 325.5 nS. Maybe the Op Amp is the way to go? Or can I realize the divide by 2 using a faster logic family? Remember that my supply voltage is 3.3V.[Cruise update] Docked in Ushuaia with perfect weather - we went around Cape Horn yesterday in near millpond like conditions.

author: edavid
author_rank: Super Contributor
timestamp: December 31, 2018, 05:16:24 pm
content: Quote from: Gandalf_Sr on December 31, 2018, 09:50:23 amYou are mixing up 2 different red herrings:1. The op amp would be part of a PLL active loop filter, which you wouldn't need.2. The divider flip flop (74HC74, not 174) propagation delay would be removed by the action of the PLL. The offset between the two clocks is determined by the phase detector characteristics.

author: Benta
author_rank: Super Contributor
timestamp: December 31, 2018, 07:17:48 pm
content: I have to agree with edavid.The flipflop or divider delay in the PLL would rather advance the output of the VCO, so the VCO output will lead the input. This can easily be compensated, but still...The RC delay plus XOR is still the best solution for a simple constant frequency doubling IMO.

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: January 01, 2019, 11:05:34 am
content: Quote from: edavid on December 31, 2018, 05:16:24 pmIf the phase comparator compares the original 1.536 MHz clock input to the VCO output fed through a /2 flip fop that introduces a 13 nS delay then surely the output signal edges will lead the edges of the input signal by 13 nS?I agree that the XOR should work but it doesn't, at least not reliably. I have a thread running on this on TI's e2e forum - the question is why the TAS5755M doesn't like my slightly jittery and variable M/S ratio doubled MCLK, maybe they'll shed some light on this eventually? Perhaps the fact that the SCLK and associated signals come on before the MCLK does is something the Amp doesn't like?Thanks for the proactive input folks, and a Happy New Year to you all.

author: spec
author_rank: Frequent Contributor
timestamp: January 01, 2019, 11:44:45 am
content: Just a suggestion, but wouln't the SN74LV4046A PLL chip be worth considering. It is high performance and 3V3 compatible.http://www.ti.com/lit/ds/symlink/sn74lv4046a.pdf

author: spec
author_rank: Frequent Contributor
timestamp: January 01, 2019, 12:29:12 pm
content: (3MHz = 3.072 MHz and 1.5MHz = 1.536 MHz throughout)This is an intriguing thread, because the requirement is a lot more demanding than would first appear.The suggested solutions so far (hope I have this right) are:XOR with open loop mark to space ratio (MSR) definitionPLLTransformerI have been looking at other approaches as well:logic frequency doubling (similar to XOR above) with two analog servo control loops to provide an accurate 1:1 mark to space ratio of the 3MHz signal (LDAS)Digital Sampling Counter (DSC)The LDAS approach is reasonably self explanatory, so I will only describe the DSC approach:The inputs to the DSC are the 1.5 MHz reference signal, and a clock reference signal (CRS) of as high a frequency as the logic in use will take, say 100mHz, for the SN74LVxA family of logic chips running at a 3V3 supply line. The CRS absolute frequency is unimportant. The only requirement is that it is frequency stable for around 10uS and jitter free.A synchronous digital counter (DC1), clocked by CRS, counts the number of CRS periods in one cycle of the 1.5Mhz signal and loads 1/4 of the digital value into another synchronous digital counter (DC2) which is also clocked by CRS.The output of DC2 would then be a 3MHz signal with a 1:1 MSR, synced to the 1.5MHz reference signal.The only drift would be due to any drift of CRS over a 10uS period.Of course, if you really wanted to do a Rolls Royce job you could use ECL or PECL to get the sampling rate right up.The design of the DSC would be pretty straight forward for a digital designer and the physical the same. I recon the DSC could be implemented with four chips and possibly a 100mHz Xtal oscillator, but I haven't done a trial schematic.This is really thinking aloud but I would be interested to hear the general view of these two approaches, especially the DSC approach.

author: edavid
author_rank: Super Contributor
timestamp: January 01, 2019, 04:08:08 pm
content: Quote from: Gandalf_Sr on January 01, 2019, 11:05:34 amWe are talking about using an XOR phase detector for a PLL doubler, *not* about an XOR frequency doubler.

author: edavid
author_rank: Super Contributor
timestamp: January 01, 2019, 04:10:00 pm
content: Quote from: spec on January 01, 2019, 12:29:12 pmThis is more commonly called a Frequency Locked Loop. It has its applications, but for a fixed frequency multiplier it has more jitter than the simpler open loop or PLL approaches, so it's not a good idea.

author: spec
author_rank: Frequent Contributor
timestamp: January 02, 2019, 03:57:26 pm
content: Quote from: edavid on January 01, 2019, 04:10:00 pmYes, I was wondering about the jitter. Thanks for the info

author: Benta
author_rank: Super Contributor
timestamp: January 02, 2019, 04:04:10 pm
content: Quote from: edavid on January 01, 2019, 04:08:08 pmProblem is, that the simple XOR phase/frequency detector does not have phase coherence. It can be anywhere between -90 and +90 degrees.

author: edavid
author_rank: Super Contributor
timestamp: January 02, 2019, 04:23:18 pm
content: Quote from: Benta on January 02, 2019, 04:04:10 pmThat is not correct. A PLL with filtered XOR phase detector will always lock at 90 degrees phase difference.

author: Benta
author_rank: Super Contributor
timestamp: January 02, 2019, 04:36:51 pm
content: Quote from: edavid on January 02, 2019, 04:23:18 pmYour understanding is incorrect. A type 1 PLL (which an XOR PD is) has varying phase difference between the input signals, depending on which voltage the VCO needs. Otherwise it would not work as FM detector, for instance. I recommend that you invest in a Gardner ~100$).

author: nick_d
author_rank: Regular Contributor
timestamp: January 03, 2019, 01:01:47 am
content: Check specs on TAS5755M master clock, it is highly unlikely it would need a 50% duty cycle unless it's sampling the data on both clock edges. At around 10MHz with HC logic the 50% duty cycle becomes inportant to avoid pulses that are too narrow for the logic to handle, but this is unlikely to be a problem at 3MHz and at 3.3V you will be using more advanced logic anyway. So how I would handle this is the Schmitt XOR... you only need 1 gate, just put the undelayed 1.5MHz in one input and the RC delayed 1.5MHz in the other. The Schmitt wouldn't be needed with HC logic at MHz rates since by the time it had switched the input would be well past threshold preventing oscillation, but it might be beneficial with more advanced logic. If you are usng 1 gate packages get the Schmitt XOR. Otherwise if you have spare gates let us know and we may be able to see a way.cheers, Nick

author: Gandalf_Sr
author_rank: Super Contributor
timestamp: January 03, 2019, 12:23:22 pm
content: I ordered some parts from Digikey today so that I can try some of the approaches suggested here.Quantity Part Number Manufacturer Part Number Description10 296-17660-1-ND SN74AUP1G79DCKR IC FF D-TYPE SNGL 1BIT2 296-14856-1-ND SN74HC590ADWR IC 8BIT BINARY COUNTR 3ST10 296-27397-1-ND SN74AUP1T86DCKR IC GATE XOR SCHMITT 1CH10 296-21048-1-ND SN74LV4046ADGVR IC LOGIC PLL W/VCO10 712-1274-1-ND 500R07S220GV4T CAP CER 22PF 50V C0G/NP010 TC33X-103ECT-ND TC33X-2-103E TRIMMER 10K OHM 0.1W J LEADNot much money and they will all come in for experimentation - the Caps are 2% vs the 20% ones that I used before