Tools and Design Flows for DSP Algorithm Implementation in Xilinx FPGAs - Page 1
Forum section: electronics / general

author: MixedSignalSystems
author_rank: Contributor
timestamp: May 13, 2019, 03:06:38 pm
content: Hello,I'm looking for tools to reduce the time required to implement a given DSP algorithm in a Xilinx FPGA.I am comfortable implementing the design using HDLs such as Verilog or VHDL but I am interested in learning more about High-Level Synthesis (HLS) tools.For example, if an algorithm is designed and verified in MATLAB, what tools can be used to generate a synthesizable design block targeting Xilinx FPGAs?How sophisticated are these tools? Do they work well for real-world designs? For example, for a design with challenging timing constraints, can the HLS tool be directed to optimise for timing rather than area, implement parallel data paths, etc.Any recommendations for tools that I should look at?Many thanks,Kieran

author: whollender
author_rank: Regular Contributor
timestamp: May 13, 2019, 05:14:36 pm
content: Have you looked into System Generator?It's Xilinx's dedicated tool for MATLAB -> FPGA flows and it works very well.

author: MixedSignalSystems
author_rank: Contributor
timestamp: May 13, 2019, 06:04:38 pm
content: Thanks for the reply. Yes, I am familiar with System Generator.Many years ago, I worked as an Applications Engineer for Xilinx. I used to support SysGen for a while. The tools have come on leaps and bounds over the years.It's been a long time since I've done any algorithm implementations on a FPGA. I focus more on embedded system design. I'm just wondering if there are any 3rd party tools that an algorithm designer could use to specify a solution with reasonable confidence that the underlying implementation would be efficient (whatever that may mean for a given design).I want to broaden my horizons. I suspect that my knowledge in this area is quite out of date.For example, being able to use C to implement a FIR filter and have it implemented using the dedicated DSP48 blocks available in modern Xilinx FPGAs.Back when I was looking at this kind of thing regularly (over a decade ago), the "C to hardware" style tools were notoriously poor at producing sensible designs for anything but the simplest of cases. I assume that the situation is a lot better now.With a microcontroller, e.g. STM32, most of the time most people will use C rather than assembly without giving it a second thought. I'm not sure that the same can be said for "C to hardware" but I am willing/hoping to be proven wrong.

author: mark03
author_rank: Frequent Contributor
timestamp: May 13, 2019, 06:30:09 pm
content: I'm only just starting out, but AFAICT, you should count yourself lucky, because your current interest lines up very nicely with Xilinx/Altera's marketing focus: Virtually all of their educational resources / app notes / etc. seem geared towards this. What's *not* easy is learning the stuff you already have in your head... basic HDL implementation of DSP algorithms. (A trivial example would be all of the different ways to implement a FIR filter, from full systolic (?) at one extreme, to single-multiplier at the other.) All I have found from Xilinx/Altera are really old app notes, and I'm still looking for a good book on the topic.

author: whollender
author_rank: Regular Contributor
timestamp: May 13, 2019, 06:41:14 pm
content: MATLAB has their own HDL generator toolbox as well. I would imagine that the HDL it generates would automatically map to DSP blocks, but you would have to play with it to find out.Vivado's HLS tools are pretty advanced now for C->HDL flows. I did a training on Vivado HLS a year or so ago, but haven't really had a chance to play with it much.It looks like there are a lot of 3rd party tools as well (https://en.wikipedia.org/wiki/High-level_synthesis), but I'm sure the quality varies quite a bit.I don't think any of the tools are quite to the point of feeding it C and not giving it a second thought. My take from the training is that you have to use carefully crafted C to get an efficient implementation, but that may have changed now.