using voltage translator to isolate ADC from digital circuitry - Page 1
Forum section: electronics / beginners

author: V_King
author_rank: Regular Contributor
timestamp: October 25, 2016, 12:17:49 pm
content: Hello,I am planning of using AD7606-4 ADC for 4channel simultaneous sampling. In my previous project I was running into noise issues from the digital circuits, even though I had analog ground plane separated.This time I am doing a separate LDO for ADC side, following all AD layout guidelines and was looking into analog deviced ADUM isolators and other familiar ones to isolate the digital lines from microcontroller. But all of them come with max of 6 channels and are quire expensive. So for 22 digital lines I would need a lot of PCB space and complexity. And I do not want to use optical isolators.But when I had a look at analog devices AD7606 evaluation board, I found a SN74LVCH16T245 voltage level translator between their analog end and MCU. An idea popped into my mind. Can I use a voltage level translator for analog and digital side isolation? TI has up to 32 channel lever translators, with separate Vin on both sides, supporting the same voltage levels (my system is currently at 5V). The TI SN74LVCH16T245 has even ESD protection.Any other recommendations are welcome regarding uC and ADC isolation.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 25, 2016, 12:41:30 pm
content: The voltage translator does not provide insulation for the ground. The main advantage would be on power up: so a different rate for power up would be a big problem. Also different supply voltages would work. So it will not provide much protection from EMI.If you don't need a high datarate, one could get away with using only the serial interface. So no D0-D15 and this much less lines. A few of the signal may not need to be connected to the µC (e.g. chose reference).For a fast running system one has to take care of the ADC - insulator interface anyway. This may not be so much easier than going to the µC directly. SO you need to look at a clean interface anyway. Per se an µC does not have to produce much noise - it's often the parts connected and a not so good layout.

author: Neilm
author_rank: Super Contributor
timestamp: October 25, 2016, 06:19:32 pm
content: Quote from: V_King on October 25, 2016, 12:17:49 pmDon't have separate 0V - just look at the current flows and keep digital in one area and analogue in another. Almost every time I have see separate 0V there is noise issues - those exceptions are where the designer has taken care and spent a lot of time chasing how the current is flowing through every device involved.Some years ago, I had to re-work instruments as the EMC regulations had changed. My solution in every case was to combine the separate 0Vs unless there were safety isolation issues. The result was that most of the instruments passed with no other changes and on several of them I fixed other issues.The trouble with some chip manufactures is that they developed good techniques 20 years ago, and while the technology has changed, they keep trotting out those old fashioned techniques.

author: lukier
author_rank: Unknown
timestamp: October 25, 2016, 06:51:25 pm
content: Quote from: Neilm on October 25, 2016, 06:19:32 pmThanks for the tip. I too read often about separate analog and digital grounds. With 2 layer boards and similar analyzing current flows might be doable, separate GND lines to each section and mecca point, right? Some parts make this easier, for example ADS1265 ADC has separate AGND and DGND pins, so I would assume the current from the digital interface returns on the DGND and the analog parts on the AGND. But what about, let's say AD5689 DAC, only one GND pin - where it should return?Similarly, what about ground planes (let's assume 4 layer PCB). Just straight via from each (A/D)GND pin to the plane and let's hope the currents will find their way?As an analog noob I'm quite curious to know how to properly solve such problems in precision circuits.When I do some power electronics I find it easier to grasp, as the mecca point (at the power supply) approach is more intuitive when one has one thick conductor for 24V 10A return from the motor let's say, and an IDC cable carrying 5V and its GND for the MOSFET driver. Problems might still appear (e.g. if thick cable disconnects and 10A wants to go back over IDC) hence such power electronics is often optoisolated.

author: Neilm
author_rank: Super Contributor
timestamp: October 26, 2016, 06:31:40 pm
content: On 2 layer boards, it was a reasonable way of controlling noise as the designer would know exactly where the currents would flow - he had a track with 0V on it.Quote from: lukier on October 25, 2016, 06:51:25 pmA via directly to the 0V plane as close to the pin as possible. When there are 0V planes, the return currents will take the path of least impedance, mostly directly under the track with the signal.Quote from: lukier on October 25, 2016, 06:51:25 pmWhen you are talking about signals down long wires it gets more complex. The wires contribute impedance to the signals, so it adds another impedance to consider. Signals will get optoisolated not only for noise issues but for safety isolation as well.To minimise noise on multi-layer board with a solid 0V plane try to visualize where the currents are going to flow. This means you will end up partitioning the PCB in to almost discrete areas. One of these areas would be for digital circuits and one for analogue circuits. Then put the ADC between them. With careful layout a board with a single solid 0V plane will happily measure very small signals with little or no noise.

author: V_King
author_rank: Regular Contributor
timestamp: October 28, 2016, 08:42:25 am
content: Thanks for all the info Neil. I am trying to layout the board following the analog devices evaluation board layout and their general advice on board layout for ADC circuits. They also separate parts of PCB into analog and digital parts.My concern is with having a v-reg for analog side and v-reg for digital side. Both sides would be not just connected through grounds going to AC-DC converter, but through adc<>uC digital interface lines. And current will be flowing back and forth between adc and uC as some will be low, some will pulled low, some will be pulled high hence thinking of isolating two sides. Or am I thinking too deep?Will probably try doing the board with general recommendations, and fingers crossed everything will be fine.

author: dmills
author_rank: Super Contributor
timestamp: October 28, 2016, 02:07:37 pm
content: I concur that you should be starting with a common ground plane, it is almost always the smart move.ADCs have Agnd and Dgnd pins NOT because they expect you to connect them to different planes, but in order to separate the currents in the bond wire within the package to avoid common impedance coupling (I **REALLY** wish that folks would understand this little detail, it would stop so much pain).Tie AGnd and Dgnd down to the plane with a vias as close to the pin as possible.Separate power supplies are not a horrible thing, and as long as the sequencing is reasonable they do work, but remember that most LDOs have very poor PSRR above a few hundred KHz (There are exceptions), lossy ferrite and a ceramic cap will often help here.Another thing that helps is source terminating lines that do not need to be screamingly fast, a 100 ohms in series right by the driver pin will reduce the peak currents a huge amount.73 Dan.

author: danadak
author_rank: Super Contributor
timestamp: October 28, 2016, 11:15:56 pm
content: Some useful PCB layout guides -https://www.dropbox.com/s/ruaf9booe17jk8n/PCB%20Layout.zip?dl=0Regards, Dana.