I2C - is it bad to have a slow SCL rise time? - Page 1
Forum section: electronics / beginners

author: Saimoun
author_rank: Frequent Contributor
timestamp: October 06, 2021, 08:03:51 am
content: HiI've got this I2C bus between my uC and two devices, running at 50kHz.I measured the ICL rise time (from 0.3Vcc to 0.7Vcc) of about 600ns. But that is including the capacitance of the probes, so I'm thinking the real rise time is a little lower.One of the device (an EEPROM) says max 300ns rise and fall time.Everything seems to work perfectly fine - but is this something I should look into or is the "max rise time" spec of the devices only important when running at high speed?Thank youSimon

author: iMo
author_rank: Super Contributor
timestamp: October 06, 2021, 08:44:59 am
content: What are your I2C pull-up resistors??

author: tszaboo
author_rank: Super Contributor
timestamp: October 06, 2021, 08:56:30 am
content: 600ns isn't slow it is OK, for a bus which is supposed to work at 400 KBAUD.If you can, decrease the value of the pullup resistor. Check if the EEPROM can do 3 MHz I2C, which is called fast mode plus, or superspeed or hyperspeed or whatever. Maybe the rise time is because of that.

author: AndyC_772
author_rank: Super Contributor
timestamp: October 06, 2021, 08:59:22 am
content: The only reason it would be bad, is if:- it's noisy,- it spends significant time around the transition region from 0 to 1, and- the receiving device does not have inputs with hysteresis, so it sees multiple transitions as the noise takes the signal between logic 0 and 1 levels multiple timesI2C devices usually have Schmitt trigger inputs which include hysteresis, so it's not a problem. However, if a device's data sheet specifies a max rise time, it's a good idea to meet this spec.The rise time, and issues that a slow rise time might cause, has nothing whatsoever to do with the bus speed (ie. number of edges / sec).

author: PeteH
author_rank: Unknown
timestamp: October 06, 2021, 10:29:18 am
content: Typically the MAX rise time is spec'd for reliable operation near the high end of the speed range of the device.... I.e. fast mode, 1kHz to 400kHz... Max of 300ns makes sense.If you run nowhere near 400kHz, you can derate the rise time in proportion.Other thing is ultra low power design, you may not want to have very slow transitions (even with Schmitt's) but 600ns sounds perfectly fine....

author: Saimoun
author_rank: Frequent Contributor
timestamp: October 06, 2021, 02:06:48 pm
content: Thank you all for the replies!!Your answers make me think I might have misunderstood the datasheet - looking at this one for example:https://www.st.com/resource/en/datasheet/m24c02-f.pdfPage 21 (attached) it says max 50ns SCL input rise/fall time. Is that a requirement or is that the specs of how fast the IC can move SCL and SDA? If it is the latter, then it does not make sense since this is only a slave and will therefore never move the SCL line...?

author: Saimoun
author_rank: Frequent Contributor
timestamp: October 06, 2021, 02:11:22 pm
content: As for the device I am actually using, it is basically an equivalent from Shanghai Belling, and the datasheet is not the best:https://datasheet.lcsc.com/lcsc/2003172239_BL-Shanghai-Belling-BL24C02F-RRRC_C498263.pdfIt does say "Input Rise Time" and "Input Fall Time" at max 0.3us (see attached screenshot).

author: harerod
author_rank: Frequent Contributor
timestamp: October 06, 2021, 06:08:14 pm
content: A great opportunity to have a look at the actual I2C specification:https://www.nxp.com/docs/en/user-guide/UM10204.pdfYour device seems to implement and specify the "fast mode" alone. Incidentally, that datasheet is not too different from the Microchip AT24C256's.

author: mikerj
author_rank: Super Contributor
timestamp: October 06, 2021, 06:33:56 pm
content: Quote from: simonlasnier on October 06, 2021, 02:06:48 pmThose are the measurementconditionsi.e. the state under which the values in the performance characteristics are valid.The actual performance characteristics are in tables 15 (400kHz) and 16 (100kHz) in the M24C02 datasheet. The parameter of interest for you is tXH1XH2which has a maximum value of 1us for 100kHz operation.

author: iMo
author_rank: Super Contributor
timestamp: October 06, 2021, 08:06:17 pm
content: Quote from: imo on October 06, 2021, 08:44:59 amTell us the value of your I2C pullup resistors..

author: radiolistener
author_rank: Super Contributor
timestamp: October 06, 2021, 08:21:45 pm
content: rise time requirements are intended to guarantee specific communication speed. Slow rise time leads to a lower communication speed limit. But on the other hand, the fast rise time makes your circuit more sensitive to a high frequency noise and interferences from other equipment. So, the slow rise time is a good for protection from noise and interferences, but it is bad for a high speed communication. And vice versa.The actual rise time will depends on transmission line properties. If you have no errors at max required communication speed, then rise time is fast enough for your needs.You can try to slow down rise time for a little with capacitor and check if communication is still ok. If it still has no error then your rise time is good enough and has some reserve margin.

author: Saimoun
author_rank: Frequent Contributor
timestamp: October 07, 2021, 07:07:57 am
content: Thank you all again for the replies - I think I have a much better understanding of it now.@mikerj: thank you! Gosh I don't know how I missed that ha haMakes much better sense now.@imo: the pullup are weak internal pullups in one of the I2C slave ICs (value is not mentioned).There are no capacitors on the bus lines, so I would estimate bus capacitance C=15pF. So by measuring tau=RC=750ns (63% of the rise time) , I get R=50k, which also fits what you would expect from a "weak pullup".Now before everybody starts bashing me, let me explain my trail of thoughts: I really do not need fast speed, and I would rather be on the safe side of EMC.I heard 4.7k external pullup is standard'ish, but also that one should add a 100pF capacitor to "slow it down". That would give tau=RC=470ns.So I thought why not saving PCB traces, space, and two resistors and two capacitors by simply using the weak internal pullups? This would give the same result anyways, and lower currentsNow you may bash - I'm ready

author: iMo
author_rank: Super Contributor
timestamp: October 07, 2021, 08:04:15 am
content: Quote from: simonlasnier on October 07, 2021, 07:07:57 amAnd that is the answer to your original question: why the edges are so slowish..I2C bus resistors are typically set from 1k to 10k based on the required speed. The faster you want go (and/or the more devices hanging on the bus) the lower values should be the pullups. The I2C bus works with "open collectors/drains" where the bus has to be terminated with the pullups otherwise it will not work - the "chip's output" only pulls down the line to log0, the logic one is created by pulling up the line via the resistor to Vcc (and the bus capacitances and the pullups create the RC you see). It means you have not wired those pullups yet and your stuff works by chance..

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 07, 2021, 09:31:54 pm
content: 600ns slow? For a simple pullup resistor driven bus?That's almost 2MHz, quite fast indeed.Also I don't think you need to measure the complete rise time, but to the min. Specified high level threshold, over that, it does nothing.For 20pf and 10K you get 2RC of 400ns, so it's pretty close.I say 2RC because it's pretty enough, already 90% of VDD.Lower the pullup to 4k7 or 2k2, will lower the rise times a lot.However, the falling times should be much faster, as it's actively pulled down.