Coaxial crimping tool  [Solved] - Page 1
Forum section: electronics / rf-microwave

author: rhb
author_rank: Super Contributor
timestamp: March 29, 2019, 11:19:01 pm
content: I'm trying to find a decent quality, affordable crimping tool for crimping SMA, BNC and N connectors on RG8, RG58 and RG402 and other SMA size cables.I did a search with google of eevblog.com and generally without learning anything. RG8 and RG58 crimpers don't seem to be a problem, but crimpers for RG402 and smaller have been impossible to find.Edit:I just received these:https://www.ebay.com/itm/Coax-Crimp-Tool-for-RG179-RG174-RG316-Wires-SMA-SMB-MCX-TNC-SMC-Connectors/272305772500https://www.ebay.com/itm/Coax-Crimp-Tool-for-RG179-RG174-RG316-Wires-SMA-SMB-MCX-TNC-SMC-Connectors/272305772500The fit and finish is very nice and the die dimensions are spot on using drill bits as go/no-go gauges.

author: chris_leyson
author_rank: Super Contributor
timestamp: March 29, 2019, 11:55:50 pm
content: Must admit I gave up looking for a crimp tools for RG402 and RG405, ended up buying solder connectors.

author: rhb
author_rank: Super Contributor
timestamp: March 30, 2019, 01:24:49 am
content: Looks as if I may be making custom tips for my resistance soldering tweezers if it will provide enough current. Otherwise building a bespoke version if it doesn't have the current capacity is not a huge issue.Small amounts of dielectric melting will cause all manner of annoyance.I want to measure timing delays for various DSP filter topologies in an FPGA. Buying 16 phase adjusters from Bracke for $140 each is just too expensive. I can buy a Sherline lathe and make them for less if I don't bill for my labor.

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: March 30, 2019, 02:23:48 pm
content: The gold standard for RF crimpers is the DMC HX4, with inter-changable dies for various flexible coax types. They're not cheap ($400), so if you want affordable, maybe look on ebay. RG402/405 in crimpable form is somewhat rare, like @chris_leyson I use the soldered kind. You can also get inexpensive RG402/405 jumper cables from Mini-circuits or a number of smaller outfits (I like Cross RF).

author: OwO
author_rank: Super Contributor
timestamp: March 30, 2019, 02:31:15 pm
content: Quote from: rhb on March 30, 2019, 01:24:49 amAre you sure this isn't a job for the timing analyzer in Vivado/Quartus?

author: rhb
author_rank: Super Contributor
timestamp: March 30, 2019, 03:35:00 pm
content: Quote from: OwO on March 30, 2019, 02:31:15 pmAnd how would I tell if the output of the timing analyzer was wrong?

author: OwO
author_rank: Super Contributor
timestamp: March 30, 2019, 03:44:35 pm
content: Quote from: rhb on March 30, 2019, 03:35:00 pmTiming analyzer is never wrong provided your FPGA is up to spec, but that's irrelevant because DSP designs are generally synchronous and pipelined, meaning the delay is a statically known quantity measured in clock cycles and can be seen from simulations. If the design isn't actually meeting timing you won't be able to measure that either, you will simply see wrong values. The other thing to note is you are supposed to use additional register stages at the IOs because the IOBs are physically far away from user fabric in an FPGA and only with registers at the IOBs will you get reasonable performance. This also means any "timing" you see at the IOs are simply the characteristics of the IOB and have nothing to do with your design.This is the kind of shit they don't tell you in books and classes.

author: OwO
author_rank: Super Contributor
timestamp: March 30, 2019, 03:46:34 pm
content: I would recommend starting a new topic about your DSP filter experimentation project and posting more details so people can help you with the problem directly and avoid going down a rabbithole then realizing you were chasing the wrong problem the entire time.

author: rhb
author_rank: Super Contributor
timestamp: March 30, 2019, 07:48:36 pm
content: I just want to find a crimping tool so I can make cables which are as precisely the same length as possible. I'd like them to be no more than 1 ps difference in electrical length. Soldering has the potential of melting the dielectric, so for the level of precision I want crimping is more attractive.I'm sorry I mentioned what the cables were for. I am not interested in discussing that.Edit: It appears that RG402/U is solder only.

author: radiolistener
author_rank: Super Contributor
timestamp: March 30, 2019, 08:25:34 pm
content: I think soldering connectors will be better - smaller loss and more reliable

author: OwO
author_rank: Super Contributor
timestamp: March 31, 2019, 04:13:56 am
content: Quote from: rhb on March 30, 2019, 07:48:36 pm1ps is ~0.2mm in teflon coax and ~0.17mm on PCB. I don't think what you are suggesting is feasible to achieve without tuning or calibration (which again requires expensive adjustable delay lines).I was trying to help you avoid wasting time doing something that very likely won't do what you are trying to achieve, even if you manage to get 1ps matching of cables (this is the polite version). In your other posts you mentioned you have several FPGA dev boards, so I recommend actually playing with various designs, look at the physical layout of the implemented design in Vivado, play with the timing analyzer, then come back and revisit this problem.Actually I'll just spoil it for you: logic delays are going to be a tiny fraction of total delay and routing delay to/from the pins will dominate.

author: rhb
author_rank: Super Contributor
timestamp: March 31, 2019, 01:17:12 pm
content: I know you mean well, but I get a barrage of well meaning, but incorrect advice.The attachment is from "VLSI DSP Systems" by K.K. Parhi which I bought and am reading because it was highly recommended in "FPGA based implementations of Digital Signal Processing" by Wood et al. I was already aware of the issues mentioned in the attachment. This is why I bought the book.I'm a retired PhD level research scientist with 37 years of DSP experience and a 5000+ volume personal technical library. So I am accustomed to doing very difficult things I've never done before. And a long track record of successfully doing what some of my peers insisted could not be done. I also don't care what other people think.If I cannot make the measurements I want, the sole reason will be that Vivado & Quartus don't allow me to configure the chip the way I want. The most treacherous part of making the cables to length will be the 0.1" PMOD header connection. But a 20 GHz, SD-24 TDR head in my Tek 11801 should solve that. I fully expect that if I breathe on the test fixture for making the SMA-M to PMOD connector things will change.If it turns out I need phase adjusters I shall buy a Sherline lathe and make them. It's cheaper and I get a free lathe at the end. The delays I'm concerned with are of the order of a 1-2 ns, So long as the two cables connected to a head are close enough, I can adjust the phase of the head electronically.

author: Bud
author_rank: Super Contributor
timestamp: March 31, 2019, 01:37:38 pm
content: @rhbLook man, in every other your post you tell how genius you are. We get it, c'mon man, stop it, it is getting ridiculous.

author: chris_leyson
author_rank: Super Contributor
timestamp: March 31, 2019, 02:36:21 pm
content: Anvil AV-CRMPE and AV-CRMPE5 are not too expensive. CRMPE5 will do for smaller cable sizes but to honest most SMA connectors for semi-rigid RG405/RG402 from Amphenol and Radiall are solder rather than crimp.https://www.rapidonline.com/Catalogue/Product/85-0218https://www.rapidonline.com/Catalogue/Product/85-0222

author: OwO
author_rank: Super Contributor
timestamp: March 31, 2019, 02:40:32 pm
content: OK, I see what you are trying to do:QuoteThere is nothing wrong with this idea, but applying it in an FPGA has 3 main problems:1. The LUTs are only characterized by single "delay" parameter, meaning outputs are assumed to become invalid as soon as inputs change. This means you have to re-characterize the LUTs and the routing yourself. The latter part I'm inclined to believe is impossible because neither Xilinx nor Altera publish any information about the specific routing resources available or allow you to constrain a net to a specific wire. If it's possible at all it's a major undertaking.2. Flipflops are basically "free" in an FPGA because every LUT output is followed by a FF. You might as well use it.3. The shrinking of the "data valid" window that is inherent in wave pipelining. Each LUT that your data passes through will add its own "transition window" which is the time from when previous data is invalidated to new data becoming valid. After a few logic levels the data "eye" closes and data is never valid.I think this idea might be something worth playing with but personally I'll stick with synchronous logic, at least on an FPGA.Quote from: rhb on March 31, 2019, 01:17:12 pmOK, I'll be awaiting your reverse engineering and characterization of an entire modern FPGA

author: rhb
author_rank: Super Contributor
timestamp: March 31, 2019, 03:29:21 pm
content: I have never had an intention of using anything but synchronous logic. But the speed at which I can clock the filters is very dependent on the skew in the multiplier and adder topology chosen. So I want to verify just how fast I can clock each topology.I'll use the simulator and start with what it says is the fastest. I just want to verify that it is correct and which lines are fastest and slowest. I might be able to avoid a retiming register if I can identify a pair of topologies with complementary skews.It was a very crappy setup, but I measured the 2 way delay of ~1 mm of extra wire in air at 2.1 ps. A significant error, but I need a shorter cable so I can expand the timescale as I was at 340 ps/div to be able to the start and end of the reflection. Ultimately the jitter of the 11801 will limit my accuracy to probably no better than 3-4 ps. But that is good enough for the task.I've been setting up for this effort for over a year and have spent about $2k for HW and almost $1k for books. That's just for the FOSS DSO FW project. I've spent quite a bit more setting up my lab space.Making the fixture to connect the 11801 to the PMOD port is going to be more challenging than I thought. Cable capacitance really kills the rise time quickly. Fortunately I'm dealing with clock periods of 1 ns or longer. But it appears I'll need to mount the dev board on a small shelf clamped to the sampling heads.

author: OwO
author_rank: Super Contributor
timestamp: March 31, 2019, 03:51:24 pm
content: Quote from: rhb on March 31, 2019, 03:29:21 pmIn that case why not just let the timing analyzer do its thing? All you need to do is input the period of your clocks and Vivado will tell you whether your design meets timing or not. If you don't trust the timing analyzer or characterization then the far more practical way to verify is by actually verifying the output data and comparing against a software implementation or known good outputs.

author: rhb
author_rank: Super Contributor
timestamp: March 31, 2019, 04:11:36 pm
content: Parhi's book is ~750 pages. I read it for a reason. I want to go as fast as the chip will go. I'll actually implement and test the topologies he discusses when I read it the 2nd time. This may be a hobby project, but it is a full on PhD level professional effort. I can't get work in the oil industry and I have to do something to keep my sanity. This is it.When I was writing a seismic imaging program 20 years ago I was counting clock cycles and paying very close attention to the cache organization. As well as testing a slew of different ways of coding the inner loop and how their performance was affected by the various optimization flags for the compiler. And every node in the cluster had two NICs. One for reading data and one for writing data so that I could stream data as fast as possible to the compute nodes.Over 30 years ago I tuned a MicroVAX II to run at 100% CPU utilization for weeks with a pair of batch queues and seem as if it were an idle system to an interactive user. I read the fine print and know how to exploit it.

author: tomato
author_rank: Regular Contributor
timestamp: March 31, 2019, 04:20:59 pm
content: Quote from: Bud on March 31, 2019, 01:37:38 pmEveryone has to drink a shot every time he does it.

author: rhb
author_rank: Super Contributor
timestamp: March 31, 2019, 05:53:54 pm
content: @Bud and @tomatoNeither of you were involved in this discussion previously. I made the statements to @Owo to explain that I am not some naive 20 something. I started the thread because I was aware that 1 ps is ~ 0.2 mm of PTFE coax. The problem posed by dielectric movement while soldering was the motivation for seeking a crimping tool for the task.On investigation, it turns out that the only means of terminating RG402 is solder connectors. For that you need a heat sink/fixture that prevents the dielectric from moving during soldering.As you find my posts objectionable, may I suggest that you not read them?

author: tomato
author_rank: Regular Contributor
timestamp: March 31, 2019, 06:17:06 pm
content: You need a sense of humor.

author: OwO
author_rank: Super Contributor
timestamp: April 01, 2019, 04:18:27 am
content: My experience with Xilinx 7 series FPGAs is that if your design is well optimized you can easily reach the Fmax of the block ram (if you are using block ram) or multipliers. That is the brick wall of how fast a DSP design can run (unless you want to overclock). Beyond that your best bet is parallelizing the design (take multiple samples per clock cycle).Measuring the delay of the multipliers will not do any good because the only way to reach the rated Fmax is to enable every single integral register in the DSP slice itself (read the DSP48E1 user guide). Once you do that the Fmax of the multiplier is simply a characteristic of the DSP block and have nothing to do with your design, and Xilinx has already characterized it very well. If you think you can clock the multiplier faster then what you are saying is Xilinx under-rated their DSP blocks, which I seriously doubt.EDIT: actually I don't doubt that the multipliers can run at higher than rated clock rates, but then you are just removing margin for process, temperature, and voltage variations. It may work on one sample but not another one. I think it's best to stick with the official characterizations and timing tools so that your design is guaranteed to work.

author: rhb
author_rank: Super Contributor
timestamp: April 01, 2019, 04:29:42 am
content: FWIWAccording to my 11801 & SD-22 sampling head, I filed 500 fs off the end of a piece of solid wall RG402 with about 3 strokes of the file. I'll actually believe it when I am in a position to make precise changes in length on a lathe.But I made before and after measurements twice with the same result each time. It will require a very carefully made fixture, but 0.008" is not that difficult a tolerance to hold.I suspect that the FPGA board timing to a PMOD connector is not that close.

author: rhb
author_rank: Super Contributor
timestamp: April 01, 2019, 05:19:37 am
content: Parhi enumerates a wide variety of ways to speed up DSP operations, reduce the power consumption and reduce area. Usually pick one, sometimes two. Most of these should be applicable to FPGAs. Some are clearly not as they involve changes that would probably not be possible with the DSP48E1. But the pipeline and parallel topologies do apply. I bought Parhi because Woods et al referenced it so much.I have no intention of going outside the vendor recommendations. I'm simply trying to learn how to use FPGAs for DSP operations.I ordered crimpers and SMA connectors. My first effort will be to meet my ridiculous length matching spec. That will *not* be easy and I certainly won't be surprised if I fail. But I think if I have an SMA-F mounted at one end of a fixture, torque the RG316 cable connector to spec, apply a fixed tension to the cable using a weight and force the dielectric and wire into an IDC header that it should be sufficiently repeatable.This is really driven by buying a new toy that absolutely blows my mind. I have barely learned how to use the 11801 and I can measure 500 fs changes in electrical length? Wow!When I bought my Clausing lathe I set about to make a test bar. This is a steel bar about 18" long with a series of collars every 1-2" which are turned to the same diameter to within 0.0001". That is seriously hard to do. The heat produced by making even a very light cut expands the bar to the point that the result is undersize when it cools down. I still have the bar and plan a rematch once I have a flood cooling system setup for the lathe. That will help, but still won't make it easy.If you want to see really over the top crazy, check out this guy:https://www.craftsmanshipmuseum.com/Kieffer3.htmHe made 1/4" - 20 bolts to 1/30th scale. Scale was 0.010" diameter!!! That's the diameter of the treble E string in a set of light gauge guitar strings.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: April 01, 2019, 06:14:08 am
content: Seeing as at work we pay literal thousands of euros/dollars or more to get pico-second matched phase-stable cables, I don't think what you want is really possible by hand, unless you make hundreds and just measure them and find the few closest ones. In fact, I think that with RG316 and RG405 etc, unless you have runs of a few millimeters, it is not unlikely that the uncertainty on your phase as a result of bending and so on will be far greater than a picosecond (after all, that is why we need cables that cost thousands of euros a piece and are phase stable in the first place).I might not fully understand your application here, but if you have a way to measure the phase of a cable to a few hundred femtoseconds anyways, why don't you just measure your cables and de-embed the difference in your measurements?

author: OwO
author_rank: Super Contributor
timestamp: April 01, 2019, 06:20:09 am
content: Quote from: rhb on April 01, 2019, 05:19:37 amOK, then measuring delays is the last thing you want to do, especially since the timing analyzer will give you everything you need to know.The only legitimate case for doing any measurements at FPGA IOs is when dealing with high speed I/O interfaces (gigabit transceivers). In that case you are more interested in signal integrity and would be looking at waveforms using a 10GHz oscilloscope and not measuring delays. You absolutely can not tell anything about user logic in the FPGA looking at timings at the IO pins.

author: rhb
author_rank: Super Contributor
timestamp: April 01, 2019, 01:26:50 pm
content: I'm using a 30 year old touch screen sampling scope with FW which is *worse* than the worst Chinese low end scope both in UI design and implementation. It's a testimony to the fall of Tektronix. But for an outlay of under $1500 I should be able to measure the skew on 8 channels to within 3-5 ps with careful work. That's more than sufficient for my purposes.I want to understand FPGA based DSP operations applicable to a COTS DSO. I'd originally just planned to blunder along blindly with Vivado and Quartus. But I bought a square wave and a 100 ps pulse generator from Leo Bodnar. They came accompanied by a plot from a CSA803 showing the waveform of my units. Before long I was looking for one on eBay. I managed to get an 11801 for $185 delivered and a pair of SD-22 heads for another $150 delivered. I've got four 20 GHz SD-26 heads waiting for me at the PO.Unfortunately, the concept that someone would go to a considerable amount of expense and effort to learn something purely for the sake of learning something seems to have almost completely disappeared. Jerry Kieffer didn't build that Corliss engine to have a model Corliss engine. He built it to learn to machine metal.Prior to Thomas Edison, scientific and mathematical research was almost entirely the province of gentlemen of means and abundant curiosity, with a small admixture of people like George Green. I am merely following that tradition because it pleases me. I have nothing further to say on the matter.