High side drive transformer saturation - Page 1
Forum section: electronics / general

author: Faringdon
author_rank: Super Contributor
timestamp: April 21, 2022, 11:54:37 pm
content: When you drive the high side fet in a half bridge LLC converter from a pulse transformer…..you must do it like in the attached….otherwise you stand a chance of saturation due to non-zero average core flux…….why is this never spoken of in any document?(LTspice sim and jpeg attached)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 22, 2022, 12:13:06 am
content: I don't get it, why use a transformer at all if it's already powered (by another transformer)? Opto or digital isolator is cheaper and DC coupled.Or if sticking with transformers, a much smaller part can be used, like Ethernet transformers almost, though you'll need a receiver (comparator + hysteresis?) as the signal level is low (fractional volt, for a reasonable 10s kHz bandwidth). Don't know of any gate drivers like that offhand, so it'd just be more work than using a generic pulse transformer (i.e., one with higher flux).All that's needed to run a generic pulse transformer, is AC coupling on the primary side and DC restore on the secondary side (i.e., a coupling cap into a clamp diode to set consistent negative pulse level).Tim

author: uer166
author_rank: Super Contributor
timestamp: April 22, 2022, 02:44:10 am
content: DC restore is definitely talked about to avoid that issue, the volt-seconds should be 0 on average.https://www.ti.com/lit/ml/slua618a/slua618a.pdf?ts=1650547667760.In your case, you already have a gate driver, it's better to use some digital isolator. A transformer makes more sense as a direct drive since it's a cheap/basic way to isolate.If you want to use a pulse transformer with a latching circuit on the other end, maybe look athttps://www.ti.com/lit/ug/tidu804/tidu804.pdf?ts=1650595345178, but that kind of circuit relies on the edges to change state, so can be tricky to implement, and sensitive to transient noise latching the output the wrong way.

author: Faringdon
author_rank: Super Contributor
timestamp: April 22, 2022, 09:05:07 am
content: QuoteThanks, as you know, there are serious problems with using a series cap on the secondary of the pulse transformer, as it can hold the fet on if the duty cycle suddenly goes to zero from the driver. It can also result in the fet being held on for several switching cycles at start-up......i have an LTspice sim of this very thing if you want me to send it?....in fact, ive now attached the LTspice sim showing the problem with pulse transformers with series cap in the sec side...QuoteDigital isolators and bootstrap drivers have the problem as described on page 16 of this...https://www.onsemi.com/pdf/datasheet/ncp5106-d.pdfAlso, even if you use a "no latch up" bootstrap driver, the logic inside the chip stops working if the vs pin rings 11v below the ground pin...as the following page states...https://www.infineon.com/cms/en/product/power/gate-driver-ics/2ed2101s06f/The attached Ray Ridley doc tells of the problems with bootstrap high side fet drivers (and by implication, the problems with digital isolators too, for the same purpose) ...they are not to be used in offline high power circuits.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 22, 2022, 09:50:32 am
content: In what way is a digital isolator identical to a bootstrap gate driver??Tim

author: Faringdon
author_rank: Super Contributor
timestamp: April 22, 2022, 09:57:51 am
content: Quote...in that you have a GND pin on the low voltage "side" of the digital isolator....and the other "side" of it is "grounded" to the switching node...the switching node can ring well below that low-side ground....and thus mess up the digital isolator....as discussed in that page 16 above (NCP5106 doc)....I mean, maybe you can alleviate the problem by putting a high value resistor (and diode) into the "high side ground" pin of the digital isolator....(like the fix given in the NCP5106 doc)...but there's no gaurantee that its really going to totally stop problems.I am just wondering if the 1EDI20N12AF is the solution to this problem?https://www.infineon.com/dgdl/Infineon-1EDI20N12AF-DS-v02_00-EN.pdf?fileId=5546d4614755559a014790299add6112...just being a "core-less" gate drive transformer itself, maybe it doesnt suffer at all from the negative voltage spiking at the bridge switching node?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 23, 2022, 12:08:07 am
content: What part of "isolator" are you missing, there's no physical connection between sides?Huh, never even realized Infineon had a line of magnetic isolators. Oh I see, originally by eupec, and always priced well out of consideration.So yes, that is... _a_ solution.Tim

author: Faringdon
author_rank: Super Contributor
timestamp: April 23, 2022, 08:48:07 am
content: QuoteThanks, well yes, but see page 16 of the below about NCP5106, which is an isolator, and suffers the problem......https://www.onsemi.com/pdf/datasheet/ncp5106-d.pdfAlso, it can be read about on the "SOI" page of the infineon website.....they say their isolators which are based on "silcon on insulator" are the most robust to latch up caused by high dv/dt.As such, this is indeed specifically a problem with isolators.As you know, they all have their CMTI (common mode transient immunity) figure.....and the best you get is about 100v/ns.......bridge switching nodes can go quicker than that.I must admit i woudlnt dare put a standard digital isolator as a translator up into the high side of an offline bridge power supply.....it sounds like a great solution but the potential for negative bridge switching node transients messing up is considerable.I do wonder if the 1EDi20N12AF suffers the problem though?.........its price is about $0.07 which isnt that bad?

author: xavier60
author_rank: Super Contributor
timestamp: April 23, 2022, 11:31:39 am
content: There is no need to look any further than the STGAP series galvanically isolated drivers,https://au.mouser.com/ProductDetail/STMicroelectronics/STGAP2DMTR?qs=W0yvOO0ixfF%252Bp5Pfo9gPjQ%3D%3DThey are in short supply as most things are.

author: uer166
author_rank: Super Contributor
timestamp: April 23, 2022, 08:17:07 pm
content: Quote from: Faringdon on April 23, 2022, 08:48:07 amWhat are you talking about? The chip you linked is a regular bootstrap gate driver, non isolated. An isolator has no such issues by definition, when you reference your isolator/GD combo to the switch node.. Of course CMTI needs to be respected but it's a trivial check.Sounds like you're searching for problems that cannot physically exist in the first place.

author: Faringdon
author_rank: Super Contributor
timestamp: April 23, 2022, 08:37:50 pm
content: QuoteOK thanks, i see what you mean, my apologies, i mixed up the terms "isolator" and "level translator"...but its actually not relevant to this discussion.......the fact is , whether its an isolator or level translator without isolation, they all potentially suffer from negative voltage spikes on the "Vs pin", which can bring about serious malfunction.It makes a non robust power supply....as also stated by Dr Ray Ridley.QuoteThanks, but an isolator has the same issues...the 1EDi20N12AF literature discusses it....that is an isolator but suffers it.If isolators didnt suffer this, nobody would ever use bootstrap IC's or "level translators".

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 23, 2022, 08:50:07 pm
content: Isolators are concerned with dV/dt at all, not the direction of isolation voltage.Tim

author: Faringdon
author_rank: Super Contributor
timestamp: April 23, 2022, 09:55:12 pm
content: Quote...Thanks, i take it you meant to have the "NOT" in there...Page 10 of this...https://www.infineon.com/dgdl/Infineon-Selection_Guide_Gate_Driver_ICs-SG-v01_00-EN.pdf?fileId=5546d46250cc1fdf015110069cb90f49..tells of an isolator, the "core-less" tech.It saysQUOTE__Common mode transit immunity (CMTI) up to 100 V/ns___UNQUOTE...which shows it is concerned with dv/dt, and offers CTMI no better than standard bootstrap gate drivers.____....Here is a digital isolator, the SI8610...https://docs.rs-online.com/46c2/0900766b8129b31d.pdf...it lists 50kV/us Transient immunity...this is worse than most standard bootstrap gate drivers_____....Its unfortunate, but all these IC's .....level translators or isolators, which drive hi side fets from low side, are unreliable, and as Dr Ray Ridley says, they are not for use in driving offline hi side fets.

author: xavier60
author_rank: Super Contributor
timestamp: April 23, 2022, 10:38:45 pm
content: Quote from: Faringdon on April 21, 2022, 11:54:37 pmAssuming ZVS, what is the expected voltage slew rate in your application?

author: Faringdon
author_rank: Super Contributor
timestamp: April 23, 2022, 10:50:52 pm
content: I couldnt say till ive measured it...for now, would have to go with the attached LTspice sim which gives 400v/35ns = 11V/ns.However, under certain transient conditions, who knows if its going to be more than this......and with high power smps, the layout cant always be "textbook", and so i may get worse than 11v/ns....also, there may be , during certain transients, big negative voltage spikes on the switching node going well below ground......which is another gremlin of these kind of hi side gate drive IC's......as the above NCP5106 datasheet says.

author: xavier60
author_rank: Super Contributor
timestamp: April 23, 2022, 11:26:35 pm
content: Quote from: Faringdon on April 23, 2022, 10:50:52 pmEven with galvanically isolated drivers, if their output stages are to be powered from a non-isolated supply, a precaution needs to be taken to prevent the negative spikes from adding to the voltage supply to the drivers' output stages. As well as adequate capacitor bypassing, each driver output stage should be supplied through a series low ohm resistor. There is likely to be some negative spike on the low-side Source pins also.I was surprised to see comparable propagation delay specs between the NCP5106 and STGAP drivers, being the faster.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 24, 2022, 04:15:06 am
content: Quote from: Faringdon on April 23, 2022, 09:55:12 pmAn unusual phrasing, but I mean what I said, and you confirmed it by reference.Indeed above 100kV/us, the rate is so insane, mere geometry alone is a problem; a 1ns edge from a HV GAN inverter, across a 2pF isolation gap, with 10nH pin inductances (i.e., typical SOIC / wide body pins), is enough to couple some volts into the pins/traces/leadframe itself. It's not a bad idea to add common mode chokes when using GaN.Plain old Si, you're lucky to get much over 10kV/us anyway.Tim