Next to star grounding also star powering/decoupling? - Page 1
Forum section: electronics / projects

author: DutchGert
author_rank: Frequent Contributor
timestamp: February 19, 2014, 09:32:43 am
content: I just had a discussion with a collegue about decoupling component placement and layout.What I usually do with the below circuit is place the filters (FE30x) close to the component and connect the output (sometimes with a bigger buffer cap of 4u7/10u) with a couple of via's to the inner powerplane.Then I place a set of decoupling caps on the bottom next to each power pin with a shared via to the inner power plane and connect them with the same via on the top side to the chip.In my oppinion this ensures all the caps get sort of evenly used by the IC's power pads.My colleague shares this oppinion but instead of connecting the output of the filter straight to the power plane he uses sepperate tracks from the filter output to each of the power pin/decoupling cap combination. A kind of 'star power' connection from each power pin/decoupling cap back to its origin so to speak.In my oppinion this king of star layout doenst make any sense or improvement to the layout and only difficults routing. Is this true?

author: tszaboo
author_rank: Super Contributor
timestamp: February 19, 2014, 09:42:41 am
content: I think I'm with your colleague, but It is hard to tell from your description. First, if it is possible, I place the decoupling on the top layer, have a via close to the cap, and rout from the cap to the power pin. The order is via-> cap -> pin. The reason for this is via inductance. But I've seen kelvin connected decoupling, LC filtered decoupling and all sorts of magic. Ultimately it depends on the application. I usually work on mixed signal, analog and power, the rules can be quite different from what you show, which is a DSP or high speed MCU I think.

author: DutchGert
author_rank: Frequent Contributor
timestamp: February 19, 2014, 09:53:42 am
content: Quote from: NANDBlog on February 19, 2014, 09:42:41 amI agree that its best to place the cap on the same layer as the ic but in this case that is not possible. Now my order is from top to bottom: pin->via->big power plane->capMy colleague wants pin->via->dedicated line back to filter->capIt is a mixed signal board with HDMI to 1.3GHz coax/STP serialiser/deserialiser

author: nctnico
author_rank: Super Contributor
timestamp: February 19, 2014, 10:04:02 am
content: My advice is to use at least one via per capacitor pin (so 2 vias per capacitor). If possible more and make a small copper poor connecting pins at the same potential if possible.

author: DutchGert
author_rank: Frequent Contributor
timestamp: February 19, 2014, 10:05:56 am
content: Quote from: nctnico on February 19, 2014, 10:04:02 amThats what I thought as well, make the same potential nets as big as possible.Why I only use a dedicated GND pin per cap and share a power via per cap is to ensure that the power from both caps to the pin is 'clean'.

author: AlfBaz
author_rank: Super Contributor
timestamp: February 19, 2014, 10:26:56 am
content: Wouldn't running separate tracks from the filter to the power pins add more inductance than taking the shortest route to a plane?I always thought that keeping tracks as short as possible from the caps to vias to ground/power planes was beneficial and if so why add more track on the incoming side of power as opposed to the return?

author: DutchGert
author_rank: Frequent Contributor
timestamp: February 19, 2014, 10:30:37 am
content: Quote from: AlfBaz on February 19, 2014, 10:26:56 amExactly, thats what I thought

author: AlfBaz
author_rank: Super Contributor
timestamp: February 19, 2014, 11:00:07 am
content: This post here should give some idea as to the magnitude of inductances we are talking abouthttps://www.eevblog.com/forum/beginners/capacitors-position-close-to-ic-why/msg379848/#msg379848

author: tszaboo
author_rank: Super Contributor
timestamp: February 19, 2014, 12:23:23 pm
content: Quote from: DutchGert on February 19, 2014, 10:30:37 amIt wouldn't be better according to TI, if it is on the same layer.http://www.ti.com/lit/an/scaa082/scaa082.pdfFigure 12.And the text said: "Make sure that the signal must flow along the capacitor."

author: AlfBaz
author_rank: Super Contributor
timestamp: February 19, 2014, 12:55:44 pm
content: Quote from: NANDBlog on February 19, 2014, 12:23:23 pmI see what you are saying but the alternate DutchGert's colleague is proposing, or so I think, is running a separate track to each cap/pwr pin combination, instead of going from the filter directly to a power plane or mini-pour. You seem to be talking about the capacitor/power pin combination.

author: free_electron
author_rank: Super Contributor
timestamp: February 19, 2014, 01:52:15 pm
content: A few corrections on misconceptions.1) You never share a via for DIFFERENT return paths.This not the case here. It would be the case if a ground via both feeds ground to caps coming from DIFFERENT pins. So your layout does not violate.2) The signal must flow along the capacitor. This is true only if you do not have a power/ground plane pair. If you have plane pair , that are coupled (meaning no signal layer inbetween) , it is better to give the ic pin its own via to the planes and the capacitor its own via to the planes. The total plane impedance is much lower than what the single cap can provide.Your layout looks fine to me. But ... Why double caps on all these pins ? Does the appnot give specific capacitor mafifacturer /partnumber ? You may wanna do an impedance plot... I suspect you can throw out half of those caps and get away with something like a 22nf cap per pin.

author: DutchGert
author_rank: Frequent Contributor
timestamp: February 19, 2014, 03:03:54 pm
content: Quote from: free_electron on February 19, 2014, 01:52:15 pmThx free_electron, I just started doubting myself.The double caps are straight from the datasheet and appnotes. Since this is the first proto I'll just stick to what they recommend.