D flip flop freq. devider - Page 1
Forum section: electronics / beginners

author: miso156
author_rank: Contributor
timestamp: February 04, 2020, 03:49:10 pm
content: Id like to design freq. devider by 2 using something like D flop build from PBJT.But i dont like to use egde firering D flops, so it must hold the output by some another logic or something. Is there some solution?Until now , I did something like figure below, but it of course oscilate due to immediate changes on D pin:

author: rstofer
author_rank: Super Contributor
timestamp: February 04, 2020, 04:19:42 pm
content: If you don't use edge triggering, what you have is a transparent latch. Since you have negative feedback, as long as the latch input is enabled, the output continues to change state, it oscillates.There's a reason that flops are edge triggered.

author: miso156
author_rank: Contributor
timestamp: February 04, 2020, 04:45:00 pm
content: Can you navigate me how level triggering can be achieved? Means that the change can occur only once per positive Clk.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 04, 2020, 04:56:20 pm
content: A counter is always kind of edge triggered in one way or the other. One can just shorten the pulse so far that one only gets a very short pulse of something like 1 gate delay and this way get a kind of edge trigger with a circuit that otherwise looks like not explicitly looking for a edge.With discrete transistors it is more the other way around and capacitove coupling could be used for the edge to get away with less transistors.

author: miso156
author_rank: Contributor
timestamp: February 04, 2020, 05:12:16 pm
content: THx, from some pherspective, it can be done by circuit "turn on-off by one button". See:However, i am looking for some solution without helping with condensators, only logic.Until now get to solution like pic. below, when I use two Dflops. It should work like when 1st one is set, wait until CLK low to set a 2nd one, and in next positive cycle reset the 1st. Of course, its is not complete done yet.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 04, 2020, 06:26:09 pm
content: One could have a look at the old patents on flipflops. For the ECL version this could be US6191629.

author: David Hess
author_rank: Super Contributor
timestamp: February 04, 2020, 06:26:41 pm
content: Quote from: miso156 on February 04, 2020, 04:45:00 pmI think the standard way is to create a deliberate race condition with gate delays which always comes out one way. Old databooks show the transistor level details for edge triggered flip-flops and you can also find gate level schematics.

author: rstofer
author_rank: Super Contributor
timestamp: February 04, 2020, 06:58:02 pm
content: With 2 D-flops, we would usually just run Q of the first flop into D of the 2d flop. D of the first flop is connected to Q' of the first flop. But this is providing up to divide by 4. If that's what you need... The clocks for both flops are the original system clock.Ordinarily, it is bad practice to gate the clocks. It leads to skew in the outputs caused by differing gate delays for the clocks. This may not be desirable. You can put all the logic you want on the D input as long as you meet the setup time before the clock comes along.

author: miso156
author_rank: Contributor
timestamp: February 04, 2020, 07:06:20 pm
content: Do you thing it should work?

author: rstofer
author_rank: Super Contributor
timestamp: February 04, 2020, 08:56:20 pm
content: No, D needs to connect to Q', not QThat circuit represents a Master Slave D-Flop, an elegant solution.Seehttps://www.electronics-tutorials.ws/sequential/seq_4.html- scroll down to "Master-Slave D Flip-Flop Circuit"Or, for a simpler D flop, look at the 7474 datasheethttp://www.ti.com/lit/ds/sdls119/sdls119.pdfYou can just remove the gates related to Preset and Clear

author: miso156
author_rank: Contributor
timestamp: February 04, 2020, 11:01:27 pm
content: Thank you, one another question, in books i can see a Dflop made by NAND gates, but if I imagine to build freq. devider from this I always end up in oscilating during positive clk. Pls correct me If I am wrong.When I start with Qneg 1, it put a 0 from upper NAND to Set pin of Dflop and switch Qneg to 0. Then the inverter put 1 to lower NAND with CLK still 1 it switch to Qneg to 1 again.Pls correct me If I am wrong.

author: rstofer
author_rank: Super Contributor
timestamp: February 05, 2020, 02:49:37 am
content: Let's suppose Q' = 1, Q = 0, D = 1 and Clk = 1The top left NAND has both inputs = 1 so the output is 0.The top right NAND has a 0 on one input so the output is 1 and Q just changed from 0 to 1 because D was 1The lower left NAND gate has a 0 on the pin from the inverter (because D = 1) so the output is 1The lower right NAND gate as ones on both inputs so the output is 0 which makes Q' = 0 and holds Q = 1Now let's suppose Q' = 0, Q = 1, D = 0 and Clk = 1The top left NAND has a 0 on the D input so the output is 1The lower left NAND has 1's in both inputs so the output is 0The lower right NAND has a 0 on the bottom input so the output is 1 and Q' = 1The top right NAND has 1s on both inputs so the output is 0 and Q=0. In addition, the output wraps around to the lower right NAND and holds it a '1'.I don't see any reason for it to oscillate.The logic values written on the drawing are wrong, the output of the inverter should be 0 because D = 1. This error messes up the lower right NAND as well.It's easy enough to set up an initial state, pick a value for D and then let the clock be '1'. Just walk it through. I did 2 cases, there are two more: D = 1 and Q is already 1 and D = 0 and Q is already 0. Walk them through like I did above.

author: TerminalJack505
author_rank: Super Contributor
timestamp: February 05, 2020, 08:00:56 pm
content: Quote from: miso156 on February 04, 2020, 11:01:27 pmYou are correct. That is a Gated D Latch and it will allow the D signal to shoot through to the outputs when the enable signal (Clk) is high.You can put two of these in series to create a master/slave configuration to build a D Type Flip-Flop. The Clk signal is inverted (and slightly delayed) for the master. This will cause only one of the latches to be enabled (= transparent) at one time.Edit: Had Q and Qn swapped on the Gated D Latch schematic.

author: miso156
author_rank: Contributor
timestamp: February 08, 2020, 09:28:12 pm
content: Finally i did it. The master-slave work pretty good.And the waveforms, where for two clock cycle it makes one period on the output.