New switcher - causing issues! - Page 1
Forum section: electronics / projects

author: Wilksey
author_rank: Super Contributor
timestamp: November 14, 2015, 02:37:56 am
content: Hi Gurus!Attached is a PSU that I am trying to get to work, datasheet for the chip here:http://www.farnell.com/datasheets/1747276.pdfI have pretty much copied the reference circuit from page 10, just adjusted the FB resistors for ~4V.This is the second chip that has decided it will stop working for no apparent reason, the first one just died, no output, nothing!Second one worked for a bit, I had 3.9V on the output, and 0.78V on the feedback, so to be expected, going into the 3.3V regulator, which remains fine, I can feed 5V into the test point and get 3.3V reliably out of the LDO.The buck decided to adjust it's output to 2.3V to 3.2V randomly, now it is dead, 0V on the output, I have tried changing the inductor, and the caps, tried electrolytic and ceramic, makes no difference.Current wise, the 3.3V rail has a PIC24 connected to it, which works fine, checked the outputs, the board itself has no shorts, the PSU draws 30mA @ 12V, the 4V eventually will go to a GSM chip, but this is not connected, so the only thing on the buck output is the LDO.I have designed other switch regs in the past with no issues, these we ~50p on Farnell, should have known better!Can anyone see anything obviously wrong with the attached circuit, specifically why the chip would fail.TIA!

author: georges80
author_rank: Frequent Contributor
timestamp: November 14, 2015, 03:09:02 am
content: More likely your PCB layout - got a picture of the layout (all layers)?cheers,george.

author: Wilksey
author_rank: Super Contributor
timestamp: November 14, 2015, 06:20:50 pm
content: Hi George,Thanks for the reply,I have attached pictures of the regulator section board layout, just 2 layers, mostly top copper, I have omitted the ground plane for clarity.I have laid out boards before with switchers on and they have all been fine, this one is a bit odd!TIA!

author: kony
author_rank: Regular Contributor
timestamp: November 14, 2015, 07:20:41 pm
content: Board preview wihtout poured planes shown serves no purpose - I almost started ranting, then saw the note in post. Please show PCB layout in as-is fashion.

author: nctnico
author_rank: Super Contributor
timestamp: November 14, 2015, 07:56:30 pm
content: Even with pours the ground loop is probably way too large. I'm inclined say its all wrong because the feedback circuit is in the way of creating a small loop for the ground return currents. Check some layout recommendations from TI or National for optimal component placement for such a circuit.

author: DanielS
author_rank: Frequent Contributor
timestamp: November 14, 2015, 08:07:07 pm
content: I agree with nico, the ground and signal loop in the feedback network are far too large, this cannot be doing you any good. You should also be tapping your feedback signal from one of the output filter capacitors, not right off the inductor, otherwise you end up adding trace inductance , resistance and switching noise to your error signal when what you want is the filtered output voltage. I would tap the feedback trace from the second capacitor and snake the trace between the first capacitor's pads.

author: homebrew
author_rank: Frequent Contributor
timestamp: November 14, 2015, 09:08:56 pm
content: Two things that I would add:1) The electrolytic capacitors might be problematic by themselves. The datasheet recommends to use MLCCs. They specify to use 2x C3216JB1C226M which I would stick to or replace them with X7R caps in the first place.2) The datasheet also recommends to connect the thermal pad to a ground plane using some vias. You could easily put 5 vias (0.3 mm) under this pad. If using ground planes on both sides, stitch them together with vias.3) Your input traces are quite large (which is totally fine) but it gets VERY dense at the pads. Is this really still compatible to your boardmaker's design rules?

author: Wilksey
author_rank: Super Contributor
timestamp: November 14, 2015, 10:51:10 pm
content: Hi,Thanks all of for your replies.The feedback pin stays at 0.78/0.79V, but the output voltage changes, input stays the same.I tried replacing the 22uF electros with multi layer ceramics but it made no difference.The ground of the feedback circuit is connected almost opposite the power input pad, so it doesn't have that far to go?There are quite a few GND via's around to connect various points to the GND plane on the bottom, there is no top plane.Yes the components could be tighter, and I could try cutting the track and moving the feedback to the end of the output capsI could understand if the supply was unstable, but what could cause it to give 0 output suddenly? The input is fine, the chip itself doesn't even get warm, the thermal pad is not connected to the ground admittedly, but there is a thermal pad and I have reflow soldered it before soldering the chip pins to make sure it is connected.I presume something is blowing the chips, but I can't see what would, the output also goes to a FET which is not fitted, I have checked for shorts, the PSU doesn't dip or short when the output goes dead.

author: hamdi.tn
author_rank: Frequent Contributor
timestamp: November 14, 2015, 11:49:06 pm
content: PCB layout and Ground with DC/DC switcher are important, however i did a lot of prototype with buck chips and bunch of wires not even a proper pcb. chip react poorly but it do the job for a quick test.still you have to reconsider your layout! . i think like homebrew said , capacitor are important too, low ESR cap are a must.

author: georges80
author_rank: Frequent Contributor
timestamp: November 14, 2015, 11:50:59 pm
content: Where is the ground plane layer? Please post it. I assume then that this is a 4 layer board since you mention that you're only showing the top/bottom layers?Show us the ACTUAL layers as flooded etc (all of them).cheers,george.

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 12:17:03 am
content: Hi George,The bottom layer is the GND plane, I removed the GND plane for clarity, the board is indeed 2 layers - top and bottom.Apologies, I should have included the image with the GND filled. This is now attached. I've removed the top copper again, for clarity.Thanks

author: c4757p
author_rank: Super Contributor
timestamp: November 15, 2015, 12:19:17 am
content: That's quite bad, look at the current path between the input cap and the output cap.

author: georges80
author_rank: Frequent Contributor
timestamp: November 15, 2015, 12:25:32 am
content: Yeah, you have a huge cut ground plane with that trace running from TP1 - can't be good...Please show the vias from the top layer (e.g. to the in/out cap grounds) going to the ground flood.What I'd like to see is the complete Top and Bottom layers - with traces/floods/vias etc.cheers,george.

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 12:32:34 am
content: The plane is cut, but the ground is routed on the top layer for that chip, not the bottom layer.I tried to keep the ground path for the chip relatively straight and point to point.The caps do not go through vias, but directly to the GND pad on the top layer (as shown in previous post with top and bottom layer) where the GND connection is soldered to on the top layer.

author: georges80
author_rank: Frequent Contributor
timestamp: November 15, 2015, 12:38:45 am
content: Please, post the top/bottom layers, showing traces/floods and vias.If you have all the vias shown, then there's really minimal connection from the output caps to the ground plane other than a long trace and that's not a good plan.cheers,george.

author: rx8pilot
author_rank: Super Contributor
timestamp: November 15, 2015, 12:44:28 am
content: The layout, as others have said, is not going to work. The layout details are AT LEAST as important as the components you put on it. I learned these lessons the hard way.Notes that others have not yet mentioned:PGND and AGND are different for a reason. They need to be tied together at a single point. The idea is to keep the inevitable high current/voltage (di/dt and vi/vt) switching noise from impacting the FB and COMP pins. The FB divider should be very close to the FB pin and be surrounded by the AGND if possible. The same goes for the COMP components.The current path from IN to OUT should be as short as possible. PCB inductance is deadly and it only takes tiny amount of it to destabilize the circuit.I seriously doubt there is anything wrong with the parts you have. The layout of a switcher, even a simple one like this, is nearly a black art. Just getting voltage on the other side with a DMM does not mean it is working right. It only means that it is doing something. To know if the circuit is behaving as designed, you have to at least have a scope and the delicate skills to measure your circuit. I spent a ton of time just learning how to measure an SMPS and get basic performance information. It took even longer to learn the details of layout. I read a lot, experimented a lot, and the looked at known good examples. The examples were invaluable at cluing be into what was wrong.There was a design that I did that was too noisy. I purchased the dev board from TI and saw that they had a rather quiet design, so I hunted for the differences, some of which seemed so insignificant. Sure enough, my next revision was fantastic - step response, PARD, ripple, regulation, efficiency, etc.Dont give up, but also don't think that an SMPS is something you slap on a PCB and go. They are sensitive little devils that mix fast current switching right next to super sensitive analog controls. There is no forgiveness.

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 12:47:35 am
content: Hi George,Apologies, Is this what you wanted? An all-in-one view?On the far left, there are pads 3 and 4 shown as GND and VIN, this is where I have soldered 2 wires directly and connected the 12v PSU.Thanks

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 01:01:17 am
content: Hi RX8Pilot,I have used different switchers in the past and put a few on perf board, they may not have been ideal, or worked 100% efficient, but they have worked, I have never had any other chip perform like this one.AcHmed99,I recalculated the components for 4V rather than the values supplied in the DS. The output voltage went from 3.9 to around 3.7 down to 3.2 down to 3.0 down to 2.8 then to 0, all in the space of a minute or so, it didn't give me chance to hook a scope up before it died, nothing measures short cct, just 0V on the output pin, the FB pin stayed around 0.79 (0.8 it should be), the 12V PSU was drawing around 30mA, do you think it could be not enough load? I must admit I didn't think of that, I could add a load to see if it works better?My main wonder if you will is why the output has gone to 0V, if I set the bench supply at 4V and stick it on the VOUT TP it works absolutely fine, I am sure the components are fine, and I have more than likely messed up, which I don't mind , maybe on my other layouts with SMPS chips I have just been lucky, I try to make the main PSU components continuous if I can, I am no expert at PCB design, I know enough to get by usually.If I redesigned with the LM2576 or something it would have probably worked fine first time, but I am now curious as to what I did to make the chip feel like not working.

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 01:05:59 am
content: Hi Blueskull,Two short (1 or 2cm 16/0.2mm) wires were used, PSU was powered up first to check voltage, powered off, GND connected then 12V, PSU turned on, subsequently the PSU was then just turned on thereafter.The chip was stone cold, I checked the power rails for shorts etc and found none.

author: Monkeh
author_rank: Super Contributor
timestamp: November 15, 2015, 01:08:50 am
content: Quote from: Wilksey on November 15, 2015, 01:01:17 amHow fast a switcher have you used before?I have blown up a number of 600kHz switchers with poor layout (actually, the external FETs, they're quite high power). Your layout is not workable for these frequencies.

author: georges80
author_rank: Frequent Contributor
timestamp: November 15, 2015, 01:10:57 am
content: The ground connections are quite weird/horrible. Your output caps only go to ground via the long traces and not to the plane.Analog small signal stuff (compensation, feedback etc) need to be over 'quiet' ground areas.Some switchers can be hobbled together on perf board, some on 2 layer boards and some NEED 4 layer boards. I work with switchers all the time (though mostly constant current for LED drivers) and I have a few designs that will NOT work with 2 layers.Attached is an example proto of a 3.3A LED driver. I used some copper tape to create the ground plane and the switcher IC has a thermal pad and PGND connections that solder to the copper plane. You can see how I've soldered the caps to minimise ground loop/path length etc. This was thrown together to test a new switcher chip before I get prototype PCB's fabricated.Anyhow, I'd safely bet that you have primarily a layout issue with your design versus component issues. I've used ceramic caps with long leads into buck and boost LED drivers and no issues. Concentrate on your layout an THINK about where the current flows in your various paths. Consider the Feedback signal (critical) and where noise can couple in due to ground noise and ground offset issue (high currents in long paths will create voltage drops). Consider noise around the compensation pin and components AND the noise on its ground.Sometimes ONE ground for everything (power and signals) will NOT be a good thing.cheers,george.

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 01:22:32 am
content: Quote from: Monkeh on November 15, 2015, 01:08:50 amI have used a TI TPS6 part before which runs at 1MHz I think from memory, two LT parts, which I think were 0.5 / 1Mhz parts, a LM2676 which is 60 odd KHz I think.George,Are you saying that it would have been beneficial to have connected the ground connection to the plane?I am wondering if it has anything to do with the analogue ground being connected with the digital ground, I can't see anything about isolation on the DS, but do they need to be isolated?I must be honest I am quite ignorant when it comes to frequencies, not on purpose, but I try and make the connections as direct / short as possible, sometimes they are bit longer than they perhaps could be, but usually I can get away with it.

author: georges80
author_rank: Frequent Contributor
timestamp: November 15, 2015, 01:30:20 am
content: The output caps etc should definitely go to the main power ground (same as the thermal pad of the switcher). You need a quiet ground for the comp circuitry and under the feedback trace etc. The quiet ground would be a cut area that current doesn't flow through (i.e. the ground currents that the main in/out caps connect to and your load).Create a good ground to tie the input/output caps together and directly to the switcher IC PGND. That is job #1. Then create the cut ground that is quiet (analog ground). Think about where the compensation circuit connects to and also the feedback trace etc - i.e. NOT over the noisy power ground.I'd rearrange your circuitry if needed to achieve the ground goals. Fatter traces to/from the inductor and as short as possible. Don't route feedback etc need the inductor and certainly not under it etc.Read the datasheet where it talks about the layout, it's not very details and unlike other manufacturers there's not even a recommended layout, but at least there's some hints.Unfortunately some switcher IC's are easier to use than others. In the near MHz frequencies, many can be very 'tricky' to get running stable an efficiently.That's about the limit of my suggestions since I've never used that part and don't know how finicky it is.cheers,george.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 15, 2015, 01:35:10 am
content: Flood both sides with ground, and stitch heavily with vias. Such construction can save a lot of bad routing, of course you should be doing that well in the first place.Tim

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 01:37:46 am
content: Hi George (and others)I do appreciate the tips and hints!It's the first time I have used this switching reg, and it will probably be the last! I will probably stick to TI or LT parts, at least they work with my bad layoutsIf anyone has any more feedback / info as to why the switcher may have just died I would still be very interested to see what thoughts are!Thanks

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 01:41:54 am
content: Tim!Yeah, but bad routing is me specialityI think the next rev of the board will be taking everything and applying it to the next one, I might stick with the same chip, for the price of an experimental PCB (or 10) from China, I can still use the boards I have for prototyping / development by sticking in a linear adjustable reg.

author: rx8pilot
author_rank: Super Contributor
timestamp: November 15, 2015, 01:42:20 am
content: FWIW, I have had bad results with TI and LT as well, due to layout problems. I was seconds away from throwing them away thinking TI doesn't know what they are doing. After a cool down period, I decided to seek out the root cause of my problems.It is unlikely that this chip is an unworkable design. Moving to another chip will not fix your layout issues.

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 01:48:33 am
content: Hi rx8pilot,No, I know that a different chip won't fix my layout issues, I am surprised the chip failed though through the layout, instability, yes, death, I can't get my simple mind around why it would kill the chip.I will take everything that people have suggested and try a different layout, I think my previous board (I would have to look at them as I did them at work in Altium) with the LM2576 did use a GND plane with vias from the chip. Not sure why I did it differently (continuous top route) on this one, seemed like a good idea at the time, and taking the feedback from the inductor rather than the 2nd output cap is probably not helping it either, isolating the feedback and analogue ground seems sensible, not sure it would cause the chip to blow, but cause instability issues, which I guess in turn, could cause the chip to blow?

author: rx8pilot
author_rank: Super Contributor
timestamp: November 15, 2015, 02:04:39 am
content: I am mobile right now, but I think I can find some waveforms I captured from previous learning efforts of mine.Huge voltage spikes can appear on internal mosfet killing it. If you had a low indunctance probe to look at the SW node, you may find some surprisingly large voltage peaks.Do you have a scope?Sent from my SAMSUNG-SM-G890A using Tapatalk

author: Wilksey
author_rank: Super Contributor
timestamp: November 15, 2015, 02:18:25 am
content: Yes, I have a scope I can put it on and see what if anything comes out!What would cause the high spikes / peaks? The ground layout, feedback point (VOUT from inductor) or something else?Thanks

author: DanielS
author_rank: Frequent Contributor
timestamp: November 15, 2015, 02:47:30 am
content: Quote from: Wilksey on November 15, 2015, 01:48:33 amIf the chip operation becomes unstable due to excessive power, ground and feedback parasitics, the chip may have irregular switching not only from noisy feedback signal but also from internal voltages jumping all over the place: the chip may start turning on its switch, this causes the supply to droop and ground to bounce, VCC-GND drops below the UVLO and the driver turns off prematurely, supply across the chip's terminal bounces back, the chip turns back on, rinse and repeat. The output driver ends up spending more time in the on-off-on transient state than on/off, overheats and fails.

author: hli
author_rank: Frequent Contributor
timestamp: November 15, 2015, 02:41:29 pm
content: Quote from: Wilksey on November 15, 2015, 01:01:17 amSo you say that the output went down to 0V while the feedback voltage stayed at 0.79V? That would be strange - where did this voltage come from? When you power it now, is it still that way? Can you hook up a scope to the feedback voltage pin and see whether it follows the output voltage?

author: wraper
author_rank: Unknown
timestamp: November 15, 2015, 03:47:22 pm
content: Quote from: Wilksey on November 15, 2015, 01:01:17 amExcuse me, but this is 500kHz, you cannot do with PCB just what you want. And your pcb have just awful layout which is inappropriate even for 10x slower switchers.Edit: Also you cannot use 22uF electrolytic capacitors, they have too much ESR.

author: Niklas
author_rank: Frequent Contributor
timestamp: November 15, 2015, 05:55:40 pm
content: The datasheet specifies 20V as an absolute maximum rating for SW pins. It could be the electrolytics and/or the long GND trace that adds an L*di/dt transient high enough to cause a breakdown of the switch transistors in the IC. Jim Williams did an interesting video and app note about the importance of diode turn on time and possible failure of the switcher IC.http://cds.linear.com/docs/en/application-note/an122f.pdf

author: rx8pilot
author_rank: Super Contributor
timestamp: November 15, 2015, 06:58:30 pm
content: Shows how to 'see' what is going on.https://e2e.ti.com/support/power_management/simple_switcher/w/simple_switcher_wiki/2243.understanding-measuring-and-reducing-output-voltage-rippleConfigure your scope probe like this (you can make it yourself if needed). Measure from PGND pin to SW pin and see what you have. I would guess that you will see the problem as a very large and very fast voltage spike resulting from the stray inductance on your PCB reacting to your switching currents. If you also look at your FB pin, you will probably see a ton of noise as well which directly impacts the control of the internal MOSFET. The circuit is sufficiently out of control that the mosfet is is being damaged from over current or over voltage or both. This can happen so fast that the chip never has time to heat up on the outside but is burned on the inside.The difference between good and evil is very small.

author: Wilksey
author_rank: Super Contributor
timestamp: November 16, 2015, 12:15:18 am
content: 0.79 on the feedback whilst the switcher was going from 3.9 to 3.7, 3.2, 2.8V, when the output of the switcher was 0V the feedback was 0V as the R divider takes it's reference from VOUT, which was 0V.I suspect as others have highlighted, the internal circuitry has been oscillating and damaging the output FET.I tried electrolytics to begin with, but I tried MLCC's (before the chip died) as I thought it was the cause of the chip going from 3.9 to 3.2V initially, perhaps too much ESR. But it didn't make a difference.I have yet to see if the chip works and if the shutdown was an internal thing to protect itself, if it has blown I am reluctant to put another on, I would rather re-design the board, or a PSU board to retro fit onto the existing one.Interesting links rx8pilot and Niklas, and some valuable feedback from yourselves and others, much appreciated! I do not confess to be a PCB design aficionado, most of my designs, work, most of my layouts, work, but they are not pretty by any means!I shall cut the plane around FB and AGND and put the rest of the GND's on the plane below with VIAs, including the TR pad on the switcher, and putting the feedback input onto the inductor rather than the output caps was just stupid of me! I'll probably move the FB circuitry over towards the output caps also.

author: nctnico
author_rank: Super Contributor
timestamp: November 16, 2015, 03:30:14 pm
content: Still I'm not a fan of Rohm. The chips I've seen from them where rather unlogical which hints to ultra low cost designs made by people with very little experience.

author: Wilksey
author_rank: Super Contributor
timestamp: November 16, 2015, 04:01:32 pm
content: I looked at a previous one I did earlier, which worked out of the box, using a TPS62110, I must admit, I did not put the feedback near the inductor, and I did connect everything to the plane on the 2nd layer, but the plane was continuous around the feedback circuit, and I connected analogue and digital ground together without issue.

author: Wilksey
author_rank: Super Contributor
timestamp: November 16, 2015, 04:30:19 pm
content: I have decided to stick with the chip and make a separate power board as I can still use my old one for prototyping with a bench supply, but I think it is worth designing a SMPS the right way as everything in the future will be SM, and I would like to use the cheaper chips, even if the more expensive ones are more forgiving to bad layout!The capacitors I would use on the output are:http://uk.farnell.com/kemet/c1206c226m8ractu/cap-mlcc-x7r-22uf-10v-1206/dp/21181351206 X7R 22uF 10V (don't need 35V as I am only outputting 4V, which gives plenty of overhead).As nobody commented on the actual schematic I assume it was OK?Well, if someone wouldn't mind just doing a quick sanity check on this before I start the new layout I would be appreciative. The VIN will be protected by the other board as there is a bridge rectifier on the input of the power, so VIN on this board is AFTER the bridge.I shall post the entire schematic for this as it is only a PSU, I have also added a few extra comments to the schematic (the tilde ~ means approximately / nominal it might look like a '-' at first glance)TIA!

author: Wilksey
author_rank: Super Contributor
timestamp: November 17, 2015, 09:19:15 pm
content: Anyone?

author: georges80
author_rank: Frequent Contributor
timestamp: November 17, 2015, 09:27:11 pm
content: It's the layout that we'll want to see. We 'assume' your schematic is correct and based on the reference design...cheers,george.

author: metacollin
author_rank: Contributor
timestamp: November 17, 2015, 09:59:07 pm
content: Ok, there is a lot of solid advice in this thread, but also a lot of speculation and vagueness. No one has actually given a specific cause of the problem, or how to fix it. But all the layout advice is good, regardless.Well, everyone is taking about frequency like its a big deal. It's not, in this case. This isn't a sine wave. The slew rates of MOSFET switches is not even a little related to how often you switch them.Anyway, I'm going to go all in and give a specific answer: it's your input capacitors. The high dV/dt loop will have ringing voltages superimposed on your switching wave form, and you have easily 10nH of loop inductance there, more than enough to cause >8V of ringing. 12V+ >8V = blown output MOSFETs. And that is indeed what you're seeing, the switcher works at first but as spikes on switching node hammer and quickly blow the FETs, they get more and more leaky, the output voltage falls, and eventually they can't even turn on anymore. The 30mA draw is almost certainly the gate drivers trying to turn on the blown FETs, but there is just one big hole in the oxide layer separating the gate, so it's just shorting through to ground. Whoops.When the data sheet says the input capacitors should be as close as physically possible to the input of the chip (which, by the way, the data sheet does) what it really means is this: the input capacitors should be as close as physically possible to the input of the chip.The frequency is not the issue at all here, as mentioned earlier. The MOSFET turn on time is the same regardless of if you're turning it on 50,000 times per second or 500,000 times a second. The switch node formed by the MOSFET drains has no series inductor there. The drains are shorted together to form the SW pin. Frequency is irrelevant. The dV/dt is independent of frequency.The primary switching loop that sees all the actual switching and (being MOSFETS, very different beasts from, say, a BJT based switcher like the lm25xx parts) extremely high dV/dt slews is a loop from the input capacitors, to the sources of the top side and low side switches, with the drains connected to the inductor. The inductor itself is not actually part of this loop. The two switches wiggle it's one terminal between them, pulling and returning currents from the input capacitors. The input caps are the most critical part of the buck convrter. Output capacitors only effect output ripple, and it's not terrible if they are relatively far away. Parasitic inductance in series with 4.7uH inducantance is just a little more inductance to store energy in, it is not really an issue. The position and loop size of the input to output is mostly DC save for the output ripple, and it should not be a focal point.Though aluminum electrolytics are not capacitors at 500khz, too much ESL due to their physical construction. They're expensive resistors. They will just have ripple current proportional to their ESR flowing in and out of them, so serve no purpose beyond generating heat. They have far too much ESL to do anything at all to a 500khz ripple. So I assume they must be to heat the board, though it seems resistors would be a cheaper and more reliable means of doing this.Also, be sure to have enough ceramic output capacitance to keep the ripple voltage low enough that the ripple current on electrolytic output caps (which is simply the ripple voltage/their ESR, since remember, they are resistors at this frequency) does not exceed their maximum. Generally 75mV is the rule of thumb for this.

author: Wilksey
author_rank: Super Contributor
timestamp: November 18, 2015, 12:40:27 am
content: Wow, metacolin, that was a superb and very specific answer, which makes absolute sense, I never would have though to look at the input cap locations, I mean, they seem close, but I guess from what you are saying they need to be almost touching pad?I am going to redo the layout, would appreciate, when I post it up if you experts could cast your eye over it, as even if my other circuits have worked in the past, these MOSFET ones need a bit more care taken at the layout stage, live and learn!I don't mind spending a few ££'s to get a few boards made (cheap as chips from China) to learn the correct way to layout a switching supply. Linears are so much easier!Thanks (all) once again! I shall post a layout soon!

author: Monkeh
author_rank: Super Contributor
timestamp: November 18, 2015, 01:17:53 am
content: Quote from: metacollin on November 17, 2015, 09:59:07 pmBut the requirement to switch them very fast is driven by the rising switching frequency..Quote from: Wilksey on November 18, 2015, 12:40:27 amI wouldn't go that far. The major problem with your existing layout is the complete lack of a useable ground plane, and the resultant horrific loop area. Also, pay attention to your AGND and PGND pins.

author: rx8pilot
author_rank: Super Contributor
timestamp: November 18, 2015, 01:35:34 am
content: Quote from: metacollin on November 17, 2015, 09:59:07 pmI believe the switching frequency is relevant because the higher frequencies require faster slew rates than lower frequencies. As you pointed out, the slew rate required is kind of the root of all evil and largely what created the layout challenges. With lower frequency you have more options to slow the gate pulse down passively to avoid the problems you get with very high dV/dt. It is harder to layout a 500khz SMPS than a 50Khz in my opinion. The higher freq's have a lot less forgiveness.I definitely agree that the input caps need to be nearly on top of the input to the chip. My general lesson from SMPS designs is that the layout can't be tight enough. Visualize the current paths - I print it out on paper and use a highlighter to follow the current around. Sounds silly, but the tiniest details make real improvements.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 18, 2015, 03:12:52 am
content: Contrary to popular belief, minimial series inductanceisn't a good idea.That said, monolithic switchers are designed with it in mind, so you need the caps nearby anyway, in this case. 10nH won't be a problem, they wouldn't ever work if they needed less than that.Tim

author: Wilksey
author_rank: Super Contributor
timestamp: November 18, 2015, 06:53:13 pm
content: I have redone the PSU section as a separate board, I have tightened up the placement and put a plane on the bottom, and connected everything to the plane, moved the feedback circuitry across near the output, added 6 VIAs to the centre pad of the switcher. I hope I have captured all comments sufficiently and laid the board out accordingly.Will this layout work for this switcher?TIA!

author: Monkeh
author_rank: Super Contributor
timestamp: November 18, 2015, 07:00:06 pm
content: Your comp pin is effectively floating. You've still mixed up AGND and PGND.Get rid of the thermals on the vias in the thermal pad. They defeat the purpose.You may want to use more and larger vias, and pour GND on the top as well.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 18, 2015, 07:18:37 pm
content: Pins 7 and 8, it's preferable to route them lengthwise, out from the footprint, then join together. When pads are shorted together laterally, you are depending on the soldermask to prevent a shorted solder joint. So you're at risk of generating false-positives during inspection. AOI (automated optical inspection) can detect when solder joints are correct or shorted together, but doesn't know that pads might be joined electrically anyway.Doesn't really matter for manual assembly, but even then, pins glommed together are probably a slight mechanical concern, so should still be avoided. And it looks ugly..Also, neck down the traces. They shouldn't be wider than the pads. Pin 2 to TP1 can all be smaller traces, and it's not a problem for performance.I'd rather see pin 6 routed on the bottom, but keep it down around (below, even) where the compensation parts are. That way it's not disturbing the bottom ground pour beneath the circuit.One of C4-C5 should be flipped so it can connect directly to pin 1 as well.Why not pour copper over the top, and stitch with vias?Tim

author: rx8pilot
author_rank: Super Contributor
timestamp: November 18, 2015, 08:10:43 pm
content: Your FB divider and filter cap will pickup less noise if placed close to the chip. Make the trace after the output caps, but consider putting the divider itselfe right next to the chip. It is drastically lowering the voltage for the FB pin and has a long way to travel and pickup noise.Overall, there is a major improvement!Quote from: Monkeh on November 18, 2015, 07:00:06 pmThat is weird. That cap should be on the 'quiet ground' which is the AGND and it appears to be connected to nothing. The FB divider should also be returned to this ground. For my designs, I cut an AGND below the chip and the comp, FB parts. then tie them together at one small point. The goal is to keep the PGND and AGND separated since you can expect ground noise on the high current side and the control components need to be isolated as much as possible from that.

author: Wilksey
author_rank: Super Contributor
timestamp: November 18, 2015, 11:28:20 pm
content: Hi,Thanks for the feedback!I have moved the FB components closer to the chip, flipped one of the input caps, removed thermals on the GND pads, separated AGND from PGND, though I am not sure if I have routed this correctly, I presumed separate net connections, so I have removed it from the plane, was this the correct thing to do?I have moved the traces out on the SW pins, rather than link them.I have routed pin 6 below the feedback path.I did forget to connect pin 5 comp cap to ground!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 19, 2015, 01:34:42 am
content: Hmm, it's not obvious if AGND can be disconnected from PGND...I wouldn't bother routing it on the bottom either, just tie everything to ground.Tim

author: rx8pilot
author_rank: Super Contributor
timestamp: November 19, 2015, 02:13:16 am
content: At some point (one point) the AGND and PGND need to be tied together. The reason they are separated on the chip is to allow a separation in the layout.Here is an example from one of my projects. It does not translate perfectly because it is a 4 layer double sided design, but it shows how I handled the AGND as an isolated island and tied it to PGND through an 0603 ferrite (mainly for convenience and a little filtering). The components inside the island are the delicate ones that make up the control loop and feedback. The FETs and inductor are far away from the GND tie.In the end, this design is very quiet and stable, in part by keeping the AGND as noise free as possible. I think the changes you have made so far will keep the system from self destructing but there are always little tweaks.

author: Wilksey
author_rank: Super Contributor
timestamp: November 19, 2015, 02:47:13 am
content: Hi Tim, rx8pilot,I have modified it such as the AGND is routed on the top layer rather than bottom.The AGND and GND are connected via a 0R resistor (can use an 0805 FB if better?)Really do appreciate all the help and input thus far!

author: georges80
author_rank: Frequent Contributor
timestamp: November 19, 2015, 02:58:39 am
content: Tie the AGND and PGND planes together with a trace or via at an appropriate location. No need to add a component unless you want two separate nets.i.e. create your cut plane areas, route the connection from AGND to PGND and then flood the areas. Attached is an example of separating a power ground (high current switch ground) from the signal/ucontroller ground and connecting the two in a 'quiet' area of the power ground.This separation is to ensure that the uC regulator/ADC etc are all referenced from the same GND without and 'bouncing' (from one area to another) due to high current flow.cheers,george.Oh, the switcher core (LED driver) is capable of 120W+ output, hence the need to separate the digital ground from the power ground. Same reason to keep the control loop circuitry of the switcher isolated from high current switching paths.

author: rx8pilot
author_rank: Super Contributor
timestamp: November 19, 2015, 03:09:50 am
content: Quote from: georges80 on November 19, 2015, 02:58:39 amMost certainly, I chose to make two nets to help avoid tying anything to the AGND that should not be. In my case, the extra part is no big deal. A trace accomplishes the same thing on a tight and/or cost sensitive layout.My last note.....you can now go direct with the EN trace and keep a fatter GND plane. It's a big change from the previous layout.

author: Wilksey
author_rank: Super Contributor
timestamp: November 19, 2015, 03:29:57 am
content: Hi,Ok, in KiCAD I think the only way to link two signals together like that is by using a link, which is easily enough to do, otherwise the DRC get's upset!rx8pilot, when you say go direct with EN, do you mean route it on the bottom (probably not as it will interrupt the GND plane) or route it solely on the top layer?I can route it either around the inductor or at the bottom of the comp components?Thanks!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 19, 2015, 04:20:24 am
content: I'm fine with where EN is routed.Obviously, don't put AGND on a separate net, put it on GND. Just route it differently.Still haven't tried top side pour and stitching?Tim

author: Wilksey
author_rank: Super Contributor
timestamp: November 19, 2015, 12:59:14 pm
content: Hi Tim,No I haven't done the top copper pour yet, it will make the routing harder to see I think unless I leave it till the end?I could route AGND on the top layer and then add a via to ground, but I can't route it on the bottom layer as it will just merge with the ground pour.I'll do that in a sec to see how it looks.EDIT---Layout attached.

author: Wilksey
author_rank: Super Contributor
timestamp: November 20, 2015, 01:04:55 pm
content: I've added a second pour for the AGND and added a copper link, would this layout be better over the other or is the other one better?TIA!

author: nctnico
author_rank: Super Contributor
timestamp: November 20, 2015, 02:35:58 pm
content: I'd put C1 and C2 at the top of IC1 to reduce the size of the return current loop. I'd keep the ground plane solid but make sure the analog ground is not in a high current return path (line of sight).

author: DanielS
author_rank: Frequent Contributor
timestamp: November 20, 2015, 03:49:49 pm
content: Reduce the length of that link to reduce the size of the ground pour slot. You may also want to add a bypass capacitor near pin 6 since that very long trace might pick up a fair amount of noise. I would also put my SMD vias much closer to the capacitor pads. I usually put mine only far enough to be under the solder mask where possible.

author: Wilksey
author_rank: Super Contributor
timestamp: November 20, 2015, 03:54:00 pm
content: Quote from: nctnico on November 20, 2015, 02:35:58 pmHi,WRT the AGND, do you mean as I did the routing yesterday, with the pads connected together then on a via to GND?

author: georges80
author_rank: Frequent Contributor
timestamp: November 20, 2015, 05:09:20 pm
content: Actually, you want that AGND via gone. Connect the AGND pin to the PGND on the chip with a trace - i.e. route the trace from the AGND pin inwards to the PGND thermal/solder pad. All the high current stuff will flow from the PGND copper flood, up through the vias you have on the thermal pad area and into the PGND pad of the switcher chip.You do want the AGND to have the same potential as the rest of the chip's ground (i.e. PGND), you just don't want high currents flowing through that path - and you have achieved that by cutting the AGND away from PGND and connecting all the appropriate components (compensation network, feedback divider etc) to that isolated AGND island. Now you just want the AGND to connect to the PGND right at the switcher chip.cheers,george.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 20, 2015, 07:52:23 pm
content: Earlier was better.

author: Wilksey
author_rank: Super Contributor
timestamp: November 20, 2015, 10:05:48 pm
content: Ok, I have done as suggested and routed the AGND into the thermal pad.Hopefully this should work now?TIA!

author: c4757p
author_rank: Super Contributor
timestamp: November 20, 2015, 10:09:49 pm
content: You're one trace short of an unbroken back plane now.... you can do it!

author: rx8pilot
author_rank: Super Contributor
timestamp: November 20, 2015, 10:18:58 pm
content: That EN trace can easily go around the top, may have to move the GND via from the input cap a little. Then you have the coveted unbroken GND plane.

author: nctnico
author_rank: Super Contributor
timestamp: November 20, 2015, 10:53:51 pm
content: In this case a ground plane going from one side of the PCB to the other isn't going to improve things since the loop carrying high currents is still too large. C1 and C2 need to be moved close to the switcher chip. Now the ripple current needs to travel a very long way back to the chip.

author: georges80
author_rank: Frequent Contributor
timestamp: November 20, 2015, 11:27:12 pm
content: Rotate L1 90 deg clockwise. Then move C1/C2 and TP1 below the inductor. That shortens all the paths including your FB/VOUT trace.Put a couple of vias on the Cap Grounds rather than relying on just one via. i.e. do a bit of via stitching. Ditto for the input caps.cheers,george.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 21, 2015, 06:49:37 am
content: Speaking of shorter paths, if there should be any ground loop voltage generated by this circuit (and keeping unbroken ground plane is top priority towards achieving that -- which is fine as shown, because all the current carrying paths are over solid ground), then it appears between the grounds of the two connectors, as common mode noise.A good way to address this is to place the connectors on the same side of the board, together. That way, any voltage drops in the ground path, due to switching currents, will tend to be equal and opposite for both the VIN and VOUT routes. You'd also place one last filter cap near the connectors, to ensure ground loop or differential mode noise doesn't make it out.Please excuse the crudity of my drawing:Without being able to put both connectors in the same area, it would be quite challenging otherwise to implement this. The traces can be organized as above, where they're filtered together like, but then the trace turns around and goes all the way across the board, to the connector on the other side.Now, the ground to that connector has to be drawn from the far side, as well. So in this case, you might actually use an -- ever so dubious --ground plane cutto isolate ground loop voltages from the far connector. In fact, think of it less as cutting ground, and more as placing a connector in the (electrically) correct place to begin with, but changing your mind and running a parallel pair of wires over to where you actually wanted the physical connector. You're just using PCB traces instead of wire.You can generalize this to other noisy circuits, even in the middle of a PCB. Suppose you have a large PCB, with many sensitive analog circuits around the edges. In the center, you have an FPGA-ADC combo to acquire all those signals, then shoot the data down a digital bus of some sort, I don't know. So, you need to provide power somewhere. If you needed to place the DC-DC converters right in the middle of everything (straddling the line between noisy digital and quiet analog regions), it might be reasonable to allocate a rectangular area for it, placing keep-out areas on three of the four sides. This cuts the ground plane*, and prevents traces from entering the region on those sides. Thus achieving the single entry point condition, containing any ground loop voltages, and making it much easier to filter.(*Physically carving the board along the same path isn't necessary, but can be helpful for other purposes, like thermal, mechanical and EM isolation for precision voltage references, or high stability crystal oscillators.)The primary downside to cutting planes is, you get a tuning-fork type resonance mode along that gap. Which means, if you have ground loop voltages, at just the right frequencies, you can get a rather good antenna, which is even worse for your circuit (and your system, which might not pass EMC!).Also, the cardinal sin of cut planes is: routing tracks over the gap. That directly couples the trace's displacement current** into the slot, making not only an antenna, but a coupling network to deliver power directly into it! Likewise, the power sapped from the signal manifests as poor frequency response, or a bouncy logic edge.**That is, the current which flows due to AC and transmission line effects. The image current. Any gap along the "path of least impedance".Also,EMC can be addressed somewhat by adding damping to slots and gaps. As long as the main isolation goal has been achieved (e.g., keeping really low impedance voltage sources away from your connector grounds), a little damping resistance here or there can help suppress the radiating antenna modes. A small resistor or ferrite bead placed across the gap (yes, literally "GND" net on both pins; or if it's a galvanically isolated gap as well, then a Y-type capacitor, usually still with the added R/FB) is the best way. Preferably at the open end of a slot near the edge of the board, or in the middle of the length of a slot that's closed at both ends. The impedance of such a slot is probably in the 50-200 ohm range, so a similar resistance (or impedance of ferrite bead in whatever frequency range matters) will provide the best damping.Tim

author: Christopher
author_rank: Frequent Contributor
timestamp: November 21, 2015, 08:56:17 am
content: Some integrated converters can be very forgiving of bad layouts. You know the ones--put the chip down, an inductor diode and two caps. But just cos it works... doesn't mean it's not radiating like an fm radio tower!That being said... thus thread has a lot of awesome info from you gurus.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 21, 2015, 07:38:53 pm
content: Well, the last few pages we're just been nitpicking...Hopefully the OP has learned something useful, rather than being frustrated by us pedants.All that's left, really, is for OP to build it again, and see if it works this time. The rest is just noise.Tim

author: rx8pilot
author_rank: Super Contributor
timestamp: November 21, 2015, 08:37:58 pm
content: Quote from: T3sl4co1l on November 21, 2015, 07:38:53 pmAgreed. The original layout was clearly self-destructive. Half of this thread was dedicated to keeping the circuit alive and delivering voltage/current. The other half seems to be dedicated to doing it well. I have a few designs that were 'slapped' on a PCB. They deliver the expected voltage and current, but noisier and less stable than they could be. On the circuits that matter, I have been sharply focused on the nit-picking details of SMPS designs and layout. They perform better than data sheets in some cases and I get a very clean and reliable source of power that does not cause problems with delicate low voltage analog and high-speed digital that the SMPS feeds. I like knowing how to do it 'right' and how to do it 'fast'. Both of those concepts need to be balanced based on the application.One of the biggest challenges in SMPS design for me has been learning how to measure the performance of it. You can't just stick a DMM on the output and declare it to be working.

author: Wilksey
author_rank: Super Contributor
timestamp: November 21, 2015, 10:53:09 pm
content: To be honest, originally I thought it was something wrong with the schematic, as I have put several layouts down as said previously with no thought, probably much like blueskull, I did the layout in a bit of a rush, and the 2 stupid mistakes I should not have made was taking the feedback from the inductor and not putting the caps etc on the groundplane, and I know some of the things like placement of certain components and flooding the top with copper is nitpicking / belt and braces.BUT...Having said this, I really do appreciate all of the sound advice given in this thread, and I think a lot of others can benefit from it also, there is a shed load of useful information on this thread alone not to mention the other threads! I do not confess to being any kind of expert in electronic design or layout, most of my stuff works usually by fluke, but one of the great things about this forum, is the community that participates, I try and help out if I can, but there are others with far more experience and worth that help also.It's very easy to take information and advice and disappear from the face of the planet without so much as a thank you, and we're all guilty of it at some point or another, but we / you continue to help.So, with that said, thank you everyone who has had any input, good or bad, it's all useful and appreciated advice!

author: rx8pilot
author_rank: Super Contributor
timestamp: November 21, 2015, 11:37:21 pm
content: Quote from: Wilksey on November 21, 2015, 10:53:09 pmFWIW, I joined this board specifically looking to understand how to build a high performance power supply. When I joined roughly 18 months ago, I had a Fluke 87, a soldering station. I dropped out of EE school in the early 90's but have been a hobbyist since I was a kid. Since then, the members of this community not only helped build my skills and understanding, but gave me the confidence to transition my mechanical design and manufacturing business into an electronics business. My living now solely depends on my electronics skills. While I have been studying and experimenting every waking hour of every single day - 7 days a week. There is only so much you can get from books and online classes. The real -life experiences that are shared on the EEVblog have been absolutely critical to me moving up, getting smarter.My first few SMPS designs were a disaster. They were all copies of data sheet examples that were slapped on a PCB. While I am not (yet) the worlds gift to SMPS design, I have learned in a short period how to design pretty much any topology, any voltage, and any current that I could possibly need. I can also control the performance of each supply and balance that with any financial and space restrictions. It's kinda awesome. Now, I am primarily working on the high-speed digital, delicate noise sensitive analog signals, DSP, FPGA's, etc that are being powered by my SMPS.

author: Wilksey
author_rank: Super Contributor
timestamp: November 26, 2015, 11:05:00 am
content: Did a few last minute tweaks and new PSU board ordered, just have to wait for China to make and send them!The bloody switcher IC is out of stock now!Typical!