explaination of 34401a dc input amplifier section? - Page 1
Forum section: electronics / projects

author: sarepairman2
author_rank: Frequent Contributor
timestamp: August 13, 2015, 02:47:11 am
content: So I had a gander at the 34401a service manual and the input amplifier seems pretty confusing.is there any good write up to explain the logic behind the design?

author: nfmax
author_rank: Super Contributor
timestamp: August 13, 2015, 06:49:41 am
content: 'The Art of Electronics', third edition, pages 343-344

author: Cerebus
author_rank: Super Contributor
timestamp: August 17, 2015, 04:38:17 pm
content: As many people won't have The Art of Electronics 3rd edition (I don't, I've only the 2nd edition) and a quick look at the AoE contents listing shows this is new and very specific material I think a more detailed look at this is necessary.Like many CAD produced schematics it's not the easiest in the world to decypher. If it was redrawn I suspect it would be quite obvious to you how it works - except possibly for the JFET and op amp feeding the drains of the JFET pair, that's a bit trick. The first time I saw that page in the service manual I didn't understand what was going on until I re-drew the schematic "on the back of a fag packet".Basically, it's a differential JFET source follower with a trick that keeps the FETs operating in the ohmic region, but I think a bit more explaination is in order. I'll try and attach the relevent schematic from the manual and talk you through it.The op amp U103-B along with the resistors in U102-C basically produce two stable voltages, nominally -16V at pin 19 and -14.6V at pin 18. This is used to impress a voltage drop of 1.4V across the the two 2K resistors at pins 16 and 17 with the help of (U153-A + Q152 + Q153) and (U153-B + Q150 + Q151) respectively. That is, this is a pair of constant current sources (strictly, current sinks) acting as 700 uA source loads for the dual n-channel JFET U104.I suspect that the over-the-top use of the 10V reference to drive this, rather than a simple voltage divider, is to scratch back some CMRR lost to poor matching of the JFET pair. Even monolithic pairs such as this have poor matching compared to what is possible in bipolar processes. The JFET pair used here is obscure and probably obselete and I can't find any data on it. The very similar HP E1412A VXI system DMM uses an LS844 JFET pair. The figures for the LS844 are 5 mV matching of Vp, 1% matching of Idss and 0.6% matching of gm.So we've got a differential pair with constant current loads, sounds familiar? It might be a bit unfamiliar because this is a source follower stage rather than the more familiar common source stage but they work in essentially the same but complimentary fashion. The OP27 op amp, U106-A, is just providing voltage gain and output drive and U101-C with U102-B are providing switchable negative feedback to set the amplifier gain.The unusual, and clever, bit is the current source (Q105-A, Q104) driving the drains of the JFET pair (U104). This tries to keep the Vds of the JFETs to 0V - of course it won't quite get there, but it'll get close. Forcing the Vds of the FETs to be as low as possible keeps the FETs operating in the ohmic region rather than operating in the more usual saturated region. This keeps the gate operating current (input leakage/bias current) as low as possible. We're talking in the 10's of femtoamps region here, perhaps 100 fA. My simulation of the E1412A circuit gives 67 fA input leakage - you are definately going to need guard rings on a PCB for this baby.I hope that's helpful.