Xilinx XCZU2EG - Flashing spi flash over jtag? - Page 1
Forum section: electronics / general

author: glenneaux
author_rank: Contributor
timestamp: December 22, 2024, 07:54:13 am
content: Have this deviceWant to play around with flashing the spi flash, and can do from uboot.But if something goes wrong, it will be one way flash.Can I flash this memory via jtag without the sources ? What's required software/hardware wise? Can we get away with an stlink converted into jlink?

author: laugensalm
author_rank: Regular Contributor
timestamp: December 22, 2024, 09:54:38 am
content: I haven't tried on this particular platform, but you should be able to access a standard boot flash via OpenOCD and any supported third party adapter, there are various config files for MPSoC platforms.There are two methods, one is the CPU built-in in circuit emulation which works for standard boot flashes, typically. The hard low level method is boundary scan which allows you to selectively toggle pins, but you need a config file and be very much aware of which pins you are toggling, meaning, there is no general solution and you might have to dig into the BSCAN tools.WRT original JLink, I remember issues with different firmware versions in openOCD, but in general it should work.

author: asmi
author_rank: Super Contributor
timestamp: December 23, 2024, 02:34:38 pm
content: Vivado Hardware Manager allows you to read/write boot qspi flash via JTAG. So you can use it to back up existing programming as well as to program something new.

author: glenneaux
author_rank: Contributor
timestamp: December 23, 2024, 09:53:37 pm
content: Quote from: asmi on December 23, 2024, 02:34:38 pmThat sounds promising. Is there a cheap tool that will work? Would a knock off platform cable do the trick?

author: asmi
author_rank: Super Contributor
timestamp: December 24, 2024, 02:34:07 pm
content: Quote from: glenneaux on December 23, 2024, 09:53:37 pmDon't know about knock-offs, but you can buy a "legal" JTAG-HS3 cable from Digilent for $59, or build the one yourself for about $10 worth of parts and program it using a tool provided by AMD/Xilinx to turn it into a "real" debugger.

author: glenneaux
author_rank: Contributor
timestamp: January 09, 2025, 07:55:13 am
content: Quote from: asmi on December 23, 2024, 02:34:38 pmI'm back!Got a HS3 and can communicate with the device.Any pointers?Not sure how to go about downloading or reprogramming the qspi flash - Have tried some things i've googled, including "adding" a "Configuration Memory Device", which I'm not sure which one to choose, and issuing a readback command ( readback_hw_cfgmem ) which fails with the belowCode:readback_hw_cfgmem -all -format bin -file c:/ifmdata/test.binERROR: [Labtools 27-3756] Configuration memory readback is not supported for specified deviceHave been playing with xsct which is interesting but not sure how to tackle itCode:xsct% targets1 PS TAP2 PMU3 PL4 PSU5 RPU (Reset)6* Cortex-R5 #0 (RPU Reset)7 Cortex-R5 #1 (RPU Reset)8 APU (L2 Cache Reset)9 Cortex-A53 #0 (APU Reset)10 Cortex-A53 #1 (APU Reset)11 Cortex-A53 #2 (APU Reset)12 Cortex-A53 #3 (APU Reset)xsct%I have an feeling the device needs to be in JTAG boot mode (this device doesnt' have jumpers or dip switches, maybe I can change boot mode on the board somehow - have read that its possible to change while booted up via JTAG? through xsct perhaps?https://github.com/slaclab/axi-soc-ultra-plus-coreIdeally I'd like to be able to flash a new BOOT.bin to the qspi flash and read/write the emmc.This was also interesting but I imagine/hope don't need to go down this path?https://github.com/raczben/zynq_flashedit: worked out which pins were boot modes, can start in JTAG boot (by checking boot mode register in vivado, confirmed i could switch between 0010 QSPI and 0000 JTAG, is this helpful?)

author: asmi
author_rank: Super Contributor
timestamp: January 10, 2025, 12:50:17 am
content: Quote from: glenneaux on January 09, 2025, 07:55:13 amHmm, it looks like you are right, I've been thinking with "pure" FPGA, for which it is possible to both program flash and read it back.

author: glenneaux
author_rank: Contributor
timestamp: January 10, 2025, 08:33:24 am
content: Quote from: asmi on January 10, 2025, 12:50:17 amVivado offers to verify the programming of the external device so it must be able to read back, unless it verifies in the FPGA and the data never comes back to the PC.In a whole new world now with this one.

author: asmi
author_rank: Super Contributor
timestamp: January 10, 2025, 02:30:02 pm
content: Quote from: glenneaux on January 10, 2025, 08:33:24 amI don't have that much experience with SoCs - I've been working mostly with FPGAs.

author: glenenglish
author_rank: Frequent Contributor
timestamp: January 12, 2025, 10:05:11 am
content: Xilinx SoC - Vivado loads a program into the PS to do the job..... In the FPGA on the TAP it either works with pins directly, or loads a picoblaze ....

author: glenneaux
author_rank: Contributor
timestamp: January 12, 2025, 10:14:44 am
content: Quote from: glenenglish on January 12, 2025, 10:05:11 amI've been going down that path, playing with Vivado and Vitis to try and get my head around whats involved.I'm generating an FSBL based off my config, but it doesnt appear to run.. or at least Vitis is attempting to set a breakpoint for when the FSBL exits and its never getting there, apparently.

author: glenneaux
author_rank: Contributor
timestamp: January 14, 2025, 12:33:44 pm
content: Good news.I installed the toolchain, including Vivado and Vitis.I spent some time tinkering and learning, getting it to boot up the "hello world" sample thats included, with no memory controller etc, just the zynq itself.That seemed to work after learning the toolchain a bit, and struggling a little with the new version of Vitis.. appeared to hang and do weird things. I was able to have it send stdin and stdout to the jtag uart.I went back to "Vitis Classic" and got back to square one, re-learning the IDE, reproduced the same hello world program.One thing that I found was that I had to change it from using the FSBL it was building, to bringing board up with tcl script.. in the "new" version of the IDE Vitis, it would run FSBL and wait for it to hit an exit command - maybe this was never hit because it doesn't have debug symbols enabled for the FSBL.. not sure, but this would cause it to not load the hello world ELF file and it would stop.In the old version of the IDE, it would actually progress past this stage, maybe on a timer.. so that was a suggestion that the FSBL was infact functioning.I went back to the "Program Flash" command, now under the impression my FSBL was OK. This time in the debug console it actually loaded a "mini uboot" binary that is included in Vitis but it hung once it tried to access the QSPI - This wasnt enabled in the hardware platform.I went back to Vivado and enabled QSPI and recompiled everything. Tried it again and away it went - I reflashed the original .bin file I had dumped through linux as /dev/mtd0, 1, 2, 3, 4, and it appeared to verify ok but at the end of the verification the function hung.I repowered the board and just from the LED's on the back I could see it had booted the linux system.. plugged in the network and its back to square 1.

author: glenenglish
author_rank: Frequent Contributor
timestamp: January 17, 2025, 11:50:37 pm
content: I'm still using vitis-classic also, I dont think vitis-new is ready for prime time, yet. and too much fluff.