Matching High Impedance Probe to 50 Ohm Output - Page 1
Forum section: electronics / rf-microwave

author: ignilux
author_rank: Unknown
timestamp: June 24, 2019, 07:08:02 pm
content: All-I'm currently working on designing a high impedance, low capacitance active buffer probe for troubleshooting RF circuits. The output will be primarily used with my 50 ohm spectrum analyzer, and my design will cater to its Zo. The goal is, of course, to get as much bandwidth as possible, but realistically I'm shooting for a minimum of ~1 to 250 MHz.While there is no shortage of designs out there, the one thing that I don't see mentioned is the impedance matching. I understand the fact that matching impedance 1:1 is for maximizing power, and that high impedance probes are designed to maximize voltage / minimize loading -- that's not what I'm asking about. What I'm mainly concerned with is signal reflections. For instance, in Wolfgang'sBF998-based probe, the high impedance input is fed to one gate of the BF998. I'm assuming there is a mismatch at the gate, which should result in some combination of reflection and absorption. Why doesn't this matter?The primary reason that I ask is to determine trace width for impedance control. My design (see attached) is a bit more classic, with a J310 source follower feeding in to a BFR35 emitter follower. It is an amalgamation of the various circuits I've come across while researching this topic. Impedance in to the JFET gate is 1M || TBD pf, and impedance out to the SMA connector is ~50 ohm. I have no idea what happens in between impedance-wise, nor how to eliminate reflections.What do?

author: Marco
author_rank: Super Contributor
timestamp: June 24, 2019, 08:35:34 pm
content: Quote from: ignilux on June 24, 2019, 07:08:02 pmThere is no reflection because there is no transmission line. Here you need to use the parallel to the everything is a transmission line saying, everything is lumped elements.

author: ignilux
author_rank: Unknown
timestamp: June 24, 2019, 10:06:30 pm
content: How do you decide? I have a pair of conductors carrying AC of a sufficiently high frequency to allow the consideration of the wave nature of the electron. Why, in this particular case is it not important?

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: June 25, 2019, 10:44:05 am
content: Quote from: Marco on June 24, 2019, 08:35:34 pmThere is always a transmission line. But the trick here is to keep it so short, that you don't notice the impacts.The thing is: the OP is looking at a frequency of 250 MHz. That is a wavelength on the order of a meter. Even with the slower wave velocity on an FR4 board, you will still have a wavelength around 50 cm. So if you get that buffer say 5 mm from the probe tips, you already have only 1/100th of a wavelenght. So it is very unlikely to have a big impact.Think of it this way: Reflections are an issue because they make a different impedance appear. The cause of this difference in impedance is the fact that your reflected wave is out of phase. As a result, it is kinda like your transmission line is 'fighting' your incoming wave - if it is 180 degrees out of phase, whenever it tries to increase the voltage, that reflected wave will try to lower it, and you end up with no voltage at all (or, you guessed it, a short).In the case of this probe, the length of that transmission line is so short that the reflection has almost no phase shift. As a result it looks like a high impedance, and you can ignore the probe.Try to keep inductance low - low loop area. Your gate will look like a capacitor, so your probe will look like a capacitor at high frequencies.

author: IconicPCB
author_rank: Super Contributor
timestamp: June 25, 2019, 11:13:39 am
content: do a bit of googling for complimentary pair topologies... N channel fet with PNP transistor in feedback topology.This is to say colector circuit feeding back to the source of the FET. A kind of bootstrap topology whihc will increase input impedance of the FET and give you a much broader band buffer.

author: Marco
author_rank: Super Contributor
timestamp: June 25, 2019, 06:56:53 pm
content: Quote from: ignilux on June 24, 2019, 10:06:30 pmGenerally size, if the size of a transmission line gets short enough you can just approximate it as a LCR circuit ... when it gets large you can model as an infinite series of LCR circuits or use the transmission line approximation. It's all just abstractions of the underlying physics in the end. Use what's convenient and close nuff.Quote from: IconicPCB on June 25, 2019, 11:13:39 amIt improves the gate source capacitance, but it makes it harder to improve the gate drain capacitance. Because if you want to bootstrap the drain the signal now has to go through three transistors worth of phase shifts.Great for audio, but can you really make it work for RF?You can achieve almost the same impedance improving effect by simply adding a NPN emitter follower behind the JFET ... but then you can still bootstrap the drain without going through 3 transistors and without needing ancient relatively slow RF PNPs going out of production.PS. also for Wolfgang's BF998-based probe the impedance of the buffer is less relevant because of the coupling capacitor, which increases the impedance at the cost of increased attenuation.

author: ignilux
author_rank: Unknown
timestamp: June 26, 2019, 12:09:35 am
content: QuoteWoah buddy, my (still unused) strip of 100 MMBTH81 has something to say about that!And the whole idea about the length of the transmission line in comparison to the wavelength of the signal makes total sense, so thanks for explaining that.QuoteI was thinking about this, too. My gut tells me to always keep inductance low no matter what. But considering the fact that capacitance will be the limiting factor, why doesn't inductance counteract it, making a net positive effect? Also along those lines, am I better off with relatively thick or relatively narrow tracks? Right now I'm routing signal at 15 mil and power at 25 mil. Ground fill on top and bottom layers, except where the probe tips attach. Board edge hugs the probe attachment pads in hopes of reducing capacitance. It might be worth noting that the 0p5 cap in my schematic is going to be two copper rectangles-- one per layer. I calculated the right size based on ε*A/d, and oversized it a bit so I can trim as needed.

author: David Hess
author_rank: Super Contributor
timestamp: June 26, 2019, 02:11:29 am
content: Quote from: ignilux on June 24, 2019, 07:08:02 pmSo you need an impedance buffer. Or just buy an active probe.QuoteIt does not matter for three reasons:1. In an active probe, the distance between the input and buffer is insignificant.2. If the distance is significant, then a passive attenuation head is used which serves the same purpose as the attenuator and transmission like in a high impedance passive probe. The cable in a passive high impedance probe is *not* 1 megohm impedance cable.3. The low capacitance of the input device and construction means series inductance has less of an effect. This can be seen in old oscilloscope construction where the connection between the BNC and input circuits is just a wire hanging in the air.QuoteThe only thing you need to do, besides using RF construction techniques, is to minimize capacitance to all high impedance nodes which includes everything adjacent to the gate of the J310 and probably the source as well. Exclude the ground plane from these areas.Take a look at the design of the Tektronix P6202A (and P6201 to some extent) active probe which is fully documented. The J310 should get you to 250MHz but I would include the source resistors and configuration shown in the P6202A schematic because operating at Vgs=0 is not going to be feasible with a J310. You might get away with that on a J309 but I would still include the source resistor.

author: Marco
author_rank: Super Contributor
timestamp: June 26, 2019, 12:48:49 pm
content: Quote from: ignilux on June 26, 2019, 12:09:35 amInductive peaking can work and it's probably helping Wolfgang's circuit somewhat, but assuming the capacitance of the buffer itself is low (sub pF) it's going to be dependent on the parasitic capacitance in how it affects the response.You want the track for the signal probe pin as wide as possible for low inductance but at the same time as narrow as possible for parasitic capacitance ... there's no right answer, just copy Wolfgang's design. It seems to work well enough.

author: ignilux
author_rank: Unknown
timestamp: June 28, 2019, 09:20:42 pm
content: Quote from: David Hess on June 26, 2019, 02:11:29 amThat's inline with how I had done the preliminary routing-- no ground plane on top nor bottom on probe-side of the JFET. Board edge hugs the probe pads, and there is nothing but air between them.Quote from: David Hess on June 26, 2019, 02:11:29 amAre you referring to R17 fromthis schematic? Switching to a bipolar supply and adding a second FET is do-able, but not ideal. If only I could find a connector for the probe power output (+15V / GND / -12.6V) on the 8568B thatdoesn'tcost an exorbitant sum.Quote from: Marco on June 26, 2019, 12:48:49 pmIf I had a dollar for every time that was the case...Thanks gents, I think I'll ultimately build some version of the proposed probe, plus a copy of Wolfgang's design. I have 25 BF998's hanging around somewhere.

author: David Hess
author_rank: Super Contributor
timestamp: June 29, 2019, 07:29:00 am
content: Quote from: ignilux on June 28, 2019, 09:20:42 pmThe second JFET is operating as a temperature compensated current sink load so the zero voltage does not shift with temperature. The 27 ohm source resistor in the first JFET allows operating at a more reasonable channel current while maintaining zero offset voltage between input and output. Sometimes a diode is used in series with the source as well or alone. The matching 27 ohm resistor in the second JFET makes them operate with the same Vgs.That may be the best way to do it for precision and performance but it is not the only way. A bipolar transistor current sink load could also be used with feedback to control the DC offset but this requires a DC connection to the input which will add to the input capacitance. Or the bipolar current could be fixed at the expense of more offset drive with temperature which may be acceptable.I would not even try to get away from using a bipolar supply.