another DIY AD9951 DDS - Page 1
Forum section: electronics / projects

author: minion
author_rank: Contributor
timestamp: January 19, 2017, 01:22:53 pm
content: Hey guys!I am planning to build my own DIY DDS signal generator. I know, a lot of topics are already opened on this forum regarding DDS and a read pretty much all of them.SPECS:Sine freq: 0Hz – 30MHz (50MHz ?)10V pp into 50Ohm load+- 5V DC offset adjustmentFor signal generation, I am planning to use AD9951 DDS chip. It is 400Msps 14bit DDS chip. On both outputs I will put 100Ohm resistor, so with 10mA of current, I will have 1Vpp signal. It will be followed by 270MHz @G=1, differential amplifier. Because it is used in G=3 configuration, I think it is reasonable to expect at least 50MHz bandwidth.Following that will be low passband ripple, 9. order Chebyshev filter. After that, I am planning to add switchable (enabled/disabled) -20dB pi attenuator. Filter and attenuator both have 250Ohm in out impedance.Following that are two parallel THS3091 current feedback amplifier @ G=6.8. I paralleled them so I can expect lower THD.On the signal line, I am also injecting DC offset. I am not really sure if I did it correctly. 1.25V is 0V offset and you can change it from around -2.2 to 2.2, to achieve around +-5VA the end of the signal line, there should be 250 Ohm terminating resistor to ground, but because I have two amplifiers and DC offset circuitry, I multiplied resistors by three, so there are three 750 Ohm resistors. 750||750||750=250. But for PCB layout I don't know hot to properly terminate 250 Ohm line if the signal will be ending on three locations.Other than that, I am attaching LTspice simulation. Spice models for AD8130 and THS3091 exclude signal distortion and noise modeling, so I am not really sure what to expect from final design.In LTspice I am currently simulating DAC via two PWL files, that are controlling current from I1 and I2. I created those PWS files to simulate AD9851 chip, which is worse than AD9951, that I am planning to use. PWL files are outputting 10MHz sine wave with sampling rate of 180MHz and 10bit resolution.All remarks, comment, etc.. are very welcome.tnx

author: awallin
author_rank: Frequent Contributor
timestamp: January 19, 2017, 07:39:48 pm
content: For time-nuts kind of stuff AD9912 and especially AD9914 would be more interesting.. (but harder packages to solder, and probably more expensive).You'd also want an internal OCXO (at e.g. 10 MHz) and a PLL to generate the clock for the DDS, with a possibility of connecting an external 10MHz reference that locks the OCXO with a PLL.From an SNR viewpoint, wouldn't you want the attenuator as late as possible in the chain? (maybe it already is..)Maybe think about a sine-to-square converter on the main signal to provide a "sync" output in addition to the main signal?Do you really need a Chebyshev filter that has pass-band ripple, or would a flatter Butterworth or Bessel be better?Are you making a board with SPI-control - so that everyone can add on their favourite arduino/RPi/whatever controller/UI?

author: minion
author_rank: Contributor
timestamp: January 19, 2017, 08:31:42 pm
content: Yeah, AD9912 and AD9914 ar definitely interesting, but I don't really need that powerful chips. They are also 50€ and 160€ on farnell, while AD9951 is 23€.I was planning on using 20MHz external oscillator and multiply it with PLL by 20 to achieve 400MHz. Would that work ok? How would the accuracy and jitter be? What did you mean with the external reference? Is it possible to calibrate PLL with it or did you mean connecting external reference just when you need higher precision?I think, attenuator already is as late in the chain as possible. After the opamps, there is already the output.Yeah, I am also thinking about creating square signal with a comparator on the output. I would also like to create PWM signal, but I am not really sure how to to it. I was thinking about connecting reference voltage from DAC and sine to the comparator. That way, you kind of get PWM signal, but because sine is not a triangle, changing duty cycle wouldn't be very elegant, especially if you would want very low or very high duty cycle. Do you have any suggestion, maybe?At first, I was planning on using Butterworth filter but later changed for Chebyshev. I liked flat passband response of Butterworth but somehow I become worried about not being efficient enough in stopband.But you might be right. Especially if I will use 400Msps DAC, and signal will be max 50MHz, Butterworth should be enough, right? Maybe even Bessel, and then I can do arbitrary waveform with the same filter. Will simulate it out.I am planning on putting a cheap STM32f103 chip on the board, that will control the DA9951.tnx

author: Kleinstein
author_rank: Super Contributor
timestamp: January 19, 2017, 09:01:50 pm
content: Usually elliptic / Chauer filters are used with DDS. As they provide better stop band suppression and thus getting closer to the theoretical limit. So you could get 30 MHz even from an AD9850 or AD9851. At least having one zero could really help. Having the 1.st amplifier before the filter could cause some problem, as there are still higher frequency components included. To be on the sure side one might have at least some of the filter before the 1 st amplifier, even if this means a differential filter and thus a few more parts.An 1 V_pp amplitude is already quite a lot for the DDS chip - not sure so much voltage is permitted or might cause extra distortion.I am not so sure about the way the DC offset is added: the filter could have a resonance and will not be constant impedance.Switching the attenuator at 200 Ohms could be not as good as having a 50-100 Ohms impedance, especially at higher frequencies. For 30 MHz this might still be good enough. One could have the attenuator right at the output despite of some power wasted. This might need to add the DC offset to the ground side instead of before the amplifier. So a second output could be a problem.Often is second output (e.g. for triggering) is a good idea. It does not have to be high amplitude or square wave. Conversion to square wave would be an option. PWM usually does not need a fine adjustable frequency. So one could generate PWM signals directly from the µC, with digital accuracy but only limited choice of frequencies.Multiplying a frequency with an PLL also multiply the jitter, and there can be additional jitter from the PLL too. So for low jitter, a higher frequency oscillator would be better - no need to run the DDS chip at it's maximum permissible speed, if you don't need it. A little less could ease on the thermal design.

author: minion
author_rank: Contributor
timestamp: January 23, 2017, 09:44:07 pm
content: Hey, thx for the reply!What do you thing about having two filters, that will be switched between with relays? One would then be elliptic, and one linear phase filter. The thing about elliptic filter is, that it has quite big ripple in pass band. If I would want to have smooth response throughout the whole frequency range, I would probably have to fix amplitude control in software.About DAC current, this is written in the datasheet:QuoteI guess, it should be ok, then.I changed DC circuitry a bit and did some simulations (pic attached). Now it is pretty flat (750 Ohm), up until couple 300Hz. For lower frequencies, it goes steeply up and as a result, combined impedance is not 250 Ohm, but goes up to 360 Ohm. As a consequence, signals under 300Hz will have slightly higher amplitude, but I think I can fix that in the software later. Do you think it is OK now?What do you mean by "Switching the attenuator"? Switching it on and off, or just having the attenuator with input and output impedance of 250 Ohm? And why Is it not good? Why would 50-100 be better?I am definitely adding second output for square waves. I am not decided yet on PWM. Probably you are right. I don't really need 10MHz PWM signal and can generate it with uC.About jitter and PLL, I will definitely keep that in mind and will probably use higher frequency oscillator.tnx

author: Kleinstein
author_rank: Super Contributor
timestamp: January 23, 2017, 10:06:11 pm
content: An elliptic filter should not have that much pass band ripple, it has quite some stop band ripple, but one usually does not care. With such a fast DDS chip (capable of about 150 MHz output) and only using frequencies up to 30 MHz, the filter is not that critical. However it depends on the actual clock frequency used.So I see no need to switch the filter - this might be a good idea for one of the DDS chips that also generate a triangle, but not for pure sine generation.I am not so sure about the impedance of the filter - it might not be constant over all frequencies, and this could have an influence on the attenuator.With a 100 Ohms resistor at the DAC output a 10 mA current would give up to 1 V above AVDD - that is outside the 0.5 V limit cited.Even if not made for RF and thus controlled impedance, usual impedance for tracks and the relays is more like 30-150 Ohms. A 250 Ohms impedance would need a rather special design. So preferred impedance for RF is more like 30-120 Ohms. As 30 MHz is not that high, this may not really matter. I understand the use of a higher impedance, as this needs less power at a given voltage.

author: eeFearless
author_rank: Contributor
timestamp: January 24, 2017, 04:18:52 am
content: Quote from: minion on January 19, 2017, 01:22:53 pmIs distortion in amplifiers uncorrelated?SNR due to uncorrelated noise in amplifiers can be effectively improved by paralleling amps.But, I'm not so sure that the same can be said for distortion.From a SNR point of view, I doubt there is a benefit to paralleling the amps, because you're not going to be amplifying something like a mic level signal, and the noise will be set earlier in the signal chain.I think ...

author: eeFearless
author_rank: Contributor
timestamp: January 24, 2017, 04:28:52 am
content: If you are really concerned about distortion in the amp, then go full differential, to reduce even order harmonics.

author: minion
author_rank: Contributor
timestamp: January 25, 2017, 08:24:12 pm
content: @KleinsteinFilter switching would be exclusively for the arbitrary waveforms, but I will probably not implement it. At least not in the first revision.Oh, tnx. I somehow miscalculated output voltage of the DAC. I will change it to 50 Ohm, so voltage is within +-0.5V of AVDD.Yes, I was trying to spare the AD8130 a little, so I used higher impedance. In the first revision, I will probably use 250 or 150 Ohm and then go on fro there.@eeFearlessI saw load sharing configuration in this application note from TI:http://www.ti.com/lit/an/sboa127/sboa127.pdfIt is meant for larger signals, where output drive of the opamp is at its limits. Because I want output swing into 50 Ohm from +5V to -5V, that is +10V to -10V on the output of the amplifier, so paralleling should help. Picture on page 10 shows clear improvement of the output voltage.Other than that, I don't think I need full differential amps.

author: eeFearless
author_rank: Contributor
timestamp: January 26, 2017, 01:04:50 am
content: Thanks for that app note ...