Spikes in spice transient  - Page 1
Forum section: electronics / beginners

author: fabiodl
author_rank: Frequent Contributor
timestamp: February 26, 2021, 02:33:46 pm
content: I am trying to simulate a DC removal circuit. I tried two versions, a transistor based one and a comparator based one.I use kicad + ngspice. I attach the schematic and the simulation result. There's a spike in the output, which I do not understand where it originates from. I would imagine numerical errors, but the conditions I used are time=1E-2 s and time step 1E-8s. I tried varying the time step, but I still get those overshoots.Do you think the real circuit will have the same spikes? Am I doing something dumb in the simulation ?

author: Capernicus
author_rank: Frequent Contributor
timestamp: February 26, 2021, 02:49:03 pm
content: Isnt it the capacitor making an LC oscillator with the wire inductance? the one at the bottom has more ring because there is less resistance dampening it.In the top one it seems to be the loop through the base, cause its where the lowest value resistor is.But, I actually dont know what im talking about yet, so I could be wrong.I need more experience...

author: PKTKS
author_rank: Super Contributor
timestamp: February 26, 2021, 05:00:49 pm
content: ... export your spice netlist and attach here...it may be checked properlyPaul

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 26, 2021, 05:31:58 pm
content: Consider the magnitude, and effect, of a capacitor from base to collector. Also, what value is that capacitance anyway, does the datasheet say anything--?The comparator, no friggin' idea. No model I'm aware of should do that, but who knows. If it's the same kind of thing (capacitance between pins), it could do that.Also, zoom in and see what it looks like. If it's ping-ponging every other timestep (graph looks triangular), it's probably just numerical instability; try adjusting TRTOL, reducing RELTOL, adjusting maximum timestep, or using GEAR 2 or higher integration. (I don't know about Ngspice specifically, but the traditional TRAP integration of 3f5 SPICE tends to do this.)Quote from: Capernicus on February 26, 2021, 02:49:03 pmNah, there's no stray inductance in SPICE. I mean, who knows what the symbols are representing, they could be hiding any kind of model within -- but, assuming the basic (ideal) case, yeah.All the more reason to,Quote from: PKTKS on February 26, 2021, 05:00:49 pm^^^Tim

author: twospoons
author_rank: Frequent Contributor
timestamp: February 26, 2021, 10:05:35 pm
content: What is the rise and fall time specified on V2? Think about what T3sl4co1l said about base-collector capacitance wrt the rise and fall times ( ie frequency). You have V2 -> capacitor -> resistor -> base|collector capacitance -> resistor -> DC supply. Do you see why you might get a spike on the collector?Another clue - run an AC analysis and see what you find.BTW, I always use GEAR integration for transient sims, and usually run a pretty small max timestep. There seems to be fewer numerical issues this way, though it does run slower.

author: Manul
author_rank: Super Contributor
timestamp: February 26, 2021, 11:04:22 pm
content: What are rise and fall times of the input signal? If it is something insane like 1ns, then try to increase to something like 50ns. This seems like high frequencies having fun with parasitic capacitancies.

author: StillTrying
author_rank: Super Contributor
timestamp: February 27, 2021, 12:05:55 am
content: Using the schem in the 1st post the spikes are smaller in LT, ~0.12V and ~45ns wide, which seems about right.

author: fabiodl
author_rank: Frequent Contributor
timestamp: February 27, 2021, 04:56:58 am
content: Thank you everybody. I attach the spice netlist.Quote from: T3sl4co1l on February 26, 2021, 05:31:58 pmAs for the transistor version, simulation numerical errors aside, this is the reason!I am new to ngspice as well, I will try looking for the equivalent of these options.Quote from: StillTrying on February 27, 2021, 12:05:55 amAwesome, thank you! Your simulation confirms the hypothesis that the spike is there, but the magnitude is off!Quote from: Manul on February 26, 2021, 11:04:22 pm0nsI changed it to 50ns but that lead to no change.I verified that a 1n capacitor between B and E brings the overshoot down to 1mv