0.5mm pitch BGA too small to bother with? - Page 1
Forum section: electronics / general

author: ajcrm125
author_rank: Contributor
timestamp: July 20, 2015, 04:22:03 pm
content: I'm working on an FPGA based design and it seems the Xilinx Artix XC7A35T fits my needs perfectly. Only problem is.. it's in a crazy small package (0.5mm pitch and only 1cm x 1cm in size). Can most boardhouses deal with packages this small? Are there any additional concerns/caveats I should have when laying out the PCB?I would love to go QFP and forget BGA entirely so I can assemble at home but it looks like all the devices that have the internal block ram I need in the Spartan 3 or Spartan 6 families are crazy expensive compared to the Artix.Any info is greatly appreciated!-Adam

author: AndyC_772
author_rank: Super Contributor
timestamp: July 20, 2015, 04:58:17 pm
content: Any commercial PCB assembler should be able to handle a 0.5mm pitch BGA. It doesn't require any greater precision from their equipment than a 0.5mm pitch TQFP, and they've been around for years.One potential issue is the aspect ratio that your PCB vendor can achieve, ie. the ratio of board thickness to via diameter. If you need to get vias in between the BGA balls, they can end up having to be very small in diameter, and there's a limit to what can be reliably plated. Talk to your PCB vendor and ask them what design rules they'd recommend.

author: ajcrm125
author_rank: Contributor
timestamp: July 20, 2015, 05:04:12 pm
content: Awesome thanks for the info. What about PCB fab from home via a reflow oven etc. Is that out of the question with something this small?

author: AndyC_772
author_rank: Super Contributor
timestamp: July 20, 2015, 05:12:33 pm
content: I'd think carefully about the economics here. If you're looking to have just one or two boards built, then the cost of the device is neither here nor there compared to the tooling charges you'll incur, so IMHO there's no benefit to using a cheap component.If you want to save the tooling costs and make the board yourself, pick whatever device you can be sure to solder reliably.How will you escape the device if you're making your own PCB? Without plated vias you're limited to just the outer balls of the device, or the outer 2 rows if you can get a track through between adjacent balls. That's seriously fine geometry for a home setup, and I wouldn't even bother trying.

author: Berni
author_rank: Super Contributor
timestamp: July 20, 2015, 05:14:34 pm
content: Should be no problem for a PCB house to assemble, but doing it at home is likely going to be really hard. There is a company that sells adhesive kapton stencils for BGAs where the stencil it left in there between the pcb and chip. Helps with alignment and makes shorts a lot less likely. Without that you probably need quite fancy equipment to do it reliably.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 20, 2015, 05:47:02 pm
content: You can't do traditional 18/8 mil vias with a dogbone pattern. You must use via-in-pad. This can be bad for soldering. Tracks between pads are also rather tight, though I think offhand a 5/5 rule should still work? For more than two rows in from the side, obviously, you'll still need multilayer construction.Parts like that are intended for buried, blind and filled via construction. The kind of thing cell phones are made of. Via-in-pad doesn't matter, because the vias are solid copper and don't obstruct soldering. It's not cheap to get protos of that construction and pitch. As far as I know (I haven't needed it yet).Tim

author: ajcrm125
author_rank: Contributor
timestamp: July 20, 2015, 05:58:20 pm
content: Yeah my plan was to just use the first 2 outer rows as I really only need about 1/2 the I/O. Other than that... that particular package has a vacant ring inside so I'm thinking I should be able to use vias to get to the 3rd row if needed?Oh.. did I mention I'm looking to do 2 layer?I do plan on making a hundred or so of these at least, which is why I'm trying to be aware of the costs etc.

author: ajcrm125
author_rank: Contributor
timestamp: July 20, 2015, 06:00:36 pm
content: And just to clarify.. I'm not looking to make the PCBs myself.. just the assembly. If it's not worth my time etc then I'll just have the whole thing assembled or perhaps just the BGA mounting.

author: ataradov
author_rank: Super Contributor
timestamp: July 20, 2015, 06:04:56 pm
content: (Big) FPGAs and two layer boards is a highly risky area. If you also will be running this at any significant frequency (> 10 MHz) be prepared to do many iterations of the board and have equipment to catch all sorts of EMI problems.

author: FrankBuss
author_rank: Unknown
timestamp: July 20, 2015, 06:42:22 pm
content: Do you really need that much block RAM? If 70 ns access time is fast enough, you could use a$5 2 MB SRAMwith 16 bit databus. It's very easy to use SRAM from a FPGA and routing is not much of a problem for 70 ns (more difficult to use DDR RAM). And you can get the FPGA and the RAM both in easy to solder packages (TQFP and TSOP). The cost of the FPGA and the external RAM is lower than a big FPGA with lots of block RAM.If you can talk about what you want to design, people can give better advises. There are cheap modules with FPGA and fast DDR RAM, which you can use in your design without worrying about designing your own board. 2 layers is nearly impossible for compact and complex high speed designs, because you should have a good dedicated ground plane and maybe a dedicated supply voltage plane.

author: codeboy2k
author_rank: Super Contributor
timestamp: July 20, 2015, 07:07:01 pm
content: Quote from: T3sl4co1l on July 20, 2015, 05:47:02 pmNope. 3/3 only. If you did use a 5 mil track you would only have 2.4 mil spacing which could work but might be tight.The pads are 500um pitch, the balls are 300um and will need 250um NSMD pads (that's about 10 mil pads). That leaves 250um (10 mils) pad-to-pad spacing. Divided by 3 (space/track/space) yields 83.3um which is about 3.2 mils, so 3/3 spacing is good. Also, there is room for a single 250um (10 mil) via between 4 pads (dog-bone style), and it would have to be laser drilled at 4 mils, leaving a 3 mil annular ring.So we have 10 mil pads, 10 mil vias and 4 mil drill. That's what I would do if I had to do it and had a very dense package.However, this CP236 package has some room in the middle, so you might get away with doing this on just 2 layers and a cheap board house, but you need to find a house that can do at least 3/3 spacing so you can route between the pads to get at the inner rows. Depending on how fast you are running external to the FPGA, and how much I/O you are actually using, you might get away with it on just 2 layers. If needed, some inner row pads can be routed into the large space and can use larger vias there. However, anything high-speed off the FPGA will give you trouble on 2 layers, and like everyone else, I recommend 4 layers at least.As an aside: OSH Park only claims 5/5, but users have been able to do 3/3 reliably, but they don't guarantee it. For 2 layer boards, the smallest drill size is 13 mil, with a 7 mil annular ring. That means they want a 27 mil via. For 4 layer boards, the smallest drill size is 10 mil, with a 4 mil annular ring (that's an 18 mil via). You might be able to get a relatively inexpensive 2 or 4 layer board from them.Also, @FrankBuss's suggestion to consider external SRAM is a valid point and worth looking into.

author: ajcrm125
author_rank: Contributor
timestamp: July 20, 2015, 07:47:29 pm
content: Quote from: FrankBuss on July 20, 2015, 06:42:22 pmGood point... I'd appreciate any insight from you guys. Do you think it makes sense to describe what I'm trying to do here or start a new thread?

author: ataradov
author_rank: Super Contributor
timestamp: July 20, 2015, 07:48:35 pm
content: Here would be better, IMO.

author: wraper
author_rank: Unknown
timestamp: July 20, 2015, 08:01:06 pm
content: Quote from: ajcrm125 on July 20, 2015, 04:22:03 pmI don't see why it cannot be assembled at home. Have soldered 0.4 mm pitch package on package BGAs (repaired things). Have rebelled them too. Unless doing any serious amount where you are concerned about reliability (needs x-ray inspection anyway) I don't see it being much more difficult than QFP. the only issue would be if you have not reflow oven or hot air, but then producing such PCB and paying to assembly house will cost more than hot air station anyway.

author: ajcrm125
author_rank: Contributor
timestamp: July 20, 2015, 08:33:45 pm
content: So here's the plan... I've been working for quite some time on a modern replacement to Atari's Pole Position Arcade PCB.(http://ppclone.blogspot.com)Several guys have done modern FPGA replacements for classic arcade games (http://www.arcadeshop.com/mylstar_jamma_pcb/mylstar_pcb_big.jpg) so nothing new there... the problem is that compared to other arcade games, the Pole Position design is rather large with multiple processors and moreso.. uses a ton of ROM and RAM.Most games have maybe 30-50kBytes of ROM data alone... Pole Position has 193k or so.I've been prototyping on MikeJ's FPGA Arcade Replay board (www.fpgaarcade.com) where's he's using an older Spartan-3 XC3S1600E and external SRAM and my plan 'was' to do the same, but for all the internal blocks that have their own central ROM/RAM I would have to create an arbiter so that they could all share the single external SRAM.So I started down that path until for whatever reason I decided to get some pricing on the XC3S1600E that Mike uses: Digikey lists it as anywhere from $90 to $135.Then I stumbled on the Artix 7 series: plenty of logic cells and more than enough internal block RAM for everything (no extrenal SRAM needed) for only $40??That's when I jumped ship on the Spartan-3 and went for the Artix. The only problem is that the 7 series FPGAs only come in a BGA package. As far as speed goes, this is a pretty low-speed design: 24Mhz or so.While I've done PCBs in my home lab, I'm not a PCB guy.. I'm a logic designer and I do GPU design for a living. And I don't plan on fabbing these at home.. these will be sent out to a boardhouse and (hopefully) assembled here in the home lab, unless it ends up taking too much time for me to assemble them at home or perhaps it makes financial sense. In that case I'll just have them built for me as well.So I'm open to any suggestions you guys may have!

author: ataradov
author_rank: Super Contributor
timestamp: July 20, 2015, 10:03:22 pm
content: It might be easier to get a beefy MCU (Cortex-M7) and do software emulation. And possibly use very small FPGA for the display controller. This will be way more cost-efficient, but will turn mostly into software project.

author: ajcrm125
author_rank: Contributor
timestamp: July 20, 2015, 10:49:26 pm
content: Yeah emulation is not an option here. The target audience wants authentic hardware implementation.

author: ataradov
author_rank: Super Contributor
timestamp: July 20, 2015, 10:54:17 pm
content: A fair point. Then getting back to the arbiter - presumably original MCU architecture did not have a lot of types of memory and arbiter would be a part of the "authentic hardware"? You may need to load the contents into emulated ROM on startup, but after that everything will look just like the real system.

author: poorchava
author_rank: Super Contributor
timestamp: July 20, 2015, 11:00:19 pm
content: I recall reading some app note from TI regarding design rules for their 0.5mm pitch BGAs. Recommended dimensions were like 3.8mils trace width and clearance. Not every board house will fabricate that. Also - microvias might be necessary which ain't cheap.For my own purposes I consider 0.8mm BGAs the finest pitch to be used unless somebody puts serious money into the project.Sent from my HTC One M8s using Tapatalk

author: ajcrm125
author_rank: Contributor
timestamp: July 20, 2015, 11:08:30 pm
content: Quote from: ataradov on July 20, 2015, 10:54:17 pmActually no.. Remember this game is from the 80's.  Multiple ROM and RAM all the place across 2 massive PCBs. But yes, if i do have to go with the arbiter then i would preload the external RAM with ROM images from an SD card.

author: ataradov
author_rank: Super Contributor
timestamp: July 20, 2015, 11:27:29 pm
content: Yes, but the microcontroller itself (what it is, BTW?) has a limited number number of pins, and usually there is only one external bus.Suppose there is two buses for program and data, then just put two smaller SRAM chips.

author: ajcrm125
author_rank: Contributor
timestamp: July 21, 2015, 12:02:33 am
content: Quote from: ataradov on July 20, 2015, 11:27:29 pmThe design has a Z80 core, 2 Z8002 cores and a bunch of proprietary microcontrollers synthesized in the fpga. There's an external micro but it's just to program the fpga and access the SD card.

author: ataradov
author_rank: Super Contributor
timestamp: July 21, 2015, 12:10:02 am
content: I meant microcontroller in the design that is being replicated. So it are two Z80s, which means that there are at most two external buses going out. They may have a lot of stuff connected to them, but in the end, I don't see a problem doing cycle accurate implementation with two external SRAM chips.With FPGA you can run at higher speed and get away with one SRAM chip.

author: ajcrm125
author_rank: Contributor
timestamp: July 21, 2015, 01:25:55 am
content: The z80 has it's own dedicated rom and ram, the 2 z8002s each have dedicated rom and ram, then there's the car sprite logic, signs, road, background, characters, etc each with their own rom and ram and running at different frequencies. Not to mention the sound hardware (more rom and ram). All in all there's almost a dozen clients that need access to the external memory I believe.Sent from my cm_tenderloin using Tapatalk

author: ataradov
author_rank: Super Contributor
timestamp: July 21, 2015, 01:55:21 am
content: Then you may be stuck with more complex FPGAs, or a few of less complex. It is hard to tell without actually looking at the required hardware.

author: FrankBuss
author_rank: Unknown
timestamp: July 21, 2015, 05:56:08 am
content: You can use more than one external SRAM in parallel. For 16 bit 2 MB you need 21 address lines, 16 data lines, and 3 control lines (2, if CE is always on), so 40 lines per 2 MB chip. There are 240 QFP pin FPGAs like an old Cyclone II, which is sufficient for your project, with 142 usable IOs. 3 SRAM chips would be no problem for it and you would still have 22 IOs for parallel video output (VGA would be the simplest way, 4 bit R2R per color component) and for buttons, LEDs etc. This would simplify the design, because you could use one SRAM for the Z80 and z8002s, and another one or two for the graphics RAMs, which might need to be faster so that you can't share it with the CPU RAMs. And it can be done with a 2 layer board and soldering is no problem.A general purpose FPGA board with 3 x 2 MB SRAMs, 16 bit data bus, could be useful for other projects as well.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 21, 2015, 07:00:28 am
content: Yeah, guessing you'll spend more on the tight spec PCBs. Go with the easier FPGA.Tim

author: ajcrm125
author_rank: Contributor
timestamp: July 23, 2015, 03:29:36 pm
content: I came across this video of Dave himself pulling this off with a 0.4mm pitch BGA on a 2-layer board.I guess it's not that crazy??

author: exmadscientist
author_rank: Frequent Contributor
timestamp: July 24, 2015, 06:14:59 am
content: It seems to me that you would probably be best served by moving up to the FTG256 package. Its ball pitch is 1.0mm, which is alotmore forgiving. Particularly if you only need a modest number of external I/Os, you should be able to get away with a 4-layer board and 5/5 design rules + 18/10 vias (as you get with, for example, OSH Park's 4-layer service).Dave is away to get away with 2 layers because the device in that video istiny(only 36 pins!) and he uses 4/4 design rules. Trying to do a 2-layer 24MHz design with an Artix-7 is just asking for pain. 4-layer boards are relatively affordable these days and you'll save more in development time than the boards end up costing you.You also may run into trouble with running out of memory on the XC7A35T. 193kB is getting pretty close to its maximum capacity of about 200kB, and you can easily lose several BRAMs due to the FPGA's restrictions. You might have to step up to the XC7A50T. Fortunately it isn't too much pricier and comes in the same packages, so it's a drop-in replacement.

author: ajcrm125
author_rank: Contributor
timestamp: July 24, 2015, 02:12:50 pm
content: Quote from: exmadscientist on July 24, 2015, 06:14:59 amAll very good points. I guess I was just afraid of having to go the 4-layer route due to pricing. I was just eye-balling some boardhouse prices and it seems going from 2-layer to 4-layer will double or triple the board price. But if I order say 100 PCBs or so (which will be the case) perhaps the delta is smaller?

author: Korken
author_rank: Regular Contributor
timestamp: July 25, 2015, 12:41:55 pm
content: A quick search on pcbshopper.com with 5x5 cm, ENIG and 100 boards gave 90 USD total for 2 layers and 140 USD total for 4 layers.This gives some feel for it, about 50% more for a 4 layer board.

author: MagicSmoker
author_rank: Super Contributor
timestamp: August 02, 2015, 04:24:31 pm
content: Quote from: ajcrm125 on July 24, 2015, 02:12:50 pmThe only time it makes sense to (attempt to) go with 2 layer on a design like this is when the product is both cost sensitive and will be made in relatively high volumes (greater than 1k, at least). It will be *much* harder to lay out a board with a 0.5mm pitch BGA if constrained to 2 layers (indeed, it might be impossible) and the time you will spend ripping up and retrying routes and the time you will spend debugging noise problems because you can't have a proper ground plane will absolutely and totally swallow the extra cost of going with a 4 layer board from the beginning.Exceptions: you are doing this as a hobby and you are a masochist.