Turn off name mangling during Vivado behavioural simulation - Page 1
Forum section: electronics / general

author: tom66
author_rank: Super Contributor
timestamp: July 12, 2022, 02:33:28 pm
content: Is there a way to prevent Vivado from optimising the net names into a near-undebuggable mess of replicated and inverted signals when running a Behavioural Simulation with IP cores?I found a few tips on the Xilinx forum but none work here, wondering if anyone else has encountered this. The test bench otherwise works but it's so hard to see what is happening.I am using Vivado 2020.1.Thanks

author: hamster_nz
author_rank: Super Contributor
timestamp: July 12, 2022, 11:06:06 pm
content: IP cores are opaque, and usually they are a mess of script-generated code.In general you debug them at their outer interface, by checking that you are using them correctly.

author: tom66
author_rank: Super Contributor
timestamp: July 13, 2022, 07:37:50 am
content: Ah - the problem is they're my IP cores!I figured it out in the end, I needed to run the build with 'out of context' disabled. I think with 'out of context' enabled it means Vivado pre-synthesises the cores and only changes them if anything material changes on the other end. That meant it wasn't obeying my simulator settings and while the behaviour of the cores would have been correct, it had optimised inall my bugsso I could not see any state machine transitions etc.

author: asmi
author_rank: Super Contributor
timestamp: July 13, 2022, 12:22:28 pm
content: Quote from: tom66 on July 12, 2022, 02:33:28 pmAre you running post-synthesis behavioral simulations? Do you have a specific reason for doing so, as opposed to "normal" (pre-synth) behavioral sims?

author: BrianHG
author_rank: Super Contributor
timestamp: July 13, 2022, 01:35:12 pm
content: In the past, when using Quartus, the only reason for post-synth sims would be to observe timing meta-stability behavior of my combinational logic. But, in the end, it always comes down to something I could have engineered better with full synchronous logic as well as when I solely develop within a sim dedicated platform like Modelsim, development productivity has increased 10 fold. Porting my functions to Quartus is now the last thing I do and I expect to never engineer at the post synth level ever again.

author: tom66
author_rank: Super Contributor
timestamp: July 13, 2022, 01:36:55 pm
content: Quote from: asmi on July 13, 2022, 12:22:28 pmThis 'issue' was happening in behavioural simulation, prior to any synthesis (as I had thought!), hence why I was surprised at the mangle-ment of net names.

author: asmi
author_rank: Super Contributor
timestamp: July 13, 2022, 05:26:41 pm
content: Quote from: tom66 on July 13, 2022, 01:36:55 pmThat is odd, never seen it do anything like that. Have you tried asking on Xilinx forums?

author: tom66
author_rank: Super Contributor
timestamp: July 13, 2022, 07:07:20 pm
content: No. It's generally difficult to get answers on there unfortunately, so I haven't bothered this time.I'll see if the bug (if it is one) is fixed in 2022.1, as I'm currently running 2020.1 for this.

author: asmi
author_rank: Super Contributor
timestamp: July 13, 2022, 08:15:08 pm
content: Quote from: tom66 on July 13, 2022, 07:07:20 pmActually it has been quite the opposide for me. I always got responses, some were more helpful than others, but at least they pointed me into a right direction.