[Zynq] transferring data between CPU cores and fabric without too much hassle - Page 1
Forum section: electronics / general

author: Digitalio
author_rank: Contributor
timestamp: September 29, 2020, 09:49:19 pm
content: I need to transfer blocks of data (up to several megabytes each) between CPU core and FPGA fabric, bidirectionally. Could anyone point to me any good tutorials / books / samples / etc?

author: colorado.rob
author_rank: Frequent Contributor
timestamp: September 30, 2020, 12:41:32 pm
content: Have you read The Zynq Book yet?

author: Digitalio
author_rank: Contributor
timestamp: September 30, 2020, 04:19:28 pm
content: Quote from: colorado.rob on September 30, 2020, 12:41:32 pmIn process.

author: Digitalio
author_rank: Contributor
timestamp: September 30, 2020, 05:05:16 pm
content: It seems that I need AXI, right?

author: hamster_nz
author_rank: Super Contributor
timestamp: September 30, 2020, 10:57:50 pm
content: What does your programming interfaces look like? It really depends on how you intend to use it.For example you could do it with a memory window, in which case you hang your design off of an AXI mastter.or you could use two FIFOs, which will need maybe four registers (data + status reg in each direction).Or you could do it using DMA,Or you could use GPIO, like we used to do with the good old EPP printer port in days of yore.Or you could have the fabric talk to the AXI slave interface and read and write the data directly from the DDR, without the CPU being involved.But Adam Taylor's Zynq book is a great start.

author: langwadt
author_rank: Super Contributor
timestamp: September 30, 2020, 11:04:40 pm
content: Quote from: Digitalio on September 30, 2020, 05:05:16 pmyes you will need axi, either make your PL a slave the CPU can write to, or make PL a master than can directly read/write main memory

author: Digitalio
author_rank: Contributor
timestamp: October 04, 2020, 06:24:03 am
content: Quote from: hamster_nz on September 30, 2020, 10:57:50 pmWhat's the best method for sending data of fixed width in both directions on every clock tick?

author: brucehoult
author_rank: Super Contributor
timestamp: October 04, 2020, 07:27:16 am
content: To and from what?No CPU can continuously absorb data arriving on every clock tick. And put it where? There are only a few registers.You can't depend on accessing DRAM every clock because it takes time and because the CPU wants to use it also.Assuming that this is not continuous, forever, you can put the data in SRAM in the FPGA, and provide the CPU with access to this, perhaps by mapping it as a range of addresses, or perhaps by reading from the same address repeatedly, with new data appearing each time.You need to specify much more precisely what it is you are trying to do.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 04, 2020, 10:17:20 am
content: Quote from: Digitalio on October 04, 2020, 06:24:03 amThe best is to not go near the CPU at all.If you seriously want to process a word of data every clock cycle, without hiccups, then you need to do it all in a fixed latency pipeline in the FPGA fabric, and just use the CPU for command and control duties. This is what you would do for a low-latency audio, video or SDR processing pipeline.

author: Digitalio
author_rank: Contributor
timestamp: October 06, 2020, 02:35:26 am
content: Quote from: hamster_nz on October 04, 2020, 10:17:20 amMy ultimate goal is to use Ultra96 for performing calculations on data loaded from SSDs connected via its USB 3 ports and saving the results back. It's not a problem to have some hiccups if it saves me a good deal of time writing the firmware code.

author: Dmeads
author_rank: Regular Contributor
timestamp: October 10, 2020, 12:33:27 am
content: The xilinx axi gpio cores can be instantiated via the block diagram in vivado. The configuration Wizard for them can be enabled for dual channel bidirectional (double click on the instance in the GUI). I use these to move data from the CPU to my RTL code on the FPGA fabric, however I have never done it with the amount of data you are using. I think each channel on the AXI_gpio blocks can be 32 bits?I made a very basic video series on moving data in from io pins, then having it be processed by the FPGA. That processed Data is sent to the Zynq core via AXI_GPIO, further processed, and sent back outside the chip via another AXI_gpio block.maybe it will help you? there are two partspart 1:part 2:give me some feedback if it works

author: lincoln
author_rank: Regular Contributor
timestamp: November 05, 2020, 02:23:00 am
content: Some other axi video that helped me :