AND Gate Delay Circuit - Page 1
Forum section: electronics / beginners

author: FreudianSip
author_rank: Contributor
timestamp: June 23, 2014, 02:15:59 pm
content: Hello all, I'm doing some undergraduate physics research this summer and the grad student that I'm working with told me to come here and tell you all the project that I'm working on to see what you think. The TL;DR is that I'm prototyping a delay circuit using AND gates.The experiment that I'm using this circuit on is a quantum photon detector. I've attached a diagram of the experiment. The physics behind it is probably not as interesting to you all (although I will happily go into detail with it if you'd like!), but essentially it is a coincidence detector: detecting when two photons hit separate detectors at the same time. The way we do this is by delaying one of the signals from a detector a known amount of time, say 19ns, send both signals into a time-to-amplitude converter (TAC), and only accept the pulses coming out with voltage corresponding to a 19ns delay.We have been introducing the delay by sending the signal through coils of cable, but this looks messy and is not easily adjusted. My goal for this summer is to build a delay circuit that sends the signal through an adjustable number of AND gates (with the other input always on). The incoming signal is from a Nuclear Instrumentation Module (NIM) discriminator and is a -720mV negative pulse lasting for 6ns. The pulse will be accepted by a NIM TAC.A diagram of my proposed circuit is attached. Green is the signal going into the + terminal of the comparator and the blue signal is from after the final AND gate. I have to bump the pulse up by~2.2V to get a fast comparator (LT1720) to recognize it and compare it to a 2V reference. I'm still waiting to get the comparator in to test it, but the 74F AND gates are delaying as expected, 2-2.5ns each. So do you all have any thoughts or advice on this experiment? Any roadblocks that you think I'll run into? I'm pretty new to electronics but eager to learn. Please let me know if I should provide additional information. Thank you!

author: jlmoon
author_rank: Unknown
timestamp: June 23, 2014, 02:37:46 pm
content: have you considered using integration techniques instead of relying on silicon logic to establish your delays. Integrators provide much more stability and allow precise control of the delay.There are some pretty good app notes out there (such as with Linear) and numerous others.Best of luck!

author: FreudianSip
author_rank: Contributor
timestamp: June 23, 2014, 02:43:22 pm
content: Quote from: jlmoon on June 23, 2014, 02:37:46 pmIntegration techniques... I have not heard of that but I'll start researching. I'll start at wikipedia and see where it takes me, any other places that are good to learn about integration techniques from? Thank you!

author: Marco
author_rank: Super Contributor
timestamp: June 23, 2014, 02:47:18 pm
content: You just take the TAC circuit and do everything in reverse, on the the trigger you start discharging a capacitor from a given voltage with a constant current and a ZCD generates your delayed pulse.

author: FreudianSip
author_rank: Contributor
timestamp: June 23, 2014, 02:59:36 pm
content: Quote from: Marco on June 23, 2014, 02:47:18 pmI suppose I should clarify: I did not make the time-to-amplitude converter, it is a pre-assembled Nuclear Instrumentation Module, specifically the Ortec 437.http://www.colorado.edu/physics/phys3340/phys3340_sp12/manuals_and_datasheets/Ortec%20437%20Time%20to%20Pulse%20Height%20Converter%20Specs.pdf

author: Marco
author_rank: Super Contributor
timestamp: June 23, 2014, 03:12:39 pm
content: Sorry, I realized it was an existing module a little late ... was just editing my post to explain what I meant.It's not impossible to do this stuff with logic, there areICsfor it. But analogue is more fun

author: jlmoon
author_rank: Unknown
timestamp: June 23, 2014, 03:32:49 pm
content: As I come to think of this, integration / differentiation at those speeds 6 x10-^9 to say 20 x 10-^9 would be a pretty tall order. We're dealing with some really fast sample times here. Have you considered the Propagation delay the LT part is going to introduce? I know back in the 50's 60's .. Tektronix used coaxial cable delay lines in their older scopes for the delay time multiplier functions. I recall quite a bit of conversation on this topic back a few years ago. Dealing in the sub uSec range can be a mind boggling experience..

author: FreudianSip
author_rank: Contributor
timestamp: June 23, 2014, 03:48:35 pm
content: Thanks Marco, I would prefer to use ICs but I will ask my supervisor what he can tell me about analog.Quote from: jlmoon on June 23, 2014, 03:32:49 pmHaha yes it can be quite mind boggling! I have considered the propagation delay of the LT part, the datasheet suggests that it should be 2 or 3ns.

author: Paul Price
author_rank: Super Contributor
timestamp: June 23, 2014, 04:42:24 pm
content: Use a single high speed exclusive-nor ALS or ECL: gate with just a small RC delay on one input to the gate..3mm diam. 75-ohm coax cable is widely used in laptop computers to interface the antennas of wireless networking circuits. To achieve the delays you want would only require a neat spool of wire the diameter the size of a .25 cent US quarter but would be much taller than an US quarter.Maxim precision delay line IC

author: FreudianSip
author_rank: Contributor
timestamp: June 23, 2014, 04:44:26 pm
content: So yea the comparator is introducing some delay.. this is fine and wanted. The next item in line, the and gates, will also add delay. By controlling the number of and gates the amount of delay will be controlled. I want to steer clear of analog just don't want to mess with high speed analog design problems... I think the comparator will pick off my NIM pulse and I will be able to feed the signal through the and gates now I am struggling to find an easy solution to get the NIM pulse back to supply to the TAC unit. I was thinking an opamp into a differential amplifier design using BJT. Does anyone have any suggestions.Also, here is a schematic of the ORTEC 9302 Amplifier Discriminator!!! Circuit PORN!!!! Thanks a lot guys/gals!

author: FreudianSip
author_rank: Contributor
timestamp: June 23, 2014, 04:45:59 pm
content: Quote from: Paul Price on June 23, 2014, 04:42:24 pmHey thanks! I am checking these out now!

author: FreudianSip
author_rank: Contributor
timestamp: June 24, 2014, 09:02:55 pm
content: Hi all, just thought I'd update on where I am with this project. Thanks to the posts from Marco and Paul Price, I think I will use delay line ICs instead of AND gates- a much larger range can be covered that way. The plan is to use two chips, each with 5 equal steps, one with 4ns steps and the other with 20ns steps. I'm thinking I'll use two rotary switches to select the desired steps, giving an adjustable delay from 4ns to 120ns in 4ns increments.What is keeping me busy now is converting the TTL pulse back to an NIM fast negative pulse (~-720mV). I have simulated a circuit that I think will be acceptable (see attached) which I got from the schematic of this NIM/TTL translator module:http://www.ipnl.in2p3.fr/cms/cmsecal/TTL_NIM%20user%20manual_v10.pdfThis works when I have the default transistors in, but once I specify them, the output looks completely different (see second pic). Any ideas as to why this happens would be much appreciated! Thanks.

author: jlmoon
author_rank: Unknown
timestamp: June 24, 2014, 09:19:26 pm
content: Freud,With the junction of R4 & R6 and bottom of C3.. do you have this pulled to -6 volts?JLM

author: FreudianSip
author_rank: Contributor
timestamp: June 24, 2014, 09:26:49 pm
content: Quote from: jlmoon on June 24, 2014, 09:19:26 pmNot quite sure where you're talking about, but I do not have any voltage sources other than +5V... Does that answer your question?

author: jlmoon
author_rank: Unknown
timestamp: June 24, 2014, 09:40:33 pm
content: Well in your sim circuit TTLtoNIM1.. I don't see any way for you to bias those transistors Q1 & Q2, or no dc ground path. Bottom of R4 , R6 need a reference point somewhere >.6v below ground or -5 to -6 volts.. as per the schematic on your TTL to NIM device provided via your link. In summary, the emitters Q1/Q2 have to be lower than ground (R5 point) for them to work right.

author: FreudianSip
author_rank: Contributor
timestamp: June 24, 2014, 09:44:30 pm
content: Does the ground between C2 and C3 count?

author: Marco
author_rank: Super Contributor
timestamp: June 24, 2014, 09:49:37 pm
content: No, you're simply missing an entire power supplyThe bottom of r3-r4-r6-c3 needs to be at -6 Volt.PS. you'll need a fast logic family for the XOR or it will add way too much propagation delay, might need some faster transistors than those 2n5210s as well.

author: jlmoon
author_rank: Unknown
timestamp: June 24, 2014, 09:53:46 pm
content: or somewhere > -.6 volts.. to bias Q1 & Q2. You might want to change this voltage along with your bias divider networks to you liking. Don't know what your output voltage requirements are.say -.7 or -.8 to -x volts

author: FreudianSip
author_rank: Contributor
timestamp: June 24, 2014, 09:55:51 pm
content: Hmmm... Okay, thanks guys! I'll mess around some more with that.

author: eetech00
author_rank: Regular Contributor
timestamp: June 25, 2014, 03:00:26 am
content: Quote from: FreudianSip on June 24, 2014, 09:02:55 pmHiOne thing to be aware of in your simulation is the default setting for the "A1" device. This is an LTspice proprietary behavioral device. Propagation delay and output rise and fall times are 0 by default. They can be set using parameters Td, Tfall and Trise.Also, the NPN and PNP devices are also "Idealized" devices and as such do not behave like a real device by default. When you make a selection to specify a specific device, like "2N5210", the default parameters of the "idealized" device is changed to relect the behavior of a real "2N5210" device.eT

author: Marco
author_rank: Super Contributor
timestamp: June 25, 2014, 10:37:33 am
content: Quote from: FreudianSip on June 24, 2014, 09:44:30 pmThese are decoupling caps BTW, 3.3p is a bit small.

author: amyk
author_rank: Super Contributor
timestamp: June 25, 2014, 12:07:50 pm
content: Quote from: FreudianSip on June 23, 2014, 04:44:26 pmI just want to say that, at the speeds you're working with, the "analogueness" of digital logic starts to become very important too.

author: jlmoon
author_rank: Unknown
timestamp: June 25, 2014, 02:38:52 pm
content: Quote from: amyk on June 25, 2014, 12:07:50 pmI concur, in my earlier post.. I made reference that at these speeds it can be a mind boggling experience. Pretty hard to keep things from becoming "Analog" in nature regarding those really fast rise times.