hybridfree/eevblog-posts huggingface dataset:
Incrementing a counter in Verilog - Page 1
Forum section: electronics / general

author: Miti
author_rank: Super Contributor
timestamp: March 16, 2021, 10:48:27 pm
content: Looking through code examples in Verilog I found multiple ways to increment a counter and I wonder if there's any difference.Code:reg [19:0] counter;// Method 1if (condition) counter <= counter + 1'b1;// Method 2if (condition) counter <= counter + 20'b1;// Method 3if (condition) counter <= counter + 20'd1;// Method 4if (condition) counter <= counter + 1;All seem to work but what are the dangers?Cheers,Miti

author: asmi
author_rank: Super Contributor
timestamp: March 16, 2021, 11:38:34 pm
content: They are equivalent, and will infer the same logic. The only thing is some synthesizers will issue a warning for the last method to the effect of "truncating number", as they treat dimensionless numbers as 32 bit values, and so it will need to chop off higher bits.

author: Miti
author_rank: Super Contributor
timestamp: March 17, 2021, 03:16:41 am
content: Thanks asmi!
Xilinx SliceM LUTs as distributed RAMs: read-first, write-first, or selectable? - Page 1
Forum section: electronics / general

author: SMB784
author_rank: Frequent Contributor
timestamp: March 07, 2021, 12:27:35 am
content: I know that for Xilinx parts, block RAM ports can be specified as read-first or write-first when accessing a shared read/write port. I cant find any information on whether or not the Xilinx SliceM LUT RAMs share this capability with their block RAM cousins. Does anyone know?

author: langwadt
author_rank: Super Contributor
timestamp: March 07, 2021, 12:51:43 am
content: the LUT RAM is async read, I seems to remember an app note describing it as similar to write first on a block RAM

author: SMB784
author_rank: Frequent Contributor
timestamp: March 07, 2021, 01:18:20 am
content: Yeah I read that it's got asynchronus read (with the option for synchronus read if you implement a flipflop on the read port). I am wondering if it is possible to configure these rams as READ FIRST.

author: langwadt
author_rank: Super Contributor
timestamp: March 07, 2021, 01:29:43 am
content: https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/Read-First-mode-in-7-Series-Distributed-Rams/td-p/669251

author: SMB784
author_rank: Frequent Contributor
timestamp: March 07, 2021, 02:16:02 am
content: Quote from: langwadt on March 07, 2021, 01:29:43 amPerfect, thank you! Very helpful!

author: NorthGuy
author_rank: Super Contributor
timestamp: March 07, 2021, 02:49:44 am
content: With distributed RAM, you simply write to the configuration bits of the LUTs.
Can't get ISE10.1 to recognize platform xilinx platform cable on Win10 etc.?? - Page 1
Forum section: electronics / general

author: CaptDon
author_rank: Super Contributor
timestamp: February 24, 2021, 03:46:13 pm
content: Probably seen this question before, ISE10.1 being used with older XP all is working fine for Jtagging old xilinx parts. For newer stuff we had to upgrade to Crapvado and Windows 10. Now the when running ISE10.1 to program the older stuff that Vivado doesn't support the ISE10.1 can no longer find the platform cable. The cable is still good and runs under Vivado. Really Xilinx?Your software is so pathetic that it needs over 9gb of my drive and yet your drivers can no longer operate a platform cable that was operating fine under XP (so I know the problem isn't the computer) With the release of Crapvado suddenly the older small CPLD's and FPGA's are just written off unless I keep an XP machine in my stable? And then the flip side is the old XP machine can't run Vivado without crashing every two minutes. Got to be one of the worst companies and products I've ever dealt with.

author: Bassman59
author_rank: Super Contributor
timestamp: February 25, 2021, 02:41:06 am
content: The short story is that your ancient ISE 10 isn't supported on Windows 10.And the rest of your complaint is nothing new, to be honest. It's been the case for nearly a decade, or whenever ISE 14.7 (the last version) was released.For the record, I installed an Ubuntu virtual machine on my Win10 box, and I run ISE 14.7 in that so I can support a few old designs that have Spartan 3ANs.

author: mac.6
author_rank: Regular Contributor
timestamp: March 02, 2021, 05:32:45 pm
content: old platform cable is know to be broken on windows due to newer jungo USB driver. Try to re-install the one from ISE, there is a Xilinx support post about this.

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: March 02, 2021, 07:19:20 pm
content: While installing the current Vivado, I found that Win7 was no longersupported. That forced me to move to Windows 10. Then I tried toinstall ISE14.7 for my Coolrunners, I found out that the win10 updatefor ISE 14.7 is a virtual machine. I decided not to push my luck too farby running a virtual machine in the Win10 virtual machine that runson Linux. I'll simply keep the old Win7 virtual machine.When they can't run 14.7 under Win10, they very probably cannot run 10.1.Gerhard

author: Gribo
author_rank: Frequent Contributor
timestamp: March 02, 2021, 08:12:43 pm
content: The Jungo driver can be reverted by uninstalling it, and deleting windriver.sys from the system32\drivers folder, then installing the driver that comes with ISE.I have the same situation (need to support Spartan 6 boards), I have a windows 7 machine dedicated to programming them.
Vivado - pin location conflict. Bug? - Page 1
Forum section: electronics / general

author: JohnnyMalaria
author_rank: Super Contributor
timestamp: March 04, 2021, 11:11:32 pm
content: Hi,I'm trying to elaborate/synthesize a design but I'm getting this error:Vivado is complaining that it can't place portmax261_0because the target pin is already assigned toltc2357_spi_ss_io. But that isn't true according to my constraints file.Any ideas???

author: JohnnyMalaria
author_rank: Super Contributor
timestamp: March 05, 2021, 12:04:24 am
content: UPDATE:I found a workaround but I have no idea what was happening. When I tried an implementation, I got a slew of errors about not enough locations remaining and stuff I fundamentally don't understand.I moved some of my ports from one of the Arty Z7's chipkit connectors to one of its Pmod connectors. That allowed me to create a bitstream successfully.(But I don't like not knowing what was wrong)

author: miken
author_rank: Regular Contributor
timestamp: March 05, 2021, 08:28:28 am
content: This sounds too basic to be a bug in Vivado. The assignment must be being made somewhere... check the xdc associated with the Zynq Block.

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 05, 2021, 04:29:51 pm
content: Quote from: miken on March 05, 2021, 08:28:28 amYes, I suspect another definition for the same port (ltc2357_spi_ss_io), either in them xdc file (although I guess the OP already checked that), or in another one. A given project can have multiple xdc files AFAIK so that could be the culprit.
Xilinx SDK - library for regex? - Page 1
Forum section: electronics / general

author: JohnnyMalaria
author_rank: Super Contributor
timestamp: February 26, 2021, 07:49:46 pm
content: Hi,I'm trying to useCode:regex.hin a Zynq application. SDK quite happily finds the file but not the associated library. Two hours of Googling have come up empty. Any ideas what library to add to the linker options?Thanks.
Machx03 I2C programming - Page 1
Forum section: electronics / general

author: bal255
author_rank: Newbie
timestamp: February 19, 2021, 02:19:55 pm
content: Dear users,We are using the Mach0x3-1300L devices in one of our products.According to the datasheets, the I2C interface can be used to program the device. The device's I2C interfaces is connected to an SoC.Using a self written Python script, we are able to program the devices after the nstantiation of the I2C EFB.No, during the manufacturing, we would like to program the Machx03 af part of installation. We can ofcourse use the JTAG interface, which would require manual flashing.I would like to use the I2C interface for this. The problem is, the Machx03 does not show up using I2C detect, so I'm unable to program the device.Does somebody know if there is a special sequence of I2C commands or sequence of dedicated pins we need to toggle?

author: mon2
author_rank: Frequent Contributor
timestamp: February 19, 2021, 08:38:55 pm
content: See if this article helps.https://electronics.stackexchange.com/questions/429201/lattice-machxo3-fpga-configuration-using-i2c

author: bal255
author_rank: Newbie
timestamp: February 22, 2021, 04:13:11 pm
content: NopeI cannot access the I2C interface.Could it be that the blank CPLD's I2C bootloader is blocked by assert/deasserting the PROGRAMN_T, DONE_T or INITN_T?

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 22, 2021, 04:46:46 pm
content: According to the "MachXO3 Programming and Configuration Guide" document:"Start SSPI or I 2 C programming operations after PROGRAMN is deasserted."Note that this is an active-low signal, so asserted means => logic low, and deasserted means => back to logic high.Keeping the PROGRAMN signal low would indeed prevent programming through I2C (or SPI).

author: bal255
author_rank: Newbie
timestamp: February 24, 2021, 08:12:30 am
content: hmm thats no good... I will need to measure it.... (this totally flew over my head)

author: KrudyZ
author_rank: Frequent Contributor
timestamp: February 24, 2021, 04:28:22 pm
content: Have you programmed the part you are testing via JTAG before?If so, then there is a non-zero chance that you disabled I2C programming.It is a setting in the feature row of the device and the "blank" state of the device is different (enabled) from the "default" state that the Lattice tools puts it in (disabled) even if you never make any changes to the feature row yourself...
FMC recommendations for beginner RF - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: March 01, 2021, 06:24:49 am
content: Hello all!Im looking for FMC cards that have both an ADC and DAC on board (if not possible then probably just an ADC) that are $400 US or under.I just want to mess around with some RF stuff in the HF to VHF bands. Probably not gonna do much except for sample and then process the audio, but it would be nice to have a DAC to generate some of my own signals to receive on my spectrum analyzer.Think of my projects like a band-limited SDR sort of. The FMC port on my FPGA is high pin count.I have been looking at some Analog Devices ones but those are just way over budget. Any reccomendations?
MAX 10 common supply voltage banks 1a and 1b for ADC use - Page 1
Forum section: electronics / general

author: Betomane
author_rank: Newbie
timestamp: February 18, 2021, 04:24:02 pm
content: Hi everybody.Currently, I am working on a project with the MAX 10 and ADC use.In the documentation, it says that if using the ADC banks 1a and 1b need to have a common supply voltage.I supplied 3V3 to bank 1a and used a LC filter to supply 3V3 to bank 1b.Can this 3V3 voltage supply still be considered 'common'.I am asking because in the documentation is also commented 'same' supply voltage in another issue.For me, 'same' and 'common' are not the same.Thank you.

author: vstrakh
author_rank: Contributor
timestamp: February 20, 2021, 01:11:33 pm
content: The "pin connection quidelines" pdf tells that "If you enable the ADC feature, connect VCCIO1A and VCCIO1B to 2.5 V."So at least it should not be 3v3.

author: jziegler
author_rank: Newbie
timestamp: February 20, 2021, 01:36:57 pm
content: Quote from: vstrakh on February 20, 2021, 01:11:33 pmThe pin connections guidelines has different sections that are relevant here. It depends on if you are using a single supply or dual supply device. For a single supply device, you connect VCCIO1A and 1b to the same voltage as VCC_ONE, which is 3.3/3.0V.The board that I have designed with a single supply MAX 10 with ADC use a ferrite bead to isolate some of the supply pins. I'd need to check which, but it's based on the diagrams in the pin connection guidelines.

author: vstrakh
author_rank: Contributor
timestamp: February 21, 2021, 08:24:44 am
content: Quote from: jziegler on February 20, 2021, 01:36:57 pmAh, true... I had experience with dual supply devices only, so assumed that's the case.

author: Betomane
author_rank: Newbie
timestamp: February 23, 2021, 10:36:05 am
content: Thank you for the responses.I think it seems to be ok to use a ferrite bead to supple banks 1A and 1B.
DPSK demodulator circuit - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: February 21, 2021, 03:17:04 am
content: InA DPSK demodulator for biomedical application, how to obtain the twoMSBwaveform signals in orange and green colors fromPulse+andPulse-signals ?

author: Foxxz
author_rank: Regular Contributor
timestamp: February 21, 2021, 04:10:45 am
content: It looks like for Pulse- the digital DPSK used as a reset line is an active low which resets a counter. When pulse- sees two pulses the counter outputs a pulse for approximately 1 clock cycle.Pulse+ is the save except that the digital DPSK used as a reset is an active high.

author: promach
author_rank: Frequent Contributor
timestamp: February 21, 2021, 04:20:22 am
content: But it still does not make sense to me why there is only a single green MSB pulse generated ?

author: Foxxz
author_rank: Regular Contributor
timestamp: February 21, 2021, 04:43:03 am
content: Because near the middle of the logic waveform is the only time when there are two green pulses while digital DPSK is high. I'm assuming while the digitial DPSK is held low the counter value stays at 0 and its not an edge detect. Unfortunately the waveform by itself isn't enough to determine this.

author: promach
author_rank: Frequent Contributor
timestamp: February 21, 2021, 06:32:28 am
content: Why would the orangePulse+signal needs active-lowResetsignal ?Why would the greenPulse-signal needs active-highResetsignal ?

author: promach
author_rank: Frequent Contributor
timestamp: February 21, 2021, 01:12:32 pm
content: I think the two RESET signals into the 2-bit counter module might be wrong, they should be swapped with each other.Besides, this circuit is only for demodulating DBPSK if I am not wrong ?What about DQPSK and 8-DPSK ?

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 21, 2021, 04:16:34 pm
content: It looks right to me. Indeed the author here has assumed the two counters had a low-level active reset, which should IMO have been noted with a circle at the reset inputs or something.If you count pulses between reset events, the MSB signals look right. Or I missed something.
Review of FlashLINK JTAG interface - Page 1
Forum section: electronics / general

author: petemate
author_rank: Regular Contributor
timestamp: February 20, 2021, 06:05:45 pm
content: Hi guys, I need JTAG access to some old hardware and found the original software for programming said hardware. Its an ST PSD4235G2V, in case anyone is wondering.Anyway, the old software supports a FlashLINK JTAG interface, which is really simple to make. So I copied the design and would like your inputs on the few changes I have made.There are two versions of the old design:https://media.digikey.com/pdf/Data%20Sheets/ST%20Microelectronics%20PDFS/FL-101.pdf(from 2002)http://www.manley.com.cn/web/admin_ml32/pic/down/200882917341835980.pdf(From 2003)It looks as though they re-did the design in 2003, but forgot a few things: A 100pF capacitor on a line and they changed shorting DB13 to DB8 to DB13 to DB20 instead. I believe this is a mistake and I found a forum post elsewhere that mentions this as a mistake. So I added a solder bridge to fix this, in case its needed.Anyawy, I made a few other changes that I'd like you guys to review.They use 74A240/74VHC240, which are inverting buffer/drivers for U1. Since I couldn't get those from JLCPCB, I decided to use 74HC244 instead. That is a non-inverting buffer/driver. I believe the two cascaded inverters to be equal to my non-inverting solution. Is that correct?They use DM54ALS05A or 74AC05 for all the inverters, which are open-collector inverters. Again, I couldn't get that, so I decided to use 74HC04, which are push-pull versions. To make them open-collector compatible, I added a PNP transistor on the output. Any issues with this?They use the signal JEN to control whether or not U1 should enable the outputs. The signal is inverted twice and is again open-collector. Since I had a spare buffer in U1, I decided to use that to buffer JEN instead of the double inverter, as this saves me an IC. However, I ran into the same open-collector vs push-pull problem and added a PNP transistor.I used 33 ohm resistor networks instead of 47 ohm ones.Please let me know if you spot anything else!Thanks for your help!

author: CJay
author_rank: Super Contributor
timestamp: February 20, 2021, 09:36:02 pm
content: Should also work for PSD103 which I have a need for, what software are you going to use?

author: petemate
author_rank: Regular Contributor
timestamp: February 20, 2021, 10:01:18 pm
content: Quote from: CJay on February 20, 2021, 09:36:02 pmPSDSoft Express. It is freely available from the ST web page. Only problem is that I have to run it in an windows xp virtual machine and that the JTAG thingie works on a parallel port. So i'd have to get a parallel port interface or install on an old computer(probably the latter).It doesn't appear that PSDSoft express supports anything below PSD3xx, though. You're welcome to get a copy of the design when its done.
Quartus II v13.0.1 MAX7000S Bidirectional Pins - Page 1
Forum section: electronics / general

author: jdgabbard
author_rank: Contributor
timestamp: February 15, 2021, 07:16:20 pm
content: I'm using Quartus II v13.0.1 with a MAX7128. I'm using schematic view with some components that I've already designed and added to my project.I am attempting to connect Data pins together so that they are bidirectional. The components that output data already have active-high output enables for gating of the data. However, I am having a heck of a time wrapping my head around which primitives to use, how to use them, and what is going to produce the results that I'm looking for. To be clear, data input with the output at high-z should be the default. When attempting to output data, the data should be available when the active-high enable changes state to '1'. Otherwise the BIDIR pin should act like an input (high-z ?).Initially, I thought I should be using ALT_IOBUF. However, that primitive is apparently not compatible with the MAX7000S family. After doing some Google-Fu, I found a single thread on another forum that suggested using TRI and WIRE primitives to create the desired effect in the poster's BDF. However, it didn't give an example of HOW to do this.I've added a photo of how I think it should be done. Can anyone confirm this? Is there an easier way without going back through my VHDL (which is broken down into several modules)?

author: BrianHG
author_rank: Super Contributor
timestamp: February 16, 2021, 01:40:58 am
content: This is how we would do it in Verilog/StsremVerilog:https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/verilog/ver_bidirec.htmlMaybe the 'Z' assignment is available in VHDL. However, I do not have a clue.You could always mix VHDL calling the above Verilog module minus the clocked regs A&B.

author: Bassman59
author_rank: Super Contributor
timestamp: February 16, 2021, 04:55:18 am
content: Quote from: BrianHG on February 16, 2021, 01:40:58 amIn VHDL:Code:entity foo isport (pio : inout std_logic;... -- other ports);end entity foo;architecture bar of foo issignal goingout : std_logic;signal oe : std_logic;begin-- ...pio <= goingout when oe = '1' else 'Z';-- and you can just use pio as the input directly, or register it.end architecture bar;
DDR memory READ preamble and postamble - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: February 21, 2021, 04:22:58 pm
content: 1) ForPreamble detection and postamble closure for a memory interface controller, could anyone explain how the following Figure 4 , Figure 5 and Figure 6 work to sample (or capture) the incoming DQ signal during DDR read activities ?2)Delaying the incoming strobe for READs is more involved and will be covered in detail in an independent technical note.<-- Do anyone have idea on which exact independent technical note it is referring to ? I suppose for READ preamble, DQS is aligned with DQ , so why need to delay the incoming DQS strobe ? If it is due to DQS setup timing requirement for sampling DQ signal, then how would I implement the slight delay in verilog coding implementation ?

author: gregben
author_rank: Newbie
timestamp: February 23, 2021, 05:45:49 am
content: First post, so I'm putting on my flame shield!How about some context? Link to the source of this? I'd like to read more.I find Figure 6, especially the mux? marked 620 interesting. I fail to see how this circuit would do anything useful unless there are missing details like preset or clear. As shown it would circulate whatever random garbage the flip-flops output on power up.
Altium Nanoboard NB300AL - Altera Cyclone III Board - Page 1
Forum section: electronics / general

author: ceteras
author_rank: Newbie
timestamp: January 18, 2021, 12:10:01 am
content: I have one of these, I think it was released in 2008 or 9, I know it's old, but it still seems to be quite an impressive piece of kit.It sports an EP3C40F780C8N, and a ton of memory chips, interfaces, even an LCD display.[ Specified attachment is not available ]I could only find the schematics, a few information about it, and some projects on github, but however I've tried I couldn't find functional software to run with it.Quartus II version 13.1 with usb blaster detects it as shown in the attached image (unknown).[ Specified attachment is not available ]Anyone has experience with this board? Any advice is much appreciated!

author: Scrts
author_rank: Frequent Contributor
timestamp: January 20, 2021, 02:16:57 pm
content: JTAG should identify the FPGA correctly. My guess is that either something is not right with the power rails or the jumper configuration is incorrect.

author: mon2
author_rank: Frequent Contributor
timestamp: February 03, 2021, 08:44:49 am
content: https://techdocs.altium.com/display/HWARE/Setting+up+the+NanoBoard+3000We also own the same kit but do not believe that we have used it yet. It was an eBay special.For starters, the Altium suite should offer demo code, tutorials and docs on this kit.Due to the age of the FPGA, you will have to install an older Quartus tool chain to support the device. Had to do the same for one of the SRAM based 5 volt tolerant Altera devices onboard a kit from fpga4fun.com - highly recommended website. Jean has a wealth of knowledge on that website. That was our first serious exposure to FPGA. For us, Jean informed us that Quartus 9.1 was required for the purchased kit. You should be able to download older tool versions from Intel.You will find that as the Quartus versions changed, they dropped the support of various devices upon their release.
Altera MAX 10 accessing lpddr2 sdram - Page 1
Forum section: electronics / general

author: pinout_1
author_rank: Newbie
timestamp: January 29, 2021, 12:53:56 pm
content: Hello. I'm fairly new in FPGA, but I got a task to access LPDDR2 SDRAM memory based on the MAX 10 10M50 FPGA Evaluation Kit. So, sorry for my misunderstanding, but maybe you can point me to the right direction.I have been able to program the board for simple on-board led blinking, but even with a large amount of documentation, I still can't access the memory. I use Quartus prime Lite with Quartus Prime programmer. I need to generate a video output signal and write data into the onboard LPDDR2 SDRAM memory. When I can access the memory, then I think I can try to test HDMI video framing.Thanks for the answers

author: Jope
author_rank: Regular Contributor
timestamp: January 29, 2021, 03:35:01 pm
content: You can use the UniPHY IP core from Altera/Intel.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: February 01, 2021, 08:17:32 am
content: Did you have a look at thedesign examplefor your kit?

author: Scrts
author_rank: Frequent Contributor
timestamp: February 01, 2021, 02:57:48 pm
content: There are more relevant examples as well:https://fpgacloud.intel.com/devstore/platform/15.1.0/Standard/framebuffer-driven-lcd-display/You will most likely need Nios (at least free version) to initialize the memory and the registers.Before you include frame buffer, try to generate video frames using a color bar generator and video output block. It will not need Nios or frame buffer to get the actual video on the display.
Running DOOM on a tiny ice40 - Page 1
Forum section: electronics / general

author: tnt
author_rank: Regular Contributor
timestamp: January 28, 2021, 07:19:46 pm
content: Just thought I'd share this here :https://youtu.be/3ZBAZ5QoCAkPeople always seem to underestimate what a small (and relatively slow !) iCE40 up5k can do ... but I find it fun to play with the low end.All done with the OSS tools btw.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 28, 2021, 09:23:57 pm
content: Nice job

author: Ed.Kloonk
author_rank: Super Contributor
timestamp: January 28, 2021, 10:12:20 pm
content: Yes, but can it run Do...Oh, wait.

author: tnt
author_rank: Regular Contributor
timestamp: January 28, 2021, 10:15:37 pm
content: ThanksNext up is probably going to be "But can it run linux" ?Need to see if I can fit a mmu in there. Also probably going to use HyperRAM instead of SPI PSRAM just to get a bit more capacity.
[Xilinx SDK] Target reset in debug perspective - Page 1
Forum section: electronics / general

author: dtodorov
author_rank: Contributor
timestamp: January 16, 2021, 09:19:16 am
content: Hi there,recently I started exploring the Microblaze microcontroller system (MCS) offered by Xilinx. For a hardware-oriented guy I find it's a blessing to be able to add uC next to your hardware in a matter of minutes and bring up the entire build/toolchain system automatically.However, when debugging I frequently need to reset the target (without modifying the code) and start the debug process all over. But the only way I could do that (for what I know already) is to rebuild the project and relaunch the debug target, which in my case costs a few tens of seconds and it gets really annoying. In other Eclipse-based IDEs (e.g. Atollic, SW4STM, CubeIDE) there is a "Reset" debug button available that did the job easily.Searching through the web I found a XSCT console commands that may do the job, but I have not yet come to understand that completely.I know it's a bit perky, but has anyone already found a solution to it?Thanks,Dimitar

author: dtodorov
author_rank: Contributor
timestamp: January 26, 2021, 08:11:57 pm
content: Hi,just to share a bit of a progress - apparently a XSCT console commands can facilitate target reset without re-laucnhing of the build and target programming procedures.So in the XSCT console I use 3 commands as follows:1. Reset the target -> PC gets set at 0x00 and execution is suspendedCode:xsct% rst;2. Add breakpoint on main routine [this is optional]Code:xsct% bpadd -addr &main;3. Run the target [to the first breakpoint]Code:xsct% conNice thing is this console accepts multiple delimited commands, so a single spell does itCode:xsct% rst;bpadd -addr &main;conSource of knowledge:https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1208-xsct-reference-guide.pdf
Why this simple code generates wrong results for MUL operation - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 17, 2021, 11:09:31 am
content: Hi,I'm developing a RMS module , input data are 24bit singed , here is the verilog code, But in model sim the results are wrong!?what I have done wrong in the * operation?Code:module RMS (//Interfaceinput i_Clk,input i_Rst,input signed [23:0] i_Data,output reg [23:0] o_Data,output reg o_Dv//output data valid);reg [47:0] r_MAC;reg [7:0] r_SampleCnt;//it will count how many samples we gotwire [47:0] w_c;//to see the mul in debug windowalways @(posedge i_Clk ) beginif(i_Rst == 1'b1) begino_Data <= 24'h0;r_MAC <= 48'h0;r_SampleCnt <= 8'h0;end else begino_Dv<= 1'b0;r_MAC <= (i_Data * i_Data) + r_MAC;r_SampleCnt <= r_SampleCnt + 1'b1;if(r_SampleCnt == 8'hff) begino_Dv <= 1'b1;endendendassign w_c = i_Data*i_Data;endmoduleThe first input data is -668399 and the result should be 4467451921‬ But model sim shows a very big wrong number 446757223201‬

author: tru
author_rank: Regular Contributor
timestamp: January 17, 2021, 12:13:07 pm
content: I see that you have assigned i_Data with value: -668399, which is a lot bigger than you intended input: -66839.Also a suggestion for the code:Code:o_Dv<= 1'b0;...if(r_SampleCnt == 8'hff) begino_Dv <= 1'b1;endto:Code:if(r_SampleCnt == 8'hff) begino_Dv <= 1'b1;endelse begino_Dv <= 1'b0;endReason is because the assignment operator <= is non-blocking and when the if statement is true, it is telling it to assign both values!Although, it seems the compiler corrected your mistake so no errors in the simulation, no idea.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 17, 2021, 01:46:43 pm
content: Thanks for the points, Actually the first post value was correct in the picture and it can be fitted in a 24Bit value, I have corrected the first post value,So any other Idea what might be wrong?

author: NorthGuy
author_rank: Super Contributor
timestamp: January 17, 2021, 02:57:20 pm
content: For what it's worth, 668399*668399=446757223201, unless my calculator is broken.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 17, 2021, 03:09:20 pm
content: Quote from: NorthGuy on January 17, 2021, 02:57:20 pmSame here. There doesn't seem to be anything wrong with the op's code and sim result.Looks like the op missed one digit and used 66839 instead of 668399.

author: asmi
author_rank: Super Contributor
timestamp: January 17, 2021, 04:06:35 pm
content: Yep, here's what I got.

author: asmi
author_rank: Super Contributor
timestamp: January 17, 2021, 05:14:26 pm
content: Quote from: tru on January 17, 2021, 12:13:07 pmThis is not a mistake, but a well-defined behavior. Multiple assignments are allowed, and only the last one in the code flow will actually take effect. This is very useful for assigning "default" values.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 17, 2021, 07:18:30 pm
content: Thanks guys, my mistake on missing a digit on my calculator
Xilinx Stanford Digilent NetFPGA Open Platform Gigabit Network Development  - Page 1
Forum section: electronics / general

author: DiTBho
author_rank: Super Contributor
timestamp: January 13, 2021, 12:19:11 pm
content: Yesterday eBay sent me some promotional email about the old Digilent NetFPGA Virtex-II Pro FPGA Development SystemThe NetFPGA is the low-cost re-configurable hardware platform optimized for high-speed networking. The NetFPGA includes all of the logic resources, memory, and Gigabit Ethernet interfaces necessary to build a complete switch, router, and/or security device. Because the entire datapath is implemented in hardware, the system can support back-to-back packets at full Gigabit line rates and has a processing latency measured in only a few clock cycles.It seems there is a multi-university research ecosystem hosted atnetfpga dot org, with design examples and other resources.eBay mentioned this:QuoteUmm, Xilinx Virtex-II Pro 50 ... PCIX, and dram: what do you think?

author: hamster_nz
author_rank: Super Contributor
timestamp: January 13, 2021, 09:02:56 pm
content: Do you have access to a license for the EDA tools? If not, it is a brick.

author: DiTBho
author_rank: Super Contributor
timestamp: January 13, 2021, 09:17:57 pm
content: Quote from: hamster_nz on January 13, 2021, 09:02:56 pmUnfortunately no.

author: Morgan127
author_rank: Contributor
timestamp: January 14, 2021, 07:05:05 am
content: I would not go for that board. VII Pro is deprecated and it is not even supported by the latest ISE Tools. So you have to find an old version of ISE and probably a old version of operating system if that should run stable. I had to go through this procedure a couple of months ago to fix a new firmware to an old VPII Pro product.So my advise is forget Virtex II Pro.

author: Scrts
author_rank: Frequent Contributor
timestamp: January 15, 2021, 06:51:00 pm
content: Quote from: Morgan127 on January 14, 2021, 07:05:05 amI second this. It was already old 10 years ago.
PLL Variable Clock Phase Shift - Page 1
Forum section: electronics / general

author: Foxxz
author_rank: Regular Contributor
timestamp: February 01, 2021, 06:37:47 pm
content: Can I tie an external clock to an FPGA and use the PLL to do phase shifting if the external clock has variable frequency? Or do I need to use the PLL to vary the frequency and phase?

author: hamster_nz
author_rank: Super Contributor
timestamp: February 01, 2021, 08:40:42 pm
content: Quote from: Foxxz on February 01, 2021, 06:37:47 pmIf your external clock clock changes frequency and/or phase too much then the PLL will lose lock, stop generating signals and need to be reset.

author: BrianHG
author_rank: Super Contributor
timestamp: February 02, 2021, 12:43:14 am
content: Quote from: hamster_nz on February 01, 2021, 08:40:42 pmWe haven't a clue about what kind of frequencies he is talking about. Maybe he shouldn't be using a PLL. Is he creating a clock source or exclusively responding to one. Maybe it should be done in logic gates. These isn't much we can do with such an open vague question without a clue to any specifics. All I say is make your code operate in-phase or 180degree out and you don't need to worry about phase. As for PLL range, it depends on the core PLL frequency and pull range. This is more advanced as you need to know what frequency the core of the PLL is running at, not you chosen output frequency. This info is available, different for different FPGAs and you will need advanced access techniques to operate here especially if the PLL is clocking a bunch of logic other than data ports as you may corrupt design functionality.

author: hamster_nz
author_rank: Super Contributor
timestamp: February 02, 2021, 01:28:05 am
content: Quote from: BrianHG on February 02, 2021, 12:43:14 amA tweet-sized question deserves a tweet-sized answer...

author: Foxxz
author_rank: Regular Contributor
timestamp: February 02, 2021, 02:33:46 am
content: It was just a general question because I don't have alot of specifics. But if I was thinking in terms of using the FPGA to generate the phase offsets to make the LO for an SDR platform (maybe -45 degrees I and +45 degrees for Q? Or just 90 degrees phase for one?) using a chip like the Si5351A to generate the frequency which is fed into the FPGA PLL. I was thinking about using 45 degree offsets as a way to keep the phase noise/delay to a minimum. I don't have any specific frequency ranges in mind.Thinking out loud...
Top Level Module IceCube2 - Page 1
Forum section: electronics / general

author: myval
author_rank: Contributor
timestamp: January 07, 2021, 09:14:23 pm
content: Hi,can someone please explain to me how to tell Icecube2 what module to use as top?I have been scratching my head here and that bloody thing keeps picking wrong module as top level module.thank youJosef

author: Foxxz
author_rank: Regular Contributor
timestamp: January 07, 2021, 09:22:19 pm
content: See attached.

author: myval
author_rank: Contributor
timestamp: January 08, 2021, 09:26:48 am
content: Hi,thanks but isn't this for Simulation only? I am having issue during Synthesis.
Is this how MIPI DSI FPGA Bridge implemented? Constructive Criticism needed  - Page 1
Forum section: electronics / general

author: RoadRunner
author_rank: Frequent Contributor
timestamp: January 21, 2020, 08:51:09 am
content: I have been using FPGA for small project since quite some time but thoese project were either really simple or made like students. I wanted to increse quality so i have desiced to take relatively complex for the sake of learning. After looking at mike's video on mipi lcd i had decided to implement a spi to spi dsi bridge. Sytem works perferectly can go upto full 60 FPS with MIPI DSI Clock rate of 96Mhz. i have tested with feeding spi from another fpga. I have connected whole fpga setup to PIC32MZ USB HS micro in order to be able to transmit image from PC over USB. In steup with PIC32 SPI @max 50Mhz is limitation.if any FPGA experts out here will be willing to shine some light on my design will be really helpful.Project is completely open source. more details can be found here on my bloghttps://www.circuitvalley.com/2020/01/spi-mipi-bridge-fpga-verilog-hdl-ipod-nano-nano-lcd-iphone-mipi-lcd.htmlSource can be found in my githubhttps://github.com/circuitvalley/mipi_dsi_bridge_fpgaThere is a smally youtube video explaning whole thing, (i am absolute newbie on youtube)

author: mon2
author_rank: Frequent Contributor
timestamp: January 10, 2021, 06:33:04 pm
content: @Gaurav yaar, excellent article!! Been reading and reviewing it in details. You should be very proud of this accomplishment.One thought on how to possibly speed up the USB from host to FPGA transfer is to consider the USB 2.0 HS Cypress FX2LP USB Bridge or perhaps even the more current USB 3.0 USB parallel bridge. Then use LibUSB to xfer the data to the widget.Have you experimented with more than 1 lane MIPI displays? 2 lane or 4 lane?Would you know if such multi-lane MIPI displays can be configured to operate with a single lane (at slower display data refresh rates)?Thanks.
Zynq board throws "pl35x_nand_cmd_function timed out" error - Page 1
Forum section: electronics / general

author: sink
author_rank: Contributor
timestamp: January 01, 2021, 07:48:41 pm
content: Hi everybody!I got a niceevalboard EBAZ4205 with Zynq XC7Z010-1CLG400.I made project according to this guideshttps://www.programmersought.com/article/65574959208/,https://hhuysqt.github.io/zynq1/.My point was to make HW project, and then compile a PetaLinux for it. When I finally compiled it, and uploaded a Boot.bin with image.ub to sdcard, and booted a board, I get this error - "pl35x_nand_cmd_function timed out". What should I correct to make it work? Is the problem that i compiled it on ubuntu 18.04, not 16 version?There is a bootlog -https://pastebin.com/BNG0Nhuq.Thanks in advice for help.

author: miken
author_rank: Regular Contributor
timestamp: January 03, 2021, 03:41:14 am
content: It sounds like the loader is trying to talk to a NAND controller and not finding anything. I'm not familiar with this particular board or the PetaLinux workflow though.
Sipeed Tang Nano embedded flash programming - Page 1
Forum section: electronics / general

author: davorin
author_rank: Unknown
timestamp: March 28, 2020, 10:17:25 am
content: Good morning (o;Received some of the cheap SIpeed Tang Nano boards for testing...Install of the IDE went fine on Debian 10 Linux....just the programmer won't detect anything when the IDE is not run as root...but that's another story (o;So when I use the LCD example I can synthesize it normally...and also program the SRAM....fine...Just when I select embedded flash as destination I get:Code:Info:"embFlash Erase,Program" starting on device-1...Info:Status Code: 0x00015421Error:Finished, NOT wakes upInfo:User Code: 0x00000000Info:Finished!Info:Cost 9.08 second(s)and the design isn't stored into FPGA:..Any tips how to make a design permanent on this Tang Nano board?thanks in advancerichard

author: FlyingDutch
author_rank: Regular Contributor
timestamp: March 31, 2020, 05:53:29 pm
content: Hello,when I encountered dificulties with "Sipeed Tang Nano" I got help from "Sipeed Forum" on Telegram messenger. You have to instal "Telegram messenger" and then find "Sipped" forum and ask a question - it is quite responsive.Best Regards

author: davorin
author_rank: Unknown
timestamp: March 31, 2020, 06:01:11 pm
content: Well it works now somehow (o;Did a sudo wrapper script for the programmer itself so I don't have to start the IDE as root....But will switch to Trion FPGA now anyway (o;

author: ebclr
author_rank: Super Contributor
timestamp: September 26, 2020, 09:36:44 am
content: Caution If you Use Windows 10 TD Dinasty does not permit you to open IO constraint Window, If you need that you need to move back to Windows 7, If you find a solution to do this on windows 10 please post

author: vstrakh
author_rank: Contributor
timestamp: October 11, 2020, 07:50:45 am
content: I had same issues with Tang Nano.Apparently it's related to the programming cable implementation version and the programmer version.The newer programmer has programming frequency set to 30MHz by default, while the Tang Nano can support only up to 25MHz.Just open the cable settings in the programmer and force/save some low value, like 2.5MHz. It did work for me immediately.

author: alxlabs
author_rank: Newbie
timestamp: December 29, 2020, 06:09:31 pm
content: Same here.. and thanks vstrakh for the advice of playing with download speed. The default was 2MHz, I changed it to 2.5MHz and it started to work.

author: RonB
author_rank: Newbie
timestamp: January 01, 2021, 02:57:45 pm
content: Yes you are right @alxlab and @vstrakh, it worked for me using 2.5MHz. Thanks.
Xilinx Spartan-6, Spartan-7 lead times - Page 1
Forum section: electronics / general

author: ebastler
author_rank: Super Contributor
timestamp: February 06, 2021, 01:06:23 pm
content: According to Mouser, Xilinx now quotes 44 to 48 week lead times for their Spartan-6 and Spartan-7 series. There is limited stock for some types (at Xilinx and other distributors), and back-orders with October or November ship dates for others.Is that Xilinx' normal lead time, or are they experiencing shortages due to Covid-19 or other reasons? Their Spartan-6 web page still claims "12 weeks"...https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 06, 2021, 06:13:28 pm
content: No this is not normal, but here it is:https://asia.nikkei.com/Business/Tech/Semiconductors/Chipmaker-Xilinx-says-car-supply-crunch-goes-beyond-semiconductorsI got recently interested in Lattice ECP5 parts for new projects (instead of Xilinx Spartan 6/7), and interestingly, Lattice doesn't seem to be affected by this shortage issue (at least as of now...)

author: gnuarm
author_rank: Super Contributor
timestamp: February 06, 2021, 10:04:43 pm
content: Quote from: ebastler on February 06, 2021, 01:06:23 pmMy experience is 14 weeks is a typical lead time from the factory. Once lead times stretch out beyond half a year, they are basically saying, we'll let you know when something becomes available. They are going to keep their bigger customers happy as much as possible and will happily ship product planned for you to any larger customer. I've had distributors do this and there was nothing I could do about it, even though they acknowledged my reel came in and they gave it to someone else.So when lead times stretch out the small guys are always screwed. Get parts when and where you can.
Testbench waveform creator application? - Page 1
Forum section: electronics / general

author: dentaku
author_rank: Frequent Contributor
timestamp: December 18, 2020, 03:21:18 am
content: I just used the Simulation Waveform Editor in Quartus 13.0.1 web edition and was wondering if there was a small standalone tool out there that does roughly the same thing?I'd love to be able to create waveforms in a graphical environment this way (instead of actually typing it all out doing #10; A = 1; #10; A = 0; $finish; etc...) to help me create testbench files that I could use with Icarus/VVP/GTKWave instead of the convoluted Quartus.
Gowin B-SRAM Bit Ordering - Page 1
Forum section: electronics / general

author: gnuarm
author_rank: Super Contributor
timestamp: December 14, 2020, 07:41:03 am
content: i want to use a 2 port B-SRAM as an interface between two processes with different bit widths. One port should be 1 bit wide and the other port should be 16 bits. I can't find anything saying which bit in the 16 bit words maps to which sequence of addresses in the 1 bit port.This is sort of a big endian vs. little endian thing, I can see either connection being justified. I'm rather hoping it is little endian with the lsb of the 16 bit words mapped to addresses xxx0 and the msb mapped to xxxF.I'm only asking here because I don't know of any forums where Gowin devices are much discussed. if no one knows I guess I can rig up a simulation and test it out. That will be another module I'll have to reverse engineer as any detailed documentation is pretty much absent. Or I could ask the FAE. He seems to be a pretty good guy and so far doesn't seem to mind my questions.

author: BrianHG
author_rank: Super Contributor
timestamp: December 14, 2020, 08:00:29 am
content: You can simulate and test. Usually 0x0 would point to the LSB of the 16 bit side while 0xF would point to the MSB as you are basically addressing in order of magnitude, however, this is what I have used in Intel's Quartus.If you want to change the order, you can XOR your address on the chosen side of the ram with 0x00F.Or, swap the bits around on the 16 bit side.There is 0 delay or logic consumption in doing so in an FPGA.Worst case, you can do 16bit x 16bit and demux the output / or use a bit write mask to write 1 bit at a time.(Additional note: in some of my code, I just have a 'parameter' to select the endian...)

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 14, 2020, 06:06:58 pm
content: If this is not documented, this clearly sucks. I guess you could safely assume this will be LSB first, as this is how it's done one most FPGAs I know of these days, but this *should* be documented by GOWIN. Is there no doc for this? And yes, in doubt, just test it. Or use the same width on both ports and do the serializing or deserializing yourself, which is not hard.
AES 256 FPGA core - Page 1
Forum section: electronics / general

author: Guy Shemesh
author_rank: Contributor
timestamp: December 29, 2020, 02:14:12 pm
content: HiI need a recommendation free AES256 FPGA core - for a project involving software and hardware co-processing on a Xilinx Zynq ultrascale+ device.no further requirements (i.e ECB mode is enough, without authentication as the rest is done in software).Anyone who did it can recommend on a working and stable core ?Thank youGuyePiccolo Engineering

author: rstofer
author_rank: Super Contributor
timestamp: December 31, 2020, 01:29:20 am
content: OpenCores.org has one under Project -> Crypto. I don't know anything about it.

author: dolbeau
author_rank: Regular Contributor
timestamp: December 31, 2020, 05:49:48 pm
content: I'm usingthe one fromhttps://github.com/secworks/aesfor AES128, planning to add/move to AES256 (core does both, encrypt & decrypt). I'm instantiating theaes_corenot the high-levelaes. Works for me...

author: Guy Shemesh
author_rank: Contributor
timestamp: January 25, 2021, 02:49:34 pm
content: Thank you very much dolbeau for the recomendation,I have used the Secworks and it's working great. Simple, working and easy to use.Guy

author: dolbeau
author_rank: Regular Contributor
timestamp: January 25, 2021, 07:17:37 pm
content: Quote from: Guy Shemesh on January 25, 2021, 02:49:34 pmExcellent :-) BTW I since discovered an updated implementation of the same core - the 'aes-speed' fromhttps://trac.cryptech.is/wiki/GitRepositories. It's larger but faster (cycles-wise), with the same interface. Depending on your requirements it might be an option.They also have a bunch of FPGA-proven implementations for other algorithms.

author: Guy Shemesh
author_rank: Contributor
timestamp: February 09, 2021, 05:24:33 pm
content: Wow!Sorry only now I see this, it looks amazing!Indeed the other AES took 72 cycles/block, now I see it's down to 20 cycles/block !I had already finished my project for this so I could not test it. And regarding the relatively long encryption/decryption time, I hid it -:) We also have a software SHA256 which takes quite alot from the processor, so I let these processes work in parallel (PL-AES / SW-SHA).Thanks dolbeau, I'll keep this link as I see there are many other interesting implementations thereBest Regards and keep safeGuy