Generate 3 phase sine w/ AD9833.  Sync'ing??? - Page 1
Forum section: electronics / projects

author: Skimask
author_rank: Super Contributor
timestamp: June 23, 2014, 06:12:42 am
content: Looking at making a 3 phase (120 degree offset) generator with a trio of AD9833's.The datasheet notes that output won't be updated for 7-8 MCLK pulses after the RESET is set back to 1, with 1 MCLK ambiguity due to the internals.If I'm reading this right...Need a single buffered clock source that can drive all 3 AD9833 MCLK inputs.An SPI interface for all 3, individual FSYNC lines, combined Data/Clock lines, normal stuff.Set all 3 up individually, but drive the FSYNC line at the same time for the RESET after loading freq and phase registers. Re-RESET all 3 at the same time by clocking in the control word that does the resetting and kicking the FSYNC line at the same time on all three, thereby all three will 'come up' at the same time (or at least within 1 MCLK cycle), and as long as the phase offset register is set for a 120 degree offset for each one.Yes, 4096/3 isn't an integer, but should be close enough here, off by about .03 degrees per phase vs. being perfect at 0/120/240 degree offsets.P.S. Building up a 3-phase power supply for doing initial checking of 28VAC 400Hz 3-phase synchro transmitters/resolvers/transolvers/etc.(Before anybody scolds me for trying to circumvent any FAA regulations or anything of that nature, NO, this is not for any kind of calibration, final checkout, or anything like that. It's only going to be used for a quicky 'dead or alive' check of parts headed to an accredited facility for refurb and/or repair)

author: johnwa
author_rank: Frequent Contributor
timestamp: June 23, 2014, 08:00:34 am
content: Hi,I am afraid I am not familiar with the AD9833, so I can't really help with your original question. However, one of my current projects is a three phase signal source similar to what you have described. I am using LM13700s in an analogue oscillator circuit, with voltage controlled frequency and amplitude. If you think this might be suitable for your application, I can send through the circuit details.

author: atferrari
author_rank: Frequent Contributor
timestamp: June 23, 2014, 09:56:28 am
content: Quote from: Skimask on June 23, 2014, 06:12:42 amI implemented a 3-phase generator, IIRC going from 10 to 998Hz with a 18F4431 + 3 CD4015+3 R2R.Three LMF100, to BP filter each output, smoothed in turn with caps progressively added along the range.EDITTo add: this design makes the phase difference exactly 120º, always./EDIT

author: tszaboo
author_rank: Super Contributor
timestamp: June 23, 2014, 12:02:23 pm
content: Yo dont need to do everything at the same time if you can disable the clock source, for example with an and gate. If this makes it any easier. Otherwise everything else seems to be like you explained.

author: Skimask
author_rank: Super Contributor
timestamp: June 23, 2014, 12:25:13 pm
content: Quote from: NANDBlog on June 23, 2014, 12:02:23 pmInteresting idea.The clock source I'm using on my homemade single AD9833 demo PCB has an enable/disable pin. I'll give that a shot.Took a look at the datasheet. Seems like all the data, register updates, etc. should clock in without an active MCLK, then as you suggest, everything should start up with the new settings 7-8 MCLK cycles after enabling the MCLK source.

author: mamalala
author_rank: Unknown
timestamp: June 23, 2014, 04:08:48 pm
content: You won't be off by only 0.03° anyways. The AD9833 has a phase resolution (!) of 12 bits effectively, giving you around 0.1° phase resolution. Unless you set a frequency so that the frequency word is an even fraction of the internal phase accumulator, phase-to-sine lookup table, etc., you will over time wander around within that 0.1° margin. Also note that the DAC used in the chip has only 10 bits, so you won't get even get a 0.1° resolution at the output, since there are only 1024 discrete steps available, 360/1024=0.3515625° per step at best.Since the internal phase accumulator counts up, has the lowest bits truncated, fed into the lookup table, which finally ends up at the DAC, you will (with only a few exceptions) always see a phase difference of that 0.35° from time to time between phases. The exceptions being frequencies that use a frequency-word that is a direct power-of-two, everything else will at some point have those errors periodically.Greetings,Chris

author: Skimask
author_rank: Super Contributor
timestamp: June 23, 2014, 07:20:11 pm
content: Quote from: mamalala on June 23, 2014, 04:08:48 pmOf course, you're absolutely right....thinking I'd probably be good with even 10 degrees of error anyways...

author: mamalala
author_rank: Unknown
timestamp: June 23, 2014, 08:28:12 pm
content: Quote from: Skimask on June 23, 2014, 07:20:11 pmYeah. What i forgot to mention, you won't get an exact 120° phase offset either, since the chip works binary, so you will have a problem with dividing by 3 for the phase word _exactly_ anyways.Plus, you have to look at what the actual use is in the end. Just getting a good output is one side, but you also have cabling and connectors, which introduce capacitance and inductance. The you have whatever it ends up in, which again will probably introduce C and L. Each of that will mess with the phase angle to some extent.Greetings,Chris

author: dannyf
author_rank: Super Contributor
timestamp: June 23, 2014, 09:39:48 pm
content: Easy:hang all three chips off the same bus. When sending the frequency, bring all three vs pins low. Then bring the second vs pin low and load up the 120 phase angle. Then bring the third vs pin low and load the 240 phase angle.

author: dannyf
author_rank: Super Contributor
timestamp: June 23, 2014, 09:40:49 pm
content: The above approach assumes one master clock for all three dds chips.

author: Skimask
author_rank: Super Contributor
timestamp: June 23, 2014, 11:54:03 pm
content: Quote from: dannyf on June 23, 2014, 09:39:48 pmIsn't that what I said in the first post?

author: mamalala
author_rank: Unknown
timestamp: June 23, 2014, 11:55:20 pm
content: Quote from: dannyf on June 23, 2014, 09:40:49 pmStill doesn't help with the inherent workings of these chips. No matter what you do, you will never get the phases exactly 120 degrees apart all the time.Greetings,Chris

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: June 24, 2014, 02:12:22 am
content: Hi,You reduce the number of DDS channels from 3 to 2. The technique that I am describing is useful for generating an arbitrary number of phases from a sine and cosine waveform. It can be used to make three phase from an oscillator with sine and cosine outputs.If you take the sine and cosine waves and add (or subtract) them in the right proportions you can generate other phases.Here is an example:And the results:Phase R= sin(Wt)Phase S = -0.5sin(Wt) - 0.866cos(Wt)Phase T = -0.5sin(Wt) +0.866cos(Wt)Regards,Jay_Diddy_B

author: mamalala
author_rank: Unknown
timestamp: June 24, 2014, 03:37:49 am
content: Jay_Diddy_B, thanks for sharing, that's a really neat thing to know!Greetings,ChrisEdit: I think there are even DDS available that have a simultaneous sin and cos output, but not 100% sure.

author: Skimask
author_rank: Super Contributor
timestamp: June 24, 2014, 04:53:41 am
content: Nice! Never thought of doing it that way either.And stepping back a bit, the math behind it immediately makes sense too.

author: jlmoon
author_rank: Unknown
timestamp: June 24, 2014, 06:39:45 pm
content: Quote from: Jay_Diddy_B on June 24, 2014, 02:12:22 am3 ph delta power generation math. .by chance?