Any CPLD IDE software that can synthesize SystemVerilog 2012? - Page 1
Forum section: electronics / projects

author: Fusion916
author_rank: Regular Contributor
timestamp: October 28, 2018, 08:47:30 pm
content: So my adventure into CPLD software has been extremely disappointing. No only are there only a few CPLD vendors (same with FPGA), there software support for their CPLD devices is very poor. It seems like most (if not all?) can only synthesize verilog 2001 or maybe 2005 (unclear with some software). I can't find any one than can synthesize SV2012. Is this only supported with modern FPGA synthesis tools?

author: Fusion916
author_rank: Regular Contributor
timestamp: October 29, 2018, 08:10:53 pm
content: No info?

author: ataradov
author_rank: Super Contributor
timestamp: October 29, 2018, 08:18:00 pm
content: CPLDs are typically very simple devices. What's wrong with Verilog-2001? What exactly are you missing from SV for CPLD development?

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 29, 2018, 08:47:09 pm
content: It's not just CPLDs. From what I gathered, SystemVerilog is still poorly supported by many vendors.

author: Fusion916
author_rank: Regular Contributor
timestamp: October 29, 2018, 09:07:21 pm
content: Quote from: ataradov on October 29, 2018, 08:18:00 pmThey may be simple devices but SV2012 support is in the software layer, so I don't know why they would not support it. FSM coding is much better looking with SV2012 support with typedef enumerations, and in general there are quite a few datatypes that Verilog 2001 doesn't support.

author: Fusion916
author_rank: Regular Contributor
timestamp: October 29, 2018, 09:09:29 pm
content: Quote from: SiliconWizard on October 29, 2018, 08:47:09 pmThat is disappointing. From what I can see, there are NO CPLD manufacturers that support SV2012 with their IDE suite. Zero.If I move up to the expensive FPGA device they probably support with their 10k/license IDE software however

author: ataradov
author_rank: Super Contributor
timestamp: October 29, 2018, 09:09:49 pm
content: Quote from: Fusion916 on October 29, 2018, 09:07:21 pmI know exactly why. Testing and QA of the software will take more resources while adding little value. Companies cut software features all the time because if this.

author: Bassman59
author_rank: Super Contributor
timestamp: October 30, 2018, 02:50:26 am
content: Quote from: Fusion916 on October 29, 2018, 09:07:21 pmYou should just use VHDL and you’ll get those enumerated states and more useful data types, most of which have been in the language for 25 years.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 30, 2018, 02:53:48 am
content: Quote from: Bassman59 on October 30, 2018, 02:50:26 amI agree with that but I'm smelling the start of a flame war!

author: Fusion916
author_rank: Regular Contributor
timestamp: October 30, 2018, 04:18:40 am
content: Quote from: Bassman59 on October 30, 2018, 02:50:26 amI have no experience with VHDL nor do I have any intention of learning. I rather just live with Verilog 2001.

author: rstofer
author_rank: Super Contributor
timestamp: October 30, 2018, 07:14:19 pm
content: Quote from: Fusion916 on October 30, 2018, 04:18:40 amThere you go! Problem solved...

author: Fusion916
author_rank: Regular Contributor
timestamp: October 30, 2018, 09:21:10 pm
content: Quote from: rstofer on October 30, 2018, 07:14:19 pmsigh, no ideal, but fine.