Trouble understanding Inrush Current Load Switch - Page 1
Forum section: electronics / beginners

author: LoveLaika
author_rank: Frequent Contributor
timestamp: September 13, 2023, 04:04:54 pm
content: I'm following the app noteAN9093Dby OnSemi to develop an inrush-current limiter with a PMOS, but I'm having trouble understanding how it works compared to simulations. I've attached an image of the app note section as well as my LTspice simulation to illustrate my confusion. The LTspice sim uses parts that come with the software, so there should be no custom SPICE models needed.Looking at the app note, it appears straightforward when you look at the regions. In region 1, no current flows to the load because the source-gate voltage, VSG, is below the threshold voltage, VTP. In region 2, VSGis above the threshold voltage, so the PMOS turns on. However, since VSDis much greater than VSG-VTP, the PMOS is in saturation mode until the gate-source parasitic capacitance charges, CSG. Once there, it goes to region 3, and VSDdecreases until the PMOS is in linear mode while the drain current stays the same.The idea seems straightforward, but when I try to simulate it, I'm getting a really large inrush current during stage 2. You can see that when you compare the current from the PMOS compared to the current without the PMOS in the picture below. According to the specs of the PMOS, its threshold is -2 volts, and it has capacitances in the pico-Farads. It shouldn't take that long to charge, but why is there such a big inrush current (only for ~200 us) when the PMOS starts to turn on? Are there assumptions about this circuit that I'm not taking into account?EDIT: Looking at it more, I'd like to add on some thoughts following the app-note diagram. So, at startup from 0 volts, the R2 and C1 form an RC-circuit. Current goes from VIN through R2 to C3 until the PMOS Gate (VPG) is the same voltage as VIN while the PMOS drain (VPD) acts as a virtual ground of sorts. R2 has to be chosen so that it's large enough to have a voltage difference between PMOS source and gate when you turn it on (too low, it will always be off) while not too large such that the large voltage difference at the start will automatically turn it on (and since it's in saturation, lots of current will be drawn by accident). R2 and C3 have to not be too big or too large.Once it "settles", the NMOS turns on pulling R1 to ground. So, R1 and R2 form a voltage divider which will turn on the PMOS once the PMOS source-gate voltage difference passes its threshold. At that point, the PMOS is in saturation since the PMOS source-drain voltage is assumed to be much larger than its source-gate voltage. That's where the "inrush" comes in which rises until the PMOS is in linear mode (when the PMOS source-drain voltage lowers). Then, the drain current is reduced from its peak until it "settles" to the load current value.From this, it seems that it's best to pick values for R2 and C3 first to control the startup, and then you perform calculations to select an appropriate value for R1 to limit the inrush current.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: September 13, 2023, 09:05:57 pm
content: It's a simulator. So play with the parameters.Put in a 10uF capacitor instead of the measly 1nF and see what happens.And on top of that. I am strongly superstitious towards simulations. Before trying to "tune" anything, make absolutely sure that the models, voltage sources, etc are set up correct and working.

author: jwet
author_rank: Frequent Contributor
timestamp: September 14, 2023, 04:52:53 pm
content: Dropping a generic capacitor in a spice circuit gives you an idealized cap with zero ESL, zero ESR, etc, etc. If you put a voltage step into an ideal cap from a zero impedance source like spice voltage source, you'll get an infinite current. You have to think through your sim. Besides ESR, there are distribution losses, etc, even a fuse looks like 10 m-ohms of DCR. Either put a better model in or fake it by putting a small R (.1 ohms) in series with the cap. This will give you something that might make more sense.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: September 14, 2023, 09:11:29 pm
content: The intended goal is to limit the gate current to make the FET switch slowly. When the FET switches slowly then the Ug-s will stay at the same voltage (miller plateau) for a while, and I don't see that happening in your circuit.