TRACE DIRECTION AFTER VIA - Page 1
Forum section: electronics / rf-microwave

author: Nikos A.
author_rank: Regular Contributor
timestamp: May 13, 2019, 11:04:57 am
content: Hi everyone,A just finished the designing of a PCB and there is a point that I am worried about.At the screenshot attached the blue traces are control (logic) at layer 4 and orange traces is the Vcc at layer 3 and I use vias to access layer 1 (just for reference, layer one is the RF and layer 2 is the ground plane).Is it correct the trace direction while I exit the via. I mean is there any specific rule (in terms of trace direction) to apply when exit a via?Nick

author: shadow.dark
author_rank: Contributor
timestamp: May 13, 2019, 01:44:10 pm
content: You mean there's an acute angle between the lines? Because your routes are in 1st layer and layer 4 respectively, I don't think the sharp angle will cause problems.GND in layer 2 will isolate the coupling between the two layers.Most importantly, these lines are Not High Frequency Signal Transmission Line.Don't worry too much.I suggested that,use polygon pour on the third layer to enhance conductivity ,For signal VCC and GND Play the same role.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 13, 2019, 01:45:42 pm
content: No, at least not into the many GHz, or sub-100ps range.Incidentally, why empty layer 3? Why not pour 5V (and whatever else is needed by area)?Tim

author: shadow.dark
author_rank: Contributor
timestamp: May 13, 2019, 02:03:06 pm
content: Quote from: T3sl4co1l on May 13, 2019, 01:45:42 pmThose are just control lines.I think it's looks like Acute angle just because of the view.From a three-dimensional perspective. That's just two right angles.（From line to via & From via to line ）Because the GND layer exists.There is no Interact between the two sides.

author: free_electron
author_rank: Super Contributor
timestamp: May 13, 2019, 02:03:19 pm
content: depending on your layer stack- on adjacent layers : you do not want to fold back over the other trace because you create an inductance. Continue in same direction, or in a swing of up to +90/-90 degrees. don't overlap.Looks like you are doing some RF kerjiggery .. balun to two amplifiers back to unbal ?your 5 volt rail needs decoupling. and make that orange layer a plane. and never share a via to a plane.

author: Nikos A.
author_rank: Regular Contributor
timestamp: May 14, 2019, 07:12:51 am
content: Thank you for your answers!!So, it is suggested Vcc pour?QuoteI am going to decouple, thanks!!QuoteYou mean I have to place a single via for each ground pour? Do you have any suggestion of grounding these ICs?One last question.. I know that there is a lot of conversation around this topic but from your experience is it dangerous to fill the RF layer with ground pour?

author: RadioNerd
author_rank: Regular Contributor
timestamp: May 14, 2019, 11:07:21 am
content: This looks like a switched SAW filter bank.For optimum performance (i.e. stop band rejection) I would make sure that every GND pad of the SAW filters is connected by 2 or more vias directly to the ground plane.Regarding the GND pour on the RF plane: It may help to further improve isolation and stop band rejection of the filters BUT ONLY IF following is kept in mind:1) The pour must have a tight connection to the actual ground plane. it is advisable to use some degree of via stitching on the plane and around the RF lines. The optimum spacing between the vias depends on the frequency of operation.2) Leave enough clearance between top pour and other nets. Making the gaps too narrow may accidentally turn your microstrip lines more into coplanar-ish waveguides. These have a lower impedance than microstrips (for the same trace width) and tend to be more lossy and less controllable, especially if you plan to manufacture your PCB with a cheap FR4 pooling service manufacturer.

author: shadow.dark
author_rank: Contributor
timestamp: May 14, 2019, 12:12:52 pm
content: Quote from: Nikos A. on May 14, 2019, 07:12:51 amYES suggest Vcc pour.place as much VIA as you can for each ground pour.fill the RF layer with ground pour IS dangerous.

author: Nikos A.
author_rank: Regular Contributor
timestamp: May 14, 2019, 12:25:18 pm
content: Thank you guys,I am going to place a Vcc pour on the third layer and keep RF layer clear of ground plane (as I am not sure for the concequenses)Why free_electron said to never share a via to a plane. What is actually means?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 14, 2019, 12:33:22 pm
content: Basically, just run the numbers and make sure you aren't shrinking the transmission line impedance by pouring ground around it.If this is a typical fab with thin outer dielectric, a clearance of twice the dielectric thickness will hardly be noticed, and won't encroach on nearby pads very much at all. (You only need to set clearance between fill/pour/poly and trace; the same clearance to small things like GND pads isn't really practical anyway.)http://www.chemandy.com/calculators/coplanar-waveguide-with-ground-calculator.htmFor example, with a 0.2-1.0-0.2 mm dielectric stackup, dielectric constant = 4, solid inner planes, outer layer GND pour, and a Clearance(InPoly AND InNet('GND'), InNetClass('RF')) = 0.4mm rule, you need a 0.42mm width trace to get 50 ohms.With ground clearance set to 2mm (might as well be ordinary microstrip), you need 0.47mm width to get 50 ohms. Not a huge difference.The microstrip calculators give 44-49 ohms for the 0.42mm trace (same stackup, 1oz copper, no coplanar ground). Probably the CPW number is optimistic and a slightly narrower trace would be appropriate (0.38-0.4mm?).I don't remember which microstrip formula is supposed to be the most accurate. Probably this one:http://www.chemandy.com/calculators/microstrip-transmission-line-calculator.htmIn any case, you're unlikely to get layer thickness, trace width and laminate K this precise, so these are all in the same ballpark in any case.Tim

author: shadow.dark
author_rank: Contributor
timestamp: May 14, 2019, 11:47:58 pm
content: Quote from: Nikos A. on May 14, 2019, 12:25:18 pmHe may mean that: do not let two components share one VIA to the GND plane.This can cause interference.one VIA for one component at lest.Better be more.

author: Nikos A.
author_rank: Regular Contributor
timestamp: May 15, 2019, 07:24:00 am
content: Thank you guys, I will take into consideration every advice!!

author: free_electron
author_rank: Super Contributor
timestamp: May 18, 2019, 02:55:52 am
content: one current path = 1 via.currents should never share a via, especially not return (ground) currents.vias form complex impedances and in RF appliactions you will get all kinds of crud intermodulating in the via...