shared memory? - Page 1
Forum section: electronics / projects

author: coppercone2
author_rank: Super Contributor
timestamp: September 01, 2018, 10:31:02 pm
content: If I have 2 pics controlling a system, one doing DAQ/filter math, and the other doing control (like relays, display, maybe more post processing, communicating to UART, user button presses), is there some way to store a share a small amount of memory between them, so some kind of common thing can be updated to update something in memory like calibration coeffients related to range switching? I guess you can connect the GPIO to make a very simple "memory" that is 8 bits, with one of the chips being considered a slave.(i.e. the chip would have bit codes associated with the state it has the control system in, so the DAQ system knows what correction coefficents to use), but this is pretty limited in size and you can't store say a big float that is transferred from the computer.I mean without bit banging or using SPI requests between the chips.So the memory has a busy signal for both chips, so if one of them happens to read the memory another one is writing to, it would read the busy flag, or possibly the memory would just be doubled up, so whatever was previously written to it is stored during the duration of the update (so it does not crash or go unstable if its doing a control loop, at least has a low probability of misbehaving, since everything should be alot faster then the loop it is controlling). One of the chips could just write something to a registers in the correct roder in the shared memory so the thing does not start up before both are initialized.Is dual port memory what I am looking for? And do pics have support for it in the compiler through some kind of bus? Like some way of pointing to it, so you can do something like store/ldi/load/whateveitwas 0b0000001 -> externalram (pointer command),memorylocation (I don't know, it would be like R18), and some kind of hardware subsystem would deal with it rather then having to jump to some loop that does a SPI or I2C to negotiate something with the memory, and so the routing is seperate from SPI so I don't get ram balony being sent to the high-z adc disrupting my board (otherwise I would need to disable it with a buffer controlled by something else), and its more clock cycles so I need to worry about interrupting sampling or having some bogus sampling restriction because of slowness.And the ram would need to be smart enough either to give the previous value there (be doubled up) or the ldi (lets call it ELDI1 for special write external memory location 1, or maybe instead of 1 you would have a memory address there that is some number of bits (say 8 for up to 256 external memory modules, maybe during initalization you could name the modules, but I don't know how you would acess the memory quick wihtout an identifier, so maybe it should be limited to only 1 chip because then you need some kind of very time consuming bus overhead, or I guses you can use a parallel port to activate em but thats alot of routing, so Iguess restrict it to like a few chips or make it so you don't need all the bus wires, but any kind of bus is at least 1 clock cycle, so the option of single memory chip would be nice without any kind of bus choke) would need to know not to work some how if there is a hardware flag (so it has to interface with the ram), but I guess that would at least flag something, which is annoying, so I would prefer if the memory is just doubled up so there are no traces or things to go wrong with flag registers because thats an annoying programming complication to need to clear them/have lost cycles, if you just have 1 chip then you don't need to communicate bus data so it can be just as fast as reading or writing to internal memory save for the propagation delayTotally forgot if you need to declare which register you use with C.yes its been like a 7 years since I programmed, I have some kind of mix of assembly and C in my mind

author: David Hess
author_rank: Super Contributor
timestamp: September 01, 2018, 11:12:24 pm
content: Dual port memory would work and there actually is at least one dual port serial EEPROM available which would make it if not easy then at least straightforward:http://www.onsemi.com/PowerSolutions/product.do?id=CAT24C208https://www.mouser.com/Semiconductors/Memory-ICs/EEPROM/_/N-488u2Z1yzvvqx?Keyword=dualIf I was doing this using PIC though, I would consider programming a third microcontroller to operate as dual port serial memory.

author: coppercone2
author_rank: Super Contributor
timestamp: September 01, 2018, 11:18:03 pm
content: How does that work in the compiler? Do you just set a port for it and there is some kind of special way to ask to read/write a memory location in the external eeprom?How does the eeprom negotiate timing if there is a update while it wants to read, is it unconditional stable?How many clock cycles does it use?I mean I guess you can store it and use it from local memory but then it occupies registers and you need to signal between them somehow to tell it the ram was updated. I guess you can check a flag in the beginning of each loop, but thats 1 gpio down

author: coppercone2
author_rank: Super Contributor
timestamp: September 01, 2018, 11:41:56 pm
content: ohh your talking serial, so it will just wait. That will introduce some kind of timing error though that can fuck up DSP I think right?I would prefer it to just spit out what it already had then causing some kind of delay.Like, what I mean by double up.ER01 is shared between MCU1MCU2MCU1 requests R01 while MCU2 is updating R01. Rather then making MCU1 wait, I would rather have some kind of internal thing that just gives MCU1 the last known R01 before update rather then making it wait, so you get some kind of amplitude error rather then a mistimed sample. I mean you would still get some sort of error, in both time and amplitude domain, but the time domain error would be slow since the reroute to last known memory would be faster then a memory write delay.Am I right in thinking that a pause like that will chowder FFT?It would double up the storage requirements like RAID though.Am I right in thinking that if your FFTing the data later, the random timing error would cause frequency related inaccuracy and the wrong calibration constant being used would effect amplitude accuracy? Not sure on specifically what it would do. And what about phase?For demodulating one method vs the other method would be better for different modulation schemes right?

author: JS
author_rank: Frequent Contributor
timestamp: September 01, 2018, 11:56:10 pm
content: That looks like a µC using DMA to talk to the other. µC1 has some spare memory set with DMA to a serial port, when µC2 needs something in that memory asks for it and the other responds (without needing to wait the core to have time to do it)If you want a 3rd device you will need a µC with 3 DMA accessing the same memory, one to talk each µC and another to keep updating the data between the buffers.In any case the memory buffer could be just updating when it tries to read in which case you have a problem, but only takes what write takes and it can probably wait for it or obtain corrupted data if you do it wrong, which seems like what you want to do.I think the problem you have with it is that you need a buffer in each µC to talk to the shared mem, and the µC takes critical data from it. It could be smaller or bigger depending in your time response needs and bandwidth, but in any case, you won't have such fast access as you do to the internal mem for a time critical application. That difference must be buffered and deal with it that way.JS

author: David Hess
author_rank: Super Contributor
timestamp: September 02, 2018, 12:01:16 am
content: You will have to study the datasheet to learn how to interface with the dual port serial EEPROM.The dual port serial EEPROM handles the arbitration between the two ports internally so corruption is not a problem but as far as conflicts, it then comes down tomultiprocessing locks. This would be the case with any dual port memory though.

author: coppercone2
author_rank: Super Contributor
timestamp: September 02, 2018, 12:01:54 am
content: is there a memory that gives the last known rather then a lockout? don't know what to look forand can you explain lockout consequences for DSP/demodulationlol or a memory that has a input that can either do lockout or last known depending on how the process is behaving at the time so it can be part of the filter

author: nctnico
author_rank: Super Contributor
timestamp: September 02, 2018, 12:26:26 am
content: Re-design the damn thing to use 1 microcontroller for everything. Having two asynchronous parallel processes is a major PITA to get working right. You'll have to think about what happens if one microcontroller isn't working? How does that work when the shared resource (in this case a memory) stays locked?I've seen this approach fail many times before: people use a too small microcontroller because that is what they know (if you only have a hammer then everything looks like a nail). If a problem gets too big they just throw more too small microcontrollers at it. Learning a bigger microcontroller may take a few days but trust me that it will take less time to try and debug a system with multiple processors.

author: coppercone2
author_rank: Super Contributor
timestamp: September 02, 2018, 12:28:30 am
content: i wanna learn about it though, its interesting unlike a single microcontroller.Again what I am looking for means no lock out, just old values. I don't think it exists. It's essentially memory which may be lying. Sometimes things work even if you lie. Might be better then a hold up. Like a lazy man in a bureaucracy.is this kind of like a quantum computer? a political computer?I am sure it can be useful, its like the computation equivalent of a confidential informant.

author: JS
author_rank: Frequent Contributor
timestamp: September 02, 2018, 01:10:51 am
content: I'd use a bigger µC too, running some RTOS and all hard stuff is done! A few tasks and shared memory already attended by the OS...There is a section of the forum dedicated to µC and FPGAs, people who knows this stuff grow there, not so much here in the general design forum...JS

author: guenthert
author_rank: Frequent Contributor
timestamp: September 02, 2018, 10:42:04 am
content: You might want to try Parallax' Propeller -- multiple MCU (cores, cogs whathaveyou) with shared memory in one case. And as long as you access only word size data (32bits), no issues with locking.

author: nctnico
author_rank: Super Contributor
timestamp: September 02, 2018, 01:28:54 pm
content: Quote from: coppercone2 on September 02, 2018, 12:28:30 amIn that case you are in for a lot of fun. I think an FRAM with an I2C interface may be 'interesting'. First of all it involves sharing one I2C bus with 2 masters (this should be doable and fun). I recommend the FRAM because it is much faster to write if you want to implement locking / status updates. Depending on the type of FRAM it may even have infinite write cycles.

author: David Hess
author_rank: Super Contributor
timestamp: September 02, 2018, 02:28:42 pm
content: Serial interface SRAMs are also available. They can be made non-volatile with a backup power source.