SPARTAN 6 DNA_CYCLES - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: February 17, 2025, 12:09:17 pm
content: HiI have designed a project I want to use SPARTAN 6 DNA as the portion of each MAC address, but I have seen this in the data sheeteFUSE Read Endurance is around 30M read Read Cycleswhat does it mean? what happens after 30M read cycles? why it has this weird behaviour?

author: ataradov
author_rank: Super Contributor
timestamp: February 17, 2025, 04:01:55 pm
content: I don't know anything about Xilinx implementation, so just guessing based on general Flash understanding.Assuming those bits are stored in a flash-like cells, they will have limited number of read cycles. Flash is subject to a read disturbance effect, where reading the same cells over and over causes them to change the state. Here is explanation from Transcendhttps://www.transcend-info.com/embedded/technology/read-disturbanceThe usual solutions involve periodic rewrites and designing in a lot of margin so that drift is not an issue over the expected lifetime of the device.

author: langwadt
author_rank: Super Contributor
timestamp: February 17, 2025, 07:51:04 pm
content: Quote from: ataradov on February 17, 2025, 04:01:55 pmafaiu it is like actual fuses, it's connections that gets "burned" so strictly write-once. I don't know why they would have a read limit, but I've seen some NXP processors with efuses that also list a limit on efuse reads

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: February 21, 2025, 10:20:27 am
content: I have written a verilog module to read the DNA,dna_readerCode:module dna_reader (input clk,input reset,input start,output reg [56:0] dna_value,output reg valid);localparam IDLE = 2'b00;localparam LOAD = 2'b01;localparam SHIFT = 2'b10;localparam DONE = 2'b11;reg [1:0] state;reg [6:0] shift_count;wire read;wire shift;wire dout;// Instantiate DNA_PORT with simulation valueDNA_PORT #(.SIM_DNA_VALUE(57'h0123456789ABCDE)) dna_port_inst (.DOUT(dout),.CLK(clk),.DIN(1'b0), // DIN not used for reading.READ(read),.SHIFT(shift));// Control signalsassign read = (state == LOAD);assign shift = (state == SHIFT);always @(posedge clk) beginif (reset) beginstate <= IDLE;shift_count <= 7'd56;dna_value <= 57'b0;valid <= 1'b0;end else beginvalid <= 1'b0; // Default valid to 0case (state)IDLE: beginif (start) beginstate <= LOAD;endendLOAD: beginstate <= SHIFT;shift_count <= 7'd56;endSHIFT: begindna_value <= dout;if (shift_count == 7'd0) beginstate <= DONE;end else beginshift_count <= shift_count - 7'd1;endendDONE: beginvalid <= 1'b1;state <= IDLE;endendcaseendendendmoduletb_dna_reader Test BenchCode:`timescale 1ns/1psmodule tb_dna_reader();reg clk;reg reset;reg start;wire [56:0] dna_value;wire valid;// Instantiate the unit under testdna_reader uut (.clk(clk),.reset(reset),.start(start),.dna_value(dna_value),.valid(valid));// Clock generation (10ns period)initial beginclk = 0;forever #5 clk = ~clk;end// Stimulusinitial begin// Initialize inputsreset = 1;start = 0;// Release reset after 20ns#20;reset = 0;// Wait for next clock edge@(posedge clk);// Assert start signalstart = 1;@(posedge clk);start = 0;// Wait for valid signalwait (valid == 1);// Check the DNA valueif (dna_value === 57'h0123456789ABCDE) begin$display("Test Passed: DNA value matches expected.");end else begin$display("Test Failed: DNA value = %h", dna_value);end// End simulation#100;//$finish;endendmoduleThe output code is like this1123456789ABCDEBut I expect0123456789ABCDEI'm scratching my head, what am I doing wrong?