Another unstable MOSFET based current source - Page 1
Forum section: electronics / projects

author: BelgianEngineer
author_rank: Contributor
timestamp: October 01, 2021, 08:40:29 pm
content: Hey All,I am working on a controlled current source (or DC load). The approach I chose is to have both a current sense opamp and a compensation opamp so I can avoid the big power resistor which you usually get in the single opamp circuit.I have a simulation which runs smoothly with a phase/gain margin around 90deg and 10dB. Unfortunately in practice I get an oscillating circuit which somehow I can't manage to stabilize... I have played around with the gains, filters, damping of input line, gate resistance etc. but nothing successful up to now. I only noticed that the oscillation disappears when I run the compensator "proportional-only" by removing the feedback capacitor. Unfortunately that does result in a steady state offset which I am exactly trying to avoid.LT spice diagram and the observed waveforms hereby attached. Unlike the simulation, in practice I am using the IXTH80N075L2.I am slowly running out of ideas so any input/observation/comments would be much welcome

author: ajb
author_rank: Super Contributor
timestamp: October 01, 2021, 10:06:44 pm
content: Assuming your simulation model is reasonably accurate, a stable simulation and unstable real-world circuit implies a problem with the layout. Can you show your real circuit?

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: October 01, 2021, 11:18:32 pm
content: Siliconix published a good stable design many years ago. Note where the 100k resistor connects.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 01, 2021, 11:45:32 pm
content: 741, with what supplies?No additional compensation is shown, and their transistor is only a few hundred pF, whereas OP's is some 4nF at 5V -- and rapidly changing with voltage, at that; the nonlinear (distorted) waveforms should be no surprise. The 100k is irrelevant, wherever it's connected.C2 shouldn't be necessary, and C1 is rather large. First adjust R1 for stability, or as well as you can over the desired voltage range; then lower C1 to maximize response rate while maintaining stability.Note that load voltage is a free variable, and the output of a current source should indeed be rather... "squirrelly". That is, it may nearly oscillate into an inductive load. You need to make sure that that ringing is always decaying. Easier to just sacrifice the AC impedance, and dampen the output with a R+C (from drain to GND). Especially as you have a huge amount of feedback capacitance at this voltage, so the output voltage does matter (both to stability and in terms of feedback voltage affecting the loop).Tim

author: magic
author_rank: Super Contributor
timestamp: October 02, 2021, 06:38:45 am
content: The simple way:Move Rgain1,Rgain2 so that they divide the input signal going into U2.Remove U1 and connect R9 to the shunt.One opamp less to worry aboutThen tweak R1,C1, maybe remove R1.editC2 isn't unnecessary, it's actively harmful because it adds 90° phase lag above the C2·Rgain1 corner. It may be the reason why you needed to insert the R1·C1 zero. Why?Quote from: Conrad Hoffman on October 01, 2021, 11:18:32 pmWhat the 100k is actually supposed to do there?

author: BelgianEngineer
author_rank: Contributor
timestamp: October 02, 2021, 07:32:44 am
content: Quote from: Conrad Hoffman on October 01, 2021, 11:18:32 pmI was actually trying to avoid that one so I can skip the power resistorQuote from: T3sl4co1l on October 01, 2021, 11:45:32 pmThe 100k is indeed irrelevantI have tried to compensate at input level by adding a 4.7u, 3Ohm RC damper between drain and source. Oscillations still there. Would it really make a difference if I connect the damper to ground and not to source?Would it not make sense to have a C2 such that a pole is formed and the control loop then tune C1 to have a zero at that same frequency? Eventually ending up with a nice straight line around -20dB/decade on the Bode plot? My aproach is to tune C1 and C2 to have their pole and zero at the same frequency then tune R9 to change overall circuit gain and define the cut-off frequency. Currently it is tune for a cut-off frequency around 70kHz which may be too high.In the current state, the circuit runs without oscillations if C1 is completely shorted. As soon as I had an value of C1 oscillations appear (tried 1p to 100n).Quote from: magic on October 02, 2021, 06:38:45 amThe 100k is indeed irrelevant.I will give it a try without C2 but I would like to have C1 in there to remove any steady-state offset like an integrating action would do.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 02, 2021, 08:31:33 am
content: The effect will be that U1 and C2 act to delay (and phase shift, and attenuate) the feedback signal, which is already in part delayed by M1's capacitance. Yes, placing C1*R1 zero at the same place restores phase margin, at least due to one of those limits; but doesn't solve the other one. Probably better to have U1 run faster, and just deal with the loop as it is.The amps are only 1MHz GBW anyway; they're probably the limitation more than M1's capacitance, or their drive capability (along with R2), really.For which, all you can really do is set the control loop (R9 * C1) below the lowest pole, so that loop gain drops below 1 before phase shift rolls around. Which will be U1's GBW divided by gain, or about 50kHz.Did you try many values for R1? It seems suspiciously low; but loops are weird sometimes, and it's not obvious what value is really right, as such. (Again, the biggest difficulty is the complexity of M1's capacitances, being significant between all three terminals. It also has very high transconductance. It manifests as a mix of poles and zeroes, and this also makes it dependent on load impedance.)Tim

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 02, 2021, 08:39:55 am
content: What about a simple negative comparator, reducing the reference instead amplifying the shunt?Only needing to slightly tweak the reference to overcome any small offset due the very low input signals.Don't hit me, it's been years since last time I worked with op-amps

author: Kleinstein
author_rank: Super Contributor
timestamp: October 02, 2021, 08:45:27 am
content: The 2nd OP does not really help much. If at all it could make sense if one has a lower noise / lower dirft OP for the extra amplifier and a higher output drive one to drive the FET. There is no need to make the regulating part high impedance, so one could consider a low noise / low dirft OP there as well and no need for the 2nd OP.A 2 OP combination may make sense to combine a low noise BJT based OP (like OPA211 or LT1128) with an AZ op (like ADA4523) to correct for the small DC error / low frequencies ( < 0.1 Hz).The way to get away with a smaller shunt resistors and thus less power would be 1 good OP, not 2 relatively noisy ones.To allow also good performance with a smaller current one could use only 1 of several parallel channels for low currents, possibly a seprate low current one.A large MOSFET may want some extra higher current driver, if the regulator loop really has to be fast.Another point to add for stability is some RC snubber at the output. Without it gets tricky with a inductive load. Depending on the main circuit one can get away with a relatively small capacitance, but it would hardly work without.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 02, 2021, 09:08:13 am
content: I don't mind the shunt amp, because that can be useful in a variety of cases, about which I haven't asked, because they're reasonable enough to assume. But if that assumption fails, it's certainly an optimization that can be done.Example: REF is distant from shunt, thus some CM error may arise. Diffamp accounts for that. Now, it's not a diffamp in the sim, but it can very easily be changed to such, or maybe it's just drawn as a noninverting amp for convenience while the real thing is actually slightly different. (Which would be slightly disingenuous as far as what the model is representing, but far from egregious.)Another example: the shunt signal is being read elsewhere in the circuit, say going to an ADC. A couple tens of mV isn't going to cut it there. At least, on most generic ADCs. (Some do have pipelined amplification available, ATXMEGA for one; though the accuracy may suffer. Or if a low sample rate is acceptable, some high-bit (16+) delta-sigma type converters have quite sensitive (and accurate) input gain options.)And yes, using different amps is another option. Not that microvolt precision amps are expensive these days, but you only need the one, and can use something jellybean for the error amp otherwise.Tim

author: iMo
author_rank: Super Contributor
timestamp: October 02, 2021, 09:26:06 am
content: In LTSpice you can make "stability analysis".Try it and show the results..The guide:https://www.analog.com/en/technical-articles/ltspice-extracting-switch-mode-power-supply-loop-gain-in-simulation-and-why-you-usually-don-t-need.html

author: BelgianEngineer
author_rank: Contributor
timestamp: October 02, 2021, 12:40:27 pm
content: Quote from: imo on October 02, 2021, 09:26:06 amI did the stability analysis and in simulation it shows good behavior with around 90deg phase margin so I assume something is wrong or badly modelled in the simulationHere are my latest observations:Cannot get anything satisfactory changing the values of R9, R1, C1. That does not mean that there is not a sweet compensation spot but I cannot find it...Shorting C1 makes it stop oscillating and keeping the current sense opamp circuit now has the benefit to reduce a bit the setpoint value needed on U2 positive input (which is important because the goal is to use a DAC there)Some instability appears in pure proportional if I remove the RC damper between drain and sourceQuote from: T3sl4co1l on October 02, 2021, 09:08:13 amCould you tell me more? Wouldn't a non-inverting amplifier and differential amplifier be the same in this case since one branch is connected to ground?

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: October 02, 2021, 12:48:38 pm
content: Everybody says the 100k is unnecessary in the Siliconix design but I remember building variations without it, and they weren't as stable. Never did a sim on it.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 02, 2021, 03:07:41 pm
content: The 100 K directly around the OP helps a little with another problem: it limits the integrator windup when the MOSFET goes into saturation, all the way on. However as a sideeffect the 100 K in direct feedback also reduced the accuracy. It should not help with the more usual instability problem.A differential amplifier would make sense if the low side of the shunt is not exactly the same ground as the setpoint signal. The low side shund may very well be a 4 wire type and thus the shunt low side not exactly at GND. One could still used the low side as GND for the set point (at at least a divider for the set values), but it starts to get tricky when there are 2 such channels in parallel for higher power.

author: Pulsepowerguy
author_rank: Regular Contributor
timestamp: October 02, 2021, 03:52:48 pm
content: Try adjusting R2 (gate resistor) up or down and observe the results.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 02, 2021, 03:59:35 pm
content: Quote from: magic on October 02, 2021, 06:38:45 amAgreed.Anyway, the extra shunt amp U1 is completely useless in this case IMO. And is even harmful. Even without C2, it can bring you a number of issues.I would also start without any compensation, and would add compensation after thoroughly testing it only if absolutely needed in your case.The basic "Siliconix" arrangement shown above (it's barebones) is what is suggested in a great number of app notes, of course with various opamps and mosfets.The need for compensation (and its characteristics) entirely depends on the choice of components (opamp, mosfet) and the characteristics of the load itself.

author: Terry Bites
author_rank: Super Contributor
timestamp: October 02, 2021, 04:24:20 pm
content: I dont see the purpose of the 100k. I suspect that the LT1013 cannot drive the Mosfet very well. Chuck a +1 buffer into your simulation. Does that help?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 02, 2021, 05:35:28 pm
content: Quote from: BelgianEngineer on October 02, 2021, 12:40:27 pmIndeed. But if GND has slightly different potentials in different parts of the circuit (say some ~mV from current drops through the ground plane, to whole ~V in more serious cases e.g. high-side sensing), it would be valuable to subtract out that difference, hence the differential amplifier.Tim

author: Pulsepowerguy
author_rank: Regular Contributor
timestamp: October 02, 2021, 09:36:27 pm
content: The LT1013 probably doesn't work well on single supply with it's inputs so close to zero (the one looking at the shunt R). Use a true single supply part or add a negative rail.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 02, 2021, 09:56:22 pm
content: The LT1013 is a single supply OP, so no problem there. However it is not especially low noise or very low drift and also relatively slow. With a low shunt the OP has to provide some gain. With a factor of 20 as in the original circuit the LT1013 is quite slow. So one may want a faster OP with less noise and better accuracy. For the simulation the LT1013 may still be not such a bad start.

author: Pulsepowerguy
author_rank: Regular Contributor
timestamp: October 02, 2021, 10:07:17 pm
content: I now think the problem is the miller capacitance of the FET. A cascode arrangement with a depletion mode FET feeding the drain of the controlled FET helps a lot. This can also be done with another enhancement mode FET and a dc bias for its gate. The penalty is a higher limit to the minimum operating voltage of the current sink.The extra, shunt-reading opamp is not needed, just as others have suggested.

author: KE5FX
author_rank: Super Contributor
timestamp: October 02, 2021, 10:52:32 pm
content: The ~100 kHz oscillation makes me wonder about the (1 MHz) GBP of the LT1013. Try a faster opamp just to see if it makes a difference?And yes, as suggested above, I'd use + and - supplies, at least for initial debugging. Does the oscillation occur throughout the operating range, or only near ground? Capture the power-up behavior with the scope and see if that offers any useful clues.

author: David Hess
author_rank: Super Contributor
timestamp: October 02, 2021, 11:12:55 pm
content: U1 is not doing anything useful, and is complicating the frequency compensation. Remove it and tie the ground end of R8 to the sense side of Rgain_1.The output resistance of U1 and the input capacitance of the big MOSFET cause more phase lag. The 50 ohm gate resistors helps but maybe not enough. This also varies with operating point because it depends on the transconductance of the MOSFET which varies with drain current.

author: Pulsepowerguy
author_rank: Regular Contributor
timestamp: October 03, 2021, 03:00:06 am
content: It is due to the miller capacitance (and possibly the varying transconductance) interacting with the inductive reactance in series with the voltage source. I simulated it in LTspsice, and an added cascode element makes it stable. See attached. Play with it and see for yourselves.

author: Pulsepowerguy
author_rank: Regular Contributor
timestamp: October 03, 2021, 03:11:51 am
content: Quote from: KE5FX on October 02, 2021, 10:52:32 pmThe inputs of the opamp across the 50mOhm resistor are always just a few millivolts from 'ground'.

author: 2N3055
author_rank: Super Contributor
timestamp: October 03, 2021, 07:33:30 am
content: When you say phase/gain margin, do you think phase/gain margin of the whole system including two opamps each with it's own mulitple pole response... an then output opamp is driving large capacitive load..Excerpt from HP Load schematic. Make note of the opamp choices, and how shunt amp is connected. And multiple compensations happening.Also, negative supply helps opamp pull current out of gate..Excellent analysis by Jayhttps://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg309035/#msg309035Read and learn...

author: David Hess
author_rank: Super Contributor
timestamp: October 03, 2021, 08:53:41 pm
content: The reason for difference amplifier U1 in yours, and U14 in the HP design, is to implement remote sense of the voltage across the current shunt because the current into ground would otherwise cause a considerable error. If you do not need that and can implement a single point ground at the bottom of the current shunt like I described, then it is not needed.The HP implementation also uses a fast precision operational amplifier to remove the input offset errors from the error amplifier but if the operational amplifiers are the same type, then it does not help.

author: 2N3055
author_rank: Super Contributor
timestamp: October 03, 2021, 09:26:55 pm
content: Quote from: David Hess on October 03, 2021, 08:53:41 pmDavid,like usual, all very correct.Also note that MC34072 is a Opamp specified to directly drive (and be stable) for loads up to 10nF.Also make note, that it is also single supply specified opamp, it's common mode input voltage range includes ground, but HP decided to run it from symmetrical supplies.. It also have symmetrical source/sink AC frequency response...All of that contributes to performance. And then you have several pole compensations, local and global..Making a well behaved electronic load of production quality is deceptively hard.. It look quite simple, but if you have to make it stable for all possible (or at least for as many of possible) scenarios, gets a bit more involved.There are also nice tricks in that circuit, like safe OFF, a current summator (from all the stages) etc etc.Voltage and current measurements and control are all ground referenced which simplifies control and readout..Service manual with full schematics and detailed theory of operation and troubleshooting guides is available and is great read for people interested in electronic loads. There are many "AHA!" moments in that manual...

author: Zero999
author_rank: Super Contributor
timestamp: October 04, 2021, 05:54:34 pm
content: Why are you using such a big MOSFET with a huge capacitance? The current is only 620mA, at 5V, giving a power dissipation of just 3.1W.The old school IRF510 would be better, as it has a much lower gate charge and is more than capable of dissipating the power.

author: Terry Bites
author_rank: Super Contributor
timestamp: October 04, 2021, 06:03:59 pm
content: Yes. Cascoding is a good idea.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 04, 2021, 06:24:38 pm
content: The cascode can help with stability, but it also adds a little to the on_resistance.Ideally the lower MOSFET can that be a relatively low voltage (e.g. 40 V) and low power type. Only the upper one would be a higher power, higher voltage (e.g. 400 V) one with a good SOA. So the lower voltage one can be lower capacitance and still relatively low R_on.For higher DUT voltages this is not a problem, but with low voltage (e.g. dicharge a singel battry cell) this can be a bit limiting. The low voltage drop out limit would also need to be higher.

author: Zero999
author_rank: Super Contributor
timestamp: October 04, 2021, 09:45:51 pm
content: Quote from: Kleinstein on October 04, 2021, 06:24:38 pmTrue, but a low on resistance is probably not necessary in this application.

author: David Hess
author_rank: Super Contributor
timestamp: October 05, 2021, 09:58:22 pm
content: Quote from: 2N3055 on October 03, 2021, 09:26:55 pmAn operational amplifier specified to drive a large capacitive load refers to stability and not performance. Frequency response is limited by the pole formed by the open loop output resistance and load capacitance, and the slew rate is limited by the output current limit into the output capacitance. Both are improved by adding a high current output buffer. There are also ways to use operational amplifiers in parallel to lower the output resistance and increase the output current.QuoteCheck out the article "My Approach to Feedback Loop Design" by Phil Perkins found in "Analog Circuit Design, Art, Science, and Personalities" edited by Jim Williams where he describes 3dB/octave 45 degree phase shift networks.QuoteA lot can be learned by reverse engineering old service manuals. I fear later generations have lost this source of knowledge.

author: Terry Bites
author_rank: Super Contributor
timestamp: October 08, 2021, 02:43:26 pm
content: I had a go at simulating a current source and there are two dificult probems to overcome especially with a rapidly changing load or current setting. I'm aiming at a 0.05 to 5A @ 50V and at least 0.1% accuracy and a big cooler of course.Getting the compensation and MOSFET drive are crucial. I am revisiting Darlingtons. Oh yes! If you mearsure the current after the control element then base currents are not a problem. They are so much easier to drive. They will dissipate almost the same power as a MOSFET, I*V is I*V. A Darlington will allow for a bit more compliance headroom as well. A Sziklai pair will save another 0.7V of headroom.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 08, 2021, 03:20:04 pm
content: 5 A and 50 V, if at the same time is a lot of power. This would be likely with more than 1 channel in parallel. Parallel channels also reduce the drive needs for the MOSFETs. For the lower current one could just turn off all except one channel and this way get a little more resolution on the shunt.With a darlington transistor the compensation is not that easy: they tend to be slower than MOSFETs. With a gain of some 1000-10000 an accuracy in the 0.1% range gets challanging. This is especially at lower current, as many darlingtons have a base emitter resistor and this would change things at low currents. There is allways a minimum drop of some 0.7 V to 1 V at higher current.With 50 V a cascode configuration the lower FET could take away some 10 V from the main MOSFETs, so some load sharing also for the 2 FETs in series. If high speed is wanted this would be definitely an option, as the low FET in the cascode could be a lower voltage one and thus lower capacitance.