Vias and Capacitors - Page 1
Forum section: electronics / beginners

author: Nikos A.
author_rank: Regular Contributor
timestamp: June 25, 2019, 07:43:03 am
content: Hi everyone, one more question by the newbie..Actually I have to questions..1. Why they say that you shouldn't attempt to share vias between capacitors? Keep the ratio between components and vias 1:1...a. How does this influence the designing? I've never seen a documented answer.2. I've seen in many designs to apply two or more vias for each cap.. I've read that this method reduces vias' parasitic inductance but I cannot understand how this is working in practice.. Vias inductance it isn't additive?

author: Zero999
author_rank: Super Contributor
timestamp: June 25, 2019, 07:52:31 am
content: Yes, vias have inductance. As with resistance, inductance is only additive, if it's in series. If multiple vias are used for one capacitor, the current will be shared between each via, therefore they will be in parallel, not series. Connecting inductors in parallel reduces the over all inductance.The formula is the same for resistors in parallel. LTOTAL= (L1-1+L2-1+L3-1)-1.Reducing the inductance is good, because it lowers the impedance, especially to high frequencies, thus keeping the supply voltage more stable.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 25, 2019, 08:01:20 am
content: Exactly like Zero999 said, and what comes to sharing vias, sharing helps you put higher effective number of vias for each cap without running out of space, and hence helps in reducing impedance.Sharing may be bad if you have different supplies which could couple noise. In this case, you sometimes want to intentionally add individual trace inductance (or even an explicit inductor), then have the capacitor right at the load, and that load alone. For a typical digital circuit having a few digital supplies, I would just share the vias instead, to minimize impedance.

author: Rerouter
author_rank: Super Contributor
timestamp: June 25, 2019, 08:08:00 am
content: This mainly falls under rules of thumb, does not mean the best solution in all cases, just the least likely to cause issues.1. They say not to share Via's and equally to use multiple vias to reduce the inductance of that given decoupling capacitor, in reality it only gets important when your dealing with either fast edges, low noise or high current signals. as these are when that inductance can cause issues for the single via per capacitor, and crosstalk via the return path for low noise signals.Fast Edges - As the frequency increases away from DC, more and more of the return signal (your ground current for most things) starts following the path of least impedance instead of the path of least resistance, this path generally follows the signal trace as close as possible, and how it could be described is having the smallest loop area, so for each decoupling capacitor you ideally want it so the current can hop adjacent to your signal or under it in as short a distance as possible. more distance = more inductance = larger loop area ~ poorer decouplingLow noise - Most people like to think of a via to a ground plane as a perfect 0 ohms, in reality it has resistance and inductance, so lets say you have a nice high resolution ADC with a few uV / bit, well the internal reference voltage and other parts shift up and down in voltage with that devices Ground pin, lets say you share a via to ground with something else, say a little status LED, or something that takes gulps of a few mA of current. the voltage across that via to the ground plane can cause your ADC to jump up and down in reading,High current - Any time the current changes, inductance is a problem, Equally at a certain point heat dissipation is an issue. so sprinkling lots of vias around something you expect to take large gulps of current e.g. a GSM modem, (can draw spikes of 1.2A) helps improve the decoupling to that deviceInductance adds like resistance, you have 2 vias in series you have double the inductance, you have 2 vias in parallel you have half the inductance.Actual rule of thumb to follow- Pay attention to the return path of a signal, e.g. where its ground current has to flow to keep close to the signal, the smaller this loop the better, this is why they recommend a ground plane via where a high speed signal changes layers. beside it is just as good as below it- Keep decoupling capacitors close to the device pins, and dont forget the length of the ground path, Usually its better to keep the ground trace to the chip on the same layer where possible,- For decoupling capacitors, the current to your device should flow through the decoupling capacitor pads, this way the capacitor filters down any current spikes from your device.

author: Nikos A.
author_rank: Regular Contributor
timestamp: June 25, 2019, 09:23:54 am
content: Thank you for your answers!!So, using vias in parallel reduces the mounting inductance and hence the impedance, creating a lower impedance return path. Also, by keeping the return path as short as possible minimizes again the inductance.. So, the key element is a low impradance/inductance return path for optimum decoupling..Furthermore, by sharing vias between components/pins with different current drawn, there is the danger of inducing noise between them..Tell you the truth I am facing some difficulties most of the time to identify the current loop, but I guess that I am going to be better through practice..Quote from: Rerouter on June 25, 2019, 08:08:00 amCan you give me some more explanation on this?

author: Rerouter
author_rank: Super Contributor
timestamp: June 25, 2019, 11:41:44 am
content: most modern IC's have a ground pin and supply pin either directly next to one another, or close enough to do on the same layer most times. a trace / fill on the same layer placed well can be much lower than the 2 via hops if you went through the ground plane,Went digging and found 2 good example PCB's from images I made for forum replies,The first image was a switch mode converter, and me drawing out the current loop to show how to keep a certain area of the circuit as quiet as possible, I don't know what the orignal cad package was, as this I more or less edited into shape with paint to convey what I felt the best layout of the chips I would produce.The second image was someone layout out something like 1.8GBps LVDS trancievers, he uploaded his Kicad project so I had a spin at improving its chances as best I could. For the left most chip take a look at C5 / C6 above it, middle chip just a ton of capacitors with solid ground connections (make production a pain but as there would be a lot of ground current wanted as thick as possible, and the right chip tucked in the bottom right corner. All of these decoupling caps where places as closely as I could manage with nice low inductance (for most traces it was not really possible to thicken them up)The second image also shows what I mean about grouping I was taking about, all 3 chips where routed out on there own, then packed together,And the third image, on the lower right there is a little capacitor on the Vcore supply just crammed up next to the pins, (I'm also particularly proud of this layout pic because it was my first go at length matched USB routing,