What do you think about this Soft Start PMOS for 48V and 10A - Page 1
Forum section: electronics / projects

author: PeLa
author_rank: Contributor
timestamp: February 21, 2022, 08:52:19 am
content: Hi everyone,I have to build a soft start circuit for a hand full of motor drivers as I have been having problems with inrush currents. What do you think about this idea?0. The system is OFF1. Power is switched on instantly, simulated by the pulsed source2. The capacitor of the load C2 charges up via R4. At the same time C1 charges up. At the same time M2 (depletion mode N channel FET) opens.3. Eventually the potential at the Gate of the P channel FET gets below the gate threshold and (M1) opens.4. The system is now ON5. Power is switched off. A big current spike is observed at D7.6. The depletion mode N channel Fet (M2) conducts, the gate capacitor (C1) discharges through M2. The load discharges (C2 discharges through R3).7. The P channel FET M1 stops conducting.8. The system is OFFAny thoughts on this design? What can be improved without using a fancy softstart controller, which cannot be purchased at the moment anyway?[edit: modified the zip file to not include logs, etc.]

author: Someone
author_rank: Super Contributor
timestamp: February 21, 2022, 09:16:37 am
content: That scheme works well (have similar designs in the field/production) but you need to be careful with the SOA of the fet at M1, be sure to simulate corner cases.A few things:an npn transistor at M2 is an option, whatever is convenientI found better dynamics referencing C1 from the drain rather than the sourceconsider pulling R2 up to the input rail rather than to ground

author: PeLa
author_rank: Contributor
timestamp: February 21, 2022, 10:09:24 am
content: Thank you, Someone!Referencing C1 from the drain of M1,and R2 between gate and source of M1 seems to help any potential overshoot, but does not seem to soft start. - At least not in my simulation.Is the circuit in the image below what you suggested or did I misunderstand something?Cheers,Pete

author: Someone
author_rank: Super Contributor
timestamp: February 21, 2022, 11:49:43 am
content: Quote from: PeLa on February 21, 2022, 10:09:24 amYou are right, I checked through the simulations here and having C1 on that side relied on known ramping/limits of the source and load. Back to the source for C1 !

author: PeLa
author_rank: Contributor
timestamp: February 21, 2022, 12:56:33 pm
content: Thank you so much for this very helpful reply!!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 21, 2022, 05:19:36 pm
content: There's so much weirdness going on here, I'm not sure about the intended functionality --What are all the diodes besides D4 and D9? What type(s)?Why the inordinately massive M2?And a depletion mode at that, so it's always on regardless of any Vgs accessible in the circuit?Why M2 + R5 at all, there's already R2? (Or alternately: why R2, when R5 is always on, and dominates?)Why is C1 so large, and why are there so many low-impedance components in parallel with M1 G-S (making it prone to oscillation)?Why is V1 described as "switched off", but it's a PULSE source meaning itforcesthe connected node to the specified voltage, with rise/fall times of 1µs evidently?Why R1? R4?Have you considered current limiting? Fault protection? These will take much more circuitry, but can be done without ICs.Tim

author: PeLa
author_rank: Contributor
timestamp: February 22, 2022, 07:28:28 am
content: Hi Tim,thank you for the questions. They made me go over it again and that is always a good thing. Let me try and explain:Quote from: T3sl4co1l on February 21, 2022, 05:19:36 pmThe 12V Zener D4 makes sure I don't blow M1 with -48V at the gate.The 12V Zener D9 makes sure I don't blow M2 with unreasonable gate voltages.I will likely use a PDZ12BGWJ, because I've got them in a drawer somewhere.Quote from: T3sl4co1l on February 21, 2022, 05:19:36 pmI ordered a BSS169H6327XTSA1‎ as M2. I forgot to change it in the simulation.Quote from: T3sl4co1l on February 21, 2022, 05:19:36 pmM2 is always on while power is applied and discharges the large C1, when power is removed. In this way the soft start function works more than once in a row, when switching on and off the device in quick succession. If you know of a better way to do it, I am all ears! [edit: on closer inspection, it seems it does not do what I want it to do...]Quote from: T3sl4co1l on February 21, 2022, 05:19:36 pmAre you primarily talking about C1 and D4 as low impedance component here? Would it make sense to put a resistor between C1 and the source and D1 and the source?Not sure what else I would consider low impedance between source and gate... R2 charges C1 slowly, D4 limits Vgs to 12V, D5 seemed like a good idea to protect the gate of M1, R5 limits the discharge current of C1 to below 100mA, D7 is a fly-back diode that passes lots of current, when the device is turned off, R4 slowly charges the load capacitor C2, while M1 is still off.C1 is large to get a slow down the M1 FET turn on. I tried lower values but this gives me the slow turn on, I want... I'd prefer a smaller value, too.Quote from: T3sl4co1l on February 21, 2022, 05:19:36 pmV1 is described as switched off because I did not know any better, and has a 1us rise because I thought that would be a reasonably fast rise time that I can try and slow down using this circuit. How do I simulate a switched off source in a better way? [edit: see next post. it's apparently not that difficult]Quote from: T3sl4co1l on February 21, 2022, 05:19:36 pmR1 can be ignored and should be removed. True. It's part of the load.Quote from: T3sl4co1l on February 21, 2022, 05:19:36 pmI haven't yet. But I should. Good advice is welcome!

author: PeLa
author_rank: Contributor
timestamp: February 22, 2022, 02:23:16 pm
content: I have simplified the model. This works ok (in simulation) as a soft start circuit, but has the problem that the capacitor responsible for the delay (C1) does not discharge fast enough, when power is removed, i.e. when the switch stops conducting. Especially, when the load is not 5 Ohm as shown in the model but e.g. 50 Ohm, this circuit has a recovery time that is too long. The big load capacitor C2 stores enough energy to keep C1 charged for a while, so the next time the switch starts conducting, the gate is already at a voltage that causes M1 to conduct.Does anyone have a good idea how to discharge C1 relatively quickly (let's say within 200ms), when the switch stops conducting?(the attached image shows the soft start: blue is the voltage at the source of M1 and green is the voltage at the drain of M1)

author: Someone
author_rank: Super Contributor
timestamp: February 22, 2022, 10:17:10 pm
content: Quote from: PeLa on February 22, 2022, 02:23:16 pmYou have too many variables in such a system: is power efficiency important? what are the characteristics of the power source? what possible ranges of load and source (including their dynamics and reactance) are expected?Rather than pulling the gate capacitor all the way to the other rail and clipping it with a diode,ifthe input voltage is non-varying then you can set a resistor divider to the desired gate voltage directly. For the same startup time that will have a shorter turn-off (x5-10 faster depending on where you put the gate threshold).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 22, 2022, 11:13:32 pm
content: Ah, that's more normal.So, gate impedance, as in impedance to the gate -- anywhere in the S-G loop would do but simply a series resistor at the gate is most likely. For a beefy transistor like that, just a few ohms should do. It can be a few kohms and it doesn't matter, everything's quite slow here.Note that the input side has no discharge when it's switched off, so the only path for the gate capacitor to discharge is through the transistor itself, and load. And it'll turn off once it's down to a few volts, and discharge will level off to around Vgs(th).A smaller capacitor can be used, and larger resistor; doesn't really matter. Gate leakage is quite low, that's all you need to overcome.To get faster discharge, a S-G resistor can be used; just in parallel with the zener. This increases the minimum turn-on voltage, since it makes a voltage divider at low voltages (before the zener is conducting). I'm guessing input is always in the vicinity of 48V so that's not a problem. (Indeed you can dispense with the zener if the input really is consistent, but the zener is a good precaution to protect the gate in case anything weird happens.)Note that, for fast charge rates, the energy stored in C2 must also be dissipated in M1. Which is 5.5J, so good luck getting that into any single-die transistor for short periods of time (10-100us?) -- even the largest transistors hardly do 1J (often shown in the avalanche rating, which is also a short duration, high dissipation test).For longer startup times, the energy rating goes up -- basically, more of the die, lead frame, component body, etc. is able to heat up -- but so too your load dissipation. For short risetimes (much less than C2*R3), you can essentially say it's charging a capacitor and that's it; but for longer time scales, the load current will have a significant impact on transistor dissipation.The limiting case being for an extremely slow rise, which will dissipate a maximum continuous 120W in the device (because the load resistor is 480W continuous, maximum power point is at half output voltage or 24V, at which each device (M1, R3) is dissipating 120W for a total of 240). Which clearly isn't going to happen with that part (but a TO-247 on generous heatsink, could).Somewhere between these extremes, you need a device big enough to provide adequate pulsed-power dissipation. This is shown on the SOA (with a series of curves for different pulse widths) and transient thermal impedance (curves for different duty cycles; this is a single cycle event).I don't know offhand just how big of a device you'll need for this much capacity, and what risetime will be best suited to it. I have a sneaking suspicion that a TO-247 or D3PAK style device will be needed.BTW, if you want a smoother voltage slope, consider adding some capacitance from D to G (again, keeping a resistor to the gate pin itself, to stop possible oscillation). This is effectively multiplied by Miller effect, so not much is needed (say 1/100th that of G-S). The reason for the lumpy rise is twofold: one, transconductance increases with Vgs, so it accelerates to begin with (into a fixed load resistance, it's usually about a parabola); two, Cdg internal to the component (Crss on the datasheet) serves the same function but varies wildly with Vds. Which is probably in part why your simulation kind of rounds off at the top corner, but also it's not clear how accurately the SPICE model has captured this characteristic (it's so nonlinear, SPICE has trouble representing it, and often a custom model is needed in addition to the somewhat-more-ideal MOSFET model used internally), so you may find different results in practice.Tim

author: PeLa
author_rank: Contributor
timestamp: February 23, 2022, 03:07:45 pm
content: Hi Tim,Thank you very much for your help!Quote from: T3sl4co1l on February 22, 2022, 11:13:32 pmYes. That's my main problem. Hence my failed attempt to discharge the cap using a depletion mode n channel fet.Quote from: T3sl4co1l on February 22, 2022, 11:13:32 pmI have reduced capacitance and increased resistance.Quote from: T3sl4co1l on February 22, 2022, 11:13:32 pmI did not do that yet...Quote from: T3sl4co1l on February 22, 2022, 11:13:32 pmYeah... that's a lot. I wonder how many I'll break until I have found an acceptably slow rise time to reduce the inrush and and acceptably fast rise time to not break the FET. I'll have a look at different packages as per your suggestion.Quote from: T3sl4co1l on February 22, 2022, 11:13:32 pmI found that C3 in the image below causes a big spike so I put a small resistor in series with it.In spite of your increadibly helpful advice, I still haven't understood, how to best discharge C2. - I assume it would have to be actively discharged somehow... I did get a link to a circuit that should do something similar. But I haven't had time to sit down and understand.Attached is the current iteration.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 23, 2022, 05:46:42 pm
content: What's the minimum load (maximum R3)? Are frequent power interruptions a problem? For how long at a time?Once M1 has turned on, it's not going to turn off until about 15V, at which point Vgs should be low enough not to deliver too much inrush current when it comes back on. It's hard to see at this zoom but I think that's more or less confirmed with the series sweep.Since M1 is "stuck" on, and has a body diode anyway, there's no way to sense the input turning off without also measuring load current, rate-of-change, or inserting a series diode or something. After all, C3 is literally powering the load while the input is off; who's to say there's anything wrong with that? So, options are either something that isn't very reliable (if the input simply fluctuates as a normal thing, dV/dt is out), increases losses (diode drop, or a shunt resistor to a potentially lesser extent), or requires higher sensitivity (current sense amp?). For which a hot plugging or load switch controller IC would be far better suited.Tim

author: Someone
author_rank: Super Contributor
timestamp: February 23, 2022, 10:40:07 pm
content: Quote from: T3sl4co1l on February 23, 2022, 05:46:42 pmStuck on indeed! Most fets like this have reverse conduction characteristics as sturdy as forward, and body diodes with lower forward voltages than 0.7V silicon diodes (or transistor base junctions).