Class D: Half Bridge vs Full Bridge Loss Calculations - Page 1
Forum section: electronics / projects

author: Evan.Cornell
author_rank: Regular Contributor
timestamp: August 16, 2022, 09:26:52 pm
content: Given two different Class D amplifier power stage topologies:half bridge (2 FETs) with bipolar power supplies (say +-24V, output switch node is GND-centered)Full bridge (4 FETs) with unipolar power supply (+24V, each of the two output switch notes are +12V-centered)Both of these power stages have maximum theoretical output of ~17Vrms (24/sqrt(2), yeah I know it's lower in practice).What would be the sort of back-of-the-envelope power stage power loss calculations? For example, "Half bridge with bipolar supplies will have half the switching loss, but FETs need to withstand twice as much voltage..." or maybe it's "total FET switching loss is the same between these two scenarios because half-bridge has twice the voltage on each FET as full-bridge configuration, so each FET in half-bridge will see twice as much switching loss as in a full-bridge..."

author: sam[PS]
author_rank: Contributor
timestamp: August 22, 2022, 02:00:47 pm
content: The thing with that kind of high power switching gizmo we tend to think about the pulses when in fact the devil is in the transition. What happen during a transition ? Let's start with the half bridge, if you switch both MOSFET at same time they will probably NOT have a matching transition curve. The result is potentially momentary shortcut, overheating and failure (don't ask me how i know). In any way it's always more consumption than expected as at some point both mosfet will be in resistive mode and forming a voltage divider. As a result you get both erratique signal and in any case more heat than expected. Badly optimized you'll get more loss out of transition than from the RdsOn. Another aftermath is unwanted noise/distortion that are problematic if the intended use is high end audio (not a problem for a boombox). To avoid that the first approach is to not command the two MOSFET at the same time but carefully tune the dephasing of the two commands. The extra step is to not command the MOSFET with a binary signal (i.e. : directly your PWM or PDM audio signal) but optimise the grid voltage curve for each switching phase. The good quality integrated classD amp IC do both of that. That's why that kind of circuit is super hard to DIY properly. And i haven't even talked about EMF and PCB trace impedance messing up your painfully tuned timing.Now for the full bridge, well take all those trouble and now square them. You now got a circuit that is order of magnitude harder to fine tune to optimize transition. In other word in a world where both time and money are limited that mean they end up indeed orders of magnitude less optimized and you end up with both a less efficient amp and a lower audio quality. Not that it is not possible to make a full bridge class D amp performe as well as a half bridge one (minus the 2x RdsOn you mentioned), just it's very unlikely to happen.As for how to precisely calculate the resulting loss... Let's say it's complicated. Better of measuring. The state of the art in research today is to use IA to learn each transistor's behavior and generate as good a compromise commande as possible. So it's indeed by measure and per component.Just my 2cts...

author: NiHaoMike
author_rank: Super Contributor
timestamp: August 23, 2022, 03:12:43 am
content: If you use full bridge with in phase carriers, in theory there would be no net voltage to the load with no input signal yielding very low idle losses.The vast majority of audio amplifiers nowadays are full bridge.

author: langwadt
author_rank: Super Contributor
timestamp: August 23, 2022, 07:57:07 am
content: Quote from: NiHaoMike on August 23, 2022, 03:12:43 amhttps://aetechron.com/Service/bca%20whitepaper.pdf