Should one gate SPI signals to an ADC or DAC, to reduce noise? - Page 1
Forum section: electronics / general

author: peter-h
author_rank: Super Contributor
timestamp: April 24, 2025, 02:51:57 pm
content: If you have a product where an SPI is used to drive multiple peripherals, the data and clock wires go to every device, and then a /CS selects the device being spoken to.This distribution of the two signals has the potential to create noise all over the place. Normally, with an ADC or DAC, the SPI transaction has no edges during the conversion (unless one is polling the ADC for EOC, which is sometimes necessary) and that should minimise noise, but you can't do it if driving multiple devices - unless you gate the two signals with the /CS.

author: Siwastaja
author_rank: Super Contributor
timestamp: April 24, 2025, 06:38:08 pm
content: Gating them is indeed done in some high-precision reference designs, have seen it. I think the easiest way to know what difference it makes is to test with prototypes. Estimating or simulating it would be pretty complicated and it's hard to guess if the added disturbance is at -50dB or -100dB.Also don't forget the obvious thing of slowing the edges down with series resistance at driver. SPI signals being unidirectional, it's obvious where to put source termination.

author: thm_w
author_rank: Super Contributor
timestamp: April 24, 2025, 11:19:37 pm
content: Needs context, if its 8 or 12 bit ADC, unless very poorly laid out, and lacks any filtering, I can't see it making much difference.24-bit ADC that is used to its limits? Sure.For 24-bit ADC, datasheet will usually tell you to route digital signals away from the analog inputs, and recommend various filter components.

author: uer166
author_rank: Super Contributor
timestamp: April 24, 2025, 11:52:31 pm
content: Quote from: thm_w on April 24, 2025, 11:19:37 pmA lot of them will also recommend splitting the ground plane into "analog" and "digital", and connect them underneath the ADC. (*ahem* Microchip).Feel free to completely ignore this nonsense and use actual proven techniques to reduce crosstalk (physical separation, defined return paths, solid low impedance ground plane without slots, PSRR accountability, etc).

author: Bud
author_rank: Super Contributor
timestamp: April 25, 2025, 01:30:46 am
content: I had a 24-bit ADC design and found no detectible difference by adding series resistors to the control lines.

author: David Hess
author_rank: Super Contributor
timestamp: April 25, 2025, 06:03:40 am
content: High resolution sampling ADCs are much more sensitive to noise on their control lines than integrating converters like delta-sigma designs.Quote from: uer166 on April 24, 2025, 11:52:31 pmThere are good reasons for that recommendation. If you have not experienced it, then you were not working with enough resolution, or there were other noise sources obscuring what was going on. Common mode currents through a ground plane can produce errors of an order of magnitude greater than the LSBs of a high resolution converter.The recommendation to separate analog and digital planes and connect them below the converter works, and datasheet specifications usually rely on it, but what do you do if you have more than one converter? The application notes never discuss this compromise.Better may be to use a common mode suppression like an instrumentation amplifier to drive the ADC, or currents instead of voltages, however this can also compromise performance. Some converters have differential inputs which will help considerably in a single ground plane design, up to the limits of common mode rejection anyway.

author: peter-h
author_rank: Super Contributor
timestamp: April 25, 2025, 06:16:55 am
content: QuoteThey end up within < 1mm of each other when they reach the chip

author: David Hess
author_rank: Super Contributor
timestamp: April 25, 2025, 10:33:09 am
content: Quote from: peter-h on April 25, 2025, 06:16:55 amSometimes you just have to do the best that you can. In one design I routed sensitive analog signals on one side of the board and other signals on the other. In another, I had short lengths of shielded cable to jump across the board. And in another, I moved the converter to a corner for easy access.

author: peter-h
author_rank: Super Contributor
timestamp: April 25, 2025, 12:28:00 pm
content: It seems to me that gating the digital signals is pretty easy (happens anyway if you use a dedicated SPI) and will eliminate noise sources during the conversion.One needs to park the clock in the right place when it is gated-off. Usually at 0 but some SPI modes use 1.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 25, 2025, 12:56:29 pm
content: Yeah, do NOT split ground planes, but route digital signals on one side of the converter and analog on the other side, usually packages for "precision" converters are designed this way. Do not cross digital and analog traces if you can avoid it.After that, series resistors for SPI lines is a plus.Gating clock & data would be a last resort plan IMO.Keep in mind that the analog conditioning will usually be the hard design part for getting >= 16 real bits out of an ADC.

author: David Hess
author_rank: Super Contributor
timestamp: April 25, 2025, 03:21:55 pm
content: Quote from: peter-h on April 25, 2025, 12:28:00 pmA 74HC75 dual 2-bit transparent latch will do everything required.Quote from: SiliconWizard on April 25, 2025, 12:56:29 pmI have had mixed results with series termination. It lowers the high frequency response, but the total injected charge remains the same. I would use gating as my first plan.QuoteThe analog signal conditioning at high resolution is tough, and proper verification makes it tougher.

author: peter-h
author_rank: Super Contributor
timestamp: April 25, 2025, 05:49:16 pm
content: How would you wire the 74HC75? What is wanted is to force DATA and CLK to 0 when /CS=1.

author: David Hess
author_rank: Super Contributor
timestamp: April 25, 2025, 06:02:57 pm
content: Quote from: peter-h on April 25, 2025, 05:49:16 pmThe transparent latch will hold the last state on its output when disabled, so wait for the SPI transaction to complete, and then disable the transparent latch with CS. I looked but did not find a transparent latch with an active low enable, which seems odd.If you want to force DATA and CLK to 0 when -CS is 1, then invert -CS and use a pair of AND gates.

author: thm_w
author_rank: Super Contributor
timestamp: April 25, 2025, 09:26:12 pm
content: Quote from: peter-h on April 25, 2025, 06:16:55 amCoupled length is what matters:https://resources.altium.com/p/crosstalk-or-couplingUnless you are talking ultra high impedance signals affected by leakage, which is unlikely.

author: Siwastaja
author_rank: Super Contributor
timestamp: April 26, 2025, 06:01:05 am
content: Quote from: uer166 on April 24, 2025, 11:52:31 pmThis is a valid concept and is used for single-ended, high accuracy DC/low frequency signals. Of course, when done carelessly, it risks adding problems athighfrequencies.It became a problem when misguided application note writers started to present this strategy, EMC-neutral at best and EMC disaster at worst, as some sort of EMC improvement tactic.

author: peter-h
author_rank: Super Contributor
timestamp: April 26, 2025, 06:16:30 am
content: I would think using a differential input ADC, like the MCP3550, is the way to go for any precision.That chip works down to GND minus 0.2V or so, too.You still have the problem of radiation from the SPI. On this chip that can be up to 5MHz, but arguably one should run it much slower, given the ~80ms conversion time. OTOH- the SPI activity is outside the conversion period (so is there any point in running it slower?)- if the SPI is used for other stuff, that activity (up to 10MHz on mine) can beinsidethe conversion period, unless the SPI is gatedAlso, on aDAC, the SPI is obviously going to be active when the output is active

author: Doctorandus_P
author_rank: Super Contributor
timestamp: April 26, 2025, 12:55:34 pm
content: It's common to have programmable slewrate control on modern microcontrollers. Adding logic to gate the SPI signals undoes that. If you want to be really cautious, you can add analog switches in your SPI signals, or use separate SPI buses.Signal integrity and noise is also hugely impacted by the quality of the PCB design. In one of my old projects, a one-off soldered on matrix board, the uC both did some ADC conversions, and multiplexing of a keyboard matrix. Scanning the keyboard matrix generated a huge amount of noise all over the PCB. That was a good learning moment for me.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 26, 2025, 01:14:32 pm
content: Quote from: Siwastaja on April 26, 2025, 06:01:05 amYes, it only "works" for very low-frequency signals, so applying that concept to anything containing "digital" signals (so high-frequency components due to the sharp edges, regardless of the actual switching frequency) is detrimental in 99.9% of the cases.I'll put a link to this video which was posted recently:What do you call an engineer who splits a ground plane?- A customer!

author: David Hess
author_rank: Super Contributor
timestamp: April 26, 2025, 03:33:56 pm
content: Quote from: peter-h on April 26, 2025, 06:16:30 amI suspect precision is actually worse with a differential input, but the differential input makes up for it by rejecting common mode noise.

author: Siwastaja
author_rank: Super Contributor
timestamp: April 26, 2025, 03:36:22 pm
content: Quote from: SiliconWizard on April 26, 2025, 01:14:32 pmWell, if you have an analog single-ended signal and need to digitize it to, say, 24-bit resolution and 20-bit accuracy, then surely you do need to use splits (or star grounding, or other techniques known detrimental to EMI), even when you have digital signals on the same PCB (and you are going to if it's an ADC). It is then up to you to analyze how much EMC suffers and if it passes, but you have no options if you want to avoid currents in the ground plane causing microvolts of shift, ruining accuracy of analog.This is the true use case of split ground planes and it's funny to see how it has been forgotten. We don't need to overreact to poor use of split planes either. They have true use cases.Maybe if 0.1% of your designs concern precision analog, then your comment about 99.9% is true. But such percentage is useless. You have to use whatever relevant techniques to make every design work to requirements, you can't just use something which works 99.9% of time.

author: David Hess
author_rank: Super Contributor
timestamp: April 26, 2025, 04:31:17 pm
content: Quote from: Siwastaja on April 26, 2025, 03:36:22 pmI do not understand the problem here. When the star grounding is properly used, all signals are located over their respective ground planes. There should be no signals that cross them producing EMI problems. In the case of an ADC or other mixed signal device, the star ground is at the ADC, where the analog and digital signals terminate.

author: peter-h
author_rank: Super Contributor
timestamp: April 26, 2025, 05:36:26 pm
content: QuoteWe had various threads on this. This setting is more a programmable Rds of the MOSFETs; not a slew rate control as such. Of course increasing the Rds impacts the slew rate into a given load capacitance...QuoteWhy would it be?ISTM that delta sigma switched-capacitor ADCs are naturally differential input. Others might not be.

author: David Hess
author_rank: Super Contributor
timestamp: April 26, 2025, 08:18:11 pm
content: Quote from: peter-h on April 26, 2025, 05:36:26 pmThe errors from each side still add together, especially with noise.It would be interesting to know whether matching the source impedances causes cancellation of the correlated errors between the inputs.Early designs tended to not have differential inputs, but I wonder if there was greater demand later for differential inputs to remove ground referred errors in single ground plane designs. That is a big advantage of using a differential input, but previous designs using single ended inputs did work if the design was good.To give a concrete example, each input has Johnson noise from the series resistance of its input switch. Doubling the number of inputs to a differential configuration places these Johnson noise sources in series, increasing noise by 1.414 times.For almost anybody using these ADCs it will not matter, because their design is not going to achieve the datasheet specifications for noise and precision anyway.

author: uer166
author_rank: Super Contributor
timestamp: April 26, 2025, 09:22:59 pm
content: Quote from: Siwastaja on April 26, 2025, 03:36:22 pmI'd agree with this if you have really high currents and SE ADC referenced to GND as you mentioned.The thing is, at really high resolution I've only personally used fully differential ADCs from microchip (24 bits) that recommended that GND split.It does absolutely nothing to improve performance or offsets since the inputs won't be affected by a few common mode microvolts anyway (CMRR would easily reduce the error to below 1LSB). The use case where it does make sense is so rare that the whole concept should be discouraged unless you really know what you're doing and what the trade-offs are.