hybridfree/eevblog-posts huggingface dataset:
Schematic for old QMTECH Zynq XC7Z010 Starter Kit - Page 1
Forum section: electronics / general

author: Jope
author_rank: Regular Contributor
timestamp: July 29, 2022, 08:53:56 am
content: Hi,I'm looking for the schematic of the old version of the QMTECH Zynq XC7Z010 Starter Kit.I've bought this board some time ago, and it has been collecting dust ever since. It seems back then I did only download the user manual and forgot to download the schematic.I've just found out that the github page of QTMECH only has the files for a new version of this starter kit:https://github.com/ChinaQMTECH/ZYJZGW_ZYNQ_STARTER_KITThe old site was this:https://github.com/ChinaQMTECH/ZYNQ_STARTER_KITDoes anybody here have the schematic for the old version of this board?

author: Wiljan
author_rank: Regular Contributor
timestamp: July 29, 2022, 03:35:39 pm
content: Tryhttps://web.archive.org/web/20200907002444/https://github.com/ChinaQMTECH/ZYNQ_STARTER_KIT/

author: Jope
author_rank: Regular Contributor
timestamp: July 29, 2022, 04:33:09 pm
content: Quote from: Wiljan on July 29, 2022, 03:35:39 pmThanks, but I've already tried that.If you actually click on the folder links, there is nothing there; Web Archive only archived the main url.

author: agehall
author_rank: Frequent Contributor
timestamp: July 30, 2022, 06:31:21 am
content: Check ifhttps://github.com/pranukeviciusm/ZYNQ_STARTER_KITcontains what you need. Looks like it might be a fork of the original repo.

author: Jope
author_rank: Regular Contributor
timestamp: July 30, 2022, 11:17:57 am
content: Quote from: agehall on July 30, 2022, 06:31:21 amThank you so much! This is the repo I was looking for. This contains the manual I already have (it's the exact same one) plus all the other files.

author: agehall
author_rank: Frequent Contributor
timestamp: July 30, 2022, 05:00:48 pm
content: Glad to hear it!If you have a link to a github repo that has been removed, just search GitHub for the repo name - chances are that if it ever contained anything useful, someone will have made a fork that is still there.
How to download ispVM System software version 17.7 (or later)? - Page 1
Forum section: electronics / general

author: thenndral
author_rank: Newbie
timestamp: July 12, 2022, 07:54:19 am
content: Dear All,I'm new to this forum.I'm looking for ispVM System software version 17.7 (or later), May I know where can I download it.OS : Windows 7Thanks in advance,Thenndral.

author: mon2
author_rank: Frequent Contributor
timestamp: July 12, 2022, 03:26:29 pm
content: Have you tried to install the latest Lattice tools ? Believe that this is a part of their toolchain. You can also ask their technical support for the confirmation.

author: thenndral
author_rank: Newbie
timestamp: July 13, 2022, 01:57:24 am
content: Thanks for your reply.Actually, I found the below link on google and search for the software. but I can't find it.https://www.latticesemi.com/en/Support/AnswerDatabase/3/0/4/3045https://www.latticesemi.com/Support/SoftwareArchive.aspx//You can also ask their technical support for the confirmation.//Thanks for your suggestion. I will check with their technical team.Thanks again,Thenndral.
Reading a file in Verilog - Page 1
Forum section: electronics / general

author: blackblade
author_rank: Newbie
timestamp: July 10, 2022, 12:04:23 pm
content: Hello. I want to read a file in Verilog that contains both positive and negative numbers. For example, the file contents are:-42028-52 and so on.Also, after reading I have to multiply these numbers with a signal. I'm confused how to read these numbers.One approach is to use $readmemb() directive but it requires numbers in binary format. That can be done easily but what about the negative numbers, in which format does Verilog accept negative numbers?Thanks

author: Foxxz
author_rank: Regular Contributor
timestamp: July 10, 2022, 04:25:45 pm
content: Since the file will be in binary you just format the numbers in binary how you expect to process them with your FPGA. Your code determines how the FPGA processes this binary information. Typically, the MSB signifies the sign of a binary number.

author: BrianHG
author_rank: Super Contributor
timestamp: July 10, 2022, 07:24:51 pm
content: Could the op be talking about :Code:string source_file_name = "data_file.txt" ; // or "spread_sheet.csv"integer fin_pointer, status;reg signed [31:0] signed_data;fin_pointer= $fopen(source_file_name, "r");status = $fscanf(fin_pointer,"%d",signed_data);I use something like this a lot in my test benches to read a ascii table of data into register arrays, even going as far as being compatible with tabulated .csv database files.I make extensive use of $fopen, reading and writing data from ascii files as well as binary data here:https://github.com/BrianHGinc/SystemVerilog-TestBench-BPM-picture-generator/blob/main/ellipse_generator_tb.sv

author: BrianHG
author_rank: Super Contributor
timestamp: July 10, 2022, 08:01:00 pm
content: Other solutions are arrays having a signed table of numbers in a source verilog file:Code:input clk;input [1:0] address;output reg signed [7:0] read_data;wire/reg/integer/parameter int/bit signed [7:0] data_table [0:3] = '{-2,5,9,-12};always @(posedge clk) beginread_data <= data_table;end
Tang Nano 1K/4K/9K  connecting LVDS LCD? - Page 1
Forum section: electronics / general

author: up8051
author_rank: Frequent Contributor
timestamp: June 27, 2022, 09:21:16 pm
content: Hi,I am trying to connect a laptop display to one of these modules TangNano /4k/9k.LCD:- 1366X768- color 3x6bit- clock 76.8MHz/268,750 MHz (readed from EDID EEPROM)The code is based on "GOWIN LVDS71 LCD reference design".The first attempt of Tang Nano:Because GW1NR-1LV does not have true LVDS ports and none of the banks on this module is powered by 2.5V, I decided to use external transmitters DS90LV047ATM.Unfortunately, only half of the success: color bar and net grid are displayed correctly but gray scale (color change every pixel) is no longer displayed, the entire image is distorted.This could be because the transmitter is too slow ( DS90LV047ATM - Max switching frequency Min:200MHZ Typical:250Mhz)The second attemnpt TangNano 4kWe have a Bank-2 powered by 2.5V and true LVDS output but this time nothing is displayed correctly.Of course I remaped outputs and configre PLL respectively for GW1NSR-4C.I think the problem is that the lines are used for HDMI interface (the lines are loaded by serial capacitors C2-C9 and pull-down resistor R1-R8).Unfortunately, these elements are so small that when I desolder them, I will not mount them again and I only have one 4k module.Tang Nano 9k again no 2.5V I/O Bank.Any idea how to connect LVDS LCD to Tang Nano or some other FPGA modules with such a possibility?BR JarekC

author: mon2
author_rank: Frequent Contributor
timestamp: June 29, 2022, 10:00:27 pm
content: I would study the Gowin video kit (believe it is the proper one) which features an external FPC cable going to a local LCD. That kit documentation and IP should be a good start for such a project.
Using SPICE for signal integrity simulation - Page 1
Forum section: electronics / general

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: June 21, 2022, 11:51:12 pm
content: Signal integrity simulation programs like HyperLynx, ANSI Wave SI, Sigrity e.t.c are robust but very expensive. Ultimately they carry out simulation of a system containing transmission line models connected to models of IO buffers. The IO buffer models could be IBIS or SPICE models.I am wondering, why spend so much money on such expensive programs? Can't we just create the entire scenario we want to simulate in free SPICE program like LT SPICE and just run the simulation in that instead?

author: asmi
author_rank: Super Contributor
timestamp: June 22, 2022, 02:17:58 am
content: No vendor is going to release a SPICE model of their IO structures because they reveal their internal structure. So IBIS/HSPICE model is the best you ever going to get.As far as simulation goes, some simulation tools is included into relatively (compared to tools you've mentioned) affordable eCADs like Cadence Orcad Professional or even Standard editions (though the latter is pretty limited because it can't run post-route PCB sims, only pre-route "model" ones). Altium Designer presumably also contains SI simulation tool, but I'm yet to figure out how to use them, and so I use my old license of Orcad Pro whenever I need to run board-level sims.

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: June 23, 2022, 09:03:15 am
content: About Altium I have been told that the jack of all trades is master of none, so Altium designer may have a lot of simulation capability but it is not reliable. This is heresay though.

author: tggzzz
author_rank: Super Contributor
timestamp: June 23, 2022, 09:23:30 am
content: Have a look at Micro-Cap, which is now free as in beer.I believe it can import IBIS models, but I haven't tried it

author: KaneTW
author_rank: Frequent Contributor
timestamp: June 23, 2022, 10:22:50 am
content: Same, haven't figured out how to use Altium's SI analysis yet. Evaluating HyperLynx rn and it's night and day.

author: Bassman59
author_rank: Super Contributor
timestamp: June 23, 2022, 06:14:14 pm
content: Quote from: KaneTW on June 23, 2022, 10:22:50 amWhich is better? Saying "it's night and day" doesn't make that clear.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 23, 2022, 06:23:57 pm
content: Quote from: tggzzz on June 23, 2022, 09:23:30 amYup, IBIS is supported. I haven't tried it yet either, but look at the documentation, it seems fully documented.I do like Micro-Cap quite a bit. Too bad it's become abandonware (but good thing they released it for free.)

author: KaneTW
author_rank: Frequent Contributor
timestamp: June 24, 2022, 01:04:09 am
content: Quote from: Bassman59 on June 23, 2022, 06:14:14 pmSorry. Hyperlynx is way better and easier to use/configure.
I need a small fpga with 2-4MB of RAM and nothing else - Page 1
Forum section: electronics / general

author: DiTBho
author_rank: Super Contributor
timestamp: June 27, 2022, 01:54:43 pm
content: hiI need a small board with an FPGA (I prefer Xilinx) with just SDRAM or something simpler than DRAM.I don't want to use a IP-core to manage the ram, and I need to address up to 2 or 4Mbyte.I don't need other gadgets on the board, I don't want e.g. 7segments LCDs, buttons, .. etc. Just soldered ram and a header with pins!Is there anything that I can buy? I don't have the skill and the equipment to design and make one myself

author: Foxxz
author_rank: Regular Contributor
timestamp: June 27, 2022, 03:49:47 pm
content: This is a rebranded MOJO boardhttps://www.amazon.com/dp/B07P39F1V6/Here is a chunk of SDRAMhttps://www.amazon.com/Mister-Manual-Welding-Computer-Accessories/dp/B08RN5YCGG/Heres the board info for the SDRAMhttps://boogermann.github.io/Bible_MiSTer/hardware/assembly/sdram-board-assembly/

author: langwadt
author_rank: Super Contributor
timestamp: June 27, 2022, 03:58:22 pm
content: https://www.ebay.com/itm/124439000584

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 27, 2022, 05:49:01 pm
content: I can also mention boards that I talked about a while ago, with Lattice ECP5 FPGAs (they are actually FPGA boards made for light controllers, that some company made dev base boards for). Relatively cheap and work well. They have 8 MBytes SDRAM (32-bit data bus, which is not bad). They also embed 2 Ethernet PHYs (but not the connectors, but normally all you'll need is MAGJACKs if you wanna implement Ethernet), just one user LED and many IOs. I have two of them, one with a ECP5-25 and one with a ECP5-45.https://www.aliexpress.com/item/1005001686186007.html

author: Canis Dirus Leidy
author_rank: Regular Contributor
timestamp: June 28, 2022, 07:06:27 am
content: Chinese board with Spartan-6 (XC6SLX16) and MT48LC16M16A2 SDRAM chip:https://aliexpress.com/item/32801899786.html

author: jevinskie
author_rank: Newbie
timestamp: June 28, 2022, 04:27:25 pm
content: Not Xilinx but the Gowin parts can come with built in PSRAM or SDRAM. The Sipeed Tang Nano 4k/9k are under $20 and have 8 Mbyte of PSRAM on chip.
Xilinx IP Core with native data in and AXI bus data out - Page 1
Forum section: electronics / general

author: FlyingDutch
author_rank: Regular Contributor
timestamp: June 13, 2022, 05:18:57 pm
content: Hello Forum,I have written a design wich produce periodically some data. Data has parallel form 28-bit of data. There also is "strobe" signal (active High) which means that data should be transferred. I am searching for Xilinx Vivado IP Core which on one side has just "native" parallel data and on the second side has AXI bus. Ultimately I would like to send this parallel data in burst by 8 packages. i mean I have stored 28-bit X 8 array and when strobe goes high then I want to send this array by AXI bus in burst mode of length 8. AXI data will has width of 32-bit. What Xilinx IP Core best fits with described behavior?Thanks in advance and Regards

author: asmi
author_rank: Super Contributor
timestamp: June 13, 2022, 06:27:48 pm
content: That sounds like a job for AXI DMA - you program it with destination address of receiving buffer, push data into the AXI Stream port (which is as close as it gets to parallel interface, the only additional signals are two handshake signals - ready/valid, and a "last" signal which indicates an end of the data packet), and then your CPU waits for DMA interrupt signalling completion of transter. Take a look at PG021 to see how it works and how to use it.
Custom SDR + optical fiber - Page 1
Forum section: electronics / general

author: e.sotillet
author_rank: Contributor
timestamp: June 01, 2022, 01:29:58 pm
content: Hi folksI am looking for a designer or company to design a telecommunications device that basically includes an SDR (FPGA + DAC /ADC) and a fiber optic connection.Let me know if someone has recommedations.Best regards

author: Scrts
author_rank: Frequent Contributor
timestamp: June 01, 2022, 04:27:15 pm
content: Optics you mean like SFP connection?Example:http://www.hitechglobal.com/Boards/16ADC-DAC_Zynq_RFSOC.htm

author: jevinskie
author_rank: Newbie
timestamp: June 02, 2022, 01:33:48 am
content: These folks have experience with SDR and are wonderful in the open source community.http://www.enjoy-digital.fr/

author: e.sotillet
author_rank: Contributor
timestamp: June 02, 2022, 01:28:02 pm
content: Quote from: Scrts on June 01, 2022, 04:27:15 pmYes, I mean SFP connection. We need to design a custom board.Quote from: jevinskie on June 02, 2022, 01:33:48 amThanks, I will contact them.Best regards

author: glenenglish
author_rank: Frequent Contributor
timestamp: June 09, 2022, 11:25:02 pm
content: HiWe make just the device....We use a Xilinx Ultrascale platform and ADI converters, with SFPs directly from the transceivers. We build in house.-glen(Xilinx Alliance Partner)

author: e.sotillet
author_rank: Contributor
timestamp: June 13, 2022, 12:11:51 pm
content: Quote from: glenenglish on June 09, 2022, 11:25:02 pmHi GlenExcellent, how I can contact you?Best regards
Stupid question - what does axis mean? - Page 1
Forum section: electronics / general

author: agehall
author_rank: Frequent Contributor
timestamp: June 12, 2022, 08:16:20 pm
content: When looking at Verilog code, I often see _axis_ as part of the signal names. I’m not able to figure out what this means but it seems common enough that I guess it is some sort of convention for something.Anyone able to enlighten me?

author: BrianHG
author_rank: Super Contributor
timestamp: June 12, 2022, 08:49:45 pm
content: Please give us 2 unrelated examples from different projects from different authors.

author: ejeffrey
author_rank: Super Contributor
timestamp: June 12, 2022, 08:53:44 pm
content: With no context I would guess AXI stream.

author: asmi
author_rank: Super Contributor
timestamp: June 12, 2022, 08:59:55 pm
content: I hazard a guess that it stands for AXI Slave.

author: agehall
author_rank: Frequent Contributor
timestamp: June 12, 2022, 09:58:48 pm
content: I’ve mostly been looking at digilent example code the past few days. Take a look at the code here for example:https://github.com/Digilent/Pmod-I2S2/tree/master/shared/src/hdl. There are plenty of other examples like this that follow similar naming schemes in their repositories.I don’t believe this is an AXI design, but maybe it is and I just don’t get it… I would expect to see a lot more signals if this was AXI though.

author: hamster_nz
author_rank: Super Contributor
timestamp: June 12, 2022, 10:12:22 pm
content: Comment from first file I clicked into inside that repo:Code:// Create Date: 03/23/2018 01:23:15 PM// Module Name: axis_i2s2// Description: AXI-Stream I2S controller intended for use with Pmod I2S2.Looks like it is an AXI Stream.These youngens, trained to never read the comments

author: agehall
author_rank: Frequent Contributor
timestamp: June 13, 2022, 05:58:03 am
content: Ok, I’ll put on my stupid hat and go back to being an idiot.I guess reading the comments would have been much easier than trying to google the answer. Thanks for pointing out what should have been obvious long before I posted the question.

author: radiolistener
author_rank: Super Contributor
timestamp: June 13, 2022, 06:24:43 am
content: It looks like some kind of AXI-stream:https://docs.xilinx.com/v/u/en-US/ug761_axi_reference_guide
Vivado / Vitis 2022.1 on Ubuntu 22.04 LTS? - Page 1
Forum section: electronics / general

author: evb149
author_rank: Regular Contributor
timestamp: May 21, 2022, 11:24:09 pm
content: Does anyone have reports as to the success / problems of runningVivado / Vitis 2022.1 on Ubuntu 22.04 LTS?I ask because Ubuntu 20.04.1 LTS is the most recent OS listed in the Vivado ML 2022.1 OS compatibility list, so the newer LTS is officially unsupported, and may continue be so for a long while?

author: RoGeorge
author_rank: Super Contributor
timestamp: May 22, 2022, 07:20:32 am
content: Never had problems with Vivado/Linux in the past. I didn't try this combination you ask, but AFAIK Vivado is developed on Linux, then ported to Windows, too. Also, latest Ubuntu LTS is now 22.04 LTS (we are in May already).My bet is it will work as well on Ubuntu 22.04 LTS.

author: mac.6
author_rank: Regular Contributor
timestamp: June 20, 2022, 06:59:06 am
content: The only problem I ran when using vivado on unsupported linux distro was the cable driver install.I mostly resolved the problem by using virtual download cable using esp32 instead of hacking the badly written install scripts...

author: evb149
author_rank: Regular Contributor
timestamp: June 20, 2022, 07:17:53 am
content: Thanks for the encouragement / notes.I did have some cable driver install issues some while back trying to get it running on Centos 6/7/whatever it was.I'll give it a try when I can get the system set up appropriately.
GOWIN FPGA. Packages removed from documentation. Why? - Page 1
Forum section: electronics / general

author: atom1477
author_rank: Newbie
timestamp: April 16, 2022, 07:41:55 pm
content: Hello.Here it is the shot from UG103-2.6E:They removed pinouts for some devices.But on GOWIN website I don't see any information about it.GW1N-1 are not marked as obsolete or something.Does anyone know what's going on here?PS. Do not pay attention to the typo on the picture (GWN-1 instead of GW1N). This is not the issue.

author: Bassman59
author_rank: Super Contributor
timestamp: April 18, 2022, 02:57:44 pm
content: They don't want to sell those devices in those packages any more.

author: mc68000
author_rank: Contributor
timestamp: May 23, 2022, 04:09:22 pm
content: The same packages have been added to GW1NR-1. You can check their Website in the same page.
verilog conditional compilation with several flags in condition - Page 1
Forum section: electronics / general

author: radiolistener
author_rank: Super Contributor
timestamp: May 30, 2022, 08:51:57 am
content: I want to use several flags in condition for conditional compilation directive, something like this:Code:`ifdef FLAG1 or FLAG2// stuff1`else// stuff2`endifbut it seems that `ifdef doesn't support several flags and I don't want to duplicate code for several directives. So, what is the best way to write such condition in verilog?

author: Someone
author_rank: Super Contributor
timestamp: May 30, 2022, 10:32:01 am
content: its a define, one of the few situations where Veirlog has some form of typing:https://verificationacademy.com/forums/systemverilog/oring-ifdef
Implementing Verilog designs in real hardware - Page 1
Forum section: electronics / general

author: agehall
author_rank: Frequent Contributor
timestamp: May 22, 2022, 12:22:34 pm
content: So I consider myself a newbie when it comes to HDL but I get by. I’ve done a few small designs that I’ve implemented in CPLDs before but only fairly basic stuff and most HDL things I’ve done so far have only been simulated.I’m now trying to step up my game a little and I’m glancing at all the different things that Xilinx provides, like IOBUFs and other things. Do I need to care about them or is Vivado typically smart enough to do-the-right-thing(tm) if I just hook up my design to external pins? And if I should manually add these things and other elements available instead of letting the tools infer them, is there a good place to start reading about how to use these?I know these questions are kind of vague but I need some guidance. I’m at the point where I think I need to ask some questions but not 100% sure what the questions should be. Any pointers are appreciated.

author: mblinov
author_rank: Contributor
timestamp: May 22, 2022, 01:21:31 pm
content: Specifically for I/O pins, Vivado should figure it out just fine.Vivado can infer many (but not all) primitives from the way in which the verilog is written - Xilinx document some of this under chapter 4, called "HDL Coding Techniques" of the manual here:https://docs.xilinx.com/v/u/en-US/ug901-vivado-synthesisHowever sometimes you really want to instantiate a concrete primitive in order to have full control over its presence and name - I used to do this with BRAM blocks, because I wanted to have consistent RAM layout and naming in order to then initialize those blocks with data using TCL in post-layout, without having to re-do the synth/PnR step. For this, Xilinx provide a guide here:https://docs.xilinx.com/r/en-US/ug953-vivado-7series-librariesYou probably want to look under the chapter "Design Elements"

author: asmi
author_rank: Super Contributor
timestamp: May 22, 2022, 01:26:02 pm
content: It will infer basic IO buffers on it's own (stuff like IBUF/OBUF/IOBUF), but if you want to use advanced IO features (like DDR, SERDES), you will need to instantiate them manually in your HDL.

author: agehall
author_rank: Frequent Contributor
timestamp: May 22, 2022, 01:31:05 pm
content: Thanks guys! That’s exactly what I needed to hear!I have a project that I’m working on that will be far bigger than anything else I’ve done in HDL so far and I guess I’ll just push on without much concern at the moment and tackle issues as I run into them!
Spartan3e with BPI flash - Page 1
Forum section: electronics / general

author: pepe
author_rank: Newbie
timestamp: May 15, 2022, 08:30:36 pm
content: Hello,i have a board with XC3S250e, with a paralel NOR flash glued on its BPI interface. I am trying to program this memory using Impact in ISE 14.7, created an MCS file from the binary using promgen, with with option -bpi_dc parallel, this was just OK (at least as far as i can tell )But. Tried to add this flash image in Impact after initializing the chain, selected the above MCS file but it only allows me to select SPI PROM as a target device:
What has happened to my Vivado Project? - Page 1
Forum section: electronics / general

author: Mario87
author_rank: Frequent Contributor
timestamp: May 11, 2022, 11:27:09 pm
content: Hi all,I opened Vivado and made some changes to the block design of my project, but when I went to re-synthesize I keep getting the error message below saying one of the IP dcp files doesn't exist, but when you look at the file location it is nonsense.The file does exist, I have found it as part of the out of context synthesis in its own folder, but for some reason Vivado keeps looking for it in the location below. Anyone know how I can correct this and point vivado to the right location??QuoteThe correct file location should be C:/PROJECT/PROJECT.gen/sources_1/bd/video_processing/ip/video_processing_mig_7series_0_0/video_processing_mig_7series_0_0.dcpAny help greatly appreciated as I really don't want to have to re-create the project!

author: Mario87
author_rank: Frequent Contributor
timestamp: May 12, 2022, 09:28:30 pm
content: Anyone any ideas? I have found that if I reset the synth run, make the C:/PROJECT/PROJECT.runs/synth_1/Users/MyName/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-21428-MyName-PC/coregen directory and then copy the video_processing_mig_7series_0_0 directory from the correct location into this new directory then run synthesis, it works totally fine.The issue is that every time I run synthesis it deletes everything in the synth_1 folder and I have to re-create the folder structure.So the project appears to be "fine", just that vivado is pointing in the wrong place for these file locations.Surely there must be some way to fix this / change the location vivado is checking....but how do I do that?

author: Someone
author_rank: Super Contributor
timestamp: May 12, 2022, 10:11:35 pm
content: Vivado projects are brittle, the UI hides what is going on. Its pretty common to have projects fall apart like this where the underlying tools spit out errors but there is no obvious way in the GUI to influence what they are complaining about. Most errors with block diagrams are fixed by resetting the design, manually deleting all the cached/intermediate build products, and regenerating them all from scratch. Move to a non-project flow to save time.

author: Mario87
author_rank: Frequent Contributor
timestamp: May 14, 2022, 09:31:58 am
content: Just for info, I managed to work around this by deleting the MIG7 IP block and creating a new one that has "_1" at the end instead of "_0". Project now synthesis' without that silly error.
Idea to use SPLD chips(PEEL18CV8ZP) - Page 1
Forum section: electronics / general

author: up8051
author_rank: Frequent Contributor
timestamp: January 12, 2022, 03:01:57 pm
content: Hi,I have in my stock about 500 pieces of PEEL18CV8ZP left after the finished production.Nobody wants to buy them back so I'm looking for an idea what to use them for.I have software for them and compatibile programmer.PEEL18CV8ZP it is ultra low power version of GAL16V8 with enhanced architecture.Any ideas?

author: Benta
author_rank: Super Contributor
timestamp: January 12, 2022, 11:10:06 pm
content: I might have an idea.Which package and speed grade?Why can't I send a PM?Cheers.

author: up8051
author_rank: Frequent Contributor
timestamp: January 12, 2022, 11:21:09 pm
content: Quote from: Benta on January 12, 2022, 11:10:06 pmpackage: DIP20Speed Grade: 25

author: up8051
author_rank: Frequent Contributor
timestamp: January 14, 2022, 10:33:27 am
content: Quote from: Benta on January 12, 2022, 11:10:06 pmI don't know why.You can write to e-mail: jarekc(dot)diy(at)mail(dot)com

author: DeepLink
author_rank: Regular Contributor
timestamp: May 10, 2022, 06:29:26 am
content: up8051 - which software are you using? And which programmer?I do have some PEEL18CV8 and 22CV10And an old copy of ICTPLACE for DOSBut can't find a suitable programmer/Hans

author: up8051
author_rank: Frequent Contributor
timestamp: May 10, 2022, 03:13:57 pm
content: Soft: ICT PLACE 3.0.0 (DOS) / WinPlace 2.1Programmer: Labtool-48
STA timing closure for asynchronous FIFO - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: May 03, 2022, 07:16:48 am
content: I have implemented anasynchronous FIFOHowever, I have setup timing violation whenread_clkis having phase shift of 270 degrees , andwrite_clkis having phase shift of 90 degrees.Bothread_clkandwrite_clkare having the same clock frequency.Could anyone advise ?

author: hamster_nz
author_rank: Super Contributor
timestamp: May 03, 2022, 07:42:00 am
content: It you are using Vivado, I suggest using the XPM clock crossing macros where possible. They have embedded constraints so you don't have to fiddle with constraints or attributes yourself.Makes life so much easier.I know that you most likely have your own clock domain crossing solution, but there are quite a few gotchas lurking - like the correct use of the 'async_reg' attributes...

author: ejeffrey
author_rank: Super Contributor
timestamp: May 04, 2022, 06:26:29 am
content: Definitely use the vendor macro if available. They will provide the most efficient implementation for the specific platform.I'm not sure how other tools work exactly, but in Quartus for instance, synchronizer chains for CDC between unrelated clock domains are automatically detected and protected from optimization, and they automatically creates a false path constraint for timing analysis. However, if the launch and latch clocks are the same or have a fixed phase relationship it will just treat it as standard logic. The synthesizer has no way to recognize this as a correct async FIFO implementation that never reads and writes the same location at the same time, so it has to check timing as if you could. The solution is to either add the proper timing directives or to use the platform macros and it is definitely better to use the macros when possible.
Help, how to program TMS32F2812GHHA - Page 1
Forum section: electronics / general

author: daisizhou
author_rank: Super Contributor
timestamp: April 30, 2022, 10:57:25 am
content: The chip model is TMS32F2812GHHA.Found a 5V short circuit, the chip has been damaged.I would like to know, how to re-read the program and re-write the program.I found a similar JTAG interface on the board, I can't be sure.I hope to use a cheap programmer or something like that, if you know please let me know, thanks

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 30, 2022, 01:11:58 pm
content: You are posting in the wrong section. This is a DSP (digital signal processing) chip not a FPGA (field programmable gate array).If the chip is damaged changes are you are not going to be able to read the on chip FLASH memory. It is also possible that the FLASH is read protected.To get to know more about the chip look at the datasheet here:https://www.ti.com/lit/ds/symlink/tms320f2812.pdf?ts=1651324013398&ref_url=https%253A%252F%252Fwww.google.com%252F
LDPC soft decoding - a breadcrumb trail for others. - Page 1
Forum section: electronics / general

author: hamster_nz
author_rank: Super Contributor
timestamp: April 25, 2022, 09:50:05 pm
content: I'm looking at implemented LPDCs in an FPGA. Here's what Wikipedia has to say about LDPC:QuoteThey are becoming pretty ubiquitous - DVB, Satellite Comms, WiFi and so on.I found the math behind LDPC decoding pretty hard to get to grips with. Log likelihoods, and working with the products and sums of hyperbolic tangents was all beyond my understanding when I started. The area is very rich in research, and authors always assume that you understand the basics. So finding an understandable way to get a foot in the door is hard. The best introduction to LDPC codes I've found is this paper, as it has a fully worked example you can follow along with.https://www.researchgate.net/publication/228977165_Introducing_Low-Density_Parity-Check_CodesTo make sure that my understanding of the math is correct, I made a small bit of code that mirrors the fully worked example Sum Product decoder, and lets you play with the numbers interactively:https://github.com/hamsternz/LDPC_demoHopefully if others have to make the same journey as me it will help them clarify what exactly is going on!

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 25, 2022, 10:15:24 pm
content: Interesting. I'm working on line codes and data recovery, so I'll keep an eye on this.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 25, 2022, 10:22:34 pm
content: Quote from: SiliconWizard on April 25, 2022, 10:15:24 pmThat project most probably won't change much apart form code tidy-ups. That little project above won't be gong far - my next steps are code generators so on so I can do BER vs S/N simulations, and the block lengths are too big to display on a screen unless I start mapping bits to pixels.Actually, that would be quite interesting to see...
Hacking surplus Pano Logic thin clients - Page 1
Forum section: electronics / general

author: skip
author_rank: Contributor
timestamp: April 23, 2022, 08:19:58 pm
content: Pano Logic was a Bay Area startup that manufactured tiny FPGA based thin clients with a Ethernet interface, a few USB ports, audio, and one or two video ports. Ever since Pano when out of business in 2012 TONS of both new and used Pano Logic devices have appeared ebay for very little. They are still readily available today.The technology is a bit dated, but it still very capable. One version is based on the largest Spartan6 device Xilinx ever made and includes 128MB DDR2 Ram, gigabit Ethernet, four USB2 ports, and supports dual monitors. That version typical goes for less that $25.I've been playing with Panos on and off for a couple of years now and I have been having a blast.Anyone who is interested in a cheap FPGA platforms might want to checkout the Wikihttps://github.com/tomverbeure/panologic-g2/wiki.Skip
Basic Serializer Verilog - Page 1
Forum section: electronics / general

author: beginner43
author_rank: Newbie
timestamp: April 05, 2022, 11:53:15 am
content: Hello everyone. I'm new to Verilog. I want to convert a parallel data to serial, but without success. What are the bullshit and flaws in my code?----- TOP------------------`timescale 1ns / 1psmodule Serializer(input wire clk,input wire [7:0] in_data,input wire valid_data,output reg out_data);reg [7:0] temp_data;always @(posedge clk)begintemp_data <= in_data;if(valid_data == 1)begintemp_data <= {1'b0, temp_data[7:1]};out_data <= temp_data;endendendmodule-----TESTBENCH-------------`timescale 1ns / 1psmodule tb_serializer();reg tb_clk = 1'b0;reg [7:0] tb_in_data = 8'b01010011;reg tb_valid_data =1'b1;wire tb_out_data ;//Clockalways begintb_clk = ~tb_clk;#5;end//Testbench ConnectionSerializer DUT(.clk(tb_clk),.in_data(tb_in_data),.valid_data(tb_valid_data),.out_data(tb_out_data));//Serializerinitial begin#200;tb_in_data = 8'b11001111;endendmodule

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 05, 2022, 01:28:01 pm
content: Quote from: beginner43 on April 05, 2022, 11:53:15 amI'm no expert, but I think it has to do with the fact that on every clock you load the "in_data" into your "temp_data" undoing the shift.To make it work you have to latch the data into your "temp_data" first and clear a flag to switch to serializing. So load on the first clock and then shift on the next 8 clocks.

author: BrianHG
author_rank: Super Contributor
timestamp: April 05, 2022, 02:42:59 pm
content: Also, in your simulation testbench, you are not driving ' input wire valid_data,'.Your code does nothing without it. Also make sure your stimulus first loads the parallel data into the temp for a clock cycle, then hold the 'valid_data' high for 9 clocks.

author: josuah
author_rank: Regular Contributor
timestamp: April 23, 2022, 12:41:12 pm
content: Quote from: beginner43 on April 05, 2022, 11:53:15 amMaybe this could be simplified a bit by making this anassignstatement?Theout_datawould no more need to be a register, but a mere wire.Having it a register would delay the output by one clock, but maybe this was on purpose.

author: josuah
author_rank: Regular Contributor
timestamp: April 23, 2022, 12:45:19 pm
content: Quote from: beginner43 on April 05, 2022, 11:53:15 amSo on every "incoming request", marked byvalid_dataI supose, you are shifting temp_data (a shift register) by one clock?Do you not want that to happen on every clock instead of just when new data comes in?: It looks like I am saying the same thing as pcprogrammer with different wording.
What is the proper way to invert and tie high/low, signals in the Vivado IP inte - Page 1
Forum section: electronics / general

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: April 22, 2022, 11:34:22 am
content: I have attached a Vivado IP integrator block diagram. I have a few questions about the things in red.1. Is using inverter from Utility Vector Logic IP, the only way to invert input signals into an IP block? I had expected an option to invert input when I right click on an input pin. But Vivado does not appear to have this option.2. Is using the constant IP the only way to generate a permanent logic low or logic high to tie unused inputs low or high? I had expected to have a tie high or tie low option when I right click on an input pin. But Vivado does not appear to have this option.3. Why does Vivado generate a port called gpio_rtl_0 from the AXI_GPIO block and not a port from the actual output port called gpio_io_o[3:0]? Why is the gpio_io_o[3:0] present if it is not going to be used?

author: Someone
author_rank: Super Contributor
timestamp: April 22, 2022, 11:55:41 am
content: Yep, block/schematic input for FPGAs continues to be a mess!1. Some of the IP has options to set the polarity of the reset inside (or they take the parameter of the reset port and auto-magically select the right polarity ? dim memories of such)2.? have always seen constant blocks sprinkled around so there is probably no better alternative3. Wait until it renames some of your busses, just because it felt like it!Vivado block diagrams are a buggy pile of turd, avoid wherever possible.

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: April 22, 2022, 01:20:05 pm
content: Actually in my case, I am dealing with AMBA busses. Therefore, I just need to use the IP integrator at the end of the day.Actually I have used Libero SoC SmartDesign before. In there we can put in an inverter symbol quite easily along with flip flop and other things. They are all found under Primitives section of the IP catalogue. Also, we can tie IP block inputs to low or high, or mark them as unused, quite easily as well by just right click on pin and select the right option. However, I can see that it is not like that here in IP Integrator. This is quite a big surprise for me actually.

author: langwadt
author_rank: Super Contributor
timestamp: April 22, 2022, 02:31:31 pm
content: double click the clock wizard and there is an option to make the reset active high or active lowthe gpio_io_o shows because you have expanded the port (click the - next to GPIO),if it had been an input/output port it would also show io_i, io_t the GPIO port is the port with the IO buffer included
Pixel to byte  - Page 1
Forum section: electronics / general

author: beginner43
author_rank: Newbie
timestamp: April 19, 2022, 12:46:54 pm
content: Hello, has anyone done a pixel to byte converter with fpga before? I don't understand the purpose of this block.

author: Bassman59
author_rank: Super Contributor
timestamp: April 19, 2022, 05:20:42 pm
content: Quote from: beginner43 on April 19, 2022, 12:46:54 pmYou'll have to be a lot more specific about what you are asking.
CSI-2 - Page 1
Forum section: electronics / general

author: beginner43
author_rank: Newbie
timestamp: April 07, 2022, 08:42:18 am
content: Hello, has anyone dealt with CSI-2 before? How is byte synchronization done?

author: mon2
author_rank: Frequent Contributor
timestamp: April 08, 2022, 05:27:49 pm
content: http://caxapa.ru/thumbs/799244/MIPI_Alliance_Specification_for_Camera_S.pdf

author: laugensalm
author_rank: Regular Contributor
timestamp: April 10, 2022, 11:35:40 am
content: Do you want to build your own core or get into MIPI development in general?For the latter, the Lattice Crosslink (LIFMD) architecture is probably the least painful approach towards working MIPI-Hardware.For real world behaviour, you can gather some information from their MIPIDPHYA simulation primitives.

author: beginner43
author_rank: Newbie
timestamp: April 11, 2022, 08:20:30 am
content: Yes, to create my own IP. I will try to do the project with Verilog. Now I am converting the parallel data into serial, but I don't know how to do byte synchronization. Line and frame synchronization are available in their own documentation. There is no problem with them. For example, let's assume that parallel data comes in the CMOS 21.04Mhz 8-bit standard. I want to convert these to pixels to bytes. But I didn't understand the clock and sync part.

author: mon2
author_rank: Frequent Contributor
timestamp: April 11, 2022, 09:17:21 am
content: https://purisa.me/blog/mipi-camera-progress/
EPM240T100C5N -> Fitter requires XX LABs to implement the project but the device - Page 1
Forum section: electronics / general

author: krzysiobal
author_rank: Newbie
timestamp: April 02, 2022, 07:08:12 am
content: EPM240T100C5N is a quite cheap and popular (but obsolete and small in terms of capacity) CPLD from atera.Though for some unknown reason when my design approaches almost the full capacity of chip, I started encoutering synthetisation errors, for example:Error (170012): Fitter requires 26 LABs to implement the project, but the device contains only 24 LABs(the total logic element usage as denoted by Quartus is 237/240 (99%))This error message seems not rational to me, for example - when I hava a design that fits perfectly and in some place of code I change the left one into right one:Code:case cpu_d(7 downto 0) is | case cpu_d(4 downto 0) iswhen "00000010" => | when "0010" =>mapper_current <= MAPPER003; | mapper_current <= MAPPER003;when "00000011" => | when "0011" =>mapper_current <= MAPPER004; | mapper_current <= MAPPER004;when "00000100" => | when "0100" =>mapper_current <= MAPPER002; | mapper_current <= MAPPER002;when "00000101" => | when "0101" =>mapper_current <= MAPPER015; | mapper_current <= MAPPER015;when "00000110" => | when "0110" =>mapper_current <= MAPPER232; | mapper_current <= MAPPER232;when "00000111" => | when "0111" =>mapper_current <= MAPPER007; | mapper_current <= MAPPER007;when "00000000" => | when "0000" =>mapper_current <= MAPPER001; | mapper_current <= MAPPER001;when others => | when others =>end case; | end case;I am getting this error. This is super weird as the logic formula for right one should be less complex as it gets less terms in the case statementOr for example, when I have a working design and change the Fitter seed in quartus (from 2 to 1), it also stops fitting in the resourcesOr for example, when I change direction of one signal from "out" into "inout" (but without any other modifications), I also get this message.Or for example, when I add location constraint to "reserved - as input tri-stated" in Pin Planner to a pin, that is never used in my design, I also get this message.I am using Quartus II 32 bit (13.0.1 Build 232 06/12/2013) - but any newest version seems to abandon the support for this chip.Why is that all hapening?

author: hamster_nz
author_rank: Super Contributor
timestamp: April 02, 2022, 07:25:09 am
content: When you are at 99% utilization the design is going to be very sensitive to little changes.Maybe iit changes from binary encoding to one-hot for a state machine's states?Maybe when you have the extra zeros it can reuse some common logic?Very hard to say...

author: miken
author_rank: Regular Contributor
timestamp: April 03, 2022, 11:11:15 pm
content: Yeah, CPLD tools are not as "smart" as modern tools and they don't seem to try very hard.
Specific to the group but slightly off topic - Page 1
Forum section: electronics / general

author: prophoss
author_rank: Contributor
timestamp: March 15, 2022, 09:44:28 pm
content: My name is Brian Cooper and I am an older student in college. One of my classes is career development. I have been tasked with having an informational interview with someone in a field I would like to get into. My dream job would be FPGA engineer/ programmer. The problem is how would I go about contacting someone in that field? I am not asking for that from anyone here rather, for those in the industry, how could someone contact you so that it would be something you might actually do? The best idea I've read about so far is using Linked In. Simply put I don't know anyone, personally, that does anything remotely like this. This would be a cold call situation. I am hoping some of y'all might help make this a bit easier. I appreciate any help.Brian CooperIf I posted this in the wrong place feel free to move it.

author: hamster_nz
author_rank: Super Contributor
timestamp: March 16, 2022, 07:03:52 am
content: Ask on Reddit : /r/FPGA Be specific about your timezone (or where in the world you are), how long you would want to interview for, and method of talking (email, messenger, zoom, teams).Somebody will answer. They will usually be overly keen sort, happy to talk about their favorite topic.Be aware that most FPGA work will have some sort of Non-Disclosure Agreement (NDA) involved, so people can't talk about the projects they work on, just about the sort of work people do.

author: prophoss
author_rank: Contributor
timestamp: March 18, 2022, 12:29:36 am
content: I appreciate your response. I will give that a try!

author: prophoss
author_rank: Contributor
timestamp: March 29, 2022, 11:15:58 pm
content: Thank for that. I might just do that.
Any tutorial on AXI PS-PL interop for the latest version of Vitis? - Page 1
Forum section: electronics / general

author: Code_Monkey
author_rank: Newbie
timestamp: March 03, 2022, 11:05:08 pm
content: There are some tutorials for older versions of the Vivado SDK, but there were quite a few breaking changes in later versions since Vitis was introduced so I wonder if there are any up to date tutorials?

author: asperised
author_rank: Contributor
timestamp: March 28, 2022, 09:55:34 am
content: I am looking for the same thing so if anyone has any tutorials that would be of great help!
Waveform generation on FPGA - Page 1
Forum section: electronics / general

author: knight
author_rank: Regular Contributor
timestamp: March 21, 2022, 05:22:57 am
content: Can anyone give me an idea on how to generate this RF waveform on FPGA? I already have the I(cos) and Q(sin) signals generated just need a guide to produce this weird shaped pulse. Maybe you can point me to some resource if this has already been done before.Thank You.

author: FlyingDutch
author_rank: Regular Contributor
timestamp: March 21, 2022, 06:50:40 am
content: hello,you have to multiply two sinusoidal signals with different frequencies. The sinusoid with smaller frequency is called envelope. If you have digital samples of these two signals just multiply the samples. Here is few links ilustrating this process:https://electronics.stackexchange.com/questions/32310/what-exactly-are-harmonics-and-how-do-they-appearhttps://www.chegg.com/homework-help/questions-and-answers/multiplying-two-sine-waves-together-observe-waveform-result-outer-sine-wave-called-envelop-q51567387BTW: if you haven't these signals in digital form, you have to change it from analog to digital using ADC (Analog to Digital Converter). Some models of FPGAs have such ADC on-board. The digital samples have to be taken with proper sampling frequency and resolution (resolution is number of bits per sample). The sampling frequency can be calculated from "Nyquist–Shannon sampling theorem" - see link:https://en.wikipedia.org/wiki/Nyquist%E2%80%93Shannon_sampling_theoremThe resolution of samples affect output signal dynamics. Dynamics is signal to noise ratio (measured in decibels).Best Regards

author: hamster_nz
author_rank: Super Contributor
timestamp: March 21, 2022, 07:53:05 am
content: This might be of interest. It seems that the envelopes used are a Gaussian-shaped pulse, followed with a Hilbert Transform Filter.https://www.researchgate.net/publication/233387853_Improving_Quantum_Gate_Fidelities_by_Using_a_Qubit_to_Measure_Microwave_Pulse_DistortionsA web forum on Electronics and FPGAs will most likely not get you a useful answer for such advanced/niche topics.