Need advice, logic gate delay - Page 1
Forum section: electronics / projects

author: ghoetic
author_rank: Contributor
timestamp: April 07, 2024, 03:52:11 pm
content: I am working on a project where i need asymetric delay for the safe turn-off of gate driver buffer.I have two buffers, one forinnerswitches and one forouter. the inner switch need to turn on before the outer turns on and turn off after the outer has turned off (about 1uS should do)currently i latch two types of fault with a nand SR, the final output of the logic is the "enable signal" which is active low. this enable signal need to reach the buffers with the mentioned delays, but i am not quite sure how to make it robust.Any advice?

author: Victorman222
author_rank: Regular Contributor
timestamp: April 07, 2024, 04:32:59 pm
content: For an asymmetric digital delay the first thing that came to mind is a schmitt trigger with RC delay on input but the resistor is bypassed with diode in one direction to get asymmetry (might need schottky diode if low voltage levels). May be a bit of a hack though, i'm not too confident in my digital..

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 07, 2024, 07:08:49 pm
content: Quote from: ghoetic on April 07, 2024, 03:52:11 pmYou can get gate drivers with inbuilt safe dead times. Can you not use those ?1us is a long time for gate delays, so you will need a RC + Schmitt, as above.You can get configurable gates with Schmitt, and TI have a new logic series 74HCS where all pins on all members have Schmitt.

author: ghoetic
author_rank: Contributor
timestamp: April 07, 2024, 07:33:49 pm
content: Going to look into that then (74hc),the deadtime will be MCU dependent , but my application need to safely turn off the gate drivers in case of hardware fault, in the sequence mentioned becasue of the topology "three level npc inverter", so there are 4 fets in a switching leg, and the outer most (1 & 4) need to turn off first if a fault occurs then the inner fets (2 & 3) need to turn of, and the same applies in reverse for when turning back on (first 2 & 3 then 1 & 4).I guess i will need to have one RC with pararell diode to quickly charge and slowly discharge (buffer disabled with high signal, for the outer fets 1 & 4) and the an RC with diode anti pararell to quickly discharge and slowly charge (inner fets 2 & 3)looks ok? any tips?

author: Terry Bites
author_rank: Super Contributor
timestamp: April 08, 2024, 04:08:19 pm
content: Note that series diodes will lower the noise margin of the gate, that could be an issue for LV devicesI'd use a small signal high speed Schottky eg BAS70 and variants.You can probably exploit the intrinsic gate input capacitance rather than using an external C. A typical HC gate will have about 5pF of input capacitance, so 220k puts you in the 1uS ball park.

author: ghoetic
author_rank: Contributor
timestamp: April 09, 2024, 08:03:42 pm
content: Good idea to use the intrinsic capacitance will keep that in mind! but i managed to find my solution.With a total of 12 nands (3x4channel IC) i can make my protection logic including making an OR & AND gate which gives me the desired sequencing of the disable signal, simulated in LTspice

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 09, 2024, 08:14:17 pm
content: Quote from: ghoetic on April 09, 2024, 08:03:42 pmYes, using AND/OR gates can save diodes.This is a link for those TI 74HCS parts, that might reduce your BOM count ? (they are new, so they do not make DIP )https://www.ti.com/logic-voltage-translation/logic-gates/products.html#1512=HCS&sort=1130;asc&The Nexperia LVC family also claim to have Schmitt trigger action on all pins, and the single-gate configurable gates 1G58/1G59 etc all have Schmitt pins.