Transmille 8081 ADC - Page 1
Forum section: electronics / general

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 18, 2021, 02:40:56 am
content: I was the unfortunate winner of the brokenTransmilleFisherprice 8081 that was listed on ebay some time ago.Long story short is that something unwise was done with the input that vaporised part of the input circuitry and PCB. The +15v regulator was burnt short circuit which fed -15V & +25V unreg to everything on the -15V & +15V rails. ToastySpot the difference?I eventually got the thing running and giving readings but wasn't happy enough with it to make any posts here about it.Transmille sometimes respond to messages placed on their system regarding the 8081, but aside from a brief exchange of useful messages with Martin Cox they show little to no interest in support. They won't release any diagrams or service details and they ignore requests to purchase spare parts from them.I've still got more work to do on it, but I've finally gotten around to do something I have had in mind for a while. Reverse engineering the ADC board.Please bear in mind that I haven't reverse engineered a complete board for anything before, so there will be errors.Here's my attempt.[ Specified attachment is not available ]I'm thinking about making another ADC PCB because the reference voltages run through a silly number of vias, quality of the original really isn't great and all of my hacking about has taken its toll.I think I can delete IC16 by using the unused /2 in IC14 in the remake. Comments, fixes and suggestions for changes in the remake are welcome.Edit: fixed unannotated diodes and duplicated resistor numbers.

author: TiN
author_rank: Super Contributor
timestamp: July 18, 2021, 04:44:10 am
content: Would be interesting to see high res photos of the boards (all, not just ADC) of the unit for education purposes. Not very popular unit out there.

author: mendip_discovery
author_rank: Super Contributor
timestamp: July 18, 2021, 08:22:26 am
content: I had one of these in a lab I used to work in, never used it much. I remember that it was still rather experimental when they had it, but the lab manager never knew how to use it. Of the times I touched it I just referred to it as a random number generator, the last 4 or 5 digits were always jumping about. This was before I got my VoltNut and started to hunt for better readings. I left the lab about only a year and a half.I did have some stuff from Tansmille about it, I will see if I can find it.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 18, 2021, 09:26:27 am
content: The ADC looks quite similar to the mark-space ADC of the older Solartron 7081 and similar. The counter part went to the µCs, though still quite a bit discrete logic left.Much of the parts look like standard parts. So they could be replaced if needed. Some of the OPs may have well survived a -15 and +25 V operation.Running the reference through many vias should not be a issue - the voltage of 10 V is relatively high and thus a low µV range of largely constant thermal EMF there should be no real problem.There are other points that can be more important than that:It starts with having 3 separate crystalls that can and will interact in some way. Ideally they would rund in sync and things may be OK - but chances are they are not that equal and would synchonize to a different ratio, ausing trouble on the beat frequency. The creation of the +-10 V reference would be quite important. The buffering of the reference would also be a mayor issue. With long traces there can be RF range issues and some length may even be a good thing, though more a source of trouble.Anyway with 2 µCs with internal flash memory it would be hard to duplicate the board without reusing these chips.The ADC type has principle limitations. So it would likely not be low noise, no matter what. A principle limitiation is that is needs a realtively stable input signal and switching the input would be slow - it may need some 10-100 ms to recover, before giving a stable reading. So a fast auto zero cycle is not an option and ADC drift would thus be an issue. At best I would see it comparable to the Solartron - more like lower grade.It could still be good INL for very long integration times, if everything else is done right.With the PLL chip there is still a chance to get some interference, so good INL is by no way guaranteed.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 18, 2021, 04:24:31 pm
content: Quote from: TiN on July 18, 2021, 04:44:10 amThere isn't much more to see over the pictures your have on xdevs.Is there anything in particular you want to see?

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 18, 2021, 04:29:03 pm
content: Quote from: mendip_discovery on July 18, 2021, 08:22:26 amThis wasn't the most stable measurement in it's original form.Transmille do something odd with the 50Hz sync that causes noise. The original code in the 18F252 timing pic switches on the UART TX and feeds it to IC11 where it mixes and offsets the zero crossing. Not to mention that when the IC11 output transistor switches to ground, shorting out the UART, it introduces > 10mV of noise on the 5V rail.Switching off the UART and swapping the inputs to IC11 reduces noise a LOT.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 18, 2021, 04:57:22 pm
content: Quote from: Kleinstein on July 18, 2021, 09:26:27 amA couple did survive, but not many. All of the muxes went low resistance and drew enough current to blow fuses. The LTZ IC went thermonuclear and melted the foam insulation around it.Quote from: Kleinstein on July 18, 2021, 09:26:27 amI can rework the 10MHz in the remake. Single crystal through a buffer?The reference is a datasheet copy circuit with the LTZ1000CH package mounted inverted on the PCB.2 x OP177 generating main 10V/-10V Vref and 2 x OP27 in unity gain providing 10V/-10V buffered Vref.The reference is a good 30cm away from the ADC. I have considered moving it to the ADC boardIn the attached case image the red and blue lines are the +10V/-10V reference voltage path, and the green line is the path for the reference 0VQuote from: Kleinstein on July 18, 2021, 09:26:27 amI have copied the PIC micros.Quote from: Kleinstein on July 18, 2021, 09:26:27 amThe last pieces of the puzzle (VHP202) will hopefully be on the way to me shortly. If all works out as planned I'll log some measurements and post results.

author: guenthert
author_rank: Frequent Contributor
timestamp: July 18, 2021, 05:07:04 pm
content: Thanks for the ADC schematic. Perhaps I'm looking at an older drawing (Ref 1), but I'm pretty sure that R6 is connected to (some) GND, much like R5 (R6, R20 forming a voltage divider, much like R5, R11). Further, I have a hard time believing that there shouldn't be any DC feedback for IC1, IC2.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 18, 2021, 05:25:36 pm
content: NO direct feedback at IC1 / IC2 is correct, this is an 2 OP integrator with IC1 for the low frequenccies and IC2 for the higher frequencies.The DC feedback comes via the reference switching. Any direct DC feedback would cause INL errors, so there may be extra guard-traces to avoid it.If one would really respin a PCB for the ADC here are a few points to consider:For the clock, my favorite would be a single canned oscillator and than maybe (but not absolutely needed) extra buffers / level shifters.I would consider a little low pass filtering for the AC signal goint to IC11 - this could reduce some effect of a poor mains waveform.The supply decoupling can be critical at a few points: The PLL chip and IC11 - jitter here can cause noise and a frequency modulation from the input signal may cause INL errors.The switches at IC6 may also be critical with the supply. At least they are possible sources of interference / noise. So it may be good to have more than just a decoupling cap, but also some series ferrite / resistor to separate it from the main supply.The LTC1150 AZ (IC1) is an old and rather noisy type. The input impedance is rather high, so a very low noise type like OPA189 is not a good choice, but a AD8628 should be OK. There is no need to have a high supply for this OP: +- 2 V would be enough.Ideally one could add a slope amplifier before the comparators - this may be lower noise than the LM311.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 18, 2021, 05:26:57 pm
content: R6 and R20 in my diagram appear to be correct.There are no top side traces for either R6 or R20 footprint, and R20 routes through a via to IC3 pin 3IC1 and IC2 don't have any feedback other than C6 and C7

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 18, 2021, 05:36:40 pm
content: Quote from: Kleinstein on July 18, 2021, 05:25:36 pmThanks for that. I'll tidy up the schematic and apply your suggestions.The decoupling of the supply is shockingly bad on the original PCB. There are a few 100nF scattered about the board, not necessarily near to IC supply pins.Do you have an understanding of what IC7 is achieving? Half of it isn't connected and the other half is in a static state that doesn't seem to have a purpose. Other than shifting the references a little, removing it has no effect on operation.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 18, 2021, 06:50:39 pm
content: Pictures of the ADC boardOriginally the integrator side was pottedIt took a while but I eventually got the potting compound off - revealing

author: branadic
author_rank: Super Contributor
timestamp: July 18, 2021, 06:52:01 pm
content: Thanks for sharing the pictures. The implementation of the reference is amazing, allthough I'm missing in copper etched excommunication to complete the magic.-branadic-

author: Kleinstein
author_rank: Super Contributor
timestamp: July 18, 2021, 08:42:48 pm
content: The connection to ground via IC7 should have some purpose: it avoids the point between IC6A and IC6B to be floating in the short time between the 2 phases with positive and negative reference. The controls by 2 switches in series is odd, but could still work. I would have more favored a logic connection and only 1 switch. It should not be static.The effect of removing this chip could be small, but effecting the INL. A few ppm change of the signal may not be much but could still be quite some effect on the INL.The UART part at the 50 Hz clock input looks odd. It can still make sense to have the option to choose between an crystal clock and the 50 Hz mains signal. Though just connecting the 2 signals is kind of a fail.Decoupling is a tricky part. In many areas one can get away with surprisingly little. In other cases decopling can make quite some difference. It is a bit hard to tell upfront. With my ADC version I see a measurable effect on how decouling near the oscillator is done. Other parts look possibly sensitive, but in my case did not show much effect. HP did notice an effect of decoupling capacitance at the integrator at the 3458 (though a different circuit). The relatively slow modulaton (200 Hz forcing frequency compared to some 330 kHz in the 3458 or 34401 can make some effects like decoupling and also clock jitter less important.Still it makes not much sense to save on the decoupling - it is like 1 cent for a cap or resistor and maybe 5 cents for a ferrite.From the pictures decoupling does not look so bad, though it could be better.The part around R20 / R6 looks indeed suspect, but the pictures also look like that is the way it is. Is the ouput of IC 3 at all active in this confuguration - this could explain why IC7 is also static, not doing much. The logic way would be 2 trigger levels just a bit separated, like +-10 mV from ground.For the resistors at the ADC input one could also consider an resistor array and maybe get away with 150 K (instead of 160 K) and 100 K. It could be at least an alternative footprint. The input range would be a bit smaller.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 18, 2021, 10:16:51 pm
content: Quote from: Kleinstein on July 18, 2021, 08:42:48 pmThe max313 IC7 switches are normally open. When powered on switch A closes, but switch D always stays open with the -10V applied to its control line.The ground on IC7 pin 14 isn't utilised.Quote from: Kleinstein on July 18, 2021, 08:42:48 pmIt's a bizarre choice to have the UART enabledandhave the pin as an input at the same time.Quote from: Kleinstein on July 18, 2021, 08:42:48 pmFor the respin I'll add more decoupling closer to each IC. I'll re-route the supplies to. The clock generator and its subsequent dividers will get their own clean supply.Quote from: Kleinstein on July 18, 2021, 08:42:48 pmScreen grabs attached from pin 7 outputs of IC3 & 4. Taken with 10V input to the ADC board.Quote from: Kleinstein on July 18, 2021, 08:42:48 pmInput resistors must be as low TCR as possible. It's just about usable with a 3ppm/C, anything worse than that shows large drift with case temperature.

author: TiN
author_rank: Super Contributor
timestamp: July 19, 2021, 03:38:36 am
content: Cool looking, but pointless LTZ design. Also that wirelessly connected resistor near LT1013 opamp looks like just what needed for ultimate LTZ trim.What is the board with shield, "10 ohm" transformer and SMB connectors? AC board? I think the more photos shared the better, in case somebody in future wants to compare/repair different 8081s. You can upload RAW images to my FTP, I'll move them to 8081 folder.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 19, 2021, 03:53:55 am
content: The 390K is lifted because I was experimenting with trimmingThe board with the 10 ohm writing is the electrometer. That is also brokenI haven't bothered looking at repairing that board yet. No point until the rest of the DMM is working.I've roughly scribbled the main functions on to the pictures you have on your site. Hopefully it will help if you're looking for a particular section?

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 19, 2021, 04:58:20 am
content: Quote from: rigrunner on July 18, 2021, 10:16:51 pmLooking at the Solartron 7081 schematic I see what is supposed to happen with IC7. In the 8081 it's broken by designI should be able to implement a fix that will short R10 to 0V in the dead time between IC6A and IC6B activity.Modified like this

author: Kleinstein
author_rank: Super Contributor
timestamp: July 19, 2021, 06:13:17 am
content: For the resistors at the input the requitement is a low relative TC. This can be achieved with good resistors as shown, but also with a resistor array. The relative TC specs for LT5400 and MORN arrays are quite good. In my ADC circuit I see a relative TC of around 1 ppm/K for ORN and NOMCA (not good noise wise) resistor arrays. So the relative TC could be at an acceptable level. It may still need some tests. There is also the problem that LT5400 and MORN are quite small size and thus possibly more self heating. With some luck the relative TC for the resistor array may be comparable to the BMF resistors. The advantage would be mainly a lower price and possibly faster (may be of the shelf) delivery.There is anyway some residual TC from the switch resistance. With low R resistors and relatively large resistors at the input the effect would not be very large though. 12 Ohms / 100 K * 6000 ppm/K is 0.7 ppm/K contribution. So one may consider a possible compensation with a resistor of known positive TC in series to the input path. Something like a PT100 with some 100 Ohms in parallel could be an option for the compensation and may also be used for a little trim (only workung for the amplifier gain, but not the INL from self heating).The comparator IC 3 seem to still work despite the odd resistor R20.Thanks for the pictures with shown functions. I would guess the still unlabled part above the AC part should be the AC amplifier / rang switching.The DC input part seems to also include an amplifier, not just a buffer.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 19, 2021, 03:25:12 pm
content: Quote from: Kleinstein on July 19, 2021, 06:13:17 amI'm thinking of putting footprints in for PWW and arrays along with the BMF. There will be plenty of space and as you mention, much cheaper.Quote from: Kleinstein on July 19, 2021, 06:13:17 amI'll bear this in mind.Quote from: Kleinstein on July 19, 2021, 06:13:17 amIf I tie pin 3 of IC3 to ground (as the Solartron does) the output from IC3 inverts but everything still works.Quote from: Kleinstein on July 19, 2021, 06:13:17 amYou are quite right on both accounts. I quickly scribbled on Tin's pictures without much thought for finite detail.I'll try to take some pictures of all of the sections and make a better attempt at showing each one.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 19, 2021, 05:48:06 pm
content: Quote from: rigrunner on July 19, 2021, 03:25:12 pmI don't think the signal would really be inverted, it is more like a change in the signal that makes it looks like it. With 3 possible states of positive zero and negative reference there are more options to get the same feedback. The change in the comparator level would change from zero to positive/negative combinations. It may also effect the maximum range for the signal. It depends one the details of the forcing signal how large the range is. AFAIK the useful range is largest with quite some difference between the comparator levels.I am a bit surprised that the clock frequency is quite low with only 6.25 MHz for the synchronizing flip-flops. This would limit the resolution at short (e.g. less than 10 seconds or so) integration time. The newer Solartron DMMs use a really high clock frequency (close to 50 MHz).A point to consider would be to change the option to choose a crystal based clock instead of the 50 Hz PLL. The old, likely not working way with the UART signal would still have the jitter from the PLL. The better way would be to switch the clock behind the PLL chip, so that the crystal clock would be low jitter.I have looked at the noise for a multi-slope and similar ADC quite a bit. So I could do an analysis of the expected noise levels and the expected dominant noise sources. What are the relevant integration times used ? I would expect them to use mainly longer integration, like 10 seconds. I would expect the performance for short integration quite poor and quantization limited.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 19, 2021, 06:13:33 pm
content: Quote from: Kleinstein on July 19, 2021, 05:48:06 pmQuote from: Kleinstein on July 19, 2021, 05:48:06 pmOne of the use cases for the CS2000 pll is jitter removal. I guess they chose it for this reason?Quote from: Kleinstein on July 19, 2021, 05:48:06 pmThe fastest integration time with 8 digits is 4 seconds. Maximum selectable is 64 seconds.Fastest at 7 digits is 1 second, and at 6 digits or less fastest is 125ms.In 8 digit mode at 4 second integration the last digit appears to be restricted to increments of 6 or 7. e.g. 10.000,000,0V would move to either 10.000,000,6 or 9.999,999,3 - is this your expected quantization limit in action?

author: Kleinstein
author_rank: Super Contributor
timestamp: July 19, 2021, 07:30:16 pm
content: The 0.6 to 0.7 µV steps after 4 seconds corresponds to the simple calculation:With 160K and 100 K at the ADC the theoretical range would be up to 16 V. This is divided by 6.25 MHz and 4 seconds which results in some 0.64 µV steps.In theory there may be a little extra resolution from looking at more start / stop values (a bit like higher order filter), but it seem to be not using this and the rather slow (200 Hz) modulation does not make this very attractive.I would normally call this 7 bit resolution, not much better.Similar I don't think 125 ms would really give 6 digits. I should more like takes 250 ms for digits.Theoretical ( use the root of 12 factor) 0.64 µV quantization would correspond to 180 nV RMS noise - if this would be simple quantization with no other noise. However here it is quantization at the start and stop at least, so 250 nV expected quantization noise alone after 4 seconds. So some 10 seconds integration to get 100 nV quantization noise (still more than 100 nV steps !).The CS2000 may be used for jitter removal for the 50 Hz mains clock, but the jitter specs I found (~60 ps) are not that great compared to a low cost crystal oscillator (e.g. 1 ps range). Jitter specs are still a bit tricky, as there are different conditions / time windows used. There would be additional jitter from the logic anyway, but better than 10 ps jitter would be nice for the clock. It may be a good PLL, but even with a very good input signal it is hard to get good jitter specs for the much higher clock. The importance of jitter scales with the square root of the modulation frequency. So jitter is much less (e.g. a factor of 30) important than with the fast modulation MS-ADCs. So the PLL may be just good enough to be not a mayor problem. Chances are the rather slow modulation is chosen because of jitter from the PLL.The effective input noise from jitter should be square root of the switching frequency (4x200 Hz) times the jitter amplitude, times 16 V (theoretical range). So this would be some 27 nV/sqrt(Hz) and thus still OK. a poor mains signal may still add jitter, though the PLL (seems to be digital) could be quite good in suppression here and may not add much extra noise.An easy to handle noise source are the resistors at the integrator. As the noise adds as current noise the 100 K would act like about 256 Kohms in series to the input. So a total effective resistance of 416 Kohms or some 83 nV/sqrt(Hz) from the resistor Johnson noise alone.The OPs (LTC1150) low frequency noise is multiplied by a factor of 2.64.16due to the resistor ratio. So this would be some350 nV/sqrt(Hz)220 nV/sqrt(Hz)- a major noise source. So it could be worth using a lower noise OP here. They are available, with more choice with a low supply voltage, which would be sufficient.The overall input referred noise sources should be at some400300 nV/sqrt(Hz). For 4 s integration the BW is 1/8 Hz. So the white noise would correspond to some140100 nV_rms. So at 4 seconds the quantization noise may still be dominant to the other noise sources. Less noise from the OP would mainly be effective a longer integration, like 16 seconds or more.The higher frequency noise of the OP27 and the LM311 comparators would compete with the quantization noise as they have the same dependence on the integration time.It is a bit hard to estimate an effective BW and noise for the LM311. The bias current suggest a noise level in the 10 nV/sqrt(Hz) range. For the BW I would estimate some 10 MHz, maybe a little more.This would give a high frequency RMS noise of some 30 µV. The slope is 10 V / 100K / 100 nF = 1 V/ms.So the 30 µV would correspond to 30 ns_rms for the comparator timing. With 6.25 MHz the quantization noise is at some 46 ns_rms and thus comparable. Reducing the comparator noise would thus be only partially effective, as there is still the limited quantization.So for 4 second integration I would expect the main noise sources to be1) quantization: ~ 180 nV_RMS2) LM311 ~ 120 nV_RMS3) LTC1151 ~12580 nV_RMSThe LTC1151 noise gets more important for longer integration, less for shorter integration.For a board remake, the question is, if this is meant only to be used in the transmille DMM or possibly also "standalone" with maybe a simple extra front end (e.g. buffer only).

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 19, 2021, 07:45:48 pm
content: There are a quite a few things there to take into consideration. I'll need to digest and ponder a little.Quote from: Kleinstein on July 19, 2021, 07:30:16 pmA stand-alone PCB isn't something I'd considered...If I do place the reference on the ADC board it lends itself even more to becoming a stand-alone option. Yes, OK I'm gameIf the remake PCB for the DMM works i'll take that as the base and if you're willing to assist in upgrading I'll turn that into a stand-alone that others can make too.I have the firmware from the two PIC micros that can also be reworked if needs be, but that might require someone with good PIC skills to make that happen quickly.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 19, 2021, 08:07:55 pm
content: Even with some slight improvements (e.g. 2x the clock, lower noise OP, slope amplifier to improve on LM311 noise) the performance of the ADC is still not great. The INL may be good, but there are enough details to do wrong here.For a standalone version a simple LM399 reference may be good enough. It still needs the +-10 V scaling part, which can be one of the most critical parts from the components. An error in the ratio of 10 V to -10 V would result in an offset error / noise to the ADC. So the OPA177 used there could be a major noise and drift source, if there is no extra auto zero mode (which is a bit tricky with the slow ADC).

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 19, 2021, 10:54:10 pm
content: Quote from: Kleinstein link=topic=285380.msg3610653#msg3610653It would be simple enough to reconfigure the 74HC390 chain to divide down the new 10MHz oscilator to 200Hz and remove the whole 50Hz line sync and pll. Would anything be lost by doing this? I'm thinking perhaps mains frequency immunity might be a side effect of syncing to it?Quote from: Kleinstein link=topic=285380.msg3610653#msg3610653I've added your earlier suggestion of the AD8628 to my updated schematic. With a pair of 13V zeners from the 15V rails to run it at +/-2V. The 5V rails are noisy and full of hash.Quote from: Kleinstein link=topic=285380.msg3610653#msg3610653For1) it would need the modulation probably quadrupling and the software tweaking to make any real reduction.2) does switching to an LT1011 help here? 20-25nA IB.3) this is the low hanging fruit. Do this first and tweak other stuff afterwards.Quote from: Kleinstein link=topic=285380.msg3610653#msg3610653I've previously wondered if an LT1044A might be put into use to generate the -10V. Or something similar to how Datron 12x1 generate their inverted reference. Leaving only the 7->10V boost amp and one divider as main noise and drift sources.

author: TiN
author_rank: Super Contributor
timestamp: July 20, 2021, 08:21:47 am
content: I did run few INL tests for 8081. Setup is typical, source was calibrated Fluke 5720A.For completeness and sanity check other DMMs also connected in parallel.HP3485A is old good unitHP3458B is Agilent unit with drifty A3 ADCK2182 was used with channel 1F8508A is RESL8. FILT_OFF modeAll units were configured same NPLC30 readout, guard floating.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 20, 2021, 08:57:08 am
content: For improving on the quatization noise, it would be a faster clock for measuring the timing. Usually the signal from one of the comparators is used (here by the PIC) to measure the exact timing at the start and end of conversion. A faster clock would likely need a modified software, except maybe a simple factor of 2 for all and than getting half the integration time than set. The crazy case would be to also directly measure the time at the comparator output with some time to digital solution. There are ways to convert the time difference at HC175 flipflop to an analog voltage, as a kind of analog interpolator. Similar solutions are used in high resolution counters / timers. It may not even need that much extra HW, but quite some addition to the software.For the comparator noise the bias current gives an indirect hint on the current used in the input stage and this way the noise. So a higher bias is more like indicating low noise. The way to reduce the noise would be a kind of slope amplifier (only needed for one of the comparators,but could be used for both). This would be an extra low noise (e.g. OP27, NE5534) OP adding gain (e.g. 5 x) and limiting the bandwidth (no need to be super fast like the comparator, some 0.5 to 2 MHz BW should be enough).The noisy part in a slope amplifier may be actually a resistor and for the extremes one would use JFETs there, like in some very old meters.Something like a factor of 2-3 comparator noise reduction should be easy from the reduced BW. Maybe another factor 1.5 from lower noise from lower amplifier noise, though in the simple form a 6 K resistor may have similar noise as the LM311. Just an RC filter would not work, as much of the noise is likely from the comparator itself.Speeding up the modulation could help indirectly: with a faster modulation the integration capacitor could be smaller and thus less charge noise from the same voltage noise. However faster modulation makes the jitter and possible switching artifacts more important. The PIC software would also have slightly less time, though likely not so critical.A slight change in the modulation speed (e.g. 250 or 300 Hz) would be probably still acceptable, but it should still be an multiple of 50 Hz.The mains syncronous PLL has some sense. The mains suppression is quite a bit better in synchronous mode. With a relatively high hum level there can be additional problems to the normal residual beat frequency. However with a poor mains waveform the PLL could also be major noise source. I don't know how good the PLL is in removing jitter from the mains input. Not all jitter parts are equally bad and it is thus hard to judge. So it would be nice to have both options: with a mains PLL or with a stable low jitter crystal clock. It depends on the conditions which mode works best. Some of the Solartron meters (AFAIR the 7061) have the option for a crystal clock instead of the PLL, though AFAIK no easy switching between the 2 options.For the supply of the low voltage AZ OP, I would not use simple series Zeners to reduce the voltage. More like extra filtering and than zeners, LEDs (or TL431) as shunt regulators. With enough filtering even noisy +-5 V may not be so bad.A switched capacitor part for the -10 V generation would definitely be a possible way. It still needs some fitlering for the output. The amplifier for the -10 V part would also add to the noise. If the original is an OPA177 one would see it's low frequency part, so possibly quite some 1/f noise. Similar noisy resistors (like an NOMCA array) could add quite some 1/f noise.I would expect the meter to use only very infrequent drift correction like the Solartron meters. So the effective frequency is very low.The INL does not look very good. With a noisy supply this is not such a surprise, though the square law part does not look that much like supply coupling. Maybe more loading down the references.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 20, 2021, 04:50:29 pm
content: Quote from: Kleinstein on July 20, 2021, 08:57:08 amI may tackle this after the other changes are in place. Even though the code in each PIC is small it will take me some time to disassemble and comment it.Quote from: Kleinstein on July 20, 2021, 08:57:08 amWould this be acceptable to place between the output of IC2 and inputs to both comparators? Would lower value resistors than the 1K/4K3 lower the noise further?(inline image doesn't seem to be working for me)Quote from: Kleinstein on July 20, 2021, 08:57:08 amI have replaced the 47K resistor in the mains sampling input with a low pass.I can get a 6.25MHz oscillator from mouser, there should be enough room to have it alongside - or perhaps add another chain of HC390 to divide the 10MHz micro clock to 200Hz with a solder bridge select. Tying the PLL lock detect low allows start up to continue with the PLL disabled.Quote from: Kleinstein on July 20, 2021, 08:57:08 amI'll play around with the supply options...Quote from: Kleinstein on July 20, 2021, 08:57:08 amY1365V0008QT or LT5400AHMS8E-1 both look OK TCR wise. Would they be OK noise wise?Vishay part is twice the cost of the LT.Quote from: Kleinstein on July 20, 2021, 08:57:08 amThe UART signal being pulled to ground was causing lots of 50Hz noise on the +5V rail, and the logic inputs of a MAX313 were connected to the +/-10V references. Would they have an effect on INL?@TiN It will be interesting to compare the modified 8081 to the set you checked out. I only have an un-calibrated 5440B to run against.Edit: Typo on low pass R18 and R24 should read 24K.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 20, 2021, 08:14:26 pm
content: The slope-amplifier usually has additional back to back diodes in the feedback, so the OP is not driven so hard into saturation and also the comparator sees only a smaller signal. In addition a cap to reduce the BW may be good. A single slope amplifier for both comparators can be OK if the 2 trigger levels are similar (e.g. within some 400 mV after the gain). The less critical comparator could also use to signal directly from the integrator - usually only one comparator is used for the start / stop of integration, though in theory both could be used with averaging for reduced noise.The resistor values are a balance between the noise and the current drawn: there could be quite a bit of current with a large input from the integrator.I don't think it is needed here, as the quatization noise is more limiting, but as an alternative solutuion one could replace the low resistor with 2 JFETs, to give a low resistance at low current and than limit the current to some 1-3 mA. The exact gain of the amplifier is not critical, only that it is reasonable stable for one convesion. I would consider the main advantage in a reduced (controllable) bandwidth, not so much in having a lower noise density to start with.With reusing the µC code in a new board there could be a copy-right problem. So there could be a catch with the stand-alone idea.Ideally it would be a new software and just get the info on the interfaces / messages. Still not sure if this would worth the effort. The ADC is still not very low noise, slow (or limited resolution) and quite some effort. I may be a bit biased here, as I have my own ADC design with less effort and noise. However it is made for an AZ mode in the front end and thus not easy to use in the 8081 environment.The jitter is slightly less critical with the 200 Hz forcing signal, than with the clock to the HC175 flip-flops. If the 10 MHz µC clock would be used, one could also use a µC timer to create the 200 (or 400 Hz) signal - so no need for another divider chain, just switching of the clocks.As far as I see it the CS2000 should normally run with 3.3 V supply - though 5 V supply is still in the absolute maximum range. Lower supply would reduce the supply current and spikes. Not many parts actually need the full 5 V (e.g. the RS232 and external control).The LT5400 resistor array should be OK from the noise. Normally the higher tolerance version should be OK too. It is not so impoartant that the 2 are really accurate, but they should be very stable over the time of a experiment (e.g. a few hours). Drift of the resistors results in offset drift of the ADC. 1ppm ratio dirft would correspond to some 16 µV ADC drift. So there is a reason one wants resistor excess noise levels very low (e.g. better -50 dBi).Noise of the amplifier for the inversion comes to the result with a gain of 1.6 (or whatever the resistor ratio at the integrator).The capacitor C1 looks quite large to me. I think one should get away (and get a better settling after jumps) with a little less capacitance. I see no real need for a PP cap here. A smaller size MKS type should be sufficient. Similar C2 should be OK with MKS and less size to reduce the parasitic capacitance.The max313 not switching correctly and thus a floating resistor could be an INL issue, though this is hard to tell. If the 2 compararator levels are close togehter, the high Z phase would be only quite short and not too variable in length. Some 50 Hz hum on the 5 V supply would be less of an issue, but if the state or switching of the HC175 or the 200 Hz signal has an effect on the 5 V supply and this effects the 10 MHz clock at the CS2000, this could be an issue.My main suspect for the square law INL part is an effect of the charge injection of the max312 switches to the +-10 V reference signals. With rather large 3.3 µF caps, the recovery of the reference signal can take quite some time. So while the large caps help to keep the spikes small, they also extend the time. It may be worth testing smaller caps there, so that the reference signal would recover in less than some 100 µs. Short pulses would more like cause an offset only, not INL. INL is possible if the recovery takes longer than to the next time the reference is switched. It may be good to have seprate buffers for the forcing signal and the main reference signals to the other half of the max312. The extra buffers are quite some effort.For linearity testing calibration of the 5440 calibrator should not be very important.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 20, 2021, 10:27:46 pm
content: Quote from: Kleinstein on July 20, 2021, 08:14:26 pmThis is my current iteration. The GBW of the OP27 is 8MHz. Gain setting is x174 that gives a BW of 45KHz. Too tight?Quote from: Kleinstein on July 20, 2021, 08:14:26 pmI've changed them to reduce current, increase gain and the anti parallel diodes should prevent saturation. The low resistor is a small value now, so shouldn't require JFETs.Quote from: Kleinstein on July 20, 2021, 08:14:26 pmA fair comment regarding copyright. When I take a look at tweaking the software I'll have an idea of what is involved and how tricky new software will be.Quote from: Kleinstein on July 20, 2021, 08:14:26 pmGood point. I'll take a look at that.Quote from: Kleinstein on July 20, 2021, 08:14:26 pmLowering the supply to the CS2000 would further isolate it from the other supplies and noise. I can experiment with this on the current board prior to the rework.Quote from: Kleinstein on July 20, 2021, 08:14:26 pmI'll add a footprint for the LT5400, along with PWW and VHP.Quote from: Kleinstein on July 20, 2021, 08:14:26 pmI'll test some other values and types on the existing board and see what difference it makes. I think I have some 220nF mkp caps hanging around.Quote from: Kleinstein on July 20, 2021, 08:14:26 pmThe 5V rail has a small amount of 200Hz + 50Hz remaining on it. More bulk and bypass caps to be added and maybe some ferrites for the clock part.Quote from: Kleinstein on July 20, 2021, 08:14:26 pmThis is a deviation from the 7081. Are the 3u3 caps there because the reference is 30cm away?I have some similar 1uF caps that I can try in place.Edit: Forgot to add that the REFBUF signals are buffered from the OP177 REF signals by OP27. These are also 30cm away from the ADC PCB.Quote from: Kleinstein on July 20, 2021, 08:14:26 pm

author: Kleinstein
author_rank: Super Contributor
timestamp: July 20, 2021, 11:01:33 pm
content: At the slope amplifier the resistor to ground would still see nearly the full input voltage (integrator swing). This is why one can not use a really small resistor there. I would consider some 2 K the practical minimum. If really less noise is needed, 2 JFETs (low threshold) with a resistor in between would be the option to get low resistance in the critical range and still limit the current.I think 140 x gain would be a bit too much and too slow. The minimum pulse length should be around 100 µs and settling should be quite a bit faster. So I would like to have still some 100 kHz BW at least. There is also no real need to lower this noise part that much: the quatization noise is comparable, if not higher. So a factor 10 down in the BW and thus a factor of 3 in the noise should be enough.This would still allow some 5 K as the lower resistor.Anyway it is only a question of resistor value, not effecting the layout.For the value of C1 and the spacing of the compartors it may make sense to run a simulation (e.g. LTspice). The value effect the speed a stable integrator waveforme is reached and thus the settling time are a jump. Not well settled the INL error can be larger, depeding on how much math is used for the result.I think the 2.2 µF (or 3.3 ?) caps at the reference are there to reduce the drop in the voltage from the charge injection. The long trance may be part of the reason, though there is still a limited speed of the buffer. The reference for the forcing signal would be the slightly less critical part.One may be able to lower the capacitance quite a bit - like in the 100 nF maybe even 10 nF range. The buffers can be quite a critical part. Extra Buffers would also add noise and drift.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 21, 2021, 04:53:28 pm
content: Quote from: Kleinstein on July 20, 2021, 11:01:33 pmExperimenting with values for the 3u3 capacitors turned up something unexpected.With my IC7 modification removed and the circuit restored to original static state I can drop the capacitor values down to 100nF without any adverse effects.With my IC7 modification in place the -10VREF, -10VREFBUF and 10VREFBUF are still fine down to 100nF, but the 10VREF goes into wild oscillation.With 3u3 it is stable. With 1uF there is oscillation at mid 30s KHz and with 100nF oscillation is at mid 40s KHz.Also noticed another deviation from the 7081 implementation. The forcing waveform on the 7081 appears to be 0V (both reference voltages switched together via 1K resistors) whereas the 8081 switches both references separately.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 21, 2021, 06:19:09 pm
content: The DG301 should be a SPDT switch. So the 1 K resistors at the Solartron 7081 are just at the reference side, reducing the switching spikes to the reference. So they effectively replace the buffers there.A large capacitor like the 3.3 µF usually needs an amplifier / buffer that is made to tolerate this capacitance. If it oscillates with a slightly smaller cap (like 1 µF) this is not a good sign: it is likely not very stable with the 3.3 µF either. If it is just an OP with no extra measures it would need something like a series resistor or manybe a capacitor and RC in parallel (e.g. 100 nF to ground and 22 Ohms + 220 nF in parallel). Which combination is suitetable depends on the OP and details of the amplifier / buffer.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 21, 2021, 07:40:43 pm
content: Quote from: Kleinstein on July 21, 2021, 06:19:09 pmWhen the forcing waveform drive signal is applied the two references are combined to cancel out. The 8081 switches the forcing waveform between +ve and -ve reference.Quote from: Kleinstein on July 21, 2021, 06:19:09 pmThe 10V reference is an OP177 with a vishay 25K/10K divider to give 1.4x gainNegative reference is another OP177 with the usual 10K/10K arrangement.Both have 10nF MKS feedback capacitors and a 220pF cap across their respective inputs.I'll experiment with them later to try and find out why one goes into oscillation but the other doesn't.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 21, 2021, 09:47:27 pm
content: The forcing signal needs to switch from +ref to -ref. The DG301 has one of the 2 switches with inverted polarity. So the drawing is misleading and there is only one ref. active at a time (except maybe for a very short time, if there is no defined break before make).The OPA177 probably does not like driving a hefty capacitive load. The 220 pF across the inputs may help, but this is probably still only borderline stable and slow settling. The usual circuit to drive a highly capacitive load is with an extra series resistor and seprate high and low frequency feedback. For fast settling one would include a fast in loop buffer and low ohms series resistor (e.g. 20 ohms range - what the buffer can compftably drive). Ideally the OP for the inverter would be lower low-frequency noise and maybe an AZ OP like LTC2057. For the 0.1 Hz noise the OPA177 is not that great.The buffers with the less critical forcing signal are good: so spikes from the forcing signal would not effect the main reference, which would cause an INL error. A simple buffer would still be OK - it does not even have to be super stable, as the output is AC coupled anyway. So the OP27 there are more like overkill, but OK. Filtering the signal to the buffers for the forcing signal would be nice and simple. It would avoid coupling the other way around, though this is allready less critical.Extra buffers instead of the large filter caps could be an option, but the bufers would add noise and drift. So ideally it would be directly the 7 to +-10 V circuit that has good drive power, so it would get away with smaller caps (e.g. more like 10 or 100 nF and not 3 µF).I had a though on the value of C1: the large capacitance helps getting a known slope for the start to stop difference. A smaller cap would give more noise with a not so stable signal and thus waveform. So there is justification for the large cap. The option for a smaller cap at the forcing signal is with a slightly different, related ADC version that uses a separate "integrator" for the forcing signal.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 21, 2021, 10:24:52 pm
content: Quote from: Kleinstein on July 21, 2021, 09:47:27 pmThat makes sense. The diagram looks to show both switches operating at the same time in parallel.Quote from: Kleinstein on July 21, 2021, 09:47:27 pmAs a test I powered the 8081 on with 100nF caps in place of the 3u3 and with the 220pF across the OP177 removed, and the oscillation frequency has almost halved. Resistor for the next test.I'll add swapping the inverter to LT2057 to my notes. For tweaking later.Quote from: Kleinstein on July 21, 2021, 09:47:27 pmIf I can get rid of the oscillation I'll keep testing with lower caps. Would you keep the film caps as for the 3u3 replacements?Quote from: Kleinstein on July 21, 2021, 09:47:27 pmDoes the physical size of C1 & C2 have any benefit to the circuit?

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 22, 2021, 04:19:59 am
content: There's something odd going on here that eludes me.Original IC in 10V boost stage was OP177.[ Specified attachment is not available ]With ADC PCB unplugged and traces to the other two outputs cut so that the OP output is isolated it still oscillates.Remove 220pF across inputs, still oscillatesSwapped OP177 with a new one, still oscillates.Swapped vishay divider for pair of S102, still oscillates.Swapped those for pair of PWW, still oscillates.Swapped those for pair of S102 10K, perfectly stable.Put divider back to 25K/10K and swapped OP177 for OPA277, oscillates again.Replaced OPA277 with LT2057, still oscillates.[ Specified attachment is not available ]Adding the 3u3F between the OP and GND for any of the oscillating states and everything is stable.Edit: added 10nF to circuit

author: Kleinstein
author_rank: Super Contributor
timestamp: July 22, 2021, 07:06:43 am
content: With the capacitive load from the ADC board most OPs will tend to oscillate.Without the capacitive load the OPs should be stable. The type of resistors should not make a difference, especially not with already the 10 nF cap in the feedback.The 2 OPs for the gain stage and the inverter may couple though the supply. Especially the negative supply has rather poor PSRR. The OPA177 is however not that fast to be really picky on the decoupling or prone to oscillation.I somewhat doubt it can be so simple as putting the 220 pF cap between the inputs to make the OPA177 stable with a large ( > 10 nF) capacitive load. Even if stable it would be more like marginally stable and still not good: instead of a short drop there would be ringing. The amplitude may not be visible with the short spikes from the switches, but it could still cause trouble.The OPA202 may be slightly more tolerant to capacitive load, but I doubt it would help with more then 100 nF.They mention 25 nF with still a fast recovery. This is already quite good for a BJT based OP. For some reason I don't know good capacitive drive capability is more often found with FET based typesThe Solatron circuit gets away without extra capacitors at the references output. So it may be still an option to totally skip on the 3.3 µF caps at the references (quite sure this is OK for the forcing signal with the extra buffers). For the main reference I would consider something like 50-100 ohms in series with some 10-100 nF as a little support, but without negative effect on the stability.Small physical size of C1 and c2 could reduce parasitic capacitance and hum pic up, but is not that critical.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 22, 2021, 05:43:09 pm
content: Quote from: Kleinstein on July 22, 2021, 07:06:43 amI expected the OP to be stable after isolating the output. I'm still scratching my head as to why it isn't. Stable atunity2x gain with 2 x 10K but oscillating at 1.4x gain still makes no sense to me.I have added extra decoupling at the supply rails and that makes a noticeable different to the supplies, but no change to the oscillation.Quote from: Kleinstein on July 22, 2021, 07:06:43 amMy plan was to get the 10V OP stable and then remove the 3u3 and the 220pF from the circuit and test. Then perhaps add 100 Ohms and 1nF at the ADC end. I've not got far down that path

author: MiDi
author_rank: Frequent Contributor
timestamp: July 22, 2021, 09:17:57 pm
content: Divider of Out-10k-NFB-10k-Gnd gives gain of 2, Out-10k-NFB-25k-Gnd gives gain of 1.4.The more gain, the more phase margin the op has.The more capacitance at the output, the more phase margin the op has.If I got you right, this is the behaviour shown.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 22, 2021, 10:14:43 pm
content: Quote from: MiDi on July 22, 2021, 09:17:57 pmYes, 2x and not unity. My errorI have progress, of sorts.Take the OP177, S102 and 10nF off the main board and place them on a separate PCB and the oscillation completely vanishes.Could the PCB layout itself cause the oscillation?Here are the spikes at the ADC input of 10VREF into the MAX312 switch. All capacitance on the output removed and also no 220pF across the OP inputs.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 23, 2021, 09:12:55 am
content: The OP177 is not really fast and usually not prone o oscillation even with a really poor layout / breadboard.A weakness of essentially all slow OPs is the PSRR for the negative side. So negative side decoupling is often more important than positive side.It is rather difficult to get a layout so poor that it oscillates with such a slow OP. It can happen with some hidden capacitive load ( > 1 nF) and maybe extra gain from following stages. So if the OP27 based buffers at the output of the amplifier get instable an oscillate, this may effect the OP177. Similar there could be oscillation already with the reference circuit.The 10 K (1 mA) load from the inverting part is usually more like a good thing for the first stage.The spikes without any capacitance are quite large. It is not such a surprise as the OP177 is rather slow (and thus high closed loop output impedance) and the max312 switches have quite some charge injection (~ 50 pC at +-10 V). To at least limit the hight of the spike one could have a capacitor with a resistor in series. The peak would be smaller, though longer. In theory one could have the 2 unused switches of the max313 to switch opposite polarity to compensate some of the charge pulse and also the average current with a resistor (some 100 K) to ground.Besides the charge injection there is also the capacitance at resistors.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 23, 2021, 04:51:25 pm
content: Quote from: Kleinstein on July 23, 2021, 09:12:55 amThe reference is stable and quiet. The 10VREFBUF and both of the negative OPs showed only a very small amount of the oscillation they were seeing from the 10V input.Edit: The charge injection comment has me wondering if it is worth changing the max312 to something else? A different quad switch or individual FETs?The main PCB layout is attached, along with the daughter board that removes the oscillation.(The PCB is nasty with flux. I know, I know, but I was only cleaning the DIP area between IC swaps.)Would the PSRR of the negative rail be mitigated somewhat by having a single supply 0-15V for the OP instead of the +/-15V dual?Quote from: Kleinstein on July 23, 2021, 09:12:55 amThose spikes were visible in the DMM measurements, it made them extremely jumpy. Placing a 100 Ohm in series with the 10V ref and either a 1nF or a 10nF film after the new resistor to REFGND reduces the spikes and returns the DMM readings to normal.Edit: Your charge injection comment has me wondering if changing the max 312 to another part, or individual FETs would be beneficial?

author: Kleinstein
author_rank: Super Contributor
timestamp: July 23, 2021, 09:31:05 pm
content: Lower resistance switches have more charge injection. In this respect the max312 is not that bad - this is just the level of charge injection one has to live with, for R_on in the 10 Ohms range. I know no more suitable replacement. Using idividual fets like in the Solartron or the new KS 3446x is quite some effort and it is not sure they are actually better. The supply to the max312 /313 needs good decoupling. Using a second part of switches for an invertes signal could be worth it. It would compensate much of the spikes and the overall reference current would be independent from the modulation, with always one resistor active. Using a 0 and 15 V supply could help a little, like good decoupling. The difference to a more normal +-15 V supply would not be very large, unless the supply has a low of crap signal. It still help reducing the heat.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 24, 2021, 01:37:11 am
content: Quote from: Kleinstein on July 23, 2021, 09:31:05 pmI am adding decoupling to the two max ICs.In the attached circuit part I have connected the unused part of the max313 to switch the opposite reference polarity to that being used by the integrator to ref ground via another 100K resistor. Is this what you had in mind by switching an inverted signal?Quote from: Kleinstein on July 23, 2021, 09:31:05 pmThe -15V rail is noisy, but not too bad. Heat might be a thing to worry about if the reference and buffers are moved to the ADC board.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 24, 2021, 05:44:18 am
content: The inverted switching looks like I suggested. The capacitors in parallel to the 100 ohms resistors likely don't help.If heat is a problem and with a new PCB, one could replace the OP177 with a lower power (and lower noise) OPA207, OPA202 or ADA4077. These are also a little faster and may thus settle faster. For the inverter part an AZ OP like LTC2057 / OPA189 could be worth considering.The reference buffers for the forcing signal would also use lower power chips than the OP27. Here DC precision is less critical.The old PCB show a series resistor to the LTZ1000 ref. This is good and could be used for some low pass fitlering (have a capacitor of a few µC to ground). The 200 Hz range noise from the reference would add to the ADC noise (not much compared to this ADC, but still avoidable).

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 25, 2021, 05:42:25 am
content: Quote from: Kleinstein on July 24, 2021, 05:44:18 amCapacitors removed.Attached is the comparator section of the ADC as it stands with IC1 changed, the slope amplifier in place, added decoupling and the multiple options for the front end resistors.Anything broken or need changing?Quote from: Kleinstein on July 24, 2021, 05:44:18 amThe case of the 8081 gets toasty, some 13C above ambient most of the time. The mains transformers run very warm and are the main cause of the case temperature. I'm not too concerned about physical IC temperatures but localised heating of the ADC PCB.Quote from: Kleinstein on July 24, 2021, 05:44:18 amI'll add pads for low pass here if/when I move the reference parts to the ADC board.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 25, 2021, 09:21:26 am
content: Most of the circuit looks sensible. The +-2.5 V supply should have more 200 Ohms - the TL431 would not be happy with so much current. One could consider to use additional resisistrs for the choice of input voltage (5 V or 15 V) instead of the suggested solder bridges.The comparator switch level, especially for the upper LM311 may want an adjustment. So not the 100 K to pin3, but pin 3 to ground. Because of the gain in front the levels may be better a bit more separated. So maybe something like 1 K or 2.2 K and 100 K for the dividers. One would not need the same separation, as in the original, as much of the separation was likely just there to make sure the offsets of the LM311 do not cause trouble. It still helps if the integrator has reasonable settled in the time in between. Still the linear range of the slope amplifier is limtied.Saving on the power makes sense if easy, like using lower power, more modern OPs (e.g. an OPA209 instead of the OP27).

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 25, 2021, 04:08:52 pm
content: Quote from: Kleinstein on July 25, 2021, 09:21:26 amThe datasheet suggests operating range between 1 - 100mA. I thought the 200 Ohms was a reasonable starting point.I'll increase the 200 Ohm to 510 Ohm. 5mA @ 5V and 25mA @ 15V. If I chose to stick with the 15V supply I can change the 510 out for 2k4.Quote from: Kleinstein on July 25, 2021, 09:21:26 amI've added a resistor to create a new divider for IC3 pin 3. I've used the isolated GND that IC4 uses for its divider.Two questions came to mind when tweaking this part.1) Do both IC3 and IC4 dividers require sub 15ppm TCR resistors to keep them reasonably stable?2) Would a trimmer potentiometer be of any use for these dividers to allow adjustment?Quote from: Kleinstein on July 25, 2021, 09:21:26 amDone. OPA209 are slightly lower cost that OP27 too

author: Kleinstein
author_rank: Super Contributor
timestamp: July 25, 2021, 04:55:33 pm
content: The TL431 should operate with some 1-2 mA. More is only produching extra heat. The AD8628 take up to 1 mA ( a little less typical, and not significant load), so something like 1 K from the 5 V supply or some 5.6 K maybe 4.7 K from the 15 V would be suitable.The dividers for the lm311 trigger level don't need to be very stable - normal 100 ppm/K resistors are good enough. This also applies to the slope amplifier. The OPA209 is slight over-kill (but also low power) there, a NE5534 could be sufficient too (but needs a compensation cap). Only the drift over the time of a single conversion would matter. I would still connect pin3 of IC3 directly to ground and do the divider at pin 2. So the 680 ohms (maybe change to 1 K) and than 100 K to +15 V. With 1 K and 100 K on each side the trigger levels would be at some +-150 mV or some +-20 mV before the amplification. With a slope of some 3 mV (mainly from the forcing signal) per µs, this would be length of some 6 µs for the phase with no reference active. This should be long enough for settling at the integrator. Up to about twice the separation would be possible.There is no need for a fine trim - if at all it would be more like exchanging the resistors in large steps (e.g. 1 K or 2.2 K). I would not expect much of a difference. A very large gap with IC3 essentially at 15 V looks more like a problem to me and the 100 K add quite some noise. I consider this more like an unnoticed mistake.Which ground to use for the LM311 trigger levels and the slope amplifier is a good question. Chances are it should be the same ground.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 25, 2021, 05:31:30 pm
content: Quote from: Kleinstein on July 25, 2021, 04:55:33 pmI've changed the TL431 resistors to 1k.Quote from: Kleinstein on July 25, 2021, 04:55:33 pmThanks for that reasoning. I've amended the divider accordingly.I noticed that in the Solartron 7081 the negative rail for the high speed parts of the comparator and both LM311s are lifted by a 68 Ohm resistor.Does that add anything useful to the circuit?Quote from: Kleinstein on July 25, 2021, 04:55:33 pmSlope amplifier GND amended.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 25, 2021, 06:57:02 pm
content: The resistors ins the negative supply isolate the supply, like already done with the max312 switches and some OPs. I don't think the 68 Ohms in the Solatron are about reducing the supply voltage, more about reducing possible interference as a possible source of INL errors. It may be a bit overkill to have most parts separated, but with SMD parts this may not be such a bad idea, even if the resistors and capacitors are smaller. The nasty parts are the high frequencies (e.g. > 100 MHz) from fast swtiching that are hard to control. Here just a MLCC at every chip may not be enough, as there can be CLC resonances with the trace-inductance. Spooky RF is nothing I like in a precision circuit.I would consider a comon pair of resistors for both LM311 could be enough, as they don't switch together. I would more consider them as source than targets of interference.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 25, 2021, 10:46:22 pm
content: Quote from: Kleinstein on July 25, 2021, 06:57:02 pmWith everything except the LT5400, AD8628 and OPA209 I can go with through hole parts. The only thing I have seen producing any kind of high frequency noise so far is the PLL LM311 ringing a little at the 50Hz zero crossing. The noise seemed localised and I have that isolated from the supply too.Quote from: Kleinstein on July 25, 2021, 06:57:02 pmI think that's the new comparator mk1 circuit readyTime to measure the existing mounts and connectors and see how layout goes.The original PCB has the two metal cans over most of the components, along with that annoying potting compoundWas there really a need to have two cans to separate the micros from the analogue side? I haven't noticed any ill effect running with the shield removed from the micro side of the board. Solartron didn't even bother with full shielding, just a copper clad cover over the ADC area.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 26, 2021, 06:15:06 am
content: With the LM311 for the 50 Hz signal there should be no ringing at the output. The supply should have isolating resistors if needed. At least the extra signal would be mains synchronous and thus suppressed quite well.The PLL should definitely have a clean supply.The can for the µC is a little odd - there are plenty other µCs and possibly EMI sources in the DMM. Also with no realy filtering in the supply the cans are not very tight. As far as I can see the PLL was outside the cans. So chances are the can around the µCs is not really needed. Improved decoupling / supply filtering is likely more effective.The can around the integrator has a dual effect. One is a little EMI reduction - again without porper filtering the supply not very effective. The other is to improve thermal stability for the integrator and switches. I still don't think the can is really needed. With an AZ OP the integrator would not be that sensitive. The more sensitive part would be the reference amplification.For many parts I see no real advantages with THT parts. SMD resistors are much easier to exchange if needed. 0805 size are still reasonable readable and easy to solder. The film capacitors kind of need to be THT. Combined THT and SMD can be a bit tricky: the THT parts can block the access to soldering the SMD parts. So it helps if the SMD parts are on the bottom.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 26, 2021, 06:41:57 pm
content: Quote from: Kleinstein on July 26, 2021, 06:15:06 amI saw ringing at the output on both the rise and fall of the square wave, and some noise on the ZC at the input.Just checked again and it's quiet. I think I screen captured the earlier ringing. If I can locate the captured images I'll post them.I experimented with isolating the PLL supply and lowering the voltage. With the I2C lines from the 18F252 now being higher they introduce significant noise to PLL as pulses on the supply. Is it OK inserted resistors into the I2C lines to mitigate this? Not sure I want to lower the supply to the timing PIC.Quote from: Kleinstein on July 26, 2021, 06:15:06 amI have my suspicions that the cans on the ADC has a lot to do with obfuscation.I'll experiment and see what effect running without cans has.The most significant EMI output is directly under the ADC PCB. The 10MHz clock that is used to output a PPS trigger for the main micro.The oscillator itself isn't that bad, but on my revision the supply resistor (R119 10R) is cut and a pair of wires tun to a internal/external 10MHz switch. These wires hoot quite a signal. I'm thinking of switching the oscillator supply with a FET rather than have the supply running to the switch and back.It's a same the 10MHz is on the unguarded size of DMM. It could be used to clock everything on the ADC otherwise.Quote from: Kleinstein on July 26, 2021, 06:15:06 amMounting the SMD parts on the underside of this PCB isn't something I'd considered. I'll bear it in mind though whilst I'm laying it out.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 26, 2021, 07:02:50 pm
content: I2C uses open drain/collector outputs and pull-up resistors. It would be OK to lower the voltage with an additional resistor (likely 20-50 K range, depends on the pull ups installed) from the signals to ground. Something like 3.5 - 4 V should be OK for the PIC and other 5 V chips to be safely recognized as high.A 10 MHz signal running all over with lose wires sounds like an EMI nightmare. I would still be more worried about the supply / ground, not so much simple capacitive coupling. The supply still should be clean - so local decouling and a resistor in the wire to the switch.If the 50 Hz signal is now clean, all is fine. It could have been a poor ground / supply.A agree, obfuscation could be a reason for the can and potting. The 100 K at pin3 of IC3 need a kind of cover up.

author: rigrunner
author_rank: Frequent Contributor
timestamp: July 26, 2021, 07:21:48 pm
content: Quote from: Kleinstein on July 26, 2021, 07:02:50 pmI'll test with a few values to see how it runs.Quote from: Kleinstein on July 26, 2021, 07:02:50 pmIt's quite a sloppy implementation. The wires to the switch aren't shielded, nor are they twisted.I forgot to add the image to my previous post.Red and Blue wires are supply to the oscillator via the switch.Coax is 10MHz in from rear.Black and Red are the reference in to the ADC - they don't usually dress in this place, but they do run close by.Quote from: Kleinstein on July 26, 2021, 07:02:50 pmvery true.

author: rigrunner
author_rank: Frequent Contributor
timestamp: August 04, 2021, 10:16:43 pm
content: Quote from: Kleinstein on July 26, 2021, 07:02:50 pmIt would seem the joke is on mePulling R5 to test with a different value revealed a joining trace to IC4_divider_GND. The 100K resistor doesn't look silly now. It's used to offset the negative voltage on IC4_divider_GND from R5+R11.

author: rigrunner
author_rank: Frequent Contributor
timestamp: October 22, 2021, 03:47:59 pm
content: I was asked if I did re-spin the ADC board in the 8081?It is still a work in progress but I did indeed create a new PCB and it does work, mostly...With the main clock at 10MHz all the measurements are x1.6. I'll need to do something with the firmware in the 4620 pic to fix that.The CS2000 is now outputting 12.5MHz rather than 6.25MHz, so although I have jumpers in place to swap between clocks that's broken.The pics are using the original firmware so I don't see why the CS2000 is being programmed differently. Something else to sort out.Only one bodge wire needed to get the new board running. I wired the negative supply on the 50Hz LM311 to 0V when it should have gone to -5V.To try and resolve the oscillations I had I also made a daughter board for the +/- 10V refs. Board works perfectly wired up outside the 8081, but oscillates when installed.Picture of the new ADC board attached (jumper wire over slope amp for testing).