FPGA Cost Model Help Please! - Page 1
Forum section: electronics / general

author: fgt4w
author_rank: Newbie
timestamp: September 13, 2013, 09:12:37 pm
content: Hi Everyone,I'm quite new to FPGA development, and I was hoping you guys could help me out. I've been given a project to take an old ASIC development/production cost model, and adapt it to estimate FPGA costs. I've done some basic research, but I still have many questions.1. My first main issue is how to measure "size" of a design. The ASIC model uses number of gates. From what I've read, active logic cells is the sizing metric used in the FPGA community, and there is no perfect formula to convert active logic cells to gates. I don't need a "perfect" solution - i need a pretty good solution that gets me in the ballpark. Are there some rules of thumb I could use to compare ASIC and FPGA design sizes? I also read that the 'size' of an active logic cell can vary from vendor to vendor. Maybe I need to find a conversion factor for each vendor? Anything to steer me in the right direction is appreciated.2. Generally speaking, what is the development cost difference between an FPGA project and a standard cell ASIC project of the same 'size'? How much of this cost difference is due to a difference in scope (activities that must be performed for ASIC projects, but not for FPGAs. example: mask set generation) and how much is due to a difference in complexity (difficulty of implementing the same thing in a normal ASIC CAD tool vs. a normal FPGA CAD tool.)3. I would guess that anyone using a high-level cost model like this could easily get a vendor quote for FPGA purchase prices, so I wasn't going to build anything to estimate it as its already known. Is this the right approach?4. I've covered the purchase price, the design phase effort, downloading it to the FPGA and testing it. Am I missing any other significant costs?Thanks so much for any help you can offer!

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 12:16:46 pm
content: Now wherehave I read this before.Basically, what ads-ee said.

author: free_electron
author_rank: Super Contributor
timestamp: September 14, 2013, 01:41:41 pm
content: Much is going to depend on the technology used.A maskset for 22nM is an order of magnitude pricier than one for 0.5u ...As fpgas these days are all run in the deep nanometer field you d have to compare apples to apples.That being said : are we talking about real asic ? Or a sea of gates implementation ?There are companies that can do fpga to gate array reasonably cheap. Even altera offers that serive. Others are quicklogic.Above a certain volume the nre is easily written off and the parts are much cheaper than continuing with fpga's

author: fgt4w
author_rank: Newbie
timestamp: September 17, 2013, 03:33:17 pm
content: Thanks for your replies.Yes, the minimum feature size is a major cost driver in this cost model. It already estimates many different kinds of ASICs, sea of gates, standard cell, semi-custom, full-custom, as well as hybrids. I'm simply trying to find the best way to add options so that it estimates FPGAs too. And the biggest issue i'm running into is that Number of Gates is a major input, but everyone seems to say Gates won't work for sizing an FPGA design - they say Active Logic Cells is the best metric. It also seems that, according to the other thread mrflibble linked, that Active Logic Cells is a terrible sizing metric, which is basically why it cannot be converted to Gates.The model is intended to be used at a very early stage in the project - before you ever sit down with a CAD tool. The number of gates are being estimated by the eventual designers, and they are estimating this gate count from requirements documents and things like that. Why does it seem that people can estimate gate counts from an early design phase based on requirements documents, but if I suddenly switch and say "we want this design in an FPGA, not an ASIC..." now its impossible for anyone to estimate the size in a way thats comparable to number of gates?Thanks for any help you can offer.

author: marshallh
author_rank: Unknown
timestamp: September 17, 2013, 03:44:30 pm
content: Here's some numbers for you I pulled from a fairly complex IP core:So here's a very ballpark-type estimate:1 Altera ALM (Stratix, Arria) = 9.7 gates1 Altera LE (Cyclone, MAX) = 5.22 gates1 Xilinx slice (Virtex) = 19.7 gatesKeep in mind the fpga numbers will vary by up to 10-20% depending on fitment settings used, optimization, even different versions of the vendor tools will affect the number, etc.

author: fgt4w
author_rank: Newbie
timestamp: September 20, 2013, 07:02:49 pm
content: Thanks marshallh, that looks like some really useful stuff, if only I was more knowledgeable.Just to give you an idea of my level of understanding - I had to look up what an IP core is, what Slices are, Fmax, CLK/PCLK, etc. Now I'm much closer to understanding your post, though.Here's my best guess/interpretation of what you did - please correct me if i'm wrong (and i know i'm wrong):You took an IP soft core (basically some HDL code), and synthesized it with tools for each of the 9 devices listed in your table. The table data are outputs from the synthesis tools. The ASIC tools gave you a gate count, and ... clock speed info. is 100 MHz the speed required for the design to work? and 125 is the maximum supported by the tool? or is there another way to interpret those numbers? The FPGA tools gave you metrics on how many LE/ALUT/Slices will be utilized, how many memory bits and IO pins will be utilized. I'm not sure what the DSP/MULT means or if its relevant. Same for Quartus, BRAM, special features, and ISE. But somehow, you took all that information and converted it to gates? perhaps you could explain how you used the numbers in the table to come up with a gate count estimate?Thanks for helping a newb out - I really appreciate it. I'd be screwed without you awesome people guiding me through this

author: free_electron
author_rank: Super Contributor
timestamp: September 20, 2013, 07:38:10 pm
content: This sounds to me like you have been given a project that is way over your head.Your manager is an idiot. He should not assign such an important task to you if you don't have any experience with FPGA , nor ASICs (since you don't even know what an IP core is let alone a multiplier o look up table, or a slice you obviously have no experience designing integrated circuits... have you ever made a digital design ? you are waaaaay out of your comfort zone here.)Do yourself a favor ( honestly , i am saying this to protect you from being finger pointed at later in time ) and tell your manager that this needs to be looked at by someone with experience in the field. Someone who has done a bunch of ASIC or gate array designs and prototyped them on FPGA's. Such a person would be able to give you a good feedback.Every FPGA family is different. every design is different. a design that fits poorly in one fpga may fit very well in another fpga family. Only a seasoned designer with experience in the field will have a feel for what can and cannot be done. the answer is not a hard line, it is a scatter plot. some designs lean one way, some the other.Honestly, protect yourself. If you deliver a report and it turns out to be way off because you lack the experience they will put the blame on you. Better be up front.

author: marshallh
author_rank: Unknown
timestamp: September 20, 2013, 07:49:51 pm
content: "100/125mhz clk/pclk" means that there are 2 clock domains in the design -i.e. part of the design is clocked at 100mhz, and part at 125mhz.PCLK is the clock generated by the usb3 clock recovery circuitry. Don't worry about that.Fmax generally refers to the maximum frequency you could clock a certain blob of logic at, before it starts failing. I'm not sure why CAST decided to use it for the internal clock. It's usually something the fitter tool generates telling you how much margin you have left.BRAM/Memory bits are the same thing, vendors quantify them differently. It's like L1 cache memory in CPUs, very fast, expensive, and smallDSP/M14k/Multiplier blocks are hardware multiplers, MACs, etc.Each vendor has their own FPGA architecture that's slightly different and theres no standardization.I got the average gate counts by taking the 95000 ASIC gates of the reference implementation and dividing by the number of vendor-specific logic blocks in each type of FPGA.After a while of seeing these numbers you can just grab numbers out of your posterior and usually be right.So to have a "gate count" number and figure out how big of an fpga you need, it depends mostly on:1. FPGA FamilyAltera: Stratix, Cyclone, Arria,Xilinx: Virtex/Kintex, Spartan/Artix (new 7 series parts are the *tix names)2. Other IP inside the fpgaThe more stuff you put inside, the worse routing gets. You may have a bunch of logic elements or slices but lots of the time, you run out of interconnects! The result is you fall off the edge of a knee curve with regards to your Fmax I mentioned earlier. Very easily a crowded FPGA will not be able to meet timing requirements. The solution is to use a 15%-20% bigger device than you actually need.