deriving three clock freqs from one, 1980's style - Page 1
Forum section: electronics / beginners

author: Pugbutt
author_rank: Contributor
timestamp: February 14, 2022, 08:08:34 pm
content: Hi Guys,I have a retrocomputing project that requires three synchronous clocks, and I'm hoping for guidance coming up with a solution that is 1980's period correct and low parts-count.Code:F0 = 315/88 MHz= 3.5795455 MHzF1 = F0 * 6= 21.4772727 MhzF2 = F0 * 4= 14.3181818 MHzIs using a 42.96 MHz master clock with integer clock division the best way, or does a more elegant method stand out? (I really need two 3.58MHz clocks, 90 degrees out of phase, if that changes things.)Thanks,Craig

author: Benta
author_rank: Super Contributor
timestamp: February 14, 2022, 09:43:30 pm
content: Here's an example of a 1980s design:

author: Pugbutt
author_rank: Contributor
timestamp: February 15, 2022, 03:11:54 pm
content: Thanks! Two flip-flops, a gate, and a 14.318 MHz master clock gets me 3/4 of the needed clocks, and it's clearly legit. Would a 1980's HW guy use a x6 PLL to generate that 21.48 MHz clock?Thanks!

author: Yansi
author_rank: Super Contributor
timestamp: February 15, 2022, 03:29:40 pm
content: With two D-flops, it can be done also (probably more common to find a 7474 instead of 7473 these days).The circuit can make full 0/90/180/270 signals. And no XOR gate required.Output clock is of course input divided by 4.

author: Ian.M
author_rank: Super Contributor
timestamp: February 15, 2022, 05:03:46 pm
content: You can get 21.4772727 MHz crystals off the shelf. ~43 MHz ones are vanishingly rare.Here's an '80s style lineup:21.4772727 MHz Pierce oscillator (F1) => delay + XOR frequency doubler (gives ~43 MHz)=> Divide by 3 (50% duty cycle) (gives F2) => divide by 4 (gives F0). Use Yansi's twisted ring if you need quadrature F0'Of course, it depends how much jitter you can tolerate on the F2 edges which is dependent on the oscillator duty cycle and how close to 50% duty cycle the doubler duty cycle is given an exact 50% input, and how close to coincident matching edges of F0, F1 and F2 have to be. Worst case you may have to PLL up to ~86 MHz so you can use fully synchronous dividers clocked on a single master clock edge, but that would have a distinctly late 80's / early90's flavor.

author: Benta
author_rank: Super Contributor
timestamp: February 15, 2022, 05:29:59 pm
content: Quote from: Pugbutt on February 15, 2022, 03:11:54 pmI don't understand. You said that the end result should be a quadrature 3.58 MHz signal. Why do you need the other clocks?

author: Benta
author_rank: Super Contributor
timestamp: February 15, 2022, 05:31:16 pm
content: Quote from: Yansi on February 15, 2022, 03:29:40 pm@Yansi: nice one. I hadn't thought of that option

author: Pugbutt
author_rank: Contributor
timestamp: February 15, 2022, 10:33:21 pm
content: Thanks for taking the time to help, and sorry Benta, the original post wasn't very clear. There's an HD63C09EP needing the 358 MHz two-phase clock, the 14.318 is a YM262 sound chip, and the 21MHz is a V9958 video chip. I really should do my due diligence to understand the way these are to interact before asking for too much help. Thanks again,Craig

author: basinstreetdesign
author_rank: Frequent Contributor
timestamp: February 16, 2022, 05:36:09 am
content: Quote from: Yansi on February 15, 2022, 03:29:40 pmYep: +1

author: m k
author_rank: Super Contributor
timestamp: February 16, 2022, 12:21:33 pm
content: Quote from: Pugbutt on February 15, 2022, 10:33:21 pmVideo is independent so synced clock is not needed.Chip manual is also indicating it.

author: Pugbutt
author_rank: Contributor
timestamp: February 19, 2022, 01:45:49 am
content: Quote from: m k on February 16, 2022, 12:21:33 pmThank you, that's good to know. Will try that first on the prototype.