Gates propagation delay issue - Page 1
Forum section: electronics / beginners

author: Saimoun
author_rank: Frequent Contributor
timestamp: November 28, 2023, 01:00:26 pm
content: HiI am doing some testing in LTSpice, I downloaded a model for the 74HC gates.I have two signals, called "DATA1" and "DATA2", as well as a "SWITCH" signal, which must determine if the output should be DATA1 or DATA2.I have sorted this out with gates:Code:OUT = (DATA1 && !SWITCH) || (SWITCH && DATA2)So far so good - it works. My problem is that when the SWITCH signal is going high to low, because of the little propagation delay, I get a very short pulse on the output. See the attached circuit, as well as the simlation results (note that in the simulation DATA1 and DATA2 are not moving, constantly high).Do you guys have any suggestions?Thank you

author: Ian.M
author_rank: Super Contributor
timestamp: November 28, 2023, 01:56:28 pm
content: Race Conditions are one of the major hazards in asynchronous logic designs. Sometimes they don't matter - e.g. if an intermediate signal can glitch but before it reaches the output, is sampled by synchronous logic with a clock edge sufficiently far from the glitch that it doesn't violate its setup and hold times, or if the glitch is short enough not to matter for the circuit it is driving - but you frequently need to mitigate them.Seehttps://en.wikipedia.org/wiki/Race_conditionandhttps://en.wikipedia.org/wiki/Karnaugh_mapwhich has some suggestions on avoiding them.If you just need to shorten the glitch, roughly balancing the propagation delays may help. e.g. use an XOR gate for the inverter to generate /SWITCH and another XOR in the same package as a non-inverting buffer for SWITCH so there is less skew between them when they reach the NAND gatesIf you need to eliminate the glitch you'll need to add a term to the logic equation to 'bridge' the transition between the two minterms. i.e.Code:OUT = (DATA1 && !SWITCH) || (DATA2 && SWITCH) || (DATA1 && DATA2);

author: CaptDon
author_rank: Super Contributor
timestamp: November 28, 2023, 03:12:47 pm
content: Why not just use the 'quad 1 of 2 data selector' 74157 or any of the variants HC ACT etc. Look at the entire '150' series and you will find 1 of 8, 1 of 16, dual 1 of 4. Very handy without all the distributed logic which will indeed cause race condition problems.

author: Tation
author_rank: Regular Contributor
timestamp: November 28, 2023, 11:22:19 pm
content: What you have found is called a "hazard". They come in 3 varities: static, dynamic and functional hazards, being yours a static hazard. There are many sites describing them.There are some ways to design logic free from static hazards. If all static hazards are prevented, then there will not be dynamic ones, but functional hazards are not easily removed.Registering the outputs and synchronizing the inputs is a general mechanism solving all hazard related issues.

author: Benta
author_rank: Super Contributor
timestamp: November 28, 2023, 11:38:01 pm
content: Yep, the 74HC157 will do the job without problems. Much simpler.

author: Saimoun
author_rank: Frequent Contributor
timestamp: November 30, 2023, 04:49:04 pm
content: Thank you all for the very helpful answers, and thank you Ian for the thorough explanation!It sounds like the 74HC157 is perfect, and testing it in LT spice I do not get the glitch (makes sense since the IC is designed for it).What sucks is with my previous design (with the glitch), I used exactly 6 inverters and 4 nand gates, which fit 2 SOP packages perfectly... Now I have 1 unused inverter, 3 unused gates, and another big SOP package (the 74HC157) with 4 multiplexers even though I only use one... Does not matter much, it just feels like a lot of wasted space and pins

author: Ian.M
author_rank: Super Contributor
timestamp: November 30, 2023, 05:45:45 pm
content: Use a 74LVC1G157 single mux and a 74LVC1G00 single NAND, keep your existing hex inverter and you'll only have one inverter spare, and probably save board area.

author: Saimoun
author_rank: Frequent Contributor
timestamp: December 02, 2023, 03:15:10 pm
content: Quote from: Ian.M on November 30, 2023, 05:45:45 pmAwesome! Silly me who did not find any single package int he 74HC family, I did not think about looking into other families (I'm not very familiar with the gates family yet).I actually realized I could re-arrange the circuit with only 3 inverters and one nand gate, so I'll get a 74HC132 package (quad NAND gates with Schmitt trigger inputs), wiring 3 of them as inverters (grouping the inputs).I'll assume I won't run into any issues by combining inputs/outputs of the two different families (HC and LVC)?Thanks

author: Ian.M
author_rank: Super Contributor
timestamp: December 02, 2023, 04:17:02 pm
content: You shouldn't run into any issues mixing 74HC and 74LVC on the same board at 5V Vcc, but be aware that LVC is about two times faster than HC.Do check your rearrangement doesn't expose any other hazards!

author: Saimoun
author_rank: Frequent Contributor
timestamp: December 02, 2023, 04:41:21 pm
content: Thanks for the reply - the circuit runs at 3.3V though.And good idea I'll double-check for potential hazards, thanks to you guys I have plenty reading about it

author: Ian.M
author_rank: Super Contributor
timestamp: December 02, 2023, 07:28:34 pm
content: 3.3V is fine for LVC. My point was only that in spite of the 'LV' (which stands for Low Voltage), the 74LVC1G (and 2G) series are rated for 5V operation with 5V logic compatible thresholds at 5V Vcc.

author: NDani
author_rank: Contributor
timestamp: October 10, 2025, 12:49:39 pm
content: Hi all!Can anyone confirm by experience that the 74HC157 (or any equivalent from another logic family) does not suffer from the static hazard problem mentioned above? Looking at the functional block diagram at the front page of the TI datasheet (https://www.ti.com/lit/gpn/sn74hc157), it seems like the extra minterm to eliminate static hazard is not present. If the circuit is indeed hazard-free, does anyone know how that is achieved and how reliable it is e.g. over temperature? I see no mention in the datasheet that hazard-free behavior is granted.

author: rstofer
author_rank: Super Contributor
timestamp: October 10, 2025, 03:26:29 pm
content: According to Google AI, there is still a potential race condition with the 74LS157 and I suspect it is present with all the other families. Google for 'potential race condition in 74ls157'. If you expand the result, there is a section on how to work around it.I really like the Google AI thing.In the world of FPGAs, we would put 2 D flops in series with the inputs to synchronize them with the logic (2 clock delay) and a D flop on the output to get rid of glitches (1 clock delay). Synchronous logic is the way to go when gltches are a consideration.