PCB : route VCC to multiple ICs - Page 1
Forum section: electronics / beginners

author: claudiux
author_rank: Newbie
timestamp: July 09, 2018, 05:11:53 am
content: Hello,I am trying to build my first PCB. It has 8 ICs on it and I wonder what is the best way to route the VCC to the ICs.I attached some examples . Thanks for tour advices.Claude

author: Chriss
author_rank: Frequent Contributor
timestamp: July 09, 2018, 05:27:49 am
content: I would prefer the 1. & 4. trace. Depending on how much current your ic's consuming. ..Sent from my GT-I8260 using Tapatalk

author: forrestc
author_rank: Unknown
timestamp: July 09, 2018, 05:43:13 am
content: Quote from: claudiux on July 09, 2018, 05:11:53 amMy preference is to us a fill the top layer entirely with Vcc and flood the bottom layer with ground. Vcc and Ground will then flow 'around' all of your signal traces. You will occasionally run into problems doing this, but generally for most low-frequency designs this works well.Of the ones you showed, I agree with others: avoid the 2nd one, the others are fine.

author: JS
author_rank: Frequent Contributor
timestamp: July 09, 2018, 08:06:36 am
content: I'd probably go with 1 in a dual layer design, 4 could be ok for a multilayer board but with dual sided you won't be able to route half the pins of your ICs.I even go with Vcc all over the place, just taking care it goes to the bypass cap and from there to the ic and die there for each ic, just to be able to route sensitive signals in a better way.JS

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 09, 2018, 02:22:19 pm
content: 2-layer PCB? That basically rules out the last one (which would otherwise be the best).So many capacitors, doesn't matter. One cap can be shared between two adjacent ICs, no problem. Maybe more.PDN (power distribution network) analysis can be done to see how much it matters. Typical results say: the distances between ICs and caps should be under 10cm, for the kind of logic beginners would be using (CD4000, 74HC families).Tim

author: TimNJ
author_rank: Super Contributor
timestamp: July 09, 2018, 10:35:13 pm
content: Quote from: T3sl4co1l on July 09, 2018, 02:22:19 pmOn that note, are those all electrolytic caps? For capacitors used in bypass applications, you want to use a cap with a low-impedance at high frequencies. Low(ish) value MLCCs are generally a good pick.Also, if you have a ton of capacitance hooked up to your supply rail, you can (perhaps) cause the voltage regulator to go unstable. On top of that, lots of capacitance means large inrush current on startup.With only 8 ICs, I don't think you will run into the last two issues, but if you had 80 ICs, maybe different story.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 09, 2018, 11:42:13 pm
content: Yeah, if those are electrolytics, all the more reason -- electrolytics are "slow", so it isn't very meaningful to have them spaced so tightly. Best use is to put one at the input, and one at the far end, of a chain of supply connections. Ceramic capacitors are then used at every link in the chain (however often that might be, see above).Tim

author: Muny
author_rank: Contributor
timestamp: July 10, 2018, 12:55:52 am
content: Quote from: blueskull on July 09, 2018, 05:15:15 amQuote from: forrestc on July 09, 2018, 05:43:13 amI'm just curious, what's so horribly wrong with the 2nd one?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 10, 2018, 02:46:46 am
content: Quote from: blueskull on July 10, 2018, 01:02:25 amCitation neededTim

author: forrestc
author_rank: Unknown
timestamp: July 10, 2018, 02:54:58 am
content: Quote from: Muny on July 10, 2018, 12:55:52 amGenerally you want to create a bus, and then tap off of it, with the signal going from the bus to the bypass capacitor to the part. Ideally your ground would do the same thing. The capacitor will act as a small energy source for each part, which both ensures the part has enough power during switching events and also helps prevent the noise from the part getting on the bus. This is somewhat oversimplified, but it's a good way to think about it.Between options 1 and 3, 1 is probably better.I like 4, or my equivalent of it (just flood the entire unused area of the top of the board with VCC, bottom with GND) because it typically creates an even lower impedance source of power and in higher speed designs helps to provide a low-impedance signal return path. Usually you can move traces and/or parts around such that the pours are contiguous and you don't have to separately route VCC or ground. Like I mentioned, though, this can cause more problems if you aren't careful. For most low speed designs as a beginner doing #1 is probably better.

author: forrestc
author_rank: Unknown
timestamp: July 10, 2018, 03:16:46 am
content: Quote from: T3sl4co1l on July 10, 2018, 02:46:46 amHis statement is definitely good for Power integrity 101. In the 2nd year course you learn that that rule of thumb can be ignored if you understand what you're doing. There are lots and lots of studies out there which have tried different ways to decouple, with varying results. But if you're not prepared to jump into the full understanding of what is going on (and you're working with lower speed designs), it's safest to just run from vcc/ground through the cap and to the device. Most of the time you'll find that even if you know what you're doing, running from vcc/ground through the cap to the device is actually safest. Especially on 2 layer boards.I was looking for a couple of documents I have somewhere with details on this, but don't seem to be able to find them.... I do know that TI and others have high speed design appnotes which cover this and others.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 10, 2018, 03:47:30 am
content: "General rules for placing capacitors"That, and no justification given. The plots just above are nice, but at a glance, don't seem to be connected to a specific layout. (Adequate justification requires high level math, which yes, is well beyond beginner scope.)The comment about "signal flow" is particularly jarring -- signals don't flow one way along a passive component, they bounce around a thousand times at the speed of light. The impedance at a power pin is the sum of all those waves superimposed. The pin doesn't know what's going on here -- can't -- it's just a complex number that varies with frequency.A knee-jerk reaction is absolutely undeserved. That "general" rules as sloppy as these, continue to exist and (mostly) work, is proof that PDNs can be quite messy indeed compared to an optimal case, without impairing overall performance of the system.Indeed, I think you will find the impedance is quite low either way. You may even be pleasantly surprised to see the performance, if you take the time to measure or simulate it.What really matters is ensuring you don't have poorly damped LC resonances, which is where you win with a regular structure with bulk caps for termination.Tim

author: matseng
author_rank: Frequent Contributor
timestamp: July 10, 2018, 06:41:01 am
content: If I'm allowed to slightly hijack/follow up on the subject of this thread I've been thinking of the standard oldskool 2-layer DIP-based logic boards where they used a fork-like structure to distribute the pwr & gnd to the ICs without messing up the available routing space for the signals. [please note that I've left out the decoupling caps in the images below for clarity reasons]As I remember it the two buses came in from one side each - both on the same layer. So the vcc bus went up the left edge of the pcb and then forked off horizontally into each row of ICs. And gnd went up the right edge and forked off into the rows in the other direction. This is shown in the first image named "A"Without decoupling caps this would give enormous return current loops - and I guess since the decoupling caps aren't perfect there will still be residual currents going all around the loop.Now I've been taught that one should try to keep the high-frequency return currents as close as possible to the source currents. So the "B" version might be better then? Where both gnd and vcc is going up the pcb on separate layers on the same edge and then change the layer on one of them and let both fork out on the same layer across each row. This will significantly minimize the loop area.After all this I finally come to my question - would version "C" be better or worse than "B"? Here I loop the vcc / gnd, on separate layers, all the way around the full edge, and from each edge go into the rows of ICs. This make the power distribution be more like a grid than a fork. This would hopefully reduce the resistance and impedances, but I'm afraid it will act as some antenna and fsck up the emi profile and whatnot.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 10, 2018, 07:53:54 am
content: Indeed, all these structures are some kind of folded dipole. As such, they are quite fine radiators, at resonant frequencies; and good enough to be bothersome at other frequencies.At frequencies below resonance, C has the least inductance from any one chip to the power supply, followed by B, then distantly by A (which has full loop area).With bypass caps, A is about as good as any other. Consider: bypass caps effectively short together the VCC/GND traces, at RF. The HF equivalent circuit is the same as C, give or take trace width (C then has two traces effectively in parallel; A could be made with slightly-more-than-double-width traces to give the same result).With bypass caps, the loops are small and everything's happy, riiiight? Well, the conceit to that logic is ignoring traces spanning between rungs of the ladder. Which inevitably carry signal current into input pin capacitances, or off into transmission lines (backplanes, cables, anything with a heavier dynamic or static load). That draws current between rungs, and makes them bounce.If the transition rate (rise time) is much longer than the electrical length of the folded dipole structure, it's not a big deal: the voltage between rungs will bounce a proportionally small amount. Say the width is 0.3m, the risetime is 5ns (1.5m) and the supply is 5V, then the bounce will be on the order of 5V * 0.3 / 1.5 = 1V. "On the order of" meaning, it will be proportional to this, but give or take whatever factors due to geometry, exact waveform (TTL high is slower and weaker than TTL low), load and so on. 1V might be fine for logic levels (well, that'd still be marginal for TTL, but not hard to improve), but would be a nightmare for EMI, where millivolts matter. That "geometry factor" isn't going to be more than a factor of 10, and we're off by three of those for EMI purposes, so it's obvious something must be done to fix EMI in this case.The usual solution is backing the board with a ground shield, which somewhat shortens the loops (say the rungs are spaced 2cm apart, and the shield is 6mm away -- that's a significant reduction in free space around the loops), and reflects noise back into the circuit, preventing it from radiating. Then you only have to worry about connections which penetrate the shield: conducted EMI. This is still an EMI problem and all that entails, but you at least have a plane to stand on (literally): if nothing else, you can extend the shield out (i.e., use shielded cable), or filter the signals where they penetrate the shield.The same principle extends to the estimation of local bypass and such.First, guess how much impedance you actually need, and at what frequencies.Example: TTL might require less than 0.5V ripple, with 5ns edges, and say 100mA worst-case transient current draw (step or impulse) for a whole chip. That gives you an impedance of 0.5V / 0.1A = 5Ω, and an inductance of 5ns * 5Ω = 25nH. (Again, give or take factors -- if these were sine waves, inductance would have a 2*pi in there. We're not talking sine waves here, but actually we'd expect some kind of humpy, or triangular, or square waves to be generated by logic chips. A different factor applies in that case -- use the inductor equation V = L * dI/dt to figure that out exactly. For now, understanding that there's a modest constant in there, and that this will give the right ballpark, is sufficient.)Second, turn that impedance into a trace length. Typical traces are around 100 ohms, higher for thinner traces and without ground plane, and lower for wider traces and with ground plane. (You should always endeavor to design a 2-layer board with CPW (coplanar waveguide), i.e., a trace on top, surrounded by ground fill on top and bottom, with the pours stitched together with vias everywhere traces cut through them.) Impedance divided by the speed of light, gives trace inductivity: 100Ω / (3e8 m/s) = 0.33 uH/m. 25nH then is 7.5cm.And there you have it, your maximum target supply trace length. Note this includes component body length -- it's rather futile to sweat millimeters here and there when you're laying out DIPs two centimeters long! -- and still includes geometry factors, so you should target, say, 1/3 of this or less. Which is quite feasible with chips placed end to end, with a bypass cap every chip or two.This also shows it's absurd to try and use, say, 74LVC (~1ns!) on a DIP scale. (Something like a 74AC series bus driver is ridiculous enough!) If the poor thing is able to switch at all (without breaking into oscillation), there's no way you're going to keep that edge clean as it leaves the chip. Rise time is a big driver for SMT, and carries many other advantages as well.Tim

author: matseng
author_rank: Frequent Contributor
timestamp: July 10, 2018, 11:26:58 am
content: That's a nice explanation - thank you for spending time writing it up.

author: claudiux
author_rank: Newbie
timestamp: July 17, 2018, 02:47:06 pm
content: Thanks to all for theses responses