Routing questions - GND traces on top / GND vias + bottom GND plane / TOP fill - Page 1
Forum section: electronics / projects

author: Holup
author_rank: Newbie
timestamp: November 03, 2024, 03:34:34 pm
content: Hi,I am a beginner designing a DEV board for Simcom A7670 modem and have some questions about routing.I have came up with 3 different ideas for routing GND and could use some help deciding.The schematic...Design 1:(All GND traces are routed on TOP layer. Bottom layer is almost solid GNP plane, but nothing is really connected to it expect the through-hole headers.)(All GND nodes on the screenshot are highlighted)Design 2:(Most of GND pads from TOP layer drops by a via to BOTTOM layer, which is solid ground plane.)(All GND nodes on the screenshot are highlighted)Design 3:(All GND nodes are connected by a TOP layer ground fill.)(All GND nodes on the screenshot are highlighted)Question 1 (GND connection):Which of the designs is best in terms of EMC, layer stackup and good routing practice in general? Or is it some combination or something else entirely?Question 2 (POWER tracks):I have multiple power pins on the modem U1 next to each other. I have routed thick traces from J1 > C2 > U1. The traces covers 3 pins at once. Is this OK, or should it be avoided, for example for soldering reasons?Question 3 (anything else?):Do you see something else bad on the design?

author: Siwastaja
author_rank: Super Contributor
timestamp: November 03, 2024, 03:45:31 pm
content: Continuous ground plane occupying a full layer. Do not waste time on routing GND traces, go to the plane with a via (or two if they fit!) with shortest possible track (needed to take the via away from the pad to prevent it from sucking solder, not any longer than that).For very simple designs, 2 layers work. You have one layer for GND, another for routing signals and power traces. When that single routing layer becomes difficult to manage, then you go for a 4-layer design.This is optimum for EMC, signal integrityandease of design. Of course, you can cost-reduce by carefully ignoring the above rule about GND layer only being GND. Add a track or two (signal or power); but then you need to be quite careful to have plane at that location on the other layer and stitch them together with vias, to form a wide "jumper".With a full ground plane, adding fill to the signal/power routing layer (top in your case) is optional and not that big of an improvement. If you do it, stitch the two ground fills together with vias regularly. Avoid very long, narrow, unstiched fingers. Extra work with not much to gain.

author: Ian.M
author_rank: Super Contributor
timestamp: November 03, 2024, 03:53:42 pm
content: Its a dev board, so break out all unused signal pins at least to pads round the chip so you've got somewhere to solder any bodge wires you later require without having to solder direct to the IC pins. Similarly add a few spare pins to J2, so you don't have to glue on a header for any extra signals you need to take off-board. Put mounting holes in the corners!

author: PGPG
author_rank: Frequent Contributor
timestamp: November 03, 2024, 10:44:50 pm
content: My example is here:https://forum.kicad.info/t/approaching-pcb-track-routing-for-a-newbie/36302/8All vias you see there are GND.

author: ArdWar
author_rank: Frequent Contributor
timestamp: November 04, 2024, 08:32:38 am
content: Put R1-3 in a neat row pleaseIt's good to organize similar function components in a logical way. Especially when the signal traces are already neatly ordered. No need for snaking around.

author: Holup
author_rank: Newbie
timestamp: November 05, 2024, 08:29:11 am
content: Thanks for the replies. I am uploading what I ended up with.I just want to get manufactured 2 of these with JLCPCB, so it does not have to be perfect. If everything is working fine, I will be integrating this into final product comprising of this modem, microcontroller, power regulation and battery management. I started with everything mentioned as a cheap module and built the first prototype and now I am designing every one of the modules myself with some changes. They will be merged into final PCB once every one is tested on a breadboard/perfboard together.