Circuit analysis / simulation problem - Page 1
Forum section: electronics / projects

author: ormaaj
author_rank: Contributor
timestamp: January 11, 2022, 10:37:12 am
content: This is one of my simulation test jigs for designing and comparing amplifier models.In order to create an ideal signal source that accurately reflects power drawn from the supply source, I had to design an effectively infinite gain amplifier model. I've come up with many ways to do that, but the operation of this one particulrly baffles me. It is meant to work as follows:The signal source S0 is copied into the infinite impedance node S1 by two infinitesmal current sources B1 and B2. This somehow creates a virtual voltage value at S1 from which B4 calculates a current based on the impedance of its load (which we can assume to be a fixed 50 ohms. Those subcircuits are just simple LTRA models that can be ignored). B3 then copies a corresponding current out of S1 so the overall system scales itself to ultimately converge to the S2 voltage following S0.How are V(S2) and I(B4) calculated?I have set this up to be a perfectly rigid model with infinite rshunt, so I'm pretty sure it isn't cheating with tiny hidden current paths or anything like that. It also appears to be an incomplete / imperfect implementation at least in ngspice. For example if you try mirroring the B{1,2} current with a CCS the simulation either fails or produces erroneous results. So it seems these virtual infinite values can only be indirectly accessed in certain ways, otherwise SPICE tries to force conversion to a float representation which obviously fails.I've reused this concept several times now for things like opamp output stage models. It works surprisingly well given I have absolutely no clue how it works!I'm using ngspice but I would guess this should work in any simulator with standard B sources, though I've never seen an example like this or found this "feature" documented anywhere.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 11, 2022, 02:01:15 pm
content: I don't get it, what's being tested? U1, U2? Why two at once? Why is there no connection(?) to the VCC0, etc.?Oh, just noticed VCC0 chains into the other numbers. Why not direct wire them then? Smells of addiction to net labels?There's apparently no loss on the LCs, which maybe isn't a great idea for a simulation. Simulating arbitrary reactive supply impedances doesn't seem like a great idea either, especially when it apparently affects your... sense amp? as well. Typically these are analyzed by RF techniques: hook up a VNA to the port and measure the impedance there. This will tell you the transmission from power port to output (PSRR) as well as the port impedance and stability.And so, is your question, how the sense? amp works..? I'm not clear on what's the "problem" here.S1 should probably have some RSHUNT (I don't know offhand if ng has a default for this; one is not set in .options), or CSHUNT to define its gain at AC.I don't get why VCC1/etc. currents need to be mimicked from the behavioral circuit in the corner, or what it's really doing. I guess V17 is a signal source, B1 and B2 are supply currents, B5 and B6 are some kind of common mode / output current, and... why does it go into transmission lines?Finally, why all the stacked capacitors? Unless those are actually SUBCKTs, their values simply add up in total. SPICE doesn't care how you connect or wire ideal components together, only the equivalent total matters.Is that a bug? The junction of e.g. L6, V... H??, C19? It looks like it should be a junction, but one does not show. I don't know how this schematic capture resolves overlapped pins. It looks to me like C19 and the battery are in series, and separate from the rest.And yeah, the labels overlap in several places, further hurting readability..Also in params, I see LSRC, but RSRC and LESR don't show up anywh... ah fuck so it is part models, and this isn't the complete schematic at all.Pet peeve: schematics not representing what they're supposed to be!Tim

author: ormaaj
author_rank: Contributor
timestamp: January 11, 2022, 04:52:37 pm
content: Quote from: T3sl4co1l on January 11, 2022, 02:01:15 pmYep two at once because I'm typically comparing my models against some reference which is usually some garbage broken vendor model. Characterizing what has changed if anything requires subjecting it to a battery of tests under various biasing conditions and whatnot.QuoteOh yeah the gazillion labels are totally essential when there are numerous grounds. This is the greatly simplified version in which I've merely approximated actual analog delays with inductors. That gets rather complicated quickly.QuoteThere is. They are subcircuits. All the L's and C's have an ESR, SRF, Q/D-factor. etc. At minimum there is at least a 1m series resistance for all of them.QuoteSure. I'm specifically testing macromodels here which involves is a somewhat odd combination of ideal circuit testing and mimicing of real circuit conditions.QuoteAnd yet there is none, which is in fact the key point to my entire question! Evidently SPICE is resolving this by implicitly solving some sort of differential equations there which is rather interesting. Normally a construction like this would not work.QuoteBecause as I've alluded to I'm simulating a "single supply" type of circuit in which all parts including signal source are incorporated into the supply currents etc. Transmission line models are quite good for imparting analog delays onto "small signals" but not very good for doing the same with the supply currents themselves. LRC networks are the easiest way to roughly approximate that. More complex behavioral circuits are another. Eventually you give up and move to a real field solver.QuoteGiven the complexity of svg rendering and the way that I generated this a bug would not be very surprising. :/

author: ormaaj
author_rank: Contributor
timestamp: January 11, 2022, 05:09:20 pm
content: Oh you're the seventransistorlabs dude. Thanks for the spice page! I use some of those. Let my unclear schematics be revenge for making me decypher your damn netlists!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 11, 2022, 09:45:55 pm
content: Quote from: ormaaj on January 11, 2022, 04:52:37 pmAh, OK.Would it be better then, to have them better (or completely) isolated? Example, removing L3, L8, L9 and etc., and whatever ESR of V13 and V14, so they're on a voltage supernode. Or using separate sources, so, just two independent paths of 4th-order LPFs.QuoteTo what end is that all simulating? Is this modeling a specific real environment, say? And do you have VNA measurements of that environment to match it up to..?QuoteAh, OK. Well, I don't know about ngSpice specifically; perhaps there's some technical documentation out there? If nothing else, ask the devs?I'm not too familiar with base SPICE, myself, as in actual implementation. Not sure offhand if that would lead to an ill-conditioned matrix, or, how/when dependent sources are put into the matrix calculation in the first place. NG has made a number of improvements (which, again, I know very little about), could very well be they have a solution for that, yeah.QuoteSo this is to model some real-world environment? Would you not be better off assuming contiguous ground plane, and modeling supply inductance / trace length as whatever RLC or TL equivalent is suitable for the frequency range of interest?I don't think there's a whole lot of value in modeling, like, distributed ground impedances. So long as the grounds are good locally, and any trace length between them is a reasonable TL as such. We can assume good shielding (by the plane) and concentrate on DM alone; CM is a matter for external purposes (i.e., leakage from the circuit), and maybe we need better shielding to realize that assumption, but that it's not dangerous to make such assumptions, given that we have the means to implement them (i.e., reserving enough space on the layout to get the desired isolation between traces or surroundings, to be able to add shields, etc.).Mind, "distributed". That's different from local device ground/power, which may still need to be modeled: via/trace inductance, local bypass if applicable, etc. This can then be modeled as a 1-port in series between ideal ground and the device, and a 1- to 2-port to power (depending on how much of the board you want to model, i.e. including PSU, planes, etc.).Quote from: ormaaj on January 11, 2022, 05:09:20 pmAlright, I'll give you that one.Anything you especially wished for a schematic or description on, BTW? Have documented a couple of the more interesting ones, but if there's interest I can add more.Tim