Varying Verilog code simulation results in "Xilinx Vivado" compared to "Xilinx I - Page 1
Forum section: electronics / general

author: FlyingDutch
author_rank: Regular Contributor
timestamp: September 04, 2022, 01:03:43 pm
content: Hello,I wrote Verilog code for implementing "LPC protocol"(Low Pin Count Protocol) driver. And this code works fine in simulation. There was "LPC Host" which sends data over a 4-bit LAD bus and signals Reset and LFRAME (start of LPC frame - cycle) and "LPC Peripheral" which is connected to Host. First I have only I/O cycles support in the project and on simulation (test bench brings "LPC Host" and "LPC Peripheral" to life) and it works fine. Now I want to check if "LPC Peripheral" ignores other cycle types (eg Memory R? W, DMA, etc.). For this purpose, I implemented additional support for "Memory R / W" cycles in "LPC Host" without changing "LPC Peripheral". I also made the required changes to the test bench.Now I come to the heart of my problem: "When I simulate Verilog code in "Xilinx Vivado 2019.1" the results are perfectly correct (as expected), but if I simulate the same code in Xilinx ISE - the results are very different and incorrect."I checked also a simulation of this code in an open-source Verilog simulator called "Icarus Verilog" (see link: Icarus Verilog), and the results also were bad and similar to those in "Xilinx ISE".Could someone more experienced explain to me what could be the reason for this behavior of the simulation? I am not sure if my design is working properly and checking on the FPGA kit, in this case, can be difficult for several reasons.I attached source files of my project (in zipped archive)1) lpc_host.v2) lpc_periph3) lpc_defines.v (constants used in the design)4) lpc_periph_tb.v (this is test bench)Thanks in advance and Regards

author: FlyingDutch
author_rank: Regular Contributor
timestamp: September 05, 2022, 08:12:05 am
content: Hi,nobody can help?Best Regards

author: up8051
author_rank: Frequent Contributor
timestamp: September 05, 2022, 12:22:00 pm
content: Maybe show differences in simulation.

author: FlyingDutch
author_rank: Regular Contributor
timestamp: September 05, 2022, 04:54:34 pm
content: Hello,yes, I would like to attach simulations from these two: Vivado and ISE, but it will take some time.Thanks and Regards

author: hamster_nz
author_rank: Super Contributor
timestamp: September 06, 2022, 04:34:16 am
content: In lpcdefines.v:Code:`define LPC_ST_CYCTYPE_MEMORY_RD 5'h20 //LPC Memory Read (new)`define LPC_ST_CYCTYPE_MEMORY_WR 5'h21 //LPC Memory Write (new)Isn't 0x20 and 0x21 a 6-bit number? 100000 and 100001? They will be aliases for:Code:`define LPC_ST_FORCE_RESET 5'h00 // Force reset (used in the host FSM only)`define LPC_ST_IDLE 5'h01 // LPC Idle stateHere's code where it is used in lpc_host.v:Code:reg [4:0] fsm_host_state;....fsm_host_state = `LPC_ST_CYCTYPE_MEMORY_RD....And the warnings:Code:WARNING: [VRFC 10-8497] literal value 'h20 truncated to fit in 5 bits [Downloads/LPC_protocol/lpc_host.v:118]WARNING: [VRFC 10-8497] literal value 'h21 truncated to fit in 5 bits [Downloads/LPC_protocol/lpc_host.v:123]WARNING: [VRFC 10-8497] literal value 'h20 truncated to fit in 5 bits [Downloads/LPC_protocol/lpc_host.v:127]WARNING: [VRFC 10-8497] literal value 'h21 truncated to fit in 5 bits [Downloads/LPC_protocol/lpc_host.v:174]

author: FlyingDutch
author_rank: Regular Contributor
timestamp: September 06, 2022, 10:43:00 am
content: Hello @hamster_nz,yes, that is actually the cause of the error.Thank you very much for your helpBest Regards

author: hamster_nz
author_rank: Super Contributor
timestamp: September 06, 2022, 09:37:35 pm
content: Yay! Happy I helped