FM modulation and PLLs. Please help me understand! - Page 1
Forum section: electronics / projects

author: tbj
author_rank: Contributor
timestamp: January 28, 2014, 01:27:28 pm
content: Hi everyone,I am currently trying to make a PLL-based FM transmitter, and whilst I think I understand the fundamentals behind PLLs, I'm having a bit of trouble with the theory of how the output can be FM modulated with audio.The rubbish block diagram below shows what I think the PLL should look like. There's a VCO (which, let's say for argument's sake, can tune from 150-200MHz), a frequency divider, a phase detector and a reference frequency of 50kHz, which corresponds to the channel width of the band I am using. This means I can tune to any of the available channels by changing the division ratio of the divider.Code:+-------------+ fVCO| V.C.O |--------->----+-----[ to RF amp ]+---------+---+ || |Audio | +---------------+o--| |--+ Control | Frequency |In | Voltage | Divider || +---------------+| |+------------+ || Phase | | fDiv = fVCO/d| Detector | |+------------+ || | || +-------------------+|fRefExample:Desired frequency = 173.35 MHzReference frequency (fRef) = 50kHz = 0.05 MHzDivider (d) = 173.35/0.05 = 3467In this example, the control voltage will be adjusted by the phase detector until the input frequency is equal to fRef, so the PLL will lock to the center frequency of the channel - no problem.But what if I want to FM modulate the carrier with audio?Let's say an audio signal (for argument's sake, a 1kHz sine) is injected into the control voltage input at the "Audio In" point.This will vary the output frequency at fVCO depending on the level of the input signal - or, in other words, frequency modulation. Good, right?However, let's say we inject a signal to "Audio In" that deflects fVCO by (for example) 10kHz.At this point, fVCO = 173.36 MHzDivider = 3467Phase detector input = 173.36 / 3467 = 50.002 kHzSurely at this point the phase detector sees the error and outputs an error voltage to 'retune' the VCO to the correct frequency, thereby nulling the input signal?Am I missing something fundamental here?I know my block diagram is missing a filter, but isn't the filter just to stop the PLL from "jittering" causing rapid frequency changes?

author: Richard Head
author_rank: Frequent Contributor
timestamp: January 28, 2014, 01:38:09 pm
content: You must modulate the Reference frequency with a varactor diode.If you try to modulate the VCO control voltage the control loop will try to remove the error signal!

author: KJDS
author_rank: Super Contributor
timestamp: January 28, 2014, 01:47:59 pm
content: The scheme you have shown is how it is normally done, however you need to integrate that part of the audio signal below the PLL loop bandwidth to prevent the loop from attenuating it.If all the audio is below the loop bandwidth then it's not too difficult. If you run a very narrow loop bandwidth then that can also be ok for audio. Trying to modulate when it's partially below and partially above the loop bandwidth is usually a recipe for a horrible mess. It can be done, I've even done it once myself, but I think I should have found an alternative scheme.

author: fcb
author_rank: Super Contributor
timestamp: January 28, 2014, 02:16:47 pm
content: Quote from: Richard Head on January 28, 2014, 01:38:09 pmTosh.Most FM (audio) transmitters (PLL based), apply the audio to the varicap in the VCO. The PLL responds to the average frequency, not the instantaneous frequency - getting the PLL loop filter right is the trick.I've built plenty of these in my time, they aren't that difficult. Just make sure your VCO is fairly good BEFORE you close the loop.There's a good app note on the 4046 that will explain the maths better, or just search for a data sheet for something like the UMA1014T (phillips) for application examples (I used to use the UMA1014T in transmitters, I still have 500 or so of them gathering dust here).

author: G0HZU
author_rank: Super Contributor
timestamp: January 28, 2014, 05:14:27 pm
content: There's two common ways to FM modulate that loop.One is the classic way where you arrange the loop bandwidth to be very low. eg 30Hz. Therefore the loop can't respond to >200Hz modulation stimulus added to the VCO tune voltage. So the modulation doesn't get removed by the PLL and you get your FM centred on the wanted frequency. it will respond well to audio frequencies that are >5 times the loop bandwidth.If you reduce the modulation frequency a lot (eg to 10Hz) then the loop will be able to cancel it as an error so the effective deviation goes down a lot for low frequencies.The other way to do it is to have a very wide loop bandwidth (eg 100kHz) and apply the modulation to give FM at the reference oscillator instead of the VCO. This will give FM down to very low modulation frequencies but will have an upper frequency limit of about a fifth of the loop bandwidth before you begin to get unwanted phase and amplitude effects in the modulation.

author: Zero999
author_rank: Super Contributor
timestamp: January 28, 2014, 09:03:41 pm
content: http://educypedia.karadimov.info/library/scha002a.pdf

author: tbj
author_rank: Contributor
timestamp: January 29, 2014, 09:01:52 pm
content: Thanks guys, I think I get it now. So the solution, in simple terms, is to set the low pass filter (loop filter) on the output of the phase detector so that the loop cannot respond fast enough to be able to null the audio signal.One more (probably unrelated) question - what if I wanted to use a much lower reference frequency, such as 5kHz instead of 50kHz? What effect does this have on the stability and accuracy of the PLL?I ask because after doing some research into parts that are easily available, finding a programmable divider that will operate directly at the 173-175MHz band seems to be difficult, so I am thinking of using a /10 prescaler with a CD74HC4059 programmable divider and setting the reference frequency to 5kHz, giving me my desired 50kHz channel spacing. Perhaps I am doing the maths all wrong

author: fcb
author_rank: Super Contributor
timestamp: January 29, 2014, 09:31:39 pm
content: The simple answer is it shouldn't affect the performance of a 'well designed' system.Although, as you point out, the front end of the system needs a fast divider.I'd probably use a ADF4116 and be done, as prescalers cost the about the same as the whole shebang.

author: KJDS
author_rank: Super Contributor
timestamp: January 29, 2014, 09:49:03 pm
content: The prime concern in choosing loop bandwidth is phase noise.Analog devices have a neat phase noise simulator that you can spend many happy hours playing with.