Narrow Band SDR Project - Page 1
Forum section: electronics / projects

author: radioactive
author_rank: Regular Contributor
timestamp: September 13, 2019, 02:41:09 am
content: An image of an SDR optimized for narrow-band project I've been working on for quite a bit of the past year. It has evolved to this. Just an image for now. More later.I planned on crowd-sourcing it, but I'm starting to think I made it too expensive. For once as an engineer, I wanted to not worry too much about cost and just do what I really wanted to do. Got kinda spendy due to all the high-end Analog Devices/Linear Tech parts. add block diagram for the hardware. (will attach diagrams for software later). remove older block diagram

author: radioactive
author_rank: Regular Contributor
timestamp: September 22, 2019, 05:10:58 pm
content: Now that I'm finished with the hardware design, I'm trying to get motivated to work on some block diagrams for the hardware and channel models. I'll share those when I get them ready. I put a video up demonstrating the wide (+/- 90kHz channel) and narrow (+/-10kHz channel). The baseband filters before the ADC are switched capacitor, 8th-order programmable in 10kHz steps. The MCU is an STM32H743 (Y version). The device operates completely stand-alone, but I have it connected to the PC to record the audio output from the device and to display the RF waveforms being streamed over Ethernet/UDP in baudline. The device has lots of CPU left over after demod for decoding digital signals stand-alone as well. Both RF signals in the video were around -94dBm to the antenna port. I zoomed in on the time-domain and XY plots on the second half.The wide signal is from an FM radio station, the narrow signal is from NOAA weather broadcast (about 70 miles away I think).superH FM demod demonstrationhttps://youtu.be/HBXcUFW8yaA

author: awallin
author_rank: Frequent Contributor
timestamp: September 22, 2019, 05:38:53 pm
content: how many bits is the ADC?16-bit good ADC and dual-channel could be interesting...

author: radioactive
author_rank: Regular Contributor
timestamp: September 22, 2019, 05:52:11 pm
content: The I/Q signals are filtered separately and converted from single-ended to differential before being fed to the 16-bit converters on the MCU. The ADCs on the stm32h743 really does live up to the datasheet specs. 83 dB of clean dynamic range for 16-bit, differential mode. I'm using DMA for ADC in interleaved mode. Both I/Q and I2S audio output utilize DMA with double buffering. The front-end can demod a narrow FM signal cleanly from -116dBm to +22dBm (with software AGC adjusting attenuators). I'll have more details when I get the block diagrams ready to go.

author: TiN
author_rank: Super Contributor
timestamp: September 23, 2019, 01:39:27 am
content: I wouldn't worry much about cost of prototype, because it's easier to make something crappy and cheaper , but hard to get high-performance stuff. I'm sure there would be customers who ready to pay the price if the performance and features are in place, since commercial devices of similar capability are likely 10-100 times the cost of your design?

author: radioactive
author_rank: Regular Contributor
timestamp: September 23, 2019, 08:16:48 pm
content: QuoteI was thinking that all along as well, but I'm not sure if enough people would really want to pay the extra money for this device. The expensive parts don't get a significant break until qty 100. Even then, I think it is probably too expensive to get 100 people interested. Everybody seems to want the LTE chip-set bandwidths and larger tuning range. From a poll I saw, most people use their SDR for narrow-band reception, so who knows... maybe.On the first board, I had a totally different design based on STM32H743 + ICE40-8K FPGA + AT86RF215 (TX/RX I/Q streaming over LVDS lines). This design would be a lot less expensive and has really good sensitivity, but the tuning range is limited and the selectivity for narrow-band applications is limited due to slow-roll-off anti-alias filters. No way to fix that issue since the filters are on the die. Still a very interesting part that some might want to take a look at. I've never seen a project utilizing it in the streaming IQ mode before. In addition to the streaming IQ, it also has baseband that can do 128 subcarrier OFDM. The second board added a tuner to the front-end to extend the tuning range. I still hadn't really realized that the selectivity was not going to be good enough at this point. After that, I started working on what has become the current design. All of those $20 parts start adding up quickly.The stm32h743 does have enough mips to do digital voice decoding as well as poly-phase symbol sync for the demodulation. More on that later., I added a hardware block diagram to the first post.

author: awallin
author_rank: Frequent Contributor
timestamp: September 24, 2019, 04:55:34 am
content: Quote from: radioactive on September 23, 2019, 08:16:48 pmFWIW (not much!) for the things we use SDRs for we would need:- input for an external reference frequency, to lock the TCXO that produces the LO (and ADC clock?)- gnu-radio driver, IQ samples either over Ethernet or USB, so the (slow) signal-processing can be in gnu-radio on a PC.

author: radioactive
author_rank: Regular Contributor
timestamp: September 24, 2019, 03:03:45 pm
content: For a gnu-radio driver, I modified the rtl_tcp driver in gr-osmosdr. It uses tcp to control frequency, etc, but changed it to receive 16-bit IQ data over UDP. I still need to add some more features for controlling other aspects, but it works pretty good as is. I just captured some 40-meter Asian AM station from a wire antenna (I don't know what is being said). I had to record video and audio separate (thanks system-d). Doubt they are lined up, but you get the idea:https://youtu.be/u9L5sJRPFiQI'll have to think about how to add the option for a ref clock. Thanks for the suggestion. The TCXO I have on there is really stable inside the RF shield. I wanted to capture some 20-meter CW to show how tight it holds frequency, but didn't see anything this morning.

author: awallin
author_rank: Frequent Contributor
timestamp: September 24, 2019, 04:46:56 pm
content: Quote from: radioactive on September 24, 2019, 03:03:45 pmp4 here shows one solution that Ettus useshttps://files.ettus.com/schematics/n200/n2xx.pdf10MHz is selected either from an external connector, or an internal tcxo. this drives a AD9510 PLL that disciplines a 100MHz vco which is the ADC sample clock.

author: radioactive
author_rank: Regular Contributor
timestamp: September 24, 2019, 11:13:25 pm
content: QuoteI have been running the MCU from a separate 8 MHz crystal reference. I decided to try running some coax from the TCXO reference over to clock the MCU today after your suggestion. After getting the ADC and I2S clocks set up for 10 MHz, all seems to be running well. I have a 3d model for extruded aluminum enclosure that the board fits into. I guess I would probably use a u.fl connector and have a patch coax cable from the TCXO area to bring the external ref input to the enclosure panel. What would be the preference for connector on that? SMA or BNC? Not sure what I was thinking there. I can easily route that and just have another edge mount SMA connector opposite to the antenna connector. add updated block diagram with ext reference input I'm looking at the Si53301 for the 10 MHz ref clock mux. It has a loss-of-signal detection that I think could be used to switch to the external reference automatically when present. Thoughts? Kinda random, but I already posted videos at 7.xx MHz, 97 MHz, and 400.xx MHz, I thought I would add a demonstration of flex and pocsag pager audio output @ 931 MHz. This is direct audio from the fm demodulator in the firmware of the device without editing the waveforms @ -90 dBm. I should note that there is a nearby 902-928 MHz frequency hopper hitting the antenna @ > -60dBm. This could be a problem, but in addition to the programmable base-band filters, the final conversion is an NCO in firmware (away from DC).Back to the reference clock topic. My plan is to make a small test board for the Si53301 that I can wire up to the current board. If all goes well, it will demonstrate being able to switch from the internal reference to an external GPSDO reference automatically (when present). I've been testing the MCU being clocked with the TCXO (and thus acting as a reference for the ADC / Audio clocks, etc.). Works great. Should have done this in the first place. Thanks @awallin. Si53301-B-GMR (not Si53308)

author: radioactive
author_rank: Regular Contributor
timestamp: October 02, 2019, 07:40:53 pm
content: I acquired a GPSDO. Should have done that a long time ago! Very nice.Here is what I'm thinking for the reference clock mux / distribution test board. This is just to test the Si53301 which I plan to connect with small lengths of coax to the existing sdr design. I figured it might be a good idea just to add BNC connector footprints and make the test board usable as a 10 MHz reference for other projects. Thoughts / suggestions?Here is another random example of stand-alone operation (I'm recording the audio directly from the sdr. No PC needed.).Some ham communications via VHF:https://youtu.be/9KYXXc-55yA Yet another random example. The sdr receiving ADSB via stream UDP over Ethernet:https://youtu.be/LvIR2hlR7_Aremove clock_mux_test_rev0.pdfAttached clock_mux_test_final_rev0.pdf I'm just about done routing the test board. Feel free to comment. Will probably order this eve or tomorrow. I'll share results of testing as well as gerbers / BOM after I get one assembled. Should make a nice board for syncing test equipment even without GPSDO.The boards have been ordered. I'll post the results of testing in a couple of weeks or so.

author: radioactive
author_rank: Regular Contributor
timestamp: November 02, 2019, 02:41:12 am
content: I received the Si53301-based reference clock auto-switchover board I mentioned in previous posts. I assembled two boards. I've only tested one of them. See attached results and design files (the SA plots with max hold were run for approximately 1 hour each). I updated the design files to reflect minor changes I made (noted in the last page of the schematic). I'm happy with the results, so will continue to add the Si53301 to the receiver design in order to add the external reference clock with auto-switch over functionality. (allow an external GPSDO to be the reference for the freq synth/ADC/Audio/MCU clocks). The second board will have coax for all the outputs instead of BNC connectors. As I mentioned before, I'm planning on connecting the coax connections to the reference inputs of both frequency synths and the reference input of the MCU for testing before I commit to another spin of the receiver pcb. Will report on that later.While waiting for the boards and parts, I was able to make a lot of progress on the firmware. I continue to be amazed by the capabilities of the STM32H743 part. I will expand on the details of the firmware at a later time, but I am very happy with the performance of the entire system.Here is an example of the current list of built-in demodulators and decoders (no PC required, except for GNURadio driver). The P25P1 output is stellar. I will probably have to remove the calls to the DMR audio codec if I crowd-source it due to potential patent issues, but it does work quite well. Even with all the fir filters, poly-phase resampling / symbol sync, decoders, etc, there is still >180kB of ram left ( could be significantly more if needed) and only using something like 300kB for program flash. I'm definitely one of the people that think that the time is right for these higher powered MCU parts that have great peripherals built in (like the 16-bit ADC modules). With this kind of MCU, I was able to concentrate all the cost on the RF front-end all the way up to the ADCs. I know there isn't much interest in this thread so far, so I will keep the posting to a minimum unless significant progress is made.List of stand-alone / built-in demod and decoders with audio output:~$ ls decodersAvailable SuperH+ built-in demod/decoders------------------FM Analog narrow/med/wide (mode fm)AM Analog narrow/med/wide (mode am)IQ 16-bit over UDP (mode iq) + GNURadio DriverP25P1 Voice + Trunking Control Channel (mode p25)DMR Voice + ConnectPlus Trunking Control Channel (mode dmr)ADSB Mode-S - Console output (mode adsb)ACARS - Console output (mode acars)FLEX-4FSK-1600 - Console output (mode pagers, fm)POCSAG 1200 - Console output (mode pagers, fm) add note about time that max hold was run for each plot during testing 2020-05-11 Due to the cost of this design combined with the entire lack of interest, I decided to open-source it. You can find the repository here:https://github.com/tvelliott/superH_rev4