2 stage OpAmp - Page 1
Forum section: electronics / projects

author: kingkings
author_rank: Newbie
timestamp: May 24, 2020, 10:42:32 pm
content: hello guys , i have been designing 2 stage Op Amp with this specsand this is what i have done so farmy input voltage here is 1 V , i know i should decrease it because my supply is 3V , but to what value so i can saturate my mosfets and get the 75dB

author: Wimberleytech
author_rank: Super Contributor
timestamp: May 25, 2020, 01:45:24 am
content: Is it stable?What is the phase margin?Did it meet you SR spec?You are burning a lot of current in the input stage...why?Your gain depends on gm and r0, where r0 depends on channel-length-modulation...determined by your model. Where are you getting your model? Level 1,2,3, ??Looks like a Cadence schematic...would be nice if you simulated it in LTSpice and provided an asc file.As a starting point the ratio of Pm0/Pm1 should be twice Nm4/Nm0: Pm0/Pm1= 2*2/6 = 4/6 NE 6/10...but close I guess.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: May 25, 2020, 02:29:51 am
content: Hi Wimberlytech and the group,I have modelled lots of circuits in LTspice, but never tried IC design. I know that this can be done, I have heard that Linear Tech used LTspice for many of their IC designs.I followed instruction that I found here:http://www.blog-tm.de/?p=291And inserted the PTM from here:http://ptm.asu.edu/modelcard/2006/65nm_bulk.pmI assume that this is the NMOS and PMOS models for 65nm process.I used the W parameter to vary the geometry between the MOSFETs and built a 1:12 current mirror:This gives M2 drain current is 1.2mA (not the desired result)Do I have set other parameters?I assume that you need a PTM for the process that you are using?The LTspice License agreement includes:4. Restrictions. Licensee shall not ...Snip ..This program is specifically not licensed for use by semiconductor manufacturers in the design, promotion, demonstration, development, or sale of their products. Specific permission must be obtained from Analog Devices for the use of LTspice for these applications.I guess it is okay for educational use.Regards,Jay_Diddy_BCurrent Mirror.asc(5.91 kB - downloaded 59 times.)

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: May 25, 2020, 03:01:59 am
content: Hi,There are other process models here:http://ptm.asu.edu/latest.htmlIf I switch my LTspice model to use the 90nm BSIM3 I get a bunch of warnings but I get M2 Drain current 124uA which is better.Model attached below.Regards,Jay_Diddy_BCurrent Mirror 90nm.asc(8.71 kB - downloaded 65 times.)

author: Wimberleytech
author_rank: Super Contributor
timestamp: May 25, 2020, 12:26:51 pm
content: Quote from: Jay_Diddy_B on May 25, 2020, 02:29:51 amI have never used Level 54 model. However, if this is a 65nm process, your voltages are too high. I ran some curve tracer simulations using the model and it is clear that you need to keep voltages below about 1.2 volts. But, there is still gate current...I question the model, franklyYou are not setting you channel length. Not sure what LTSpice defaults to. You need to set W=xx L=xx

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: May 25, 2020, 12:30:27 pm
content: Quote from: Wimberleytech on May 25, 2020, 12:26:51 pmI'm not familiar with predictive 65nm, but I suspect the 'D33' part in the transistor names of the original poster's screen shot refer to them being models for 3.3V IO transistors.Jay_Diddy_B is indeed using the wrong transistors that will break past 1.2 V probably.EDIT: I'm not even sure that the OP is using a predictive PDK. If this is an actual technology, it is very possible they can't even simulate outside of Cadence since those models are often encrypted and tied to Spectre.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: May 25, 2020, 12:55:37 pm
content: Hi,I understand about the 1.2V limitation of the 65nm process.I was looking at the original posters specifications:So they need to do something 'special' like using 3V3 output transistors to build this op-amp in the 65nm process?(I have done at lot with LTspice put not at the silicon level).But the general idea of having a process model and then specifying different transistors with W=xx and L=yy is correct?The default value for W and L is 20u in LTspice.Regards,Jay_Diddy_B

author: Wimberleytech
author_rank: Super Contributor
timestamp: May 25, 2020, 01:25:18 pm
content: Quote from: Jay_Diddy_B on May 25, 2020, 12:55:37 pmYesSee example here:

author: SiliconWizard
author_rank: Super Contributor
timestamp: May 25, 2020, 02:14:01 pm
content: Quote from: Jay_Diddy_B on May 25, 2020, 02:29:51 amSlightly off-topic, but just to elaborate: AD excludes "semiconductor manufacturers". So that's not just OK for educational use IMO. As I read it, if you're not a semiconductor manufacturer (as per your main activity) but are just working at some company designing an ASIC for internal uses, that should be OK too. Take this with a pinch of salt, I'm no lawyer, but just designing some IC doesn't imply you're a "semiconductor manufacturer" IMHO.Anyway, the OP could also learn how to use ngspice. It's fine for this kind of simulations, it's open-source, and the transistors models are quite good.Although not for a 65nm process, but a 180nm one, I'm attaching a small ngspice lib I have used in the past, in case that could interest anyone.