Debouncing technique for a SPDT switch connected to CPLD - Page 1
Forum section: electronics / general

author: garvind25
author_rank: Regular Contributor
timestamp: June 11, 2019, 04:54:51 pm
content: Hi there,I am making a project where I wanted to connect a SPDT switch to an I/O pin of a CPLD (as shown in the attachment).I was looking for any proper switch debouncing technique to reduce the ringing when the switch is moved from VDD position to GND position (and vice versa). I am worried as while using a SPDT, there will be switch ringing while breaking the VDD connection and while making the GND connection (and similarly for the reverse operation)Pls. note that I prefer a SPDT to SPST as unlike SPST, there is never a direct connection between VDD and GND.Looking forward to your comments.Thanks and Regards,Arvind Gupta.

author: asmi
author_rank: Super Contributor
timestamp: June 11, 2019, 05:30:59 pm
content: Easy (but expensive) way is to use MAX6816 (single), MAX6817 (dual) or MAX6818 (octal) debouncer. The advantages are 1) it's a "plug-and-play" - connect a chip and that's it, and 2) it saves registers in CPLD that you would use for a "soft" debouncer. The disadvantage is that these chips are pricey.

author: boffin
author_rank: Unknown
timestamp: June 11, 2019, 06:04:36 pm
content: Just use an SPST, with a pullup and cap.100k and 0.1uF should work fine.

author: garvind25
author_rank: Regular Contributor
timestamp: June 11, 2019, 06:09:07 pm
content: Thanks for the info. I was unaware of any debouncing ICs that were available! Apart from that, if I dont want a sophisticated debouncing solution (like MAX6818 ), can you suggest any passive element solution or any other low cost solution? I need to interface 8 SPDT switches as digital inputs.Thanks again,Arvind Gupta

author: Fred27
author_rank: Unknown
timestamp: June 11, 2019, 06:14:51 pm
content: If you have an SPDT switch and don't mind using 2 pins then debouncing is easy. Connect the shared contact to ground and the two others to CPLD (or microcontroller) pins. Add pull-up resistors as required. The 2 pins can be connected to set and reset inputs of a latch. I've assumed active low in my diagram, but active high is fine too.Basically, the contacts may bounce but they will never bounce right across from one contact to the other.

author: garvind25
author_rank: Regular Contributor
timestamp: June 11, 2019, 06:30:11 pm
content: @ moffinOK. How does this debouncer circuit work pls? As I understand, when the SPST is open, entire VCC is available across the CPLD I/O pin and the capacitor acts as a reservoir for charge. What happens when the SPST is closed? The node where the cap is connected to the I/O pin gets grounded. Any noise due to switch bouncing gets diverted towards the power supply or towards the pin of the CPLD. The capacitor filters the high transients which come towards the pin of the CPLD. Fine. But there is a direct path between the VCC and GND through the R (10k). So there is a 0.33mA leakage current per switch to the gnd (assuming VCC = 3.3v). For 8 switches, it is 2.64 mA leakage current.Arvind Gupta

author: jmelson
author_rank: Super Contributor
timestamp: June 11, 2019, 07:18:04 pm
content: Quote from: garvind25 on June 11, 2019, 04:54:51 pmOne method is to use a SPDT switch with resistor pull-up to the fixed contacts and the moving contact grounded.Then, use a negative-triggered RS flip-flop to debounce the switch. This, of course, takes two inputs per switch.Another scheme is to have a counter that is "bounded", ie. it will not overflow or underflow.When the switch is pressed, the counter counts up, when not pressed the counter counts down.So, when not pressed, the counter counts down to zero and then stays there. When pressed, it counts up to, say, 255 and stays there.That would be an 8-bit counter. Use the 8th bit as the switch state. This requires the switch to be pressed for 127 count cycles for the counter to reach that state and set the 8th bit high.This takes up a fair bit of logic, so might be too much for a small CPLD. I've used this scheme in some FPGA projects where I had more logic available.Jon

author: jmelson
author_rank: Super Contributor
timestamp: June 11, 2019, 07:22:50 pm
content: You don't say whose CPLDs you will be using. Some Xilinx CPLDs have a "weak keeper" on all inputs. This is a non-inverting buffer that feeds back to the input with a 50 K or so series resistor. It is designed to keep inputs from floating.You might be able to use the weak keeper to add hysteresis to the input to suppress contact bounce. Make your series resistor in the original circuit about 10 K, and add a capacitor to ground at the CPLD side of the resistor. Choose the cap value to provide the desired debounce time constant.Of course, your chosen CPLD may not have such a feature.Jon

author: jmelson
author_rank: Super Contributor
timestamp: June 11, 2019, 07:24:44 pm
content: Quote from: boffin on June 11, 2019, 06:04:36 pm100K will not work on Xilinx XC95xxXL CPLDs, as the weak keeper will override it. You need something like 22K or less to override the weak keeper on the inputs.Jon

author: Wiljan
author_rank: Regular Contributor
timestamp: June 11, 2019, 07:28:19 pm
content: Regarding debouncing on FPGA have a look here, there is a very good analyze and also a solutionhttps://www.fpga4fun.com/Debouncer1.html

author: TomS_
author_rank: Frequent Contributor
timestamp: June 13, 2019, 07:32:29 am
content: Quote from: boffin on June 11, 2019, 06:04:36 pmWill you not need a series resistor between the cap and the switch? In my experience, simple circuits like these have not worked very well for debouncing.

author: BrianHG
author_rank: Super Contributor
timestamp: July 15, 2019, 08:29:54 pm
content: Quote from: Fred27 on June 11, 2019, 06:14:51 pmOMG... Thanks... Out of all the things I do for debouncing, and I'm not complaining as they are functional, using 2 inputs to a SR flipflop has never even once entered my mind at all...So long as your switch is a break-before-make on the 2 throws, this circuit will always work fine!As for software debouncing, I use 2 or 3 D-flipflops tied in series with a common clock. If all the flipflops in the 2-3 line stage pipe are high, I set my result register. If all the flipflops are low, I clear my result register.The speed which I clock the line delay piped flipflops determines the debounce timing. I do it this way since I may have 8 dip switch inputs, each one using 3-4 flipflops while all the inputs share 1 common divided clock or clock enable down at around 50hz.