Finished Digital Clock Design - Page 1
Forum section: electronics / projects

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: June 12, 2016, 12:26:56 pm
content: Hello 5 months ago i finished the circuit diagram for my Digital Clock Project.I was inspired by Daves own videoI found an Instructables project that only displayed Hours Minutes and Seconds .So i figured i could go one step further and added Milliseconds and designed the logic circuitry for Days Months and Years the most difficult part was designing the part which counts the leap year.Linked bellow will be a scan of my circuit.I also added another divider so i can get 1 Hz frequency to drive some leds usind a mosfet ... the leds will sit between the displays so it looks like a real clock.So please take a look and comment on my design keeping please in mind that it is my first "big" circuit design.Also if you need additional information please leave a reply below.Thank you very much.

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: July 05, 2016, 08:06:51 pm
content: Any feedback would be awesome guys.

author: danadak
author_rank: Super Contributor
timestamp: July 05, 2016, 08:59:48 pm
content: Curious, why was it done in discrete logic vs an embedded controller ?The latter of course would replace much of the logic with code that youcan enhance/change to your hearts desire. There are even parts now thatcan be programmed in discrete logic using Verilog, so you get the bestof both worlds. referring to Cypress PSOC.Regards, Dana.

author: brumbarchris
author_rank: Regular Contributor
timestamp: July 06, 2016, 07:35:01 am
content: Do you have decoupling caps on the ICs?The schematic (if that is the only schematic you have) is not showing much in that regards. But then again, it looks more like a combination between a block diagram and a real schematic.regards,Cristian

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: July 07, 2016, 09:38:31 pm
content: Thank you all for your feedback.I was so pumped after watching Dave's video that i never even considered a microcontroller or a FPGA replacing the discrete logic circuitry.I would also like to point out that my schematic originally started out as a schematic but i then run out of paper so it became a diagram.If i were to draw the connections between the BCD drivers and the Displays it would look ugly and probably unreadable so i went with the schematic /circuit diagram hybrid.As for the decoupling caps i have none because I am not familiar with their placement in the circuit.I mean i was planning on having a reasonably big cap between Vcc and Gnd but beyond that i have no idea how to couple discrete logic signals.

author: bitslice
author_rank: Frequent Contributor
timestamp: July 08, 2016, 12:08:05 am
content: That's pretty awesomeDid you do any mathematical reduction for the counter logic, or just wing it?I'm really hoping you'll sketch this up in Eagle or something, I bet lots of people would like to follow your lead but automatically assume a pencil drawing is going to contain a few errors or bits they can't decipher.

author: Macbeth
author_rank: Super Contributor
timestamp: July 08, 2016, 01:47:19 am
content: Forget Eagle, sketch it up in something like Altera Quartus (free) - you can wire up 74 series TTL and emulate it and also go ahead and flash it to a CPLD like an EPM240 board you can get from ebay for next to nothing and build your clock from that. It's all of the old school design but without the cost and headache of discrete logic IC's and mountains of wiring.

author: tron9000
author_rank: Frequent Contributor
timestamp: July 08, 2016, 12:47:21 pm
content: Thumbs up from me, that's some painstaking schematic drawing there!

author: StillTrying
author_rank: Super Contributor
timestamp: July 08, 2016, 10:10:15 pm
content: I couldn't do anything like this, when I know it could be all done with one 14pin chip, 6 switching transistors, and 180 lines of code, and that would include the 100year/400year leap year thing - just in case.However I've got loads of old TTL chips that will never be used, I suppose I could glue them all over a board and hide the uP in the middle of them somewhere, who'd ever know.

author: Macbeth
author_rank: Super Contributor
timestamp: July 08, 2016, 10:58:50 pm
content: I'm with you until you say use procedural code and a 14 pin micro.The point of this exercise is to do it using pure logic. 1980's style.Which is why it should be done with an FPGA/CPLD (with >100 pins) instead. Then try doing it without the TTL circuit and do it in VHDL/Verilog instead,But when it comes to purely making a functional clock as the only goal I'm totally with you. Far easier to program a micro than this!

author: danadak
author_rank: Super Contributor
timestamp: July 09, 2016, 02:22:51 am
content: Use a Cypress PSOC, ARM + Logic Fabric (you can program with Verilog or just usegui logic elements in drag and drop).+ lots of analog, DSP, Comm, display.......see attachment.Regards, Dana.

author: ZeTeX
author_rank: Frequent Contributor
timestamp: July 09, 2016, 10:48:47 am
content: Why hand drawn schematic?

author: oldway
author_rank: Super Contributor
timestamp: July 09, 2016, 12:30:53 pm
content: This isold waytechnology I like

author: Macbeth
author_rank: Super Contributor
timestamp: July 09, 2016, 10:38:14 pm
content: Quote from: ZeTeX on July 09, 2016, 10:48:47 amBecause he is using DaveCAD? Perhaps without the latest animation plugin, but still good enough.

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: August 19, 2016, 01:47:41 am
content: Quote from: bitslice on July 08, 2016, 12:08:05 amI am so sorry for the late answer.I have not touched a single part of the RTC yet.Yesterday i added a backup battery so when power goes down the counters will keep running everything was done by hand including the calculations to get 1Khz out.I will try bringing it into a digital form to be easy to read and to modify.

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: August 19, 2016, 01:49:58 am
content: Quote from: Macbeth on July 08, 2016, 01:47:19 amI will try creating both an Eagle Schematic and one using Altera Quartus after i do some research on it.Call me a masochist but i loved wiring up chips in the past and i have no problem doing it large scale for this project

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: August 19, 2016, 01:51:40 am
content: Quote from: StillTrying on July 08, 2016, 10:10:15 pmHahahahahah i laughed with your commentbut ill stick with the logic after i am done with this i will consider your evil plan

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: August 19, 2016, 01:53:29 am
content: Quote from: Macbeth on July 08, 2016, 10:58:50 pmOf course i could use and an FPGA but where would be all the soldering fun and the frustration that comes with it

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: August 19, 2016, 01:54:41 am
content: Quote from: ZeTeX on July 09, 2016, 10:48:47 amIts easier for me to draw the schematic by hand instead of making it digitally ... i love to write and erase stuff with a pencil.

author: rstofer
author_rank: Super Contributor
timestamp: August 19, 2016, 03:34:54 am
content: i like the old school approach. I ran across my cut-strip-wrap gun the other day and was wondering if I would ever used it again. Sure, the project could be done with a uC, CPLD or FPGA but old school is a much better learning opportunity.Great project!

author: EEVblog
author_rank: Unknown
timestamp: August 19, 2016, 06:36:53 am
content: Quote from: danadak on July 05, 2016, 08:59:48 pmBecause it's way cooler

author: Zero999
author_rank: Super Contributor
timestamp: August 19, 2016, 08:02:09 am
content: Quote from: ChrisGreece52 on July 07, 2016, 09:38:31 pmDecoupling capacitors are used because quite often the power supply has a high impedance to high frequencies. If the circuit suddenly draws a large current for a short time, the supply voltage will drop, then when the circuit suddenly stops drawing current, the supply voltage will increase, often to much more than the nominal voltage. A capacitor will discharge slightly, when the supply voltage starts to fall, therefore keeping the circuit powered and charge up more, when the supply voltage increases, thus absorbing excess energy.The general rule of thumb for decoupling is one 100nF capacitor per IC, but if it's low speed then one capacitor across the supply will often suffice and if it's run off a battery with a low impedance and very short leads, you may be able to get away with none.Capacitors are cheap though, so unless there's a reason not to have decoupling, then just do it.

author: Ammar
author_rank: Regular Contributor
timestamp: August 19, 2016, 08:23:36 am
content: Looks like a lot of fun. A good exercise would be implementing the same thing with an FPGA. One of the first projects I did with an FPGA was implement an alarm clock using RTOS. Great learning experience.

author: Pjotr
author_rank: Frequent Contributor
timestamp: August 19, 2016, 09:32:35 am
content: Nice project!Quote from: ChrisGreece52 on August 19, 2016, 01:54:41 amThat's not a fault of "digital" software but the clumsy counter intuitive implementation of it. With modern schematic entry software you are more or less enforced to draw a net list directly, not a decent schematic. And it's almost impossible, or at least cumbersome, to "sketch". And sketching is an important part of the process to evolute ideas into real working things.Funny enough there is a schematic software package that do this almost right. It is 30 years old and did not change much over that time! It was almost right done the first time. It's called DesignWorks. There is still a active site about it:http://designworkssolutions.com/It was originally written for the Mac, so maybe that's the cause not many EE's know about it. I myself use it still daily as a schematic entry front end for Altium PCB.

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: August 19, 2016, 11:24:13 am
content: Quote from: Hero999 on August 19, 2016, 08:02:09 amThank you very much i did a bit of research on this and found some pdf files that i read and i get it now the use of a decoupling capacitor.

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: August 19, 2016, 11:28:08 am
content: Quote from: Ammar on August 19, 2016, 08:23:36 amAs i said after the original TTL project is finished i will be implementing it into an FPGA

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: August 19, 2016, 11:34:20 am
content: Quote from: Pjotr on August 19, 2016, 09:32:35 amI looked into it and i have to say it looks good i submitted a demo request but i could not buy the whole software because i cannot afford it.If there are free student versions i am willing to download them though

author: Pjotr
author_rank: Frequent Contributor
timestamp: August 19, 2016, 11:37:30 am
content: Quote from: ChrisGreece52 on August 19, 2016, 11:28:08 amDon't do it. FPGA's run a lot faster so you time will pass by a lot fasterAbout DesignWorks: I don't know the status of it at the moment and if it is still active sold. It seems not maintained for the last 10 years.

author: ChrisGreece52
author_rank: Frequent Contributor
timestamp: August 19, 2016, 11:41:26 am
content: Quote from: Pjotr on August 19, 2016, 11:37:30 amI have not even looked at an FPGA yet so i cant tell but anyway i will find a way to overcome the problems that will occur as i did with this project