Vivado Entity Problems - Page 1
Forum section: electronics / beginners

author: mack_g
author_rank: Newbie
timestamp: August 13, 2017, 12:42:39 am
content: After spending a few hours researching I can't seem to find a solution to this error. I added a constraint file to my project that defines the led and switch pins:Code:set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw }]; #IO_L12N_T1_MRCC_16 Sch=swset_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw }]; #IO_L13P_T2_MRCC_16 Sch=swset_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw }]; #IO_L13N_T2_MRCC_16 Sch=swset_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw }]; #IO_L14P_T2_SRCC_16 Sch=swset_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS18 } [get_ports { led }]; #IO_L24N_T3_35 Sch=ledset_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS18 } [get_ports { led }]; #IO_25_35 Sch=ledset_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS18 } [get_ports { led }]; #IO_L24P_T3_A01_D17_14 Sch=ledset_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS18 } [get_ports { led }]; #IO_L24N_T3_A00_D16_14 Sch=ledwhich was fine when the only inputs and outputs that were defined were led or sw but when adding anything other I get this error:[DRC NSTD-1] Unspecified I/O Standard: 16 out of 16 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.This applies to all modules such as any entity that is added to the project. These shouldn't be physical i/o ports and just internal signals. Any ideas?

author: mack_g
author_rank: Newbie
timestamp: August 13, 2017, 12:49:22 am
content: ex vhdl that works:Code:entity adder_test isport (sw : in STD_LOGIC_VECTOR (3 downto 0);led : out STD_LOGIC_VECTOR (3 downto 0));end adder_test;ex vhdl that breaks:Code:entity adder_test isport (sw : in STD_LOGIC_VECTOR (3 downto 0);btn : in STD_LOGIC_VECTOR (3 downto 0);led : out STD_LOGIC_VECTOR (3 downto 0);another_output: out STD_LOGIC_VECTOR(3 downto 0););end adder_test;

author: kbarnette
author_rank: Contributor
timestamp: August 13, 2017, 01:13:34 am
content: What's your constraints file look like with the new inputs and outputs defined?

author: mack_g
author_rank: Newbie
timestamp: August 13, 2017, 01:25:03 am
content: Code:set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw }]; #IO_L12N_T1_MRCC_16 Sch=swset_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw }]; #IO_L13P_T2_MRCC_16 Sch=swset_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw }]; #IO_L13N_T2_MRCC_16 Sch=swset_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw }]; #IO_L14P_T2_SRCC_16 Sch=swset_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS18 } [get_ports { led }]; #IO_L24N_T3_35 Sch=ledset_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS18 } [get_ports { led }]; #IO_25_35 Sch=ledset_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS18 } [get_ports { led }]; #IO_L24P_T3_A01_D17_14 Sch=ledset_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS18 } [get_ports { led }]; #IO_L24N_T3_A00_D16_14 Sch=ledCode:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity adder_test isport (sw : in STD_LOGIC_VECTOR (3 downto 0);btn : in STD_LOGIC_VECTOR (3 downto 0);led : out STD_LOGIC_VECTOR (3 downto 0));end adder_test;architecture Behavioral of adder_test iscomponent full_sumport (cin: in std_logic;a, b: in std_logic_vector(3 downto 0);sum: out std_logic_vector(3 downto 0);cout: out std_logic;propogate: out std_logic;group_gen: out std_logic);end component;begingen : full_sum port map ('0', sw, btn, led);end Behavioral;All the inputs and outputs on full_sum have this error.

author: kbarnette
author_rank: Contributor
timestamp: August 13, 2017, 02:14:28 am
content: I only see definitions in your contraints file for theswandledbusses, not yourbtnbuss.Do you get the same error if you also make assignment for thebtnbus in your constraints file?Disclaimer: I'm an undergrad EE student. I have been known to be wrong.