DIY sine generator SG-642 - Page 1
Forum section: electronics / projects

author: Liv
author_rank: Regular Contributor
timestamp: April 12, 2015, 10:50:40 am
content: Features:• frequency range: 0.1 Hz - 50 kHz• frequency resolution: 0.001 Hz• phase range: ±360°• phase resolution: 0.1°• output amplitude: 0 - 10 V• amplitude step: 0.01 V• attenuator: 0 dB, -20 dB, -40 dB• output impedance: 50 Ohm• meander mode• 10 presets• digital calibration (frequency, amplitude)• interface: USB (optocoupled)• case type: Z-4A (160 x 140 x 60 mm)Probably, this generator is stupid project, because all of its features provides a sound card of the computer.Pulse generatorPG-872

author: Yansi
author_rank: Super Contributor
timestamp: April 12, 2015, 11:03:26 am
content: Thats really nice!Mmm and some I2S DAC there too driven by an AVR

author: Liv
author_rank: Regular Contributor
timestamp: April 12, 2015, 11:08:41 am
content: I2S emulation and DDS implementation with interrupt latency align and interpolation to 16-bit resolution - this is the most interesting in this project.Code:;4 address storeDDS: lds ZL,TCNT1L;2 TCNT1L = 5..8ldi ZH,high(JmpTab) ;1ijmp ;2.org(PC + 0x100) & 0xFF00 ;align to pageJmpTab: nop ; dummynop ; dummynop ; dummynop ; dummynop ; dummynop ;0/1 TCNT1L = 5nop ;0/1 TCNT1L = 6nop ;0/1 TCNT1L = 7; TCNT1L = 8intsreg,SREG;10/13 save status registeroutSPDR,SinH;1 ---> load DAC L high byteaddAPhaseK,AFreqK;1 Phase(0..33) = Phase(0..33) + Freq(0..31)adcAPhaseL,AFreqL;1adcAPhaseM,AFreqM ;1adcAPhaseN,AFreqN ;1adcAPhaseP,zero ;1movZL,APhaseN;1 ZL = wa (word address)movr0,APhaseM;1 r0 = dxsbrcAPhaseP,0;2/1 if(Phase.24 == 0)comZL;0/1 wa = !wasbrcAPhaseP,0;2/1 if(Phase.24 == 0)comr0;0/1 dx = !dxldiZH,high(LUT);1 ZH = table base (low(LUT) = 0)addZL,ZL;1 offset * 2 (word offset)adcZH,zero ;1ldiSinH,44 ;1stsOCR1BL,SinH ;2outSPDR,SinL;19 ---> load DAC L low byteldSinL,Z+;2 SinL = lo sinldSinH,Z+;2 SinH = hi sinldr1,Z;2 r1 = lo sin[x + 1]subr1,SinL;1 r1 = dAmulr1,r0;2 r1,r0 = dA * dxrolr0;1 C = 1 if r0.7 == 1adcSinL,r1;1 SinH:SinL = sin + round(r1:r0 / 256)adcSinH,zero;1 SinH:SinL = AsbrsAPhaseP,1 ;2/1rjmpph_cd1;0/2 jump if Phase.25 == 0ph_ab1:comSinL;1/0 SIN > 0, data line has NOT gate,comSinH;1/0 SinH:SinL = !SinH:SinLrjmpph_ad1 ;2/0ph_cd1:sec ;0/1sbcSinL,zero ;0/1 SIN < 0, data line has NOT gate,sbcSinH,zero;0/1 SinH:SinL = SinH:SinL - 1ph_ad1:outSPDR,SinH;38 ---> load DAC R high byteaddBPhaseK,BFreqK;1 Phase(0..33) = Phase(0..33) + Freq(0..31)adcBPhaseL,BFreqL;1adcBPhaseM,BFreqM ;1adcBPhaseN,BFreqN ;1adcBPhaseP,zero ;1movZL,BPhaseN;1 ZL = wa (word address)movr0,BPhaseM;1 r0 = dxsbrcBPhaseP,0;2/1 if(Phase.24 == 0)comZL;0/1 wa = !wasbrcBPhaseP,0;2/1 if(Phase.24 == 0)comr0;0/1 dx = !dxldiZH,high(LUT);1 ZH = table base (low(LUT) = 0)addZL,ZL;1 offset * 2 (word offset)adcZH,zero ;1ldiSinH,81 ;1stsOCR1BL,SinH ;2outSPDR,SinL;56 ---> load DAC R low byteldSinL,Z+;2 SinL = lo sinldSinH,Z+;2 SinH = hi sinldr1,Z;2 r1 = lo sin[x + 1]subr1,SinL;1 r1 = dAmulr1,r0;2 r1,r0 = dA * dxrolr0;1 C = 1 if r0.7 == 1adcSinL,r1;1 SinH:SinL = sin + round(r1:r0 / 256)adcSinH,zero;1 SinH:SinL = AsbrsBPhaseP,1;2/1rjmpph_cd2;0/2 jump if Phase.25 == 0ph_ab2:comSinL;1/0 SIN > 0, data line has NOT gate,comSinH;1/0 SinH:SinL = !SinH:SinLrjmpph_ad2 ;2/0ph_cd2:sec ;0/1sbcSinL,zero;0/1 SIN < 0, data line has NOT gate,sbcSinH,zero;0/1 SinH:SinL = SinH:SinL - 1ph_ad2:outSREG,tsreg;1 restore status registerreti ;4;89/92 total

author: dom0
author_rank: Super Contributor
timestamp: April 12, 2015, 11:14:50 am
content: Quote from: Liv on April 12, 2015, 10:50:40 amExcept that most sound cards have a higher SFDR (and thus lower THD) than the TDA1543 (~75 dB SFDR to harmonics, other spurious responsesshouldmainly depend on supply and PSRR)

author: Yansi
author_rank: Super Contributor
timestamp: April 12, 2015, 11:20:25 am
content: Forget that TDA1543 is almost vintage, it is still a masterpiece.How much time have you spent making this?//small curious question, what is the functionality of DETx signals?

author: dom0
author_rank: Super Contributor
timestamp: April 12, 2015, 11:24:00 am
content: Quick glance: VT5 peak detector, R64+R65+R61, C73 filter network. So it's probably for amplitude servoing as it goes to the main controllers ADC.

author: Yansi
author_rank: Super Contributor
timestamp: April 12, 2015, 11:27:00 am
content: Possibly, I only don't understand why the base of VT5 goes where it goes, not directly on the output then.. ?

author: dom0
author_rank: Super Contributor
timestamp: April 12, 2015, 11:33:36 am
content: The trick here is that he uses acomplementarybuffer stage (circuit is described en detail in Jim Williams app note no. 47 (linear technology), AN47 page 46). This means that VT8 + VT14 amplify* the positive half of the signal and VT9 and VT17 the negative half. So at the emitter of VT8 you'll only ever get positive swing, and very much so at the base of emitter follower VT5.* only current amplification. Usual voltage drops apply ; are compensated by the feedback loop.

author: Liv
author_rank: Regular Contributor
timestamp: April 12, 2015, 11:36:46 am
content: Quote from: dom0 on April 12, 2015, 11:14:50 amI wanted to make a sine generator based on a modern 24-bit DAC. But the generator SG-642 is enough for me (audio measurements do not mean).Quote from: Yansi on April 12, 2015, 11:20:25 amThis DAC is freely available today.Quote from: Yansi on April 12, 2015, 11:20:25 amI had a few versions of such a generator (for example, SG-420M), so spent a few years.Quote from: Yansi on April 12, 2015, 11:20:25 amThis is detected output level signal. Used for filter frequency responce calibration.

author: dannyf
author_rank: Super Contributor
timestamp: April 12, 2015, 03:38:00 pm
content: Interesting project.QuoteYou can do that in C by outputing the msb/msw of the phase accumulator to the port/ports.

author: Liv
author_rank: Regular Contributor
timestamp: April 12, 2015, 03:51:54 pm
content: No, in C I'll never get this performance. Given the dedicated registers, the difference will be many times.

author: dannyf
author_rank: Super Contributor
timestamp: April 12, 2015, 05:10:17 pm
content: QuoteIn C, you can read/write those "dedicated registers" just as well.

author: Liv
author_rank: Regular Contributor
timestamp: April 12, 2015, 05:45:28 pm
content: No, in C I can't allocate 22 registers for my task. This is a good example what can be done in ASM, but can not do in C.

author: pickle9000
author_rank: Super Contributor
timestamp: April 12, 2015, 06:00:58 pm
content: That is very nice work, great stuff for the resume.

author: dannyf
author_rank: Super Contributor
timestamp: April 12, 2015, 06:32:52 pm
content: I played around on a PIC16F886 (non-buffered spi send). I can complete the transmission of two channels (32 bit data in total) in 150us (=6.3Khz), on a 4Mhz oscillator (1MIPS). All done in C.On a mcu with a buffered spi, I can double the speed. So it is entirely doable in C for audio frequency output.

author: Liv
author_rank: Regular Contributor
timestamp: April 12, 2015, 06:43:00 pm
content: I have a sampling frequency of 206 kHz, for this time is calculated 2-channel DDS with interpolation and transferred to 2-channel 16-bit DAC in I2S. When the CPU speed of 20 MHz (20 MIPS).

author: Chris56000
author_rank: Frequent Contributor
timestamp: October 29, 2017, 02:30:51 pm
content: Hi!I only recently joined the EEV Blog Forum and I came across your Projects whilst looking for schematics for lab supplies!Member Liv. I'd like to express my personal thanks to you for providing details of this suite of economical easy-to-build instruments that any hobbyist or electronics student can build from your plans, and please don't feel anything you post details of has been a waste of time or stupid!You've put a lot of work into each of these and I congratulate you for the time and effort you've taken!Chris Williams

author: Liv
author_rank: Regular Contributor
timestamp: October 29, 2017, 04:59:14 pm
content: Thank you very much for your feedback!

author: Yansi
author_rank: Super Contributor
timestamp: November 13, 2017, 07:30:32 pm
content: Have you thought of using a CPLD+SRAM and a multiplying DAC instead? Could made possibly a nice arbitrary wave gen up to few MHz (tens of MSps at the DAC) for very cheap with quite interesting specs though.

author: Liv
author_rank: Regular Contributor
timestamp: November 13, 2017, 07:47:23 pm
content: Yes, I had plans to make AWG based on Altera Cyclone and AD7744. Even designed an analog circuit board. But then the work was abandoned.

author: Chris56000
author_rank: Frequent Contributor
timestamp: September 19, 2020, 12:36:01 pm
content: Hi!I have now found out Liv's original display is now unobtainable, as are the equivalent replacement ment types!I have contacted Liv by PM to see if he still has his native PCAD design files, so I can use them as a starting–point to make a replacement front PCB that will drive a cheap standard 128 × 64 Graphic LCD Module of the ST7920 type, with an MCP32017 or PCF8574 to interface Liv's I²C interface to the parallel LCD module, and await his reply if he's still available!Chris Williams

author: Liv
author_rank: Regular Contributor
timestamp: September 19, 2020, 02:07:29 pm
content: PCAD files can be found on this page:http://www.leoniv.diod.club/projects/measuring/sg-642/sg-642.html