Looking for a Verilog HDL crash course - Page 1
Forum section: electronics / beginners

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2014, 09:54:33 pm
content: Hi everyone,I'm taking a digital design course this semester. My professor started us off with designing a full adder in Verilog as our first project. This was very easy and only took a few lines of code. Now, our second project is to design a FSM for a traffic light controller. This is a pretty standard project,howeverwe do not have nearly enough knowledge and experience in Verilog to do this. Conceptually it is simple, but actually implementing it is proving difficult.I'm looking for some documentation/websites/books/anything that might help me quickly understand the Verilog language.Any ideas?Right now I'm looking at:http://www.asic-world.com/verilog/veritut.htmlAnd this list:http://www.fpga4fun.com/HDL%20tutorials.htmlBut I'm not sure what would be best for me.

author: marshallh
author_rank: Unknown
timestamp: November 03, 2014, 10:10:55 pm
content: Check out the links in my sig's PDF (Verilog tips)

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2014, 10:17:15 pm
content: Thank you! Just reading it and you say that 80% of Verilog is not synthesizable...Does that mean that it cannot be physically implemented in an FPGA? If so...what's the point?

author: mrflibble
author_rank: Super Contributor
timestamp: November 03, 2014, 10:19:05 pm
content: Quote from: TimNJ on November 03, 2014, 10:17:15 pmSimulation.

author: jancumps
author_rank: Unknown
timestamp: November 03, 2014, 10:19:51 pm
content: Quote from: TimNJ on November 03, 2014, 10:17:15 pmVerilog and VHDL have a simulation origin. Parts of the language constructs are directed to that.

author: jancumps
author_rank: Unknown
timestamp: November 03, 2014, 10:20:43 pm
content: ok flibble, you were first

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2014, 10:25:40 pm
content: Thanks. So can I write something in a Verliog design package, be able to simulate it, but NOT be able to implement it on an FPGA?

author: free_electron
author_rank: Super Contributor
timestamp: November 03, 2014, 10:38:20 pm
content: Quote from: jancumps on November 03, 2014, 10:19:51 pmWrong. Verilog was from the onset a design language.

author: free_electron
author_rank: Super Contributor
timestamp: November 03, 2014, 10:38:54 pm
content: Quote from: TimNJ on November 03, 2014, 10:25:40 pmperfectly.

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2014, 10:43:51 pm
content: Thanks. So, my problem with this concept is "Why have constructs that can only be used in simulation if the end goal is to build a real working chip?"

author: marshallh
author_rank: Unknown
timestamp: November 03, 2014, 11:00:44 pm
content: Simulation and testbenching is absolutely essential for big projects. The idea is you isolate your design into functional modules and write a spec for its I/O, then design a verilog testbench that makes sure it performs as designed by generating stimuli and checking the output.Compile for simulation takes seconds to minutes. A fulll synthesis/P&R on real hardware takes minutes to hours. Iteration is more easily done via simulation.That said, there are some things you can't simulate, and I've done a lot without it.As an example: say you're writing a SDRAM controller, which is a pretty basic thing, but can also be difficult to ensure you don't violate any of the various timing specs. The SDRAM has no way of telling you you are violating its timing, except that it may fail 2 years down the road in a hot place on a certain phase of the moon. So you download Micron's behavioral model and wire it up to your controller as if it were real memory. Then it can print out debug messages about things the chip wouldn't like if you were actually controlling it.

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2014, 11:31:49 pm
content: Quote from: marshallh on November 03, 2014, 11:00:44 pmThanks Marshall. I think I might just be on a different page here. We have been simulating our designs in software by writing a testbench for Xilinx ISIM , and then we confirm the I/O behavior through a timing diagram. Everything we have done has been in simulation so far.So I can write something in Xilinx ISE and it will not be able to create a netlist for it? However, I might want to just simulate something for another reason?

author: tggzzz
author_rank: Super Contributor
timestamp: November 04, 2014, 01:52:16 am
content: Quote from: TimNJ on November 03, 2014, 11:31:49 pmConsider a complex system, e.g. a FFT engine or Fast Packet Switch or communications system.Initially you want to be able tomodelthe design concepts at a high level without having to worry about all the low-level implementation details. At this point you need simple and fast simulations. For example, the FFT engine or communications system might use floating point but the real implementation might be fixed point. Once you have the high level concepts validated, you then implement them in gates. These placing and routing and timing simulations are much slower than the high level simulations. It takes engineering judgement to ensure that the high level models can be implemented without too much difficulty.As a separate use case, consider trying to verify that the gate-level implementation actually performs the expected operation. In this case it is common to have a non-synthesisable testbench firing test sequences at the circuit-under-test and observing the results. In such cases it is irrelevant that the testbench can't be turned into gates - in fact it is a positive advantage!

author: TimNJ
author_rank: Super Contributor
timestamp: November 04, 2014, 02:28:49 am
content: Quote from: tggzzz on November 04, 2014, 01:52:16 amtggzzz,Thank you so much! Now it makes sense why there are non-synthesizeable constructs in Verilog. It's to help simplify the work so you don't get caught up with little things. Once you're ready to take it down to gate level, you can make the appropriate adjustments.I don't know what I would do without you guys because my professors sure as hell don't teach these ideas.

author: slburris
author_rank: Frequent Contributor
timestamp: November 04, 2014, 04:40:39 am
content: I use this book.http://www.amazon.com/Verilog-HDL-Synthesis-Practical-Primer/dp/0965039153It's specifically about synthesis. It's fairly old, so you can pick up used copies <$10.

author: TimNJ
author_rank: Super Contributor
timestamp: November 04, 2014, 04:24:44 pm
content: Quote from: slburris on November 04, 2014, 04:40:39 amThanks! That looks like a solid book. For $10 shipped, I think I might buy it!

author: TimNJ
author_rank: Super Contributor
timestamp: November 06, 2014, 11:36:50 pm
content: Hi guys,I'm working on a project and I'm getting a problem using ISIM. Im using a line like: #10 clk = ~clk in my test bench to create a test clock.If i keep my timescale on the default 1ns / 1ps, it works fine and my timing diagram comes up nicely. However I'm trying to make a 3Hz clock so i need the timescale to be much bigger.But when i increase it to a longer time, the timing diagram makes one of my regs red and xxxxxx instead of cycling through them.Any ideas why it is red and an 'x' instead of green and 1s and 0s??Thanks! Really need help.