How to minimize effect of opamp in. offset voltage on electronic load response? - Page 1
Forum section: electronics / projects

author: RandomUser
author_rank: Contributor
timestamp: July 27, 2022, 03:44:24 pm
content: Hi,I got inspired by Jay_Diddy_B's thread "Dynamic Electronic Load Project". Wanted to build one myself for a long time now!Goal is to improve my analog design knowledge + obtain a usable end-result.The question comes at the end. I want to guide through my setup, so anyone who's interested can step in and/or build up on thisSimulation SetupI hope the circuit is readable but still, some of my thoughts on the circuit.Universal Opamp -> Aol=1Meg, GBW=10Meg, Slew=10Meg and Ilim=25m. No parasitics, so I can model those with external sources. (e.g. input offset voltage)C2 is used to improve the transient behavior while keeping the higher-valued gate-resistor to decouple the gate capacitance from the opamp output for stability.The voltage source "Vio" models the input offset voltage of the opamp. (TL072/4H have typ. +/-1mV, max. +/-5mV)Regarding the simulation, it steps the control voltage "Vset" as a trapezoidal waveform with 10us rise/fall times. --> Load step of 1A with 0.1A/us transients --> 10x "power stages" in parllel = 1A/us total (spec. of the BK Precision 8500B I think)The temperature is set to 100°C (only affects MOSFET).The input offset voltage is stepped from 0 to -1mV to showcase my design challengeSimulation ResultTop pane is the control voltage.Mid pane is the drain current of M1 which, in general, tracks the control voltage almost perfectly.Bottom pane shows the gate voltage at M1.The blue curves show the result with Vio=0mVThe green curves show the result with Vio=-1mV.Observation and (my) explanation of the resultsLooking at the drain current (1.), the blue curve shows an almost negligible initial step, but otherwise a good track of the control voltage.Observing the gate voltage (2.), the little initial step is also visible.My explanation:During the little initial step, the MOSFET is driven through it's non-linear region of the Id(Vgs) curve. Since the current at the Vgs threshold only increases very slowly (low trans-conductance), I think the Id(Vgs) characteristic in combination with the RC-time constant formed by the gate resistor + gate Ciss||Crss creates a dead-time.Can someone confirm/correct my explanation?Also notice, that the Vgs is around the gate threshold voltage ~3V. Only a small voltage step is required by the opamp to drive the MOSFET into its saturation region.My explanation for Vgs@3V is, that this is not the first transient step. During the last falling edge, the opamp "stopped" reducing the Vgs since the opamp inputs got 0V differential due to the missing input offset voltage.In green you can see the behavior with an input offset voltage Vio=-1mV.Looking at the drain current (3.) you see a very noticeable dead time. Reviewing the gate voltage we see, that the voltage goes down to negative ~-10V.My explanation:This behavior is created by a negative input offset voltage at the opamp's inputs.While the control voltage is 0V, the Vio=-1mV is still present between opamp's inputs. Therefore, it tries to compensate by decreasing the gate voltage. Due to no response at the feedback pin (negative currents are not possible), it runs into negative rail.At the rising edge, where we observe the dead time, it takes the opamp ~3us to drive the gate voltage to it's threshold where, current starts flowing again.Problem descriptionBasically, the problem is the dead time and how to improve it.Since every opamp has a different input offset voltage, especially across different ICs, how to compensate for the dead-time?Considering that multiple opamp / MOSFET stages are working in parallel, how can I ensure, that none of the stages is seeing extensive dead-times, although the tolerances of components (resistors, capacitors, MOSFETs, opamps, etc.) are vaying?How do the professional loads do that? E.g. the BK Precision, Siglents or Rigols?Does someone have current transient behavior measurements of such a professional loads with maximum transient from 0A-1A?I'm looking forward to your responseIn the meantime, I try to prepare more simulations to show some more results!EDIT: I'm too stupid to insert images inline.... That would be part of the problem description nowEDIT: Added LTSpice simulation file.

author: RandomUser
author_rank: Contributor
timestamp: July 27, 2022, 08:52:10 pm
content: UPDATEI added a 0.7V ideal diode between the IN- and OUT pin of the opamp to limit the output voltage to -0.7V.SchematicsSimulation result(My) Interpretation of the resultsAs can be seen from the gate voltage, it is now limited to -0.7V.Hence, the opamp works with less voltage swing until the gate threshold is reached.This reduces the dead time.EDIT:Can someone explain me what I'm doing wrong with the attached images? Why are the only showing up at the bottom of the post?

author: magic
author_rank: Super Contributor
timestamp: July 27, 2022, 09:06:44 pm
content: Quote from: RandomUser on July 27, 2022, 08:52:10 pmNothing, image inlining is broken on this forum.As for the question, your identification of the problem is correct. Depending on offset, either a very small current flows all the time but the MOSFET is at its threshold voltage and ready to be turned on quickly, or the MOSFET is turned off hard and takes a moment to turn on. I suppose what could help somewhat is to use a single supply opamp so that minimum gate voltage is zero. Also, using a faster-slewing opamp and/or tweaking C3/R7 time constant.There is an opposite problem too: if load voltage disappears and current is zero, the opamp will drive the gate to 10V unless set voltage (including offset) is negative. High inrush current occurs when the voltage source comes back.

author: RandomUser
author_rank: Contributor
timestamp: July 28, 2022, 07:56:13 am
content: Here are my thoughts on your proposal, to get some discussion started.Maybe I'm missing some important points.Quote from: magic on July 27, 2022, 09:06:44 pmUsing a single supplied opampwould mean, that the opamp now really drives into lower rail saturation which I tried to prevent with the diode D1 while also reducing voltage swing.--> Choose an opamp with low "get out of saturation" time would be required (sorry, forgot the name for that feature)? Probably, this is getting expensive?Addtionally, wouldn't it be required to deal with setting the opamp in an proper operating point by adding some known DC offset etc?Or use a Rail-To-Rail In/Out OpAmp?But to be honest, I want to keep the opamp in "industry standard" territory. Take a look at Daves teardown of the BK Precision Loads. Those are using TL074.If they can design such awesome equipment with it, I hope we can achieve that too. At least, thats the challenge I try to tackleTweaking C3/R7 time constantis not helping anymore. For those fast transients, an increase of C3 wouldn't help.Tried that with 100nF. No noticeable change.Going lower to ~1nF or higher to ~1uF worsens the response.OfftopicQuote from: magic on July 27, 2022, 09:06:44 pmIs this supposed to be fixed?

author: magic
author_rank: Super Contributor
timestamp: July 28, 2022, 08:20:42 am
content: For the record, I don't know how big name loads solve it and whether they even bother. I recall a recent thread about a homebrew fast dummy load, but I don't remember if it was about low latency or only fast rise time. Anyway, it's here:https://www.eevblog.com/forum/projects/gt1mhz-bandwidth-electronic-load/Right about saturation, the diode trick could be faster even if it has to slew 0.7V more. I imagine you could devise an even more effective solution, which compares gate voltage against ~2V and tricks the opamp into increasing it - for example, a PNP whose collector pulls up IN+ (a series resistor required), assuming the signal source can tolerate it. Or something more elaborate, but watch out for oscillation of this secondary loop if it gets too complex and watch out for variation of FET threshold voltage.Beware that TL074H is not an industry standard part, it's TI's proprietary, single-sourced R2R output CMOS opamp with a confusingly similar name.

author: RandomUser
author_rank: Contributor
timestamp: July 28, 2022, 08:34:40 am
content: UPDATEIn my last update, I added D1 to prevent lower rail saturation and to decrease the voltage swing for the opamp.Result is, that the gate voltage can only swing between -0.7V...10V. This decreased the dead time by ~1us.The question I asked myself is, how to get the minimum gate voltage closer to the gate threshold?Here is my attempt. I would love to read some feedback of how you would solve that!SchematicAs you can see, I added 2 components.1. Pullup resistorR1and...2. ...the Zener-DiodeD2.R1forms a voltage divider with R5. Since the opamp only can drive down to -0.7V we can set the gate voltage to the desired value using the formula:Vgate = Vdd*R5/(R1+R5)-VD2 = 10V*1kR/(1kR+1.8kR)-0.7V = 2.87VConsidering the change of gate threshold over MOSFET temperature, getting the lower gate voltage limit to the gate threshold is a trade-off between having a min. current flowing in the MOSFET and optimizing the dead time (as mentioned by magic).Also, consider the tolerances of the resistors. Thats why I added the (my) defined worst-case scenario of 5% over lifetime of the resistors R1/R5, assuming those are 1% tol.D2is optional and was introduced to limit the gate voltage to a max. value to limit the max. drain current. This is a first attemp to fix magics concern:Quote from: magic on July 27, 2022, 09:06:44 pmSimulation result(My) Interpretation of the resultsLooking at the drain current Id(M1) first, it can be seen that the difference between the simulation with an input offset voltage Vio=0mV (blue) and Vio=-1mV becomes quite small.Reviewing the gate voltage, the almost negligible difference in transient response can be explained by the much lower difference of min. gate voltage and the threshold.At least for me, this is now acceptable. Now, the next design challenge is incoming... We're only stepping between to operating points, i.e. 0A and 1A. What happens if we want to reduce step size, e.g. 10mA?Here the result with transient changed from 0A->1A in 10us to 0A->10mA in 10us.I guess we touch the limits of the opamp Aol/GBW/Slew-Rate now. I have no idea how to improve that behavior other than changing to a faster opamp.Maybe you have an idea? Is that even a realistic scenario? How do the professional electronic loads behave in such border-line scenarios?