Quartus II logic element 0 help - Page 1
Forum section: electronics / general

author: kiran_shrestha
author_rank: Regular Contributor
timestamp: October 31, 2015, 04:24:08 pm
content: I have been doing some VHDL but most of the time after compilation the result show the logic element used is zero. Found no solution for this problem , I have used pin assignment file for my altera DE2 with cyclone II board.Here's the simple not gate i have used ,even its not working.Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity not1 isport(a:instd_logic_vector(0 downto 0);y:outstd_logic_vector (0 downto 0));end not1;architecture behavior of not1 isbeginy(0) <= not a(0);end behavior;this is the top level file i have madeCode:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity not1_top isport(SW:in std_logic_vector(0 downto 0);LEDR:out std_logic_vector(0 downto 0));end not1_top;architecture behavior of not1_top iscomponent not1 isport(a:instd_logic_vector(0 downto 0);y:outstd_logic_vector (0 downto 0));end component;beginnot1_0 : not1 port map(a(0) => SW(0),y(0) => LEDR(0));end behavior;I think i need some help.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 31, 2015, 05:48:28 pm
content: Maybe your design is so simple it really doesn't need any logic elements to implement - does the design actually work?I'm not familiar with the Altera parts, but it is quite possible that the input buffer has the ability to invert the input signal, or that the output buffer can do it. If that was the case no LUTs would be needed.

author: Dago
author_rank: Frequent Contributor
timestamp: October 31, 2015, 06:10:10 pm
content: Have you actually assigned the ports to any pins? If the inputs and outputs of your design are not connected to anything on the hardware then the design will occupy no elements because nothing will change state no matter what happens.Also I'm not 100% sure if "0 downto 0" actually creates anything (might be valid, never tried it)? "std_logic" would be a single bit instead of std_logic_vector.

author: gael
author_rank: Newbie
timestamp: October 31, 2015, 06:36:06 pm
content: It could be that the NOT is implemented within the I/O PAD logic, hence no LEs in the FPGA core fabric are actually consumed.

author: AndyC_772
author_rank: Super Contributor
timestamp: October 31, 2015, 10:45:13 pm
content: Quote from: Dago on October 31, 2015, 06:10:10 pmThe top level component in any design is automatically assigned physical pins. If you don't specify particular pins, they'll be assigned by the Fitter.A STD_LOGIC_VECTOR (0 DOWNTO 0) is perfectly valid, it's just a single element array.I'd go along with the other suggestions that the design is so trivial it doesn't actually occupy any resources.Try making a clocked register instead, it's guaranteed to require a memory element:Code:IF clk'event AND clk = '1' THENy <= NOT a;END IF;

author: kiran_shrestha
author_rank: Regular Contributor
timestamp: November 01, 2015, 03:28:43 am
content: Thanks all,Adding a clock helped me, but clock made this synchronous and really solved the problem. But I was wondering the real problem which caused the 0 logic element while its asynchronous (not using clock). May be what AndyC_772 say its might be trival but i dont think its real problem.Actually I am not stuck in designing this small NOT GATE, but most of the time when i see this 0 zero logic element error i search on internet but find no legit reason why this is happening.If i see vhdl code for not gate in internet everywhere i can find the same code. So i think it must work, there's something else causing the problem.

author: hamster_nz
author_rank: Super Contributor
timestamp: November 01, 2015, 04:18:17 am
content: I cut and pasted your code into Xilinx ISE (I know it isn't Quartus...), and can report that it too uses zero logic resources in the fabric there too.So I drilled down in the FPGA Editor, and you can see in the attached image that the signal is being inverted in the input buffer.I don't think you have a problem at all.Also, one thing that you won't come across until it is too late is that you don't have set the range for STD_LOGIC_VECTOR explicitly all the time. That way you won't need a NOT1, NOT2, NOT3 and so on.Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity not_n isport(a : in std_logic_vector;y : out std_logic_vector);end not_n;architecture behavior of not_n isbeginy(0) <= not a(0);end behavior;And here it is used in the top module:Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity not1_top isport(SW : in std_logic_vector(0 downto 0);LEDR : out std_logic_vector(0 downto 0));end not1_top;architecture behavior of not1_top iscomponent not_n isport(a : in std_logic_vector;y : out std_logic_vector);end component;begini_not_n : not_n port map(a => SW,y => LEDR);end behavior;