Help Understanding Xilinx timing constraints - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: March 24, 2020, 06:59:09 am
content: hello all! I hope you are staying healthy in this sad time. My state in the U.S. is making us all stay home, so lots of time to work on FPGAs for meIm working on understanding timing constraints in Vivado.basically here is what I have come up with from researchGood timing constraints practice1). First, define and constrain the clocks in your design2). Group signal paths (global/specific)3). assign global constraints (before synthesis)4). assign detailed path constraintsI made a simple design to play with. It consists of 2 registers with a few not gates between them. Input is clock and a switch, output is an LED. (code at bottom)I made two constraints (XDC) files: timing and physical.In the timing file i just putCode:create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];I didnt include anything else (input/output delays) because the external inputs/outputs aren't synchronous or using a clock domain common to the FPGA.In the physical constraints file I mapped the pins to the top module ports.The picture attached is what I got out of my post-synthesis timing report:Since WNS, WHS, and WPWS are all positive, then everything is okay right?My questions are:-for my simple RTL code, is my timing constraints file accurate (just the create_clock constraint)?-is what i did considered a (very basic) static timing analysis?-what other timing constraints would be useful in my design?-is the order of the good practices (above) correct?Thank you and stay healthy!!!-DomCode:module top(input clk,input SW0,output LED0);reg R1,R2; //synchronous registersreg a,b,c,d; // used for combinational logicalways @ (posedge clk) // pipelinebeginR1 <= SW0;R2 <= R1;endalways @ (*) // combinational logic inbetween R1 and R2begina = ~R1;b = ~a;c = ~b;d = ~c;endassign LED0 = R2;endmodule

author: Dmeads
author_rank: Regular Contributor
timestamp: March 24, 2020, 07:03:26 am
content: also a picture of the schematic might help.I tried to code the RTL so there would be a few LUTs inbetween the registers, but since there were 4 not gates, i guess those cancled out and the tools didnt want to put an unnessecary LUT there.

author: cruff
author_rank: Regular Contributor
timestamp: March 24, 2020, 12:34:22 pm
content: The code in the second always block is never assigned to an output, so can be optimized away completely. The comment associated with that code implies that perhaps the d register will feed into R2, but it doesn't.

author: Dmeads
author_rank: Regular Contributor
timestamp: March 24, 2020, 08:16:55 pm
content: Ahh yes good point bad coding sorryy

author: nctnico
author_rank: Super Contributor
timestamp: March 24, 2020, 10:00:43 pm
content: For most designs it suffices to setup the following constraints:- clock frequency- input to clock- clock to outputThings get a little more hairy if you have two unrelated clocks. Then you will also need to have timing constraints between the clocks. The actual time constraint depends on the maximum delay your clock crossing scheme allows.

author: NorthGuy
author_rank: Super Contributor
timestamp: March 24, 2020, 10:02:46 pm
content: For a simple design, create_clock for your external clock is enough. Vivado will infer everything else.