Rewrite life FLASH fpga - Page 1
Forum section: electronics / general

author: fonograph
author_rank: Frequent Contributor
timestamp: June 08, 2017, 05:52:56 am
content: Since flash fpga have limited life just like flash SSD,how many times can you rewrite the flash fpga before it gets unusable?

author: helius
author_rank: Super Contributor
timestamp: June 08, 2017, 06:14:33 am
content: The ProASIC3 configuration memory is rated to be written 400 times, and will typically last 500 times.

author: AndyC_772
author_rank: Super Contributor
timestamp: June 08, 2017, 06:44:06 am
content: You need to check the data sheet for the specific device you're using.High endurance is typically not a priority for this type of product. I've seen fewer than 100 erase/write cycles specified.

author: legacy
author_rank: Super Contributor
timestamp: June 08, 2017, 01:56:31 pm
content: There are also fpga with sram config, so you can forget the number-of-write-cycles but you need to inject the bitstream trough the jtag cable, and it will be lost on power off. In this case, if you need permanent config, then the bitstream needs to be loaded from external flash chip, usually serial line (SPI?), or something on parallel bus.

author: bktemp
author_rank: Super Contributor
timestamp: June 08, 2017, 02:08:39 pm
content: Quote from: legacy on June 08, 2017, 01:56:31 pmIs there any FPGA without SRAM? I have never seen one.During development you write the configuration data only to SRAM (this is also much faster), so a couple of 100 write cycles should be enough for most applications.

author: helius
author_rank: Super Contributor
timestamp: June 08, 2017, 04:24:46 pm
content: From what I understand, the true nonvolatile configuration FPGAs use the flash gates directly inside their fabric. Writing the flash is theonlyway to program them, so the write cycle limit is important. Some other chips have configuration flash inside the package, but it needs to be loaded into the fabric. Spartan 3-AN for example. These FPGAs can be configured directly into SRAM without wearing down the flash during development. Another example is the iCE40, which can be configured as many times as necessary into its SRAM, but also includes a configuration PROM. When this NVCM is used, the write limit is 1 time only.

author: Bassman59
author_rank: Super Contributor
timestamp: June 08, 2017, 05:18:54 pm
content: Quote from: bktemp on June 08, 2017, 02:08:39 pmAll of MicroSemi's non-OTP FPGAs have flash-based configuration cells instead of SRAM.

author: Someone
author_rank: Super Contributor
timestamp: June 09, 2017, 01:25:34 am
content: Quote from: Bassman59 on June 08, 2017, 05:18:54 pmAnd their OTP (antifuse) parts can have no memory resources on them, instead building memory from register and mux primitives. So no SRAM arrays at all.

author: Buriedcode
author_rank: Super Contributor
timestamp: June 10, 2017, 02:10:27 am
content: Although I have never been stung by this in practice, I have known it happen to others. I remember when MAXII came out, 100 cycles was the norm. That is of course quite an old device, and most 'flash' based devices from that era and onwards have significantly higher endurance. With that said, the MaxV has 1000. This page is 6 years old (and has devices that are well over 15 years old) but mentions the subject:http://dangerousprototypes.com/blog/2011/07/30/cpld-flash-memory-write-cycles/For most applications 100 is more than enough, and chances are the memory will be just as reliable after that number. But if you're learning, or using a dev board for education - where its going to get re-flashed very often - one can easily use that up in a week. Up to a thousand, and I think anyone would struggle to even approach that, again, unless its used in education and flashed tens of times a day.Although I cannot lay my hands on the spec sheet from lattice I vaguely remember the NVCM MachXO3 has very few write cycles, as it is the low-cost version, but that isn't actually flash memory.Notice I've only mentioned CPLD's here. I am unaware of an FPGA with flash (I'm sure they exist, just haven't used them) but then again the lines between CPLD and FPGA have been blurred in the past few years. I guess the MachX03 is an FPGA, but one with built-in config flash and low densities.

author: MK14
author_rank: Super Contributor
timestamp: June 10, 2017, 02:26:17 am
content: Quote from: Buriedcode on June 10, 2017, 02:10:27 amThe reliability or similar PDF seems to say it is rated for 9 write cycles.I think the idea is that for development you use the "internal SRam fuses" and/or external SPI configuration Flash devices. So that only final boards would use the NVCM mechanism, so would need hopefully very few changes of firmware. Otherwise you would be advised to include an SPI configuration flash device.tl;drA life of 9 should be fine for (final) production units with rarely changing firmware.