Buck converter CC regulation dynamics - Page 1
Forum section: electronics / general

author: multipla
author_rank: Contributor
timestamp: March 20, 2025, 12:03:20 pm
content: Hello all,I am designing a peak current mode controlled buck derivated converter (PSFB) which can operate both in CC and CV mode. It is digitally controlled with a 2p2z compensator. CV mode works fine in any load case so far, but I'm having some difficulties in CC mode.During load transients in CC mode, for example going from 600 mOhm to 100 mOhm (nominal output current is up to 200 A), a certain amount of peak current comes solely from discharging the output capacitors.Initially, I used a hall effect current sensor to measure the output current. The transient peak current upsets my control circuit though because, naturally, the MOSFETs don't have any influence on this peak current, but the control circuit can see this current.Next I tried putting the current sensor so that it measures the inductor current, to ignore the output capacitor's influence. I have made some measurements but it still behaves rather sluggishly and I don't know how to design the compensator for this case.I can decrease the gain of the compensator to make it behave stable at the transition from 600 mOhm to 100 mOhm, but then it reacts really slowly on the return.The other way round, increasing the gain improves the return from 100 mOhm to 600 mOhm, but it starts oscillating when reducing the resistance from 600 mOhm to 100 mOhm.Furthermore, I really couldn't find any useful literature so far, the only field that goes slightly into that direction are constant current LED drivers, but none that I found describe the control dynamics or transfer functions.Does anyone have any tips or literature regarding the digital control of constant current buck converters or something that mentions the current transients during load change? Anything that describles compensator design for constant output current?t. multipla

author: Someone
author_rank: Super Contributor
timestamp: March 20, 2025, 10:15:19 pm
content: Quote from: multipla on March 20, 2025, 12:03:20 pmThat is the inherent limitation of linear control applied to a non-linear system, you have to accept the worst case performance under all other conditions. The only solution is non-linear control.

author: mtwieg
author_rank: Frequent Contributor
timestamp: March 22, 2025, 12:54:01 pm
content: Quote from: multipla on March 20, 2025, 12:03:20 pmSo it sounds like you want to regulate the current after your bulk decoupling capacitors, rather than regulating your choke current (before the decoupling caps). This is problematic, as your loop gain will become extremely sensitive to the impedance of the external load. I would only try such an approach if you know the load impedance is restricted to a reasonable range.Could you give a more clear idea of what sort of response time/bandwidth you're looking for? It's possible that simply reducing the size of the output capacitors might be sufficient.Also I'm assuming the peak current mode control loop is using current measured on the transformer or output choke, not the current after Cout.

author: multipla
author_rank: Contributor
timestamp: March 24, 2025, 07:17:42 am
content: Quote from: Someone on March 20, 2025, 10:15:19 pmYes, but surely there must be some literature about output current control and its dynamics rather than CV only? It's pretty scarce...Quote from: mtwieg on March 22, 2025, 12:54:01 pmThe point you mention about the load is part of the problem, yes. It's a converter for industrial use in galvanic processes and such, I need controllable output current and voltage across the whole range: zero to nominal value in current and voltage, with all the possible load configurations inbetween, like an open output and even shorted output with settable current.It should be the output current that is regulated well, but if it's easier to control the secondary choke current it would be an option. It should at least give me an increase in bandwidth of the current regulation, shouldn't it? Of course, the accuracy will be lower because filtering is much more difficult and the moment in time for the current measurement is more critical.Quote from: mtwieg on March 22, 2025, 12:54:01 pmYes I have thought about that too, but I can't go down on capacitance much more since the ripple would increase too much. I could increase the inductance instead, but that would mean a big change in the whole construction of the device, and I want to avoid that if possible.I have calculated the compensator coefficients to get a crossover frequency of the CV control loop of 4 kHz. I have measured the loop with an oscilloscope and it's pretty close to that.For the current loop, I use the same coefficients but adjust the final gain factor at the moment. I think this is not ideal, but I don't know how to do it better at the moment.There are no really restrictive requirements on the control speed and the application is forgiving, if it settles within 5 ms it's good enough.Quote from: mtwieg on March 22, 2025, 12:54:01 pmYes, I am using peak current mode control on the primary transformer current. In my current setup I rigged a second current sensor to the secondary, now I can test it with both current information, either secondary choke current (before Cout) or the real output current (after Cout)Thanks to both of you for your answers.

author: Siwastaja
author_rank: Super Contributor
timestamp: March 24, 2025, 07:55:53 am
content: The problem is trying to apply control theory to something you have no control over.You can't current-limit after the output capacitors. They supply current as defined by your load impedance and their ESR. The idea of output capacitance is inherently incompatibly with constant-current mode (and very suitable to constant-voltage mode). You can't change that by anything you do with the control loop.This is the compromise which every lab power supply needs to deal with. Consider just reducing the value of output capacitance. Investigate why and how much you need it, instead of just slapping it there. Increase f_sw as much as you can. If it's still too much capacitance, it may be necessary to have a linear output stage (with very high bandwidth).

author: mtwieg
author_rank: Frequent Contributor
timestamp: March 24, 2025, 12:12:08 pm
content: Quote from: multipla on March 24, 2025, 07:17:42 amOk I'm guessing by "galvanic process" you mean something like electroplating where you're applying constant current for at least tens of seconds and the load is basically static from the perspective of the power supply. In this case, why do you think you need very fast current regulation bandwidth? Is this actually a problem worth "solving"?QuoteIncreasing inductance likely wouldn't help. Increasing switching frequency might though.QuoteIf the load is effectively a big resistor (sounds plausible for electroplating) then this sounds reasonable.QuoteThis sounds reasonable, but I'm not understanding why you're having trouble hitting this requirement (unless you are using a truly massive output capacitance).Could you share a schematic/simulation?

author: David Hess
author_rank: Super Contributor
timestamp: March 24, 2025, 03:47:35 pm
content: Fundamentally the current control loop problem is the same with a linear power supply. How do synchronous current mode buck converters in continuous conduction mode manage this in variable lab power supplies?Does your design use synchronous rectification and force continuous conduction mode?Is your control bandwidth significantly below half of the switching frequency? Nyquist criteria still apply.I suspect the answer is going to be that you need to increase the inductance to reduce the ripple current into the output capacitance, so that like a linear power supply, the current can be measured before the output capacitance. How much ripple current did you design for? All of it?

author: multipla
author_rank: Contributor
timestamp: March 25, 2025, 08:24:54 am
content: Thanks again for your answers.Quote from: Siwastaja on March 24, 2025, 07:55:53 amYes, I understand. Ideally, it would have no output capacitance to achieve a well controlled output current.But should it be possible to regulate the inductor current instead and achieve a better control? With reasonable filtering and the right measurement time I should be able to get the current output current (minus the transient coming out of the output capacitor)?I will look into the dimensioning of the output caps again though, thanks. I already did some calculations of course, but maybe I can improve the situation there with my latest results.Quote from: mtwieg on March 24, 2025, 12:12:08 pmYes, you are right. I guess even a few tens of milliseconds would be okay, but, in the past, we also sold these supplies in other areas where it might be too slow.But I get what you are saying, without definite requirements I can't do this properly and specific help is difficult. I will talk to the people in charge again because I don't have enough info atm.Quote from: mtwieg on March 24, 2025, 12:12:08 pmI have the configuration in attached drawing. The inductor is 1 μH, capacitance is 10 times 680 μF with 10 mOhm ESR each. Switching frequency is 100 kHz on the primary side, the inductor ripple current is 200 kHz.Yesterday I might have found another problem in my prototype that also interferes with the behaviour in these operating points (e.g. going from an output of 10 V, 20 A into a short with 20 A). In order to increase the operating range into very low setpoints, I implemented a frequency reduction mode when the setpoint for the primary current gets below a certain threshold. Some of the apparent instabilites are originating from this mechanism, I have to look into this first.I'm beginning to think the topology was the wrong choice and am wondering if I should have opted for a plain full bridge with PCMC or a PSFB with VMC instead. The short negative input current spike during the resonant inductor discharge really limits the minimum phase shift angle a lot, I have had to do lots of workaround to address that so far and it's still giving me problems.Quote from: David Hess on March 24, 2025, 03:47:35 pmI don't know, but it's a good point I will look into. If I can find anything on the topic.Quote from: David Hess on March 24, 2025, 03:47:35 pmYes and yes.Quote from: David Hess on March 24, 2025, 03:47:35 pmYes, as I wrote above, the switching frequency on the secondary side is 200 kHz and my control loop crossover frequency is 4 kHz. In CV at least, for CC I reduced the gain even further so it's slower.Quote from: David Hess on March 24, 2025, 03:47:35 pmHowever, if I increase the inductance and decrease the capacitance too much, it creates large voltage overshoots when going into no load from a high current operating point.Here is the current ripple for all operating points:

author: mtwieg
author_rank: Frequent Contributor
timestamp: March 25, 2025, 12:29:46 pm
content: Quote from: multipla on March 25, 2025, 08:24:54 amYeah you (or you're boss) need to put some thought into the essential requirements of this SMPS. One scenario maybe worth thinking about is "hot plugging" the output. That is, the load is disconnected but the current setpoint is nonzero, causing Vout to rise to its setpoint. Then imagine if the electrodes drop into the bath in that state. You could get a massive current surge from the output caps, completely beyond your ability control from the primary side of the circuit. Perhaps some clever software feature could detect the open load and prevent this...I'm not an expert on electroplating, does it actually care much about high frequency ripple current? AFAIK electroplating rectifiers used to be just AC mains rectified by SCRs, so ripple would be pretty high. But maybe 100kHz ripple is worse somehow?Using multiple interleaved phases is another way to reduce Cout requirements. Might also simplify some aspects of the power stage implementation as well (I imagine your synchronous rectifier FETs must be enormous, probably several in parallel).QuoteOk so your LC tank frequency is around 2kHz, so your 4kHz control bandwidth makes more sense now. I'm guessing your output caps are sized for the ripple handling requirement (not for capacitance). If so choosing another capacitor type with (like film or ceramic instead of aluminum polymer) may allow you to reduce Cout a lot while maintaining good ESR and ripple handling.QuoteYes I recall your previous thread about this. If you require operation at very low duty cycles (i.e. with a shorted load), I would strongly advise that the peak CMC loop use the transformer primary current. That way you'll be observing a much smoother waveform without all the issues associated with sensing current on the bridge input. Using the output choke current would probably be even better, but will of course require a DCCT instead of a CT.QuoteYes this is another scenario worth considering. Even if your controller responds instantly to stop delivering power, the energy stored in the choke will end up dumping into the output caps, so less capacitance means more voltage increase. With 200A in 1uH that's 0.02J, which is equivalent to 2.425V in 6.8mF of capacitance. Doesn't sound like much actually, but not sure how much is tolerable for your application.

author: temperance
author_rank: Super Contributor
timestamp: March 25, 2025, 02:43:44 pm
content: QuoteThat's the old brute force method. I think the application is precision plating with minimal or no voids.Maybe, instead of trying to battle the "inrush current", the simple solution is to detect when the load is open, discharge the output and wait until you detect a load and ramp up the output power. It is also more gentle on the power supply and the output capacitors.

author: Siwastaja
author_rank: Super Contributor
timestamp: March 25, 2025, 03:54:43 pm
content: Quote from: mtwieg on March 25, 2025, 12:29:46 pmRipple can be actuallygoodwhich is why there are fancy "pulse" electroplaters. AFAIK, some go as far as use pulses of reverse current, some others just reduce current to 0. I experimented with some of that when I did through-hole plating of PCBs and remember seeing a minor improvement from a simple 555-based circuit after the DC supply. The idea is to reduce the dendrites and get more even surface, or being able to increase average current beyond what would otherwise start causing dendrite issues.In that light, I can fully understand the idea of having a lot of control loop bandwidth, so that arbitrary AC pattern injection could be developed, while keeping the average DC current accurate. And to get that bandwidth plus good efficiency of a switcher, maximized f_sw and minimized output capacitance is the key; some current ripple then inevitably passes through, but is that a problem? Maybe it is for EMC, if nothing else...Also remember that synchronized polyphase might be the trick you need to reduce ripple current while still maintaining regulation!

author: Someone
author_rank: Super Contributor
timestamp: March 25, 2025, 09:53:41 pm
content: Quote from: temperance on March 25, 2025, 02:43:44 pmSimpler: Parallel a (massive/remote) load bank to maintain a minimum load under all conditions.

author: multipla
author_rank: Contributor
timestamp: March 26, 2025, 10:51:30 am
content: Quote from: mtwieg on March 25, 2025, 12:29:46 pmWith interleaved phases you mean parallel primaries and secondaries feeding with 1 output inductor each into a common output capacitance? It would be possible, however, I also have restrictions on space and more importantly on the cooling duct, it should have almost no air coming from the outside to the electronics because it can be quite dirty.The power stage implementation is pretty simple at the moment, I have 4 D2PAK MOSFETs for synchronous rectification, together with SMT high current flat wire inductors and SMT alu polymer caps on an alu IMS board on a big heatsink.QuoteI am using the primary bus current at the moment. Yes you are correct, using the transformer primary current as PCMC-variable would be much smoother and would also make decoupling the bus voltage much easier, the CT between the bus cap and the bridge is not ideal.I have a sample of an Aceinna MCR1101-50-5 AMR sensor here that we used for another project, this could work. At least in the simulation it does and I have done some preliminary measurements with it already with the evaluation board in the transformer wire. Of course the setup is not ideal because it's connected with a few cm extra of leads, but here is a comparison at steady state, a current clamp (yellow) and the sensor's output signal (blue):QuoteNo at the moment it is absolutely not much and acceptable, I was just speaking about when I reduced the capacitance by a lot.Quote from: temperance on March 25, 2025, 02:43:44 pmThe problem is that I have to cover all the other operating points as well, an unloaded output with nominal voltage also has to be possible. Therefore I can't really avoid that transient current, but as long as it doesn't damage my supply it is accepted.Quote from: Siwastaja on March 25, 2025, 03:54:43 pmYes, you are right with the applications.But when using polyphase topologies, doesn't it work best around duty cycles of 50% (or even divisors of that, depending on the number of stages)?In short circuit operation (next to zero duty cycles) it surely wouldn't be ideal either. But probably still better than now.I have to read about that again. One possibility that would maybe work with not too much changes would be using a current doubler rectifier, but iirc it doesn't improve the ripple a lot at duty cycles below e.g. 10%.I have to use 650 ns of leading edge blanking at the moment with using the CT to measure the input current into the bridge, that really messes up the low voltage operating points.

author: Siwastaja
author_rank: Super Contributor
timestamp: March 26, 2025, 11:22:50 am
content: Quote from: multipla on March 26, 2025, 10:51:30 amNo, polyphase makes even more sense with near zero duty cycles. This is exactly why motherboard CPU Vcore supplies are nowadays like 10-phase supplies or even more. High-current, low-voltage buck converters are especially harsh on the input capacitors. By having 10 parallel buck converters each producing 10% duty cycle for total of 10*I_out, you have now basically continuous input current of I_out, instead of 10% duty cycle 10*I_out peaks.But it sure also does help with output ripple as well. Just align the triangle ramps on the paper and you will see. The ripple current moves to higher frequencies so less capacitance is needed to filter it out.What do you mean by "primaries" and "secondaries"? No such terminology in buck converters.Polyphase simply means complete buck converters in parallel. Each has their own inductor. The thing which makes it "polyphase" is synchronization of PWM with optimal phase shift between the units.

author: temperance
author_rank: Super Contributor
timestamp: March 26, 2025, 11:27:37 am
content: QuoteThe best you will be able to find will be papers dealing with on board battery chargers for cars. But they don't need the dynamics you need for your application.

author: multipla
author_rank: Contributor
timestamp: March 26, 2025, 12:14:11 pm
content: Quote from: Siwastaja on March 26, 2025, 11:22:50 amAh yes, I understand it now, you're right. Thanks, that's interesting.Actually my topology is a phase shifted full bridge, I mentioned it briefly in the previous posts. Doing this multiple phases is not possible with my setup currently, I will explore other ways first, at least the stuff I can do with the current setup.So the next things I will try is improving the measurement of the PCMC-variable (transformer current instead of input current) and optimize the output capacitance. I think I might be able to solve some of my problems with that, thanks again for your answers.Quote from: temperance on March 26, 2025, 11:27:37 amThanks, I'll have a look.

author: temperance
author_rank: Super Contributor
timestamp: March 26, 2025, 10:03:06 pm
content: If you say sluggish response, what is the maximum voltage supplied by the transformer and how large is the output inductor? Or how many clock cycles does the system need to settle to a new current value.You might be able to tweak the response by having a current dependent inductor.

author: mtwieg
author_rank: Frequent Contributor
timestamp: March 27, 2025, 11:42:02 am
content: Quote from: multipla on March 26, 2025, 10:51:30 amNo, with interleaved phases basically the entire power stage is duplicated (including bridge, transformer, current sensor, secondary rectifiers, and output choke). But the size of the components will handle only a fraction of the total current, allowing them to be smaller. Often interleaved designs are equal or slightly larger in size to non-interleaved designs. Power efficiency shouldn't be any worse, so thermals shouldn't be a concern either. Interleaved designs are most useful when:1. Your operating current is very high, restricting component selection (like custom inductors for >100A). Splitting into multiple phases might allow for using COTS components.2. Low ripple is critical.3. High control bandwidth is critical.A good example is the voltage regulators used for modern GPU/CPUs, which often need >100A into <1V (not unlike your application) but with only a few millivolts of ripple allowed, and load transients must settle in ~100us. These VRMs often have 8-12 interleaved phases (simple buck converters, not PSFB).A proper multiphase pwm controller is of course necessary for this to actually work properly.Quote from: temperance on March 25, 2025, 02:43:44 pmYeah the more I think on it, the more I think such a feature would be very desirable (at least as an option when testing). Assuming a MCU is used for control, that is.QuoteOk then you're going to have to deal with some very large transient currents in some cases. At the very least I hope the capacitors can withstand it.QuoteNot quite. Basically, if you have N interleaved phases, the net ripple will have nulls with zero ripple current at duty cycles equal to 1/N, 2/N, etc up to (N-1)/N. The peak net ripple current will scale with 1/N. I've attached a simple diagram showing this with different numbers of phases.QuoteAt duty cycles very near 0% or 100%, interleaving has little effect on net ripple current. But ripple current is very low here to begin with. It's unclear if you're having issues specifically near 0% duty cycle (short circuit load condition).Another way to leverage interleaving is that you can reduce the switching frequency of each phase by a factor of N while effectively still having the same switching frequency you started with. This may be very helpful if extreme duty cycles (due to minimum pulse width requirements) are giving you trouble.QuoteThe schematic you showed above will already have an output ripple frequency twice the primary frequency. Using a current doubler rectifier won't affect ripple, but may improve power efficiency though. Maybe you're referring to something else though.