How does this reverse current blocking circuit with two mosfets work? - Page 1
Forum section: electronics / beginners

author: Starlord
author_rank: Frequent Contributor
timestamp: May 22, 2015, 09:01:26 am
content: http://electronics.stackexchange.com/questions/79028/understanding-two-mosfet-with-sources-connectedTwo NFETs, connected source to source. How does this work?To determine what the FETs will do, I need to calculate Vgs. But I can't calculate Vgs because the source is seems to be floating and therefore undefined.Maybe the body diodes have something to do with it? If I have 5V on the left, and on the right, a circuit connected to ground through some load, maybe S will be pulled to ground through the diode on the right?But if so, what voltage potential will S be at? It can't be 0V with the diode's voltage drop, can it? So is it negative? Or positive?I've also seen this circuit made with PFETs. I think in that case they're supposed to be connected drain to drain. Will either circuit work as both a high or low side switch with reverse current blocking? Is there any advantage to using PFETs? I think NFETs might be cheaper and have a lower Rds on, but is there any upside to the PFET? I guess the logic would be reversed too and that might come in handy. Anything else?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 22, 2015, 01:32:35 pm
content: Correct, S cannot be more than 0.7V (ish) above the load side. If the load side is constrained so that it can't go negative (e.g., a unidirectional TVS), and tends to be a positive load (like a resistor), then it will tend to sink current from the right hand MOSFET, pulling its drain down.Thus, a gate voltage of, say, 5-10V above the load's supply rail, will always turn it on.Since it's symmetrical, the same applies to the input side as well.Turning off is a bit more difficult, because Cgs could potentially suck V(S) down along with it, leading to a leaky, drooling turn-off (the transistor(s) remain on above Vgs(th), but as they turn off, and Vds rises, V(S) can move around, and now you have a problem trying to drive V(G) from a ground referenced signal -- a source-referenced driver is always better.Tim

author: suicidaleggroll
author_rank: Super Contributor
timestamp: May 22, 2015, 02:28:45 pm
content: The source voltage will be wherever it needs to be so that the reverse current through the diode on the left is equal to the forward current through the diode on the right, which will be somewhere between 0-0.7v.This circuit can also be made with PFETs, and the same advantages to using a PFET vs an NFET as a high side switch apply here - namely ease of control. In order to use an NFET as a high side switch, you need to drive the gate with a voltage even higher than what you're switching, which may not be easy. With a PFET you simply pull the gate to ground to turn it on.One of the interesting things about this kind of back to back switch is that the order of the FETs does not matter. You can connect them source to source or drain to drain and it will still work properly, though if they're connected drain to drain I don't believe they can share a gate, they need to be driven independently.

author: Starlord
author_rank: Frequent Contributor
timestamp: May 22, 2015, 02:41:49 pm
content: Quote from: T3sl4co1l on May 22, 2015, 01:32:35 pmI didn't understand everything you said, but I take it you mean that doing this with NFETs is hard and doesn't work well, but doing it with PFETs, where the drains are connected is fine?The PFET one makes more sense, and I did the math on it. If my calculations are correct then for my setup, where VIN may be disconnected or between 3.6 and 5.5V, and USB may be disconnectored or 4.5-5.5V, Vth has to be > -4.5V for 0V to turn the FETs on, and if I want to use 3.3V logic to turn them off Vth has to be < -2.2V. Kind of a narrow range of values, but I think there are a few FETs within that range.This setup isn't ideal for my needs though. I'm trying to work out a way to have USB be my primary power source, switch to VIN if that's not available, and short VIN to USB when the ID pin goes low or the uC pulls it down to handle USB OTG. I've been at this for a week now. I think I almost have a solution involving two PFETs with their sources connected. But I'm kinda scared to use it because while it only uses a few components I'm still not 100% certain of how it's going to behave and so far my attempts to simulate any of these FET circuits uisng Digikey's PartSim have failed and I don't know why.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: May 22, 2015, 02:48:24 pm
content: Quote from: Starlord on May 22, 2015, 02:41:49 pmHe's just saying that whatever device you use to power the gate needs to be referenced to the source (IE: lift the gate 5V above the source, rather than 10V above ground (assuming you're switching 5V power)). This is because when you go to switch off the device, the gate/source capacitance is going to drag the source with the gate. You'll try to bring the gate to 0, but it's going to pull the source negative along with it, to keep Vgs constant. Of course if the FETs are still on, then the 5V power input is going to tend to keep the source stable, but it's going to be fighting Cgs. Long term the leakage through the diodes is going to bring it back to 0-0.7V, but that might take some time.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: May 22, 2015, 02:55:31 pm
content: Quote from: Starlord on May 22, 2015, 02:41:49 pmThat's not difficult at all to find. You need to look for Vgs(th) values that are even closer to 0 than that though if you plan to pull any significant current (again, not hard to find). Remember, at Vgs(th) the device is not really "on", you need to more or less double the specified Vgs(th) in order to get an Rds(on) that even approaches what you see in the datasheet.

author: Starlord
author_rank: Frequent Contributor
timestamp: May 26, 2015, 06:29:53 am
content: > One of the interesting things about this kind of back to back switch is that the order of the FETs does not matter. You can connect them source to source or drain to drain and it will still work properly, though if they're connected drain to drain I don't believe they can share a gate, they need to be driven independently.What do you mean by driven independently?

author: Delta
author_rank: Super Contributor
timestamp: May 26, 2015, 11:58:47 am
content: Quote from: Starlord on May 26, 2015, 06:29:53 amErm, as in, erm "not connected together"Are you currently calculating launch trajectories for NASA?

author: Starlord
author_rank: Frequent Contributor
timestamp: May 26, 2015, 08:13:30 pm
content: Quote from: Delta on May 26, 2015, 11:58:47 amHow do you "not connect together" two gates in the same circuit? If I pull them to ground, they're connected together. If I pull them up, even with individual resistors, they're connected together, through a resistor.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: May 26, 2015, 08:39:57 pm
content: Quote from: Starlord on May 26, 2015, 08:13:30 pmEach gate needs to be driven based on its own fet's source. For a Pch fet, gate A needs to be pulled below source A, and gate B needs to be pulled below source B, in order to turn it on. If the two fets share a source, then the gates can be connected together, pulled to the common source, and a single GPIO can drive them. If the two fets share a drain, then the sources are separated, which means the gates need to be separated and they need to be driven independently.If they weren't separated, then which source would you pull them to? If you pulled both gates to source A, and source A was 0V while source B was 5V, then you'd turn on fet B and subsequently push current through fet A's body diode, raising the voltage of source A until it tried to shut off fet B, etc.

author: Starlord
author_rank: Frequent Contributor
timestamp: May 26, 2015, 09:33:08 pm
content: Quote from: suicidaleggroll on May 26, 2015, 08:39:57 pmI don't understand. When you say "if the fets share a source" do you mean when the source pins of the FETs are connected?Because if I'm connecting two FETs back to back to block current flow, there is no "source" to share... no connection to 5V in the middle. But the way you're wording it sounds like there's supposed to be one.Of course there would be a connection through the body diode of one FET to 5V, so the source would see 3.8V or so. Perhaps that is the shared source to which you refer?QuoteBut they can't be driven "independently". Not completely. I mean, they have to be driven to ground to be turned on. And if they're both connected to ground, they're connected. Saying I can't connect the two gates together doesn't just imply that I have to drive them high with their own source it implies I can't connect them together, period.QuoteI think I understand what you're saying. But earlier someone said it didn't matter which way they were connected if I wanted to place them back to back to block reverse current flow. So you think I should connect them source to source?Should I... also pull them up to the point between them to turn them off, rather than to the voltage at one of the drains? That kinda makes sense, but after a week of working on this and thinking I understood it well enough to move forward with my implementation I just don't know.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: May 26, 2015, 09:58:06 pm
content: Quote from: Starlord on May 26, 2015, 09:33:08 pmYes. I thought that "share a drain" vs "share a source" made that pretty clear...I guess not. This is very common terminology. When you buy a multi-fet package it will very often be labeled as "common drain" or "common source", which simply means the drains are connected together or the sources are connected together.Quote from: Starlord on May 26, 2015, 09:33:08 pm...what? I never said they needed to be galvanically isolated and I never said they can never be the same voltage. They just need to not be connected directly to each other so they can be driven independently. If an MCU has two outputs, and both outputs are set to 0, that doesn't mean they're connected to each other...it means you have two independent outputs that both happen to be set to 0. They're still independent, they're just independently being set to the same value.Independent != isolated.Quote from: Starlord on May 26, 2015, 09:33:08 pmI never said that. I said you can hook them up either way, but if you hook up them up so they share a drain (drain pins connected together, common drain, whatever terminology floats your boat) you need to drive the gates independently, you cannot jump them directly to each other and drive them with one GPIO like you can if they share a source.Quote from: Starlord on May 26, 2015, 09:33:08 pmVgs is what matters, not Vgd.

author: Starlord
author_rank: Frequent Contributor
timestamp: May 26, 2015, 10:40:58 pm
content: Quote from: suicidaleggroll on May 26, 2015, 09:58:06 pmIf they're both low, they're both connected to ground. If they're both connected to ground, there's path between them. If there's a path between them, they're connected.I get what you mean now, but it's still a confusing way of putting it. And we can argue about that till the cows come home, but that won't change the fact that I was in fact, confused. Whether that makes me an idiot or not, is however, debatable.QuoteAnd I never said you said that.QuoteI understand the term common drain. I just did not understand what you meant by "share a source". And I'm not here to argue correct terminology, I was simply explaining what it was that confused me about your wording.QuoteI can't tell if you're confused about the configuration I was referring to, or if you're saying yes in a roundabout way.

author: Starlord
author_rank: Frequent Contributor
timestamp: May 27, 2015, 11:29:44 am
content: Quote from: suicidaleggroll on May 26, 2015, 08:39:57 pmTwo FETs, (Q103 and Q104) back to back, drain to drain, with both gates driven by the same source and from a single uC pin, something you say can't be done. One source can be 5V while the other is 0V. This is from Atmel's own SAMD21 Xplained board. It's used for switching between USB and external power.Still think I'm being dumb for being confused by all this?

author: suicidaleggroll
author_rank: Super Contributor
timestamp: May 27, 2015, 03:55:45 pm
content: Quote from: Starlord on May 27, 2015, 11:29:44 amI don't want to say it's wrong, but...it's wrong. Unless I'm missing something, Q104 is pointless in that circuit. It is incapable of blocking current flow from VCC_TARGET_USB_P5V0 to VCC_P5V0.If VCC_TARGET_USB_P5V0 is 5V and VCC_P5V0 is 0V, R112 will pull Q104's gate down and turn it on, which will cause current to flow through Q103's body diode. VCC_P5V0 will be driven to about one diode drop below Q104's Vgs(th). A spice simulation confirms this.Maybe in this circuit it doesn't matter. Maybe VCC_TARGET_USB_P5V0 will never be 5V while VCC_P5V0 is unpowered, but in that case Q104 is unnecessary and Q103 is all that's required to shut off current flow from VCC_P5V0 to VCC_TARGET_USB_P5V0.If you want to be able to block current flow in either direction, you cannot follow that schematic. You can either wire the PMOS sources together and pull the gates up to the common source, or you can wire the PMOS drains together and pull each gate up to its respective source with separate NMOS drivers, but you cannot wire the drains together and pull both gates up to one of the sources as they've done.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: May 27, 2015, 04:00:15 pm
content: Quote from: Starlord on May 26, 2015, 10:40:58 pmVgs is what matters, Vgd does not, therefore the gate should always be referenced to the source. So yes, you should pull the gate up to the source, not the drain.

author: Starlord
author_rank: Frequent Contributor
timestamp: May 27, 2015, 05:17:38 pm
content: Well based on this new information, I'm guessing this isn't going to work:[link removed]And if that isn't going to work, I'm guessing that to make it work would require a ton more FETs, which puts me back at square one because I can't fit ten different chips on this board and I'm already pretty much maxed out with five - the three dual PFETs, an NFET, and a buffer for the ID pin.I'm guessing at a minimum I'd need a pair of NFETs each for SW_USB and SW_VIN so that I can pull their gets up to their source when USB / VIN is high.