custom little SoftCores, what do you think about this? [closed] - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: October 09, 2016, 11:37:12 pm
content: Code:* Instruction format:** 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+* | 0 | 0 | operation | dst | imm | - alu imm* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+* | 0 | 1 | smode | dmode | dst | src | offset | - mov* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+* | 1 | 0 | operation | dst | src | reserved | - alu* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+* | 1 | 1 | 0 | 0 | must be zero | - ret* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+* | 1 | 1 | 0 | 1 | address | - call* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+* | 1 | 1 | 1 | 0 | address | - jump* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+* | 1 | 1 | 1 | 1 | cond | rel | - branch* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+*Code:* 'operation' can be one of the following:** two cycle operations (00--)** 0000 logical shift right* 0001 logical shift left* 0010 multiply* 0011 -- reserved** single cycle operations** 0100 bitwise and* 0101 bitwise or* 0110 bitwise xor* 0111 -- reserved* 1000 bitwise invert* 1001 memory load* 1010 move* 1011 byte swap* 1100 add* 1101 -- reserved* 1110 subtract* 1111 compare** smode/dmode can be one of the following:** 00 direct register load/store ("mov reg, reg" not supported)* 01 indirect load/store (offset is added to base address)* 02 indirect load/store with pre-decrement* 03 indirect load/store with post-increment** branch cond codes:** 000 BEQ* 001 BNE* 010 BCS* 011 BCC* 100 BMI* 101 BPL* 110 BLT (signed less than)* 111 BGE (signed greater or equal)

author: rstofer
author_rank: Super Contributor
timestamp: October 09, 2016, 11:52:13 pm
content: I would take a look at the requirements for porting the GCC compiler or read through "A Retargetable C Compiler" and see what the code generator wants/needs. One way or the other, I would want to support C from day one. GCC would be nice because other languages should use the same backend. If you were a real glutton for punishment, you could port the Ada runtime.https://www.amazon.com/Retargetable-Compiler-Design-Implementation/dp/0805316701

author: ataradov
author_rank: Super Contributor
timestamp: October 10, 2016, 12:01:24 am
content: Arrangement of bits in the opcode makes no difference whatsoever. If there is no C compiler for the core, then it is pretty useless given that alternatives exist.

author: C
author_rank: Super Contributor
timestamp: October 10, 2016, 12:29:39 am
content: Quote from: legacy on October 09, 2016, 11:37:12 pmThink if you do some row swaps things will get easer.Example, If you put "- branch" where "- call" is then you have a bit to say "address" used here.Might be a swap for first three to make logic easer.

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 09:18:18 am
content: Quote from: rstofer on October 09, 2016, 11:52:13 pmgcc = crap

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 09:25:16 am
content: Quote from: ataradov on October 10, 2016, 12:01:24 amwith HC11 you usually don't need any C compiler, instead you prefer use assemblywith PicoBlaze (by Xilinx) it's the almost the same case,and every C compiler I have seen ... was not confortable at all (frankly the suck)those things like the ISA above are usesable with fpga,and usually you want to use them because you need somethingeasy to be implemented with a good code density

author: ale500
author_rank: Frequent Contributor
timestamp: October 10, 2016, 09:34:02 am
content: With 18-Bits opcodes, he is targetting FPGA's Block RAMs(but not MAX 10 directly), meaning not that much RAM. Of course Unix v 7 ran in 256 kBytes and a Cyclone V even the smallest one has > 160 kBytes.How much addressing space are you planning ? With 14 bits for addresses, meaning 16 kWords, one can do something.... are DATA/Program spaces separated ?CALL and RET are problematic instructions due to the stack manipulation. A link register that not always has to be pushed/popped simplifies the design. Small constants are used the most. Look at instructions statistics to know where to put the money, so to say.Great would be if one could do a 32-bit core in say 500 LEs... in 3000 you can do almost anything..... RISC 5 (the one used by Project Oberon) is really small for a 32-bit core: 1930 LEs (Lattice MachXO2) with floating point !, yeah those are 32 bit opcodes, though.(But... the point about C is valid. Maybe GCC is not the best but the question is how are you planning on programming your core ? what do you want to do with it ? and others ?)

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 09:34:34 am
content: Quote from: C on October 10, 2016, 12:29:39 amfirst answer about the ISAand it's very interesting, thanks, good idea

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 10:20:50 am
content: don't worry about the tool, I am pretty able to implement (already done)a working assembly compiler in a couple of days during the weekendQuote from: ale500 on October 10, 2016, 09:34:02 amso cool when you don't use it, gcc is for sure the worst choiceeven the dude who made the home brew cpumagic1stayed awayand usedlccQuote from: ale500 on October 10, 2016, 09:34:02 amIf I had came in the need of C compiler for complex things like porting an OS, I would have ignored gccand I would have used a common architecture, such as MIPS or ARM, which all come with professionaltoolchains (Keils?) and debuggersQuote from: ale500 on October 10, 2016, 09:34:02 amI have implemented adebug-eninein vhdl, it's a big finite state machines which talks over the serial lineit's used to import/export things like CPU registers, signals (events like break points/watch point events)and blocks of memory from/to the host to/from the fpgaI started this project in 2008, done in spare time, and it was used along with my own soft core Arise-v2whose ISA is much more complex than the ISA published abovemy Arise-v2 soft core hasn't yet come with an high level language such as a C compilerI am digging in the possibility of a) retargeting lcc, or b) making my own compilerI have an old project about that, it's a sort of "--C", just statements, labels, loops, variables and nothing elseit generated good machine code, in three passes, there is no standard linker (I am using my own symbol table format),but it compiles module per module, and at the end there is a linking stage, even it there is no linker-scriptit was done when I was a student as "examination test", useful to get my degreeanyhow, Arise-v2 is made for fun, I have a degree in computer science, I have studied "languages" and "architectures"Arise-v2 is just "Putting Knowledge into Practice"(1), whereas the above small ISA comes for the need of having a small corein fpga, for same need you might have for things like picoBlaze(1) I have a job in avionics, nobody pays you to do the above thingsthere is no research in the direction of soft core and languageswe use ADA and Misra-C with PowerPC, and our fpgas come in the needof getting the most out of things like ARINC 429

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 10:48:48 am
content: Quote from: ale500 on October 10, 2016, 09:34:02 amyes, no more than 14bitdata and code are separated due to implementation constrainsbut you can access the code space through a trick (dual port ram)p.s. within 512 byte I have implemented a PSX-Pad controlleron 68HC11, which happens to have (in single chip mode) 512byte of ramincluding data, code, and stackI can't, (edit: well it's much more difficult to) achieve such a purpose in CI'd better use assembly

author: C
author_rank: Super Contributor
timestamp: October 10, 2016, 11:18:59 am
content: Did you intend to leave out ADD & SUB with carry?With you can do large math.In your compiler thinking.For pascal with modules, you hear the the "System" module is built in.Think of this a different way. The System module was compiled separately just like any other module. The compiler then before each compile adds a line and processes it before your code "Uses System"This causes a Read the interface which put's system in the AST and dymanic link compiler to system blob or have system blob prelinked.This simple idea lets you remove a lot from pascal compiler and put it into the system module and still act like what is now in system module is built into the compiler.Bit = 0..1Byte = 0..255SByte = -127..128The above being in system module adds pascal's built in types using the compiler.Go a step further a where the compiler knows how to add functions that look like operators and the compiler just got simpler again while using what has to be in compiler.Think the current extreme is C# with Net frame work.

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 12:15:18 pm
content: Quote from: C on October 10, 2016, 11:18:59 ammmm, although architectures like MIPS have already shown that you can do*carry and overflow checks* in software (e.g. the first R2K did it in that way)I am tempted to introduce them in hardware, along with bit-fields instructionsbit{set,clear,get}Quote from: C on October 10, 2016, 11:18:59 aminteresting, thanks

author: C
author_rank: Super Contributor
timestamp: October 10, 2016, 02:19:12 pm
content: You may have missed what I was sayingwith ADD with carryvery Large number math even a small processor, when you have ADD & ADD with carry. I do not remember a CPU with out this.in binary A, B,D = array of bits. for crazy say 1024 bitsFor an 8-bit machine this is three 128 byte arrays.Code:A = add B, Cfor x = 1 to 127A = ADD with carry B, Cnext xThis is a 1024 bit add. Just changing array size and x max lets you have any size of binary add.The first ADD sets status bit as needed for overflow of first 8 bits.ADD with carry uses overflow bit as third input to adder and sets status bit for overflow.The PDP11-35 was built around 4 74181 chips for math & logic. Might want to look at what 74181 does vs what you have.http://www.ti.com/lit/ds/symlink/sn54ls181.pdf\Note that PDP11-35 used microcode to reduce logic in CPU. While a programmer sees 8 registers, internal there were more. If memory serves 16 total.Address buss outdata buss indata buss outinstructionThink there was Interrupt vector in and Interrupt level.and some temps to reduce logic.For a clock it used different taps from a delay line to adjust for logic path delays. It actually stopped dead for memory. A nano sec change in memory speed changed how fast the CPU ran. Accessing non existing memory caused a timeout interrupt to restart CPU in this case.Edit: forgot the Instruction register in list.

author: bingo600
author_rank: Super Contributor
timestamp: October 10, 2016, 03:19:18 pm
content: Quote from: legacy on October 10, 2016, 09:18:18 amBut free/Bingo

author: ataradov
author_rank: Super Contributor
timestamp: October 10, 2016, 03:33:00 pm
content: Quote from: legacy on October 10, 2016, 09:18:18 amYour personal bad experience with GCC is irrelevant here. You don't support it (or any other C compiler) == your project is one of the 1000 other student cores that get abandoned the moment you get bored with it.Now, if I needed a soft core and for whatever reason I did not like NIOS II or MicroBlaze, then I would just take basic MIPS core and be done. Even if I did not want to look around for a reasonably licensed implementation, I can roll my own in a couple days. And I do get both assembler and C support, if I need it.Let's say this core is to compete with PicoBlaze, then it is too wasteful. [next statement is retracted - did not notice 18 bit opcodes at first]You have 28 bits for jumps and calls. What is the point of this? Do you really want to write a program that big in assembly?I simply don't see the point of why this is better than any of the existing alternatives, except that alternatives are not made by you.

author: ataradov
author_rank: Super Contributor
timestamp: October 10, 2016, 03:37:19 pm
content: Quote from: legacy on October 10, 2016, 09:25:16 am32-bit instructions and good code density? Not happening. Look at Thumb-2. It is plenty for controller-like use and actually does provide density.I feel like this is not very well positioned product. On one hand you are talking about simplicity, and on the other propose real heavy-weight architecture.For a really embedded controller, I would like to see what interface you propose for interfacing with FPGA internals. I hope it is not full-blown AHB-like bus, that will put this thing into MicroBlaze / NIOS II / MIPS category, for sure.

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 04:38:12 pm
content: Quote from: C on October 10, 2016, 02:19:12 pmdude, MIPS doesn't have it

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 04:44:36 pm
content: Quote from: ataradov on October 10, 2016, 03:37:19 pm68K is 32bit, good code density

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 04:46:04 pm
content: Quote from: ataradov on October 10, 2016, 03:33:00 pmPicoBlaze needs the Copyright by Xilinx, just to say

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 04:47:32 pm
content: Quote from: bingo600 on October 10, 2016, 03:19:18 pmLLVM and LCC are also OpenSourcebetter code, easier to be retargeted

author: bingo600
author_rank: Super Contributor
timestamp: October 10, 2016, 04:52:41 pm
content: Quote from: legacy on October 10, 2016, 04:46:04 pmWell ....Fromhttps://en.wikipedia.org/wiki/PicoBlazeBSD licensehttp://bleyer.org/pacoblaze/Apache licensehttps://github.com/krabo0om/pauloBlaze/Bingo

author: bingo600
author_rank: Super Contributor
timestamp: October 10, 2016, 04:56:36 pm
content: Quote from: legacy on October 10, 2016, 04:47:32 pmAnd that makes gcc=crap ??/Bingo

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 05:13:56 pm
content: Quote from: ataradov on October 10, 2016, 03:33:00 pmare you really sure ?I did, for HPPA/PA2, when I tested gcc in the v4.1.* eraI remember when I found bugs(1), sent emails etc etcfrankly, it was when I discovered that gcc is all crapand my conclusion is that supporting GCC or GNUsubtracts effort to other projects (e.g. to LLVM)also, GNU has the effect of making UNUX brokene.g. the GNU "tar" adds a lot of entropy and it's not compatiblewith anything in the UNIX world (e.g. with IRIX)you might be shocked when you see a tape's content completly distroyedbecasue the tarbal was done with UNUX tar, and GNU tar has "improved"it's not irrelevant, I guess(1) one of those was interesting, since it had made the "conditional branch"like the randomly launch of the coin, where you have the 50% of probabilityto take the correct branch, and the 50% of probability to cause a crashit happened under the -O2 flags, and … we got a disaster inCatalyst(gentoo builder, stage1: consistently bad in quality, not able to be trusted)

author: ataradov
author_rank: Super Contributor
timestamp: October 10, 2016, 05:29:00 pm
content: Quote from: legacy on October 10, 2016, 05:13:56 pmI'm not saying that GCC is beautiful on the inside. I agree that Clang/LLVM is way better. But it also consistently generates lower performing code. This will change of course, but that the moment is the fact.It is like complaining about x86. Yes, it is complicated and bloated, but it is also the highest performance thing we have and we need to live with that, not just close our eyes because we don't like it.You can bash GNU all you like, but the fact is, they have working tools, you have lots cool proposals on forums.

author: ataradov
author_rank: Super Contributor
timestamp: October 10, 2016, 05:35:50 pm
content: Quote from: legacy on October 10, 2016, 05:32:05 pmIf we want to have discussion at that level, then your architecture is also crap.

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 05:41:09 pm
content: Quote from: legacy on October 10, 2016, 04:46:04 pmQuoteok

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 05:47:09 pm
content: Quote from: ataradov on October 10, 2016, 05:35:50 pmwhich level?this topic is not willing to talk about GCCplease stop to annoy!

author: bingo600
author_rank: Super Contributor
timestamp: October 10, 2016, 06:09:30 pm
content: Kaplonk

author: C
author_rank: Super Contributor
timestamp: October 10, 2016, 06:30:51 pm
content: Quote from: legacy on October 10, 2016, 04:38:12 pmYou can do a work around for almost anything.Take you MIPS and work out the instructions to do some adds 4 x built in size and see what you get;====================You could think of "Address" in your instruction set as a relative address. When code needs to jump further then this you can add a bounce jump block in code.

author: nctnico
author_rank: Super Contributor
timestamp: October 10, 2016, 07:05:56 pm
content: Quote from: legacy on October 10, 2016, 05:47:09 pmThere is no use to create a (popular) softcore if there is no GCC support for it. IMHO it would be nice if there where a good 16 bit softcore with GCC support. I think a lot of people will want to use it in their FPGA designs. The best bet is to emulate a popular CPU core for which a good (=strong optimisation) compiler is available because the memory available in an FPGA isn't very large.

author: legacy
author_rank: Super Contributor
timestamp: October 10, 2016, 07:17:39 pm
content: Quote from: nctnico on October 10, 2016, 07:05:56 pmcorollary: discussing these things in this forum is definitely a waste of timeI pass, guys

author: ataradov
author_rank: Super Contributor
timestamp: October 10, 2016, 08:05:40 pm
content: Quote from: legacy on October 10, 2016, 07:17:39 pmObviously. People want real compilers, not assemblers made in two days. No matter how many softcores you invent, people will still need proper tools.If something takes two days to make, it will be made in-house for a specific project.

author: legacy
author_rank: Super Contributor
timestamp: October 11, 2016, 09:01:42 am
content: Quote from: ataradov on October 10, 2016, 08:05:40 pmpeople who?for sure people like *you*, who completely misses that we were here to discussadvices, tips and tricks for a personal projectwho has ever said that I want to replace a common architecture?who has ever said that it must be the best ever?all bullshits!so why should I beobligedto support gcc? for who? you? do you pay me?if you ever passed an university oral examination , you should know thatthe C compiler is irrelevant when you talk about "architectures"the C language is itself irrelevant, and machines like 68HC11 must be programmed in assemblyin the computer hystory we also have examplesRISCOS (ARM) was written in assembly, AmigaOS classic (m68k) was written in assemblyso? do you believe they had a C compiler? sure, after a while Acorn did her own C compilerwhich is much more beautiful, productive, and comfortable than gcc, but it's not the pointtherefore arguing that you will ignore an architecture because there is no C compileris like saying you are one of those clueless who don't understand nerither a bit nor a bytein computer science, and, even worse, along with the theory, you seem to fail the practiceif you are not a no-gooder, then you are able to write your own supportinstead of annoying people because of that f*cking gccwhich no, it's not irrelevant, it's my f*cking free time, *I* decide how to spend itI have decided to make my own Compileralso, supporting your stupid thesis, you are also claiming that people in OpenCoresare *all morons?* because their soft cores do not support gcc (along with no C support)and the don't come with a C compiler, just an assembler made in two working daysso what? does it make sense? do you understand how stupid it is ?and, still worse, how annoying is to hear all of these bullshits all the time?frankly dude …

author: legacy
author_rank: Super Contributor
timestamp: October 11, 2016, 09:05:24 am
content: Quote from: nctnico on October 10, 2016, 07:05:56 pmwhy don't *YOU* make it ?are *YOU* able? will *YOU* make it for free?even if it will take a lot of effort?even if it's *YOUR* free time?even if having to deal with gcc in *YOUR* free time is a masochistic experience?so, shut up

author: Scrts
author_rank: Frequent Contributor
timestamp: October 11, 2016, 02:03:24 pm
content: Not sure why you should take all those posts so seriously. Relax. People always try to discourage good ideas and this will happen all the time.I've seen good projects where something was made from scratch, completely custom, open source and released to the world as a very good quality design. I'd say go for what you dream of.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: October 11, 2016, 02:44:59 pm
content: Too bad this is 'closed'.I had an idea to make a bit-sliced FPGA softcore but I totally lack the knowledge to think that through. I don't even know if my idea is possible. So any discussion on something similar (by the looks of it) would be interesting to me.So please ignore the "you have to serve the world and support a c compiler" remarks and continue...I would love to hear what else you can say about designing your own softcores...

author: ataradov
author_rank: Super Contributor
timestamp: October 11, 2016, 03:14:22 pm
content: Quote from: legacy on October 11, 2016, 09:01:42 amPeople in this thread. People, who actually decided to give any input at ll.Quote from: legacy on October 11, 2016, 09:01:42 amEven more so. I can tolerate writing something in assembly for work, since I'm being paid to do so. I won't program in assembly for a hobby. I also don't care about closed nature of things, since for a hobby I stick with one FPGA vendor and their tools. I also don't care if NIOS II is not the most optimal solution, but again for a hobby, I don't care, I'll take a bigger FPGA, I'm not making 100K of those device and $20 price difference is not a factor.Quote from: legacy on October 11, 2016, 09:01:42 amNot for me, but for me even to consider using this thing.Quote from: legacy on October 11, 2016, 09:01:42 amPositions of bits in opcodes are even more irrelevant, compilers and assemblers hide all of this.And you actually have not said a word about architecture. How does the pipeline look like? How does this interact with the world?If this is a replacement or close analog of PicoBlaze, there must be dedicated instructions and I/Os for a fast manipulation of inputs.So far you have proposed instruction set that looks exactly like 1000s o others and nothing new or particularly interesting.

author: ataradov
author_rank: Super Contributor
timestamp: October 11, 2016, 03:18:30 pm
content: Quote from: Scrts on October 11, 2016, 02:03:24 pmBut people often want to encourage silly things, just because. There must be a balance.Quote from: Scrts on October 11, 2016, 02:03:24 pmI've also seen a ton of abandoned projects just like that on OpenCores. CPUs there is the most popular category. But they basically get abandoned as soon as author gets tired of realities of supporting a thing like that.

author: helius
author_rank: Super Contributor
timestamp: October 11, 2016, 03:27:58 pm
content: Quote from: ataradov on October 11, 2016, 03:14:22 pmI wasn't going to reply to this thread, as it doesn't interest me, but this remark is just too silly.Compilers and assemblers do not "hide" the costs of implementing logic in hardware. A more flagrant category error cannot even be imagined.

author: ataradov
author_rank: Super Contributor
timestamp: October 11, 2016, 03:52:11 pm
content: Quote from: helius on October 11, 2016, 03:27:58 pmWell, they do hide the actual cost. But I get what you are saying. This particular proposed instruction set is nothing new, it is basically MIPS I shrunk down a bit to fit into BRAMs. Compilers know how to deal with that reasonably well.

author: nctnico
author_rank: Super Contributor
timestamp: October 11, 2016, 03:58:31 pm
content: Quote from: legacy on October 11, 2016, 09:05:24 amIf you mimic an existing core (which doesn't mean it has to execute instructions within the same number of clock ticks) you don't have to deal with the internals of GCC but you can use GCC out of the box. IMHO what kills so many CPU cores on OpenCores is the lack of good software tools to support them.

author: ataradov
author_rank: Super Contributor
timestamp: October 11, 2016, 04:00:24 pm
content: Quote from: nctnico on October 11, 2016, 03:58:31 pmIt is fun to create cores. Not so fun to make and support tools.

author: Kalvin
author_rank: Super Contributor
timestamp: October 11, 2016, 04:10:25 pm
content: Quote from: nctnico on October 11, 2016, 03:58:31 pmIndeed. Create a small softcore and write an x86 emulator (or an emulator for any of the supported targets listed inhttps://gcc.gnu.org/backends.html) in assembler, and you will have a support for a GCC compiler

author: Kalvin
author_rank: Super Contributor
timestamp: October 12, 2016, 12:21:01 pm
content: Although my previous post above was meant to be a somewhat humorous, it does contain a grain of reality: Once upon a time there was a project which targeted the GCC for the JVM (You know, compile once, run and debug everywhere) . The concept would have been just great as you could use the all GCC languages and libraries (C, C++, Ada, FORTRAN, Modula, just name it) and make it run on the JVM along with the Java. However, for some reason, the project was abandoned until it was resurrected a few years ago.The new concept took a different route: Instead of targeting the GCC to output directly JVM byte code, the GCC produced output for the existing MIPS architecture. The resulting MIPS assembly code was then converted to JVM byte code. Quite a clever approach. For more information:http://www.xwt.org/mips2java/In a similar fashion, one could enable the GCC support for a custom softcore: Just make the GCC to emit the output for a suitable architecture, and the run the output through a source-to-source translator generating the assembly code for the custom softcore. The code efficiency and ease of porting depends of course how well the custom architecture reflects the GCC target architecture.The concept can be used with other compilers like Keil, LLVM, etc., too.

author: rstofer
author_rank: Super Contributor
timestamp: October 12, 2016, 01:33:01 pm
content: Quote from: Kalvin on October 12, 2016, 12:21:01 pmThat is a very clever idea! Target a similar architecture and then manipulate the assembly language output for the new architecture.

author: legacy
author_rank: Super Contributor
timestamp: October 12, 2016, 01:37:52 pm
content: Quote from: nctnico on October 11, 2016, 03:58:31 pmdude, we did some mimic of the MC6809, retargeting gcc took three yearsmemories, some very bad experiences with GNU, something I won't repeat for hobby, for sureif you do something in fpga, you do it to do something interestinge.g.Arise-v2makes the assembly programming like a piece of cakeand could be used to teach computer science in schoolsits complexity and elegance might make the learning curve easierand at least its integrated debugger engine is comfortablep.s.have you ever heard about ijvm32? (i=integer stack machine)it's a didactical machine invented by Andrew Stuart Tanenbaumdescribed in his book and to be programmed in assemblyI passed two examinations in a UK Computer Science Campand they used that strange machine in ~2001-2002

author: nctnico
author_rank: Super Contributor
timestamp: October 12, 2016, 02:47:19 pm
content: Quote from: legacy on October 12, 2016, 01:37:52 pmOfcourse you take a core which already has good support in GCC otherwise there is no benefit of using an existing toolchain@Kalvin:I like your translation idea. The problem with many CPUs is that they tend to do things which don't scale well in an FPGA (like push/pop on a stack and calling subroutines). One solution could be to translate the instructions into single cycle microcode which is then executed inside the FPGA. This process would need to keep track of jumps though so it is not that simple.

author: legacy
author_rank: Super Contributor
timestamp: October 12, 2016, 03:13:11 pm
content: Quote from: Kalvin on October 12, 2016, 12:21:01 pmhow many times should you repeat GCC in a sentence?in this topic?

author: Kalvin
author_rank: Super Contributor
timestamp: October 12, 2016, 03:14:27 pm
content: Quote from: nctnico on October 12, 2016, 02:47:19 pmPush and pop instructions may or may not implemented directly by the softcore or they need to be simulated using indirect register writes and increment/decrement. Also the support for the subroutines may or may not implemented in the instruction set or they need to be simulated. The current FPGA devices have qute a fair amount of built-in RAM, so implementing the stack should not be too problematic.Even if the stack is not implemented in hardware / instruction set and the CPU has lots or registers, one of the registers can be dedicate to be a stack pointer. The translator will then perform necessary indirect register writings and readings with needed register increment/decrement in order to simulate the stack push and pop operations.The subroutine calls can be simulated for example as follows: The subroutine parameters are pushed to the stack along with the return address, and a JMP #address instruction is executed to the specific subroutine address. The subroutine return can be simulated as follows: the return address is popped into a register and a JMP register is executed.The simulated instructions will consume some memory of course, but the simulated instructions may help keeping the instruction set simple and implementation straightforward. If the FPGA has lots of resources available, then a straightforward VLIW instruction set may be a useful as it will typically map into hardware quite easily.

author: Kalvin
author_rank: Super Contributor
timestamp: October 12, 2016, 03:17:30 pm
content: Quote from: legacy on October 12, 2016, 03:13:11 pmYou can substitute the GCC with something else like LLVM or Keil if you will. The GCC was used only as a generic term for a compiler and the toolchain.

author: legacy
author_rank: Super Contributor
timestamp: October 12, 2016, 03:26:57 pm
content: Quote from: nctnico on October 12, 2016, 02:47:19 pmsomething similar was done byDallas Semiconductoraround 1999-2001they had developed aTini-Java platformimplemented on the top of theirM80C390(intel i51 architecture compatibile)so, the common used java compiler was able to compile your sourcesand once omitted java-assembly (java language-> assembly)then their "jump'51"(1) took its place along the convertionof the java assembly (stack machine) into i51 assemblyat the end of the process, you obtained a native-binary,to be loaded into the tini-machineit sounded like a good idea, it was not(1) it was itself a java programto be executed by the JVM on the hoste.g. on linux, windows, macOSX

author: Kalvin
author_rank: Super Contributor
timestamp: October 12, 2016, 03:46:30 pm
content: Just use a single instruction set architecture which uses only a single assembly instruction: movehttps://en.wikipedia.org/wiki/One_instruction_set_computer#Transport_triggered_architecture. The assembler, the disassembler and the debugger will be quite simple to write.

author: C
author_rank: Super Contributor
timestamp: October 13, 2016, 01:42:06 am
content: legacyYou know one size does not fit all.From what I see most compilers lack information needed at times.In programming it is not unusual to work around a problem.Start your compiler with BITAn integer then becomes an array of bit.The logic instructions become logic of array of bit.The code gen part then can look at is what is need the size_wise to do directly or if code needed to fit to what can be done directly.The compiler can get the job done and give a warning when extra code was used.This adds requirement of where the array of bit is located in a register or memory.You gain when there is offsets by the compiler having more ways to do task.When you define a structure for the PDP11 instruction set which is mostly octal in a 16-bit word. The compiler can now make a choice of use bits in current location in word or shift to 0. You no longer write code to mask & shift the register & mode field of a two register instruction in program as the smart compiler can do it. Dumb smart compiler will function and as compiler gets smarter, your program gains speed with out source change.You also need the concept of Unknown, 0 or more. The Dumb smart compiler knows one way to work above while the smart compiler knows two or more ways.Keep in mind what is hidden in compile process. When you add modules to pascal, you need to generate initialization code. This same list can be used to had to the compiler. You could have a module for each keyword of language. You could have a module to handle pascal's "program" keyword & one to handle module it's self. If you want to add the concept of Class, add some modules. Events, Add more modules.Oberon's ebnf has fewer rules than pascal and at the same time is more powerful. name.name.name.name...(type,var,function,proc) is allowed.You know about SYSTEM module.You are setting the rules, you could use COMPILER.MODULE.List in a program. or COMPILER.PROGRAM.MODULE.ListThe editor can shift from unknown to program editor, module editor, class editor.Unknown, 0 or more

author: helius
author_rank: Super Contributor
timestamp: October 13, 2016, 09:09:32 am
content: GCC (like some other FSF projects like Emacs) is burdened with a high technical debt. Anyone adding enhancements is therefore starting from negative territory on a cost/benefit curve.