hybridfree/eevblog-posts huggingface dataset:
Detect Protocol on bus - Page 1
Forum section: electronics / general

author: LittleRain
author_rank: Contributor
timestamp: October 05, 2019, 02:02:14 am
content: Just got my first CPLD, the Altera Max II.I was wondering if it would be possible to detect a protocol on a bus, not necessarily for the max II, just in general.What I want to do, is add a micro USB port to my board, and use custom cables that plug into different devices with different protocols.One device would be a regular PC, and use regular USB.Then another device uses SPI, another using 1 wire, and possibly some other protocols, not at the same time of course.What I want the CPLD to do, is to detect what protocol it is, and then forward the signal to the correct pins on a micro controller.The device is hand held, and doesn't have the room to have separate ports for each protocol.Is this possible, and how would I go about getting started on something like this?Thanks

author: rjp
author_rank: Regular Contributor
timestamp: October 05, 2019, 02:05:49 am
content: sounds like a digital logic analyzer ?if you dont want to take on the hardware and the software, learning how to drivehttps://sigrok.org/would probably be a start, you get lots of protocol decoders for free.--misread requirement, sorry.

author: LittleRain
author_rank: Contributor
timestamp: October 05, 2019, 02:18:28 am
content: Not quite, I already have a logic analyzer actually.Sorry I should have been a little more specific, once it finds out which protocol, I need my device to start talking to the PC/device on said protocol.I basically want to squish a few devices I have made, and am currently working on, into 1 device.

author: senso
author_rank: Frequent Contributor
timestamp: October 13, 2019, 09:13:03 pm
content: Use a pin, or a couple to give an ID to each cable, now it just knows the protocol based on the cable that is plugged in.Or just use a couple positions/connectors, and each position is one protocol.

author: LittleRain
author_rank: Contributor
timestamp: October 16, 2019, 04:38:43 am
content: I was thinking about doing that, but I'd have to use USB C to get enough pins for each ID, and unfortunately I'd have to do the same for the position based approach.But if it is cost effective compared to a CPLD I may as well go that route. Big problem is, if the consumer uses a regular USB C cable, power could be sent to another buses pins.I'll look into it further though, thanks.

author: TomS_
author_rank: Frequent Contributor
timestamp: October 23, 2019, 08:50:48 am
content: Quote from: LittleRain on October 16, 2019, 04:38:43 amWhat about a multi-way IDC header/connector?Or perhaps a smaller connector, even USB type A, but hook various resistor values up to one pin and use an ADC or some opamps to detect various voltages created by a resistor divider, with each voltage corresponding to a different protocol?

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: October 23, 2019, 07:07:39 pm
content: I2C EEPROMs are available in SOT23-5 packages.
Tools for programming 16V8 GAL - Page 1
Forum section: electronics / general

author: perdrix
author_rank: Frequent Contributor
timestamp: September 20, 2019, 05:57:44 pm
content: OK I know about WinCUPL, but this isn't C or anything like, and I'd like to be able to use Schematic entry which the MicroChip version doesn't seem to support.If there's a version out there that does allow schematic entry please point me to the DL location.Are there any tools out there that will allow me to do schematic entry for programming the 16V8 and also use VHDL which seems easier for me to understand then CUPL.ThanksDavid

author: oPossum
author_rank: Super Contributor
timestamp: September 20, 2019, 06:03:37 pm
content: Schematic and VHDL for GALshttp://www.latticesemi.com/ispleverclassic

author: perdrix
author_rank: Frequent Contributor
timestamp: September 23, 2019, 03:09:37 am
content: Thank you, I'll give it a try, but have a nasty suspicion it will only support Lattice parts.D.

author: james_s
author_rank: Super Contributor
timestamp: September 23, 2019, 04:44:11 am
content: Schematic entry is a waste of time, it's just a gimmick that is used to impress people at trade shows. Take the time to learn enough HDL and you'll save a lot of time in the long run. The logic you'd be putting in a little GAL like that is going to be pretty trivial.

author: amspire
author_rank: Super Contributor
timestamp: September 23, 2019, 05:14:48 am
content: Quote from: james_s on September 23, 2019, 04:44:11 amI totally agree with James. These devices are so simple that you basically need to use code that directly specifies how the device will be configured. When I have programmed devices like this, I could literally list the state that will be needed for every programmable link. They are not like the bigger chips that need routing.Also many of these devices use a lot of power. If you are used to microcontrollers running off 5mA, these are in another league. 75mA or 45mA before you even look at switching power losses. Since the chips are so simple, designs often need several chips and that makes the power dissipation worse. Forget it for battery operation. I would really advise you look for some more recent cmos based chips that uses near zero power in a static mode.

author: TomS_
author_rank: Frequent Contributor
timestamp: October 23, 2019, 08:57:50 am
content: I dont find WinCUPL to be all that bad. Well, CUPL the language isnt too bad, but WinCUPL the software has some quirks that take some time to get used to...I like CUPL because youre basically writing the logic that will be implemented in almost the most direct form possible. Its like assembly language for logic devices. Maybe Im just weird like that.A GAL is so simple that to define your logic in schematic would probably end up taking longer than writing a few equations in CUPL. Take the time to learn it (some kind of HDL whether CUPL for GAL or one of the Vs for CPLD/FPGA), if you ever end up having to work with this stuff in the real world you probably wont be working with schematics.
Unspecified I/O standard in vivado when trying to set AXI gpio to 1 bit width - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: October 06, 2019, 03:18:54 am
content: Hi alltrying to set my axi gpio blocks to 1 bit each but got this message when generating bitstream.[DRC NSTD-1] Unspecified I/O Standard: 5 out of 135 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: io5_tri_o, LED4_tri_o, LED1_tri_o, switch_tri_i, and BTN1_tri_i.I don't even have these ports in my axi gpio when I click on it.here is my block diagram and constraints file:Code:##switchset_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { switch }];##led4set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { LED4 }];##led1set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { LED1 }];##BTN1set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { BTN1 }];##io5set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { io5 }];

author: asmi
author_rank: Super Contributor
timestamp: October 06, 2019, 03:59:31 am
content: That's because these ports are always arrays (even if they contain only single wire - [0:0]), so your constraints need to be something like this:set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { switch }];Moreover, you didn't specify port directions in your GPIO IPs, hence all ports are exported as tristate (this is where suffix _tri comes from in the port name). Small hint - if you open the wrapper file, you will see actual port names as they need to appear in constraints file.Fix these things, and it should be good to go.
10 level logic in VHDL (for simulation only) - Page 1
Forum section: electronics / general

author: SSL
author_rank: Newbie
timestamp: October 03, 2019, 10:11:01 pm
content: Hi,I'm taking a class in numerical numerical methods and we have an assignment on floating-point arithmetic.I thought it might be fun to implement this in VHDL.But the assignment require us to use FP numbers with base10 instead for of base2Is there any way to implement logic in VHDL with 10 logic levels instead the normal 2?I don't care if it will never synthesize, but for simulation I can't see any reasons for it not being possible? I just can't find any types or methods that will support 10 level logic - is it possible? If, how?

author: Bassman59
author_rank: Super Contributor
timestamp: October 03, 2019, 11:11:52 pm
content: Quote from: SSL on October 03, 2019, 10:11:01 pmVHDL has long supported therealtype. It's generally not synthesizable but for simulation purposes it's used all the time.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 03, 2019, 11:50:24 pm
content: Well, I guess the OP still wants to implement FP arithmetic "from scratch", and not use a FP type? (Otherwise I wouldn't see the point of this assignment?)The OP's not completely full clear, but from what I understand, they want to implement FP in base 10? I don't really see the problem. Doing this even with very low-level logic. The OP may not have heard of BCD.In very short: encode each digit with 4 bits (only using the 0-9 values obviously). The rest is up to you.

author: SSL
author_rank: Newbie
timestamp: October 04, 2019, 12:17:59 am
content: Quote from: SiliconWizard on October 03, 2019, 11:50:24 pmCorrect. It must be implemented from scratch so a FP type is not an option.Quote from: SiliconWizard on October 03, 2019, 11:50:24 pmI think you understood the assignment correctly.I have heard of BCD and used it previously. But only to print my internal binary values in a more human friendly form on a 7-segment or some other type of display.Using BCD to work with base10 numbers in base2 in this context haven't crossed my mind.Thank you very much!
Lattice Mach XO2 - Unable to simulate reading TraceID through Wishbone - Page 1
Forum section: electronics / general

author: bsccara
author_rank: Contributor
timestamp: September 20, 2019, 03:21:04 pm
content: I need to read the TraceID from inside the fabric, using the Wishbone interface and the EFB. According to my understanding the Wishbone master has to do a write cycle to register 0x70, setting it to 0x80 to open the connection, followed by four write cycles to register 0x71 for the 'Read TraceID Code' command, setting it to 0x19, 0x00, 0x00, 0x00. After this eight read cycles from register 0x73 should provide the data.I've implemented the master but in simulation with Active-HDL 10.3 the first cycle looks OK but on all other the 'wb_ack_o' signal goes high as soon as the master drives the 'wb_stb_i' signal high. Originally the master did the cycles back to back but I've since changed the master to insert a long delay between each cycle and again changed the master to keep the 'wb_cyc_i' signal high during the whole sequence but to no avail. On the EFB instantiation, done with IPExpress, I've tested with 'User Flash Memory' both selected and unselected. The 'wb_clk_i' signal is driven from the internal oscillator, at 88.67 MHz.So it seems the Wishbone slave on the EFB gets confused after the first write cycle, but why?P.S. I've attached a picture of the signals on the simulation; the blue line crosses the first write cycle and the red the second one. The second picture is from Lattice's TN1246 and has an example of reading the UserCode, which is quite similar to what I want to do.

author: bsccara
author_rank: Contributor
timestamp: September 21, 2019, 11:43:28 am
content: More strangeness... According to the attached paragraph from page 7 of the TN1246 for the simulation to work properly the 'wb_cyc_i' and 'wb_stb_i' signals need to have their assignment delayed by 100ps. Doing that the simulation now appears as shown; the 'wb_ack_o' signal is now driven by the slave some time after (first write cycle) or on (other cycles) the second clock transition. The discrepancy doesn't fill me with confidence on the correctness of the simulation but it seems to be an improvement.The paragraph also states that those signals should be deasserted immediately on 'wb_ack_o' assertion, which I took to mean that combinatorial logic was needed to short the signals low. But alas if I do that combined with the delayed assignment all these signals enter into a fast oscillation (in the GHz range) until the next clock transition. Go figure...Regardless I'm getting all zeros as TraceID, which I'm not too sure is correct for the simulation. Guess I'll try using Reveal to debug on the actual FPGA.
Lattice Mach XO2 - Reading UFM flash - Page 1
Forum section: electronics / general

author: Axk
author_rank: Regular Contributor
timestamp: September 19, 2019, 07:01:11 pm
content: I'm debugging my sample design to write/read one page of data to/from UFM flash in Lattice LCMXO2-1200HC.It always returns all 0xFF s when reading with the 0xCA command.I've specified an initialization binary file for user flash memory in the UFM IPExpress wizard filling all 511 pages with 0xCB bytes and it does show up during synthesis but it still reads all 0xFFs.So I suppose something's wrong with how I'm reading it.I'm following the examples in TN1246 "Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide" dated November 2016.I've put the design through simulation and it appears to be fine.I've also did a basic check on with an oscilloscope of the wishbone enable/write enable/acknowledge signals and it looks good - wishbone does acknowledge writes/reads and it does return the status register with the busy flag set after write for some 100+ microseconds.It may be a basic error on my part, but I wonder if anyone has experience with reading UFM flash on Lattice MachXO2 devices via Wishbone and can share what instructions they follow to implement the protocol.

author: Axk
author_rank: Regular Contributor
timestamp: September 19, 2019, 09:06:20 pm
content: The issue in my case was that my clock is 50MHz and it needs a 200ns (I've added 400ns for now) delay between the read command (0xCA) and it's first operand (0x00).TN1246 is a bit confusing in this regard, it does mention the delay:QuoteBecause it is talking about "inserting WB wait states" I initially thought that it would handle it automatically by deferring the wb_ack_o signal for as long as it needs.But the oscilloscope shows that it doesn't deffer wb_ack_o.So I had to "manually" insert a delay and it fixed the issue, now my UFM read/erase/write sequence is working as expected.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 19, 2019, 09:12:52 pm
content: OK, thanks for sharing the experience.
Implementing D-type latch with ATF16V8CZ - Page 1
Forum section: electronics / general

author: Ketturi
author_rank: Regular Contributor
timestamp: September 19, 2019, 01:25:53 pm
content: I am converting memory glue logic to PLD to simplify board layout and lessen the chips and power needed. Logic is fairly simple consisting from nand and and gates, but it does contain 5-bit D-type latch which is used as memory segment register:.Replacing logic with single ATF16V8CZ GAL would result following schematic:.I came up with following CUPL code. And of course it would not work as 16v8 GALs only can use pin 1 as a clock input in registered mode, so I can't use build in latch functionality. Is there any way to implement that in this PLD family? I'm bit stuck with this as I have ~zero experience in CUPL coding and PLDs.Code:/* *************** INPUT PINS *********************/PIN 2 = !SS; /* Slot select signal, active low */PIN 3 = !OE; /* Output enable, active low */PIN 4 = MR; /* Memory counter reset, active high */PIN 5 = D0; /* Data lines for address register */PIN 6 = D1;PIN 7 = D2;PIN 8 = D3;PIN 9 = D4;/* *************** OUTPUT PINS *********************/PIN 12 = A18; /* Address register outputs */PIN 13 = A17;PIN 14 = A16;PIN 15 = A15;PIN 16 = A14;PIN 17 = HWID; /* Hardware ID, open collector, active high */PIN 18 = !WE; /* Write enable, active low */PIN 19 = !CS; /* Chip select, active low */WE = !OE; /* WE is low when OE is high */!CS = !MR & SS; /* CS is low when MR and SS are low */HWID = (WE & SS) & MR; /* HWID is high when MR, SS and WE are high *//* REGSEL clocks when MR and OE are high and SS goes low /*/* 5-bit latch */A14.l = D0;A15.l = D1;A16.l = D2;A17.l = D3;A18.l = D4;[A14, A15, A16, A17, A18].le = (!OE & MR) & SS;

author: up8051
author_rank: Frequent Contributor
timestamp: September 19, 2019, 02:21:55 pm
content: Use ATF22V10, 16V8 don't have enough resources.CPLD like PAL/GAL/ATF 16V8/20V8 are not suitable for low power devices (ICC=30mA at 5MHz, ICC=60mA at 10MHz)For low power design I used PEEL18CV8ZP, nowv obsolete but I have some stock (ICC=2mA at 1MHZ).In PEEL18CV8ZP pin1 and 11 can be used as normal inputs, clock for latches can be sourced from internal logic.

author: Ketturi
author_rank: Regular Contributor
timestamp: September 19, 2019, 06:22:55 pm
content: Memory device is used as NV storage device and is driven from MCU i/o port and not from system bus (which would be clocked at 3MHz) so far more important factor would be static standby current than active current. Power budget for active memory device is 70mA. When not powered from device, memory circuitry is fed from 3V coin cell, so standby current should be measured in micro amps.Even ATF22V10 does not allow to clock output logic from internal logic, so I would need to connect one output to clock input pin, that seems like bit kludge.
Intel\Altera EP53F8QI Short to GND Fault - Page 1
Forum section: electronics / general

author: shmueld
author_rank: Newbie
timestamp: September 12, 2019, 11:52:58 am
content: We have a design with an EP53F8QI that multiple ICs have been burned both at room temperature and +80 °.C. We are using it to create a +3.3V and on fault we have found that the +3.3V supply is shorted to GND. We have checked all the capacitors and resistors and they are according to the spec outlined in the data sheet. The only thing we could found is that the GND plane was not routed directly underneath the layer on which the IC was placed much further into the PCB.Is there someone who can help me with this issue ?

author: Daixiwen
author_rank: Frequent Contributor
timestamp: September 13, 2019, 06:56:02 am
content: We are using the similar EP53A8HQI on several designs but never had this problem.Are you sure it's coming from the DC/DC converter and not another chip connected to the 3.3V supply? If you desolder the converter, is the fault still there?How and when are they exactly burning? Is it all of your products, or just come of them? Does it happen at first power up, of after a while? Is there anything specific happening on the board at the time they burn?I don't think having the ground plane several layers down is the reason for your problem. It won't make such a big difference. Could you show the PCB layout around the converter?
How to config the AD9517-3 registers(fine delay ) to produced 180-degrees output - Page 1
Forum section: electronics / general

author: javad2040
author_rank: Contributor
timestamp: September 11, 2019, 05:12:38 pm
content: hello guys.I design the processing board that contains the AD9517-3, tow AD9643, and Kintex-7 FPGA.The AD9517-3 LVDS outputs directly connected to AD9643 input_clk and FPGA HP banks; tow AD9643 ADCs works with 250 Mhz that AD9517-3 drives them. The ADCs work correctly but I want to set one ADC works with 0-degree and another by 180-degrees input_clk.According to the AD9517-3 datasheet, fine delay block must be added to the LVDS output that output shifted to 180-degree,please help me to config the AD9517-3 registers to LVDS fine Delay that 180-degrees produced.best regards,
CPLD divide by 1.5 50% duty cycle - Page 1
Forum section: electronics / general

author: perdrix
author_rank: Frequent Contributor
timestamp: September 19, 2019, 12:17:53 pm
content: OK all you CPLD mavens, I have a problem for which a CPLD is possibly a solution.I need a physically small device with low pin count, VSSOP or TSSOP, and I want to convert a 15MHz input signal to 10MHz 50% duty cycle output.So probably a divide by 3 with 50% duty cycle and a doubler, but there's likely a better way?Initially I was thinking ATF16V8BQL-15XU, but that has more inputs and outputs than I really need.I have no previous experience of programming these beasts and only know of the tools by name (e.g. WinCUPL).ThanksDavid

author: artag
author_rank: Super Contributor
timestamp: September 19, 2019, 01:30:43 pm
content: Rather than divide by 3 and multiply by 2, you probably want to multiply by two (delay and XOR) then divide by 3. Though you'll still end up with a mark-space ratio that's influenced by the difference between low-to-high propagation delay and high-to-low propagation delay, and the width of the doubler's delay.Is that important ? It might be adjustable by messing with the offset of the input slicer, but I guess that will add some jitter.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 19, 2019, 02:27:51 pm
content: 15 MHz to 10 MHz with 50% duty cycle is no possible with just logic. This would be more like something for a PLL, or maybe a synchronization of a 10 MHz oscillator.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 19, 2019, 03:02:08 pm
content: Agree, if all you need your CPLD to do here is generate this clock output, use a specialized PLL IC. There are many out there.If the CPLD could implement additional logic functions, then you could select a small FPGA instead (like in the Lattice iCE40/MachXO2/XO3 series, and there are similar small ones with other vendors), with a minimum number of logic cells, and just one embedded PLL. Cost would be pretty low. You'd use the embedded PLL for your clock output, and the available logic cells for anything else you might need now or in the future.

author: daqq
author_rank: Super Contributor
timestamp: September 20, 2019, 08:26:42 pm
content: Well, the simplest/smallest solution might actually be an MCU. STM has a fair amount of small cheap ARMs. You could use for instance the STM32L011 in any of the packages (3x3mm QFN or the TSSOP14 package). The device acccepts a logic signal as a clock input, use the internal PLL to convert it to your desired freq and enable the master clock output, which will output the generated clock. Cheaper and simpler than a CPLD/FPGA, just add a cap or two.
Should a new EPM3064A be 'blank'? - Page 1
Forum section: electronics / general

author: Illusionist
author_rank: Regular Contributor
timestamp: August 20, 2019, 03:42:30 pm
content: I got some 'new/old stock' EPM3064A CPLDs from China... possibly dodgy, I know, but at £1 each it was worth a punt for a hobbyist. They came in a cut off piece of a large antistatic tray and look new.The Quartus II programmer identifies them OK, but they fail a blank check. Should new/unused devices pass?Since I've never bought a new CPLD from a real supplier, I don't know if they should pass or if there is some 'manufacturing configuration' on them or something.The one I tested programmed and functioned OK, but I'm concerned about using one in a project in case it proves to have a fault due to being a pull. If they are pulls I'll put in a claim.At least the jtag pins weren't reassigned like the load of used 7128s I once bought (thank The Great Prophet Zarquon for access to a master programmer!)

author: Mr. Scram
author_rank: Super Contributor
timestamp: August 20, 2019, 03:47:07 pm
content: Always assume anything from unofficial sources are counterfeits or pulls. It'd be naive to think you can get this kind of kit through dodgy channels and get pristine new chips.

author: Illusionist
author_rank: Regular Contributor
timestamp: August 20, 2019, 04:04:21 pm
content: I know, but they could also be exactly what was advertised. Those chips have been around for long enough. If they are pulls, they've been cleaned up remarkably well because I can't tell.My question remains...

author: rstofer
author_rank: Super Contributor
timestamp: August 28, 2019, 07:40:58 pm
content: For the hobbyist, what difference does it make? Does it function? Does it do what you want? Then, it's fine. Just don't try to market anything with floor sweepings from China.

author: Illusionist
author_rank: Regular Contributor
timestamp: August 28, 2019, 11:39:16 pm
content: It matters because as I said in my OP:"I'm concerned about using one in a project in case it proves to have a fault due to being a pull."Until it's soldered onto a board, I won't know if it functions properly. Then I'm left trying to repair a board if it doesn't.Anyway, I pointed out the fact to the seller, who immediately issued a refund with no further comments. I guess that answered my question.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 06, 2019, 04:11:13 pm
content: Even if they are "new old stock" it is possible they are from a production overstock in which case they could easily have been factory programmed but never assembled. There is no way to tell.I honestly wouldn't let the existence of a pre-existing image sway me. If I was willing to take a chance on a $1 part from a dodgy seller I would go ahead and try anyway. If I were that concerned about soldering it onto a board and finding it non-functional I would be buying parts from an authorized distributor in the first place.
problem with LVDS Oscillator on Zynq borad !!!!!!! - Page 1
Forum section: electronics / general

author: javad2040
author_rank: Contributor
timestamp: August 13, 2019, 02:03:50 pm
content: hello guys,I designed the zynq (Z030) board that 3 LVDS oscillators is connected to HP & HR banks of it. Two oscillator has 200 Mhz that works properly(i use DCMs of FPGA that oscillators connected to input of them and multiple Frequency signals produced by it), i defined Counter that counting by F=300MHz (DCM output) and the value of it displayed on 14 bit LED .My problem is that the 125 MHz LVDS Oscillator is connected to DCM and the output of counter that displayed on LED not stabled and the DCM reset randomly (i use reset signal that value of it is not(pll_Lock) and when pll_lock is disabled, the counter and LED reset to zero).The Clock must be produced continuously and be stabled, this problem influences the entire system and it be failed.The PartNumber of Oscillator is: "EEG-2102 125000P" that works with 3.3v and the jitter is 3ps. I use "tektronix 2465A 350 Mhz Analog Oscilloscope" and i can't watch and measure the LVDS outputs and my question is how can i measure the LVDS signal values by Oscilloscope?please help me to solve this problem.best regards,

author: Scrts
author_rank: Frequent Contributor
timestamp: September 04, 2019, 01:33:25 pm
content: Did you terminate the LVDS correctly? Show us the schematics first.
I2S clock from 100MHz on Artix-7 - Page 1
Forum section: electronics / general

author: hamster_nz
author_rank: Super Contributor
timestamp: August 31, 2019, 10:20:31 am
content: Just been mucking around... if you use an MMCME2_BASE:Take the 100MHz system clock100MHz / 5 = 20MHz (DIVCLK_DIVIDE = 5)20Mhz * 48 = 960 MHz VCO frequency (CLKFBOUT_MULT_F = 48)960MHz/78.125 = 12.288 MHz (CLKOUT_DIVIDE_F = 78.125)12.288 is a great I2S master clock frequency for most audio DACs running at 48000 S/s, as it is 512 times the sample rate e.g. for with a CS4244 DAC.
Tthe VDF Alliance FPGA Competition. - Page 1
Forum section: electronics / general

author: hamster_nz
author_rank: Super Contributor
timestamp: August 23, 2019, 11:33:45 pm
content: Be in to will a cool $100k - I haven't read it all yet, but it seems to be just compute h=x^(2^T) mod N, faster than anybody else. Sponsered by Xilinx and some Blockchain alliance.Need to use Vivado as the toolset. Amazon F1 instances are tied up in the judging. Open internationally.https://supranational.atlassian.net/wiki/spaces/VA/pages/36569208/FPGA+Competition

author: Bassman59
author_rank: Super Contributor
timestamp: August 29, 2019, 08:17:46 pm
content: Quote from: hamster_nz on August 23, 2019, 11:33:45 pmSeems to me that Xilinx & Friends are just trying to get this work done on the cheap. If the results are any good, they're worth more than the $100k.
Error In Encoder (Verilog Code) - Page 1
Forum section: electronics / general

author: 1s1
author_rank: Newbie
timestamp: August 13, 2019, 02:58:02 pm
content: module burglar_alarm(output [2:0] intruder_zone,output valid,input [1:8] zone);assign intruder_zone = zone | zone | zone | zone;assign intruder_zone = zone | zone | zone | zone;assign intruder_zone = zone | zone | zone | zone;assign valid = zone | zone | zone | zone | zone zone | zone | zone;endmoduleERRORSunexpected token: 'zone'expecting ';', found ']'expecting 'endmodule', found '|'on checking the syntax in Xilinx ISE suit, i am getting those errors for the last assign statement in the code -" assign valid = zone | zone | zone | zone | zone zone | zone | zone; "can anybody please help me with this?Thank you in advance

author: Evan.Cornell
author_rank: Regular Contributor
timestamp: August 13, 2019, 04:02:53 pm
content: Missing | between zone and zone, perhaps?

author: LeoTech
author_rank: Regular Contributor
timestamp: August 13, 2019, 04:09:16 pm
content: Quote from: Evan.Cornell on August 13, 2019, 04:02:53 pmThat is indeed the problem, I just stumbled upon that myself and ran it, with the fix, through the Quartus compiler and it does indeed work now.

author: kfnight
author_rank: Regular Contributor
timestamp: August 22, 2019, 04:07:13 pm
content: Code:assign valid = zone | zone | zone | zone | zone | zone | zone | zone;can be simplified toCode:assign valid = |zone;since you are ORing all the bits of zone.
Help with this verilog video - Page 1
Forum section: electronics / general

author: lawrence11
author_rank: Frequent Contributor
timestamp: August 17, 2019, 06:00:49 pm
content: Lecture 2 of 10.Here in this @ 5:10 , the line that bugs me is WORD [i+3:i], because it has an error box that points to itMr Kirk Weedman says its in the same direction? So its good or not, or did he just make a mistake? he never states this is a error but the box is there.

author: ataradov
author_rank: Super Contributor
timestamp: August 17, 2019, 06:22:46 pm
content: The error is because index is not constant.This construction would be fine in the 'generate' block. Because in the end it still results in a fixed index.

author: langwadt
author_rank: Super Contributor
timestamp: August 17, 2019, 06:24:11 pm
content: it's right on the slide: indexes must be constants

author: BrianHG
author_rank: Super Contributor
timestamp: August 20, 2019, 03:38:38 am
content: That one got me thinking, didn't I successfully use variables in my indexes in the past?I just checked, and it was not a normal variable, but a 'Parameter'.If you want parameters for your Verilog module, say a configuration for the address size for a block of memory, the assigned label you use for the parameterisallowed in your indexes.

author: ejeffrey
author_rank: Super Contributor
timestamp: August 20, 2019, 04:03:30 am
content: Yes, parameter and `define values are constant so they can be used freely in index expressions.You can use a single variable expression index with no problem. Only for ranges are constant expressions required. Note that you can also do a variable range select using the -: syntax: myreg[8*i + 7 -: 8] will select bytes out of a multi-byte register. The starting index can be variable only the offset has to be constant.

author: kfnight
author_rank: Regular Contributor
timestamp: August 22, 2019, 03:02:15 pm
content: The desire for non-constant width part selects has been on the SV ballot for a while now. Seehttps://accellera.mantishub.io/view.php?id=2684

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 22, 2019, 03:27:53 pm
content: Note that it's been available in VHDL for ages.
Quartus programmer chain file [Solved] - Page 1
Forum section: electronics / general

author: Wiljan
author_rank: Regular Contributor
timestamp: August 18, 2019, 09:19:58 am
content: In Quartus when you have compiled a project and you go to the programmer you select the right chip etc.I work on a project where I do create svf output file which does include 4 FPGA's which you have to choose manually each timeI does work as expected but I have a question ... in the programmer you can save (It nag's you always to save) a chain.cdf file.So can do that and it create a ASCII file with the programmer setting, so far so good....But after next compile ... I don't see where to open the chain file already saved... it just create a new one (and have to set it all up again).So how to open an existing chain.cdf file in Quartus?

author: Wiljan
author_rank: Regular Contributor
timestamp: August 18, 2019, 05:03:18 pm
content: Ok, found out, pretty simpleIn the main menu of Quartus (not in the programmer) select : File=> Open => Change Filetype to "Programming Files" and select your .cdf filehttp://www.pldworld.com/_altera/html/_sw/q2help/source/pgm/pgm_pro_open_prog_win.htm
input [7:0] data; in verilog. Serial or parallel? - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: July 26, 2019, 07:15:16 am
content: Hello!im messing around in verilog, and i have an 8 bit input data variable of type wire.does this mean that the data will come into the module one bit at a time? or do all the bits come in parallel and the one wire acts as 8?thanks!

author: hamster_nz
author_rank: Super Contributor
timestamp: July 26, 2019, 07:32:29 am
content: 8 bits in parallel.

author: mrflibble
author_rank: Super Contributor
timestamp: July 26, 2019, 08:15:46 am
content: This one might be useful for a quick lookup of verilog related questions:http://www.asic-world.com/verilog/veritut.html

author: SethGI
author_rank: Regular Contributor
timestamp: August 11, 2019, 03:24:35 pm
content: In verilog, when you use the [n:m] syntax, you're specifying abus. That means, as others have answered, it'll come in in parallel. So 8 wires.The most important thing everyone needs to know about verilog is it isNOTa programming language (at least how you'd typically think about it). You're not specifying what the FPGA should *do*, you're specifying how to connect the hardware. Even things like case switches which feel more like imperative programming are really just convenient ways to specify the hardware connections. In that context, it wouldn't make much sense for the 8 bits to somehow serialize themselves, you'd have to specify the hardware for that. Go ahead and look at the visualization tools in your compiler each time you compile to understand the hardware you're implying. I think the biggest thing which causes people issues in FPGA programming is they think "what are the steps I need to take to get the desired behavior" and try to program in those steps, whereas the correct question is "what hardware do I need for the desired behavior". Sorry for the tangential rant you likely already (kinda) understood, but this is really important to keep in mind when learning verilog.
case statement written so output is low, but sim shows high pulse? - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: August 06, 2019, 12:36:22 am
content: Hi!https://www.edaplayground.com/x/5YL2trying to make another spwm code in verilog. I have the duty cycle values stored in a register, which is called up by a select which cycles through them.My case statement is written so the output should be low when a certain select value is input, however there is actually a very small pulse shown where the output should be low. the red circles in the picture are where this occurs, and you can run the code on EDA playground to see for yourself. Am i missing something very basic?Code:always @ (posedge clk or select)begincase(select)0 : r_duty_cycle <= 0;1 : r_duty_cycle <= 9;2 : r_duty_cycle <= 17;3 : r_duty_cycle <= 26;4 : r_duty_cycle <= 35;5 : r_duty_cycle <= 42;6 : r_duty_cycle <= 50;7 : r_duty_cycle <= 57;8 : r_duty_cycle <= 64;9 : r_duty_cycle <= 71;10 : r_duty_cycle <= 77;11 : r_duty_cycle <= 82;12 : r_duty_cycle <= 87;13 : r_duty_cycle <= 90;14 : r_duty_cycle <= 93;15 : r_duty_cycle <= 96;16 : r_duty_cycle <= 97;17 : r_duty_cycle <= 98;18 : r_duty_cycle <= 99; //middle19 : r_duty_cycle <= 98;20 : r_duty_cycle <= 97;21 : r_duty_cycle <= 96;22 : r_duty_cycle <= 93;23 : r_duty_cycle <= 90;24 : r_duty_cycle <= 87;25 : r_duty_cycle <= 82;26 : r_duty_cycle <= 77;27 : r_duty_cycle <= 71;28 : r_duty_cycle <= 64;29 : r_duty_cycle <= 57;30 : r_duty_cycle <= 50;31 : r_duty_cycle <= 42;32 : r_duty_cycle <= 35;33 : r_duty_cycle <= 26;34 : r_duty_cycle <= 17;35 : r_duty_cycle <= 9;36 : r_duty_cycle <= 0;endcaseend

author: Nusa
author_rank: Super Contributor
timestamp: August 06, 2019, 01:12:33 am
content: What is the value of r_duty_cycle when the always statement evaluates to false? Is it guaranteed to be zero at declaration?

author: asmi
author_rank: Super Contributor
timestamp: August 06, 2019, 02:16:48 am
content: Your code declares asynchronous inputs "select" (via "always" clause with mixed sensitivity list). Because different parts of that input takes different ways to output, you're getting these glitches.Never do that with real FPGAs, and always use synchronous inputs, or re-synchronize them yourself. If you remove "select" from sensitivity list, it should work properly.

author: NorthGuy
author_rank: Super Contributor
timestamp: August 06, 2019, 03:45:20 am
content: Code:assign out = (counter <= r_duty_cycle) ? 1:0What do expect when both counter and r_duty_cycle are 0?

author: Dmeads
author_rank: Regular Contributor
timestamp: August 06, 2019, 04:38:51 am
content: great feedback and got it working thanks!

author: hamster_nz
author_rank: Super Contributor
timestamp: August 06, 2019, 06:06:46 am
content: I always think that there is something interesting about how there are 257 different levels if you use an 8-bit counter in your PWM design:0 of 256 periods high (0%)1 of 256 periods high...255 of 256 periods high256 of 256 periods high (100%)Solutions are easy, but the issue isn"t self evident until somebody points it out to you.
Verilog module with SPI needs to read AXI - Page 1
Forum section: electronics / general

author: raff5184
author_rank: Regular Contributor
timestamp: June 25, 2019, 12:41:00 pm
content: Hi,I'm new to this topic. Basically I have a Verilog module that gets some data via SPI. I want to create an IP module in Vivado with the Verilog code and get the data from BRAM. Thus I need to use an AXI interface. How do I "convert" the SPI into AXI? I am not sure this is conceptually correct

author: asmi
author_rank: Super Contributor
timestamp: June 25, 2019, 03:15:11 pm
content: Quote from: raff5184 on June 25, 2019, 12:41:00 pm1. You don't need AXI interface to get data from BRAM. You can use the "native" interface if you wish. You can have one BRAM port connected to AXI BRAM controller, and the second port directly connected to your core. There is nothing wrong with this approach. You will still need some kind of out of band signal which would tell your core when the data is ready so that it can start transmission.2. If you prefer to still use AXI (which would allow your core to pull the data from any AXI-compliant source, like DDR for example, and not just BRAM), you can implement AXI master interface. It's quite easy to implement, despite the fact that amount of signals you have to deal with might feel intimidating at first. Just read the AXI spec - it's very good and easy to understand. Also - Xilinx added AXI transaction viewer in the most recent version of Vivado, so debugging this interface has become easier than ever. Another extremely useful IP is "AXI Verification IP", which is basically a SystemVerilog library with full source code available, and allows you to issue and/or receive AXI transactions with very little code in test benches.3. You can use Xilinx's "AXI Quad SPI" IP block to talk to your SPI peripheral, and a small Microblaze core to orchestrate all data transfers.
Xilinx is now available at Mouser! - Page 1
Forum section: electronics / general

author: asmi
author_rank: Super Contributor
timestamp: July 10, 2019, 05:32:54 pm
content: https://www.mouser.ca/xilinx/Finally we're getting a second reliable source of their chips! Prices seems a bit lower than DK too - at least in Canadian Mouser.

author: NorthGuy
author_rank: Super Contributor
timestamp: July 10, 2019, 05:59:27 pm
content: Quote from: asmi on July 10, 2019, 05:32:54 pmLower indeed, by 30-40 centsNothing in stock yet.

author: asmi
author_rank: Super Contributor
timestamp: July 10, 2019, 06:05:16 pm
content: Quote from: NorthGuy on July 10, 2019, 05:59:27 pmXC7A100T-2FGG484C is cheaper by 7 CADQuote from: NorthGuy on July 10, 2019, 05:59:27 pmSome stuff is in stock already (for example, XC7A35T-2FGG484C), but a lot is "On Order", which is typical for Mouser. When they started selling Micron parts, it was the same thing, except prices were quite a bit higher in the beginning. But by now it all settled down.
clock gen on fpga simulates correctly but doesnt work in hardware.  - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: June 22, 2019, 06:42:57 pm
content: Hi everyone.The board I am using has a 12MHz clock. For much easier math and accurate timing, it would be better for me to use a 10 Mhz clock.I tried generating one, but it does not work in the actual hardware. All I see on my oscilloscope is a 3.3v DC signal.It simulates fine in both the board manufacturer's software and eda playground. this is my verilog.Code:`default_nettype none`timescale 1ns / 1nsmodule clk(output clk);reg clk1 = 0;always #1000 clk1 = ~clk1;assign clk = clk1;endmoduleand testbench:Code:`default_nettype none`timescale 1ns / 1nsmodule tb;wire clk;clk uut(clk);initialbegin$dumpfile("dump.vcd");$dumpvars(0,uut);#100000$finish;endendmoduledoes anyone know why this doesn't work in the hardware?thanks.

author: ataradov
author_rank: Super Contributor
timestamp: June 22, 2019, 06:46:07 pm
content: There is nothing in FPGA that can do "#1000". This is a simulation-only construction.You will have to actually use PLL in the FPGA to get what you need. There is no way to describe it in a pure Verilog.And if your FPGA does not have a PLL, then you are out of luck entirely.
SPWM in verilog timing issue - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: June 19, 2019, 09:43:06 pm
content: Hi peeps. I am making an SPWM verilog algorithm for an FPGA board I got.I am having trouble in with timing, and I am getting some voltage pikes that shouldnt be in the output.Basically, I am generating a few PWM signals with different duty cycles. I am using a multiplexer to choose which signal is output. The select for the multiplexer is driven by an up-down counter that first selects the PWM signals from smallest to largest, and then back down (so it makes a wave).I implemented a more basic version of this code with a lowpass filter on a lattice Icestick and got it to work pretty good actually.Where i am having trouble is some PWM signals in the output that shouldn't be there. It seems to be a timing issue with the select for the multiplexer and one of the PWM signals. (SEE red circle in picture)Does anyone know how I can fix this?This is a link to my code:https://www.edaplayground.com/x/2cK2hit run a the top to see the waveform.Also I am a beginner, so please go easy on meOnce I get the code working the way I want it to, I will post it for critique. If you need me to rename any of the signals/modules for easier interpretation please let me know.Thanks!

author: NorthGuy
author_rank: Super Contributor
timestamp: June 20, 2019, 12:38:18 am
content: Looks like you're switching your PWMs close to the end of the PWM period, so your 4-th PWM which is already in the low state is being changed to the 5-th PWM which is still in the high state, which creates what you perceive as a glitch.Instead, switch your PWMs at the very first clock of the PWM cycle.

author: Dmeads
author_rank: Regular Contributor
timestamp: June 20, 2019, 07:49:01 pm
content: Thanks so much!Worked like a charm!
xilinx xc4000 - anyone worked on it? - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: June 11, 2019, 02:06:23 pm
content: hiI have found a couple of cool PCI-cards with a xc4000 fpga on it.The price is very good (20 euro/each), and the PCI card looks cool.I am tempted, just to play with the PCI bus, which is something that is intriguing me.Anyway, the first question in my head is: which software tool will be the right one today?It seems ISE has no support

author: asmi
author_rank: Super Contributor
timestamp: June 11, 2019, 02:27:37 pm
content: https://www.xilinx.com/support/answers/33560.htmlQuoteHere is another useful AR:https://www.xilinx.com/support/answers/33562.html

author: Bassman59
author_rank: Super Contributor
timestamp: June 11, 2019, 04:38:40 pm
content: Quote from: legacy on June 11, 2019, 02:06:23 pmThe last time I used an XC4000 device was twenty years ago.None of the modern tools support it. If you want to do VHDL or Verilog, you're doubly outta luck, because the only synthesis tool available for those parts was Synopsys' awful thing (Synplify, before it was bought by Synopsys, was better but quite pricey at the time).Don't bother.

author: legacy
author_rank: Super Contributor
timestamp: June 11, 2019, 05:11:57 pm
content: Quote from: Bassman59 on June 11, 2019, 04:38:40 pmyes, vhdl, so "d'oh!". I'd better passthanks guys, anyway

author: Heartbreaker
author_rank: Unknown
timestamp: June 17, 2019, 09:15:01 pm
content: Quote from: legacy on June 11, 2019, 05:11:57 pmIf you are looking for FPGAs with PCI connectivity then there is the HP 82350B GPIB interface board. It features a Spartan2, which is last supported by ISE 10.1.Just my $0.02.
Altera 7000 dev board - Page 1
Forum section: electronics / general

author: Daxxin
author_rank: Regular Contributor
timestamp: March 29, 2019, 11:05:37 am
content: Any schematic or nice project about to make 7000 series?

author: marcopolo
author_rank: Regular Contributor
timestamp: June 17, 2019, 07:31:26 pm
content: Hello,Altera UP1 and UP2 boards: MAX7000 and Flex10Khttp://www.altera.co.kr/_altera/html/ref/UP2_board_schematics.zipMarc
Xilinx XC2064 Development Board - Page 1
Forum section: electronics / general

author: KK6IL
author_rank: Regular Contributor
timestamp: June 08, 2019, 05:11:48 am
content: Found a XC2064 Development Board in the garage - not supported by any version of ISE on the Xilins site. Free to a good home if anyone has a use for it.John

author: legacy
author_rank: Super Contributor
timestamp: June 08, 2019, 09:21:18 am
content: eh, I am still looking for a spartan2 board ...the hope is someday someone will find one in his/her garage

author: KrudyZ
author_rank: Frequent Contributor
timestamp: June 09, 2019, 10:30:59 am
content: Some museum might want it, after all it's in the IEEE's chip hall of fame...https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Xilinx-XC2064-world-s-first-commercial-FPGA-inducted-into-IEEE-s/ba-p/775806

author: LapTop006
author_rank: Unknown
timestamp: June 09, 2019, 01:07:53 pm
content: The folk working on the open source FPGA toolchains would almost certainly love it. I'll point them at this thread.

author: JohnDMcMaster
author_rank: Newbie
timestamp: June 09, 2019, 05:05:49 pm
content: Sent PM (I'm one of the XC2000 FOSS FPGA devs)