hybridfree/eevblog-posts huggingface dataset:
Is the F4PGA / Chipsalliance project still active? - Page 1
Forum section: electronics / general

author: betocool
author_rank: Regular Contributor
timestamp: July 16, 2024, 01:22:32 pm
content: Hey all,about two or so years ago I was very interested in the whole Open Source / Yosys / Risc-V FPGA news that were coming out about... well... open source tools to synthesize, place and route FPGAs. I also looked into Litex and Migen a bit (that's the Python HDL description language), but of late I've been busy with other things and this kinda went off my mind.I was looking again today after a longer absence, I can see the GIT repohttps://github.com/chipsalliance/f4pgahasn't been updated in 10 months, and there are not many "new" on thehttps://f4pga.org/website.Is this still active? Is it very slow? I can't easily find what chips are supported how exactly either, so, it looks a bit neglected for lack of a better word. Academic interest only?Cheers,Alberto

author: laugensalm
author_rank: Regular Contributor
timestamp: July 17, 2024, 10:02:58 am
content: That's the former Symbiflow toolchain, right?I could so far not see the extra value in it apart from the already existing [Design Entry of whatever kind] -> yosys -> nextpnr -> [ bitffile programming of your target] flow that is pretty straightforward already. I don't really understand the motivation of its sales points, hence.I'd characterize the situation with these toolchain flows like: Everyone seriously working with it sets up their (his/her) configuration that works well with a particular project, but not everyone sets a standard, and often those enthusiastic projects don't gain enough momentum to justify investment into a fancy org and website or attract more developers after those Summer of Code projects have ended. Also, broad support for a large number of targets is often very underestimated in complexity.Nevertheless, I'd say the yosys-nextpnr-toolchain is far from academic and good enough to handle some industrial applications where the last f_max optimization is irrelevant.

author: betocool
author_rank: Regular Contributor
timestamp: July 18, 2024, 06:12:58 am
content: Momentum, that I think is they key word. It feels they ran out of momentum. I remember a bit more talk about 4 or so years ago, but now it seems to have slowed down.Then again, I am not as active as I would like to, in the end out of simplicity I end up using the same old suspects, Quartus, Vivado, etc.Cheers,Alberto

author: dolbeau
author_rank: Regular Contributor
timestamp: July 20, 2024, 04:01:12 pm
content: FPGA internals are mostly fully closed still, so such open-source toolchains have to do a lot of reverse-engineering and guesswork.With the multiplications of open-sourced PDKs for ASICs, it seems to me the momentum for open-source toolchains has moved toward ASIC flows. Those PDKs are for non-leading-edge processes that usually have regular MPW slots for academics at somewhat reduced cost, so there is quite a bit of interest there. For instance, The IHPS13G2is availablefrom europractice.
JTAG Programming on PLUTO PLUS or ADALM Pluto - Page 1
Forum section: electronics / general

author: jemp
author_rank: Contributor
timestamp: July 29, 2024, 03:44:55 pm
content: Hello, AllAs many of the Pluto User i have seen, there are many that obtained a bricked version after changing the firmware..AD describes how to JTAG this bricked Pluto Plus, which will not come into DFU mode and NOT recognized by Windows anymoreSo I bougt a Xilinx USB Platform II Cable and installed XilinxSDK 2017.4I downloaded the Jtag firmware v0.29, to be found on the Github, with 4 files in it run.tcl, ps7_init.tcl, system_top.bit, u-boot.elf and installed these in ...sdk/scripts/xmd folder of Xilinx SDKMy pluto is seen by the SDK and when I enter run.tcl I get this result.. ( see picture )The ps7_init.tcl is not found.. strange because I put them beside the run.tcl file..Can anyone explain this.. or where should this file be then ?Tnx for any help

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 29, 2024, 08:37:28 pm
content: Suggest asking in the xilinx-AMD forums.
STM32 jetson - Page 1
Forum section: electronics / general

author: LootMaster
author_rank: Regular Contributor
timestamp: May 23, 2024, 09:26:56 am
content: I need help. Who wants to help me fight back vs NVIDIA and claim a bit of their %?Your role is to help me with the FPGA, and maybe the FMC/QSPI dual bank.You get what I get, 50/50.

author: LootMaster
author_rank: Regular Contributor
timestamp: May 24, 2024, 02:53:54 am
content: The only reason I am showing you guys this beauteous design ie because I know full well there is no time for you guys to steal my design.I am indeed, a prophetic person, as you can see, from my past posts. 3 years ago... When I started preaching everywhere like a HOBO with Homer Simpson's sign... the end is near.... God loves you, he's going to kill youuuuuuu.

author: gnif
author_rank: Unknown
timestamp: May 24, 2024, 05:46:07 am
content: Double posting here is frowned upon, please do not do this again. LockedOriginal Topic:https://www.eevblog.com/forum/projects/stm32-jetson-429535/
open source USB OTG core? - Page 1
Forum section: electronics / general

author: FrankBuss
author_rank: Unknown
timestamp: May 21, 2024, 05:37:42 am
content: I thought about using a USB PHY like the USB3320 to implement host and device USB with USB OTG for a project in a FPGA (GW1NR-4). Is there an open source core for it? I asked a commercial company, but source code license for their cores is very expensive, much more than the entire planned profit of my product.
Can Microchip Configurable Logic Block (CLB) match UART address? - Page 1
Forum section: electronics / general

author: nunojpg
author_rank: Contributor
timestamp: March 09, 2024, 10:46:37 am
content: Hey!I want to implement 1-Wire like slaves with a uC and looking for a option to stay sleeping while the master doesn't send the address.Other functions like Search and Alert don't need to be implemented on sleep.For this case I wonder if Microchip CLB would be able to match a preamble and address, even if 8 bits.The specs are:1x CLB - Interconnected fabric containing 32 Basic Logic Elements (BLE) / each BLE contains one 16-input Look-Up Table (LUT) and one flip-flop4x CLC - Configurable Logic Cells - Integrated combinational and sequential logicI have very limited experience in configurable circuits, so I wouldn't be surprised if the answer is trivial.Thanks

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: March 09, 2024, 11:09:40 am
content: You'd need to keep the clock running so is there much benefit to being asleep?What sort of baudrate are you looking at? - maybe you could decode in software & wake on a leasing edge - the RC osc would probably startfast enough for lower baudrates.

author: voltsandjolts
author_rank: Unknown
timestamp: March 09, 2024, 11:30:31 am
content: DS28E18 interface is powered from the 1-wire bus (saves your slave power) but you would need to wakeup mcu fairly quick, few microseconds.

author: nunojpg
author_rank: Contributor
timestamp: May 18, 2024, 11:03:38 am
content: Right. I ended up implementing it in assembly with the attiny. Need about 2MHz to do the proper shapes, so about 1mA per device when the bus is active (all need to be awake).

author: nunojpg
author_rank: Contributor
timestamp: May 18, 2024, 11:05:32 am
content: I was extending the 1W protocol with a industrial bus style mode (like CAN/Ethercat), where each device participates in the same 1W transaction and just sets some bits, so using the DS28E18 was not a option.
Lattice IP use with Modelsim - Page 1
Forum section: electronics / general

author: rayhaynes
author_rank: Newbie
timestamp: May 15, 2024, 07:00:42 pm
content: I'm using the ModelSim that came with the Diamond 3.13 installation and running simulations successfully on a medium sized design (multiple modules with multiple levels of hierarchy) and but once I add my first Lattice IP block, a customized FIFO_DC, I run into a problem.I used IP Express to create the IP (my_fifo).Added the my_fifo.v that was created by IP Express in the project root to the my VLOG list of files.Added -L xp2 to the vsim command line and now I'm stuck at this error when I run the simulation:Error (suppressible): (vsim-10000) Unresolved defparam reference to 'LUT4_16' in LUT4_16.initvalI get this error for each of the defparams in the my_fifo.v file (there are many). Here is code snipit from the my_fifo.v file that is creating the error:Code:// synopsys translate_offdefparam LUT4_16.initval = 16'h8000 ;// synopsys translate_onROM16X1 LUT4_16 (.AD3(scuba_vhi), .AD2(wren_i), .AD1(scuba_vhi), .AD0(scuba_vhi), .DO0(dec0_wre3))When expand the xp2 library in modelsim I can see the ROM16x1 entry.The xp2 library came pre-compiled and VMAP'ed in this Lattice version of ModelsimWhat step am I missing?

author: BrianHG
author_rank: Super Contributor
timestamp: May 15, 2024, 10:59:46 pm
content: Try writing the line like this:Code:ROM16X1 #( .initval (16'h8000) ) LUT4_16 (.AD3(scuba_vhi), .AD2(wren_i), .AD1(scuba_vhi), .AD0(scuba_vhi), .DO0(dec0_wre3))If this doesn't work, then the 'initval' is not a proper parameter within 'ROM16x1'.Maybe 'initval' needs to be uppercase?Also, some of Lattice's functions actually have fake parameters generated by their wizard code generator, where Lattice Diamond uses comments to set controls for their FPGA compiler which are completely ignored by Modelsim. Lattice's PLL is notorious for this placing controls and settings as ASCII text as actual comments in your code and Diamond fails to fully reach a proper timing if you remove those /* abc_frequency = number_mhz */ in your code.
Loss of connectivity with Virtex 6 FPGA after successful programming - Page 1
Forum section: electronics / general

author: lenaf
author_rank: Newbie
timestamp: May 13, 2024, 03:11:12 pm
content: I am trying to program my Virtex 6 over JTAG using ISE/Impact 13.1 on Ubuntu 18.04. I installed ISE 13.1 and followed the Arch Linux instructions to install the drivers (https://wiki.archlinux.org/title/Xilinx_ISE_WebPACK#Xilinx_Platform_Cable_USB-JTAG_Drivers). I did a boundary scan in Impact, the FPGA was detected, and I was able to successfully program the FPGA. When I was done for the day, I turned off the FPGA but did not change anything else. When I came back the next day and turned on the FPGA, the JTAG LED on the FPGA did not turn on and Impact was not able to detect the FPGA. The console shows:AutoDetecting cable. Please wait.PROGRESS_START - Starting Operation.If you are using the Platform Cable USB, please refer to the USB Cable Installation Guide (UG344) to install the libusb package.Using windrvr6 driver.Connecting to cable (Usb Port - USB21).Checking cable driver.File version of /opt/Xilinx/13.1/ISE_DS/ISE/bin/lin64/xusbdfwu.hex = 1030.File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1030.libusb-driver.so version: 2023-01-11 12:17:37.Cable connection failed.I am able to successfully program the FPGA from another machine with no issues (Red Hat VM running on Windows 10). Puzzlingly, if I connect my FPGA to my Windows computer over the USB cable, wait for the JTAG LED to illuminate, and then unplug the USB and plug in to my Ubuntu machine, I can connect and program using ISE on Ubuntu. However as soon as I power cycle the FPGA or unplug the USB cable the problem returns and the FPGA is no longer detected. I have tried using the "Disconnect all cables" feature in Impact before power cycling the FPGA but this doesn't solve the problems.I'm puzzled... does anyone know what's going on? Thanks!
OpenCores.org login - Page 1
Forum section: electronics / general

author: bill8n95
author_rank: Newbie
timestamp: April 14, 2024, 05:15:22 pm
content: website opencores.org has a problem about sending password resetting email. So you shouldn't ask for this kind of email, because the password will be changed and you'll never get the email with the new password. That's what I did !Could someone with access to opencores.org please send me the download from the projects :"https://opencores.org/projects/ax4lbr" and"https://opencores.org/projects/can"

author: ataradov
author_rank: Super Contributor
timestamp: April 14, 2024, 06:17:03 pm
content: Here they are. Rename .zip to .gz, forum does not allow that extension.OpenCores login system has been the real pain since the start and it never got better.

author: bill8n95
author_rank: Newbie
timestamp: April 14, 2024, 07:22:39 pm
content: Thank you very much !

author: bson
author_rank: Unknown
timestamp: May 08, 2024, 07:24:45 pm
content: I can't even register to create an account. After filling out all info on screen 1/7, Basic Info, the "next" button remains grayed out. I think I had an account sometime in the past, but it doesn't seem able to find it, maybe it got deleted due to inactivity. I wonder how hard it would be to set up a better hosting service for this...

author: ataradov
author_rank: Super Contributor
timestamp: May 08, 2024, 07:53:56 pm
content: GitHub or GitLab is a better hosting. Most of the stuff on OpenCores is abandoned. I expect that all the supported stuff already moved to less antiquated places.

author: bson
author_rank: Unknown
timestamp: May 09, 2024, 12:27:38 am
content: Yeah, I was thinking github/gitlab would be much better, this way people could fork repos, submit PRs/MRs, track issues, versioning, etc... So what's really needed is a discovery mechanism with decent categorization, license info, authors, some rough estimates for complexity (LUTs etc), requirements (e.g. LVDS pads)... but the stuffs that matters can live on github/gitlab.

author: Siwastaja
author_rank: Super Contributor
timestamp: May 09, 2024, 11:32:43 am
content: I never found anything useful on OpenCores. Most of the projects are overengineered and underimplemented. You usually create what you need from scratch is much less time than trying to get something from OpenCores work.

author: luudee
author_rank: Frequent Contributor
timestamp: May 09, 2024, 11:38:09 am
content: Quote from: ataradov on May 08, 2024, 07:53:56 pmAlex,Unfortunately, I believe you are right. These people were the last owners of OpenCores.org:https://oliscience.nl/But I think that organization is also inactive ...rudi

author: bson
author_rank: Unknown
timestamp: May 12, 2024, 08:59:59 pm
content: Quote from: Siwastaja on May 09, 2024, 11:32:43 amThere was mention of the T80 project on the "RIP Z80" thread in the Microcontrollers forum, so I thought I'd download it and poke around a bit. Oh well, it's not exactly important.
Alchitry CU (Lattice iCE40HX8K CB132) 3D GPU example - Page 1
Forum section: electronics / general

author: trossin
author_rank: Contributor
timestamp: June 16, 2024, 10:41:22 pm
content: I connected a Raspberry Pi Pico, some static RAM and a 320x240 TFT display to create an OpenGL 3D system. I tried to make things parametrized so that the multipliers, dividers, span interpolator and triangle code can be used in different sized designs. Making triangles mesh nicely requires interpolated snapping of start points for edge walkers and spans so there is more complexity. The book " Advanced Animation and Rendering Techniques" that I got in the mid 1990s has the secrets of how to properly render triangles.The lack of floating point hardware in the Pico and my not so clever OpenGL implementation are the performance limiters. I seldom see the full led flash. The design does have a 256 triangle input FIFO and 256 pixel output FIFO and I slightly overclock the FPGA at 40MHz (it times for around 36 to 38 MHz depending on the weather). I also double overclock the Pico to run at 250 MHz instead of the default 125 MHz. Word on the street is that it can do nearly 350 MHz for most folks.Details with Verilog and test benches can be found here (I use Icarus and my own VCD waveform viewer that can be found on my tools page):https://sites.google.com/site/tedrossin/home/electronics/lattice-fpgaVideo Here:https://youtu.be/kEHmk7wb3PY
REQ: AVNET SPARTAN-6 LX9 Microboard Files - Page 1
Forum section: electronics / general

author: RomDump
author_rank: Regular Contributor
timestamp: April 22, 2024, 10:17:41 pm
content: Looking for a couple of files.1) Avnet Spartan-6 LX9 Factory Test ApplicationFactory_Test_Install.zip2)Avnet SPI BootloaderC30_Bootloader.zipWondering if anyone still has a copy?Thanks.

author: JimboJack
author_rank: Regular Contributor
timestamp: May 02, 2024, 04:22:12 am
content: it about ~2.4 GB in total all the files if you count different versions for ISE ...blah blah ,etc dropped in the last of the ISE builds.J.

author: JimboJack
author_rank: Regular Contributor
timestamp: May 02, 2024, 05:45:16 am
content: Just in case you need the old USB driversprevious post the 14.4_2 was a duplicate

author: RomDump
author_rank: Regular Contributor
timestamp: May 02, 2024, 08:28:47 am
content: Thank You JimboJack.
PS PL Communication using AXI DMA and FreeRTOS on zynq arty z7-20 - Page 1
Forum section: electronics / general

author: pepep
author_rank: Newbie
timestamp: April 18, 2024, 08:16:51 pm
content: Hello everyone!I'm new to FPGAs but i have worked in software. I have to create a project for an application and i need to configure the PS PL communication for it.I'm using FreeRTOS on my board and in the ARM i have developed the code that does the processing i need to.I have configured an echo server using the examples in Vitis and i send data via ethernet to the board. I then parse the data, make some calculations and then i ready them for dispatch. I need to send them to the FPGA but i don't know how i need to connect the AXI DMA to the fabric.I want to notify the FPGA when the packet is ready and the FPGA to go and read the data. I'm stuck!For start i think i could do a simpler project like an AND gate module and an empty application in the ARM. I will set 1 or 0 in the application and i want to feed it to the FPGA. How would i do that? How would i connect them?Thanks in advance!
3 bit Dff Counter Issue - Page 1
Forum section: electronics / general

author: jrw0531
author_rank: Newbie
timestamp: April 17, 2024, 12:37:25 pm
content: Hello all,Overall project: getting a 555 timer to power a stepper motor with 7400 logic only. I've decided to try a 3 bit counter with D flip flops but I am not getting the desired output.My desired output is a half step of a stepper motor, so A, AB, B, BC, C, CD, D, DA but I am getting some weird results in my simulation. TIA! I've checked my K-map process and output logic multiple times and I don't think that is the issue. Attached is schematic and waveform.

author: BrianHG
author_rank: Super Contributor
timestamp: April 17, 2024, 02:37:36 pm
content: In your simulation, you should also display your 3 bit counter's output so you may see if it is counting properly. This will help you debug.If you are designing to eventually place this logic in a PLD:I'm curious. You appear to be using an old quartus schematic entry, manually entering gates and wires.Would you not prefer to do this in an HDL language like verilog or System Verilog?It would be much easier to code, simulate and edit as you are talking about a basic setup, then very few lines of code.Also, you may use a proper simulator like Modelsim which is also available for free with Quartus as well as for most other FPGA vendors.

author: BrianHG
author_rank: Super Contributor
timestamp: April 17, 2024, 02:51:51 pm
content: If you want to stick with the 74xx logic, maybe instead of using 3 DFFs as your counter, try using a 4bit UP-Down counter. This way, you at least know your counter logic itself is sound.Maybe look at the 74LS169.
VHDL CODE QUESTION - Page 1
Forum section: electronics / general

author: Austin
author_rank: Newbie
timestamp: April 03, 2024, 02:27:10 am
content: I'm trying to make a pulse width counter with 32bit counter on FPGA.I haven't tried it on the actual board yet.(I don't have the board around me right now)The question I came up with is this.When the rst is1,TMP<=cnt; and cnt <=X"00000000"; will be executed simultaneously.At least that's what I thought ...Will this code run stably and reliably?library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Top isPort ( clk : in STD_LOGIC;rst : in STD_LOGIC;count : out STD_LOGIC_VECTOR(31 downto 0);hold : out STD_LOGIC_VECTOR(31 downto 0));end Top;architecture Behavioral of Top issignal cnt : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');signal TMP : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');beginprocess(clk, rst)beginif rst = '1' thenTMP<=cnt;cnt <=X"00000000";elsif rising_edge(clk) thencnt <= cnt + 1;end if;end process;count <= cnt;hold <= TMP;end Behavioral;

author: pgo
author_rank: Regular Contributor
timestamp: April 03, 2024, 07:10:53 am
content: Hi,You are using an asynchronous signal rst.When active the value in X'00.." will flow to CNT and also will flow to TMP after propagation delays.I suspect you want something like:QuotePS. I should probably be using unsigned for the counter and add conversions as needed.PPS. Please don't double-post.

author: nctnico
author_rank: Super Contributor
timestamp: April 03, 2024, 08:47:44 pm
content: As a general rule: when writing VHDL, use a numeric type (in most cases unsigned) instead of std_logic_vector for everything which is a number or an index. Yes, an address is an index as well. This way you can index arrays with less code by casting the unsigned type to an integer AND numeric types can be used in 'math' expressions directly.

author: jahonen
author_rank: Super Contributor
timestamp: April 04, 2024, 06:40:19 am
content: Generally in a VHDL process, all updates to signals happen only when process ends. So you can "change your mind" several times in a process and the last decision will remain effective. This also means that you always see the value of the signal which it had before the process started, even after you changed it (on the same execution).That means that your TMP signal will contain the value of cnt just before reset. Then cnt will be reset. This also means that cnt signal is an inferred latch, which is generally a bad idea on a FPGA. You should try to implement this synchronously, like suggested.Also note that reset signal will usually need to obey some timing constraints (recovery/removal) for the implementation to work reliably. So even if reset is "asynchronous", it still usually needs to be synchronized with the clock.Regards,Janne
Programming with Topjtag trought blacfin only - Page 1
Forum section: electronics / general

author: GGMM
author_rank: Frequent Contributor
timestamp: March 10, 2024, 07:40:13 pm
content: Hello,Some technical question:I’m still on my spansion flash programming for a Rigol 1052eWith software TopJtag i can use a Wiggler programmer. I can see in the Jtag chain the lattice Lxmo256 and the blackfin.After programming the pins, it's works but takes 10 hours for 8MB of flash!!I would like to improve the delay, I have a Usb Blaster, but TopJtagflash, does not detect the Lxmo256.You will see on this link, a whole description made by Igor.https://www.eevblog.com/forum/testgear/backup-firmware-dg1022/In particular see the connection scheme of blackfin, Lxmo256 and Spansion.So I would, and this was mentioned on the forum, (but never done) program the Spansion flash only through the Blackfin. Possible?But then what signal and static pins parameters to add on the blackfin?See the attachments of the link for all pictures of the configuration.https://www.eevblog.com/forum/testgear/backup-firmware-dg1022/Thanks

author: laugensalm
author_rank: Regular Contributor
timestamp: April 03, 2024, 05:25:49 pm
content: This used to be possible with the ICEbearPlus programmers, but they are no longer sold. I believe though that there was OpenOCD support somewhere for it that did not have to use Boundary Scan for programming. Even then, the BSCAN approach should not take 10 hours, this is probably due to the wiggler scheme with a lot of ping pong interaction that can be avoided.Maybe you could also find some stuff from GnICE legacy repositories. Unfortunately, all that stuff might be pretty orphaned.Good luck anyway!
Xil_Out32 causes my program to crash? - Page 1
Forum section: electronics / general

author: Boscoe
author_rank: Frequent Contributor
timestamp: March 31, 2024, 03:02:34 pm
content: Hi all,I created a Hello World FreeRTOS project in Vitis 2023.2 which works fine with xil_printf running with FreeRTOS timers. However, when I try to initialise AXI GPIO using the Xilinx libraries supplied in the demos, it crashes on calls to Xil_Out32 and Xil_In32. However if I build the peripheral_test example, everything works correctly. I've been over the differences between the two but I can't find anything. Even if I copy the code from the peripheral_test to my code, it doesn't work. I have checked the CMakeLists files and the linker files but the they are all the same. The values for the addresses and peripheral parameters are also identical in xParameters.h. Has anyone experienced this before?Thanks!

author: Boscoe
author_rank: Frequent Contributor
timestamp: March 31, 2024, 04:11:15 pm
content: I have looked at both launch configurations and they are identical. the ps7_init.tcl is also exactly the same for both.The only difference so far is the working peripheral_tests are on bare metal and my program is FreeRTOS. However, no FreeRTOS code gets called before the gpio_init function is called where Xil_Out32 is called and the crash occurs.

author: Boscoe
author_rank: Frequent Contributor
timestamp: March 31, 2024, 09:29:00 pm
content: So I found the issue... When creating the peripheral_test project, the latest .bit was being imported from the platform project. I wasn't regenerating the BSP when updating the platform project on my FreeRTOS project which meant the FPGA version was not being updated...On top of this it seems the updated of the bitstream in the application side of things is unreliable. Even fully regenerating the platform, cleaning and updating all parts of the application, sometimes the bitstream does not get updated. I'm now sourcing the bitstream directing from the platform project to avoid any issues here.
Verilog best way to replicate if else logic inside always block? Macros? - Page 1
Forum section: electronics / general

author: hal9001
author_rank: Regular Contributor
timestamp: March 27, 2024, 04:32:24 am
content: I want to replicate logic inside an always block. The logic contains if elses. The same logic is used a few places in the always block with only register names and parameters changing.Whats the best way to do this in Verilog (not SystemVerilog)? Im using Xilinx ISE. Maybe multi line macros can be used but I dont find examples for it in Verilog?Cheers!

author: BrianHG
author_rank: Super Contributor
timestamp: March 27, 2024, 05:17:53 am
content: Since you aren't showing us an example of what you want to replace, it is hard to make an appropriate suggestion.Have you thought about using a 'case' statement?You also have access to 'while' and 'for' loops.If you want to replicate logic based on parameters, you can even go as far as using compiler code generating directives like 'generate' and 'genvar'.If you have grouped circumstances for your 'if' statements, you can always use 'assign' to create a shortcut net/label.I mean, there is just soooo much which is possible.Probably you are looking to use the 'for' loop to operate repetitious logic on different points in an array.

author: ataradov
author_rank: Super Contributor
timestamp: March 27, 2024, 05:47:17 am
content: You can also use functions.

author: BrianHG
author_rank: Super Contributor
timestamp: March 27, 2024, 06:41:04 pm
content: You can also use `define label (replacement function)EG: (some old code of mine)Code:`define VOL_factor ( ( DAC_LSB_DB+LSB_DB_CORRECTION ) /31 ) // factor the decibel range over the 5 bit volume range.// Volume attenuation to linear amplitude formula with -infinity/basement mute correction.`define atten_dbv(x) ( (10**(((31-x)*`VOL_factor)/20) *(2**DAC_BITS-1)) )`define gain_fix ( (2**DAC_BITS-1) / (`atten_dbv(31) - `atten_dbv(0)) )`define dac_vout(z) ( (`atten_dbv(z) - `atten_dbv(0)) * `gain_fix )However, it's use cases are kinda narrow and I only use it to simplify some long esoteric calculation function down to a single final function name. I only used it for verilog coding once in my life, the example above.(The code was used to generate a table of constants based on the module's set parameter, DAC_BITS. The constants became a 32 entry rom LUT table with the width of DAC_BITS)

author: pbernardi
author_rank: Contributor
timestamp: March 28, 2024, 01:01:53 pm
content: Consider the use of ternary operators (? : )For example, in case of:Code:if (cond1)a <= value1;elsea <= value2;you can write:Code:a <= cond1 ? value1 : value2;The restriction is that the affected register must be the same on the if and else condition.as cited above, "case" may be useful in several situations as well, or even "generate". Once you did not post your code, we do not know exactly which approach is more suitable.
FPGA Bluetooth/WiFi Project - Page 1
Forum section: electronics / general

author: Razvan1203
author_rank: Newbie
timestamp: March 27, 2024, 10:48:19 am
content: Hello everyone!I'm currently working on a project where I have 2 seperate circuits. One with Arduino that has an ultrasonic sensor that capture motions and the other one with an FPGA board Nexys A7 100T with a display that displays the exact time at which the motion was detected. Both circuit are communicating via Bluetooth with the help of 2 Pmod BLE modules. I intend to use Pmod ESP32 with WiFi instead.My first question is: How can I transmit a message to my phone when a motion is detected? Essentially I am using a led on the FPGA board that turns on when the motion is detected. What options do I have in order to do that?My second question is: How can I save those clock times when the motion was detected for future purpose? I mention that I also made a digital clock so the clock is not the problem. I want that after a whole day of motion detection, I can access those clock values stored somewhere and process them elsewhere.Any answer or advice to any question is welcome! Thank you!

author: Foxxz
author_rank: Regular Contributor
timestamp: March 28, 2024, 11:16:19 pm
content: Is this a learning exercise? Why is an FPGA being used at all? Add a clock display (and LED?) to the arduino. Can't help much on the BT stuff. The "nRF Connect" app on android is a good way to freehand BT communications without writing your own app.
Design cascaded sinc filters, how to? - Page 1
Forum section: electronics / general

author: greenstrike
author_rank: Contributor
timestamp: March 22, 2024, 04:17:08 pm
content: Hi guys, I have a doubt about designing cascaded sinc filters: I read I sinc filter is created using a CIC filter.I've seen, in a decimation filter IC placed behind a sigma-delta modulator, I can use cascaded sinc filters to select desired decimation factor.Taking a look to CIC filters I need to use following register width:Register width = Input value register widt + ceiling(sinc order * log2(decimation factor)I start with 1 bit input value (modulator output), then a 5th order sinc filter, decimation factor by 8.So 1 + 5*3 = 16 bitFollowing sinc filter is a 4th order, decimation factor by 2:16+4*1=20..and so on, but taking care of following sinc filters (different orders, different decimation factors), I get up to 85 bits, while ADC output is 24 bit wide.What's wrong? Do I really work using 85 bit wide registers?Thanks.

author: dietert1
author_rank: Super Contributor
timestamp: March 23, 2024, 07:28:42 am
content: I'd guess you forgot to clip the filter result to some meaningful length after each filter stage. Your first stage filter calculation may require 16 bit yet the result has 3 significant bits as the decimation factor is 8.Regards, Dieter
DDR3L -> DDR3 compatibility - Page 1
Forum section: electronics / general

author: rgc_
author_rank: Newbie
timestamp: March 13, 2024, 03:41:28 pm
content: Hello folks,I have been using Micron DDR3 chips in A7 series. Sadly, part availability for 256x16 are going low and prices rocket.OTOH, same chips in DDR3L are available and well priced (would they be phasing out 'high-voltage' DDR3 chips?).MIG seems to have a different clock period for DDR3 and DDR3L (400 vs 333 MHz), which is ungood.However, the DDR3L parts are supposed to be 'backwards compatible to DDR3' (or voltage-compatible). So my question:Can I just use a DDR3L part, power the bank with 1V5 and party?Bestrgc

author: wasedadoc
author_rank: Super Contributor
timestamp: March 13, 2024, 06:04:33 pm
content: This sub-forum is for FPGA topics. "Everything programmable logic related. FPGA's, PLD's, VHDL, Verilog etc"DDR3 and DDR3L are RAM, not FPGA etc

author: rgc_
author_rank: Newbie
timestamp: March 13, 2024, 06:43:38 pm
content: I am kindly asking connecting a DDR3L to an Artix 7 FPGA :-)

author: asmi
author_rank: Super Contributor
timestamp: March 14, 2024, 09:17:17 pm
content: Quote from: rgc_ on March 13, 2024, 03:41:28 pmYes you can, and here is the proof:https://www.eevblog.com/forum/fpga/planningdesignreview-for-a-6-layer-xilinx-artix-7-board-for-diy-computer/msg5134983/#msg5134983(Note the SODIMM is DDR3L 1.35 V yet it's powered by 1.5 V).Any DDR3L device is guaranteed to work as DDR3 one with the same timings. Also - as long as you use JEDEC timings (which is what MIG does), you can use DDR3/DDR3L device from any vendor as long as it's got the same internal organization (say 256Mx16) and the same speed grade (or better) as the device you've chosen in MIG. For example, right now there are plenty of cheap DDR3L devices from Kingston on Mouser, you can use them instead of Micron parts with no problems.

author: rgc_
author_rank: Newbie
timestamp: March 16, 2024, 12:30:32 am
content: Thank you asmi, great info. Much appreciated./rgc
Detection of damaged pins of FPGA - CYCLONE V - 5CSEBA2U23I7SN - Page 1
Forum section: electronics / general

author: ieeeHuseyin
author_rank: Contributor
timestamp: March 08, 2024, 05:21:35 am
content: I think some pins of the FPGA on the PCB are damaged.I could not detect the problem on the PCB.I separated the FPGA from the pcb.Is there any test I can do to find damaged pins of the FPGA (e.g. with a multimeter)? (cycloneV.jpg)

author: NiHaoMike
author_rank: Super Contributor
timestamp: March 14, 2024, 02:21:07 am
content: You could measure the ESD diodes, a damaged one will read higher or lower than the rest. You can also check for leakage, a damaged gate will tend to show substantially more than usual.
Bram Memory Size Configuration - Page 1
Forum section: electronics / general

author: Rainwater
author_rank: Regular Contributor
timestamp: February 08, 2024, 11:46:56 pm
content: Dev Board: tang nano 9kDataSheet:http://cdn.gowinsemi.com.cn/DS117E.pdfpage 35-36 table 2-4The datasheet page 35 says each block of bram is 18,432bits. Page 36, Table 2-4 shows a configurable block size of "2K x 8". Is this table an approximation of the the bits available, or a hard value? Do I lose 2,432bits just by using this a "2k x 8" configuration?I have noticed this trend in many datasheets.

author: hamster_nz
author_rank: Super Contributor
timestamp: February 09, 2024, 12:55:00 am
content: It is normal for block ram to have a 'parity bit', allowing a 9-bit, 18-bit or 36-bit interface.See section 2.2 ofhttps://cdn.gowinsemi.com.cn/UG285E.pdffor allowed modes.

author: Rainwater
author_rank: Regular Contributor
timestamp: February 09, 2024, 09:07:53 pm
content: Thank you for the info, seams like an easy question, after reading the ds again and the user guide you posted, there is not a simple yes or no answer as I was expecting. It looks as tho, in the mode I want only 2048 bytes (16384 bits) will be available.Even more details than the datasheet, page 13, heres another "got ya" I missedQuoteThis leads me to ask about usage, specifically addressing, on page 11(same page you referenced). When I assert an address onto the .... wait, page 26, example code....Thank you again hamster_nz.

author: Rainwater
author_rank: Regular Contributor
timestamp: February 28, 2024, 01:24:56 am
content: Quote from: hamster_nz on February 09, 2024, 12:55:00 amIs there a standard to the parity bit position?That question just feels vague.It looks as tho there will be a parity bit for every 8 bits(byte). 8+1=9 2(8+1)=18 4(8+1)=36What in trying to ask is, all the parity bits all grouped together at the end of the register, or distributed after each byte?Or just personal preference?

author: Someone
author_rank: Super Contributor
timestamp: February 28, 2024, 01:41:01 am
content: Parity Bits** serving suggestionIts just a 9/18/36/72 bit wide ram with 2^n addressing, you can use the bits however you want.
ice40 ultra icecube2 software does not recognize my input constraint - Page 1
Forum section: electronics / general

author: eds
author_rank: Newbie
timestamp: February 22, 2024, 08:06:20 am
content: Hi, please bear with me as I have been struggling with lattice softwares as I am used to Xilinx. I have been using icecube2 for a project. It was working fine but yesterday I have encountered this problem where the software automatically deletes my constraint specification saying that it is unconnected. Below is the warning it gives me and also I have added my code where I use the FPGAKONE_SDI inside a module as SDI. I connect the input FPGAKONE_SDI directly from the top module to this module I added.Update: I have written a check algorithm where I need to check the register (and output the check as an STD_LOGIC) I have loaded with my input and the constraints seem to be working fine with that.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 23, 2024, 10:49:03 pm
content: Without seeing both the code that defines the entity and the code that instantiates it, there's nothing we can say.

author: eds
author_rank: Newbie
timestamp: February 26, 2024, 06:51:53 am
content: I deleted my code as I have found my problem, and wanted to inform people who will come across with the same problem.
Phase sync two same frequency input's ? - Page 1
Forum section: electronics / general

author: sunilsha
author_rank: Newbie
timestamp: December 13, 2023, 04:44:59 pm
content: I am trying to implement a phase correction verilog module for two clock inputs coming into my cycloneiv fpga.My module hasTwo clock signals, clock_1 and clock_2 with frequency 8Khz from different clock sources that are input to the fpga pins, and a ref_clk 25Mhz to sample the signals. I have an output of the module phase_sycned_out.Requirement:I need to come up with a verilog logic which preserve's the phase information of clock_1 and then uses the standalone clock_2 to delay clock_2 by the necessary cycles so as to match the clock_1's phase. This delayed clock_2 is to can be further output on phase_synced_out of the fpga. This is the 1st step of my problem.Regards-sunilsha

author: Rainwater
author_rank: Regular Contributor
timestamp: February 20, 2024, 11:45:07 am
content: Would measuring phase difference between two digital inputs of he same frequency would be as simple as measuring the time between rising edges or am I missing something?

author: hamster_nz
author_rank: Super Contributor
timestamp: February 20, 2024, 11:02:13 pm
content: The easiest way I could see is a 4096 x 1 bit memory - that allows for up to 163us of delay.A free-running write counter in the 25MHz domain is used to write the reference signal to the memory.An offset behind the write counter is used to read the memory, and send to the output.You have a phase comparator comparing the input and output, and use that to adjust the offsetCode:on a clock_25MHzram <= ref_input;ref_output <= ref_input;tracking_output <= ram[wr_addr - delay/64];# Rising edge of ref clockif ref_output = '0' and ref_input = '1' thenif tracking_output = 1 then#we are leading, so increase the delaydelay++;if tracking_output = '0' then#we are lagging, so decrease the delaydelay--;wr_addr++;Note that such a thing will only work if both of the slow clocks come from the same reference - if not, eventually you will need to skip / insert an extra cycle to keep synced.You could code it a lot more subtilly than this, but as a 0th approximation it should be workable.
Opal Kelly 7310 Pin Mapping - Page 1
Forum section: electronics / general

author: loftusmi
author_rank: Newbie
timestamp: February 20, 2024, 04:25:14 pm
content: Hello,I'm designing a PCB to interface with an OpalKelly XEM7310 that I plan to configure with some open source firmware. I'm trying to connect the PCB traces to the correct pads for the PCB/XEM7310 pin connector so that the firmware will not require modification for different pins. However, I'm not finding an I/O pin map for the XEM7310 online like one might find for a microcontroller. Opal Kelly does explain which MC1/MC2 pin that the FPGA maps to, but I don't see where it says which MC1/MC2 pin is which on the XEM7310 (nor do I really understand what MC1/MC2 means). Am I misunderstanding something about the way FPGA pins work or have I not found the proper documentation yet? If it's the latter case, does anyone know where I can find the pin map that I'm looking for?OS Firmware Documentation:https://intantech.com/files/Intan_RHD_XEM7310_interface.pdfPCB/XEM7310 pin connector:https://www.samtec.com/products/bteOpal Kelly XEM7310 Pin Reference:https://pins.opalkelly.com/pin_list/XEM7310

author: Simon
author_rank: Unknown
timestamp: February 20, 2024, 04:52:31 pm
content: please do not double post. You will be hated by all.https://www.eevblog.com/forum/beginners/opal-kelly-7310-pin-mapping/msg5345552/#msg5345552
FPGA based SSDs - Page 1
Forum section: electronics / general

author: NiHaoMike
author_rank: Super Contributor
timestamp: February 18, 2024, 06:46:26 pm
content: I recently got some PCIe SSDs based on FPGAs, a 365GB ioDrive2 for $33 and a 2.6TB ioMemory PX600 for $68. The ioDrive2 is based on a Virtex 6 and the ioMemory a Virtex 7. The ioDrive2 could be repurposed by designing a board to fit the memory board sockets. Other than that, the only other reuse I can think of are those that would do well with a large FPGA coupled to a large amount of Flash memory, maybe some crypto mining or AI would fit that description with the Flash containing massive lookup tables.From my understanding, the Virtex 6 can be used with the free unlocked "Windows 10" ISE. The Virtex 7 might as well but I think it's intended for Vivado of which only the paid version supports it.
DE10-Lite Problems with 7-Segment Display - Page 1
Forum section: electronics / general

author: dieciduej
author_rank: Newbie
timestamp: September 19, 2023, 04:36:48 pm
content: Has anyone run into the issue of one of the on-board 7-segment displays not working? We are using the DE10-Lites in our Digital Logic course for several years now with little to no problem. Now within the past year several of our boards are having one or two of the 7-segment displays no longer working, not the whole segment just some of the elements of the segment. There doesn't seem to be a pattern to it, IE the same 7-segment across the boards and so on. If I look closely at the non-working segment it appears to be discolored slightly. I haven't taking to unsoldering the display and installing an new one yet.If any one has some insight to the problem please let me know.Thanks,JoeD

author: colorado.rob
author_rank: Frequent Contributor
timestamp: September 19, 2023, 09:14:22 pm
content: Have you asked Terasic about it? They should be able to tell you if it is a known problem, what would cause it, and maybe how to prevent it from happening.

author: dieciduej
author_rank: Newbie
timestamp: September 20, 2023, 11:56:40 am
content: Someone had already posted the same problem on there/Intel forum with no real results, other than send it back. When I get a chance I have to see if I get a signal on the pins in question.JoeD

author: amine
author_rank: Newbie
timestamp: February 12, 2024, 03:48:53 pm
content: This appears to be a common fault, maybe due to a short, since the bottom of the board is usually exposed.Replacing the faulty 7 segments will fix the problem.Also, better think of protecting the bottom side with some anti-static cover.Regards
VHDL Port Declaration issues in Lattice Diamond - Page 1
Forum section: electronics / general

author: MuriTheMyth
author_rank: Contributor
timestamp: February 03, 2024, 05:02:46 pm
content: Hi folks:I'm new to Lattice Diamond and I ran into some weird problem when trying to work in there.As shown in the picture, the port "clk" and "s" are declared in the same line. But the first script with "clk" in line 17 passed the syntax check, and the second with "s" in the same place failed.I tried to search online and I still can't see why.A big thank you for your time and patience in advance.Sincerely,Muri

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 03, 2024, 08:17:01 pm
content: Shouldn't it beCode:architecture bhv of srlatch

author: coppercone2
author_rank: Super Contributor
timestamp: February 03, 2024, 08:23:24 pm
content: I would consider bribing the port authority
Jtag with Wiggler - Page 1
Forum section: electronics / general

author: GGMM
author_rank: Frequent Contributor
timestamp: February 18, 2024, 03:51:50 pm
content: Hello,Do you know if there is a possibility to program faster with Topjtag. (Modified version or other soft)I explain, I have a wiggler programmer (said the poor man’s programmer Lol) and my Topjtag 1.3.3 version (date of 2012!!) only allows a maximum speed of 200K max in choices with a Wiggler.So it takes about 5 hours to program a 4mo flash.It’s not a problem for me, just start programming at night, but if we could move faster....Thank'scdt
$20 FPGA board with 2x8 PCIe and 2x QSFP - Page 1
Forum section: electronics / general

author: NiHaoMike
author_rank: Super Contributor
timestamp: December 09, 2023, 12:15:37 am
content: https://www.ebay.com/itm/265967136205Too bad (from what I can tell from a quick search) it requires the paid version of Quartus to use...

author: liaifat85
author_rank: Regular Contributor
timestamp: December 14, 2023, 03:54:48 pm
content: Have you used this board?

author: CJay
author_rank: Super Contributor
timestamp: December 14, 2023, 06:21:20 pm
content: For $20 I'd buy the thing and store it away for a little while until the free tier of Quartus supports it, heck if they shipped to the UK there'd be a couple on the way already.

author: ejeffrey
author_rank: Super Contributor
timestamp: December 16, 2023, 05:28:11 pm
content: At least some random person on Reddit says it's a stratix V. That's likely never going to be supported by the free version of quartus.

author: paf
author_rank: Regular Contributor
timestamp: December 17, 2023, 08:55:04 am
content: First one of a series of posts here:https://j-marjanovic.io/stratix-v-accelerator-card-from-ebay.html

author: daybyter2
author_rank: Newbie
timestamp: January 03, 2024, 09:17:18 pm
content: Got this board here. I am looking for other tinkerers to play with this board.

author: Wiljan
author_rank: Regular Contributor
timestamp: January 04, 2024, 12:44:39 pm
content: Quote from: daybyter2 on January 03, 2024, 09:17:18 pmGot the board here as wellWin10Quartus 15.0 with Stratix V devices installed and can compile projects.Quartus 20.1 lite programmer with a clone USB blaster connected to J5 (pretty slow)https://github.com/tow3rs/jtag-mpsse-blasterCompiled in VS2019 and copied the "jtag_hw_mpsse.dll" to the ALTERA\20.1\quartus\bin64 folderNow the you can program over the USB cable way faster and don't have to find a 2x4 2.0mm pitch IDC connectorWhat kind of project do you have in mind?

author: daybyter2
author_rank: Newbie
timestamp: January 04, 2024, 09:51:53 pm
content: Wow! Seems like you are a lot further than me. I only programmed the cyclone 2 mini dev board and my de0 nano cyclone 4 board so far.I write tradebots (currently mainly for crypto) and want to implement some of the code as verilog in a fpga. Would like to code ethernet connections etc.PS: sent you a PM

author: Alde
author_rank: Newbie
timestamp: February 19, 2024, 09:14:44 pm
content: https://www.ebay.com/itm/155967025111I wonder if anyone tried this board? Is it amd/intel based?

author: NiHaoMike
author_rank: Super Contributor
timestamp: February 20, 2024, 01:40:20 pm
content: Quote from: Alde on February 19, 2024, 09:14:44 pmI could not find any reference as to what FPGA it uses so it's a gamble as to whether or not it would work with the free tools.