CYCLONE V HPS - ACCESS SDRAM CONTROLLER SUBSYSTEM OVER JTAG WITH OPENOCD - Page 1
Forum section: electronics / general

author: ieeeHuseyin
author_rank: Contributor
timestamp: August 04, 2023, 12:31:32 pm
content: Hello,I tried some scenarios as shown below.However, I couldn't access the SDRAM controller subsystem completely. (forexample; 0xFFC25000 address => Controller Configuration Register)Which registers do I need to configure to access the SDRAM controller subsystem via JTAG?Is there a register list available for this purpose?All registers are available in the link below.However, which registers do I need to configure?https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.htmlThanks.

author: tru
author_rank: Regular Contributor
timestamp: August 04, 2023, 02:01:27 pm
content: You're referring to the existing DDR-3 on a development board kit, such as DE-10 standard/nano or Intel/Arrow SoC Kit?AFAIK, the DDR-3 on the PCB is wired to the SDRAM controller IP (module) for the ARM dual core Cortex A9 processor side (HPS), it is not an IP on the FPGA side. It requires initialisations on the processor side. I guess the minimum initialisation could be setting up the PLLs and enabling the SDRAM - I've not done this myself, but I would leave this to U-Boot.Some background, the initialisation for the processor side (peripherals and system stuff) is commonly known as board initialisation, and is normally carried out by U-Boot. In the past, as an alternative you could use Altera's (now Intel's) minimal board initialisation example program, which is called MPL (Minimal PreLoader), but seems they have removed it from their HWLIB (library) - just stick with U-Boot.Unfortunately, it is not a simple matter of writing a few registers. If you really want to know how to configure it you will need to look at the board initialisation code for Cyclone V in the U-Boot or MPL source code.In summary, you will need to boot a pre-configured U-Boot (pre-configured to your specific board) first. There are a number of ways to boot U-Boot:a. a micro SD Card (with U-Boot on it)b. or the NAND flash (with U-Boot on it)c. JTAG with OpenOCD or GDB and load U-Boot SPL (you only need the preloader) from a file located on the hostOnce booted you can then access and use the SDRAM from JTAG.The instructions for setting up and compiling U-Boot can be found here:https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10References:Intel's U-Boot fork:https://github.com/altera-opensource/u-boot-socfpgaIntel's baremetal HWLIB library:https://github.com/altera-opensource/intel-socfpga-hwlib

author: ieeeHuseyin
author_rank: Contributor
timestamp: August 04, 2023, 02:27:37 pm
content: The board I am using has the 5CSEBA2U23I7SN chip, and the DDR3L RAMs(MT41K64M16TW-107) are connected to the HPS.In fact, my goal is to conduct JTAG boundary scan tests to detect board faults such as open circuits, short circuits, etc. I am developing a system for this purpose. I can test the GPIOs using JTAG boundary scan, but I haven't been able to access the DDR3L RAMs via JTAG.According to what you've mentioned, the option C seems to be the most reasonable for me.I will examine it as soon as possible and get back to you.By the way, I had conducted a similar experiment for ERTEC200 before. I was able to connect via JTAG and control the EMIF (External Memory Interface) unit using openocd. I assume this process might be a bit more complex for Cyclone V. Am I correct in this assumption? Nonetheless, it's encouraging to hear that such operations can be carried out through JTAG for Cyclone V.For ERTEC, I had established access via openocd as follows:haltsleep 500mww 0x70000008 0x00000420

author: ieeeHuseyin
author_rank: Contributor
timestamp: August 25, 2023, 08:09:05 am
content: I performed a DDR RAM test attempt with u-boot for my PCB with 256MiB memory.When I select HARDWARE_DIAGNOSTIC in bsp-editor.exe for this purpose, I receive a warning as follows: "At least 1GB memory required."Nevertheless, I can still generate and create the preloader. However, I encounter an error as shown in the attached image.What approach should I follow to test DDR systems below 1GB?

author: ieeeHuseyin
author_rank: Contributor
timestamp: August 25, 2023, 11:27:44 am
content: In the "Cyclone V Hard Processor System Technical Reference Manual" PDF, there is a sample code provided for testing SDRAM with the preloader.I have attached the image below.When I executed this code, I encountered a verification error. Upon inspecting the code, it seems that they might have incorrectly incremented the "cnt" value in the "read" and "write" loops.It worked correctly when I modified the "for" loop in the "read" section to be "cnt++".Is it normal to have errors in the code provided in the PDF, or am I misinterpreting certain parts of it?

author: tru
author_rank: Regular Contributor
timestamp: August 26, 2023, 02:28:18 pm
content: I have not had a chance to try out Intel's DDR RAM test program (no spare time), but my guess is yes. I have seen mistakes in their HWLIB (baremetal library).I see that you are following the old build flows, with older versions of their tools.I have only experience with a DE-10 Nano dev kit, which has 1GB of DDR SDRAM (2x 512MB), but it has the same Cyclone V SoC family FPGA as yours. The RAM is different, so you will need generate Quartus Prime handoff files from Platform Designer (formerly QSys) with the correct RAM settings in EMIF tab within the HPS component.Not sure if it will help you, but some useful scripts and notes (using new build flow) can be found from my github files:https://github.com/truhy/de10nano-scriptsUsing my scripts you can build your own U-Boot-SPL, suitable for loading and running with OpenOCD. You can then also run your elf, e.g. the DDR RAM tester app all from JTAG.There is also OpenOCD config files for the DE10-Nano. I am using the USB Blaster II JTAG, so for your case, a different JTAG, you will need to create a suitable JTAG config file - that's if you don't already have one.

author: ieeeHuseyin
author_rank: Contributor
timestamp: September 05, 2023, 12:34:46 pm
content: I tried an experiment with the config file at the link.(https://github.com/truhy/de10nano-scripts/blob/main/openocd-config-scripts/target/altera_fpgasoc_2_with_comments.cfg)However, I couldn't establish a connection with the HPS.I'm getting an error that says, "Debug regions are unpowered, an unexpected reset might have happened."I have attached the files I used. (files.zip)What could be the cause of this error?

author: tru
author_rank: Regular Contributor
timestamp: September 05, 2023, 08:04:54 pm
content: The message suggests that the HPS is rebooting before OpenOCD has a chance to initialize and halt.Attached is my successful connection with the DE10-Nano board (Cyclone V SoC). Perhaps nothing related, I am using the USB Blaster II compared to your USB Blaster (version 1). Also, I have no program running when I run OpenOCD, both the on board SD Card slot is empty and flash is not selected from booting (via config switches).Is your system booting up a program by any chance, e.g. from flash? If so, it could be starting a watchdogPerhaps tryCode:openocd.exe -f altera-usb-blaster.cfg -f hps.cfg -c "init; halt;"Or, try issuing a HPS warm reset command, then halting it straight away.Code:openocd.exe -f altera-usb-blaster.cfg -f hps.cfg -c "init; halt; mww 0xffd05004 0x00100002; halt;"

author: ieeeHuseyin
author_rank: Contributor
timestamp: September 06, 2023, 07:41:31 am
content: I am using QSPI flash for booting up in my system.The following seems to be working. Thank you.Code:openocd.exe -f altera-usb-blaster.cfg -f hps.cfg -c "init; halt;"However, one part I didn't quite understand is this:The size of the preloader I created is 256KB (262,144 bytes), and the file type is binary (preloader-mkpimage.bin).In this case, can I perform the upload without an elf file?When I try this, I get the error I mentioned in the attachment.Code:load_image preloader-mkpimage.binAlso, when I look at the Cyclone V reference manual, it states that the HPS OCRAM size is 64KB.My binary file is 256KB. So, it seems like it won't fit into OCRAM.Is there another setting I need to adjust during preloader generation?

author: tru
author_rank: Regular Contributor
timestamp: September 06, 2023, 10:23:07 am
content: Yes, you're right about the OCRAM. The preloader-mkpimage.bin is too big to load directly to the 64KB OCRAM to initialise the board.I assume it was created by Qsys. The preloader-mkpimage.bin is actually a combined file. It is just U-Boot-SPL (the preloader) at the start of it, with the SDRAM tester program (in mkimage format with magic header) tacked to the end of it multiple times (I think).To load from OpenOCD directly, you need to use the original files instead:U-Boot-SPL (elf or bin)SDRAM tester program (elf or bin)Perhaps Qsys keeps the original files in the output folder?If not, you will need to build/make them yourself from sources.For U-Boot-SPL I will upload a pre-built version to my github later tonight.If you're ok with linux, you can build the U-Boot-SPL yourself. If using Ubuntu, try using my bash shell scripts:https://github.com/truhy/de10nano-scripts/tree/main/de10nano_ocram_uboot_spl_build_scriptsSee my readme files, there are some helpful notes on necessary configurations.

author: ieeeHuseyin
author_rank: Contributor
timestamp: September 06, 2023, 11:48:13 am
content: I found the "u-boot-spl.bin" file (size 41144 bytes, smaller than OCRAM size).However, I encountered a similar problem when loading this file (see "error2.png").Actually, for now, I can overlook this issue. First, I will need to focus on the other issue.I can conduct my experiments using "quartus_hps.exe". I write the binary file to the QSPI flash using "quartus_hps.exe", and after turning the system's power off and on, the preloader code I have modified for testing starts working. I observe to the test messages via UART.Code:quartus_hps.exe -c1 -a 0x00000000 -o P "preloader-mkpimage.bin"There are two functions used in the "spl.c" file.One is "sdram_calculate_size()", and the other is "get_ram_size(...)".When I run them and observe the results on UART, I see differences.Why don't both of them show 256 MiB? (see "error3.png")On the PCB, there are two 128 MiB SDRAMs.The debug messages show the SDRAM capacity as 256 MiB, which is actually correct.However, when I try to write and read data from the SDRAM for testing, I can only access the first 128 MiB.I can't write data to the second part.Code:// spl.c...sdram_size = sdram_calculate_size();printf ("\n\nsdram_size = %x - get_ram_size() = %x \n\n" , sdram_size, get_ram_size(0, sdram_size));/* Sanity check ensure correct SDRAM size specified */puts("SDRAM: Ensuring specified SDRAM size is correct ...");if (get_ram_size(0, sdram_size) != sdram_size) {puts("failed\n");hang();}puts("passed\n");/** A simple sdram memory test* If you want more coverage, change the argument as below* SDRAM_TEST_FAST -> quick test which run around 5s* SDRAM_TEST_NORMAL -> normal test which run around 30s* SDRAM_TEST_LONG -> long test which run in minutes*/if (hps_emif_diag_test(SDRAM_TEST_FAST, 0, sdram_size) == 0)hang();...

author: tru
author_rank: Regular Contributor
timestamp: September 06, 2023, 12:39:04 pm
content: If using a binary file you need to tell OpenOCD to load it to the start of the OCRAM, so the command is:Code:load_image u-boot-spl.bin 0xffff0000Then you need to jump to that location using the resume command:Code:resume 0xffff0000Is this part of the memory tester program?https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/enabling-simple-memory-test.htmlI wonder if the DRAM banks needs changing?*Correction: I've just realised that I mentioned Qsys in previous post, I meant BSP editor.

author: tru
author_rank: Regular Contributor
timestamp: September 06, 2023, 12:43:45 pm
content: Ouch, I forgot that U-Boot SPL defaults to a hang function and also enables watchdog. The provided U-Boot SPL will reboot. In my github, I have a patched U-Boot contributed source (spl_gen5.c) which disables the watchdog and stays in the hang function.

author: ieeeHuseyin
author_rank: Contributor
timestamp: September 07, 2023, 08:50:30 am
content: Here are the links I referenced for DDR tests:page - 274 [Writing a Predefined Data Pattern to SDRAM in the Preloader] -https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/hard-processor-system-technical-reference.htmlhttps://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/enabling-simple-memory-test.htmlI updated the SDRAM size as follows.Code:// socfpga_common.h#define PHYS_SDRAM_1_SIZE0x10000000//256MBIn the spl.c file in the u-boot version I use, there is a block of code like this:Code:/* detect the SDRAM size */#ifdef CONFIG_SDRAM_CALCULATE_SIZEsdram_size = sdram_calculate_size();#elsesdram_size = PHYS_SDRAM_1_SIZE;#endifWhen I run the code, the line "sdram_size = sdram_calculate_size();" is active.Therefore the variable "PHYS_SDRAM_1_SIZE" becomes irrelevant.But the result of the function "sdram_calculate_size()" is 256MB, so it is correct.Then, when I examine the contents of "spl.c", there is a block of code like below:Code:#if (CONFIG_PRELOADER_HARDWARE_DIAGNOSTIC == 1)/* Sanity check ensure correct SDRAM size specified */puts("SDRAM: Ensuring specified SDRAM size is correct ...");if (get_ram_size(0, sdram_size) != sdram_size) {puts("failed\n");hang();}puts("passed\n");/** A simple sdram memory test* If you want more coverage, change the argument as below* SDRAM_TEST_FAST -> quick test which run around 5s* SDRAM_TEST_NORMAL -> normal test which run around 30s* SDRAM_TEST_LONG -> long test which run in minutes*/if (hps_emif_diag_test(SDRAM_TEST_FAST, 0, sdram_size) == 0)hang();#endif /* CONFIG_PRELOADER_HARDWARE_DIAGNOSTIC */According to the BSP Editor, you need at least 1GB of ram to activate the HARDWARE_DIAGNOSTIC feature (warning_bsp-editor.png - I already added this picture before).I tried anyway by removing the "CONFIG_PRELOADER_HARDWARE_DIAGNOSTIC" condition, but the result of the get_ram_size function is 128MB.I also experimented as follows."maxAdr = 0x2000000" => there is no problem => test_success_log.txt - test_success_code.txt"maxAdr = 0x4000000" => there is an error in verify => test_error_log.txt - test_error_code.txtI don't know if the exact problem is that I have less than 1GB of ram as the BSP editor says or something else!

author: tru
author_rank: Regular Contributor
timestamp: September 07, 2023, 08:34:06 pm
content: Have you double checked that your HPS SDRAM settings are correct, under Platform Designer (formerly Qsys) of the fpga project you're using (Quartus Prime)?Perhaps it is set to use only 1x 128MB chip?The BSP editor relies on the files (handoff files) that the above generates.Attached is setting for DE10-Nano board, which has 2x 512M DDR-3 (IS43TR16256A-15HBL) chips.

author: ieeeHuseyin
author_rank: Contributor
timestamp: September 08, 2023, 06:56:43 am
content: I have attached the settings of the project I used and the sdram connection schematic below."Total interface width" is selected as 16.Is that why I can't access all 256MB?