Logic gate translation - Page 1
Forum section: electronics / beginners

author: pyromaniac4382
author_rank: Contributor
timestamp: September 24, 2014, 02:42:39 pm
content: Hi,I am currently trying to simplify my schematic by reducing the number of chips I need (74 series logic). I noticed that I am only using one inverter, and want to eliminate this chip addition. I have an open 74LS74 D-type flip flop, and was wondering if I could somehow wire this as an inverter, take in a value, and spit out the inverse. Any help would be greatly appreciated. If I cannot eliminated this chip I will probably move to using a general purpose transistor to do the inversion. Thanks.

author: Simon
author_rank: Unknown
timestamp: September 24, 2014, 02:44:25 pm
content: If you have a negated output maybe but it will only respond to the input on clock transitions. We need a bit more information.

author: fcb
author_rank: Super Contributor
timestamp: September 24, 2014, 03:01:29 pm
content: A guarded yes. It will depend on what you want to do with the inverted signal.If you have a high frequency lying about your board (say a tap off a xtal oscillator), then you could just feed that to the clock input on your spare 74LS74, then use the _Q output to give you an inverted version of the D input.You will get clock related jitter - but it might not matter in your application, and of course the Ic of your 74LS74 will shoot up with a fast clock.More info required really.

author: pyromaniac4382
author_rank: Contributor
timestamp: September 24, 2014, 04:02:46 pm
content: Trying to invert a high address line (A15) on a Z80 to feed an OR gate with /MREQ signal to create a /RAMCE to enable the RAM chip only when the address the Z80 spits out is above 7FFFH and there is currently a memory request. (0000H -> 7FFFH ROM && 8000H -> FFFFH RAM)I currently was using a 74LS14, but wanted to eliminate this chip from the design while making use of the spare 74LS74 flip-flop which is un-used to keep chip count down.Going to be running at 10MHz Xtal Oscillator system clock.

author: fcb
author_rank: Super Contributor
timestamp: September 24, 2014, 05:21:22 pm
content: It's been so long since I did any Z80 work I couldn't say for sure - the 74LS74 is +ve triggered though and this will probably mean that the inverted address line will lag a cycle behind the reset. The Z80 also uses the +ve edge of the clock.Do you access to the inverted clock, I reckon that would work, or perhaps even arrange a little passive RC network to delay the clock to the 74LS74 by some small amount.Can't you test it out prior to layout?

author: David Hess
author_rank: Super Contributor
timestamp: September 24, 2014, 08:14:03 pm
content: It is probably not good practice but you might get away with wiring -set or -reset in parallel with the clock input so when the input goes high, D is transferred to Q and -Q and when the input goes low, Q and -Q are set or reset. Wire D to the appropriate level depending on if you are using -set or -reset and you have both an inverting and non-inverting buffer.The datasheet I have does not describe any limits to the timing between the clock and -set or -reset but if there is a problem, a small RC delay could be used to delay the clock input.

author: DJohn
author_rank: Regular Contributor
timestamp: September 25, 2014, 02:23:10 pm
content: I remember the Commodore 64 used this trick in its clock generator: there was a spare half of a '74, but no inverters nearby.Looking at the datasheet for TI's 74LS74 (http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn54s74&fileType=pdf), I can't see a nice way of doing it. If you keep CLK stable (at either level), put anything you want into D, and keep /CLR low, then Q will follow the inverse of /PRE. But there's a warning attached to the /PRE=L state saying that the output levels are not guaranteed to meet the specified values.NXP's 74HC74 datasheet (www.nxp.com/documents/data_sheet/74HC_HCT74.pdf) has a similar table on page 4. This time there's no problem: in that configuration it's specified to work as an inverter. They give the propagation delay for one edge, but not the other.If you must use the LS version, it'll probably work, but I wouldn't put it in a commercial product (although Commodore did). I don't see a problem with HC or HCT, as long as you don't mind not knowing how slow it is.