Gate driver keeps blowing up - Page 1
Forum section: electronics / projects

author: leblanc
author_rank: Regular Contributor
timestamp: November 15, 2022, 08:42:43 pm
content: I'm using the FAN7390 for driving PMSM/BLDC motors. For some reason, I keep blowing up these gate drivers and I can't figure out why.I'm fairly confident that the control signals allow for plenty of dead time (I tentatively set it to 500ns, which I believe is overkill). My VBUS is way lower than the max for the part (600V).After it's damaged here's what I observe. The FAN7390 heats up when I try to use it to control a motor. Simply applying a load to the phase (just a ~22 ohm resistor between PHA and GND) makes it heat up even when the control signals are both low. Even if I remove VBUS and power the 15V separately this still happens. So somehow when it's damaged, the gate driver provides a path from +15V to the phase. Applying a load across VBUS and GND also makes it heat up.Here's a snippet of the schematic (with no-stuffs removed, etc.):

author: jonpaul
author_rank: Super Contributor
timestamp: November 15, 2022, 09:36:18 pm
content: suspect RF, VHF parasitic oscillatons, increase R2,R3 100 ohmsj

author: Psi
author_rank: Super Contributor
timestamp: November 15, 2022, 09:39:11 pm
content: Also a TVS diode across the IC VCC/GND might be a good idea.Who knows what back EMF voltage spikes that motor is pushing onto the IC supply rails through the body diodes.Assuming the 15V is derived from Vbus somewhere else in the circuit.

author: 741
author_rank: Frequent Contributor
timestamp: November 15, 2022, 09:45:51 pm
content: HiI had a look for applications information for that i.c. and found nothing.TI offer a chip promoted as very similarOn p32 here (https://www.ti.com/lit/ds/symlink/ucc27714.pdf), they say "...The LO and HO driver outputs may exhibit output overshoot beyond the VDD or HB level or output undershoot below COM or HS. This overshoot and/or undershoot is typically due to the high di/dt during switch transition and parasitic inductance...If the driver output overshoot or undershoot exceeds the datasheet limits...the driver output can be in the incorrect state..."Agree with JeanPaul about raising gate resistors somewhat (my reasoning is maybe gate charge comes back into the driver, but I am unsure that is valid...)

author: uer166
author_rank: Super Contributor
timestamp: November 15, 2022, 09:50:55 pm
content: Often the negative transient on the Vs node is what gets you. Lots of crappier gate drives have an absolute max rating of GND-0.3V there. The datasheet infuriatingly doesn't give that number directly, but reading between the lines, and looking at internal schematic, this is likely one of those parts. You need to measure the Vs node relative to GND to make sure it doesn't go too far down below GND. If it does, tackle the transient, or better yet, choose a better gate drive where the abs max is GND-4V or something decent.

author: xavier60
author_rank: Super Contributor
timestamp: November 15, 2022, 10:03:02 pm
content: I use a fully galvanically isolated Gate driver, STGAP2DMTR.Precautions still need to be taken to prevent the negative spikes from over charging the bootstrap capacitor.Some resistance in series with the diode, 10Ω, and a 47uF electrolytic in parallel with a 100nF ceramic for the bootstrap cap in my current project.I do the same for the low channel also.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 15, 2022, 10:09:52 pm
content: Show layout.

author: DavidAlfa
author_rank: Super Contributor
timestamp: November 15, 2022, 11:28:06 pm
content: Switching capacitive loads like fet gates cause a lot of current trasients, try adding more caps to the VDD pin, 100nF+100nF+10nF+1nFAlso 1R for gate is too low, probably causing a lot of ringing. 10-22R is more typical.Don't you have a scope to watch these signals?

author: jmelson
author_rank: Super Contributor
timestamp: November 16, 2022, 05:24:36 pm
content: I build motor drives. I use IR half-bridge driver chips. One of the issues with these chips is if the high-side source goes below ground by more than a certain amount, it activates parasitic paths through the chip that are destructive. I had to put big ultra-fast diodes across the lower transistor to clamp any negative transients on that node. I assumed the FET's body diode would clamp this, but using a digital scope and crreping up on the condition, I could see that the body diode could be forward biased by up to 6 V or so, for several microseconds without conducting! You might check the datasheet to see if your driver chip has the same limitation. The root cause is inductance. When the high-side transistor is sourcing current to the load, inductance will continue flowing current out of the common node, driving it negative during the deadtime.Jon

author: jmelson
author_rank: Super Contributor
timestamp: November 16, 2022, 05:29:56 pm
content: Yup, they have the same restriction, Vs must be kept between -6 and +600, relative to Vdd. They don't say what happens if you exceet the minus limit, but now YOU know what the result is. This appears to be a TYPO, Vs is shown as 6-Vdd, I think it should be 6-COM.Jon

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 16, 2022, 07:56:25 pm
content: There's a couple designs for those out there.Some, the COM or VS can't be below VSS, i.e. they're common-substrate and that would forward bias the diode isolating them. Usually I think these are just special-case or integrated things, or for low voltages where the transient negative voltage can be small.Others (that usually say they have higher immunity), Vbs can't be below Vdd, or below somewhat above Vss -- something like that. This reflects the signal coupling circuit, which is something like a small high voltage MOSFET pair, driving differential pulses, and that's how the level shifter block actually works. Obviously the body diode of those coupling transistors, and the receiver circuitry, puts a hard limit on that, and it's with respect to supply rails of either side.Have also seen a few with a limit of like -30V, transiently at least, which I wonder if that involves a series resistor and clamp diode sort of arrangement. Key is that they say output state CANNOT change during such an excursion -- which makes sense, there's no signal voltage for the level shifter to work with at all.Inverter applications aren't usually switching at completely arbitrary timings anyway, so this isn't much of a problem, but do keep in mind these are stateful circuits -- the high side is triggered by pulses only -- generated from input edges, and remembers what it's doing the rest of the time.The same caution applies to a number of digital isolators, which are pulse coupled, not continuously modulated. I believe Silicon Labs' ones are such an example? The ADuM family, in contrast, transmits a keep-alive pulse, and if it goes missing, the output times out. So you can arrange for a fail-safe condition, or have a default known state when the input isn't powered up, etc.I have never, ever seen a gate driver for the reverse case, i.e., common positive supply, large negative voltage range. It's certainly not a common case, but it comes up from time to time, synchronous inverting buck-boost and Cuk for example. (I have done the latter with an inverting gate driver, DC restore circuit, and PMOS; but PMOS suck, so the performance wasn't great.)Or PMOS drivers of any sort in general, I might've seen a handful? A high side level shifter with "Vbs" below Vs (it wouldn't be a bootstrap anymore) would be handy for these cases, when they occasionally show up. But yeah, very rare. Bootstrapped NMOS are often usable in such a case, but it's a force fit and requires a lot of support circuitry (how do you make a buck converter bootstrap start up in the first place? How do you ensure it stays running once started?)Tim

author: leblanc
author_rank: Regular Contributor
timestamp: November 21, 2022, 04:34:22 pm
content: I tried a few things:Change bootstrap resistor to 1R0Change bootstrap diode to ultra fast reverse recovery (onsemi rep let me know that's very important)Increase bootstrap cap to 470nFChange gate resistors to 10R0 (100R was too slow)I didn't see any negative transient on VS (although I'm working with ano-tso-great scope). On the next iteration I'll see if I can squeeze in at least a placeholder for a parallel diode on the low side FET.Although I haven't destroyed any more gate drivers with this new configuration, I might add a TVS diode on the +15V rail too, just in case. I'll also improve the decoupling on the VDD if I can fit it in. I do have a 2.2uF MLCC not too far away, but I'll see about reducing impedance for higher frequencies with lower value capacitors (although now with the higher gate resistance maybe it's notasimportant).As for sharing the layout, that's probably more detailed than I'm allowed to share on a public forum. It's not theideallayout, but I followed best practices as much as I could, keeping traces nice and wide. This is on a MCPCB so it limits my options for routing!I'm glad I put in lots of placeholders to experiment with these gate drivers. I took them out of the circuit I attached here for simplicity, but I've got lots of options (for example, I put a resistor+diode path in parallel with the gate resistor so I can have faster turn-off than turn-on, etc.). I just wish I had used larger package for my bootstrap cap (I have an 0603, so I ended up stacking them); next spin I guess!