SiFive FE310-G002 - Page 1
Forum section: electronics / general

author: brucehoult
author_rank: Super Contributor
timestamp: June 02, 2019, 07:57:50 am
content: Now that the HiFive1 RevB has been out for a few weeks and the backorders caught up with I thought I'd mention a little about the -G002 MCU on it and the differences from the previous version. The MCU is, again, available as five pack of bare 6x6mm QFN 48 0.4mm pitch packages for $25 on the same CrowdSupply page.On the board itself, the main changes other than the MCU are the addition of an ESP32 WIFI/BT chip, replacing the FTDI/openocd with Segger J-Link (which can program/debug both the FE310 and the ESP32, and removing the 3.3V to 5V level converters on GPIOs significantly decreasing the latency at the cost of losing 5V compatibility. The J-Link provides a USB drive on the host (as well as USB serial) and the user can if they wish reflash the board simply by drag-and-drop (or command line copy operation) of an Intel hex file to the USB drive.On the FE310-G002 itself:Unchanged:- 32 bit RISC-V RV32IMAC instruction set- hardware multiply (max 4 cycle) and divide (max 32 cycle)- up to 320 MHz (PLL based off a 16 MHz crystal)- 1.61 DMIPS/MHz, 2.73 Coremark/MHz- 19 GPIO, 9 PWM- 1 QSPI, 1 SPI with 3 chip selects- JTAG- 8 kB OTP program/data ROM- 8 kB Mask ROM- 16 kB data SRAM- 16 kB iCache- still no ADCNew:- hardware I2C- 2 UART vs 1- User and Machine mode (prev only Machine mode)- low power sleep mode- improved debug, including 8 hardware breakpoints- icache can be dynamically reconfigured as up to 8 kB ITIM (at least 8 kB must remain as cache)- 8 regions of Physical Memory Protection, normally affecting User mode, but if you lock a region then protections also applies to Machine mode, plus it can not be reconfigured until after a full system reset.- hardware performance monitor: dedicated 64 bit counters for cycles and instructions, plus two configurable 40 bit counters for 11 classes of instructions, plus 12 microarchitectural events such as various pipeline interlocks (stalls), branch and jump target mispredicts, pipeline flushes, icache misses.- vectored interrupts with 7 priority levelsI don't have a final data sheet yet. The preliminary datasheet gives the following typical current draws:ACTIVE 16 MHz: 8mA from 3.3V, 8mA from 1.8VACTIVE 250 MHz: 16mA from 3.3V, 150mA from 1.8VI don't have current draw figures for WFI (Wait For Interrupt) or SLEEP states.

author: JPortici
author_rank: Super Contributor
timestamp: June 02, 2019, 04:32:31 pm
content: what's the reason behindQuote?

author: brucehoult
author_rank: Super Contributor
timestamp: June 02, 2019, 09:50:12 pm
content: Quote from: JPortici on June 02, 2019, 04:32:31 pmThe E31 core is marketed to many different customers. Those who are integrating it into their own SoC can put their code into mask ROM (assuming it fits) without affecting the layout and placement of the core.Buyers of a retail chip obviously can't choose what is in in the mask ROM. It contains a little bit of code and a device tree description.OTP is of course more flexible. In the retail chips the boot sequence goes from mask ROM to OTP and the (normally) on to external SPI flash. There are only a few bytes used in the OTP and the code is designed in a way that you can patch an existing NOP (actually FENCE) instruction into a jump to new code. The core can self-program the OTP.

author: legacy
author_rank: Super Contributor
timestamp: June 03, 2019, 10:04:41 am
content: I would put a tiny bootloader in the mask-rom for hobbists.

author: brucehoult
author_rank: Super Contributor
timestamp: June 03, 2019, 09:47:55 pm
content: Quote from: legacy on June 03, 2019, 10:04:41 amOn the HiFive1 boards there is a small "bootloader" in SPI flash at 0x2000000 that blinks a green LED, delays 500 mS, and if the user didn't press reset in that time then jumps to user code at 0x20400000 (RevA) or 0x20010000 (RevB). [0x20400000 always seems excessive to me, but anyway it's past the end of the 4 MB flash in the RevB!]Before getting to SPI, the initial power-on goes to a tiny bit of gate ROM (i.e. implemented in RTL) that reads the MSEL0 and MSEL1 pins on the chip and acts as follows:00: loops forever waiting for debugger01: jumps to 0x2000000 (memory mapped QSPI)10: jumps to 0x00020000 (OTP)11: jumps to 0x00010000 (Mask ROM)If a hobbyist has a bare chip on their own board without QSPI flash they can set MSEL to 00, use the J-Link to download code into the 16 KB of SRAM, and use that code to program something into the OTP.It would certainly be good to have something useful in the mask ROM. Maybe some part of libc. If you have a big flash memory then it really doesn't matter, but it could help people building embedded solutions from off-the-shelf SoCs.Do STM or NXP or others put something useful into ROM on their SoCs?

author: thm_w
author_rank: Super Contributor
timestamp: June 03, 2019, 10:11:41 pm
content: Link for the curious:https://www.crowdsupply.com/sifive/hifive1-rev-b

author: oPossum
author_rank: Super Contributor
timestamp: June 03, 2019, 10:28:58 pm
content: TI puts peripheral support libraries in some Tiva (TivaWare) and C2000 (SYS/BIOS) microcontrollers.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: June 03, 2019, 11:00:25 pm
content: Are there plans for an MCU with on-chip FLASH?

author: mariush
author_rank: Super Contributor
timestamp: June 03, 2019, 11:33:23 pm
content: I'd be interested if someone investigated using FRAM instead of Flash ... there's quad SPI versions available of FRAM chips and power consumption seems low (20-30mA at 1.8v and 108 Mhz quad spi) ...I realize it's more expensive at something like 8$ for 4mbps but maybe it would be worth for some to use in data logging or other things (use spare area to write stuff into)... not sure if it's more power efficient during writes compared to flashIt's also not clear if there's a built in oscillator (i would think 16 mhz) and if there's an additional 32khz or some other such tiny for sleep/stand-by/low power etc .. is the minimum 16 mhz or can you get it down to something like 1 MhzWould probably be really useful to implement USB even if it's just 1.1 or 2.0 low speed... with some usb functions pre-written into the ROM (reusable for bootloader/flashing) it could be really useful.Wonder if adding some eeprom into the chip would be difficult... even if it's just 64-256 bytes of it. Is the manufacturing process too small to allow for it, does it require boosting voltage to program eeprom, too complex?

author: brucehoult
author_rank: Super Contributor
timestamp: June 04, 2019, 06:25:33 am
content: Quote from: Sal Ammoniac on June 03, 2019, 11:00:25 pmEven if I knew, I couldn't tell you :-)However I can say SiFive is not in intending to be a MicroChip, NXP, or STMicroelectronics, but like ARM to license cores to companies like those for them to add the peripherals their customers want. For smaller customers we can also help with integration of IP, layout, physical design, and fabrication if they don't have those capabilities.Any chips SiFive makes are primarily just to showcase the cores themselves. And the same for boards.

author: JPortici
author_rank: Super Contributor
timestamp: June 04, 2019, 07:52:34 am
content: NXP has bootloader and the usb stack in ROM... Or at least, in the 11U68 You have zero informations on the usb peripheral, the datasheet only gives you the API.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: June 04, 2019, 10:06:39 pm
content: Quote from: brucehoult on June 04, 2019, 06:25:33 amI thought one of the big advantages of RISC-V over Cortex-M was no license or royalty fees? Is SiFive going to license cores to chip vendors and charge royalties just like ARM does? Why would a big vendor like an NXP or an STMicroelectronics license a core from SiFive when they can implement their own RISC-V core based on the open standard?

author: Monkeh
author_rank: Super Contributor
timestamp: June 04, 2019, 10:10:08 pm
content: Quote from: Sal Ammoniac on June 04, 2019, 10:06:39 pmThere may be no royalty for the specification, but if you want a proven implementation to use, well, someone has to get paid. The specifications are, of course, provided under a license - but it's a rather open one, Creative Commons Attribution 4.0 International, at least for the user level spec (I assume everything is equally licensed).Quote from: Sal Ammoniac on June 04, 2019, 10:06:39 pmWhy would a big vendor like the above license the core implementation from ARM rather than develop their own (based on the spec they can license in order to do so)? Because they don't have to do all the work and can seek help when it goes wrong (when. not if.).

author: brucehoult
author_rank: Super Contributor
timestamp: June 04, 2019, 10:29:08 pm
content: Quote from: Sal Ammoniac on June 04, 2019, 10:06:39 pmSiFive is a for-profit company. It makes money by licensing standard or customised cores to other companies, and also by integrating cores with other IP (some developed in-house, some itself licensed) to design and fab complete SoCs.There are no royalties, permissions, or license fees to develop your own RISC-V core. Anyone may do it.This is unlike x86 where only Intel, AMD and I think VIA can develop cores. Or in the ARM world, companies such as Apple, Samsung, Qualcomm pay many millions of dollars to ARM to be permitted to develop their own 100% compatible cores (NOTHING added, NOTHING removed).Once you've developed a core, you are free to use it yourself, give it away, or charge license fees for it.Not everyone wants to develop their own core, which after all takes a lot of time, effort, and expertise. Those people can take a free one from github, or they can license a commercially supported one.SiFive is just one of the companies commercially licensing RISC-V cores, though one of the biggest right now.Andes has a similar number of customers, or maybe more. They had their own proprietary instruction set C-SKY (that is even supported the Linux kernel), and their own cores, but they decided to switch their cores to using the RISC-V instruction set.A number of companies, including NXP, are also using cores from the PULP project at ETH Zurich.Western Digital may well at some point commercially license some of their in-house developed cores. At the moment they have SweRV which they are giving away free. (And they also license cores from SiFive)

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 06, 2019, 05:00:46 pm
content: 16KB RAM is a bit on the low side. Was this choice constrained by the die size or other considerations?

author: brucehoult
author_rank: Super Contributor
timestamp: June 06, 2019, 08:36:15 pm
content: Quote from: SiliconWizard on June 06, 2019, 05:00:46 pmI just did a search on digikey for STM Cortex-M3's. The first 8 pages out of 28 were filled with chips with 16 kB or less of RAM, and many with 4 kB. The next few pages are 20 or 24 kB.Seems like a lot of people find 16 kB pretty useful.If you want more, you can go tohttps://www.sifive.com/core-designerand configure an E2 core with anything from 0.5 - 512 kB of ITIM and 0.5 - 512 kB of DTIM. Or configure an E3 core with 4 - 32 kB of icache and 8 - 128 kB of DTIM.64 kB is currently the default size for E3 cores. Don't forget the FE310 was the first commercially-available RISC-V silicon, and SiFive's first tape-out, more than 2.5 years ago.If you want a chip "Just like the FE310-G002 but with 64 kB SRAM" contact sales, and I think they'd be able to accommodate you surprisingly easily, especially if you want at least a few thousand of them.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 07, 2019, 04:43:34 pm
content: Well, many things can certainly be done with 16KB RAM! And yes many MCUs still have this amount of RAM or less, but more often with low-cost/low-power as a target. So I just found at first sight that a 320MHz CPU with just 16KB RAM was kind of a rare beast market-wise, not that it was useless.I realize the whole business model of SiFive is selling custom parts more than off-the-shelf MCUs, so that also makes sense from this POV, as the FE310-G002, for instance, is probably more to be seen as an evaluation platform than an all-purpose MCU (although, again, I admit it can still find many applications). I was just thinking about market considerations.

author: JPortici
author_rank: Super Contributor
timestamp: June 07, 2019, 08:34:12 pm
content: IME i need a lot of ram only when i have to reconstruct tables or filter signals, and in that case 4k is usually PLENTY.Then there's a bunch of peripherals that will consume A LOT of memory like canbus if the FIFOs are stored in GP ram instead of a dedicated peripheral memory, or other chips like those stupid Sillab radios that need a 800byte long firmware patch + configuration structure to be applied at every startup (Which can reside in flash, but not always)

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: June 11, 2020, 02:42:42 am
content: QFN48 is rather hobbyist unfriendly. Why not a QFP package in addition to the QFN?

author: asmi
author_rank: Super Contributor
timestamp: June 11, 2020, 03:21:44 am
content: Quote from: brucehoult on June 03, 2019, 09:47:55 pmYou might want to skim over this:https://www.st.com/resource/en/application_note/cd00167594-stm32-microcontroller-system-memory-boot-mode-stmicroelectronics.pdfas well as specific bootloader protocol specifications (for example this one for USART:https://www.st.com/resource/en/application_note/cd00264342-usart-protocol-used-in-the-stm32-bootloader-stmicroelectronics.pdfor this one for USB DFU:https://www.st.com/resource/en/application_note/cd00264379-usb-dfu-protocol-used-in-the-stm32-bootloader-stmicroelectronics.pdf).

author: mikerj
author_rank: Super Contributor
timestamp: June 11, 2020, 07:06:28 am
content: Quote from: brucehoult on June 06, 2019, 08:36:15 pmLots of people find 16k very useful when it is used purely for data rather than having to store the program as well. I suspect most everything you found with 16k SRAM also had a sizeable amount of flash memory. 8k of OTP isn't useful for development.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: June 11, 2020, 04:10:52 pm
content: Quote from: mikerj on June 11, 2020, 07:06:28 amI'd like to see an FE310 part with 64K of SRAM and 128K (or more) of onboard FLASH in a QFP package. That would be a really useful part. Support for RV32F or RV32D would also be nice.

author: brucehoult
author_rank: Super Contributor
timestamp: June 11, 2020, 05:18:16 pm
content: Quote from: Sal Ammoniac on June 11, 2020, 04:10:52 pmThe FE310-G003 used on the "SiFive Learn Inventor" has 64K of SRAM.If you want some custom chips, on the SiFive Core Designer sitehttps://scs.sifive.com/core-designer/there is a standard E34 core with single precision FPU. You can customize it to have double precision and you can increase SRAM to up to 256K (64K is standard for both E31 and E34).180nm chips don't cost all that much to make masks for, so a production run of a custom FE310 SoC would I think be well within what you might be able to do with a KickStarter project.Flash is fundamentally hard to put on a high MHz small geometry process node. I believe things such as ATMega are on 350 nm.As has been discussed on another thread, the GigaDevice GD32F103 ARM and GD32F103V RISC-V packages that appear to have high performance onboard flash actually have it on a separate die in the same package, and copy it to SRAM on reset.

author: asmi
author_rank: Super Contributor
timestamp: June 11, 2020, 05:28:47 pm
content: Quote from: brucehoult on June 11, 2020, 05:18:16 pmWhat is "not all that much" in real $$? Is it 1k? 10K? 100K? 1M?

author: brucehoult
author_rank: Super Contributor
timestamp: June 12, 2020, 02:21:50 am
content: Quote from: asmi on June 11, 2020, 05:28:47 pmIt's really hard to know. I wasn't in sales. This document ...https://nmi.org.uk/wp-content/uploads/2016/11/01-Easy-Access-ASIC-imec-IC-link-v1.2.pdf... says $134.4k for NRE for a mask with only your chip on (as many tiled copies as will fit), including the first 12 wafers with around 3000 FE310-sized chips per 200mm wafer (so 36000 or so chips). Additional wafers (which could be months or years later as they keep the masks on file) for $1000 each. If you made a million chips the overall cost might be under $0.50 per die.That document appears to be from 2016, so it might be a bit cheaper by now.I really don't know what SiFive's charge would be for their NRE and licensing. I think probably in the $100k to $200k range for a fairly standard chip not that different from the existing FE310 that comes out of the core designer and chip designer tools with some parameters tweaked. But I was never in sales. If interested, you should ask for a quote. I believe there are licensing deals (with the customer handling the FAB relationship) in that price range.As I said, I think this is well within the range of a kickstarter project. If you did the minimum order the cost might be around $8 a chip for that first 36000 or so, but as you went higher the marginal cost might be around $0.35. Both plus packaging&testing, which I think might bring it up to around $1 a chip marginal cost.But this is all guesswork. The way to find out would be to get a quote.

author: asmi
author_rank: Super Contributor
timestamp: June 12, 2020, 03:38:15 am
content: Quote from: brucehoult on June 12, 2020, 02:21:50 amI guess we have very different ideas of what constitutes "not all that much".I personally don't find FE310 all that useful or exciting. I would rather have something more high-end with DDR3/4 memory controller and PCI Express ports, so something more fitting to build a desktop-class system without usual crap ton of useless peripherals which litter pretty much all modern SoCs. Given what you said above, that will probably be an order of magnitude more $$$.

author: brucehoult
author_rank: Super Contributor
timestamp: June 12, 2020, 06:03:56 am
content: Quote from: asmi on June 12, 2020, 03:38:15 amDDR? PCI? You clearly don't want a microcontroller, which is what we've been discussing here. You also won't want something running at 100 MHz to 300 MHz, which is what the old and cheap 180 nm process is usually capable of.Until now there aren't a lot of custom application processors with external DDR and PCI made. Everything is off the shelf in standard configurations because they cost something between hundreds of millions and billions of dollars to design, and the smaller process nodes necessary to fit enough transistors on them in a reasonable area and get clock speeds over 1 GHz cost millions or tens of millions just to make a set of masks. You can't justify that unless you're going to make many many millions of the same thing and use them for many different things, which tends to mean they need to be general purpose not custom.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: June 14, 2020, 12:54:24 am
content: Quote from: brucehoult on June 11, 2020, 05:18:16 pmCan I buy the FE310-G003 ICs anywhere? CrowdSupply has the -002, but I don’t see the -003 parts listed.

author: brucehoult
author_rank: Super Contributor
timestamp: June 14, 2020, 02:39:20 am
content: Quote from: Sal Ammoniac on June 14, 2020, 12:54:24 amIf you watch this video very carefully ...... some things are revealed which have not been formally announced. Interestingly SiFive retweeted the @hacksterio tweet with this video.You might imagine that the board and chip are intended for high volume production but the initial production of the chip is spoken for. I'd expect to see it in Mouser or Digikey later.Who knows what has happened after COVID-19.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: June 15, 2020, 05:04:08 pm
content: Interesting (but also annoying) video. I only found one source for that board, but it seems they're perpetually out of stock.It's probably a good thing I'm working at home due to Covid-19. If I brought one of those boards to the office, I'd get no end of ribbing from the guys over its silly shape.

author: brucehoult
author_rank: Super Contributor
timestamp: June 16, 2020, 12:16:52 am
content: Yeah pimoroni. I'm afraid I can't offer any further insight into what is going on. Not what was planned, it seems.

author: asmi
author_rank: Super Contributor
timestamp: June 16, 2020, 01:38:35 pm
content: Quote from: Sal Ammoniac on June 15, 2020, 05:04:08 pmYea whoever designed this was smoking some serious stuff.

author: andersm
author_rank: Super Contributor
timestamp: June 16, 2020, 02:23:56 pm
content: The bottom connector is the same as the BBC micro:bit, which should give you an idea of the target audience.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: June 16, 2020, 04:10:47 pm
content: Quote from: andersm on June 16, 2020, 02:23:56 pmInteresting. I didn't know the BBC was involved. This is kind of ironic, in a way, since the original BBC Micro from back in the early 1980s was developed by Acorn Computers, who, of course, originated the ARM architecture (ARM = Acorn RISC Machine).

author: andersm
author_rank: Super Contributor
timestamp: June 16, 2020, 08:14:03 pm
content: I haven't heard anything about the BBC having anything to do with the SiFive board, but the micro:bit was aimed at schoolchildren, so it's a little less weird that they went with a "fun" design.

author: brucehoult
author_rank: Super Contributor
timestamp: June 17, 2020, 02:30:30 am
content: Quote from: andersm on June 16, 2020, 08:14:03 pmExactly. And watch the video.