1Gb Ethernet core - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 19, 2021, 09:01:49 pm
content: Hi,Till now, I have done my Ethernet Projects using w5300 and a simple state machine in HDL to control it and I have used TCP/IP mode and C# or Qt for the PC side to communicate with my boards.Now I need to switch to 1Gb Ethernet, and since I should route the PCB myself too, I want something easier to route, so RGMII interface is the easiest PHY interface I think, I want to know if we have any opensource cores out there, supporting UPD or TCP, also what PHY chip does it support?Any Hints on your last experiences would highly help me to achieve the goal easier.which Open source 1Gb Ethernet core do you suggest?Thanks

author: Morgan127
author_rank: Contributor
timestamp: August 20, 2021, 04:49:50 am
content: FPGA-Cores.com has support for gigabit Ethernet, UDP and TCP.It is not open source however it is free to download and use for non commercial use.I did a board with KSZ9031RNX and it works great.You can find the cores here:https://www.fpga-cores.com/cores/

author: dolbeau
author_rank: Regular Contributor
timestamp: August 20, 2021, 06:33:59 am
content: LiteEth (from Litex)has support for GbE including GMII and RGMII (but not yet SGMII, I think).For external *GMII transceivers you can look at theLitex-supported boards, they will tell you what is 'known to work' (e.g. my board has a RTL8211EG).

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 20, 2021, 08:07:22 am
content: Thanks for the linksMorgan127 how can I download and evaluate the cores? I do not see any download button.http://www.fpga-cores.com/cores/fc1004_rgmii/

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 20, 2021, 08:18:06 am
content: dolbeau The core is in Python? what would be the generated core language? Can it be used on a custom designed hardware? Do you know any quick and useful tutorial or youtube video. thanks for sharing.

author: Morgan127
author_rank: Contributor
timestamp: August 20, 2021, 09:18:03 am
content: Quote from: ali_asadzadeh on August 20, 2021, 08:07:22 amYes all links are gone. I have sent them a feedback message.

author: Morgan127
author_rank: Contributor
timestamp: August 20, 2021, 09:40:59 am
content: Quote from: ali_asadzadeh on August 20, 2021, 08:07:22 amNow it should be solved.

author: dolbeau
author_rank: Regular Contributor
timestamp: August 20, 2021, 11:00:09 am
content: Quote from: ali_asadzadeh on August 20, 2021, 08:18:06 amThe language isMigen, which is basically Python yes.The infrastructure then generate Verilog and uses the 'platform' tools (either the vendors', such as Vivado for Xilinx, or for some FPGAs you can use a FOSS toolchain).The primary repo would behttps://github.com/enjoy-digital/litex/. It is originally designed to create full SoC, but you can use it to create partial SoC and sometimes just the specific IP in Verilog, for instance for LiteEth there's a generator exampleliteeth/gen.py.For help, there's an IRC channel #litex on libera.chat .

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 20, 2021, 12:34:55 pm
content: QuoteThanks, Now I can download the files, is there any documentation or tutorial on how to use this core in TCP mode or UDP mode?Also I'm interested in using DP83867 PHY from TI, how can I make sure this core support this PHY?

author: Morgan127
author_rank: Contributor
timestamp: August 20, 2021, 02:01:33 pm
content: Quote from: ali_asadzadeh on August 20, 2021, 12:34:55 pmThere are a couple of tutorials here:https://www.fpga-cores.com/tutorials/It is really simple. You only need to set the TCP or UDP port and connect to that from any PC.The interface is a standard AXI-Stream and you can google that and find a lot of examples.It works basically like this: If "ready" and "valid" both are '1' the transfer is done. The UDP packet is send when "last" is '1' at same time as "valid".If DP83867 support standard RGMII I guess that device will work fine.

author: asmi
author_rank: Super Contributor
timestamp: August 20, 2021, 06:12:17 pm
content: Quote from: ali_asadzadeh on August 20, 2021, 12:34:55 pmMAC layer is generally PHY-agnostic as long as it supports the right protocol (GMII, RGMII, SGMII). There are differences in initialization protocol for different PHY chips, but they are commonly handled at the software level within PHY-specific driver.As far as the PHY protocols go, SGMII is by far the simplest to route, but there are some gotchas - like with Artix/Spartan-7 when you have to have Vccio of 2.5 V in order to use LVDS, or 1.8 V if you want to mess with ac-coupled DIFF_HSTL, not to mention that routing 1.25 Gbps differential pairs requires some experience with high-speed layouts. With that, I only recommend going for this standard for experienced designers. That said, Xilinx provides a free SGMII-to-GMII IP core, so you can connect any GMII core to SGMII PHY via that core.Now, RGMII has it's own share of idiosyncrasies. For example, some RGMII PHY chips have internal clock delay (they sometimes are called "RGMII v2.0"), others require this delay implemented externally - either on a PCB with clock line being artificially longer than data lines, or inside MAC. So the easiest option is full-on GMII, but it's got quite a number of traces which need to be length-matched.As for the MAC itself - why not roll out your own? It's not very complex (IO being probably the hardest part), and it's fun project which can be as simple or as complex as you want - from AXI-steram-to-R/S/GMII using AXI DMA IP on the simple end, all the way to built-in SG DMA master with HW CRC offload and timestamping support on the complex end.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 20, 2021, 07:58:03 pm
content: Thanks Morgan127 and asmi for the tips,QuoteMy final goal is to roll out my own code, But some projects have limited dead times, also for comparing my own code, which can take a few months, these open source projects would help a lot. Also I have read the DP83867 data sheet today, the clock delays can be tuned in the PHY from 0.25ns to 4ns! so I think either I should role out my own core, or use a true open source core to control the PHY extended regs,As for SGMII I agree that it would be simpler for PCB design But it needs MGTs and I just wanted to play with them, also using it would limit the core to only FPGA's with internal MGT's, so I think I should have both cores in my arsenal.Did you role your own core or are you using an open source core? what about implementing UDP and TCP, I think they would take quite a big time, do you suggest any direction regarding how to impalement them too?

author: asmi
author_rank: Super Contributor
timestamp: August 20, 2021, 08:34:21 pm
content: Quote from: ali_asadzadeh on August 20, 2021, 07:58:03 pmYou don't need MGTs for SGMII as LVDS SERDES in Artix-7/Spartan-7 speed grade 2 is fast enough for that - it's rated for 1250 Mbps (and SGMII requires just that - what a coincidence!).Quote from: ali_asadzadeh on August 20, 2021, 07:58:03 pmI did both, but for commercial projects I always recommended my customers to stick to commercial cores - this way they get to receive tech support from IP vendor, and per-project license for Xilinx TEMAC is very affordable at $650:https://www.mouser.com/ProductDetail/Xilinx/EF-DI-TEMAC-PROJ?qs=rrS6PyfT74djTUXjNtaK3g%3D%3DThat license allows you to have any number of these cores in a project, so you can implement multiple Ethernet interfaces.For TCP/IP stack you can use lwip for baremetal/RTOS applications, or Linux IP stack for Linux-based ones. Implementing your own IP stack is not easy and requires deep knowledge of this area, so it's definitely not worth it unless that is your area of expertise/interest.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 20, 2021, 09:22:11 pm
content: asmi Thanks for the hints,Have you seen this one on open coreshttps://opencores.org/projects/ethernet_tri_modeAny Idea about that?Morgan127 would you please share the FPGA resources that this core took?

author: asmi
author_rank: Super Contributor
timestamp: August 20, 2021, 09:42:39 pm
content: Quote from: ali_asadzadeh on August 20, 2021, 09:22:11 pmNo idea. Like I said - if you need it for commercial project - just buy a project license for Xilinx TRIMAC as it's known to work, it's easy to integrate, and it's got drivers. You can request a free trial version to build a time-limited bitstream in order to confirm that it works with your project. US$650 is nothing for R&D - 1-2 days worth of HDL designer's work. You will likely spend more time figuring out how to integrate that OS core.If you want this for a hobby project - then design your own. It's a fun project, and once you figure out 1G Ethernet, you will be much better positioned to try 10G (or 2.5/5G), than if you use somebody else's code.

author: hamster_nz
author_rank: Super Contributor
timestamp: August 20, 2021, 11:53:30 pm
content: I have got a VHDL core that spits data from a FIFO UDP down a given port at 1Gb/s on a Digilent dev board.Can't remember which one off the top of my head, might be Nexys Video. Can take a look and post links if interested.

author: Morgan127
author_rank: Contributor
timestamp: August 21, 2021, 06:29:52 am
content: Quote from: ali_asadzadeh on August 20, 2021, 09:22:11 pmIf I use theFC_1004_RGMIIcore and make a simple code around that.The code used the following parts in the core TCP, UDP, flash programmer and the logic analyzer the total resources reported in Vivado are:LUT 2839LUTRAM 12FF 2828BRAM 12.5I guess a major part of that is TCP.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 21, 2021, 07:50:16 am
content: QuoteI'm all earsQuoteThanks Morgan127.QuoteI agree with you, and I think I need a softcore and lwip, also those resources form Morgan127 core, Might say that it has done it in a soft CPU too, becuase of the BRAM usage.

author: laugensalm
author_rank: Regular Contributor
timestamp: August 23, 2021, 07:07:34 am
content: I've used this one and found it very portable among different architectures (with both RGMII and GMII setups):https://github.com/yol/ethernet_macIt's VHDL and required only minor modifications in order to work with Autobuffer DMA in conjunction with a CPU. For that however, I'm using a handcoded UDP stack to get maximum performance (to transmit video). With the low performance lwip architecture, a 1Gb MAC is somewhat void.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 23, 2021, 08:13:45 am
content: thanks laugensalm for sharing, would you please tell the recourse utilization of this core? is the UDP stack open source too?

author: laugensalm
author_rank: Regular Contributor
timestamp: August 23, 2021, 10:31:32 am
content: The resource usage should be along those lines in the PNG below.Fits nicely as a network SoC onto a Spartan 6 LX-9 (see alsohttps://hackaday.io/project/162259-netpp-node).The UDP stack isn't opensource, as it's tightly coupled to the associated `DMAA` core doing the continuous DMA for internal data streams or packet buffer queues where minimal CPU interaction is desired. For simple ping-pong communication, packet buffers as per lwip architecture will do.

author: hamster_nz
author_rank: Super Contributor
timestamp: August 25, 2021, 09:12:36 pm
content: The TCP/IP code never really got started (due to resends, slow starts and so on), but the UDP & ARP is tested and good to go.https://github.com/hamsternz/FPGA_Webserver

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 26, 2021, 05:33:10 am
content: Hi, hamster_nzThanks for sharing.

author: radiolistener
author_rank: Super Contributor
timestamp: August 26, 2021, 08:12:53 pm
content: Here is nice core for 10M / 100M / 1G / 10G / 25G ethernet PHY. It also include UDP stack and ARP.https://github.com/alexforencich/verilog-ethernetworks very good.Also it has automatic flow speed detection, so you're don't need to implement read it from PHY control registers through MDIO. It just automatically switch the speed and you can use it with no need to access control registers. It allows fine tuning protocol details and use different interfaces. I connected it to GMII PHY RTL8211EG with no issue.Other Ethernet cores that I found support just one fixed and hardcoded speed, because it's a little complicated to implement automatic speed switching. It needs to properly select CLK and other stuff.This core works for both - Xilinx and Altera/Intel FPGA just out of the box.It also include ready to use examples for known FPGA dev boards.I used these examples to remap it forQMTECH Cyclone 4 EP4CE15 starter kit

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 26, 2021, 08:32:30 pm
content: Thanks radiolistener for sharing, It has many modules, which one did you use? also what's the resource utilization for the job?

author: radiolistener
author_rank: Super Contributor
timestamp: August 27, 2021, 02:13:07 am
content: Quote from: ali_asadzadeh on August 26, 2021, 08:32:30 pmTEST.v is my main module.I just a little modified main module from examples to fit with my QMTECH starter kit board.It shows the first payload byte from UDP packet on 7-LED display and re-transmit packet back to the sender.led7_hex.v is my module for onboard 7 segment LED.This stack supports 1G/100M ARP and UDP stack and include FIFO buffering for packets.QuoteQuote from: ali_asadzadeh on August 26, 2021, 08:32:30 pmQuoteIt eat a lot of elements, but in comparison with other ethernet implementations it supports both 100M/1G with automatic speed switching and works very stable. I was impressed after fighting with another implementations. This is the only one implementation which I found that can work with at both speed 100M and 1G just out of the box with no need to modify something

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 27, 2021, 08:22:04 am
content: Thanks radiolistener for the update.

author: radiolistener
author_rank: Super Contributor
timestamp: August 27, 2021, 08:46:08 am
content: the main ethernet module is fpga_core, it connects all modules together, you can find examples for different starter kit boards in example folderI just added fpga_core from examples, fixed it and then copy all required modules to my projectHere is main entry TEST.v:Code:module TEST(input clk50mhz,input key0,output led0,output [2:0] led_dig,output [7:0] led_seg,input [3:0] j101, // J10 1-6output [3:0] j102, // J10 7-12// CP2102-GMinput wire uart_rxd,output wire uart_txd,// PHY RTL8211EGoutput phy_reset_n, // Hardware Reset. Active low.input phy_rxclk, // RX GMII reference clock 125MHz, 25MHz, or 2.5MHz. It is derived from the received data stream.input phy_txclk, // TX MII reference clock 25MHz, or 2.5MHz depending on speed.output phy_gtxclk, // TX GMII reference clock 125 MHz(* useioff = 1 *) output [7:0] phy_txd, // Transmit Data(* useioff = 1 *) output phy_txen, // Transmit Enable(* useioff = 1 *) output phy_txer, // Transmit Error (Connect to GND if MAC does not have a TXER pin)(* useioff = 1 *) input [7:0] phy_rxd, // Receive Data(* useioff = 1 *) input phy_rxdv, // Receive Data Valid(* useioff = 1 *) input phy_rxer, // Receive Erroroutput phy_mdc,inout phy_mdio,input phy_col, // Collision In Half Duplex Modeinput phy_crs // Carrier Sense);assign led0 = !phy_crs;led7_hex #(.RATE(12500)) led7_hex(.clk(clk_int),.enable(key0),.data({speed[1:0], payload[7:0]}),.dots({badframe, overflow_tx, overflow_rx}),.led_dig(led_dig),.led_seg(led_seg));reg overflow_rx;reg overflow_tx;reg badframe;reg [7:0] payload;reg [1:0] speed;// Clock and reset// Internal 125 MHz clockwire clk_int;wire rst_int;wire pll_rst = 0;//~KEY;wire pll_locked;wire clk90_int;altpll #(.bandwidth_type("AUTO"),.clk0_divide_by(2),.clk0_duty_cycle(50),.clk0_multiply_by(5),.clk0_phase_shift("0"),.clk1_divide_by(2),.clk1_duty_cycle(50),.clk1_multiply_by(5),.clk1_phase_shift("2000"),.compensate_clock("CLK0"),.inclk0_input_frequency(20000),.intended_device_family("Cyclone IV E"),.operation_mode("NORMAL"),.pll_type("AUTO"),.port_activeclock("PORT_UNUSED"),.port_areset("PORT_USED"),.port_clkbad0("PORT_UNUSED"),.port_clkbad1("PORT_UNUSED"),.port_clkloss("PORT_UNUSED"),.port_clkswitch("PORT_UNUSED"),.port_configupdate("PORT_UNUSED"),.port_fbin("PORT_UNUSED"),.port_inclk0("PORT_USED"),.port_inclk1("PORT_UNUSED"),.port_locked("PORT_USED"),.port_pfdena("PORT_UNUSED"),.port_phasecounterselect("PORT_UNUSED"),.port_phasedone("PORT_UNUSED"),.port_phasestep("PORT_UNUSED"),.port_phaseupdown("PORT_UNUSED"),.port_pllena("PORT_UNUSED"),.port_scanaclr("PORT_UNUSED"),.port_scanclk("PORT_UNUSED"),.port_scanclkena("PORT_UNUSED"),.port_scandata("PORT_UNUSED"),.port_scandataout("PORT_UNUSED"),.port_scandone("PORT_UNUSED"),.port_scanread("PORT_UNUSED"),.port_scanwrite("PORT_UNUSED"),.port_clk0("PORT_USED"),.port_clk1("PORT_USED"),.port_clk2("PORT_UNUSED"),.port_clk3("PORT_UNUSED"),.port_clk4("PORT_UNUSED"),.port_clk5("PORT_UNUSED"),.port_clkena0("PORT_UNUSED"),.port_clkena1("PORT_UNUSED"),.port_clkena2("PORT_UNUSED"),.port_clkena3("PORT_UNUSED"),.port_clkena4("PORT_UNUSED"),.port_clkena5("PORT_UNUSED"),.port_extclk0("PORT_UNUSED"),.port_extclk1("PORT_UNUSED"),.port_extclk2("PORT_UNUSED"),.port_extclk3("PORT_UNUSED"),.self_reset_on_loss_lock("ON"),.width_clock(5))altpll_component (.areset(pll_rst),.inclk({1'b0, clk50mhz}),.clk({clk90_int, clk_int}),.locked(pll_locked),.activeclock(),.clkbad(),.clkena({6{1'b1}}),.clkloss(),.clkswitch(1'b0),.configupdate(1'b0),.enable0(),.enable1(),.extclk(),.extclkena({4{1'b1}}),.fbin(1'b1),.fbmimicbidir(),.fbout(),.fref(),.icdrclk(),.pfdena(1'b1),.phasecounterselect({4{1'b1}}),.phasedone(),.phasestep(1'b1),.phaseupdown(1'b1),.pllena(1'b1),.scanaclr(1'b0),.scanclk(1'b0),.scanclkena(1'b1),.scandata(1'b0),.scandataout(),.scandone(),.scanread(1'b0),.scanwrite(1'b0),.sclkout0(),.sclkout1(),.vcooverrange(),.vcounderrange());sync_reset #(.N(4)) sync_reset_inst (.clk(clk_int),.rst(~pll_locked),.out(rst_int));// GPIOwire key0_int;wire [3:0] j101_int;wire uart_rxd_int;debounce_switch #(.WIDTH(13), .N(4), .RATE(125000)) debounce_switch_inst (.clk(clk_int),.rst(rst_int),.in({key0, j101}),.out({key0_int, j101_int}));sync_signal #(.WIDTH(1), .N(2)) sync_signal_inst (.clk(clk_int),.in({uart_rxd}),.out({uart_rxd_int}));fpga_core core_inst (// Clock: 125MHz// Synchronous reset.clk(clk_int),.rst(rst_int),// GPIO//.key0(key0_int),.overflow_rx(overflow_rx),.overflow_tx(overflow_tx),.badframe(badframe),.payload(payload),.speed(speed),// Ethernet: 1000BASE-T GMII.phy_rx_clk(phy_rxclk),.phy_rxd(phy_rxd),.phy_rx_dv(phy_rxdv),.phy_rx_er(phy_rxer),.phy_gtx_clk(phy_gtxclk),.phy_tx_clk(phy_txclk),.phy_txd(phy_txd),.phy_tx_en(phy_txen),.phy_tx_er(phy_txer),.phy_reset_n(phy_reset_n));endmoduleand my fpga_core:Code:/** FPGA core logic*/module fpga_core #(parameter TARGET = "ALTERA")(/** Clock: 125MHz* Synchronous reset*/input wire clk,input wire rst,/** GPIO*/output wire overflow_rx,output wire overflow_tx,output wire badframe,output wire [7:0] payload,output wire [1:0] speed,/** Ethernet: 1000BASE-T GMII*/input wire phy_rx_clk,input wire [7:0] phy_rxd,input wire phy_rx_dv,input wire phy_rx_er,output wire phy_gtx_clk,input wire phy_tx_clk,output wire [7:0] phy_txd,output wire phy_tx_en,output wire phy_tx_er,output wire phy_reset_n);// AXI between MAC and Ethernet moduleswire [7:0] rx_axis_tdata;wire rx_axis_tvalid;wire rx_axis_tready;wire rx_axis_tlast;wire rx_axis_tuser;wire [7:0] tx_axis_tdata;wire tx_axis_tvalid;wire tx_axis_tready;wire tx_axis_tlast;wire tx_axis_tuser;// Ethernet frame between Ethernet modules and UDP stackwire rx_eth_hdr_ready;wire rx_eth_hdr_valid;wire [47:0] rx_eth_dest_mac;wire [47:0] rx_eth_src_mac;wire [15:0] rx_eth_type;wire [7:0] rx_eth_payload_axis_tdata;wire rx_eth_payload_axis_tvalid;wire rx_eth_payload_axis_tready;wire rx_eth_payload_axis_tlast;wire rx_eth_payload_axis_tuser;wire tx_eth_hdr_ready;wire tx_eth_hdr_valid;wire [47:0] tx_eth_dest_mac;wire [47:0] tx_eth_src_mac;wire [15:0] tx_eth_type;wire [7:0] tx_eth_payload_axis_tdata;wire tx_eth_payload_axis_tvalid;wire tx_eth_payload_axis_tready;wire tx_eth_payload_axis_tlast;wire tx_eth_payload_axis_tuser;// IP frame connectionswire rx_ip_hdr_valid;wire rx_ip_hdr_ready;wire [47:0] rx_ip_eth_dest_mac;wire [47:0] rx_ip_eth_src_mac;wire [15:0] rx_ip_eth_type;wire [3:0] rx_ip_version;wire [3:0] rx_ip_ihl;wire [5:0] rx_ip_dscp;wire [1:0] rx_ip_ecn;wire [15:0] rx_ip_length;wire [15:0] rx_ip_identification;wire [2:0] rx_ip_flags;wire [12:0] rx_ip_fragment_offset;wire [7:0] rx_ip_ttl;wire [7:0] rx_ip_protocol;wire [15:0] rx_ip_header_checksum;wire [31:0] rx_ip_source_ip;wire [31:0] rx_ip_dest_ip;wire [7:0] rx_ip_payload_axis_tdata;wire rx_ip_payload_axis_tvalid;wire rx_ip_payload_axis_tready;wire rx_ip_payload_axis_tlast;wire rx_ip_payload_axis_tuser;wire tx_ip_hdr_valid;wire tx_ip_hdr_ready;wire [5:0] tx_ip_dscp;wire [1:0] tx_ip_ecn;wire [15:0] tx_ip_length;wire [7:0] tx_ip_ttl;wire [7:0] tx_ip_protocol;wire [31:0] tx_ip_source_ip;wire [31:0] tx_ip_dest_ip;wire [7:0] tx_ip_payload_axis_tdata;wire tx_ip_payload_axis_tvalid;wire tx_ip_payload_axis_tready;wire tx_ip_payload_axis_tlast;wire tx_ip_payload_axis_tuser;// UDP frame connectionswire rx_udp_hdr_valid;wire rx_udp_hdr_ready;wire [47:0] rx_udp_eth_dest_mac;wire [47:0] rx_udp_eth_src_mac;wire [15:0] rx_udp_eth_type;wire [3:0] rx_udp_ip_version;wire [3:0] rx_udp_ip_ihl;wire [5:0] rx_udp_ip_dscp;wire [1:0] rx_udp_ip_ecn;wire [15:0] rx_udp_ip_length;wire [15:0] rx_udp_ip_identification;wire [2:0] rx_udp_ip_flags;wire [12:0] rx_udp_ip_fragment_offset;wire [7:0] rx_udp_ip_ttl;wire [7:0] rx_udp_ip_protocol;wire [15:0] rx_udp_ip_header_checksum;wire [31:0] rx_udp_ip_source_ip;wire [31:0] rx_udp_ip_dest_ip;wire [15:0] rx_udp_source_port;wire [15:0] rx_udp_dest_port;wire [15:0] rx_udp_length;wire [15:0] rx_udp_checksum;wire [7:0] rx_udp_payload_axis_tdata;wire rx_udp_payload_axis_tvalid;wire rx_udp_payload_axis_tready;wire rx_udp_payload_axis_tlast;wire rx_udp_payload_axis_tuser;wire tx_udp_hdr_valid;wire tx_udp_hdr_ready;wire [5:0] tx_udp_ip_dscp;wire [1:0] tx_udp_ip_ecn;wire [7:0] tx_udp_ip_ttl;wire [31:0] tx_udp_ip_source_ip;wire [31:0] tx_udp_ip_dest_ip;wire [15:0] tx_udp_source_port;wire [15:0] tx_udp_dest_port;wire [15:0] tx_udp_length;wire [15:0] tx_udp_checksum;wire [7:0] tx_udp_payload_axis_tdata;wire tx_udp_payload_axis_tvalid;wire tx_udp_payload_axis_tready;wire tx_udp_payload_axis_tlast;wire tx_udp_payload_axis_tuser;wire [7:0] rx_fifo_udp_payload_axis_tdata;wire rx_fifo_udp_payload_axis_tvalid;wire rx_fifo_udp_payload_axis_tready;wire rx_fifo_udp_payload_axis_tlast;wire rx_fifo_udp_payload_axis_tuser;wire [7:0] tx_fifo_udp_payload_axis_tdata;wire tx_fifo_udp_payload_axis_tvalid;wire tx_fifo_udp_payload_axis_tready;wire tx_fifo_udp_payload_axis_tlast;wire tx_fifo_udp_payload_axis_tuser;// Configurationwire [47:0] local_mac = 48'h02_00_00_00_00_00;wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};// IP ports not usedassign rx_ip_hdr_ready = 1;assign rx_ip_payload_axis_tready = 1;assign tx_ip_hdr_valid = 0;assign tx_ip_dscp = 0;assign tx_ip_ecn = 0;assign tx_ip_length = 0;assign tx_ip_ttl = 0;assign tx_ip_protocol = 0;assign tx_ip_source_ip = 0;assign tx_ip_dest_ip = 0;assign tx_ip_payload_axis_tdata = 0;assign tx_ip_payload_axis_tvalid = 0;assign tx_ip_payload_axis_tlast = 0;assign tx_ip_payload_axis_tuser = 0;// Loop back UDPwire match_cond = rx_udp_dest_port == 1234;wire no_match = !match_cond;reg match_cond_reg = 0;reg no_match_reg = 0;always @(posedge clk) beginif (rst) beginmatch_cond_reg <= 0;no_match_reg <= 0;end else beginif (rx_udp_payload_axis_tvalid) beginif ((!match_cond_reg && !no_match_reg) ||(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) beginmatch_cond_reg <= match_cond;no_match_reg <= no_match;endend else beginmatch_cond_reg <= 0;no_match_reg <= 0;endendendassign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;assign tx_udp_ip_dscp = 0;assign tx_udp_ip_ecn = 0;assign tx_udp_ip_ttl = 64;assign tx_udp_ip_source_ip = local_ip;assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;assign tx_udp_source_port = rx_udp_dest_port;assign tx_udp_dest_port = rx_udp_source_port;assign tx_udp_length = rx_udp_length;assign tx_udp_checksum = 0;assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;// Place first payload byte onto LEDsreg valid_last = 0;reg [7:0] led_reg = 0;always @(posedge clk) beginif (rst) beginled_reg <= 0;end else beginif (tx_udp_payload_axis_tvalid) beginif (!valid_last) beginled_reg <= tx_udp_payload_axis_tdata;valid_last <= 1'b1;endif (tx_udp_payload_axis_tlast) beginvalid_last <= 1'b0;endendendend//assign led = sw;assign payload = led_reg;assign phy_reset_n = !rst;//assign uart_txd = 0;eth_mac_1g_gmii_fifo #(.TARGET(TARGET),.IODDR_STYLE("IODDR2"),.CLOCK_INPUT_STYLE("BUFIO2"),.ENABLE_PADDING(1),.MIN_FRAME_LENGTH(64),.TX_FIFO_DEPTH(4096),.TX_FRAME_FIFO(1),.RX_FIFO_DEPTH(4096),.RX_FRAME_FIFO(1))eth_mac_inst (.gtx_clk(clk),.gtx_rst(rst),.logic_clk(clk),.logic_rst(rst),.tx_axis_tdata(tx_axis_tdata),.tx_axis_tvalid(tx_axis_tvalid),.tx_axis_tready(tx_axis_tready),.tx_axis_tlast(tx_axis_tlast),.tx_axis_tuser(tx_axis_tuser),.rx_axis_tdata(rx_axis_tdata),.rx_axis_tvalid(rx_axis_tvalid),.rx_axis_tready(rx_axis_tready),.rx_axis_tlast(rx_axis_tlast),.rx_axis_tuser(rx_axis_tuser),.gmii_rx_clk(phy_rx_clk),.gmii_rxd(phy_rxd),.gmii_rx_dv(phy_rx_dv),.gmii_rx_er(phy_rx_er),.gmii_tx_clk(phy_gtx_clk),.mii_tx_clk(phy_tx_clk),.gmii_txd(phy_txd),.gmii_tx_en(phy_tx_en),.gmii_tx_er(phy_tx_er),.tx_fifo_overflow(overflow_tx),.tx_fifo_bad_frame(),.tx_fifo_good_frame(),.rx_error_bad_frame(),.rx_error_bad_fcs(),.rx_fifo_overflow(overflow_rx),.rx_fifo_bad_frame(badframe),.rx_fifo_good_frame(),.speed(speed),.ifg_delay(12));eth_axis_rx eth_axis_rx_inst (.clk(clk),.rst(rst),// AXI input.s_axis_tdata(rx_axis_tdata),.s_axis_tvalid(rx_axis_tvalid),.s_axis_tready(rx_axis_tready),.s_axis_tlast(rx_axis_tlast),.s_axis_tuser(rx_axis_tuser),// Ethernet frame output.m_eth_hdr_valid(rx_eth_hdr_valid),.m_eth_hdr_ready(rx_eth_hdr_ready),.m_eth_dest_mac(rx_eth_dest_mac),.m_eth_src_mac(rx_eth_src_mac),.m_eth_type(rx_eth_type),.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),// Status signals.busy(),.error_header_early_termination());eth_axis_tx eth_axis_tx_inst (.clk(clk),.rst(rst),// Ethernet frame input.s_eth_hdr_valid(tx_eth_hdr_valid),.s_eth_hdr_ready(tx_eth_hdr_ready),.s_eth_dest_mac(tx_eth_dest_mac),.s_eth_src_mac(tx_eth_src_mac),.s_eth_type(tx_eth_type),.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),// AXI output.m_axis_tdata(tx_axis_tdata),.m_axis_tvalid(tx_axis_tvalid),.m_axis_tready(tx_axis_tready),.m_axis_tlast(tx_axis_tlast),.m_axis_tuser(tx_axis_tuser),// Status signals.busy());udp_complete udp_complete_inst (.clk(clk),.rst(rst),// Ethernet frame input.s_eth_hdr_valid(rx_eth_hdr_valid),.s_eth_hdr_ready(rx_eth_hdr_ready),.s_eth_dest_mac(rx_eth_dest_mac),.s_eth_src_mac(rx_eth_src_mac),.s_eth_type(rx_eth_type),.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),// Ethernet frame output.m_eth_hdr_valid(tx_eth_hdr_valid),.m_eth_hdr_ready(tx_eth_hdr_ready),.m_eth_dest_mac(tx_eth_dest_mac),.m_eth_src_mac(tx_eth_src_mac),.m_eth_type(tx_eth_type),.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),// IP frame input.s_ip_hdr_valid(tx_ip_hdr_valid),.s_ip_hdr_ready(tx_ip_hdr_ready),.s_ip_dscp(tx_ip_dscp),.s_ip_ecn(tx_ip_ecn),.s_ip_length(tx_ip_length),.s_ip_ttl(tx_ip_ttl),.s_ip_protocol(tx_ip_protocol),.s_ip_source_ip(tx_ip_source_ip),.s_ip_dest_ip(tx_ip_dest_ip),.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),// IP frame output.m_ip_hdr_valid(rx_ip_hdr_valid),.m_ip_hdr_ready(rx_ip_hdr_ready),.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),.m_ip_eth_src_mac(rx_ip_eth_src_mac),.m_ip_eth_type(rx_ip_eth_type),.m_ip_version(rx_ip_version),.m_ip_ihl(rx_ip_ihl),.m_ip_dscp(rx_ip_dscp),.m_ip_ecn(rx_ip_ecn),.m_ip_length(rx_ip_length),.m_ip_identification(rx_ip_identification),.m_ip_flags(rx_ip_flags),.m_ip_fragment_offset(rx_ip_fragment_offset),.m_ip_ttl(rx_ip_ttl),.m_ip_protocol(rx_ip_protocol),.m_ip_header_checksum(rx_ip_header_checksum),.m_ip_source_ip(rx_ip_source_ip),.m_ip_dest_ip(rx_ip_dest_ip),.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),// UDP frame input.s_udp_hdr_valid(tx_udp_hdr_valid),.s_udp_hdr_ready(tx_udp_hdr_ready),.s_udp_ip_dscp(tx_udp_ip_dscp),.s_udp_ip_ecn(tx_udp_ip_ecn),.s_udp_ip_ttl(tx_udp_ip_ttl),.s_udp_ip_source_ip(tx_udp_ip_source_ip),.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),.s_udp_source_port(tx_udp_source_port),.s_udp_dest_port(tx_udp_dest_port),.s_udp_length(tx_udp_length),.s_udp_checksum(tx_udp_checksum),.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),// UDP frame output.m_udp_hdr_valid(rx_udp_hdr_valid),.m_udp_hdr_ready(rx_udp_hdr_ready),.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),.m_udp_eth_src_mac(rx_udp_eth_src_mac),.m_udp_eth_type(rx_udp_eth_type),.m_udp_ip_version(rx_udp_ip_version),.m_udp_ip_ihl(rx_udp_ip_ihl),.m_udp_ip_dscp(rx_udp_ip_dscp),.m_udp_ip_ecn(rx_udp_ip_ecn),.m_udp_ip_length(rx_udp_ip_length),.m_udp_ip_identification(rx_udp_ip_identification),.m_udp_ip_flags(rx_udp_ip_flags),.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),.m_udp_ip_ttl(rx_udp_ip_ttl),.m_udp_ip_protocol(rx_udp_ip_protocol),.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),.m_udp_ip_source_ip(rx_udp_ip_source_ip),.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),.m_udp_source_port(rx_udp_source_port),.m_udp_dest_port(rx_udp_dest_port),.m_udp_length(rx_udp_length),.m_udp_checksum(rx_udp_checksum),.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),// Status signals.ip_rx_busy(),.ip_tx_busy(),.udp_rx_busy(),.udp_tx_busy(),.ip_rx_error_header_early_termination(),.ip_rx_error_payload_early_termination(),.ip_rx_error_invalid_header(),.ip_rx_error_invalid_checksum(),.ip_tx_error_payload_early_termination(),.ip_tx_error_arp_failed(),.udp_rx_error_header_early_termination(),.udp_rx_error_payload_early_termination(),.udp_tx_error_payload_early_termination(),// Configuration.local_mac(local_mac),.local_ip(local_ip),.gateway_ip(gateway_ip),.subnet_mask(subnet_mask),.clear_arp_cache(0));axis_fifo #(.DEPTH(8192),.DATA_WIDTH(8),.KEEP_ENABLE(0),.ID_ENABLE(0),.DEST_ENABLE(0),.USER_ENABLE(1),.USER_WIDTH(1),.FRAME_FIFO(0))udp_payload_fifo (.clk(clk),.rst(rst),// AXI input.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),.s_axis_tkeep(0),.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),.s_axis_tready(rx_fifo_udp_payload_axis_tready),.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),.s_axis_tid(0),.s_axis_tdest(0),.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),// AXI output.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),.m_axis_tkeep(),.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),.m_axis_tready(tx_fifo_udp_payload_axis_tready),.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),.m_axis_tid(),.m_axis_tdest(),.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),// Status.status_overflow(),.status_bad_frame(),.status_good_frame());endmodulejust checked, all other verilog files taken from github with no changes.