8-channel ADC selection (suggestion of non-whiny* 1-channel ADCs also encouraged - Page 1
Forum section: electronics / projects

author: rs20
author_rank: Super Contributor
timestamp: September 03, 2017, 11:12:22 am
content: Going into it, I thought this problem would be as simple as slotting the appropriate ADC chip into my design. But now I'm pulling my hair out. Am I missing something? The required specs are as follows:-- Inputs: 8 differential channels, +/- 20mA (+/- 2V). all coming from current transformers and locally being terminated into a 100ohm load || 1uF smoothing capacitor (for a ~1.5 kHz fC).-- The ADC: Simultaneous sampling at 10 kSPS, 12+ bits.-- The output: Any form that be streamed into RAM by the DMA module in aSTM32F0.Priorities:-- Low BOM part count (not really fussed about cost, this is a one-off)-- Reasonable CMRRThat's all there is to the question; but I shall keep talking just to explain why I feel like I'm stuck:-- *Thefirst ADCI ever worked with could be run with its #CS pin held low and was fully clocked from the SCLK pin; which was great because I could just pull the #CS pin low manually via a GPIO in software, and then set the DMA in motion, which could do everything it needed with SCLK and MISO pins alone. But all the differential ADCs I'm coming across are whiny little brats whichrequirethat the #CS pin be brought high every sample, which seems needlessly complicated/incompatible with DMA? If I could find even a single-differential-channel ADC which was this easy to drive, I could just use 8 of them and read all 8 outputs at once via the DMA+GPIO.-- Many of these parts require ADC driver chips, which turns into a real BOM blowout when dealing with 8 channels. For example, theAD7779would be perfect if it weren't for the requirement for differential buffering. So chips with built-in buffering would be really valuable, and I'm happy to compromise heavily on DC bias/offset for this.Any suggestions or hints would be most appreciated.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 03, 2017, 12:01:58 pm
content: With a signal from a current transformer, I am surprised that a differential reading is needed and thus CMRR is important. Usually a current transformer is a isolated source and can thus be tied to a reference level / GND at will.With already having so much filtering with 1 µF caps, there should be no real need for simultaneous sampling. The filter will introduce delays (and possible uncertainties in the delay) that are more than the typical delay with 10 kSPS. So one might even consider using the µC internal ADCs. These are not the best, but usually 12 Bit.If there is no need for a differential signal, buffering could be as simple as a single OP. Unless one needs the full performance one could drive the AD7779 input also single sided. So I see not problem using the AD7779.With a 100 Ohms source impedance one might not need buffering, even if the data-sheets for the ADCs suggest some buffering for the best performance.With a sigma delta ADC, there should be no really need for a 1 µF capacitor for so much filtering at the input. SD converter include a kind of anti aliasing filter. So much less filtering (more like a 10-100 nF cap) should be sufficient.

author: rs20
author_rank: Super Contributor
timestamp: September 04, 2017, 07:14:53 am
content: Quote from: Kleinstein on September 03, 2017, 12:01:58 pmMaybe I'm missing something, but it was my idea that an isolated/differential line is ruined if you tie the minus side to ground and tie the plus side to a high-impedance ADC input -- because any common mode noise (e.g. capacitatively) coupled into the two side-by-side lines will be shunted to ground on the minus line, but proceed unhindered into the ADC where it will appear in the digital output. Right?In any case, if the AD7779 is suitable, I'd just use it differential anyway.Quote from: Kleinstein on September 03, 2017, 12:01:58 pmA "single opamp" needs at least a couple of support components, and with 8 channels that's 24 components straight up -- this is the sort of BOM blow-out I am looking to avoid!Quote from: Kleinstein on September 03, 2017, 12:01:58 pmThis is a great point; I was focussing on what kind of drop the ADC input current could cause in the capacitor over the period of a sample, and was getting worrying answers. But the drop across 100 ohms is negligible, so with any luck I can avoid all buffering.Quote from: Kleinstein on September 03, 2017, 12:01:58 pmThis is a great point, I had forgotten that ?? were so great at antialiasing; thank you for pointing this out.I am curious to hear how others would solve this problem; I doubt everyone would arrive at exactly the same solution (AD7779) as me; and the AD7779 (in contrast to what I said earlier) has a rather odd digital output where the data clock is running all the time, even if there's no data being transmitted. This makes it, as ever, perplexingly difficult to deal with using DMA so my current plan is to use a little CPLD instead to coerce the data in RS-485 and chuck it down the line. I'm sure others wouldn't wind up with the same solution!

author: AndyC_772
author_rank: Super Contributor
timestamp: September 04, 2017, 07:50:18 am
content: If you have an ADC with a clock that runs continuously, and has no requirement for CS#, how do you achieve synchronisation (ie. know which is the first bit of each sample)?I'd be concerned about an interface which relies on synchronising at power-up and then never losing track of which bit is which. A single clock error would break every subsequent sample until the system is rebooted.Most of my designs end up with an FPGA on them for some reason, so personally I'd use one to drive any suitable ADC with whatever pattern of signals it happens to prefer, then buffer into DPRAM and read via SPI. Insert a known synchronisation word after every group of samples as a check that the interface hasn't lost sync.

author: rs20
author_rank: Super Contributor
timestamp: September 05, 2017, 01:51:08 am
content: Quote from: AndyC_772 on September 04, 2017, 07:50:18 amThere's a DRDY pin which blips high for one clock cycle -- so there's no synchronisation issue per se; but it's still extremely unfriendly to DMA.

author: danadak
author_rank: Super Contributor
timestamp: September 05, 2017, 11:41:40 am
content: Possibly PSOC using Sequencing SAR (yields 12500 SPS). Note some parts have 2SARs + DelSig, so could do some simul sampling that way. Or use on chip S/H, T/Hto effect.See attached.Regards, Dana.

author: ajb
author_rank: Super Contributor
timestamp: September 05, 2017, 04:43:19 pm
content: Quote from: rs20 on September 03, 2017, 11:12:22 amCan't you configure the SPI peripheral to generate a CS pulse every transaction? I know you can do that on the F4/F7, using the NSS pin. Worst case, you should be able to drop CS, start the DMA transaction in software, and then raise CS in a DMA complete interrupt. Or you might be able to link a timer event and DMA or something to have it all happen in the background.

author: jbb
author_rank: Super Contributor
timestamp: September 05, 2017, 07:42:37 pm
content: Quote from: ajb on September 05, 2017, 04:43:19 pmYou can also use a hardware timer output (e.g. PWM) for this. The 'PWM' output pin can pull down #CS and while the timer event triggers the DMA.Note: if you want to attach some other device (e.g. memory chip) to this bus you'll have to be really careful about the access timing...

author: floobydust
author_rank: Super Contributor
timestamp: September 05, 2017, 08:00:21 pm
content: You could just bias the CT's at 1/2Vcc. CT's are low-impedance and don't pick up that much CM noise if filtered properly.I have done this with measuring 480VAC 100A and it simplified A/D requirements and lowered cost.Looking at AC energy metering IC's likeADE7878,it is single-supply with differential inputs and practically nothing for CMRR I think 50mV max. so not useful with CT's it is designed for.I have also usedLMP90100but it also has pretty much nothing for -ve input tolerance, and a bit slow.My point is "differential" sometimes is misleading on the datasheets.