Tesla H bridge likes to fail mysteriously - Page 1
Forum section: electronics / projects

author: Powermax
author_rank: Regular Contributor
timestamp: September 16, 2020, 02:50:17 am
content: I originally posted the question here, but didn't really get many good answers. Or to the other related questions I posted a while back over at r/askElectronics, so I thought I'd ask here, where all the cool EE's hang outhttps://www.reddit.com/r/AskElectronics/comments/isbozj/why_do_drsstcs_fail_when_run_continuous_duty/I'm trying to build a small desktop dual-resonant Tesla Coil using a series LC primary (50 to 100nf capacitor series with primary calculated to be 6.5uH, or around 200 - 300kHz resonant frequency. Real life test showed shockingly accurate frequency!) My FET's are rated 200V / 90A (HY1920P). I am using a 110Vdc supply voltage.Boring design details:PCB design can be found here:https://github.com/power-max/universal-half-bridge/blob/master/export/universal-half-bridge.pdfThe 2 HY1920 FETs are a bit far apart due because of the heatsinks constraints, so 30ns ultrafast diodes parallel to each FET were added, with them physically placed next to the _opposing_ transistor on my PCB. The Purpose of them is to create a lossless snubber and very small current loop. Overshoot energy is immediatly dumped to the local supply rail, absorbed by 4 100nf, 250V X7R bypass capacitors. I did not add additional snubber network since I thought it was not needed.The driver IC is a IRS2186, and dead-time of 100ns. (dead-time-insertion circuit is simply an 7400 series XOR gate because of the low logic threshold) I designed the circuit to operate slightly above resonance, so the primary appears predominantly inductive and ZVS condition can be achieved. A 12 ohm series resistor drives a 6nf 180nC gate to ensures soft turn on, and a 1n4148 diode ensures snappy turn off.---So what is killing my FETs??I doubt the FETs are dying from exceeding voltage.I hacked in a zener diode on the gate, even though gate drive looks fine. The diodes should guarantee the voltage does not exceed the supply voltage, which is half of the 200v Vds rating. They still die even at 48V supply when drawing a hot arc. I didn't see much overshoot on the D and S of the bottom FET when running, or the half bridge output measured at the top FET.Also doubt it's excessive current...When measuring the current with a DIY current transformer, I calculated 60A peak in/out of the primary when drawing a nice long arc. (transformer uses a absolutely MASSIVE ferrite core, 30T to 1T, 5 ohm 5W power resistor) The FETs are rated for 90A continuous, 24mOhms or so and they are not getting hot.Could it be shoot-through??I mean I added dead-time of about 100ns, and tried both increasing and decreasing it without much difference. Decreasing it a lot causes the output to not be very square and I get less power at the output.you can see the gate drive waveform (yellow) and Vout at 50V. Don't remember what the load was in this pic, I think I had it connected to the coil with a breakout point, since that seems to be when it fails most frequently.http://imgur.com/a/4XbPAiVDespite mitigations for miller effects (diode to discharge the gate fast, 12 ohm resistor to turn the other fet on more slowly) the effect of miller capacitance still looks pretty alarming! Look at the Vgs spike when the other FET is turning on! I really hope that is just bad probing and not real! 😱 If it is real, what can I do to really clamp that voltage to 0V when it is supposed to be OFF? Would adding a current amplifying transistor right next to the gate help?Could occasional shoot-through cause FETs to insta-fail without heating up much first?

author: Powermax
author_rank: Regular Contributor
timestamp: September 16, 2020, 02:55:22 am
content: More questions:What problems could I expect if operating below resonance, where the Xc term is not totally canceled out, or the primary load looks predominately capacitive? In this region I expect the voltage to not self-actuate but the current direction to change just before the FETs are switched.In such a mode, I was curious what would happen if I chose to use SCRs instead since you can get pretty beefy ones cheap! Though I'm too afraid of shoot through with that lol.

author: Whales
author_rank: Super Contributor
timestamp: September 16, 2020, 03:19:30 am
content: That gate voltage curve seems to very gently rise -> the fets may be spending a lot of time (eg 5-10% of each cycle) in their linear region. What current are you running through these?Did you buy your HY1920P's from a greymarket source or a reputable vendor?

author: Powermax
author_rank: Regular Contributor
timestamp: September 16, 2020, 03:36:27 am
content: I did that intentionally, as a mitigation of miller effect on the lower transistor, to prevent the bottom FET from conducting while the top FET turns on. You can still see the transient on that gate waveform. It did seem to help considerably with reliability, but it didn't fix it, I still kill transistors occasionally.Since my intention is to operate slightly above resonance, the current waveform is supposed to lag behind the voltage switching a bit. The result is that when, say, the top FET is turned off, the voltage fly's to the other rail to maintain current in the same direction, and is clamped by the body diode and/or the additional diodes I added. Then that FET is switched on gently. No need to hurry turning it onOperating below resonance will cause the current waveform to lead the voltage, so the current will reverse polarity before the transition occurs, and this would be undesirable region for the design as it stands since now the turn off losses are insignificant but turn-on losses dominate (switching on occurs during high voltage condition)Either way I never observed my heatsinks getting too hot to touch. They just get a bit warm, and they are not even very big heatsinks, maybe 10oC/WEither way I never observed my heatsinks getting too hot to touch. They just get a bit warm, and they are not even very big heatsinks, maybe 10oC/W

author: Whales
author_rank: Super Contributor
timestamp: September 16, 2020, 06:01:35 am
content: Hmm OK. If your waveform is as you say then you won't have issues (turn on + turn off + transient load changes too?)Keep in mind that heatsink temperature is not the whole story: operating most/normal FETs in their linear region quickly takes them out of their SOA, even for very low currents, which leads to catastrophic internal damages.

author: Phoenix
author_rank: Frequent Contributor
timestamp: September 16, 2020, 06:44:02 am
content: Quote from: Powermax on September 16, 2020, 03:36:27 amCan you zoom in on the waveform switching edges? It looks like that gate spike is still plenty big enough to start turning on the incorrect FET during transition. Also with a 50MHz scope you might be missing a lot of HF ringing.Got a photo of your PCB?

author: strawberry
author_rank: Super Contributor
timestamp: September 16, 2020, 08:48:07 am
content: phase feedback(or tune above unloaded tank circuit resonance frequency) and deadtimehttps://richieburnett-co-uk-mirror.gitlab.io/indheat.html

author: Wolfram
author_rank: Frequent Contributor
timestamp: September 16, 2020, 10:59:46 am
content: Be wary of negative spikes on Vs (pin 6) of the IRS2186. Non-isolated high+low side drivers like this one are notoriously sensitive to negative voltage on this pin in relation to the gate driver ground. Under "Absolute maximum ratings" in the IRS2186 datasheet, the high side floating supply offset voltage is given as Vb (high side gate drive voltage) - 20 V. If your gate drive supply is 12 V, then it would only take - 8 V on the switching node to exceed this specification. Having less than 8 V peak of ringing on the switching node with a two layer board is not trivial. Especially not when you're potentially switching high currents without ZVS, which is inevitable if you ever have a ground or primary strike in your DRSSTC.I prefer to use fully isolated gate drivers for applications over a few hundred watts, as they are a lot more robust towards switching node ringing. Also watch out for the maximum dV/dt rating of isolated gate drivers, although I expect this to be much less of a problem with less than 200 V on your DC bus. Most people use gate drive transformers with DRSSTCs for these reasons. Edit: there are fully isolated gate drive chips available as well, for example the SI8230, or the SI82395 if you want more dV/dt robustness.As this is more likely a layout problem than a circuit problem, I'd recommend posting some images of the board layout as well. I have KiCAD installed so it was easy for me to open the board files to have a look, but you're severely limiting the pool of people who will be willing to look into your problem.

author: Powermax
author_rank: Regular Contributor
timestamp: September 16, 2020, 01:45:10 pm
content: Quote from: Phoenix on September 16, 2020, 06:44:02 amI added some screenshots of the PCB. there is probably a way in KiCAD to make the ground planes translucent (I did it before) but for now the 3D viewer shows the clearest view of the PCB. Gerber files and a PDF schematic should exist in the export folder on my technical design package.Yes, if I zoom in on those waveforms, I can see the transient can be around 3V or so, sometimes more. I know when the FETs fail with gate shorted to drain, which used to happen with my old hacked up PCB and lots of mod wires, the whole FET would act basically like a 4V zener diode. As 4V is enough to turn the FET on apparently.

author: Powermax
author_rank: Regular Contributor
timestamp: September 16, 2020, 02:02:10 pm
content: Quote from: Wolfram on September 16, 2020, 10:59:46 amFunny you mention that, I had some accidents with accidentally shorting my supply to ground rail while probing points that were not ground on the PCB, and sure enough I blew pretty much every IC and voltage regulator. my old 7486 had a chunk blown out of it, IRS2186 had a blowhole, FETs survived! even the 7805 died.Same thing happened when I tried drawing an arc on the primary to ground, since the primary voltage rings up to a couple KV. shorting that node to ground caused the voltage at ground on the driver board to shoot down to the -KV region and same thing happened. Oops!Not sure if that is the failure mode otherwise though. Since its the hi or lo fet that dies, then 50% of the time the other FET dies from the shoot-through, even with a 100V power supply with pretty fast short circuit protection. (not much sparks when I short it.) I have a single 100uF ~400V photoflash capacitor for bulk filtering of the regulated supply on the board.Quote from: Wolfram on September 16, 2020, 10:59:46 amI added 3D screenshots of the layout of the H bridge on the last post, gerbers for it should be available on the github for anyone with a gerber viewer, in the /export folder, along with a PDF schematic.I think one mistake I made was not making the ground point of the gate driver IC a "star connection" to the source of the low side FET and instead opting to make it a filled plane. Maybe? not sure.Another thing I can try is adding a small value resistor that goes to the source of the Hi-side FET and a diode to clamp the voltage from going negiive. Would that help prevent negative voltage killing it? I did have the chip "shut down" a number of times while messing with the circuit at low duty cycles, but found that it came good after powering it off and letting it cool I guess. SCR latchup maybe? The chip runs slightly warm when working but gets very hot when it latches up and shorts my 12V rail.

author: DannyTheGhost
author_rank: Contributor
timestamp: September 16, 2020, 06:05:55 pm
content: I noticed quite thin traces going from driver to transistors - that is not quite good for traces that should carry ~4A current pulses. I suggest to make them wider, and to try really minimize all current loops - even if it means to change heatsinks. Your chosen frequency of operation is very hard to tackle and is not forgiving for this kind of stuffCapacitors for their high-frequency operation should not be placed outside of main current loops - when your transistors are switching they cannot draw energy from capacitors. In this case, capacitors are essentialy worthless.If you really doesn't sure about using cu pours - don't use them, make sure that you made good traces by yourself.In short - rethink your board layout.

author: Powermax
author_rank: Regular Contributor
timestamp: September 16, 2020, 08:55:39 pm
content: Quote from: DannyTheGhost on September 16, 2020, 06:05:55 pmHi DannyTheGhost, thanks for the feedback!You say the layout is bad, do you have any pointers? I analysed all the current loops to make sure they are as tight as I could get reasonably them, and I've seen what looked like worse layout on successful designs.You specifically call out the MLCCs. There are ultrafast 3A 30ns diodes at the source/drain of both FETs serve to clamp the voltage to the opposing rail. The current loop is as small as I could possibly make it! Take the bottom FET for instance, the loop area includes the package size of the MOSFET, the diode, and the nearest of the 4 capacitors, so if the drain exceeds VCC, the diode enters forward conduction and dumps the energy to the 4 local bypass caps. It should guarantee the local voltage across D and S does not exceed VCC, assuming diode conducts instantaneously and the overshoot on the silicon die is dependent on is the stray inductance which I minimized as much as I think I can without going to different package components.Hi side drive have the traces running close together to minimize loop area and inductance. Don't care about the distributed capacitance since the FET poses a ~6nf load. Lo side drive has the ground plane which runs alongside it that should work ad the current return. This is the one I'm less sure about, but I imagine high frequency currents run alongside the gate drive trace. I think I stitched the ground planes with a couple vias to help as well.

author: Circlotron
author_rank: Super Contributor
timestamp: September 16, 2020, 09:25:09 pm
content: Some stuff here about if the body diode conducts then you may trigger a parasitic bjt, causing failure.https://www.st.com/resource/en/application_note/cd00171347-mosfet-body-diode-recovery-mechanism-in-a-phaseshifted-zvs-full-bridge-dcdc-converter-stmicroelectronics.pdf

author: Powermax
author_rank: Regular Contributor
timestamp: September 17, 2020, 12:59:35 am
content: Quote from: Circlotron on September 16, 2020, 09:25:09 pmThat's a good thought, I have considered it. Looked at online pictures of equivalent circuits and it shows a BJT with a very low value resistor shorting the base to ground and the a capacitor to the drain, implying that the BJT is triggered with very high dv/dt.I tried to measure it and while I don't remember the exact slew rate, it looked to be almost exactly an order of magnitude higher than the maximum rating in the datasheet. I added 470pF ceramic film capacitors parallel to the H bridge and it seemed to make things fail more often. Need to find some 1nf caps and maybe my 5 ohm power resistors to make a random snubber network.

author: DannyTheGhost
author_rank: Contributor
timestamp: September 17, 2020, 05:34:20 pm
content: Quote from: Powermax on September 16, 2020, 08:55:39 pmThe point of decoupling caps here - to decouple transistor pins from all other traces. Here you have ~5cm traces and who knows how long cables to your tesla coil, which means TONS of parasitic inductance. You can get away with this kind of design only if operating frequency is below ~50khz, higher frequency means more switching losses, and more undesireable, unpredictable transients.First of all - make transistors closer to each other. Even if it means changing heatsinks and using only one heatsink.Then, you placed your electrolytic caps too far. Your power traces - VCC and GND - should come through their leads. This achieves at least some decoupling - you are getting rid of parasitic inductance that comes from power cables by making your capacitors as voltage sources for HF part. Do the same with ceramics. There is so-called 'hot loop', in which you have all above components.As I already mentioned - make your gate driver output traces wider. Driver tries to dump into/from them 4A peak - thin traces have more inductance than wider ones, so you may not see what is your real gate waveform.Frewheeling diodes are for your coil, not the transistors - you should put them closer to terminal pins if all mentioned above won't help enough.P.S. I wrote this with huge breaks - sorry if all points are not in better order.

author: Powermax
author_rank: Regular Contributor
timestamp: September 19, 2020, 03:33:16 pm
content: Quote from: DannyTheGhost on September 17, 2020, 05:34:20 pmPlacing the MOSFETs closer together is certainly going to be the next thing I will have to do while work on a new PCB. I think it is mostly the problem of the gate drive, the series inductance of my traces is apparently enough to cause the sudden di/dt fromm parasitiv Cds to cause the gate to shoot up, causing shoot-through. I can try hacking in a BJT current amplifier (PNP setup as an emitter follower) and see if that helps. The BJT will be placed right up at the MOSFET gate, hopefully a SOT23 package will be adequate for this. Can't do much to make the trace thicker until I finish a new PCB.I think I did an OK job with preventing ringing on the output because of the placement of the MLCC capacitors and the ultrafast diodes. They should close the "hot loop" you mention. When the FET is on, it should be impossible to have Vds > 200V, and when the FET is transitioning off, the voltage should fly to the opposite rail, and the local MLCC capacitors and diode should clamp this overshoot. This loop area only includes the FET, diode, and 4 100nF capacitors as close together as I can physically place them. Depsite this I do still see 5V overshoot, al for a 5ns period, which appears the freewheeling diode. The MLCC capacitors do successfully maintain a steady voltage w/o any visible transients. This test was done at low voltage so I'm not sure if it scales linearly with input voltage, hopefully not!Having a small amount of controlled inductance between the top and bottom FET (the output) is probably desirable in case of nanosecond long shoot-through, which is why a lot of gate driver IC's seem to suggest not having the FETs directly tied together and instead having the 2 connections join at the load. Not sure, but that was the reason I didn't really care to place the FETs super close together last time.

author: DannyTheGhost
author_rank: Contributor
timestamp: September 19, 2020, 08:21:35 pm
content: I re-checked your schematic, what you have here - freewheeling diodes for ZVS operation, they help body diodes with smooth transition. In this case they do not work as clamping diodes - what you actually needed in case of inductive voltage spikes.I'm pretty sure that you can actually make only worse with your BJT idea, so I'd rather not doing that.I'm suggesting to place some kind of RC or RCD snubber - see if it helps. At least it is a solution that can be made without making new PCB.Another thing I didn't remember to mention - MLCC caps - their capacitance is derating by applied DC voltage. In some cases - 20% of rated capacitance during 70% rated DC voltage. This alone can lower the chances to fully catch voltage transient.One of things you should definitely do - make your cables to and from coil as short as possible, for minimizing leakage inductance of your system.By the way - how much power you want to deliver to your coil?

author: Powermax
author_rank: Regular Contributor
timestamp: September 19, 2020, 11:59:15 pm
content: Quote from: DannyTheGhost on September 19, 2020, 08:21:35 pmYeah saying they "clamp" the voltage, what I mean is they clamp the voltage within the bounds of the supply. They are free-wheeling diodes as they "catch" the current of the inductive load, and as I understand using the ones in my MOSFET is not a good idea in general. I did the math and found that even if I did, they should not dissipate a lot of power (reverse recovery charge Q = 160nC, 160nC * 300kHz = 4.8W) although I guess instantaneous power could get pretty high, outside the safe operating regions? I would think the power dissipation in my added diodes is in fact smaller. MOSFET body diode is rated for the same 90A as the FET.How would it be worse with the BJT to help discharge the gate faster? The idea here is to clamp the voltage at 0V and forbid any voltage appearing at the gate, causing it to conduct. this transistor will be close to the MOSFET to reduce series inductance (make loop area small) As a consequence the dv/dt will be higher, however.If the dv/dt is too high then the only practical solution is to add a snubber. Thinking a 4.7nf and 1 ohm resistor would be a good place to start.You mean to not use 1 foot long alligator clips running to my 10 turn primary through a bunch of MKP film capacitors strung up in series? Or provide power from a long leads coming from my power supplies strung together in series?? Or switch 120VDC at up to 10A through an automotive 10A 12v relay? NAHHHHI want to deliver all the power in the world to my coil!Well realistically 120V outlets are typically 12A maximum sustained. I'd be happy if the only thing I was popping with the coil was the circuit breaker.

author: Powermax
author_rank: Regular Contributor
timestamp: September 20, 2020, 12:25:54 am
content: While I can't test it right now, I am going off the top of my head with the figures, I think I measured rise/fall times to be on the order of 50 nanoseconds. This was measured at 55V before I had the balls to try putting my 2 supplies in seriesBut just thinking about that... 50V / 50ns = 1V/ns! That's 1000V/μs maybe my FET's just don't like that dv/dt!The datasheet for those particular FET's does not make any claims for how fast is too fast. Just the 165pf of reverse transfer capacitance. Well, I = dv/dt * C = 165pf * 1V/ns = (165 * 10^-12) * (1/10^-9) evaluates to about 170mA or so. Doesn't sound too crazy.I guess that the switching time is about constant, which means it would end up being closer to 500mA at the 170V I eventually want to try, that's quite fast. Still I would expect the huge gate capacitance to clamp that. It should act like a capacitor divider right!?

author: Powermax
author_rank: Regular Contributor
timestamp: November 15, 2020, 07:48:49 pm
content: update / (bump)I have been fiddling with the circuit more. I can't find any evidence of over-voltage being what kills my MOSFETs. I have tested my Tesla coil driver now with the full 170VDC from the wall, half and full bridge rectified. The coil seems to fail most frequently in the following conditions:if higher voltage but lower current transistors are used (FDP33N25 vs HY1920P)High voltage secondary is short-circuited or nearly so.output is tuned to resonant with the primary. (using current transformer feedback).continuous wave (no interrupter) and smooth filtered DC.coil operates fine off half-wave rectified unfiltered AC.cooling fan extends life of TC very slightly at the cost of noise (acoustic and electrical EMI) from the fan being present in the otherwise silent arcfailure does not seem to be related to power supply current, probably as a result of reactive current between the primary and the series resonant capacitor. Seems to be at a peak when things fail.*I think it is in fact OVER-CURRENT that is killing my MOSFETs.But, peculiarly, the heatsinks don't get very hot (evidenced by me feeling them immediately after failure). Usually they are just very warm, one being a bit warmer than the other (although I don't remember if it is the low-side or high-side). Probably around 50 to 60*C since I can keep my hand on them for several seconds or indefinably.Can MOSFETs fail from over current even if they're kept cold? (from perhaps some quantum process I am not familiar with), or does current simply cause the junction to heat up to the point where the FET fails short circuit; i.e. is there a hard limit on how much current a FET can carry even if it is cryogenically cooled?While the HY1920P is rated for 90A, similar spec'd FETs from more reputable manufactures claim 60A as the maximum (ones with similar on-state resistance and Ciss). I've only seen 90A peaks (peak during the peak of the RF envelope shortly after interupter enables the FET driver) on the current transformer a few times when monitoring w/ a scope when running the coil in interrupted mode. When run continuous wave it seems once the RF envelope is stable, the primary resonating current is around 60A peak, or 43A rms. Each FET only conducts one half cycle of current, so the RMS per fet should be half. With 20mOhms of on-state resistance each FET should only be generating 9W of heat. This sounds very reasonable, although the peak power dissipation is much higher, 162W.What is the best thermal interface material to use for joining the FETs to a heat-sink?Ideally I'd buy some beryllium oxide ceramic insulators, but those are hard to come by, although Digikey does sell them for TO-3 packages. I'm probably going to buy a couple before they become obsolete, even at $20 / piece! aluminum nitride is another pretty decent ceramic insulator but it also is hard to find. Aluminum oxide is the 3rd option but it's thermal conductivity much less.! As of now I've been using some sil-pads I have in my junk drawers, of unknown origin (most of them salvaged). For now I might just try modifying my PCB so the heatsinks are electrically tied to the middle pin to eliminiate the need for an insulator, that should provide the best thermal performance, and monitor the heatsinks with my thermal camera to see if I can rule out thermals being the problem.* NOTE the RF current was measured by using a DIY current transformer; 30:1 turns ratio around a random green ferrite and a 5 ohm resistor, with voltage amplitude as high as 15V observed, but generally around 5 to 10 volts when run continuous duty

author: Wolfram
author_rank: Frequent Contributor
timestamp: November 23, 2020, 07:02:34 pm
content: Quote from: Powermax on November 15, 2020, 07:48:49 pmThe die will always be warmer than the casing when power is being dissipated, due to the thermal resistance between them. So it's possible to overheat the die with a reasonably cold casing, in case of excessive dissipation. Additionally, any extra thermal resistance between the casing and the heatsink will make the situation worse. Due to the small thermal mass of the transistor itself, it's possible to overheat the device and then have it cool down again before you can check the temperature, so make sure you measure the case temperature while it's processing full power, ideally with a thermal camera or an IR temperature probe.QuoteIgnore the current rating in the datasheet, this is practically useless for real world use. Extreme cooling measures are used to get this figure (I've heard of full immersion in nucleated boiling Freon), and it also assumes all the dissipation comes from conduction losses. Likewise, the 375 W dissipation rating in the datasheet for this TO-220 device is practically unrealizable, even a tenth of this dissipation requires some care.QuoteThis sounds like too much current for the performance you're getting. Having a resonant primary in this configuration complicates things by requiring correct tuning between the primary and secondary resonant frequencies, while the secondary resonant frequency changes with spark loading. I've had good success with an untuned primary coil in CW SSTCs. As long as you keep the primary-secondary coupling high (above 0.3 or so), you can push plenty of power without excessive primary magnetizing current.Also, do you have any current limiting or overcurrent protection? Running a double-resonant CW Tesla Coil with arcs to ground can lead to very high primary currentsQuoteThe full current half of the time equals 71 % (1/sqrt(2)) of the RMS current, while the average current is 50 %. The Rdson is 24 mohm max at room temperature, but 3x this value at Tj = 150 C. This gives 66 W of conduction losses per device, and switching losses come in addition to this. For a TO220 mounted with a screw through the hole, thermal resistance between the casing and heatsink is usually around 1 k/W, in addition to the 0.4 k/W of thermal resistance from the die to the casing. This gives a total thermal gradient of 66 W * 1.4 k/W = 92 k, on top of the 50 - 60 C heatsink temperature. This gives 150 celcius for the junction, without considering switching losses and budgeting for variations in device-heatsink contact. It's plausible that your problems simply come from overheating of the silicon dice inside your MOSFETs. If you want to push over 40 A RMS at 170 V, I would recommend going for more devices in parallel or a bigger package like a TO-247.QuoteAlN is similar in performance to BeO, and it doesn't have any of the issues with toxicity that BeO does. It's also much cheaper than BeO if you buy it from China on eBay or Aliexpress. 50 cents for TO-220 sized pads, and about twice that for TO-247 sized pads is typical.QuoteAluminium oxide is about an order of magnitude worse than the Nitride, but it's still pretty decent, and also cheaper by at least as much. A 0.63 mm thick pad of Alumina will add around 0.3 k/w for a TO-220 device, which is often much less than the required thermal grease adds. Other factors can easily dominate the thermal resistance here, so to fully benefit from AlN you also need precision flattened and polished heatsink surfaces, a good thermal grease and plenty of clamping force applied evenly across the device package. If you just bolt the device to a stock extruded heatsink with a screw through the hole in the package, I doubt the difference between Al2O3 and AlN would even be visible.Sil-pads are pretty miserable. Bergquist 900S in 0.23 mm thickness adds over 3 k/w for a TO-220. In my calculation of the junction temperature above, you can add another 120 degrees in this case.Nothing beats direct contact between the device and the metallic heatsink, when that's possible. But to get the full benefit of this, the heatsink flatness, finish and clamping force matters a lot here too. A well clamped transistor with a thin alumina pad can easily be much better than one without any insulation at all, but mounted using a single screw through the package hole.QuoteThis is an excellent method to measure HF AC currents, I've made many HF CTs like this, and in many applications they perform just as well as 500 dollar Pearson wideband CTs.

author: Powermax
author_rank: Regular Contributor
timestamp: November 23, 2020, 08:56:19 pm
content: Yeah I realized how crap silpads really are, and even Mica sheets, just look at these thermal images! Each thermal image was taken with the TO-220 device set up to dissipate about 9.5W. I should have been more scientific about it, I forgot which thermal image is with which thermal interface!Suffice it to say, the really bad ones are mica and silpads. I think I calculated a bit over 1 *C/W, and 0.5*C/W for the one using just arctic silver 5, measuring heatsink temperature vs the plastic case temperature. (I might be measuring the junction to case of 0.4 *C/W for the HY1920P with this test... Huh!I just bought a pyrolytic graphite sheet on DigiKey, a bunch of alumina TO-247 insulators, and the highest performance sil-pads money can buy (well not really, I'm not spending $1000 on the really good ones, the best cheap ones). I might make a video being more scientific with my testing, too.http://imgur.com/gallery/Q0oAqgV

author: profdc9
author_rank: Frequent Contributor
timestamp: November 24, 2020, 12:26:30 am
content: I can provide an example of my full-bridge PCB from my projecthttps://github.com/profdc9/DRSSTC-PCB-Packin the directoryhttps://github.com/profdc9/DRSSTC-PCB-Pack/tree/master/full-bridge-transistorNotice a few things:Traces are as well as possible by using copper fills to utilize copper around components.Copper clearance is 2 mm to ensure no arcing from high voltage.DC Link capacitors are placed as close as possible to the source/drains of the MOSFETs. There is a continuous copper plane to supply power from the capacitors.Similarly, there is a continuous copper plane as the output of the bridgeAt the corners are the input from the gate drive transformers. Obviously you may need to change this if necessary because you are using hi-side drive ICs. Bootstrapped hi-side drives can have their own issues too by the way with voltage transients.Also there are RC snubbers. If you are drawing arcs, you an have high voltages on the bridge when arcs break. You may need snubbers at source/drain to prevent overvoltage of the transistors.Also, you may need TVS diodes to absorb those kind of brief overvoltages from arcs as well. I would try TVS before RC snubbers as the snubbers can definitely dissipate significant power at high drive frequency.