Are high-side gate drivers (like IR2106) easy to use and short proof? - Page 1
Forum section: electronics / projects

author: Whales
author_rank: Super Contributor
timestamp: May 14, 2025, 05:39:42 am
content: A few months back I tried a high-side bootstrap-style N mosfet driver for the first time:The (offbrand HGsemi IR2106) drivers misbehaved and I destroyed a couple of them, but could not work out why at the time and put it aside. I have since been putting some more thought into why.Q1:Are the output current limits for these drivers a safe limit (self-limiting) or a do-not-exceed-this-maximum? ie do I need to size my gate resistor so that the driver can't possibly exceed the datasheet output current limits when charging the gate of my mosfet?Q2:Can oversizing the bootstrap capacitor (C6) similarly cause overcurrent failures? Or is it safe to heavily oversize it?Q3:How do I determine if I'm going to overstress the part thermally? P = Gate charge * frequency * voltage, or does something else dominate?I notice that the official (non-knockoff) IR2106 datasheet suggests that driving at hundreds of KHz can get it quite hot:The HGsemi datasheet of course doesn't list anything that could help. Even the official datasheet makes me feel like I'm missing lots of stuff, and the gate driver appnotes I've seen do not seem to address my points above.I was tempted to build my own bootstrap gate driver circuit out of discrete transistors (), but the level shifting of a low voltage input signal to a 24V referenced gate drive turned out to be harder than I thought.Q4:Are gate driver transformers ever simpler, cheaper or better than one of these bootstrap high-side drivers (ignoring their advantage of high voltage isolation)? I assume not, but I might be wrong.

author: BennoG
author_rank: Frequent Contributor
timestamp: May 14, 2025, 07:04:16 am
content: They are not short proof to begin with.For the ringing you can use a snubber circuit over the mosfet or the output (I don't know what the best position for it is)Please someone with more experience with snubbers can explain what the best position is.And optional how to calculate the values for R and C.Benno

author: jwet
author_rank: Frequent Contributor
timestamp: May 14, 2025, 03:02:53 pm
content: They generally require careful design- calculation and good layout. Whenever you get high currents, high voltages and high speed together- you have to watch things. Small parasitics that usually don't matter can turn into big problems- things like small inductances with big di/dt's turn into big spikes. The other thing about these high side parts is that they are floating at the high rail (<600v) and one slip with a test probe and they're gone along with the end of your probe and your nerves for an hour. Other than the level shifting stuff, they're pretty simple parts. They're just a beefy CMOS switch with a boot-strap cap across them. They push the charge in the boost cap to a FET with a big gate charge (hign non linear capacitance). That big slug of current has to have a clean low inductance path from this part to Vgs. (layout- keep the high current loops fat and small).-- I'll try to answer your Q's- I used the IR2106 data sheet and the SE4060GBQ1- The abs max ratings are do not exceed values, the static and recommended are design guidance and are recommended. The external gate resistor limits peak current and is kind of damper in these circuits- its adds a little loss to what would otherwise be resonant- the parasitic L and gate C. The parts are designed to drive discharged capacitive loads- which are a short first order but turn into an open after charging. The short circuit current in the static specs of about 200 mA is what the part can provide for 10 uS- from this you can calc what your gate charge time will be, it also implies the Ron of the HS driver (10v/.12) = 83 ohms. Your FET has a charge of ~15 nC, if you feed it 120 mA (min high current for IR2106), you'd charge it in 125 nS. Is that what you want? This current would go though the gate R and would drop only about a Volt but could drop ten (the whole gate drive) if the current tried to get to 1 amp. There is no max current spec- all you get is a min that it can source 120 mA for 10 uS and can sink 250 mA for the same. Its limited by the Ron of the FET's and so in this sense they are current limited but only for short pulses. What's going to burn the part up isn't peak I (this is limited by FET R's), its power dissipation which we'll get to.Q2- There is no reason to oversize the boost cap. Each time the gate fires, the boost cap will provide the charge and you'll get a little ripple at Vb. If you have a .1 uF and take 15 nC at 10V, you'll droop Q/C or 15 mV- its charging up though a diode so will recover quickly. Even at a Mhz, this doesn't matter. The boost cap also has to provide what ever quiescent current the HS drive takes in the off state and the leakagae of the boost diode, etc. All pretty minimal. Having extra energy stored here might be a detriment.Q3- Your P=QVF is the main part of the dissipation and will dominate. There is some ohmic type losses like the quiescent current power but its pretty small comparatively. The formula assumes that the driver charges up the gate to on and then discharges for off. This is all internal to the driver. The gate resistor can be used to dissipate some of the power that would be dissipated by the drive but don't get carried away.Q4- Pulse transformers are more complicated and expensive. They are useful when you get to where these level shifter parts run out of iso volts(600 or 1200 for the common ones)Vishay has written books about driving FET's as has Motorola and Infineon.Also- In your circuit above, the diode that feeds the bootstrap diode should be fast recovery type- a schottky is common if you watch leakage. The 1N4007 is almost the worst part you could use here. A slow diode here could wipe out the driver when Top FET turns on and drives current thought the boostrap into the positive supply with any inductive boost added to it.

author: Whales
author_rank: Super Contributor
timestamp: May 14, 2025, 08:52:58 pm
content: QuoteOuch. Only working with <50VDC as my bus here, so I'm more worried about shorts than static voltages, but thanks for the heads up anyway.I can't claim "no probes were hurt in the making of this design" as I've already melted the caps of two after having them clipped on a TO-220 P-chan mosfet that got above 100degC.QuoteI didn't post a pic of my layout (apologies) but I think I should be good here. I placed the driver chip right against the gate drive resistors which are themselves right against the gate pin. Lots of vias for ground to the ground plane.I do perhaps need to pay attention to the 12V incoming power a bit more though, I think it's a snake across the board. Hopefully lots of local capacitance should help.QuoteAhah, good to hear they're not abs max ratings. There were not in the abs max section of the datasheet, but I was still suspicious I might be misinterpreting them.I guess that they're just the min saturated drain channel currents for the output transistors inside the IC.QuoteOK. The datasheets mostly seem to gloss over the "why" behind this. I found an appnote which provides some calculations, but I assume your rule of thumb (100nF being >> gate charges & capacitances) might be what the datasheets are assuming I follow too.I tried some spice sims with my own discrete bootstrap high-side gate driver and found that 100nF wasn't enough, which prompted me to put larger caps in. I think now that your next point might explain this however:QuoteWoops. Ty muchly. The 1n4007 has 2us of recovery time (whenstronglydriven).This might explain much of the weirdness I saw.

author: mtwieg
author_rank: Frequent Contributor
timestamp: May 14, 2025, 09:45:53 pm
content: Bootstrapping drivers are fairly simple and easy to use, but there are some common "gotchas" to avoid:1. Obviously, the high side cannot be kept on continuously (unless you add some sort of isolated power supply or charge pump to keep the bootstrap cap charged).2. In order to operate at all, the switching node needs to first be pulled near GND, so the bootstrap cap can charge up (enough to satisfy its UVLO threshold). In most cases this is taken care of by the switch node being loaded to GND initially. However, in some cases this will not happen. The simplest example is if this is a buck converter connected to a 24V battery. In that case, when the gate driver is powered up, the battery will hold the switch node at 24V, meaning the bootstrap cap cannot charge. You need a low side FET to force the switch node low at least once so the high side driver can start working.3. Generally it's advised to make the bootstrap capacitor smaller than the bypass capacitor for the Vcc pin.Power dissipation usually isn't an issue for these gate driver chips. Quiescent current will increase with switching frequency, even with no load connected to the gate driver output. The actual gate charge will also cause some power dissipation, which will also be proportional to frequency. If you have external gate resistance, then those resistors will bear a fraction of that power instead.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: May 14, 2025, 10:54:36 pm
content: Such MOSFET drivers have quite fast current pulses with steep flanks. As a result PCB layout for these things is quite critical. 1N4007 is also a very slow diode, and not suitable for this application.