SPI and CAN BUS Signal Integrity  - Page 1
Forum section: electronics / projects

author: sanwal209
author_rank: Regular Contributor
timestamp: February 23, 2018, 02:49:20 pm
content: Hi,We have a board on which MPC5774P MCU is connected to external flash via SPI and have 3 CAN BUS. SPI and CAN BUSES are working fine but we want to make sure in field it will not go absolutely nuts due to some noise.What could be the possible tests to make sure SPI and CAN BUS have good signal integrity. If i check for signal integrity then what is accepted level of error. I am totally confused here.

author: jbb
author_rank: Super Contributor
timestamp: February 23, 2018, 07:06:05 pm
content: Well done for being proactive about this!Generally, I would be more worried about the SPI bus. SPI was really designed to go on a circuit board. CAN was designed to work over wires inside a car (a difficult environment).I suggest the following as the ‘basics’:Review your software to estimate what happens if data gets corrupted. Or a wire falls off :-|.Check you have ESD protection on your SPI and CAN cable ports. (Note: CAN driver chips may have it built in.)Measure the waveforms at both ends of the SPI with a scope. You want to see smooth rises and falls, without overshoot, undershoot or cross talk.repeat test with minimum and maximum supply voltage.Put the units in an oven and run them for some hours at the maximum specified ambient temperature.Put the units in a freezer ...Following that, it’s time to do some EMC lab work:Do some ESD testing.Do EMC immunity testing (I.e. hit the unit with external RF sources to see what happens.)You’ll need to determine which standards you test to - which is where I always feel a bit uncomformtable because there are so many to choose from...

author: Brutte
author_rank: Frequent Contributor
timestamp: February 23, 2018, 07:54:32 pm
content: You should put a stress on a bus.With short SPI the problem is the impedance of the lines. Increase R*C on the lines for tests. Pick values that would double the natural RC constant. If it passes the tests with additional load then it would most likely work flawlessly without it.With CAN - well a termination could be a problem, also abuse (shorts, overvoltages etc).

author: sanwal209
author_rank: Regular Contributor
timestamp: February 26, 2018, 08:43:36 am
content: Thanks @jbb and @Brutte, I really appreciate it.What if there is an under or over shoot on line how can i tackle it? I didn't checked SPI because of the busy schedule of software guys but i did check CAN BUS and there is high frequency ringing on it. How can i remove it?I have attached CAN Filter which we have on board and snapshot of the waveform.Another question which confuses me is that for example if we have some noise on either SPI or CAN, how can i know which is acceptable value of noise?

author: tautech
author_rank: Super Contributor
timestamp: February 26, 2018, 09:08:40 am
content: Probe the supply pin of the MCU and the main power rails too to check if supply decoupling is sufficient to suppress noise that might be coupled through to the bus.You've got enough channels to line up all the traces to check if it's a problem or not.Use AC coupling for these checks.

author: sanwal209
author_rank: Regular Contributor
timestamp: February 26, 2018, 09:49:25 am
content: @Tautech Thanks, I will post the snapshot of waveform soon.

author: sanwal209
author_rank: Regular Contributor
timestamp: February 26, 2018, 10:00:19 am
content: Attached are the snapshots of MCU Supply and CAN Transceiver Supply

author: tautech
author_rank: Super Contributor
timestamp: February 26, 2018, 12:07:39 pm
content: Quote from: sanwal209 on February 26, 2018, 09:49:25 amYes, but show this trace ...........on/in this setup >3 channels !That will show if there is a correlation between supply noise and bus noise and then you can make choices if supply noise needs further/more decoupling.

author: sanwal209
author_rank: Regular Contributor
timestamp: February 26, 2018, 12:40:46 pm
content: CH1 & CH2 are on CANL & CANH. CH3 is on Power supply with AC Coupling.

author: tautech
author_rank: Super Contributor
timestamp: February 26, 2018, 12:50:02 pm
content: Quote from: sanwal209 on February 26, 2018, 12:40:46 pmNo.CAN; DC coupled, 1V/div, 2us/div.Then add ch3, AC coupled, 20mV/div, and same timebase setting 2us/div.All 1x probe.

author: vealmike
author_rank: Regular Contributor
timestamp: February 26, 2018, 01:21:05 pm
content: Let's start with CAN, which is I2C with a checksum. And Let's assume a single master and a single slave. This is a generic preceedure for measuring any clocked bus.The goal of your signal integrity measurement is to ensure that the design has sufficient margin, both in terms of voltage and time for the bus to work.The bus is bidirectional ,both slave and master drive SDA and SCL (see clock extension), so the measurement should ideally be taken twice, once at the pins of the master and once at the pins of the slave. We can take probably a shortcut and only measure one end as the bus is slow, I'll explain that nextSo, at one end of the bus, attach a 'scope to both SDA and SCL.Measuring SDA, measure the rise time and the fall time of the signal. Use Vil min and Vih max as your thresholds. Now do the same to SCL.Because this is an open drain bus with pull ups, you should find that rise time is very much longer than fall time.Now measure the longest SDA / SDA trace on your board. We want to find out if we need to consider it a transmission line. Can we ignore propagation delay and reflections? The answer is almost certainly 'yes' for I2C. If we can ignore them then one measurement anywhere on the bus will suffice. If we can't then we have to take one measurement at each master & slave.The simple rule is that if the rise (or fall) time of the signal is less than three times the transmission line propagation delay, then treat as a transmission line. The reason for this rule is simple. Imagine a transmission line of length x picoseconds.The master sends a bit at time =0, and x picoseconds later the bit arrives at the slave. Being imperfectly terminated, the signal reflects at the slave and heads back towards the mater. At time = 2*x the reflected signal arrives back at the master and, being imperfectly terminated, reflects again. At time =3*x the reflected signal arrives at the slave.So the slave sees the original signal at time = x and the first reflection at time =3*x. Now if the signal being sent by the master has a nice slow rising edge, it will still be rising at time =3*x and if it is, we can ignore transmission line effects.It's a rule of thumb, it's not perfect as I'm sure other posters will be quick to point out. But it does get you thinking about what's going on, and that's a good thing!So, measure your transmission line in inches, and use the 180ps/inch guideline to work out if you have a transmission line or not.Let's assume not.Now lets measure some margins. For I2C everything is clocked on the rising edge of SCL.Firstly, look at SCL rising edge. Is it monotonic? If not, stop and fix it (transmission line problem!). Only carry on when it's good.Next, set your 'scope to trigger on the rising edge of SCL, set infinite persistence and capture SDA with the two waveforms separated on the display.Adjust the timebase so that you see SDA changing before and after the rising edge of SCL and let it run. You'll see a distinctive eye forming on SDA.There are four measurements we're interested in. We want to know that SDA has sufficient setup and hold time, and we want to know that we have sufficient voltage margin above Vih max and below Vil min.Set your Y cursor at VIL min on SDA. It should cross the eye at two points, one before and one after the clock edge.Measure the time from VIL min before the clock edge to the clock edge. This is the set up time that you have for VIL.Measure the time from VIL min after the clock edge to the clock edge. This is the hold time that you have for VIL.Set your Y cursor at VIH max on SDA. Again it should cross the eye at two points, one before and one after the clock edge.Measure the time from VIH max before the clock edge to the clock edge. This is the set up time that you have for VIH.Measure the time from VIH max after the clock edge to the clock edge. This is the hold time that you have for VIH.Take the smaller of the measured VIL setup and the VIH setup. Look at the spec. of the receiver IC and find the setup time. If your numbers are bigger, congratulations! You have design margin.Repeat for the hold times.Now you need to measure voltage margin. Set x cursors at the setup and hold times specified in the datasheet. Look at the top of the SDA eye only between these two cursors. Is it always above VIH max? Great, that's margin.Repeat for VIL min.Once you know these basics, you can apply to any bus.Hmmn, from memory, the I2C protocol hold time is measured from the falling edge of SCL, so you will need to tweak the above, forgive me for not retyping. I've already spent too long on this!Hope that helps - a bit.

author: JPortici
author_rank: Super Contributor
timestamp: February 26, 2018, 01:50:44 pm
content: Quote from: vealmike on February 26, 2018, 01:21:05 pmit's not. not at all.Quotethere is no such thing as master and slave in a can network. only nodes talking on the bus.Quotebut CAN is not a clocked bus. there is no clock line.anyway, regarding the ringing in the first photo, could it be related to that LC filter? i ran a simulation and the oscillation frequency was around 1MHz, which is what i see in there

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 26, 2018, 02:00:26 pm
content: What relevance is the SPI bus? Does it leave the board?CAN in general is ridiculously robust, both in common mode range (meets or exceeds RS485 levels -- supposedly the first CAN devices were built with RS485 transceivers), transient tolerance (some 42V peak) and protocol reliability (checksums and automatic retransmission). You can literally send it down wet string!**Wet and salty.The only change I would make is to remove the ESD diode outside of the CMC; you're restricting the CMC's range there, which will cause worse signal quality under very noisy conditions (when the ESD diode is occasionally driven into conduction). If anything, an R+C damper could be placed there instead, to help dampen the common mode oscillations visible in the dominant state. It's tricky to recommend anything at all, really, because inevitably the components will be imperfectly matched, leaving some residual emissions that the CMC would've otherwise filtered out.Tim

author: sanwal209
author_rank: Regular Contributor
timestamp: February 26, 2018, 02:21:55 pm
content: SPI Bus doesn't leave the board. It is used only to communicate between 1x MRAM, 1x Flash and MCU.So i have checked the Main switcher and the osculation is due to main switcher. As T3sl4c01l suggested to use R+C damper to dampen the oscillations. Thanks a bunch. I will try to remove also the ESD Diode outside CMC.Thanks a lot guys

author: vealmike
author_rank: Regular Contributor
timestamp: February 26, 2018, 02:22:23 pm
content: Quote from: JPortici on February 26, 2018, 01:50:44 pmFair enough, I stand corrected. I've never used it, so I'll bow to you on that.