Thumb Rule for Via Sizes - Page 1
Forum section: electronics / beginners

author: Vini Ness
author_rank: Newbie
timestamp: May 29, 2025, 12:36:07 am
content: Hi GuysI'm using a Eagle to design some simple, 2 Layers PCBsIn general i follow those size rules6mil for the traces (Minimun free on JLCPCB)12mil for the via drill (Minimun free for JLCPCB)So, my questions are1.: What is the thumb rule for the relation between, trace, Via Drill/hole and Diameter/Annular ring?2.: What is the good value for the diameter/Annular ring of the via when i use 12mil for the drill/holeThanks for the Help!!!

author: Konkedout
author_rank: Frequent Contributor
timestamp: May 29, 2025, 03:14:39 am
content: Why make your traces only 6 mils?IFyou have the board space available, except in rare situations, you are better off using more copper. It is more robust against physical damage, offers slightly less layout inductance, and it provides lower DC resistance. I like to make my traces (we call them tracks in KiCad) as wide (or almost as wide) as the pads to which they are connecting.Similarly, No reason to make your vias small unless you are squeezed for space. I would use something like a 40 mil via with a 20 mil pad. Why increase the risk of having it break or be a bad via?I am testing my web access here....Ignore this sentence.

author: jwet
author_rank: Frequent Contributor
timestamp: May 29, 2025, 05:07:19 am
content: I agree with Konkedout- use the loosest rules that you can for your whatever you're designing. This is specially true for prototypes and early production where there is any chance of rework. You can optimize later.If you're doing middling SMT work with SOIC's etc with 50 mil lead pitch. You'll generally have 25 mils between pads. If you want to push a track and two spaces between pins, this is 8 mil tracks min with 8 mil spaces, or 10/7. I would only use this 8/10 mil when I needed to go between pads. If you're doing stuff with 25 mil pitch, 6 mil tracks and 4 mil spaces but don't do this unless you need to. If you're down a .5 mm BGA and trying to escape some via hell, you do what you can.I do a lot of mixed signal and my favorite pitch is 12/12 routing analog with 20 or 30 mil power tracks. I do digital at 10/7. I've done finer but I generally farm that stuff out.30 AWG wire-wrap bodge wire is about .01 and for reasonable solder clearance its nice to be 5 over so don't make vias any smaller than that .015 to .5 mm. 6 mil boards are difficult to troubleshoot and rework. Board houses can yield at 4/4 rules but don't do it if you don't NEED to.

author: Solder_Junkie
author_rank: Frequent Contributor
timestamp: May 29, 2025, 09:58:11 am
content: Like the other reply, there is no reason to use the smallest of tracks, unless you really need to route between pins of a part.A point to be aware of when designing boards that useanythrough hole parts... if the holes for components are only just a fraction larger than the component leg/wire, removal of the component can be almost impossible. The reason is that removing solder with a sucker (or solder wick) doesn't entirely remove the solder and you cannot move the component leg/wire with the tip of your soldering iron to create a bad joint, as it is such a tight fit!Measure your components with a digital caliper to ensure your board holes are slightly larger. PCB design software doesn't know about your particular components, it is easy to measure them and avoid possible future problems.I've had to throw away a board where I couldn't remove a part without damage to the board, and I worked on board level repairs for nearly 20 years!

author: PGPG
author_rank: Frequent Contributor
timestamp: May 29, 2025, 10:32:14 am
content: My standard is to use 0.25mm (10 mils) tracks and 0.2mm (8 mils) when needed.When routing I use (all in mm) 0.8/0.4, 0.9/0.5 and 1.0/0.6 vias.Smaller vias with 0.3mm hole I use only at IC bottom exposed pads.Quote from: Solder_Junkie on May 29, 2025, 09:58:11 amLast time we were using THT ICs was in 90s. When I had to delete it I cut it out and then was removing pin by pin.

author: Solder_Junkie
author_rank: Frequent Contributor
timestamp: May 29, 2025, 10:42:16 am
content: Quote from: PGPG on May 29, 2025, 10:32:14 amIt also applies to sockets and some larger components on mostly SMD boards... not just general through hole boards.I don't trust data sheets either, I had a set of boards made without measuring some ALPs pots. The pots were larger than the data sheet suggested as the sheet only gave the drilling data not the measurements of the overall outlineFortunately, I am only a hobby builder these days and boards are incredibly cheap from JLCPCB, so it was just a matter of waiting a few days for replacements.

author: Vini Ness
author_rank: Newbie
timestamp: May 29, 2025, 11:27:13 am
content: Thanks for all replys!!!My question is not about the trace sizeI was drawing a GBA Cartridge PCB, Using all TSSOP components and a can't go any higher than 6mil (For the data line), becouse i have to put a 100 pin CLPD, 52 Pin Flash and a 32 Pin FRAM in a 2,5cm x 5cmHigh density components and the original project uses 6milMy question is more about the relation between the trace size, the via drill/hole and the via diameter/annular ring for a consist signalIn my situation for exemple, using 6mil for the traces, what is the minimum reliable for the via drill/hole and the via diameter/annular ringMy question is the logic behind this for not creating a bottleneck for the data lineI know for exemple, that i can't run part of the signal using 12mil then shrink down to 6 mil then go back to 12mil, i will creat a bottleneck and more resistance in the 6mil spot

author: Vovk_Z
author_rank: Super Contributor
timestamp: May 30, 2025, 11:47:14 am
content: Quote from: Vini Ness on May 29, 2025, 11:27:13 amIt (all those answers about trace size) remembered me great SNL video (moment about 'You asked about a temperature')Washington's Dream - SNL

author: tooki
author_rank: Super Contributor
timestamp: May 30, 2025, 12:45:02 pm
content: Quote from: Vini Ness on May 29, 2025, 11:27:13 amSure, and that is bad… why?A 12 mil track that temporarily necks down to 6 mil will have much less total resistance than the 6 mil track. It’s not uncommon to see this done. Altium recently added the ability to do this automatically when routing.No, you probably don’t want to do it for tracks that are carrying a ton of current. But for ordinary signal lines? No problem.

author: Vini Ness
author_rank: Newbie
timestamp: May 30, 2025, 12:47:12 pm
content: Quote from: jwet on May 29, 2025, 05:07:19 amI past the Prototype level, last year i made 200 boards, using this configuration 6mil trace, 12mil via drill and 20mil annular ring all work fineBut i'm curious about the relation over via and traces6mil@100mm (MAX) can support arround 100mA ~ 200mACPLD Altera MAX3000 = -25mA to 25mA (Accordind to the datasheet, PAGE 18)Flash MX29GL128 = 60mA MAX (Accordind to the datasheet, PAGE 38)Flash 39VF215 = 20mA (Accordind to the datasheet, PAGEI think that i using too much for the drill in relation with the annular ring in relation to the traces, i don't know the relation between then

author: Vini Ness
author_rank: Newbie
timestamp: May 30, 2025, 12:50:26 pm
content: Quote from: tooki on May 30, 2025, 12:45:02 pmSorry i express myself wrongI mean using a high current you creat a bottle neck when you down to 6mill and if 6mil is fine, very low current, work point to point with 6mil

author: ejeffrey
author_rank: Super Contributor
timestamp: May 30, 2025, 01:11:28 pm
content: Even for power trace it's fine to neck down significantly for small distances. For instance a you have 500 mA in a 12 mil trace and you have to neck down to 6 mil for 50 mills to pass between some vias, that will only dissipate an extra 1 mW of heat. It won't generate a significant hot spot because the heat will be conducted into the surrounding copper.It's essentially inevitable that you effectively neck down power traces at component and connector pins, as well as vias. Don't worry about your annual rings size at this level as long as it doesn't create manufacturing problems. That's the issue with annular rings: if your manufacturer has poor drill alignment you can end up breaking the ring and causing an open circuit.

author: tooki
author_rank: Super Contributor
timestamp: May 30, 2025, 01:23:41 pm
content: Quote from: Vini Ness on May 30, 2025, 12:50:26 pmThat’s… the same thing you said before, basically?Again, having increased resistance in one short spot is better than having increased resistanceeverywhere. Obviously you’re not going to run 10A through it.For example, suppose you have a current of 1A running through a 10cm long trace using standard 35 μm copper on an outer layer. If it’s 6 mil wide, the trace will experience a temperature rise of 31C, and voltage drop of 0.357V, dissipating 0.357W.Make the same trace 12 mil wide, and your temperature rise is just under 10C, with voltage drop of 0.165V and 0.165W dissipation.If we now just neck that down from 12 to 6 mil for 3mm, then the voltage drop increases to 0.177V and 0.177W dissipation, and we’ll still be at 10C temperature rise. That’s way, way better than the 6 mil trace!

author: Vini Ness
author_rank: Newbie
timestamp: May 30, 2025, 02:01:17 pm
content: Quote from: ejeffrey on May 30, 2025, 01:11:28 pmFor the power traces, i create a VCC Plane and a GND Plane, then i route using 16mil when need and i create some thermal reliefs (i had some issues without theses)Thanks for the answer about the annular ringI manufacture in JLCPCB, the minimun size of the trace without a extra charge is 6mil, and by my calculus it's more than enoughAs for the via Drill 12mil is the minimunSo arbitrarily i use 20mil for the diameter, i don't even know if it's good or if it's make a annular ring thinner or i have to increase to 22milAbout this i have no ideia