Designing a FPGA board for a 90s SPARCstation... - Page 1
Forum section: electronics / general

author: dolbeau
author_rank: Regular Contributor
timestamp: September 19, 2020, 04:34:00 pm
content: Hello,First, a brief introduction - I'm a software guy, not a hardware designer at all, so it's likely I've bitten off more than I can chew with this. Also there's probably going to be some rookie mistakes in there, sorry. I hope I will at least learn something along the way :-)Second, a long post...I'd like to design myself a custom FPGA board, designed to fit the IEEE 1496 standard  (a.k.a SBus ), which would fit in a early 90s SPARCstation and add some capabilities to the aging relic(s) . Something like offloading the SSH handshake (SPARC v7 doesn't even have hardware integer multiplication... and even the v8 HyperSPARC struggles with modern crypto), or have some USB support, or some SDcard support (SCSI drives are old, small and no longer reliable), or a small 24-bits framebuffer to a HDMI-compatible plug (13W3, or whatever else would fit in the device... Just blinking a led from the operating system (NetBSD, in all likelihood) would already be a huge achivement as it would mean hardware and the protocol are working :-)There's plenty of FGPA cards on the market, but SBus daughtercards have a highly specific connector  and form factor. This connector has 96 pins, of which 82 are signals (plus 7 grounds, 5 +5V for up to 2A total, and +12V/-12V up to 30mA). Hence, the need for a custom board - or at the very least a custom adapter. Frequency of the clock signal on the bus is between 16.67 and 25 MHz (SPARCstation 20 are settable to 20 MHz or 25 MHz; I'd like 25 MHz but I can live with 20 MHz). Voltage is not 100% clear to me, but I'm pretty sure signals can go as high as 5V (below 0.4V is 0, above 2.4V is 1).For that last point, I figure out that some (well, 11...) TXS0108EPW  could do the job. They add delay to the signals, but the SBus book  mentions a prototype board ('SERFboard') that uses 74FCT{244,245} to buffer the signals and those add a similar delay, so I figure they shouldn't break the design timing-wise.As I know nothing about doing a FPGA card from scratch, I tried a couple of approaches:a) Reuse an existing OpenSource design and modify it to my form factor, retaining most of the functional parts of the original design so I don't have to worry about power, programming the FPGA, and so on.b) Use an existing small FPGA card with some high-density connector, and design an 'adapter board' that would just do power regulation (seems everything is 3V3 or less these days) and routing of signals.For a), I started from the ULX3S board  and removed the user-oriented stuff (ADC, user LEDs, audio, buttons, wifi, ...). I kept the 3V3 power circuitry to feed from the 5V SBus instead of USB, the FTDI stuff for programming, and the DRAM/GPDI/USB/SDcard I might want. I then had enough pins (I think...) for the SBus. Unfortunately, routing has proven to be a major issue - FreeRouting  won't open the DSN file if I keep the trace for the stuff I keep, and can't route everything on its own. The pins I can route to are not ideally placed in the design either, due to the reuse aspect. Not being used to it, I don't think routing everything by hand is a viable option.So I tried to give a go at b). I picked the Trenz TE0713  for no other reason than its size and number of pins seemed OK to me (though it's a bit expensive for my taste, and probably completely overkill for my use case). Even with the eleven TXS0108EPW in there, FreeRouting manages to route everything, and then optimize somewhat (it starts with ~140 vias and is now below 90, and the parallel signals don't look to bad to my untrained eyes). However, I only routed the power, ground and my 82+1 signals (82 from SBus and the OE from the TXS0108EPW). There's plenty more signals on those high-density connector, some with names that make me feel like they could be necessary. I did not add programming capabilities, as I wouldn't know how to do it and I thought I should be able to program the TE0713 from one of Trenz' carrier board anyway (and the moved the module to my board). I'm also missing external interfaces, as looking at the ULX3S design they don't seem obvious how to connect to the FPGA (except LEDs, so I added some LEDs :-) ).Of course even if I had the hardware working, I still would have to understand how to make the FPGA talk to the bus... but that's a task for another day (or month, or decade ;-) ).Attached below are Kicad 3D views of my current attempts.I'm not sure which hardware design makes the most sense - if any. I'm not even sure about the need or adequacy of the TXS0108EPW, or if I need something simpler/more complicated between the 5V 25 MHz signals and the FPGA. My current feeling is that the board should be doable and perhaps not even excessively complex to design (all things considered) by a pro, but might be out-of-reach for a rank amateur like myself :-(Anyway, any pointers/comments/criticisms/advices on the above or where to go to now are welcome, thanks! Official standard:https://standards.ieee.org/standard/1496-1993.html Original Sun standard:http://bitsavers.trailing-edge.com/pdf/sun/sparc/800-5922-10_SBus_Specification_B.0_Dec90.pdf Fujitsu FCN-234P096-G/Y,https://www.mouser.fr/ProductDetail/Fujitsu/FCN-234P096-G-Y?qs=uqct%252BzVq%2FBfM88%2F7KmJJ2Q== ISBN 9781461229421, beginning of the relevant chapter visible here:https://link.springer.com/chapter/10.1007%2F978-1-4612-2942-1_9https://www.ti.com/lit/ds/symlink/txs0108e.pdfhttps://github.com/emard/ulx3shttps://shop.trenz-electronic.de/en/TE0713-02-100-2C-FPGA-Module-with-Xilinx-Artix-7-XC7A100T-2FGG484C-4-x-5-cm-1-GByte-DDR3L?c=458https://freerouting.org/ This was done many times in the 90s, but it seems only scientific publications survived the end of the millennium, no trace of detailed schematics let alone software/firmware/gateware/hardware, e.g.https://www.microsemi.com/document-portal/doc_view/129952-hispeedserialdatainterface-an,https://ieeexplore.ieee.org/document/1377276,https://www.esa.informatik.tu-darmstadt.de/archive/twiki/pub/Staff/AndreasKochPublications/1993_fpl.pdf,https://www.spiedigitallibrary.org/conference-proceedings-of-spie/2914/0000/Application-of-FPGA-technology-to-performance-limitations-in-radiation-therapy/10.1117/12.255827.short?SSO=1, ...

author: impalaengineer
author_rank: Newbie
timestamp: June 11, 2022, 07:04:07 am
content: Hi,I'm interested how your project turned out.I have the same background as you and as for my project I would like to design a computer around the Motorola 68030 with the same constraints in terms of speed as your project.Thanks

author: dolbeau
author_rank: Regular Contributor
timestamp: July 06, 2022, 02:05:56 pm
content: @impalaengineer Thanks for the interest; it turned out a lot better than I originally expected :-) Thecurrent version is on GitHub.I had help from this very forum for the level-shifting, timing definition, etc. and V1.0 worked well, and eventually I did a V1.2 with better support for USB and a PMod connector to try additional stuff (a framebuffer with a low-depth VGA PMod, I2C bus with a temperature sensor).And eventually I leveraged the same FGPA board (Ztex 2.13a) in another carrier board for another bus, the NuBus as used by older Macintoshes. Theproject is also on GitHub. This is mostly targeted at supplying a framebuffer/display device. It currently supports single-resolution, all possible depth (1/2/4/8/16/32 bits), and some basic acceleration.