Understanding some GAL code... - Page 1
Forum section: electronics / projects

author: NivagSwerdna
author_rank: Super Contributor
timestamp: July 31, 2023, 02:27:34 pm
content: I'm trying to understand some code which was extracted from a .JED image for a Data I/O EPROM programmer.I ran the JED code through MAME's JEDUTIL and got this..Code:E:\mame>jedutil -view c:\Users\NivagSwerdna\Desktop\U13_V27.JED PAL16R4Inputs:2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19Outputs:13 (Combinatorial, Output feedback output, Active low)14 (Registered, Output feedback registered, Active low)15 (Registered, Output feedback registered, Active low)16 (Registered, Output feedback registered, Active low)17 (Registered, Output feedback registered, Active low)18 (Combinatorial, Output feedback output, Active low)19 (Combinatorial, Output feedback output, Active low)Equations:/o13 =o13.oe = vcc/rf14 := /i3 & /rf14 +/i4 & /rf14 +i5 & /rf14 +i6 & /rf14 +i3 & i4 & /i5 & /i6 & i9rf14.oe = OE/rf15 := /i3 & /rf15 +/i4 & /rf15 +i5 & /rf15 +i6 & /rf15 +i3 & i4 & /i5 & /i6 & /i8rf15.oe = OE/rf16 := /i3 & /rf16 +/i4 & /rf16 +i5 & /rf16 +i6 & /rf16 +i3 & i4 & /i5 & /i6 & i7rf16.oe = OE/rf17 :=rf17.oe = OE/o18 = /i2 & /rf14o18.oe = vcc/o19 = /i2 & rf14o19.oe = vccE:\mame>One thing I would like to understand is what would be the state of the outputs on start-up given from the datasheet "All flip-flops power-up to a logic LOW for predictablesystem initialization. "For those playing along at home... pin 7, 8, 9 and 12 are connected to the databus d0, d1, d2, d3. pins 3, 4, 5, and 6 are connected to the address bus A13, A14, A15 and RnW, pin 1 is a clock nV02 determining when the bus is valid.So here are my newbie questions...Why /rf14 ? Why not rf14? In fact everything on the LHS seems to be not-ed?I think the purpose is a 3 bit register that is addressed on a Write (i6=0) and A13=1, A14=1 and A15=0... i.e. to address 6xxx or 7xxx. The register is subsequent used to provide address decoding to pins 15, 16, and 17 with a CS for one of two ROMs coming from pins 18 and 19. 18 and 19 are mutually exclusive and based on 14.So at startup the "All flip-flops power-up to a logic LOW"... so that would make the flip-flop at 14 LOW? so it should be low... but /rf14? does that actually make pin14 output HI?Device is PAL16R4

author: MarkS
author_rank: Unknown
timestamp: July 31, 2023, 02:56:19 pm
content: The '/' character is the same as an overbar, i.e., active low.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: July 31, 2023, 03:44:13 pm
content: Quote from: MarkS on July 31, 2023, 02:56:19 pmI know. So will the pin be 5V or GND at startup?

author: MarkS
author_rank: Unknown
timestamp: July 31, 2023, 03:49:26 pm
content: From thedatasheet, page 5:

author: NivagSwerdna
author_rank: Super Contributor
timestamp: July 31, 2023, 03:56:08 pm
content: Because it's / ? Would it be 0 if it was not "/"? i.e. not active low?My datasheet specifies the register value being Zero... doesn't the actual pin value depend on if it is not-ed?

author: MarkS
author_rank: Unknown
timestamp: July 31, 2023, 04:00:00 pm
content: Someone else is going to have to jump in here. I can only go by the datasheet. From the POR description, I would think that the output is NOT the register value. So, if the register is 0, the output is 1 and vice versa. Truth be told, I have never messed with programable logic. I could be totally wrong, but it seems reasonable. My best advice would be to program the device and test it on a breadboard.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: July 31, 2023, 04:25:59 pm
content: Sadly I don't have a blank 16R4

author: PCB.Wiz
author_rank: Super Contributor
timestamp: July 31, 2023, 06:43:00 pm
content: Quote from: NivagSwerdna on July 31, 2023, 03:56:08 pmYes, there is a pin polarity fuse that can flip things.The active low comment reflects that fuse value.Most memories etc have ACTIVE LOW /OE and /CE/pin = (equations) is the same aspin = /(equations)If you have PLD SW like Atmel’s WinCUPL you can edit the report so it compiles, and then simulate the pld.That can create a .JED file with fuse and test vectors, the programmer runs to test operation after programming.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 01, 2023, 10:37:11 am
content: I don't speak CUPL. But I could give it a try.It looks like the /pin term is used where the inverter on the output can be used to assist in the reduction of terms. So it looks like when that has happened the inverter is in circuit.But looking at the datasheet... (see attached)You cannot get out of the flip flop without being inverted at the transceiver buffer.So... logically if the flip flop assumes LO at start-up then the output would have to be HI?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 01, 2023, 04:12:39 pm
content: Quote from: NivagSwerdna on August 01, 2023, 10:37:11 amThey draw these using some default, but the polarity fuse can flip as needed.Seehttps://blog.frankdecaire.com/2017/02/25/programming-the-gal22v10/Do you need to change parts, or just copy what you have, or just extract eqns for servicing ?You can also usually also edit test vectors directly inside programmer sw, so a few lines is enough for simple code like this.Just enter 1,0,H,L,Z,C,K,N for each pin.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 01, 2023, 06:55:31 pm
content: So I tried a crash course in WinCPL...Code:Name DECODE;PartNo 00;Date 01/08/2023 ;Revision 01 ;Designer Engineer ;Company ACME ;Assembly None ;Location ;Device g16v8 ;/* *************** INPUT PINS *********************/PIN 1 = CLK ; /* */PIN 2 = i2 ; /* *//* *************** OUTPUT PINS *********************/PIN 14 = !O1 ; /* */O1.D = i2;Admittedly this is a different part but the principle may the same...And I ran a simulation...So here Pin 14 is !O1The simulation shows that the Pin 14 will be 0V until a value has been CLKed into O1.So now I'm not sure again... I would have expected the opposite!

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 01, 2023, 07:04:47 pm
content: Reading the GAL16V8 datasheet is even less understandable... The simulation shows 0V...

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 01, 2023, 10:24:40 pm
content: Quote from: NivagSwerdna on August 01, 2023, 06:55:31 pmYou also need care that a NOT can simulate as positive but invert at the pin. The O1 here is FF.Q upstream of the pin, and the pin-flip nature means the pin is not the sim waveformSometimes it's best to try an actual deviceMy recollection is that a leading NOT 'ripples thru to the fuse', so I tried thisCode:/* *************** OUTPUT PINS *********************/PIN 14 = !O1 ; /* */PIN 15 = ChkPolA ; /* */PIN 16 = ChkPolB ; /* */O1.D = i2;ChkPolA.D = !i2;!ChkPolB.D = !i2;and that report in the .DOC file asCode:Pin #16 02051 Pol x 02123 Ac1 xPin #15 02052 Pol - 02124 Ac1 xPin #14 02053 Pol x 02125 Ac1 xand my test cases do have opposite polarity fuses, which is a good sign. The difference here will be how they POR.but a different part of the same DOC file reports thisCode:Pin Variable Pterms Max MinPol Name Ext Pin Type Used Pterms Level--- -------- --- --- ---- ------ ------ -----CLK 1 V - - -ChkPolA d 15 X 1 8 1ChkPolB d 16 X 1 8 1! O1 d 14 X 1 8 1i2 2 V - - -not the same pol pattern as the fuse reports ?Running a sim, gives a POR indication that not all POR the same, but this follows the Pol column not the fuse map infoCode:================CChhkkPPC ooLi OllK2 1AB================Power on checks0001: 00 LHH0002: C0 LHL0003: C0 LHL0004: C1 HLH0005: C1 HLHSim is happy with either !ChkPolB, or ChkPolB, but which one matches the physical pin behaviour ?When you run a SIM, the JED file has the test vectors included, so a programmer can check a real device after program.At this point, trying physical device is a good idea.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 02, 2023, 08:28:28 am
content: Thanks for your interest.Sadly I don't think I'm going to be able to get near a real device. This is 16R4 andI cannot see any NOS of thosejust found some NOS on EBAY UK but I don't have a burner that will do them.FYII'm trying to understand the behaviour of U13 on a Data I/O 701-2126 memory board (from a UniPak2B) but this is something I don't physical have and are pretty unobtainium... hence I'm trying to mod my 702-1650 board to behave as if it was a 701-2126. It's possible that the power on state doesn't matter (because the register is written before being accessed) but I'm trying to narrow down the variables as testing will be hard.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 02, 2023, 08:50:37 am
content: Quote from: NivagSwerdna on August 02, 2023, 08:28:28 amOperationally, the power-up state is less important, it's mainly to ensure power-up is also safe until first write.You can map a 16R4 design onto a 16V8, as you already see winCUPL do. Programmers for ATF16V8 should be more common.Some programmers can take 16R4 fuses and map onto 16V8 - it says something likeDevice name:ATF16V8BQLas16R4

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 05, 2023, 01:28:15 pm
content: So I got my hands on a real device...It doesn't seem to behave exactly how I had hoped...I would expect the registered outputs 14, 15, 16, 17 to all be high because they are behind an inverting buffer and their registers would be expected to be LO... but hey... we have a non-beliverer... pin 15

author: Stray Electron
author_rank: Super Contributor
timestamp: August 05, 2023, 02:50:19 pm
content: Quote from: NivagSwerdna on August 02, 2023, 08:28:28 amWouldn't the Data I/O model 28 burn them with the right plug in module? I think one of the UniPak plug ins will handle those PALs. I bought a bunch of that stuff years ago with the plan to burn some PALs but I never got around to it. Years ago I had ahoardof Data I/O programmers, manuals, plugins and other stuff but never used much of it and I don't know where it is now.IIRC Heathkit/Zenith used a lot of those simple PALs in their H-100/Z-100 computers and the manuals for the Heathkit version included all of the logic equations for the PALs. Zenith made the same computer but it came already assembled but the Heathkit versions were kits so that gave you detailed assembly manuals with their equipment.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 05, 2023, 07:58:33 pm
content: Wot no Logicpak. I have a UniPak only.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 06, 2023, 06:06:50 am
content: Quote from: NivagSwerdna on August 05, 2023, 01:28:15 pmYes, one seems out of step.How did you obtain those plots ?Is that test vectors running on a real programmed part ?Maybe a CLK applied at Power-up ?What does a part do, placed in a decoupled DIP socket, and CLK tied to GND, then power-up ?

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 06, 2023, 02:44:16 pm
content: My test rig is a homebrew chip tester that allows me to arbitrarily twiddle bits.So I bent up in 1 and connected it with a bodge wire to pin 10 GND14, 15 LO, 16 and 17 HI!Then I twiddled the state of 13 to be HI14, 15, 16, 17 HIpin 13 should have no impact; it's not in the equations!Then I made 12 also HI...14, 15, 16, 17 HIVery weird. This would be much easier if you could imbed inline images in posts

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 07, 2023, 09:06:33 am
content: I don't want to give up just yet... so thinking about why pin 13 is involved... On the schematic pin 13 appears to be provided with a signal but the equations I got from JEDUTIL didn't mention pin 13...So looking into the JED file and datasheet...I never tried to read one of these before... I assume that each line of 32 bits reflects a fuse in this diagram so 48 actually is offset 1536In the JED file...L1536 11111111111111111111111111111111*L1568 11111111111111111111111111111111*L1600 00000000000000000000000000000000*L1632 00000000000000000000000000000000*L1664 00000000000000000000000000000000*L1696 00000000000000000000000000000000*L1728 00000000000000000000000000000000*L1760 00000000000000000000000000000000*L1792 00000000000000000000000000000000*L1824 00000000000000000000000000000000*L1856 00000000000000000000000000000000*L1888 00000000000000000000000000000000*L1920 00000000000000000000000000000000*L1952 00000000000000000000000000000000*L1984 00000000000000000000000000000000*L2016 00000000000000000000000000000000*At 1536 there are lots of 1's... and also the next row and then 0's to the end of the file.If the intersection of every row with the 32 lines is a fuse does that mean don't burn fuses on line 48 and 49 and burn them all below? Wouldn't that mean all the vertical lines get connected?

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 07, 2023, 10:16:37 am
content: So looking at the JED file... I see no ZEROs in column 26 or 27... so I think this pin 13 is unused and should have no effect.. but it does.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 07, 2023, 08:26:24 pm
content: Certainly strange.Are you driving all pins with clean CMOS edges ?I have seen CPLD’s get disturbed by touched floating pins with zero enabled logic.My conclusion was the pin buffer was oscillating on the slow edges.