How reliable data captured by a Logic analyzer?? - Page 1
Forum section: electronics / beginners

author: rakeshm55
author_rank: Regular Contributor
timestamp: July 15, 2014, 04:28:53 am
content: Hi,I have a basic question to ask....How reliable is the data captured in Logic analyzer??.... Can it be used for jitter analysis (aim is to capture departure of clock from 50% duty cycle) I have used oscilloscopes for this purpose but can logic analyzer be used??.... I want to know how the analyzer resolves the metastable issues that may arise due to digital sampling... One of my design uses a 100Mhz clock and has logic analyzer with internal clock frequency set as 800Mhz.....Same analyzer can even go to 40ps sampling ..... Even with this resolution do engineers use logic analyzer to analyze jitter.In case of FPGA designs What advantage does logic analyzer offer over chipscope and oscilloscopes???usually in FPGA designs we use Chipscope to capture internal signals For what purpose do i use logic analyzer in FPGA ... i have seen colleagues capturing internal signals using logic analyzer by routing the signals to external pins.... is this advisable?? wont the nature of the signal be lost when routed to external pins..... My understanding was to use logic analyzer to capture board level signals .....

author: Rerouter
author_rank: Super Contributor
timestamp: July 15, 2014, 10:42:23 am
content: Sounds like you are concerned with aliasing of samples, this is where statistics can help, get enough samples and you can remove the aliasing from the results, (I recently was measuring a frequency sources drift, and had the reading dancing between 2 bits of resolution for the entire measurement (was working with what i had on hand), recorded on average 20,000 samples and calculated the min,max,average,standard deviation,etc at a much higher effective resolution, )As for routing out pins to capture the signal, if they are concerned about the phase delay between 2 pins, then differential routing solves this, as for "the nature of the signal" depends on how much high speed layout practices where paid attention to, as it is very possible to bring out a test point where the signal is properly terminated etc, and remain looking almost exactly the same as the original (capacitive loading will slow the edges a little) with the same jitter and all, just possibly a little rounder eye diagram,

author: Bassman59
author_rank: Super Contributor
timestamp: July 15, 2014, 07:21:30 pm
content: Quote from: rakeshm55 on July 15, 2014, 04:28:53 amFor starters, Xilinx ChipScopeisa logic analyzer.Now, a logic analyzer can work in basically two modes (folks familiar with the HP 16xx and 165xx analyzers will recognize this nomenclature).One is "state" mode, in which the sampling clock is an inputtothe analyzer, and is assumed to be the same clock which drives the logic you're sampling. (This is the ChipScope model.) Signals being captured must meet setup and hold times around the sampling clock at the analyzer's input registers; read the analyzer documentation for those numbers. In the case of ChipScope, the usual Xilinx timing analysis will tell you whether you meet timing or not. Obviously the clock input to the analyzer must run at or less than the analyzer's maximum input frequency.The other is "timing" mode, where the analyzer generates the sampling clock, and all of the signal inputs to the analyzer are considered to be asynchronous to that clock. This has several implications. One is that the sampling frequency needs to be much higher than the maximum toggle rate of the signals, otherwise you get the usual aliasing and uncertainty. Also, since the inputs are asynchronous to the analyzer there's the possibility of metastability (you can be sure that the analyzer has proper synchronizers) and there's still the uncertainty in the sample position. So this means that you can't use a logic analyzer to measure jitter.QuoteWe had to do that before ChipScope was invented, and if you don't spend the money for a ChipScope license, there's not much else you can do. And seriously, ChipScope is pretty great and worth the cost.QuoteRouting internal FPGA signals to pins can change the timing, although probably not too significantly. Certainly the analyzer is used to capture board-level signals, but most designs with FPGAs simply don't have that many board-level signals to begin with. It's not like you have a wirewrapped board full of MSI TTL chips to which you can connect probes. When something doesn't work on one of my boards, the first thing I reach for is the oscilloscope; usually with four channels I can figure out what's not working as expected. I rarely use my HP logic analyzer any more, although I use ChipScope frequently.

author: hamster_nz
author_rank: Super Contributor
timestamp: July 16, 2014, 02:57:31 am
content: If you haven't got Chipscope and you want something with none of the cost and none of the features you could try my cheapscope project -http://hamsterworks.co.nz/mediawiki/index.php/CheapScopeI am the first to admit that it is very limited and a pain to add it to your design, but it will most likely take you much longer to debug the design with zero visibility of what is going on inside of the FPGA.

author: free_electron
author_rank: Super Contributor
timestamp: July 16, 2014, 06:14:08 am
content: Real logic analyser (i'm talking like the 16900 style machines from agilent) with the appropriate blades like a 16760 or 16910 can perform jitter analysis and eye diagrams. The way they do this is by burst firing in interleave mode. You need the probe adapter that combines 34 or 68 channels into 12.What the do is first deskew their own logic by altering the sampling points. Next they set up for interleaving the channels. If the blade can do 800MHz and it uses 4 combined channels it can resolve up to 3.2 Ghz. If you combine more channels (theblades need to support that) you can get picoscond resolution.The way it works is they first align all channels , including a clock channel the same. Then they skewAll channels around the clock in a staggered pattern. If an event comes the clock triggers the analyser but the signals have not reached the samples yet due to the skew. Burst firing can then very accurately trap the exact edge occurrence.It is a simple technique. Even the oldest blades in the 167xx series hit 4Ghz that way.