Help wanted, any CMOS Amplifier design experts on here? - Page 1
Forum section: electronics / projects

author: tinker65
author_rank: Contributor
timestamp: December 17, 2019, 08:07:40 pm
content: Hi guys,Here is a photodiode amplifier used to charge an integration capacitor via analog switch (not shown). Could anyone help me to understand how this amplifier works? What are the criteria for choosing correct transistors to make it work?Right hand side looks more or less common but it gets weirder as you go left. There is that M3 transistor in the middle, so the right hand side does not have inputs where I would expect them. Vb2 seem to be a photodiode bias, yet why the photodiode is also connected to S/D of M3 and M6.I believe the schematics is correct, but there is a possibility it might not have been traced 100% correctly. Any input is highly appreciated!

author: Wimberleytech
author_rank: Super Contributor
timestamp: December 17, 2019, 08:42:26 pm
content: I redrew your circuit in a way that might make it easier to understand.M1 sets up a bias current that drives the gate of M3 high until such time the feedback path via M2 increases M2 drain current to the point where it equals the bias current coming from M1.The remaining transistors are in a classic turnaround cascode structure. The diode modulates the current at the source of M3 which gets mirrored to the output via the Pch turnaround.The delta current generated by the diode gets multiplied by the output resistance which is VERY high, generating an output voltage.This is a high-gain open-loop amplifier. Is there any additional circuitry that you did not trace?

author: Wimberleytech
author_rank: Super Contributor
timestamp: December 17, 2019, 09:01:36 pm
content: Here is the simlulation schematic.The circuit behaves fairly nicely in the simulation with perfectly matched transistors. Real world is different, however.I sized all nch transistors 20u/1u and all pch transistors 40u/1u

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 17, 2019, 09:14:13 pm
content: Consider M6/7. These are biased with fixed gate voltage, thus they form a cascode current sink. The current is quite reasonably constant, until drain voltage drops so low that saturation is reached. (Note I'm referring to voltage saturation here.)If there were no diode attached, that would mean M3 has no transconductance, i.e., its drain current is insensitive to gate voltage, except at low gate voltages where the current sink saturates.M4/5/8/9 are a cascode current mirror, so the output gets whatever current M3 passes, inverted (and subtracted from the constant bias that M10/11 draw).So the key seems to be the diode current tapping into M3 source.We can rearrange the circuit, thinking of M3 and the diode acting as a differential pair, i.e. a current-steering function. The diode current adds to I(M6), though, not actually steering (diverting?) current but increasing it; it would be as if we could drive a diff pair with an imaginary input that causes it to deliver more current than it is biased to.So the interpretation changes again, and M3 is simply a biased cascode: it takes the diode current, plus a bias current, and communicates it to the mirror.What is M1-3 doing?Making the cascode more stable, i.e. reducing the change in diode voltage. M2 is biased around one Vgs (about Vb4, give or take Vb2 and relative geometry), so M3's source must be at this potential, and M3's gate must be at about 2*Vgs. (Evidently Vdd > 3*Vgs is required here.)The impedance of the gain node (M1/2 drain) may not be very high (as suggested by the need for cascoded sources elsewhere in the circuit), and without device characteristics, I can't calculate what this will be; but in any case, the gain acts to reduce M3's source impedance (~ 1/gm) by the gain ratio. I would guess at DC, the diode sees a load impedance of a few ohms, or tens of ohms (maybe hundreds if this is small transistors in the middle of a chip?). This keeps the photogain stable, but more important is high frequency response.At high frequencies, capacitances (especially Cgs and Cgd) dominate, and the loop gain (of M1-3) is reduced; at high frequencies, also, the diode's junction capacitance has considerable admittance, shunting its photocurrent. This will shelve around where M2's gain drops by, say, half or more.The slight bias also helps reduce the diode's capacitance by reverse biasing it. Though this isn't a huge difference, being maybe a volt. (It's best to run diodes near their reverse bias rating, to take full advantage of the C(V) curve. Certain diodes can be driven even further, increasing gain exponentially -- avalanche photodiodes.) But it's still better than, say, a voltage amplifier sensing an unbiased diode (i.e., photovoltaic mode).Another advantage for reverse bias, even if it's not reducing capacitance much, is it sweeps charges out of the junction faster than recombination alone does.Quote from: Wimberleytech on December 17, 2019, 08:42:26 pmQuote from: tinker65 on December 17, 2019, 08:07:40 pmYeah, this -- since the output is simply a direct complement of the input current (a current follower, as it were: whereas a voltage follower has ~infinite input and ~0 output impedance, this has ~0 input and ~infinite output impedance), it would be an excellent pairing for anything current-mode, like an integration capacitor, or a voltage follower and feedback network.We should probably assume that the load is a modest impedance centered around mid-supply, so that the outputs aren't saturating and the amplifier amplifies, so in the absence of anything else, assuming a feedback network would also be fair.Incidentally, it's a current follower if the mirror has equal transistors, but some gain can be had here by making the output side a bit larger. I'm not sure by what ratio is acceptable, which is going to depend on bandwidth of course; I would guess 10-50x would be fine.Tim

author: tinker65
author_rank: Contributor
timestamp: December 17, 2019, 11:13:39 pm
content: Wow, you guys really rock! I am more than impressed! Thanks a bunch!Wimberleytech, do you mind me asking what software have you used for the simulation? You got it drawn and simulated in less time than took me to type this messageI can get the actual dimensions, but don't know any other parameters like oxide thickness or Vth. M1-M3 are all different sizes, M4-M11 are all the same. Actually M8 is made out of multiple paralleled transistors, each identical to M4, same for M9-M11. So T3sl4co1l probably got it right, output current must be multiple of the input current. All of the transistors are fairly large, with a gate length several times that of the transistors used for digital logic. Vdd is 5V.I have a bias circuit too, will try to arrange it in a more meaningful way and post later. PD is a part of the same chip, not an external component. Its fairly large, so must have a decent parasitic capacitance to it.There is no feedback from what I can tell. Output goes to one of the analog switches. 4 analog switches form an H bridge with the capacitor in the middle, so capacitor can be charged by this amplifier, discharged, or voltage across it can be read. In reality it probably works the other way around: capacitor is initially precharged to a certain voltage and then photocurrent discharges it.

author: Wimberleytech
author_rank: Super Contributor
timestamp: December 18, 2019, 12:11:11 am
content: Quote from: tinker65 on December 17, 2019, 11:13:39 pmBorn and raised a cmos analog ic designerQuoteLTSpice It is the simulator most everyone in the forum uses.QuoteWell, you won't be able to get this information from visual inspection. Since VDD is 5V, the Vth is prolly 0.5 to 0.8 volts...close enough. When I simulated it, I used some model parameters I had from a 0.35um process node. Not critical at any rate.QuoteYes, this is standard analog practice for matching.QuoteYeah, I just built a simple bias string to get it running.QuoteAhhhhhh, viva la difference! No feedback required for that scheme of operation.What, may I ask, is your project...goal? Sounds like you are reverse-engineering a chip, n'cest pas?

author: tinker65
author_rank: Contributor
timestamp: December 18, 2019, 05:17:55 am
content: Quote from: Wimberleytech on December 18, 2019, 12:11:11 amYou can probably tell that analog is not my strongest point. I am mostly digital guy, embedded software etc.Quote from: Wimberleytech on December 18, 2019, 12:11:11 amI guess I can try probing one of the transistors to get some curves. Process node appears to be 0.8umQuote from: Wimberleytech on December 18, 2019, 12:11:11 amCan you tell if increasing the photo current causes the output voltage to go up or down? That should tell us if it charges or discharges the capacitor.Quote from: Wimberleytech on December 18, 2019, 12:11:11 amRE, understand and improve. Application and origin will probably require an NDAAnd here is the bias circuit. Does it make sense?

author: Wimberleytech
author_rank: Super Contributor
timestamp: December 18, 2019, 01:09:30 pm
content: M6 needs a current path to ground! Without it, the circuit is dead. I will take a deeper look into the details.If you PM me, I will remove the veil, and maybe I can help. Not adverse to an NDA.

author: Wimberleytech
author_rank: Super Contributor
timestamp: December 18, 2019, 01:13:01 pm
content: Here is my LTspice file. Add your bias circuit and modify all of the device sizes to the ones you have measured and post it. I have an 0.8um model that I can use to simulate.QuoteDiode current and output voltage are in phase.