Discrete Memristor Chips from Bio Inspired Technologies. Any in the wild yet? - Page 1
Forum section: electronics / general

author: richfiles
author_rank: Regular Contributor
timestamp: May 27, 2015, 09:20:35 pm
content: Just curious if anyone has managed to snag one of the new Bio Inspired Technologies (Idaho, USA company) discrete memristor chips yet? They apparently make three versions, as far as I can tell. One is a die only version, with 80 primary memristors, 16 secondary memristors, and an approximate 75% yield. For prepackaged chip versions, they offer a 16-pin DIP with 8 memristors, and a 44-pin PLCC with 20 memristors.The things are NOT cheap... I got a quote, and the message had no indications or requests that the quote should be kept private, so I'll share. I was quoted $240 for the DIP, and $750 for the PLCC. They do offer a 10% academic discount. It's alotof cash for an experimental part, but a chance to own one of the first parts of it's kind, and experiment with a new technology.The specs are listed below:Pre-programming resistance--Greater than 50 megaOhmsWrite voltage--300 - 400 milliVoltsPost-write resistance--Less than 500 OhmsErase voltage--(-300) - (-400) milliVoltsPost-erase resistance--5 megaOhmsWrite speed--less than 5 nanosecondsMaximum cycles--Greater than 2K**The website states greater than 10 million, and the manual states greater than 2K, with a note that the number of achievable cycles is dependent on the "roughness" of the programming parameters, and that carefully following the specs of the operating parameters can "result in devices that last nearly indefinitely."The programming cycle. When freshly manufactured, the memristors have not yet developed preferential dendrite programming pathways. As a result, initial resistance measurements should indicate a very high resistance (nearly open).The read cycle. A simple resistance measurement should be done with a voltage of less than 50mV. Conventional multi-meters or unverified equipment should not be used because of the often very large open circuit voltages or unconstrained current parameters. It is important that the sample voltage be kept minimal to prevent the measurements from changing the state of the device. If the sample voltages are greater than 50mV, the device will begin to write while being sampled.The write cycle. The write cycle typically involves simply sweeping the device to a value above the expected switching threshold, or approximately 400mV for the Neuro-Bit devices. A typical sweep for these devices would be from zero to one volt.During DC sweeps, setting a current compliance for your measurement is extremely important and critical to preserving functioning devices.While sweeping the devices above the write threshold is important to perform a write, the current compliance you set will determine both the final resistance value of the memristor and how stable the device will be at that state. Reasonable current compliance values will range between 100nA and 30uA. When experimenting with the Neuro-Bit Memristors, it is best to begin with very conservative values until you are comfortable with the performance.Note regarding writes: The reason for this is that the devices form a conductive dendrite (or several) during the programming process. The dendrite effectively makes a connection between the top electrode and bottom electrode. The conductivity of the dendrites is set by the current allowed to pass through the device while being programmed. If the current is left unconstrained, the dendrites will effectively form a short circuit between the electrodes. This will make it nearly impossible to reverse the process during the erase cycle and the device will be “stuck”. It may be possible to reverse this through repeated erase sweeps, but the process is difficult to implement and not always effective.The erase cycle. The erase cycle will reverse the effects of the write cycle, resetting the device back to a high resistance state. Since it is important to allow the device to consume the necessary current to reverse the dendrite growth, a current compliance is not normally required. A typical sweep would be from zero the negative one volt, setting the current compliance to between 1mV and 10mV as a safety precaution. After the erase step, the resistance of the device should be significantly less than the as-deposited values, and the device is now considered “conditioned”. Occasionally, the erase cycle may be repeated to achieve the desired resistance values if the first cycle does not erase effectively. There are no ill-effects from repeating the erase cycle.These are also extraordinarily ESD sensitive. It would appear they are a purely experimental part, and I have seen no indication that they have any form of clamping or ESD protection circuitry. At ALL. They are a LITERAL discrete memristor on silicon, tied directly to the external pin leads, as far as I have read.Bio Inspired Website. Literally bio inspired. They have pictures of butterflies and stuff!http://www.bioinspired.netDatasheet/manualhttp://nebula.wsimg.com/6dba75009009af7a59036365876b3f66?AccessKeyId=64577CB1C10F8DCEF8A3&disposition=0&alloworigin=1

author: Tinkerer
author_rank: Frequent Contributor
timestamp: May 29, 2015, 12:26:19 am
content: QuoteWell it is the first time in history these things are commercially available. I am excited to see what people manage to come up with. I am sure at somepoint someone will throw a bunch together on a large board and simulate a primitive brain if possible.

author: LabSpokane
author_rank: Super Contributor
timestamp: May 29, 2015, 04:47:21 am
content: I'm fuzzy as to what a memristor can do that couldn't be simulated digitally. I get the whole analog value storage and what appears to be a dramatic reduction in power consumption. And the write speed appears impressive. But I'm not sure what having one of these ICs in hand does that couldn't be done DRAM. Unless the dendrites actually form relational networks among the memristors...then that's totally different. But I'm not getting that from the documentation.Any insight?

author: richfiles
author_rank: Regular Contributor
timestamp: May 29, 2015, 11:38:02 am
content: It's about eventual density. It's presumable, that these memristors will someday be at least as small as individual transistors on silicon. Try and emulate that functionality in the silicon space of one transistor. Remember, these are VERY new. They will come down in cost, and they will shrink, in time. The first LED cost $200 EACH, back in the 1960s. It's the same story here. It costs as much as an Intel CPU because the parts are large, cumbersome, have extra redundancy to account for yield losses, and each part is individually probed, conditioned, and tested, and then bonded based on the yield results... It's an expensive process. It's also very, very new. People look at these and often consider the digital switching aspect, but they have an analog range that can be tapped with a very low current compliance. You can use these to create very intriguing parts like neurons, that have their "weight" shift with subsequent firings, and not have to emulate that characteristic digitally. There are more abstract applications where the analog features are a benefit. Pattern recognition is just one area where these parts could excel. They bring to the table the degree of fuzzy processing that neurons excel at, and they do it without emulation, using efficient discrete hardware, with switching compliance currents measuring in the nano and micro amp range, at under a volt.There is also the fact that they arenon volatile, storing their analog state indefinitely, without power. Even flash loses it's data integrity after a certain period of time. These won't lose their data. Emulate that digitally, without requiring a power source.Further communication with the company reveals nothing surprising. They roll custom silicon, and their biggest early application has been ASICs for the US DoD. They are also working on developing a memristor based FPGA like device. DoD work is nothing new... The government is typically first to fund new tech, and to push it's limits. The same was true with the early transistors and early integrated circuits as well.Memory is the "easiest" solution. You get fast, one device memory cells with great speed, retention, and non-volatility. A single element, that will someday presumably be no larger than an on die transistor, able to hold a state, without power, with the density of flash and the speed of DRAM. The ability to perform logic, at the active memory, that also doubles as storage... That's a huge deal.One proposed concept, would have a massive FPGA like memristor matrix that can reconfigure it's logic, so you essentially write a free area of your unified working/storage memory to perform a pipelined logic function, that is non volatile (by nature of memristors), that simply feeds your initial memory down a pipeline, to be calculated and stored at the end of the pipeline. Shift data into the pipeline and shift results out, and just watch a massively parallel task complete as memory is read on one side and filled up on the other. You could feed the results into another pipeline, configured for another processing task. Make a loop in the memory. Feed some data back forward, make a hardware video encoder that places the logic right in the memory area containing the video. Maybe you wanna play a game. Your memory could be reconfigured into a massively parallel shader pipeline. Why send data over PCIe lanes to a GPU. Just configure the GPU logic right in the unified system memory. That's the kind of long term potential that we may see with these memristors.No drive fetches.No sending or reading data out over busses to external storage or devices.No fetching from RAM into the CPU registers.No sending the results back to RAM.You just create the logic block you want, right IN the memory space, and start shifting data through it. It's no longer necessary to even rely on general purpose functions... You can create ASIC like hardware logic functions, as needed, thanks to the FPGA like potential of such a future system configuration. Look up crossbar latches for more info on this concept.Hewlett Packard gets it... even if they don't get branding...*cough* Keysight *cough*... They first developed the memristor in 2007ish, over 10 years of prior work led to its development, and now, after another 8 years of directly developing the tech, they've decided to gamble most of their chips on the tech. As in, reportedly, 75% of their computer division's R&D is focused on this new project. I don't know if they plan to use the in situ logic elements yet (that's a tech that might still need time to develop), but they are already proposing an all new concept for a next generation server that uses memristors for unified storage and system memory. They simply refer to it as "The Machine". They claim that it will eliminate the waste of seeking data over busses, from drives, and they also claim up to 90% increases in efficiency, due to the fact that memristors only require current flow to change, not to hold state. It's one of the big benefits of non volatile active processing elements. You only need power to change states or to read them.Basically, HP realized that 5% margins on rebadged intel hardware was not a worthwhile future for their server business. They decided that they would devote their resources into creating a technology that had the potential to completely displace the competition. Stop and consider, if you were a data center, and HP offered you a machine that used up to 90% less energy, and was orders of magnitude faster at accessing and delivering stored data to customers... Would you be interested? That's HP's gamble. If they succeed, they escape intel's hold on the market, and return to being the market leader, with an innovator new tech. If they fail... They dumped 75% of their R&D for however many years they develop this.I personally wish them luck. Those claims can't be emulated. It takes new hardware to pull that off.