Noob: DAC linearity in the DP832 - Page 1
Forum section: electronics / testgear

author: LaurentR
author_rank: Frequent Contributor
timestamp: January 08, 2015, 08:38:30 pm
content: Hi all,since I got my DP832, I noticed the output was always a few mV off, as measured by both an external DMM and the internal ADC. That's still in spec but I got curious so I decided to script a sweep on Ch1 Volts to see the big picture.The setup ran at cold ambient (~15C), so somewhat out of calibration spec but the overall shape of the curve is still similar to what I saw at higher ambient.I don't have much experience with DAC linearity, but the result still surprised me. Ignoring static offset, there is still about 8mV of range in variation (in spec for the DP832), but I can't explain the abrupt changes, especially around 10V. I assume the plot is a combination of calibration curve-fitting and actual DAC response...BTW, the DP832 internal ADC agreed in the general shape of the curve.

author: wiss
author_rank: Frequent Contributor
timestamp: January 08, 2015, 10:59:22 pm
content: But, you can only set it to even 10 or 1 mV, right?

author: TopLoser
author_rank: Unknown
timestamp: January 08, 2015, 11:27:12 pm
content: Sounds like it's related to your DMM changing ranges at 10v?

author: LaurentR
author_rank: Frequent Contributor
timestamp: January 08, 2015, 11:33:13 pm
content: Quote from: wiss on January 08, 2015, 10:59:22 pmRight. This particular run is stepping through every even 10mV value from 0 to 30V. That's already 3000 steps... I am planning to try a smaller window with 1mV steps (using the high res option), but first I was wondering if anybody could explain what is going on with this one.Zooming on this one, the vertical noise already looks like the DAC has somewhere between 1/4 and 1/2 mV steps (which would be more or less consistent with a 16 or 17b range over 30V).

author: LaurentR
author_rank: Frequent Contributor
timestamp: January 08, 2015, 11:47:59 pm
content: Quote from: TopLoser on January 08, 2015, 11:27:12 pmI thought it might be the case and ran some sanity checks around this, but I'll have another more serious look.OTOH, the huge peak and dip happen before 10V and the DMM stays in the 10V range until 12V (I am stepping up).And the internal ADC of the DP832 agrees with the curve (I am not sure what the precision on the ADC is - accuracy is something like .01% + 5mV). There is some slow drift compared to the DMM across the range, but it definitely sees the same relative peaks and dips.

author: wiss
author_rank: Frequent Contributor
timestamp: January 09, 2015, 12:10:51 am
content: What DMM is it?

author: LaurentR
author_rank: Frequent Contributor
timestamp: January 09, 2015, 01:12:53 am
content: Quote from: wiss on January 09, 2015, 12:10:51 am34461A. This plot is 0.5sec delay in SW between a status read of the DP832 after the voltage change and the DMM READ? trigger and 10PLC on the DMM (supposed to get a 10uV of resolution on the 10V range). I tried various other parameters on subsets (like 2sec and 100PLC) and it's all very similar.

author: LaurentR
author_rank: Frequent Contributor
timestamp: January 10, 2015, 03:55:50 pm
content: Did a full 1mV sweep. Nothing groundbreaking on the weird peaks and dips. However, did confirm that the DAC output precision is ~520uV (see histogram), which is consistent with a 16b value over ~34V.

author: thmjpr
author_rank: Regular Contributor
timestamp: January 13, 2015, 06:40:45 am
content: Here is some quick data using 0.1V steps 1s delay and only the internal ADC to read back. 0.5s delay had some data loss.Some spot checks agree that the ADC readings are at least relatively accurate. Might try with proper DMM readback in future.I manually calibrated the unit ~6months ago in an attempt to remove the offset. Its a bit worse now it seems, but I did not record original data. I wonder if the DAC reference is drifting internally (ADR381?).Looking at various DAC cal points: 8.4, 9.8, 12.1 for example, they don't seem to correspond to jump locations. I would assume rigol is using a basic linear interpolation between the cal points.To improve this they potentially could single step through each voltage value to build an offset table (~60kB). Or employ some digital feedback to adjust DAC up/down until the ADC readback matches set voltage.

author: LaurentR
author_rank: Frequent Contributor
timestamp: January 13, 2015, 06:37:22 pm
content: Thanks!I ran a home-written automated calibration based on the calibration DIY in the DP832 threadhttps://www.eevblog.com/forum/testgear/rigol-dp832-firmware-updates-and-bug-list/180/and as a result:* The DAC behavior hasn't really changed. It looks a lot like yours and my old one. Strangely, even after calibration, the error is not centered on 0 at all. I get very little undershoot (going to ~ -1mV) and mostly overshoot (to ~ +9mV).* During the calibration, the DAC is way off (by about 500mV) when stepping through values.* The ADC does pretty nicely after calibration. With ambient matching my calibration ambient, the ADC goes from about -0mV to +1mV, well within specs. There is noticeable ambient temperature drift.* During calibration, it seems pretty close, so there is not much adjustment due to calibration.

author: smgvbest
author_rank: Unknown
timestamp: January 14, 2015, 04:02:55 am
content: @LaurentRWould you be willing to share your calibration script?

author: LaurentR
author_rank: Frequent Contributor
timestamp: January 14, 2015, 04:17:21 am
content: Quote from: smgvbest on January 14, 2015, 04:02:55 amAbsolutely. I am cleaning it up and will post it in the DP832 thread in the next few days. It's a straight port of ted572's instructions (from TooOldForThis's work).