Atmel ATF150x CPLD and WinCUPL - Page 1
Forum section: electronics / general

author: deanclaxton
author_rank: Regular Contributor
timestamp: June 18, 2020, 12:09:54 am
content: Hi all,I'm working on a project (my first CPLD project) using an Atmel/Microchip ATF1504 5V part (chosen as it is still an active part that is readily available), and am struggling a little with the CUPL language. Unfortunately there isn't a free toolchain for VHDL or Verilog (I havent used them either(!) but there are more examples on the net).The issue I'm currently having is around pin I/O. I have some output pins that are technically I/O pins on the CPLD (I will only use them as outputs), and I'm setting one high, and the other low using these statements :PROPERTY ATMEL {pin_keep=off};PIN 29 = !OE ; /* define OE pin active low */PIN 27 = !WE ; /* define WE pin active low */OE = 'b'0; /*enable the output */WE = 'b'1; /* disable write */I have the pinkeep function turned off (that was messing things up elsewhere earlier on with my address bus pin inputs).When I program the device and check these pins, they are the opposite of what I'm expecting. I tried setting OE to 1, and WE to 0 (thought I might have been confusing myself with the active low pin definitions!), but there was no change in the output.I must be missing something - perhaps something around the output enable for these pins?Does anyone have any simple examples, or can otherwise shed some light on what may be happening? I'd love to find some good documentation for these devices - I must be looking in the wrong place for it! I guess I'm a little unclear on how to define a pin as an input, an output or both - the compiler seems to do this automatically based on a) the actual pin capability on the device, and b) the logic equations. It does seem to be assigning my input pins as inputs, but leaving the outputs defined as i/o. I was thinking that may be my issue.Edit - i should add that I'm using the statementPROPERTY ATMEL {preassign KEEP};- and the fitter appears to be assigning the pins mapping correctly (my declared pin number is what it uses when fitting everything into the device).cheers,Dean

author: deanclaxton
author_rank: Regular Contributor
timestamp: June 18, 2020, 10:33:52 am
content: Got it sorted! I found a paragraph at the end of a uni lecturers course notes I found online (http://ecee.colorado.edu/~mcclurel/WinCUPL_Intro_handouts2.pdf) that said :"Students have reported that the negative polarity declaration on output pins does not work. The code compiles without error, but the actual SPLD doesnt seem to work. Be forewarned! I recommend you declare active HI outputs and avoid using negative polarity". FFSAnyway, modified my code and it works!!!BTW I believe the logic was wrong, and should have been as follows for active low outputs :OE = 'b'1; /*enable the output */WE = 'b'0; /* disable write */But as said, that didn't help - I think I struck the bug with declaration of active low outputs.

author: TomS_
author_rank: Frequent Contributor
timestamp: June 20, 2020, 08:37:06 am
content: This is interesting, because Im planning to use the same devices in an upcoming project for much the same reasons - still actively available and 5V - and have been playing with WinCUPL quite a bit in recent times. It was my understanding that the negative polarity issue only existed on the smaller GAL/SPLD like devices, and not the bigger CPLD brothers, but from what you are suggesting this will also be an issue in the CPLDs too?It all seems to be working great in WinSIM anyway, whereas I recall I definitely saw issues with trying to simulate it on GALs.But anyway, if I have read this all correctly on a Saturday morning, then I think what you initially experienced is correct. These devices seem to have a slant towards positive logic, e.g. to reset a latch you need to send its reset pin a positive going edge whereas on a physical IC you might give it a negative going edge.So if you have an active low output, then you would still have to give that pin a high signal to cause it to go low because you negated the output polarity. Or did I just swing and miss...?But the pin not changing at all is concerning... I have a dev kit for the ATF1500 series, so I might dust it off and test it out again, because I dont recall seeing this.I would be happy to exchange notes in general, PM me. Ive collected a lot of documents about CUPL etc that have helped me get to grips with it.

author: TomS_
author_rank: Frequent Contributor
timestamp: June 20, 2020, 09:33:25 am
content: Yes, on my test device that came with my dev kit, an ATF1502AS, I can definitely toggle pins using negative logic correctly.The code (stupidly simple test):Code:Name tqfp ;PartNo 00 ;Date 6/20/2020 ;Revision 01 ;Designer Engineer ;Company Engineer ;Assembly None ;Location U1 ;Device f1502isptqfp44 ;/* *************** INPUT PINS *********************/PIN 15 = sw1;/* *************** OUTPUT PINS *********************/PIN 2 = !output;output = sw1;WinSIM result:And real world result:As terrible as WinCUPL is, the assembler seems to be reasonably clever, so you shouldnt need to do anything special.Pins can be bidirectional, you can read the value off the pin using the .io extension. If you wanted to have a bidirectional data bus for example you would write your output values into the pins latches and use .oe to enable the outputs (low Z), and you would read in a value using the corresponding .io's.

author: deanclaxton
author_rank: Regular Contributor
timestamp: June 20, 2020, 12:37:23 pm
content: Interesting - thanks TomS_I have since found that the programming software doesnt seem to pick up the latest JED file after recompiling - its possible that when I changed my code to fix my logic, compiled and reprogrammed - the programming software actually programmed the previous file onto the chip and I saw no change.Anyways, I will PM you as if would be great to share notes on these CPLD

author: TomS_
author_rank: Frequent Contributor
timestamp: June 20, 2020, 02:17:37 pm
content: Quote from: deanclaxton on June 20, 2020, 12:37:23 pmAh yeah, that might do it. I havent done much beyond WinSIM to test out my theories, although I do have a programmer and some actual silicon, but given the apparent quality of the software I wouldnt be surprised if you would have to restart ATMISP or which ever other software you use each time the file changes. Probably its not meant for rapid development, which is why things like WinSIM exist.WinSIM has its fair share of quirks and its own learning curve too, and sometimes it just seems to stop working and you have to restart it too. Takes a bit of time to get used to the signs, but I would prefer to use it than constantly reprogramming a device because you can test changes very rapidly.

author: Bassman59
author_rank: Super Contributor
timestamp: June 20, 2020, 07:34:10 pm
content: Wow, a walk down memory lane.A bad memory. Because when I was using WinCUPL for 22V10s and suchlike back in the early 90s, the tool was buggy as hell and none of the bugs were ever addressed. Altera's HDL (AHDL) and later VHDL were obviously much better. But doubtful that those options are available for your ancient device.

author: TomS_
author_rank: Frequent Contributor
timestamp: June 20, 2020, 08:30:46 pm
content: Yeah, it's not the greatest development experience I will admit. The very latest (last!) version of the software still has issues that are very much like beta version issues. A lot more polishing could have been done.But I've been working out the quirks and getting used to them and I feel like I can be quite productive.I think the only viable alternative which I have considered from time to time are the Altera 7000 series CPLDs. You can write Verilog and maybe VHDL for them, but you either have to find NOS or get lucky with second hand parts (JTAG not locked out).I don't mind CUPL though, reminds me a lot of writing assembly - you're just describing exactly what the logic should do, good brain exercise I think. :-)

author: up8051
author_rank: Frequent Contributor
timestamp: June 21, 2020, 09:32:47 am
content: For ATF150x CPLD is available ProChip Designer V5.0.1 (VHDL/Verilog entry) but unfortunately it is paid.I don't understand why Atmel / Microchip doesn't make it available for free.You can apply for 1-month free evaluation licenese:https://www.microchip.com/prochiplicensing/

author: TomS_
author_rank: Frequent Contributor
timestamp: June 25, 2020, 06:29:11 am
content: Yeah, I heard about that, but you also then need some additional software to do simulation, which is also not free IIRC.So I pretty much ruled out out as an option because it's not accessible enough.For all of their problems, WinCUPL and WinSIM are completely free now, and once you "figure them out" you can just crack on.

author: spudboy488
author_rank: Regular Contributor
timestamp: June 25, 2020, 11:38:13 am
content: I use Quartus, but schematic capture because that's the way I roll. Convert the .pof to .jed using POF2JED 4.45.1. Program using the .jed with ATMISP v7.2.2 and the Microchip ATDH1150USB-K pod. All free tools (except for the programming pod).Using this line-up, I have converted MAX3000/7000 designs to ATF150x parts.

author: deanclaxton
author_rank: Regular Contributor
timestamp: June 26, 2020, 09:43:44 am
content: Interesting - could Quartus be used to program in HDL and somehow converted for the Atmel CPLD & programming tools?

author: up8051
author_rank: Frequent Contributor
timestamp: June 28, 2020, 06:32:47 pm
content: Yes.https://stageapps.microchip.com/design-centers/programmable-logic/spld-cpld/tools/software/pof2jed

author: TomS_
author_rank: Frequent Contributor
timestamp: June 29, 2020, 10:30:03 am
content: Going to have to check this out myself. Thanks!edit:Is it Quartus II (web edition?) 13.1 (edit: no 13.0sp1 is the latest to support MAX 7000) that is the most recent version to still support the MAX 7000 series? At least that is what Intels website suggests. But presumably I can download and install this and take the .pof files and run them through pof2jed and then program to an ATMEL part?It has taken me to this page:https://fpgasoftware.intel.com/13.0sp1/?edition=web&platform=windows

author: spudboy488
author_rank: Regular Contributor
timestamp: June 30, 2020, 11:38:14 am
content: Quote from: TomS_ on June 29, 2020, 10:30:03 am13.0sp1 web edition is the version I use. Yes, you can take the .pof and convert it to .jed using pof2jed and program the part with a compatible programmer/SW. See my post above regarding the version that I use.

author: TomS_
author_rank: Frequent Contributor
timestamp: June 30, 2020, 07:00:25 pm
content: Ive managed to build myself a working hardware "hello world" - a blinking LED. :-)Heres are the processes I had to follow.On the first run:1. Compile in Quartus to produce a .pof2. Open pof2jed, open the .pof file, click Run to make a .jed3. Open ATMISP, add a device and assign the .jed to it, save your chain file!, then click Run to programOn subsequent runs:1. Recompile in Quartus2. In pof2jed simply hit the Run button (you dont need to re-open the .jed file)3. In ATMISP, re-open the chain file, then click Run to programIt seems that ATMISP reads the .jed file into memory when the chain file is opened, rather than reading it in on each subsequent programming attempt. Oh well, I guess that makes sense, since it is a production programming tool, not an iterative development tool. :-)Heres my test code which I developed as an EPM7032 and programmed into an ATF1502 on my ATF15XX-DK3 dev board.(edit: tidied up code a little)top.vCode:`timescale 1ns/1psmodule pof2jed_test(input clk,output reg led);wire out;clk_div clk_div1(.clk(clk),.out(out));always @(posedge out) beginled <= ~led;endendmoduleclk_div.vCode:`timescale 1ns/1psmodule clk_div(input wire clk,output reg out);reg [15:0] count;// localparam tc = 32767;localparam tc = 65535;always @(posedge clk) beginif (count == tc) begincount <= 16'b0;out <= ~out;endelse begincount <= count + 1;endendendmodule

author: deanclaxton
author_rank: Regular Contributor
timestamp: July 01, 2020, 02:11:28 am
content: That's awesome! Good to know there is another free development path for these Atmel CPLD devices. I've got my code working now using WinCUPL - quite used to it now, but the editor is terrible, and error messages are a little brief (can take a bit to work out an issue). On the plus side it's straight-to-the-point and quick to get something running.My original issue with the inverse pin logic turned out to be 2 things :1. Me stuffing up the logic for the pin when declared active low (setting the pin to 1 (active) sets a pin declared active low, to 0 (low) - makes sense! )2. Recompiling after trying to fix the logic, but not re-loading the file into ATMISP before reflashing (assuming that it always loaded the file from disk before flashing- it doesnt).Once all that was understood, then it all works. I'm still interested to learn VHDL or Verilog though, so this gives a great opportunity to do that with free toolsI dont know anything about the EPM7000 series - if EPM7032 maps to ATF1502, and I'm using ATF1504AS, I assume (wrongly!) there is a EPM7034 maybe that is equivalent. EDIT : oh of course - the '32' part is the number of macrocells - 1504 maps to a EPM7064!

author: TomS_
author_rank: Frequent Contributor
timestamp: July 01, 2020, 07:02:27 am
content: Quote from: deanclaxton on July 01, 2020, 02:11:28 amThe ATF15xx are pin for pin compatible with the MAX 7000 series (kind of amazing really, or was that deliberate?), so as long as you choose one with the same number of macrocells and the same package type (!!) then it seems you should be fine.EPM7032 = ATF1502EPM7064 = ATF1504EPM7128 = ATF1508

author: deanclaxton
author_rank: Regular Contributor
timestamp: July 29, 2020, 04:41:07 am
content: I've discovered some useful information about the ISP versions of these devices as I've been using them for my ROM X product (http://www.theromexchange.com).It IS possible to use the JTAG pins as general I/O by adding the following property to your source :PROPERTY ATMEL {JTAG=OFF};With that in there, the code should compile, the fitter should then re-use the JTAG pins as you intend, and create a .JED file for programming. Once programmed (you'll be prompted to set the JTAG Port Check Override option in the ATMISP options menu), the JTAG will be locked out, but you've got 4 more pins to play with!Now, if in your design you ensure that you can isolate the OE1 pin on the CPLD from any other circuitry (so that you can safely apply +12V to the OE1 pin without blowing the crap out of anything attached to it!) then you can re-enable the JTAG port in this manner. Applying +12V to the OE1 pin through a resistor (1k8 is fine) whilst attemting to reprogram the chip in ATMISP should yield results. I initially get a verify error, but after that the JTAG is unlocked again and usableI suppose you also best ensure that nothing is going to be driving the JTAG pins while you are programming else include links (jumpers or smd resistors etc) to disconnect other circuitry from the JTAG pins.Anyways, this may free up some pins for you

author: TomS_
author_rank: Frequent Contributor
timestamp: August 06, 2020, 06:34:42 am
content: Ah nice. I wonder if the same process works for Altera MAX7000 devices... I know several people that buy these second hand, and sometimes they come with JTAG locked (I guess because they are pulled from boards), and have to use very special programmers to unlock them again.Might see if one of them can give this a go if they dont mind potentially blowing a hole in the top of one.(I did already know about using the JTAG pins as IOs, but not how to reverse that once programmed, so thats a useful bit of knowledge to tuck away!)

author: deanclaxton
author_rank: Regular Contributor
timestamp: September 05, 2020, 05:35:02 am
content: Hmmm - word of caution. Whilst applying 12V to OE1 does unlock the JTAG port to allow you to reprogram the device, it appears that if the security fuse has been set (PROPERTY ATMEL {security ON}) then this doesnt work. Not much info on the security fuse in the datasheet other than this:A single fuse is provided to prevent unauthorized copying of the ATF1504AS(L) fuse patterns. Onceprogrammed, fuse verify is inhibited; however, the 16-bit User Signature remains accessible.If you arent worried about security of your CPLD, and don't set the security fuse, then re-using the pins works great, and the device is reprogrammable via the 12V OE1 trick.I'd love to know if there is a way to recover from the security fuse being set - I'd like to be able to erase a device after setting the fuse. Does anyone know about this? Is this where the expensive 3rd party programmer comes in? If so, what does it do to erase the device?

author: TomS_
author_rank: Frequent Contributor
timestamp: September 07, 2020, 07:54:27 pm
content: According to this documenthttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/archives/m7000.pdfan "erase pulse" of 100ms is required after shifting in erase instructions via the JTAG port.I wonder what this erase pulse is supposed to be voltage wise and to which pin it is applied.If it can even remove the security bit setting at all...

author: deanclaxton
author_rank: Regular Contributor
timestamp: September 08, 2020, 09:36:35 am
content: Hmmm - yes that datasheet also states :Design SecurityAll MAX 7000 devices contain a programmable security bit that controlsaccess to the data programmed into the device. When this bit isprogrammed, a proprietary design implemented in the device cannot becopied or retrieved. This feature provides a high level of design securitybecause programmed data within EEPROM cells is invisible.The securitybit that controls this function, as well as all other programmed data, isreset only when the device is reprogrammed.So it seems it can be done, but the question is how

author: Andy Watson
author_rank: Super Contributor
timestamp: September 08, 2020, 10:23:05 am
content: Does it make a difference if you replace the word "reprogrammed" with "erased" ? Whatever the security mechanism is, it must ensure that the original IP cannot be read, or otherwise inferred by manipulating bits. Erasing the device to a blank state is a good method of achieving this.

author: deanclaxton
author_rank: Regular Contributor
timestamp: September 08, 2020, 11:05:24 am
content: Yes - thats what I'm looking for - to be able to secure the device, but to also be able to erase it and reprogram it. I'm reusing the JTAG pins as IO - those can be "unlocked" again by applying +12V to the OE1 pin whilst reprogramming (JTAG) - that works great. It all went pear shaped when I set security - well, in that the +12V OE1 trick doesnt let me erase it. I'll do some more experimenting though. I guess I should log a support query with Microchip!

author: TomS_
author_rank: Frequent Contributor
timestamp: September 09, 2020, 11:28:49 am
content: Do you have to maintain 12V on the OE pin to keep the JTAG port open, or only on power up?If only on power up, I wonder if you could remove 12V from OE1 once youve established that JTAG is working, send in the erase command, and then do a 100ms pulse of 12V perhaps? If that is what is meant by an "erase pulse" anyway.Otherwise yeah, send a support request to Microchip and see if they will give you anything. Very interesting stuff though!Otherwise I wonder if there is any documentation for the MAX7000 series around that shows the programming/erase waveforms and whether they would happen to be the same. I did try searching the other day but it was late so I didnt get too far.

author: maginnovision
author_rank: Super Contributor
timestamp: September 09, 2020, 02:35:54 pm
content: I know the conversation has shifted somewhat but if you ever do use wincupl I recommend removing any of the optimizations as they sometimes fail to create equations that match the originals. It's best to compare the output to what you wrote if you do run into any issues. Generally it actually does exactly what it says, it just doesn't do what you asked when you attempted to compile. Also when you flash you need to re-select the file since atmisp caches the .jed.

author: LittleRain
author_rank: Contributor
timestamp: March 25, 2021, 09:31:47 am
content: Quote from: deanclaxton on June 18, 2020, 12:09:54 amPage 3, says Prochip Designer is free.Can download from here, although you need to be approved before you can actually download.I just put in an application, so I'm not sure how the process really works.I know this is an old post, but I thought the original poster would be happy to know about it, as well as anyone else interested in Atmel CPLDs.

author: oPossum
author_rank: Super Contributor
timestamp: March 25, 2021, 11:56:34 pm
content: They will give you a free 30 day eval. After that is is $600 for a 2 year license. Part # ATDS15xxKSW1

author: shutay
author_rank: Newbie
timestamp: April 19, 2021, 03:11:13 am
content: I'm rather late to the party, but you might want to consider this open source tool by H. Neeman, called "Digital", which unfortunately makes it very hard to find using Google if you only know the name of the tool. It is a schematic entry simulation software written in Java that, working together with the fitter tools from WinCUPL (which needs to be installed alongside it), can generate the necessary files to program the ATF150x series CPLDs (via ATMISP 7.0, which also needs to be installed). It seems to be actively supported, and version 0.27 was released just 10 days ago. Remember to tell Digital where to find WinCUPL and ATMISP in the settings dialog.https://github.com/hneemann/DigitalSupported devices: GAL16v8, GAL22v10, ATF1502 (TQFP & PLCC), ATF1504 (TQFP & PLCC44), ATF1508 (PLCC84 only).You can also check out this series of videos produced by Douglas Gabbard on YouTube:https://youtu.be/4LYgWtVbT2sI have been using them with the ATF1504AS PLCC44 chips and can confirm that at least for my needs, it has served me well (WinCUPL keeps crashing on me).It can take a truth table and generate logic based on NAND gates or NOR gates, or LUTS, export Verilog or VHDL. It does not allow a circuit to be defined in HDL, AFAIK. To me, this tool alone can help make the ATF150x series more popular again. If not, then more usable.Best, Jason