VGA on a FPGA board - Page 1
Forum section: electronics / general

author: Moondeck
author_rank: Regular Contributor
timestamp: June 11, 2015, 01:35:29 pm
content: Hi, could anyone explain to me this code in Verilog? I am new to FPGAs, but i did MCUs before (C, Arduino) so i am not a complete noob when it comes to coding, but could someone explain what this code does step-by-step?Code on this site:http://www.fpga4fun.com/PongGame.htmlRegards, Moondeck

author: amyk
author_rank: Super Contributor
timestamp: June 11, 2015, 01:50:39 pm
content: QuoteArduino doesn't count.QuoteYes they could, but how about you learn some Verilog first...?

author: Moondeck
author_rank: Regular Contributor
timestamp: June 11, 2015, 01:54:23 pm
content: I know SOME verilog, but not enough to understand it myself. And i am also not using Ardooinoo anymore, its inefficient, so yeah.

author: tggzzz
author_rank: Super Contributor
timestamp: June 11, 2015, 01:57:12 pm
content: Quote from: Moondeck on June 11, 2015, 01:35:29 pmNo. That would either take far too long or the explanation wouldn't be sufficient. You have a learning curve ahead of you that is comparable to that of learning to use a computer and the to program a computer.Be aware that despite some similarsyntax, thesemanticsof the statements are completely different to any procedural computer language. Why? Because hardware has completely different characteristics and constraints to computer programs.For example, if you have a 10000 LUT FPGA, then there is an argument that you are "programming" 10000 very simple "computers" all running in parallel at ~100MHz. You will see claims that you can program FPGAs in C or C++ or another prcedural language. I've been seeing such claims for 30 years, and expect to go on seeing them for the rest of my career!There are many FPGA and Verilog tutorials around, easily found via your favourite search engine. Use them, and eventually you will enjoy programming FPGAs.

author: Moondeck
author_rank: Regular Contributor
timestamp: June 11, 2015, 01:59:02 pm
content: Thanks for the answer, i tried googling the topic, and i've found plenty of examples, but no explanation of the code.

author: tggzzz
author_rank: Super Contributor
timestamp: June 11, 2015, 02:05:41 pm
content: Quote from: Moondeck on June 11, 2015, 01:59:02 pmWould you expect a google search to enable you to find the "explanation" of an arbitrary piece of C code? No, of course not.

author: Moondeck
author_rank: Regular Contributor
timestamp: June 11, 2015, 02:08:00 pm
content: Nope, but when i had a hard time figuring out C i have asked here.

author: tggzzz
author_rank: Super Contributor
timestamp: June 11, 2015, 02:09:48 pm
content: Have a look athttp://www.catb.org/esr/faqs/smart-questions.html#intro

author: Moondeck
author_rank: Regular Contributor
timestamp: June 11, 2015, 02:15:51 pm
content: Okay, i am probably better off doing it myself then.

author: matseng
author_rank: Frequent Contributor
timestamp: June 11, 2015, 02:16:53 pm
content: To get a better base for later on learning either of the "real" FPGA languages Verilog and VHDL I'm working my way through the freehttp://nand2tetris.org/course. It's not bad at all. The HDL they use in that course is a simplified variant that you can be quite proficient in after just one hour, but it's enough to implement a complete PC in it anyways.If you have some digital electronics background and know how regular combinatorial and sequential logic devices work the first three weeks of the course will just take a couple of hour to listen to the lectures (at 1.5x speed), read the recommended chapters in the free book, and doing the assignments.So far I'm very happy with my spent time and I really feel that I'll have good use of the new skills when in the future I'll start learning and playing with VHDL & FPGAs. I have some different development FPGA and CPLD development boards in my drawers that I never used because of the steep learning curve. But now I have new hope for actually being able to use them.

author: tggzzz
author_rank: Super Contributor
timestamp: June 11, 2015, 03:22:37 pm
content: Quote from: Moondeck on June 11, 2015, 02:15:51 pmDo your preparation, then come back and ask a question that people can reasonably answer.

author: ale500
author_rank: Frequent Contributor
timestamp: June 11, 2015, 04:13:35 pm
content: There are some on line courses. They are quite basic, but very useful.Here there is one from asic world:http://www.asic-world.com/verilog/index.html.I'd recommend you get yourself acquainted with a simulator like icarus verilog (http://iverilog.icarus.com), you can also use the ones that come with Xilinx' WebISE/Vivado or Lattice Diamond (Aldec HDL). Do the examples and code there, and remember (almost) everything happens in parallel, Verilog and VHDL describe circuits with gates and flip-flops.Note: I haven't looked at your VGA example but from what I have done I know that you can easily construct a (simple) VGA controller using counters, comparators and gates, and an oscillator. Try a circuit for the horizontal sync. A counter, 3 comparators, few gates and an oscillator... there is nothing more to it.Code:module hsync(input wire clk_25,output reg hsync);reg [9:0] hreg;always @(posedge clk_25)beginif (hreg < 10'd800)hreg <= hreg + 10'd1;elsebeginhreg <= 10'd0;endhsync <= (hreg < 96) ? 1'b0:1'b1;endendmoduleThere you have a counterhreg, two comparators:(hreg < 96)and(hreg < 10'd800), and I used an extra flip-flop for the sync signalhsync.How does it work ?Well, the horizontal synchronism signal is a periodic signal, it has a low part (sync active) and a high part (no sync inactive) (for VGA 640x480 @ 60 Hz). The low part are some 96 clocks @ 25 MHz, aka 96 pixels. Visible pixels are 640... the rest are what is know as front porch (before visible part) and back porch (after visible part).There are several ways of achieving such a signal. The code above is one of those.vertical sync is generated in a similar manner but the timing is different.have fun !

author: Moondeck
author_rank: Regular Contributor
timestamp: August 11, 2015, 09:24:59 am
content: Hi.Sorry for reviving an old post, but i need help again. I now understand the code, but the problem is i have an FPGA with 12MHz main clock, how should i go about generating VGA with that frequency?

author: miguelvp
author_rank: Super Contributor
timestamp: August 11, 2015, 01:47:50 pm
content: Most FPGAs have PLLs (Phase Locked Loop) hardware that allows you to multiply and divide the board frequency to higher, lower and fractional frequencies.

author: Moondeck
author_rank: Regular Contributor
timestamp: August 11, 2015, 02:27:22 pm
content: I have read the Spartan-3 paper, UG331, where it describes the "DCM" (Digital Clock Manager) But from what ive read, it can only multiply by an integer, not a float. would VGA work at 24MHz? Also, how do i call the DCM? Is it just like registers in microcontrollers, fx. OSCCON = 0b10101010 or OSCCON = 5?Edit> It CAN take non-integer values, which increases jitter, but thats for the DLL

author: tggzzz
author_rank: Super Contributor
timestamp: August 11, 2015, 02:55:32 pm
content: Quote from: Moondeck on August 11, 2015, 02:27:22 pmI challenge you to findanyic that can multiply by a float. Of course many can multiply by a range of rational numbers. That distinction is important to understanding what and why!

author: Moondeck
author_rank: Regular Contributor
timestamp: August 11, 2015, 03:01:46 pm
content: Well, yeah. But will the 24 MHz clock work then, when the nominal clock is 25 - 25.125 MHz?

author: miguelvp
author_rank: Super Contributor
timestamp: August 11, 2015, 03:09:43 pm
content: When I mentioned fractional I meant two integers, a multiplier and a divider so not really floating point but out of 12MHz you can get lots of useful frequencies.I don't know much about Xilinx, but if they do offer PLL then you can derive your VGA pixel clock from that. It doesn't have to be on the dot, something close to 25.175 MHz will do, exact frequency for 640x480 @ 60Hz is 3600/143, since you are starting with 12MHz you can get the exact ratio if you multiply by 300 and divide by 143.Source for exact dot clock rate fraction:https://pineight.com/mw/index.php?title=Dot_clock_ratesSource for VGA specs:http://tinyvga.com/vga-timing/640x480@60Hz

author: Moondeck
author_rank: Regular Contributor
timestamp: August 11, 2015, 03:23:02 pm
content: Will try that, now how should i call the DCM? Is it like i've mentioned, like registers or how?

author: miguelvp
author_rank: Super Contributor
timestamp: August 11, 2015, 04:07:00 pm
content: I don't have time to look at the details of this doc but it might help you:http://www.xilinx.com/support/documentation/application_notes/xapp462.pdfI don't know much about Xilinx, it if was an Altera FPGA then I would have more 1st hand experience.

author: Moondeck
author_rank: Regular Contributor
timestamp: August 11, 2015, 04:09:26 pm
content: Thank you, i will try it and see what the result will be.

author: ale500
author_rank: Frequent Contributor
timestamp: August 11, 2015, 05:13:42 pm
content: Try to get 25 = 12 * 25  / 12  the DCM in Frequency synthesis mode, page 46 of that xapp462. There is 800x600x56 @36 MHz, it may be an option too...

author: Moondeck
author_rank: Regular Contributor
timestamp: August 11, 2015, 06:10:24 pm
content: Quote from: ale500 on August 11, 2015, 05:13:42 pmI have got the freq i wanted, i am now going to implement the actual VGA generation part.