[SOLVED] Struggling to work out a crossover switch equivalent in logic - Page 1
Forum section: electronics / beginners

author: castingflame
author_rank: Regular Contributor
timestamp: May 18, 2020, 11:26:16 am
content: Hi thereI have been struggling for several days/weeks to find a solution to what must be a very common requirement.I have 2 inputs and 2 outputs and I wish to cross them over on demand using an MCU. This works fine in an MCU using a state machine but the tiny processing delay that has been created is stopping this from working correctly as the Ins and Outs are part of a signal packet. I was looking to use some sort of logic gates / flip flops to do this but I keep running into brick walls. I ran the In /Outs through 74HC series logic OR gates and it works okay to a point. I was able to turn each In and out of using my MCU as the second 'CTRL In3' input but not able to swap the Outputs over.Truth Table: Signals are active lowIn1 | In2 | CTRL In3 | Out1 | Out2---------------------------------------0 0 0 1 1 : In practice In1 & In2 can will not be high at the same time. (Mutually Exclusive on low) de-active outputs1 0 0 1 0 : In2 active to Out20 1 0 0 1 : In1 active to Out10 0 1 1 1 : Again Invalid due to mutually exclusive low In1 & In2 so keep outputs high1 1 0 1 1 : Both Ins inactive, Both Outs inactive regardless of CTRL In3 state0 1 1 1 0 : In1 active to Out21 0 1 0 1 : In2 active to Out11 1 1 1 1 : Both Ins inactive, Both Outs inactive even regarless of CTRL In3 stateCTRL In3is and MCU pin.Update:In1 and In2 are Mutually Exclusive to the low condition; ie both will not be low at the same time.Thanks in advance for any help you can give.

author: Nusa
author_rank: Super Contributor
timestamp: May 18, 2020, 11:42:38 am
content: Your truth table is incomplete. Expand it to include all 8 possible input combinations, which of course map to 4 possible output combinations.

author: capt bullshot
author_rank: Super Contributor
timestamp: May 18, 2020, 11:46:46 am
content: A simple example in vhdl to do so (no clock and no flipflops involved, so delay is just the propagation delay of the synthesized logic):outp: process(in1,in2,in3)beginif (in3 = '0') thenout1 <= in1;out2 <= in2;elseout1 <= in2;out2 <= in1;end if;end process outp;This equals to a simple circuit using inverter, AND and OR gates:Alternatively, one could use a double 2:1 mux like thishttps://assets.nexperia.com/documents/data-sheet/74HC_HCT157.pdfEdit: Yes, the truth table is incomplete, just assumed something and hope I assumed right.

author: castingflame
author_rank: Regular Contributor
timestamp: May 18, 2020, 12:24:55 pm
content: I've updated the true table, sorry about that!Quote from: capt bullshot on May 18, 2020, 11:46:46 amThank you, I'll go and have a read and come back in a bit. Very much appreciated.

author: Ian.M
author_rank: Super Contributor
timestamp: May 18, 2020, 12:50:35 pm
content: If you want to implement a two input data selector in SSI (gate level) logic, you need to AND the input signals with Ctrl and /Ctrl respectively, so one gets through, then OR the AND outputs together. The whole can be done with a single 74xx00 quad two input NAND. as by De Morgan's laws, an AND wrapped in NOTs transforms to an OR, using the remaining gate to invert the control signal.To swap two inputs routed to two outputs, you'd need two of the above, but can save a gate as they can share the inverter for the control signal.However it would be pretty dumb to use two chips when a single 74xx157 can do the job, unless you are stuck patching something together out of your lockdown junkbox!Note: for xx in 74xx... substitute whatever 74 series logic family you are using e.g LS, HC, HCT etc

author: capt bullshot
author_rank: Super Contributor
timestamp: May 18, 2020, 01:15:18 pm
content: Quote from: castingflame on May 18, 2020, 11:26:16 amThis condition shouldn't make any difference on the logic to built. Assuming both inputs low will never occur, it doesn't matter what the logic puts out on this condition.So one could fill the truth table with an X (meaning don't care) for these input combinations. Then one could reduce the required logic using these KV (Karnaugh maps) diagrams. Or just use the dual multiplexer solution.

author: castingflame
author_rank: Regular Contributor
timestamp: May 18, 2020, 02:02:04 pm
content: Gentlemen, we have a winner!I only have 74LS157 in stock but I set it up on a new breadboard in isolation and it is working exactly as requiredI have ordered some HT variant from RS so hopefully I should be able to try it in my project tomorrow.This is the first time I have used a MUX and it wasn't half as scary as I had imagined. As a massive bonus, the 74HC157 has also freed up an I/O pin on my MCU. I guess I will provisionally look at trying to shoe-horn the 157 on to my PCB design in KiCAD now!Your help is VERY much appreciated as it was a big stumbling block for my little project so thank you

author: brucehoult
author_rank: Super Contributor
timestamp: May 18, 2020, 04:00:36 pm
content: Quote from: Ian.M on May 18, 2020, 12:50:35 pmIn fact, half of one...

author: Ian.M
author_rank: Super Contributor
timestamp: May 18, 2020, 07:26:39 pm
content: Half of its data width, *YES* as it is after all a quad multiplexer, but it only has a single select input, so its questionable how useful the remaining 'poles' will be.Another approach, useful when you are dealing with bidirectional signals or squeezing your margin for propagation delays in the signal path down to their minimum limit, is to literally switch the signals with a DPDT analog switch. Unfortunately the switch on resistance in series with the signal makes it unsuitable for fast signals with high capacitive loading e.g long wires or driving many IC inputs in parallel. A suitable IC for this approach would be 2/3 of the 74HC4053 triple SPDT analog switch, which at 5V Vcc typically has an on resistance under 100 ohms, which gives a RC delay of around 5ns when driving a 50pF load with normal CMOS input thresholds.