Interfacing with fast (MHz) open-drain outputs? - Page 1
Forum section: electronics / projects

author: exmadscientist
author_rank: Frequent Contributor
timestamp: December 11, 2022, 08:19:42 am
content: Through the usual series of misfortunes, I've been asked to work with a poorly-designed (ok, mostly just pin-starved) chip having a (single-bit) open-drain output. We'd like to get the clock rate on this interface up to 10MHz (or maybe it was 5MHz, I forget, but overdesigning to get a little SI margin is going to be useful here so who cares).Dealing with an open-drain output having an unspec'ed, kinda-wimpy output transistor operating at 10MHz is not simple. This is not GTL or anything like that, with a real spec and some parts available. Just an output where the manufacturer suggests maybe using a 300-ohm pull-up. Maybe that'll work. I don't need much from this thing, I can plop a regular buffer next to it (a fast '34 or '1T45 or whatever) in the next spin/rework and get to the 3.3V CMOS I need to have at the other end of this (biggish) board. I am a little worried right now because the waveforms at 500kHz with a 1k pullup were not stellar, but I always forget how crappy open-drain outputs are supposed to look. I also didn't pay too much attention because it was working. That was before they asked to speed it up....Is there anything better or more clever to do here than dump pull-up resistor current into the poor chip? I would prefer not to burn that much power, but if that's the best option, it can be accommodated.

author: moffy
author_rank: Super Contributor
timestamp: December 11, 2022, 08:42:27 am
content: You are fighting against capacitance, maybe if you used a non saturating PNP current source instead of the pull up resistor you would get a linear rise rather than the normal RC rise. Might be a little faster. You do have to worry about the open collector transistors delay in getting out of saturation. That might be the biggest limiting factor.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: December 11, 2022, 09:52:04 am
content: Low resistance and low capacitance is about the only answer, however depending on the nature of the signal, and how much you care about power draw, you may be able to reduce static draw a bit with an R + RC network of some sort.A TTL-level buffer ( e.g. 74HCT) might be useful as it has a narrower input threshold, so you don't have to swing so far to get a clean signal.

author: thm_w
author_rank: Super Contributor
timestamp: December 13, 2022, 12:29:45 am
content: Presumably there is only the footprint for the one pullup resistor. So any suggestions outside of what will fit there are not usable.Maybe small chance something like a current regulating diode, or capping the pullup voltage with a diode + R could work. But I wouldn't even touch it, just say it can't be done with this hardware, requires new layout, and move on.If there are no spare I/O left, that is not ideal design. Consider a GPIO expander or something else that would have given you spare IO (although it wouldnt work for this 10MHz signal).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 13, 2022, 02:27:11 am
content: Mind that the scope probe totals some 10s of pF by itself, so you aren't getting the whole picture, not without a lighter touch (FET probe, say?) anyway.A transistor CCS can about halve the rise time by delivering full current over much of the swing, whereas a resistor drops current as the voltage rises. That's about it. If it's output-only, you could put a buffer after it so the node capacitance is just the two pins, and CCS if applicable, which should be okay to run that fast.What kind of coding would you use, anyway, if it's a single bit stream, no clock, no peripherals (SPI/I2C/etc.)? Or is this one part of an overall bus so most of those issues are solved, just the physical problem remains?Is this an MCU or FPGA? Which one? What is the pin spec (VOL, IOL, etc.)?If the circuit is more or less fixed (minimal alterations available), maximum clock is simply whatever it is. If that makes the underlying task impossible, well, maybe that's incentive to open up those other changes.Tim

author: profdc9
author_rank: Frequent Contributor
timestamp: December 13, 2022, 04:33:37 am
content: Perhaps have the output drive the base of a low capacitance common-emitter PNP transistor (e.g. 2N3906) to use the open drain output like a current sink output. Use a Baker clamp diode on the base-collector junction of the PNP (low capacitance Schottky like 1N5711) so that when the current from the output drive shuts off, the PNP transistor shuts off more quickly. This will provide an inverted output you can use to drive a regular CMOS inverter (for example 74HC04).

author: exmadscientist
author_rank: Frequent Contributor
timestamp: December 27, 2022, 10:55:53 am
content: Thanks for all the suggestions (and apologies for ignoring this topic, I've been swamped lately, including a stint as cable tech, since there's no one else to do it).This is an output driver built into a poorly-designed and worse-documented recent IC by one of the majors that I (generously?) don't much feel like slagging at the moment. (Also someone else around here might or might not -- I can't be arsed to track these things, I have cables to build -- have signed an NDA with them. That too.) It really shouldn't be open-drain, but they haven't actually got a V_IO input pin on this part, so they did this instead. Thanks?The goal is to get this interface running faster on the next spin, so there's full freedom of design and no need to bother with bodging something in to the current boards (save for any testing/prototyping... which I am inclined to be rather reckless about as the fallback plan is just "rip out all the fancy stuff but leave the pull-up resistor"). I have to send this signal something like 300mm across a standard FR4 board to the (unremarkable LVCMOS33) MCU input. That's enough capacitance that the next spin will have a fast buffer gate right at the chip, which should help a lot. It also makes the buffer's input spec the relevant one, and there's plenty of freedom there if ordinary LVC logic won't do.Present measurements were done with an analog channel of a recent Saleae logic analyzer model. Probably not the best (and I don't even know its input specs) but it was already there. The point about input capacitance is well taken.I'm disappointed but not surprised there's no standard circuit for doing this that someone's pointing me to. Itisa rather stupid thing to have to do, but that's life in this line of work.In terms of actual solutions, the active current source was my first thought as well, but it looks like crud in Spice. Very little benefit, dumps all that current anyway, and costs you a Vbe drop on your output. Spice is claiming that it can be quite slow to get moving, and that there ismassivecharge injection from the small N-MOSFET I'm using to mock the IC output driver. Any variation I've tried has been worse than the basic version.The best design so far seems to be turning on a "strong" pull as soon as the output rises above some small level (like one Vbe drop). That requires an NPN + PNP/PMOS and Spice is having fits that that pair suffers from all kind of charge storage/turn-on/turn-off issues and is getting extremely sensitive to the specific models used. Which is always a bad sign. There are also some LVDS-receiver based solutions, but they don't have great signal levels (even if they shouldn't need them) and have massive common-mode swings, neither of which inspires great confidence.Even though it should be great at this, I don't really believe the Spice results here. Sure, 10MHz is high enough that the weird stuff can start to show up... but enough stuff is fishy that I'm not buying it. I guess I'll have to see if I can find some time to prototype something. I'll also give the Baker clamped PNP another try. I could have sworn I tried that one (in Spice) but who knows... I also swore that remaking someone else's cables wasn't going to be my problem unless I was allowed to approve drawings before they were sent out, and you can guess how that ended....Thanks all for the guidance.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 27, 2022, 02:26:15 pm
content: You can't avoid the current dump, right. Any positive feedback (reduce current with rising voltage drop) will do weird things -- either it's very slow until it kicks in, or the threshold is too tight and feedforward through capacitance trips it up -- but also mind that the IC transistor doesn't have the massive capacitance of a, I'm going to guess 2N7002? That's about 6 times too big, or more, and many times more voltage rating too. IIRC, real logic outputs don't have nearly so much feedforward capacitance, so you won't see as much ugliness in practice. Use 74HC07 or LVC if you have a model available?All that a current source gets you is shaving off some ns at the top of the rise, versus a resistor that slow-walks it. That's all. Using smaller transistors like MMBT3906 is preferable (or MMBTH81 if you can still find it?), and discrete MOSFETs aren't available in those sizes so that's about it. Or I suppose a JFET as CRD (current regulating diode, strap G-S so it always delivers Idss), but you'd need to select(!) parts to get current in a reasonable range (5-10mA say?).If you had a complementary output (same type, open N-drain, just logical inversion), you could have one current contingent on the other, so it only drops current on transitions (this is how CMOS level shifters work); but I suppose if you had two pins available, you might have other possible solutions available, too.Tim

author: fourfathom
author_rank: Super Contributor
timestamp: December 27, 2022, 04:17:46 pm
content: Is this 10MHz clock just used as a 10 MHz source, or is it clocking data and so requires good phase control? If it's just a frequency source you can use a resonant LC step-up circuit driven by the open-drain transistor, feeding a HI-Z buffer. This is probably too touchy if you need precise phase alignment.

author: moffy
author_rank: Super Contributor
timestamp: December 27, 2022, 10:10:21 pm
content: I've had a thought about your dilemma. Since you can add components to condition the signal, what if you reduce the output impedance of the OC(open collector) circuit without drawing excessive current. Please see the attached LTSpice file. If you use a resistive divider R1/R2 to lower the output impedance to say 20 ohms, it also reduces the output level, but if you feed that signal into a fast(5ns) comparator the signal will be restored to its logic levels. Please note the values have been chosen purely for the simulation and do not represent a real life design i.e. in real life I would add extra caps and some hysteresis. Hope this helps.P.S. The blue trace is the output of the comparator. C1 is to simulate excessive trace/load capacitance.