Calculate value of DEcoupling capcitors  - Page 1
Forum section: electronics / beginners

author: caltroniks
author_rank: Newbie
timestamp: June 26, 2020, 09:10:10 am
content: Hello AllA basic query about decoupling capacitors.As a day to day activity of adding decaps to any micro.. (normally two decaps ,a higher value one and a small value cap in parellel to the high value one) they get added to the schematic and then to PCB e.g 10uf ,0.1uf)However am trying to understand if we an calculate the value of the capacitors .is there a standard formula for this .??Best RegardsAlun

author: Vovk_Z
author_rank: Super Contributor
timestamp: June 26, 2020, 09:15:26 am
content: There isn't a ready formula for decoupling capacitors but there is a formulas for resonant circuits.

author: Zero999
author_rank: Super Contributor
timestamp: June 26, 2020, 10:01:47 am
content: Short answer is no, no one bothers calculating the value of a decoupling capacitor, which is normally a much larger value, than the bare minimum.Quite often decoupling capacitors aren't even necessary, but are put in because they're much cheaper, than the potential problems created by their absence.

author: caltroniks
author_rank: Newbie
timestamp: June 26, 2020, 11:03:40 am
content: Hello ..Thanks for getting back ..any typical values recommend ..?and in general these values would be based on what crietria .other than cost...?Best RegardsAlun

author: schratterulrich
author_rank: Regular Contributor
timestamp: June 26, 2020, 11:09:29 am
content: Hi,For smaller micros and logic ICs it is usual to just use the datasheet values and you are on the safe site by doing so.On the other hand FPGAs, DRAMS and so on sometimes call for a specified target impedance up to a target frequency.Then there exist a formula - Ztarget = allowed ripple voltage / delta IThen not only the caps itself matters but the power planes too. Especially with very thin prepregs you can reach the goal of a low impedance up to high frequencies with nicely damped resonances.Major CAD companies offer simulation solutions for this problem - keyword PI (Power Integrity) - SimulationIntel (Altera) offers a spreadsheet for making calculations.https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/signal-power-integrity/power-distribution-network.htmlhttp://www.pdntool.com/is also useful - it will probably show, that 100nF || 10µF shows a good result.And last but not least I have written a tool, too.You can find it athttps://leiterplatte.jimdo.com/pdn-sim/

author: EEVblog
author_rank: Unknown
timestamp: June 26, 2020, 11:17:10 am
content: Quote from: Zero999 on June 26, 2020, 10:01:47 amYes, this.I've done videos on this:

author: David Hess
author_rank: Super Contributor
timestamp: June 26, 2020, 05:59:48 pm
content: The short answer is yes, there is a formula, but it is usually not worth bothering with if only because up to 0.1 microfarads, decoupling capacitors all have about the same cost. Typical designs use decoupling capacitors which are several times larger than necessary and performance could actually be better with properly selected values. (1)Take the simplified simple case of small scale integrated logic like a quad gate. The decoupling capacitance and driven output capacitance form a divider which modulates the supply voltage by pumping charge between the power pins and output pins. So if you know the driven output capacitance, and how many outputs switch simultaneously, and the allowable supply voltage drop, then you can calculate the minimum required decoupling capacitance.The same applies to large scale integrated logic however internal details are rarely provided and instead decoupling recommendations are made. On old datasheets you can sometimes find details for how much internal capacitance is switched for purposes of calculating power draw and external decoupling requirements.Where the above method for calculating the required input decoupling comes in very handy is driver circuits which operate with much higher capacitive loads like unterminated transmission lines and switching power transistors.(1) Selecting the proper value of decoupling capacitance combined with the series inductance of the decoupling capacitor and layout can place a low impedance null on a troublesome frequency spike.Quote from: caltroniks on June 26, 2020, 09:10:10 amThe bulk decoupling capacitor acts as an AC termination to suppress ringing between power and ground. Its value depends on the impedance between power and ground which is usually poorly defined. Selection is usually empirical but if the power distribution impedance is known, an optimal part can be chosen.

author: bob91343
author_rank: Super Contributor
timestamp: June 26, 2020, 11:23:17 pm
content: As expected, it's more complicated than it seems at first.A decoupling capacitor needs to have a low enough reactance at the frequencies of interest to avoid circuit instability. A higher value capacitor doesn't guarantee lower reactance due to the parasitic parameters such as ESL and ESR. So the first thing is to figure out how good it has to be, and the second thing to select a component that meets that criterion.I have measured electrolytic capacitors over a wide frequency range and was unhappy with the result. I have measured nonpolar foil capacitors with similar answers, although they do generally go to higher frequencies. Sometimes you need three capacitors in parallel. And when putting capacitors in parallel, use good lead dress for the higher frequency unit.Worse yet, sometimes the ESL of one capacitor can resonate with the C of another and create a tuned circuit, which will have the undesired high impedance.So the answer is that each situation is unique and needs evaluation. You can also shotgun it, as many have suggested, and often get satisfactory performance.

author: EEVblog
author_rank: Unknown
timestamp: June 27, 2020, 02:22:51 am
content: Quote from: David Hess on June 26, 2020, 05:59:48 pmBut that formula doesn't take into account all sorts of parasitics and application specific parameters.The only way to do it truly properly is to model the entire system extensively using special purpose tools and build up and verify the performance, and that can be weeks of work just for a fee bypass caps.This is why rules of thumbs rule in practical applications, and most don't even bother with general formula's.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 27, 2020, 02:59:31 am
content: The complete analysis is this:1. What supply impedance does the device require?This is rarely if ever documented, unfortunately. You can make some educated guesses, for example if it suddenly jumps from minimum load to full load (as a microcontroller might, going in and out of sleep mode), then that step change in current shouldn't cause more than a nominal change in supply voltage (say 10% or less of total supply, e.g. 330mV for a 3.3V supply). Or if the quiescent load is reasonably stable while driven loads dominate, then that (e.g., a MCU driving an LED display at 10mA/segment; the maximum step change is all 8 segments or 80mA total).2. And at what bandwidth?Most digital logic responds in a few nanoseconds, so the bandwidth is effectively a few 100 MHz. There isn't really much you can do beyond 50 or 100MHz on board, anyway (due to trace, pin and wirebond inductance), so it's fairly safe to assume you don't need to account for frequencies above there. (There are exceptions, like RF amplifiers and discrete circuits; these should be designed with the help of board-level simulators, where the supply network is an integral part of the output coupling network itself.)Note that plenty of CPUs, SoCs, etc. operate at core frequencies much higher (up to some GHz); these contain internal bypassing, on the die itself, and on the interposer board if applicable, so that the PCB doesn't need to handle frequencies quite so high. They do tend to require quite low voltages, and high currents (e.g., the 0.9 and upwards of 100A that desktop/server CPUs and GPUs require!), which makes bypassing and layout a challenge even with the bandwidth requirement relaxed as it is.3. Design the PDN (power distribution network). A power rail is a chain or tree (or other graph) of connecting traces, or pours, and branches. Every branch draws a load current, and has an impedance. Note that some loads might merely have zero DC current (e.g., bypass caps), that's fine.Note that loads themselves have some impedance. Chips with onboard bypass are an example, having a capacitive characteristic at high frequencies. Many devices have a resistive characteristic also (e.g., digital logic, current draw ~proportional to supply voltage), but many also have a constant-current characteristic (e.g., many analog circuits, op-amps and such). Switching supplies have a negative resistance characteristic, at low frequencies (i.e., as supply voltage increases, load current decreases -- a switching regulator only needs to draw ~constant power from its supply).The PDN needs to be designed so that:- The impedance from #1- Over the frequency range from #2- is never exceeded, at any given device's supply pin(s), by the network designed in #34. Lay out the PDN, and go back-and-forth with step 3 to ensure the model and layout match in characteristics. (These two can be done in either order, and repeated any number of times for accuracy.)This is probably uselessly high level, but it is a reasonably complete answer to the question. It is not a subject which can be resolved at a single point, or component or load; it is system wide, and so the whole system must be considered.For a beginner, following these steps will not be easy at all, and it will be better to follow conventional wisdom. The above may perhaps give some hints as to testing ones' system -- measuring the impedance at points (say by injecting an AC current into a node, and measuring the resulting AC voltage drop), and if that impedance is too high at some frequency, then adjusting component types or values until it works.Tim

author: EEVblog
author_rank: Unknown
timestamp: June 27, 2020, 04:04:44 am
content: 5. Actually test it. And not just for device functionality, but actual impedance characteristics over frequency.And it wouldn't be the first time that even if you went to all that effort, you still (bad)luck upon an obscure operational mode that causes LC resonance at some point and your circuit comes-a-gutsa.

author: Bud
author_rank: Super Contributor
timestamp: June 27, 2020, 05:35:40 am
content: I often approach it from practical perspective - connect the spectrum analyzer to the point of interest, and try single or a combination of capacitors while observing the screen, for the best suppression of unwanted signals over a frequency range of interest. This way you see the real effect. Capacitor values depend on the frequency range, the higher frequency is the smaller the decoupling capacitor value should be. I used decoupling capacitors as small as 10pF at frequencies of hundreds of MHz in RF circuits or in switching power supplies.

author: schratterulrich
author_rank: Regular Contributor
timestamp: June 27, 2020, 10:38:30 am
content: I want to show a practical example:I have measured the PDN of a simple 2-layer board with a VNA and simulated it with my tool(https://leiterplatte.jimdo.com/pdn-sim/):I have carried out S21 measurements with PORT1 connected to an unmounted Capacitor and PORT2 to another unmounted Capacitor.The impedance can be calculated by Zdut = 25 x S21/(1-S21)The bare board:Measurement vs SimulationUp to 200 MHz it's a nearly perfect capacitor with ~55 pF. Above 200 MHz transmission line effects are presentThe bare board with just the bulk capacitor (470 µF 0.5 Ohm ESR and a surprisingly low ESL of 3 nH if the measurements are correct)Now there is a lower base impedance up to 10 MHz.The dip in the VNA measurement at 25 kHz is due to the lack of a full SOL calibration.Adding a 100nF Cap ( 85nF 37mOhm 700pH)You can see the dip at 7 MHz. This is not as much useful. But more important is, that the impedance above that frequency has lowered, too. To effectively <5nH at the position of measurementAdding a 10uF Cap( 10uF 5mOhm 900pH)This cap has lowered the impedance quiet much over a broad range.Adding another 3 100 nF CapsThis has reduced the effective inductance at single point at high frequencies to about 2.3 nH!And the micro uses another trick to get lower impedance at high frequencies: It has a powerpin-pair at each side of the package. So this will reduce the inductance further, if there is a 100 nF Cap on each side ACAP.

author: David Hess
author_rank: Super Contributor
timestamp: June 28, 2020, 12:42:57 am
content: Quote from: EEVblog on June 27, 2020, 02:22:51 amThe formula applies exactly where the existing rules of thumb are acceptable which is what the original question asked about. At higher frequencies, transmission line effects come into play but the same concept can be applied.Do the calculation for a practical test like CMOS quad gates or bus buffers/transceivers driving specified capacitive loads and then build a lumped circuit to test it; the results will be just as I described. Or do it for a MOSFET gate driver in a switching circuit which is probably more relevant to most here and find out why they have such large decoupling requirements, which often get ignored.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: June 28, 2020, 01:50:30 pm
content: Because nobody mentioned buffer capacitors I'll add my own 2 cents.The decoupling has to be done over any applicable frequency range, down to low frequencies.If the power supply is on another board, connected with (long) wires, then usually buffer capacitors are also recommended.The size for these buffer capacitors is also very dependent on the circuitry on the board.The main reason for the buffer capacitors is that the power supply leads have (some) inductance, and therefore no instant current change.If you switch for example a small light bulb with a transistor then during the switch-on event the voltage may dip enough to upset other circuitry.For small circuits usually 10uF to 100uF is enough but for high current stuff such as motor drivers multiple thousands of uF may be needed.If you look at the datasheet for for example the LM3886 audio amplifier, they recommend an extra 220uF near the chip, regardless of the main bulk capacitors in the power supply. Without these capacitors (or too small) you have a big chance of instabilities and oscillation.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 28, 2020, 02:38:41 pm
content: Incidentally, note the one thing you areNOTdoing -- energy storage.If we could reduce supply impedance without storing any energy at all, we would!Indeed, we often do. Linear regulators have arbitrarily high performance, from the old LM317 and relatives (pretty slow, good enough for audio, say), all the way up to "RF" rated parts (which have especially high PSRR and low Zo up into the MHz). Linear regulators of course don't store energy at all, they merely control power. The price we pay is the dissipation of some of that power.Fast switching regulators store a minimum of energy; with a control-loop response time in the 100s of us, their load and supply currents track pretty quickly. There's very little hold-up time, in case of power interruption, say. Even an offline supply stores only enough energy to keep alive between mains cycles.But in the power supply, the key is this: we want a low supply impedance. That means, for a given change in load current, the supply voltage changes little. Energy stored or released in a capacitor is proportional to the voltage change (exactly, E = C Vcc ΔV). Indeed, you might even say we are actively trying to minimize energy storage; it doesn't do anything for us, just makes our supplies come up slower!If we could get bypass capacitors that have maximum capacitance around quiescent supply voltage, and nearly zero everywhere else, we would actually prefer that. This means minimal energy storage starting from zero, and minimum impedance around the operating point.It sounds imaginary, but such a component is actually possible -- an electret is a dielectric with a built-in electric field (in much the same way that a magnet has a built-in magnetic field). If we use a dielectric that saturates easily (i.e., as field increases past a point, capacitance decreases sharply), we can control where that saturation occurs, and in fact shift the maximum-capacitance point to the middle of our nominal range.They are even available! TDK Cera-Link capacitors are made for industrial inverter application, so, with a built-in field corresponding to about 400V.An interesting consequence of this -- what energy it does store, is mainly stored around some voltage, rather than around zero. Energy is voltage times charge, so if we're putting in the same amount of charge, but doing it around some nonzero voltage, suddenly all that charge stores a ton of energy!And actually, we're putting in up to double the charge -- effectively, it's like charging a capacitor starting from a negative voltage, so we can go through negative saturation, to zero field, to positive saturation, in a single swing. Whereas with a regular capacitor, we'd most often start from zero, using only the positive charge area.We're still not concerned about energy storage for bypassing purposes; but in essence, the capacitor is that much more effective, so we can use less of it. And if we are storing energy, they have much higher energy density than anything else in its class. Which helps, as they aren't cheap...Tim