Hierarchical Design, some nets are not connected - Page 1
Forum section: electronics / general

author: hitech95
author_rank: Regular Contributor
timestamp: December 27, 2020, 03:21:32 pm
content: Hi,I've started designing a new PCB, this time the project is a bit more complicated than usual,Having a lot of busses, and connector and channels I've started digging into Hierarchical Design.Now I'm facing issues even with the simplest desing.Lets say I have 3 connectors with one I2S bus each (MCLK, BCLK, WS, SD)Now lets say I have another connector that receive the three busses.My project structure is:OverviewConnector_MUXConnector_AFE1Connector_AFE2Connector_AFE3The Connector_AFEX files have a Harnes connector called BUS_I2S_AFE. (The three inputs are basically the same thing)The Connector_MUX file have the three Harnes (BUS_I2S_AFE) as inputs but with three different harness ports.When I import the changes to the PCB not all the nets are connected, some headers have pins with correct net names, some other time they don't.The issue is that this issue is creating me a lot of troubleshooting non-sensese. Especially when each import changes the netlist even if the schematic is unchanged.What I'm I doing wrong?In the atachments there is my simplified project.

author: PlainName
author_rank: Super Contributor
timestamp: December 27, 2020, 04:58:09 pm
content: I am not seeing your problem. Maybe I'm not looking for the right thing, but an update to the PCB results in the three AFEx connectors having the same connections each time. The kind of problem you note might be caused by having global scope for net connections, but the project options look OK. Presumably your non-simple project has the same settings.I note there are issues with missing connections in the schematic - could they be affecting things?

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: December 27, 2020, 07:01:09 pm
content: Yeah, I am not seeing any issue either. Ratsnest looks correct. Can you give an example of a pin that has the missing connection or specific nets giving you issues?

author: hitech95
author_rank: Regular Contributor
timestamp: December 27, 2020, 08:56:57 pm
content: This is the same project with the correct connectors, and some more ports, this one is failing (Randomly).In this design I only changed AFE1 and AFE2, AFE3 is the same but it is also failing. Afe 2 Intead is correcly created.

author: hitech95
author_rank: Regular Contributor
timestamp: December 31, 2020, 12:51:48 am
content: No,I'm still tring to understand how to use this functionStarting to feel dumb.For my protype board I will have to go with flat design at this point...It will be a mess:

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: January 04, 2021, 02:34:19 pm
content: I need specifics give me pins and nets to look at, and show me the error.

author: hitech95
author_rank: Regular Contributor
timestamp: January 17, 2021, 06:04:13 pm
content: On my previous post there is the project with the issue.As you can see P3 and P1 are not connected to J3 and J1.J2 and J1 sould also connected to J3.P4 should connect to J3.You can find the details in the schematics.Master connector:Slave conector 3x:Block diagram:

author: ajb
author_rank: Super Contributor
timestamp: January 21, 2021, 05:12:24 am
content: I took a look at the project, and a few things:When I first open your project, I see that P2 is connected to J2, but J3 and P1-P4 do not show any signal connections (only power).When I try to update the PCB from schematic, I get "Cannot match pads with new footprint in component" for J1-3, because the PCB has different versions of those connectors than referenced in the project. Are you seeing those errors as well? This seems to cause the "Add Net" operations to fail. If I just delete those connectors from Sch, then P1 and P3 get the proper connectivity to P4 (P2 does not) with no other changes.The reason P2 doesn't get its connectivity is that in Connector_AFE2 you have the I2S harness break out into nets that you have manually labeled "AFE[1_MCLK" etc. This is a problem because of the way that AD resolves net names when it compiles the project. Altium will automatically name the nets that go into harnesses HarnessName_HarnessSignalName, so if you were to delete those net labels in Connector_AFE1 and Connector_AFE2 and just use wires for connecting within the sheet, you would get one net named "AFE1_MCLK" and another net named "AFE2_MCLK" automatically, because the harnesses will take their names from the sheet entries in the top level sheet. But your net labels directly collide with these names, and this clearly prevents Altium from resolving the netlist correctly for some reason. This is a little strange because you can name those nets basically anything else--you can even name all of those nets "MCLK", "BCLK" etc on each sheet--as long as it doesn't match one of the names that Altium autogenerates and everything will resolve correctly. I suspect that at some point in the net resolution process Altium does a check to see if a net already has a prefix that matches a harness and then skips the prefixing. If you were to name the AFE2 MCLK signal "FOO" via a net label it will end up getting resolved to "AFE2_MCLK", but if you name it "AFE1_FOO" it will remain "AFE1_FOO". I guess this behavior sort of makes sense in most cases, especially in designs with more hierarchical layers where you don't want a net name to end up as a long string of prefixes, you just happened to create a situation where that makes it blow up.What makes this even weirder is that once you get the correct connectivity by changing the net names to something else, you can change them back and altium will simply rename the net and otherwise compile the project and update the PCB with no complaint, although this leaves you with duplicate net names. It's apparently only when initially building the net list that it needs these precautions.So the solution is to fix those net labels. Either use wires instead of labels (remember you can use harnesses within a sheet, which may work nicely here for you given the way the signals land on the connectors), or use net names that do not start with the name of one of your harnesses. If you really only need one I2S instance in each of the sheets then you can just name them "MCLK" or whatever, but I notice that you have all three of the AFE1 and AFE2 and WI harness signals on each of the three card connectors, which will mean you need to differentiate them some way, but NOT by using the harness names directly as prefixes.

author: hitech95
author_rank: Regular Contributor
timestamp: January 23, 2021, 11:01:27 pm
content: Quote from: ajb on January 21, 2021, 05:12:24 amYes, my schematic import generate that.Quote from: ajb on January 21, 2021, 05:12:24 amI actually don't get the error: "Cannot match pads with new footprint in component", I only get the "footprint not found" and then if fails to add the nets.Quote from: ajb on January 21, 2021, 05:12:24 amP2 and J2 is (for me) the only correctly connected connetor.This is my first time using the hierarchical design.My goal is that the "PCIe" style connector have a fixed pinout.The one defined in each Connector_AFEX and Connector_Main files.That said depending of which file I'm creating I have to connect some of thoose pins.According to the Altium DOC, net names are only used inside the sheet.From what you are saing looks like I cannot use the same names on multiple files.And this simply make no sense to use the hierarchical design all toghether.A solution might be to use AFE instead of AFE. Could this be a good practice?

author: ajb
author_rank: Super Contributor
timestamp: January 24, 2021, 08:17:47 am
content: Quote from: hitech95 on January 23, 2021, 11:01:27 pmNo, you CAN have the same net names in different sheets, that's not the problem. The problem is that your net labels just happen to collide with the net names that altium auto generates from the harness, and that prevents altium from being able to resolve the net list initially. This is clearly a bug in altium, or at least an area where the net resolution system has some gaps. You just can't have a signal called "MCLK" in a harness called "AFE1" and then have a net labeled "AFE1_MCLK".QuoteIf you keep the harness ports labeled AFE and switched the net labels to AFE that should work. Changing both would presumably give you the same trouble you have now. Getting rid of the net labels and using wires would fix it as well. Using a ton of net labels to create connectivity within a sheet makes it hard to understand, so has the benefit of arguably improving the schematic as a bonus.

author: hitech95
author_rank: Regular Contributor
timestamp: January 24, 2021, 01:28:35 pm
content: Ok, looks like that now the connectors are connected but the address selection resistors are still not connected. Are the busses global?This also happends on the in sheed net class PRSNT#, when compiling it says that nets are duplicates.Thi snet is only inside child sheets, it does not have ports or harnesses.Why the hell are the nets in some way global?This is starting to make even less sense.Removing net names and only using wires is a no go. the project you have is really simplified, in the original design all those nets are connected, there are net classes, directives, etc.Each sheet have distinct blocks with descriptions.looks like that altium is not appling the suffixes on the child nets namesThe only way is to enable sheet number, but having rooms name as prefix/postfix would be lot better.

author: ajb
author_rank: Super Contributor
timestamp: January 25, 2021, 04:58:59 pm
content: I can't really see the connectivity issues with the PRSNT nets because of the footprint errors, but I would guess, at least in the test project, that it's because those nets go to ports without any further connection, and are again ending up with duplicate names during the initial netlist creation which causes Altium to give up. However, if this is a problem in your larger project, then I have no idea because there's more going on in that project and no one can see it unless the have access to that project. But as a general rule, solve the footprint errors first, then if you still have problems try adjusting the names of the ports, nets, and harnesses, and be mindful of the limitations I mentioned previously. Any net labels that use a scheme that fits into the patterns that Altium uses for creating net names in harnesses is liable to run into the same problems.

author: hitech95
author_rank: Regular Contributor
timestamp: February 03, 2021, 04:15:27 pm
content: I have attacched another example project with the issue in details.The file "ReDriver" is an example of the issue I'm facing. The nets are only connected on one side.The annoing thing is that the connetor have a specific pinout and in reality it is another child sheet.For what I can understand is that the issue is "Duplicate Nets Label" on two different child files.AFIK Altium should add SheetSyblo prefix to the nets to prevent those issues.What does you suggest?The "fake" redriver circuit:The broken harness:

author: frogblender
author_rank: Regular Contributor
timestamp: June 03, 2021, 04:23:55 am
content: Quote from: hitech95 on February 03, 2021, 04:15:27 pmHi hitech95... did you ever solve the ""Duplicate Nets Label" on two different child files." problem???I have the exact same issue.