Any good recommendation for a Quad SPI Slave-capable microcontroller? - Page 1
Forum section: electronics / general

author: benSTmax
author_rank: Regular Contributor
timestamp: April 25, 2020, 04:09:26 pm
content: I am trying to interface a PicoRV32 SoC in FPGA with a host computer and have way more bandwidth than a plain UART for transferring large amounts of data (a few MBs)Since my FPGA I/Os are a bit of a premium (not many available), I was looking to interface the FPGA to the PC via a reduced I/O interface which in the same time offers a relatively good bandwidth too (more than 5MB/sec).While looking at the possible options, I realized the Quad SPI might be a good fit.The FPGA SoC would act as a Quad SPI Master connected to a microcontroller (acting as a Quad SPI Slave) which in turn bridges the data over USB-HS or Ethernet. In this way, the microcontroller would behave like a bridge to the FPGA SoC.For this purpose, I was looking for microcontrollers with Slave Quad SPI capabilities.I bumped into Infineon's XMC4800 and TI's TM4C1294 but I don't know if their Quad SPI works ok in Slave mode (I used the Tiva in the past but not for its Quad SPI, while with the Infineon micros I have no prior experience). I also found there are some serious issues with the Quad SPI peripheral of TI's micro (TI version of the Quad SPI is called QSSI and it seems the errata shows some potential serious issues when running the QSSI in slave mode).I would appreciate any recommendation for other microcontrollers having such a capability or if anyone can share some past experience working with Quad SPI Slave on microcontrollers. Thank you

author: mark03
author_rank: Frequent Contributor
timestamp: April 27, 2020, 05:02:31 pm
content: A couple other possibilities you might look into, especially if an 8-bit parallel interface is possible:1) The camera interface on some MCUs has a generic mode where it just strobes parallel data into a buffer without sync/framing signals.2) On most modern MCUs you can set up a GPIO DMA to trigger on an external strobe. This also wants to be at least eight bits wide, I think, because most DMA engines won't back nybbles into bytes for you.

author: Scrts
author_rank: Frequent Contributor
timestamp: April 27, 2020, 06:32:01 pm
content: Maybe consider something specialized?E.g. Cypress FX2 or FX3? FTDI FT245 or FT313?Other than that, I've used parallel data ports, that are available in Atmel/Microchip or STM32 devices. The FPGA acts as SRAM and Microcontroller just pulls data providing data and address. Many pins, but super fast and DMA capable.

author: AloyseTech
author_rank: Regular Contributor
timestamp: April 27, 2020, 06:33:57 pm
content: The Atmel/Microchip SAMS70 has high-speed USB and QSPI or automatic parallel input capture mode capabilities.

author: capt bullshot
author_rank: Super Contributor
timestamp: April 27, 2020, 07:38:15 pm
content: Stay away from Infineon XMC series, they're a dead end and might disappear without notice.Haven't seen a uC yet that has a QSPI slave, normally the uC is the master end and you're supposed to connect e.g. a QSPI flash chip here.

author: ajb
author_rank: Super Contributor
timestamp: April 27, 2020, 07:44:03 pm
content: Is there a reason you want the FPGA to control the interface instead of the MCU? Letting the MCU control the interface opens up a lot more possibilities, and it should be easier to overcome any limitations in the peripheral implementation on the FPGA side rather than the MCU side of the equation. An eight bit bus with a 'data to be read' signal from the FPGA and a read clock/strobe signal only needs four more pins than QSPI but should be dead easy to implement using a parallel memory interface on the MCU, and even starting from scratch the FPGA side should be pretty straightforward.

author: splin
author_rank: Frequent Contributor
timestamp: April 27, 2020, 08:53:38 pm
content: The STM32H750 supports 150Mb/s SPI in slave mode - 18.75MB/s. If that isn't enough interleave bytes over 2 or more SPI's.Other high speed, up to 125Mb/s, serial interfaces you could use include I2S, SAI and SDIO (MMC in stream read mode, data width = 1 bit, may be the most appropriate) but may be more complicated protocol wise,Doesn't look like the QUAD SPI i/f supports slave mode.It's quite cheap, < $4 @ 1K (Farnell), has Ethernet and high speed USB i/fs and is fast.

author: splin
author_rank: Frequent Contributor
timestamp: April 27, 2020, 10:15:02 pm
content: Also look at NXP's LPC43xx range. They all have an SGPIO (serial GPIO) peripheral which should be perfect for your application. It's a highly configurable serial/parallel interface module with clocks/counters etc. to allow various types of serial interfaces to be emulated or proprietry interfaces to be implemented.There is a training video here:https://www.nxp.com/video/configurable-and-virtual-peripherals-sgpio-and-sct:PERIPHERALS-SGPIO-AND-SCTI don't believe they've implemented it on more recent MCUs which is a shame - perhaps it used too much silicon or maybe was too intimidating to developers used to the usual USARTs, SPI etc. peripherals.What data rate do you need? You said 'more than 5MB/s' - does that mean 5MB/s will suffice in which case there are plenty of devices with enough throughput using 2 or more USARTs or SPIs in parallel?

author: hans
author_rank: Super Contributor
timestamp: April 28, 2020, 08:34:12 am
content: Most QSPI peripherals on microcontrollers support mapping the address space of the QSPI device(s) to the CPU memory space. This allows QSPI for external FLASH, S(D)RAM, etc. In turn, this also means that these QSPI peripherals are typically focused on master-only use.I think you can probably use any microcontroller with such a QSPI interface, if you can spare the buffering in the FPGA such that it acts like a QSPI slave, and the uC as a QSPI master.

author: asmi
author_rank: Super Contributor
timestamp: April 28, 2020, 03:46:13 pm
content: The real question is why do you need an MCU if you already have FPGA? Just pick an FPGA that has enough resources to accommodate everything you need from MCU, and call it a day.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 28, 2020, 04:34:10 pm
content: Just a thought - your need is to transfer data at 5MB/s (or a tad more) from some FPGA to a PC.How many IOs would you actually have available? QSPI would require a strict minimum of 5 signals, preferrably 6 with a /CS signal, and this, only for one-way communication (if that's what you are after). For two-way comm, you'll need 4 more lines - you could also change direction dynamically, but QSPI per se doesn't support that, that would be a bit cumbersome. So for 2-way, that would be up to 10 lines.With just a couple more, you could use some FTDI chip like the FT232H instead of having to use an extra MCU, write software for it, etc. The 245 asynchronous mode would get you over 5MB/s with no issue, and that comes with certified drivers. I know it's popular to bash FTDI, but it would just get you there in no time.If you still don't have enough IOs foir the 245 mode, you could use the FT1248 mode (if IIRC) of the FT232H which can be used as some sort of SPI with a bus width of 1,2,4, or 8. In this mode, you can still get transfer rates up to over 20MB/s.And an FT232H is much cheaper than one of those beefy MCUs (like the TM4C1294) you were thinking about.Just my 2 cents.

author: benSTmax
author_rank: Regular Contributor
timestamp: April 29, 2020, 10:53:11 am
content: Thank you all for your suggestions. I appreciate a lot all your feedbackThe FPGA board in question is theiCEBreaker FPGAhttps://www.crowdsupply.com/1bitsquared/icebreaker-fpgahttps://github.com/icebreaker-fpga/icebreakerThis board has only 39 I/Os. It might seem like a lot but here's how they are assigned:4 pins for config (SDI, SDO, SCK, CSB). Either loading config from on board FLASH chip or provided through the FTDI chip with direct SRAM config2 extra GPIO pins for QSPI. Together with the config pins, allows storage of additional data in the FLASH chip, and high speed QSPI DDR access. For example picosoc firmware.3 PINs for RGB LED (pin header)2 LEDs (one on output-only PLL pin)1 Clock pin (on PLL GBIN)1 UART Rx Pin via FTDI1 UART Tx Pin via FTDI1 Push Button16 PINs on dual PMOD8 PINs on single PMOD / snap-off sectionNow, I don't have anything against using the FTDI chip. In fact, the UART pins along with the 8 PMOD pins in the snap-off section can be used as an 8-bit data bus with the FTDI chip working in asynchronous mode. This is plan B in my case.The reminder of the I/Os are needed for a couple of ADCs (sampling at a minimum of 1Msps/16bit per sample), audio and misc. The bare minimum ADC data stream is at 4MB/sec (2 x ADCs, each running at 1Msps/16 bits per sample)The reason why I was asking specifically about the QSPI Slave mode in the microcontroller has a number of reasons:I can re-use the QSPI bus connecting the SPI NOR flash. Of course, to connect with the microcontroller I will use a different CS line. Minimal additions in the FPGA fabricThe PicoSoC already has a QSPI Master implementation - this is needed for the RISC-V soft core to fetch its firmware and non-volatile storage. This allows me to reuse the same QSPI Master controllerA microcontroller behaving like an emulated SPI flash has a number of benefits. I can use the same read/write SPI NOR flash routines to transfer ADC data from the FPGA. The added bonus would be an option to execute code from the RAM region of the microcontroller (Since the PicoSoC's RISC-V fetches code from the SPI NOR flash to execute, it could do the same by fetching code from an emulated SPI flash running on the microcontrollerAll the above options might be nice to have but if it proves too cumbersome, I might fall-back to a FTDI async streaming solution or external memory interface/camera option.I am going to go through all the very useful information you provided me and explore other options I wasn't aware before. Thanks again

author: ebclr
author_rank: Super Contributor
timestamp: April 29, 2020, 01:25:49 pm
content: CH552 will be a cheap option, You can handle a lot of things directly to USB, And will also give you some extra i/os to be used,

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 29, 2020, 01:38:58 pm
content: A CH552 will never get you 5MB/s.Regarding benSTmax's answer:with this additional info, I understand your point for QSPI, especially if you intend on reusing QSPI for other uses.I also understand the very limited number of IOs if you're going to use an iCEBreaker board. But I'm just thinking... is this board a hard requirement? Because with the VERY limited number of IOs (which is restricting you already and will have no room for further expansion unless as you said, you reuse QSPI, but even so, that'll be limited to the extra number of /CS pins you can get out of it. Could you not consider using another board with more IOs, or designing your own?

author: OwO
author_rank: Super Contributor
timestamp: April 29, 2020, 03:37:23 pm
content: http://jorisvr.nl/article/usb-serialUse this + USB3343. I can post more details if needed.

author: benSTmax
author_rank: Regular Contributor
timestamp: April 29, 2020, 06:01:22 pm
content: I am trying to create some add-ons for the iCEBreaker board. Therefore, I am aiming to use this exact board.If it wasn't for the I/O limitation, I would have used a simple parallel-style port between the FPGA and a bridge chip (FTDI, FX2/3 or microcontroller).

author: asmi
author_rank: Super Contributor
timestamp: May 01, 2020, 01:04:18 pm
content: Quote from: benSTmax on April 29, 2020, 06:01:22 pmIn this case you can put a second FPGA on your addon, and connect it to the main board via LVDS. If my memory serves me, these FPGAs can go up to 600 Mbps per LVDS lane, and a single lane requires only 2 pins per direction (+2 ref clock pins for a link).

author: klmbk
author_rank: Contributor
timestamp: May 06, 2020, 09:26:45 pm
content: The ESP32 seems to support SPI slave mode operation:https://docs.espressif.com/projects/esp-idf/en/stable/api-reference/peripherals/spi_slave.htmlQSPI isn't mentioned there but the datasheet discusses the SPI/SDIO slave controller on p. 27:https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdfQuoteThis could imply QSPI operation as it's similar to SDIO, but I'm actually curious about SDIO as well. Anyone knows other MCUs that can act as an SDIO slave device? Thanks.