7SEGMENT display with MAX7219 - Page 1
Forum section: electronics / projects

author: alireza7
author_rank: Regular Contributor
timestamp: September 21, 2017, 05:23:03 pm
content: hii have 21 8digit 7SEGMENT dispalay with MAX7219 driverthe interface of MAX7219 is spi.these 21 modules can be connected cascading (as shown in attached picture ) and all of them can be driven just by 3 signal : cs clk data. cs and clk is comman among them and the data_out of each module is connected to the next module data_in,my problem is when i connect 10 of these all of them , they work correctly but when i connect more of them , problems arise and the 11'nth display and more do not work correctly .i checked signal integrity with oscilloscope and i found out ringing in signal , then i tried some termination resistors but i couldn't solve the problem.my driver is 74f245d which is a buffer.i slow down the speed of the spi as i could but don't you think the rise and fall time of my driver cause ringing and problems with signal integrity?do you have any suggestion ?

author: David Hess
author_rank: Super Contributor
timestamp: September 21, 2017, 07:09:43 pm
content: Quote from: alireza7 on September 21, 2017, 05:23:03 pmThe rise and fall time are too fast for the transmission line environment and termination.You might try replacing the 74F245 with a slower 74LS245 or 74HC245/74HCT245. Beyond that, I would use some type of filter at the output of the '245 drivers to increase the rise and fall times unless you want to fix the layout.The layout and circuit should have been designed to operate as a transmission line to start with.

author: matseng
author_rank: Frequent Contributor
timestamp: September 21, 2017, 07:41:42 pm
content: There are two major issues with daisychaining many 7219's.1) The load on the CLK and CS/LOAD lines that are paralleled to all the ICs can make the logic levels too low and the rise/fall times to fall out of spec.2) The combined propagation delays between DATA-IN and DATA-OUT on each chip will eventually make the data arrive too late on the last chip relative to the CLK signal that is not delayed at each chip.

author: Ian.M
author_rank: Super Contributor
timestamp: September 21, 2017, 07:56:05 pm
content: Quote from: matseng on September 21, 2017, 07:41:42 pmNot quite. Because DATA-OUT taps off Q from the final flipflop of the internal 16 bit shift register, its resynchronised to CLK in each device, so the propagation delays with respect to CLK do not accumulate along the chain.

author: Benta
author_rank: Super Contributor
timestamp: September 21, 2017, 08:41:06 pm
content: And check your supply decoupling. And that your power/ground lines are routed sensibly.

author: alireza7
author_rank: Regular Contributor
timestamp: September 21, 2017, 10:53:28 pm
content: i think Ian.m is right, as data sheet says :Serial-Data Output. The data into DIN is valid at DOUT 16.5 clock cycles later. This pin is usedto daisy-chain several MAX7219/MAX7221’s and is never high-impedance.so at 17'nth clock cycle data is available for (n+1)'th module from n'th module and here the only thing is delay between (n+1)'th module clk and n'th module clk and it is negligible although this 0.5 (17-16.5) clock cycle ensure that this delay do not cause any problem .if i am wrong i will be appreciated if some one explain my misunderstanding.

author: Ian.M
author_rank: Super Contributor
timestamp: September 22, 2017, 12:45:18 am
content: The signal integrity of /CS and CLK cant be too bad if the first few displays are getting the correct data.I'd suspect ground offset along the daisy-chain due to the LED return current in the 0V wire(s). Run a 12 or 14 AWG bare copper wire ground busbar past all the displays and hook each one to it with a *short* length of hookup wire soldered to the busbar and a ground point on the board and the problem *may* go away.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: September 22, 2017, 09:06:16 am
content: I agree with Ian.M, I think the ground for last few modules has higher potentials

author: alireza7
author_rank: Regular Contributor
timestamp: September 23, 2017, 04:36:13 pm
content: Quote from: David Hess on September 21, 2017, 07:09:43 pmyou said"The layout and circuit should have been designed to operate as a transmission line to start with."can you please detailing about such design?or can you introduce me any book,website,tutorial,.etc. ?

author: David Hess
author_rank: Super Contributor
timestamp: September 23, 2017, 05:25:00 pm
content: Quote from: alireza7 on September 23, 2017, 04:36:13 pmFor simple designs, it may be sufficient to minimize the loop area between the signal and its ground return. Just routing them adjacent may be enough. If they are far apart, then the added inductance will become a serious problem.An AC termination made from a series capacitor and resistor at the end of each clock line to ground on each board might fix the problem.But as Ian.M pointed out, you may be having a problem with the LED ground current sharing the signal ground.