simple llc converter prototype resistive load ok, but oscillation with rectifier - Page 1
Forum section: electronics / projects

author: julian1
author_rank: Frequent Contributor
timestamp: May 24, 2022, 01:27:08 am
content: Consider this simple low-voltage DC-DC full-bridge llc converter prototype. using a mcu peripheral timer driving two half bridge gate drivers. cap is 1uF, resonant inductor is 3.3uH, transformer windings are 18uH.When driving a purely resistive load (halogen bulb) directly from the secondary up to 30W, the traces appear good. light blue + yellow traces are fet gates, The pink trace is one node of the primary, and the dark blue trace is the secondary trace which is gnd referenced by the scope gnd clip.but after connecting the output section - consisting of rectifier + reservoir caps + low pass filtering - an oscillation problem appears on the primary (and secondary).- the oscillation issue, exists regardless of whether the output is loaded (eg halogen bulb) or open.- problem exists - with 10uF/50V MLCC. or 220uF aluminium electrolytics for resevoir caps- problem exists when inductor of low-pass LC filters are shorted.The rectifier diodes are fast schottky 4A SMC MBRS4201.The resevoir caps are unfortunately bodged through-hole (mlcc, or electrolytic) - and have long leads - so lead inductance is suspect. But I still find it odd that this might affect the trace of the primary winding.Any thoughts?

author: TimNJ
author_rank: Super Contributor
timestamp: May 24, 2022, 02:26:49 am
content: Well done on the waveforms. Primary side waveforms are indicative of operation above the resonant frequency of the LLC tank. Basically the transformer is still energized when the next switching cycle is forced. This results in hard commutation of the output rectifiers because the conducting diode abruptly gets reversed biased while it is still delivering current to the load. Thus, you get ringing due to non ZCS condition.Not that I understand the control algorithms well (or at all), but how are you controlling (i.e. what is dictating) the switching frequency?

author: julian1
author_rank: Frequent Contributor
timestamp: May 24, 2022, 05:00:33 am
content: Quote from: TimNJ on May 24, 2022, 02:26:49 amOk that sounds reasonable and makes sense.I believed it was possible to stay in the inductive region (above resonant freq around 35kHz) freely, for control over power transfer, with the only tradeoff being efficiency due to no ZVS.And it appears to work ok (everything stays cool, no oscillations), so long as there not a rectifier on the secondary.In fact the one case/condition I have not tested - is operation right at resonant frequency/full power - due to limitations in source/load . So I should probably test that, and see if the rectifier behaves.The design at the moment is running open loop. So I just play-around with setting freqency, and deadtime, over usart.I did try running at resonant frequency, with high (eg. 90% deadtime), but the waveform was awful. But that was with hard switching and no free-wheeling one of the fets (like psfb).

author: strawberry
author_rank: Super Contributor
timestamp: May 24, 2022, 06:00:46 am
content: when run above resonance it is no longer resonant LLC but regular hard switching converter(where it operates at no load/standby)need fast ZCS detector to keep as close as possible to resonance (unreliable detection will result in ringing and transistor failure)

author: uer166
author_rank: Super Contributor
timestamp: May 24, 2022, 06:08:25 am
content: It was my understanding that you always run an LLC primary well above resonance (in the inductive region), and do control via frequency. The idea is the higher frequency, the farther away you are from Fres -> less gain, and vice versa.

author: julian1
author_rank: Frequent Contributor
timestamp: May 24, 2022, 07:42:06 am
content: I changed/bodged the rectifier from centre-tap / dual supply to a single output.Not sure how to interpret the result, but it appears to have cleared up the parasitic oscillation. Maybe the problem is/was something in the way the diodes are loaded, or slightly unbalanced currents in the windings.

author: TimNJ
author_rank: Super Contributor
timestamp: May 24, 2022, 03:18:57 pm
content: Yes, you generally want to ensure operation either at resonance or above resonance, due to the inverted control law below resonance. Though, new LLC control ICs can deal with this (sort of) to avoid blowing MOSFETs.You can control by frequency directly (using an oscillator) or you can control by 'hysteric control' whereby the switch timing is based on current state of the sensed resonant voltage (ususally across the resonant cap).Frequency/oscillator control:https://www.nxp.com/docs/en/data-sheet/TEA1716T.pdfHysteretic control:https://www.nxp.com/docs/en/data-sheet/TEA2016AAT.pdfThe idea in any of these techniques is that the frequency adapts to the output power by maintaining (close) to ZVS for all conditions. As the load increases, the Q of the tank decreases, which results in a slight downward shift in operating frequency, as the resonant period becomes longer.I would also check that your transformer turns ratio is logical for the output voltage you are trying to regulate to. Forcing a conversion ratio which does not make sense with transformer can result in working away from resonant frequency too much. Though, I don't see the optocoupler populated? Is this running open-loop?

author: julian1
author_rank: Frequent Contributor
timestamp: May 26, 2022, 12:36:30 am
content: Yes, the design at the moment is running open loop, or human-in-loop. So I just play-around with setting freqency, and deadtime, over usart. It behaves well, with good control over power transfer across the inductive freq region.

author: julian1
author_rank: Frequent Contributor
timestamp: August 18, 2022, 10:33:46 pm
content: In case anyone else stumbles into the same issue where a centre-tap /dual rail output is needed. The parasitic resonance was fixed with a series RC snubber after the secondary but before the rectifier. This follows Linear Tech AN29 notes on DC/DC converters (Fig 1, or Fig 4 etc).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 19, 2022, 06:51:58 am
content: Also, "hybrid hysteretic" control:https://www.ti.com/lit/ds/symlink/ucc256404.pdfBasics for most types seem to be either doing a VCO, or a comparator on the resonant cap voltage (or some sampling of it), or both (basically, doing a VCO with current source/sink into a capacitor, but also feeding some resonant cap current into it with a cap divider).At a glance, I don't know what the waveforms are measuring. In general, the output will ring when commutation occurs slowly: current falls to zero, diode recovery occurs (or equivalent from relatively abrupt schottky capacitance), ringing ensues, waveform swings down and delivers another gulp of current, etc.Likewise, primary side rings whenever it's open circuit (free ringdown), or hard switching (loop inductance * inverter capacitance). Neither of which should happen in normal operation, except ringdown at the end of a tone burst, when burst mode (at light load or current limiting) is employed.Specifically, it's aprotective featureto avoid hard switching, except for a few cycles during startup, usually with a brief delay and auto-restart, or a fault-out, function when it occurs otherwise. Hard switching means insufficient or wrong phase of circulating current, very high peak switching currents, and high inverter dissipation.I absolutely don't recommend doing it (like, full deal, at scale) with an MCU, as you'll have a hard time processing signals fast enough to handle it. I can think of some workarounds, that might work with certain hardware, but I don't have nearly a complete solution myself, let alone enough to tell a beginner how to do it. (But, at low power levels, by all means experiment; the stakes are low and the learning is high.)Tim

author: julian1
author_rank: Frequent Contributor
timestamp: August 19, 2022, 08:23:44 am
content: I was going to use a VCO initially/ and there is unpopulated RCD to bias the gate timing. But the mcu gets one a long way in using code asserts to range clamp the operating frequency region, adjust/control deadtime, and run the slow regulation outer-loop.But one cannot break into it, for cycle-by-cycle control.If the voltage across the resonant cap is the feature of interest - then I will at least put a diff-amp on it, if I do a board revision. That should should make it easier to probe/understand the waveform.Switching into a LC tank circuit, just seems like a fundamentally simpler/ way to deal with parasitic inductance (versus all manner of contraptions like primary side snubbers, reset windings, active clamps etc ).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 19, 2022, 09:55:04 am
content: Yeah, definitely seems neat, a good way to handle things.Usual thing is to at least get the resonant current -- a current transformer or shunt can be used as is otherwise traditional, but the resonant cap being a cap, there's an easier way: make a C divider into diodes into a burden resistor.I did that, and the VCO method, in this discrete demo circuit:Which I should revisit some time; reduce the frequency (it doesn't need to be so high, core losses are negligible; and actually, most of the power dissipation is from the gate drive(!!)), maybe try the hybrid control (as simple as coupling a bit of C23 into C19).I based the control on ST's L6599:https://www.st.com/resource/en/datasheet/l6599.pdfTim