Bootloader and/or SWD programming information for Zilog's Z32F0642 Cortex-M0 - Page 1
Forum section: electronics / general

author: jesuscf
author_rank: Frequent Contributor
timestamp: April 19, 2019, 04:13:05 pm
content: Does anybody knows where to find information about the bootloader protocol or the SWD flash programming steps for the Z32F0642? Zilog has a flash programmer in their web page, but it looks like it only supports the Cortex-M3 parts.

author: ataradov
author_rank: Super Contributor
timestamp: April 19, 2019, 05:46:43 pm
content: Physical SWD protocol is the same for all Cortex-M0 devices. And once you get that working, the actual programming of the flash happens through normal flash controller registers and procedures described in the section "7. Flash Memory Controller".But it may be easier to contact Zilog and ask them for the information on the bootloader. Sounds like something they should be able to provide.

author: jesuscf
author_rank: Frequent Contributor
timestamp: April 20, 2019, 04:32:17 pm
content: Quote from: ataradov on April 19, 2019, 05:46:43 pmI've contacted Zilog a few days ago but no reply yet. Maybe the SWD protocol access is the way to go.

author: ataradov
author_rank: Super Contributor
timestamp: April 20, 2019, 05:53:40 pm
content: Here is example of SWD implementationhttps://github.com/ataradov/embedded-swd.You will have to change things in dap_target.c, they are dependent on the target MCU.But if you can't get any help with trivial stuff from a vendor, why bother using their stuff.

author: jesuscf
author_rank: Frequent Contributor
timestamp: April 24, 2019, 07:04:23 am
content: Quote from: ataradov on April 20, 2019, 05:53:40 pmThank you! Very usefull SWD implementation. I am getting something already:Code:IDCODE = 0x0bb11477PRER1 = 0x040f0f2fCPUID = 0x410cc20040000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0040000010: 00 00 00 00 00 00 00 00 69 00 00 00 a8 00 00 0040000020: 2f 0f 0f 04 11 03 11 00 0f 00 00 00 01 01 00 0040000030: 0f 00 00 00 01 01 00 00 00 00 00 00 00 00 00 00The boot loader:1fff0000: 00 10 00 20 0d 00 ff 1f 07 00 00 00 f8 b5 01 201fff0010: 80 07 86 46 a2 4d 00 20 01 23 6e 00 9b 02 3f 221fff0020: 01 46 12 06 14 68 ac 42 0b d1 54 68 b4 42 08 d11fff0030: 40 1c 10 28 06 db 9b 48 a5 21 41 60 5a 21 41 60QuoteGood point. Is Zilog even around anymore?

author: jesuscf
author_rank: Frequent Contributor
timestamp: May 02, 2019, 04:30:06 pm
content: Success. A few things that I found out about erasing/loading the flash of the Z32F0642 using SWD:1) After power-on, the internal 40kHz oscillator is selected as the CPU clock source. This limits the maximum frequency of the SWDCLK signal to just a few kHz. A SWDCLK frequency of 8kHz seems to work reliably. After executingCode:dap_init();dap_connect();dap_reset_link();dap_target_prepare();dap_target_select();it is required to change the CPU clock source from the 40kHz oscillator to the 40MHz oscillator as the flash memory controller uses only the 40MHz oscillator as clock source.2) To switch the clock to the internal 40MHz it is necessary to write to the 8-bit registers CSCR and SCCR. Since there is no 'dap_write_byte()' inhttps://github.com/ataradov/embedded-swdI used 'dap_write_word()' instead and called 'dap_reset_link()' after. That seemed to work:Code:dap_write_word(CSCR, 0x28); // Enable high speed internal oscillator. The low speed oscillator needs to remain activatedSleep(10); // Wait for oscillator to start.dap_reset_link(); // Since apparently swd doesn't like a 32-bit write to an 8-bit registerdap_write_word(SCCR, 0x04); // Select high speed internal oscillator as clock sourcedap_reset_link(); // Since apparently swd doesn't like a 32-bit write to an 8-bit register3) After switching to 40MHz the SWDCLK frequency can be increased. A SWDCLK frequency of 400kHz seems to work reliably.4) Before following the procedure outlined in chapter 7 of the Z32F0642 datasheet/manual to erase/program the flash memory it is necessary to 'disable protection' for the flash sectors:Code:dap_write_word(FM_WPROT, 0x98000000); // Disable write protection for sectors 0-1dap_write_word(FM_WPROT, 0x87000000); // Disable write protection for sectors 2-155) Of course, anything that has to do with a different processor in 'dap_target.c' must be removed. The rest has to be re-written for the Z32F064 as pointed out by ataradov. The only thing I kept was the function 'dap_target_select()' with a line for the SAMD21 removed:Code:void dap_target_select(void){// Stop the coredap_write_word(DHCSR, 0xa05f0003); // Debug Halting Controldap_write_word(DEMCR, 0x00000001); // Debug Exception and Monitor Control Registerdap_write_word(AIRCR, 0x05fa0004); // Application Interrupt and Reset Control Register}

author: ataradov
author_rank: Super Contributor
timestamp: May 02, 2019, 04:48:21 pm
content: If you want 8-bit register support, you can port back the code register size code from herehttps://github.com/ataradov/edbg/blob/master/dap.c