Modified LQFP land pattern to solve bridging problems (reflow only) - Page 1
Forum section: electronics / general

author: Georgy.Moshkin
author_rank: Frequent Contributor
timestamp: September 30, 2022, 08:02:07 am
content: Hello, recently I came up with alternate pin arrangement that allows to use wider stencil openings and minimize solder bridging possibility. Standard 0.5mm pitch LQFP stencil paste openings are too thin and paste is easily smeared during stencil removal and/or when components are placed by hand. No solder bridges so far after switching to this land pattern. Mechanical strength to be investigated. Additionally, 0.2 mm thin paste-less area seem to act as solder thief. Distance between pad centers are the same as standard LQFP layout of STM32 chips. Paste shrink: 0mm , mask swell: 0.05mm.LQFP100 pattern in Diptrace format:diptrace-lqfp100.zipPDF dimensions + photos:Modified LQFP land pattern for solder bridging prevention.pdf

author: ataradov
author_rank: Super Contributor
timestamp: September 30, 2022, 04:30:36 pm
content: This looks interesting. But I would expect board houses to have issues with solder mask bridges that are this narrow. Cheaper ones would not be able to manufacture then for sure. At the same time it may not matter this much with this design.

author: Georgy.Moshkin
author_rank: Frequent Contributor
timestamp: September 30, 2022, 11:58:25 pm
content: Good point! But actually the gap is the same as for standard LQFP layout (Diptrace part libraries, stm32 datasheet)Standard: pad width 0.3mm / pitch 0.5mm / gap between pads 0.2mm; If solder mask swell is 0.05mm then solder mask thinnest area would be 0.1mmProposed: alternated pad widths 0.2mm / 0.4mm / gap = 0.5 - (0.2/2+ 0.4/2) = 0.5 - 0.3 = 0.2 . Gap is the same because thinnest zone reduced to 0.2mm whereas adjacent zone increased to 0.4mm.Maybe different mask swell or thinner pad areas of 0.16mm will perform better.Evenly numbered pins have hidden solder joints, so no visual inspection for those. It looks good from the sides, solder climbed up the second and fourth pin from below. For guaranteed results need more experimentation and x-ray inspection.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 01, 2022, 07:34:12 am
content: Interesting practically, but how applicable is it in principle? That is, given min and max dimensions of typical footprints (let alone of of ancient JEDEC types..), how can you guarantee a full heel AND toe (alternately) fillet? Often the difference between accumulated min/max dimensions exceeds this, so you can't guarantee meeting both.I mean, the pads can always be longer, without preventing the reservoir effect. But if the intent is for the blob to touch the pin, that would seem hard to achieve given the specs of most parts. And you don't have much space under the part (between plastic body and lead heel) for the inner blobs.*Shrug*, it's neat at least; just, probably one of those things that's somewhere between "neat but not neat enough" and "too clever for its own good". Which, I'm not sure where this lands, really?For my part, I've had no problem with traditional footprints, I've also not had a ton of feedback from assembly so that maybe doesn't mean much.Tim

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: October 01, 2022, 08:01:09 am
content: Might be helpful for hand assembly and less-than-stellar pick/place machines, as IME what causes shorts is when the part is mis-placed and needs sliding in to position, dragging paste with it

author: NorthGuy
author_rank: Super Contributor
timestamp: October 01, 2022, 04:01:27 pm
content: I think the most common cause for bridges is too much paste. This footprint reduces the amount of paste, but there are more conventional ways to do so - such as narrower aperture or thinner stencil. These methods should yield similar results.You can study and measure the effect by counting number of actual bridges per million pins. Since you don't get many bridges with 0.5 mm pitch anyway, you would need to solder dozens (if not hundreds) of chips to get any measurable difference.Also, if you do get a bridge, does it get harder to repair with this footprint compared to the conventional one?

author: nctnico
author_rank: Super Contributor
timestamp: October 01, 2022, 06:22:37 pm
content: IMHO this is bad solution. I'd make the pads narrower. For an LQFP a pad width of 0.25 is better. Using higher quality solder paste (with better flux) and a better temperature profile should fix the problem. AFAIK the solder joints on an LQFP package should have a heel at the package side of the pins (see item 6 for gull-wing packageshttps://www.circuitrework.com/guides/7-1-3.html)

author: Feynman
author_rank: Regular Contributor
timestamp: October 02, 2022, 09:44:34 am
content: Looks like overkill to me. Using maybe a thinner stencil, properly stored solder paste and solder mask between the pads shouldn't cause significant problems with 0.5 mm pitch devices.And for mass production every decent assembly shop will modify your stencil openings according to their process know-how anyway.

author: Georgy.Moshkin
author_rank: Frequent Contributor
timestamp: June 07, 2023, 01:26:41 am
content: Quote from: mikeselectricstuff on October 01, 2022, 08:01:09 amI think that you've noted most important point of this modified pattern. Placing LQFP100 on my prototype boards is now significantly less worrying. Stencil cleaning is a little easier too, cleaning with alcohol pads is enough, I do not use small brush anymore. The main disadvantages: difficult to inspect hidden solder joints, so need to use properly stored chips with no minimal pin oxidation or renew pins surfaces by some kind of no-clean flux before placing. If anyone use this pattern be prepared if chip is not soldered properly, trying to fix it with soldering iron and wick may become pretty annoying and transform it to disadvantage.In a few days I am going to test the same approach for 16-pin USB type C surface mount connector.EDIT:and post results with photos here

author: Georgy.Moshkin
author_rank: Frequent Contributor
timestamp: June 16, 2023, 12:38:17 am
content: Modern PCBs have a lot of dense surface mounted tiny components. I think majority do not use a simulator, and just stick to some IPC standards. I think, these standards may be derived from both experimentation and simulation (or calculations).

author: Georgy.Moshkin
author_rank: Frequent Contributor
timestamp: July 12, 2023, 03:26:38 am
content: Modified USB Type-C land pattern for less bridging and easier stencil cleaning tested (https://youtu.be/JSf-CUBMFco)Note that I used desoldered LQFP chip in this video (it already had some solder bridges), stencil was too thick, board jumped around a little during application, paste is expired, and heat plate was already hot. I think results with new paste and standard preheating in reflow oven will provide better results. USB Type-C connector was new and soldered very well.

author: NorthGuy
author_rank: Super Contributor
timestamp: July 12, 2023, 01:52:46 pm
content: Quote from: Georgy.Moshkin on July 12, 2023, 03:26:38 amI use this USB connector and it has very good yield with standard footprint. If you get bridging, this must be because your stencil is too thick and deposits too much paste.

author: Georgy.Moshkin
author_rank: Frequent Contributor
timestamp: July 12, 2023, 03:51:04 pm
content: Yes, stencil is thick and I align it manually. Photo shows smeared paste before placement. This small stencil sheet is many times cheaper than normal stencil with aluminum frame. I just let the good manufacturing people use any sheets they have and not bothering them with demands on stencil thickness.

author: Georgy.Moshkin
author_rank: Frequent Contributor
timestamp: March 24, 2024, 01:03:21 am
content: Recently, I've got a comment on one of my videos that such pattern is probably more suitable for 3D printing. I never heard that 3D printer can be toprint a SMT stencilbeforeI think that this idea might be useful.