DDR RAM PCB trace question - Page 1
Forum section: electronics / beginners

author: emusan
author_rank: Newbie
timestamp: August 03, 2014, 11:23:29 pm
content: I'm doing my first PCB design with DDR SDRAM memory. Everything was going great until now when I'm reading more on the PCB design aspect.I was initially going to route everything as a 50 Ohm transmission line using 50 Ohm series termination resistors. (The RAM is directly next to the controller so I don't think that a full set of parallel termination resistors are necessary.)I'm using OSHpark for the PCB's, and they use an FR408 material for the 4-layer boards. I may have done something wrong, but I calculated approximately .348mm/13.7mil wide traces in order to achieve the 50 Ohm impedence. However, reading back through some of the micron pcb layout recommendations, it looks like they recommend 4-6mil traces with ~12mil separation. This comes out closer to a 75 Ohm impedence. I would then assume if I were to use a 75 Ohm transmission line that I should use 75 Ohm series termination resistors, however the micron guide still recommends ~50 Ohm. I'm guessing they recommend this because the line length is <2in (for longer lines they recommend parallel termination), and that the ringing doesn't matter because the bounces finish within the clock cycle. Though, if using a 50Ohm series termination I'd guess that the transient voltages on some of the pins may go out of spec (though only for a few ns).I'm curious if this is correct, and I should be running an ~75Ohm transmission line with 50 Ohm termination resistors, or if perhaps I should keep the lines at ~50 Ohm, or maybe I need to change the resistances I'm using as well?I could also just be overthinking this all, I just want to make sure I get this right.The micron guide I'm using (among others) can be found here:http://www.micron.com/-/media/documents/products/technical%20note/dram/tn4614.pdfThanks in advance for any help!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 04, 2014, 03:04:09 am
content: Quote from: emusan on August 03, 2014, 11:23:29 pmUnless you specifically instruct that you require controlled impedances, I doubt you'll even get that. I would be very surprised if budget suppliers like OSHpark or Itead have anywhere near that capability, even if you insisted. ("Ain't nobody got time fo' dat!", especially not sweatshops.)QuoteHere,http://chemandy.com/calculators/microstrip-transmission-line-calculator.htmI calculate 93 ohms for that (using e_r spec from a typical FR408 datasheet)!There are several calculators listed, unfortunately they don't provide an indication of which is most authoritative (perhaps you'd have to refer to the literature to find that out).The geometry varies by manufacture anyway, so as usual, you're better off putting down something close enough, then instructing that certain traces be impedance controlled, and verifying that what you requested is, in fact, what you wanted (and be willing and able to shove the boards back at them if they didn't achieve the desired result).Last time I used a modern-ish DRAM, it was regular SDRAM, 3.3V signaling I believe. Worked fine without termination, and was adjacent to the FPGA (under 2" trace length). I haven't used any DDR before.Important reading:http://ssl.xmu.edu.cn/download%5CStandards%5CJEDSD%5Csstl_2spec.pdfQuoteIf it goes out of spec at all, you're screwed. There are SSTL clocks in there, which would double-tap (or worse) if that were the case.Fortunately, it appears the standard is robust enough to tolerate some mismatch, between drivers, transmission line, stubs (i.e., DIMMs present on the bus or not) and terminators. It's also designed with enough transmitter capacity and receiver range to accommodate a variety of source, load or doubly terminated methods.QuoteThe transmitter itself appears to be a plain old CMOS logic output, with an Rds(ON) around 25 ohms. Compare with 74HC's 50~100 ohms (at >= 3.3V), or so on. Though they may be current mode, or current limited (at least 8/16mA being available into the indicated termination, for the respective transmitter class)The receivers specify AC and DC thresholds (meaning, I think, there's a few-ns-long band where transients must fall within a diamond shaped eye), which -- between the relatively narrow threshold (VREF +/- 0.35V), leaves a pretty fair room for error, for instance, out of a +/-1.25V possible swing (2.5V supplies, VREF = VDD/2), you can have some 72% undershoot before violating the threshold. It'll be tighter than that when loading and overshoot limits are included, but it looks like just dumping the transmitter into the transmission line (through a (Zo - 25 ohms) resistor or so), and terminating the end of that (with a resistor of Zo), will do the job; or for single point (as is the case here), a source terminator alone (of Zo - 25 ohms) will be sufficient.I don't think I would recommend doing it direct point-to-point, no resistors at all, but it seems like a simple layout doesn't need to be very fancy, just source terminators really. Do take note of which lines have transmitters: you won't want to miss out on terminating the DQs on both ends, for example (because it is a dual driven line).Don't neglect the VREF; it should probably be something like, the ground plane immediately under the signals, and well bypassed at both ends. (Make a suitable compromise between where VREF and VDD/GND planes/polys are routed.) An op-amp making VDD/2 might be okay for setting level; I don't think I would condone using a relatively high resistance voltage divider, even if the load may be small (CMOS inputs?). Something much beefier is required for parallel terminated buses, as all those termination resistors can add up to several amps (from a few chips' worth of bus) very quickly! On a computer motherboard, you'll find such a VREF controller near the DIMM sockets, or something like that.Also, check if either IC generates VREF internally, and if it's okay to connect them, or what's going on with that.Tim

author: emusan
author_rank: Newbie
timestamp: August 04, 2014, 03:44:34 am
content: Thanks for the reply!Quote from: T3sl4co1l on August 04, 2014, 03:04:09 amI know that they wont do a full on controlled impedance, but I figure if I can get it close on my own then it should be "good enough" (I've seen a few working DDR RAM designs from OSHpark, so it is possible).QuoteYeah, DDR is a bit more finicky than SDRAM, I've read through a fair bit of documentation, but I will give a read through those as well just in case they shed some more light.QuoteI figure series should be all I need, but just want to make sure that I'm understanding this correctly. Also, are you getting the transmitter resistance of 25 ohms from the standard or another source? I did a quick skim through the document you linked and it doesn't seem to state the driver output impedance to be 25 ohms (I may have missed it though, I still have to give it a longer read-through).As far as series termination goes, from the micron guide they recommend that signals which have a single direction should be terminated close to the transmitter, whereas bidirectional signals should be terminated about midway between the transmitter and receiver.QuoteI was going to be routing my VREF directly above the ground plane on an internal layer (I think that should keep the noise lower). I've seen many guides that say that VREF an be generated using a simple resistor divider when only dealing with a single memory module (as I am for this project). Neither my controller nor the memory I'm using generate it either. I also have some decoupling caps near each of the pins that it connects to.When doing parallel termination they typically recommend a completely separate supply for the termination voltage than the VREF rail in order to prevent those transient currents from throwing off the reference. As far as I know the reference voltage doesn't have much load as it's only used in comparators on the inputs (with fairly low leakage current). Ideally if I can get away with only using series terminations then I wouldn't have to generate this separate rail, which would be rather nice as I don't want to invest *too* much into this project right off the bat.

author: free_electron
author_rank: Super Contributor
timestamp: August 04, 2014, 08:02:52 am
content: something is wrong in your calculations , or your layerstack is crap.thedifferentialdrive is 120 for DDR , 100 ohms for DDRxread that datasheet : page 8 has the answers you seek.

author: Precipice
author_rank: Frequent Contributor
timestamp: August 04, 2014, 08:48:27 am
content: Bear in mind - this stuff matters far less for a single device on a tiny stub of a bus, running way under the DRAM's Fmax than it does, say, on a PC motherboard with 6" traces and a bunch of DIMM sockets that may or may not be occupied, running balls-out (and then overclocked a bit)I'd place a decent bet on it just working, no matter what you do, as long as ground is good, and power and Vref are adequately decoupled.That's not to say that you shouldn't try to get the layout and lengths (and differential pairs) roughly right, but fretting massively over impedances - nah. (Seen the discontinuities that a DIMM socket introduces in a bus?)It's my opinion that length matching the signals to extreme precision is actually worse for EMC than staggering them (within the spec), and if you're allowed to length match different bytes (and strobes) to different lengths, do it...Not that I've ever bothered to build a back-to-back comparison board, mind. It just feels reasonable that changing all the lines into a chip simultaneously will have more effect than staggering them (although it's only over a few tens of ps, worst case). Might be worth it from a ground bounce perspective, too)

author: emusan
author_rank: Newbie
timestamp: August 04, 2014, 05:01:04 pm
content: Quote from: free_electron on August 04, 2014, 08:02:52 amI don't think this has anything to do with my layer stackup directly, my question is more broad than that. EDIT: gave some more thought and I guess you're saying that I should be doing the calculations for a layer stackup that would give a matching impedance with the recommended traces? I think that may be possible...For DDR SDRAM the only differential signal is the clock line, which I have already routed, what I'm asking about here is the rest of the signals, which are all single ended and don't need to be routed as a 100-120ohm transmission line.If you're referring to the micron datasheet, then that's exactly what my question is about (I've read through it a number of times). They recommend a trace that would give >50 ohm characteristic impedance, and then later on recommend a 50 ohm termination (which would cause some bouncing). Now that I've given some more thought to it though I think that it's okay because of the speeds and distances in question.QuoteYeah, I kind of figured I might be overthinking all of this, given the size/scope of my project. I'll just follow Microns recommendations and worst case I'll have to change out a few series termination resistors. I had also never considered how empty DIMM slots might affect the signals on a motherboard, that must be interesting to deal with.Thanks for the help everyone!EDIT again: Well looks like I'm an idiot, one of the footnotes on a page stated that they recommend a pcb stackup where a 4mil trace gives a 50 ohm impedance, so that basically answers my question. Always have to remember those footnotes.