understand the design of USB hubs - Page 1
Forum section: electronics / beginners

author: m4rtin
author_rank: Regular Contributor
timestamp: July 18, 2016, 06:22:01 pm
content: I have an embedded PC which runs FreeBSD OS. It detects following USB devices:Code:usb0 (addr 1) EHCI root hub 0 Freescale uhub0usb0 (addr 2) USB2513Bi 9491 SMSC uhub1usb0 (addr 3) AF8GSSGH-JP4 45185 ATP Electronics umass0usb0 (addr 4) Ultra Fit 21891 SanDisk umass1umass0device is internal flash memory device.umass1is an USB flash-drive. However, why are there two USB hub devices(uhub0anduhub1)? Does one of those hubs handle low-speed and full-speed devices and second one handles only high-speed devices? If yes, then which controller handles which speeds? According to specs, bothFrescale Integrated USB 2.0controller andSMSC USB2513Bisupport high-speed devices. If it helps, then this information is logged during the system bootup regarding USB controllers:Code:ehci0: <Frescale Integrated USB 2.0 controller> iomem 0xfe210000-0xfe210fff irq 60 on ocpbus0usb0: EHCI version 1.0usb0 on ehci0usb0: USB revision 2.0uhub0: Freescale EHCI root hub, class 9/0, rev 2.00/1.00, addr 1uhub0: 1 port with 1 removable, self powereduhub1: SMSC USB2513Bi, class 9/0, rev 2.00/b.a0, addr 2uhub1: multiple transaction translatorsuhub1: 3 ports with 3 removable, self powered

author: Kilrah
author_rank: Unknown
timestamp: July 18, 2016, 06:33:49 pm
content: Looks like the Freescale device is the root USB controller that only has one single port. Connected to it is an SMSC hub to provide multiple ports for the various devices.The interesting thing to take from this architecture is that all USB devices share the bandwidth of a single port.

author: m4rtin
author_rank: Regular Contributor
timestamp: July 18, 2016, 07:19:29 pm
content: Quote from: Kilrah on July 18, 2016, 06:33:49 pmYes, looks like that:Code:# usbdevs -vController /dev/usb0:addr 1: high speed, self powered, config 1, EHCI root hub(0x0000), Freescale(0x0000), rev 0x0100port 1 addr 2: high speed, self powered, config 1, USB2513Bi(0x2513), SMSC(0x0424), rev 0x0ba0port 1 addr 4: high speed, power 224 mA, config 1, Ultra Fit(0x5583), SanDisk(0x0781), rev 0x0100port 2 poweredport 3 addr 3: high speed, power 500 mA, config 1, AF8GSSGH-JP4(0xb081), ATP Electronics(0x14af), rev 0x1100#Quote from: Kilrah on July 18, 2016, 06:33:49 pmI made a small drawing:Am I correct that USB traffic betweenSanDisk USB flash-driveandAF8GSSGH-JP4 internal flash-drivestill needs to go through SoC/CPU and thus through the link between the USB hubs and link between theFreescale USB 2.0 huband CPU? In addition, what bus might be used between theFreescale USB 2.0 huband CPU(Freescale e5500)? Or maybe thisFreescale USB 2.0 hubis built into Freescale e5500..

author: helius
author_rank: Super Contributor
timestamp: July 18, 2016, 08:07:21 pm
content: Quote from: m4rtin on July 18, 2016, 07:19:29 pme5500 is the name of a PowerPC core. The SoC that uses it are P5010, P5020, P5021, P5040.... They do contain integrated USB 2.0, but only full speed. If the machine has hi-speed USB, it must be on a peripheral companion chip connected to the main SoC (using PCIe or whatever).You are right that all transfers from one USB device to another must go through the CPU, or at least a central DMA engine as many SoCs have these days. That's because USB is strictly driven by the root and no multi-master operation is possible.

author: Monkeh
author_rank: Super Contributor
timestamp: July 18, 2016, 08:22:53 pm
content: Quote from: helius on July 18, 2016, 08:07:21 pmP5021 and P5040 have HS. P5010 and P5020 are FS.

author: m4rtin
author_rank: Regular Contributor
timestamp: July 18, 2016, 10:06:30 pm
content: According to messages printed to console during bootup, it uses P5021 SoC:Code:CPU0: P5021, Version: 2.0, (0x82050020)Core: E5500, Version: 1.2, (0x80240012)AsMonkehalready mentioned,P5021has two High-Speed USB 2.0 controllers with integrated PHY. However, it says that it hastwoHigh-Speed USB 2.0 controllers. Does this mean that both theFreescale Integrated USB 2.0 controllerandSMSC USB2513Bi controllerare actually integrated to SoC? Are integraded USB controllers also connected to CPU/DMA-engine over PCIe? If yes, then the diagram should look like that:If my drawing is correct, then what is the purpose of this one port("uhub0: 1 port with 1 removable, self powered"according to log messages)Freescale USB 2.0 hub? The only purpose I could see is thatSMSC USB2513Bidoes not have PCIe interface..

author: Kilrah
author_rank: Unknown
timestamp: July 18, 2016, 10:08:50 pm
content: Can you look at the board? What isn't visible on there is obviously internal to another chip.

author: m4rtin
author_rank: Regular Contributor
timestamp: July 18, 2016, 10:10:31 pm
content: Quote from: Kilrah on July 18, 2016, 10:08:50 pmUnfortunately not. It is a remote device.

author: Monkeh
author_rank: Super Contributor
timestamp: July 18, 2016, 10:12:22 pm
content: The SMSC/Microchip (Microchip acquired them a while back) chip is a purely external hub. The chip may have two controllers, but they can be disabled independently.The internal controller is not attached via PCI-E, it is part of the chip (note the mention of 'ocpbus0') and accessed pretty much directly (I imagine).

author: m4rtin
author_rank: Regular Contributor
timestamp: July 18, 2016, 11:03:48 pm
content: Quote from: Monkeh on July 18, 2016, 10:12:22 pmThanks! I further improved the diagram:So the point ofSMSC/Microchip USB2513Biis simply to provide three downstream High-Speed USB ports becauseFreescale Integrated USB 2.0 controllerhas only a single downstream USB port? And the maximum theoretical data transfer rate shared between all the devices connected toSMSC/Microchip USB2513Biis 60MB/s in half-duplex.

author: gslick
author_rank: Frequent Contributor
timestamp: July 18, 2016, 11:59:37 pm
content: Quote from: m4rtin on July 18, 2016, 11:03:48 pmThe theoretical max bandwidth would be 60MB/second. According to the USB 2.0 specification for high-speed bulk transactions using 512-byte packets the max bandwidth is 53,248,000 bytes/second. That is a maximum of 13 512-byte packets per microframe with 8,000 microframes per second.

author: helius
author_rank: Super Contributor
timestamp: July 19, 2016, 02:41:02 am
content: Quote from: Monkeh on July 18, 2016, 10:12:22 pmFreescale/NXP calls the on-chip crossbar "CoreNet". ocp sounds like a generic BSD name for on-chip peripherals.Why use a single root port and a hub if two root ports are available? It could be a decision for power consumption or PCB routing reasons, or to reduce EMI.

author: Monkeh
author_rank: Super Contributor
timestamp: July 19, 2016, 02:58:07 am
content: Quote from: helius on July 19, 2016, 02:41:02 amOne which was, as far as I can tell, disposed of 6 years ago..

author: m4rtin
author_rank: Regular Contributor
timestamp: July 19, 2016, 07:12:24 am
content: Quote from: helius on July 19, 2016, 02:41:02 amThis device needs three USB ports, i.e those two High-Speed USB 2.0 controllers with integrated PHY in P5021 SoC would not be enough. One is for internal flash and two are for USB flash-drives. You can see this from output of "usbdevs -v", where port 2 is powered, but nothing is connected at the moment:Code:# usbdevs -vController /dev/usb0:addr 1: high speed, self powered, config 1, EHCI root hub(0x0000), Freescale(0x0000), rev 0x0100port 1 addr 2: high speed, self powered, config 1, USB2513Bi(0x2513), SMSC(0x0424), rev 0x0ba0port 1 addr 4: high speed, power 224 mA, config 1, Ultra Fit(0x5583), SanDisk(0x0781), rev 0x0100port 2 poweredport 3 addr 3: high speed, power 500 mA, config 1, AF8GSSGH-JP4(0xb081), ATP Electronics(0x14af), rev 0x1100#AsMonkehsaid, probably one of those is disabled as it is nowhere mentioned during the boot messages.