SPI Mode 1, missing MSB - Page 1
Forum section: electronics / beginners

author: Jinhao
author_rank: Contributor
timestamp: March 26, 2023, 05:43:34 am
content: Hi,I am working on project using a 32 bit ADC (LTC2500-32). I think SPI mode 1 should be used as the picture suggests: sampling happens on falling edge and clock is by default low.(I'm only using channel SDOB, link to the datasheet:https://www.analog.com/media/en/technical-documentation/data-sheets/250032fb.pdf)My question:Why the first bit (MSB) seems never got sampled and there is always a dummy zero sampled at the end? Is this normal?Thank you.

author: ataradov
author_rank: Super Contributor
timestamp: March 26, 2023, 06:00:54 am
content: This is SPI mode 0, sampling happens on the rising edge with low idle clock level.There are also more detailed timing diagrams showing setup and hold times later in the document.Also, when SPI things don't seem to work correctly, it is always worth simply trying all combinations to see if something changes.

author: Jinhao
author_rank: Contributor
timestamp: March 26, 2023, 06:45:16 am
content: Thank you Alex, you are right. I should have read the datasheet more carefully. The datasheet indeed explicitly says the "output code appears on this pin (MSB first) on each rising edge of SCKB".I'm still a bit confused about the timing. It also says the shifting happens on the rising edge. If so, then shifting and sampling happens on the same edge. I thought shifting should happens first and let the data bit to stabilize over a half clock cycle, so sampling happens on the opposite edge. Am I fundamentally wrong?Thank you for your patience

author: ataradov
author_rank: Super Contributor
timestamp: March 26, 2023, 06:48:51 am
content: Quote from: Jinhao on March 26, 2023, 06:45:16 amThis is because it is not actually SPI, it is something compatible with most SPI controllers.This follows a standard singe edge logic, the data is sampled by the master and changed on the same clock cycle. There is some delay (hold time), so you generally have plenty of time to sample it and the data remains stable for the whole cycle, which is what you really want in most cases.The real SPI design is more conservative, but also is not necessary and annoying to implement.

author: Jinhao
author_rank: Contributor
timestamp: March 26, 2023, 06:51:51 am
content: Thank you so much. I learnt new things and I really appreciate your help.

author: mikerj
author_rank: Super Contributor
timestamp: March 26, 2023, 04:06:12 pm
content: Quote from: ataradov on March 26, 2023, 06:00:54 amAs always, exercise with caution. Years ago I had a design that appeared to work fine but would very occasionally fail at elevated temperatures, the cause was the wrong SPI mode giving marginal timing.

author: ataradov
author_rank: Super Contributor
timestamp: March 26, 2023, 05:18:55 pm
content: Quote from: mikerj on March 26, 2023, 04:06:12 pmYes, absolutely. I'm not saying that you should find the one that works and move one. This is just a method to start figuring it out. Sometimes SPI controllers have inverted meaning of bits or different numbering of the modes. This will at least tell you what seems to work, and then you can figure out if it makes sense that that specific configuration works.