Usage of the word 'strobe' - Page 1
Forum section: electronics / general

author: TheGreatNed
author_rank: Contributor
timestamp: March 11, 2020, 02:23:38 am
content: Hi,Opencore's FFT256 gives the following pin description for the block diagram of their FFT core:SIGNAL TYPE DESCRIPTIONCLK input Global clockRST input Global resetSTART input FFT startED input Input data and operation enable strobeDR [nb-1:0] input Input data real sampleDI [nb-1:0] input Input data imaginary sampleSHIFT input Shift left codeRDY output Result ready strobeWERES output Result write enable strobeFFTRDY output Input data accepting ready strobeADDR [7:0] output Result number or addressDOR [nb+3:0] output Output data real sampleDOI [nb+3:0] output Output data imaginary sampleOVF1 output Overflow flagOVF2 output Overflow flagWhat is meant by 'strobe' here? Wiki only says that Strobe signals are sent with data signals so a receiver knows the clock speed of the data sent.I have noticed that these strobe signals are one-shot signals -- not continuous.Thanks

author: greenpossum
author_rank: Frequent Contributor
timestamp: March 11, 2020, 02:26:53 am
content: In a general sense a strobe signal is used to indicate the receiver when data is to be taken. It could be a level or edge signal. While it may indicate clock speed, that's not the most common use.

author: OwO
author_rank: Super Contributor
timestamp: March 11, 2020, 06:58:28 am
content: That interface design sucks though, there are so many control signals with complex interactions, and for whatever reason it has input control flow (FFTRDY) even though the output side doesn't accept backpressure. Which means you need more logic to deal with FFTRDY='0', even though in a well designed pipelined FFT core the input should *always* be ready to accept data. And wtf is "Result ready" and "Result write enable strobe" which are both outputs? I recommend looking for another core.EDIT: btw just google "fpga fft github". You will find >10 different implementations but only two of them are worth your time.

author: TheGreatNed
author_rank: Contributor
timestamp: March 11, 2020, 08:21:56 am
content: Ah ok, now I feel better about being confused with this interface... I am going to assume 'strobe' is just intended to mean 'signal that informs receiver of *something*'.by the way, is it weird that these flow control signals (RDY, START, FFTRDY) are one-shot signals and non continuous?

author: OwO
author_rank: Super Contributor
timestamp: March 11, 2020, 10:07:41 am
content: You haven't given a link to the core or documentation, so it's impossible to tell what those signals really mean. There should at the very least be a timing diagram showing example usage, and detailed descriptions of each signal. Without documentation those signals can mean anything; "strobe" can mean flash an LED for all I know. If you post a link to the code I might be able to guess (or just tell you the core is rubbish and to use something else)

author: David Hess
author_rank: Super Contributor
timestamp: March 12, 2020, 01:52:36 am
content: I usually think of a digital strobe in the same way as a sampling strobe; one edge of the strobe is aligned with the data such that it is used to latch the data in a register which could be composed of flip-flops or latches.

author: TheGreatNed
author_rank: Contributor
timestamp: March 12, 2020, 04:58:58 am
content: https://opencores.org/websvn/filedetails?repname=pipelined_fft_256&path=%2Fpipelined_fft_256%2Ftrunk%2FDOC%2Ffft256_um.pdfWould be very curious what your 2 chosen fft cores are ;]

author: OwO
author_rank: Super Contributor
timestamp: March 12, 2020, 05:19:23 am
content: ooooo, not bad, that one actually implements high radix (Bailey's large FFT method) and the documentation is pretty good. But it boggles the mind why it's fixed to size 256 rather than being parameterized. Oh yeah because verilog that's why.FFTRDY doesn't appear in any of the timing diagrams, so I'll assume it's not actually used and the core is always ready to accept data. WERES also appears to be unused, so the core is assumed to be always outputting data (when clock enable is high). START and RDY are framing indicators, where START indicates the first sample of the input frame, and RDY indicates the first sample of the output frame. ED is simply a global clock enable signal; when it is low the core does nothing and no data is input or output. Now it is clear that this core is very similar to my core, with the only difference being how data is framed and synchronized. (my core uses a user-supplied monotonic counter which is allowed to be reset).Seehttps://github.com/owocomm-0/fpga-ffthttps://github.com/owocomm-0/fpga-fft/raw/master/docs/ug9001.pdfThe only two other FFT cores on GitHub (excluding mine) that are usable are:https://github.com/ZipCPU/dblclockffthttps://github.com/capitanov/intfftkThese both can run reasonably fast *if* you fix a few timing issues (see the GitHub issues I've opened on both repos).

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 12, 2020, 04:24:58 pm
content: A "strobe" signal is kind of the equivalent of a data sampling control signal. Said data will be "sampled" (latched/registered) on the rising or falling edge of the signal.Note that when dealing with purely synchronous designs, I think this is a bit of a misnomer. We use no "strobe" signals per se, but enable signals with a clock constantly running. A different approach to latching data. IMO (your definition may vary), "strobe" signals in the strict sense are more used for asynchronous data latching (which I don't think it's the case here, as it's clearly an enable signal.)

author: TheGreatNed
author_rank: Contributor
timestamp: March 12, 2020, 10:47:56 pm
content: Quote from: OwO on March 12, 2020, 05:19:23 amThanks so much for your insight. I want to see what a good design looks like. I'll be checking this out.Quote from: SiliconWizard on March 12, 2020, 04:24:58 pmOk got it. Author misused it.