2kW Boost PFC blown up....how? - Page 1
Forum section: electronics / general

author: Faringdon
author_rank: Super Contributor
timestamp: August 04, 2022, 12:04:05 pm
content: Hi,EDIT....This post is not worth reading if you are seeking interesting power supply issues....this problem was caused by poor PCB layout......the blow up problem has now been solved by increasing soft start cap and more importantly, by increasing the fet gate series resistor......doing that reduced the switching transition noise, which "covered up" the poor PCB layout to an extent........END OF EDIT}Just tried initial mains powering of 2Kw Dual Boost PFC with UCC28070A. Only 7W load. Mains input fuse 3.15A.FETs = 600V (SiHG186N60)Sic output diode. (C6D0465A)First did inrush via 47R….no problem….…Then enabled PFC stages….input fuse blew immediately. Didn’t see any rise in Vout.Current sense peak maximum threshold is set well below inductor saturation level.Duty cycle of UCC28070A is set to 0.9 maximum.CSTs are 50:1Cout = 540uF.UCC28070A datasheethttps://www.ti.com/lit/ds/symlink/ucc28070a.pdf?ts=1659614618238&ref_url=https%253A%252F%252Fwww.google.com%252FOn examination, both FETs are short G-D-S. Nothing else on the board is damaged (other than input fuse). Gate drives still working fine.Suspect problem due to either…1…..Much stray inductance in the FET current sense transformer output circuit. This could have caused the BAS16 current sense rectifier diode (75V) to blow given that reset Zener is 68V. Also, it’s a distance of some 15cm from CST to the burden resistor which is near the PFC controller……..so stray inductance ringing in this may have wadgered the current sense signal? (even though I have a 1k/470p filter on the way to current sense pin).2…….Ringing on the 650V Boost FET Drain……there are no snubbers on the boost FETs. I have simulated stray inductance in the FET/DIODE/Cout wiring, and I cannot get it to ring above 600V, so I doubt that there was ringing above 650V on the Boost FET?For the next power up, I will…..a…..Set the UCC28070A max duty cycle to 0.1.b……Take the current sense burden resistors off the PFC controller board, and bring them much nearer the CST (I have blank footprints there ready for them).c……Introduce the “slope compensation” ramp signal, which I had previously unpopulated.d….Add RC snubbers to the Boost FETs.e….Change the PFC disable/enable signal so it grounds the soft start input, instead of the current sense error amplifier outputs.f…..Use 1200V FETs for the next power up.___---___The disadvantage of (b) above is that the current sense signal will now be going some 15cm back to the PFC control board…..however , this seems better than sending the CST output current that far.I’m also wondering if the FETs have been mis-handled and have ESD damage? Also, they came from Farnell in a clear plastic tube (as attached)…..this therefore cannot be ESD safe? Its possible these FETs may have been ESD weakened, and making then switch mains killed them off?

author: wraper
author_rank: Unknown
timestamp: August 04, 2022, 12:12:46 pm
content: That is a cut to length piece of tube in which they come from the factory. As long as it is put into ESD shielding bag, it's a proper way how to package them. Although I don't think that tube is intended to shield from static discharge as such, it's unlikely ESD will shot through due to its thickness. Nor power MOSFETS are particularly sensitive to ESD. They have large gate capacitance and often TVS diode between its gate and source.

author: Faringdon
author_rank: Super Contributor
timestamp: August 04, 2022, 01:32:58 pm
content: Thanks, when the staff cut these tubes up, they have to handle the FETs, and i wonder if they do so with proper ESD precautions?...i mean, they probably all wear these trainers, with their rubber souls, which will give static zaps to anything they touch aswell?I also noted that this FET does not have the bidi TVS from gate to source...SiHG186N60 FET datasheet..https://www.mouser.co.uk/datasheet/2/427/sihg186n60ef-2897279.pdfMust admit ive had several TO247 SIC 1200V NFETs (as used in a 300W, 300-100V Buck SMPS) go short on me from me handling them without ESD protection in an electronics lab. (not even powering them up)Also, the gate to drain capacitance of this SiHG186N60 fet is only 5pF.

author: wraper
author_rank: Unknown
timestamp: August 04, 2022, 01:45:34 pm
content: Quote from: Faringdon on August 04, 2022, 01:32:58 pmI'm pretty sure farnell has proper ESD precautions implemented. Chances that your issue is from Farnell side is nearly zero.QuoteThe fact you don't see it in datasheet does not mean there is none. Quite likely there is none but often it's just not mentioned.Also if you don't want something like this not to blow on first power on, you should use protection. Like a high power incandescent bulb or iron for clothes in series with mains.

author: Faringdon
author_rank: Super Contributor
timestamp: August 04, 2022, 02:10:23 pm
content: QuoteThanks, Maybe 40 years ago i would have agreed, but the UK now is virtually devoid of electronics, it all having been outsourced to the Far East, so nobody could blame Farnell if they have a lack of electronics knowledge within their ranks.....AYK, it comes with the "outsourcing" territory unfortunately.I have worked in a very good number of (small) electronics co's in UK which do not have any ESD precaution at all....even working on static gen carpets......these are small co's doing bits of government grant funded projects. (As such because few woudl invest in an electronics project in uk now, for fear of being gazumped by a Far Eastern product.)There are token UK projects in electronics, which give a co the "designer/manuf" status they need in order to be given the middle man importer-of-electronics jobs, which pay big bucks.I think "lack of ESD awareness " is on the rise malheuresement.

author: Gyro
author_rank: Super Contributor
timestamp: August 04, 2022, 04:32:44 pm
content: Quote from: Faringdon on August 04, 2022, 02:10:23 pmGet off your soapbox treez, A volume distributor like Farnell will have infinitely better ESD control than you do - as is evident from your several threads on the subject.Now stop trying to blame other people and sit (or kneel) down and work out what's wrong with your design. You'll find it far more productive!

author: uer166
author_rank: Super Contributor
timestamp: August 04, 2022, 07:04:35 pm
content: Thank you for posting pics of hardware, that is much more interesting than abstract LTSpice sims..The chance of it being ESD damage vs. a design issue is something like 1:1000000. Measure drain current and Vds voltage at startup, it's almost certainly over-stress due to a design issue..

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 04, 2022, 07:37:14 pm
content: I did a 800W PFC earlier this year, just starting with the mfg eval board. Worked out surprisingly well, just beef everything up basically. The stray loops suck (almost single layer design, yuck) so I had to tack on some snubbers, but that's easy enough. Not expecting any problems with the final build.The CCM design will be more sensitive to strays, so blowing up is a strong possibility. It's very difficult to start a PFC full-send without any way to bring it up slowly and check operation.Tim

author: Faringdon
author_rank: Super Contributor
timestamp: August 04, 2022, 08:03:14 pm
content: Thanks, i believe i will put on an RCD clamp around the current sense transformer primary, and RC snubbers on the FET and diode, as attached. In fact, i think i wont need the diode RC snubber if i have the RCD clamp. [EDIT----Rather, the typical RCD clamp like attached cant be used, as theres no path for the CST leakage L to freewheel in----END-OF-EDIT]Page 11 of the L4981A datasheet shows an RCD clamp being used to take the freewheel current of the anti-reverse-recovery-spike inductor in a 400W PFC [EDIT---woops, missed the accompanying TVS/diode needed to contain the freewheeling current of the CST L Leakage) END-OF-EDIT]And L4981A shows an NTC in series with the boost diode.And a turn-off snubber.For the UCC28070A though, i think i will end up making do with a RCD turn off snubber on the FET, and an RC across the diode.L4981A datasheethttps://www.st.com/resource/en/datasheet/l4981.pdf

author: Wolfram
author_rank: Frequent Contributor
timestamp: August 04, 2022, 10:21:50 pm
content: In a case like this, I would separate the testing into stages to reduce the risk of something going badly wrong on initial testing, leaving you without any sensible measurement results indicating what might be wrong.I would feed the PFC stage from a current limited DC supply, and drive the MOSFET gates from a signal generator of the right frequency and maybe 50 % duty cycle, with a sensible load resistor on the output. You probably need a gate driver as well here for buffering. Bring up the input voltage while looking for unexpected behavior or excessive ringing. Once you are confident the power stage is working correctly, look at the current sense signals to see if they have sensible shape and scaling. Once this is done, you can add in the actual PFC controller and try to power it from a low voltage AC source. If you want to play it safe, you can disconnect the gate drive signals to verify that the chip is doing something sensible.

author: Faringdon
author_rank: Super Contributor
timestamp: August 04, 2022, 11:06:30 pm
content: Thanks Wolfram, that does sound like the best way to do it, at the moment i cant afford those supplies, but will start saving.In fact, the UCC28070A Boost PFC has the extra "inductor" (leakage L from CST primary) in the drain....so needs the TVS/diode/diode/100n+6R8 circuit as attached here. I am surprised none of the vast number of app notes on UCC28070A have any kind of snubbing at all.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 05, 2022, 01:02:13 am
content: It's only 60kHz... a tight loop and either soft recovery or preferably SiC nowadays, is all you need. Control rate with gate resistors or source FBs.Tim

author: jonpaul
author_rank: Super Contributor
timestamp: August 05, 2022, 11:50:41 am
content: Farrington: Had that same situation in many projects, all of us Power Electronics engineers have a box of blown transistors. Welcom to the club!0/ Probably poor /overshoot drive at FET gate, or poor control of leakage L causing transients at FET or driver.Note that coupling coeff is NOT notmally tested or a parameter except in simulations.in 1970s..1990, as designer and consultants, for magnetics, we used parametersLpri magRdc priLsecRdc secLeakage L of P and SratioOur magentics CAD was IntuSoft Magnetics designer. We never did any simulations they are not accurate.1/ FET damage due to ESD is unlikely to be the culprit in a new design proto. To be sure replace with FET from alternate source and take extreme precautions.2/ Please precice the inductor/trsf winding, core, design. The parameters on the schem are not sufficient, the magnetics may be affecting.3/ Place probes on the devices for V and I and bring up mains at lower lever, perhaps set Vout to 100..200 not 390 at first.Try to see the FET waves before it blows.Bon ChanceJon

author: jonpaul
author_rank: Super Contributor
timestamp: August 05, 2022, 12:39:10 pm
content: Farrington: I advise you to to study and learn the theory and practical issues in FET drive, FET protection and especially PFC design/That will save you a lot of tome and blown FETS.I recommend papers and seminar notes of my old friend Dr Richard REDL, of Switzerland, a fellow of IEEE and super Power Electronics guy.https://www.linkedin.com/in/richard-redl-30580012/?originalSubdomain=chHis work is on IEEE, PESC, PELS, Nuremberg, etc. and his seminar notes should be online .....Jon

author: Faringdon
author_rank: Super Contributor
timestamp: August 06, 2022, 02:02:21 pm
content: Thanks....Doing 1kW Boost PFC with UCC28070A. (240VAC, 390Vout, 60kHz)Will do “initial” power up on just 7W load, and with a 1200V IGBT (TO247) in place of the NFET. Also, Duty cycle will be limited to just 0.1. (The first actual power up resulted in the 650V NFET blowing up almost as soon as the PFC was enabled)The DG25X12T2 is the cheapest I can find on Farnell with sub 200ns fall time , tf (AKA ‘tail time’). None of the component sites allow you to sort IGBTs on tf. Do you know how you can find IGBTs suitable for 60kHz SMPS use? I suppose you just have to search on “td”, and hope that “tf” kind of follows it?Would you agree that the fall time will actually act in some way as a turn-off snubber for the IGBT? (albeit a highly dissipative one)DG25X12T2 IGBThttps://www.farnell.com/datasheets/3550990.pdf

author: jonpaul
author_rank: Super Contributor
timestamp: August 06, 2022, 03:34:17 pm
content: No IGBT experence I am an old tim,er....No production desing can depend on a vendor to do "binning" or testing.Do not rely on typocal specs, Tr, Tf are never specified or guaranteed.Your design must be worst case for all devices and parameters.Finally Tr Tf are functions of current, die temp, circuit, etc.Enjoy,Jon

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 06, 2022, 04:11:46 pm
content: Eon, Eoff are more useful measures with IGBTs. Includes turn-off tail. Eon can be waived in ZVS but not in CCM. Mind, Eon is usually measured with a PN junction rectifier; expect somewhat less if using schottky.Load is irrelevant if the controller is self-destructing on inrush. Maybe precharge the output above Vout(nom) and then turn on mains and the load. Still won't save anything if it starts oscillating, goes apeshit and blows up.Alternately, scale down by reducing C and increasing L and R, and adjusting feedback resistors. Run at say a couple amperes and 100V. Solve loop transients and compensation, then scale up by say 100% and try again.Tim

author: Faringdon
author_rank: Super Contributor
timestamp: August 07, 2022, 05:34:30 pm
content: QuoteThanks.....Looking at using the IGBT, IHW20N120R5, with the attached (LTspice) 1kW Boost PFC at 60kHz. (230VAC input).At mains peak, the Boost PFC collector current would be 9A at turn off. So for that, Eoff = 0.75mJ (page 9 of datasheet). However, that is for 600V….for us its only 325V (mains peak). As such, would we take Eoff as 0.75e-3 * 325/600 = 0.41mJ?Even then, that would mean 24.6W of turn-off switching losses for the mains peak bit. Seems an awful lot. I thought IGBTs were getting good for SMPS these days?IHW20N120R5 datasheet:-https://www.infineon.com/dgdl/Infineon-IHW20N120R5-DataSheet-v02_02-EN.pdf?fileId=5546d4614546039901458dd19d89437c

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 07, 2022, 07:49:17 pm
content: So it'd be around 96% efficient overall? Sounds pretty good to me.IGBTs aren't made for efficiency, they're made for cost. They have absolute highest power switching density in Si (without being something like an SCR). You can fit a lot of kVAs through a tiny chip.If you want more efficiency, use MOSFETs, large enough to get Vds(on) less than Vce(on). But use them carefully so that Coss doesn't dominate (Eoss is often spec'd these days, to the same end). ZVS / QR / valley switching may be attractive (e.g. UCC28065) but very high quality inductors are required.I would probably choose SiC for such a project, myself. Or even GaN, if small size or even higher efficiency is prioritized over cost. But mind, I'm also experienced enough to use them; if one lacks experience, a lower switching frequency and regular Si is probably the safer bet.Tim

author: Faringdon
author_rank: Super Contributor
timestamp: August 07, 2022, 09:03:58 pm
content: Thanks, I am thinking that an IGBT with a turn-off snubber could be a good thing. Because as the Vce rises just after turn-off....the inductor current will be diverted into the snubber capacitor rather than the IGBT.......this must be so, but it seems odd that you could beat the "tail current" problem (overlap of v and i at switch off) of an IGBT like this?

author: mzzj
author_rank: Super Contributor
timestamp: August 13, 2022, 07:02:00 pm
content: Quote from: Faringdon on August 07, 2022, 05:34:30 pmwhy would you select 1200V IGBT?try to google for ”pfc igbt” to get more reasonable candidates