Power efficient oscillator topologies? - Page 1
Forum section: electronics / rf-microwave

author: Teal
author_rank: Newbie
timestamp: August 15, 2019, 06:13:44 pm
content: I'm building an oscillator for a battery powered capacitive proximity sensor and I need it to have a high swing (>800 mV) at the output while keeping power consumption low enough. I'm feeding the output into the FPGA LVDS input so the oscillator must have a sufficient swing to drive it. Also it has to have large tuning range, a high ΔF/ΔC ratio and one side of the sensor must be grounded.Right now I'm using a cascode Lampkin oscillator (see picture below), it has quite high sensitivity but it outputs only up to 600 mV into 4 pF load, consuming 2 mA at 3.3V.I've built a cross-coupled class D oscillator and I got 3 times Vcc at the output while consuming only 1.2 mA! But it's a differential oscillator so I can't use it because the probe is not differential and it can't handle the whole possible capacitance range. I also saw aclass-C Hartley oscillatorthat has higher efficiency by the looks of it but I don't quite understand how it works and how to change the circuit for my application.So is there any oscillator topologies that are more power efficient than the one I'm using and still sensitive enough to capacitance changes?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 15, 2019, 10:23:20 pm
content: Does the frequency have to be so high?Apparently, LVDS inputs typically behave as comparators, with adequate gain and offset to sense differences of 10s of mV. Maybe not so well at higher frequencies, but in any case you probably don't need such signal strengths.Anyway, LVDS itself is only a few hundred mV, what do you need 800 for?Your circuit will have a few limiting parameters:- Since the output is coupled from the same transistors as the resonant tank is coupled to, the tank voltage will correspond to output voltage. So the tank voltage will be relatively high, and you need a high impedance and Q here to save current consumption.- You need high gain at low currents. RF BJTs are the best among traditional types, but also consider a SiGe HBT, or PHEMT.- These devices can operate at low voltages (a volt or so); consider a switching converter to save power, then, I don't know, maybe a transformer or impedance-matching-network output to get adequate voltage to the device pin?- Is your output coupling network resonant with the FPGA pin? And is its Q adequate for the operating range?- Speaking of, do you know the impedance of the FPGA pin? Does it have significant losses? It may limit your operating efficiency just as well.- Perhaps the FPGA pins have different response in different modes; could there be advantage going to, say, 1.2V VCCIO and using a plain CMOS logic input, instead of LVDS? (If nothing else, a 1.2V CMOS input should only require as much swing as you are currently after, i.e., 0.2 to 0.8 times VCC, or thereabouts.) Or any of the oddball types (SSTL, GTL, etc.), or other differential or referenced types (CML, ECL..).In a somewhat different direction:- Have you considered using the FPGA as an oscillator directly? Set one pin as input, another as output, string an inverter between them, and specify input hysteresis (if possible). Or three pins, one input and complementary outputs.In the complete opposite direction:- Have you considered instead using the capacitor as the integrating capacitor in a slope converter? This can be biased with very low currents (<uA), giving very low operating frequencies (<kHz?) with no need of inductors whatsoever. Subject to whatever your minimum sample rate is, of course.- Consider another transducer type entirely. There may be better tradeoffs possible. For example, a switch doesn't need to consume current at all. We have no idea what kind of proximity you're after!Tim

author: Teal
author_rank: Newbie
timestamp: August 16, 2019, 08:21:11 am
content: QuoteDisplacement sensor. Language barrier, sorry. Actually that's a device that measures heart and respiratory rate without making contact with a body. Also that's why the frequency is so high, I need high sensitivity, orders of femtofarads.QuoteI wish that was true...QuoteRight, I actually can get a balun, put it instead of L3 and essentially double the voltage by converting it from single-ended to differential. And it also simplifies biasing, no need to create an offset at both LVDS inputs, just offset the center tap.QuoteNo, it can't be resonant because of wide bandwidth. But I guess a bit of simple matching might help.QuoteYes, the oscillation is stable over the whole range. Hartley topology is better than Colpitts in that sense.Quote100 kΩ, 4 pF. I calculated the reactance at my frequency range and now I see that that's a quite heavy load. I'm actually thinking about building a low-power oscillator followed by some kind of switching amplifier for better efficiency. The distortions don't really matter since the processing circuitry works only with rising edges, it doesn't care about duty cycle.QuoteThe smallest VCCIO here is 1.8V, so LVDS wins. And I'm not comfortable in operating close to undefined state, I want something more reliable.QuoteThat's what I did initially. The phase noise of RC oscillators is terrible. But what if I try to build an LC oscillator, I wasn't thinking about that option actually..

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 16, 2019, 03:09:28 pm
content: The shit? +/- 0.3V common mode range? What kind of a dumb design is that? That's literally not even usable as an LVDS receiver. I'd dump it just from that alone.It might still be fine over whatever range anyway, and they just don't want to tell you about it. Only way to tell is to test it.Note that those arerecommendedoperating conditions, not the full spec. Characteristics are in another table.The ones I've heard this about, might've been Altera or Xilinx, or maybe the discrete receivers (made by various, TI, Fairchild, etc.).Tim

author: ogden
author_rank: Super Contributor
timestamp: August 16, 2019, 03:28:31 pm
content: Quote from: T3sl4co1l on August 16, 2019, 03:09:28 pmI do not see any problem here. That's I/O of *FPGA*! Sane designer would use buffer/driver for outer connections anyway.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 16, 2019, 03:38:25 pm
content: Quote from: ogden on August 16, 2019, 03:28:31 pmNo, if this is the characteristic, then this fully defeats the entire purpose of LVDS, which is to tolerate relatively large common-mode errors from on-board interference, crossing between power planes etc. This is why they usually have a 0-VCC common mode range.Let alone outside connections. Which don't need to be buffered, you don't really gain anything doing that -- unless you find a wide-CM-range receiver (I haven't seen any, but would be interested to!), you're going to have the same VCC range as ever. Just some clamp diodes for ESD, and good grounding of a shielded cable (HDMI is a good illustration of proper signal quality here).Tim

author: ogden
author_rank: Super Contributor
timestamp: August 16, 2019, 04:22:45 pm
content: Quote from: T3sl4co1l on August 16, 2019, 03:38:25 pmI am glad you mentioned HDMI. Only cheap *ss devices follow your advice to drive LVDS outer cable directly from FPGA which can exceed 100$ or even 1000$. Anyway it is much easier to add buffer such as TPD12S016 which will provide not only cable driver, ESD, but guaranteed conformance to standards.QuotePlease mention at least few devices, such information could be useful for many.Quote If +/- 0.3V common mode specs "limit" of modern FPGA LVDS I/O (JESD204B) does not allow you to safely route signals between boards/grounds of device, you seriously shall reconsider your occupation.

author: Teal
author_rank: Newbie
timestamp: August 17, 2019, 07:28:46 am
content: QuoteI'm using Lattice iCE40 because the code uses only 91 gates and 9 IO pins and Altera and Xilinx don't make low gate and pin count FPGAs anymore. And Lattice low range FPGAs even have LVDS. It's rudimentary though but better than nothing, I guess.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 17, 2019, 03:42:34 pm
content: Quote from: ogden on August 16, 2019, 04:22:45 pmOld example:https://www.onsemi.com/pub/Collateral/FIN1028-D.PDF0-2.35V CM range from 3.3V supply. Presumably it's got an NMOS diff pair or something like that for the input circuit.Again, they only guarantee you a span of +/-100mV, but they're good for much smaller than that. Probably they want to discourage their use as a comparator. Because that couple-nanosecond propagation kicks the crap out of anything else they offer in the same price range.QuoteI'd gladly discuss representative EMC situations but it seems you are just out for an argument. Good day,Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 17, 2019, 03:47:34 pm
content: Quote from: Teal on August 17, 2019, 07:28:46 amAh, iCE40. I don't see anything else in the datasheet, so it may well be their "LVDS" really is that awful.You might consider an external LVDS receiver chip or comparator then. Hopefully something exists that's modest in current consumption?Tim

author: ogden
author_rank: Super Contributor
timestamp: August 17, 2019, 04:31:26 pm
content: Quote from: T3sl4co1l on August 17, 2019, 03:42:34 pmThat's just buffer you said nobody needs. I did expect to see **device** having some function. ADC or some ASIC.QuoteYes I have argument indeed, it is against your statement where you say that LVDS25 I/O of Lattice iCE40 is shit & dumb design. So good day learning what LVDS actually is.Quote from: T3sl4co1l on August 17, 2019, 03:47:34 pmAccording to your reasoning, whole industry is designing awful LVDS interfacesAD9250 LVDS18 specs attached