verilog to vhdl - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: August 11, 2014, 02:26:47 pm
content: hi guysfor a lot of reasons i can't use verilog files in my tools, i got a very interesting paper but it is talking about a verilog source which i'd like to convert into vhdlit is a very long file, so .. converting by hands requires a lot of effort, for this reason i guess if there is around an automatic tool that translate verilog to vhdllet me know

author: legacy
author_rank: Super Contributor
timestamp: August 11, 2014, 06:31:48 pm
content: any idea?

author: miguelvp
author_rank: Super Contributor
timestamp: August 11, 2014, 06:48:36 pm
content: You said you can't use Verilog. But that's the only solution I can think off the top of my head, make a VHDL module declaration for that Verilog code and use it.Otherwise maybe there is a decompiler that could go from RTL or Netlists back to VHDL using the Verilog code as a guide to get the right names?.But I know of no such tool.

author: mrflibble
author_rank: Super Contributor
timestamp: August 11, 2014, 07:09:58 pm
content: All the vhdl <--> verilog converters I've tried in the past were total crap. From a language point of view you will have slightly more chance (well, slightly less of a non-chance really) with a vhdl to verilog conversion. VHDL is more strictly typed, so it's easier to parse it to something non-ambiguous.Time spent on the tool side is probably better spent on making sure your toolchain can handle mixed vhdl/verilog. Or let me guess, you have some version of ISE that does not support mixed language? If so then you might want to look at some workaround for that. That will cost you less time than the language conversion circus.

author: legacy
author_rank: Super Contributor
timestamp: August 11, 2014, 07:29:06 pm
content: Quote from: mrflibble on August 11, 2014, 07:09:58 pmISE is pretty able to support mixed language, i have used something similar for my hobby's toys, but this story is different and all the other tools i have (and that i can't change, it is not may decision, it's my boss) can't support VerilogIn short, i am afraid i will have to translate by hands, and … it is a very very very time consuming and ugly task

author: legacy
author_rank: Super Contributor
timestamp: August 11, 2014, 07:33:44 pm
content: a friend of mine has said that … it may be possible to have a look about "Icarus"perhapsusing code vhdl code generatorcould helpunfortunately he has never used it

author: free_electron
author_rank: Super Contributor
timestamp: August 11, 2014, 07:45:46 pm
content: send to verilog synthesizer, pull netlist. then from netlist pull vhdl.Quartus can do that. load the verilog code, export as a block , then reimport and save as vhdl.note that this becomes a netlist ! so essentially a bunch of gates wired together.

author: mrflibble
author_rank: Super Contributor
timestamp: August 11, 2014, 10:41:02 pm
content: Quote from: legacy on August 11, 2014, 07:29:06 pmThen tell your boss this particular choice of tools has increased cost (in terms of your time spent) as a linear consequence.Not that this will make you any happier, but oh well.QuoteSounds like it.Also, you haven't mentioned anything about this "doesn't do vhdl" toolchain other than that it doesn't do vhdl. That and should the end result be synthesizable, or is it only for simulation?Re: icarus ... could be. It is ages ago since I last used iverilog for anything. Waaay back it was fairly useful for mixing verilog + C simulation using PLI.... Quality for that was okay back then so it might be worth a try.

author: legacy
author_rank: Super Contributor
timestamp: August 11, 2014, 11:31:26 pm
content: Quote from: mrflibble on August 11, 2014, 10:41:02 pmsynthesizable, it's an ugly "radiation hardened" soft core all written in Verilog

author: legacy
author_rank: Super Contributor
timestamp: August 11, 2014, 11:32:01 pm
content: @free_electronok, i will get it a try, thank you for the advice!