4 Layer buck converter layout - Page 1
Forum section: electronics / projects

author: anishkgt
author_rank: Frequent Contributor
timestamp: August 14, 2020, 10:03:28 am
content: What is the standard layout for a 4Layer PCB that everyone follows for a buck converter or similar ? I was planning to go like thisSignalSignalGNDSignalSince inductors and FETS are nosiest of all i was thinking on having them on the top layer. Second layer for routing the Gate signal, voltage feedback, current sense from and to the IC and other routes that are not possible on the top layer. Third would hold the GND plane with no routing. A reasonably large exposed layer on the First and Fourth layer for the mosfets to dissipate heat. Would this be a bad idea ?Should i have the GND in the Second layer to keep the path to GND the shortest ?

author: jkostb
author_rank: Regular Contributor
timestamp: August 14, 2020, 11:53:44 am
content: Your stackup is not best for SMPS. You need a ground plane just below your inductor, input and output capacitor of buck converter for best EMC behavior. You must keep critical loop area of buck converter small. So usual stackup is then signal - GND - Power - Signal. Datasheets usually also give recommendations. Further ground pour your top and bottom layers with GND and stitch all ground together with via's.

author: KT88
author_rank: Frequent Contributor
timestamp: August 14, 2020, 01:17:06 pm
content: there is no universal rule as far as I can tell... The requirements depend on the design constraints. To give a few examples - if you have a simple low power regulator like an ADP2108 or alike you have only three parts to add to the IC which lets you get away with using only one layer (top) to place and route the whole circuit. Below that you would have a ground layer and the rest won't really matter anymore.If you have a high power multi-phase buck you have not only the challenge of keeping loop-areas small but also heat dissipation becomes a challenge which spilts into getting the heat away and maitainig a large enough copper cross-sections to avoid overheating and parasitic inductance. Finding a good placement for a lot of bulky parts is another part of the game...If you are in between these extremes you want to minimize loop areas in the fisrst place. Part of that is to avoid vias (adds parasitic inductance) for critical pathts - in case of a buck the input cap has the highst priority. Next would be the output cap. Input cap and output cap return should meet in a star point which is in many case the EP of the package. Ideally you saty on the top layer with these traces...The EP pad should also contain some (mainly) themal vias that tranport the heat to the bottom side where an appropriately sized ground area could then dissipate the heat.CheersAndreas

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 14, 2020, 02:42:59 pm
content: I've done some special-case routing like that before, but I doubt it makes much of a difference anyway. I made it specific to the route. Definitely don't reserve a whole ass layer for just two connections.Concentrate on understanding where current flows and what the loop inductances are. You should find that about three layers is ideal, of course we need four for manufacturing purposes, so you can put whatever you like on the last layer.Tim