SMPS design questions for RF amp EER / Kahn technique - Page 1
Forum section: electronics / projects

author: mark03
author_rank: Frequent Contributor
timestamp: June 27, 2018, 11:51:02 pm
content: I've been playing around with some simulations of switch-based amplifier topologies for QRP (low-power, 1-10W) transmitters in the amateur shortwave bands. Here is a simple example, a "class E/F_odd" which achieves better than 90% efficiency in LTspice with tiny GaN devices and logic-level drive:(There is a much higher-power worked example here, from the same people who wrote the definitive paper on the subject:http://www.its.caltech.edu/~mmic/reshpubindex/papers/scott01.pdf)I think this type of transmitter is particularly attractive for battery-powered portable operation, which is enjoying a surge in popularity right now, and a natural fit to SDR architectures where you put as much of the radio as possible into the digital domain.The obvious limitation, that you can only produce CW or constant-envelope signals, has a workaround known as the "envelope elimination and restoration" (EER) or Kahn technique. Given baseband I/Q, you drive the switches with the phase-modulated square-wave carrier and modulate the supply voltage according to sqrt(I^2+Q^2). (The "elimination" part of the EER acronym comes from the assumption of an analog-input, analog-output amplifier; in an  fully digital transmitter you would synthesize the necessary signals inside an FPGA instead.)The drain supply modulator requires a switch-mode power supply with sufficient bandwidth to reproduce the envelope signal. This is a real challenge for modern 3G/4G mobile standards with multi-MHz bandwidths, but for amateur radio applications 10 kHz would be sufficient. I've also read that it's common to design with a linear regulator in parallel to "take up the slack" at high frequencies where the SMPS cannot slew fast enough, and perhaps also to handle dips in the envelope below the bottom end of the SMPS range. For example, implementing SSB modulation would require a modulator which can seamlessly ramp all the way down to zero.For the sake of discussion, my constraints are:* Single-cell Li-ion power supply, 3.6V* SMPS output voltage peaks >= 12V @ 1A (lower currents at lower voltages)* SMPS output bandwidth >= 10 kHz, but it could be fun to aim higherFirst question would be, Is this crazy difficult, really easy, or somewhere in between? My SMPS design experience is mostly limited to integrated buck or boost regulators with internal switches. I have some familiarity with the basic principles, and I can mostly understand data-sheet discussions on loop compensation, at least well enough to follow the instructions and get a working design. But this is definitely outside my skill area.In papers discussing these supplies, I frequently see reference to having the switching frequency at least 10x the modulator bandwidth. Since there are plenty of integrated solutions running at 1-2 MHz, does this mean I can adapt them to my purpose with suitable loop compensation? One problem is that I need a boost converter, and apparently the boost topology has an inherent right-half-plane zero which forces a rather limited bandwidth for stability. I could cascade boost-then-buck, although I hate to take the efficiency hit.In researching this I did learn about an entirely new (to me) product category at TI, the "RF DC/DC converter". See, for example, the LM3209:http://www.ti.com/lit/ds/symlink/lm3209-g3.pdfThis would be an almost a perfect solution except for it being a low-voltage part (0.6-4.2V output range) and the inconvenient DSBGA packaging.Any pointers, google search terms, reading suggestions? Thanks.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 28, 2018, 01:51:00 am
content: Not hard at all, this would do:https://www.eevblog.com/forum/projects/building-a-simple-switching-circuit/msg1252706/#msg1252706You even have your choice of voltage, current or raw PWM modulation (depending on which opamp you input to / replace, and how much protection you want to remove..). Obviously(?), for a [common ground] buck application, you need a bootstrap gate driver, instead of the parallel logic gates.A third one of those GaN FETs would do, or a fourth even, for synchronous buck -- more responsive especially when slewing down to zero, and not a big efficiency hit because of the fast switching.The SMPS should run at a subharmonic of the carrier, so the central spur hides with the carrier (you can null the carrier balance later), and its spurs are relatively easily filtered with the output bandpass.Tim

author: mark03
author_rank: Frequent Contributor
timestamp: June 29, 2018, 12:37:13 am
content: Thanks T3sl4co1l!That's a really nice tutorial. I'll have to study it a while to pick up all of the nuances, but would I be correct in assuming that the main advantage of the discrete solution over a packaged switch-mode controller from Linear or TI, is in the educational benefit? I think many (most?) of the integrated solutions are using current-mode control and some let you compensate the control loop yourself.I am still concerned about the hard limit imposed by the RHP zero at R_load * (Vin/Vout)^2 / (pi * L). I guess it will let me achieve 10 kHz BW without too much trouble, although it would be fun to contemplate a design capable of more.

author: dmills
author_rank: Super Contributor
timestamp: June 29, 2018, 11:19:31 am
content: Note that the elephant in the room for EER in SSB type applications is that as the drain supply falls towards zero, the device capacitance rises rapidly, this causes phase distortion raising EVM.I have been playing with something doing envelope tracking (But not full on EER, the RF parts run in class AB), where the supply swings from about 12V to about 50V as the envelope varies.This avoids the very low voltage region where device capacitance rises massively, while still getting a nice efficiency gain because the drain impedance remains close to correct over a better then 10dB power range.My latest design just uses a single turn winding on the DC injection bifiliar feeding a fast rectifier to sample the RF voltage being produced at the drains and feed it to the power supply controller, this has the advantage that a low Z load will reduce the supply voltage to suit.Regards, Dan.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 29, 2018, 06:21:56 pm
content: Quote from: mark03 on June 29, 2018, 12:37:13 amSome do, yes -- but few expose anything else. Peak mode control is very popular, because it's easy, but provides poor control of the average current, so you need to add your own external loop if you want a precision current limit. It's hard to use anything in a slightly different topology or application than intended.QuoteMy example is average current mode, not peak, so that's not a problem.Quote from: dmills on June 29, 2018, 11:19:31 amProbably easy enough to get away with, using GaN at SW frequencies. Wouldn't be so easy at VHF+, and definitely not with Si LDMOS or whatever. (If you were really committed, I suppose you could put some high power varactors on the drains, carefully adjusted so they always have complementary capacitance to the drains. You could at least get the average frequency right, but you'd still have distortion.)Tim

author: mark03
author_rank: Frequent Contributor
timestamp: July 23, 2018, 05:05:22 am
content: I made a test board to verify the LTSpice simulation; summary here:https://www.eevblog.com/forum/rf-microwave/gan-class-ef_odd-hf-transmitter-logic-gate-drive-14w-out-90-efficiency/