4-layer board - power plane or routed power? - Page 1
Forum section: electronics / beginners

author: jrs45
author_rank: Regular Contributor
timestamp: June 02, 2020, 08:58:11 pm
content: I most of the reference designs I've seen, from top to bottom is signal-gnd-power-signal, and the power plane is usually flooded with the various power supplies needed, segmented as necessary.Wouldn't it be better to route the power with (fat) traces on this plane, and flood the rest with ground? Otherwise there is no good coupling between the bottom layer signal traces and their ground reference.

author: tkamiya
author_rank: Super Contributor
timestamp: June 02, 2020, 09:37:58 pm
content: It really depends on the circuit and its purpose.If you need an low impedance power source and dealing with fast signals, it may not be a choice but to use a layer for power and another layer for ground. Using wide width has a limit. Say fast rising signal going at ns or less, and there are hundreds of devices, fat traces won't cut it. I've seen an entire layer or have a bus bar on top of PC.I have to say, PC circuit design is more of an art, and good intentions doesn't always work out. It's sort of like do what you gotta do to get the job done with "rules" as a guide.

author: thm_w
author_rank: Super Contributor
timestamp: June 02, 2020, 09:42:14 pm
content: Can still couple to the power plane.Any stackup choice is a compromise.https://resources.altium.com/p/should-you-use-your-power-plane-as-a-return-pathhttps://electronics.stackexchange.com/questions/243347/ac-coupled-rf-microstrip-routing-over-power-planehttps://electronics.stackexchange.com/questions/26577/microstrip-over-power-plane

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 02, 2020, 09:50:37 pm
content: What do you mean none? -- the fact that the power planes are in close proximity to ground, and frequently bypassed to it, makes them an equivalent AC ground.Routed power may still need a lot of local bypasses.Yes, that's right -- one of the advantages of planes is not needing local bypasses, or as many. Appnotes never assume this is good enough, mind, but they also don't want to get angry calls about poorly-followed advice. That, and the general quality of appnotes is poor enough that I wouldn't expect most authors are aware of PDN (power distribution network) analysis, or how to do it...Likewise, if you do route a board in that way, the ground fill doesn't need many stitching vias. Stitch inside corners, peninsulas, gaps, that sort of stuff -- but no need to go crazy with it. There may be enough vias in the design already, not to need many/any additional ones.Mind that this all depends upon two things:1. Signals routed above the plane layer, are not corrupted by discontinuities in the planes.2. The PDN, at each load point, has a low enough impedance, over a sufficient frequency range, that no devices have functional issues.#1 is mainly a high frequency signal quality problem, i.e., sub-ns edges in digital logic, or very high bandwidth or sensitive analog signals. A trace couples to what conductors are around it, inducing an image current; if that image current is interrupted, say by a slot between planes -- it must spread out along and under that slot, and eventually be returned somehow to the trace path.When power planes are wide and the ground plane is contiguous, the power planes couple to ground, and the signal current spreads out quickly under the gap and back out. Effectively the trace has an impedance discontinuity where it's higher for a short length. For typical plane geometry, this is on the order of 10ps -- you won't notice it for 100ps digital edges, and you probably won't notice it with <1GHz, say <8 bit ENOB, analog signals.The current can be returned through a shorter path, if vias and a bypass capacitor are placed directly beside the trace, effectively stitching the gap between planes with an AC short (the cap). This extends performance further, so, say, maybe it's good for 1GHz and 10 bits (which I think is about all the bits you're going to get at 50 ohms, anyway?).#2 is partly doing the same thing -- a signal current, launched into a trace, is sourced from the part's supply/ground pins. When these currents are sunk to the planes quickly, with short length traces and vias, there isn't much to worry about. Bypass caps don't have to deal much with high frequency currents (there isn't anything you can do about ~100MHz+ currents on the PCB, anyway -- pin and bondwire strays dominate up there), and they are only needed to keep the overall plane well damped at modest frequencies (1-100MHz say).Of course, if a power plane is unavailable, those transient VCC currents must be returned through nearby bypass caps, to the ground plane. Hence, you likely need local bypass for routed power.How much, and which way, depends on the load. If the part is switching large currents, it probably needs a lower supply impedance. Parallel bus drivers, display drivers, FPGAs with lots of parallel IO -- those sorts of things are likely suspects.If it's switching little current, or doing it slowly, you might not need any local bypass at all, and can depend upon nearby or overall PDN impedance to do the job. Old school CD4000 logic (and 74LS and 74HC to a lesser extent) might not need local bypass. Routed power, with a cap every couple of chips, is fine. 74LVC and faster, use local bypass and/or a plane.Note I've been concentrating on parallel buses and single-ended signals. Here's where differential really shines:a. Where both traces cross over a discontinuity, a common-mode error is introduced.As long as the two traces experience the same disturbance, with the same timing (the signal wave crosses the discontinuity at the same time for both traces, i.e., the lengths are matched from the transmitter, to the discontinuity, to the receiver), and the discontinuity isn't large enough to violate the receiver's common mode range -- the signal will be received perfectly with no error.b. When the differential pair is load-terminated, the transmitter drawsconstant current-- no transient current drawn from its power pin, only the little amount needed to operate internal circuitry. This vastly eases the job of PDN design -- especially important because at these rates (GHz), there's very little we can do on board, bypass has to be handled inside the chip itself! (Which it is, say by alternating metal layers for power and ground nets, or by placing low profile capacitors on the die or interposer.)Plus a variety of other improvements (signal path compensation, reclocking, error correction, etc.), this is why differential signaling is king at high rates -- Ethernet, USB, PCIe, HDMI, etc.Tim

author: jrs45
author_rank: Regular Contributor
timestamp: June 03, 2020, 02:40:36 pm
content: Quote from: tkamiya on June 02, 2020, 09:37:58 pmI would be surprised if there were much difference between a power plane area and fat traces, at least when local bypass capacitors were (always) used?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 03, 2020, 04:17:51 pm
content: Quote from: jrs45 on June 03, 2020, 02:40:36 pmAs the width of trace goes down -- you can consider a plane as a very wide trace -- at some point its transmission line impedance becomes high enough, its inductance/length begins to matter. Now you have to worry about the local bypass cap resonating with it.If you have a linear route between loads, with local bypasses more or less evenly spaced, you've formed a lumped-equivalent transmission line, with lowpass cutoff 1 / (2 pi sqrt(LC)) (for unit L and C) and impedance Zo = sqrt(L/C). If the transmission line isn't well terminated (by a bulk capacitor at one or both ends, with ESR = Zo), it will have an impedance peak corresponding to its electrical length (roughly the cutoff for total L and C).A subtle refinement on plane impedance:The plane itself has a low characteristic impedance (~ohms?), but it's not a very useful measure because, how could you connect to the whole plane at once -- in a single wavefront? It's too wide, it's not like you can sink a row of vias into it and measure that way, any wave has to propagate across the width of the connection first. Or if you make a tapered horn connection, you can't remove the length of the horn.If we consider the plane as infinite, then we can ignore reflections, and it'll take infinite time just to measure Zo = 0 ohms (how long it takes for the wave radiating out from a via to sense the full width of the plane). For finite times/frequencies, the fact that waves move radially is key.Indeed, the equivalent inductance of a coaxial cavity goes as ln(R/r) * h * mu_0. What does that come from? Well, consider a via of inner diameter r, a plane pair of radius R, and a plane separation h. In this case the planes are shorted together at R, so that our complete circuit is a (DC) short circuit, from via, down to the bottom plane, radially outward to the outer wall, up to the top plane, and back inside up to the source (which we'll assume is a perfect connection, but of course will be another via itself; that via connects on the outside of this cavity so we don't need to include it in the calculation yet).If we measure the low frequency equivalent impedance of some such cavities, we find that the inductance varies as the ratio R/r, and it varies fairly slowly -- that is, for r = 0.5mm and R = 50mm, it's maybe 6.6nH, and for R = 500mm, it's only ln(10) ~= 2.3 times higher or ~15nH. And that 15nH is connected across nearly the full plane capacitance of that area (a 1m wide PCB) so it's quite a low impedance indeed.And of course for vias, connecting traces and component bodies, we add the constant ESL of those structures.The full impedance plot of a plane, as measured from a connection in the middle, will be something like: at high frequencies (below the first cavity resonance), there's an ESL corresponding to about the plane's dimensions as above; at some middle frequency, impedance will reach a minima, the effective series resonance between that ESL and plane capacitance. At low frequencies, impedance is rising as the plane capacitance dominates.So we can clearly see some advantages we can make in circuit design: if we need a low ESL connection to the plane, we can use multiple vias; assuming the waves they're carrying arrive at the same time. A pattern of two or three vias around one or a pair of bypass caps, has an effective radius much larger than just one, so the ESL is much lower. We place these vias adjacent to the capacitor pads, and the VCC and GND vias close together as well, so that there's very little trace length, and minimal component body length.At medium frequencies, we can treat the plane as an ideal conductor between all connections, with those connections having some local ESL that dominates at high frequencies. At low frequencies, the plane has no effect (just a tiny capacitance, some nF -- hardly anything to be concerned about in the MHz or below), and this is where our distribution of bypass caps, and bulk caps, takes over.And we can interpolate between plane and trace conditions, by considering what happens as the plane width becomes narrow enough to reflect waves inside -- rather than a logarithmic impedance at high frequencies, it flattens out, and behaves like any 1D transmission line. The impedance may be low enough that we don't need to worry about resonance (namely, sqrt(ESL / Cbyp) < ESR), but at some point it will be high enough to matter, and we will need both local bypasses and damping (the linear routed supply case, for example).Likewise, we can consider what happens on boundary conditions -- vias near an edge of the plane will simply get ~1/2 the benefit, and vias near a (square) corner get ~1/4. Avoid placing demanding loads in these locations.Tim