Noise from 74HC logic gates - Page 1
Forum section: electronics / beginners

author: TheCalligrapher
author_rank: Regular Contributor
timestamp: July 18, 2023, 08:06:24 am
content: A simple PWM signal generator, built from a binary 4-bit counter (74HC393), a 4-bit 3-way comparator (74HC85), a register specifying the duty cycle (temporarily implemented by 4 manual DIP switches) and an inverter (74HC04). The counter is driven by an external 400 kHz square wave generator, which means that at the output we should get 25 kHz PWM, controllable in 16 steps (from 6.25% to 100% duty cycle, no 0%).It works as intended. However, the output signal looks rather "dirty", as can be seen on the first oscilogram. This can be alleviated somewhat by adding a bunch of bypass capacitors to power supply pins of each IC. However, no matter what caps I choose as bypass and where I place them, I can't get rid of some tall signal spikes in the output signal (visible in the first oscillogram, pink channel, narrow and high vertical spikes coming up during each zero PWM period).But If I connect the inverter input to the ground by a 1nF capacitor, these spikes will disappear (see the second oscillogram). Obviously, I simply filter these spikes out of the signal line at the expense of introducing some delay (completely undetectable with 1nF cap).So, I wonder, is filtering the signal lines actually an acceptable way to fight noise? Is it done that way in real designs? Or is this a "loser's way out"? Perhaps one should strive to resolve such issues by enhancing power supply instead?

author: wasedadoc
author_rank: Super Contributor
timestamp: July 18, 2023, 08:35:10 am
content: 1. The decoupling caps should be directly across the power pins of the ICs. Pins 1 and 16. One end is right at pin 16 but the other end has a long route back to pin 1.2. The large spikes are present because the outputs of the counter do not change at precisely the same time. There is a brief period when the comparator sees a set of states which is neither of the true states the counter is coming from or going to. A proper fix is to put the comparator output through a clocked latch. The latch should operate on the opposite polarity edge to that of the counter.

author: Shonky
author_rank: Frequent Contributor
timestamp: July 18, 2023, 08:57:06 am
content: I would guess the problem you're having is that the counter has a race condition on its outputs when two outputs change. This may be due to propagation delays in the outputs.eg when going from 0011 to 0100 three bits need to change at once. If say the third bit is faster you might see 0011 > 0111 > 0100 with the middle stage being very short.A Gray code counter should resolve this problem as only 1 bit will change each time. A latch synchronised to the clock is better as the Gray code won't work for your PWM concept.If your filter works its probably good enough but may need tuning and may vary from circuit to circuit.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 18, 2023, 09:14:00 am
content: Besides the decoupling there can also be interference from the ground side of the scope probes. The large loop can pick up some of the clock signal and also the common ground can cause coupling.The limited sampling rate / decimation in the scope can make the glitches look noisy / unstable.

author: srb1954
author_rank: Super Contributor
timestamp: July 18, 2023, 09:19:39 am
content: Quote from: TheCalligrapher on July 18, 2023, 08:06:24 amThe "tall spikes" you are seeing are decoding errors resulting from propagation delays between stages in the HC393 counter. This counter is a ripple counter, which means that each stage is clocked by the previous stage rather than sharing a common input clock so all outputs don't change simultaneously with the main clock signal. At major transitions say, when going from a count of 0111 to 1000, the least significant bit (Q1) will change first and this in turn toggles the next least bit (Q2) and so on. This sequence of changes "ripples" through the counter hence the name. If you looked very closely at the sequence of outputs you would see values of 0111, 0110, 0100, 0000 before finally settling on the correct value of 1000. The incorrect intermediate values are being picked up by the 74HC85 comparator generating the spurious narrow spikes on the its output.There are several ways of getting round this problem:You can filter out the narrow spikes with a capacitor on the HC85 O/P. This is OK for non-critical applications but will be somewhat sensitive to the IC paramaters and you may need to tune the capacitance for the worst case ICs or variations of the clock frequency.You can re-time the PWM signal by passing the O/P of the HC85 comparator though a D-type FF (HC74), which is clocked on the opposite edge of the clock to the HC393 counter. This gives a half period of the clock for the propagation delays through the counter and for its O/Ps to settle and a valid O/P from the HC85 can be latched by the HC74. This works well for all but the fastest clock frequencies where the total propagation delays through the HC393 and the HC85 approach half a clock period.You can substitue a synchronous counter e.g. 74HC163 for the HC393. With a synchronous counter all O/Ps change simultaneously at the clock transition and there are no spurious O/P codes, except perhaps for extremely short glitches due to minor variations in propagation delays between individual O/Ps. These extremely short glitches are unlikely to propagate through the HC85 and subsequent stages.

author: Benta
author_rank: Super Contributor
timestamp: July 18, 2023, 10:32:24 am
content: As srb1954 says: don't use ripple counters, it's looking for trouble. Always choose synchronous counters.In this case, 74HC191 or 74HC163. Your spikes (aka "runt pulses") will disappear immediately.

author: langwadt
author_rank: Super Contributor
timestamp: July 18, 2023, 10:42:14 am
content: Quote from: srb1954 on July 18, 2023, 09:19:39 amyou don't need the opposite edge, hold time for a hc74 is ~0 the output of the counter and comparator can't change before the edgeunless you have a time machine;)

author: RoGeorge
author_rank: Super Contributor
timestamp: July 18, 2023, 11:21:27 am
content: First words from the datasheet: "The ’HC393 and ’HCT393 are 4-stageripple-carrybinary counters."Ripple-carry counters, sometimes called asynchronous counters, means the internal flip-flops will change their state one after another, only one FF at a time, instead of flipping to the new number all at once.This will imply that during a counting transition (and for a very short time, 30-50ns or so, equal with the propagation time through a flip-flop), other values will appear at the output, which may throw the following circuits in an unexpected state, and that's why the spikes on the oscilloscope.Either use a synchronous counter (for a synchronous counter all FF are controlled by the same input edge of the clock, so all FF will flip at once), or use a second circuit as a 4 bits latch, to sample all 4 bits at once after giving them some time to settle (usually the latch is wired to sample at the next edge).

author: langwadt
author_rank: Super Contributor
timestamp: July 18, 2023, 11:34:58 am
content: Quote from: RoGeorge on July 18, 2023, 11:21:27 amI don't see how a synchronous counter can guarantee no glitches, that would depend in the comparator. The FF needs to be on the output of the comparator

author: Benta
author_rank: Super Contributor
timestamp: July 18, 2023, 02:49:21 pm
content: Quote from: langwadt on July 18, 2023, 11:34:58 amPerhaps try it yourself? I can assure you it works.Theoretically, you can have some skew between the outputs of a synchronous counter, but this skew is so small that it's of no consequence. Gating together the outputs (like in the comparator) may generate small spikes, but they are so narrow and contain so little energy that they "die" in the circuit I/O capacitances.

author: langwadt
author_rank: Super Contributor
timestamp: July 18, 2023, 03:14:56 pm
content: Quote from: Benta on July 18, 2023, 02:49:21 pmsure it will probably work, but that's not guaranteed, a FF on the output of the comparator is guaranteedit is the comparator that will have spikes, relying on I/O capacitances to mask them in no different than sticking a cap in the output of the comparator

author: Benta
author_rank: Super Contributor
timestamp: July 18, 2023, 03:28:18 pm
content: I think you need a little practical experience here instead of flogging a dead horse. Thousands of practical designs work like this. But OK, if you want to add unnecessary extra FFs, go ahead. It no longer engineering, but overkill. It's your (and your employer's) money.

author: RoGeorge
author_rank: Super Contributor
timestamp: July 18, 2023, 03:33:12 pm
content: Quote from: langwadt on July 18, 2023, 11:34:58 amThe advice about adding a 4 bits latch was a way to make a ripple counter to flip all bits at once.The comparator would still remain an asynchronous CLC dealing with many bits at once, which might create glitches. Any eventual gltches will probably be too small to be seen on the oscilloscope, but some other circuit following after the PWM might still be affected. Indeed that won't guarantee no glitches, only a synchronous design can do that.A single D-type FF at the output of the comparator would turn the entire PWM circuit into a synchronous design, so your solution is the proper fix.

author: langwadt
author_rank: Super Contributor
timestamp: July 18, 2023, 04:32:28 pm
content: Quote from: Benta on July 18, 2023, 03:28:18 pmyou missed the point the difference between; guaranteed to work by design, and likely to work in practice

author: wasedadoc
author_rank: Super Contributor
timestamp: July 18, 2023, 05:05:05 pm
content: Quote from: RoGeorge on July 18, 2023, 03:33:12 pmAs stated in the very first reply.

author: srb1954
author_rank: Super Contributor
timestamp: July 18, 2023, 10:23:11 pm
content: Quote from: langwadt on July 18, 2023, 10:42:14 amI prefer to design circuits so as not to rely on approximately zero hold time specifications. I have wasted far too much time in my career chasing down weird race conditions and metastability problems with chips that don't quite meet the manufacturer's datasheet hold time specifications.As it happens the HC393 and the HC74 clock on different edges so it is simplest to just connect them to the same clock line and that will automatically introduce the desired half clock period settling time. To have the HC393 and HC74 clock on the same edge would require the clock signal for one of the devices to be inverted. Put the clock inverter on the wrong device and you will get a whole host of timing problems to worry about.

author: langwadt
author_rank: Super Contributor
timestamp: July 18, 2023, 10:33:59 pm
content: Quote from: srb1954 on July 18, 2023, 10:23:11 pmbut the counter and comparator each a has a +10ns TpdQuote from: srb1954 on July 18, 2023, 10:23:11 pmif it saves an inverter then there is no reason to not use the other edge, other than running out of time

author: TheCalligrapher
author_rank: Regular Contributor
timestamp: August 10, 2023, 06:36:30 pm
content: While it is true that a synchronous counter does not and cannot really guarantee perfect synchronicity of transitions at its outputs, it will all obviously depend on the desired operating frequencies of the system. In my case we are talking about 400 kHz clock. At 400 kHz replacing 74HC393 with 74HC163 (per srb1954's suggestion above) does completely eliminate the ripple artefacts described in the original post.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 10, 2023, 11:37:30 pm
content: If you want to make something reliable, you can not rely on "practical experience" as Benta suggests.The only proper way is to calculate propagation delays and allow for them. For example by only sampling the output of the 74HC85 after this delay. Usually the next chip has some latch or clock input.74xx logic is very old technology. The chips are simple building blocks, and adding "glitch free" circuits to each and every chip would make all the stuff so slow that it is pretty much useless. Using a synchronous counter would reduce the glitches a lot, but does not guarantee there are none. What are the specs for the 74hc85 when multiple inputs toggle within the propagation delay of the chips?When designing logic circuits to be reliable, there are also other dragons about. Do some research into the area of "metastability". Metastability is a quite big horror for logic circuits and you need synchronizers to clean up the signals. Usually these are two cascaded flipflops clocked after each other, or clocked from the same clock if their propagation delays guarantee this can be done safely.Truly, you can build "working" circuits on such rule of thumb, and they may work 99.98% of the time.Now consider you are a computer or TV manufacturer and you have sold a million products. That means that 200 of your products will be returned because they are faulty.When designing reliable products, you also have to allow for differences in timing and other parameters between batches of parts, changes in parameters over temperature differences and a whole list of other things.There is a huge difference between a hobbyist tinkering in their garage and an experienced designer that designs reliable products. The hobbyist tinkering in his garage has a much simpler job, and I admit, somewhere between sometimes and quite often it is "good enough".

author: DavidAlfa
author_rank: Super Contributor
timestamp: August 11, 2023, 02:08:55 pm
content: Add a latch to the comparator output, like the 74hc373.Take the input clock and connect it to the latch enable input through a RC filter, for example 1K and 100pF (You'll need some trial and error).When the clock rises, the counter and comparator will make their stuff, but the clock signal will be slighly delayed for the latch, so it will always sample a clean signal.You could also add a small delay by routing the clock through four of the unused 7404 gates in series, each gate adds ~10ns so it'll be 40ns, hopefully enough, otherwise just use the RC method.A 74HC74 can also fit this job.

author: langwadt
author_rank: Super Contributor
timestamp: August 11, 2023, 03:41:20 pm
content: Quote from: DavidAlfa on August 11, 2023, 02:08:55 pman RC delay is a hack and it shouldn't be needed, the comparator output can't possibly change until after the delay thought the counter and comparator

author: DavidAlfa
author_rank: Super Contributor
timestamp: August 11, 2023, 04:09:43 pm
content: The counter outputs won't change at the exact same speed, neither the comparator input circuitry.So it's very possible to get nanosecond glitches.I've seen such glitch filter everywhere, basically a simple nand gate, one input connected directly and the other with a small RC filter.

author: langwadt
author_rank: Super Contributor
timestamp: August 11, 2023, 04:46:01 pm
content: Quote from: DavidAlfa on August 11, 2023, 04:09:43 pmbut with a FF at the output clocked by the same clock it doesn't matter, the FF samples the output at the edge, all the changes happens after the edge

author: DavidAlfa
author_rank: Super Contributor
timestamp: August 11, 2023, 06:20:30 pm
content: Ah, the 393 takes the negative edge, thought it was in the positive one.Then no need for any RC.The 373 and the 74 work in the positive edge, can be connected right to the clock signal.Edit: The glitches happen even in the simulationBlue is the comparator output, red is the 74hc74.

author: langwadt
author_rank: Super Contributor
timestamp: August 11, 2023, 06:45:51 pm
content: Quote from: DavidAlfa on August 11, 2023, 06:20:30 pmit would also work if the counter worked on the positive edge

author: BillyO
author_rank: Super Contributor
timestamp: August 11, 2023, 07:59:55 pm
content: I designed something very similar to this about 10 years ago. It's an 8-bit PWM generator for use in a micro computer system I designed too.It uses the 74HC590 counter which has a built in register which prevents the problem you are seeing. Plus, it has 16x the resolution.