74HC-Series chip behaving weird on PCB - Page 1
Forum section: electronics / projects

author: GabrielWeingardt
author_rank: Newbie
timestamp: October 10, 2025, 11:40:07 am
content: Hello all,across the last 3 years, I've build a 6502 computer with a video card with 74HC-Series logic.The project developed on a breadboard. I copied the design to a schematic and drew a PCB.This was revision 1 of the board, which worked rock-solid. I've used a track width of 0.254mm andspacing of 1.27mm. I also forgot to add a ground plane with that revision, which I realized 5 minutes afterordering the PCB. But even with that, the board worked rock solid.Here comes revision 2, which added more features to the computer side, with the video card staying almost the same.I decided to cramp the IC's a little together. Still with a track width of 0.254mm, but the spacing being reduced to 0.635mm.Even the placement of the video card chips was almost identical to revision 1.But in revision 2, I've decided to add a ground plane and I think this is where I screwed up:I let KiCad plot the ground plane on both layers. (This PCB is just 2 layers).I've read online, that something like ground-looping exists, but I'm unsure, because I frequentlyconnect the two ground planes together with the IC's GND pin.Secondly, there are not major ground islands.I have never made a PCB with a ground plane, so I don't know if I did anything wrong there.Okay, let's get to the actual problem I'm experiencing:The 74HC574 (U40, page 11 in schematic: M Register ) is behaving weird.The CPU can write data to it, but it seemingly gets lostand replaced with random values after a random amount of time. The CPU only writes to this register once.(Which I can verify using the scope).There are also no pulses on the latch pin of the chip. Power is also stable at +5V and I've addedenough decoupling capacitors across the board. Also, the computer and video card don't share the samepower regulator. They have their own (I've done this to mitigate noise, which is visible in the VGA color).The output pins of the latch are not in a "floating" state. Even when it latches these random values,they are represented as 0V or +5V with no weird state in between the switches.Note: The video card works fine, it's just this little chip that's causing problems. I've also tried replacing it with no results.I've included the schematic in the attachment. The PCB and KiCad files are downloadable on my website.PCB Image:https://www.weingardt.dev/ls7pcb.pdfKiCad files:https://www.weingardt.dev/ls7files.zip.I don't know any further, especially as it worked flawlessly on a breadboard.Thank you all in advance and have a nice day!

author: Benta
author_rank: Super Contributor
timestamp: October 10, 2025, 03:40:19 pm
content: Check the compatibility of your logic voltage levels.It's likely that you need to use 74HCT instead of 74HC.

author: GabrielWeingardt
author_rank: Newbie
timestamp: October 10, 2025, 05:17:20 pm
content: I don't think it's due to the voltage level.The board is running on +5V, with the power being stable with no ripples.And it's not a high frequency part, as the others are.Like the sync circuitry works on 20MHz.I've looked how I routed the track of one of the latches outputsand it's routed near the 20MHz line from the oscillator.But as again said, every pin of the latch looks good on the scope.74HC parts are rated up to 25MHz, which is proven by the rest of the circuit.Something else must be going on...

author: PGPG
author_rank: Frequent Contributor
timestamp: October 10, 2025, 06:44:24 pm
content: Quote from: GabrielWeingardt on October 10, 2025, 11:40:07 amAccording to my experience whenever the problem could be described like you describe it the reason was CAPACITOR.HC ICs you could buy 30 years ago and having the same name ICs you can buy nowadays are different devices. The modern are made using much smaller technology (it cuts costs) with the effect of being much faster (datasheet specifies the maximum times and not minimum). Faster means generating much stronger IC current pulses in supply lines when switching and also being able to respond to very short disturbance that old ICs would even didn't noticed.Because of this PCB designed like 30 years ago but assembled nowadays can have much bigger problems than assembled 30 years ago.We used one serial EEPROM in device in 1995 then when assembled the same device in 2006 it didn't worked just because the same EEPROM from the same manufacturer was more 'modern'.In such PCB you should have 10nF ..100nF capacitor connected as short as possible to supply pins ofeachIC, but it looks that in many cases you connect capacitor between VCC pin of one IC and GND pin of another IC.Ground plane to be effective should be continuous. I'd suggest to use 4 layer PCB here with whole internal layers destined to GND and VCC.My example of 2 layer board with one layer 100% destined to GND:https://forum.kicad.info/t/approaching-pcb-track-routing-for-a-newbie/36302/7If you want to learn about PCB design read articles I have mentioned here:https://forum.kicad.info/t/decoupling-capacitor-via-placement/25132/14https://forum.kicad.info/t/decoupling-capacitor-via-placement/25132/18

author: srb1954
author_rank: Super Contributor
timestamp: October 10, 2025, 06:46:12 pm
content: Quote from: GabrielWeingardt on October 10, 2025, 05:17:20 pmJust relying on the maximum clock rating of a chip being morelessthan the circuit clock rate is not a reliable way to design logic circuits. You need to perform a comprehensive timing analysis of every signal path to ensure that data set-up and hold times are within suitable limits. It is always best to perform such timing analysis using the worst case delays from the data sheets. I note that your circuit has some rather long, multi-gate decoding chains which may produce unexpectedly long delays when worst case timing figures are calculated.With respect to your latch apparently changing values you should look very closely at the timing relationships between the data presented to the latch and the clock signal latching that data. The datasheet will specify a set-up time where the data input must be stable so many nanoseconds prior to the arrival of the clock edge and possibly a data hold time where the data must remain stable so many nanoseconds after the active clock edge. Failure to meet or better the datasheet specified timings may result in meta-stability, where a flip-flop can appear to randomly change its latched data state to an incorrect value. This meta-stability issue can manifest itself as output change many nanoseconds, or even microseconds, after the relevant clock edge, thus appearing to be a random change.

author: Benta
author_rank: Super Contributor
timestamp: October 10, 2025, 06:51:55 pm
content: Quote from: GabrielWeingardt on October 10, 2025, 05:17:20 pmYou don't understand what I'm saying. I'm talking about LOGIC VOLTAGE LEVELS. I've worked on 6502 and 65C02 boards, and they're NOT CMOS-level compatible. Changing the logic parts to 74HCT solved the issue.It's got nothing to do with the supply voltage.

author: free_electron
author_rank: Super Contributor
timestamp: October 10, 2025, 07:20:30 pm
content: Listen to Benta. You need HCT logic. HC needs cmos logic levels and fast rise times Logic high for HC @5v vcc is at least 2/3VCC . Your chosen CPU cannot provide that. HCT family sees a "high" at 2.4 voltAnd have proper bypass caps close to power pins of all logic.With HC logic : make sure you are not driving anything from open collector style outputs. You need to have pull-up/down on the inputs if you do that. TTL logic can have an input open. it floats high. Cmos logic becomes one huge noise magnet...

author: langwadt
author_rank: Super Contributor
timestamp: October 10, 2025, 07:26:31 pm
content: Quote from: free_electron on October 10, 2025, 07:20:30 pmhttps://www.ebay.com/itm/186025115231

author: GabrielWeingardt
author_rank: Newbie
timestamp: October 10, 2025, 07:45:28 pm
content: Thank you for all the feedback.From what I've gathered here, I should use HCT logic as recommend.But to clear some confusion, the CPU latches the correct data into the latch.Without the CPU interfacing with this latch, it changes state. This is what's weird and which has never happened to me.Btw, all chips I use were bought in the last 5 years and were brand new. I've not checked each chips production date,but most of the time, especially with TI chips one can tell their age.Also the 74HC574 seems to work pretty fine with motorolla timings, so that's not the problem I guess.Maybe I could take a similar approach to the Commodore 64: Use bus transceivers between certain sections of the board,like between the video card and computer. But building the board purely out of HCT logic would archive the same goal I guess.Another thing, I'll remember for the next PCB:- Use more capacitors and place them directly at each IC's VCC pin- Use more VIA's to interconnect the two ground planes (As I want my board to only be double sided)Another question I have is if I should just leave the ground plane out all togetheror if I should do ground on the bottom and VCC on the top layer, "as it's done" in 4 layer boards?

author: langwadt
author_rank: Super Contributor
timestamp: October 10, 2025, 07:58:35 pm
content: Quote from: GabrielWeingardt on October 10, 2025, 07:45:28 pmif the voltage on the clock is right on the very edge of being high enough to be interpreted as high it takes very little noise to get a high-low-high transition

author: Benta
author_rank: Super Contributor
timestamp: October 10, 2025, 08:34:36 pm
content: Quote from: GabrielWeingardt on October 10, 2025, 07:45:28 pmI think you'll find that PCB layout is pretty uncritical. The 6502 will run at what? 1, 2, 4 MHz? Easy.I've never had problems with either layout or missing ground planes. I've even built a 65C02 mini-system on a Euro-size perfboard.It's not like it's a 633 MHz SDRAM bus.

author: moffy
author_rank: Super Contributor
timestamp: October 10, 2025, 10:54:31 pm
content: I think Benta makes sense in using 74HCT instead of 74HC, but if looking for a reason why the same circuit with a ground plane doesn't work vs no ground plane and working, ground planes add capacitance to traces, extra capacitance means slightly slower edges which are more vulnerable to crosstalk corruption, multiple edges and consider also the reduced spacing between traces. It's just a theory.

author: aeg
author_rank: Regular Contributor
timestamp: October 11, 2025, 12:06:20 am
content: I agree with the previous comments about bypass caps, input thresholds and timing analysis.If you have an MSO, you can trigger on output transition and probably catch a smoking gun on the clock input.

author: tggzzz
author_rank: Super Contributor
timestamp: October 11, 2025, 08:03:12 am
content: Quote from: aeg on October 11, 2025, 12:06:20 amYou don't need an MSO to check gross signal integrity. Any scope with sufficient bandwidth is sufficient.For subtle problems a storage scope with infinite persistence is necessary, but I doubt the OP's problems are subtle.Hint for the OP: you are usinganaloguecomponents thatinterpretthe input voltage as a digital signal. For the interpretation to be correct, the input voltages must be within the the VILand VIHspecification, and the tsuand thtiming specification must all be observed. If those specifications aren't observed, there are no guarantees about what the components will do. That includes transients, of course.

author: PGPG
author_rank: Frequent Contributor
timestamp: October 11, 2025, 12:05:44 pm
content: Quote from: srb1954 on October 10, 2025, 06:46:12 pmAccording to what OP has writtenQuote from: GabrielWeingardt on October 10, 2025, 11:40:07 amdata is written correctly but after some random time it changes even no other writes were done.For me that means that it is not the problem of correct timing during write but in disturbances reaching the IC.It can be noisy VCC (ns pulses) or crosstalk reaching IC latch input.It is why I assume that it would be no a problem when using old ICs that will have much slower output state change and much slower input response (crosstalk would be no problem).If crosstalk exists and you connect oscilloscope probe to input pin than probe capacitance can be enough to filter out pulses.I think that classical way of routing DIP digital ICs was to put them in a row and run with GND and VCC tracks under them adding 10nF after each IC.

author: tggzzz
author_rank: Super Contributor
timestamp: October 11, 2025, 01:15:25 pm
content: Quote from: PGPG on October 11, 2025, 12:05:44 pmShowpicturesof (1) how you are measuring that and (2) what is shown on the scope. Frequently beginners do not mention the important points (because they don't realise they are important, but they are visible in photos.Why? Signal integritymustbe assured.Demonstrate signal integrity by...Stating your components' VILVIHspecification. There are important differences between HC and HCT devices.For clocked devices, state your components setup and hold time (tsuand th) specifications.Show on your scope that the input voltages are within the the VILand VIHspecification.Show on your scope that the tsuand thtiming specification are observed atalltimes.If those specifications aren't observed, there are no guarantees about what the components will do. That includes transients, of course.A very useful technique is to set the scope to infinite persistence, which creates an "eye diagram". That will capture rare signal integrity violations.QuoteCrosstalkhas a specific meaning; I very much doubt you are seeing crosstalk problems.QuoteGround bounceis more likely to be an issue that can be avoided with slower transition times.QuoteCrosstalkwon't be significantly changed by a scope probe with slow transition times.Showing a picture of how you are connecting your probe to the circuit can reveal problems.QuoteOn a two layer, board put the (analogue) components that you mention in a row, run Vcc/Gnd in a line underneath the ICs, 10nF by each IC, at each end connect the Vcc/Gnd to create agrid/mesh, add occasional Gnd lines tying adjacent Gnd rows together, then place the signal lines. The objective is to provide a short path for the current to flow between source and destination; long loops are your enemy.

author: davep238
author_rank: Contributor
timestamp: October 11, 2025, 02:07:06 pm
content: Your PCB layout has very few ground stitching vias. Perhaps adding more would help.

author: tggzzz
author_rank: Super Contributor
timestamp: October 11, 2025, 02:19:53 pm
content: Glancing at your schematic, it appears that some of your register's clocks (e.g. pram_bank_e) are derivedsolelyfrom the address bus.The digital signals on the address bus are probably only defined and valid at some times, and are undefined at others. When undefined, the clocks will also be undefined, and that could clock the registers.Any such "glitches" should show up on a logic analyser or scope trace with infinite persistence.