hybridfree/eevblog-posts huggingface dataset:
There is a Pspice model for component JT3028 or SG6841 to add in Orcad Cadence ? - Page 1
Forum section: electronics / general

author: eletmoraes
author_rank: Newbie
timestamp: April 28, 2020, 11:33:37 pm
content: I would like to be able to simulate a power supply circuit using the integrated JT3028 and the SG6841 component, I am using the Orcad Cadence program.

author: PKTKS
author_rank: Super Contributor
timestamp: April 29, 2020, 05:16:33 pm
content: The second one falls the category of "patented" obscurenew features from elsewhere.Hardly you will a have a "model" of such patented stuff.Exception - and worth noted - is all the LINEAR (now ANALOG)patented and totally crypto models bundled in LTSpice.They do work - although the models are encrypted and onlyLTSpice can handle themLast fallback is all the normal regular fully backed stuff( best example tje good fit all 494 or UC38xx ) which alreadyhas dozen of clones and models (PSPICE mostly) available.IMHO? go LTSPICE ones or fallback trusty open stufffar more reliable the last alternativeI am getting sick of these new patented worthless shitthey consume time effort and they fail more than the others.Trusty stuff are more reliablePaul
Elecrow Vias & Through Holes - Page 1
Forum section: electronics / general

author: 741
author_rank: Frequent Contributor
timestamp: April 20, 2020, 03:55:58 pm
content: In theElecrow PCB Specification Guide, I see the minimum via & through hole drawings.I do not quite understand them.For through holes, I think they are saying min drill is 0.3mmFor vias, the drawing seems to show the outer via diameter, not the drill size?I'd like to know I can specify a via with drill 0.25mm, I think this is OK.P.S.If the restriction is "smallest drill", why specify different values anyway? Is it related to the fact vias can be buried? (Is a blind via a micro-via almost by definition incidentally?)

author: thm_w
author_rank: Super Contributor
timestamp: April 20, 2020, 09:06:50 pm
content: Select the minimum hole size during checkout:https://www.elecrow.com/pcb-manufacturing.html0.3 0.25 or 0.2mm

author: 741
author_rank: Frequent Contributor
timestamp: April 21, 2020, 09:38:19 am
content: I've never seen the hole size choice before. That must be because as soon as I upload a Gerber, it detects the answer and removes that dialog detail.However, if I want to answer the question "is it still $4.90 for 0.25mm?", it seems the price stays as $0.00 until I upload an actual gerber.So it seems the only way to find out is to create some gerbers having different minimum via sizes.

author: thm_w
author_rank: Super Contributor
timestamp: April 21, 2020, 08:52:05 pm
content: Weird now it just removes the hole size selection, and at the bottom says 0.3mm hole.And in the spec it says 0.3mm hole (regardless of number of layers), 0.2mm for special service only:https://www.elecrow.com/download/quote/PCB_Specification_FAQ.pdfSo you might have to contact them for a quote.JLC will do 0.3mm for 2 layer boards and 0.2mm for 4 layer boards by default.
Mechanical layer convention, does it exist? - Page 1
Forum section: electronics / general

author: EPTech
author_rank: Regular Contributor
timestamp: April 20, 2020, 05:05:32 pm
content: Hi all,Does there exist some kind of concensus in the use of mechanical layers. I have searched for this many times and I hope that some of my collegues here can point me in the right direction.In Altium I found a lot of inconsistancies in libraries when it comes to mechanical layer usage and I do not know which ones to correct.I have found a description at ninedotsconnect. Is this a good reference?Greetings,Pascal.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 20, 2020, 09:57:30 pm
content: Nope. Use house standard.In Altium, layers are easily changed in libraries or PCBs, so it's not a big deal updating stock, old or outside libraries as needed.For example I use, I think it's the default from Altium stock libraries: Mech 1 centroid mark, Mech 13 3D info (models and outlines), Mech 15 courtyards. Paired with Mech 3, 14 and 16 respectively, for top/bottom pairs.Have also often merged Mech 1 into Mech 15 so 15 has both centroids and courtyards. Have seen multiple kinds of outlines (body, pins, etc.) and courtyards on other layers, as well as labels and such. PCB templates, might have sheet graphics on a layer or two, sometimes including different title blocks for different drawings (fab, assembly top/bottom).Other tools, might have only a few layers, of specific purpose. Eagle is kind of this way, I think. Ultiboard has a few spare mech layers, which can be used for drawings. That sort of thing.Now that Altium's been expanded to ludicrous layers (as of... AD18, 19?), there's no worry about running out... Plus you can rename the layers how ever you like. Which I find a bit annoying as they still show up as "Mech-N" but you can't query them by number, you need to remember the actual exact (case-insensitive) name to do a query on...Tim
Manufacturing PCB options - Page 1
Forum section: electronics / general

author: VEGETA
author_rank: Super Contributor
timestamp: June 06, 2020, 01:00:49 am
content: Hello fellow EEVblog fans,I know how to design PCBs and manufactured some using JLCPCB, but now I plan to make a small batch of a certain project and get it assembled. JLCPCB assembly service will fit this particular project but other projects won't... since I need black solder mask and so on.so typically, is there a way I could manufacture and assemble the boards at one place? since shipping components and boards to me in Jordan then re-shipping them to assembler, after that re-shipping them to me... will cost a fortune!what do you do usually?how much typically can assembly cost (setup + assemble) for say 280mmx280mm board?do you buy all the components yourself then ship them at once to your assembler? do you then ship the PCBs themselves to the assembler? I need details.also what about your components? I can make an excel sheet with LCSC, Digikey, mouser part numbers for example. will this work?I really hope you guys help me in details.regards!

author: thm_w
author_rank: Super Contributor
timestamp: June 08, 2020, 09:05:21 pm
content: https://www.pcbway.com/pcb-assembly.html

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: June 08, 2020, 11:04:46 pm
content: Most contract manufacturers will order FABs for you, although the documentation typically requested by a CM generally exceeds the level of documentation that most hobbyists provide.It is all about ensuring that everyone else knows how to build the thing that you designed. Good drawings and notes are the thing that most layout guys struggle with. When you ship out your data and get 10 EQs back from the assembler or fab house, you know you are either doing some really fancy shit or your drawing is bad.I mentioned what files you should supply to a CM in a different post.https://www.eevblog.com/forum/altium/dblib-with-individual-tables-for-each-component-type-thoughts/msg2773338/#msg2773338
EDA for Wiring Diagrams - Page 1
Forum section: electronics / general

author: aw_rw1
author_rank: Contributor
timestamp: April 01, 2020, 09:54:27 pm
content: Does anyone know any good free or open source wiring diagram software?

author: HwAoRrDk
author_rank: Super Contributor
timestamp: April 01, 2020, 10:57:59 pm
content: Have a look at QElectroTech:https://qelectrotech.org/

author: aw_rw1
author_rank: Contributor
timestamp: April 02, 2020, 07:03:09 pm
content: Thanks hwaorrdk!QElectroTech looks good. I installed it and will try it.But do you know how QET compares to KiCAD or Visio?

author: Chris56000
author_rank: Frequent Contributor
timestamp: April 18, 2020, 03:09:41 pm
content: Hi!QElectroTech is NOT a PCB design or export tool – it doesn't export a netlist and cannot of course, design PCBs natively!Think of it as a free open–source version of ePlan!Chris Williams
Latest Microchip packaging is where? - Page 1
Forum section: electronics / general

author: 741
author_rank: Frequent Contributor
timestamp: April 13, 2020, 08:11:41 am
content: I often find Microchip's site hard to use. I can not find a link to the latest packaging herehttps://www.microchip.com/quality/packaging-specificationsAnyway, as a "lucky dip" I found the 2015 specshttps://ww1.microchip.com/downloads/en/PackagingSpec/00000049BZ.pdf(The obvious thing to then try,https://ww1.microchip.com/downloads/en/PackagingSpec/gives errors)

author: jc101
author_rank: Frequent Contributor
timestamp: April 13, 2020, 03:26:02 pm
content: From the menu at the top... "Design Support", then menus below "Documentation" -> "Packaging Specifications" is that what you are after?This is the page that links tohttps://www.microchip.com/quality/packaging-specifications

author: 741
author_rank: Frequent Contributor
timestamp: April 14, 2020, 08:29:08 am
content: HiYour link seems to match the link I have already tried. It should indeed be the place to go. It is the link given on datasheets etc.My problem is I am unable to find the download link once I land on that page.Maybe it is because I use Firefox?

author: jc101
author_rank: Frequent Contributor
timestamp: April 14, 2020, 09:06:36 am
content: The View Details is a link to some code that grabs the .pdf, so you can't right click and download. Just clicking the link should bring up the .pdf file though.Just tried it Firefox, Safari, Chrome and Edge and seems to work OK. {edit} if somewhat slowly...

author: 741
author_rank: Frequent Contributor
timestamp: April 14, 2020, 12:38:06 pm
content: I tried this just now. All I get is a specific package pdf, wheras I had hoped top get the big pdf holding all packages.I cannot see a link or a region to click to do this.The best I can get is to click on any old package, say XSON, then follow the clicks and then just a small pdf with one footprint.

author: jc101
author_rank: Frequent Contributor
timestamp: April 14, 2020, 12:41:01 pm
content: Yes, there is no single large document any more.Splitting them up makes it easier to just update those that need updating, without refreshing the single large document again.
Move LTSpice files to another drive ? - Page 1
Forum section: electronics / general

author: MathWizard
author_rank: Super Contributor
timestamp: March 29, 2020, 07:51:53 pm
content: I have LTSpice installed on my c: and it simulations easily fill the partition. I looked in the settings file but I don't see how to choose where it stores files ? I don't want to just re-install because I don't remember where/how I installed the extra part models.

author: AlfBaz
author_rank: Super Contributor
timestamp: March 29, 2020, 09:11:41 pm
content: Just copy and paste your asc files to a new drive directory. LTSpice remembers the last directory you used between starts.Leave the install lib directory in its original spot and every thing will just work.The only thing you may have to do is change the path of any custom lib files you are using if you move them as well

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: March 29, 2020, 09:50:04 pm
content: Hi,You can safely delete all the .raw files that have been generated by LTspice. These are the results from the simulations.You can also use the.save V(in) V(out) …directive to reduce the amount of data that is saved in the first place. You specify which nodes you want to save.Regards,Jay_Diddy_B
Alternative to Digi-Key Scheme it - Page 1
Forum section: electronics / general

author: JesusCastane
author_rank: Newbie
timestamp: May 01, 2020, 10:28:50 am
content: Hello,I'm using Digi-Key Scheme it to sketch some schematics.www.digikey.com/schemeitIs there any alternative that is open source and/or offline?What tool do you use to capture some quick ideas about circuits?Thanks,

author: Eternauta
author_rank: Contributor
timestamp: May 02, 2020, 08:20:21 am
content: I found sPlan 7 a good solution for schematics, block diagrams, wiring diagrams for documentation etc etc.it is not free but the price is acceptable (45 Euro).

author: MarkF
author_rank: Super Contributor
timestamp: May 02, 2020, 03:33:07 pm
content: Use the same tools you would use for a PCB layout.Then, you can proceed directly from the schematic to layout and having a board made if you like.See the following discussion:https://www.eevblog.com/forum/manufacture/are-osh-park-and-kicad-still-a-good-starting-place/?topicseen

author: JesusCastane
author_rank: Newbie
timestamp: May 04, 2020, 09:13:21 am
content: I will check sPlan 7, looks good.I use Altium and I could use it to capture these ideas but just exploring other options that might be quickerThanks for your comments
Rectangular QFP's - Page 1
Forum section: electronics / general

author: fcb
author_rank: Super Contributor
timestamp: March 22, 2020, 07:48:41 pm
content: Busy writing SW for a feature in one of our products (ASA100) and I'm wondering the following:Rectangular QFP's? Is there a rule of thumb, or a JEDEC rule that says what the number of pins per side should be? So currently I have:64 pin QFP - 19/13/19/1380 pin QFP - 24/16/24/16100 pin QFP - 30/20/30/20128 pin QFP - 38/26/38/26Any other rectangular parts you've come across?

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: March 22, 2020, 07:52:55 pm
content: lots of qfn's most recentlyhttp://www.ti.com/lit/ds/symlink/ts3l501e.pdf

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: March 22, 2020, 07:55:14 pm
content: also PQFNs PLCCs BGAs LGAs PGAs

author: fcb
author_rank: Super Contributor
timestamp: March 22, 2020, 08:09:44 pm
content: At this stage I'm mostly interested in part you could actually get a test probe down onto. So no BGA's, but you could get to the outside of QFN's I guess.Looks like I might have to write a 'custom' package option.
using negative dry film - Page 1
Forum section: electronics / general

author: johntech
author_rank: Newbie
timestamp: March 21, 2020, 12:11:56 pm
content: Having used the laser toner method of pcb image transfer to copper clad,and also positive resist,i want to use the negative dry film as it is very cheap,from youtube vids resolution is good.This would be ideal as i could make single and double sided pcb's for pennies.I use Tina7 pro Ind and find it very good for my needs,so far.I cannot find and means to invert the gerber images ,the standard track is positive imaged and no good for this abundant and very cheap dry film.If i have to bite the bullet and buy new software that can output positive and negative gerber images then so be it,but if anyone knows how to sort this,and it seems some people have this fixed,i can't for the life of me find anything ,i'd try printing and the photo copying,but scale may be altered,and that opens a can of worms to sort out.Plus my version of Tina is on a cd-rom not a subscribe per year scam,pcb houses for what i make charge way too much,as i say ,i can make for pennies even with toner,it's just a pain sorting out missing toner,and a single fieche can last for ages ,positive dry film is quite expensive for some reason,spray resist is inconsistant.Any help here would i believe help more than myself.cheers.
EasyEDA uCurrent design with JLC STM assembly available parts - Page 1
Forum section: electronics / general

author: horvbrun
author_rank: Newbie
timestamp: March 31, 2020, 08:14:58 pm
content: Hello, I am new to this forum. I entered in contest of building a low power device and now I have a problem with measuring the current my device pulls. Due to limited funds I decided to make my own uCurrent based of Daves rev 5. schematic and parts available on JLC PCB STM assembly service. And I ran into few problems, there are no precision resistors so I had to pick first tolerance next to specified, instead of having 0.05% tolerance and 10ppm temperature coefficient I picked 0.1% tolerance and 25ppm temperature coefficient and they didnt have MAX4239 (high bandwidth) so I picked MAX4238(low bandwidth). Will these choices greatly affect device ability to measure current? And I wasnt able to find DP3T L203011MS02Q switch that Dave used in his design so would like to use JS203011AQN or JS203011CQN but I am not sure whether to use them or not because the datasheets don t look the same. L203011MS02Q has 4 neighbour pins connected and JS203011AQN , JS203011CQN have their pins different, my question here is can I plug in switches I found without changing pin order or schematic?
Need feedback on my Visual Version Control for EDA product. - Page 1
Forum section: electronics / general

author: usama
author_rank: Newbie
timestamp: March 07, 2020, 08:11:26 pm
content: Hi. I need some help.What’s your process of working in a team going from a prototype to a product? Do you use any version control system?For the past year, I’ve been working on a platform for managing collaboration among hardware developers by layering multiple features on top of git. The platform is called InventHub (https://inventhub.io) and offers visual version control for ECAD designs with GitHub like collaborative features. I’d love some feedback on the platform as well.Any tips or suggestions for making it more useful for you?
Good news, JLC is back to work. - Page 1
Forum section: electronics / general

author: 501
author_rank: Newbie
timestamp: March 04, 2020, 07:43:07 am
content: Good news, JLC is back to work.Affected by the virus, I haven't designed PCB for a long time. I finally saw good news this afternoon。I hope the epidemic will end as soon as possible。

author: 501
author_rank: Newbie
timestamp: March 04, 2020, 08:05:19 am
content: PCB costs only 5 RMB, about $0.72, including freight.
Discovery AIM - Page 1
Forum section: electronics / general

author: 13
author_rank: Contributor
timestamp: February 14, 2020, 03:46:03 am
content: Hello,I am having difficulties simulating the electromagnetic fields of an inductor in Discovery AIM (student version of ANSYS). When I attempt to build the physics model I get the following error:Conduction Paths 1 is conditionally up-to-date.1. Illegal external terminal 'Current 1': An external terminal must border the edge of the problem region and coincides with the surface of a 3D object.Illegal external terminal 'Current 1': An external terminal must border the edge of the problem region and coincides with the surface of a 3D object.I am putting a DC current through a bifilar coil by selecting the source and return option. Has anyone encountered this error before and would know where to go from it?Thanks,13
Shaving BGA pads for better clearance - Page 1
Forum section: electronics / general

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 12, 2020, 10:25:35 pm
content: Say you want to layout a 0.8mm pitch (or even finer) BGA, on a fairly average fab. Maybe not 7 mil trace/space, 5 or 6 looks to be about the minimum, at least with round pads. (Or if that's not adequate motivation, just take any finer BGA or CSP and the next step up from its recommended fab. With a nod to capped vias or HDI, where via-in-pad is acceptable.)Well, what if you shave down the edges of the pads, making them octagonal, or rounded squares? This could afford, maybe another mil or two of clearance, for traces routed between pads. Doing this on the outermost pads could help fanout. Could be used under the BGA as well, when pads are sparsely connected (so there can be some trace routing on the component layer). It wouldn't do so well for clearing vias (when dogbone style connections are used). Possibly the vias could be shaved as well, but not by much before annular rings get quite questionable.Tim

author: thm_w
author_rank: Super Contributor
timestamp: March 12, 2020, 11:02:09 pm
content: https://www.eevblog.com/forum/projects/(potentially-stupid)-crazy-bga-pad-design/10/

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: March 14, 2020, 12:54:38 am
content: We use octagon pads all the time for decoupling caps on large BGAs. When you make them octagons you can fit the caps on a grid in the center of 4 pads.
LTSpice: Plotting two different simulation traces in one plot - Page 1
Forum section: electronics / general

author: mc172
author_rank: Frequent Contributor
timestamp: February 02, 2020, 05:35:16 pm
content: I've got a simulation in LTSpice and what I want to do is plot the output if R10 for example is 10k and also when it is 11k, on the same graph at the same time. Does anyone know if this is possible please?I'm not doing a tolerance study so don't need to do Monte Carlo analysis, just trying to demonstrate what happens to the output when values change or a variable resistor is adjusted one way or another for example.Thanks.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: February 02, 2020, 05:51:34 pm
content: Hi,Use the .step command like this:.step param Rvalue LIST 10K 11Kreplace the value of the resistor you want to change with:{Rvalue}Nothing special about the name Rvalue, the names have to be the same.The simulation will run as many times as you have values.To display the legend.[Right Click] in the waveform windowViewSelect 'step legend'Regards,Jay_Diddy_B

author: ogden
author_rank: Super Contributor
timestamp: February 02, 2020, 06:13:07 pm
content: Quote from: mc172 on February 02, 2020, 05:35:16 pmEasy. Make copy of whole circuit, in same project. Modify value of resistor in 2nd copy.

author: mc172
author_rank: Frequent Contributor
timestamp: February 02, 2020, 06:32:18 pm
content: Spot on. Thanks guys.
SIMETRIX users: how to display calculated parameters? - Page 1
Forum section: electronics / general

author: twospoons
author_rank: Frequent Contributor
timestamp: January 31, 2020, 01:21:35 am
content: Does anyone know if there's a simple way to display calculated parameters on the schematic? E.g. I have several resistors with values calculated from a few starting parameters, and I'd like to know what those calculated values are.The crude way is to add a resistor in series with 1A current source to the sch, make the resistor value = parameter of interest, then add a voltage marker to see the result.But surely there's a more elegant way to do this?
Digi-Key giving one-year licence for PADS Standard - Page 1
Forum section: electronics / general

author: mc6800
author_rank: Contributor
timestamp: January 07, 2020, 11:57:43 am
content: It seems that Digi-Key/Mentor is ending PADS maker, and are offering a one-year licence of PADS Standard instead. I've received an email with a link to download the software and a code to generate an ethernet-MAC tied one-year licence.I assume the idea is that at the end of the year people will pay for a full licence - although I'm not sure how many people who used a free tool will want to pay $5000

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: January 08, 2020, 12:01:54 pm
content: I've downloaded the 6GB installer but haven't installed yet... not sure I really want to.I think ECAD players are struggling with the threat of Open Source, and subscription/cloud type business models.

author: dimbmw
author_rank: Regular Contributor
timestamp: January 10, 2020, 03:55:09 am
content: Is the link on digikey ? I don’t see Pads Maker there.

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: January 10, 2020, 01:53:47 pm
content: Hmm, I guess you get the offer only if you were registered for PADS Maker previously.

author: O.B.U.B.
author_rank: Newbie
timestamp: January 12, 2020, 04:50:00 pm
content: The offer is only for registered PADS Maker user.I've got one.
Micro-Cap 12 for free - Page 1
Forum section: electronics / general

author: pwlps
author_rank: Frequent Contributor
timestamp: January 09, 2020, 11:25:58 am
content: https://hackaday.com/2020/01/08/commercial-circuit-simulator-goes-free/Anyone has experience with this software ?

author: Gyro
author_rank: Super Contributor
timestamp: January 09, 2020, 12:45:08 pm
content: Tryhttps://www.eevblog.com/forum/projects/microcap-12-is-free-(as-in-beer)-now/(Hackaday have been pretty slow!)
Small BGA pad size - likelihood of success? - Page 1
Forum section: electronics / general

author: zigenz
author_rank: Newbie
timestamp: December 06, 2019, 02:25:14 am
content: Hi guys,I'm trying fan out a 36 pin BGA for prototyping - I had a look at this video by Dave:He's managed to fan out a 36 pin 0.4mm pitch BGA on the top layer; this is what I'm trying to do. I tried the same thing with a random 36 ball BGA I had in my library assuming a 3/3 mil process and it wouldn't work - the pad size was 200 micron as recommended on its datasheet. Makes sense since at 200 micron, assuming an X/X mil process capability yields X = 66.7 micron => 2.7 mil < 3 mil.A closer analysis of the video (i.e. snapshot + scaling pad size off grid) indicated that Dave had used a 6 mil (152 micron) pad with 10 mil (254 micron) mask (i.e. NSMD). I looked up the datasheet for the IGLOO Nano UC36 package; they recommend NSMD, pad diameter of 230 micron with a 330 micron mask, suggesting that the pads are 34% smaller than recommended!I'm just wondering based on others' experience, how this is likely to go assuming I use 6 mil pads with a 10 mil mask? I'm just prototyping, so trying to keep the NRE cost down.Thanks in advance for any guidance.Cheers,Z

author: EEVblog
author_rank: Unknown
timestamp: December 06, 2019, 10:27:46 am
content: Not sure I'd even have the board file any more in order to check.Are you actually using the same Igloo nano part?

author: zigenz
author_rank: Newbie
timestamp: December 06, 2019, 03:41:49 pm
content: Nah, it's an entirely different part altogether, but still 0.4 mm pitch. Recommended pad dimensions are approx. the same however.Ignoring that specific part, any pointers on successful reflows for 0.4mm pitch BGAs avoiding blind vias would be most appreciated! It's just for prototyping, so not THAT concerned with long-term performance, heat-cycling stress resistance etc.Cheers,Z

author: zigenz
author_rank: Newbie
timestamp: December 30, 2019, 03:56:39 am
content: Hey guys,Hope everyone had a great Christmas and all the best for 2020!Just FYI, I managed to get it done using a 2.5/2.5 mil process capability which quite a few board houses are competent with. My actual target device was a 52-pin package which didn't require a "tradtional" BGA breakout in a sense. I only used the narrow trace in the vicinity of the BGA, and expanded to a minimum of 3 mil as soon as possible. To fit in the board envelope, I also needed to go down to a 0.2mm drill with a 6 mil annular ring - again, most board houses that can do 2.5/2.5 will be able to accommodate this too. See below:If you are using compatible packages (i.e. where single-layer breakout is feasible), it saves a lot of the cost associated with using laser-drilled micro-vias.For the less experienced, I recommend the following guideline:http://www.ti.com/lit/an/spraav1b/spraav1b.pdf. You can largely ignore the package-on-package stuff, but the 0.4mm BGA layout recommendations are invaluable IMHO.Just thought I'd feed back in case it helps someone else.Cheers,Z
LTC3901 simulation in LTspice malfunctions (synchronous  rectifier controller) - Page 1
Forum section: electronics / general

author: ocset
author_rank: Super Contributor
timestamp: December 31, 2019, 01:49:02 am
content: Hi,The attached is a LTspice simulation of a full bridge with synchronous rectifiers using LTC3723 and LTC3901 . (LTC3901 is a sync rect controller)If the 2:1 signal transformer has Lp = 10mH, then the sync rect drive malfunctions. If I increase LP of the signal transformer to 11mH (keeping the 2:1 turns ratio), then it functions properly.(The signal transformer feeds the SYNC pin of the LTC3901)Why is it malfunctioning?The Sync pin waveform on the LTC3901 looks fine when LP=10mH…so why does it malfunction?LTC3723 datasheet:https://www.analog.com/media/en/technical-documentation/data-sheets/372312f.pdfLTC3901 datasheet:https://www.analog.com/media/en/technical-documentation/data-sheets/3901f.pdf
$4500 Top professional SPICE for free!! - Page 1
Forum section: electronics / general

author: FriedMule
author_rank: Frequent Contributor
timestamp: December 23, 2019, 09:54:06 pm
content: HiI have just seen a video about Micro-Cap SPICE v.12 that is one of the industry top notch SPIC's, it is totally free for the moment, normal costs $4500+.Please look at this video:

author: nctnico
author_rank: Super Contributor
timestamp: December 23, 2019, 10:28:05 pm
content: Hmm, it seems they have closed the company down and made the software available for free. I guess $4500 wasn't enough to keep the business going. Sad.

author: ataradov
author_rank: Super Contributor
timestamp: December 23, 2019, 11:02:36 pm
content: There is a discussion somewhere here about this. I belie the author has retired and it was not really a "company" behind it. So it served it purpose - got the person to the retirement.

author: nctnico
author_rank: Super Contributor
timestamp: December 24, 2019, 12:01:29 am
content: Quote from: ataradov on December 23, 2019, 11:02:36 pmYou are right. There are several other threads already.

author: thm_w
author_rank: Super Contributor
timestamp: December 24, 2019, 12:23:20 am
content: https://www.eevblog.com/forum/projects/microcap-12-is-free-(as-in-beer)-now/

author: ebclr
author_rank: Super Contributor
timestamp: December 25, 2019, 04:26:49 pm
content: It's old news, But Kiss Analog gets a new subscriber liked the channel
Altium: Polygon pour breaks on rigid-flex "split" lines - Page 1
Forum section: electronics / general

author: The_PCB_Guy
author_rank: Regular Contributor
timestamp: August 25, 2016, 05:39:53 pm
content: Hi folks,I'm working on a rigid-flex design that consists of two rigid 8-layer sections separated by a short 4-layer flexible section. I am working on an internal layer (that is shared by the rigid and flex portions) and am trying to create a pour that covers the entire layer (effectively a plane, but I need more control than that, which is why I'm using a polygon instead). I have a board edge clearance rule set up of 0.381mm but the problem is that Altium is seeing the "split line" (between the rigid sections and the flex section) as the board edge, and will not allow me to pour over the entire surface. Attached is a screenshot.How can I get the pour to flow between all three sections? Perhaps I can create a custom query to have the board outline clearance rule ignore the split lines? Not sure what queries I can use to do that, though.Thanks

author: RF-Tech
author_rank: Contributor
timestamp: September 09, 2016, 02:11:25 pm
content: I've designed a few rigid-flex boards in Altium 15 and didn't have this trouble - I poured an internal layer to cross over from the rigid to flex layer and had no problem. When we recently went to Altium 16.1 I had to design a similar board and had major issues, after working with it for a few hours I went back to Altium 15 and designed it there. Apparently 16.1 has some bugs in the flex tools.-S

author: beamray
author_rank: Newbie
timestamp: December 06, 2019, 06:32:54 am
content: I had this problem, but I figured it out.It appears, that AD 16 and newer (up to 19.1) considering split line like a boarder.So it should be fixed with rules.
Altium Connection Issues - Page 1
Forum section: electronics / general

author: Victor15
author_rank: Newbie
timestamp: January 10, 2020, 05:06:31 pm
content: Hello there!I'm new in Altium, I'm using the 19.0.15 versions, only in this project it's happened, not in the others.I've placed some components in the PCB, but need to change their position, it's ok, but the old connections lines still there, like the image:https://drive.google.com/file/d/17RCE97s1K5TlMXfDpWxHXmOCztec3Sht/view?usp=sharingSomeone can help me with this? how to delete these lines?

author: thm_w
author_rank: Super Contributor
timestamp: January 10, 2020, 09:56:51 pm
content: https://www.eevblog.com/forum/altium/connection-issues-225390/Please don't cross post.
pcb-rnd 2.2.0 release - Page 1
Forum section: electronics / general

author: ScribblesOnNapkins
author_rank: Regular Contributor
timestamp: January 24, 2020, 03:35:00 am
content: The following is reposted from our pcb-rnd mailing list.***Hi all,after another busy development cycle, I'm happy to announce pcb-rnd 2.2.0,our latest stable release.Thanks to everyone who contributed!Project page:http://pcb-rnd.repo.huRelease notes:pcb-rnd 2.2.0~~~~~~~~~~~~~This version of pcb-rnd is mainly a cleanup/bugfix version with 3notable new features. One of the new features is the extended objectinfrastructure, that provides a sustainable way to extend pcb-rnd featureswith new tools and objects without having to complicate the data model.With this release the second digit of the version bumped because pcb-rndis entering a new era. librnd (including the hidlib) is already installedand being used by external applications. The new 2.2.x era is aboutstarting to separate librnd from pcb-rnd. This effort will take multipledevelopment cycles.Feature highlight:1. extended objects (line-of-vias and dimension lines)2. OpenEMS export: suitable for microwave filter and antenna simulation3. STL export: yet another path to 3D4. io_eagle: various bugfixes and improvements in the loader allows moreeagle boards to be loaded with less glitches5. scripting: action code upgrade allows delivering the hidlib/PCB pointerto actions as argument (in argv) which long term makes the codereentrant; centralized and unified layer and layer group addressing(using the syntax and experiences from cam)6. windows port: the cross compilation setup got smoother and the startupcode more robust, removing all known windows-port-specific bugs -locales and parametric footprint dialog work well nowBest regards,Igor2
Fusion 360:  Anyone get a startup license ?? - Page 1
Forum section: electronics / general

author: frogblender
author_rank: Regular Contributor
timestamp: November 29, 2019, 08:35:24 pm
content: Has anyone been successful in getting a startup license for Fusion360? (I mean, since they changed the licensing a few months back).I "applied" (filled out the webform), but received nothing but radio silence.

author: Jeroen3
author_rank: Super Contributor
timestamp: November 29, 2019, 08:48:14 pm
content: Are you a startup? You only get one year, one time.

author: Warhawk
author_rank: Frequent Contributor
timestamp: November 30, 2019, 10:47:57 am
content: Quote from: Jeroen3 on November 29, 2019, 08:48:14 pmWhere does this information come from?https://knowledge.autodesk.com/support/fusion-360/learn-explore/caas/sfdcarticles/sfdcarticles/How-to-renew-your-hobbyist-enthusiast-license-for-Fusion-360.html"Fill out all the required fields in the form and select Apply. Once the application has been sent, an Autodesk representative reviews the application and contacts you within ten business days."I understand you can get it multiple times if Autodesk likes you.I am not into fusion anymore but anyways..
Another 2D CAD free alternative DoubleCad XT (Turbocad) - Page 1
Forum section: electronics / general

author: Warhawk
author_rank: Frequent Contributor
timestamp: November 24, 2019, 04:30:59 pm
content: Hello Guys,I believe I am not alone who occasionally needs a 2D-cad that can produce either DXF or DWG files. I grew up with Autocad and for this reason, I still use AutoCad 98LT (that I have license for)...I was also a big fan of Draftsight but it is not free anymore (except the Linux version). A friend of mine showed DoubleCad XT v5 to me yesterday. So far I am surprised how good it is.And now wait for the best part...You will get the activation and license code through the email andyou don't need any internet connection to install, activate, or use the software. Yes, it is a standalone license with no strings attached. Free for commercial use....You can get it from here:https://www.turbocad.com/doublecad-downloadPS: I have nothing to do with the company or the software. Just sharing with the community.Drawback: Does not work under wine

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 25, 2019, 04:03:40 pm
content: If it's indeed the same company, I remember using Turbocad a long time ago, and it was fine for my needs back then.I'll definitely have a look.
Symbol Standards - Page 1
Forum section: electronics / general

author: Spark-Doctor
author_rank: Contributor
timestamp: November 26, 2019, 05:24:15 pm
content: Hi AllDoes anyone know of a reference for labelling components on schematics and board layouts ie Resistor's R, Capacitors C ect.Many Thanks

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 26, 2019, 05:28:55 pm
content: You can start here:https://en.wikipedia.org/wiki/Reference_designator

author: Feynman
author_rank: Regular Contributor
timestamp: November 26, 2019, 10:17:34 pm
content: Here are some IPC-2612 designators:Taken fromhttps://blogs.mentor.com/tom-hausherr/
[pcb-rnd] pcb-rnd on win32: stable release 2.1.4 - Page 1
Forum section: electronics / general

author: ScribblesOnNapkins
author_rank: Regular Contributor
timestamp: November 25, 2019, 12:12:54 pm
content: The following was the release announcement. Sorry it's a bit late to posting here. (nov. 1st).Hi all,for the last stable release, I've:- cleaned up and recompiled the whole dependency tree; it is still notout-of-the-box, but is already somewhat portable (in the sense that it hasa chance to work on someone else's Linux system):http://repo.hu/projects/hidlib.w32/- I've released the binary development pack, required for cross-compilingpcb-rnd:http://repo.hu/projects/hidlib.w32/download/(you can use thispack to cross-compile your own project if it has similar dependencies)- I've cross-compiled pcb-rnd 1.2.4 and created the official binarydownload area for pcb-rnd:http://repo.hu/projects/pcb-rnd/releases-bin/- I've updated the win32 installation doc:http://repo.hu/projects/pcb-rnd/windows.htmlThe new version of hidlib.w32 has libjpeg, libgd, libxml2 and everythingwe missed from the experimental version so the new release should offerabout as much features as a standard *NIX installation. If you havewindows, please test and report back.In theory we could relatively easily roll the pack for every upcomingrelease. It all depends on whether production users appear or not.Best regards,Igor2
[pcb-rnd] new: openems direct path (simulation), with howto - Page 1
Forum section: electronics / general

author: ScribblesOnNapkins
author_rank: Regular Contributor
timestamp: November 25, 2019, 12:22:16 pm
content: This took a lot longer than I thought but I am proud of what we did. Again Igor2's announcement.***Hi all,Evan has been working on an export path to openems for some time and hiswork got to production state lately. He has just finished the pool nodethat describes how it works:http://repo.hu/cgi-bin/pool.cgi?cmd=show&node=s_paramThis is the first application of the new export path. The exampledemonstrates how to determine the s-parameters of a hairpin filter drawnin pcb-rnd. The same method can be used to simulate other high freqfilters as well. With some tweaking, the method will potentially besuitable for simulating PCB antennas too.The openems export plugin (mesher included) is auto-enabled with svn HEADversion and from the next release. With the last stable release you needto configure export_openems either as buildin or plugin.Thanks to Evan, Thorsten and Koen.Best regards,Igor2
IPC-D-356 data request - for research purposes - Page 1
Forum section: electronics / general

author: James Jackson
author_rank: Newbie
timestamp: November 23, 2019, 08:19:23 pm
content: Hello fellow EDA users,Some of you may know me from way back when... when around the turn of the century I wrote an IPC-D-356A netlist generator for users of P-CAD 200x. Way back then they did not have their own IPC-D-356A generator, and I saw a need for one.I am currently evaluating the data in IPC-D-356A netlist files.If anyone is willing to assist me, I would be interested in a partial output of data – not the whole file.What I could use for my research is a part, say the Voltage (I.E. 5V or VCC, etc.) and Ground (I.E. GND, AGND, DGND, etc.) sections of the file.It will look something like this...317GND VIA - D0120PA00X 032500Y 025400X0000 S0327GND D7 -1 UA01X 028350Y 026035X0315Y0315R180 S0317GND VIA - D0180PA00X 028450Y 028500X0000 S0327GND D6 -1 UA01X 029950Y 026035X0315Y0315R180 S0327GND D4 -1 UA01X 031650Y 026035X0315Y0315R180 S0327GND D5 -1 UA01X 030800Y 026035X0315Y0315R180 S0327GND D3 -1 UA01X 032500Y 026035X0315Y0315R180 S0327GND D2 -1 UA01X 033350Y 026035X0315Y0315R180 S0317GND VIA - D0120PA00X 033350Y 025400X0000 S0327GND R14 -2 UA04X 034296Y 026850X0291Y0366R090 S0317GND VIA - D0120PA00X 033800Y 027500X0000 S0You will notice the characters from the fourth space in identify the Net Name.All that it requires is an IPC-D-356A file, a text editor and a cut-n-paste of the above mentioned sections to a new text file (NotePad will work for this).If you don't feel comfortable sharing even a snippet of the file, then that's okay. No worries. Hopefully someone else will help out.Bonus points go to those that send the above portions of the file from designs that are step-and-repeat designs or that are hierarchical designs and use 'rooms' (in Altium Designer lingo).I don't need the information produced by any specific CAD software, as a matter of fact, I would prefer that there be a variety of CAD software 'test files' be provided.If you decide to send me the above requested text files, please send them directly to me (oztronics at hotmail dot com) and not to this forum....and yes, I'm for real. If I have violated any rule here, or because I am new and do not have a 'history' of posting - don't let that upset you. If it does, just ignore me.Thanks for your time and any assistance with this.--Regards,James Jackson, CIDOztronics
good specs for a "break off" debug + testpoint tab - Page 1
Forum section: electronics / general

author: julianhigginson
author_rank: Frequent Contributor
timestamp: December 05, 2019, 01:43:33 am
content: Has anyone got any basic spec or approach or pointers for a breakaway debug header + testpoints tab?I've finally met a design size requirement that's not going to work any other way.PCB is nominal 0.8mm 4 layer with HDI aspects (laser drilled blind vias, and vias in pad)here's a screenshot of my first attempt..FYI, the 1mm routing path break gives the tab a min distance of 3.6mm, and that's 4 x 0.5mm non plated holes at 1mm pitch between them on the original board edge.I'm a little worried it's going to cause problems as-is.

author: Gribo
author_rank: Frequent Contributor
timestamp: December 05, 2019, 12:34:50 pm
content: If you plan on using pogo pins in production, you want to keep your pitch at 0.05" at minimum. 4 test points at 1mm pitch will have to use a staggered arrangement.Also, have a look at the Tag Connect footprint, you might be able to fit it somewhere.I would also rearrange the traces not to be on top of each other, you might have shorts after de-panelizing the PCB.

author: Ian.M
author_rank: Super Contributor
timestamp: December 05, 2019, 01:00:57 pm
content: Also neck down surface traces where they pass through the mousebites to control where the copper breaks and reduce the risk of peeling up the end of a trace.

author: julianhigginson
author_rank: Frequent Contributor
timestamp: December 05, 2019, 11:31:49 pm
content: yeah I have a tag connect cable already.. used it once where I had a board that didn't have the space for a header, thanks to a low profile custom case... But I prefer cortex-debug header normally it's a lot more straightforward.Also, yeah testpoints for production will be spaced properly for bed of nails... I can do that. This version of the board is gong to be more for development/prototyping, but I will try to do test points for Pogo pins on the breakaway tab just in case it's perfect and can become full production.. :-)Thanks for the idea of narrowing down the traces at the intended break.. I was worrying about the copper not breaking, and ripping off the board. though would be cutting the mousebite, so probably not likely unless someone tried doing it by hand.

author: julianhigginson
author_rank: Frequent Contributor
timestamp: December 06, 2019, 08:22:00 am
content: I was avoiding internal traces, and have only routed top and bottom across the mousebites because i was more worried about internal traces shorting.. is surface track tearing generally seen to be more of a worry than shorting of cut mousebites?I could relatively easily change it to routing on the two internal layers if that is seen as better, in actual experience.
0.4mm bga manufacturing ipc requirement - Page 1
Forum section: electronics / general

author: rookie
author_rank: Contributor
timestamp: November 01, 2019, 05:55:10 pm
content: Working on a design that uses 0.4mm bga. The design needs to adhere to class3 guidelines, but the fab house came back saying there's going to be breakout on the annular ring on the inner layer and they cannot drill smaller mechanical holes[already at 6mil], eventually asking to drop class3 requirement for that part. So my questions are:a) should i assume/accept a fallout in boards due to breakouts - how concerned should i be?b) If this part[0.4mm pitch] can even be designed to a class3 requirement,c) if yes then what techniques are used?

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: November 01, 2019, 06:20:20 pm
content: LASER drillsVia in pad plugged and plated over.

author: rookie
author_rank: Contributor
timestamp: November 04, 2019, 08:16:09 pm
content: So laser drills because they can go lower than 6mil? The annular ring requirement is pretty strict, and the pad size cannot increase because there is no space left, so the minimum ring distance still could not be met right? I guess the tolerance on the drill head should be pretty low.

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: November 07, 2019, 05:30:12 pm
content: Quote from: rookie on November 04, 2019, 08:16:09 pmWith a laser you can go smaller than 6mil. 4mil is pretty common. As long as you meet the aspect ratio requirements you should be fine. That means you may only be able to laser drill from layer 1-2. Once you are a layer below the BGA you gain space because there are no pads. You can make a small trace over to another via that goes to some other layer.Drill pairs example 8 layer board:1-8 through1-2 blind1-3 blind2-3 buried3-6 buried6-7 buried6-8 blind7-8 blind1_______________________2___| |_| |________| |_____3______| |_| |_____| |_____4___________| |___| |_____5___________| |___| |_____6___________| |___| |_____7______| |_| |_____| |_____8___| |_| |________| |_____You should place your via directly in the pad of the BGA. You might need to use a few layers/drill pairs to fanout the BGA properly.