Painted myself into a corner. Any tips? - Page 1
Forum section: electronics / general

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 23, 2016, 10:49:16 am
content: Doing my first board (in ages) for a Z80 retro project. I want to stick with the 10cm x 10cm dimensions for cost and modularity. Its a 2 layer board.I am trying to get a fair number of parts fitted on the pcb and if I look at other designs it should be possible. But I am running out of space. Attached is an image of the problem area (I see people embed attached images, but have not found how that works yet). The data bus it not connected to the connector yet as well as the connector on the side (decoder connector).I was wondering if the more experienced could take a look at it and perhaps share your thoughts.

author: krivx
author_rank: Frequent Contributor
timestamp: March 23, 2016, 10:55:09 am
content: If you just need to keep things cheap and you don't have any modern high speed signals then you could just add a small daughterboard and stack the boards. Connect them with simple header pins, much like an Arduino shield.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 23, 2016, 11:02:58 am
content: Yes, that is sort of the idea of this design. A whole bunch is stacked and connected using a ribbon cable(s) (2x 40 pin).I have thought of removing the top 4 ICs (memory bank switcher) but that isn't really efficient use of area.So I want to try to pull this off. I have also swapped the 74-573 for soic packages. Although these are smaller the lack of the through-hole pin does not seem to make routing easier.I will have other boards for the power supply, address decoder (CPLD), system controller and bus-status/debug components. But these (subsytems) are not finalized in design yet.

author: elgonzo
author_rank: Unknown
timestamp: March 23, 2016, 11:11:24 am
content: Do you need to use one large connector? The large connector is clearly meant for more than just address bus, data bus, clock, R/W signal, interrupt signals and alike. I don't know about your system design, but could you split the connector in two in a meaningful way? This could provide you with more flexibility with the placement of the two connectors and thus help you with your PCB layout.With regard to the embedded pictures: You will first need to attach a picture to a post and submit this post. Then, from your submitted post, get the URL to the attached picture. Edit your post to insert/add the URL to the post. Yeah, it's a bit "how ya doin'", but that's the way it is...

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 23, 2016, 12:26:57 pm
content: Quote from: elgonzo on March 23, 2016, 11:11:24 amUh, I already did that This is one halfAs you can see on the screen shot I have started to move some tracks out of the way. Another aspect that also didn't help was that I had a 20mil trace width and that (together with 10mil clearance) did not allow me to pack them in tight. I have reduced the trace with to 14mil which at least allows me to route them closer together on vertical and horizontal axis.

author: botcrusher
author_rank: Regular Contributor
timestamp: March 23, 2016, 12:34:54 pm
content: Aren't PATA cables just the best?

author: elgonzo
author_rank: Unknown
timestamp: March 23, 2016, 12:38:23 pm
content: Would it be possible to place the two large connectors on the left and right side (or at least the one connector which will carry address and data bus)?This could simplify routing of the address and data bus to the connector. As it looks like, you already route the two buses in a horizontal fashion to connect the CPU with the memory ICs. It should therefore be easy to extend the horizontal routing of these two busses to either the right or the left edge without wasting too much PCB space for doing so.I can't give more than this general advice because i have not the faintest clue of what you need so many connections (a-ka connector pin count) for...

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 23, 2016, 01:02:31 pm
content: The two connectors are the main buses of the system - and pretty essential to the modularity of the design.I have tried to pack everything in between the two connectors but there is too little room to fit. I hoped with this arrangement with the horizontal traces on one side and vertical traces on the other I had the most space and best chance to get it all connected...I have rerouted the address bus a bit freeing up some space in the problem area, which is good

author: mariush
author_rank: Super Contributor
timestamp: March 23, 2016, 04:53:26 pm
content: How much vertical real-estate do you have?You could make your design simpler if you make some small adapter boards to convert your DIP chips into tiny boards with single row header that you plug straight into the pcb? This way you won't have all that weaving of traces between holes of your chips and you could also put some decoupling caps on the tiny pcbs instead of adding them directly to your pcb and you could get the chips much closer to each other leaving room for your other chips. And besides decoupling cap you could also route the trace for the ground on the tiny pcb to come out near the vcc pin which would simplify the design of your main boardSuch layout should also allow you to rotate ic101..ic104 by 90 degrees and basically have that z80 above the four memory chips and you wouldn't need to have so long traces coming from the large header at the top going to the z80 chip

author: sca
author_rank: Regular Contributor
timestamp: March 23, 2016, 06:16:16 pm
content: Without either a circuit diagram, or a screenshot with rats nest showing, it's hard to be sure how much is left to route, but I think you may be worrying prematurely.I think if you carry on as you have been, doing largely horizontal on read and vertical on green, you'll get reasonably close. Then look at what is left, and maybe move some areas to 10th tracks on a 20th grid, rather than what looks like a 25th grid that you currently have. You will probably need to switch temporarily to a 10th or even 5th grid to get the diagonals to stack most efficiently, but that can be left until you've determined where it will be necessary.There's most likely plenty of space to be found by moving some of the verticals currently running between U103 and U106 further left, even under the SMT part, leaving plenty of room for the rest of the verticals from the top connector to the left of and between the pins of U103 and U101.From your comments about keeping to 10cm x 10cm and low cost, I presume you're planning on using someone like Elecrow or Itead - they'll have no problem whatsoever going down to 10-10 or even 8-8 if necessary.sca

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 24, 2016, 06:17:24 am
content: Good tips, thanx!I think you're right to say I worried prematurely. After I moved some of the address bus more to the left I had more room to route more signals from the SMD package to the ICs on the right. I also have done the bottom connector now - I wanted to see if I could move the ICs 101-104 further down to make more room, but that was not the case. All that is left now is the connector on the right and the last pins of the SMD part. Oh and then I have some caps, pull-up resistors and the ground plane left to do...(I am at work now, but I will post a new screen shot when I get home)

author: nctnico
author_rank: Super Contributor
timestamp: March 24, 2016, 08:35:58 am
content: The traces look rather thick and the spaces between them is wide. I think you can put twice as much traces on the board by making them thinner and put them closer together. Make sure to route the power in a grid (and put a 0.1uf ceramic capacitor at each intersection) and keep top/bottom layer traces strictly horizontal/vertical.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 24, 2016, 09:16:43 am
content: I had 10mil traces and someone said (in an other thread) that they were somewhat thin...I have a .25 grid. Would it be better to go to a .20 grid or even .10?Why is it important to route the power on the grid (what size?) and put caps on the intersections?I do not keep a "strict" horizontal / vertical separation. Doing it strict would result in unneeded via's.

author: sca
author_rank: Regular Contributor
timestamp: March 24, 2016, 11:51:56 am
content: Quote from: obiwanjacobi on March 24, 2016, 09:16:43 amYou can't win!The general rule is don't route any thinner than you NEED to. A tell-tale sign of auto-routed boards by people who don't know any better is every track (including power, or mains, or even that nice 20A dc motor drive) routed at 8th. If you've got a simple board with 3 tracks on it, make them thick! In this case not so much...For home produced boards, thicker obviously results in a better chance of a working PCB as well. For a bought in PTH board it's really not an issue.Quote from: obiwanjacobi on March 24, 2016, 09:16:43 amYou'll probably use all of the above in the course of routing the board - 25th to get the majority of the stuff done on PTH, then dropping down in the areas where you need to save space. Don't be afraid to change size - there isn't a one size fits all solution.Quote from: obiwanjacobi on March 24, 2016, 09:16:43 amWhat was that quote about rules being for the guidance of wise men, and the obedience of fools?sca

author: jmarkwolf
author_rank: Regular Contributor
timestamp: March 24, 2016, 12:18:57 pm
content: One trick I've employed on through hole boards was to reduce the pad size a scoche, go to a 20mil grid, reduce your track width a little, and you can get 2 tracks between pads.10mil wide tracks are quite large for signal tracks. I think you'll find 8mil wide tracks will allow two tracks between pads.I did an old through-hole board design once, that was so dense there was no room for any silk screen and had multiple "skinny dips" underneath wider dips! The tricks above allowed it work.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 24, 2016, 12:50:10 pm
content: How much clearance would you use in such a case?

author: sca
author_rank: Regular Contributor
timestamp: March 24, 2016, 03:11:48 pm
content: Quote from: obiwanjacobi on March 24, 2016, 12:50:10 pmYou can do the maths.100th between pins on DIP.If, say you wanted 8-8 rules, two tracks plus three lots of clearance gives you 40th, leaving a 60th pad.Those are resonable numbers.Somewhere like Itead / Elecrow will almost certainly be fine down to 6-6, so check your PCB place and adjust to what you and they are comfortable with.sca

author: nctnico
author_rank: Super Contributor
timestamp: March 24, 2016, 05:13:08 pm
content: Quote from: obiwanjacobi on March 24, 2016, 12:50:10 pmI assume you'll have the board made by Seeedstudio etc. Most of these services are perfectly fine with 0.15mm clearance, 0.15mm trace widths and 0.15mm anular ring (your vias look a bit small!). In my designs I usually set the minimum clearance to 0.15mm and route digital signals with 0.2mm. With power on a grid I mean the grid you have due to component placement. You seem to have lined up the chips nicely in rows and columns: that is your grid. Put power traces (+ and ground) in each row and column and connect them at intersections. This already enforces using strict horizontal/vertical trace rules. Vias don't matter these days so don't worry about them. Back in the old days I used Protel Autotrax (MS-DOS) for these kind of boards and let the autorouter do the hard work.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 24, 2016, 05:28:15 pm
content: I think elecrow has a 8-8th limit. I currently use 10th clearance and 14th traces.This is what I have so far. The bottom is pretty much routed, the SMD part and the connector on the right are left. I think I will need to squeeze stuff in a bit because I also have to route VCC. I was planning on doing a GND plane on both layers and stitch them together. I have to go over all the traces when I am done to bundle them together as much as possible to have a big a plane as possible.

author: nctnico
author_rank: Super Contributor
timestamp: March 24, 2016, 08:44:39 pm
content: I see no room for the power traces!

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 25, 2016, 10:15:53 am
content: Yes, I am not out of the woods yet!

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 25, 2016, 04:33:55 pm
content: Well, I am almost done I think.I have routed everything except GND. I have to work out via-stitching to get that solved. I used a slightly thicker trace for VCC (20mil).I have also positioned all silk texts for all parts.I have placed some parts on the back for convenience. I know that silk on the back is more expensive. I don't think it's a big deal when there is no text - it's only a hobby project.What do you think?

author: elgonzo
author_rank: Unknown
timestamp: March 25, 2016, 06:04:02 pm
content: Not related to the layout itself, but i noticed you use both IC? and U? designations for ICs. Not sure if you made this intentionally, but if not it is preferable to use only one designation for the same component type...Many of the decoupling caps seem to be placed rather inefficiently, because their (current) ground connection are often very far away from the ground pin of their respective IC. When you work on routing GND, keep an eye on it...EDIT: Since both your top and bottom layer are almost completely covered by traces, there is probably little reason to use copper pours for your ground. Using copper pours like you did in your last design revision above would not give you a ground plane, but rather many separate little ground planes (with some of them kind of forming little antennas). Also, when routing ground, make sure you don't create ground loops...

author: nctnico
author_rank: Super Contributor
timestamp: March 25, 2016, 10:22:44 pm
content: I agree about the copper pours for ground. At least try and stitch them together and add extra traces to minimise loop areas.@obiwanjacobi: You really need to break up some signal traces in order to have a better connection between the various ground pins! Why didn't you follow the gridded power distribution solution? It is there for a reason! IMHO you made the classic mistake by routing the signals first and then the power. It is much better to route the power first and then the signals. For some (more complex) circuits the layout of the power and ground traces can be a project in itself!

author: Smokey
author_rank: Super Contributor
timestamp: March 26, 2016, 02:08:58 am
content: Not that I'm saying autorouting is generally a good thing... But that boards looks like a slam dunk for autorouting.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 26, 2016, 08:34:43 am
content: @elgonzo: Why is this important? The reason is that the Zilog library I got the Z80 from used IC. Then I made the memory chips (IC101-IC104) myself also using IC. Later I decided to put more on the board and the 74-logic library used U.I have placed the decoupling caps near to the VCC of the IC.Is it better to place them near the GND pin of the IC?About the copper planes: I just filled the two sides without any via stiching. So this is not final - just to give an idea. I am following the advicein this thread (last paragraph). So the idea is to stitch top and bottom planes together and thus connect 'island' fills...?@ntcnico: I did indeed not start with routing the power lines - which should have been obvious from post #1. I did this because I thought that was best (and seem to remember hearing it somewhere). When I route power first in a grid (I do not have a mental picture in my head yet of how that would look) I have already segmented the area. Trace would have to bounce from one side to the other a lot more in order to be routed.If the design needs more via's, it also needs more room. A via is wider than a trace. I have to fan out tightly packed traces in order to make room for the via's. Although I do think that using a smaller grid will alleviate that somewhat. You (nctnico) said that my via's looked small: I wish they could be smaller still.How would I solve the power traces in the most efficient way (without ripping up the whole board and practically start over)?Auto router: I did try it (KiCad), but it could only route like half the board and it was a complete mess in my inexperienced eyes...Thank you for the input. Although I spent days on this and felt a bit annoyed at first I do realize it is valuable info. I do appreciate it.PS: I also discovered I forgot to connect the top data bus to the bottom part. Doh!I think I will move the SMD part a bit more to the left in order to make more room for the traces down (green). I find redoing/reworking existing traces a complete disaster. You practically have to delete them and redo them again. Totally sucks.

author: nctnico
author_rank: Super Contributor
timestamp: March 26, 2016, 08:43:29 am
content: The quick way out is to go for a 4 layer board with power and ground planes. It doesn't cost that much extra.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 26, 2016, 08:58:05 am
content: Yes, but that is like more than 3 times the price of a 2 layer board (pcbshopper)...

author: Aodhan145
author_rank: Frequent Contributor
timestamp: March 26, 2016, 01:00:28 pm
content: Quote from: Smokey on March 26, 2016, 02:08:58 amYeah especially if they are low rise time parts. Jack Ganssle on his YouTube explained a problem where a company had made a lot of Z80 boards but then a new batch failed because the new logic ICs had a low rise time so it destroyed the batch as the boards were not routed with high frequency in mind. Make sure you order the right ICs. Good Luck as well it seems like a good project.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 26, 2016, 07:02:53 pm
content: Its a 20MHz Z80 - don't know about the rise time though.Its done. It may not be the best but its all in there. No errors, no unconnected nets.

author: elgonzo
author_rank: Unknown
timestamp: March 26, 2016, 07:04:30 pm
content: Quote from: obiwanjacobi on March 26, 2016, 08:34:43 amUse whatever designators you want. After all, it will just be some print on the silkcreen and has no functional relevance to the circuit. But it looks kinda odd to the eye. Again, not really important. I just noticed it...QuoteTheconnectionsfrom the decoupling cap to the VCC and GND pin should be as short as possible. You can keep the decoupling near VCC, but keep the connection with the ground pin of the IC as short as possible (i.e., avoid the path of the ground connection between the cap and the GND pin meandering across half of your board; inductance of the traces and all that...).QuoteAh, okay. Didn't know that you were working on a 20MHz design (as the thread you linked states). Somehow the term "retro Z80 project" invoked in my mind memories of those ~4MHz home computers like Amstrad CPC and ZX81.Let's see what what you design... With the current routing ("current" referring the last picture of the PCB you posted here), there would not be much opportunities for overlapping ground pours on both sides of the PCBs, but i guess you are working on that

author: Aodhan145
author_rank: Frequent Contributor
timestamp: March 26, 2016, 07:41:34 pm
content: Quote from: obiwanjacobi on March 26, 2016, 07:02:53 pmIts the logic ics not the z80 itself.

author: nctnico
author_rank: Super Contributor
timestamp: March 27, 2016, 12:19:15 am
content: I'm still not convinced the ground connections on this design are OK. It may work or not. It would be a waste of time & money to just try and see where it goes. The quick fix is to make a 4 layer board, the cheap fix is to redo the board but this time start with the power traces.Wax-on wax-offHmmm wrong movie... try this onePatience. Use the force. Think..

author: obiwanjacobi
author_rank: Super Contributor
timestamp: March 29, 2016, 05:58:19 am
content: Oops, I already ordered the boardsSo I guess we'll see how it goes.Thanx for everyone's input anyway.(Already working on the next board in the stack)

author: Aodhan145
author_rank: Frequent Contributor
timestamp: March 29, 2016, 01:43:51 pm
content: Quote from: obiwanjacobi on March 29, 2016, 05:58:19 amahaahahaha. You can pray they will work.