Dividing 180 MHz by 8 (to get 22.5 MHz), cheaply. - Page 1
Forum section: electronics / projects

author: rs20
author_rank: Super Contributor
timestamp: February 19, 2017, 04:37:12 am
content: Input signal:160~180 MHz - Preferably 3.3V CMOS, but can be LVDS or LVPECL (to be clear, I'm not looking for a solution that supports all of these, just a solution that supports one of these.)Output signal: (180 / 8 MHz) - 3.3V CMOS-- Clocking an LPC824 microSupply voltage: 3.3VJitter, etc: Not at all fussy.I know that dividing frequencies is "easy" because "all you need is a binary counter", but the only 3.3V counter chip on digikey that goes up to 180MHz is the $30, 30-pin MC10EP016FAG which consumes an eye-watering amount of power. So I suspect there are better solutions available!I checked dividers on Digikey as well, and seems you have to choose between Divide-by-4 or an input frequency less than 30 MHz; there doesn't appear to be a Divide-by-8 or Divide-by-N option that operates at 180 MHz.So before I start designing a chain of divide-by-2 followed by divide-by-4 or something like that, I was wondering if anyone had some clever ideas? Seems like something that an FPGA could do in its sleep, but that seems like dramatic overkill for this task.EDIT: Clarifications in green

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: February 19, 2017, 05:09:47 am
content: It seems like a prescaler chip used for frequency counters and such might get you close, though maybe not at 3.3v. On Semi has some with 4.5v minimums.

author: Someone
author_rank: Super Contributor
timestamp: February 19, 2017, 05:17:31 am
content: Hand selected NXP (nexperia) 74LVC163/74LVC161 parts will do it. But if you need guaranteed specs then its back to a couple of dollars for a clock buffer/prescaler/divider/combi chip and ignoring the differential IO on most of them, TI (probably others) have some that can be configured with simple pin strapping.

author: james_s
author_rank: Super Contributor
timestamp: February 19, 2017, 06:27:42 am
content: How about a CPLD? EPM3032ALC44 will run on 3.3V, claims it can implement a counter at up to 227 MHz. The code to divide by 8 is trivial. $1.93 in single quantities for the fastest bin.

author: ThomasDK
author_rank: Regular Contributor
timestamp: February 19, 2017, 07:15:21 am
content: ADF4002?Put your signal on the reference input, set the reference divider and take the output from the mux.Thomas

author: ebclr
author_rank: Super Contributor
timestamp: February 19, 2017, 07:42:02 am
content: http://www.onsemi.com/pub_link/Collateral/MC12093-D.PDF

author: james_s
author_rank: Super Contributor
timestamp: February 19, 2017, 08:36:24 am
content: Using a Spartan6 FPGA for this task is like using a sledge hammer to hang a picture. A $2 CPLD would do the same thing a lot cheaper with a simpler PCB layout, or one of the prescaler chips suggested above.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 19, 2017, 08:45:59 am
content: An EPM3032 might be able to run simple logic internally at 180 MHz, but it won't support that rate on an I/O pin.I'd be looking at the wider context to see if there's a device already on the board that could do it, or be substituted for one that can. Maybe the clock source doesn't need to be 180 MHz at all, if other devices contain PLLs that can multiply up a slower reference?

author: rs20
author_rank: Super Contributor
timestamp: February 19, 2017, 09:27:52 am
content: Thanks all for the various suggestions, a fascinating variety on show here.MC12093 looks like a great option, I'm especially attracted to how small it is (I should have mentioned that small would be nice in the OP) and how it doesn't require programming of any sort (not even SPI configuration). The output looks a little weak, but the thing being clocked (LPC824 ARM Micro) can probably accept that directly if I trick it into thinking it's running an external crystal (or I can just buffer it, of course.)ADF4002 is also a clever suggestion, I would never have considered select parts of a phase detector for this job!Also good to see there are some less exotic binary counters available that can do the job at a stretch.CPLD + FPGA seems like overkill, if even only in terms of board space, but the specific part numbers are much appreciated for familiarising myself with the area.And I hadn't even considered D FF's, but of course you can wire ~Q back into D to make it a toggle FF, right? I assume that was the suggestion at hand. Unfortunately the board size is a bit much here once you chain 3 chips.Quote from: evb149 on February 19, 2017, 08:42:26 amGood question; the input frequency will be staying in the 160 MHz - 180 MHz range, so the MC12093 is absolutely suitable in that sense.Quote from: AndyC_772 on February 19, 2017, 08:45:59 amOh yes, there are a whole host of other options, but I'd like to focus on this particular route to keep the scope of this discussion limited (enough different suggestions as it is!), and because a bigger redesign means more NRE work for me on this very low quantity board.But I would be rude not to answer your question, so I will :-). The thing that's getting the 160~180 MHz clock is aAD9102, which has no internal PLL. So there is certainly going to be (differential) 160~180 MHz on the board. The reason I need to vary the frequency is because the AD9102 arb playback functionality is rather limited, so there are some things that can only be achieved by screwing with the clock rate of the DAC. However, I want the MCU to be clocked at DAC clock / 8, to eliminate "quantization jitter" on the interface between the DAC and the MCU. If it sounds like I'm jumping through lots of hoops to workaround oversights in the AD9102 design(/a poor part choice on my part), you'd be right.The 160~180MHz clock is being generated by anAD9552PLL/clock gen chip, and you're right, substituting this part would be the most obvious choice (specifically, to a similar part that has the facility for different post-dividers on each output). But I've already spun and coded the first revision of the board, so there's a definite cost to switching there -- but open to close substitutions by all means.Yet another option would be to actually generate the /8 clock first, and then use an x8 chip which seems inexplicably easier to find.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 19, 2017, 10:25:59 am
content: Won't changing the CPU clock speed break other interfaces attached to it? Doesn't the CPU need to communicate with the outside world over any port (eg. UART, USB, Ethernet...) which needs the clock configuration to be set up correctly?I'm not saying it's always a "bad" idea, but I don't think I've ever come across a design problem in which varying the CPU clock speed was a good solution, other than for power saving reasons.Another option worth considering might be a dual port RAM, which would support the CPU clock domain on one port and the output device on the other. FPGAs contain them, and they're often used for exactly this reason.

author: rs20
author_rank: Super Contributor
timestamp: February 19, 2017, 11:54:49 am
content: Quote from: AndyC_772 on February 19, 2017, 10:25:59 amBut which is thefunidea?I totally get you, if this were a commerical project, I'd be taking two or three steps back, not the one step back I'm trying to take now. UART is actually super-chill about considerable clock errors (+/-3%), especially if the other side (which is totally under my control) sends 8N2 while the receiver assumes 8N1. Regardless, it's trivial to change the UART prescaler compared to the rest of these issues.I'll have no trouble at all loading the SPI data into the DAC using any old clock -- the issue is the Trigger pin, which starts and stops the waveform. I need it to stay active for a precisely repeatable(/"jitter immune") number of DAC clock cycles*, or else the waveform will be lopped off at the wrong point**. So I don't even need dual port RAM, I just need a 24-bit counter that holds the trigger pin low for a programmable number of DAC clock cycles (hmm, a 180 MHz counter -- ever get that feeling that you've come full-circle?). Clearly this could be implemented in an FPGA, but the MC12093 is more fun, more unusual/interesting, and smaller.* "Can't the AD9102 count out its own burst period", I hear you ask? Why yes, but the counter only counts to 256I may never understand why IC designers don't just stick a 24-bit counters where they might occasionally be useful... I mean, the chip has 14-bit multipliers operating at 180 MSPS on board, how hard would it be to add an extra 16 bits counting at 180/256 = 0.7MHz?** For those who are intently playing along at home, theactualconcern I have is with the DOUT line falling edge coming after an unpredictable number of DAC clock cycles, causing the falling edge to not have a fixed relationship with the waveform itself. I could look at the rising edge, but the accumulated phase error over the length of the burst from 1ppm oscillators would be too bad (~9 degrees).

author: cyberfish
author_rank: Regular Contributor
timestamp: February 19, 2017, 03:05:41 pm
content: Quote from: rs20 on February 19, 2017, 04:37:12 amSilly question, but do the clocks have to be in phase?Otherwise it would be cheaper, easier, takes less space, and probably also less power to just add another crystal?

author: james_s
author_rank: Super Contributor
timestamp: February 19, 2017, 05:39:22 pm
content: Quote from: AndyC_772 on February 19, 2017, 08:45:59 amHow is it going to handle that frequency internally if you can't get it into it via a pin? CPLDs have no PLLs like FPGAs have. You can't have a higher frequency internally than you have going into the thing. I don't know how fast the the IO pins can output but they will certainly do 22.5 MHz. Probably want to feed it into one of the global clock network inputs.

author: mino-fm
author_rank: Regular Contributor
timestamp: February 19, 2017, 05:50:43 pm
content: 3 x 74AUP1G74 by NXP will work up to 600 MHz @ 3V3. Alternatively 3 x SN74AUP1G80 by TI.

author: jpb
author_rank: Super Contributor
timestamp: February 19, 2017, 06:08:44 pm
content: It is possible (apparently, I've not done it in practice myself) to get much higher speeds out of logic families by introducing delay. See the third page of Charles Wenzels paper:http://www.techlib.com/files/dividers.pdfI would have thought also that using a fast D flip-flop to get down to 90 MHz then a divide by 4 or just 3 flip flops would work ok.Otherwise IDT does clock dividers that go up to well above 180MHz, e.g.http://www.digikey.co.uk/product-detail/en/idt-integrated-device-technology-inc/674R-01ILF/800-3317-5-ND/2005578If you go on the IDT site the following looks a good option:http://www.idt.com/products/clocks-timing/clock-distribution/fanout-buffers-dividers-and-multiplexers/87001i-01-lvcmoslvttl-clock-dividerThough looking on Digikey it appears to becoming end of life.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 19, 2017, 06:52:31 pm
content: Quote from: james_s on February 19, 2017, 05:39:22 pmFair comment. It's quite a while since I last designed with an EPM3032.MAX V would probably be a better bet now anyway.

author: Zero999
author_rank: Super Contributor
timestamp: February 19, 2017, 07:05:41 pm
content: How about the 74ALVC74? Rated to 300MHz at 3V and there are two per IC, which will simplify the design.http://pdf.datasheetcatalog.com/datasheet/philips/74alvc74.pdf

author: james_s
author_rank: Super Contributor
timestamp: February 19, 2017, 08:04:37 pm
content: Quote from: AndyC_772 on February 19, 2017, 06:52:31 pmI only suggested the 3032 because in the parametric search on Digikey it was the cheapest part that looked like it would do the job and I've worked with parts in that family before. Any number of similar parts would work just as well.

author: Benta
author_rank: Super Contributor
timestamp: February 19, 2017, 08:13:36 pm
content: +1 to MC12093.It's small, inexpensive and does the job. Icing on the cake: it's ECL, meaning almost no transients/noise on the supply lines.