Condensing identical pins? - Page 1
Forum section: electronics / general

author: Rachie5272
author_rank: Regular Contributor
timestamp: February 28, 2020, 05:49:48 pm
content: I'm working on the footprint for a part with dozens of identical ground and power pins, all meant to be connected together. So far the only way I know how to do this is actually place every pin in the schematic library, and connect them all in the schematic. This seems clunky and inelegant.Is there a better way to represent these connections?

author: thm_w
author_rank: Super Contributor
timestamp: February 28, 2020, 11:13:18 pm
content: Stack them and disable the name for all but one.The only "issue" with this is that when you connect the pin in your schematic it will show a dot, indicating multiple pins are connected together.edit:https://electronics.stackexchange.com/questions/403080/altium-assign-one-pin-to-multiple-pads

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 29, 2020, 12:16:02 am
content: If that's something with a lot of pins anyway (MCU, FPGA, etc.), probably just better to enumerate all of them, and toss the power sections off on their own sheets.You can stack pins, but it makes the dot, and doesn't specify which footprint pins are actually connecting, which may be helpful to read. Yeah, outstanding problem, pretty sure I've voted for the bugfix myself...Can also make a custom footprint, but this isn't really sensible for parts with pin counts this high. I do this sometimes for, like, single transistors. For example, the DFN/PDSO-8 footprints that are nominally 8 pins but 4+pad are literally the same piece of metal? Doesn't make sense to pin those differently. May have a few variants of those in case you run into, like, different gate/source pinouts, or I suppose there might be, like, regulators using the separate pins for whatever, and the rest as a tab, so they can't all be numbered 1-2-3 as they can for the MOSFET case. In which case you need a 1-2-3-4 and the rest 5 pinout.Personally, that's as far as I prefer to go, as far as folding pins together in footprints, and keeping variants of them.There's also the trivial-ish case, of unconnected pins -- I typically use '0' for unconnected (usually unplated mechanical) holes, of which there can be however many of, in a given footprint. Common on connectors with mounting pegs and such.Also, incidentally, a lot of packages are made in a certain way, for example SOT-223-4 and DPAK-3 (4 including tab) where the center pin is physically the same piece of metal as the main tab; but this isn't always the case, as there are some LDOs for instance in SOT-223 where pins 2 and 4 are not physically connected! Read the datasheet carefully.Tim

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: March 01, 2020, 10:26:16 pm
content: Personally I think the way you are doing it now is the best wayThink of it this way, someone pulls up your schematic a year down the track and has to figure out where GND is connected on this IC. Your current schematic footprint shows this clearly, but if you combine/overlay the pins then there will be more deciphering to do

author: exmadscientist
author_rank: Frequent Contributor
timestamp: March 02, 2020, 08:16:04 am
content: I agree with Tim on this one.My general rule for Altium is tonever stack or hide pins. Some other software (Cadence?) gets upset if you have multiple pins sharing designators or names or footprint pads. Altium does not, and you should use this to make your schematics as clear as possible:If a regulator has two pins for VOUT (example: a SOT-223 with pins 2 and 4), just put two VOUT pins on the component.If a footprint has two pads for a single pin (example: PCB-mounted quick disconnect), just put down two pads on the footprint. Everything will work out fine. (And don't use the jumper feature unless you have to. A good example of when it's appropriate would be PCB-mount heatsinks for say a TO-220 that have to be electrically connected to a node. If you route the heatsink net between the pins, you probably won't be able to get the transistor's pins routed!)Large ICs are best handled as you've done. Iexpectto see a pile of big power symbols for any complex IC.For packages like a power SO-8 FET, where there is one big "drain" tab that covers pins 5, 6, 7, and 8, I'll actually just call the pad "5678" because there's no way it can be anything else. This also ensures that if someone tries to link this footprint with a standard SO-8, there will just be a pin mismatch error and an obvious failure rather than a subtle latent bug.I've seen engineers who will handle a SOT-223 regulator by putting the 2 and 4 pins on top of each other, hiding the pin designators, and drawing it in themselves with a string. This is very brittle (if it's done wrong enough, even rotating the regulator can break it...), buys you nothing over doing it right with two distinct pins, and is even extra work.So don't bloody well do that!Schematics exist to document and communicate. They are there to explain your design, its goals, its intents, and its reasons for existence to other people: your colleagues, your manager, your customers, your field circus, and the most important and easily confused person of all... futureyou. Schematic drafting is not a time to show off your cleverness. It is a time to be so dull, straightforward, and transparent that other interpretations for your work simply can not exist. Making schematics as clear as possible is a sign of an expert engineer!(Apologies for the... I've had to deal with a few related messes at work lately, and venting helps....)

author: Rachie5272
author_rank: Regular Contributor
timestamp: March 02, 2020, 04:38:50 pm
content: Thanks everyone. I definitely don't like the idea of stacking or hiding pins, but I am contemplating naming multiple pads with the same identifier. This particular component is a module with its own specialized footprint, so there's no risk of reusing it. The issue then becomes lots of pads which are called "GND" rather than their proper pin number, and not being able to find them during debugging.It looks like the ugly way is probably the best.I'm curious if anyone here has experience asking altium staff to fix some of these long outstanding usability issues. They basically told me "nope, can't do that", even when offering to buy another license.

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: March 03, 2020, 02:25:39 pm
content: Quote from: Rachie5272 on March 02, 2020, 04:38:50 pmUnfortunately the best you can do is ask for it onhttps://bugcrunch.live.altium.com/. Unfortunately the clout needed to get altium to add functionality requires you to be a company with hundreds of licenses. They do have seemed to step up the bug crunch development in the past years though.

author: ajb
author_rank: Super Contributor
timestamp: March 03, 2020, 05:11:55 pm
content: In addition to all the other reasons to NOT do this, consider your time investment. How much time does stacking pins save you when you go to create a new schematic? Not a whole lot. How much does it cost you (time and money) to respin a board because of a mistake in the pinout of a part? Quite a bit!So given those two facts, how many different designs do you have to use the part in question in before the time saved in schematic entry justifies the increased risk of screwing up a board because you've made the design harder to validate by hiding information?Re: Bugs and useability, AD has been especially tumultuous over the last couple of years, and while some of the recent updates on their bug tracker have given a glimmer of hope that maybe they're renewing their focus on quality instead of shiny but half-baked 'features', there's still a huge backlog of longstanding issues. Go to bugcrunch and sort by oldest first, it's pretty amazing how long so many serious issues have been languishing for so long with zero feedback from Altium.