How do EEs evaluate new digital ICs - Page 1
Forum section: electronics / projects

author: rsridhar
author_rank: Contributor
timestamp: August 20, 2025, 04:31:25 pm
content: Hi,I have been getting more into hardware and after spending weeks trying to get an ADC working reliably with my DE0 Nano FPGA, and I have officially given up. I believe (don’t have a high enough speed O-scope to confirm) that I just have too much noise in my cabling for signals to be relatable; and I get lots of “noise” which I assume are misread bits.The way I have been trying to evaluate the ADC is to use a solderless adapter (like thishttps://www.amazon.ca/ALLSOCKET-QFP64-0-5-Programming-FPQ-64-0-5-06-QFP64-0-5-ACL/dp/B06ZYWJYXH) and connecting the dip pins to the FPGA demo board’s pins with jumper wire. The end looks like the attached - which I’m sure many of you will look at and know that I will see a ton of noise.My question is, what is the usual process of evaluating a new IC? Do you need to design a pcb which houses an FPGA and the IC you are evaluating, and get it manufactured? Or is there an easier way I am missing?I thought a FPGA demo board, package/pin adapter, and jumper wire was an easy way to do so. But what are the biggest sources of noise/mis-reading in this setup; is it the long cables (all signal cables were 3-4 inches)? The solderless package adapter or dip connections (causing reflections?)?

author: Terry Bites
author_rank: Super Contributor
timestamp: August 20, 2025, 05:59:14 pm
content: Signal integrity is everything in T&M.It doesnt look like you've got enough of it.Free Book

author: tggzzz
author_rank: Super Contributor
timestamp: August 20, 2025, 06:10:12 pm
content: Quote from: rsridhar on August 20, 2025, 04:31:25 pmSolderless breadboards cause many problems, not least because they often don't discourage excessive capacitance, inductance and mutual inductance. Here's an example (inspired by TAoE x-Chapters 2x.10 p138)https://entertaininghacks.wordpress.com/2024/03/16/practical-traps-with-a-one-transistor-audio-amplifier-solderless-breadboards-and-oscilloscopes/Another way of looking at that is if you do find a place where we can buy one of the interconnections seen in schematic and Spice simulations,pleaselet us all knowFortunately there are several other breadboard techniques which are simple, fast and cheap. See good and bad examples athttps://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/and then choose thecombinationrelevant toyourrequirements.

author: ejeffrey
author_rank: Super Contributor
timestamp: August 20, 2025, 06:45:00 pm
content: You didn't say what ADC you are using.In a professional setting, this is what people use evaluation kits for. They are expensive, but they have generally solved most of these problems. For high speed DACs/ADCs, most have settled on the FMC standard, so you can buy an FPGA evaluation kit and an ADC evaluation kit and snap them together.You should definitely check out if the manufacturer produces an evaluation kit. Even if it's out of your price range or won't meet your needs it should give you an idea of how the manufacturer expects you to use it.

author: rsridhar
author_rank: Contributor
timestamp: August 20, 2025, 09:09:06 pm
content: I am using a TI ADS8598 right now; but was also looking into other options as well. I am not tied to this ADC, I just need one that is100-200kHz, low latency (so sticking with SAR instead of Sig/Delta). I went with this chip since it also has a Parallel mode; which can xfer the sample in 2 clock ticks instead of 18 on SPI.I am really just doing a sort of proof of concept algorithm on an FPGA; so trying to find out the simplest way to test my ideas out (essentially ADC->FPGA Algorithm->DAC).I would worry that even with a demo board I would run into issues with signal integrity; if the issue is with the jumper cables. I guess the final takeaway for me is that I really need a Scope to find out where the signal integrity issues are coming from.Thanks for the response

author: rsridhar
author_rank: Contributor
timestamp: August 20, 2025, 09:22:24 pm
content: Quote from: tggzzz on August 20, 2025, 06:10:12 pmThanks. Very informative read for me. I am coming firm the world of dynamic signal analysis (Mechanical engineering) so we never consider lots of these effects.

author: rsridhar
author_rank: Contributor
timestamp: August 20, 2025, 09:23:38 pm
content: Quote from: Terry Bites on August 20, 2025, 05:59:14 pmThanks. I think my takeaway is that I need a scope.

author: David Hess
author_rank: Super Contributor
timestamp: August 20, 2025, 09:42:01 pm
content: Quote from: rsridhar on August 20, 2025, 04:31:25 pmAt higher frequencies where signal integrity becomes important, it is common to either use existing evaluation boards or to make your own evaluation board which may be essentially a prototype of the intended product or application.It is possible to prototype a circuit using Manhattan and dead bug construction with soldered breakout boards, but this is hardly ever done. This can work when the point-to-point wiring between breakout boards is over a ground plane yielding a low impedance transmission line environment, but it is not practical where a large number of connections are involved.

author: tggzzz
author_rank: Super Contributor
timestamp: August 20, 2025, 10:14:15 pm
content: Quote from: rsridhar on August 20, 2025, 09:22:24 pmGlad it has been of some use.I echo other contributors statements that "eval boards" are a very good starting point - especially for sensitive analogue devices, and digital devices with a large number of outputs.If a device's data sheet contains suggested PCB layouts, that is astrongindication that layout is critical.For digital devices and signals, ignore the clock frequency; the only relevant parameter is the transition time. The higher the number of outputs and PSU connections, the more important the layout.