Lattice Radiant Software runs too slow, 5+ minutes each time. - Page 1
Forum section: electronics / general

author: Shell Albert
author_rank: Contributor
timestamp: July 15, 2025, 12:41:30 am
content: Hi, Guys.I'm newbie to use Lattice LIFCL-40 FPGA,I downloaded the latest version of IDE Lattice Radiant Software Version 2024.2.0.3.0But when i compile my project, it runs extremely slow. I can't suffer.Each time, it takes me more than 5 minutes.especially, in the step of "Place & Route Design".previously, i use Altera Quartus, it runs fast.By the way, my operating system is Windows 11.CPU: Intel i5 @3.10GHz Memory: 32.0GBCould some give me suggestions?Best regards.

author: iMo
author_rank: Super Contributor
timestamp: July 15, 2025, 05:27:01 am
content: What is your design like? Complex designs with ice40UP5k (which is 3-4x smaller in resources) took me easily 3-4 minutes on a similar machine, afaik.

author: Shell Albert
author_rank: Contributor
timestamp: July 15, 2025, 07:46:02 am
content: My design is not complicated.Only receive OV5640 DVP Interface data, and write info Hyper-RAM.Compared to Xilinx/IBM(Altera), Lattice Radiant IDE is much slow.I highly recommend Lattice Company concerns about Users Feedback and makes upgrade.I used iCE40UP5K, not friendly to users.Lacking reference documents.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 15, 2025, 01:27:08 pm
content: First you need to compare the devices before comparing tools.How does a LIFCL-40 compare to whatever FPGA you were using with Quartus? Even with "small" RTL designs, P&R time increases with the number of LUTs and overall complexity of the FPGA itself.Then, the "strategy" used can make a significant difference too. You can also check whether you are using LSE or Sinplify Pro, as Radiant offers both and see if it makes a difference (although these are for synthesis and most of the execution time will be spent on P&R).

author: zapta
author_rank: Super Contributor
timestamp: July 15, 2025, 05:36:23 pm
content: What is the utilization report once the build is complete? (this will give an indication of the complexity of your design).You can also try with Apio, an easy to use open source fpga design toolbox. Details herehttps://www.eevblog.com/forum/fpga/new-to-fpga-but-considering-it-for-adc-decimation/msg5975615/#msg5975615

author: Someone
author_rank: Super Contributor
timestamp: July 15, 2025, 11:46:38 pm
content: Quote from: SiliconWizard on July 15, 2025, 01:27:08 pmQuote from: zapta on July 15, 2025, 05:36:23 pmUtilitzation, and also timing margin GREATLY affect implementation time. Larger device size is often paradoxically improving time to build as it slackens the utilisation and timing constraints.

author: laugensalm
author_rank: Regular Contributor
timestamp: July 22, 2025, 09:18:54 am
content: Yosys synthesizes significantly faster, typically under a minute on my 10 year old machine for a rather complex design. Including download..I migrated to Gowin though, their software and reference documents are surprisingly usable compared to the bloatware from the usual three big FPGA players. There are only minor synthesis issues with dual port RAM combinations (which you wouldn't run into on an ICE40).

author: iMo
author_rank: Super Contributor
timestamp: July 22, 2025, 11:26:51 am
content: Apio/Yosys is much faster in creating the bitstream, but I would check its output against radiant, sure. From my experience (well, years back when the yosys was starting) the icecube/radiant produced faster logic (up to 30-50%), and there might be small devils in the details hidden as well.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 22, 2025, 01:03:40 pm
content: If there is a larger (more resources) device available which is otherwise sufficiently similar to the one you are targetting, using this during development may be faster as it's easier to fit a design if more space is available.