Starting a State Machine at a known state - Page 1
Forum section: electronics / beginners

author: Pulse Cloud
author_rank: Contributor
timestamp: June 24, 2012, 06:54:46 pm
content: 1st year EE student here.How do I guarantee that a shift register (for example... could have said any type of state machine) is at a RESET (all '0's) state when I first use it?I'm designing a synchronous system to be used in a larger system (which infinitely loops) and I need to make sure everything's at a known state because in VHDL the std_logic type defaults to 'U' (undefined) and not '0'.My system's delay is 4 clock cycles, but it appears that I have to waste one clock cycle to reset everything first...Do I really need to? Is there another way?It really would mess things up because I'm using a counter to count the cycle the system's at and it would mean I would have to redesign a lot of it (and make it uglier).The exercises always told us to assume the initial state of whatever was all '0's, but I can't just assume things in a practical application.I'm writing the VHDL to test my circuit. I'm not really sure it will work as expected because I have to set the keypad's column to '0' andthenget the value from the row to the shift register.Also, if I reset everything at first, the clock counter will start counting from 1 instead of 0! Oh god, this is getting more complicated than I expected!

author: jahonen
author_rank: Super Contributor
timestamp: June 24, 2012, 07:19:43 pm
content: Not clear what you are actually trying to do, do you mean how you initialize a state of a variable or a signal in VHDL or do you want to initialize a shift register done with a discrete 74-series logic?For VHDL, you can try something like "signal x : std_logic := '0';" to initialize signal x to '0' from the very beginning. In case of the 74-series logic, you must arrange a asynchronous reset pulse by some means.Regards,Janne

author: Pulse Cloud
author_rank: Contributor
timestamp: June 24, 2012, 07:34:30 pm
content: Quote from: jahonen on June 24, 2012, 07:19:43 pmThis.I've thought about it and I think I can leave the schematic as is, but I need to do a quick (half cycle duration?) asynchronous reset to everything the first time the whole system starts, something like a "run once" initialization procedure. Not really sure how I could do that, though...

author: Simon
author_rank: Unknown
timestamp: June 24, 2012, 07:36:54 pm
content: I'm not sure why this is a problem, as soon as your circuit powers up a reset signal goes round to all IC's, your program cannot be running the nanosecond the power comes on....

author: IanB
author_rank: Super Contributor
timestamp: June 24, 2012, 08:29:13 pm
content: Quote from: Simon on June 24, 2012, 07:36:54 pmIn any real logic circuit you have to ensure that on power up everything is set to a known state. Off the shelf logic chips may do this automatically, but if you are designing custom logic you may have to do this yourself. Remember too that logic chips can reset their internal state and their outputs, but they cannot control their inputs. It may still be incumbent upon you to ensure your inputs all start up in the desired state when power is applied. Capacitors, for instance, may make this less than automatic (what is the time constant of the discharge resistors, and what if you do a fast power cycle before the capacitors have discharged?).

author: free_electron
author_rank: Super Contributor
timestamp: June 24, 2012, 08:44:22 pm
content: that's whay proper designs have a reset circuit.the reset pulse is valif for multipe clock pulses of the entire system. so both synchronous and asynchronous reset can be applied.

author: hlavac
author_rank: Frequent Contributor
timestamp: June 24, 2012, 09:51:41 pm
content: In Verilog you have theinitialprocedure block, not sure about VHDL didn't get to it yet

author: hlavac
author_rank: Frequent Contributor
timestamp: June 24, 2012, 09:55:35 pm
content: Here it ishttp://www.edaboard.com/thread28862.html

author: free_electron
author_rank: Super Contributor
timestamp: June 24, 2012, 11:08:44 pm
content: 'initial' is for SIMULATION only. It is NOT synthesisable !any block of logic needs to have a reset signal and there needs ot be a handler that sets all the flipflops to the right state.

author: vk6zgo
author_rank: Super Contributor
timestamp: June 24, 2012, 11:34:29 pm
content: This is a problem that rears its head with any control system,be it VHDL,discrete logic,PLC,relays,trained Gerbils,or whatever.You design this wonderful elegant system which does everything,providing that everything is already "up & running".When you try to start it from scratch,it doesn't work!!You are then confronted with butchering your beautiful design,so it will start up with everything in the "normal"operating state.At least you can simulate such things these days.Spare a thought for the person designing a relay based control system,back in the day,who had to sort these problems out on the actual system,with the Boss/Customer breathing down his neck!

author: caroper
author_rank: Regular Contributor
timestamp: June 25, 2012, 12:29:06 am
content: "Trained Gerbils" falls under fuzzy logic, but I do find that the "Include Persian.cat" statement tends to ensure that the Gerbils are in a known stare of panic and in the cage at start upCheersChris

author: hlavac
author_rank: Frequent Contributor
timestamp: June 25, 2012, 12:39:25 am
content: Quote from: free_electron on June 24, 2012, 11:08:44 pmThat is not the case at least with Altera's Quartus II. You just need to have synthesizable statements in the initial block, theyaresynthesizable.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: June 25, 2012, 06:10:41 am
content: Quote from: caroper on June 25, 2012, 12:29:06 amShouldn't that be 'Furry Logic' ??

author: jahonen
author_rank: Super Contributor
timestamp: June 25, 2012, 07:52:08 am
content: Quote from: hlavac on June 25, 2012, 12:39:25 amThat probably works in a FPGA where the whole logic matrix is initialized during the configuration process but does not generally work everywhere. Thus one should always include an asynchronous reset statement in the logic, like in VHDL:Code:my_process: process(clk, reset_n)beginif reset_n = '0' then-- Asynchronous reset stuff herex <= (others => '0');y <= '0';elsif rising_edge(clk) then-- Application specific synchronous stuff hereend if;end process;Small detail is that the reset_n signal should be synchronized to the clk signal to prevent odd timing issues but that is an another story...Regards,Janne