Interfacing high speed ADC to microcontroller - Page 1
Forum section: electronics / projects

author: tszaboo
author_rank: Super Contributor
timestamp: April 15, 2019, 03:07:58 pm
content: Hi. There is a project I'm investigating. One of the options is to interface a high speed ADC to a Microcontroller. We are talking about 30 MSPS 12 bit into an ARM cortex M4, running at about 120 MHz.My question is not about how to do it. This would be PITA and it probably wouldn't work in the end.My question is about proving that this is a really bad idea. Because there are ADCs with parallel CMOS interface, I actually need to give reasons why this wouldn't work, before we could go with the FIFO/DSP/FPGA and other routes. And it should work from less than a watt of course. Any white papers or application notes or articles? Thank you!

author: voltsandjolts
author_rank: Unknown
timestamp: April 15, 2019, 04:32:55 pm
content: I have no experience of high-speed ADCs feeding uCs.I do have experience of manipulating management decisions to make them go my way!In this case I would say something like 'Programmable logic offers a development process with reduced risk of systemic errors and thus improved estimates of costs going forward, particulary in respect of certification for regulatory compliance where the lower clock rates required by custom logic reduce the potential EMC profile'It's kinda fun, isn't it?

author: ataradov
author_rank: Super Contributor
timestamp: April 15, 2019, 04:55:22 pm
content: Microchip SAM S70/E70/V7x have parallel capture interface that can capture data on external clock. In combination will the DMA, it will handle 30 MHz without any issues. Obviously once you run out of buffer memory, there will be a gap in the capture. There is no way you will be able to process that stream in real time.

author: moffy
author_rank: Super Contributor
timestamp: April 16, 2019, 12:11:57 am
content: And what do you want to do with the data after you get it into the micro? NXP have an LPC4370 processor with integrated 12bit/80 MS/s ADC but it's what you want to do with the data. If you need to process at that rate or get it out that can be an issue unless it's just burst mode.

author: DaJMasta
author_rank: Super Contributor
timestamp: April 16, 2019, 02:14:46 am
content: Would it suffice to tell them that unless all the processing and communication that they want to happen would have to happen in three clock cycles because on the fourth you'll be getting another package of data from the ADC?DMA can help a bit, sure, but if they want continuous data transfer, a 120MHz single threaded chip and a 30MHz data input doesn't leave that much time for actually doing something with the data.

author: tszaboo
author_rank: Super Contributor
timestamp: April 16, 2019, 06:41:22 am
content: Hmm, so the S70 has something like the parallel master port on the PIC32s? That might actually do it.The NXP LPC4370 is another choice that might do it... Maybe I need to re-think this, cause it is possible?I need to store a few thousand samples, 40000 or so, and then there is plenty of time to process it, measurement stopped. That is why I was thinking about FIFOs, but they are ridiculously priced. Only ADT makes them, and this happens if there is no competition.

author: ataradov
author_rank: Super Contributor
timestamp: April 16, 2019, 06:45:30 am
content: Quote from: NANDBlog on April 16, 2019, 06:41:22 amI'm not syre what they have on PIC32s. S70 has Parallel Capture Mode where you have data lines + clock (an input) + clock enable pin (also an input).But it looks like this mode is limited to 8-bit bus, so it won't work for 12-bit ADC.

author: moffy
author_rank: Super Contributor
timestamp: April 16, 2019, 08:24:59 am
content: There is a good discussion about successfully using the NXP LPC4370 ADC @ 80 MS/s at:https://community.nxp.com/thread/429528It can be a bit complex to use sometimes as it has 3 independent processors inside, (you don't need to use them all) but the development environment is good and the LPC LINK 2 card provides a very cheap development board.

author: Someone
author_rank: Super Contributor
timestamp: April 16, 2019, 10:54:27 am
content: Quote from: NANDBlog on April 16, 2019, 06:41:22 amIf you don't need to do anything else significant when capturing, there are ranges of micocontrollers with external memory interfaces or camera/image sensor ports which can be used for that too.

author: jonroger
author_rank: Regular Contributor
timestamp: April 16, 2019, 05:45:21 pm
content: You could create your own FIFO using static ram. But micro-controllers are so simple and cheap that I'd also look at using several of them. Perhaps 5, each sampling at 6 Msps (20 instructions is probably enough to do something where 4 isn't).

author: DaJMasta
author_rank: Super Contributor
timestamp: April 16, 2019, 06:09:24 pm
content: Quote from: jonroger on April 16, 2019, 05:45:21 pmUnless you have an obvious choice of micro with a lot of SRAM built in, this would be my choice for what you're describing. Write directly to an external memory then have the micro load and process it. 40kS with 12 bit depth is certainly achievable with a micro's internal memory, but you're going to be looking at the high-tier priced parts, since 64kb probably wouldn't suffice after memory for your program and 40kS worth of storage, whereas a 64kb SRAM for samples and whatever amount you need on the MCU itself gives you a lot more flexibility with MCU choice and probably saves you a good bit on the price as long as you can afford the board real estate. Though, I guess, as far as 120MHz ARM M4s go, maybe you do actually have the SRAM onboard already, so just doing the whole thing on the MCU is paid for

author: ejeffrey
author_rank: Super Contributor
timestamp: April 16, 2019, 07:52:49 pm
content: TBH, this doesn't sound too hard as stated. It should be obvious that the microcontroller core can't do this in real-time, so you will need a GPIO DMA with enough speed and bits to handle your ADC. You also need the clock to work, so either you need a GPIO peripheral that can be externally clocked or you need the sample clock to by synchronous with your master clock. These requirements plus sufficient SRAM should filter you down to a handful of candidate parts and you can easily compare the cost and power budget vs. an external SRAM based FIFO or a small FPGA.The thing to emphasize in your comparison is flexibility and extensability. 40,000 samples is maybe fine, but then what happens if your requirements change to take 80,000 samples? With an SRAM based FIFO you just pick a bigger SRAM chip and add one address line. With an FPGA you may not need to do anything if it already has enough SRAM built in, otherwise maybe you migrate to a larger pin compatible part in the same family. With an MCU you probably have to scrap the project and start over with an FPGA, or at the very least do a complete redesign with multiple interleaved MCUs. If there is any chance you will need to process the data in real time (for instance to detect some error/out of range condition and trigger a halt in deterministic time), you want an FPGA.

author: Marco
author_rank: Super Contributor
timestamp: April 16, 2019, 07:54:28 pm
content: Here'ssomeone saying he managed 30 MHz with just triggered DMA and GPIO.FSMC/FMC might work better.

author: MasterT
author_rank: Frequent Contributor
timestamp: April 16, 2019, 09:21:00 pm
content: Quote from: Marco on April 16, 2019, 07:54:28 pmI did some test using stm32f446re, same family uCPU as f429, and mistakenly marked 36 MHz. After close inspection using two synchronous 4-bits counters 74lvc161 /163 and sorting input array for "missing code" , I downscaled my results. Down to 11.5 MHz ! So, it looks in theory like DMA has no limits to push data to memory, but reality shows a lot more details need to be considered. If GPIO port directly mapped to specific data bus, if there are "bridges" - what latency they have, etc.In summary, I'm absolutely sure 120 MHz uCPU NO Way could manage 60 MBytes/sec . For comparison, my stm32f446re is 180 MHz core, dual DMA - though only one may have an access to GPIO.

author: splin
author_rank: Frequent Contributor
timestamp: April 17, 2019, 02:53:01 am
content: The LPC4370 seems to be a no-brainer given that a 30MSPS 12bit ADC alone will likely cost you more - at Digikey the 40MSPS MAX1421ECM+D costs $7.24 @ 1K compared to $6.4 for the LPC4370FET100E. You will need to add an SPI FLASH but they are fairly cheap and physically much smaller than most standalone ADCs.The encrypted version (for firmware copy protection), LPC43S70FET100551, is only $5.09 from Avnet for which you get 282K RAM, a 204MHz M4 plus 2 x 204MHz M0 processors, Ethernet, USB and a powerful configurable serial peripheral etc. thrown in for free with the 80MSPS ADC.If it turns out to be advantageous to proceess in real-time then using the SIMD instructions you could get up to 12 instruction cycles per sample - not a lot but the ADC does have hardware high/low limit comparators which might help.Biggest issue might be the long term availability of the part but on that front you might not want to be comparing with a MAXIM ADC either - a TI part is over $10.

author: splin
author_rank: Frequent Contributor
timestamp: April 17, 2019, 03:56:52 am
content: If you want to use an STM32F4 then I highly recommend reading this:http://cliffle.com/article/2015/06/11/matrix/It's the third part of a series on driving an an 800 x 600 VGA display with an STM32F407 which goes into some depth on the STM32F4 DMA. He achieves 40MSPS memory to GPIO on a 168MHz part using the DMA in memory to memory mode. Although perhaps not directly useful for your use case, it provides some good information on the DMA implementation on the F407 whilst being succinct and refreshingly well written. I wish I could communicate 10% as effectively...Most interesting is the amount of non-documented (by ST) stuff he covers and the real world behaviour. I suggest reading all parts - it shouldn't take long - as an excellent insight into problem solving and working out what the documentation fails to tell you.

author: tszaboo
author_rank: Super Contributor
timestamp: April 17, 2019, 08:16:49 am
content: Quote from: splin on April 17, 2019, 02:53:01 amYes, I think this is what I'm going to present as the easy solution. The ADC is in it, has a margin for the sampling speed, and probably lower power overall than driving an entire bus on the PCB, lower component count and size. I just completely forgot about this part.Quote from: ejeffrey on April 16, 2019, 07:52:49 pmThis is already the redesign part. We have a prototype operated at 5 MSPS, and they found out that is too slow. The firmware guys are still trying to do equivalent sample method to get some more data, but it seems that the signal is not that repeatable, at least not to 12 bit.

author: jonroger
author_rank: Regular Contributor
timestamp: April 17, 2019, 12:44:34 pm
content: Looks like the NXP LPC-Link2 can act as an evaluation board for the LPC4370.

author: tszaboo
author_rank: Super Contributor
timestamp: April 19, 2019, 01:15:15 pm
content: By the looks of it, they can do equivalent sampling, so I dont need to make an entirely new project out of it.Solving hardware problems by firmware again.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: April 19, 2019, 05:13:48 pm
content: The Cyrpess FX2 series uC are a quite lowly 8051 derivative (They never seem to die) but it has a quite nice feature to stream bulk data to an USB interface quite rapidly, but it cops out at (I think) 24MSps. But what do you expect for that price? It's quite popular in EUR7 logic analysers and entry level USB scopes.The newer FX3 series does the same trick, but on USB3 and development boards cost around EUR 60.