Working with FPGA - Page 1
Forum section: electronics / general

author: Stiege
author_rank: Regular Contributor
timestamp: February 08, 2013, 10:12:38 pm
content: Hey everyone,I'm recently been getting into designing stuff on an Altera DE0 board at home, but at work I'm also using a Spartan 3a-dsp 1800 development board. I'm enjoying it heaps, but I'm confused about what's required to use an FPGA without a development board. Especially regarding how the FPGA has to be reprogrammed on every power up. Are there stock parts for this? Are they unique to Altera vs Xilinx FPGAs, or is it all fairly generic.Basically any directions on where I can read about porting my designs from the development board and onto my own board would be appreciated.Kind regards and thanks in advance

author: marshallh
author_rank: Unknown
timestamp: February 08, 2013, 10:37:39 pm
content: The bare minimum for an fpga design to run standalone:1. Power supplies (I/O voltages of maybe 3.3/1.8/2.5, analog PLL supplies 2.5v, Vcore 1.2v or 1.1v)2. Clock source (50mhz LVCMOS oscillator is common)3. Config storage (usually SPI flash rom)Altera's EPCS chips are just remarked ST/Numonyx flash roms. If you are careful about what specs parts you get you can find a drop-in commodity replacement.FPGAs generally have builtin self-configuration circuitry. They have a rough internal oscillator, enough to clock in bits from the external SPI rom.They will also have a variety of other configuration schemes, fast parallel, fast serial (QSPI), etc... It depends if you need to re-configure the FPGA on the fly to swap operating modes often, or just send updates in the field.For lowest PLL jitter at the very least put a pi filter on the Vcca supplies, you can use a switching regulator fine.Low-demand fpga boards can get by with just a few LDOs.For low voltage, high current core voltages like 1v2, use a push pull converter instead of the classical buck converter. I use the semtech SC185, switching speed is 1Mhz and uses cheap small passives. For high speed switching regs like this you will want to use MLCC caps, not alum. electrolytic because of their lower ESR.Anyway that's the real bog-standard stuff, more specific applications will come with more specific requirements.

author: Stiege
author_rank: Regular Contributor
timestamp: February 08, 2013, 10:54:44 pm
content: Quote from: marshallh on February 08, 2013, 10:37:39 pmGreat!So I'm looking for more information on the config storage. The DE0 board has a Cyclone III 3C16 FPGA. I've had a quick look though some of the literature:http://www.altera.com/literature/lit-cyc3.jspIs that the best way to learn about it? It talks about a lot of standards that I have pretty much no understanding of, do I have to understand all of that before I can implement a basic FPGA design? Where's a good starting point that just covers the basics for implementing an FPGA design and covers some of the options that I could look into?

author: marshallh
author_rank: Unknown
timestamp: February 08, 2013, 11:02:49 pm
content: Read, read, read. There is no short cut. FPGAs are picky and you are only going to know what you're doing if you get in there and learn it. The Cyclone III handbook is a compilation of all relevant chapters.Don't sweat it over all the chapters over SSTL, LVDS, QDR sram blah blah, the short story is that there are several categories of pin types and within those each pin has several different possible functions determined by the device fitter (part of synthesis)

author: Unknown
author_rank: Unknown
timestamp: February 08, 2013, 11:42:26 pm
content: A while ago I bought a very minimal fpga dev board which looks like one of these, the schematic for it is pretty much the bare essentials but it gave me a good "boost" up and over the wall into fpga land! without doing too much reading ;-)http://www.topelectronics.com.au/image-eb/EP2C5T144.pdf

author: Stiege
author_rank: Regular Contributor
timestamp: February 08, 2013, 11:54:48 pm
content: That's excellent! Nice reference to Phi just there.

author: EEVblog
author_rank: Unknown
timestamp: February 09, 2013, 12:16:47 am
content: Just take any FPGA development boardfor the same chip family you are usingand simply copyexactlyeverything it's doing. SPI FLASH boot memory, power supplies, clock, config pins etc.Once you have that base working system, you can work backwards and figure out why they are doing what they are doing.Different families of FPGA can have very differing requirements, let alone between brands whcih can use entirely different terminology and configuration techniques.If you get one config pin wrong, or put the clock on the wrong pin, then your system will just sit there and do nothing, or give you lots of confusing errors.Dave.

author: Stiege
author_rank: Regular Contributor
timestamp: February 09, 2013, 12:54:22 am
content: Very pragmatic, I'll take that advice.

author: EEVblog
author_rank: Unknown
timestamp: February 09, 2013, 08:42:35 am
content: I forgot that I have a video on this. Kinda, it's a bit random, but might have some useful info.Dave.

author: Codemonkey
author_rank: Regular Contributor
timestamp: February 09, 2013, 10:40:05 am
content: Quote from: EEVblog on February 09, 2013, 12:16:47 amNot quite so straight forward with the DE0-Nano board, its also got circuitry on there that acts as an Altera Byteblaster. Its a shame you can't re-purpose it to use it to program other boards when you start doing your own designs.

author: EEVblog
author_rank: Unknown
timestamp: February 09, 2013, 11:26:10 am
content: Quote from: Codemonkey on February 09, 2013, 10:40:05 amYes, good point. It should be a dev board that is only programmable via JTAG. Not these smarter all-in-one dev boards.Dave.

author: Neilm
author_rank: Super Contributor
timestamp: February 09, 2013, 11:42:59 am
content: If you are looking at porting designs between chip manufacturers, do your best to ensure that the code has been done in a portable format, like VHDL or Verilog. I worked for a company many years ago that insisted that everything be done in a schematic capture format. (They used OrCad). Unfortunately for them, OrCad promptly dropped the FPGA synthesis support meaning they ended up with a station that was using an old version of OrCad and couldn't be updated and would not support the latest chips.They then decided that the best thing to do would be using the manufacturers schematic capture options. No problem there, every thing worked - until the head office made a deal with a big FPGA manufacturer and decided that all FPGAs would be from that manufacturer.The result was I had to re-write the code for a third time, only in this instance it was in the format I had originally asked for - having "accidentally" mentioned in a meeting that if we had made it portable in the first place, my time wouldn't have been tied up for best part of three weeks (again).Neil

author: EEVblog
author_rank: Unknown
timestamp: February 09, 2013, 11:59:14 am
content: Quote from: Neilm on February 09, 2013, 11:42:59 amOut of interest, I know of cases (military) where schematic capture is used for FPGA's because VHDL ad Verilog are classed as "source code" and therefore fall under different stricter regulatory requirements. Source code in this instance has to have every line of code independently checked and verified at $$/line, but schematic capture falls under the "hardware" definition, so they get away without doing that!Dave.

author: Marco
author_rank: Super Contributor
timestamp: February 09, 2013, 01:04:30 pm
content: It's a shame there is no universal markup for VHDL/Verilog which at least lets you (portably) design the hierarchy and signal connections in schematic form.

author: Christe4nM
author_rank: Unknown
timestamp: February 09, 2013, 01:13:29 pm
content: Quote from: EEVblog on February 09, 2013, 11:26:10 amThe Terasic Max-II CPLD microkit does have an on-board USB Blaster that with a breakout header for stand alone use to program your own devices using JTAG. Unfortunately for me the shipping costs outweigh the purchase price by a lot.

author: free_electron
author_rank: Super Contributor
timestamp: February 09, 2013, 04:13:33 pm
content: Quote from: marshallh link=topic=14109.msg190436#msg190436No they're not. If you pay a chip maker enough he will put whatever you want on the package. No need for re-marking. They're now made by micron. ST spun off flash to numonyx which got 'borged' by micron.But yes, they are essentially 25F series spi flash chips. And they were fabbed by ST for a long time

author: Neilm
author_rank: Super Contributor
timestamp: February 09, 2013, 05:40:11 pm
content: Quote from: EEVblog on February 09, 2013, 11:59:14 amIt was a company making military hardware I was referring to. The diktat at the end was done from head office who also insisted we use VHDL (although after I made my comment to managers).Neil

author: Stiege
author_rank: Regular Contributor
timestamp: February 10, 2013, 02:32:52 am
content: Thanks for all that info. I have actually watched that video already, and it was very useful. I use VHDL at work on the spartan 3a-dsp, and I use verilog on the DE0. This way I'm covering all the permutations of language and brand.Have been reading the datasheets some more and I understand the config stuff a lot better now.Being a student is such as shame, all the will in the world but have to save my pennies to afford some of the gear I need to implement this stuff. Feel like I might try to something with a low cost Xilinx chip since I have the programmer at work. Sort of stuck with doing anything with an Altera device, as has been mentioned about the on board DE0 programmer.

author: Marco
author_rank: Super Contributor
timestamp: February 10, 2013, 02:56:31 am
content: A blaster clone is 10$.

author: Stiege
author_rank: Regular Contributor
timestamp: February 10, 2013, 08:16:27 am
content: Quote from: Marco on February 10, 2013, 02:56:31 amSorry? I thought the USB blaster would be my only real option. Where could I find this clone?

author: jeroen74
author_rank: Frequent Contributor
timestamp: February 10, 2013, 08:31:12 am
content: A $10 clone is likely one that uses the parallel port. You don't want that.Another one for which you don't need an external programmer:Morph IC II. IIRC it recalls the FPGA configuration from the host PC upon connection, so might not be what you're after.Schematic capture of FPGA logic is handy to replace old-school 74xxx based logic boards with an FPGA. You can do this with Altera Quartus and also use the special IP blocks like RAM blocks, multipliers, PLLs etc. Though replicating timing tricks with RC networks is bit trickier in an FPGA.

author: EEVblog
author_rank: Unknown
timestamp: February 10, 2013, 08:53:36 am
content: Quote from: jeroen74 on February 10, 2013, 08:31:12 amNope, it's the USB Blaster.AU$8.98 delivered from Hong Kong!http://www.ebay.com.au/itm/New-Mini-Usb-Blaster-Cable-For-CPLD-FPGA-NIOS-JTAG-Altera-Programmer-/180891115065?pt=LH_DefaultDomain_0&hash=item2a1df35e39&_uhb=1#ht_4697wt_1397Dave.

author: jeroen74
author_rank: Frequent Contributor
timestamp: February 10, 2013, 08:56:04 am
content: Amazing...

author: Stiege
author_rank: Regular Contributor
timestamp: February 10, 2013, 08:07:40 pm
content: Sweet!

author: Stiege
author_rank: Regular Contributor
timestamp: February 10, 2013, 09:02:51 pm
content: So just in my quest to learn more about FPGAs I decided to check out what was on the market. Found the most expensive FPGA on Mouser:http://nz.mouser.com/ProductDetail/Altera-Corporation/5SGTMC7K2F40C2ES/?qs=sGAEpiMZZMvoScKlWpK8TBFFO0FjFVkjBsZMkmLO2aw%3dI'm not sure who pays over $50 000 for a chip. Has anyone ever played with one of these things? What's it used for? I'm thinking maybe areas like international fibre optic link data management systems maybe?

author: jeroen74
author_rank: Frequent Contributor
timestamp: February 10, 2013, 09:11:48 pm
content: I think its main use is ASIC prototyping. Or very high end low volume stuff like MRI scanners and the like.

author: Unknown
author_rank: Unknown
timestamp: February 10, 2013, 09:16:47 pm
content: I think Dave mentioned using some of these expensive FPGAs in military products: not enough volume for ASICs, but too complex for smaller FPGAs. Paying $50k per chip might still be cheaper than developing a custom ASIC if you will only sell 10-100 of them.

author: Stiege
author_rank: Regular Contributor
timestamp: February 10, 2013, 09:33:22 pm
content: Quote from: alm on February 10, 2013, 09:16:47 pmMmmk. The PhD students here sometimes design their own ASICs and have 10 or so manufactured. Apparently the cost is around the $NZ10k mark. Think I'm talking about 45nm technology (but could be wrong, don't know a whole lot about it).For $50 000, $83 per pin, I would really expect some sexy results from this thing.

author: jeroen74
author_rank: Frequent Contributor
timestamp: February 10, 2013, 09:41:09 pm
content: How sexy the results are, only depends on the designer using the chip530K LEs is enough to place ~150 NIOSII CPU on one chip.These are monstrous chips with dies the size of big stamps. Low production, low yield... high priceProbably made to order too.

author: ChipArchitect
author_rank: Newbie
timestamp: February 11, 2013, 03:42:54 am
content: Quote from: Stiege on February 10, 2013, 09:33:22 pmNo semiconductor company will manufacture only 10 chips for a commercial customer - the cost figure you're mentioning is only valid for subsidized "shared mask" chip manufacturing programs for education. Pretty much every industrialized country either runs, or has access to such subsidized semiconductor prototyping programs (MOSIS in the USA, Europractice in the EU, etc.) that allows students and other university personnel to get their chips manufactured at low prices.Not too many small companies have access to these programs, and even if they did; the performance improvement they would get by getting an ASIC manufactured vs. simply implementing an FPGA is often not worth the complexity/cost of designing the ASIC; so an FPGA is usually the most viable solution for low-volume applications.

author: amyk
author_rank: Super Contributor
timestamp: February 11, 2013, 12:01:34 pm
content: Quote from: ChipArchitect on February 11, 2013, 03:42:54 am"low", relatively speaking.I've looked up prices for chip fab before and thought about whether ways to decrease the initial mask costs, processes, etc. could lead to much cheaper services much like what iTead/Seeed does for PCBs today. It doesn't have to be the latest process with a dozen metal layers, but making rapid chip prototyping more accessible to e.g. hobbyists (and then also small companies) may lower ASIC costs considerably.

author: jeroen74
author_rank: Frequent Contributor
timestamp: February 11, 2013, 12:15:23 pm
content: Why would you want an ASIC? FPGAs are perfect for this if it's only digital. If you need analogue stuff, that's something for a specialist chip designer. Things are done completely different on a chip then you would with regular components.You have no resistors and capacitors, only in extremely small values, so things are replaced with current sources and mirrors. That's why you some ICs have a 'reference resistor' pin. From that single current a whole bunch of other currents are derived using current mirrors and different transistor geometries. There is an ebook on the internet on analogue chip design, IIRC written by the 555 designer. Very interesting read.IC fabrication is so expensive compared to PCBs that prices probably never get down that becomes feasible from low volume stuff. Where low is likely millionsExcept for specialist applications where there's is no alternative to an ASIC; like cochlear implants, there is a reason the implant costs like €25K and the external behind-the-ear piece about €8K.

author: free_electron
author_rank: Super Contributor
timestamp: February 11, 2013, 04:35:00 pm
content: Quote from: Stiege on February 10, 2013, 09:02:51 pmMmm, you can get those cheaper directly from Altera.But then again , thes parts are a selected few that perform extremely well from a whole batch.We got a few boards laying around from the Dini group. If you think this fpga is expensive.. Try a board that has six of em on it...You do not wanna know the cost of those things.These super fpga's are used to prototype asics. Nobody really uses these in production.

author: Stiege
author_rank: Regular Contributor
timestamp: February 11, 2013, 07:22:23 pm
content: Quote from: ChipArchitect on February 11, 2013, 03:42:54 amThanks, I was aware it was shared mask, but wasn't aware that not everyone had access to that.

author: free_electron
author_rank: Super Contributor
timestamp: February 11, 2013, 07:59:05 pm
content: Basically anyone has access to MOSIS. the problem is getting the toolkit and the layout tools...