logic design Question: Doubling a pulse too two clock pulses / delaying by 1 clk - Page 1
Forum section: electronics / general

author: BurnedResistor
author_rank: Regular Contributor
timestamp: April 26, 2017, 09:17:08 am
content: Hello All,Fairly new to logic design so bear with me. I was trying to convert a pulse of a single clk cycle image to a pulse on the next pulse, and a pulse the width of two clock pulses (see attached pic again)I was however struggeling quite a bit.Is this possible with a fairly easy logic design? Generating one and then generating the other from it would also work!Regards

author: Ian.M
author_rank: Super Contributor
timestamp: April 26, 2017, 09:23:31 am
content: Please use a ruler and/or squared paper so we can see how the pulse edges line up.

author: capt bullshot
author_rank: Super Contributor
timestamp: April 26, 2017, 09:25:25 am
content: You didn't specify setup and hold times - that makes it more difficult to find a suitable solutionYou can do something like that:use a D-FF latching IN at the rising edge of CLK to generate OUT1, then another D-FF latching IN or OUT1 at the falling edge of CLK to generate an intermediate signal, then push OUT1 and intermediate into an AND gate to generate OUT2Edit: OUT2 could also be generated by AND-ing OUT1 with inverted CLK - beware of glitches

author: BurnedResistor
author_rank: Regular Contributor
timestamp: April 26, 2017, 10:41:59 am
content: Quote from: Ian.M on April 26, 2017, 09:23:31 amQuote from: capt bullshot on April 26, 2017, 09:25:25 amVery Nice!Thank you for your help, and sorry about the diagram. For the second round I figure out WaveDromNow the previous circuit descried by capt bulshot required the signal to be present before the clock, if they are in the same instant, there is a race condition. Is it possible to design a circuit which would perform similarly, but even if the input came up after the beginning of the clock pulse?Kinda hard to explain, diagram should talk novels (hopefully!)

author: capt bullshot
author_rank: Super Contributor
timestamp: April 26, 2017, 11:09:12 am
content: Well - it still depends on the timing of IN related to CLK:you may consider using a D-FF with Set/Reset inputs like the '74:Set the FF via the static S input, using inverted IN, use the rising edge of CLK to latch a static LOW (reset at CLK edge) - maybe you want to add some CLK enable logic (like AND of (FF out latched with second D-FF at the falling edge of CLK) and CLK) to avoid too early resetting.

author: BurnedResistor
author_rank: Regular Contributor
timestamp: April 26, 2017, 11:10:01 am
content: Ups. Now with white background!

author: BrianHG
author_rank: Super Contributor
timestamp: April 26, 2017, 11:44:47 am
content: The simplest is using a DFF, tie the DFF's data input to GND. The DFF's positive edge clk to your 'clk'. Positive asynchronous set to your 'in'.When your 'in' goes high, the DFF's output goes high immediately and locks high until your 'in' goes low. The output of the DFF wont go low until the next 'clk' transition from low to high.You didn't provide the exact timing for out #2. There are similar tricks to do that signal as well depending on how you want it timed.Since I don't know what king of IC you may have access to, the appropriate 2 or 3 74LSxx, or 74HCxx should work, though I was personally thinking PAL/GAL/FPGA code with my above instructions since you placed the question in this section.A single positive edge triggered DFF register with async set written in Verilog should be around 5 lines of code.It's time for bed, I hope I got this right...

author: Rerouter
author_rank: Super Contributor
timestamp: April 26, 2017, 11:51:44 am
content: So to my eyes, you want Out to Equal In while it is high, and then remain high until the next rising edge,Equally you want output 2 to be the XNOR of Out and In. (Only high when they are different, probably done with 2 nand gates)Attached looks to meet your timing diagram, uses a hex nand gate chip.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 27, 2017, 09:35:39 pm
content: Would something likehttps://www.onsemi.com/pub/Collateral/MC74HC74A-D.PDFbe of any help? It is a D Flipflop with async set /reset.You would need to tie D low, invert your input to match the 'inverted set' input, and it will stretch any incoming pulse till the next clock edge.

author: rstofer
author_rank: Super Contributor
timestamp: April 27, 2017, 09:43:12 pm
content: Quote from: hamster_nz on April 27, 2017, 09:35:39 pmI never really liked asynchronous logic.The input pulse is apparently unrelated to the clock and it could turn out that the input bit sets the flop a couple of nanoseconds before the falling edge of the clock resets it. Runt pulses seem guaranteed.

author: BrianHG
author_rank: Super Contributor
timestamp: April 28, 2017, 11:48:25 am
content: Quote from: rstofer on April 27, 2017, 09:43:12 pmIn my first description, I chosen this solution since the OT didn't define setup times, delays, and other important info if you want to make a clean RTL design. Remembering that this question was placed in the FPGA/Microcontroller forum, I think the OT was looking for logic code to put in a FPGA or PLD.If I were to do a cleaner version of something along the line of interpreting the OT's inputs, I would use 2 D-flipflops in a row, DQ-DQ, with positive and negative edge triggered clock input shifting the input at every clock transition. This would be clean and no async.Data in would come from the OP's data in.Out would be DFF's #1, #2 output OR ed together.No async here, the input is just being shifted every rise and fall of the clock, unless you have a really old PLD/FPGA from years back which couldn't do positive and negative clocking on a macrocell.BUT, looking at the OT's second diagram, his output swings immediately after the source rises, exactly 50% in-between a clock cycle.I guess you can cut my design down to 1 D-FF and OR the input with the output of DFF's for the effect.Without knowing why and how the OP needs this pattern, what it is being used for, this is the best suggestion I can make.However, the best FPGA solution is to do all logic on a single rising edge, synchronous clock design if possible. All all IOs, especially if high speed, are synchronous DFF driven or data inputted unless you are struggling to preserve macrocells.The last solution is just to use a enable low transparent latch (tied to clk). When the !LE input his high, the output = the input (in) in real time, but, when the !LE goes low, the output holds the last state. This might be finicky due to the timing of the OP's source waveforms.

author: rstofer
author_rank: Super Contributor
timestamp: April 28, 2017, 02:19:25 pm
content: Quote from: BrianHG on April 28, 2017, 11:48:25 amI don't think FPGAs like asynchronous logic. I know Xilinx ISE warns about it.QuoteI was thinking, broadly, about doubling the clock rate. Personally, I have never tried clocking on both edges but it serves the same purpose.QuoteI was wondering about the timing and why the input is so far removed from the clock edges and the pulse so much narrower than a clock state. I wasn't sure that 50% was real or just where the OP happened to draw the input.It seems to me that the alignment of the leading edge is important somehow but the trailing edge is also a concern. Is the pulse always about 1/4 of a clock state. Will the falling edge of the input always occur before the falling edge of the clock? I guess we take the diagram as is...QuoteYup! Single rising edge is what I prefer. Even if I have to create a 2x clock (assuming I get to choose the clock).

author: Someone
author_rank: Super Contributor
timestamp: April 29, 2017, 04:23:47 am
content: Quote from: rstofer on April 28, 2017, 02:19:25 pmThey warn about it as they can't make timing constraints against asynchronous designs, but the FPGA fabric actually has quite a few asynchronous primitives and the capability to do dirty tricks if you want.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 29, 2017, 09:21:20 am
content: Just in case BurnedResistor is still watching, and is thinking FPGA/CPLD, here is some code that seems to do what he is after:Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity test_module isPort ( clk : in STD_LOGIC;i : in STD_LOGIC;q1 : out STD_LOGIC;q2 : out STD_LOGIC);end test_module;architecture Behavioral of test_module issignal reg0 : std_logic := '0';signal reg1 : std_logic := '0';beginq1 <= reg0;q2 <= reg1;process(clk,i)beginif i = '1' thenreg0 <= '1';reg1 <= '1';elsif rising_edge(clk) thenreg1 <= reg0;reg0 <= '0';end if;end process;end Behavioral;You can see a video of it running on a devboard here:(LED0 is the clock, LED1 is Q1, LED2 is Q2, and the button is the input I)I've also attached a schematic.

author: sokoloff
author_rank: Super Contributor
timestamp: April 29, 2017, 12:49:11 pm
content: @hamster_nz - that video comes up as unavailable for me. (might be set to private for you?)

author: hamster_nz
author_rank: Super Contributor
timestamp: April 29, 2017, 08:18:33 pm
content: Quote from: sokoloff on April 29, 2017, 12:49:11 pmOops, grrrrr, sigh.. fixed