Custom Pad with 'No Net' causes short circuit rule violation - Page 1
Forum section: electronics / general

author: MrRadiotron
author_rank: Contributor
timestamp: November 04, 2015, 07:14:34 am
content: Hi,I've made some custom pads to better match a manufacturers recommended land pattern.Every thing is fine unless the pad has no net,Altium will then report a short circuit between 'pad on top layer and region on top layer'. (see attached image).I've followed free_electrons advicehereInvoking "Design -> Netlist -> Update Free Primitives From Component Pads..." works,the regions are assigned the same net as the pads, "No Net".....so the violation is still valid.I've tried allowing short-circuits between 'No Net' and 'No Net', (see attached image)I've also tried Non-Specific No ERC directives in the schematic, (see attached image)any ideas on how to get around this without assign names nets to every unused pin?thanks so much for reading!

author: Gribo
author_rank: Frequent Contributor
timestamp: November 04, 2015, 09:20:05 am
content: Per your layout screen capture, you still have left over objects connected to the pads. Delete them and you should be fine.

author: ajb
author_rank: Super Contributor
timestamp: November 04, 2015, 03:36:22 pm
content: From recollection, 'No Net' is not actually a net, so using it as an a argument to the InNet() function doesn't work. You need to use "Not InAnyNet" to return objects that are not assigned to a proper net. That's why your design rule didn't work, and may be why Altium throws a design rule violation with the default rules in the first place.

author: Fgrir
author_rank: Regular Contributor
timestamp: November 04, 2015, 05:40:57 pm
content: Quote from: MrRadiotron on November 04, 2015, 07:14:34 amIf you are not philosophically opposed to the nets being named and just don't want to have to do it yourself, you can select the "Allow Single Pin Nets" project option. Beyond what the name suggests it will also assign named nets to the unused pins for you. I would think that would make your problem go away with very little effort on your part.

author: MrRadiotron
author_rank: Contributor
timestamp: November 05, 2015, 10:52:04 am
content: all fantastic suggestions, I'll see how I go tomorrow and report back.

author: MrRadiotron
author_rank: Contributor
timestamp: November 05, 2015, 11:07:48 pm
content: Quote from: Fgrir on November 04, 2015, 05:40:57 pmThis solves my problem, but I think I am philosophically opposed to the nets being named, or more so, allowing single pin Nets,by highlighting all net objects with 'No Net' I can quickly find faults in the schematic,e.g. three components are in series and two of them have 'No Net' pins, somethings up!Quote from: ajb on November 04, 2015, 03:36:22 pmThis works and I like it the most,I assume because this is a short circuit constraint rule,it won't stop clearance constraint rules applying to other non net objects?I'm pretty sure it won't, but tell me if I'm wrong!thanks all

author: wireworker
author_rank: Newbie
timestamp: September 05, 2016, 06:35:12 am
content: QuoteI had the exact problem and doing as you suggested did solve it for me - the nets were all assigned to a common one (GND) in my case, not "no net". It is possible that I had already manually assigned the pad in the middle of the copper poly region a net name of GND in past edits, so Altium took that as the new net name for the copper poly primitive.

author: Bud
author_rank: Super Contributor
timestamp: September 08, 2016, 04:15:17 am
content: Why bother adding regions to unused pads ?If I am not happy with a supplied footprint I copy it to my custom PCB library and edit to my liking, then link it to the part schematic.