Why did removing capacitor, restore VRef of DAC? - Page 1
Forum section: electronics / repair

author: paul8f
author_rank: Regular Contributor
timestamp: September 23, 2019, 08:12:15 pm
content: Hi,had an issue recently where a DAC chip was not generating its own internal voltage reference. I think it was a 4ch Analogue Devices model, where VREF needed to be configured at power-up. The configuration sequence gets sent from the MCU to the DAC using the linesSCLK,DINandSYNC.At power-up, the scope showed activity on the DIN and SYNC lines, but nothing on the SCLK line. I desoldered the filter cap from the SYNC line, and hey presto... the 2.5v VREF was once again output on DAC pin 10!The removed cap measured very close to the expected 100nF, and it was not shorted, so why did removing it restore VREF???

author: shakalnokturn
author_rank: Super Contributor
timestamp: September 23, 2019, 08:29:50 pm
content: The DAC model would help...Depending on pulse width/frequency of SYNC line there may not be much variation left after the filter, other than that if the transitions are slow enough for the filter to actually let them exist it could just be that the filter adds enough delay for SYNC to be out of sync with whatever it's needed to sync....

author: wraper
author_rank: Unknown
timestamp: September 23, 2019, 08:36:29 pm
content: Why did you think it was a good idea to put a cap on clock signal to begin with? It basically becomes a dead short to any signal that is not very slow.

author: paul8f
author_rank: Regular Contributor
timestamp: September 23, 2019, 08:55:08 pm
content: Not my design, I just drew the partial schematic from memory.I'll post back with DAC model, and double check values etc.

author: paul8f
author_rank: Regular Contributor
timestamp: September 24, 2019, 06:29:37 am
content: Quote from: paul8f on September 23, 2019, 08:55:08 pmOk...The DAC is anAD5644.My diagram had 2 mistakes...:(1) The filter cap was supposed to show1nF(2) The SCLK line was actually fed topin 7on DACAnyway, I think I figured out the problem... the cap when removed from the PCB measured closer to 100nF than 1nF, so the clock signal coming in was getting attenuated. I'm guessing the cap being 100 times too big, meant all the energy from the clock signal went into trying to charge the cap, rather than signal the chip...

author: wraper
author_rank: Unknown
timestamp: September 24, 2019, 10:18:32 am
content: Quote from: paul8f on September 24, 2019, 06:29:37 amDunno who made that circuit. But using cap there is counterproductive. Even if it's 100 times smaller. It can only make things worse, not better. Generally is no reason why you would put capacitor on SPI, tiny one like <30 pF might be acceptable though in some cases if say clock speed is slow and you fight with some interference.

author: paul8f
author_rank: Regular Contributor
timestamp: September 24, 2019, 07:23:07 pm
content: Quote from: wraper on September 24, 2019, 10:18:32 amI'm not sure of the LPF requirements for the SPI in this design. Thousands of units have been made, so I'm sure the designer knew all about impedance matching, risk of EM interference, and the relative speed of the bus. 1nF is still really small, especially since the micro only runs at about 14MHz, so the SCLK line of DAC is probably only a fraction of that.Thanks to all for your help.

author: wraper
author_rank: Unknown
timestamp: September 24, 2019, 07:47:50 pm
content: Quote from: paul8f on September 24, 2019, 07:23:07 pm1 nF cap + 100 ohm resistor there can only mean that someone who designed that crap had no clue what he was doing. I can assure you, I had repaired plenty of $40k devices which were produced for many years with many engineering decisions I can only frown upon. With some very stupid and unreliable ones replaced in newer revisions with something different but still flawed but in different way. For example the worst buck converter PCB layout I've ever seen. Strange that it works at all, I guess by lucky coincidence.