MC68360 - BR and OR registers - Page 1
Forum section: electronics / general

author: TomS_
author_rank: Frequent Contributor
timestamp: February 22, 2021, 08:02:54 am
content: Hi all.Is anyone familiar with the MC68360? Specifically the BR and OR registers and how the address masking works?Along with doing some reverse engineering of a Cisco 2500 series router (68030), I'm also trying my hand at a 1600R which has the 68360 in it while I wait for some PCBs to arrive which will let me test out an idea on the 2500.I believe I understand what it is doing in principal, but I just can't seem to wrap my head around how it is doing it - i.e. the sequence of operations to go from an address presented on the address bus, combined somehow with the BR and OR to assert the corresponding chip select to address the required memory.I *think* that a 0 bit in the address mask acts like a "don't care", but it's one of those situations where the explanation the datasheet gives is just not clicking with me and I think I need to see it explained in a different way.Thanks!

author: trukresom
author_rank: Contributor
timestamp: February 22, 2021, 01:28:58 pm
content: Hello TomS_Back in 1995 I co-worked on a project using the MC68360. I was involvedwith the programming of a board support package to run pSOS.Talking about the BR and OR registers it is probably best explainedwith an example. In our project we connected among others a custom interfacefor an IDE-harddisk on CS5. We reserved a window of 2 kBytes within thememory map for this interface at a base address of 0x400000 with a portsize width of 16 bits. Note, that the databits used were NOT D0...D15 aswe could expect but D16..D31 !Below are the definitions of the values written to OR5 & BR5 respectively:#define CS5_BR_VAL (CS5_BASE_ADR+VALID+CSNTQ)#define CS5_OR_VAL (WAIT_9_STATE+SIZE_2KB+WIDTH_16_BITS)with the actual values below:#define CS5_BASE_ADR 0x400000#define VALID 0x00000001#define CSNTQ 0x000008#define SIZE_2KB 0x0FFFF800#define WAIT_9_STATE 0xA0000000#define WIDTH_16_BITS 0x00000002Hope that this helps.

author: TomS_
author_rank: Frequent Contributor
timestamp: February 22, 2021, 06:31:35 pm
content: Thanks trukresom.This helps a lot, seeing another example, and I think I might have it now.The AM field in the OR register only covers A27..A11 or some such, and I can see that the mask you have supplied, if inverted, gives a value of 0x7FF, which is 2048 possible address locations.So I think that my thinking that 0 bits in the mask are the "dont cares" might not be so far off the mark.In my case, I am looking at the following equivalent values in one case (BR0/OR0):move.l #0x04000003, 0x0FF01050 /* BR0 */move.l #0x5BC00002, 0x0FF01054 /* OR0 */so that makes a base address of 0x04000000 and a mask of 0x0BC00000 (4MB). The thing that was throwing me off is that the mask in binary is 0b0000 1011 1100 0000 0000 0000 0000 0000, and in particular the 1011 nibble. Based on this understanding, this suggests that this chip select will assert on address 0x04xxxxxx and 0x00xxxxxx (roughly speaking) since it basically seems to be ignoring the 4's bit position? This does seem to be the case, because I can see the same memory contents (in this case, boot ROMs) when dumping memory from both address 0 and address 0x04000000.Slightly odd arrangement I suppose. The initial PC points to a location somewhere in the 0x04xxxxxx's, but I guess they never decided to close it up for what ever reason. I saw in the Cisco 2500 that they write a "JMP zero_jump_handler" kind of thing to address 0, perhaps to help catch bad/uninitialised pointers or something. But in that device, address 0 is mapped to RAM, and in this case it is mapped to ROM so they couldnt do that...Anyway, it would seem that the "logical equation" to determine if CS is asserted would be:(PC & AM) == (base_address & AM)And yep, from what I could see, the dynamic bus sizing means that most things end up being connected to the higher numbered data lines rather than the lower ones.Thanks again!

author: trukresom
author_rank: Contributor
timestamp: February 23, 2021, 08:10:12 am
content: Hello TomS_Just to be sure that you have a copy of the User Manual of the MC68360If not, you can download it here :https://www.nxp.com/docs/en/reference-manual/MC68360UM.pdfYou can find a description of the BR & OR in6.13.3 Base Register (BR) on page 6-70 and6.13.4 Option Register (OR) on page 6-72I think you understood the behaviour of the AM bits very well.The possibility to make a memory bank visible from more thanone address range is explicitely mentioned in the paragraphfor the AM bits on page 6-76.

author: TomS_
author_rank: Frequent Contributor
timestamp: February 23, 2021, 06:38:03 pm
content: Yep, Ive got that document, and have 4 copies of it open at once to be able to reference different parts of it quickly.I dont usually have trouble understanding datasheets, but this one just had me stumped a bit. Maybe Ive just missed it, but if they had an example like yours then I might have been right.