Sum open collector signals to an analog signal, equal spacing over full V range - Page 1
Forum section: electronics / beginners

author: Infraviolet
author_rank: Super Contributor
timestamp: March 02, 2024, 03:02:18 am
content: I've been looking at summing 3 digital open collector signals to make an analogue level output:https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCCsB0AM8MYsBTAtAdhAZmgTjACYiAObPPEsSbY7KWKBqdMMAKABdwxsA2cH0ZF4gxsJBoALPgpy8fDNnJ8wJKHHkVFsAlPLo84UQBMUAMwCGAVwA2nLj34hCU4YVGvx4STK3a2fmxqDV0tIRJI3j5DY0YzKzsHbkCBZQERRnSQCWlZLUheSMIMCBgw+UKwN11XWLBTCxt7dgBzcA9hDAziDO6cnLaOz0gesAFCUYHYIcycSEIO8fnF8XYAJycMoWNIsQGG+A2tlzdd9S8DhGPUnGcGvezha4Blc-3D9XHvRitbAGcUANCOw3g8LmdPqcfiA-oDgaD3tkoU8BnCgYwQe0oWB+hRFriBGtsfALlN8S4psS4upsAsQBS6atBgAlGngKRSBn9apc7xnSDTHLQSDsNlQwiubkTKX8xiCn4isXs2iMRkeIUCoWwJUAd2Gwk54GCBKNM31c0lXN4RBcsvYFs6OA1NsWqtZxttCg6JDVRIGWsVovFJvAPMI3sJmvl2qVIdtJQJEYmGGZjED0yVm1dHOtnMNfLiM2zoatucxspc1xLtvdvKyGvT1wt+edBYrfId5btechZvY-C+rbL1FgXLLa2zrd53b4hcOM3FrbnHL2K7lTCDN1DkdDM+e1c9BJ5pcrC+LR5cqcv7oPR0HBtzPBI1ttawflqlbD4F1g6nfP6PnWajjnsaxAAshows the principleBut I'm finding it seems impossible to get the output levels all equally spaced across the full voltage range.I wrote a script in R to try to optimise the values of the 3 series resistors (1K,2K and 4K here) and the 1K pullup, neglecting the 10K extra pullups*, but when it calculated the output levels possible by trying all reasonable (1K to 100K E12 series) values for the 4 resistors it couldn't find a combination better than the one shown.*those are present because some of the open collector units I want to add in practice are on module boards where a 10K pullup is already includedBy BETTTER I mean having the largest possible distance between whichever analogue output levels are closest to each other.The script finds the parallel combinations of the resistors for different states:Rparasum=infRparasum=1 / ( (1/RC) )Rparasum=1 / ( (1/RB) )Rparasum=1 / ( (1/RB) + (1/RC) )Rparasum=1 / ( (1/RA) )Rparasum=1 / ( (1/RA) + (1/RC) )Rparasum=1 / ( (1/RA) + (1/RB) )Rparasum=1 / ( (1/RA) + (1/RB) + (1/RC) )Calculates the output voltage for each given the value used as the main pullup:Vout[ i ]=Vin*(Rparasum[ i ])/( RPUL + Rparasum[ i ])and then the script looks at the differences between voltage levels for neighbouring states.It rejects cases where neighbouring states go in the "wrong order", anything where a higher numbered state would be pulling down to a lesser extent than the state before it.After testing all RA, RB, RC and RPUL values it reports the best combination found, the one where the lowest voltage difference between any pair of states is higher than the lowest voltage diference found for any other RA,RB,RC,RPUL combination.1K,2K,4K and 1K (test example, not in the E series script) gives only 0.24V difference between the output level for the "5" state (1K active and pulled low, 2K inactive and floating, 4K active and puleld low) and the "6" state (1K active and pulled low, 2K active and pulled low, 4K inactive and floating).The script found: 8.2K, 15K, 27K and 8.2K. Where the difference between levels "3" and "4" was the lowest difference between any pair of levels, coming in at 0.202V.So I tried summing open collectors this way instead:https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCCsB0AM8MYsBTAtAdhAZmgTjACYiAObPPEsSbY7KWKBqdMMAKABdwxsA2cH0ZF4gxsJCxofWhlgAWbPIWESfPJOl9CfZRn5g+JWIUL0wogCYoAZgEMArgBtOXHvxCFl4QqK-jwTRlVEkVIMApDYg0pPkgMeQw8BUh5eTw4vHlwK1tHFzc2D2wPEUYSgQlY2jwMI1NCDBJiLFjUtMTa1X0FAQtGa3tnVwBzH1EwOp9DcCnxdjGyz0g+4gFCFclJBfHyyEJpgWx9rdh2ACd3PqEckhIxLf6zy6L17ws7z29hBAurnFKsE+FUevwAyrd7oYfkCHhJ7E4AM4oLaEdgQj73fw5WHY+F2JEoxhojFA+4g-rkjz4wmonaU2YCCgHSaVbaLeBYzbM5Zss4c2HHA48oWndgAJRxULSIFqfRlAW8kFOmkgEqlni8sqmpmyisYyoCUjVkoZtEYIt8KqVKuN7AA7rtwDLeERnXqHU7deBsG7vWdHUtzT63cGzqbfcLVsZZXyQDajdATSGWVMiBlGdaDbak+rXQdGizCBnC1mmIm1S9I+73cIFTjninNdkwGliVrib8q6Gra3vGH479A22cL2R-7PX32y2R33tvxpd5vdQFM2xd2o025zDG-nM3v-Z4u03S3uB8p4OwF0652xQjwDvNr0tl4YsbCn0YncG79kQmKgANow the smallest difference with 1K, 2K, 4K and 1K is 0.39 volts, between the "6" (1K active pulling down, 2K active pulling down, 4K inactive) and "7" states (all active and pulling down).But I can't seem to find a method to add the states of 3 inputs so the 8 possible states are all equally separated across the whole 5V. There should surely be a way to sum open collector inputs so all output states are 0.625V apart (0V, 0.625V, 1.25V,...4.375V, 5V), preferably whilst tolerating all of them already having a 10K pullup present already before entering the summing circuit.Is there some other topology for a circuit to sum these sort of open collector inputs, so they do all end up evenly distributed across the full voltage range?Thanks

author: ArdWar
author_rank: Frequent Contributor
timestamp: March 02, 2024, 03:08:36 am
content: How good are your open collector output sinking? Anyway just use R2R topology, no need for increasingly weird resistor values.

author: Infraviolet
author_rank: Super Contributor
timestamp: March 02, 2024, 04:07:41 am
content: R-2R DAC style? Thanks, hadn't thought to search for DAC topologies for this, looks like it might be a viable way.EDIT: I'm not sure if the R-"R ladder can work for me. None of my open collector inputs can output a low impedance HIGH, each either pulls down, or lets a pullup take the line up to 5V. R-2R seems to need every input to be able to drive high and drive low?

author: Ian.M
author_rank: Super Contributor
timestamp: March 02, 2024, 05:08:36 am
content: Try this:https://preview.tinyurl.com/2yyetst20 to 4.15V range in fairly even steps.At the cost of some extra complexity, adding diodes to prevent the pullups if present shunting the current mirror could further improve linearity. I doubt you can do any better without either an OPAMP or CMOS buffering all the inputs so you can build a true R-2R DAC.

author: BillyO
author_rank: Super Contributor
timestamp: March 02, 2024, 09:28:23 pm
content: You can bang you head against this or you can use CMOS outputs and an R-2R ladder. Yes R-2R requires a push-pull drive.

author: Infraviolet
author_rank: Super Contributor
timestamp: March 02, 2024, 09:43:19 pm
content: Ian M, that looks an excellent solution. ThanksI'll try with that for the real circuit and resort to buffering each open collector with CMOS gates to convert them to push-pull signals if the current mirror method doesn't prove effective enough.