Is there anything between implementing logic with FPGAs and with discrete ICs? - Page 1
Forum section: electronics / beginners

author: zigunov
author_rank: Contributor
timestamp: February 21, 2021, 02:58:03 pm
content: Hi!I have a small digital logic circuit I want to implement with discrete logic chips (it's like a programmable trigger generator but I couldn't quite find the exact implementation I wanted on a single IC). I was able to build it with 1 counter, 2 AND ports, 2 NOT ports and 2 D flip flops (plus a clock). If you're interested in the specific implementation, here's a link from circuitverse:https://circuitverse.org/users/68239/projects/led-trigger-testI could use an FPGA to implement this logic, or I could just use discrete logic IC's. It feels to me an FPGA is an overkill for such a simple circuit, but discrete IC's will take a lot of real estate in my PCB. Maybe there's another solution that I'm not seeing that is some sort of compromise between the two??Thanks for your help!!

author: coppice
author_rank: Super Contributor
timestamp: February 21, 2021, 03:01:10 pm
content: Quote from: zigunov on February 21, 2021, 02:58:03 pmYeah, why use one part when a small board full will do.

author: zigunov
author_rank: Contributor
timestamp: February 21, 2021, 03:04:05 pm
content: I mean, I'm not very good at FPGA programming and design, so it's an overkill to me. I know it can be implemented, but going about actually implementing it will be kind of a big project to me!!

author: wraper
author_rank: Unknown
timestamp: February 21, 2021, 03:15:25 pm
content: As minimum you don't need NOT gates at all since D-Type Flip-Flop usually have inverting and non-inverting outputs. Likely other optimizations can be done to reduce IC count.

author: zigunov
author_rank: Contributor
timestamp: February 21, 2021, 03:58:55 pm
content: wraper, thanks for the idea, that's actually a good point!!

author: rstofer
author_rank: Super Contributor
timestamp: February 21, 2021, 04:00:00 pm
content: One solution is to use a CPLD. You might even find a 5V version. Here's a thread on the topic:https://www.eevblog.com/forum/fpga/5v-cpld/msg3429798/#msg3429798You can also implement all of the logic except the D flops with a simple EPROM or EEPROM.Do a search for 'CPLD' atwww.jameco.com.Make sure you can obtain the programming tools.

author: rstofer
author_rank: Super Contributor
timestamp: February 21, 2021, 04:00:34 pm
content: Quote from: zigunov on February 21, 2021, 03:58:55 pmPost a schematic and let people help minimize it.

author: zigunov
author_rank: Contributor
timestamp: February 21, 2021, 04:54:46 pm
content: rstofer, I didn't know about CPLD's. I'll have a look. To whom might be interested, here's the circuit attached.It generates a pulse of programmable width (by the counter) every rising edge of the input.I'll use a 16-bit counter, in practice.Thanks for the ideas!!

author: Benta
author_rank: Super Contributor
timestamp: February 21, 2021, 05:01:35 pm
content: Microchip still offers 16V8 and 22V10 PALs; electrically erasable, too. Should be enough for this job.

author: wraper
author_rank: Unknown
timestamp: February 21, 2021, 05:48:07 pm
content: Also depending on how fast this circuit needs to be, the simplest and cheapest option might be just using some cheap MCU.

author: pwlps
author_rank: Frequent Contributor
timestamp: February 21, 2021, 05:51:19 pm
content: The classic GAL16V8 should be enough for a 3-4 bit counter+a D flip flop.https://eu.mouser.com/ProductDetail/Microchip-Technology-Atmel/ATF16V8B-15PU?qs=2mdvTlUeTfCsdBIzx6v3gA==&vip=1&gclid=Cj0KCQiApsiBBhCKARIsAN8o_4hN0YBmYkfDompQMRHPPsr7A9U_mZVPrZD2Ek6wqq9GRzrOrSojFMQaAorFEALw_wcBhttps://estebon.mx/?cat=21He is synthesizing logic by hand in CUPL and this is a pain. Back in the days when Verilog weren't popular yet we were doing it with ABEL (liked it very much) but I don't know the actual tools used for these chips.

author: rstofer
author_rank: Super Contributor
timestamp: February 21, 2021, 06:04:48 pm
content: If you go down the GAL/PAL path, make sure you can find a DIY device programmer for the specific chip you are using. Commercial programmers are EXPENSIVE!

author: ataradov
author_rank: Super Contributor
timestamp: February 21, 2021, 07:31:33 pm
content: But be careful with old parts. The design software is often either complete junk or does not run at all on modern OSes. Be prepared to make a WinXP virtual machine, I'm not kidding.But I personally would just go with small Lattice FPGAs. And while I'm at it, see if there is something else that can be moved into the FPGA.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 21, 2021, 08:38:18 pm
content: What sort of operating frequency do you need?If it's slow, you could do it in software on a small PIC or similar microcontroller, which would probably be the cheapest solution overall. If that won't work, try a CPLD - my personal preferences are Lattice and Altera.

author: jmelson
author_rank: Super Contributor
timestamp: February 21, 2021, 09:39:17 pm
content: There are also CPLDs such as the Xilinx 9500XL family that have much less logic capacity than a full FPGA. There's also Xilinx's Cool Runner II family, but it needs two supply voltages. I use a 9536XL to replace a couple one shots on a board, it only costs $1.Jon

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: February 21, 2021, 09:53:04 pm
content: If you can, do it with an MCUIf this is for production, the Dialog GreenPak devices might be worth a look

author: james_s
author_rank: Super Contributor
timestamp: February 21, 2021, 11:41:35 pm
content: I like CPLDs for simple logic stuff. They're fairly cheap, easy to work with, and unlike most FPGAs they have built in configuration memory. Usually simpler power requirements too.

author: Cerebus
author_rank: Super Contributor
timestamp: February 22, 2021, 12:11:27 am
content: I'll just point out the Mach series of CPLD/FPGAs* from Lattice and also the iCE40 series of FPGAs from Lattice. Both have parts in the range with onboard FLASH for instant startup, the iCE40 range in particular features some small parts, both in terms of 'gate count' and package size (If that's your thing. They are both also available in QFP). They both fit in the niche between discrete logic and large expensive FPGAs. One will cost you the same as a few discrete logic chips, save board area, give you 'on board' programability that fixed logic obviously wouldn't, and probably save a few mA on the way.Also, if it's important to you, there's a completely open source toolchain available for (most of) the iCE40 chips.* The range started out as CPLDs and ended up as fully fledged FPGAs.

author: wizard69
author_rank: Super Contributor
timestamp: February 22, 2021, 01:05:27 am
content: I'm glad to hear that PALs are still in production as they came to mind the very first thing.However it might be easier to program a PIC chip to give you the logical function you want. You would need to consider if you can get the code to function fast enough.Substituting programmable devices for discreet logic can by useful in any number of situations. In the industrial realm I've done so for "card logic" modules that are not available anymore. The reality is programmable devices today are often fast enough do the job.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 22, 2021, 04:38:11 am
content: Yeah, that's about the problem with digital logic -- if you don't want to use an FPGA, even fairly simple (nontrivial) circuits take up a handful of chips!As for optimization, you might be able to swap around a few D flip-flops, or find a registered counter that effectively integrates their function; but I'm not sure you'll be able to save both of them. Or, perhaps one can be replaced with a latch, built from a pair of NOR or NAND gates -- using a quad gate IC might be feasible. Of course you'll need to convert your AND and OR gates to NAND/NOR. Which looks doable.There are some hacks that can be done to optimize further, at some expense to strict performance -- for example, using timers and latches to substitute for D flip-flops. It looks like the counter is only supposed to start upon a trigger rising edge (synchronized to the system clock) -- this can be approximated with a time delay into a gate, so that the output from the gate goes active for a short period, perhaps 100ns, only when the input rises. This is an approximation, because we rarely create ideal time delays: for comparable input pulse widths, the time delay may be less, or may not fire at all. It's also an approximation because, if the input is a cluster of short pulses (as sparking noise can easily produce), maybe a lot of those pulses are let through, rather than only the first edge.Anyway, when this is acceptable, we can use the short pulse to trigger a latch, which can be simply two NAND/NOR in a loop. It acts like a D-type flip-flop for certain inputs (only triggered during rising edge, when the input isn't changing frequently), but uses far fewer transistors.And the time delay might be a simple RC lowpass filter, into a schmitt trigger gate. Simple analog tricks like thatWe can go further with our analog tricks. Suppose we accumulate charge onto some capacitor, and we deliver a constant charge (thus, make a fixed step change in voltage) with one of those short pulses, derived from the system clock. Now we get a staircase waveform, where the capacitor voltage counts up with each clock pulse. Finally, suppose we add a comparator, so when the voltage steps above threshold, a discharge is triggered (which might be a fixed time delay, so the capacitor is guaranteed to be fully discharged -- if we use a hysteresis comparator, the amount it discharges by, will depend on the discharge rate and the input-falling threshold). And we feed that discharge signal into a latch into the LED, so it lights for the, ten or whatever, clock pulses. Add another latch and gate to produce the trigger / gating function, and you're done.This is an even trickier method -- now it depends on all the squishy properties that analog circuits have. If the clock pulse is really slow, the capacitor voltage might leak away between steps, and maybe it loses count, skipping a pulse or taking extras later. I notice trigger can be double-tapped to pause the count, if that's a necessary feature then the logic to handle that must still be present, and if that means pausing an analog count, we need to know how long it may be paused for -- if it can be paused forever, this solution cannot be used: it will always decay, eventually.This is also the domain of dynamic logic, where digital logic operations are performed, as long as it's always in strict sequence and above a minimum rate. When the clock frequency is tightly controlled, this is fine -- older CPUs used this regularly, and probably a lot of current tech does, too. Dynamic logic, as far as I know, tends to avoid intermediate levels, unlike the above stairstep counter -- logic ICs usually have a simplified process that may not support circuits complicated enough to implement these kinds of functions, or their performance just isn't good enough to be worthwhile (more in terms of voltage range, and consistent operation, than in terms of raw speed).So, I don't think I'd recommend trying this for a production circuit or something, but it's a curiosity if nothing else, worth playing with on the breadboard if that's the extent of it. It can still be an effective design method (in production), when the problem happens to evade all the edge cases these methods bring along.Tim

author: tszaboo
author_rank: Super Contributor
timestamp: February 22, 2021, 10:42:14 am
content: As others mentioned, CPLD.There is also something called configurable gate. TI, ON, NXP and big players will have this. It will be an OR, NAND AND or NOT, depending on how you connect it. It might save you from using 8 different parts in our BOM.Ah and dont forget, you can just program a parallel 256 byte EEPROM to do logic functions for you, if you connect 8 digital lines to the address line.

author: gnuarm
author_rank: Super Contributor
timestamp: February 22, 2021, 12:41:32 pm
content: There is a line of MCUs with programmable logic which might do what you want. Cypress PSOC. I haven't looked at them in a while. The oldest chips use a proprietary 8 bit CPU with programmable logic and analog, very inexpensive. Newer parts have various ARM CPUs and different types and amounts of logic.Just a thought.

author: larsdenmark
author_rank: Regular Contributor
timestamp: February 22, 2021, 01:47:54 pm
content: Bil Herd has made a series of videos about CPLDs. E.g.:https://hackaday.com/2015/10/28/programmable-logic-build-yourself-a-cpld-module/

author: DC1MC
author_rank: Super Contributor
timestamp: February 22, 2021, 06:37:44 pm
content: A honorable mention for GreenPak if the design fits in the tiny logic block:https://www.dialog-semiconductor.com/greenpak

author: Cerebus
author_rank: Super Contributor
timestamp: February 22, 2021, 07:02:14 pm
content: Good call, this is exactly GreenPak territory as far as I understand the product line.

author: zigunov
author_rank: Contributor
timestamp: February 22, 2021, 07:28:59 pm
content: WOW that's a lot of answers!! Thanks for everyone for your contributions - hopefully others will also benefit in the future. I think I won't escape from having to use either a CPLD or a FPGA, as it looks like. I'm sure it'll be a fun skill to build, though!As for the questions about the timing, it would be great to have ~50ns jitter in the trigger, so it's definitely in the "not-so-simple" territory and a uC is really out of consideration. I appreciate everyone's ideas!

author: gnuarm
author_rank: Super Contributor
timestamp: February 22, 2021, 08:56:23 pm
content: Quote from: zigunov on February 22, 2021, 07:28:59 pmYou mean no more than 50 ns? That can be done in an MCU. Or do you want to introduce jitter for some reason?

author: zigunov
author_rank: Contributor
timestamp: February 23, 2021, 07:44:36 pm
content: Hi, gnuarm, I said "jitter" because I don't know when the pulse will come, and the clock updates the circuit at a constant rate. So, this "unpredictable delay" between the rising edge coming and the circuit updating at the next clock tick is what I'm calling "jitter". I would like this to be about 50ns; i.e., the clock (update rate) to be of the order of 20 MHz. Sorry if it wasn't clear.About the MCU, I see your point. If the MCU is there solely for that task, it should be able to implement that logic. I haven't thought about the optimal program but maybe it's possible to do it in 4 instructions. If so, I would need a 320MHz clock (assuming 4 cycles/instruction; 20MHz*4 instructions * 4 clock cycles/instruction).Might be feasible; let me have a crack at it. I think if it is not possible to fit the program in 4 instructions or less then it might not be possible to use a MCU for this one. But now I see it is definitely an option for the general case; with lower update rates.

author: Terry Bites
author_rank: Super Contributor
timestamp: February 23, 2021, 10:48:35 pm
content: 10/10 great answer. Quicker and cheaper than programing a PGA. PGA is one time, oops... PGAs and programming tools that will be gone soon, stay away unless you are up into the thousands of units!

author: wraper
author_rank: Unknown
timestamp: February 24, 2021, 12:41:33 am
content: Quote from: zigunov on February 23, 2021, 07:44:36 pmYou should not forget there are hardware things in MCU. Like timers/counters which often can work from external source and output directly to IO. Probably all you need to do by CPU is configuring hardware so it can then do the job by itself. As I understand what you want to do is just generating pulse of set length on external trigger.

author: gnuarm
author_rank: Super Contributor
timestamp: February 24, 2021, 05:29:22 am
content: Quote from: Terry Bites on February 23, 2021, 10:48:35 pmWhat is a PGA? To me a PGA is a programmable gain amplifier. Also, who are you replying to???

author: Cerebus
author_rank: Super Contributor
timestamp: February 24, 2021, 02:56:37 pm
content: Quote from: gnuarm on February 24, 2021, 05:29:22 amProgrammable Gate Array? As in Field Programmable Gate Array? If so, some misconceptions there. One-time programability is the exception, not the rule, for FPGAs. Or perhaps the poster is using Programmable Gate Array as a generic for PALs, GALs and CPLDs?