Fractional-N frequency synthesis does not work on Mach XO2 FPGA - Page 1
Forum section: electronics / general

author: bsccara
author_rank: Contributor
timestamp: June 16, 2019, 09:27:05 am
content: I'm using the Right side PLL to implement a clock generator on a Mach XO2 7000 FPGA that takes in a 50 MHz clock generated by the Left side PLL and outputs a clock that can be changed from 50 MHz to close to 100 MHz by means of the Fractional-N functionality of the Right Side PLL. I'm aware that this is not a great solution in terms of jitter, but that's a tradeoff I'm willing to take.For that purpose I've used IPExpress to configure the PLL with these settings:QuoteThese settings should configure the PLL to generate a 75 MHz clock signal on the CLKOP output. But instead the PLL locks to the 50 MHz input signal, disregarding the Fractional-N settings. The Right side PLL is kept in a reset state until the Left side one locks. I'm also using a Wishbone interface to both PLLs and use it to configure the same settings onto the PLL and reset it afterwards but signal capture shows the PLL losing lock after the reset command is sent, with the CLKOP output low for ~20uS and then a frequency increase on the CLKOP output from around 10 Mhz to 50 Mhz, at which time the LOCK signal is set again.I can't find any examples of Fractional-N synthesis on this FPGA nor do I understand why it disregards the settings, as the IPExpress wizard shows the CLKOP frequency at 75 Mhz. Any thoughs on what might be the issue ?

author: TimCambridge
author_rank: Regular Contributor
timestamp: June 18, 2019, 09:16:28 pm
content: A Lattice FAE can help with your exact problem. Meanwhile this VHDL example might be useful. It runs the PLL at 500 MHz from a 24MHz input clock. CLKOS is 250MHz (i.e. 500/2) which is then divided down by 10 in the feedback path. The fractional divider, also in the feedback path, drops 25MHz to 24MHz so that the loop locks.Code:-- 25/24 = 1.041666 = 1 + 0.041666 = 1 + 2731/65536FRACN_DIV => 10 * 2731, -- 25MHz down to 24MHzFRACN_ENABLE => "ENABLED",CLKOS_DIV => 2, -- 500MHz PLL -> 250CLKI_DIV => 1,CLKFB_DIV => 10, -- 250MHz from DivB/ClkOS -> 25FEEDBK_PATH => "INT_DIVB",This only makes sense in conjunction with the PLL diagram in the Lattice TR, and even then it isn't super-clear.

author: bsccara
author_rank: Contributor
timestamp: June 20, 2019, 11:00:48 am
content: Tim, thank you for your example. I've opened a ticket on the Lattice website with this question beforehand, but got no reply so far. Further testing seems to indicate that the source of the problem is the FBK divider being set to 1. Simply changing that to 2 makes the PLL lock onto a frequency that takes into account the fractional settings.Meanwhile I've looked into the design again and decided to change it to a single PLL, using multiple ranges driven by the CLKOS divider to cover the 50-100MHz range that I need. This design allow for finer control at the expense of uneven stepping across ranges.I'm now hoping that the Mach XO2 DS is wrong on the jitter numbers, as I can't understand the jump in jitter at output frequencies below 100 MHz when using Fractional-N; going from 0.007 UIPP to 0.12 UIPP while at frequencies above 100 MHz the jump is from 150 ps to 230 ps makes no sense to me.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 20, 2019, 11:56:06 am
content: Your problem probably comes from the phase detector's input clock frequency not being in the specified range (7MHz to 400MHz).(See: p. 3-31 of the datasheet and note TN1199.)

author: bsccara
author_rank: Contributor
timestamp: June 21, 2019, 09:43:29 am
content: Don't think so; the Left side PLL is driven with a 12 MHz clock and the Right side one with the aforementioned 50 MHz. Both PLLs have their CLKI dividers set to 1.

author: TimCambridge
author_rank: Regular Contributor
timestamp: June 24, 2019, 10:33:50 am
content: Quote from: bsccara on June 20, 2019, 11:00:48 amThat's pretty much what I did when I built a 1GHz logic analyzer in an XO2. I used the wishbone interface to control the PLL and was a little surprised when it all worked OK. As you might expect I ended up doing a fair amount of tedious hand routing in the XO2; that's a capability that has been reduced in current versions of Lattice Diamond - keep a copy of Diamond 2.x on your machine.Also the PLL has more capability than is documented. The details are a fading memory but you can rely on the PLL being logical rather than absolutely as documented. For instance there is no logical reason why you cannot cascade all the dividers and indeed you can and they work just fine.