Slew rate, settling time and other OPAMP parameters - Page 1
Forum section: electronics / beginners

author: Bel16ario
author_rank: Newbie
timestamp: October 26, 2023, 05:14:08 am
content: Good day to everyone, I apologize for poor english. I am a university student and I am trying to design an analog signal treatment board to interface with an ADC for my semester project for one of my classes. The board is supposed to have a pre-amp, a selectable attenuator (I am using a rotary switch with different tee attenuator values) and a low pass filter all cascaded together. I am trying to select the proper OPAMP for the pre-amp, and using the SRS760 manual as a reference. I can see that they use a FET opamp with 3.5 nv*sqrt(Hz) input noise, but I cannot find much more information. I have looked at TI's catalog and identified three options, the OPA828, the OPA838 and the OPA847. On the OPA828 datasheet, it mentions that it's settling time is well suited for data adquisition of up to 18 bits due to its settling time. My ADC is 24 bits (ADC127L11) so I do not know if this will be insufficient. Both the OPA838 and OPA848 have higher slew rates and lower settling times, which leads me to believe that they might help me get closer to 24 bit accuracy, however, I am not sure if this is the right aproach, specially since the OP838 datasheet mentions only 12-14 bit capability. The other parameters which I am looking at is input voltage offset and input voltage noise. I will only be working with low frequencies of up to around 100kHz (but 150 kHz is the -90dB frequency on my anti alias filter). I hope you can give me some guidance with selecting the best OPAMP for the job.

author: jonpaul
author_rank: Super Contributor
timestamp: October 26, 2023, 07:51:44 am
content: Hello: Bravo for the project: 100 kHz is NOT low for a 24 bit ADC.Study the ADI spec sheet and app noteshttps://www.ti.com/lit/ds/symlink/ads127l11.pdfNO LPF needed as Delta-Sigma ADC have BUILT IN digital LPF.At 24 bits your problems will be not slew but noise and THD.Beware that design and debug of a 24 bit ADC system speced at 115 dB SNR/DYN (theory much more) requires specialized techniques and very expensive test equipment.https://3roam.com/adc-snr-calculator/See ADC papers and info on ENOB and "marketing bits"https://en.wikipedia.org/wiki/Effective_number_of_bitsBON CHANCEJon

author: Terry Bites
author_rank: Super Contributor
timestamp: October 26, 2023, 08:28:50 am
content: I think the attached my help you get to grips with the opamp parameters and their effects on your signal path performance.Firstly decide on the number of bits you really need. The quoted 24bits refer to the DC precision not the AC resolution.That may or may not matter in your application. You can calculate the effective number of bits required (ENOB) from the SNR you wan to achieve.ENOB = (SNR – 1.76)/6.02 dB. Are you trying to emulate the FFT analyser?Slew rate = 2 π f Vpp. So for a 1Vpp signal @ 100kHz you need at least 0.628V/uS. Thats not a big ask even from a DC precision amp. For a lab project, opamp cost is not a big deciding factor, you're not making millions of units, so you can over specify. Consider using a dedicated ADC driver, eg THS4551.https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/896538/ths4551-bw-of-butterworth-filterAs a rule of thumb, for a lowpass filter you want an opamp with a GBW 10x your filter bandwidth.en doesn’t tell the whole story, in flowing in the attenuator output impedance creates an additional noise voltage. You can think of the opamp and having an input noise resistance, Rn=en/in. For the best noise performance Rn needs to match Zsource (give or take). Note that the opamp has to be able to drive the ADC input properly. It must also be configured to prevent the opamp output exceeding the ADC input range. If not the ADC can be damaged.Read up on opamp parameters and "error budgets" in your H&H.www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwi2m72AnZOCAxUxVUEAHaJ0CMYQFnoECA0QAQ&url=https%3A%2F%2Feclass.uniwa.gr%2Fmodules%2Fdocument%2Findex.php%3Fcourse%3DEEE265%26download%3D%2F6218412aGLbn%2F5e6db8cd5KNP.pdf&usg=AOvVaw2plc0PuOn_OWln4yGUYbMM&opi=89978449

author: Bel16ario
author_rank: Newbie
timestamp: October 27, 2023, 06:18:53 am
content: Merci, Jon. I have read the datasheet for the ADC and even in the typical implementation it has a low pass filter for anti alias. This is what I meant when I said that it had to have a filter. Going by the SRS760 manual, it seems like I should have -96dB at approximately 200kHz. With respect to ENOB and noise/THD, I have read on the subject today and talked to my teacher about it. I think that I will "sacrifice" some of the ADC bits in order to facilitate or improve other areas of the design, and I will target the ADC outputting 24 bit data that is only accurate to 18 bits. If I did not understand incorrectly, that is what is implied in the application note that Terry Bites provided below.Thank you very much Terry. I found the application note that you provided extremely insightful, I even read it over with a teacher to understand the provided example (that I found to be a little unrelated to the rest of the document). I arrived at the end, after filtering the op amps using the methodology described in the document, with the same opamp that you suggested and that is on the implementation on the ADC datasheet, the THS4551. As for impedance matching, I was planning to compensate the ADC series resistance and parasitic capacitance using this method:.As for the FFT analyzer, it is the equipment I have at my lab, and I found that the manual is very insightful at describing a typical analog signal chain. Obviously reproducing all those relay-set gain stages is impractical for the scope of my project and the level of my habilities, but it is a nice reference. My plan is to have the input amplifier have a fixed 20dB gain and have the attenuators be selected manually like in the attatched picture. I plan on changing the values for the attenuators so that they have values from 0 to 40dB in 4 dB increments which will hopefully net me a -20dB to 20dB gain/attenuation from the input to the ADC.As for The Art of Electronics, I actually own a physical copy of the third edition, it has helped with a bunch of different classes, but with the advent of the internet and stuff like that, it is often easy to forget that actual books exist.I have one more question, however. On the application note you provided, (SLOA035D), it mentions at the beginning that it is possible for a single opamp to perform the amplification and the filtering. I am reading the MFB design application note, ¿Is it just setting the pass band gain to my desired 20dB in the equations provided?. Also, I assume that I do not need to impedance match to the input of the ADC but I do need to match to the signal source... ¿Am I correct?Cheers, Luca

author: Kleinstein
author_rank: Super Contributor
timestamp: October 27, 2023, 12:01:39 pm
content: For an ADC with such high resolution and dynamic range there is little need to adjust the gain in very fine steps. There are usually 1 or 2 spare bits anyway. A fine adjustable gain is something for a low resolution (e.g. 8 bit) system. So Gain/attenuation steps of some 20 dB, should likely be enough. Usually DMMs use 1:10 range steps (20 dB), while a scope with a mire limited resolution is more 1:3:10 or 1:2:5:10 ranges and thus 10 or around 6 dB steps.I think the input may want a bit more care with the protection.The ADCs usually want a rather low impedance drive and thus no impedance matching. For the input it depends and both cases can make sense: either a rather high impedance, similar to the 1 M scope inputs or impedance matching to the cables (e.g. 50 ohm). Impedance matching helps with the high frequencies, if the cable lenght is no longer much (e.g. > 50 x) shorter than the wavelength, but it can limit the overall low frequency accuracy. For 100-500 kHz I would normally prefer high impedance. 50 Ohm matching is a thing for > 20 MHz mainly.