PMOS Gate Drive in Typical Application Circuit - Page 1
Forum section: electronics / beginners

author: Freshman
author_rank: Regular Contributor
timestamp: March 18, 2025, 05:18:54 am
content: In the datasheet of this [charger IC], on the Typical Application circuit figure there's this PMOS () connected to pin 8.The gate-source threshold voltage (V_GS(th), max) of this transistor is -1V. I would like to understand how pin 8 is driving this MOSFET.In my design, I am using a similar application circuit with the MCP73842 device, operating at an input voltage of 12V. The MOSFET I am using is the , which has a maximum gate-source threshold voltage of -2.5V. However, when measuring pin 8, I observe that it is only driving 2V between the gate and source.Could you provide insight into why this behavior occurs? Is there a design consideration in the IC that limits the gate drive voltage?:https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/21823D.pdf:https://rocelec.widen.net/view/pdf/390aq0tg47/ONSM-S-A0003584530-1.pdf?t.download=true&u=5oefqw:https://www.vishay.com/docs/63262/sis413dn.pdf

author: Konkedout
author_rank: Frequent Contributor
timestamp: March 18, 2025, 05:37:24 am
content: Understand that -2.5 is a MAXIMUM Vgs threshold voltage. True...the current at that point is only 250 uA. But the Vgs threshold (magnitude) of your sample FET may be lower.Assuming that there is not some other problem...is your battery fully charged? If you load your charger circuit with......maybe a 10 ohm resistor instead of a battery, how much current flows through the resistor? Does Vgs magnitude increase if you do that?

author: ahsrabrifat
author_rank: Regular Contributor
timestamp: March 18, 2025, 05:54:30 am
content: The MCP73842 charger IC uses an external PMOS transistor for input power path control, and pin 8 (PROG2) is responsible for driving the PMOS gate. The MCP73842’s PROG2 pin likely has an internal pull-down limitation that prevents it from pulling the PMOS gate low enough for transistors with a higher V_GS(th) like the SIS413DN. Switch to a lower-threshold PMOS (like the NDS8434) or try an external pull-down resistor to improve drive voltage.

author: Freshman
author_rank: Regular Contributor
timestamp: March 18, 2025, 06:24:06 am
content: How you deduced that DRV (pin 8 ) might have an internal pull-down limitation? Couldn't find in the datasheet or from the Figure on page 2. How does adding an external pull-down resistor improve the drive voltage? Can you shed some light on how does pin 8 work from internally to have better understanding?

author: Zero999
author_rank: Super Contributor
timestamp: March 18, 2025, 08:51:10 am
content: Quote from: Freshman on March 18, 2025, 05:18:54 amWhat voltage are you expecting to see and why?Is the charging current and cell voltage correct?

author: mtwieg
author_rank: Frequent Contributor
timestamp: March 18, 2025, 12:09:40 pm
content: Quote from: Freshman on March 18, 2025, 06:24:06 amThe DC characteristics table mentions a Gate-Source clamp voltage between -7V to -4.5V, so maybe that's what they're referring to.Section 6.1.1.2 describes the worst case gate drive conditions in more detail.Anyways, I agree with other above that the exact Vgs you observe isn't really relevant, so long as the charge controller is properly regulating the charge voltage and/or current as expected. Do you think it's not working somehow?