Crystal oscillator circuit for Sony image sensor - Page 1
Forum section: electronics / beginners

author: bmxsesh
author_rank: Regular Contributor
timestamp: December 19, 2024, 08:25:29 pm
content: Hello,I am trying to build a circuit for Sony CXD3611R which seems to be a must have in order to be able to drive one of their CCD image sensors (ICX415AQ)The datasheet seems to have a lot of missing information as for me, but regardless I am trying to understand what this circuit meansFirst, what could be a possible CKI capacitor value? 0.1 pF is my wild guessSecond, why would it divide the frequency by two? I picked a crystal SJK 7U29500E20UCG and the datasheet attachedSupposedly it takes a crystal oscillation for its PLL and should produce a 29.5MHz square clock on the MCKO pin for the image processor? But then why "1/2" which I assume is divide by two?-bmxsesh

author: lunar
author_rank: Contributor
timestamp: December 30, 2024, 03:24:27 am
content: Quote from: bmxsesh on December 19, 2024, 08:25:29 pmConvert the crystal in the circuit into an equivalent resistance/inductance/capacitance electrical model and you can estimate what the impact a given capacitance will have on the circuit. It might help to have a VNA of some sort (maybe a nanoVNA will work). See:

author: jwet
author_rank: Frequent Contributor
timestamp: December 30, 2024, 03:48:07 pm
content: Quote from: bmxsesh on December 19, 2024, 08:25:29 pm1 Coupling CKI is a coupling cap to couple the oscillator signal out to further stages. I think they loop this out in case you want to add some circuits like dividers, etc or apply an external clock. The cap should be a reasonable value to couple 29.5 MHz to the following amp at CKI. I would think you'd want a reactance that could drive a little- 100 pF would be 53 ohms probably too much, perhaps 22 pF would be comfortable. The amplitude at the CKI is specified as about .5v sine in the DS.2/3 I don't think its dividing by two and that's not what these blocks mean. I think it CAN divide by two but those 1/2 blocks are not just dividers, they are a divider with a data selector that let's either the input flow through or a divided by two signal flow through. I noted that the clock path can go up to 50M, so when using a 50M xtal, you can divide by two. I didn't see explicitly in the register table where this is set. See if Sony has an applications guide for this stuff. These docs are pretty thin. Often the really good docs are in japanese but you can glean a lot "reading" them.

author: bmxsesh
author_rank: Regular Contributor
timestamp: February 09, 2025, 10:51:19 am
content: Huh, I was monitoring for a while but didn't think anyone would answer. Thank you guys for the replies.Quote from: lunar on December 30, 2024, 03:24:27 amMy only problem is that these chips are pricey and always must/should be ordered in a batch, and as soon as I open the ESD package it is only left for me and the PCB fab won't accept it for surface mount. At some point I may be getting one of these but as for now my only tools are an oscilloscope and a power supply, and as much theory and modeling with calculators and emulators such as IBIS is my only option right now.Quote from: jwet on December 30, 2024, 03:48:07 pmSo the CKI will remove the DC bias from the sine wave but also should not attenuate it? Values seem pretty arbitrary anyway, something like an IBIS model would probably help. Unless, as it often turns out, if it's not in the datasheet, then it doesn't really matter, although is obvious to the technical writer of the datasheet