Here is something I built for my own enjoyment. - Page 1
Forum section: electronics / general

author: technix
author_rank: Super Contributor
timestamp: September 20, 2019, 03:04:43 pm
content: XC3S500E + XCF04S at the core. That W25Q128FV is not wired as a boot device, since iMPACT can not write to it, and this FPGA does not support QSPI boot. There is also a PIC12F1840 implementing a combined power/reset button, and an ATtiny841 implementing PS/2 to UART. Both MCU runs at 5V too.Then there is 64MB SDRAM and interface for a 128x64 dot matrix display.

author: laugensalm
author_rank: Regular Contributor
timestamp: September 22, 2019, 01:47:30 pm
content: Quote from: technix on September 20, 2019, 03:04:43 pmYou could use xc3sprog for that. It would have been interesting to see booting from SPI flash and then the logic taking over QSPI support (fast spiffs..)

author: technix
author_rank: Super Contributor
timestamp: September 22, 2019, 01:52:49 pm
content: Quote from: laugensalm on September 22, 2019, 01:47:30 pmSPI boot then QSPI read would be problematic if I need to allow the FPGA be reset using an external signal.

author: legacy
author_rank: Super Contributor
timestamp: September 22, 2019, 03:16:12 pm
content: scheduled project? which dot-matrix display?

author: technix
author_rank: Super Contributor
timestamp: September 22, 2019, 04:03:11 pm
content: Quote from: legacy on September 22, 2019, 03:16:12 pmSchoolwork. I would use one of those ST7920-based "LCM12864M" modules.

author: Ditiris
author_rank: Contributor
timestamp: November 01, 2019, 01:27:59 pm
content: Nice work! Is J4 JTAG, or is the FTDI chip doing that? If the FTDI chip is doing the JTAG, I'd love to talk to you about that. I'm tired of sticking the Xilinx header on my boards and using the programming pods.

author: laugensalm
author_rank: Regular Contributor
timestamp: November 01, 2019, 02:07:45 pm
content: Quote from: Ditiris on November 01, 2019, 01:27:59 pmSee the xc3sprog comment above, programming the chip is way more faster/reliable that way. There are also some advanced forks of it, like papilio-prog (https://github.com/GadgetFactory/Papilio-Loader.git). I'm using this on a similar project as this one, although no SRAM and Spartan6 instead (https://hackaday.io/project/162259-netpp-node) where I tend to build/download everything using oneliners ('make download').

author: technix
author_rank: Super Contributor
timestamp: November 05, 2019, 09:34:35 am
content: Quote from: Ditiris on November 01, 2019, 01:27:59 pmJ4 is not JTAG to the FPGA, it is Microchip ICSP to the PIC12F1840 chip which is acting as a power/reset controller chip.FPGA JTAG is the 10-pin header J1 and the FTDI chip at the same time. The 10-pin header uses 1.27mm ARM Cortex Debug Connector, and it contains a sense line that will disable the logic level shifter U5 when a JTAG pod is connected. Spartan-3E uses 2.5V JTAG but FTDI chip can not go down that low, so a 74AHC4T774 is used as a logic level shifter between the two. Disabling that chip disconnects the FTDI JTAG, allowing the pin header to take over.Quote from: laugensalm on November 01, 2019, 02:07:45 pmI found that someone leaked a copy of the configuration data of Digilent JTAG-SMT1 online. My board is loaded with a modified version of that configuration data, allowing both iMPACT-compatible JTAG and UART at the same time.Quote from: laugensalm on November 01, 2019, 02:07:45 pmThat memory chip is not SRAM. It is SDR SDRAM with a density of 512Mbit, arranged as 64M x8.

author: Ditiris
author_rank: Contributor
timestamp: November 05, 2019, 03:33:45 pm
content: Quote from: technix on November 05, 2019, 09:34:35 amInteresting. Are you able to use Chipscope too? I guess Digilent has some arrangement with Xilinx so that their chips are recongized by the tools. That is a shame. I wonder if Xilinx would be open to some sort of open standard so that the community could duplicate the functionality. I would love to design some starter boards for students, but including Digilent's chip or requiring the student to purchase a programmer for debug drives up the cost enormously.Quote from: laugensalm on November 01, 2019, 02:07:45 pmThose don't support debug do they? Ideally I'd like to reproduce Digilent's UART/JTAG channel that allows debug. I don't see anything in any of the projects that suggest that is supported.

author: laugensalm
author_rank: Regular Contributor
timestamp: November 06, 2019, 11:00:39 am
content: Quote from: Ditiris on November 05, 2019, 03:33:45 pmnetpp node supports JTAG debugging of the CPU (ZPU arch and Risc-V only) through the BSCAN primitives using a gdb proxy server. You CAN get chipscope to work, but I found it easier to just implement a simple trace on trigger logic (less intrusive on small FPGAs). I'm not up to date with the ZPUino/Papilio, but I'd assume this being state of the art these days.

author: technix
author_rank: Super Contributor
timestamp: November 06, 2019, 04:56:04 pm
content: Quote from: Ditiris on November 05, 2019, 03:33:45 pmAFAIK Chipscope should also work if your ISE version is recent enough. ISE 14.7 came with Digilent plugin preinstalled for both ISE and ChipScope.Digilent did not use a special chip of their own, they used a regular FTDI FT2232HQ (JTAG-SMT1 and JTAG-SMT3) or FT232HQ (JTAG-SMT2) with some special configuration data in its EEPROM. My own implementation used an FT2232HL and a modified version of JTAG-SMT1 EEPROM image I found online. Xilinx tool just detects it as a regular Digilent JTAG-SMT1. (I also have a USB stick sized Xilinx debugger with wiring and EEPROM based on JTAG-SMT2, using a FT232HL.)