Switching frequencies and noise in DC-DC converters - Page 1
Forum section: electronics / beginners

author: analogo
author_rank: Regular Contributor
timestamp: July 21, 2018, 08:09:36 am
content: What produces less noise (ripple) in a switching DC-DC converter: higher or lower frequencies?The switching frequency of DC-DC converter affects its efficiency and the size of the filtering components: the higher the frequency the lower the efficiency, the higher the frequency the smaller the external filtering components.https://www.sunpower-uk.com/glossary/what-is-switching-frequency/But what about the noise?Naively I would say that higher frequency converters produce the biggest ripple, but I am not so sure.Is there a thorough but understandable guide (app note) to the tradeoffs involved in choosing a switching frequency?

author: Ice-Tea
author_rank: Super Contributor
timestamp: July 21, 2018, 08:14:32 am
content: Higher frequency wih same components = lower ripple. At least with a regular buck.In simple terms: it's essentialy a PMW with a filter after it. You charge coil and cap during the 'on' part and you drain it while the switch is 'off'. The lower the frequency, the longer you are discharging coil and cap and the more the voltage will drop. At higher frequency your energy buffer get charged sooner or you can get away with less energy storage/lower value components/smaller components.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 21, 2018, 02:46:55 pm
content: Higher frequencies are more prone to radiating, but are also easier to filter (requires smaller filter components).Tim

author: ocset
author_rank: Super Contributor
timestamp: July 21, 2018, 09:38:12 pm
content: QuoteProbably the best way to kill noise in SMPS is to damp the switching transition....ie make the dv/dt and di/dt of the fet switch on and switch off slower......you do this by eg adding series fet gate resistance....but this does increase switchiong losses.Once i did a 150w led driver with 1r in series with fet gate.........when turned on , the lab radio turned off.......we increased gate resistor to 4r7 and problem was solved.

author: MaxSimmonds
author_rank: Contributor
timestamp: July 22, 2018, 04:32:16 pm
content: As Treez mentioned, this is very true. You can also have different turn on/turn off times by using a series gate resistor, and a parallel diode + series resistor. Like this:+----D-----R---+_______ | || Driver |------------R--------+--------- MOSFET GATE----------The diode would be reversed biased during turn on, and forward biased during turn off. I usually add this is as a precaution when laying out the pcb, incase the driver discharges the gate too fast for my likely and I want to dampen the resultant ringing with a different value resistor. It would be interesting to know if anyone thinks this is over kill/not needed?Either way, like Treez said, it's a fine line between high di/dt (causing voltage spikes and ringing) and a series resistor to dampen the ringing, which then increases the turn on/off times of the FETs (by an R*C time constant, where C is the gate capacitance) and hence increased switching losses.Usually a value between 1-5 ohms is good enough, it's best to leave space for a resistor on the PCB (if building one), you can always use a 0 ohm resistor if you see that you don't need it - but at frequencies of around 100-150k, I think they're going to be needed.I'm still very new myself with switch mode power supplies, I'm fresh out of uni, but that's my experience with them!

author: Ice-Tea
author_rank: Super Contributor
timestamp: July 22, 2018, 08:04:16 pm
content: Note that in this context noise is not the same as ripple...

author: jmw
author_rank: Frequent Contributor
timestamp: July 22, 2018, 08:09:49 pm
content: QuoteYou can think of your losses as being the sum of three categories:P_loss = P_cond + P_sw + P_fixedP_cond is conduction losses from traces, inductor DC resistance and capacitor ESRP_sw is the switching loss from transistor turn on/off, diode reverse recovery, etc.P_fixed is fixed loss from the running the controller circuit, etc.Since P_sw = W_sw * fs, where W_sw is the energy loss across one complete switching cycle, the above equation is alsoP_loss = P_cond + W_sw * fs + P_fixed, so there is, to a first-order, a linear dependence on the switch frequency.Solving for fs yields the critical frequency fs_crit = (P_cond - P_fixed)/W_sw. Below this frequency, the conduction losses dominate, and you might as well increase the switching frequency since you get to use smaller capacitors and inductors, yielding a cheaper and physically smaller converter. Above the critical frequency, the total loss is much more sensitive to switching frequency and it makes sense to reduce it to improve efficiency with the trade-off for larger components.It's probably not feasible to get analytical expressions for the above quantities, especially as the whole thing changes when you swap out components. But for a specific circuit and operating point, you can get an idea of the comparison between switching and conduction losses and iterate on the switching frequency for the design.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 23, 2018, 02:43:20 am
content: A crude approximation for P_cond is the RMS current through the switches (for MOSFETs), plus diode drops (for diodes), or some combination of both (i.e., the internal resistance + Vf model for diodes, also applicable to IGBTs).Speaking of analyticity, linear or quadratic models like this are simple enough to write, and may have straightforward solutions, enough that you can draw some conclusions on paper. As soon as you involve an exponential (ideal diode equation), however, the problem becomes transcendental: hopeless on paper, and you need an iterated approximation, or the Lambert W function, to solve it! (Such iterations are SPICE's specialty, however...)Likewise, P_sw can be approximated as the triangular region between rising (falling) voltage and falling (rising) current. The switch dissipates P_cond while on, effectively nothing while off (typical leakage currents are ~uA), and P_sw when commutating between these states. If we treat the edges as straight lines, either coincident (resistive switching) or one after the other (inductive switching, more typical at least for turn-off), then power is the product of those lines, either a triangle (one after the other) or a parabolic section (coincident). In either case (give or take a splash of calculus), we can determine the area under the curve, and thus the switching energy. Finally, multiplying energy by frequency, we get the average power P_sw.This is actually a bad approximation in most cases! Modern transistors have an extremely pear-shaped capacitance curve. The factor that makes a linear rise, is Miller effect: as gate voltage rises (falls), drain voltage falls (rises), causing a change in charge across the D-G capacitance. Because the transistor's gain is quite high during switching, the change in gate voltage is small, in fact it plateaus while drain voltage is changing most rapidly.Well, during the Miller plateau, if Cdg is constant, and Ig is constant, then the drain voltage will be a simple linear ramp. But Cdg actually depends severely on Vds: it's over 100 times higher at low voltages (under 5V, say) than at high voltages (over 200V, say -- typical for a ~600V part). This means most of the gate plateau is spent at low drain voltages, where power dissipation is small.This also means we don't gain much, in terms of EMI response, by introducing extra gate resistance. The drain risetime is dominated by the low-capacitance region (where it spends, say, 20% of its time, but 80% of its voltage swing). All we've done is increase the delay from gate-falling to drain-rising! To effectively limit drain dV/dt, we need to add a snubber, or add external (and linear) capacitance across D-G to extend the Miller slope. The former is preferable, since we're only adding more power dissipation in the latter case.(However, if you are stacking devices in series, the latter is unavoidable -- switching times will inevitably mismatch, even if the gates are driven from a common transformer, for example. Ensuring all transistors are rising at the same rate, not just the same time, limits how much worst-case voltage any one transistor will see.)Back to power, the consequence is that we will grossly overestimate how much P_sw these devices incur. But it's tricky, because it depends on which phase of switching you're looking at. If you have a hard-switching bridge circuit (like a class D amplifier -- in general, load current won't always be positive, sometimes it will go the other way because of a reactive load), you can have the unfortunate case that one transistor is off, but resting at ~0V (i.e., when it turned off, the voltage didn't simply swing up and away), and the other transistor turns on hard, yanking the switching node up and effectively shorting the supply into the other transistor. This goes slowly at first, because the other transistor has that huge capacitance at low Vds, then once it's charged past ~20V, capacitance drops off and fwoom, the switch node flings up at great velocity and usually overshoots and rings. In the process, switch current spikes sharply, loading the switching loop (the stray inductances between the high side and low side transistors, and the nearest supply bypass cap) with that peak current, which drives the capacitance to overshoot and ring. This ringing is often in the 30-100MHz range,Incidentally, a lot of references, to this day, suggest minimizing switching loop area / stray inductance, as if it were somehow an easily attainable goal. This was fine, back in the days of bipolar transistors and slow MOSFETs -- but it is inapplicable today. You can't get the inductance low enough to reach the required level*. What the advice should say is: optimize. If we can't get it effectively to zero, then what value should we pick? A hint: consider the both-switches-open impedance, which is 2*Coss (the D-S capacitance, at whatever voltage we're measuring -- probably take slightly less than the worst case condition). Then consider the both-switches-shorted impedance, which is the loop inductance. The ratio of these has units of squared impedance, interestingly enough. So we might define Zsw = sqrt(Lloop / Coss), the switching impedance. Compare this impedance to the load impedance, Vsupply / Isw(pk).*Some examples for illustration: a typical TO-220 device has 10nH lead + bondwire inductance. Put two together in a half bridge, plus another 10nH from each to the nearest bypass cap, and you have a total 40nH switching loop inductance. Modern transistors will switch in 10s of ns even without driving them hard, which implies, for a 10A load say, 40nH * 10A/20ns = 20V induced in that loop. (That's the inductor equation, V = L * dI/dt.) Expect a similar amount of overshoot!Or a pair of PDFN-8s in a DC-DC converter, say 24V input, 5V 20A output. The switching loop has to deliver those 20A in that fraction of a second, and the loop inductance can't be less than about 4nH for the best possible layout (transistors on opposite sides of a 4-layer board, vias inbetween, bypass caps adjacent). We might have 4nH * 20A / 10ns = 8V here, a full third of the supply -- this induced voltage acts to momentarily reduce the supply voltage, so the switching will actually be that 1/3 slower as a result (i.e., ~4/3 times what we expected). And this feeds into the P_sw calculation.Tim

author: analogo
author_rank: Regular Contributor
timestamp: July 23, 2018, 03:19:01 pm
content: Quote from: Ice-Tea on July 22, 2018, 08:04:16 pmWhat is the difference between noise and ripple when it comes to switching converters and their switching frequency?

author: MaxSimmonds
author_rank: Contributor
timestamp: July 23, 2018, 05:17:08 pm
content: Quote from: analogo on July 23, 2018, 03:19:01 pmI can't say forsure and perhaps Ice-Tea would be able to explain his point better, but I would say that ripple, when it comes to switching converters, is something that can be calculated and is often set as a requirement, IE, the output voltage ripple must be no more than 0.5%. However, noise is random and an effect of the high switching frequencies.Noise would be irregular and random, whereas any ripple will be fairly periodic and constant. I've attached two simulation outputs of a buck switch mode that I designed (it was a quick simulation to check that my equations I derived for component values to ensure I met the ripple requirements were correct).Transient shows the clean output, and ripple is the zoomed in version showing the periodic ripple - NOTE, there is no noise here, which is introduced from the high frequency switching and EMI from traces etc.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 23, 2018, 07:44:41 pm
content: Ehh, RFI is typically "fairly periodic and constant", too. Maybe a more practical definition: an undesirable signal. It's not exactly white noise if it's a modulated carrier buzzing at 120Hz (as so many PSUs create), but it's not helping your radio reception, or your high speed ADC, or whatever, in terms of reading some other signal that is desired.Thinking about "noise", there's another aspects to RFI, that's noisy (random), but in a different way: structurally, rather than temporally.It's difficult to predict the response of an arbitrary circuit. Even in a design structured to constrain the RFI output, there is uncertainty in just how much will be present at any given point, and how much will conduct out the connecting cables, or radiate off the circuit itself. The errors lie in uncertainty over component parasitics, circuit layout, phasing between different regions of the board, etc.In the same way that you might guard-band an intentional radiator for some minimum SNR, so too, you want to guard-band the design of an unintentional radiator, to ensure you're some minimum factor below whatever constraint your design has (usually regulatory, but also functional, say for that sensitive high speed ADC).Tim

author: Ice-Tea
author_rank: Super Contributor
timestamp: July 23, 2018, 08:56:51 pm
content: This is a classic example of ripple as you would get in a rectifier. You will find something comparable in a buck DC/DC.This is switching noise superimposed on that ripple. This is stuff you can get rid of with series resistors in the gate drive, decreasing parasitics, whatnot. Two different things.

author: Kjelt
author_rank: Super Contributor
timestamp: July 23, 2018, 08:56:59 pm
content: With high frequencies beeds can be a lifesaver, low ohmage for DC , high ohmage for high frequencies.Saved me a couple of times, but hard to simulate or does someone have a tip for that?

author: analogo
author_rank: Regular Contributor
timestamp: July 25, 2018, 06:01:56 pm
content: Quote from: Ice-Tea on July 23, 2018, 08:56:51 pmIIUC, higher switching frequency means less ripple but more noise. However the noise can be filtered out more easily at higher frequencies (says Tim/T3sl4co1l).Did I get it right?