Vivado error : size mismatch in assignment; read failed  - Page 1
Forum section: electronics / general

author: MichailM
author_rank: Newbie
timestamp: March 11, 2018, 10:50:10 am
content: Hello there, it's my first time posting here so I am not 100% sure if I chose the right category.My problem is FPGA synthesis related. While simulations seem to work fine, when i try to synthesize my code i get the following error.Code:[Synth 8-5765] size mismatch in assignment; read failedwhich is associated with the reading code I have.Code:read(inline, dataread1);[\code] to be specificSome parts of the code are below.Code: library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use work.system_definitions.all;use STD.textio.all;.........process(clk,reset)file infile : text;variable inline : line;variable dataread1 : asobel_int_internal;begin......elsif reset = '0' thenif (not endfile(infile)) thenreadline(infile, inline);read(inline, dataread1);data_in <= dataread1;Asobel_int_internal is a -2^10 to 2^10 integer declared in the system_definitions package.Any idea how to fix this ?Thanks in advance

author: m_t
author_rank: Contributor
timestamp: March 11, 2018, 09:09:00 pm
content: Unless you're creating a ROM, file operations cannot be synthesised. Can you post your complete code?

author: hamster_nz
author_rank: Super Contributor
timestamp: March 11, 2018, 11:28:16 pm
content: (Just to expand on m_t's answer).You can load data from a a file and use it to initialize signals. The way I've always seen it done is to define a function that reads in the the file, returning the desired values, and then have the signal initialized with the value returned by calling that function.For an example of how to do this, have a look at:https://electronics.stackexchange.com/questions/180446/how-to-load-std-logic-vector-array-from-text-file-at-start-of-simulationAlthough that link is aimed at simulation, the same technique works during synthesis too.

author: rstofer
author_rank: Super Contributor
timestamp: March 12, 2018, 05:20:15 am
content: Here is one example of using a hex file to program BlockRAM. It causes the executable code for a CPU core to be included in the build.If I'm not mistaken, the file handling code came from something hamster_nz posted elsewhere some time ago.Code:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use STD.textio.all;use ieee.std_logic_textio.all;entity BlockRAM isgeneric (SIZE : integer := 65536;ADDR_WIDTH : integer := 16;COL_WIDTH : integer := 16;NB_COL : integer := 1;FILENAME : STRING := "LC3.hex");port (clk : in std_logic;we : in std_logic_vector(NB_COL-1 downto 0);addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);di : in std_logic_vector(NB_COL*COL_WIDTH-1 downto 0);do : out std_logic_vector(NB_COL*COL_WIDTH-1 downto 0));end BlockRAM;architecture behavioral of BlockRAM istype ram_type is array (SIZE-1 downto 0) of std_logic_vector (NB_COL*COL_WIDTH-1 downto 0);impure function ocram_ReadMemFile(FileName : STRING) return ram_type isfile FileHandle : TEXT open READ_MODE is FileName;variable CurrentLine : LINE;variable TempWord : std_logic_vector(15 downto 0);variable Result : ram_type;beginfor i in 0 to 65535 loopexit when endfile(FileHandle);readLine(FileHandle, CurrentLine);hread(CurrentLine, TempWord);Result(i) := TempWord;end loop;return Result;end function;signal RAM : ram_type := ocram_ReadMemFile(FILENAME);beginprocess (clk)beginif rising_edge(clk) thendo <= RAM(conv_integer(addr));if we(0) = '1' thenRAM(conv_integer(addr)) <= di;end if;end if;end process;end behavioral;This is known to work with Vivado, and it does synthesize...

author: MichailM
author_rank: Newbie
timestamp: March 12, 2018, 08:49:01 am
content: Thanks a lot everyone, i have completely ignored that something like that is not synthesizable.What i was trying to do with it is feed my circuit a series of input from a txt and then write the outputs to another txt, creating a testbench of some short.So if i have understood correctly, you all said that i have to create a ROM containing the whole input txt folder and then start reading this ROM to get my inputs.Will the writing be synthesizable?Also, the reason i am doing this is to make a post-implementation simulation, you think that it is necessary or the simple simulation will be enough to guarantee that i will get the same results on an FPGA ?Thanks again

author: hamster_nz
author_rank: Super Contributor
timestamp: March 12, 2018, 09:18:36 am
content: Quote from: MichailM on March 12, 2018, 08:49:01 amIf that is the case, a non-synthesizable test bench that feeds your design and writes the output should be all you need. You only need the ROM if you want a synthesizable design that includes your test data.QuoteAs long as your design is correctly constrained and you use only one clock the hardware should agree with simulation... but only if enough care and attention have been put into the edges of the design (for example, have all async inputs been correctly synchronized?).If you use multiple clock domains in your design and ask this question, then I am pretty sure your design is broken without looking at it. Getting clock crossing to work correct is quite hard, even when you think you know what you are doing.

author: MichailM
author_rank: Newbie
timestamp: March 12, 2018, 09:40:49 am
content: Thanks a lotI am a beginner so I cant say I am sure about what I am doing but i do have only one clock