Problems with Quartus Modelsim simulation - Page 1
Forum section: electronics / general

author: e0ne199
author_rank: Regular Contributor
timestamp: March 04, 2024, 06:22:12 am
content: hello everyone, I am trying to make a RAM using the code below :RAM :Code:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity project1 isPort ( RAM_DATA_IN_OUT : inout STD_LOGIC_VECTOR (7 downto 0);RAM_ADDR : in std_logic_vector(7 downto 0);RAM_WR_EN : in std_logic;RAM_OUT_EN : in std_logic;RAM_CLK : in std_logic);end entity;architecture Behavioral of project1 iscomponent ram_entity isport (clk :in std_logic; -- Clock Inputaddress :in std_logic_vector (7 downto 0); -- address Inputdata_line :inout std_logic_vector (7 downto 0); -- data bi-directionalwrite_enable :in std_logic; -- Write Enable/Read Enableoutput_enable:instd_logic-- output enable);end component;begin----------------Code Starts Here------------------mem_module : ram_entity port map(clk=>RAM_CLK,address=>RAM_ADDR,data_line=>RAM_DATA_IN_OUT,write_enable=>RAM_WR_EN,output_enable=>RAM_OUT_EN);end Behavioral;Entity :Code:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ram_entity isport (clk :in std_logic; -- Clock Inputaddress :in std_logic_vector (7 downto 0); -- address Inputdata_line :inout std_logic_vector (7 downto 0); -- data bi-directionalwrite_enable :in std_logic; -- Write Enable/Read Enableoutput_enable:instd_logic-- output enable);end entity;architecture Behavioral of ram_entity is----------------Internal variables----------------type RAM is array (0 to 255) of std_logic_vector (7 downto 0);signal mem : RAM := (others => (others => '0'));--clear RAM on startupbegin----------------Code Starts Here-------------------- Memory Write Block-- Write Operation : When write_enable = 1MEM_WRITE:process (clk) beginif (rising_edge(clk)) thenif ( write_enable = '1' and output_enable = '0') thenmem(conv_integer(address)) <= data_line;end if;end if;end process;-- Tri-State Buffer control-- output : When write_enable = 0, output_enable = 1data_line <= mem(conv_integer(address)) when (write_enable = '0' and output_enable = '1')else (others=>'Z');end Behavioral;Test bench :Code:-- Copyright (C) 2019 Intel Corporation. All rights reserved.-- Your use of Intel Corporation's design tools, logic functions-- and other software and tools, and any partner logic-- functions, and any output files from any of the foregoing-- (including device programming or simulation files), and any-- associated documentation or information are expressly subject-- to the terms and conditions of the Intel Program License-- Subscription Agreement, the Intel Quartus Prime License Agreement,-- the Intel FPGA IP License Agreement, or other applicable license-- agreement, including, without limitation, that your use is for-- the sole purpose of programming logic devices manufactured by-- Intel and sold by Intel or its authorized distributors. Please-- refer to the applicable agreement for further details, at-- https://fpgasoftware.intel.com/eula.-- ***************************************************************************-- This file contains a Vhdl test bench template that is freely editable to-- suit user's needs .Comments are provided in each section to help the user-- fill out necessary details.-- ***************************************************************************-- Generated on "02/20/2024 05:17:47"-- Vhdl Test Bench template for design : project1---- Simulation tool : ModelSim-Altera (VHDL)--LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY project1_vhd_tst ISEND project1_vhd_tst;ARCHITECTURE project1_arch OF project1_vhd_tst IS-- constants-- signalsSIGNAL RAM_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL RAM_CLK : STD_LOGIC;SIGNAL RAM_DATA_IN_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL RAM_OUT_EN : STD_LOGIC;SIGNAL RAM_WR_EN : STD_LOGIC;COMPONENT project1PORT (RAM_ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);RAM_CLK : IN STD_LOGIC;RAM_DATA_IN_OUT : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);RAM_OUT_EN : IN STD_LOGIC;RAM_WR_EN : IN STD_LOGIC);END COMPONENT;BEGINi1 : project1PORT MAP (-- list connections between master ports and signalsRAM_ADDR => RAM_ADDR,RAM_CLK => RAM_CLK,RAM_DATA_IN_OUT => RAM_DATA_IN_OUT,RAM_OUT_EN => RAM_OUT_EN,RAM_WR_EN => RAM_WR_EN);mem_test : PROCESS-- variable declarationsBEGINRAM_WR_EN <= '0';RAM_OUT_EN <='1';RAM_ADDR <= "00000000";RAM_DATA_IN_OUT <= "00000000";wait for 100 ns;-- start reading data from RAMfor i in 0 to 5 loopRAM_ADDR <= RAM_ADDR + "00000001";wait for 50 ns;end loop;RAM_ADDR <= "00000000";RAM_WR_EN <= '1';RAM_OUT_EN <='0';-- start writing to RAMwait for 100 ns;for i in 0 to 5 loopRAM_ADDR <= RAM_ADDR + "00000001";RAM_DATA_IN_OUT <= RAM_DATA_IN_OUT-x"01";wait for 50 ns;end loop;RAM_WR_EN <= '0';RAM_OUT_EN <='1';RAM_ADDR <= "00000000";RAM_DATA_IN_OUT <= "00000000";wait for 295 ns;RAM_ADDR <= "00000000";-- start reading data from RAM--for i in 0 to 5 loop--RAM_ADDR <= RAM_ADDR + "00000001";-- wait for 100 ns;--end loop;WAIT;END PROCESS mem_test;CLK : PROCESS-- variable declarationsBEGIN-- code executes for every event on sensitivity listfor i in 0 to 1000 loopRAM_CLK<='0';wait for 5 ns;RAM_CLK<='1';wait for 5 ns;end loop;WAIT;END PROCESS CLK;END project1_arch;after reading the generated RAM (which is initially empty), I try to write into the RAM and read the first address of the written RAM again. The result is like this :the logic becomes floating after I try to read the RAM (red lines)...do you know what is wrong with this simulation??btw I am still new to FPGA and I hope you could give me guidance for this problem since I am still unable to resolve it until now..thanks before

author: Daixiwen
author_rank: Frequent Contributor
timestamp: March 04, 2024, 02:29:00 pm
content: When reading from your test bench, you need to assign a high impedance value to RAM_DATA_IN_OUT:Code:RAM_DATA_IN_OUT <= (others => 'Z');In your code currently both the test bench and the RAM try to send an output on the same signal. As long as it's 0 there won't be a problem, but if the RAM tries to assign a 1 to a signal and the test bench tries to assign a 0 to it, then there is a conflict and the resolved signal becomes 'X'.As a side note you should avoid using ieee.std_logic_unsigned. It is non standard but unfortunately there are still a lot of examples and books that use it. It makes it also impossible to use signed signals in the same code. You should use ieee.numeric_std instead and the standard signed and unsigned types.

author: e0ne199
author_rank: Regular Contributor
timestamp: March 04, 2024, 05:31:29 pm
content: Quote from: Daixiwen on March 04, 2024, 02:29:00 pmdamn you are right...thank you so much for the helphowever, do I have to change the variable if I change ieee.std_logic_unsigned into ieee.numeric_std?

author: Daixiwen
author_rank: Frequent Contributor
timestamp: March 06, 2024, 08:59:32 am
content: Quote from: e0ne199 on March 04, 2024, 05:31:29 pmYou're welcome.Switching to ieee.numeric_std implies a few changes to your code. You can't use std_logic_vector as signed or unsigned values any more, there are two new types, called "signed" and "unsigned". You can convert to and from std_logic_vector using casting. The conv_integer() function is also called to_integer() when using a "signed" or "unsigned" parameter.