How to size capacitors based on the ripple current in a buck converter? - Page 1
Forum section: electronics / beginners

author: Faranight
author_rank: Unknown
timestamp: January 31, 2022, 11:01:24 am
content: Hello!I'm trying to design a synchronous buck converter for a hobby project. I've already done some calculations to size the components (inductor, caps, mosfet switches, etc). I've sized the input and output capacitors based on the maximum allowed input/output voltage ripple and ESR, but I'm having some trouble understanding how to also size them for their maximumrated ripple current. Yes, I know I can use several smaller caps in a bank to get lower ESR and larger total surge current, and that combining MLCC's with electrolytic caps lowers the ESR over wider frequency range. It's the equations I don't understand.Can someone please verify, if the calculations are correct because I've seen several different equations proposed in various papers. I'll post them and some other relevant ones for the caps ripple current in a PDF attachment. The equations 1A and 1B are for the output capacitor while equations 2A through 2C are for the input caps.Thanks!

author: Faranight
author_rank: Unknown
timestamp: February 01, 2022, 10:25:40 am
content: Unfortunately I'm not sure I understand your answer.What you told me is essentially a part of the the basic buck calculations that I've already been through. The equation you mentioned (or at least another one derived from it) supposedly gives a minimumcapacitancerequired to keep the input/output voltage ripple within the given specification, but does not directly specify the capacitor ripple current. Manufacturers usually specify what surge current rating their capacitors are, and if you exceed this current you will significantly shorten the cap life.I was trying to calculate this ripple current so I can pick the capacitors with larger ripple current ratings. Are you saying that I should just ignore this rating and build a bank of caps that has its total ESR lower than the one used your the equation?

author: Mechatrommer
author_rank: Super Contributor
timestamp: February 01, 2022, 11:30:05 am
content: if you like formulas, then you can read...https://www.ti.com/lit/pdf/slva477https://www.coursehero.com/file/19652517/AN041-EN/i dont read them carefully since i use spice simulator... ymmv.

author: David Hess
author_rank: Super Contributor
timestamp: February 01, 2022, 03:04:15 pm
content: What matters is that the ripple current causes self heating of the capacitor and higher temperature shortens capacitor lifetime. So the capacitor is rated to last a given number of hours at a given ripple current or temperature, and lowering the temperature 10 degrees C roughly doubles operating life.Lower ESR capacitors have less self heating so they last longer. Using several smaller capacitors in parallel or series increases surface area for a lower thermal resistance to ambient so temperature rise is lower and they last longer.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 01, 2022, 04:11:20 pm
content: Ripple ratings can be estimated from ESR or tan δ and an estimate of power dissipation capability (conduction/convection and size) -- but mind this misses internal temp rise, and capacitors aren't always the most conductive materials. In particular, electrolytics are made of layers of moist paper, film capacitors are, well, made of plastic, and the ceramic material (BaTiO3 and relatives) is less than half the conductivity of say chip resistor material (Al2O3). The metal layers are very thin so it doesn't make much difference in the conductivity of film or ceramic caps, and it's spiraled in electrolytics. (It does depend on the film cap: some are made with heavier metallization, or foil. The beefiest are made of multiple smaller units in parallel, soldered between heavy copper plates for water cooling!)Since this is rather unreliable, a better policy is to not use any capacitor that doesn't carry ratings, for anything that is likely to be important. Keep shopping and find something that carries ratings. You likely need ESR or impedance for such applications too, and general info like tan δ isn't very good for that.Mind that you may not find ratings in the supplier's catalog. Electrolytic ESR is most common I think, followed by film ESR, and ceramic characteristics. You may have to search the manufacturer's website to find characteristics. Most have some kind of database or "simulation" section to look this up, or, find the web page for the part/family, and see if it links to these resources.Characteristics are particularly important for ceramic capacitors, as their capacitance varies with applied voltage, and this bears little if any relation to the rated voltage, and a modest relation to size. So you really have to look up the char and see if a part has enough capacitance left at operating level to be useful.Char sheets usually include rated current as well, or permissible voltage vs. frequency. Again, if it doesn't have what you're looking for, keep shopping, there's plenty to choose from.Tim

author: Siwastaja
author_rank: Super Contributor
timestamp: February 01, 2022, 04:57:49 pm
content: Am I really the only one who understood what the OP is asking?I mean, a lot of answers, some even good, but no one is addressing the question at all?Which was, how to calculate the ripple current of the capacitors in a synchronous buck. Capacitor selection is obviously then quite easy as the ripple current is listed on datasheets directly (fsw=78kHz seems to be quite close to the 100kHz rating in electrolytic cap datasheets).Or maybe I'm the only one who didn't get it.Anyway, my take on it, regarding the input cap; I don't understand how the formulas ended up with 15A. Look at the theoretical waveform, and the answer is there: if we approximate delta I_L as zero, the input current to a buck converter is a pretty square wave, with I_off = 0, and I_on = I_out. Thisisthe ripple current. So the answer would be 30A. Yes, a buck is horror for the input caps, that's its well known Achilles heel. Also the reason why multiphase converters are a big thing. High frequency at least allows you to use small enough capacitance to make it fully MLCC, with small ESR.Now, how much is actually supplied by the capacitors, and how much is supplied from the upstream circuitry - in the end, capacitors in whatever power supply is supplying the buck! - is very hard to calculate, I guess. I usually try to simulate this in Spice, modeling the wiring ESL and ESR, and the capacitance of the upstream circuit.

author: David Hess
author_rank: Super Contributor
timestamp: February 01, 2022, 11:20:50 pm
content: Quote from: Siwastaja on February 01, 2022, 04:57:49 pmCalculating the ripple current for a given design is not difficult, and there are many excellent application notes showing exactly how. Page 61 ofLinear Technology application note 19gives the formulas for calculating ripple current of various topologies.Less obvious is how ESR and ripple current rating interact with capacitor operating life so that is what I discussed.

author: Faranight
author_rank: Unknown
timestamp: February 02, 2022, 07:50:59 am
content: Full buck document attachedWhile I still don't completely understand the work behind cap selection, I thank you for all the answers so far. I should probably have published my full research notes in the first post. Hopefully this will clear up how far I managed to get in the design phase. So, if anyone is interested, here is the full document that shows how I calculated and sized various components for the power stage (WARNING: Lots of math inside). Most of these equations I found by reading a number of papers and application notes on buck design. I also did some power loss calculations on paper for the inductor, switches and caps, but those are not included. Schematics in KiCAD isn't finished yet.Regards!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 02, 2022, 08:50:34 pm
content: Ah, some notes on notes would be useful then...1. p3: ΔI_L is determined by desired inductor loss, controller capability, and desired output ripple.Controllers matter, because you will choose a current-mode control for performance and safety. Voltage-mode (monitors Vout, sets PWM directly) controllers are undesirable for poor transient response and uncontrolled peak currents. Consequently, you also need something to monitor inductor current: this can be direct, as a shunt resistor, Hall effect sensor, etc. in series with it (typically on the output side, or input of a boost, so there's less switching noise to deal with), or in the ground return if common grounds (between input and output) are not required. The switch and/or diode currents can also be monitored, with some limitations.Peak current mode control is quite popular for smaller applications (under 100W say), and is one of the simplest methods, requiring only a switch current sense. Consider theUC3842family for example. The downside here is, in CCM (continuous current mode, ΔI_L/I_L < 100%), it enters a limit cycle, where an initial difference in pulse widths, grows over subsequent cycles, until one pulse is very short, effectively at BCM (boundary conduction mode), and the other is very long. The threshold for this cycle is called bifurcation, and the symptom is called subharmonic oscillation. At still higher output current (lower ripple fraction)*, the pulse widths break into a cycle of 4 pulse widths (passing another bifurcation point), and so on, increasing rapidly from here, until the period is so long and poorly defined, it's essentially random noise -- full-on chaos. It's fascinating that such a simple system exhibits chaos -- this is in fact an analog implementation of the logistic map function. Of which, the bifurcation diagram is a rather beautiful structure you can derive from it. But this behavior is unfortunately not something too useful for power conversion, as the ripple is increased -- so, noisier input and output, and more inductor losses.*This is fixed frequency, so ΔI_L is constant for I_L > ΔI_L/2, and ripple fraction is inverse with load current.Peak current mode can be improved with slope compensation, which makes it a hybrid with voltage-mode PWM control. Some of the timing ramp is bled into the current sense pin, so that rather than a fixed current threshold, the current threshold varies with time, dropping through the duration of a cycle. This has the downside of reducing current regulation, so short-circuit (fault) or startup current is increased. This extends the stable region into CCM, down to ripple fractions about on par with the ratio of current to voltage slopes in the sense signal. It's typically not a good idea using more than 2-3x slope compensation (the fault current is too high / poorly controlled), and so, peak current mode controllers aren't suitable for ripple fraction under 30% or so.Ripple fraction corresponds directly with inductor AC losses, so this likewise puts an upper limit on what's economical with respect to efficiency and scale. A bigger like 500W capacity converter, you probably want to cheap out and use a powdered iron inductor if you can, but those need quite low ripple fraction (say 10% or less) so peak current mode is unsuitable.Note that ripple fraction is also the amount the current can change during a cycle. If the ripple fraction is 10%, roughly speaking, it takes about 1/(10%) = 10 cycles to ramp the (cycle-averaged) inductor current up/down by that amount. Which means the loop bandwidth must be also that slow -- about 10% of Fsw. This makesaverage current mode controlattractive given the limitations of many sensors: current sense amps tend to have limited GBW, and Hall effect sensors simply aren't that fast, even with what little dynamic range they have. Both tend to roll off in the 100kHz region -- but if we're using them to run an AvCMC, we can still run Fsw up quite high (300kHz+?) and not worry too much about it. Put another way, we don't need cycle-by-cycle current limiting, as long as the response time is adequate to protect the switching devices (MOSFETs can handle some 10s to 100s µs of overload -- as long as it's not repetitive, anyway). (We might still want a peak current protection, just in case of gross error; this can be by sensing switch current again, or even switch voltage (Rds(on) sense, or desat protection). Usually such a fault is latched, either with a long timeout (auto-restart), or requiring external reset or power cycle.)The nice thing about average current mode control, is we can limit the inductor current very precisely, by design. Here's a discrete implementation of an average current mode control boost converter:https://www.seventransistorlabs.com/Images/Flashlight2Sch.pnghttps://www.seventransistorlabs.com/Images/Flashlight2_Schematic.pngNote the input ground side current sensing, possible thanks to battery power. IC2 produces direct (voltage mode) PWM for the switch; this is controlled by IC3B, the current error amp. By controlling the current setpoint INSP, the inductor current is likewise precisely defined. Specifically, by limiting the maximum voltage here (by allowing IC3A to saturate positive, or if a variable limit is desired, adding additional circuitry to clamp it lower),But current, so what, that's useless, you want regulated voltage, right? That's the beautiful thing. Simply control the current to regulate the voltage. IC3A is the voltage error amp, or, well -- it's a little more than that, in this LED driver, because LED current is regulated first**, and output voltage only as a safety valve (D3). But this is merely down to the connection of R25 and related components. (There's also overtemp, and input undervoltage to prevent overdischarging the battery.)**This is useful because inductor current is not the same as LED current. As battery voltage varies (with load, and as it discharges), input power varies, and so output power accordingly. Not really necessary for a flashlight, but a nice-to-have: the output will not dim at all until the battery is physically unable to supply the power requested.(Oh what the hell, this screenshot is old. R17, R18 are supplied by VBATT, not VOUT. How did that happen?... Apologies.)Anyway, the best part is this: the inductor and capacitor responses are decoupled, and the circuit behaves as two first-order loops concatenated, rather than one second-order loop (as with the voltage-mode case, where PWM goes into an LC filter with 180° phase shift above Fc). The response rate can, in fact, be faster than Fc (~1/sqrt(LC)), giving better transient response, in addition to the perfect current limiting/protection.So, I strongly recommend understanding and using current mode control, whatever the method; it fully cures one of the big hazards to switching converters. There are still plenty of other ways to kill them -- voltage and temperature for example -- but eliminating one (overcurrent) is a huge help.One more thing about AvCMC, it's well suited to synchronous application: just drive a full wave at whatever the PWM is, and that's your ΔI_L fixed in stone, always on, all the time (well, proportionate to VIN and L, but not depending much on ISET or VOUT anyway). Note that it's still drawing ΔI_L even at Iout = 0, i.e., inductor current is pulled negative for half the cycle! This can be advantageous when consistent operation is required (the control loop is always active, giving low output ripple and stable output impedance), but obviously all that switching effort is for naught, so the light-load efficiency is crap. If you're building a discrete control, like the above, it's easy enough to do this way, and that's fine, just deal with the poor efficiency, it's an experiment or whatever, right?Most controller/regulator ICs, have a synchronous rectification mode, disabling low-side drive when current reverses, or a burst mode, disabling the output when light load is detected (for example, maybe ISET is made to saturate at some minimum value, chosen so that inductor current is always positive; this would overcharge the output at light load, so the output is simply disabled when it reaches nominal max, then is allowed to discharge to nominal min where it restarts, and so on).There are many other controller types out there; hysteretic control can be very efficient, but suffers from poor frequency control (so, min/max t_on, t_off may be poorly defined) and high output ripple; constant-on/off time controls work similarly to peak current mode but bypass the chaotic instability by changing frequency; etc. Most have some tradeoff between input/output ripple (variable frequency, hysteresis) and efficiency. There's also resonant topologies which can offer exceptional efficiency, but are even harder to control (you've got to juggle not just an inductor, but one or more capacitors along with it, in real time!) so are out of scope here.Back to the notes. The relations are more or less fine. Not sure what I_L(min) is in (3.3), that's not what I would expect for a label and that's not how RMS works; but it's not a big deal for the most part, because the effect of AC RMS isn't easy to model (i.e., datasheets rarely give enough information to calculate AC heating / losses).To clarify: RMS of a triangle wave is 1/sqrt(3) of the peak value (just as that of a sine is 1/sqrt(2) of peak, neat huh?). So that's true for a triangle going symmetrically above and below zero (i.e., no DC). Which is not the same as ΔI_L, but actually half that. We can then take the RMS sum of DC and AC components, to get the actual RMS total: sqrt( I_L(DC)^2 + ( ΔI_L/(2 sqrt(3)) )^2 ). In general, orthogonal currents add like the axes in a distance vector, RMS = sqrt(x^2 + y^2 + ...) (Parseval's theorem). DC and a triangle wave are orthogonal (a definition of this, is probably out of scope, so take that as given for now) so this is okay.(3.4) You haven't drawn any waveforms here, but note this simply comes from the flux balance condition: in steady state, flux during a cycle must total zero. This is especially easy in SMPS because the voltages are square: draw the SW node waveform, draw VOUT through it, and mark the areas above and below (thus, V_L during high and low phases). The areas must be equal. Period = 1/f_sw and pulse width = period * D so this all works out.Note that you may have to modify the top/bottom levels of the square wave, to account for switch/diode loss; that's where η comes in. Just using it as a rough factor is more or less fine. There isn't really any point in using it in the inductor calculation, mind -- it's going to be what, a 10% or so difference, but you can hardly even buy 10% inductors, and 20% is more than good enough.Also, since L is more or less constant in a given application, the effect is that either ΔI_L or f_sw must vary with respect to supply/output voltages. This is just the nature of things, a range we need to guard-band / min-max to have a stable and reliable design.(3.5) Not much info on that inductor, is there...Ah, I see the mfg site here:https://www.feryster.com/polski/dtmss1.php?lang=en&id=52&ver=vRather encouraging BTW that it's multi-stranded, proper braided litz even, by the looks of it(!). This greatly reduces AC resistance of the wire, a substantial improvement particularly at high ripple fraction. The core appears to be powder, uhh, looks blue, it might be a Sendust type? Colors aren't very specific unfortunately. Ooh, L(Idc) and L(f) plots, very nice! Oh, and the former even gives the part number: MS-... is indeed a Micrometals Sendust type, reasonably low losses. Probably okay to run up to 20% or so ripple fraction? Core losses can be calculated as well (vs. f and ΔI_L), given that core type and turns are known!(4.1) a very reasonable figure with ceramics, or polymers; electrolytics you would indeed use more -- as this is just a minimum figure based on reactance, not the sum with ESR as well. Actual ripple is the (RMS*) sum of both.*Because the components are orthogonal: while the voltage drops due to reactance and resistance, are at the same frequency, the components are at 90° to each other (orthogonal in the geometric sense!), so we can apply the same formula. There is exactly one perpendicularity this way (resistance vs. reactance), so this RMS sum will only ever use just the two terms. Note this doesn't help for design purposes; C and ESR are independent, we can't constrain both with this one relation. We just keep shopping until we find capacitors good enough (alone, or when arrayed in parallel).(4.3) comes from the impedance of the network: an LC filter has characteristic impedance Zo = sqrt(L/C). This is, for example, the peak output voltage change, divided by some input current step, for an LC hanging off an ideal voltage source. Which is fairly relevant for the voltage-mode control case: the controller must be slower than 1/sqrt(LC) so for frequencies near/above that, the dynamics are given more or less by the filter alone -- but this does not apply in the case of current-mode control, where the response can be faster than this.We might still use this relation elsewhere in the circuit -- if we need additional filtering for example, we might place an LC local to a device, and we need to set Zo such that it is well damped by nearby resistances (such as capacitor ESR and inductor DCR, i.e. ESR ~= Zo). If we cannot afford this (say because we need too much L to achieve the desired Fc and attenuation, and the C would be both excessively large and too low ESR anyway), then we can introduce ESR by adding explicit resistance. This doesn't need to be done at expense to high-frequency transient response; smaller, low-ESR caps can be connected in parallel, so long as the large, lossy cap dominates near Fc.Oh, I've been using Fc a bit, let me be clear: Fc = 1 / (2 pi sqrt(L C)). I used 1/sqrt(LC) earlier as a proportion; this is the angular frequency, and Fc = ω_c / (2 pi). So, same thing give or take a constant of proportionality.So, when we want to dampen a filter, we might have a series inductor L, and a shunt capacitor C, such that Fc is met (or, for attenuation at some frequency, Fc being however far below that to suit -- assuming say -40dB/dec. slope as a starting point, or higher order for more LC's), Zo < Zmax, and with enough ESR in C to equal Zo. We can then add up to about C/3 in parallel, with low ESR, to keep a low output impedance at high frequencies. So, 1uH into 10uF should have 0.3Ω ESR (and is good for any load that needs >= 0.3Ω source impedance), and can have up to 3.3uF (low ESR) in parallel with that cap.(4.4) I think either should do, but your RMS figure is incorrect. The second one is just undoing the RMS, so it's identical to whatever was put into that number, eh?In steady state, likewise for the flux balance in the inductor, so too, the capacitor has a charge balance; it has 0 DC, and only absorbs the AC component. So its peak is ΔI_L/2, and the RMS is 1/sqrt(3) of that.(4.5) Voltage rating is fine to be equal or greater for ceramic, polymer and electrolytic, with some derating being desirable for longevity; tantalums usually should be 2-3 times, as they are prone to failure with lower margins. You wouldn't use tantalum here anyway, they're not recommended for power supplies, especially at high currents like this.The one glaring exception is ceramic voltage ratings: just as the L(Idc) curve drops off under bias, the C(Vdc) curve drops off under bias for type 2 ceramics. This is poorly documented on the supplier side, so you must go shopping for characteristic sheets that plot this. Sometimes it's linked from the supplier (Digi-Key sometimes has these), sometimes you have to look up the part on mfg's site and find their database/simulator/whatever resources to find this out.On the upside, it's hard to make ceramic capacitors that run out of steam below a couple volts -- likely you won't have any problem using say 1210 size chips at 22uF, 6.3V or higher ratings. But do check to be sure. You typically want to keep 50-80% of nominal value at operating voltage. This cutoff point may be above or below the rated voltage -- the voltage rating is just that, a functional rating -- it has nothing to do with the electrical characteristic!Likewise, ferrite beads -- if you find a need for them -- saturate at high DC current. They are only rated for thermal current ratings and rarely if ever have saturation listed (inductors however, typically do list saturation). Ferrite beads are an inductive component, but used for slightly different purposes from inductors, so the market makes this distinction, and not knowing the difference can result in misuse (i.e., placing ferrite beads in high-current supplies, where they saturate, accomplishing nothing). For point of reference, typically chip beads around say 100Ω (at 100MHz) and 0805 chip size, saturate at 200mA or so. It's more or less proportional to component size and inverse with impedance rating, but you really need to check the characteristics to be sure (and mfgs are even more stingy about ferrite bead ratings than ceramic caps, alas).(5) 75mV is quite a low ripple for an automotive-ish input range! Would a percentage not be more realistic?Also, it might turn out that you needmuch less-- maybe not for this, I have no idea what context this is in, but for something offline (mains) powered, you typically need just a few 10mV of noise to meet EMI limits. In this case, you'll calculate for some modest supply inlet ripple, then add an LC filter in front to improve it further. This is designed same as an output filter, so the above commentary applies, as well as general filter design which is a bit out of scope here, but a matter of importance all its own.And, the rest goes the same way, derive Irms from the waveform, etc.Oh, about drawing waveforms: this website shows them for you, as well as giving the formulas to obtain them. I suggest reading in detail, working it out, draw the waveforms yourself and get comfortable with it.http://schmidt-walter-schaltnetzteile.de/smps_e/smps_e.htmlThen once you know how to do it, use this to save time drawing it all out every time.As for input caps, yes, likely MLCCs, at that voltage maybe 1206 or 1210 chip with 4.7uF+ rating, X7R, or no worse than X5R anyway. (Besides C(V) curve, C(Temp) is also a thing, being reasonable for these types and much worse for anything more dense like Z5U etc..) You can use a parallel combination with higher-ESR caps, the ceramics to "take the edge off", handling whatever total ripple is needed.Tim

author: Faranight
author_rank: Unknown
timestamp: February 05, 2022, 10:00:37 am
content: Whoa, thank you so very much for this extensive answer. Seems like plenty of food for thought.I will definitely re-read it several times as I try to re-do my design.-far

author: Siwastaja
author_rank: Super Contributor
timestamp: February 05, 2022, 10:16:19 am
content: I think it just boils down to:* Understanding the waveforms of the topology. Buck is pretty trivial.* Separating the AC and DC part of those waveforms* Understanding how to calculate the RMS of the AC part, because that is what flows through the capacitor ESR and heats it up.Cheatsheets with RMS calculation for different types of waveforms are useful.