Replacing SRAM with SPI PSRAM concerns - Page 1
Forum section: electronics / projects

author: pieroc91
author_rank: Contributor
timestamp: January 10, 2023, 07:45:45 pm
content: Hi everyone.I'm evaluating my choices on choosing RAM for a project. On short I need to buffer in RAM data that is being sent from an ADC that's connected to an FPGA, the ADC data is only at 6mhz but it's 8 bits in parallel, so 48Mbits/s worth of data, I need to buffer it on RAM so I can write it later to an SD Card, the amount of data is just 1.3Mbytes, so any 2Mx8 or more is good enough.Question is, PSRAM is fast and good enough to do so, but are SOIC 8 SPI ones good enough for it? I know they have low performance on random operations, but how about burst operations?And the very specific question, can I scavenge the 4MB PSRAM chip included on the ESP32-CAM board for this purpose? (this is the only one I can source on my country, buying overseas is quite of a problem over here).Thanks!

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 10, 2023, 07:51:36 pm
content: Get the datasheet of the part you want to use. Only it can answer your question.A general answer will be that most PSRAM chips should have no problem with a throughput of 6 Mbytes/s per se if you use burst transfers, but the limiting factor here will be the data bus. If it's standard SPI and not QSPI, you'll need a SPI clock > 50 MHz which may be a problem. You need to check what max rate the SPI interface supports, both on the PSRAM chip and on the MCU you plan on using.

author: tmadness
author_rank: Regular Contributor
timestamp: January 10, 2023, 07:55:49 pm
content: I found this on Infineon's PSRAM webpage:Quoteso depends on how long and often the bursts are and how fast the PSRAM refreshes.

author: pieroc91
author_rank: Contributor
timestamp: January 10, 2023, 09:05:45 pm
content: As far as I can see on the datasheet it is possible but is kind of a mistery, on a picture i can see it is an IPS8404LSQ , which might be a clone of the APS6406L-SQN (i've found both datasheets but I don't trust much this no-brand documentation).I can use QSPI without problems on the FPGA up to 100mhz.The question is more regarding continuous speed, the data burst cannot be paused or slowed down since is reading a still from a CCD sensor, any hiccup is data that is lost.I want to know if i'll be able to shoot data to the IC and get it buffered correctly or if the SPI bus and/or internal controller of the IC can add too much latency or overhead to the point of making it not suitable for this usage. Not specifically from a datasheet but from an experience stand point.

author: langwadt
author_rank: Super Contributor
timestamp: January 10, 2023, 09:16:42 pm
content: Quote from: pieroc91 on January 10, 2023, 09:05:45 pmit say 84MHz linear burst so in quad mode almost 8 times what you need, and since you are using an FPGA even if you had pauses that should easily be handled with a small buffer

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 10, 2023, 09:18:08 pm
content: There is always going to be some possible latency, the only thing that can be more or less guaranteed is the average throughput. Just like with any other kind of SDRAM.You'll need to buffer your data in the MCU's (or FPGA's) RAM using a double-buffering scheme or similar. Very typical.

author: pieroc91
author_rank: Contributor
timestamp: January 10, 2023, 09:46:09 pm
content: Quote from: langwadt on January 10, 2023, 09:16:42 pmExcellent! I guess I can use some of the internal register memory inside the FPGA to compensate any stutter on the transfer.Had you any experiences using this kind of chips? is always good to know if there are any perks of using some stuff.Anyway, thanks a lot!

author: DavidAlfa
author_rank: Super Contributor
timestamp: January 10, 2023, 11:36:01 pm
content: Also your must free the CS pin every 64us or so to allow internal refresh, you can't make indefinitely long transfers like in a SPI flash.

author: pieroc91
author_rank: Contributor
timestamp: January 11, 2023, 01:59:34 am
content: Quote from: DavidAlfa on January 10, 2023, 11:36:01 pmThat's quite an important piece of information, I have to check how much time the CS pin must be freed and calculate if I have enough space on register memory inside the FPGA to hold the data while the ram refresh.Thanks!

author: Scrts
author_rank: Frequent Contributor
timestamp: January 11, 2023, 03:14:14 am
content: Is there any reason you don't want regular SRAM or SDRAM chip? Lack of pins on FPGA?

author: pieroc91
author_rank: Contributor
timestamp: January 11, 2023, 03:41:03 am
content: Quote from: Scrts on January 11, 2023, 03:14:14 amMultiple reasons, one of course is I'm getting short on I/O, another one is that SDRAM requires quite some coding and i'm not that skilled, on the other hand SRAM is easy to code but where I am is not easy to get, and the final reason is because I can use the SPI RAM shared between devices, I write on it with the FPGA and read it with and ESP32 to dump the content to an SD Card without adding code complexity.