LoFive R1 (320 MHz RISC-V board) - Page 1
Forum section: electronics / general

author: brucehoult
author_rank: Super Contributor
timestamp: April 24, 2019, 09:48:52 pm
content: https://groupgets.com/campaigns/533-lofive-r1This is a 3rd party board in something roughly similar to Arduino Pro Mini form factor using the newly updated SiFive FE310-G002.SpecificationsMCU – SiFive Freedom E310 (FE310-G002) 32-bit RV32IMAC processor @ up to 320+ MHz (1.61 DMIPS/MHz)16 KB RAMStorage - 128-Mbit SPI flash (ISSI IS25LP128)Expansion - 2x 14-pin headers with JTAG, GPIO, PWM, SPI, I2C, UART, 5V, 3.3V and GNDMisc - 1x reset button, 16 MHz crystalPower Supply - 5V via pin 1 on header; Operating Voltage: 3.3 V and 1.8 VDimensions - 38 x 18 mm (estimated)License - CERN Open Hardware License v1.2$25N.B. requires an external programmer e.g. FTDI breakout (also available from the same page)

author: andersm
author_rank: Super Contributor
timestamp: April 24, 2019, 11:11:21 pm
content: There's also an updated HiFive1 Rev B available for preorder on CrowdSupply, featuring the new FE310-G002 chip, on-board ESP32 wireless module and embedded J-Link debug interface.https://www.crowdsupply.com/sifive/hifive1-rev-b

author: legacy
author_rank: Super Contributor
timestamp: April 26, 2019, 10:20:59 am
content: These two are really small. Perfect for hacking a graphics calculator, replacing the main board with something new.

author: ralph F
author_rank: Newbie
timestamp: December 02, 2019, 01:53:41 pm
content: Hi guys, after first stumbling upon this thread I found that this board is also supported by J-Link which works flawlessly for me.I found their guide here.https://wiki.segger.com/GroupGets_LoFive_R1_1So maybe this helps others that find this thread as well.Cheers.

author: pallav.aggarwal@gmail.com
author_rank: Contributor
timestamp: December 07, 2019, 04:20:26 pm
content: Did anyone try FreeRTOS on this MCU?Do you guys know if they will be launching any new MCUs in the future, any roadmap published somewhere?Thanks.

author: tszaboo
author_rank: Super Contributor
timestamp: December 07, 2019, 04:40:24 pm
content: That SRAM sounds like a bad joke. Is that supposed to be just some on chip cache, or thats all we get?

author: brucehoult
author_rank: Super Contributor
timestamp: December 07, 2019, 08:05:29 pm
content: Quote from: NANDBlog on December 07, 2019, 04:40:24 pmWhy a joke?I had a look through the MCUs offered on Digikey and Mouser recently and the *vast* majority have 16 KB or less of SRAM.If you want a different amount, you're free to contact the manufacturer, SiFive in this case. As you can see onhttps://scs.sifive.com/core-designerthe E3 core has standard, tested, options of from 4 to 64 KB of icache and from 4 to 256 KB of data SRAM. There are many, many other customizations that can be made -- far too many to build all the tousands of variants possible and keep them in a warehouse somewhere on the off-chance that someone wants to buy one. "Made to Order" is the business model here.The new "SiFive Learn Inventor" board for education has an E31 variant with 64 KB of SRAM.https://shop.pimoroni.com/products/sifive-inventor

author: brucehoult
author_rank: Super Contributor
timestamp: December 07, 2019, 08:11:37 pm
content: Quote from: pallav.aggarwal@gmail.com on December 07, 2019, 04:20:26 pmBetter than a roadmap, there is a web site where you can configure exactly the CPU core you want (and soon the entire SoC)https://scs.sifive.com/core-designerand then get them made to order.Thousands of variants can be made, but what is actually made depends on what some customer wants and orders. Excess production might then be made available in the (tiny) retail chip market.

author: soFPG
author_rank: Frequent Contributor
timestamp: December 08, 2019, 12:20:22 am
content: I am wondering what kind of applications would need so much flash but little to no SRAM.I would much rather like to see an external QSPI PSRAM interface instead of that stupid 128Mbit flash which no one is ever able to fill (besides with sprites but then I would probably go for another external flash which just contains that)

author: brucehoult
author_rank: Super Contributor
timestamp: December 08, 2019, 01:26:24 am
content: Quote from: soFPG on December 08, 2019, 12:20:22 amOh, that's about the board, not the SoC. I think it's just a matter of what flash chips were available. The original HiFive1 and 3rd party LoFive and LoFive R1 use 128 Mbit flash, but the current HiFive1 rev B reduced that to 32 Mbit (4 MB), and the SiFive Learn Inventor has 4 Mbit (512 KB) -- and 64 KB of SRAM.Building a board yourself at home is certainly something a lot of people can do themselves, and the FE310 MCU is available at retail (qty 5 for $25).

author: brucehoult
author_rank: Super Contributor
timestamp: December 08, 2019, 01:30:10 am
content: Quote from: pallav.aggarwal@gmail.com on December 07, 2019, 04:20:26 pmOops, I missed that part.FreeRTOS is the standard software for the new SiFive Learn Inventor which uses another iteration of the same FE310 SoC, and it is also Amazon AWS certified.https://shop.pimoroni.com/products/sifive-inventorhttps://www.prnewswire.com/news-releases/sifive-learn-inventor-development-system-now-aws-qualified-300968135.html

author: ehughes
author_rank: Frequent Contributor
timestamp: December 08, 2019, 05:01:25 am
content: For the semi custom option with Sifive,. Are we talking 100k unit runs? 10k? At what QTY does the price match COTS MCUs of a similar capability?

author: brucehoult
author_rank: Super Contributor
timestamp: December 08, 2019, 06:25:55 am
content: Quote from: ehughes on December 08, 2019, 05:01:25 amYou'd have to talk to sales@sifive.com to get exact costs. I don't think you'd ever do it because it was *cheaper*, unless you're talking pretty large quantities and the savings come from avoiding distribution chain markups.If you go for full-reticle production then the marginal cost per chip should be lower right from the first wafer of chips (typically something like 1000 to 5000, depending on chip die size and wafer size). You're looking under $1 a chip for something like the FE310 -- maybe even $0.10. At some point the ~$0.20 cost of putting the chips into packages starts to dominate...The question is how many chips *you'd* feel you'd need to amortize the NRE costs over to make it worth your while.According to this three year old article, getting a mask set made for 180nm costs around $100k. That would have been what I've said if you'd just asked me, but it may be less by now. Older processes such as 350nm may be less.https://anysilicon.com/semiconductor-wafer-mask-costs/SiFive's FE310-G000 and FE310-G002 are made in 180nm and run at up to 320 MHz (they *all* run that fast -- some do 400). If you don't need 320 MHz then you could use a cheaper and older process: 250nm, 350nm, 500nm (originally and maybe still called 0.35um and 0.5um) I think 0.5um is the largest TSMC still does, but others may still do larger. I don't know how much cheaper the mask set costs get with the older process nodes.So let's say you're looking at FAB NRE costs of $100k, so you spread that over however many chips you make. If you're making under 100k chips then probably this costs more than the actual cost of the chips. But maybe getting exactly the right chip for your purpose is worth paying $10 or $20 each -- only you can know that.Note that you don't have to make them all at one time. Once the FAB has the masks they keep them in storage and you can order I think just one wafer worth of chips at a time whenever you want.Then you need to add SiFive's NRE costs. We're trying to automate that as much as possible to bring the price down, especially for minor variations on things we've made before, but aren't there yet. Call that another low six figures, or a dollar or two per chip if you're making 100k. We want to drive this part of the costs down by an order of magnitude over the next few years but aren't there yet.If you want a million chips or ten million ships then the per chip NRE costs start to disappear anyway.If you want only a small number of chips then using Multi-Project-Wafer services is useful. This lets you share the mask making costs with 5 or 10 or 20 other customers, but the flip side is that you get only about 40 to 100 chips per wafer processed (for 200mm wafers and 300mm wafers respectively). This brings your total cost from the FAB down to maybe around $20k or $30k for that minimum order of 40 or 100 chips, so that's maybe $30 to $50 per chip. Again, if you have the FAB run multiple wafers using those same masks then the additional chips.The current FE310-G000 and FE310-G002 chips on the HIFive1 and LoFive are made using repeat runs of the same Multi-Project masks. We're selling the chips for $5 each and Crowd Supply take a significant cut. I'd expect we're covering our FAB costs on those no problem.

author: mac.6
author_rank: Regular Contributor
timestamp: December 08, 2019, 09:06:16 am
content: Last price I seen was about 5k$ per mask for a 90nm process (short run of one wafer). But this price was maybe be lowered by the global volume order at the foundry.

author: tszaboo
author_rank: Super Contributor
timestamp: December 08, 2019, 10:26:01 am
content: Quote from: brucehoult on December 07, 2019, 08:05:29 pmMy latest projects are always with some sort of Wireless Gecko microcontroller (ERF32), and the smallest RAM you get is 64K, but typically 256K. Considering that it is a lot faster to excecute from it, and this micro is running at 300MHz, how much time will it spend waiting for the instructions to fetch from the Flash?

author: brucehoult
author_rank: Super Contributor
timestamp: December 08, 2019, 11:09:36 am
content: Quote from: NANDBlog on December 08, 2019, 10:26:01 amThere is 16 KB of instruction cache, so that depends on your code. Most real programs -- especially MCU programs -- get quite good instruction cache hit rates with 16 KB. I'd say CoreMark has an unusually large hot section, and it fits and gets 2.75 coremark/MHz.

author: OwO
author_rank: Super Contributor
timestamp: December 08, 2019, 12:34:37 pm
content: Yeah 16KB is kind ofreally tinykind of on the small side, and is less than what the cheap STM32F103C8T6 that I use for really low end stuff has. Example application: NanoVNA with GUI: the measured data array + calibration data alone takes 12KB of memory (201 frequency points * (2 measured channels + 6 calibration values) * 2 floats per complex value * 4 bytes per float). This really can not be reduced without sacrificing functionality. Add in all the UI stuff and DMA buffers (ADC, USB transmit buffer, LCD SPI transmit buffer/drawing buffer, etc) and with a LOT of optimization (skimping on data types) you still need >32KB. The MCU I'm using has 48KB of memory and the budget for such a MCU is around $1. It's VERY hard to beat STM32/GD32 on price so I think there is room for mid- or higher end offerings, like for example the Kendryte K210 which sells for $6 @ 5pcs and has 8MB (!!) of SRAM.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 08, 2019, 04:55:07 pm
content: Yeah, I already made remarks about the RAM size of the typical off-the-shelf FE310 a while ago. But as Bruce told you, you can customize them as you see fit (of course it's probably not for the hobbyist!) The whole business model of SiFive revolves around that AFAIK, and it makes sense. It would probably be a lost cause for them if they focused on off-the-shelf parts that would be meant to compete with the big ones. If they did that, Bruce would probably end up as bitter as treez.

author: ehughes
author_rank: Frequent Contributor
timestamp: December 09, 2019, 07:40:30 pm
content: Thanks. I find the model interesting for sure. The ability to customize does sound interesting. For me cost isn't the main issue. For lower volume industrial products, a chip that is 3x price is OK. Longevity is the key.I may have to kick the tires...