Nonminimum Phase Zero - Page 1
Forum section: electronics / projects

author: aep9690
author_rank: Regular Contributor
timestamp: September 12, 2013, 02:03:52 am
content: Can someone explain to me why a nonminimum phase zero is a bad thing? Everything I read says things along the lines of "... undesirable nonminimum phase zero..." and I can't figure out why exactly this is bad.I know it can lead to lack luster performance of the system but I haven't read anywhere why this is.Thanks

author: w2aew
author_rank: Super Contributor
timestamp: September 12, 2013, 02:13:08 am
content: Quote from: aep9690 on September 12, 2013, 02:03:52 amI've been a 'EE for almost 30 years, and never heard that phrase. So, on the face of it, it makes no sense to me. Can you provide more context?

author: HackedFridgeMagnet
author_rank: Super Contributor
timestamp: September 12, 2013, 02:34:08 am
content: Is it something to do withhttp://en.wikipedia.org/wiki/Minimum_phase#Non-minimum_phase

author: aep9690
author_rank: Regular Contributor
timestamp: September 12, 2013, 03:06:45 am
content: I did see the Wikipedia article on it, I suppose the phase delay would slow the system down but I was hoping for something more in depth than that.

author: Kremmen
author_rank: Super Contributor
timestamp: September 12, 2013, 06:22:22 am
content: Quote from: aep9690 on September 12, 2013, 02:03:52 amThis is the dreaded right half plane zero. The math tractation would be a bit cumbersome to enter here, but read the wikipedia already linked. I will try to explain in easy terms.Think of the familiar Bode plot. This is a graphical frequency domain representation of the poles and zeros of the system transfer function. In a "normal" stable system the poles and zeros are in the left half plane of the complex Laplace space (or inside the z-space unit circle in discrete time systems) . As the system parameters vary, the poles and zeros move, creating what is called the root locus of the characteristic equation (the solutions of which these poles and zeros are). As long as all poles stay in the left half plane, we have an essentially stable system.But back to the Bode plot.A pole expresses itself as a downward sloping corner in the amplitude plot, at the frequency of the pole. A single pole angles the plot down at 20 dB/decade from the pole frequency, at the same time lagging the phase response by 90 degrees. The phase lag plot is an exponential curve starting from negative infinity (on the log plot) and reaching -90 degrees in positive infinity, but already 45 degrees behind at the pole frequency. (With pen & paper this is approximated using straight lines: level at 0 degrees from - inf until 1 decade below corner -> slope -90 degrees by 1 decade over corner -> level at -90 deg to +inf).A zero works the opposite way, causing an upward angle; increasing gain at 20 dB/decade from the zero frequency, while advancing the phase by 90 degrees similar to the pole, but the other direction.The above is normal behavior and manageable. If you think of the Bode stability criterion you can see why: A system is stable if the loop phase lag is less than 180 degrees at the point where the loop gain descends below 0dB. In other words, if the feedback stays negative in the range where it is amplified, the system is stable. There are other more advanced criteria for stability, but this suffices for now. We can move poles and zeros by changing circuit parameters (R, C and L values) to juggle the plot so that stability is achieved, or if not we can introduce new poles and zeros judiciously to achieve stabilization.Enter the right half plane zero. This bugger works like a zero regarding gain, i.e. the gain will increase 20 dB/decade from the zero frequency upwards, BUT the phase acts like the phase of a pole, i.e. lagging 90 degrees, and is 45 degrees behind at the zero frequency. Compare this to the above rule of stability, and you will spot an issue. The gain is going up while the phase is lagging - not good. There is no simple way to associate such a zero with certain components of the circuit, as we can do with left side poles and zeros. It is often (always?) associated with a concept called group delay and the zero rises from the topology of the circuit, not from any individual components.This is the definition. What you can do about it is a completely different thing. Normal stabilization methods are usually marginally effective at best, and result in systems with very lazy dynamics. That's why this condition is so dreaded. This situation is built in to certain circuit topologies and avoidance is normally to change the topology. If that won't work then good luck.

author: aep9690
author_rank: Regular Contributor
timestamp: September 13, 2013, 01:08:14 am
content: Thanks a lot for the explanation, I knew all the stuff about the bode plot and stability but I didn't know that the right hand zero provided phase lag.