How to test PLD chips - Page 1
Forum section: electronics / projects

author: daisizhou
author_rank: Super Contributor
timestamp: October 28, 2023, 06:03:02 am
content: Hi every one.In my spare time, I plan to make a circuit,The original author's circuit is composed of a 22V10 chip,I have obtained its firmware, but I am unable to determine whether the firmware design is consistent with the schematic diagram.I want to know if there is a way to test the 22v10 chip,Is the internal code consistent with the physical circuit diagram.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: October 28, 2023, 07:05:41 am
content: Quote from: daisizhou on October 28, 2023, 06:03:02 amIf you have the source, just reading that can check the pin mapping and eqns.If you have .JED file, there is a (very) old PGM called JED2EQN that can turn PAL jed files into boolean equations.If you have just the programmed and secured chip, you can use a universal programmer to run vector testing, on an iterative basis.

author: daisizhou
author_rank: Super Contributor
timestamp: October 28, 2023, 01:25:10 pm
content: Thanks.I have obtained the firmware. I am a beginner in PLD. Can you help me?I cannot confirm that the schematic and the firmware read are consistent,Because the schematic is the initial version and the firmware has been upgraded

author: PCB.Wiz
author_rank: Super Contributor
timestamp: October 28, 2023, 11:18:36 pm
content: What form is your firmware in ? Do you not have a .JED file, or boolean equations file ?The image has red dots, but they do not all make sense.

author: daisizhou
author_rank: Super Contributor
timestamp: October 29, 2023, 12:09:54 am
content: The firmware is in the. jed file format.It is in the attachment of the above post (PAL22V10Z_V2.0. zip).The 22v10 logic diagram was completed with the assistance of a friend, but I cannot analyze it,I am not good at logical analysis.The following attachment is the complete manual, 22v10 on page 57, in the upper left corner

author: PCB.Wiz
author_rank: Super Contributor
timestamp: October 29, 2023, 09:04:36 am
content: Quote from: daisizhou on October 29, 2023, 12:09:54 amDid you search for JED2EQN.exe and run that on your JED file ?

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 29, 2023, 09:39:08 am
content: Quote from: PCB.Wiz on October 29, 2023, 09:04:36 amI guess its's the continuation of this:https://www.eevblog.com/forum/microcontrollers/help-who-can-reverse-compile-27c1001-firmware-internally-i-encountered-difficu/msg5050921/#msg5050921And this:https://www.eevblog.com/forum/microcontrollers/help-who-can-reverse-compile-27c1001-firmware-internally-i-encountered-difficu/msg5050942/#msg5050942He got the equations and videos explaining how to interpret .jed files.How to test PLDs? PLDs are OTP only, so you can't put a test program to check every gate.So, the only way is to program and test them in the real hardware or some kind of testing platform which ensures the PLDs I/O pins behave as expected.

author: daisizhou
author_rank: Super Contributor
timestamp: October 29, 2023, 09:46:30 am
content: I have not downloaded or used JED2EQN.exe.I spent a long time, but I couldn't figure out how to test this PLD chip

author: daisizhou
author_rank: Super Contributor
timestamp: October 29, 2023, 09:47:52 am
content: Thanks.Yes, I have been hoping to test it, but there has been no progress

author: daisizhou
author_rank: Super Contributor
timestamp: October 30, 2023, 01:06:42 am
content: I have searched for the LCD display module signal and am not sure if it will be helpful for analysis

author: PCB.Wiz
author_rank: Super Contributor
timestamp: October 30, 2023, 05:33:26 am
content: Quote from: daisizhou on October 30, 2023, 01:06:42 amYou will need the signal names and what they drive, if you hope to reverse engineer this.As the info above in #2 suggested, the JED file you have is strange, and largely gibberish.You may be better to try to find a better/less corrupted JED copy, or a version that is close to this model.Do you have a working PLD ?The JED2EQN result attached confirms what the repeated dots suggested in #2 - for some reason, this PLD has multiple copies of the same equation burnt into many product terms.It does suggest only Pin18 is registered to the pin1 CLK, all others are combinational.Some equations you can simplify, and extract something plausibleThe simple ones :f23 = i2 * i10f16 = f22 * f14f20 = /i1 * /f23 * /i2 * /f22 * /i9 * /f15 * /i10 * /f14but others make no sensef22 = vcc+ i1 * /i1 * f23 * /f23 * i2 * /i2 * f22 * /f22 * i3 * /i3 * f21 * /f21 * i4 * /i4 * f20 (etc)That combines Sig and !Sig, which always reduces to FALSE. ie The JED is corrupt.If you have a known good device, but secured, you can plug it into a device programmer and run manually generated test vectors.Start with the 3 pins above that do not look like nonsense, and verify those work, then expand. Expect it to take a few hours.