Is my FPGA Decoupling enough? - Page 1
Forum section: electronics / general

author: MattHollands
author_rank: Frequent Contributor
timestamp: September 10, 2017, 07:57:49 pm
content: Hi,I am doing my first ever FPGA PCB layout and I am using a Lattice MachXO LCMXO1200C part and I want to check my decoupling capacitors are ok. Nothing on the board should be operating above 51MHz.All of the caps are 0603 size, and I have one 0.1uF cap per pin. I've tried to get the caps as close as possible to the pins. There is a 4.7uF and a 0.1uF on the power supply. All VCC pins are on the same rail.I know it's generally a good idea to use two caps of different size per pin but I don't think I can really fit that in using 0603. Ideally I don't want to go down to 0402 or smaller as I've never soldered that small, but I guess that's possible if necessary. I could also make some of them 0.1uF and some 0.01uF etc.I don't expect anyone to guarantee that this will work, but given that it isn't very high speed I was wondering if it looks likely to be fine?I've included pictures of the layout. Capacitors are yellow, VCCs are red and GNDs are green.Cheers!

author: Ice-Tea
author_rank: Super Contributor
timestamp: September 10, 2017, 08:10:09 pm
content: Lattice has a document on this:www.latticesemi.com/view_document?document_id=8374You're not too far off I supposeRegarding your layout (and just looking at the 3V3 portion): it would seem it's coming from the bottom right of your board? Those tracks look pretty thin to me.. I'd put something a lot beefier. And it looks like you don't havetoomuch going on beneath that TQFP so it would make sense to flood it with 3V3 where possible...

author: nctnico
author_rank: Super Contributor
timestamp: September 10, 2017, 08:12:30 pm
content: I agree. On two layer designs I have a solid 3.3V (or whatever voltage) copper pour on the top layer and a solid ground plane on the bottom layer for a chip in a QFP package.

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: September 10, 2017, 08:45:29 pm
content: Just do a copper pour on 3.3V and it should look a lot better. Remember that thicker traces have lower inductance, so they raise the effective resonant frequency of the decoupling caps.QuoteAt 51MHz a bunch of 100nFs with a single bulk 4.7uF should be fine. You could go a bit smaller than 100nF but the improvement will probably be marginal.

author: ale500
author_rank: Frequent Contributor
timestamp: September 11, 2017, 12:27:55 pm
content: I'm curious about your FPGA choice, I see that MachXO2 parts tend to be a bit cheaper and have a larger amount of block RAM. Why did you choose a MachXO part ?

author: suicidaleggroll
author_rank: Super Contributor
timestamp: September 11, 2017, 05:38:36 pm
content: The decoupling looks fine, but there are some other issues. I don't like the single tiny power trace that's daisy-chaining the entire FPGA. That trace should be much larger and IMO it should go beneath the FPGA and then fan out to all of the power pins in parallel instead of hopping down the chain (or use a copper pour). Also on the left side of your layout you have a signal labeled CLK100MHZ, which presumably is a 100 MHz clock, and you have your little 3.3V power line cutting perpendicular to it on the ground plane below, cutting off its return path.Remember, current does not follow the path of least resistance. It follows all paths, but it's biased toward the path of least IMPEDANCE. For DC that means a straight line, but for high frequency AC that often means whatever path minimizes loop area to keep inductance low. At 100 MHz, the return current is going to be flowing on the ground plane directly underneath your source trace. When you run another trace across this, you cut the return path off, and you force it to take a large loop around the break. This increases loop area significantly, and can cause problems from signal integrity issues to EMI.

author: MattHollands
author_rank: Frequent Contributor
timestamp: September 11, 2017, 11:46:36 pm
content: On the top side I've put a 3V3 fill in around the FPGA (top half of the PCB) and a GND fill on the bottom half (see first attachment). Am I going to face issues of traces passing from one fill to the next? (The only traces that pass from one to the other are the busses between the two big chips).Quote from: suicidaleggroll on September 11, 2017, 05:38:36 pmThe trace coming out the top of the chip actually only goes to a debug header so it shouldn't matter that the return path is broken I think. The oscillator that is providing the 100MHz is under the FPGA. Nonetheless, I have brought the oscillator closer to the FPGA pin and ensured a straight loop on the top side and back on the bottom side. Is this ok? (see second attachment)Quote from: ale500 on September 11, 2017, 12:27:55 pmI wanted to use a Lattice part as I have used them before and don't need an expensive programmer to program them. I had a basic RAM and IO requirement and this was the cheapest part on Digikey that satisfied that need.

author: Gribo
author_rank: Frequent Contributor
timestamp: September 12, 2017, 12:31:54 pm
content: Your 100MHz clock goes somewhere off the picture. Is it a test point? If so, you might want to place it as near as possible to the clock source.

author: MattHollands
author_rank: Frequent Contributor
timestamp: September 12, 2017, 02:49:39 pm
content: Quote from: Gribo on September 12, 2017, 12:31:54 pmIt goes to a pin header. When I want to check signal integrity I will measure it at the FPGA, not on the header. The header is just for debugging purposes and I don't really care about the SI at the header - its presence shouldn't cause an issue with SI at the FPGA should it?

author: stmdude
author_rank: Frequent Contributor
timestamp: September 12, 2017, 05:34:02 pm
content: Quote from: MattHollands on September 12, 2017, 02:49:39 pmThat's nifty. You should be able to listen to your 100MHz clock on a regular radio since you added an antenna..Seriously though, and disregarding EMI, is it an oscillator or a crystal? If it's a crystal, you might be placing a bit more capacitive load on it than it can handle.Also, is this a 100MHz clock _into_ the FPGA? If so, why? 100MHz gets kind of sensitive, and a PLLed 25MHz clock usually works for most things you'd want to do.

author: MattHollands
author_rank: Frequent Contributor
timestamp: September 12, 2017, 07:36:52 pm
content: Quote from: stmdude on September 12, 2017, 05:34:02 pmIt's an oscillator rather than a crystal. I haven't actually decided exactly what frequency it will be, but I will probably be something like 10 or 25MHz and PLL up to 100MHz. I will remove the pin header, as I don't really need it, and if I need to output the clock I can just do that via one of the FPGA GPIOs. Attachment shows clock no longer goes to the pin header. Instead the pin header has been routed to pin 37 which is a GPIO.

author: rs20
author_rank: Super Contributor
timestamp: September 13, 2017, 08:23:09 am
content: Is it just me, or have you taken the instruction of putting the capacitors "as close as possible" a little bit too far to the extreme? I mean, you're going to give yourself a comparitively difficult time with the caps on the opposite side of the board as the IC; and the inductance of the vias will probably be worse than some simple traces to nearby caps on the same side of the board?

author: MattHollands
author_rank: Frequent Contributor
timestamp: September 13, 2017, 01:57:50 pm
content: Quote from: rs20 on September 13, 2017, 08:23:09 amI've seen tons of FPGA boards with decoupling caps on the bottom side. It saves space to hide them away there.Seeing as the ground return path is on the bottom side of the board anyway, the loop size is the same because we would need a via to get to ground anyway?

author: rs20
author_rank: Super Contributor
timestamp: September 13, 2017, 02:32:25 pm
content: Quote from: MattHollands on September 13, 2017, 01:57:50 pmDecoupling caps on the bottom of a BGA FPGA board, absolutely, and basically demanded in the datasheets. Decoupling caps on the bottom of aTQFPFPGA board? Not in my experience.You raise a good point about the loop. My main concern of the added bother of double-sided assembly would still put me off thought. Up to you, though, of course.

author: stmdude
author_rank: Frequent Contributor
timestamp: September 13, 2017, 02:49:34 pm
content: Quote from: rs20 on September 13, 2017, 02:32:25 pmMeh, I did the same thing when I started out. There's nothing _wrong_ with it. I did however change my ways when I wanted to get some boards assembled for me, and saw the price-difference for SMA with components on one side vs. both sides of the board...

author: MattHollands
author_rank: Frequent Contributor
timestamp: September 13, 2017, 03:04:17 pm
content: Quote from: rs20 on September 13, 2017, 02:32:25 pmYep, if I wasn't hand assembling I would probably stick to one side.

author: marshallh
author_rank: Unknown
timestamp: September 14, 2017, 12:11:04 am
content: Will it work perfectly? Yes.Could you also improve on it? Yes.

author: MattHollands
author_rank: Frequent Contributor
timestamp: September 14, 2017, 01:08:54 am
content: Quote from: marshallh on September 14, 2017, 12:11:04 amI'm here to learn! If you had time to drop me some pointers I would be more than happy to hear (/read) it.