Another Stupid Question - Page 1
Forum section: electronics / beginners

author: IntegratedValve
author_rank: Regular Contributor
timestamp: January 17, 2014, 08:05:48 pm
content: My question for today regarding JK flip-flops. When setting both J and K to be (1, 1) the output should be complement of previous output Q. It works for one flow of states but then as soon as the output is complemented it will feedback to the input gates and destabilize the successive output states until J and K are set to something different.As I understand flip-flops change state upon clock transition edge trigger. But is this transition period short enough so that after the Q output changes there will be not time for the feedback circuit to change the output again?Does JK flip-flop when (J, K) = (1, 1) keeps complement the output Q on every edge trigger resulting in alternating output 1, 0, 1, 0, 1, 0, 1, ...?

author: grumpydoc
author_rank: Super Contributor
timestamp: January 17, 2014, 08:16:53 pm
content: QuoteYes that's the way it works.Well, not every edge, just either the positive ones or negative ones depending on the implementation.

author: IanB
author_rank: Super Contributor
timestamp: January 17, 2014, 09:41:34 pm
content: From Wikipedia:MetastabilityFlip-flops are subject to a problem called metastability, which can happen when two inputs, such as data and clock or clock and reset, are changing at about the same time. When the order is not clear, within appropriate timing constraints, the result is that the output may behave unpredictably, taking many times longer than normal to settle to one state or the other, or even oscillating several times before settling. Theoretically, the time to settle down is not bounded. In a computer system, this metastability can cause corruption of data or a program crash, if the state is not stable before another circuit uses its value; in particular, if two different logical paths use the output of a flip-flop, one path can interpret it as a 0 and the other as a 1 when it has not resolved to stable state, putting the machine into an inconsistent state.So be careful of your timing if you want predictable results...

author: IntegratedValve
author_rank: Regular Contributor
timestamp: January 17, 2014, 10:49:27 pm
content: But then how does JK FF stabilize itself when J=1 and K=1? I mean it's not oscillating unpredictably at positive/xor negative edge trigger, is it? Or the transition time is short enough to only allow output to complement before feedback circuit does nasty things? Then how to calc this time period of the edge transition pulse?

author: IanB
author_rank: Super Contributor
timestamp: January 17, 2014, 10:55:07 pm
content: Quote from: IntegratedValve on January 17, 2014, 10:49:27 pmSet J to 1. Wait an appropriate time period for the circuit to settle. Set K to 1. Wait an appropriate period for the circuit to settle. Examine the output.Do not try to change the state of J and K from 0 to 1 both at the same time.

author: IntegratedValve
author_rank: Regular Contributor
timestamp: January 17, 2014, 10:57:00 pm
content: I tried several times, it's not stable.

author: IanB
author_rank: Super Contributor
timestamp: January 17, 2014, 10:58:20 pm
content: What's not stable?You would have to post a circuit and an implementation.Are you clocking your pulses? What clock frequency are you using?

author: IntegratedValve
author_rank: Regular Contributor
timestamp: January 17, 2014, 11:09:23 pm
content: Quote from: IanB on January 17, 2014, 10:58:20 pmPen and paper. No real circuit or simulation.

author: IanB
author_rank: Super Contributor
timestamp: January 17, 2014, 11:20:16 pm
content: Quote from: IntegratedValve on January 17, 2014, 11:09:23 pmMaybe this will help:http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/jkflipflop.htmlIf you don't have an enabling clock input then the output will oscillate indefinitely for as long as both J and K remain 1.

author: grumpydoc
author_rank: Super Contributor
timestamp: January 17, 2014, 11:26:06 pm
content: QuoteJ&K only affect the output after a clock transition so you should be able to set both together. You just need to ensure they are not changing at the same time as the clock edge. There is, or should be, a "set-up" time in the datasheet of the J-K that you're using. For the 74LS76A it's 0ns (i.e OK as long as they don't all change together).QuoteErr, no.

author: IanB
author_rank: Super Contributor
timestamp: January 17, 2014, 11:29:05 pm
content: Quote from: grumpydoc on January 17, 2014, 11:26:06 pmThis is a pen and paper simulation. If you solve the circuit with J, K and Q all at 1, then Q will transition to 0. If you now solve the circuit again with J, K = 1, Q = 0, then Q will switch back to 1. Q will keep switching each time you solve the circuit.

author: IanB
author_rank: Super Contributor
timestamp: January 17, 2014, 11:31:46 pm
content: Quote from: grumpydoc on January 17, 2014, 11:26:06 pmI see that after further reading. Unless you derive an implied clock from the rising edge of J or K, such that the circuit only changes state when a rising edge occurs on one of the inputs? (No idea if any physical realizations do this.)

author: grumpydoc
author_rank: Super Contributor
timestamp: January 17, 2014, 11:53:51 pm
content: QuoteAh, I see where you're coming from.Are you looking at one of the master-slave equivalent circuits or the "4 nand" one.EDIT: Sorry - single malt is nice but not good for concentrationThe "4 nand" equivalent circuit is not all that useful because it needs the clock input to be a short positive going pulse to work - ie, it's not truly edge triggered and misbehaves when the clock input is high, as you have worked out. With the clock low no change on J or K will propagate to the output. You could make a useful flip-flop by running the clock through a differentiator (i.e small cap) to ensure that you just got a pulse corresponding to the edge.

author: IanB
author_rank: Super Contributor
timestamp: January 18, 2014, 02:10:43 am
content: I just set a truth table up in Excel which seems to work out fine as below, using the formula:Qnext= (J and not Q) or (not K and Q)I have not really gone through the exercise of converting this to just NAND gates and reducing it down to the minimum number.