24ch 16bit Variable PWM frequency Drivers - Page 1
Forum section: electronics / projects

author: 24602
author_rank: Contributor
timestamp: April 13, 2024, 03:28:39 pm
content: Hi AllBeen looking for a while, need a IC that can do 16bit (or similar fine resolution) that can have a variable PWM frequency (doesn't have to be full 16bit over the frequency range). Ideally 77hz to 25khz. Something like the TLC59711 but with variable PWM frequency would be greatNeed 24channels in this design case.The option I'm probably going to go with is two microcontrollers with a SPI/I2C connection or similar between them.Thanks!

author: Kleinstein
author_rank: Super Contributor
timestamp: April 13, 2024, 04:09:54 pm
content: The RP2040 may be able to get 24 PWM channels. It has 2 x 8 dedicated PWM channels and than programmable IO to add more. I don't know if programmable IOs can get high resolution thought.

author: Miyuki
author_rank: Frequent Contributor
timestamp: April 13, 2024, 04:57:20 pm
content: Just do it from software on any MCU, target frequencies are low.Way more flexible and probably cheaper than a dedicated chip.

author: langwadt
author_rank: Super Contributor
timestamp: April 13, 2024, 05:01:43 pm
content: Quote from: Miyuki on April 13, 2024, 04:57:20 pmeven at 77Hz 16bit is 5MHz, good luck doing that in software

author: RoGeorge
author_rank: Super Contributor
timestamp: April 13, 2024, 05:13:16 pm
content: Try PDM instead of PWM. Any microcontroller with enough pins should do, with whatever resolution you need. A demo with PDM on each pin of a MSP430G2211:https://hackaday.io/project/6356-delta-sigma-versus-pwm

author: xvr
author_rank: Frequent Contributor
timestamp: April 13, 2024, 06:30:46 pm
content: Any low end FPGA

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 13, 2024, 07:15:06 pm
content: Quote from: 24602 on April 13, 2024, 03:28:39 pmThe Parallax P2 (P2X8C4M64P) has 64 io and PWM on every pin, can easily do that. > 180MHz sysclk

author: Miyuki
author_rank: Frequent Contributor
timestamp: April 13, 2024, 07:58:10 pm
content: Quote from: langwadt on April 13, 2024, 05:01:43 pmEven if you count software it is easy, just increase and compare = 2 instructions. So even this can go like 100 MHz on modern MCU relatively easyWith the HW counter just set it to the next trigger value, they can run really fast. And just toggle the pin in an interrupt or some event system if available

author: langwadt
author_rank: Super Contributor
timestamp: April 13, 2024, 08:06:04 pm
content: Quote from: Miyuki on April 13, 2024, 07:58:10 pmat +5MHz for 24 pins ?

author: RoGeorge
author_rank: Super Contributor
timestamp: April 13, 2024, 08:13:50 pm
content: Software PDM (Pulse Density Modulation) only consumes 5 clock cycles per pin (plus entering and exiting from interrupt (once for all pins), can be very fast, faster than even the hardware PWM.That's all the code to calculate 1 pin of software PDM:Code:// Sigma delta modulation algorithm using "synthetic division"sum += req;// Update integrator valueif (sum < max)outBits++;// LSB = 1elsesum -= max;// LSB = 0 (untached) and adjust integratorhttps://github.com/RoGeorge/Delta-Sigma_versus_PWM

author: xvr
author_rank: Frequent Contributor
timestamp: April 13, 2024, 08:46:27 pm
content: > Software PDM (Pulse Density Modulation) only consumes 5 clock cycles per pin5 x 24 pin = 120 ticks. With 5 MHz for PDM carrier CPU should run at 120*5 = 600 MHz and processing ONLY interruptsGood luckPS. Again: consider FPGAICE40LP384-SG32 - $2.22 on Digikey. You will need 2 pcs (not enough pins and triggers in one). QFN

author: BrianHG
author_rank: Super Contributor
timestamp: April 14, 2024, 01:02:53 am
content: Use multiple slave MCUs running in parallel from a master slave clock.All the master MCU should be doing is feeding the slaves via a high speed parallel or serial port depending on your refresh requirements.If you were to use a FPGA, then your com control feeding the FPGA would be identical to the multiple slave MCUs, so planning along this line can give you multiple outs.Only go FPGA if you want to spend something like 25$ on a MAX10fpga, or use a cheaper FPGA with a bootprom and multiple power supplies for the core VCCint while learning to use a HDL and a complete dev environment toolchain and purchase programming hardware.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 14, 2024, 04:53:22 am
content: Quote from: 24602 on April 13, 2024, 03:28:39 pmThere is also the stc8g2k64, which offers up to 45 channels of PWM.

author: MarkT
author_rank: Frequent Contributor
timestamp: April 14, 2024, 07:38:02 am
content: Quote from: 24602 on April 13, 2024, 03:28:39 pmEven at the lowest of those frequencies, 16 bit at 25kHz implies a clock rate of more than 1.5GHz....Perhaps explain what you are trying to actually achieve, there may be a better approach.

author: Miyuki
author_rank: Frequent Contributor
timestamp: April 14, 2024, 08:04:31 am
content: Quote from: langwadt on April 13, 2024, 08:06:04 pmThere is only one counter but with 25 trigger pointsAnd you need to compare just to the next trigger valueIt can serve hundreds of outputs without any added complexity

author: mino-fm
author_rank: Regular Contributor
timestamp: April 14, 2024, 09:13:49 am
content: Quote from: Kleinstein on April 13, 2024, 04:09:54 pmI think this will work fast enough. Otherwise you can take two RP2040.Using PDM? Concerning pulsewidth risetime and falltime won't be identical. So 50% digital signal output will not result into 50% analog output.PWM has only one +edge and one -edge per periode.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 14, 2024, 09:32:10 am
content: Quote from: Miyuki on April 14, 2024, 08:04:31 amSw systems are simple, but have cross-talk effects when waypoints are very close. Edges suffer jitter when the MCU simply cannot react fast enough.The OP has not returned so we do not know whta they are trying to do, or drive.All they said wasQuote77Hz is only ~5MHz, for 16b, so that is simple, a 36MHz clk is good up to roughly 550Hz at 16b PWM.25kHz is impractical to manage 16b, on a typical MCU, but they already said they are ok with less than 16b.The example 36MHz MCU can manage 10.5 bits at 25kHz and may be able to dither LSB for more bits.PLL's on PWMs are becoming more common on low cost MCUs, for 100MHz or 144MHz PWM clocks in 8b MCU

author: Miyuki
author_rank: Frequent Contributor
timestamp: April 14, 2024, 10:57:27 am
content: With now common cheap 32bit MCU with frequencies sometimes even over 200MHz, like many ARM and ESP32It is different than in times of lower tens of MHzBut I must agree, that it is a poorly specified problem, so it is hard to select an optimal solution

author: xvr
author_rank: Frequent Contributor
timestamp: April 14, 2024, 11:06:12 am
content: > Only go FPGA if you want to spend something like 25$ on a MAX10fpga,Lattice:ICE40LP384-SG32 - $2.22 on Digikey. 2 pcs needed. Package: QFN32 (a little tricky to hand soldering, but still possible).If you happy with BGA packages you can take ICE40LP1K-CM49 - $5.36 on Digikey. 1 pcs will be enoughGowin:GW1N-LV1LQ144C6/I5 - €8.16 on Mouser. Package LQFP-144.GW1N-UV1P5LQ100C6/I5 - €9.61 on Mouser. Support powering from single supply voltage> and multiple power supplies for the core VCCintYes. Lattice require 3 power supply (but they can be just simple LDO), Gowin - 2 power supply, or just 1 for UV series> while learning to use a HDL and a complete dev environment toolchainYes, but MCU also required dev environment. As for HDL - this design is a very simple, so no deep dive in Verilog required.> and purchase programming hardware.Lattice use SPI interface, Gowin - JTAG. So any JTAG adapter will suite for Gowin, and any, based on FTDI chip - for Lattice. Even ready made adapters (by China) is very cheap now.A couple lines of code for Verilog:Code:module top(input wire clk,input wire spi_clk,input wire spi_mosi,input wire spi_cs,input wire address,output wire [11:0] pwm);reg [15:0] counter = 0;reg [20:0] spi_data = 0;always @(posedge clk)if (counter == 16'hFFFE) counter <= 0;else counter <= counter + 1'b1;always @(posedge spi_clk) spi_data <= (spi_data << 1) | spi_mosi;wire spi_addtess = spi_data;wire [3:0] pwm_selector = spi_data[19:16];wire pwm_preset = spi_data[15:0];genvar i;generate for(i=0; i<12; i=i+1) beginpwm_module pm(.clk(clk), .pwm(counter), .out(pwm), .setup(pwm_preset), .setup_cs(spi_address == address && pwm_selector == i), .setup_clk(spi_cs));endendmodulemodule pwm_module(input wire clk,input wire [15:0] pwm,output wire out,input wire [15:0] setup,input wire setup_cs,input wire setup_clk);reg [15:0] pwm_preset = 0;reg out_ff = 0;assign out = out_ff;always @(posedge setup_clk)if (setup_cs) pwm_preset <= setup;qlways @(posedge clk)if (pwm == pwm_preset) out_ff <= 1'b0; elseif (pwm == 0) out_ff <= 1'b1;endmodulePS. Code was writen right here, some bugs/typos can be