Ultra fast DAC - Page 1
Forum section: electronics / projects

author: Leopoldo
author_rank: Contributor
timestamp: December 02, 2016, 10:47:54 pm
content: Hi,I'm working on a project for which I'd like to use a ultra high speed DAC, I'm talking about 1-1.2Gsps @8bit resolution or more. I don't really care about the interface (even though I think at that speed the only possible way to get the data in is LVDS and such, not even single ended parallel), but I'd like to find a cheap IC (somewhere around 10-15$).I was wondering: looking at certain DACs like this one:http://www.analog.com/media/en/technical-documentation/data-sheets/DAC10.pdfwhy there is no sps value? only the settling time...it's quite hard to figure out how fast I could push those boundariesI found a site where they said they drove it at 200MHz, but how did they now it could go that fast?Also, do you know where I could find the IC i'm looking for?To recap:- 1Gsps or higher- 8bit or higher- cheap (10-15$ top)If you really can't seem to find anything at 1Gsps, I could eventually slow it down to 500Msps, even though I'd rather not do so.Thank you all!

author: nctnico
author_rank: Super Contributor
timestamp: December 02, 2016, 10:59:14 pm
content: Make sure to look at how well the DAC behaves when it comes to output glitches!

author: danadak
author_rank: Super Contributor
timestamp: December 02, 2016, 11:12:18 pm
content: Here is a starting point -http://www.ti.com/lsds/ti/data-converters/high-speed-dac-greater-10msps-products.pageYou have a very challenging design, layout issues, data path......consider using their dev boardsas a way of getting a design working.Regards, Dana.

author: ebclr
author_rank: Super Contributor
timestamp: December 05, 2016, 04:06:47 am
content: 30 Buckshttp://www.ti.com/lit/ds/symlink/dac5681.pdfYou can try something passivehttp://www.allaboutcircuits.com/textbook/digital/chpt-13/r-2r-dac/

author: Leopoldo
author_rank: Contributor
timestamp: December 05, 2016, 07:53:40 pm
content: I thought about the R-2R DAC but it's worthless at those speeds...1Gsps is way too high, even tens of MHz could result in a bad performance.Thanks though, I also looked at the other IC you pointed out.But I'm now wondering instead:This chiphttp://www.ti.com/lit/ds/symlink/dac3151.pdf,even though it's clocked at a maximum of 500MHz (still pretty high, though), claims to have an internal FIFO, but why there is no information about the size or anything? Am I wrong, is it just a controller maybe?BTW, do FIFOs go that fast anyway?It would be very helpful if I could use a FIFO hooked up directly to the DAC and clocked at that impressive speed through a parallel multiplexing port to select the location in the memory! I really need that, and to be honest, I'm still searching for a RAM of some sort that can go that fast...so far I've only found RAMs that go roughly up to 100MHz.Thank you!

author: KE5FX
author_rank: Super Contributor
timestamp: December 05, 2016, 09:42:11 pm
content: What's the bandwidth of the signal you're actually generating? You may be able to use a much slower DAC in a higher Nyquist zone. This can work almost ridiculously well.

author: Leopoldo
author_rank: Contributor
timestamp: December 05, 2016, 11:12:36 pm
content: Quote from: KE5FX on December 05, 2016, 09:42:11 pmThanks KE5FX, I'm not that into that stuff....I only studied Nyquist for stability and outside of that all I know is that the sampling rate I have to keep is at least 2 times the output frequency. I would like to generate a (ridiculous) bandwidth of close to 0Hz - 500MHz, with a sampling rate of 1GHz. What do you mean by "higher Nyquist zone"?

author: tggzzz
author_rank: Super Contributor
timestamp: December 05, 2016, 11:19:49 pm
content: Quote from: Leopoldo on December 05, 2016, 11:12:36 pmNot quite. Two times thesignalbandwidth.That's the reason you can, for example, use a 10MS/s ADC to recover a 1MHz bandwidth signal superimposed on a 1GHz carrier.

author: Leopoldo
author_rank: Contributor
timestamp: December 05, 2016, 11:38:59 pm
content: Quote from: tggzzz on December 05, 2016, 11:19:49 pmRight, sorry, that's actually what I meantAnyone that can help me out?

author: langwadt
author_rank: Super Contributor
timestamp: December 05, 2016, 11:47:01 pm
content: Quote from: tggzzz on December 05, 2016, 11:19:49 pmcareful there, that assumes the front end and sampler can actually handle a 1GHz signalyou need to check the ADC's analog bandwidth

author: Zero999
author_rank: Super Contributor
timestamp: December 05, 2016, 11:52:54 pm
content: Quote from: langwadt on December 05, 2016, 11:47:01 pmIt can still be done with an ADC with a mere 2MHz bandwidth.The 1MHz bandwidth signal, superimposed on the 1GHz carrier can be separated using traditional analogue demodulation methods, before the ADC.In your case you haven't said what you're trying to do. For example, if your bandwidth is only 5MHz superimposed on a 500MHz carrier, then you don't need a 1G sample DAC, 10M sample will do fine.

author: Leopoldo
author_rank: Contributor
timestamp: December 06, 2016, 12:05:11 am
content: Guys, I think we're going a bit out of topic here...I was talking about DACs, not ADCs. When I talk about sampling I'm actually referring to the data sent to the DAC to get the analog value out of it (of course), which data comes from a memory that I've yet to find, since it's hard to find such a high speed memory.Basically, just keep in mind that I have to clock into the DAC data coming from a memory connected in parallel through an LVDS interface; all of this has to be clocked at >500MHz, possibly even at 1GHz if I can actually find a memory that can go that fast.Thank you.

author: nctnico
author_rank: Super Contributor
timestamp: December 06, 2016, 12:12:47 am
content: With these kind of speeds you are in FPGA territory. 16 bit wide DDR memory connected to an FPGA can easely transfer 1.3GB/s (bytes per second!) on a cheap Xilinx SParten 6 device. The high speed DACs others pointed to are also clearly intended to be driven by an FPGA. IMHO your project is doable if you know (or learn) how to do high speed digital designs and have a good logic analyser + oscilloscope to check the timing.

author: salbayeng
author_rank: Frequent Contributor
timestamp: December 06, 2016, 03:53:13 am
content: Did you look at these:http://au.mouser.com/Semiconductors/Data-Converter-ICs/Digital-to-Analog-Converters-DAC/_/N-4c44dZscv7?P=1z0w0s5Z1z0vywfZ1yxvlkxZ1yztou0Z1yxzfopZ1yzj1loZ1yztotzZ1yztotvZ1yztottZ1yztovlZ1yyhnulZ1yyhnup&Keyword=DAC&FS=True&Ns=Sampling%20Rate|1(that search is 8 to 10bits, and settle <+ 50nS)orhttp://au.mouser.com/Semiconductors/Data-Converter-ICs/Digital-to-Analog-Converters-DAC/_/N-4c44d?P=1z0w0s5Z1z0vywfZ1yrr994Z1yrswzlZ1yrsx0zZ1yrrbenZ1yzul22Z1yrswzxZ1yrsw9sZ1z0jw3eZ1yrhdiw&Keyword=DAC&Ns=Sampling+Rate%7c1&FS=Truesample rate > 180MSPS(the DAC10 doesn't appear in either list)If you look at say the AD9740 , it is clocked (unlike the DAC10) , the min setup and hold times are 2ns and 1.5ns , so you could get data input a little bit faster than 250MSPS. Provided you deskewed all your data bits and tweaked the clock skew. So 4 of those with 4 banks of DDR, and outputs summed.The DAC3152 is interesting , it is interleaved 2channels.The DAC3151 gets 500MSPS on a single channel , so you could get 2 of these and bolt the outputs together (current mode) and drive your 2banks of DDR and 2 DACs interleaved for 1MSPS. assuming you can get all the skews aligned.You can't actually write to your DDR as you will be flat out reading it. Might be OK for repetitive UWB or chirps.

author: coppice
author_rank: Super Contributor
timestamp: December 06, 2016, 05:48:01 am
content: Quote from: Leopoldo on December 05, 2016, 07:53:40 pmThe FIFO is just big enough to cover the latency due to deserialising the data. Figures 66 to 69 show the FIFO as being 8 samples deep for all devices in the family. The ability to synchronise the FIFO register pointers across multiple devices is described, so concurrent output can be achieved. What information about the FIFO do feel is missing? Why would you expect FIFOs to have a serious speed constraint? They should be able to run as fast as any other logic in the system.

author: ebclr
author_rank: Super Contributor
timestamp: December 06, 2016, 06:23:09 am
content: 166 Mhz ramhttp://www.cypress.com/file/183506/download

author: tggzzz
author_rank: Super Contributor
timestamp: December 06, 2016, 09:29:14 am
content: Quote from: coppice on December 06, 2016, 05:48:01 amFIFOs cannot alter latency nor mean bandwidth. All they can do is "absorb" peak bandwidth for a limited time, and reduce the peak bandwidth to the mean bandwidth.

author: nctnico
author_rank: Super Contributor
timestamp: December 06, 2016, 10:07:57 am
content: It seems the function of the FIFOs in the devices is to decouple the data source clock phase from the sample output clock phase. Both clocks may have different phases due to different data source path lengths and interleaving outputs.

author: tggzzz
author_rank: Super Contributor
timestamp: December 06, 2016, 10:47:01 am
content: Quote from: nctnico on December 06, 2016, 10:07:57 amMosty probably; that's a standard use of FIFOs, including inside large ICs and especially where clock domains are crossed.

author: coppice
author_rank: Super Contributor
timestamp: December 06, 2016, 11:01:34 am
content: Quote from: tggzzz on December 06, 2016, 09:29:14 amSo, you agree with what I said. What was the purpose of your posting?

author: coppice
author_rank: Super Contributor
timestamp: December 06, 2016, 11:07:06 am
content: Quote from: nctnico on December 06, 2016, 10:07:57 amThe FIFO has nothing to do with the phase of the clock. It is to do with the need to deserialise the input streams. The FIFO is just big enough to absorb enough working data to keep a steady flow of output samples while the next bunch is deserialised.

author: cowana
author_rank: Frequent Contributor
timestamp: December 06, 2016, 12:55:55 pm
content: Quote from: Leopoldo on December 02, 2016, 10:47:54 pmAt those speeds, JESD204B is likely to be the only option. There are plenty of 1GSPS+ DACs available (both AD and TI have a good selection).

author: Leopoldo
author_rank: Contributor
timestamp: December 06, 2016, 07:38:39 pm
content: Quote from: nctnico on December 06, 2016, 12:12:47 amThanks nctnico, but I have no experience in FPGAs. My plan was to use a microcontroller (yes, a simple micro) to send commands or set frequency via a SPI/I2C/parallel/etc. bus to the various ICs that then operate at those high frequencies; basically, every aspect of the main functionality is managed in hardware.Quote from: salbayeng on December 06, 2016, 03:53:13 amSalbayeng, that's actually something that I though about as well, but I was wondering: how do I sum the, say, 4 analog outputs and get the result that I want? Do I have to multiplex the adder in order to "listen" to each DAC individually or how am I supposed to do?Quote from: ebclr on December 06, 2016, 06:23:09 amThanks ebclr, but I need something that can go at least at 500MHz, even better if it can go up to 1GHz and beyond. If I find a way to put more rams in "parallel" I would certainly consider this option.Quote from: coppice on December 06, 2016, 05:48:01 amHi coppice, What do you mean by "deserialising the data" ?For what concernes the FIFO, I hoped I could use the FIFO as an internal RAM to clock data right inside the DAC, so that I could avoid external memories....but apparently I can't.Quote from: cowana on December 06, 2016, 12:55:55 pmYes, cowana, though if I could get away with an almost solely hardware-driven solution it would be even better, since I've never programmed FPGAs before

author: suicidaleggroll
author_rank: Super Contributor
timestamp: December 06, 2016, 07:59:25 pm
content: Quote from: Leopoldo on December 06, 2016, 07:38:39 pmHow do you expect a little MCU to transfer data at 1 GSPS to a DAC? It sounds like you're envisioning some kind of system where your MCU wouldn't be sending the actual data, it would be sending some high level command instead. If that's the case, ignore the MCU for now, it's irrelevant to this discussion. You need to focus on the interface to the DAC.Somethingneeds to drive it, and it can't be the MCU or a random block of RAM. You're well into FPGA territory, time to grab some dev boards and start experimenting.Maybe you should be looking at self-contained DDS chips instead of DACs? What kind of signals are you trying to generate?

author: Leopoldo
author_rank: Contributor
timestamp: December 06, 2016, 10:50:58 pm
content: Quote from: suicidaleggroll on December 06, 2016, 07:59:25 pmAs I explained, I'm obviously not expecting anything above 100s of KHz from a MCU.The MCU would only send commands to the clock generator connected to a counter, hooked up to a memory bank which is then connected to the DAC. That's why I don't need high speed computing (FPGAs).

author: dmills
author_rank: Super Contributor
timestamp: December 06, 2016, 11:13:00 pm
content: Some of the AD DDS chips have one die ram that can be loaded to allow them to run as an arbitrary waveform gen and can do Chirps and such internally in the hardware, IIRC they are available up to at least 2.5Ghz sample rate in 12 - 14 bits or so, and if you do not need to reprogram them quickly you can use a simple SPI link for configuration....Not exactly cheap, but one chip does it all, and you are not messing around with intermittent bugs due to clock skew mismatches at the 100 femto second level.Other then that an FPGA is pretty much the only way to fly, JESD204 (Which is sort of standard for high speed converters) has per lane data rates in the multi Gb/s region and need complex logic to synchronize and drive that is only really practical at chip scale.Regards, Dan.

author: JPortici
author_rank: Super Contributor
timestamp: December 06, 2016, 11:24:43 pm
content: Quote from: Leopoldo on December 06, 2016, 10:50:58 pmi think you'd prefer to have an FPGA so you don't actually have to go through the ordeal of designing a PCB that have to handle such high frequencies between millimeters of distance, as all the signal and clock paths are created for you inside

author: suicidaleggroll
author_rank: Super Contributor
timestamp: December 07, 2016, 01:23:45 am
content: Quote from: Leopoldo on December 06, 2016, 10:50:58 pmYes, you do. Your proposed approach of using discrete clock generators, counters, and RAM modules will never work at these speeds, you're about an order of magnitude past that point. It's going to have to be an FPGA with a very high speed interface (eg: JESD204), or you need to switch to a self-contained DDS chip rather than a discrete DAC and drive circuitry.

author: salbayeng
author_rank: Frequent Contributor
timestamp: December 07, 2016, 08:36:39 am
content: Just found the AD9106 , its a quad 180MSPS function gen with DDS with 4k words of memory. (AD9102 is single channel version)Does anyone know of any similar devices?

author: nctnico
author_rank: Super Contributor
timestamp: December 07, 2016, 09:54:53 am
content: Quote from: Leopoldo on December 06, 2016, 07:38:39 pmThat basic idea is OK but you need glue logic to connect it all together (convert interface standards, multiplex memory between MCU and DAC access, stream data, etc) and the only options I see at the data rates you want to achieve is an FPGA or an ASIC (specially made chip).

author: cowana
author_rank: Frequent Contributor
timestamp: December 07, 2016, 11:01:20 am
content: What are you trying to do?It almost sounds like you'd be better of with a programmable synth chip rather than a DAC - they are usually controllable via SPI, and you just tell it what frequency you want it to output.