How to improve signal integrity or signal conditioning? - Page 1
Forum section: electronics / beginners

author: slow_rider
author_rank: Regular Contributor
timestamp: January 23, 2019, 09:34:31 pm
content: I have a battery operated device with a B&W LCD. I'm tapping into the video bus and inputs it into an FPGA for some video manipulation. The source signals are 5V with the highest freq. being a clk signal at about 4 MHz. The FPGA would like to see no more than 3.3V + from whatever reason the video output has its baseline at -0.5V which is not good - even with the ground connected to the FPGA board ground so it won't be "floating".After simple resistor dividers didn't solve the problem and loaded down the bus I've decided to hookup ahttp://www.ti.com/lit/ds/symlink/txb0108.pdfin-line with the video bus however now the 4 MHz signal looks like cap charge / discharge cycle.Before I go and insert some inverters in order to "square" back the signal, perhaps there is something I can do so that signal won't get loaded down so badly?Worth mentioning that the wires I am using are all 28 AWG flat cables with connectors simple headers. Wires are kept short as possible. Maybe the wiring + connectors cause all that capacitance? However keep in mind the signal is just 4 MHz.So any ideas are welcomed!

author: StillTrying
author_rank: Super Contributor
timestamp: January 23, 2019, 10:06:55 pm
content: "however now the 4 MHz signal looks like cap charge / discharge cycle."I can't see why the 4MHz would be so bad, are VCCA, VCCB and OE all connected.

author: slow_rider
author_rank: Regular Contributor
timestamp: January 23, 2019, 11:01:39 pm
content: Yes, all are connected.I've disconnected the txb0108 so I'm probing straight from the video bus with a scope. No other load connected.

author: StillTrying
author_rank: Super Contributor
timestamp: January 23, 2019, 11:18:20 pm
content: Scope probe on X10 ?

author: tggzzz
author_rank: Super Contributor
timestamp: January 23, 2019, 11:29:45 pm
content: Quote from: slow_rider on January 23, 2019, 09:34:31 pmNo, that isn't the case. Theonlyparameter relevant to the highest frequency is the risetime/falltime.See the theory and measurements at:https://entertaininghacks.wordpress.com/2018/05/08/digital-signal-integrity-and-bandwidth-signals-risetime-is-important-period-is-irrelevant/Apart from that, you supply inadequate information, e.g. "resistors" - but where and what value, "probing with a scope" - but what type of probe and how long is the ground lead. Details matter.

author: slow_rider
author_rank: Regular Contributor
timestamp: January 23, 2019, 11:46:55 pm
content: Scope was on x1, setting it to x10 had a dramatic effect - the signal actually looks much more like square wave now (without any load but the scope).The probe is passive (not sure what capacitance).The voltage divider I had tried to make is 10k-20k however that is now not part of the circuit.Ground loop is about 10cm long.

author: tggzzz
author_rank: Super Contributor
timestamp: January 24, 2019, 09:19:49 am
content: Quote from: slow_rider on January 23, 2019, 11:46:55 pmI think you mean the "scopeprobe". Details matter. In this case it was unimportant, but poor information runs the risk of wasting other people's time.In future, in order allow us to help you, have a look athttps://entertaininghacks.wordpress.com/library-2/good-questions-pique-our-interest-and-dont-waste-our-time-2/QuoteIt should say so somewhere on the probe.QuoteSo the Thevenin equivalent resistance is 6.6kohm. With a 15pF tip capacitance the measurement would be limited by the RC time constant of 100ns, or with 100pF it would be 660ns.Compare that with your original trace.Quote

author: kg4arn
author_rank: Unknown
timestamp: January 24, 2019, 10:49:05 am
content: @slow_riderThe scope probe always loads the signal test point. The trick is knowing if the loading is significant or not. x10 setting on the probe typically has 10-15pF capacitive load to the ground point. x1 setting will have 10 times that amount. Using a long grounding lead from the probe to the test point causes other issues.Download the ABCS of probes document from Tektronix. The whole document is very good and I think the issues you were having are discussed around page 32.https://www.tek.com/document/primer/abcs-probes-primer

author: spec
author_rank: Frequent Contributor
timestamp: January 24, 2019, 11:21:27 am
content: Hi slow_riderThe problems you are encountering are common when driving displays.As has been said by tggzzz in replay#4, 4MHz is not a slow signal, and especially when you take into account rise time, jitter, etc.The other thing is that the TXB0108, and the resistor, resistor/BJT, resistor/MOSFET translators you see floating around on the net, are only good for slow signals, and even then they are best avoided as they do not meet the edge speed specification or logic level specification for MOS logic and fall apart hopelessly as the frequency increases due to parasitic capacitive loading.You also need to decouple the chips with 100nF X7R ceramic capacitor across the supply pins.It is not clear, but do you need bi-directional comms?

author: bson
author_rank: Unknown
timestamp: January 24, 2019, 09:33:35 pm
content: The LVC logic family will both convert 5V to 3.3V and give you fast transitions on the output. It does have amaximumtransition time of 10ns/V (16.5ns for a 1.65V threshold) on its inputs. Basically it can be used as 3.3V logic that's 5V tolerant.For the opposite, going from a 3.3V logic domain to 5V, consider AHC powered by the 5V domain.http://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf