Clock PLL interface?? - Page 1
Forum section: electronics / projects

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 27, 2016, 03:17:24 pm
content: Hi all,I was wondering if anyone could please help me work out a problem I have interfacing two chips together. I need an accurate clock for a DAC project I'm working on.The first part is a CWX813 CMOS Oscillatorhttp://www.conwin.com/datasheets/sm/sm126.pdfThe second is the LMX2582 Wideband "PLLatinum" RF synthesizer.http://www.ti.com/lit/ds/symlink/lmx2582.pdfThe problem is the listed output voltage levels of the CWX813 and input levels of the LMX2582. Both state supply voltage Vcc = 3.3VThe CMX part states output voltage High = Vcc-0.4 Vdc giving us 2.9V.The LMX part states clock input (REFv) max recomended is 2 Vpp (for AC coupled single ended operation)The footnote (3 page 6) explains further.QuoteThen I get more confused. On the previous page for the LMX spec, absolute max rating for VOSCin <= 1.8 V ?? lower then the recommended 2 V ??Now I'm not just randomly selecting the wrong parts I presume because on page 33 shows TI using this exact CMX clock to drive the LMX as an option.The Resistor divider they have is 18 Ohms on 68 Ohms followed by a 18 ohm then the 0.1uF coupling cap direct in to the LMX chip.So 68 / (18 + 68 ) * 2.9 = 2.293 V .... so what gives?Are they breaking the rules here or have I just missed something obvious.For that reason I was thinking to just use this Si514 as it has a 1.8V differential LVPECL option.https://www.silabs.com/Support%20Documents/TechnicalDocs/Si514.pdfOr otherwise just adjust the resistor divider in the LMX reference design.Any ideas would be most welcome.Thanks

author: lincoln
author_rank: Regular Contributor
timestamp: April 28, 2016, 07:12:12 pm
content: so the oscillator pins are to be ac coupled, a 2 volt Pk-Pk signal with be roughly +1 high -1 low (or where every thin bias the signal internally) what they are saying is that don't apply a dc signal above 1.8 volts with the power on.Is your reference clock going to be a fixed frequency?

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 28, 2016, 07:28:13 pm
content: Thank you..Firstly I just realised I linked the wrong datasheet for the LMX2582 and have corrected that in my original post now.SoI forgot about the coupling and you are correct.. I'll have another look at it.The reference clock is fixed to 200 Mhz. because the LMX sheet states "The best PLL noise floor is achieved with a 200-MHz"Thanks

author: lincoln
author_rank: Regular Contributor
timestamp: April 28, 2016, 07:31:54 pm
content: Ok, At that rate I would start with a capacitor divider,

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 28, 2016, 07:49:16 pm
content: That is some kind of a joke comment ? In what respect would a capacitor divider be applicable in this instance?

author: lincoln
author_rank: Regular Contributor
timestamp: April 28, 2016, 09:56:30 pm
content: nope, no joke. For your pll you want fast edges with lower peek to peek voltage.

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 28, 2016, 10:19:31 pm
content: Hi Lincoln, sorry for my reaction I've just not seen this before. I'll run the numbers and do a simulation and see what I can get from this..Thanks for your input

author: lincoln
author_rank: Regular Contributor
timestamp: April 28, 2016, 10:26:02 pm
content: Its quite all right, A number of factors, device parasitics, oscillator drive strength, ect will effect the voltage level...

author: uncle_bob
author_rank: Unknown
timestamp: April 28, 2016, 11:08:44 pm
content: Quote from: lincoln on April 28, 2016, 09:56:30 pmHiThat CMOS clock oscillator probably will not be very happy driving a 47PF series 82 PF load at 200 MHz. It's already a very noisy part. Adding a major load to it isn't going to help that at all. (Yes, the same divide ratio happens at 4.7 and 8.2 pf ...). There are much better reference oscillators to use for a PLL.Bob

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 29, 2016, 09:20:26 am
content: Hi LincolnI'm still not getting it, in the snippet of the reference design, in my first post, they are not using a captivate divider to solve the problem.But yes I did miss the effect of the AC coupling at the input, so after the resistor network I had 2.293V. So the coupling would produce +- 1.15'ish V that does satisfy and answer my original question.Hi BobThis is the first time for me designing with PLL so go easy on me. Some times datasheets do my head in. I mentioned the LMX2582 recommends 200MHz source to achieve lowest noise.I would have preferred to use a OCXO or TCO but could not find any that would go up to 200MHz, so the poor mans choice was the CWX813.I'll do some more searching.How about this bad-boy rubidium clock?http://www.microsemi.com/document-portal/doc_download/133364-sa-31m-sa-33m-sa-35mThanks.

author: lincoln
author_rank: Regular Contributor
timestamp: April 29, 2016, 08:08:27 pm
content: Quote from: pixulator on April 29, 2016, 09:20:26 amDo you need stability? Accuracy? Or Both?

author: uncle_bob
author_rank: Unknown
timestamp: April 29, 2016, 11:39:51 pm
content: Quote from: pixulator on April 29, 2016, 09:20:26 amHiWhat matters for many PLL designs is noise. That is typically described in terms of phase noise. The units are normally in dbc / Hz. The phase noise changes by 20 log N when you multiply a signal by N. Multiply by 10 and you get 20 db more noise. Divide by 10 and you get 20 db less noise.Various parts of a PLL chip have noise floors. The phase detector has a noise floor. The dividers have a noise floor. These noise floors likely change with frequency. It's a pretty good guess that they change by 10 log N when you go from a frequency of F to a frequency of N x F and look at the floor.So, is there a "magic lowest noise frequency" for the PLL chip? Not really. To the extent there is, it's only looking at the noise floor of the dividers and the phase detector. If those noise floors are *below* the noise on your reference, (and the VCO is even higher), they really don't matter.That's a really simple start to this. There is a *whole* lot more you can dig into...Bob

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 30, 2016, 10:45:46 am
content: Thanks again Bob and Lincoln,I'll give you a little background, and discussion about rabbit holes.So one day I woke up and thought to my self I want to measure the speed of light - how hard can that be. So I purchased a laser (that I had been wanting for other projects anyway) with a TTL input. Its a 532nm 150mW diode with thermoelectric cooling and is mounted in a solid aluminium block. The separate power supply is a very noisy switch mode device but that another story.I constructed a reverse biased photodiode detector (BPX65) and enclosed it in a metal box with a short coax cable (20cm) in to my DS1102D scope. Picture below.Bouncing the laser from one end of my house back to the detector I should expect about 80ns delay for the round trip on the leading edge of the pulse, and if I subtract the system delay at 0 meters I should be able to get a good measurement. The DS1102 has a 100MHz bandwidth so should be plenty.To drive the laser I used a raspberry pi and it's onboard PWM module and this is where the problems started. It has an AMAZING amount of jitter of around 20ns so I was getting a large error in my results.Hence I thought I would just "Whip up" my own pulse generator to drive the laser.Well two weeks later and I've almost completed the schematic of a two channel 50MHz arbitrary function generator based on two AD9102 chips and a ATSAM4E core. So rabbit holedSo long story shorter, I'm looking for short term accuracy over long term stability.I'm wanting to move to PCB layout this weekend so will select several footprints such that I can experiment with different clock sources. The rubidium one was a joke but might go for a OCXO at best and just drive my PLL at a lower frequency. I ultimately need 180MHz for the two AD9102 chips and 18 MHz for the ATSAM. So that's a simple divide by 10 for the AD9514 clock distribution chip.In terms of phase noise, Lincoln, I suppose this is additive through the network, or just as bad as a single component.Thanks.

author: uncle_bob
author_rank: Unknown
timestamp: April 30, 2016, 05:04:43 pm
content: Quote from: pixulator on April 30, 2016, 10:45:46 amHiHere's the next layer:There is no magic boundary between phase noise, short term stability, jitter, wander, and long term stability. They are all just ways to talk about noise on a signal. The units may be a bit different. Some measures can (or can not) be easily converted into other measures. What you are after is a signal with a reasonable ADEV floor. That is something you will not get off of the 200 MHz clock oscillator.Probably the best way to do this would be with a generic FPGA board. Something like an Artix-7 (Arty board maybe) fed by a GPSDO or at least an OCXO. The Arty board is about $100 and an eBay GPSDO is in the same range. An OCXO would be a bit cheaper.Bob

author: lincoln
author_rank: Regular Contributor
timestamp: April 30, 2016, 06:43:17 pm
content: Quote from: pixulator on April 30, 2016, 10:45:46 amGroovy...Quote from: uncle_bob on April 30, 2016, 05:04:43 pmSort of, it depend on the noize type. White noize will be have like that but there is almost noth that can be done about flicker noize. Because flicker noise is self similar it don't really go away if you apply an averging scheam.Quote from: uncle_bob on April 30, 2016, 05:04:43 pmWell sort of, by convention there is, I don't have the ITU standard handy but its 10 Hz, freqency componets 10 Hzand above are consider jitter and below 10Hz is considered wander.Quote from: uncle_bob on April 30, 2016, 05:04:43 pmI have a FPGA board I made for work that has a good VC-TCXO on it that we put together to help coustomes build thier own time related applications. The local TCXO can be traind to an incoming clock or a 1PPS form a GPS. If your interesed I can see if we can get you one. I will PM you the details.

author: uncle_bob
author_rank: Unknown
timestamp: April 30, 2016, 10:03:54 pm
content: Quote from: lincoln on April 30, 2016, 06:43:17 pmHiThe gotcha with disciplining a TCXO against GPS is that GPS is *really* noisy at short tau. You need a long time constant filter to get that noise out of the system. Inside the loop, you simply have the noise of the TCXO, which it generally pretty poor .... Your TCXO likely will have an ADEV of around 2 to 5 ppb at a tau of 1 second. A GPS without sawtooth correction will be much worse than that. If it's a simple L1 unit, it probably will be worse than that even with sawtooth. An OCXO will get you down to 1 ppt at 1 second without spending a lot of money. It all depends on how many digits you want to get on your speed of light estimate ....Bob

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: May 02, 2016, 09:45:25 am
content: Quote from: uncle_bob on April 30, 2016, 10:03:54 pmThank Bob, but I think we are getting in to a degree of accuracy here that goes well beyond 100MHz scope bandwidth.I've settled on Abracon AOCJ2 (OCXO) for 85 pounds on Digikey. 5ppb.http://www.abracon.com/Precisiontiming/AOCJY2.pdfTo get down to 100ppt at one second then you are looking at a 1200 pounds, so I would not call that cheap and still a couple orders of magnatude worse then 1ppt.http://www.abracon.com/Precisiontiming/AOCJY6.pdf

author: dmills
author_rank: Super Contributor
timestamp: May 02, 2016, 10:26:48 am
content: Your other problem is that that laser (532nm is a doubled YAG, it might be diode pumped but it is NOT a diode laser) is not going to start up reliably the same every time...If I was doing it I would grab a Q switched laser, but that is specialist and somewhat dangerous, you might actually have better luck with an LED instead of a DPSS laser of the crude sort.Regards, Dan.

author: uncle_bob
author_rank: Unknown
timestamp: May 03, 2016, 01:08:18 am
content: Quote from: pixulator on May 02, 2016, 09:45:25 amHiADEV of 1x10^-12 at 1 second is a very common spec on a *bunch* of sub $50 eBay OCXO's .... Hitting 1x10^-11 ADEV at 1 second with a GPSDO will not cost you over $200 including the antenna. It will hold frequency to < 5x10^-11 at the 99% level.Bob