Converting a two level analog signal to two bits digital in Cyclone IV or/and V - Page 1
Forum section: electronics / general

author: Miti
author_rank: Super Contributor
timestamp: July 12, 2020, 05:30:00 pm
content: I'm looking to convert a two level analog signal into a two bits digital using only the input features of the Cyclone 4 (and I don't thing Cyclone 5 is that much different). I see it can be done in Xilinx Spartan 6, I'm looking at the NewScope-0Jr Operating Manual from Simmconn Labs, board shot attached.Looking at the "Cyclone IV Device Datasheet" I can't find an easy way to achieve this. I was hoping that I can find a voltage referenced or differential standard that I can play with the Vref or negative input but looks like the requirements are pretty tight and I cannot deviate too much from the VCCIO/2 either with Vref or VCM.Is Xilinx so much more versatile from this point of view than Altera or am I missing something? Which wouldn't surprise me.Thanks!

author: BrianHG
author_rank: Super Contributor
timestamp: July 12, 2020, 06:28:58 pm
content: Not enough analog details. For all I know from your scope shot, 2 NPN transistors, 4 correct resistors will suffice, though the data out will be inverted and you would have to do a thermal range sweep. A dual comparator or 2 single ones in SOT23-5 package would do the same with better temp immunity if you use your VCCA from the FPGA for your resistor divider feeding your reference. Again you would need 3 correct resistor values. 2 more if the comparator you choose needs pullups on the outputs.If your source is an analog signal, I would not trust driving any FPGAs IOs directly. Though with a series resistor like 10k, the input diode protection on most IO pins are sufficient, but, I would still use schottky protection diodes.There is a warning in Intel's data sheets about 1 or 2 configuration PS/JTAG IO pins which do not have protection. The rest should have them.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 12, 2020, 06:38:55 pm
content: There's a hack to use the differential input features of a FPGA as an ADC. Should be able to distinguish between 3 levels pretty easily.BTW, such strange waveforms often occur during bus collisions as a voltage divider is unintentionally formed by the two drivers, probably would be a good idea to make sure the system has current limiting resistors to prevent damage.

author: langwadt
author_rank: Super Contributor
timestamp: July 12, 2020, 06:43:42 pm
content: Quote from: BrianHG on July 12, 2020, 06:28:58 pmLVDS inputs are usually pretty good comparators. I don't know about Intel but Xilinx usually specs 20mA into the protection diodes

author: Miti
author_rank: Super Contributor
timestamp: July 12, 2020, 07:55:42 pm
content: Quote from: BrianHG on July 12, 2020, 06:28:58 pmThanks Brian! I know I can do it with external components but I was intrigued by how easy was done on the board that I mentioned.It is the internal video output of an HP8591E spectrum analyzer that goes to the CRT display. It has low intensity for the grid and menus and higher intensity for the trace.Quote from: BrianHG on July 12, 2020, 06:28:58 pmIf I read correctly in the Cyclone 4 datasheet in the "Table 1–3. Recommended Operating Conditions for Cyclone IV E Devices", the maximum input voltage is 3.6V so doesn't that mean that the IOs are all 3.6V tolerant, regardless of the IO standard selected or Vccio?

author: Miti
author_rank: Super Contributor
timestamp: July 12, 2020, 07:58:34 pm
content: Quote from: NiHaoMike on July 12, 2020, 06:38:55 pmDo you have a link about that hack?Yes, I know it looks that way but it is not. As I mentioned above, it is the internal video output of an HP8591E spectrum analyzer that goes to the CRT display. It has low intensity for the grid and menus and higher intensity for the trace.

author: Miti
author_rank: Super Contributor
timestamp: July 12, 2020, 08:03:00 pm
content: Quote from: langwadt on July 12, 2020, 06:43:42 pmThey should be but if you look at the datasheet, the common mode is specified pretty tight around the VCCIO/2. I'm not sure how far from that I can push it and it still works or I don't damage the inputs.

author: langwadt
author_rank: Super Contributor
timestamp: July 12, 2020, 08:30:42 pm
content: Quote from: Miti on July 12, 2020, 08:03:00 pmwhat are your signal levels?

author: BrianHG
author_rank: Super Contributor
timestamp: July 12, 2020, 08:55:11 pm
content: Quote from: Miti on July 12, 2020, 07:55:42 pmAre you trying to capture a video signal? You want to derive 2 levels of luminance?Without clock locking, it will be noisy, but you can still do it. It would be better getting that clock from the analyzer's video output oscilator. Also, that 2 level gray is most likely already just 2 TTL outputs going through 2-3 resistors. Tapping those source outputs and the clock oscillator on the analyzer would give you the capability of dead perfect sampling.As for getting that 3 level signal into an IO in a determined way, a 3.3v IO bank should be able to capture the low pulse already. If not, a 2.5v bank IO pin would for certain.To capture the high contrast signal, the source signal should go through a small signal double silicon or double schottky diode. This will erase the first 1.3 to 1.5v of the source signal and only let through the remaining 1.5v as 1.5v when high contrast is coming out. After the diode, you need a pull down resistor and tie that to a second IO.These options do not use the 'VREF' input pin. I have never used the feature so I cant comment.

author: Miti
author_rank: Super Contributor
timestamp: July 12, 2020, 09:08:24 pm
content: Quote from: langwadt on July 12, 2020, 08:30:42 pmMaximum is 3V for high contrast and 1.5 for low contrast.

author: langwadt
author_rank: Super Contributor
timestamp: July 12, 2020, 09:50:30 pm
content: Quote from: Miti on July 12, 2020, 09:08:24 pmmight get away with just two cmos inputs in a 1.8/2.5V bank, high contrast with a voltage dividermight even work in a 3.3V bank, low contrast with a series resistor and pull-up

author: Miti
author_rank: Super Contributor
timestamp: July 12, 2020, 09:59:18 pm
content: Quote from: BrianHG on July 12, 2020, 08:55:11 pmI've attached the schematic for that section of the SA. I will capture the HSync, VSync and video, digitize the video and buffer it in a two port RAM, then re-clock it into a VGA output. I found a timing scheme where the video frame rate and the VGA frame rate are in sync and I only need to buffer half the video frame then reuse the buffer. I will regenerate the 21MHz clock from the HSync using ICS9173B-15, I tried and it works very well on the VGA side, a pattern on the VGA monitor is very clean, even though there is a bit of jitter in the regenerated video clock, but I didn't have time to play with the other side, the video capture.See herehttps://www.eevblog.com/forum/projects/modern-equivalent-of-74hc4046-pll/msg3057236/#msg3057236Now, sure I can solder some wires at the inputs of U312, and tap into the 21MHz clock, and be done with it, but first I would like to try the less invasive way of simply connecting my circuit to J8 and have an image on the LCD.

author: BrianHG
author_rank: Super Contributor
timestamp: July 12, 2020, 10:48:17 pm
content: https://www.eevblog.com/forum/projects/modern-equivalent-of-74hc4046-pll/msg3133760/#msg3133760

author: Miti
author_rank: Super Contributor
timestamp: July 12, 2020, 11:33:48 pm
content: Quote from: BrianHG on July 12, 2020, 10:48:17 pmSo, do you say that you coded the 74HC4046's PC2 into the FPGA, then used its VCO?Would that be an advantage over using the internal PC2? I think I tried that (74HC4046 at 10.5MHz) and the clock jitter wasn't great but I blamed it on the low frequency of 15KHz. It didn't cross my mind that 50% duty cycle would help since the phase is compared on the edge.Can you share the R and C values for the VCO and the loop filter for 10.5MHz?

author: BrianHG
author_rank: Super Contributor
timestamp: July 12, 2020, 11:59:40 pm
content: Yes, PC2out needs 50/50 duty cycle on both sources to reliably work at such low frequencies. And it can work even way down at 1Hz with something like a 10k series resistor out and a 1uf-10uf cap to GND for the VCO in.I would start with 1k and 1nf - 10nf. For the cap, (cap should be right at pin 9 and GND) film capacitors offer slightly better performance during the transitions in the source signal as the comparator makes slight pulses, however, this is outside your picture area and it shouldn't affect sampling. I assume your dividing the output of pin 4 and feeding the 7.5khz into pin 3 while pin 14 will have the 15KHz sync divided by 2 to get your 50/50 7.5KHz reference.As for sampling, make the FPGA multiply the source signal clk by 10x. When you take in pixels, you should sample a pixel every 5 clocks with a software selection of which one of those 5 phases to use. This is how some VGA samplers with built in PLL select which phase to sample the input pixels to get rid of transition edge noise.The R&C for the 10.5MHz oscillator itself is tuned by setting the VCO in to 1/2 VCC and adjust the C and R so that the output is 10.5 MHz. Then with the VCO in at GND you want something like 9MHz, and at VCC, something like 12MHz.You do not want too wide tuning as that amplifies noise from the VCO input pin. Noise isn't generated here, it's generated above with the PC2 output and it's filter to the VCO input pin. Plus, power supply noise.This is why I like the TI CDCE PLL clock. I run it with the PLL VCCa of the cyclone at 2.5v and tune it with 2 transistors from 2 IOs replicating the charge pump function of PC2out inside the 74HC4046.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 13, 2020, 12:25:51 am
content: Quote from: Miti on July 12, 2020, 07:58:34 pmhttps://hackaday.com/2015/09/09/video-fpga-with-no-external-ad/

author: asmi
author_rank: Super Contributor
timestamp: July 13, 2020, 01:25:42 pm
content: Almost all Xilinx 7 series devices have built-in dual 1MSPS ADC. I can't remember if Antel chips have it as well, but if they do, that would be the best solution. Depending on ADC parameters, you might need a voltage divider - for example 7 series ADC is only rated for up to 1 V in unipolar mode or ±0.5 V in bipolar mode.

author: langwadt
author_rank: Super Contributor
timestamp: July 13, 2020, 01:46:54 pm
content: Quote from: asmi on July 13, 2020, 01:25:42 pmhow's 1Msps going to work with the ~100ns pulse widths shown the OP?two cmos inputs and few resistors should be enough to distinguish 0V, 1.5V and 3V

author: c64
author_rank: Frequent Contributor
timestamp: July 16, 2020, 06:30:34 am
content: If you have some free IO pins, you can feed your signal to two separate input pins, with different VCCIO.For example, to 3.3V bank and 2.5V bankIf both capture 1, it's high brightness, if one is 1 and another is 0 - it's low brightness.May need some pull-ups or pull-downs to make sure it's never near 1/2 VCCAnd protection diodes

author: BrianHG
author_rank: Super Contributor
timestamp: July 16, 2020, 07:00:47 pm
content: Your cleanest separation would be use a 2.7-3.3v powered 74AC04, feed 1 input directly, feed a second input through 1 or 2 series 1N914 small signal silicon diode (mmbd914) with a pull down resistor. The 2 74AC04D outputs will have an inverted image and they will not damage your FPGA. I would also feed your syncs through the other spare gates in the 74AC04D as you do not care if that IC dies. It will also respond in less than 5ns.Most other solutions here are dependent on a finicky transition point in logic gate input threshold and dividing the source signal until that divided down shrinking threshold changes on the source signal level. Good for 1 home project board, but I wouldn't rely on making such a project public domain, or sell it to anyone.

author: BrianHG
author_rank: Super Contributor
timestamp: July 16, 2020, 07:05:58 pm
content: Quote from: c64 on July 16, 2020, 06:30:34 amCan't guarantee functionality with Intel FPGAs. The FPGA data sheet has the same 0.7v-1,7v threshold for 2.5v through 3.3v powered IO banks. Only 1.8v and below do these figures change.

author: Miti
author_rank: Super Contributor
timestamp: July 17, 2020, 11:54:52 am
content: I think the title of my post should have been "How did that guy do it?". Considering that he fed the signal to two inputs directly through two zero ohm resistors, I suspect he used differential inputs with the negative side to two different levels, I don't know what's on the bottom side of the board, but I suspect there are two voltage dividers.

author: BrianHG
author_rank: Super Contributor
timestamp: July 17, 2020, 07:06:22 pm
content: Quote from: Miti on July 17, 2020, 11:54:52 amAssuming it's done exclusively with divider resistors, I would not personally guarantee such a design over many FPGA & pcbs.Looking at your 500mv/div scope shots. I would use 2 npn transistors, a series resistor to transistor #1's base, and 1 diode in series with pulldown resistor, the series resistor after the diode feeding the second transistor's base. Emitters to GND. Pullups on the output collectors to your desired VCCIO. That would create a clean digital signal with around 5-15ns pull-down, around 50ns rise when released.Powering a 74LVC04 at around 2.0v, feeding 2 inputs like the transistor bases above would do the same thing, but respond much faster than the transistors and provide a definite switch to high and low rail, super fast delay + rise and fall times in the order of a few ns.

author: langwadt
author_rank: Super Contributor
timestamp: July 18, 2020, 01:06:54 pm
content: Quote from: BrianHG on July 17, 2020, 07:06:22 pmwhy not? looking at the spec for LVDS inputs: Vcom = 0.05-1.8V, Vdif = 100mVso divide input by 2 to get inside the common mode range, and two dividers to set the thresholds

author: Miti
author_rank: Super Contributor
timestamp: July 18, 2020, 02:56:25 pm
content: Quote from: langwadt on July 18, 2020, 01:06:54 pmThis is what I'm talking about. It seems to work very well in simulation.Since my development board has all VCCIOs connected to 3.3V, I wonder what happens if I assign 2.5V LVDS pairs but the bank is supplied by 3.3V. Is it going to blow up the chip, or is just the levels are messed up? I'm aware that all the I/Os in that bank must be 2.5V, otherwise Quartus will swear at me...Rename .txt to .asc to simulate in Ltspice.

author: BrianHG
author_rank: Super Contributor
timestamp: July 18, 2020, 03:44:47 pm
content: OMG, an 8$ chip when a (looking at your first scope shot) 0.50$ 74ALVC04 powered with 2v (yes, this ICs inputs are 3.6v tolerant even powered with 2v) and 2 diodes will do the same job, though the logic switch edge will be fixed at ~1v on each input. Powering your IO bank at 3.3v would mean no ICs needed, just the 1-2 silicon diodes to separate the 2 voltage levels to 2 different inputs.Ok, back to your question:For CycloneIV, you have 0.3-0.5v above the VCCIO before the clamping diodes engage.An output resistor divider would work with your illustrated circuit.A 1k series resistor alone would also work so long as the selected IO pin has the PCI clamp diodes mentioned in the CycloneIV hand book in section 3, DC electrical characteristics.As for powering an IO bank with 3.3v and telling quartus to run the IOs in differential 2.5vLVDS, I don't think it will destroy the chip, however, I never done this.Can you change your dev board's 3.3v regulator to 2.5v?Most other 3.3v lvcmos ICs should work at 2.5v, but a bit slower.

author: langwadt
author_rank: Super Contributor
timestamp: July 18, 2020, 04:21:12 pm
content: Quote from: Miti on July 18, 2020, 02:56:25 pmDon't know about Intel but Xilinx has said that LVDS inputs will work just fine at 3.3V but the if you use the internal termination it not be accurateOutputs won't work in the newer families because the faster LVDS transistors are disconnected about ~2.9V to protect them

author: Miti
author_rank: Super Contributor
timestamp: July 18, 2020, 08:04:21 pm
content: Quote from: BrianHG on July 18, 2020, 03:44:47 pmBrian, the comparators are not extra chips. They're supposed to be the internal FPGA LVDS comparators. I used those chips only for simulation and I selected the resistors to bring the common mode inside the 0.5 to 1.8V range.Quote from: BrianHG on July 18, 2020, 03:44:47 pmI think I could do that. Actually there is a 2.5V regulator on the board, I could just remove the 3.3V and connect 2.5V and 3.3V line. I don't think the VCCIOs need too much current.

author: Miti
author_rank: Super Contributor
timestamp: July 18, 2020, 08:06:15 pm
content: Quote from: langwadt on July 18, 2020, 04:21:12 pmGreat, thanks! I only need inputs. I will give it a try.

author: BrianHG
author_rank: Super Contributor
timestamp: July 18, 2020, 09:53:26 pm
content: Note that lying to Quartus, setting a fake IO voltage to get access to the differential LVDS input features will mean none of your final timing report can be considered valid. Same with the precision of the LVDS characteristics listed in the Cyclone handbook.

author: langwadt
author_rank: Super Contributor
timestamp: July 18, 2020, 10:02:51 pm
content: Quote from: BrianHG on July 18, 2020, 09:53:26 pmnone of the timing report being valid seems a bit hyperbolic

author: BrianHG
author_rank: Super Contributor
timestamp: July 18, 2020, 10:39:52 pm
content: Quote from: langwadt on July 18, 2020, 10:02:51 pmOoops, sorry, your right my choice of words is overkill. I mean regarding those IO in that bank in particular will present skewed results.

author: Miti
author_rank: Super Contributor
timestamp: July 18, 2020, 11:18:49 pm
content: Quote from: BrianHG on July 18, 2020, 09:53:26 pmThat would be for testing only. The final board will have the correct voltage.

author: BrianHG
author_rank: Super Contributor
timestamp: July 19, 2020, 01:23:28 am
content: Quote from: Miti on July 18, 2020, 11:18:49 pmJust watch the temperature of the Cyclone. If it stays cool, your ok.

author: c64
author_rank: Frequent Contributor
timestamp: July 19, 2020, 03:39:36 am
content: Quote from: Miti on July 18, 2020, 02:56:25 pmInteresting question, I would like to know as well. It might blow up, if comparators only support 2.5V or less

author: langwadt
author_rank: Super Contributor
timestamp: July 19, 2020, 12:55:33 pm
content: Quote from: c64 on July 19, 2020, 03:39:36 amit would be a really bad design if you could connect a legal 3.3V and then kill the IC by loading a bit file that use LVDS

author: Miti
author_rank: Super Contributor
timestamp: July 19, 2020, 09:29:20 pm
content: Quote from: langwadt on July 19, 2020, 12:55:33 pmI can't imagine that just by selecting wrong input type in Quartus, you can blow up a chip. I think the different blocks are all supplied at the same time, selection is done through some enable lines. My uneducated 2 cents.

author: BrianHG
author_rank: Super Contributor
timestamp: July 19, 2020, 09:34:11 pm
content: You should be fine. However, just remember, a larger VCCIO on any CMOS chip whose inputs sit in the middle threshold turns on 2 mosfets simultaneously at the input generating additional power supply current and heat unless it's a specifically engineered schmitt trigger input.Being careful on 2-3 IO should allow you to get away with it.Final results can only be guaranteed if you operate within the high&low confines of the DC electrical characteristics mentioned in the Cyclone Handbook.I would personally drop the PLL chip in your other thread, do that inside the Cyclone and use a 74ALC04 or 74ALC245 to buffer the video into 2 bits & also pass the H&V sync through the cmos chip isolating and protecting the IOs on your FPGA from the scope you are connecting to as the 74ALC series has protection diodes at their inputs while the outputs will not drive the IO pins while the IC is powered down with the Cyclone.Yes, powering up the source scope and feeding inputs into the Cyclone while it is powered off is potentially more of a problem than feeding inputs an odd differential signal within the range of VCCIO & GND.

author: Miti
author_rank: Super Contributor
timestamp: July 19, 2020, 11:25:10 pm
content: Here it is. It works perfect. I loaded one of my FY6600 arbitrary slots with a signal that simulates the video signal, then I assigned two LVDS inputs to two 3.3V outputs inside the FPGA. With two programmable power supplies as negative inputs references set to 0.9V and 1.5V and a long cable from the generator to the positive inputs, you can say by the amount of ringing, it works just perfect. No heating at all. If it works this well with lots of wires flapping in the wind, I'm sure it works even better on a board.

author: BrianHG
author_rank: Super Contributor
timestamp: July 19, 2020, 11:40:20 pm
content: You're good to go!

author: Miti
author_rank: Super Contributor
timestamp: July 19, 2020, 11:42:10 pm
content: Thank you all who helped me!