[FPGA] From zero to DVB parsing - Page 1
Forum section: electronics / general

author: jack burton
author_rank: Contributor
timestamp: February 12, 2019, 08:54:06 am
content: Hi all,I'm looking for a good tutorial to start my first project in fpga world.I've never used fpga and i don't know vhdl.My goal is to parse a dvb stream to retrieve some informations about sats pointed by a motorized dish.But this is the final goal, my first need is to start with the right step..Someone told me to use xilinx spartan, but i have no idea about the performance of an fpga, i don't need to buy now the same fpga i'll use for my project,but at least keep using same ide and same family.There are too much options, too much parameters... and i'd like to have some suggestions to make my first step.Thank you.Ciao all !

author: JacobPilsen
author_rank: Regular Contributor
timestamp: February 12, 2019, 07:01:47 pm
content: 1) Xilinx or Altera (or Lattice)2) IDE is huge !EEVblog: Best FPGA Dev Board For ApplicationEEVblog: Learning FPGAs: wrong approach?

author: Scrts
author_rank: Frequent Contributor
timestamp: February 12, 2019, 07:19:50 pm
content: Quote from: jack burton on February 12, 2019, 08:54:06 amI've used Altera Cyclone III & V for MPEG-TS processing. Do you want to analyze the stream coming from DVB-S/S2? At analog level or digital packets?

author: rstofer
author_rank: Super Contributor
timestamp: February 12, 2019, 07:33:22 pm
content: I don't know anything about your application so I can't even begin to think about data rate. Faster rates require faster chips which will, oddly, cost a lot more money!fpga4fun.com may be interesting for you.There is a concurrent thread and you might check out my reply #7https://www.eevblog.com/forum/beginners/online-fpga-simulator/I talk about a couple of my favorite boards.

author: ebastler
author_rank: Super Contributor
timestamp: February 12, 2019, 07:38:49 pm
content: This forum's own Mike Field (hamster_nz) has a very nice set of pages.Maybe not a systematic tutorial, but many great ideas and examples!http://hamsterworks.co.nz/mediawiki/index.php/FPGA_ProjectsIncluding e.g. HDMI output and capture:http://hamsterworks.co.nz/mediawiki/index.php/HDMI_Capture

author: jack burton
author_rank: Contributor
timestamp: February 13, 2019, 10:21:13 am
content: Quote from: rstofer on February 12, 2019, 07:33:22 pmHi,i don't need to analyze or decode video stream, i have just to extract PID, NIT, PMT (ecc..) tables from TS in order to detect a given satellite...

author: Wiljan
author_rank: Regular Contributor
timestamp: February 13, 2019, 12:07:03 pm
content: HiDon't know what receiver you do use, but if it's on Linux there is a software called "dvbsnoop" which will give you the info you can expect.http://dvbsnoop.sourceforge.net/If you want to go the FPGA way it might be wort to have a look herehttps://www.netup.tv/en/headends/unicardyou will find open source for FPGA herehttps://github.com/aospan/NetUP_Dual_Universal_CI-fpgaHere is a small info on state machine to extract the most base info from the tshttp://dpi-proceedings.com/index.php/dtcse/article/download/18953/18449On the other hand it sound like you want to build is what are in many newer Satfinder boxes for low money

author: jack burton
author_rank: Contributor
timestamp: February 13, 2019, 02:20:11 pm
content: Quote from: Wiljan on February 13, 2019, 12:07:03 pmWe are trying the fpga way because years ago my company chose to use a windows pc with technisat dvb-s cards, and we are dealing with components obsolescence, drivers/os, etc, and year after year it is always worse , it's getting harder to replicate the same product.FPGA is a technology we have wanted to learn for years and this could be the right opportunity to begin.

author: TimCambridge
author_rank: Regular Contributor
timestamp: February 14, 2019, 01:03:16 am
content: You might find that starting with something like Python/MyHDL eases the learning curve. For sure it adds an extra bit of tooling, but you have less to worry about on the language front.You write and simulate in Python, auto compile to VHDL or Verilog, then use the manufacturer's tools to generate a bitstream for your FPGA. Simulation is the biggest piece of the job.

author: Scrts
author_rank: Frequent Contributor
timestamp: February 14, 2019, 02:36:07 pm
content: Quote from: jack burton on February 13, 2019, 10:21:13 amYes, I've done this. FPGA is a good solution for your application. Just remember that the table contents get updated and you also have to track the table version. You should also understand that there are many satellites, especially in east region, which do not adhere to DVB standards well and you will see some missing tables, missing data, bad padding, etc..

author: hamster_nz
author_rank: Super Contributor
timestamp: February 15, 2019, 08:11:28 am
content: Quote from: jack burton on February 13, 2019, 02:20:11 pmI would be interested to hear how you get on with this. Do you intend to be doing the RF work too (e.g. a tuner and a high speed ADC)? or do you already have a stream of samples or a data stream?I worry will may run into the same problem with obsolescence with FPGA. It is a much harder wall when you can no longer get your FPGA, so you may need to have the design you are selling, plus the one with the later FPGA ready to go when the time is right. Fortunately most of the HDL should be the same...

author: jack burton
author_rank: Contributor
timestamp: April 09, 2019, 09:29:00 am
content: Hi all,i'm still alive after 2 months of intensive tests with customers, now i have time to breathe again...so.. i'm going to buy a dev board to start approaching fpga world.I'm oriented on Spartan6/7 board, something my purchase office can find easily on biggest suppliers like digikey, farnell, etc..i've found ARTY S7-50 SPARTAN-7 that seems to have all the i/os and leds needed to complete an hello world project.what do you think ?Bye

author: rstofer
author_rank: Super Contributor
timestamp: April 09, 2019, 02:54:54 pm
content: I have a couple of the older Arty boards and they work fine. However... Notice how there is always a "However..."?I prefer boards with a LOT of onboard gadgets like 7 segment displays, toggle switches, buttons, LEDs and so on. I find they make debugging a lot simpler and the time they save makes up for the additional cost.I like this board:https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/Now, I have no idea how much IO you need and I'll concede that PMOD headers are limiting. In that regard, the Arty board has more headers. And, of course, the Nexys-A7 board is $140 more money but my time is worth something.And definitely the 100T version, not the 50T because more logic and more BlockRAM is always better than less.You can play with Xilinx's HLS, write your project in C and have the tools translate it to VHDL (or Verilog). I haven't done this but somebody must think it's a good idea.

author: jack burton
author_rank: Contributor
timestamp: April 09, 2019, 03:35:27 pm
content: Quote from: rstofer on April 09, 2019, 02:54:54 pmHi,i'm looking to another board instead, the basys-3 from digilent...https://reference.digilentinc.com/reference/programmable-logic/basys-3/start?redirect=1as i wrote before, at this stage i'm looking for a baic dev board to move first step in fpga..

author: NorthGuy
author_rank: Super Contributor
timestamp: April 09, 2019, 03:54:18 pm
content: Quote from: jack burton on April 09, 2019, 03:35:27 pmI would create a list of what I need on the board and then would buy a minimal board which contains all the items from the list.

author: asmi
author_rank: Super Contributor
timestamp: April 09, 2019, 04:16:13 pm
content: Quote from: NorthGuy on April 09, 2019, 03:54:18 pmOr get a board with FMC connector (or some other hi-speed connector) which would allow to build a daughter board with whatever peripherals you want.Or - my personal favorite - design and build the board yourself.

author: rstofer
author_rank: Super Contributor
timestamp: April 09, 2019, 06:57:59 pm
content: Quote from: jack burton on April 09, 2019, 03:35:27 pmI have that board too! Side issue: I hate to think how much money I have tied up in boards...It's a nice board and it has a few gadgets. There aren't many PMOD connectors and there are no headers. Make sure you can meet your IO requirements.Do be aware that it comes with the 35T version of the FPGA which is smaller than the 50T version and a LOT smaller than the 100T versions. Page 3 here:https://www.xilinx.com/support/documentation/selection-guides/7-series-product-selection-guide.pdfTo learn basic VHDL stuff, the smaller chip will be fine. But I like using the largest chip available just in case I get carried away. And if you need BlockRam, there is a heck of a difference between the 35T and 100T.I mostly play with CPUs and, when possible, I like to use BlockRAM to meet my memory needs. I don't prefer to get involved with DDR or other off-chip technologies if BlockRAM will meet my needs.The Nexys board includes 128MB DDR2 and 16MB Cellular Ram (very helpful) while the Arty boards have 256MB of DDR3 memory. The Basys board has no separate memory (AFAICT). One of my projects uses the Cellular Ram as static memory for a CPU design. That is so much cleaner than dealing the dynamic memory.Lots of choices...

author: jack burton
author_rank: Contributor
timestamp: April 12, 2019, 09:55:32 am
content: Quote from: rstofer on April 09, 2019, 06:57:59 pmHi,i received the basys 3 board right now..i'll try to turn on a led following this book:https://www.mhprofessional.com/9781259837906-usa-digital-system-design-with-fpga-implementation-using-verilog-and-vhdl-group

author: jack burton
author_rank: Contributor
timestamp: April 12, 2019, 12:51:35 pm
content: Hi,i was looking on xilinx website for an IP to demux TS but as far as i've foud, it seems they have only modulators for mpeg/DVBhttps://www.xilinx.com/products/intellectual-property.htmlJust to understand, is it a too simple project to sell it as IP ?

author: aandrew
author_rank: Frequent Contributor
timestamp: April 12, 2019, 01:20:00 pm
content: The TS isn't that bad to parse out; I did some of this years (jeez almost a decade??) ago using off the shelf DVB-S2 demodulators that spat out an 8 bit bus with some control signals. Pulling that into an FPGA was just a matter of writing a state machine that understood the bus and then spat the data into a FIFO or out to ethernet or really anything.I may have missed it, but I don't recall what you intend to do with the TS data. Will it be sent to a PC or an embedded MCU to do something useful with the "what's overhead" data?Come to think of it, I bet you could make an FX2LP or FX3 understand the bus and emit a digital stream to the PC for processing.

author: Psi
author_rank: Super Contributor
timestamp: April 12, 2019, 01:29:49 pm
content: TSreaderlite is a useful free tool for viewing the TS data.

author: jack burton
author_rank: Contributor
timestamp: April 12, 2019, 02:35:20 pm
content: Quote from: aandrew on April 12, 2019, 01:20:00 pmhi,my goal is to obtain Provider, Satellite and signal level of a given transponder.My input is a stream from a DVB-S decoder chip and my output is a uart to send info to an STM32 microcontroller.

author: jack burton
author_rank: Contributor
timestamp: April 12, 2019, 02:37:27 pm
content: Quote from: Psi on April 12, 2019, 01:29:49 pmThank you,i remember i used TSreader a lot of years ago at the university when i was experimenting streaming from DVB cards to ip

author: Scrts
author_rank: Frequent Contributor
timestamp: April 12, 2019, 06:00:31 pm
content: Quote from: jack burton on April 12, 2019, 02:35:20 pmDo you really need FPGA for this? I'd say get a raspberry PI with USB DVB-S2 receiver:https://www.linuxtv.org/wiki/index.php/Category:DVB-S2_USB_DevicesThen write a small app or script using LibDVB and extract that data.https://linuxtv.org/docs/libdvbv5/https://github.com/esurharun/libdvbThis should allow any data extraction you need from the PAT/PMT/NIT tables and push it over UART.

author: jack burton
author_rank: Contributor
timestamp: April 15, 2019, 09:44:18 am
content: Quote from: Scrts on April 12, 2019, 06:00:31 pmHi,i want to learn fpga development, so i want to do it with fpga,thank you for the links anyway !bye !

author: jack burton
author_rank: Contributor
timestamp: April 16, 2019, 09:46:34 am
content: This is the board i'll interface with, the connector P1 is the one that brings out the 8-bit TS for the FPGA board.Actually the board uses a stm32f7 to control the NIC (STV0910) via i2c interface.Looking forward to the development, assuming that i could parse a TS, what do i need to test the algoritm ?I was wondering if there's a way to simulate it using a TS file recorded with a DVB-S2 tuner on a PC ?

author: Scrts
author_rank: Frequent Contributor
timestamp: April 16, 2019, 01:11:56 pm
content: Quote from: jack burton on April 16, 2019, 09:46:34 amPossible, but with some pain. E.g. it is possible to play .TS file from VLC over network, then you can receive that stream with FPGA and extract from UDP/RTP frames. It is straightforward, if you only need the tables, but would be way more complex if you'd need the video as Program Clock Reference (PCR) tracking is extremely important there.

author: jack burton
author_rank: Contributor
timestamp: April 16, 2019, 02:36:54 pm
content: Quote from: Scrts on April 16, 2019, 01:11:56 pmI was thinking to something like simulate the IP with modelsim giving the file as input, feeding the fpga model with 8 bit bus extracted from the file.

author: rstofer
author_rank: Super Contributor
timestamp: April 16, 2019, 03:36:23 pm
content: You may find this book helpful:http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

author: jack burton
author_rank: Contributor
timestamp: April 16, 2019, 03:56:47 pm
content: Quote from: rstofer on April 16, 2019, 03:36:23 pmthank you Rstofer

author: Scrts
author_rank: Frequent Contributor
timestamp: April 17, 2019, 03:20:13 am
content: Quote from: jack burton on April 16, 2019, 02:36:54 pmYes, this is the good way to do it as well - feed TS file using textio library. You will have to generate TS_Start yourself though.