Questions about designing a low-voltage, low-noise Vref for a 16bit ADC - Page 1
Forum section: electronics / beginners

author: Melon
author_rank: Newbie
timestamp: October 29, 2019, 03:56:30 pm
content: Hello, I need to design a set of voltage references for a 16-bit DSM. The two most constrained go to the input DAC of the DSM so all the noise on these is coupled directly to the input. The accuracy is not as important but the higher the better. The specs would be the following:- Low noise: < 20 nV/sqrt(Hz)- Nominal value of 0.4V and 1.4V, but better if they are adjustable. I have a common mode of 0.9V which should be in the center, I don't know if I can make use of this to generate a symmetric range.- The current drawn by the DSM is a high frequency (i.e. 12.8MHz) pulsing current. The average is quite low however (way smaller than 1mA). To reduce the switching noise I want to use big decoupling capacitors at the DSM input pins (1uF or 10uF the biggest and then a ladder of decades (e.g. 10u-0.1u-1n)So far this is what I have tried and looked at:- First I tried using the circuit in fig1 (some component references are different) to use my common mode to generate a symmetric signal using only one low-noise regulator. However I had stability problems with the opamp due to the big decoupling capacitors. What I did is add an emitter follower after the opamp and the feed it back to the negative pin. This solved the stability but the output voltage when the DSM was running was very noisy due to switching currents. The output measurements weren't very good either.- I also tried generating both voltage references separately using the typical scheme seen in integrated voltage references (LDO-voltage divider+filter-opamp buffer stage) (fig2). I repeated the emitter follower stage after the opamp to decouple the opamp output from all the DSM capacitors. I think this kind of worked since the measurements were limited by a different issue but I still saw ugly switching noise on the oscilloscope. I can't confirm this is due to current fluctuations, but I don't think is due to PCB couplings. I was careful separating the digital and analog domains and using different regulators for both analog and digital pins. Advice is welcome nonetheless.- I think the easier would be that the output voltage was the output of a LDO regulator to avoid using an opamps so I don't have to worry about stability, etc. The problem is there are no adjustable nor fixed regulators that can provide such low voltages as the 0.4V I need. I also looked at voltage references since the buffer is already integrated but from what I've seen they are fixed, the noise is quite high (at least the ones I've seen) and the voltages are not as low as 0.4V anywaySo I'd like to ask any of you with experience in high-resolution ADC measurements how to properly generate the bias voltages since I have a couple attempts and I'm still not convinced on the right way to do it. If you need any information about the components I used in the designs I will post it.Thank you in advance.p.d. the transistor in fig2 should be a NMOS

author: Vgkid
author_rank: Super Contributor
timestamp: October 29, 2019, 06:39:27 pm
content: Pictures of the circuit are needed.

author: Melon
author_rank: Newbie
timestamp: October 29, 2019, 06:50:14 pm
content: Sorry I thought I had attached them. I have added them now.

author: JustMeHere
author_rank: Frequent Contributor
timestamp: October 30, 2019, 02:13:55 pm
content: You will want a big ground plane. Grounding in this is the most important part. A 4-layer board from oshpark might be something to consider. The answer to this is covered by Howard Johnson in his High Speed Digital Design book. You can watch the lectures with a 10 day trial account at learning.oreilly.com. There actually one set of lectures just about grounding, but the High Speed one covers what you need too.Check this out, I might have found the circuit you're looking for:https://www.ti.com/lit/ds/symlink/tpl0401a-10.pdf#page=21

author: Melon
author_rank: Newbie
timestamp: October 30, 2019, 03:38:06 pm
content: Thanks I will take a look at the lectures. I've read quite a lot about grounding but sometimes the information between different sources is conflicting. In some places they say it is better to use split grounds planes for analog and digital and join them under the ADC, and in others to just use a solid GND plane with virtual separation. I've tried the two designs, one with a solid plane and another with separated planes joined at the ADC and DC input. The first one performed slightly better but I changed many things so I cannot say it is due to that.My main concern is that in my last design I saw some ugly switching noise at the sampling frequency (12.8Mhz). I thought this should be solved by using large decoupling capacitors but this forces me to use the voltage follower transistor stage (fig2) to isolate the opamp output and ensure stability. I don't know if this is the best solution or if this is causing problems anyway. I'm currently looking for low-noise opamps able to drive large capacitors so I don't have to add the transistor. The current drawn by the ADC is small (1mA in total from the power supplies, from the voltage references should be negligible). I don't own very high-end equipment so I can't really measure accurately the voltages with my oscilloscope at that frequency, I just see some rippling but maybe it is just a pulse and it stabilizes afterwards. Maybe it is actually some coupling on the board although I think I was careful with that.I have actually used those digital potentiometers in the SPI version and they worked OK, but in the end I'm just using regular potentiometers as I prefer the simplicity laying out the PCB over the flexibility since I just want to take some measurements. As I said I don't care as much about having a 1mV difference from the nominal value as I do regarding the noise density of the voltage source and the switching noise from the ADC.