Nested interrupts on CH32V003 - how ?  - Page 1
Forum section: electronics / general

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: August 21, 2025, 04:51:19 pm
content: As far as I can see, it should be possible to have 2 levels of interrupts, with the higher priority one interrupting the low-priority one if it's active, guaranteeing a low latency on the high priority one regardless of the lower priority int.but I can't for the life of me figure out how to do it - the documentation is basically nonexistent.The reference manual mentions a "nesting enable" configuration bit in the INTSYSCR register, but gives no clue as to how to actually set it as it's a special internal core register, not a normal peripheral registerthe definition of the NVC_Init library call mentions it but in a very non-useful way which AFAICS implies you have already figured out how to set itCode:* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the* configuration information for the specified NVIC peripheral.* interrupt nesting enable(CSR-0x804 bit1 = 1)* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.* NVIC_IRQChannelSubPriority - range from 0 to 1.** interrupt nesting disable(CSR-0x804 bit1 = 0)* NVIC_IRQChannelPreemptionPriority - range is 0.* NVIC_IRQChannelSubPriority - range from 0 to 3.Does anyone have a simple working example of setting up two interrupts with nesting ?

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 21, 2025, 05:53:43 pm
content: INTSYSCR is a CSR.Below, you have a discussion about enabling the hardware stack, also in INTSYSCR, which should help you figure it out:https://www.eevblog.com/forum/microcontrollers/ch32v003-fast-interrupt-(pfic)-features/

author: hans
author_rank: Super Contributor
timestamp: August 21, 2025, 05:54:58 pm
content: I haven't worked with that part, but looks like that register is part of the 'coprocessor'. You can access these registers using the "Zicsr" instruction set extension of RISC-V.Basically the CSRRW / CSRRC / CSRRS instructions.Iirc there are several "special" registers for the RISC-V, such as interrupt return address, performance counters, etc.Edit:Maybe something like this?Code:void IntEnableNesting() {uint32_t val = 1 << 1; // Set INESTENasm volatile("csrr %0, INTSYSCR": : "r"(val) : "memory");}

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: August 21, 2025, 06:39:14 pm
content: the default startup code appears to allow nesting :Code:/* Enable interrupt nesting and hardware stack */li t0, 0x3csrw 0x804, t0I'm enabling ints as follows - I want the DMA interrup to to have priority over SysTick. I'm setting an I/O during each int handler so I can see if any nesting is happenniing ( it isn't)Code:NVIC_InitTypeDef NVIC_InitStructure = {0};NVIC_InitStructure.NVIC_IRQChannel = SysTicK_IRQn;NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;NVIC_Init(&NVIC_InitStructure);NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel5_IRQn;NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;NVIC_Init(&NVIC_InitStructure);

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: August 21, 2025, 06:43:54 pm
content: Ok seems to be working now after addingCode:NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);