Renesas "lowest cost" ForgeFPGA low-density  FPGA - free eval boards - Page 1
Forum section: electronics / general

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 09, 2024, 08:04:33 am
content: Apply for free eval board :https://www.my-boardclub.com/boards/slg7evbforge/1K LUT, 32K BRAM. configure from MCU SPI flash or Onboard OTP50MHz +/-5% onboard osc + PLLI/O only goes up to 2.75v0.4mm QFN packageDatasheethttps://www.renesas.com/us/en/document/dst/slg47910-datasheet?r=25546631

author: ftg
author_rank: Frequent Contributor
timestamp: July 09, 2024, 12:35:33 pm
content: Applied for one. Time will tell if I'm deemed worthy of one.The 2.75v MAX IO's do sound a bit limiting.Are there even that many <3V3 PMOD's out there?

author: ataradov
author_rank: Super Contributor
timestamp: July 09, 2024, 01:49:28 pm
content: The I/O voltage limit is new. I guess they ran into some issues with the higher voltages and decided to not change the design. This combined with the need for 1.1 V core voltage regulator makes the device pretty pointless.So, this is what they were working on for 3 years since the announcement?So, it looks like it is entirely new design with the same name. Specs from the preliminary datasheet from 2 years ago:QuoteNew specs:Quote

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 09, 2024, 09:07:11 pm
content: maybe they have some big customer they needed this part for, and just bought some IP and fabbed it. Maybe they have some internal kit (say an ADAS system) that they found they needed some glue logic for, and again, bought some IP and fabbed it.amusing

author: ataradov
author_rank: Super Contributor
timestamp: July 09, 2024, 09:18:57 pm
content: I think they did license the FPGA fabric. I don't remember their name, but there is some company that makes small FPGA IP.But the rest of the design is theirs. At some point they admitted that the initial delays were caused by some issues with the early silicon and they needed a silicon revision. So, I guess the revision did not work out.This voltage lowering is not intentional, since early engineering samples and boards they sent out used 3.3 V supply.The whole thing is strange from the beginning. And in that time a lot more low end FPGAs became available. The only thing Renesas had is easy and lightweight IDE that did not need registration or licenses to use. But that only gets you so far if the silicon is crap.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 09, 2024, 09:31:03 pm
content: yeah, agreedas such, I think it is for some internal glue logic they need for some product, and , hey, why not flog it on the market, see if anyone buys it. LOL..... If you want a tiny FPGA, u buy Lattice or Microchip....

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 09, 2024, 11:40:57 pm
content: We'll see still what they bring, for instance in terms of power consumption. Nothing wrong with having more alternatives. Whether it's good strategy for Renesas is another question, time will tell.

author: tom66
author_rank: Super Contributor
timestamp: July 11, 2024, 09:52:36 am
content: 2.7V IO kills it for so many applications. Ok your FPGA is 3x3mm but if I need to pepper the IO in level translation ICs then it's not really that small is it?Very weird that they'd release silicon like this with a known limitation that is so critical.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 11, 2024, 11:30:27 am
content: Quote from: tom66 on July 11, 2024, 09:52:36 amThey probably have some big customers for whom that's not an issue. Wouldn't surprise me if this gets "fixed" in future.

author: coppice
author_rank: Super Contributor
timestamp: July 11, 2024, 12:28:07 pm
content: Quote from: tom66 on July 11, 2024, 09:52:36 amDon't be so parochial. There are vast numbers of systems running on <2.7V these days. No part suits everyone. You just need to suit a substantial market to succeed. 2.7V would be an odd initial target voltage right now, but if you fail to achieve your goal while having a solid solution that suits substantial markets you need to get to market and start getting some revenue. You learn so much from the feedback you get with early parts in a family. That can really improve your follow ons.... assuming you are good at listening.

author: asmi
author_rank: Super Contributor
timestamp: July 11, 2024, 06:28:52 pm
content: Quote from: tom66 on July 11, 2024, 09:52:36 amI disagree that it's critical, or even especially important. A lot of peripherals nowadays can work just fine at 1.8 V level or even lower, that's clearly where industry is heading to save power and/or reach higher performance for the same power, heck Xilinx FPGAs had 1.8 V only IO banks in Kintex-7/Virtex-7 for a long time now, and I didn't see many complaints about that. I for one always choose 1.8 V level for peripherals over 3.3 V versions whenever possible because it's got some serious upsides and almost no downsides. 3.3 V IO gets in the way of utilizing finer silicon nodes, and as they become more affordable, more and more devices will ditch 3.3 V IO for many advantages offered by finer nodes.

author: ataradov
author_rank: Super Contributor
timestamp: July 11, 2024, 07:17:35 pm
content: Quote from: asmi on July 11, 2024, 06:28:52 pmThe core already works at 1.1 V and takes advantages of any new technology. The fact that you need beefier transistors on I/O cells should not be a huge issue.3.3 V would still remain relevant for a long time. But it is not even the issue here. Clearly they intended this to run at 3.3 V, but then could not figure it out after a couple mask changes, and then just gave up and released this half-baked device as is. Does not instill a lot of confidence.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 11, 2024, 08:05:28 pm
content: All my FPGA designs are all 1.8V I/O. I have not used 3.3V on an FPGA for years....Still use 3.3V with microcontrollers, and I have TXU0101 1V-5V <>1V-5V sc70 translators on tape and reel....

author: asmi
author_rank: Super Contributor
timestamp: July 11, 2024, 08:06:24 pm
content: Quote from: ataradov on July 11, 2024, 07:17:35 pmOf course it is an issue, because space on finer process nodes gets progressively more expensive, and at some point space taken by these IO cells might become a significant portion of the entire design, which kind of defeats the purpose of using finer node in the first place.Quote from: ataradov on July 11, 2024, 07:17:35 pmThat doesn't make any sense. There is nothing to figure out, you simply use the correct primitive from the tech library for the process that is provided by the fab, and you're done. If that primitive ends up not meeting specs, that's a fab's problem, not customer's.

author: asmi
author_rank: Super Contributor
timestamp: July 11, 2024, 08:10:32 pm
content: Quote from: glenenglish on July 11, 2024, 08:05:28 pmThat's the direction my designs are heading too. On my latest board I only had one IO bank powered by 3.3 V, and the main reason was that I wanted to use native TMDS support which requires 3.3 V Vccio.

author: langwadt
author_rank: Super Contributor
timestamp: July 11, 2024, 09:04:02 pm
content: Quote from: asmi on July 11, 2024, 08:10:32 pmI found an interesting feature on a Xilinx FPGA. While you can use 3.3V powered bank for LVDS input you cannot use it for LVDS output, once the IO voltage goes above ~2.9V the LVDS outputs gets powered off to protect them

author: asmi
author_rank: Super Contributor
timestamp: July 11, 2024, 09:15:22 pm
content: Quote from: langwadt on July 11, 2024, 09:04:02 pmYep, this is described in documentation - you can use LVDS receiver in bank with any Vccio (not just 3.3 V) provided that you don't use on-chip termination (and instead have external 100 Ohm termination resistor). MIG uses this trick for placing a system differential clock input in the same IO bank as regular memory IO pins.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 11, 2024, 10:20:23 pm
content: I run single 1.8V for VCCIO and VCCBRAM, AUX etc everything for most 16nm/28nm FPGA like xilinx, efinix etcThis means I have only two power planes to deal with Vddcore and 1.8V.. IE no 3.3V. Those go in the upper 4 layers (TOP, Vcore, GND, Vio ) and I dont need any caps on the bottom side...nor does the fpga have to reach down below the FR4 core to the bottom 4 layers for power....On 7 series though, 2.5V LVDS output, yes, need the extra small platelette. You can run them down to about 2.35V and they still make spec at full gas over temp. datasheet says 2.375V. It is worth it because you can save quite a bit of heat.1.8V LVDS compared ot 2.5 in xilinx is about 1/3 the power from memory......anyway, yeah Renases , bit of a mystery there. It's an interesting year for FPGA because you have Lattice AVANT E, Altera Agilex5, and new SERDES RISCV hardcore Efinix all being production available by year end.new Xilinx Spartan 8is interesting for some(lots of 3.3V IO)but lacks 1.8V IO (quantity) for me.

author: langwadt
author_rank: Super Contributor
timestamp: July 11, 2024, 10:35:10 pm
content: Quote from: asmi on July 11, 2024, 09:15:22 pmit was quite few years ago, I'm quite sure it wasn't in the datasheet at that point

author: asmi
author_rank: Super Contributor
timestamp: July 12, 2024, 01:14:53 am
content: Quote from: langwadt on July 11, 2024, 10:35:10 pmIit's been there for at least as long as I've been using these devices - so about 7 years:Quote

author: asmi
author_rank: Super Contributor
timestamp: July 12, 2024, 01:27:18 am
content: Quote from: glenenglish on July 11, 2024, 10:20:23 pmPretty much all of my boards contain DDR3 interface, so I still need at least 1.35/1.5 V rail as well, in addition to 1.0 and 1.8 V rails.Quote from: glenenglish on July 11, 2024, 10:20:23 pmDo you mean Spartan UltraScale+? If so, HDIO pins support 1.8 V standards among other. - though they are MUCH slower than good old HR ones. Also higher-spec devices will have dedicated pins for hard LPDDR5 controllers, so you won't have to spend HP pins on memory interfaces anymore (typical deal with HP banks in previous device families), and can use them for something else for a change.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 12, 2024, 05:36:27 am
content: yeah, they're HDIO. good for SPI etc...and the rest are XPIO, the 1.2V logic, but they are mostly MIPI banksI use LPDDR2(Zynq) or DDR4 (MPSoc) so I only need 1.2V extra....or HyperRAM ( non SoC) , cant remember but the HDIO are probably OK for HyperRAM... lets see -HDIO - pseudo diff output. true diff input but they do have IODLY blockshttps://docs.amd.com/r/en-US/ug571-ultrascale-selectio/Introduction-to-High-Density-I/O-BanksOn Versal they're 250 Mbps DDR. mmm not good enough for full speed hyperram. ah well. but good for motor controllers etc, right ?So 3.3V is clearly not dead, probably alot of automotive people wanting it

author: langwadt
author_rank: Super Contributor
timestamp: July 12, 2024, 01:13:41 pm
content: Quote from: asmi on July 12, 2024, 01:14:53 amchecked thee revision notes forhttps://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO05/15/2015 , Added note 2 to Table 1-55

author: asmi
author_rank: Super Contributor
timestamp: July 12, 2024, 04:21:31 pm
content: Quote from: langwadt on July 12, 2024, 01:13:41 pmNote 1 and additional narrative in "LVDS and LVDS_25 (Low Voltage Differential Signaling)" section (towards the bottom of the page 92 in current revision 1.10) has been added back in 2012. There is even a schematics added on how to AC-couple and DC-bias receiver in case incoming LVDS has different common voltage. So it's there for at least 12 years, which is why I thought it's been always there.

author: slburris
author_rank: Frequent Contributor
timestamp: July 12, 2024, 06:15:25 pm
content: As a hobbyist, my ears perk up at "lowest cost FPGA'. My low-end projects use XC6SLX9-2TQG144C chips, but they can be overkillfor some logic. Is it time to get excited? Let's take a look.Hobbyist friendly package, like a TQFP or the like? Oh, it's a STQFN. I will grumble, but at least it's not a BGA, so with care I can solder this.The lack of 3.3v I/O isn't a showstopper, but I'd have to think if I can rework some potential projects to run at 2.5v or deal with level shifting.I'm not a company, so I'm not likely to get a free eval board. So can I buy it? Well yes, not very many around, and prices are all over the mapfrom $126 (Digikey) to $292 (Verical). I know eval boards are ridiculously priced (usually), but still seems kinda costly for a low cost FPGA.Speaking of which, what does this chip cost and can I actually buy it? Hmm, neither Digikey nor Mouser even lists the chip (SLG47910V),not a good sign for easy availability. Oh, it's listed at Avnet. Except they have no inventory. And no pricing?? What does this thing actually cost??When can I actually buy chips???So I went to the Renasas site, surely they have pricing and inventory? Nope, no pricing information, and their "buy now" takes me to Avnet. Gee thanks. Sigh.I'm no longer excited. Guess I'll check back on these chips in 6 months to see if anything has changed.

author: ataradov
author_rank: Super Contributor
timestamp: July 12, 2024, 06:37:30 pm
content: Quote from: slburris on July 12, 2024, 06:15:25 pmI was excited 3 years ago when this was first announced. It is now 3 years later, still no chips and the new promised chips are not what was promised originally.The real talk will start when there are actual chips available. If they end up costing way more than promised, then this is DOA except for whatever real large volume customers they have.There will be boards with ICs soldered on them and they will be much cheaper. The current even boards are expensive because they use expensive sockets. And the device is pretty simple, you probably don't even need an eval board.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 12, 2024, 07:41:15 pm
content: The FPGA effort by renesas is a bit of a joke.I maintain its for some internal requirement, they really cant be serious about being an fgpa supplier ?!?!Maybe a thought bubble. Maybe their FPGA is one from TinyTAPEOUT ? lol@ slburris : Efinix have a 3.3V capable FPGA in a 100/144 QFP- the Trion series T20 is a fair chunk of FPGAThe T20 in a 100 TQFP also has on board 16MB flash memory chip, saving wiring....The tools are quite OK. basic but they do the job without surprises.https://www.efinixinc.com/docs/trion-selector-guide-v3.3.pdfhttps://www.efinixinc.com/docs/trion20-ds-v5.7.pdf

author: ataradov
author_rank: Super Contributor
timestamp: July 12, 2024, 07:55:15 pm
content: T20 is not in the same market as ForgeFPGA. On a 100 pin package, it uses half the pins for power supplies and configuration. And a lot of other pins are configuration straps that have specific pull-up/down requirements. They also have core supply with specific sequencing requirements with respect to VDDIO. The amount of support components is maddening.ForgeFPGA is more of a continuation of Silego Greenpak devices - a simple replacements for a bunch of logic ICs.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 12, 2024, 08:08:12 pm
content: Alex, you have used Efinix ? I've found the supply sequencing on Trion didnt matter at all (apart from Vcore first, then everything else) .... as long as everything was stable quickly before config begins.... easy enough to sequence core then vccio, just use the power-good from Vcore regulator for Vccio Enable. that is not difficult . the 144 QFP yes has more IO available...But I take your point that its not a PLD glue logic size FPGA, more like a "real FPGA" (that you can run a soft core on).Yes, an easy-to-use fpga has 1 supply rail , and internal flash config and jtag.My point was Efinix Trion is a modern FPGA with modern tools AND a QFP, not some relic from the 2000s (Spartan6) with unsupported tools.Lattice has some QFPs

author: ataradov
author_rank: Super Contributor
timestamp: July 12, 2024, 08:17:19 pm
content: Quote from: glenenglish on July 12, 2024, 08:08:12 pmI just made the board with T20. Have not used them in practice yet. I made a board out of curiosity. And the whole way I was annoyed by their configuration pins.But I like the IDE that you can download and continue to use without requesting a license every 6 months.Quote from: glenenglish on July 12, 2024, 08:08:12 pmBut that is still a requirement, so something that required additional components to sequence. Surprisingly, this sort of sequencing is what Greenpak and ForgeFPGAs are designed for.Quote from: glenenglish on July 12, 2024, 08:08:12 pmBut also requires a huge board area.Quote from: glenenglish on July 12, 2024, 08:08:12 pmThis is why I use Lattice MachXO2 HC. Single supply, plenty of I/O in a full range of pin counts.Quote from: glenenglish on July 12, 2024, 08:08:12 pmWell, it would be great if they could take pin assignments from SDC files instead of some goofy GUI tool. And not supporting tri-state pins directly is also not very "modern".Also, their IDE is very strange. They have the central widget set to be the log, so your editor is forced to be on a side panel. I guess they don't expect anyone to actually use their editor, just like most FPGA IDEs.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 12, 2024, 08:38:14 pm
content: agreed.although "But also requires a huge board area.". well you cant please everybody !I do like Lattice MACHX02.... great combination of features.Alex do you know if any of those flash based Lattice parts can reconfigure themselves from a bitstream once they are runningI need to have the fpga start on the internal flash config and then load a new config from a RS485 serial connection to a host.because -I'm looking at doing a (maybe) T20 in a front panel of a remote panel device.....- the on-chip flash memory gets it going (initial display and IO config) ) and the part then waits for the 'running' config file download on the RS485 serial wires that connect it to the 'main unit'. That way the front panel always has the correct (matching) firmware as the main control unit. .....On Trion, I would need to program a SPI FRAM , and then set a config bit and retrigger configuration from the SPI device. might work.... Efinix Titanium would be easier, since it can do a reconfig from a bitstream while operating . But no QFP for Ti

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 12, 2024, 09:41:48 pm
content: Quote from: glenenglish on July 12, 2024, 08:38:14 pmYes of course. They are still SRAM-based (contrary to the Actel Igoo series, IIRC) and can be reconfigured at any point (without reprogramming the internal flash) via JTAG.But if by "themselves", you mean without JTAG, then, the answer is, I think, no.If you're gonna do what you describe above, your best bet is to do this from a small MCU (or your main MCU if there is any on your board) which will handle the RS485 communication, check integrity of the bitstream (always a plus), and upload it to the FPGA SRAM via JTAG. Benefit is that the code for doing this will be, for a large part, FPGA-agnostic and will be reusable. You'll only need to port a small section of MCU code for each FPGA.

author: ataradov
author_rank: Super Contributor
timestamp: July 12, 2024, 09:50:13 pm
content: Quote from: glenenglish on July 12, 2024, 08:38:14 pmAs far as I know it is not possible. They don't support partial reconfiguration and full reconfiguration would erase the SRAM. You can update the flash from the FPGA logic, but if you need this to be highly dynamic, it will wear out the flash fast.They do support reconfiguration from the external SPI flash. I have not looked into the specifics, but the same FRAM might work. You would need to store the received bitstream somewhere anyway.The configuration method is selected thought the NVM fuses, so it might be tricky to switch in run-time.There is also a dual-boot mode with a fail-safe image. But it might not be as useful, since the "safe" image is stored in the external device and it always tries to configure from the external device first.In general with updates like this, it might be easier to have a small external MCU to load the new bitstream over JTAG. Let FPGA configure from the safe internal flash, receive the new image, tell the MCU to reconfigure with the new image over JTAG.And unlike flash configuration over JTAG, SRAM configuration is very easy.

author: slburris
author_rank: Frequent Contributor
timestamp: July 12, 2024, 10:06:56 pm
content: Quote from: glenenglish on July 12, 2024, 07:41:15 pmI have not looked at Efnix parts. I'll have to study the datasheet.Since I can get the Spartan 6 for $6-7, I'd like to find something less than that for smaller use cases, and have it commonlyavailable and in stock (dk/mouser). While I'm stuck with ISE, I'm at least familiar with its quirks. I've used Vivado (for S7 and Artix 7),and it's an entirely different set of quirks!I did a couple of projects a few years ago with the MachX02 1200, and it was pretty easy to use. Maybe I should revisit them.Huh, actually, I can get the LCMXO2-1200HC-4TG144C for $2.61 qty 1, that's nicely in the "cheap" category.

author: ataradov
author_rank: Super Contributor
timestamp: July 12, 2024, 10:09:29 pm
content: Quote from: slburris on July 12, 2024, 10:06:56 pmWhere? This is a highly irregular price even for chap sources. I would not rely on getting it at that price consistently.

author: slburris
author_rank: Frequent Contributor
timestamp: July 12, 2024, 10:15:50 pm
content: Quote from: ataradov on July 12, 2024, 10:09:29 pmAt LCSC:https://www.lcsc.com/product-detail/Programmable-Logic-Device-CPLDs-FPGAs_Lattice-LCMXO2-1200HC-4TG144C_C1521637.htmlI order a lot from them, so I'll probably just toss 10 or 20 of them into my next order of other parts.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 12, 2024, 10:18:50 pm
content: https://www.digikey.com/en/products/detail/efinix-inc/T20Q100F3C3/19100262includes on package flash chip for USD$9 qu 1T20 can run a fair size RISC-V (efinix supply canned IP) and has a megabit of block ram.However ! if you want a small, single power pin FPGA, MACHX02 is hard to beat......the larger ones can run a small microcontroller....

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 12, 2024, 11:01:42 pm
content: back to the Renesas(as the T20 above is 20x the size)Let's apraise the datasheetOK so it is low power when it's doing nothing : 50uA at room temperature. 1mA at 85CBRAM clock freq : 87 MHz at 25 degc, 45MHz at 85Cwhat's the story with this silicon process? It's like its made with Z5U / Y5V dielectric.....32 bit counter : 56MHz at room temperature. no speed demon.FF to LUT- FF : 182 MHz room temp. yeah well that's not too bad I guesshas a 5 input LUT/FF, (1120 of those) ---- they are formed as fractuable 6 input LUT and dual FF, in a CLB array of four of those.reading how the shift registers are implemented, and the terminology used , you'd think you were reading a Xilinx manual.That the CLBs can be used as distributed memory is good.The block rams are are oK with basic features like variable aspect ratio etc, 16kb in size.If this was a 0.8mm QFP32 and ran 3.3V, it would be a a good option for many.Wonder what the tools do ? Does it use / based the open source toolchains ? etc like ICE40 ? Gatemate ?Gatemate is cool.I cannot see how this competes in a world where ICE40 is so easy , available, known toolchains and worksalthough, for the number of LUTs, it does have more multipliers and ram resources compared to an ICE40other options- largest MACHXO3 device in a QFP is MachXO3LF-2100 (100QFP) and 3.3V core. GOWIN has QFP.

author: ataradov
author_rank: Super Contributor
timestamp: July 12, 2024, 11:29:01 pm
content: Quote from: slburris on July 12, 2024, 10:15:50 pmI would not rely on that price long term. LCMXO2 availability on LCSC is really spotty. They come and go fast.

author: ataradov
author_rank: Super Contributor
timestamp: July 12, 2024, 11:33:15 pm
content: Quote from: glenenglish on July 12, 2024, 11:01:42 pmYosys for synthesis and a custom P&R tool. We investigated that in detail in the other thread.Their "project" contains all the source code. There are no separate Verilog files. Your project is one self contained file. They do it so that you can send that project to the factory for mass programming, which seems like their main goal here.This also has a potential to be a version control nightmare.Quote from: glenenglish on July 12, 2024, 11:01:42 pmI would be very skeptical of those clocks. Because it is using Yosys, there is no timing-driven synthesis or timing constraints of any sort. You just get what you get.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 12, 2024, 11:35:11 pm
content: what ? so its up to the designer to count the number of logic levels in series to figure out of something will meet timing??

author: ataradov
author_rank: Super Contributor
timestamp: July 12, 2024, 11:38:03 pm
content: I think the tools are designed to meet internal timings and just report the maximum frequency for the design. But there is no way to specify setup/hold times for the I/O pins.Again, the idea here is not performance, but simplicity. And they probably wanted all those things, but it is just not in the OSS tools and they don't want to invest resources to implement it.This is the same thing you get with ICE40. So, I guess it can work, but does not really make me feel good putting that into mass produced things.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 12, 2024, 11:49:10 pm
content: Quote from: ataradov on July 12, 2024, 11:38:03 pmYes, that's one limitation of the yosys toolchain - I don't know if they use nextpnr for PAR (or a derivative thereof), but nextpnr, last I checked, indeed didn't allow specififying any timing constraints for IOs. Which is a bummer.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 12, 2024, 11:55:51 pm
content: except as a teaching tool how could one ever time anything .. (and because it doesnt teach about timing, I wonder just how useful??) OH ok so it times internal paths. right. yes.... but not to the IO pinI guess the idea is if the individual logic LUT can run at 100 MHz, then if the clock of the system is no higher than 10 MHz, it will probably make timing on many / simple designs (< 10 LUT logic levels)I also see that MACHX03 in QFP is unobtanium.There would a use in the community for someone to put BGAs with bypass caps and a core regulator into a 100QFP 0.65mm leadframe ? whattya think ? Not to make any money, I mean just to enable people to experiment a bit more .... Or a big DIL DIP

author: ataradov
author_rank: Super Contributor
timestamp: July 13, 2024, 12:05:15 am
content: For the internal logic, you don't need to guess or estimate. Even if you have 100 levels of logic, the tool just calculates the delay and limits the maximum clock for the FFs around the logic. But this breaks apart quickly with multiple clocks in the design. Without ability to specify relative timing, things may get hairy. But I think for 1K LUT device, it is probably fine.The bigger issue is the I/O pin timing. You just need to have very generous setup and hold times for anything to work.Is there even technology to do that? Even just placing decoupling capacitors into the package increases the packaging cost a lot. I can't imagine placing a BGA IC and supporting components is cheap, if possible at all.Single power supply versions of LCMXO2 are really easy to use already. Probably the least annoying FPGAs out there. And they are plenty powerful for experimentation.

author: nctnico
author_rank: Super Contributor
timestamp: July 13, 2024, 09:40:49 am
content: Quote from: glenenglish on July 12, 2024, 11:55:51 pmA small PCB with castellated holes at the side (like uBlox and BLE / Wifi modules) is easier to make. Companies like JLCPCB can also take care of assembly.

author: iMo
author_rank: Super Contributor
timestamp: July 13, 2024, 04:32:07 pm
content: Quote from: mikeselectricstuff on July 09, 2024, 08:04:33 am1k Luts - too smallish today, imho. What you could try with it? PicoRV32_small @16-20MHz clock perhaps?

author: ataradov
author_rank: Super Contributor
timestamp: July 13, 2024, 04:55:29 pm
content: Not everything needs an MCU. Sometimes you just need a real time reaction to events. The device is big enough to do motor control with necessary protections, for example.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 13, 2024, 07:43:04 pm
content: I think Alex has the best option- LCMX02 is probably hobbyists best go-to option at the moment . I'v done a few professional designs in recent times using LCMX02s to solve things like- high speed LVDS based large IO expander port serializer/deserializer,-PDM microphone x4 array input to TDM PCM output (digital cic filters, multiplexing) etc.------ all good applications for FPGAs, not easy nor practical applications for microcontrollers - where timing must be cycle correct for every I/O down to 15nS ......I'll have to ask JLC what their minimum reasonable castellated hole size is. YEARS ago, I built some large PLCC modules by buying leadfreame-packaging and the fingers were thermosonically bonded down onto a small PCB.

author: slburris
author_rank: Frequent Contributor
timestamp: July 21, 2024, 01:27:51 am
content: Quote from: slburris on July 12, 2024, 10:15:50 pmWell, I ended up ordering about $300 of LCMXO2 in various sizes (100 and 144 pin packages), just to have parts in stock for projects. That should keep me going for a year or so for "low cost" FPGAs until something better comes along.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 21, 2024, 02:25:24 am
content: Quote from: slburris on July 21, 2024, 01:27:51 amIn various sizes, do you mean only pin-wise, or also the number of LUTs? Because if you have bought only -1200 ones, that's cool but a bit limited. The MachXO2 comes with up to about 7000 LUTs (-7000 variant) and you can certainly fit much more logic in that, so for using these on various projects, I would have bought maybe a set of different variants, but maybe that's what you did.

author: ataradov
author_rank: Super Contributor
timestamp: July 21, 2024, 02:34:01 am
content: They seem to only have the lowest speed grade at this cheap price. And Lattice devices are not that fast to begin with. It is still fine for experiments, but many real projects will not do well at speed grade 4. And speed grade 6 devices cost the same as on Mouser.Also, I just noticed " View marketplace suppliers’ inventory" on LCSC. So they are also about to turn into crap aliexpress/wish clone.

author: slburris
author_rank: Frequent Contributor
timestamp: July 23, 2024, 05:47:50 pm
content: Quote from: SiliconWizard on July 21, 2024, 02:25:24 amBought both pin and LUT variations in all nice leaded packages which are easy for me to solder. Also have XC6SLX9 in LQFP-144 for the most LUTs. And yeah, I know you can't directly compare LUT counts, different architectures, etc. Beyond that, I'm out of hobby friendly soldering options. Then I've used complete boards as "modules", from Digilent, random boards from Aliexpress (yes, I know), and ugh, reclaimed bitcoin miners.Who wouldn't want a board with a XC6SLX45 on it from a place called Grandmas Secret Closet?https://www.ebay.com/itm/124648331917I'm sure it's totally fine!

author: glenenglish
author_rank: Frequent Contributor
timestamp: August 07, 2024, 12:24:45 am
content: So.. I am now seeing Renesas ForgeFlash FPGA eval kit advertising in my EEVBLOG feed :-)The chip datasheet says VCCIO 1.7 to 2.75VThe eval kit says VCCIO 1.8 to 3.6they cant both be right.I'll ask the question

author: ataradov
author_rank: Super Contributor
timestamp: August 07, 2024, 12:41:56 am
content: It is pretty clear that the kit was designed before the they knew that I/O ring is broken on the device. Then they decided to not fix the bug and declare it a feature.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 07, 2024, 12:45:12 am
content: Max VCCIO at 2.75V. Sales will be interesting.

author: glenenglish
author_rank: Frequent Contributor
timestamp: August 13, 2024, 11:09:47 pm
content: I am going to get an eval board and apply 3.3V (you can) and measure impact on power consumption, and logic thresholds.My bet is the static power on the HVIO banks goes up more than they want but surely that wouldnt stop them selling it as 3.3Vperhaps there is an issue with level shifting between IO cells and the core going bad.Renesas sent me a reply to my question which just says "Has been actioned". But there's no changes to the documentation.... useless.I'll ask the FAE.

author: ftg
author_rank: Frequent Contributor
timestamp: August 14, 2024, 07:02:08 am
content: Has anyone of you actually received the SLG7EVBFORGE ForgeFPGA devboard mentioned in the first post?I sure have not.

author: glenenglish
author_rank: Frequent Contributor
timestamp: August 14, 2024, 11:05:41 pm
content: Got a reply from Renesas"There is an errata on this, and the new silicon works at 3.3V, there will be a datasheet update this quarter"so, 3.3V yes.

author: ataradov
author_rank: Super Contributor
timestamp: August 14, 2024, 11:06:58 pm
content: What an amateur hour. What errata? They rewrote the whole datasheet from the original version. It is not something you do by mistake.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 15, 2024, 05:24:16 am
content: Quote from: ataradov on August 14, 2024, 11:06:58 pm'Yes, a novel way to release 'engineering samples' ! Maybe they ran so many, they wanted some design wins to use them up !

author: bson
author_rank: Unknown
timestamp: August 16, 2024, 07:59:08 pm
content: OTP??? For developing bus timing, arbitration, control logic, clocks?Is there a version with internal flash?

author: ataradov
author_rank: Super Contributor
timestamp: August 16, 2024, 08:04:33 pm
content: It can be configured in a RAM-only mode for development over SPI interface. There is no flash version. Their whole story for this device is that they will mass program it for you OTP. The whole toolchain is oriented towards that.And it can also act as a master and load the firmware from any SPI flash too.

author: bson
author_rank: Unknown
timestamp: August 16, 2024, 08:27:40 pm
content: The board has an "emulation" mode. The chip datasheet doesn't mention any emulation mode; it lists: external SPI flash, MCU, and OTP. What is this emulation mode? There is no schematic for the board in post 1, the documentation is literally just a single page quickstart. Does this simply mean the board has an external SPI flash that's programmed in "emulation"? They're not exactly using this word according to its meaning (physical impersonation).I'm wondering what it takes to do development with this part; if it needs external SPI flash that's fine, as it can be left depopulated or removed later. But I'd find internal flash far more practical for a CPLD.

author: ataradov
author_rank: Super Contributor
timestamp: August 16, 2024, 08:36:01 pm
content: They don't position it as a CPLD. It is a direct continuation of a GreenPAK line, which always targeted OTP process.No idea about emulation mode, I would assume this is just the SPI slave (MCU) mode where USB interface IC acts as a master.Having SPI flash will take up I/O pins, which are already limited. In that sense, having a configuration master that can tri-state its pins after the configuration is done is a big plus.

author: bson
author_rank: Unknown
timestamp: August 17, 2024, 07:00:13 pm
content: So they can load config from internal RAM, or load LUTs etc from SPI as if it were addressable RAM? I don't see this mode listed in the datasheet...

author: langwadt
author_rank: Super Contributor
timestamp: August 17, 2024, 09:10:37 pm
content: Quote from: bson on August 17, 2024, 07:00:13 pmdatasheet points to this,https://www.renesas.com/us/en/document/mah/forgefpga-configuration-guide

author: ataradov
author_rank: Super Contributor
timestamp: August 17, 2024, 09:24:02 pm
content: By RAM I meant the actual configuration RAM. There is nothing to load once it it loaded with the config. I don't know if it is actually RAM cells or something else, but the memory that in the final design gets loaded from the OTP memory.That "RAM" can be loaded from SPI in passive or active mode.It is loaded as a bit-stream, jut like any other FPGA would load, so it is not really addressable, you just push the bit-stream over SPI and it configures itself.

author: PartialDischarge
author_rank: Super Contributor
timestamp: February 05, 2025, 04:34:27 pm
content: Did anyone get the ForgeFPGA Evaluation Board? Seems like a really nice device with good enough free software, but the SLG47910 is still not available on Mouser/DK etc....

author: rounin
author_rank: Regular Contributor
timestamp: February 10, 2025, 04:08:35 am
content: Quote from: glenenglish on August 14, 2024, 11:05:41 pmLooks like SLG47910 datasheet rev 1.03 (dated Nov 8th 2024) says VDDIO can be in 1.71V - 3.465V. So maybe good for 3V3 now? I was debating getting into the greenpak cplds, after playing with the block diagram UI and some samples i kinda of want to use a small FPGA instead I can write verilog for. No being able to eg diff the verilog or reuse blocks of code / gates was kinda annoying for dev effort. I did just do a PCB with a trial greenpak cpld as a supervisor / reset voting logic / button debouncer. Might do a version with the SLG47910 too if I get the dev kit.Ordering a dev kit,digikey says mid-march for deliveryin stock at mouser. The actual chip seems to be unavailable in distribution still, I'll request samples...I don't know. These looked good at first, but maybe a ice40 LP384 in a QFN32 is better, although lower LUT count. That has internal config memory, my volume might be to low for OTP to be a good idea. Hmm, hopefully will play with the dev kit and read datasheet more next week, compare prices including a boot flash chip.

author: shabaz
author_rank: Frequent Contributor
timestamp: February 10, 2025, 04:48:45 am
content: The QFN package for that part is slightly non-standard, I made a little easy-to-solder breakout board for it (also works with the GreenPAK parts). The Gerber files are attached in case anyone wants such a board. There is space on the underside for any SMD decoupling caps, and the board can be soldered onto a standard 24-pin DIP pin header if desired (or just use a couple of strips of normal SIL pin headers of course).

author: PartialDischarge
author_rank: Super Contributor
timestamp: February 10, 2025, 07:31:30 am
content: The dev board has like 8 ICs in it. But the MOQ for the SLG47910 is 5000 units, ie 10000€.So unless Mouser/DK stocks it no way I'm doing anything with it...Just asked Lattice for a free startup IceCube2 license and they gave it to me, and ICE40 units are available at 2€ so I guess Lattice wins here

author: rounin
author_rank: Regular Contributor
timestamp: March 17, 2025, 04:04:22 am
content: Got the dev kit and Renesas also sent me another 10 sample ICs after I asked, so I have a few to play with nowThrew together a little test board with a random hodgepodge of other things I wanted to try out, haven't laid it out yet. Tried to make it so I can boot the FPGA over USB or from the SPI flash.Probably would have been cleaner to use a native USB/SPI instead of FT260 USB/I2C and then another I2C/SPI bridge, but I already have a bunch of FT260S and this way the PC can talk to the other stuff on the I2C bus too.

author: glenenglish
author_rank: Frequent Contributor
timestamp: April 09, 2025, 09:41:36 pm
content: The (new) AVNET AU15P FPGA dev board uses the Greenpak device :SLG7AV46723Vas a supply rail sequencer. it is a simple attractive idea, I just have not had any experience with programmign these beasts, woulds need to get it right on a test PCB with like 25 of them to program, since they are OTP !they went to discrete power supplies on this PCB compared to a sequencing PMIC. probably because VCCINT can get high and maybe most PMICs cantr do the 10 amps at 0.85V.or maybe they wanted ot showcase a few mfrs, or had plenty spare in stock...https://www.avnet.com/wps/wcm/connect/onesite/072cc291-885c-466d-9fa6-6e48eae3e900/AUB-15P-DK-UG-V1P3.pdf

author: zapta
author_rank: Super Contributor
timestamp: April 11, 2025, 01:41:29 am
content: Quote from: PartialDischarge on February 10, 2025, 07:31:30 amYou can program ICE40's such as ICE40LP384-QN32 using the open source Apio suite. It's inspired by platformio and provide simple commands such as 'apio build', 'apio uplad', 'apio test' and 'apio sim' that does what you would expect. It's platform agnostic and runs on Windows/Mac/Linux.

author: glenenglish
author_rank: Frequent Contributor
timestamp: April 11, 2025, 02:26:08 am
content: Renases GreenPak -So, turns out the way to develop with these things is to get the emulator kit....https://www.renesas.com/en/products/programmable-mixed-signal-asic-ip-products/greenpak-programmable-mixed-signal-products/slg4dvkadv-greenpak-advanced-development-boardhttps://www.renesas.com/en/document/mat/greenpak-advanced-development-platform-user-guideand there is also a ZIF programmerhttps://www.renesas.com/en/products/programmable-mixed-signal-asic-ip-products/greenpak-programmable-mixed-signal-products/other-greenpaks/slg46722v-skt-greenpak-slg46722-development-kit-socket-adapter

author: PartialDischarge
author_rank: Super Contributor
timestamp: May 04, 2025, 07:11:05 am
content: A new FPGA from them is coming, SLG47921V in QFN48. Specs seem to be double of the SLG47910V in terms of LUTs, DFFs and memory.VDDcore is 1.1V and VDDIO is from 1.7 to 3.3V