Phase Locked Loops (PLL) - Page 1
Forum section: electronics / beginners

author: richard1991
author_rank: Contributor
timestamp: January 11, 2018, 12:18:58 pm
content: Hi. In Art of Electronics (2nd Edn) on page 641 it says "At that point, the filtered output of the phase detector is a dc signal, ..."Now, "that point" is when there is a lock. So, I understand that, actually, when there is lock, you can say the output of the phase detector is a dc signal. At that point (lock) the filter is not modifying the phase detector output, because it's steady dc. Is this correct? Just checking. Thanks.

author: Rerouter
author_rank: Super Contributor
timestamp: January 11, 2018, 12:27:15 pm
content: In reality as its part of an imperfect feedback loop there will still be a small amount of correction happening, however to a bandwidth limited scope or meter is appears as DC, or near enough that most people stop caring,Similar to the + and - input of an op amp wired as a buffer, when measured across you see approximately DC, even if the signal is changing.The goal is designing your PLL such that those correction are so small that you stop caring to measure them,

author: richard1991
author_rank: Contributor
timestamp: January 11, 2018, 12:37:29 pm
content: So, when there is lock, in a well designed PLLs, it's very close to dc. Also, the period of the signal should be very small, such that, I suppose the filter has not much filtering to do. Anyway, I'm happy to think when there is lock the filter is doing practically nothing to the signal output from the phase detector. I have the understanding that the output from the phase detector is not zero volts at lock.

author: Benta
author_rank: Super Contributor
timestamp: January 11, 2018, 05:23:12 pm
content: Your quote says "thefilteredoutput of the phase detector", which is correct.I prefer not to use the term "loop filter", but rather "Loop Controller", as this is the only place where you can modify the PLL's dynamic characteristics.Do not underestimate the function of the Loop Controller, it is crucial for how fast the PLL acquires lock and how well it keeps lock when disturbed.When talking about type I PLLs, which are characterized by having a constant phase difference between the input signals (when locked), the output of the phase comparator is a square wave.For type II PLLs, which have zero phase difference between the inputs, the output from the phase comparator is "off", but with extremely narrow spikes, both positive and negative. These occur because the PLL tends to "hunt" around the zero phase point, just to keep the loop alive.

author: albert22
author_rank: Regular Contributor
timestamp: January 11, 2018, 05:26:44 pm
content: Type I and type II phase detectors are shown in the book. Type I, for example an xor gate, will not have a DC output, but a digital output which is a variable duty cycle pulse train that should be filtered to get the DC that controls the VCO.Type II, will give positive, negative pulses or zero depending on the phase difference, to bring the phase difference to zero. Basically positive pulses charge a capacitor and negative pulses discharge it. When the difference is zero there will be no more pulses and the voltage at the capacitor stays at the same value. The voltage at the capacitor is the vco control voltage.For example the output of the type II phase detector may be +1, -1 and 0v not the DC value that controls the VCO.Hope that helps, I tried to made it as simple as possible.Regards

author: Wimberleytech
author_rank: Super Contributor
timestamp: January 11, 2018, 05:37:41 pm
content: Quote from: richard1991 on January 11, 2018, 12:37:29 pmIt might be helpful to work the signal flow in reverse.At lock, a specific frequency must be output from the VCO.To achieve that specific frequency, a particular voltage is required as input to the VCO.For the example in ART, an exclusive OR is used for the phase detector and a simple RC as the filter.Clearly, to achieve some average voltage (the one needed by the VCO to achieved the desired frequency), the XOR must output a digital signal with the appropriate duty cycle to achieve the desired (average) VCO voltage.So, in this case, the filter is critical to filter the XOR output.Phase detectors that I have designed are far more complex than an XOR. They have all been implemented in CMOS using charge pumps to convert the PD output to an analog value. In lock, such phase detectors will generate an equal pump up followed by an equivalent pump down so that the average value remains constant. Even so, the detector will be constantly searching up and down. Filter is always smoothing oscillation.I hope this aids your understanding.

author: w2aew
author_rank: Super Contributor
timestamp: January 11, 2018, 09:21:30 pm
content: If it's helpful Richard, I have a 20 minute video covering the basics of PLLs - which illustrates the operation of type I and II phase detectors as well as the other blocks.

author: rx8pilot
author_rank: Super Contributor
timestamp: January 11, 2018, 11:29:39 pm
content: Another winning explanation from W2AEW.......It takes genius to explain complicated to common folk like me.Short and misplld from my mobile......