hybridfree/eevblog-posts huggingface dataset:
lpc2103: PWM for Stepper Motor - Page 1
Forum section: electronics / general

author: s.mosfet
author_rank: Contributor
timestamp: February 12, 2011, 04:28:30 pm
content: I should control 2 Stepper Motors with the LPC2103 microcontroller (ARM).It supplies:- 4 timers- each timer can produce 3 PWM signals.The problem is that i should produce 4 PWM signals to control the motor with 4 phases (see pic)...How to do this?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: February 12, 2011, 05:33:39 pm
content: You wouldn't use PWM mode as you want to control the position of both edges.The set/clear on match functions are probably useable for this if there are enough pins.

author: Unknown
author_rank: Unknown
timestamp: February 12, 2011, 05:37:34 pm
content: Are you allowed to use external ICs or you must only use the NXP MCU?

author: JohnS_AZ
author_rank: Frequent Contributor
timestamp: February 12, 2011, 05:58:28 pm
content: You wouldn't use PWM unless you wanted to microstep the motors. Plain digital outputs into a driver transistor should do fine.

author: s.mosfet
author_rank: Contributor
timestamp: February 12, 2011, 06:28:37 pm
content: i would use only the MCU (and a driver IC..)....Can i use the PWM outputs to make these types of signals?or i must create it with the code?

author: JohnS_AZ
author_rank: Frequent Contributor
timestamp: February 12, 2011, 06:42:16 pm
content: Even if you use PWM, you'll still need to step the outputs in the proper sequence to drive the motor.You can either do the step sequence in code, or you can add external circuitry to generate it. I would do it in code.

author: Unknown
author_rank: Unknown
timestamp: February 12, 2011, 06:45:54 pm
content: Then you can use a Capture-Compare module or even a timer connected to the main clock with a suitable divided.As mentioned, you do not need to use PWM for single or half stepping. The final application might be a bit noisy when the motors are rotating.There are external drivers that you can just assert the direction and then send clock pulses for the required number of steps. They include the power drivers (H-bridges). I have used one from ST in the past and still have the schematic on paper if you want to go down that route and simpy use a stepper motor in your applications.Hvae a look on Microchip, they have an excellent app-note on stepper motors fundamentals.
showing a pic output up to 15V via high resistance - Page 1
Forum section: electronics / general

author: Simon
author_rank: Unknown
timestamp: February 25, 2011, 06:57:40 pm
content: I'm building a project where it would be advantageous for me to be able to let 15V be seen on the PWM output of the PIC via a 100+ Kohm resistor. Will I do any damage ?

author: jimmc
author_rank: Frequent Contributor
timestamp: February 25, 2011, 07:53:33 pm
content: Simple answer is... no damage.Of course the PIC pin will never rise to more than approximately Vdd + 0.7v (even if Tri-stated or configured as an input).Looking at the data-sheet for the 16F628 (as an example) Section 17.0 - Electrical specifications - Absolute Maximum ratingsThe output clamp current for Vo < 0 or Vo > Vdd is+20mA .Similarly the input clamp current for Vi < 0 or Vi > Vdd is+20mA so your 100uA max. is safe with a 2000% margin. ((15v-5v)/100k)(There is an overall limit of 300mA for Vss and 250mA for Vdd, so not all I/O pins can take the maximum current simultaneously.)Jim

author: Simon
author_rank: Unknown
timestamp: February 25, 2011, 07:57:39 pm
content: Thanks, I thought there was some sort of protection circuitry but not sure if it was just there as extreme last resort

author: Zero999
author_rank: Super Contributor
timestamp: February 25, 2011, 08:35:17 pm
content: Yes, thre's no chance of it doing any harm. The PIC has built-in protection diodes and the current will be a mere 100µA. There's even an application note by Microchip which involves connecting the mains to an I/O pin via a 1M resistor.
PICkit3 - linux command line programmer.... when.... - Page 1
Forum section: electronics / general

author: adam1213
author_rank: Regular Contributor
timestamp: February 09, 2011, 10:13:24 pm
content: from Re: Wanting to begin using AtmelQuote from: EEVblog on February 09, 2011, 04:39:22 amWhen is a linux command line programmer going to come out (/are ever going to make one?Currently I have not got a PICkit2 or PICkit3 as if I ever want to use mplabx on linux to debug it has to be with the pickit3 not the pickit2. However most of the time I just want my make file to be able to call the compiler and call a programmer for the device.It would be nice if the PICkit3 could just pretend to be a PICkit2 some times.... then I might know which one to get.
MCU Programing Forum Section. - Page 1
Forum section: electronics / general

author: PeterG
author_rank: Frequent Contributor
timestamp: January 31, 2011, 05:45:58 am
content: I would like to see a forum section or the main stream programing languages (Basic, C and ASM). Given the well balanced nature of this Forum, i think it would work well.Given that most projects these days involve some form of MCU, i feel this is a natural extension.Anyone else feel this would benefit the forum and its members?Regards

author: tyblu
author_rank: Frequent Contributor
timestamp: January 31, 2011, 06:55:35 am
content: I think other forums fill this niche quite well: RenesasRulz, Four-Three-Oh, AVRFreaks, Microchip forums, then fall back to Electronics&Robotics (Stack Exchange beta site).

author: EEVblog
author_rank: Unknown
timestamp: January 31, 2011, 06:59:43 am
content: Quote from: tyblu on January 31, 2011, 06:55:35 amI don't disagree. But if people want to ask here because it's where they hang out, then I think a category is a good idea.Dave.

author: Unknown
author_rank: Unknown
timestamp: February 01, 2011, 10:56:46 am
content: I can see why a vendor-neutral forum might be useful, you can't very well expect a balanced answer on something like AVRFreaks. Plus it makes for more interesting flame wars.I'm sure there are plenty of other forums where people could get the same information, but no harm in creating another as long as there is enough interest.

author: Mechatrommer
author_rank: Super Contributor
timestamp: February 01, 2011, 03:38:29 pm
content: i'm glad with the new section. but i'm not sure what Dave think on the direction of eevblog, or his interest. i mean software vs hardware design, analog vs digital, things like that.

author: Simon
author_rank: Unknown
timestamp: February 04, 2011, 06:53:08 pm
content: hopefully all aspects of electronics are brought to the forum. analogue still has it's place as does descrete electronics. there was a time when you didn't just whack an MCU in there but we probably don't realize how much used to be done with logic gates and transistors.The thing with a forum for C and Basic is Who's C and Basic, true enough I head over to the mikroe forums when I have a software issue as they made the software. I once suggested a more hardware section ansd they refused.
AVR - ATmega Zero Cross Det. - Page 1
Forum section: electronics / general

author: delwinbest
author_rank: Newbie
timestamp: February 02, 2011, 07:44:00 pm
content: Howdy all,Know its been done before and there are hundreds of examples out there... but I'm got an awesome twist I'm trying to work with here.It includes:8 Analog InputsATmega16Rigol scope (ps don't give up guys working in the dis-assembly of the Rigol 1052 firmware in another thread)Current TransformersSome C programmingSo I'm making use of the on chip multiplexer with is switching the Analogue to Digital Converter (ADC) as WELL as the Comparator.My system is governed by interrupts, every second or so it changes the MUX to the next input, it then disables the ADC and enables the comparator and waits for a zero crossing, this multiplexing is not a problem and its all working, as far as I know.The strange thing I\m running into is this, I'm not using the comparators interrupt, instead, I've configured it to Capture the contents of Timer1 (for frequency measurement), so the comparators interupts area and the Timer1 Input Capture Interrupt is enabled. This works fine, however, I'm now unable to select the rising or falling edge as a trigger, it only interrupts on the falling edge.And in theory this should not be so... or do I have this wrong?Anyone ever worked on something similar?Ultimately I want to measure the frequency and amplitude or all inputs.

author: Psi
author_rank: Super Contributor
timestamp: February 02, 2011, 11:42:42 pm
content: There are three things i noticed in the datasheet that may be something to do with your issue....There is this bit in the datasheet about the comparators rise/falling edge triggering"When changing the ACIS1/ACIS0 bits, theAnalog Comparator Interrupt must be disabledbyclearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when thebits are changed."The timer also says this"Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for theInput Capture unit. The Analog Comparator is selected as trigger source by setting the AnalogComparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register(ACSR). Be aware that changing trigger source can trigger a capture.The Input Capture Flagmust therefore be cleared after the change."Also, i noticed this text on the ACIC bit for the comparator"The comparator output is in this case directly connected to theInput Capture front-end logic,making the comparator utilize the noise canceler and edge selectfeatures of the Timer/Counter1 Input Capture interrupt."maybe you need to change the edge select mode for the timer and not the comparator ?

author: delwinbest
author_rank: Newbie
timestamp: February 03, 2011, 11:46:35 am
content: Quote from: Psi on February 02, 2011, 11:42:42 pmFantastic! Can't believe I missed this!Bit 6 – ICES1: Input Capture Edge SelectNo to continue with peak measurement.Thanks a mil.
help with HP 35s - Page 1
Forum section: electronics / general

author: dilbert
author_rank: Contributor
timestamp: April 09, 2011, 01:20:09 pm
content: Hello everybody,this is my first post.I write as a user of Hp calculators,in particular of the new 35shttp://en.wikipedia.org/wiki/HP_35sIt is a great calc,but it misses three big things:-a dozen-plus list of bugs-no I/O whatsoever,so you cannot update/hack/fix it-2032 instead of AAA batteriesThis the teardown:http://i.cmpnet.com/embedded/2008/February08/0208esdTDNass02.gifhttp://www.finetune.jp/~lyuka/interests/calc/hp35s/It uses a modern 8502 made by Sunplus Tecnology(SPLB31A),but i also get references to Generalplus GPLB31A.Datasheet:http://www.generalplus.com/products/lcdcontroller/datasheet/GPLB31AV14_ds.pdfNow,as the datasheet says there should be a serial-RS232-compatible Tx/Rx couple of pins(I'm sorry i a have an IT background,not an electronic one) coming out of the chip,right?Where are they in the board?Can this thing be hooked up to a pc?It will make hundreds of users very,very,very happy.Thanks guys,Nicola

author: Unknown
author_rank: Unknown
timestamp: April 09, 2011, 01:45:47 pm
content: Not much point in connecting to the UART pins if the firmware does not support it, the firmware will have to configure the UART and do something with the data. If the firmware supports it and the pins are not used for something else, connecting it to a PC via a logic-level (3.3V?) to UART converter should be fairly straightforward.

author: dilbert
author_rank: Contributor
timestamp: April 09, 2011, 02:20:20 pm
content: I forgot the firmware.Who knows.Only HP does.Where are on the board those pins?Thanks

author: Zero999
author_rank: Super Contributor
timestamp: April 09, 2011, 03:40:15 pm
content: Just read the Wikipedia link.I have an old HP 35 I got from an office clearout at work a few years ago. I wonder how much it's worth? Not that I'm selling it any time soon..

author: EEVblog
author_rank: Unknown
timestamp: April 10, 2011, 02:29:42 am
content: If Cyrille didn't bring the RS232 pins out the pads on the board for troubleshooting et.al then it's likely the firmware does not have any UART capability at all. In which case it's pretty pointless to try I think.Dave.

author: AdShea
author_rank: Contributor
timestamp: April 11, 2011, 04:04:04 am
content: Sadly they don't make them like the HP-41C anymore.
A tool for updating Lattice ECP5 BRAM contents after routing with NextPNR - Page 1
Forum section: electronics / general

author: berke
author_rank: Frequent Contributor
timestamp: September 23, 2025, 04:57:06 pm
content: Hello,I was tired of waiting for a new bitstream to be generated every time I made a firmware change, so I've written a tool to update the BRAM contents of an existing chip configuration. It's called "brup" for Block Ram UPdater. Now it only takes 2 seconds to see the effect of a firmware change.I'm using LFE45-UM Versa board.You need to replace your firmware with a random pattern, this allows the tool to find it in the configuration file. Did you know that Yosys can and will reorder data bits and may even suppress some? Or select surprising layouts (e.g. 16x 1-bit DP16Ks for a 16-bit memory)? That's why brup has to try different RAM layouts and identify the bit permutations for each block.Although I've included a decent testbench, feedback is welcome.It's written in Rust with minimal dependencies, so it should work on Windows and Mac as well.When you run it it looks like this:Code:% brup update \--config $CHIP_CONFIG \--width 32 \--mem $RTL/code_pattern.hex \--new-mem $ASM/code.hex \--output $RTL/tcpu_test_with_code.configLoading current memory contents from "/home/berke/src/verilog/ecp5/code_pattern.hex"Loaded, word size: 32, number of words: 1024Loading desired memory contents from "/home/berke/src/tcpuasm/code.hex"Loading PrjTrellis configuration from "/home/berke/src/verilog/ecp5/tcpu_test_out.config"Number of BRAMs: 18Memory: 1024 x 32BRAM: 4096 x 4Number of sectors: 1Layout mode 4096x4 failed: Identification failed, number of slices not found: 32, conflicts:>Memory: 1024 x 32BRAM: 8192 x 2Number of sectors: 1Layout mode 8192x2 failed: Identification failed, number of slices not found: 32, conflicts:>Memory: 1024 x 32BRAM: 16384 x 1Number of sectors: 1Layout mode 16384x1 failed: Identification failed, number of slices not found: 32, conflicts>Memory: 1024 x 32BRAM: 512 x 36Number of sectors: 2Layout mode 512x36 failed: Identification failed, number of slices not found: 64, conflicts:>Memory: 1024 x 32BRAM: 1024 x 18Number of sectors: 1Identification succeeded with layout 1024x18Assembling BRAM contents into bitmaps...Updating BRAM bitmaps...Reassembling BRAM contents from bitmaps...Saving updated configuration to "/home/berke/src/verilog/ecp5/tcpu_test_with_code.config"Link:https://github.com/berke/brupIf you have cargo, you can just typeCode:cargo install brupto have it installed.

author: booscrawl
author_rank: Contributor
timestamp: September 25, 2025, 06:41:05 am
content: Nice work!

author: berke
author_rank: Frequent Contributor
timestamp: October 02, 2025, 03:43:44 pm
content: Also tested on an ECP5-EVN board with a LFEUM5G-85.Is anyone interested in iCE40 support?EDIT: I've just discovered that icestorm has an icebram tool that does that exact thing for the iCE40, with the same approach (using a random pattern and locating it in the bitfile). I wonder if there is an ECP5 version hiding somewhere?
GAL strange behaviour... - Page 1
Forum section: electronics / general

author: Wawavoun
author_rank: Regular Contributor
timestamp: September 19, 2025, 06:24:45 pm
content: Hi All,I am facing a very strange problem.The question is around a 6 MHz (crystal) 6809 home computer with gal addresses decoding.On a version, say V3, the addresses decoding and some logic glue is made by a 74LS10 and a Lattice 22V10D.In this version I can use a 512 ko x 8 dip 32 ram (70 ns) or a 1024 ko x 8 tsop (45 ns) on a dip32 adapter pcb.I can do that because A19 line of the 1024 ko ram is pulled down by a resistor.All good !Hoping to use all the 1024 ko of ram I create a V4 version.This time the 74LS10 is replaced by a ATF16V8B just doing two 3 inputs nand and one 4 inputs nand (instead of three 3 inputs nand for the 74LS10).In this version the DIP32 512 ko ram is still working well. But there is nothing to do with the 1024 ko one even in 512 ko mode with A19 line just pulled down.There is no sign of life of the computer.Of course when I switch from one memory to another every other things are the same.I assume my equations and the wiring are correct because everything works well with the dip32 memory.All the gals are given for 15 ns MAX propagation time which is very similar to 74LS10 propagation time (10 to 15 ns). All these times are very short relative to the period of the cpu clock (E signal is 1.5 MHz = 333 ns for a half period) and the timing dont look critical.I have check the timing of both rams and have not find any evidence why this can works in one case and not in another one...The 74LS10 replacement by a gal may be can can change some timing (more close) but not reverse signals order due to the combinatorics equations...I have try to slow down the signals coming from the 16V8 gal (using an intermediate free output, I assume this need twice the propagation time) without success...So I am lost.Here joined are the datasheets of both memories I use. If anybody is kindly enough to give a look and give an opinion I will really appreciate.Happy electronics to All !Philippe

author: Wawavoun
author_rank: Regular Contributor
timestamp: September 26, 2025, 12:28:03 pm
content: Solved.
Seeking advice on a Bittware S7t Accelerator Card - Page 1
Forum section: electronics / general

author: lowrykun
author_rank: Newbie
timestamp: September 19, 2025, 04:43:53 pm
content: Hi All,I have a Bittware S7t "VectorPath Accelerator Card (powered by Achronix)". It was purchased by a former company a few years ago and wasn't ever used and has been in storage since. I understand it is an expensive card; I don't have a use for this card, but may decide to keep the server.My question is around how to value and sell the card. I don't see any recent sales on eBay and nothing is listed for that particular model upcoming. I'm trying to estimate its value and understand if there is a better marketplace for specialized hardware other than eBay.Thanks for any advice!

author: ejeffrey
author_rank: Super Contributor
timestamp: September 23, 2025, 05:27:40 pm
content: Bittware's products are basically FPGA reference designs from various vendors for which they provide some level of software support and contract development. For instance, they usually provide a project template with a PCIe instantiation and some host drivers to make it simpler to get data between your custom logic and the host.Without that, it's just an FPGA dev kit in a PCIe form factor. It will be worth something if you can find someone who wants that particular FPGA in a PCIe slot, and if you can get enough documentation to know how to configure it. It would probably be worth more if it were a Xilinx or even an Altera FPGA, since there are at least lot more people who are familiar with those tools chains.

author: lowrykun
author_rank: Newbie
timestamp: September 24, 2025, 10:39:49 pm
content: Thanks. I did reach out to Bittware and they basically blew me off and said I would need to talk to Achronix. I have a relationship there, but I understand they aren't easy to work with. I'm trying to understand if I can transfer ownership to sell or donate to a university. Not much luck so far.
Spartan FPGA CRC check & INIT_B pin - Page 1
Forum section: electronics / general

author: 2X
author_rank: Frequent Contributor
timestamp: September 23, 2025, 07:37:04 pm
content: (CRC)Cyclic Redundancy Check:It is a mechanism where is used to detect errors on the configuration code (bitfile).If an error will be detected the INIT_B goes low.Hello,I have the below query:Is the configuration code checking (CRC) it happens parallel with the loading of the bitfile (checks for instance the sending bytes/packets) and if an error is detected on a “byte/packet” the INIT_B goes immediately Low a or the checking is doneafterthe configuration code loading is completed and then if an error is detected the INTI_B pin goes Low?Excerpts:Spartan-3 Generation Configuration User Guide (page 49):The INIT_B pins perform multiple functions. At the start of configuration, INIT_B goes Low indication that the FPGA is clearing its internal configuration memory—a process called housecleaning. Later, when the FPGA is actively loading its configuration bitstream, INIT_B goes Low if the bitstream fails its CRC check. On Extended Spartan-3A family FPGAs, if so enabled in the FPGA application, the INIT_B pin also potentially signals a post-configuration CRC* error.Spartan-3 Generation Configuration User Guide (page 66):INIT_B: Drives Low after power-on reset (POR) or when PROG_B pulsed Low while the FPGA is clearing its configuration memory. If a CRC error detected during configuration, FPGA again drives INIT_B Low.Spartan-3 Generation Configuration User Guidehttps://docs.amd.com/v/u/en-US/ug332

author: xvr
author_rank: Frequent Contributor
timestamp: September 23, 2025, 08:33:50 pm
content: QuoteAfter.The CRC itself is not self-checking; it must be calculated over the byte stream and ultimately compared to the expected value. This "expected" CRC is placed at the end of the bitstream, so a CRC error is impossible until the entire stream is read and a "reference" CRC is obtained for comparison.
Need documentation for used bittware XUP-VV4 board - Page 1
Forum section: electronics / general

author: leedh
author_rank: Newbie
timestamp: September 23, 2025, 02:30:33 am
content: So, I just pay the price for my blind actions. Here's what happened:I bought a used Bittware XUP-VV4 board from eBay. The seller listed it as 'card only,' but I was hoping I could find the constraint files or any publicly available documentation, like with other FPGA boards. When I contacted Bittware to get the supporting files, they told me that only the original buyer has access...Has anyone got some advice? or provide Constraints file, clock frequencies, whatever.Thanks,Leedh
desighing in vitis HLS block for writing samples into DDR - Page 1
Forum section: electronics / general

author: john23
author_rank: Frequent Contributor
timestamp: September 18, 2025, 02:47:06 am
content: Hello , In the attached TCL file and PDF file described block diagram in RFSOCK 4x2.I want to create an IP block in VITIS HLS so I could import it into vivado, which writes samples into DDR so I could see the value of a 1.5GHz tone on the output.Is there some example codes or guidelines in need to use for this purpose?Thanks.
New cheap PCIe FPGA board XCKU3P-FFVB676 - Page 1
Forum section: electronics / general

author: dmendesf
author_rank: Frequent Contributor
timestamp: September 10, 2025, 02:20:42 pm
content: Found this board at the usual site:https://www.ebay.com/itm/167626831054It´s a XCKU3P-FFVB676 (Kintex ku3p ultra scale+) that´s supported by free Vivado tools. Seller says it has "Vivado board file pin constraints Import Vivado to use Clock, sfp, pcie.led". I have asked for it but seller hasn´t answered yet (if someone has it or any other info about this board please share it here). Seems like a good deal for me. What do you think?Bad things about it: lack of extensive GPIO, external memoryGood things about it: (supposed) Known good PCIE and SFP28 interface, support by free tools

author: dmendesf
author_rank: Frequent Contributor
timestamp: September 13, 2025, 05:32:35 pm
content: Got the support files from the seller.
FTDI Communication Problem with Pylibftdi on a Windows Machine - Page 1
Forum section: electronics / general

author: aunal
author_rank: Newbie
timestamp: September 11, 2025, 02:22:20 pm
content: Hello Everyone,I have a Digilent Nexys Video Artix-7 FPGA development board. This board has two Micro USB ports. One is used for UART-USB communication, and the other one for uploading bitstreams(as a JTAG). I programmed the FPGA such that I can acquire high-speed data via FTDI using the JTAG Micro USB port(I communicate with pylibftdi). I programmed the UART-USB port for the configuration(I communicate with pyserial). These ports can be found in the attached screenshot of the board as 9 and 10.When I use Linux based OS, I can use both ports without any problem. But when I try to run my Python program on a Windows machine, it doesn't allow me to use one port as a COM port(which is used for serial communication by serial lib in Python). Somehow the driver of the USB-UART conflicts Pylibftdi library such that whenever I connect USB-UART port to my Windows machine, Pylibftdi library starts to give error which I attached as a screenshot again. I also added the screenshot of the device when USB-UART port was removed.I think I tried every possible driver that might be found on the internet. Do you have any recommendations about this issue?Best regards,ArdaU
Advanced Educational Resources - Page 1
Forum section: electronics / general

author: Foxxz
author_rank: Regular Contributor
timestamp: October 13, 2025, 03:45:33 pm
content: I could use some suggestions for where to find more advanced FPGA educational resources. I would like to learn more about how to use Vivado to create designs using the PCIe bus and partial reconfiguration and related topics. I am willing to pay for classes, tutoring or working with a professional, etc.

author: laugensalm
author_rank: Regular Contributor
timestamp: October 18, 2025 12:46:18 pm
content: You might check with PLC2 (plc2.com) in Germany, they would have the know how and probably english speaking people on board.

author: asmi
author_rank: Super Contributor
timestamp: October 18, 2025 02:57:50 pm
content: AMD has a ton of courses, both paid and free:https://learningcatalog-amd.netexam.com/
Vivado Simulator: Can you compile only changed files and re-run? - Page 1
Forum section: electronics / general

author: betocool
author_rank: Regular Contributor
timestamp: August 20, 2025, 01:34:00 am
content: Hey all,I'm following up a bit on my other thread about a test server, but I decided to ask this on a different topic.Not too long ago in another company I used Modelsim (the Quartus Edition) to simulate my VHDL code. Once I got into the groove of Modelsim I remember just recompiling the files that had changed and re-starting a simulation. In very odd cases I had to restart the whole thing. It was pretty quick.I'm using Xilinx now and their simulator. It does the job, can't complain, but everytime I restart a simulation after minimal changes on a file, the simulator recompiles EVERYTHING, IP blocks, other .vhd files, the lot.I tried looking into the tcl or command line to see if there is a way to just recompile one file within the project or library and re-start the simulation but had no luck so far.Is it at all possible? I'm happy to run the simulations via command line if that helps. If anyone has managed to do that, I'd appreciate some links or examples.Cheers,Alberto
Primus tool for Efinix - Page 1
Forum section: electronics / general

author: mon2
author_rank: Frequent Contributor
timestamp: March 16, 2025, 02:47:53 am
content: Hi. Came across this website that appears to be out of Shenzhen (using Google translate):https://www.elitestek.com/product/kaifahuanjingPrimus/They are listing a new toolchain by Efinix named Primus. Anyone have experience with this tool? So far, unable to download this tool as my phone is not in China so the account setup is failing. One beef we have had is with the rather long time to synthesize even small projects as compared to Gowin toolchain which is very fast. Perhaps Primus is faster to sythensize to a bitstream?Perhaps Primus will be available on the USA website soon.

author: Zengfh
author_rank: Newbie
timestamp: August 14, 2025, 02:28:57 pm
content: I registered him in the evening, but was reminded that I did not have permission to download. I will consult again during working hours tomorrow to see if I can download it. I am also interested in this new version of the software and their 16nm FPGA ti60f225. Perhaps it can process IO signals more quickly.
Updating base overlay with IP block of basic input - Page 1
Forum section: electronics / general

author: john23
author_rank: Frequent Contributor
timestamp: August 09, 2025, 09:38:57 am
content: Hello ,I want to input a signal to the radio IP (part of the basic overlay)PDF attached.So I could use as DAC.Vin2_01 is the port I want to put the signal inside as shown below.Two questions:1.looking at the RFDC block shown below , what is the variable type that its looking for when inputing the Vin2_01?2.Is there IP I can use to input digital data to Vin2_01?I tried to use the constant block as shown below to input the Vin2_01 but they dont mactch.How do I make them match?Thanks.
How to have a reset signal for a Sipeed/Tang verilog design? - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: December 29, 2024, 04:31:39 am
content: I would like to program Sipeed Tang 4K in verilog and am not sure where to get the system reset signal that resets the entire design. Does the FPGA or the board provide such signal? If not, can I implement it myself?The board documentation and schematic are here:https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-4K/Nano-4K.htmlOn an Latice ice40 board I implemented a reset generator, based on the fact that all registers start at zero state. Can I assume the same about the Gowin FPGA?https://github.com/FPGAwars/apio-examples/blob/master/examples/alhambra-ii/bcd-counter/reset_gen.v

author: vagran
author_rank: Newbie
timestamp: December 29, 2024, 03:28:03 pm
content: I did not check for Tang, but many FPGAs synthesize `initial` block where you can explicitly assign initial values to registers.

author: zapta
author_rank: Super Contributor
timestamp: January 06, 2025, 05:42:53 am
content: I ended up implementing this.https://github.com/FPGAwars/apio-examples/blob/11826b8addc47cce8d84ab612eab4077feef5e73/examples/sipeed-tang-nano-9k/blinky/blinky.v#L9

author: sigint
author_rank: Contributor
timestamp: March 23, 2025, 11:09:03 am
content: There should be a pin called "RECONFIG_N". Pull this down to reload the FPGA configuration.P.S.: Dang! ... that signal is missing on most packages. Why?!

author: pcprogrammer
author_rank: Super Contributor
timestamp: March 23, 2025, 12:07:48 pm
content: There is a bit in the bitstream that has to do with power on reset. In the project configuration you can specify the usage of it, but it is not fully clear to me what it actually does, or how it can be used in the code.It is being used by the synthesis and routing software though. Within the primitives files there is a global reset object.You can always assign an IO pin to be a reset input and use that in your design to reset things. Another option is to make use of the PLL lock signals, but only useful if you are using a PLL to make your clock signals of course.I recently did a design on the Tang Nano 20K and it sets up the registers in the way that you initialize them in your design. When you declare a register and assign a value to it on startup, it will be set to this value after loading the configuration.

author: zapta
author_rank: Super Contributor
timestamp: March 23, 2025, 03:19:34 pm
content: From the documentation, it seems to be some form of brownout detection and automatic reset.

author: Zengfh
author_rank: Newbie
timestamp: August 14, 2025, 02:17:27 pm
content: Hi, I am using the GW1NSR-LV4CQN48P chip without introducing an external RESET signal. I used the PLL's LOCK signal as the global reset, which is feasible after testing.
Xilinx XC2C128 Coolrunner CPLD replacement - what's best? - Page 1
Forum section: electronics / general

author: Mark
author_rank: Frequent Contributor
timestamp: June 30, 2025, 01:25:23 pm
content: I need to replace a XC2C128-7VQG100I. I'm looking at a small Efinix Trion T4 FPGA as a replacement, but I was wondering if there might be an easier option. The Trion T4 is BGA, I would prefer QFP.

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: July 01, 2025, 12:51:44 pm
content: Microchip ProASIC3 A3P030-VQG100 ?https://www.microchip.com/en-us/product/a3p030

author: mopplayer
author_rank: Contributor
timestamp: October 02, 2025, 12:09:56 pm
content: Quote from: Mark on June 30, 2025, 01:25:23 pmIf you don't live in China, you shall not consider the Chinese companies like PANGO, ANLOGIC, elitestek (Efinix, outside of China) and GOWIN, their hardwares also have potential issues and defects...If the small ball-package is also fine, I recommend Lattice LCMXO3LF-1300E-5UWG36ITR, and there is also a TQFP package, LCMXO3LF-1300E-5TG100C. Their prices aren't expensive than the Chinese chips...
GAL programming WINCUPL vs PALASM  - Page 1
Forum section: electronics / general

author: Wawavoun
author_rank: Regular Contributor
timestamp: July 24, 2025, 10:08:33 am
content: Hi All,For my new 6809 cpu board I have to program a 22V10 gal.I have Atmel ones and also old Lattice's.I am more confident with Lattice gal because in some previous designs Lattice gal are working where Atmel gal dont. And I never really find why...Using Lattice gal mean use Palasm4 for compiling equations. This soft works ok in Dosbox.My question is :In WINCUPL it is possible to use intermediate variables (not affected to any pin). This is handy in case of use of the term into several output equations.Is it possible to do the same in PALASM4 and how ? I have tried different things but as soon as a term isn't affected to a pin PALASM indicate an error...Thanks for your attention.Philippe

author: PCB.Wiz
author_rank: Super Contributor
timestamp: July 24, 2025, 07:48:49 pm
content: Quote22V10 should be std fuse map, allowing you to use CUPL on lattice.Did you compare JED files ?IIRC CUPL has a fuse command that lets you set setup/config fuses if not supported by a command.Does lattice have any features not in atmel ?

author: Wawavoun
author_rank: Regular Contributor
timestamp: July 30, 2025, 06:46:33 pm
content: You are right.I compare the fuse maps produced by both softwares for a simple example and they are identical.I got a success by programming a Lattice 22V10D with a JED file coming from WinCupl and the TL866II Plus.I think the subject is close !Thanks.Philippe
New AI Tool to Accelerate Design and Development - Page 1
Forum section: electronics / general

author: virenvelacheri
author_rank: Newbie
timestamp: July 28, 2025, 06:03:01 pm
content: Hey all! Would you be open to trying a new AI tool designed to accelerate hardware design and development?I'm a developer working on a tool aimed at doing just that and am looking for early users to give feedback.For those interested in a quick 20-minute user interview (with a $20 thank-you gift) to share your thoughts and help shape the product, book a time that works for you here thanks!https://cal.com/viren-velacheri/20min. Also can always message me directly any questions/concerns you may have

author: tggzzz
author_rank: Super Contributor
timestamp: July 28, 2025, 06:37:41 pm
content: Start by telling us how we can tell when the LLM is hallucinating.Then tell us how we can tell that the LLM has understood our requirements sufficiently well that it's output is useful.Actually don't start there. Start by telling us what tool canand cannotdo.

author: ataradov
author_rank: Super Contributor
timestamp: July 28, 2025, 08:01:58 pm
content: Yeah, how exactly does it accelerate things and what specifically it accelerates?

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 28, 2025, 09:33:29 pm
content: But even if it was very good at translating requirements into implementation, what makes you think that it would help?I know I've been saying that over and over again, but that's unfortunately just a thing: silver-bullet people assume that the hard part is implementation, while the hard part is actually formulating useful, clear and unambiguous requirements.

author: tggzzz
author_rank: Super Contributor
timestamp: July 28, 2025, 10:28:05 pm
content: Quote from: SiliconWizard on July 28, 2025, 09:33:29 pmThere speaks someone with experienceUsually formulating the tests (unit, integration, acceptance) is at least as difficult as formulating the gate interconnectionsIn general, it is relatively easy to answer a question correctly. It is more difficult and more important to ask the right question.

author: EEVblog
author_rank: Unknown
timestamp: July 28, 2025, 11:47:08 pm
content: Quote from: virenvelacheri on July 28, 2025, 06:03:01 pmDon't spam your link in more than one thread.

author: Simon
author_rank: Unknown
timestamp: July 29, 2025, 06:09:31 am
content: I've cleaned their mess out of the other thread.
Altera Cyclone IV Firmware analysis / decompiler? - Page 1
Forum section: electronics / general

author: gamerpaddy
author_rank: Regular Contributor
timestamp: July 26, 2025, 06:33:05 pm
content: HelloDoes anyone know how to analyze or decompile a firmware / bitstream for Altera Cyclone IV?in particular a EP4CE4OU1917 with a W25Q128FV flash hooked up to it.Im trying to figure out since days now how a particular firmware works, find a hidden password for factory menu and try to get a list of commands that can be sent via UART.it may contains NiOS-II RTOS of some sorts. if that helps (at offset 0x10A133) 6 dumped binaries from individual devices attached as a zipi also listed all offset from the flash i could findCode:0x000000-altera cyclone iv stuff / bitstream?0x200000-camera settings0x280000-weird pattern with second byte allways 1x?0x4C0000-looks like a image, weird pattern?? 36010 bytes0x580000-same as above? 36010 bytes0x740000-GUIX header?0x7C0000-Strings for GUI?0x800000-another shorter GUIX0x880000-Strings for second GUI?0x8C0000-another GUIX0x940000-More Strings for GUI0xE00000-? no data in dumps but it reads from eeprom0xE80000-dzxg? pretty short0xEC0000-just a crosshair.bmp0xF40000-3DTM header?0xF80000-Bad pixel mapThe EEPROM gets read from turn-on to idle like so: (may have missed smaller reads)A nios-ii plugin for Ghidra didnt work, Hexrays IDA is clueless.i also tried splitting the binary into its chunks to feed them individually, nothing.BinaryNinja allways produces pseudocode... but it does that for everything you feed it .. not helpful.What im looking for?Commands that are allways 3 uppercase Letters like "SCO" followed by a comma to give it a parameter or end it.a password consisting of 6 digits. the digits are not numbers or letters. they are 6 different hardware buttons. one known password is +-+-+-

author: radiolistener
author_rank: Super Contributor
timestamp: July 27, 2025, 02:42:04 am
content: uC/OS-II is a nice and tiny RTOS kernel, certified for critical applications. I was used it in the past.It is easy to port to any platform, and it has a lot of ports for different MCU.
DDR setting for my rfsoc4x2 proccesor - Page 1
Forum section: electronics / general

author: john23
author_rank: Frequent Contributor
timestamp: July 06, 2025, 07:35:13 am
content: Hello , I started to build a block diagram for my xczu48dr-ffvg1517-2-e component in vivado the proccesor called zynq ulatascale+MPSoC.When I try to do the basic automation, It gives me and error ash shown below.In other manuals that use zynq-700 xc7z020clg484-1 there is no such problem when I press automation.I want to use it in simple GPIO manner.What is the difference with this proccesor?Do you have any manual regarding how to configure this kind of proccesor?Thanks.[PSU-3] Setting of DDR Row Address Count (Parameter PSU__DDRC__ROW_ADDR_COUNT) to 17 is not valid when the value of Device Capacity (Parameter PSU__DDRC__DEVICE_CAPACITY) is set to 8192. The valid value for Row Address Count (Parameter PSU__DDRC__ROW_ADDR_COUNT) is 16.

author: Psi
author_rank: Super Contributor
timestamp: July 06, 2025, 07:56:49 am
content: Quote from: john23 on July 06, 2025, 07:35:13 amI don't know anything about xczu48dr-ffvg1517-2-e or using DDR chips, but seems like 17 is too many address rows for the configured ram size.If it was 16 it would be 8192.eg.2^16 = 65,536 / 8 bits = 8192Are you saying that you are setting PSU__DDRC__ROW_ADDR_COUNT to 16, but get the error about it being 17 ?Are you sure you are not mixing up a count vs an index somewhere. eg 0-16 = count of 17 possible numbers.Or maybe PSU__DDRC__ROW_ADDR_COUNT is being set in multiple places.

author: john23
author_rank: Frequent Contributor
timestamp: July 18, 2025, 05:01:48 pm
content: Hello PSI, I just put this block into vivado and tried to press automation so I'll get started using it.It needs to generate some output pins
Unknown EP4CE6E Cyclone IV board on Ali  - Page 1
Forum section: electronics / general

author: bingo600
author_rank: Super Contributor
timestamp: July 25, 2025, 07:22:58 am
content: Just bought a Cyclone IV board on Ali.https://www.aliexpress.com/item/1005009306876743.html?Board doc here ... Thanx to a kind Chinese EEVblog userhttps://www.eevblog.com/forum/chat/heep-to-access-some-fpga-documentation-on-beidu/I can't seem to find any schematic, and seller only had the info in the EEV url above.I have gathered a bit of component info below.Code:******************************FPGA = EP4CE6E22C8NFPGA Flash = EPCS4NB444X - 3v3WinBond Flash = 25Q64JVSiQ - 3v3WCH USB-Serial = CH340C - 5vOSC1 = 50MHzOSC2 = 27MHz*** Remember to connect Jtag-Pin4 to 2v5JTAG Vtgt (Pin4) = Seems to 2v5.Someone mentions 3v3 though .... What is correct ?******************************I'm still a HDL beginnerAnd mostly played with CPLD's.But have a working Quartus 13.0-sp1 setup on a Linux Mint 17 VM ... The last version that supports the old epm3xxx/7xx CPLD'sIt seems to work for the CycloneIV too.After connecting Jtag (Pin4) Vtgt on the board to 2.5v, i can program the EPCS4 flash chip with the (already in LED demo oroject) :output_file.jigI have 1 question ( for now) :1:Since i have no schematic:What is usually the "normal" Jtag Vtgt voltage ?Is Jtag pin voltages following some "bank" voltage ?Doc (pict) mentions 2.5v, but other schematic's use 3.3vEdit:Well I tried wo those offsets , and i could generae a pof & jic file , that would program ok.I'm using Vtgt = 2.5vTIA/Bingo

author: bingo600
author_rank: Super Contributor
timestamp: July 25, 2025, 08:27:35 am
content: Another question :In the programmer, the flash device :I have blankcheck and erase.I'm a bit confused about those selections.If i tick blankcheck , do i still need to do an "erase step before programming" ?Is the erase step for a "special situation" ie. flash locked or do i need to do that brfore every "programming" ?/Bingo

author: xvr
author_rank: Frequent Contributor
timestamp: July 28, 2025, 01:06:37 pm
content: QuoteIt must follow voltage of JTAG interface pins of FPGA. Moreover, it must be directly connected to this voltage source of FPGA board. JTAG adapter use this pin as reference voltage, to adjust IO levels of its own JTAG IO pins.QuoteYou can use 'blank check', and if it success you can skip 'erase' step. FLASH should be in blank state before programming, It could be initial state (when it comes from fabric), or state obtained after 'erase' cycle.
iCE40 Ultra Plus hard ip sb_i2c problem  - Page 1
Forum section: electronics / general

author: r3v
author_rank: Newbie
timestamp: January 14, 2023, 02:53:47 pm
content: Hi,I'm trying to use the hard ip i2c with a fpga lattice iCE40 ultra plus. I have the breakout board.when I symthetise the project I have this : I1202: Reading Architecture of device iCE40UP5KWarning-1411: No clock is reaching the reference clock pin 'SBCLKI' of instance 'i2c_control.SB_I2C_INST_RT'. So, no gen clock will be inferred at output of this instance.the clock signal is the clock system.I'm using iCECube2.I'm looking for a project example.thanks

author: mon2
author_rank: Frequent Contributor
timestamp: January 15, 2023, 03:02:11 pm
content: See if this helps:https://www.eevblog.com/forum/fpga/ice40up-pll-with-external-clock-howto/

author: iMo
author_rank: Super Contributor
timestamp: January 15, 2023, 05:03:50 pm
content: Have you tried with Radiant?Quote from: r3v on January 14, 2023, 02:53:47 pm

author: hp23
author_rank: Contributor
timestamp: July 15, 2025, 07:30:31 am
content: I know I'm resurecting a thread that's old. But was a solution found here? I have exactly the same symptoms.Pete
X-SP6-X9 Spartan 6 demo bord, need documentation files - Page 1
Forum section: electronics / general

author: MetalHead
author_rank: Contributor
timestamp: July 04, 2025, 12:21:59 pm
content: Hello!Can someone share documentation to this board.X-SP6-X9 image below. Thanks!

author: vstrakh
author_rank: Contributor
timestamp: July 05, 2025, 06:17:18 am
content: But all the pinout is specified on the silkscreen, you shouldn't really require any schematic.

author: MetalHead
author_rank: Contributor
timestamp: July 05, 2025, 10:27:21 am
content: I know that but anyway, there is a lot of other useful information in supporting documentation Like code examples, schematics etc

author: cfbsoftware
author_rank: Regular Contributor
timestamp: July 05, 2025, 10:49:51 pm
content: Try asking the vendor:https://artofcircuits.com/product/spartan-6-fpga-development-board-xc6slx9-tqg144

author: MetalHead
author_rank: Contributor
timestamp: July 13, 2025, 08:53:49 am
content: No reply from Pakistan)
Issues with LCD and PS/2 Keyboard in Xilinx Spartan 3AN - Page 1
Forum section: electronics / general

author: eusouopedro
author_rank: Newbie
timestamp: July 12, 2025, 05:51:07 pm
content: HelloWe are trying to make a calculator using the PS/2 Keyboard and LCD display in Spartan 3AN FPGA Board. We have made a code to print in the LCD the key that was last released on the keyboard.Our problem is: the LCD seems kinda delayed. For example:We press "J" -> LCD shows nothing, thenWe press "K" -> LCD shows nothing, thenWe press "L" -> LCD shows "J".And so on. If we press the same key 3 times, it will show that key.I don't know if I could made the problem clear, but if anyone has any clue or tip on how to solve it, I would aprecciate it.GitHub Repository:https://github.com/eusouopedro/FPGACalculator

author: rstofer
author_rank: Super Contributor
timestamp: August 02, 2025, 03:46:12 am
content: Opencores has a PS/2 keyboard interface that is known to work. Maybe you can get some ideas. I used it 20 years ago with a Spartan 3 FPGA 'Starter Board'. I'm pretty sure it was this code...https://opencores.org/projects/ps2_keyboard_interfaceCount every clock and see where the code is hanging in some state longer than necessary.
Lattice Diamond Timing Closure (Constraints) files. - Page 1
Forum section: electronics / general

author: atom1477
author_rank: Newbie
timestamp: July 11, 2025, 10:53:04 am
content: Hello.I have trouble understanding how to create files for Timing Closure.Of course, I read the user guide:https://www.latticesemi.com/view_document?document_id=45588But I still have some questions:1. In page 16 we have:Select where?2. In page 14:Does this mean that I have to create 3 constraint files?For example, if I have a CLK = 200 MHz, do I need to specify constraints for it in 3 separate files?And, additionally for first file (SDC), do I need separate "mirror" LDC file when I use LSE alternately to Synplify?Thanks in advance!