Trying to understand some old school logic... - Page 1
Forum section: electronics / projects

author: alank2
author_rank: Super Contributor
timestamp: July 18, 2017, 12:36:27 am
content: I'm trying to figure out the way the BUS signals work on an old retro computer I am going to clone this project from. The schematic is from a fellow in Japan who designed it, but they don't have any more boards/pcbs so I am going to make my own. It is a 3-in-1 cartridge that plugs into the PC-6001A computer and it provides 16K extended RAM (originally DRAM but this project uses SRAM), 16K of ROM (switchable banks to have different "cartridges" loaded), and finally an 8255 interface to an AVR that emulates floppy drives. One thing he did not have in his design was a way to decide which image files to mount from the SDCARD into which drives. I plan on expanding to an atmega325 with more I/O pins so I can drive a tiny 4 digit 7 segment display and have a few buttons for input. With that I can select which drive to view/change and then use the +/- buttons to change the mounted image (obviously numeric only, but that will be fine for me).Here are the control signals - am I understanding these correctly:The parenthesis name is the signal name from computer documentation, not the schematic. Some of them are not listed properly in the documentation (NC!)1 nRAS2 (RAS) (active low)10 nEXCAS (MPX) (active low)both go through an OR gate to the SRAM CS (active low), both must be active low to activate the SRAMwhy 2 of these? are they a remnant from some sort of refreshing for DRAM? Does it make sense they should both be low to enable the SRAM IC?3 nDRD2 (DBIN) (active low)SRAM OE (active low)5 nWE (WE) (active low)Connected to SRAM WE (active low)---2 nCS3 (ROM2 OE) (active low)4 nCS2 (ROM1 OE) (active low)either activate the flash via two nand gates to flash CEnCS2 also connected to A13, so nCS2 means first 8K IC and nCS3 means the second 8K. This makes sense as cartridges for this computer had a pair of 8K IC's in a rom.14 nRD (NC!) (active low) (***FLASH or 8255)it feeds to the 8255 via an OR gate which can't go low unless the other gate input goes low as wellit feeds the flash OE directly (active low)13 nWR (NC!) (active low)it feeds to the 8255 via an OR gate which can't go low unless the other gate input goes low as well11 nIORQ (NC!) (active low)connects to the decoder nG2A (active low)The decoder is setup so it will only output active low to the 8255 OR gate when D7-D4 are 0xD for ports 0xD0-0xDF15 nRESET1 (NC!) (active low)When it goes low, it pulls the AVR reset to ground which is normally pulled high with 10K.When it goes low, it goes through an inverter which drives the 8255 reset high which clears it.His schematic does not have this, but if I wanted to disable the 8255 and the floppy drive emulation can I modify the CS pin circuit. Right now it is grounded (always enabled). Can I pull it high with a 1K resistor and then use a DIP switch to switch it to ground? DIP on=grounded=enabled, DIP off=5V=disabled.Any thoughts on the wierd signal names?

author: rstofer
author_rank: Super Contributor
timestamp: July 18, 2017, 03:19:47 pm
content: nEXCAS and nRAS are the column and row access strobes for DRAM.http://hardwarehell.com/articles/ras_cas.htmI doubt they will be meaningful for SRAM as you have some form or nRd and nWr. I would look at those versus some data line to make sure they go low after the data is stable and go high before the data transitions. In other words, they are well behaved.

author: C
author_rank: Super Contributor
timestamp: July 18, 2017, 06:55:54 pm
content: The dynamic ram memory back then could have been the TMS4116http://www.rogtronics.net/files/datasheets/mem_dram/TMS4116.pdfA Z80 with 64k ram would have had 4 rows of 8 chips.RAS, CAS or both would be used to select which row handled the request.To switch address lines to ram chip a third signal was needed. This signal went to a set of chips like the 74157.To reduce the number of chips needed in a cartridge, the common chips needed for most cartridge(s) would be moved to main part of computer.A good design would have a transceiver chip on the data lines. A cartridge read would require a direction change of transceiver chip to Z80. The remaining time it could be from Z80.The leading lower case "n" means that signal is active low.I would think that all the signals that do not match a Z80 pin name to be special for cartridge use. There could also be some with Z80 pin names that are modified also.What you can do is limited by what exists on main board.

author: alank2
author_rank: Super Contributor
timestamp: July 19, 2017, 12:28:10 pm
content: Quote from: C on July 18, 2017, 06:55:54 pmI noticed this too - I expected the card slot would have a bus with all the main bus signals, but that isn't how they designed it.Someone emailed me a link to the schematic!

author: NivagSwerdna
author_rank: Super Contributor
timestamp: July 19, 2017, 12:47:47 pm
content: A very classic design. The 4116 DRAM has +/- 12V. (The DRAM refresh being a killer Z80 feature)Even has AY-3-8910 for sound.The 32K SRAM would have been expensive back in the day.I guess this was a predecessor to the MSX.

author: alank2
author_rank: Super Contributor
timestamp: July 19, 2017, 03:24:17 pm
content: On the 0304 schematic (power board) there are two connections off to the right CN606 and CN607. CN607 goes to a micro switch to detect whether a cartridge is plugged in or not. There is a switch in the slot with a roller wheel that is activated when you put a cartridge in. It looks to me like the roller wheel does something to perhaps increase the output of the +12 and +5 (it is marked -5 for some reason on the sch, but actual power board pcb shows +5). Looking at the way CN606 and CN607 are wired, either can short the signal to ground. If you look at 0307 in the upper left, you see the power area and it shows CN12 going to pins 44 and 46 which on 0303 are labeled OFF-SW (GND) and OFF-SW (HOT) on the cartridge pinout. The ROM cartridge I have shorts pins 44/46. Would you assume this is accomplishing the same thing as the the roller micro switch then? If I make an add in board, can I just short these two pins and forget about the microswitch leaving it open? Does that make sense?

author: alank2
author_rank: Super Contributor
timestamp: July 21, 2017, 12:19:04 pm
content: In the schematic above, R6 and R7 are 1K pullups. Any thoughts on why they are so strong? The logic driving the signal/overriding the pullup is 74LS series.

author: alank2
author_rank: Super Contributor
timestamp: July 27, 2017, 12:47:21 pm
content: Quote from: rstofer on July 18, 2017, 03:19:47 pmHere is the question though - why are CAS and RAS relevant for enabling the SRAM? The way this is wired up, both CAS and RAS go through an OR gate so for that to output low, both CAS and RAS must be low. That is fed into the nCS of the SRAM. It looks like you can't read from or write to the SRAM unless CAS/RAS are both low. Both CAS and RAS have a line above them, so they would be active low. So, normally they would be high when inactive, right? I guess if it were the other way around, CAS/RAS are normally low and sometimes go high when we would want to disable the SRAM for that strobing to occur... What am I not getting about this?

author: NivagSwerdna
author_rank: Super Contributor
timestamp: July 27, 2017, 01:46:55 pm
content: To avoid DRAM operations. RAS and CAS return to inactive after read, write or refresh cycle.

author: alank2
author_rank: Super Contributor
timestamp: July 27, 2017, 01:50:01 pm
content: Quote from: NivagSwerdna on July 27, 2017, 01:46:55 pmDoes that mean that it is normal for DRAM for RAS and CAS to be enabled before a read or write cycle?

author: NivagSwerdna
author_rank: Super Contributor
timestamp: July 27, 2017, 02:05:39 pm
content: https://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf"1. The row address must be applied... 2. RAS must go from high to low....""Before the ..... cycle can be considered complete, CAS and RAS must return to their inactive states"Also...http://www.rogtronics.net/files/datasheets/mem_dram/TMS4116.pdfyou can see CAS and RAS going inactive as the cycle ends.

author: alank2
author_rank: Super Contributor
timestamp: July 27, 2017, 02:42:58 pm
content: Thank you - that document covers it all right!

author: alank2
author_rank: Super Contributor
timestamp: July 28, 2017, 02:12:07 am
content: Up in the sch in post #1, R6 and R7 seem to be pretty strong pullups that take over when the dip switch is opened. Do you think they are meant to assist the logic output, make it stronger, etc. ? I think the original schematic uses 74LS series IC's. I'd like to change them to 10K if it would still work.Also, I noticed the 74LS series isn't available in a ton of packages, singles or doubles instead of quads. Are there other 74 series that I could look at that would also work well with this type of logic?

author: alank2
author_rank: Super Contributor
timestamp: July 28, 2017, 09:05:26 pm
content: Does anyone know what VR301 does in the video schematic above (_0304) ??