Long SPI bus lines - should I use series resistors? - Page 1
Forum section: electronics / projects

author: HwAoRrDk
author_rank: Super Contributor
timestamp: April 17, 2018, 04:27:21 pm
content: I have been working on a project to augment the capabilities of a device that uses an SPI controlled character-based LCD, by intercepting the SPI communications to the LCD and using my own microcontroller to display other information. I will be using a 74HC365 hex buffer to split the bus on demand (i.e. turn on or off of my additional display info), with my MCU then acting as both a slave to the original mainboard of the device, and as a new master to the LCD.One thing has made me pause for thought. In its original configuration, the LCD is attached to the mainboard by a rather long cable harness - by the time it winds its way around the chassis, the length totals approximately 2ft/60cm! I believe it is because of this, to mitigate EMI/RFI problems, that the SPI bus is run at a pretty slow clock speed, 10kHz, and the mainboard has 2.2K series resistors on all bus lines. However, by inserting the '365 buffer into the bus, I lose that mitigation for the secondary side, and it will still have a fairly long length (at least 1ft/30cm) to the LCD; will it be wise to replicate the series resistors there?To add to this, when the bus is split, I would like to talk to the LCD at a much higher speed, preferably the maximum of 1MHz it supports, because I will be adding another SPI device on the bus that it would be too slow to talk to at 10kHz. Should lower series resistance values be used in that case (e.g. < 1K)? Also, should I place the resistors before or after the branch off to the tertiary SPI device?Any other suggestions or hints for good practice with a long SPI lines most appreciated.

author: IDEngineer
author_rank: Super Contributor
timestamp: April 17, 2018, 04:36:37 pm
content: I would start by looking at the existing SPI signals with a scope. Then start making your changes, see what effect they have on the signals, and adjust things as necessary to obtain reasonable signals (in-spec rise/fall times, critically damped, etc.).

author: iMo
author_rank: Super Contributor
timestamp: April 17, 2018, 05:34:04 pm
content: The insertion of serial resistors into SPI with long wires shall minimize the ringing (caused by the inductance of the long wire).2k2 may work with 10kHz, with 1MHz you need a smaller value - the higher the resistor value the slower are the signal edges (caused by RC, where C is the capacitance of the long wire).Use something like 50-220ohm with ~xMHz SPI frequencies.

author: IDEngineer
author_rank: Super Contributor
timestamp: April 17, 2018, 05:44:18 pm
content: Quote from: imo on April 17, 2018, 05:34:04 pm...where "something" is a not a value you guess at, but a value you determine by examination with a scope. As I suggested above.

author: iMo
author_rank: Super Contributor
timestamp: April 17, 2018, 05:57:24 pm
content: Sure, for example do measure the rising edge for different Rserial values and stay with an Rserial where the rising time is no more than 10% of the H pulse width..QuoteThe best place for the Rserial is at the active line driver's output.

author: Siwastaja
author_rank: Super Contributor
timestamp: April 17, 2018, 06:11:23 pm
content: 2k2 series resistance sounds totally insane.Yes, the idea of series termination is:1) to reduce peak current, which naturally causes electromagnetic interference by the very definition of current2) to slow down the voltage change over time dV/dt, which causes interference by capacitive coupling. (You can think this on a frequency domain: sharp edge ("nice" digital waveform) generates infinite series of frequencies, even if you just "switch" at 10kHz or whatever, but if you extend the rise/fall times to, say, 5-10% of the total period, you have wiped out far-away frequencies but your circuit still works.)3) to damp any parasitic ringing; you can think about it either as an LC circuit with wire inductance and capacitance, or as a transmission line where reflections occur, but in either case, you want to get rid of the reflected energy so that it doesn't bounce back, and back, and back, and...In any case, sizing the resistor so that it's equal or bigger than the transmission lines characteristic impedance, is enough to do the damping.Going much over 100R does not provide any benefit IMHO. After that, you'll only make any noise, crosstalk, etc. easier to couple to the line which is now fairly high-impedance.So, my answer is, yes, definitely use series termination resistors in all driven standard CMOS outputs (MOSI, SCK, CS) to dampen ringing when you have significant cable lengths, especially if the grounding is iffy (for example, only one shared ground wire in a connector, not adjacent to MOSI and SCK) so the current takes a longer loop, with higher inductance).But size this resistor sanely. Often, around 22R to 47R is enough to get rid of ringing. 100R may be justified. Even 100R shouldn't be a problem in a 60cm wire unless you are aiming for multi-megahertz communication. At 1MHz, there shouldn't be an issue, unless you go for insanely high resistances.For example, right now, I'm running standard single ended 8-bit parallel CMOS at 40MHz in a 50cm FFC cable, every other wire as ground. Source series termination is 33R and we are not having any reliability issues, and the scope trace looks as expected.

author: nctnico
author_rank: Super Contributor
timestamp: April 17, 2018, 06:24:53 pm
content: 2k2 is not a bad idea if it is used together with filter capacitors. The biggest problem isn't radiated emissions but susceptibility. SPI is one of the worst busses to transport over wires because one false pulse which goes over the logic threshold will mess up the clock signal or cause a false select. I2C for example has some inherent features to make it resillient against external pulses.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 17, 2018, 06:36:24 pm
content: Yeah.If you're overly concerned with emissions and susceptibility in your application, and the wiring length is significant, you could use LVDS transceivers and shielded twisted pairs. Probably (very) overkill for a local display, but that would work well.

author: Siwastaja
author_rank: Super Contributor
timestamp: April 17, 2018, 07:34:36 pm
content: If filter capacitance is to be used, which is indeed great in some cases where noise cannot be dealt with otherwise, I'd still go with lower R (than 2.2k) and higher C for the same RC cutoff, foreven moreincreased immunity against external pulses by having bigger C. (Of course, C cannot become excessively big without having its package size and parasitic inductance increased, making very high-frequency filtration worse again, so indeed, you can see bigger (than your typical 10R-47R series termination) resistors in these cases.)Just to give an example, a combination of 470R and 1nF would result in an RC time constant of 0.47 us. Assigning 10% of time to transitions, this would ballpark to a usable frequency of around 100kHz. 1nF capacitor would require quite some significant noise energy to be injected to change its terminal voltage to give false input reading. Now, with 2k2, the capacitor would only be 220pF. Still a huge improvement over just the pin parasitics, but given the higher level of noise coupling due to higher output impedance of the driving side, the capacitor has more to do. Hence, I'd choose 470R+1nF over 2k2+220pF.By the way, the noise susceptibility figure (delta V required to cause a glitch) of the digital input stage isnotthe '0' to '1' or '1' to '0' threshold value; it's either the input hysteresis value, or the said logic threshold value, whichever is smaller; usually the hysteresis is smaller. Because noise can also couple during switching!The input stage hysteresis is highly critical, because the transition is the critical moment where noise coupling can happen as well, and in fact, in synchronous digital logic, several signals tend to be switching nearly at the same time, possibly causing coupling exactly at this worst moment when the signal is exactly in the halfway of the logic low and high thresholds. If the input stage has way too little hysteresis, no amount of filter capacitance is going to fix the noise issues, because the capacitor can never filter perfectly due to its ESL, and especially PCB layout inductance - the extra filtration is then only making the susceptible transition area longer, and increasing the odds of the disturbance happening at that moment.With very careful layout design, the filter capacitor can be placed within 1mm of the input pin, right to the ground plane, properly stiched and connected to the nearest ground pin of the input IC, and if it's a nice 0402 part, this is as good as it gets. However, nothing beats a nice schmitt trigger input in this kind of single-ended design, so that a noise disturbance of, say, even 1V, simply doesn't matter, even while transitioning.BTW, I have yet to see a bus that is magically unsusceptible to "single pulses" strong enough to cause wrong logic interpretation. Single pulse strong enough will corrupt SPI, I2C, LVDS, RS422, or CAN, and in each case, requires design on how to manage data consistency checks and resends (some busses such as CAN offer this automatically or semi-automatically, but the designer still needs to understand how and why it happens, and monitor how often it occurs).Sure, SPI is probably about two orders of magnitude more susceptible to noise than, say, RS422 or LVDS, but that doesn't mean that a properly designed system would have such noise sources. In fact, seeing SPI corruption inside your equipment is a signal that there is something really, really wrong with that design and it needs to be fixed very first. For communicating with the "outside world" or long cables (what is long? It depends, 60cm is not impossible), things are of course different; there, while using SPI is not a total non-option, it requires careful understanding of the consequences and mitigation strategies.Many I2C devices I have worked with tend to totally lock down and kill the whole bus, necessitating bus resets, sometimes unpowering the devices with added PFETs on their Vcc which seems to be alarmingly common mitigation technique (also, modifications of I2C such as PMBUS exist to address the commonly known reliability problems). OTOH, I have never had such issues with SPI, since the most typical implementation selects one device at a time with a robust select signal, which tends to reset any communication state logic within that device, so that even after one faulty transmission, we are back again and can get fresh data out of a sensor - or send a new refresh to the screen. Of course, with both typical SPI and I2C devices, you never tend to have checksums or any other means for 100% protected communication (IC manufacturers simply don't seem to design in such features), so you are on your own if you need to think about data checking & resending. If you are having noise issues, quite frankly, you need to look at where these issues originate, and only resort to extra filtration when you are doing something quite non-standard (such as running long cables outside the box). These busses are simply meant to be designed in so that the designer guarantees that electrical data distrubations simply do not happen, or are so rare that they are consider acceptable failures (such as an unimportant consumer device freezing once a year, requiring a reboot; but usage in a life support system, for example, wouldn't be allowed for most SPI/I2C parts).

author: IDEngineer
author_rank: Super Contributor
timestamp: April 17, 2018, 08:33:01 pm
content: Excellent review, should be read by everyone in this forum. Thanks for taking the time!

author: HwAoRrDk
author_rank: Super Contributor
timestamp: April 17, 2018, 08:38:10 pm
content: Thank you all for the suggestions and information, particularly Siwastaja for the in-depth review.I haven't actually constructed anything yet; I'm just at the design stage. All I have done so far to look at the existing signals on the bus is to put a logic analyser on it and inspect the content of the communications. Of course, that will not tell me anything about the nature of the signals, so I will have to put a scope on each line (cheap scope, no many-channel action for me) and see how they look with the original standard configuration.I think I will put 100R series resistors into my design for the moment, located after the point where the '365's and my MCU's SPI lines join. Attached is the current rough schematic of how I have my design for the SPI bus splitting section at the moment.When I get around to constructing a prototype, I will then be sure to look at the signal when operating the split master side at 1MHz and see if I need to change the values. Perhaps add some capacitors, a few hundred pF maybe. I could even always put both on my final design just in case and not populate the caps if unnecessary.One thing that I hope may help keep a cleaner signal than otherwise is that within the original 12-wire harness going to the LCD, three of them are ground wires (all commoned).

author: Siwastaja
author_rank: Super Contributor
timestamp: April 18, 2018, 07:09:55 am
content: For even better performance, you could use separate 100R resistors for both MCU and the buffer, so that the resistors can be closer to the source. This would have an added benefit that if you ever accidentally enable both MCU outputs and the buffer at the same time, 200R would then completely protect both outputs from excessive short circuit currents. (This might be a non-issue, since it's fairly easy to write the software to guarantee they are not on simultaneously, except some super rare freak incidences.)Probably not a big thing, and the BOM / PCB estate reduction may be worth only using one set of resistors, especially if the buffer and MCU are within only a few cm of each other.

author: HwAoRrDk
author_rank: Super Contributor
timestamp: April 18, 2018, 12:31:04 pm
content: Good point, I hadn't thought of that. I will have to see if I can fit that into my final layout.If only they made 5 or 6 element SMD resistor arrays, it would be easy.I will be making every effort in my code to not allow the master SPI outputs and the buffer to be enabled at the same time, but like you say, the unexpected can happen, so probably best to try and mitigate that.

author: r0d3z1
author_rank: Regular Contributor
timestamp: February 03, 2020, 01:31:52 pm
content: Quote from: Siwastaja on April 17, 2018, 07:34:36 pmthanks, good explanation. I would like to ask you further details about the RC filter, there are various way to place the filter:source -> RC -> cable -> receiver (slow edge on cable, low emission, low coupling, not very effective for EMI immunity)source -> cable -> RC -> receiver (effective for EMI immunity, doesn't solve coupling between signal)source -> R-> cable -> C -> receiver (quite sharp edge on cable, quite effective for EMI immunity, maybe a good compromise)source -> R/2 -> cable ->R/2 C -> receiver (quite sharp edge on cable, veryy effective for EMI immunity, maybe a good compromise)source -> R/2 C-> cable ->R/2 C -> receiver (the best ?)source -> RC -> cable -> CR -> receiver (seen herehttps://electronics.stackexchange.com/questions/35091/alternatives-to-spi-because-of-emi)I would probably select the 4th solution, however the solution 6 proposed herehttps://electronics.stackexchange.com/questions/35091/alternatives-to-spi-because-of-emifrom user3624 seems to be interesting but I can't understand the meaning of "What I would do is to put an RC filter on the PCB at both ends of the cable. The RC filter would have the C on the cable side and the R on the chip side."

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 03, 2020, 01:50:29 pm
content: FYI, it's generally better to put resistance towards the cable. Capacitance towards cable encourages resonance, increasing peak voltages (at far end) and currents (at C end) at resonant frequencies. If those peaks happen to line up with harmonics from the signals within, you can get increased emissions; likewise if an ambient noise source happens to transmit at those frequencies, you can get increased susceptibility.Whereas, keeping resistance towards the cable encourages damping or termination, including for common mode noise.Ferrite beads are an excellent source of RF resistance, without adding much DC resistance. Good idea for output pins when you don't know if the load is hi-Z or not. (Plain R is fine when you know the load is hi-Z, like CMOS logic inputs.)The ideal filter network is, say: series R, parallel C, parallel ESD diode, series R. Change R for FB when low-Z is priority. (The series R between ESD diode and chip limits peak surge current into the chip, whereas if they're wired together in parallel, surge currents will be shared.)Can also use C || (R+C) to dampen a capacitor without adding series resistance, given a few other limitations.All of these options do quickly multiply the parts count, though, so you may find it's more economical to compromise with a simplified combination. This shows which kinds of things you can expect to be compromised as a result, so choose accordingly.Also don't ignore filtering ICs -- USBUF01W6 and family for example, a handy shortcut for these sorts of things. For the OP's application, a lower cutoff frequency than this would be desirable, so shop around.Tim

author: Renate
author_rank: Super Contributor
timestamp: February 03, 2020, 02:45:02 pm
content: On a more basic level:This is a closed source piece of equipment that is putting out 10kbps SPI to a character LCD?Presumably the character LCD is a stock parallel one with an SPI "backpack"?If you are displaying additional info, why wouldn't you use a bigger/different/OLED display?Why not take the 10kbps SPI in and spit out parallel directly to the LCD.For OLED, you'd be using a separate SPI bus.What is this "additional high speed data source"?Why wouldn't this use a separate SPI into your micro?SPI is really the least shareable bus thing around.

author: profdc9
author_rank: Frequent Contributor
timestamp: February 03, 2020, 03:17:29 pm
content: Probably overkill, but I have used ribbon cables alternative every other line as a ground line. The impedance of this transmission line is about 100 ohms or so. It also helps to shield noise. Source termination is not a bad idea either if you use a controlled impedance line. I have used SPI ribbon cable buses up to 2 meters long and 8 MHz clocking frequency.

author: MagicSmoker
author_rank: Super Contributor
timestamp: February 03, 2020, 03:25:17 pm
content: If the SPI bus is multi-drop then I prefer to use split termination at the very end: 220R for each resistor usually works well enough for both traces and ribbon cable conductors. I also use the "assign every other wire as ground" trick with ribbon cables like profdc9 mentioned to good effect in extremely high noise environments like motor drives, plasma power supplies and other unfriendly environments.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 03, 2020, 05:33:13 pm
content: Back in the day, you'd use a TTL bus driver IC at the source end, and an asymmetrical terminator at the far end, 390R pullup and 150R pulldown I believe was very popular. Spot in the middle of TTL input threshold, a nice match. Ye Olde ST-412 interface used such a system for the control signals (the high speed data being RS-422).Can do the same today, give or take terminator voltage offset and receiver threshold voltage, with for example 74HC7014 hex precision schmitt buffer. Very handy device, if a bit obscure. I mean, all the old bus drivers and receivers are still around, too, if you like.Tim