+12V to -12V 1A NCP3163 Inverting DC-DC Converter Design/PCB Review - Page 1
Forum section: electronics / projects

author: tinfever
author_rank: Regular Contributor
timestamp: January 12, 2022, 02:53:47 am
content: Hi everyone,I'm working on a project that requires a -12V power supply so I decided to build a standalone version of the DC-DC converter for testing first. I *think* this design should work but I'd appreciate any feedback.Target Specs:+12V input (11-13V)-12V output1A output50mV max output voltage ripple50mV max output voltage transient overshoot/undershoot with 0.8A load stepI selected the Onsemi NCP3163 for the regulator IC.A few things I've been pondering:I designed a custom footprint that will accept the NCP3163 in either DFN18 or SOIC packages since the DFN is cheaper but looks at risk of going out-of-stock. Do you see any reason why this wouldn't work? The datasheet mentioned the SOIC package has an exposed pad so there is a risk that might short the DFN pads if the measurements aren't perfect. The datasheet also shows the exposed pad isn't perfectly rectangular so I reduced some of the DFN pad lengths to try to clear the protrusions. I presume doing this combo footprint will negatively impact EMI due to longer traces but I'm thinking it would probably still be acceptable?Is there any room for improvement on inductor, capacitor, and diode placement? I went around and around but eventually settled on this design. I'm not thrilled with the output Al-poly cap placement but couldn't find a better placement without making the whole board substantially bigger. I'm trying to make it as small as possible as a challenge.Do you have any concerns about the planes partially running under some components like the capacitors? I tried to minimize it but without doing that I was worried about the width of the power planes/tracks.Note: the one axial resistor is because I thought I might have to try a different value and I only have a selection of axial resistors on hand.Edit: The pin numbering on the IC is based on the DFN18 pinout so it looks weird when translated to the SOIC footprint.Edit2: Fixed P/N typo in titleThanks!

author: strawberry
author_rank: Super Contributor
timestamp: January 12, 2022, 03:38:15 am
content: soldermask on IC pads onlysolder will flow and make mess otherwise

author: moffy
author_rank: Super Contributor
timestamp: January 12, 2022, 04:04:09 am
content: 1. Your title should be NCP3163 not NCP3136 as it is confusing even if only a typo. Worse is that an NCP3136 exists as I found out.2. Pins 6,7,8,9(Switch Collector) need to be joined together on the PCB, using DFN18 package.3. Pins 10,11,12,13(Switch Emitter) need to be joined together on the PCB, using DFN18 package.Those are just the most obvious issues I can see.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 12, 2022, 04:19:17 am
content: Consider using local GND plane under the regulator. This greatly shrinks the switching loop. As shown, the loop returns through two capacitors on opposite sides of the regulator -- and the board! Which also puts a lot of voltage drop across the plane and thus between connectors (common mode noise). The latter can also be avoided by placing the connectors together (or as an extreme case, using a 3-terminal connector so there's literally no common mode between input and output).Tim

author: tinfever
author_rank: Regular Contributor
timestamp: January 12, 2022, 07:59:04 am
content: Thanks for all the feedback!Quote from: strawberry on January 12, 2022, 03:38:15 amI never would have caught that! I'll modify the footprint so that the solder mask is only removed where either the SOIC or DFN package pads would contact the IC.Quote from: moffy on January 12, 2022, 04:04:09 amOops... I fixed the title. Thank you.As weird as it looks with my combo footprint, I think the pins are correct. Pin 1 on the DFN18 is in the upper left corner of where the IC would be, for reference. What would be pins 6,7,8,9 are tied together and labeled as pin 6 VIN. What would be pins 10,11,12,13 are tied together and labeled as pin 10 SW NODE. I really should have used the SOIC pin numbering to make life easier for everyone, myself included.Quote from: T3sl4co1l on January 12, 2022, 04:19:17 amI'm not quite sure I understand. The exposed pad on the bottom of the IC is connected to the "GND" pin on the IC, but in the inverting configuration that is actually tied to the -12V output.I've attached a photo of the current loops (yellow lines) as I think I understand them. I don't think much current at all actually flows through the "GND" pin on the IC at all, right?I need to do more reading on common mode and differential noise since I don't really have a good grasp of them. My intuition is that when the switch is on, nearly all of the current would flow in the +12V input > IC > Inductor > Ground Plane > Input Ground Terminal. Then when the IC is off, the inductor induces the negative voltage to keep current flowing so it goes "in" (because negative voltages are weird) the -12V output > Diode > Inductor > Ground Plane > Output Ground Terminal, and I think it would have to go out specifically the Output Ground Terminal to create a working circuit. It feels like almost no current would flow between the two ground terminals. Although... maybe I should add an optional footprint where I can slice the ground plane and install a current shunt to test it. That could be interesting.Am I missing something here?I hadn't even considered a three terminal connector before though. I can definitely see how that could make the whole thing much tighter.

author: moffy
author_rank: Super Contributor
timestamp: January 12, 2022, 08:45:50 am
content: QuoteYour schematic should match your PCB, that is how you generate your netlist and look for unconnected pins etc. You should show all the pins used on the schematic i.e. 6,7,8,9 tied together and that should match the PCB, otherwise sometime down the line you are going to confuse yourself or someone else when time has passed. Notice that in the data sheet they show in their schematic the common pins tied together.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 12, 2022, 03:51:04 pm
content: The critical point is commutation, when the switch is turning on or off. Current is abruptly diverted from the left side to the right, or vice versa. This puts a large dI/dt through the loop shown:The solution is putting the bypass cap(s), current sense and diode very close together.Note that wiring length corresponds to loop inductance, on the order of 1nH/mm. Paths through wide planes are lower (which is why having plane is so nice -- the impedance is low), hard to estimate, but also not zero as we would like to be able to assume.The inductor doesn't need to be close by. The key insight here is, current is varying slowly through it -- indeed, a triangle waveform, and any stray wiring inductance merely acts in series with it. Whereas stray inductance in the above loop, amplifies switching noise.Yes -- local ground, as the regulator sees it, is -12V in the circuit. This could be extended on the bottom layer, and stitched to circuit GND with some bypass caps around the edge of it. This gets -12V closer to, and around, the regulator (use vias in the middle, both to heatsink the thermal pad and better ground it), and gets to the bypass caps right out in front. Change the input side caps to go between +/-12V.Note that the above loop has some width, and the connectors are horizontally opposed, so will create some voltage drop between grounds. This might be only some ~mV, but it's more than nothing, and good practice is to avoid such loops, especially by connectors. If the connectors were moved to the same edge of the board, there will be a much smaller segment of loop between them, and can also be at a greater distance to the loop. Both factors reduce switching noise coupled between them.Finally, with outputs off to one side, arbitrary amounts of filtering can be applied, if needed for a very low noise system (<<1mV). The filter caps will be local to each other, again minimizing differences between the two connectors.Tim

author: tinfever
author_rank: Regular Contributor
timestamp: January 14, 2022, 02:08:15 am
content: Quote from: T3sl4co1l on January 12, 2022, 03:51:04 pmThank you.I've been giving this lots of thought and I think I'm starting to understand. Both C_in and C_out will be charging at nearly the same time but because C_out is at -12V, current would be flowing in to the C_out GND terminal and out of the C_in GND terminal, thus creating kind of a loop. Since the current is changing direction through the caps very quickly, that creates the problematic di/dt area.Falstad circuit I put together to try to visualize it:The problem I'm running in to is that if I don't want the inductor stuck between the input and output caps, then the -12V_out net gets boxed in between +12V_in and GND, so I'd have to use the bottom layer to get -12V_out to the output terminal. I've done exactly this in the attached layout. However, I'm not thrilled about having what is almost a split ground between the two layers, even though the bottom GND layer would only be used for the small auxiliary circuits.I also looked at the example layout from the datasheet and theirs didn't seem much better than my first layout.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 14, 2022, 04:32:43 am
content: Yes, that layout looks excellent.Go figure, appnotes and eval boards are hit and miss. Sometimes they're written by top engineers, sometimes you wonder if their intern was even paid at all...On the upside, it's not a huge difference, functionally speaking. The chip only drives an ampere or so. It's not terrifyingly fast, and so that 1A switching in, whatever, 50ns say, and an inductive loop of say 20nH, will see a peak voltage of (or probably less than) V = L dI/dt = (20nH) (1A) / (50ns) = 0.4V. Out of a 40V or so rating, who cares, right? You probably don't want too much of that impressed between the connectors however; a fraction of a volt will show up on the scope as a pervasive spike or ring almost everywhere in the circuit; or for regulatory purposes, it needs to be some ~mV to not interfere with radios. (Of course, whether that reaches the outside world from deep within some other system -- presumably this module would just be a small component of something bigger -- is another matter; worst case would be something like, the module strung up on long wires hanging in free space.)The switching loop looks like this, shown with 1st order parasitics:Transistor and diode are shown as switches Q and D, and note they have junction capacitance, which is in series with stray inductance around the loop. Depending on which one is on/off, you get a resonant circuit between loop inductance and one or the other junction capacitance. So if you see ringing, it's at the frequency corresponding to these elements.Tim

author: tinfever
author_rank: Regular Contributor
timestamp: January 23, 2022, 08:56:37 pm
content: Quote from: T3sl4co1l on January 14, 2022, 04:32:43 amThank you very much for your help and feedback.I finished the board and sent it to Oshpark a few days ago. Once it comes back I'll get to try my hand at assembling it and see how it works!Thinking about it some more, I think having the "split" ground with all the power paths on the top layer and all the small aux. circuits using the bottom layer might actually be ideal. Although I wish I didn't have to route the feedback line all the way around the perimeter of the board, but the only alternatives were to route it under the inductor (bad) or only take feedback from the -12V polygon on the bottom instead of directly off the output terminal.Quote from: moffy on January 12, 2022, 08:45:50 amThank you. I took your advise and reworked my schematic to include all the pins on the actual IC and also fixed the pin numbering so it matches the SOIC pinout from the datasheet, since that's what they use primarily throughout the datasheet and those are just the more visibly obvious pins on my custom footprint.