Should plane be used to connect power or just thicker tracks? - Page 1
Forum section: electronics / general

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: August 22, 2023, 07:55:51 pm
content: I understand that one can use PCB tracks to connect power to ICs. The tracks will need to be thicker to reduce the temperature rise due to current on the path.Lets look at the problem from perspective of real world PCBs that contain FPGAs, DDR RAMs, DSPs, Microcontrollers, OpAmps, ADCs, DACs. These are boards that will need a complex stack up and contain many voltage rails in digital and analogue domain.What is the correct way to connect the power rails? Just use PCB tracks like we do with signals or use copper pours or power planes? This is really confusing me.

author: ataradov
author_rank: Super Contributor
timestamp: August 22, 2023, 08:14:33 pm
content: There is only one real answer - use power planes on dedicated power/ground layers.Exact layer allocation would vary depending on how many layers you plan in total and how many and how distributed your voltage rails are.

author: bpiphany
author_rank: Regular Contributor
timestamp: August 22, 2023, 08:38:41 pm
content: Do You Really Need Power Planes? Are you sure? | Eric Bogatinhttps://youtu.be/kdCJxdR7L_I

author: Infraviolet
author_rank: Super Contributor
timestamp: August 22, 2023, 08:42:52 pm
content: Really depends how much current is needed and how demanding the speed and analogue accuracy needs within a design are, but often for currents of <100mA doing things which aren't articularly fast and don't need great analogue accuracy then even using power traces as small as 0.2mm signal traces will work fine (so long as decoupling caps are presentand very close). This will often happen when doing single or two layer design. Most of the components you list are usually not all that current hungry, so track thickness for resistance matters less here than ensuring the other types of impedance are kept under control by avoiding long snaking many-via'd paths without appropriate decoupling.

author: ataradov
author_rank: Super Contributor
timestamp: August 22, 2023, 09:00:24 pm
content: With "FPGAs, DDR RAMs, DSPs, Microcontrollers," you are basically forced to do 4 or 6 layer design.If you are going with 4 layer design, then S/G/P/S is pretty much the only layer configuration that would work for a complex design. Artificial test boards with 3 components in the middle would reveal that this design may not be ideal, but there are piratical limitations in real designs you have to keep in mind. And a lot of those issues are addresses or minimized by adding ground pours everywhere where there are no signals and adding via stitching.I don't see a scenario where individual power traces are better than just a plane. It sound like a lot of work for no real gain. And you don't have to have entire layer be a power plane, of course. It is fine to have copper fills under the components that take those power supplies.

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: August 22, 2023, 09:51:55 pm
content: If we use power planes, we still need to use vias to connect them to the power pins. Doesn't that kind of defeat the purpose of planes? I mean first we have this vast copper pour (in an inner layer) with low impedance for the current path, and then when it comes to connecting the power, the current needs to pass through vias. haha. Looks funny to me.

author: ataradov
author_rank: Super Contributor
timestamp: August 22, 2023, 10:17:00 pm
content: You will have vias no matter what, unless you somehow manage to route power supplies on the outer layers. But that usually prevents proper routing of the signals, so you would have to use a lot more vias for that. And that is far worse.This is why you ideally should have bypass capacitors close to the pin on the same side as the device. In that case via inductance does not matter as much.The planes are useful because they eliminate spaghetti of power signals and make it far easier to do the layout.Not sure what is so funny about that. This is a standard way of laying out a board, lots of designs do that without any issues.

author: Bud
author_rank: Super Contributor
timestamp: August 22, 2023, 10:24:13 pm
content: Ìt may look funny to you until you realize power planes have distributed capacitance, which is a free fiter capacitance. Connections to chips may be done through vias but power delivered to the via point will be cleaner because of the plane bulk capacitance.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 22, 2023, 10:56:53 pm
content: Quote from: ataradov on August 22, 2023, 08:14:33 pmI mean, any absolute answer, one can almost certainly assume is wrong...It would be better to phrase as: for high speed digital, power on planes is almost certainly the right answer; potentially even multiple planes acting in parallel (when a particularly low-Z supply is needed). More likely, enough supplies will be needed (core, LV IO, 3V IO, AVDDs...) that several planes will be required in total (and more if paralleled planes are then required). Designs using even modest size BGAs, tend to be extremely limited in how much IO can be escaped and routed on 4 layers, and even 6 may be sketchy. Top-of-the-line high density designs may need dozens of layers.In contrast, analog domains needn't use planes, as power supplies are usually low current and low dynamics. I would mainly use a plane to simplify connections (drop a via vs. having to route and bypass everywhere). You can save on some bypasses as well, with a plane. When low noise is required, use planes carefully, as you don't want to pull noise in from other areas -- a VCCA routed in from a noisy digital domain, or noisy supply* for that matter, could be disastrous. It's a compromise between plane area (reduces Z, easier to lay out) and, well, connecting everything together, noise and all.(*Many years ago, I heard report that one then-National sync buck reg exhibited something suspiciously like drift step recovery, due to a slight dead time between low-side turn-off and high-side turn-on. The affected board had 100s-of-Msps ADCs on it, which showed occasional noise peaks which were eventually tracked to the reg's "impossible" risetime. Needless to say, noise figure was ruined until this was accommodated. I forget if it was replaced, or just synchronized.)An RF circuit might also prefer GND all layers, to minimize crosstalk between areas; power might be routed as feed-thru connections between locally shielded sections. (Feed-thrus being "faked" with SMTs around the boundaries is close enough.)Planes don't have to span the whole board, and since we're talking mixed signal circuits here, probablyshouldn't. Use supplies local to each domain. What counts as a "domain" depends on voltage requirement, if it needs to be switched, how much noise can be coupled around and can be tolerated, etc.An average embedded project might have say 12 or 24V or whatever in the input / power section, a 5V domain for peripherals and interface, a 3.3V domain for MCU or VCCIO, and maybe some others as applicable (say if you have some high speed stuff or VCORE or whatever). An average design with QFP/QFN as the most dense devices, is most likely fine on 4 layers, and you should only need 6 or 8 if it's particularly high density (for which, blind, buried or HDI vias may be necessary to achieve high density, and at that point, BGAs aren't a problem either!).Tim

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: August 22, 2023, 11:03:20 pm
content: By funny I did not mean wrong. What I meant is that, we first want to have low inductance path from VRM to the IC power pin. But after having this wide pour, we suddenly use vias to connect to the power pins.Now, if we just look at this topic, once I have a power plane, should I still create a small-tiny region of pour on the top/bottom layer (and connect power plane via into it) before connecting to the IC power pin or just use a track between the via and the IC power pin?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 22, 2023, 11:22:15 pm
content: The GND plane is not just for power distribution, it also provides for the return path of signal currents with the smallest loop area. Above about 10kHz the loop inductance is the dominating factor over DC resistance. So a full GND plane improves signal integrity and EMC performance ( both send and receive of noise).It's even common to have multiple GND planes on a multi layer PCB, because prepreg is much thinner then the PCB core (unless you have many layers) and this provides for tighter coupling and better performance.

author: ataradov
author_rank: Super Contributor
timestamp: August 22, 2023, 11:29:26 pm
content: Quote from: matrixofdynamism on August 22, 2023, 11:03:20 pmIf your design allows to do this without compromising routing of the data signals - yes. This is the best case scenario. You would still want to place decoupling capacitors as close to the pins as possible.But you will likely find that with complex designs, it is not that easy to have a solid plane for the power on the outer layers.And this plane is also not even an option for BGA devices.Also, when looking at the vias and their impact on inductance, you should also consider the bonding wire and the pin of the package. And when you look at something like TQFP-144 package, the via would end up being the least significant part of that.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 23, 2023, 01:46:55 am
content: I would say more vias, matters more than having same-side pours. You can for example put vias on either end of a pad (if not otherwise restricted). But that can be a useful way to route power over a modest distance, if for some reason you can't put vias directly adjacent; the wide pour is effectively a low-Z transmission line, and the wider it is (assuming the pads can connect into it as quickly; long thin traces or necks between pads and the bulk of the plane add a penalty), the closer to ideal it is. Which includes tying it with multiple vias where it can finally get tied in.On less critical devices (most low end MCUs, common logic, etc.), bypass doesn't even need to be nearby; a wide plane is a nearly ideal connection between points. Make the connection points better (i.e. using multiple vias) and the bypasses can be pretty much anywhere.Per-device let alone per-pin bypassing is really only a concern for 2-layer designs, or generally where power is routed on traces; or on faster or more critical devices. (For example, notice the via grid under a BGA compromises plane integrity: they're turned into hollow meshes instead. This allows more signal bounce -- with respect to VCC or GND, or between both just as well, which also means a stronger benefit for local bypasses underneath the device.)Tim