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Forum section: electronics / projects

author: cleaningOut
author_rank: Contributor
timestamp: January 15, 2018, 06:49:44 am
content: ...

author: daveshah
author_rank: Unknown
timestamp: January 15, 2018, 09:22:47 am
content: Looks good to me, I can't see any of the common mistakes (VccPLL is correct unlike the official breakout board.)What clock frequency do you plan to run the CSI interface at?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 15, 2018, 09:59:59 am
content: Quote from: cleaningOut on January 15, 2018, 09:41:34 amYes, that will be the 400kHz, CSI will be running at hundreds of MHz. You may need an FPGA with some SerDes support to do anything serious unless you can slow it down a bit.

author: iMo
author_rank: Super Contributor
timestamp: January 15, 2018, 11:56:14 am
content: On the first glance:The 3 decoupling caps are usually selected in 1:100 ratio to make more sense, like 1n||100n||10u.The schottky diode there will not make 2.5V probably, better use a standard one instead.Also I would add a 100n decoupling at the cathode of the diode.Missing pin 30 (VCC).I would add a ferrite bead into the VCC rail..PS: is there any practical experience with UP5k and larger and faster designs?? It seems to me the UP5k is not the best performer, even it is 40nm stuff..

author: daveshah
author_rank: Unknown
timestamp: January 15, 2018, 12:05:53 pm
content: Bayer encoded 8-bit 320x240x60fps is only ~36MHz before overhead, so 18MHz per lane. Maybe say 25Mbps per lane with blanking, overhead, etc, which means a fabric clock of only 12.5MHz because CSI-2 is a DDR interface. The only problem is the Pi's CSI-2 receiver probably won't lock that low, so you might actually need to bump things up to ~100Mbps/50MHz which should still be doable.

author: xaxaxa
author_rank: Regular Contributor
timestamp: January 15, 2018, 02:27:09 pm
content: You could also consider the xc6slx9 fpga in a tqfp package; it has 9K logic elements, serdes supporting up to 900Mb/s, and a faster fabric than the ice40. Many of my signal processing cores can meet timing at 300MHz on it. It is about $5 on aliexpress.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 15, 2018, 03:44:15 pm
content: I don't like the schottky diode for generating the 2.5V supply either.To begin with, its Vfd (thus voltage drop) will usually be much less than 0.8V, and it will also depend on the current that's drawn (and also temperature, but that may be less of an issue).I'd replace it with a standard ldo unless you're *really* tight on overall cost.

author: Scrts
author_rank: Frequent Contributor
timestamp: January 15, 2018, 04:50:17 pm
content: Quote from: SiliconWizard on January 15, 2018, 03:44:15 pmI agree on this as well.

author: asmi
author_rank: Super Contributor
timestamp: January 16, 2018, 01:58:41 am
content: I used TLV7111225 dual-LDO for my UP4K breakout - I like that it's so tiny, it provides clean power lines, and since FPGA consumes so little power, it's more than enough.Also I'd replace 100 Ohm resistor in Vcore rail and put in ferrite bead instead. LDOs are inefficient enough, so no need to increase losses by adding another resistor.Lastly I didn't see any SPI flash IC on board - are you going to burn firmware into the FPGA itself (it's OTP memory)?

author: asmi
author_rank: Super Contributor
timestamp: January 16, 2018, 02:16:28 am
content: Quote from: cleaningOut on January 16, 2018, 02:03:45 amI see - I'm just used to "big" FPGAs where using resistor filters is a recipe for disasterQuote from: cleaningOut on January 16, 2018, 02:03:45 amYou might want to hold FPGA in reset than until the host is ready to configure it, because otherwise FPGA will attempt to read the bitstream using SPI bus, which might interfere with host operation - FPGA will start providing clock signal and commands onto the bus, and in general SPI masters don't like when there are additional masters on the same bus.Quote from: cleaningOut on January 16, 2018, 02:03:45 amI like that it's so tiny and kinda fits into the whole Lattice "theme" of making super-compact designs. It requires only three external caps to work if my memory serves me, and it provides separate "enabled" inputs in case you want to implement power sequencing (I didn't implement it on my board because 3V3 rail powered this LDOs and FPGA IO buffers, and datasheet requires Vcore to be present when Vccio inputs are powered up).Here it's U2 on the right side:

author: humbug11
author_rank: Newbie
timestamp: January 16, 2018, 05:46:10 am
content: Did you verify the power supply sequencing and ramp times? I looked into the iCE40 and finding cheap LDOs that could power it as specified in the datasheet seemed difficult. But I'm not sure how critical that is..Sent from my A0001 using Tapatalk

author: asmi
author_rank: Super Contributor
timestamp: January 17, 2018, 01:19:27 am
content: Quote from: cleaningOut on January 16, 2018, 06:27:45 amActually I've never had any power-up issues with my Artix-based boards (and I don't bother power sequencing it aside from setting up slew rates to Xilinx specs - I "borrowed" this circuitry from Digilent's Arty-Z7 board with few changes), but iCE40 Ultra board did have a problem of not booting up properly on power up. As it turned out, the problem was that SPI flash chip I was using was too slow to initialize upon power up, such that FPGA started sending commands to it before it was ready to accept and execute them. I solved the problem by introducing a capacitor in the reset net that delayed FPGA startup enough for flash to become ready.