Should my design use Stripline in USB differential pair impedance calculation? - Page 1
Forum section: electronics / projects

author: sfcircuit
author_rank: Newbie
timestamp: January 28, 2018, 07:37:52 am
content: Hi,I am designing a PCB that involves USB 2.0 differential pair trace. It is a 4-layer board with the following configuration:Top layer: Analog and low-speed digital signalLayer 2: 3.0V Power PlaneLayer 1: USB2.0 Differential pair traceBottom layer: Ground PlaneAccording to this:http://www.bitweenie.com/listings/microstrip-vs-stripline/A stripline is in between 2 Ground planes, however in my design, the USB2.0 differential pair is in between a Power plane and a Ground plane instead.I am planning to use "Saturn PCB Design - PCB Toolkit" to do differential pair impedance calculation. However, I am not sure which type of differential layer should I use:1. Edge Cpld Ext (Microstrip)2. Edge Cpld Int Sym (Edge-Coupled Symmetrical Stripline)3. Edge Cpld Int Asym (Edge-Coupled Asymmetrical Stripline)4. Edge Cpld Embed5. Broad Cpld Shld6. Broad Cpld NShldCan my design still be considered as a Stripline for impedance calculation? Or should I select another one.Thank you.Cheers.

author: ataradov
author_rank: Super Contributor
timestamp: January 28, 2018, 07:41:34 am
content: How long are your USB traces? If they are under 2-3", then just route them as your normal traces. USB 2.0 is not that picky. Just look at any product or a development kit - people jump between layers, route around stuff, and it all works in the end.

author: sfcircuit
author_rank: Newbie
timestamp: January 28, 2018, 10:51:54 am
content: Quote from: ataradov on January 28, 2018, 07:41:34 amThanks for your advice Alex. Yes, they are just around 1.5", separated by a USB 2.0 switch in between. Unfortunately, my project (a PCB to connect between a smartphone and laptop, a current measuring meter) had signal integrity problem, at a very specific situation, which it failed when a USB 3.0 phone is trying to connected to a USB 2.0 laptop port, it works fine for USB3.0 laptop port and USB 2.0 phones. I tried to troubleshoot, and I suspect it might be due to length mismatch of the differential pair. Also, before I dive into the next design, I am trying to rule out all possibilities including the impedance mismatch.Hence, I hope to find out whether how should I calculate the impedance for this design (due to design constraint, the USB 2.0 trace has to be between a power plane and a ground plane).

author: Leo Bodnar
author_rank: Frequent Contributor
timestamp: January 28, 2018, 10:59:58 am
content: If you are trying to tightly-couple them consider the fact they are not true differential signals.Each packet ends with two bit long SE0 state where both lines go low (SE0 = single-ended zero) so mind the return path(s)In general - don't overthink it unless you are worried about radiated EMI.Leo

author: ataradov
author_rank: Super Contributor
timestamp: January 28, 2018, 07:07:31 pm
content: Quote from: sfcircuit on January 28, 2018, 10:51:54 amWhat is USB switch? Are you sure it is working correctly? Can you bypass it for a test?Quote from: sfcircuit on January 28, 2018, 10:51:54 amUSB 3.0 devices start talking in USB 2.0 mode until they fully understand that host is USB 3.0. I don't think it is a signal integrity issue, it must be something else, especially given that true USB 2.0 devices work fine.I really don't know how to do actual calculations, but if you won't find anything useful, then just make traces a bit wider (20-30 mil). It looks like that's what typically happens when you try to do proper matching anyway.

author: sfcircuit
author_rank: Newbie
timestamp: January 29, 2018, 01:05:41 am
content: Quote from: Leo Bodnar on January 28, 2018, 10:59:58 amAlright, thanks Leo. It seems like USB 2.0 is pretty straight forward.

author: sfcircuit
author_rank: Newbie
timestamp: January 29, 2018, 01:13:49 am
content: Quote from: ataradov on January 28, 2018, 07:07:31 pmThe switch I am referring to is a basically a multiplexer:http://www.mouser.com/ds/2/149/FSUSB30-1010253.pdfAnd yes, I am able to bypass it. Regarding making the trace wider, may I know why so?Thanks.SF

author: ataradov
author_rank: Super Contributor
timestamp: January 29, 2018, 01:19:49 am
content: I would definitely try to bypass that switch first.Quote from: sfcircuit on January 29, 2018, 01:13:49 amI have not seen calculations for USB specifically, but that's what happens when you try to do impedance matching for RF and other stuff - traces get wider on standard PCBs. At least that's what I would do in this case, but I never had problems with 10 mil traces either.

author: NiHaoMike
author_rank: Super Contributor
timestamp: January 29, 2018, 02:08:53 am
content: Check if the connection seems to be sensitive to slight movement. I have seen issues with a USB 3 network adapter having problems working with a Raspberry Pi because of that problem.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 29, 2018, 02:37:22 am
content: A power plane is a ground plane, for RF / transmission line purposes, if it is significantly larger than the trace in question, contiguous over the length of the trace, and well bypassed to ground.Tim

author: tan98010
author_rank: Contributor
timestamp: January 29, 2018, 03:39:50 am
content: Edge Cpld Ext (Microstrip) might be a good choice, it will be a "good practice" to route all the USB connection in 90ohm.As an alternative you could use "co-planar wave guide" if you have ground pour beside your diff pair.

author: sfcircuit
author_rank: Newbie
timestamp: January 29, 2018, 05:18:30 am
content: Quote from: T3sl4co1l on January 29, 2018, 02:37:22 amHi Tim, yes, the power plane is significantly larger than the differential signal and almost the same size as the ground plane. I will try the edge-coupled stripline calculation. However, I don't quite understand what do you mean by "well bypassed to ground".

author: sfcircuit
author_rank: Newbie
timestamp: January 29, 2018, 05:21:55 am
content: Quote from: tan98010 on January 29, 2018, 03:39:50 amHi tan,Thanks for your suggestion. My design however has already a crowded slow signal trace on the top layer, I have no choice to route the USB differential trace on the third layer. Regarding the "co-planar wave guide", my design have no ground pour beside the differential pair.

author: ejeffrey
author_rank: Super Contributor
timestamp: January 29, 2018, 05:43:57 am
content: Quote from: sfcircuit on January 29, 2018, 05:18:30 amBasically it means that you have plenty of capacitance between the power and ground plane in all the right places. That creates a low AC impedance between the planes and for the purposes of AC signals makes them equivalent."all the right places" means (basically) wherever your high speed signals begin, end, or change layers. Begin and end are usually easy, as these are the "standard" local bypass capacitors you place on any ICs. But if your signal goes through a via from top to bottom you need a bypass cap between the two internal planes as close as possible to the via. There are a couple cases where you might get tripped up on the bypassing at the signal beginning or end. One would be of the begin or end is a passive component (such as a connector) that doesn't have a power connection and wouldn't ordinarily need a bypass capacitor. The second is if you have multiple power planes, and the one near the signal trace is not the one that powers the chip that produces/consumes the signal.In addition if you have split power planes and you need signals to cross the split, you should have capacitors bridging the gap near the signal crossing.

author: sfcircuit
author_rank: Newbie
timestamp: January 29, 2018, 06:13:00 am
content: Quote from: ejeffrey on January 29, 2018, 05:43:57 amHi ejeffrey,Thanks for your detailed explanation. I do have a split plane where the signal needs to cross over, I will try to remove it or get some caps on it.