Lan transformers CM chokes... confusion - Page 1
Forum section: electronics / projects

author: temperance
author_rank: Super Contributor
timestamp: April 12, 2022, 10:35:24 pm
content: Hi,I'm designing a product which requires and Ethernet connection for which I want to use a jack with integrated magnetics. However, looking into catalogues from Pulse, WE, TE,... one can find many different transformer / CM choke configurations.There are versions with both CM chokes on the cable side while you can also find versions with a CM choke on the Phy side for RX with all sorts of "funny" transformer configurations for TX.I would like to know when to use which configuration and what to look for when you need a MDIX capable mag-jack. (Probably symmetry in case of an MDIX capable device.) I looked into app note for different Phy's. But that doesn't help to answer my question. Even worse, an evaluation board for a TI Phy seems to use the wrong transformer / CM choke combination. (TIDA-00207)Thank you

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 12, 2022, 11:07:14 pm
content: MDIX is pretty much universal these days, also I don't know that it makes much difference anyway, like even in the days of thinnet and AUI ports, the transmitters and receivers weren't very different, at least from what I've seen of them.Anyway, more CMCs means more CMRR, or at least potentially, perhaps. Though I think they all meet the same spec sheet (the important figure here would be CMRR at 10, 30, 100, etc. MHz) so whether it's actually better in practice and "meets or exceeds" the spec, or what, isn't always clear on these things.The downside to the PHY side CMC, is greater stub length of the two phases. These load the output signal, limiting bandwidth. That is, the PHY's output stage is push-pull (one e.g. N-ch MOSFET, pulling down to GND, each side), and it takes a split second for the signal from one to propagate along that stub length (PCB traces and transformer windings) to reach the other side and become balanced again. Which has implications for the CMRR of the thing, too (another good reason to put CMCs on it, though in this case the PHY side CMC might not improve things as much, due to it increasing this stub length).The other major difference is between 10/100 and 1000, where the stub length must be shorter and typically drivers are full bridge instead (both ends driven, so the center tap is not wired to AVCC, merely bypassed with a cap if anything at all). Note that gigabit is still not actually very fast, electrically speaking: 400MHz or so bandwidth, limiting stub length to "merely" some 10s of cm -- still far from restrictive when you're talking on-board trace lengths. (The bitrate is made up in multiple voltage levels (more bits/symbol), or splitting between lane pairs (100BASE-TX only uses two pairs, gig can use all four).)Finally, there's also the various magnetics used for PoE, usually as CT chokes, or combined transformers, taking DC off the center tap so that DC can flow in the common mode on a given pair, and return on the other, or, I think there's a few configurations of it; I haven't designed anything with it as yet. There's also somewhat more specialized parts, like single transformers with low isolation for compact applications (automotive Ethernet?), 100BASE-T1 (single pair, higher bandwidth, half or full duplex), etc. You won't need any of these, unless of course these are features you want to target.For absolutely bog standard 10/100BASE-T(X), the kind with CT primary, CT secondary (with "Howard Johnson" termination resistor to cap to GND), and secondary side CMC, is what you're looking for. Primary (PHY) side CMC optional. Two channels are needed per port ("4 core" or "6 core" set).Tim

author: temperance
author_rank: Super Contributor
timestamp: April 13, 2022, 12:24:45 am
content: Hi Tim, thank you very much for some pointers.Do you mean a discontinuity in the transmission line impedance created by the CMC when you wrote "stub"?Till now, I've found only few mag-jacks with a CMC on the RX pair being placed at the Phy side. I see how this has an advantage over placing the CMC at the cable side because of the, hopefully small, discontinuity created by the CMC when placed at the cable side.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 13, 2022, 05:56:13 pm
content: Well the CMC doesn't necessarily create a discontinuity, it's twisted pair up on the core, that's the point. It might be different dimensions than the cable, might not match exactly, but it can be pretty close still. And there's mismatch due to the terminations, pins, traces and connectors, but all those are very short (low ~cm) with respect to the bit times (multiple ~ns) so aren't an issue.The stub lengths -- consider when a wave enters from the media. It's coupled through the transformer, and one side goes up and the other side goes down, around the PHY side CT. These go into 50 ohm traces on the board, which act in series for a 100 ohm differential total, which couples through the 1:1 transformer to the 100 ohm line just fine. And these traces are terminated into 50 ohm resistors near the PHY chip (but not perfectly near, there are some ~mm between). The characteristic of the PHY output pins is capacitive (open drain, 10/100). In this case, we have one very short stub, the trace extending beyond the termination resistor(s) into the pin. The pin capacitance also reflects some, though only at very high frequencies of course (and the output transistors are sized so that they handle just enough load current (~100mA) while adding minimal capacitance, giving adequate frequency response overall).Note that the pin-to-termination stubs are absent on the 100/1000 (full bridge) case, which has a resistive source characteristic (I think?).But that's fine, that mode doesn't matter, nothing depends on the overall primary side trace length.So the other direction in which there is a stub, is as follows:The 10/100 transmitter is a pair of open drain NMOS. They can either pull down, or turn off; there is no "push up" action. So, to generate a full wave, they must pull alternately. Which we call "push-pull", but it's really pull-pull, the push is reflected through the transformer. Well, consider the step wave from one side turning on. It propagates up the pin and connecting trace, draws current through the termination resistor, and propagates up into the transformer. The PHY primary acts as a 1:1 inverter transformer, flipping this wave so it's now a rising wavefront, propagating onward to the opposing side transistor (which stays off during this phase, at least for class B/D operation*), finally terminating into the resistor on that side.During the propagation of this wave, from one PHY driver to the other, the media sees half the level: the transformer is momentarily driven with (-, 0, 0) for an average -/2 amplitude. When the terminated wave is communicated back to the transformer, it finally sees (+, 0, -) on its terminals, for a full amplitude output.And this propagation is due to the stub lengths of the two sides of the PHY winding. They are terminated, so there's no ringing, but the length is nonetheless present in the output, as a limitation of its bandwidth / risetime.And that length depends on the wire length of the CT winding itself, but also the connecting pins, traces, and any PHY side CMC if applicable.So that's all, just to be clear.*They could be using class A or AB, I don't know; in that case, both transistors are partially on at idle, and one device turns off incrementally while the other turns on incrementally. In class AB, one turns off fully, beyond some amplitude; in class A, both remain on (or one is just turning fully off, at the full output peak amplitude). I'm not sure offhand how much analog they actually use in these things; there is some line and frequency-response compensation, but that might be handled entirely by the receiver, no transmitter involvement at all, I don't know. Read this more as: it could be done this way. I do know that, at least at its most basic, 10BASE-T is Manchester encoded (20MHz clock, 10Mbaud data), full wave, so, class D (devices switching fully on/off, alternately). And, 100BASE-T, I think, is similar but also adding an undriven zero level, so that a transmitted symbol has three levels, increasing data rate slightly. For the multiple levels in 1000BASE-T, they must be doing something smoother; it could still be as simple as a source follower or transconductance stage, but it's probably a bit more involved, to get a stable output impedance as well. Which more than halves the signal amplitude (each drive pin swings 0...VCC at most, not idling at VCC and swinging 0...2VCC), further making the cable quality more important and probably demanding a more sensitive receiver.Tim

author: temperance
author_rank: Super Contributor
timestamp: April 13, 2022, 10:14:32 pm
content: Hi Tim, thanks again for the very extensive clarification.I just found this explanation from you about winding a transmission line onto a core.https://www.eevblog.com/forum/renewable-energy/pulse-transformer-leakage-inductance-is-amazingly-low/Just what I was looking for because I didn't think about it that way before. Unfortunately I can't answer your question regarding the drive structure being used in 100/1000 Phy's.

author: PeteH
author_rank: Unknown
timestamp: April 13, 2022, 10:55:37 pm
content: I've seen some PHYs have issues on networks with some switches... Depending on what side the magnetics common mode choke is on. Very intermittent problem...

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 14, 2022, 01:24:12 am
content: Incidentally, Ethernet is usually (almost always?) toroids, like 1mm thick, 5mm across, nice small things -- but not too small. The LF cutoff (at 100 ohms) is around 20kHz, and saturation is uh, I forget, like 10uVs or something? Enough to do a few us (10s of?) at ~1V, so, typical signal levels (and frequency range) for Ethernet after all. (Ethernet is mostly DC balanced, but has some worst-case codes that need a modestly-low frequency response. LF loss also causes "droop" of square-wave pulses, but this isn't as important as receivers compensate for that too.) So yeah, transmission line transformers, small package (as small as can be, given signal level and LF requirements), low strays, good bandwidth. It's not bad stuff.Tim

author: Scrts
author_rank: Frequent Contributor
timestamp: April 14, 2022, 09:04:16 pm
content: Please be aware that there are PHYs with current output and with voltage output. The choke must match that. I've made a mistake once... Check the supported choke datasheets as well as devkit part numbers for a good reference.

author: jonpaul
author_rank: Super Contributor
timestamp: April 15, 2022, 01:10:01 am
content: Hello just see this nowIn a matched system the issues discussed seem odd.UTP/TP Zo is ~ 110 Ohms.The TX and RX are balanced and meant to have a transformer for galvanic isolation and CM noise rejection.An additional CM choke is effective at frequencies beyond the CM rejection of the trsf due to capacitance P-S.The sequence of connection we have seen and used for decades is alwaysCable>>Connector>>CM choke (optional) >>transformer>>TX or RX IC.Bon ChanceJon