EMC test with 480MHz peak? Any ideas? - Page 1
Forum section: electronics / projects

author: ricko_uk
author_rank: Super Contributor
timestamp: June 26, 2023, 07:35:34 pm
content: UPDATE (OP further below)Hi,I am modifying the PCB and adding as many EMC improving suggestions mentioned above as possible.Because the peak is at 480MHz I am thinking of adding ferrites on theUSB data linestoo. I didn't find much info about this solution online but I did find this app note:https://www.ti.com/sc/docs/apps/msp/intrface/usb/emitest.pdfAnd attached is a screenshot from page 5.- Nctnico in his reply above suggested to place the ferrites near the IC (which I assume makes sense so it stops emissions right at the IC pins) but the attached app note shows the ferrites next to the connector. Any thoughts on why they would be better near the connector? Do they put them near the connector because in that app note they have the termination resistors next to the IC (and they would cause some issues if placed next to the resistors in terms of affecting the impedance perhaps)?- On the LAN9514 that I use the termination resistors are inside the IC (as per second screenshot attached). Where would you place the ferrites?- I am thinking of adding also a USB CM choke on the USB data lines (just in case to test). Where should I place it? At the IC side before the ferrites? The IC side after the ferrites? The connector side?Thank you as alwaysORIGINAL POSTHi,I ran a PCB through EMC pre-compliance and it relatively quiet across the spectrum but has a massive peak (5dB below the limit line) at 483MHz. And another at 345MHz. Graph attached.For the 483MHz peak my first thought was the USB2.0 but there are no USB peripheral connected nor any wires (not USB nor anything else apart from the external brick-type PSU. So the USB hub (LAN9514-JZX) should be completely off. Or does it still send bursts of small data to detect if there is a device attached?If not that, chat else could it be?This is the list of all peripherals and clocks:Compute module (its own clock throttling from 600MHz to 1.2 GHz)LAN9514-JZX Ethernet/USB 2.0 hub running at 48MHz. It has a USB "input" and ethernet and 4 USBs as "outputs"Various switcher PSUs (only a few hundreds of KHz)HDMI (frequency selected by the Compute Module so no idea but I don't think 480MHz is it)Any suggestions perhaps also looking at the other peaks on the graph?Thank you

author: srb1954
author_rank: Super Contributor
timestamp: June 26, 2023, 08:35:28 pm
content: Quote from: ricko_uk on June 26, 2023, 07:35:34 pmGet yourself a set of near-field probes and scan the PCB to see if there any hot-spots corresponding to the frequencies of your problematic emissions.It may also be useful to do alternate scans with the spectrum analyser set to average and peak mode. Comparing these scans against the the QP scans may give some clues as to whether the emission is continuous from a clock source or intermittent from I/O activity.

author: nctnico
author_rank: Super Contributor
timestamp: June 26, 2023, 09:38:57 pm
content: Get some near field probes indeed. But the LAN9514 is definitely a trouble maker. Needs very careful layout, locally filtered power supply (through beads and dedicated analog power plane) and 10 Ohm (@100MHz) beads on the ethernet signals to make it quiet enough to pass EMC testing with an ethernet cable attached. Been there done that.

author: langwadt
author_rank: Super Contributor
timestamp: June 26, 2023, 09:45:26 pm
content: the USB hub probably has its PLL running even with nothing connected

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 26, 2023, 10:06:54 pm
content: That's almost for sure.Now what would help would be to selectively shut down the various peripherals of this board until the peak disappears. The 480MHz peak is high enough that testing this even with a simple antenna and an entry-level spectrum analyzer should be enough to find the culprit, before going back to the EMC lab.

author: ricko_uk
author_rank: Super Contributor
timestamp: June 26, 2023, 10:49:47 pm
content: Thank you all!About the near field probes, I am waiting for the spectrum analyzer so will try that next week. And will also try selective IC shutdown.@Nctnico,I already placed plenty of ferrites on the power lines as per datasheet and app notes. But the "10 Ohm (@100MHz) beads on the ethernet signals" is interesting. So some questions:1) You mention ferritebeadsso I assume on the PCB and in series / inline on the traces going to the connector, correct? I am asking because I have never seen that and could not find anything on online. If you meant on the cable then we already tried and not much difference.2) If you mean to place them inline between the IC and the connector, should I place them near the IC or near the connector?3) about the ferrites, I did place ferrite beads on the power lines. As you can see from the attached schematic, I placed 1 single ferrite for each rail and then between the ferrite andeach oneof the power pins bypass caps. Would you recommend a different configuration?4) if you remember, in your design, roughly how many dBs did you manage to improve by after your suggested solutions?Thank you.

author: nctnico
author_rank: Super Contributor
timestamp: July 01, 2023, 07:18:35 pm
content: I'd change the capacitors to 50V. 6.3V capacitors will have lost 90% of their capacity at 3.3V. Change the 47uf ones to two 10uf 25V 0603 for example. Also add a few 10nf 0402 decoupling capacitors that go close to the analog and digital supply pins.The ferrite beads are inline with the ethernet lines (Wurth 74279274 ) near the chip. See attached schematicAlso make sure to have some ethernet TVS diodes at the PHY side of the transformer to catch peaks that may enter from the ethernet line. The LAN9500 is easy to damage.I forgot how much dB the emissions go lower but I remember it was quite a bit. I choose the ferrite beads specifically to have most of their attenuation at frequencies over 200MHz.However, your 480MHz peak may come from somewhere else on your board. Consider the above as an improvement but it may not solve the problem with the 480MHz peak. You'll need to do some measurements using a spectrum analyser & near field probes in order to hunt down the source of this peak.Recently I had a similar problem and it turned out a pin driving a clock signal that runs for a long distance over a board was set to maximum drive and fastest switching. That needed a bit of software tweaking to reduce the drive strength.

author: ricko_uk
author_rank: Super Contributor
timestamp: July 02, 2023, 05:25:53 pm
content: Thank you Nico!

author: jwet
author_rank: Frequent Contributor
timestamp: July 02, 2023, 06:36:00 pm
content: The other thing to investigate is stuff related to wavelength- at 480 Mhz, lambda in air is 24". In PCB with er of 4 its -12" (/root (er))- these kind of numbers of even fractions of them along the perimeter of a board can make an efficient radiator/antenna. I have had issues with boards acting as efficient "slot antennas" radiating at the edges. You could have a weak 10th harmonic of your USB oscillator, etc and an efficient antenna and it becomes visible in a test. As a test, if possible, scrape some soldermask off and go around the edges with copper tape soldered down at intervals of a cm or so. The real fix would be to spin the board and put a grounded copper perimeter on all layers and stitch them together vertically with VIA's. You might be able to see some of this with your EM probes and an SA. Good luck.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 02, 2023, 07:48:25 pm
content: Quote from: nctnico on July 01, 2023, 07:18:35 pmHow would you know without a BOM? Or size even?Tim

author: nctnico
author_rank: Super Contributor
timestamp: July 02, 2023, 08:54:05 pm
content: Quote from: T3sl4co1l on July 02, 2023, 07:48:25 pmAny cheap 6.3V MLCC will lose close to 90% of the capacitance in any size at over 50% of the rated voltage. Unless you are using some kind of boutique part. Realistically you won't be able to place anything larger than 0603 close enough to the chip the OP is using (interleaved top/bottom). 0402 size (or smaller) is a more logical choice and thus most likely. The schematic I posted shows 100nf 16V 0402 because it is about a decade old already. Nowadays I specify 100nf 50V 0402.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 02, 2023, 09:30:02 pm
content: The voltage rating is irrelevant -- it's a breakdown rating, much like the thermal DC rating of ferrite beads. Like ferrite beads, the saturation depends more on body size than anything else. Look up the characteristic curves of your favorite types some time (if they publish such data at all(!)) -- be prepared to be surprised!Tim

author: ricko_uk
author_rank: Super Contributor
timestamp: July 03, 2023, 12:01:37 pm
content: BTW, looking at the schematic above shared by nctnico, would a pair of data line CM chokes work better instead of 4 ferrites (one on each single line) to reduce emissions?Thank you

author: Siwastaja
author_rank: Super Contributor
timestamp: July 03, 2023, 12:08:50 pm
content: Quote from: nctnico on July 02, 2023, 08:54:05 pmThis is just wrong. Voltage rating is nearly irrelevant; better metric is volumetric energy density, in other words, too-good-to-be-true capacitance in small package means the C will drop more under voltage bias. This is absolute voltage; physics do not care about the voltage rating, and say 6.3V and 25V X7R MLCCs in 0402 package are manufactured the same way, could even be the same part! In other words, if one keeps the same package size (including height!) and picks an MLCC rated to higher voltage, they likely won't see any significant improvement in the actual C under their DC bias, even if it goes from 50% to 10%. Going for a taller package will of course help; or for modest improvement, going through all manufacturers who publish the data and pick one that performs the best.

author: tszaboo
author_rank: Super Contributor
timestamp: July 03, 2023, 02:26:11 pm
content: Quote from: nctnico on July 01, 2023, 07:18:35 pmThere is no correlation between capacitance loss at a voltage, and voltage rating of a ceramic capacitor.There is a very good correlation between size and capacitance loss, bigger parts will lose less.Play around in a bit in redexpert (since you already menationed würth) to see it.mod: And now I see this was mentioned by others, didn't mean to gang up on you.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 03, 2023, 02:59:30 pm
content: Quote from: ricko_uk on July 03, 2023, 12:01:37 pmMaybe. Not really any way to tell; depends on phase of the noise between pins, and phase response of the magnetics (which likely is poor, this far above design frequency). And trace matching and other balance factors.That is, at 480MHz, the magnetics probably have poor CMRR, which is to say, the mode conversion is significant. So it may not matter much that the pins are in phase (where a CMC would help) or not. (I mean, if the pins are in phase, a CMC will still help; but it might not help as much as you would hope, because of the as-yet unknown impedance looking into the transformer(s) at this frequency. Or, maybe it's better with the caps on the other side of the FBs.)FBs, or other normal-mode filtering scheme, is better to the extent that: 1. you don't know the phase of the noise between sources (pins), or subsequent network (i.e. the magnetics); and 2. the desired signal is lower bandwidth (i.e., ~50MHz) so you can afford to use a simple normal mode LPF.Tim

author: nctnico
author_rank: Super Contributor
timestamp: July 03, 2023, 03:15:39 pm
content: Quote from: Siwastaja on July 03, 2023, 12:08:50 pmBut that is the thing: the higher voltage parts are bigger and will hold their capacitance better. Check these (absolutely randomly picked) Murata 100nf 0402 capacitors for example:https://www.murata.com/en-global/products/productdetail?partno=GRM155B31H104KE14%23https://www.murata.com/en-global/products/productdetail?partno=GRM152B30J104KE19%23The 6.3V version is at -20% at 5V while the 50V version is at -20% at 10V. I'll admit that these samples look better than I expected (also due to the relatively low capacitance) in this case but still you can't trust what an assembler will pick from their stock. Voltage rating is something you can use to steer selection though.

author: nctnico
author_rank: Super Contributor
timestamp: July 03, 2023, 03:18:38 pm
content: Quote from: ricko_uk on July 03, 2023, 12:01:37 pmNo, there is already a common mode choke in the transformer. But that doesn't help for signals that are not differentially coupled into the lines. The output stage of an ethernet phy is using pulses (call it a crude PWM) to create the signals. On the cheaper phys, these leak high frequency content onto the lines.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 03, 2023, 08:31:53 pm
content: Well yeah, those are 0.2 and 0.5mm thick, you're proving the point.Compare these instead:https://www.murata.com/en-global/products/productdetail?partno=GRM152B30J104KE19%23(your example)https://www.murata.com/en-global/products/productdetail?partno=GRM152B31A104KE19%23(fair comparison)Conversely, compare these:https://www.murata.com/en-global/products/productdetail?partno=GRM155B31H104KE14%23(your example, thick)https://www.murata.com/en-global/products/productdetail?partno=GRM155B11A104KA01%23(fair comparison)Surprisingly, the HV one still does outperform, though only by a small margin: -16.7 instead of -24% at 10V. So they probably are constructed differently; perhaps the ceramic has to be higher density to withstand 50V, whereas they can get by with a lower grade for the lower voltage rating.The size difference is even more stark in high voltages, where the ceramic is a more reliable insulator (thicker layers to begin with), and parts can be -90% at rated voltage. IIRC, values in X7R from 47nF to 470nF (about the most they advertise) in 630V 1210 are pretty consistently 20-30nF at rated, with the actual value still going up as you go up in rated value, but at a sub-linear rate.Tim

author: nctnico
author_rank: Super Contributor
timestamp: July 03, 2023, 09:22:36 pm
content: Quote from: T3sl4co1l on July 03, 2023, 08:31:53 pmNo. The point is, higher voltage rating = more likely you get MLCC capacitors on your board that keep their capacitance at their working voltage. For larger capacitances this becomes even more important. Typically I don't specify the exact type of MLCC capacitors because there are so many of these out there that every assembler will ask whether they can substitute their random part with the part number you have specified. I just make sure the cheapest part I can find meets the specs. It only gets better from there. Some of my designs are produced by by 5 to 6 different assemblers over their life span so do the math to the amount of work it adds up to versus the cost that is saved. IOW: the more universal your specification for a jelly-bean part, the easier you make your own life.

author: ricko_uk
author_rank: Super Contributor
timestamp: July 04, 2023, 01:07:43 am
content: Thank you both

author: ricko_uk
author_rank: Super Contributor
timestamp: July 18, 2023, 01:20:06 pm
content: Hi,I am modifying the PCB and adding as many EMC improving suggestions mentioned above as possible.Because the peak is at 480MHz I am thinking of adding ferrites on theUSB data linestoo. I didn't find much info about this solution online but I did find this app note:https://www.ti.com/sc/docs/apps/msp/intrface/usb/emitest.pdfAnd attached is a screenshot from page 5.- Nctnico in his reply above suggested to place the ferrites near the IC (which I assume makes sense so it stops emissions right at the IC pins) but the attached app note shows the ferrites next to the connector. Any thoughts on why they would be better near the connector? Do they put them near the connector because in that app note they have the termination resistors next to the IC (and they would cause some issues if placed next to the resistors in terms of affecting the impedance perhaps)?- On the LAN9514 that I use the termination resistors are inside the IC (as per second screenshot attached). Where would you place the ferrites?- I am thinking of adding also a USB CM choke on the USB data lines (just in case to test). Where should I place it? At the IC side before the ferrites? The IC side after the ferrites? The connector side?Thank you as always

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 19, 2023, 12:57:15 am
content: Notice if you don't have a metal enclosure as EMI shield / plane, the PCB becomes it, and the USB shieldsmust be (at least AC) grounded to the PCB.USB can't support very much CMC due to its inherently unbalanced design (SE0 symbol is common mode). The maximum is about 80-120 ohms (@100MHz) for High Speed, or 200-300 ohms for Full Speed.Any noise filtering for incidental purposes (like the LAN noise symptom mentioned above) can potentially use smaller value FBs, or an LC lowpass configuration (with small caps, and lossy L using FBs). You may want to evaluate comm signal quality (potentially requires a standards-verifying USB/Ethernet/etc. tester, or pattern generator + fast scope to measure the eye diagram directly) while testing EMI response. Which, is probably a PITA, but that would be ideal.Tim

author: ricko_uk
author_rank: Super Contributor
timestamp: July 19, 2023, 05:22:06 pm
content: Thank you Tim

author: temperance
author_rank: Super Contributor
timestamp: July 20, 2023, 10:34:47 am
content: Can you post a pictures of the layout of each layer?-Are the diff pair signals matched in length because a perfect diff pair doesn't radiate. Timing alone is not what you're after with respect to USB timing requirements. From a radiation point of view a 100ps mismatch does make a difference because the return path becomes undefined at the signal edges, causing radiation.-Beware when adding filter components onto a diff pair to not create asymmetry (including component tolerances) undoing your length matching.-Are the USB cables attached to your board of good quality? Some cheap cables and even some fancy expensive cables claiming excellent signal fidelity are pretty bad. Cut one open if in doubt. Some are just straight pairs instead of twisted.An app note from TDK with some practical advice regarding CM filters:https://product.tdk.com/system/files/dam/doc/content/emc-guidebook/en/eemc_practice_02.pdf

author: moffy
author_rank: Super Contributor
timestamp: July 20, 2023, 12:20:21 pm
content: Quote from: ricko_uk on July 18, 2023, 01:20:06 pmI would assume the ferrites are near the connector because that is the divider between a controlled impedance/signal environment, to the unknown outside environment I would think it's more about suppressing the outside e.g. RF interference getting inside. Perhaps they could be placed both ends as long as they don't distort the signal too much, but that might be overkill.

author: temperance
author_rank: Super Contributor
timestamp: July 20, 2023, 02:49:33 pm
content: The better option is a common mode choke designed for this kind of signals with the required diff impedance instead of two ferrite beads.I put a link to an app note from TDK in my earlier post.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 20, 2023, 03:30:42 pm
content: Quote from: temperance on July 20, 2023, 10:34:47 amNowthat'sa hell of a strong statement. Surely you can think of some cases where a diff pair, given perfect geometric matching, radiates?Please don't post misinformation like that.QuoteApplication notes, case in point.You'd think, reading this, that USB is a fully perfectly differential scheme and rightly wonder why they only list chokes up to 1kohm, and most of them much less than that. Surely we can go for broke and eliminate any CM issues slam-dunk?A reader would also wonder, reading your post, if USB can then be put over UTP. Can you think of any reasons why not?There are in fact two very strong reasons why not.Quote from: temperance on July 20, 2023, 02:49:33 pmbecause of the nature of USB, this doesn't really matter. A CMC (as such) gives a better eye diagram during the data packet, but doesn't do much overall. At best it's an average-case improvement with a worst-case impairment. It's a statistical sausage effect: tighten one aspect, the other expands.This is why appnotes mustalwaysbe taken for what they are: at best, supporting information, a jumping-off point for further research. They should never be taken at face value. Always read critically.Fortunately, the USB standard is free and open: we need not go to third parties to understand it. We can go straight to the horse's mouth.Tim

author: jkostb
author_rank: Regular Contributor
timestamp: July 20, 2023, 07:19:16 pm
content: I have made several designs with the LAN9514, and all my designs passed with large margins the radiated emission tests without using ferrite beads, common mode chokes in USB lines. Blindly adding ferrite beads and common mode chokes is usually not the way forward for solving these emission issues. From your emission plot you can easily observe that the culprit is some clock source. You need to figure out whether cables are radiating (USB, ethernet, other cables) or some PCB trace. You can unplug all cables and look what effect it has on emission plot. If after unplugging of all cables spectrum remains unchanged, then you need to identify the source on your PCB. As indicated earlier by others you need to use nearfield probes and spectrum analyser. Further you have not given any details about whether PCB is contained in metal (shielded enclosure) or plastic housing or shared your layout. From past experience I have seen emission failures due to poor layout of high speed digital lines. For example a clock routed over slots in reference planes can easily give same emission plots like yours.

author: ricko_uk
author_rank: Super Contributor
timestamp: July 20, 2023, 08:09:21 pm
content: Thank you all,I will post the layout as soon as I get back to the office.In the meantime, I was wondering... If I have a USB pair running over a solid GND plane (i.e. no slots or cuts in the GND plane) that spans the entire length and width of the traces and below a power plane that covers only part of the length of the USB traces, would that increase the emissions significantly?Thank you

author: temperance
author_rank: Super Contributor
timestamp: July 20, 2023, 09:09:08 pm
content: QuoteI will clarify my statement: every differential pair radiates and the radiation depends on the loop area. In case of a differential pair designed as a microstrip onto a PCB with a spacing <1mm and perfect impedance matching along its length, the radiation is insignificant when measured at a distance of 1m.Causes for radiation from a differential signals:1. Rise and fall time mismatch in the drivers.2. Timing differences in the drivers.3. Amplitude differences in the driver.4. Asymmetry in the differential pair.5. Impedance mismatch. (wrong cables attached)6. Coupling onto shields or other things nearby because of the loop area / distance ratio.7. Common mode noise present on the reference plane.https://ewh.ieee.org/r6/scv/emc/archive/2013/January/012013Sam_Connor.pdfQuoteAdding separate components onto both signals like ferrite beads and capacitors will create some asymmetry. Because of that I'm thinking that a CM choke will cause the least disturbance. Nonetheless, inserting "random" components into differentials signals isn't going to work very well.As stated by jkostb who wrote the below quote while I wrote my post:QuoteYou might make things worse and perhaps solve the EMI problem but now the interface isn't always working properly on every device.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 20, 2023, 10:47:29 pm
content: Quote from: ricko_uk on July 20, 2023, 08:09:21 pmThe ground needs to be wider than the bus, by several trace-plane (substrate height) spacings, preferably trace widths as well (whichever is higher). And, if we're talking a strip of ground, with microstrip on top, and less-well-specified stuff on the bottom, then we may want to be concerned about the fields around the whole thing. Like if you launch these traces onto a flex circuit, having the specified geometry, now there's a loop between that cable and the surrounding space that can pick up common mode, and maybe that couples into the signals at one end or the other.But given that limitation, yes, that's absolutely fine. As long as the ground plane is wide enough, and at frequencies where it's an adequate shield (so, some MHz up, more or less), the traces on top don't care what's going on underneath.That means you can still have interference at lower frequencies, where ground isn't such a good shield. The ground impedance will be lower at those frequencies too, so it takes larger currents to cause such interference; a good reason to avoid routing under an SMPS, for example. Go around instead, steer around the close-in current loops of that section. Or if you have a pathological example, like this narrow strip of GND, carrying just this data pair, over a the-floor-is-lava patchwork of nasty power planes and unrelated (noisy) grounds -- that's more like the flex-cable case, with it taped down to a bunch of other nodes that therefore capacitively couple into it, and who knows what that's going to do to the common mode (and in turn CM-DM coupling), like, maybe you'd want to lift one end of it and put the whole thing (GND wrapped around data pair!) through a ferrite bead or something, to help relieve what would otherwise contribute to GND-loop current.Or say this "pair on GND strip" pseudo-cable is routed circuitously around the board, and because it's still "GND" (net), a connection is made lackadaisically back to bulk GND elsewhere on the board -- creating a large open loop, exposing it to fields (again, mostly of importance at lower frequencies, where the shielding value of the GND layer is less).The most common case, I would say, is a whole board poured with GND, and it doesn't much matter what power domains are on the bottom side of that, with respect to traces on the top. The most common case of which is probably 3.3V poured most everywhere. Which, as long as the supplies are well bypassed to GND, it doesn't even matter much which layer the pair is routed on.And, vias don't add much trouble either at these frequencies; that's more something you need to watch out for in the 3Gbps+ range.There is still the separate matter of microstrip radiation, which is generally low for average PCB microstrip dimensions and lengths, but is a nonzero effect. It's normally not an issue for typical signaling standards and commercial emissions thresholds. If you needed an extra 20dB lower emissions, or need to pass particularly sensitive tests (of various kinds, not necessarily regular radiated emissions), you may find (buried) stripline or shielding (or a metal enclosure) is required.Which...Quote from: temperance on July 20, 2023, 09:09:08 pmThat's more like itThere are a few more provisios missing here -- trace length vs. signal frequency, how it's looped around if at all, if there are any resonances or stubs, etc. For the usual case -- and to be perfectly definite, equipment like embedded and small computer boards, typical interfaces used therein (LVCMOS at lower rates, LVDS or similar for wideband), and typical test levels (say FCC Part 15), that can be a passing combination.The key insight is that, any trace exposed on the surface of the board, is a patch antenna. Being narrow, it doesn't couple very much into radiation, but if it were unterminated, quite a bit of radiation resistance could be resolved in its impedance, for example. If terminated, one loses the multiplication effect of resonance, and radiation resistance will be a small fraction of Zo; but, indeed, nonzero.I don't actually have numbers for this; I suppose it's just as well, because modeling radiation simply requires too many variables anyway, and it's best to test. (I also don't have any RF/field simulation tools to model it.) To be sure, most intentional antenna structures do so with much wider patches, or as traces over a ground-free patch (BT/WiFi meander or 'F' type antennas being a commonly seen example). And, given that typical signal levels (some volts at up to maybe ~100MHz, i.e. where LVCMOS becomes inconvenient to use, or 100s mV at ~GHz, where LVDS dominates) typically pass commercial levels (in the 30-40dBuV/m ballpark), under standards such as CISPR 22.Anyway, differential has the bonus that, as long as CM is small (it can be ~mV from typical transmitters), the active area is not so much the full width of the pair, but the quadrupole made between them and the surrounding ground plane. Quadrupoles drop off even faster with distance than dipoles, so the near field can be quite low level. Still nonzero, of course -- and one of the limiting factors of PCB pairs is, they're almost always parallel, i.e. if you look at a PCB from a distance, with a pair running straight along its length, then PAIR_P is always on top and PAIR_N is always on bottom, and that polarity is sensible at a distance with some dipole moment (just with zeroes at more angles because it's actually a quadrupole). It's harder to make a twisted pair (i.e. swap +/- periodically along the route) because vias are generally worse for signal quality than the radiation concern is...Mmm, or maybe it is an overall dipole characteristic still, because a quadrupole would be +/-/+/-, whereas this is 0/+/-/0. Think maybe it's a sum of both cases? Because you could have four points (x+y, -x + y/2, x - y/2, -x - y) as the superposition of a dipole and quadrupole, with the same resulting arrangement. Ah yeah, that makes more sense. Hey, I remember electrostatics...Well then in that case, the dipole of course dominates; but it's less than unshielded untwisted pair (e.g. ladder line) because the ground plane shorts out much of the dipole. It's an intermediate case.QuoteThis is a good primer, at least on topics; I assume it's just slides that went with a talk which gives more detail about things.Actually... p.38 in part answers the question raised above (distance from plane edge) -- it's in terms of skew (propagation delay), but similar compromises to impedance matching and CMRR occur. Oh, this is actually good data down here (pp.30-40 range say) too. Nice!Like, as you can see, the effect of GND via placement is tiny: fractional percent. This isn't relevant to commercially-important standards that are designed for messy on-PCB use, like PCIe and USB -- not to say improvements aren't nice, but also, there's no reason to go out of your way and build everything on Rogers laminate with perfect geometry and everything, that's the whole point of them is to handle modest errors like this. Likewise, the CMRR might be comparable, like in the 40 to 60dB range, so it helps that signals start in the -20 to -10dBV range (~100mV), i.e. 100-110dBuV, so that by the time they might radiate to space, they're down in the 40dBuV range. And, give or take field strength and wavelength, that can be comparably in the 40dBuV/m range as well.It is however relevant to extremely sensitive signals, for precision (~fs jitter?) timing, high purity RF measurements, etc. If you can reclock your signals, and decode line codings, and all that stuff -- please do, by all means! -- but in the few cases where you absolutely cannot, yeah, such lengths are worth going to. (Being this guy works at IBM research, that's a pretty understandable motivation!)Or, not entirely sure what's going on in the pp. 48-55 range -- think there's some context missing here that would be in the talk. Like, why they're looking at these approaches in the first place (explaining because someone else suggested them? suggesting them for potential albeit narrow application? etc.), or what they expected to find, or if it's just throwing spaghetti to see, etc. Sometimes weird things can help (like the EBG structure to get filtering in narrow band(s) only), other times you kinda just have to shield and that's all you can do. (USB is kind of that way, due to its use of the common mode, albeit at lower frequencies than this doc is concerned with -- 100s MHz instead of GHz.)And, balance is hard to construct and maintain, as I think this document kind of illustrates in part; which, it would also be worth asking what the test setups looked like, like for the asymmetric ground via tests, how exactly do you get a 120dB isolation fixture in the first place? That's actually a very good question, but also out of scope of a mere talk; we have to assume that it was characterized as such, but if you're going to rely on these data, you might want to contact the guy to see how that was all done.Anyway, balance is an issue even for Ethernet magnetics, which -- granted, they're only targeting the minimum requirements of the standard (IEEE 802.3xxx) so you'll never see parts that wildly outperform the standard -- but the standard is similarly somewhat relaxed with its specs because it must be commercially practical: not terribly expensive to implement, nor sensitive to, like, cable placement and stuff. If the Ethernet signal level was 10V for example, you might get significant mode conversion and thus radiation just from touching a cable (some turns of the twist closer to your hand than others), and, to be clear I don't mean theamount of mode conversionvaries with amplitude but that the total system, amplitude and conversion gain and radiation all included, would exceed threshold. (Another of those regrettable things with language, it's so tedious to speak precisely about these topics.)Anyway, referring back to your list of points -- and specifically with respect to USB -- USB packets start and end (or just end? I forget exactly, hey it's not like I ever have toimplementthe thing okay?) with the SE0 symbol, which is both lines low -- a common mode symbol. CM filtering corrupts this symbol, causing malformed packets and communication errors; likewise, USB can't simply be sent down UTP through free space, because not only would that CM impedance mismatch, plus and ambient noise, corrupt the SE0 symbol, but the symbol would radiate as well.I have some USB cables right now actually, that I'm not sure how exactly they're failing (frayed braid? fretted connector?), or which ones even are affected, but I've got some ~10s mV of noise on my bench and it goes away when I unplug my USB hub. It looks like low frequency noise (impulsive in the 100s kHz sort of range, at a center frequency in the ~10MHz range -- cable resonances basically, fed by data crossing over a poor ground). And that low frequency, AFAIK, corresponds to packet transmission. It's erratic (noisy) because it's data, of course.QuoteYup. And, as with the Ethernet example -- even when you try and balance things, you can't do a perfect job, not with commercially available parts at least. A CMC will always have more wire to one side or another, or even, like, Idunno, inhomogeneity in the ferrite itself I guess, why not?; and you can't LC filter it (even when you can afford loading C on the line) because even if you use 1% precision capacitors, that's still a 40dB expected imbalance!Tim

author: ricko_uk
author_rank: Super Contributor
timestamp: July 20, 2023, 11:17:48 pm
content: Thank you Tim and Temperance

author: temperance
author_rank: Super Contributor
timestamp: July 21, 2023, 02:50:26 am
content: QuoteThose are indeed just slides and "the talking" is missing. But the slides themself contain interesting information i.e. something to think about. Unfortunately the talk itself is not available on the usual channels.

author: nctnico
author_rank: Super Contributor
timestamp: July 22, 2023, 12:35:13 am
content: Quote from: temperance on July 20, 2023, 02:49:33 pmUnfortunately that does not always help with all the noise. But USB may be less of a problem due to the short cables. I typically put a USB specific common mode choke on USB interfaces but then again, USB never has really long cables attached like ethernet.@ricko_uk: did you manage to make any measurements on your board using a spectrum analyser + H field probes? That really is step one before changing anything in the circuit! If yes, please share the results of these measurements otherwise we'd probably re-iterate the same problem without having any new information that can lead to an actual solution.

author: ricko_uk
author_rank: Super Contributor
timestamp: July 22, 2023, 11:35:23 pm
content: Thank you all.@nctnico:I did and it seemed to be higher along red trace and flexi connector at the end of it (see attached screenshot). Is might be because the plane below it is power instead of ground.I kept the same track-gap as for the blue part of the traces (referenced directly to GND) because I assumed the power plane would act "enough" as reference plane due to the capacitance coupling with the ground plane (an Altium video also suggested that). But the gap between GND and PWR (i.e. core thickness) might be way too much to have enough capacitance to allow the power plane to act as reference plane. I have rerouted all differential pairs so they are all referencing GND directly below them and never change layers.I also added 0402 ferrites and CM choke with overlapping footprint (so there are no stubs) and so I can try various solutions.If you think of anything else please do share it. Feedback, suggestions and tips are always welcomed!Thank you as always

author: nctnico
author_rank: Super Contributor
timestamp: July 23, 2023, 01:36:52 am
content: What kind of connector is that at the end of the red traces? An FPC cable connector? Is there ground next to the differential pair in the flex cable? And what kind of signal is it anyway? USB?

author: ricko_uk
author_rank: Super Contributor
timestamp: July 23, 2023, 02:27:53 pm
content: Yes, it is a FPC connector for a USB signal (see screenshot). In the new version of PCB I am doing there is a GND plane right under it and also directly under all the USB traces for their entire length.Any additional thoughts?Thank you

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 23, 2023, 04:12:44 pm
content: What are the other pins in the connector? Did you try ferrite bead(s) on the cable?Tim

author: nctnico
author_rank: Super Contributor
timestamp: July 23, 2023, 04:26:34 pm
content: @ricko_uk:Ah, that explains quite a bit. For this construction to have any chance to work at all you'll need at least to have grounds next to the differential pair at both sides in the FPC cable in order to form a return path. But it is still iffy to use an FPC cable for USB. Likely the problem isn't in the PCB but in the FPC cable. Did you measure near the FPC cable using the H field probe?

author: ricko_uk
author_rank: Super Contributor
timestamp: July 23, 2023, 11:43:16 pm
content: Thank you both.@T3sl4co1lTim, the other pins are just very low speed digital signals (speaker on/off, alarm flag, and similar ones). I assume you mean ferrite on the external (classic round) USB cable? If so, I didn't try try them because the EMC tests did not pass even without any cables connected. If you mean on the flexi cable (it connects to a micro scanner module), I haven't because it is tiny and haven't seen any "rectangular" ferrites for such tiny cables and the dangling flexi might get pulled out by such ferrite's weight.@nctnico,Nico, that's interesting and makes sense. Tested it just now and they do go up in that area around the cable. The pinout is set by the scanner module connected to it. There is a GND right next to them but on one side only (see attached screenshot). Is that not enough? Would the fact that is is only on one side imbalance it and radiate more?Thank you

author: nctnico
author_rank: Super Contributor
timestamp: July 25, 2023, 02:37:54 pm
content: I'd retest with the scanner attached. At least the lines will be terminated. Testing with unterminated transmission lines is not good anyway. Based on less than perfect grounding in the cable, chances are very high the terminal is a low speed (12Mbit/s) device. So the USB interface is likely to run at relatively low speeds. IOW: all the testing you have done without the scanner unit is irrelevant. If you want to do testing without the scanner unit (which I strongly unrecommend), then solder a 90 Ohm resistor across the USB pins on the FPC connector so at least the transmission lines are terminated.Having an USB common mode choke as close as possible to the FPC connector is a good idea. Additionally there are special ferrite cores that are intended to put over FPC cables (seehttps://www.we-online.com/en/components/products/WE-FLATF) but I'd test without those first.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 25, 2023, 05:32:56 pm
content: Wait, so was the scanner not attached either? Yeah, those ports should be inactive and the culprit lies elsewhere.What was the host again? MCU? Some kind of bridge? Maybe it has poor grounding and that's carrying EMI along the trace (ground bounce) even while the port is inactive?H-field probe should read zero at the connector with nothing plugged into it. Is it a shielded type probe? Maybe you're picking up voltage instead?Oh, what does EDA say the length of that route is (trace / electrical length)?Tim

author: jkostb
author_rank: Regular Contributor
timestamp: July 25, 2023, 06:11:24 pm
content: Have you already retested with all cables disconnected and observed any differences?Did you succeed testing with a near field probe and spectrum analyzer and find correlation with observed peaks?From your figures it can be observed that the frequencies are not broad band. This is an indication that the culprit is some clock source or signal with fast rise times. I have seen and debugged similar radiated emission issues in past. In both cases the culprit was a signal (clock, PWM etc) with fast rise time.Is it a 4-layer board? If not can you provide stackup. Can you show snapshot of top layer and closest reference layer, same for bottom layer and closest reference layer?Please note that if you switch signals with fast rise/fall times from top to bottom layer (assuming 4-layer board) this can cause the behavior which you observed. The return current must also change reference layer (i.e. from GND plane to power plane. If there are cutouts in power plane, the return current needs to find path via closes bypass capacitor). The current loop is an effective dipole and radiate! So if you have excluded that your cabling is the culprit, you need to start examining PCB layout. So from this discussion you hopefully understand that the differential pairs changing layer from top to bottom can already be the root cause. My advise is to route all differential pairs first and try to route it without changing layer. If this is not possible ensure that you always have same reference layer (e.g. GND) as reference layer. Please note that if layer 3 is power plane, you can also add polygon GND pour in power plane just below the differential pair. You need to stitch this small plane with sufficient vias with layer 2 (GND) otherwise it will not work. The same applies for all signals with fast rise/fall times.Hope this helps.

author: ricko_uk
author_rank: Super Contributor
timestamp: July 26, 2023, 09:47:03 pm
content: Thank you all, I will get hold of the spectrum analyser on Mon and run more tests with the scanner attached and compare them without scanner attached. But, as Tim mentioned, I assumed there should not be any activities on the USB bus as the scanner was not attached.In the meantime replies to all your questions:@T3sl4co1l:The USB diff pair lengths are 122mm (both within 0.5mm of each other)The host is a hub Microchip's LAN9514-JZX. I don't think it could be ground bounce because all ground pins as well as the large pad under the IC are all connected directly to GND right at the pin (1mm away) and there is a solid ground plane under the entire board. And the IC large (thermal) pad has also multiple vias. Maybe there are other reasons for a ground bounce?The probe is a Rigol H-field, I cannot find any information whether they are shielded or not.@nctnico:I will retest them on Mon when I get hold of the spectrum analyser again.Why the CM choke is best put close to the connector (while the ferrites close to the IC)?@jkostb:Yes in the new PCB I have routed all traces on the top layer with GN under them.The previous PCB was a 6 layer with the following stackup:SIGSIGVDDGNDSIGSIGThe new one is as follows:SIGGNDSIGSIGVDDSIGThank you all

author: jkostb
author_rank: Regular Contributor
timestamp: July 27, 2023, 06:08:25 pm
content: If I look at your new stackup, then hopefully you have routed all high speed signals at top layer or on layer 3. If you route high speed signals on layer 4 or 6 or you switch from layer 1,3 to layer 4 or 6, then this potentially could cause the issue which you have seen.

author: ricko_uk
author_rank: Super Contributor
timestamp: July 27, 2023, 09:31:49 pm
content: Yes I haveBTW, why is a CM choke best placed next to the connector instead of next to the IC (assuming relatively long traces)?Thank you

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 27, 2023, 11:27:58 pm
content: So you don't have the extra trace-GND capacitance loading it, also coupling in some CM noise from the board (in case there's ground loop voltages onboard, or when routed over dirty supply pours, etc.).Again, you can't use much CMC on USB, at least not the pair; if you have all four lines accessible, a 4-line choke can be used (but these are uncommon and expensive). What is available (without violating USB levels) has little effect (some dB flatband, more vs. resonant peaks).Tim

author: jkostb
author_rank: Regular Contributor
timestamp: July 28, 2023, 04:37:03 pm
content: In addition to what Tim wrote:There exists common mode chokes specially designed for high speed differential pairs (USB3, etc). Have a look at Wurth Electronics WE-CNSW HF series:https://www.we-online.com/en/components/products/WE-CNSW-HFAgain it does not make sense blindly adding these parts because it makes your design expensive and you don't know whether this was the root cause.