FPGA's in Digital Voltmeters - Page 1
Forum section: electronics / general

author: Dmillar
author_rank: Newbie
timestamp: December 31, 2020, 06:26:29 pm
content: Some of the newer DVM's use FPGA, and I am sure D/A converters. I am assuming that from the traditional dual slope integrator on out to the display we have transitioned to basically an SDR sort of environment where the input gets digitized as close to the input as possible. Am I right? or close? I am thinking of the Agilent 34460a and the Siglint SDX3065x meters. Thanks Doug K6JEY

author: Kleinstein
author_rank: Super Contributor
timestamp: December 31, 2020, 07:38:58 pm
content: Most of the newer high end DMMs use an FPGA to implement some kind of continuous time SD ADC or a kind of multi-slope ADC. Besides the FPGA this need quite some OPs, switches and resistors for the analog part of the ADC. The Keysight 3446x do it with a SD ADC build from separate parts and this includes some low resolution ADC chips.The Keysight meter does the AC measurement a little SDR like: digitizing the AC signal at a relatively high speed and calculating the RMS value instead of a more classical RMS to DC converter and than converting the DC signal.AFAIK the SDX3065 uses a high resolution SD chip and the FPGA mainly for interfacing and control of the input part. This configuration is common for the lower grade (e.g. 5.5 digits) bench DMMs, not so much at 6.5 digits. There usually is still quite some gain switching and amplification before the ADC. There is quite some digital processing as part of the SD-ADC, but not very much more than a simple average filter externally. So the FPGA is not really doing number crunching. It is more like doing a job a µC could to as well - just with a little better protection of the code.

author: Dmillar
author_rank: Newbie
timestamp: December 31, 2020, 10:18:08 pm
content: Thank you. It is more complicated than I thought. Do the meters retain dual slope integration, or are the normalized input signal j and reference ust digitized? Doug

author: Kleinstein
author_rank: Super Contributor
timestamp: December 31, 2020, 11:19:34 pm
content: The meters usually use a slightly more complex multi-slope integration, not just simple dual slope. The main difference is that input integration and reference integration happens at the same time. This allows for lower noise, as the input signal is integrated for most of the time and this reduces the input bandwidth and thus noise. It is also more flexible: a dual slope ADC is essentially fixed in speed. The Multi-slope ADC can easily work or something like 5 to 1000 readings per second, with the same hardware.Normally the reference voltage is used as the reference at the ADC and the scaled input signal converted. For tests and internal calibration they may also convert the reference voltage as a separate input signal to get the ADC scale factor.The actual setup can be quite complicated, especially in meters like the 3446x series. Some older meter work similar, but a little simpler and there are good explanations available. In the old days, before FPGA the control was with a µC or special logic chips. A example explanation can be found in the old HP Journal, e.g. 1981 no. 4 , that explains the HP3456, an early 6 digit DMM.

author: David Hess
author_rank: Super Contributor
timestamp: January 02, 2021, 09:27:05 pm
content: Quote from: Kleinstein on December 31, 2020, 11:19:34 pmIt also allows the measured charge to be greater than the size of the integration capacitor which divides the effects of dielectric absorption which at least in my experience dominates error at 16-bits and higher.Siliconix made a dual chip integrating converter in the 1970s like that showing that complex logic was not required however for reasons I have not completely divined, they did not perform better than contemporary dual-slope converters. Performance might have been limited by the automatic-zero loop not canceling common mode error in the input buffer like Intersil did and I suspect Siliconix was aware of the problem.https://en.wikipedia.org/wiki/Integrating_ADC#Multi-slope_run-up