Help figure out a flip-flop's logic diagram? - Page 1
Forum section: electronics / projects

author: D Straney
author_rank: Frequent Contributor
timestamp: July 12, 2025, 07:15:55 pm
content: I'm trying to reverse-engineer a mystery chip that turned up on an old avionics board - I've gotten as far as tracing all the individual transistor connections, and turning them into logic gates, but I can't quite figure out what itdoes.There's a clear R-S flip-flop with the 2 NOR gates and the cross-connections in purple, with 2 AND gates to produce a "gated R-S flip-flop"...but the rest is somewhat confusing. The signal I labeled "set state" clearly drives the R & S inputs of the R-S flip-flop, and there's only one set of conditions that will allow that to go high (producing S=1 instead of R=1) but I can't figure out how the 2 additional NAND gates are working with this, or what their associate inputs are doing.I haven't found any logic diagrams that look anything like this: it doesn't have the multiple R-S flip-flops of the edge-triggered D flip-flops, and it's too complex for either a transparent D-type latch, or a J-K flip-flop. Does this circuit look familiar to anyone?

author: jwet
author_rank: Frequent Contributor
timestamp: July 13, 2025, 02:57:58 pm
content: Sunday morning distraction while I listen to NPR I thought. Didn't reach any conclusions, but maybe sparks something.I redrew it to make it flow left to right. I think there are two latches - a bit like a master slave FF. The NOR at the output and a gated one with the two three input ANDs and the rear facing inverters. SS looks a bit like a clock for a JK or similar- it is derived from 2 and 12. The inverter on SS makes the first latch edge trigger. EN and RST are just setup inputs and are there to confuse you.One of my favorite youtubers is Curious Marc and his genius sidekick Ken Sheriff. They reverse engineer and did similar stuff in the the Apollo Guidance computer. There is a similar logic mess on Ken's blog that turned out to be one bit of adder. Ken has a good blog and Marc makes a lot of great addictive videos. What they have done in the past is to put this stuff into Logism and simulate it for a bit more transparency.Good luck- I enjoy your posts.

author: D Straney
author_rank: Frequent Contributor
timestamp: July 13, 2025, 07:12:26 pm
content: Thanks for taking a look - and those are both good points: that does look like a master-slave FF when arranged that way, and going hands-on in a logic simulator might make it a lot easier to figure out. "Messy latch" is definitely the right name for the first one. Going to play around with it in simulation and see what falls out...seems like the feedback from the "output latch" to the "messy latch" might be a roundabout way of doing a rising-edge trigger or something like that.And yes big fan here too of the "Ken & crew" videos. Glad you enjoy the teardowns as well. This board is really nice-looking but with a bunch of custom-numbered chips with zero data out there. Luckily there are only 3 unique part numbers, so decapped 1 of each type and got some die shots - the other two are simple combinational logic but this one is the real holdup.

author: gerbay
author_rank: Regular Contributor
timestamp: July 13, 2025, 07:22:49 pm
content: It looks like an Arinc-429 decoder with the Manchester decoder part.

author: Terry Bites
author_rank: Super Contributor
timestamp: July 14, 2025, 01:56:31 pm
content: "master slave" RS FF?

author: D Straney
author_rank: Frequent Contributor
timestamp: July 14, 2025, 02:45:19 pm
content: It kind of is -jwet's suggestion was spot-on, and taking the empirical approach and playing around with it in Logisim showed that it's a J-K flip-flop. The "Enable" input is actually a clock, and pins 12 and 2 are K and J, respectively. Here's a simplified schematic drawn in a more intuitive way (as in jwet's example) - you can see how Q and ~Q feed back to the input for the J/K logic, and I think the little feedback loop created by the Q25 inverter is what makes the rising-edge clocking work (instead of being a transparent latch).