Can I get come help with Tspice please? Fatal Error: Redefinition of subcircuit - Page 1
Forum section: electronics / projects

author: Ronny
author_rank: Contributor
timestamp: April 13, 2017, 05:30:22 am
content: Good night everybody,I am working on a project that is getting quite huge, so I decided to make subcircuits and include them in the main file so it does not get out of control.Problem is I am getting an error in the main file, saying that there is a problem in one of the subcircuits, but the subcircuit is working fine by itself.So right now I am making a Flip flop subcircuit (D), and I am using an inverter a NAND and an AND for it. When I try to test the flipflop it says there is a problem in the inverter, but the inverter is working.InverterCode:.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\project.l*INVERTER.subckt inv in out Vdd <============ Trouble is heremt1 out in GND GND CMOSN l='0.18*10^-6' w='1.8*10^-6'mt2 out in Vdd Vdd CMOSP l='0.18*10^-6' w='3.6*10^-6'.ends invThe red line is where Tspice says there is trouble.Flipflop test fileCode:.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\project.l.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\FLIPFLOP\FLIPFLOP.spxflipflop1 Vi Vo E rst CLK Vdd FLIPFLOPVdd Vdd 0 1.8VVe E 0 1.8VVrst A 0 0VVina Vin 0 PULSE(0 1.8V 0 1ns 1ns 3000ns 6000ns)Vclk CLK 0 1.8 PULSE(0 1.8V 0 1ns 1ns 1000ns 2000ns).op.tran 1ns 10000ns.print tran v(Vina) v(CLK) v(Vo) v(Vo1)I don't know if the other files will show the same problem because the fatal error stops the test.Does anybody know how to solve this?Thank you!EDIT: I am not being able to make the line where the trouble appears show in red, it is inside the code box.

author: Ronny
author_rank: Contributor
timestamp: April 13, 2017, 05:35:24 am
content: The rest of the circuit:AND:Code:.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\project.l.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\INVERTER\INVERTER.sp*AND.subckt AND A B out Vdd*PMOSM1 outx A VDD VDD CMOSP l=0.18*10^-6 w=3.6*10^-6M2 outx B VDD VDD CMOSP l=0.18*10^-6 w=3.6*10^-6*NMOSM3 outx A Vx Vx CMOSN l=0.18*10^-6 w=1.8*10^-6M4 Vx B 0 0 CMOSN l=0.18*10^-6 w=1.8*10^-6*INVERTERxinv outx out Vdd inv.ends ANDNANDCode:.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\project.l*NAND.subckt NAND A B out Vdd*PMOSM1 out A VDD VDD CMOSP l=0.18*10^-6 w=3.6*10^-6M2 out B VDD VDD CMOSP l=0.18*10^-6 w=3.6*10^-6*NMOSM3 out A Vx Vx CMOSN l=0.18*10^-6 w=1.8*10^-6M4 Vx B 0 0 CMOSN l=0.18*10^-6 w=1.8*10^-6.ends NANDFLIPFLOPCode:.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\project.l.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\NAND\NAND.sp.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\INVERTER\INVERTER.sp.include C:\Users\Ronny\Desktop\vlsiproject\Archivepull\AND\AND.sp*FLIPFLOP.subckt FLIPFLOP in out enable rst CLK Vdd*=========================================================================*ENABLExand1 enable CLK CLK1 Vdd AND*Latch 1xinv1 in a1 Vdd invxinv2 CLK1 CLK2 Vdd invxinv3 a2 Vo Vdd invxinv4 a2 B Vdd inv*NANDxnand1 A B a3 Vdd NAND*NMOSM1 a1 CLK1 a2 a2 CMOSN l='0.18*10^-6' w='1.8*10^-6'M2 a3 CLK2 a2 a2 CMOSN l='0.18*10^-6' w='1.8*10^-6'*PMOSM3 a2 CLK2 a1 a1 CMOSP l='0.18*10^-6' w='3.6*10^-6'M4 a2 CLK1 a3 a3 CMOSP l='0.18*10^-6' w='3.6*10^-6'*=========================================================================*Latch 2xinv11 Vo a11 Vdd invxinv21 CLK2 CLK1 Vdd invxinv31 a21 Vo1 Vdd invxinv41 a21 B1 Vdd inv*NANDxnand2 A B1 a31 Vdd NAND*NMOSM11 a11 CLK2 a21 a21 CMOSN l='0.18*10^-6' w='1.8*10^-6'M21 a31 CLK1 a21 a21 CMOSN l='0.18*10^-6' w='1.8*10^-6'*PMOSM31 a21 CLK1 a11 a11 CMOSP l='0.18*10^-6' w='3.6*10^-6'M41 a21 CLK2 a31 a31 CMOSP l='0.18*10^-6' w='3.6*10^-6'.ends FLIPFLOP

author: Ronny
author_rank: Contributor
timestamp: April 13, 2017, 07:27:11 am
content: Found the problem.I included the inverter in the AND file and on the FLIPFLOP file. I had to delete the include on the AND file, now it works.