Variable Duty Cycle Square Wave with FPGA - Page 1
Forum section: electronics / general

author: pigtwo
author_rank: Regular Contributor
timestamp: December 03, 2015, 07:02:56 pm
content: Hello all,I have a quick generic question. I'm working with a device that sends data by sending a square wave with varying duty cycles to denote a one or zero.To do this with an FPGA seems pretty simple. I would just have the FPGA count a certain number of cycles until the correct on time is achieved, then count a certain number of cycles to get the low time. This seems kind of cumbersome to me and also will require a much higher clock frequency compared to the output frequency.Is there a better way to do this or is this the best way?I was thinking maybe something with PLLs since you can set the duty cycle when you set them up but I couldn't find anything about changing the duty cycle in real time.Thank you!

author: hamster_nz
author_rank: Super Contributor
timestamp: December 03, 2015, 09:03:53 pm
content: It all depends on your exact requirements...Two shift registers - set up as rolling loops, "0001" in one and a second with "0111" and then switch between them? Fabric clock is 4x the data rateA DDR register, and on one cycle send "0b" and then on the other send "b1", where 'b' is the bit. Fabric clock is 2x the data rateUse a 4:1 SERDES to send 0bb1, Fabric clock is 1x the data rateUse a 8:1 SERDES to send 0bb10cc1, Fabric clock is half the data rate.Use a high speed transceiver to send 32 bits per cycle - 0aa10bb10cc10dd10ee10ff10gg10hh1 (where a,b,d,c,d,e,f,g are the data bits). Clock rate is 1/8th the data rate.(Oh in all cases the leftmost bit is sent first)

author: pigtwo
author_rank: Regular Contributor
timestamp: December 03, 2015, 10:48:35 pm
content: Using a shift register does seem easier. Thank you I'll probably go with that for now. Thank you.I'll have to look into a SERDES later. Just out of curiosity, if I were to try to implement a SERDES, it would essentially just be a parallel to serial converter that ran at a faster clock rate, right? Or is it a more hardware specific implantation(like PLLs on an FPGA).

author: hamster_nz
author_rank: Super Contributor
timestamp: December 03, 2015, 11:56:20 pm
content: Quote from: pigtwo on December 03, 2015, 10:48:35 pmYes, pretty much. At least for Xilinx devices you have your basic data clock, and then a clock that is running at half the SERDES bit rate, and then a strobe that indicates when the new parallel data will be loaded into the SERDES's output register. You have to have the right sort of clock buffer in the right place to make it all work. Seehttp://hamsterworks.co.nz/mediawiki/index.php/DVI-D_Serdesif you want to see one in action.A lot of those suggestions are actually a bit facetious. Here's a few a few reasons why:* PLLs have a minimum clock rate that they can generate - usually between 1 and 10MHz or so, most often based on minimum Vco frequency divided by the PLL's highest divider.* Basic I/O pins have a max frequency, limited by the speed of the logic in the fabric (maybe 300Mb/s if you are lucky)* DDR pins have a max frequency too, twice that of the basic pins, so from 0 to 600MB/s* Because SERDES blocks are driven directly by a PLL, they usually have a minimum rate of a few 10s of MB/s up to the early 1Gb/s range* High speed transceivers also have a minimum and maximum clock rate due to the limits of the transceiver PLLs, which tends to overlap the higher end of the SERDES range

author: marshallh
author_rank: Unknown
timestamp: December 05, 2015, 08:15:17 pm
content: Depends how fast you need it. Since a reasonable upper limit for FPGA logic is about 200 mhz, divide by 8 (example number of cycles per "bit") and again by 2 (because you have rising/falling edge) and you get 12.5mhz generated.For my nixie driver I did exactly this, except with 1024 steps, and a compare counter.PLLs arent usable for this since reconfiguration takes many cycles and sometimes you have to reboot them.