TPS61021A boost regulator can't handle 50mA - Page 1
Forum section: electronics / general

author: hlab
author_rank: Contributor
timestamp: April 29, 2024, 04:59:43 pm
content: Hello all,I'm in need of some pointers for a problem I have with a TPS61021A boost circuit. I've designed a small GPS tracker device that is supposed to run from a single AA battery. The boost circuit is supplies a 3.3V LDO with 3.6V, with a maximum draw of 150mA. Without the GPS unpowered, the entire circuit draws around 25mA, and the boost converter has no problem operating all the way down to 0.5V as the datasheet indicates, with around 80% efficiency at this voltage. But as soon as I connect the GPS module (which is using 25-30mA), the efficiency drops off a cliff. At 2.0V, the input current is 1A. If I decrease the input voltage further to 1.5V, input current quickly rises to 3A (which is the internal current limit) and output voltage falls out of regulation. L1 is BDHE002016101R0MQ1 1uH inductor from Pulse Electronics, with a saturation current of 3.6A. C1, C2, and C3 are CL21A476MQYNNNE, with an effective capacitance of 18.8uF at 3.6V. The output voltage of the boost converter is spot on 3.6V, so I can rule out the resistor divider being incorrect. One point that may or may not be relevant is that when I supply 3.6V on Vout with the the boost converter disabled, I get ~2V at Vin. The datasheet seems to indicate this shouldn't be happening due to the 'True output disconnect' feature.Troubleshooting I've done so farMy first thought was the inductor was saturating for some reason, so I put an identical inductor in parallel with L1, but the efficiency numbers were the same.I forgot to add the feedforward capacitor to the current design, but I haven't experienced any instability issues. Just to rule this out, I've added a 10pF cap in parallel with R2, but I didn't see any difference in efficiency.I tried adding/removing output capacitance, still no effect.At higher input voltages like 3.0V, I'm seeing the expected 2MHz switching frequency on the scope, and nothing stands out as unusual. Tonight I will collect more datapoints with the scope.All of these findings have been replicated on multiple units, so I don't think faulty components are to blame.At this point, I'm starting to wonder if there's a problem with the layout, given the relatively high switching frequency of 2MHz. The chip's ground pad extends on the same layer to the input and output caps. There's also an uninterrupted ground plane under the whole circuit. I tried to minimize the switching loop size, but maybe there's something I missed.Any suggestions from power supply gurus out there?Best Regards,Caleb

author: artag
author_rank: Super Contributor
timestamp: April 29, 2024, 11:08:33 pm
content: Not sure about the reason for the high current draw.However, applying voltage at Vout might well produce something at Vin. The output disconnect feature is so you can fully switch off the output (rather than getting the input passed through to the output as happens with a simple boost). I wouldn't say it offers any guarantees about backwards paths whether through the inductor or through internal circuitry (note that the gate drive circuit has both Vin and Vout connected to it but what happens inside isn't shown on the datasheet.

author: __steven
author_rank: Newbie
timestamp: April 30, 2024, 02:39:41 am
content: Caleb, can you confirm that the PGND pad is indeed connected to ground in your layout (I believe this is pin 9)? I cannot tell from the photograph. Alternatively, have you attempted reflowing the IC such that you can validate that the PGND pad is making a good connection to the pad? I have had IC's that use this pad as an internal reference act funny when the part is not correctly soldered. It should dance under waving hot air.Steven

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 30, 2024, 12:53:28 pm
content: Quote from: hlab on April 29, 2024, 04:59:43 pmThat's quite an extreme drop in efficiency. If your measurements are correct, that excess power is being dissipated somewhere, and it's probably getting very hot. Do you have access to a thermal camera?If possible, I would try disconnecting the LDO and other load circuitry from the TPS61021A and test it with a simple dummy load (electronic load or dummy resistor), that way you will know exactly where power is going.Quote from: hlab on April 29, 2024, 04:59:43 pmIf nothing else is connected to Vin, then it's not surprising to see some voltage there due to a few uA of leakage current. I'm betting if you add a 1K resistor from Vin to GND the voltage there will drop a great deal.Also would suggest checking the PGND connection. In your layout screenshot it doesn't even look like there are any vias connecting it to anything...

author: hlab
author_rank: Contributor
timestamp: April 30, 2024, 08:06:24 pm
content: Thanks for the input guys. Yes the ground pour is continuous below the chip, you can't tell with that screenshot. Its definitely possible the ground pad isn't soldered since I didn't assemble these myself, I will have to check on that. The board does a good job of keeping the chip cool though, my finger says it's only 50-60C. I don't have an adjustable load, but I will test with various resistances on the output with the LDO disconnected. I have doubts that I'll learn anything from that, because when I supply 3.6V at the LDO's input, the entire circuit only draws 50-60mA as previously mentioned. All the datapoints I've collected so far indicate the power is being lost in the boost regulator itself. Very strange....

author: wraper
author_rank: Unknown
timestamp: April 30, 2024, 08:10:55 pm
content: Chip certainly needs vias to GND plane under its center pad. Why so thin trace to the inductor? AGND is totally screwed up, don't reinvent the wheel and tie it and feedback resistor directly to PGND pad as shown in the datasheet.

author: hlab
author_rank: Contributor
timestamp: April 30, 2024, 08:37:57 pm
content: QuoteThe chip datasheet doesn't mention vias under the PGND pad, so I though I would save some $ by skipping via-in-pad. I don't see why vias are necessary there? Shouldn't most of the current be going through the top copper? I'm also not following with the AGND connection, since the rest of my circuit is referenced to the 2nd layer ground plane, shouldn't AGND be connected here to minimize noise?

author: wraper
author_rank: Unknown
timestamp: April 30, 2024, 08:41:04 pm
content: You don't need via in pad. Just normal 0.3 mm vias and tent them from underside. Some solder sucked in via won't be an issue there. I think tying AGND to C3 GND terminal with as short as possible jumper likely will be enough to fix the issue.

author: hlab
author_rank: Contributor
timestamp: April 30, 2024, 08:47:48 pm
content: Quote from: wraper on April 30, 2024, 08:41:04 pmI'll give that a try, but I'm still not understanding the issue with the current AGND placement. Could be the chip is just very layout-sensitive I guess, especially given the black-box internal compensation.

author: wraper
author_rank: Unknown
timestamp: April 30, 2024, 08:48:26 pm
content: Quote from: hlab on April 30, 2024, 08:37:57 pmThink how large of a GND loop you are creating considering there are no vias under PGND. I suspect chip is latching up due to large voltage transients between its grounds. IME it's a very bad idea trying to separate GND pins. It may even work fine on a first glance then latch up once in a year when already sold to customers.

author: __steven
author_rank: Newbie
timestamp: May 01, 2024, 04:42:25 pm
content: I have to agree with wraper here. Can you try connecting the net of pin 1 and the net of pin 9 together close by and see if your issues are resolved? A simple jumper wire should suffice. Perhaps from C3 to R3?

author: hlab
author_rank: Contributor
timestamp: May 02, 2024, 03:12:58 pm
content: Last night I tried tying AGND pad directly to C3's ground, still no effect. I don't have the best scope probes (200MHz rated BW), but it appears that I've got some ground bounce at the SW pin, which reaches ~ -1.1V for 5 nS maybe. There's also some ringing after the low side switchoff, first peak reaches ~4.5V for 10nS, but that may partially be due to probes. At one point, I swear I measured the output at 4.5V, at which point the overvoltage protection kicks in, but since then I've only ever gotten 3.6V. Output remains in regulation until approximately 1.7V, at which point input current is 1.5A. I've also tried 0.47uH and 2.2uH inductors with little effect.

author: __steven
author_rank: Newbie
timestamp: May 02, 2024, 03:39:55 pm
content: Looking back at your initial post, I see that you mention that the boost circuit works fine until you connect the GPS module, is that correct? If that is the case, can you share the GPS LDO circuit? I now believe that is the issue.Steven

author: hlab
author_rank: Contributor
timestamp: May 15, 2024, 05:13:20 pm
content: Life has been a little busy recently, but I finally managed to figure out what was going on. In my circuit, I had connected the VBCKP on the GPS directly to the battery. My original design was supposed to run from a 3V lithium primary cell, which is within the specified 3.6-1.65V backup range. Somehow the 3.3V rail was back-feeding into the battery through the VBCKP. There must be a PFET in the GPS's power multiplexing circuit whose body diode allows current from VDD to pass through to the battery. Maybe the PFET is driven from VBCKP, and you get strange behavior when the voltage is below 1.65V? In any case, severing the trace that connects VBCKP to battery appears to solve my issues.

author: Harry_22
author_rank: Frequent Contributor
timestamp: May 15, 2024, 06:46:01 pm
content: Hello hlab! Have you tried connecting a regular 100 Ohm resistive load instead of GPS?

author: hlab
author_rank: Contributor
timestamp: May 15, 2024, 07:36:27 pm
content: Yes, I've tested with 47 ohm resistive load with no issues whatsoever