Reoccurring interrupt of same priority on 8051 architecture - Page 1
Forum section: electronics / general

author: Dajgoro
author_rank: Frequent Contributor
timestamp: December 29, 2017, 02:35:39 pm
content: Hi.I'm a bit unsure what exactly happens in the following scenario with a 8051 system:I have three external sources that generate a interrupt which is fed to the mcu via a single INT line.The interrupts are generated at random times, they might occur all at the same time, or in very short time intervals.In my case I have three timers rolling over which are clocked with a variable frequency which then latch a new value on one of the three dac-s, pull the INT line low and the mcu then needs to prepare a new value for the dac of which the timer rolled over.So the situations which might occur is that a interrupt is asserted, the mcu goes to service the interrupt, and just before it leaves the interrupt routine the same interrupt is asserted again, but this time from another peripheral, which again pulls the same INT line low which caused the interrupt in the first place.What does happen in such a situation?Does the mcu leave the interrupt and not service the new interrupt or does upon leaving reenter the interrupt routine?In short, I need to make sure that all the peripherals are serviced, whenever the interrupt is asserted, even if the servicing occurs a bit later.

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: December 29, 2017, 08:06:43 pm
content: How can you tell which of the three external sources pulled the INT line low?

author: ebclr
author_rank: Super Contributor
timestamp: December 29, 2017, 08:16:19 pm
content: http://www.8052.com/tutint.phtml

author: Dajgoro
author_rank: Frequent Contributor
timestamp: December 30, 2017, 12:43:01 am
content: QuoteI don't, I have to poll.There lies also part of the problem, since a new int can occur while I'm polling, and that source was already checked.So what should happen is for the interrupt routine to run again.QuoteIt just says: "In the case of Timer and External interrupts, the corresponding interrupt flag is cleared." and "Nothing can interrupt a high-priority interrupt--not even another high priority interrupt.".But does then asserting the external interrupt make it reenter the interrupt routine once it has finished the one it started already or is it ignored?

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: December 30, 2017, 05:42:36 am
content: Quote from: Dajgoro on December 30, 2017, 12:43:01 amPollingishow you tell.To work properly the interrupt must be set to level-triggered, and the devices must hold it on until they are polled. In the ISR you poll all the devices, which releases the interrupt.QuoteYes.Exactly what are these external sources?

author: David Hess
author_rank: Super Contributor
timestamp: December 30, 2017, 06:03:16 am
content: If the 8051 external interrupt pin is configured for level triggering, then the interrupt will be retriggered until the service routine resets the hardware which is holding the level. If edge triggered interrupts are used, then alternate provisions must be made to prevent missing an interrupt.

author: Dajgoro
author_rank: Frequent Contributor
timestamp: December 30, 2017, 03:24:20 pm
content: QuoteI mentioned them in the first posts, they are three async timers overflowing on variable input frequencies.QuoteAndQuote from: David Hess on December 30, 2017, 06:03:16 amYes, I see, this is the info I needed, thanks!I went looking into that and I found I need to set the IT0 bit in the TCON register, it is nicely described in this presentation on page 13 and 14:https://www.slideshare.net/daniemol/8-interrupt-8051So now if an interrupt occurs right before leaving the interrupt routine after it processed another interrupt with the interrupt set to trigger on low state it should reenter the interrupt routine and handle it, and keep handling interrupts that pop up until the INT pin goes high and stays high.

author: David Hess
author_rank: Super Contributor
timestamp: December 30, 2017, 03:41:59 pm
content: Quote from: Dajgoro on December 30, 2017, 03:24:20 pmExactly. Of course this depends on the interrupt signal being reset which may or may not require a specific action by the interrupt service routine. Presumably devices which generate level sensitive interrupts are designed to handle this automatically when a register is read or other access is made. If an edge triggered interrupt signal was converted to a level triggered interrupt signal with a set/reset flip-flop, then the latch would need to be reset by the interrupt service routine.