Bus switch with data-hold - Page 1
Forum section: electronics / projects

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: September 27, 2022, 03:49:46 pm
content: I'm struggling to find a chip which can multiplex a bus over two sets of outputs, but also hold the last value it had on the currently-not-selected set of outputs. I'm not sure if it doesn't exist (outside a CPLD/FPGA) or whether my google-fu is being shown to be sadly lacking once again...Basically, I want to drive both an address bus and a data bus from a pin-constrained microcontroller, but the address bus is set up very early in the clock-cycle, and the data bus doesn't need to be valid until much later. When the data busisvalid however, the data sheet says the address isalsovalid. So I'd like to drive the address bus, switch to the other outputs at some later time and drive the data bus - while the address is still being driven by the intermediate buffer.Something like:Code:┌───────────┬─────────────┐│ │ │ Last dataSelect │ │ Port A │ ──────────▶──────────▶│ │ │port B │ Input │ ││ side ├─────────────┤│ │ │──────────▶│ │ Port B │ 'now' dataData │ │ │ ──────────▶│ │ │└───────────┴─────────────┘I'm sure something like this must exist, but I can't seem to find the magical incantation to summon it from the internets, any help very much appreciated...Never mind, of course as soon as I posted a question about it, I foundsomething I can useto do the job. either in combination with a NOT gate, or just using 2 pins for /OE. The magic term was "flip flop", which makes sense in hindsight...

author: Benta
author_rank: Super Contributor
timestamp: September 27, 2022, 06:26:49 pm
content: There are several ways to skin this cat, but it's very hard to say as we don't know which control signals are available.An octal D-FF is indeed a possibility if you can trigger it correctly, an octal transparent latch could also be the solution.

author: srb1954
author_rank: Super Contributor
timestamp: September 27, 2022, 08:15:45 pm
content: Quote from: SpacedCowboy on September 27, 2022, 03:49:46 pmThis sounds very much like a common multiplexed bus micro which can easily be demultiplexed with a 74xx373 (or 74xx573) transperent latch or similar. The '373 or '573 is preferred in this application as it has the benefit of propagating the address through to its output pins immediately easing the timing for connected memory chips and peripheral chips. The '574 is a D-type latch so the address output is not updated until the clock signal is pulsed so the new address is not valid until later in the cycle whereas the '373 merely holds the previous address when its strobe goes inactive.Multiplexed bus micros usually have a strobe output, often labelled ALE (address latch enable), which is designed to directly connect to the LE (latch enable) input of the '373 to control the latching and holding of the address.Which micro are you using? There will usually be a diagram in the datasheet or user manual showing how to demultiplex the address bus.

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: September 30, 2022, 05:32:44 pm
content: Thanks folks, in fact I was guilty of over-thinking it. I realized that I don't need the flip-flops at all - the bus access is separated sufficiently in time that I just need output-enables on the level-translators. The setup looks as below (setup.png) and the clock-cycle signaling details are in clock-cycle.png.In order to generate the /MPD and /EXSEL signals, I want to read the upper 8 bits of the address, do a lookup to see whether this page is being served from the external system, and assert either or both of them depending on which memory location is being requested. I want this to be programmable, but in days of yore, this was all done with fixed hardware that could respond reasonably rapidly (for the time) so there isn't much time budget - about 40-45ns. Still ought to be plenty for an FPGA, even with 10ns of delay in either direction for the level translation (once worst-case clock cycles are taken into account).Anyway, I only need the upper 8 bits of the address in the purple time-region, I then have aeons to read the (green region) lower 8 bits and construct an address if required, go fetch the data from RAM attached to the FPGA, and present it during the (red) time-region. I don't care what the address is when I'm driving the data-bus, all I need to do is make sure OE is set appropriately on the various level translators.

author: exmadscientist
author_rank: Frequent Contributor
timestamp: September 30, 2022, 06:21:13 pm
content: It sounds like you're converging on a solution you like, but just for posterity I'll suggest an answer for the more general case too. You can do this pretty readily with your favorite tristate switch driving a bus hold buffer or two (one buffer can serve both "phases"), such as a LVTH244 or similar. These guys are not that common, and a little mysterious, but when you find a use for them, they can be really useful. They're basically just beefy logic buffers with an input keeper circuit, if that helps demystify them.