Lattice Certus-NX PCIe, or alternative - Page 1
Forum section: electronics / general

author: davorin
author_rank: Unknown
timestamp: October 20, 2021, 02:19:45 pm
content: Good afternoonOn the search for an FPGA with built-in PCIe block I stumbled upon the Lattice Certus-NX product and the corresponding PCIe eval board...But when I do a simple design with the PCIe x1 core enabled, synthesize is okay but mapping fails...So is this again another product from LAttice where they require you to buy an expensive 1-year license to use what's already built-in?Is there another, preferrably low-cost, FPGA alternative which doesn't require you to buy a license and can be used with a free synthesize tool?thanks in advancerichardPS: At least their Radiant software is easier to install compared to the alien rpm fiddling on a Debian system requiring you to install obsolete libraries (o;

author: mon2
author_rank: Frequent Contributor
timestamp: October 20, 2021, 03:04:13 pm
content: Do you require native PCIe support? Gen1 or is it faster ?A practical approach is to consider a PCIe to PCI bridge and then apply the Gowin PCI FPGA with their free toolchain. Much more cost effective. The lack of proper support with Lattice is disturbing. It is obvious that they do not wish to entertain the smaller developers.For the PCIe to PCI transparent bridge, recommend the Diodes (aka Pericom) line. We have very high volumes of designs using this approach using ASSP PCI bus devices. The use of Gowin FPGA for PCI bus is on our pending project list.

author: davorin
author_rank: Unknown
timestamp: October 20, 2021, 03:21:34 pm
content: Interesting approach...know Pericom from 20 years ago with their logic level shifters....Also interesting you use Gowin....evaluating them for another project.Native would be nice...also for the learning factor....dunno if Xilinx offers a license free implementation..project is a simple pcie x1 io board to put on github...Haven't checked Trion devices what they offer...But sure I'll have a look at Pericom...

author: mon2
author_rank: Frequent Contributor
timestamp: October 20, 2021, 03:42:00 pm
content: Can you share more details on your requirements for the GPIO interface? Would like to at least offer component details where we can.The Diodes PI7C9X113SL is a transparent PCIe to PCI bus bridge for Gen1 speed. It will be backwards compatible with all PCIe slots (x1 -> x16). We use them in many of our designs. The current market price is insane. The drop in replacement is the PI7C9X118SL. Same device, different p/n. Don't ask...There is some stock of this device available from Mouser. We can help to review your schematic if needed but is very simple to deploy. The bridge features an EEPROM to correct / program any of the default registers but to date, have shipped product with the eeprom blank. No compatibility issues to date using a 4L PCB with impedance controlled traces for the PCIe bus layout (Gen1 speed).Fairly sure the PCIe to PCI bridge offers GPIO pins onboard. However, can certainly see the value to use a FPGA to bit bang out some state machine, etc. so the idea of a native PCIe or PCI device inside a FPGA is desirable.Efinix is a good company to watch but had to side track for the past few months to Gowin as Efinix does not offer MPI DSI support where as Gowin does. Gowin is very cost effective for their devices (work with Edge Electronics in the USA for the best pricing if you can). We are sourcing through them but having the parts drop shipped to us from HK to save on the USA applied tariffs as we are in Canada.The support from Gowin is top notch - the best we have seen from the assorted FPGA firms we have dealt with to date. Most of the FPGA vendors / factories do not reply back to us and others report - 'just read the docs and work it out' comments. After weeks and weeks of troubleshooting, we convinced the factory, every time, that they made mistakes.What is our time worth ? To where do we send my invoice ? Tired of correcting other's mistakes in the semiconductor business and all this so we can buy their silicon?? We are far from being verilog and FPGA pros but getting very comfortable with Gowin tools. Just need to study their GAO. Have an excellent support contact in the USA if you need help.Consider a Gowin FPGA with a hard CM3 CPU with enough LUTS to allow you to embed the PCI bus interface. Then the FPGA fabric and handle the GPIO or you can use the CM3 (will be slower).One key concern is that what about the device driver to support this widget. You are ok to write code for Windows / Linux drivers ?Also, a good website in case you have not seen it...https://www.fpga4fun.com/PCI-Express.htmlJean has excellent articles on this website. We have learned a great deal about FPGA from here.

author: asmi
author_rank: Super Contributor
timestamp: October 20, 2021, 04:48:55 pm
content: Xilinx offers free IP for PCI Express endpoint or root port. Just this week I've built a Linux system on Zynq 015 with PCI Express 2.0 x2 root port using that IP and got few PCIE cards I had around to work (among them 2.5G ethernet card and some usb 3.0/1G ethernet combo card I bought on Amazon some time ago). Chip supports x4, but the board I use only routed 2 lanes. I'm working on a new PCB which would have several PCIE ports - x1 and x4 via switch for further experiments. I also have a few Zynq030 chips laying around that I've managed to snag for cheap, they will be next once I make that board, as they theoretically allow PCIE 3.0x4 (though I will have to implement it myself as Xilinx only provides IP for 2.0).One thing is that PCIE switches currently are super expensive and hard to find in stock anywhere. So I will probably have to resort to some shady places to get some, but for a prototype that shouldn't be a big deal.

author: davorin
author_rank: Unknown
timestamp: October 20, 2021, 04:59:58 pm
content: Very interesting....Zynq.....so Artix-7 should handle this as well..just did some HDMI with it...Did you connect the PCIe lanes directly to the edge connector?

author: asmi
author_rank: Super Contributor
timestamp: October 20, 2021, 05:08:39 pm
content: Quote from: davorin on October 20, 2021, 04:59:58 pmYep (through AC-coupling caps for TX lanes of course), you will also need to make sure you provide PCIE ref clock if you are implementing a root port, it's not required for endpoint. Currently I usethis boardas a proof of concept, which is why I'm limited to x2 arrangement. You can download a baseboard schematics and take a look if you're curious. Or you can check out Xilinx AC701 schematics - that board has PCIE x4 edge connector (while my board has a slot because it's a host).The idea of the new board I'm working on is to provide an assortment of x1 and x2/x4 ports so that I can use it while designing endpoints in the future.Just make sure you use the right package, as not all Artix packages have bonded MGTs (just like Zynqs - 010 and 020 don't have them, but 015 does). Also remember that -1 speed grade can only do PCIE 1.0 (2.5 Gbps per lane), while -2 and above can do 2.0 (5 Gbps per lane), which of course is backward-compatible to 1.0 endpoints if required.

author: Yansi
author_rank: Super Contributor
timestamp: October 20, 2021, 05:09:38 pm
content: Also I think Cyclone IV I is pretty cheap having a hard PCIe IP, but I am not sure if you need license to run the IP, or if they have it for free as Xilinx has it.

author: davorin
author_rank: Unknown
timestamp: October 20, 2021, 05:34:29 pm
content: Hmm...this LimeSDR project uses a Cyclone IV GX and states:"The gateware can be built with the free version of the Altera Quartus tools."https://github.com/myriadrf/LimeSDR-PCIe

author: asmi
author_rank: Super Contributor
timestamp: October 20, 2021, 05:46:22 pm
content: Quote from: Yansi on October 20, 2021, 05:09:38 pmI think PCIE 1.0 is a bit too ancient. As far as I remember, there are some versions of Cyclone V which support 2.0, but I'm not sure as I have no experience with them.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 20, 2021, 05:49:48 pm
content: The Lattice ECP5 also supports PCIe. But the IP also needs a license...Apart from Xilinx, I don't know of free IPs from vendors for PCIe.For Intel:https://www.intel.com/content/www/us/en/programmable/products/intellectual-property/ip/interface-protocols/m-pci-express-protocol.htmlalso requires a license, but they have an evaluation mode.

author: davorin
author_rank: Unknown
timestamp: October 20, 2021, 05:56:03 pm
content: That would leave Efinix Titanium Series...though no hardware available atm...Ti90 and above should do PCIe Gen4.....gonna try tomorrow if the IDE already supports it..

author: Yansi
author_rank: Super Contributor
timestamp: October 20, 2021, 06:04:18 pm
content: Quote from: asmi on October 20, 2021, 05:46:22 pmAncient or not, I see no specific requirement for version of PCIe. Depending on the job, Gen 1 may be good enuf. Or, by varying the angle of the view, Cyclone IV is ancient itself anyway.

author: asmi
author_rank: Super Contributor
timestamp: October 20, 2021, 06:24:26 pm
content: Quote from: Yansi on October 20, 2021, 06:04:18 pmXlinx 7 series is rather ancient too, yet they support 2.0. I actually tried implementing 1.0 root port first, but both of PCIE cards I had laying around (Usb 3.0/1G Ethernet combo card and 2.5G Ethernet card, both PCIE x1) refused to work properly in 1.0 mode. Even PCIE 2.0 is too slow for USB 3.0 if you have multiple ports (my card had three), but at least it's something that I envision using - for example PCIE-to-USB 3 is the only reasonable way to add USB 3.0 support for regular Zynqs (not MPSoCs).

author: davorin
author_rank: Unknown
timestamp: October 26, 2021, 10:48:30 am
content: Was looking the past days on Aliexpress for a cheap FPGA PCIe card for getting my feet wet....Then I stumbled upon one card that is in the MiniPCIe form factor...though sadly EP4C15GX....According to the schematics a rather simple design.....which raises one question in me...When I don't use most of the IO banks, can I leave their power supply pins unconnected and just route the GND pins?Or would this cause unpredictable results in the logic?

author: BrianHG
author_rank: Super Contributor
timestamp: October 26, 2021, 11:23:31 am
content: Quote from: davorin on October 26, 2021, 10:48:30 amRead the FPGA data sheet in the DC characteristics.VCCIO pins have a maximum and minimum compared to the rise and fall of VCCINT.I usually leave such banks at 3.3v or 2.5v and leave a few spare IO pins on pads next to the FPGA just as emergency extras.

author: jeremy
author_rank: Super Contributor
timestamp: October 26, 2021, 11:36:36 am
content: Getting the pcie xdma block working on artix7 is very easy (assuming the MGTs are wired up correctly) with free tools. I had previously put aside a week to work it out, but I was done in <2hr. xdma drivers in Linux are available in source form:https://github.com/Xilinx/dma_ip_driversHere is an example of using xdma in python on Linux:https://github.com/RHSResearchLLC/NiteFury-and-LiteFury/blob/master/Sample-Projects/Project-0/Host/Host/dma-test-2.pyAnd an example of using the optional AXI-Lite interface:https://github.com/RHSResearchLLC/PicoEVB/blob/master/Sample-Projects/Project-0/Host/blink-leds.py

author: davorin
author_rank: Unknown
timestamp: October 26, 2021, 12:01:33 pm
content: Thanks for the pointer :-)Well Linux is definitively my target system...though it's been almost 20 years I wrote/modified kernel drivers (o;Stumbled upon lately during my research over this RIFFA framework project...someone worked with this as well?Just saw many aliexpress suppliers use that in their example designs...

author: asmi
author_rank: Super Contributor
timestamp: October 26, 2021, 02:01:21 pm
content: Yea, Xilinx is definitely doing an excellent job on supporting PCIE designs. My Z015 project with PCIE root complex has been the easiest project I ever had. The only issues I encountered was 1) 2.5G Ethernet PCIE card based on Realtek RTL8125A chip required firmware and it needed longer CPL completion timeout setting (by default it's 50 us, but 50 ms is also an option), and 2) my USB 3.0/1G ethernet combo card refused to work unless I connect SATA power to it (also easily fixable as my devboard has a Molex 4pin power connector wired up, so a single Molex-to-SATA power adapter did the job). Just for fun I bought a cheap M.2 to PCIE x4 adapter and a small 500G NVMe PCIE drive on Amazon, and it worked with no fuss in PCIEx2 mode (limitation of my devboard) once I included the driver in the Linux build.So if you can afford a Xilinx solution, I would definitely recommend going for it. It requires no HDL coding, it's free and there are some tutorials online, for example here is a quicktake video on a subject:They are using a rather expensive devboard in that video, but I use much cheaper MYD-C7Z015 board by MyIR, (it's US$390 and you can buy it via Mouser), and the steps are the same (of course except that you can only do an x2 design as it's PCIE slot has only two lanes wired up).

author: davorin
author_rank: Unknown
timestamp: November 01, 2021, 07:58:59 am
content: Good morningWas browsing aliexpress over this weekend and saw some cheap XIlinx Artix-7/Kintex-7 PCIe boards in the US$ 190 - US$ 350 price range...like this one for example:https://de.aliexpress.com/item/4001076104078.html?spm=a2g0o.cart.0.0.16ae3c00kASGqo&mp=1Has anyone used some of the PCIe boards listed there and can share his experience?