Is this routing bad/messy? - Page 1
Forum section: electronics / beginners

author: aaronhance
author_rank: Regular Contributor
timestamp: December 16, 2015, 06:27:54 pm
content: Hello! I'm looking to get some feedback on a little bit of routing/layout of the 4 layer board I'm making. The usb data lines are matched to about 0.1mm, from what I've read this is ok. I have ground planes around and under the crystal, and the caps are near to the mcu. Is there anything here that needs correcting or improving?Thanks!

author: stmdude
author_rank: Frequent Contributor
timestamp: December 16, 2015, 08:12:09 pm
content: Well, I'm not an expert, but I've built more than a few functioning boards..The crystal routing looks good, a bit overkill, but it would certainly work.Usually, just a trace that's tied to ground around the crystal is enough, hence the name "guard ring".Oh, and if you're running out of PCB space later on, have a look at FA-238 (3.2mm x 2.5mm) sized ones.Without knowing what MCU you're routing for, the decoupling looks a bit odd. Usually, you do a trace from the MCU into the power-rail, and place the cap as close to that pin as possible/convenient. The other pad of the capacitor goes the shortest route possible to ground. Usually just a via down to a ground-plane.The ground-pins of the MCUs are treated the same way. Shortest way to ground, which is usually a via.Also, all traces seem to be the same width. You seem to have a distribution-tree going on already, which is good. I usually beef up the trace that is the "trunk" of the tree, as to reduce voltage-drops and voltage-differences on the different VDD pins of the MCU itself.Now, if you have a power-layer going on, just ignore what I just rambled on about.Oh, and yea, 0.1mm matching of the USB lines should be fine. Just double-check the datasheet for your MCU so that you don't need in-series resistors for it. If it's USB host, you might also need a pull-up for the D+ line.

author: aaronhance
author_rank: Regular Contributor
timestamp: December 16, 2015, 08:55:19 pm
content: Thanks for the tips, I've changed it to a power plane under the mcu and will re-arrange the caps.

author: mariush
author_rank: Super Contributor
timestamp: December 16, 2015, 09:15:09 pm
content: The crystal footprint is huge compared to the mcu and other parts... have a look at digikey or other shops, they have smd crystals with built in capacitors and in much smaller footprints and with very reasonable prices.Other comments,,, the picture is really to "suck" to give some meaningful advice... looks like an IC with huge amount of pins for the small size, with HUGE capacitors and resistors compared to the IC size and the USB connector footprint.. something doesn't seem right to me. The traces are also looking bad, with 90 degree angles and all those vias under the IC etc etc..

author: stmdude
author_rank: Frequent Contributor
timestamp: December 16, 2015, 09:22:25 pm
content: Just noticed something..The crystall has a rectangular thing around its footprint, and the traces to it and its capacitors are intersecting it. Is that on the copper-plane? If so, then it won't work.

author: aaronhance
author_rank: Regular Contributor
timestamp: December 16, 2015, 09:31:54 pm
content: Quote from: stmdude on December 16, 2015, 09:22:25 pmThanks for pointing it out I think it may be copper, I guess I messed up when making the footprint and used that instead of a white line, partially due to eagles fantastic tool names.EDIT: this is what I've got now:

author: stmdude
author_rank: Frequent Contributor
timestamp: December 16, 2015, 09:41:14 pm
content: So, which mcu is this?It would help if I could read its datasheet to see what the decoupling is supposed to be like.Also, why 4-layer? I can't see anything on the board that would warrant it.

author: aaronhance
author_rank: Regular Contributor
timestamp: December 16, 2015, 10:03:16 pm
content: Quote from: stmdude on December 16, 2015, 09:41:14 pmhere's the datasheet:http://www.farnell.com/datasheets/1506142.pdfIt's a PIC32MX575F256L-80I

author: Neilm
author_rank: Super Contributor
timestamp: December 16, 2015, 10:03:55 pm
content: When doing decoupling, the trace should go from the via, to the capacitor then on to the processor pin. This will ensure that the capacitor is the source of energy for the current spikes rather than the power plane thereby reducing the noise on the power plane.

author: aaronhance
author_rank: Regular Contributor
timestamp: December 16, 2015, 10:10:20 pm
content: Quote from: Neilm on December 16, 2015, 10:03:55 pmThanks for the tip!

author: john_p_wi
author_rank: Regular Contributor
timestamp: December 16, 2015, 10:21:04 pm
content: You could really tighten things up, additionally I would suggest having the decoupling caps parallel to the processor, to have the traces as short as possible between the pins. This app note is from atmel, but demonstrates similar methods:http://www.atmel.com/images/atmel-2521-avr-hardware-design-considerations_applicationnote_avr042.pdfAdditionally, search for app notes for the processor family that you are using, there should be a wealth of knowledge contained in them.

author: aaronhance
author_rank: Regular Contributor
timestamp: December 16, 2015, 10:35:03 pm
content: Quote from: stmdude on December 16, 2015, 09:41:14 pmIt's 4-layer because I have that fine pin pitch mcu and I also have 2x 48 pin devices, I figure 4 layer would be easier, besides 100x100 4-layer is the same price as 200x100 2-layer from the manufacturer I'm going with($75 for 5 boards).

author: Gurpreet
author_rank: Contributor
timestamp: December 16, 2015, 10:42:33 pm
content: From which manufacturer are you getting the boards made from?

author: aaronhance
author_rank: Regular Contributor
timestamp: December 16, 2015, 10:47:15 pm
content: Quote from: Gurpreet on December 16, 2015, 10:42:33 pmpcbway

author: robotix3
author_rank: Regular Contributor
timestamp: December 16, 2015, 11:30:43 pm
content: A good way for beginners to learn, I have found, is to look at reputable open-source boards and analyze what the designer is doing. Sparkfun.com has all of their in-house boards downloadable in Eagle format, I would check these out. Compare the PCB layout to the schematics. Look at trace widths, trace groupings, copper pours, via placements, etc.

author: stmdude
author_rank: Frequent Contributor
timestamp: December 17, 2015, 07:50:47 am
content: Alright, skimmed the datasheet, and came up with how I would have done it.All signals are on the top layer. The bottom layer (only two layers) is just a massive ground-plane.PCB Editor view:3D Front:3D Back:The two-pin header next to the USB connector is where "VDD" comes from, as I had no idea how you were getting your VDD.Without knowing exactly what you want to do, I'd still venture to guess that two layers would be plenty for your design. TQFP-64 with 0.5mm pitch isn't really fine-pitch these days with manufactured PCBs and decent tools. Neither would some 48-pin packages change that. I've never had to go 4-layer yet, and I regularly do designs with multiple 100+ pin components with <=0.5mm pitch. And, as I mentioned, I'm not an expert.

author: tron9000
author_rank: Frequent Contributor
timestamp: December 17, 2015, 08:45:19 am
content: Quote from: aaronhance on December 16, 2015, 06:27:54 pmBottom right, there's a trace that goes across the copper relief of the component hole. That may be an issue.

author: alexanderbrevig
author_rank: Frequent Contributor
timestamp: December 17, 2015, 08:58:55 am
content: Quote from: stmdude on December 17, 2015, 07:50:47 amPretty sure you've made some mistakes on those decoupling caps though

author: stmdude
author_rank: Frequent Contributor
timestamp: December 17, 2015, 10:23:37 am
content: Quote from: alexanderbrevig on December 17, 2015, 08:58:55 amMight have, but if you see something I've missed, let me know, and I'll update it.I just noticed that I didn't re-do the copper-pour, so the 2-pin connector effectively shorts GND and VDD, which would be an issue if you actually tried to power this board up. Doesn't change the routing though

author: alexanderbrevig
author_rank: Frequent Contributor
timestamp: December 17, 2015, 10:43:54 am
content: Quote from: stmdude on December 17, 2015, 10:23:37 amRight now nothing would be powered.

author: HackedFridgeMagnet
author_rank: Super Contributor
timestamp: December 17, 2015, 10:46:49 am
content: Putting the IC at 45 degrees can help with fine pitch stuff. Looks pro too.

author: stmdude
author_rank: Frequent Contributor
timestamp: December 17, 2015, 11:04:42 am
content: Quote from: alexanderbrevig on December 17, 2015, 10:43:54 amGawdammit.. That'll teach me to route before my morning coffee.. Jeez.

author: stmdude
author_rank: Frequent Contributor
timestamp: December 17, 2015, 11:14:37 am
content: Ok, take 2. Now, after my coffee

author: ElektroQuark
author_rank: Unknown
timestamp: December 17, 2015, 11:44:02 am
content: You may need a parallel resistor of about 1M with the crystal. Not always necesary but if it refuses to start working take a look at it.

author: v8dave
author_rank: Regular Contributor
timestamp: December 17, 2015, 12:49:25 pm
content: Don't have any 90 degree track bends. Use 45. I also see a few lines that are not at 45. Mostly aesthetics but it can make routing around them easier too so try to stick to horizontal, vertical and 45.Beef up the power rails even if just short. Use the technique someone posted for connecting the decoupling caps to the micro power pins. Power issues are the biggest cause of failure in processor designs.Use smaller via's for your signal lines. This will make routing easier too.

author: AndyC_772
author_rank: Super Contributor
timestamp: December 17, 2015, 02:12:39 pm
content: Quote from: alexanderbrevig on December 17, 2015, 10:43:54 amWhoever drew this info-graphic clearly has a very poor understanding - if any - of how high frequency currents flow in a PCB, what the priorities are when routing power traces, and the roles of the decoupling cap and the board's internal plane-to-plane capacitance. I'd describe it as highly misleading, bordering on just plain wrong in some cases.Have a read:https://www.eevblog.com/forum/beginners/how-much-noise-on-power-rail-is-normal/msg478428/#msg478428

author: aaronhance
author_rank: Regular Contributor
timestamp: December 17, 2015, 03:49:45 pm
content: Thanks for the help guys! I think I might also switch to a smaller cap size rather than 1206's

author: tron9000
author_rank: Frequent Contributor
timestamp: December 21, 2015, 11:23:19 am
content: Quote from: AndyC_772 on December 17, 2015, 02:12:39 pmQuoteYou know I was looking at that thinking: "there's something not quite right." and then read your other post and then it made sense.Given that the OP is starting out on PCB's that info-graphic could lead him down the garden path.I always though figure d) was the ideal way to minimise trace inductance?

author: AndyC_772
author_rank: Super Contributor
timestamp: December 21, 2015, 12:27:24 pm
content: The GND layout in (d) is OK, though it could still be improved by bringing the vias closer to the respective component pins. In terms of topology, though, it's good in that:- inductance between the IC and the cap is minimised, by using the plane to link the two rather than a surface trace, and- inductance between the IC and the intrinsic capacitance between the power and GND planes is kept to a minimum.The VCC layout is less good, because there's too much inductance between the connection point into the power plane and the IC pin. If it's desirable to have just a single via, it's better to put it between the capacitor and the IC. This minimises inductance between the plane and the IC, but still maintains much of the benefit of the capacitor.

author: DutchGert
author_rank: Frequent Contributor
timestamp: December 22, 2015, 05:10:57 pm
content: How are you programming the PIC?Why not put VCC on an innerlayer fill?minimise traces between pad-gnd via and cap-vcc pinstick to 45 degrees corners, also route tracks 0/90/45 degrees