which one's better? Rigol DS1202CA or Instek GDS-2202 - Page 1
Forum section: electronics / general

author: blueboy
author_rank: Newbie
timestamp: June 17, 2011, 12:09:50 am
content: Hi guyscan help me again..?which one's better for my home lab?1- Rigol DS1202CA [ 200Mhz ,2 GSs/s, 1450 $ , Made inChina]Code:http://www.tequipment.net/RigolDS1202CA.htmlor2- GwInstek DSO 2202 [ 200Mhz ,1 GSa/s, 1450 $ , Made inTiwan]Code:http://www.tequipment.net/InstekGDS-2202.htmlplz share ur own reviewthanks..

author: Mechatrommer
author_rank: Super Contributor
timestamp: June 17, 2011, 04:49:46 am
content: well, 2GS/s vs 1GS/s tells me something!

author: Bored@Work
author_rank: Super Contributor
timestamp: June 17, 2011, 05:47:17 am
content: Quote from: blueboy on June 17, 2011, 12:09:50 amWhy don't you get your lazy arse up and read the specs?

author: blueboy
author_rank: Newbie
timestamp: June 17, 2011, 10:17:50 pm
content: Hey Guys..I know the2Gs/ssample rate is better1Gs/s...i just find report about INSTEK GDS-220XCode:https://www.youtube.com/watch?v=BdPkQHO4A68&feature=relatedand a rate compare between Rigol DS1000CD & GW Instek GDS2000Code:https://www.youtube.com/watch?v=zuE-jkpyN4Q&feature=relatedand report a problem in Rigol DS1102Code:https://www.youtube.com/watch?v=W7Opur1Xbvs&feature=relatedbut i cant find nothing about Rigol DS1202CA.. its mean it had not any bugs?Can itrustto this China Scope "Rigol 1202CA?thanks

author: Mechatrommer
author_rank: Super Contributor
timestamp: June 17, 2011, 10:23:44 pm
content: link pleaseeeeeee...

author: tinhead
author_rank: Super Contributor
timestamp: June 18, 2011, 12:00:27 am
content: the answer is very simple:Instek GDS-2202 have 100Mhz single shot bw which is indication for 100MHz clocked interleaved ADCs.Rigol DS1202CAhave one two channel 1GSs ADC.On Rigol CA, if you sample with 2GSs then they are interleaved too, so the double sample rate is not necessarily better than 10 x 100MHz clocked ADCs (or 8 x 125MHz) on other models (Instek, Rigol D/E, Hantek and so on).Sure, you will have maybe a bit less aliasing issues due higher (single) sampling freq, but the diff will be small.This means Rigol CA series is better (at least on paper), but only if you enable both channels (to prevent interleaving).And btw, 1GSs is anyway enough for 200MHz bw.

author: Mechatrommer
author_rank: Super Contributor
timestamp: June 18, 2011, 12:33:56 am
content: so meaning with both channel on, rigol is not in interleaved mode, so assuming the adc chip and brand is near perfect, and with "proper" sincx, rigol can reconstruct 400MHz signal perfectly?ok we know rigol sincx is sux, so we just turn off the sincx in scope, and hack it in pc software later for proper sincx?

author: Unknown
author_rank: Unknown
timestamp: June 18, 2011, 04:00:25 pm
content: According to the Nyquist-Shannon sampling theorem, you can reconstruct a signal if you sample faster than two times the bandwidth of the signal. So if you sample at 1GS/s, signals with a bandwidth less than 500MHz can be completely reconstructed. The major issue with applying this theorem to a DSO is that it's about thesignal bandwidth, i.e. the fastest frequency component in the signal. In real life, the front-end doesn't have an infinite roll-off, so higher frequency components will be present. The limited sampling time (<< infinite) also adds extra high-frequency components. This screws up your ideal interpolation. This is why scopes with a Gaussian response need a sampling rate about 10x higher than the bandwidth, but scopes with a so-called brick-wall response need only a 2-4x higher sampling rate. Agilent has a nice appnote about this.Another issue is that you need ideal sinc interpolation of infinite length.Of course the DS1052E has nowhere near 500MHz analog bandwidth, so the whole discussion is mostly academic.

author: tinhead
author_rank: Super Contributor
timestamp: June 20, 2011, 12:48:30 pm
content: Quote from: Mechatrommer on June 18, 2011, 12:33:56 ama perfectly synchronous interleaved ADCs will do the job exact the same as non-interleaved one,but in the reality you will never get them to work perfect, so additional waveform distortionis coming from interleaving, see Agilent app note 5989-5732EN.pdf

author: Mechatrommer
author_rank: Super Contributor
timestamp: June 20, 2011, 03:25:27 pm
content: thats what i tried to demo. in non interleaved mode, signal reconstruction should be better, or what? and alm's answer, if there's higher order harmonics then of course aliasing will occur, no matter how perfect sincx is. and i think, we should also consider noise, where in reality zero noise adc is nonexistence. so even a perfect 400MHz sine is injected, the internal of dso will create harmonics from noise which will corrupt sincx. and the point is, as you said, a perfect interleaving mode is impossible, making reconstruction even worst.

author: tinhead
author_rank: Super Contributor
timestamp: June 20, 2011, 07:40:19 pm
content: Quote from: Mechatrommer on June 20, 2011, 03:25:27 pmthe reconstruction itself is always as good as the sampled data, no matter if interleaved or not.With interleaved ADCs the clock path need to be very exact, which can be of course tuned because as EEyou can calculate potential clock delay. However the random jitter will be already enough tocreate waveform distortion during sinx reconstruction. On Rigol E/Hantek/UNI-T etc. class of DSOs we have alreadyup to 650ps total jitter which is large number and you can see distortion already on signals above samplerate/10.The jitter (and resulting error) is not because of interleaved ADCs but because of bad clock, which is of coursetypical because in all these designs FPGA is responsible for clock generation.You can take any DSO (with int. ADCs), connect all the ADCs to low jitter clock domain (let say total jitter 50ps, for UNI-T you will need 4 clocks on same die, for Rigol 10 clocks ... ugly thing, and of course the phase shift need to be controlled by sw in let say 50-150ps steps) calibrate DSO and you will see almost perfectly reconstructed 200MHz sine wave on 1GSs range DSO.However if you look what's available on market you will see that such low jitter clocks are expensive, they actuallycosts more than complette DSO in china.So for sure this tech. works almost perfect, but only if you don't care about costs. As Rigol started with CAseries there was no Agilent DSOX series, and the price for CA series was really high. Today you canbuy 60MHz CA model for 500EUR, which is cheap (PLL clock and ADC costs already 250EUR).You can imagine now why there is only small sample memory - because nobody would buy 100MHz chineseDSO for 2k EUR (it is not only extra memory chip necessary, the FPGA need to be faster and have additional i/o pins,the additional dev. work costs money too).Quote from: Mechatrommer on June 20, 2011, 03:25:27 pmthe noise didn't really matter that much, for good reconstruction on interleaved ADCs you need to have low jitter clocks,good signal path, good calibration/compensation for potential parts tolerance and of course exact the same vertical ADC gain/response. For 8bit ADCs the vertical gain/tolerance are not that critical as long you not push them to the limits.So again, common problem for all low ranage DSOs is the clock jitter, and of course all manufacuturers know it (that's probably they even don't care about not sufficient filtered ADC supply, or overclocked ADCs .. because it didn't really matter, the jitter is destroying everything anyway ).Now back to topic, for sure Rigol CA with non interleaved ADC is a good value for money however there are other design aspects which i personaly don't like, especially the odd display, definitely too small sample memory and yeah the firmware.