Partial slope compensation for better boost inductor utilization  - Page 1
Forum section: electronics / projects

author: uer166
author_rank: Super Contributor
timestamp: August 11, 2021, 03:06:10 am
content: Some questions/ideas related to to a 2kW boost converter. It's a peak current current control slope compensated. The issue I ran into is that the usual slope compensation ballpark of Vo/(2L) is so high that at my 60% duty the peak current achievable is quite low.E.g. inductor saturates at 11A, so that's the maximum initial current I can set, yet at 60% duty the slope compensation brings that down to ~6A at that point in time so it's shit utilization. So 2 options I thought of:Set initial current limit higher than inductor saturation. I think that's a terrible idea and would fault out the hardware overcurrent latch."Delay" the slope compensation until later in the cycle, essentially chopping some initial part of the down-slope to below inductor saturationHas option #2 been ever done in practice? Are there any stability issues with essentially disabling the slope for the first 20% or whatever of the cycle? Attached is a analog trace of the DAC-generated cycle-by-cycle current limit as an example. I think it would allow me to use most of the inductor and still have no sub-harmonic oscillation steady-state?

author: xavier60
author_rank: Super Contributor
timestamp: August 11, 2021, 07:54:44 am
content: I don't have a direct solution.Instead of constant frequency, constant-off-time type control is supposed to cure sub-harmonic oscillation.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 11, 2021, 05:40:49 pm
content: You can't have slope compensation AND a precise current limit; that's simply the tradeoff. Choose everything (inductor, switches, etc.) large enough to handle the worst case output current and ripple, or choose a different method.As a rule, I strongly recommend against doing anything nonlinear in the control loop. There are tons of possibilities, but that's the thing. As soon as you're looking at a nonlinear dynamical system, analysis becomes exponentially harder, and you have to do so much more work to prove that the system is stable, well behaved, easy to design, etc. Some nonlinear systems have analytical results (meaning, you can fairly easily prove that all operating corners are well-behaved), most you're at the mercy of your intuition, and how many simulations you run. And it's bad enough starting with the peak current mode control, which isan implementation of the logistic map function(cool, huh?).Regarding your proposed method: how is the delay set? Shall it be variable, or fixed? How is the waveform generated? If you simply delay the summation of slope and sense signals (as in the standard UC3842 circuit for example), you're truncating the slope -- resulting in a trapezoidal slope waveform (not a delayed ramp), putting a huge step in your signal; extra work is required to remove that step. (Probably not a lot of work: the delay can for example release a switch holding a capacitor + CCS at ground, so the ramp starts from zero volts, at the delay.)If the delay is fixed, then for pulse widths less than the delay, there is no slope compensation. At low output voltages, current can still be continuous, and bifurcation occurs. (By the way: almost all references insist that instability occurs above 50% duty. This is, at best, erroneous. It's actually about inductor current going continuous (DCM to CCM boundary). In a typical flyback design, 50% duty is the design nominal condition, coincident with this condition, and I think this is why they always say so; they've simply forgotten that their example was crafted to hit BCM at 50%. For arbitrary ratios, absolutely nothing important happens at 50%.)Or the delay might be proportional to (Vout - Vin), but that just forces maximum compensation at minimum output, and the current limit spread problem is basically the same.We could go further and consider a nonlinear ramp, which is always continuous (no switched or piecewise-linear behavior), but whose slope varies with time. Should it be steeper at the start (an RC integrator would do a fine job for this), or at the end (a ramp into a x^2 or exp(x) function, say)? I don't think either case really helps, as you're still subtracting from sense current and thus changing the current limit.Maybe the ramp or offset should be stateful. We could sample the inductor current at (or just after) turn-on, and thus infer its minimum peak current, or the average. That sounds complicated, but also suggests something else much simpler (see below).I think the whole purpose of peak current mode control, is it's cheap. You can do it with a low-side switch and shunt (for boost and flyback applications), and the control is simply an oscillator, flip-flop, comparator and error amp. Super simple, cheap to make, easy to design. The downside is the high ripple fraction, typically over 100% (DCM) but able to go a bit lower, via slope compensation, if the looser current limit is acceptable.And that doesn't scale well, because efficiency is more critical at higher power levels. Your core loss must be enormous..? Would you be interested in reducing that?Average current mode is preferred for higher power levels. It can be an old school e.g. TL494 control, wired for current feedback (you do need a measure of continuous inductor current*), then add a voltage error amp to set current setpoint and regulate output (which can be as simple as a TL(V)431 or LM321). Input current is well defined at all times, no compromise with duty cycle; output current is limited (depending on Vout), except for Vout < Vin of course.*Three typical ways:1. With current transformers: one each goes on the switch and diode. Their outputs are diode-ORed into a common burden resistor. (The intermittent primary current, combined with the intermittent load (it's only Rburden in the forward direction), allows flux reset to occur, at least over modest ranges of duty cycle. Recommend adding clamps to prevent extreme duty, say <5% or >95%.)2. With shunt resistors: if common grounds are not required, this can be placed in the input ground return path. Else, it's in series with the VIN end of the inductor, and a current sense amp, level translator or analog isolator is required.3. Hall effect sensor. This is probably the easiest, but doesn't have great bandwidth; probably maximum Fsw around 200kHz, with loop bandwidth much lower. (HE sensors typically roll off at 100kHz. Loop BW / Fsw ~= ripple fraction is why this can be okay.)On a related note, if you haven't already, consider multi-phase interleave. You need a means of synchronizing multiple controllers at a fixed phase shift (and obviously this is easiest for fixed-frequency controls), and you need current mode channels so that they can be wired in parallel. Then, a common voltage error amp sets their currents together, and everything shares and tracks. (You can't simply phase shift a common PWM signal: mismatch in driver/switch timing, and inductor ESR, will cause huge mismatches in current flow, in CCM.) Maximum input and output ripple current is reduced proportionally, and average (with respect to operating point) goes down even more (for example, two phases at 50% duty and 180° phase, cancel out perfectly, drawing no ripple current at all). This really just saves on input and output capacitors, but the capacitors required for a single phase 2kW converter are huge, and just going to 2 phases is a very worthwhile improvement.Tim

author: uer166
author_rank: Super Contributor
timestamp: August 11, 2021, 06:00:18 pm
content: Thanks for the feedback (heh) Tim. Some more background that maybe I should have included:This is already a 2-phase interleaved boost, each phase handles 750-1kW. They're all perfectly synchronized to reduce/cancel some of the capacitor ripple.Efficiency is >99.1% boosting 150 to 250V at 750W tested on a single phase, so no, the core losses are actually quite small in the grand scheme of things. I'm running maybe 60% ripple fraction. At this efficiency I am perfectly happy. I expect the efficiency to increase slightly when running both phases interleaved.I'm using a low-side shunt in the FET sourcesThe ramp is generated by a DAC that runs in ramp mode. A 1MHz timer is used to decrement the DAC each pulse, creating the sawtooth. To "delay" that ramp I simply gate that timer with another, it is easily variable in softwareThe whole current control loop is running inside the STM32 hardware (comparator, timers, DAC, opamp)The outer voltage control loop is running at 10kHz sample rate, I absolutely cannot use that to do average current mode control, way too slow

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 11, 2021, 06:02:59 pm
content: If you're curious, here's a full wave forward converter with double current mode control, using a TL598 (494 with totem pole outputs):Heh, I forgot that I even did it that way, there's a primary side shunt resistor -- which gives a crude measure of inductor current, because it's multiplied by PWM% -- it's only correct when the transistors are on. So it reads extremely low at low duty (startup / fault conditions), which is dangerous, but at least it's something. (The RC lowpass filter coming off the shunt, the R could be in parallel with a diode to speed up the path at high currents -- pushing it into a peak-current-mode sort of regime. This would likely make the thing unstable, and screech or hiss; but safely limiting current is the higher priority.) Note that this continues to function even if the secondary side is unpowered (ISO12V failed -- this is provided by a separate UC3843, not shown).With the secondary side circuitry active, first the shunt resistor senses inductor current, and feeds this back to the TL494; the current setpoint in turn is driven by the voltage error amp, which regulates actual output voltage.So the overall characteristic is a smooth and well-behaved current-limited voltage output, with probably some crunchy behavior if the aux supply gets disabled somehow. Current ripple is low in CCM, and efficiency is quite reasonable. (Incidentally, I found SiC schottky run absolutely cool here (3-4A rated diodes, output is only about 1A), while UF5406s or whatever I tried first, got much too toasty. Hard-recovery losses, man...)Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 11, 2021, 06:09:26 pm
content: Quote from: uer166 on August 11, 2021, 06:00:18 pmAh, that's much more advanced than I would've assumed!Oh wait, is this that old boosting thing, for, uh, I forget what even, but someone was working on that. It's been a while!How about, if you're measuring output current, just do a feedback loop on that (perhaps in parallel with the voltage loop, similar rate, just I_setpoint = min(Verr, Ierr) or whatever? oh and integrator windup clamp of course)? Who cares if the overload is momentary, the transistors/diodes should handle it fine. The overcurrent fault either shouldn't (don't make it a hard fault, just make it stop the current cycle?), or raise it to a narrower but still safe margin.Tim

author: uer166
author_rank: Super Contributor
timestamp: August 11, 2021, 07:17:13 pm
content: Heh, wait til you see the planar auxiliary flyback. This is actually a solar MPPT for vehicle charging, not related toy 2 previous experiments (one was a 2-phase boost, another was a wonky sync boost inverter). Unfortunately I'm not measuring the output current since I can sample the source current synchronously with the middle of PWM pulse and derive the output with some math.The main issue with doing any sort of average current control is it'll need to be exceedingly fast (probably software running at Fsw actually). And the margins between "everything is fine" and "oh shit inductor is now a short circuit past 12A" are exceedingly small. I'm not complaining too much about the vanilla slope compensation method, I just could extract another ~600W out of it if I didn't have to waste the inductor so much.I think in the future I would change this a continuous current sense (not just the pulse drain current), and try average mode as well as maybe BCM (can't interleave that, ugh). In any case we're pushing fractions of a percent here.Other fun facts:It's 1400x44AWG Litz on each inductor, currently that alone is $60 per unit.Thy are ETD54 cores with 2mm gap total.Main source of heat seems to be the SiC FET.At real operating point of 160V in and 360V out, it's more like 98.6% efficient.The "precharge" is not a relay and resistor, but rather boosting the input to match the output, and then closing the relay, just like on some EVs.

author: uer166
author_rank: Super Contributor
timestamp: August 11, 2021, 07:20:50 pm
content: Here's a pic of it in enclosure and only one phase inductor. The power stages sit under the ETD54 bobbins. As I do interesting experiments I'll be posting results here I suppose to avoid another thread.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 11, 2021, 07:30:28 pm
content: Neat!Heh, wonder how much of the heat is from near fields, from that ball of wire over the inverter.(Probably not very much, but it's amusing to think about the, I'd guess fractional watt delivered in this way, actually being somewhat significant compared to the high overall efficiency.)Tim

author: kreutz
author_rank: Contributor
timestamp: August 11, 2021, 10:35:06 pm
content: Quote from: uer166 on August 11, 2021, 03:06:10 amA few years ago I used a parabolic slope compensation instead of of the usual sawtooth slope compensation, It worked really well in my application (High power Stepper motor drive) and probably solve or attenuate your problem. The idea was to eliminate sub-harmonic audible noise.kreutz

author: jonpaul
author_rank: Super Contributor
timestamp: August 12, 2021, 12:32:49 am
content: Hello this issue was studied and solved years back.Search some of the PESC, IEEE Power Electronics and Nuremberg seminars for analysis of this.The work of Prof LEE at VPI and Dr Richard REDL is especially recommended.Kind Regards,Jon