Is there a better/simpler way to implement this logic? - Page 1
Forum section: electronics / projects

author: HwAoRrDk
author_rank: Super Contributor
timestamp: December 17, 2023, 10:30:33 pm
content: I wanted to implement some control logic for controlling power from an external PSU (just your typical SMPS) to an external load that can handle a couple of possible fault conditions. I decided it was probably simple enough to handle using discrete logic chips, so what I came up with was the attached design. But I would like some feedback because I can't help feeling that there may be a simpler/better/cheaper way of doing this, or perhaps there are some gotchas I've missed.Some notes:- The PSU takes an active-low PS_ON_N signal to turn on, and has a PWR_OK (aka 'power good') open drain output. PS_ON_N and PWR_OK are both internally pulled-up by the PSU with approx. 1k to its 5V standby rail.- I am using a 'smart' current-limiting high-side load switch to switch power output to the load, which is not shown on the schematic. It has an EN enable input, and a FAULT_N active-low open-drain output. FAULT_N also has a 47k pull-up not shown here. The load switch triggers the fault output when it detects a short-circuit or current overload, but is non-latching - i.e. as soon as the fault condition goes away, the fault output toggles back high.- R1 & C2 provide some de-bouncing for on/off switch S1.- FAULT_OUT will probably go to a warning LED or something.- U4 is a D-type flip-flop with reset and positive-edge triggering.The behaviour I'm aiming for is as follows:- When PS_ON_N is active together with PWR_OK, the EN output will go high to enable the load switch.- During this time, if either of PWR_OK or FAULT_N go low, then FAULT_OUT should go high and EN should go low, turning off power to the load.- FAULT_OUT should be latched such that any subsequent toggling of either PWR_OK or FAULT_N will not re-enable power output.- To reset the fault condition, the on/off switch must be turn to off (i.e. PS_ON_N de-asserted).I've simulated this circuit, and I think I've worked out all the minutiae, but I'm not 100% sure about it.- The RC delay from R3 & C3 is critical to capturing PWR_OK failures. If PWR_OK goes low, they ensure that the flip-flop clock rising edge is immediately produced, but the previous PWR_OK high state is momentarily held through the gates producing EN, and thus the D input to the flip-flop (so that its state can be propagated to the Q output for FAULT_OUT).- I think R5 & C4mightnot be necessary. I only included them because I was concerned about having enough hold time on the D input after Q toggles. The 74LVC1G175 datasheet says it needs 0.5ns. But in reality I think the propagation delays of U2.3 and U3.1 might satisfy that. Not sure though. I made the RC values 1k and 4.7n simply because I'm already using those values elsewhere.- I think AHCT and LVC logic levels are the same, if not very similar, right? Not that I think it really matters in this design.- As it's taking inputs only from other logic ICs, U3 should be fine being non-schmitt-trigger, yes?(P.S. Yes, I know a 50-cent microcontroller can do the job - I don't want to use an MCU!)

author: zapta
author_rank: Super Contributor
timestamp: December 18, 2023, 01:55:05 am
content: This could fit nicely into a single SLG46826G SPLD.It has comparators, gates, flip flops, and timing elements. You design by drawing a schematic and and can update the design in-circuit using a standard I2C adapter.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: December 18, 2023, 03:10:52 am
content: Quote from: HwAoRrDk on December 17, 2023, 10:30:33 pmYou could also look at TI's schmitt trigger families : SN74HCS72 SN74HCS74 etcThose allow RC type timing delays on any pins, have have a choice of =\_ and _/= clocks.QuoteModern flipflops should all be capable of connecting Q to D, so any additional gates will have more than enough margin.

author: HwAoRrDk
author_rank: Super Contributor
timestamp: December 18, 2023, 04:02:15 am
content: Quote from: zapta on December 18, 2023, 01:55:05 amHmm, interesting. I had forgotten about these things. Looks like Renesas own them now. I think even perhaps one of the smallest devices like the SLG46110 might do the job, although that one is OTP. Can you just download the design software and play around with logic for a certain device and simulate it without any hardware? If so, I might try it.

author: zapta
author_rank: Super Contributor
timestamp: December 18, 2023, 05:26:10 am
content: Yes, you can design and simulate without any hardware, and the Renesas software is easy to download without complicated license procedue. Here is a blnky example that was designed and simulated without any hardware.https://github.com/zapta/GreenPAKs/tree/main/blinkyYou probably want to start with one of the NVM devices such as SLG46826G. They will allow you go to to prod without having Renesas in the loop, programming OTP's for you. Unless if this is for large quantities and you want to get pre programmed ICs.BTW, there is a recent long thread about those devices that covers a few aspectshttps://www.eevblog.com/forum/fpga/help-finding-a-small-and-low-cost-programable-logic-ic/