LTSpice simulation not completing - Page 1
Forum section: electronics / projects

author: garvind25
author_rank: Regular Contributor
timestamp: June 08, 2025, 01:50:00 am
content: Hi,I am running a LTSpice (v 24.1.7) transient simulation using TLV271 model file. I first ran a sim with a single op amp. The sim ran OK.When I ran the sim on my ckt, the simulation is continuously running for more than half an hour and not ending. I tried by relaxing the gmin to half the value but no joy. I even changed the integration method from trapezoidal to modified trap. my ckt has three op amps, few resistors and few capacitors. My PhD guide has asked me not to share the ckt anywhere. Hence cannot post it.The status of the progress bar is attached as image.My query is: how long can TLV271 simulations typically take? What can I do to quicken the speed of simulation (I am using a Corei3 processor with 8GB RAM). Do you think its worthwhile to try integrating another simulator with LTSpice (such as NGSpice) and try?Looking forward to your comment pls.Thanks in advance,Arvind Gupta.

author: moffy
author_rank: Super Contributor
timestamp: June 08, 2025, 03:07:22 am
content: Without sharing the simulation we are literally in the dark as to what it could possibly be.

author: Ian.M
author_rank: Super Contributor
timestamp: June 08, 2025, 03:24:29 am
content: The status line indicates its stalled trying to find the initial operating point. However as Moffy has pointed out, without the sim files, we have no way of knowing why.

author: Simmed
author_rank: Frequent Contributor
timestamp: June 08, 2025, 04:16:23 am
content: mmm bummer ?first, i am not LTspice expertsecret sauce simulation that cannot be shownmy suggestion is to read up all the possible startup condition parametersbut this will take hoursso a quick wayi would suggest replace TLVxxx with LT6013 or LT1012A and try again(normally i find that a non-LT opamp have certain limits)good luck

author: iMo
author_rank: Super Contributor
timestamp: June 08, 2025, 06:36:29 am
content: There is the magic button named "ESCAPE".While your sim loops looking for a better result just press once or twice the ESCAPE and it will continue.It helps most of the time.BTW., while looking in the bottom status line it writes there something like "..or press .."

author: mikerj
author_rank: Super Contributor
timestamp: June 08, 2025, 10:41:37 am
content: I've had several TI Spice models cause problems with convergence in LTSpice, and spent far too long trying to resolve them. I've had a TI op-amp model that just plain didn't work, but the model for the quad version was different and worked just fine.

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 08, 2025, 12:07:31 pm
content: There are a lot of potential causes for the infamous "stepping source" hangup. Here are some suggestions:1. Add "startup" to the .tran directive (can do this in the GUI by opening the Configure Analysis window and checking "Start external DC supply voltages at 0V"). This almost always gets past the issue.2. Hit escape while it's in this state to skip this step and move on. You can make this automatic by adding ".options srcsteps=0" to the simulation (can do this in the GUI by opening the Configure Analysis window and checking "Skip initial operating point solution")However, in my experience seeing this message usually indicates a real issue with the circuit, and the above methods basically sidestep it rather than resolving it. Also, in the case where you need the simulation to start with a specific operating point, these methods won't work. If you actually want to resolve this issue:3. Start replacing complex subcircuits and macromodels (like the TLV271) with simpler models, like a universal opamp, or something made of behavioral sources.4. Adjust the initial conditions of signal sources. For example, if you're using a voltage source to provide a clock signal, try changing the initial state of the clock from 0 to 1.5. If all else fails, break the circuit into smaller chunks to try and find which specific part is causing the issue.