Quartus II 18.1 light problem getting functional simulation to work. - Page 1
Forum section: electronics / general

author: garthenar
author_rank: Newbie
timestamp: February 28, 2020, 08:55:15 pm
content: The Code I get is;Error: (vlog-7) Failed to open design unit file "Waveform.vwf.vt" in read mode.I am not able to see the answer in the quick start guide.https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_gs_msa_qii.pdfThe file is not named Waveform, it's named Lab4 in both the source file and testbenchFirst, I would like to state that before coming here I've been reading through technical guides, manuals and the Intel forums looking for an answer. Now I'm resorting to posting on this forum.I'm trying to run a functional system but it's failing and from what I can tell it's trying to open a different file thant the one I'm having it create. I cant figure out where I can change whatever setting is causing this.I may have to create a new project and copy my .bdf files into it as I have had that work before. However, I am genuinely interested in this software even beyond the scope of my class and would like to learn how to fix this problem in the future.Also, This is my first project where I've created a .bsf file to create a component in my top level design (A full adder). I don't know if I messed that up in some way but it's the only difference I know of between this and previous projects.EdditI have tested this circuits on my DEO-CV CycloneV and it works fine as a 8bit 2's complement binary adder/subtractor.Testbench Generation Comand (pathing)quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab4 -c Lab4 --vector_source="C:/Users/xgp15a2/Documents/ECE 102 Labs/Lab4/Lab4.vwf" --testbench_file="C:/Users/xgp15a2/Documents/ECE 102 Labs/Lab4/simulation/qsim/Lab4.vwf.vt"I have fixed pathing in previous projects and have checked to make sure the pathing is correct.Netlist Generation Command (all i know is this generates a Netlist, I don't know what the Netlist is)quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/xgp15a2/Documents/ECE 102 Labs/Lab4/simulation/qsim/" Lab4 -c Lab4Modelsim Scriptonerror {exit -code 1}vlib workvlog -work work Lab4.vovlog -work work Waveform.vwf.vtvsim -novopt -c -t 1ps -L cyclonev_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab4_vlg_vec_tstvcd file -direction Lab4.msim.vcdvcd add -internal Lab4_vlg_vec_tst/*vcd add -internal Lab4_vlg_vec_tst/i1/*proc simTimestamp {} {echo "Simulation time: $::now ps"if { [string equal running ] } {after 2500 simTimestamp}}after 2500 simTimestamprun -allquit -fOn a lighter note it's my first post to the forumI'm not the least surprised that there are emojis.

author: garthenar
author_rank: Newbie
timestamp: February 28, 2020, 10:23:26 pm
content: the situation is evolving and I've posted updates onhttps://www.physicsforums.com/threads/quartus-ii-18-1-light-problem-getting-functional-simulation-to-work.984901/I'll put the updates here in a little while one I've had some more time at the problem.

author: fourtytwo42
author_rank: Super Contributor
timestamp: March 01, 2020, 09:19:16 am
content: Well if it helps to get some moral support you are certainly not alone, I use the stuff (Quartus) grudgingly and most days I fight itIt is appallingly documented, way over complicated and stuffed full of obscure scripts. Trying to find out why something doesn't work can take days if you don't give up and find a workaround (like abandoning trying to do whatever it is). Unfortunately this seems to have become common in the FPGA EDA tool industry and you need as much of a team to work the tool as you need to develop the product, ok in a large organization but a pita for those who work aloneBest way is usually duckduck whatever error you have and hope someone has posted a fix/explanation somewhere........Don't wait around for anything sensible from the Intel forum, it's rare!One thing that turned up doing a shortened search washttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Error-vcom-7-Failed-to-open-design-unit-file-quot-quot-in-read/td-p/705649there are many others, I wish you luck!I also note you have posted this on numerous forums!