32F417 security question (disabling SWD etc) - Page 1
Forum section: electronics / general

author: peter-h
author_rank: Super Contributor
timestamp: August 24, 2022, 03:39:17 pm
content: I've been reading the various ST appnotes on this, but I can't find clear answers on whether one can achieve this1) Disable SWD, so the only way to reload firmware would be with some form of firmware loader (which I have done, via USB MSC FatFS or file upload via HTTP server) and there one can put a secure hash etc on the file being uploaded2) Prevent bottom 32k of FLASH being read out3) The secure status beingreversibleso if a customer returns a unit it doesn't have to go in the rubbish bin (with various heavy political implications if the customer is a big company with lots of power, and ready to withold payments, etc). ST deny warranty on Level 2 fused devices, which is completely understandable, but they are bigger than anybody else4) A RAM based boot loader (copied from bottom 32k block to the RAM, for rewriting the whole FLASH) needs to work even when above security features have been set.AFAICS onlyLevel 2security is not reversible by uploading suitably written software.Item 2) is a bit of an odd one because if you disable SWD, it cannot be read with a debugger anyway, but it needs to be accessible by code executing on the CPU, including the RAM based boot loader. So maybe that bit is pointless.I've also read that all the time BOOT0/BOOT1 are accessible, somebody can use them to activate ST's boot loader and inject code via e.g. a UART. The method to disable these, by remapping with AF, can apparently be easily bypassed with a carefully timed reset.I think disabling SWD will be the biggest gain. But it needs to be software-reversible.

author: wek
author_rank: Frequent Contributor
timestamp: August 24, 2022, 04:13:29 pm
content: We can stop here:> 1) Disable SWDOnly through setting Level 2 lock.But let's discuss also other points.> 2) Prevent bottom 32k of FLASH being read outNot in 'F405/407/415/417. In newer STM32 - including 'F42x/43x - maybe, keyword is PCROP, read related chapters of RM.> 3) The secure status being reversibleThat's only Level 1, in 'F417.> 4) A RAM based boot loaderThat should work with Level 1.You are surely aware of existing "unlocking services" and the publicly known vulnerabilities.JW

author: peter-h
author_rank: Super Contributor
timestamp: August 24, 2022, 04:47:48 pm
content: Thank youIf disabling SWD needs Level 2, that kills this whole idea, because I won't ship out such a product unless it contains absolutely finished and debugged code and the customer has signed off on the functionality.My board has even got the 10-pin ARM SWD/JTAG connector on it, clearly markedI could use the 437 instead of 417 if that helped.Yes I've read various things, and there are many attacks e.g. measuring the supply current which have been used to crack even dedicated "secure" smartcard chips. These attacks go back decades, as do the countermeasures like "encrypting" the supply current! I would just want to p1ss off somebody who thinks it is a 5 minute job

author: wek
author_rank: Frequent Contributor
timestamp: August 24, 2022, 05:42:13 pm
content: QuoteThat might help point 2) but not 1).JW

author: darkspr1te
author_rank: Frequent Contributor
timestamp: August 24, 2022, 06:02:50 pm
content: Quote from: peter-h on August 24, 2022, 04:47:48 pmYou can disable swd in boot code if you patch the load to ram routine in most dev env's. but that still falls to the connect on reset and irq dump routine.you can hinder realtime debugging with calls to the pins for the swd system so make it a patch nightmare , place secure code around irq 13 and such , use rtc for crc storage like factory boot, real time, tamper and many more tricks so your code does lock up the test the heck out of it.You can also use irq's a lot more, the jump is just another cash/cost/day delay for them but it not much extra code.depending on the stm clone too have larger storage in areas like rtc which is where sram code is hidden so when a device is opened it mis-behaves, something i'll write up at some pointdarkspr1te

author: peter-h
author_rank: Super Contributor
timestamp: August 25, 2022, 06:27:10 am
content: You mean setting up an interrupt to do stuff with the SWD pins? But surely the debugger resets the CPU and stops all that?In the days of dongles, software used timers to detect single stepping, to make it harder to discover where the dongle code is. But on the arm32 you can freeze timers (and the watchdog) while stepping.