FPGA open drain output, can pullup to higher voltage? - Page 1
Forum section: electronics / projects

author: c64
author_rank: Frequent Contributor
timestamp: September 27, 2020, 07:54:26 am
content: For normal chips, it's safe to connect open drain/collector output to the voltage higher than Vcc (within reasonable limits of course), because it's just a transistor with drain/collector not connected to anything.What about FPGA? Is it safe to do the same? Even if pin is configured as open drain, there are still other elements inside FPGA.FPGA in question is Cyclone 2, if it matters

author: Yansi
author_rank: Super Contributor
timestamp: September 27, 2020, 08:19:18 am
content: You are unfortunately very wrong.It is NOT and NEVER safe to connect higher voltage than VDD to ANY IO pin of an IC (whatever it might be), expcet when CLEARLY stated by the manufacturer such can be done.So, you can NOT generalize with "normal chips".That you are not using the high side output transistor does not mean the substrate diode magically disappeared.Only special and purpose designed IOs explicitly stated by the manufacturer can be used as you intend.There is a very small subset of digital logic ICs, that are designed with this in mind, such as level translation logic chips:https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf(page 7), or special purpose built GPIOs on some MCUs or some other interfacechips, that are expected to work in between different voltage domains.(As far as I know, there are none FPGA familys with such feature)

author: Siwastaja
author_rank: Super Contributor
timestamp: September 27, 2020, 08:53:01 am
content: Yansi's right, your generalization is wrong and you have succeeded by luck. In this regard, FPGA is like any "normal" IC.There's no other way than to look at the datasheets carefully, case-by-case. Unfortunately, sometimes open drain outputs are undermarketed so that they could pull up to a higher voltage but this isn't mentioned in the datasheet; then if you want to save the cost of external transistor, your option is to test and operate the part outside the specs. I guess this is what you have been mostly doing.Some ICs have some pins with their own region where the substrate diodes conduct to, there can be a further avalanche diode integrated for ESD protection, for example so that this part of chip can withstand up to, say, 5.5V, while Vcc=3.6V max. But this is something that must be explicitly specified. Some FPGAs may have such 5V tolerant pins, I don't know.

author: chris_leyson
author_rank: Super Contributor
timestamp: September 27, 2020, 10:58:06 am
content: ^^^ What Yansi said together with all of the other posts. You might also want to check power sequencing at start up and shut down and especially brownouts.I know it's going off topic but I've recently come across a microcontroller that uses an open drain mosfet connected to it's reset pin to discharge the reset capacitor. The "Auto Reset" feature kicks in at VDD = 1.9V typically and then starts to discharge the reset cap which has already been discharged by an Si diode connected to VDD. A little while later the core shuts down at VDD = 1.5V and at more or less the same time the reset cap, 1uF, starts to charge back up and occasionally an I/O pin which should be at 0V generates a 1V drive pulse that causes some system mayhem. It seems the N channel mosfet is still being driven but its transconductance has dropped to next to nothing, you can tell by looking at the reset cap voltage. In hindsight perhaps the "Auto Reset" doesn't perform any sort of expected reset at all and is just there to discharge the reset cap. Will have to read thePanasonicNuvoton MN101EF50D data sheet again.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 27, 2020, 12:03:09 pm
content: Well, depends what "normal" is. Ye olde SN7406 has 30V open collector outputs, obviously independent of supply (no clamp diodes to VCC). The next closest CMOS equivalent 74HC05, does have ESD diodes to VCC (as evidenced by the output voltage max being relative to Vcc, seehttps://assets.nexperia.com/documents/data-sheet/74HC05.pdf).Some families have 5V tolerance built in. 74LVC for example. They do not use clamp diodes to VCC, so input voltages (and output, when applicable) are freely independent. They did make a version of the '06 hex inverter:https://assets.nexperia.com/documents/data-sheet/74LVC06A.pdfOf course not with 30V outputs, but a respectable 6.5V maximum rating given the low-ns speed of the family.Some MCUs have 5V-tolerant pins (e.g. much of the STM32 family, AFAIK), which can be used in this way -- the datasheet usually warns of not driving the pins above VCC in output-high state, but that's fine as the pin would be used as '0' or 'Z'.More devices have clamp diodes to VCC, so it's somewhat unlikely that you would find 5V tolerance to be "normal". But as you can see, there are entire families of devices where it is normal, so it could happen, especially given limited experience.I don't see the need to jump on this aggressively... just giving typical examples is enough.Tim

author: Someone
author_rank: Super Contributor
timestamp: September 28, 2020, 02:30:45 am
content: Step 1: check the "Absolute Maximum Ratings" so you know the absolute limitsStep 2: decide which mode the pin is configured forStep 3: check the IBIS sweeps for an example IV curve in that modeThen its over to the specific circuit and characteristics of the other devices.

author: c64
author_rank: Frequent Contributor
timestamp: September 28, 2020, 06:57:24 am
content: Guys you are all right. I don't know where I got this idea fromMaybe I used 5v tolerant chips before but forgot.So, basically my best options are (to translate 3.3v output from FPGA to 5v open-drain):a. Use transistor (N-ch FET or BJT with resistor) on each outputb. Use something like 74LVC06 (thanks T3sl4co1l), powering it from 3.3vIs it right?

author: c64
author_rank: Frequent Contributor
timestamp: September 28, 2020, 07:01:25 am
content: Quote from: Yansi on September 27, 2020, 08:19:18 amYou mean clamping diode? Substrate diode would not conduct if output pulled high

author: Zero999
author_rank: Super Contributor
timestamp: September 28, 2020, 08:08:13 am
content: Quote from: c64 on September 28, 2020, 06:57:24 amYes, those are your options, although if all you need to do is translate 3.3V to 5V and don't need open drain, the 74HCT04 (hex but also available in single, 74HCT1G14, dual and tripple) will do. You could use a MOSFET in common base mode: Vcc to gate and output pin to gate. Obviously it needs to be a logic level MOSFET.

author: Yansi
author_rank: Super Contributor
timestamp: September 28, 2020, 09:20:07 am
content: Using opendrain stuff for high speed signalling is a bad idea anway.Example:For single direction translation of 3 to 5V, HCT gates may be used.For single direction translation of 5V to 3V, some LVC gates may be used.But most commonly, specialized translator ICs are used in complex systems with a lot of parallel data busses (such as ISA backplanes and stuff), such as 74LVC16T245 and a like. But beware of the tPD (propagation delay) of that IC and be prepared you will need to control the direction pin.There are also specialized bidirectional translation ICs without a direction pin, but these are getting expensive and are typically quite slow, so can't be used for anything but low speed buses (<10MHz).The last option, when you need high speed and meet tight timing is to cleverly use a bus switch IC. This is a hack I hate to see and don't like, but it seems it works fine and lastly there is no way around it, if you for example want to interface a 3V FPGA with a 5V PCI bus. (Hell that PCI standard is in some waysstupid...)This is a bit of both hackery and clever solution at the same time - you don't need direction switching, it is very cheap to implement and the propagation delay is very small. VERY small.https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an330.pdf