hybridfree/eevblog-posts huggingface dataset:
Disappearing Tracks - Page 1
Forum section: electronics / general

author: dlmmartins
author_rank: Newbie
timestamp: January 03, 2017, 07:17:54 pm
content: Good afternoon Sirs,I am finalizing a PCI, and would like to do a "finishing" between the tracks and the tracks.Similar to the attached photo.What I would like to do: Add two semi-arcs on each side of the trail.It turns out that when I put a side, OK. When I add the other side, it deletes the previous one.I have already disabled the "Automatically Remove Loops" function in the "Interactive Routing Options".I put a link from a Youtube video to exemplify what is happening.https://youtu.be/taDI4bitlVkKind regards,

author: langwadt
author_rank: Super Contributor
timestamp: January 03, 2017, 07:37:44 pm
content: I don't use altium but doesn't it have an option to turn on "teardrops"

author: DerekG
author_rank: Frequent Contributor
timestamp: January 03, 2017, 11:54:25 pm
content: Quote from: dlmmartins on January 03, 2017, 07:17:54 pmAltium is doing this as there is already a connecting track in the circuit.Turning on the teardrop function (as suggested by langwadt above) is the best way to do it (you can adjust the parameters of the teardrops to what you want).But if you really want to do it manually, left click on the curved track to select it, then right click on the highlighted track & select "Properties" then tick the "Locked" dialog box.

author: kiran_shrestha
author_rank: Regular Contributor
timestamp: January 04, 2017, 12:46:54 am
content: If you want the easy way .. as everybody says its use Altium Teardrop option... from Altium 2015 I think Teardrop have much more option and more powerful. If you really want hardware take your routing tool and hit tab and uncheck remove loops option and there you have it....

author: dlmmartins
author_rank: Newbie
timestamp: January 05, 2017, 04:56:08 pm
content: Guys,This is what I need. I did not know about this tool. I saw in the PCBs and thought it was manual. I did it through the tool, and it stayed the way I would.Thank you again for your help.
Multichannel design NetClass - Page 1
Forum section: electronics / general

author: aleks223
author_rank: Newbie
timestamp: December 12, 2016, 02:19:05 pm
content: I'm wondering how to set different NetClass for each channel of a Multichannel design, where REPEAT(..) is used to create diplicate sheets. The idea is then to set different rules for nets within the same NetClass and between nets of different NetClass as they are at different potentials.

author: technotronix
author_rank: Regular Contributor
timestamp: December 30, 2016, 09:59:36 am
content: I like the idea but don’t know much about implementation. Can you give some more about multichannel design netclass?
General Advice PCB, Planes - Page 1
Forum section: electronics / general

author: goldfinger
author_rank: Regular Contributor
timestamp: December 08, 2016, 08:24:00 am
content: Hi Guys,I'm designing my first pcb for manufacturing and I'm hoping I can get some advice on people's general thoughts on gnd planes. I'm working on a two layer board with most of gnd traces running on bottom with exception of a few traces.My question is what should be a standard clearance between the pad and ground pour for through holes that aren't connected to the gnd plane? Most of the tH are between 0.8-1.1mm with pads between 1.5-2.5mm, my main concern is soldering and ensuring that I don't short to the ground plane. Also, for TH for screws mounting (I'm thinking m3 screws) what sort of clearance around should I aim for?Is there any general guidelines at all?Any advice would be appreciated, I'm using circuit maker.Thanks guys!

author: DerekG
author_rank: Frequent Contributor
timestamp: December 09, 2016, 03:16:32 am
content: Quote from: goldfinger on December 08, 2016, 08:24:00 amIt really depends on how tightly packed your board is. If you have plenty of room then 30mil (30 thousandths of an inch) or 35mil is a good clearance.Quote3.2mm would give you a clearance of 0.1mm around the screw. If you want it a little more sloppy you could go to 3.3mm.Make sure you don't plate through the mounting holes if these boards are going to be wave soldered. If you do, the plating will suck the solder through the holes ending up with spillage on the top side of the board.I hope this helps.

author: DTJ
author_rank: Super Contributor
timestamp: December 09, 2016, 04:16:07 am
content: For pad to tracks I usually use 10mil or even 8mil.For mounting screws, say M3, I place a pad with a 3.5mm hole and make the pad diameter so that its one or two mm bigger in diameter than the screw head or nut driver socket that will be used to fasten the board down. Putting a silk screen circle around the mounting holes can help as a placement guideline when pushing parts around and routing.

author: goldfinger
author_rank: Regular Contributor
timestamp: December 13, 2016, 10:31:18 am
content: Quote from: DerekG on December 09, 2016, 03:16:32 amThanks for feedback appreciated

author: goldfinger
author_rank: Regular Contributor
timestamp: December 13, 2016, 10:33:05 am
content: Quote from: DTJ on December 09, 2016, 04:16:07 amThanks for feedback!!! I ended up with a 4.2mm keep out around the m3

author: technotronix
author_rank: Regular Contributor
timestamp: December 30, 2016, 09:52:58 am
content: 3.2mm would be better to get perfect clearance.
Polygon pour - sharp corners -> rounded corners - Page 1
Forum section: electronics / general

author: Mandragora
author_rank: Contributor
timestamp: December 27, 2016, 05:46:14 pm
content: Hello Altium users, I am using AD 10.I am designing HV PCB. Circuit is simple, it is half bridge made on SiC N mosfets switching 800V DC, PCB works as BUS BAR on internal layers.To maximize cooper area from HB output to Wurth press fit terminal I've made rectangular polygon.Polygon correctly keeps clearance from other HV points but in a result creates sharp corners (marked with black circles on the attachment). Such corners are very bad for HV aplication. Is there any solution to add a rule or something where corners have to be smoothed to at least 2mm radius? I haven't fount any options to set it.Did any one of You had similar problem?Regards,Mandragora

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 27, 2016, 08:27:27 pm
content: Well, the points indicated at the bottom of the figure aren't contributing much if any conductance, so you can simply trim the polygon in that area.There isn't a general "round corners" function. The "remove narrow necks" option has some effect, but makes a straight line cut (and not always making a mitered corner). If you must have rounded shapes, you're probably best off adding polygon cutouts with rounded perimeters (arc segments can be drawn by grabbing a segment midpoint and CTRL+SPACE to cycle segment type). Don't forget to update their positions and angles after moving things around!Tim

author: Someone
author_rank: Super Contributor
timestamp: December 27, 2016, 10:13:34 pm
content: Quote from: T3sl4co1l on December 27, 2016, 08:27:27 pmIts the field concentration from sharp points that is the problem, clearance/creepage rules are generally assuming parallel or rounded conductors facing each other. For something that small where the poly fill isn't doing much you can route some thick traces by hand and use the rounded edge pours for the less important sections.
Altium 17 Backdrilling not working on some vias - Page 1
Forum section: electronics / general

author: dmg
author_rank: Regular Contributor
timestamp: January 26, 2017, 12:21:10 pm
content: Hi,I'm working on a design that requires backdrilled vias on altium 2017.I was trying to use the new feature to ease the backdrilling definition and report I've defined the rule to target them and the corresponding backdrilling pair according to altium's documentation and it does automatically recognize most of the targeted backdrilled vias, but not all of them. Some of the vias don't get recognized as requiring backdrill and I don't know why, as they have the exact same geometry, net class and starting-ending layer as the other vias that do get backdrilled. I've even substituted some of these vias for copypasta'd vias from others that get recognized as backdrilled, but to no avail.Even on vias on the very same net that are very close to each other, one gets recognized and the other doesn't. Exact same geometry and layer stack on both.Anyone got any idea on what might be the issue?
Protel99se all of a sudden won't recognize .ddb when adding libraries. - Page 1
Forum section: electronics / general

author: BrianHG
author_rank: Super Contributor
timestamp: December 25, 2016, 11:02:53 pm
content: Well, ok, this forum section is as close as it gets to Protel...I've just started a new project in Protel99se, it's been a year since I started a new one. After creating a new project, then schematic, I tried to add a schematic library. When trying to add my default library, Protel99se said 'The file type is not recognized.' (see attached photo)Now, I can open the .ddb as a project and go in and edit any and all of the components so I know the .ddb is good and valid. In fact, when trying to add a blank newly created .ddb I just generated today as a test, it also fails to recognize the file type. Did Windows update do something within the past year to make my Protel99se useless? On both of my Windows 7 professional systems.Is there a way to un-do this damage? I know Protel uses a component within windows to create and manage the compact .ddb files.
Polygon plan doesn't appear in the gerber files - Page 1
Forum section: electronics / general

author: alex934
author_rank: Contributor
timestamp: September 16, 2016, 02:27:25 pm
content: Hi everyone,I have a board with components on the top layer and electrodes on the bottom. On the bottom there are 20 electrodes and one polygone plan which is intricated between all the electrodes to fill the board.See in attachment the two first images.So in my project everything looks good.I generated gerber files (Files->FabricationOutput->GerberFiles) I choose all the layer (to be sure everything is in it) and I generate the .CAM first (see cam.png in attachment)In the Cam, my bottom layer looks okay, I can see my polygone plane.But after that when I do Export->Gerber , If I look at the .gbl (which is the gerber bottom layer), It seems that the polygon plan is not there (see gerber.png in attachment)Did you have the same issue?Thank you very much

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 16, 2016, 06:19:56 pm
content: Why would you export gerber from CAM? It's already in gerber!Export from CAM has known issues, besides.Tim

author: kiran_shrestha
author_rank: Regular Contributor
timestamp: December 20, 2016, 06:09:36 am
content: I think you are confused..... the first picture shows your poly on bottom layer.. and ur gerber output shows same thing in top layer(red).

author: julianhigginson
author_rank: Frequent Contributor
timestamp: December 20, 2016, 10:01:41 am
content: As already mentioned - once you have a camtastic running, (as shown in your third screenshot - polygonPlan.png) that's the gerber viewer - so you've already got the gerbers somewhere! and those gerbers have the electrodes plus the groundplane, just like in the screenshot from the PCB editor shown above it.No need to regenerate new gerbers while viewing your gerbers in the gerber viewer.The weird thing is what's that last screenshot meant to be? looks like a single layer gerber view where now you have the electrodes on another layer?? what did you do to get that?? showing at least the layers panel as well as the editor panel would be useful here!Anyway - What happens if you use an outjob file to generate the gerbers?The outjob file is an awesome tool for keeping your project outputs consistent, and recommended over add-hoc artefact generation available any other way.I prefer to put the gerbers straight to disk when writing gerbers, then load them up separately to have a look.
How to assign Pin to a solid region - Page 1
Forum section: electronics / general

author: alex934
author_rank: Contributor
timestamp: December 14, 2016, 05:46:00 pm
content: Hi everyone,I need to design an electrode so I did my footprint using solid region. I would like to assign to my solid region two pins, my problem is when I use it in my design it's like there is a problem.I tryed to do >>design >> netlist >> update free primitives from component pads but it doesn't change anythingThank you

author: free_electron
author_rank: Super Contributor
timestamp: December 14, 2016, 06:09:39 pm
content: make sure your region COMPLETELY overlaps your pins. make those pins like 1mm by 1mm.the region essntially neds to cross the hotspot of the pad. if not you get this behavior. a connection is only valid if it crosses the hotspot.in 17 they have new rule and a glosser to fix such problems automatically

author: alex934
author_rank: Contributor
timestamp: December 14, 2016, 06:37:53 pm
content: Hum it's still the same the pin is completly in the solid region.Maybe it's because I superposed several solid region?

author: tautech
author_rank: Super Contributor
timestamp: December 14, 2016, 07:11:46 pm
content: Have you assigned a Net name to the pins/pads ?Should be the same as the same of the Net/s you are trying to connect to.

author: alex934
author_rank: Contributor
timestamp: December 14, 2016, 07:20:09 pm
content: Well when I connect something in schematic, the problem disappears...But I don't really understand

author: free_electron
author_rank: Super Contributor
timestamp: December 15, 2016, 06:04:10 pm
content: of course. if nothing is connected to it the no net gets assigned and you get a short circuit violation ! that is normal behaviour

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 15, 2016, 06:33:08 pm
content: To do the same thing, you can add wires to the pins, and put net labels on them. You get "single pin nets", which are disabled by default under Project Options.The DRC eval for "No Net" copper is kind of weird, but it has its purpose I suppose.Remember too, you can always use the fab outputs, whether the DRC is there or not. If the copper is correct, nothing else matters.Tim
Drawing Guard rings in Schematic - Page 1
Forum section: electronics / general

author: nns
author_rank: Newbie
timestamp: December 07, 2016, 02:58:39 pm
content: Does anyone have a "nice" way of drawing guard rings in Altium schematic capture? I like my schematics to clearly convey what's going on, so drawing a guard ring like:Is attractive to me.I can use line segments (and set them to dashed), or I can use a blanket directive (basically a dashed polygon). The blanket directive has the added benefit of being able to put the guarded nets into a class (helpful during PCB layout), but has the drawback that the dashed line looks a little crappier than the line segments. With both of them, I can't clearly show the guard net "attached" to the blanket directive (the wire just ends touching the directive/line, instead of with a node marker like in the drawing above).For now, it works. I'm just wondering what other people do and if there is a better/more standard way to show this in Altium.

author: Miles Teg
author_rank: Regular Contributor
timestamp: December 07, 2016, 04:57:14 pm
content: Hello,I should have bring another net and using the netcolor on it.

author: ajb
author_rank: Super Contributor
timestamp: December 07, 2016, 06:00:05 pm
content: You can change the visual style of the blanket to suit, and you can place a manual junction to show that the blanket outline is 'connected' to the guard net. Does that get you what you want?

author: nns
author_rank: Newbie
timestamp: December 08, 2016, 12:47:53 pm
content: Quote from: ajb on December 07, 2016, 06:00:05 pmSomehow I managed to totally miss the manual junction object for 3 years. Wow. Thanks for pointing out my (obvious) oversight!I think that solution will result in the best look of the final schematic. Thanks!Quote from: Miles Teg on December 07, 2016, 04:57:14 pmThat's a good idea, however for my needs, I think I prefer a dashed line solution. I believe it's more obvious when printed black and white.

author: Miles Teg
author_rank: Regular Contributor
timestamp: December 08, 2016, 04:56:54 pm
content: Quote from: nns on December 08, 2016, 12:47:53 pmI understand, but still believe getting the right color to have a easily indentified different grey from the black nets in grey scale printed schematic could be usable.Hope you will find also the optimal solution with dashed lines.
Altium Designer 17 Serious ERC Bug - Page 1
Forum section: electronics / general

author: EEVblog
author_rank: Unknown
timestamp: December 07, 2016, 05:29:44 am
content: UPDATE:Setting the .OutJob source to "Project" fixes that.So clearly it's a problem with invoking the compile for just the schematic sheet, either in OutJOb or Right Click Compiling

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 07, 2016, 02:46:26 pm
content: I've seen inconsistent behavior before, between Compile Sheet and Compile Project.My example is, if you have component names interfering, normally on compile it generates an error and highlights the offending components; but after renaming them and doing a sheet compile, the highlights don't go away.That might be sensible because it's only the one sheet, but you'd think maybe there's project information floating around for that sheet compile to figure out.Go figure, the best way is to do it every way possible (in these cases, compile sheet, project and ERC), and see what the worst conclusions are, out of all of them.Personally, I hate inconsistency worse than simply ill-designed procedures. The latter you simply add more steps to run around the bug. The former, each step that's okay ceases to remind you of possible problems lurking beneath, and you can forget to complete the full sequence of steps, very easily.Tim

author: tszaboo
author_rank: Super Contributor
timestamp: December 07, 2016, 03:36:16 pm
content: The outjob has a different "connection matrix" than the project. You need to configure the outjob , right click. Also, if you compile only a sheet (not project), it cannot check a bunch of stuff, like harnesses, which are described in a different file. I guess some more info is not stored where it should be. I think it is working as intended.
Rip-up a power plane - Page 1
Forum section: electronics / general

author: hansibull
author_rank: Regular Contributor
timestamp: November 28, 2016, 10:02:48 am
content: Hi!I'm creating a PCB where I created a ground plane with rounded edges to fit the board. Problem is, the plane is covering the while board, and traces on the other layers are hard to see even if the transparent mode is selected.Are there any way to hide or rip-up the polygon like you can in Eagle, without deleting it?

author: BradC
author_rank: Super Contributor
timestamp: November 28, 2016, 11:48:14 am
content: Shelve it.

author: hansibull
author_rank: Regular Contributor
timestamp: November 28, 2016, 03:21:45 pm
content: Well, that was hidden deep in there! Thanks

author: julianhigginson
author_rank: Frequent Contributor
timestamp: November 28, 2016, 11:12:12 pm
content: If this is a plane on its own layer (ie not a broken up polygon pour over a tracking layer) You can also use plane layers. defined in PCB stackup.They are drawn negative, so show up nice and see-through when they're holding a single whole board net. (you can also easily cut through those with drawn lines if you want, and assign different nets to different unconnected areas)You can also use the view setup to make polygon pours shown as draft or invisible.right click on PCB: options > Show/hideOr just hit Ctrl+dDraft View mostly turns the polygon display off, but leaves a basic tint in place, and a few edge details here and there so you know it's still there. Hidden View makes it completely invisible, so isn't recommended if you tend to forget what you've done or you share designs with others. This feature, not used carefully, can really drive someone mad. Especially someone not familiar with the design or with Altium.
Push routing not working in Altium - Page 1
Forum section: electronics / general

author: ECEdesign
author_rank: Regular Contributor
timestamp: November 21, 2016, 02:14:17 am
content: I'm pretty frustrated, I've gone through the settings in Altium so many times and still can't get push routing (or any interactive routing feature) to work. I will have the interactive mode to push or hug and push and you can just go right over other tracks like it is on ignore all. If I pick up a component it will push the other components but not when doing traces.Any ideas?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 21, 2016, 09:30:21 am
content: While routing, hit SHIFT+R. (Press ~ for other options.)Tim

author: ECEdesign
author_rank: Regular Contributor
timestamp: November 21, 2016, 03:17:10 pm
content: Holding shift and R doesn't do anything except for change the mode. The walkaround objects seems to work but push doesn't push anything.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 21, 2016, 03:58:00 pm
content: The traces are all on a copper layer, have a net assigned, and aren't locked, right?Tim

author: ECEdesign
author_rank: Regular Contributor
timestamp: November 21, 2016, 04:21:00 pm
content: Opened a service request with Altium, they responded within 4 minutes!! I had my clearance rule set to differential pair only instead of different nets only. Now it works like a charm!
[SOLVED] Custom components library - import schematics and footprints? - Page 1
Forum section: electronics / general

author: hansibull
author_rank: Regular Contributor
timestamp: November 21, 2016, 11:17:55 am
content: Hi!I'm in the process of learning Altium Designer, and I want to create a custom library where I store all the components I use the most. A lot of these components allready exist in the official 3rd party libraries (such as microcontrollers, passives etc.), and the all got great schematic symbols and footprints.I don't want to re-invent the wheel again, so I hoped I was able to import the an allready existing part schematic symbol and the footprint. I'm able to import the footprint, but cannor figure out how to import the existing schematic symbol. All tutorials on youtube only shows you how to create your own. Is there any way to import e.g Atmels ATmega324PA-AU schematic symbol into my custom library?

author: julianhigginson
author_rank: Frequent Contributor
timestamp: November 21, 2016, 11:27:37 am
content: whats the original library format you have?I don't normally copy library parts, but if you can open the source library for editing and open the destination library for editing then you should be able to select the source component in the SCH library panel, then go to menu: tools>Copy Component, and then select your destination library for it to get copied to... (if you have your source library in intlib format you may have to split it first?)another way is just place all the parts into your design from the original source library, then when you've done the design export project libraries from the design.. this will give you a schlib and a pcblib with everything that was used... and from there you can copy to an official "my used parts" lib if you want.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 21, 2016, 12:27:15 pm
content: You can open the library file directly, and copy symbols out of it.Or you can place them on your schematics or PCB, and generate a library from that.(There are no lib-merge tools built in, unfortunately, so you can't dump a sch's components into an existing library, for example. There might be a script that does something handy like that.)The built-in libraries are kind of weird, mostly having badly proportioned shapes, ugly labels, and non-compliant footprints (with minimal mechanical features, e.g. courtyard, 3D model). It's a good plan to edit them anyway.Tim

author: hansibull
author_rank: Regular Contributor
timestamp: November 21, 2016, 01:19:52 pm
content: Thanks you so much guys!It's a bit clumsy, indeed, but at least I'm now able to (slowly) create my own components llibrary without needing to redraw every component!
Altium unrouted net on NPTH pad to copper pour - Page 1
Forum section: electronics / general

author: robotly
author_rank: Newbie
timestamp: November 23, 2016, 06:50:18 am
content: In Altium, I have a non-plated through hole with a pad. The pad is assigned to net GND. I have a polygon pour defined as GND. When I pour the polygon, the pad has thermal connections to the pour, as expected, but when I run the DRC I get an "unrouted net" error associated with that pad.I wanted the pad, connected to GND, I GOT the pad connected to GND, but Altium throws an error. Other than ignoring it, what's the way around this error?

author: ajb
author_rank: Super Contributor
timestamp: November 23, 2016, 01:05:00 pm
content: If you edit the pad properties and under "Size and Shape" select "Top-Middle-Bottom" and set the pad size on the unused layer to zero so that there's no pad on that side, does it still throw an error?
Multiple 3D models for the same footprint - Page 1
Forum section: electronics / general

author: hansibull
author_rank: Regular Contributor
timestamp: November 22, 2016, 09:10:57 am
content: Hi!Is it possible to add multiple 3D-models to the same footprint, and choose which one to use?I'm creating a custom component library, and e.g for the DIP-8 footprint I want to add a DIP-8 IC and a 4P DIP switch. Can the 3D model be added to the schematic library instead?Now I've just imported the 3d model using "P + 3D Body" and selected "Generic 3D model"Thanks!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 22, 2016, 11:42:18 am
content: Legacy PCB3D models I think can do that?The canonical way to do that today, would probably be, make one footprint for each (as if you're using the parts, one at a time, alone), then use project variants to link an alternate library part and footprint for the other kinds.Tim

author: hansibull
author_rank: Regular Contributor
timestamp: November 22, 2016, 12:02:00 pm
content: the PCB3D library designer is not very intuitive. I'm able to import the .step 3d model, but there's no way to align the 3D model to the PCB footprint. After adding the component to a schematic (preview with the 3D model) and importing them into the PCB, I'm just getting the bare footprint and not the 3D model. There's very little resources about the PCB3D editor out there. Is it weird wanting to have jellybean footprints with different 3D models?EDIT:I tried to add a component from Analog Devices (ofiicial library), which had its 3D model in a separate file. The 3D model did not appear on the PCB, only the footprint.

author: hansibull
author_rank: Regular Contributor
timestamp: November 28, 2016, 09:29:21 am
content: I send a mail to the Altium support team, and it turns out it isn't possible. I'm joining Dave's rant!Quote
Using 3d models for case cutouts? - Page 1
Forum section: electronics / general

author: poodyp
author_rank: Regular Contributor
timestamp: November 17, 2016, 01:21:13 am
content: So I'm trying to design a project using a Hammond case. Thankfully Hammond provides 3d models, which is great for finding the right board shape, but I was wondering if I can use the 3D models of the buttons, plugs, and whatnot, to make a drawing for cutting the openings.I know I could just do it by hand with the measurements, but it would be much simpler if there were a way to do it automatically.

author: D3f1ant
author_rank: Frequent Contributor
timestamp: November 17, 2016, 06:49:12 am
content: I recommend CAD software such as Solidworks or Inventor (or some other 3D cad package) for the mechanical aspects. Virtually assembling PCBs into boxes, adding switches, displays etc is much much easier if you use the right tool for the job.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 17, 2016, 10:09:29 am
content: That's at the point where I save the STEP and send it to the project ME.Actually, beyond that point, because we've probably been doing some back-and-forth already. Or, the mechanical design is fixed by other constraints, and I already have a model to go.If you're doing this yourself, you can make the drawing for where to cut -- pick off another mechanical layer and start drawing. Add lots of points on the 3D models to snap lines to. You can also turn the model sideways (open its properties and change angles) and get snap locations that way. Or save a STEP of the PCB and load that, working from it in whatever orientations are suitable, so you get board and components in the same view.It's not going to be anywhere as nice, or as easy, as doing it in SolidWorks (or having someone else do it!), of course.Tim

author: poodyp
author_rank: Regular Contributor
timestamp: November 19, 2016, 11:35:51 am
content: Ah yes, doing it in Solidworks makes sense, I'll have to figure all that out then. Thanks for the help.

author: ajb
author_rank: Super Contributor
timestamp: November 20, 2016, 10:16:27 pm
content: If you're not already familiar with SolidWorks and/or don't want to pay another $8k for MCAD, you might take a look at Autodesk's Fusion 360. I've been hearing a lot of good things about it, and it's much less expensive than SW, down to being free for hobbyists or small entrepreneurs. I think the commercial license is like US$30/month.
Designators in child sheets? - Page 1
Forum section: electronics / general

author: slow_rider
author_rank: Regular Contributor
timestamp: November 12, 2016, 10:47:42 pm
content: I have a schematic with a hierarchical block in it. The block appears 3 times and is linked to a child schematic. When I annotate the project, the child sheet schematic will get treated as if it appears once, but in reality the parts should have a different designator in each instance.How to do that?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 13, 2016, 12:47:12 am
content: Compile project.Open the subsheet.Click the tab along the bottom of the view: one for each channel. You will find physical designators here.On this view, you can also assign substitute parts for different variants (for that, you will need to set up project variants).Or you can change them on the PCB and back-annotate.Tim
Looking for design rule files for OSHPark - Page 1
Forum section: electronics / general

author: cgroen
author_rank: Unknown
timestamp: November 14, 2016, 06:14:02 pm
content: Looking into AD (used Protel in the VERY old days and PADS), we have been using OSHPark for prototype boards the last few years.I was wondering if there is any of you superusers that have made design rule files for OSHpark 2 and 4 layer boards already that would be willing to share ?(I know it is just a matter of stuffing the right numbers in, but there are already a bunch of things to get up to speed on in AD, so was kinda hoping we could cut a corner here at least for the initial tests....
Purple pads , no other layers visible - Page 1
Forum section: electronics / general

author: strawberry
author_rank: Super Contributor
timestamp: November 01, 2016, 12:23:22 pm
content: Did I broke Altium?All layers turned on

author: vzoole
author_rank: Regular Contributor
timestamp: November 01, 2016, 07:20:08 pm
content: Maybe press 'Clear' (right down).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 02, 2016, 05:10:58 pm
content: SHIFT+C (clear mask),SHIFT+S (toggle single layer mode),Numpad + or - or * (change layers, or select layers from the tabs along the bottom)Also check that other layers are enabled (leftmost tab, or Design / Manage Layer Sets).Also check that the layers are not all colored purple ('L' or D, Y -- Board Layers and Colors).Tim

author: DutchGert
author_rank: Frequent Contributor
timestamp: November 04, 2016, 01:38:29 pm
content: ^U just discovered a very handy feature
Equal length fanout - Page 1
Forum section: electronics / general

author: blueskull
author_rank: Unknown
timestamp: October 31, 2016, 09:06:32 am
content: How do you do equal length fanout in AD? I'm not asking for length matching between nets of the same class. I'm asking for fanning out signal of same net from a common source to different locations.I do not want to touch xSignals unless necessary. I only have 4 nets need this kind of delay matching, other nets are not delay sensitive.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 31, 2016, 01:52:44 pm
content: So it's not really a matched net length, but a matched subnet length? Should you be using From-Tos? Or a clock distributor or buffer to minimize the mismatch at the source? (Yes, the buffer itself may have much worse delay matching than your PCB layout, making that a silly solution. On the other hand, if it has to be that precise, surely you're screwed regardless, and some means of fine adjustment will be necessary anyway?)Anyway, there's an example in the Altium docs of using a net bridge to fan out symmetrical delays. That's another option.Tim
Error Altium Designer 17 Extensions & Updates - Page 1
Forum section: electronics / general

author: montcler
author_rank: Contributor
timestamp: November 25, 2016, 07:48:19 pm
content: Hello all.After installing Altium Designer 17 twice and clean the registry.When I update Extension & Updates and Ejection Altium the following errors ...Code:C:\ProgramData\Altium\Altium Designer {E992429A-B704-4AF7-9EC0-55256E4170B2}\Extensions\Supplier_Newark\Supplier_Newark.dll(The File Exist)C:\ProgramData\Altium\Altium Designer {E992429A-B704-4AF7-9EC0-55256E4170B2}\Extensions\Supplier_FEData_PCB\Supplier_FEData.dll(The File Exist)C:\ProgramData\Altium\Altium Designer {E992429A-B704-4AF7-9EC0-55256E4170B2}\Extensions\Supplier_FEData_CS\Supplier_FEData.dll(The File Exist)C:\ProgramData\Altium\Altium Designer {E992429A-B704-4AF7-9EC0-55256E4170B2}\Extensions\Supplier_Octopart_CS\Supplier_Octopart.dll(The File Exist)C:\ProgramData\Altium\Altium Designer {E992429A-B704-4AF7-9EC0-55256E4170B2}\Extensions\Supplier_ODBC\Supplier_Odbc.dll(The File Exist)When rebooting the Altium later appears "Please" wait a moment ....And the program will not start.I go to the folder path and they exist.What can happen..¿?THX.

author: ElektroQuark
author_rank: Unknown
timestamp: November 25, 2016, 08:05:50 pm
content: Years ago I saw something similar: the setup files were corrupt (a bad trial download from Altium). Downloading the file again and reinstalling solved all problems.
BNC bulkhead footprint (D hole) - Page 1
Forum section: electronics / general

author: eliocor
author_rank: Unknown
timestamp: October 24, 2016, 05:37:46 pm
content: Being new to Altium, I have LOTS of things to learn...One for all is how to define the mounting hole for a BNC bulkhead connector (to be mounted directly on the PCB): see attached pictures.Any suggestion on how to define the hole like in the pictures (it should be metalized)?

author: ataradov
author_rank: Super Contributor
timestamp: October 24, 2016, 06:12:37 pm
content: Just define it in a mechanical layer. For metalization, you will have to talk to your board manufacturer and specifically negotiate this point.Also, keep in mind that typical mill diameter is 2 mm, so you need to think hoe those sharp corners will end up, and plan for that.

author: free_electron
author_rank: Super Contributor
timestamp: October 24, 2016, 07:46:04 pm
content: draw on a mechanical layer , select the drawn elements and go to tools- > board -> create cutout.

author: eliocor
author_rank: Unknown
timestamp: October 24, 2016, 11:13:11 pm
content: QuoteI would prefer to define a component with the already defined cutout, instead of putting a PCB cutout after placing the component...Any suitable suggestion?What I would like is to define a "plated multi-layer pad" but with a shape different from "round/rect/slot"

author: Fortran
author_rank: Regular Contributor
timestamp: October 25, 2016, 12:02:49 am
content: Does it really have to be plated through?I would have made a ring without soldermask on both sides and coupled with some via stitching. You can define cutout in footprint.Easier and cheaper. Your fab house will likely charge plenty for an oddly shaped plated hole like that.

author: eliocor
author_rank: Unknown
timestamp: October 25, 2016, 12:07:26 am
content: the via stitching is a reasonable option... Thanks

author: free_electron
author_rank: Super Contributor
timestamp: October 25, 2016, 07:06:14 pm
content: Quote from: eliocor on October 24, 2016, 11:13:11 pmso? that is what i describe. store the cutout in the library itself.anything you can do on the pcb you can throw in the library.here is a little secret with altium : ANYTHING that can be created on the PCB can be copied into the library. the library editor itself has a few limitations in terms of editing capabilities, but NO restrictions as to what can be put into it... you can even store an entire board as a library element ...i frequently create new components in the PCB editor itself. then select the primitives , open the library editor and simply paste them there ...

author: eliocor
author_rank: Unknown
timestamp: October 25, 2016, 10:00:39 pm
content: thanks for all suggestions, but as I wrote, I'm really a newbie regarding Altium and what it seems straightforward for you it is not so easy for me...
Drawing subscript/superscript - Page 1
Forum section: electronics / general

author: crispytato
author_rank: Regular Contributor
timestamp: October 20, 2016, 11:42:00 am
content: Hi all,I've been working on a project in Altium recently, and for the first time I've been making a bunch of schematic symbols from scratch for my personal library, rather than modifying existing ones or finding them online, already made.I've stumbled onto an issue I can't seem to find an answer for, even with many google searches using all sorts of keywords. I would also like to be able to place subscript or superscript in a pin name, for example DOUT. Or, for that matter, using sub or superscript in other places in AD would be cool too. I'm aware of using backslash to create a bar above a character for an active-low function, so I'm guessing this is possible, somehow. I've tried all the basic escape characters like * or #, and had no success.I assume a function this simple would be included in the software, but as with a lot of stuff you can do in AD, it always seems to be well hidden, to all but the most long term, dedicated users.I have AD16 at the moment, if that's important.Thanks!Chris

author: drane2
author_rank: Newbie
timestamp: October 26, 2016, 09:04:46 pm
content: I don't believe this is possible, only because I've never seen it done before. Personally, I would just emulate the effect with a combination of upper and lower characters.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 27, 2016, 12:45:34 am
content: Nope. Very limited formatting, for good reason I would suppose. (Though the lack of Unicode support is, I think, a historical issue.)Use mixed case, or separators (hyphens or underscores, most often), to name things.Tim
What via size is correct - Page 1
Forum section: electronics / general

author: kvresto
author_rank: Regular Contributor
timestamp: October 18, 2016, 05:16:23 am
content: Hi Everyone, just a quick question about via sizes. I have a 3.3V power trace snaking its way around the PCB, using top and bottom layers. I'm using via sizes of 0.66mm diameter, and 0.33mm hole size, and I want to know is it advisable to use this size via to connect a 1mm power traces across the top and bottom layers, there a few of these connections?What is the correct design practice here? current capacity? impedance? other?The pic shows a 0.65mm trace.thankskvresto

author: DerekG
author_rank: Frequent Contributor
timestamp: October 18, 2016, 11:45:44 am
content: Quote from: kvresto on October 18, 2016, 05:16:23 amPower planes (copper flood areas) are always good practice, especially for the earth.Having said that, often you can "snake your way around in a circle" to that the power track is fed current from both ends. I do this very regularly.

author: kvresto
author_rank: Regular Contributor
timestamp: October 19, 2016, 10:37:13 am
content: great, thanks

author: Jeroen3
author_rank: Super Contributor
timestamp: October 19, 2016, 11:10:48 am
content: Use two 0.5 mm via's.

author: fanOfeeDIY
author_rank: Unknown
timestamp: October 20, 2016, 02:30:17 pm
content: I am not a PCB designer so I only could comment the size commonly saw and used when I was working at an Electronic company which the PCB designed by others colleagues.For regular signal trace, track width was 0.2mm, via diameter was 0.6mm, via drill was 0.3mm.For power rail, track width was 1mm, via diameter was 0.6mm, via drill was 0.3mm and often time multiple vias were used to connect the rails.I have no idea of math behind how the size was chosen, but it seemed to be working OK.Of course real analog, RF, high frequency digital circuit, and etc, were different.

author: crispytato
author_rank: Regular Contributor
timestamp: October 20, 2016, 02:55:51 pm
content: Check out Saturn PCB toolkit. It allows you to calculate, to excruciating level of detail, the properties of vias/traces etc. You just need to decide on an acceptable level of voltage drop, put in your pcb properties, and you can get the minimum size of via that would be acceptable.It's free, and helps me a heap when I'm worried that a power trace might be marginal (they seldom are, but I like to design with a large margin of error, rather than cutting it close to the limit!)

author: kvresto
author_rank: Regular Contributor
timestamp: October 20, 2016, 11:59:51 pm
content: Great app, also found one of Daves older videos, EEVBlog #543 - PCB VIA Current Investigation. All the information you could ask for.
How do i design guard ring in PCB? - Page 1
Forum section: electronics / general

author: behzad63
author_rank: Contributor
timestamp: October 10, 2016, 04:13:08 am
content: Hi dearI want to know how do i design guard ring in PCB?Thanks

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 10, 2016, 06:14:10 am
content: Place the copper shapes as needed, then select them and apply the "solder mask opening" setting in the Inspector Panel.Tim

author: tszaboo
author_rank: Super Contributor
timestamp: October 10, 2016, 12:00:24 pm
content: You should place lines instead of tracks. Put it on the top/bottom copper and the soldermask. Tracks might work, but make sure to turn off "automatically remove loops". You probably know that the guard ring is only working, if the voltage difference between the senistive node (*pcb junction) and the guard node are the same voltage. So the guard ring is driven by something, like an opamp. I usually use the "VCC power port" to name the guard ring.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 13, 2016, 04:19:50 pm
content: Thanks, how a floating copper loop protects the circuit? I mean what's the purpose of the guard ring and how does it help us?

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 13, 2016, 06:14:26 pm
content: Quote from: ali_asadzadeh on October 13, 2016, 04:19:50 pmguard ring is not floating, usually its connected to the buffer of the high impedance signal input. the purpose is to avoid any stray different signal from surrounding got injected into the high impedance node.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 14, 2016, 06:20:22 am
content: Do you not know... have you not read about what a guard ring is? You must've readsomethingor you wouldn't know it's a thing that exists! Surely if you have understood its purpose, you would also understand where to apply it...Tim
Allegro .dra footprint to Altium - Page 1
Forum section: electronics / general

author: arduino_guy
author_rank: Contributor
timestamp: October 23, 2016, 10:43:12 am
content: Hi,Presently I have a large component library in Cadence Allegro. I'm trying to convert the library completely into Altium. I have already converted .OLB schematic symbol library to Altium using Altium import wizard. But it seems that there is no way to import footprints directly into Altium. I have an entire folder with .dra and .psm Allegro footprints. So far, I have been placing all the needed footprints on a board file and then import it using Altium import wizard. But this is impractical for placing my huge component library. Please chip in if someone knows a solution.
Undocumented cut-copy feature/bug? - Page 1
Forum section: electronics / general

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 07, 2016, 11:27:22 pm
content: Works in AD16.0, at least.In schematic view, select some objects.Under Tools/Preferences/Graphical Editing, turn on Clipboard Reference.CTRL+C, CTRL+X, left click (to execute Cut), right click (to cancel the stacked Copy).CTRL+V and click. You Paste a screenshot of the selection (transparent background, roughly 100 DPI resolution), instead of objects!Not sure how many permutations of stacked CTRL+C/X/other modes can be used together. Also I don't recommend using stacked modes, since they tend to be buggy, and hard to use. I just thought this behavior was rather unusual, and potentially useful, on the odd occasion you might need a screenshot snippet somewhere.Tim

author: free_electron
author_rank: Super Contributor
timestamp: October 11, 2016, 02:04:27 pm
content: stacked mode works perfectly fine. BUT !!! only 3 levels deep. if you are unsure where you are : <ESC><ESC><ESC> this brings you out of stacked mode, irrespective of where you are
Removing silkscreen without unlocking primitives ? - Page 1
Forum section: electronics / general

author: Warhawk
author_rank: Frequent Contributor
timestamp: October 11, 2016, 07:48:35 am
content: Hello folks,I am wondering if there is a chance (e.g. trick using design rules) to get rid of the 'Top Overlay' layer for all components without unlocking primitives and deleting the layer** ?I would love to get rid of those silly Top Overlay contours which are the part of libraries.https://ctrlv.cz/YiU7On the other hand I would like to have some custom silkscreen prints on the board so removing the layer (excluding it from manufacturing) is not the solution.I could not find the way how to add a custom layer, something like "my_Top_Overlay" either.Any ideas ?Thanks !______________________** I don't want to unlock primitives because of the possible problems with library update later and related risks.

author: vzoole
author_rank: Regular Contributor
timestamp: October 11, 2016, 11:25:51 am
content: Just create a new mechanical layer for custom silk screen and create gerber file for it.You can ignore or delete the original .GTO file.

author: Warhawk
author_rank: Frequent Contributor
timestamp: October 11, 2016, 12:38:27 pm
content: vzoole - Thanks for the answer. How can I create a new mechanical layer ? Looking and the Layer Set Manager does not give me any option to add a new layer. Just to create a new Layer Set (pre-configured view).Thanks in advance.I found it. I had to uncheck "Only show enable mechanical Layer". However now I am not able to see my text in 3D preview. But it is still better than nothing.