AD4134 / AD7134 in minimum I/O mode - Page 1
Forum section: electronics / projects

author: Alex
author_rank: Regular Contributor
timestamp: July 03, 2023, 12:49:46 pm
content: Hi all - we are stuck with getting the AD4134 to output data in minimum I/O mode. I was wondering if there is anyone here that has experience with this chip, or the older part the AD7134?In summary, it looks to us like everything should be set up correctly to get data out of the AD4134 in minimum I/O mode, but SDO is actually silent when trying to read data. This doesn't appear to be a physical issue with the MISO line, as we are successfully using it to set and readback config registers over SPI. We believe the ODR clock and CLKIN signals are correct, having checked frequency, voltage levels and jitter. Jitter is ~3.7ns for ODR and <0.4ns for CLKIN. Pin config of the ADC also looks correct on the schematics and voltage levels are correct on the pcb.Detailed description of the issue:Meanwhile, we are also trying to get some pointers from ADI.- SPI SCLK is 8MHz- ODR is 8kHz, with a 20%-80% rise time of 3.7ns and a jitter of about the same (see scope traces, attached). We have tried different duty cycles, from 50%, 5%, 0.5%. The signal is generated by a hardware timer, without software intervention except starting it.An init sequence sets the AD4134 to:- high power mode- CLKOUT disabled- reference gain correction enabled- data frame of 24 bits data + 6bit CRC + 2 status bits (total 32 bits)- DOUT format 0 (i.e. serialised channels on DOUT0)- MPC_CLOCK_DEL = 0 for all 4 channels- wideband filter set to 0.443 * ODRAfter the init above, starting data capture, the following happens:- CS is brought low (we used a scope to observe it going low and staying low)- SDO_PIN_SRC_SEL is set to 1 (enable DOUT0 duplication to SDO)- the hardware timer that generates ODR is started. We can measure ODR behaving as expected (i.e. as described above)- after each falling edge of ODR, a 16 bytes (i.e. 4 frames of 4 bytes each) SPI transfer is made. We observe some crosstalk on ODR, but the peak is below Vin Low, so we think it's not affecting the PLL lock)- However, we don't see SDO (MISO) moving at all. (see attached logic analyser trace)We have also tried the following test, to rule out issues with ODR:- usual init as described above- CS is brought low (we used a scope to observe it going low and staying low)- SDO_PIN_SRC_SEL is reset to 0 (disable DOUT0 duplication to SDO, so that we can use SPI to read the diagnostic reads)- the hardware timer that generates ODR is started. We can measure ODR behaving as expected (i.e. as described above)- every 25ms, we read DEVICE_STATUS and the diagnostic registers between 0x40 and 0x47), with the following result:- DEVICE_STATUS=0x01 DIG_FILTER_OFUF=0x00 DIG_FILTER_SETTLED=0x0F INTERNAL_ERROR=0x08 SPI_ERROR=0x00 AIN_OR_ERROR=0x00- we think this means that the PLL is locked, the FIR filter has settled and the only issue is that there weren't enough SCLK clocks to shift out all 16 bytes of data in an ODR period (which is normal, because we are using the SPI to read the diagnostic registers, not clocking out data)In short, it looks to us like everything should be setup correctly to get data out of the AD4134 in minimum I/O mode, but SDO is actually silent when trying to read data (note that we can normally get data from MISO when using SPI to accessconfiguration registers, so it's not a physical problem with the MISO line)