Understanding peculiarities of the switch node in a SEPIC - Page 1
Forum section: electronics / projects

author: liteyear
author_rank: Regular Contributor
timestamp: May 26, 2025, 06:02:52 am
content: I've been studying a 12V-in, 56V-out SEPIC with reports of frequent failures. The final failure scenario is a short between SW and PGND.Mostly the switch node does as I would expect, sitting at the input voltage and then switching to the output voltage + input voltage according to the soft start ramp:Occasionally I catch it doing something less desirable:At the knee of the soft start, the switch node (yellow) and the anode of the diode (cyan) oscillate wildly:And if you zoom in you can see the duty going a bit nuts:I have a couple of theories on the cause, but I'm trying to understand what factors are relevant here. Given this is during soft start, when the FB pin is ignored and the rising voltage on SS is used instead, how is the compensation network involved? Further, given that the output voltage is oblivious to this oscillation (it just rises as if the oscillation wasn't present), what can the controller do to control for this event?

author: Berni
author_rank: Super Contributor
timestamp: May 26, 2025, 06:17:28 am
content: One guess might be the inductor going close to saturation during startup.The softstart does usually still use the FB. The way softstart is most often implemented is to ramp the internal reference voltage from 0V to whatever the actual reference voltage is. This way the feedback network also wants the output to make a ramp from 0V to rated output. This also means the COMP pin is relevant during startup, so it can still be a regulation loop instability. You can put a scope probe on the COMP pin to get an idea of how aggressively the regulation loop is trying to steer the output.So perhaps slowing down the soft start could help the inductor not saturate while charging the caps.

author: liteyear
author_rank: Regular Contributor
timestamp: May 26, 2025, 09:38:03 am
content: Thanks Berni,Quote from: Berni on May 26, 2025, 06:17:28 amIt was an early theory of mine too. But saturation is rated as 8A, and the controller's cycle-by-cycle current limit is supposed to kick in at 3.26A. It now seems more likely that the current limit is triggering.QuoteOh you're quite right! I'd got my wires crossed. "The device regulates the FB pin to the SS pin voltage or the internal reference, whichever is lower.". So yes, it'serror = SS - FBduring this time.Still, this oscillation does not appear on FB, so can it be regulated?QuoteThis does seem to help, and has guided me towards the dV/dt of that early SS period as being a contributing factor. But there are practical limits on SS time, and because it's impossible to prove the absence of a fault, I'd like to better understand this instability in case more is latent.Here's SS, FB and COMP during these events. Note the timebase is the same but voltage scale is much finer.SS:FB:COMP:It's not obvious how COMP is aligned in time, so to help I've annotated it with a "T", which corresponds to the trigger point in my previous post.

author: mtwieg
author_rank: Frequent Contributor
timestamp: May 26, 2025, 12:55:41 pm
content: The 85V absolute maximum rating on the SW node leaves very little margin for this design. Clearly the oscillation can cause Vsw to exceed this limit, so that might be the cause of your failures.Quote from: liteyear on May 26, 2025, 09:38:03 amOne thing that's peculiar is that in the fourth capture of your second post, the COMP pin reaches around 2.65V. According to the datasheet, Vcomp = 1.1 + 0.19*Isw, which suggests that peak Isw is around 8.6A at this time. However, that equation doesn't factor in slope compensation, so perhaps this is a red herring.One thing to consider is subharmonic oscillation, but I don't think that alone would explain that oscillation.Quote from: liteyear on May 26, 2025, 09:38:03 amIn your latest scope captures, I can't see any evidence of the instability, are you sure it's actually happening? Are these captures with the increased SS time?I'd like to see something similar to the third or fourth captures of your first post, but with the COMP pin voltage included as well.

author: jonpaul
author_rank: Super Contributor
timestamp: May 26, 2025, 01:46:25 pm
content: find and read the many papers and app notes/seminars on SEPIC, CUK and other such SMPS topologies.See especially Dr Richard REDL.j

author: UnijunctionTransistor
author_rank: Frequent Contributor
timestamp: May 26, 2025, 04:03:23 pm
content: I believe that JonPaul meant Dr Ray Ridley, a power supply stability guru and founder of Ridley Engineering.Ridleyengineering dot comHe has dozens and dozens app notes and videos in the web page, and buried somewhere in there, there is a lengthy discussion about Sepic controller stability. Search for it.Dr Ridley is, or was, very skeptical of the Sepic topology, mentioning that it was a nightmare to stabilize correctly.

author: jonpaul
author_rank: Super Contributor
timestamp: May 26, 2025, 04:46:51 pm
content: Hello again: I referred to my old friend Dr Richard REDL, fellow of IEEE and editor for many proceedings....Specialist in power electronics, topology, compliance, EMI, PFC.Since 1980s, Richard has done Many seminars and papers on these topics....https://www.researchgate.net/profile/Richard-RedlAgree that Ray Ridley is another great resource ....Jon

author: Berni
author_rank: Super Contributor
timestamp: May 26, 2025, 07:34:43 pm
content: That COMP pin doesn't seam to be oscillating but it does make a pretty sharp transitions during startup. It could be that this transition briefly causes it to hit the current limit from the jolt and the oscilation is the controller bouncing off the current limit (Since SEPIC topologies are known to be a bit unstable in certain conditions)Id try increasing the value of the capacitor on the COMP pin to slow it down and see if it behaves better.For best results it is a good idea to put the converter trough a load transient test and see how it reacts. If it is reacting quickly enough then you can increase capacitor values on the compensation node without worries. Good easy way of performing a load test is to hook up a power mosfet to a signal generator and have it quickly switch in a large resistive load on the output at the rate of a few Hz, then watch the output voltage with a scope.

author: liteyear
author_rank: Regular Contributor
timestamp: May 26, 2025, 09:52:16 pm
content: Quote from: mtwieg on May 26, 2025, 12:55:41 pmAye. I figure if this is notthefailure cause it will beafailure cause. Of course, I need to findallfailure causes to be successful.QuoteYeah, I noticed that. Vslope is 500mV, so even at 90% duty that would still be 5.8A for Isw. Given the current limit is 3.26A, I don't think that's right. Maybe because I'm measuring COMP, which is the inverting input, and that calculation is for the non-inverting input? See:What's also interesting is that the "COMP clamp voltage" is 2.5/2.8 min/typ, and it looks like the COMP signal is flat-lining at this value.But, the oscillation starts when the COMP voltage starts to come down, not when it saturates. Again, I don't know if this is a worthy line of investigation, given that the oscillation is not present in FB.QuoteYep! The oscillation is not present at these nodes (except maybe a smidgen on SS, but that may be an effect, not a cause). It is contained to the SW node and the anode of the diode.QuoteGood idea. I'll capture something today.

author: liteyear
author_rank: Regular Contributor
timestamp: May 26, 2025, 09:55:43 pm
content: Quote from: jonpaul on May 26, 2025, 04:46:51 pmI've read so many references at this point, including the excellent work by Ridley. His comment on SEPIC is burnt into my brain:QuoteI'll look up Dr Richard REDL, thank you for the recommendation. Is there any particular work you'd suggest? I seem to be reaching the limit of my ability to find anything illuminating in published work.

author: liteyear
author_rank: Regular Contributor
timestamp: May 26, 2025, 10:07:26 pm
content: Quote from: Berni on May 26, 2025, 07:34:43 pmThis makes a bit of sense.QuoteOh boy yes that was an early line of investigation. Results were... inconclusive. When I added 100nF to the COMP pin (across the Chf cap) the oscillation reduced somewhat, and its frequency doubled! When I undid that and halved the Rcomp value instead (added another same value R in parallel), nothing seemed to happen. I concluded this issue was outside the realm of compensation, but that might have been premature. Possibly I could find alargerbandwidth that still provides sufficient phase margin, but I was really struggling to get confidence here.QuoteYes good idea. I think the challenge here is that the load presented by the output caps during ramp-up is way bigger than the real load. At the dV/dt I see during that soft start, the caps will draw 1.5A on average. The max load is 0.2A. Honestly, I don't know how the design calculator came up with these values. I feel like the controller is incapable of controlling this situation. But given that the oscillations require a very precise setup (I had to play with my experimental setup a lot to get it to occur consistently), there's more to this than I understand.

author: Afrotechmods
author_rank: Unknown
timestamp: May 26, 2025, 11:01:13 pm
content: Quote from: liteyear on May 26, 2025, 06:02:52 amThis might be a stupid comment but... have you considered that there is a resonance occurring at a certain frequency/pulse width during the startup phase?Some experience I can share from SEPIC design:1) The layout is the most finicky of all SMPS topologies. If you change the PCB layout, does it change these whacky oscillations?2) The coupling capacitor (C81 in your design) gets stressed REALLY hard in SEPIC. My intuition tells me that a 0.47uF 0805 will not be enough. Especially not with this high voltage a design. At a minimum try replacing it with 2x 1uF 1206. Maybe even 1210. It makes a shocking difference to efficiency too.

author: liteyear
author_rank: Regular Contributor
timestamp: May 27, 2025, 12:29:49 am
content: Quote from: Afrotechmods on May 26, 2025, 11:01:13 pmSeems perfectly reasonable to me! I just don't know what levers I can pull toalwayssteer clear of it, without affecting overall function.QuoteThe board actually has three identical layouts of this circuit on it, and all three exhibit different behaviour!! It's definitely sensitive to layout. Also sensitive to the phase of the moon, it seems.QuoteI thought for sure that was true. But it doesn't get at all warm. And I'm struggling to see why the design calculator only suggests at least 0.06µF! Do you have an intuition for how this value affects behaviour? I don't really, but can certainly trying slapping another one in parallel and testing.

author: mtwieg
author_rank: Frequent Contributor
timestamp: May 27, 2025, 12:39:52 am
content: Quote from: liteyear on May 26, 2025, 09:52:16 pmYes, according to the datasheet the slope compensation can only account for 0.5V on Vcomp. If possible I would try and probe the actual input current waveform.QuoteThe equation applies to Vcomp. However it only applies when the PWM comparator is the one being tripped first. When the fixed current limit comparator trips, then that should limit the peak Isw to the expected value of ~3.75A. Vcomp will continue to rise though, meaning Vcomp will no longer indicate the peak Isw. I'm guessing that's what's happening here. Even so, would be useful to probe the true current waveform.QuoteIf the oscillation truly doesn't appear on the voltage feedback loop (FB and COMP), then that means the instability exists purely within the peak current control loop. One thing to note is that slope compensation is not applied to the fixed current limit comparator. Therefore subharmonic oscillation is very likely to happen then. But you also stated that the oscillation doesn't happen until Vcomp starts to fall from it's maximum...But my gut tells me the oscillation is in fact in the voltage feedback loop though, and if you probe COMP and the switch node at the same time you'll see them both oscillating.It might be worthwhile to override the SS voltage and adjusting it carefully so the oscillation sustains itself. Just be careful to not wreck the LM5158 in the process...

author: mtwieg
author_rank: Frequent Contributor
timestamp: May 27, 2025, 12:43:59 am
content: Quote from: liteyear on May 27, 2025, 12:29:49 amDefinitely worthwhile to check out the coupling cap. Heat isn't what I'd be watching out for, but rather voltage stress. I'm assuming you're using a class II dielectric cap, in which case its effective capacitance may decrease a great deal as its DC bias voltage increases. So your 0.47uF might effectively be 47nF.

author: Afrotechmods
author_rank: Unknown
timestamp: May 27, 2025, 12:56:59 am
content: Quote from: liteyear on May 27, 2025, 12:29:49 amWow okay any design calculator that suggests 0.06uF for a SEPIC like this is a worthless design calculator. I hate to say it but now all the other component recommendations are sus too.The ESR of the cap matters a lot in general for any SEPIC design. And in the case of what you are dealing with here, the ESL too since we suspect resonance. mtwieg correctly expanded upon my point, stating that effective capacitance will drop massively at the voltages you are using this thing at. Also don't forget this capacitance change will be nonlinear and vary greatly from cycle to cycle. Nonidealities of the coupling cap can also throw off the control loop too because it's a huge part of the current path. Don't just slap another 0805 in parallel. Stick some really bigass cer caps on there to rule that part of the circuit out entirely. You want this cap to be as perfect a capacitor as possible, then you can scale things back given budget constraints. Forget about the temp of the capacitors. Measure the overall efficiency before and after and I would not be surprised if your converter gains 1%.

author: liteyear
author_rank: Regular Contributor
timestamp: May 27, 2025, 01:01:55 am
content: Quote from: mtwieg on May 26, 2025, 12:55:41 pmSW and COMP:SW and COMP zoomed:And for completeness, SW and FB:PS. Oh what a joy it is now that this is 100% repeatable and easy to capture.

author: liteyear
author_rank: Regular Contributor
timestamp: May 27, 2025, 01:25:04 am
content: Quote from: mtwieg on May 27, 2025, 12:39:52 amMakes a bit of sense. Still, according to the block diagram, the COMP pin is "just"Gm * (SS-FB)filtered by the compensation network. It's the other input of the PWM comparator that's proportional to Isw, and based on the capture I just posted it could well be sawtoothing as normal. But with the COMP pin clamped at max, the converter is just operating at its maximum duty cycle trying to catch up.Alas, I am currently without a decent current probe.QuoteThis could be the defining question! Look at the capture I just posted and tell me what you think.

author: liteyear
author_rank: Regular Contributor
timestamp: May 27, 2025, 01:52:25 am
content: Quote from: mtwieg on May 27, 2025, 12:43:59 amYes, Class II X7R MLCC. 08051C474K4Z2A from KYOCERA AVX. But it's rated at 100V. I so wanted this to be the smoking gun, but when the oscillation starts there's only ~15Vdc across the cap. I noticed these caps are "soft termination" and spent a long time trying to dig up characteristics. Apart from some vague ESR impact (which my measurements suggest are not particularly significant) I couldn't find much. I do still wonder if they have some peculiar aversion to current.Quote from: Afrotechmods on May 27, 2025, 12:56:59 amI'm always suspicious of these calculators' "operating range". The calculation is:Iout * Duty_min / (Vin_max * VCrr * Fsw)where VCrr is an undocumented constant of 0.05.I've done a bunch of sensitivity analysis on the 0.06µF value. It can be as high as 0.26µF with some fiddling of the specs, so I thought 0.47µF was an okay margin. What impact do you think the 0.47µF choice has?QuoteOkay, but given the load current is 200mA max and usually much less (in all the captures I've shared, it's about 5mA), that the instability starts with not more than 15% rated voltage across the cap (the instability is resolved by the time the voltage gets to ~50%), would you still apply the same focus? The DC current at the point of instability could well be ~3A, so I could imagine ESL and possibly even ESR being significant.

author: Someone
author_rank: Super Contributor
timestamp: May 27, 2025, 02:26:44 am
content: Quote from: liteyear on May 27, 2025, 01:25:04 amBlock diagrams are not the full detail and often missing significant parts/interactions. Without specific guidance from the parts engineers don't assume anything, particularly in start up and protection.

author: jonpaul
author_rank: Super Contributor
timestamp: May 27, 2025, 06:27:35 am
content: Bonjour: Selection of SMPS topology requires experience and knowledge of the benefits and downsides of available solutions.Three overviews:https://www.ieee.li/pdf/viewgraphs/smps-topologies-and-fundamentals.pdfhttps://www.smps.us/topologies.htmlhttps://www.we-online.com/en/news-center/blog?d=switch-mode-power-supplySee also the excellent work of Dr Cuk at Cal Tech Pasadena , circa 1980s..1990s.Dr Slobodan Cuk's 1977 PhD thesishttps://thesis.library.caltech.edu/1157/1/Cuk_sm_1977.pdfDr Cuk's USC Power Research Workshop:2011https://afjlevi.org/cgi-bin/Html/publications/PRW%20Cuk_TESLAco.pdfBoth SEPIC and CUK converters have severe requirements on the coupling caps. The inductors are also somewhat critical.SEPIC (and Cuk) SMPS topologies require careful attention to compensation to achieve a reliable stable result without oscillations or other instability.So, experienced SMPS designers usually select other topologies, eg buck/boost/buck-boost, forward or flyback configurations.The OP could review these refs and reconsider SEPIC topology, if simpler and less demanding solutions can be found.Bon ChanceJonPS: I Knew Cuk since 1980s. Brilliant power electronics guy. Still active after 50 years!

author: liteyear
author_rank: Regular Contributor
timestamp: May 27, 2025, 07:24:51 am
content: Quote from: liteyear on May 27, 2025, 01:52:25 amI found a description of this equation in another TI reference:but it uses 10% of Vin_min, not 5% of Vin_max! Anyway, it doesn't make a lot of difference, it still comes out to <0.5µF.This only strengthens my theory that the issue is the unusually large current required during start up - if I plug in the ~1.5A startup current (based on the dV/dt on the output caps) instead of the 0.2A load current I get something more like 1.5µF as the minimum. But then I don't know if that's just fiddling around at the edges, tuning for this scenario at the expense of others.FWIW, I did try adding another two 0.47µF series caps on the back of the existing one. Unfortunately I don't have a lot of 100V+ caps lying around to test options without common causes! Not surprising, it makes a difference. Anything makes a difference - input capacitance, output capacitance, input voltage, layout, etc. So tripling the series capacitance makes a difference:I see that COMP still hits the clamp, but much less severely now. And crucially it comes back down just before the critical knee point where input current is highest (because dV/dt and input/output current ratio are both high). There's still a wobble at this point, and importantly, it looksno lessthan when I was fiddling around trying to find a reproducible set of conditions. In other words, this looks just as prone to the oscillation as it did before I made the change. It might not be, I just can't be sure.And of course, now I can't restore the reproducible set of conditions. Removing the two extra caps, in theory putting it exactly as it was before, resulted in this:And then re-touching the solder joints and letting everything cool, results in this (repeatedly, now):So the oscillation is back, but it's different to before.So I'm led to believe that I can't expect this controller to handle a 1.5A startup current with a design spec of 0.2A load current. I could redesign it all to handle 1.5A, and roll the dice again on parasitics ruining the party. But given the input/output ratio I don't think it's really feasible. I could let it bounce off the current limit, but for reasons I don't fully understand, this seems unstable. It's proving difficult to pinpoint why. Various non-idealities and parasitics could be at play. As Ridley put it "the Sepic is not well understood".Unfortunately that weird steep part of the SS curve seems inherent. I've not got further insight from the TI support. Even if I did smooth the SS curve, I remain prone to the current limit in short-circuit conditions. In this application these are very rare, and failure may be acceptable. I'm also slightly encouraged by the datasheet comment that "recommends choosing the soft-start time long enough so that the converter can start up without going into an overcurrent state". Could there be known danger in overcurrent during soft-start?

author: mtwieg
author_rank: Frequent Contributor
timestamp: May 27, 2025, 12:32:49 pm
content: Ok so based on those waveforms, the oscillation only happens when Vcomp is saturated (but doesn't always happen), and always dies down once Vcomp decreases. So it looks like it is the peak current control loop, not the voltage control loop.I don't think I've ever designed a SEPIC with peak current mode control before, apparently it has quirks, especially when using the switch current as the peak current sense point. For buck and boost converters, the switch current is equivalent to the input current when the switch is on. But in SEPIC, the switch current is the sum of the input inductor current and the coupling capacitor current. I think this is why the current control loop tends to be unstable. I made a quick mockup simulation and I see even worse oscillation than what you're showing. But if I sense current on the input inductor, it behaves very nicely.

author: Berni
author_rank: Super Contributor
timestamp: May 27, 2025, 05:04:01 pm
content: Yeah looks like the startup is too tough for it.At this point id likely be trying to go for a different controller chip. Tho one trick you can do is add external current regulation. Did that a few times before when i needed a current limit on a controller chip that doesn't support it. You can add a shunt resistor and current sense amplifier to where you want to limit the current (can be input or output) then run that trough a diode into the FB pin. This means that whenever the current sense amplifier starts to output higher than the reference voltage + diode drop then the FB pin starts getting dragged upwards and this forces the controller to reduce the duty cycle, turning it into a current regulated supply. Found this useful for fast supercap chargers (without buying LTs absurdly expensive chips). Similarly you can use a inverting amplifier as voltage feedback into FB to build a Ćuk converter out of a regular boost converter controller (Also did that before because it was cheaper than buying the proper chip)You can also sometimes steal some power from the controller chip to conveniently power this current sense amplifier. Your chip a useful VCC pin that gives you a nice regulated 5V,

author: fourtytwo42
author_rank: Super Contributor
timestamp: May 27, 2025, 06:14:46 pm
content: I hope this is not to far off topic but can anyone tell me the specific advantage of this complex SEPIC converter in this application vs a straight boost converter ?EDIT:Thank you for allowing me to but in & provide me with illuminating answers, I guess the most obvious I should have thought of first is the o/p short

author: langwadt
author_rank: Super Contributor
timestamp: May 27, 2025, 07:29:25 pm
content: Quote from: fourtytwo42 on May 27, 2025, 06:14:46 pmthat there's no current limit if you short the output of a boost?

author: UnijunctionTransistor
author_rank: Frequent Contributor
timestamp: May 27, 2025, 08:30:12 pm
content: -SEPIC provides an output voltage which can higher or lower than the input voltage, without the polarity inversion.-On a boost circuit, even if you fully disable the PWM controller, there is still a direct DC path from the input to the output.-With coupled inductors, there is some degree of ripple steering.

author: langwadt
author_rank: Super Contributor
timestamp: May 27, 2025, 09:39:02 pm
content: Quote from: UnijunctionTransistor on May 27, 2025, 08:30:12 pmbut that wouldn't be needed for application mentioned, 12V in, 56V out

author: liteyear
author_rank: Regular Contributor
timestamp: May 27, 2025, 11:54:55 pm
content: Thanks all, especially @mtweig and @Berni for their illuminating suggestion for coupling current sensing into the feedback loop. Makes a lot of sense.Also to @jonpaul for pointing me towards some great references. I'm reading and reading and Cuk's work comes up a lot! You know... I thought I knew everything there was to know about SMPS. The more you know the more you realise you don't...I don't know why a SEPIC was picked for this application, but there's evidence it was designed for a much wider (60Vmax) input range and reused here. And @UnijunctionTransistor's list is great. Even if points 1 and 3 don't apply in this case!I suspect there's no appetite for significant redesign, so I'm still looking to mitigate rather than do-over.A TI engineer pointed out a significant mistake I'd made in my early reporting - the oscillation frequency is actually 39kHz, not 10kHz, which puts it in the ball park of the Lin-Cseries-Lout resonant frequency! And sure enough, in my last post the frequency of the oscillation with Cseries increased to 1.4µF matches the new resonant frequency! This has put me on a much clearer path, and I'm finding a lot of references describing this resonance as the SEPIC Achilles' heel.But I can't come up with a clear rationale for whether lowering or raising this resonant frequency is more likely to shift it away from excitation or towards control! I even found an old thread with @mtweig in it, with contradictory results! I see many references resort to adding a RC dampener instead, which feels a bit like cutting off your nose to spite your face.I think in this case, if the voltage control loop is out of action, then the excitation just comes from the balls-to-the-wall max duty cycle di/dt of the input inductor. That's Vin sensitive which rings true in my testing. And because my Vin is variable, could excite a range of frequencies perhaps.So maybe I could push the resonant frequency either way with a change to Cseries. Higher where its easier to dampen, or lower where its harder to excite. Or I could reduce the output capacitance and slow the soft start, to try to stay within the COMP limits at all time. Of course, any change I do make shifts the non-idealarities and parasitics, so it's hard to be sure of the net result.

author: liteyear
author_rank: Regular Contributor
timestamp: May 28, 2025, 12:19:53 am
content: Quote from: liteyear on May 27, 2025, 11:54:55 pmEh, it doesn't. It comes from the classic "sub-harmonic oscillation". Before the SW node oscillation I've been describing is present, the duty is a steady ~50%. Then as COMP increases, the classic short-long-short-long duty cycle grows and grows until it's around 86% / 8% and all hell breaks loose.Here's the emergence of the oscillation. SW in yellow and COMP in cyan.So is the root cause inadequate slope compensation all along, and the SW node oscillation is an effect due to inherent resonance??AddendumI've got my original reproducible case back! Earlier I reported that after adding 2 series caps in parallel and then removing, things were a bit different. Well I took a punt and increased Vin from 12.0V to 12.2V and boom, right back where we were. So, for proper demonstration of the point made in this post, see here for equivalent on my original reproducible scenario:Zoomed out:Zoomed in to start of oscillation.Note COMP is much higher and flatter, and the oscillation takes longer to form, but otherwise same story? Honestly I don't know how peak current control can be in effect with COMP so high.Addendum 2No wait! Here's an oscillation emergence thatproceedsthe sub-harmonic duty oscillation. The duty increases at the emergence, as it should, but it does not seem to oscillate. It clearly does start doing so 4 switch node oscillation cycles later. After that, things get out of control.Zoomed:So I'm back to thinking they're just partners in crime, rather than one being the cause of the other.

author: incf
author_rank: Frequent Contributor
timestamp: May 28, 2025, 12:32:21 am
content: QuoteI'm late to the party.I recently ran into problems on a more conventional SMPS where an internal op-amp saturated on the controller. It caused oscillation/chattering (and specifically in my case, it made an annoying noise) during startup in a very unpredictable manner. I don't know if that is relevant here or not, but it looks similar to my own oscilloscope captures. The behavior was fairly random and unpredictable, but once it started it would randomly bounce around for a while (tens or hundreds of milliseconds IIRC?) until the converter "got going"Those skipping alternate cycles were present on my design during saturationIn my case the magnetics (I presume) made quite a bit of noise. They seemed "unhappy" at stress the controller was subjecting them to.*When op-amps goes into saturation, they become slow, and the amount of slowness changes in a manner that can appear almost random (but is proportional to the amount of saturation). It can severely compromise the control loop. Invalidates many assumptions that apply to it during normal operation.Again, this might not apply to you. Take with a grain of salt. Your mileage may vary. et cetera

author: incf
author_rank: Frequent Contributor
timestamp: May 28, 2025, 12:51:34 am
content: Follow up question / speculation (I am perhaps too tired to be writing this):At the risk of ignoring the intricacies of SEPIC/etc. and making myself look sillyDoes this issue occur if you impose a minimum load of say 100mA? 10mA? 1mA? If you reduce the real load, does it get worse?"If I was a control loop with a transient saturation problem causing a slow response, what would I do? overvoltage the system and self destruct""It's consuming how many amps peak? and it only needs to supply 5mA?..." SMPS don't like transients, and they don't like being forced to perform the job of being a voltage source.The above is just superstition on my part. I have not thought about it nearly enough. But I do wonder - if there is a large inrush current that suddenly stops, is that a problem? I always have something like a minimum load resistor on my supplies to ease the job of the control loop at low loads.Just a hunch, I certainly could be wrong. I look forward to learning what the problem really is.addendum: would it make sense to clamp the voltages at the sensitive nodes with a TVS? (I don't know if there is enough margin for a TVS to clamp) Designing to be clamped by a TVS is another thing I tend to do - transients happen, SMPS controllers are terrible at dealing with certain things.

author: liteyear
author_rank: Regular Contributor
timestamp: May 28, 2025, 01:41:00 am
content: Quote from: incf on May 28, 2025, 12:51:34 amNo load (Iin still increases by ~35mA so maybe 6mA phantom load?):11mA load:43mA load:Honestly I'm pretty surprised how little this helped. Given that (1) I agree - current with nowhere to go is gunna go rogue, and (2) just looking sideways at the circuit usually helps, temporarily.I suppose the load is just so insignificant compared to the in-rush. However, note that the in-rush cycles around just fine, charging the caps, and then smoothly tapers off. But the magnitude of it still concerns me.QuoteI wouldn't call this is a transient issue. There's an unstable (increasing) oscillation so a TVS might backfire by providing a low impedance path for the peaks of the oscillation. Besides, yes, unfortunately there is bugger all margin - max rating is 83V and input+output could easily be 15+56 = 71V in normal operation.

author: incf
author_rank: Frequent Contributor
timestamp: May 28, 2025, 01:53:01 am
content: Can you confirm or deny the compensation op-amp going into saturation?it looks to me like the voltages of the inverting and non-invering inputs became unequal. Once that happens, it is no longer an op-amp and the control loops is temporarily broken. (voltages or currents will transiently make excursions from their expected values)If this is true, you need to find out why. In saturation op-amps slow down enough to cause problems.Can you drastically slow down the soft start for testing? (eg. by a factor of 100x or 1000x)Can you drastically speed up the soft start for testing?I suspect TI may have implemented their soft start in a way that might catch an unsuspecting user off guard.

author: liteyear
author_rank: Regular Contributor
timestamp: May 28, 2025, 02:34:51 am
content: Quote from: incf on May 28, 2025, 01:53:01 amI think this might be a misinterpretation. The COMP signal has a voltage clamp. This limit is being hit (we believe). At some point someone (me?) referred to it as "saturation" since it resembles that phenomena. There was also mention early on of possible (unlikely) inductor saturation. As far as I know, at no point has anyone suggested any op amp is saturated. Although now that you mention it I suppose a comparator is always in "saturation" but that's normal?QuoteIf we're talking about the same thing, in normal practice it acts as a comparator. The inputs are pretty much always unequal. See for example, Figure 9-18.QuoteYes. There's still a steep rise at the beginning of the soft start ramp, but its short lived and the subsequent very slow ramp results in long pulse skipping periods so nothing builds up. Here's 11x. I don't have anything higher as yet.QuoteNo! Oddly enough, when I halved the SS capacitance, the ramp didn't seem to change much. I could revisit this.QuoteSame. There's something strange about that initial turn on period.

author: incf
author_rank: Frequent Contributor
timestamp: May 28, 2025, 03:10:26 am
content: Quote from: liteyear on May 28, 2025, 02:34:51 amIn my experience with a similar controller, although it may not be well documented, the internal op amp(s) inside of SMPS ICs do not "like" being operated as comparators. If they are to maintain their response speed/bandwidth, they must be operated as an op-amp. (this can be impractical, having negative feedback, but that is how op-amps work, at least on the controller IC's I've dealt with)The (slow!) internal op-amp might work fine as a comparator at a fixed operating point (steady state), but when operating conditions are changing (transient operation) it won't work as expected due to its inability to respond quickly enough.Op-amps have an input stage and an output stage. When the inputs are too unequal, that input stage saturates. Once this happens, it becomes slow and exhibits symptoms that look (at least superficially) like your problem.In other words, the op-amp stops behaving like an op-amp (or comparator for that matter) for a period of time whenever it's inverting and non-inverting inputs are allowed to become unequal.I believe you may be assuming that your IC's internal op-amp is functioning as an ideal op-amp / "good" comparator. However, I'd wager its actual performance is that of a non-ideal op-amp / "bad" comparator.You may be tempted to think "but the datasheet didn't tell me to add negative feedback" unfortunately, I don't think it matters. During soft start you are rapidly changing the operating point, and if things change too quickly, the saturated input stage of the op-amp that you are operating as a comparator won't be able to keep up.If you can prove or disprove this, it may get you closer to an answer.I could be wrong. Not all controller ICs are the same. But it looks an awful lot like a problem I ran into previously.

author: liteyear
author_rank: Regular Contributor
timestamp: May 28, 2025, 05:31:11 am
content: Quote from: incf on May 28, 2025, 03:10:26 amHmm, I think I see what you're saying thank you. I made a small edit ("now that you mention it") to your quoted section while you were posting.Certainly, the controller seems to lose control whenever that COMP voltage goes near the limit. Not necessarily blowing up, but certainly behaving differently. I still think it could be explained even with "good" comparator behaviour (at the limit the comparator simply cannot invert), but don't really have anything definitive. The 1V to 2.8V clamp limits on COMP suggest it can't go too far.I did note the built-in slope compensation seems very adequate for any possible inductor slope by my calcs, so given subharmonic oscillation is present, perhaps the PWM comparator is out of action due to high COMP voltage. The fallback control is the current limit comparator, which doesn't have slope compensation.In any case, high COMP means we're no longer in ideal control territory.

author: Berni
author_rank: Super Contributor
timestamp: May 28, 2025, 05:54:19 am
content: Quote from: langwadt on May 27, 2025, 09:39:02 pmThat is also a fair point. But i assumed the OP has some specific reason for doing SEPIC.If i was designing a 12V to 56V DC/DC at these lower powers, i would likely go for the flyback topology instead. This means you can use any cheap boost converter chip, does not need to handle 60V and the flyback transformer helps keep the duty cycle closer to 50% so that it gets reasonable efficiency. Does need some careful design to keep the EMI noise down tho.

author: mtwieg
author_rank: Frequent Contributor
timestamp: May 28, 2025, 12:54:51 pm
content: Quote from: liteyear on May 27, 2025, 11:54:55 pmDamping is probably the right thing to do, short of a full redesign. In my simulation, using the component values in your original schematic, the oscillation happens at about 35kHz (regardless of whether Vcomp is saturated or not). If I add 1.5uF + 10ohms in parallel with the 0.47uF, then that oscillation goes away. If Vcomp does saturate, then I do see some oscillation but it's more familiar subharmonic oscillation at 250kHz, which is much easier to manage (and doesn't cause the SW voltage to rise significantly).The damping resistor dissipates negligible power (like a few mW) once everything is at steady state.edit: VVVVVVVVVV lol that is definitely an option as well!

author: langwadt
author_rank: Super Contributor
timestamp: May 28, 2025, 01:29:30 pm
content: Quote from: liteyear on May 27, 2025, 11:54:55 pmif can live with a boost, just change the BOM, removing L4 and replacing C81 with a 0R resistor ?