VHDL exponential operator (**) works for synthesis? - Page 1
Forum section: electronics / general

author: Maister
author_rank: Contributor
timestamp: October 27, 2023, 12:02:08 pm
content: Hi everyone,I am using a Tang nano 9k dev board to display some generated characters on an LCD display.Used FPGA is the GOWIN GW1NR-LV9QN88PC6/I5.I have included a feature that can rezise the characters by stretching the pixels in both axis by a power of 2.The piece of code that stretches the area for displaying characters uses the double asterisk operator (**) to calculate a power.I was aware that this operator only works when both operands are constants, however, I tryed it with a signal as power that even changes over time.Like : 2**<signal integer>To my surprise, this was synthesizeable and I could see the characters rezising in real time on my LCD.So what is going on? Every book I read about VHDL states that the exponentiation operator cannot be synthesised unless both operands are constants.The GW1NR-LV9QN88PC6/I5 has quite some adders, multipliers and even an ALU on board that seem to get instantiated in my design. But the ALU cannot do powers.Or is it because my base is 2? Because 2**x is actually the same as "0000001" sll x in VHDL, isn't it? So the syntheziser could recognize that and just do a left shift for that operation?Anyways I was really surprised.Any idea why this got synthesised correctly?BR;Patrick

author: ejeffrey
author_rank: Super Contributor
timestamp: October 27, 2023, 02:12:39 pm
content: There is no hard line for what is and isn't synthesizable. 2**N is a bit shift, it's easy for a synthesize to implement, so I guess it does. There isn't really any more mystery than that.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 27, 2023, 08:20:29 pm
content: Yes. There's often a misunderstanding of what is or is not synthesizable.And yes, it synthesizes multiplying by 2**n as a left shift by n positions, which is always synthesizable (it's a barrel shifter).Only a very old and crusty VHDL compiler would not manage to synthesize this as a simple shift. Not even sure it ever existed.But obviously, replace the 2 by a larger constant or by an integer signal and it won't be synthesizable anymore.(As a side note, if you want to use shift operators in VHDL, for reasons similar to favoring rising_edge() to 'event, I recommend using shift_left() rather than sll and similar for right shifting. It behaves better for simulation and is more readable.)

author: Maister
author_rank: Contributor
timestamp: October 27, 2023, 09:09:48 pm
content: Thank you for your input so far.For the shifting:I recall from one of my VHDL bed-time readings that theclk and clk'eventcondition expression can be replaced with the IEEE 1164rising_edge()function, if std_logic (or std_ulogic) is used for the Clk signal. Using rising_edge() can improve the accuracy of simulations, particularly in cases where you are simulating transitionsfrom uninitialized states.But I did not know that same holds for shifting. I find it cumbersome having to typeshift_left()when I can instead writesll. Also for me it is much more readable when the shifting operator is separating the word or vector to shift from the number of positions to shift, instead of having both as arguments to a function!Anyways, seems thatshift_left()andshift_right()have some advantages over srl and sll.Maybe I will consider switching to those.