Help me understand the Gowin speed grade - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: January 17, 2025, 03:30:17 am
content: Take for example the FPGA LV9QN88PC6/I5, the ordering information mention speed grade 6 for commercial temperature range and speed grade 5 for commercial temperature range.1. Does it means that if I use it for industrial temp range, the max clock speed I can use is lower than if I run it in commercial temperature range?2. The Gowin IDE report the max clock speed of the design. Should I expect a lower max speed reported if I specify to the tools the industrial range?We have a long thread in the link below about the meaning of C6/I5 and hasn't converge yet on a clear understanding. Any input would be useful.

author: ataradov
author_rank: Super Contributor
timestamp: January 17, 2025, 05:23:51 am
content: I think the only meaningful way to interpret it is this:The part number is for both speed grades at the same time and in the IDE you select the part number that includes both and the reported speed is for the part. And this has to be the speed for the full (industrial) range.The silicon performs worse in the extended temperature range, which is reflected in the number, but it is meaningless because your only option is to buy a "combined" partIt is kind of a bad way to specify this. It would be fine if the number actually meant something (like propagation delay or max clock speed in x100 MHz). And it might mean something internally, so the numbering makes sense to them. But externally it is just a number.The only way to find out which part you need is to synthesize for all speed grades and see which part fits the constraints.

author: zapta
author_rank: Super Contributor
timestamp: January 17, 2025, 04:20:39 pm
content: @ataradov, the IDE allows you to specify if you plan to use for the commercial or industrial temp range and adjust the speed grade field accordingly (5 or 6). You can see it the the dialog box in the attached page below.With this in mind, I would expect that if I build for C (speed 6) or I (speed 5) I should get different max clock speed reports.

author: ataradov
author_rank: Super Contributor
timestamp: January 17, 2025, 04:41:26 pm
content: I did not see that window before. I looked at the usual places where other IDEs specify operating conditions and I could only see the bank voltage levels.In that case their actual models may be tuned to the actual conditions, and the reported max clock should match set operating conditions. But I would not expect significant difference. So, the maximum clock for C6 would be about the same as for I5. At the end of the day, it has to work in the same silicon.

author: gael
author_rank: Newbie
timestamp: January 17, 2025, 08:57:59 pm
content: Speed grade is how fast a device is.COM/IND temperature range is over which temperature range the speed grade speed of a device applies.

author: ataradov
author_rank: Super Contributor
timestamp: January 17, 2025, 09:13:50 pm
content: That does not really clarify anything. Unlike other vendors, Gowin uses double I/C grades from the same device.

author: gael
author_rank: Newbie
timestamp: January 17, 2025, 09:25:55 pm
content: Yes, because a C6 can be used also as an I5. Faster in COM temp. range, -6, performing as -5 in the IND temp. range.

author: zapta
author_rank: Super Contributor
timestamp: January 18, 2025, 04:13:42 am
content: I played with and example on the gowin IDE with 4 settingsCode:set_operating_conditions -grade c -speed 5set_operating_conditions -grade c -speed 6set_operating_conditions -grade i -speed 5set_operating_conditions -grade i -speed 6And got these speeds (in Mhz):I must say that I am even more confused. What is the max speed I can use if I plan to use my design in commercial and industrial temperatures ranges respectively? According to that table its 186 for both temperature ranges which puzzles me.

author: ataradov
author_rank: Super Contributor
timestamp: January 18, 2025, 04:21:39 am
content: Have you constrained the required clock? What is it set to? Often tools will get over the desired clock speed and give up optimizing. Set some really high value, so they actually try.And then try multiple runs, since they often use random seeds producing different results.

author: zapta
author_rank: Super Contributor
timestamp: January 18, 2025, 04:29:11 am
content: The results seems to be very stable with runs with the same configuration. The max freq report looks like the screenshot below, it lists the constraints as well as the actual max.

author: ataradov
author_rank: Super Contributor
timestamp: January 18, 2025, 04:49:39 am
content: Set constraints higher than max values. The reported max value is not absolute max, but just the max for that placement. When it sees that it already met the required frequency, it does not try to optimize anymore.

author: zapta
author_rank: Super Contributor
timestamp: January 18, 2025, 07:01:53 am
content: I tried but the results seems to be the same. Looks like it tries to minimizes as much as it can, even if already within the constrains. Which is a good thing.

author: ataradov
author_rank: Super Contributor
timestamp: January 18, 2025, 07:24:49 am
content: The results seem to be much worse. It seems like it is struggling with so many things identified as clocks. I'd try to change one at a time and increase it gradually.I just tried on one of my projects that has one clock and supposed to be running at 60 MHz. With that set, it says max is 75.307(MHz). Setting it to 80 MHz, it improves to 80.3 MHz. Setting to 85 MHz. it tops out at 82.085 MHz.So, it does change the effort in response to the constraints. But the routing strategy setting also matters. Timing change is the most obvious when timing is set as a criteria.Those numbers are with no operating conditions set at all. With target of 100 MHz I get the following results: I5 and C6 Fast - ~86 MHz, I5 and C6 Slow - ~64 MHz.In any case, placing and routing is an NP-complete problem, so the tools are doing the best they can given the time constraints. Grownup tools can do a lot of random attempts and pick the best one. This does not seem to have anything like that.

author: zapta
author_rank: Super Contributor
timestamp: January 18, 2025, 07:00:25 pm
content: I repeated it with a simple example that doesn't leave much room for optimizations and the results are about the same. It seems that the Gowin IDE indeed uses the same timing information for I5 and for C6. As if numbering of speed grades for I are shifted by one from the numbering of speed grades of C..v file:Code:module parity (input sys_clk,output reg led // Active low);// Placement fails around 269.reg [260:0] counter = 0;always @(posedge sys_clk) begincounter <= counter + 1;led <= ^counter;endendmodule.cst file:Code:IO_LOC "sys_clk" 52;IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE;IO_LOC "led" 10; // Active low.sdc file:Code:create_clock -name sys_clk -period 2 -waveform {0 1} [get_nets {sys_clk}]set_operating_conditions -grade c -model slow -speed 5