fpga boards: curious about projects that *you* do, guys - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: August 21, 2017, 03:33:19 pm
content: talking about suggested fpga boards has made me a bit curious about projects (which kind) that you do guyshere I am focused on softcore & its debug processor (my own design, looooong story, looooooooong time project), and STN LCD drivers.what about you?

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: August 21, 2017, 04:53:31 pm
content: I like to replicate ancient processors, such as the 6502, 8080, and Z80.

author: legacy
author_rank: Super Contributor
timestamp: August 21, 2017, 05:00:15 pm
content: Yup, a good idea, because it makes things cheaper and smaller

author: hamster_nz
author_rank: Super Contributor
timestamp: August 21, 2017, 05:23:33 pm
content: Just general tinkering and experimenting at the moment.I'm making an Optical VOR-like directional IR beacon - just a one-pager of HDL generating the signals for the LED array used for transmission.I'm also playing around with an audio codec chip and I2S, playing with real-time audio processing algorithms.

author: rstofer
author_rank: Super Contributor
timestamp: August 21, 2017, 06:12:19 pm
content: My first true love was an IBM 1130 back in the early '70s. I have a fully functional version running on a Nexys2 board. 'Fully functional' means I have emulated card reader input, line printer output, console input/output, all as serial ports, and, from a hardware perspective, the most important component, an emulated drum plotter that heads over to my LaserJet. It also means it runs the entire IBM OS/compilers/assembler unaltered. Mine runs at 125x the speed of the original.At this very moment, I am implementing the LC3 RISC machine on a Nexys4. This got started when I ran across the project while discussing a microcoded Z80 in this thread:https://www.eevblog.com/forum/projects/home-build-microcode-design/Various links for LC3 are over there...It seems like an interesting project plus it comes with a C compiler (modified LCC) which means I might be able to use it as an embedded core for some other project.I have done a couple of Z80 projects (using the T80 core from OpenCores). One runs CP/M 2.0 in all its glory and at 50 MHz and the other runs PacMan using the original PROMs.I have also built a couple of logic analyzers, the latest fromhttps://sump.org/projects/analyzer/

author: legacy
author_rank: Super Contributor
timestamp: August 21, 2017, 08:11:14 pm
content: Quote from: rstofer on August 21, 2017, 06:12:19 pmYup, it's a common problem for those who want to develop his personal ISA. The first step tries to get hands on a assembly compiler which suites the new architecture, the second step tries to sort out the need of a C-compiler.LCC is the best solution since it comes with a book, and the code is enough modular

author: NorthGuy
author_rank: Super Contributor
timestamp: August 21, 2017, 11:52:10 pm
content: Setting aside the things I do with an intention to make money ...I want to design and build a good scope. I don't have much time, so it's going very slow.

author: legacy
author_rank: Super Contributor
timestamp: August 22, 2017, 06:55:05 am
content: Quote from: NorthGuy on August 21, 2017, 11:52:10 pmfind a job in avionics, we are plenty of needs for fpga!

author: legacy
author_rank: Super Contributor
timestamp: August 22, 2017, 07:16:03 am
content: Currently I am still on a LCD-driver for a customer.But it seems I can recycle a part of an old project.Some module.Oh, I am trying to write code like library code, even for hobbyCode:0 Jun 30 19:07 doc15132 Aug 21 22:43 kb_ctrl.vhd878 Aug 18 21:46 kb_ctrl_decode.interface.vhd1816 Aug 22 00:00 kb_ctrl_decode.vhd0 Aug 19 17:00 library.component.clock_scale_v10 Aug 19 17:05 library.component.signal_debounce_v2737 Aug 18 18:11 library.component.priority_decoder_v10 Aug 19 19:17 library.component.uart_16n1_v10 Jun 15 15:16 simfiles list in my keyboard controller folderCode:OrangeCube# myhdl-use-a-module-from-library signal_debounce_v2caching  library.component.signal_debounce_v2 {definition, interface, functions, body, testbenchs} ... doneBoth ModelSim and ISE are happy now: they have files, and I can reuse modules inside a new project and if I modify a line of these modules, I will be asked to commit the differences to the library, or to create a new branch.Not so bad(it's personal, but for me this method increase the productivity and helps in keeping things tidy)

author: legacy
author_rank: Super Contributor
timestamp: August 22, 2017, 08:20:37 am
content: Quote from: rstofer on August 21, 2017, 06:12:19 pma few resources foundhere. A simulator, LCC, examples, and a book!Where is the HDL code?

author: rstofer
author_rank: Super Contributor
timestamp: August 22, 2017, 01:05:36 pm
content: Quote from: legacy on August 22, 2017, 08:20:37 amDon't know about any HDL code, I whipped up my own in about a day. Essentially, I just took the author's FSM diagram and coded it directly. State for state. I have also used their hardware architecture as shown. Mux for mux...So far all I have are the basic 14 instructions. I have to take a break and rework that Python coded assembler to output hex instead of binary. Thanks to a posting elsewhere by Hamster_NZ, I have a way to get a hex file read into BlockRAM at synthesis time. But the file has to be in plain hex (I think!) to use the VHDL read function.My goal was to explore the similarity of HDL coding of FSMs and microcoding. Except for the format on the page, the processes are identical. Define the fields, define default values for the fields and then at each state define just the exceptions to the defaults.I ordered a copy of the book w/CD from Alibris, $10/shipped.It's just something to do. Vivado isn't necessarily helping. It keeps telling me that it has eliminated dozens of sequential elements when, in fact, it hasn't. Known "oopsie". To be fixed soon, I hope!

author: legacy
author_rank: Super Contributor
timestamp: August 22, 2017, 01:36:09 pm
content: Quote from: rstofer on August 22, 2017, 01:05:36 pmWhich is the full title of the book from Alibris?

author: rstofer
author_rank: Super Contributor
timestamp: August 22, 2017, 02:34:56 pm
content: Introduction to Computing Systems: From Bits and Gates to C and Beyond with CD-ROM by Patt Yale N. Patel Sanjay J. (2000-10-05) HardcoverI saw some expensive copies and I specifically wanted the CD-ROM. I found just one copy that was cheap and appeared to include the CD so I bought it.https://www.alibris.com/booksearch?keyword=patt+and+patelThere seem to be a LOT of cheap copies without the CD.

author: ebastler
author_rank: Super Contributor
timestamp: August 23, 2017, 04:52:55 pm
content: Quote from: Sal Ammoniac on August 21, 2017, 04:53:31 pmI enjoyed replicating this really ancient processor from 1956:http://www.e-basteln.de/lgp30/The Spartan-6 I used is totally over the top as far as computing power is concerned, of course. But it was very satisfying to be able to directly map the LGP-30 logic equations (which were published back then) to a VHDL model.

author: rstofer
author_rank: Super Contributor
timestamp: August 23, 2017, 07:04:12 pm
content: Quote from: ebastler on August 23, 2017, 04:52:55 pmVery nice project. I like the final construction (if a project is ever 'final').

author: ebastler
author_rank: Super Contributor
timestamp: August 23, 2017, 07:22:43 pm
content: Quote from: rstofer on August 23, 2017, 07:04:12 pmThanks! I had some fun with creative use of the copper and solder mask layers when designing the front panel as another PCB.With the freedom the Chinese board houses give you for contour milling etc., PCBs can actually make quite neat and cost-effecive front panels.It's not 'final' yet, as you guessed -- I just added a USB port as an alternative to the RS-232. Just the jack and three resistors, with the USB protocol and transceiver all in the FPGA (thanks to some tips from this forum!).

author: dnotq
author_rank: Contributor
timestamp: August 24, 2017, 03:56:19 am
content: I like implementing retro systems like the computers in coin-op video game and classic home computers. CPUs are very interesting to me right now, as well as video generation and implementing hardware support for for video operations. I have done a TMS9900 core and I'm working on a rewrite based on microcode (the first one has hard-coded control logic). I started looking into doing some of the 8-bit CPUs (Z80, 6809, 6502, etc.) but the instruction decode on those is rather overwhelming when you start getting into the details, so I put those projects on hold for now. I have also done an FPGA version of the TMS-9918A VDP, details here:http://codehackcreate.com/archives/30I did the the initial development on a Spartan3e devboard, and used the same FPGA on the final board. I have since accumulated many FPGA devboards with Spartan6 FPGAs and Zynq SoCs. It seems VGA output is no longer acceptable, so I have to step-up my game and learn to generate HDMI video.I would like to work on a project to make an FPGA-based computer that could be a serious computer system, i.e. usable for personal information security, programming, graphics, games, sharing code and programs, and communication.

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2017, 07:19:23 am
content: Quote from: dnotq on August 24, 2017, 03:56:19 amLike an fpga-based laptop? Or what?

author: rstofer
author_rank: Super Contributor
timestamp: August 24, 2017, 12:52:36 pm
content: Quote from: dnotq on August 24, 2017, 03:56:19 amOver at OpenCores.org there is a project named T80 which implements a Z80 CPU. The Z80 is a really complicated design but the core works well.I have one instance where I use the core along with some peripherals like a Compact Flash to run the old CP/M 2.0 Operating System. It runs pretty fast at 50 MHz and would be suitable for a lot of projects. A little power hungry so I wouldn't be looking at battery power.I have another incantation that replicates the game board for PacMan. One of these days I'm going to build the bar table version.There are many other CPU cores at OpenCores.One of the most complete projects in terms of documentation and tools is LC3. I haven't found an HDL version so I am working on one but the OS, assembler and C compiler are available.Google is your friend but here's a start:https://en.wikipedia.org/wiki/LC-3Even though the project is well described, it doesn't translate directly to HDL. There are a couple of MUXen missing but you'll spot that when you start writing the code. There may be other solutions to the issue but that's the way I solved it.I like the LC3 project because it is well documented and the architecture is really easy to understand. There is even a flow chart of the steps required by each instruction. Very well documented!

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2017, 01:22:34 pm
content: judging on my personal experience with OpenCores I woudln't suggest it as reference for beginners since it teaches the wrong way, e.g. too often the code is full of magic functions auto-magically instantiated by Altera's tool.

author: brucehoult
author_rank: Super Contributor
timestamp: August 24, 2017, 01:53:04 pm
content: As with many others, I'm interested in implementing historic CPUs and playing with new instructions for modern processors (e.g. RISCV).I've done quite a lot with software emulation on PCs, but having it in "hardware" is attractive because then you can put it on a small PCB/breadboard.Sadly, it's fairly trivial to implement most instruction sets in QEMU so they run at a billion instructions per second on an i3, which is not going to happen on an FPGA. On the other hand, if you want to play with special instructions that are completely different to what is in C or an x86 then FPGA can be faster.

author: Cerebus
author_rank: Super Contributor
timestamp: August 24, 2017, 02:33:52 pm
content: Current project is the controller for a multislope ADC and I've been trying to get back to writing the Verilog for it for the past few days. I just keep getting interrupted by other things - the GTKwave window with the output from the first cut of the core of it has been sitting staring at me from my second monitor since Monday.Once that's done and dusted and on a PCB of its own, I might re-purpose the dev board to trying to spin up the CPU design I wrote, as a way of teaching myself Verilog, a few years back. At the time I only had simulation tools, and no synthesis tools or hardware to try it on 'for real'.

author: rstofer
author_rank: Super Contributor
timestamp: August 24, 2017, 03:04:02 pm
content: Quote from: legacy on August 24, 2017, 01:22:34 pmThe T80 core is quite good and well presented. It is excellent.As to the rest, they are a start. Sometimes good, sometimes not so good. I'm just not aware of any other repository for HDL. There are individual projects out there but they will almost always be hardware specific if they are somebody's project.Finding high quality code for significant projects isn't all that easy.

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2017, 03:08:32 pm
content: Quote from: brucehoult on August 24, 2017, 01:53:04 pmwhich kind of instructions? something like the Altivec (PowerPC-G4)?Vectorial CoPro? BKM-like? Hash-accelerators (crypto-Cops)?large (64bit or 128bit) FixedPoing engine? with CooRdic support?or what?

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2017, 03:35:58 pm
content: Quote from: rstofer on August 24, 2017, 03:04:02 pmThe same applies to OpenCores, if you look as some projects you find that they are ALTERA specif, written with mega-functions, and poor VHDL quality.Editcut.

author: ebastler
author_rank: Super Contributor
timestamp: August 24, 2017, 03:46:48 pm
content: Bad day?

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2017, 03:57:59 pm
content: LOL, theDNX_RISCis funnyit looks similar to the first MIPS processor (R2K), even simpler, instructions are 32 bits long, it's a classic RISC load/store machine, the branch unit is simplified, and it comes with a simulator which implements the pipelined-version (won't be surprised to see some multi-cycles implementation in VHDL)EscapeSimulatorWOW! I haven't checked for any HDL code, but though it's good material for students

author: brucehoult
author_rank: Super Contributor
timestamp: August 24, 2017, 04:03:33 pm
content: Quote from: legacy on August 24, 2017, 03:08:32 pmThose all seem like possible examples. Or "tensors" for ML. Or texture sampling/averaging for graphics. Even something as simple as bitreverse or Count Leading Zeroes if the target CPU doesn't have it.

author: rstofer
author_rank: Super Contributor
timestamp: August 24, 2017, 04:29:31 pm
content: Quote from: legacy on August 24, 2017, 03:35:58 pmSo, what's the alternative for a newcomer? They need something to help them climb the hill and most of what I see in other forums are just bits and pieces.Where does the newcomer find a complete project, fully documented, that is understandable? Personally, I have no idea!My very first project hung a Compact Flash on that T80 core and got CP/M running. First I blinked an LED and then I brought up a CPU with OS. Not because I had any experience, it's because the T80 is easy to work with. I looked at the top level long enough to figure out how to add the IO devices and I was off to the races. I never had to look at the internals, they just do what they are supposed to do. In fact, I never have. I glanced through the code one time and decided to put that on back burner. To be fair, I had a great deal of experience bringing up real systems using the 8085 so I pretty much new what was required.There are plenty of tutorials that show how to implement a gate, MUX, decoder and even FSMs but there is a huge step to the level of tying these blocks together to create something interesting. Even a simple CPU will be a few hundred lines of code.

author: stmdude
author_rank: Frequent Contributor
timestamp: August 24, 2017, 04:31:38 pm
content: Quote from: legacy on August 24, 2017, 04:20:53 pmI run the same distro as you, and I solved that particular issue by giving them binaries linked against a recent version of libavcodec..Them: "It won't run!"Me: "Give it a year or two, and once Ubuntu catches up, it'll work"Anyhow. Back on topic. I'm just a beginner, and I was planning on building old home-computers, but in a single FPGA.I got some soft-cores working, RAM, ROM, IO chips, etc.However, I kind of got tired of it when I wanted to test stuff together with the old hardware, and came to the realization that 5V FPGAs are pure unobtanium these days.But, it's another (powerful) tool in my toolbox, so I'm glad I learned it. I'm sure I'll make more projects later, but right now it's stalled.

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: August 24, 2017, 04:43:20 pm
content: Quote from: legacy on August 24, 2017, 03:35:58 pmDisgusting. You should demand a refund.Oh wait..."OpenCores is a community that enables engineers to develop open source hardware, with a similar ethos to thefree softwaremovement... There is no formal affiliation between the people contribute to OpenCores.... All kinds of people: Students, HW Professionals, SW Professionals, Companies, Hobby engineers,"

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2017, 04:53:49 pm
content: Quote from: stmdude on August 24, 2017, 04:31:38 pmI can't do that, they are the kind of customer whose software MUST come from Catalyst, compiled from sources, and has to come to them with some hardening-rule set applied.

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2017, 04:56:21 pm
content: Quote from: rstofer on August 24, 2017, 04:29:31 pma good university course, plus a good book with a mixture of theory and practice!

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2017, 05:03:11 pm
content: Quote from: brucehoult on August 24, 2017, 04:03:33 pmNot yet 100% stable on HDL, this is a BKM-like algorithm simulated in fixedpoint-32bitA tensor unit is much more interesting, but ... can you believe that I have been working on the BKM-like algorithm for 5 years? And it's still unstable for certain input values.I mean, they sounds as "long story projects"About texturing .... SGIInfinite Realityseems to be a very interesting piece of hardware. Might be replicated on HDL? I don't know, for sure it's damn complex for common human beings, but SGI engineers did it in 2000s when there were no modern FPGA and tools costed an arm and a leg.I believe that at least it's good material to for a lecture, something that one would like to understood in details (may be also replicated in some part).There was a good paper on internet,I can't find it at the moment, but I will link it to the forum as soon as I find itedit:found and attached! enjoy

author: brucehoult
author_rank: Super Contributor
timestamp: August 24, 2017, 05:22:41 pm
content: Quote from: legacy on August 24, 2017, 03:57:59 pmDLX has been around for a long time. It was designed by Hennessy (original MIPS designer) and Patterson (original RISC1/2/SPARC designer) for use in teaching and their famous hardware design book " Computer Architecture: A Quantitative Approach".DLX is also the basis for "OpenRISC", the first open source CPU core which is unfortunately (for commercial users) GPL.RISC-V is also inspired by MIPS2000 and DLX, but with aims to have a more liberal license, to support 64 bit (and 128 bit), to leave a large amount of opcode room for future extensions for architecture research or commercial users, and to support variable length instructions for more compact code and to (again) leave lots of room for future extensions.

author: rstofer
author_rank: Super Contributor
timestamp: August 24, 2017, 07:47:19 pm
content: Quote from: legacy on August 24, 2017, 04:56:21 pmWhich probably leaves out the hobbyist.FPGAs would, I suspect, be an upper division course at the undergrad level and a course unto themselves in grad school.I have 2 pretty good books but only one is directly aimed at FPGAs and that is "Microprocessor Design Using Verilog HDL". The other is Patterson and Hennessy and it's very good. I have a copy of Patt and Patel incoming. I also have a raft of other computer architecture books and they could all result in a project but they don't provide any hand-holding in that direction. And they target very high end processors because that's where all the excitement it. I could still see a project coming out of Caxton C Foster's BLUE computer. An extremely simple CPU similar to very early minicomputers.

author: NorthGuy
author_rank: Super Contributor
timestamp: August 24, 2017, 09:43:39 pm
content: FPGA structure is very different from the structure used to build real-life CPUs.FPGA mostly consists of interconnected LUTs and FFs. In modern FPGAs, such as Xilinx 7 series, LUTs are very polymorphic - the same LUT can be used as a couple of logic gates, or as 64-bit RAM, or as 32-bit shift register, or as 4:2 MUX etc. Such elements are quite powerful and you can create much more efficient core if your design uses the polymorphic power of LUTs. Not to mention built-in carry chains to build adders and multipliers, or DSP blocks which can add and multiply really fast.On the other hand, some things which are easy in the real world, are not that easy in FPGA. For example, a physical CPU may have a bus which may be driven by a number of sources - active source drives the bus while the rest is tri-stated. If you want to emulate such a bus in FPGA, you'll have to use a huge MUX which selects the driver out of the list of all possible drives.

author: rstofer
author_rank: Super Contributor
timestamp: August 24, 2017, 11:11:40 pm
content: And yet an entire minicomputer including emulations of its peripherals can easily fit in a single FPGA. A machine that could fill a small room will fit in a chip about the size of a postage stamp. Sure there is a really wide MUX and it will necessarily limit speed but in terms of emulating older CPUs, the FPGA will outrun the original by at least an order of magnitude. The T80 core runs at 50 MHz and the original Z80 only 6, the 8080 only 2. The real IBM1130 had a 400 kHz clock, my version runs at 50 MHz - 125x and when I port it to the Nexys2_DDR, I am hoping for 100 MHz - 250x. That 27 pass Fortran compiler will RIP!For practical implementations of historically significant CPUs, a single FPGA will probably perform quite well. I have often wondered how many FPGAs is would take to emulate the largest IBM360 or one of the Control Data machines (eg 6400). At least in terms of the CDC machine, with no software out in the wild, the project wouldn't be worth doing. I'm pretty sure some of IBMs code is available for license (free, I believe). I see there are some 360/30 projects out there.No, it won't keep up with a multi-GHz x64.That really wide MUX is a PITA.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: August 25, 2017, 02:01:24 am
content: Quote from: ebastler on August 23, 2017, 04:52:55 pmThat's really cool!

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: August 25, 2017, 02:12:51 am
content: Quote from: rstofer on August 24, 2017, 07:47:19 pmThis is a pretty good book and easy to follow. It was written by the guy who designed the Rabbit micros, so he knows what he's talking about.https://www.amazon.com/Microprocessor-Design-Using-Verilog-HDL/dp/0963013351https://www.digi.com/products/rabbitprocessor

author: dnotq
author_rank: Contributor
timestamp: August 25, 2017, 05:09:47 am
content: Quote from: rstofer on August 24, 2017, 04:29:31 pmThis book is the book that did it for me:https://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/0470185317/I also really like this book too:https://www.amazon.com/Digital-Design-Computer-Architecture-Second/dp/0123944244/It gives VHDL and Verilog examples side-by-side, which really helps for learning.However, I'm a self-learner and my interests and curiosity are what drive me. I have found most other people need to be told "ok, now it's time to learn xyz" in a classroom setting before they will even consider the possibility of learning something new.

author: dnotq
author_rank: Contributor
timestamp: August 25, 2017, 05:54:19 am
content: Quote from: legacy on August 24, 2017, 07:19:23 amKind of. Something portable and accessible for sure, but big enough to have a keyboard and a screen. I really like the form-factor of the Ello 2M:https://www.crowdsupply.com/yellow-beak-computer/ello-2mI'm just really sick of the state of computers today. It is getting to the point where you can't even trust the hardware in your computer, you have no idea what is going on with the OS, the barrier to creating software is very high, "programming" these days seems to be slapping poorly written libraries together, the "future" is perceived to be in the "browser" (which is the worse software development environment humans ever came up with), etc. blah blah blah.Hell, I have been programming assembly since 1983 and I can't even say for sure that my Windows 10 computer has not been compromised in some way. I have no interest in spending all my time "maintaining" my computer. I want to use it, play around, write code, share programs with others without worrying that my computer will be compromised, communicate confidentially, and just feel confident that I can trust my computer.Also, computers a 1000 times faster than the systems I grew up with, so why is it that they are slower to start-up and I'm still waiting on the computer to do things?? All actions on a computer these days should be freaking *instant* from the user's perspective! I don't need the cursor to animate between characters when I'm typing, enough already!Hell, my TI-99/4A boots faster (instant on) and is more responsive than my modern 3GHz desktop computer. Seconds after powering on a classic computer you could be programming, and that is *very* powerful! No other systems are like that today, and I can't figure out why we lost that ability. Even the Rpi fails to provide a decent environment (it boots into Linux for crying out loud!) What a pain in the ass. And if you try to kick Linux out and build your own OS on the Rpi, you lose access to the video parts since they are proprietary.Now that you can't even buy a CPU that does not spy on you, I figure the only way to really get a system that you can trust, that is easy to use, and that does not have all the cruft of the x86 architecture, is to just build the system from the ground up. Not what I would like to be doing for sure, but I thought we (the collective "we" that make up the technology world) would have created better systems by now...I have some CPU architecture ideas that I would like to experiment with, as well as a basic system design. Some of the basic parts would be an FPGA for the CPU, something reasonable like a Spartan 6 LX16 or LX25. Another FPGA for a graphics subsystem and sound, and maybe something like an ARM for controlling interfaces like storage, USB, network, etc. The CPU would clock around 200MHz, and the whole system would be balanced, i.e. the memory subsystem would be as fast as the CPU, network, storage, etc.This is nothing over-the-top and would be cheap enough that it would be affordable to justify getting one to mess around with. Anyway, that is the quick rant about it. Any takers? ;-)

author: stmdude
author_rank: Frequent Contributor
timestamp: August 25, 2017, 07:30:36 am
content: Quote from: dnotq on August 25, 2017, 05:54:19 amMy current plan-of-attack for this is to buy this:https://www.olimex.com/Products/DIY-Laptop/Then, throw out the mainboard, and replace it with something like a Zynq.Why that laptop, and not some other random one? Well, this one comes with schematics and PCB design files, so I can keep the pinouts, board outlines and such to make my life a bit easier.

author: legacy
author_rank: Super Contributor
timestamp: August 25, 2017, 12:33:58 pm
content: Quote from: stmdude on August 25, 2017, 07:30:36 amSo, linux on Zync's ARM core, and fpga used for VDU and keyboard controller stuff.InterestingHere I have reversed the keyboard matrix of a laptop, and designed a matrix keyboard controller.A customer want to integrate the keyboard controller inside an fpga of his PCB, and I had to develop the RTL part.Now I can re-use the sub-project. In some way, as well as I can re-use a VDU sun-project. It's text only, something like VT220.

author: legacy
author_rank: Super Contributor
timestamp: August 25, 2017, 12:55:37 pm
content: Quote from: NorthGuy on August 24, 2017, 09:43:39 pmThat is a common mistake that I have seen in projects around: internally to the CPU inside the fpga, instead being mux-driven to/from devices they wanted to use ... INOUT coupled to tri-statesas well as when I was shocked to see that someone wanted to justify the use of 'Z' to express on the timing VCD diagram when signals are not-valid

author: legacy
author_rank: Super Contributor
timestamp: August 25, 2017, 01:00:53 pm
content: Quote from: dnotq on August 25, 2017, 05:54:19 amYup, good idea!

author: b_force
author_rank: Super Contributor
timestamp: August 25, 2017, 01:05:28 pm
content: I am actually looking for some minimal option (mostly price) to build something like an audio DSP type like thing with some ADCs.Anyone suggestions (needs to be as cheap as possible for a customer)?

author: legacy
author_rank: Super Contributor
timestamp: August 25, 2017, 01:36:36 pm
content: Quote from: dnotq on August 25, 2017, 05:09:47 amYup, good books, I have a paper copy of both, and I bought en ebook of the second one.Oh, an other good good book is: Real World FPGA Design With Verilog.It's Verilog-only oriented, but it talks about ASIC pointing out a lot of interesting things and best practices. It's a bit old and all the software in the CD is pretty useless because we have Icarus nowadays, but it looks very interesting to me. I found a copy on Ebay for 5 euro + postage.

author: rstofer
author_rank: Super Contributor
timestamp: August 25, 2017, 01:59:44 pm
content: Quote from: dnotq on August 25, 2017, 05:09:47 amI ordered the 2d book "Digital Design..." - building a MIPS processor seems like a worthy goal. The first book is a little pricey for my tastes. Still pretty pricey at Alibris too...Pong Chu has also written "RTL Hardware Design Using VHDL...", again, pretty expensive. I have this book and it's excellent.I think I am more interested in books that present a project.Now, if someone would upgrade the Spartan 3 book to Artix with Vivado, I'd be all in to order today. Just the Vivado topic would take volumes! That's an amazing tool once you have enough computer horsepower to use it. Attention span foreshortens with age.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: August 25, 2017, 02:51:14 pm
content: Quote from: dnotq on August 25, 2017, 05:54:19 amDepends on how the machine is put together. I recently built a new machine with an AMD Ryzen CPU and an M.2 NVME SSD as the system disk. This system gets to the Windows 10 login screen six seconds after pressing the power button. Once booted, the machine is very fast and responsive with no perceptible lag when doing any typical task.

author: rstofer
author_rank: Super Contributor
timestamp: August 25, 2017, 03:07:04 pm
content: Quote from: Sal Ammoniac on August 25, 2017, 02:51:14 pmOn my new machine, it isn't Win10 boot that takes time, it's the BIOS. Actual boot of Win 10 is just a couple of seconds from the splash screen to the login screen.The I7 7700K and a very fast M.2 SSD make all the difference. I looked at one of the high end Ryzen CPUs and they looked really good. Unfortunately, Vivado won't use more than 8 threads and, more often than not, it won't use more than 2. Having a multi-chip bazillion thread Xeon machine (floor heater) won't help. At least for the WebPack version.In any event, my simple LC3 project times something like: 55 seconds to synthesize, 55 seconds to implement and 10 seconds to write the bit file. Two minutes is an enormous improvement - even if the project is only about 1000 lines of code. In the bad old days of slower machines, I had a project that took 20 minutes to run ISE. I can't imagine what it would have taken for Vivado.Speed is good! How fast can you afford to go?

author: dnotq
author_rank: Contributor
timestamp: August 26, 2017, 03:20:03 am
content: Quote from: rstofer on August 25, 2017, 01:59:44 pmI also have that book, and yes it is excellent just like his FPGA Prototyping By VHDL Examples book. However, IMO the RTL Hardware Design book should be read once you have a good handle on working with FPGAs, since it is very heavy in HDL analysis rather than making things.Quote from: rstofer on August 25, 2017, 01:59:44 pmThat's why I suggested Pong's FPGA Prototyping By VHDL Examples book. He even wrote a version for Verilog if that is your thing. It is expensive, but worth it IMO, and it is very project oriented. Pong gives you enough information about a topic, then takes you through projects that demonstrate the topic being learned. It starts off with some projects like PWM LED control, shifting techniques, from FSM introductions, etc. Then he moves into chapters that show how to make a working UART, PS2 Keyboard an mouse interface, external SRAM controller, VGA controller, then ties it all together by implementing a PONG game. At the end of the book he shows how to work with a Xilinx PicoBlaze core.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: August 26, 2017, 07:49:03 am
content: Quote from: rstofer on August 25, 2017, 03:07:04 pmThere are usually BIOS settings to make the startup complete quicker. Often it's just sitting there for a few seconds waiting for you to hit DEL or F2 to get into BIOS setup.QuoteEventually companies like Xilinx will realize they're in the business of selling chips, not software, and this nonsense will go away.

author: legacy
author_rank: Super Contributor
timestamp: August 26, 2017, 09:28:04 am
content: Quote from: Sal Ammoniac on August 26, 2017, 07:49:03 amEventually, next time he will come down town, Santa Claus will probably give you a basket of coal!Even Santa knows that that Software like Cadence Allegro costs more money than a flat just in license, while ISE and Vivado having being been released as Xmas gift, you can download them, and use them in a features-reduced version without paying a penny.Thus, it's like you're pissing on Santa's shoes as your personal complaining that you want more feature in the gift that he is giving you.Does it make sense? Sure, cold winter, have a basket of coal

author: legacy
author_rank: Super Contributor
timestamp: August 26, 2017, 02:49:22 pm
content: Ups.thisis the book I was talking about.

author: rstofer
author_rank: Super Contributor
timestamp: August 26, 2017, 02:50:26 pm
content: Quote from: dnotq on August 26, 2017, 03:20:03 amIn the spectrum of things FPGA, I don't know where I sit. While I can code up anything I am likely to need, I am certain there are 'better' ways to do it. 'Better' is subjective but that's the kind of thing I am looking for. I want to see how others have done a complete project. How they started with an ISA and broke it up into one of more FSMs. Where they used integers, where they used SLVs, why in the world they used variables for anything other than loop counters, that kind of thing.There's a lot of bitching on the Internet about projects that are 100% SLVs but when you pick up a bit of code off the Internet, sure enough, it is all SLVs. And I'm not about to start a religious war over unsigned versus SLV but I would like to see what gets synthesized. I don't care a bit about how it gets simulated, simulation isn't hardware and the only thing I care about is hardware.I spent some time with the RTL Schematic view in ISE. I haven't tumbled to that feature in Vivado. But ISE is good enough to see how the circuits differ. And, if they don't differ, then the whole discussion is Ford versus Chevy. Because what gets implemented is SLVs. Hardware better not be anything else.I guess it is this corner of the HDL sandbox that interests me. The stuff at the margins. I already know how to create all the building blocks in several different ways and I have several very good books to help. But it is always interesting to see how someone else does things from beginning to end.

author: rstofer
author_rank: Super Contributor
timestamp: August 26, 2017, 03:09:11 pm
content: Quote from: legacy on August 26, 2017, 02:49:22 pmI ordered a used copy from Amazon, it'll be here Monday. I have next to no interest in ASICs or silicon, I'm long retired! Nothing I build will be of any interest to anybody.I have been wanting to learn more about Verilog. I just don't 'get it' so maybe this will broaden my horizons. It's kind of like wanting to learn COBOL after programming business applications in FORTRAN. You get the same answers but the code looks a lot different! And just when you think you have a handle on things, along comes PL/I.It still gets down to patterns. A MUX is coded this way, an FSM like this. Learn the patterns and just link blocks together.

author: rstofer
author_rank: Super Contributor
timestamp: August 26, 2017, 03:21:01 pm
content: Quote from: Sal Ammoniac on August 26, 2017, 07:49:03 amThat is true, I can set the BIOS for fast boot. Since I only boot once a day and it takes perhaps 15 seconds, I just don't care enough to wade through the BIOS menus looking for the option. And, yes, it is in the User Manual. Just not something I care about.QuoteI'm not sure that the 'for pay' version uses any more threads than the WebPack. When I researched the answer, the limitation didn't say anything about WebPack versus 'for pay'.It's taken me a while but I'm finally getting to enjoy Vivado. Not that I'll ever get away from ISE, I have too many Spartan 3 boards.

author: legacy
author_rank: Super Contributor
timestamp: August 26, 2017, 04:03:53 pm
content: Quote from: rstofer on August 26, 2017, 03:21:01 pmI remember something about ISE v10.1-v14.7, anyway I can confirm you that there is an huge difference between the WEBPack and the FULL license version.We have a couple of copies at work, they don't have any limitation on usable threads, and the same software on the hardware with the same project gives you results in different times and it depends on having the license enabled/disabled.Last time I wanted to check:License Valid & License Enabled -> extremely fast on large projects, no matter how much complex the project goesNo license | no Valid License | License Disabled -> time results depend on the project's complexitya) -> largely slow on large projects!b) -> lightly slow on simple small projects (<1000 lines)!Sonata Simili and Sigasi have the same behavior: the free license is limited and slower by several orders of magnitude when the project is large and doesn't use threads.We don't use VivadoBy the way, consider yourself "lucky" of having the free WebPack, some UNIX solutions don't come with any free version and you have to pay for the license, otherwise the program doesn't run at all. Oh, and the licence is something like 20-50K euro per year!edit: p.s.on old Altera tools there was a trick: if you agreed with "I want to give statistic(1) back to Altera" they give you a bonus acceleration. It is an hidden button to be clicked and a some lines to read and to agree. I don't remember precisely where what etc.(1) I just remember that it was like: which chip you mainly use? how many lines of code? VHDL or VERILOG? which is the used simulator? External? Internal? how many magic functions got used? how many IP? which IP? etc ...

author: legacy
author_rank: Super Contributor
timestamp: August 26, 2017, 04:18:36 pm
content: back to the topic, I am still trying to improve the division algorithm(and it is still too slow)

author: rstofer
author_rank: Super Contributor
timestamp: August 26, 2017, 04:34:50 pm
content: Quote from: legacy on August 26, 2017, 04:03:53 pmIf it wasn't for free tools, I couldn't play with FPGAs at all. I never look a gift horse in the mouth. I'm totally pleased with both ISE and Vivado. I haven't used it much but the free Altera Quartus tool seems to work pretty well and I have installed the Lattice tools but haven't got around to using them.Free is good! Even if Xilinx does collect usage information from WebPack users.I think there will always be a requirement for a 'student' edition and it will probably be free or very close to free. The manufacturers need to get students locked into their devices as early as possible.

author: legacy
author_rank: Super Contributor
timestamp: August 26, 2017, 05:17:39 pm
content: Quote from: rstofer on August 26, 2017, 04:34:50 pmIt's obnoxiously irritating when Xilinx/Altera/whoever releases something for free with some feature limited (e.g. threads) and people complain that they want *ALL* for free!This is always the point! You give them a thumb, they want the the whole armSome time ago I read about people who wanted ISE's source code in order to recompile it on their Linux/ARM (tablet? SBC? does it make sense?) so they can -1- remove limitations and -2- run the binary on modern OSsThought: are they kidding?No, they were serious! They actually believed that it was a reasonable question, probably because they believe that "since Xilinx sells chip, then the software MUST be OpenSource"OMG too much OpenSource has given them a mind-bug

author: NorthGuy
author_rank: Super Contributor
timestamp: August 26, 2017, 05:41:15 pm
content: I don't think the "paid for" Vivado is any faster than WebPack. If it was, Xilinx wouldn't keep this in secret.If you're using small Artix-es, Vivado may look expensive.If you're forking over $20K for fast Virtex, paying for Vivado is peanuts.

author: rstofer
author_rank: Super Contributor
timestamp: August 26, 2017, 06:06:41 pm
content: Quote from: NorthGuy on August 26, 2017, 05:41:15 pmI guess it depends on who is paying for it. Us pensioners have to watch how we spend money!I don't care if the WebPack is slowed, I've got nothing but time. No deadlines, no commitments, just mental exercise.

author: brucehoult
author_rank: Super Contributor
timestamp: August 26, 2017, 06:07:21 pm
content: Quote from: legacy on August 26, 2017, 05:17:39 pmOpenSource is a bit far, since it would help other FPGA manufacturers.I can't see what use Vivado is is you don't use Xilinx FPGAs though. I guess you could just use it for simulation. But they would not sell one FPGA fewer if unrestricted Vivado was free, and they might sell a lot more.Apple was charging for MacOS updates for a while, but eventually they understood it's far less hassle for support if everyone is on the same version, and the Mac and iPhone hardware sales is where the money is.

author: hamster_nz
author_rank: Super Contributor
timestamp: August 26, 2017, 07:40:22 pm
content: Quote from: brucehoult on August 26, 2017, 06:07:21 pmI think it might be caused by accounting practice. If a company spends a lot of time investing money into building something (e.g. Vivado), then the have a big asset on the books, and have a business unit to support and develop it. And if they have this asset they have to work out how it make return on that investment. After all, if they didn't develop the tools themselves, they would need to license the tools from somebody else for $$$So saying that this big multi-million $ asset has has no commercial value and giving it away for free sounds wrong, I assume in America the directors could be sued by shareholders for not maximizing profit. It also sounds wrong to load up the prices of the chips to allow the chip-making part of the business pay for it - the tools are not really involved in manufacturing the silicon (they would use very expensive licensed ASIC tools for their design work).Giving the tools away for free most likely looks like "not in the shareholders best interest" when you have what looks to be a somewhat profitable development & support business units.

author: brucehoult
author_rank: Super Contributor
timestamp: August 26, 2017, 08:44:44 pm
content: Quote from: hamster_nz on August 26, 2017, 07:40:22 pmSometimes accountants try to make businesses do all kinds of perverse things. It's the executives job to resist that.If Vivado was an unrelated product to FGPAs then it would be correct to run it as a different profit center, and try to recoup the costs of developing it from software sales.But it's not. If they didn't have Vivado (whether developed in-house or bought in) they would sell a big fat *zero* FPGAs. Having the software is a cost of being in the FPGA business. It simply can't be accounted separately.

author: NorthGuy
author_rank: Super Contributor
timestamp: August 26, 2017, 08:53:38 pm
content: Quote from: hamster_nz on August 26, 2017, 07:40:22 pmPure non-sense. They also spent lots of money developing assets for advertising campaigns. Would you say they now need to work on the way to sell their ads instead of showing them for free?They wouldn't sell any of the chips, IPs etc. if they didn't have tools. Similarly, they wouldn't sell anything if they didn't have buildings, tables, printers and other stuff. These all are assets which do not bring any direct revenue (and quietly depreciate over time). The goal of these assets is to support sales of the chips. The revenue they get from selling Vivado is insignificant. "High" price is simply a method to pump-up the perceived value of their software.If Vivado was owned by a separate company where it was the sole revenue source, the price, representation, everything would be different. For example, Xilinx would have to pay a lot for using the Vivado software as a venue for selling IPs, which would be a nice revenue source for Vivado company.

author: Cerebus
author_rank: Super Contributor
timestamp: August 26, 2017, 10:07:23 pm
content: Quote from: NorthGuy on August 26, 2017, 08:53:38 pmIt's not even that, it's almost pure classical "rent-seeking".

author: joeqsmith
author_rank: Super Contributor
timestamp: August 27, 2017, 04:30:36 am
content: Quote from: legacy on August 21, 2017, 03:33:19 pmThe last larger home project was my HIL simulator for one of my bikes. Basically everything is done in the FPGA from simulating the sensors to reading the fuel and timing information.

author: legacy
author_rank: Super Contributor
timestamp: August 27, 2017, 07:23:13 am
content: Quote from: joeqsmith on August 27, 2017, 04:30:36 amHIL stands for hardware in the loop. Right?Does the timing information come from the combustion engine?Interesting project

author: joeqsmith
author_rank: Super Contributor
timestamp: August 27, 2017, 05:27:41 pm
content: Quote from: legacy on August 27, 2017, 07:23:13 amSorry, yes Hardware In the Loop. There is a engine, vehicle model running on the PC. The actual ECM (Engine Control Module) plugs into the simulator. The idea then is the ECM thinks it is running on the real vehicle. The ECM controls the fuel and ignition timing. The FPGA decodes this information and passes to the engine model. Likewise, the models then passes information back to the FPGA.Sorry but due to some background music, YT flagged most of my videos of it. This is a fairly old video but gives some idea how it works. The simulator today has no C code at all. Everything is done in LabVIEW including the interrupt (event) handler. I bought a new PC and it was just so fast, it needed something to do....

author: legacy
author_rank: Super Contributor
timestamp: August 27, 2017, 05:35:48 pm
content: WOW impressed

author: joeqsmith
author_rank: Super Contributor
timestamp: August 27, 2017, 05:51:21 pm
content: Quote from: legacy on August 27, 2017, 05:35:48 pmThere is a technical side playing behind a keyboard which I enjoy but nothing beats putting things into practice.

author: legacy
author_rank: Super Contributor
timestamp: September 20, 2017, 12:14:36 pm
content: Quote from: joeqsmith on August 27, 2017, 05:51:21 pmYou! You do a lot of interesting stuff, man

author: legacy
author_rank: Super Contributor
timestamp: September 20, 2017, 12:27:46 pm
content: Currently I am trying to design a simplified bus intended to let the parts of a SoC communicate with each other. The aim is to allow the connection of differing cores and devices to each other inside of a SoC.In the above picture I am more focused on auto-negotiating sub cycles when data trasfers are misalignment, as well as wait states dynamically inferred on the need.No doubt theWISHBONEbus is light years ahead better, but it's too complex for my purposes

author: brucehoult
author_rank: Super Contributor
timestamp: September 20, 2017, 12:52:43 pm
content: hoplite looks good if you have something between dozens and thousands of things communicating within one FPGA.http://fpga.org/hoplite/

author: legacy
author_rank: Super Contributor
timestamp: September 20, 2017, 03:03:47 pm
content: This is the best I am willing to do

author: Mr. Scram
author_rank: Super Contributor
timestamp: September 20, 2017, 03:31:01 pm
content: Quote from: joeqsmith on August 27, 2017, 05:27:41 pmIt's these kinds of posts that make me feel I'm a useless slob that's wasting its life. This, plus the multimeter videos and probably a real career too.

author: gary_01
author_rank: Newbie
timestamp: September 21, 2017, 10:47:42 pm
content: I've only just started learning about FPGAs and using VHDL (a couple of month now). I have an interest in retro computing and arcade machines which led to me buying the FPGA Replay and working on implementing the Acorn Electron with it.The project is nearly to the point I can load games now. Just a cassette interface and sound to go.I've writtenseveral blog postsabout it and the mistakes made along the way

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: September 22, 2017, 12:06:02 am
content: Quote from: gary_01 on September 21, 2017, 10:47:42 pmThat's pretty impressive for someone who only started learning FPGAs a few months ago.

author: joeqsmith
author_rank: Super Contributor
timestamp: September 22, 2017, 01:48:23 am
content: Quote from: Mr. Scram on September 20, 2017, 03:31:01 pmSorry about that. But thanks, I think..