Impedance Matching tolerances in question - Freelancer delivered gerbers - Page 1
Forum section: electronics / general

author: phaseform
author_rank: Regular Contributor
timestamp: May 31, 2020, 09:37:37 am
content: I have just received a reply from JLCPCB saying " the impedance control we don't produce the special impedance lines ！"... So I asked a free lancer to build me up a PCB with some required impedance matching, I sent his gerbers of to JLC and that ^ is the part of the response from JLC I don't understand. The gerbers in question have this text at the top:Is this simply a case that JLC cannotprovidethe required tolerances (Qs 14 and 15)?.. Are these notes totally required or superfluous in any way (re impedance matching)?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 31, 2020, 04:13:04 pm
content: 10% impedance? Geez, special order that from a US manufacturer, that's tight as PCBs go, especially in FR-4.Tim

author: Siwastaja
author_rank: Super Contributor
timestamp: May 31, 2020, 05:18:58 pm
content: Is this a space rocket or what?If not, it surely sounds like a copy-paste specification to sound fancy, i.e., overengineering. (Just guessing. But maybe itisa space rocket!)With that level of specification, maybe the choice of JLCPCB isn't the right one? If there is a reason for all this, maybe ask the designer's opinion where to manufacture it?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 31, 2020, 08:55:00 pm
content: Quote from: Siwastaja on May 31, 2020, 05:18:58 pmHahaha.... I mean, it AIN'T gonna be ITAR approved if it's from JLC, that's for damn sure.This is a very good point, by the way: shopping at JLC implies cheaping out to the maximum possible degree on the finished product. Not to say it simply won't work at all; but... if that spec is in there for good reason, maybe it won't? You went to the trouble of hiring a designer for it, a substantial expense; if that money was well spent, then this would seem like the very last place you want to cheap out on!Tim

author: Gribo
author_rank: Frequent Contributor
timestamp: May 31, 2020, 09:22:59 pm
content: Let me guess, USB (90) and Ethernet? (100) FR4 dielectric constant is anywhere from 3.5 to 4.8, it is affected by temperature, humidity and the phase of the moon. Good luck with that requirement.

author: phaseform
author_rank: Regular Contributor
timestamp: June 01, 2020, 01:23:34 am
content: Thankyou for the clarifications, that was my thought exactly when I read it, that the PCB designer (who in fact appears to be subcontracted from my 'highly rated engineer' designer) had just usedQuote from: Siwastaja on May 31, 2020, 05:18:58 pmwhich bugs me, because it confuses the PCB manufacturer (as has happened). I have asked my designer to clarify, and he sent me a word document to explain.I was really happy with this.. until I read it..I really didnt need a 2 page Wikipedia definition of what a differential line is, thank you... sigh.. I mean this guy (my designer) is claiming to be an engineer that studied in Australia and has written all kinds of device drivers etc... but is struggling (I would say failed) to answer this simple question.. and seems to really struggle with understanding simple question I ask him.. despite asking me to close this contract and that he deserves an excellent review....I didn't pay a huge sum for the schematic and PCB design.. but yeah.. Hopefully his speciality in schematic design yields no significant bugs... 🙏I have asked for a quote from PCBWay, which is looking much higher than JLC..Just looking at the issue in question here (notes 14 and 15 from the gerber) my understanding is that basically we are talking about the tolerances for "Min. Trace width/Spacing"... JLC says 3.5 Mil ashere, this falls within the specs of the gerber notes if I understand correctly..?? (So good to go ahead with this IoT board from JLC..? -regarding advanced requirements has onboard Eth, USB and a PCA9615 I2C differential converter)Oh also JLC said "the min dill holes we can produce for 4-layer boards is 0.2mm, and the min annular ring is 0.13mm" I assume there is no good reason my PCB designer has required such fine tolerances..? - and I should get them to modify the gerbers for something JLC can handle perhaps..?Quote from: Gribo on May 31, 2020, 09:22:59 pmcorrect heh"In our project we need 100Ω characteristic impedance for differential ended signals of LAN8710A, 90Ω characteristic impedance for differential ended signals of from USB connector to USB to UART IC and 50Ω characteristic impedance for single-ended signals is set to meet the signal integrity requirements."I'm just looking at the impedance specs for JLCas here, they have three different Prepreg types with associated Dielectric constants, my designer has said to choose JCL 7628, perhaps this is not so significant..?

author: free_electron
author_rank: Super Contributor
timestamp: June 01, 2020, 02:28:16 am
content: That kind of boilerplate doesn't work.You need to provide an exact stackup ( prepreg and core thicknesses ) and you need to specify what material to use including weave specs.Most of the time this has to be done in reverse : you FIRST approach your board maker by asking them to give you a list of what they stock in terms of materials.Manufacturer , part number and datasheets. Based on that information you create a workable stackup and then you crosscheck with the factory that this stackup is workable. If they sign off then you do the layout.For impedance controlled boards the substrates used become part of the BOM. Just like your capacitors and resistors and other parts.You need to call out : This board uses Isola G200 5 mil prepreg and 42 mil core in a stack of 2 prepregs, 1 core , 2 prepregs. Copper is ED-Jima 18micron Electrolytic copper EDCA-HC with a final plating of 14 micron. Surface treatement is ENIG or ENEPIG at 0.5 micron.You NEED to be accurate when doing impedance control. Everything else is just wafting in the wind. There are thousands of materials and copper foils. ( rolled copper bahvase differently from electroplated copper . if you are going to do very high frequency stuff this becomes important.So it's time ot go yell a bit at your 'star designer' as he clearly has no experience on how this kind of stuff is done..So ,since JLC provides yuo with the stackups and materials they use : run the calculations for 7628 and 2313 and see what works for you r application. You have USB and ethernet so you need 90 ohms for USB and 100 for ethernet.Based on the stackup you can work out the linewidths and clearances needed. Try both stacks to see which one gives you the tightest routing ( based on the density of your board you may want the routing that takes the least amount of room : smallest line width and smallest gap.)Then verify the layout is using that and correct if necessary.Oh, and also verify that differential coupling is maintained fo r the entire run. This is not just impedance control ! this is DIFFERENTIAL impedance control. So it is not just line width that is important. also signal to signal and signal to ground is important ( edge coupling) .And , out of an abundance of caution : check length tuning as well. If your layouter does the hand waving on stackup , he may not take those things that seriously as well...

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 01, 2020, 03:26:01 am
content: Conversely, since it's just digital signals -- particularly if it's lower spec digital (e.g., USB 2.0, 100BASE-T); and the routes are short (a few inches): impedance control doesn't matter very much, and an average proto will do just fine.Layouts can sometimes even be done with absurd lack of impedance control (e.g., 2-layer board with whatever trace width and ground proximity), when the critical lengths are kept very short. (This isn't always possible, in general, but can work out sometimes. Otherwise, the 4-layer board is not much more cost, and very likely to succeed.)If it's a small IoT gadget, it might be a candidate for one of these cases.But this is a call for an engineer to make, and it sounds like, you don't really have the experience to make that call; which is wise. Your contractor(s) may or may not understand this (the above), I don't know. It may also be that you've specified (intentionally or not) that these signals must have the utmost fidelity, performance, whatever; and the best way to strive towards that goal, is the specification in question.Tim

author: JLCPCB Official
author_rank: Regular Contributor
timestamp: June 01, 2020, 07:39:09 am
content: Hi, Our company does not make personalized impedance. If the customer needs impedance, a specific impedance value needs to be calculated in advance with our calculator.

author: phaseform
author_rank: Regular Contributor
timestamp: June 01, 2020, 09:42:27 am
content: I've just asked for the design to be made affordably in the initial criteria..Seems that perhaps PCBWay are accepting the Gerber as is, although have quoted a much higher price (x5) than JLC..Perhaps JLC will be suitable for prototypes... although still there are some issues with JLC capabilities for this design.I noted JLC hasmax 85 Ohmfor outer layer and less for inner... so the design requirements wont fit within their specs.. (So no.. this will not be suitable for space flight) I am wondering about the best way to handle this (assuming I want to go this route and pay 20% of the cost of PCBWay).. set the calculator to 85 Ohm..? (I realise this is a terrible design decision and I'm unsure of how to try optimise a solution within this JLC Stack Up)- misunderstood impedance calculatorI have asked my designer:1. Can we set track width and track space to be as good as possible for the JLC7628 Stackup as per theJLC calculatorhere.2. Is mains voltage on inner layers? Will inner layers be suitable for 10A 240V at 0.0175 mm thickness?3. Also I have asked my designer to make the drill sizes within the tolerance for JLC

author: asmi
author_rank: Super Contributor
timestamp: June 01, 2020, 12:30:56 pm
content: Quote from: phaseform on June 01, 2020, 09:42:27 amThat stackup sucks for controlled impedance, I recommend you to use JLC2313 instead as it allows using sane trace width to achieve commonly required impedances.Quote from: phaseform on June 01, 2020, 09:42:27 amNO.Quote from: phaseform on June 01, 2020, 09:42:27 amSounds like communication issue to me.

author: phaseform
author_rank: Regular Contributor
timestamp: June 01, 2020, 01:15:30 pm
content: hmm, if I set the calculator for 90 Ohm it says JLC2313 can only do 10 - 66 ohm..If JLC can't get close to the impedance requirements perhaps just best to go with PCBWay with space ship tolerances

author: asmi
author_rank: Super Contributor
timestamp: June 01, 2020, 01:23:27 pm
content: Quote from: phaseform on June 01, 2020, 01:15:30 pmDid you check 90 singled-ended or 90 differential?

author: phaseform
author_rank: Regular Contributor
timestamp: June 01, 2020, 01:36:14 pm
content: Aah I think you've done this before

author: free_electron
author_rank: Super Contributor
timestamp: June 01, 2020, 02:03:45 pm
content: JLCPCB even has an on-line calculator ! just plug the numbers. what are you waiting for ?https://cart.jlcpcb.com/impedanceCalculationi also heavily recommend the free Saturn PCB toolkit ! saturnpcb.com

author: phaseform
author_rank: Regular Contributor
timestamp: June 01, 2020, 02:14:06 pm
content: Quote from: asmi on June 01, 2020, 12:30:56 pmI checked out the calculator and JLC2313 seemed to require thinner traces - but I want them to stay above 5 mil - which I cant quite do for 100 Ohm differential

author: asmi
author_rank: Super Contributor
timestamp: June 01, 2020, 02:23:03 pm
content: Quote from: phaseform on June 01, 2020, 02:14:06 pmI would love to hear one good reason why you'd want wider traces. For me it's always the opposite - the narrower traces are - the better.

author: KaneTW
author_rank: Frequent Contributor
timestamp: June 01, 2020, 02:32:30 pm
content: Insertion loss is lower with wider traces.

author: asmi
author_rank: Super Contributor
timestamp: June 01, 2020, 02:51:57 pm
content: Quote from: KaneTW on June 01, 2020, 02:32:30 pmProof? As far as I know insertion loss is higher when you have impedance discontinuities. And since you will have narrow traces under BGAs anyway (because there is no space for wider traces), so having "full" traces' width closer to what you have in BGA breakout areas will reduce impedance discontinuities.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 01, 2020, 03:34:45 pm
content: Roughly speaking, more copper means lower loss. RG-174 is smaller and has higher unit loss than RG-8.But it depends.https://www.protoexpress.com/blog/losses-in-pcb-transmission-lines/This shows some examples, and some counterexamples. (Newsflash, reality is messy.) They are using approximations, so one shouldn't expect their results are fractional-dB accurate. They're also assuming, I think, a wide stripline; this will be significantly different from narrow stripline and microstrip. If youreallyneed to know, fab a test coupon and plug it into a network analyzer.I imagine there's also a loss(impedance) tradeoff, similar to the case for coax (if weaker in effect). Therefore substrate thickness matters as well.Tim

author: phaseform
author_rank: Regular Contributor
timestamp: June 01, 2020, 03:59:08 pm
content: Quote from: free_electron on June 01, 2020, 02:28:16 amI feel I’m stretching the limits of this contract just going back to ensure that our goals are met “high quality and most affordable” I feel if I can just get trace width set for the JLC Stack Up, along with drill sizes, I feel it will be a win.. don’t want the designer to self combust if I add more on..

author: KaneTW
author_rank: Frequent Contributor
timestamp: June 01, 2020, 05:26:12 pm
content: Honestly, just ask the designer to verify that the design works with JLCPCB's published controlled impedance stack, and adjust trace widths etc if needed. My suggestion is to use the JLC2313 stackup.

author: free_electron
author_rank: Super Contributor
timestamp: June 01, 2020, 06:31:38 pm
content: Quote from: phaseform on June 01, 2020, 02:14:06 pmChange the pitch between the traces.7 mil track with 6 mil gap on 7628as for stretching the contract. you are not stretching the contract. He didn't meet deliverables. The requirement was controlled impedance. It is the layout engineers job to figure that one out ! He should have asked you where you were going to fab it and then done the math. not design something where you then have to spend time finding someone who can build it , if it can be built at all ! Here is my design . it uses a square screw in a triangular hole. you figure out how to drill it and where to get the screw ? it doesn't work that way ...

author: phaseform
author_rank: Regular Contributor
timestamp: June 02, 2020, 09:04:53 am
content: I do find it kinda annoying that I had to create the process of delivering a PCB along the way (largely thanks to this thread).. shrug..I sent some calcs for JLC7628 to my designer50 Ohm for JLC7628 gives trace width single ended 11.55mil outer layer and 9.25mil inner layer, slightly wider than the V1 gerbers90 Ohm differential gives trace space and width 7 mil100 Ohm differential gives 5.7mil width with 8 mil trace spaceSo I have some understanding about what is required here.. perhaps if I can achieve something like as described below.. then I will have a nice solution clearly organised for JLC.. which seems suitable for a prototypeQuote from: free_electron on June 01, 2020, 02:28:16 amTightest routing seems to align with 2313, so perhaps this will be best outcomeonly reason I wanted wider traces was to avoid possible higher price for higher spec, also just an assumption that wider traces may be better suited to non high precision production

author: asmi
author_rank: Super Contributor
timestamp: June 02, 2020, 07:05:30 pm
content: Quote from: phaseform on June 02, 2020, 09:04:53 amNo such thing at JLC.

author: Ice-Tea
author_rank: Super Contributor
timestamp: June 02, 2020, 07:17:17 pm
content: Quote from: free_electron on June 01, 2020, 02:03:45 pmOut of curiousity: do the results match?

author: thm_w
author_rank: Super Contributor
timestamp: June 02, 2020, 10:44:32 pm
content: Quote from: Ice-Tea on June 02, 2020, 07:17:17 pmIts close enough, depends on which conductor height you go with, for JLC7628 (width 9.01mil, space 6mil, er 4.6) Saturn gives:7.87mil = 92.7R7.10mil = 89.1RJLC shows 7.10 in the photo but 2mm (7.87) in the stackup. So maybe 7.10 is reality.

author: GerardG
author_rank: Regular Contributor
timestamp: June 03, 2020, 02:14:33 pm
content: Herewith my 2 cents on impedance.The outside copper thickness must be above 33.4µm for IPC class 2 and above 38.4µm for IPC class 3, asking for an outgoing test report will most likely show copper thickness up to 46µm.Manufacture will check the impedance on an optimized coupon that is placed in the production panel. Not the trace you have specified.Because of the co-planar copper it can not meet the exact requirements over the full length of the traces.Thickness of pressing can vary 10% after pressing. The epoxy will flow to parts that have no copper. This means another variable in the calculation.I worked with a big company in Germany that at first requested impossible impedance requirements.After doing some tests (maybe 40.000 boards) for USB and Ethernet they switched to specifying the stackup and required trace width tolerance.Placed the impedance traces on the inner layers of the board (where possible) to avoid too much plating.Of coarse these designers already knew what they where designing. That is why they now do only Impedance testing on the MLB8 and above.

author: Kasper
author_rank: Frequent Contributor
timestamp: June 03, 2020, 05:35:36 pm
content: Quote from: asmi on June 01, 2020, 02:23:03 pmMight want wide traces if you are connecting them to wide pins. This 50 ohm SMA connector has a 0.76 mm dia pin and recommended footprint has trace width of 2.5 mm.SMA MPN: 142-0701-801Also some places, seeed for example, charge extra for less than 6 mil trace width.

author: asmi
author_rank: Super Contributor
timestamp: June 03, 2020, 06:11:16 pm
content: Quote from: Kasper on June 03, 2020, 05:35:36 pmContext is everything! OP is talking about USB and Ethernet, none of them have such wide pins.Quote from: Kasper on June 03, 2020, 05:35:36 pmI don't use fabs which are stuck in the past century, as there are enough of them which don't nickel and dime their customers. 6 mil limit is a stone age tech nowadays, heck I was able to make such traces at home several years ago.

author: phaseform
author_rank: Regular Contributor
timestamp: June 09, 2020, 02:40:52 am
content: my designer previously sent me a photo of a terribly soldered SMD board, he says he paid to have it 'stuffed' and that was an example why I should pay to have it stuffed (advising against doing it myself)..(??)I'm just like why would you send me an example of you failing to manufacture something..?So I have stencils and boards on the way, also components are on their way.Woke up dreaming about aspecific partwhich is out of stock for a month or so.. How it doesnt seem to be RoHS..more rabbit holes..

author: phaseform
author_rank: Regular Contributor
timestamp: June 23, 2020, 04:23:02 am
content: Saga continues. My (PHD Doctor...) designer did infact route mains voltage though .5oz internal layers, but not to worry, he routed the mains line in series with a 3A fuse... (kinda makes the 16A specification redundant... time for a new designer)PCBs have arrived so I will assemble them and test for functionality.I will have to basically start from scratch.. I will need the schematic audited and then PCB rebuilt. So me next step is to find a someone competent to do this. As with this version of the build I will follow the work (perhaps even do the PCB myself), so I will be looking for someone who can detail the steps taken and ideally work in KiCad or some other software I will be able to follow along in.. any retired gurus who aren't looking for government contract wages?