Digital logic: How to write back to the source? - Page 1
Forum section: electronics / projects

author: Artlav
author_rank: Frequent Contributor
timestamp: February 07, 2016, 11:55:24 pm
content: I'm trying to figure out how to do the basic digital logic thing - write the result back to one of the result's sources.Let' say we want to do something like A = A & B, or even simple one like PC = PC + 1How can that be done on logic gate level?In the first case, we have A, a register of some sort - memory cells, flip-flop, anything with an input, write enable signal and output.And B - 8 wires with either high or low levels on them.They get fed into 8 AND gates, one from each of A, one from each of B.The output is our result - A & B.Now, how the hell can i get that result back into A?Just feeding it into the input would create a feedback loop of the results being ANDed until some equilibrium or loop is found. You'd need to pulse it fast enough to outrun light - does not feel like a real solution.Feeding the result into a separate buffer A', then on the next clock feeding the A' into A would work, but it doubles every register in the design, which again feels wrong.Same thing with incrementing a program counter through a common ALU - how can you read and write into something at the same time?What am i missing here?

author: Howardlong
author_rank: Super Contributor
timestamp: February 08, 2016, 12:05:23 am
content: Quote from: Artlav on February 07, 2016, 11:55:24 pmEdge triggered flip flop, usually a D type.

author: langwadt
author_rank: Super Contributor
timestamp: February 08, 2016, 12:06:05 am
content: the output of the register only changes on the clock edge, i.e. what was on the input of register shortly before the clock edgewill be on the output shortly after the clock edge

author: ataradov
author_rank: Super Contributor
timestamp: February 08, 2016, 12:07:33 am
content: Triggers are edge sensitive, so they will take a new value on the edge of the clock signal. Sure, that new value will be almost immediately (after the propagation delay) used for new calculation, but the result will not be written until the next clock cycle. And it is your responsibility to remove the write enable signal before that next clock cycle comes.

author: Artlav
author_rank: Frequent Contributor
timestamp: February 08, 2016, 12:09:26 am
content: In case that this is confusing, here is a typical diagram of a CPU.I fail to imagine how the red paths could be made without intermediary storage, clock edge triggering or not.

author: ataradov
author_rank: Super Contributor
timestamp: February 08, 2016, 12:10:13 am
content: Akku and AdReg are registers.So on each clock cycle AdReg will be written either new value (from DataIn) or AdReg + 1. Just like planned.

author: Artlav
author_rank: Frequent Contributor
timestamp: February 08, 2016, 12:17:13 am
content: Sorry, i'm confused now that i took a good look at that diagram.In verilog that was described the way below.In there there are statements like "accumulator[7:0]<=~(accumulator[7:0]|datain);"So, the way they are synthesized is by adding an intermediary register?Code:module tcpu(input [7:0] datain,output [7:0] dataout,output [5:0] adress,output we,input rst,input clk);reg [8:0] accumulator; //accumulator(8) is carryreg [5:0] adreg;reg [5:0] pc;reg [2:0] states;always @(posedge clk)beginif(~rst)beginadreg <=0;states <=0;accumulator<=0;pc <=0;end else beginif(~|states)begin //NOR with three inputspc <=adreg+1;adreg<=datain[5:0];end else beginadreg<=pc;end//ALU/Data Pathcase(states)3'b010:accumulator <={1'b0,accumulator[7:0]}+{1'b0,datain}; //add3'b011:accumulator[7:0]<=~(accumulator[7:0]|datain); //nor3'b101:accumulator <=1'b0; //branch not taken, clear carrydefault:;endcase //default: instruction fetch, jcc taken//State machineif(|states)states<=0; else begin //3-port orif(&datain[7:6]&&accumulator)states<=3'b101;else states<={1'b0,~datain[7:6]};endendend//outputassign adress =adreg;assign dataout=(states==3'b001)?accumulator[7:0]:8'bZZZZZZZZ;assign we =clk|~rst|(states!=3'b001);endmodule

author: ataradov
author_rank: Super Contributor
timestamp: February 08, 2016, 12:19:41 am
content: You have declared it as a register and described how it must be updated (on "posedge clk"). Of course, it will be a register.It is not an intermediate, it itself is that register.And sometimes, even if you don't declare a latch, tools will infer a latch, and complain about that. This is why it is important to either really-really-really know what you are doing, or read all the warnings.

author: langwadt
author_rank: Super Contributor
timestamp: February 08, 2016, 12:28:02 am
content: Quote from: Artlav on February 08, 2016, 12:17:13 amaccumulator is the register, at the rising edge of clk what is at the input of the register will be stored in the registereasier to see in a waveform if you add delays to your verilog to make it look more like the real world, i.e.accumulator[7:0]<= #1 ~(accumulator[7:0]|datain);

author: Artlav
author_rank: Frequent Contributor
timestamp: February 08, 2016, 12:35:21 am
content: Ah, no. Not confused.The diagram just swapped the places.The problem with red lines is - on one clock we are taking the data from the register, feeding it into the ALU, then it's supposed to write back into the same register.But once it does, what prevents it from just looping again?Where is that inferred latch, implicit register or whatever it is?Quote from: langwadt on February 08, 2016, 12:28:02 amIt took data from itself, it writes data into itself. The data can't just get stored in the wires.Where/how is it stored when the state of the register is changing?Quote from: ataradov on February 08, 2016, 12:19:41 amThat is what i'm trying to achieve...

author: ataradov
author_rank: Super Contributor
timestamp: February 08, 2016, 12:46:56 am
content: Quote from: Artlav on February 08, 2016, 12:35:21 amChange is not instantaneous. So there is plenty of time to write the new data while result still stays the same. So in effect, yes, it is stored in wires.In fact, that's what limits your clock rate. There is a propagation delay within the latch. Another major contributor to the clock rate limit is logic propagation delay. Even when new value is stored into the register, and it has propagated to the output, there is still delay in the logic before it gets back to the input of the latch.

author: langwadt
author_rank: Super Contributor
timestamp: February 08, 2016, 01:00:00 am
content: Quote from: Artlav on February 08, 2016, 12:35:21 amthe register stores what is at the input only when there is a clock edge, before the signal has a change to it isafter the clock edge and register doesn't care what is at the input it doesn't change until there is a new edge

author: amyk
author_rank: Super Contributor
timestamp: February 08, 2016, 04:31:06 am
content: Quote from: ataradov on February 08, 2016, 12:46:56 am

author: Artlav
author_rank: Frequent Contributor
timestamp: February 08, 2016, 11:12:35 am
content: Ok, that starts to make a bit more sense, but i still feel like i'm missing a concept.I still can't quite grasp if we are dealing with the data being stored in the delay?I.e. looking at the gif above - with an edge-triggered flip-flop how does it happen that the input is sampled before the output is set?Quote from: langwadt on February 08, 2016, 01:00:00 amWhich raises the question - what is a register?I was thinking about it as an SRAM cell or something similar, but then you would need several latches per cell to make it edge-triggered, which sounds like a lot of extra gates.

author: dmills
author_rank: Super Contributor
timestamp: February 08, 2016, 12:04:56 pm
content: A register is usually some form of D type flipflop per bit, so yea, a modest amount of logic.Note that in most HDLs, a latch is level triggered and a register is edge triggered (And latches are usually a really bad idea, but can be inferred if you are not careful).Take a look at something like a 74HC74, a jellybean D type flipflop (Which is annoyingly referred to as a latch outside the HDL world), the datasheet lists three critical parameters, a propagation delay, a setup time and a hold time.The output takes the value the input had at the rising edge of the clock after the propagation delay thru the device, and for that to reliably be the case the input must be stable for the duration defined as the setup time before the clock edge and for the hold time after it (Fail to meet setup and hold and really weird things can happen, the term is metastability and it can be a major pain when you have more then one clock in play).The key is that conceptually the output of a register takes the state of the input measured at the clock edge, and holds it constant the rest of the time, and that the state of the output updates shortly after the clock edge that sampled the input.The edge triggering of the update means that the output of the register changes at most once per clock cycle (We will gloss over async set and clear).Regards, Dan.

author: Siwastaja
author_rank: Super Contributor
timestamp: February 08, 2016, 01:34:52 pm
content: Quote from: Artlav on February 08, 2016, 11:12:35 amRegister is a D flip flop. While "flip flop" typically refers to a single bit, "register" usually means an arbitrary number of D flip flops (for every bit) which share the clock.D flip flop normally ignores the input. During the brief moment of the clock edge, it copies the input to the output and continues storing it. The input must be stable (i.e., not changing or fluctuating) during a brief moment around the clock edge. The idea of synchronous logic is that the intermediate paths have ample time to resolve to a stable state during the time when the flip flops are ignoring the inputs.

author: amyk
author_rank: Super Contributor
timestamp: February 08, 2016, 04:26:26 pm
content: Quote from: Artlav on February 08, 2016, 11:12:35 amLook at the lowest left gate. It only lets the input into the rest of the circuit when the clock is low, but blocks it going past that gate when the clock is high. Similarly, the two middle gates on the left allow the signal to go through when the clock is high, and block when the clock is low. The idea is that one closes while the other opens, and vice-versa, so at the trigger edge, one latches the input at the same time the other lets what was latched go through. It all works because of propagation delay; nothing happens instantaneously.That circuit is a cute way of drawing an edge-triggered flip-flop, but it's easier to understand in a master-slave configuration.QuoteIn practice, edge-triggered elements are usually based on two non-overlapping clocks, either generated globally or locally via inverters, which controls a pair of transparent latches and is similar to master-slave configuration.

author: Artlav
author_rank: Frequent Contributor
timestamp: February 08, 2016, 11:21:08 pm
content: Ok, i think i get it now.The input is being stored on the falling edge of the clock in the master part, and then on the rising edge the output/slave part gets set.So there is no race against the propagation speed, just implicit storage.And, registers are not memory, so the idea of needing extra gates is not relevant.Essentially, a register is not just was is intuitively thought of as a memory cell with a write input and state output, it's a special element that was designed for these sorts of purposes, feedback write included.Thanks everyone for helping!