Bypassing parts of JTAG chain in power off conditions - Page 1
Forum section: electronics / projects

author: tom66
author_rank: Super Contributor
timestamp: December 10, 2024, 01:40:40 pm
content: I have a board with an FPGA and a microcontroller on the bus. To simplify debugging and allow for an implementation of boundary scan, the JTAG bus is chained from the microcontroller to the FPGA. A single JTAG bus is available on the debug connector. We are pin-constrained on this connector so adding two JTAG ports is not practical.The issue with this method is that when the FPGA is asleep, the JTAG bus is inoperative, because the TDO from the FPGA will not be driving anything, and it is likely TMS/TCK will be sinking low through the ESD diodes.The only method I can see which can avoid this issue would be to fit a multiplexer which bypasses all JTAG signals away from the FPGA in sleep mode. It isn't practical for us to force the FPGA to run all the time, or even during FPGA operation.I am wondering if others have better solutions to this problem. It feels like a problem which ought to have a standard solution.

author: ataradov
author_rank: Super Contributor
timestamp: December 11, 2024, 01:29:04 am
content: If powering on and off is not frequent, then lust a mechanical 3 position switch or 3 jumpers should do the trick. Two jumpers to disconnect TMS and TCK, and one jumper to short TDI and TDO.

author: tom66
author_rank: Super Contributor
timestamp: December 11, 2024, 02:54:05 pm
content: The board is too small to accommodate either, unfortunately.

author: ataradov
author_rank: Super Contributor
timestamp: December 11, 2024, 03:10:25 pm
content: How much board space do you have? It sounds like you can't accommodate anything.From the added board space, just bringing out JTAG on a separate connector may be the most optimal solution. It adds 4 pins worth of board area.

author: tom66
author_rank: Super Contributor
timestamp: December 11, 2024, 03:37:59 pm
content: The board can't really accommodate an additional connector because the interface needs to be exposed over the single connector in the stack for mechanical reasons. That connector has every pin allocated. The board is smaller than a credit card.Essentially I am asking for a sanity check, I can solve this with a mux to bypass signals, but has anyone encountered this before and had a better idea? For all I know a JTAG bypass/buffer IC is a common part... but I can't find one.

author: MLi
author_rank: Newbie
timestamp: December 11, 2024, 04:41:31 pm
content: I've done a bunch of JTAG switching at work, and my goto IC is the 74CBTLV3244 analog switch.It has two groups of four bidirectional ports, and I normally use it as one eight port chip to also switch the reference voltage and ground detect pins (if available).There is also a 2x5 port version called 74CBTLV3384 also.

author: langwadt
author_rank: Super Contributor
timestamp: December 11, 2024, 05:01:50 pm
content: all the FPGA need is power, why is that not possible?

author: jbb
author_rank: Super Contributor
timestamp: December 11, 2024, 08:51:49 pm
content: Maybe SN74LVT8996 ? I’ve never used it but looks interesting. However, it could be pricey or go obsolete with little warning.Using simple analog mux chips might be a better bet.

author: tom66
author_rank: Super Contributor
timestamp: December 12, 2024, 10:36:17 pm
content: Quote from: langwadt on December 11, 2024, 05:01:50 pmBecause I need to JTAG debug the system when the FPGA is offline, e.g. testing low power operation.

author: bson
author_rank: Unknown
timestamp: December 13, 2024, 08:19:02 pm
content: You can't wake the FPGA for a boundary scan? Shouldn't it be part of the scan? Is the scan even meaningful with it asleep?

author: tom66
author_rank: Super Contributor
timestamp: December 13, 2024, 10:20:56 pm
content: Quote from: bson on December 13, 2024, 08:19:02 pmI can wake it for a boundary scan, but there are situations in which I would need to JTAG debug the system when the FPGA is offline, e.g. low power debugging whilst the MCU is alive, FPGA is asleep (completely powered down in most cases).