FPGA VGA Glitch Problem - Page 1
Forum section: electronics / general

author: nmcgnyksl
author_rank: Newbie
timestamp: May 09, 2015, 07:16:50 am
content: Hi guys,I am trying to use VGA with FPGA for a school project but I encountered a glitchy screen problem and I don't know how to solve it. Can you tell me what may cause this problem and how can I solve it? Help is much appriciated. I am posting screen photo and the codes. Thank you and sorry for my english.// initial parameters for vga syncronizationparameter hpix = 800; // total horizontal pixelsparameter vpix = 525; // total vertical pixelsparameter hlow = 96; // first low signal of horizontalparameter hbp = 144; // end of back porchparameter hfp = 784; // start of front porchparameter vlow = 2; // first low verticalparameter vbp = 35; // back porch endparameter vfp = 515; // front porch startalways @(posedge sclk) //count hreg and vregbeginif (hreg < hpix-1)hreg <= hreg+1;elsebeginhreg <=0;if (vreg < vpix-1)vreg <= vreg+1;elsevreg <=0;endif(hreg>142) // create another map for screensh <= hreg-143;elsesh <= hreg+657;if(vreg>31)sv <= vreg-32;elsesv <= vreg+491;endassign hsync = (hreg<hlow) ? 0:1; //s?f?rlar? verassign vsync = (vreg<vlow) ? 0:1;

author: hamster_nz
author_rank: Super Contributor
timestamp: May 09, 2015, 08:30:32 am
content: My money is that you are using a digilent basys2, which has a precision RC oscillator thing on it, rather than a crystal.You will need to get a better, stable clock source. The one on the board sucks, so badly that most LCD monitors refuse to lock on the syncs.If you search on the web you might find how loading down the power supply with a 100 ohm resistor stuck in a pmod port helps a little. I couldn't tell the difference.....

author: hamster_nz
author_rank: Super Contributor
timestamp: May 09, 2015, 08:36:06 am
content: Oh, and make sure that your signal pins are connected to clocked registers. If there is any logic between the last register and the pin then glitches can happen.If rising edge of clock then....If count = sync_start-1 then set sync signalIf count = end_of sync then clear sync signal

author: nmcgnyksl
author_rank: Newbie
timestamp: May 09, 2015, 11:19:41 am
content: Thanks for the reply. Yes i am using basys2 but i will use an high quality altera board while demonstrating. basys2 will be used only for trials when i cannot use school's lab.About your second guess i am using some algoritims like below. I am posting whole code hoping you can help me find if there is any problem as you mentioned.Code:module ilkdeneme(input wire clk,output wire hsync,output wire vsync,output reg [2:0] red,output reg [2:0] green,output reg [1:0] blue);// initial parameters for vga syncronizationparameter hpix = 800; // total horizontal pixelsparameter vpix = 525;// total vertical pixelsparameter hlow = 96;// first low signal of horizontalparameter hbp = 144;// end of back porchparameter hfp = 784;// start of front porchparameter vlow = 2;// first low verticalparameter vbp = 35;// back porch endparameter vfp = 515;// front porch startreg [9:0] hreg;// horizontal counter storagereg [9:0] vreg;// vertical counter storagereg [9:0] sh;reg [9:0] sv;reg [17:0]c;wire sclk;wire gclk;wire solserit_beyaz =(((sh>19)&&(sh<25))||((sh>54)&&(sh<60))||((sv>2&&sv<6)&&(sh>19&&sh<60))||((sv>444&&sv<449)&&(sh>19&&sh<60)));wire solserit_gri = ((sh>24)&&(sh<55));initialbeginscary =440;scarx =30;endalways @(posedge clk)beginc<=c+1;endassign sclk = c;always @(posedge sclk) // count hreg vregbeginif (hreg < hpix-1)hreg <= hreg+1;elsebeginhreg <=0;if (vreg < vpix-1)vreg <= vreg+1;elsevreg <=0;endif(hreg>142) // mapping for screensh <= hreg-143;elsesh <= hreg+657;if(vreg>31)sv <= vreg-32;elsesv <= vreg+491;endassign hsync = (hreg<hlow) ? 0:1; //s?f?rlar? verassign vsync = (vreg<vlow) ? 0:1;//always @(posedge gclk)//oyun hakk?nda her sey burda//begin////endwire r2 = (solserit_beyaz)&&((sh<640)&&(sv<480));wire r1 = (solserit_beyaz)&&((sh<640)&&(sv<480));wire r = ((solserit_beyaz)||(solserit_gri))&&((sh<640)&&(sv<480));wire g2 = ((solserit_beyaz))&&((sh<640)&&(sv<480));wire g1 = ((solserit_beyaz))&&((sh<640)&&(sv<480));wire g = ((solserit_beyaz)||(solserit_gri))&&((sh<640)&&(sv<480));wire b1 = ((solserit_beyaz))&&((sh<640)&&(sv<480));wire b = ((solserit_beyaz)||(solserit_gri))&&((sh<640)&&(sv<480));always @(clk)beginred <= r2;red <= r1;red <= r;green <=g2;green <= g1;green <= g;blue <= b1;blue <= b;endendmodule

author: ale500
author_rank: Frequent Contributor
timestamp: May 09, 2015, 02:31:21 pm
content: he means doing something like this:reg hsync, vsync;always @(posedge sclk) //count hreg and vregbegin...hsync <= (hreg<hlow) ? 1'b0:1'b1;vsync <= (vreg<vlow) ? 1'b0:1'b1;end

author: hamster_nz
author_rank: Super Contributor
timestamp: May 09, 2015, 08:09:31 pm
content: Quote from: nmcgnyksl on May 09, 2015, 11:19:41 amThis video shows the effect that adding a resistor might have while using the Basys2:You can't really get it any better unless you add your own oscillator - at least there is a socket on the board for one!

author: ale500
author_rank: Frequent Contributor
timestamp: May 14, 2015, 02:17:02 pm
content: Get a crystal oscillator. It doesn't have to be 25 MHz, 5, 10, 50 and so on as you can use the pll, something that is anyways recommended

author: hamster_nz
author_rank: Super Contributor
timestamp: May 14, 2015, 06:17:59 pm
content: Quote from: ale500 on May 14, 2015, 02:17:02 pmIf you are ordering something, the over 24 MHz is best - the minimum frequency for DLL CLKIN input is 24MHz (see Table 28 of DS099 - "Spartan-3 FPGA Family: DC and Switching Characteristics"). But you can still use the DFS all the way down to 1MHz...