XMHz - 100MHz phase detector - Page 1
Forum section: electronics / projects

author: GK
author_rank: Super Contributor
timestamp: November 26, 2015, 08:49:27 am
content: Making a DC-100MHz DDS-based AM/FSK/BPSK quadrature signal generator. Due to component tolerances/component mismatches in the high-order elliptical passive filters for the I/Q channels the phase deviation from the ideal 90 degrees becomes unacceptable beyond a certain operating frequency (high-order filters generate a lot of phase shift and only a small mismatch in fc between identical filters screws things up).So I need a phase detector for auto-calibration. The ideal detector would output 0V when the phase (difference) = 90 degrees and, say, +/-1V for +/-10 degrees deviation from 90 degrees. Would like to auto-correct to +/-0.5 degrees or better. A window comparator could detect the output level of the detector corresponding to +/-0.5 degrees deviation; the 3-states (<,"in range",>) detected by the uC running a simple successive approximation routine to program the phase tuning word of one DDS channel (starting at a bit height simply adequately great for the required correction factor range). This will give a quick auto-phase calibrate run whenever the frequency is changed. Phase correction will only operate at operating frequencies high enough for the phase error to be theoretically out of bounds due to the worst case tolerances. The phase detector must maintain its <=0.5 degree spec out to 100MHz.I can immediately think of a number or ways to possibly implement a detector but does anyone know of the existence of an elegant single (or close) chip detector for accurate quadrature detection out to 100MHz from a few MHz having a high degree of accuracy and stability? Logic level deviation/threshold outputs?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 26, 2015, 09:12:43 am
content: Comparators and type 1 or 2 PD? Preferably screaming fast e.g. ECL/LVDS?Good old diode ring mixer works too. Probably easier to get right than all the stuff in the digital chain (i.e., matched comparator delays, matched gate delays..). You may need relays to switch it in/out of the signal path, or additional buffer stages so it stays isolated from the main output (lest it introduce power absorption, reflections and THD).In either case, filter the result, and read the average with an ADC. (1-1.5 bit acquisition sounds so... dumb. Unless you truly don't have an ADC handy, and can't be bothered to add one. In which case, you need to implement the SAR manually.)You play with this stuff all the time though... I doubt I'm adding anything new. What's missing?Tim

author: KJDS
author_rank: Super Contributor
timestamp: November 26, 2015, 09:16:32 am
content: A Bessel filter with quasi-eliptic stopband would reduce your passband phase shift problems

author: GK
author_rank: Super Contributor
timestamp: November 26, 2015, 10:00:59 am
content: Quote from: T3sl4co1l on November 26, 2015, 09:12:43 amA typical CMOS digital output phase/frequency detector produces a DC-level output (after integration) that is a function of both phase and supply voltage. For a phase detector implemented in ECL (say an XOR gate to be super-simple) the output would be a function of both phase and the internal clamping level, which is imprecise and variable with temperature for one thing, making that avenue useless.With CMOS logic the integrated output can be compared to a trimmed reference level (corresponding to 90 degrees) derived from and thus ratiometric to the supply potential, eliminating that source of error, but CMOS is too slow for accuracy out to 100MHz. Differences in rise/fall and on/off propagation delays cause too much error.In a typical PLL with a digital-output detector the detector output steers in sign (thus controlling the loop) about the phase difference point (typically 0 degrees), so supply voltage variation effecting the logic output level only modulates the detectors gain (and thus the loop gain of the PLL), not the accuracy of the detectors phase/frequency discrimination. Totally different application.QuoteNot sure what you are getting at here. I proposed the SAR implemented in software. It would toggle the DDS phase tuning word bits in turn, MSB first, each time checking the phase detector "<", "in range", or ">" status before deciding on the final status of the current bit and moving onto the next one. Thus in only a handful of bit-toggles the complete phase calibration is complete. This is nothing more complicated than a few lines of code (not counting the subroutine called to program the DDS registers).EDIT: technically, to implement the SAR, I wouldn't even need an "in range" logic status from the detector - Just higher or lower would do. Logic 0 could = phase deviation lower and logic 1 = phase deviation higher. That simplifies my detector specification further.So what I need is an accurate quadrature detector that can accurately steer a logic-level output in response to a small deviation (0.5 degrees or better) from 90 degrees. Rather that a phase detector, call it a phase comparator with a threshold of 90 degrees

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 26, 2015, 10:26:44 am
content: Quote from: GK on November 26, 2015, 10:00:59 amAh, but the internal reference level drifts the same way. Probably. Hopefully?Since you don't care about gain at all, the supply voltage can be all over the place. That's one problem solved. So, for most solutions, errors should be dominated by delays. At least as long as you can track the V_OH / V_OL ranges, if they drift disparately.ECL example: use the complementary outputs to your advantage. Filter each, and use a differential amplifier for the error amp. (Or comparator for your 1-bit ADC, or whatever.) The thresholds are complementary and errors cancel out, all you need to check is the difference is zero.Or use additional gates (e.g., a quad XOR?), strapped in static states, to obtain V_OH and V_OL, and treat accordingly. But that's hackier and worse.QuoteCMOS need not be slow, but it probably has to be done internally. With some help from some latches or counters or whatever, it might be feasible to do it entirely digitally, within an FPGA (the transistors are 1.2V or less -- guessing you can't get discrete CMOS that low and that fast).Or the DBM, what's wrong with that? Typically, you drive one port at "LO" levels (some dBm's) and the other at "RF" levels (< 0 dBm?). The output is DC (and 2 x f_clk, but that's filtered out) proportional to the RF amplitude.I don't know too much about phase shift and delay in DBMs. Presumably the delays will be mismatched due to signal intensity, if nothing else. Which will give rise to some residual error as frequency varies. But I should think a few degrees wouldn't be out of the question.DBMs can be driven symmetrically as well (i.e., equal amplitudes), but the linearity should be worse (because diode Vf is dependent on both signals' amplitudes and phases).QuoteI like to use dual-clocked flip-flops, which produce a square wave output of constant PWM for a given phase shift. Tristate PFDs are good for frequency control in simple loops, but I don't think they're a good idea for a static measurement.Such a flip-flop is impossible to implement in an FPGA (no synthesizer will accept two clock events), unless you specify it purely as combinatorial logic (in which case, it won't know how to synthesize it well, and the speed sucks).But it can be implemented in two D-f/f's and a gate, or 8 fundamental gates (i.e. NAND/NOR), which isn't so bad.Tim

author: GK
author_rank: Super Contributor
timestamp: November 26, 2015, 10:46:16 am
content: Quote from: T3sl4co1l on November 26, 2015, 10:26:44 amIncorrect! I DO care about gain because the DC potential indicating the phase difference between detectors inputs is a function of gain. If the gain varies, the indicated phase varies. I did explain that the way to eliminate gain error is to compare the integrated detector output to a reference ratiometric to the supply potential.QuoteI was of course taking generic discrete logic families. I would prefer not to design in an FPGA to implement my phase detector/comparator.QuoteA DBM does not inherently detect 90 degrees of phase shift! If my goal was to detect phase/frequency equality all would be a walk in the park, but I don't and it isn't.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 26, 2015, 10:50:07 am
content: Quote from: GK on November 26, 2015, 10:46:16 amDid I not just propose... what?QuoteEh? DBM output is null at 90 degrees, with maximum gain there (since output goes as cos(phi) and gain goes as the derivative, -sin). If it were 0 or 180, you'd have a problem (i.e., needing something like a MPPT controller to detect the local max/min).Anyway, cheers,Tim

author: GK
author_rank: Super Contributor
timestamp: November 26, 2015, 11:04:48 am
content: Quote from: T3sl4co1l on November 26, 2015, 10:50:07 amI was pointing out that I had already stated what you were telling me in response. Why do you repeat what I said in different words? Do you suffer reading comprehension difficulties or is this supposed to be some sort of game?Quote from: T3sl4co1l on November 26, 2015, 10:50:07 amWell of course it is. That was an obvious oversight on my behalf. You've managed to post one useful sentence. Issue resolved, I have a plethora of high frequency DBM's within actual reach. Thread closed.

author: GK
author_rank: Super Contributor
timestamp: November 26, 2015, 11:11:02 am
content: Quote from: KJDS on November 26, 2015, 09:16:32 amNot by enough.

author: GK
author_rank: Super Contributor
timestamp: November 28, 2015, 07:42:44 pm
content: Quote from: GK on November 26, 2015, 08:49:27 amI'll float this question one last time in the hope thatsomeone with actual RF experience in this area who can actually grasp the non-triviality of my quoted specificationmight chime in. A quadrature detector based on a common DBM is a possibility, but there are difficulties. For example a DBM with a 1GHz bandwidth on the LO port and 500MHz on the RF port will already have nearly 6 degrees of its own phase error at 100MHz - as already stated I need detection out to 100MHz to 0.5 degrees or better. I have a couple of passive/active hybrid FET-based multi-GHz DBM's here that have pretty decent bandwidth matching between RF and LO ports at several GHz, but they do not operate at anything near as low as 100MHz (transformer coupled inputs), let alone several MHz. Passive DBMs do not appear a particularly viable solution due to the typical low frequency bandwidth limitations.I've got a few integrated mixers with LO/RF/IF port responses extending to DC still to evaluate, but these aren't typically designed to have matched bandwidths between RF and LO ports. One part tried also had excessive DC drift at the IF port, making it unsuitable for <=0.5 degree detection even after external trimming (in itself not overly trivial) for bandwidth/phase equalization out to 100MHz.Given general utility/requirement for accurate quadrature signals out there in RF land, I'm just postulating in my ignorance that it isn't outside the realms of possibility that at specialist quadrature detector chip or chip family exists, but I haven't found a potentially promising example yet.

author: c4757p
author_rank: Super Contributor
timestamp: November 28, 2015, 07:58:12 pm
content: Feed both signals into the analog pins of an Arduino and use an FFT to compute the phase of each.source: I AM RF XPURT

author: KJDS
author_rank: Super Contributor
timestamp: November 29, 2015, 12:24:19 am
content: How much filter loss do you need at what frequency?With that, I'll have a crack at designing a filter that will meet your needs.

author: rfeecs
author_rank: Frequent Contributor
timestamp: November 29, 2015, 03:46:11 am
content: Quote from: GK on November 28, 2015, 07:42:44 pmHow about the active version, a Gilbert cell phase detector? Maybe using MC1496 or HFA3101.It may be easier/better to solve the root cause of the problem instead of trying to calibrate it out. But I'm sure you already considered that.

author: rfeecs
author_rank: Frequent Contributor
timestamp: November 30, 2015, 08:35:05 pm
content: FYI, a few articles on mixers as phase detectors, with a lot of discussion of DC offset issues:http://www.markimicrowave.com/blog/2015/02/all-about-mixers-as-phase-detectors/http://www.markimicrowave.com/blog/2013/05/dc-offset-and-mixers-as-microwave-phase-detectors/http://www.rfcafe.com/references/articles/wj-tech-notes/Mixers_phase_detectors.pdfThe last one is the classic WJ app note.

author: kony
author_rank: Regular Contributor
timestamp: November 30, 2015, 09:07:23 pm
content: Possible single chip solution:AD8302.

author: GK
author_rank: Super Contributor
timestamp: December 01, 2015, 01:48:31 am
content: Those articles are interesting, particularly the one discussing DC offset error in passive mixers.I've only skimmed the datasheet but the AD8302 looks promising. Input bandwidth extends down to DC. The envelope bandwidth is too high at 30MHz, but the datasheet says this can be lowered as desired with external capacitance. To get it as low as I need external capacitance in combination with additional external filtering would likely be required. The magnitude/difference output could additionally simplify my ALC loop.

author: cncjerry
author_rank: Unknown
timestamp: December 01, 2015, 03:27:52 am
content: The 8302 has a problem right around zero phase and I can't remember if there is a way around it. You have to look at the output peak of the triangle. You can purchase ready made boards from that guy in Greece, I think, off eBay. He's pretty sharp and whips promptly. I have a few of his boards.