LCMXO640C-3TN144C - Clock Pins Configuration - Page 1
Forum section: electronics / general

author: 2X
author_rank: Frequent Contributor
timestamp: July 11, 2025, 09:49:09 pm
content: Hello,I want to start with FPGAs.I selected the LCMXO640C-3TN144C Lattice FPGA. Because I have never use an FPGA... in what pins I have to connect the crystal for the FPGAs clock and what crystal in MHz?Do you know where I can find it on the datasheet?On pages 14-16 "2.2. Clock/Control Distribution Network" says about the clock but I am not sure.

author: ataradov
author_rank: Super Contributor
timestamp: July 11, 2025, 11:46:12 pm
content: FPGAs don't work with crystals, they need clock generators. The frequency depends on your requirements, there is no standard. FPGA itself does not need a clock, your logic does.All pins may be used for the clock, but it is better to use the pins that have CLK in the name, those pins connect to the clock distribution network directly. But for a first project, it likely does not matter.

author: 2X
author_rank: Frequent Contributor
timestamp: July 12, 2025, 10:10:40 am
content: Quote from: ataradov on July 11, 2025, 11:46:12 pmOn the datasheet where can I see the maximum frequency of clock where this FPGA can work "LCMXO640C-3TN144C"?Also, I searched about clock generators and there are plenty of types (like on the below link). There is any certain type of "clock generators" where used for FPGAs? I will use "Standard Clock Oscillators" with 4 pins but I am not sure if it is right choice forn an FPGA.https://gr.mouser.com/c/semiconductors/clock-timer-ics/clock-generators-support-products/Standard Oscillators Standard Clock Oscillatorshttps://eu.mouser.com/c/passive-components/frequency-control-timing-devices/oscillators/standard-clock-oscillators/?product%20type=Standard%20Oscillators

author: atom1477
author_rank: Newbie
timestamp: July 12, 2025, 01:03:32 pm
content: Use one from this list, because the ones from the previous list are advanced clock management systems (dividers, synthesizers, etc.), and they might not even have their own oscillator—they may require an external one.https://gr.mouser.com/c/passive-components/frequency-control-timing-devices/oscillators/You can use almost any oscillator from this list. The only requirement is that it provides a signal no greater than 3.3V (so no 5V).In contrary toataradov, I suggest to use dedicated CLK input pins,especiallyif this is the first project.The reason for this is that for inappropriate pins, Lattice Diamond generates warnings and even errors, which may be unsolvable for a beginner.

author: laugensalm
author_rank: Regular Contributor
timestamp: July 12, 2025, 01:46:36 pm
content: Are you also aware of the internal Oscillator primitive of the MachXO2 family (i.e. one of those, OSCG or OSCH primitives)? That's the easiest way to start ticking.Edit: Duh. Ok, realized too late it's a MachXO (not 2). Not sure if they work the same...There used to be breakout boards from digikey, mouser et al, with a decent number of solderable pads broken out. Not sure if they are still around 30 USD..The greater pain might be the Lattice tools (and their licensing model) though. I found the Gowin TangNano an interesting alternative with less hassle and quite a boost in synthesis speed. There are always dragons, but if you don't need to get into specific signal transmission details, the GW1NR family is a cost effective starter and also works with the opensource tools from the yosys family.

author: 2X
author_rank: Frequent Contributor
timestamp: July 12, 2025, 04:52:55 pm
content: Quote from: atom1477 on July 12, 2025, 01:03:32 pmAt the pictures below from the FPGAs datasheet which pins are the dedicated clock pins and also where I can see on the datasheet what is the maximum clock frequency where these pins can work?

author: ataradov
author_rank: Super Contributor
timestamp: July 12, 2025, 07:53:48 pm
content: Pins that have PCLK in the "dual function" column. Usually there are a lot more of them, but this is a very simple device.You are looking in the wrong section. You need to be looking herehttps://www.mouser.com/c/passive-components/frequency-control-timing-devices/oscillators/standard-clock-oscillators/You need to be looking at something like thishttps://www.mouser.com/ProductDetail/Microchip-Technology/DSC1001CI5-050.0000T?qs=moDRE%2FDosU2MhkmESXOWMg%3D%3DMost of those MEMS oscillators are basically the same, pick whatever works for the frequency and price/availability.

author: 2X
author_rank: Frequent Contributor
timestamp: July 12, 2025, 11:30:10 pm
content: Quote from: ataradov on July 12, 2025, 07:53:48 pmI must connect all the pins together and drive all of them from the single output of the crystal oscillator? Also, I have seen in some designs that each clock pin has a 10ohm resistor in series. This resistor is for short-circuit protection or for some other reason and I have place it?

author: 2X
author_rank: Frequent Contributor
timestamp: July 12, 2025, 11:33:51 pm
content: On the datasheet where I can see what is the maximum clock frequency where the "PCLK" pins and the other I/O pins (or maybe all the pins have the same maximum frequency?) can work?

author: ataradov
author_rank: Super Contributor
timestamp: July 13, 2025, 12:03:07 am
content: Quote from: 2X on July 12, 2025, 11:30:10 pmYou need to pick one. It does not matter which one. FPGAs are very configurable devices, so they provide you with a lot of options. You may also need multiple frequencies in your design, so each input can get its own clock.Quote from: 2X on July 12, 2025, 11:30:10 pmIt may help reducing overshots by limiting a slew rate. It is a good idea to have this resistor for fast frequencies, but it is not mandatory.

author: 2X
author_rank: Frequent Contributor
timestamp: July 13, 2025, 11:52:52 am
content: Where I can find on the datasheet the maximum clock frequency fo the I/O and PCLK pins? Maybe on page 40 from the datasheet?

author: atom1477
author_rank: Newbie
timestamp: July 13, 2025, 02:00:50 pm
content: For that kind of devices there a lot more documents than just only "datasheet".At least two for Your case:https://www.latticesemi.com/~/media/79F188B67E89495AA1A0B2377818A595.ashxhttp://application-notes.digchip.com/030/30-20540.pdfBut the frequency is actually specified in the main datasheet.But you must know that this is the absolute maximum, and it generally applies to IO block, not to every type of IO.These few hundred MHz can be achieved for LDVS type. Ordinary CMOS will reach a maximum of 100...200 MHz.Of course logic blocks (Your VHDL/Verilog code) can reduce the speed even further.

author: ataradov
author_rank: Super Contributor
timestamp: July 13, 2025, 03:40:12 pm
content: Don't worry about the frequencies, they will be high enough for anything you do. There is no point in having 100 MHz oscillator if any real practical design can't run at that clock.The actual design frequency is limited by your design and you will only know it after the synthesis is done.

author: 2X
author_rank: Frequent Contributor
timestamp: July 13, 2025, 04:18:37 pm
content: Quote from: atom1477 on July 13, 2025, 02:00:50 pmIf I understand right....1. The clock frequency on FPGAs are more complex than MCUs (with these I have experience)2. There is not a clear answer on the FPGAs datasheet about in what frequency can work each pin of the FPGA but just a maximum frequency and from this if you have experience you have to estimate or with trials to find the maxixmum frequency for each pin you want?3. For this FPGA I saw on the pdf (MachXOsysIOUsageGuide) at page 5 (Table 8-3. I/O Standards Supported by Various Banks in the MachXO640 and MachXO256) that each bank supportsLVDS25Ebut only with 2.5V, so only with signals at 2.5V in theory all the I/O pins for three Banks can read or output signals at 500MHz?Also, I found also another post about the same FPGA where a guy says about FFs on the I/O:QuoteSource:https://electronics.stackexchange.com/questions/751727/lcmxo640c-3tn144c-maximum-clock-frequencyP.S. I apologise If I am asking two much but when I learn something I want to be documented. If there is any book or something on the internet where I can read about the working frequencies of the FPGAs please tell me.

author: ataradov
author_rank: Super Contributor
timestamp: July 13, 2025, 04:39:48 pm
content: Before you do any hardware, run the software, make a simply blinking LED project and see the maximum reported frequency.Frequencies like 500 MHz are crazy numbers for this device. Those are based on the propagation delay of individual cells not taking any routing into account.In practice, if you get a basic blinky running at 150 MHz, you should be happy. It will get slower from there. Don't expect projects with significant utilization to run much faster than 50 MHz.The advantage of FPGAs is that you can do a lot without actually having the hardware, tools are really good at estimating how the project will operate.

author: 2X
author_rank: Frequent Contributor
timestamp: July 13, 2025, 04:46:02 pm
content: Quote from: ataradov on July 13, 2025, 04:39:48 pmThere is any general thumb of rule where can I estimate the practical working frequency of an FPGA... maybe 1/4 of the maximum frequency... I am wondering how can we choose/buy an FPGA for a certain project in order to cover the frequencies demands of the project?

author: atom1477
author_rank: Newbie
timestamp: July 13, 2025, 04:53:07 pm
content: Quote from: 2X on July 13, 2025, 04:18:37 pmYes, because You may have multiple and asynchronous different clocks in one design. Also, maximum frequency strongly depend on Your design.Quote from: 2X on July 13, 2025, 04:18:37 pmSpecifically, when it comes to the pins themselves, it is concrete. I just don't see it for the MAXHXO device. This is old and retired device. But for MACHXO2 or ECP5, there are specific values for the CMOC or LVDS pins provided in the datasheets.Quote from: 2X on July 13, 2025, 04:18:37 pmA don't have experience witch MACHXO, but with newer devices it's approximately 200 MHz for CMOS and 400 MHz for LVDS.For IOs only! And with good PCB layout.Quote from: 2X on July 13, 2025, 04:18:37 pmFirst of all, LVDS25EisemulatedLDVS. So what I mentioned about LDVS, does not apply to this.You must search fortrue LVDSpins. If there are any at all in such an old device like MACHXO.Quote from: 2X on July 13, 2025, 04:18:37 pmwebSuch a statement is misleading. Using the input FFs is not mandatory. Therefore, the input frequency can be the full "several" MHz, not "half" of it.Quote from: 2X on July 13, 2025, 04:18:37 pm"Goog" information for You. Such a book or webpage does not exist. So you might as well not waste your time trying to find it.1/4 of maximum frequency is good estimation at the beginning. So, assume that in this case it's 100MHz.

author: ataradov
author_rank: Super Contributor
timestamp: July 13, 2025, 05:11:58 pm
content: Quote from: 2X on July 13, 2025, 04:46:02 pmNot really, especially given that FPGA vendors like to lie in different ways about their operating frequencies. And a lot depends on your design. If there is a lot of combinatorial logic, it will be slow.Quote from: 2X on July 13, 2025, 04:46:02 pmYou start with the software. Do the thing you think will be slowest in your design, create a test project and synthesize it. See the reported operating frequency.You don't need the hardware to start working with FPGAs. Most of the time you will be spending in the simulator anyway. The hardware becomes necessary when you are almost done with the project. At that time you will know the device required for the project.The alternative is to get a dev kit with the biggest device in the series and prototype ion that.

author: bson
author_rank: Unknown
timestamp: July 14, 2025, 06:22:12 pm
content: Here's a simple example from a MachXO2. Obviously the actual pins differ, but the device will have a preferred PLL REFCLK input pin.Note that the term 'clock' is a little different with FPGAs than MCUs; in FPGAs a clock technically speaking is any signal used to latch or synchronize on and doesn't have to be a repeating clock. Think a chip select for example, CS#.The clock generator is an LTC6905, in this examplethe 20/40/80MHz 20ppmvariety.

author: 2X
author_rank: Frequent Contributor
timestamp: July 14, 2025, 07:53:55 pm
content: Quote from: bson on July 14, 2025, 06:22:12 pmThanks for the reply.The link is not working.LTC6905IS5-80#TRPBFhttps://eu.mouser.com/ProductDetail/584-C6905IS5-80TRPBF

author: atom1477
author_rank: Newbie
timestamp: July 15, 2025, 06:04:11 am
content: Quote from: bson on July 14, 2025, 06:22:12 pmYou're wrong. For uC and FPGA, it's exactly the same: there are cases where the clock signal doesn't have to be continuous, and others where it must be (for example when it drives internal PLL).