PH processor (MIPS clone) wanted - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: July 12, 2014, 07:24:08 pm
content: hi guysgoogling i have foundthisproject that seems very very interesting, P.H. stands for "Patterson-Hennessy", so it looks a very good didactical thing, btw following its link i have reachedthisweb that is provided by Embedded Systems Laboratory, Department of Engineering of the University of Leicester (UK).Reading their web page i have seen all the features included in a download: they are exactly what i am looking for !QuoteUnfortunately the download link is broken and the email contact is obsoleted.Anyone that has downloaded this material ?

author: PA0PBZ
author_rank: Super Contributor
timestamp: July 12, 2014, 08:13:52 pm
content: Play around with the web.archive.org site. Some (older) downloads are still accessible like the ones here:http://web.archive.org/web/20061011194049/http://www.le.ac.uk/eg/embedded/PH.htmI did not check all possibilities, so there's a challenge for you

author: legacy
author_rank: Super Contributor
timestamp: July 12, 2014, 09:57:58 pm
content: thank you, it seems working

author: legacy
author_rank: Super Contributor
timestamp: July 12, 2014, 10:06:17 pm
content: yes, from sources it is the v1.0 release of the PH Processor{ MUL/DIV, exceptions, coprocessor } are not includedwandering if there is around the v2, too

author: legacy
author_rank: Super Contributor
timestamp: July 14, 2014, 03:40:45 pm
content: no body has the version2 ?

author: PA0PBZ
author_rank: Super Contributor
timestamp: July 14, 2014, 07:22:55 pm
content: Yes, I know this is the 1.0 release, that's why I said play around with the archive site. They have 61 copies from 2005-2013, so maybe there is something interesting hiding.

author: legacy
author_rank: Super Contributor
timestamp: July 14, 2014, 09:44:47 pm
content: wandering why they have removed the linkit was useful !i have alsto tried to contact the university, i hope somebody has archived sources and can provide them on demand.

author: Marco
author_rank: Super Contributor
timestamp: July 14, 2014, 11:25:25 pm
content: Unfortunately the sources were never on the University page to begin with, but on the TTE page. A company which seems to have made a restart under a new name.The original author seems to work at ARM now, you could try to contact him via linkedin if his uni email no longer works.

author: amyk
author_rank: Super Contributor
timestamp: July 15, 2014, 12:42:08 pm
content: Why are you interested inthiscore in particular? There are tons of MIPS cores on opencores.org

author: bwat
author_rank: Frequent Contributor
timestamp: July 15, 2014, 01:01:21 pm
content: Quote from: legacy on July 15, 2014, 12:57:31 pmThe one that is detailed in that book you've recommended to others maybe??

author: legacy
author_rank: Super Contributor
timestamp: July 15, 2014, 01:22:39 pm
content: Quote from: amyk on July 15, 2014, 12:42:08 pmbecause of its debug ideaabout OpenCores and "tons of MIPS core", can you provide me a good one ?I have also googled for implementations/tutorials realizing there are quite a few MIPS cores written in VHDL in the public domain:-1-plasma-> my comment about is something like that-2-minimips-> it needs a lot of work and code refactorin-3-hamblen->-4- PH …. sources are not still available, but its debug-idea seems very interesting, missing code, the v1 is no usable-5- may be OpenCores/ION -> his author has asked to wait a pair of months for his code restylingin particular, i am following these two:-ION: it may be good if his author will do code-refactor (as he has promised), actually it is using B16 memory model which is Xilinx Spartan3 only -> you have to fix things in oder to use on other platform, also it is missing a solid exception handler -> you have to fix the Cop0, and other things like that.-miniMips: it is a very mini project and it could be OK if you fix and improve stuff, for example it missed DIV, LB/SB, it has MUL and LW, SW, you have to implement CPU_BUS_SIZE in order to do load/store operation with byte=8bit (and lh/sw, ha stands for half=16bit) instead word=32bit only. Actually it is word-32bit-I/O-only. Also it has a bidirectional CPU bus (using 3state) and a lot of code that needs to be restyled: for example it also has CPU_reset out of clock'event construct-> bad code! Also it has a poor memory model of any real word usage. In short: you have to spend a lot of time on it, wandering if it is useful.

author: legacy
author_rank: Super Contributor
timestamp: July 15, 2014, 01:34:48 pm
content: Quote from: bwat on July 15, 2014, 01:01:21 pmthe one you have to write, and test, by yourself: there are a lot of things that are not covered in details: this book looks to me more like aproof of conceptabout how a CPU works and about how HDL works about design a CPU: it is good to learn and to have a summary idea of the whole but .. real life details are missing. Also i have not recommended this book, i have written thati was suggested about itand i have followed the advice about buying it: it's a bit different as the fact i haven't still read it for second timep.s.i have a "sample pdf" about this book, i have bought the "mobi" electronic format from Amazon, so i am trashing the pdf: in case send me a PM if you are interested, i can send you the pdf as "sample": that means two things, -1- as sample it is not complete but it is enough to evaluate the book, -2- you can use it to evaluate the book, and in case you like it, you can buy it.