Stitching vias - how many? (density) - Page 1
Forum section: electronics / general

author: shadewind
author_rank: Frequent Contributor
timestamp: July 08, 2011, 11:56:52 pm
content: I'm laying out a PCB for an LED driver and I want to stitch the top and bottom planes together. I have a ground plane which is mainly for grounding purposes except for the driver chip itself which has a die attach pad for thermal relief. I also have a large island for where the switching FET, freewheel diode and inductor meet and I intend for this to provide thermal relief for the FET and diode. I have an identical one on the bottom to be stitched together with the top one.How many should I use? Right now, I'm using a grid with 100 mil spacing but that results in a lot of vias (perhaps 200 on the whole board which is about 5 cm x 5 cm). Is that too much? How many should I use for the ground plane (which isn't so much for thermal relief) and how much for the switching island?

author: Unknown
author_rank: Unknown
timestamp: July 09, 2011, 11:38:46 am
content: lamda/20 where lamba is the wavelength of the highest frequency of concern with the propagation speed on whatever PCB material and stackup you are using.

author: shadewind
author_rank: Frequent Contributor
timestamp: July 09, 2011, 11:43:55 am
content: Quote from: Alex on July 09, 2011, 11:38:46 amBut I'm not really using that many high frequencies and I have nothing which is that important, I just want to create a low impedance ground path everywhere. For the switching island, I want to lower thermal resistance.This is what it looks like now:http://dl.dropbox.com/u/2462319/highpowerled.pdf

author: Unknown
author_rank: Unknown
timestamp: July 09, 2011, 11:49:50 am
content: Low impedance at what frequency? You should also pay attention to harmonics; products with a 1kHz clock fail EMC tests at 1MHz...You could then bring the via closer to the heat generating components and remove them from where they are not needed. possibly via-in-pad which is then flooded with solder when the component is soldered.

author: shadewind
author_rank: Frequent Contributor
timestamp: July 09, 2011, 01:36:52 pm
content: Quote from: Alex on July 09, 2011, 11:49:50 amI see. My switching frequency is 800 kHz so I suppose I have harmonics much higher than that though I'm not sure what the "highest" frequency of concern is and I'm not sure what the propagation speed for a 1.6 mm two layer board with 1 oz copper is either.Quote from: Alex on July 09, 2011, 11:49:50 amIs that a suggestion to reduce the number of vias? Any particular reason or just that it's unnecessary?I suppose that if I have vias in the pads of the FET and the Schottky diode, I wouldn't really need to stitch the layers together at any other points, right?

author: Unknown
author_rank: Unknown
timestamp: July 09, 2011, 02:14:38 pm
content: Is this a commercial product shade? What level of performance/compliance are you looking for?FR4 has a dielectric constant around 4.2 (hence the 4 in FR4), ballpark figure.You can use that to calculate propagation speed. But the PCB is quite small wrt switching speed + harmonics so you should be able to get away with standard pcb layout practices. Possibly slow down the rise and fall times of the switching transistor if there are issues.Some board houses (Eurocircuits) charge extra if you exceed some number. With the vias you will be offering an extra heat path from the component layer to the second copper layer. But that heat path will have much higher thermal impedance than the flooded vias-in -pad, so there will be little benefit. Do you have an indication of the dissipated (RMS) power?

author: shadewind
author_rank: Frequent Contributor
timestamp: July 09, 2011, 02:47:37 pm
content: Quote from: Alex on July 09, 2011, 02:14:38 pmNo this is not a commercial product, it's a hobby level project as might have guessed. If I was doing this professionally, I would expect myself to know all of this.I'm guesstimating the power dissipation of the diode and the FET to somewhere between 1W and 2W, probably closer to 1W.Right now, I'm using 0.3mm vias which is as small as the board house will go. Will that likely give me trouble? Should I go a bit larger?

author: jahonen
author_rank: Super Contributor
timestamp: July 09, 2011, 02:50:23 pm
content: I'd prefer somewhat larger "general-purpose" vias, say, 0.5 mm, if possible. Advantage is somewhat lower inductance and better manufacturability.Regards,Janne

author: Unknown
author_rank: Unknown
timestamp: July 09, 2011, 03:11:24 pm
content: Yeah, bigger via dia as opposed to more vias , and see if you can bring the power loss down by maybe using a lower RdsON FET. You could possibly utilise the area above C1 too. L1 will also act as a heatsink, so make sure the resistance of L1 is low so that it only contributes a fraction of the total loses. I see you have put a lot of effort to keep all the signal traces on top.I would use only the bottom layer as ground here and possibly move all the driving and control circuitry down to the currently empty space to free up more space for heatsinking on top.QuoteYou will be surprised...

author: shadewind
author_rank: Frequent Contributor
timestamp: July 09, 2011, 06:41:20 pm
content: Should I also make the vias located in pads bigger? Won't that drain out solder?

author: Unknown
author_rank: Unknown
timestamp: July 09, 2011, 06:49:53 pm
content: If you increase the top heatsink area by moving the rest of the components down then you can dissipate 1W without overheating the transistor. Otherwise you can add say 4 0.5 mm dia pads under, or immediately around, the drain of the transistor. If you do this make sure these pads have soldermask stop specified, so you can fill them with solder. Not sure what you mean by drain out solder.

author: shadewind
author_rank: Frequent Contributor
timestamp: July 09, 2011, 07:05:21 pm
content: Won't the solder drain out through the vias so that there's not enough solder left to make good thermal contact with the pad?

author: Unknown
author_rank: Unknown
timestamp: July 09, 2011, 07:13:59 pm
content: Ah..no, surface tension will keep it in the vias.