Port pins missing in Debug net list - Page 1
Forum section: electronics / general

author: notooth
author_rank: Contributor
timestamp: November 14, 2023, 04:03:20 am
content: I have this module with a 256 bit width port, but I see only 1 bit port in the Debug net list. Can anyone help?Code:module test (input aclk,output reg [255:0] responce_tdata = 0);always @(posedge aclk) beginresponce_tdata <= 256'h1111111111111111111111111111111111111111111111111111111111111111;endendmodule

author: Someone
author_rank: Super Contributor
timestamp: November 15, 2023, 01:03:27 am
content: Read the synthesis report (assuming you are adding debug pre-implementation) it will explain why the signal has changed.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 15, 2023, 01:17:53 am
content: Because all 256 bits are the same value (either all 0 or all 1) they have been deduplicated down to a single net.

author: BrianHG
author_rank: Super Contributor
timestamp: November 15, 2023, 01:45:12 am
content: Which Debug net list?Did you compile in something like Modelsim? The entire net should be visible.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 15, 2023, 03:18:41 am
content: Ah, I misread that but it doesn't matter. The zero bits are constant and can be eliminated entirely, only the bits that toggle need to exist at all, and they are all equal.

author: notooth
author_rank: Contributor
timestamp: November 15, 2023, 04:08:29 am
content: Quote from: Someone on November 15, 2023, 01:03:27 amI do not see any info about the signal has changed.

author: notooth
author_rank: Contributor
timestamp: November 15, 2023, 04:43:29 am
content: Quote from: ejeffrey on November 15, 2023, 01:17:53 amChanging the value to 256'hfedcba9876543210fedcba9876543210fedcba9876543210fedcba9876543210 did not fix the issue.

author: notooth
author_rank: Contributor
timestamp: November 15, 2023, 04:44:50 am
content: Quote from: BrianHG on November 15, 2023, 01:45:12 amIt is Vivado Debug Netlist.

author: notooth
author_rank: Contributor
timestamp: November 15, 2023, 04:50:15 am
content: Quote from: karpouzi9 on November 15, 2023, 03:46:48 amIt does not fix the issue.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 15, 2023, 03:28:02 pm
content: Quote from: notooth on November 15, 2023, 04:43:29 amDoesn't matter. All the bits initialized to zero and then set to zero will be eliminated entirely, all the bits initialized to zero but assigned to one will be combined into a single signal during synthesis.Try making a counter.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 15, 2023, 03:36:09 pm
content: Quote from: notooth on November 15, 2023, 04:50:15 amTo be clear I don't think there is an issue except for your expectation. The circuit you described only has one bit of unique information and the synthesizer has noted that and produced an equivalent netlist.

author: hamster_nz
author_rank: Super Contributor
timestamp: November 15, 2023, 07:25:03 pm
content: Have a look at addint the KEEP and DONT_TOUCH synthesis attributes.They can ensure that things don't get optimized out.

author: notooth
author_rank: Contributor
timestamp: November 16, 2023, 02:28:27 pm
content: I used DONT_TOUCH to keep all 256 bits of the port:Code:module test (input aclk,(* dont_touch = "yes" *) output reg [255:0] responce_tdata = 0);always @(posedge aclk) beginresponce_tdata <= 256'h1111111111111111111111111111111111111111111111111111111111111111;endendmoduleI can see the value 256'h1111111111111111111111111111111111111111111111111111111111111111 in the ILA window, but I got a different value when reading the XDMA c2h port which connected to it.

author: hamster_nz
author_rank: Super Contributor
timestamp: November 17, 2023, 04:24:27 am
content: Sounds like you have a new problem, one where us here have been given zero details.

author: Someone
author_rank: Super Contributor
timestamp: November 17, 2023, 04:39:28 am
content: Quote from: hamster_nz on November 17, 2023, 04:24:27 amThis huge complex system will work if you spoon feed me the fix for this tiny problem.... wishful thinking.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 17, 2023, 07:37:54 am
content: Quote from: hamster_nz on November 17, 2023, 04:24:27 amOr the original problem remains and the optimized out signals were a red herring. Either way there is no information.