Free ARM core for FPGA - Page 1
Forum section: electronics / general

author: CJay
author_rank: Super Contributor
timestamp: October 01, 2018, 08:53:44 pm
content: Well this looks funhttps://www.theregister.co.uk/2018/10/01/arm_cortex_m_xilinx/

author: nctnico
author_rank: Super Contributor
timestamp: October 01, 2018, 09:55:18 pm
content: That seems cool. Anyone going to try this and see what kind of performance can be achieved?

author: ataradov
author_rank: Super Contributor
timestamp: October 01, 2018, 10:07:47 pm
content: They've been available for a while. I have played with M1 in a simulator and synthesized a dummy project in FPGA. It does work, but given the licensing limitations and obfuscated code, it is not really practical for hobby use. Maybe if you actually plan to manufacture devices.Also, it is not clear why it says that is is only Xilinx. I've synthesized it for MAX10 without any issues. They may provide some better tools for Xilinx, of course. But the code is just a Verilog file, nothing special about it.EDIT: Actually the original DesignStart was CM0 with all the debug features removed. Not sure when they have switched to M1.

author: langwadt
author_rank: Super Contributor
timestamp: October 01, 2018, 10:19:19 pm
content: the problem is usually where do you find enough memory

author: nctnico
author_rank: Super Contributor
timestamp: October 01, 2018, 10:33:16 pm
content: Quote from: langwadt on October 01, 2018, 10:19:19 pmCortex M1 is microcontroller territory and many FPGAs have tens of KB of internal memory nowadays. And if that is not enough even on a Spartan6 you can connect many megabytes of fast DDR memory.

author: ataradov
author_rank: Super Contributor
timestamp: October 01, 2018, 10:38:50 pm
content: Looks like they separated into DesignStart Pro and DesignStart FPGA. The first one gives "real" cores for evaluation, but ultimate implementation in ASICs. The later gives you FPGA-optimized cores to be implemented in FPGAs. This is new.The problem is that FPGA vendors have their own cores well optimized for FPGAs and their memories, usually for free (with purchase of FPGA, or course). Not sure if ARM has enough advantage here.

author: nctnico
author_rank: Super Contributor
timestamp: October 01, 2018, 10:43:33 pm
content: To me the advantage would seem the use of a good compiler. I have the Lattice LM32 in a Xilinx FPGA in a couple of inherited projects.

author: langwadt
author_rank: Super Contributor
timestamp: October 01, 2018, 10:56:01 pm
content: Quote from: nctnico on October 01, 2018, 10:33:16 pmbut then you have not only spend quite a bit of logic resources for the core but also lots of memory spread out all over the fpga,which is fine if you are prototyping a custom chip before an expensive tapeout, I've done it back in the day of ARM7TDMI-Sbut for an actual product or once you start needing to add external memory an external MCU with ram and flash seems to make more sense

author: NorthGuy
author_rank: Super Contributor
timestamp: October 01, 2018, 11:33:47 pm
content: What's wrong with Zynq?

author: asmi
author_rank: Super Contributor
timestamp: October 01, 2018, 11:34:55 pm
content: Quote from: NorthGuy on October 01, 2018, 11:33:47 pmPrice

author: langwadt
author_rank: Super Contributor
timestamp: October 01, 2018, 11:40:26 pm
content: Quote from: asmi on October 01, 2018, 11:34:55 pmand a cortex-a9 is a very different from a cortex-m0

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 12:25:29 am
content: Quote from: langwadt on October 01, 2018, 10:56:01 pmFPGA gives you endless flexibility to use whatever memory you need, and not the only those supported by MCU of your choice, and share memory bandwidth with other modules of your system.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 02, 2018, 12:28:53 am
content: Quote from: langwadt on October 01, 2018, 11:40:26 pmYes, much better.

author: langwadt
author_rank: Super Contributor
timestamp: October 02, 2018, 12:34:12 am
content: Quote from: NorthGuy on October 02, 2018, 12:28:53 amit is like bicycle vs. an SUV, each have it's purpose

author: langwadt
author_rank: Super Contributor
timestamp: October 02, 2018, 12:38:37 am
content: Quote from: asmi on October 02, 2018, 12:25:29 ambut an FPGA is an expensive way to implement dumb memory

author: NorthGuy
author_rank: Super Contributor
timestamp: October 02, 2018, 02:19:39 am
content: Quote from: langwadt on October 02, 2018, 12:34:12 amAnd what's the purpose of building a soft M0 core in the fabric which cannot be achieved by the built-in A9 cores?

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 02:50:20 am
content: Quote from: NorthGuy on October 02, 2018, 02:19:39 amAbility to use much cheaper FPGAs like A7 or S7 as there are no built-in A9 cores.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 02, 2018, 03:19:00 am
content: Quote from: asmi on October 02, 2018, 02:50:20 amThis is impossible to discuss without knowing what is the resource utilization for these soft cores including memory supply etc.If your goal is to save money, you can get external real M0 "cores" for less than $1 a piece.

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 03:52:56 am
content: Quote from: NorthGuy on October 02, 2018, 03:19:00 amThis is very easy to figure out as the core is available for download. M1 core takes about 2k LUTs, 3k FFs and 3 BRAMs (in default configuration).Quote from: NorthGuy on October 02, 2018, 03:19:00 amZynq is about 2 times more expensive than equivalent Artix, while being a MASSIVE overkill if M1 suffices.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 02, 2018, 04:37:50 am
content: Quote from: asmi on October 02, 2018, 03:52:56 amNot really. There's no exact equivalency, butSmall Zynq: $46.13 -https://www.digikey.com/product-detail/en/xilinx-inc/XC7Z007S-1CLG225C/122-2002-ND/Similar Artix: $32.90 -https://www.digikey.com/product-detail/en/xilinx-inc/XC7A25T-1CPG238C/XC7A25T-1CPG238C-ND/Slightly bigger Artix to accommodate softcore: $40.04 -https://www.digikey.com/product-detail/en/xilinx-inc/XC7A35T-1CPG236C/122-1907-ND/orBig Artix-based Zinq - $113.89 -https://www.digikey.com/product-detail/en/xilinx-inc/XC7Z020-1CLG400C/122-1851-ND/Similar Artix - $125.58 -https://www.digikey.com/product-detail/en/xilinx-inc/XC7A100T-1CSG324C/122-1886-ND/

author: nctnico
author_rank: Super Contributor
timestamp: October 02, 2018, 06:23:29 am
content: Quote from: langwadt on October 01, 2018, 10:56:01 pmNot if you need to interface directly with peripherals inside the FPGA where you need to move a reasonable amount of data around. For some projects a soft core makes a lot of sense. One of the projects I'm involved in has an ARM CPU on board and a soft core is used to implement a fast realtime control loop (and other household tasks).@Northguy: a Zync adds too much complexity because the ARM cores in there are much more complex than a 'simple' Cortex M1 or M3.

author: a59d1
author_rank: Regular Contributor
timestamp: October 02, 2018, 07:24:07 am
content: Why would you want this instead of a picoRV2?

author: Kjelt
author_rank: Super Contributor
timestamp: October 02, 2018, 09:49:22 am
content: Cool, back in 2001 we needed something like this for prototyping, 25 pieces or something like that.I remember the quote from Arm being a high 5 numbers, way too much for just a prototype but they had only one pricescheme back then IIRC.We ended up using a Nios core instead.Why you want this? That could differ per solution in our case we needed a 1024 bit HW multiplier and other cryptorelated resources and time does matter so if you can directly copy the results to the core registers that can be really helpfull instead of serially clocking it in.A softcore can also bring advantages to protecting your product from cloners.

author: julianhigginson
author_rank: Frequent Contributor
timestamp: October 02, 2018, 11:50:37 am
content: I guess how well it goes will depend on how easy it is to use the arm core(s) with your custom logic, and how easy it is to get to everything you need to from your code... if it's easy to generate good hw API, and integrate with good arm toolchains, maybe it's worthwhile sometimes, assuming the soft arm is similar in resource use to similar existing options. there's plenty of existing options for running processor cores in your digital logic for programatic applications when you need something like that, so for this to gain a share of that space alongside the solutions that everyone already uses and knows, you'd want to see some advantages rather than just arm brand recognition....Seems to me that if you're considering one of these M1 or M3 cores to be the bulk of your design in a regular small FPGA like a Spartan or artix, well, you'd be far better off with microsemi smartfusion (or maybe even cypress psoc if the digital design requirements are simple enough...)Also don't forget the big A series processor zynq (and the newer A53/R5 cored socs) has another big advantage over straight FPGA. It also has a dedicated DDR controller... Very valuable if you have an application that needs a lot of memory storage coupled closely to your digital hw design, like lots of FPGA applications seem to.

author: nctnico
author_rank: Super Contributor
timestamp: October 02, 2018, 01:39:16 pm
content: Quote from: julianhigginson on October 02, 2018, 11:50:37 am(Almost) every modern FPGA has a hardware DDR memory controller nowadays so that doesn't really make a difference.

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 01:44:48 pm
content: Quote from: nctnico on October 02, 2018, 01:39:16 pmNone of 7 series FPGAs have hardware memory controllers. Their fabric is fast enough to allow "soft" implementation of these controllers, so MIG can generate any configuration you require, and even several controllers at the same time. It does take quite a bit of logical resources though, for example DDR3L x16 controller takes about 8k LUTs and 10k FFs.

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 01:48:13 pm
content: Quote from: NorthGuy on October 02, 2018, 04:37:50 amThis is not a fair comparison. How much is a Zynq version of A35T with four 6Gbps MGTs?There is much better selection of devices in Artix family. If you come just short on resources of a small Zynq, your next option is waaay more money, while with Artix scales up quite nicely.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 02, 2018, 02:08:15 pm
content: Quote from: asmi on October 02, 2018, 01:48:13 pmBoth Zynq and Spartans go to about 100K. With Artix'es the only device above 100K is A200T, but the experts say it should never be used:Quote from: asmi on April 22, 2018, 10:18:38 pm

author: julianhigginson
author_rank: Frequent Contributor
timestamp: October 02, 2018, 02:09:51 pm
content: Quote from: nctnico on October 02, 2018, 01:39:16 pmId be interested to know what device size and cost they start to appear at.It's certainly not in any of the smaller (artix) xilinx FPGAs that are cheaper than zynqs.

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 04:11:22 pm
content: Quote from: NorthGuy on October 02, 2018, 02:08:15 pmI'm not talking above - I'm talking below. Again - what is going to be Zynq version of A35 with 4 6Gpbs MGTs?Quote from: NorthGuy on October 02, 2018, 02:08:15 pmI meant it should never be used as a starting device, but it still is available as pin-compatible "size up" device in case design won't fit in A100 and it's too late to respin the board for completely new device.

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 04:13:58 pm
content: Quote from: julianhigginson on October 02, 2018, 02:09:51 pmNone of 7 series FPGA devices do because it's possible to implement them in logic if required. The only reason Zynqs have it is because lots of memory is all-but required for the MPU to be useful.

author: nctnico
author_rank: Super Contributor
timestamp: October 02, 2018, 04:21:44 pm
content: Quote from: julianhigginson on October 02, 2018, 02:09:51 pmSpartan6 for example.

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 04:34:59 pm
content: Quote from: nctnico on October 02, 2018, 04:21:44 pmThe core provided only for Vivado as and such 7 series devices and above.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 02, 2018, 04:36:27 pm
content: Quote from: julianhigginson on October 02, 2018, 02:09:51 pmIt is in all 7-series devices. Except the controllers are not monolithic. Rather there's a set of undocumented components, such as various kinds of PHASERs, frequency references, undocumented clock routing, undocumented clock options for SERDES's, byteline handling hardware etc. Xilinx's MIG IP uses all this stuff (along with regular fabric and documented components) to build DDR memory controllers.

author: nctnico
author_rank: Super Contributor
timestamp: October 02, 2018, 05:39:16 pm
content: Quote from: asmi on October 02, 2018, 04:34:59 pmIt is Verilog so I don't see any problems using a different tool. Someone else in this thread created a project using tools from a different manufacturer.

author: ataradov
author_rank: Super Contributor
timestamp: October 02, 2018, 05:44:40 pm
content: Quote from: nctnico on October 02, 2018, 05:39:16 pmIt is actually not clear. The DesignStart FPGA may not give you full Verilog, it is possible that they've made an exclusive deal with Xilinx and provide a locked IP core.I tried with DesignStart Pro (the only thing available at a time). It is still available, but it is not licensed for free commercial use, only for educational purposes.The whole DesignStart started with university programs and was only accessible to students. And then RISC V came along and ARM ended up worried and extended the program to everyone. Plus added M3 core as well, the original DesignStart only had M0.DesignStart FPGA has M1, which makes sense if you plan to keep in in a final FPGA-based product.

author: langwadt
author_rank: Super Contributor
timestamp: October 02, 2018, 06:03:15 pm
content: Quote from: asmi on October 02, 2018, 04:13:58 pmand I'd expect a hard DDR memory controller to be a fraction of the die area needed to implement it in logic

author: langwadt
author_rank: Super Contributor
timestamp: October 02, 2018, 06:09:46 pm
content: Quote from: julianhigginson on October 02, 2018, 11:50:37 amthe integrated cpu + fpga never really took of until they changed from "fpga with a cpu core" to "cpu with an fpga"

author: nctnico
author_rank: Super Contributor
timestamp: October 02, 2018, 06:25:14 pm
content: Quote from: langwadt on October 02, 2018, 06:09:46 pmIMHO this is also due to the previous CPU cores in Xilinx FPGAs being PowerPC based.

author: Bassman59
author_rank: Super Contributor
timestamp: October 02, 2018, 07:03:44 pm
content: Quote from: nctnico on October 02, 2018, 06:25:14 pmI don't blame the processor core in the Virtex 4 and 5 for issues with it.I blame the awful EDK and the awful Xilinx peripherals.

author: langwadt
author_rank: Super Contributor
timestamp: October 02, 2018, 07:04:42 pm
content: Quote from: nctnico on October 02, 2018, 06:25:14 pmmaybe that was also an issue, but having to add a bunch of stuff to a core just to get it to do something,and unless you added the same stuff as everyone else you need you to build you own OS etc. doesn't make it easier

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 07:31:08 pm
content: Back on topic...It looks like the current build will only allow to use Keil to build softwareAt least I couldn't make SDK to create an application project for CM1 - it doesn't let me reuse BSP project that I've created beforehand, but generating new one right in the wizard throws some errors. Hardware did build successfully though for my latest Artix board (I had to use MDM for UART as my board doesn't have dedicated UART port), but I don't want to bother with Keil as I would never be able to afford it anyway...So I guess I will wait until they fix all that.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 02, 2018, 07:34:26 pm
content: Quote from: langwadt on October 02, 2018, 06:03:15 pmThat's exactly one of the reasons why Zynq's PS DDR2/DDR3 controller makes the built-in ARM cores much more effective.BTW: Still waiting for you to describe the advantages of feeble soft M0 cores over built-in A9 cores of Zynq.

author: mac.6
author_rank: Regular Contributor
timestamp: October 02, 2018, 08:06:10 pm
content: easy: you don't need to roll full linux build to do simple microcontroller task

author: ataradov
author_rank: Super Contributor
timestamp: October 02, 2018, 08:06:57 pm
content: Quote from: mac.6 on October 02, 2018, 08:06:10 pmYou can easily do bare-metal stuff with A9. No need for Linux at all.

author: langwadt
author_rank: Super Contributor
timestamp: October 02, 2018, 08:10:39 pm
content: Quote from: NorthGuy on October 02, 2018, 07:34:26 pmhuh? they are two totally different classes of cpus, if all you need is a small state machine programmable in C or assemblyM0 fits the bill, if you need processsing power and linux A9 fits

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 08:43:57 pm
content: Quote from: NorthGuy on October 02, 2018, 07:34:26 pmReally? I think they are obvious. Lower power consumption, easier to code for, better packages (Zynqs <30 only exist in 0.8 mm pitch packages, I prefer 1.0 mm ones for routing reasons). And since they take so little resources, you can fit 10 of them into A35. How much is 10-core Zynq?

author: NorthGuy
author_rank: Super Contributor
timestamp: October 02, 2018, 10:10:18 pm
content: Quote from: langwadt on October 02, 2018, 08:10:39 pmIf all you need is a small state machine, it's best programmed directly in HDL.Quote from: asmi on October 02, 2018, 08:43:57 pmWhy would you trade FPGA for a dozen of ARM cores?Using langwadt analogy, it's like getting a fighter jet, melting it down, and making 10 bicycles.

author: bson
author_rank: Unknown
timestamp: October 02, 2018, 10:14:42 pm
content: Quote from: NorthGuy on October 02, 2018, 02:19:39 amThe A9 and your custom peripheral are going to sit at opposite ends of a bus, which is a shared resource and potential bottleneck, so often you're going to need to move any "thinking" to the peripheral end of the bus. The question as I see it isn't what a soft M1 can do that the A9 in a Zynq can't, but rather what kind of applications it excels at where other techniques like DSP blocks or sprawling logic/LUTs don't work as well, are difficult to get to work right, or are grossly resource inefficient. Or, where it can greatly reduce bus traffic; one such example might be a custom protocol bridge between two very different physical wires or networks. Say also add a monitoring port - with a soft M1 all this can be done in a peripheral without the back-and-forth copies across the bus. The M1 just interfaces directly to the transceivers, and has a control interface of higher level driver interactions (configurations, statistics, routing, error reporting, etc etc). The reason to use a CM of course instead of any ofter soft core is software familiarity (software quality improves with familiarity), tool chain quality and familiarity, and potential for code reuse. If you already have a protocol implementation in C/C++ with a long trusted history because you've used it in a bunch of projects already, then it's pretty sweet to just drop it into your soft core project and use without modification. You'll just need to figure out the platform end of things, like retransmit timers etc.

author: nctnico
author_rank: Super Contributor
timestamp: October 02, 2018, 10:19:59 pm
content: Quote from: NorthGuy on October 02, 2018, 10:10:18 pmNo. The turn-around time on a large FPGA design can be several hours compared to several seconds to recompile software. Sure you can do simulations but if you have real hardware 'in the loop' then that goes out of the window. No, I'm not talking external chips here but complicated external systems. Using software to solve a complicated problem is much quicker. One of the FPGA projects I'm responsible for takes at least 2 hours to build in a minimal setup. This has a softcore it is a lot quicker to change when doing algorithm & parameter tweaking.

author: asmi
author_rank: Super Contributor
timestamp: October 02, 2018, 11:12:12 pm
content: Quote from: NorthGuy on October 02, 2018, 10:10:18 pmI don't have to trade anything - I can have both, and with Zynq you can't

author: langwadt
author_rank: Super Contributor
timestamp: October 02, 2018, 11:31:06 pm
content: Quote from: nctnico on October 02, 2018, 10:19:59 pmand you can do in on the fly

author: langwadt
author_rank: Super Contributor
timestamp: October 02, 2018, 11:33:09 pm
content: Quote from: asmi on October 02, 2018, 11:12:12 pmsure you can if it fits in the PL and with a bit of trickery you could even run code from the A9 memory

author: NorthGuy
author_rank: Super Contributor
timestamp: October 03, 2018, 12:19:17 am
content: Quote from: bson on October 02, 2018, 10:14:42 pmFirst of all I would rule out data processing. Say, you have a core running at 200 MHz and producing some work at the loop. I guess, such loop will be at least 20 cycles (especially with ARM architecture), which means loops are coming at 10 MHz. Let's say, you can do the same task in fabric at 300 MHz. How do you replicate such performance with cores? Install 30 cores and distribute the processing? It may end up to be much bigger job than doing it with FSM in fabric. But may be you're content with 10 MHz? Why would I need FPGA in the first place?Housekeeping tasks? You certainly can do them with ARM core. Or without an ARM core. May be it's just me, but I don't care much how the housekeeping is done. Creating a counter in HDL is about as easy as in C.IMHO, soft cores might be used for complex UI, complicated command interfaces, long slow and diverse calculations. The more complex and diverse is the task, the more useful is the core, because it saves lots of fabric. But also, the more complex tasks will require more memory. You have a choice of really small cores, such as Picoblaze, where you can add custom commands to the stock core and make things working nicely and efficiently. Or, you can design your own cores which have a limited set of operations (exactly what you need). Another choice is a big core, such as ARM or Microblaze. If you seriously need it, I think Zynq is much better choice, because it is implemented in hardware, runs much faster, has autonomous memory. You put the PS into the center and use PL as a slave which does all the fast processing tasks and is controlled by the CPU. It's easy to develop your apps in PS, easy to re-compile and re-run (without even touching PL), and you have plenty of resources to spare. Such approach will save you tons of time, effort, and will produce an efficient system.I think there's some overlap between using Picoblaze/specialized cores and going Zynq. Soft ARM cores (or Microblaze for that matter) hardly can fit in between. Even if you want to get an ARM core because you're an ARM fan, Zynq is still ARM, so you've got to love it.

author: langwadt
author_rank: Super Contributor
timestamp: October 03, 2018, 12:29:03 am
content: Quote from: NorthGuy on October 03, 2018, 12:19:17 amif you do FSM in fabric it could take hours to make a change with code it takes minutes and designing your own core means making you own tools

author: NorthGuy
author_rank: Super Contributor
timestamp: October 03, 2018, 01:32:48 am
content: Quote from: langwadt on October 03, 2018, 12:29:03 amWho cares if your core only gives you 10% of the design speed. It's like bringing a bicycle to a drag race and say: "look guys, it took me only 2 minutes to prepare my bicycle for the race!"It doesn't take hours to make a change to HDL. You usually break it into parts and do piece by piece. Even when you need to compile a big project, it's not the end of the world. Although compile times are long (and I hate that), you figure out things to do while it is synthesising/optimizing/implementing ...

author: brucehoult
author_rank: Super Contributor
timestamp: October 03, 2018, 03:24:50 am
content: Quote from: a59d1 on October 02, 2018, 07:24:07 amThat's "PicoRV32". Or one of the other freely available RISC-V cores. Yes, good question.PicoRV32 needs on average about 4 clock cycles per instruction. But it runs at 400+ MHz on Xilinx 7-series, so it's 100+ MIPS. I don't think a soft M1 is going to be allowed to run that fast (an SoC M0+ is 50 MHz max, I suspect contractually).PicoRV32 can be configured to use as few as 810 LUTs, default about 1000, and all the bells and whistles (PCPI, IRQ, MUL, DIV, BARREL_SHIFTER, and COMPRESSED_ISA features) 2100.If you're writing in C then you're probably not going to notice a lot of difference. And if you don't need hardware multiply and divide or fast arbitrary shifts or super-compact code then you can save a lot of LUTs with PicoRV32. And you can mix and match exactly which of those *is* important to you.

author: asmi
author_rank: Super Contributor
timestamp: October 03, 2018, 03:52:59 am
content: Quote from: brucehoult on October 03, 2018, 03:24:50 amExample design for Arty-A7 has M1 core running at 100 MHz. And I kinda suspect it could be pushed farther if desired.

author: langwadt
author_rank: Super Contributor
timestamp: October 03, 2018, 12:37:53 pm
content: Quote from: NorthGuy on October 03, 2018, 01:32:48 amnot everything is a dragraceQuote from: NorthGuy on October 03, 2018, 01:32:48 amdoesn't matter why it takes long, the result is the same; it takes long much longer than software

author: mac.6
author_rank: Regular Contributor
timestamp: October 03, 2018, 01:01:42 pm
content: Everything in electronic/embedded is a dragrace. Not faster product but faster time to market...

author: langwadt
author_rank: Super Contributor
timestamp: October 03, 2018, 01:49:11 pm
content: Quote from: mac.6 on October 03, 2018, 01:01:42 pmand if it takes 20 minutes to get the dragcar ready to run the bike will be first across the line

author: NorthGuy
author_rank: Super Contributor
timestamp: October 03, 2018, 08:29:51 pm
content: Quote from: langwadt on October 03, 2018, 01:49:11 pmand then it takes only a little bit of marketing touch to convince people that the bicycle is in fact the best dragster.The force has a strong influence on a weak mind

author: langwadt
author_rank: Super Contributor
timestamp: October 03, 2018, 08:36:57 pm
content: Quote from: NorthGuy on October 03, 2018, 08:29:51 pmwho is convinced that "the bicycle is in fact the best dragster" ?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: October 04, 2018, 12:53:14 am
content: Gosh it's "free" for Xilinx stuff. (Yawn).Anyone here familiar with opencores?https://opencores.org/100+ different uC cores from different architectures (in variable state of maintenance). and lots of other stuff.

author: nctnico
author_rank: Super Contributor
timestamp: October 04, 2018, 05:05:45 pm
content: Quote from: Doctorandus_P on October 04, 2018, 12:53:14 amIf you ever used something from Opencores then you'll be cured quickly. 99.9% of it is pure rubbish.

author: legacy
author_rank: Super Contributor
timestamp: October 04, 2018, 06:00:48 pm
content: Quote from: nctnico on October 04, 2018, 05:05:45 pmI agree.

author: a59d1
author_rank: Regular Contributor
timestamp: October 04, 2018, 11:58:32 pm
content: Quote from: legacy on October 04, 2018, 06:00:48 pmI don't see anything wrong with the NEO430.https://opencores.org/websvn/filedetails?repname=neo430&path=%2Fneo430%2Ftrunk%2Frtl%2Fcore%2Fneo430_cpu.vhd

author: technix
author_rank: Super Contributor
timestamp: October 05, 2018, 02:37:41 am
content: AFAIK Xilinx FPGA contains hard DDR memory controllers and there is a reference implementation for a XIP-capable QSPI master. If you need a Cortex-M0+ with tons of RAM and Flash (e.g. 1GB RAM + 128MB Flash) this might be the only option available: Cortex-M0+ and two QSPI controller in the FPGA fabric, make use of that hard DRAM controller, two MT41K256M16 DDR3 chips on the DRAM controller, and two W25Q256 QSPI chips on the two QSPI controllers. (With more RAM than Flash, it is a better idea to link application code to run from DDR3, store it hard compressed in QSPI, and expand them into DDR3 in the bootloader.)

author: asmi
author_rank: Super Contributor
timestamp: November 05, 2018, 04:42:42 pm
content: M3 core is now available too. Didn't try it myself yet.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 05, 2018, 05:56:51 pm
content: Is ARM mandatory?You could try the Potato processor:https://github.com/skordal/potato