Dual mosfet - dual chip or not? - Page 1
Forum section: electronics / projects

author: dobsonr741
author_rank: Frequent Contributor
timestamp: June 16, 2023, 12:01:21 am
content: I have a few SI4511DY - I wonder if I can assume the SO8 package contains two independent chips or they are made on the same substrate?I think the prior, as the datasheet does not mention any limitations:https://www.vishay.com/docs/72223/72223.pdfNeither does any other comparable dual N-P mosfet package from other vendors.

author: Psi
author_rank: Super Contributor
timestamp: June 16, 2023, 12:07:27 am
content: Why does it matter?The datasheet should give isolation specs between each part regardless of how they are made internally.

author: dobsonr741
author_rank: Frequent Contributor
timestamp: June 16, 2023, 12:23:07 am
content: No word on isolation on the data sheet at all.

author: wraper
author_rank: Unknown
timestamp: June 16, 2023, 12:32:57 am
content: I don't think any of these are a single die. Does not make sense economically and there would be only downsides.

author: thm_w
author_rank: Super Contributor
timestamp: June 20, 2023, 11:31:34 pm
content: I tested on a few dual SOIC8 FETs I have here and do not have high enough voltage to see a breakdown.FDS6982 - dual N-Ch 30V- D1 to D2 breakdown = >2700VFDS8858 - dual N and P-CH 30V- D1 to D2 breakdown = >2700VSOIC pin spacing is about 1.3mm so there is already potential to arc between pins at around 2200V, worst case.Silicon is 1000V/um, the package itself would be a bit less than that. To me it seems you wouldn't need much extra silicon to ensure good isolation, die streets when cutting are already 75um wide.Capacitance was so low I couldn't measure it, <1pF?

author: jbb
author_rank: Super Contributor
timestamp: June 21, 2023, 12:40:23 am
content: If you’ve got a couple of spares, you can (sorta!) de-cap the package with some fine sandpaper (say 1500 grit). Then you can literally see the dice.Edit: or single die, of course

author: thm_w
author_rank: Super Contributor
timestamp: June 21, 2023, 01:29:05 am
content: Quote from: jbb on June 21, 2023, 12:40:23 amHere is the quick decap.Top has one die No bond wires visible, somehow the leadframe attaches to the die on the top and bottom.FDS8858 has two die, P-CH one is larger one, N-CH smaller, as both are rated about 8A. Many wire bonds go to each one.

author: wraper
author_rank: Unknown
timestamp: June 21, 2023, 03:19:10 pm
content: Quote from: thm_w on June 21, 2023, 01:29:05 amQuite expected. Producing two same type MOSFETs on a single die is almost the same as making just one. From my limited understanding, producing two different types on a single die should basically double the number of lithography processes needed if not worse.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 21, 2023, 04:05:50 pm
content: Not only will they be separate die, but the two drain tabs are separate as well -- obviously electrically, but thermally as well. Expect very high thermal resistance like 50 C/W differential between them -- heatsink both tabs for best performance, do not assume just one will do.Monolithic parts are very rare (boutique) today, and you will know it by the price.You can even get matched pair BJTs for current mirror service, for example -- they are matched dice, and in a say SOT-363 package, the Rth between chips is something like 500 C/W. Independent lead frames. (Consequently, they are usually careful to note what's needed for good performance -- keep current, and output voltage, low; or use a Wilson (cascoded) current mirror to enforce the latter.)The one thing I'm not sure about offhand, is the "FETky" family (and related) parts, whether monolithic or co-pack. I don't think there's any meaningful way to integrate schottky junctions into the FET structure? And having a diode off to the side would probably end up cheaper. Dunno.I do know IGBTs are almost all co-pack (and usually labeled as such) when integrated with diode, and diode arrays generally track well enough despite being multiple die (since they have a common-tab design; the dies are likely matched, too).Tim

author: TimNJ
author_rank: Super Contributor
timestamp: June 21, 2023, 04:32:10 pm
content: How about Darlington connected transistors?e.g. BCV46 (SOT-23), TIP22 (TO-220 +)I would figure the little Darlingtons are probably one die. But maybe not the big ones? I have no idea why you would or would not make it monolithic. Is it a yield thing?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 21, 2023, 06:08:43 pm
content: Think those are monolithic. The Darlington configuration is pretty convenient on a planar process; the transistor die photos thread has a few (10A+ I think?) examples. Would guess the old really big ones (1200V 30A+, triple BJT) are as well?Tim

author: magic
author_rank: Super Contributor
timestamp: June 21, 2023, 08:18:16 pm
content: The bulk of the die is the drain in vertical MOSFETs and the collector in vertical BJTs, remaining parts being thin layers on top of it.Hence it gets awkward to separate collectors or drains of transistors on one die, let alone of different polarities. This is what integrated circuit technology is about, and it seems that no one bothers with it if the customer isn't paying extra and then it further appears that no one pays extra for monolithic power transistor pairs for some reason, so dual dice they are.OTOH, making BJTs which share a collector is straightforward and Darlingtons are normally made this way. Nothing precludes a monolithic triple Darlington either, although those large brick modules might be multiple dice, hell knows. Maybe Noopy has photographed something of that sort?I don't recall seeing vertical MOSFETs with common drains, which would be the closest analog in the FET world. The FDS6982 is surprising, how are the drains isolated from each other and why are there no isolation breakdown ratings in the datasheet?Another thing is lateral MOSFETs, where the die is the bulk/body. I strongly suspect that dual gate (cascode) RF MOSFETs are made on one die.Nobody seems to be selling discrete lateral BJTs, where the base could potentially be shared by multiple transistors.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 21, 2023, 08:52:07 pm
content: Quote from: magic on June 21, 2023, 08:18:16 pmThat picture appears to be marked erroneously; the left side is clearly three source pins, an SO-8 single FET.QuoteRF FETs (typically LDMOS) also benefit from the lower power density (wider SOA for linear operation) and common source (ground plane is also heatsink).Lateral BJTs, good one.Tim

author: thm_w
author_rank: Super Contributor
timestamp: June 21, 2023, 10:43:23 pm
content: Quote from: T3sl4co1l on June 21, 2023, 08:52:07 pmGood eye. Must have mixed it up, that was single NFET as you say.Here is therealFDS6982- dual N-FET 6A, 8A, 30VNow, I just need to add a dual FET that has two of the same FETs instead of two different ones... maybe those would be the same die.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 21, 2023, 11:00:17 pm
content: That makes more sense; the PFET is also double size for similar rating.Tim

author: thm_w
author_rank: Super Contributor
timestamp: June 21, 2023, 11:05:41 pm
content: New contender,4925Ddual P-CH FET, 6A, 30VD1 -> D2 voltage = >2700V good isolation, same as before.Confirmed dual die also..Quote from: T3sl4co1l on June 21, 2023, 11:00:17 pmThat one is two different NFETs, kind of an oddball part, says for different laptop rails.

author: magic
author_rank: Super Contributor
timestamp: June 22, 2023, 08:24:53 am
content: No, it says it's for high-side and low-side switch of a single synchronous buck converter.I presume the larger one is the low-side, which conducts for most of the time when the step-down ratio is high, going from 19V to 5V or less.