FPGA high speed/ethernet data, how is it handled?? - Page 1
Forum section: electronics / beginners

author: steamedhams
author_rank: Regular Contributor
timestamp: July 02, 2021, 08:08:11 am
content: I have been thinking about doing some little projects to understand UART and FPGA..etcI bought a great 37 e bought MAX10 with every kind of perf you can thinking of.I would like to use the ethernet connection to communicate to other devices.If I read in a large packet, how should I find a specific tag in the data using an FPGA??FIFOs? On the fly?? dump it into memory using DMA?

author: Berni
author_rank: Super Contributor
timestamp: July 02, 2021, 08:30:04 am
content: It's not so much a question of how to handle it, but more a question of how do YOU want it handled, so that it fits well with what you want to do with that data. All of those are valid way of doing it. This is the main magic of a FPGA, you build your own peripherals that can be made to work however you want them to. For some applications you might never even store a packet in RAM and just process it as its coming in, for some you might hold onto just one packet in RAM for a bit of processing, for some you might store it in a large external RAM chip that can hold milions of packets.If you are just beginning with FPGAs then Ethernet is way too complex of a protocol to implement yourself. Tackle some simpler protocols first like serial ones. If you need high speed then an easy way are USB to CDC serial converter chips with parallel buses. Ones for USB 3.0 will do >200MB/s

author: RoadRunner
author_rank: Frequent Contributor
timestamp: July 02, 2021, 09:25:32 am
content: I do not want to hack this post, but does small FPGA have enough room for etherent? I see lot of Dev boards with small FPGA with only few hundred LUTs and have etherent PHY. Do the implement only basic data IO and have yet another custom device talk to it or do they implement something that can be used on any network.

author: steamedhams
author_rank: Regular Contributor
timestamp: July 02, 2021, 09:35:05 am
content: Berni had a good point though, you could just manage the data rate suited to the hardware.If my FIFO is small, I can just slow down the rate packets are sent so the fpga can have time to filter..

author: RoadRunner
author_rank: Frequent Contributor
timestamp: July 02, 2021, 09:42:08 am
content: Quote from: RoadRunner on July 02, 2021, 09:25:32 amDo people have things like DHCP client or ARP implemented on FPGA fabric ?

author: Berni
author_rank: Super Contributor
timestamp: July 02, 2021, 09:53:17 am
content: Well for doing something useful on a actual LAN network tends to require some sort of softcore to run the higher layers of the networking stack, so that you can actually get a IP address on the network. You can probably fit one into the small FPGAs if you try hard enugh but pretty sure you would barely have any of the FPGA remaining to actually do something useful with it.But if you throw away most of the networking stack and just connect two FPGA dev boards with a ethernet cable then you can use it as a glorified RS422 bus that runs at ridiculously fast 100Mbit or 1Gbit speeds. Most of the smarts for getting data onto the ethernet link are inside the PHY, so you can just do a minimal initialization of the PHY and start throwing blocks of data into it. So this requires very little in the way of FPGA logic.You can also get something in between if you only implement the MAC layer. This mostly just involves sticking some sender and recipient addressees along with a CRC in your data packet, so its resonably easy to generate one in a FPGA. This is enough to get network switches to route your packet around and for a PC network card to see the packet. So using this you could for example create some sort of high speed data capture device with ethernet output on that small FPGA.Another option is also to offload the higher network layers to a extra MCU that runs the higher up IP, TCP, UDP, ARP..etc in software. So the MCU can get the IP on the network and set up a UDP connection, then just hands the FPGA the appropriate packet header that it can just glue on in front of the data to make it a valid UDP packet. This now has the ability to travel trough routers and over the internet.

author: steamedhams
author_rank: Regular Contributor
timestamp: July 02, 2021, 11:27:00 am
content: I am not worthyI want to learn more, any resources you could recommend?

author: rstofer
author_rank: Super Contributor
timestamp: July 02, 2021, 04:38:11 pm
content: Take a look at lwip (Lightweight IP) to get an idea about how the stack goes togetherhttps://savannah.nongnu.org/projects/lwip/An obvious solution is to implement the MAC layer in FPGA fabric and then implement a CPU core that can be programmed in a higher level language to handle the protocols. Altera NIOS or Xilinx microBlaze are candidates as is the Zynq platform with a built in ARM core. Linux will run on a Zynq board so all of the work has already been done.https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841961/Zynq+LinuxHamster_nz did some MAC code on the FPGA forum a year or two back.I didn't find it in a quick search but it's there somewhere.It was just a bandwidth test but very useful code. I found the thread but the link to Hamster_nz's code is broken. Perhaps the webserver example will better serve your needshttps://www.eevblog.com/forum/microcontrollers/need-some-advice-on-transferring-data-from-lvds-to-ethernet-around-60-mbits/As is a webserver in some state of completion on his githubhttps://github.com/hamsternzThere are other projects at OpenCores.org

author: radiolistener
author_rank: Super Contributor
timestamp: July 03, 2021, 04:53:40 am
content: Quote from: RoadRunner on July 02, 2021, 09:25:32 amIt depends on what kind of protocol you're want to implement with hardware logic. For example, if you're needs just a physical layer of ethernet to send some signal over media from one device to another, it doesn't require a lot of logic. But on the other hand, if you're needs to implement all protocol stacks with large packets and packet processing it require a lot of high speed logic and memory.Of course, if your FPGA has only a few hundred LUTs, this is not enough to implement full IP/UDP stack.

author: radiolistener
author_rank: Super Contributor
timestamp: July 03, 2021, 05:07:03 am
content: Quote from: RoadRunner on July 02, 2021, 09:42:08 amYes, ARP + DHCP + UDP stack needs for about 4-6 kLE on a Cyclone 4 or Cyclone 10 FPGA. But it doesn't include logic to parse UDP packet content, it just have FIFO which provide you with UDP packet.With optimizations and simplification, simple protocol stack can fit at about 1-2 kLE.In my case, with custom protocol over UDP it needs about 5 kLE and a half of RAM blocks on EP4CE22. So, protocol stack eats almost a half of available resources.I think it's crazy to start with ethernet implementation if you're novice in FPGAYou can look at implementation of IP/UDP stack from Alex Forencich on github:https://github.com/alexforencich/verilog-ethernetIt include collection of ethernet components for 100M, 1G, 10G, and 25G packet processing, include 8 bit and 64 bit datapaths. With a nice speed auto-detection from the stream which doesn't require to read/write PHY registers through MDIO bus.