who uses fpga's - Page 1
Forum section: electronics / beginners

author: Capernicus
author_rank: Frequent Contributor
timestamp: March 31, 2021, 11:14:06 am
content: I'm just a GPU nut, I've doing it with direct compute ever since I was 21 doing direct x 6 win32 tutorials watching Martin Short on tv back in the olden days possibly 10 years after inner-space came out. I loved that movie, it was absolute magic and the robot suit's were fricken amazing! and as I think back terrify the absolute shit out of me now if it ever became a reality. curse the singularity.So the biggest mystery to me now is, now I'm old,40 sick still feel and look like an immature teenager and just about carked it in the head, what the hell are FPGA's and who uses them -and what do they use them for?They seem to be a step up from GPU's in what I imagine about them, but thats only a fantasy because I never got the guts to work on them.One thing that put me off was the cheap ones seem to only go to a megahert for some reason and that ruins the performance interest somewhat of what I thought they could do for me, so I put them off and just kept going with GPUs because they apparently hert quicker. and whats the difference between any type of physical parallelization, isnt it all equally as good as itself?But has anyone here got some real experience with them - is there any forums to go to get tips off guys that have been doing it for ages?The only implementations I've scarcely heard about is people use them to emulate old computers perfectly, but that is to me so uncreative and not even capitalizing on the power to do some original logic with them, at a modern performance, as long as it fit on the FPGA, isnt it as good as an ASIC - its just with a little wasted space here and there - that seems more like what I'd like to do with it.GPU's are what I know, and they are good for AI because you can do lots of brute forcing with them, when it comes to FPGA's is the brute forcing ability higher than a GPU?

author: agehall
author_rank: Frequent Contributor
timestamp: March 31, 2021, 12:30:30 pm
content: FPGAs can be anything you want them to be. They are programmable logic, on a large scale. They are very different from GPUs and I don't really think you can compare the two in any meaningful way.There is a whole section on this forum dedicated to FPGAs where you can see what people are doing with them. I've used them for custom I/O bridges myself where I need to work with a parallel interface and turn it into a serialized form or vice versa but that is a very trivial usecase.

author: mvs
author_rank: Frequent Contributor
timestamp: March 31, 2021, 01:29:45 pm
content: Quote from: Capernicus on March 31, 2021, 11:14:06 amAI and neuronal networks are based matrix multiplication. You do not need any flexibility of a FPGA hier.An ASIC with a large amount of matrix multiplier units, like nVidia A100 GPU, will do the job better then any FPGA existent on the market today.

author: SilverSolder
author_rank: Super Contributor
timestamp: March 31, 2021, 01:30:15 pm
content: Crypto mining is apparently a popular application...

author: CaptDon
author_rank: Super Contributor
timestamp: March 31, 2021, 02:03:08 pm
content: Most of my applications for programmable logic were small enough that I preferred to use CPLD's instead of FPGA's. The biggest difference for me was that a CPLD 'is what it is' directly on power up. An FPGA generally requires some time to 'get educated' from a serial eprom and with EMI glitches an FPGA can suddenly go stupid and lose its programming. A CPLD is more robust and they both can usually use a similar JTAG programming device. FPGA's can be huge and a real workhorse, CPLD's tend to be much smaller in flop capacity and are more for simple logic steering, lookup matix 'corn cob' lookup tables or simple clock signal buffering, steering and dividing.

author: rstofer
author_rank: Super Contributor
timestamp: March 31, 2021, 02:11:28 pm
content: You can think of an FPGA as a dumpster-full of unconnected logic chips. Connect them up to do what you want!I tend to think in terms of CPUs. I used the Z80 core from OpenCores.org to recreate a Z80 system complete with a Compact Flash disk drive and the CP/M operating system. I extended the idea and recreated an IBM 1130 minicomputer that runs all of the factory software unchanged. I use it as a computing platform from time to time where Fortran and/or plotting is required.I have also created a version of the LC3 CPU that is so popular at universities for an undergraduate course in computer architecture.

author: rstofer
author_rank: Super Contributor
timestamp: March 31, 2021, 02:47:20 pm
content: In terms of raw computing, I would expect the GPUs to win. Easily...I have a Jetson Nano and it's spec'd at about 472 GFlops and TFlop versions are readily available. It would take a heck of an FPGA to keep up with something like that. OTOH, my FPGA can have a half dozen SPI channels or any other interface I want. I can add parallel channels and talk to multiple devices concurrently. FPGAs are a great deal more flexible but in terms of raw compute power, I don't think they can win.When we went to the Moon the CDC 6400 was good for a MFlop or so. The modern Jetson Nano GPU is about 150,000 times faster.I'm just getting started with the Nano and haven't even a clue about what I'm going to do with it. I don't tend to have a lot of math problems waiting for a parallel solution.

author: SilverSolder
author_rank: Super Contributor
timestamp: March 31, 2021, 03:17:09 pm
content: Quote from: rstofer on March 31, 2021, 02:47:20 pmGive your daughter a credit card?

author: Siwastaja
author_rank: Super Contributor
timestamp: March 31, 2021, 04:10:03 pm
content: All those application-specific digital, computationally heavy integrated circuits, but in cases when you can't sell millions of units so can't warrant ASIC design. You only sell from one unit to maybe hundred thousand, so you use FPGA.Image processing, audio processing, communication, non-trivial cases of power conversion, crypto applications, ...I have made film scanner control / image processing, and some motor controllers on FPGAs.Widely used in network routers as well whenever the router is either too new, or too unique of an snowflake professional piece, so it can't include the ASIC which takes a year more development than the FPGA and requires sales in millions.I'm also quite sure an MRI machine contains a metric shitload of FPGAs.

author: rstofer
author_rank: Super Contributor
timestamp: March 31, 2021, 04:54:38 pm
content: Quote from: Capernicus on March 31, 2021, 11:14:06 amVHDLwhiz.com nandland.com and likely a couple of hundred others. I highly recommend VHDLwhizQuoteUncreative? Perhaps...The thing is, back in early 1970, I was introduced to the IBM 1130 computer system and began using one extensively. Almost all day, every day. Sometimes for company work, sometimes for college work (Bode' Plots weren't easy back in 1970). I loved that machine!And, like all loves, I was disappointed when we were separated. I wanted to use the identical software in 2005 that I used in 1970. So I built one! Every line of IBM code works including the 27 pass FORTRAN compiler.I had made another attempt to build the machine using with TTL, microprogramming and blown-link PROMS back around '75 or so but the 2102 static ram wasn't readily available. And, really, I would need 512 of them to create a 32kx16bit memory. That's a LOT of wire-wrap.I put the project on back-burner for 30 years and finally got what I wanted with a Spartan III FPGA. I did the Z80 CP/M project with a Spartan II (a 5V device which I still have).Everybody remembers their first love. I got mine back!FWIW, you probably get higher speeds and lower power with ASIC versus FPGA. Or so sayeth Google.http://ibm1130.org/

author: JohnnyMalaria
author_rank: Super Contributor
timestamp: March 31, 2021, 05:41:58 pm
content: I'm only in the early stages of FPGA application development but here's what I can already do with a $100 FPGA chip:1. Capture an I-Q pair of analog signals (FPGA controls the SPI communication etc) typically at 16-bit/32kHz2. Calculate the amplitude and phase3. Modify the phase according to my patent4. Calculate a modified I-Q pair5. Decimate all IQ data to 1kHz through a suitable IIR filter6. Calculate Fourier transform of both IQ pairs (1024 point)7. Do some other calculations based on phase.8. Average and store data in local block RAM9. Every second, raise an interrupt for a processor to copy the data for subsequent processing. Because I'm using a Zynq SoC, the FPGA and a dual-core ARM processor are built into the same physical chip.For every one-second of data I capture, the FFTs are ready within 50 microseconds of arrival of the last data. No software required.

author: fourfathom
author_rank: Super Contributor
timestamp: March 31, 2021, 06:10:14 pm
content: Here's my latest FPGA design, using a $5.00 Lattice MachX02 device:A four-channel event timestamper, using an external 10 MHz clock (or an on-board TCXO), driving the FPGA internal PLL at 100 MHz. This gives me 10ns timstamp resolution, selectable rising/falling edge detection, selectable prescalers and dividers for each channel, a 48-bit wide timestamp FIFO with SPI interface for the whole thing, as well as miscellaneous logic functions. I have the FPGA connected to a ATSAMD21 uController.The entire board, with input signal-conditioning, termination selection, AC/DC coupling selection, and display, is powered from the USB interface. The uController processes these timestamps for frequency/period/duty-cycle measurements, and event tagging. This handles input frequencies up to 200+ MHz and events many weeks apart, four independent channels.

author: Kerlin
author_rank: Regular Contributor
timestamp: March 31, 2021, 10:10:28 pm
content: In my experience the biggest use of FPGAs has been clearly where the designer wants to hide the design secrets of a piece of equipment.I have seen them used most extensively in military and avionics equipment.The other applications have been where speed and a cheap price is a requirement, like the dash cam I fitted to my car.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 01, 2021, 11:36:35 am
content: Thanks for all the replys, sorry I was sick and I to sleep for a day.Quote from: rstofer on March 31, 2021, 02:47:20 pmA Jetson Nano is a tiny GPU, and if that can already beat an FPGA, FPGAs are useless!!Quote from: JohnnyMalaria on March 31, 2021, 05:41:58 pmYes I realize you put in a method, and to get parallel power, you just put the same method repeated in more than once. Did that use up all the resources of the FPGA?How many times you put that code into the FPGA to run it more than once in parallel? Isnt the more expensive the FPGA the more gates it has?

author: JohnnyMalaria
author_rank: Super Contributor
timestamp: April 01, 2021, 12:29:40 pm
content: Quote from: Capernicus on April 01, 2021, 11:36:35 amThat's not how it works. You don't put multiple copies of the methods in parallel. You exploit the fact that every flip-flop etc in the logic is clocked and simply responds every clock cycle to whatever it's connected to. So, one area of the FPGA logic could be doing an FFT and another creating a MIDI stream of Happy Birthday. And another could implement an HDMI interface to drive a display. The power comes from the speed. In my case, for example, new analog data arrive every 30 microseconds. With the chip running at 100 MHz, that's 30,000 clock cycles between new data. In my current design, the FFT uses about 3% of the FPGA's resources.

author: joeqsmith
author_rank: Super Contributor
timestamp: April 01, 2021, 01:32:57 pm
content: Quote from: Capernicus on March 31, 2021, 11:14:06 amI have very limited experience using GPUs. For most things I do, they are a poor choice. In most cases, they wouldn't even be an option as I tend to work more on the hardware side of things. More often than not, I will use an FPGA in cases where I require critical timing. Sorry, I can't provide you with too many examples and sadly, nothing recent. Shown below is my Hayabusa hardware in the loop simulator. The simulator starts around 37:00 in. Because Windows doesn't make for a great realtime OS, most of the heavy lifting is done in an FPGA.Here are some very old boards I built back in the 90s to play around with my own CPU designs.Here is a reverse print server I built using an FPGA and Motorola 6811. The FPGA handles the DRAM, DMA, printer port. The CPU handles the high level Ethernet stack (I wrote in assembler).Today, even the smallest parts would out perform anything I have shown in these videos. About 4 years ago I purchased a cheap Xilinx eval board and had some fun with it. I could clock that part in excess of 700MHz. Here you can see it generating pseudo random patterns on the scope.https://www.eevblog.com/forum/microcontrollers/typical-speed-of-fpgas/msg1274875/#msg1274875

author: jmelson
author_rank: Super Contributor
timestamp: April 01, 2021, 03:50:09 pm
content: Quote from: Capernicus on April 01, 2021, 11:36:35 amI make a line of products that all use FPGAs or CPLDs. The FPGA does many things at the same time. On one device it watches quadrature encoders for any transitions, performing digital filtering from 1 to 10 MHz, so it can count up to 5 million quadrature transitions a second with a guarantee to not miss any. It does that on 4 encoders in parallel. It also generates 4 PWM signals with a 40 MHz clock, so you have 25 ns steps of pulse width. And, it also communicates with a host CPU and some digital I/O. While that can be done with a CPU, a CPU only does ONE THING at a time. Guarantees to not miss any encoder counts or to give very precise PWM timing become difficult. This is all done in ONE $10 chip with a $0.69 serial EPROM to store the configuration.For massive number crunching, CPUs and GPUs have an advantage. For interfacing to real-world events and doing many things at once, FPGAs really can show an advantage.Jon

author: rstofer
author_rank: Super Contributor
timestamp: April 01, 2021, 03:59:36 pm
content: I built the IBM1130 around a Spartan 3 1200k device which has 1.2 million system gates. That's a fairly large chip as things go.The system includes a CPU plus emulations for the card reader, line printer, keyboard, typewriter (all wind up as serial ports) plus a Compact Flash and an SPI channel delivering plotter step commands to an LPC1768 ARM chip that converts the steps to HPGL sentences and sends plots to my networked LaserJet. It's not a drum plotter but it works pretty well. See attached PlotArea.png -- yes, I get carried away sometimes.This easily fits in the device and, in fact, uses just 25% of the LUTs (Look Up Tables) - see attached summary.These days, the hot setup is the Artix 7 and I prefer the 100T variant and my project would use on the order of 17% of the available slices. Maybe less because the Artix uses 6 input LUTs and the Spartan 3 only used 4 input LUTs. And I wouldn't have to go off-chip to create the RAM. The system maximum is 32k x 16bits. Fits pretty easy in the massive BlockRAM of the 100T.That 100T device is like a virtual dumpster full of logic and it's reasonably priced on Digilent boards. See page 3 of the attached .pdfhttps://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/

author: rstofer
author_rank: Super Contributor
timestamp: April 01, 2021, 04:17:04 pm
content: Quote from: Capernicus on April 01, 2021, 11:36:35 amI'm just starting with GPUs so I know exactly nothing.One question though: How do I use a GPU to create that PlotArea graph I posted above. It has to start out using an obsolete version of FORTRAN and wind up as step pulses sent over SPI to an off-board gadget that converts them to HPGL sentences and forwards them to a LaserJet over TCP/IP. Let's just omit that part, it could still be external to the GPU.I'm not betting that the GPU is any part of the solution to that requirement. Maybe it could compute the points for the graph but that's about it. Math isn't the big part of this project.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 01, 2021, 05:00:18 pm
content: joeqsmith! thats amazing stuff, so u build your own computers from scratch. I loved the pong game, it was so cool watching that old computer go faster than our computers today even with gigahert clock speeds!! Things have gone backwards somewhat.Thanks for the videos, really fun educational stuff. Things seem a little decietful with this computer stuff (but maybe its just nonsense in my head), I'll eventually work it out tho, just have to keep seeing things here and there and thinking.Quote from: rstofer on April 01, 2021, 03:59:36 pmSo u can build a computer from scratch too - Thats majorly cool.If u took up 25% of the FPGA with a cpu - Couldn't you put 4 of them on the chip then and run em asynch? Im a little confused, its what your like when your just started at the bum of the mountain ready to shoot past the apex and fly like an eagle.Quote from: rstofer on April 01, 2021, 03:59:36 pmJust do the function range in parallel, just make sure you are using at least as much threads as cuda cores on your machine and then its saturated and should be 99% efficiency. Another thing that affects efficiency (alot) is accessing less video ram in the code, the more ram that is repeat accessed the more u get the memory lookup for free. (Thats even between all of the cuda cores) doing maths functions slows you down, it actually goes worse than what I was expecting it too, u go fast for accessing small lookup tables than doing maths functions (as long as there is alot of repeat reads), unexpectedly.I'm gathering all the information, which I thank everyone for.The best idea I have right now, about these FPGA's even tho I dont know much about them (Im a programmer, not a hardware guy) Is if you put in a simpler computer, it means that you get more repeats of it than a complex computer, so if its a frogger computer, you get to run more at once than if its a doom computer. (More effective framerate.)Even tho that rings true to just running software as a programmer as well, its the same.Ill definitely try an FPGA forum next time, instead of in the beginners section, thanks everyone for the replys.

author: crossroad
author_rank: Contributor
timestamp: April 01, 2021, 05:25:57 pm
content: Quote from: Capernicus on April 01, 2021, 05:00:18 pmGlue logic to make multiple cores work together efficiently is non trivial.I notice that you seem to focus on "how much you can pack into and FPGA" and comparing them to modern CPUs and GPUs solely by numerical performance metrics. A big part of what makes FPGAs so useful for certain applications is their ability to perform parallel operations with guaranteed latency. They can do that while often having lower power consumption and heat output and program complexity, which are desirable in embedded real time designs.I'm working on an FMCW radar that uses a Zynq to do some DSP preprocessing/filtering that cannot be matched by microcontrollers (example 50 Msps and 1 GHz clock = 20 cycles between each sample, which is absolutely not enough. 1 GHz in microcontrollers is pretty rare too, though NXP i.MX can reach that) while the FPGA can do it easily. Of course, it's very possible to use a much more powerful modern CPU for this but it would be inefficient and a downright awful engineering decision

author: rstofer
author_rank: Super Contributor
timestamp: April 01, 2021, 05:50:32 pm
content: Quote from: Capernicus on April 01, 2021, 05:00:18 pmSure and with an amazing amount of effort, multiple CPUs could share the RAM in some way. But since the OS doesn't understand such mechanizations, and the OS is cast in stone, I'm not sure of the utility. But, yes, multiple cores would work. In a more general case, of course they would work.ETA: The IBM 1130 came with various hardware devices. I chose to implement the devices that used DMA transfer versus character interrupt transfer. I just implemented a DMA channel and hooked up all the devices (CPU, Card Reader, Line Printer, Disk, Keyboard, Typewriter, Plotter) with a priority scheme. I was using off-chip memory so I couldn't take advantage of the DualPort BlockRAM. FWIW, the CPU must have the lowest priority or no other device will ever get a cycle.I never finished working on the problem but microMouse maze solvers usually use a flood-fill algorithm. I decided to create a single universal cell (tile) that computed it's value based on the neighbors and then replicating that tile for the entire matrix of 256 cells. The idea was to get some parallelism in computing the path. It still winds up being a serial operation but not for the entire matrix of 256 entries. There's an opportunity for some parallelism.Once the solution is found, the second pass is easily taken using the value in the computed cells.https://en.wikipedia.org/wiki/Micromousehttps://en.wikipedia.org/wiki/Flood_fillThere is also the possibility of creating CPUs that don't exist. I worked at using the output of Niklaus Wirth's P4 Pascal Compiler project as native instructions. It's not hard, the entire code is just stack operations. I got hung up when I had to implement complex instructions like floating point multiply and, later, I came to the conclusion that I could take them out of the main state machine or even implement a system call of some kind. In the real world, the output code ran on an interpreter on a CDC 6400.http://pascal.hansotten.com/niklaus-wirth/px-compilers/p4-compiler/Back around 1980, the UCSD variant of the P4 project was very popular on small computers. I did a lot of work adding IO devices to UCSD Pascal. I truly enjoyed using the language.Who wouldn't want an Apollo Guidance Computer?https://github.com/rzinkstok/fpga_agchttps://github.com/virtualagc/agc_simulationNo, I haven't pursued these.One more thing: PacMan! The OpenCores T80 (Z80) core will run PacMan with the original ROMs. There is nothing quite so iconic as PacMan. I mean Galaga is great but PacMan is historic. Yes, I have the electronics (Digilent Nexys 2 board), I just don't have room for the bar table. I do have room for a full size arcade cabinet running MAME (PC based but another way to get PacMan).https://www.mamedev.org/This system plays a LOT of the old arcade games - probably more than a thousand by now. I built my cabinet after I retired back in '03.There are a number of sites dealing with vintage games. Here is one:https://www.fpgaarcade.com/

author: SilverSolder
author_rank: Super Contributor
timestamp: April 01, 2021, 05:58:32 pm
content: Quote from: rstofer on April 01, 2021, 05:50:32 pmHa, that's funny - I learned to program on an Apple ][e using UCSD Pascal... and even used it on early PCs. Very cool environment!An FPGA P-machine would be an awesome thing!These days I use Delphi when I can, and find it more enjoyable than other environments.

author: rstofer
author_rank: Super Contributor
timestamp: April 01, 2021, 06:21:28 pm
content: Quote from: SilverSolder on April 01, 2021, 05:58:32 pmIt would be smokin' fast!UCSD Pascal was fast even on 6 MHz Z80s and an interpreter. Imagine native P code at 100 MHz (or more).I really like Wirth's book "Algorithms Plus Data Structures = Programs". It is my favorite text on data structures and traversing. I have implemented that P0 compiler from the last chapter several times. I actually think I understand recursive descent compilers.https://www.alibris.com/booksearch?mtype=B&keyword=niklaus+wirthOur local community college has a Pascal course as one of the very first in the sequence of computer science. I doubt that anybody is still using it but it remains my favorite language. I haven't worked with Delphi but I know I would like it. Today we can use Astrobe on ARMs and FPGAs. Astrobe is a variant of Oberon which is an upgrade from Modula which is an upgrade from Pascal which is an upgrade from Algol. Or something like that...https://www.astrobe.com/I would still like Algol. In school I had to write a compiler for a tiny version of Algol using, of all things, Basic. It was UGLY! Had I thought through it, I would have written a very tiny version and then bootstrapped up to something workable. Kind of like that P0 compiler. It would be possible to use that to write the P4 compiler in some series of steps.

author: mvs
author_rank: Frequent Contributor
timestamp: April 01, 2021, 06:22:03 pm
content: Quote from: Capernicus on April 01, 2021, 05:00:18 pmYes, you can, but this is not the best way to increase performance. The funny thing about FPGA is that you can build a CPU that is designed/optimized for the task. For instance if you have a need to do crypto - you can implement instructions for modular and big integer arythmetic, crypto functions or even whole algorithms in hardware.You are also not restricted with word length in any way. It does not need to be even a power of 2.

author: SilverSolder
author_rank: Super Contributor
timestamp: April 01, 2021, 06:40:55 pm
content: Quote from: rstofer on April 01, 2021, 06:21:28 pmOne of Delphi's claims to fame is that Object Pascal can be compiled in a single pass - you can compile almost as fast as the source code can be read off the drive! It is truly amazing, almost like working with an interpreter...All of the different programming languages have stolen the best ideas from each other these days, pretty much. So now it just boils down to what is supported and works well for you - rarely will you miss out on anything...Native P-code would be crazy cool - imagine a P-code transputer, to parallelize the load... something for a Sunday afternoon project?

author: rstofer
author_rank: Super Contributor
timestamp: April 01, 2021, 08:13:56 pm
content: Quote from: SilverSolder on April 01, 2021, 06:40:55 pmLet's skip over Python's white space indentation rules. I'm not found of the : operator either. But, yes, it is a lot easier to write loops and conditionals with modern languages. I never really like the 3 way IF branch of early incantations of FORTRAN. For mathematics, it worked well. For business programming it was a bit awkward. And the lack of an ELSE target. Well, we didn't have logical expressions anyway.But only in the Algol .. Pascal .. Oberon branch do we have nested procedures and functions. The first thing I missed when I changed to C was block structured code. When parsing an expression, recursive descent and block structuring is a natural approach. PL/I is also block structured.QuoteI'm afraid I'm not that prolific...

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 01, 2021, 08:42:16 pm
content: Has anyone ever heard of Instruction Level Parallelism?It actually is a serial code -> parallel code converter, because it can run serial code in parallel, given a latency of the string length of the sequence. You have to wait for it to get to the other side, but when it comes out it can keep pumping outputs out every cycle, like a manufacturing assembly lineIf u got the system to not skip a beat, it means that one core actually counts as, as many cores as their is instructions in the series.How about that for a space saver, but the issue is powering it, every instruction has to run at the same time so it chews up watts like no other technique if it was ideal.

author: james_s
author_rank: Super Contributor
timestamp: April 01, 2021, 08:57:52 pm
content: Quote from: Capernicus on March 31, 2021, 11:14:06 amFPGAs and GPUs are two entirely different things, you're comparing apples to oranges. GPUs are high performance microprocessors optimized to perform specific types of tasks. FPGAs are a huge breadboard with an unlimited pile of logic chips that you can wire up any way you see fit.I use FPGAs for recreating vintage computers, arcade games and other stuff, that is not really what they're intended for but they can do a good job of it. In a former job we used an FPGA as a crossbar switch to route the digital video and audio signals between the tuners, recorder and TV in a digital video recorder. They're also used in a lot of small volume specialized equipment where it is not cost effective to produce custom silicon.

author: rstofer
author_rank: Super Contributor
timestamp: April 01, 2021, 08:58:46 pm
content: The idea of pipelining is used all the time in CPU design and, by implication, FPGA design. Latency is higher but throughput is much higher.Most RISC designs use a classic 5 stage pipeline:https://en.wikipedia.org/wiki/Classic_RISC_pipelineOf course, there are interlock issues to work through and pipeline stalls to handle but it is certainly possible and, in fact, quite common.This book details ARM pipelining although the included code is for a non-pipelined processor:https://www.amazon.com/gp/product/0128000562It's a pretty good book and includes SystemVerilog and VHDL code.The authors also have a book about MIPS architecture:https://www.amazon.com/gp/product/0123944244This book includes Verilog and VHDL code.

author: dmills
author_rank: Super Contributor
timestamp: April 01, 2021, 10:41:17 pm
content: Ironically a MAJOR user of FPGAs is broadcast video.Sure you could do 4k60 video effects on a GPU, but you are talking whole frames of latency to get the data in and back out, going line by line with only sufficient buffering to deal with the skew due to speed of light in the video cables lets you pull in multiple 12Gb/s SDI flows, do the gamma and colour space conversions, handle switching and keying, maybe do some DVE stuff and get the pixels back on the wire, with delays measured in terms of lines not frames, all this while NEVER dropping a frame or having to slow down because something was busy).Getting a GPU to handle 20 bit 4:2:2 cleanly is MUCH harder then it at first appears, especially if trying to work with much less then a frame at a time (Yea, broadcast video is 10 bits per channel, non linear).The a cpu (or even a whole field of them) you are telling preconfigured hardware what to DO, with an FPGA you tell a sea of gates (There is a reason FPGA folk call it a fabric) what to BE.Where FPGAs really excel is in very highly pipelined doings, basically dataflow stuff where the ability to cascade a whole mess of DSP and logic and have it ALL execute on every clock is really quite powerful.Where FPGAs are a pain in the arse is when there is 'sequence in time' sort of stuff, you basically have to build explicit state machines (In fact this is so much of a pain in the arse that both major vendors have small CPU models that you can build into your designs to deal with the stateful control stuff that is a pain in HDL).GPUs also generally suck at IO, how are you going to get 16 12Gb/s links into a GPU, when they all have slightly different timing offsets (Oh, and you need to get some AES3 in and out as well, and handle a couple of shaft encoders, and output PTP V2 synchronous ST2110 on the low latency profile? Raw compute power is not the hard bit, moving data is.

author: rstofer
author_rank: Super Contributor
timestamp: April 01, 2021, 11:04:39 pm
content: At least the entry level DSOs use FPGAs to make things happen including timing the GS/s A2D converters. I'm not sure about the very high dollar scopes. Their price may justify ASICs.

author: james_s
author_rank: Super Contributor
timestamp: April 02, 2021, 02:46:16 am
content: Quote from: rstofer on April 01, 2021, 11:04:39 pmI haven't been inside a high dollar DSO although maybe Dave has taken a peak. I think it has more to do with sales volume than cost though. At a former job we had a HDMI analyzer that cost close to $100k and it had a big FPGA in it. It was one of the most expensive pieces of test equipment I've ever used but it's the sort of thing that has a global market of maybe a few hundred to a few thousand units.

author: rstofer
author_rank: Super Contributor
timestamp: April 02, 2021, 04:02:19 pm
content: Quote from: james_s on April 02, 2021, 02:46:16 amWhich would make you think that the Rigol DS1054Z would be ASIC based due to volume and any of the Keysight scopes would be FPGA based. I don't think it works out that way.I think the reason that most scopes are FPGA based is the ability to update the firmware. Nothing as complex as a modern DSO is likely to ship day one with no bugs. There is also the ability to add features on request (assuming they are workable).

author: dietert1
author_rank: Super Contributor
timestamp: April 02, 2021, 05:16:46 pm
content: An FPGA may be a good method to improve time to market. You just wire all components to the FPGA and implement major parts of board layout inside the FPGA. And a modern FPGA includes multiple ARM cores, so you don't waste your time with large VHDL descriptions of embedded processors. A modern FPGA has other prebuilt components like RAM blocks, serial interfaces, PLL, ... Once you learn how to describe your system in VHDL, that's something very useful and universal.I'm afraid a JETSON nano is a wonderful number crunching machine that won't perform well when trying to implement logic. Would you implement an ethernet node using one if its processors? Or does it include an FPGA to do that? GPU and FPGA are completely different concepts.Regards, Dieter

author: fourfathom
author_rank: Super Contributor
timestamp: April 02, 2021, 06:31:50 pm
content: Quote from: dietert1 on April 02, 2021, 05:16:46 pmIn my previous companies we would often jump-start the process by developing boards (plug-ins for multi-board communications systems) using FPGAs, designed in Verilog. This gave hardware / software / marketing something to work with while we were fine-tuning the design. We would then follow up with a full ASIC design for cost / power reduction and performance enhancements. Other boards would require ASICs at the start, as the FPGAs couldn't provide required the speed and/or density.

author: Siwastaja
author_rank: Super Contributor
timestamp: April 02, 2021, 06:33:50 pm
content: Who uses knives? You know they invented scissors, right? So cutting paper with a knife is stupid and obsolete. This scissor brand I happen to know is just ultimate for cutting paper. And cutting paper is everything that counts because I don't know anything else than how important cutting paper is.What uses can you come up with for a knife? Who uses knives??

author: james_s
author_rank: Super Contributor
timestamp: April 02, 2021, 07:44:13 pm
content: Quote from: rstofer on April 02, 2021, 04:02:19 pmHigh market volume doesn't preclude the use of an FPGA, but low market volume usually does preclude the use of a custom ASIC. There's no one reason to go with one over the other, rather it's a decision based on numerous different factors. Oscilloscopes as a whole are low market volume compared to say consumer electronics. I'm only speculating but I would guess there are probably more of one specific model of iPad sold in a year than all oscilloscopes from all makes all put together.

author: jmelson
author_rank: Super Contributor
timestamp: April 02, 2021, 11:59:29 pm
content: Quote from: dmills on April 01, 2021, 10:41:17 pmWell, actually, state machines are not that big of a deal. You have a "process" with statements like :if (state=some_number) thenstate <= 21;signal <= '1';end if;and so on for each state. While a CPU can only do one state machine at a time, you can have dozens of them in an FPGA, and link them all together in a top-level file.Jon

author: james_s
author_rank: Super Contributor
timestamp: April 03, 2021, 04:16:57 am
content: Yeah state machines are part of just about every basic HDL lesson I've encountered, no big deal at all. The CPU soft cores are available for more complex tasks where it makes sense to have a general purpose microprocessor along with your custom logic.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 03, 2021, 07:40:10 am
content: Not that I know what im talking about, but if I were using an fpga I wouldnt be using some provided ram array, I may as well be on a CPU and it would slow you down, Id be using purely registers connected directly to the gates, if I needed a state id set up a circular access memory of registers and drill it directly into the logic, and see how fast my framerate is.performance performance performance, thats what I always imaged FPGA's were about. GPUs just let me down these days, gtx3080 may be 4 times faster than my card but for what ive got in front of me I need more than that, and it just costs so much.If I can carve the logic down, keep the model as simple as possible maybe I can get away with something cheaper and runs faster at the task at hand.Even tho you can optimize software as well, for the same result, but maybe doing the hardware directly gets you more performance for your transistor count.

author: dmills
author_rank: Super Contributor
timestamp: April 03, 2021, 08:55:40 am
content: Oh state machines are routine, (And a CPU is a state machine!), but there are definite limits to how complex a state machine written as such can be and remain tractable.Throwing a microblaze or such in the fabric gains you two things:You can program the stupid thing in C, debug it with a debugger and generally treat some of the work as software dev.Also, changes to the software side do not usually require P&R to be rerun, particularly with a mostly full part that can save literally hours of compute time.High performance those little cores are not, but a lot of control (as opposed to data flow) stuff just does not need a high performance computer.The on chip block rams are in fact a KEY feature of an FPGA, these are usually relatively small memories (a few tens of kb typically), BUT there are potentially hundreds of them! This makes for fantastic memory bandwidth, and they get used for everything from filter coefficients, to fifos, to look up tables, to yes, program and data storage. They are explicitly designed to be useful for crossing clock domains and similar purposes.Same with the 'DSP' cores, which are really some combination of adder/multiplier/accumulator, good typically (with some pipelining) to a few hundred MHz, but again you got a hundred or so on the chip, and they can be wired directly into the block rams for data or coefficients.A common mistake is to thing of writing an FPGA configuration as software, you can sort of do that, but software generally has an implicit notion of sequence, VHDL does not, it describes wiring, look up tables, and registers, if you need sequential, you have to describe the circuit to make things happen one after another, it is not built in.Say, rather, IO, IO, IO is what FPGAs are really about, you can get some very nice performance as well, for problems that fit the model well, basically masses of data flow stuff that pipelines nicely, but the selling feature is hundreds of fast IO pins and a handful of scary fast transceivers.

author: Siwastaja
author_rank: Super Contributor
timestamp: April 03, 2021, 02:42:31 pm
content: FPGA is an electronic component, not a trendsetter. Youknowif you need one.Capacitors are not about "performance". Neither are FPGAs.And you can't replace a capacitor with a CPU even though CPU processes approximately infinite times more data per second than a capacitor.I don't know why but for some strange reason the term "FPGA" sometimes seems to sneak into the discussion of so-called laymen who have no idea what it is, but somehow they have got the wrong impression like it's some kind of new contender against CPUs or GPUs or whatever. This makes absolutely zero sense. Then they Google it and are more and more confused, commenting something utterly bizarre such as "it's not FPGA's year yet".Meanwhile, we designers use FPGAs whenever needed like we always did.

author: rstofer
author_rank: Super Contributor
timestamp: April 03, 2021, 04:53:18 pm
content: Quote from: Capernicus on April 03, 2021, 07:40:10 amThe Artix 7 -100T variant has 1188Kb of distributed RAM - basically flip-flops in the logic cells. If we're building a 16 bit processor, this is about 74Kwords and more than enough for a 32K machine. But this RAM is usually used for more important things like code conversion.The card reader uses Hollerith, the CPU uses Hollerith, the printer uses printer code, the keyboard is different yet and, of course, the bouncing ball typewriter uses rotate-tilt code. But I want everything in ASCII at the edges! I really can't change the internal codes without rewriting the OS and that's not going to happen.BlockRAM is organized around 36Kb words which is really 32K bits plus 4 bits if I decide to implement some kind of ECC. On the 100T, there are 135 of these blocks. For my mythical 16 bit x 32K CPU, I need 16 of these blocks. There is plenty left for a 25x80 video display.https://www.xilinx.com/support/documentation/selection-guides/7-series-product-selection-guide.pdfThe modern FPGA has a LOT of memory and it's VERY fast. I have yet to figure out how fast but it runs single-cycle at 100 MHz without a hiccup. Of course, if you register the output then you add a cycle (or you have to think in terms of a pipeline).https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdfThe fact that all of this RAM, distributed or Block, can be initialized at startup is a very power feature. The 1130 always used some kind of cold start program on the first card through the reader. In my design, the cold start code is copied into memory from another chunk of initialized RAM at startup. There is no separate operation, it just happens by magic. Boot the processor and the first thing the CPU sees is the cold start code.The idea of using some of the BlockRAM for microcode doesn't seem like a popular design approach AFAICT but it should work perfectly. Maybe the microcode is 64 or 128 bits wide and perhaps 256 words deep. This fits easily.The memory resources of even a modest FPGA are pretty staggering.

author: camila
author_rank: Contributor
timestamp: April 03, 2021, 05:30:36 pm
content: I have used them in a project? What's the query?

author: james_s
author_rank: Super Contributor
timestamp: April 03, 2021, 06:05:38 pm
content: Quote from: Capernicus on April 03, 2021, 07:40:10 amYou could just stop right there. It's clear that you don't know what you're talking about, you're just babbling complete nonsense and you don't seem to be paying any attention to what people are saying who are explaining what FPGAs are and what they're used for. You're just embarrassing yourself.

author: Raj
author_rank: Frequent Contributor
timestamp: April 04, 2021, 10:39:17 am
content: Apparently Razer's shitty deathstalker ultimate keyboard (cause it has the worst software support) has an FPGA inside of it. It also has 2 microcontrollers. (overkill? absolutely)You haven't seen fpga cause they are too damn expensive to be in a consumer device.I've also seen a lot of people use FPGA in Imaging application, be it driving displays or be a camera interface.

author: james_s
author_rank: Super Contributor
timestamp: April 04, 2021, 06:29:27 pm
content: I've seen FPGAs in consumer devices before, one in particular that I recall was a LCD TV from around 2005, I didn't delve into it deeply enough to determine precisely what it was used for but I suspect it was routing the HDMI signals from the various inputs. You can spend a fortune on high end FPGAs but there are lots of inexpensive ones too.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 04, 2021, 07:01:29 pm
content: Quote from: camila on April 03, 2021, 05:30:36 pmWhat Id like to do is take an oldschool game, like pong or turbo snake, and then run as many instances as I can fit in parallel, does this make sense at all to FPGA design?I need to do that for an Ai application.The implementation I saw of an FPGA was doing picture matching with k nearest neighbour (basic artificial intellignce), but there wasnt enough details for me to tell or learn much, but it did look like it was going pretty fast.

author: james_s
author_rank: Super Contributor
timestamp: April 08, 2021, 04:48:31 am
content: You could certainly do it, although I'm not sure how it could be useful to have a bunch of Pong games running in the same IC. Pong didn't even use a microprocessor, it was all implemented using counters and logic, discrete TTL ICs. FPGAs are quite good at recreating early games like this since they can't be emulated in the traditional sense, there is no microprocessor and no code to emulate. You can write a program that creates a very similar game, but it will not be exactly the same as the original. There's quite a good writeup analyzing the original Atari Pong circuithttp://www.pong-story.com/LAWN_TENNIS.pdfBut back to my point, say you put a bunch of Pong circuits in parallel, once you have one working it's easy to instantiate as many copies as will fit in your FPGA, but then you have a bunch of vaguely NTSC-like composite video signals, what do you do with those? Once microprocessors started to displace the hardwired logic games most used the 6502 and 6800 micros to run the game logic, but generally the video generation circuitry remained similar to the pre-microprocessor games. The code would just manipulate variables in RAM, for example the object code in an address corresponding to a particular tile location on the background, or the position of a motion object. Without the video circuitry you're left with a typically sub-1MHz 6502 computer with just a few kB of RAM.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 08, 2021, 05:15:44 pm
content: What I need to do now is get some free simulation software, work out how much estate I need, and get the cheapest FPGA that'll fit the hardware description.I was looking at buying a rack of smaller ones or 1 big one, but 1 big one was cheaper.SPARTAN 6 XC6SLX9 has ~10,000 CLBS - and its worth $40 - a 16'r rack would be 146,432 CLBS cost $640 (but less if u get bulk)SPARTAN 6 XC6SLX150T has 147,443 CLBS (so its only 1k more) - and it costs ~$340.... so its actually cheaper just to buy 1 big one in this case.My idea is really simple.I don't need the video signals, I just need the game model to play through with random controls, then the score goes into a max circuit, the one that scored the highest out of the whole lot of testing every 100 milliseconds is what the computer does, to do the Ai. It helps if its an FPGA because u get the "game samples" at the HZ of the machine just with the electrical delay slowing it down. (so its bloody quick!)

author: james_s
author_rank: Super Contributor
timestamp: April 08, 2021, 05:45:51 pm
content: That seems like an awfully strange way of generating random numbers. In most cases the score is going to be zero if you try to play a game like Pong with random controls, save for the occasional fluke where the ball hits a paddle once or twice. You could probably fit several thousand instances of a game like that in a XC6SLX9 though, that's quite a large FPGA by my standards. Just for reference, I did a few classic games like Super Breakout, Sprint 2 and others of the same generation and they consume about half the resources of the EP2C5T144C8 I used, quite a small FPGA by modern standards. The speed only matters for the video signal, you can easily clock the system many times faster than the original except that makes the video timing all wrong. Using a CRO as a vector monitor I can run Asteroids at something like 20x speed even on an old FPGA, it's completely unplayable at that point.The software for any of the major FPGA players is available free for personal use. Quartus for Altera (Intel) and ISE or Vivado for Xilinx. Learning HDL (either VHDL or Verilog) is a long road, and existing programming experience is usually more hindrance than help since it LOOKS like programming but it is a completely different paradigm, it is actually digital hardware design.

author: ebastler
author_rank: Super Contributor
timestamp: April 08, 2021, 06:05:03 pm
content: Quote from: Capernicus on April 08, 2021, 05:15:44 pmGood plan. That might give you some insights into what FPGAs actually do and what they can be used for. Warning: There is work and learning involved.QuoteI don't think you have thought this through. Wouldn't your AI need to formulate some "strategies" for the controls, see how these perform, refine them etc. rather than just rely on a never-ending stream of random paddle moves? How would it feed that "strategy" back into the FPGA?On the other hand, the "optimum strategy" for PONG is so trivial that this does not seem to be a worthwhile example for a self-learning system. "Always keep your paddle at the height of the ball", duh...

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 08, 2021, 06:28:22 pm
content: Yes, for pong its a little over engineered, but something like 2 player turbo snake (where the snakes are blocking each other in.) would suit it more, something thats hybrid reflexes - strategy close to the moment decisions is what it would be best at. Racing would be good too.That's amazing that 2000? "logic elements" (not that I know what I'm talking about yet.) Is enough for a sprint game and pong (From james_s's exp), and that u can fit 1000?? whole game repeats on that little spartan, by my early computations, that would exceed GPU performance (what I know myself) by a huge amount, but early days yet.I have to wait and see what I get for real.But I do realize that a big GPU will compete with a big FPGA, and u can even use GPUS for high frame rate/output frequency tasks as well, if your very good at divvying out the instructions to the cores, u can get kilohert framerates even out of a GPU. But it would be funny if FPGA's come out cheaper by a mile. Industry market secrets, but I dont know yet.

author: james_s
author_rank: Super Contributor
timestamp: April 08, 2021, 06:37:17 pm
content: Well I just know that I fit Pong into a CPLD years ago, it was my first ever project with that sort of device and I never got it working quite right, but it fit in a device that was something like 180 logic blocks and it ran the attract mode. You're welcome to play around with the projects I've released, most of the arcade games I did use a 6502 CPU, and my releases are all targeted for the EP2C5T144C8 but should be easily ported to other hardware.https://github.com/james10952001Think about the original hardware, Pong for example is something around 70 TTL chips, each of those is only a handful of gates, what is amazing is how much they were able to get out of so little hardware. Pong in particular was ingenious, it pioneered techniques like the "slipping counters" that create the ball movement. There is no computer, no code, no ROM, no memory of any sort beyond a few latches. The other early B&W games were the first uses of things like ROM to hold graphical elements, motion objects, collision detection and other techniques that went on to be staples in video game design.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 08, 2021, 06:49:01 pm
content: Thanks alot for the link! I love the old arcade too, I only got a short glimpse of the B&W arcade, it died out by the time I was 8-10 or something.200 logic blocks hey, that's quite amazing. I bet it was hard to get it that small tho, I doubt my model is going to get that small, but optimization lowers cost and increases performance!So I know what I need to do then to get this thing going good.Can I just download those and plug them straight into a sim and run them?

author: james_s
author_rank: Super Contributor
timestamp: April 08, 2021, 07:13:45 pm
content: I didn't do anything to get it that small, I just duplicated the original schematic which was already small, I didn't even use HDL in that early experiment, I used the schematic entry feature in Quartus, Nolan Bushnell did all the optimization 45 years ago when TTL logic chips cost around $10 each so there was good motivation to find tricks to minimize parts count. Part of the reason I never completed it is I discovered that schematic entry looks nice for beginners but it is a nightmare to debug and maintain, it was still an interesting proof of concept though. I'll reiterate, FPGA development is not programming, it is hardware design. Optimization isn't done the same way it is in code, it is a matter of simplifying hardware, and to some degree it requires familiarity with the internal structure of the FPGA. It's entirely possible for very tidy compact looking HDL to synthesize hardware that is a convoluted mess, while what appears to be a bloated mess of code can produce very clean well optimized hardware. It's a whole different world, which is why I mentioned that previous coding experience is often more hindrance than help. Superficially HDL LOOKS like code, but that's where the similarities end. You are actually describing a schematic, using a special language that superficially resembles a program.Well to run it in simulation you'll need to write a test bench that generates the master clock and some control inputs but otherwise yes, more or less. Just keep in mind that in simulation you will not be running it anywhere near real-time, it will spit out a simulation of a few milliseconds of operation. Simulation is intended for debugging portions of a design, something akin to unit testing, timing in particular.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 08, 2021, 07:26:37 pm
content: Thanks for the advice. Respect to the old hardware wizards, including u guys oc.I have coded my own truth table machines before, and I am a fairly hardened beginner when it comes to hardware/electronics even with raw electricity, I actually re-invented the marx generator by accident, it was just a novel form of voltage doubler as far as I knew, it was funny when I saw it was invented along time ago! =), so I should be ok thanks.So Ill try verilog in Quartus?

author: dmills
author_rank: Super Contributor
timestamp: April 08, 2021, 07:55:08 pm
content: Personally if you have a software background I would go VHDL, verilog looks far too much like a C family language and you are likely to fall into the trap of writing software rather then describing a circuit.Regards, Dan.

author: james_s
author_rank: Super Contributor
timestamp: April 08, 2021, 08:49:09 pm
content: I use VHDL personally, it clicks better in my brain. It's strictly a matter of personal preference, anything you can do in one can be done in the other, you can even mix and match VHDL and Verilog files in the same project. My suggestion is try them both and see which one you like.

author: rstofer
author_rank: Super Contributor
timestamp: April 08, 2021, 08:50:18 pm
content: Quote from: Capernicus on April 08, 2021, 06:49:01 pmMANY years ago, my brother worked in a bar and they had a table-top Pong game. Inside the cabinets were the schematics so I wire-wrapped one. I have forgotten how many chips were involved but the case was about 7"x12". It worked well!I sure wouldn't waste an FPGA on a Pong game when it can be built (and upgraded a bit) from a PIC 16F688 which costs $2.04https://geoffg.net/Pong.htmlhttps://www.digikey.com/en/products/detail/microchip-technology/PIC16F688-I-P/593003It might be a suitable first project but I would recapture the FPGA fairly quick.You also need some form of A2D converters for the analog inputs. Perhaps hanging on an SPI bus? I like SPI a lot more than I like I2C...

author: james_s
author_rank: Super Contributor
timestamp: April 08, 2021, 09:29:38 pm
content: Quote from: rstofer on April 08, 2021, 08:50:18 pmIt's not the same game though. You can write a Pong game in software but it will not be quite exactly the same as the original because the original didn't have any software. It is actually more nuanced than it first appears, and the original actually had a bug in the wiring of a signal that determines the trajectory of the ball bouncing off certain parts of the paddle.Either way it doesn't really matter, Pong will fit in a $3 CPLD, an FPGA makes a good development platform though.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 08, 2021, 09:36:26 pm
content: So 144 (edit, oops that was inches not chip count sorry) TTL logic chips roughly estimates to 2000 logic units?Im not sure if Ill need analogue ins yet. Depends if I'm just making an fpga retro game ai system, or something else...

author: james_s
author_rank: Super Contributor
timestamp: April 08, 2021, 09:40:21 pm
content: Quote from: Capernicus on April 08, 2021, 09:36:26 pmIt's pretty hard to make a direct comparison since the contents of TTL chips varies considerably. You can look at the datasheet for a CPLD or FPGA and it will show you exactly what is in a logic block. You can also try some very simple circuits and compile them for a particular part and see what it shows you as far as resource consumption. It gives you all the details you could possibly want.

author: ebastler
author_rank: Super Contributor
timestamp: April 09, 2021, 04:57:35 am
content: Quote from: Capernicus on April 08, 2021, 09:36:26 pmI am not sure where you got your example numbers (the 144 chips as well as the 2000 logic units); they don't seem to correlate with anything mentioned about PONG in this thread?A typical logic cell in an FPGA comprises a flip-flop and a configurable logic table at its input. Hence, for a first ballpark number I would estimate "one FPGA logic cell per flip-flop in the TTL chip", and "one FPGA logic cell per externally avaliable logic gate in the TTL chip". E.g. eight logic cells for an 8-bit latch or counter, and four cells for a 7400 NAND gate.That estimate may be too low for some of the flip-flop based chips; e.g. a synchronous counter will have logic with many inputs for its high bits and may require some extra cells. On the other hand the estimate should be high for the discrete logic gates, since they can often be "absorbed" into the front-end logic of a flip-flop. So overall this should get you into the ballpark.Besides the number of logic cells, the infrastructure to connect them may limit the density of your FPGA design. But with your PONG idea, which will mainly need local interconnects within the small PONG game units, I would not expect that to have a severe impact.For PONG with its sixty-some chips, and assuming an average of 5 or 6 logic cells per chip, that would give you 300 to 400 cells. A bit higher than what james_s had mentioned earlier, but directionally right.

author: james_s
author_rank: Super Contributor
timestamp: April 09, 2021, 05:48:51 am
content: It occurred to me that I could just go and look at the usage. As it turns out, it seems I no longer have the initial Pong I did using the schematic layout, however I do have a Pong implementation someone else wrote in Verilog that I ported to some of my hardware so I compiled that and your 300-400 cells estimate is actually very close. I thought the CPLD I used was only about 200 cells but I could be wrong, it was not a very big one though. In this case here I used an FPGA instead, they're convenient in that they have PLLs and such so you don't need to feed the thing a specific clock frequency.Flow Status Successful - Thu Apr 08 22:44:34 2021Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web EditionRevision Name pong_vTop-level Entity Name pong_vFamily Cyclone IIDevice EP2C5T144C8Timing Models FinalTotal logic elements 365 / 4,608 ( 8 % )Total combinational functions 364 / 4,608 ( 8 % )Dedicated logic registers 163 / 4,608 ( 4 % )Total registers 163Total pins 10 / 89 ( 11 % )Total virtual pins 0Total memory bits 0 / 119,808 ( 0 % )Embedded Multiplier 9-bit elements 0 / 26 ( 0 % )Total PLLs 1 / 2 ( 50 % )

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 09, 2021, 04:02:20 pm
content: Yes I was a bit optimisticly budgetting things, so being about 1 gate a logic element roughly, an adder taking a logic element up per significant bit, its not quite as fabulous as I was thinking, but its still quite good, especially if you can shave down the significance for different variables as you need to.So now im just drawing up my model, i want to fit it in 100,000 LE's hopefully, (Im guestimating ill need 10,000 10 bit adders) but need to wait and see.

author: ebastler
author_rank: Super Contributor
timestamp: April 09, 2021, 04:25:45 pm
content: Sorry, you lost me there. This must be a different project now than the "many parallel PONGs" you sketched earlier?Where do the 10,000 10-bit adders come from? What do they add, i.e. where are the data they are adding being held? And you are assuming a ripple carry, right, otherwise you would definitely need more logic.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 09, 2021, 05:12:17 pm
content: I'm not doing pong exactly, but it is a physics model the same.INPUT last scene image|\/(500 adders worth,to transform the scene.) <-THIS IS WHERE PONG WOULD GO, if i were doing pong.|\/OUTPUT next scene image.(edit, its 500 adders (ripple carry yes) not 10,000 cause I need 20 in a row physically, for the frames in front.) - thats what I have to fit 1 step in. So maybe it wont quite fit, but Ill finally know what im dealing with once i get the gate design down.then I need to put the whole chain of frames for how long in front it looks, But that is always less than 30.probably only 20 or even 10 would still work for me.Its 3d vector matrix maths, inside the transform, like in a 3d video game (opengl or directx), but I get rid of all the multiplies and just do it with add and subtract, I do rotation without sine and cosine and its split 360 degrees onto a flat edged polygon instead of a perfect circle. (old school.)Its more complex than pong, but hopefully not much more, I have the ordinary c version half typed out, I need to get the motivation to finish it off, and then ill see how many adders it will be. (Its just adders and conditions, should be the whole thing.)I dont know how complex itll be, there could be some really great shaves in front of me, I have to get the basic idea down first.If I could afford a really expensive FPGA, then I could put parallel cores in, but as it turns out Ill probably be only able to fit 1, that's what its looking like now, but it'll still be extremely quick anyway, well worth doing.

author: james_s
author_rank: Super Contributor
timestamp: April 09, 2021, 05:48:13 pm
content: Well keep in mind the FPGA I'm using in my example here is a very old part, and tiny by modern standards. Even several years ago the entire dev board was only $13.

author: rstofer
author_rank: Super Contributor
timestamp: April 09, 2021, 06:18:08 pm
content: I have posted several times that my favorite FPGA, at the moment, is the Xilinx Artix 7 (-100T variant). That particular device has 101,440 logic cells.The more affordable -50T has 52,160 logic cells and there are boards using the -35T with just 33,280 logic cells.See page 3 here:https://www.xilinx.com/support/documentation/selection-guides/7-series-product-selection-guide.pdfThis little 'stamp style' module is available in the -35T variant for $89. If 33,000 logic cells is useful.https://store.digilentinc.com/cmod-a7-breadboardable-artix-7-fpga-module/

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 09, 2021, 07:10:54 pm
content: That breadboardable one looks cool, if u had 3 working together ud get as much working space as the -100T varient.Would cost $225, quite cheap indeed for ~100,000 gates, I have to finish my plan yet, get all the main bugs out before I can know how cheap I can do this per core. Ill be chopping off as much as I can, the more I chop it off the more chance for multicore there is.So 1 million gates, going by that cost would be ~$2000. and thats what I might get, because I'm used to buying new GPU's Im used to paying an arm and a leg anyway. I want to get a big daddy for it, because this thing is kinda special to me.Ill put the log of (how many cores by the fpga hz) on the name of it. the "X" 31, maybe it might be. =)

author: rstofer
author_rank: Super Contributor
timestamp: April 09, 2021, 09:20:48 pm
content: Be careful with 'gates', 'logic cells' and other terms. Make sure you know the exact definition as it applies to your chosen device. 'Logic cells' in particular is a marketing term used to level the playing field across logic families and vendors. It is mythical and of no particular importance. 'Gates' is even more obscure because everything is based on the LUT (Look Up Table) which is really just a MUX and can have a lot of 'gates' involved.Better to know how many 6 input LUTs a 7 series device has because that is about as granular as you can make your logic. So, look at the definition of a CLB (Configurable Logic Block). It will have a pair of 'slices' each of which has 6 input LUTs, some carry chain logic and a couple of flip-flops.QuoteNote 1, Page 11 here:https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdfThe -100T has 15,850 CLBs and that is a heck of a lot more than 1,000,000 gates. Even the Spartan 3 1200E had more than a million gate equivalents and it's tiny compared to the Artix 7 100T.See page 2 here:https://www.xilinx.com/support/documentation/data_sheets/ds312.pdfI used the XC3S1200E for my 1130 project (the 7 series wouldn't even be invented for several years after I finished the project. At least to the consumer grade Artix 7...The device has 1,200,000 'gates' or 19,572 'cells'. One way to compare the 1200k versus -100T is in terms of CLBs. The -100T has 7,925 and the old Spartan 3 1200E has 2,168, I told you the -100T was large. Remember, the 1200E has 1,200,000 gate equivalents so the -100T might be talking about 4,386,000 'gates'.It's really tough to compare devices or even figure how large any one device is. It's better to just read the Synthesis Report and figure out how full the device actually is. See attachedNote that my IBM1130 project uses around 10% of the flip-flops and just 24% of the LUTs. That's for a complete system including CPU, Card Reader, Line Printer, Disk Drive, Keyboard and Selectric Typewriter. The Artix 7 is more than 3 times as large.

author: gnuarm
author_rank: Super Contributor
timestamp: April 09, 2021, 10:25:09 pm
content: "Logic cells", "gates", "LUTs"... they are never an accurate way to compare FPGAs because FPGAs are not just any of those things. Even worse, the logic features of each family may or may not be particularly usable in your design, so if counted in the "logic cell" or "gates" count it may or may not be useful counts.The bottom line is to test your design against the various chips. This is not so much different from using standard benchmarks to compare MCUs. The only meaningful benchmark is your application.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 09, 2021, 10:37:49 pm
content: How big a computer is a IBM1130 - thats nifty that u got that working, so u could fit about 4-5 more cores on it if u wanted?That would be great if if its true! I hope your right, but if you look at this video he shows that the adder takes up ~80 of the "dots" and theres only ~10,000 of them there, so that would come to as far as I know about adders granular 64 gates for a 32 bit adder, but I spose I dont know how many bits this adder is, but its taking up a fair bit of space, theres only room for ~200 here, it looks like.(at 12:40)But if these LUTS are 6 input, that means they are 64 row, but I bet if the compiler is any good it could put more than one granular gate into the same LUT? But I guess maybe its not always good to rely apon the software to do things, because sometimes its not so good.But that doesnt make sense, if the LUTS were larger than 2 op gates, then there wouldnt be 80 dots there used space... doesnt look large from this standpoint. But maybe this isnt just a ripple carry adder and theres more there than that, and hes being a bit cryptic about it, not sure.So I'm not sure what I'm doing but Ive got Intel Quartus 64gig download on the way, then Ill see if I can get something emulating.but why the hell is it a 64gig download... that is terrible!!!

author: rstofer
author_rank: Super Contributor
timestamp: April 09, 2021, 11:54:44 pm
content: Quote from: Capernicus on April 09, 2021, 10:37:49 pmI don't know that IBM ever referred to the IBM 1130 as a 'minicomputer' but that's about what it was. Maximum memory was 32K 16-bit words. At first it was just a single user system and later in life it became a host for remote entry. Sometimes it was a front end for the mainframes. IBM was the largest customer and they used it on the factory floor for a number of operations. First computer you could see over the top of and the first computer system to lease for less than $1000 per month. I assume this was the 4K paper tape based system. Our department was charged $8 per run hour for usage. There was also a vector graphics display with light-pen function. Useful for CAD involved with building airplanes. We didn't have one at the time. The internal (to the main desk cabinet) disk drive held 512,000 words on a removable cartridge. It seemed like a lot way back when. I never did fill one up.There was another model, the IBM 1800 which was identical (conceptually) except for having 2 more instructions. It had serious real-time capability and, where I worked, it was used for data collection from a supersonic high speed wind tunnel. Lift, drag, that kind of thing. To be fair, these were very small models because the window was only about 12" square, IIRC. It had a gigantic Roots style supercharger to compress the air into a storage tank. On the discharge side there was a valve styled just like a camera shutter so it could open quickly. The mechanical guys tell me the structural calculations for the piping was rather involved. For some reason, it was half-U shaped around the building and a supersonic slug of air hitting the elbows created interesting mathematics.http://ibm1130.org/https://en.wikipedia.org/wiki/IBM_1800_Data_Acquisition_and_Control_SystemEVERYTHING necessary to build a replica is in the Functional Characteristics manual:http://media.ibm1130.org/E0006.pdfThe processor had no hardware stack and, as a result, self-modifying code abounds. The return address of a calling function is always stored in the first word of the called function. So much for reentrancy! An indirect branch through that location got the PC back to the instruction after the call.I guess you had to be there ('71 or so) and be a college student to really appreciate what this machine could do.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 10, 2021, 12:36:24 am
content: Had 64kbyte ram, same as a commodore 64.There's still ppl coding really good games on a c64 today, probably with emulators I see on u-tube.If u emulate that computer on an fpga, it goes the fpga clock speed, doesn't it, not the original clock speed, unless u down clock it.Hotswappable hard-disc drives are cool, I always liked them, Before thumb drives become popular I used to just bring my hard-disc to my friends house instead of burning cd's cause it was just easier for software transfer, because we had tonnes of games to copy.How much pressure does it take to speed up air past supersonic?Makes me think of an idea maybe pneumatic computers oscillate almost as quick as electrical ones if they are fully solid state.Then the whole thing is just a hunk of plastic or fibreglass, dont need metal at all which has interesting fab potential.

author: rstofer
author_rank: Super Contributor
timestamp: April 10, 2021, 01:49:13 am
content: Quote from: Capernicus on April 10, 2021, 12:36:24 amYes. My emulation runs at 50 MHz and the original ran at about 400 kHz (ours had the low 3.6 us core so, perhaps, 278kHz). I slowed down the IO devices to near factory speed (1000 cards/minute, 800 lines/min, 100 plotter steps/sec, 16 typewriter characters per second) to avoid the problem where the CPU hadn't executed enough instructions before the IO complete interrupt occurred. It seems I have increased the speed but when I port the project to an Attix 7, I will reevaluate this. There's a problem watching printer output go buy at 10,000 lines per minute. It's off the screen before you can see what happened!QuoteThe disk wasn't really hot swappable but each group had their own dedicated disk that were stored in a rack between the two systems.QuoteI have no idea but I seem to recall that the drive motor was 8,000 HP. I may be way off on that, I didn't work over there very often. I do know that we had to tell the utility before we could start the motor. That and there was a jacking motor that kept the shafting in continuous rotation. The idea was to prevent the shaft from warping from the loads imposed by the weight.

author: dmills
author_rank: Super Contributor
timestamp: April 10, 2021, 11:21:40 am
content: Pressures required for supersonic flow depends strongly on the nozzle geometry, in not always obvious ways...Interestingly amateur built supersonic wind tunnels are an occasional thing, there was one described in "The amateur scientist" back before Scientific American turned crap.IIRC the usual approach is a pressure vessel valved into a suitable nozzle geometry and exhausting into an evacuated tank, the key being that the system exhausts into vacuum so you are not having to push air out of the way to make your flow.In an era of cheap 3D printing this is a much easier thing to build models for then it was back when carved wood was the way to play.

author: jmelson
author_rank: Super Contributor
timestamp: April 10, 2021, 04:00:21 pm
content: Quote from: Capernicus on April 10, 2021, 12:36:24 amIIRC, 13 PSI in a properly shaped nozzle. Maybe just a bit more for a plain orifice.Jon

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 10, 2021, 05:51:59 pm
content: 13 psi, isnt standard air pressure at room temperature 14?Or do you mean when its entering a vacuum. that is pretty efficient! =)

author: gnuarm
author_rank: Super Contributor
timestamp: April 11, 2021, 12:03:54 am
content: Quote from: Capernicus on April 10, 2021, 05:51:59 pm1 ATM is 14.7 lb/sq in absolute. Most often people talk about pressure which is relative to ambient and called gage or gauge pressure.

author: james_s
author_rank: Super Contributor
timestamp: April 11, 2021, 07:36:21 am
content: Quote from: Capernicus on April 10, 2021, 12:36:24 amBack when any kind of external hard drive was exotic and expensive, I used to take a bare 40MB IDE HDD over to my friends' places and we would plug it into the internal cable in our PCs to transfer data around, mostly games. Doesn't sound like much now, but 40MB was a fair amount of space in the mid 90s.

author: rstofer
author_rank: Super Contributor
timestamp: April 11, 2021, 03:16:45 pm
content: I remember buying a 500MB drive for $500 and considering it a virtual garbage can. I could never fill it up. This was around '90. It came in handy when 386BSD Unix came out in '92.Many years earlier (around '80?), I wrote some driver code for a 5 MB fixed drive (SCSI stuff) that cost about $5k.Now we buy 1 TB drives for around $50.

author: fourfathom
author_rank: Super Contributor
timestamp: April 11, 2021, 03:39:36 pm
content: Quote from: rstofer on April 11, 2021, 03:16:45 pmScoff- youngsters! My first hard drive was a 5MB for my original dual-floppy IBM PC clone (4.77 MHz clock). The half-shoebox-size drive was a 10MB unit with bad sectors. Ludicrously expensive, for me at least, but an amazing amount of space on that MSDOS machine. In keeping with the topic, I actually used that PC to design PALs (Programmable Array Logic). PALs led to CPLDs, which led to Gate-Array ASICs and FPGAs. I used PALs for general logic and state-machine designs. I also used PROMs (programmable Read Only Memory) for state-machine work. This was back mid - 1970's or early 80's.

author: ebastler
author_rank: Super Contributor
timestamp: April 11, 2021, 04:33:13 pm
content: Quote from: fourfathom on April 11, 2021, 03:39:36 pmGiven that the IBM PC came out in late 1981, and generic clones ony became available in 1983, mid 1980s seems more plausible? Also, the IBM PC XT came out with a built-in hard disk in 1983, so 1983/84 seems like a plausible year for getting a second-grade 5 MB disk.

author: SilverSolder
author_rank: Super Contributor
timestamp: April 11, 2021, 04:56:28 pm
content: Quote from: ebastler on April 11, 2021, 04:33:13 pmI recall getting a 20MB disk in 1984 or so... you never forget a bill like that!

author: fourfathom
author_rank: Super Contributor
timestamp: April 11, 2021, 05:39:11 pm
content: Quote from: ebastler on April 11, 2021, 04:33:13 pmYeah, you're no doubt correct. I was guessing -- there have been lots of years and more than a few employers along the way. It was the era of the early clones, as I recall my first clone had a 4.77 / 10MHz clock-selector switch on the back.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 11, 2021, 07:18:28 pm
content: Quote from: fourfathom on April 11, 2021, 03:39:36 pmThere's nothing new to digital logic is there, its always been there and its always been the same.How big were the PALS you were working on, and how fast could you oscillate them?The FPGA im looking at to buy is thishttps://au.mouser.com/ProductDetail/Intel-Altera/10AX048H3F34I2SG/?qs=Rv6LVDxB0ZouSsIL4OazgQ%3D%3Da $3,200 australian dollar, one with 480,000 luts (4 input 2 output) on it. its very expensive and I already doesnt look like ill be able to fit my whole design onto it fully unrolled. (I want to unroll the whole thing!)I havent got the fully finished logic schematic yet, but its getting there. Its a 3d geometry thing, full of repeated rotate operations.I also have a plan for an FPGA raytracer as well I might do, for casting heaps and heaps of rays, for global illumination and radiosity.So expensive, I wonder how hard these things are to make from scratch yourself, seems like such a ripoff just for a grid of electronic lookup tables...

author: fourfathom
author_rank: Super Contributor
timestamp: April 11, 2021, 07:44:59 pm
content: Quote from: Capernicus on April 11, 2021, 07:18:28 pmI don't recall the specifics, but I probably used a 16R8 or something similar (.pdf]https://www.dataman.com/media/datasheet/Cypress/PAL.pdf). The spec sheet says the clock-Q delay is about 25ns but I wouldn't have been running them that fast.I could probably build you your FPGA at home, with a $50 Million investment, if you didn't mind waiting a few years. The programming tools would be another million. These things are fast and complicated. That said, my current FPPGA needs are modest, with a $5 chip fitting the bill just fine: Lattice MACHX02 with 1200 LUTs and 1 PLL. I'm clocking the internals at 100 MHz.

author: gnuarm
author_rank: Super Contributor
timestamp: April 11, 2021, 08:31:52 pm
content: Quote from: Capernicus on April 11, 2021, 07:18:28 pmI haven't followed this thread enough to know what you are using them for, but maybe there are other ways to skin this cat.I think people mentioned the parallel processing capabilities of a GPU which comes with similar issues the massive FPGAs have such as large size and heat loads. Another option is a multiprocessor that doesn't use so much power. An array of 144 very simple CPUs on a chip that uses a maximum of about 1 Watt. Each CPU has very limited resources but cranks at up to 700 MIPS. They run about $10 in quantity and are not hard to interconnect. Greenarrays GA144.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 11, 2021, 08:56:39 pm
content: Quote from: fourfathom on April 11, 2021, 07:44:59 pmThey arent that hard to make! the only problem is getting them smaller I guess.If you could get transistors under a millimetre maybe u could put down a 300x300 map of transistors, in not too much space, that would give you 90,000 gates. One step of my "physics model" is looking to be 60,000, but I need 20 steps...Home made ASIC->https://www.assemblymag.com/articles/83109-placing-tiny-parts-precisely

author: james_s
author_rank: Super Contributor
timestamp: April 12, 2021, 02:08:42 am
content: Quote from: Capernicus on April 11, 2021, 07:18:28 pmWhat new-ness would you expect? There are only so many ways you can manipulate a bit, and you only really need NAND gates technically, you can make any other gate you want out of those. Boolean logic is like basic arithmetic, the fundamentals were laid out a LONG time ago and haven't really changed. The only thing that changes is parts get smaller and faster and/or lower power consumption.IIRC PALs had something roughly equivalent to 10-20 logic blocks and could be clocked up to around 20MHz or so depending on the family. They were used a lot for address decoding in microprocessor systems, I've seen PALs and GALs in early 90s computers and expansion boards. One of the compact Macs (SE?) was a notable use of them, replacing a bunch of glue logic on the motherboard.

author: gnuarm
author_rank: Super Contributor
timestamp: April 12, 2021, 02:31:45 am
content: Quote from: james_s on April 12, 2021, 02:08:42 amSure, logic was invented a long time ago, even before electronics. Boole published his Laws of Thought book in 1854. However, that does not equate to the simplifications you describe such as NAND gates being universal. While you can make any logic function using NAND gates that doesn't mean it is the best way to do it. We learned multiplexer logic in college and lo and behold, it showed up in FPGAs! We learned multivalued logic which is based on a more general form of algebra called Post algebra, which even now sees very little use. One FPGA vendor found that rather than a 4 input LUT, they could combine an AND gate and an XOR gate as a more general form of programmable logic, complete enough to implement adders and anything else. It didn't pan out, not because it was a poor idea, but because it could not compete unless implemented in the same process as the other brands of FPGA. Also, they had very little routing using the logic blocks for routing.My point being there are many ways to implement logic, programmable and otherwise. So we need to remain flexible. BTW, the typical 4 input LUT does not use gates at all in the mux. They use transmission gates because of the speed issues with logic.

author: SilverSolder
author_rank: Super Contributor
timestamp: April 12, 2021, 02:57:04 am
content: Quote from: gnuarm on April 12, 2021, 02:31:45 amAre modern SSD drives with 3 or 4 valued cells (instead of binary logic values) an example of an application?

author: Bassman59
author_rank: Super Contributor
timestamp: April 12, 2021, 02:59:46 am
content: Quote from: Capernicus on March 31, 2021, 11:14:06 amSo, four pages, and as typical, nobody's answered your question.I'll just say upfront that I've been working with FPGAs (and CPLDs, and PALs/GALs and whatnot) since the days of the Xilinx XC3000, when we used to use ViewLogic for schematic entry and HDLs and synthesis did not exist. Those days were horrible and it was common to make a design change and let the tools run overnight and hopefully you didn't make a mistake. Like working with PALs, you had to do your own logic minimization.So, anyway. It seems like all of my FPGA designs are of the "we need a boatload of logic and it needs to fit in this small space." And it's all of the sort of thing where a sequentially-execution processor doesn't make sense for the design. Most things now are controlling a sensor (providing it digital signals from a state sequencer), capturing data from that sensor (whether directly from the sensor's built-in ADCs or with external ADCs) and buffering and reordering it, controlling biases for the sensor, running a temperature-control loop for the sensor, reading housekeeping (voltages, temperature, vacuum, whatever), an interface for FRAM which is used as local parameter store, and managing a gigabit communications link to a remote server, and that includes a command parser and fast data path. Because of the environment in which the product is used, there is also a LOT of test logic built in.Some of the stuff could be done in a standard processor, I suppose, but finding one that fits the bill for all of the various things is tough. Pick an ARM, any ARM. It has a fixed number of serial interfaces (UART, USART, SPI, I2C, whatever) but what if what's offered is not sufficient? For example, the most recent design has I think a dozen SPI and SPI-like interfaces. Rather than trying to figure out how to make Weird Sensor's "SPI" port work with a micro, I design the exact interface necessary.Or, there's a dozen digital pots in the design, and to save pins on a feedthrough, we did something which is basically like QSPI but not really. There are six pairs of digital pots. Each pot needs an 8-bit control setting. Each pair is in series, so 16 bits have to be shifted out to load both. And all of the pairs are in parallel, so they share common SCLK and CS\ and there are six parallel MOSI lines. (We don't read them back, so there's no mux or other logic to deal with the MISO.) I'd probably slit my wrists if I had to do that in a micro, but in the FPGA it was trivially easy. Oh, yeah, we decided to save even more feedthrough pinsAnother thing. A local server will send commands up over the gigabit fiber. The FPGA captures the commands (a four-byte packet) and decodes them. There are 256 possible commands (the command token is one byte). The cool thing about the FPGA command decoder is that it happens in parallel. That is, the time from receipt of the command token to the execution of the command is the same for ALL commands (and is very fast, like two clock ticks). Do that in a sequential-execution processor with a big CASE statement. How many compares does it need to do for the last command in the list?And so on. The FPGA is basically just one big pile of logic resources you can use as your design dictates. You can even embed a processor core in your FPGA, for things which benefit from one (like, say, an Ethernet stack). I've done Xilinx MicroBlaze, Xilinx' Virtex-4 with the hard PowerPC, and I'm going to use a RISC-V in a new thing. The point is that the processor is "just another logic block" to the FPGA: you can do the things that "make sense" to do in the processor in a processor, and you can do the specialist stuff in the FPGA.QuoteBack in the day, there was the Usenet newsgroup comp.arch.fpga, which was exactly what you're asking for. I don't know if it still exists.Good luck.

author: Bassman59
author_rank: Super Contributor
timestamp: April 12, 2021, 03:01:11 am
content: Quote from: SilverSolder on April 12, 2021, 02:57:04 amMulti-value memory cells, like the various "constellations" of digital modulation, are more about packing more information in a given space than any particular application of the data.

author: 1design
author_rank: Regular Contributor
timestamp: April 12, 2021, 03:12:12 am
content: In my line of work FPGAs are used for two very specific services that no other GPU/CPU does well:-Receive market data and trade faster than any ETH stack and processor pair will ever be able to, I can't go into the details, just google HFT.-Be the home of custom ultra low latency modems, again, I can't go too deep into how/what. You can google Sniper in Mahwah.Both are constantly updated/improved and an ASIC would be obsolete by the time it is done and both need to achieve performance levels that are not achievable in SW or GPU.The point is that there are plenty of industries/services out there, where ASIC product cycles are too long and SW is too slow. Look at defence, space, communications, physics(particle accelerators) etc.

author: fourfathom
author_rank: Super Contributor
timestamp: April 12, 2021, 03:39:54 am
content: Quote from: Bassman59 on April 12, 2021, 02:59:46 amThat's pretty harsh. I think the question has been answered many times, from multiple perspectives. Your answer is another good one.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 12, 2021, 03:50:01 am
content: Quote from: Bassman59 on April 12, 2021, 02:59:46 amThanks for the info about your work!Ive actually learnt alot since the beginning of this thread, Ive actually downloaded the HDL IDE now, and Im getting some stuff tested in visual studio ready to convert over to the LUT format.GPU vs FPGA - hard to say whats better out of a DEVBOARD and a GPU talking through an arduino or other micro.I actually dont know if FPGA is going to win over GPU for my task yet, I think it will, but I havent actually got it emulating yet to know for sure. Im looking at a $3000 FPGA for my job!!! so its not cheap at all, u can buy a GTX3080 for that price, I know from my experience how well the GPU is going to go, and for the FPGA to beat it, its going to be about cutting down precision and getting rid of as many complex operations as I can.I know what u mean about having to optimize it to hell to fit it in the FPGA!!! Getting it one cycle is really tough, and it needs to be or I may as well whip out my GPU and just run it with that.I'm right in the middle of the big optimization job, I've got a big system I'm chopping down bit by bit to see how small I can get the instructions without ruining the output too much. Its 3d geometry, its like a 3d game, except I cant get hypotenuses because it requires square root, I'm not using matrix multiply and using very little trigonometry. Its going good!! I think I'm going to make it, I just need a bit more time.. I think alot ppl with less drive would have given up by now and just resorted to vector matrix math and dot and cross products, instead of making it original.As I made this thing, I accidentally worked out on the side how I could get a 3d fractal to render on an FPGA with global illumination, it really can beat the GPU! ray count. but you need to cater it alot to more simpler methods, I think. More like how they coded PS1 games instead of DX11 games.

author: james_s
author_rank: Super Contributor
timestamp: April 12, 2021, 03:57:40 am
content: Scale it down as a proof of concept. You're talking about large numbers of parallel blocks, so to start with use just a few, you shouldn't need a massive expensive FPGA in order to see if your concept works and how well it performs.Something else to keep in mind, the free editions of the tools I've used have limits in the devices they support, they handle bigger parts than I've ever needed, but for the really big guns you need the paid versions which are generally $$$. Not a big deal for a company with a budget but cost prohibitive for the average hobbyist not doing this stuff for a living.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 12, 2021, 04:33:40 am
content: Quote from: james_s on April 12, 2021, 03:57:40 amYeh its all downscalable u just get it in smaller hits. Ill see if I can hit a happy medium there that I like. For that raytracer I was talking about 1 ray costs 20,000 LUTS last time I looked at it, thats not that much! but its best if there were a parallel block of them, if u wanted to show off hardware raytracing properly.Quote from: james_s on April 12, 2021, 03:57:40 amIt looks quite rich indeed, these FPGA things, If It ends being up that prohibitively expensive (software... licencies... FPGA + the goddamn dev board...) Ill at least have my design and then maybe I can even just run it on the gpu again and maybe itll be faster this time because I put so much work into it.There might be something I can do, maybe there is some kind of cheap rack you can get thats more performance for money that u have to look for somewhere...

author: gnuarm
author_rank: Super Contributor
timestamp: April 12, 2021, 04:34:04 am
content: Quote from: Bassman59 on April 12, 2021, 02:59:46 amcomp.arch.fpga still exists, but you need a newsreader to access it or use Google Groups which is a truly, truly horrible interface. I am not exaggerating in the least when I say every time Google touches the UI they make it significantly worse as if they intend to drive everyone off. But there are still some knowledgeable people in the group. It's been very quiet lately though. Maybe too many old timers have kicked off.

author: agehall
author_rank: Frequent Contributor
timestamp: April 12, 2021, 04:47:34 am
content: Quote from: Capernicus on April 11, 2021, 07:18:28 pmYou do realize that to make use of that chip, you also need a $4000 software license?Quite honestly, what you seem to be looking to do is probably better done in a GPU. FPGAs are great for some things, but the more you describe your idea, the more I doubt it is a good way to solve the problem. There are many problems where the best solution would be using an FPGA but there are just as many where a GPU would be the best solution.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 12, 2021, 05:11:34 am
content: Quote from: agehall on April 12, 2021, 04:47:34 amWhy all the licensing crud - theres no licensing for GPUS, whats the big deal? 480,000 isnt even BIG I need bigger. What a let down.

author: ebastler
author_rank: Super Contributor
timestamp: April 12, 2021, 05:20:21 am
content: Quote from: Capernicus on April 11, 2021, 07:18:28 pmA bare FPGA chip?! Do you buy your GPUs as loose chips as well and roll your own boards? If the answer is "yes", I'm impressed. Otherwise, youdefinitelywant to start with an off-the-shelf FPGA development board.It is not straightforward to design and manufacture a board around a large FPGA, and a learning curve at $3000 a pop becomes painful quickly. I would also start with a smaller (cheaper) FPGA to test whether your concept works as you expect.

author: james_s
author_rank: Super Contributor
timestamp: April 12, 2021, 05:23:32 am
content: Quote from: Capernicus on April 12, 2021, 05:11:34 amBecause that's their business model? Because that's how it's always been? Because the profitable customers are willing to pay for it? It doesn't really matter, it is what it is. For most things it's a total non-issue, I've never even heard of a hobbyist FPGA developer needing something larger than the largest parts supported by the free tools.You keep trying to compare FPGAs with GPUs and we keep trying to explain they are two completely different animals. There is some crossover, there are some things you can do with a general purpose microprocessor that you can also do with an FPGA or vice versa but they are not even remotely the same thing, the entire paradigm is different and a lot of the applications are completely different. If you're trying to pump gigabits of data out a dozen or more ADCs in parallel reading a high speed camera CCD into RAM in real time at 10,000 fps the FPGA is the way to go, a GPU simply cannot do that. If you're trying to render textured polygons to create smooth flowing high resolution graphics a GPU is the way to go, they are literally designed from the ground up to do exactly that, and no FPGA is going to touch one, at least in terms of cost.Comparing a FPGA to a GPU is like comparing a farm tractor to a forklift, or a claw hammer to a hockey stick. They are different tools that excel at different applications, with some amount of crossover in the middle where either tool could do an acceptable job.

author: gnuarm
author_rank: Super Contributor
timestamp: April 12, 2021, 05:31:47 am
content: Quote from: ebastler on April 12, 2021, 05:20:21 amYou don't even need a board. Everything needed to answer the question of can it work can be tested in simulation. Of course, the simulations will run much more effectively if a portion of the design is run rather than the entire design. Simulating a half million LUTs will take a tremendous amount of time.Now that we all have supercomputers on our desks and in our computer bags, I wonder what people use to simulate large designs on?I worked at a place that did a lot of FPGA designs and they would have four servers to run simulations on. Every year or so they would be upgraded and the previous year's servers would end up on people's desks. The servers were just the latest and greatest with plenty of memory.

author: agehall
author_rank: Frequent Contributor
timestamp: April 12, 2021, 11:28:24 am
content: Quote from: Capernicus on April 12, 2021, 05:11:34 amStop comparing the two. They are different things for different purposes with some overlap. FPGAs are logic. GPUs are purpose built devices for doing specific math relating to 3D but can also be generalized to do more.And how did you come to the conclusion that a 480k LE device "isnt even big"? I'd say it is a fairly large chip. How much of the footprint is your implementation using at the moment? Have you looked at optimizing it? Any device can be too small for even a blink sketch if you implement it badly.I know this might be harsh to hear, but if you have no or little experience with VHDL/Verilog development, you are probably doing it wrong since you are coming from the software world. I know this trap all too well from my own experience - I can easily write simple Verilog that does what I need but it won't be optimized or very good in general. On the other hand, the devices I play with are typically way bigger than the minimum requirements so I just don't care about it.As I said before, for your application, FPGAs might not be the right solution. You started this thread by asking "who uses fpga's" and I think I wasn't the only one who read your first post as (paraphrasing) "FPGAs are useless - GPUs are much better!" which is kind of like saying "Bananas are better than apples!". I think there are several very good examples of where FPGAs are used in this thread. But I don't think anyone is saying that they will replace GPUs anytime soon but that doesn't mean that GPUs will replace FPGAs either - they are mostly different solutions to different problems.

author: Bassman59
author_rank: Super Contributor
timestamp: April 12, 2021, 02:48:18 pm
content: Quote from: agehall on April 12, 2021, 11:28:24 amYes, this, exactly.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 12, 2021, 03:17:53 pm
content: So a 480,000 LUT FPGA needs an exhorbitant $4000 extra licensing fee. I remember a few days ago I thought I saw a billion gate FPGA! but I must have read it wrong.Is there smaller ones which have a free license? - I need something I can afford.I just shaved some more off the ALU and it should fit in 7366 gates now, by dropping precision and simplifying the geometry, if I only put 1 physics step in there physically, instead of the 20, I know its still a bit big, but its smaller than it used to be. Have to see if I can get it even less tho!

author: gnuarm
author_rank: Super Contributor
timestamp: April 12, 2021, 03:45:24 pm
content: Quote from: Capernicus on April 12, 2021, 03:17:53 pmYes, you read it wrong. When I searched I found a board vendor with 200,000,000 gates per board with four chips. You don't seem to understand the distinction between a gate and a LUT. You also need to understand that an FPGA is not just LUTs. It also has about as many FFs which take a number of gates to make and the routing also uses transistors although not as gates, but the area of the routing is more than the logic. The VU19P has 9 million LUTs, not a billion.QuoteYes, many. Check out Xilinx web site as well as Intel's.QuoteWhy do you keep talking gates??? If you mean LUTs, that is a huge number of LUTs for an ALU. Why don't you post your code?

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 12, 2021, 03:56:39 pm
content: I would post my code, but its not worth showing yet its all comments still, I've gone through 3 more revisions now to get it as tight as it is, I could post the method steps, but not the actual code yet. Its a stick insect walking on a flat plane, would you believe.U wonder what I'm up to.Thats why I was talking about pong before, its similar, its just a little game the same, and I need to run it as many times as I can in a second.Its taking me a while because I haven't even got the new rotation instructions down pat yet, I'm not using matrix multiplies, I'm doing the rotate with additions instead.Heres a video of my old version running on the GPU. (this new one is going to be way better!!)To get that to happen again (10 million times better) I need an ALU with these steps in it->// 1. integrate rigid body, hinge rotations and the reverse reaction.// 2. generate the points. (this can be low depth!)// 3. get the lowest point below the floor level.// 4. binary hone this one point to find the intersection point.// 5. recompute the tipping axis, and the reverse reaction point/hinges.// 6. integrate rigid body, hinge rotations and the reverse reaction.(I think I can do that in 1000 adds, but i have to see for sure..)and that runs one frame of the physics simulation... then i just need to keep spamming it as fast as I can to get it to move along.

author: rstofer
author_rank: Super Contributor
timestamp: April 12, 2021, 04:16:00 pm
content: Quote from: gnuarm on April 12, 2021, 03:45:24 pmTruly, gates is a useless number and Xilinx gave up on it some time after the Spartan 3. It's all about cells or LUTs these days. The problem is, it's hard to estimate how many LUTs are required because the synthesizer lays out the logic. It splits 6-input LUTs into 2 5-input LUTs whenever it wants. It's way smarter than me so I just let it do it's thing.So, if the synthesizer wants to do all the work, fine, just tell me what percentage of each resource is allocated and I'll take it from there. I can select the biggest chip in the family for the design steps and back off when I see the LUT count (or flip-flops or BlockRAM or <some other constrained resource>.Unless latency with respect to an external event is a critical design parameter, pipeline everything. If you can't do 'n' operations in parallel, do them serial (step by step) and just accept the latency. In concept, everything is done in just one clock cycle. It just takes 'n' clocks to get the result of any particular input.Pipelining eats up a lot of flip-flops saving state at each step. Good thing we have so many!Why does Vivado cost so much for the commercial version? Maybe because it took 1000 person-years and $200 million to develop. The big developers would rather pay once for the tools than have the cost of Vivado amortized over all the devices they buy. Hobbyists would rather pay more for the chips (of which they will buy very few) than pay for software. We're just damn lucky to get the software at all. There was a time when there were no free versions of anything.https://en.wikipedia.org/wiki/Xilinx_Vivado

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 12, 2021, 04:31:32 pm
content: This is what im making (PPU)https://en.wikipedia.org/wiki/Physics_processing_unit

author: emece67
author_rank: Frequent Contributor
timestamp: April 12, 2021, 07:51:24 pm
content: .

author: ebastler
author_rank: Super Contributor
timestamp: April 12, 2021, 08:21:43 pm
content: Quote from: emece67 on April 12, 2021, 07:51:24 pmI believe we are witnessing some kind of midlife crisis. "Oh gosh, I have missed out on FPGAs all my life. I need to get me the biggest, baddest FPGA of them all, and I need to get itnow!"

author: Bassman59
author_rank: Super Contributor
timestamp: April 12, 2021, 09:36:06 pm
content: Quote from: ebastler on April 12, 2021, 08:21:43 pmYeah, seriously, he should just buy a two-seat convertible roadster! It might be cheaper than that biggest, baddest FPGA of them all!

author: james_s
author_rank: Super Contributor
timestamp: April 12, 2021, 09:49:02 pm
content: When you can fit an entire 8 bit computer complete with VGA video, PS/2 keyboard and a UART in one of the cheapest FPGA boards on the market I have a hard time getting excited about really big parts. It's going to be different for everybody but I have never come close to filling up the midsized Cyclone II on my DE2 and that isn't even big by modern standards, most of my projects are block RAM constrained. The bigger the FPGA, the longer it takes to compile, and that is primarily why the little $13 Cyclone II boards are the ones I use the most often, they're big enough for most of the stuff I'm playing around with, and they compile in a few seconds. Compiling the same project for a big FPGA could take several minutes. Compiling something that actually fills that big FPGA could take hours.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 12, 2021, 10:00:29 pm
content: Quote from: Bassman59 on April 12, 2021, 09:36:06 pmComputer cost as much as a car... then he walks to the shop for a pie and hasn't got a license.

author: Bassman59
author_rank: Super Contributor
timestamp: April 13, 2021, 03:40:02 pm
content: Quote from: james_s on April 12, 2021, 09:49:02 pmWhat seems to be missing here is that you don't choose the biggest/baddest FPGA because you're in a dick-measuring contest. You choose the part that fits the design need. In some cases, that need is a Spartan 3AN50 or a Lattice MachXO2 1200. In other cases, it's a big/bad Virtex7 like a friend is using for a radio astronomy project.As a rule I have no need for FPGA development boards. My designs need the external peripherals and connections they need, and eval kits never have the rest of the hardware. And if you have to spin a daughter-card to get that extra stuff, why not put the FPGA on the end product's board straight away? (Wearetalking about product design, not hobby stuff, right?)OK: I will admit to an exception of the "no need for FPGA development boards." I needed to prove that a PolarFire FPGAs gigabit transceiver could be configured to talk to an existing design's transceivers over fiber with an SFP+ module. (If that didn't work then there was no point in pursuing the PolarFire as a solution.) I was all set to design a small test board to do that, but then I found a board from Future which was $179 and had the SFP connector attached to one of the FPGA transceiver ports and there's no way I can beat that price for a one-off! Oh, yeah, the PolarFire transceiver works well, once you figure out how to configure the thing.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 13, 2021, 09:12:29 pm
content: Is the Lattice MachXO2 1200, 1k gates/LUTs?I wonder what decides the price of an fpga, why "this many gates = this many dollars?" I wonder, do they run benchmarks on GPUs and then see what matches what FPGA?I'm just taking a rest from my work, But I've got a bit more done, Doing the 3d maths in such a wierd way gets tiresome, and my poor head to begin with.

author: ebastler
author_rank: Super Contributor
timestamp: April 13, 2021, 09:21:47 pm
content: Quote from: Capernicus on April 13, 2021, 09:12:29 pmNo, they don't.They don't care about GPUs.Those are different beasts.Don't keep mixing them up please.Has anyone mentioned this before?

author: james_s
author_rank: Super Contributor
timestamp: April 13, 2021, 09:28:53 pm
content: Quote from: Capernicus on April 13, 2021, 09:12:29 pmPrices are determined by their marketing department, it's based on features compared to their other products, and performance binning across parts of the same type. Just like any other high dollar semiconductor.What is your obsession with GPUs? FPGAs and GPUs *ARE NOT RELATED*, they don't do the same thing, they don't work the same way, they're not used for the same tasks, STOP COMPARING them, it doesn't make any sense. Do you see supermarkets comparing apple pie to beef stew? Are resistors better than capacitors? Are LEDs better than rectifier diodes? Do hammers perform better than crowbars? That all makes as much sense. You keep circling back to GPUs for reasons that are a mystery to me and it's starting to feel like trolling.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 13, 2021, 09:39:05 pm
content: Sorry, but I think I do have a point here.GPUS and FPGAS can actually run the same task. AND! U can make a gpu on an fpga! Its another kind of microcontroller.If fpgas were cheaper than GPUS then it would cheaper to make a gpu on an fpga.Both a gpu and an fpga are digital logic, they are the same thing, wires connecting transistors. A gpu is an fpga in the form of a gpu with the programmality removed.So the market would have to take it into account to a degree.

author: james_s
author_rank: Super Contributor
timestamp: April 13, 2021, 09:56:53 pm
content: Yes and you can hammer in nails with a crowbar, or you can pry things apart with a claw hammer, they're both made of tool steel so they're the same thing in a sense and if crowbars were cheaper than hammers you could build a house using crowbars instead so the market would have to take that into account.Yes FPGAs and GPUs (and CPUs and ASICs and...) are made of silicon and comprised of logic gates and other various elements, and yes they can do some of the same tasks. Yes you can make a GPU (of sorts) out of an FPGA but youcannotmake an FPGA out of a GPU. The FPGA is a massive digital breadboard that you can "wire" into any sort of digital device you want, THAT is what makes it so powerful, it is versatile, it is flexible, a GPU on the other hand is a hardwired device, it will always be a GPU, it is a microprocessor, it cannot do anything at all without code and you can never change what it is, you cannot add a new instruction or tweak an existing one to work differently, the design is cast in stone.An FPGA is a block of clay, a GPU is a ceramic mug. You can make a mug out of a block of clay, it probably won't be as nice as a mug you can go buy from the store but you can make it exactly the way you like, precisely the dimensions, shape and design you want, your imagination is the limit. You're not limited to a mug either, you can make a vase too, or a flower pot, or a floor tile, or a trivet to set hot pans on, or a candle holder, a sculpture, or if you're like some of the kids in my Ceramics class in highschool you can make a bong and hope the teacher doesn't realize what it is. Blocks of clay are not really competing with ready made mugs, making your own mug will probably cost more, depending on your skill it will probably not turn out as nice, and it will certainly take a lot more time and effort but in exchange you get the flexibility to make whatever you want, to specify every detail, to tune and tweak the design in any way imaginable.Maybe you need one very special mug designed specifically for some very unique need that will never be made in volumes sufficient to have them mass produced, or maybe you have an idea for a new type of mug that you wish to test out in the field before committing to the considerable cost of manufacturing a batch of tens of thousands of them, THAT is what FPGAs are good for, and THAT is what people pay the money for. If they need a GPU they buy a GPU, but a GPU is useless if you need something that doesn't involve mathematical calculations of the sort used to render 3D images.

author: ebastler
author_rank: Super Contributor
timestamp: April 13, 2021, 10:04:53 pm
content: Quote from: Capernicus on April 13, 2021, 09:39:05 pmThis is either a rather lame trolling attempt or an indication of rather muddled thinking.I'm out of here, have fun with your digital fpga microcontroller gpu logic programmality transistors.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 13, 2021, 10:20:22 pm
content: You can emulate an fpga with a gpu.

author: james_s
author_rank: Super Contributor
timestamp: April 13, 2021, 10:27:18 pm
content: Quote from: Capernicus on April 13, 2021, 10:20:22 pmNo, you can't.You could emulate some of the behavior modeled by an FPGA, but not any more than you can simulate any electronic circuit on a general purpose computer, it won't be the same thing and it won't be useful for the sort of applications that FPGAs are good for. Going back to an earlier example, even Pong cannot be emulated at a gate level anywhere near real-time on even a modern high end PC.

author: Capernicus
author_rank: Frequent Contributor
timestamp: April 13, 2021, 10:43:36 pm
content: depends on how much estate is devoted to the gpu.

author: emece67
author_rank: Frequent Contributor
timestamp: April 13, 2021, 11:20:55 pm
content: .

author: Daixiwen
author_rank: Frequent Contributor
timestamp: April 14, 2021, 07:56:19 am
content: Quote from: Capernicus on April 13, 2021, 10:20:22 pmIt's in fact a lot easier to emulate an fpga with a cpu. It's called an hdl simulator.

author: dietert1
author_rank: Super Contributor
timestamp: April 14, 2021, 08:34:09 am
content: Nonsense. We don't call this "emulation" but "simulation". It will be a factor 1000 or more slower than the real FPGA and completely useless except for debugging the VHDL description to some extent. Nobody will simulate a complete FPGA solution but only components.Regards, Dieter

author: emece67
author_rank: Frequent Contributor
timestamp: April 14, 2021, 10:15:21 am
content: .

author: dietert1
author_rank: Super Contributor
timestamp: April 14, 2021, 10:50:11 am
content: A simulation will never be an emulation, that was the wrong term and it represents a stupid idea. Even if you have a powerful simulator, it will still be a lot slower than the original. Of course, if you abuse an FPGA to simulate an ARM processor, the original will probably run faster and you have a chance of making an emulator for that FPGA. Everybody understands that FPGAs can be used to simulate or even emulate other types of logic. The other way around it's simulation only.Regards, Dieter

author: Daixiwen
author_rank: Frequent Contributor
timestamp: April 14, 2021, 11:14:25 am
content: should have put a smiley there.... my point to Capernicus was that if you want to have a gpu to emulate an FPGA, you'll run into the same set of problems than when simulating with a CPU. It may work in real time for some simple designs, but most of the time it will be a lot slower.if you need to run an algorithm that GPUs are well optimized for, then by all means use a GPU. Trying to port it to an FPGA would probably be a waste of time and resources. But there are all sorts of algorithms FPGAs are better suited for, if you are looking for performance.

author: vaualbus
author_rank: Frequent Contributor
timestamp: May 12, 2021, 09:30:18 am
content: Trolling aside you main problem is another you thing about FPGA as computer where to run code and this yield to you about confusion.When you are using FPGA you are not programming per se what you are doing is telling what the hardware should do by synthesizing it into a set of LUT/ALU/FF/ecc.You are not compiling the code and make it run. So first I don't think a body simulation is good for FPGA also because a part form your algo than in FPGA you should implement video/memory controller/ecc and above this it's not easy to made a board with DDR4, for example, memory in term of layout too.You are missing some points. Also before thinking about which FPGA you use you should have your RTL design ready and simulated and be sure it work. After you would look at your CAD software and knowing the resource the designed required chose which FPGA to use. In there you would also decide which optimization to perform ecc.So I think you main problem is that you think you can program as you program a software an FPGA and that is not correct either.

author: vaualbus
author_rank: Frequent Contributor
timestamp: May 12, 2021, 12:28:32 pm
content: good luck running 2ghz on FPGA..... Before making any quote you should realize what it mean don't pretend to know stuff when you are saying bul***.FPGA cannot be used when the bitrate is high as the fact that there is a routing network i there make the critical path longer so the overall fMax is lower.There is a reason why you need ASICs, there you can decide the floorplan of the chip to reduce as much as possible the critical path.Also you are completely unaware of how a digital design is performed is not like programming