PCB layout: connecting pins with power plane - Page 1
Forum section: electronics / beginners

author: Moriambar
author_rank: Unknown
timestamp: August 20, 2023, 09:34:07 am
content: Hi.When having a powerplane in my pcb, I usually do not connect pins that belong to that plane.EG: let's say I have VCC on the F.Cu and GND on the B.Cu layers. If my part is THT I never connect those pins to other VCC pins or GND pins (with smd parts I just use vias to connect the proper pins to their planes). This assuming the copper fill will reach my pins ofc.What I've seen in some tutorials, though, is that regardless of the fact that the pins are connected through a power plane, the designer still connects power pins together and gnd pins together.Is this a best practice? If so why?Cheers!

author: DavidAlfa
author_rank: Super Contributor
timestamp: August 20, 2023, 12:25:11 pm
content: Why? Power planes should automatically connect these pins.Any missing connection will be detected by DRC tool.I only saw this in crappy yt videos. Just like soldering 2 parts using 1/2 ton of flux.

author: Moriambar
author_rank: Unknown
timestamp: August 20, 2023, 02:24:28 pm
content: Quote from: DavidAlfa on August 20, 2023, 12:25:11 pmI won't disclose the source but, being a non professional, I just tend to assume that others know better.For reference in the videos/book they also use a hatched fill pattern for no reason at all apparently.Thanks for your reply though, glad I've been avoiding a lot of useless work

author: DavidAlfa
author_rank: Super Contributor
timestamp: August 20, 2023, 03:17:42 pm
content: I'm neither a professional designer! But I've never seen that in properly designed pcbs.In fact, I never connect any gnd pin.I route all the signals, then place the power plane.Then I see mistakes, perhabs missing connections as the copper plane might not be able to reach everything, so I optimize the layout to fix that, removing islands or weak ground connections.But this might be a terrible practice because I'm not engineer.Another issue I see a lot is people forgetting to connect bottom and top planes through vias to enhance the ground.Search "via stitching".

author: sparkydog
author_rank: Regular Contributor
timestamp: August 21, 2023, 04:41:36 pm
content: Quote from: Moriambar on August 20, 2023, 09:34:07 amDepending on your EDA software, onepossible, reasonable explanation (that I've seen from another user on this forum, in fact) is to get traces to those pins that are wider than the default thermal spoke width. However, this would typically only be done for those few pins that handle a lot of power and not foreverything. Sometimes you can also use this technique to bodge thermal spokes if you don't like how your EDA is doing them. I feel like I've even done this myself a couple times.However, you would normally see this done only for specific pins (and when adjusting the per-pin thermal spoke size isn't sufficient, or because your EDA doesn't give you that option), not for everything, and the traces might "end" once they encounter a pour....but I'm generally with DavidAlfa; connectingeverythingwith traces when you're just going to add a pour over the same is silly. (But I'malsonot an EE, so what do I know? 🤷)

author: PlainName
author_rank: Super Contributor
timestamp: August 21, 2023, 05:54:49 pm
content: Yeah, I do it. Main reason is to know it can be done as I'm going along, and to know that the pins aren't just connected but aren't at the end of a long thin twisty track that passes DRC but isn't optimal. Essentially the same reason I don't use auto routing. In the end it doesn't add much time but adds peace of mind - what's not to like?

author: JustMeHere
author_rank: Frequent Contributor
timestamp: August 22, 2023, 02:14:39 am
content: Are you talking about a 2 or 4 layer board? Hopefully you are talking about 4 layer boards because they are much easier to route and are the same price as 2 layers these days. If you're talking about a 2 layer board, I'd avoid panes all together. Slots in panes are bad for EMI. So you should avoid panes on 2 layer boards. On 2 layer boards you will need to make sure to keep your loops small.

author: Smokey
author_rank: Super Contributor
timestamp: August 22, 2023, 03:26:14 am
content: For 4 layer boards with a full ground plane layer...Anything that needs heatsinking (typically to ground for lots of chips with a thermal pad) gets a localized ground copper pour on the top or bottom around the part. That gets stitched to the inner ground layer. Anything that has a ground pin that gets caught up in that localized pour gets a thermal spoke into the pour (as well as a via to the inner plane).Pretty much everything else just gets a via down to the inner plane. Two vias if I'm worried about impedance or it's higher current or something.

author: Moriambar
author_rank: Unknown
timestamp: August 22, 2023, 06:08:06 am
content: Quote from: JustMeHere on August 22, 2023, 02:14:39 amThe examples I've seen were both for 2 and 4 layer boards.

author: JustMeHere
author_rank: Frequent Contributor
timestamp: August 22, 2023, 07:32:57 am
content: Chapter 5 in this book is what convinced me to never run a trace on a ground or power pane. The author is considered one of the best in the world. See section 5.3 for TLDR. Even if you aren't running 100MHz signals, the edges of your 1 Hz square signal will suffer. 4 layer boards are much easier to route than 2 layer boards. I will never do a 2 layer board again.http://electronix.org.ru/books/high-speed-digital-design.pdf

author: PlainName
author_rank: Super Contributor
timestamp: August 22, 2023, 07:53:20 am
content: Quote from: JustMeHere on August 22, 2023, 07:32:57 amI think you misunderstand (or I do). The question is not whether a signal should (or should not) be routed on a plane, but whether theplaneconnected pins be connected via discrete trackingas wellas being plane connected. Electrically there is no difference at all, and that book isn't relevant because it's talking about something else.And, to avoid further confusion, we are not talking connections on one layer and the plane on another, but both on the same layer (so, technically it's not a plane but a flood fill). That is, you route with tracking and afterwards flood fill over that.Clearly (or it should be), if you're using a plane properly then the discrete routing should be a waste of effort. If you're flood filling then it should still be a waste but you are relying on DRC to save your ass. And, as I pointed out earlier, DRC can say it's OK whereas it could be rather suboptimal.

author: Moriambar
author_rank: Unknown
timestamp: August 22, 2023, 08:27:17 am
content: Quote from: PlainName on August 22, 2023, 07:53:20 amthis was exactly my question, you got it.QuoteexactlyQuoteThat's what I thought, thanks

author: sparkydog
author_rank: Regular Contributor
timestamp: August 22, 2023, 06:59:05 pm
content: Quote from: JustMeHere on August 22, 2023, 02:14:39 amI wish people would stop saying this. No, they are not... generally. Only from specific suppliers (JLC?), only for very small boards, and only for several other specific criteria. (For example, I seem to recall you can only get them in green... which may not matter to you, but then again, maybe it does.) You get alotmore flexibility with 2-layer boards before the price starts to skyrocket.Of the boards I've designed, onlyoneis small enough to even qualify, and I ended up sticking with my two-layer design for a number of reasons.Don't assume 2- and 4-layer boards are the same price. Figure out your board size and get a quote (the initial form will update in real time with no Gerbers) first. There might be some cases where 2- and 4-layer are the same price or where the difference is negligible, but it'snotuniversal.

author: WatchfulEye
author_rank: Regular Contributor
timestamp: August 22, 2023, 07:39:54 pm
content: Quote from: PlainName on August 22, 2023, 07:53:20 amWhen I've designed 2 layer boards, I've tended to route ground/power for sensitive components, and then pour afterwards. This ensures that components which should be low-inductance connected (e.g. decoupling caps) are connected are connected optimally.For example, I was getting jittery and noisy outputs on a low cost MCU dev board. Examination of the board showed that the current path between the MCU and decoupling cap had to go through 6 vias and had a total path length of nearly 10 cm through multiple segments of copper pour. Modifying the board to add direct wire connections between MCU and capacitors greatly reduced the noise.

author: Infraviolet
author_rank: Super Contributor
timestamp: August 22, 2023, 09:10:41 pm
content: For 2 layer I usually deal with low inductance traces first, then lay out the ground plane area, then route all the signals, and finally rebuild the ground plane in whichever way leaves the lets any gaps in it be routed around without long diversions. Power on two layer boards usually gets thick traces, or thin ones are often adequate, and not a partial plane of its own.