Level Shift - Page 1
Forum section: electronics / projects

author: Tnixsw
author_rank: Contributor
timestamp: August 22, 2025, 03:18:59 am
content: HI all, I am not an engineer by any stretch of the imagination and am having trouble level shifting a system clock signal which is +6V to -12V from some 1970's digital equipment of which a non-obtainium part has failed. I would like to replace this using a modern micro but need to use a 0 - 5V input signal. The actual signal is +6V for about 5uS and -12V for around 1uS - see attached. All I need is to capture as close as possible, the leading edge of the low going pulse. So far from my simple ideas, I am getting what looks like a discharging capacitor causing timing issues.Any help appreciated, thank youTony

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 22, 2025, 03:25:49 am
content: Quote from: Tnixsw on August 22, 2025, 03:18:59 am0-5v is within +6 to -12 so a simple clamp will do. ie a series R and diodes to V+ and GND, or a series R and a diode+resistor to GNDOr, aresistors onlysolution also exists, that avoids going > 100mV outside the rails.:11k series , 47k to GND, 4k7 to +5V gives -83mV to 4.953V from -12V~+6V, rise time of appx 60ns into 10pF load.or 11.3k, 51k, 4k7 gives 5mV to 4.970V from -12V~+6V, but a clock signal does not need to be anything like that precise.Quote from: Tnixsw on August 22, 2025, 03:18:59 amCapture by what, to what resolution?

author: pqass
author_rank: Super Contributor
timestamp: August 22, 2025, 04:51:52 am
content: See attached for some solutions (incl. a couple noted by PCB.Wiz). I like the transistor-based options. Simulation ishere.

author: Tnixsw
author_rank: Contributor
timestamp: August 22, 2025, 05:23:59 am
content: Quote from: PCB.Wiz on August 22, 2025, 03:25:49 amThank you for the reply.My processor has to have new data ready in an output buffer only during the LO period of the clock signal then as soon the clock goes HI, this data will appear on a common serial bus until the clock goes LO again. With my simple methods producing a skewed low input signal, this is proving a headache. Having the data ready is no problem, it is making sure it is in the buffer only during the 1uS LO clock, so I need an input signal that follows the LO going clock edge as closely as possible to trigger the transfer. Attached is a clock signal showing the relationship with some 1000001 data bits belowI tried a 1N4148 with resistor to ground and get a capacitive discharge type of signal longer than the LO pulse. I'll try the other values you mention.cheersTony

author: Tnixsw
author_rank: Contributor
timestamp: August 22, 2025, 05:26:56 am
content: Thanks 'pqass' I will try the suggestions.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 22, 2025, 05:39:43 am
content: Quote from: Tnixsw on August 22, 2025, 05:23:59 amWhat value resistor did you use, and what load capacitance (scope probe on x10 ? )What is the rise/fall times of your clock?If your load C is significant, (10's of pF) you can add a small C in parallel with the 11k series resistor, to shave off some RC rise time effects. About 39% of your load C is ideal, you then match the source fall time.That will be the fastest leading delay, as there is no Td or Ts effects of an active part.

author: Tnixsw
author_rank: Contributor
timestamp: August 22, 2025, 07:02:28 am
content: Probe on 10xI setup the PNP transistor solution using a BC558 (all I had) and got the results in image which is similar to all the tries I have had so far. Clock (yellow), Emitter out (Blue), Processor out (Purple). The processor is just running a small loop to detect HI and LO input. I tried another faulty original board and this one has a slightly faster clock rate. I'll try the resistive solution, but bread-boarded connected by leads to the original IC's might be adding to the problem.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 22, 2025, 07:26:12 am
content: Quote from: Tnixsw on August 22, 2025, 07:02:28 amWas that with 4k7 and 330 ?Spice says that should be << 100ns, on leading edge, did you wire it correctly, or does it have a very large load C ?If I flip the PNP backward, spice gets close to that terrible.

author: pqass
author_rank: Super Contributor
timestamp: August 22, 2025, 07:49:30 am
content: QuotePNP emitter should be tied to +5V, right?With the collector as the output and a 330R to ground?See the PNP option in the attachment in my last message.Also, I forgot to mention that the all transistors have"storage charge"which introduces an off delay of typically 1us or so. I discuss ithere. You can eliminate the delay by just putting a 100pF cap across the base resistor.Also, another solution may be to just use a 74HC125 buffer (Vcc=+5V) with a 1K resistor on its input. According to thedatasheet, IIK"Input clamp current(2)" is +/-20mA with "Note (2): The input and output voltage ratings may be exceeded if the input and output current ratings are observed." i.e. a level shifter that can handle input voltages beyond its supply rails.

author: Tnixsw
author_rank: Contributor
timestamp: August 22, 2025, 01:36:14 pm
content: Arrrg - long day, you were absolutely correct pqass, reversed transistor. New image attached, looks great. As you also mention there is a 1uS lag on the falling edge but that is of no consequence. Many thanks for your help, I can now move forward.

author: aeg
author_rank: Regular Contributor
timestamp: August 23, 2025, 01:53:02 am
content: Quote from: pqass on August 22, 2025, 07:49:30 amThis is not a good idea. As stated in Note (1), the +-20mA clamp current is "stress ratings only, which do not imply functional operation of the device". When you exceed the input voltage range of 0V to Vcc, specified in the recommended operating conditions, there is no guarantee that the device will meet the characteristics shown in the datasheet, or that it will even operate as a buffer.(Edited to be less nasty and more informative)

author: pqass
author_rank: Super Contributor
timestamp: August 23, 2025, 03:52:35 pm
content: Quote from: aeg on August 23, 2025, 01:53:02 amI would normally agree but this part is specifically used in 5V to 3.3V level-shifting.So adding a 1K input resistor would guarantee no more than 12mA at -12V and 6mA at +6V, which is within spec.

author: aeg
author_rank: Regular Contributor
timestamp: August 23, 2025, 11:11:09 pm
content: Quote from: pqass on August 23, 2025, 03:52:35 pmNo, it's not. 74HC125 is not appropriate for 5V to 3.3V level shifting. 74AHC125 has different ESD structure and is appropriate for 5V to 3.3V level shifting. Neither one is OK to routinely handle a -12V input.Quote from: pqass on August 23, 2025, 03:52:35 pmNo, it's not. Spec for functional operation (in recommended operating conditions) is Vi of 0V to Vcc. Not -0.6V to Vcc+0.6V. All functional and parametric characteristics go out the window when you dump current into the substrate through the ESD diodes.

author: bingo600
author_rank: Super Contributor
timestamp: August 24, 2025, 07:55:44 pm
content: +6v and -12v ...Could you sneak in a MAX232 ?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 24, 2025, 08:20:07 pm
content: Quote from: bingo600 on August 24, 2025, 07:55:44 pmThat would be level compatible, but no where near fast enough.

author: ledtester
author_rank: Super Contributor
timestamp: August 25, 2025, 12:48:11 am
content: Quote from: PCB.Wiz on August 24, 2025, 08:20:07 pmI was actually looking into trying it or possibly simulating it. I'm holding out hope that it could work since you're only using the receive circuitry.

author: langwadt
author_rank: Super Contributor
timestamp: August 25, 2025, 01:12:10 am
content: Quote from: aeg on August 23, 2025, 11:11:09 pmdepends on who you ask,https://assets.nexperia.com/documents/data-sheet/74HC_HCT125.pdf

author: MathWizard
author_rank: Super Contributor
timestamp: August 26, 2025, 07:04:35 am
content: So what about trying a cascode amplifier? How much faster would the 2 BJT version be ? I'll have to try that myself in LTSpice.1us low time is pretty fast, I think the ATmega Arduino family is based off stuff from the 1970's, so yeah maybe that's why common Atmel MCU's are usually too slow for much stuff w/ 1us signals.But it makes me wonder how anything got done, like in TV's w/ VHF/UHF. Going by op-amps, I guess all these discrete circuits had pretty low gain to get any high speed.