Logic pin must be high or low, what happens with power loss?   - Page 1
Forum section: electronics / general

author: viper
author_rank: Regular Contributor
timestamp: September 30, 2025, 02:21:24 am
content: ESP32 connected to another IC with I2C in which I want the ensure the slave device is off if the ESP does not have power. The slave has a CE pin indicating the device is enabled when pulled low, and disabled when high, but says "do not keep floating". I would say it would be floating if the ESP is off and can't do either? This relates to a charger IC where there is likely good battery power, or even adapter power, but the safest route is to deny charging unless the ESP has I2C connectivity, alive, and gives the CE pin authority.

author: Psi
author_rank: Super Contributor
timestamp: September 30, 2025, 02:23:21 am
content: If you want one state when off, or in reset, use a pullup resistor to ICs VCC or pulldown resistor to ICs GND.Just need to make sure you're not trying to pull any IC pins high when the chips own VCC is off. Or it will back feed and power the chip upIn this case, if I understand correctly, you would pull CE high with pullup from any battery or adapter power (making sure voltage is right). Then your ESP can pull this low to turn it on when needed and its always off if the ESP is off..

author: viper
author_rank: Regular Contributor
timestamp: September 30, 2025, 02:51:27 am
content: Quote from: Psi on September 30, 2025, 02:23:21 amAgree, that is likely the answer. I just need to figure out the safe logic high V, as battery will be much higher and the goal is extremely low sleepy consumption. Not sure of the right approach just yet.

author: free_electron
author_rank: Super Contributor
timestamp: September 30, 2025, 04:22:27 pm
content: If the ESP32 is powerless it will take energy from the pull-up resistor wired to the CS pin. Even though the current may be low and not enough to power the ESP32, it is leakage !put a mosfet between them. ESP32 drives the gate. The drain can pull the CS low. Put a pull-down resistor on the gate.No energy can flow backwards through this fet since the gate is a floating object in respect to the drain. You can do this with an NPN as well. the base-emitter is reverse biassed if the ESP32 is off so there will be no current flow.An ic that is powered off is not "floating". The ESD diodes will shunt incoming energy to the power rails, unless that particular pin does not have protection diodes. That is very uncommon for CMOS devices.You need to prevent energy from leaking to the powered off device

author: viper
author_rank: Regular Contributor
timestamp: September 30, 2025, 05:37:22 pm
content: Quote from: free_electron on September 30, 2025, 04:22:27 pmWhat about an optocoupler? I tend to like them anyway from a circuit protection standpoint. Program a GPIO to go high, which connects the CE pin to ground. ? I guess I need to better understand the MCU behavior when powered down. By design, technically the ESP should never be powered down, only in sleep states, but I have to plan for anything.Edit, crap, that still leaves the CE pin floating when Opto is open.

author: viper
author_rank: Regular Contributor
timestamp: October 01, 2025, 01:06:10 am
content: just an update to stoke the fire. I have collected the Logic data for that pin config to aid in the design. All values are relative to GND. CE max is 0-6V, min level high state is 1.3V, max level low is .4V, and leakage current on CE with 1.8V input is 1uA.What I am thinking is a pull up to that pin, more than enough to serve 1uA so the internals of chip govern that. Then need your thoughts on how best to pull it low? Is an opto an overkill? I don't expect bad things to happen. Primarily I need low leakage in the off state, in which I would probably serve that pin at 3.3V.Probably very simple here, just trying to build a robust circuit. It will only take a single component to kill the whole device.

author: ledtester
author_rank: Super Contributor
timestamp: October 01, 2025, 03:39:05 am
content: I'm curious what you mean when you say the ESP32 is "unpowered".If the ESP32 is in a sleep mode (deep- or light-) it remains powered but its GPIO pins may change to high-impedance mode. In this case you shouldn't have to worry about free-electron's concern about the ESP32 taking power from the I2C lines.From this discussion:https://electronics.stackexchange.com/questions/350158/esp32-how-to-keep-a-pin-high-during-deep-sleep-rtc-gpio-pull-ups-are-too-weakusing calls like gpio_hold_en() call you can tell the ESP32 to have a GPIO remain an output through the deep- or light-sleep. Also see the gpio_hold_dis() and gpio_deep_sleep_hold_dis() calls.If your ESP32 is actually powered-off (disconnected from one or both power rails) that's a different situation.

author: viper
author_rank: Regular Contributor
timestamp: October 01, 2025, 04:48:25 am
content: Quote from: ledtester on October 01, 2025, 03:39:05 amThanks! I will try to clarify. I am both working power mode strategies for this MCU to hit the end results, but also evaluating the worst case scenarios, and one of those is the MCU totally dies or it's power source fails. I simply need/want to ensure there is not a nuclear moment. Reason I mention is it will only take a single component failure to kill the design, so I am trying to be proactive. This is one reason we are using a battery fuse as opposed to other strategies. It won't matter what caused the fuse failure other than to know something serious happened. We would then want the device back for evaluation.But circling back, my question was indeed a dead MCU, but also trying to understand the behavior pattern of other power modes. One of the strategies in play is to use higher power levels but only until we see a lower battery concern, in which we can switch to a very low power mode. One that asks the circuit to do nothing at all, other than survive until it can get some charge.