How many transistors / gates can a signal get through? - Page 1
Forum section: electronics / beginners

author: Richardcavell
author_rank: Contributor
timestamp: February 21, 2023, 02:16:41 pm
content: Hi. I’m an electronics enthusiast, self-taught.I am a fan of the Motorola 6809 and Motorola 68000 CPUs, which run at about 1-4 MHz and 8-16 MHz.At those speeds, how many transistors or gates can an electrical signal get through? If I were to design those CPUs, or a peripheral chip that is intended to interface with them, how conscious should I be of propagation delay?Richard

author: pcprogrammer
author_rank: Super Contributor
timestamp: February 21, 2023, 02:56:42 pm
content: You can find a lot of information about this in the datasheets.The technology you mention is old and slow and can work with quite some delay. How much gates can be used in a control chain depends on the delay of each gate and the type of the technology used.But what do you mean with "If I were to design those CPU's". Are you thinking of using the technology in an FPGA?To learn about this older technology look at how computers where designed using these CPU's. Like for instance theTandy CoCo 1 schematics.

author: rstofer
author_rank: Super Contributor
timestamp: February 21, 2023, 03:15:03 pm
content: As signals race through the logic, so does the clock. Those monstrous mainframes of yesteryear sent signals through many feet of wire between gates. But the clock went through the same distance so for all appearances, the delay was not significant as long as a signal didn't need to return. Same with transistors or any other form of logic. The signal is coming and so is the clock.But if the signal needs to come back to the beginning then the timing gets critical. You start to add up the logic delay at every level of logic. Here are a few definitions:https://testbook.com/question-answer/for-a-transistor-used-as-a-switch-td-is-delay-tim--5fb63c256d800165e58aabb3You can look at the 2N2222A datasheet and find that it is good for 350 MHz under some condition. Figure maybe a more realistic 100 MHz (10 ns delay) and divide by the number of logic levels.https://www.onsemi.com/pdf/datasheet/p2n2222a-d.pdfAs to external peripherals, the CPU has certain expectations of external timing and if a peripheral can't meet it then there is always the HOLD' signal to cause the CPU to wait. But even that has timing constraints.The time delay inside a CPU chip is pretty small because the distances are so short. That's why we can have GHz CPUs - short distances and low capacitance. And architecture that minimizes the logic levels plus the addition of pipelining. Pipelining really saves the day. It doesn't improve latency but it does improve logic delay in one direction.In the case of FPGAs it is not unusual for the same logic expression to be evaluated more than once in order to have the output generated in different parts of the chip. This holds down time delay due to routing. Routing delay in a chip that is about 1" square and signal velocities that are some high percentage of the speed of light!There are FPGA projects re-implementing many popular CPUs and, if you actually want to build something, FPGAs are the way to go. It saves a LOT of time on wire-wrapping and a lot of heat and volume. And the toolchain will worry about timing and tell you how fast your design will run.www.opencores.org- look in the Processor tab

author: pcprogrammer
author_rank: Super Contributor
timestamp: February 21, 2023, 03:32:44 pm
content: I just remembered that there is theMOnSter 6502project.This is a functional transistor based replica of the 6502. It provides some insights in the workings of it.

author: BillyO
author_rank: Super Contributor
timestamp: February 21, 2023, 03:55:15 pm
content: Generally the faster you run a device the more susceptible it will be to PD. More specifically, it really depends on the CPU (it's tolerances) and the type of logic you are using (PD per gate).Learn to read the spec sheets. The timing diagrams and the related data lists for read and write cycles of the CPU will give you idea of what it will tolerate.The biggest concern comes in glue logic. Usually that logic that selects a particular device for teh CPU to write to or read from. The slowest popular logic are the 74LS and 74HC(T) families. 74AC(T) is much faster but tends to create noise since the edges of it's outputs can be as fast as 1ns. It is usually a good idea to not be too specific about addressing, especially I/O devices. This will help reduce the number of gate delays.One thing I have done is to move to programmable logic (GAL) to implement my chip select glue. I have had no problem fining NOS Lattice items on eBay and such that have PD as low as 7ns. That has solved the issue for me.

author: TomKatt
author_rank: Frequent Contributor
timestamp: February 21, 2023, 04:00:25 pm
content: I believe the spec you are referring to is called 'fanout' :In digital electronics, the fan-out is the number of gate inputs driven by the output of another single logic gate.A quick Googler of 6809 + 'fanout' yielded this interesting article about interfacing to the old M6809E based Tandy Color Computer that might interest you...https://www.go4retro.com/tag/dragon/

author: pcprogrammer
author_rank: Super Contributor
timestamp: February 21, 2023, 04:09:50 pm
content: Quote from: TomKatt on February 21, 2023, 04:00:25 pmFanout is only part of the issue, and not directly what the original poster asked about.But it does affect how signals behave. The additional capacitance also adds to the delay.In it's whole it is complex mater. There is setup and hold time to consider, clock skew, propagation delay, voltage levels, etc.

author: TomKatt
author_rank: Frequent Contributor
timestamp: February 21, 2023, 04:17:56 pm
content: As an aside, I've created numerous 6502 and microcontroller based projects on breadboards with jumper wires all over the place and can count on one hand the number of times that anything like propagation delay or lead lengths caused parallel bussed peripheral devices or similar to fail.

author: BillyO
author_rank: Super Contributor
timestamp: February 21, 2023, 05:00:44 pm
content: Quote from: TomKatt on February 21, 2023, 04:17:56 pmIn most cases things will work out. Especially at 1MHz or so. Push it to 14MHz and you might find more issues.In any case, the problem of PD comes up with newbies and their trying to segment memory mapped devices very specifically, like putting a UART at precisely at $C0F0-$C0F3 and they used 74LS logic to do it, like multiple stacked 3 or 4 74LS138 decoders along with a few other gates thrown in (yes, I've seen this).The fan-out issues is not one I've personally come across. YMMV.

author: Jwillis
author_rank: Super Contributor
timestamp: February 21, 2023, 09:57:11 pm
content: Quote from: Richardcavell on February 21, 2023, 02:16:41 pmIt's really about power. The older CPU's had more power behind the signal than newer CPU's with and equivalent computing capability. The more powerful the signal the less the parasitic elements (inductance, capacitance and resistance) becomes and issue.Think of it like this . You set up a stereo and put up walls in from of the speaker . The less the volume the few number of walls can be put up before you can no longer hear the music. Crank up the volume and you will here the music again.Theoretically you could build a modern CPU with vacuum valves but the layout would be the size of a football pitch and you would need your own nuclear power plant to run it.So if your use jellybean transistors it could be done . you just need more space and more power.Best regards and have fun.

author: Benta
author_rank: Super Contributor
timestamp: February 21, 2023, 10:00:47 pm
content: As the OP hasn't clarifed the intention here, the discussion is somewhat going off in any direction.

author: Richardcavell
author_rank: Contributor
timestamp: February 21, 2023, 10:43:33 pm
content: So what stopped those CPUs from running much faster?By the way, rstofer, where do you get 350 MHz from? I can see the timing info in the data sheet but I don’t see that number.

author: Zero999
author_rank: Super Contributor
timestamp: February 21, 2023, 10:59:18 pm
content: Quote from: Richardcavell on February 21, 2023, 10:43:33 pmGoing faster would mean a much smaller die, which has to be a tiny fraction of the wavelength of the clock, otherwise one part of the chip will be out of sync with the other.QuoteI very much doubt the 2N2222A can be used in a logic circuit at 350MHz. It has a GBWP at around that figure, meaning the change in base current would have to equal the change in collector current. It still will have some voltage gain, but the low base impedance would mean too much loading between one stage and the next.

author: edavid
author_rank: Super Contributor
timestamp: February 21, 2023, 11:30:40 pm
content: Quote from: Richardcavell on February 21, 2023, 10:43:33 pmIt's all about the RC delays. The relevant Rs are the on resistance of the transistors, metal interconnect, and especially the (high resistance) polysilicon interconnect. The Cs are the transistor and interconnect capacitances. As the process feature size is reduced, the Rs and Cs both get smaller, speeding up the chip.For NMOS designs like the MC6809 and MC68000, the resistance of depletion mode load transistors is especially problematic. If it's too high the gate output risetime will be too slow; if it's too low the chip will draw too much power.Since these are dynamic designs, there is also the complication that the clock cycle has to be slow enough for storage node capacitances to be fully charged.

author: rstofer
author_rank: Super Contributor
timestamp: February 22, 2023, 12:07:20 am
content: Quote from: Richardcavell on February 21, 2023, 10:43:33 pmPage 2 of the datasheet lists 300 MHz for the Gain-Bandwidth product but I see it is tested at 100 MHz which is where I discussed using it. I'm still not clear what the spec implies.

author: edavid
author_rank: Super Contributor
timestamp: February 22, 2023, 01:22:45 am
content: Quote from: TomKatt on February 21, 2023, 04:00:25 pmNo, it's called gate depth - it's roughly the clock cycle time divided by the gate propagation delay.

author: pcprogrammer
author_rank: Super Contributor
timestamp: February 22, 2023, 06:28:25 am
content: Quite a while back I read about problems with quantum effects in the getting smaller transistor sizes. Think it was about the <10nm technology, but today I found an already 2 year oldarticlethat IBM got down to 2nm technology, so it seems they found new ways to deal with this.50000000000 transistors on the size of a fingernail

author: David Hess
author_rank: Super Contributor
timestamp: February 22, 2023, 03:17:52 pm
content: Quote from: Richardcavell on February 21, 2023, 02:16:41 pmWhat ends up mattering is how long the address decoding and memory respond to a memory read request. Old CPUs were intended to be used with LS or HC logic and pretty slow memory to meet their timing requirements, and in the worst case you might get 3 levels of logic for decoding.Modern memory is so much faster, typically 50 nanoseconds or better, that the number of old logic stages can be doubles, and with faster logic like FAST, AS, or AC, at least doubled again.The maximum clock speed in a system is more about meeting the timing requirements with the access speed of the memory and decoding logic.

author: iMo
author_rank: Super Contributor
timestamp: February 22, 2023, 04:52:58 pm
content: Quote from: Richardcavell on February 21, 2023, 02:16:41 pmWhen designing such an MCU you will often get a string of many transistors/gates in series. How much it depends on the actual design, architecture and quality of the design tools. As a rule the longest propagation delay has to be shorter than the min clock period (provided we talk single clock stuff). With 8MHz single clock the longest prop delay on the chip has to be shorter than 125ns.When you put such an MCU into an FPGA with a typical propagation delay (in reality the delays differ based on type of the logical gate/element and its position within the FPGA) of, say, max 500ps per gate (in the entire operating range) you may have a string of 250 gates in series and it still will work.. But that is theory, in practice the development tool will tell you what is the longest delay inside the FPGA in a final report after placing all MCU elements, based on that number you will get whether the MCU would work at a specific frequency or not.