How far away would you place your bypass caps before you considered a problem? - Page 1
Forum section: electronics / general

author: NaDobraNich
author_rank: Regular Contributor
timestamp: September 23, 2023, 01:34:04 am
content: I’m laying out in stm32 part, using up some excess inventory on the side project.https://www.st.com/resource/en/datasheet/stm32h725ie.pdfNo ADC, no DAC, just some digital UART, SPI, IO, USB, Ethernet. It’s a BGA package, 176+25. Plan to run 260Mhz or so.I don’t have a great access to the bottom of the board. Not enough to put the bypass caps as close to the pins as I would like. This part needs like 13x 100nF and another 6x various for the internal LDO and etc. I can got down to 0401 and 0201 parts.How far away would you route these before getting concerned?In an ideal world, I think I can get the traces to be about 1mm with via. Would 4mm be OK? 6mm? I know there is no hard answer here, just gut, how far would until it’s an issue?

author: uer166
author_rank: Super Contributor
timestamp: September 23, 2023, 03:36:29 am
content: Presumably the die in the BGA is the same as the LQFP parts which are very large. The internal lead frame and bond wires are likely quite far from the die, and have no magical properties vs. traces on a PCB. I suspect you'll be okay placing all decoupling at the periphery of the BGA, just prioritize them and you'll probably be ok on emissions with a good stack up.

author: NaDobraNich
author_rank: Regular Contributor
timestamp: September 23, 2023, 03:58:29 am
content: … how have I never thought about it like that!I agree, the die probably is the same, and it’s just wires to it…. Huh.I can get most on the bottom nicely but some would have to be a little longer and it was bugging me.

author: NaDobraNich
author_rank: Regular Contributor
timestamp: September 24, 2023, 04:22:02 am
content: So thinking about it a little, if you had a high power usage, that the BGA parts should preform “better” than the large LQFP parts in terms of how much closer you can get the bypass caps? Does anyone recommend BGA parts for that reason? I’ve never seen it.The alternative is that 10mm isn’t going to hurt anything very little of it matters despite being a large topic of discussion.

author: Psi
author_rank: Super Contributor
timestamp: September 24, 2023, 04:46:57 am
content: Have you considered capacitor array packages. The kind that have like 4 caps in one package.They cost more, but are a little smaller.

author: dietert1
author_rank: Super Contributor
timestamp: September 24, 2023, 04:54:34 am
content: As there are many unknowns in this i would have a look at the STM32 evaluation boards with this or a similar MCU and try to learn from that. If you have one of those boards you could also measure how much noise appears on the external buffer caps. Using a spectrum analyzer, you can probably see the clocks and some capacitor resonances. I'd assume there are small buffer caps on chip and the spectrum should level off at some frequency (like 50 or 100 MHz).Regards, Dieter

author: Silenos
author_rank: Regular Contributor
timestamp: September 24, 2023, 11:28:11 am
content: Quote from: NaDobraNich on September 24, 2023, 04:22:02 amIf it is just for power the designs are propably optimized around it and packages. If you use proper +4 layers stackup, you should be fine - I saw 2 layers boards with old stm32f1 were noisy. You mentioned eth - I would take that eth phy is more layout demanding and noisier when it comes to power transients than your bga h7.It may starts mattering around the LDO or those integrated dc-dc converters, see the ANs. Also packages matter with ADC/DAC performance, see eg an5354.

author: peter-h
author_rank: Super Contributor
timestamp: September 24, 2023, 05:08:29 pm
content: The answer obviously depends on the chip which specifies them.There are two reasons for these caps1) to supply transient current demands without an excessive Vcc dip2) to ensure stability of (typically LDO) voltage regulatorsOn 1), if you go back say 20-30 years, 4+ layer PCBs were rare and expensive, so people used 2 layer and because the supply rails were just thin tracks, you peppered the board with decoupling caps. With 4 layer boards (inner layers being GND and VCC) this is far less critical. Also modern digital boards rarely are just hundreds of logic gate chips (74HC240 etc); you tend to have a CPU and a few other chips, so putting caps close to them is not a problem.On 2), the distance does not usually matter but if a given LDO, say LM2940CT-5.0, says thisthen youhaveto provide that capacitance.

author: nctnico
author_rank: Super Contributor
timestamp: September 25, 2023, 12:00:03 am
content: I'd follow the appnote of the manufacturer of the chip to be sure. IOW: read the manual.

author: NaDobraNich
author_rank: Regular Contributor
timestamp: September 25, 2023, 01:17:58 am
content: There’s really no need to read the datasheet on this.This is exactly what you’d expect and we’ve all seen hundred or thousand times:Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.What I’m trying to figure out is when is it too much?It’ll be a 6 or 8 layer board, and the power and ground layers are very close to each other.On my design, I have some that are about 3-4 mm away because of other bottom side components that I can’t move. I’m pretty sure it’s not going to be a problem, but that’s why I am asking.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 25, 2023, 10:28:17 am
content: Quote from: NaDobraNich on September 25, 2023, 01:17:58 amThere is no way to determine the limit beforehand, because it depends on the entire circuit and the supply. After all, IC's tend to consume current in spikes, and the bypass capacitors are intended to act as local reservoirs so that the voltage stays reasonably stable without dipping and causing errors. The amount of capacitance needed depends on those spikes, and the distance affects how fast the capacitor reacts.Some circuits even keep working when you remove some/most of the 'required' bypass caps entirely.If you examine existing boards and designs, you'll see both 1µF and 100nF ceramic capacitors of the same type in parallel, next to each other, on the same supply pin –– even though the 100nF of the same ceramic type is utterly useless there. In other words, because there is no easy to verify rules, people rely on rules of thumb, and tend to not think about it.

author: nctnico
author_rank: Super Contributor
timestamp: September 25, 2023, 11:09:39 am
content: Quote from: Nominal Animal on September 25, 2023, 10:28:17 amThe 100nf isn't useless at all. Do some measurements with a network analyser and you'll see why. For really high frequency stuff, it is even useful to put a 10nf or even a 1nf in parallel. A higher value capacitor will have a lower self resonance frequency after which the impedance rises up again. So with several values in parallel using the same package size, you get a low impedance from your power supply network over a wider frequency range.Quote from: NaDobraNich on September 25, 2023, 01:17:58 amIndeed, you need to read the application notes / reference designs to get an idea about what is critical and what is not. The datasheet is not the place to look for circuit application information. Heck, many of the circuits shows in datasheets won't lead to a product you can sell.

author: Someone
author_rank: Super Contributor
timestamp: September 25, 2023, 10:04:20 pm
content: Quote from: nctnico on September 25, 2023, 11:09:39 amStill playing your game of saying technically true and inflammatory things by omission?Parasitics are what cause resonances, not the capacitance values alone. In real world useswhen comparing the same case sizeas you would for 1n 10n 100n and 1uF the largest capacitance is almost always the optimal choice.https://www.eevblog.com/forum/projects/decoupling-caps-value/?all

author: nctnico
author_rank: Super Contributor
timestamp: September 25, 2023, 10:12:42 pm
content: I guess you never measured the effect of having several capacitors with different values (same case size) in parallel using a network analyser. I have but the thread you are referring to shows no measurement data at all. Just a lot of guess work.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 25, 2023, 10:14:15 pm
content: Just compare the ESR and ESL of 1uF, 100nF, 10nF, 1nF caps in the same package.Now if one puts a 1uF cap in say 0402 and a 1nF cap in 0201 or 01005 in parallel, you will (marginally) improve the frequency response at very high frequencies.But for small ceramic caps it's more about the package itself than the capacitance, so it's more about putting a smaller package cap in parallel rather than the capacitance itself (just that you have less chance of finding a larger capacitance in a smaller package.)

author: Someone
author_rank: Super Contributor
timestamp: September 25, 2023, 11:45:48 pm
content: Quote from: nctnico on September 25, 2023, 10:12:42 pmWell done throwing shade rather than any support of your position....I have measured PDN impedance with a range of instruments, including VNAs. But they aren't nessecary for the scalar impedance as a recent example shows:https://jmw.name/projects/exploring-pdns/Neatly answering the OPs question directly.Adding disparate capacitance values in parallel (of the same case size) is usually a bad idea, tiny gains at resonant frequencies being offset by loss at anti-resonances. Having run optimisation on capacitance selection and placement the general solution is: start with the smallest case size practical adding in a bunch of those at the largest economic capacitance until the highest frequency constraint is met, then add some much larger capacitance size+value (100x-1000x step) until that cant practically improve the result. I'm yet to see a real application where that worked less well or was more expensive than the finely distributed values approach.These sorts of "rules" need to pointed out for the overly simplified crap they are, parroted and argued about without actually mentioning the how's/why's/limitations.

author: westfw
author_rank: Super Contributor
timestamp: September 26, 2023, 12:28:56 am
content: QuotePresumably there is a hard limit imposed by physics if the clock period of the device gets significantly close to the speed-of-light-in-copper delay of current from the capacitor. But that's pretty far away (I get 1cm should be OK for up to about ~20GHz)! Of course RLC issues would make the distance shorter.

author: SL4P
author_rank: Super Contributor
timestamp: September 26, 2023, 12:51:54 am
content: My personal rule of thumb is around 10mm from the pin.

author: NaDobraNich
author_rank: Regular Contributor
timestamp: September 26, 2023, 05:51:48 am
content: Quote from: SL4P on September 26, 2023, 12:51:54 amIt seems ST would agree with you.Some of their reference designs have an LCD opposite of the BGA so they use single side components, and in that case all of their caps are ~10mm, usually just fortifying the ground plane all around the chip. Then the chip ties into the planes as well. I’ll still try and beat that, but now I know that 4-6mm isn’t going to kill me.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 26, 2023, 06:49:19 am
content: Quote from: westfw on September 26, 2023, 12:28:56 amThe RLC issues including the inherent capacitance, inductance, and resistance of the PCB traces themselves, and even in the bond wires inside the ICs.So yeah, it is modelable and theoretically computable; but no software package or mathematical rules of thumb or even theoretical models exist, for one to predict the exact capacitances and maximum distances one needs for the circuit to work –– except via practical experimentation.Perhaps I should have writtenno practical way, but I am not aware of any theoretical framework for determining such limits either: even if it is theoretically possible to compute such a limit, it would be extremely complex and require much more information than normally available to circuit designers, and end up being much more work than experimenting with the said ICs in practice to find out their typical bypass capacitor needs and distance limits.This is one field where practical experimentation rules. But it is not just about finding the minimum sufficient limit, but also about taking into consideration the aging of the capacitors, and the bias voltage affecting the effective capacitance wrt. noise or signal on top of the DC bias. Rules of thumb like "double the minimum" are common, as are all sorts of weird beliefs based on specific special corner cases, so one will just have to wade through the bypass capacitorfudmud being slung everywhere, and find the stable ground underneath for yourself.Remember this about those who claim to be an authority: At one point, doctors and surgeons refused to wash their hands, because they obviously were doing good work, and the idea of them conveying a disease via their hands was simply completely unacceptable.

author: nctnico
author_rank: Super Contributor
timestamp: September 26, 2023, 07:27:55 am
content: Quote from: Someone on September 25, 2023, 11:45:48 pmThis link just proves my point: if you parallel capacitors of different values, you'll get a low impedance over a wider frequency range.But there are several omissions by the author of that web page (trying to use the parallel plate formula to calculate capacitance from a board without taking fringe effects into account and the sub-optimal board layout used for the measurement are clear signs) so take the conclusions with a pinch of salt.

author: tszaboo
author_rank: Super Contributor
timestamp: September 26, 2023, 10:27:57 am
content: Quote from: westfw on September 26, 2023, 12:28:56 amBut usually the caps are not there to filter the clock frequency. In fact, for a logic chip, the clock frequency doesn't matter much, it's the slew rate that matters. Sure you will get a little noise due to the internal switching but most of the noise is coming from the pins switching.All: TBH I don't like these anecdotes on engineering forums outside the beginners section. Have you looked at your power delivery network with any measurement tool? Have you simulated it? Have you recorded eye diagrams? And have you sent your device through EMC or RED certification? Those measure up to 70GHz in the new RED.Something working is very different from something properly designed.Quote from: SiliconWizard on September 25, 2023, 10:14:15 pmYes, this absolutely. I've been stuck with 0402 for one reason or another for a while now, and it's really a struggle to make good layout. On my last layout I had to place the bypassing up to 1.5mm from the pins of a micro, because everything is in the way. I already don't like the idea to go to the RED certification.

author: tggzzz
author_rank: Super Contributor
timestamp: September 26, 2023, 10:43:36 am
content: Quote from: tszaboo on September 26, 2023, 10:27:57 amExactly.In pessimal designs the clock frequency will match the anti-parallel resonant peak impedance (oops!)QuoteDesign is so.... old fashioned. As long as it passes the tests (i.e. in Test Driven Development), it works - by definition. (Yes Virginia, nowadays you can inspect/test quality into a product. Not.)More sensibly testing is used toconfirmthe unit is working as designed.QuoteThere is a reason 0306 capacitors exist: lower package inductance than 0603 capacitors. I'm sureyouknew that

author: nctnico
author_rank: Super Contributor
timestamp: September 26, 2023, 12:47:39 pm
content: Quote from: Nominal Animal on September 26, 2023, 06:49:19 amYou are aware that the higher end PCB CAD packages offer DC and AC power distribution network analysis? In addition to that, chips running at high frequencies (like SoCs) have specifications in their hardware manuals that say what kind of DC resistance and AC impedance (typically specified at several frequency ranges) the chip requires on the various supply pins in order to work. There really isn't any need for magic or experimentation. You can at least measure it to verify your board design. Even a cheap NanoVNA (at least a version with a decent dynamic range) can get you quite far for doing HF PDN measurements.And simulating DC resistance using free tools isn't out of the question. Recently I came across this video:

author: uer166
author_rank: Super Contributor
timestamp: September 26, 2023, 07:33:23 pm
content: In general paralleling caps of different values but of same case size results in a higher PDN impedance over the frequency range, vs just using the maximum possible values.You don't need a VNA to realize that, just look at capacitor impedance plots in KSIM and such. Of course I have observed that via measurements as well.. Some of the above comments imply that somehow a cap stops working above self-resonance which is bs. The absolute impedance is what matters, not whether the cap "looks" like an inductor or not.Anti-resonance is a real effect as well, and you need to do actual PDN design to avoid it (i.e. it's not just throwing a couple caps of different values together). In practice that means many different cases sizes, closely spaced nominal values, and highly optimized layout. Nothing to do with OP's problem of decoupling an MCU designed for a 1inchx1inch TQFP.

author: Someone
author_rank: Super Contributor
timestamp: September 26, 2023, 10:42:02 pm
content: Quote from: nctnico on September 26, 2023, 07:27:55 amHow does it prove a parallel combination of many values is better than a parallel combination of fewer values (but the same number of caps) ? That is what I am pointing out is a vast over simplification on your part by deliberate omission, and now instead of discussing that you're going to great length to flood the discussion with any other distraction rather than try and backup your specific claim.Adding in intermediate values between the "large" and "small" capacitances, or choosing smaller capacitances than the case size economically supports is almost always producing a worse result. Sprinkling 1nF caps (as you specifically claim is good) is a complete waste of time where a 100nF or 1uF part could be placed in the same case size. Parasitic inductance from the packaging and layout are what limits the high frequency impedance, not making the capacitance smaller.If it's such a great idea to intentionally use less capacitance, why isn't there any evidence for it? Or a basic explanation of why it works? All the usual hand waving comes back to.... oh but the smaller capacitances have smaller cases.

author: dietert1
author_rank: Super Contributor
timestamp: September 27, 2023, 05:13:46 am
content: There is a trap with larger capacitors. For a given position and trace length the resonant frequency with a larger cap (let's say 10 uF instead of 100 nF) will be lower (10x). The resonant frequency isn't a parameter of the part alone but of the combination of trace (=inductor) and smd capacitor. The difference between a 0603 and a 0805 capacitor of same capacitance gets lost behind a trace of 1 cm.A quick estimate of the resonant frequency of a 10 uF capacitor behind a 1 cm track (w=0,6 mm, t=0,035 mm, h=0,4 mm: L = 3.2 nH) gave 900 KHz. With a 100 nF cap it is 9 MHz.The resonant frequency might happen to coincide with one of the clocks involved in the circuit. The resonance sucks energy but that's not the best solution. The power network may also include small resistors like 10 or 20 Ohm to reduce the resonances.Regards, Dieter

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 27, 2023, 05:44:36 am
content: Resonance to an unstated datum (e.g. voltage source??) is strictly a good thing: series resonance is the lowest impedance such a system will exhibit. It's the perfect frequency to run a clock at, it would seem. Though the impedance won't be much lower than the ESL of an "oversized" capacitor of the same dimensions, so this isn't very important.What is important, is how that capacitor behaves in a real system, connected to a bunch of other ones. The problem isn't the valleys, it's the maximum peak. You absolutelydo not wanta parallel-resonant peak at a clock frequency, harmonic, or subharmonic. And you're way the hell more likely to get such a thing, with small values whose resonances and antiresonances cluster close to such frequencies.Tim

author: dietert1
author_rank: Super Contributor
timestamp: September 27, 2023, 06:29:43 am
content: No confusion, please. If the MCU has a crystal of 8 MHz, we are talking about 100 nF or maybe 1 uF capacitors, not 10 uF. Larger caps are used for other objectives and can sit further away. On-chip operations at hundreds of MHz depend on small on-chip buffer caps.Regards, Dieter

author: uer166
author_rank: Super Contributor
timestamp: September 27, 2023, 06:50:53 am
content: Quote from: dietert1 on September 27, 2023, 05:13:46 amWhat exactly is the concern with that, and why would that be a bad thing? We're probably going in circles here..

author: dietert1
author_rank: Super Contributor
timestamp: September 27, 2023, 08:11:35 am
content: Quote from: uer166 on September 27, 2023, 06:50:53 amNobody wants resonance in the power distribution. Traces will radiate and couple to digital signals, similar to ground bounce.Regards, Dieter

author: tszaboo
author_rank: Super Contributor
timestamp: September 27, 2023, 11:20:25 am
content: Quote from: T3sl4co1l on September 27, 2023, 05:44:36 amNo, it will amplify the noise. Sure it will look good on the ESR graph, but the real effect it bad, especially if you cannot dump this noise into something, like another capacitor with different value that is somewhat lossy. Low Q factor is what's good here, why do you think there are snubbers existing. Or elcos that have maybe 100 times more ESR than a ceramic, perfect way to dissipate the noise. Oh and smd ferrite beads.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 27, 2023, 11:30:06 am
content: Quote from: tszaboo on September 27, 2023, 11:20:25 amAmplify what, where? Show a simulation.Tim

author: tszaboo
author_rank: Super Contributor
timestamp: September 27, 2023, 12:00:24 pm
content: Quote from: T3sl4co1l on September 27, 2023, 11:30:06 amhttps://www.murata.com/en-eu/products/emc/emifil/library/knowhow/basic/chapter03-p1"When a digital signal is connected to a resonant circuitFig. 3-2-6 shows the test circuit and the measurement results of the voltage waveform. 74AC00 has been used for the digital ID that works as a noise source origin. The output of this IC is connected to the series resonant circuit with the resonance frequency of 50MHz. You can see that the observed waveform indicates a strong ringing in the 10MHz digital pulse, making the pulse waveform seriously distorted. This is considered to be because only the 5th order harmonic (50MHz) has been extracted among the harmonics contained in the 10MHz signal. (A ringing frequency of 50MHz has been observed)"So no, series resonance of the PDN is not really a good thing. Series resonance of an individual capacitor could be, if it's strictly matching the "clock signal", also including the ESL of any trace going there. But maybe we are talking about the same thing. It's such a complex topic, that without writing pages of the boundary conditions for each sentence we could be proven wrong.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 27, 2023, 01:09:34 pm
content: That's an output pin; I thought we were talking about PDN?Tim

author: temperance
author_rank: Super Contributor
timestamp: September 27, 2023, 03:14:37 pm
content: QuoteThe dangerous stuff. Ferrite beads combined with high Q ceramics can create a lot of problems if not used properly.How much decoupling do you need and how close?-modern microcontrollers are extremely power efficient meaning that the 32bit wide bus capacitance is extremely low.-Most chips contain on chip capacitance. Not much of course. But the bus capacitance is extremely low.-The core of a ARM controller is fed by an LDO and the decoupling cap is placed on the outside on some controllers. For other controllers the LDO decoupling is done on the chip itself.What remains is the decoupling required for the GPIO's and the LDO input.-What are they driving, at which speed.-Slow rising inputs causing cross conduction in the input buffer circuits. (but it seems to be a problem of the past)...Where are those currents flowing? How large is the loop area?An other observation:The power supply section for microcontrollers often contains guidelines such as: place decoupling capacitors close to the supply pins. But what does "close" mean considering that the same controller is available in QFN, TQFP and BGA for example where the TQFP package has longer bond wires.

author: NorthGuy
author_rank: Super Contributor
timestamp: September 27, 2023, 03:52:50 pm
content: Quote from: tszaboo on September 26, 2023, 10:27:57 amNo. Bypassing capacitors are for the CPU. Gazillions of transistors in the CPU switch at the same time at the clock edge. Outputs of these transistors must reach their intended logic levels by the time the next clock comes. The higher the clock frequency, the faster this should happen. This requires lots of current which must come from somewhere. Hence you need bypass capacitors to supply this current. To supply the current faster, they need to be close to the chip, they must have lower ESR.The more is the frequency of the CPU, the more important bypass capacitors are. For a low frequency all-digital chip, somewhere up to 100 MHz, you can get by without any bypass capacitors. 260 MHz chip will probably won't work without bypass capacitors at all, but you don't have to stick the capacitors ridiculously close. 30-50 mm will probably still work. Of course, sticking them closer is better, but there's no reason to get paranoid about it.EMI is another story.

author: temperance
author_rank: Super Contributor
timestamp: September 27, 2023, 04:15:04 pm
content: QuoteThe average current consumption for modern 32 microcontrollers is extremely low. Something like 50...100 µA/MHz and the core is fed by an LDO who's decoupling capacitors are on chip for some controllers.The power supply decoupling for those type of controllers is purely for the GPIO's and the input of the LDO. That's why you will find reports about EMI for those controllers because you can't alter the core decoupling.QuoteIt's all about the loop area. Placing the caps closer to the chip doesn't help if the loop area (not the length) for the remaining circuit is not being dealt with.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 27, 2023, 05:51:11 pm
content: Quote from: NorthGuy on September 27, 2023, 03:52:50 pmI'm curious, how you would plan bypassing for a modern 5GHz CPU? There's a whole lot of transistors inside there, sounds like a horrible challenge.Tim

author: NorthGuy
author_rank: Super Contributor
timestamp: September 27, 2023, 05:58:52 pm
content: Quote from: temperance on September 27, 2023, 04:15:04 pmLoop area is important for EMI, and doesn't have straight relation to capacitors. The distance between the core and capacitors is important for quality of bypassing.

author: NorthGuy
author_rank: Super Contributor
timestamp: September 27, 2023, 05:59:55 pm
content: Quote from: T3sl4co1l on September 27, 2023, 05:51:11 pmLook at the picture of these. They have capacitors straight on the chip.

author: nctnico
author_rank: Super Contributor
timestamp: September 27, 2023, 06:14:23 pm
content: Quote from: NorthGuy on September 27, 2023, 05:59:55 pmYes. And this is not only that case for modern CPUs. The older Intel x86 processors also have capacitors right on the package.

author: Zero999
author_rank: Super Contributor
timestamp: September 27, 2023, 06:21:53 pm
content: Quote from: Someone on September 25, 2023, 10:04:20 pmThat hostility was uncalled for. You might have a had a beef in another thread, but should send a PM, rather than spread it elsewhere.You're right that it's generally better to use a single, large capacitor, rather than several smaller ones. It doesn't matter if it has a lower self-resonant frequency. It will have a lower impedance at higher frequencies, simply because it has a lower ESR.

author: nctnico
author_rank: Super Contributor
timestamp: September 27, 2023, 06:27:25 pm
content: Quote from: Zero999 on September 27, 2023, 06:21:53 pmIt doesn't because of the parasitic inductance. Look at an impedance/ESR versus frequency graph and you'll see the impedance/ESR doesn't keep dropping off. Instead impedance / ESR increase beyond the self resonance point.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 27, 2023, 06:33:28 pm
content: Quote from: Zero999 on September 27, 2023, 06:21:53 pmIt is called for, because nctnico is simply trolling here. Anything I post, he'll answer to with some inane twittery, even though he knows I don't read his brainfarts at all anymore. Others are getting fed up with his inanery, so some hostility is definitely warranted, until he starts posting sense instead of trolling.

author: temperance
author_rank: Super Contributor
timestamp: September 27, 2023, 07:00:02 pm
content: QuoteTrue: The distance between the core and capacitors is important for quality of bypassing. That's why, as I wrote, modern µC's with an on chip LDO have their capacitors on chip and no capacitors can be added on the outside of the µC. The loop area can't get any smaller than that. (Some µC with might require capacitors on the outside for stability. For decoupling they aren't of much value)Questionable: Loop area is important for EMI, and doesn't have straight relation to capacitors.You have a GPIO pin driving a MOSFET for example trough a small resistor. Without decoupling the transient current will be provided from whichever "nearby" source, increasing the loop area. By decoupling the driver side, the area has been reduced to the decoupling cap if the GND return is done in a proper way ie minimizing the loop area or more correct the path of the least inductance.

author: nctnico
author_rank: Super Contributor
timestamp: September 27, 2023, 07:00:59 pm
content: @Nominal Animal: Well, sorry for not posting a book on PDN and for not doing your homework. I can point you in the right direction though... but in the end: Horse.. water...But you don't have to take my word for it. Just download the IMX8MQ evaluation design from NXP. You'll see they use a range of capacitance values in the same case on the same power net. But maybe the people at NXP are complete morons just like me.

author: uer166
author_rank: Super Contributor
timestamp: September 27, 2023, 08:06:19 pm
content: Quote from: nctnico on September 27, 2023, 06:27:25 pmpack it up, lock the thread.. how many times does Tim have to repeat the wordsABSOLUTE IMPEDANCE IS WHAT THE IC RAIL SEESbefore you realize just how wrong/misleading/incorrect the above statement is, and how many new generations of engineers will it take to purge 1980's thinking.

author: nctnico
author_rank: Super Contributor
timestamp: September 27, 2023, 08:23:58 pm
content: Quote from: uer166 on September 27, 2023, 08:06:19 pmThen come up with a graph that shows the real behaviour according to you. If I hook up an SMT capacitor to a VNA, I see the impedance going up above the resonance point. And that matches the graphs when I go to the capacitor manufacturer's website. Logical, because there is an inductor in series with the capacitor which starts to dominate the impedance at some frequency (just like a piece of trace and/or a via does). Ofcourse power distribution is more than the capacitors alone but you have to start with basic part behaviour and add the circuit board behaviour to it in order to reach the required impedance.

author: tggzzz
author_rank: Super Contributor
timestamp: September 27, 2023, 08:43:48 pm
content: Quote from: nctnico on September 27, 2023, 08:23:58 pmSo what if the impedance is going up (or down for that matter)?What's important is that the impedance is low enough.

author: nctnico
author_rank: Super Contributor
timestamp: September 27, 2023, 08:59:41 pm
content: Quote from: tggzzz on September 27, 2023, 08:43:48 pmThat goes without sayingBut the way you accomplish the impedance getting low enough is the million dollar question. At some point you simply run out of room to add more 10uf capacitors around a BGA package (not to mention leaving room for traces). So what to do then? What you see in practise is that various values and/or package sizes are mixed to reach a wide enough frequency range. Some of the designs I have worked on need <7 milli-Ohm up to 20MHz and <30milli-Ohm up to 100MHz on some power nets. The chip manufacturer (NXP in this case) is very specific about mixing capacitor values in order to meet the design criteria.

author: uer166
author_rank: Super Contributor
timestamp: September 27, 2023, 09:24:13 pm
content: Quote from: nctnico on September 27, 2023, 08:59:41 pmHoly f**king shit. You started the whole thing of "So with several values in parallel using thesame package size, you get a low impedance" crap which is what everyone has been debunking, but somehow the goal posts have moved once again.Nobodyin this thread has argued even once that you could not achieve a low wideband impedance with multiple case sizes and an optimal layout. Here is the homework you are unwilling to do:Consider 3 0402 size caps: 1nF, 10nF, 100nF parallel, vs 3 100nF caps parallel. Which one gives best impedance at high frequency? I chose the following parts in KSIM since they are characterized:I have derived the parasitics and re-simulated in LTSpice with the following well matching result:And here is the comparison of 3 caps of different values and 3 caps of the largest:Which one is better? Obvious answer: below 400MHz, the 100nF x3 iswaybetter, above that, they areidentical.

author: nctnico
author_rank: Super Contributor
timestamp: September 27, 2023, 09:28:30 pm
content: Quote from: uer166 on September 27, 2023, 09:24:13 pmYou are reading selectively. I already wrote that NXP is using 3 (or even more) different values in the same package size in order to get the impedance low enough for their iMX8MQ reference design. I'm not making it up. Feel free to comment on the reference design.

author: temperance
author_rank: Super Contributor
timestamp: September 27, 2023, 09:49:23 pm
content: QuoteThe inductance for a 0603 10 nF capacitor with a resonant frequency of 50 MHz is about 1 nH. For a 0402 10 nF capacitor with a resonant frequency in the 100 MHz range the inductance is 250 nH.Ignoring PCB layout inductance, one can safely assume the capacitor series inductance to be much lower than those of bond wires found in IC's like SO, TQFP,....Bond wire inductance tables for different packages:https://www.ti.com/lit/an/snoa405a/snoa405a.pdfBGA decoupling, no bond wires: you will need VIA's to connect those capacitors. One 0.1 mm via with a height of 1 mm is typical 0.8 nH or even more and a 0201 capacitor has an inductance around 200 nH.Just to put things into perspective.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 27, 2023, 09:50:38 pm
content: Quote from: nctnico on September 27, 2023, 08:59:41 pm...You do nothing at all, of course.What more could you do, anyway?Probably the most graphic examples are those ancient, giant CPU hybrids -- IBM, and... SPARC??, among others?? -- where the power supply interconnect was multilayer PCB absolutely studded with ceramics to essentially make a loaded transmission line of extremely low impedance.And those were only, what, 100s of MHz? Very hungry, 3.3 (or even 5?) V, huge chips, butting into the limits of the relatively coarse process node they had at the time.Many of those modules had wide body and even LGA ceramic chip caps on them, too, for the same reason we put them on interposers (or even die directly) today of course. But they did it on metal-ceramic monster backplates, because PCBs couldn't possibly handle the number of signals and planes, impedances, tempco (expansion rate), etc. that these beasts demanded.The trickery doesn't end there; PDN design extends quite far on-chip, to the extent that logic itself is designed carefully so that limited populations are switching all at once, in any given region, so that the say 90% of inactive transistors that cyclecan act as bypass capacitors for the ones that are switching. Chip designers aren't dummies, obviously; in particular, they know the limitations of their systems and environments. You can make estimates for the characteristic impedance or stray inductance of wire bonding, or die attach (flip chip), the interposer, balls, etc. You will find it's not simply difficult, but outright impossible to get low supply impedances, at the PCB, much beyond 100MHz or thereabouts.You can certainly have effective bypassing higher than 100MHz -- indeed bypasses need not even be explicit components at the highest frequencies, but that's for RF amplifiers, where much higher impedances are seen (say 50 ohm ballpark), and the inductance of the return paths is integrated as part of the resonant circuit design. No such advantage is had for extremely low impedance CPU supplies, which also need it low across the board, and the only way they can do that is with a staged bypass scheme, from PSU to chip-adjacent to onboard to within-die.What I don't know, is whether embedded stuff generally does this, onboard (interposer, stacked-die, or sufficient as bare die), or how close it must be placed on PCB. Datasheetsnevergive impedance and frequency requirements, so we are all in the dark here, bickering about long shadows cast upon our walls.That still leaves "best practice", which aims for low and stable impedance, which is easiest done with the larger values, small chips, and avoiding certain parallel combinations, staggered sizes, etc. as discussed in part above. But don't be a damned fool about it. Plenty of newbies throw together boards with poor bypassing, or even lacking planes entirely, and manage to do work with them. They might be an EMC disaster, but only the worst are so bad they're entirely nonfunctional.Personally, I suspect that, by combination of onboard capacitance and modest power consumption, most embedded MCUs (of more than modest frequency i.e. >= 100MHz; say, STM32F4 to F7 and similar) aren't very demanding, whether by way of a relatively high impedance limit (imagine, bypassing an MCU with a couple high-ESR electrolytics instead... but, that should indeed be possible with some parts!), or a relatively low frequency limit (say, onboard handles >50MHz so you only have to worry up til then). The noise and jitter requirements are also rather banal, except for certain specific peripherals, which likely have isolated / separately filtered IO or VCCA domains anyway (ADC most obviously, but also Ethernet, USB, core clock (PLL), etc. may apply).Even the most trivial specs, manufacturers never provide -- consider the capacitance of VDD to GND alone! This is so easily measured, you can do it yourself; I'd be willing to bet you'll find many large-ish MCUs in the ~uF range. Nowthatwould be some interesting (and useful) context for PDN design, wouldn't it?Related note: microSD cards are permitted up to 8.2uF onboard capacitance, good to know for hot plugging purposes. Where's that capacitance coming from? Integrated chip caps? Or the chip itself? Who knows...Tim

author: temperance
author_rank: Super Contributor
timestamp: September 27, 2023, 09:59:23 pm
content: QuoteQuoteSee my earlier post on typical modern 32Bit controllers. They have an on board LDO and decoupling is done on chip. Some older chips require a capacitor on the outside for stability while some don't require an external capacitor.The external decoupling is more required for:-The input of the LDO. (but not much information is given very often.)-The transient current (di/dt) required by what has been connected to the GPIO pins.QuoteOnly the LDO is messing up your measurement for most 32bit micros.

author: nctnico
author_rank: Super Contributor
timestamp: September 27, 2023, 10:10:33 pm
content: Quote from: T3sl4co1l on September 27, 2023, 09:50:38 pmFor microcontrollers such info is typically missing in the datasheet but you might be able to find an appnote (unless putting a 100nf capacitor withing a few mm of the power pin will just work). Whatever could be perceived as a hindrance to design a component in, gets burried in an application note. For SoCs the power impedance requirements are very well specified; but this info is in the hardware manual or an application note. BTW: If you want to see an interesting appnote on power supply routing & decoupling, get the hardware manual for the ESP32-S3They use the trace impedance to seperate the various analog and digital power supplies.

author: Someone
author_rank: Super Contributor
timestamp: September 27, 2023, 10:19:08 pm
content: Quote from: Zero999 on September 27, 2023, 06:21:53 pmI'm specifically not saying that, and framed the situation of a given number of (possibly specifically physically sized) capacitances. Through all this noise the important point keeps getting pushed away.If you had a choice of capacitance in a given footprint, almost universally the larger capacitance produces the better result.Which is far more practical than the "spread out capacitance values to have resonances everywhere" that keeps getting parroted. Trace and case parasitics are the dominant limitation to high frequency decoupling, which is what the OP asked about. So I'm trying to cut through all the rubbish here and point people to contemporary and accurate content on that. But a certain member has taken it upon themselves to attack anyone else's discussion on the matter, walking the goalposts way off into troll land.

author: temperance
author_rank: Super Contributor
timestamp: September 27, 2023, 10:33:40 pm
content: QuoteAn other important point missing is this discussion is that the PCB layout becomes very critical of you want to keep the PDN impedance below that of a small MLCC. It's better to take a very close look at the PCB layout than looking at infinitum into the impedance offered by some MLCC caps. After all, a BGA has only a limited number of GND and VCC connections for which you need a bunch of VIA's measuring about 1 nH each.

author: nctnico
author_rank: Super Contributor
timestamp: September 28, 2023, 07:23:58 am
content: Quote from: temperance on September 27, 2023, 10:33:40 pmIndeed. Which is why I keep bringing up the fact that designers who must be using board level PDN simulation tools + board level verification (measurements) are mixing values in the same package size. I can't believe they do this just for fun. In power distribution the PCB itself is a component you can't leave out of the analysis (just like RF design).

author: Simon
author_rank: Unknown
timestamp: September 28, 2023, 09:08:34 am
content: Quote from: NaDobraNich on September 24, 2023, 04:22:02 amI think it's price mostly Capacitance is physical, you can't wish it into a smaller space so making tiny silicon and then asking for a ton of bypass capacitance will not magically make it happen. I have never worked on anything with so many caps. What I tend to use is a micro controller where a 100nF is recommended on each power pin, on a 64VQFN this is a challenge as a analogue supply and digital supply pins are next to each other. Obviously on 0.5mm pitch you won't get the cap sideways to get positive rail and GND close to the chip. So I end up pointing the positive to the chip and rely on the ground plane to not have much inductance. They then recommend something ridiculous like 10µF on each rail, I don't even try to get these close, it's impossible with a 1206-1812 part size. I think these are desirable mainly as bulk capacitance on steroids ESR wise and are more for arse covering purposes, so I don't fuss too much about them. Generally they go behind one of the smaller ones on the same rail.

author: temperance
author_rank: Super Contributor
timestamp: September 28, 2023, 10:30:04 am
content: QuoteThe idea for the kind of PDN you are thinking about is to keep the impedance as constant as possible because any peak or valley is responsible for noise on the PDN network even if those peaks are below the required PDN impedance.A tough subject on its own for which you will need pretty expensive software and equipment to verify final product performance. Did NXP go so far to develop a dev board? Maybe you can ask them or connect a network analyzer to the dev board if you've got one and post the result here.Is it a good idea to follow the dev board schematic? No if the PDN on your own board is different.

author: nctnico
author_rank: Super Contributor
timestamp: September 28, 2023, 09:23:59 pm
content: Quote from: temperance on September 28, 2023, 10:30:04 amI think they went this far. Typically these evaluation boards from serious manufacturers (like NXP, NVidia, TI) are used as golden standards. If you ask support to help fixing a problem using your own design, their first reply is to try and replicate the problem on their reference design. Getting access to some form of board level AC power integrity simulation for my own designs is high on my list though.QuoteI have an IMX8MQ eval board so I hooked it up to my LF network analyser for a (crude) S21 shunt measurement for the memory supply (which is amongst the more critical supplies):This is from a IMX8-nano design I designed myself:In both cases I tried to pick injections & pickup points at a bulk decoupling site that has many vias to both ground and the power plane with the injection point close to the power supply. Also note that the eval board uses 0201 sized parts where my own design uses 0402 parts. When converting the S21 attenuation to impedance, both designs are well within specs.QuoteYes and no. In the end the power connections on the package and the layout guidelines (like placing the DDR memory within a few mm of the SoC, layer use, stackup, etc) limit the possible routing strategies (assuming a capable PCB designer). Or put differently: if you follow the layout guidelines where it comes to component placement, layer use and stackup you are not likely to screw things up. OTOH, if you just get creative with the schematic, you are on your own.