Need help from the old farts! :D How were dense DIP boards routed way back then? - Page 1
Forum section: electronics / projects

author: MarkS
author_rank: Unknown
timestamp: March 26, 2023, 02:21:19 pm
content: I'm working on several projects based on the MC68000. To make my life easier (HA!) I am separating everything into multiple development boards. To keep with the retro look and feel, I'm using as close to 100% DIP packages as possible.Right now I'm working on the processor board. I have all of the buses broken out to female headers via 74LVC245's. No matter how I orient the processor or transceivers, the ratsnest is just a total twisted mess. And I'm giving quite a bit of space between components! Some of the truly densely populated boards of old have chips so close you'd think the pins would short out! I've tried rotating and moving the transceivers and CPU, but all that does is move the twisted mess.How do I tackle this? I'm going 4 layers, just because of this issue, but in reality, 2 layers should suffice. I can reorder the nets so that they line up better with the transceivers coming from the CPU, only that twists them between the transceivers and headers. I could make the bus out of order at the headers, but that complicates development and ensures nasty errors when wiring between development boards.How was this done efficiently back in the day?

author: mariush
author_rank: Super Contributor
timestamp: March 26, 2023, 02:33:53 pm
content: Seems simple to me : U5 to U11 have to be rotated 90 degrees. Align them as close as possible to the top headers so you more or less have traces go directly from DIP chips to the headers.You can route some traces UNDER (inside the footprint of ) the microprocessor and some traces can go on the bottom layer of the pcb. Especially where a bunch of traces have to be flipped/reversed ... use vias to route them to other layer and then you no longer have to reverse them.If you're reluctant to use VIAs you can use 0 ohm resistors / jumper links to jump over traces where needed.If the order of the headers is not critical, maybe they can be rearranged to work better, for example CONTROL BUS and the one to the left and U5 and U8 may be better all the way to the right.

author: jonpaul
author_rank: Super Contributor
timestamp: March 26, 2023, 02:39:50 pm
content: narrow down your pads, route traces in between two padsj

author: MarkS
author_rank: Unknown
timestamp: March 26, 2023, 03:20:42 pm
content: Thank you! That got me in the right direction!

author: Terry Bites
author_rank: Super Contributor
timestamp: March 26, 2023, 03:43:35 pm
content: Manual routing is efficent if you have the skills!Mariush is right.Placement is everything. Rotate the 245sMake the pads 64 thou or less. You'll get a 16 thou track through the pin spacing with ease.Mil to you.68000 thats old fart territory alright!

author: MarkS
author_rank: Unknown
timestamp: March 26, 2023, 04:36:00 pm
content: Quote from: Terry Bites on March 26, 2023, 03:43:35 pmThe problem is that KiCAD has very few footprint options. I did reduce it to the footprint with the smallest available pads, but if I wanted the pads smaller, I'd have to make my own footprints and I really don't want to do that. I'm using KiCAD's default track width of 0.25mm, which very easily fits though even the larger footprint's pads.68000 is old fart territory, but I'm 46, so I'm not too far off and my first computer was a Mac 512KE. I learned to program on the 680xx line of processors, including 68K assembly. It holds a special place in my heart.

author: MarkS
author_rank: Unknown
timestamp: March 26, 2023, 04:40:55 pm
content: Wait a minute!I meant to rotate the chips.Back to the drawing board... Fortunately I didn't get far.

author: m k
author_rank: Super Contributor
timestamp: March 26, 2023, 05:21:05 pm
content: Back in the day simple cost reduced two layer MCU modules were already fine line, two tracks between pads.There pads are quite small, maybe a chat with the maker is required.Obviously width is more critical with semi unknown outside connections.

author: MarkS
author_rank: Unknown
timestamp: March 26, 2023, 05:23:37 pm
content: MUCH better!

author: pcprogrammer
author_rank: Super Contributor
timestamp: March 26, 2023, 05:36:15 pm
content: With a bit of practice you can reroute and get rid of the five vias near pin 1 of the cpu. And like m k wrote it is possible to route two tracks between the pads when you make the track width and the pads smaller.Since you are doing 4 layer you can forget about the power and ground which makes things much easier.I did this kind of stuff 30 years ago with PLCC84 and DIP sockets (SAB80537 MCU and XC3042 FPGA) with Protel PCB. Would think that it should be easy to do now with current production processes.Edit: Added some pictures as proof

author: james_s
author_rank: Super Contributor
timestamp: March 26, 2023, 05:48:57 pm
content: It was all done manually back in the day, drafted by hand without any CAD tools. I don't recall seeing many 4 layer boards back in the DIP era, just PC motherboards starting around the early 80s. Stuff like arcade games were all just double sided boards and errors corrected by bodge wires were common. I have one board where it's obvious a small trace was meant to go on the other side because it crosses over another trace and they had to cut it and replace it with a wire.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: March 26, 2023, 06:15:14 pm
content: General rule for DIP boards - have all chips facing the same way, and use one layer for horizontal routing, and another for vertical. Don't worry about how many vias this takes. Only break the horizontal/vertical rule at the edges where there is no chance of blocking.That way you have multiple options for any route, based on minimising congestion.If things get tight, you can reduce the pad size on the top layer without affecting solderability, so having the top layer be routed perpendicular to the IC orientation is probably best for density - you may be able to do 2 traces between each pad.4-layer makes this a lot easier as all your power/grounds disappear from the picture.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: March 26, 2023, 06:17:29 pm
content: Where you have things like buffers, remember all gates are equivalent, so you may be able to seriously simplfy by juggling these around - nailing down the gates used at the schematic stage can constrain you too much. Ditto SRAMs, where any address or data line can be swapped with another.

author: mariush
author_rank: Super Contributor
timestamp: March 26, 2023, 06:25:21 pm
content: Quote from: MarkS on March 26, 2023, 05:23:37 pmUnless you have to squeeze them so much vertically, I think you could do better by having U7 and U12 shifted to the left, so that U7's first two pins would be inline with U8.Something like this (excuse the paint skills):edit : unless you make it 4 layers, also be careful to leave some spacing to route power to the chips. I'm thinking you'll probably want to have the bottom as much ground fill as possible and break that fill just to have small breaks for traces that have to jump over traces, or traces that have to go short lengths. \Another practice in the old days was for one layer to have traces routed mostly vertically, and the other layer to have traces mostly horizontal. Dave can probably explain well why this was done.

author: tooki
author_rank: Super Contributor
timestamp: March 26, 2023, 07:23:53 pm
content: Quote from: MarkS on March 26, 2023, 04:36:00 pmI strongly suggest embracing DIY footprint (and schematic symbol) design as early as possible, because the moment where you need some footprint that isn’t available WILL come sooner than you think! But it also gives you the flexibility to do what you need, like using oval pads for DIPs instead of the abominably difficult-to-hand-solder-nicely circular pads with nearly no pad surface.

author: jonpaul
author_rank: Super Contributor
timestamp: March 26, 2023, 07:35:49 pm
content: We used Bishop red/blue tapes on mylar size b,c or d with registration pins.On a 2x or 4x scale, one or even two traces could pass between adjacent DIP 0.100" pins.My last PCD CAD was OrCad and Altium.Bon ChanceJon ( NOT AN OLD FART)

author: MarkS
author_rank: Unknown
timestamp: March 26, 2023, 07:36:12 pm
content: Quote from: tooki on March 26, 2023, 07:23:53 pmI do my own quite frequently. I just don't like doing it if it can be avoided.

author: MarkS
author_rank: Unknown
timestamp: March 26, 2023, 07:58:24 pm
content: Quote from: jonpaul on March 26, 2023, 07:35:49 pmIt's OK to admit it!

author: Benta
author_rank: Super Contributor
timestamp: March 26, 2023, 08:58:21 pm
content: Old Fart reporting for service!!Frankly, we started with paper and pencil, sketching possible placement for best layout.You don't seem to appreciate the fantastic leap forward the "rat's nest" functionality in CAD was!Rotating and dragging parts until the chaos begins to straighten itself out is a blessing. See that you use it properly! (which your original post did NOT show).Be glad to have it, we didn't.

author: MarkS
author_rank: Unknown
timestamp: March 26, 2023, 10:29:44 pm
content: Thanks for all the help! It's coming together!Quote from: Benta on March 26, 2023, 08:58:21 pmI agree! That's why I was stumped and why I asked. I knew I was doing something wrong and that it couldn't possibly be that hard, and I was and it wasn't.Quote from: Benta on March 26, 2023, 08:58:21 pmOh, I am! I cannot even imagine what you guys went through!

author: DrGeoff
author_rank: Frequent Contributor
timestamp: March 26, 2023, 10:45:55 pm
content: I did many 68K boards back in the 1980's. All on 2-layer hand routed (some with red/blue tape) boards.First thing to do is to orient your chips on a grid and located correctly to make routing easier.Second thing to do is route the power grid. Two traces down the middle of each chip row with crosses at each end and, if a long board, in the middle too.Add a decoupling cap to each chip across these power rails.Now start routing the signals. 10 thou track and spacing was usually used for most signals on digital boards.

author: profdc9
author_rank: Frequent Contributor
timestamp: March 26, 2023, 11:28:58 pm
content: I have a Z80 single board computer with many 40 pin DIP ICs on it close together.You can see how I routed things.http://www.github.com/profdc9/Z80SBCBasically, use 0.35 mm wide traces or less, place chips so that particular bus lines are near the same bus lines of other chips, cluster traces so that you can jump them with vias over other traces more easily.

author: shakalnokturn
author_rank: Super Contributor
timestamp: March 27, 2023, 12:28:34 am
content: On densely populated power-hungry fast TTL boards you'd sometimes find vertically mounted power strips running in-between rows of IC's (can't remember the exact name nor find an example online).They had the advantage of taking some of the heavier tracks off the board to free space for the logic routing, I'm not certain but seem to remember some dual power rails doubled-up as decoupling capacitors.

author: MarkS
author_rank: Unknown
timestamp: March 27, 2023, 12:31:33 am
content: Quote from: profdc9 on March 26, 2023, 11:28:58 pmThat's how I plan on routing the board once I'm done with prototyping. The board I'm designing here is just the processor so that I can connect it to memory and IO boards and breadboards for prototyping. It will be much easier when I am not routing to transceivers and headers.Anyway, I am about 90% done! Thanks for all the help!

author: MarkS
author_rank: Unknown
timestamp: March 27, 2023, 12:33:06 am
content: Quote from: shakalnokturn on March 27, 2023, 12:28:34 amSo, basically heavy gauge bare copper wire? Hmm.... Not a bad idea.

author: DrGeoff
author_rank: Frequent Contributor
timestamp: March 27, 2023, 12:42:07 am
content: Quote from: MarkS on March 27, 2023, 12:33:06 amThey were kind of busbars with pins, but you had to make sure your grid aligned with the spacing of the pins. They were used as grid row crosses (perpendicular to the column traces).For 68K boards I vaguely remember we used 70 thou traces for the pair of column rails through the middle of all the chips in the column, which tapped of + and GND as it passed by.Since these were done by hand there were no copper pours.

author: jonpaul
author_rank: Super Contributor
timestamp: March 27, 2023, 12:45:27 am
content: the power bus strips were like an SIP upright flat strip but actually a ceramic bypass capacitor, and power strip in one, with 5V and GRD pins paired.Thus PCB is simpler and noise on the Vcc bus greatly reduced.Jon

author: Nusa
author_rank: Super Contributor
timestamp: March 27, 2023, 01:43:39 am
content: Quote from: james_s on March 26, 2023, 05:48:57 pmDepending on how far back in the day you're talking about. I know I first used AutoCAD back in 1987, which had been around for a few years by then. I never did hand layout myself, but I've watched it being done. Some of those boards are beautiful in the artistic sense, since designers could freely use curves instead of straight lines or angled corners. I did do some wire wrap stuff before that, which of course skips the layout process entirely. I still have the tools, and it's great for the occasional one-off projects even today.

author: james_s
author_rank: Super Contributor
timestamp: March 27, 2023, 02:17:13 am
content: Quote from: Nusa on March 27, 2023, 01:43:39 amI'm thinking of arcade game boards, so early 70s to early 80s primarily. I've also xrayed and reverse engineered a handful of potted HeNe laser power supplies that were obviously hand routed, they tend to have nice swoopy curved traces that are hard to do in modern CAD.Once the PC revolution took off in the mid 80s I think CAD took over pretty quickly. PCB layout was one of the obvious tasks that computers could make easier and less error prone.

author: MarkS
author_rank: Unknown
timestamp: March 27, 2023, 03:46:42 am
content: Fin!

author: mariush
author_rank: Super Contributor
timestamp: March 27, 2023, 08:46:26 am
content: It can still be improved ... like for example U10 jumps to me like kinda bad.A14-A16 traces could be routed to the left of U11 and C13 so you don't route the traces through pins. Same deal with FC0 and FC1 and FC2Traces between U12 and U11 could be routed directly if you use vias (on the short distance between the chips)I like seeing at least a few mm of trace going directly vertical from a pin, and then go 45 degrees to left or right, but that's just personal preference, not something that would make the circuit better in any way.U9 traces look ugly to me.I'd route CLK, RESET, HALT traces around the decoupling capacitorCheck traces and vias on traces going to u8 looks like the vias thinned some traces something's wonky in the picturelooks like you didn't put much thought on u3, u2, u4 ...U3 may be routed easier if you rotate it 180 degrees, probably also U4 ... u2 is probably fine there, but the resistorsmaybe x1 should be closer to the micro pin, maybe between u4 and u2 .. don't see a reason why u4 would need to be so closemaybe shift power on reset bit where the x1 is, or maybe to the left of that if you move x1 closer to the mculots of empty space to the right of the buttons, could you possibly optimize something by using that space, making it use less vias on u2,u3,u4 by spreading those chips a bit ?You have the horizontal size imposed by the headers, so why not take advantage of that spaceIf you want to, look into configuring minimum spacing between tracing and then pushing traces so they're closer together, at same distance between them, for nicer visual look. It can also help with minimizing the length of trace that jumps to other layer and comes back.If this is gonna be open source / free, why not post the project so others could play around with the layout if they feel like it?

author: Wolfram
author_rank: Frequent Contributor
timestamp: March 27, 2023, 09:23:50 am
content: No GND on any of the signal connectors? Logic signals over flat flex cables will benefit from using as many pins for GND as possible, close to each signal wire. I see every signal is wired to two pins, making every other pin GND instead would offer a lot better signal integrity.

author: MarkS
author_rank: Unknown
timestamp: March 27, 2023, 02:55:33 pm
content: Quote from: mariush on March 27, 2023, 08:46:26 amI know it's ugly, but I was more intent on functionality than aesthetic, but the Wolfram popped that bubble!Quote from: mariush on March 27, 2023, 08:46:26 amWill do! However, do know that this is just the prototyping phase of a bigger project.Quote from: Wolfram on March 27, 2023, 09:23:50 amI even thought about that while routing. *SIGH!*

author: mariush
author_rank: Super Contributor
timestamp: March 27, 2023, 04:15:37 pm
content: Another very minor observation... and I don't even know if it's possible, maybe it MUST be this way.If this is gonna be some kit you're gonna sell, or provide BOM for people to buy, you may want to make it easier for people to buy ready made ribbon cables, or to use connectors that are the most common size, therefore cheaper.For example, 2x5 would be super common because it's USB 2.0 and lots of other things in computers. 2x10 would be another very common size, as it's USB 3.0 headers on motherboards.You have CONTROL and DATA with 32 pins (2x16) each, but you have the ADDRESS with 46 pin (2 x 23)For example, you could standardize on 2x10 headers, and then you'd have CONTROL and DATA made out of 2 20 pin headers, and the ADDRESS could be made out of 3 20 pin headers (or 2 20 pin + 1 10 pin)This way your kit would have 6-7 20 pin ribbon cables and 6/8/10 pin cable.2x10 would work, as I said, power of usb headers.... 20 pin headers with walls and keying are available in huge volumes and cheap, for example 260k pieces in stock :https://www.digikey.com/en/products/detail/on-shore-technology-inc/302-S201/2794235or even cheaper, 15 euro cents each if you get a bag of 160:https://www.tme.eu/ro/en/details/zl231-20pg/idc-connectors/connfly/ds1013-20ssib1-b-0/

author: inse
author_rank: Super Contributor
timestamp: March 27, 2023, 04:30:40 pm
content: Swapping data and address lines will make debugging a real fun job

author: MarkS
author_rank: Unknown
timestamp: March 27, 2023, 04:35:49 pm
content: This isn't a kit. Just a hobby project. I have no plans to sell the final design or any part of it. The headers only exist here to connect to the memory and IO prototyping boards. The final design will look nothing like this.

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: March 27, 2023, 04:42:40 pm
content: Quote from: DrGeoff on March 27, 2023, 12:42:07 amWe used to do manual boards with copper pours, but they were done by the process camera operator. He'd do some trick with an extra negative by changing the scale and creating a margin around traces. A bit of hand clean-up and Bob's your uncle.

author: srb1954
author_rank: Super Contributor
timestamp: March 27, 2023, 08:14:05 pm
content: Quote from: MarkS on March 27, 2023, 03:46:42 amNot quite.Any reasonably capable 68K system normally requires 2 additional bits of control circuitry:A ROM remapping circuit to shift the ROM down to the bottom of memory when fetching the initial power-up reset vectors. After power up reset is complete the bottom addresses in memory are usually assigned to back RAM so that the interrupt vectors can easily be reassigned.A bus time-out clock so that the 68K doesn't hang forever if it doesn't receive a DTACK from a peripheral or memory controller.

author: davep238
author_rank: Contributor
timestamp: March 27, 2023, 08:29:43 pm
content: Re: post #29The schematic shows that your Reset and Halt switch circuits have a redundant resistor.You also have a problem with the spacing of your headers. I took a photo* of a mock-up that shows the issue. Staggering the headers buys you a small amount of space. Regarding connector grounds, I suggest making the even numbered pins ground, and keeping the odd numbered pins as signals.The output of U3F (an open-collector gate) doesn't appear to have a pull-up resistor.* I don't know why the photo shows up in landscape format when it appears in portrait format on my PC.

author: MarkS
author_rank: Unknown
timestamp: March 27, 2023, 09:21:07 pm
content: Quote from: srb1954 onTodayat 14:14:05I think you (an several others...) are missing the point of this particular circuit. This isNOTTHEproject. This is nothing more than a solderless breadboard prototype placed on PCB. All this does is break out the CPU's buses to external circuitry for testing, prototyping and experimentation. I'm doing this to reduce the likelihood of ringing and other instabilities that can come from using solderless breadboards. The memory subsystem and IO have yet to be designed and will connect to the headers here via probably breadboard jumpers for testing purposes only. The memory map has yet to even been thought of at this point.Once I'm happy with the total design of the entire system, I'll redesign the board to combine everything, sans headers and transceivers, into a single PCB. I am nowhere near that point.Quote from: davep238 onTodayat 14:29:43Totally missed that!Quote from: davep238 onTodayat 14:29:43This will have to be redesigned, yes. However, I will not be using ribbon cables. I'm going to connect jumpers between the memory subsystem, IO and CPU, hence the double headers. There's no point in supplying a full 23-bit address bus to an IO circuit that may only require a half dozen address lines, for instance.Quote from: davep238 onTodayat 14:29:43Thank you!

author: Benta
author_rank: Super Contributor
timestamp: March 27, 2023, 09:54:23 pm
content: Yeah, lots of stuff missing for a complete 68k system: memory decode, bus control etc. It's half a design.I'd like to compliment you especially on one thing: you're working completely consequently with signal names vs. assertion levels.Some people do "double negations" by using both bar and bubble notation at the same time.You don't, bravo!

author: MarkS
author_rank: Unknown
timestamp: March 27, 2023, 10:11:23 pm
content: Quote from: Benta on March 27, 2023, 09:54:23 pmWhich, again, is the point here.Quote from: Benta on March 27, 2023, 09:54:23 pmThank you! This way feels "natural". Besides, the CPU is the central aspect of any computer design. The 68K uses bar notation, so the design uses bar notation. Why overly complicate things?

author: Benta
author_rank: Super Contributor
timestamp: March 27, 2023, 10:26:28 pm
content: Quote from: MarkS on March 27, 2023, 10:11:23 pmNo, your design does NOT show bar notation (perhaps "overbar" is the right term), which is why I praised you.But perhaps the resolution of the image is cheating me?EDIT: the credit actually goes to the KiCAD library designer.

author: DavidAlfa
author_rank: Super Contributor
timestamp: March 27, 2023, 10:34:20 pm
content: Now add via stitching everywhere for best gnd plane.

author: davep238
author_rank: Contributor
timestamp: March 28, 2023, 01:25:26 am
content: I'm glad that I helped, Mark.-Dave Pollum

author: MarkS
author_rank: Unknown
timestamp: March 28, 2023, 02:34:02 am
content: Quote from: davep238 on March 27, 2023, 08:29:43 pmI knew that didn't make sense as I hadn't planned for that. It should have been a 74LS04. I was looking for a 74-series inverter on Digi-Key and picked the wrong one. Thanks for pointing out the mistake. You saved me a ton of headaches later!

author: srb1954
author_rank: Super Contributor
timestamp: March 28, 2023, 06:23:20 am
content: Quote from: MarkS on March 27, 2023, 09:21:07 pmNo, I think you are missing the point.Since this ancillary circuitry is required in most 68K applications it makes more sense that you incorporate it into this module rather than having to replicate it anew on your breadboard every time you want to try out a new circuit configuration. With the error-prone nature of wiring up circuits on a breadboard it is good practice to minimise the extent of new circuitry that has to be debugged each time. Debugging 68K systems is hard enough without adding extra complications and workload.With the bus time-out circuit or watch dog circuit this is typically quite tightly integrated with the operation of the power-on reset circuit so it may not even be possible to properly implement these ancillary circuits externally given the limited access you have brought out from the internals of the reset circuits.These seems little point in having a manual HALT switch as currently implemented it is largely useless in controlling a program halt with any precision. However, if you add some additional circuitry you can make into a a single step control which could be quite useful for debugging a errant program or tricky interrupt service routines.There also seems little point bringing out the bus arbitration to the external headers without also implementing some logic to control the data, address bus and control signal buffers. As it stands there is no way that another bus master can take control of the bus for DMA or other purposes. If you never intend implementing multiple bus masters then don't bother bringing the bus arbitration signals to the headers and just tie the BR line inactive.Quite apart from the bus mastering issue you should also review the use of 74LVC245 buffers in this application. For most manufacturers these are only specified for supply voltages up to 3.6V. With a 5V supply they will survive and maybe even operate correctly but you get no guarantee of logic levels or timing from the manufacturer. This may cause an issue with incompatible logic levels between the 68000 and the bus buffer chip. The 68000 is specified for a logic high of only 2.4V on most outputs and this may not be high enough to guarantee a good logic high into a 74LVC245 operated on 5V. If you are only going to design 5V systems it would be better to use a buffer specified for operation on 5V, preferably with TTL thresholds to match the 68000. However, if you change the processor to a 68HC000 (which should probably have specified right from the start) then you could also use ordinary CMOS threshold buffer chips.A few other minor comments:OC gates U3A,U3B and U3F haven't got any pull-ups on their O/Ps.Even with a pull-up on the O/P of U3F it may be too slow transitioning from low to high and turning the data bus buffers around. You need to carefully check the timing of this signal as it could give rise to the possibility of data bus conflicts with external circuitry.Pull-up R11 is too low in value to guarantee a proper logic low level when the processor drives out on the HALT pin. It should be increased to not less than 3k3.Since you don't appear to be using the 6800 peripheral compatiblity bus cycle mode the control line VPA should be permanently tied to its inactive state.All other control inputs BERR, BR, BGACK, DTACK and IPL0-2 should have pull-up resistors holding these signals in their inactive state. This saves having to add pull-up resistors to your breadboard every time you aren't explicitly connecting these signals.Just a few comments from an old fart who has been designing 68K systems from the early 1980s.

author: MarkS
author_rank: Unknown
timestamp: March 28, 2023, 09:34:01 pm
content: Quote from: srb1954 on March 28, 2023, 06:23:20 amI hate to admit it, but you're correct. Not only for the reasons given, but because it's clear I'm making this harder on myself that I need to.WHYam I doing it this way? I can work out the memory map easily enough on paper and memory decoding logic is not difficult. What purpose does it serve to make an unwieldy, complicated and unnecessary protoboard when I can just work everything out on paper or in my head and design the complete PCB in one go?One question I do have... Why shift the ROM address? I'm aware that this was done, but I've never seen a reason as to why. If the CPU expects the vector table to start at 0x000000, why not have the ROM and vector table at 0x000000? It seems unnecessary to shift it around, although I admit this is coming from a place of ignorance on my part.

author: DrGeoff
author_rank: Frequent Contributor
timestamp: March 28, 2023, 09:37:00 pm
content: The 68010 had a relocatable IV table.Being able to rewrite the interrupt vectors on the fly is important for many RTOS.

author: MarkS
author_rank: Unknown
timestamp: March 28, 2023, 10:07:04 pm
content: Quote from: DrGeoff on March 28, 2023, 09:37:00 pmSystem design, both hardware and software, is a new frontier for me. Why is it important?

author: Benta
author_rank: Super Contributor
timestamp: March 28, 2023, 11:04:08 pm
content: Quote from: MarkS on March 28, 2023, 10:07:04 pmIt's partial gobbledygook. No one ever rewrites IVs "on the fly".What happens is that when the 68k (applies to other architectures as well) comes out of reset, all vectors are stored inROM(starting at 0x0000...). Otherwise it wouldn't boot.Normally the vectors will be the lower part of a larger boot ROM containing all the startup code.Classic 68k systems will then copy the full contents of this ROM to RAM somewhere in the memory map.The external memory address decoder will have a hardware function to remap the relevant RAM area to 0x0000... and either disable the ROM or remap is as well.Now all exception vectors and boot code are in RAM, but still at 0x0000...This allows next step booting of operating system etc. that needs its own exception vectors like interrupts.

author: MarkS
author_rank: Unknown
timestamp: March 28, 2023, 11:30:05 pm
content: Oooohhh! That makes perfect sense!It may not be necessary in this project, but will be in the next one. Thank you for the explanation!

author: Benta
author_rank: Super Contributor
timestamp: March 28, 2023, 11:45:49 pm
content: Exactly.If you have an embedded 68k system with fixed functionality in ROM and RAM just for data, the memory map modification HW is unnecessary.But you'll still need HW for AS, LDS, UDS and DTACK.

author: MarkS
author_rank: Unknown
timestamp: March 29, 2023, 12:04:01 am
content: Quote from: Benta on March 28, 2023, 11:45:49 pmMy understanding about DTACK is that it was necessary when memory was much slower than today. Supposedly, I can ground it and be fine. I'm not opposed to implementing the circuitry, but I'd like to avoid it if possible.

author: srb1954
author_rank: Super Contributor
timestamp: March 29, 2023, 01:15:40 am
content: Quote from: MarkS on March 29, 2023, 12:04:01 amYou will need DTACK if you intend to use any of 68K peripheral chips.For sufficiently fast memory you can wire DTACK low, or preferably connect it to the memory address decoder so that it only responds in valid areas of the memory map. With this arrangement, and in conjunction with a bus time-out circuit, you can catch runaway programs that access invalid memory areas and re-route the program to a bus error handler routine.

author: Benta
author_rank: Super Contributor
timestamp: March 29, 2023, 05:07:50 pm
content: I'm with srb1954 here.If you're looking to make an absolute minimum 68k SBC, I'd drop all the buffers, they're not really necessary these days. Modern CMOS Flash and SRAM are no big bus loads.But in my opinion, the following elements are necessary for a well-functioning and robust 68k system:Clock.Interrupt encoder (74xx148).Memory decode (74xx139 or 74xx138).DTACK generator (74xx30 + 74xx04) and associated bus error timer.RESET/HALT logic.All this was in earlier days done with a PAL/GAL, but those are out of fashion.

author: David Hess
author_rank: Super Contributor
timestamp: March 29, 2023, 11:59:33 pm
content: Quote from: MarkS on March 26, 2023, 02:21:19 pmI know what boards you are talking about. They used 4 or more layers, and blind vias.

author: MarkS
author_rank: Unknown
timestamp: March 30, 2023, 12:57:41 pm
content: Quote from: srb1954 on March 28, 2023, 06:23:20 amYes, it is a little odd, I agree. The book I'm using for reference shows a debounced reset circuit and below that, a line labeled "single step" tied to HALT. Not too sure what that meant, I duplicated the reset circuitry. Now that I think about it, that truly is pointless. I'd have to press and hold that button once per 10 MHz clock pulse!So, what would a single step circuit look like? I can work it out myself, I'm sure, but I don't even know where to begin.

author: bson
author_rank: Unknown
timestamp: March 30, 2023, 05:59:00 pm
content: In general, ideally you want to place the buffers next to the header, attach the outputs 1:1 to the nearest header pin, then pick buffer input pins for signals as you route. Unfortunately, KiCad doesn't make this easy as you have to go to the schematic to draw lines, then update the PCB and route them. Ideally, you'd route buses to buffers on the PCB to then get a rats nest in the schematic, and then add the bus connections there. Sometimes for some design elements PCB-first is really the best approach...If acceptable you can also route the signals to buffers and buffers to the header and just let header signals fall where they may. This would yield the absolutely most compact layout, but at the expense of a bit of bus fragmentation on the header...

author: Benta
author_rank: Super Contributor
timestamp: March 30, 2023, 07:16:21 pm
content: Quote from: MarkS on March 30, 2023, 12:57:41 pmYou need to remember that the RESET and HALT pins have several functions, and that both signals arebidirectional.For a HW reset, you need to assert RESET and HALT simultaneously (mandatory).For resetting external peripherals, RESET is an output after executing the RESET instruction (seldom used).For the "big red mushroom" emergency stop button, HALT may be used as an input (very seldom used).For an LED indicating a catastrophic failure (double bus fault), HALT can be used as output (very often used).Single-stepping will normally be done using interrupts, much cleaner.

author: Benta
author_rank: Super Contributor
timestamp: March 30, 2023, 07:19:54 pm
content: PS: I hope you have this already:https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf

author: MarkS
author_rank: Unknown
timestamp: March 30, 2023, 08:08:45 pm
content: Quote from: Benta on March 30, 2023, 07:19:54 pmOh heck yeah! But it's a dense read.

author: Benta
author_rank: Super Contributor
timestamp: March 30, 2023, 08:42:43 pm
content: Quote from: MarkS on March 30, 2023, 08:08:45 pmI know what you mean. Looking at the 68000 is the mid-80s, I gave up on it as well - too complex.But around 1990, a mentor who understood the Motorola Computer Group's (and the associated Architecture guys) thinking behind the 68K took me under his wings. Bingo!When you understand the philosophy behind the CPU, everything about it suddenly becomes logical and inevitable somehow. Many idiosynchrasies come from squeezing everything into a 64-pin package.The fully-fledged 68020 didn't have that problem.

author: KubaSO
author_rank: Contributor
timestamp: March 30, 2023, 11:33:33 pm
content: Also, when things are twisted, flip the layer. Yep, sometimes that's what it takes to make layout easy. And make sure you can get one trace between each pair of pads. At least one. Two if you make the pads quite narrow and go for thin traces, say 7+7mil trace/space

author: KubaSO
author_rank: Contributor
timestamp: March 30, 2023, 11:43:17 pm
content: Quote from: MarkS on March 26, 2023, 04:36:00 pmI don't think I laid out anything in KiCad or Altium or anything else that didn't take some footprint modifications and new schematic symbols. Especially schematic symbols - my pet peeve. I have a seething hatred for the modern "everything is a box with net labels sprinkled around" approach. Yuck.You'll not want any defaults. Create at least a project-specific footprint library and keep all the tweaked footprints there. Measure actual dimensions of the pins you'll be soldering - whether directly or via milled sockets - and dimension things based on that + some radial clearance between pin and hole. 10mils diametric clearance should be fine if the holes are dimensioned as finished sizes.Look up the chosen PCB manufacturer service for minimum trace and space. For logic signals you may well use the thinnest to go between pads.I have several DIP designs that had "routing dots" between the pads. Those dots were tiny non-connected pads that maintained the trace and space as needed, and I could then easily route traces through them. The pads were back-annotated on the last schematic sheet, and weren't a big deal once I had the process worked out. Yes, in KiCad.PCB layout is an art. You won't do much good without some work to figure out a good process that gets good results. About the only footprints I haven't had to touch were SMD ones that have IPC-derived sizing and the reflow and hand-soldered variants are spot-on. For through hole stuff? Even the same axial part may need a couple different pad/hole size options, so yeah, you'll be having that footprint editor open and busy. It's part of the job.

author: MarkS
author_rank: Unknown
timestamp: March 31, 2023, 05:28:07 pm
content: Quote from: KubaSO on March 30, 2023, 11:43:17 pmThis is an absolutely brilliant idea! You've sold me! I don't WANT to make my own footprints, but that is a great reason to do so! Thank you very much for the idea!

author: KubaSO
author_rank: Contributor
timestamp: October 16, 2023, 01:34:05 am
content: Here's a 6.15x6.5 4-layer board I did a while ago for a discrete Z80-reimplementation. This is a 4-bit bit slice of the register file. Every DIP in the picture is for a CD4000-family chipAlso, every single pin on the card connector is used up, with just the minimal number of GND and VCC repeats needed for signal integrity. The capacitors are surface-mount 1206 on the bottom side. Through-hole capacitors waste a lot of real estate on such tight boards. Top layer mostly has vertical traces, bottom layer mostly horizontal traces. The internal planes are GND and VCC.Since this was a single-cycle-per-instruction Harvard implementation, with no pipeline, the register file had to have multiple read and write ports according to what the instruction set needed. This thing can run at about 4MHz from 12.5V supply. 4MIPS. 18 registers in total, with alternate register file included. The register file is 4-slices wide, so the data paths are all 16-bits. That was the only way to do 4MIPS with 70s discrete CMOS logic. Data and program memories also had multiple ports... I'm glad this is over, I got in way deeper than I thought it'd take.To get the ALU fast enough, only two bits fit on a card of the same size. All of it was implemented using 4066 muxes for logic and some 4051s as complementary output buffers to keep the muxes fed with strong inputs4 slice cards for registers, 8 slices for ALU, 8 slices for code memory and instruction decoder, another 4 slices for data memory, 6 unique cards for the controller, external bus interface, etc. No time to publish the whole thing yet...

author: floobydust
author_rank: Super Contributor
timestamp: October 16, 2023, 02:05:49 am
content: Where are the capacitorsOh and not sure if it's been mentioned but one layer is X direction only and other layer is Y direction only for traces, was a common method for routing, back in the day.

author: Agent24
author_rank: Regular Contributor
timestamp: October 16, 2023, 06:04:56 am
content: Quote from: MarkS on March 26, 2023, 04:36:00 pmYou don't need to, you can just edit the pad sizes on the component you need to change. Then you can update all pads on the IC or just change only the ones that need changing.Assuming you're using v6 or such, make sure the footprint is not selected, then right-click the pad and choose "properties" and edit the pad size etc. Once done, right click the pad again, choose "Push pad properties to other pads" and use the options there as appropriate.

author: jonpaul
author_rank: Super Contributor
timestamp: October 16, 2023, 06:43:56 am
content: Rebonjour,In 1970s..1990s,with double sided boards it was Common to use jumpers, route 2..3 traces between adjacent DIP pads, with special narrow elongated pads.JonPS: post title is insulting. Kindly edit out "Old farts"I suggest it is rude.

author: Nusa
author_rank: Super Contributor
timestamp: October 16, 2023, 08:18:27 am
content: Well, all of us who predate the internet are reasonably considered "old" now. And everyone farts. It's no worse than greybeard. Which is also true, although not that different from the blonde beard I used to have.