MAX4820 Daisy Chain Problem - Page 1
Forum section: electronics / projects

author: sixtimesseven
author_rank: Frequent Contributor
timestamp: January 01, 2022, 12:39:37 am
content: I have a rather strange problem regarding four MAX4820 relay drivers.https://datasheets.maximintegrated.com/en/ds/MAX4820-MAX4821.pdfI'm trying to run them in the Daisy Chain Configuration (Datasheet page 8 figure 3).Schematic looks like this:If I set the first device, all works fine. If I bridge the DIN from the first device to any other devices, they both work as expected (both with the same settings). But even the second device in the Daisy Chain does not work at all. I have attached two logic analyzer screenshots, showing the first device's DIN and DOUT. DIN looks fine (and the chip works), DOUT seems to be garbage.(MOSI = DIN and MISO = DOUT, I'm sending four bytes: [0xff, 0x04, 0x03, 0x01].There is something on DOUT, but I would eg. expect 8 high bits after 8 hight clock flanks, however I get 9 high bits on DOUT after 7 clock flanks.I have measured the resistances on the board for the DOUT-DIN connections and they're all fine. Layout:I'll attach the function to bit bang the DIN signal as well.Code:void setRelaysOn(uint8_t state[]){int delay = 0;int setupDelay = 4;HAL_GPIO_WritePin(GPIOA, CS_Pin, GPIO_PIN_SET); //Pull CS low to start writingHAL_Delay(setupDelay);for(int i = 0; i < 4; i++) // Loop for every of the four relay drivers{for(int j = 0; j < 8; j++) // Clock out 8bits each coresponding to the{HAL_GPIO_WritePin(GPIOA, SCK_Pin, GPIO_PIN_SET); // Reset clockHAL_Delay(delay);if(state[3-i] & (1 << (7 - j))) // D7 gets clocked out first, invert!{HAL_GPIO_WritePin(GPIOA, MOSI_Pin, GPIO_PIN_RESET); //Shift a high bit}else{HAL_GPIO_WritePin(GPIOA, MOSI_Pin, GPIO_PIN_SET); //Shift a low bit}HAL_Delay(delay);HAL_GPIO_WritePin(GPIOA, SCK_Pin, GPIO_PIN_RESET); //Rising Edge ClockHAL_Delay(delay);}}HAL_Delay(setupDelay);HAL_GPIO_WritePin(GPIOA, CS_Pin, GPIO_PIN_RESET); //Pull CS high and set statesreturn;}Maybe there is something hidden in the datasheet but I can't seem to find it

author: jwet
author_rank: Frequent Contributor
timestamp: January 01, 2022, 02:37:34 am
content: I was on the design team for these parts in my tenure at Maxim! Your logic analyzer plot doesn't show any DOUT pins- need to see this. What you're doing looks correct- do you know if the parts are initialized? This is that the reset is for. You can fake it by sending a dummy string or two first to get the part in a known state. The parts work just like a generic shift register. The max clock is somewhat slow at 2.1 MHz which was the main problem customers using hardware SPI, etc. but you're way below this.Do some initializations and see if that fixes things. Post DOUT from the first stage otherwise. The parts should just work.John

author: sixtimesseven
author_rank: Frequent Contributor
timestamp: January 02, 2022, 01:22:21 am
content: Quote from: jwet on January 01, 2022, 02:37:34 amHi JohnThank you very much for your answer. Well you can see the DOUT logic analyzer output in the picture above, named somewhat incorrectly MISO (worked well for decoding).After setting up another chip on a breadboard and rechecking the signal again with the oscilloscope I finally found the problem. It has nothing to do with the MAX4820 but with my optocouplers used to isolate the analog from the digital side. Classic signal bouncing problem. Directly connected the MAX4820 works fine of course. I will have to include buffer with Schmidt trigger input in the next revision.Edit: Note: The RC filter on the Opto input was intended to filter any noise from the digital side. Turns out that was not a smart idea at all

author: jwet
author_rank: Frequent Contributor
timestamp: January 02, 2022, 02:33:02 pm
content: This was an oversite by Maxim, actually me, as the product definer. We generally would have put a schmidt input on anything that we thought would be used with opto's commonly. Since relays are inherently isolating, I hadn't considered this. Many customers complain about schmidt type inputs because they can create skew and create assymetric delays- can be especially troublesome on synchronous data like this. Glad you solved it.