Which HDMI serializer chip to use for small fpga design?  - Page 1
Forum section: electronics / general

author: hve
author_rank: Regular Contributor
timestamp: July 28, 2021, 09:57:11 am
content: Hi All,Does anyone have a suggestion on a HDMI serializer chip to use, for a smal fpga project involving video on hdmi screen?I dont have any high speed differential pairs on the chip available unfortunately.Ideally I want to clock with pixelrates of up to 25-50 Mhz with 8-10 bits at a time, giving me a bitclock of up to 500 Mhz.I am looking at the TFP410 TI PanelBus™ Digital Transmitterhttps://www.ti.com/lit/ds/symlink/tfp410.pdfThis needs 12 bits + dual clocks + 4 controls = total of 18 IO'sAnyone in the field has some suggestions on alternatives?

author: Mario87
author_rank: Frequent Contributor
timestamp: July 28, 2021, 10:25:34 am
content: A little bit on confusion here as you mention the TFP410 but link to the datasheet for the TS3DV642.The TFP410 looks like it is limited to either 12 or 24-bit inputs, so not sure how well it will work (if at all) with your 8-10 bit pixel data.An alternative may be the ADV7513 from Analog Devices which says it does support 8-bit & 10-bit Y:Cb:Cr 4:2:2 inputs.You can see the tables on page 23 - 27 of the hardware user guide....https://www.analog.com/media/en/technical-documentation/user-guides/adv7513_hardware_user_guide.pdf

author: hve
author_rank: Regular Contributor
timestamp: July 28, 2021, 11:09:40 am
content: Quote from: Mario87 on July 28, 2021, 10:25:34 amThanks I corrected the link.I misspoke I mean bandwidth instead of pixelclock.My interface has a maximum of 14 IO's, and I would like to limit the bandwidth to max 50 Mhz.Otherwise I would have to add additional connectors which would make it overly complex.The ADV7513 still would require to much IO's.Ideally the chip would have a PLL for multiplying the input clock an input FIFO and a serializer in order to generate the 4 differential signals for the HDMI.

author: Mario87
author_rank: Frequent Contributor
timestamp: July 28, 2021, 12:17:17 pm
content: Not sure why you think the ADV7513 still requires too much IO? It supports 8-bit & 10-bit input + CLK + SDA + SCL (that is 11- 13 IO). You can have the syncs embedded in your bit steam and the H-Sync, V-Sync & DE can all be generated internally from that on the ADV7513 once the registers are correctly configured via the I2C (hence the need for SDA / SCL) and it does have an internal PLL to generate the TMDS and other clocks used internally to the ADV7513 from your input clock.Seems like it fits your needs from what I can see. Have you had a proper look at the Hardware User Guide I linked to? There is also a separate datasheet and programming guide with more details in them.

author: hve
author_rank: Regular Contributor
timestamp: July 28, 2021, 02:43:28 pm
content: Also see it is used on the DE10NANO, and 12 bits of IO seems possible.Browsing the 188 pages of programming info..I am still figuring out if it will let me inject audio, without using the I2S interface.

author: hve
author_rank: Regular Contributor
timestamp: July 28, 2021, 02:46:14 pm
content: Don't need high bit audio, low bit audio is perfectly fine for me

author: BrianHG
author_rank: Super Contributor
timestamp: July 28, 2021, 03:28:37 pm
content: You can try this:https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/Note that you would need to change the PLL and serializer modules to get this code to work on Xilinx or Lattice.You may ignore the I2C and the HotPlug Detect lines saving you a few IOs, but, doing so, I recommend sticking to official HDMI basic modes. You will need only 8 outputs at the absolute minimum. For 480p, maybe 720p you might get away with only 4 outputs using my recommended differential HDMI driver amp IC, (use 0.1uf caps to GND on the -inputs) but this would be up to you to test and verify.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 28, 2021, 03:59:53 pm
content: Tell us more.What kind of FPGA really? Maybe you can integrate the HDMI encoder and serializer inside the FPGA instead, as BrianHG suggested. Or maybe you can't. So tell us what FPGA you have in mind.If you really need an external chip, you will have a hard time finding something requiring fewer IOs. And, there is no magic anyway: the narrower the data bus, and the higher the data rate for a given pixel clock frequency. So... how fast could you pump out data with your FPGA? But anyway, I for one do not know of such a chip with a narrower data bus.Now for the obvious trick: the TFP410 supports several modes (12 bits/pixel and 24 bits/pixel, the latter can use a 12-bit data bus or a 24-bit data bus...)The question: do you really need 24 bpp? Can you do with less? In the latter case, you can just tie several data bits together, and save a few IOs.For instance, if 12 bpp is enough, you can use the 24 bits/pixel, 12-bit data bus mode and tie D0/D1, D2/D3, ... D10/D11. Thus you'll only need 6 IOs for the pixel data instead of 12.Likewise, if 6 bpp is enough, you can wire the data bus in the same way and use the 12 bit/pixel mode - with only half the data rate required compared to the above.You get the idea.

author: hve
author_rank: Regular Contributor
timestamp: July 29, 2021, 01:43:15 pm
content: Quote from: BrianHG on July 28, 2021, 03:28:37 pmHi Brian,Super nice project, I was thinking on building something similar.So as I understand the FPGA directly couples to the driver amp, this is the ideal way. However I think my board is limited as I will try to explain below.Quote from: SiliconWizard on July 28, 2021, 03:59:53 pmHi SiWizzard,This is the board:https://github.com/q3k/chubby75/blob/master/5a-75b/hardware_V7.0.mdits repurposed led? panel board from AliExpress which was about 17 Euro including shipping.Problem 1: board has most likely traces that are probably not matched for 250 Mhz operation and with different delays.Problem 2: Pins are split/shared in multiple paths, which makes problem no 1 even worse.Problem 3: At most 3 pairs of differential outputs available on a given connector.Code:] # Differential pairsconnectors = [ # high-speed | regular-speedConnector("j", 1, "F3 F1 G3 - G2 H3 H5 F15 L2 K1 J5 K2 B16 J14 F12 -"), # F1-G2 | G3-H3 K1-K2Connector("j", 2, "J4 K3 G1 - K4 C2 E3 F15 L2 K1 J5 K2 B16 J14 F12 -"), # | J4-J5 K1-K2Connector("j", 3, "H4 K5 P1 - R1 L5 F2 F15 L2 K1 J5 K2 B16 J14 F12 -"), # P1-R1 | K1-K2Connector("j", 4, "P4 R2 M8 - M9 T6 R6 F15 L2 K1 J5 K2 B16 J14 F12 -"), # | T6-R6 K1-K2Connector("j", 5, "M11 N11 P12 - K15 N12 L16 F15 L2 K1 J5 K2 B16 J14 F12 -"), # M11-N11 | K1-K2Connector("j", 6, "K16 J15 J16 - J12 H15 G16 F15 L2 K1 J5 K2 B16 J14 F12 -"), # J16-J15 G16-H15 | K1-K2Connector("j", 7, "H13 J13 H12 - G14 H14 G15 F15 L2 K1 J5 K2 B16 J14 F12 -"), # H12-H13 | G14-H14 K1-K2Connector("j", 8, "A15 F16 A14 - E13 B14 A13 F15 L2 K1 J5 K2 B16 J14 F12 -"), # | B14-A15 A13-A14 K1-K2Connector("j", 19, " - M13 - - P11"),]The thing crossed my mind to tie different inputs together, however the input pin cycles between different bits of the same stream.So in order to control the 4 MSB's of each stream I would still have to connect the 12 pins.Need some experimenting todo... probablyI will hookup a scopeand create some high speed clocks on the pins in order to see what can be done...Might find myself creating a simple VGA frontend and buy one of those cheap VGA-HDMI adapters

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 29, 2021, 03:49:57 pm
content: QuoteThose are cheap and have a Lattice ECP5-25, with which a lot can be done. When you said "small FPGA", I was thinking about some ice40, or something like this.One big problem with those boards, IIRC, is that all IOs are broken out to connectors through 5V level shifters. Pretty inconvenient if you want to interface with 3.3V logic. (OTOH, if you plan on using this board for interfacing with some vintage equipment, it could be handy.) But, no way you could directly interface with a TFP410, unless you butcher the board or add levels shifters to the level shifters...Dev boards based on similar stuff from Colorlight are available too. But not as cheap. I bought a couple, and they work fine. Much easier to deal with:https://aliexpress.com/item/1005002484371869.html?spm=a2g0o.productlist.0.0.75476dd22r8UCl&algo_pvid=699e880a-77d0-45b6-a02a-f90fd09e62ee&algo_exp_id=699e880a-77d0-45b6-a02a-f90fd09e62ee-4Those even have an HDMI connector. Although the ECP5 on those boards doesn't have embedded SERDES, you can implement HDMI for a resolution of 640x480 without a problem (there are demos available). For higher than this, nope.QuoteIf using the 12bpp mode, there's no problem. But then as I said, that would give you only 6bpp, which admittedly is pretty limited (but that's still 64 colors, could be enough, don't know what you want to do.)If you want 12bpp, then yes you'd have to use the 24bpp mode, and you'd have to figure out the color palette you'd get when tying data pins like this. It won't be linear, but again depending on application, it may be good enough, you'd just need to implement some conversion for the colors.

author: BrianHG
author_rank: Super Contributor
timestamp: July 29, 2021, 05:07:12 pm
content: People have gotten 480p/270MHz working with hand wired wirewrap designs. You can get away with minor trace differences. 743Mhz 720p is a different story.

author: BrianHG
author_rank: Super Contributor
timestamp: July 30, 2021, 05:47:45 am
content: Quote from: SiliconWizard on July 29, 2021, 03:49:57 pmNope, the limit of the ECP5 is the same as the DDR output pins, 800mbps. 720p@60Hz or 1080p@30Hz only needs 743mbps.The slowest ECP5 can do 624mbps, enough for 1024x768 reduced blanking at 60Hz, or 720p DVI reduced blanking which only requires 620mbps. (no audio, audio reduced blanking 720p requires 650mbps)

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 30, 2021, 04:53:42 pm
content: Quote from: BrianHG on July 30, 2021, 05:47:45 amDo not hesitate to have at it and report back.

author: BrianHG
author_rank: Super Contributor
timestamp: July 31, 2021, 01:16:34 am
content: Using the listed modes and LVTTL2.5v DDR outputs as a dumb serializer in emulated differential mode, driving the the Philips 90cent HDMI driver IC converter amp IC is exactly how my HDMI/DVI transmitter thread has been wired and tested with Nockieboy on his GPU thread. He has screenshots of the output in his 8 bit GPU thread. We know it works including tests on the odd video modes where we squeezed higher resolutions with lower mbps transmitters rates by reducing the front and back porch blanking periods.

author: hve
author_rank: Regular Contributor
timestamp: August 02, 2021, 08:57:08 pm
content: Quote from: SiliconWizard on July 29, 2021, 03:49:57 pmThe "level shifters" are HC245T chips, I will probably de-solder one, and connect directly to the inputs.I have seen the Colorlight i5 modules on AliExpress, might indeed get one, you need to replace the spi-flash in order to make your design persistent.Also interesting is this zynq boardhttps://www.aliexpress.com/item/4001309317597.htmlAnd I see thehttps://www.aliexpress.com/item/4000170003461.htmlXC7A100T with 100K cells...Quote from: BrianHG on July 31, 2021, 01:16:34 amI will have shot at the dumb serializer..Just put 262.5 Mhz on Pin K1 of the FPGA and made a screenshot on the scope:So chain is roughly:K1@LVCMOS33 --- 74HC245T --- 330 ohm --- J4-pin10 gives me:Seems pretty decent..

author: BrianHG
author_rank: Super Contributor
timestamp: August 02, 2021, 09:41:09 pm
content: Quote from: hve on August 02, 2021, 08:57:08 pmNope, your gonna need to probe the inputs of the 245. That's just too slowand it is no longer 50/50% duty cycledue to the 245s drive a logic low faster/harder than a logic high. Though, also remember, with a serial 250MHz clocked data output, each data output's toggle rate will max out at 125MHz, not 250MHz.Also, there is importance in phase between channels. One thing when you design you code driving the IOs is that you want to use the logic cells directly wired on the IO buffers, not have the compiler randomly route an internal logic cell somewhere else in the fabric to the IO's buffer. This is easy enough when you define the output buffer type like using a DDR buffer.

author: BrianHG
author_rank: Super Contributor
timestamp: August 02, 2021, 09:50:30 pm
content: The schem & gerbers using that 4 channel HDMI amplifier cable driver IC are available on Nockieboy's Github page. It a 2 layer board which should cost around 5$ for a few at that size.The IC should clean up some poor trace length matching on your existing third party PCB, though for 480p, most monitors should work without it. Just remember to diode protect your FPGA IOs if you are hard wiring it directly to a HDMI cable.

author: BrianHG
author_rank: Super Contributor
timestamp: August 02, 2021, 09:58:13 pm
content: Though it's Altera, have you taken a look at this:https://www.eevblog.com/forum/fpga/arrow-deca-max-10-board-for-$37/board? It has everything you need.It's a fraction the price of your other stuff, has 50kgate fpga and DDR3 ram with HDMI encoder onboard, as well as a crap load of other peripherals.

author: BrianHG
author_rank: Super Contributor
timestamp: August 02, 2021, 10:08:45 pm
content: Quote from: hve on August 02, 2021, 08:57:08 pmAlso, you will probably best choose a connector close to the FPGA and only use IOs which are not shared across all the Jxx connectors for the best timing, this may mean using 2 adjacent connectors.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 02, 2021, 10:27:58 pm
content: Quote from: hve on August 02, 2021, 08:57:08 pmNo, you don't. Dunno where you read this? Edit: I think I know why you said that: the SPI flash on those boards is locked (write-protected) in factory. But the program below (and others) can unlock it through just a command line option. You only need to do this once.There's absolutely nothing to butcher on those boards. You just need to use the right tools for programming them. I have zero problem programming the onboard Flash and have the FPGA configured from it at power-on. I currently use ECPDAP, which works a treat (can both configure the FPGA on the fly - very fast, so I use this for developing - and program the SPI Flash.)https://github.com/adamgreig/ecpdap