Power Consumption of Cyclone IV on each voltage rail - Page 1
Forum section: electronics / general

author: soFPG
author_rank: Frequent Contributor
timestamp: July 05, 2020, 09:48:55 pm
content: I plan to design a PCB with a EP4CE6E22C8N on it. According to the "Cyclone IV Device Datasheet" - Table 1-3, this FPGA needs 1.2V (Vccint), 3.3V (Vccio) and 2.5V (Vcca).This means I am probably going to have three LDOs on my PCB. To properly size them in terms of max. current output I was looking at the chapter "Power Consumption" - but here the datasheet tells me to download some weird Excel file (I don't even have Microsoft Office) or instead use the Quartus PowerPlay analyzer.Is it too much to ask for a rough max current draw for each voltage rail?Is 300mA per voltage rail enough?

author: asmi
author_rank: Super Contributor
timestamp: July 06, 2020, 01:14:16 am
content: Estimating FPGA power consumption is inherently difficult because it very much depends on design it's running, but also on speed grade, package, external connections/interfaces, etc. This is why there are no set numbers. Xilinx also provides Excel file which allows to guesstimate the currents on each rail by entering some basic information about design. The way I go about this is typically to assume fairly high utilization of onboard resources (CLBs, BRAM, DSPs, etc), plus high-speed interfaces I plan to have on board (because they typically have very large transient currents).But there is one thing I can tell you - using LDO for core voltage is very bad idea, because it's going to be horrendously inefficient and will have to dissipate a lot of heat, and FPGA tend to consume quite a bit of current on that rail due to low voltage. Instead I suggest using switched mode buck converter, as they can reach efficiency of 90% and more. I would recommend you to take a look at TPS65581 chip - it's a triple buck converter, so it can provide all three rails in a single chip, it's about as simple to use as it gets (no need for external compensation, no I2C interface - basically you need input cap, inductor, output cap(s) and two resistors to set the output voltage), each channel can be independently enabled/disabled via ENx pin, and there is an optional open-collector "power good" pin per channel in case you need it. Check the project in my signature for example as it uses that very chip. The datasheet for the chip has a table listing recommended values of all these external parts for each output voltage, so there is no reason to guess or calculate anything. It also accepts any input from 4.5 to 18 V, which makes it very versatile.

author: ejeffrey
author_rank: Super Contributor
timestamp: July 06, 2020, 02:04:37 am
content: You can almost certainly use the spreadsheet in libreoffice and possibly in Google sheets.Current varies by a huge amount depending on logic utilization, DSP slice usage, serializer use, clockk frequency, number of IO pins in use and so on. In addition there are dozens of models with different amounts of logic, pins and peripherals which all have different maximums. It's easier just to use the spreadsheet.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 06, 2020, 08:38:31 am
content: Thank you!I think using switching regulators instead of LDOs was probably the most important hint. Nevertheless, if this FPGA needs more than 1A on each voltage rail I think I am going to have some serious heat problems (what I am trying to say is that a 1.5 - 2.0A regulator should be enough).

author: Daixiwen
author_rank: Frequent Contributor
timestamp: July 06, 2020, 10:20:02 am
content: It really depends on your design. The load on the 2.5V is pretty low. The load on your 3.3V depends on I/O usage, and can usually be low also, but of course it depends on your interfaces, how much they are loaded and their switching frequency.The load on the 1.2V though depends a lot on how much of the internal logic you use, and at which frequency. It can quickly go up to several amps.

author: OwO
author_rank: Super Contributor
timestamp: July 06, 2020, 10:40:29 am
content: That is a tiny FPGA. 1A for the 1.2V rail should be enough. I would simply use one of those standard SOT26 buck converters like the FP6373A.This is the standard pinout for a SOT26 buck IC you should look for (avoid buck ICs with nonstandard pinouts).

author: soFPG
author_rank: Frequent Contributor
timestamp: July 06, 2020, 11:01:09 am
content: Thank you!QuoteThere are even more tiny FPGAs. I think 6k LUTs aren't that tiny?Another question: What determines how voltage stable a DC/DC buck converter is? Because taking a look again at the Cyclone IV Device Datasheet, the range of voltage is tight:Vccint: 1.15 - 1.25V (0.1V)Vccio: 3.135 - 3.465V (0.33V)Vcca: 2.375 - 2.625V (0.25V)

author: asmi
author_rank: Super Contributor
timestamp: July 06, 2020, 02:00:07 pm
content: Quote from: soFPG on July 06, 2020, 11:01:09 amIt is tiny. I have Spartan-7 S50 device (over 52K logic cells) on a board consuming less than 2.5 amps of power at like 70% utilization and some clock buffer overclocking, and it uses even lower Vccint (1.0 V±5%).Quote from: soFPG on July 06, 2020, 11:01:09 amModern buck converters are very precise and stable. The device I recommended above has 1.5% accuracy, and it's a rather old chip (from 2013 AFAIR). Modern bucks - even cheap ones like AOZ2151 - have accuracy of 1%, and some are 0.5% accurate, or even better for things like CPUs and GPUs where tolerances are very tight.Now, you have to remember, that reference precision is only one factor to the final accuracy. Another one is how precise your resistors are in divider that sets the output voltage. You should use at least 1% accurate resistors, but it's not uncommon to see even more precise ones used when the tolerance is tight. With 0.1% resistors prices right now being a fraction of a dollar I think you should consider using them.Another useful trick I learned while working with FPGAs - their current consumption (and consequently, power dissipation) depends on voltage, so I always try to keep the Vccint closer to the lower side of tolerance corridor (closer to 0.95 V in my case of spec being 1.0±5%V). And the reason I can do it exactly because these bucks are very precise.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 07, 2020, 05:51:29 pm
content: I thought about choosing the TPS65581 but at 3$ it seems to be rather expensive.I now went with three JW5033S (https://datasheet.lcsc.com/szlcsc/1906281506_JoulWatt-Tech-JW5033S_C324577.pdf) which are even able to supply 2A output current.One of the advantages of the TI-part probably was their table for inductor values. Unfortunately, I now have to calculate them on my own for the JW5033S but I am not really able to grasp how the formula works.The formula on page 11 requires a fixed input voltage parameter (at least that's the way I understand it). On page 12, however, the datasheet says "Vin: 4.7V - 18V" - how are they able to give a range of input voltages if their formula one page above requires one specific value for input voltage?I am also not so sure what to choose for the ripple current parameter. 0.4 * 2A = 0.8? What if the whole system doesn't need 2A on that particular voltage rail but maybe just 250mA? Is the formula then invalid?My plan was to use USB (5V, 0.5A may seem to be a little low but in case that's not enough I am going to switch to a external power supply) for the time being.Any ideas how to calculate the three inductor values for 1.2V, 2.5V and 3.3V?

author: asmi
author_rank: Super Contributor
timestamp: July 07, 2020, 06:14:52 pm
content: Quote from: soFPG on July 07, 2020, 05:51:29 pmSeriously? Remember you get 3 buck converters in a single package. That's super-cheap.Quote from: soFPG on July 07, 2020, 05:51:29 pmIt's reference accuracy is only ±3%. That's quite poor for a buck. You get what you pay for. Add two 1% resistors, and you're already at 5%, which is not good enough for low-voltage Vccint rail.Quote from: soFPG on July 07, 2020, 05:51:29 pmTypical values for low current bucks are 2.2 uH for < 2.5 V, 3.3 uH for 3.3 V, 4.7 uH for 5 V. You can get away with using 2.2 uH across the board (I've done so in the past to optimize BOM, though obviously using more respectable devices), though the ripple might be higher, which can be countered by adding more output caps. When choosing inductors, make sure saturation current is at least 1.5 times maximum output current.

author: soFPG
author_rank: Frequent Contributor
timestamp: July 07, 2020, 06:41:09 pm
content: QuoteWhere did you get these values from?QuoteWhy? Are these "empirical values"?QuoteYeah, I see. That's unfortunate, my bad. Thanks for the information.Are there books about step-down buck switching converters (more focused around application than on theoretical formulas) which are recommandable?

author: asmi
author_rank: Super Contributor
timestamp: July 07, 2020, 07:21:59 pm
content: Quote from: soFPG on July 07, 2020, 06:41:09 pmThese are typical values I've seen used in many different designs. For this very part, there are two reference designs for 3.3 and 5 V outputs, and you can see that they recommend 3.3 and 4.7 uH respectively.Quote from: soFPG on July 07, 2020, 06:41:09 pmQuote from datasheet:QuoteDifferent manufacturers recommend different margins, I usually use 50% because more is safer, even if it might be a bit excessive.You have to be a bit careful here, because inductors typically have two current limits - maximum rated current, and saturation current. First one is determined by the maximum allowed temperature rise (or, to simplify a bit, how much power will be dissipated on inductor's DC resistance, plus inductor losses caused by the core and some other physical properties). So it's more of a "soft-limit", meaning it's OK if the current goes above it every once in a while - the worst thing will happen is device will be a bit hotter - so not that big of a deal in the grand scheme of things, as long as it doesn't stay there long enough to cause serious overheating. Second one (saturation current) is MUCH more important. Again, to save you from reading a lecture on electromagnetics, I will just mention that you want to make sure your inductor's current does NOT go above saturation under ANY circumstances. You can google for "inductor saturation current" to get more detailed explanation. There is also DC resistance, which determines amount of ripple you get, and also affects efficiency - basically you want it to be as low as possible while still being small enough and cheap enough for your intended application.Quote from: soFPG on July 07, 2020, 06:41:09 pmYou can still use it for your IO rail if you so desire, as it usually doesn't require high precision. For Vccint you might want to take a look at TLV62130 - it's cheap, it's carried by LSCS, and it's a bit more accurate - 2.5% over PVT, it's good enough if you use 1% (or better) resistors for Vout divider. The datasheet includes schematics for 1.2 V Vout, showing all values you need (btw they use 2.2 uH inductor).Quote from: soFPG on July 07, 2020, 06:41:09 pmI recommend you to start research from here:https://www.ti.com/power-management/non-isolated-dc-dc-switching-regulators/step-down-buck/buck-converter-integrated-switch/support-training.htmlIt's a good all-around source of information, though obviously they are using TI parts as example (which I personally don't mind and use a lot), but the principles are universal regardless of manufacturer - they all work in a pretty much the same way.

author: asmi
author_rank: Super Contributor
timestamp: July 07, 2020, 07:33:59 pm
content: Forgot to mention - as you will learn soon enough, proper layout is critical for ensuring good performance of DC-DC converters. Every converter chip's datasheet I've seen includes reference layout recommendations and examples, pay attention to them and do your best to follow these recommendations (it's not always possible to follow them to the letter, but do what you can to accommodate at least the most critical ones - positioning input/output caps and inductor as close as possible to chip to reduce current loops, separating noisy switching traces from sensitive analog ones).

author: OwO
author_rank: Super Contributor
timestamp: July 08, 2020, 06:09:25 pm
content: JW5062T has the same pinout but with 1.6% reference accuracy. Inductor value lower bound is determined by the ripple current you can tolerate, but there is also an upper bound related to voltage overshoot (e.g. if load current suddenly drops to 0, all the stored energy in the inductor will be dumped into the output capacitors, and this will give you an overshoot).

author: Miti
author_rank: Super Contributor
timestamp: July 28, 2020, 10:43:03 am
content: I hope the OP doesn’t mind me asking a question somewhat related to his question. What about the power up sequencing, how do you achieve that? Controlling the EN pin on the switching regulators I think. What about the linear regulators? I bought a development board with Cyclone 4 from Ali, it has 3 x 1117 regulators.

author: rstofer
author_rank: Super Contributor
timestamp: July 28, 2020, 11:29:17 am
content: I don't play in the Cyclone arena but don't they make a development board for just about every device? How do they handle the power supplies? Power sequencing is indeed an issue but the multi-output converters can probably deal with it.If I were building a board for a Xilinx part, I would copy the design info from the Digilent schematics for that device.This document is targeted at Xilinx but the ideas are sound:https://www.maximintegrated.com/en/design/technical-documents/tutorials/5/5132.html

author: BrianHG
author_rank: Super Contributor
timestamp: July 28, 2020, 07:48:53 pm
content: Quote from: Miti on July 28, 2020, 10:43:03 amSo long as the core voltage of a Cyclone I/II/III/IV/V is supplied in parallel with IO bank supply, the Cyclone series do not require a power up sequence.So, if the core is 1.2v, as you power up, as long as the IO supplies go up in parallel, you are ok. If you power up the IO banks, then power up the core to 1.2v, this may be a bad idea, though it does not seem to be specified in the Cyclone handbook other than you should not exceed the min and max voltage spread listed in the DC electrical characteristics.This is why simple 3 linear regulators will be fine as the 1.2v is usually reached right away as the higher voltage IO banks continue on their way to 2.5v & 3.3v as the power feeding the regulator's inputs rises.This means do not power the core voltage 1.2v regulator off of the 3.3v regulator output as with this configuration, the core 1.2v voltage will now rise with slight lag behind the 3.3v IO voltage as the 1.2v regulator has a voltage drop from it's vin to vout making your VCCIO appear to rise to beyond 1.5v before the core supply begins to rise, and then the IO will be at ~2.5v before the core gets to 1.2v.

author: mariush
author_rank: Super Contributor
timestamp: July 28, 2020, 08:50:04 pm
content: I'd suggest looking into one buck regulator for the highest current rail (or the first required) and a regulator with 2 outputs for the 2 other voltages.For example, look into a 1.2v buck regulator, and a dual output regulator for 2.5v and 3.3v. There's also buck regulators with a built in LDO ... so for example you could have buck regulator to 3.3v and use the built in LDO to output 2.5v if the current is low enough.Examples for 1.2vYou have chips like AP63200 for 50 cents, or higher frequency chips like ST1S06 from ST that runs at 1.6 mhz for around 75 cents.For dual output, see maybe chips like AP3427M :https://www.diodes.com/assets/Datasheets/AP3427M.pdfor a bit more expensive mic23158 (dual 2a running at 3 mhz so you're saving on everything else) :https://www.digikey.com/product-detail/en/microchip-technology/MIC23158YML-TR/MIC23158YML-CT-ND/9643561

author: Miti
author_rank: Super Contributor
timestamp: August 01, 2020, 12:18:03 am
content: Quote from: BrianHG on July 28, 2020, 07:48:53 pmI guess the designers of this development board did not read the datasheet. That's exactly what they did, they power the core voltage from the 3.3V rail, not to mention the overshot. See attached scope shots. I never had a problem with it starting or anything...so far.

author: BrianHG
author_rank: Super Contributor
timestamp: August 01, 2020, 12:57:22 am
content: Like I said, Altera/Intel doesn't really specify a powerup order for the Cyclone series.However, if I was designing with a 500$+ Stratix FPGA, you better believe I would scrutiny every ounce of the data handbooks.If there was a problem, like with one of my Analog devices HDMI RXD / sampling processors, the chip gets hot and a regulator may burn up as the IC draws too much current on a supply rail and fails to function, or it just doesn't do anything at all. I bet if my regulator was strong enough in this situation, the IC may have been blown.

author: Miti
author_rank: Super Contributor
timestamp: August 01, 2020, 02:03:51 am
content: Quote from: BrianHG on August 01, 2020, 12:57:22 amIt does specify for Cyclone V:Power-Up Sequence Recommendation for Cyclone V DevicesFigure 10-3: Power-Up Sequence Recommendation for Cyclone V DevicesTo ensure the minimum current draw during device power up for Cyclone V devices, follow the power-upsequence recommendations as shown in the following figure.Power up VCCBAT at any time. Ramp up the power rails in Group 1 to a minimum of 80% of their full railbefore Group 2 starts. Power up VCCE_GXB and VCCL_GXB together with VCCPower UpPower up all the power supplies that are monitored by the POR circuitry. All power supplies, includingVCCPGM and VCCPD, must ramp up from 0 V to the recommended operating voltage level within theramp-up time specification. Otherwise, hold the nCONFIG pin low until all the power supplies reach therecommended voltage level.For Cyclone IV:Power UpIf the device is powered up from the power-down state, VCCINT, VCCA, and VCCIO (forthe I/O banks in which the configuration and JTAG pins reside) must be powered upto the appropriate level for the device to exit from POR.Power-On Reset (POR) CircuitThe POR circuit keeps the device in reset state until the power supply voltage levelshave stabilized during device power up. After device power up, the device does notrelease nSTATUS until VCCINT, VCCA, and VCCIO (for I/O banks in which theconfiguration and JTAG pins reside) are above the POR trip point of the device.VCCINT and VCCA are monitored for brown-out conditions after device power upDevices Driven Before Power-UpYou can drive signals into regular Cyclone IV E I/O pins and transceiverCyclone IV GX I/O pins before or during power up or power down withoutdamaging the device. Cyclone IV devices support any power-up or power-downsequence to simplify system-level designs.

author: BrianHG
author_rank: Super Contributor
timestamp: August 01, 2020, 04:00:50 am
content: Quote from: Miti on August 01, 2020, 02:03:51 amYup, had to do this on my CycloneIII video scaler project. Also had to drive that pin low during a power off with a brown-out detect circuit since my voltages dropped slowly enough with a bounce on the VCCint that sometimes, a few IO cycles would erase a block of connected flash memory. It took me awhile to discover that as the flash I was using was shared free space inside the cyclone's boot-prom. So, my boot prom basically would self-destruct around 1 in 100 power downs.