Efinix - Page 1
Forum section: electronics / general

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 04, 2019, 05:54:08 pm
content: https://www.efinixinc.com/products.htmlHas anyone heard of them?

author: ebclr
author_rank: Super Contributor
timestamp: December 04, 2019, 07:42:41 pm
content: 1st time, appear interesting

author: mark03
author_rank: Frequent Contributor
timestamp: December 04, 2019, 09:54:15 pm
content: QuoteFairly useless marketing-ese. Anyone care to speculate what their "Quantum technology" actually is? And what gives this an edge over "traditional" FPGA products?Their initial package matrix is pretty awful. Nothing in a low-ball-count package except for the tiniest devices, and only enormous-ball-count packages for their larger devices. It is even more extreme than, e.g., Xilinx: fully half of the line is only available in packages with more than 256 balls! And of course no QFN options, which is perhaps more understandable, but still unfortunate. I don't understand why no one caters to applications which need lots of fabric but very little I/O?

author: mark03
author_rank: Frequent Contributor
timestamp: December 04, 2019, 10:15:42 pm
content: So they actually do say more on their technology page:QuoteThis doesn't sound like it involves any new process technology, just a design innovation. After decades of progress in programmable logic, how is it that Efinix have come up with this [apparently revolutionary] advance while Xilinx/Intel are stuck with inefficient legacy designs?But what do I know...? Curious what the seasoned FPGA folks think.

author: ebclr
author_rank: Super Contributor
timestamp: December 05, 2019, 05:35:16 am
content: I guess Risc V is the thing

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: December 05, 2019, 11:05:53 am
content: Quote from: mark03 on December 04, 2019, 10:15:42 pmThere was a time when "innovation" meant "false prophecy", and in subtext it remains so today. If it were really "quantum" each cell could act as both logic and routing at the same time.Oh well, any load ofto create patentable subject matter to keep the game going.Quote from: blueskull on December 05, 2019, 05:53:02 amThey're apparently a joint venture including Xilinx. I think Efinix are in it to get bought. Moving back to the USA is a natural move under such circumstances.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 05, 2019, 09:03:30 pm
content: Quote from: blueskull on December 05, 2019, 05:53:02 amYeah, I'd be curious to do that, just to see. Unfortunately, you need to buy at least a dev kit to be able to download the tools. I'll see.

author: djnz
author_rank: Regular Contributor
timestamp: December 15, 2019, 07:49:46 pm
content: Somewhat cheaper dev board:https://www.crowdsupply.com/xips-technology/fireantSoftware (~ 260MB in size), link should be valid till about Christmas 2019:Windows 64 bit:https://transfer.sh/102PQ2/efinity-windows-x64.msiUbuntu linux 64 bit:https://transfer.sh/12FHcs/efinity-ubuntu-x64.tar.bz2I haven't had time to play with it much but like that the software seems quite light-weight. I am very interested in hearing the views of more experienced forum veterans about the software.

author: Smokey
author_rank: Super Contributor
timestamp: November 16, 2022, 08:58:08 pm
content: Resurrecting this old thread because they are the only parts readily in stock at Digikey right now.I found this article from 2019:https://www.eejournal.com/article/efinix-yet-another-fpga-company/Anyone used their FPGAs in an actual design?

author: asmi
author_rank: Super Contributor
timestamp: November 17, 2022, 03:55:35 pm
content: I wanted to give it a try, but their IDE is not available publicly (you have to buy a devkit to get access to it), which is a problem if I would want to design a more sensible devboard and somebody else would want to use it, and their own devboards are insanely overpriced for what they are. It's almost as if they are trying to hide a license cost of IDE in prices of their devkits. NOT a good idea.

author: mon2
author_rank: Frequent Contributor
timestamp: November 17, 2022, 04:43:03 pm
content: Hi. Have worked with the Ti60 since the introduction. Faced assorted hurdles including 3 weeks of trying to convince the factory that their demo examples and documentation were flawed. After some brow beating, they agreed and have since then, corrected the bugs we reported.We are in a similar boat with GOWIN -> now the factory is silent. Had excellent support from Gowin till we alerted the HYPER RAM IP was buggy. Crickets after this reporting.I get it, 'buy containers of our devices and without support'. Wish we could do the same. Our building is full of buggy silicon so no thank you. We will buy when we are confident the devices function as advertised.We are still very green (not meaning low power) to FPGA devices but apparently can locate bugs that the factory could not.The tech support from Efinix has been excellent and David (FAE; USA) from Gowin has been amazing till the last bug reporting.The IDE from Efinix does not expire but a valid kit is required for the updates. Noting these conditions, I am confident they will not have an issue to share the IDE here. Have had these open chats with Roger (Efinix, USA) in the past.Is that of interest ? Can share via a cloud account. We have a few years of active account support with Efinix.Would not hesitate to work with either company if you are comfortable with their toolchain / IP generation. We have active designs in development with both vendors.Wish to comment that the GOWIN toolchain is quite fast from start to end - can generate a binary image in a few minutes or sooner (sometimes seconds).The Efinix toolchain takes about 35-40 mins on average to almost 1 hour. Just a FYI.

author: up8051
author_rank: Frequent Contributor
timestamp: November 17, 2022, 05:38:48 pm
content: Quote from: mon2 on November 17, 2022, 04:43:03 pmDoes this also apply to PSRAM Controller IP?Can you say more about this bugs?Just started trying with PSRAM Video Buffer (GW1NR-9).

author: mon2
author_rank: Frequent Contributor
timestamp: November 17, 2022, 05:43:38 pm
content: Please see here:https://www.reddit.com/r/FPGA/comments/vdzowh/using_gowin_gw1nsrlv4c_psram_and_hyperram/I posted the details there. Still have not resolved the fault but it is enough, for now, to use this external storage for data / FIFOs / serial port buffering. In the near future, need this working properly for video bitmap storage for MIPI DSI projects.

author: asmi
author_rank: Super Contributor
timestamp: November 18, 2022, 03:39:42 pm
content: Quote from: mon2 on November 17, 2022, 04:43:03 pmIf so they would've just posted a download link publicly/behind free ITAR check, like every other FPGA vendor is doing. I'm really interested to play around with their software, but I don't feel like dumping $500+ for their devboard just to satisfy my curiousity. Parts by themselves look somewhat interesting, due to the 16 nm process the fabric should be quite fast.

author: mon2
author_rank: Frequent Contributor
timestamp: November 18, 2022, 04:25:57 pm
content: You can receive full access to their toolchain / IP for a year with one of their lower cost kits through Digikey:p/n:2134-XYLONI-NDXyloni FPGA T8F81 Trion® FPGA Evaluation Boardhttps://www.digikey.ca/en/products/detail/efinix-inc/XYLONI/13535080This used to be a $35 USD kit (pre-covid).

author: asmi
author_rank: Super Contributor
timestamp: November 18, 2022, 05:02:02 pm
content: Quote from: mon2 on November 18, 2022, 04:25:57 pm$110 for a useless devboard which will be collecting dust? No thank you.

author: AndyC_772
author_rank: Super Contributor
timestamp: November 18, 2022, 05:21:55 pm
content: I'm busy porting a design to Efinix right now, thanks to the complete failure of Intel to make Cyclone parts available any longer.So far, my impressions are:- I can actually buy them. Can't overstate just how important this is. Seriously, it trumps absolutely everything else.- Having to buy a Xyloni board to get a licence key was a completely trivial non-issue. I'm using these products commercially, so a 2 or low 3 figure sum to obtain the dev tools doesn't even warrant the time spent to think about it. The value of my time that'll be spent porting the design, not to mention the commercial value of the end product, makes it barely even a rounding error. Just order the board.- Support from the manufacturer has been good so far. Yes, you read that correctly - support from theactual manufacturer. Try getting that from one of the bigger players.- There are some important architectural quirks, especially to do with the internal interface between the programmable core and thecompletely logically separateI/O ring (which includes PLLs, DDIO interfaces and optional latches). It's like having two physically separate parts inside the same package, and I've yet to find anything I actually like about that.- Timing constraints are applied to the core, NOT the physical pins of the device. If anyone's figured out how to apply constraints that govern, say, the Tco for a data pin on the FPGA relative to a clock pin also driven by the FPGA, then do please let me know. This does seem to be an area in which that separation between core and I/O ring is particularly awkward.- Documentation surrounding timing constraints is - as per the industry standard - incredibly unclear. Would it really be asking too much to be told 'this is the delay fromspecific point Atospecific point Bwhen triggered byspecific clock C' - complete with a few diagrams and worked examples?- On the subject of timing - the synthesis tool appears incapable of inserting delays to cope with internal clock skew. So, for example, you can create a slow clock from a fast one by using a logical counter, but you'll struggle to pass data between those two clock domains because the tool can't then meet hold timing when going from the slower domain to the faster one. This is a big difference, and a major limitation, compared to Altera / Quartus, which copes admirably with this scenario.

author: asmi
author_rank: Super Contributor
timestamp: November 18, 2022, 05:59:44 pm
content: Quote from: AndyC_772 on November 18, 2022, 05:21:55 pmYes, that is a big reason I'm considering looking at them as well.Quote from: AndyC_772 on November 18, 2022, 05:21:55 pmIt's a point of principle. I don't know how it works with Antel, but with Xilinx once you buy a license, that version stays with you FOREVER without a need to buy any upgrades. You only renew license if you want to get access to newer versions of software. But for many parts they just provide a free version which can be freely downloaded (without buying any of their devboards) and used forever without any time limitations.Quote from: AndyC_772 on November 18, 2022, 05:21:55 pmThis is balanced by the fact that you don't require support from big mfgs nearly as often. Also from my personal experience, on a few times I actually needed their support, I was able to get it in a timely fashion. So not really an advantage here.Quote from: AndyC_772 on November 18, 2022, 05:21:55 pmUnfortunately timing is a PITA in pretty much all toolchains, and poor documentation doesn't really make things easier. But using logic to create clocks is incredibly bad idea anyways (that's what PLLs are for!), so no big problem here.One more major point is their IDE doesn't seem to come with any simulator. That is a BIG problem for me.

author: Neilm
author_rank: Super Contributor
timestamp: November 18, 2022, 07:50:22 pm
content: Quote from: AndyC_772 on November 18, 2022, 05:21:55 pmI am in the same boat for the same reasons. I think Intel are going to make that obsolete - we have been quoted 2024 for parts.The toolset seems to be a bit immature and the split between the logic and the IO doesn't make sense. So far, the bits that annoy me the most are that some of the IP cores are generating warnings (seriously) and a bidirectional port is fiddly to use. You have to generate an input, an output and an enable line then mash them together. Very annoying if the signal is going a few blocks deep. Also, the tool set does not seem to want to use logic to generate multipliers. I'm not going to moan about the FIR IP as it is a prototype they note is not finished (but if they implementd a folding parrallel FIR it would fit the chip I originally speced)I am just starting to look at fixing the timing issues so... Yay

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: November 18, 2022, 07:54:01 pm
content: Quote from: asmi on November 18, 2022, 05:59:44 pmThat's the sort of thing that a bigger company can afford. Smaller guys need revenue streams and even nominal ones add up over time.FWIW, when my license ran out, I just pinged support and they gave me an extra year, no questions asked. I'll echo the comment below that the support is excellent.Quote from: asmi on November 18, 2022, 05:59:44 pmYou must have much better contacts at Xilinx and Altera than I do then. When I had an issue with the SDRAM controller, we exchanged emails even late at night (and Rochelle was based in the same timezone as I am in), and even on weekends. When that didn't fix it, she set up a video conference so we could walk it through together.I've never had anything even remotely like that from the big players, and Efinix know I'm small-fry - they know they probably won't get huge business from me, so it's even more impressive IMHO. Of course, I do tend to tell people about how good their support is at every opportunity - so maybe it's paying off for them that way .Quote from: asmi on November 18, 2022, 05:59:44 pmYep, this is a downside. I was using Icarus / GTKwave.

author: AndyC_772
author_rank: Super Contributor
timestamp: November 18, 2022, 08:33:02 pm
content: Quote from: Neilm on November 18, 2022, 07:50:22 pmYep - today I spotted that the dual clock FIFO is complaining about an internal reset signal not being connected.I've also just found out that the same function's 'empty' output doesn't seem to work at all - maybe it's synchronised to the read clock, which in my design, doesn't run until there's something in the buffer to read.Chicken, egg, and all that. Maybe it's something to look at on Monday.QuoteGood luck!

author: Neilm
author_rank: Super Contributor
timestamp: November 19, 2022, 06:36:42 pm
content: Quote from: AndyC_772 on November 18, 2022, 08:33:02 pmThat is one of them I have found - along with size mismatches getting truncated.QuoteThanks - I have a horrible feeling I'll need it...Neil

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 24, 2022, 11:45:18 pm
content: I've a heavy Xilinx user. Well, small SPartan7 up to MPSoC Ultrascale+ (which I love and hate due to the 12,000 pages of doco you really DO need to read)....I have been evaluating the Efinix parts the past 4 months. I bought a Xyloni kit to start(never used). and now I have a Ti180-M484 Dev kit to show them I am at least half serious.The manufacturer's factory and representative support (Braemac) has been excellent.I get the feeling the devices are good, but the toolchain is young.I rely quite heavily on alot of the xilinx IP. to move some of those designs to efinix I will need to do things a different way- which means writing my own cores (likely wit the bare minimum of paramaterization) with high level synthesis , which the mfr support have been good with guidance- of course this technique usually chews logic cells like there is no tomorrow, so I think the 180 size part will be suitable to replace the a 50k logic cell heavily optimized with xilinx core xilinx..... They are FAST ! Sure I can use that multiplier 4x as fast. but- it takes work to use that speed. IE sharing DSPs to do different jobs, multiple jobs etc is non trivial.the leakage is very low. price is good. very good, but I have a bunch of IP to write. and its verilog centric. groan, (I am a VHDL shop)My work is 99% signal processing with screaming DDR converter interfaces. (SDR platforms)-glen

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 25, 2022, 12:34:13 am
content: NEIL- xilinx cores do that also. that is pretty normal stuff. expect loads of warnings from cores.-glenQuote from: Neilm on November 18, 2022, 07:50:22 pmQuote from: Neilm on November 18, 2022, 07:50:22 pm

author: asmi
author_rank: Super Contributor
timestamp: November 25, 2022, 01:32:21 am
content: For me the lack of built-in simulator is a big problem. I'm too used to Xilinx full-featured sim being always available, and, more importantly, I can be sure that what it outputs is what's actually going to happen in a real life - including timing-wise. Also I've been using AXI Verification IP for pretty much all of my component designs that use AXI bus in some way or another as it not only ensures compliance, but also provides great sim capabilities like easy generation of AXI requests, and simulating AXI memories for sim/debug purposes.

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 25, 2022, 01:53:00 am
content: Oh, well if you are a hobbyist or a student I guess the built in simulator is important.For serious project syou need a serious simulator. I have a Modelsim maintenance seat but I have let it lapse and will move over to ALDEC. Modelsim seems to have stood still for 15 years ....glen

author: asmi
author_rank: Super Contributor
timestamp: November 25, 2022, 02:32:00 am
content: Quote from: glenenglish on November 25, 2022, 01:53:00 amI'm both hobbyist and professional, and Vivado's simulator has been enough for me thus far. I guess real-time image/video processing and signal processing boards I've designed for my commercial customers are not serious enough to warrant "serious" simulator

author: Neilm
author_rank: Super Contributor
timestamp: November 25, 2022, 06:41:59 pm
content: Quote from: glenenglish on November 25, 2022, 12:34:13 amI have not noticed errors from other manufacturers in the past (Xilinx and Altera).Quote from: asmi on November 25, 2022, 01:32:21 amI have been using a free copy of Modelsim that came with Altera - it seems to work OK. Unfortunatly I am updating a design that didn't have any gate level simulaitons so who knows how well that would work.Was able to sort out the timing constraints reasonably easily - just have to get it in silicon and test it.Neil

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 25, 2022, 07:20:49 pm
content: Hi Neilno errors per say, but warnings certainly. (in cores).So, you got your timing stuff to close. I have not yet seen any high speed interface demo on efinix, lots of video centric stuff using the MIPI hard blocks which is a pretty much non event for timing since you connect it up externally and it works. I think the fastest I have seen is the RGMII 1Gbit interface on the eval board which unless you;ve being quite precise with the layout, you do need to ensure the clock is late. I've been using $1 RTL8211FS (because the usually suspects are unobtanium) and that's worked quite well but has no timing tweaks like the $10 TI device.actually I guess the 200 meg DDR HyperRam eval board interface is getting up there.like you say, the support is very good.Neil how fast are your interfaces ? source synch or async ? regards, glen.

author: AndyC_772
author_rank: Super Contributor
timestamp: November 25, 2022, 07:32:26 pm
content: Has anyone looked at the quality of the PLL clocks on a Trion device?Pk-to-pk jitter seems considerably worse than the data sheet spec, at least on my first board to ever use one. I'd like to know whether it's my layout, my test methodology, or the chip just not meeting the 200ps tOPJIT (PK - PK) spec.

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 25, 2022, 07:43:54 pm
content: Andy does the Trion config in your application use any sort of wacky divide ? I had a look at the Trion specs and it didnt qualify the measurement configuration.I would think you can get this looked at very quickly by the Efinix support/factory. Their online forum software setup needs a lift eh ? I've told them....I have some of these Ti180 devices.. logic cell, for the money they're monsters. The Sapphire RISCV custom instruction setup is useful and easy to use. Bit slower (clock and DMIPS) than my multicore A53s and R5s on the MPSoC , but I am used to MicroBlaze so similar ecosystem. glen

author: AndyC_772
author_rank: Super Contributor
timestamp: November 25, 2022, 07:53:26 pm
content: It's 16M in (which is nice and clean), x48 = 768M for the VCO, then /8 to give 96M out with about 600ps pk-pk jitter.

author: KE5FX
author_rank: Super Contributor
timestamp: November 25, 2022, 07:55:50 pm
content: Are these still fabbed at SMIC?

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 25, 2022, 08:53:40 pm
content: Andy, maybe for diagnostic, do your 96 meg generation on two PLLs in the device, bring them out through unrelated clock trees, to pins then into each side of a mixer and observe on a scope the result.... see if that helps you learn anything about behaviour.17 years ago I found any clock routed through fabric was hopelessly noisy for driving high speed DACs.HOWEVER ! - what you are seeing in jitter is ENORMOUS. 600ps ptp on 96 MHz severe.yes get onto factory support. If you have difficulty finding the right people I know someone.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 26, 2022, 05:32:37 am
content: Quote from: Neilm on November 25, 2022, 06:41:59 pmNot errors, but I just built basically trivial project for a xilinx FPGA (just a memory block attached to the zynq processor and a couple of IOs) and it produced over 600 warnings. Altera/Intel is the same way, they actually have a separate class of "critical warnings" that are not hard errors but warnings that maybe you should really pay attention to because normal warnings are so common in vendor code that they are not even worth looking at. It's maddening, and while I understand some of the reasons why it is different than the software world, but it's still embarrassing and frankly unacceptable, but it is also the reality of FPGA development.

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 26, 2022, 05:50:32 am
content: Hi ejyeah same with mpsoc etc /axi/amb connectors.anyway, so far, so good with Efinix.WHat can it do for me ? Well currently I seek to deal with the heat. it costs fancy metalwork to deal with the heat, and the completed Efinix design *will likely * be lower power, according to power estimator. about half !Still, what you pay for with Xilinx is the absolute benchmark superb quality of the documentation, tools and logicores. Unbeatable. (disclaimer I am a Xilinx alliance partner)Efinix device are low comparative cost, and the tool chain is improving quite quickly. and they seem to listen.It will take me a little while to go to being efficient and effective with high level language design which I will need on the Efinix. Fortunately, gates are cheap. How is it for getting timing closure on a external 64 lane wide 1200 Msps LVDS bus, I dunno yet.I used to use Microblaze alot. Then I got used to having an A53 core (admittidly running down at 600 megs) and 16 bits of DDR4 attached (600 meg clock) for an otherwise 2 Mbyte requirement.... and being rather haphazard with code efficiency, rooms for giant deug buffers, whole of program updating, etc (I use FreeRTOS+TCP) and having the neon cores if I wanted them- IE that much horsepower in hand gives me upgrade proof capability. At a heat and complexity cost. The MPSoC is a complex beast- not to be underestimated whatever your skill.Technique on the efinix will be more high level synthesised cores, and custom instructions on the 200 meg Sapphire RISC-V and 32 MB of HyperRAM. (200 megs is about what it will do with complex configuration) .My feeling is that I am abotu a year ahead from where I really want the Efinix toolchain to be in terms of performance/stability. But if you dont use it and dont push them, it will not advance...

author: AndyC_772
author_rank: Super Contributor
timestamp: November 28, 2022, 03:36:13 pm
content: Quote from: glenenglish on November 25, 2022, 08:53:40 pmThanks to Harald at Efinix (Europe) for help on this one. He suggested updating to the latest patch (3.17) which has some improvements in this area.He also mentioned that the jitter depends on VCO speed, so I tried reconfiguring the PLL to run the VCO as fast as possible.It's *much* better now

author: Someone
author_rank: Super Contributor
timestamp: November 28, 2022, 09:48:26 pm
content: Quote from: AndyC_772 on November 28, 2022, 03:36:13 pmPretty standard across all FPGA vendors.

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 29, 2022, 03:40:02 am
content: did you see NOV27 another patch out*** 2022.1.226.3.# patch notes--  Addresses functionality issues with PLL phase-shifted outputclocks and post divider = 1 PLL setting [PT-1695, PT-1207, SIP-264, DOC-1019, DOC-1026]--  Significantly increases F_VCO, F_PFD maximum frequencies for Trion PLLs (notincluding T4, T8F49 & T8F81 devices) [PT-1695, DOC-1026]--  Use classic router (same as used in Efinity 2021.2) by default--  Fixes small number of cases where global clocks incorrectly routededge destinations [VPR-1716]--  Fixes instantiation of DSP48 with different MODE values [SYN-632]--  Fixes functionality issue in certain DSP cascaded cases [SIP-252]-- Fixes issue where IP Manager mistakenly deletes Sapphire standalone applicationsfolder upon Sapphire IP regeneration [IPM-425]-- Fixes jtag_bridge read flash error on MX25L device [PROG-417]-- Fixes issue with programmer's JTAG clock speed control [PROG-411]

author: AndyC_772
author_rank: Super Contributor
timestamp: November 29, 2022, 07:19:28 am
content: Yes, that's v2022.1.226.3.17. Seems my support enquiry was timely...!

author: glenenglish
author_rank: Frequent Contributor
timestamp: November 29, 2022, 07:29:43 am
content: Efinix seems very good at listening.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 17, 2023, 03:07:21 pm
content: Bump for this thread now I'm working on another project...Has anyone seen any issues with temperature stability on Trion devices?My prototype is working fine on my bench, but falls over when I heat the FPGA with warm air. The underlying problem appears to be that data being clocked into a dual port FIFO is getting corrupted.Since both sides of the FIFO are clocked from the same PLL output, and all the data and control lines go into the rest of the FPGA core, there's not a great deal I can do w.r.t. timing margins. In any case, I expect the synthesis tool to take care of timing within the device fabric, and provided I keep within the reported Fmax, every chip should work across its entire rated temperature range. That is, after all, the entire purpose of the device timing model that's built into the synthesis tools for any FPGA.Slowing the design down won't work if the problem is a hold time violation, so although that might be a fix, it's not guaranteed.I've emailed Efinix support asking for help, but in the meantime, has anyone else encountered any such issues please?

author: glenenglish
author_rank: Frequent Contributor
timestamp: February 17, 2023, 08:23:40 pm
content: how fast are you talking ?what if you register the data each side ?almost like its being clocked on the wrong edge.... everything becomes hairy.

author: Someone
author_rank: Super Contributor
timestamp: February 17, 2023, 11:02:19 pm
content: Quote from: AndyC_772 on February 17, 2023, 03:07:21 pmObvious/stupid question, but is that instance set for Synchronous clocking?

author: AndyC_772
author_rank: Super Contributor
timestamp: March 01, 2023, 05:50:09 pm
content: Update... it wasn't the FIFO after all. Instead it was the SPI interface, which ironically is much slower. Set up on falling edges, sample on rising, so it should 'just work' provided the clock isn't too fast - except it was.It turns out there are significant differences in the delays getting signals on and off the chip, depending on which pins are used for the clock and/or where the output signal is registered.I gained about 5ns of additional setup time at the CPU by registering MISO in the I/O ring of the Efinix FPGA, and moving the SPI clock to one of the pins that supports the GCLK input type. You have to do this in order for the clock to be available to the registers in the I/O ring; they can't accept a clock from just anywhere.I know it's early days and I'm still learning, but it's also quite apparent that there are hardware limitations in the Efinix architecture compared to the Altera parts I've been using for many years. The separate I/O ring is a PITA, frankly, and I can't help but feel that such a new device architecture should have fewer limitations, not more, compared to one that's been around since 2009 (Cyclone IV).Although I/O pins can just be configured as transparent, there's significant propagation delay through the ring which means it may be necessary to modify the core logic and use the registers in the I/O ring instead just to meet timing. Portability definitely takes a hit; my VHDL code is now logically different from how it was before, and no longer describes the behaviour of the physical device in full.It's not entirely clear whether the clear distinction between the core logic and the I/O ring is truly architectural (ie. the chip itself is physically different from other FPGAs in this respect), or whether it's a software thing. Why should the synthesis tool NOT be able to see that a logic output is registered, and make use of the register physically located in the I/O ring? Why would the option even exist to register it in the core, then add the delay through an I/O buffer configured to transparent mode?Waiting patiently (ish) for a new version of the Efinity tool chain to get a tick box for "configure I/O clocks & registers automatically to make best use of them given the design of the core logic".

author: glenenglish
author_rank: Frequent Contributor
timestamp: March 01, 2023, 10:22:06 pm
content: Hi Andyreally good comment , well writtenI have pinged my Efinix FAE on this with your message referenced.It really does affect portability. The tool CAN know, it has all the information to know this.-glen