Looking for Help with CPLD and Quartus II - Page 1
Forum section: electronics / general

author: MatCat
author_rank: Frequent Contributor
timestamp: April 14, 2014, 07:42:20 am
content: I am trying to experiment with CPLDs, and in-fact have a potential use for one that I have been testing in the sim, now my next step was to see exactly how many LE's it would take for my design and figure out how pin assignments work, but for the life of me I cannot figure out how it works. My project just consists of a singular .v file for the verilog, if I go to the pin editor I can see the pins graphically layed out according the the chip I want to use, but I have no idea how to assign them or use them, any help would be greatly appreciated.

author: miguelvp
author_rank: Super Contributor
timestamp: April 14, 2014, 07:58:12 am
content: All you need (and it will take a while to learn) is in here:http://www.altera.com/education/training/curriculum/cpld/trn-cpld.htmlI'm on the fpga front so I'm using:http://www.altera.com/education/training/curriculum/fpga/trn-fpga.htmlBut it should be similar.

author: jahonen
author_rank: Super Contributor
timestamp: April 14, 2014, 08:02:21 am
content: Have you compiled your design for the chip you are planning to use? After successful compilation, the pin planner should provide a list of assignable pins in bottom of the pin planner window. Then simply type the desired pin number for each pin into "Location" column.Although you could enter the pin assignments beforehand by adding node names manually, it is usually better to see first where fitter likes to put them. Then you can either back-annotate the fitter selections or assign different pin.Regards,Janne

author: MatCat
author_rank: Frequent Contributor
timestamp: April 14, 2014, 08:57:40 am
content: Quote from: jahonen on April 14, 2014, 08:02:21 amI see what was happening, the module I used as my testbench module I modified it for compile test but I failed since it contained no actual logic methods so I couldn't compile. I think I have an idea now of how this all works.

author: MatCat
author_rank: Frequent Contributor
timestamp: April 14, 2014, 08:57:55 am
content: Quote from: miguelvp on April 14, 2014, 07:58:12 amI will take a look at that, thanks!

author: MatCat
author_rank: Frequent Contributor
timestamp: April 14, 2014, 08:01:35 pm
content: Ok so I am at another brick wall, I am now trying to do a simple PWM Driver (not completed yet, will eventually have multiple PWM outputs), I have a PWM module, a shift register input for serial data, and a top level to tie it all together, problem is when I try to compile it I get the design does not contain any logic, no errors or warnings otherwise other then the fact that I have no license for parallel compiling, why?Code:module PWMMAIN;reg sclk;reg clk;reg latch;reg sdata;reg reset;wire p0out;reg [11:0] p0data;wire [5:0] pwmAddr;wire [11:0] pwmData;PWM p0 (.clk (clk),.reset (reset),.data (p0data),.out (p0out));SHIFTIN sd (.sclk (sclk), .latch (latch),.data (sdata), .addr (pwmAddr),.data_out (pwmData));always @(posedge latch)p0data <= pwmData;endmodulemodule PWM(clk,reset,data,out);input clk;input reset;input [11:0] data;output out;reg out;reg [11:0] pwmclk;always @(posedge clk)if (reset) beginpwmclk <= 12'b0;end else beginif (pwmclk < data) beginout <= 1;end else beginout <= 0;endpwmclk <= pwmclk + 1'b1;endendmodulemodule SHIFTIN(sclk,latch,data,addr,data_out);input sclk;input latch;input data;output [11:0] data_out;output [5:0] addr;reg [5:0] bitCount;reg [5:0] addr;reg [11:0] data_out;always @(posedge sclk or posedge latch)if (latch) beginbitCount <= 0;end else beginif (bitCount < 5) begin// Addressaddr <= addr << 1;addr <= data;end else begin// Datadata_out <= data_out << 1;data_out <= data;endbitCount <= bitCount + 1'b1;endendmodule

author: marshallh
author_rank: Unknown
timestamp: April 14, 2014, 10:55:54 pm
content: On the very first line you have instantiated a new module except with no i/o -- you forgot the parentheses. So it thinks your toplevel is completely empty.

author: MatCat
author_rank: Frequent Contributor
timestamp: April 15, 2014, 12:59:55 am
content: Quote from: marshallh on April 14, 2014, 10:55:54 pmYep, all of the examples I have been reading on the internet use sim and the top level never has I/O in that case (testbench), putting proper I/O did fix it.

author: ktulu
author_rank: Regular Contributor
timestamp: September 13, 2017, 10:18:59 am
content: Hi.I'm trying to read back a MaxII EMP570 with QuartusII and ByteblasterMV.I attach the resulting .pof file.The entire CFM region is all 0's. Interestingly the security bit is not checked in QuartusII programmer after executing a read.Can somebody tell me what is the cause?I'm guessing it is code protected. Is there any way to verify this, and tell for sure?(I've tried many different versions of QuartusII btw.)Thanks.

author: ktulu
author_rank: Regular Contributor
timestamp: September 13, 2017, 06:27:03 pm
content: If I try to verify, it always fails at 7% (right after an examine)Any idea?