68k-MBC: a 3 IC easy to build 68008 SBC running CP/M-68K - Page 1
Forum section: electronics / general

author: Just4Fun
author_rank: Contributor
timestamp: April 21, 2021, 09:28:58 am
content: Hi all,I've done an easy to build SBC with a 68008 CPU.Two HW options available: Lite and Full. Lite allows to build a 3 ICs 68008 system running CP/M-68K.Here the 68k-MBC hardware main specs:68008 CPU running at 8MHz;multi-boot capability;two main HW configuration options: Lite or Full. Lite HW configuration option allows to build a minimal 3 ICs 68008 system;RAM can be configured as 128/512/1024KB (1024KB supported on the Full HW configuration option only);optional RTC and microSD (16 HD emulation) modules (the same used in the Z80-MBC2);optional 16x GPIO port;I2C expansion port;2 serial ports (Serial Port 2 supported on the Full HW configuration option only) ;on board RS232 drivers for both the two serial ports (Full HW configuration option only);serial-USB adapter support on the Serial Port 2 with independent power supply (Full HW configuration option only);User led and key;ICSP connector (for the PIC18F47Q10) for an easy firmware installation/upgrade;it is compatible with the uTerm (https://hackaday.io/project/165325) and uCom (https://hackaday.io/project/165709) add-on boards.If anyone is interested all the details arein this page.Regards.J4F

author: woofy
author_rank: Frequent Contributor
timestamp: April 21, 2021, 03:37:24 pm
content: Very nice.The 68k is not a processor I've ever plated with, though I've certainly looked at it over the years. I may build one one day.Well done.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 21, 2021, 04:25:24 pm
content: Interesting, and a good illustration of why Sinclair chose the 68008 for the QL.

author: saipan59
author_rank: Contributor
timestamp: April 22, 2021, 05:45:42 pm
content: Nice project! A question:I have considered doing something similar. I see that the PIC you chose actually operates at 5V (not just "5V tolerant").What about using an MCU that runs from 3.3V, but has "5v tolerant" GPIOs? Is it feasible? Can 3.3V signals drive an NMOS input? I looked at my favorite part, the DEC T-11, and it appears to be OK, but I haven't tried it. It seems that Vih-minimum is typically 2.0V for these older parts.My interest would be to use a board like this, which provides a fairly high-performance MCU, with a USB programmer, and 0.1" header pins, for $13. This part is "5V tolerant", but runs at 3.3V. I have a variety of these T.I. boards on many projects.https://www.ti.com/tool/EK-TM4C123GXL?utm_source=google&utm_medium=cpc&utm_campaign=epd-null-amcu-TM4C123g-cpc-evm-google-wwe&utm_content=TM4C123g&ds_k=tm4c123g+launchpad&DCM=yes&gclid=Cj0KCQjwvYSEBhDjARIsAJMn0ljCPUTBd_9d2xfnERhc4WU-5495RXEnB6x7ntaOwK6LhGrmqydFaA8aArt0EALw_wcB&gclsrc=aw.dsPete

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 22, 2021, 06:00:49 pm
content: Quote from: saipan59 on April 22, 2021, 05:45:42 pmI just checked in the 68k datasheet:* Safety-wise, 5-V tolerant inputs will be fine for the CPU -> MCU direction, but beware the maximum "Output Low Voltage" of a 68k is 0.5V. Check that it's ok with the MCU you select (it should be).* For the MCU -> CPU direction, the minimum "Input High Voltage" is spec'ed at 2.0V (for Vcc = 5V), so this should work fine without any level shifter.

author: saipan59
author_rank: Contributor
timestamp: April 22, 2021, 07:25:29 pm
content: Looking at your schematic, I only see 3 address lines connected to the PIC.Am I missing something?I would be interested in a brief description of how the PIC firmware handles the interface with the 68008. For example, how are bus transactions detected?Thanks!Pete

author: saipan59
author_rank: Contributor
timestamp: April 22, 2021, 08:04:15 pm
content: Um, I'm (maybe) starting to understand how it works. How about this:- At startup, the PIC already "knows" what addresses are being fetched, so it can feed the 68k opcodes in a certain order. A "real" address bus is not required!- The boot code is very deterministic - no decision-branches that would require a "real" address bus.- The boot code pokes bytes into RAM.- Eventually, execution starts (or re-starts) from RAM...Very clever!I'm still not sure I see how I/O is handled through the PIC, with only 8 "real" addresses to work with.Pete

author: ledtester
author_rank: Super Contributor
timestamp: April 23, 2021, 07:35:59 am
content: QuoteIn main.c around line 1000 I found code implementing a virtual I/O engine based at address 0xFFFFC.In the schematic AND gates U2A and U2B decode the top 6 address lines into signal -IO/M connected to GPIO pin RA3, so I'm sure this is used to detect access to the virtual engine.Update: Found that the virtual engine loop starts at line 875. Seems that first an "opcode" byte is written to a virtual engine address and then the CPU is expected to read/write additional data bytes from/to the engine to complete the I/O operation.

author: Just4Fun
author_rank: Contributor
timestamp: April 23, 2021, 08:17:52 am
content: Quote from: saipan59 on April 22, 2021, 07:25:29 pmHi,only two address lines (A1 and A0) are used, so you have 4 real I/O addresses. This allows to save MCU GPIO pins.To allow more selections, an Opcodes "strategy" has been implemented.The Opcodes are atomic operations that can be done by the CPU as "Virtual HW registers" managed by the FW inside the PIC.With the Opcodes you have a "two stages" I/O operation, so at first you write the opcode wanted into the Opcode "register" (i.e. send a character to the serial port 2) and then make the data exchange writing (or reading) into the "Execute Opcode" register (can be a multi-byte operation as in the Virtual Disk Opcodes).The memory mapped I/O address space depends on the HW configuration option that has been implemented (between Full or Lite).In the Lite HW configuration option only the A19 is used to "switch" between the memory and I/O addresses, while in the Full HW option A15 to A19 are"sensed" to select a 16KB I/O area.This seemed to me a good trade off between HW implementation and address space "consumption".In any case only 4 I/O addresses are recognised, and are "mirrored" in all the remaining I/O address space.The IO#/M signal is used to detect the I/O address space (see schematic) and this signal is an input of an internal logic function made with two CLC modules (a sort of LUT of a CPLD) inside the PIC to "stop" the CPU deselecting the DTACK signal (CLC generated).This gives the time to the PIC to interface the CPU bus for the needed operation. The DS# and R/W# signals are used to recognise the bus operation (together with the INTA signal).On the bus a combination of DTACK + HALT signals is used to avoid data clash, and this is the "heart" of the "virtual engine" of the FW inside the PIC.The logic function inside the CLC is "dynamic" as it changes depending by which one between the Full or Lite HW option is implemented.The FW can recognise it and changes the logic function at first as some signals work inverted in the Lite HW option.Regards.J4F

author: Just4Fun
author_rank: Contributor
timestamp: April 23, 2021, 09:13:50 am
content: Quote from: saipan59 on April 22, 2021, 05:45:42 pmHi,in a previous board (V20-MBC) during the first phase I've done a prototype on a breadboard using a STM32F030 custom board to interface it with a V20 CPU bus @ 5V (as I've done here with the PIC).The STM32 runs at 3.3V but has a lot of 5V tolerant GPIO pins (fully TTL compatible), and the breadboard prototype worked perfectly:So if your MCU has 5V tolerant pins that are TTL compatible you can do it for sure!BTW: I've a soviet PDP11 clone CPU too, and I'll use it in the next for sure...

author: woofy
author_rank: Frequent Contributor
timestamp: May 12, 2021, 05:11:07 pm
content: I like this project and as I've never played with the MC68008, I decided to build one. It works fine.JLCPCB had an MOQ of 5 boards, so I have 4 left over.If anyone wants one, drop me a PM with your name, address and a promise to donate something to your favourite charity, and I'll pop one in the post.But please, only if you really are going to build it, and UK only please.First come, first served.