hybridfree/eevblog-posts huggingface dataset:
low-jitter timing generation using FPGA - Page 1
Forum section: electronics / general

author: bonelli
author_rank: Contributor
timestamp: March 15, 2022, 05:16:01 pm
content: Hello,I'm trying to generate accurate timings using a FPGA, I'm looking for something like that:- 3.3V input trigger (SMA connector, 50 ohm matched)- 2 outputs, respectively delayed with T1/T2 from the rising edge of the trigger- A serial port to set T1/T2- A 10MHz TCXO as stable and accurate clock source- Ideally, (T2-T1), T1 and T2 range from 1ns to µsecs, with ns resolution and <200ps jitterBasically, I have implemented 2 counters, one for each output. I have 2 cascaded flip-flop to resync the input trigger to the local clock, meaning 2Tcy of jitter. Using a 500MHz clock, the resulting jitter is 4ns, very bad for my application. The 500MHz comes from the PLL of the FPGA, clocked with the 10MHz TCXO.I'm planning to use all 4 phase-shifted outputs of the PLL, clocking 4 implementations of my counters, to reduce the jitter to 1ns (still bad but better). For each output, I suppose I can OR the output of each phase-delayed counter (using pure combinational circuits).If the FPGA has multiples PLL, I suppose I can use them all to play with delays and clock more than 4 counters.But is this approach good? To keep synchronization to the clock (excluding combinational delay loops), I don't see any other way to do the job.Any advice and ideas appreciatedMany thanks

author: RoGeorge
author_rank: Super Contributor
timestamp: March 15, 2022, 06:47:15 pm
content: I'll be tempted to use tapped delay lines. Googled for "FPGA ns programmable delay", didn't went into detailed reading, but by their specs the papers seem applicable. See if any of these design ideas applies to your application:A programmable delay lineTime Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time CalibrationA high-resolution programmable Vernier delay generator based on carry chains in FPGANon-blocking programmable delay line with minimal dead time and tens ofpicoseconds jitter

author: BrianHG
author_rank: Super Contributor
timestamp: March 15, 2022, 07:42:19 pm
content: Quote from: bonelli on March 15, 2022, 05:16:01 pmYou should be achieving 2ns jitter. If you use a DDR output, sampling your input trigger with a DDR input and storing which clk phase the transition came in on, and using that phase as a reference when driving your DDR output, you should achieve 1ns jitter. IE: only 1 counter needed, you just need to store which internal CLK phase the source trigger came in on to know which phase you want to drive the output on.Using LVDS multi-GHZ receivers and transmitters doing the same trick, but x# of bits wide, you can further refine that bleeding edge jitter down to 200ps with 5GHz transceivers.The other choice is using separate external true VCXOs. TI has their CDCE9xx series VCXO programable PLL clock generators which run from a single crystal. Though a mess of parts and wiring for multiple channels, you can potentially get down to below 200ps refinement without such fast PLD IOs.
PALCE programming algorithm - Page 1
Forum section: electronics / general

author: TomS_
author_rank: Frequent Contributor
timestamp: March 09, 2022, 02:52:26 pm
content: Hi all,Would anyone happen to know whether PALCE devices use the same programming algorithm as GAL devices, or if they are completely different?Thanks

author: Beta_vulgaris
author_rank: Regular Contributor
timestamp: March 10, 2022, 10:41:01 am
content: With some similarities, all of them require high voltage ("programming voltage") on one or more of input-only pins. But the detailed algorithm may be completely different. Here are GAL22V10 (EEPROM) and PALC22V10 (UV EPROM) diagrams:
Interfacing LVDS laptop screen with fpga - Page 1
Forum section: electronics / general

author: Lopfi
author_rank: Newbie
timestamp: February 17, 2022, 10:43:37 am
content: I have a few old laptops of the same model and wanted to try to show something on the screen(datasheet attached) without the laptop hardware and play around a little bit with fpgas. But after reading a bit about LVDS something stood out to me. The mentions the LVDScommon voltage of the screen to be 1.25V but all FPGAs and even most IC's use 1.8V or higher for LVDS. So am I missing something or is this just a weird voltage to use with LVDS? And if so do you know any FPGAs or IC's I could use to interface with the screen?

author: mon2
author_rank: Frequent Contributor
timestamp: February 17, 2022, 11:22:09 am
content: I have trained with Bolo Yeung. Using my black belt in Google-fu:https://community.element14.com/products/devtools/avnetboardscommunity/b/blog/posts/driving-a-laptop-lcd-using-an-fpga

author: mascotte
author_rank: Newbie
timestamp: March 08, 2022, 09:07:10 am
content: Common mode of LVDS is always 1.25V, this is specified in the corresponding standard. What you think of is the bank voltage of the FPGA, some have LVDS IOs that can be powered e.g. with 1.8V, 2.5V, 3.3V, but nevertheless they will output a common mode of 1.25V.
Fpga verification when to do - Page 1
Forum section: electronics / general

author: rakeshm55
author_rank: Regular Contributor
timestamp: February 18, 2022, 05:18:12 pm
content: Hi,When should one consider verification for FPGA designs. In order to vet an FPGA design do we need to show verification docs or will simulation results do.What is the investment one should make inorder to setup infrastructure or FPGA verification?Does xilinx toolchain has packages that are geared for verification

author: laugensalm
author_rank: Regular Contributor
timestamp: February 20, 2022, 08:40:33 am
content: You might want to check the yosys verification pool of tools for your needs. It really depends on your architecture, language used, design rules, etc. Therefore it's hard to make a general statement. The Xilinx tools can't help you there, in fact they're quite a mess when it comes to VHDL standards.There's a lot of noise made on formal verification, however in reality it turned out for me that the test bench needs to be thoroughly designed (in neither of the V* HDLs). Eventually, what I had to deal with was: static code checks (design rules met), glitch checks on clock domain crossings (one hot/cold flip per event), coverage (all input vectors yield a defined result, no dangling blind states in FSMs, etc).Some Python HDL approaches help with verification while you develop code. But this is an extensive topic we better not open here.

author: nvmR
author_rank: Regular Contributor
timestamp: February 20, 2022, 11:53:32 am
content: It really depends on what you are trying to achieve.Sometimes, verification is good when you have a complex black box in your design you would like to check - and you can fairly simply write a model of it. Afterwards, you can plan different tests and arrive at code coverage of the verification.In other cases though, you might want to check an entire system - in a validation mindset, where you would like to treat your entire system as a black box, and check it electrically and behaviorally. This is more automation than verification.Both of these vector - verification of FPGA code, and system validation are mainly relevant for "breathing" projects where features are added and tested.
Intel/Altera FPGA board with HSMC 1.8V - Page 1
Forum section: electronics / general

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: February 18, 2022, 06:59:29 am
content: Fellow GeeksDo you know any Intel based FPGA boards with HSMC connector (1.8V compatible) which can be bought for about < $300.The FPGA need not be very high end. The low end Cyclone series is good enough.The objective is to test out some digital signals on the HSMC connector for functionality. eg. SPI, UART etc.Cost and availability are the key concerns here.

author: Wiljan
author_rank: Regular Contributor
timestamp: February 18, 2022, 09:34:21 am
content: I have this one which support 1.8V, but it's not in stock SoCKit - the Development Kit for New SoC Devicehttps://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=816I did a search on Ebay to see if one was for sale but found this one DE10-Standardhttps://www.ebay.com/itm/224835409928?hash=item34593c1808:g:asoAAOSw-pJiCg8pakahttps://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1081It's actually in stoc and if you are Academic it's $340 but the one on Ebay you might get cheaperOne HSMC Connector(Configurable I/O Standards 1.5/1.8/2.5/3.3V)

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: February 18, 2022, 11:02:40 am
content: Quote from: Wiljan on February 18, 2022, 09:34:21 amMany thanks.. The Terasic one just seems to fit the bill although a bit pricey.

author: saresigi
author_rank: Contributor
timestamp: February 20, 2022, 12:23:48 am
content: Did you know this one:https://www.ebay-kleinanzeigen.de/s-anzeige/cyclone-iii-fpga-starter-board/2009426148-168-7403orthis one:https://www.ebay-kleinanzeigen.de/s-anzeige/terasic-altera-nios-ii-embedded-evaluation-kit-cyclone-iii-/2009400518-168-7403

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: March 02, 2022, 12:56:23 pm
content: Quote from: saresigi on February 20, 2022, 12:23:48 amLooks like they stopped manufacturing those and made them obsolete. I would stick with something which is actively made, so don't run into long lead times.
Gowin FPGAs: What is equivalent of "AXI Bus" (Xilinx) in Gowin's IP Cores - Page 1
Forum section: electronics / general

author: FlyingDutch
author_rank: Regular Contributor
timestamp: February 10, 2022, 04:06:40 pm
content: Hello Forum,I just get the "Sipeed Lichee Tang Nano 4K Gowin" from AliExpress - see product page:https://www.aliexpress.com/item/1005003630533312.html?gatewayAdapt=glo2pol&spm=a2g0o.9042311.0.0.40445c0fFJV8ISEarlier I try a little project "Breakout" game, of earlier version of "Sipeed Lichee Tang Nano 1K", so I became a bit familiar with Gowin synthesis software called "Gowin EDA". I am familiar with "Xilinx Vivado" software and their "AXI" bus (memory mapped and stream versions). The :"AXI" bus is standard for interconnecting Xilinx IP Cores on "Block Desing" tools of "Vivado".Now I would like to connect I2C ADC (Analog 2 Digital Converter) to "Sipeed Lichee Tang Nano 4K" FPGA board, then make FFT on data from ADC and send the FFT data to MCU for displaying. I found IP Cores in "Gowin EDA" for implementing I2C controller and FFT. There is one issue I don't know if there is a standard bus for interconnecting Gowin IP Cores. The best if it would be an counterpart of "AXI Stream" interface in Gowin Eda.Could somebody give me a clue in this subject?Thanks in advance and Regards

author: nctnico
author_rank: Super Contributor
timestamp: February 10, 2022, 05:07:38 pm
content: Al alternative is to use the (open source) Wishbone bus.https://en.wikipedia.org/wiki/Wishbone_(computer_bus)

author: FlyingDutch
author_rank: Regular Contributor
timestamp: February 10, 2022, 05:50:18 pm
content: Hello @nctnico,I know that open-source IP Cores are using Wishbone bus, but Gowin IP Cores don't use it. I would like to use Gowin IP Cores because them are optimized for Gowin FPGAs hardware (especialyy the FFT IP Core). So in this case I rather not would like to use open-source IP Cores. But thanks for an answerBest Regards

author: nctnico
author_rank: Super Contributor
timestamp: February 10, 2022, 06:32:13 pm
content: I see an AHB bus arbiter in the core generator so appearantly Gowin seems to like the AHB bus.

author: FlyingDutch
author_rank: Regular Contributor
timestamp: February 11, 2022, 06:52:32 am
content: Quote from: nctnico on February 10, 2022, 06:32:13 pmHello,yes I also saw the "AHB Bus Arbiter" in Gowin IP Cores - I have to take a closer look at this subject.Thanks and Regards

author: dawnclaude
author_rank: Contributor
timestamp: February 11, 2022, 07:58:26 am
content: I have used the I2C core and it had a generic dual port RAM interface. You configure the IP registers using address and data bus. One port is for reading and the other for writing
PCB design for FPGA DDR4 - Looking for books for novice on SI/PI - Page 1
Forum section: electronics / general

author: rdpdo
author_rank: Contributor
timestamp: February 10, 2022, 07:55:57 am
content: Hello,I have a project to create a board with FPGA DDR4 but I know nothing about signal integrity for PCB design and the use of software like cadence SI, ADS from keysight and other...Do you have some reference of book to read to understand the concept of signal integrity studie in the case of PCB with FPGA and DDR4 ?Thanks a lot !
ModelSim "soft pathnames" and MGC_LOCATION_MAP - Page 1
Forum section: electronics / general

author: Bassman59
author_rank: Super Contributor
timestamp: January 28, 2022, 04:06:05 pm
content: Has anyone ever used this feature on Windows?I'm working from home for a bit and all of my ModelSim projects are broken because they have hard absolute paths.The project setting "Location map -- convert pathnames to softnames" requires an environment variable MGC_LOCATION_MAP, but there's no useful documentation from Mentor about how to set this.Ideally, of course, the map would be to a location relative to the project file's directory. That is, given a tree:project root \\src\tb\fitterand the ModelSim project file lives intb.Ideally, the path to the sources would be ..\src and the path to test benches would be in ..\tb which is referencing tb but that's OK.

author: Bassman59
author_rank: Super Contributor
timestamp: January 28, 2022, 04:21:36 pm
content: replying to myself:This feature is stupid.If you do NOT check the "convert pathnames to softnames" box, then your MPF can have relative paths that will not get converted to an absolute path. The environment variable doesn't matter.The problem is that when you add files to the project, they are added with an absolute path, so you have to go in and manually edit the MPF to change the paths to relative.I guess the design decisions they made back in 1990 or whenever are still paying dividends!

author: Daixiwen
author_rank: Frequent Contributor
timestamp: January 31, 2022, 09:11:12 am
content: I stopped creating projects in Modelsim when I discoveredVUnit. If you can spare a few days to become familiar with it you will save a lot of time in the long run. You create your project files in Python, with all the power of the language for automatic absolute/relative path finding, and you can include files with wildcards. VUnit automatically makes a dependency tree from your source code and only recompiles the files that need recompiling. It automatically finds your testbenches, and you can write them so that each test can be individually run during a test or not.If you combine this with an add-on such as TerosHDL in Visual Studio Code, you can run each test directly without leaving the editor and without even needing to open Modelsim.

author: Bassman59
author_rank: Super Contributor
timestamp: January 31, 2022, 07:29:11 pm
content: Quote from: Daixiwen on January 31, 2022, 09:11:12 amThanks! I just installed it, now to find those few days to spare on a small project so I can wrap my head around it.ModelSim's UI is so long in the tooth it's unbelievable.
ATF22v10b outputs oscillate - Page 1
Forum section: electronics / general

author: c64
author_rank: Frequent Contributor
timestamp: January 20, 2022, 05:34:13 am
content: I programmed few of them and they all have same strange behavior. I have test PCB to test if they work correctly. No long wires, traces ~5cm long, solid ground, 4 layers, decoupling. After switching inputs for few seconds some outputs suddenly start oscillating in the range 3-5v at about 400kHz. Well, technically it's withing TTL levels but still strangePart number is ATF22V10BQL in PLCC package. I program them using arduino/afterburner. I did conditioning (writing all 0) before programming.

author: Beta_vulgaris
author_rank: Regular Contributor
timestamp: January 20, 2022, 07:36:19 am
content: Pin 4 (DIP, PLCC pin 5) Power Down not disabled?

author: c64
author_rank: Frequent Contributor
timestamp: January 21, 2022, 03:29:54 am
content: It doesn't have power down pin. Power down is automatic and can not be disabled (AFAIK)
Anyone ever come across AnDAPT PMICs? - Page 1
Forum section: electronics / general

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: January 20, 2022, 11:21:17 pm
content: I only heard of them today, they do PMICs for FPGAs:https://www.andapt.com/pmic-solutions/

author: jayk
author_rank: Regular Contributor
timestamp: January 21, 2022, 02:57:13 am
content: Pretty cool on-line config tool for Xilinx and Microchip - has a bunch of devices along with voltages, currents and sequencing and generates a schematic/bom/config file you can download.Do these have on-chip EEPROM to store the config or do you have load them at power-on?I can't tell if they support multiple phases for higher currents (say >= 50A).
FPGA Benchmarking - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: January 07, 2022, 02:43:11 pm
content: I want to create a bunch on bench-marking RTL designs for testing different FPGA technologies.This includes DSP, LUTs, DFF, memory..etc.Currently, I see many tests using adders, multipliers, standard algorithms to compare different FPGAs.I'd like to have a test that includes PLL, memory speed, routing delay time (oscillator ring with frequency counter inside the design).I see this type of work done in academia but nothing is readily available.I had the thought to cobble together some IPs from FuseSoC as a basis for such benchmark circuits.Any thoughts?Does anyone know if these already exist?

author: pbernardi
author_rank: Contributor
timestamp: January 07, 2022, 08:55:29 pm
content: Benchmarking does not make sense for FPGA. You can just check the timings for target device at datasheet and compare.Benchmarking is more a CPU thing, where you have many different architectures which cannot be compared directly - in most cases, CPU are seen as black-boxes. But for FPGA, you can just compare the max. speed for a given block, as DSP/BRAM/LUT, for example.A FPGA benchmarking can be created, of course. If well done, it should just give the expected result from device datasheet.

author: Gribo
author_rank: Frequent Contributor
timestamp: January 18, 2022, 08:02:04 pm
content: It makes sense if other parameters are included.For example,For a specific FIFO (Insert your favorite standard) implementation, what is the % of resources utilized in a 10$ part from a specific series, at which fMax etc.

author: asmi
author_rank: Super Contributor
timestamp: January 18, 2022, 08:08:59 pm
content: Quote from: Gribo on January 18, 2022, 08:02:04 pmMost modern FPGAs have hardware FIFOs, so no coding required. But even if they didn't, it would be testing mostly synthesis, place&route as opposed to actual device. Infact you won't even need to have a device in hand, because if P&R says a design can reach certain frequency, it will reach it for sure. Testing resources utilized is also difficult because not all devices have the same base block designs - for example, Lattice and Antel's Cyclone 4-5 parts have LUT4 blocks, while Xilinx 7 series have LUT6 (which can be configured to work as two LUT5's), the latter allows packing more logic into the same amount of base blocks.
ABEL to VHLD conversion - Page 1
Forum section: electronics / general

author: Ribster
author_rank: Frequent Contributor
timestamp: January 15, 2022, 08:20:11 pm
content: Hi all,I have a design that needs to be ported to a modern FPGA.The hardware design is done and i can program the new FPGA.The old code however is written in ABEL and used ispLever.With some research i'm feeling that ABEL to VHDL conversion is not quite possible through a conversion tool ?Anyone has got any experience on the lattice platform of converting this ?Kind regards

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 15, 2022, 08:24:17 pm
content: Typical stuff written in ABEL was rarely very big. Shouldn't take a lot of time translating this manually, even if just using low-level constructs in VHDL. So how large could have your code been?

author: Bassman59
author_rank: Super Contributor
timestamp: January 15, 2022, 08:50:15 pm
content: Do it by hand.And remember that VHDL has many constructs that ABEL didn't, for example numbers for counters and the like. Your translated code will likely be simpler and easier to understand!

author: nctnico
author_rank: Super Contributor
timestamp: January 16, 2022, 05:24:27 pm
content: Quote from: Bassman59 on January 15, 2022, 08:50:15 pmBut it will have to be re-validated (tested) from A to Z.

author: Bassman59
author_rank: Super Contributor
timestamp: January 17, 2022, 12:47:58 am
content: Quote from: nctnico on January 16, 2022, 05:24:27 pmYou have to do that with an automated conversion too.
simulation in gowin fpga designer - Page 1
Forum section: electronics / general

author: mozhgan
author_rank: Newbie
timestamp: January 08, 2022, 07:08:57 am
content: helloI want to simulation with gowin fpga designer and write test bench, but There is no simulation option in the tools menu.How can I simulate with gowin fpga designer?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 09, 2022, 08:14:43 am
content: Currently there is no simulation for their IP, But you can simulate normal HDL with modelsim. sadly they do not bother with that

author: mozhgan
author_rank: Newbie
timestamp: January 09, 2022, 04:36:51 pm
content: Thank you.Why in the software learning documents there is a simulation option in the tool menu but this option (simulation option) is not in the software I installed?can modelsim be invoked from gowin fpga designer ?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 10, 2022, 09:43:18 am
content: No, But if you found something please let me know too.
Sipeed Spartan Edge Accelerator Board and HDMI output - Page 1
Forum section: electronics / general

author: davorin
author_rank: Unknown
timestamp: November 17, 2021, 12:41:52 pm
content: Good afternoon (o;I was (and not only me) surprised that the Digilent Artix-7 board could do FullHD HDMI output..so I thought I give another board a go..well..basically two boards...First one being the Spartan-7 starter kit from QMTech from Aliexpress....and then discovered that Digikey sells those Spartan Edge accelerator boards with a XC7S15, ESP32 and a mini HDMI connector...So modified the QMTech HDMI example a little (different sysclk) et violà....getting FullHD output as well on this board :-)Next compiling some ESPHome example to display smart home values onto my HDMI monitor (o;Digikey part number: 1597-102030005-ND

author: x86guru
author_rank: Regular Contributor
timestamp: December 16, 2021, 06:08:33 pm
content: The QMTech Spartan-7 board is great. I got one last month for only $29 from AliExpress. The QMTech board also has onboard 256MB (2Gbit x16) DDR3-1600 as a framebuffer to play with...

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 16, 2021, 06:19:13 pm
content: This QMTech Spartan-7 board doesn't seem to be available anymore.

author: x86guru
author_rank: Regular Contributor
timestamp: December 16, 2021, 11:18:13 pm
content: Quote from: SiliconWizard on December 16, 2021, 06:19:13 pmMaybe not available temporarily... It's still listed on their website with the download for examples/documentation/etc:It's the top left board here:http://www.chinaqmtech.com/download_fpga

author: davorin
author_rank: Unknown
timestamp: December 17, 2021, 06:39:54 am
content: Well I see jsut one being left atm...so hurry (o;You may have to check back at their shop site from time to time...also one month ago they didn't have a Kintex board...now there is one available...Or go with the Sipeed Spartan accelerator board..62 pcs left @Digikey...This is their Github:https://github.com/ChinaQMTECH
How to solve this FPGA Problem from Embedded SoPC Design with Nios II Processor  - Page 1
Forum section: electronics / general

author: polarKaung
author_rank: Contributor
timestamp: December 24, 2021, 03:24:05 pm
content: How do i solve this problem. I can write a basic floating point header with these steps: sort, align, add, and normalize. But i am having trouble adding rounding feature. I do know how the general rounding works. But, not in VHDL.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: January 04, 2022, 10:35:57 am
content: Is this an assignment you have? Why don't you show us the code you have written so far and the exact trouble that you have?If it's not an assignment and you just need to do floating point operations in an FPGA, Quartus can generate IP blocks that do all the operations for you and fine tune them to your requirements. Just open the Megawizard.
Searching for Quartus 14.0 installer [solved] - Page 1
Forum section: electronics / general

author: voltsandjolts
author_rank: Unknown
timestamp: January 09, 2022, 01:44:09 pm
content: Anyone got a Quartus 14.0 (or perhaps slightly older version) installer they could share, preferably for windows?Version 14.1 and up have some free IP removed (e.g.altmemphy).Version slightly older than 14.0 would probably be OK too.Intel only provides 17.0 and up.

author: voltsandjolts
author_rank: Unknown
timestamp: January 09, 2022, 02:37:05 pm
content: Thanks but no luck.I see the link for "Intel® Quartus® II Web Edition Design Software Version 14.0 for Windows" on the second page there but clicking it just takes me to the "Product Discontinuation Notice".

author: MadTux
author_rank: Frequent Contributor
timestamp: January 09, 2022, 02:41:31 pm
content: Could offer 14.00, although Linux only.Perhaps PM me, then I can set up SSH or something, so you can pull it from my computer directly.....13.00 Lin64 and some 8.0/9.0 Win32 are available as well.

author: RoGeorge
author_rank: Super Contributor
timestamp: January 09, 2022, 02:56:39 pm
content: If you are lucky and know the exact version of 14, you may try a direct download (use fetch, or wget, or paste the URL in the browser address bar). The ones I've used were for Quartus 15, might have a similar form for Quartus 14.The direct download URL's format looks like in this post:https://www.eevblog.com/forum/fpga/arrow-deca-max-10-board-for-$37/msg3646726/#msg3646726

author: voltsandjolts
author_rank: Unknown
timestamp: January 09, 2022, 03:26:26 pm
content: Thanks folks...and I think we have a winner...downloading now:http://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/QuartusSetup-14.0.0.200-windows.exe1.45GBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/QuartusHelpSetup-14.0.0.200-windows.exe356MBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/ModelSimSetup-14.0.0.200-windows.exe661MBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/arria-14.0.0.200.qdz601MBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/arriav-14.0.0.200.qdz1.23GBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/arriavgz-14.0.0.200.qdz1.82GBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/cyclone-14.0.0.200.qdz397MBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/cyclonev-14.0.0.200.qdz944MBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/max-14.0.0.200.qdz6.66MBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/stratixiv-14.0.0.200.qdz433MBhttp://download.altera.com/akdlm/software/acdsinst/14.0/200/ib_installers/stratixv-14.0.0.200.qdz2.47MB
Anyone working with Intel Agilex F-series? - Page 1
Forum section: electronics / general

author: x86guru
author_rank: Regular Contributor
timestamp: December 16, 2021, 04:05:27 pm
content: I'll be working with the Intel Agilex F-series for general R&D on custom server offloads via PCIe4 and was wondering if anyone has experience with the Agilex F or I series?
DECA board and Ethernet/USB standard com emulator. - Page 1
Forum section: electronics / general

author: BrianHG
author_rank: Super Contributor
timestamp: December 28, 2021, 07:45:42 pm
content: Hi, I was wondering if anyone has HDL to get Arrow's DECA onboard Ethernet or USB phy to be seen in windows as a standard com port instead of my current external hand wired FTDI-IO pins solution.Unfortunately, my current Windows control app is already written to use the standard system COM ports.
iCE40 PLL filter_range parameter - Page 1
Forum section: electronics / general

author: H3ndrik-Jan
author_rank: Newbie
timestamp: December 03, 2021, 08:14:02 pm
content: Hello everybody,I am trying to figure out how to use the PLL on the iCE40, and even bought a board (icesugar v1.5) to play around with. Reading the datasheet, I cannot figure out what the filter_range parameter means. Figure 3.1 in the PLL manual (linked under my post) shows a low-pass filter after the input divider, so I think it probably sets the cutoff frequency of that low-pass filter. Yet I don't know how to decide on the right FILTER_RANGE value. The table on page 11 shows the number is a 3-bit value.So far I found out the filter_range does matter. For instance, when I configure the PLL for 15MHz output with simple feedback path and 24MHz input (following the provided equation), setting the filter_range variable to 0 results in a 24MHz output, but setting it to 1 gives me 15MHz on the output. The other values give me a very jittery clock-signal on the output, approaching 15MHz.Can anyone tell me more about this parameter? I'm aware the manual says you should just use their software to determine the right values for the PLL, but I would like to know how to determine/calculate the value myself.iCE40 PLL manual:https://www.latticesemi.com/view_document?document_id=47778

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 04, 2021, 02:56:40 am
content: Project icestorm has a tool that can compute PLL parameters.From its source code, you can figure out how to:https://github.com/YosysHQ/icestorm/blob/master/icepll/icepll.ccSee line 'int filter_range = ...'it just depends on the PFD parameter.Where they got this information from, I don't know. I suspect they reverse-engineered it using Lattice tools.

author: sicco
author_rank: Regular Contributor
timestamp: December 06, 2021, 01:58:40 pm
content: I also had struggles with Lattice ICE40UP5K PLL. Documentation (datasheets) for this chip have many errors. On the filter range question I don't have an answer. But sharing what I think is wrong in the block diagrams and the text in the Lattice documents.

author: mon2
author_rank: Frequent Contributor
timestamp: December 07, 2021, 07:15:39 pm
content: You may have better luck in hunting down the original docs from Silicon Blue on this topic. It was Silicon Blue that created the ICE40 IP and was then aqcquired by Lattice.

author: H3ndrik-Jan
author_rank: Newbie
timestamp: December 08, 2021, 05:19:35 pm
content: Thanks all for the helpful responses! As for determining the filter range, I think I can indeed use the 'table' from icepll. Also thanks for the corrected block diagram!
LVDS FPGA on carrier - Page 1
Forum section: electronics / general

author: ezalys
author_rank: Frequent Contributor
timestamp: December 02, 2021, 04:38:01 pm
content: Does anyone know of a relatively inexpensive (<$150 USD) FPGA board meant to be socketed into a larger board that has the LVDS pins broken out? The CMODs from Digilent would be ideal if they had diff pair routing and the banks were powered appropriately. I would be happy with any mid-range FPGA — Spartan-7, Artix-7, or ECP5. I want to design a board with a high speed DAC and ADC but would rather avoid the task of doing layout and soldering for such a complex device.

author: asmi
author_rank: Super Contributor
timestamp: December 02, 2021, 04:49:34 pm
content: These are the only ones I know of which I would trust enough to actually put in a product:https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Artix-7/But I would design my own board, as I've done this enough times so it's not a big deal for me. This complexity is overrated, in reality it's rather simple. I'd say laying out say iMX6 boards is more complex than any 7 series FPGA.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 02, 2021, 06:08:38 pm
content: I second the Trenz boards in that price range.
How do you get the module outline/hierarchy on VSCode + VerilogHDL extension? - Page 1
Forum section: electronics / general

author: betocool
author_rank: Regular Contributor
timestamp: November 30, 2021, 12:55:43 am
content: Hi all,I've installed the Verilog-HDL extension in VSCode. And the syntax highlighting works, but for the life of me, I cannot get the outline and modules to show hierarchically. Am I missing something?Cheers,Alberto
A7-FTG256: Decoupling caps on unused banks - Page 1
Forum section: electronics / general

author: rgc_
author_rank: Newbie
timestamp: November 23, 2021, 11:25:02 am
content: Hi folks,I have an A7-FTG256 based design in which every penny and mm2 of board is relevant. I managed to get the IOs under 100, so I can make them fit in two banks out of the 3.5 banks in the package.The UG483 indicates how to maximize ESD protection in unused banks, and so I did. What is not specified, and I just assumed, is that I can remove also the decoupling caps for the unused banks from the design.Is this OK? anyone have done that already?Thanks in advance.

author: asmi
author_rank: Super Contributor
timestamp: November 23, 2021, 06:09:05 pm
content: Yes you can.Also, if you want to shave a bit more off PCB area and cost, you might want to consider using Spartan-7 instead of Artix-7. They are available in smaller 15x15 mm 196 ball package which has 100 I/O balls, so it should be a better fit for your needs. S7 has a bit less of DSPs that equivalent A7, but otherwise they are pretty much the same (sans MGTs of course, but FTG256 package doesn't bond out any, so it's a wash).

author: rgc_
author_rank: Newbie
timestamp: November 24, 2021, 03:39:09 pm
content: Thanks asmi, much appreciated.Thanks for the heads-up on the S7, too. Unluckily (and strangely) there's no S35 part, and the design wouldn't fit on an S25. That makes the A35 the less expensive part available for the project.

author: NorthGuy
author_rank: Super Contributor
timestamp: November 25, 2021, 05:12:14 am
content: Quote from: rgc_ on November 24, 2021, 03:39:09 pmHow do you determine the price when it is not sold anywhere?

author: rgc_
author_rank: Newbie
timestamp: November 26, 2021, 02:49:39 pm
content: Distributors will usually give you a quotation, even when there's no stock. It is true that price ratio in between devices of the same family sometimes change, but I haven't seen too much of a change for the S7/A7 series in a few years, specially in high volumes where prices are nothing like in DK listings.While that doesn't work for setting final product/contract pricings, it does work for picking up devices for new designs.

author: NorthGuy
author_rank: Super Contributor
timestamp: November 26, 2021, 03:34:49 pm
content: Quote from: rgc_ on November 26, 2021, 02:49:39 pmThe price is useless when there's no stock. The prices will be different when (if?) new stock emerges.

author: rgc_
author_rank: Newbie
timestamp: November 27, 2021, 02:21:28 am
content: Prices will most likely be different, but that is irrelevant for the device selection as long as all devices of a given brand/series are changed by a more-or-less similar %, and this is what happens in most cases in our experience.
#Rant: Intel can't even host files correctly. - Page 1
Forum section: electronics / general

author: Yansi
author_rank: Super Contributor
timestamp: November 22, 2021, 11:33:14 am
content: Normal work day as always, just wanted to download EPM570 pinout file and mind my business, but oh no, sorry, you do not have authorized access to theEPM570 pinout file, fuck you!Not even mentioning, you need to have a registered account to download any file. Screw you again!Tried couple files around it inthe pinout section, almost every third I get Err500, no response or similar.Yes, first class support for Altera.Rant end.//So, can anyone download it, or is it just me (our coporate network problem)?

author: Daixiwen
author_rank: Frequent Contributor
timestamp: November 22, 2021, 11:45:47 am
content: Their search function is also useless. It's a lot easier to search from Google for documents on their website.What are your language / location settings on the Intel.com website? I get lots of 500/404 errors when using another language and location than United States (English).We at least know where all the QA testers are located

author: Daixiwen
author_rank: Frequent Contributor
timestamp: November 22, 2021, 11:48:17 am
content: I just got this one from your link

author: Yansi
author_rank: Super Contributor
timestamp: November 22, 2021, 12:37:05 pm
content: Quote from: Daixiwen on November 22, 2021, 11:45:47 amVery good hint! I will try. But it seems to be switched to US/English already. But I am accessing through a Austria(?Germany?) corporate network.Thanks for the file Daixiwen!

author: mon2
author_rank: Frequent Contributor
timestamp: November 22, 2021, 12:45:50 pm
content: Intel sucks at everything they do. They have the kiss of death with no vision. Chased their flawed thunderbolt designs for many years. They would rather support their buddies in the back alleys of Taipei than bricks and mortar companies with million++ shipped products. Avoid!!!
Xilinx FPGA XCZU27DRFFVG15 - Page 1
Forum section: electronics / general

author: Thomas83
author_rank: Contributor
timestamp: December 10, 2021, 12:15:47 pm
content: Hi everebody,I use XCZU27DRFFVG15 FPGA, I want to know if we could configure the PINS A27, C25, F25, B25 or D25 as I2C bus (CLK & SDA)?If yes which ones and how to do thatThank you for your comeback
how to make sd card bootable in linux os - Page 1
Forum section: electronics / general

author: newit
author_rank: Contributor
timestamp: November 25, 2021, 03:26:43 am
content: HiDoes any one know how to make an sd or mini sd card size 2GB bootable in linux OS, Thanks in advance.regards;s

author: agehall
author_rank: Frequent Contributor
timestamp: November 25, 2021, 08:26:25 am
content: No, we don't know what your telescope expects.

author: tszaboo
author_rank: Super Contributor
timestamp: November 25, 2021, 09:46:39 am
content: You typically download an image, than you use a SD card image burning tool to copy the files, and the file system. Simply copying the files won't work.Stuff like this:https://www.balena.io/etcher/

author: FlyingDutch
author_rank: Regular Contributor
timestamp: November 25, 2021, 04:01:07 pm
content: Hello,it depends of used bootloader. Mostly it involves editing "boot.ini" file and place Linux kernel image, "Device Tree" file and Linux filesystem image (ziped) on SD card. All process is quite complex, for claryfing i propose to watch this tutorial:Best regards

author: tunk
author_rank: Super Contributor
timestamp: November 25, 2021, 04:12:24 pm
content: What will you be using it in, e.g. a SBC like a raspberry?

author: agehall
author_rank: Frequent Contributor
timestamp: November 25, 2021, 06:01:58 pm
content: Quote from: tunk on November 25, 2021, 04:12:24 pmThis is probably the 10th thread around some proprietary telescope that isn’t working. See his other threads for random bits of information about the system.

author: abyrvalg
author_rank: Frequent Contributor
timestamp: November 25, 2021, 07:23:04 pm
content: newit, your problem has nothing neither with Linux (your scopedoesn'trun Linux) nor with FPGA. The solution is described in this message:https://www.cloudynights.com/topic/792080-meade-etx-ls-hbx-freeze-while-updating/#entry11408348(follow the less error prone "Win7 or Win10" path). If it doesn't work for you - open a topic in theRepairsectionhttps://www.eevblog.com/forum/repair/instead of spamming random sections.

author: newit
author_rank: Contributor
timestamp: November 26, 2021, 02:10:36 am
content: Quote from: tunk on November 25, 2021, 04:12:24 pmNo, my scope motor control system do not boot up, if i can boot up the scope I will then be able to communicate with scope via USB.
Update firmware failure boot loader may gone bad - Page 1
Forum section: electronics / general

author: newit
author_rank: Contributor
timestamp: November 14, 2021, 11:39:02 am
content: HiI have a telescope motor control board with Linux OS I'm attempt to update firmware but failed, when power back on can't boot to the menu page only can boot to Update firmware again via Mini Sd card. How can i repair this boot loader or re-flash it? System consist of following chip CPU ADSP-BF531 sbstz400, Nand Micron 29F2g08AACWP, Exilinx XC2C256. You can look at PIctures.Thank you
Easy Quartus II / Cyclone III Question - Page 1
Forum section: electronics / general

author: NorthernWing
author_rank: Contributor
timestamp: November 12, 2021, 12:01:33 am
content: So I currently have the displeasure of learning how to use Quartus II 13.0 to implement a design on an old Cyclone III chip. My god this is awful. Yeah it's a 14 year old FPGA, but it's what I've got and frankly this EP3C16 still has more capacity and is faster than most of the modern chips I can get my hands on right now anyway.I usually write my hierarchy as ["device.vhd"] -> ["top.vhd"] -> [Fabric/Logic], where top is thetoplevel of the RTL/logic itself, anddeviceinstantiates chip-specific hardware like PLLs, IO buffers, etc.I've got synthesis, p&r, timing, and simulation all completing successfully in Quartus II here, but I can't for the life of me find any documentation, libraries, or menu options for instantiating hard macros like the I/O buffers and PLL/clock conditioning. I know they exist because the thing has an EMIF and misc PLL cores/etc, but where exactly are these described?

author: oPossum
author_rank: Super Contributor
timestamp: November 12, 2021, 12:55:12 am
content: Tools menu, Megawizard Plug-In Manager.If you can't find something where it should be, check the I/O category. They like to hide stuff there.

author: NorthernWing
author_rank: Contributor
timestamp: November 12, 2021, 01:04:59 am
content: Ah yep, that's it - looks a lot like the Vivado IP catalog. Much appreciated, not sure how I missed that one.Time to see if I can turn a pair of LVDS buffers into a SAR ADC on this thing.
Interfacing ADXL335 accelerometer with ZCU104 - Page 1
Forum section: electronics / general

author: hyper
author_rank: Newbie
timestamp: November 16, 2021, 02:24:17 am
content: Hello Everyone. I am a newbie in the embedded system/soc.my advisor want me to work on ZCU104. presently having a task to interface adxl335 accelerometer sensor with the pmod. Firstly, i try to create a block design using SPI on (Zynq processor and microblaze) with no result. the sensor is an analog sensor good for quick prototyping with arduino and other analog support microcontroller board.What is best way to approach the usage of analog sensor on MPSOC and i will appreciate if there is any book any one can suggest or website with guide on xilinix struct and sdk programming.Thank you all
Anlogic TD IDE license generation - Page 1
Forum section: electronics / general

author: davorin
author_rank: Unknown
timestamp: November 05, 2021, 06:47:17 am
content: Good morning (o;Registered at Anlogic website to download latest TD IDE for Linux..installs fine and also runs fine with the license from Sipeed site, which is only valid to March 2022.So....has someone has a clue what to enter exactly on Anlogics website as MAC address for generating a TD IDE license?http://www.anlogic.com/down_view.aspx?TypeId=23&Id=479&Fid=t14:23:14Only response I get is a Javascript alert box saying "unkwon".I use Chrome browser for converting chinese into english on the fly...

author: RoGeorge
author_rank: Super Contributor
timestamp: November 05, 2021, 07:04:49 am
content: The MAC address is a unique ID (a hex number) for each network card, either LAN or WiFi.https://en.wikipedia.org/wiki/MAC_addressSearch for how to "find my MAC address" and follow the instructions for how to find that for your operating system.

author: davorin
author_rank: Unknown
timestamp: November 05, 2021, 07:21:36 am
content: I know what a MAC address is ...configured many Cisco and Juniper devices in the past (o;No the problem is that regardless in which format I enter the MAC address, the site respsonds with the Javascript alert box....No format is accepted...either as plain hex number or with ":" or "-" as Lattice requires....

author: RoGeorge
author_rank: Super Contributor
timestamp: November 05, 2021, 07:31:18 am
content: Sorry. Then you may want to write to them, or try another browser, or maybe search for a generic license number in more obscure places of the Internet (other FPGA vendors usually accept other licensing numbers that are not tied to any hardware ID, chances are these guys do the same)
Trion FPGA PLL instantiation in Verilog - Page 1
Forum section: electronics / general

author: davorin
author_rank: Unknown
timestamp: November 04, 2021, 12:16:51 pm
content: Good afternoonTo use a PLL on a Trion FPGA you have to use the Interface Designer to set input/output names and clock multiplier/divider....and then assign the dedicated PLL input to a GPIO pin...so far so good.In the pt_demo example I see that the PLL signals have to be used in the interface definition fot he Verilog top module....but seems my PLL clock is ignored therefore leading to a design where it throws an error that only VCC and GND nets are generated...Code:module test_lcd(input pll_clk,output wire [0:7] R,output wire [0:7] G,output wire [0:7] B,output wire LCD_CLK,output wire LCD_HSYNC,output wire LCD_VSYNC,output wire LCD_DEN,output wire LCD_PWM);Someone knows what the trick is in Efinity IDE to correctly use a PLL?Don't know why they don't use the same approach as Xilinx and Quartus to generate a Verilog file to be included in your design instead.thanks in advance

author: mon2
author_rank: Frequent Contributor
timestamp: November 04, 2021, 08:07:24 pm
content: See if this helps:https://www.digikey.ca/en/videos/e/efinix-inc/efinix-development-tool-tutorial-simple-pll-creation-in-interface-designerIf not, can share the contact for a FAE in the USA via a PM.

author: davorin
author_rank: Unknown
timestamp: November 04, 2021, 09:07:43 pm
content: Found my stupid mistake ;-)During migration from Anlogic to Efinix I deleted the pll instantination which outputted a reset signal to the timing module....so it used 0 as a constant driver ;-)Still have to get used to the Efinity IDE.....
Power measurements of a PLL - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: November 02, 2021, 12:40:04 pm
content: I am currently doing characterization of a PLL on an FPGA.I am thinking about some meaningful measurements.I am not sure if I just sweep the frequency and measure the current consumption or is there anything else worth measuring when it comes to power.Perhaps the ramp up current usage before the PLL is locked.

author: FlyingDutch
author_rank: Regular Contributor
timestamp: November 02, 2021, 01:29:45 pm
content: Hi,you can also measure: "jitter" and "phase shift">Regards

author: steamedhams
author_rank: Regular Contributor
timestamp: November 02, 2021, 02:52:06 pm
content: It is only focused around power consumption.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 02, 2021, 06:26:39 pm
content: Ramp-up current? I guess you mean the current draw from the moment you enable it to the moment it's locked? Not sure you'll see anything really interesting compared to its steady-state current, but why not. For this you'll need to write proper HDL code - for instance toggling an IO when you enable the PLL and toggling it back when it's locked, so you can synchronize you measurement. Then you'll need a proper dynamic measurement of current - I'm assuming you already have this setup.As to "sweep the frequency", it's a bit trickier here I guess. The power consumption of a PLL will depend on the input frequency, VCO frequency and the various dividers - not just the output frequency.That may be a lot of configurations to test.