SRAM - WE and CE controlled writes - what's the difference? - Page 1
Forum section: electronics / projects

author: TomS_
author_rank: Frequent Contributor
timestamp: February 02, 2023, 09:58:22 am
content: Hi all.Does anyone know what the actual or functional difference is between these two types of write on an SRAM?The timing diagrams (for e.g. AS6C4008) only depict that CE or WE falls before the other, but not how soon (min/max).There are no timing constraints listed in the datasheet for signals OE/WE/CE in respect to each other for the beginning or end of a cycle.Thanks!

author: RoGeorge
author_rank: Super Contributor
timestamp: February 02, 2023, 10:18:46 am
content: Not sure what datasheet, maybe yours is an excerpt. Let's take this one:https://www.farnell.com/datasheets/1911297.pdfMark on the timing waveforms the missing timings you need.

author: iMo
author_rank: Super Contributor
timestamp: February 02, 2023, 10:28:05 am
content: The DS says:QuoteSo it does not matter. Usually /CE and WE/ are two inputs into a single gate..

author: TomS_
author_rank: Frequent Contributor
timestamp: February 02, 2023, 10:53:11 am
content: Quote from: imo on February 02, 2023, 10:28:05 amThis is much what I expected, but I just dont really understand why they would call the two out separately if logically they appear the same to the device internally? Unless it is just showing that both are permissable as methods to perform a write?Basically the write is effected by the rising edge of a signal (CE or WE) that ends the cycle?

author: TomS_
author_rank: Frequent Contributor
timestamp: February 02, 2023, 11:01:10 am
content: Quote from: RoGeorge on February 02, 2023, 10:18:46 amYep, that looks like the one I was looking at.The attached basically shows the unclear timing, perhaps because it doesnt matter?

author: TomS_
author_rank: Frequent Contributor
timestamp: February 02, 2023, 11:05:46 am
content: I suspect the key is really in the way the waveforms are represented. e.g. in the WE controlled diagram, the waveform for CE represents that it can either be constantly low, fall before and/or rise after (or roughly at the same time as?) WE.For CE controlled, WE may be constantly low or fall before and/or rise after CE.But I presume that you can use basically any combination of the befores and afters? In a circuit that I have built I start with a waveform more like CE controlled where WE goes low before CE, but then end with something more like WE controlled where WE goes high before CE. It all seems to work perfectly fine.

author: Berni
author_rank: Super Contributor
timestamp: February 02, 2023, 11:09:19 am
content: There are cases where some chips are picky about not supporting one of those methods.Like i seen some asynchronous parallel FRAM chips that require it to be WE controlled.By listing out both WE and CE controlled the datasheet tells you that this chip doesn't matter, so you can use whatever method you find more convenient for your design.

author: iMo
author_rank: Super Contributor
timestamp: February 02, 2023, 11:20:09 am
content: There are some constrains with PSRAMs (pseudoSRAMs == dynamic ram with built in SRAM controller), afaik, as the signals have got some max duration in order the information will not vanish off the Leyden jars (the internal dram's refresh stops during the access)..

author: Doctorandus_P
author_rank: Super Contributor
timestamp: February 02, 2023, 11:36:06 am
content: Don't generalize too much. Have a look at several datasheets from different manufacturers.Some may have clearer timing diagrams or text notes. Also don't assume all IC's work the same. there may be differences. I think that the chip enable is used to put the whole IC into some power down mode in some IC's, and then it needs more time to activate again.

author: pcprogrammer
author_rank: Super Contributor
timestamp: February 02, 2023, 12:04:24 pm
content: You also have to see the bigger picture of the usage. There is also reading of the device and for this /WE needs to be high.Like Berni wrote, this chip supports all kinds of ways to either read or write to the memory, but it still boils down to the signals needing to be in a certain state to perform the actions. The latching of the data in the addressed cell is done on the rising edge of either /CE or /WE, which ever comes first.Reading:/CE needs to be low/WE needs to be high/OE needs to be lowWriting:/CE needs to be low/WE needs to be low/OE does not matterAddress change in case of writing:/CE needs to be high/WE needs to be high/OE does not matterFor reading the address can change with /CE low but the data is only valid after some time.

author: RoGeorge
author_rank: Super Contributor
timestamp: February 02, 2023, 12:43:01 pm
content: Quote from: TomS_ on February 02, 2023, 11:01:10 amIndeed, the edges of CE# and WE# relative to each other doesn't matter. Internally, a WRITE# signal is considering either of the two. WRITE# = WE# AND CE#. So what matters is the timing for the resulting signal WRITE# in regards with the data bus and the address bus, and those timings are shown in the diagrams either relative to the CE# or relative to the WE#.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 02, 2023, 01:14:50 pm
content: Just to hint at some historical context -- there are many other types, besides the newer e.g. FeRAM and whatnot, but older types ranging from CMOS and TTL SRAMs, also to DRAMs for which there are /RAS and /CAS instead (to save on pins, but also reflective of their internal structure -- you can perform refresh with just a /RAS cycle).Even modern SDRAMs, they usually document them as being not just words, rows and columns, but layers/planes too; the relevance of these axes may not be all that obvious after all (if at all; but, I'm no SDRAM expert so I don't actually know the details here), but one example is, you can't expect burst mode accesses across such boundaries, and at that, they're usually limited to bursts on aligned blocks. Probably because they're accessing rows/planes together, eh.So, just to say -- they might indeed be symmetrical inputs to an internal gate, but this isn't generally true across all families, so it's historically relevant to document WE/CE-controlled writes separately. Or CE/OE reads.So, just make sure to check you're using the appropriate timing diagrams for your bus waveforms, and design appropriately.Tim