How to pull-back individual PCB's planes in a panelized PCB in Altium? - Page 1
Forum section: electronics / general

author: smoothVTer
author_rank: Regular Contributor
timestamp: April 14, 2017, 02:49:17 pm
content: Almost universally, a layout designer will use a pull-back rule for board outline clearance so that when the router bit cuts out the PCB's shape, it doesn't hit any metal along the edges and possibly short the VDD plane to GND plane through a sliver of metal along the outside edge which might have gotten bent or ripped during routing.So I've got a few PCB's to which I've implemented pull-back on all metal levels. Here's one example of an internal signal level which has a polygon pour on it, and the polygon pour is pulled back from the edge of the PCB:You can see the gold colored metal pulled away from the PCB edge, showing only blank/black.Ok so now I want to panelize this PCB along with several other PCB's. I use Altium's embedded board feature to place instances of my sub-PCB's into a panel, I place routing paths for CAM tools to cut out the individual PCB's into a tab routed array:The problem isthat when I place a PCB which contains plane pull-back into the 'master' panelized PCB, I lose the pull-back of my individual PCB's in the array. As you can see in the above image, the inner edges of my route paths abut the global inner plane metal of the panelized PCB.Is there a method to maintain inner plane pullback in panelized PCBs? How should I approach this issue differently?

author: ajb
author_rank: Super Contributor
timestamp: April 14, 2017, 05:40:00 pm
content: How are you defining the pullback?If you use the manufacturing->Board Outline Clearance rule and use embedded board arrays to panelize it should work just fine. If you're using a keepout layer or something, maybe you need to add another design rule to the main panel file?

author: smoothVTer
author_rank: Regular Contributor
timestamp: April 14, 2017, 06:05:02 pm
content: One caveat I neglected to mention: the individual PCB's pullback works fine on signal levels. But on internal plane levels, the plane of the carrier PCB pours over the 'gap' in the individual sub-PCB's.I'm defining the pullback using the PCB Rules & Constraints Editor, under Manufacturing-->Board Outline Clearance and I have this value set to 10 mils for all objects. This has the effect of pulling back the metal in the individual PCBs for both signal layers and plane layers. But in the top-level panelized PCB, if I use this same rule, it applies to the top-level plane only. That is to say, the top level carrier PCB has its GND plane pulled back from the outer edges, but still pours over that gap in the sub-PCB's.I am not using a keep out layer in this design.

author: Niklas
author_rank: Frequent Contributor
timestamp: April 18, 2017, 05:16:51 am
content: There is a pullback definition for each plane layer in Design>Layer Stack Manager. Check the values set for the assembly panel.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 18, 2017, 06:49:37 am
content: Also, would recommend avoiding planes entirely, using Polygons instead.Tim

author: julianhigginson
author_rank: Frequent Contributor
timestamp: April 20, 2017, 05:40:20 am
content: Quote from: T3sl4co1l on April 18, 2017, 06:49:37 amoops... a bit of off topic, but I'm curious to know... I have worked both ways, but prefer working with plane layers as it makes things easier to see in the PCB as I route, and seems to be less heavy on my computer's processor. Also I like the differentiation of a plane layer from a routing layer - stops people running tracks on layers they shouldn't!So is there any particular current reason (or known bug) that polygons are seen as a better thing to use than planes in 2017?I hear chinese whispers about planes not being "reliable" and yes, once, back in 2001, using protel99se, I was caught out with a short inside a 6 layer PCB due to the behaviour of via thermal relief patterning around a via at the very edge of a plane net area. But AFAIK that bug got squashed, and it's never bothered me again (even though I always check..) I'm wondering what other issues people have with plane layers?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 20, 2017, 08:01:29 am
content: Even Altium recommends Polygons over Pours, IIRC.Pours are only useful on very large boards, where computing a poly is prohibitive, and where there aren't any unusual footprints* or demanding routes (you have more than enough signal layers for routing, and don't have to steal any space on the plane layer). You'll probably autoroute much of such a board, as well.*Oval and slot pads don't work at all with Planes: the thermals aren't stretched to the pad shape. Planes have hardly any rules, while Polygons have enough to be useful. Planes seem very... primitive.Tim

author: julianhigginson
author_rank: Frequent Contributor
timestamp: April 21, 2017, 01:36:23 am
content: I guess I don't use slots much, so haven't seen that issue where I was expecting them to work with a plane layer that also has thermal reliefs. Thinking back, most of the time when I need slots, I have either had them for parts that wanted them for mechanical strength pins, which have no connection, or for metal shields, where I didn't want thermal relief. With QFN thermal pad vias, I just do the connection for that part to the plane layer as direct connect. (And where the thermal vias decimate non GND plane layers leaving little fragments of copper I just mask it away under the part if I can't keep the copper continuous)My main issue with using poly pours for whole plane layers is when I have all the power and GND planes in place (and I like to have them in place first, goes with the parts placement) it's nice when routing to not have to worry about crashing into polygon pours and causing violations that turn the whole screen green whenever I have a trace that changes layers... even when I turn polygons to draft mode, and then set the polygon to ignore online violations, (I just tried this with a quick sample attempt in a new PCB file and am still seeing the online DRC blow up my whole screen with green the instant I finish routing a track with a via... green goes away when I go to the layer the polygon is on, double click it to get the dialog, then click OK to dismiss the dialog...)I can shelve the polygons when I route, but then I can't use them at all when I want to run tracks to actually connect to them!So yeah - my main experience with using polygons as the main planes in a design has been painful, and it's either been when I do need to steal some space to push a sneaky track or two on a plane layer, or where I have had to work on something someone else started.So is there some nice and simple workflow I'm missing if I want to use poly pours instead of plane layers? I have a relatively simple 4 layer board I'm about to do for prototyping purposes (schematic mostly captured already) and I am willing to try the whole polygon pour thing woith this if I learn something useful from it. I would love to know how to make working with polygon planes less painful.

author: julianhigginson
author_rank: Frequent Contributor
timestamp: April 21, 2017, 01:49:07 am
content: Quote from: smoothVTer on April 14, 2017, 02:49:17 pmYou can replace board edge pullback rules on the plane layers with standard fills (or poly regions if you want to get fancy, or thick lines, come to think of it...) on the plane layers.Ideally you would go through the individual PCB files and put them around each board. This way the individual PCB files still hold the design intent when it comes to defining the edge pullback distance for their plane layers.You only have to surround the PCB edge on one plane layer, then you select all the primitives you used and "paste special" them to the other layer(s) as needed.Otherwise you could go oldschool and pannelise at the gerber level.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 21, 2017, 06:50:41 am
content: Quote from: julianhigginson on April 21, 2017, 01:36:23 amEww, online DRC. Slows everything down. Live repour, too (though it's nice on small boards).I don't use online DRC because I can clearly see where I'm creating violations, while I'm working.That... may be a more advanced point than where you're at, though. YMMV.I also pour large polys after placement and routing. (Polys used for power and thermal routes, typically in switchers, are done earlier.) I don't think it makes sense to worry too much about where the supplies are, and to have that influence your placement and routing. Consider the tradeoff: if you're placing and routing with a higher priority towards supplies, that implies a lesser priority towards signals. But there's more signals than supplies, so you're most likely making more congestion for yourself.Tim

author: julianhigginson
author_rank: Frequent Contributor
timestamp: April 21, 2017, 07:28:08 am
content: Yeah, I guess I could turn online DRC off, but I'm just used to it now, so haven't considered the option. And the online DRC check doesn't seem to take up that much time that it bothers me with the kinds of boards I do.... But now I think about online DRC, I suppose the options around smart routing and maintaining clearance rules would make the online DRC pretty redundant normally. I could probably live without it.Come to think of it, last time I had to turn off online DRC, polygon pours were not proper polygon objects, but auto-generated crosshatched fills made with tracks, and if you had even a reasonable sized board and touched 2 polygons of the same net together, the online DRC would spend about 5 minutes calculating all the current paths through all the tracks in the polygons (or something like that... who knows...) that was painful, and pretty much every user was screaming about it and threatening to leave for different software. (the more things change, eh?)Anyway, I'll give your approach a try when I get to the board layout phase of this little part evaluation I'm working on.. I'll see what life is like nowdays without online DRC, and putting power and ground planes in last as polygon pours on normal copper layers.