Two Stage Open Loop Comparator Question - Page 1
Forum section: electronics / projects

author: Melvin Edwards II
author_rank: Newbie
timestamp: May 27, 2019, 06:32:11 pm
content: Hello All,I am trying to understand the operation of a two stage open loop comparator.In the attachment is the output stage of the two stage comparator, a current-sink inverter.What my question is, is how do I know that the output voltage can go to Vss in the low state. To me, it would seem like if Vo dropped to Vss in its low state then transistor M7 would no longer be in saturation mode(possibly triode mode) and I am not sure what this means for the operation of the circuit.I've also tried looking at this from the approach of transistor M6. The maximum that Vg6 can be is Vdd-|Vtp| in order to maintain M6 turned on. I wasn't able to develop this thought any further.My thoughts are that the Vo can't drop to Vss, rather it can drop to (Vgs - Vt) above Vss and maintain saturation of M7. The book says that this voltage can drop to Vss though which confuses me.Any help in understanding is appreciated. Sorry about the slanted image.This circuit is from CMOS Analog Circuit Design by PE Allen, page 450, Figure 8.2-1.Thanks,Melvin

author: ejeffrey
author_rank: Super Contributor
timestamp: May 27, 2019, 08:04:08 pm
content: I'm sure you could design a circuit that required some supply inductance, but relying on placing the bypass caps a certain distance away wouldn't be an effective or repeatable way to accomplish that. I'm sure it is just a typo.

author: Wimberleytech
author_rank: Super Contributor
timestamp: May 27, 2019, 08:45:52 pm
content: Quote from: Melvin Edwards II on May 27, 2019, 06:32:11 pmIt is OK if M7 is no longer in saturation. In fact it is in "nonsaturation" (the books term for "triode" region). When a transistor is in nonsaturation, the channel is fully inverted from drain to source and looks like a resistor (but non linear).QuoteVg6 can be equal to VDD when Vin is negative. In that case, all of the tail current from M5 flows through M1 and M3 and none of it flows through M2. Therefore M4 pulls Vg6 to VDD.QuoteNo, your confusion is in thinking that all transistors must operate in saturation. This is not the case for a comparator.

author: Wimberleytech
author_rank: Super Contributor
timestamp: May 27, 2019, 08:49:33 pm
content: Quote from: ejeffrey on May 27, 2019, 08:04:08 pmI think this answer accidentally landed in the wrong post.Possibly belongs to: Lead length to bypass cap "must exceed 20mm" ??https://www.eevblog.com/forum/projects/lead-length-to-bypass-cap-must-exceed-20mm/

author: Melvin Edwards II
author_rank: Newbie
timestamp: May 27, 2019, 11:00:42 pm
content: Quote from: Wimberleytech on May 27, 2019, 08:45:52 pmThanks for the response.Just to make sure I understand(hopefully)1. Vin is negative(enough to cause all current to be steered through M3 and M1)2. Current is steered from M5 through M3 and M1.3. This causes M4 to go into triode mode(small Rds,on)4. Vg6 is now pulled up to Vdd by M4.5. M6 is turned off(Vsg < Vthreshold, because Vg6 is at Vdd and Vs6 is also at Vdd)6. M7 is placed in triode mode and pulls the output to Vss.I have one question, if my sequence of events is correct. If M6 is turned off how do we know what voltage Vd7 is at in order to say that it is in triode mode?Thanks

author: Wimberleytech
author_rank: Super Contributor
timestamp: May 28, 2019, 12:42:41 am
content: QuoteAll correctQuoteSince there is a load capacitor. If the output is initially VDD, then when the comparator flips, M7 is initially in saturation and draws current from the load capacitor and the output voltage falls. As the voltage falls below VDsat, M7 goes into nonsaturation and acts like a nonlinear resistor. The capacitor continues to discharge as it asymptotically approaches VSS. VDsat is determined by the voltage on the gate of M7 using Eq 3.1-15.

author: duak
author_rank: Super Contributor
timestamp: May 28, 2019, 01:30:30 am
content: You can think of M7 as a current sink that is pulling VOUT down towards VSS. If M7's drain current is less than what VBIAS and its transfer function will allow, M7 will act as a resistor and VOUT will approach VSS. If M6 is off, and M7 has no drain current, VOUT will equal VSS.If M6 and/or whatever is connected to VOUT, say a pull up resistor, tries to source or supply more current than M7 can accept or sink, VOUT will rise and approach VDD.