TTL NAND gate from discrete transistors - Page 1
Forum section: electronics / beginners

author: nand2025
author_rank: Newbie
timestamp: January 18, 2025, 07:03:03 pm
content: Hi,I'm trying to build all the logic gates using transistors.I have the following circuit working on a breadboard and connected to an Analog Discovery 2.This is just for learning, as a hobby, and for fun.My questions:Q1: The output (Q) does not reach 5V; it stays around 4V when high. How can I get this to be 5V?Q2: Looking at the attached waveforms, I have one input tied high and the other input fed with a square wave. As seen in the waveform, the output does not keep up with the input at higher frequencies. What could be causing this, and how can I improve the response?

author: ledtester
author_rank: Super Contributor
timestamp: January 18, 2025, 07:26:38 pm
content: Quote from: nand2025 on January 18, 2025, 07:03:03 pmTTL defines a HIGH signal as anything above 2V (as well as an ability to source current).See the "Interfacing considerations" section of this Wikipedia article:https://en.wikipedia.org/wiki/Transistor–transistor_logic#Interfacing_considerationsAlso, the paragraph just before it gives some reasons for the output voltage of a logic "1" not reaching 5V.

author: nand2025
author_rank: Newbie
timestamp: January 18, 2025, 07:37:00 pm
content: Thanks, ledtester!I appreciate the link - knowledge gained! 🙂I tried my circuit with a 2V square wave, and it works fine.So, I think I just need to speed up the circuit now.

author: ledtester
author_rank: Super Contributor
timestamp: January 18, 2025, 08:10:40 pm
content: Read up on the "Schottky Transistor" - it's a way to prevent transistors from saturating and thus improving turn on/off speed. It was used in the LS TTL family.https://en.wikipedia.org/wiki/Schottky_transistorA video from FesZ Electronics (highly recommended channel):Electronics tutorial - Improving switching times - The Baker Clamp and the Schottky transistorhttps://youtu.be/C_SaJfBvkLc

author: golden_labels
author_rank: Super Contributor
timestamp: January 18, 2025, 08:23:07 pm
content: Welcome to the forum.Quote from: nand2025 on January 18, 2025, 07:03:03 pmWith this output style you can’t. Q4 is avoltage follower (common collector configuration)and it’s emitter will not go above supply voltage minus B-E junction drop. That is approximately 5 V - 0.6 V = 4.4 V in your case. If any noticeable current is drawn from output, R4 and D3 will cause an even larger drop.As mentioned by ledtester, this isn’t a problem. Your circuit actually does well. TI’s datasheet for SN7400 gives typical 3.4 V output, at 4.75 V supply and 400 nA load.Quote from: nand2025 on January 18, 2025, 07:03:03 pmBy turning it into an integrated circuit.Or by using a different thing.BJTs exhibit some capacitance and it takes time for that to discharge. In particular a saturated transistor takes tremendously long time to turn off.(1)To avoid that problem, TTL usedSchottky transistorsin 74S*, 74LS*, 74AS*, and 74ALS* families. Nowadays you can see mostly 74HC* and 74HCT*, which should give you a hint: there are limits to the architecture even with Schottky hacks.But what is more important: implementing integrated circuit designs in discrete components may yield poor results. It’s nice for leaning basic concepts. It’s great for understanding inherent limitations of the circuits, and how the actual implementation affects observable behavior of an IC. But there is are major differences, which leads to discrete circuits having poor performance or — in particular with more modern designs — not work at all.One crucial thing is timing. Signals don’t travel instantly. The ultra-short distances you get on a silicon die are a part of the design and you can’t get around it with wires that are orders of magnitude longer. Parasitic inductances and capacitances are also very different in those scales. Another huge difference is that the diagrams are meant to give a general idea of how the circuit behaves. To start with: in the actual 7400, on which this diagram was based, Q1 and Q3 areonetransistor with two emitters. This alone changes its characteristics. And then we have all the magic and weirdness of things implemented in silicon.Here’s a beautifulshot of the 1965 SN7400by “Mister rf” of Wikimedia Commons. Each quadrant is a single NAND gate. In each, connections on sides go from top: output, input, input. In bottom-outside of each gate you can see inputs go to a single element: this is the BJT with two emitters. Then the collector is the lower line going towards inside and then turning back. What it reaches is two hugeDarlington pairs. One would roughly correspond to Q2+Q6 in your diagram, the other would be Q4… except that Q4 is in the actual die an exact copy of Q2+Q6, and both have much higher amplification than the transistors in your diagram. And you can’t get the same performance, at least not in terms of bandwidth, as you’d squeeze out of that microscopic structure.As a bonus: here is a74AHC* series version(CMOS) from Zeptobars.(1)Relative to the time scales we are talking about here.

author: edavid
author_rank: Super Contributor
timestamp: January 18, 2025, 08:29:59 pm
content: Standard TTL uses gold doped transistors for faster saturated switching speed.You can get closer to TTL speed by using gold doped discrete NPNs. They are not as common as they used to be, but PN2369A, MMBT2369A,and MMBT5179are still in production.

author: nand2025
author_rank: Newbie
timestamp: January 18, 2025, 08:55:31 pm
content: Thanks for all the help and advice! I’ll order some Schottky diodes and test them in my circuit.

author: brucehoult
author_rank: Super Contributor
timestamp: January 18, 2025, 09:10:22 pm
content: Quote from: golden_labels on January 18, 2025, 08:23:07 pmNote that the CDC6600 in 1964 was a 60 bit CPU  that ran at 3 MIPS using only silicon transistors, no ICs at all.This might be of interest:https://cpldcpu.com/2020/02/14/what-made-the-cdc6600-fast/ for the main arithmetic registers, 18 bits for addresses and counters since they couldn't afford much RAM in those days

author: PGPG
author_rank: Frequent Contributor
timestamp: January 19, 2025, 12:57:45 am
content: Quote from: nand2025 on January 18, 2025, 07:03:03 pmIn NAND schematics I saw R2 was 1k6 and R3 was 1k. Will be 2 times faster.

author: mawyatt
author_rank: Super Contributor
timestamp: January 19, 2025, 02:42:48 pm
content: Quote from: edavid on January 18, 2025, 08:29:59 pmWasn't aware the type 5179 NPN transistors were gold doped, these were intended for RF applications and not switching like the 2369 types.Best

author: David Hess
author_rank: Super Contributor
timestamp: January 19, 2025, 03:36:33 pm
content: Quote from: mawyatt on January 19, 2025, 02:42:48 pmUsing an RF transistor like the 5179 will help, but they are not in the same class as fast saturated switches like the 2369, even with Baker clamps.Adding small signal schottky diodes as Baker clamps will help the most.

author: edavid
author_rank: Super Contributor
timestamp: January 19, 2025, 04:13:18 pm
content: Quote from: mawyatt on January 19, 2025, 02:42:48 pmMy mistake, I thought they were because of the low HFE.It might still be interesting to try them in a Baker clamped or Schottky clamped circuit.

author: mawyatt
author_rank: Super Contributor
timestamp: January 20, 2025, 05:34:42 pm
content: Quote from: edavid on January 19, 2025, 04:13:18 pmWell in the past when we did discrete design (later career was IC design) we utilized the 2N5179 and 2N2369 often for RF and Switching applications respectively, but didn't "recall" the 2N5179 was gold doped like the 2N2369 (1N4148 was also gold doped for fast switching).BTW the fastest bipolar logic back then was ECL and CML, these were non-saturating thus avoiding the transistor saturation effects.Anyway, thanks for clearing this up, thought we may have missed something from way back then.Best,

author: nand2025
author_rank: Newbie
timestamp: January 20, 2025, 07:37:08 pm
content: Thanks, Brucehoult. The link on the CDC 6600 is very interesting—a very powerful machine for its time.Thanks to everyone for the other replies.I changed the transistors from BC547 to S9018 and placed 1N34A diodes across the base-collector of Q2 and Q5 (they did not help with the other transistors).Some waveforms are attached: 500 kHz, 1 MHz, and 2 MHz. Do you think the 500 kHz waveform is usable?P.S. I switched to a better oscilloscope.

author: Analog Kid
author_rank: Super Contributor
timestamp: January 20, 2025, 07:59:21 pm
content: Is that ringing from the circuit itself or from the way you've connected your probes to it?Other than that, it looks pretty good.

author: nand2025
author_rank: Newbie
timestamp: January 20, 2025, 08:34:51 pm
content: Attached is a better oscilloscope capture and a photo of the circuit on the breadboard.

author: brucehoult
author_rank: Super Contributor
timestamp: January 21, 2025, 02:03:49 am
content: Quote from: nand2025 on January 20, 2025, 07:37:08 pmVery powerful for the technology available. It and its compatible upgrade the 7600 were the fastest (arguably first) supercomputers in the world for ten years, until Cray left CDC and formed his own company and made the Cray 1 which introduced vector processing very similar to today's ARM SVE and especially RISC-V RVV. The Cray 1 used ONLY four kinds of ICs: a fast expensive power hungry chip containing one 3-input and one 4-input NOR gate, a cheaper slower chip with the same logic gates, a 6ns 16x4 bit SRAM chip, and a 50ns 1024x1 SRAM chip.You can download a complete book on the design of the CDC 6600:http://www.bitsavers.org/pdf/cdc/cyber/books/DesignOfAComputer_CDC6600.pdfAll the above machines would be recognised as "RISC" if they were designed today.

author: nand2025
author_rank: Newbie
timestamp: January 21, 2025, 06:18:52 pm
content: Thanks, brucehoult, a very interesting book!I would like to build a complete set of logic gates: NAND, AND, NOR, OR, XOR, XNOR, NOT, and a buffer.Does anyone know of any good websites or books that cover this, particularly in TTL logic?Thanks, everyone, for the input so far! 🙂

author: brucehoult
author_rank: Super Contributor
timestamp: January 21, 2025, 11:36:21 pm
content: Quote from: nand2025 on January 21, 2025, 06:18:52 pmAnd interesting machine.Another very interesting aspect is the implementation of the OoO using what they called a "scoreboard" rather than the modern technique based on Tomasulo's work at IBM. Tomasulo's algorithm gives higher performance on machines with few registers (or carelessly-written code) because it enables OoO in the presence of WAW hazards, while the CDC6600 has to stall in this situation. But scoreboarding is cheaper to implement and might give just as good results on a modern machine with 32 registers and a compiler that schedules code appropriately (not reusing a register until all instructions using the old value have read their inputs).QuoteIt seems to me that Cray's work demonstrates (and maybe it was common at the time) that youdon'twant or need a full set of logic functions, especially using discrete components or even SSI. As mentioned before, Cray favoured designing using only NOR gates, and I think the 7400 quad NAND is the most popular TTL chip.In many technologies a straightforward AND or OR gate is going to be an inferior gate with poor signal swing and drive capability, so you'd want to follow it by an inverter anyway.I note that Mouser shows the SN7408N (quad AND) having 27ns propagation delay, while the SN7400N (quad NAND) has 11ns delay. There is Extra Stuff needed in the non-inverting gate to get a usable output signal.So a 7408 might be useful for minimising SSI packages if an AND function is the only thing you are doing between outside world inputs and outputs, but it's not something you want to use in a more complex circuit where speed matters.The better idea is to use inverting NAND or NOR gates and keep track of which signals are in positive logic and which are in negative logic.Further to this, the SN7486N quad XOR has 30ns delay. Unless SSI package count is your primary concern you're at least as well off using the 4x NAND or 4x NOR implementation of XOR -- both using discrete components and on an ASIC.

author: Analog Kid
author_rank: Super Contributor
timestamp: January 22, 2025, 12:16:21 am
content: For those of us here in the peanut gallery who are trying to follow along but don't know what all those TLAs mean:OoO:out-of-order executionWAW:write-after-write

author: I wanted a rude username
author_rank: Frequent Contributor
timestamp: January 25, 2025, 01:16:00 am
content: The Nexperia PMBT2369 identified as most promising inthe 6600 articleis actually pretty cheap, about 2¢ in volume, andavailable at JLCPCB. One could make a CPU based on it from less than $100 in parts ... the large PCB required for an elaborate design like the MOnSter 6502 would probably cost more than that ...

author: Tation
author_rank: Regular Contributor
timestamp: January 25, 2025, 01:21:06 pm
content: The Apollo Guidance System (AGC) onboard the Apollo missions to the Moon was built with silicon ICs containing only 2 NOR3 gates. The NOR gate is the "canonical" gate for RTL (the technology used by AGC), as the NAND one is for TTL: other gates should be more complex and show lower performance.Provided that both NOR and NAND gates arefunctionally complete(meaning that any boolean function can be build using only NOR or NAND gates) maybe it would be interesting to build other digital components (say a latch and then a flip-flop) with more discrete TTL gates.Old datasheet for TTL ICs (I remember those from Philips/Signetics for being highly informative) may be of interest for the OP.Regards.

author: David Hess
author_rank: Super Contributor
timestamp: January 25, 2025, 02:28:42 pm
content: More complex TTL functions used transistors as well as gates, like for flip-flops. Integrated RTL and DTL does this also.

author: mawyatt
author_rank: Super Contributor
timestamp: January 25, 2025, 02:55:22 pm
content: ECL/CML Logic started appearing in the mid 60s also. Since this is non-saturating logic it didn't require gold doped transistors or SBD with Baker clamps. Tektronix famously utilized ECL in their analog scope trigger functions which out-performed HP and others for some time!!IBM build their mainframes based upon this logic family and later when the IBM 360 was to upgraded started the investigation into implanting Germanium into Silicon to speed up the transistor for ECL/CML use which became the SiGe BiCMOS processes of later. This never made it into the mainframes tho as midstream IBM switched to massive-paralleled CMOS. Later IBM utilized implanted Ge into CMOS for creating a "Ballistic Transistor" in Strained Silicon, here the purpose was to strain the Silicon lattice to improve the Mean-Free-Path of the MOS channel carriers, thus improving the MOS FET speed.Best

author: David Hess
author_rank: Super Contributor
timestamp: January 26, 2025, 11:50:51 am
content: Quote from: mawyatt on January 25, 2025, 02:55:22 pmEverybody used ECL/CML logic, at least in the form of differential pairs. Diode clamps on the collectors prevented saturation where necessary.Tektronix used tunnel diodes in place of the first comparator, but switched to a differential pair in the 1970s some time after trigger logic was integrated.

author: nand2025
author_rank: Newbie
timestamp: January 27, 2025, 08:25:43 pm
content: Thanks for all the replies - very interesting!I spent a little more time making an AND gate and improving the layout on the breadboard.Attached is a photo of the breadboard, along with the input and output waveforms at 1 MHz.1 MHz was my original goal, so I'm happy with that.Thanks for all the help in getting to this point!

author: brucehoult
author_rank: Super Contributor
timestamp: January 28, 2025, 04:08:40 am
content: That looks like about 40ns propagation delay, which is not bad.Typical 5-stage pipelined (or 5 clock multi-cycle) RISC CPUs have around 30 gate delays per clock, so you might not be able to reach an actual 1 MHz operating speed with gates like that. On the other hand a borderline insane design such as the Pentium 4 was apparently around a dozen gate delays per pipeline stage -- that's just barely enough for a good 32 bit carry-lookahead adder.

author: gcewing
author_rank: Regular Contributor
timestamp: January 28, 2025, 07:35:14 am
content: Quote from: golden_labels on January 18, 2025, 08:23:07 pmInterestingly, the LS TTL family seems to do without an input transisor at all and just uses a diode AND gate made from shottky diodes.

author: chilternview
author_rank: Frequent Contributor
timestamp: January 28, 2025, 07:45:27 am
content: Quote from: gcewing on January 28, 2025, 07:35:14 amYes LS used diodes (schottky) as they were faster than multiemitter transistors and had higher breakdown voltages (the transistor reverse B/E breakdown voltage was only just better that the maximum supply voltage). The 74F series, which I worked on, had very thin base junctions, breakdown was typically 6v.