need high resolution PWM - Page 1
Forum section: electronics / general

author: tatus1969
author_rank: Super Contributor
timestamp: March 23, 2019, 01:43:23 pm
content: For an instrument that I am desigining, I need a PWM at 450kHz with good linearity and resolution (equivalent to at least 14 bits). At the moment, I have a 16-bit DAC with 900kHz update rate and output filtering. The PWM is then generated in the classic way by a triangle generator and a comparator. I am also opting for an additional feedback loop for linearization (cancel out comparator deadtime). The circuit is then used to create a mix of DC and sinusodial AC amplitudes from DC to 50kHz.Using a DAC to convert the digital information to analog, and then to use triangle+comparator to then make it "digital" again adds more cost and complexity to the solution that I feel would be necessary. But a pure digital / counter based approach isn't possible either. I wonder if there are affordable chips dedicated to this task, does anyone know? I need good linearity and resolution. Precision gain and frequency flatness aren't important, that is controlled by other means.

author: NorthGuy
author_rank: Super Contributor
timestamp: March 23, 2019, 02:27:00 pm
content: 14-bit at 450kHz is about 120 ps. I know newer dsPIC33C can do 250 ps resolution (according to the data sheet), just one bit short of what you want.

author: iMo
author_rank: Super Contributor
timestamp: March 23, 2019, 02:47:10 pm
content: STM32F334 can do 217ps.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 23, 2019, 11:49:53 pm
content: Quote from: tatus1969 on March 23, 2019, 01:43:23 pm(1/450k)/2^14 = 135.63psInfineon XMC parts specify 150ps PWMsI think TI has some 180ps DSPs too....

author: tatus1969
author_rank: Super Contributor
timestamp: March 24, 2019, 12:04:34 pm
content: Thanks for your answers, especially the STM32F334 was new to me as I didn't know that ST also has devices with high resolution timers now.I should have mentioned that I already have an STM32 in the design (STM32L4R9). I need that one because the application requires significant processing power (need for on-the-fly floating point DFT with two channels simultaneously) and I also have two sigma-delta ADCs that this micro can directly support.The DAC/comparator solution will be around 5..10€ and gives me 16 bits on paper, but I expect that a full digital solution would have a better phase noise performance. I don't want to add another micro or DSP though, so I'll likely stick with my current solution. I was hoping for a magic block like "SPI in" "PWM out", but I'm not aware of such a thing.The task is quite challenging: I need to superimpose a sinusodial AC in the millivolts range on a 0..30V DC voltage. I'm using PWM because I also need high output current. And the frequency analysis also requires phase coherency, which is why I am using the microcontroller to shape the waveform.EDIT: just had a look at XMC4400, they also have sigma delta modulators, run at 120MHz, and are comparable or better in price. As I am an STM32 "native", I had started with that but I guess that I need to reconsider now...

author: NorthGuy
author_rank: Super Contributor
timestamp: March 24, 2019, 12:56:42 pm
content: You don't really need floating point for DFT.IMHO, instead of using many MCUs stitching them together through I2C, SPI or alike, it's usually better to chose one MCU which does everything you need. Even if you're an STM prisoner, you should be able to find a single STM to do all your tasks.

author: MT
author_rank: Super Contributor
timestamp: March 24, 2019, 02:37:36 pm
content: Quote from: tatus1969 on March 24, 2019, 12:04:34 pmThere is also the STM32H743 and H750 etc who have the computing power and HRTIM1 but runs at max 400Mhz instead of F334 4.6Ghz.

author: tatus1969
author_rank: Super Contributor
timestamp: March 24, 2019, 05:56:03 pm
content: Quote from: NorthGuy on March 24, 2019, 12:56:42 pmI'm using the Goerzel method on up to 32768 samples, which is fast but numerically not very stable. I may try integer arithmetic, but that part is working very well and other things need more attention right now.Quote from: NorthGuy on March 24, 2019, 12:56:42 pmThat's definitely my goal. And multiple MCUs and possible other logic like CPLDs or FPGAs make the field firmware update procedure much more complicated.I'll stick with the analog solution for now, as it has another important advantage. The feedback loop that I have mentioned is not only for linearization, but it also provides power supply ripple rejection. In a fully digital solution, I'd have to emulate this in the microcontroller as well, and I'm not sure if I could achieve a comparable performance.Quote from: NorthGuy on March 24, 2019, 12:56:42 pmNot a prisoner, but getting acquainted with new toolchains and architectures takes time that I can't use to concentrate on my real task: designing this instrument. I'd rather go the second best route if that saves me time.

author: tatus1969
author_rank: Super Contributor
timestamp: March 24, 2019, 05:58:47 pm
content: Quote from: MT on March 24, 2019, 02:37:36 pmThat timer is too slow at 2.5ns, and these chips only seem to have a single sigma delta demodulator input...

author: nctnico
author_rank: Super Contributor
timestamp: March 24, 2019, 06:10:02 pm
content: Quote from: tatus1969 on March 23, 2019, 01:43:23 pmWhy aren't you using a class-D audio amplifier chip?http://www.ti.com/audio-ic/amplifiers/speaker-amplifiers/overview.htmlThis one for example (a completely random pick) can deliver over 30W, has 111dB of dynamic range (around 18 bit) and a bandwidth of way over 50kHz.http://www.ti.com/product/TAS5825MYou'll have to look for one where you can disable the DC offset fault detection.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 24, 2019, 09:03:24 pm
content: Quote from: tatus1969 on March 24, 2019, 12:04:34 pmThe Class D amplifier mentioned above, is probably the nearest to Serial IN, (i2s) to PWM out.Quote from: tatus1969 on March 24, 2019, 12:04:34 pmWhat range of AC (mV, Hz) do you need to superimpose on the DC, and at what current ?Another approach could be to take a standard SMPS, which has a ramp/comparator built in, and control the DC and AC sides separately.A high resolution DAC sets DC levels, and then a scaled modulator DAC can set the AC modulation.If the AC is always small, you can use a DC SMPS for the main DC control and then a linear regulator (which has low voltage drop & thus tolerable? power loss) for the AC modulate.

author: nctnico
author_rank: Super Contributor
timestamp: March 24, 2019, 11:25:29 pm
content: The method of PCB.Wiz also seems like a good approach to me. Generate the DC level with a regular power supply and provide the AC part using a seperate path. A transformer could to the job and this also provides a way to step the AC voltage down. For example: using a class-D amplifier to drive a 10 to 1 transformer gives a lot of dynamic range for small signal levels. A suitable transformer would be a gap-less one intended for building a forward converter. These are standard off-the-shelve parts from Coilcraft or Wurth (and probably others as well).

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: March 25, 2019, 06:14:21 am
content: 16Bit SPI @ 50MHz would do that for you, you can use up to 8 words as your PWM duty cycle, also it's free in your STM32.Also you can use circular DMA to free update the PWM

author: OwO
author_rank: Super Contributor
timestamp: March 25, 2019, 08:00:07 am
content: Does the output have to be fixed-frequency PWM or is delta-sigma modulation acceptable too? It's very easy to implement on a STM32, you just need to compute the "bitstream" in chunks and use the DMA to stream the bit values onto a GPIO. You can easily get modest dynamic range this way, for example 16bit equivalent @ 1MHz toggle rate is easily achievable.

author: tatus1969
author_rank: Super Contributor
timestamp: March 25, 2019, 09:55:48 am
content: Thanks to all your ideas, and I'm open in all directions.Here is what the amplifier specifically needs to do:- drive complex loads down to 1 milliOhm- source current into load and sink current from it- DC 0.0 to 30V- sinusodial AC of 1mV to 5V (at least, better full range) and 1mHz to 50kHz- current is +/- 5AIt is a device meant for DIYers, so every penny counts to keep the BOM cost in a reasonable region.I'll tell more about this in this forum soon. At the moment I need to stay fuzzy as this something that is new to the market and I don't want our Chinese copier friends to be faster than me. It's maybe interesting to mention that such instruments exists in the professional segment, starting at USD8000.Quote from: OwO on March 25, 2019, 08:00:07 amThat's an interesting idea, but without calculating it my intuition tells me that I can't get 16 bits for a 50kHz signal from a 1MHz bitstream. My sigma delta ADCs achieve just that but run at 20MHz.Quote from: ali_asadzadeh on March 25, 2019, 06:14:21 amThe SPI itself is not my problem, that's running well. Although I can't use DMA for it, because the STM32's SPI block does not allow me to insert adjustable pauses between packets. I ended up doing the (integer) waveform calculations and SPI feeding in an interrupt at 900kHz. The microcontroller is surprisingly powerful and only needs 10% of its time for all that.Quote from: nctnico on March 24, 2019, 06:10:02 pmQuote from: PCB.Wiz on March 24, 2019, 09:03:24 pmI actually have one in service in my proof-of-concept build, a Hypex UcD180HG. These use a hysteretic approach that should theoretically have less problems driving my low impedance load. I don't see any instability, which is good, but it a) introduces significant nonlinearity at lower frequencies, and b) it is designed for a symmetrical supply. The latter causes issues when sinking load current, ending up in the need of having dissipative supply voltage limiters even when it is sourcing current. The solution needs to run from a single supply and be able to operate down to the negative rail. And all class D amps that I have looked into have classic output stages with switching deadtime, and that is a linearity killer for power stages operating in two quadrants. If my concept turns out to be working, then it will almost completely eliminate that (at the expense of higher idle current). I'm actually thinking of making a later spin off in form of a high end audio amp :-)Quote from: PCB.Wiz on March 24, 2019, 09:03:24 pmQuote from: nctnico on March 24, 2019, 11:25:29 pmMy requirements don't allow that, as the AC isn't always small. But I might end up with a hybrid approach if I can't get a single output stage to meet my requirements, like having a low resolution class D power stage tied to a second high resolution / low voltage "servo" class A amplifier. But that could make the solution unaffordable for its target audience.

author: OwO
author_rank: Super Contributor
timestamp: March 25, 2019, 10:59:05 am
content: Instead of a ramp gen + comparator I would at least use a feedback+integrator+hysteresis analog delta-sigma modulator which will give you better linearity at the upper and lower extremes of the signal swing, as well as killing two birds with one stone by also adding the negative feedback you need. It would also likely use less parts than a classic PWM modulator, consisting of only ~2 op-amps.EDIT: Also don't make the mistake of thinking you can keep "clones" out by secrecy, it doesn't work that way. There are "real engineers" in China, given the idea they can engineer their own solution that costs less and performs similarly. The only way to do things is make your product competitive as well in terms of bang for buck.

author: ejeffrey
author_rank: Super Contributor
timestamp: March 25, 2019, 02:30:42 pm
content: +1 on using delta sigma output over pure PWM. For many applications that will be strictly better and the computation overhead can be very small. At least if you are filtering anyway. If you are trying to switch transistors that can't switch at higher frequency you have to weigh the noise budget more carefully, but often even then delta sigma is better even if it degrades your high frequency SNR slightly.

author: tatus1969
author_rank: Super Contributor
timestamp: March 25, 2019, 10:34:46 pm
content: Quote from: OwO on March 25, 2019, 10:59:05 amQuote from: ejeffrey on March 25, 2019, 02:30:42 pmSounds like a good idea, I'll definitely evaluate that. The MOSFET's switching transitions will be around 20 to 50ns, and the delay will be maybe double of that. Switching action creates more heat than usual with my intended topology, and I cannot see at the moment whether PWM or sigma delta will be more beneficial here. I'll design my first attempt such that I can easily switch between them. Which sampling clock frequency would you choose? Available sigma-delta class D audio amplifiers seem to use 6 .. 10MHz.Good SNR is especially important at low frequencies. I can easily average across multiple periods at 10kHz, but that's not an option at 1mHz :-)Quote from: OwO on March 25, 2019, 10:59:05 amThat's exactly why I am hinding the idea at the moment. I'm an indivdual and they are many, my only chance is to use my time advantage.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 26, 2019, 12:12:34 am
content: Quote from: tatus1969 on March 25, 2019, 09:55:48 amIf you need to go cleanly to 0V, a common trick for universal device programmers, was to generate a slight negative rail, of the smallest needed to reach 0V. (eg -1.2V or -2V)If you want that power range, and low price, I'd still say Class D is the best choice, as you get to piggyback on the big volumes, but you may need to tweak/enhance designs to get DC operation.You have also not mentioned measure/control of current, which could be harder in Class D designs.Is your load passive (like a battery) or active (like operating electronics) ?

author: tatus1969
author_rank: Super Contributor
timestamp: March 26, 2019, 01:28:05 pm
content: Quote from: PCB.Wiz on March 26, 2019, 12:12:34 amI want to avoid that if possible, but doing that would extend the usability of the device even further.Quote from: PCB.Wiz on March 26, 2019, 12:12:34 amBoth voltage and current are controlled via other parts of the circuit (the MCU adjusts the DAC output waveform accordingly), which is why the only task of the power amp is to provide linearity and SNR. Precise gain is not necessary.Quote from: PCB.Wiz on March 26, 2019, 12:12:34 amPassive, but complex of any kind (both reactive and capacitive).

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 27, 2019, 06:23:58 am
content: Quote from: tatus1969 on March 26, 2019, 01:28:05 pmA useful part to look at could be the TI TAS3251 - that has 24b DACs included, and i2s interface, 36V and ~300WYou would need to do a careful DC level shift on the coupling, and probably add an external ADC to verify/feedback DC offset errors.For more discrete solutions, Audio DACs can go to above 192KHz sample rates (TI part is 96kHz) and the specs I checked give 0Hz as minimum.Their DC may not be super-stable, but it does look like they go to DC.

author: tatus1969
author_rank: Super Contributor
timestamp: March 27, 2019, 12:41:55 pm
content: I have to update one of the requirements: 14 bit DAC resolution is definitely not enough, I'll have to go for at least 20 bits. I was chasing noise problems in my demonstrator (using a 16 bit DAC), which made this clear to me. The picture shows the DAC value in blue, and red is the measured DC current into a 50 milliohm load (no AC amplitude). Clearly not good enough.Quote from: PCB.Wiz on March 27, 2019, 06:23:58 amI'll definitely try that, as i2s naturally gives me enough resolution, and the chip seems to be DC capable. The power stage is closed loop, which is my major concern as the loop is certainly not tuned to drive an ultra low impedance load.

author: Yansi
author_rank: Super Contributor
timestamp: March 27, 2019, 12:46:41 pm
content: Are you the proffesor that has written us on the st support service recently about the hrtim and GaN?

author: FrankBuss
author_rank: Unknown
timestamp: March 27, 2019, 01:17:09 pm
content: I don't think it is a good idea to use PWM for the output. There is a reason why most good power supplies are using a linear output stage with big heat sinks.A 20 bit DAC with 900 kHz gets really expensive, and I doubt it would help, because then you would need very accurate comparators with very low hysteresis, and a very fast switching output stage as well. And it would cost more than linear regulation with a big MOSFET and heatsink.

author: tatus1969
author_rank: Super Contributor
timestamp: March 27, 2019, 02:43:23 pm
content: Quote from: Yansi on March 27, 2019, 12:46:41 pmNo :-) But I have actually written you (ST) in the past, because that STM32 has problems getting the DFSDM channels in sync. Even when I start them in consecutive instruction cycles, they exhibit varying phase shift. I use two channels and need them to sample them synchronously, because I am measuring the phase between the channels. It is only 1..2 degrees at 50kHz if I remember correctly, but this is significant in this application. Haven't heard back from ST sadly, my expected annual volumes seem to be low (1k .. 10k)...Quote from: FrankBuss on March 27, 2019, 01:17:09 pmThey do that to keep noise levels down, but analog noise is not my problem as you can see from the graph. On the left, you can see the analog noise which is only a few 100 microamperes. This includes the class D audio amp that is in the system, and it creates *huge* output ripple.But try to get a linear amplifier drive a 1 milliohm load - this is a really challenging task. That's why my plan is to achieve enough "stiffness" in the H bridge itself, which should allow me to reduce feedback gain. And I should even be able to live with nonlinearity, because the system uses frequency analysis.EDIT: And I still would need the DAC.Quote from: FrankBuss on March 27, 2019, 01:17:09 pmI'll use a 24 bit I2S DAC for audio applications, their prices are reasonable. The output stage is custom and uses a new method to elimininate dead time. That method already uses 4.5ns comparators, 2€ a piece.Quote from: FrankBuss on March 27, 2019, 01:17:09 pmI'm not so sure. Power dissipation would be 5A x15V30V =75W150W meaning substantial heat sink and probably fan. And power consumption also doubles requiring a bigger PSU brick.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 27, 2019, 07:22:15 pm
content: Quote from: tatus1969 on March 27, 2019, 12:41:55 pmThinking more about that any-load dictate, you may be better to move from Audio-stages which seem to have just under 100 mΩ, to a much 'stiffer' sync SMPS design.Quote from: tatus1969 on March 27, 2019, 02:43:23 pmThat original 30V raw power has to come from somewhere, usually the AC mains.So you modulate that upstream power supply to give just the voltage you need, to run a linear regulator, thus slashing the linear-stage watts.Quote from: tatus1969 on March 27, 2019, 02:43:23 pmThat infers you need very good current control, as a deviation of just 5mV into that 1mΩ* ohm load, hits your 5A current limit.* You must also have exceptionally short leads

author: tatus1969
author_rank: Super Contributor
timestamp: March 28, 2019, 09:17:36 am
content: Quote from: PCB.Wiz on March 27, 2019, 07:22:15 pmI had looked into the TAS3251 datasheet, and that number actually ended that route.Quote from: PCB.Wiz on March 27, 2019, 07:22:15 pmAs the system operates in two quadrants (both sinking and sourcing AC and DC current), this would need two (two-quadrant capable) DCDC's with the linear stage sandwiched between them...Quote from: PCB.Wiz on March 27, 2019, 07:22:15 pmThe system uses a 4-terminal connection. The (all digital) control loops in the demonstrator have already shown that they maintain stability even when shorting the outputs with crocodile clips (after voltage sensing). That's probably in the order of 1milliohm. But I have an additional fast current supervisor that would kick in otherwise. The only problems that I see at the moment are DAC resolution and a stiff yet cost effective power stage.

author: dmendesf
author_rank: Frequent Contributor
timestamp: March 28, 2019, 10:37:11 am
content: I had this problem with the ADCs... If I Started them one after the other I got a few degrees of phase delay between them. Solved it by disabling the ADC clock, enabling the ADCs and then enabling the ADCs clocks.Enviado de meu moto g(6) plus usando o Tapatalk

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 28, 2019, 08:20:29 pm
content: Quote from: tatus1969 on March 28, 2019, 09:17:36 amSync SMPS are inherently two quadrant if driven in fixed PWM mode, so you just need to find low mOhm Dual MOSFETS, and a matching driver.HP8S36TB Rohm is a good price at $0.56270/1k but is 30V rated ( DUAL 30V 2.4 mOhm @ 32A, 10V)Infineon have Audio class D pre-drivers that use external MOSFETS with choice of Audio or PWM in, but there are many SMPS drivers out there.... ?

author: Yansi
author_rank: Super Contributor
timestamp: March 28, 2019, 10:28:01 pm
content: International rectumfryer also has some interesting ones.. (IRS2092, etc...)

author: tatus1969
author_rank: Super Contributor
timestamp: March 29, 2019, 07:40:57 am
content: Quote from: dmendesf on March 28, 2019, 10:37:11 amThanks, I'll try this out!Quote from: PCB.Wiz on March 28, 2019, 08:20:29 pmSure, but two DCCM SMPS plus an analog amplifier is too much in terms of BOM and cost. I plan to fulfill all requirements with a single power stage. Thanks to all your support I will make the first attempt with CS4334-KSZ (24bit audio DAC), sigma delta modulation, and my own proprietary H bridge topology that (if my idea works) will eliminate switching deadtime entirely.Quote from: PCB.Wiz on March 28, 2019, 08:20:29 pmQuote from: Yansi on March 28, 2019, 10:28:01 pmUsing such a driver is actually quite tempting, as my own approach is quite complex. But as said, they all introduce switching deadtime and that is a significant source of nonlinearity.

author: r0d3z1
author_rank: Regular Contributor
timestamp: March 29, 2019, 08:35:21 am
content: Quote from: imo on March 23, 2019, 02:47:10 pmI also vote for F334, I have already used it for the digital control of a DC/DC at 300khz, the resolution is quite impressive. HRTIM is not strightforward but it worth it.

author: Siwastaja
author_rank: Super Contributor
timestamp: March 29, 2019, 09:09:33 am
content: Quote from: r0d3z1 on March 29, 2019, 08:35:21 amIt's great, I like it, and IMHO HRTIM is more straightforward than most other STM32 peripherals... At least when considering the possibilities / ease of use ratio. It's not completely trivial, but it's very flexible, and its design isn't brainfucked. I have a feeling that had they copypasted one more slave timer with output module (6 instead of 5) it could have become even more widely usable.

author: SteveyG
author_rank: Unknown
timestamp: March 29, 2019, 09:12:43 am
content: The requirements from what I've read look a little steep, have you taken a step back to see if there is a general alternative for what you're trying to do?IMO, when you start looking for such specialised parts, 90% of the time there is a different solution that avoids these rare/expensive items.

author: tatus1969
author_rank: Super Contributor
timestamp: March 29, 2019, 01:25:08 pm
content: Quote from: Siwastaja on March 29, 2019, 09:09:33 amNow that I know that I will need at least 20bits DAC resolution, any kind of HRTIM is out. The audio DAC will very likely do that job.Quote from: SteveyG on March 29, 2019, 09:12:43 amI mentioned earlier, there is professional gear that does what my system is doing - starting at USD8000. I am collaborating with a large technical uni that has these instruments, and they are making comparison measurements right now. The first results look very promisingQuote from: SteveyG on March 29, 2019, 09:12:43 amI try to avoid that wherever possible, as I know the availability nightmare that I would steer myself into when in mass production. At the moment, it is only special with regards to the microcontroller, an audio DAC, and some fast comparators and precision opamps [EDIT: plus SI8423 iso drivers].

author: Siwastaja
author_rank: Super Contributor
timestamp: March 29, 2019, 03:33:29 pm
content: Li-ion battery AC analysis?

author: tatus1969
author_rank: Super Contributor
timestamp: April 01, 2019, 08:25:56 am
content: Quote from: Siwastaja on March 29, 2019, 03:33:29 pmSorry, I can't disclouse at the moment what it is intended for. I need a few months to build prototypes that I can show here or maybe even sell. They will have a documented control interface (and open source USB library) that will allow many different applications, for example plotting the voltage/capacitance dependency of high capacitance MLCC capacitors. I plan to keep hardware and firmware confidential though, as I think that Chinese copying will be a major thing.I just found the source of the excessive measurement noise that I posted a picture of earlier. It was not (only) insufficient DAC resolution, but rather the algorithm that computes the sinusodial waveform. Updating this at 900kHz and using only a 32-bit integer for the phase is *not* sufficient to computer a 10Hz sine wave. Upgraded to 64 bits, working perfectly now.

author: Yansi
author_rank: Super Contributor
timestamp: April 01, 2019, 01:54:58 pm
content: Quote from: tatus1969 on March 29, 2019, 07:40:57 amBut they DO NOT use strict constant frequency PWM as their modulation scheme. PWM modulation is plain bad in the first case.Deadtime is part of the feedback loop. Look closely how those drivers work. They integrate the output voltage, deadtime is pretty much cancelled out. You better worry about the linearity of the output filter.

author: tatus1969
author_rank: Super Contributor
timestamp: April 01, 2019, 02:12:11 pm
content: Quote from: Yansi on April 01, 2019, 01:54:58 pmSimilar to classical linear amps, avoiding nonlinearity in the first place gives the feedback opamp less work to do and improves THD. You can consider my approach being a combination of class A and class D.

author: tatus1969
author_rank: Super Contributor
timestamp: April 02, 2019, 08:43:01 am
content: Thinking about sigma delta modulation for the power amplifier... I'll need a clock in the order of 10MHz or higher. A first order SD modulator will then cause the H bridge to switch at the same rate, which will cause way too much power dissipation due to switching loss. I need to keep that below 500kHz. I don't see a simple way to reduce the frequency content of the generated bit stream, although there seem to be a few approaches. I see myself ending up adding an FPGA to the system to model that (although that would also eliminate the DAC). Also, sigma delta introduces quantization noise that pure analog PWM doesn't have.I've also looked into self-oscillating topologies aka Bruno Putzey / UcD. It appears that these do not follow the input signal well according to my first ballpark simulations (picture). This leads me to think that I would either get too much load dependency and thus nonlinearity, or need to add another global feedback loop.I think that I will revert to analog PWM with linearization feedback tapped at H bridge. Other than with the UcD approach, the output filters cannot be part of this feedback because that will cause instability with low impedance loads. I plan to make the LC filters as linear as possible instead, by overdimensioning L, and using voltage independent film capacitors.Guys, does this sound reasonable?

author: Yansi
author_rank: Super Contributor
timestamp: April 02, 2019, 10:31:17 am
content: Why don't you try the second order modulator, as presented by me above? (IRS2092 for example, being a cheap integrated solution of that). There is a ton of application notes about it, including implementing these from discrete components.The strange circuit in your last post is well known to misbehave. (I have tried bulding several amplifiers with this principle, with not that much of a success) I think that self-oscillating structure (feedback after the LC filter) was patented by Philips few decades ago, but not certainly sure - please correct me if anyone knows exactly.I do not think you can make a single ended class-D much better than that second order modulator. The principle is industry-wide accepted and used across multiple brands power amplifiers.I think there is a good reason why straight PWM is not used and sigma-delta isn't any good either, due to the switching loss as you have correctly identified.

author: tatus1969
author_rank: Super Contributor
timestamp: April 05, 2019, 09:58:20 am
content: Quote from: Yansi on April 02, 2019, 10:31:17 amI've tried to model the IRS2092 (which is a poor mans 2nd order self oscillating sigma delta if I see this correctly) but could'nt make it to work as it should. I then created a 1st order model from scratch, which works as it should. Is there any benefit of a 2nd order modulator in my situation?I had to realize again that sigma delta is not an option for me. I can't afford a high ratio of switching frequency to input frequency (that would allow clocked sd modulators), and I also can't work with the reduced switching speed of the self oscillating modulatorat high excursions. This is because I have to set the output filter cutoff frequency to at least 50kHz. And I have to use high Q LC filters that get overly excited in this situation. This brings me back to PWM and Putzeys being the only options. I'll keep you updated

author: mrflibble
author_rank: Super Contributor
timestamp: April 05, 2019, 12:53:47 pm
content: Quote from: imo on March 23, 2019, 02:47:10 pmOooh, nice! Didn't know that one yet. Guess what disco/nucleo board I will use to pad the next Mouser or Digikey order?Also, minor nitpick: according to the datasheet that F334 runs at a boring clock rate of 144 MHz and does not have any 4.6 GHz bits in it (as a previous post would seem to suggest). That would have been an interesting waste of process technology if it did.Quote from: tatus1969 on April 05, 2019, 09:58:20 amDelta-sigma does not automatically means that your output stage has to toggle at the same rate as your internal stages. You can use a multi-bit quantizer, and let that n-bit result be the PWM value for that period. So an example would be to have an internal rate of 1.280 MHz, but with a 6-bit quantizer. Which would translate to a 6-bit PWM with a toggle rate of 20 kHz on your 666 nC gatecharge mosfets, thus keeping those evil switching losses at an acceptable level.Also, are all topologies (CIFF, CIFB, etc) a no-no, or just some? Anyways, even if you end up with straightup PWM for whatever top-secret reason, I would suggest you add some properly scaled pseudo-random noise at the quantizer stage. The bad stuff: raised noise floor. The good stuff: those pesky spurs at harmonics of your PWM frequency are waaay down. Cannot speak for your application, but so far in every case I had to make the call the advantages of the added PRNG far outweighed any drawbacks. And the PRNG doesn't even have to be fancy. At first I expended entirely too much time & effort making sure those random bits were nicely polished high quality random bits. Only to find out after more experimentation that any old LFSR would do just fine. You just have to make sure the LFSR period is sufficiently large for the given application, but that constraint is trivially met.Minor suggestion: it might help if you could provide a minimal spice schematic of the load. No need to divulge what kind of top secret thingy you are trying to build. Just model the nasty difficult to drive aspects of the load. And if you are targeting a variety of loads, then lets say the top 3 nasty loads. Basically, take a bunch of R,L,C's, put in representative configurations. Then given those configurations, for what ranges of R,L,C values are you trying to do whatever it is you are trying to do. Ifthatis already a top secret it's kind of difficult to give meaningful suggestions other than"Use delta-sigma, it's awesome!".

author: Siwastaja
author_rank: Super Contributor
timestamp: April 05, 2019, 04:07:13 pm
content: Quote from: mrflibble on April 05, 2019, 12:53:47 pmThe HRTIM output generation counters run at 4.6GHzequivalent(yes, that's on the front page of the datasheet). Equivalent, because it isn't an actual binary digital counter; it's not clocked on an actual digital 4.6GHz square wave clock signal. Instead, it's some sort of analog implementation, and it runs self-calibration constantly against varying operating conditions. The key point is, it can time your output changes with 1/4.6GHz intervals, and it's presented to the programmer like it was a digital counter clocked from a 4.6GHz signal (but, unsuprisingly, with more jitter, and the step sizes probably showing slight non-linearity). There are some extra limitations for minimum pulse width as well.

author: jmelson
author_rank: Super Contributor
timestamp: April 05, 2019, 10:52:30 pm
content: Quote from: tatus1969 on March 23, 2019, 01:43:23 pmHmmm, the totally simple way to do this has a counter running at 7.37 GHz. This sounds QUITE challenging!There possibly could be some solution with SERDES moduies on a FPGA with phase-shifted clocks.But, sounds like a very tough problem.Jon

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 06, 2019, 03:25:28 am
content: Quote from: Siwastaja on April 05, 2019, 04:07:13 pmYes, the simplest way to get deep sub-ns is to use CMOS gate delay lines, (just tapped chains of gates) - very simple, but they do vary with Vcc and temperature, hence the calibration step most mention.I've seen one Sanken MCU part that did a 1GHz PLL for a 1ns counter based PWM. (Not cheap and niche ...)

author: tatus1969
author_rank: Super Contributor
timestamp: April 06, 2019, 10:08:45 am
content: Quote from: jmelson on April 05, 2019, 10:52:30 pmI have moved to an analog solution, and a 192kHz / 24 bit sigma delta audio DAC will deliver enough resolution without having to deal with (quasi) GHz timers.Quote from: mrflibble on April 05, 2019, 12:53:47 pmThat sounds actually very interesting, and may be worth the necessary FPGA between MCU and power stage. I'm on a starting-to-learn-beginner level with respect to sigma delta, may I ask some questions?- that approach above would result in a constant-frequency PWM, but I can imagine that a more complex mapping from multi-bit SD state to ON / OFF periods could allow for some frequency spreading that would help EMI. I have no practical idea of that though.- when moving from an all analog PWM duty cycle at 500kHz to this time discrete solution, wouldn't I have to increase power stage switching frequency significantly?- do I understand your proposal correctly that it would require a multi-bit DAC, or have you thought of an alll digital solution? In the latter case, I have no possibility to create linearization feedback from the power stage. In the earlier case, I would expect to introduce DAC nonlinearity, and would need some kind of low pass filtering.- when going that route, what is the actual benefit that I can expect over a PWM?Quote from: mrflibble on April 05, 2019, 12:53:47 pmThat top-secret reasons are- lack of profound knowledge of sigma delta modeling.- wanting to make a solution with basic discrete components because of availability, price, and flexibility. If I would jump on integrated solutions like IRS2092, there's not much to tweak if that misbehaves.- the demonstrator has already proven feasibility, the only identified problems were amplifier linearity when having to drive milliohm loads, and output filter oscillations because of dropping switching frequency when approaching the voltage rails.Quote from: mrflibble on April 05, 2019, 12:53:47 pmThere are no no-no's, I'm open to everything that will help. So far the only topologie that seems to be able to meet my goals is DAC + analog PWM + low-deadtime power stage + moderate feedback before the output filters + overdimensioned output filters.Quote from: mrflibble on April 05, 2019, 12:53:47 pmI know what you mean. My last visit in the EMC chamber at our local TÜV office was a big fail - 30db above the limit. That should be solved now, fingers crossed for my next visit. Luckily this application requires multi-stage output filtering anyway and the final system will be metal enclosed.Quote from: mrflibble on April 05, 2019, 12:53:47 pmI'd say, a typical representation of the worst case load is a voltage source of 2 to 25V, with a 1 milliOhm resistor at it's output. My instrument then has to drive current into that resistor, with that current having DC and AC amplitudes of up to +/- 5A with frequencies from 1mHz to 50kHz.

author: nctnico
author_rank: Super Contributor
timestamp: April 06, 2019, 10:29:57 am
content: So it is a battery analyser. That means the output swing (in voltage) is actually very low and so is the power. I think you are going at this the wrong way entirely. I have designed/made similar devices (some that needed to go up to 300VDC) and I always used a capacitor in series with the current source to get rid of the DC offset (with a fast settling circuit at startup). That way you can use a simple but precisely controlled linear current source. Since you'll be measuring the AC voltage across the battery and the AC current through it any voltage drop across the capacitor won't matter as long a the current source doesn't go outside it's output voltage. Another problem I see it resolution. If you have 14bit to go up to 25V then you'll have 1.5mV per bit. With a 1m Ohm resistor as a load you'll have very few bits left to construct a clean AC waveform. Unless you do some hefty filtering but the filter characteristic itself will also depend on the load. Either way at low frequencies you'll be applying a stepped waveform instead of a (somewhat) pure sine.

author: tatus1969
author_rank: Super Contributor
timestamp: April 06, 2019, 11:00:49 am
content: Quote from: nctnico on April 06, 2019, 10:29:57 amWhat capacitor should that be that can couple 5A AC at 1mHz? For the same reason, I also can't use a transformer.Quote from: nctnico on April 06, 2019, 10:29:57 amI've noticed this mistake in an earlier post and upgraded to 24 bits.EDIT:Quote from: nctnico on April 06, 2019, 10:29:57 amThat's not always true. That 1mOhm load was meant to describe the worst case situation for the amplifier. I also need to be able to deliver full 1 to 27V DC and AC for higher impedance loads.

author: nctnico
author_rank: Super Contributor
timestamp: April 06, 2019, 11:34:51 am
content: You can always consider a hybrid system where you have a charger & dc load for the low frequencies and a typical LCR meter circuit for the higher frequencies. This will greatly simplify your system.A ceramic or polyester film capacitor can handle quite a bit of current as long as the ESR isn't causing problems. In a typical half-bridge forward converter (like any PC power supply) the current through the bridge is fed through a capacitor to prevent DC current through the core. Depending on the impedance of the measurement system you use 10uF to 100uF should get you in the single digit Hertz range. I recommend using a PET capacitor because these have an ultra low leakage current.

author: tatus1969
author_rank: Super Contributor
timestamp: April 06, 2019, 03:41:27 pm
content: Quote from: nctnico on April 06, 2019, 11:34:51 amYou're assuming that it is a battery analyser. I'll be able to tell about what it is soon, but at the moment I afraid I can't. Your assumption seems to be leading to false conclusions here.Quote from: nctnico on April 06, 2019, 11:34:51 amMy concern of the capacitor wasn't so much ESR, but it's actual value. For it to have let's say 10V of voltage drop at 1mHz and 5A, the required capacitance would be ~ 80 Farads.

author: nctnico
author_rank: Super Contributor
timestamp: April 06, 2019, 03:56:24 pm
content: Still if the load is a voltage source you'll need to be able to sink and source current from it. I don't see that happening with a switching mode amplifier with a big DC offset. You'll need to dissipate the power you pull from the load somewhere if you want to send a true AC current through the load while dealing with a large DC offset.

author: tatus1969
author_rank: Super Contributor
timestamp: April 06, 2019, 06:33:38 pm
content: Quote from: nctnico on April 06, 2019, 03:56:24 pmThat switching mode amplifier is basically a step-down DCDC converter with forced continuous conduction, these are inherently two-quadrant capable and feed back energy into their supply. The instrument then has a dissipative bus voltage limiter that starts PWMing a MOSFET, which in turn connects a power resistor across the main supply.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 06, 2019, 08:22:02 pm
content: Quote from: nctnico on April 06, 2019, 10:29:57 amI tend to agree, this is best designed as a current amplifier, not a voltage amplifier and could even be done as a 4 terminal system that uses a series resistor 'dummy load' approach to avoid the need to try to drivemillivollts into milliohmsjust to try to get your Stiff-DC-Source, into the teensy transfer zone. ie Even if you can do that, the noise-floor will dominate the current result.,A 4 terminal system means you need 2 good ADCs and a current meter, tho that could be a 3rd ADC across the known and stable series resistor.A quick Digikey search findsCSR2512C0R05F Riedon RES 0.05 OHM 1% 3W 2512 16,000 - Immediate $0.18354/2,000 50 mOhms ±1% 3W ±50ppm/°C5A into 50mOhms is 1.25 Watts and needs 250mV of swing (and that lands you in some nice current-ADC specs, high volume parts)Quote from: tatus1969 on April 06, 2019, 03:41:27 pmyes, OUTPUT end AC coupling gives big numbers, but it does not need to be applied at the output pin.I'm not sure a cap is needed, as you can build a current amplifier and manage the voltage swings that way. The test software can emulate AC coupling as needed.Having a finite, series R helps greatly in all of this.

author: Yansi
author_rank: Super Contributor
timestamp: April 06, 2019, 09:55:52 pm
content: Quote from: nctnico on April 06, 2019, 03:56:24 pmClass-D amplifier is a pretty nice synchronous buck (or even boost, if the load is an energy source) and will pretty happily push energy back from load to the supply. (Ever heard about "bus pumping" with single ended stages?)

author: tatus1969
author_rank: Super Contributor
timestamp: April 07, 2019, 07:53:29 am
content: Quote from: PCB.Wiz on April 06, 2019, 08:22:02 pmThanks for pointing this out (+ntcnico), this could be an interesting alternative. The instrument has a sense resistor at its output (actually, 50 mOhms), I could easily add an opamp there and use the amplified signal to control the PA. The DAC output would then become a current, and this would naturally solve my resolution problem as you guys point out. This would make voltage regulation for higher impedance loads more difficulty though. Maybe even a hybrid approach with selectable configuraton would make sense. (EDIT: and also likely hard to tame no-load output voltage that I have to maintain before the load is connected through a relais.) (EDIT2: thinkg further... this may not work as doing so would include the phase delay caused by the output filters in the feedback loop, which may lead to instability.)Quote from: PCB.Wiz on April 06, 2019, 08:22:02 pmYou're practically describing many aspects of how the instrument works - it uses 4 terminal voltage measurement (one isolated ADC) and shunt resistor based current measurement. At lower frequencies, I currently get > 15 ENOB for current and > 16 ENOB for voltage - and it is a total mess in terms of signal integrity.EDIT: that also made me realize that the PA cannot see less than 50mOhms load, which is almost relaxing.Quote from: Yansi on April 06, 2019, 09:55:52 pmI had this very topic in a recent project but the reason for that is actually different. It is the power conversion nature of a DCDC, being able to deliver more current at its output than it takes from its supply, in combination with a symmetrical supply having the load tied to midpoint. When the amplifier delivers e.g. positive current into the load, and output voltage is low, then the lower side supply capacitor sees the small negative supply current superimposed with the larger positive output current, and by is getting charged. The solution is to use two amplifiers in BTL.

author: nctnico
author_rank: Super Contributor
timestamp: April 07, 2019, 10:12:15 am
content: Either way some form of feedback will take care of reducing non-linearities.

author: tatus1969
author_rank: Super Contributor
timestamp: April 21, 2019, 12:17:05 pm
content: The prototype PCB is ordered, and I'm very curious to see if my "class AD" power stage idea is any good. As you can see from the first picture, the H bridge driver is far more complex than usual. The other picture shows the PWM generator that I have implemented in the end. Sorry, no sigma delta, in the hope that I haven't made a bad decision