hybridfree/eevblog-posts huggingface dataset:
Need help with XDMA Stream - Page 1
Forum section: electronics / general

author: notooth
author_rank: Contributor
timestamp: July 27, 2023, 08:37:05 pm
content: Can anyone tell me what is wrong with this block design? It is supposed to return the multiplication of 2 float numbers, but I always get 0.

author: asmi
author_rank: Super Contributor
timestamp: July 27, 2023, 08:41:15 pm
content: I see nothing wrong because I see no block design

author: notooth
author_rank: Contributor
timestamp: July 27, 2023, 08:46:16 pm
content: I have just attached the picture of the block design.

author: asmi
author_rank: Super Contributor
timestamp: July 28, 2023, 02:10:55 am
content: That block is Ultrascale+ only, so I can't help with that because I have no experience with it. I can only offer some general suggestions like using ILA to see what is going on.

author: notooth
author_rank: Contributor
timestamp: July 29, 2023, 02:26:24 pm
content: I tried to do the following with ILA:In the Hardware window, I clickedRun Trigger ImmediateIn a terminal, I run a command to send 256-bit data to /dev/xdma0_h2c_0In the Waveform window, I clickedRun trigger immediate for this ILA coreBut I did not see any change ofxdma_0_m_axis_h2c_tdata_0sinal. What did I do wrong?

author: Someone
author_rank: Super Contributor
timestamp: July 29, 2023, 11:37:37 pm
content: Quote from: notooth on July 29, 2023, 02:26:24 pmTake some steps back and learn the parts one at a time.https://docs.xilinx.com/r/en-US/ug908-vivado-programming-debugging/Running-the-TriggerTest things in small parts rather than asking "why doesn't this big complex thing that no-one else has ever built before not work the way I expect it to".

author: notooth
author_rank: Contributor
timestamp: July 30, 2023, 12:19:55 pm
content: Quote from: Someone on July 29, 2023, 11:37:37 pmThat was exactly the document that I learned, but I have not got the idea how to capture data of m_axis_h2c_tdata_0 interface when I wrote data to /dev/xdma0_h2c_0.

author: Someone
author_rank: Super Contributor
timestamp: July 30, 2023, 09:19:19 pm
content: Quote from: notooth on July 30, 2023, 12:19:55 pmIf you can't take what that document describes and figure out how to capture a write, then you need to go back further. What is a write? what does it look like in simulation? what should it look like on the logic analyser?
Vivado MIG Generator Crashes - Page 1
Forum section: electronics / general

author: Mario87
author_rank: Frequent Contributor
timestamp: July 17, 2023, 03:35:27 pm
content: Hi all, I am trying to use the MIG generator for a new design and when I get to the 'Pin / Bank Selection Mode' I click on 'New Design: Pick the optimum banks for a new design'.When I do this, firstly Vivado / MIG does not give me a default design as I expected, everything is set to 'Unassigned' and worse of all if I click on any button on screen except for 'Back' Vivado just crashes out, this happens every single time without fail.I am running Vivado 2022.2 on Windows 10 Pro 64-bit. Anyone had this before and are there any known solutions?Also, as you can see in the image bank 34 is just greyed out for some reason? Why would this be? Part selected is a XC7A50T-FTG256 device (speed grade 1).Image of the screen I am getting stuck at attached.

author: asmi
author_rank: Super Contributor
timestamp: July 17, 2023, 03:57:31 pm
content: Quote from: Mario87 on July 17, 2023, 03:35:27 pmIs you project inside a folder which is syncronized with some kind of real-time backup software? I had a problem with MIG when my project folder was inside OneDrive sync folder. Though I didn't ever crash, but it still didn't work properly.Quote from: Mario87 on July 17, 2023, 03:35:27 pmThat is because bank 34 in FTG256 package is not fully bonded out. So it can not be used for memory controller. Read MIG user guide for details and other restrictions. For example, you can implement a 16 bit DDR2/DDR3 interface in a single IO bank, but MIG GUI won't let you do it unless you manually assign all pins.

author: Mario87
author_rank: Frequent Contributor
timestamp: July 17, 2023, 08:34:39 pm
content: Quote from: asmi on July 17, 2023, 03:57:31 pmThanks, it is not linked to any backup software, I did also try disabling anti-virus bit it made no difference. In the end I deleted the IP block and made a new one, seemed to work fine this time round? Very strange...but its now setup and happy.Quote from: asmi on July 17, 2023, 03:57:31 pmThanks, good info to have! I'll take a look at the MIG user guide.
XC7A100T How Many GTP? - Page 1
Forum section: electronics / general

author: hal9001
author_rank: Regular Contributor
timestamp: July 13, 2023, 10:00:49 am
content: I want a XC7A100T to communicate with 4 other XC7A100T. The data sheet says the XC7A100T has 4 GTP. Is each GTP a independent GTP quad?Thanks

author: asmi
author_rank: Super Contributor
timestamp: July 13, 2023, 02:11:42 pm
content: 4 GTPs mean 4 GTP transceivers (1 quad), not 4 quads.

author: hal9001
author_rank: Regular Contributor
timestamp: July 14, 2023, 04:35:29 am
content: Quote from: asmi on July 13, 2023, 02:11:42 pmThanks! Does each GTPE channel have a dedicated clock? Is the GTP Quad intended to host 4 independent channels?

author: asmi
author_rank: Super Contributor
timestamp: July 14, 2023, 03:12:47 pm
content: Quote from: hal9001 on July 14, 2023, 04:35:29 amEach quad has 2 clock inputs and 2 PLLs which can be used to generate clocks for transceivers. Each GTP within a quad can be used independently provided that you can come up with clocking configuration which will work with all of them - in reality it means that all transceivers work off one or two different clock frequencies (you can select either of those two clocks for each individual transceiver), or a divided versions of them (it is possible to divide PLL clock by 1,2,4 or 8 for each individual transceiver). See user guide UG482 for more details.Now, you have to remember that high speed serial links carry embedded clock, so a receiving side need not use the same reference clock signal as transceiver side - only the same clockfrequency. So as long as you can find a clocking solution which would give each GPT in a quad the frequency they need, they can work independently without any problems.

author: hal9001
author_rank: Regular Contributor
timestamp: July 16, 2023, 10:26:23 am
content: Quote from: asmi on July 14, 2023, 03:12:47 pmThanks for the details! Helps a lot. Cheers!
Need some video Lecture to understand OOPS with System verilog - Page 1
Forum section: electronics / general

author: audio
author_rank: Regular Contributor
timestamp: June 27, 2023, 05:45:34 pm
content: Hi all,Need some video Lectures to understand OOPS, Basically i am under grad Student who have studied only C.Now I am Learning SYSTEM VERILOG by self study, When i went to the constructor, how to copy objects(DEEP COPY or Shallow Copy)I cant understand the concepts.Suggest me some video lectures and books which could be useful for studying system VerilogThank you all.

author: AK6DN
author_rank: Regular Contributor
timestamp: June 27, 2023, 10:03:37 pm
content: Quote from: audio on June 27, 2023, 05:45:34 pmHow about this for an overview:

author: audio
author_rank: Regular Contributor
timestamp: July 01, 2023, 06:06:00 am
content: HI allI request to suggest some books on OOPS or methods to understand System Verilog in a easier way. Thank You.

author: audio
author_rank: Regular Contributor
timestamp: August 02, 2023, 09:38:11 am
content: hi all,I doesnt understand the passing object as a value for a function,function void copy (PCITop p); any body can please explain the function which has been highlighted below.module class_TOP( );class PCIChild;logic [7:0] burstC;function new (logic [7:0] burst);burstC = burst;endfunctionendclass : PCIChildclass PCITop;logic [31:0] addrTop;logic [31:0] dataTop;PCIChild PCIc;// creating object for PCIChildfunction new(logic [31:0] addr, logic [31:0] data, logic[7:0] burst);PCIc = new(burst); //instantiate PCIcaddrTop = addr;dataTop = data;endfunctionfunction void copy (PCITop p);addrTop = p.addrTop;dataTop = p.dataTop;PCIc.burstC = p.PCIc.burstC;endfunctionfunction void disp (string instName);$display("[%s] addr = %h data = %h burst=%h", instName, addrTop, dataTop, PCIc.burstC);endfunctionendclass : PCITopPCITop PCI1, PCI2;initial begin;PCI1 = new (32'h 0000_00ff, 32'h f0f0_f0f0, 8'h12);PCI1.disp("PCI1");PCI2 = new (1,2,3);PCI2.copy(PCI1); //deep copy PCI1 into PCI2PCI2.disp("PCI2"); //copied content displayedPCI2.addrTop = 32'h1234_5678;PCI2.dataTop = 32'h5678_abcd;PCI2.PCIc.burstC = 8'h 9a;PCI2.disp("PCI2");PCI1.disp("PCI1");endendmodule
How to Get Support When You Can't Contact Support? - Page 1
Forum section: electronics / general

author: gnuarm
author_rank: Super Contributor
timestamp: June 15, 2023, 05:40:06 pm
content: Yeah, I can't log into the support center, probably because I don't remember my password. I can't reset my password for an unexplained reason. It says, "contact your administrator". I can't create a new account with the same email address. Efinix doesn't answer their phone at the office in California (voicemail only). I can't find any other way to contact them, other than a sales email address.WTF? This is one buttoned down company. They really do not want to bother when new customers I suppose.

author: Nusa
author_rank: Super Contributor
timestamp: June 15, 2023, 05:52:44 pm
content: The easiest and quickest solution would be to create an account with another email address. And write the password down this time.

author: gnuarm
author_rank: Super Contributor
timestamp: June 15, 2023, 06:14:18 pm
content: Quote from: Nusa on June 15, 2023, 05:52:44 pmAlready tried that. "Access denied"Any other ideas?

author: jpanhalt
author_rank: Super Contributor
timestamp: June 15, 2023, 06:23:06 pm
content: The site claims to be on Twitter. I haven't registered with Twitter, so can't check.

author: gnuarm
author_rank: Super Contributor
timestamp: June 15, 2023, 06:34:09 pm
content: Quote from: jpanhalt on June 15, 2023, 06:23:06 pmNot sure what you mean. Are you saying they do support through Twitter?

author: xrunner
author_rank: Super Contributor
timestamp: June 15, 2023, 06:37:55 pm
content: Quote from: gnuarm on June 15, 2023, 06:14:18 pmContact sales - what do you have to lose?

author: gnuarm
author_rank: Super Contributor
timestamp: June 15, 2023, 06:42:07 pm
content: Quote from: xrunner on June 15, 2023, 06:37:55 pmI've sent them an email. In general, I find the sales contacts to be the slowest. They are much more tuned into calls or direct emails from existing clients. I would go through a distributor or rep, but they only use Digikey here and there's no rep in my state.

author: AK6DN
author_rank: Regular Contributor
timestamp: June 15, 2023, 08:54:13 pm
content: Quote from: gnuarm on June 15, 2023, 05:40:06 pmWell, I just went to the Efinix website and registered a new account. No problems at all.

author: mon2
author_rank: Frequent Contributor
timestamp: June 16, 2023, 10:24:13 am
content: Contact:Rochellezefinixinc.comShe is the one who created most of the tutorial videos at Efinix.

author: gnuarm
author_rank: Super Contributor
timestamp: June 16, 2023, 03:27:23 pm
content: Quote from: mon2 on June 16, 2023, 10:24:13 amThanks. I managed to get it sorted.
clocking scheme/CDC for half-band filter - Page 1
Forum section: electronics / general

author: jlcordar
author_rank: Newbie
timestamp: June 10, 2023, 03:50:36 pm
content: I've done some FPGA design but not any multi-bit multirate stuff. I designed a half-band filter in SystemVerilog, and I will decimate the filter output by 2. The decimated clock is derived from the clock the filter is running at (implemented a /2 since the speed was too low for the FPGA PLL to generate the clock).To handle the different clock domains, should I do Multi-Cycle Path or a short rate adaptation async FIFO or something else?This will be in Efinity because I can't find any other cheap boards at the moment.For a CIC filter, I imagine it would be the same answer just with a greater clock difference between the clocks. This is for PDM -> I2S.thanks.

author: Someone
author_rank: Super Contributor
timestamp: June 10, 2023, 08:22:35 pm
content: Where there are integer ratio clocks (particularly 2^n ratios, but the concept still works even for non integers) it is more common to leave everything on the "fast" clock and use clock enables for the parts that operate slower.

author: jlcordar
author_rank: Newbie
timestamp: June 13, 2023, 04:47:46 pm
content: thanks, I'll try to implement w/clock enables. I'll try the async FIFOs later but I'll try clock enables first.
FMEA of a digital design - Page 1
Forum section: electronics / general

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: June 06, 2023, 03:49:32 pm
content: I have carried out FMEA of physical circuits long ago where we have failure modes like resistor become open circuit or short circuit or its value drifts e.t.c and use MIL standard document to caculate the failure probability for different components on a circuit board.At this time I need to carry out FMEA on a digital design that has been created in RTL and shall be implemented in ASIC. It is the design itself that needs to go through FMEA or FMEDA (don't know if they are the same thing or not). There is basically no resource on the internet on how to do this, i.e define failure modes for an RTL design. How can one proceed with this exercise?

author: Someone
author_rank: Super Contributor
timestamp: June 07, 2023, 12:40:24 am
content: Hello SEU:https://en.wikipedia.org/wiki/Single-event_upset

author: AK6DN
author_rank: Regular Contributor
timestamp: June 07, 2023, 12:52:51 am
content: And TMR:https://en.wikipedia.org/wiki/Triple_modular_redundancyAnd FMEA:https://en.wikipedia.org/wiki/Failure_mode_and_effects_analysis

author: Tation
author_rank: Regular Contributor
timestamp: June 07, 2023, 04:15:21 pm
content: Please, note that this info may be outdated:look for (digital) fault modeling, mainly thestuck-atfault modellook for LSSDhttps://www.slideshare.net/PraveenKumar3664/level-sensitive-scan-designlssd-and-boundry-scanbsDesign tools can compute, from post P&R simulations, the fault coverage of your design (% of faults that can be detected by the test vectors, not to be confused with the code coverage). You must design the vectors (and a way to apply them in a real chip, LSSD comes here) to achieve ~100 % fault coverage. There are also tools helping on these (look for ATPG).Foundries may reject design + vectors combos showing too low a fault coverage, as they may use your vectors to test the chips before cutting/packaging/shipment.If your design does have some kind of redundancy (like TMR above), you will be far from 100 % fault coverage, but talking with the foundry explaining it may help. Or you may need a mechanism to disable redundancy during tests.Your best source of info will be your CAD tool manuals and foundry interface.
n00b question about gaming project - Page 1
Forum section: electronics / general

author: vivi-d
author_rank: Regular Contributor
timestamp: June 02, 2023, 11:30:05 pm
content: Quick question... I'm thinking of developing a small device that could be an "adaptor" between gaming controllers. The idea would be to (thru USB?) make it possible to use a PS4 controller on xbox. Or vice versa.About how many lines of VHDL programming would a project like this need? Would it be a good beginner project?

author: ataradov
author_rank: Super Contributor
timestamp: June 02, 2023, 11:38:11 pm
content: This is more of a microcontroller project than an FPGA project. USB on FPGA is likely to require an MCU core anyway.First order of business would be to figure out what protocols they are using and if they are documented anywhere.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 03, 2023, 12:27:30 am
content: First, I would suppose both are HID devices.I don't have a Xbox but I do have a PS4, and I just checked connecting one controller via USB to a PC. The controller shows up as "Sony Corp. DualShock 4" and can be used as a regular joystick.Not sure about the Xbox, but I suspect this is the same. So if that's the case (which is likely), it will mostly be a matter of matching controls from one controller to the other.This could be done with a MCU of course, but you'd need one with two USB OTG controllers, one programmed as host and the other as device.IIRC (although i've never tested myself), RPi's can be used as USB devices on one of their USB ports. If that's indeed the case (someone here may have more info/already done that), then this would probably be the easiest path for what you want to achieve.

author: asmi
author_rank: Super Contributor
timestamp: June 03, 2023, 04:12:40 am
content: Yeah, USB is a very "software-heavy" protocol as it heavily relies on a software driver stack, which is what made it so successful because adding/changing software is always easier than modifying hardware, especially when it comes to adding support for new features to existing hardware.But the flip side is that basically requires some sort of CPU to actually run that software stack, unlike some other protocols which can be implemented in pure hardware, or mostly in hardware.

author: dobsonr741
author_rank: Frequent Contributor
timestamp: June 03, 2023, 04:20:22 am
content: Done already on MCU:https://github.com/jfedor2/hid-remapper
Spartan 6 production through 2030 - Page 1
Forum section: electronics / general

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: June 01, 2023, 08:34:08 pm
content: Scattered in a few threads across the forum, like the chipageddon thread are concerns about spartan six availability and Xilinx's commitment to continued production.Well they now announced:https://community.amd.com/t5/adaptive-computing/amd-extends-spartan-6-product-lifecycle-through-at-least-2030/ba-p/610178

author: langwadt
author_rank: Super Contributor
timestamp: June 01, 2023, 08:40:44 pm
content: so I guess ISE will live on even though it was discontinued more than 10 years ago

author: nctnico
author_rank: Super Contributor
timestamp: June 01, 2023, 10:01:24 pm
content: It would have been better if they backed it with parts being available... On top of that, AMD has not been very reliable where it comes to part availability in the past. I've been burned a couple of times already by using AMD parts which got sold off and became obsolete.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 01, 2023, 11:14:33 pm
content: Through *at least* 2030. And I'm not surprised. The 6-series has been very popular and I myself have a number of devices using it to support.ISE works fine on Win 7, requires a VM in Windows 10+ IIRC? But it works fine also on Linux.

author: langwadt
author_rank: Super Contributor
timestamp: June 01, 2023, 11:22:57 pm
content: Quote from: SiliconWizard on June 01, 2023, 11:14:33 pmyeh, I think the last windows version comes prepackaged as a vm.it runs fine on linux or in WSL

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 02, 2023, 07:34:49 pm
content: As a side note, I think it's unfortunate that vendors would decide to stop maintaining the software that supports some parts that they still sell and support. That is a problem IMHO.Either you support a product, or you don't, and the necessary tools to use it are every bit as important as the product itself.As I said in another thread, it looks like Lattice is gonna do the same thing with Diamond.I understand that it takes resources to maintain software, but I see little justification from a customer's POV for this kind of decision.The rationale that the software "just works as it is" is a pretty limited one. You still make customers' life harder - like regarding OS support, and the remaining list of bugs that will never get fixed, etc.Just MO. If everyone is happy with that, so be it.

author: nctnico
author_rank: Super Contributor
timestamp: June 02, 2023, 09:20:44 pm
content: Fixing ISE would mean rewriting it from scratch...Which Xilinx actually did in the form of Vivado. I just don't quite understand why they didn't add support for Spartan 6 in Vivado. I can't imagine Spartan 6 needing the tools to be completely different due to outlandish FPGA structures inside Spartan 6 FPGAs.Or maybe people aren't using ISE so much. For the Spartan 6 / Virtex 6 projects I maintain I use Eclipse for editing and a makefile to do the final synthesis runs. I only use ISE for things like looking at timing reports and checking some RTL schematics every now and then.
[newbie] Doubt on verilog code - Page 1
Forum section: electronics / general

author: greenstrike
author_rank: Contributor
timestamp: May 30, 2023, 04:15:40 pm
content: Hi guys, I'm starting using verilog.I need Numerically Controlled Oscillator as clock generator but code I've found on the web is too complicated for me, so I'm designing my NCO step by step.I am using overflow bit as flag, to be cleared after 1 clock cycle.Here my working (until now) code:Code:module NCO_4bit#(parameter WACCUM = 24// accumulator register width /*output frequency  = (step  * Fosc )/(2^WACCUM)example:always #5 ck = ~ck;clock period = 10ns, clock frequency = 100 WACCUM = 8 step = 3 output frequency fout = 1.1764705882 */)(input [WACCUM-1:0]step,// phase valueoutput reg [WACCUM:0]accu,// accumulatoroutputfout,// output frequencyinputn_res,// clear command (active low)inputck// system clock (on rising edge));wire [WACCUM:0]mask;assign mask = { {1'b0}, {(WACCUM){1'b1}} };// creating mask, WACCUM+1 bits wide, only MSB 0, remaining bits set to 1// check for reset, check at falling edge of n_res or every rising edge of ckalways @(posedge ck or negedge n_res)beginif (!n_res)accu <= 0;// clear accu registerelsebegin// check if accu MSB is set, if so clear it so fout high only for 1 clock cycle//$display("\ninit accu= %b, flag= %b", accu, accu);if (accu)begin//accu <= 1'b0;accu <= (accu+step)&mask;endelsebeginaccu <= accu+step;end$display("current accu value= %b, flag= %b", accu, accu);endendassign fout={accu};endmoduleIt looks working, I just add "step" value to "accu" and using MSB of accu register to detect rollover of the counter.I want rollover flag (fout) high for 1 clock cycle, then I clear it.First code I wrote:Code:if (!n_res)accu <= 0;// clear accu registerelsebegin// check if accu MSB is set, if so clear it so fout high only for 1 clock cycle//$display("\ninit accu= %b, flag= %b", accu, accu);if (accu)beginaccu <= 1'b0;endaccu <= accu+step;endWhen detecting MSB set I try to clear it, but no effect.I also tested accu <= 5 as test.I can enter inside if (accu) but it looksaccu <= accu+step;would override all previous instructions.Am I missing something?Thanks.

author: langwadt
author_rank: Super Contributor
timestamp: May 30, 2023, 07:04:00 pm
content: the last assignment "wins" so you need to have the default "accu <= accu+step;" firstyou could do it all in one linereg fout;{fout,accu} <= {1'b0,accu}+{1'b0,step};

author: greenstrike
author_rank: Contributor
timestamp: May 31, 2023, 12:27:17 pm
content: Ok, thanks, finally I've understood difference between blocking and non-blocking...
FPGA in a toothbrush? - Page 1
Forum section: electronics / general

author: NiHaoMike
author_rank: Super Contributor
timestamp: May 20, 2023, 02:51:09 am
content: https://hackaday.com/2023/05/18/toothbrush-speed-controller-secrets-revealed/Obviously a very tiny FPGA, buy why that instead of a microcontroller?

author: Whales
author_rank: Super Contributor
timestamp: May 20, 2023, 03:33:50 am
content: Possibly their goal was a custom ASIC and massive manufacture quantity, but perhaps either their quantity changed or they couldn't secure an ASIC contract? If the product succeeds in the market they might try harder to get an ASIC instead?

author: Someone
author_rank: Super Contributor
timestamp: May 20, 2023, 04:19:24 am
content: Not sure many people would call a GreenPak device an FPGA, they're cheaper than microcontrollers and have a fairly limited count of primitives. Its pretty much what you'd expect for a simple toothbrush where all you need is some power conversion and a timer or two.

author: SiliconWizard
author_rank: Super Contributor
timestamp: May 20, 2023, 06:30:58 am
content: Quote from: Someone on May 20, 2023, 04:19:24 amAgreed. It's mixed-signal too, something that a "regular" FPGA *usually* isn't. (Well, it has analog comparators, not much but again most FPGAs do not embed such things.) It's cheap but its simplicity is also a nice feature.No software => usually fewer problems.

author: AK6DN
author_rank: Regular Contributor
timestamp: May 21, 2023, 08:33:05 pm
content: Quote from: Whales on May 20, 2023, 03:33:50 amI can buy a reel of GreenPAK SLG47513 parts for US$0.46 each.So spending big bucks to make an ASIC is not a wise choice.At best you could save about US$0.45 per unit, if you got the ASIC cost down to US$0.01.Sometimes making an ASIC is the wise thing NOT to do.

author: NiHaoMike
author_rank: Super Contributor
timestamp: May 23, 2023, 10:17:07 pm
content: Quote from: AK6DN on May 21, 2023, 08:33:05 pmSeems relatively expensive compared to low end microcontrollers.

author: kleiner Rainer
author_rank: Regular Contributor
timestamp: May 26, 2023, 04:04:40 pm
content: There are not many low cost microcontrollers that can operate off a single NiMh cell.Application note with detailed description:https://www.renesas.com/us/en/document/apn/cm-360-electric-toothbrush?r=1570446Greetings,Rainer

author: SiliconWizard
author_rank: Super Contributor
timestamp: May 26, 2023, 07:27:10 pm
content: As I hinted, there are just so many ways to screw up even the firmware of something as mundane as a toothbrush that not using software-controlled solutions at all may justify even paying 4 times the price of the programmable logic component. IMHO.
Parser for (Altera) FPGA programming files - Page 1
Forum section: electronics / general

author: tv84
author_rank: Super Contributor
timestamp: September 14, 2017, 07:07:51 pm
content: I've created a small parsing utility that shows the contents of some Altera (+ others??) .SOF/.POF/.RBF/.JIC/.RPD files.It's a very rudimentary experimental tool but it can show some of the contents of theses files (CRCs, checksums, etc...)Sometimes it can help people understand why their files fail programming, etc.There's little information available on this (proprietary) topic so if you have anything to add or correct, or find a file that doesn't process, please leave a msg.

author: luilui
author_rank: Newbie
timestamp: May 16, 2023, 12:35:50 pm
content: Hello, I'm currently working on bitstream parsing. I was wondering if Altera has publicly available documentation on the configuration file structure. Could you please explain how your tool is developed?

author: AK6DN
author_rank: Regular Contributor
timestamp: May 16, 2023, 09:36:38 pm
content: Quote from: luilui on May 16, 2023, 12:35:50 pmThe detailed format of an Altera FPGA configuration file is non-public proprietary info. You would need to sign an NDA to get it.The higher level format of some files (like .POF for example which originally came from DataIO the programmer maker) are available.Likely that info is what was used to develop the original parser application. But it won't tell you how the individual records are encoded.

author: Mark
author_rank: Frequent Contributor
timestamp: May 19, 2023, 10:56:23 am
content: Ummm....

author: radiolistener
author_rank: Super Contributor
timestamp: May 28, 2023, 07:39:19 pm
content: can you provide source code?
Capturing a JTAG programming stream - Page 1
Forum section: electronics / general

author: macona
author_rank: Regular Contributor
timestamp: May 24, 2023, 11:19:31 pm
content: So we ran into an issue where we have a piece of hardware that we make and the dedicated eeprom for the FPGA became unavailable and we had to move to a generic eeprom for it. The issue we are having it we used to be able to program the eeprom on board without the assistance of the FPGA through our own software. Now with the new eeprom it is connected through the fpga and we cant use our software to program it because the software cant configure the fpga to write to the eeprom. We can program through JTAG though and we found that the JTAG sends the configuration data before the eeprom payload. So if we can capture the data before the payload we think we can use that with our software to program the eeprom.So the question is, is there a way to capture the data that the JTAG programmer is sending to the FPGA? I dont think any of our logic analyzers have a deep enough capture to get everything. Anything third party that might work?
Does it exist Xilink Ultrascale courses not too expensive - Page 1
Forum section: electronics / general

author: rdpdo
author_rank: Contributor
timestamp: May 21, 2023, 08:50:11 am
content: HelloOn xilink website we can buy courses but it is very expensive to buy a package of courses. One course is about 200 but as I wanted do have some package it is expensive...Do someone know where I could have access of courses like that but less expensive ?Thanks you !
Multiplexing a pin for i2c signals and normal output signals - Page 1
Forum section: electronics / general

author: polarKaung
author_rank: Contributor
timestamp: May 25, 2023, 04:18:40 am
content: Hi, I am doing a project which needs to multiplex a pin for i2c sda and a normal output signal. How do i do that? really appreciate your time and wisdom. I have been researching this on the internet and haven't really come up with any solution. Thanks.

author: TomS_
author_rank: Frequent Contributor
timestamp: May 25, 2023, 10:46:06 am
content: You can very likely manually control the SDA pin without interfering with the i2c devices, but to use the pin for some other purpose (output) you're going to want to latch/clock the state of it into a flip flop or something along those lines. For input you probably want to feed it through a tri-state buffer that you can enable when ever you need to read it's state.That's going to require one more pin to control the latch/clock/enable function, at which point you haven't really saved yourself any pins, so you might as well use that pin for your IO.Alternatively, add a GPIO expander to the i2c bus and get yourself a bunch more IO pins.

author: DavidAlfa
author_rank: Super Contributor
timestamp: May 25, 2023, 12:13:03 pm
content: Not easy because you're going to mess the i2c bus.You might get it working as long as you are careful, avoiding causing a start or stop condition.That is, SCL can never change while SDA is low.So you would need to always set SDA high before changing SCL, then you can whatever with SDA.
Virtex-6 Partial reconfiguration - Page 1
Forum section: electronics / general

author: MexEngineer
author_rank: Newbie
timestamp: May 02, 2023, 07:00:26 am
content: Hello!I'm trying to understand how to do the partial reconfiguration of an FPGA, I hope someone could help me to get my thoughts straight.Currently, I'm able to create the project and generate the full and partial bitstreams, I know that those work because I can load the partial bitstreams using iMPACT and it works as intended.I've read the configuration userguide (UG360) and I understand that I can do the reconfiguration through the ICAP primitive, but can I do it using the IPROG command? Or do I need to load the bitstream from the flash using my own code?Note: I want to do partial reconfiguration and not full configuration.
Cyclone IV PLL not working correctly - Page 1
Forum section: electronics / general

author: rokspy
author_rank: Contributor
timestamp: April 22, 2023, 09:57:32 pm
content: I'm using Quartus PLL IP on the Cyclone IV EP4CE22E22C6, but the frequency is incorrect. I supplied the PLL with 50MHz from a crystal and configured the PLL to output 100MHz. It did work some time ago, but today when I started testing things, the data rate was much slower than required, but the data is still correct, so I believe that the logic element part of the FPGA okay. The crystal also supplies stable 50MHz. The PLL output frequency is around 66kHz... At, the moment I'm directly connecting the PLL output to an open pin and nothing else.What could be the cause of this behavior? Dead PLL??Thanks for the answers in advance!

author: rokspy
author_rank: Contributor
timestamp: April 22, 2023, 10:06:55 pm
content: Sorry for wasting space and time here... There was an issue with the pin planner. The name of the signal in the pin planner was slightly changed at some point in time and I did not notice that. The PLL was supplied by some random input that was not connected to any port.
Lattice CrossLink NX EVB Clocking w/higher speed clocks - Page 1
Forum section: electronics / general

author: jlcordar
author_rank: Newbie
timestamp: April 23, 2023, 08:00:53 pm
content: Hi,I bought a Lattice CrossLink NX EVB (LIFCL-40-9BG400C) to try it out and do some MIPI D-PHY experiments, and to learn about Lattice FPGAs. I completed the 'hello world' tutorial which uses on onboard [the FPGA] +/- 12% RC oscillator. I did a simple blinky LED/SPI project clocked by the FTDI 12MHz oscillator. Unfortunately, for projects that require higher speed + tighter ppm clocks, the PLL minimum input frequency is 18MHz so I can't use the FTDI 12MHz clock, I need a higher-speed clock. The documentation says the PLL should be fed by a dedicated PLL pin for best performance. OK. U4 is a 125MHz LVDS Abracon oscillator. I think that this is connected to the dedicated PLLCLK pin. I cannot figure out how to configure the device to accept U4's LVDS as the clock. Does anybody have any advice/can point to example project or code? I looked around for examples, there are not a lot for this board, and no Lattice forum. I can always run a semirigid to a deadbugged LVCMOS oscillator but I would rather not do that just yet on a board I paid $130 for.thanks,Jay

author: jlcordar
author_rank: Newbie
timestamp: April 26, 2023, 05:25:03 pm
content: Lattice tech support told me U4 (LVDS 125MHz clock) is intended for Ethernet SerDes applications, and the only other clock on this board besides the internal is the 12MHz FTDI clock. So I would need to connect an external clock to pin 1 of JP2. I will ask them if I can just turn the Ethernet SerDes on and just use it for the clock.
Quartus ALTFP_SQRT IP not working in simulation - Page 1
Forum section: electronics / general

author: rokspy
author_rank: Contributor
timestamp: April 09, 2023, 06:36:40 pm
content: I am trying to use the Quartus ALTFP_SQRT IP in simulation, but the output always results in undefined state. It should take and output single precision floating point number (23 bits for mantissa, 8 for exponent and 1 for sign). Left the latency to the default value of 28 cycles and avoided any optional inputs and outputs. Clock is set to 100MHz. All files, including the generated IP .vhd, compiles without any issues. Tried feeding the input in different ways - just a constant vector, signals from other parts of the design, but output remains undefined anyways. Quartus can also compile it and generate a netlist for it, but have not tried to check in in real life yet, before I can deal with the simulation. What could be the cause for the undefined output?? Am I completely missing something??EDIT: My personal thought is that it may be something related to the Modelsim libraries and the file describing the IP behavior is not present and it does not know how to simulate it, but I would assume that the compiler would cry about this, and I'm not really sure how to verify this.FINAL UPDATE:Got it working.. Initially I assumed that the behavior of the generated IP component is already present in the "altera_mf" library, which was a faulty assumption because when I started digging through the library, could not find the component, which was used in the generated ip .vhd file. What I failed to notice initially was that there were additional simulation files generated, that had to be compiled and added to the testbench. After switching to these files, dealing with some other minor compilation nonsense, simulation worked, and provided valid results (square root of 4 is indeed 2)Thanks for the suggestions in advance!

author: ejeffrey
author_rank: Super Contributor
timestamp: April 09, 2023, 07:24:18 pm
content: Are you resetting it?Some simple IPs like this will work without reset when synthesized because the pipeline will clear deterministically but in simulation will stay X forever due to x propagation.

author: rokspy
author_rank: Contributor
timestamp: April 09, 2023, 07:35:18 pm
content: Initially there was no reset in the generated IP. I added it now and tried resetting it as well, but with no luck, the result is still 'UUU...'.. A good try though

author: Daixiwen
author_rank: Frequent Contributor
timestamp: April 17, 2023, 09:33:32 am
content: Quote from: rokspy on April 09, 2023, 06:36:40 pmModelsim is very annoying with that. If it doesn't find an entity that you instantiate in your code, it just says "instance xxx is not bound" as a warning, it's not even an error. When I get some strange behavior the first time I run a testbench the first thing I do is search the log for "not bound".
Alternative for Lattice 4032ZE? - Page 1
Forum section: electronics / general

author: hneel
author_rank: Newbie
timestamp: April 07, 2023, 01:02:19 pm
content: A few years ago we developped a board which included a 4032ZE. But now these are either hard to get or very expensive. We tried to replace it with a 4032ZC, as the datasheets were very similar. But then our product became instable.What alternatives could we look for?We're using 24 pins, 4 of them 5V inputs. We're feeding it 3.3V. If we have to redesign the pcb we could add another 74LVC4245 chip for level convertion. Our pcb already has a couple of those. But we'd prefer a 5V tolerant device.Anything pin-compatible would be nice, of course.

author: Ling
author_rank: Contributor
timestamp: April 10, 2023, 06:52:49 am
content: just I'm confused.... u mean the Lattice LC4032ZE series? I read through whole data sheet try to figure out full mfg P/N u're refering to with PIN-24, can only find pin / ball of 48 & 64....hmm, so is there any error or misunderstanding?

author: hneel
author_rank: Newbie
timestamp: April 11, 2023, 06:57:12 am
content: Ah, I see the misunderstanding. We are using the 48-pin TQFP: LC4032ZE-7TN48IBut we are only using 24 inputs/outputs.

author: up8051
author_rank: Frequent Contributor
timestamp: April 11, 2023, 10:37:29 am
content: Do you neet Industial Temperature Range.Commercial is avilaible in rs-components:https://nl.rs-online.com/web/p/cplds/8276511

author: hneel
author_rank: Newbie
timestamp: April 11, 2023, 11:55:40 am
content: They have to be industrial in our case. The product is used outdoors, in all parts of the world.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: April 11, 2023, 06:03:40 pm
content: This is definitely a discussion to be had with a Lattice FAE.

author: Ling
author_rank: Contributor
timestamp: April 18, 2023, 04:08:54 am
content: the biggest problem for replacement is dimension, lattice one is 7*7, all other mfg have bigger size than it, unless u're willing to change whole pcba dimension togtherso maybe colorod.rob is right, best way to consult lattice itself
Gowin triple speed ethernet MAC. Trouble with tx data - Page 1
Forum section: electronics / general

author: SomeDayFpga
author_rank: Newbie
timestamp: April 07, 2023, 06:03:40 pm
content: Hello everyone!Now I have deal with Gowin triple speed ethernet mac. I have a simple project where I taking data from MII interface, putting it into fifo and sending back (loopback).There is no problem with the part where I get the data, it occurs during the transfer.If you believe the IP documentation, you should set tx_mac_valid and send bytes until tx_mac_ready signal is high, but the problem is that this signal is not set at all.If there are people here who have worked with this IP core, I would be very grateful for your help.

author: Ling
author_rank: Contributor
timestamp: April 10, 2023, 06:42:27 am
content: why not consult the rep who sell/recommend this device to you? whenever u asked with a rep or local agent they always ask lots of project details ahead. the money u paid deserves technical support together,

author: Scrts
author_rank: Frequent Contributor
timestamp: April 10, 2023, 09:59:22 pm
content: Quote from: SomeDayFpga on April 07, 2023, 06:03:40 pmSeems like wrong implementation. You set valid to 'high' together with the data, potentially overflowing input FIFO. If you properly clock and reset the logic, then wait for ready signal to be available first, then try to send your data.
Simultaneous read/write with Quartus-|| single clock FIFOs - Page 1
Forum section: electronics / general

author: AussieBruce
author_rank: Regular Contributor
timestamp: April 06, 2023, 06:13:14 am
content: I’m starting to use single clock FIFOs implemented under Quartus-II, implemented as megafunctions. I’ve read through the documentation, and can’t see any specific reference to the query I have, that is: Can writes and reads occur completely asynchronously, or must there be some user input to keep them separate in time?My understanding of FIFOs is that their specific purpose is to allow, for example, reads and writes on the same clock cycle, but I want to be certain. That situation is going to occur from time to time with my application.

author: jahonen
author_rank: Super Contributor
timestamp: April 06, 2023, 09:19:22 am
content: Yes, it is ok to simultaneously read and write with a single clock FIFO. I think that is quite usual use case.Regards,Janne

author: AndyC_772
author_rank: Super Contributor
timestamp: April 06, 2023, 09:49:56 am
content: You certainly can both read and write on the same clock edge, no issue with that at all.Do note that most, if not all, Intel / Altera FPGAs are unavailable to purchase through distribution right now, and have been for some time. Personally I'd be designing these parts out and migrating to a new vendor, unless this is a one-off hobby project, or you have some special arrangement with Intel to obtain a supply of parts.
Trouble shooting ZCU111 RFSoC board - Page 1
Forum section: electronics / general

author: sabeeha
author_rank: Newbie
timestamp: April 05, 2023, 07:26:39 pm
content: HiI was using ZCU111 RFSoC evaluation kitBIST was running fineSuddenly by mistake I powered OFF the button using SW1On power ON ,init_B LED went RED , PS DDR4 LED (das on factory setting of board) went off , all other power and status LEDs are OKBut BIST is not initializing nowPlease suggest some solution
Zynq Quad SPI controller: has anyone used it successfully for non-flash devices? - Page 1
Forum section: electronics / general

author: tom66
author_rank: Super Contributor
timestamp: April 04, 2023, 11:47:15 am
content: Hi allI'm looking at an existing hardware platform which needs to interact with a reasonably high speed quad SPI peripheral (40MHz+). Unfortunately, we do not have any more pins broken out from the PL, but we do have some pins on a connector which go to the Quad SPI peripheral on the PS. This Quad SPI peripheral was never used, as we ultimately used SDIO for boot.Looking at the Zynq TRM it would appear that we could manually drive the RxFIFO and TxFIFO to place commands on the bus, but it's not clear at all to me how this might work in the 'real world'. I need raw access, and the ability to turn-around the lane, i.e. put the QSPI into receive mode and drive clock to receive a response from a downstream peripheral. The lane-turn-around is initiated by external GPIOs, it doesn't work the same way as flash memory devices where a command follows a possible receive. The Zynq manual is not very clear on how this turn-around is done in manual mode.We also need to be able to switch on boot up from 1x SPI to 4x SPI, but we don't need to do that any more than once on start up to initialise the module. (This appears to be possible using the "Legacy SPI" mode.)A quick Google revealed no one else has done this, and the native Linux driver for the Zynq does not appear to support anything other than flash devices. It is worth us writing a custom kernel driver to achieve this if we need to do so. (Lots of field hardware we can update!)Any thoughts appreciated.
Using embedded I2C in Lattice MachXO2 as DS3231 - Page 1
Forum section: electronics / general

author: greenstrike
author_rank: Contributor
timestamp: March 31, 2023, 02:58:02 pm
content: Hi to all!I am using Lattice MachXO2 FPGA.On datasheet I read there is embedded I2C module on this FPGA.I would like to create a fake DS3231 I2C slave, I mean, as exercise I would write I2C slave module, read and write registers from master (microcontroller) and increase internal registers using external clock.Are there available examples about verilog code using embedded I2C modules?Thanks.

author: AK6DN
author_rank: Regular Contributor
timestamp: April 01, 2023, 01:10:28 am
content: How about this ...https://hackaday.io/project/26175-hdl-training-board-by-fpga-for-real-beginner/log/65122-how-to-enjoy-i2c-by-efb-inside-lattice-fpga
How to add in Verilog? Quartus, EPM7064STC44 etc. - Page 1
Forum section: electronics / general

author: NivagSwerdna
author_rank: Super Contributor
timestamp: March 27, 2023, 08:25:59 pm
content: So following on from my other thread I am essentially going to try to target a EPM7064STC44 and develop in Verilog using Quartus II 13.x...All is going well for my first design... so moving to my second...I have 2 values (both 8-bit unsigned) that I have to add together and then add 1... I need to produce the output.Now simplistically...adj_value = value1+value2+1This works but produces some interesting output...Info (278001): Inferred 1 megafunctions from design logicInfo (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add0"Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add0"OK... well if it wants to I suppose it can...but this one is a bit more worrying...Warning (10230): Verilog HDL assignment warning at Thing.sv(25): truncated value with size 32 to match size of target (I have...reg [7:0] adjusted_value;always @(posedge s1_i) beginadjusted_value = value1+value2+1;endSo really I just want an 8 bit full adder (where I can use the lowest carry to incorporate my +1)These warnings made me wonder... Should I be using something that is more knowledgeable about the underlying device? Can I force the arithmetic to 8bit? Should I bite the bullet and use a megafunction (and lock myself into the IP) or is there some more portable middle-ground?Apologies for the newbie question!

author: AK6DN
author_rank: Regular Contributor
timestamp: March 27, 2023, 08:40:32 pm
content: The warning is referring to the unsized constant "+1" you are using, it will be inferred as 32b by default.So you are adding two 8b values and a 32b value and storing an 8b result. Thus the (innocuous, usually) warning.If you want change the "+1" to be a sized value, like "+8'd1" to make it an 8b decimal 1.Or just ignore the warning.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: March 27, 2023, 09:02:33 pm
content: That fixed it! Thanks!PSI could probably squeeze an extra LUT by going proprietary but I have spare. Much nicer to be more portable.