Memory - die pictures - Page 1
Forum section: electronics / projects

author: Noopy
author_rank: Super Contributor
timestamp: September 10, 2021, 03:37:39 am
content: Let´s start a new topic for memory die pictures.At first I wanted to split the topic in RAM and ROM but in my view volatile and non-volatile is more convenient:https://www.richis-lab.de/RAM.htmhttps://www.richis-lab.de/ROM.htmToday let´s take a look into a FRAM, a Cypress FM24V10 (1MBit).The die is 3,2 x 2,0mm. There is a huge amount of bondpads. Perhaps you can use the die in a parallel configuration too.You can spot the big uniform memory area divided in eight columns. There is probably some control circuit on the right side of the die.The structures are tiny but you can spot the year 2008.The memory itself is way too small to do a deep dive.https://www.richis-lab.de/RAM01.htm

author: RoGeorge
author_rank: Super Contributor
timestamp: September 10, 2021, 08:24:24 am
content: Thank you, subscribed!

author: Noopy
author_rank: Super Contributor
timestamp: September 13, 2021, 08:00:27 am
content: HML087, you don´t find very much about this chip. It´s a PROM manufactured by Hughes Electronics and can be found in BMW instrument panels.The die is 2,9mm x 2,1mm.HMLOh it seems to be a HML069. You find the HML069 in some old universal programmer manuals. It´s a PROM that has to be programmed with 12,25V.There is a 8C in the metal layer and above it is something like 4A or 4H, probably 4A.Unfortunately layer 3B is quite hard to read that makes it difficult to analyse the circuit.Quite some masks: 1A, 2D, 3B, 4A, 5B, 7B, 8C, 11A, 16DThe different crosses allowed them to check the alignment of the masks.test structuresA big test structure. That´s probably kind of a ring oscillator. There is even a fuse!Most of the bondpads have the same protection structure.The output is easy to spot. There is a big highside and a big lowside transistor around it. From the left there comes a differential control signal.The right bondpad is the high voltage input you need to program the device. It has a different protection circuit.On the left side of the die there are seven similar looking blocks that get the chipselect and the clock. Three are connected to the line selection. Four are connected to the column selection. That are probably Flip-Flops counting the clock pulses and switching from one memory cell to the other.Leftmost there are six similar looking blocks connected to the Flip-Flops, probably some support circuit.On the right side of the die there are eight similar looking blocks connected to the input bondpad. They are controlled by the circuit in the middle which uses the line selection signals generated on the left side of the die. That is probably the latch for the data input. The output of the latches controls the second part of the line selection circuit.There is a ninth block locking like the latches. It is not connected to the line selection just to the input signal. There are two lines connected to something on the left side of the die.That´s a good picture of the actual memory. There are 16x8 memory cells. On the left side is the output circuit (it´s connected to the output bondpad). On the top there is the column selection. On the right side there is the line selection (read/write) and on the bottom there is some biasing and control circuit.Every eight columns have one column selection block. Each column selection block consists of a lowside area and a highside area (in the middle) giving you a push-pull driver for every column.The output circuit is hard to read.The line selection is quite complex. On the left side you see four lines going into the memory area (red/green). Every memory line has one red and one green line.On the right side there is the write circuit. The latches switch the HV or the GND to the red lines.The green lines are connected to the red lines with the short dark green lines. The yellow transistors are controlled by the line selection generated on the left side of the die.An overview...Here we have the memory. It is built out of 2x2 cells. Each cell consists of a floating gate transistor (FG) connected to the red line and a selection gate transistor (SG) connected to the green line that is connected to the output circuit too. A short red line (the "real" red) connects the FG and the SG.I assume reading a cell is done like this:The column selection switches a high on the column we want to see. The others are low.The outer red lines (formerly marked red) are low.The inner red lines (formerly marked green) are low too except the one we want to select. This one is floating.The floating gates normally need a mid range voltage to work probably. I assume the high of the column selection is routed to the floating gates by the uppermost line in the lower area. Perhaps the low in the second line is connected to the floating gate line too to get this mid range potential.Now the combination FG / SG switches the low of the outer red lines to the inner red lines if the floating gate has been programmed active.I assume the output circuit contains weak pull-ups that are pulled low by the inactive lines. The active line remains high or is pulled low by the FG/SG depending on the data in the FG.I´m not perfectly sure about that explanation but it seems reasonable.If you want to write data you just have to select one column no line because you have already eight bit of data in your latches that control all the lines at once.On the outer red lines (formerly marked red) there is HV if we want to program the FG and a low if we don´t want to.In the column we want to write the SG is high and with the help of the circuit at the bottom also the FG is high.The output circuit probably switches a low on the inner red line (formerly marked green).In this configuration the drain source voltage of the FG transistor is quite high and there is a mid range gate source voltage. The high voltage generates charges by avalanche effects that are attracted to the gate and stored there. This is called "Drain Avalanche Hot-Carrier Injection". That´s not very good for the gate oxide but in a PROM you do that only once.https://www.richis-lab.de/ROM01.htm

author: Noopy
author_rank: Super Contributor
timestamp: October 15, 2021, 07:06:19 am
content: Well a BBD is also a memory, it´s an anlog memory.The other BBDs can be found here:https://www.eevblog.com/forum/projects/different-die-pictures/msg3632153/#msg3632153(and following)And of course I have listed them here:https://www.richis-lab.de/bbd.htmNow that should be a Matsushita/Panasonic MN3007. The MN3007 is the PMOS version of the MN3207 (https://www.richis-lab.de/bbd04.htm).Surprise! That´s not a MN3007 but a MN3207!Interesting they changed a MN3207 to a MN3007. The MN3207 is completely useless in a circuit designed for the MN3007. It would have been more economic to use any other DIL-8 chip and sell the MN3207 as it is.Looking at the MN3207 (https://www.eevblog.com/forum/projects/different-die-pictures/msg3672253/#msg3672253) I just found five masks. With the better picture out of the counterfeit MN3007 we know can spot the sixth mask. It seems to be a via in the silicon oxide.Here you can see the way the MN3207 went. The MN3207 has a pin 1 marking and some kind of a frame.The MN3007 in the middle has just been ground a little. You can still see the pin 1 marking and the frame except in an area in the upper left corner. There are also some grinding marks.The right MN3007 has been ground flat. They had to paint it and because of that the pins are black on their shoulders. You can spot grinding marks too.https://www.richis-lab.de/bbd05.htm

author: Noopy
author_rank: Super Contributor
timestamp: November 09, 2021, 09:01:50 pm
content: U552C built by VEB Mikroelektronik Karl Marx (what a name). The U552C is a p-channel EPROM with 2kBit of memory. It is similar to the first EPROM 1702A built by Intel. RD should be the date code for December 1983.Since the EPROM can be erased with UV light it has a window on top of the package. Here we see the version with a special ceramic window. They did a different version with a quartz glass window. The ceramic window needs nearly three times more light to erase the memory.Since the U552 is a p-channel EPROM it needs 5V at Ucc and Ubb and -9V at Ugg and Udd to work properly. To write information into the memory you have to decrease Udd to -48V and increase Ubb to 13,2V (max voltages).CS is chip select. PR makes it possible to write data. P1 and P2 are test inputs.Udd and Ucc are connected with two bondwires. Ubb is not connected directly but the pin is connected to the area below the die. This special pin is tagged with an arrow on the package.The die is 3,5mm x 3,2mm. The smallest structures are a little smaller than 10µm so it´s easy to identify and analyze the circuits.Some markers to check the process quality.There are five numbers. In GDR the masks were named with letters while numbers showed the revision. It looks like they had to modify one mask eight times!And some test structures!This one looks like a normal MOSFET.Here on the left side, there is another "normal" MOSFET. On the right side there is a MOSFET with a metal gate electrode. Sometimes such MOSFETs with a thick gate oxide are used for ESD protection.Perhaps a MOSFET with a polysilicon gate but a thick gate oxide?On the lower edge of the die there is a metal line connected to two testpads so you can check the conductivity of the metal layer.Hey, some kind of a logo that is integrated in an active structure.The S-layer acts as gate electrode for the transistors left and right of the S.At every input bondpad there is the complementary type of a grounded gate NMOS (ggNMOS). In this MOSFET a parasitic bipolar transistor is conducting whenever an ESD impulse occurs.On the right side of the die there are two 32x32 memory arrays (white). The address inputs A0-A6 are converted in differential signals (blue). A0-A4 control the column selection between the two memory areas (green). The 2*32 lines are converted to 2*16 to 2*8 to 2*4 (cyan). The address inputs A5-A7 control these switches. The 8 output signals are fed into an inverter stage (orange). If the chip select circuit (pink) is active the inverter stage can control the push-pull output stages (yellow) O1-O6. If you want to write data additional transistors (red) bypass the output stage.

author: Noopy
author_rank: Super Contributor
timestamp: November 09, 2021, 09:02:57 pm
content: The input/output circuit is relatively complex.On the right side there are the outputs of the memory lines (L1, L2,...). Here we can see just two of the three multiplex stages (yellow). There is a Pull-up- and a Pull-down-transistor at the output line of the multiplex stage (green). The inverter stage (white) consists of two inverter that share one Pull-Up. The differential output of the inverter stage controls the Push-Pull output stage (blue/red). Between the inverter and the output stage there is the chipselect circuit that is able to drain the current controlling the output stage.Some transistors used as resistors are controlled by Ugg. The datasheet states that you can toggle Ugg to reduce heat dissipation.While writing the input pin PR activates the pink transistor that bypasses the output stage to get the input signal at O1 to the multiplexer.Here we see the amplification stage for the CS signal. The big transistor switches to Udd. In the upper right corner there is a small Pull-Up-transistor.In the memory array there are horizontal metal lines transferring the information. After four information lines there is one Ucc line.Vertical polysilicon lines transfer the column signals.The memory cells are similar to the memory cells in the HML087 (https://www.richis-lab.de/ROM01.htm). Two memory cells share one via to the horizontal line. The active area in the substrate is formed like a grid. The vertical lines distribute Ucc. The horizontal lines are the base for the memory cells.Every memory cell consists of a control gate and a floating gate. The polysilicon column line activates the control gates. The state of the floating gate controls whether Ucc is connected to the horizontal line or not.You can put charges into the isolated floating gate by using high voltage. The datasheet specifies 0V at Ucc and -46V to -48V at Udd. The horizontal line and the column line are connected to Udd. With this voltage you generate hot electrons that can travel into the floating gate. As soon as you have charges in the floating gate the memory cell conducts Ucc.While writing you have to put Ubb to 10,8-13,2V. The positive voltage is necessary to drain the free charges that are generated.Up to 61,2V, holy shit...UV light generates free charges in the whole circuit which allows the charges to drain from the floating gate. Writing and erasing damages the gate oxide. That is why an EPROM is dead after a lot of write cycles.It works like this: One column is selected which activates the control gates (yellow). Depending on the state of the floating gate Ucc is switched to the horizontal line (green/grey).Here we see the column selection circuit between the memory blocks. Differential signals generated out of the address inputs A0-A4 are fed from left and right into the circuit.The opposing columns are connected by the metal layer (yellow). Below the upper memory block there are Pull-Ups (white) that are connected to the column connection line (green).At the contact of the Pull-Up there is the beginning of an active area that travels to the lower memory block. The horizontal polysilicon lines form transistors (red). Some are shorted by the metal layer. Depending on the potential of the polysilicon one column line is switched to the Udd potential at the bottom of the column selection area.The active area is splitted at some points (cyan) so the lines next to each other don´t interfere with each other. In addition the uppermost three polysilicon lines do a special job. One column is connected to an area above the first line and the next one is connected between the next two lines which conduct the inverse potential of the first one (blue). These two columns are always isolated from each other.Address input circuit which generates differential control signals.There are two test inputs that are connected to a circuit located between the input/output circuit and the memory area. There are two lines of transistors that can switch the horizontal lines to Ucc (red). The first line isn´t connected to any transistor. The other lines are connected alternating but not in an uniform manner. You can´t really switch off half of the memory if you have faulty cells because the other half would be place chaotic in the address area. Strange...In addition P1 can bypass two floating cells in the first line.At the bonpad of P1 there is a single memory cell. You can see that the active area is thinner at the floating gate. The control gate is connected to P2.https://www.richis-lab.de/ROM03.htm

author: Noopy
author_rank: Super Contributor
timestamp: November 19, 2021, 06:43:00 pm
content: The MOSTEK MK37092 is a NMOS-Mask-ROM with 8kB of memory. The naming of the memory chips is explained in the datasheet except for the three numbers 092. As we will see later it looks like 092 is the name of the project, more precisely the data that is written into the ROM.The datasheet shows us the internal setup of the memory.It looks like the contacts in the package were arranged to perfectly fit to such a memory die.It seems like half of the die was cut and the lower half was broken to get the die out of the wafer. That was a common procedure.The die is 5,3mm x 4,8mm.There are some mask markings on the die. The name of the ROM and the mask revisions can be found in an area which isn´t coated by the passivation layer. The metal looks brighter in this area.Mask 1 forms the active area. Mask 2X includes some special doping which is necessary to "program" the information into the memory array. We will see that later. The numbers 092 are integrated with this mask so 092 is probably the number of the project. If there is this special doping under the gate of a transistor the threshold voltage is modified. We can´t be sure whether 2X is one mask or there are two masks named 2 and X. One for normal operation (2) and one for the data (X). In the upper picture 2 and X are in two separated squares.Mask 5 forms the polysilicon. Mask 8 forms the metal layer. Mask 7 seems to generate the vias. I´m not sure about mask 6 perhaps that´s another via, one to contact the polysilicon and one to contact the active area.There are a lot of test structures on the die. These strings contain small polysilicon stripes connected with the metal layer. I assume that´s for testing the interconnection resistance. I further assume the two long structures left and right of the die and the different spacing is for identifying local process imperfections.Some transistors with different W/L-factors.That looks like small parts of the memory area.On the left side you can measure a stripe of the polysilicon and a stripe of the active area.On the right side you can contact a normal transistor with a polysilicon gate and a metal gate transistor.Some more transistors... ...but here there are no contact slots in the passivation layer...Here we see the structure of the memory area without the metal layer. I will explain how it works later. In the three areas the width of grid structure is different.The ROM was designed in 1980. The test structures show the resolution of the manufacturing process. Metal layer is a little coarser than the other structures.

author: Noopy
author_rank: Super Contributor
timestamp: November 19, 2021, 06:44:10 pm
content: The memory consists of four blocks (red), each containing 256x64 memory cells. The inner blocks have two, the outer four additional rows that do not contribute to the memory size. However, these are not just dummy structures, which have to ensure a functional core. They partly serve the function of neighboring memory lines.Most of the address lines arrive from the right. On the right side there are the 12 input buffers too (yellow). The address lines A0, A1, A10 and A11 control a first multiplex column (blue). This column generates 16 control signals for each memory block. Address line A9 doubles the control signals in a second column, so in each memory block 32 lines can be selected (white). In each memory block there are always two lines active.To select a column in a first step the address lines A2, A3, A5, A6, A7, A8 and A12 in the middle of the die are converted into 128 control signals (black). The address line A4 controls two small output stages at the left end of the memory area. The two output signals of this circuit are connected to the two double lines, which in turn realize the column selection (pink). The address line A4 thus doubles the 128 control signals and only one of the 256 columns of the memory is activated.At the left output of each memory block, the 64 lines are combined to two outputs (orange). This grouping is possible because only two of the 64 lines are active simultaneously. A mixing of the information cannot occur if you have done the interconnections right.The output signals of the four memory blocks are fed to two output stages each (light green). The signals pass through another circuit (dark green) which contains the drivers for the output stages.Here you can see two buffer stages for the address lines. The differential outputs are connected with the first stage of the line selection. The input signals of the corresponding bondpads arrive from above and contact the buffers on the right side. Vertically, four common control lines run through all buffer stages.The differential signals of the address lines A0, A1, A10 and A11 are connected to eight vertical lines which pass through eight active areas at each of the four memory blocks (red). In these active areas there are two rows of polysilicon gate electrodes. The gate electrodes are placed and contacted in such a way that, depending on the address applied, only one of the 16 outputs in each memory block becomes active. Considering the whole memory, there are four control signals active.To the left follows the changeover switch, which ensures that 32 line pairs can be selected with the 16 control signals (green). The alternating contacts in the two vertical running control lines are clearly visible. Strictly speaking, this is not a changeover switch. The active areas contain two switches which are supplied by the two vertical lines. By switching the two supply lines, one ensures that just every second active area can switch through the desired signal.Behind the block with the changeover switches there is another circuit. Probably there are supporting circuit parts, like pull-up or pull-down structures.The interruption between the inner and the outer memory block is caused by the interconnection circuit at the left side of the memory block. The control on the right side has been mirrored for better signal routing.After removing the metal layer it becomes more obvious how the line selection circuit is working. Even without a complete analysis it´s clear that there is always one inactive line between the two active lines.In the right area you can see how the control signals are generated out of the differential address lines. It´s like a NOR circuit. The output is active when none of the transistors is active.Column selection is performed with the other differential address lines running horizontally in the middle of the die. Similar to the row selection, the lines contact vertically arranged polysilicon strips. Half of the total 14 address lines are located above the wider Vss line in the middle, the other half is located below it. Depending on the contacting of the polysilicon strips and the structure of the active area below only one of the 128 control lines is active.Between the address lines and the memory areas there are two lines each, which can drive the columns. Depending on the status of the address line 4, one of the two lines becomes active and thus one of 256 columns can be selected with the 128 control lines. In the lower and the upper memory blocks always the same column is active.A closer look does not reveal the function of the column selection right away. Although there are some differences in the structure and contacts, the majority of the structure appears quite uniform.After removing the metal layer it becomes clearer. At the lower edge of the picture small part of the column selection circuit is shown. There are small vertical polysilicon strips which are connected partly at the upper partly at the lower end with one of the address lines. The active transistors connect the columns to Vss until the address of the column is selected, thus disabling all transistors. Above the address lines is a pull-up structure.The two rows of column selection circuits are basically the same. The lower area of the upper row and the upper area of the lower row are just extended a little so the necessary interconnections could be made.

author: Noopy
author_rank: Super Contributor
timestamp: November 19, 2021, 06:45:15 pm
content: The structures in the memory area do not reveal anything about the programming. The metal layer is connected to the active area at regular intervals. Two polysilicon lines of the column selection run between each of the vias.The functionality becomes clearer as soon as the metal layer is removed. The memory is based on a diagonal grid of the active area. The polysilicon lines run above this grid. In the lower picture they are marked with straight stripes. In fact, they run in a curved pattern as you can seen in the test structures. The polysilicon strips form transistors in the diagonal connections between the crossing points. In the crossing points, the metal layer contacts the active region.There are always two rows active (green) with one inactive row in between. Actually at the lower end of the memory area there are three lines active. I have ignored this here for better understanding. Each memory line needs two adjacent lines to do it´s job properly. This explains a lot of the dummy lines. They do not directly contribute to the usable memory. Parallel to the two active rows, one of the columns is active (green). The active polysilicon line can activate two of the diagonal transistors at each memory cell in the column. An active transistor causes the potential of the active row to be pulled to the potential of the neighboring inactive rows (bottom row). The desired information is introduced into the memory area by adding an additional doping. If one changes the doping in the diagonal transistors (blue) they never become conductive. The selected row is not affected and delivers a high level to the output (upper row).After removing the polysilicon there are just the outlines of the active areas left. The doping that represents the programming is not visible. Even in a sharper image it would not stand out. However apparently there are special chemicals that can be used to make different dopants visible.At the left end of the column selection you can see the buffer stages that realize the switching of the two column driver lines for the upper and the lower memory area.Left of the memory area the rows are interconnected in a circuit with two columns. The circuit outputs two differential output signals from each of the four memory blocks. Since only two rows are active in each memory block the circuit does not require any additional control. The rows simply need to be alternately connected to one of the outputs.Left of the interconnection circuit there is a circuit section that most likely takes the output signal of the memory, does some signal conditioning and switching (OE) and drives the output stage. Each output has a large lowside and a large highside transistor placed directly at the bondpad.The bondwire leading to the bottom of the ceramic package is connected to the substrate, to a frame structure and to a circuit. Perhaps the circuit generates a negative voltage that is supplied to the substrate. A negative substrate gives you better transistor performance. We have seen such circuits on the die of the NEC µPD7220 (https://www.richis-lab.de/GraKa02.htm)In the upper left corner of the die there is a preparation for an additional bondpad. Just the metal layer is missing. Probably you can use the die in a different configuration as well.We can take a closer look at the input protection. The bondpad is connected to a resistor strip. The reddish frame overlaps the end of the resistor strip. The frame carries the presumably negative substrate potential. The overlapping area most likely forms a diode that limits negative input voltages.The seemingly unnecessarily long and wide metal line from the bondpad to the resistor strip forms a transistor with the structures underneath. The resistor strip runs parallel to an active area. In the event of an overvoltage the gate-source voltage of the transistor is high enough to establish a conductive channel between the resistor and the active area under the metal electrode. That´s the protection path for overvoltages.https://www.richis-lab.de/ROM02.htm

author: Noopy
author_rank: Super Contributor
timestamp: November 22, 2021, 05:01:24 am
content: Quote from: Noopy on November 09, 2021, 09:02:57 pmSome more pictures to get the memory cell structure of the U552 clearer.After removing the passivation layer and the metal layer the areas under the metal remains opaque and must be dissolved with the underlying silicon oxide layer. In the process, however, the polysilicon strips are also gradually removed. So you have to be careful with the HF.You can see the active layer under the memory cell pairs narrows towards the central contact. In the narrower region there is the isolated floating gate. Towards the Ucc distribution the control gate activates all memory cells belonging to the column. In these pictures you can see that the Ucc distribution in the active layer does not extend through the complete memory block but is interrupted every eight rows.The active areas are p-doped (red). Just under the polysilicon gate electrodes (green) the n-doping of the substrate (blue) is still present. In the center, the metal layer contacts the memory cell pair (purple/black).When programming a memory cell, -47V are applied to the associated row and column line. The control gate thus creates a conductive channel. The potential of the row line causes a charge shift in the floating gate. The high voltage is sufficient to create a conductive channel under the floating gate as well and a current flows. On the left, the potential of the control gate is fixed at 0V, so no conductive channel can be formed underneath.As the active region narrows in front of the floating gate the current density increases. The high current density generates a large number of free charge carriers. Some of the charge carriers are drained through the active region. The negative charges are more mobile than the positive ones. Some of them spread out in the substrate and must be drained there (12V). However, a certain part of the charges penetrate the thin gate oxide of the floating gate and is trapped there.From now on, the negative charges deposited in the floating gate ensure that a conductive channel remains under the floating gate. If the associated column is activated, the row line is connected to the Ucc potential.

author: Noopy
author_rank: Super Contributor
timestamp: April 16, 2022, 03:49:58 am
content: Tesla MHB4164, a 64kBit-DRAM built by Tesla.The die is 7,0mm x 3,4mm.Hey, the IC is a U2164, a 64kBit-DRAM developed by the "Zentrum für Mikroelektronik Dresden"!I don´t know for what the 5 stands for.There is an elephant or mammoth. That reminds me of the elephant I have found in the 16kBit-DRAM 4116 built by ITT packaged by Mikroelektronika Botevgrad:https://www.richis-lab.de/prawez06.htm#ElefantIs there a connection? Or is it normal to put an elephant in an DRAM?To understand how the U2164 works it helps to first take a look at the block diagram of the U256. The U2164 is based on this 16kBit DRAM.The signals RAS, CAS and WRITE control three clock generators which are linked in a way that the necessary functions are started at the right time.The 7 address lines are routed to a multiplexer for row or column selection. The row decoder generates 128 control signals out of the 7 address lines, which allow to select one row of the memory area.The memory consists of two 8kBit areas. Each 8kBit area contains 64 rows and 128 columns. In addition to the 128 rows used to store data, each 8kBit area contains a row of 128 dummy cells. The dummy cells provide reference values for the readout amplifiers.According to the datasheet, the refresh circuit is integrated in the center of the memory area with the readout amplifiers. After a line has been read, its information is no longer available in the memory and must be written to the memory cells again. This task is performed by the refresh circuit. However, the charge stored in the integrated capacitors also ages due to leakage currents. For this reason, the complete content of the memory must be refreshed once every 2ms at the latest.Although only a single memory cell of the DRAM is addressed, there is alwayse a complete row read out. The column decoder uses only 6 Bits, so there are always 2 of the 128 columns active at the same time. The selection which data should be routed to the output is done outside the memory area via Bit 7. Writing data follows the same pattern.The block diagram in the datasheet of the U2164 shows that the structures of the U256 were integrated four times. In the center there are 64 sense amplifiers for each 8kBit matrix. The decoders in the columns between the 8kBit blocks activate one row in each matrix. Thus the memory area provides a total of four data lines, one of which is selected by address bit 7. One bit is sufficient here because it can be used twice by row and column selection.The U256 requires a +12V, a +5V and a -5V supply. With the U2164 a +5V supply is sufficient. The device itself generates a negative voltage for the substrate.In the "Radio Fernsehen Elektronik" 08/1989 there is a detailed article about the U2164. Also the die is shown, which seems to correspond to the die in the MHB4164. According to the "RFE", more than 140,000 transistors were integrated.Most of the function blocks can be identified on the die. The 8k memory areas (green) consist of 65 columns and 130 rows. RFE explains that one column and one row serve as a reserve to increase the yield. If individual cells are faulty, these areas can be integrated into the memory. One row provides the dummy cells necessary to effectively read the memory cells. At the top and bottom outer edges are most likely the circuits that precharge the bit lines and the dummy cells with the reference level (blue).Between the memory blocks is the row selector (red), which takes seven adress lines and activates one of the 128 rows. The memory areas output 64 signals each, which are processed by 64 sense amplifiers (pink). In addition the sense amplifiers write back the active line completely. This line must then be refreshed again after 2ms. The column decoder (purple) selects one of the columns. This results in a total of four active cells. The circuit for selecting a single cell out of the four is not directly visible.At the left edge is the push-pull output stage (orange) and the circuit to generate the negative substrate voltage (cyan). On the right edge, you can see the analog multiplexer that switches the address lines back and forth between row and column selection (yellow). Two areas contain 16 and 18 equally spaced, relatively large elements (black). They probably are buffer and driver for the row and column selection, input and output data....

author: Noopy
author_rank: Super Contributor
timestamp: April 16, 2022, 03:51:05 am
content: The structure of the memory cells is described in detail in the RFE article. According to this, a memory cell contains a storage capacity of 50fF. This is the classic DRAM structure with one capacitor and one selection transistor. The article also shows the actual structure of the memory cells. One bit line, represented by the metal layer, always serves two memory cells. Polysilicon layer 2 simultaneously maps the word lines and the gate electrodes of the select transistors. Polysilicon layer 1 forms a relatively large area that serves as a capacitor.The memory area actually contains not 64 but 128 columns. Each sense amplifier is connected to two adjacent columns and evaluates the difference between the columns. The arrangement of the memory cells ensures that when two columns are active, one column contains the desired information while the other column provides the reference value of the associated dummy cell. This type of differential evaluation with the reference value of a dummy cell is common in such memories.Splitting the columns in such a way that the two active columns are directly next to each other additionally reduces the soft error rate. This describes the number of sporadic data errors that are not due to hardware errors. The main causes are alpha emitters in the package material, cosmic radiation and neutron radiation. Even small amounts of ionizing radiation can create a current flow that leads to loss of information. The paralleled lines of data and reference signal increase the probability that ionization will affect both lines equally and the information will be preserved.In total, each memory area contains 130 rows and 130 columns.How exactly reserve rows and columns could be activated remains unclear. For this, defective areas must be disconnected and reserve areas must be integrated into the circuit.There are sections at the edges of the memory blocks that could be suitable for interruption with a laser. Whether a separation would really have taken place in this way remains open.Here we have the adress lines in the column decoder.Detail of the precharge circuit.Raw decoder...Here we have the analog mulitplexer (tilted 90°). At the edge you can see 8 input signals and there are 16 output signals.The 16 signals are routed to the memory area and to the "8+8+2 latch area".The circuit for generating the negative substrate potential shows the typical structures for this. The area on the far right could be the oscillator for the charge pump. In the middle, relatively large elements, capacitors and transistors can be seen, which probably represent the actual charge pump.One could think that the bondpad on the left would be connected to pin 1 of the package. This is where the -5V supply is to be applied on the U256. Here, however, the bondpad is most likely connected to the substrate carrier, just like in the D82720 (https://www.richis-lab.de/GraKa03.htm). Fittingly, no relevant resistor, diode or voltage can be measured at pin 1 of a U2164.There is a double metal frame enclosing the whole die and contacting it many times. This effectively distributes the negative potential.In the cutting streets there are test structures. Here is looks like we have three different transistors.The protective structures at the inputs are also described in the RFE article. A grounded gate NMOS becomes active when the voltage is too low and establishes a conductive path to the GND potential. The series resistance limits the current flow. Voltages up to -2V may nevertheless not be applied for longer than 40ns. It is only a protection against undershoots, which can occur with steep switching edges.If even lower voltages are present, then the parasitic diodes become conductive. Since this path has no current limiting, such low voltages are not allowed. At very high voltages (RFE specifies 12V) the grounded gate NMOS also becomes conductive and protects the circuit.Here we have the push-pull output stage and the driver for this stage.https://www.richis-lab.de/RAM02.htm

author: Noopy
author_rank: Super Contributor
timestamp: January 11, 2023, 08:09:19 pm
content: The EDI8832C is an SRAM built by the American manufacturer Electronic Design Inc. The designation EDI8832C120CI reveals how the memory is constructed and which specifications it complies with. EDI is the manufacturer. The first 8 stands for the product group SRAM. The second 8 is the word width and the number 32 is the memory depth, resulting in 32k * 8Bit. The letter C shows that 4T memory cells were used. There are also variants with 6T cells. 120ns is the access time. The last two letters show that it is a ceramic package and that the device is approved for the industrial temperature range.In the "CMOS Static RAM DATA BOOK" EDI describes the differences between 4T and 6T SRAM cells. While in a 4T cell two transistors with two resistors store a logical value, in a 6T cell this function is performed by two CMOS pairs. The transistors to the right and left of the actual memory cell enable selective addressing of a word line. The biggest disadvantage of 6T cells is the higher area consumption. In addition, there is a somewhat higher access time. An advantage is the lower power requirement compared to a 4T cell.The block diagram in the datasheet shows the basic operation of the device. However, it is rather a principle representation. The memory array has a size of 256kBit, but just 14 address lines are shown. Six address lines therefore activate four rows. This results in 4096 active columns, which can only be reduced to 16 bits by the remaining eight address lines in this diagram. The control circuit then ensures that reading from the active cells or writing to the cells takes place.The housing contains a relatively large die. The two supply potentials are connected with two bondwires each. The die attach material is scratched surprisingly severe in the gaps.The die is covered with a polyimide layer. The thickness of this layer can be seen in the recesses for the bond pads.M5256B is probably an internal designation. In front of and behind it are some test structures, which make it possible to judge the performance of the manufacturing process.The dimensions of the die are 8,2 x 4,6mm. On the left are the data IOs. The address lines arrive on the right side of the die. The memory is composed of two areas, which in turn contain two equally structured areas. The wide stripes between these areas probably contain the column selection. The exact function cannot be clarified with absolute certainty because of the polyimide layer.A strip with test structures is integrated on the right edge of the die.Each of the four memory areas is contacted on the left side with eight structures that look the same. In detail, you can see that each of these structures contains 16 lines. This indicates that the memory contains 512 lines. The address lines, which were not needed for the column selection, select the desired 8Bit out of these lines.There is an interesting artefact in the middle of the die. Apparently, the circuit has been overloaded there. The polyimide layer is literally burned out. The location of the damage is surprising. Such high-energy overloads would rather be expected in the area of the inputs/outputs.https://www.richis-lab.de/RAM03.htm

author: Noopy
author_rank: Super Contributor
timestamp: March 16, 2023, 09:19:41 pm
content: The MH74S287 is a PROM built by Tesla with a memory depth of 1024Bit. It is a bipolar Schottky PROM with tristate outputs.The datasheet shows the basic structure of the MH74S287. The memory (IV) contains 32x32 memory cells. The first address decoder (I) generates eight control signals from the first three address lines, which activate one line each from four memory groups. The second address decoder (II) generates 32 control signals from the remaining five address lines, which activate one of the 32 columns. Thus the contents of four memory cells are transmitted to the output amplifier (V). The output can be controlled by the control signals S1 and S2.The IEEE paper "A Reliability Assessment of Bipolar PROMs" shows how the memory cells of a bipolar PROM are basically constructed. At the nodes of rows and columns there are fuse elements which are triggered by a current surge during programming. If a row is set to low potential in the circuit shown here, it depends on the state of the fuse element whether the low potential is transferred to the transistor of the respective column. The transistor, which can be activated via its base potential, transfers the state of the active memory cell to the output. The diodes ensure that really only the desired cell is read out and that no unwanted current flows through other areas.PROMs usually contain a test line and a test column. This is necessary because the functions of a PROM cannot be tested easily after production. If just an unprogrammed matrix exists, it is not even possible to test the selection and sensing circuit. For this reason, a test line and test column are usually integrated, which make it possible to test both writing and reading without influencing the usable area of the memory.The IEEE article above also provides an overview of the entire circuit of a PROM. The basic design of the PROM shown there is very similar to the MH74S287. However, the MH74S287 works with an inverse logic. Here the address decoder puts one row to ground. The column decoder selects one column each from four groups of 8. When the output is activated, the active transistors pass on the stored information.Programming is done here by applying a high potential to an enable pin, which triggers the associated fuse element via the transistor in the column selection and the configuration of the row decoder.The die of the MH74S287 is 3,6mm x 2,6mm.The type designation S287 is shown in the upper left corner of the die.Tesla's logo is shown in the lower right corner. There are also the revisions of seven masks, some of which have been revised very often.A little further to the left, squares are integrated that allow you to check the alignment of the masks against each other.The individual circuit parts are clearly visible on the die. In the center is the 32x32 memory (red), which has an additional test line at the upper edge and an additional test column at the right edge.The address lines A4 to A8 are evaluated in the left area (cyan) and fed to the column decoder (yellow) including their complementary values. The column decoder then switches Ucc to one of the 33 columns.To select one of the 32 columns you already need all five address inputs. To be able to select the test column nevertheless, the address input A4 has been extended with the additional circuit A4*. This is usually a circuit which becomes active only at a voltage which is not present in normal operation. If you want to test the PROM, you apply a slightly higher potential to pin A4 and thus reach the test column.To the signals of the address lines A1 to A3 the complementary potentials are generated too (dark green) and fed to the line decoder (orange). Here the input A2 offers the additional function to activate the test line. The eight control lines of the line decoder are fed to four blocks, where they select and forward one line in each block out of eight lines (pink). The ninth control line connects the test line to output Q1.The four tristate outputs (green) are arranged in pairs and share a small circuit section. In the upper left area is the enable circuit that activates the outputs (purple).The memory area is connected to the Vcc potential with very low impedance. Each of the four blocks is flanked by horizontal Vcc lines.The IEEE article "A Reliability Assessment of Bipolar PROMs" contains a sketch with the typical structure of a bipolar PROM. In this case, the cells are arranged in pairs. The core of the memory cells are the fuse elements, which are usually made of a nickel-chromium alloy. Alternatively, a titanium-tungsten alloy or polysilicon directly has been used. In addition to process-safe manufacturability, low resistance in the intact state and reliably high resistance after the fuse element burns out are important.In circuit diagrams, base-emitter paths of transistors are often located in series with the fuse elements. Here, there is no emitter. Instead, the base-collector junction has been used as a diode. Below the fuse elements are p-doped squares in the n-doped collector layer. The IEEE article emphasizes the robustness of this implementation. Compared to base-collector diodes, base-emitter junctions are more prone to production defects and failures.Vertically (horizontally in the MH74S287), the bit lines run in the metal layer. Horizontally (in the MH74S287 vertical) the word lines run, built up with heavily n-doped regions. Between the bit lines, elements of the metal layer reduce the resistance of the word lines. A low-resistance design of these areas but also of the surrounding circuit is important so that a sufficiently high current can flow when the fuse elements are triggered. At the same time, the circuit must also withstand the increased voltage used during programming.The IEEE article "Reliability Assessment of a Semiconductor Memory by Design Analysis" shows the typical structure of a nickel-chromium fuse. The taper there is 3,8µm wide. This corresponds to the sizes in MH74S287.Fuses of the metal layer, which are used to adjust integrated circuits, have openings in the passivation layer so that it does not suffer large-scale, undefined damage when the fuse is triggered. This can be seen well, for example, on the die of the LTFLU (https://www.richis-lab.de/REF04.htm#fuse). The fuse elements of a PROM, on the other hand, are located under the passivation layer. This is possible because they are triggered with much less energy.The amount of energy and the exposure time with which the fuse elements are triggered are critical design parameters. Strips that are not optimally fused can regenerate. The IEEE article explains this effect in more detail. If the fuse does not fuse far enough, a very high electric field is established in the opening. The metal oxides that have formed there can then cause a breakdown despite the low voltage and for the evaluation circuit the fuse appears intact again.If you compare the sketch from the IEEE article with the memory cells of the MH74S287, you can see that Tesla has always grouped four memory cells together. Otherwise, the structure is apparently the same.The present device is unprogrammed. You can see the bright fuse elements quite well.In the test column (far right) you can see how triggered fuse elements look like. The break forms a dark area in the center of the element.The datasheet shows the input and output circuitry of the MH74S287. Fast Schottky transistors are used there.The structure of the column decoder can be seen clearly. The interconnection with the address lines and their complementary lines ensures that each address activates exactly one column. The test column on the far right and the column next to it additionally receive the signals A4*, which are generated in the additional circuit of the address input A4. If the 32nd column is selected and input A4 is in overdrive, the additional circuit ensures that the 32rd column is deactiviated and the 33rd column is activated.To the right of the column selection is the decoder of the row selection (seen here at the lower edge). This works according to the same pattern and outputs nine control signals.Eight of the nine control signals pass under the continuing lines at each of the four memory blocks. Each memory block has eight larger transistors, one of which is active. A bus line then leads up from each block and to the four output drivers.If address input A2 is in overdrive, the control signal in the top block jumps to the single transistor at the top edge and the test line is connected to output driver Q1.Between the line decoder and the GND bondpad there is a small circuit connected to the two decoders. Presumably a bias generator or something like that.There is a programming instruction for the MH74S287. According to this, the module must first be supplied with its normal operating voltage. Then you set the address you want to write and apply the pattern to be programmed to the outputs. The outputs are either held at high potential by pull-up resistors or pulled hard to ground.The programming process is done with an increased voltage of 10V to 11V and is controlled by one of the enable inputs. Before raising the supply voltage, disable the outputs. If the correct voltage is applied, one activates the outputs for 1ms. Where a high current flows, the fuse elements are triggered. The high power dissipation that occurs during this process makes it necessary to define cooling times that depend on how long the increased voltage is applied to the device ("Y").On the die one has tried to make the way the high programming current has to flow as short and low impedance as possible. Ucc is fed directly to the transistors for the column selection. Depending on the state of the address lines, one of the columns becomes active and is supplied with Ucc. On the right side of the memory matrix, one of the rows is switched through in each of the four blocks. Depending on which outputs have a GND potential applied to them, a high current flows across them and the associated fuse elements are triggered.It is interesting that the output amplifiers seem to be bypassed during programming. From the line selected, a line leads directly to the bondpad via a larger structure. This also explains why a low at the output can be used to disconnect the fuse, but in normal operation a high is present at the output when the fuse is disconnected.https://www.richis-lab.de/ROM04.htm

author: Noopy
author_rank: Super Contributor
timestamp: March 29, 2023, 06:57:31 pm
content: The AS6C62256 is a 256kBit SRAM built by Alliance Memory. The American company Alliance Memory serves the market for so-called "legacy memory". These are memory chips that are no longer produced by the major manufacturers.The datasheet shows a block diagram of the AS6C62256 that does not contain any surprising things.The dimensions of the die are 2,9mm x 1,8mm. The image quality is not optimal, but the typical structure of a memory chip can be seen well.The details show that the design does not come from Alliance Memory, but was developed by the Taiwanese company Lyontek. The internal designation seems to be LT8012. The B is shown differently and could represent the revision.The design is from 2004. Above the year you can see some mask designations.https://www.richis-lab.de/RAM04.htm

author: Noopy
author_rank: Super Contributor
timestamp: April 20, 2023, 07:07:14 pm
content: A cleaned package, so what will we find inside...The dimensions of the die are only 0,92mm x 0,87mm.There are a few designations on the die, including the Microchip Technology logo. The strings cannot be recognized very well, but they do not seem to refer to a common product designation.Even though the structures are very small, some function blocks can be identified. The actual memory area (yellow) has the typical very small and very regular structures. To the left of the memory area is the row selection (purple) and below that the column selection (cyan). The column selection is clearly more complex. Presumably, in the left area actually only a row selection takes place, while below the memory area the signals of the memory cells are evaluated. Writing also requires somewhat more complex circuit parts, since it is done with increased voltages. The charge pump required for this is located at the top edge of the die (red). A clear indication of this are its relatively large capacitors. The remaining areas probably contain the necessary control logic.The column selection is connected to the memory area by 8*16 lines. In the row selection, one is able to recognize 32 elements. Here, however, it would be quite possible that each element outputs more than one control signal. The memory matrix therefore offers at least 4kBit, maybe more.The bondpads to supply the circuit can be identified by their more massive connection. This leaves three bondpads as data interface. This speaks for the fact that it is an I²C interface. For Microchip Technology, this is the 24xxyy family. The arrangement of power supply and data interface fits these devices.In the 24xxyy family there are memories with additional address inputs, but also variants that offer just one write protection pin in addition to the I²C interfaces SDA and SCL. This one here must be such a device. If it really is a 4kBit memory, then this would be the 24xx04. The two middle characters indicate variants that allow different write speeds. Microchip Technology offers memory depths between 128Bit and 2MBit.The datasheet of the 24AA04 contains a block diagram, which shows the typical circuit parts of an EEPROM. A control logic evaluates the bus signals SDA and SCL. Behind this is a control logic that evaluates the write protection input and controls all areas of the memory. Below this is the voltage generator which generates the increased programming voltage, the row selection and the column selection including signal conditioning. The page buffers allow up to 16B to be transferred before they are written to the EEPROM in one piece.https://www.richis-lab.de/ROM05.htm

author: Noopy
author_rank: Super Contributor
timestamp: June 02, 2023, 03:25:32 am
content: The T24C02A is an EEPROM with 256B of memory. The manufacturer is the Chinese company Shenzhen First-Rank Technology.In addition to the T24C02A, the T24CxxA product family offers five larger variants with up to 64kB. Voltages between 1,8V and 5,5V are permissible as supply. At 5V, the maximum clock frequency of the I2C is 1MHz.The datasheet contains a block diagram showing the usual structure of a serial EEPROM. The T24CxxA memory chips offer additional up to three pins for an address assignment. With the smallest version T24C02A, all three address inputs can be used. The memory then reacts to the address that is assigned to it via these pins, so that up to eight T24C02As can be addressed via one bus.In the variants with up to 16kB the bits of the external address assignment are partly needed to select one of the pages of the memory. In the two largest variants with 32kB and 64kB, the memory is already addressed via 16 bits and you can use all three address pins as with the T24C02A.The dimensions of the die are just 0,48mm x 0,42mm. The regular square area represents the memory area, with column and row selections extending upwards and to the right. The large number of squares to the left of the memory could contain the charge pump capacitors whose voltage is used to write into the memory cells.The bondpads of the supply voltage can be identified due to their massive connection to the frame structures. It is interesting that just three additional bondpads were contacted. This would be sufficient for the serial interface and the write protection. Presumably, the bondpads that are not contacted are the address inputs. In the T24C02A, these should actually be connected to the pins.https://www.richis-lab.de/ROM06.htm

author: Noopy
author_rank: Super Contributor
timestamp: January 13, 2024, 09:35:58 am
content: The 82S129 is a PROM with a memory volume of 1kBit. The memory cells are based on nickel-chromium elements which are burnt through during programming (see MH74S287:https://www.richis-lab.de/ROM04.htm). The address lines A3-A7 activate one row of a large 32x32 memory matrix. The address lines A0-A2 choose four signals from the 32 output signals of the matrix, which are then output depending on the control signals CE1 and CE2.The 82S129-PROM is no longer produced. However, there are still applications that use the component. One application is the Sennheiser SK 3063-U pocket transmitter, which is used in television productions, for example. Heart of the transmitter is the TDD1742 frequency synthesiser. An 82S129 PROM defines the frequencies on which the transmitter transmits. A channel selector switch operates four address lines of the PROM, the remaining three address lines are controlled by the synthesiser.Since the 82S129 PROM is no longer manufactured, Sennheiser now uses a special hybrid in this position. It was not possible to switch to a more modern memory. The pocket transmitters can be switched to other frequency ranges as part of customer service. To do this, the PROM is replaced and memory modules that are compatible with the existing interface are required.The hybrid module is based on a ceramic carrier, the design of which corresponds to a DIL-16 package. Two resistors and a transistor can be seen on the top. The actual memory is covered by a black encapsulation. There is no further information on this hybrid.If you remove the potting material, you can take a look at the memory used in the hybrid.This is obviously a much more modern circuit. The regular structure of the memory area is clearly recognisable. The extensive circuit around the memory area shows that it is most probably an EEPROM. Some capacitors are integrated at the left edge. There is certainly a charge pump there, which generates the higher voltage required to write into the memory cells.The die shows that the memory was designed by Atmel. The designation 19803 is an internal designation. It can be found in a PCN for the EEPROM AT28C64.The revisions of eight masks are shown in the lower section. The module uses two metal layers. The upper metal layer obviously cannot be structured as finely as the lower metal layer.The AT28C64 is an EEPROM with a memory capacity of 8kB. It is therefore 64 times the size of the 82S129. The datasheet contains a block diagram showing the typical structure of an EEPROM.The transistor is a BC850, an NPN transistor. The potentials are distributed on the ceramic carrier in two layers.The address lines A0-A7 of the ceramic carrier lead to the respective address lines of the EEPROM. The address lines A8-A12, which the EEPROM also provides, are connected to GND. The address range that could be reached via these adresses is not required. The outputs IO0-IO3 are connected with O1-O4. The outputs IO4-IO7 remain open. Consequently, only the first four bits of the data interface are accessible, but this is sufficient here.The CE pin of the EEPROM is connected directly to the ground potential. OE is linked to the CE2 potential of the 82S129. WE is connected to the CE1 potential via the transistor, which works as an inverter. In the transmitter circuit, CE1 and CE2 are permanently connected to GND. This could also have been integrated on the ceramic carrier. However, the OE and WE of the EEPROM are connected to the pins to allow the module to be programmed. To do this, a high potential must be applied to CE1 and CE2.https://www.richis-lab.de/ROM07.htm

author: Noopy
author_rank: Super Contributor
timestamp: March 07, 2024, 02:07:46 pm
content: The SEI0181 is a part that was used in arcade game machines made by Seibu. Seibu did not manufacture any semiconductors itself. It is either a free available part which name has been customized or an ASIC that was developed for Seibu. As will be shown, it is an SRAM. The numbers 9050 could be a date code. The component would therefore have been manufactured at the end of 1990.The die cannot be exposed without damage. The dimensions are 6,4mm x 6,0mm. The image is available in full resolution (63MB):https://www.richis-lab.de/images/RAM/05x02XL.jpgThere are some test structures on the die, but no direct reference to the manufacturer. The test structures in the lower left area of the image show how well the individual masks have been aligned with each other. The numbers 6091 could be an internal project designation. Below these numbers are mask revisions. Of the five Bs, the left-hand B represents the polysilicon layer. Next to it are two metal layers and two masks that generate the connections between the layers.The structures of the input and output circuits are visible in the frame structure. The interface types can be identified. Inputs are located on the left. Directly behind the bondpads, series resistors limit the input current and thus form part of the protective structures.There are some outputs on the upper edge. No series resistors have been integrated there. Firstly, the outputs are more robust and secondly, they would have a negative effect on the output level. The left output has only one interface, all other outputs are connected to the rest of the circuit with two lines. The structures under the supply frame are significantly larger for these outputs. They could be tristate outputs. However, it is more likely that these are interfaces that can be used as both outputs and inputs.The die contains four very similarly structured blocks, each consisting of two memory matrices. In the middle of the die is a logic strip, the exact function of which cannot be worked out easily.DRAM memory cells, such as those integrated in the Tesla MHB4164 (https://www.richis-lab.de/RAM02.htm), usually only consist of a transistor and a capacitor. They are correspondingly small, but must be recharged regularly so that they don´t lose their information. SRAM cells, on the other hand, retain their information for as long as the memory is supplied with voltage. However, depending on its structure, an SRAM cell typically requires four to six transistors per bit.From the structures of the memory cells and the control circuits, it can be concluded that each of the eight matrices contains 32x32 memory cells. The module therefore offers a total of 8kBit RAM.The die has 50 inputs. A simple SRAM requires far fewer inputs. This indicates that it is a dual-port SRAM. With a dual-port SRAM, two function blocks can access the memory at the same time.The Renesas 70V05 is an example of a dual-port SRAM. The block diagram in the datasheet shows the basic structure of such a device. In addition to two times 8 data pins, the 70V05 has two times 13 address bits and two times 9 control lines.With the SEI0181, it is noticeable that two times eight data lines are led out of the four blocks and routed to the control logic in the middle of the die. For an ordinary SRAM with an 8-bit wide data bus, the data lines would have been connected directly within these four blocks and selected appropriately. This is not possible with a dual-port SRAM, as one half of the block can be controlled via one interface, while the second interface accesses the second half at the same time.https://www.richis-lab.de/RAM05.htm

author: Noopy
author_rank: Super Contributor
timestamp: May 14, 2024, 07:56:39 pm
content: The КM537РУ1 (KM537RU1) is an SRAM with 1kBit of memory. In addition to the ceramic housing, a variant in a plastic housing was also available with the designation КP537РУ1 (KR537RU1).The manufacturer cannot be identified, which is often the case with semiconductors from the Soviet Union. Widespread types were usually produced by several manufacturers. The datecode shows that the component dates back to 1984.In addition to the КM537РУ1 (KM537RU1) and the КP537РУ1 (KR537RU1), the Russian datasheet also lists the К537РУ1 (K537RU1) and КИ537РУ1 (KI537RU1) variants. These are merely different pin arrangements. The symbol in the Russian datasheet (left) shows the pin assignment of types KM537RU1 and KR537RU1 in brackets. Next to it is the pin assignment of the K537RU1 and KI537RU1 variants.In the datasheet collection of the "Kombinat Mikroelektronik Erfurt", issue 1/86, there is a German datasheet for the KM537RU1 and the KR537RU1. A different pinning is shown there (right). The chip enable input and the read/write input are reversed. As will be shown later, the pinning in the Russian datasheet is incorrect.The table describing the states and behavior of the SRAM also contains an error in the Russian datasheet, but it is easy to spot. The collum CE, which activates the module, must contain a 0 in the first line. It is interesting to note that the memory outputs the inverted input signal while writing data.The datasheet contains a block diagram with no surprises.The dimensions of the die are 3,9mm x 3,0mm. According to the datasheet, 7.200 transistors are integrated. This image is available in higher resolution:https://www.richis-lab.de/images/RAM/06x04XL.jpg(45MB)There are no structures on the die that give an indication of the manufacturer.At the right edge there are a few auxiliary structures showing how well the masks are aligned with each other.At the top edge is a test structure that appears to contain three transistors.There are buffer stages located directly at the input bondpads (black). The buffer for the CE signal is relatively large because this signal is used in many places in the circuit. All buffer stages are activated with the CE signal. The DI signal is also controlled by the R/W signal (light blue). There is a driver at the output (white). Left of the driver is a flip-flop evaluating the differential signal output of the memory. Another part of the circuit links the output driver with the CE signal. This part of the circuit also appears to generate a certain delay so that the output only becomes active when a valid signal is present.Most of the area of the die is taken up by the memory area (green). The column selection is located at the bottom edge. This is where the address lines A0 to A4 are evaluated (yellow) and linked with the CE signal (brown). Finally, a driver activates the wordline. The line selection is located to the left of the memory area. The evaluation of address lines A5 to A9 defines which line is to be selected (yellow). This is followed by a circuit that forwards the input signal to the respective line or routes the signal present in the memory upwards (purple). There are pull-up structures between this circuit and the memory area (red).The input buffers for the address lines A0 to A4 (upper picture) are significantly larger than the buffers for the address lines A5 to A9 (lower picture). This can be explained by the fact that the column selection contains more gate area and therefore more power is required for charging the gates. The CE signal activates the buffers, which output the status of the address line differentially.At first glance, the memory area appears confusing, but you will eventually recognize the repeating structures of the individual memory cells.These are the familiar SRAM cells with six transistors. The wordline activates the transistors N3 and N4, whereupon the status of the transistors P1/N1/P2/N2 can be read or overwritten via the differential bitline.For the sake of simplicity, the MOSFET symbols commonly used in LTSpice were used here. In fact, the body potential is not hard-wired to the source potential, which is relevant for transistors N3 and N4.You always try to make the SRAM cells as small as possible. Since the area required by a cell is multiplied by the memory depth, every saving has a major effect. However, the structure of the cells is often no longer visible at first glance.Compared to the schematic, the circuit is rotated by 90°. GND lines run above and below the memory cell in the metal layer. The supply potential is transmitted to the right of the memory cell through the silicon. Between the GND lines, the metal layer carries the differential bitline across the memory area. The wordline potential runs in the polysilicon layer from the bottom to the top (yellow).The transistors N3 and N4, which activate all the memory cells in a column, are formed directly under the line that transmits the wordline potential. Inside the memory cell there are two polysilicon areas (green/cyan) which serve to distribute the potentials and represent the four transistors required for the memory cell (P1/P2/N1/N2).On one side of the large GND contacts, elongated stripes can be seen under the polysilicon. It appears that the active areas and thus the transistor properties have been modified. Particularly in the two memory cells on the left, similar stripes can be seen parallel to the supply potential. Without this control, transistor P1 would be much wider than transistor P2 and the circuit would be correspondingly asymmetrical.The five complementary signals of the address bus are evaluated in the lower area of the column selection (yellow). Under each column of the memory area there is a stack of smaller highside transistors and a stack of larger lowside transistors. Except for the transistors of address line A0, two neighboring columns always share the lowside transistors. The alternating contacting of the gate electrodes with the inverted or non-inverted potential of the address lines ensures that only one column is active at one time.The output signal of the address decoder is linked to the inverted CE potential (brown). It also passes through two inverters. The need for these two inverters is not immediately apparent. Perhaps they are used to adjust the timing of the signals. Finally, larger drivers (dark blue) apply the respective control signal to the associated wordline.The address decoder in the row selection is constructed in the same way as the address decoder in the column selection. Here, however, the lowside transistors are slightly smaller. This is followed by two inverters that provide a differential output signal (yellow).In the active row, four transistors become conductive (purple). These transistors switch the differential bitline signals to two collector lines which, depending on the R/W signal, carry the value from the memory to the output or supply the input signal. In relation to the potentials at the bondpads, the output signal is inverted compared to the input signal. This corresponds to the behavior of the module.A double transistor is integrated directly in front of the memory block, which apparently serves as a pull-up structure. The pull-up structure is only active when the CE signal is present.https://www.richis-lab.de/RAM06.htm

author: Noopy
author_rank: Super Contributor
timestamp: May 19, 2024, 02:56:38 am
content: The Texas Instruments TMS27C240 is an EPROM with a memory depth of 512kB. The suffix 12 stands for a maximum access time of 120ns. There were also two other bins with maximum access times of 100ns and 150ns.The block diagram in the datasheet shows the architecture of the memory. The TMS27C240 has 18 address inputs and a 16-bit wide data bus.The die is very large: 6,6mm x 6,4mm. The memory area is divided into several segments. This image is available in higher resolution:https://www.richis-lab.de/images/ROM/08x03XL.jpg(54MB)The internal designation appears to be T27C240A. The A could stand for a first revision. The design obviously dates back to 1992.Various masks are shown in the top left-hand corner of the screen.The memory cells themselves are too small to be resolved.https://www.richis-lab.de/ROM08.htm

author: RoGeorge
author_rank: Super Contributor
timestamp: May 19, 2024, 05:53:24 am
content: Quote from: Noopy on May 19, 2024, 02:56:38 amIf the cells are too small to be seen, then what is the chess-table like area, in the lower left corner? At first I thought each dot is a 1 bit cell. Isn't that so?

author: Noopy
author_rank: Super Contributor
timestamp: May 19, 2024, 06:19:14 am
content: There are the memory cells but I'm not sure whether each dot is a cell. Could be one or more dots building a cell....you could count all the dots...

author: RoGeorge
author_rank: Super Contributor
timestamp: May 19, 2024, 07:13:18 am
content: Yes, I wanted to ask about the size of the pics, to make an estimate.Now I've zoomed in, and noticed the vertical lines, visible in both the detailed picture, and in the full die pic.There are 32 white dots and 32 black between the vertical line and the border. And there are 8 bands like that per 1 square, 32 bands along the width of the whole chip.32 bands x 64 dots = 2048 dots on the entire width of the chip. The dots have the same density horisontal and vertical, and the total area is square, so 2048 * 2048 = 4Mbit total, if it were to be 1 bit per dot (either black or white dot).The EPROM specs are 512kB, which means ( 512 * 8 ) kbit = 4096 kbit = 4Mbit.It's one bit for each dot, so I guess each is probably a MOS transistor, is it?

author: Noopy
author_rank: Super Contributor
timestamp: May 19, 2024, 07:39:12 am
content: Well that makes sense!So one dot is probably one cell.

author: RoGeorge
author_rank: Super Contributor
timestamp: May 19, 2024, 11:37:11 am
content: If it is so, then yo got yourself a 4 Megapixel UV camera. Cool!Should also work as a 4MP X-ray camera.First, program all the EEPROM with zero's, then expose it to X-rays for a while, then read back the memory. X-rays energy is above the UV light, so the exposing time won't be that slow as when erasing the cells with UV. Too bad the EPROMs do not have some "service/debug" mode to allow analog reading of each cell instead of just 0/1. That would have turned any big enough EPROM into a high resolution X-ray film, but in silicon and reusable a few times.

author: Noopy
author_rank: Super Contributor
timestamp: May 19, 2024, 11:42:25 am
content: That's an interesting idea. Indeed, Black&White should work.But you will need some good quartz lenses.

author: Noopy
author_rank: Super Contributor
timestamp: July 15, 2024, 03:22:29 am
content: The FM28V100 is an FRAM with the same specifications as the FM24V10 (https://www.richis-lab.de/RAM01.htm). The only difference is the parallel interface of the FM28V100. It has 16 address inputs and an 8-bit wide data interface. The FM24V10, on the other hand, is available with an SPI or I2C interface.Apparently, the FM28V100 uses the same design as the FM24V10. This could already be surmised, as the die has many more bondpads than are used in the FM24V10.However, the design of the die is not completely identical. The FM28V100 has an additional metal layer, but this is only filled with a dummy structure.Dummy structures are usually added so that the layers can be processed as evenly as possible. If layers are very inhomogeneous, it can happen, for example, that a grinding process has not yet removed enough material at one point, while at another point it has already penetrated too deep into the structures. In this case, however, the top metal layer is not utilised at all. It was not present at all in FM24V10. It remains unclear what purpose the dummy structures fulfil.Apart from the dummy structure, there is no superficial difference between the FM28V100 and the FM24V10. However, there is a small update in the top right-hand corner. This shows the year 2016, while the FM24V10 shows the year 2008.https://www.richis-lab.de/ROM09.htm

author: Noopy
author_rank: Super Contributor
timestamp: August 02, 2024, 03:49:41 am
content: I have some more pictures showing details of the U2164!The 64kBit DRAM U2164 shown here was manufactured in March 1988 at the "Zentrum für Mikroelektronik Dresden". A lot of background information about the U2164 can be found in the documentation of the Tesla MHB4164, which also contains a U2164:https://www.richis-lab.de/RAM02.htmAs with the Tesla MHB4164, the dimensions of the die are 7,0mm x 3,4mm.This image is also available in a higher resolution:https://www.richis-lab.de/images/RAM/07x02XL.jpg(36MB)On the left edge is the designation and the number 5, which most likely refers to the revision of the design.The structures can be recognised a little better in this picture. Due to the high density, the area of the memory cells still remains unclear.The carrier on which the die is located is visible on the side of the package. The voltage generated by the integrated charge pump can be measured there. On another U2164 (date code March 1989) this voltage is -1,7V. The potential is applied to the substrate via the carrier and thus optimises the threshold of the integrated transistors.Each of the eight memory blocks in the U2164 has a reserve row and two reserve columns. This increases the yield considerably, as it is possible to switch to these reserve areas in the event of production errors in the memory. Switching takes place via an area on the right-hand edge of the die. There are 32 and 36 fuses located there. To trigger the fuses, the area is obviously supplied via three testpads.Large transistors can be seen above the fuses, which allow the trigger current to flow. The necessary fuses are apparently selected via the addressing interface. The area of the fuses looks a little unclean because the passivation layer has been omitted in this area. This is necessary so that triggering a fuse leads to a safe interruption of the connection. It also ensures that triggering does not cause major damage to the surrounding passivation layer.How the addresses are redirected to the reserve areas remains unclear. Usually the address decoding is changed for this purpose. Modifying the addressing does not allow completely arbitrary replacement of memory cells, but it is often sufficient to hide all defective cells.https://www.richis-lab.de/RAM07.htm

author: Noopy
author_rank: Super Contributor
timestamp: August 05, 2024, 02:49:06 pm
content: The U2164 shown here was manufactured in April 1987.The large die requires a lot of space in the DIL-16 package.On the die you can see some dirt and artefacts. This picture is also available in a higher resolution:https://www.richis-lab.de/images/RAM/08x02XL.jpg(48MB)The die is coated with a protective layer, which partly explains the dirt. Particles usually adhere very strongly to such protective layers. However, a not inconsiderable proportion of the contamination must have already been on the die before the package was opened.Coatings are not primarily used to protect memory modules from contamination, but rather to shield them from radioactive radiation. This means that alpha particles from the housing material cannot affect the memory cells.There is a dark spot on the upper edge of the die, under which one would suspect an electrical defect. However, it only appears to be soiling in the potting material.The die marking documents that this is the fourth revision of the U2164. The Tesla MHB4164 (April 1990) and the previously documented U2164 (March 1988) are labelled revision 5, which means that between April 1987 and March 1988 the revision was changed from revision 4 to revision 5.It can be seen that revision 5 of the U2164, measuring 7,1mm x 3,4mm, is significantly smaller than the revision 4 used here, which measures 8,2mm x 3,8mm. Such a significant reduction in surface area cannot be achieved with minor optimisations. All structures were apparently reduced in size for revision 5. However, the functional blocks appear to have the same electrical structure apart from minor details.The protective layer somewhat disturbs the view on the structures. However, the capacitors that store the data can now be recognised in the memory area.The details of the structures show that the memory is not built exactly as described in Radio Fernsehen Elektronik 08/1989. When analysing the U2164 in the Tesla MHB4164 (https://www.richis-lab.de/RAM02.htm), it had to be assumed that the documentation depicted reality exactly. The mode of operation is shown correctly, but the superimposition of the structures has been simplified. The very dense arrangement in the memory array means that the word lines are not only routed over the areas where they are building the selection transistors. They also lie on the areas that represent the capacities.At first glance, it appears that this additional overlay could have an undesirable effect on the memory cells. The image of the cross-section provides clarity. The storage capacities arise between the substrate and the first polysilicon layer, whereby the first polysilicon layer represents the reference potential. If there is a line in the second polysilicon layer above this first polysilicon layer, this has no relevant influence on the storage capacity.A major change has been made in the area of the charge pump, which sinks the substrate to a negative potential. The same circuit parts can be recognised, but in revision 5 (below) a lot has been omitted.Apparently, this area was not only used to generate the negative substrate voltage. In revision 5, a line leads to various elements in the left part of the die. In revision 4, the beginning of this line is present, but it leads to an open end.The circuit section for switching to reserve areas is constructed in the same way in revision 4 as in revision 5. The recesses in the passivation layer are even more clearly recognisable here. No fuse was triggered. The memory appears to have been faultless.This component is defective. Without adressing, it draws more than 100mA. An infrared camera with a macro lens makes it possible to identify the area with the greatest heat development. This is not necessarily the location of the fault. The heat development can be a subsequent reaction. However, such an image can help to identify faults.If the thermal image is superimposed, it becomes clear that the greatest heat development occurs in the area of the first bondpad. However, no obvious damage can be recognised in this area.Here you can see another U2164 in a ceramic case. It was produced at the same time as the upper U2164.The protective coating appears even more soiled here than in the first U2164. This picture is also available in a higher resolution:https://www.richis-lab.de/images/RAM/09x03XL.jpg(47MB)Here, too, a small area of the protective coating is very dark.This U2164 was obviously not perfect. Here you can see some triggered fuses.https://www.richis-lab.de/RAM08.htm

author: iMo
author_rank: Super Contributor
timestamp: August 05, 2024, 03:12:33 pm
content: Afaik those TESLA MHB4116, MHB4164 and later on MHB41256 (not sure the 256k one went into full production though) were produced in the famous spa townPiestany(Slovakia today) on a production equipment purchased and nmos/cmos technology licensed from Toshiba, 4um and perhaps 1um or 2um at the end of its existence (starting memory production from early 80ties till early 90ties)..

author: Noopy
author_rank: Super Contributor
timestamp: August 05, 2024, 03:56:06 pm
content: It seems that at least for some time the MHB4164 was a U2164 and was packaged in Erfurt.The geometries are typical for Erfurt.https://www.richis-lab.de/RAM02.htm

author: iMo
author_rank: Super Contributor
timestamp: August 05, 2024, 04:04:12 pm
content: Yep, it is possible, in the time of east european Comecon they were packaging chips cross border happily. Sometimes the chips from the west as well..

author: Noopy
author_rank: Super Contributor
timestamp: August 05, 2024, 04:11:19 pm
content: Well cooperation makes sense. Other projects were less reasonable:The DDR and the SU both independently made a copy of the MicroVAX II CPU.

author: iMo
author_rank: Super Contributor
timestamp: August 05, 2024, 05:05:22 pm
content: Btw. - a less known company Everspin sent me some 10+y back a 4Mbit MRAM sample (I think the MR20H40, but I cannot find it in my junk box anymore). Would be interesting to see that chip too - as that technology is quite mysterious..

author: Noopy
author_rank: Super Contributor
timestamp: August 05, 2024, 07:21:57 pm
content: I have heard of these MRAM devices. Unfortunately I´m pretty sure you can´t see very much in a 4Mbit device. But if you want me to take a closer look...

author: Noopy
author_rank: Super Contributor
timestamp: August 08, 2024, 04:03:42 am
content: A small update for the U2164: Here you can see the dummy cells that are used to read the memory cells.https://www.richis-lab.de/RAM07.htm#Dummy

author: Noopy
author_rank: Super Contributor
timestamp: August 11, 2024, 04:48:03 am
content: The 256kBit DRAM U61256 was developed at the Zentrum für Mikroelektronik in Dresden. It was the largest mass-produced RAM in the GDR. The subsequent 1MBit memory U61000 was only produced in a small series. The characters XN indicate production in November 1989.The numbers 10 stand for the first selection type, which allowed access times of 100ns. This was followed by selection type 08, which was specified with 80ns. The basic type (12) offers access times of 120ns, the slowest bin (15) has an access time of 150ns.The datasheet shows the structure and function of the U61256. 8 bits of the 9-bit wide addressing interface are first decoded for row selection and then for column selection. The memory consists of two 128kBit areas which output the information of four cells simultaneously when reading data. The ninth bit of the addressing interface, which is also evaluated twice, controls the selection of one of these four cells. The data output in the top right-hand corner is missing in the block diagram.The size of the die is 9,6mm x 3,8mm. Each supply potentials is routed to the die with two bondwires.The image of this is also available in a higher resolution:https://www.richis-lab.de/images/RAM/10x03XL.jpg(67MB)Here you can see another U61256. The bin marking is missing on this component. XO indicates production in October 1989.The image of this part is also available in a higher resolution:https://www.richis-lab.de/images/RAM/11x03XL.jpg(71MB)The third U61256 appears to come from the same batch as the second.The image of this part is also available in a higher resolution:https://www.richis-lab.de/images/RAM/12x03XL.jpg(71MB)All three dies are labelled U61256-1. The number 1 probably indicates the first revision of the design. Fittingly, I can´t see a difference in the three parts.The left-hand edge appears to have had some imperfections during production. The third part shows soiling or signs of corrosion that extend to the first active structures.On the upper edge you can see some masks.The metal layer appears to have penetrated from the contacts into the polysilicon layer in many areas. The effect can be found in all three parts. The section shown here is from the third part.The memory cells are too small and there are too many layers on top of each other to be able to clearly recognise the structure. The surface structure of the metal layer appears to show capacitor geometries similar to those in the U2164.As in the U2164, line selection in the U61256 also takes place laterally and data evaluation is placed at the lower or upper edge of the storage areas. In contrast to the U2164, however, the lines in the metal layer run horizontally rather than vertically.The memory area only has line drivers on the right-hand side. Correspondingly large driver transistors are integrated there in order to be able to represent the necessary charging current. This could also be an explanation for the horizontal lines in the metal layer. The metal layer has a lower impedance than the polysilicon layer.In the block diagram, the memory area is divided into two parts. The upper and lower blocks each consist of two areas. Each of these areas contains 15 segments, from each of which 64 lines lead out of the area. There are 32 lines at the beginning and 32 at the end. This results in a total of 256.000 memory cells. There are 16 additional columns on the right-hand edge. Apparently, the memory has 16 reserve columns, i.e. 8.192 additional memory cells, to compensate for production errors.Here you can see the structures that run through the two large storage areas. The supply lines are relatively massive. Perhaps they are used to preload the columns before the memory cells are read.Even if the exact structures of the column selection cannot be recognised, some functions can be surmised. Two times eight lines run horizontally between the two large memory blocks. These are most probably the address lines for the two memory blocks. Four lines run somewhat shielded from this in the centre, which then certainly transmit the four memory contents readout.The fact that the 16 columns on the right are the reserve columns can also be seen here (red arrows). The first four blocks, which read out four columns each, are constructed and contacted differently. Five additional control lines are routed to this area.The circuit that enables the reserve columns to be looped into the address range is integrated on the right-hand edge. There are two times 36 fuses near the edge of the die for this purpose. The triggering is apparently similar to that of the U2164. Two testpads are integrated, one of which transmits the triggering current.The triggered fuses can be easily recognised. The fuses are thin polysilicon strips. Some fuses were triggered in all three parts. Apparently there were defective cells in all three parts.The bias voltage generation is located in the top right-hand corner of the die, which places the substrate at a negative potential. In the upper area, the circuit contacts the frame structure. This potential is also used in some parts of the circuit.In addition to the two testpads for triggering the fuses, there are two further testpads on the die. It is interesting to note that the surface of these testpads has a different structure. It could be that two types of testpads were used depending on the application. The testpads of the fuses are always contacted during production. The bias voltage probably only rarely needs to be measured. This testpad is also significantly smaller. The function of the fourth testpad remains unclear. Although its surface is structured in the same way as the bias voltage generation testpad, it was contacted for all three components.Here you can see an input protection circuit. It probably works in a similar way to the input protection circuit in the U2164. The two long, green elements are resistors for current limitation. In the upper area, two elements are surrounded by strips that are connected to the ground potential. The first element is probably a diode. The second element is a grounded gate NMOS.The push-pull output stage of the data output is very easy to recognise.https://www.richis-lab.de/RAM09.htm

author: iMo
author_rank: Super Contributor
timestamp: August 11, 2024, 07:35:53 am
content: QuoteI wonder what was the typical yield at that time in the Dresden fab?PS: @Noopy: a high time to acquire an electron beam microscope (as a minimum)TSMC starts construction on its first European chip plant in Dresden, Germany, marking a $10 billion investment to boost the semiconductor industry.Quotehttps://manufacturing-today.com/news/tsmc-commences-10-billion-semiconductor-plant-project-in-germany/

author: Noopy
author_rank: Super Contributor
timestamp: August 11, 2024, 08:01:05 am
content: Quote from: iMo on August 11, 2024, 07:35:53 amYou don´t find very much information about the U61256. The situation is much better for the U2164 and the U61000.The U2164 yield was increased starting from 6% in 1987 to 50% in 1988. It is said that there was a cooparation with Toshiba which helped a lot. (KampfauftragMikrochip, Olaf Klenke)It seems >10% was considered as not bad.Quote from: iMo on August 11, 2024, 07:35:53 amI don´t want to own one myself I just would love to have unlimited access to one.

author: magic
author_rank: Super Contributor
timestamp: August 11, 2024, 09:28:02 am
content: You can still go further with optical, I think 1980s technology should be within reach.In order to at least pretend that I'm staying on topic, below is a memory array (probably SRAM because there was another, larger one which would be the program memory) of an unknown low cost MCU fromtenx technologywhich I extracted from a bicycle speed meter made in mid 2000s. I included bond pads for size reference, these are almost always 100×100 micron on all chips. Image scale is 200nm/px, determined by dividing measured overall die size by pixel count.This image was assembled from many smaller frames and not all of them were in perfect focus, but you can see that pretty fine details are resolvable with an ordinary 40x0.65 objective. DoF becomes a serious pain, though, and focusing on the low layers tends to blur the upper metal somewhat. You could still get twice the resolution by employing oil immersion, but there is no way the results would be usable without focus stacking.

author: Noopy
author_rank: Super Contributor
timestamp: August 11, 2024, 10:44:21 am
content: A lot is possible with the right equipment and some automation. It helps a lot if you have some knowledge in optics and programming. This french guy here produces some really nice pictures including "interactive" focus stacking:https://ic.onidev.fr/en/die/multifocus_panoramas.html

author: Noopy
author_rank: Super Contributor
timestamp: August 20, 2024, 03:39:29 am
content: The NMC27C64 is a UV-EPROM built by National Semiconductor. The device offers a memory depth of 8kB.The block diagram in the datasheet shows the structure of the EPROM.The dimensions of the die are 2,9mm x 3,2mm. The individual function blocks are easy to recognise. The output stages of the data interface are located on the right-hand edge. The address signals are analysed between the other bondpads. The memory area has 256 columns and 256 rows. The column is selected at the bottom edge. The eight addressed memory cells are selected and analysed at the right-hand edge of the memory. The memory cells are also written to via the circuit on the right-hand edge.This image is also available in a higher resolution:https://www.richis-lab.de/images/ROM/10x03XL.jpg(36MB)The top edge shows that the design dates back to 1985.The E after the designation could stand for a fifth revision of the design. National Semiconductor often used letters at the end of the type designation as revision counters.The second line shows the revisions of the masks used. The revisions of the masks are usually reset when the complete design is upgraded to a new revision. Seven masks appear to have been used. The datasheet states that the process provides two polysilicon layers. This matches the visual appearance of the structures on the die.In addition to the National Semiconductor logo, some structures show the optical performance of the process. The small squares could be etch markers that allow the progress of the individual processes to be assessed during manufacture.The lines leading into the memory area can just be recognised. The structures of the memory cells themselves are concealed by the metal layer.https://www.richis-lab.de/ROM10.htm

author: Noopy
author_rank: Super Contributor
timestamp: September 20, 2024, 03:02:32 am
content: The U61000 is a 1MBit DRAM developed at the Zentrum für Mikroelektronik Dresden. It was never transferred to mass production. The so-called megabit chip has achieved a certain fame as it was one of the last prestige projects of the GDR semiconductor industry. Much of the following information comes from people who were involved in the development of the chip, including the project manager Prof. Dr. Bernd Junghans, the chief developer Dr. Jens Knobloch, the head of technology development Dr. Michael Raab, the director of research and development Prof. Dr. Dieter Landgraf-Dietz, the division manager Jörg Ludewig and Dr. Hans Becker, who did his doctorate in the field of the U61000.The unusually large lid of the package is immediately noticeable. It covers almost the entire surface. The characters A2 show that the part was produced in February 1990. The 12 on the left-hand side indicates the slowest bin with an access time of 120ns. According to the datasheet, one faster bin was planned.This diagram was taken from the study "Der Osten Deutschlands - ein Standort europäischer Elektronik-Industrie" written by Prof. Dr. Wolfgang Marschall. It shows the technological backwardness of the GDR semiconductor industry in an international comparison.The table above, taken from the article "Die “technologische Lücke” - zum Rückstand der mikroelektronischen Industrie der DDR" published in 1998 in issue 25 of "Dresdener Beiträge zur Geschichte der Technikwissenschaften", is even clearer. According to the article, series production of the one-megabit chip in the GDR did not begin until five years after the international market launch. In addition to the technological backlog, the high development costs and the comparatively low quantities also meant that electronic components from own development and production were very expensive. Nevertheless, their own developments were necessary and sensible for the GDR, as integrated circuits were often on embargo lists and valuable foreign currency had to be sacrificed. At the same time, many different ICs were urgently needed for consumer goods, industry and, of course, the military.If new processes are developed in the semiconductor industry that enable smaller structure widths, they are usually used to produce memory first. Memory has relatively simple, constantly repeating structures. It was therefore only logical for the GDR to further develop their memory technology. The process used in the U61000 is called CSGT5d: Complementary Silicon Gate Technology, technology level 5. The letter d probably indicates a variant of this process. In the publication "Looking back: Artwork and Mask Making in Dresden for the East German Megabit Chip Project" by Hans W. Becker, it is stated that "about 16" masks were used. Michael Raab, Head of Technology Development, also spoke of 16 masks (and 6 implantation steps) at the 19th Leibniz Conference in his lecture "Technologie der Mikroelektronik der Schlüssel für die digitale Revolution". In 1989, the journal "Mikroprozessortechnik" published a large article by Dr. Jens Knobloch with a little more detail. According to this article, three polysilicon layers and one metal layer were used to connect the 2,3 million components. A total of 430 sub-steps were necessary to produce the U61000. This article mentions 18 photolithographic structuring steps.Of course, third-party samples were also analysed for the development of the U61000. The TC511000 from Toshiba was particularly important in this context. Siemens produced similar chips and had acquired a licence for them from Toshiba. The GDR's foreign intelligence service had even obtained documents on this megabit chip. However, it was not possible to build the U61000 on this basis, as it was necessary to work with the technologies and materials that were available. The basic architecture and functional blocks may have been inspired, but it was not possible to simply copy the Western product.The Soviet Union was able to produce 256kBit memory before the GDR. However, when the GDR was able to hand over a 1MBit memory to the Soviet Union, unique parts of its own megabit memories were only available there. Moreover, these were not yet based on the more modern CMOS technology. However, the GDR used some specialised technical equipment from Western production, while the Soviet Union relied solely on its own production facilities (Source: Wafer stepper and megabit chip by Otto Bernd Kirchner).According to Wikipedia, the U61000 was planned for use in the Robotron computers K1820, K1840 and EC1835, among others. Here you can see the K1822 workstation. This is a replica of the MicroVAX II from DEC. The corresponding MSC20 memory module is shown on the right. With 72 U61000, the plug-in card offers 8MB of memory.The table above shows the different revisions of the U61000, some core specifications and who published the information. Before the better-known versions, there was the U61000T, which was later renamed U61000-0. This was the first draft of the megabit memory, which was finalised in December 1987. The first chips were available in April 1988, although they still contained bit errors.With the knowledge gained from the U61000-0, the design of the U61000-1 was finalised in May 1988. This made it possible to produce the first bit-error-free chips in August 1988. In September 1988, the first samples of the megabit chip were presented to the public. The sub-variants U61000-1.1 and U61000-1.2 were then produced from this variant. Pilot production of the U61000-1.1 began in March 1989 and the U61000-1.2 was produced from September 1989 to March 1990. A total of 6.700 components were produced.The dimensions of the U61000-1 were 12,8mm x 5,1mm. For use in expoxy packages, it was necessary to make the die a little smaller. For this reason, the design of the U61000-2 version was finalised in January 1989. Dimensions between 12,5mm x 4,4mm and 12,6mm x 4,5mm are specified for this and the two sub-variants 2.1 and 2.2. It was particularly important to reduce the width. Previous tests had shown that the dimensions of the storage capacitors could be reduced from 3,89µm x 9,00µm to 3,24µm x 9,00µm. This was certainly very helpful in this context.Dr. Hans Becker states a yield of 10% and 20% respectively for the last two versions 2.1 and 2.2. According to various sources, the total number of U61000s produced must have been around 30.000.The 19th Leibniz Conference included the presentation "Entwicklung des Megabitspeichers U61000 1986 bis 1990" by Dr. Jens Knobloch. It contains the table above, which shows the characteristic values of the pilot production. The targeted specifications were achieved and in some cases significantly exceeded. The yield was 9,5% and the necessary reliability was also demonstrated.Inside the package, you can see how borderline large the die of the U61000 is. It is also noticeable that there is no thick protective layer on the silicon, as can be found on the U2164 (https://www.richis-lab.de/RAM08.htm), for example. Such layers are often used in memories to shield alpha radiation. The package materials are never completely free of radioactive elements, whose radiation can lead to bit flipping. A certain degree of robustness against ionising radiation is achieved through the structure and arrangement of the storage cells. Dr. Jens Knobloch also describes in the article "Der Megabitspeicher U61000" in the journal Mikroprozessortechnik (issue 10, 1989) that potential barriers were incorporated into the U61000 under the memory capacitors and under the bit lines to reduce the effects of ionising radiation.The lecture "Speicherchip-Packaging - die Technologielokomotive für das Back-end" by Jörg Ludewig is also part of the 19th Leibniz Conference. It includes a technical drawing of the package. The package had to be imported and was correspondingly expensive. A changeover to an epoxy package had to be made as quickly as possible.The labelling shows that the potential Ubb is contacted at both edges. Ubb is the substrate potential that is not routed to the outside, but is only connected to the metal surface on which the die is located.The dimensions of the die are 12,8mm x 5,1mm. This corresponds to the dimensions found in the literature for the U61000-1.The image of the die is also available in a higher resolution:https://www.richis-lab.de/images/RAM/13x04XL.jpg(28MB)A stylised frog is depicted next to the designation U61000. The chief developer Dr. Jens Knobloch immortalised himself on his designs with this symbol.The U61000 datasheet shows the memory interfaces. The ten address lines are used to first select the row and then the column of the memory.The above block diagram can be found in the aforementioned article "Der Megabitspeicher U61000". Four 256kB blocks form the core of the memory. Each block has 512 lines. The line decoders each activate one line. Four times 512 sensor amplifiers analyse the four times 512 columns and then write the data back again. The column decoder selects one cell from each block. One of the four cells is then analysed for the output. As will be shown later, this representation does not quite correspond to reality.For addressing, the ten address bits are stored once in the row address buffer and once in the column address buffer. The U61000 also contains a refresh control with an address counter. This function block makes it easier to update all data in the memory fast enough.The potentials of the pins are easily found on the die (cyan). As can be seen in the drawing of the package, there is a bondpad on the left and one on the right that carry the substrate potential (orange). There are two unused bondpads on the upper edge. Another unused bondpad is located at the bottom edge (white). The signals of all three bondpads end in stubs. However, the structures contain provisions to connect the bondpads with the address potentials A0, A8 and A9. This was presumably intended to keep the option of using other package types with differently positioned contact surfaces.The input protection circuit appears almost like a work of art. To a large extent, it corresponds to the protection circuit described in more detail in the U2164 (https://www.richis-lab.de/RAM02.htm). Here, an additional transistor has been integrated close to the bondpad, which uses a metal strip as a gate electrode. This transistor only becomes conductive at exceptionally high voltages and then creates a low-resistance connection to the reference potential.The die has a large number of testpads. These include 27 large testpads (red), which could also be contacted automatically. 82 significantly smaller testpads (yellow) allow internal signals to be contacted for more in-depth tests without having to modify the structures of the chip.The large testpads often contact test structures, but not exclusively. The small testpads are mainly used as taps for internal signals.The structure widths and the many layers make it difficult to analyse the circuit components precisely. However, the recognisable structures and the connections make it possible to understand how the circuit works in many places.The large structures of the charge pump, which ensures a negative substrate potential, can be found in the upper right-hand area of the die. One might think that the upper area represents the associated clock generator. However, the clock generator actually appears to be located in the lower area of the die. This leaves open what function the upper circuit fulfils. Perhaps it is an adjustment/modification of the clock signal.Here you can see the circuit at the bottom right of the die, which most likely contains the clock generator. The larger, upper part of the image contains large structures that could represent the resistors and capacitors required for a clock generator. The small, repeating structures could be the associated transistors. At the upper end of the image, four wider lines lead to the right, which appear to be clock lines.The clock lines lead to the charge pump, among other things. However, the U61000 also requires a clock signal in other areas. Obviously, this is the address counter for regularly updating the data. However, the clock is also routed to the memory blocks. For this purpose, there is a circuit in each of the two right-hand corners of the die that looks like a driver. Here you can see one of the two circuits at the bottom of the picture.The structure of the storage area cannot be recognised. The structures would still be large enough to resolve them optically. However, the many layers, which carry many lines in this area, create an unevenness in the surface that makes the image very confusing.The word line (line selection, vertical) was mapped in the aluminium layer. The relatively low-resistance metal allows for long cables. The bit lines (column selection, horizontal) could be made shorter as a result. This is advantageous as it results in lower parasitic capacitances, which makes it easier to analyse the voltages, which are only slightly above 100 mV.The image above is from the article "Der Megabitspeicher U61000" by Dr. Jens Knobloch. The four wiring layers ensure that the top view remains unclear even in the stylised representation. The cross-section is somewhat easier to understand. The first and lowest polysilicon layer forms the storage capacities with the n-doped areas in the substrate. The potentials of the word lines, which are distributed via the metal layer, reach the gate electrodes of the selection transistors via contact windows, which cannot be seen in the cross-section. The gate electrodes are structured with the second polysilicon layer. This is surprising at first glance. Normally, the highest demands are placed on the gate oxide of the transistors. One would therefore expect the gate electrodes to be manufactured first. In a DRAM, however, the storage capacity is more critical, which was probably the reason for producing it with the first polysilicon layer. The bit lines are located in the third, top polysilicon layer. As with the U2164, it contacts a point between two memory cells (https://www.richis-lab.de/RAM02.htm).Prof. Dr. Bernd Junghans and Dr. Michael Raab published the article "CSGT5 - eine moderne Basistechnologie fuer Hoechstintegration" in the magazine Jenaer Rundschau in 1989. It contains the stylised structure above and the SEM image of a polished section below. You can immediately recognise the irregular surface, which makes it difficult to resolve the structures optically.The top image in particular shows more clearly where which areas are located and how they are structured. The substrate is coloured dark green at the bottom. The orange layer contains the doping, which results in conductive structures in the substrate and between which MOS transistors are created with a gate electrode. The black shaded material is the silicon oxide that serves to insulate the conductive areas. The first polysilicon layer is shown in dark brown. As described above, it represents the storage capacity. The second polysilicon layer in dark blue on the right is the gate electrode of the selection transistor. The left-hand strip has no function in this image. It merely leads to the next, shifted memory cell and forms the gate electrode of the selection transistor there. The third polysilicon layer is shown here in more detail. The image description explains that it is molybdenum silicide, which is located on a polysilicon base. The metal layer is coloured yellow.As the structure widths are reduced, the resistances of the conductor paths and contacts between the layers become increasingly critical. For this reason, western megabit memories use titanium. Titanium reacts with silicon to form titanium silicide, which offers significantly reduced resistance. The GDR did not have titanium with a sufficiently high purity (99,9999%). It would have taken at least 5 years to produce such pure titanium. As an alternative, high-purity molybdenum could be used, which is also well suited to reducing the resistance of silicon. However, the structures produced with this material behaved differently. This was one reason why the known structures of western megabit memories could not simply be adopted.The picture above is from the lecture "Entwicklung des Megabitspeichers U61000 1986 bis 1990" by Dr. Jens Knobloch. It shows the result of an element analysis on a section of the U61000. The substrate and the polysilicon lines consist mainly of silicon, which is shown in blue. The insulating silicon oxide is shown in red. The metal lines are green. The yellow-coloured molybdenum is clearly visible in the horizontal bit line.There is another very interesting article in the Jenaer Rundschau from 1989: "Entwurf des Megabitspeichers" by Dr. Jens Knobloch, Prof. Dr. Wolf-Joachim Fischer, Stephan Dobritz and Andreas Scade. It documents, among other things, the reduction of structure sizes in the area of DRAMs with the image above. For the publication on this page, only the arrangement of the components has been slightly modified and the designations added. In some cases, only the functional areas of a structure have been coloured. This must be taken into account in order to understand the illustrations. The red areas represent the memory capacities. The selection transistor is located in the area coloured blue. Contact windows are coloured green. The metal layer is grey. A slightly darker blue colour has been chosen for the trench structure of the 4MBit DRAM.The U256, a 16kBit DRAM, has a completely different structure to all subsequent memory technologies. The structure of the memory cells in the 64kBit DRAM U2164 has already been documented in detail (https://www.richis-lab.de/RAM02.htm). The coloured illustration of the U61000 cell is easy to understand with the above basics. For the U61256 (https://www.richis-lab.de/RAM09.htm), the illustration does not appear to be quite correct. According to this, the bit and word lines would be shown in the metal layer and would cross each other. However, as the U61256 only has one metal layer, this is not possible. Judging by the pictures of the U61256, the bit line is in the polysilicon layer. This would also fit in with the fact that the U61256 is often mentioned as an important step towards the U61000. The selection transistor of the U61256 is also shown too large.The U61000 was to be the last DRAM with flat memory capacitors. The 4 MBit DRAMs already available internationally had already been converted to three-dimensional capacitors. A constant reduction in the size of the memory cells reduces the memory capacities in the first instance. This can be counteracted to a certain extent by increasing the capacitance density. For example, the dielectric in the U61000 is just 10nm thick. Nevertheless, the development is problematic. The leakage current does not decrease in the same proportion as the capacitance, so that the holding time of the information is continually reduced. The parasitic capacities in the evaluation path also become increasingly critical with smaller memory capacities. The memory capacity of the U2164 is still 50fF. No information can be found for the U61000, but for the 4MBit memory the aim was to achieve 40fF. As can be seen above, a trench capacitance was planned for this, i.e. a depression that increases the capacitance of the capacitor surface.The diagram shown here is also taken from the article: "Entwurf des Megabitspeichers". There you can see how the area of a memory cell has been reduced over the generations. The two revisions of the 64kBit DRAM U2164 have already been documented (https://www.richis-lab.de/RAM08.htm). As already described, it was possible to significantly reduce the memory cell area in the U61000 from version 1 to version 2. The 4MBit memory should again result in a very significant reduction in area requirements.[...]

author: Noopy
author_rank: Super Contributor
timestamp: September 20, 2024, 03:03:51 am
content: As shown in the block diagram, the memory is divided into four 256kbit blocks. The division is not self-evident and cannot be chosen arbitrarily. You have to find an architecture that makes as much sense as possible under the many physical conditions.The four 256kB blocks are each divided into two halves of 128kB. It seems to make the most sense to continue to display the die in the orientation shown here. However, you have to accept that the rows will be vertical and the columns horizontal. You can recognise 256(+2) rows and 1024(+4) columns. As with the U2164, the memory cells are offset from each other, so that there are effectively 512(+2) columns.In addition to the 1MBit memory cells, the U61000 also has 1,2% reserve cells. Each half of the 256kB blocks has two additional rows and two additional columns. If faulty cells occur, their addresses can be redirected to the reserve cells within certain limits.The line selection takes place in two stages. Six differential signal lines run along the lower edges of all four memory blocks (cyan). The signal lines are controlled by the line address registers of the address lines A2 to A7. In addition, the address lines A0 and A1 are analysed by small circuit blocks that generate four additional local control signals for each memory block (red). A value in the address space A0-A7 thus activates one of the 256 lines in each half of the memory block. The value of address line A8 also defines whether the 256kB memory block is active or not.You can see the different contacting of the address lines in the lower area. As you would expect, the line drivers in the upper area are relatively large.This shows more clearly that only two of the four memory blocks are active at any one time, depending on the status of address line A8. When looking at the block diagram, you might think that all four memory blocks always output a signal.The four halves of the two active memory blocks each output the status of 512 memory cells. The parallel evaluation of all memory cells takes place in the centre of the memory blocks. From there, the 2048 binary information read out destructively must then be written back into the lines.Column selection takes place between the memory blocks. The associated addressing is controlled by circuit sections above the memory blocks. There, the address lines A1 to A8 are analysed and fed differentially to the column selection (cyan). It is noticeable that the driver stages of six address lines have the same structure, while the other three driver stages are visually somewhat out of line. The drivers probably control different selection mechanisms. Due to the preselection via addresses A1 to A8, each half of the memory block supplies the states of two memory cells. Based on the address line A0, a further selection is made so that each memory block ultimately outputs two data signals (red). Writing takes place via the same path.Both in the row selection at the lower edge of the die and in the column selection at the upper edge, circuit parts are integrated that are only connected to the address line A8 (yellow). In both cases, this is the signal A8 of the row selection. Lines lead from these circuit components to the outer edges of the memory blocks. Obviously, the memory blocks are also kept inactive at these points if they do not belong to the two memory blocks that are to be read or written. The address line A9 is also read in at the upper edge. It appears to have an influence on the entire column selection.The circuit for selecting columns and for data processing is rather confusing. However, you can guess the addressing in the centre. The paired evaluation of the columns becomes clear towards the memory areas.Each of the four 256kB memory blocks ultimately supplies two values. The outputs of two neighbouring memory blocks are combined. This is possible because only two memory blocks are ever active, controlled via address line A8. In the top left-hand corner of the die is the circuit section that finally selects one of the four data lines. It is controlled via the two values that are written to the column and row selection registers using address line A9.The registers for column selection are integrated at the top edge of the die (yellow). The registers for row selection is mostly located on the right edge of the die (blue). The tabs for A0 and A9 can be found in the bottom left-hand corner. The counter function, which is used to refresh the memory cells, is integrated into the line selection register.Classic fuses were still used for the 256kBit memory U61256 (https://www.richis-lab.de/RAM09.htm). The thin polysilicon lines were cut with a relatively high current. However, such fuses and the associated trigger circuit take up a lot of area. With a 1 MBit chip, more configuration options are required in order to achieve a sufficient yield. This can no longer be sensibly realised with classic fuses. Toshiba used a laser to cut the fuses of its megabit memories during the wafer test. No suitable laser was available in the GDR. Carl Zeiss Jena did not want to develop such a laser, as only very small quantities would have been required.Consequently, an alternative to the configuration of the U61000 had to be found. In the end, it was decided to subject the circuit to another etching process after the wafer test. Customised processing was achieved using electron beam lithography. A photoresist was applied and selectively exposed with an electron beam. The subsequent etching process then only removed the previously selected fuses. The image above is from the lecture "Entwicklung des Megabitspeichers U61000 1986 bis 1990" by Dr. Jens Knobloch. It shows what a fuse strip configured in this way looked like.There are four fuse strips at the bottom and top edge of the die. Each memory block is assigned one strip on the top edge and one strip on the bottom edge. The upper strip enables the configuration of the reserve columns. The lower strip configures the reserve rows.Dr. Jens Knobloch reports that without the reserve cells, a yield of 3% could be achieved at the turn of the year 1989 / 1990. Utilising the redundancy increased the value to 10%. The U61000 documented here appears to be one of the very good memories, as none of the fuses was interrupted.The fuse strips of the line selection are located in pairs where two memory blocks meet. They are connected to the differential control signals A2-A7 of the line selection.The differential control signals of the address line A1 are also fed to the fuse strips from the lower area. The fuse elements are surrounded by several frames that carry different potentials. The substrate potential Ubb is located directly next to the fuse elements. This is followed by the positive supply potential Ucc. Below the Ucc frame is a control line and finally the Uss potential. When the passivation layer is opened, there is a risk of contamination being introduced into the system. It could be that the frames with their electrical fields are intended to prevent these contaminants from travelling.The differential control lines arriving from above are connected to transistors under the outermost, wide Uss frame. If a signal is present there, a common control line (blue) is connected to the Uss potential. As these are differential signals, the control line in this configuration is always connected to the Uss potential. If fuses are disconnected, it is possible to ensure that the control line remains open at certain addresses. The circuit to the left of the fuse strip evaluates the potential of the control line.While the fuse strip evaluates the signals from address lines A1 to A7, the following circuit (orange) is also controlled via address line A8. This means that the reserve lines are only active when the associated memory block is active. Finally, a control signal is generated that activates the two reserve lines (yellow). Another control signal activates a circuit that evaluates address line A0 (red). This switches between the two reserve lines. At the same time, the A0 evaluation of the normal line selection is deactivated (white). This ensures that the normal line selection remains deactivated for the addresses at which the reserve lines become active.The different circuits for row selection are clearly visible in detail. The two control lines that are generated from the address line A0 lead directly from bottom to top. The control line for activating the reserve rows leads over the left side to the top area of the row selection.The control line for activating the reserve rows also leads to the left area of the memory block. This means that the reserve rows in both halves of the memory block are always pushed the same distance into the usable address area. At the same time, switching the row pairs via the address line A0 ensures that the pairs can only be moved together. Both of these severely limit the possible applications of the reserve rows. However, more variable control would require a much more complex selection and control. A compromise had to be found here.At the top edge, the differential signals of the address lines A1 to A8 are used to shift the reserve columns. While the reserve lines in the memory halves only had to be configured within 128 addresses, 256 addresses had to be used for column selection. This is why the address line A8 is also located under the fuse elements. Otherwise, the circuit works in a similar way to the circuit for assigning the reserve lines.The reserve columns are located at the upper edge of the memory area. You can just about see the different controls via the thin line leading upwards under the metal layer.In the top left corner of the die there are several circuit parts, which can be seen as groups of four identical blocks. This and the following images are rotated by 90°. The details of the circuits cannot be analyzed. Electrically, the area is connected between the four data lines of the four memory blocks and the output stages for data output. The signal at the data input is also fed here. It can be assumed that the necessary multiplexing and demultiplexing takes place in this area.A closer look at the data output circuit reveals that four identical circuit blocks have been integrated in two symmetrical pairs. These are obviously four complete data outputs. In his article "Der Megabitspeicher U61000", Dr. Jens Knobloch mentions a 4-way test mode. It seems that the four blocks could be tested in parallel. That in itself is nothing unusual. It is surprising, however, that four output stages, including the necessary control, have actually been integrated.If the three additional outputs are transferred to the bondpads, only two bondpads remain whose functions remain unclear (X1, X2). It is quite possible that at least one of the bondpads activates or controls a test mode.This picture by Dr. Jens Knobloch shows a wafer that bears the structures of the U61000. These were 5" wafers on which 90 of the U61000 components could be integrated. At this stage of development, each U61000 still had a large test structure. In series production, this would have been omitted and significantly more components could have been integrated onto one wafer. Series production on 8" wafers had already started worldwide in 1990.Here are two more pictures of U61000 wafers that Carl Zeiss Jena used for advertising purposes.The above picture of the U61000 can be found in the magazine Mikroprozessortechnik (issue 10, 1989). There you can also see the large test structures.The publication "Looking back: Artwork and Mask Making in Dresden for the East German Megabit Chip Project" by Hans W. Becker provides deep insights into the technology used at the time to expose the wafers. The table above and the following images were taken from this publication.Carl Zeiss Jena made a major contribution to the development of the exposure process. For the U61000, 125mm x 125mm masks were used. The masks were made of chrome-coated glass. The structures were applied using the ZBA21 electron beam exposure system. The wafers were exposed directly using this mask and the AÜR wafer stepper. The AÜR used light with a wavelength of 436nm and could expose 25 wafers per hour.The wafer stepper AÜR offered the option of exposing two areas of different sizes. Minimum structure widths of 1,6µm could be imaged on an area of 20mm x 20mm. The imaging performance on an area of 12mm x 12mm is sometimes specified as 1,2µm and sometimes as 1,0µm.The image on the right shows that the area of 12mm x 12mm could not be used without restrictions on the AÜR. In the middle there is a strip that contains, among other things, structures that were needed for alignment and focusing. The division into two reduced the usable area, but was also intentional. The double placement of the design was used to identify errors on the mask by comparing the two halves. Errors could sometimes be corrected with a laser.Here you can see the distribution of the masks on the U61000-1 on the left. They were produced in May 1988. Due to the image scale of 5:1, the masks are significantly larger than the memory. The two large gray areas are the two memory modules. Above each memory is the test chip CT5 with its many test structures. Dr. Jens Knobloch is talking about the technology test field PTF5. The mask for the active areas is shown in the right-hand image. The structures of the memory and the test areas can be clearly seen there.The total area of the image is 12,95mm x 13,86mm and is therefore noticeably larger than the specified 12mm x 12mm of the AÜR wafer stepper. It was still possible to produce functional chips with it.Here you can see the mask for the aluminum layer of the U61000-2.1, which was produced in February 1989. More test structures are placed on it. The total area of the image is 12,70mm x 18,00mm, but not the entire area is used for exposure. The lower test structures are only used for troubleshooting on the mask.The image above shows the distribution of the masks for the U61000-2.2. This mask set was produced in October 1989. The middle two blocks represent the U61000 to be exposed and are shown on an area of 12,70mm x 10,30mm. The outer blocks are again only used for troubleshooting.Since the final version lacked the large test areas, more memory modules could be placed on the 5" wafers. If one assumes that on average 120 elements fit on a wafer across the various versions and assumes an average yield of 10%, one can estimate that around 2.500 wafers of the U61000 were produced. Since this was new technological territory, one can assume that quite some test wafers were produced and discarded in parallel.The U61000 was never mass-produced. Pilot production took place at the Zentrum für Mikroelektronik Dresden. However, the ZMD was not equipped for mass production. A separate production facility should have been set up in Erfurt for this. Before this happened, Germany was reunified. The U61000 was not even remotely competitive on the international market. The table above shows this quite clearly. It is taken from the dissertation "Wafer Stepper and Megabit Chip" by Dr. Otto Bernd Kirchner. The table documented the costs and prices of the DDR DRAM components in 1989. The world market price of a 1MBit DRAM was a factor of 100 lower than the manufacturing costs of the U61000.The U61000 had no future after reunification. However, a product was created from the know-how generated. As is usual with storage devices, attempts were made to make the circuitry of the U61000 as insensitive to radioactive radiation as possible. After reunification, the opposite was done and the storage device was developed into a radiation sensor. This gave rise to the company Megarad. This later became the company SARAD.In addition to the U61000, there was a U60998. There are no official documents for the U60998. Apparently, it is a U61000 with uncorrectable errors. This does not necessarily mean that the cells are completely defective. It may just be that certain specifications are not fully met in some cases. The U60998 could be used in applications where individual defective cells are less critical, for example as page memory in a printer. Apparently, U60998s have already been tested in which the full 1MBit could be written and read without errors.https://www.richis-lab.de/RAM10.htm

author: Noopy
author_rank: Super Contributor
timestamp: September 21, 2024, 09:47:58 am
content: There was a U61000-SIMM!And here you see a U60998. Unfortunately not mine... :'(

author: Noopy
author_rank: Super Contributor
timestamp: September 29, 2024, 04:00:20 am
content: The Intel 28F160C3TD is a Flash EEPROM in a BGA package. Intel refers to the product group as "Intel Advanced+ Boot Block Flash Memory (C3)".The datasheet shows what the designation 28F160C3TD means. The first two letters, which are not shown on the component shown here, indicates the package variant. 28F is the abbreviation for the memory family. The numbers 160 stand for a memory depth of 16 MBit. C3 specifies the product group in more detail. The T documents where the boot area is located in the memory. This area is divided differently and functionally isolated from the rest of the memory. The letter D at the end reveals that the memory was manufactured using a 130nm process.The datasheet also contains a block diagram of the memory.The package contains a die measuring 5,0 mm x 1,7 mm. The evenly structured memory areas are easy to recognise. The more inhomogeneous control logic is located at the bottom right. The circuit complexity in the control logic is only slightly dependent on which of the four memory volumes have to be controlled. It can therefore be assumed that the same control block is always used. In the 8 MBit variant, the memory area is then just as large as the control logic. For the 32 MBit and 64 MBit variants, the memory areas are simply doubled accordingly.This image is also available in a higher resolution:https://www.richis-lab.de/images/ROM/11x04XL.jpg(33MB)In the bottom right-hand corner there is a copyright from 2002 and the designation 28F1600.Here you can see one of the ten blocks that make up the memory area. Each of the two halves must contain 800kBit. This means that there are 12.500 individual bits under each of the 64 strips.Shorter strips can be recognised on the sides of two blocks. These could be reserve cells that replace defective memory cells.At the bottom edge of this you can see the smaller memory blocks in the centre, which represent the boot area.The typical chaotic structures of logic circuits can be seen in some places in the control area. In the lower right-hand area there is a relatively small square with stripes similar to the large memory areas. This could contain special memory cells. For example, the 28F160C3TD has a 128-bit "protection register", which contains a 64-bit ID that cannot be changed. In addition, further specially protected 64 bits can be stored.https://www.richis-lab.de/ROM11.htm

author: Noopy
author_rank: Super Contributor
timestamp: October 02, 2024, 03:03:05 pm
content: The CYK128K16 from Cypress Semiconductor is a PSRAM, a pseudo-static RAM. This is a DRAM that behaves like an SRAM. This means that you benefit from the less area consumed by the DRAM cells, but you don´t have to manage the refreshing of the data. In a PSRAM a circuit is integrated that takes care of the refreshing.The datasheet contains a very simple block diagram. The 2 MBit of memory are arranged in a 128k x 16 architecture. The memory is addressed via 16 address lines. The data is output in two 8-bit packets.The dimensions of the die are 4,1mm x 1,2mm. The surface has suffered some damage during removal of the epoxy, but the most important structures can be recognized. The die is coated with a polyimide layer.This picture is also available in higher resolution:https://www.richis-lab.de/images/RAM/14x03XL.jpg(25MB)The year 2003 can be found in the bottom right-hand corner. The character sequences CHD 216K9 cannot be assigned. A0 and A1 could be revisions of the metal layer.The memory area can be easily recognized by its regular structures in the metal layer.There are cut-outs in regular intervals under the memory area, in each of which there are obviously four fuses. Triggered fuses can also be seen in the right-hand area. Another block of these fuses have been integrated in the bottom right-hand corner of the die.https://www.richis-lab.de/RAM11.htm

author: Noopy
author_rank: Super Contributor
timestamp: November 03, 2024, 04:50:06 am
content: The M27C2001 is a 256kB UV EPROM built by ST Microelectronics.The datasheet explains the meaning of the marking in detail. M27 is the memory family. The C specifies the supply voltage. This is followed by the memory size. This memory belongs to an older generation with an access time of 150ns. Finally, the package type and the operating temperature range are specified in the marking.The dimensions of the die are 4,7mm x 3,1mm. The orange surface is striking. Such an old design most likely did not use copper in the metal layer. Perhaps the color is due to the passivation.This picture is also available in a higher resolution:https://www.richis-lab.de/images/ROM/12x02XL.jpg(18MB)The design dates from 1997 and M1 213 could be an internal designation.Nine masks can be seen in the bottom left-hand corner.The structures are too small to be fully resolved. The structures show clear unevenness resulting from the inhomogeneous structures in the different layers.https://www.richis-lab.de/ROM12.htm

author: magic
author_rank: Super Contributor
timestamp: November 03, 2024, 11:39:33 am
content: Quote from: Noopy on November 03, 2024, 04:50:06 amThis seems to be the case, because unpassivated areas of bonding parts are white. You may also see white elsewhere if you scratch the passivation layer on this kind of chips.

author: Noopy
author_rank: Super Contributor
timestamp: November 03, 2024, 04:26:08 pm
content: Quote from: magic on November 03, 2024, 11:39:33 amThat could also be due to different metals in the bondpad area.But I agree with you, probably it is due to the openings in the passivation layer.

author: Noopy
author_rank: Super Contributor
timestamp: November 12, 2024, 07:25:48 pm
content: The 256kBit DRAM U61256 (https://www.richis-lab.de/RAM09.htm) was produced under the name UD61256 after the reunification of Germany. The Zentrum für Mikroelektronik Dresden was transformed into a limited liability company. The above component dates back to 1994. While only the selection type of the U61256 can represent access times of 80ns, the UD61256 with index 07 is specified with a maximum of 70ns. There is also an 08 variant with a guaranteed 80ns.The dimensions of the die are 7,1mm x 3,6mm. This image of the die is also available in a higher resolution:https://www.richis-lab.de/images/RAM/15x02XL.jpg(38MB)The designation UD61256 is shown on the right-hand side of the die. The number 4 probably stands for a fourth revision. The design dates back to 1991. The design was apparently revised again after the reunification of Germany.In contrast to the U61256, the UD61256 has three additional bondpads. The location and connection suggest that there is a second data input and a second data output. The bondpad in the top right-hand corner cannot be assigned at first glance. It could be that a test mode has been integrated here, similar to the U61000 (https://www.richis-lab.de/RAM10.htm), which makes it possible to test parts of the memory simultaneously. This reduces the test time and therefore the manufacturing costs. The bondpad in the top right-hand corner could therefore be used to activate the test mode. The additional inputs and outputs could then be used to access two areas simultaneously, thus halving the test time. All three bondpads were contacted during production.The die of the U61256 was still 9,6mm x 3,8mm. In the UD61256, the area has been reduced to 7,1mm x 3,6mm. The development of the area required for one DRAM memory cell is shown in the U61000 (https://www.richis-lab.de/RAM10.htm#area). The U61256 has therefore undergone an evolutionary stage in which the area was reduced from 77µm² to 50µm². The U61256 above is labeled as U61256-1. It is very likely that this is the initial layout.The line selection in the right-hand area and the surrounding auxiliary circuits have been significantly reduced in size. The circuit has also been compressed. There are now significantly fewer free areas. The column evaluation has also been significantly reduced in size.The memory area has also been optimized. It is still divided into four large blocks, which still contain 512 x 128 memory cells. The 16 reserve columns on the right edge have also been adopted from the U61256. However, the segments that make up the blocks have been enlarged in the UD61256. Instead of 64 columns, they now contain 96 columns.The reserve columns are activated in the same way as the U61256. Two testpads are also integrated here, which enable fuses to be triggered in two blocks using the normal address interface. The fuses themselves are much harder to recognize here. They appear to have been slightly reduced in size. In addition, the silicone-like potting material with which the die was covered has accumulated in the space between the metal areas.https://www.richis-lab.de/RAM12.htm

author: Noopy
author_rank: Super Contributor
timestamp: November 20, 2024, 08:22:50 pm
content: As I already told you the 256kBit DRAM U61256 continued to be produced under the name UD61256 after the German reunification. The Zentrum für Mikroelektronik Dresden was transformed into a limited liability company. An updated datasheet exists for the UD61256. There was also the UD61259, but no information can be found on it. The component shown here was produced in 1992, slightly earlier than the UD61256 but already after reunification.The dimensions of the die are 6,9mm x 3,6mm. This image is also available in a higher resolution:https://www.richis-lab.de/images/RAM/16x02XL.jpg(46MB)The die was covered with a silicone-like protective layer. There are still residues. The designation U61256-3 is shown in the top right-hand corner of the die. This is obviously the third revision of the U61256. The copyright from 1989 shows that the design dates back to the time before the german reunification. As with the U2164 (https://www.richis-lab.de/RAM02.htm), an elephant is also depicted here.While the die of revision 1 in the U61256 was still 9,6mm x 3,8mm, revision 3 in the UD61259 is only 6,9mm x 3,6mm. Revision 3 is very similar to revision 4 in the UD61256. Revision 4 appears slightly larger. However, this is only due to the fact that more silicon has been left at the edges outside the functional area. Revisions 3 and 4 are very similar, but you can clearly see that the design has been revised. Functionally, however, the two versions appear to be the same.It remains unclear why the designation UD61259 was chosen for this variant. Perhaps there are too many memory cells which do not quite meet the specifications.https://www.richis-lab.de/RAM13.htm

author: Noopy
author_rank: Super Contributor
timestamp: December 16, 2024, 07:57:51 pm
content: The Intel D2164 is a 64kBit DRAM. The “20” variant offers a maximum access time of 200ns. A maximum access time of 150ns is specified for the “15” variant.Application Note AP-131 from Intel contains a lot of information about the D2164. The 64kBit are divided into four areas with 128 x 128 memory cells. The cells are addressed with two sets of eight address bits. The first seven address bits activate one row in the upper and one row in the lower areas. The second seven address bits select one column each in the left and right blocks. In this way, the D2164 delivers the content of four memory cells in the first moment. The eighth address bit, which has also been latched twice, realizes the selection of one memory cell, which is then output. Data is written in the same way.The dimensions of the die are 6,9mm x 3,7mm. The D2164 is based on the NMOS process HMOS-D III. The four-part division of the memory area is clearly visible.This image is also available in a higher resolution:https://www.richis-lab.de/images/RAM/17x02XL.jpg(37MB)The design dates back to 1981 and the A at the end of the designation 2164A could stand for a first revision.The Application Note AP-131 claims that the D2164 was the first commercially produced RAM to incorporate spare cells. Each of the four areas contains two additional columns and two additional rows that can replace faulty memory cells and thus significantly increase the yield.The reserve cells are assigned in the right-hand area of the die. Three testpads are integrated there for this purpose. This circuit is very similar to the spare cell configuration logic in the U2164 (https://www.richis-lab.de/RAM07.htm).There are cut-outs above the fuses. No fuse was triggered on this D2164.The application note describes the circuit for selecting the spare rows and spare columns in more detail. Each fuse is located in a so-called “programming element”, which has two transistors at the output. When the fuse is intact, the lower transistor is active. If the fuse is cut, the upper transistor becomes active. Vg and Vdp must be supplied via the testpads. The third testpad is not described in detail in the application note. On the die you can see that the current that triggers the fuse can flow through it. Intel has not disclosed how the individual fuses are selected. According to the circuit diagram, addressing is done with four lines. On the die you can see that the normal address lines are used to select the fuses. At least it seems like the normal adress lines control these programming elements.The image above shows how spare rows are integrated into the address area. First you have to trigger the “Spare Row Enable” fuse. The associated spare row then becomes active at a row address. The configuration of the fuses determines which address is assigned to the spare row. For this purpose, each programmable element forwards either its address bit or the inverted address bit.This explains the number of fuses. There are 32 fuses in the left-hand area and 36 in the right-hand area. If required, 4 fuses activate the two spare rows and the two spare columns. Four times 8 fuses can then be used to assign an address to each of the spare rows and spare columns.Parallel to the circuit described, a logic ensures that the normal line selection remains inactive as long as the spare line is active.https://www.richis-lab.de/RAM14.htm

author: Noopy
author_rank: Super Contributor
timestamp: December 30, 2024, 05:16:13 am
content: The Mikroelektronika Botevgrad CM8001 (SM8001) is an SRAM with a memory depth of 256 bits. It corresponds to the Intel 1101A. The 1101 was the second SRAM sold commercially by Intel. Intel supplied an improved version with the 1101A. Like the 1101 and the 1101A, the SM8001 is based on PMOS transistors and therefore requires a +5V potential and a -9V potential supply. The 1101 still had to be supplied with 5V, -7V and -10V. The 1101A had been optimized to such an extent that it could work with 5V and -9V. The access time of the SM8001 is specified with a maximum of 1,5µs. By selection it was possible to stay below 1µs. The marking shows that the component was manufactured in 1977.The die of the SM8001 has been placed far off-center in the package.The dimensions of the die are 3,1mm x 3,3mm.This image is also available in a higher resolution:https://www.richis-lab.de/images/RAM/18x03XL.jpg(14MB)800161 could be an internal designation.In the center of each edge is a structure that shows how well the masks were aligned during production.There are several test structures on the edges of the die. A resistor with a tap is integrated here.These structures could be used to determine the leakage currents between the lines in the substrate. They could also be used to measure the parasitic capacitance.The SM8001 is still based on a metal gate process in which the metal layer represents the gate electrodes of the MOS transistors. Where the metal layer is supposed to act as a gate electrode, there is a window with a gate oxide, a very thin silicon oxide layer in the thick, so-called field oxide. Intel has already manufactured the 1101 and the 1101A using a more modern silicon gate process. The polysilicon gate electrodes make it possible to produce more precise geometries.The source and drain areas of the transistor integrated here are difficult to recognize. In other areas, the structures are more clearly visible. On the right, a resistor leads to a fourth testpad. The contact between the resistor and the drain/source area appears to occur without a special contact window.Another test structure can be used to measure a parasitic MOSFET. This is a metal line that covers an insulation area between two lines in the substrate. Due to the thick field oxide, the charge of the metal line has a significantly lower influence on the underlying structures.The functionality of the SM8001 is very clear. The address lines A0 to A3 are buffered, decoded (red) and finally activate one of 16 columns in two memory areas (yellow). The memory is divided into two blocks, each with 16x8 memory cells. The address lines A4 to A7 are also decoded (blue) and then select one memory row (green). Two lines run in the line selection area, which either transmit a differential signal to the respective memory cell or forward the state of the memory cell to the circuit in the upper left area.The input buffer (pink) and the output driver (purple) are located in the upper left area. Both circuits are connected to the chip select and the R/W input. Like the 1101, the SM8001 also offers a complementary output to the data output. The two large push-pull output stages are clearly visible. In addition to the positive supply potential Vcc and the negative supply potential Vdd, the memory also has a Vd contact. Vd must also be connected to -9V and supplies the input and output circuits, while Vdd supplies the memory area itself.The regular structure of the memory area is clearly recognizable. It consists of blocks, each containing two memory cells.There is a Vcc line below each memory cell. The Vdd potential is located at the top and bottom. These Vdd lines are also used by the memory cells at the top and bottom. The word lines, which activate the corresponding column of the memory, run to the right and left of the two memory cells in the substrate. The two horizontal bit lines transmit the status of the selected memory cell.The SM8001 is based on 4T memory cells containing four PMOS transistors and two resistors.https://www.richis-lab.de/RAM15.htm

author: Noopy
author_rank: Super Contributor
timestamp: December 30, 2024, 03:58:46 pm
content: Quote from: Noopy on December 30, 2024, 05:16:13 amThat´s probably "8001 Б1". And Б1 (cyrillic B1) shows the design revision.

author: Noopy
author_rank: Super Contributor
timestamp: January 10, 2025, 01:53:24 pm
content: I have written a lot about the U61000 (https://www.richis-lab.de/RAM10.htm). That one was built 1990. Now I have one built in 1989. Here we see the logo of Carl Zeiss Jena.The die is the same size and design as the die of the other U61000 (A2). This was to be expected.The image of the die is also available in a higher resolution:https://www.richis-lab.de/images/RAM/19x02XL.jpg(51MB)In contrast to the other U61000 the DRAM documented here is one of the majority of components that were not initially error-free. At the turn of the year 1989 / 1990, the yield was 3%. By using redundant areas, it was possible to increase the yield to 10%.It can be seen that three of the four reserve rows and three of the four reserve columns were activated. Reserve rows and reserve columns were required in the inner two storage blocks. In the outer two memory blocks, one option was sufficient in each case.The modified fuse strips can be seen here. As described in the context of the other U61000, the individual lines have been chemically dissolved. To do this, the DRAMs were tested on the wafer and the necessary corrective measures were saved for each individual DRAM. After applying a new photoresist, individual exposure was carried out using electron beam lithography. This made it possible to chemically dissolve the desired lines selectively. The etching process attacked the frame structure to some extent.Errors in the structure of the memory are difficult to recognize in the overview. In this section, two lines of the metal layer are shorted.The pattern on the left-hand side of this image appears to be heavily disturbed. However, it cannot be said with certainty that there is a defect here. It could also be a disturbance in the layer structure that only has an optical effect.https://www.richis-lab.de/RAM16.htm

author: RoGeorge
author_rank: Super Contributor
timestamp: January 10, 2025, 02:16:51 pm
content: Quote from: Noopy on January 10, 2025, 01:53:24 pmThrowing away 97%, or throwing away "only" 90% of the dies, wouldn't that be unsustainable? Asking because I don't know what percentage would be considered normal.What was the typical yield of an IC during the 80s?

author: Noopy
author_rank: Super Contributor
timestamp: January 10, 2025, 02:38:43 pm
content: The memory was a new technology (not just the node size).The process was new.Everything had to be developed and produced in the GDR without the help of other countries.It was not yet a series production.Regarding all this the yield was not bad.Back in these days in series production in another country the yield should increase to 90% or more in my view.

author: Noopy
author_rank: Super Contributor
timestamp: January 13, 2025, 04:04:10 pm
content: Some time ago I presented the KM537RU1 but somehow I missed the nice defect in the memory area:The two bit lines of this row are interrupted. One line of the upper right-hand memory cell also melted. The polysilicon layer that forms the gates has become heavily discolored. A high current appears to have flowed from the positive supply potential in the center of the image to GND.https://www.richis-lab.de/RAM06.htm#defect

author: Noopy
author_rank: Super Contributor
timestamp: January 15, 2025, 04:32:39 am
content: We already had the КM537РУ1 (KM537RU1), the 1kBit SRAM. Here you see the КP537РУ1 (KR537RU1) the epoxy variant of this RAM.The manufacturer cannot be identified, which is often the case with semiconductors from the Soviet Union. Widespread types were usually produced by several manufacturers. The datecode shows that the component dates back to 1988.The dimensions of the die are 3,9mm x 3,0mm. The architecture is similar to that of the KM537RU1, but the two memories are very different in detail. This indicates that this is a different manufacturer.The image of this is also available in a higher resolution:https://www.richis-lab.de/images/RAM/20x02XL.jpg(66MB)The structure of the DRAM is shown in the top left-hand corner. 1024 memory cells are written and read via one data line.Nine masks are shown at the top edge of the die. A more complex test structure is also integrated there. It will become clear that this is a single memory cell.There is another memory cell as a test structure on the right-hand edge of the die.Simple structures can be measured on the lower edge using some testpads.Most of the function blocks on the die are the same as those integrated in the KM537RU1. Two input buffers of the address lines have been combined here. The pull-up structures of the bitlines are no longer located on the left but on the right edge of the memory area (red). At the upper edge there is a protective structure between the supply potentials, which is not present in the KM537RU1.The memory area is somewhat confusing at first glance, but the individual memory cells can be delimited.The KR537RU1 uses the usual 6T memory cells with six transistors. The colors (green and red) show where NMOS and PMOS transistors are integrated. The geometries of the transistors differ significantly from those in the KM537RU1. In addition, the GND potential is only distributed on one side.https://www.richis-lab.de/RAM17.htm

author: iMo
author_rank: Super Contributor
timestamp: January 15, 2025, 09:31:34 am
content: Quote from: Noopy on January 10, 2025, 02:38:43 pmAfaik, the yields at that time were perhaps half of that..Your yield might be applicable for today, imho.

author: Noopy
author_rank: Super Contributor
timestamp: January 15, 2025, 08:53:06 pm
content: Quote from: iMo on January 15, 2025, 09:31:34 amNo, I´m pretty sure the yield back in the days was round about 90% if we are talking about series production after some optimization. (The GDR of course had to struggle to reach such values.)I had a document which said that the yield of the GDR 64kBit DRAM reached 90% after some help from Hitachi. Unfortunately I can´t find the document right now.This document is german but very interesting (Siemens 1991):https://www.tf.uni-kiel.de/matwis/amat/archive_hf/kap_5/articles/foe_be_chipmaking_brochure.pdfPage 1: A final yield of 70% - 90% has to be reached.Page 19: A yield between 85% and 95% in the year 1985.

author: iMo
author_rank: Super Contributor
timestamp: January 15, 2025, 09:52:26 pm
content: Out of curiosity I asked AI:Quote

author: Noopy
author_rank: Super Contributor
timestamp: January 16, 2025, 06:14:24 pm
content: I can´t recommend to use AI to answer such questions. In the background I´m working on a DAC and just for fun I asked ChatGPT how it works. Well, ChatGPT was wrong but put a lot of nice words around the wrong information...

author: magic
author_rank: Super Contributor
timestamp: January 17, 2025, 06:50:29 am
content: Yes, this is ridiculous. The thing could make up any random numbers and write some plausible justification for them and there is no way of knowing whether the result is even remotely true.It's semi-OK to use it for some tedious work whose result can be verified faster than it would take to produce it wholly by yourself. But never trust the output.

author: Noopy
author_rank: Super Contributor
timestamp: May 30, 2025, 07:09:40 pm
content: The Atmel 5962-38267 is the military version of the 128kB EEPROM AT28C010. The character strings in the second line show that it is a bin with an access time of 150ns, an requires 10ms to write data. The qualification, the package type and the surface finish of the pins are also documented.The flat package has a strikingly large metal cover. The pins are bent inwards and rest on the circuit board.The die of the memory is 10,8mm x 9,0mm.The majority of the area is taken up by the memory cells. No segmentation can be seen within the memory area.This image is also available in a higher resolution:https://www.richis-lab.de/images/ROM/13x05XL.jpg(88MB)The internal designation appears to be 17106. Seven masks are shown. The letters usually represent revisions. This would mean that the masks with the letters N and S have been revised extremely often.The structures of the memory cells are too small and covered by too many layers to be analyzed in detail.https://www.richis-lab.de/ROM13.htm

author: Noopy
author_rank: Super Contributor
timestamp: July 19, 2025, 06:55:56 pm
content: WSI is the abbreviation of the American company Waferscale Integration, which was taken over by ST Microelectronics. The 57C51B is a 16kB EPROM, which has a predecessor with the 57C51. While the 57C51 provides access times of 70ns, the 57C51B offers bins with access times of up to 40ns. The numbers behind the type designation document the access time, here it is 55ns.The dimensions of the die are 6,0mm x 3,6mm.This image is also available in a higher resolution:https://www.richis-lab.de/images/ROM/14x02XL.jpg(38MB)The design apparently dates from 1987 and CNW44A could be an internal project designation.In one corner there are a few letters that probably represent the initials of the developers. The numbers 6026 cannot be assigned.https://www.richis-lab.de/ROM14.htm

author: Noopy
author_rank: Super Contributor
timestamp: July 22, 2025, 06:56:58 pm
content: The 57C51C is a further development of the 57C51B. The specifications hardly differ. With an access time of 35ns, the fastest bin of the 57C51C is still slightly faster.The dimensions of the die are 3,8 mm x 3,2 mm.This image is also available in a higher resolution:https://www.richis-lab.de/images/ROM/15x02XL.jpg(58 MB)Compared to the 57C51B, the die of the 57C51C is significantly smaller. The new variant was apparently introduced mainly to save silicon area.The design of the 57C51C is three years younger than that of the 57C51B. The character string and number sequence shown on the die have changed. Both could still be an internal project designation or a designation of the manufacturing process.There are some very simple test structures distributed across the surface that demonstrate the resolution capability of the process. A slightly more complex test structure is also integrated here.https://www.richis-lab.de/ROM15.htm