SAMD20: Unable to port timer counter to WO pin - SOLVED - Page 1
Forum section: electronics / general

author: bogmaerke
author_rank: Newbie
timestamp: February 24, 2023, 11:12:14 am
content: Hi guys.First time posting here, but I am quite stuck, so I figured I'd see if someone here can help. I'm attempting to setup a SAMD20 microcontroller to use the TC1 timer and generate any kind of signal on the WO (specifically PA06).I know that the counter actually works, as I can see it's value change in the debugger. I simply cannot for the life of me figure out why it isn't generating the signal on the pin.For reference, this is the datasheet I'm using:https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/DataSheets/SAM-D20-Family-Data-Sheet-DS60001504.pdfThe two functions below are called in main(). Brief overview of what the program doesSetup the 8 MHz internal oscillator to be the system clockSetup the 8 MHz internal osc. to be the source of GCLK1 (Used to outputting it's clock to another GPIO)Use 8 MHz internal osc. as GCLK0, enable this GCLKEnable GCLK for TC0 and TC1Setup pin PA06 as output, mux F -> (TC1/W, enable muxEnable TC1 in PMSetup TC1 and enable itSetup of main clock and GCLK1Code:void CPU_CLOCK_8MHZ(void){SYSCTRL->OSC8M.bit.PRESC |= 1;SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;/** Set GCLK1 as current GCLK* Set source to OSC8M* Enable output* Enable GCLK1*/GCLK->GENCTRL.reg |= GCLK_GENCTRL_ID_GCLK1;GCLK->GENCTRL.reg |= GCLK_GENCTRL_SRC_OSC8M;GCLK->GENCTRL.reg |= GCLK_GENCTRL_OE;GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;// Wait for synchronization to completewhile(GCLK->STATUS.bit.SYNCBUSY);}Initializing the timer counter TC1Code:void TC1_INIT(void){/** Set GCLK0 as current GCLK* Set source to OSC8M* Enable GCLK0*/GCLK->GENCTRL.reg |= GCLK_GENCTRL_ID_GCLK0;GCLK->GENCTRL.reg |= GCLK_GENCTRL_SRC_OSC8M;GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;// Wait for synchronization to completewhile(GCLK->STATUS.bit.SYNCBUSY);GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_ID_TC0_TC1;GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;GCLK->GENDIV.reg |= GCLK_GENDIV_ID_GCLK0 | GCLK_GENDIV_DIV(1);// Wait for synchronization to completewhile(GCLK->STATUS.bit.SYNCBUSY);// Setup RGB_DATA / PA06 to outputPORT->Group.DIRSET.reg |= (1 << RGB_DATA);// Mux TC1/WO -> FPORT->Group.PMUX.reg |= PORT_PMUX_PMUXE_F; // Odd/even register, [0 1] [2 3] [4 5] [6 7], 6 is 4th// Enable muxPORT->Group.PINCFG.reg |= PORT_PINCFG_PMUXEN;// Enable TC1PM->APBCMASK.reg |= PM_APBCMASK_TC1;// Set to 16-bit modeTC1->COUNT16.CTRLA.reg |= TC_CTRLA_MODE_COUNT16;// Set wave gen to Match frequency (p 430)TC1->COUNT16.CTRLA.reg |= TC_CTRLA_WAVEGEN_NPWM;// Prescale clock by 1 (TC1 is GCLK_GEN0) and sync on PSCTC1->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER_DIV1;TC1->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC_PRESC;// Allow running in debug modeTC1->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN;// Set count valueTC1->COUNT16.CC.reg |= TC_COUNT16_CC_CC(32000);TC1->COUNT16.CC.reg |= TC_COUNT16_CC_CC(15000);while(TC1->COUNT16.STATUS.bit.SYNCBUSY);// Enable TC1TC1->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;}

author: bogmaerke
author_rank: Newbie
timestamp: February 24, 2023, 11:30:03 am
content: Well, I solved it myself, finally.PORT->Group.PINCFG.reg |= PORT_PINCFG_PMUXEN;Not PINCFG. Off by one, but shouldn't pin 6 be index 5 in an array?

author: voltsandjolts
author_rank: Unknown
timestamp: February 24, 2023, 11:57:14 am
content: The port pins themselves are labelled starting at 0

author: bogmaerke
author_rank: Newbie
timestamp: February 24, 2023, 02:18:06 pm
content: You know, I never realized that. Thanks