Huge memory Logic Analyzer, is it worth rolling your own? - Page 1
Forum section: electronics / projects

author: Frio
author_rank: Contributor
timestamp: September 26, 2018, 02:55:59 pm
content: Hello everyone,For a long-term project I am planning, I would like to have the ability to perform one-shot store of 200+ channels at once, at ~50MHz, for ~0.2 seconds.Who wouldn't want that?The target is a mid ~1990s computer system, with several processors and busses, and I intend to trace most (or all) of its busses at the same time for a fraction of a second, which requires hundreds to thousands of MSamples of storage.My point is that other than the humongous LAs available for purchase for the very reasonable price of a good sports car, I cannot find a product that scales to what I need made from chaining a number of smaller devices, and performing all the analysis in software.So, with this in mind, would it make sense to create a small-ish device, CPU+FPGA with 256MB or so of on board DRAM, capable of handling 30-40 channels, and then either chaining multiple of these, or use them completely separately, driving them via software and aggregating the results on a PC.I realize that this is in fact how some of the modular commercial LAs are designed in the first place, but given the cost of some low-end systems like the BeagleBoard and others, I cannot help but thinking that there may be a way to engineer a ~$1000-$2000 system with the characteristics I need.Please don't be mad at me if all of this makes no sense, I am a software guyThoughts?Cheers,Frio

author: oPossum
author_rank: Super Contributor
timestamp: September 26, 2018, 03:08:02 pm
content: A used Agilent 16700/16702 can do what you want. A well equipped system can go for under $1000.

author: duak
author_rank: Super Contributor
timestamp: September 26, 2018, 03:36:56 pm
content: In the late 80's, I had a co-op student design a 192 * 128K data grabber for a product under development. It took him about a month and over the next couple of years, it paid for itself many times. We left a slot open for it in the product's cardcage just in case it was needed for debugging.I think that regardless of whether you build, buy or rent having the proper tools make a lot of sense.Cheers,

author: taydin
author_rank: Frequent Contributor
timestamp: September 26, 2018, 03:56:36 pm
content: To process a 50 MHz digital signal, you would need a roughly 200 MHz circuit design. This is far from trivial to do. The PCB would need to be designed to handle this frequency, and probes need to be used that do good matching between the LA and the DUT at these frequencies. An old HP/TEK logic analyzer would do the high frequency part of this, but those have very little memory.But ... if the signal is 50 MHz, but with very fast rise times, then the circuit design needs to be able to handle much more than 200 MHz. I remember troubleshooting an digital audio signal bus (I2S) with a sample rate of 192 KHz, where the bit clock was around 6 MHz. I brought that signal to the edge of the PCB using a header and then connected my audio analyzer to it. Audio was all garbled and a spent the better part of the day to try to understand why. In the end, it was the probing that was degrading the bit clock signal integrity. I was basically chasing a problem that I had created

author: nctnico
author_rank: Super Contributor
timestamp: September 26, 2018, 06:11:06 pm
content: 50MHz=20ns period during a 0.2sec period means 10Msamples. This is peanuts for a logic analyser like the Tektronix TLA700 series (I'd look for a TLA715 at least) with a couple of TLA7AA4 modules (hackable to 32Mpts per channel). The TLA7AA4 modules have about 760MBytes of memory in them. You can buy a setup like this for less than $1000 including the probes. You'll have to make an adapter board for the probes but this doesn't add a lot of cost. The big advantage is that the TLA700 series modules can also be used in a timestamped mode which only records changes and thus making a much longer acquisition period possible. Besides that the TLA700 series logic analysers have an extremely powerful (programmable) trigger engine.

author: TK
author_rank: Super Contributor
timestamp: September 26, 2018, 07:11:33 pm
content: Quote from: oPossum on September 26, 2018, 03:08:02 pmI recommend the 16702B, and I see them for around $500 or even less on eBay

author: iMo
author_rank: Super Contributor
timestamp: September 26, 2018, 07:56:29 pm
content: The Xilinx'es "ChipScope" (an on-chip LA) can do over a thousand of channels. You may try to connect your signals to a suitable FPGA and use the ChipScope as-is. I did with CS while I was messing with a PDP-8 on Spartan6 looking at about 50 internal signals and it worked fine.

author: Frio
author_rank: Contributor
timestamp: September 26, 2018, 08:45:27 pm
content: Amazing responses, everyone, thank you so much!I am very tempted by a bench LA like the TLA700 or 16702B, but a more compact solution would be great.Quote from: imo on September 26, 2018, 07:56:29 pmCould you please let me know a little bit more about this?I need to look at signals taken from an existing system, rather than something internal to the FPGA.Can ChipScope use external probes too? What about external memory?

author: Frio
author_rank: Contributor
timestamp: September 26, 2018, 08:53:18 pm
content: What kind of modules would allow me to probe 200 channels, with at least 10/20 MSamples?

author: Frio
author_rank: Contributor
timestamp: September 26, 2018, 08:56:42 pm
content: That is only if I can sample at the system clock speed.Shouldn't I use a much faster sampling rate (200MHz or so), which means proportionally more samples?

author: james_s
author_rank: Super Contributor
timestamp: September 26, 2018, 09:00:05 pm
content: I bet you could do it with an FPGA with a sufficient number of IO pins. There are already multiple open source FPGA logic analyzers out there.

author: TK
author_rank: Super Contributor
timestamp: September 26, 2018, 09:02:42 pm
content: When analyzing sample rate, you need to consider Timing or State analysis. State means that you provide an external clock and state bits from your DUT and you decode signals based on those state changes... timing analysis is when the logic analyzer clocks the sampling and it just captures the signals regardless of the DUT clock. The 4 times DUT clock for sampling rule applies to timing analysis, as with state analysis, each sample is a DUT state change.

author: TK
author_rank: Super Contributor
timestamp: September 26, 2018, 09:10:20 pm
content: Quote from: Frio on September 26, 2018, 08:53:18 pmHP 16702 with 16751A or 16752A modules... each module can handle 68 channels so you will need at least 3. You will need at least 13 PODs and each one can be around $20-$25.Tektronix Logic Analyzer modules tend to pack more channels per module, like the 7N4 module has 136 channels. I have not owned a Tektronix unit so I don't know how much the PODs cost on eBay.

author: iMo
author_rank: Super Contributor
timestamp: September 26, 2018, 09:40:13 pm
content: QuoteThe ChipScope IP LA is a part of the ISE14.7 (or Vivado).You add an IP LA core to your design, allocate the internal ram for the samples and connect the LA to your internal signals.You may connect your "internal signals" to the FPGA pins - that way you may analyze external signals (not tested however).The ChipScope does not use external probes or external memory. It uses internal FPGA memory. Not sure it knows RLE.BTW, the project you are starting requires certain experience with that stuff.. Wouldn't be better to start with something smaller??

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: September 27, 2018, 12:17:52 am
content: Interesting. Assuming you are trying to capture a repetitive event, can't you "undersample" it?That is, set your trigger, read 20 channels. Change to the next 20 channels, reset the system, use the same trigger, collect next 20 channels.I don't know. I have a relatively simple and old Intronix Logicport logic analyzer, probably not up to the task in any case, but I'd try to divide and conquer.I don't see why it wouldn't work, but I'm ready to learn why it wouldn't...

author: oPossum
author_rank: Super Contributor
timestamp: September 27, 2018, 03:22:55 am
content: The desire for a large capture memory usually means that someone doesn't want to spend time setting up anything other than the most basic triggers, or wants to trace program flow long enough to find a problem.

author: nctnico
author_rank: Super Contributor
timestamp: September 27, 2018, 07:29:07 am
content: Quote from: oPossum on September 27, 2018, 03:22:55 amNot quite. If you do a long capture you can do a detailed analysis quicker because you don't need to trigger on specific cases and correlate various measurements by hand. At least on Tektronix you can open the same acquissition in different windows and zoom in / search on various events.Back in the old days (before I owned a logic analyser with really deep memory) I used to print screendumps and then correlate these by hand with other measurements. Needless to say that this is a cumbersome process.

author: EEVblog
author_rank: Unknown
timestamp: September 27, 2018, 08:59:21 am
content: Quote from: Frio on September 26, 2018, 02:55:59 pmYou first need to determine if you need state analysis or timing analysis, as that determines the memory needed and the sample rate.State analysis means you clock the samples in synchronisation with the clock of the system under test. For doing a CPU based system this sounds like what you want to do?If you need timing analysis on hundreds of 50MHz max signals, what resolution do you need? i.e. is 10 samples for 1 system clock cycle enough? (500MHz LA sample rate)

author: Frio
author_rank: Contributor
timestamp: September 27, 2018, 05:02:01 pm
content: Quote from: imo on September 26, 2018, 09:40:13 pmThanks for the information.You are absolutely right, the project is complex and requires experience. My plan is to learn by reading and doing (I am in no hurry to complete it), by approaching the project incrementally, first by tracing a single bus, then tracing a CPU state, then add other busses over time.The ultimate purpose is to use the generated data in a custom software interface for the purpose of system-level performance analysis.

author: Frio
author_rank: Contributor
timestamp: September 27, 2018, 05:06:58 pm
content: Quote from: Alex Eisenhut on September 27, 2018, 12:17:52 amUnfortunately I will not be inspective repetitive events, but rather the overall behavior of a system running for a specified amount of time (around two tenths of a second is sufficient).Divide and conquer is indeed where I thought of pointing towards, given that I could theoretically use multiple LAs for different portions of the system and then aggregate the data in software...The Intronix Logicport seems interesting, 200MHz state capture would be sufficient for this specific project, although the 2048 samples are way too few, and the state capture rate would not be sufficient for some future projects I have in mind.

author: Frio
author_rank: Contributor
timestamp: September 27, 2018, 05:11:23 pm
content: Quote from: oPossum on September 27, 2018, 03:22:55 amIf I may, this is not the case in my project. My goal is to perform a full system peformance analysis over a period of time, via software, using a full system trace captured via a LA/FPGA.Of course I could capture traces in very small time increments, although I would need to identify suitable triggers to capture each time slice, and restart the system many times in order to "stitch" together the full trace, perfectly doable of course, just not very convenient...

author: Frio
author_rank: Contributor
timestamp: September 27, 2018, 05:14:18 pm
content: Quote from: EEVblog on September 27, 2018, 08:59:21 amI don't believe I need any to perform any timing measurements for my purpose, state analysis is realistically all I need.I need to trace the state of multiple CPUs, custom chips, buses and (synchronous) memory, all clocked at <50MHz.

author: DaJMasta
author_rank: Super Contributor
timestamp: September 27, 2018, 07:37:48 pm
content: If all those parts are clocked from the same source, then yes, state analysis would suffice, but if you've got multiple clock sources then you either need timing analysis or one state analysis system per clock source (since they will be slightly off and they will drift).In either case, I don't think rolling your own is all that valuable. Considering used equipment, the demand for logic analyzers is not as high as a lot of stuff, so the prices used are very reasonable even for several hundred input mainframe style units. Even if the hardware price is reasonable to do your own. the slight premium a used LA from a reputable brand would cost would give you all the software and save you the development time, perhaps including useful features you wouldn't have even considered that will speed up debugging.Even if you go the ChipScope route and have much of the software taken care of... how many of those inputs on your massive FPGA are going to be 5V tolerant (if that's you're system voltage)? Maybe you're going to be at 3.3V or lower for most of the design in which case many of the GPIOs from the FPGA will be usable, if you're needing logic analysis on regular old 5V logic, the ChipScope could need a board with hundreds of input voltage dividers to be a viable option.I think the versatility of a dedicated Logic Analyzer makes it more appealing for a project like this, and that the going price for used instruments is low enough that a DIY solution is probably only marginally cheaper if you discount the cost of your own time spent entirely.

author: rstofer
author_rank: Super Contributor
timestamp: September 27, 2018, 09:40:30 pm
content: When you start to plan your system, think about the trigger that starts the recording. There are two ways to do that: The easy way is to gin up a trigger signal in your logic and use that. For FPGAs, this is easy!The other is to have a cascade of event3 follows even2 follows event1 -> trigger. I don't know that it is useful to you but I built up this FPGA logic analyzer years ago when I was designing a CPU:https://www.sump.org/projects/analyzer/It might be worth digging through the application to see how the trigger works. It's been a long time but, as I recall, the trigger setup was excellent. Some combination of 32 signals followed by 3 more iterations for a total of 4 events before the trigger (maximum, the trigger could be as simple as a single signal).If you clock at 50 MHz for 0.2 seconds, you have 10 million samples to paw through and times N channels, that's a lot of data. Maybe look into sending it to a PC and come up with a filtering app.Any of the professional LAs will probably be adequate. The manufacturers knew what they were doing.For my project, inside an FPGA, without ChipScope or ILA, I had to bring my signals out to a 50 pin header so I brought out 32 channels. As I debugged stuff, I reorganized which signals to bring out. It worked out ok. Slow, but it worked out. Today, I would use one of the FPGAs supported by Xilinx Vivado so I could use their Internal Logic Analyzer. It's really slick.

author: rstofer
author_rank: Super Contributor
timestamp: September 27, 2018, 09:46:27 pm
content: Is there any reason you absolutely must run at 50 MHz during debugging? If you're looking at signal integrity, sure, but if you're looking at state information, perhaps running it at 1 Hz (or slower) is adequate. What I'm getting at is using port expanders and SPI/I2C to grab up the state information into a slow Arduino that can forward the information to the PC over the serial port. I don't know how fast it would allow the system to run but probably in the 100 Hz region.The last CPU I built had a single step clock mode so I could watch what happened at each clock. I couldn't bring out everything but, with 16 LEDs and 8 7-Segment displays, I could bring out a lot.Later on, after the state transitions are known to be correct, maybe there isn't a need to look at so many channels.Or not! Just instrument the heck out of it and filter the results of running at full speed.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: September 27, 2018, 11:07:28 pm
content: Quote from: Frio on September 27, 2018, 05:06:58 pmYeah it's pretty long in the tooth these days but the software is stable. It's fine for tooling around 8 bit vintage computers.

author: Frio
author_rank: Contributor
timestamp: September 28, 2018, 12:48:50 am
content: Quote from: DaJMasta on September 27, 2018, 07:37:48 pmAll extremely good points, thank you very much. This is a flawless reasoning that definitely makes me veer towards a used mainframe...

author: Frio
author_rank: Contributor
timestamp: September 28, 2018, 12:53:30 am
content: Quote from: rstofer on September 27, 2018, 09:40:30 pmOh wow, I read about the SUMP FPGA analyzer, very nice work indeed!I was thinking about sending data to a PC (if going the FPGA route), but I would need a really significant bandwidth to stream 10M samples * ~100/200 channels, that is the reason I was thinking about multiple small LAs each with its own local RAM, each dedicated to acquire and store a bunch of channels...It looks like going the mainframe route may be advantageous on several fronts...

author: EEVblog
author_rank: Unknown
timestamp: September 28, 2018, 12:54:06 am
content: Quote from: DaJMasta on September 27, 2018, 07:37:48 pmI agree, I don't see the value in rolling your own.Sure you can make your own FPGA solution or something, but why bother with all the potential development trouble involved in developing such a thing when you could just use a big 2nd hand LA.Just buy an existing tool and spend your time on the thing you want to analyse.

author: EEVblog
author_rank: Unknown
timestamp: September 28, 2018, 12:56:35 am
content: Quote from: Frio on September 27, 2018, 05:14:18 pmIf it's just a single master clock then it's easy, you could use almost any old big LA, even ones from 20+ years ago could easy do 50MHz state analysis.

author: Frio
author_rank: Contributor
timestamp: September 28, 2018, 01:00:03 am
content: Quote from: rstofer on September 27, 2018, 09:46:27 pmThis is a very good point indeed, although the design is not mine, and I am not actually sure it can be underclocked so severely.It is a videogames console, with a number of components, which I am not sure would operate correctly if the clock was altered so much.The specific one I am interested in right now (Sega Saturn) also has multiple clock sources, which really doesn't help...

author: hli
author_rank: Frequent Contributor
timestamp: September 28, 2018, 08:50:58 am
content: The Digital Discovery comes with a 2GBit memory, and can handle 32 channels. Theoretically you can fit 64MSamples in memory then, but I think the software limits it to less than that (would need to check at home, but I think 10MSamples are the maximum). But when you can use an external clock, at 50MHz this would exactly fit your needs. And its quite reasonably priced for what it can do.

author: TK
author_rank: Super Contributor
timestamp: September 28, 2018, 10:15:32 am
content: Quote from: hli on September 28, 2018, 08:50:58 amOP is asking for a logic analyzer that can capture 200+ channels

author: Frio
author_rank: Contributor
timestamp: September 28, 2018, 01:04:51 pm
content: By the way, going the Tektronix TLA route, what would be the cheapest solution for the probes?The mainframe and boards can be found for reasonable prices, but the probes (e.g. the general purpose P6810) are crazy expensive!

author: DaJMasta
author_rank: Super Contributor
timestamp: September 28, 2018, 03:33:54 pm
content: Cheapest option is to find a mainframe that has the bag attached to the top and get the probes as a bundle

author: hli
author_rank: Frequent Contributor
timestamp: September 28, 2018, 05:48:07 pm
content: Quote from: hli on September 28, 2018, 08:50:58 amOP is asking for a logic analyzer that can capture 200+ channelsI was distracted by the "capable of handling 30-40 channels" comment. Depending on the budget it might be worthwhile to just purchase multiple Digital Discoveries, then.To bad that serial (SPI) SRAMs only come up to 1MBit or so - otherwise one solution would have been to just connect one of them to each data line, and just clock the data into them after the start condition has happened (as theLogic Piratedoes). Maybe thats something you can roll on your own using a FPGA dev board that has a big enough DRAM on board.

author: nctnico
author_rank: Super Contributor
timestamp: September 28, 2018, 10:03:15 pm
content: Quote from: Frio on September 28, 2018, 01:04:51 pmI suggest to go for the TLA7AA4 modules and the P6860 probes (with the compression strips though). Don't be afraid to make an offer on Ebay because they are not selling very quickly!The advantage of the TLA7AA4 modules is the low price, large memory depth, 8GHz samplerate and 4 analog outputs. The analog outputs allow to monitor any input on an oscilloscope. IIRC the bandwidth is around 2GHz.

author: Frio
author_rank: Contributor
timestamp: September 29, 2018, 12:41:10 am
content: Quote from: nctnico on September 28, 2018, 10:03:15 pmFantastic, this is what I will be looking for then, thank you.As for the P6860, how can I use them to trace a bus or a CPU?As in: just as you said the connectors are compression strips, and to monitor a CPU I need to connect those to a TFBGA package pin array.Thoughts?

author: RomDump
author_rank: Regular Contributor
timestamp: September 29, 2018, 01:03:54 am
content: Quote from: Frio on September 29, 2018, 12:41:10 amWith the P6860 you may have to make an adapter or buy one that has Fly leads to connect to your bus. You wouldn't connect directly to the TFBGA package as the balls are inaccessible. You would connect to the bus from like the dram and peripheral chips that have their leads exposed.I disagree with getting the TLA7AA4 and P6860. You probably better off getting TLA7P4 or TLA7Q4 and with P6417 or P6418 probes. You have more probe options and memory and it may be cheaper and easier in the long run.

author: RomDump
author_rank: Regular Contributor
timestamp: September 29, 2018, 01:28:36 am
content: Quote from: Frio on September 28, 2018, 01:00:03 amDoes the Sega Saturn have BGA's?From this video doesn't look like it.

author: Frio
author_rank: Contributor
timestamp: September 29, 2018, 03:21:09 pm
content: Quote from: RomDump on September 29, 2018, 01:03:54 amGood point about the TLA7P4 as there are more and cheaper options for the probes. My concern is only on the memory size for the P4 and Q4, thoughts?Never mind, I see that the Q4 can go to 64M!

author: Frio
author_rank: Contributor
timestamp: September 29, 2018, 03:28:50 pm
content: Quote from: RomDump on September 29, 2018, 01:28:36 amYou are absolutely right, I was looking at the SH-2 spec sheet and it reports FPBGA, but this is likely only for ordering newer parts than the ones installed in the Saturn.The ones in the Saturn are QFP, what is the best way to attach the probes? Still using exposed lines or directly to the QFP pins?

author: RomDump
author_rank: Regular Contributor
timestamp: September 29, 2018, 11:23:50 pm
content: Quote from: Frio on September 29, 2018, 03:28:50 pmCourtesy of Jonathon Donaldson (jwdonal) VeriSNES project.I believe these are P6417 Probes. He made adapters to the QFP pins.You get the idea.

author: Frio
author_rank: Contributor
timestamp: September 30, 2018, 03:50:21 am
content: I most certainly do, thank you!