Two IC's outputting at the same time: Damage or Not? - Page 1
Forum section: electronics / projects

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 12:46:55 am
content: Howdy pirates,A question has come to mind about two IC's of the same logic family and brand that would have their outputs connected together. Let's say for example the output of an OR gates is connected together with that of an AND gate of say the 74HC logic family.Looking at the datasheets it says that the output impedances are symmetrical, so IOH == IOL, so the sourcing current is the same as the sinking current. In this case, there shouldn't be problems right? If the maximum output current given by a IC is 20mA, an the maximum sinking current is 20mA, then what problems could emerge if you keep the same logic family and brand?Then if you change the logic family or brand, but IOH still is IOL, could problems emerge? In other words, would any IC's get toasted for breakfast ?

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 12:50:46 am
content: Quote from: PauloConstantino on July 02, 2017, 12:46:55 amPaulo, please take a look at this:http://www.ti.com/lit/an/sdya009c/sdya009c.pdf

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 12:54:13 am
content: If I understand you correctly (and ignoring some exceptions, such as tri-state busses, open collector etc). You DON'T connect outputs to each other. Especially when the outputs can disagree (one is at 1, while the other is at 0).Those currents are guaranteed minimums, NOT guaranteed maximums. So considerably more current could flow.tl;drPlease don't short circuit outputs together (unless they are designed to be connected that way, such as tri-state, open-collector and some other exceptions).Controversially, some people connect outputs together to get a higher drive current, when the logic levels, are connected in such a way, that the outputs will always agree with each other. Such as multiple inverters in a hex inverter package. I.e. the inputs are also connected together.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 12:56:19 am
content: Quote from: MK14 on July 02, 2017, 12:54:13 amHi MK. I really want to connect two outputs together. Why can't I do this?

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 01:01:18 am
content: Quote from: PauloConstantino on July 02, 2017, 12:56:19 amYou would be basically creating a near short circuit, between the two power rails. It may well also overload/overheat the chips. Especially if lots of outputs are connected that way.You are free to do anything you like. In the same way the electronics is free to let out the magic smoke. At anytime.

author: alm
author_rank: Super Contributor
timestamp: July 02, 2017, 01:07:47 am
content: Two outputs connected together with opposite value is what can cause a glitch. This could be a hell to debug back when people still used simple logic gates on large numbers. Why would you intentionally create this?If you somehow must do this, include series resistors for both outputs to limit the current to some sensible level.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 01:13:07 am
content: Because the maximum output/input currents in my IC's are 20mA, so where could the problem be ?

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 01:16:36 am
content: Quote from: PauloConstantino on July 02, 2017, 01:13:07 amWhen the datasheet says MAXIMUM output current.It means the MINIMUM current that it is guaranteed to produce. It can and probably will allow MORE than that to flow.Some chips datasheets, allow one output to be shorted to a power rail.Analogy:If I said you can borrow a MAXIMUM of £20 from me.It means that you can borrow between £0 and £20.BUT I may have a lot more money on me. E.g. £100.So me saying a MAXIMUM of £20 to lend to you, does NOT mean if I am robbed, I only lose £20. I would actually lose £100.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 01:18:30 am
content: Quote from: MK14 on July 02, 2017, 01:16:36 amLook, how can MAXIMUM mean MINIMUM? Are you ok lad?It's the MAX output current not the MINIMUM.I am looking at the ABSOLUTE MAXIMUM RATINGS.Ok mate ?

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 01:19:31 am
content: Quote from: PauloConstantino on July 02, 2017, 01:18:30 amYou have got it the WRONG way round. Sorry.They mean the MAXIMUM safe value. In practice a lot more current can flow if there is a short circuit.

author: Rerouter
author_rank: Super Contributor
timestamp: July 02, 2017, 01:21:19 am
content: That is the maximum you can feed in to / out of those pins without damaging then, it is not the short circuit current which can be much higher,a mosfet push pull stage may appear as 1 ohm to voltage rail when switched on, now on a 5V device that will be way more than that 20mA limit. and puff goes some piece of siliconIf you wish to have the 2 connected fit a resistor inbetween the 2 so that should they output opposite signals it is still within this limit. e,g, for a 5V device you would fit a 470 ohm resistor between the 2 pins, this limits both to a maximum fault current of 10ma (Its unwise to live on the maximum ratings), and both pins should remain safe.

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 01:21:48 am
content: A MOTORWAY has an ABSOLUTE MAXIMUM speed limit of 70 MPH, in the UK.BUT, you can drive at 200 MPH if you want (to lose your driving licence).

author: sokoloff
author_rank: Super Contributor
timestamp: July 02, 2017, 01:25:11 am
content: Quote from: PauloConstantino on July 02, 2017, 01:18:30 amMK14 has it right. The datasheet is telling you that you can rely on sourcing (or sinking) that amount of current without damage to the chip or misbehavior of the circuit.It is not telling you that if you tie that pin to ground via a multimeter set on Amperes (so a direct short) and drive it high that the meter will read 20mA (as if the pin were a constant current supply).

author: Rerouter
author_rank: Super Contributor
timestamp: July 02, 2017, 01:27:58 am
content: To try and clear things up, a logic IC has powerful mosfet switches to ensure a fast transistion time. but very thin bond wire because your not expected to have high currents except for at those transitions. if you constantly pull a large amount of current through them you can damage those bond wires, this is what sets the maximumSo while the mosfets may be able to switch 2A, the wire will melt if much more than 20mA flows through it

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 01:30:29 am
content: Quote from: sokoloff on July 02, 2017, 01:25:11 amSo what parameter defines the maximum current an IC can provide then mate?

author: sokoloff
author_rank: Super Contributor
timestamp: July 02, 2017, 01:32:20 am
content: Take two deep breaths and read rerouter's explanation.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 01:33:59 am
content: Ok I was wrong. I thought the maximum ratings were the most current the IC could provide. Apologies and thanks for correcting me.So what defines the maximum current possible?

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 01:36:32 am
content: Quote from: PauloConstantino on July 02, 2017, 01:30:29 amIf you buy a battery, and it says on it 6V at a maximum of 1 Amp.It means it provides 6V, and you can use up to 1 Amp from it. Safely WITHOUT it overheating or something.But if you short-circuit it. Massively more than 1 Amp may flow. E.g. 8.5 Amps.If the Battery datasheet says Absolute Maximum Current (taken out of) battery is 1 Amp.It does NOT mean it can NEVER give more than 1 Amp if short-circuited.I.e. It can take up to 1 Amp, WITHOUT damaging it.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 01:37:17 am
content: I agree it's the maximum allowable current before damage, but it's nothing to do with MINIMUM !!! MK has brought this minimum business up. There's no minimum here. It's maximum allowable current before malfunction.

author: sokoloff
author_rank: Super Contributor
timestamp: July 02, 2017, 01:42:03 am
content: Quote from: PauloConstantino on July 02, 2017, 01:37:17 amNo, it's the minimum that any given chip (with the inherent manufacturing tolerances) can supply without damage. Some chips will necessarily be able to supply more than that without damage, but the manufacturer does not claim that.It's like a tire speed rating. The tire speed rating is a safety rating. It does not guarantee that your H rated tire will come apart at 131 mph. It merely guarantees that the worst H rated tire will be safe at 130 mph. That is the sense in which it is a minimum rating.

author: Rerouter
author_rank: Super Contributor
timestamp: July 02, 2017, 01:42:36 am
content: Ok, defining how much the internal switch can actually handle. for that look at the output low and output high specs at a few mAe.g.https://assets.nexperia.com/documents/data-sheet/74HC_HCT08.pdfBottom of page 4,So for a 6V supply, the typical switch resistance is in the ballpark of 50 ohms (thats something i will remember next time i go high speed),(6V - Out High (5.81V)) / 4mA load = 47.5 ohms, so as a hard short it should be able to sink 126mA or atleast in that ballpark, and be dissipating 0.76W in that one output, which will not last long,

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 01:42:57 am
content: Quote from: MK14 on July 02, 2017, 01:36:32 amOK agree. But why did you bring up MINIMUM ratings? It is the minimum current at which it will break down, ok. But it's also the maximum before breakdown. So it's both the minimum and the maximum before breakdown. Why bother with minimum? You bright this up. There's no need to speak of minimums. It already says maximum. I think you were just trying to contradict me again.

author: sokoloff
author_rank: Super Contributor
timestamp: July 02, 2017, 01:47:21 am
content: Quote from: PauloConstantino on July 02, 2017, 01:42:57 amHe was trying to break through your confusion in this post:Quote from: PauloConstantino on July 02, 2017, 01:13:07 amYou were clearly confused (at that time) about what that spec meant, and MK14 was trying his best to help you understand that that rating was a design spec guaranteed minimum, not a maximum in the way you were understanding it.He brought up minimum in a genuine effort to try to help you. If you persist in your aggressive responses, the problem you're experiencing with people trying to help you may resolve itself.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 01:50:49 am
content: Quote from: sokoloff on July 02, 2017, 01:42:03 am"No, it's the minimum that any given chip (with the inherent manufacturing tolerances) can supply without damage. "No, the minimum it can supply without damage is 0.I think we are entering the domain of semantics here now. And deeply flawed logic.The minimum current the IC can source or sink without damage is 0.The minimum it can source or sink, (and if you go higher) damage will occur is 25mA (in this case).The maximum it can sink or source, after which damage will occur is 25mA.You guys are confusing the semantics and logic of minimum with that of maximum.Anyways, I'm done with this thread now thanks.

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 01:52:56 am
content: Quote from: PauloConstantino on July 02, 2017, 01:42:57 amI agree with you, in that I should NOT have mentioned minimums, as it could cause confusion.The reason I mentioned minimum, was as follows.Let's say a power transistor, is rated for up to 1 amp current. With an absolute MAXIMUM current of 1 amp.As regards the absolute maximum, it is a MAXIMUM of 1 Amp.But if you accidentally short circuit the transistor, a lot more than 1 amp, may flow from it.Hence that is why I said 1 Amp is the minimum short circuit current. What I really meant was that the 1 Amp was just the safe limit. But it could go a lot higher, if the transistor was short-circuited.Anyway, I should have refrained from calling it minimum, as it was making it too confusing. Sorry.

author: sokoloff
author_rank: Super Contributor
timestamp: July 02, 2017, 01:55:35 am
content: Quote from: PauloConstantino on July 02, 2017, 01:50:49 amYou're not the only one.

author: Rerouter
author_rank: Super Contributor
timestamp: July 02, 2017, 01:56:14 am
content: now with a better understanding of why the rating exists (power dissipation) you can generally run higher currents so long as you reduce your duty cycle, e.g. 40ma at 45% PWM. to keep your average current below that 20mA, again it comes down to what you are hoping to accomplish.

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 02:01:58 am
content: Anology:The UK council, may say that we can put out an ABSOLUTE MAXIMUM of two rubbish bags in the street, each week, and NOT get prosecuted or fined.But as a minimum we can put out at least two bags and a lot more. Maybe 100 bags of rubbish/trash.I.e. The absolute maximum, can be (in some cases) exceeded. It just might get you into trouble with a fine from a council, or the chip may malfunction or be damaged etc.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 02:02:35 am
content: but Back to the original topic,my question was about shorting two IC outputs together. In this case then, it won't be safe because the maximum currents are undefined apparently.In my circuits I prevent this from happening. I prevent them from contending, however, I could make the circuit faster if I removed the protection, hence why I wanted to know what happens.I thought that because the max output sourcing was 25mA, and the max out sinking was also 25mA, that this meant I could connect them together. But since this is just the max safe level, I really can't unless I put a resistor there.Oh well, pirates

author: Richard Crowley
author_rank: Super Contributor
timestamp: July 02, 2017, 02:02:59 am
content: Perhaps the big question many of us are wondering isWHYdo you "really want to do this"?There are open-collector gates which allow you to create a "wired-OR" node. If you stretch out that node, you can call it a "bus".https://en.wikipedia.org/wiki/Wired_logic_connectionAnd there are tri-state gates which allow outputs to take turns driving a node. But never more than one at a time.But WHY one would want to connect ANY two outputs together that may have different states is simply incomprehensible to me. If one gate says 1=high and the other says 0=low, how is that supposed to work? Are you creating some sort of self-destructive device of some kind?If this question was answered somewhere already, apologies. Perhaps someone can reply with a concise answer.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 02, 2017, 02:07:16 am
content: Quote from: MK14 on July 02, 2017, 02:01:58 amMK, you are confusing minimum with maximum again. As a minimum you can put out zero bags. Minimum is minimum. I think what you mean is that the minimum number of bags you can put out, more than which you get fined, is 2 bags. But then you don't need the word minimum. You use maximum for this. The maximum bags after which you get fined is 2.You use minimum to speak of lower boundaries, lower than which something (bad) happens. In this case we don't care about lower currents, we care about higher currents or bags, so we use maximum. Minimum has no bearance in this.But the plain, flat minimum you can put out is zero.

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 02:08:07 am
content: Quote from: PauloConstantino on July 02, 2017, 02:02:35 amYou have pretty much nailed it and got it EXACTLY right now!

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 02:15:42 am
content: Quote from: PauloConstantino on July 02, 2017, 02:07:16 amI now at least understand why I was confusing you. Minimum is often associated with the lowest value.The main issue is really about the short-circuited outputs. The fact that I mentioned "minimum", is really a side issue. Not all the words and phrases I choose, in quick forum posts, are necessarily the best or perfect.

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 02:24:49 am
content: Quote from: PauloConstantino on July 02, 2017, 02:07:16 amThe MINIMUM you can put out, is indeed, zero!BUT, if you ask me to OVERLOAD (i.e. like a short-circuited output) the street with rubbish bags.Because the limit is a maximum of two. We are probably safe to assume, that the lower limit of how many bags, we can squeeze into our street, is probably a MINIMUM of 2 (i.e. like starting from the absolute maximum current of 20 milliamps), but is a maximum of some unknown size, which is something like 100. If you measure the street, outside where a person lives and would dare to leave rubbish/trash bags out.i.e. How many bags can we put out, maximally in our street, ignoring rules. Is a minimum of 2 (since we are allowed that many) and a maximum of some much bigger number, which could be 100.EDIT: I definitely agree, that my starting point of the absolute maximum. May itself, sometimes be overly overoptimistic, and so the real minimum, may be lower or even zero. E.g. maybe there is only room for a single bag, or even no room for any bags, because there are too many parked cars outside, etc.I.e. My use of "minimum", was not such a good idea or 100% correct. On reflection.

author: Audioguru
author_rank: Super Contributor
timestamp: July 02, 2017, 03:55:12 am
content: Texas Instruments has graphs of minimum and typical output current from 74HCxx ICs and with a 5V supply the typical shorted output current is 48mA sinking and is 55mA sourcing. The current is higher when the 5V supply is a little higher and some ICs produce much more current than the typical amount shown.But the ICs have a maximum allowed output current of only 25mA.

author: MK14
author_rank: Super Contributor
timestamp: July 02, 2017, 04:01:12 am
content: Thanks, nice graphs.Those graphs being labeled with "expected minimum", is a similar concept to why I was going from "Absolute Maximum", to a minimum type of term.I'm surprised the currents are as low as that, e.g. 48 mA's.I suspect the fastest/strongest logic series, would be much higher currents than those. Such as 74AC etc. Especially buffer or driver versions.EDIT: Apparently, the short circuit current can be as high as 700 mA's (with a 5output impedance).E.g. With a SN74BCT25240, page 21http://www.ti.com/lit/an/sdya009c/sdya009c.pdf

author: alm
author_rank: Super Contributor
timestamp: July 02, 2017, 10:34:09 am
content: Well yes, that is a bus driver with an absolute maximum low state output current of 376 mA and a recommended low state output current of 188 mA. So clearly the short circuit current and output impedance would be lower. However, since they are in the same DIP/SOIC packages, I would expect them to overheat more quickly.

author: Delta
author_rank: Super Contributor
timestamp: July 02, 2017, 11:15:12 am
content: If one output is driving to 5v, and the other is driving to 0v, the result will some random voltage in between, and thus useless for driving a logic input.WTF would be the point of that? (That said, you are the type of person who chats with himself - see first two posts)

author: Gyro
author_rank: Super Contributor
timestamp: July 02, 2017, 11:50:07 am
content: Quote from: PauloConstantino on July 02, 2017, 02:02:35 amIf you are preventing the outputs from contending then there is something wierd with your logic. If both of your outputs will always be in the same state then one of them is redundant.

author: Fungus
author_rank: Super Contributor
timestamp: July 02, 2017, 01:21:04 pm
content: Quote from: PauloConstantino on July 02, 2017, 01:13:07 amThat's like saying "my car can rev to 7000RPM so where's the problem in driving around in first/second gear all day at 7000RPM with the needle on the red line? I'm driving within the car's specification, right?"(assume that gasoline is free).Question: Would you buy a second-hand car from somebody who drove it like that?

author: rstofer
author_rank: Super Contributor
timestamp: July 02, 2017, 04:59:14 pm
content: Quote from: Fungus on July 02, 2017, 01:21:04 pmBack in the day, we used to joke about selling off our cars after using them for drag racing. Only 5000 miles! Of course it was 1/4 mile at a time...Thevinin Equivalent Impedance...If the OP wants to know the output impedance of a logic gate, connect a resistor to ground, say 100 Ohms, and measure the voltage at logic 1 along with Vcc. Most of the voltage drop will be across the resistor but some will be across the internal impedance. Do some number crunching and you have the internal impedance.Turn the resistor around and connect it to Vcc. Repeat the number crunching when the gate output is logic 0.I'm not going to do the math but the 100 Ohm resistor could also be chosen to come a lot closer to the pin maximum current.

author: rstofer
author_rank: Super Contributor
timestamp: July 02, 2017, 08:48:29 pm
content: Quote from: rstofer on July 02, 2017, 04:59:14 pmThat 100 Ohm resistor may be too low depending on the device. Do the math first.

author: KL27x
author_rank: Super Contributor
timestamp: July 04, 2017, 04:31:29 am
content: I could be wrong, but I imagine the maximum output capability of a solid state device (as stated in the datasheet) may be limited by not only physical damage, but by what it can output and still maintain the defined voltage level for the logic levels as defined for that logic family and voltage.For instance, CMOS 5V and 3.3V logic high output might be defined as minimum of 2.4V. And output low might be defined as maximum of 0.5V. (For TTL, these levels are different. For 1.8V CMOS, obviously, the levels are different).If, due to the circuit designer's choices, the output current were to exceed this maximum, several things could happen, depending on what Vdd you are running at and/or what duty cycle (if output is switching intermittently). This might include damage to the device. Or just a saggy signal that doesn't meet spec, due to voltage drop across the output transistor and bond wire.If you shorted the two outputs together, BTW, you will most certainly have no ill effect if is very brief and low duty cycle. You might want to beef up the decoupling caps to prevent noise coming back onto the rail. And the voltage you get at the node while it happens is going to be anyone's guess. You'd have to measure it, if it mattered. You'd be making a resistor ladder with the output transistors of the two pins... and as things heat up, it may change. But I'd go so far as to say, the average logic chip or microcontroller can't instantly burn a pin. The output impedance is just too high. It would take a significantly long pulse to cause damage even tied directly to Vdd or Vss. IOW, the maxpulsecurrent can't be exceeded short of connecting to a voltage higher/lower than the supply (and if ESD diodes were not there). Connected to another output pin of similar impedance, it might take on the order of millisecond or seconds... it might even cause no damage, indefinitely (when done within specified temperatures, and considering 5V supply or lower). This is just guessing, of course. These things aren't available to look up in the datasheet.Maximum pulse power output will be when the load impedance matches the output transistor (and bondwire) resistance. Maximum pulse current may go higher, yet. But your voltage will be in the gutter at that point. At maximum pulse current, your output high might actually be a logic low. And vice versa.

author: SL4P
author_rank: Super Contributor
timestamp: July 04, 2017, 05:54:00 am
content: OPEN-COLLECTOR, or DIODE-OR can solve many problems.Schottkys will help reduce forward drop

author: AG6QR
author_rank: Frequent Contributor
timestamp: July 04, 2017, 06:05:07 am
content: The absolute maximum ratings on the datasheet aren't limits which the IC itself enforces based on some sort of internal protection circuitry. They are limits which, if exceeded, will destroy the device (maybe not always immediately, depending on how badly you violate the limits). It's a contract between the chip makers and you, which says:As long as you keep all values within the limits specified by "absolute maximum ratings", we guarantee the chip will perform its job as specified. But if you ever exceed one of those "absolute maximum ratings", you're on your own, and we suspect the part may stop functioning.If you want the IC to continue to work, then it's up to you, the circuit designer, to make sure that you don't allow the output to source or sink more than 20mA of current. The IC itself won't help you limit its output to 20mA, except in the sense that the IC is likely to destroy itself if you try an exceed that 20mAIf you hook the output of a logic gate to the output of another logic gate, and you allow the logic gates to be in opposite states, what have you done to limit the current? Nothing. You can bet that the current will exceed the absolute maximum rating and one or both devices will be destroyed.If you must wire two outputs together, then at least put an appropriate resistor between them to limit the current to the datasheet rating.

author: alm
author_rank: Super Contributor
timestamp: July 04, 2017, 12:35:44 pm
content: Actually, they will tell you to avoid exceeding the recommended specs for a long time. And just to be clear, the IC is not guaranteed to work while you operate it beyond its recommended specs but below its absolute maximum specs. It will likely not meet its VOHand VILspecs over the temperature range. It is just guaranteed to survive (for a while).

author: CopperCone
author_rank: Super Contributor
timestamp: July 04, 2017, 05:23:45 pm
content: Someone I know said that they used to do something like this on military electronics, to drive a motor on a aircraft "pod" (i.e. the thing under the wing with cameras that allow for target tracking/guidiance munitions).I believe it was for Lockheed Martin.They paralleled up a hex buffer (chip that had multiple gates).. said it was OK so long that you calculate the current limiting resistors., to limit output current from each device and prevent unequal sharing. Not much R though.I did not really think about this problem, a conversation just came to mind I had with someone a while back. I think the issue was that the devices will back feed each other due to different output impedance.Might actually be high reliability, as you don't have all that current going through one junction. Kind of inefficient though due to the losses in the resistors. I think there was a specific reason it was done.https://en.wikipedia.org/wiki/Targeting_podMight have been multiple chipsThings can get funny if you want reliable/weird specifications. Also fun to build and cool looking. Instead of the same old boring driver every time.Reading this thread is painful. I don't know why, but my brain keeps turning off. I'd like to blame the datasheet authors for being cryptic.

author: Zero999
author_rank: Super Contributor
timestamp: July 04, 2017, 05:54:47 pm
content: To answer the original question: it should be fineas long as you're 100% certain the outputs of the gates will always be the same. The trouble with this is each gate will be slightly different, even if they're on the same IC, so they won't all switch at exactly the same time. This will cause a higher current when changing state, than what's normally expected, but it shouldn't be too much of a problem at low speeds, as long as there's adequate supply decoupling. If the gates are all on the same IC, then the current sharing should be reasonable but still imperfect.

author: CopperCone
author_rank: Super Contributor
timestamp: July 04, 2017, 10:49:23 pm
content: Quote from: Hero999 on July 04, 2017, 05:54:47 pmyes, you need to do a source impedance analysis. You might need to add inductance/capacitance/resistance.This is a fun problem.

author: joeqsmith
author_rank: Super Contributor
timestamp: July 04, 2017, 10:59:46 pm
content: I used to own a RadioShack color computer with I think a 6809. RadioShack offered a technical reference manual for it. In that manual, I will never forget they had a warning about using peek or poke in certain areas being able to damage the computer. To save money, they had not fully decoded the bus.This computer had no UART but they offered a modem. Bit banged with assembler to get the timing tight enough for 300 BAUD?Then again, that has been many years ago. Could be wrong.

author: alm
author_rank: Super Contributor
timestamp: July 04, 2017, 11:18:55 pm
content: The TI "Designing with Logic" document, linked to several times in this thread including in the second post by the original poster, actually has a fairly detailed discussion of bus contention in section 7, including a thermal analysis.

author: Zero999
author_rank: Super Contributor
timestamp: July 05, 2017, 08:16:51 am
content: Quote from: alm on July 04, 2017, 11:18:55 pmBut we don't know that's what the original poster is dealing with.It seems more like he's talking about connecting two outputs in parallel to power a device such as a buzzer or bright LED, rather than using a discrete transistor. This may be fine for logic gates, such as the 74HC14, as long as the inputs are hard wired together but may cause smoke in an MCU, during start up or in the case of a software fault. I don't know about FPGAs or CPLDs though.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 05, 2017, 10:16:01 am
content: Quote from: Gyro on July 02, 2017, 11:50:07 amHave you ever heard of something called a bus ? Probably not. So let me explain it to you.... in a bus, multiple outputs are connected together, and only one of them is active at a time. So you prevent them from contending and having two of them output at the same time. Hence why I "prevent" them from contending.There's a short period in buses when outputs might contend, since one if being switched on and the other off, there's some intersection unless you prevent it. I prevent it by adding a wait state so that both are off for 1 clock cycle. Which is a slow solution. If I remove this solution then the circuit becomes faster (no wait state), but then they might contend for a few nanoseconds. Hence my original question.

author: capt bullshot
author_rank: Super Contributor
timestamp: July 05, 2017, 10:42:30 am
content: I guess, this thread would have been a single pager with one or two replies if you'd stated this in our original postYes, it's quite normal to have short overlapping of the driving pins in a bus system, it doesn't harm the ICs because of the short duration, but it may cause all kinds of EMC related problems due to the high current spikes. Just go and test it.

author: EEVblog
author_rank: Unknown
timestamp: July 05, 2017, 10:51:34 am
content: Quote from: PauloConstantino on July 02, 2017, 02:02:35 amCorrect.Actually, they aren't entirely undefined, you can kinda guestimate the output MOSFET resistance based on the different Vol and Voh values at different output currents. But it's not going to be linear.QuoteIf you are preventing them from contending then that's fine, you can tie the output, and in fact thatis common practice to get more output current capability. e.g. putting two or more inverters in a 74HC04 package in parallel in order to get more output drive. This is even shown in many datasheets.QuotePutting outputs in parallel do a pretty good job at current sharing, you don't need current sharing resistors.Just be aware that there also a maximum total sluppy current that comes into play.e.g. if you have 6 x 25mA outputs in parallel and your maximum power pin current is 100mA, 100mA is the maximum you should draw.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 05, 2017, 10:53:36 am
content: Yes i'm not talking about parallelling the same kinds of gates to generate a higher current. I was talking about bus contention...However this has generated interesting responses.I think given the inductances and capacitances of the traces, it might or might not damage the IC's. It would depend on the impedances of the traces and the actual period of time the IC's are contending. Who knows

author: EEVblog
author_rank: Unknown
timestamp: July 05, 2017, 10:53:41 am
content: Quote from: PauloConstantino on July 05, 2017, 10:16:01 amThat is called tri-stating outputs and is an entirely different thing to what has been discussed here because you failed to mention tri-state at all.

author: EEVblog
author_rank: Unknown
timestamp: July 05, 2017, 10:58:38 am
content: Quote from: PauloConstantino on July 05, 2017, 10:53:36 amhttp://www.ti.com/lit/an/sdya009c/sdya009c.pdfPage 19

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 05, 2017, 11:01:26 am
content: Quote from: EEVblog on July 05, 2017, 10:51:34 amFantastic! Not everyday you have Dave answering your threadsThanks Dave. They were thinking I was talking about paralleling gates to generate more current but I was actually talking about bus contending...I'd like to know what are the factors that come into play if you have outputs going into the same bus "bit". How likely they are to contend... And I've been thinking it depends on the impedances of the lines as it takes a while for the currents to get going, and also on the actual period the outputs are contending... What would be a good way of determining the likelihood of damage...If I have a few control signals which tell each output whether to output or not, then if we consider the delays of the traces carrying these control signals, then the difference in (delay between the two IC's plus the propagation delays of each IC) will be equal to the amount of time they are contending in the bus... But then we need to also consider the impedances of the traces from the outputs of each gate to the bus...What do you think the best solution is Dave?

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 05, 2017, 11:03:48 am
content: Quote from: EEVblog on July 05, 2017, 10:53:41 amYes I guess I failed at that Dave mate. I wanted to focus the attention to the actual contending of the two outputs rather than tri-stating principles. Because once the IC's are contending, tri-stating doesn't come into play. But I have mentioned it finally.

author: helius
author_rank: Super Contributor
timestamp: July 05, 2017, 11:33:29 am
content: There are two basic ways of preventing electrical contention (where one driver pulls a wire high at the same time another is pulling it low).The first is a static method that ORs together all the drivers on the bus. Each driver is open-collector output, with a pull-up resistor at the end of the bus. Since each driver only pulls low for 0 and is high-Z for 1, the short circuit condition can never occur.In the second method, the output enables of the bus drivers are gated by a signal that this particular driver has exclusive access to the bus. The protocol to select which driver has access is called arbitration. As long as every driver on the bus satisfies the protocol, it will never occur that more than one tries to drive the bus at any particular time.Real systems use a combination of both methods, for example the arbitration protocol may use open-collector signals. This is all treated by basic computer design texts.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 05, 2017, 12:42:30 pm
content: Quote from: helius on July 05, 2017, 11:33:29 amHowdy.Bus arbitration is used on external buses. Have you seen it used internally in a CPU's data bus? That's where I am concerned. Firstly most IC's don't have open drains or collectors, second it would be rather slow to have an internal protocol for a CPU's internal databus.Anyways bus arbitration is a good concept, but I've not seen it used inside a CPU's internal databus. if you have I'd like to know.

author: Rerouter
author_rank: Super Contributor
timestamp: July 05, 2017, 01:00:36 pm
content: It comes down to the data rates your after, Canbus is an example of a bus that can handle multiple devices outputting at the same time, and can handle data rates over 1Mbit at a few meters distance.If your looking more at an older CPU with address decoding for a bus, then in general there is 1 master, and peripherals on the bus that are used to talk to other things, so the cpu master would select a new address, the decoder would disable the old device, and enable the new, the master would wait a number of cycles then change the bus from tristate to active and communicate with that peripheral.Even if you had a secondary processor it was generally slaved to the master, you see the same occuring in modern MCU's, they may have multiple independant DMA channels, controlled by a DMA controller, but the master processor configures the dma peripheral then hands off that connection to it, Its still acting under the master, even if its a seperate peripheral now controlling the bus, the processor waits until the peripheral returns a completion state, then retakes control.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 05, 2017, 03:36:30 pm
content: Quote from: Rerouter on July 05, 2017, 01:00:36 pmMaaaate I mean the internal cpu data buses m8. The buses where internal registers output to m8.

author: Gyro
author_rank: Super Contributor
timestamp: July 05, 2017, 04:07:21 pm
content: Quote from: PauloConstantino on July 05, 2017, 12:42:30 pmYou won't find any contending gate outputs inside an IC either.I still can't understand what you're trying to achieve. Contending gate outputs will produce an invalid (unuseable) logic level regardless of the possible damage. You say that the gate outputs won't contend but if they always output the same state, then something is redundant. The only other reason for paralleling outputs in the same state to achieve increased current drive (as Dave mentioned) but you say you're not doing that either.What is it that you're actually trying to achieve?EDIT: Scrub that - I see that you are worried about transient contention on state changes (yes or no?). In that case you will need to look at how whetever you are driving will handle the indeterminate logic levels, unless it is clocked downstream.

author: Fungus
author_rank: Super Contributor
timestamp: July 05, 2017, 04:12:57 pm
content: Quote from: Gyro on July 05, 2017, 04:07:21 pmYep. What are you expecting to see on the output? It can't possibly be anything useful.

author: helius
author_rank: Super Contributor
timestamp: July 05, 2017, 04:51:19 pm
content: Quote from: PauloConstantino on July 05, 2017, 12:42:30 pmIn a simple CPU, there is a single sequencer that controls every other component. So it's not like the situation with several I/O cards that need arbitration to decide who will be master; the CPU sequencer is always the master. The timing diagram will be designed so that the sequencer disables the previous output to a bus on one cycle, and enables the new output on a later cycle, preventing both from driving it at once. This is critical because the internal gates are not latchup protected! Making sure that these timing constraints are maintained through voltage and frequency variations is extremely important and will be fully simulated. Each full cycle is usually split into several phases to make this sequencing easier.In more complex multi-core processors it's more common to use crossbars and unidirectional links, rather than busses, to avoid the turnaround time when the bus must be inactive.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 05, 2017, 05:53:48 pm
content: Quote from: Gyro on July 05, 2017, 04:07:21 pm

author: Gyro
author_rank: Super Contributor
timestamp: July 05, 2017, 06:12:48 pm
content: Quote from: PauloConstantino on July 05, 2017, 05:53:48 pmWhat is it that you are trying to achieve?Is your problem transient contention in asynchronous logic? Yes or no?If not, then what?Are the outputs tristate logic or not? it doesn't seem clear from your previous replies.

author: KL27x
author_rank: Super Contributor
timestamp: July 05, 2017, 06:36:48 pm
content: QuoteAll microcontrollers have as many potentially open-drain outputs as they have tristate IO pins. Some even have their own pullups.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 05, 2017, 07:50:39 pm
content: Quote from: Gyro on July 05, 2017, 06:12:48 pmI have an internal CPU data bus (I've built a cpu from scratchy), which has various registers outputs connected to it. At each clock cycle one of them at most is outputting into this bus. I prevent them from being active at the same time even for a few nanoseconds by having a null state where no output is active at all, after which one of them will be active, but this eats up 1 whole CPU clock cycle, which at 5MHz is not much but still adds up.I was thinking if I would be able to remove the wait state, if the overlapping period is in the tenths of a nanosecond or something, because wire impedances might just delay it so that the outputs never really contend..... do you know?

author: Gyro
author_rank: Super Contributor
timestamp: July 05, 2017, 08:04:12 pm
content: So the outputs onto this CPU data bus are tristate outputs, not ordinary gates? (I think most of had the understanding that you were talking about ordinary gates, NAND NOR , whatever).If they are tristate and you know that the overlap is really in the order of a nanosecond then there shouldn't be a problem at all. I think all CMOS ICs (did you say what logic family?) draw a supply current spike as their output FETs change state anyway.It would help if you say exactly what device part number(s) these outputs are from.EDIT:To save time...If it is a tristate bus constructed using breadboards and wires (as your Homebrew CPU thread), your biggest problem will be ringing and ground bounce, not contention. Any contention might make the ringing worse though. You may be able to improve this by adding low value resistors in series with each output maybe 47 - 100R (nothing to do with current limiting, just to damp the ringing).Of course you will need to leave enough time for the bus lines to settle before reading them with another input, but that is not a device safety issue.

author: C
author_rank: Super Contributor
timestamp: July 05, 2017, 08:47:43 pm
content: All logic has an output type.With Tri-state logic output you enable only one output at a time.You have some Tri-state time when changing outputs.With Open Collector logic you can enable as many outputs as you want. Logic can only create a Low level with resistor pull up creating the high level.With standard logic you connect one output to one or more inputs of another gate.If you have outputs then you use a data selector like 74HC157 to pick the one you want.

author: KL27x
author_rank: Super Contributor
timestamp: July 05, 2017, 09:32:42 pm
content: To add to that, some logic chips might have digital hi/lo output only. But many, many IC's come with open drain output variants. And if they don't, there are a host of buffer/inverter/gate/logic and other generic chips (which while not specifically made to do the job, will do it) that can be used to convert the signal to open drain. If you want to get primitive, you can use descrete transistors and pullup/downs. This is a common need for such problem as you have, plus for voltage translation and probably other things I haven't even considered, yet.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 05, 2017, 09:36:17 pm
content: Last two posts are most useful!Both using multiplexers and open drain buffers are great and neat solutions to this problem.Appreciated!

author: CopperCone
author_rank: Super Contributor
timestamp: July 05, 2017, 09:56:24 pm
content: i think you would like quantum computing

author: C
author_rank: Super Contributor
timestamp: July 05, 2017, 09:57:08 pm
content: There are also data switches that can act like a multiplexers.Might I suggest that when working with logic very few problems remain.You should look for a chip or chips that solves the problem.As others have said it would have been much quicker if you had said," I Need to connect the outputs of these chips based on time"With chip numbers you would have gotten a good answer much quicker.

author: bson
author_rank: Unknown
timestamp: July 05, 2017, 10:46:07 pm
content: Quote from: PauloConstantino on July 02, 2017, 01:33:59 amThe maximum current possible is determined by the Rds(on) of the output transistor and the supply voltage. At 5V and a max safe current of 20mA, this means if Rds(on) is < 5/0.020, or less than 250ohm then it's possible to exceed the safe maximum. The output impedance of most logic is typically in the tens of ohm, with some parts getting up to 100ohm, so two shorted outputs will range from greatly exceeding to slightly exceeding the maximum rated output current.

author: Fungus
author_rank: Super Contributor
timestamp: July 06, 2017, 03:05:57 am
content: Quote from: PauloConstantino on July 05, 2017, 07:50:39 pmThat's what 74LS151 is for.

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 06, 2017, 06:42:36 am
content: Quote from: CopperCone on July 05, 2017, 09:56:24 pmlol yes I do

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 06, 2017, 06:43:51 am
content: Quote from: Fungus on July 06, 2017, 03:05:57 amThat's what 244's are for too

author: PauloConstantino
author_rank: Regular Contributor
timestamp: July 06, 2017, 06:45:21 am
content: Quote from: C on July 05, 2017, 09:57:08 pmSome people want it to be quick, some want it to be slow as they learn more