Is via stitching ever a bad idea? - Page 1
Forum section: electronics / projects

author: matthuszagh
author_rank: Frequent Contributor
timestamp: February 27, 2023, 06:48:33 pm
content: Are there any downsides to via stitching, aside from potentially cost? To put this into context, I have a 4-layer board. The top and bottom layers are signal layers and the 2 internal layers are full ground planes. I don't absolutely need via stitching, but I wanted to add a coplanar ground fill on the signal layers to add some heatsinking to a few voltage regulators (they'd probably be ok without it) and to increase isolation between adjacent traces. Of course I don't want to leave copper islands so I stitched the whole thing with 1mm-spaced vias. I think this might be unnecessary (though I'd like as much trace isolation as possible as this is quite a low noise design), but aside from it maybe being unnecessary, is there a chance it's actually bad?I've added pictures of the layout too, to make this a bit more concrete. I'm interested in this question in general though, not simply as it relates to this particular case.

author: KE5FX
author_rank: Super Contributor
timestamp: February 27, 2023, 07:07:19 pm
content: In a microwave design, a regular grid of vias may act like a resonant structure at an inconvenient frequency. Some designers will randomize the vias' locations for that reason.Otherwise, I like to add vias until the board house screams. Then add one more just to show them who's boss.The 53100A's ADC board has about 2800 vias.

author: bson
author_rank: Unknown
timestamp: February 27, 2023, 07:36:54 pm
content: Unless they're blind or hidden, vias will create routing obstacles in other unrelated layers.

author: ataradov
author_rank: Super Contributor
timestamp: February 27, 2023, 07:40:30 pm
content: It is a good idea generally, at the same time this is excessive and unnecessary. You are pushing your luck with board manufacturers for no reason. At some point they will start charging you for extra for the vias.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 27, 2023, 08:12:42 pm
content: Quote from: bson on February 27, 2023, 07:36:54 pmYep. That's the real compromise you have to make.Also, for very high-frequency designs, as via stitching is mainly done with ground planes, too many vias may end up making your power (not ground) planes look like emmental cheese - those "cutouts" may give some issues.So, it's all a matter of being reasonable.

author: matthuszagh
author_rank: Frequent Contributor
timestamp: February 27, 2023, 10:30:09 pm
content: Quote from: bson on February 27, 2023, 07:36:54 pmOh sure, but I don’t add stitching vias until everything is routed. It’s the last step. And if I need to reroute anything I delete all stitching vias, change routing as needed and then add them back. This is easy to do in kicad.

author: MathWizard
author_rank: Super Contributor
timestamp: February 28, 2023, 07:58:22 am
content: If you blew air through a wind box, with a bunch of pillars in it, you could make some vector fields for the air motions. So like Bernoulli's principle and whatever else.How much of any of that, works for electrons ? Like would an average flow of electrons moving around some via, look like air flow wrapping around and sticking to a pillar ?

author: Rerouter
author_rank: Super Contributor
timestamp: February 28, 2023, 08:16:04 am
content: Unless I'm dipping into RF, I usually just do a pass to make sure anywhere a fast signal or power rail changes a layer, there is some ground vias as close as reasonable to let the return current stay nearby, this is always one of my early passes when going through the DRC rules,Any other vias on the board are more precautions and to prevent large floating islands on other layers, most of this I will resolve with just nudging traces, but vias are usually required and not a bad habit to have (unless your in RF where it may matter)I have also used via cages like this around high noise signals or very high impedance sensitive nodes, e.g. a 10A servo motors power traces, sharing a board with some analog amplifiers, the power traces where caged to contain all the stuff it was spewing out until it got to the shielded cable running to the servo, and I did lay it on thick, luckily under testing it more than contained the noise to the level required, and the sensitive nodes ended up not caring even when I put the whole board in a swept frequency demagnetizer (there where other mitigations in place, but it did make a difference compared to earlier prototypes)If you put way too many vias on, eventually the fab may contact you asking for more details, but a grid like that, its unlikely to ever face an issue, your just trading routing space, and if its something your doing when most of the major routing is already in place, then its less of an issue

author: paulca
author_rank: Super Contributor
timestamp: February 28, 2023, 02:55:47 pm
content: Sorry to thread piggy back, but I was literally going to ask the same question, for slightly different reasons.I was working with an idea to have a top and bottom layer ground plane (2 layer), and maintain a ground between signal traces on the top layer... then stitch all the islands together to wrap the noisey digital signals in as much ground as I can.In terms of a score on the below what would you give it?Excessive:Pointless:Useful:

author: Siwastaja
author_rank: Super Contributor
timestamp: February 28, 2023, 02:58:51 pm
content: paulca, with a quick glance, that's 5/5. To the point, with the right idea, and not excessive.Most important is to stitch near the signal vias so that return path can follow the trace as close as possible. Elsewhere, a via for every inch or so as you have done (this is assuming no super fast edges).Edit: maybe add a few, to right of the R6, R5, R7, next to the pin header pins for completeness. But nah, it's good enough anyway.

author: ataradov
author_rank: Super Contributor
timestamp: February 28, 2023, 04:52:54 pm
content: Yep, this is exactly what I do. No need to flood the board with vias. All interrupted ground planes are connected and this is good enough.

author: paulca
author_rank: Super Contributor
timestamp: February 28, 2023, 06:54:20 pm
content: Quote from: Siwastaja on February 28, 2023, 02:58:51 pmIt's digital audio, so a handful to a few dozen mega-hertz. The later laid out first, but couldn't avoid a cross, aww well. I have taken an untested move to add 37Ohm (or similar) resistors on every digital output. The idea being to damp reflections / inductive ringing. I need clean voltage signals, I don't need current spikes. Some of the modules already include series resistors, of varying sizes, but the worst cause I can put 0Ohm links in if they don't work.Sorry for the user-drawings of all the mechanicals and no, I have not dealt with the silk screen or dotted any Ts nor crossed any Is.... oh wait... well it is a first prototype, I expect at least ONE "ooops."

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 28, 2023, 07:50:19 pm
content: paulca's example shows how to do it!A grid doesn't really hurt in terms of performance (just for fab), but it's suboptimal in terms of value per via. So, if you consider that unsatisfactory: try to prioritize crossings, long spans, peninsulas, and component pads. Pay attention to the negative space left in the pours by traces/etc.; follow the loops around those voids and try to keep them short.Which is the one thing auto-generated vias often do poorly at, prioritizing locations. Notice the negative space in the via grid itself, the gaps left by avoiding other features. That's more distance from traces or components, more inductance between them -- giving poorer grounds for components, and more coupling between traces, and weird sneak paths between crossing traces and the loops left in the plane.The minor critique I would give is, the traces probably don't need ground shielding inbetween them and can be grouped into buses, saving a few vias that way. (I wouldn't bother to change it; it's not like there's any space you need to save here.) And, J8-17 crosses three traces with three vias, two of which could be saved by swapping layers. Maybe that messes up the ground fill around J8 (there's lots of top-side traces connecting and crossing by it), would have to inspect closer. A few vias can also be added towards the edges, corners, or open spaces, just to help break up possible resonant modes over the long spans. Hardly matters at lower frequencies, though it's still a minor improvement in plane-to-plane impedance I suppose.Tim

author: dobsonr741
author_rank: Frequent Contributor
timestamp: February 28, 2023, 08:06:33 pm
content: QuoteWould be nice to state what qualifies as lower/higher frequency.Also, if matthiluszag can tell the frequency range the work is intended for.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 28, 2023, 08:09:46 pm
content: Quote from: matthuszagh on February 27, 2023, 10:30:09 pmWell, to illustrate my answer, your posted layout is IMHO one example of not being reasonable with via stitching. It's even surprising you could fit that many in between existing traces, but if so, they must be pretty much filling all remaining space. That's uh, a bit too much.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 28, 2023, 09:25:21 pm
content: Quote from: dobsonr741 on February 28, 2023, 08:06:33 pmAs always, "depends".Ballpark impedances are 50-120 ohms transmission line (TL) impedance for traces on board, inductances ~1nH/mm of component body/pin/trace length, and, whatever that does with respect to impedances in circuit.More often inductances matter, but capacitances matter as well. A TL looks inductive when operated at low frequencies (<< λ/4) and at low impedances (system impedance Zs < Zo). Conversely it looks capacitive for Zs > Zo.Typical signal purposes, the impedances should be comparable to TL impedance, and signal quality will be fine. For example, CMOS output pins are typically in the 30-70 ohm range, so aren't a bad match to traces, or with a little source termination (a small resistor say 22-47 ohms placed adjacent to, and in series with, the output pin). (You can always use more source termination to slow the risetime of the signal, when full bandwidth is not required.)At low frequencies (audio, say?), impedances can be quite different from Zo, matching is ~irrelevant on board scales, and we can save quite a bit of power running higher impedances. So, audio op-amps are well suited to sources/loads in the ~kohm range.Of course, that changes over very long lengths (again, wavelengths matter here), for example POTS pairs are closer to 600 ohms (that's where that audio standard comes from, more or less), which happens when you've got many ~km of twisted pair, at low frequencies where the line's resistance doesn't quite dominate over TL effects.Whereas at high frequencies, you take the nominal Zo value, like the 100 ohms of Ethernet pairs, or the 50/75 ohms (or whatever else) of coax.At low impedances, wide connections (or pours) are preferred because inductance is inversely proportional to width (specifically, L = length * height * mu_0 / width for geometries where fringing fields can be ignored, like very wide parallel-plate or microstrip lines). This is why very short and wide connections are preferred for SMPS, where while the switching frequency might be say 100s kHz, the harmonics go up to 100MHz or more, meanwhile the impedances are often single ohms.Indeed, as frequencies go up and voltages go down, like say for a CPU Vcore supply (among other reasons), you can only go so high in power level for a given layout area before the strays cost you too much switching loss (or reduction of SOA, or EMI). Instead, multiple phases should be used, which can also be phase-shifted to cancel out some ripple current between them, much as cylinders of an engine are used. This makes the controls more complex (more channels to balance currents, sequence phases, and drive transistors), but ever wider ICs are available for support.Multiphase is a bit of a PITA if you find an application for which a controller isn't available, but still, using 2-3 phases isn't too bad, as far as hardware you have to provide yourself versus the improvement over a single channel.Tim

author: KE5FX
author_rank: Super Contributor
timestamp: February 28, 2023, 09:42:21 pm
content: Quote from: T3sl4co1l on February 28, 2023, 07:50:19 pmIt's an example of how to create a bunch of random patch antennas (which is likely fine for this particular case). But if that's not what you're going for, I don't know that I'd agree.At a minimum there should be a couple of vias along each edge.

author: Siwastaja
author_rank: Super Contributor
timestamp: March 01, 2023, 06:56:05 am
content: Board edge vias are indeed missing from paulca's example. Attached is an example what happens when you forget to add edge vias on one area and submit the design for EM resonant mode simulation.In real life, if there is no energy source, then it does not matter. As vias cost next to nothing, it's still a good idea to fence the board edges; works for both emissions and immunity.

author: Psi
author_rank: Super Contributor
timestamp: March 01, 2023, 09:48:33 am
content: I guess you have too many via's when your board snaps in half like a panel route tab/mouse bite.

author: paulca
author_rank: Super Contributor
timestamp: March 01, 2023, 10:38:00 am
content: Quote from: Siwastaja on March 01, 2023, 06:56:05 amNoted.I like to "see" current in my head like water flowing around the board. Like if your board was scaled up to the size of a rather shallow swimming pool, your in rush is what happens when you tip a large bucket of water in at one end. All edges, walls, channels, etc will reflect waves which will interact. I know the analogy breaks down, as current behaves more as if the bottom of the pool was flexible, current will try and follow the most direct path, but spread/radiate out around the edges of that path to eventually fill the copper area and depending on the strength of the current, bounce back off the boundaries. Those reflections/bounces will make it back to the main current flow and "jostle" it a bit creating adverse "noise".Maybe going too far, but the edge vias could behave like breakwaters to break up the waves.I got the water flowing around the board analogy by watching a simulation of welding current when spot welding a tag onto one corner or a metal sheet while the ground clamp was on the other. Quite interesting to watch.As with all analogies it's full of holes (or vias)