PWR_FLAG - always required? - Page 1
Forum section: electronics / general

author: fivefish
author_rank: Frequent Contributor
timestamp: September 04, 2015, 03:38:06 pm
content: New Kicad user here... trying to play with this thing.Questions:Do I always have to attach a PWR_FLAG to my Vcc pins to avoid ERC warnings? The ERC on KiCad seems to be very whiny (compared to Eagle).How do I name netnames in the schematic editor? in Eagle, I can name a wire GND, and that particular net will automatically be connected to GND/Gnd plane when I do a PCB design later on. Or I can name a wire "input", or "feedback" so later on during PCB design, I can see the wire's purpose. How do I do this in KiCad?This particular warning always comes up... on power lines, input and output lines. "pin connected to some other pins but no pin to drive it"Now, for unused pins and input and output lines, I can put an "X" to it, to stop the warning. But what about on power lines? The PWR_FLAG? Why do I need to add another symbol to the power lines? What significance does this do? I may not be getting the big picture/philosophy behind Kicad yet.Thanks all.

author: Bassman59
author_rank: Super Contributor
timestamp: September 04, 2015, 05:37:42 pm
content: I reordered your questions a bit ...Quote from: fivefish on September 04, 2015, 03:38:06 pmIt depends. If the VCC pins on your ICs are connected to a net driven by a regulator's power OUTPUT pin, then no, you don't, because that regulator's pin is obviously the power net driver.But if your power source is from an off-board thing through a connector, and the connector's "power" pin is declared as passive (which is common), then your ICs' power input pins have no power driver so you need to put the PWR_FLAG on that power net so the ERC "knows" that the net has a power driver.The PWR_FLAG is separate from the usual power symbols in that its lone pin is declared as a power OUTPUT.(Why do the other power symbols such as VCC have their pins declared as power INPUTs? Simple -- so you don't get the conflict of having a regulator OUTPUT pin connected to a power OUTPUT pin. The point of the power symbols is to make global nets with standard names.)Another use case for the PWR_FLAG is if you've got a DC-DC converter on your board. The switcher chip doesn't have a power output pin, so no power net is defined by the chip. Instead, the power output is after a diode, perhaps. So whatever net you might consider the rail in that case needs to get a power flag attached to it. The ERC will be happy.QuoteLook at the EESchema window. On the right-hand side you should see a vertical toolbar. One of the icons is the letter A above a green line. (Place your mouse cursor over it and read the tool tip.) That's the "place local net label" command. (This is different from the "place global net label" command, which is right below the local one.)-a

author: fivefish
author_rank: Frequent Contributor
timestamp: September 04, 2015, 06:17:28 pm
content: Thanks bassman. Okay, I can see the usefullness of the PWR_FLAG.QuoteMaybe I'm using this tool wrong. It seems to be just adding a "text label" and I can place the resulting text anywhere on the schematic page. It doesn't seem to be actually labeling the green wire.In this case, I gave it a label of GND, but I can't query the wire to see what it's label is. I can issue another label command and give it a label of XYZ and point to the same wire and it's happy to accept it as is. I'm obviously missing something here.In Eagle, I can query the netname of a wire and see what it is. Is there a similar thing in KiCad?

author: Bassman59
author_rank: Super Contributor
timestamp: September 04, 2015, 06:32:55 pm
content: Quote from: fivefish on September 04, 2015, 06:17:28 pmIt's a text label, but look carefully at the attached picture. I want to add a net label "+19" to a wire. You'll see a square box in the lower-left of the text; that is the net label attachment point. For the label to work, that square has to be on the wire. A regular text block won't have that attachment point.As for the thing where you put two net labels on a net, I just did a test, and it's a problem. It seems that if you do that, eeschema is perfectly happy to accept it, and when the netlister runs, it doesn't throw any sort of warning or error. Instead, it gives the net the name which is lowest alphabetically. In other words, if you place the labels "foo" and "bar" on the net, the netlister chooses "bar" for the name put into the netlist for layout use.I will report that as a bug, or at least an annoyance that must be understood.QuoteUnfortunately, that capability doesn't exist in EESchema. I believe it's on the roadmap.When you generate the netlist and import it into PCBnew you'll see that the nets are labelled correctly.-a

author: fivefish
author_rank: Frequent Contributor
timestamp: September 04, 2015, 07:03:31 pm
content: Thank you bassman for taking the time to explain, I appreciate it very much.