Net "clk50" not found - only after adding extra "process" block (VHDL, Xilinx) - Page 1
Forum section: electronics / general

author: tom66
author_rank: Super Contributor
timestamp: February 14, 2015, 01:07:27 am
content: I'm a complete newb to FPGA VHDL, but decided to start playing with it... Was able to get a basic clock working (from example code, with a few modifications) but am having trouble with a new program.I'm having an issue. I'm using Xilinx ISE 13.1, and getting this error in stage "implement design":Code:ERROR:ConstraintSystem:59 - Constraint <NET "clk50" PERIOD = 50 MHz;>[clock.ucf(1)]: NET "clk50" not found. Please verify that:1. The specified design element actually exists in the original design.2. The specified object is spelled correctly in the constraint source file.Here is my VHDL:http://pastebin.com/JR6ZGw8iIf I comment out this line in the 2nd process:Code:led_ser_out1 <= led_base_clock ;and drive it directly from the currently non-functional process block with logic '0', I get the error. Otherwise, the code will work ok and generate a 2.5MHz square wave on the output 'led_ser_out1'.I can't see what would be causing this error? It doesn't directly involve the signal at all.I'm only using 3% of the floorspace on my XC3S200 FPGA (on a Spartan-3 Starter Kit board) so it's not like I'm running out of space any time soon.

author: oohal
author_rank: Newbie
timestamp: February 14, 2015, 04:52:49 am
content: Disappearing nets usually means the synthesis tool has founds some way of "optimising" the net out of your design. I noticed you haven't initialised led_base_clock anywhere, so at a guess the synthesis tool isn't quite sure how to deal with the situation and responds by tying led_ser_out1 straight to VCC or GND. After that all the logic that should have gone into generating led_ser_out1 isn't doing anything so it (and the clk50 net) gets binned. It's been a while since I've done FPGA stuff so I'm not 100% sure why moving the assignment out of that process block helps things.Try adding led_base_clock = '0'; to the reset handing logic and see if that fixes it.

author: miguelvp
author_rank: Super Contributor
timestamp: February 14, 2015, 06:05:45 am
content: clk50 is probably an input pin that needs to be placed in the pin planner and named that way. The manual of your dev board will tell you what pin has that input clock.But I've never used a Xilinx board yet (although I did get my papilio duo just last week but no time to set it up and try it)So I don't know if on the Xilinx IDE they refer to the pin association as the pin planner.

author: kony
author_rank: Regular Contributor
timestamp: February 14, 2015, 01:30:08 pm
content: Post also all user constraints (*.ucf) files associated with project.

author: Anand
author_rank: Contributor
timestamp: February 14, 2015, 03:10:49 pm
content: Your net is called "clk50in" not "clk50" in clock.ucf.

author: langwadt
author_rank: Super Contributor
timestamp: February 14, 2015, 04:56:06 pm
content: if the logic clocked by clk50 doesn't do anything that eventually result in a change on anoutput pin it gets optimized away and thus the clk50 not longer exist

author: tom66
author_rank: Super Contributor
timestamp: February 14, 2015, 06:24:41 pm
content: miguelvp and others were right, ISE was optimising them out. Simply driving an LED with CLK50 solved this issue as the complier could no longer optimise out that net.Thanks all.

author: Bassman59
author_rank: Super Contributor
timestamp: February 16, 2015, 07:30:12 pm
content: Quote from: tom66 on February 14, 2015, 01:07:27 ama) there is no need to instantiate input buffers, output buffers, or clock buffers. The tools are quite adept at inferring them when necessary. Use the UCF to set the IOSTANDARD.b) There is no need to put the translate_on/off pragmas around the unisim library-use clause.c) what are the signalslowandhighfor?