Cordic on verilog - Page 1
Forum section: electronics / general

author: den586
author_rank: Newbie
timestamp: October 12, 2023, 02:31:36 pm
content: Good time of day. Someone can share links or open sources to the Cordic algorithm on verilog, which would give out correctly SIN and COS depending on the incoming angle. I have modeled enough codes, and I have not found one whose output would coincide with the ideal SIN and COS within the limit of theoretical accuracy. Thank you in advance.

author: BrianHG
author_rank: Super Contributor
timestamp: October 12, 2023, 06:29:09 pm
content: Did you do a forum search?Maybe this code will help:https://www.eevblog.com/forum/fpga/vhdl-code-to-verilog-code/Note that the final VHDL->Verilog translation I made all the way at the bottom of the thread works and you also get a modelsim setup comparing the original VHDL and Verilog versions.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 12, 2023, 06:34:38 pm
content: CORDIC is successive approximation. You should be able to get about 1 bit per iteration.So for RF work you might implement it for 12 or 24 bits, for audio you might want 16 or 18 bits.The other thing I that the input usually isn't in radians, so that can trip things up, along with the CODIC gain (the output can have a scale factor applied).

author: Someone
author_rank: Super Contributor
timestamp: October 12, 2023, 10:56:46 pm
content: Quote from: hamster_nz on October 12, 2023, 06:34:38 pmUnfortunately no cute name like Unit Turn, or Gradians:https://en.wikipedia.org/wiki/Binary_angular_measurementBAM

author: hamster_nz
author_rank: Super Contributor
timestamp: October 12, 2023, 11:18:51 pm
content: Quote from: Someone on October 12, 2023, 10:56:46 pmNice!.. that link introduced me to 'brads' (binary radians). It is such a cute term it has to stick. "I'm demodulating at a 80 million brads per second!"

author: luudee
author_rank: Frequent Contributor
timestamp: October 13, 2023, 08:41:33 am
content: Hello,please take a look onwww.opencores.org, I believe we deposited there such an IP Core some time back ...Best Regards,rudi

author: BrianHG
author_rank: Super Contributor
timestamp: October 13, 2023, 12:21:08 pm
content: System verilog version at opencores...https://opencores.org/projects/cordic_atan_iqStrangely looks familiar...

author: den586
author_rank: Newbie
timestamp: October 13, 2023, 03:43:26 pm
content: Thanks for the answers. You can give an answer. What accuracy can cordic provide if, for example, we have a 16-bit sine output, and 16 iterations? In theory, when arctangent coefficients are given, 16 arctanges (the last one) is arctg( 2^(-15) )= 0.001°. Does this mean we will have the maximum error of the 16-bit output sin(0.001°)*2^16?

author: hamster_nz
author_rank: Super Contributor
timestamp: October 14, 2023, 02:24:40 am
content: If properly written it should be either the correct value or +/- 1 of the correct value.There is a lot of subtly as to what the correct answer is. For example you may be more bothered about the outputs purity than its amplitude. A little rounding error can cause the + and - halves to both round towards zero, causing something like crossover distortion.Or you might need the answer to be in the range of -32767 to +32767, (0x8001 to 0x7FFF) so you have no DC bias in the output.Oh, and should the transfer function be y = sin(x), or y=sin(x+1/(2^17)), as the input phase may have been rounded down as it was truncated to 16 bits.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 14, 2023, 10:46:33 am
content: There is a gold mine in zipcpu website, actually I had found a bug in cordic design there, a few years ago, and have contacted Dan and he has updated the code,check out his great article in herehttps://zipcpu.com/dsp/2017/08/30/cordic.html