How to even start routing this? - Page 1
Forum section: electronics / projects

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 06:39:50 am
content: Hi all,Was just wondering how any of you would even start to attempt manually route this rather crazy board? I could just auto-route it (which does work.)And yeah, not fully placed yet.....Thanks for any advice.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 06:42:10 am
content: Forgot to say, it's a two layer board.

author: martin1454
author_rank: Regular Contributor
timestamp: August 02, 2019, 06:52:05 am
content: Quote from: Joanna_H on August 02, 2019, 06:42:10 amGood luck! it is possible, but will take time! I would start by doing the simple connections (the straight from U22 to U18 and so)

author: Dubbie
author_rank: Unknown
timestamp: August 02, 2019, 06:56:47 am
content: Just start.

author: basinstreetdesign
author_rank: Frequent Contributor
timestamp: August 02, 2019, 07:12:32 am
content: If I was asking this question then I would have to conclude that I wasn't finished placing it. Placement generally takes more than half the total time. Shoot for the lowest average trace length no longer than about 3/8 of a boards side dimension. This is from Rents Reasoning. See here:https://en.wikipedia.org/wiki/Rent%27s_ruledown the page under "Rentian wirelength estimation".But a bigger question may be "Why only 2 layers?"; the cost jump from 2 to 4 layers is not that bad anymore. Getting rid of the power and ground distribution from the signal planes is easily worth the cost.

author: maginnovision
author_rank: Super Contributor
timestamp: August 02, 2019, 07:16:34 am
content: If I wasn't sure how to start I'd probably start by running the auto-router through multiple configs to get a basic idea of how it'd manage it and then do it myself. First, you need to finish the layout. Like basin I would recommend 4 layers. It's somewhat compact and the IC's are flipped all over which might make it pretty tough.

author: tggzzz
author_rank: Super Contributor
timestamp: August 02, 2019, 07:20:16 am
content: You don't indicate the class of IC use are using...If that will be a 2-layer digital board, the power supply will be critical; get it wrong and you will forever be chasing intermittent bugs. So:choose sensible positions for the ICsput decoupling capacitors nearbyput down a grid of 0V and Vcc rails, horizontal between the ICs's pins in one direction, vertical at both ends of those railsconnect decouplers directly to the ICs pins; easy if you have done the previous partadd in the signal wires, horizontal on one side of the PCB, vertical on the otheradd in extra ground connections wherever possible

author: Kleinstein
author_rank: Super Contributor
timestamp: August 02, 2019, 07:21:38 am
content: The placement of the chips can be quite important to simplify the layout. Another point is to check which signals are important - even with digital signals ground can be important.I would start routing the critical lines like ground - at least to a first approximation.The next part are than the difficult areas, as this may require getting more space / moving other parts.With 2 layers and so many parts one likely has to follow the general rule of 1 layer preferred horizontal the other vertical.40 MHz suggest that there will likely be EMI problems as a 2 layer board.

author: jbb
author_rank: Super Contributor
timestamp: August 02, 2019, 07:28:21 am
content: basinstreetdesign is right. Placement will be critical for a board like this - there are a lot of signal lines and you could get really tangled up.It’s going to be hard on 2 layers. I think you may need to pursue a routing strategy. For example, a classic approach is to go east-west on one layer and north-south on the other. Having SMT chips will help there.For reliable operation - or anything like FCC certification - you’ll need to pay close attention to ground connections and decoupling capacitors. Every signal current will try to return to be originsomehowand it’s best if that goes through a short ground plane. A four layer board would help a lot.

author: tggzzz
author_rank: Super Contributor
timestamp: August 02, 2019, 07:32:03 am
content: Quote from: Kleinstein on August 02, 2019, 07:21:38 amAgreed, but I'll note two points:"even with digital signals ground can be important" is an understatementa 40MHz clock sets a lower limit on the transient and EMI issues; the logic families' transition time is a key consideration

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 07:54:02 am
content: Thanks for all the replies, wow I have a lot to think about...

author: Unixon
author_rank: Frequent Contributor
timestamp: August 02, 2019, 07:56:43 am
content: 1) Make best possible placement. I see whole busses running between ICs from one end to another. This is bad, try putting these ICs with individually wide connections next to each other, so that a lesser number of signals would have to run long distances. Traces eat board space very badly, you can save a lot of it with a good layout. By the end of step (1) it may already become obvious how to route a board, because you will know what places you were trying to make traces run through.2) First route traces that you're better know how to, do short traces. For long traces route only end segment near IC, not the whole length.3) Next route traces that you have less good idea of how they should run, and again, start from both ends and join in the middle.4) Finally, solve routing problem for the few most difficult traces with a lot of side switching and snaking around.The idea about this approach is that it is much easier to route the board moving along uncertainty gradient: start from places where uncertainty is next to zero and you absolutely sure how things must be, then gradually move to places where you have not a slightest idea of if it even possible to do. The trick is, at the end of this path, not much of a ratsnest will survive the routing. Have fun with it.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 07:57:04 am
content: To answer the other questions, this is a simple SVGA 800x600@60Hz Graphics display. It's a module that I've been putting together to go with a load of other modules I'm creating to make a watch as it works CPU, variable speed up to a max of 1Mhz. The 40Mhz is required due to that being the specification for the video out. 99% of the logic is standard 74 series, when not it's all TTL compatible outputs, all running at 5V.

author: tautech
author_rank: Super Contributor
timestamp: August 02, 2019, 08:15:03 am
content: Others might have a different approach but I always start PCB layouts with the schematic sheet on the next monitor and visualize breaking the circuit into functional blocks then to lay the components for each block together in little groups in a way that they might each Autoroute OK. Some things are set in stone like I/O sockets and the like so place and lock them and jiggle around with the remaining.Then you have each little groups rat nest connections and then select each group in turn and move them around and keep a watch for routing paths to be plainly seen that might allow all the little functional blocks to be linked together. When you get/find a layout that might work Autoroute it and look for what needs improving for signal integrity or whatever.Lots of Autoroute/UnAutoroute trial and error will find a way that works that can be further tweaked to get a good looking layout.Good luck and be prepared to put real time in for a good job.

author: Ice-Tea
author_rank: Super Contributor
timestamp: August 02, 2019, 08:21:13 am
content: Take the advice of others.. Go to a 4-layer board. If this is a paying job, the extra cost will be offset easily by the saving of labor and the probably saving of a respin because of performance/EMI issues.Use a calculator from a local (Eurocircuits or somesuch) or an offshore supplier (such as PCBway) and you'll soon figure out in most cases going 2 layers just isn't worth it..

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 08:24:55 am
content: Quote from: Ice-Tea on August 02, 2019, 08:21:13 amYeah, I'm starting to think 4 layer may be the way to go.... lol

author: tggzzz
author_rank: Super Contributor
timestamp: August 02, 2019, 08:27:53 am
content: Quote from: Joanna_H on August 02, 2019, 07:57:04 amThe 1MHz is completely irrelevant - all that matters is the transition time, which can be <5ns for old school TTL. That corresponds to significant frequency content at >100MHz.Ground bounce is a real problem due to the low VILspec of TTL and the currents in switching transients. A good gridded ground is the only way to minimise the consequences. for a canter through the theory, plus some practical measurements, seehttps://entertaininghacks.wordpress.com/2018/05/08/digital-signal-integrity-and-bandwidth-signals-risetime-is-important-period-is-irrelevant/

author: tggzzz
author_rank: Super Contributor
timestamp: August 02, 2019, 08:33:09 am
content: Quote from: Joanna_H on August 02, 2019, 08:24:55 amIf you do, make one layer a solid ground plane and another a solid Vcc plane. If they are inner planes then it is easier to probe and modify signals. If they are outer planes then EMI problems will be minimised. Choices, choicesBe aware of the maximum length of a track before it has to be treated as a transmission line. With old school TTL (e.g. LS, ALS) you will probably be fine, but modern jellybean logic is a different kettle of fish (e.g. 74lvc1g* is <1ns, I've measured 300ps)

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 08:58:03 am
content: I thought I'd autoroute it just to get a feel of what I've let myself in for......4 layer board, internal gnd/power planes and top/bottom signal.I think my head is going to really hurt with this one.

author: tautech
author_rank: Super Contributor
timestamp: August 02, 2019, 09:04:49 am
content: Oh and I forgot, for dual, triple, quad and hex packages don't forget you can reassign gates to make routing easier.

author: KE5FX
author_rank: Super Contributor
timestamp: August 02, 2019, 09:07:56 am
content: Don't bother with a power plane. Use an unbroken ground plane on one of the inner layers and use the other three for routing. Leave the ground fill intact on those planes (edit: andgroundit, don't leave large islands of unconnected copper lying around.)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 02, 2019, 09:26:06 am
content: Consider enlarging the board, or using TSSOP devices (which I guess at this speed, should be 74HC for some, and AC or LVC when needed?).While it's usually possible to route a board with minimal space left between components, it's not a pleasant option. Expect to commit about half the area to routing. Routing as highways and streets may be helpful: make small blocks of tightly coupled components, then arrange those blocks near each other according to their connections, and so on hierarchically until done. For each step, leave a gap between blocks, proportional to the size of that block. That way you end up with one big gap down the middle of the board (where long distance signals and buses can be routed), smaller gaps feeding that, and smaller gaps feeding those. You always have enough room to route an average number of signals this way.Don't be afraid to rip up and try again. Swap gates, swap components between blocks, swap blocks. Adjust boundaries (the blocks probably won't be exactly the same sizes, after all, making this fractal concept a lot uglier in practice). Adjust priorities (which signals take the "right of way" as it were, with the least interruptions / bends / vias), and adjust routes (take a different "street" around this or that block, etc.). Adjust positions again to shove components closer, taking up what free space is left.If you're still new at this, just one go at the layout may take weeks; seasoned, days. Don't be discouraged; even a rip-up is still learned experience, whether in using the tool, or in understanding the relationships between components and pins.Board outline -- if you're stuck to a particular board size, consider using riser boards, or stacking. Same block-oriented concept, put stuff behind connectors of modest size. (BTW, alternate signal and ground in a one-row header, or assign one row of grounds in a two-row header.) Or, synthesize all the damn logic in an FPGA and be done with it a lot sooner.(Again, providing one has the experience; if not, expect to spend a few months learning what VHDL or Verilog is, and how to use it.)Tim

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 02, 2019, 09:28:31 am
content: Quote from: Joanna_H on August 02, 2019, 08:58:03 amThat doesn't look too shabby. Which PCB tool did you use for the autoroute?

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 09:32:55 am
content: Quote from: T3sl4co1l on August 02, 2019, 09:26:06 amHehe, the challenge was to attempt to do it with 74 series, lol.

author: Ice-Tea
author_rank: Super Contributor
timestamp: August 02, 2019, 09:41:06 am
content: Quote from: KE5FX on August 02, 2019, 09:07:56 amBut...Why??Do you hate power integrity? Do you appreciate high frequency noise? What? This will easily fit on 4-layers with GND and PWR planes.. Why not do it 'right'?

author: Unixon
author_rank: Frequent Contributor
timestamp: August 02, 2019, 09:41:18 am
content: Quote from: T3sl4co1l on August 02, 2019, 09:26:06 amSOIC packages have an underestimated and very useful feature: the ability to let traces go between pads on the same precision class board.While TSSOP packages occupy less space, they potentially make routing harder.

author: spudboy488
author_rank: Regular Contributor
timestamp: August 02, 2019, 11:19:29 am
content: Quote from: tautech on August 02, 2019, 09:04:49 amThe same holds for signals going through bus devices. For example, you don't have to keep D0 through D8 aligned through an 8-bit buffer/latch/etc. as long as the same order is applied on the other side.

author: dmills
author_rank: Super Contributor
timestamp: August 02, 2019, 11:56:45 am
content: Also, (Static) RAM can usually freely swap address lines and data pins which can be VERY helpful, and is often forgotten....4 Layers for me (It is pretty much my default position these days).Regards, Dan.

author: ejeffrey
author_rank: Super Contributor
timestamp: August 02, 2019, 12:35:12 pm
content: Quote from: tggzzz on August 02, 2019, 08:33:09 amHardly a choice. The EMI advantage of outer planes is hardly worth the ease of debug and tracing for what I assume is a one off. Plus for a project that is basically intended to show off old school 74 series logic design, it hard to give up the appearance of a nicely routed board for solid planes.

author: voltsandjolts
author_rank: Unknown
timestamp: August 02, 2019, 01:02:19 pm
content: 4 layers will save your sanity.pcbshopper.com is your friend. (no affiliation).

author: tggzzz
author_rank: Super Contributor
timestamp: August 02, 2019, 01:22:27 pm
content: Quote from: ejeffrey on August 02, 2019, 12:35:12 pmAgreed. But the OP hadn't bothered to divulge that information when I wrote that post.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 02, 2019, 01:35:07 pm
content: Just a tip, didn't really look closely how well your autorouter did, but if using autorouting, I would first hand-route all bypass caps and power supplies, then let the autorouter handle the rest. Autorouters can do a pretty atrocious job at routing supplies, and often like to create horrible loops, especially on a 2-layer board.Of course to be half successful at routing this, placement will be key.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 01:43:37 pm
content: Quote from: ejeffrey on August 02, 2019, 12:35:12 pmYeah, it's one off, showing off old 74 series, easier for someone looking at it to comprehend (well, the ic's at least.)

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 01:48:49 pm
content: Quote from: voltsandjolts on August 02, 2019, 01:02:19 pmThanks for the link.. cheapest for a 2 layer with delivery is about £20, cheapest for a 4 layer with delivery is about £40So ... hmmm...

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: August 02, 2019, 03:03:00 pm
content: PlacementPlacementPlacementGate and pin-swapping for multi-gate packages, swapping gates between packages where possible.Do you really need to keep it to two layers ?How many of these are you making? - unless it's thousands then your time getting to 2 layers is probably worth mor than the additonal cost of 4 layers , bearing in mind that it can probably be smaller on a 4L PCB as well.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: August 02, 2019, 03:04:37 pm
content: And as there is RAM, bear in mind that you can swap around any address and data pins to help layout.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 03:23:28 pm
content: Quote from: mikeselectricstuff on August 02, 2019, 03:03:00 pmI'm just having fun with a little project, doesn't have to be 2 layers, etc.. I'm just trying to keep costs down as it'll probably take a few revisions to debug it all. It's also why I restricted each module size to 100x100mm, to keep costs down. Yeah, I could have made it a lot cheaper by using a FPGA but that defeats the point of trying to create it out of 74 series..It's really just a mini (well not so mini any more) project.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 02, 2019, 03:48:32 pm
content: It's all part of a bigger modular project as described earlier, so it's just lots of 100x100mm boards connected together. Been going through doing each part and then reliased a graphical output would be nice. So put that thing together, probably will get changed again, but not sure. Other stuff has been done, but again needs to be manually routed, it's mostly auto atm just to get an idea of what is going on.

author: KE5FX
author_rank: Super Contributor
timestamp: August 02, 2019, 05:04:01 pm
content: Quote from: Ice-Tea on August 02, 2019, 09:41:06 amPower for components in this class that are mounted on boards of that size comes from capacitors, not planes. She's got plenty of bypassing, but not enough routing area.One nice thing about power planes, however, is that they can be used to maintain copper symmetry. The board will less prone to warpage if large planes are balanced from top to bottom. If the power plane is omitted, it's good to maintain a lot of ground islands for that reason. Don't remove copper unnecessarily, in other words.... but don't ascribe any magical electrical properties to it, either.

author: jmelson
author_rank: Super Contributor
timestamp: August 02, 2019, 06:45:23 pm
content: Quote from: Joanna_H on August 02, 2019, 06:42:10 am2 LAYERS? The power and ground nets, if made with even slightly thicker traces, will fill almost the entire area, leaving no space for signal routing. I really don't think you can do it.If this is all digital stuff, why not use an FPGA? You might be able to do it in one chip.Jon

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 02, 2019, 10:41:33 pm
content: Yikes! EMI-wise, you're probably slightly better off building this on solderless breadboard with a metal backplane. It absolutely will ruin your design: I'vebreadboardeda mere Z80 + RAM + couple bus latches system on one solderless breadboard panel, and had it freeze up at random times due to poor signal quality. (The randomness was due to implementing an LFSR in the main loop; with the usual loop (an LED display routine), it was fine.)The resistor placements look like they were determined based on spacial balancing (i.e., a row of this here, a row of that there..), with no regard for where they connect?Tim

author: IconicPCB
author_rank: Super Contributor
timestamp: August 02, 2019, 11:20:37 pm
content: I would like to let Topor chew on this and see what it spits out.If You are Ok with this please send pcb file.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 03, 2019, 03:01:38 pm
content: I'm seriously considering abandoning the TTL approach, it's fun, it's challenging, but I just went throught the BOM of what I've developed so far and lets just say that it's starting to get pricey.... lots of different boards, lots of B2B connectors, lots and lots of TTL chips. Adds up quickly.I'm starting to think I could achieve the same goal using a number of FGPA's (cheaper ones) that would 1) lead to lower cost, 2) require less PCB's and 3) a hell of a lot less routing!

author: rstofer
author_rank: Super Contributor
timestamp: August 03, 2019, 06:30:04 pm
content: Without a BOM, it's pretty hard to see how much logic is involved with the project. If most of those chips are MSI, I think the entire project will fit in a small FPGA. Perhaps we're not seeing the entire project, just one sub-assembly.A smallish FPGA will have millions of gate equivalents. Think of an FPGA as a dumpster full of logic with a bunch of RAM on the side.The bigger problem with the FPGA is getting all the external signals to fall in the range acceptable to the chip. These days that is usually 3.3V signals.A separate issue is packaging. Most of the FPGAs use BGA packaging and I'm not up for that. But I can buy 'stamp format' boards and just solder them in to a daughter card.I might consider something like the A7-35T variant if I wanted a 'stamp format' board:https://store.digilentinc.com/cmod-a7-breadboardable-artix-7-fpga-module/All the hard work is done, all I have to do is handle the inputs and outputs and write a little code.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: August 03, 2019, 07:08:00 pm
content: Quote from: rstofer on August 03, 2019, 06:30:04 pmThere are plenty of FPGAs in QFP, which isn't a big deal to hand solder

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 03, 2019, 08:23:10 pm
content: Sure. We don't exactly know what the complete circuit is, but it may perfectly fit in a MachXO2. If something a bit beefier is required, you can go for a Spartan 6 LX4/LX9 - all available in QFP.

author: amyk
author_rank: Super Contributor
timestamp: August 03, 2019, 08:46:04 pm
content: I didn't read each of the replies in detail to see if this was already posted: Think about how your signals flow and use that as a guide to placement. It may sound obvious but the more net crossings you eliminate, the easier it gets to route.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 03, 2019, 09:34:18 pm
content: Quote from: SiliconWizard on August 03, 2019, 08:23:10 pmI was looking at the MachX02 ( I think these are closer to CPLD than FPGA) , nice cheap little chip. Could fit a hell of a lot of logic in one of thoseI could still keep the modular design but massively reduce the chip count. Would mean switching to 3v3 though. But no biggy. Should be fun, haven't touched verilog since the 90's lol

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: August 03, 2019, 10:07:22 pm
content: Nice thing about the XO2 is it has onboard config memory, core voltage regulator and also an oscilllator, so minimal extra parts. A few package options from QFN32 to QFP144.

author: rstofer
author_rank: Super Contributor
timestamp: August 03, 2019, 10:09:28 pm
content: Start by selecting a small chip and write the code. If it won't fit, move up a notch. Unless you want to do a lot of extra work on the constraints file (pinout definition), just do synthesis and check for fit. You can use simulation without defining the pinout, I think.I tend to go the other way: I buy a big chip and leave a lot of empty logic laying around. I only have experience with Xilinx devices from Spartan II up into Artix 7.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 03, 2019, 10:29:31 pm
content: Quote from: mikeselectricstuff on August 03, 2019, 10:07:22 pmYeah, like the QFP144, enough I/O to get things going.. as I'm trying to create a "modular" cpu that you can see what each bit is doing this could be a nice path. But I think I'll need a few of them as I'll need quite a few control lines. Even so, it's worth exploring as an option

author: NivagSwerdna
author_rank: Super Contributor
timestamp: August 04, 2019, 01:19:20 pm
content: I was trying not to mention FPGA as it seemed to go against your design goals and I was assuming this was a 5V retro project. Checkout TinyFPGA for design ideas if you are going that route.Mike has replied and has a lot more experience than me but XO2 does come in small configurations or there is ICE40.Have fun

author: rstofer
author_rank: Super Contributor
timestamp: August 04, 2019, 02:37:01 pm
content: Back to routing:If any of the devices are memory chips, you don't have to keep strict alignment between A0->A0, A1->A1, etc. You can hook the address lines in any sequence. The only thing that happens is that logically adjacent address are spread around in the memory.Same deal for data lines. D0 doesn't have to be right next to D1.This turns out to be a real big deal when working with memory and MCUs.ETA: This may cause problems with DDR memory but is often used for SRAM.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 05, 2019, 01:38:35 am
content: Quote from: NivagSwerdna on August 04, 2019, 01:19:20 pmYeah, my original goal was all TTL, but with board space, number of components, etc. etc.. The cost would become silly.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 05, 2019, 07:01:13 pm
content: Thanks for the FPGA suggestion, this is fun. Different way of thinking about it all, but I should be able to achieve the same goal. A CPU that you can monitor every part of it and see how it worksThanks.Verilog is a bit interesting though....... Something new to learn.Still, having fun.. AddressLineDriver / Program Counter and a few other bits done so far.The second jump test is an inpage jumping test, which gives a data bus size jump range (16bit in this example) costing only 1 cycle.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 06, 2019, 05:44:51 pm
content: You know the world has become a little scary when you can fit the majority of an old school 16bit processor into about 2% of a low spec FGPA.......LCMXO2-640UHC-4TG144C. had to choose the 640 as the lower one doesn't have enough I/O pins :/I'll post no more on this in this thread as I've gone way of topic now.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 06, 2019, 07:44:23 pm
content: Quote from: Joanna_H on August 06, 2019, 05:44:51 pmNot surprised.You did that pretty fast!

author: PlainName
author_rank: Super Contributor
timestamp: August 06, 2019, 08:24:14 pm
content: Just like to say that a good habit to develop is to keep pin1 in the same orientation for all chips. Sometimes it's not practical but in that case keeping complete groups the same is a reasonable fallback. Similarly, diodes all point the same way (for those all pointing up/down or left/right). The reasoning is to prevent assembly cockups.

author: Joanna_H
author_rank: Regular Contributor
timestamp: August 07, 2019, 09:09:50 am
content: Woops, just noticed I was up all night messing with this.. LOLStill, have some things now working.A simple test of a NOP, JMP (in page, LSB only) and LJMP (anywhere in memory, uses both MSB and LSB) was fun. But starting to eat up those resources as I add more stuffAt least the microcode isn't on the FPGA, seperate EEPROM to allow for easy program/reprogram of that little part. Both memory and eeprom simulated in the testing to see how it's going