Help in optmizing a way of sending a reset pulse after a set time from powering  - Page 1
Forum section: electronics / projects

author: Ronny
author_rank: Contributor
timestamp: April 26, 2017, 02:11:07 am
content: ...has passed.Good night everybody,I am making a circuit that has multiple counters connected to ring oscillators (it's a PUF). For the circuit to function properly I need to wait for the ring oscillators to stabilize and then reset the counters.It is for a college project and the professor is rewarding minimum use of PADs and smallest size.My initial idea was the following:Make a counter with a nand gate connected to its terminals, once it reaches its maximum value it stops resetting a second counter that then starts counting, when the second counter reaches its maximum value it stops resetting the counters connected to the rings.Needles to say this will take a huge amount of space, the other option is to send a remote reset pulse through a PAD. Either way I am not being efficient for the project specifications.Do any of you guys know a smarter way of sending a reset pulse after waiting at least a minimum time? Another perfectly viable option (which is the one I am currently using) is to keep resetting the counters until a defined period has passed.To make things harder, this is for a VLSI class, so I can do it only with MOSFETs, no capacitors, no resistors.I'll post a photo of the block diagram I am thinking about doing, but it is so big that I am mostly likely using an external signal, unless I find a better way.Thank you very much.

author: Rerouter
author_rank: Super Contributor
timestamp: April 26, 2017, 08:15:22 am
content: You left out what your function blocks architechture was like, could reduce it furthur, but this is the simplest approach to me, just hold the main counter in reset by the msb of your sampling counter, count X counts, in this case 2048 cycles, then the nand gates switch the input clock from the sampling counter to the main counter.

author: Benta
author_rank: Super Contributor
timestamp: April 26, 2017, 08:29:13 am
content: Why don't you just hold the reset to the counters during power-up, and then release it after a set time, when you know the oscillators have stabilized? Much simpler.

author: Rerouter
author_rank: Super Contributor
timestamp: April 26, 2017, 09:07:07 am
content: My thinking was as he has no passive's, and from his diagram no dedicated clock, how do you wait for "a certain time", and took the approach that is used on most microcontroller clocks, count X number of cycles before switching to it, to allow it to stabalise.

author: Ronny
author_rank: Contributor
timestamp: April 26, 2017, 06:57:10 pm
content: Quote from: Rerouter on April 26, 2017, 08:15:22 amVery nice solution, but there is a problem with my design if I use this. The most significant bit of my counters is already being used (not shown in my drawing, sorry for that). All 5 counters's most significant bits are connected to a 5 bit NAND gate that halts the rings (to save power) and change the shift register from read to shift. Sorry for not showing this in the drawing.If I do it the way you suggested, when the most significant bit switches the input from the CLK ring to the rings it will simply stop.------------------------------Quote from: Benta on April 26, 2017, 08:29:13 amIt is a VLSI project. I must make everything for the circuit, there is no such "set time", I must make the set time.For example, when I say I will use a counter I am not going to have a little block called counter (like in Quartus for example), that is what I am working with (not finished):