High resolution dual PWM DAC with notch filters - Page 1
Forum section: electronics / projects

author: Krampmeier
author_rank: Regular Contributor
timestamp: December 10, 2017, 12:16:31 pm
content: I like the concept of using PWM for implementing a DAC, as it allows to achieve very high resolution rather easily. The most critical problem that occurs is that the PWM frequency becomes slower as the resolution goes up. This makes it necessary to use complicated high-order low pass filters in order to get rid of the ripple while still preserving a reasonable settling time.Using a passive first order R-C filter becomes implactical pretty quicky when you want to get far beyond 10 bits of resolution. The settling time becomes very long if a low corner frequency of the low pass filter is used, and the ripple gets too high if the corner frequency is too high.Using active filters is an option, but every operational amplifier adds drift and cost. At 20 bits or more, expensive zero-drift amps have to be used, which have a very low GBP and can not filter out the high frequency components of the PWM signal.A nice option is presented in the EDN:https://www.edn.com/design/analog/4441113/A-faster-PWM-based-DAC.This concept is also used in the Adret 103A calibrator, and probably many other calibrators.Several low-resolution PWMs are filtered separately and the resulting voltages are combined using a scaling summing amplifier. As the individual PWMs have lower resolution, their frequency is higher and a simpler filter design and can be used. This works because low resolution PWMs can still have very high linearity. The new problem is that resistors with excellent temperature drift matching are required, and the ripple of the "most significant" PWM must still be less than the contribution of the lastLSB of the whole DAC. If one wants to get really high resolution, that is still not easy to achieve.That could be solved if we could filter out the ripple in a better way compared to the simple LPFs. The PWM signal has a simple spectrum, consisting of only the odd number multiples of the base frequency. Why not remove the first few harmonics with passive notch filters, and use a simple L-C-R filter for the remaining high-order (and high frequency) harmonics only? That way, we can get a low ripple and fast settling time at the same time, without the cost and other disadvantages of active filters.I have never seen that approach on the internet - all PWM DAC descriptions focus on normal low pass filters. Did I miss a major weakness of that concept?I have not built the circuit yet, but I have simulated it with LTSpice. The attached circuit shows a 12-bit PWM DAC which has only about 1.5 ppm ripple at the input of the first amplifier (and even less behind it). It settles to 1 ppm accuracy within 100 ms, so it is ideal for adding a secondary PWM in order to get a much higher resolution. The inductors are rather small and could be wound without a core (and tweaked with a screw driver). The capacitors are maybe a bit too large for using COG types - I'll have to check that before I select the final structure of the DAC, but there will be a solution for that, too.You can play with the parameters in the attached LTSpice file and check how the concept behaves. It would probably make sense to use only a 10-bit PWM for the MSB part (in order to get the ripple down a couple of orders of magnitude), and a higher order PWM in the LSB arm. The ripple requirements for that one are much lower, so probably the same filters (with adapted values) could be used. Maybe 10+14 or even 11+16 Bits would be possible with a 90 MHz base clock?

author: ogden
author_rank: Super Contributor
timestamp: December 10, 2017, 01:27:55 pm
content: Quote from: Krampmeier on December 10, 2017, 12:16:31 pmDefinitely you would want to run Montecarlo simulation using real accuracy/specs of the components, especially for inductor-based notch filters.Sorry to say that, but I do not see implementation that usesso much inductorspractical as well. - Not even mentioning wound inductors which shall be tweaked (!).Where's idea of even considering to build such a "complex" DAC? Today there's plenty of 24-bit DACs around. You can get decent >= 20 bits using feedback DAC architecture (Linear Technology application note AN86, Figure1) which does not cost so much.https://www.eevblog.com/forum/chat/electronics-surplus-warehouse-find!/msg620653/#msg620653

author: Kalvin
author_rank: Super Contributor
timestamp: December 10, 2017, 01:37:28 pm
content: Have you checked this design idea:https://www.edn.com/design/analog/4459116/Cancel-PWM-DAC-ripple-with-analog-subtractionI guess (ie. I have not simulated this) that you could combine both ideas of using fast PWMs with ripple subtraction.

author: Cerebus
author_rank: Super Contributor
timestamp: December 10, 2017, 02:29:25 pm
content: One massive problem here. These are fixed frequency notch filters. You are not trying to filter a set of fixed frequency sine waves, the frequency of the underlying Fourier components of the PWM signal change as the mark:space ratio of the PWM signal changes.

author: Kleinstein
author_rank: Super Contributor
timestamp: December 10, 2017, 02:48:02 pm
content: LC filters are only practical at high frequencies. Large inductors with core are nonlinear and can thus ruin the accuracy.The ripple compensation is kind of similar to a notch filter.There are active low pass filters that don't need AZ OPs - even for higher order (like 7 th order) there is only one DC critical OP as an buffer for the output. The other OPs are only AC coupled and thus do not cause DC errors. So they can be rather normal JFET based or BJT based (though less practical) OPs. Some of the Fluke an Datron Calibrators use this system.Some modern µCs also allow very high time resolution with the PWM signal with special interpolation. This corresponds to an PWM clock in the GHZ range even when the µC is only running at maybe 50 MHz. So one could get 20 Bit PWM resolution in the kHz range. In addition, there the possibility to use a kind of sigma delta modulation with lower resolution PWM. This effectively reduces the amplitude of the lower frequency component.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 10, 2017, 02:51:39 pm
content: Quote from: Cerebus on December 10, 2017, 02:29:25 pm^^^Specifically, the PWM modulation signal (what you want to isolate in the baseband) is a sideband on each harmonic, and a sideband on a sideband and so on as you go up.So a 1kHz sine wave modulating a 100kHz clock gives you components:1kHz99kHz, 100kHz (fundamental), 101kHz (1st sidebands)198kHz, 199kHz, 200kHz*, 201kHz, 202kHz297kHz, 298kHz, 299kHz, 300kHz, 301kHz, 302kHz, 303kHzetc.*Ideally, even harmonics are balanced to zero, if the mean duty cycle is exactly 50% and the rise and fall times are matched. In practice, the 2nd and 4th may be usefully small to begin with, but higher harmonics tend to blend together, all going at similar levels with the 1/N amplitude trend.So, for this case, at the 50th harmonic (5MHz +/- 50*1kHz), you get continuous overlapping harmonics and sidebands. In this case, the signal is harmonically related to the clock (1/100th), so some sidebands will interfere with harmonics and the exact spectrum depends on phase. But for an arbitrary signal, all we can say for certain is that the harmonics are widened by the sidebands.The lower harmonics will typically dominate in amplitude, so it can be worthwhile to concentrate extra filtering on them specifically. This is done with a standard lowpass filter, except zeroes are added to its response, by placing capacitors across the inductors. (Or using active filters and introducing a feedback path between pairs of stages.) The ideal placement (for a specified minimum stopband attenuation) is given by the Cauer (elliptical) filter coefficients, but the zeroes (notches) are not evenly spaced. What you do is start with such a design, and tweak values until the zeroes are positioned at harmonics. As you adjust this, the minimum stopband attenuation will change, so be sure to start with a filter that's more than good enough to begin with.BTW, note that the maximum bandwidth of a PWMDAC is therefore Fclk/2, because going for more pushes the fundamental's sideband into the baseband (they overlap). It's a similar argument to Nyquist sampling. And a practical DAC+filter will need a gap of 2-4 times the signal bandwidth, or, say, for 10kHz BW, Fclk >= 60kHz.Also, at low frequencies (under a MHz, say?), active filters are preferred. Heck, even at modest frequencies, they can be cheaper, smaller and more accurate; GHz op-amps are plentiful these days!Tim

author: tggzzz
author_rank: Super Contributor
timestamp: December 10, 2017, 02:54:15 pm
content: Delta-sigma modulated DACs have distinct advantages over simple PWM DACs.If you are looking at a large number of bits, then you may also have to consider the non-linearities in all of your active and passive components.

author: Krampmeier
author_rank: Regular Contributor
timestamp: December 11, 2017, 12:25:05 pm
content: Thank you for all the valid and helpful comments - these are highly appreciated!You are totally right, I did not take into account that the spectrum of the PWM signal changes when the duty cycle is changed! The Wikupediahttps://de.wikipedia.org/wiki/Datei:Tastgrad-Spektrum.ogvshows that the even harmonics will also show up if the duty cycle changes - I suppose I'd have to filter out the first few of those if I want to stick to this concept.I changed the duty cycle in the simulation to several different values and the ripple stayed almost the same (1 - 1.5 ppm of full scale). Maybe filtering out the fundamental frequency already does the most important task, as the higher harmonics are attenuated by the LPF more. I still have to check which higher order filters are actually expendable.Adding the "ripple suppression" which Kalivin suggested would certainly be worth a try - it could be placed even before the notch filters. The problems with changing spectrums are automatically taken care of there. Maybe I could push the ripple down another order of magnitude with that.I don't follow a distinct purpose with this project - I was just curious about the PWM DAC concept and wanted to know if / how I could push it to 28ish Bit resolution with simple means and low cost, and learn something in the process.I don't have a voltage reference with an adaequate stability, nor a suitable DMM to verify the performance - I'd just like to play with it and see how far I can get. Restorating an orld calibrator (https://www.eevblog.com/forum/repair/documents-or-repair-experience-for-adret-103a-dc-current-and-voltage-standard/msg1318611/#msg1318611) brought me to that idea. If I can cobble something together which seems to work well, I can still take it to the cal lab at work.I will have a look if I can find out more about the active filters without DC errors which Kleinstein mentioned. Even JFET input amps have a strong input bias current drift over temperature, so I'd prefer to reduce the number of active components to a minimum.Does anyone have a link to a paper which describes how the "special interpolation" which Kleinstein mentioned works in detail, achieving high resolution with low clock frequencies?Using sigma-delta modulation (spreading the 1s and 0s more evenly over time) sounds like a good idea, but I think I'd need an FPGA for that, right? I have an ARTY board lying around here, but I couldn't get the development software running properly yet...T3sl4co1l, what you wrote about proper filtering sounds very sophisticated, but I am afraid that I didn't follow my "system theory" course well enough to fully understand it. From my gut's feeling, I don't think that GHz Opamps would be suitable if one wants to get into the 28 bit resolution area...I don't think about modulating the output voltage, so mixing products would not be an issue, right?tggzzz, if I only care about the DC component on the output, will the nonlinearities of my passives really matter that much (once the filters are tweaked right)?

author: tggzzz
author_rank: Super Contributor
timestamp: December 11, 2017, 03:59:03 pm
content: Quote from: Krampmeier on December 11, 2017, 12:25:05 pmThat depends on the clock rates, of course. If you insist on accurate edge timing (and you should!), then consider using 1 core of an XMOS xCORE processor plus its timed SERDES output ports.QuoteStart by considering solder + PCB tracks + connection junctions as being non-ideal due to the Seebeck effects. Then consider leakage currents and dielectric absorbtion. Then move onto the difficult stuff.All are "good exercises for the student"

author: Kleinstein
author_rank: Super Contributor
timestamp: December 11, 2017, 04:32:37 pm
content: The Fulke 5700 Series and some Datron calibrators use a PWM DAC for DC. There are some schematics on the xDevs web page in the service manuals. It is not only the filter to learn about. These calibrators use one AZ OP for the output buffer and non critical JFET OPs (in some cases with discrete JFETs and BJT OPs, but no more need for this) - DC performance like bias of these OPs is not that critical, as they are already separated by capacitors. These filters still need some pretty large size PP foil filter caps, but nothing out of the ordinary.Some modern µCs like STM32F334... is an example for a µC with high resolution PWM (in this case timing resolution of about 220 ps). Other manufacturers have similar solutions. There are µC specific describtions. Even the normal often rather high timer clock (e.g. 140 MHz) can give a good PWM resolution without going very low in frequency. Generating the PWM signal is more like the least problem.Full sigma delta modulation is not needed and not even wanted, as this would cause a rather high and maybe even variable switching frequency. The more practical way is to have something like an 8 - 12 Bit PWM and modulate this in a sigma delta way. The calculation is relatively simple so even an 8 Bit AVR µC can do this for full speed 8 Bit PWM and 2 channels. There is still the same lowest frequency as with normal PWM, but with a much lower (e.g. > 256 times) amplitude. With sufficient PWM resolution and a good filter one might not need this.Even if you only want DC, the settling time should still be no too long. Here the normal filter function might be the smaller problem - that is relatively easy, as it usually is just waiting a few more time constants. The nasty part is dielectric absorption that can make the settling to very low margins extra slow by adding unwanted rather slow components.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 11, 2017, 06:26:25 pm
content: Quote from: Krampmeier on December 11, 2017, 12:25:05 pmNo, just no.But why no? Consider:To get 28 bits resolution, you need an inconveniently high clock frequency for even a paltry bandwidth. A 28 bit counter is 268MHz. just for a measly 1Hz output, which will get you a maximum bandwidth of 0.5Hz, and a practical bandwidth maybe 0.2Hz or less. You might reconsider on needing that FPGA. Or some ECL counters.You also need a fine enough division between steps to support that accuracy. A small change in the propagation delay or rise/fall time translates to a fixed (not proportional) error in the output. A change of just 1ns is ~1/4th an LSB.Rise/fall time depends on load, so the first stages of the PWM filter affect DAC linearity. Ideally you'd buffer it, but now you need GHz buffers too, just for a fractional Hz result.The whole thing just reeks of scalability fail.QuotePrecision opamps with microvolt errors are readily available. (What do you think Keysight, Kiethley etc. do, rub manganin sticks together?) They're not usually the fastest, but with a S-D (D-S? who cares) DAC, that's more than alright!Quote32 bit I2C or SPI driven DACs are cheap and readily available (though managing to get nearly as many bits out of the real result (and verifying it!), is much more expensive to achieve). If nothing else, you can realize your own with a few counters and op-amps, or any amount of hardware or software you prefer -- at these clock rates (a few megs), you can bit-bang a pretty good one, if you do so carefully of course.QuoteWell, you hadn't mentioned what you were doing. Now that it's clear you're talking about ~DC range signals, you'd use a precision op-amp and that's that.Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: December 11, 2017, 07:04:31 pm
content: Just generating an higher resolution PWM Signal is not that magic anymore. With special interpolation HW inside some µC can produce high resolution PWM. As an example , the STM32F334 has a resolution equivalent to a 4.8 GHz PWM base clock. Due to Jitter the accuracy is already lower. So still 15 Hz at 28 Bit resolution ( I somewhat doubt it will support more than 24 Bits directly).The early designs usually used something like two PWM Signal with about 16 Bit resolution and combine them. The accuracy of the combination resistors set how much of the fine adjustment is real - so not 2 time 16 Bit gives 32 Bit resolution, more like 20-24 Bits. So direct super high resolution PWM was never planed.However the analog part will not give this super high resolution. The nonlinear rise / fall time is just one of the problems. Others are R_on matching, voltage dependent charge injection.It can be still a fun project to build a higher resolution PWM based DAC. Even if you only get 18 bits - you can still learn a lot from it.

author: Krampmeier
author_rank: Regular Contributor
timestamp: December 11, 2017, 10:00:04 pm
content: Thank you for all the new input!tggzzz, I don't worry about the thermoelectrical voltages so much - I still have some spare cadmium tin solder from my Keithley 150A microvolt meter which I can use. Just kidding! As long as there are no large thermal gradients in the setup and nobody touches the connectors, the thermal EMF is usually not that problematic - at least that's my experience from calibrating thermocouple input devices. I'll have plenty of other things to worry about firstI actually planned to start with an STM32F446RE Nucleo board (which I already have), as that makes it easy to get "something" quickly, and can be re-used later. I'll check out the other options as well, like the STM32F334 (which Kleinstein mentioned). That one would certainly the better tool for the job.Kleinstein, thank you again for your hints. I will have a look at the Fluke and Datron schematics, and hopefully understand them enough to get the ideas behind the circuits.I am not sure what you mean with modulating an 8-12 bit PWM. Is it just changing the duty cycle on every cycle, so that it averages to the correct intermediate value? That sounds like a very interesting idea for medium-resolution PWM, as it would make filtering much easier.On the other hand, if I understand it right, if I go as high as 28 bits (with 90 MHz main clock), the total frequency would still be 90 MHz / 2^28= 0.33 Hz - impossible to filter that, no matter how low the amplitude of that frequency is...I don't have much experience with dielectric absorption (except the "self-recharging" capacitors we all have seen). I used to think that it does not matter that much if all the signals are rather low-impedance. I may be wrong.The non-symmetrical rise/falltimes and R_on are one important aspect. The Adret calibrator takes care of the latter with a "linearity" potentiometer in series with the PWM switch "high" input, but I suppose the compensation of such basic systematic errors (also including the charge injection) could be done in software today, when modelled correctly.Yes, I would still be happy if I get 18 bits out of my circuit in the end. It is just a hobby project after all.Tim, I never planned to implement one large 28-bit PWM, but always wanted to combine 2 or 3 PWM-generated analog signals in order to get a fast settling time and easy filtering (like the Adred 103A calibrator does to get 10 +10 = 20 bits of resolution).... Yes, I know, this introduces other problems, which may be just as nasty, and I am not planning to solve all of them.I have not heard of off-the-shelf 32-Bit DACs yet, except that some audiophoolery stuff claims to have them.You sound very much like "been there, done that", while I am just at the beginning of my learning curve on this topic. I am not sure what you are pointing at when you say "with a few counters and op-amps".In the LTSpice simulation, I tried building a Sallen Key filter using the LTC2057, but that did not work well at all. The high frequency components all went right through it - I suppose that's because the GBP of that amp is not high enough. I did not have the idea of putting the filter behind capacitors so that they would not mess with the DC accuracy, so that will be something I'll check out.I just found that the same topic has already been discussed in the metrology section, starting here:https://www.eevblog.com/forum/metrology/ultra-precision-reference-ltz1000/msg272365/#msg272365Looks like I have a lot to read...Thank you again to you all!Johannes

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 11, 2017, 11:06:30 pm
content: Quote from: Krampmeier on December 11, 2017, 10:00:04 pmThere are many things to learn, just by going shopping.Take that with a grain of salt, of course -- there are lies, damn lies, statistics, and application notes, to paraphrase. Appnotes frequently tiptoe around subtle things you might not expect. That said, the superficial information is just what you need, and it's usually as good as anything else you'll find for free on the internet.Tim

author: Echo88
author_rank: Frequent Contributor
timestamp: December 12, 2017, 02:36:36 pm
content: You can find my Fluke 5700A PWM-DAC-Simulation here:https://www.eevblog.com/forum/metrology/2000-post-teardown-and-study-of-fluke-5700a-calibrator/msg1372679/#msg1372679On the first page of this thread you can also find the 5700A service manual with schematics.

author: ogden
author_rank: Super Contributor
timestamp: December 14, 2017, 10:53:40 pm
content: Quote from: Krampmeier on December 11, 2017, 12:25:05 pmFor small-scale experiments microcontroller which is able to do SPI word transmission without gaps, is good enough. Thou most likely you will not get 24 bits using suchIf you have some stm32f1xx - it's SPI will work up-to 24Mbps. Precalculate bit pattern, save into circular buffer and feed it into SPI peripheral continuously using DMA.p.s. I believe that this is just fun project and you cannot do better than existing solutions. Modern DAC's solved problem long ago.

author: Krampmeier
author_rank: Regular Contributor
timestamp: April 30, 2018, 03:11:58 pm
content: Sorry for bringing this old thread up again, but I did continue with the project and as the results look pretty good so far, I would like to share them.I built two prototypes of a 12-bit DAC and implemented the filtering with notch filters (absorption circuits). The later prototype uses a LM399 reference and very stable Megatron resistors.I measured the effect of the filter on the linearity, and I did not find any negative impact. All measurements were done using a Keithley 2010 DMM. The attached graphs show the linearity for 3 different PWM frequencies, with the notch filters at 18, 36, 54 and 72 kHz.I'd say, a linearity well within 2 ppm of the full-scale output between 4% and 99% FS is not too bad, and it proves that the notch filter concept works. With each notch filter, the settling time of the RC filter can be cut in half, so I am optimistic that I have found a neat way to get a simple, fast and low-ripple PWM DAC with high accuracy.At least I should be able to get 19-Bit"ish" performance when I add the secondary PWM channel. Maybe the remaining non-linearities can be improved by re-clocking the PWM signal with the clean CPU clock - I'll have to investigate on that.The video below shows off the first prototype which still used another noise reduction technique which was also suggested in this thread. It works, too, but not as good as the notch filters...

author: CopperCone
author_rank: Super Contributor
timestamp: April 30, 2018, 03:57:55 pm
content: I wanna see a tracking notch filter built with that many stagesYou can use a timing belt and a gear system to track the inductors

author: Krampmeier
author_rank: Regular Contributor
timestamp: April 30, 2018, 04:11:23 pm
content: Ahm, why tracking? The base frequency and the harmonics are at fixed frequencies, just at different levels, depending on the duty cycle...

author: Cerebus
author_rank: Super Contributor
timestamp: April 30, 2018, 04:44:05 pm
content: Quote from: Krampmeier on April 30, 2018, 04:11:23 pmYou still don't seem to have cottoned on that altering the duty cycle, alters the period of half of the wave, which alters the frequency of its constituent sine waves. Try it, draw a square wave, draw a sine wave fundamental that fits it. Now draw a rectangular wave with the same period and a 70:30 duty cycle - try and get that sine wave to fit the new rectangular wave.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 30, 2018, 05:17:17 pm
content: Quote from: Cerebus on April 30, 2018, 04:44:05 pmChanging the duty cycle of a square wave, changes the harmonics. As long as the frequency is constant, so is the fundamental and all harmonics...Tim

author: Cerebus
author_rank: Super Contributor
timestamp: April 30, 2018, 06:45:04 pm
content: Quote from: T3sl4co1l on April 30, 2018, 05:17:17 pmIgnore me, I thought we were revisiting an earlier stage of the discussion (as I remember it) and I was trying to offer an easy to visualise analogy to an argument we weren't actually having.It's been a long day ...

author: CopperCone
author_rank: Super Contributor
timestamp: April 30, 2018, 06:50:36 pm
content: the wikipedia makes it look like it does change frequency

author: Krampmeier
author_rank: Regular Contributor
timestamp: April 30, 2018, 09:44:25 pm
content: Cerebus, no problem, I am glad I am not the only one who learned something in this threadThanks again to all the contributers!Does the shape of the error curves for the different PWM frequencies ring any bells for anyone? The jump at 1.2 V is likely caused by the range change of the multimeter, but why is there a seconds edge at 3.6 V (18 kHz) / 3.0V (12 kHz) / 2.5 V (9 kHz)? That should not be DMM...I also wonder about the cause of the "drop" at the far left. My earlier prototype did not have that, so I think it could have something to do with the transient response of the VREF buffer. If I remember correctly, it appeared when I added capacitance to the VREF...

author: ogden
author_rank: Super Contributor
timestamp: May 01, 2018, 02:13:15 pm
content: Your filter is better than no filter - good. What about comparison to similar complexity ordinary low pass filter? By similar complexity I mean same inductor count and/or filter order. BTW waveform @1:46 video time shows significant high frequency spikes meaning insufficient low pass filtering.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 01, 2018, 02:58:43 pm
content: The reference buffer can definitely be an issue. The classical circuit to drive capacitive load include an extra resistor in the DC feedback. R12 may also be to little minimum current for the transistor. The capacitance at the output also looks rather high - here the details (ESR) can be important. Some capacitance with ESR in the 1 Ohms range might be good, but not too much.The first test should be just one PWM stage (so no fine one) to keep it simple and test that part first. Adding the fine tune is likely the easier part. Using that many AZ OPs can also produce trouble, they do produce high frequency signals that can interact with the PWM modulation and also react to the RF signal reflected back to the OP.I would consider a separate reference buffer for the fine part, to reduce interaction.The 120 Ohms series resistance to the individual switch sides are rather large - this invites errors due to charge injection.Usually the coarse and fine signal can be combined at the PWM filter. So there would be only one buffer after the filter. Another possible error source is the PWM signal coming via a long cable -if required I would consider differential transmission to avoid ground shift errors. The damping network at the digital input is only a partial solution.

author: Krampmeier
author_rank: Regular Contributor
timestamp: May 02, 2018, 11:22:54 am
content: Ogden, you are right that I should do a detailled comparison regaring settling time and ripple for both concepts. At the moment I cannot measure the remaining ripple of my DAC with my equipment, but I'll take it to work and do some spectrum analyzer measurements soon.The high frequency spikes on the oscilloscope are just as high when I short out the oscilloscope probe and touch the output (or the GND, or any other static signal) on my board. It is not caused by insufficient low-pass filtering, but rather by radiated emission and lack of a proper grounding system and board layout. There is also a GND loop via the USB cable to the µC board. I don't worry too much about that at this "proof of concept" stage of the project.Kleinstein, thank you very much for your suggestions! I fully agree that the primary PWM stage must be tested and optimized first, so this is what I am doing. The secondary PWM exists only in the schematic.At the moment, there are more than 10 µF buffer capacitance at VREF (bottom left of the board), with several tantalum and ceramic capacitors in parallel. The schematics are not 100% accurate here. Some of the smaller caps are located directly at the analog switch. This is how I got the best results so far, but I could do a fresh start and check if reducing R12 leads to a better result with lower capacitance.I have already tried different individual resistors in front of the switch. If the resistance gets too small (eg. 10 Ohm), the linearity at the top of the range suffers significantly. Some "zig zag" patterns appear at the right end of the error graph.Slightly higher resistors (180 Ohm) show the same result as I get with 120 Ohm. Much higher resistors (10 k) caused some other problems (don't remember which, I'd have to look at my logs), and would cause an increased TC of the circuit.If I wanted to combine the two filtered outputs without using individual buffers, the PWM filters would have to have an extremely stable output impedance over temperature and duty cycle, right? I don't think I can archive that...There are about 15 cm of cable between the µC board and the analog board. I tuned the dampening network so that the edges look clean right at the analog switch, but of cause this is not perfect. Especially as a 3.3V signal controls a 5V switch - this causes the negative offset of the DAC. I did verify this by using a function generator instead of the µC.I wonder if the digital gates inside the µC, which implement the timer periphery, could cause small timing non-linearities in the 5...30 ps range. I think about adding a re-clocking circuit, but I'd need a really fast flipflop for that...

author: ogden
author_rank: Super Contributor
timestamp: May 02, 2018, 12:11:54 pm
content: Quote from: Krampmeier on May 02, 2018, 11:22:54 amThere's simple solution for that: USB power bank.QuoteI would worry, especially in case when main buzzword of project is "filter"

author: Krampmeier
author_rank: Regular Contributor
timestamp: May 07, 2018, 09:16:45 pm
content: I did not have time to do the math yet, but I did some measurements today.The spectrum analyzer says the notch filters have quite a bit of attenuation. The fundamental PWM frequency, which is at 18.0 kHz, goes down from -46 dBm to -100 dBm or less (below the the noise). The only thing I changed between measurements was routing the signal through the absorption circuit cascade instead of a direct connection to the cap at the output (a whopping 1 µF, by accident).36 kHz and 54 kHz are also just gone. Surprisingly, the 72 kHz are not affected - I'll have to check that notch filter again.There is one extra peak at 17.73 kHz, which does not change if I keep the microcontroller in reset. It disappears when I pull the USB connection to the STM Nucleo board, so I suppose it is just some external noise coupling into the circuit.The rise time measurement suggests that we have a time constant τ of about 36 ms. If I made no mistake, settling time to 24 bits accuracy would thus be about 0.6 seconds, and 0.7 seconds to 28 bits.Not spectacular at all yet. I think I'll have to optimize the final capacitor size now, for reasonable attenuation at the first frequency with is not covered by a notch filter (90 kHz), and then continue from there...

author: ogden
author_rank: Super Contributor
timestamp: May 07, 2018, 09:29:44 pm
content: You shall do also 0..100MHz and 0..1GHz span spectrum measurements. I'm afraid that your filter have insufficient lowpass filtering and you are not looking at whole picture in current measurements.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: June 27, 2018, 08:46:46 pm
content: Krampmeier, the error curves for different PWM frequencies may be caused by analog switch resistance. It looks that you drive switches with RC damping. For different frequencies this damping may possibly cause different average "ON state" resistance of switch.I understand that you are trying to reduce AC everywhere. But the point of PWM at low kHz is that time to change switch state is so fast comparing to duration of cycle, that things like injection charge, or resistance of switch at "IN BETWEEN ON-OFF state" is proportionally lesser. At low PWM frequency and short transitions the curves should look the same. But if you stretch transitions then you introduce frequency dependent factors, which contradicts basic purpose of of using low PWM f in combination to fast switch.