Cheapest FPGA supporting  450MHz SERDES for ADC interfacing - Page 1
Forum section: electronics / general

author: splin
author_rank: Frequent Contributor
timestamp: October 19, 2019, 10:37:28 pm
content: The ADC is the LTC2264-14 which has a two lane LVDS serial i/f - (not JESD204B)It needs to be available in an easily solderable package, so not BGA, and one for which there is free development software.It doesn't look like the ICE40, machx02 or machx03 provide SERDES functionality, but I've never worked with FPGAs before so what do I know?A DDR or DDR I/f might be useful too, but not essential.

author: langwadt
author_rank: Super Contributor
timestamp: October 19, 2019, 11:10:08 pm
content: Quote from: splin on October 19, 2019, 10:37:28 pmI've used spartan6 with an AD9228 a quad 14bit ADC @50MHz, so 700Mbps one each of the 4 data lines

author: splin
author_rank: Frequent Contributor
timestamp: October 20, 2019, 12:04:16 am
content: Quote from: blueskull on October 19, 2019, 10:45:27 pmAh, thank you. I saw the I/O gearing but didn't know what it was - not google friendly search terms! Can you suggest a low cost development board, preferably with lots of memory?

author: splin
author_rank: Frequent Contributor
timestamp: October 20, 2019, 12:14:03 am
content: Quote from: langwadt on October 19, 2019, 11:10:08 pmThank, I'll take a look. Quite a lot more expensive than the machx03 and quite big packages, smallest is TQFP-144?

author: splin
author_rank: Frequent Contributor
timestamp: October 20, 2019, 12:28:41 am
content: Quote from: blueskull on October 20, 2019, 12:09:48 amTo be honest my requirements are a bit vague at the moment; 64M would probably be the minimum. 1G or more would be good but cost would be an issue.Speed would need to be at least 280MB/s for reading/writing the streamed ADC data.

author: langwadt
author_rank: Super Contributor
timestamp: October 20, 2019, 12:54:59 am
content: Quote from: splin on October 20, 2019, 12:14:03 amhttps://www.aliexpress.com/item/1000006703110.html

author: BrianHG
author_rank: Super Contributor
timestamp: October 20, 2019, 12:56:20 am
content: Depending on what you want to do, a MAX10 PLD device might just make it if you use the ADC's 2 bit lane mode.The ADC serial bus is a simple clock & frame and 2 interleaved data bits, so in the FPGA/PLD, you just feed the ADC clock to/from the dedicated PLL clock lines on the FPGA and the data/frame to a balanced DDR/QDR pair inputs, or dedicated balanced serial inputs.When using DDR/QDR inputs, or using a manual home made serdes:The data coming in is just going to a 2 x serial chained D flip flops, clocked at different phases, then those serial chain outputs will be parallel DFF latched on the ADC's 'FRAME' signal.When using a dedicated serial inputs, you can use the FPGA dev tool's serdes generator tool which will most likely auto-generate this code for you and feed you a parallel data & data_rdy signal.Your ADC will most likely eat 1 PLL inside the FPGA wherever you may source your clock from.Max10 in TQF 144 pin package:https://www.digikey.com/products/en/integrated-circuits-ics/embedded-fpgas-field-programmable-gate-array/696?FV=-8%7C696%2C16%7C95614&quantity=0&ColumnSort=1000011&page=1&k=max10&pageSize=25&pkeyword=max10Too bad on not using BGA, there are larger Max10s which will probably be good enough for your project.Max10s do not require a bootprom, it is internal.

author: splin
author_rank: Frequent Contributor
timestamp: October 20, 2019, 02:11:01 am
content: Quote from: blueskull on October 20, 2019, 01:28:50 am64M Byte

author: asmi
author_rank: Super Contributor
timestamp: October 20, 2019, 02:29:57 am
content: Quote from: splin on October 19, 2019, 10:37:28 pmBGA IS easily solderable. The only thing you need to solder it is a bit of a tacky flux and a hot air gun (even the cheap one from ebay will do).Quote from: splin on October 19, 2019, 10:37:28 pmPretty much all DDR memories are only available only in BGA packages (except for some old DDR-1), and most FPGA chips that are capable of driving DDR2/3 memories, have BGA packages. QFP packages just don't provide signal integrity good enough for fast DDR2/3 interfaces.

author: splin
author_rank: Frequent Contributor
timestamp: October 20, 2019, 02:43:16 am
content: Having been pointed to the Spartan 6, I see that the 3A supports 640Mb/s io rate and also has DDR and DDR2 support but is cheaper and comes in smaller packages. That probably wouldn't be a benefit though if I were to go for DDR memory - how many pins would be needed for a 64MByte, 14 bit wide memory bus?Is the development software free?Can you use the DDR IP for free or do you have to buy a licence to use it?Not having ever used FPGAs or even got involved with high speed layouts, is a DDR implementation a totally unrealistic goal? It's a far cry from the 8MHz DRAM designs I was familiar with back in the 8086 days!I assume that there are plenty of examples of layouts that could be copied easily enough, but debugging it would be a very different problem with only a 2 channel 1GSPS scope! Ok, I'd probably have to buy something but I wouldn't want to pay much more than £1000.

author: langwadt
author_rank: Super Contributor
timestamp: October 20, 2019, 02:52:36 am
content: Quote from: splin on October 20, 2019, 02:43:16 amI'd say spartan3 is too old, spartan6 is already pushing it and only supported byt the older Xilinx tool

author: splin
author_rank: Frequent Contributor
timestamp: October 20, 2019, 02:56:16 am
content: Quote from: asmi on October 20, 2019, 02:29:57 amOk, that's encouraging.QuoteAh, ok. But with BGA comes expensive 6 or 8 layer PCBs to break out the pins? Worse, .5mm pitch BGAs also require much more expensive small track width and clearance manufacturing capability ruling out the usual cheap vendors? 4 layers would probably be needed for signal integrity, but I believe the price increases sharply above that.

author: asmi
author_rank: Super Contributor
timestamp: October 20, 2019, 03:06:21 am
content: Quote from: splin on October 20, 2019, 02:56:16 amIt is possible (though not easy) to route DDR3 x16 interface on a four layer PCB, and this interface will give you a ton of bandwidth (Artix-7 FPGA in speed grade 2 can drive it at 400 MHz, so 800 million transactions/second x 16 bit = 12800 Mbit/s of max bandwidth). These boards are quite cheap at JLCPCB for example ($30 or something like that). For ease of layout I prefer to use 6 layer boards made at WellPCB, and they come at about 130-150$ for ten boards, which is incredible value if you think about it.DDR2 an DDR3 chips have 0.8 mm ball pitch, and most Spartan-7 and Artix-7 packages have 1 mm ball pitch, so it's possible to route them out without using advanced PCB tech like microvias. WellPCB allows for 3/3 mil traces and down to 0.15 mm vias, and JLCPCB goes down to 3.5/3.5 mils and 0.2 mm vias, both are perfectly adequate for routing out 0.65 mm pitch BGA and up.Xilinx provides free DDR/DDR2/DDR3/DDR4 memory controller IP for all of its' FPGAs (not all types of memories are available for all FPGAs), you it's got you covered as far as usage goes. Their Vivado IDE is also free for smaller FPGA chips, which includes entire Spartan-7 and Artix-7 lineups.

author: splin
author_rank: Frequent Contributor
timestamp: October 20, 2019, 04:40:20 am
content: Quote from: asmi on October 20, 2019, 03:06:21 amGreat information, thanks. BGAs are definately an option then. I see LCSC havd some good prices for Spartan 6 devices - XC6SLX25-2FTG256C @ $10 for example but I don't know how reliable the supply is.A DDR3 design would likely be a challenge too far; even DDR may well be too diffcult, especially if it didn't work first time. It looks to me that you take months or more to get to grips with a DDR3 datasheet! Perhaps I'm too pessimistic but 44 subnotes to the AC timing section doesn't bode well.

author: splin
author_rank: Frequent Contributor
timestamp: October 20, 2019, 04:46:08 am
content: Quote from: blueskull on October 20, 2019, 02:58:01 amThanks for the suggestion, but for my limited quantities there's no chance of getting any meaningful vendor support and I seriously doubt there would be much user group or forum support available for a relatively obscure part.

author: splin
author_rank: Frequent Contributor
timestamp: October 20, 2019, 04:54:09 am
content: Quote from: BrianHG on October 20, 2019, 12:56:20 amThanks, very helpful. BGA may be an option. I'll have a look at the MAX10. Another consideration is which devices are the most popular as this will have a big impact on the amount of help/advice available on forums which I would certainly need!

author: asmi
author_rank: Super Contributor
timestamp: October 20, 2019, 05:34:50 am
content: Quote from: splin on October 20, 2019, 04:40:20 amI think MCBs in Spartan-6 do support DDR-1 memory (though I haven't worked with them personally). For 7 series FPGA only DDR2 and DDR3/DDR3L are supported. It's not very hard to route them, and MIG User Guide (UG586) has everything you need to know to successfully implement such interface. You might want to to download the user guide and skim through DDR3 section.As a sort of encouragement I will also tell you from my experience that I got it working on a first try, and actually never had any problems with DDR3 on several of my boards. And I implemented DDR3L low power version which is less tolerant to PCB layout than regular DDR3 interface because of lower noise margins. So it's definitely not as complicated as many believe. In part it's because the interface is working at relatively low (for DDR3) frequency of 333 or 400 MHz, while the specification allows frequencies of up to 933 MHz (I think).If you decide to go for it, feel free to ask any questions here and I and others will be happy to help you out!

author: BrianHG
author_rank: Super Contributor
timestamp: October 20, 2019, 05:40:14 am
content: Quote from: splin on October 20, 2019, 04:40:20 amWhen using the available DDR2/3 controller megafunction within Xilinx's Vivado IDE, it controls the DDR2/3 ram's timing for you. Internally, within Vivado, you access the memory as if it were parallel static ram with double or quadruple the data bus size of the connected ram chips. (IE, Address, R/W, Data in and out, and RDY) The megafunction takes care of controlling and timing the DDR2/3 memory control lines and signal timing. You just need to wire them to the correct pins on the FPGA. (Same for Altera/Intel's Quartus Prime IDE).You got a lot of reading up at Xilinx's site on their DDR2/3 memory interface controller with it's setup and features.Same goes for Altera's/Intel's FPGA site.

author: asmi
author_rank: Super Contributor
timestamp: October 20, 2019, 05:45:28 am
content: Quote from: BrianHG on October 20, 2019, 05:40:14 amExcept Antel will want you to pay a lot of money for DDR3 controller