FPGA noob questions - Page 1
Forum section: electronics / beginners

author: jnz
author_rank: Frequent Contributor
timestamp: October 12, 2017, 06:43:14 pm
content: I'm sure a lot of these have been asked before, but if I was smart enough to just search maybe I wouldn't need to ask in the first place!?How do I actually determine the "size" of an FPGA, I've seen everything from cells to gates to logical blocks to macrocells in a PSoC, LUTs, etc. What are these things? Is there a standard that everyone uses?How do I know if my "application" will fit on X or Y FPGA? It seems to me the only way to do that would be to synthesize it and see how "big" it is. This would pretty much mean I need to select a line of chips and it's IDE/Suite/Environment just to get started right?PSoCs don't include "real" FPGAs ... but what does it lack? From what I see a "real" FPGA runs a lot faster like easily in the 400Mhz+ range and as I understand it the PSoCs top out at their core speed. Any other interesting gotchas about PSoCs?What is an FPGA Transceiver that some parts have? I get the idea sort of - but FPGAs aren't analog and they don't operated in a wide voltage range. Is this hat the built in transceivers do? But for example, I couldn't make a CAN Bus transceiver inside an FPGA right?On the topic of bitstream reversing... it kind of seems impossible to get that back into a readable function if you were trying to do that. What is the process of doing that? It wouldn't be like reading code, would it be like following traces into different types of gates?FPGAs unlike micros opperate their "programming" all the same time sort of as I understand it... But when you hit an always@ block that is long and has a lot of "code" in it, all of that still has to happen kind of in sequence right? like if I have a for loop in there that's executed on a clock edge and it runs from 0-10, is that representative of 10 more edges until it finishes? If that's the case though, you could easily over-run your desired effect with any loop, so that doesn't make sense.Take it easy on me.

author: Ice-Tea
author_rank: Super Contributor
timestamp: October 12, 2017, 06:57:11 pm
content: QuoteThere is no standard. It means something different for every vendor (per example, one block may have a different size LUT, 2FF's instead of 3 or whatever.QuotePretty much. Even though if you are planning to integrate a certain function you will probably find some documentation on it with typical implementation data to help you gauage things.QuoteNot my areaQuoteRegular FPGA pins will support a wide variety of 'regular' IO standards. With dedicated transceivers you can serialise data in a single differential data stream whose speed exceeds by far the 'regular' IO. Think more like the front end bus of a processor instead of a CAN bus.QuoteDon't know of anyone who does this. Don't really see the point either, unless you are reverse engineering something or trying to build an open source fitter or something.QuoteYou're still thinking in software terms. You are instantiating hardware, it does not 'run' code.

author: rmacintosh
author_rank: Regular Contributor
timestamp: October 12, 2017, 07:44:52 pm
content: Quote from: Ice-Tea on October 12, 2017, 06:57:11 pmExactly.Forget about code, loops and all that.Your code becomes hardware.https://embeddedmicro.com/tutorials/mojo/timingRead up this link...A condition similar to what is encountered in embedded software (eg. loops) where blocking code can really mess with the flow and timing of a microcontrollers intended operation. An FPGA can have timing issues where you have crammed too much combinatorial logic (/w propogation delay greater than a clock cycle) between two flip flops which would trigger on clock edges.

author: jnz
author_rank: Frequent Contributor
timestamp: October 12, 2017, 07:54:50 pm
content: I know the "code" becomes hardware. What I don't really get is if you "code" a loop... it still has to run sequentially right?

author: jmelson
author_rank: Super Contributor
timestamp: October 12, 2017, 07:58:33 pm
content: Quote from: jnz on October 12, 2017, 06:43:14 pmIt is a marketing trick to CONCEAL this info from you. Just use the free tools and code up your application, and then see what device it fits into. Then, make sure to leave 20% or so space to handle any changes.Quoteyes, all part of their PLAN to lock you in...QuoteNO! That's the whole point. It is NOT sequential! All statements in the block are evaluated in parallel. Now, there are some tricks done so that the last line (in the source code) listing that assigns a value to a signal is the one that takes precedence, so that sort of fools you into thinking there's something sequential going on there. But, it is not sequential, it is some hidden equivalent of an if then else if kind of logic.QuoteAll for loops are unrolled during the synthesis. So, if you have some FFs created by assigning a signal in the loop, it really instantiates 10 FFs in hardware, rather than re-using the same FF 10 times. All 10 FFs persist forever, so all 10 output states of the FFs exist in parallel and can be used by other logic at any time, not just when the for loop is "evaluated".Hope that explains the difference between the sequential CPU mindset and the parallel FPGA mindset.And, there are places where going sequential in an FPGA can save a lot of resources, like when you need to only sample an input at a slow rate, or don't need to hold a lot of state once you've processed some task.Jon

author: rstofer
author_rank: Super Contributor
timestamp: October 12, 2017, 08:24:20 pm
content: You need to wrap your head around the idea that EVERYTHING happens in parallel. You may read the code from top to bottom but that's not how it is synthesized. This is a HUGE concept and takes a bit of time when coming from a software world. It's easier if you come from a hardware world and understand things like Finite State Automata (or Finite State Machines).FSMs are the primary way you get sequential operation. Logic equations, unclocked, don't get you very far. You might as well use a ROM. But once you throw in flops and then add the concept of FSMs, you can build very powerful systems.In a lot of ways, FSMs are like switch() statements in C. They look a lot alike on paper but there are substantial differences between software and hardware.Buy a really big device on a board with lots of gadgets and when you have finished development, port the code to a smaller device. Or not...Sometimes you use a larger device, not for the logic cells, but for the internal BlockRAM. You may want to build a small CPU and you don't want to mess around with external DDR memory and other nonsense. You would, instead, select an FPGA with enough BlockRAM to support your CPU (assuming that you memory size is reasonable). In the old days, I had a hard time getting 32k x 16. These days I can get a lot more so my projects can be somewhat larger. 65k x 32 bits is pretty easy to come by.You might implement some wild peripheral that works with some bizarre protocol. In the end, it may be easier to create a little CPU to drive the peripheral than to write HDL. I have never implemented TCP/IP on an FPGA. If I did, the first thing I would do is find a small CPU core for which a C compiler exists and port an existing stack. Then I would implement my bizarre peripheral. Or use one of the chip vendors cores like Xilinx's Microblaze.Or, look at the new Zynq processors that include a couple of ARM cores with the FPGA fabric. Now I can run Linux and still have my peripheral blazing away.

author: jnz
author_rank: Frequent Contributor
timestamp: October 12, 2017, 08:41:53 pm
content: OK OK OK....I kinda what you guys are saying... but...block/whatever awalys @ something something [reg x = some_wireif (x == 10) beginsome_register = 1x-=1endif (x % 2 == 0) beginsome_register=0end]Super bad example, but what about things that would have different results depending on the order they were executed in? Or am I mistaking the x-1 part can't be done like that? Considering the possibility of a better example... Are you guys saying that inside a block, that x%2==0 and x==10 are being evaluated at the same time? Could I do the x-=1 (obviously using Verilog equivalent) and that's ok because x%2 already ran as well? It won't check modulo2 after I removed one value from x, right? BUT - this means the value of x is checked in one clock cycle and then would be incremented in another right? OR does all this happen in one clock cycle?Also, rstofer, are you talking about a system where you have an FPGA and a CPU that you're using the ram together on? What do I even do with RAM in an FPGA for the most part? Like I can see if I have a ton of registers, but is that all I'd use RAM for in an FPGA? A wire shouldn't take RAM right? A complex math function will just "become hardware" and also won't need to be ram, right?

author: jnz
author_rank: Frequent Contributor
timestamp: October 12, 2017, 08:44:51 pm
content: Also, glad to hear that LUTs and Blocks and Cells and whatever are sort-of intentionally confusing. Makes sense esp when looking at vendor lock-in.So....In terms of say a PSoC4/5/6... How close to they are to "real" FPGAs? It seems for a lot of projects I see the appeal... I'm just assuming you can tie the FPGA direclty to at least some CPU registers. Right? Any other interesting things to know about those?

author: taydin
author_rank: Frequent Contributor
timestamp: October 12, 2017, 09:21:58 pm
content: FPGA stuff is new to me as well, but as far as I understand from previous responses, the code you write (VHDL I presume) just describes the hardware. Think of it like HTML, which describes how the web page will look like. Once the hardware is written into the FPGA, it runs as pure hardware, with logic gates, flip flops, counters, decoders, adders, schmitt triggers ...

author: rstofer
author_rank: Super Contributor
timestamp: October 12, 2017, 10:12:50 pm
content: Quote from: jnz on October 12, 2017, 08:41:53 pmRAM won't usually be used for registers, that is the purpose of flops at the output of logic cells.Having RAM is one of the big things that separates CPLD (Complex Programmable Logic Devices) from FPGA and is one of the most critical resources.Suppose your magic CPU project just screams for a VGA text display. Well, you might need about 12k x 8 of RAM/ROM. ROM is simply RAM that is initialized at startup. So that is one use for BlockRAM. Or, suppose your project needs a little central RAM - there's another use. Maybe you need code translation tables - ROMs, really, but still in BlockRAM.Here's a REAL project: I built an FPGA implementation of the old IBM 1130 computer. It runs all of the factory software, unaltered. Internally, text type data is encoded as EBCDIC. One input device is a card reader which is assumed to feed the 1130 with Hollerith codes. I needed an ASCII->Hollerith translation table (ROM), the IBM code translated between Hollerith and EBCDIC. One output device is the line printer and it required yet another table - EBCDIC to printer code was handled by IBM but I needed ASCII. And so on.The CPU wants 32k 16 bit words and, initially, I couldn't fit that into the FPGA. Today it is easy. BlockRAM is FAST and it is dual ported! Can you imagine how well that works with a DMA channel feeding all the peripherals from one port and the CPU running out of the other port?The real machine ran at 400 kHz and my version runs at 50 MHz. That 27 pass Fortran compiler just smokes in comparison.I used ROM for code translation, you might use it for sin/cos lookup. Or some other table of useful constants. Maybe you need to linearize some transfer function so you do a little lookup.BlockRAM is a vital resource - more is always better!There is also distributed RAM but I believe that turns out to be the flops in the logic cells.

author: rstofer
author_rank: Super Contributor
timestamp: October 12, 2017, 10:28:09 pm
content: I just started playing with the PSOC 4 so I can't say much about its FPGA capability. I will say that I like the toolchain and the idea that I can diagram my hardware and the tools will create all the API files I need. I just need to call the functions that have been generated for me.If you can get a PSOC 4 -042 board like the one used in the PSOC 101 videos, do it! Work through the videos and see what you think. I'm impressed and I have only been playing for a couple of days.http://www.cypress.com/training/psoc-101-video-tutorial-series-how-use-arm-cortex-m0-based-psoc-4There is a separate series for the PSOC 6 board but there won't be a board until the end of 1st Qtr 2018 - bummer...There are also some BLE cards and I have one but I haven't gotten into it just yet. Also a -042 main board.I decided to buy the exact board used in the demos. I didn't want to have to get creative right out of the gate!I don't think I would confuse a PSOC with an FPGA. I know I can define some logic elements (gates, flops, etc) but I doubt that I could build a complete SOC from the fabric. Eventually I will look into this.

author: ataradov
author_rank: Super Contributor
timestamp: October 12, 2017, 10:38:22 pm
content: Quote from: jnz on October 12, 2017, 08:41:53 pmAnother useful thing to remember - not everything you write can be synthesized into hardware.This code will not be synthesizeable. You can still use it for simulations, but it won't result in any hardware.Verilog has print statements, they won't do anything in hardware either.You kind of need to start with a circuit in your head, and then write the code to describe that circuit, not the other way around.

author: Back2Volts
author_rank: Unknown
timestamp: October 12, 2017, 11:14:23 pm
content: Quote from: rstofer on October 12, 2017, 10:12:50 pmHow did you manage to get your hands on the 1130 OS and Fortran compiler ? It must have been quite a while since the last 1130 was decommissioned. (IIRC, my brother worked with an 1130, late 60s / early 70s, doing statistical work at a university hospital. )I think you deserve a one liner in the "1130s Today" section of the Wikipedia pagehttps://en.wikipedia.org/wiki/IBM_1130#1130s_today

author: rstofer
author_rank: Super Contributor
timestamp: October 12, 2017, 11:37:06 pm
content: The whole notion of 'what gets evaluated when' comes down to blocking versus non-blocking assignments. I'm a simple guy, I use non-blocking assignments on signals and darn little else.I am only interested in synthesizable constructs. I'm building hardware, not code for simulation.You will use default assignments when you create FSMs. In fact, you must define every signal in every state, you can't leave things floating (or you will infer a latch - bad juju...) so you will see these default assignments at the top of the combinatorial process of the FSM. Every signal that is changed in the state machine process must be define in every state. You either provide a default value once or you define a specific value in every state.If you fail to do this you can guarantee your state machine will fail! As you expand your combinatorial process and add new signals you will invariably forget to provide a default value. The FSM that worked a minute ago is suddenly catatonic. There's a reason I know this! I can't begin to count the number of times I messed this up...

author: Back2Volts
author_rank: Unknown
timestamp: October 12, 2017, 11:49:58 pm
content: Quote from: rstofer on October 12, 2017, 10:28:09 pmjnz,I have not touched FPGAs ($8 ICE40 waiting on my bench), but I have played a bit with PSoC 4 and 5 kits CY8KIT-43 and -59 respectively (about $10 each stick) . What I found, a bit frustrated, with the -43 is that it was fairly easy to run out of resources on the digital-hardware side. The processor on the -43 stick contains only 4 UDBs. I believe the -42 has also 4 UDBs. On the other hand, IIRC, the -59 has a PSoC 5 processor with 24 UDBs which should give more room to play.

author: rstofer
author_rank: Super Contributor
timestamp: October 13, 2017, 12:00:47 am
content: Quote from: Back2Volts on October 12, 2017, 11:14:23 pmEverything came with the simulator here:http://ibm1130.org/If it hadn't, I would have had to create the assembler myself and type in all the code from the microfiche that I have (somewhere). Brian Knittel's assembler really made the project possible. I had to write test code for every instruction!I started doing business applications for my employer using the 1130 and Fortran back in 1970. I also used it for homework until I graduated in '73. In '72, it was uncommon for students to turn in computer generated Bode' Plots. Very cool!I started to build a microcoded version some time in '74 or so but RAM wasn't really available and the Altair 8800 came along so I put the project on back burner. I retired in '03 and by '05 or so I decided to try my hand with FPGAs. Creating the machine was an adventure. The code is horrible and I really need to rewrite it but I lack the motivation to recreate what is essentially 10k lines of code. It's not just the CPU, it's the card reader, typewriter, keyboard, printer, disk, DMA channel and plotter. Yes, I even have the plotter. It directs output to my LaserJet using HPGL. For that I slipped in an mbed board with the FPGA sending IBM codes over SPI and the mbed restructuring the commands and sending the output over TCP/IP.There's a video of a presentation I made at the 11/30 party a few years back over at ibm1130.org. I got to meet the author of "Programming the IBM 1130" (Robert K Louden). Interesting guy!This machine has been a 47 year love affair - I still use it for some Fortran applications and write a little assembly code once in awhile.I try to keep this thing on the down-low. I'd rather not get worldwide attention. The code isn't explicitly copyrighted but it's clearly proprietary. Nobody seems to care, there's even a Google group so it isn't like a secret that the simulator exists (Brian's simulator work is magnificent, BTW) but still, down low. Brian has a real 1130 as does Carl Claunch - both in the Bay Area. Lucky guys...Heck, I couldn't afford the electric bill! I'm not sure where to buy punch cards and unburst paper. Plus I would need a keypunch...

author: Back2Volts
author_rank: Unknown
timestamp: October 13, 2017, 12:45:13 am
content: rstofer,I have no doubt it must have been a very fulfilling hobby for you !

author: rs20
author_rank: Super Contributor
timestamp: October 13, 2017, 03:13:17 am
content: Quote from: jnz on October 12, 2017, 08:41:53 pmDownloadispLever Classic, and synthesize your design. You'll either encounter synthesizer errors, or see the generated hardware in terms of easy-to-understand flipflops (seeherefor a forum post I made with included some of this output.)This way, you don't need to speculate or ask others how any given block of VHDL or Verilog is synthesized, you can just go ahead and see it with your own eyes. The reason I suggest ispLEVER classic in particular is that it works with the ispMACH 4000 parts, which have an incredibly simplistic structure (basically just a pile of flip flops) and therefore very easy-to-understand fitter output.The added bonus is that if any given design you come up with synthesizes in a tool like ispLEVER classic, you know that it is actually physically realisable (unlike print statements and those #delay statements), and you can actually load it onto a real dev board. Or you can simulate them using the provided simulators; which are much more accurate than the theoretical simulators you'll otherwise find which don't take internal delays and stuff into account.In summary, stop asking questions, just dive and get started already!

author: dmills
author_rank: Super Contributor
timestamp: October 13, 2017, 04:40:06 pm
content: At least for VHDL, the way to see a combinatoric process block is that the order of signal assignment describes priority not sequence (And all assignments actually happen in parallel at the end of the block), note that variables are a whole other animal.if statements (not involving clock edges) beget multiplexers, if statements involving clock edges form registers.Multiplexers, like simple logic collapse to LUTs.Loops and such are always fully unrolled (which means that you have to have constants for loop count limits).Regards, Dan.

author: james_s
author_rank: Super Contributor
timestamp: October 20, 2017, 11:23:20 pm
content: At least in Altera Quartus you can select a family-auto for the FPGA and when you compile the project it will tell you what the smallest part in the family it will fit in. Often times you'll be doing your development work on a large FPGA anyway and then when it comes time for real hardware you figure out the cheapest part that will meet your needs.The most important thing you need to drill into your head when learning FPGA development is YOU ARE NOT WRITING SOFTWARE, tattoo it on your arm if you have to. FPGA code *looks* like software but it isn't, you are describing hardware in a special language that superficially resembles a program but it isn't. THINK HARDWARE, visualize the circuit you want to create, the code will almost write itself.Something that may help, for the moment forget about the specific language, just look at the schematic of a digital circuit and describe in words what it does. Pretend you are going to explain to someone through text how to build a circuit that does what your circuit does but without giving them any schematics or part numbers. Now try to think of VHDL or Verilog in that context, it's not a programming language, it's a language tailored to describing the function of digital circuits. If you want any kind of looping or iteration you need a counter or a FSM, circuits that can be built out of real, physical hardware. If you can't build it out of real digital hardware then you can't write synthesizable HDL.