Need a  Cadence Allergo pcb layout review for common mistake - Page 1
Forum section: electronics / general

author: Md Mubdiul Hasan
author_rank: Regular Contributor
timestamp: September 18, 2025, 07:55:54 am
content: Hi there,I wanted to learn more the about the routing, specially in Allergo.Attached file is a messy one and you may not like it.Kindly go through the SCH and layout and make your comment,For example1. Wrong routing2. Wrong spacing3. Violating DRC4. Sensitive Net and PADS5. Unnecessary ViasNOTE: Only Cadence designer should comment here.

author: Uky
author_rank: Regular Contributor
timestamp: September 18, 2025, 01:20:10 pm
content: Hej/Hi,Once you get the hang of Allegro, you will find it to be a verypowerful tool. Learning threshold can be high but well worth the effort!(No schematic file included. Only ".opj" the project file. Not necessary.For a schematic review - include the .DSN.Bottom layer has no net: IMO - assign to GNDTop layer can have a GND-plane. Won't hurt.Stitching GND vias could be placed around board edges.Isolation between traces on bottom plane can be increased:(N00928/N01469) (OUT/MID) (MID/N00649) (MID/N00932)R8, Q5, Q6 not connected to GND.Q5 pin 2 assigned to 9V but not connected.Reference designators on layer ASSY can/should be placed inside componentextensions. Reference designations in SILK shall be placed outside the component.Keep all annotation orientations at either 0 or 90 degreesThere are several traces that can be separated. No need for having them to close.The assembly layer can have line widths set to very small, ie. 0.01mmThis will make document print outs look better.Reference designators on Silkscreen missing.(Often not desirable and can be omitted when preparing manufacturing files)Silk screen can go down to 0.1mm.No DRC rules found in the layout.Cheers.

author: Md Mubdiul Hasan
author_rank: Regular Contributor
timestamp: September 18, 2025, 03:00:56 pm
content: Hej, @Uky. Nice to get your feedback.I am nearly 2.5 years in Sweden, I only speak English here.I will get check to you after I check all the issues. Keep in touch.Attached is .DSN file here.

author: Md Mubdiul Hasan
author_rank: Regular Contributor
timestamp: September 19, 2025, 08:29:40 am
content: Hi,Thank you again to help me here. I just put my feedback here.I beg pardon for my ignorance.QuoteKindly check my last reply.QuoteYes, good point here. What I did is, I select the Shape > Polygon or Shape > Rectangle tool, then in the Options panel, I set the active subclass to the desired bottom-layer, set the net name to "GND", draw the shape, and then perform a Dynamic Fill to complete the plane.I had another copper plane, but now I can see blue GND has appeared.QuoteDo you want me to make another GND in top layer ?QuoteDo you want me to do, Place > Via Array command and configure the array parameters for a grid of vias, ensuring the vias connect to the GND net?Kindly see the Option setting, what to do here ?QuoteShould I do it manually or, from design workflow >Constraints >Net>All layer spacing ? what to do here ? suggest kindly.Should not I do, Setup> constraints>Modes>spacing > Line to line enable the check mark ?QuoteKindly edit them if possible, sch and layout back and forth update.QuoteWhere to check them?QuoteShow me the setting.QuoteTell me specifically.QuoteShow me the setting.QuoteWhere it is?(Often not desirable and can be omitted when preparing manufacturing files)QuoteKindly show me.QuoteLet me know here to set it.Cheers.

author: Md Mubdiul Hasan
author_rank: Regular Contributor
timestamp: September 30, 2025, 12:20:37 pm
content: Hi Uky,Hope you are well, passing a busy time may be.Attached file is an updated one.BR

author: Uky
author_rank: Regular Contributor
timestamp: October 02, 2025, 05:47:26 pm
content: Apart from that you have used very small text sizes (0.6mm height) and thatthe orientation of some of the reference designators are not uniform, the layoutchecks out OK. (Q2 missing in assy) Have not checked power dissipation of the power semiconductorsif there is a need to have them attached directly to GND or +V without heat relief tracks.Cheers

author: Md Mubdiul Hasan
author_rank: Regular Contributor
timestamp: October 03, 2025, 12:55:30 pm
content: Hi @Uky, thank you to respond here.QuoteWhich design you are talking about, the one that I have uploaded in my last reply ? If you give some screen shot it will be understandable.QuoteI am sorry, let me know where and how to check it.May be my second design looks fine, it had some issues in DRC but I ignored it.I will be happy if you could answer my last questions that I asked you after your first reply.It will give some overall information to understand the pcb modification.Cheers