Oscillations! Linear variable PSU - Page 1
Forum section: electronics / projects

author: Datguy123
author_rank: Contributor
timestamp: May 17, 2020, 03:00:04 am
content: Hi,Hopefully someone can help me! I've been stuck on this problem for a week.I'm designing a linear variable PSU which can output 45V@6A. It was put together with whatever I know about electronics (I'm a rookie) and it managed to work until I started load testing with heavier loads (from a 100 ohm load to a 6 ohm load). What happened was that high-frequency oscillations (around 1 to 5Mhz) started appearing as I increased the output voltage and consequently the current. This is a prototype circuit and I have built it on perfboard and have long wires everywhere (between the reservoir capacitors and the output transistors, output transistors and feedback resistors...) presumably causing the oscillation problems. The initial oscillation was periodic and has an amplitude of around hundreds of millivolts to several Vpp which increases and starts merging (the envelopes joins together to form a constant oscillation) with the output current/voltage. The oscillation is not sinusoidal like and looks "chaotic". Furthermore, the oscillation seems to be "polluting" the entire circuit, as upon probing I realized was superimposed to all signals in the circuit, making it hard to locate its origin.I suspected it was the output transistors causing the oscillation, so I added 1nF capacitors between the collectors of the output pairs and the heatsink (C15 and C16) as well as 4.7 ohm base stopper resistors (R2 and R6). However, the addition of the capacitors caused the oscillations to increase instead. By experimentation, I left 1nF C15 in because it reduces the oscillations (C16 does the contrary). This pushed the voltage before the oscillation starts higher, but in no way removes the oscillation. Grounding the heatsink reduces the "chaotic" behavior of the oscillation.I started to probe around the circuit and realized that whenever I probe the collector of driver darlington transistors (either one, Q1 and Q13), the oscillations will magically go away. My initial thought was that the capacitance of the oscilloscope probe was bypassing the oscillations to ground, so I did just that by using 12pF for C13 and 1nF with 12pF for C14, which pushed the point where oscillation starts higher. It is weird that if I use 1nF for C13, the output oscillations will increase.I've tried other things as well, listed below:1. Smaller bypass capacitors (100pF) for C15 and C16, only reduces the amplitude of the oscillations2. 4.7k base stopping resistors for Q1 and Q13, but resulted in way bigger and weirder oscillations (in the whereabouts of 5 to 6 Vpp at 11 volts output!). With this, oscillations are found to start from the base of Q1 and Q13 and not from the differential pair circuit.3. 100pF C19 and C20, but does not remove the oscillation.I am lost as I am unsure if the problem is because of the circuit design or layout. I am also unsure why adding slightly bigger capacitors would cause bigger oscillations (for C13). I hope my description of what I have done is not too messy and any help would be appreciated! Thank you for your patience because this is a rather long post.Please note!1. The LtSpice schematic is ONLY used to visualize the circuit2. The operational amplifiers in the circuit are in fact LM358 (not OP747). U7,U8 are in a single package, similarily for U5 and U63. The circuit works by splitting the voltage drop equally between 2 pairs of transistors (X volts across Q2, Q12 and around X volts across Q3, Q11). Ideally, at 0V output the emitter voltage of Q2 and Q12 is 25V4. -15V, +12V, and +2.78V rails are powered from the same transformer but from a separate winding.

author: ogden
author_rank: Super Contributor
timestamp: May 17, 2020, 05:10:40 am
content: Where's schematics of actual circuit? Sorry, but your "distributed rats nest PSU" is full of feedback antennas, no wonder it oscillates. I won't even consider working on frequency/stability compensation for such circuit & layout unless error amp, power amp and output transistors are on compact perfboard w/o wires flapping around.

author: Datguy123
author_rank: Contributor
timestamp: May 17, 2020, 05:41:36 am
content: Quote from: ogden on May 17, 2020, 05:10:40 amMy bad, forgot to attach the circuit. Thanks for your advice, I'll try to clean up the layout but do you think there's anything apparent in my circuit that could attribute to the oscillation?

author: xavier60
author_rank: Super Contributor
timestamp: May 17, 2020, 06:03:17 am
content: When I was rats nesting my project I kept the loop consisting of the pass transistors and bypass capacitors confined to a small area at the heatsink.https://www.eevblog.com/forum/projects/linear-lab-power-supply/msg2028295/#msg2028295

author: gbaddeley
author_rank: Regular Contributor
timestamp: May 17, 2020, 06:40:17 am
content: U5 & U7 are open loop at DC, too much gain! The driver transistors should have a base stopper 22 - 100 ohms. Get rid of c10. Why are you using the 2 x transistor diff stage? There are easier ways to do level / current shifting.

author: xavier60
author_rank: Super Contributor
timestamp: May 17, 2020, 07:01:30 am
content: The Darlingtons should be driven in the same way that works well in audio amplifiers. A Voltage Amplifier stage consisting of a capacitively loaded trans-conductance amplifier. The opamp will need to have some proportional gain for loop stability.https://electronics.stackexchange.com/questions/254375/purpose-of-voltage-amplifier-vas-in-three-stage-amplifier-design

author: ogden
author_rank: Super Contributor
timestamp: May 17, 2020, 09:10:05 am
content: Quote from: Datguy123 on May 17, 2020, 05:41:36 amSorry, but your circuit is rats-nest as wellMain beauty of best hobby engineering projects is simplicity. Why two stages in series? My advice - divide your project in logical steps, work on single suply until it is running, only then add/connect 2nd.

author: xavier60
author_rank: Super Contributor
timestamp: May 17, 2020, 10:09:55 am
content: This is the most simple way to level shift drive up to the high-side.

author: Datguy123
author_rank: Contributor
timestamp: May 17, 2020, 11:19:36 am
content: Quote from: gbaddeley on May 17, 2020, 06:40:17 am.Hi, would it be a big problem for U5 and U7 to be open-loop at DC? If so what changes do you think I can make? I used the diff pair because a single common emitter would introduce a 180-degree phase shift and I don't think the NFB would work. In my previous design, I used dual common-emitter stages together to shift the phase back to 0, but I think a diff pair is more "refined". C10 was added to remove a 300++khz oscillation when the power supply is unloaded; not sure if this is normal tho. Would try out a lower value for the darlingtons.

author: Datguy123
author_rank: Contributor
timestamp: May 17, 2020, 11:34:06 am
content: Quote from: xavier60 on May 17, 2020, 07:01:30 amHi, so are you saying the Darlington should be configured to have both voltage and current gain? I have no formal education in EEE so I am not sure how much gain the op-amp should have. My plan was to use the diff pair as the VAS and use the temperature stability of the op-amp to correct the errors in gain using NFB. The darlington was used to provide large current gain at high output voltages when the current in the left side (Q9 and Q17) is low.

author: xavier60
author_rank: Super Contributor
timestamp: May 17, 2020, 11:52:09 am
content: Quote from: Datguy123 on May 17, 2020, 11:34:06 amJust like with an audio amplifier, the Darlington's current gain buffers the VAS.Having a single inverting VAS transistor can be corrected by swapping the opamp's inputs so long as its local feedback still goes to its inverting input. A resistor will be needed in series with the feedback capacitor.If you drive the VAS transistor's Base directly with the opamp, Vas compensation will need to be done with a capacitor from Collector to ground.Look at some typical AB audio amplifier circuits for ideas.

author: Datguy123
author_rank: Contributor
timestamp: May 17, 2020, 12:10:40 pm
content: Quote from: ogden on May 17, 2020, 09:10:05 amHi, I thought of using two stages because of the SOA and power derating of the output transistors. If I series them, I would get more power from the output transistors at lower output voltages. I would try separating the two series parts, but the circuit works at with lighter loads so I'm not sure if I would need to take such drastic measure.

author: gbaddeley
author_rank: Regular Contributor
timestamp: May 17, 2020, 12:30:51 pm
content: 1 stage is enough. Parallel up as many power transistors as you need (run them at <50% Pmax) use a big enough heatsink (Tcase <80deg.C).

author: xavier60
author_rank: Super Contributor
timestamp: May 17, 2020, 12:51:00 pm
content: For the TIP35, max dissipation drops from about 120W at 30V to about 40W at 60V. That's a drop from 4A to 0.6A.

author: ogden
author_rank: Super Contributor
timestamp: May 17, 2020, 12:54:16 pm
content: Quote from: Datguy123 on May 17, 2020, 12:10:40 pmDon't. Why don't you look how it is done in other "DIY supplies"? This forum alone is full of powerful enough linear supply circuits that uses parallel output transistors instead of weird two supplies in series arrangement.

author: xavier60
author_rank: Super Contributor
timestamp: May 17, 2020, 01:11:56 pm
content: If it will always be outputting 45V at up to 6A, one paralleled set of transistors will do, assuming an input of about 60V.If the output needs to be set to much lower voltages, then it will be difficult to deal with unless the input voltage can be reduced also.

author: ogden
author_rank: Super Contributor
timestamp: May 17, 2020, 01:18:24 pm
content: Quote from: xavier60 on May 17, 2020, 01:11:56 pmGood point. Introduce either mains transformer with multiple output taps (oldskool approach) or switching preregulator + LC filter.

author: Datguy123
author_rank: Contributor
timestamp: May 18, 2020, 07:18:35 am
content: Quote from: xavier60 on May 17, 2020, 01:11:56 pmUnfortunately, the supply I'm planning to build have the full output range of 0-45V. As u mentioned earlier, parallelling transistors would definitely not be a practical solution here.Quote from: ogden on May 17, 2020, 01:18:24 pmThe aim of building this power supply is to utilize the parts I have available to me. The transformer I'm using comes from a power amplifier and does not have lower voltage taps on the main secondary winding. I wouldn't want to rewind the transformer because my lab doesn't have the capabilities to do so.I also wouldn't want to introduce a switching regulator as I want the suppy to be as linear as possible and it might introduce more complexity to the overall circuit.I know the design I created completely negates efficiency, simplicity, and practicality, but it wouldn't hurt to try out a new method. I envision using this as a learning point, and since I have came a long way from a blank piece of paper to a partially working circuit, I would like to cling on to any hope that the circuit could be mended to work. This might be foolish of me to you more senior engineers but I don't want to give up this circuit just yet. I hope you can understand my point of view and aid me in completing this project.

author: xavier60
author_rank: Super Contributor
timestamp: May 18, 2020, 10:16:23 am
content: Quote from: Datguy123 on May 18, 2020, 07:18:35 amYou are rectifying the secondary into split rails? What are the voltages.Some amplifier transformers have lower voltage taps in the secondary so that the rail voltages can be reduced when the speaker impedance switch is set to low.

author: Datguy123
author_rank: Contributor
timestamp: May 18, 2020, 03:53:05 pm
content: Quote from: xavier60 on May 18, 2020, 10:16:23 amThe amplifier is a conventional class AB type. Wouldn't want to tear apart a fancier class G that has split rails. Anyways, the transformer has 4 secondaries, 2 secondaries to supply the low powered electronics, and 2 center-tapped secondaries for the power amplifiers. They are of similar voltage (+/- 54Vpk unloaded wrt to the center tap), and I am going to parallel them to increase the output current.

author: ogden
author_rank: Super Contributor
timestamp: May 18, 2020, 05:23:57 pm
content: Quote from: Datguy123 on May 18, 2020, 07:18:35 amOk. That is constraint indeed, but good one.QuotePower amplifiers usually have two secondaries and possibly some auxiliary winding. In case power secondaries are two separate windings - you have option of "middle tap". Connect secondaries in parallel to get lower voltage & double current, connect in series to get higher voltagelowernominal current. Simplest way to switch between two - relay.

author: Datguy123
author_rank: Contributor
timestamp: May 22, 2020, 09:11:15 am
content: Quote from: ogden on May 18, 2020, 05:23:57 pmThe power secondary windings are center-tapped. 2 identical power secondary windings of 3 output taps 57Vpk-0-57Vpk. No way to decrease the voltage further.Quote from: xavier60 on May 17, 2020, 11:52:09 amSo you're saying that local feedback is needed for a single transistor VAS, such as a miller capacitor? Is it to reduce the gain at high frequencies and ensure sufficient phase margin? I am unfamiliar with the topic of poles and zeros and have no idea what sort of feedback/compensation is needed to deter any instability.So in your suggested configuration, my circuit would have a single transistor common-emitter stage driving a Darlington driver stage but does this have an advantage over using a differential pair as the VAS instead apart from part count?Quote from: xavier60 on May 17, 2020, 11:52:09 amSorry, but what does VAS compensation do? And why only if it's driven directly from the op-amp?Anyways with my current design, are there other areas I have overlooked? I am planning to add current limiting as well, by placing a shunt transistor between the non-inverting terminal of the U7 and ground but would that be a problem because of the slew rate of the op-amp?

author: xavier60
author_rank: Super Contributor
timestamp: May 22, 2020, 09:53:27 am
content: There is little difference between a typical AB audio amplifier and a power supply with an Emitter follower output stage.I don't properly understand Poles and Zeros.With the audio amplifier, from the inputs to the output of the VAS, it's a trans-conductance stage. Input voltage difference signal causes an output current signal. So long as the VAS output is lightly loaded, it results in very high voltage gain.To make the loop stable with feedback applied, the response is made to fall with increasing frequency. This is done by directly loading the output of the VAS with a capacitor or putting a Miller feedback capacitor between C-B of the VAS transistor.The idea is to have the gain drop too low for oscillation to occur before the phase shift of the whole loop exceeds 90°.I see no advantage in having a differential VAS stage unless it's for having a current mirror on the high-side.The single VAS transistor can have its Base directly voltage driven by the opamp and have an Emitter resistor which will cause it to be a simple voltage to current converter. The compensation capacitor would go between C-E.Or the Base could be current driven via a resistor, no Emitter resistor. The capacitor goes between C-B.The opamp makes things a bit messy, it will need local feedback to reduce its gain to something low but must not have any significant roll off.I have likely missed something.Buy now, the topology I suggested in Reply #7 should be starting to look like a good idea.

author: Datguy123
author_rank: Contributor
timestamp: May 25, 2020, 06:52:20 am
content: Quote from: xavier60 on May 22, 2020, 09:53:27 amThanks for the advice. Seems like I will redesign the power supply with regards to reply #7, but have 2 identical series stages instead of 1. I have a few questions, in that schematic, does Q2 aim to provide voltage gain and current buffering at the same time? Without an emitter resistor, wouldn't the voltage gain of that stage be huge? Also, how are the values of C9, C3 and C4 determined? And are base stoppers not needed for the output transistors? Thanks again, and sorry for all the late replies.I would be enlisting soon so this project will be put to a temporary halt.

author: xavier60
author_rank: Super Contributor
timestamp: May 25, 2020, 08:41:35 am
content: Quote from: Datguy123 on May 25, 2020, 06:52:20 amNeedless to say, develop it as a single stage first. Deriving the dynamic reference for the 1st stage could get challenging.Q2 and the TIP35C's form a Sziklai pair, it could have also been a PNP Darlington.https://www.electronics-tutorials.ws/transistor/darlington-transistor.htmlPower supply design topologies can be divided into 2 groups, voltage sourcing and current sourcing. The one I'm suggesting is the current sourcing type.The Sziklai pair has a high current gain, anywhere from 5000 to 15,000, maybe wider, depending on the spec of the particular transistors used.Q2's Base sees voltage drive via 1K resistance. Overall, a voltage change applied to the Base of Q1 causes a current change at the PSU's output. And with good linearity, surprisingly.C3 and R5 are for CV loop's compensation. The default values should result in a stable loop for a wide range of output transistor specs.The CV compensation can be the optimized by trial while doing a repetitive load transient test.C4 is for CC loop compensation. Because the PSU's outputs stage has a constant current sourcing characteristic, the loop response can be made slow.The value of C4 isn't critical but might need to be scaled to different CS resistor values. I haven't given much thought to if low-side sensing can be used for your project.Follow the layout suggestion I made in reply #3.Depending on layout, Base stoppers should not be needed. I have been using the design in a bench supply for a year with no sign of local oscillation. The only trouble I had was a short loss of regulation if an arc was caused while connecting a load. It was a layout problem causing high levels of hash to reach the inputs of the CV opamp.https://www.eevblog.com/forum/projects/linear-lab-power-supply/msg2388873/#msg2388873

author: xavier60
author_rank: Super Contributor
timestamp: May 26, 2020, 01:14:54 am
content: I think that the voltage set point for the 1st stage can be derived by halving the sum of a proportion of the input voltage and of the output voltage. This can be done closely enough with a resistor adder.For example if the input is 60V and the output of the 2nd stage is set to 10V, the sum is 70V. The output of the 1st stage gets set to 35V.There will be 25V drop across each stage.Fast current limit can be applied to both stages, slow CC can also be applied to the 2nd stage.

author: Datguy123
author_rank: Contributor
timestamp: July 27, 2020, 02:23:03 am
content: Quote from: xavier60 on May 26, 2020, 01:14:54 amHi, sorry for the period of inactivity.I have drafted out a circuit over the free time I have, and I hope i have computed the values for the resistors correctly. However, I am unsure where to place capacitors/resistors to ensure the circuit has phase/gain margin. Please advice me on thatAnd also, should I factor in current limiting into the design before doing any loop stabilizing?Thanks.

author: xavier60
author_rank: Super Contributor
timestamp: July 27, 2020, 03:22:57 am
content: Use this version of the design that I have been using as a starting point for the drive and compensation.https://www.eevblog.com/forum/beginners/lm324-power-supply-with-variable-voltage-and-current/msg3089254/#msg3089254The BD139 can be used for Q1 in case more drive current is needed.I have settled on the D45H for the driver because of its consistently higher hFE.If you already have the TIP42's, measure the hFE to be sure it's not too low.The actual output voltage needs to be used to derive the reference for the 1st stage so that both stages will share properly while current regulating.I think it can be done with just 3 resistors. 2 of the same value to sum the unreg input and the output of the 2nd stage. The 3rd goes from the summing node to ground.The current regulation can be done the same as mine applied just to the 2nd stage or maybe to both in a way only fast limiting is applied to the 1st stage.

author: Datguy123
author_rank: Contributor
timestamp: July 29, 2020, 01:12:56 am
content: Quote from: xavier60 on July 27, 2020, 03:22:57 amI saw another circuit online:http://www.kerrywong.com/blog/wp-content/uploads/2013/12/ps_pos.pngwhich also deploys a sziklai pair output.I would like to ask if the main advantage of incorporating the additional 8V supply and having op amps to sink current is to aid in the current limiting of the circuit. From my understanding, the CV op amp will try to pull the base voltage up when current limit is on and the constant current op amp doing the opposite. In the case of Kerry Wong's design, is it true to say that the base drive would be weak as both CC and CV op amps are working in different directions and would end up in an equilibrium (CV op amp at +max O/P v and CC op amp at -max O/P v) and the base does not get driven well? However in the circuit you proposed, the base drive would be stronger as the diode D1 prevents CV op amp from sourcing current to the base when CC op amp is sinking current.Also, I need to use high side current sensing as this would be part of a dual rail PSU, so would using a differential amplifier to sense the voltage from a shunt resistor on the + rail and comparing it to a voltage signal from an DAC be effective?

author: xavier60
author_rank: Super Contributor
timestamp: July 29, 2020, 01:50:19 am
content: Quote from: Datguy123 on July 29, 2020, 01:12:56 amIll have to get back to some of that later.For the best chance of success with high side sensing if you want it to be reasonably accurate and settable, do it like this,https://www.eevblog.com/forum/projects/improving-adjustable-dual-voltage-bench-power-supply/msg3020386/#msg3020386I'm not sure yet what that sensing circuit would drive into, likely an opamp/comparitor circuit.EDIT; Actually the LT6105 works the same way.

author: Datguy123
author_rank: Contributor
timestamp: August 01, 2020, 08:57:14 am
content: Quote from: xavier60 on July 29, 2020, 01:50:19 amI have incorporated the high side level shifting current limiting circuit, as well as the resistive summer and divider in the attached circuit. Please advice me if the general design has any flaws. I guess I'll use the op amp circuit instead of the LT6105, unless I want the extra level of precision in another revision of my power supply. Right now I want to use what I have currently. I will be using a dac (most likely MCP4725) for I_set, with lowest step interval of 50mA.Also, the op amps I will be using will be Lm358 instead of op747. I hope to hear from you soon on the use of the extra 8V supply opposed to not having it at all for the VAS transistor.

author: xavier60
author_rank: Super Contributor
timestamp: August 01, 2020, 09:31:05 am
content: The separate 8V isnt needed for the ORing node pullup. Just use the + opamp supply. If there is too much max drive voltage for the level shifter transistors, resistors could be put from the ORing nodes to ground.If the CC loop is needed to be stable, U4 might need a compensating capacitor from output to inverting input. But this will slow the response to sudden oveloads.Fast limiting could be added. An NPN transistor could sense the voltage across R12. It would then drive a PNP transistor that would bypass the B-E drive for Q6.For R1,2,4,5, start with 1K.

author: David Hess
author_rank: Super Contributor
timestamp: August 01, 2020, 07:03:02 pm
content: I like your level shifters. Keep in mind that the differential pairs could also be made with NPN/PNP pairs. What is really going on is an emitter follower to increase the current driving a common-base stage to increase the voltage.Track down the high current wiring and the return paths for any high currents. These are the connections which must be wide and short to minimize the effects of inductance. Of course this includes the collector and emitter wiring of the output transistors but it also includes any capacitors connected to that wiring.

author: xavier60
author_rank: Super Contributor
timestamp: August 01, 2020, 08:34:54 pm
content: The high side current sensing needs to always have some voltage present on the output to work properly.Put it before the 2nd stage.Fast limiting will be easier to implement with a PNP monitoring the voltage across the CS resistor and its Collector going to the Base of Q6.

author: David Hess
author_rank: Super Contributor
timestamp: August 02, 2020, 02:33:15 am
content: Quote from: xavier60 on August 01, 2020, 08:34:54 pmPower supply circuits of that complexity usually include a negative supply for the control circuits so the high side error amplifier can operate down to 0 volts, or actually a little lower. For bipolar dual output supplies, this is free.

author: dietert1
author_rank: Super Contributor
timestamp: August 02, 2020, 09:39:45 am
content: Let's try to write a comment concerning oscillations:You need to understand what is the meaning of unity gain stability. If you buy an OpAmp that is called unity gain stable (the OP747 is of that type), that means it has internal bandwidth limiting and enough speed that allows you to feed back the full output signal to the input - for maximum accuracy. You added additional gain stages with gain of 20 (680 Ohm/33 Ohm). That means you are feeding back 20x the OpAmp output signal back to its input. You cannot do that, otherwise you get oscillations.I can see another error in your design. You added two capacitors to reduce gain at high frequencies: C10 and C21. You cannot do this. Already at moderate frequencies those 2 caps will cause a phase shift of near 180°, which means negative feedback becomes positive feedback => oscillations.Unless you have a lot of practical experience with circuits of this type, you need to simulate your design. Open the control loop and try to understand the Bode diagram to decide whether the closed loop will be stable or not. Just soldering circuits you can spend years trying to find a good solution.Regards, Dieter

author: Datguy123
author_rank: Contributor
timestamp: August 02, 2020, 12:03:49 pm
content: Quote from: xavier60 on August 01, 2020, 09:31:05 amThanks, I will take note when I build the prototype. But any advantages to the current limiting part of the circuit with a current sinking design of the VAS transistor(quote below)?Quote from: Datguy123 on July 29, 2020, 01:12:56 amQuote from: xavier60 on August 01, 2020, 09:31:05 amI did some calculations. The max current the power supply is capable of is 6A, and having a conservative hfe of the sziklai pair (TIP42C: 30, TIP35C: 20), Q6 would need to draw 5mA of current from R6. The voltage drop across that resistor would be 5V if it was 1k ohm, which is too much. (50V input, 45V output max). Would you then advice a lower value for R1,2,4,5?

author: Datguy123
author_rank: Contributor
timestamp: August 02, 2020, 12:09:07 pm
content: Quote from: xavier60 on August 01, 2020, 08:34:54 pmWhy is that so?

author: xavier60
author_rank: Super Contributor
timestamp: August 02, 2020, 12:14:18 pm
content: There needs to be some positive voltage at the top of R13 for Q7 to source current to ground.

author: Datguy123
author_rank: Contributor
timestamp: August 02, 2020, 12:17:33 pm
content: Quote from: David Hess on August 02, 2020, 02:33:15 amHi, I'm actually building a dual rail power supply. So by having a negative rail for U3 (In fact, I'm powering all op amps with +15V and -12V rails), the current limiting circuit can work properly at 0V output?

author: xavier60
author_rank: Super Contributor
timestamp: August 02, 2020, 09:44:11 pm
content: Quote from: Datguy123 on August 02, 2020, 12:03:49 pmI didnt follow all of that. Although most BJTs have much higher hFE than the specified minimum, Im not so sure about the TIP42C. That's why I settled for the D45H11. I tested a whole packet of them finding the hFE close to 200 and within a few % of each other.Start with 1K anyway.