Monolithic 100GHz Sampler - Page 1
Forum section: electronics / projects

author: mawyatt
author_rank: Super Contributor
timestamp: August 30, 2022, 04:33:52 pm
content: From a 2008 article in Microwave Journal by Furaxa and Naval Research Labs:https://www.microwavejournal.com/articles/6729-monolithic-sampler-pulser-architecture-exceeds-100-ghzWe did some initial work in IBM 8WL (130nm SiGe BiCMOS), but don't recall ever fabricating a test chip, likely because the design team got consumed on another more important project, and we never had a chance to revisit!!Anyway, very interesting sampling technique for full integration.Best,

author: RoGeorge
author_rank: Super Contributor
timestamp: August 30, 2022, 05:43:09 pm
content: Wow!Very interesting, thank you!The MW Journal link has aUS Patent 6,433,720reference, which led to this AN page from Furaxa,http://www.furaxa.com/Specs.htmwith some neat applications for the sampler.

author: mawyatt
author_rank: Super Contributor
timestamp: August 31, 2022, 12:34:15 pm
content: Thanks.The degenerated Triplett utilized is also very interesting circuit from a linearity standpoint. Fixed the image rotation (for some reason they don't always show here as they do in image editor (Gimp)).Best,

author: magic
author_rank: Super Contributor
timestamp: August 31, 2022, 03:23:48 pm
content: Quote from: mawyatt on August 31, 2022, 12:34:15 pmYou are probably running into this problem.https://www.eevblog.com/forum/news/does-the-forum-support-exif-orientation-tag-in-jpeg-images/Simply opening with gimp and saving again should solve the problem every time, because gimp strips the EXIF tag and rotates the pixels in the file. At least that's what happens in all versions I have seen so far.Yes, I know

author: RoGeorge
author_rank: Super Contributor
timestamp: August 31, 2022, 04:07:00 pm
content: For the unexpected pics orientation, inside the image files there is also metadata, some of the EXIF tags specify the orientation of a pic at display time. The problems are:- some cameras may attach the EXIF orientation info at shooting time, some camera don't, or can be set from the camera settings to ignore the orientation sensor- some cameras might have only a landscape/portrait shooting sensor, others might support all orientations- some programs will disregard the orientation EXIF tag, while other will honor the orientation from the EXIF- while uploading pics, some forums might strip out the EXIF info to remove possible sensitive information, like e.g. the GPS location where the pic was taken, etc., there is a lot of info in the EXIF metadata:https://exiftool.org/TagNames/EXIF.html- GIMP itself has a setting (IIRC), to honor/disregard orientation from the EXIF metadata- at export from GIMP, the EXIF info can be stripped away, so yet another unexpected rotationTo check for the EXIF metadata tag of a picture file, in a terminal:Code:cd /to/the/pictures/directoryexiftool IMG_3264.JPG | grep -i orientationor, if exiftool is not already installed, then 'identify' might be there alreadyCode:identify -verbose IMG_3264.JPG | grep -i orientation'exiftool' reports it nicer something like "Orientation: Rotate 270 CW", while 'identify' will report "Orientation: LeftBottom" which is not as clear as 270 CW.From GIMP, at export time, I use to uncheck any inclusion of metadata, thumbnails, color palletes, etc. which, as a side effect, will remove future surprises regarding unexpected rotation at display time, and never upload original pics straight from the camera.Quote from: mawyatt on August 31, 2022, 12:34:15 pmNot sure I understand the quoted text, or at least frame the idea/context it refers to. Is that about a schematic topology, or about the atomic structure? Any link, or search terms, or maybe a few more words to clarify what is it about, please?

author: mawyatt
author_rank: Super Contributor
timestamp: August 31, 2022, 05:06:05 pm
content: Quote from: RoGeorge on August 31, 2022, 04:07:00 pmThe Tripplett (or Triplett not sure of spelling) is a triple differential pair with purposely unbalanced devices and emitter degeneration. The 3 diff pairs are arranged with a single diff In/Out as shown, so overall have a center symmetry with the two outer unsymmetrical diff pairs. The unbalanced device size and emitter resistors can manipulate the Odd-Order Harmoincs is an advantageous way, beyond the benefits of just simple emitter degeneration. Sketched up a schematic to show the arrangement.As you can see from the plots different combinations of re1, re2 & re3 produce interesting results, add to this varying the bias current ratios and the device scaling and you have a enormous playing field. One can manipulate the troublesome 3rd Order Products with proper scaling/ratioing of all these variables.A detailed analysis is quite involved and transcendental in nature and requires significant effort and CAD/numerical resources (the BJT device models alone are involved and likely were HICUM or MEXTRAM when we did this back in ~2008), best left for Post Doctoral StudentsBest,

author: RoGeorge
author_rank: Super Contributor
timestamp: September 01, 2022, 05:21:54 pm
content: Quote from: mawyatt on August 31, 2022, 05:06:05 pmThank you very much for taking the time to explain and draw that, you are too kind.The additional schematic is very helpful.Indeed a very flexible circuit, intriguing new toy to tinker with!

author: mawyatt
author_rank: Super Contributor
timestamp: September 02, 2022, 12:51:55 pm
content: You are quite welcomeGlad you find this sort of thing interesting. The Triplett seems to be a a little known technique for expanding a simple differential pair without incurring significant emitter degeneration voltage drop.Wish we had the opportunity to fabricate this Sampler, can you imagine the performance of this today with 10nm CMOSBest

author: RoGeorge
author_rank: Super Contributor
timestamp: September 02, 2022, 03:08:06 pm
content: Like most of the other circuits you showed here, on EEVblog, this one too is extremely interesting, and I bet everybody who clicked on this topic was amazed by this sampler's performance and by its applications. The fact that the design can be integrated, and the fact that it can also be used to generate very short pulses and not only to sample, puts it on par with an SDR in terms of flexibility and applications. That is why I'm curious to try it.A lot can be done with narrow sampling and narrow pulses, and by combining that with synchronous detection, or with Polyphase/N-Path Mixer, sparse signals, randomness, etc. When combining all these techniques, the possibilities and the applications seem unlimited.However, to fabricate the circuit on a die would be way over my skills, no mater the technology or the size of it. Never did any ASIC design, the closest I worked with was some VHDL but for FPGAs only. By tinkering with it I meant simulate it in LTspice (didn't start that yet), then solder a few NPN transistors on a PCB to make a sampler or a comb generator for the fun of it, at much lower frequencies.In regards to the transcendental equations, I just hope the LTspice simulations will substitute for my lack in advanced math. Googled today for transcendental function, which means I am nowLearning Advanced Math.

author: mawyatt
author_rank: Super Contributor
timestamp: September 02, 2022, 04:01:36 pm
content: There was an underlying purpose behind many of these circuits, which unfortunately we can't discuss, but they also helped in increasing the IP within our small Research Company/Group which helped in the perceived value.You can grab a handful of 2N3904s and configure the Triplett to play with, that would be fun for sure!!Best,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 02, 2022, 05:07:15 pm
content: It's kind of a shame it depends on extremely high fT; you could build the whole thing out of discretes, but it's not going to do any better than just using them as switches, and better can be done by pulse generators and diode gates -- classic Tek samplers for example. More or less... I think?!Also, not that you can get very nice discretes anymore; RF PNPs are gone and SiGe are awkward to use at board-level (only intended for CE amps, AFAIK).Tim

author: mawyatt
author_rank: Super Contributor
timestamp: September 03, 2022, 01:35:58 pm
content: Actually is doesn't depend totally on "extremely high ft", but squeezes the highest performance from a given process/speed devices. Sure the higher ft process produce higher speed results, but we simulated with IBM 8WL back in 2008 which certainly wasn't the fastest process available then. The concept relies on current mode steering as shown in the colored current paths during sampling, this can be somewhat quick even with modest speed devices. Suspect even with 74AC type CMOS logic edge, 2N3904 (there are much faster discrete devices tho) and a couple modest speed NMOS devices, one would achieve respectable results with a good tight RF type layout & assembly.We could have, and likely would have, if given the opportunity to actually fab a test chip (at this time we had been acquired, and no longer controlled our technology destiny, which basically went downhill after the acquisition....long story we can discuss if interested). We could have used IBM 9HP or even XP 90nm SiGe BiCMOS, which were >400GHz @90nm vs 8WL which was ~200GHz @130nm, a little later 65nm BiCMOS SiGe became available from X-Fab with over 500GHz BiCMOS, but don't know what's available today since haven't kept up since retiring a few years ago.Anyway, this is an example of squeezing the best possible performance from a given device/process limitation, very much like the old Tektronix did in their time.Best,Edit: Regarding designing with SiGe devices. These can be handled (careful ESD practices) just like another BJT with paying close attention to the various breakdown voltages which are low, usually under 5 volts. The popular discrete types like the BFU & BFP types (many are in stock at Mouser) are all specified for RF use, but should yield very fast performance when employed as switching devices, especially if kept away from Saturation and Quasi-Saturation regions (like in this application). These devices will have a very low base and emitter intrinsic and contact resistances (low RF noise), low Cec, Cbc and Cbe (high ft) as well as very flat Beta with collector current and high Early Voltage.

author: Marco
author_rank: Super Contributor
timestamp: September 03, 2022, 05:01:12 pm
content: Why are there so few highly integrated SiGe designs outside of extreme high price niches? It's not like power devices are small, in the space of one higher power transistor they should be able to fit an ADC. There's some almost complete unknowns like Adsantec making 4 bit ADCs, but no almost no one seems to want to compete in the 8+ bit space.There's pent up demand in the lower cost instrumentation industry for higher speed ADCs without 5+ digit percentage margins over manufacturing cost and they do have the volume to make it worth while. For plain old silicon look at the HMCAD15xx, but even that almost seems like it arrived on the market by accident "oops we made something useful, better never make anything like it again".

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 03, 2022, 05:25:54 pm
content: Have seen more than a few op-amps with fairly ordinary specs (10s MHz GBW, etc.) but suspiciously low Iq -- fabbed on ADI's XFCB-something (SiGe) process, and selling at just a couple bucks. Perhaps there are still quite few of them in relation to the overall op-amp market, that wouldn't be surprising.Fast ADCs don't seem to be a price priority; you aren't hooking them up to just any MCU anymore, most likely either an FPGA or ASIC, and using lanes of LVDS. And now the cost of the ADC isn't so big a part of the whole.There may be import restrictions too; the technology level that's restricted keeps going up over time, but that still means cheap (read: Chinese manufacture) equipment lags behind others. And their native fabs aren't nearly up to speed (yet).Tim

author: Marco
author_rank: Super Contributor
timestamp: September 03, 2022, 05:45:36 pm
content: Quote from: T3sl4co1l on September 03, 2022, 05:25:54 pmLVDS? No, that's far too useful for lower cost designs. Better make the bus narrower and use the highest speed serial interface available on the highest cost FPGAs.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 03, 2022, 06:25:03 pm
content: Quote from: Marco on September 03, 2022, 05:45:36 pmI detect sarcasm, but I guess it's not entirely out of the question i.e. a PCIe lane would do just fine up to fairly reasonable sample rates, and interfaces are common enough on certain devices (FPGAs, SoCs). Overkill perhaps, but standards often are.Tim

author: mawyatt
author_rank: Super Contributor
timestamp: September 03, 2022, 06:46:26 pm
content: Let's not forget the actual development cost for a new high performance ADC or whatever IC that's pushing the performance limits. You are looking at least $10M++, our last major CMOS chip design cost ~$50M over 8 years ago and that was just to the prototype stage, nowhere near SOTA CMOS either (28nm), and with only 1 process run. Yes, it was more involved with ~1B devices, and all digital, but nailed it on the 1st try!!. IC development is very very expensive and not forgiving, where one can ruin their entire career with a few errors....not for the faint of heart!!CMOS was the achilles heel of SiGe BiCMOS, and because the market for CMOS is huge, all the semiconductor process development $ are going to CMOS and no sane fab is going to mess with their leading edge CMOS just to add SiGe BJTs. So SiGe gets the old leftover CMOS processes and since much of the actual circuits that could benefit from SiGe also needs lots of CMOS for digital, the appeal of SiGe gets diluted because of the CMOS limitations. One could argue that a complex chip design, where a large portion of the chip is digital is better served with 2 chips, one with the older SiGe BiCMOS and one with the advanced pure CMOS. The 2 chips would fit within the same footprint because the SiGe BiCMOS chip would need to be large to support the digital section, and with a separate much smaller feature size CMOS only chip hosting the digital it would be significantly smaller. Another issues is with upgrading the overall design, where advances in CMOS are common place and advances is SiGe BiCMOS are few. So with a 2 chip design one can upgrade the CMOS to a smaller faster process and keep the SiGe design as is.Anyway, these are a few reasons why SiGe BiCMOS hasn't progressed much in the past couple decades. It's still a very specialized process, within a few fabs, but nowhere near with SOTA CMOS. This isn't to degrade the superb SiGe BJTs tho, they are very useful for some of the specialized high end electrical performance areas, but there is also not much demand, so the overall $ are not enough to encourage sinking significant investments into future SiGe processes. Not trying to be negative WRT SiGe, actually a big fan of SiGe since we were right in the forefront of it's development and utilization, but trying to be realistic. Realized some time ago that one must become very good at designing analog/RF/MW/MMW in CMOS, because the digital folks rule and we must live and design within their silicon frameworkBest,