hybridfree/eevblog-posts huggingface dataset:
Compiler software for creating JEDEC files to program GAL devices ? - Page 1
Forum section: electronics / general

author: eda8039
author_rank: Newbie
timestamp: October 30, 2021, 03:41:42 pm
content: I'm starting to play with my collection of GAL & PAL chips. I'm retired, have a terminal condition, and plenty of dip sockets, and GALs & PALs. So, I have no desire or need to discuss CPLDs. Right now it's GAL20V8. Maybe in my next life I'll look at CPLDs.I'm looking at a few different compiler options Wincupl, Galer, Palasm.It seems to run Palasm I have to jump through a lot of hoops to setup and run in an old DOS environment, while Galer and Wincupl run in my Windows 10 OS.Has anyone tried both of these and found one better than the other, or found an even better alternative ?

author: Bassman59
author_rank: Super Contributor
timestamp: October 30, 2021, 08:45:29 pm
content: Quote from: eda8039 on October 30, 2021, 03:41:42 pmI remember that WinCUPL was buggy as fuck-all. We used to use PALASM.

author: edavid
author_rank: Super Contributor
timestamp: October 30, 2021, 10:19:20 pm
content: Did you see this thread already?GAL design softwarehttps://www.eevblog.com/forum/microcontrollers/gal-design-software/
Bare metal dual core applications on the Zynq - Page 1
Forum section: electronics / general

author: Boscoe
author_rank: Frequent Contributor
timestamp: October 27, 2021, 08:02:15 am
content: Hi all,I'm about to start quite an ambitious project on the Zynq platform using a bare metal application as the complexity of Linux is nowhere near needed and I want (almost) instant on operation.This got me thinking about that second core on most of the Zynqs. How can one make use of it for bare metal applications? Does anyone have an example of a two bare metal applications operating on the cores? I'm keen to know what the implications are of running two applications at the same time talking to the same registers / hardware? How would one debug such an application? Is it best to have one core as the interface and the second core compute / software only? What are the details / issues that one has to deal with in the Zynq hardware platform in such an application?Would like to hear your thoughts.ThanksGeorge

author: Someone
author_rank: Super Contributor
timestamp: October 27, 2021, 10:25:36 am
content: ... there is an app(lication) note for that: XAPP1079https://lmgtfy.app/?q=zynq+bare+metal+dual

author: Scrts
author_rank: Frequent Contributor
timestamp: October 27, 2021, 05:04:21 pm
content: Look up: semaphore and mutex
Spartan6 Extended Performance - Page 1
Forum section: electronics / general

author: hal9001
author_rank: Regular Contributor
timestamp: October 26, 2021, 12:29:58 pm
content: The Spartan6 data sheet calls out a different Vccint voltage for standard v extended performance. What does the extra .03 V do to give the FPGA higher performance for a -3 or -2 part?Cheers!

author: dtodorov
author_rank: Contributor
timestamp: October 26, 2021, 12:54:45 pm
content: The specs seem generally tighter for -3/-2. For what I can think of, digital timings deteriorate with reduced supply voltageVery likely the devices are binned and their specs can be guaranteed with a narrower margin.

author: BrianHG
author_rank: Super Contributor
timestamp: October 26, 2021, 12:59:51 pm
content: Quote from: hal9001 on October 26, 2021, 12:29:58 pmYou are reading the table wrong. The margin is larger than that. You must only consider the -min column when you want to guarantee reported FMAX performance. There you see the spread is from 1.14 to 1.20. That's a 0.06v difference, almost 0.1v.

author: Someone
author_rank: Super Contributor
timestamp: October 26, 2021, 10:07:59 pm
content: Some (older) FPGA families had timing characterised across supply voltage and/or temperature. If you could guarantee the devices were running in "better" conditions, you provided your specific conditions to the timing tools and the timing was uprated (and still guaranteed by the vendor).

author: hal9001
author_rank: Regular Contributor
timestamp: October 27, 2021, 11:20:31 am
content: Thanks all. Even with .06 V difference the regulator for Vccint needs to have very low ripple to hold the extended performance!Is there a significant power draw difference on Vccint when running in standard v extended voltage?

author: dtodorov
author_rank: Contributor
timestamp: October 27, 2021, 11:27:54 am
content: Quote from: hal9001 on October 27, 2021, 11:20:31 amThis should be also described in the datasheet.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 27, 2021, 02:53:27 pm
content: Quote from: hal9001 on October 27, 2021, 11:20:31 amNo doubts. Power draw is mostly the switching losses of the FETs.Gamesters do overclocking and overvoltaging on their PCs all the time.
VHDL to Verilog (System Verilog) book suggestions. - Page 1
Forum section: electronics / general

author: ee2000
author_rank: Newbie
timestamp: November 08, 2021, 04:00:08 pm
content: HiI have now been working multiple years with VDHL, and we are now starting to getting projects that are part verilog/system verilog,is somebody having a good suggestion on a book or course that would make the transition a little easier ?Thanks a lot in advance.

author: Cerebus
author_rank: Super Contributor
timestamp: November 08, 2021, 04:30:53 pm
content: "Verilog Quickstart" by James M. Lee. A bit out of date, a bit basic, a bit terse, but if you've already a background in VHDL you will be ready to code after the day it takes to read the whole book.
Need help Exilink XC2C256 VQG100 C and ADSP-BF531 - Page 1
Forum section: electronics / general

author: newit
author_rank: Contributor
timestamp: October 27, 2021, 09:09:09 am
content: I'm new in this forum, I have a problem with my telescope computerized electronic motor control board(attached pictures), what happen is during flashing new firmware to the board(exilink xc2c256 chip or ram or rom) my power to the board is interupted when i turn the power back on there is nothing display on my hand held remote control. So I try to re-flash it again now the flashing went fine until the end the display show message" Take SD out Restart" I did exactly that and no display on the remote anymore. It's a simple motor control board only supply voltage to the Right ascendsion and Declination motors. Now I'm suspecting either the Exilink XC2C256 VQG100 Cms or Analog devices ADSP-BF531 SBSTZ400 went wrong with it that's why the chips won't store the firmware in it's macro cell, are there any way that i can reset the Exilink Macro cell or any advice to what is going on with the system it can be either Exilink or Analog device or the RAM itself? Any advice of how to fix would be appreciated. I had very few knowledge of electornicbut I only can test and replace chips, not know much on how it's work.regardssamhere is the link to the pictures of the board itself:https://postimg.cc/3WRW7dgMhttps://postimg.cc/xcmfTH8Zhttps://postimg.cc/dZdbv26m
PDM Verilog demodulator - Page 1
Forum section: electronics / general

author: davorin
author_rank: Unknown
timestamp: October 18, 2021, 02:58:04 pm
content: Good afternoon (o;For a project I would like to use some PDM microphones as they are better available than I2S ones....and I already have them (o;Googled around today how the conversion from PDM to PCM could be done for further processing in FPGA....and all papers talk about decimation with filtering...but I couldn't find any reference to any actual implementation in Verilog....and the FPGA IDE tools I want to use (Efinix and Gowin) don't come with decimation soft IP.Or could the decimation just be done like dping a rolling average on a constant amount of bits read in?thanks in advance from a total signal processing noob (o;richard

author: Someone
author_rank: Super Contributor
timestamp: October 19, 2021, 02:06:53 am
content: Quote from: davorin on October 18, 2021, 02:58:04 pmYes, that works, but may have more noise and poorer frequency response than more sophisticated methods.

author: dawnclaude
author_rank: Contributor
timestamp: October 19, 2021, 07:15:06 am
content: Here is a useful blog series that explain how to choose filter parameters depending on the mic specifications and your needs:https://tomverbeure.github.io/2020/12/20/Design-of-a-Multi-Stage-PDM-to-PCM-Decimation-Pipeline.htmlIn the design above there is a CIC and cascaded half band filters that gradually reduce the sampling rate which lets you do the filtering in less number of multiply and accumulate operations compared to using a single sharp lowpass filter.That said, on FPGA, I just use a single lowpass filter with a very sharp transition. Numbers will depend on the implementation, type of FPGA resources and vendor tools but in my case:A FIR lowpass filter with 3500 taps with transition from 12kHz to 16kHz, passband ripple of 0.1 dB and stopband attenuation of 120 dBInput sampling rate and PDM clock frequency 3.125 MHzYou just downsample the filter output by 96 to end up with 32.55kHz sample rate with minimal aliasingFinal resources:2 DSPs3.5 BRAMsI have used the Xilinx FIR Compiler to implement the filter since I have a 7-series FPGA. Not sure if GOWIN will produce a design as optimzed as this if it has a FIR tool. Of course you could implement the filter yourself with HDLYou can calculate the filter coefficients using your favourite math tool.Cheers.
Strange location of configiration pins on all Cyclone FPGA - Page 1
Forum section: electronics / general

author: c64
author_rank: Frequent Contributor
timestamp: October 17, 2021, 05:37:44 am
content: It has always been a mystery to me. All Altera Cyclone FPGA in QFP packages have most of the configuration pins on the left side, but two of them (nSTATUS, CONF_DONE) on the right side. Very inconvenient.It where a reason for this?
ACAP Real prices - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: September 30, 2021, 08:08:03 am
content: Hi,Have you seen the recent webinar on ACAP series from xilinx (it's about 6 hours!), they look very interesting, I wonder when we can get them in china in real prices!VE2002 is the smallest in the family, I think maybe we should expect to get prices in the range of 20$ if we would pass covid.have anyone here get his hands dirty with these new babies? any Idea or guess about the prices?
SERDES pronunciation? - Page 1
Forum section: electronics / general

author: jeremy
author_rank: Super Contributor
timestamp: September 20, 2021, 12:37:04 am
content: Hi all,Just curious if there is any regional difference here.

author: AaronLee
author_rank: Regular Contributor
timestamp: September 20, 2021, 12:45:26 am
content: I refuse to use the word. To me, it'll always be a "serializer/deserializer". I've heard a few people trying to pronounce it but was totally unintelligible. I'm all for shortening unnecessarily long words, but in this case I make an exception.

author: Cerebus
author_rank: Super Contributor
timestamp: September 20, 2021, 02:34:28 am
content: I say Sir Dez, as in the honorific and the short form of Desmond or Dennis.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 20, 2021, 04:10:18 am
content: Like #1 but taking the standard English laziness: "sɘrdes". ɘ as in fir (/fɘr/), and "des" like "despicable".Tim

author: colorado.rob
author_rank: Frequent Contributor
timestamp: September 20, 2021, 11:47:18 am
content: Sir Deez.

author: Bassman59
author_rank: Super Contributor
timestamp: September 20, 2021, 04:51:41 pm
content: Quote from: AaronLee on September 20, 2021, 12:45:26 amSame here.It's either a serializer or a deserializer.What the hell is an "input serdes?"(See the pet peeve thread.)I think the real answer to the question is "deez nutz."

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 20, 2021, 04:56:58 pm
content: Quote from: T3sl4co1l on September 20, 2021, 04:10:18 amYeah kinda same.Anyway, it seems reasonable to pronounce the SER part as in serializer and the DES part as in deserializer. Now the exact way you pronounce those words probably depends on local factors.

author: SMB784
author_rank: Frequent Contributor
timestamp: September 22, 2021, 01:39:43 pm
content: sir deezsir from the first syllable of serializerdeez from the first syllable of deserializer

author: armandine2
author_rank: Frequent Contributor
timestamp: September 22, 2021, 01:47:45 pm
content: Quote from: T3sl4co1l on September 20, 2021, 04:10:18 amschwa
Problem in Generate - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: September 18, 2021, 09:14:55 am
content: Hi,I have 9 channels of FIR filter, which would produce 31 bit output data, I want to trim them and use generate to connect all of them to some output module.Here is my codeCode:wire signed [30:0] wIFir,wQFir [0:8];wire signed [15:0] wIFirTrim,wQFirTrim [0:8];genvar i;generatefor (i = 0; i< 9; i = i +1) beginassign wIFirTrim = wIFir[25:10];//extract the 16 bit valuable dataassign wQFirTrim = wQFir[25:10];endendgenerateBut ISE would complain that wIFir is not a memory!what I have done wrong?

author: cruff
author_rank: Regular Contributor
timestamp: September 18, 2021, 12:37:11 pm
content: I scanned the SystemVerilog standard briefly, and it seems to me that you might need to use these declarations to declare wIFir and wIFirTrim as arrays:Code:wire signed [30:0] wIFir[0:8], wQFir[0:8];wire signed [15:0] wIFirTrim[0:8], wQFirTrim[0:8];

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: September 18, 2021, 12:45:15 pm
content: Thanks cruff

author: radiolistener
author_rank: Super Contributor
timestamp: October 14, 2021, 02:51:48 am
content: Note: if you simply cut-off unused bits for truncation, you will get unwanted DC spur on the output. As result your truncated output will be distorted with unwanted bias offset.For example it happens when you get just 10 or 16 bits from 31 bit FIR output. In order to avoid it, you're needs to use rounding.Here isarticlefor more details.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 14, 2021, 01:55:18 pm
content: thanks
FPGA IO - parallel termination resistors - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: September 07, 2021, 09:01:22 pm
content: I am looking at a schematic of the I/O buffers on an FPGA and they have the pull up resistor feeding into a VCC/2 instead of VCC.After reading about parallel termination resistors.. It seems that most are connected to ground or VCC.There is also an option to include weak termination however isnt that pointless if there is a pull up?I am not sure why but I find IOs really hard to understand.

author: ataradov
author_rank: Super Contributor
timestamp: September 07, 2021, 09:33:45 pm
content: What specific FPGA you are talking about? And attach the schematic you are looking at.Termination and pull-up/pull-down resistors are different. And usually all those things are optional and what to use depends on the I/O pin type and application.VCC/2 is often used as a reference level for high speed interfaces (DDR SDRAM and similar), so this may be the goal of this option.

author: Bassman59
author_rank: Super Contributor
timestamp: September 07, 2021, 10:50:01 pm
content: Quote from: steamedhams on September 07, 2021, 09:01:22 pmThere is a laundry list of signaling standards. Many were designed to handle multiple loads across a backplane. Their "weird" termination requirements such as being pulled to some intermediate voltage are intended to ensure good signal integrity. Your FPGA's user manual should have a list of all of the I/O standards it supports and all of their termination requirements.That said: for most cases you'll use LVCMOS for single-ended I/O and LVDS for differential, so you don't need to worry about these other termination requirements.QuoteA "weak termination" isn't really a termination. It's a pull-up or pull-down. It's meant to ensure that an input is always at some valid logic level when the driver is tristated or is not connected. The reason it's called "weak" is that it's a high enough resistance value to be easily overdriven.But because it's "weak" it's slow. That is, if you disabled the driver, the input would eventually see the pull-up voltage level. This is why, for example, I2C specifies a specific value of pull-up resistor. The 2.2k ohms to 3.3 V goes to that rail much faster than a weak pull-up of some 50k ohms.
Measuring On-chip resistive termination (impedance adaptation) - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: September 08, 2021, 04:04:07 pm
content: I am measuring the resistive termination of an FPGA's internal complex IO (single ended for now).I've been wondering how to do this..I was thinking, if I added an ammeter to the pad and then ground to the other side, i could see the current flow.. but doesn't this also draw current from the output buffer causing issues??However, if I were to somehow deactivate the output buffer, then I am just creating a circuit from Vref/2 across the resistor and then to ground through my ammeter.Seems simple enough but I am not really sure.

author: NorthGuy
author_rank: Super Contributor
timestamp: September 08, 2021, 05:26:51 pm
content: Connect a 50 Ohm resistor between the pad and Vref (or between the pad and ground). Measure the voltage on the pad and calculate using Ohm's law.

author: steamedhams
author_rank: Regular Contributor
timestamp: September 08, 2021, 08:21:07 pm
content: wouldnt an ammeter be more accurate? why 50 ohm?

author: NorthGuy
author_rank: Super Contributor
timestamp: September 08, 2021, 08:42:11 pm
content: Quote from: steamedhams on September 08, 2021, 08:21:07 pmI don't think so. It also measures voltage difference across a resistor, but it's resistor is much smaller than yours.Quote from: steamedhams on September 08, 2021, 08:21:07 pmMathematically, you'll get the least error if both DUT resistor and yours are the same.

author: steamedhams
author_rank: Regular Contributor
timestamp: September 09, 2021, 04:10:09 pm
content: turns out i had the correct approach just connected to the wrong pad.
FPGA Benchmarking algorithms - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: August 23, 2021, 11:28:35 am
content: What are these Bench marking algorithms that I keep seeing in academic papers??Stuff like "apex2"

author: cfbsoftware
author_rank: Regular Contributor
timestamp: August 23, 2021, 10:05:26 pm
content: According tohttps://docs.verilogtorouting.org/en/latest/vtr/benchmarks/apex2 is one of the "MCNC20" benchmarks"The MCNC benchmarks  are a set of small and old (circa 1991) benchmarks. They consist primarily of logic (i.e. LUTs) with few registers and no hard blocks.Warning: The MCNC20 benchmarks are not recommended for modern FPGA CAD and architecture research. Their small size and design style (e.g. few registers, no hard blocks) make them unrepresentative of modern FPGA usage. This can lead to misleading CAD and/or architecture conclusions."The reference to  is:"S. Yang. Logic Synthesis and Optimization Benchmarks User Guide 3.0. Technical Report, MCNC, 1991."

author: steamedhams
author_rank: Regular Contributor
timestamp: August 28, 2021, 08:36:50 am
content: Do you know if the benchmarks are in VHDL??I can only see BLIF which isnt ideal for what I want to do.
FPGA LVCMOS vs LVTTL standards - Page 1
Forum section: electronics / general

author: hal9001
author_rank: Regular Contributor
timestamp: August 29, 2021, 11:02:13 am
content: Vih should be different for 3.3v cmos and ttl. Xilinx Spartan 3 has LVCMOS33 and LVTTL standards that are 3.3V both but Im assuming they have different Vih thresholds. What happens inside the hardware to allow a different Vih to be detected? Is it different set of transistors?Cheers!

author: David Hess
author_rank: Super Contributor
timestamp: August 29, 2021, 11:34:19 am
content: LVTTL has the same input thresholds as TTL and they match 3.3 volt CMOS pretty well so they may be using the same receiver for both.

author: hal9001
author_rank: Regular Contributor
timestamp: August 31, 2021, 06:50:24 am
content: Quote from: David Hess on August 29, 2021, 11:34:19 amThanks!
Ring Oscillator to determine delay - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: August 13, 2021, 12:07:54 pm
content: G'day folks.I have implemented a Ring Oscillator and then I've included an extra 2 inverters located in another tile a few positions away from the Ring Oscillator.I've done this because I want to determine the delay caused by the routing.The ring oscillator should allow me to approximately calculate the delay of one inverter which I can than subtract from the overall delay, giving me the delay of the route.Unfortunately, the frequency of the oscillator is jumping around a little and isn't very different from that of the oscillator...Is there better way to measure the delay introduced by the routes???i am going to try and increase the number of inverters to see if I can slow things down... But I am not so confident with that approach. Also, increasing the number of inverters increases the error in my approximation.

author: Bassman59
author_rank: Super Contributor
timestamp: August 13, 2021, 02:52:27 pm
content: Remember that routing delay varies with temperature and voltage ...

author: nvmR
author_rank: Regular Contributor
timestamp: August 19, 2021, 12:31:26 pm
content: Interesting problem op.If I understand correctly, you are outputing both options to pins. Consider the fact that there are different "pin delays" between each output on the silicon die and the corresponding ball/pin.I assume you are using some sort of constraints to make sure the placement is in the location of your choice?My approach would be somewhere in the ballpark of implementing two counters, and use them to output a digital reading which would correspond to the delay, by counting a certain number of clock cycles of a inverter with a delay and without a delay. This removes the jitter of the ring oscillators from the picture - because it is averaged over time.This however adds other problems - as adding delay changes the behavior of the ring oscillator, so another approach is to XOR the delayed oscillator with an non-delayed oscillator, and count a reference clock.Again though, these approaches give you the affect of routing along with capacitance which changes the oscillator frequency.All this being said, a ring oscillator may not be the best of choices for this, as it is very sensitive to additional capacitance, and to process and voltage.

author: NorthGuy
author_rank: Super Contributor
timestamp: August 19, 2021, 10:37:23 pm
content: Quote from: steamedhams on August 13, 2021, 12:07:54 pmSure. Add 1000 LUTs in series. Make them part of the oscillator loop and observe the change in frequency.Or, you can do manual routing without even using extra LUTs. That's what manufacturers do to characterize routing delays. It's all known and used to run STA. Why do you want to measure routing delays on your own?There's about 3x variation in delay depending on process, temperature, voltage, and aging. You can use them in forensic work. People use delays to identify the specific FPGA chip, detect if the chip was used before, etc.
PWM output with Spartan 6 OSERDES2 - Page 1
Forum section: electronics / general

author: NiHaoMike
author_rank: Super Contributor
timestamp: August 15, 2021, 02:17:29 pm
content: Is there a good example of how to use OSERDES2 on the Spartan 6 as PWM outputs? My understanding is that it allows a higher resolution than implementing it in general purpose logic. PWM frequency target is about 15kHz.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 15, 2021, 05:06:00 pm
content: Well, sure, higher resolution for a given PWM frequency is achieved using a shorter time step, so a dedicated serializer could make sense.Note that in your case, @15 kHz => period = 66.66... usTo get an idea, to achieve 16-bit resolution, you'd need a ~1 ns resolution, so a serializer @~1 GHz.I don't have an example at hand, but it should be straightforward. Just feed the serializer with words made of a series of 1's (which will constitute the "high" level of the output signal) and then a series of 0's. The total number of bits, times the resolution, is the PWM period.

author: BrianHG
author_rank: Super Contributor
timestamp: August 16, 2021, 02:16:24 am
content: You basically need to manually simulate a serial position when sending a fat parallel word into the serializer to get that extended 2x/4x/5x output via software. This is simple when you use for example, a 2:1 serializer or DDR output and have an even PWM size.Example, say I want a 65536 PWM running at 1GHz, but my FPGA logic can only handle a 500MHz counter max, I would:Main loop_timer = 65535 -> 0 , -2 per 500MHz clock, beginData serilizer 2:1 source bit 1 <= PWM_output_val > (loop_timer - 1) ;bit 0 <= PWM_output_val > (loop_timer - 0) ;endYou can imagine using a 4:1 serializer by running the loop_timer at 250MHz, -4 per clock and extending the source bit input to source bits 3,2,1,0.Or you can do a 8:1, or 16:1 and slow down the speed of your loop_timer and it's section of code. You should be able to use 3/10/20GHz transmitters to make an insanely precise PWM.Odd numbers like 5:1 or 10:1 can also work, but, the compiler wont simplify out the logic gates a neatly as power of 2s.(Oh, don't forget to latch 'PWM_output_val' once every loop around of 'loop_timer', otherwise you will get random gobble in the middle if the that reg changes at a lemon time.)Also flip everything around to positive and add to simplify gate count.Writing it out my way allows the same code to function on any vendor's FPGA who has a DDR output or a serializer output with a parallel input. Only the IOBUF/OSERDES function initiation will be vendor specific.
Configuring Multiple Xilinx FPGAs From 1 SPI Flash? - Page 1
Forum section: electronics / general

author: petersanch
author_rank: Regular Contributor
timestamp: August 09, 2021, 10:42:05 am
content: Daisy chaining JTAG to multiple Spartan 6 FPGAs is possible according to UG380 document, is it also possible for 1 SPI flash to configure multiple FPGAs in the JTAG chain?Cheers!

author: asmi
author_rank: Super Contributor
timestamp: August 09, 2021, 12:50:50 pm
content: Yes it is, see Chapter 9 of that very document.

author: petersanch
author_rank: Regular Contributor
timestamp: August 10, 2021, 09:51:56 am
content: Quote from: asmi on August 09, 2021, 12:50:50 pmThanks exactly what I was looking for!
Techniques to measuring propagation delay of FPGA routes - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: August 04, 2021, 08:57:57 am
content: I have been tasked to measure the propagation delay of FPGA routes.From the googling I did, it appears I use a ring oscillator into another inverter, then compare the difference with the ring oscillator output arrival time with that of the inverter.I have been given a circuit that should provide me with the delay. However, I cannot understand the OR gate timing graph.Can anyone explain this??

author: FenTiger
author_rank: Regular Contributor
timestamp: August 04, 2021, 02:54:49 pm
content: I think that diagram is labelled wrongly. The time from the rising edge of I0 to the rising edge of I1 should be labelled 𝛿2H. The 𝛿2L label should apply to the time from the subsequent falling edge of I0 to the falling edge of I1.Given that change, I think I understand the circuit: when the AND gate is selected, the LUT output goes high when I0 goes low, but doesn't go low until I1 goes high, so the oscillator period includes 𝛿2H but not 𝛿2L. Similarly, when the OR gate is selected, the LUT output goes low when I0 goes high, but doesn't go high until I1 goes low, so the period includes 𝛿2L but not 𝛿2H.
MachXO2 FIFO_DC - are clocks really independent? - Page 1
Forum section: electronics / general

author: ataradov
author_rank: Super Contributor
timestamp: August 03, 2021, 06:58:19 am
content: MachXO2 family has FIFO_DC (First In First Out Dual Clock) primitive. As the name suggests, it has separate read and write clocks.I can't find a confirmation anywhere that those clocks are really independent or they can only be derived from the same clock.So the question is - is this FIFO really dual clock, so it can be used for cross clock domain transfer of data? Anyone has any experience or pointers to the documentation I missed?

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 03, 2021, 07:05:58 pm
content: I have completed a few projects using a MachXO2, so I'd think I have significant experience with it.But... I've never actually used FIFO_DC for clock domain crossing on MachXO2 (I have used True dual port memory for this, and it sure worked.)Reading back the documentation, I can see why you'd be confused. I agree: it's absolutely not clear. I can just say that I'd be very surprised if the "dual-clock FIFO" didn't support clocks on separate domains. But yeah, the docs are pure mess.

author: ataradov
author_rank: Super Contributor
timestamp: August 03, 2021, 07:57:11 pm
content: I'll do a test project later today. I have everything setup with a soft cross-domain FIFO, so I'll just replace that. And the project transfers gigabytes of data, so if there are any issues, they will be obvious. I'll report back.

author: ataradov
author_rank: Super Contributor
timestamp: August 04, 2021, 01:45:42 am
content: It does look like it is a real dual clock FIFO. I tested with 120 MHz (PLL output multiplied from CMOS oscillator) and 133 MHz (internal RC) source clock and 30 MHz target clock (from a different CMOS oscillator). I transferred over 60 GB of random data for both clock configurations with no errors.This is a nice thing to have. It just eliminated a custom cross domain FIFO and simplified design quite a bit.EDIT: In one of the documents there is an indirect confirmation: "Another clock latency is added due to the clock domain transfer from write clock to read clock using another register which is clocked by read clock that is enabled by read enable."And now that 133 MHz -> 30 MHz transferred over 250 GB, it is well confirmed.

author: fourfathom
author_rank: Super Contributor
timestamp: August 04, 2021, 04:47:29 am
content: I've used the MachX02 DC FIFO, where one clock is the internal PLL running at 100 MHz and synched to an external 10 MHz reference, and the other is the internal clock generator running at 16 MHz. Works great.
Question about shortest-path algorithm during synchronous circuit synthesis - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: July 27, 2021, 09:53:42 am
content: InRetiming synchronous circuitry, why put a negative sign tod(u)in step 1 ? Why there is no subtraction operation forW(u, v)in step 3 ?Note:1. The quantity W(u, v) is the minimum number of registers on any path from vertex u to vertex v2. The quantity D(u, v) is the maximum total propagation delay on any critical path from u to v
VCD to CSV Conversion - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 26, 2021, 01:34:20 pm
content: Hi,I have written some test benches that would read csv files and apply signals to DUT, Now I have a VCD file, I want to know is there a tool or utility to convert it to a csv file?My sample file is attached for reference.

author: BrianHG
author_rank: Super Contributor
timestamp: July 26, 2021, 03:05:10 pm
content: It's a simple ASCII file. You can write your own VCD file reader directly in your verilog testbench.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: July 27, 2021, 08:23:03 am
content: It's way more complicated than a csv file, I have written something like this for my csv fileCode:reg r_i_clk [0:65536];reg r_G_MISO [0:65536];reg r_G_SCK [0:65536];reg r_G_MOSI [0:65536];reg r_G_SS [0:65536];integer file;string line;integer lineNumber = 0,timeunitCsv,rePlayLineNumber = 0;//file operationinitialbegin////////////// Read the input file and fill the input arrayfile=$fopen("STM32SlaveSPI/SPIwrite25_core0_window0.csv","r");if(file)$display("File opened succesfuly %d",file);else$display("Can not open the file %d",file);//if we have valid file read it for me!if(file) begin//Read the top 3 lines of the file, becuase they are string info and we do not need them$fgets(line,file);$display("%s",line);$fgets(line,file);$display("%s",line);$fgets(line,file);$display("%s",line);//now read the content of the whole filewhile(!$feof(file)) begin$fgets(line,file);$sscanf(line,"%d, %b, %b, %b, %b, %b",timeunitCsv,r_i_clk,r_G_MISO,r_G_SCK,r_G_MOSI,r_G_SS);/*$display("linenumber %d",lineNumber);$display("time unit: %d us",timeunitCsv);$display("ick %b",r_i_clk);$display("miso %d",r_G_MISO);$display("sck %d",r_G_SCK);$display("mosi %d",r_G_MOSI);$display("ss %d",r_G_SS);*/lineNumber++;end$fclose(file);endend
AHB-Lite Crossbar - Page 1
Forum section: electronics / general

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 20, 2021, 08:19:41 pm
content: Does anyone have a clear description and possible HDL implementation of a typical AHB-Lite crossbar?I'm reading this:https://developer.arm.com/documentation/ihi0033/a/But if anyone has experience with implementing that, that would be interesting.
[SOLVED] Cyclone III project on Windows 10 with Quartus V13 - Page 1
Forum section: electronics / general

author: Frank
author_rank: Contributor
timestamp: July 15, 2021, 11:47:38 am
content: Hi all!I have to update some vhdl code for an old Altera Cyclone III project. I found that version 13 is the last version of Quartus supporting this family of FPGAs.Now comes the problem: there's no way to run Quartus 13 on Windows 10, not even with the compatibility modes.So, does anyone know a way to open and modify a Cyclone III project on Windows 10? Is there any way to run Quartus 13 in it?I'll try to find a computer with windows 7 or even XP to install Quartus, but I would rather use Windows 10.EDITThe solution for my problem was to install Quartus version 13.0.1.232.

author: oPossum
author_rank: Super Contributor
timestamp: July 15, 2021, 11:54:51 am
content: Quartus 13 does run on Win 10. What problems are you having getting it running?

author: BrianHG
author_rank: Super Contributor
timestamp: July 15, 2021, 11:57:21 am
content: If you are having trouble with the USB JTAG drivers, you may install newer Quartus drivers. Q13 can still use those. Do not try running earlier versions of Quartus's programmer with a 64bit OS as they don't seem to get along.

author: Frank
author_rank: Contributor
timestamp: July 15, 2021, 12:13:10 pm
content: Quote from: oPossum on July 15, 2021, 11:54:51 amWait... What? That's interesting!Here it never runs, already tried the 32 and 64 bits versions. But if it works on Windows 10 I'll try to reinstall it.Quote from: BrianHG on July 15, 2021, 11:57:21 amThat's the next thing I'll work on, the USB drivers.

author: BrianHG
author_rank: Super Contributor
timestamp: July 15, 2021, 12:31:32 pm
content: Quote from: Frank on July 15, 2021, 12:13:10 pmThe latest Quartus Prime USB drivers will also work on QII, V13.When running the QII V13 installer, try running the installer with Administrative privileges.It needs to generate a directory on your root C drive which Win10 may not like.

author: Frank
author_rank: Contributor
timestamp: July 19, 2021, 05:55:08 pm
content: So, finally Quartus 13 is running here!What I've found is that version13.0.1.232 workswith my Windows 10 instalation, but version 13.1.4.182 doesn't.My PC configuration:Windows 10 Pro version 20H2, OS compilation 19042.867Dell Precision Tower 7910 (Xeon E5-2695 v4, 64GB RAM)Quartus Version that works:13.0.1.232
FPGA Damaged - Page 1
Forum section: electronics / general

author: derek
author_rank: Contributor
timestamp: August 22, 2021, 07:29:22 pm
content: HI,I need some advice, I was programming a Lattice LPX2-8E-5TQFP144, with an updated FPGA code.But I got the programming pins on the JEDEC interface the wrong way around, the correct pin connection should be:Pin Function1. Vcc2. TDO3. TDI4. TMS5. GND6. TCKAccidently, I connected the JEDEC interface as:Pin Function1. TCK2. GND3. TMS4. TDI5. TDO6. VccThe programming failed.After seeing my stupid mistake, I reversed the connector, but Chip ID could not be found.Is the LPX2 damaged and requies replacing?

author: ataradov
author_rank: Super Contributor
timestamp: August 22, 2021, 09:06:13 pm
content: I doubt that this reversal would damage the device. If anything, applying VCC to the TCK may have damaged the programmer.Although TDO would be shorted to GND and driven by the FPGA. This is not ideal, but again, I doubt it would cause any damage.I would look with with the scope and check how signals look like.A simple test for JTAG is to clock 32 cycles on the TCK while TMS is low, and you should see some data on the TDO pin. This would be a Chip ID.Also, the device may have JTAG permanently disabled. In this case, there is nothing you can do.
Looking for Enterpoint development board manuals - Page 1
Forum section: electronics / general

author: philpem
author_rank: Frequent Contributor
timestamp: July 05, 2021, 09:15:19 pm
content: It looks like Enterpoint (www.enterpoint.co.uk), a UK-based maker of FPGA dev boards, has closed down.I've got one of their Drigmorn2 dev boards and some of the addon modules. Does anyone have a copy of these documents?- Ethernet PHY schematic (ETHERNET_PHY_V2.pdf or ETHERNET_PROJECT.pdf)- Cy7C68014 USB2 Slave module schematic (USB_SLAVE_MODULE.pdf)Sadly they're missing from the Internet Archive version of their website.ThanksPhil.
Synthesis : Pan's Algorithm - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: July 08, 2021, 08:28:52 am
content: Have anyone studiedPan's Algorithmpreviously ?1. How is Pan's algorithm being a shortest-path algorithm when clock period is computed across the critical path (longest path) ?2. Any idea about themodified version of Pan's algorithmdescribed in Figure 2 on page 4 ?3. How doesHoward's algorithmavoidsre-mapping of the non-critical nodes?4. It seems that Figures 2 and 3 of another paper :An Integrated Technology Mapping Environmentresemble Pan's Algorithm ?Why do the paper authors state that for a given node, the fanin are known at current optimization iteration, but the fanouts are known only for the previous optimization iteration ?
Understanding Timing Constraints - Page 1
Forum section: electronics / general

author: netturan
author_rank: Newbie
timestamp: July 05, 2021, 12:50:31 pm
content: I've recently started to explore the world of FPGA and it has really been a productive journey so far. I've been writing HDL designs and going through different resources so far.Now that I've got my first FPGA I've decided to test my design finally.I've been reading about how I need to look into more details regarding timing and I wanted to know what exactly do I need make sure that my design works.1. My design has a communication interface that takes in commands at a faster clock and sends triggers to my design to execute it. For this I have written up 2ff synchroniser that toggles everytime a command is to be executed.( Something I read up about clock domain crossing, don't know much)2. Another part of my design has an edge detector that detects an edge in a non clock signal using a delay registerKeeping this in mind what should be my goal while writing timing constraints ?

author: rstofer
author_rank: Super Contributor
timestamp: July 05, 2021, 02:22:39 pm
content: https://www.doulos.com/knowhow/fpga/synchronization-and-edge-detection/I have written some fairly complex projects and never worried about timing. I specified the clock rate and symmetry and the tool (Xilinx ISE or Vivado) took care of everything else. Of course, I was only running at 100 MHz. Maybe if I pushed the speed envelope things would be different.https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug903-vivado-using-constraints.pdfThere are videos re: the Timing Constraints tool. Google for 'xilinx vivado timing constraints'

author: netturan
author_rank: Newbie
timestamp: July 05, 2021, 02:34:42 pm
content: Well my internal logic is being run at below 10MHz but the part that I'm worried about is if there will be any issues when the communication interface(JTAG) works at a drastically higher frequency.

author: rstofer
author_rank: Super Contributor
timestamp: July 05, 2021, 03:47:00 pm
content: I don't see how the IO portion of your gadget is going to run faster than the system clock. Sure, you can run the logic at a submultiple of the system clock but, in the end, everything needs to be synchronized to the system clock. There are usually clock managers on-chip for the very purpose of creating phase accurate (sub)multiple clocks.But I still don't see how the internal logic, running much slower than the JTAG IO, is going to work.
JTAG simulation on Lattice MachXO2 - Page 1
Forum section: electronics / general

author: netturan
author_rank: Newbie
timestamp: July 02, 2021, 10:55:07 am
content: Anyone knows how I can simulate the JTAGF primitive (used for accessing the internal logic) found on the MachXO2 on a testbench ? I'm trying to use it to communicate and send data to the FPGA via JTAG.
Any good beginner ideas for teaching? - Page 1
Forum section: electronics / general

author: LoveLaika
author_rank: Frequent Contributor
timestamp: July 31, 2021, 09:21:35 pm
content: I'm planning to teach some rather bare-bones basics of FPGAs to some people, and I was wondering what kind of interactive projects can be good to show off the capabilities of FPGAs in general (using a Basys 3 board)? The crowd I'm teaching to has some basic knowledge about electronics, but they know nothing about FPGAs, and this session is probably for an hour or so, so nothing really long term. Just something that would help them get their feet wet into FPGAs. It's been a while since I worked with FPGAs, and I can't really think about anything that would make me think "wow...what else can I do with FPGAs". Any ideas?I was also thinking...maybe for a show-off project that would show off the power of an FPGA, something like a pre-made project like Pong or Nand2Tetris may be good, but nothing that the students would program. I thought it would be cool for them to see some big project that can be done with an FPGA, but that might be too troublesome in its own right.

author: cfbsoftware
author_rank: Regular Contributor
timestamp: August 01, 2021, 12:13:13 am
content: Check out some of the ideas on FPGA for Fun:https://www.fpga4fun.com/
Moving design between different variants - Page 1
Forum section: electronics / general

author: Mario87
author_rank: Frequent Contributor
timestamp: June 29, 2021, 07:13:44 am
content: Hi all,New to FPGA's not properly looked at them since I was at uni other than a little bit at the end of last year. Got a Basys 3 dev board on its which which I'm using along side a text book to learn Verilog / VHDL, etc.Now I have a long term project I want to fulfil, but any dev board I see which fits the bill in terms of peripherals has an FPGA which I think might be a bit more than what I need.So my question is, if I make a design on a higher end Artix-7 FPGA, get it working on the dev board, etc. How hard is it to move that design to a lower spec variant of the Artix-7 FPGA family?Is it just a case of chose the correct FPGA in vivado, map the pins accordingly to the new FPGA and done? Or is there a fair bit of work involved to go from one to the other?

author: hamster_nz
author_rank: Super Contributor
timestamp: June 29, 2021, 07:34:06 am
content: It is as you say - cjange the project setting, change the constraints, and press 'generate bitstream'.Going between vendors is usually a bit harder, as the 'edges' of a design usually uses vendor-specific primatives and features.

author: Mario87
author_rank: Frequent Contributor
timestamp: June 29, 2021, 07:56:25 am
content: Great, thanks! I thought that would be the case, especially with the same vendor and product line, but decided it would be best to ask.

author: hamster_nz
author_rank: Super Contributor
timestamp: June 29, 2021, 08:54:08 am
content: Oh, and for some parts you can play "guess which are the same die, but with different fusing", making it even less problematic to change parts.

author: NorthGuy
author_rank: Super Contributor
timestamp: June 29, 2021, 12:51:47 pm
content: Quote from: Mario87 on June 29, 2021, 07:13:44 amMoving design is very easy. Buying lower spec Artixes is not

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 29, 2021, 06:05:30 pm
content: Quote from: NorthGuy on June 29, 2021, 12:51:47 pmAh, indeed!!
FPGA BRAM power consumption, how to figure this out? - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: June 25, 2021, 09:19:27 am
content: I am looking at the Xilinx estimation tool to try and figure out how they have arrived at their estimation.For instance:This is the basic equation they use for the BRAM.VCC * (Number of BRAMs)* (PortA_clock * ((read_rate * bit_mA) + (write_rate * bit_mA)) + PortB_clock * ((read_rate * bit_mA) + (write_rate * bit_mA)))They have determined the reading and writing of one bit to be approx 1 mA.Then they have used a read and write rate.How do you think they've determined such values? (Image attached)I would really like to know how people come up with these numbers...My thoughts:I could open up spice then try and recreate the same circuit which will likely be way off. (Caps, resistors, transistor W/L)OrPhysically measure the reading of data for a given BRAM block, then just estimate some valid numbers that aren't too far off.Or ideally, I can do both and see how far off they are. Then I can use the simulated values and add the different as a percentage.I would like to apply their approach to other FPGAs or even improve upon these estimations.

author: actuallyjaseg
author_rank: Contributor
timestamp: June 29, 2021, 08:23:30 am
content: To me, the formula looks like a first-order approximation (I'd assume current consumption will be non-linear in clock speed, VCC and temperature). I would assume they chose this approximation by guessing and then validating that reality stays within a certain error band of the approximation.I'd be surprised if they did not simply measure these values using some minimal benchmark design. Program the chip with a design that continuously addresses all the BRAMs on the chip and has a read/write toggle from outside, then let it run for a second and average the chip's current consumption. Repeat for a couple chips from the same series. To take into account the effect of the benchmark's logic driving the BRAM, someone at Xilinx could simply take the routed design and remove the BRAMs from it, leaving everything else in place.I would guess that they simulated the components of the BRAM, but never the whole block at once.
Cmod A7 driving some DACs - Page 1
Forum section: electronics / general

author: ezalys
author_rank: Frequent Contributor
timestamp: August 17, 2021, 11:42:24 pm
content: Hey everyone, I'm curious about using the Cmod A7 to drive a pair of DAC3174s. I'm curious aboutWhich pins can be used as LVDS pairs?Of those pairs, what kind of DDR datarate can I hit?How will the signal integrity look after cramming those fast signals through those 0.1" headersBest wishes,Evan

author: asmi
author_rank: Super Contributor
timestamp: August 18, 2021, 01:17:14 am
content: I'm afraid you can't use that board to drive LVDS because 7 series FPGA's IO bank needs to be powered by 2.5 V in order to output LVDS (inputs are possible with any Vccio if you don't use on-chip termination and instead use external resistors), and as far as I remember Cmod A7 is a 3.3V-only system. Answering questions 2 and 3 seems pointless in light of that, but in general all differential pairs of 7 series FPGAs are identical and can reach the same data rate using SERDES (950 Mbps for speed grade 1, 1250 Mbps for SG 2 and 3). As for SI, I think your main issue will be a lack of length matching (both within diff pair and between lanes) and not necessarily connector itself.