4 PCB Layer Stackup - Page 1
Forum section: electronics / general

author: KulinBAn
author_rank: Newbie
timestamp: March 07, 2022, 07:15:26 pm
content: HelloI have the following issue:LM2596(+5V to +3V8), STM-32G070RBT6(+3V3), TF-15X15(+3V3), SIM800C(+3V8), AMS1117(+5V to +3V3)With all these voltage levels what would be the ideal layer stack up?I am thinking of GND plane on the F.Cu and +3V3 on B.Cu,should I use the 2 inner layers for signals or add addition power plane and GND plane and place the signals on top?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 07, 2022, 09:31:15 pm
content: Sure, and where do you place all the components? Inner layers as well?Snark aside, food for thought is how solid the planes will be in such a design. Signals and components should almost always be adjacent to a ground plane, so the ground plane works best as a solid, well, plane.(Also, doubly aside: it's not 100% snark; there are actually processes to place components on inner layers, laminated into the board itself. Sounds crazy, right? Well, needless to say, it's well above the price of your average proto build. Still, neat that it's possible.)And -- if you were putting ground on the outside layers, what more are you doing with 4, that can't be done with just 2? The component density can't be very high that way: the above rule prohibits components placed in the same location on opposite sides -- their footprints and trace routing would void out both planes in the area -- so you're limited to lower density or single-side placement. The inner layers get you easier routing, but that might not matter if you have plenty of area to spare. if you don't have too many signals (which seems likely with the devices listed?), they're fine to route on 2 layers, so long as traces/buses overlap a minimum, and stitching vias are placed frequently (particularly around trace/bus crossings, which should be at or near right angles to minimize the region where neither plane can reach).You do get better shielding of signal traces on inner layers (by outer planes), but in practice this rarely matters; inner-plane designs are adequate for essentially any commercial or industrial application. The fact that the planes are beneath the traces, very close by, affords quite a lot of shielding value already, even though they're still line-of-sight visible on the surface. Outer planes can be suggested for especially demanding applications (exposed to, or containing, exceptionally high levels of RF?), and, say, where the height (or cost?) of a shield can would be too much.So, by far the better plan is to use planes on inner layers, and signal routing on outer layers is easy, needs no extra vias to connect to SMT components, and has excellent performance.Note that, in the 2-layer case, essentially by stitching together partial planes on both layers, you get one reasonably-contiguous plane over the whole board. Averaging one layer in the middle, as it were. Most of the time, you want about half of the board as planes, so 2 planes are great for 4-layer designs, and this single average plane is what you can get with a 2-layer design. (Somewhat less than half, is acceptable for most designs, so for example, a 6-layer board is usually done with two planes, using the extra two layers to ease signal routing of exceptionally dense boards. Or to increase conductor cross-section in power boards.) So for 2 layers, you would assign that plane as GND, and route signal and power as traces. For 4 layers, you'd assign GND as one, and the other inner plane can be cut up as needed by region, or assigned to one priority (probably 3V3 if any?) and the remaining supplies routed as traces.Tim

author: PlainName
author_rank: Super Contributor
timestamp: March 08, 2022, 10:12:32 pm
content: Telit support recommended to me that, for a project with their GSM modem, it was preferable to have ground planes on the outer layers (punctuated only by component pads) and bury power and interconnects on internal layers.

author: montemcguire
author_rank: Regular Contributor
timestamp: April 25, 2022, 03:27:29 am
content: I've been using four layer PCBs for analog and simple logic, and what has worked well for me is to use the two inner layers for +17V and -17V to power analog, and use the two outer layers for component placement, trace routing, and copper pours to create a ground system. For mostly logic, you can use the inner layers for +3V3 and DGND instead, and if needed, you can add polygon 'islands' of ±17 or whatever special voltage you need. You can also use the inner layers for occasional routing, but in my designs, I want the power planes to be as 'unmolested' as possible so they remain low impedance.The reason this works well enough is that if most of the routing is on the outer layers, the traces will be next to the placed components, so you can avoid vias as often as possible. Sure, you need vias, but on budget PCBs, they cut through all 4 layers, so you need to avoid them as much as possible. Additionally, the stackups I get place the inner layers fairly close to the outer layers, with a relatively thick core. This means that the power planes will be fairly close to the outer ground pours, lowering the impedance of both. And, the power planes will also work as crude ground planes in that they will isolate the top and bottom layers of the board.One final suggestion with a 4 layer board is to try to remove as little copper as possible from each layer. You don't want orphaned pieces of foil, but arrange each layer to be mostly intact. This will reduce the impedance of the outer copper ground pours and the inner planes, and most importantly, it will help to make the finished board as flat as possible. If you delete a lot of copper in one area, it will make the board thinner in that area. If the overall copper distribution isn't that uniform, it can make the board expand and contract irregularly as it is reflowed, since the copper expands and contracts differently than FR4, building in tension and warpage. Nobody needs that! Besides - you paid for the copper, so why not use it all.

author: PlainName
author_rank: Super Contributor
timestamp: April 25, 2022, 10:31:53 am
content: The embedded power/gnd plane with signals on the outer layers thing is apparently what best practice used to be, but things have changed since. A reasonable explanation of this stuff is from this Altium video:Discussion of a 4-layer stackup (gnd, sig/pwr, sig/pwr, gnd) is around 1:41:00 (it's a long video!).For reference, 6-layer board stackups to avoid are at 1:44:55 and a preferred stackup is illustrated at around 1:48:00.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 25, 2022, 12:34:26 pm
content: 1:42:15 I assume when he's saying "it wasn't a five minute operation" it took several days, otherwise why, like, why mention it, why even remember it from >20 years ago..?I mean, for my part at least, I hardly remember what boards I did five or ten years ago. I have to look up the files to remember what all's on a thing, and that's if I've even remembered the right project...Note he doesn't explain ANYTHING about the environment -- just that there was some board, somewhere, somehow, and swapping around the layers this way, solved it. It fills time in a talk, but it's not real useful advice -- EMC is a holistic problem space, and cannot be approached on an individual-item basis, not without justification of it.Some possible facts he's glossed over might include:- Plastic enclosure- Metallic enclosure but with unusual (especially EM-unfriendly) design, effectively acting as antenna- Unusual standards e.g. electric near-field or TEM cell- Strict standards e.g. MIL-STD for SIGINT purposes- Circuit and layout details e.g. number and placement of bypass caps, ferrite beads, etc.To be clear, there are plenty of situations where such an arrangement can be a problem, and where those problems are solved with this solution; there are also situations where it has little effect, or even makes things worse.The couple minutes leading up to this are similarly undefined: the distance between planes, and radius of field effect, are wholly arbitrary conditions. Between planes, the incident field from a via spreads out radially, inverse with distance -- at what point is it zero? Never! We might only care that it expands to a certain point, that point corresponding to some threshold amplitude, below which we don't care, it's just background noise. Maybe that's some 10s mV, maybe ~uV. And since it expands inverse with distance, we can take that distance as a ratio to via or plane clearance diameter, or plane spacing, and figure some amount of attenuation due to that geometric factor. Maybe that's some inches as he suggests, maybe it's less than a via diameter (completely irrelevant).He does at least close that section by noting it might matterfor extremely sensitive analog applications. In other words, there's, I don't know, microvolts in the gap? It should actually be quite a bit more than that, like the ~1ns edges from some LVCMOS devices (e.g. MCU, FPGA) might tend to cause some ~mV in the plane areas where those image currents flow. Still irrelevant for digital signal quality purposes (as usual: assuming jitter isn't a concern), and can be avoided by simply not routing your dirty digital power over the sensitive analog section.The important thing is to think about these relationships, quantitatively. What ratios of signal and noise levels should you expect, given via, plane spacing, plane width/length dimensions, signal risetime, etc., and how does that compare to the required noise floor?One more thing: not only did it presumably take them some time to complete the reroute -- he notes it took some massaging to get the internal pours to connect. That's especially chilling, and that I think is where the "even makes things worse" I said above, comes in.Consider what that routing must've looked like. The outer layers are stuffed full of components and pours. Every single non-ground pin has a via hanging off it. For fine-pitch components, this turns all four planes to Swiss cheese, cut straight through by the rows of vias. (I think we can assume thru-vias, since he said this was a cost-critical design.) Even if you stagger them, you end up with mesh patterns (= higher plane impedance, more leakage between layers) that can only route one or two traces between a gap, and every trace you squeeze through specifically excludes power from pouring there. It's not obvious if they were able to stitch the internal power planes; whether this was an oversight, or a limitation of board area (the biggest reason I don't like pouring outer copper on high density designs, is because it's such a PITA to stitch, trying to find any unrouted opening through all 4+ layers to stick a via into!), isn't said.And so, all of these effects combined: the severely cut-up power pours, the GND pours full of holes, the added inductance to pours due to thin and long sections -- it could well end up that some components malfunction outright due to insufficient power quality (PDN (power distribution network) fail), or emit excessive noise by the same reason (e.g. logic lines feeding cables, which when in logic-high state, couple supply noise directly into that cable). For an experienced designer, these are problems that can be managed -- budget allowing -- but it is absolutely not what I would encourage a beginner to tackle!Similarly for the 4/6 layer comparison at 1:48:00 ish -- absolutely, more planes gets lower impedance; but does that even matter? MCUs won't care. FPGAs or application CPUs of more than small size, you probably need the extra layers anyway for routing. And, if you're willing to take the time to route and stitch pours across multiple layers -- absolutely, it will perform better, but is it worth the time required?Other thoughts:Probably covered earlier in the video, but to say for those reading:The basic mechanism for a 4-layer inner-planes design to radiate from its planes, is as an extremely short, extremely thick dipole. Imagine a dipole antenna with wire diameter equal to board dimensions, and wire length equal to board thickness (say, averaged with component height, too). It's the inverse situation of the capacitor within; there's fringing field all around the edges, and less and less on the middle of the faces, or at a distance; it's a pretty shitty antenna, but this mode does indeed still exist, and it'll lead to radiation at suitable frequencies, given enough amplitude inside.So, for most commercial purposes, where frequencies under 1GHz are the concern, the limiting levels are ca. 40dBuV/m, the board is like say 0.1m across, and amplitudes within the board are ca. 0-20dBmV (i.e. 1-10mV, typical supply ripple levels; this would be pretty intense for ripple induced by digital loads I'd say, likely indicative of needing more bypass caps -- but stick with this for sake of argument, as a worst case figure), then you need something like 40dB attenuation between in-board voltages and external electric fields (per m). Which, probably a lot of that already comes by geometric factors -- this is an electrically-short structure so it has very little gain (but, increasing with frequency), and the receive antenna is at modest distance too (3m, 10m, whatever).If you have noisy planes -- well, why are you putting all that noise into them in the first place? You can identify individual sources and isolate them, whether on their own local planes (with whatever bypass is needed to manage them), and couple that to the main supply through filtering inductors. (Avoid ferrite beads here, as they saturate under DC bias -- they can be used, but check how much their value decreases at expected load -- that's the real hard part, almost no one provides these characteristics!) Or if it's a few particularly noisy traces, how about shielding them, you could route on an inner layer and pour GND/VCC over it just locally so the rest of the board doesn't mind, and you've not given up too much layout area to this priority route.Keep in mind also, the problem of mistaken attribution. It's very rare that we get a chance to roll multiple versions of a design, let alone test them all. I've only done that once as a matter of fact, and it was just a little carrier board for a PSU module. (Conclusion: comparing e.g. XP ECL10US09-T vs. XP EML15US09-E, the medical version is a good 15-20dB better, out of the box, though still not good enough to meet, I think it was CISPR 22 class B; best results require a common mode choke on thesecondary side, we used 100uH -- in addition to pri-sec 'Y' capacitance and a primary side CMC of some mH. This was an application with enough secondary-side wiring length, or earthing, that the PSU's claimed EMC performance was most definitely not met.) It's also rare that you'll only do one layout change (minor or major, as the case may be) per rev; you're adding and moving bypass caps, filter chokes/beads, shoving around components, filtering connectors, anything you can throw at the test to get it to pass -- and rarely if ever do you come back to confirm which of those changes were necessary.Tim

author: PlainName
author_rank: Super Contributor
timestamp: April 25, 2022, 01:38:56 pm
content: There's a 1:40 lead-up to that so it's possible he covered something earlier that you've missed when jumping to those partsAnother chappy does a shorter version and comes to a similar conclusion:However, he notes your comment re puncturing the ground planes and proposes an alternative of pwr/sig, gnd, gnd, pwr/sig. Of course, you still have no power plane, but it's the return path via the ground plane that really counts and power is just another signal. Except when it's the return path...

author: eugene
author_rank: Frequent Contributor
timestamp: April 25, 2022, 03:03:29 pm
content: One can probably find a good situation for just about any conceivable stack up. For example, I have made four layer boards with PWR/GND planes in the middle, analog on one side, and digital on the other. Putting the planes on the outside layers and the signals on the inside would probably not improve those designs and would more likely make them worse.This may or may not be an interesting academic discussion, but in the end internal plane layers and external signals is proven to work and is much easier to rework. If you have signals that really need to be shielded from external noise, then maybe consider them on internal layers or maybe consider putting the entire assembly in a shielded enclosure.Honestly, I would seriously consider going to six layers before I tried to make the outside layers entirely ground pours. Super sensitive signals can be placed on the inner most layers for shielding.

author: PlainName
author_rank: Super Contributor
timestamp: April 25, 2022, 06:49:19 pm
content: QuoteIt's not about shielding but return paths. With the inside planes, a return path will cross the power plane en route to ground. With outside grounds, that doesn't happen. Which is also why the second chap suggests two inside ground planes - wherever the signal is, the adjacent plane is ground.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 25, 2022, 07:34:23 pm
content: Non sequitur; a plane is a plane. Same return path, the image current doesn't care what DC potential it's at. It's merely give or take proximity of bypass caps (= stitching vias with a DC offset), and however many mV of ripple you can accept given the return path to the nearest bypass(es), or for the wave to spread out between planes (to similar effect, handled by plane capacitance instead, more or less).The one thing that you do get, is likely more stitching -- every ground thru-via stitches across all ground planes in the stack, whereas VCC/GND pairs to bypass caps only do it where they are placed, obviously. If you're running such magnitude where this is a concern (strong signals/current flows vs. sensitive signals), those (inter-plane) currents will drop off much quicker with distance (because of the higher density of vias), which is to say, signals are better shielded from each other in that case.I mean, it's not really, or kinda to mostly not really a non sequitur, but to the extent that, in principle: if you didn't care about how many bypass caps you're using, you can stud a board with as many bypasses as you might have stitching vias through all those planes, and get basically performance (it'll be a few dB worse just because the caps+vias have a few nH more ESL than direct internal layer-to-layer vias do). The real question is, how many do you really need/want, and if it's worth it. Which, I mean, it may be; it feels like a rarer case though is all.Tim

author: PlainName
author_rank: Super Contributor
timestamp: April 25, 2022, 08:54:42 pm
content: If it matters than I think it's sensible to do something even if it has negligible effect this time. Practice makes perfect, and all that, and when it does matter it will just be normal. Unless there is a downside, and whereas with external ground planes there are obvious ones like no access to internal tracking, the variations on that stackup mitigate the issues somewhat.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: April 26, 2022, 03:12:46 am
content: From what I understand:Power planes on inside layers, and signals on the outside.First, if you put the power planes on the outside, they're riddled with holes for the pads for the footprints.Second: If you put the planes on the outside, each pad will need via's, which uses additional space and pokes more holes in your planes.Third: Prepress is thin, and signals will be close to the GND (or other !) plane and coupling is therefore tight. and the difference concerning EMC is small.Forth: Making modifications for prototypes and fault finding & repair is much more difficult if the signal tracks are all on internal layers.

author: PlainName
author_rank: Super Contributor
timestamp: April 26, 2022, 10:11:07 am
content: I suggest that if you have the time you go through those videos from the start. They explain things much better than I could (but, of course, take their time doing so). The second is probably the better quick view.And.. y'all are concentrating on vias puncturing the planes and needing a via for every pad. But have you considered there will be a whole pad for every pad which is a hell of a lot bigger than a via. Except for ground pads, of course.AIUI, the via thing isn't an issue because the return path route follows it, wherever it is.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: April 26, 2022, 05:24:00 pm
content: Personally I much rather spend an hour or two watching an interesting video about PCB design then some soap on TV.via's through pads are a very bad thing for automated assembly.When you use a solder stencil, the amount of paste for each pad is fixed and a lot of the solder can (and will) wick into the via, unless special precautions are taken.This can (and does) make solder connections unreliable.Sometimes there is no choice, when you go to dense PCB's you may need small pitch BGA's or SMT parts are so close together that you run out of space.In such cases via's can be filled with epoxy, and they can even be plated over with conductive material.Those are all extra steps which have to be added consciously when ordering PCB's and they do make the PCB more expensive.The simplest and cheapest option is to have a PCB track buggering off for long enough to be covered by solder mask and then place a via.For hand soldering it does not matter. You visually inspect each solder joint when you make it, and you just add more solder until you're satisfied.

author: c64
author_rank: Frequent Contributor
timestamp: April 30, 2022, 02:26:47 am
content: My favorite stack-up: signal / power - gnd - gnd - signal / power. This way I always have solid ground next to signal and power, and inner layers are very close to adjacent outer layers.You only have 2 power rails and your sim module already has shielding. I see no point of having signals on inner layers.