CD4046 vs 74HC4046 vs 74LV4046A - Page 1
Forum section: electronics / projects

author: NiHaoMike
author_rank: Super Contributor
timestamp: December 22, 2019, 06:31:00 pm
content: I'm working on a transmitter that sends two AC current waveforms (bandwidth of a few kHz) over the power line, using two FM carriers in the 400-600kHz range. (Low latency is one of the big goals, hence why I didn't go for a digital encoding scheme.) I built a test circuit for the 74LV4046A, but found that the output has a lot of jitter even with the VCO input biased to a steady 2.5V.I found this post claiming that the original CD4046 is superior to the 74HC4046, at least as far as the VCO is concerned:https://groups.google.com/forum/#!topic/sci.electronics.cad/j1gD_xiz-rEI'm assuming that's because, in general, older processes are better for analog circuits while the opposite is true for digital. Would I be correct in assuming the 74LV4046A would still be inferior to the CD4046? (I have some CD4046 on order but it would be a while before they show up.)Or would I be better off with some other VCO/PLL circuit? Or even a completely different modulation scheme?

author: fcb
author_rank: Super Contributor
timestamp: December 22, 2019, 06:40:59 pm
content: Difficult to know as not a huge amount of info in your post.It's been along time since I used the 4046 - there certainly was an excellent set of application notes that covered this part (seem to remember they also covered the 7046). In the 400-600KHz region you shouldn't have any problems - some of the CMOS (CD4046) units run out of steam in the low MHz range (perhaps 5MHz). The 74HC series when run at 5V will go to 17MHz or so (I used them for cheap video clocks). I don't think you'll reduce the jitter just by changing the IC series/process.You might be as well to build to PLL's with them and then modulate the VCO (keeping your PLL filter loop speed nice and low so you don't correct out the input) - how low does your modulation frequency need to go?

author: NiHaoMike
author_rank: Super Contributor
timestamp: December 22, 2019, 07:04:06 pm
content: Quote from: fcb on December 22, 2019, 06:40:59 pmLowest frequency of interest is the 60Hz fundamental, I think a loop bandwidth of just a few Hz would be plenty since I just want to make sure the carriers (which would be spaced something like 30-60kHz apart, with a peak to peak deviation of 15kHz or less) don't drift into each other.

author: Benta
author_rank: Super Contributor
timestamp: December 22, 2019, 07:25:38 pm
content: Which PFC are you using? 1 or 2?PC1 will play along at 400...600 kHz, PC2 not. The VCO is not the limiting factor here.The datasheets and application notes around the 4046 (all flavors) are atrocious and full of errors concerning the PC2 and can only be used for circuits with PC1.

author: NiHaoMike
author_rank: Super Contributor
timestamp: December 22, 2019, 07:49:09 pm
content: I'm running it open loop for testing purposes. I plan to use divide by N counters from the outputs to the phase comparators, so they will actually be working on the 32.768kHz or 38.4kHz signal from the frequency reference circuit.

author: Benta
author_rank: Super Contributor
timestamp: December 22, 2019, 07:54:09 pm
content: That didn't answer my question, and it's central to using the 4046.

author: NiHaoMike
author_rank: Super Contributor
timestamp: December 22, 2019, 09:38:17 pm
content: I'm under the impression the phase detectors are separate from the VCO and that the jitter issue has nothing to do with them. There are actually 3 different phase detectors on the 74HC4046 and 74LV4046 (as opposed to just 2 on the CD4046), I'm not sure which one would be best for my application but I'm thinking PC2 since that only applies "corrections" as it needs to.I read somewhere that its suggested configuration of the single timing capacitor causes charge injection and that a pair of capacitors to ground avoids that problem. I tried that and it seems to have reduced the jitter considerably. I then tried sweeping the VCO input and found that the 74LV4046A has the same "nonlinearity" within 0.5V or so of the supply rails that the 74HC4046 has, but I'm not sure if the CD4046 fares any better since I don't have one of those to try yet.I also wonder what kind of dynamic range I could get out of the system with the receive end doing the decoding in a FPGA. I plan to implement companding of the signal, with a few kHz pilot tone to allow proper amplitude scaling and fast detection of signal loss.

author: Gyro
author_rank: Super Contributor
timestamp: December 22, 2019, 10:08:46 pm
content: Try a forum search, there's a fairly long thread on here somewhere. Something about the later families having significant phase detector dead-zones compared to the CD4046 irrc.EDIT: This one I think...https://www.eevblog.com/forum/projects/using-4046-type-plls-successfully/

author: dmendesf
author_rank: Frequent Contributor
timestamp: December 22, 2019, 10:33:30 pm
content: If PC2 is better to your application then look for the 74hc9046a. It gives up the PC3 but has a fixed PC2 (without dead zones). About running it open loop (with fixed voltage) to test... This doesn't work well because of noise injection / temperature fluctuations. You need to close the loop and fix the input to evaluate the whole system.