What makes PCI express faster as of version 3.0? - Page 1
Forum section: electronics / beginners

author: tigrou
author_rank: Regular Contributor
timestamp: May 03, 2023, 10:14:23 am
content: It seems every new iteration of PCI express since 3.X double the bandwidth :I have been wondering if, beside doubling the clock speed, there was any other improvements that helps increasing bandwidth (from 3.0 to 5.0).If it's the case, then it means what allows to increase speed is mostly using better copper quality, am I right ?Starting PCI 6.0, it use PAM-4 and thus 4 Levels of signaling just like G6X memory (so it's no more about clock speed).

author: MarginallyStable
author_rank: Regular Contributor
timestamp: May 03, 2023, 03:42:12 pm
content: I would say there is most likely more going on behind the scene. For example tighter specifications for impedance/trace length, connectors, etc. Also the increased bit rates probably require some additional advances of SERDES functionality.

author: MathWizard
author_rank: Super Contributor
timestamp: May 04, 2023, 03:23:56 pm
content: Does anyone take the external oscillators off these type of products, to use in their own circuits ? I've made crystal oscillators up to about 24MHz before, on a breadboard even (or a copper clad board anyways). But I've never tried any of the various SMD xtals or clock chips, from off a mobo or GPU or cablebox.

author: Berni
author_rank: Super Contributor
timestamp: May 05, 2023, 05:43:50 am
content: You need faster SERDES sections in chips to actually run at these higher clock speeds. So that's why they didn't go straight for PCIe 4.0 speed from the startIt takes time to develop the chips that run this fast, verify these designs for working reliably. It has to be compatible with various PCIe hardware out there, the motherboards have to meet the signal integrity specs..etc. You also need clock recovery to work properly at the higher speeds. Taking gradual steps up in speed also lets you watch how it performs in the market. Like do users actually need the higher speed? Are there other bottlenecks that limit how much speed is actually usable? Are the motherboard vendors keeping up with the signal integrity requirements? Are there any failures/problems showing up?Slowly easing into more complexity is also a good way to get a standard out there. If implementing some interface standard is too complex and expensive for the benefit it brings then no manufacturers will actually implement it, resulting in the standard being just a pile of papers gathering dust with no real world implementation. For example Thunderbolt is having some trouble getting off the ground because of being difficult to implement.There is also some extra tricks introduced. Like for example signal preemphesis on the TX side, so that extra high frequency content is introduced into the signal that then gets reduced back down by the losses in the traces, giving you a cleaner square wave on the RX side.

author: jwet
author_rank: Frequent Contributor
timestamp: May 05, 2023, 04:15:13 pm
content: Some if not all of this is coming down in process node size in the SerDes. 2010 was about 45 nm and it followed Moore's law basically- 2012- 22 nm, 2014- 14 nm, etc. We're at something like 5 or7 nm now and many have declared the end of Moore. The transition frequency Ft is proportional to Vds sat/L^2 so you get something like 1/L since Vds is also coming down. The speeds might keep marching down but it won't be process driven any more. It will likely be using encoding tricks or other means- you can already see PAM-4 or PAM-16 in latest versions. Ft is likely maxed out.