Processor UART expansion via SRAM-like interface to FPGA - Page 1
Forum section: electronics / general

author: jt
author_rank: Regular Contributor
timestamp: December 18, 2016, 01:54:48 am
content: I'm looking at options to add additional UART peripherals (on the order of 10) to a processor without resorting to bit banging GPIOs. The UART peripherals would be used simultaneously, so multiplexing the existing peripherals is not an option. I don't have strict baud rate requirements (yet), but up to 1Mb/s would give good headroom.I see that there are some ASIC options to bridge SPI to UART but it doesn't look like this will be practical in approaching my expansion goal. I might be able to get there through some combination of a USB hub and multiple FTDI USB-UART devices, but that seems overly complicated and power hungry.I've been hesitant to consider an FPGA-companion due to my associated inexperience, however it is looking like the technically best option. So, barring any other ideas, I was hoping to get some guidance as to how to select the FPGA. I've had my eye on the Lattice Semi MachXO3LF family. They are marketed for this type of bridging application and the internal flash would appear to simplify system design compared to other options requiring an external device to store configuration. Looks like there is a wide range of pin-count options so I could optimize package size for my needs. Any other FPGA options I should trade?I *think* the best way to glue the FPGA to the processor would be through an "SRAM-like" interface using the processor's general purpose memory controller (which would be shared with NAND Flash). I believe this is a relatively common topology (but again, I'm inexperience here). Does this seem like a good approach?Also, any wags as to what power consumption I should expect from the FPGA (for the sake of discussion assume all I/O ports active)?Ultimately, the best solution might be to ditch the processor and go to a Zynq, but there is a fair amount of legacy development on the existing processor and I'm not sure I have the schedule for the porting effort.

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: December 18, 2016, 02:15:25 am
content: The FPGA approach is one used byTechnologic Systemsin their computer on module products. They have schematics available for many boards, for example the TS-4710 that uses a Lattice XP2 on the SMC bus of an iMX6. It's a good design, and they went the additional mile by simplifying the UARTs and making their own userland driver, rather than writing a kernel driver for Linux.

author: Someone
author_rank: Super Contributor
timestamp: December 18, 2016, 03:06:51 am
content: Quote from: jt on December 18, 2016, 01:54:48 amAll looks good from your description, you could expect 100mW or so power consumption for such a task.

author: jt
author_rank: Regular Contributor
timestamp: December 18, 2016, 05:26:26 am
content: QuoteThanks! These modules are a great design reference. Looks like the TS-4710 uses a Marvell PXA168 and shares its memory controller with Lattice XP2. Interestingly, the iMX6 computer on module (TS-7970) instead uses 4 UART busses for the processor-to-FPGA (MachXO2) link if I read the schematic correctly.QuoteThanks! Just to bound the estimate, do you have a sense of what the FPGA would consume while the UART busses are idle?

author: westfw
author_rank: Super Contributor
timestamp: December 18, 2016, 09:54:43 am
content: If you're willing to use a "RAM-like interface", there are a bunch of 4 and 8port uarts aimed at the PC market. TI and EXAR havexx16C554 (quad) uarts that are "industry standard" and have FIFOs. Also Similar parts with deeper FIFOs and more ports.NXP has quad and octal uarts (although I think their octal one is rather old and primitive, but is supposedly DMA-friendly.)Cirrus had some lovely 4 and 8port uarts with significant and USEFUL built-in intelligence, but the communications products got acquired by Basis semiconductor, and then by Intel, and i'm not sure what happened after that. (cl-cd2430 was one part number.)I'd second the option of using a microcontroller with lots of UARTs - 5 or 6 is pretty common, and you can add extra intelligence if you need it. OTOH, I'm pretty sure that there are open source and/or free FPGA "components" for some of the common uarts as well, so it might be reasonable to go that route. (FPGAs always seem like speed overkill for this sort of thing.)

author: Someone
author_rank: Super Contributor
timestamp: December 18, 2016, 10:13:32 am
content: Quote from: jt on December 18, 2016, 05:26:26 amNot much power at all, you'll want to get the vendors estimation tools for a more accurate answer but avoiding the PLLs you can get idle power down to 10's of mW. But only use a part that is just big enough, for low power applications the static currents can dominate. Also look at ALL the things you can integrate to the FPGA, some have ADCs and you should be able to absorb a lot of trivial/glue functions into it to cut out some other parts of the budgets.

author: jt
author_rank: Regular Contributor
timestamp: December 18, 2016, 09:29:51 pm
content: This is great stuff! Looks like there are a handful of options I hadn't considered.The MCU thought is interesting... i'll take a look to see if there is other functionality that would make sense to move over from the main processor.

author: rstofer
author_rank: Super Contributor
timestamp: December 18, 2016, 10:12:08 pm
content: Those octal port Exar chips look pretty nice. No muss, no fuss to connect to a uC. If 8 port aren't enough, maybe 16 will do it. The 100 pin package isn't my favorite but, given the number of ports, it pretty much needs the pins.The next problem is to mount the RS-232 drivers around the outside.Large FIFOs are nice, they help keep the throughput high.Or hang Ethernet to RS-232 on all the outboard devices and network the whole project...

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: December 18, 2016, 11:06:13 pm
content: Should be easy enough with a very small FPGA, or possibly CPLD depending on how much functionality you need. I be looking at Lattice ICE40 or XO2. It _might_ conceivably be doable on the 32 pin XO2Or maybe a second MCU doing bit-bashed UARTs - 10x1MBaud Tx would be doable, Rx less soI'd look to use SPI if possible to save pins on the MCU.