Modern SMPS learning materials - Page 1
Forum section: electronics / projects

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: April 15, 2022, 09:33:49 am
content: Hi,I'm interested in Designing SMPS based on new technologies like GaN, ZVS,PFC,LLC and MCU or FPGA based designs, I want to know if you know some websites or youtube channels or books that you would recommend.

author: jonpaul
author_rank: Super Contributor
timestamp: April 15, 2022, 09:59:30 am
content: bonjour bravo for the initiativeWe have worked in exactly these fields since,1970s.All of the acronyms mentioned are decades old and not new, topologies, devices, etc.Each one has a huge body of papers application notes and textbooks.It takes years of study to fully understand all of this.if you can précis your objective and intentions we can,assist you furtherBon courageJon

author: sclafa
author_rank: Newbie
timestamp: April 15, 2022, 10:29:51 am
content: You can audit these classes online for free.https://www.colorado.edu/ecee/academics/online-programs/ms-ee-coursera/curriculum/power-electronicshttps://www.colorado.edu/ecee/academics/online-programs/ms-ee-coursera/curriculum/embedded-systems

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: April 15, 2022, 12:51:50 pm
content: jonpaul thanks for the info, I know some of them are old, But the point is that I want to do it with a MCU or a FPGA, the control loop should be digital,Take this example as an example, a PC ATX power supply with LLC topology, I hope you could recommend good learning materialssclafa thanks for the links

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 15, 2022, 04:16:25 pm
content: FPGA should be straightforward, build the DSP equivalent of the analog circuit and you're set. Not many bits are needed, say 10 bits is enough for a lot of general control purposes; this affects the noise floor, which, should average out towards DC (behaving as a sigma-delta modulator, perhaps) and can be filtered for the noise mostly around Fsw and fractions thereof. Accumulators will need more bits of course, but also not too many as you likely won't have very long time constants. And waveforms can be generated with clock dividers in the usual way.Continuous-time waveforms (or fractional-clock timings) might not be so easy to do, though some chips offer them, like, some MCUs have fractional-clock timing. Not sure how they implement that. If nothing else, it's a rare case that you need very precise PWM or frequency control: the driven network will rarely have much Q at all, so the frequency hardly needs to be very tightly controlled. This may be different for say wireless power application, where the Q factor can be quite high, and the adjustable range quite narrow. But there too, since the time constant is so long, another approximation method will do just fine, i.e. dithering / DDS. Which can produce spurious tones at subharmonic frequencies, but again, the network is itself a filter so you hardly mind (but this can be quite important for radio purposes).Doing it with MCU, is entirely dependent on what peripherals they provide. A lot these days have event systems that can be routed internally, allowing complex logic with accurate timing even from simple e.g. PIC, AVR CPUs. And including current limit / fault trigger sorts of actions, directly in hardware. Not sure about the, say, ARM side of things, but probably triggered DMA serves as an even more advanced version, at minor expense to bus timing (since DMA might occasionally be delayed due to bus contention, but also, the bus is fast enough you might not care). Indeed, DMA has been demonstrated as Turing complete, on at least a PIC32 I think it was?So as for DSP stuff, if you don't know about it at all, you have some reading to do, but basically you take the differential equations of the analog system, change dees to deltas and get the difference equations, then set the time difference (sample rate) small enough that the deltas still behave like dees. It's not quite this simple for higher-order networks*, but you're likely not using many of those in a control loop, so that's easy.*A specific example: you want to reduce high-order filters to chains of 1-2 order filters, implemented usually with a "biquad" structure which is quite efficient in hardware or software, and is least sensitive to numerical stability issues. This mirrors the active analog case, where a high-order filter is built from chains of 2nd-order filters. In both cases, higher order per stage is possible, but the numeric stability / component tolerance gets very strict, very quickly as order goes up, so you don't gain much doing that.Like uh, for point of reference, I once wrote a biquad filter on AVR, taking 195 cycles per stage (plus 30 overhead), 16-bit data size, 16 bit accumulators, signed fixed point arithmetic. At F_CPU = 32MHz, that's enough to run 6 or 7 filters cascaded on 22kHz mono audio, for example. Not bad for a piddy 8-bitter. An ARM will do that in a small fraction, and a DSP even tinier still; FPGA of course can churn out results synchronously, depending on how much hardware you want to commit / share / if pipelining is needed.Tim

author: TimNJ
author_rank: Super Contributor
timestamp: April 15, 2022, 05:22:41 pm
content: Quote from: sclafa on April 15, 2022, 10:29:51 amRelated to the Colorado course, there is a new version of the Fundamental of Power Electronics book:https://link.springer.com/book/10.1007/978-3-030-43881-4I do not own it (just own the 2nd edition), but supposedly there is increased focus on digital control, algorithms, etc. That said, probably it all comes naturally once you understand the analog circuits you are trying to implement and if you have a good handle on DSP.It's a goal of mine to implement digital switch-mode control from scratch (too). Honestly, I don't think there is too much practical value in DIYing the control part since mass market switching controllers are so cheap anyway. Probably only makes sense if you are trying to implement something really novel or super specialized (in my opinion). But, it would really make me feel like a "full stack" power electronics engineer.Had a thought that I would try Cypress (Infineon) PSoC if I were to try it. Built in analog peripherals sounds handy, not sure how necessary really.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: April 16, 2022, 07:01:37 am
content: Tim thanks for the tips, Fortunately I have good understanding of DSP and have done several projects in ARM and FPGA, doing things like, Calculating RMS, FFT, FIR filters, Cordic etc... But I consider myself a novice in the SMPS field, only doing flybacks (in the range of 20W) with the help of PI expert from power integrations and using Buck or boost parts from various manufacturers like TI, analog etc.. So what do you recommend for learning.

author: jonpaul
author_rank: Super Contributor
timestamp: April 16, 2022, 08:25:37 am
content: Rebonjour à tousThe topics of "MPU/ digital control" of a SMPS is complicated by one's definition and goal.direct operation of switch transistor driver?DAC voltage or current to change servo inputs?Instaneous protection or current limit?Note that an FET can be destroyed by a misformed driver on the gate submicroseconds.All dedicated SMPS driver IC and bridge drivers include Instaneous current sense and turn off or limits.Viewing your digital control system design, discussion of sample rate, MPU speed, and software or firmware can it detect a fault and assert protection, and act in 200 nS?This most interesting issue seems to be overlooked by the certain remarks of this thread.A complete système block diagram would aid compréhension.Bon courage et bon Fêtes des Plaques !Jon

author: Shock
author_rank: Super Contributor
timestamp: April 16, 2022, 08:39:44 am
content: Thanks, just picked up the Fundamentals of Power Electronics 3rd Edition, didn't know about the newer version.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: April 16, 2022, 08:52:46 am
content: Jon thanks for the Tips, the Instantons current sense and turn off or limits can be done on FPGA easily, also Some ARM device with dedicated hardware like comparator, timer and ADC and DAC have internal logic to just do that.