Valve control circuit - switch with safety cut off - Page 1
Forum section: electronics / beginners

author: Matrix828
author_rank: Contributor
timestamp: August 24, 2025, 08:39:34 pm
content: Hello all.My basic project is seemingly far too advanced for me. I could do it in a few minutes with a microcontroller (one will be present in the enclosure!) but that is not the purpose of the exercise. I have so many electronic components that I never use because I can do it in software. But I digress.I am trying to build a control circuit for a hydroponic setup. It should fulfil the following criteria, which the wording is influenced by what I have done so far, but open to changes:- When the float switch is ON - SW_1 is now HIGH- Start a countdown timer and set output Q_1 to HIGH- If both SW_1 and Q_1 are HIGH, then set CH_1 to HIGH- If the timer expires while the switch is on, the CH_1 should go LOWNow this brings me on to my schematic and the problems I encountered and attempted to fix.- I set a NE555 in monostable mode to produce the timed output from the switch signal- I added a PNP over the timer cap so it can be reset by...- I AC coupled the switch to produce a single short pulse, to drain the cap and retrigger the 555 (it's not perfect, but adds about ~80% of the original time back, when it works...)- I added an NPN inverter (Q4) to bring the CH_1 output LOW, which is what the relay module board requires as a control signal- I use an NPN tower to provide an AND gateAnd the problem(s) I have now is:- I realised the SW_1 is active HIGH, so I've tried to invert this, but this causes the 555 to never trigger (research suggests this is because it biases it wrong and then the 555 can't see the swings it needs, but I am probably wrong here)- If I hold the switch down, the 555 never expiresWhat I have tried:- An optocoupler to isolate the SW_1 before it goes into the inverter, but again this causes biases (?) and breaks the timer- A PNP into the AND gate, but then this never works (perhaps wired wrong?)- I added the AC coupler due to my understanding of these postshttps://www.eevblog.com/forum/projects/pulse-generate-on-toggle-switch-state-change/https://www.eevblog.com/forum/beginners/is-there-a-way-to-prevent-re-trigger-on-one-shot-(555)/- but I can't lie, these tabs have been open a few days and I am a little frazzled- A lot of googling, but I lack the terminology and understanding to really see how they differ for my application, or it uses chips I do not have.I'm really out of my depth here, any advice would be appreciated.If it's at all possible, I'd really like to do it with the limited hardware I have available - hence the lack of 74 series AND gate chips and the use of lots of NPN BJTs!Also forgive my Kicad, it's not my forte, so I am happy to rejig it around if it isn't readable!Ninja Edit:This threads on another site provided what I need to retrigger:https://forum.allaboutcircuits.com/threads/how-to-make-a-555-retriggerable.159605/

author: Analog Kid
author_rank: Super Contributor
timestamp: August 24, 2025, 09:55:16 pm
content: Sorry I can't help you.Nice schematic, though. Glad you didn't go the "everything in its own little box" route!

author: xvr
author_rank: Frequent Contributor
timestamp: August 25, 2025, 11:39:37 am
content: Q3 works as a diode. When the button is pressed, it discharges capacitor C1 through junction BE. At the same time, junction BC Q3 is shorted by the same button.The discharge current is not limited in any way, so Q3 will break down sooner or later.Your circuit is all logic, so why not use logic chips instead of simple transistors? The primitive 74HC series contains everything you need.

author: PGPG
author_rank: Frequent Contributor
timestamp: August 25, 2025, 01:16:07 pm
content: I have only looked at schematic.It looks that Q1 and Q2 are intended to do logical AND, but Q1 with its collector disconnected will work as diode and you can get enough current in R7 to switch Q4 on. U1 output alone will decide of Q4 state.

author: Matrix828
author_rank: Contributor
timestamp: August 26, 2025, 09:02:22 am
content: Thank you for all the input so far.Quote from: xvr on August 25, 2025, 11:39:37 amThis sounds like a reasonable explanation as to why the holding of the button causes the 555 to never expire, as the cap is always kept discharged. The behaviour is for the retriggering of the 555 on repress. What do you suggest to resolve this? I could move the Q3 base to the 555 trigger pin, so it should just be a pulse - this resolves the problem of pressing and holding. How do I calculate a good/correct value for a current limiting resistor for Q3?Quote from: xvr on August 25, 2025, 11:39:37 amAbsolutely the case. However, I have many transistors, and regretfully little need for more components without projects to use them. The challenge and learning is part of this project.Quote from: PGPG on August 25, 2025, 01:16:07 pmThat is the intended behaviour of Q1 and Q2. I understand how that is deciding the state of the circuit, but do you know of a way to provide the correct behaviour with transistors alone?

author: PGPG
author_rank: Frequent Contributor
timestamp: August 26, 2025, 11:11:00 am
content: Quote from: Matrix828 on August 26, 2025, 09:02:22 amIf driving base resistor will be much higher then resistors driven by transistor then in case transistor working as diode you will get resistor divider constructed for example from 100k+10k and not 10k+10k.The simplest logic function to make with transistors is to connect OC (Open Collectors) together to get AND (at wire). To use it you have to have signals in correct phase (or need to use next transistor to invert them).There is no big idea in making logic functions from discrete transistors (except OC AND) while you have a full set of digital ICs.

author: Matrix828
author_rank: Contributor
timestamp: August 26, 2025, 12:53:33 pm
content: Quote from: PGPG on August 26, 2025, 11:11:00 amI'm afraid you have lost me here a little bit. However, if should I change the stack to what you specify below it may not matter much:Quote from: PGPG on August 26, 2025, 11:11:00 amWhich I believe, if I understand right, is what the schematic below represents. However, the switch is LOW when active, and thus needs an inverter before it goes into the "new" NPN gate. When I add this, it still does not work as now the inverted output is ~3v instead of 0.Thank you again for the support and forgive my misunderstandings!

author: Matrix828
author_rank: Contributor
timestamp: August 26, 2025, 01:35:32 pm
content: Pardon the double post.I didn't really give your "open collector" comment the attention I should've, so went away and actually researched it. I implemented it wrong, and thus there was no point in providing the schematic for that (which I also forgot).This should be the correct "open collector" approach now (attached). I removed the last inverter as this approach brings the CH_1 output LOW when my outputs are active, which is exactly what I need.However, it appears to be the opposite of what I need (almost). When powered, the CH_1 is LOW and my relay active. When i press the switch, it goes HIGH, and the 555 does not trigger. Presumably, this is due to the ~3v ish at SW_1, because I suppose there is a voltage divider there.Behaviour seems to be unpredictable.EDIT: actually attached now...

author: PGPG
author_rank: Frequent Contributor
timestamp: August 26, 2025, 05:49:23 pm
content: Quote from: Matrix828 on August 26, 2025, 12:53:33 pmCosider only R4,Q1,R5 from your first schematic.If Q1 collector is connected to VCC (5V) you have:- emitter current about 0.5mA (5V/10k)- base current about 1/100 of it (5uA)- R4 voltage drop about 1/100 of R5 voltage drop so about 50mV- assuming B-E voltage of 0.7V you have 4.25V at emitter.If Q1 collector is floating you have at output about (5-0.7)/2 = 2.15V.Your intention is to have in this state 0V but you have 2.15 what is enough to switch Q4 on.If R4=100k you will have:- with Q1 collector connected to VCC the voltage at emitter about 3.8V (voltage drop at R4 will be 500mV),- with Q1 collector floating you will have (5-0.7)*10/(100+10) = 0.39V what is not enough to switch Q4 on.Quote from: Matrix828 on August 26, 2025, 01:35:32 pmLooking at it from some distance.As I understand:- for SW_1 = 1 you want at output 0,- for Q_1 = 1 you want at output 0.So from each of them to the output you need odd number of inverters. Your circuit doesn't meet this needs.You also want to AND them.To do it by connecting transistor collectors you need:- two negations (two transistors) from SW_1,- the same from Q_1,- now last transistors in each path can have collectors connected together,- you need extra one output transistor (like your Q4) to get 3 negations in each path.You need 5 npn transistors for that.You can use pnp transistor for first stages and connect their collectors and then 2 x npn to get 3 negations in each channel. This solution uses 4 transistors.You can also replace 2 negators at each of your sorce signals with one diode to get AND function with diode-logic. But 0 after diode is not 0 but something about 0.7V+your source signals output voltage in 0 state. You have to do something with it as it is higher than voltage needed to switch your output transistor (you have to divide it with resistors, or shift with third diode).You can replace all of them with single NAND gate.But it is until the gate output is enough strong for your output. If not you can use AND gate + one npn.Digital ICs are manufactured in single gate (1G serie) where you have one gate in one IC. AND or NAND gate will be SOT23 package with 5 pads. It will take much less space on your PCB than all these transistors + resistors.

author: Matrix828
author_rank: Contributor
timestamp: August 27, 2025, 03:39:18 pm
content: Quote from: PGPG on August 26, 2025, 05:49:23 pmChanging R4 to 100k does resolve this issue of the 555 output being able to turn on Q4 on its own - and I understand your explanation, thank you.With this, it also seems that the apparent behaviour is almost correct - pressing and holding the switch still allows the timer to expire - perhaps there was also a wiring issue I had missed, since I had to remake the circuit from the original schematic.Quote from: PGPG on August 26, 2025, 05:49:23 pmI had made a mistake in one of my explanations. As SW_1 is active low, the case is:- for SW_1 = 0 I want at output 0,- for Q_1 = 1 I want at output 0.I tried swapping out Q2 with a PNP BC557, as I believed this would provide me with a simple inversion of the control signal in my transistor tower, however this is not the case. My naivety is apparent again.I tried this also in isolation with just the PNP and some resistors and observe the similar behaviour that you described initially. I change the base resistor from 10k to 100k, and observe the voltage at the emitter increase. Lowering the resistor to 1k lowers the emitter voltage. I don't know the name of this behaviour, so forgive me for explaining something you already understand, it's just so I can get it in my head.I add R3 at 1k to account for this, and believe it or not, it bleeding works as expected.Quote from: PGPG on August 26, 2025, 05:49:23 pmYes, but again, where is the fun in thatit will always remain a protoboard PCB, and I have transistors and resistors aplenty!I really appreciate the help you have given me so far. If you could just review the schematic and make sure there's nothing glaringly wrong as to what I have so far. I know that Q3 needs a current limiting resistor, and I have plenty of 220R, so I would just use that (R8).

author: PGPG
author_rank: Frequent Contributor
timestamp: August 27, 2025, 07:29:06 pm
content: Quote from: Matrix828 on August 27, 2025, 03:39:18 pmI don't want to think how 555 is working in your circuit.I have never done it but look around to learn to use SPICE to simulate your 555 circuit (when I was using 555 for the first time PCs were not at homes yet so no SPICE available).Good choice would be LT-Spice or Spice available in KiCad, I think.Just having available SPICE will be helpful for you to see what is going on in circuit.Until you not do something special all arrows in transistors at schematic should point down (Q2 pnp is not doing it).What is going on with Q3 will be much clear if its base would be to the left. Signals should go from left to right and in Q3 signal goes from base to emitter.

author: Matrix828
author_rank: Contributor
timestamp: August 27, 2025, 08:55:01 pm
content: Sorry, it was not my intention to imply an in depth review, just a cursory glance is enoughI will look into spice tools in Kicad, and that Q3 oddness was meant for a nicer schematic but I can see how that has made it worsethanks for all the help.

author: PGPG
author_rank: Frequent Contributor
timestamp: August 27, 2025, 11:56:23 pm
content: Quote from: Matrix828 on August 27, 2025, 08:55:01 pmYou need not to sorry..Whenever you design anything you should be sure how you want it to work. If then something doesn't work as expected then you have to find why.The more such your own mistakes you find (yourself !!) and correct the more you learn. If someone finds them for you them you learn very little.

author: mikerj
author_rank: Super Contributor
timestamp: August 30, 2025, 09:22:24 pm
content: To create a working AND gate, Q1 and Q2 should be reconfigured as common emitter switches rather than emitter followers. Since the output signal will then be inverted, you will either need an extra stage to invert this if you want to keep Q4 as NPN transistor, or you may be able to change Q4 to a PNP:

author: Matrix828
author_rank: Contributor
timestamp: September 01, 2025, 09:09:28 pm
content: Quote from: mikerj on August 30, 2025, 09:22:24 pmThat cannot possibly work with the switch being active low, unless I am misunderstanding the circuit. How is your diagram not emitter followers regarding Q1 and Q2? They appear to be the same configuration as my AND gate.

author: PGPG
author_rank: Frequent Contributor
timestamp: September 02, 2025, 11:49:58 am
content: Quote from: Matrix828 on September 01, 2025, 09:09:28 pmHave you noticed "To create a working AND gate"?It is just AND gate. Only when both inputs are high ('1') than you get high ('1') at output. In this circuit the resistor from Q3 collector to GND is lacking.Quote from: Matrix828 on September 01, 2025, 09:09:28 pmNo, because here output is from collector and not from emiter.From base to emiter transistor multiplies voltage by 0.99.From base to collector transistor multiplies voltage by 100 and more.

author: Matrix828
author_rank: Contributor
timestamp: September 02, 2025, 12:26:51 pm
content: Yes of course. I am meaning that it would not work with my configuration RE active low.I think that it would also have problems for the relay module. I have reconfigured the voltage level for the main circuit to 3.3v to support reading the voltage levels from the microcontroller. This causes the relay module to not turn off at the ~3.3v high level (research says the opto + led has too high voltage drop combination).I reconfigured like the below image. The relay module input (CH_1) is around 3.5V. I do not have a schematic for this module, but can find more information if it is relevant.(this also includes a renumber I believe, and the Q1 flipping)This schematic does appear to be functioning as intended.I believe I understand that I could do the following to be "common emitter", which would then require another PNP. My stock of those is limited, so I am happy with the current approach as is functional.Sorry if I am misunderstanding something fundamental here.

author: PGPG
author_rank: Frequent Contributor
timestamp: September 02, 2025, 04:43:34 pm
content: Quote from: Matrix828 on September 02, 2025, 12:26:51 pmYou have to distinguish logic functions from input/output functions. Not all posts are written having your full application in mind.This AND gate is the example of logic function. You can use such gates (adding the negation) to build whole (micro)controller.Why 'adding the negation'? Because it is proved that using only NAND gates you can construct circuit realizing any logic function of any number of input signals.As in logic circuits one gate output can be used to drive many other gate inputs the gate have to not only realize the logic, but also have enough 'strong' output to drive several inputs.Here is the main difference between this AND gate and your circuit. This gate having 10k at inputs can realize the AND function and drive 1k at output.In your circuit if you will have 10k at inputs and 1k at output you will not get AND. But it is special case so manipulating with resistors you can probably reach what you want.Normally (for more complicated logic (like uC)) you separately think of converting input signals to your logic level, then of realizing logic and then of making needed output drivers.I have said that all transistor arrows should point down, but in your last schematic...1. You still have Q2 with arrow pointing up.2. Q1 has base at left (as I suggested) but with arrow pointing up it is not easier readable than before (you should not rotate it but mirror).

author: 5U4GB
author_rank: Super Contributor
timestamp: September 03, 2025, 09:44:48 am
content: Coming at this from a slightly different angle, it looks like you're trying to emulate a PLC using discrete electronics. What about just using a PLC, either a cheapie second-hand unit off eBay or whatever or a new one from Aliexpress, e.g. the web-programmable KC868?

author: Matrix828
author_rank: Contributor
timestamp: September 03, 2025, 01:34:23 pm
content: Quote from: PGPG on September 02, 2025, 04:43:34 pm1. That appears to be the default symbol orientation in Kicad. If I mirror then my paths have to go in a messy way like Q1 did.2. I've mirrored this, and it's definitely better - thanks!!I'll review some schematics that include PNPs in kicad to see the best way of doing it, as I think this will help me too.Quote from: 5U4GB on September 03, 2025, 09:44:48 amAnd I could do it in minutes with the attached micro, the challenge and learning is in doing it with discrete components

author: ledtester
author_rank: Super Contributor
timestamp: September 03, 2025, 01:46:46 pm
content: Quote from: Matrix828 on August 24, 2025, 08:39:34 pmMy interpretation of this is that when the float switch is "ON" it connects +5 (or whatever your supply voltage is) to some point in your circuit which we'll call SW_1. And when the float switch is off that point is no longer connected to +5.So here's an idea which seems to work in simulation...(link to Falstad simulation)The ideas are...- when SW1 is closed it pulls the 555 out of reset and then sends a quick pulse to the trigger pin which starts the monostable- the output of the 555 is AND-ed with SW1 using a DTL AND gate to produce the output CH1- Q1, diode D1 and the 10k is meant to convert SW1 into something that can source current when it is closed and sink current when the switch is openThere's probably a better way to do what Q1 and and D1 are doing - all I can say is that it seems to work in Falstad.If you press SW1 you'll get a pulse on CH1 for the duration determined by RT and CT.If you toggle SW1 off during the pulse the pulse will be cut short.Hopefully this is how you wanted it to operate.I'd be interested to know if there is a better way to do what I'm trying to do with Q1 and D1. Btw - if the float switch has both NO and NC terminals perhaps the Q1/D1 business isn't needed.

author: calzap
author_rank: Frequent Contributor
timestamp: September 03, 2025, 02:34:29 pm
content: Perhaps you could state a bit more about the ultimate application. It appears that it’s to control water level in a hydroponics tank by using a float switch and valve. Is the timer the safety or do you want the valve to stay open for some minimum time? Is the controller a custom application or a design for a product for mass production? What sort of environment (electrical and otherwise) will the controller be in? Reinventing the wheel can be educational and maybe that’s the goal. However, there are robust adjustable timer relays available. One of these and an additional regular (could be solid state) relay might be all that’s needed.Mike

author: PGPG
author_rank: Frequent Contributor
timestamp: September 03, 2025, 06:58:25 pm
content: Quote from: Matrix828 on September 03, 2025, 01:34:23 pmI am trying to tell you how you can notice that your schematic is wrong here (arrow directions is the simplest indicator of it).Npn transistors are used with collector at higher voltage then emitter, and pnp transistors are used with collector at lower voltage than emitter. You connected pnp collector to highest voltage in your circuit so however everything will work it will not be lower than emitter.But you don't get it and assumes that if Q2 will be rotated it have to be connected like it is.

author: Matrix828
author_rank: Contributor
timestamp: September 03, 2025, 08:35:58 pm
content: Quote from: calzap on September 03, 2025, 02:34:29 pmSure! The timer is a safety to prevent overfilling, pretty much only in a "worst case" scenario like a leak, or if it literally it falls over. Normally, the switch would click on, it'll top up slowly for a few seconds, then off. It is going to be a one-off, for my own personal use, on "double sided protoboard PCB" (I am sure there is a proper name for this but I don't know it. Not the temporary breadboard but soldered, if you get me) . The environment will be inside a greenhouse (and not in ahot climate, I am not concerned about temps) and inside a waterproof enclosure. Education is the primary goal of the exercise, though I do still appreciate learning about the preexisting solutions like that!Quote from: PGPG on September 03, 2025, 06:58:25 pmYes, apologies, I did not get it at all. I will try it out, and adjust my schematic. Hopefully it will be more accurate next time.