Altera MAX 10 external memory? - Page 1
Forum section: electronics / general

author: deephaven
author_rank: Frequent Contributor
timestamp: December 27, 2014, 04:12:24 pm
content: I was contemplating using a MAX 10 but I need some external DDR memory for it. Looking at the literature, Altera recommends using their "UniPHY IP core" and just wanted to know how much this costs? I can't seem to find costings on their website, but maybe I didn't look hard enough.Otherwise, are there any DDR memory interface examples around?

author: Marco
author_rank: Super Contributor
timestamp: December 27, 2014, 09:15:06 pm
content: No idea what their core costs but Xilinx has anappnote on using DDR with their CPLD(pretty basic, should be mostly portable) and Ray Bittner from Microsoft has anopen source DDR2 controller.

author: deephaven
author_rank: Frequent Contributor
timestamp: December 28, 2014, 04:16:23 pm
content: Quote from: Marco on December 27, 2014, 09:15:06 pmMarco, thanks for the useful links.

author: Scrts
author_rank: Frequent Contributor
timestamp: January 01, 2015, 07:58:05 pm
content: Quote from: deephaven on December 27, 2014, 04:12:24 pmMemory controllers from Altera are free of charge. Check the UniPHY core documentation of MAX10 family for supported memory devices.

author: deephaven
author_rank: Frequent Contributor
timestamp: January 01, 2015, 08:08:23 pm
content: Quote from: Scrts on January 01, 2015, 07:58:05 pmI had a bit more of a look around Altera since my posting. I believe the UniPHY core core is free if I have a subscription edition of Quartus. I don't have a subscription right now, but I can still try it but it has to be connected to the programming adapter or there is a time limit on the run time. This should be fine as the subscription isn't too bad if I do decide to go with it after trying it out.

author: miguelvp
author_rank: Super Contributor
timestamp: January 02, 2015, 03:58:02 am
content: Check the BeScope codehttp://www.arrownac.com/solutions/bescope/Under Getting Started on the "Download Software (BeScope only)" linkThe software is missing some important files that can be found here:http://forums.parallax.com/showthread.php/157115-BeScopeBundle-System-FilesBut that's only if you want to use it but for the memory access it's there.Granted this is fro the BeMicro CV but they list the BeScope for their BeMicro Max 10http://www.arrow.com/bemicro/I have both but only than just compiling and testing the BeMicro CV with the BeScope (I got the bundle for $50 but they no longer have that bundle) I didn't analyze the code in detail yet, but it seems they access the memory directly without a NIOS II soft core so it's straight via the avalon interfaceMore info about the BeMicro Max 10 here including schematics:http://www.alterawiki.com/wiki/BeMicro_MAX_10If I find time to play with using the BeScope using the Max10 instead of the CycloneV I'll post it in here but might not be for quite a while.Edit: upon closer inspection it has SDRAM not DDR at all, sorry but I'll leave the links in case SDRAM fits your needs.

author: deephaven
author_rank: Frequent Contributor
timestamp: January 02, 2015, 09:33:19 am
content: Quote from: miguelvp on January 02, 2015, 03:58:02 amThanks for all the useful links. My existing design uses a Cyclone 2 with a 9 Mbit SDRAM. I rolled my own RAM controller for that one. I now need 32 Mbits and, although you can get SDRAM in that size, it is prohibitively expensive. In comparison, DDR RAM is peanuts, but it needs more brains to make it work. I also notice that Altera are only listing their 8K LE MAX 10 devices in their shop, so it might not be big enough for me, I need around 30K. This means I might have to go for a Cyclone 4 or 5 instead.

author: mirecta
author_rank: Newbie
timestamp: October 11, 2016, 08:23:26 pm
content: Quote from: miguelvp on January 02, 2015, 03:58:02 amhi i have a question is here any progress with Bescope and BeMicroMax10 ? thanx for answer

author: kilohercas
author_rank: Regular Contributor
timestamp: February 09, 2017, 02:26:12 pm
content: This is related question:If i want to connect 32b SDRAM ( not some DDR, but 3.3V CMOS level 32MB) can i do it, or i must use DQ pins for data ?Because 484pin MAX10 50k only has 24b of DQ lines, but this is low speed device, it should connect to any pin expect for Vref pin of that bank, 100MHz is nothing for this altera... Even STM32F429 can connect to this memory, with no problems.

author: Ice-Tea
author_rank: Super Contributor
timestamp: February 09, 2017, 03:24:46 pm
content: You can connect SDRAM to pretty much every pin, AFAIK. You may want to check for dedicated clock pins, though.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: February 09, 2017, 04:29:45 pm
content: You can connect SDRAM anywhere if the speed is low enough (say 50-100 MHz), for high speeds you may need to start paying attention to using dedicated clock pins.I've used hamster's SDRAM controller in the past with good success. It took a little bit of tweaking to get it running correctly for me, but not a lot.http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller

author: John_ITIC
author_rank: Frequent Contributor
timestamp: February 10, 2017, 03:35:34 am
content: Quote from: Scrts on January 01, 2015, 07:58:05 pmI believe only if you are using the subscription version of Quartus II (or whatever they call it these days)? Some $2,000 USD I believe (yearly)?

author: amb
author_rank: Newbie
timestamp: February 11, 2017, 11:28:29 am
content: @deephaven I've designed DDR2 and DDR3 interfaces with the Cyclone V, you should have a fairly easy ride if you go that way.@kilohercas talking to SDRAM should be easy, but pay attention to clock timing; you may need to run different length traces from your clock source to the FPGA and the SDRAM to meet setup and hold, or (if it's possible) play with the FPGA clock phase internally to achieve the same result (this might include generating the SDRAM clock internally). Also: remember to analyse Simultaneous Switching Noise (SSN) - see Altera's "MAX 10 FPGA Signal Integrity Design Guidelines". Filling up a bank with data I/Os has caused me problems with this, one time I had to disperse them so that no bank had more than 50% output pins. Given the relatively low speed of SDRAM, another option might be to stagger the switching timing of your data I/Os by a few hundreds of ps or a few ns. A bit fiddly but may save the day if you're short of pins.

author: Scrts
author_rank: Frequent Contributor
timestamp: February 11, 2017, 07:33:06 pm
content: I've used 5 SDRAM devices with 5 separate memory controllers on EP3C55. One SDRAM for Nios II/f and another four for 7 compressed video data streams over custom made DMA.MAX10 is faster generation than Cyclone III, so you can use every IO to interface SDRAM even at 100MHz.However, pay very careful attention to SDRAM examples from, for example, old development kits. You will see that the PLL setup has two output clocks: one for SDRAM controller internally and another for SDRAM device itself. It will have about -3ns clock phase.I gave you a hint and you can try to understand whyIn general, you should also use some primitives for clock output and understand how to write constraints file initially, then follow TimeQuest report.

author: ale500
author_rank: Frequent Contributor
timestamp: February 12, 2017, 07:23:45 am
content: @Scrts:regarding your recommendation of a phase shift of -3 ns for the sdram clock, I was wondering if one could achieve the same results using the falling edge to output address and commands to the SDRAM and the rising edge, default on SDRAMs, for it to acquire and output data.Let me ask you a related question:Or is such a scheme to be avoided due to "don't mix", only use rising edge even in different domains ?.Or is the answer you have 7 ns to process and output the data instead of 5 ns ?

author: Scrts
author_rank: Frequent Contributor
timestamp: February 12, 2017, 03:23:10 pm
content: Quote from: ale500 on February 12, 2017, 07:23:45 amIt depends on clock frequency you use. This is why the difference set in PLL is in nanoseconds.

author: ale500
author_rank: Frequent Contributor
timestamp: February 14, 2017, 06:37:30 am
content: The Max10 SDRAM example that comes with the TerAsic board DE10 Lite uses a 100 MHz clock and a phase delay of -3 ns. The NIOS example does the same.