Quartus 21.1 Free Edition - Confused about free to use IP - Page 1
Forum section: electronics / general

author: voltsandjolts
author_rank: Unknown
timestamp: November 16, 2021, 03:00:29 pm
content: I use FPGAs (smallest Cyclone IV + VHDL) for fairly basic peripheral expansion type stuff, never used any of the more complicated IP.I have a (non-commercial) project which uses a DDR2 and I tried getting into that but its a big step up from sdram.Just the signal timing alignment alone makes my head spin, as does looking atBrian's DDR3 controller, which is an amazing piece of work.So, I thought I might try the ALTMEMPHY + DDR2 Controller included in Quartus Free 21.1.But I'm not sure if this is a time limited demo version and I struggle to find information on the Intel site (I really wish they just left the Altera site seperate from the Intel site, marketing twats). TheIP Base Suiteincludes a DDR2 controller which uses UniPHY. So that makes me suspect the DDR2 controller available to me is not free to use. But on the other hand, it doesn't mention ALTMEMPHY. So, I thought I could perhaps use ALTMEMPHY and create my own controller on top of that. But the MegaWizard for ALTMEMPHY pops up a loading message then just closes after a few seconds with no other message given. So I guess it's tied to the DDR controller and can't be used independently?If anyone can clear this up for me or point to to a matrix of what IP is included in the Free Edition, that would be great.

author: BrianHG
author_rank: Super Contributor
timestamp: November 16, 2021, 03:29:33 pm
content: I believe that the ALTMEMPHY is free. Note that some of those megawizards need WSL version 1 linux distro to work, or, they are just buggy and crash without warning.See thread here:https://www.eevblog.com/forum/fpga/intelaltera-ddr3-megafunction-fails-in-quartus-20-1-1/msg3602235/#msg3602235For the megafunctions which require a license, you end up with the message at the end of compiling/fitting, not during 'ADD' ip into your project. I really hate this about Altera/Intel only to find out it is done the same way with Lattice Diamond as well.For me, I have a few versions of Quartus installed and sometimes have to run a test project and insert such megafunctions in Quartus 13/14/15, then use the generated HDL as an example. Otherwise, everything else I end up doing is 100% manual by the data-sheet's functions parameters.

author: BrianHG
author_rank: Super Contributor
timestamp: November 17, 2021, 03:57:24 am
content: My file :https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/main/BrianHG_DDR3/BrianHG_DDR3_IO_PORT_ALTERA.svIs my home-made version of Altera's ALTMEMPHY with a parameter to select whether to use Cyclone or MAX10 DDRIO buffers.The main difference between DDR2 & DDR3 is that DDR2 costs more ($4.50 for 256mbit 400mhz VS $4.05 for 512mbit 800mhz), only has 4 banks instead of 8 banks, and different MRS configuration + 200MHz low frequency instead of 303MHz low frequency, though, my controller has successfully run DDR3 at 250MHz on the DECA board.1GB DDR3 costs even less at $3.57 at digikey... pn EM6GC08EWUG-10IH, but its 8bit, not 16bit.

author: voltsandjolts
author_rank: Unknown
timestamp: November 17, 2021, 02:42:30 pm
content: Quote from: BrianHG on November 16, 2021, 03:29:33 pmI prefer not to install WSL, so instead I tried instantiating ALTMEMPHY on my linux box, but that failed too:Code:Error (14736): Error: Could not find the requested wizard, altmemphy, in the search path.Ahha, I've just foundthisIntel forum post. So it looks like ALTMEMPHY wizard is not included in newer installs. Need to install Quartus 14 to get it. But the quote "ALTMEMPHY-based memory controllers were removed from the IP Base Suite" makes me think ALTMEMPHY is perhaps not free to use...we'll see.Thanks for pointing me to your "home-made" ALTMEMPHY, I'll try to get my head around that. Agreed, DDR3 is better but I'm trying to produce an open bitstream for an existing device which uses DDR2. The LA device is currently supported insigrokwhen using the oem bitstream and I'd like to see a fully open solution for it. The DDR2 interface is the key, everything else in the FPGA is fairly straightforward. Data is captured at a fast rate using the DDR memory as a big circular buffer, then, when writing is complete, the data is exported to a PC via USB High Speed. On the plus side, that means the controller itself should be one of the simpler DDR controllers; only need to write and read 8-word bursts, linearly through memory, and read/write occurs at different times. What could possibly go wrong!