Quartus II Clocks - Page 1
Forum section: electronics / general

author: pigtwo
author_rank: Regular Contributor
timestamp: May 18, 2014, 09:01:12 pm
content: Hey guys, I'm working on a simple project using the DE0-nano and Quartus II and I'm very confused about how the clocks work or how to set them up.This started because I was working on something(I'll post the code below) and it would run correctly for about .1 second and then all the outputs would just either hold their value or go to zero. I couldn't find any reason for this and the time that it would run was seemingly random(IE some times it would be .2 seconds other times is would be .09 seconds or somewhere in between). So this made me think that it wasn't the program getting stuck somewhere.I then looked at the warnings and I saw a lot of them in reference to clocks but I didn't really understand what they meant. Unfortunately I'm very confused so my question is kind vague. So if someone could give me and idea of what I'm doing wrong or a place where I could learn about this more thoroughly that would be great.So I don't really understand how the clocks work in this. When I started I thought you didn't really have to put much thought into the clock and I found a megafunction called altclkcntr which seemed to make a global clock. So I thought this was great.Here are the warnings I'm getting.Code:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for detailsWarning (332087): The master clock for this clock assignment could not be derived. Clock: clock1|pll1|altpll_component|auto_generated|pll1|clk was not created.Warning (332035): No clocks found on or feeding the specified source node: clock1|pll1|altpll_component|auto_generated|pll1|inclkWarning (332060): Node: in_clock was determined to be a clock but was found without an associated clock assignment.Warning (332056): PLL cross checking found inconsistent PLL clock settings:Warning (332056): Node: clock1|pll1|altpll_component|auto_generated|pll1|clk was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000Warning (332061): Virtual clock in_clock is never referenced in any input or output delay assignment.Warning (20028): Parallel compilation is not licensed and has been disabledWarning (332087): The master clock for this clock assignment could not be derived. Clock: clock1|pll1|altpll_component|auto_generated|pll1|clk was not created.Warning (332035): No clocks found on or feeding the specified source node: clock1|pll1|altpll_component|auto_generated|pll1|inclkWarning (332060): Node: in_clock was determined to be a clock but was found without an associated clock assignment.Warning (332056): PLL cross checking found inconsistent PLL clock settings:Warning (332056): Node: clock1|pll1|altpll_component|auto_generated|pll1|clk was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000Warning (332061): Virtual clock in_clock is never referenced in any input or output delay assignment.Warning (332087): The master clock for this clock assignment could not be derived. Clock: clock1|pll1|altpll_component|auto_generated|pll1|clk was not created.Warning (332035): No clocks found on or feeding the specified source node: clock1|pll1|altpll_component|auto_generated|pll1|inclkWarning (332060): Node: in_clock was determined to be a clock but was found without an associated clock assignment.Warning (332056): PLL cross checking found inconsistent PLL clock settings:Warning (332056): Node: clock1|pll1|altpll_component|auto_generated|pll1|clk was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000Warning (332061): Virtual clock in_clock is never referenced in any input or output delay assignment.Warning (332087): The master clock for this clock assignment could not be derived. Clock: clock1|pll1|altpll_component|auto_generated|pll1|clk was not created.Warning (332035): No clocks found on or feeding the specified source node: clock1|pll1|altpll_component|auto_generated|pll1|inclkWarning (332060): Node: in_clock was determined to be a clock but was found without an associated clock assignment.Warning (332056): PLL cross checking found inconsistent PLL clock settings:Warning (332056): Node: clock1|pll1|altpll_component|auto_generated|pll1|clk was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000Warning (332061): Virtual clock in_clock is never referenced in any input or output delay assignment.The main module, although I doubt that this one is very important. The only thing that would probably matter is the part in the beginning where I connect the clock.Code:module LED_Matrix_Solid_Color(input wire in_clock, reset,output wire clk_out, latch_out, OE_out,output wire[5:0] color_out, // Color will hold all the color data in the form [r1,r2,g1,g2,b1,b2] where x1 is the top row and x2 is the bottom row.output wire[2:0] row_out // This specifies the row but two are choosen at once. so 1-8, 2-9, 3-10, ect);wire clock;clock_mod clock1( .CLOCK_50MHZ(in_clock), .CLOCK_1MHZ(clock) );// Symbolic state definitionslocalparam [2:0]start= 3'b000,clock_data= 3'b001,latch_clock= 3'b010,display= 3'b011,clock_data_wait= 3'b100,display_clock= 3'b101;// Internal definitionsreg[2:0] state, state_next;reg[5:0] color, color_next;reg latch, latch_next, OE, OE_next, clk, clk_next;reg[7:0] count, count_next;reg[2:0] row, row_next;// FSMD register and data specificationsalways @( posedge clock)beginif (reset)beginstate <= start;color <= 0;latch <= 0;OE <= 1;count <= 0;clk <= 0;row<= 0;endelsebeginstate <= state_next;color <= color_next;latch <= latch_next;OE <= OE_next;count <= count_next;clk <= clk_next; //Needed for the clock to complete one periodrow <= row_next;endend// FSMD next state definitionsalways @*begin// Define default casesstate_next = state;color_next = color;latch_next = latch;OE_next = OE;count_next = count;clk_next = clk;row_next = row;case (state)start:beginlatch_next = 0;OE_next = 1;color_next = 6'b001010;row_next = 0;state_next = clock_data;endclock_data:beginif (count < 191)begincolor_next = 6'b001010;clk_next = 1;count_next = count + 1'b1;state_next = clock_data_wait;endelsebegincount_next = 0;latch_next = 1;state_next = latch_clock;endendclock_data_wait:beginclk_next = 0;state_next = clock_data;endlatch_clock:beginlatch_next = 0;OE_next = 0;state_next = display;enddisplay:beginif (count < 191)beginclk_next = 1;count_next = count + 1'b1;state_next = display_clock;endelsebeginOE_next = 1;clk_next = 0;row_next = row + 1'b1;count_next = 0;state_next = clock_data;endenddisplay_clock:beginclk_next = 0;state_next = display;enddefault: state_next = start;endcaseend// Connect outputsassign clk_out = clk;assign row_out = row;assign color_out = color;assign latch_out = latch;assign OE_out = OE;endmoduleThe module that contains the PLL and altclkcntr blocks:Code:module clock_mod(input wire CLOCK_50MHZ,output wire CLOCK_1MHZ);// This module will take the 50 MHZ clock as an input// and output a 1MHZ clock that is also amplified.wire connect_pll_clock;pll pll1 ( .inclk0(CLOCK_50MHZ), .c0(connect_pll_clock) );clock_amp clock_amp1 ( .inclk(connect_pll_clock), .outclk(CLOCK_1MHZ) );endmoduleI also have an SDC file but I really don't understand it either.Code:create_clock -period 1000.000 -name clockderive_pll_clocksderive_clock_uncertaintyAny info on what I'm doing wrong or where I could learn about this would be great! Thank you for reading.

author: tsmith35
author_rank: Frequent Contributor
timestamp: May 18, 2014, 09:06:05 pm
content: Two potential sources for help here:Quartus Master Clock Warning - PLL output driving 2nd PLL InputPLL related timing constraint problemThis may help also:Internally Generated Clocks(points to page 530 of the 1640 page full handbook in pdf format)

author: pigtwo
author_rank: Regular Contributor
timestamp: May 19, 2014, 02:52:28 am
content: Thanks for the quick reply! That's perfect, I'm going to read through those.

author: marshallh
author_rank: Unknown
timestamp: May 19, 2014, 03:28:50 am
content: All you need is1. External oscillator (typically 50mhz)2. One or more PLLs (ALTPLL megafunction)Get rid of clock_ampIn your SDC file (which is simple and correct for this case) your created clock should match both the pin name and the period (in nanoseconds) of your external oscillator. Quartus can work out fine the ratios of its own PLLs but has no information about how fast the external clock is. For 50mhz this should be 20ns period.Usually I call this clk_50 for clarity.Use a more descriptive name for the 1mhz clock so you don't get confused.It looks like you have a lot of warnings because you don't actually have the PLLs wired up to any source clocks.

author: miguelvp
author_rank: Super Contributor
timestamp: May 19, 2014, 04:00:06 am
content: Look at Chapter 6 on your DE0-Nano user manual doing the my_first_fpga, They do use an schematic as the top level module and drive a verilog module by creating a symbol file from the verilog file. They derive a 5MHz clock from the built in 50MHz but you can change that.

author: Scrts
author_rank: Frequent Contributor
timestamp: May 20, 2014, 02:29:38 pm
content: The warnings here say, that you have not assigned a clock in user constraints file (SDC). When you do create_clock, you have to refer to input pin. For example:Code:create_clock -period 10 -name clk_in_100Mhz [get_ports clk_in]

author: pigtwo
author_rank: Regular Contributor
timestamp: May 25, 2014, 05:11:03 pm
content: Sorry, for the late reply.I think I'm starting to get it.@marshallh I'm just curious, what would be the use of clock_amp? I was using it because It thought it created a global clock or something but apparently not.@Scrts When you said [get_ports clk_in] would that be the pin on the FPGA? IE like PIN_A6?

author: miguelvp
author_rank: Super Contributor
timestamp: May 25, 2014, 05:41:20 pm
content: I still recommend you do the my_first_fpga tutorial from the DE0-Nano user manual. Even if it uses a schematic as the top module.But here is what it produces on my DE0-Nano regarding the input clock:my_first_fpga.qsfCode:set_location_assignment PIN_R8 -to CLOCK_50my_first_fpga.sdcCode:create_clock -period 20.000 -name CLOCK_50derive_pll_clocksderive_clock_uncertaintyCLOCK_50 being my top module input clock name.In your case it's namedin_clockBut i'm not sure how you ended up with the name being justclockinstead ofin_clock?You should be careful editing those files by hand. Edit: nevermind you have to add them by hand unless you use the system builder tool that comes with the CD. Anyways, I think you just need to call it in_clock instead of clock.Pin planner should tell you what inputs/outputs it needs, so I'm assuming you are skipping a lot of things.As far as the DE0-Nano, the only clock it has is on PIN_R8 and it's a 50MHz clock that you can feed to your pll to derive clocks from it.Edit: and the my_first_fpga uses the ALTPLL megafunction as well.

author: Scrts
author_rank: Frequent Contributor
timestamp: May 25, 2014, 08:39:50 pm
content: Since you have assigned a name to pin R8 and you want to use THE SAME name for your clock in timing constrains, here's what you have to use:Code:create_clock -period 20ns -name CLOCK_50 [get_ports CLOCK_50]You can also use different clock names in constrains, but assign a port, named by that clock, e.g.:Code:create_clock -period 20ns -name my_constrained_50MHz_clock [get_ports CLOCK_50]Remember to set a correct period.

author: pigtwo
author_rank: Regular Contributor
timestamp: May 25, 2014, 11:59:50 pm
content: @miguelvp I did actually go through it. They just didn't explain what most of it means. They just give you the code to put in the file. I got 'clock' from trying some random things I was trying at the time, I think I meant to change it back before posting but forgot. For some reason derive_pll_clocks directly doesn't work for me. I have to put it in the console and take that output and put it in the file.@Scrts Ok, that makes sense.One more question that might be kind of dumb. But what does this actually do? Is creating the clocks and all this just for testing purposes or does it effect the way it is synthesized or something?

author: miguelvp
author_rank: Super Contributor
timestamp: May 26, 2014, 12:52:31 am
content: Well the TimeQuest analyzer is what it's used to create the clocks constrainsIf you don't mind reading more examples, look in your installed path for this pdf.C:\altera\13.1\quartus\common\help\tutorial_quartusii_intro_vhdl.pdfEdit: of course select EP4CE22F17C6 and Cyclone IV E so it matches the Nano.Also check the full online free training:http://www.altera.com/education/training/curriculum/fpga/trn-fpga.htmlSpecially: TimeQuest Timing AnalyzerTiming Closure Using TimeQuest Custom ReportingTiming Closure Using Quartus II Advisors and Design Space ExplorerTiming Closure Using Quartus II Physical Synthesis OptimizationsMyself, I just keep it simple and use the system builder tool that comes on the CD to generate the pins and other files and then convert the verilog file to vhdl.

author: Scrts
author_rank: Frequent Contributor
timestamp: May 26, 2014, 08:18:14 am
content: Quote from: pigtwo on May 25, 2014, 11:59:50 pmIt does have a huge effect for placement. You always want your clock to be on a clock tree - a dedicated clock route. Then it makes the timing paths to meet the timing issues easily.

author: pigtwo
author_rank: Regular Contributor
timestamp: May 27, 2014, 08:45:28 pm
content: @Scrts Ok, that make sense.@miguelvp Wow, that's impressive how much information they have there. Thanks, I'll definitely be going through those.