Are there devices between FPGA and logic?  Is that what a GALor CPLD is? - Page 1
Forum section: electronics / projects

author: alank2
author_rank: Super Contributor
timestamp: February 11, 2018, 11:20:12 pm
content: It seems even the small FPGA's have a lot of pins and are usually pretty big. What would someone use for replacing say 6 to 12 7400 series IC's? Are there smaller things that are cost effective? How do you program them?

author: helius
author_rank: Super Contributor
timestamp: February 11, 2018, 11:31:13 pm
content: 7400 series ICs are 5V (and sometimes tolerate more than that). You need to keep in mind the signaling voltage domains.A GAL is a an erasable PAL. They are (by today's standards) very small device families that use sum-of-product logic. So if your 6 to 12 TTL chips were just implementing a truth table with so many inputs and outputs, they serve very well. CPLDs are like many GALs connected together: each part is called a macrocell and they can feed back internally. You can program CPLDs in the same RTL languages you would use for FPGAs, or use something simpler like CUPL.

author: amspire
author_rank: Super Contributor
timestamp: February 12, 2018, 12:23:12 am
content: You can program a GAL to match the functionality of a large part of the 74xx range (not the same pinout though). But also with the combination of 8 flip flops plus a lot of combinatorial logic, you could often replace about eight 74xx chips with a single GAL in a specific application. The most complex GAL I designed was one to make a Sinewave by feeding it with a clock 30x the wanted frequency, and then adding 4 phased GAL outputs with resistors to get a stepped waveform output with the first harmonic at the 9th or 11th - it was one of them. 4 of the flip flops acted as the divide by 30 function, and the other 4 flip flops latched the 4 outputs. The combinatorial logic in the GAL set the output flip flops correctly based on the current count on the counter. That felt like as far as you would want to push a 20 pin GAL.They definitely could be considered the first rung up the ladder between logic chips and FPGA's.

author: james_s
author_rank: Super Contributor
timestamp: February 12, 2018, 12:31:36 am
content: GALs are considered obsolete and have been discontinued by all the manufactures I'm aware of. Today the CPLD fills the role previously covered by GALs and before those PALs. Some modern CPLDs are still 5V tolerant.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: February 12, 2018, 12:57:16 am
content: CPLD is what you are looking for, but don't forget you may also be able to use an MCU in some applications.CPLDs start at around 44 pins, and have on-board configuration flash, usually programmed via JTAG.Design entry is typically VHDL or Verilog, though schematic type entry may still be supported by some tools -they tend to use rather old versions of vendor FPGA tools.Some of the lowest-end FPGAs (e.g. ICE40) are now getting below the cost of mid-range CPLDs (>72 macrocell) nowadays, though CPLDs may have advantages for low-power applications or when you need fast startup.

author: james_s
author_rank: Super Contributor
timestamp: February 12, 2018, 01:03:55 am
content: The line between CPLD and FPGA is somewhat blurry these days. Generally speaking a CPLD is pure logic while FPGAs will have some complex functional blocks like PLLs, hardware multipliers, memory and differential IO pairs. If it's something you'd build with a handful of 7400 or 4000 series logic chips then CPLD is the way to go.

author: amspire
author_rank: Super Contributor
timestamp: February 12, 2018, 01:04:55 am
content: Quote from: james_s on February 12, 2018, 12:31:36 amDefinitely obsolete, but you can still get them and they have very small and simple development tools.I do not have the GAL tools, but I have the Winplace software for ICT PEEL18CV8 development if you want it - like a GAL16V8 but with a bit extra. Many IC programmers still support GAL's and PEELs. It is a very simple process going from concept to a working PEEL.https://www.aliexpress.com/wholesale?catId=0&initiative_id=SB_20180211164426&SearchText=peel18cv8Winplace is only a few MBytes in size, so it is slightly easier then the modern CPLD/FPGA development environments.Now, some of the negatives. Most of the GALs and PEELs use far more current then modern devices - often 50mA to 100mA doing nothing. This used to be a big current saving when compared to the power consumption the bunch of 74xx chips it was replacing. This a is a huge problem in modern designs. There were some slower "zero power" GALs and PEELs, but these tend to be the ones that seem to be impossible to get.Second negative is that Winplace does not run on any current version of Windows. It will not run on Wine under Linux either. It may run on XP - I am not sure if it still worked on XP SP3. Definitely cannot run on Vista or later. I have a Windows NT4 VM and I can use it to run Winplace if I need it.

author: james_s
author_rank: Super Contributor
timestamp: February 12, 2018, 01:09:56 am
content: I have WinCUPL somewhere for doing GAL development, I don't recall where I found it but I have some GALs I was going to build something with at some point just because I've never used them. My TL866 programmer supports them.

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: February 12, 2018, 03:02:04 am
content: One difference between CPLDs and FPGAs is deterministic timing. CPLDs, being simpler devices, will have the same propagation delay for a given combinatorial circuit. FPGAs are far more complex, so there are almost an infinite number of different ways a given bit of logic could be implemented, each of which will have a different propagation delay. FPGA implementation software will allow you to set timing constraints, but even then the results will not be the same from run to run. Most of the time this doesn't matter if the signals are clocked by some reference, but for pure combinatorial logic, CPLDs are the only way to ensure repeatable timing results.