PIC18F46K40 start-up config for 8MHz - Page 1
Forum section: electronics / general

author: newtekuser
author_rank: Frequent Contributor
timestamp: October 20, 2024, 06:55:18 pm
content: Can someone please chime in on the configuration below? I'd like to set up my PIC18F to operate at 8MHz with the below settings and internal oscillator. Coming from a PIC16F I also see that I can't disable MCLRE, so I'm hardwiring it to VDD using a 10K pull-up.Code:// CONFIG1L#pragma config FEXTOSC = OFF // External Oscillator mode Selection bits (Oscillator not enabled)#pragma config RSTOSC = HFINTOSC_1MHZ// CONFIG1H#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled)#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)// CONFIG2L#pragma config MCLRE = INTMCLR // Master Clear Enable bit (MCLR pin is digital input)#pragma config PWRTE = OFF // Power-up Timer Enable bit (Power up timer disabled)#pragma config LPBOREN = OFF // Low-power BOR enable bit (ULPBOR disabled)#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled, SBOREN bit is ignored)// CONFIG2H#pragma config BORV = VBOR_2P45 // Brown Out Reset Voltage selection bits (Brown-out Reset Voltage (VBOR) set to 2.45V)#pragma config ZCD = OFF // ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)#pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle)#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)#pragma config DEBUG = OFF // Debugger Enable bit (Background debugger disabled)#pragma config XINST = OFF // Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)// CONFIG3L#pragma config WDTCPS = WDTCPS_31 // WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)#pragma config WDTE = OFF // Watchdog Timer Enable bit (WDT disabled)#pragma config WDTCWS = WDTCWS_7 // WDT Window Select bits (window always open (100%); software control; keyed access not required)#pragma config WDTCCS = SC // WDT input clock selector (Software Control)// CONFIG4L#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)// CONFIG4H#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)#pragma config SCANE = ON // Scanner Enable bit (Scanner module is available for use, SCANMD bit can control the module)#pragma config LVP = OFF // Low Voltage Programming Enable bit (HV on MCLR/VPP must be used for programming)// CONFIG5L#pragma config CP = OFF // UserNVM Program Memory Code Protection bit (UserNVM code protection disabled)#pragma config CPD = OFF // DataNVM Memory Code Protection bit (DataNVM code protection disabled)// CONFIG6L#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)// CONFIG6H#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)// #pragma config statements should precede project file includes.// Use project enums instead of #define for ON and OFF.OSCCON1bits.NOSC = 0b110; // Set NOSC to HFINTOSCOSCCON1bits.NDIV = 0b0000; // Set NDIV to 1 (no division)OSCFRQbits.HFFRQ = 0b011; // Set HFFRQ to 8 MHz

author: newtekuser
author_rank: Frequent Contributor
timestamp: October 21, 2024, 12:39:50 am
content: Nevermind, nothing wrong with the startup code. Device starts up fine.