Where and how do you GND reference your high speed PWM ch's return currents? - Page 1
Forum section: electronics / projects

author: MT
author_rank: Super Contributor
timestamp: September 10, 2018, 05:02:52 pm
content: Assume 2 layer standard PCB, no planes only AG/DG areas using little pond to larger pond routing impedance principle ,20 PWM channels flippin at a selected speed that can be from 700khz and 8.5Mhz, STM32 ability to change pin drive,PWM close proximity to HIFI AC coupled audio OAMPs using low signal levels so guard trace and areas is used.1: Flippin trace to resistor to cap all to DG.2: Flippin trace to resistor to cap all to AG.3: Flippin trace and half resistor to DG , as much possible rest of resistor and cap to AG. GND's sep by 10-15mil.4: Flippin trace and front pad of resistor to DG , as much possible rest of resistor and cap to AG. GND's sep by 10-15mil.5: Dont worry, whatever you do will be crap on 2 layer boards, just have a beer and relax!I used 4.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 10, 2018, 06:07:52 pm
content: I don't understand your use of language... do you have a diagram?Tim

author: DaJMasta
author_rank: Super Contributor
timestamp: September 10, 2018, 06:14:19 pm
content: Agreed I'm a bit lost.... but high speed switching is just immediately all digital ground. Wouldn't want that near my analog ground. If you're asking about floating the digital ground with an RC filter in the return path before it meets with the analog and system ground.... not worth it. A nice open return path is important, and keeping the digital side split from the analog side is helpful. Some filtering like that into the digital supply (or into the analog supply, or both) could be beneficial to keep noise off the rail, though.

author: Kjelt
author_rank: Super Contributor
timestamp: September 10, 2018, 07:56:24 pm
content: If you're lost take a beer and relax, option 5.Wait till the translation gets in and we can pick another of the options.

author: ogden
author_rank: Super Contributor
timestamp: September 10, 2018, 08:25:26 pm
content: You shall start with mixed signal layout guidelines. Most likely there are many similarities with what you are doing. TI and Analog Devices (other IC mfg's as well) have loads of information you can learn from. Just something for starters:http://www.ti.com/lit/an/slyt499/slyt499.pdf

author: MT
author_rank: Super Contributor
timestamp: September 11, 2018, 07:45:24 pm
content: Quote from: T3sl4co1l on September 10, 2018, 06:07:52 pmI barely understod it my self! To many beers!But i have a PCB picture!Quote from: ogden on September 10, 2018, 08:25:26 pmThanks, have mixed design experience (and the included headache), this multi PWM one i just haven't come across for some strange reason, but most mixed design papers sugets split the AG and DG which most of the times causes more problems then solutions. Reality are one mixed design PCB is newer like the prior one. 2 layers is most of the time more of a hassle in this regard, depends on complexity of-course and current drawn, etc, this board is very complex, 915 components majority analog.----------------------So i might run into some issues with the composite AC noise the PWM's generates.Here is 2 layout 13ch PWM examples , not entirely exactly equivalent to the questions but what realistically can be done for the questions. First is the 2 layer version of the 4 layer to the right. 10mil flippin traces, 15mil sort of DC trace, 60mil vias , (yes they are rather big) 0603 resistors and caps.Red top, grey bottom, gery/pinkish PWM DC signal, yellow top overlay. Due to complexity supplies and AG/DG is on both top and bottom. No large AG currents.2 layer, AG and DG are separated on the board and merged at a IDC connector from oposite directions into common GND pins so current flows is separated for the design while analog currents is an L shape around MCU and QSPI digital which is the biggest current hogs which have one large and short composite DG area to IDC the MCU DG return current area is almost as big as the inner fotprint of TQFP 100. the smaller QSPI area flows into the larger MCU area.

author: ogden
author_rank: Super Contributor
timestamp: September 11, 2018, 08:25:02 pm
content: Quote from: MT on September 11, 2018, 07:45:24 pmRC-filters? No worries then. - Option 5!Put at least resistors close to stm32 pins as possible. Set PWM pin speed as low as possible. Capacitors grounded to AG obviously. Yes, usually single, combined ground plane covering whole PCB is all you need. No-compromise supply decoupling for stm32. Center-aligned PWM.

author: MT
author_rank: Super Contributor
timestamp: September 11, 2018, 09:15:17 pm
content: Quote from: ogden on September 11, 2018, 08:25:02 pmYes RC filters , lesser problem then active yet they create noise and beer dont help.QuoteCant, to many PWM's.QuoteCant' they has to be as high as possible.QuoteQuoteAs mentioned no ground plane is available therefore split GND may be a solution due to garbageof the MCU and QSPI is creating.QuoteCenter aligned is an ide to considder.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 11, 2018, 09:19:21 pm
content: What are the traces going to? If they're just dead-ending in the middle of the board, don't touch analog ground at all...The above picture has two major violations:1. Digital traces crossing over analog domain.2. Digital signal currents (namely, through the filter resistors) flowing into analog domain.Tim

author: ogden
author_rank: Super Contributor
timestamp: September 11, 2018, 09:35:40 pm
content: Quote from: MT on September 11, 2018, 09:15:17 pmWhy? While answering, please tell values of RC filter components as well

author: ogden
author_rank: Super Contributor
timestamp: September 11, 2018, 09:37:15 pm
content: Quote from: T3sl4co1l on September 11, 2018, 09:19:21 pmWhat would be solution? Buffer that is powered from AVCC?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 11, 2018, 09:50:04 pm
content: Quote from: ogden on September 11, 2018, 09:37:15 pmThe solution is more holistic. You can't analyze a circuit with a signal and ground return, by looking at just a signal going one way!Tim

author: ogden
author_rank: Super Contributor
timestamp: September 11, 2018, 09:56:14 pm
content: Quote from: T3sl4co1l on September 11, 2018, 09:50:04 pmOk, Ok. It shall be advised that point where RC filter capacitors are connected to (analog) ground, shall be "star ground" point as well.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 11, 2018, 10:09:47 pm
content: Quote from: ogden on September 11, 2018, 09:56:14 pmThat's a good start, but "star grounding" is itself a minefield.A better description is a tree structure, where each subcircuit connectsonlythrough a single bundle, with connections between bundles being made at the nodes. This includes signals and power, and all bundles shall be wrapped by ground (at least as a ground plane beneath the bundle, but preferably all around; think shielded multiconductor cable).This way, signal and power line currents, and their return (ground) currents, are confined only to the paths needed, following the path of least impedance.Doing this explicitly could take up quite a lot of board area. Quite a lot of optimization is possible, but the rules for optimization are that much harder to describe and follow...Tim

author: MT
author_rank: Super Contributor
timestamp: September 12, 2018, 11:33:59 pm
content: Quote from: T3sl4co1l on September 11, 2018, 09:19:21 pmThe upper end is varying DC (with AC ripple) voltages to control of analog referenced blocks.Perhaps term Logic voltages and currents then digital currents and voltages.QuoteIsnt there just one as flippin trace is over DG while resistor current flows into cap whos AG referenced and then flows back from AG via cap via resistor into the much larger low impedance DG area then the further away and smaller AG area. Current dont flow up the creeks rather down to rivers. I havent seen a 20ch optoisolator, LTC2645 is out of the question as well. Nor is nano sized transformers available.Every textbook talks about flippin digital (logic) voltage converted to analog rippling voltage, surely you cant have an analog voltage between resistor and cap who's current is digital?When cap is filled the current comes from +VD but when cap is drained current is referenced AG. So when is the resistor/cap analog or digital?So you suggestion to this are?20pieces of MOSFET pushpull stages +VA and AG referenced? Gate voltage flipping source of garbage while gate current small to cause garbage on AG side?

author: MT
author_rank: Super Contributor
timestamp: September 12, 2018, 11:41:09 pm
content: Quote from: ogden on September 11, 2018, 09:35:40 pmWell, response time is one of the issues.QuoteThats not all determined yet

author: ogden
author_rank: Super Contributor
timestamp: September 13, 2018, 12:20:44 am
content: Quote from: MT on September 12, 2018, 11:41:09 pmThen you maybe know what those analog signals are used for?There's no need to run very high slew rate signals over your bard traces to terminate them into... RC filter. Slowest slew rate is 2MHz "speed" which means proper digital signalling at 2MHz clock rate. I doubt your PWM period frequency is even close to 2MHz. By lowering slew rate you will lower power consumption and lower EMI as well.

author: MT
author_rank: Super Contributor
timestamp: September 13, 2018, 12:30:26 am
content: Quote from: ogden on September 13, 2018, 12:20:44 amOf course you cant know what speed is needed here and mentioned 8.5Mhz is quite more then 2Mhz and of course i need to terminate into a filter else i dont get a DC. Speed gives you lower ripple and more DA bit's , smaller RC time constants give you quicker respons times, lower PWM rate is the last thing i need. Wheter or not EMI, RFI will show up as a problem is a nearfiled measurement later, as mentioned the PWM driver has programmable slew.

author: ogden
author_rank: Super Contributor
timestamp: September 13, 2018, 10:48:24 am
content: Quote from: MT on September 13, 2018, 12:30:26 am8.5 MHz is PWM clock frequency or it is PWM period frequency? Quite different things. Hopefully you understand how important is to drive outputs as slow as application allows.

author: MT
author_rank: Super Contributor
timestamp: September 14, 2018, 01:15:02 am
content: Quote from: ogden on September 13, 2018, 10:48:24 amYes i know, but i get a sense you dont fully grasp the design criteria's here and assume to much, i.e relationship of master clock, v.s resolution , ripple, and response time, RC time constants etc and ground routing impedance's who is a minefield and an form of art. Everything is as usually a "trade-off". But thanks for your input!