BGA Escape Routing from Intel Curie Module - Page 1
Forum section: electronics / beginners

author: arloomis
author_rank: Newbie
timestamp: July 12, 2017, 05:43:45 pm
content: Hello,I am trying to route an Intel Curie module package, which has two 4x14 BGAs. My minimum trace width is 6 mil, which is too wide to fit between the pads with 6 mil spacing (but I can route diagonally). I have been trying to use the outer pads as much as possible, but there are a few pads that must be routed on the inner pads. I was thinking about trying to jump between unused GPIO pads to escape route the inner pads. Is this possible? If I configure the unused GPIOs as inputs and just do nothing with them, can I use them to bridge between the inner pads and outside the package? For example, I have included a picture of one of the 4x14 BGA layouts (1 side of the Intel Curie). I need to escape the K2 pad (which needs 3.3V), and J2 can be configured as GPIO_SS and H1 can be configured as GPIO_SS. If I configure both these as GPIO inputs with no pull up resistors, can I route through these pads to escape?Intel Curie module datasheet (ball mapping starts on page 13):https://www.intel.com/content/dam/support/us/en/documents/boardsandkits/curie/intel-curie-module-datasheet.pdf

author: fourtytwo42
author_rank: Super Contributor
timestamp: July 12, 2017, 05:54:11 pm
content: The problem is you cannot know the transient state of the GPIO's during power up/down. You don't say how many other layers you have for what but assuming you have some power planes a small slot to accommodate a short link signal track may be a better solution.

author: arloomis
author_rank: Newbie
timestamp: July 12, 2017, 06:10:30 pm
content: I am trying to do this on a 2 layer board. The GPIOs all default as high impedance inputs on power up, and the K2 pad is an input for voltage selection, so would it be okay? The IO voltage is 3.3V across the module.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: July 12, 2017, 06:43:16 pm
content: Can you fit a via in the open space between 4 pads? You could also make the BGA pads a little on the smaller side of nominal if it would make the difference.

author: free_electron
author_rank: Super Contributor
timestamp: July 12, 2017, 06:47:29 pm
content: Didn't intel just discontinue all those Edison / Galileo / Joule products ?

author: arloomis
author_rank: Newbie
timestamp: July 12, 2017, 06:58:57 pm
content: Intel didn't discontinue the Curie, but they did discontinue all the other ones you mentioned. A via will not fit in between the 4 pads, but if I make the unused pads that I need to squeeze through really tiny (4 mil dia vs recommended 10 mil), then the trace will make it through. However, at that point the pad won't be able to be manufactured because it's so small, and I might as well just get rid of those pads, but I think that would cause problems when reflowing the BGA? Would it?

author: fourtytwo42
author_rank: Super Contributor
timestamp: July 13, 2017, 07:14:18 am
content: Quote from: arloomis on July 12, 2017, 06:10:30 pmAs I understand it this is a logical input rather than a power pin so you could connect it to 3V3 by a pullup resistor meaning it would then be safe to pass through the GPIO's on the way.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 13, 2017, 08:24:41 am
content: Fine pitch BGAs can't be reliably connected with bargain-basement PCBs. Pay up.Otherwise, find an alternative device that does have an accessible footprint. Or get the dev kit, I suppose (but, again... pay up?).Fine BGAs are most often used with HDI (high density interconnect) PCBs, i.e., laser drilled vias between layers, filled flat with copper plate. They're not terribly cheap to prototype, but are certainly workable when you get to the thousands or millions as cellphones do.Tim

author: arloomis
author_rank: Newbie
timestamp: July 13, 2017, 02:26:59 pm
content: I understand where you are coming from T3sl4co1l, and the Intel Curie package is not even a complex BGA, but I only have 3 pads on the inside that I need to escape. All the others I managed to use alternate functions of the GPIOs to get most of the pads I need on the outside. I find it silly to triple or quadruple the cost of my board just to safely escape those 3 pads. If I can pass through unused GPIOs instead, that would be a much better alternative.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: July 13, 2017, 03:25:16 pm
content: I think we'd need to know more about the pins on the inside that you're trying to break out. You mentioned K2 which is a voltage select input, as fourtytwo42 mentioned you might be able to use a pullup to make it safe to jump through an adjacent pad (though it's possible this other pad may temporarily output low during powerup, which could mess up the voltage selection logic on K2). What are the other pads you need to escape?Does your board manufacturer not have an option for slightly tighter tolerances for a bit more? 2 layer 6/6 trace/space sounds like it could be OSHPark, their 4 layer boards are only twice the price per square inch and have 5/5 trace/space and smaller annular rings on vias, which might help. Being 4 layers might let you make the board physically smaller as well, bringing the price difference down.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: July 13, 2017, 03:28:47 pm
content: Quote from: arloomis on July 12, 2017, 06:10:30 pmOnce the chip is up and running, yes, but during power-up many devices can temporarily output low or high on some pins before the part is completely powered up and settled.

author: arloomis
author_rank: Newbie
timestamp: July 13, 2017, 04:01:44 pm
content: The two other pads I need to escape are N2 and M2. These are pins for the internal switching regulators, which I am not using. However, the datasheet recommends tying these pins to ground with a pull down resistor (pg. 31). Unfortunately, all the pads adjacent to these pads are for power or essential GPIO. Is there a chance I could just leave these pads open instead of tying them to ground? The only other option is to tie them to adjacent ground pads P2 and P1 without a pull down resistor.Design Guide:https://www.intel.com/content/dam/support/us/en/documents/boardsandkits/curie/intel-curie-module-design-guide.pdf

author: arloomis
author_rank: Newbie
timestamp: July 13, 2017, 04:09:19 pm
content: The manufacturer I am using is Elecrow, and unfortunately their tolerances are the same for their 4 layer boards. I have had good results from Elecrow in the past, and they offer an insanely good price. I know that I am being cheap... but I'm trying to manufacture this for as little as possible.

author: arloomis
author_rank: Newbie
timestamp: July 14, 2017, 04:13:37 pm
content: So do you think I could leave pads N2 and M2 open? It's not what is recommended in the Design Guide, but it seems to be my only option.Here is the design guide, pg. 31 states the recommendation:https://www.intel.com/content/dam/support/us/en/documents/boardsandkits/curie/intel-curie-module-design-guide.pdf