Simulating and Nulling Log Converters, Op Amp Offset - Page 1
Forum section: electronics / projects

author: mc172
author_rank: Frequent Contributor
timestamp: January 22, 2021, 06:33:37 pm
content: I've had a bit of free time recently and have had another mess around with log converters. I've been trying to make sure that I've got enough adjustment range before I start to build one but am running into a problem. Here is my circuit:Vin is the input voltage, 0-10V range, 0-1mA range across R4. V4 is a reference voltage which sets up a 1mA reference current through R7.I am expecting to see 0V at Vout (output of U1) when Vin = 10V, but I can't get Vout lower than 34.2mV without adding lots of offset to the + input of U2. I am expecting to have to null/adjust the offsets on U2 but I have to put a lot more than I'd expect onto the +input of U2, around about +0.6V which seems pretty high to me, in order to get the output down in the single uV range.Like this:I have attached the LTSpice simulation.R6 and R9 are funny numbers because in reality it would be the offset null for U1 hence a random value.Has anyone got any advice please? I can't understand why the lower limit is ~34mV without lots of bias on U2.

author: mc172
author_rank: Frequent Contributor
timestamp: January 26, 2021, 03:01:02 pm
content: Not sure why my pictures didn't appear in the post?I've still not had any luck figuring this one out, has anyone got any ideas please? The circuit works as a log converter:edit: Still can't place images in the post. Oh well.

author: mawyatt
author_rank: Super Contributor
timestamp: January 26, 2021, 03:43:02 pm
content: Took a quick look. Q1 has no base R and Q2 has R2 and R1. The Q2 beta causes Q2 base to draw 1ma/beta. If the base of Q2 is forced to zero by U1, then all of 1ma/beta is supplied thru R1 which requires a voltage at U1 output of R1*(1ma/beta). So adding a 1K in Q1's base should bring the output of U1 close to zero if the + input is near zero.BestEdit: Just did a quick sim with a similar circuit using 2N3904 and R1=15K, R2=1K and Rx added to base of Q1 as R1 in parallel with R2 (937.5) and Vout is zero as expected.

author: mc172
author_rank: Frequent Contributor
timestamp: January 26, 2021, 04:59:27 pm
content: Thanks Mike, I also simulated it and you're right.Do you think it's a good idea to aim for trimming the output to very close to zero, or would it be better to live with the slight offset and put Q1's base straight to ground? After all, I only really care about the log component, the offset could be dealt with after the log converter. The reason I ask is that of all the examples of log converters I've seen, I haven't seen one with a base resistor on Q1, let alone a trimming network which I'd need.

author: mawyatt
author_rank: Super Contributor
timestamp: January 26, 2021, 05:11:12 pm
content: Not sure what would be best. You could try both methods and see which gives better results. Also consider using smaller resistors for R2 and R1 which will also reduce the offset.BTW have you considered Successive Detection Log Amps, these can have ~100dB range.Best,

author: mawyatt
author_rank: Super Contributor
timestamp: January 26, 2021, 07:58:13 pm
content: Here's the circuit used and the output with the zero output reference at 1ua.Best,

author: mc172
author_rank: Frequent Contributor
timestamp: January 27, 2021, 02:46:51 pm
content: Once again, thanks Mike.

author: mawyatt
author_rank: Super Contributor
timestamp: January 27, 2021, 05:19:55 pm
content: If you look at the circuit I've posted the reference current can be placed anywhere in the range, from nano amps to milliamps, without any need for a circuit change. So the Voutput output "zero" volts can be placed anywhere in that range from nano amps to milliamps. The "extra" base resistor is optional, and can be omitted, but allows compensation for the reference transistor effective base resistance as "seen" for the reference transistor base. You don't need to worry about the collector or base voltage of either transistor, the feedback setup keeps the collector voltage of both transistors at 0 volts. The emitter voltage is always negative and servoed to the proper value to maintain the proper collector currents in both transistors, with the sum of those currents flowing thru the emitter resistor (R11) to the reference op-amp output. This is why you want this resistor (R11) to have a value low enough to support those currents without the op-amp nearing the negative rail at maximum input.Remember this is a log amp with an output that represents Voutput = -K*log (Input Current)/(Ref Current), where Input Current can be Vinput/Rinput like in your circuit. Log of 0 is undefined and the output will go to the + rail of the op-amp as shown below where the input current is so low (below 10fA) as to be determined to be zero. K in this circuit is calculated based upon the transistor characteristics as follows.Vbe = Vt*Ln (Ic/Is), where Vt is kT/q or 1.38e-23*300/1.6e-19 or 25.875mv @ 300KVbe1 = Vt*Ln(Ic1/Is) and Vbe2 = VtLn(Ic2/Is), then Delta Vbe = Vbe1-Vbe2 = Vt*(Ln(Ic1/Is) -Ln(Ic2/Is)) or Vt*Ln(Ic1/Ic2)For a ratio of 10, then Delta Vbe = Vt*(Ln(10)) or 59.5794mv @ 300KFor a desired Voutput scale of 1V/decade of Input Current then the feedback resistor ratio (R10/R9) should be 1/Delta Vbe -1, or 15.7843, so for R9 = 100 ohms then R10 is 1.5784K.Anyway, this is how the circuit works and how the scale factor can be created with a simple resistor ratio. Since the collector is always at 0 volts leakage currents to the base are very low and the transistor can be operated at very low currents, although in actual practice one must pay attention to op-amp bias currents (low bias current op-amps are good for this) and likely the lower limit is a few 10s of picoamps. On the high current end the transistor collector, emitter, and base internal resistances come into effect and well as some other non-ideal transistor factors.Edit: Added a plot showing the effect of a high input current causing the op-amp to go to the negative rail due to a higher value emitter resistor (1K) and/or the op-amp sinking current limit. As you can see this happen just after 10ma of input current. Then added a pnp emitter output to the op-amp to increase the current capability and you can see this in the next plot, note how the graph begins to deviate from idea ~20ma due to the mentioned transistor effects.Best,

author: mc172
author_rank: Frequent Contributor
timestamp: January 29, 2021, 10:41:53 pm
content: That's really helpful, thanks!I seem to remember reading somewhere (AoE? It's also mentioned in the LOG114 datasheet) that the reference current should be roughly in the middle of the expected input current range (so about 1uA). I also recall reading that the reference current should be about a decade larger than the largest expected input current, but this doesn't seem to work very well. It seems to be easier to adjust for input Vos, output scale and zero intersect with the reference current in the middle of the input range, so I'll go with that.

author: mawyatt
author_rank: Super Contributor
timestamp: January 29, 2021, 11:54:23 pm
content: If you use a low input bias current op-amp the low end can be extended.Another interesting adaptation is to use this circuit to read dBm referenced to 50 ohms. Since 0dBm is 1mw, then Irms is 4.472ma for the reference current. You may need to use a pnp buffer for the op-amp output if you want to sense above 0dBm, for example +10dBm is 14.1421ma and +20dBm is 44.7214ma. These higher currents will require a higher current sense and reference transistors also and the mentioned buffered op-amp outputs. The scale factor remains the same and with the mentioned resistor ratio is 20dB/volt. Of course the input must always be + and never go below zero (input could be from an absolute value circuit).Best,