Using upper 15bits of a 16bit, does the INL gets halved? - Page 1
Forum section: electronics / projects

author: Kokoriantz
author_rank: Frequent Contributor
timestamp: September 14, 2025, 08:56:05 am
content: I want to use DAC8830 ID version with +/-4LSB INL. I need only 15bits. My LSB is the double that of 16bit.The Gougle AI saying me that the INL doesn't change with the bit depth.Will it become +/-2LSB or not?

author: radiolistener
author_rank: Super Contributor
timestamp: September 14, 2025, 09:08:02 am
content: Truncating the LSB does not improve the DAC intrinsic INL — it stays the same. What you add is quantization error from discarding the bit. If you really want to drop to 15 bits, rounding or applying dither is preferable than simple truncation, as it minimizes added distortion and turns the error into benign noise.

author: wraper
author_rank: Unknown
timestamp: September 14, 2025, 09:11:12 am
content: INL stays the same, you use less bits. So 4 out of 16 bits INL becomes 3 out of 15.EDIT: I had a brainfart. Yes, effectively it will be 2 bit INL if only 15 bits are used.

author: Kokoriantz
author_rank: Frequent Contributor
timestamp: September 14, 2025, 12:05:39 pm
content: The definition of INL is the accumulated error expressed in LSB. The 16bit LSB is 1/64k, the accumulated error than is +/-4/64k units. My 15bit only DAC, the LSB is 1/32k which now has +/-2LSB accumulated error or INL all keeping the absolute value the same.

author: radiolistener
author_rank: Super Contributor
timestamp: September 14, 2025, 01:39:15 pm
content: The DAC’s INL in its own LSB units does not change when feeding lower-resolution values. However, if you express INL in terms of the LSB of the applied lower-resolution signal, the numerical value in your custom LSB appears reduced, giving the impression of improved linearity. In reality, this does not change the actual linearity of the DAC, it only gives the illusion of improvement, since you are comparing INL in LSB units across different bit resolutions which is not meaningful.Note that this also reduces the effective dynamic range. Also keep in mind that simply filling the unused LSB with a constant introduces quantization noise and may add a DC offset. Dithering is recommended to minimize these effects.I would advise against this approach, as it increases quantization noise and may introduce additional spurious artifacts. Using fewer bits does not actually improve the DAC linearity — the absolute nonlinearity remains unchanged.Quote from: Kokoriantz on September 14, 2025, 12:05:39 pmBut the weight of your custom (truncated) LSB is doubled, so the actual output non-linearity in voltage remains unchanged.In other words, reducing the bit depth does not improve the output signal linearity of the DAC — it remains the same as before. However, the signal quality will noticeably degrade, with increased quantization noise and adding spurious artifacts.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: September 14, 2025, 09:03:52 pm
content: Quote from: Kokoriantz on September 14, 2025, 08:56:05 amEffectively 4 LSB on 16b is giving you 14 bits of INL, so you are still coming up short of your 15b target, unless that is 'near enough'.

author: Kokoriantz
author_rank: Frequent Contributor
timestamp: September 15, 2025, 12:54:58 am
content: I am not truncating the LSB, I am truncating the sign bit MSB and loading the DAC only with the magnitude 15bit on the upper bits. The sign bit is sampled out by a D latch and steers the output of the DAC to either inputs of a differential amp. By this, I don't have zero crossing problems, the same cheap DAC is used for both polarity gives perfect symmetry (-1 add by a 100M resistor from MSB/) and my DAC is twice higher resolution. NO?

author: Kleinstein
author_rank: Super Contributor
timestamp: September 15, 2025, 08:08:50 am
content: Using only half the range is completely different from dropping the LSB. How this effects the INL very much depends on the DAC. There is not easy way to tell how the INL changes. Depending on the exact definition used (e.g. end points or best fit line) the INL error expressed in LSBs could even get worse. If much of the INL error is from the MSB switching, there is a chance to get a slightly better looking number, but hardly half the LSB number, as the new MSB is usually not better, but more not as good.

author: radiolistener
author_rank: Super Contributor
timestamp: September 15, 2025, 11:43:18 am
content: Quote from: Kokoriantz on September 15, 2025, 12:54:58 amThe DAC output linearity is fundamentally determined by resistor matching errors inside the DAC itself, so it cannot be improved by external bit manipulation — at best it stays the same, but more often it gets much worse.Regarding to implementing the sign bit externally with switching - this is a very poor idea: your external circuitry will never track the phase timing of the DAC core, which leads to glitches and sharp transients during transitions due to phase delay difference between your external circuit controlled by sign bit and internal DAC circuit for the rest of the bits. In addition, the positive and negative paths will have different amplitude and phase responses, introducing further nonlinearity.In practice, phase skew between bits makes it impossible to implement a DAC with more than about 10 bits of resolution using discrete components, even if the layout is perfectly symmetrical and timing is tightly controlled. Technically, you can build a higher-resolution DAC from discrete components, but its performance will usually be inferior to that of standard 10 bit DAC, mainly due to nonlinearity and output glitches caused by phase-skew between the bit transitions. In practice good 14-bit DAC on discrete SMD with precise resistors will have SNR about 40 dB which is just 6 bit ENOB - this is the real value taken with discrete 14-bit DAC on precise SMD resistors.This is why higher-resolution DAC are implemented as integrated circuits, where resistor networks and switching elements can be precisely matched. For applications requiring exceptional linearity, manufacturers perform precise on-chip laser trimming of resistors during production.In short, you will not reduce INL by this method, instead you will significantly increase nonlinearity and add noticeable output glitches.If the goal is to improve the DAC linearity, in theory the only direct way would be to remove the chip’s package and, under a microscope with a precision laser, trim the internal resistor network to reduce matching errors. In practice, however, modern DAC architectures are far more complex than a simple resistor ladder, so this approach is neither feasible nor effective.If the output stage uses an amplifier with significant nonlinearity, you can apply digital pre-distortion to the DAC input to compensate for the amplifier’s behavior. However, this approach does not work for correcting the DAC own nonlinearity, since it is typically on the order of 1–2 LSB and cannot be effectively compensated in the digital domain due to resolution limits. In practice, the best option is to select a DAC chip with inherently better linearity — there is no real alternative.In theory, one could try to improve effective linearity using oversampling combined with digital pre-distortion based on a calibration table — significantly increasing the sample rate, applying DSP, and then filtering with an analog low-pass filter at the output. Oversampling and noise shaping can increase effective resolution, while digital pre-distortion could in principle be used to compensate for DAC non-linearity. However, this requires a very complex DSP chain and a sophisticated calibration process to build an accurate pre-distortion table. In practice, this approach is usually far more complex and costly than simply selecting a DAC with better intrinsic linearity, and the results are not guaranteed, as they strongly depend on the internal architecture of the specific DAC chip.