GAL program example search - Page 1
Forum section: electronics / general

author: Wawavoun
author_rank: Regular Contributor
timestamp: August 10, 2025, 08:39:25 am
content: Hi All,I am in search of an example of a 22V10 GAL program that do a by 2 division and a by 3 division of pin 1 clock.This output clocks must have 50 % cycle time.I expect to do other things with the GAL so the less outputs the program use the better it is.I already successfully program 22V10 GAL with basic logic equations (and, or, etc..).By 2 division is easy to to do.I have walk into a lot of manuals and documents but honestly I lack the basic programming concepts of sequential machine so they are hard to read for me.I am lost between nodes, fields, what I must affect to an output pin, what I can not affect to a output pin, what clock I can use or not for each macrocell etc...Thanks for any help or pointing me a relevant document or example.Philippeps : first try is attached in txt file because .pld is not accepted here...

author: up8051
author_rank: Frequent Contributor
timestamp: August 10, 2025, 12:51:02 pm
content: https://www.scribd.com/document/73736318/Divide-3-Counter

author: Wawavoun
author_rank: Regular Contributor
timestamp: August 10, 2025, 04:40:17 pm
content: SCRIBD ask about a payment...I revised my strategy because using both edges of the clock is a requirement for DIV/3 with 50 % duty cycle and its not possible into 16V8 nor in 22V10.So I switch to a by 6 divide. Much more easy, working code is below...But now I want to divide the resulting clock by 2 and 4. How can I do that ? A state machine with 24 steps (5 latches required) seem to be very complicated...Thanks.Philippe

author: up8051
author_rank: Frequent Contributor
timestamp: August 10, 2025, 06:47:56 pm
content: https://www.mikrocontroller.net/attachment/177198/Clock_Dividers_Made_Easy.pdfPage 14 : 5.3 Divide by 3 with 50% duty cycle output

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 12, 2025, 09:44:38 am
content: Quote from: Wawavoun on August 10, 2025, 04:40:17 pmLook at register select (or similar?) in CUPL that allows you to code for .t FF, but compiles to the chips .d FF.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 12, 2025, 09:17:30 pm
content: Quote from: Wawavoun on August 10, 2025, 04:40:17 pmThe better way to manage that is to divide by 3, then divide by 2 so your output is a clocked register, not a decoded combin term, which might glitch, and costs one more pin.Code:Register_select Div6 = 1; /* Register_select 1:= .D, 2:= .T 3:= JK, 4:= RS 5:= Best, but check! */Div6.t = D3q1;/*DIVIDE BY 3000110*/D3q0.d = !D3q1 & !D3q0;D3q1.d = !D3q1 & D3q0;If you want to divide by further 2 and 4Code:Div6TC = Div6 & D3q1 & !D3q0; /* true once in 6 clks */Register_select Div12 = 1;Register_select Div24 = 1;Div12.t = Div6TC;Div24.t = Div6TC & Div12;

author: zapta
author_rank: Super Contributor
timestamp: August 13, 2025, 01:32:18 am
content: Quote from: Wawavoun on August 10, 2025, 08:39:25 amWhat do you use the output for? If it's not used as a transition based clock than it's not sensitive to glitches (which makes the solution simple) and if it does, why do you care about the duty cycle?(I am trying to understand if the problem is over constrained).

author: Adrian_Taylor333
author_rank: Regular Contributor
timestamp: August 13, 2025, 04:27:32 am
content: 1. PALCE is usually much better choice than GAL ( == cheaper, lower power, faster), but it requires solid programmer, since algorithm is proprietary.2. Divide-by3 trick with 50% duty ratio is IIRC done as divide-by-2 of the clock that is negated between each flip ( simple XOR with the latest state of the divide-by-2 flipflop).3. There is no "program" for these PLDs as nothign gets executed. You can only write equations in ABEL or similar form, which then get compiled into fusemap.