DC/DC converter for Inverter - Page 1
Forum section: electronics / general

author: ManniW
author_rank: Contributor
timestamp: June 22, 2023, 02:29:06 pm
content: Hi everyone,I want to design a DC/DC converter that can produce half-waves for a grid tie inverter. The nominal input voltage is 41V and the ouput power is about 400W. Output voltage is 250V RMS, so I need about 350V peak voltage. The targeted efficiency is 96% or higher. I have looked at various topologies, especially interleaved Flyback Converters, LLC Converters and the Push-Pull Converter. At this point I believe the best way to move forward is using a push-pull converter, but I am open for other suggestions! Is it possible to achieve the targeted efficiency of 96% with a push-pull converter and how do I need to design the transformer in order to achieve that?Regards

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 22, 2023, 06:11:47 pm
content: That's quite high efficiency. The challenge with high efficiency is tracking every possible source of loss, and shrinking them down, without increasing others more.For example, you can't simply use massive transistors because the junction capacitance has to be charged and discharged; in a pulse type converter, this is a direct loss. In a resonant converter, this isn't much of a problem, but a resonant converter also needs high quality components -- typically PP film or C0G ceramic capacitors, and inductors and transformers using litz wire and ferrite. Give or take whether some can be recovered via quasi/resonant snubbing. Which is particularly difficult to apply these days, switching times being comparable to device (inductor and diode) parasitics. There are loss mechanisms in some cases. High voltage (Superjunction) transistors exhibit hysteresis loss (there's an RC characteristic to the junction capacitance); this does not affect planar (old or low voltage) types, or at least not to such a degree.And even in a resonant converter, there are strays that can't be coupled to the resonant (recirculating) energy system, and thus result in losses. For example, a push-pull inverter (or FWCT rectifier), the leakage between winding halves is not coupled, and experiences not just dI/dt, but harmonics as well (each half-winding sees half-wave current). The harmonics excite the leakage mode and you either get ringing, or add an R+C snubber or whatever to absorb it.In general, larger components can have lower loss, but they're, well, a lot bigger -- and more expensive. What is your budget, how much size and component cost can you tolerate?Lower frequency tends to help by reducing core hysteresis, and switching loss in pulse-type converters, but size goes up especially fast at low frequency. So it's a weak effect, and if you are size or cost constrained, frequency can't be kept too low.Conversely, high frequencies tend to improve by inductive reactance being higher for the same inductance. Magnetics by themselves, have a roughly F^(1/4) scaling factor, something like that I think? That is, size is smaller with higher frequency, but not proportionally, because of various loss mechanisms: core losses have a range of exponents, but often more than F^1 B^2; skin effect goes as F^(-1/2), but can be countered with litz wire at least up to modest frequencies (MHz?); etc.Tim

author: ManniW
author_rank: Contributor
timestamp: June 22, 2023, 06:51:54 pm
content: Quote from: T3sl4co1l on June 22, 2023, 06:11:47 pmI was thinking about theSIR5102DPas it has a low RDSon and a low gate charge, allowing fast switching. Is the junction capacitance mentioned in the datasheet of that part aswell (maybe under a different name?) so I can look out for it when comparing available options?Quote from: T3sl4co1l on June 22, 2023, 06:11:47 pmHigh quality components aren't an issue, what I am more worried about is that they need accurate calculations and tuning so they work correctly as far as I know. Can a converter that has to produce a voltage that follows a sinus half wave even be run as a resonant converter?I found a research paper describing a current-fed push pull converter, but I believe as they have an inductor on the primary side they are not suitable for my use case as I need the output voltage/current to be a half-sine? The efficiency of that converter is above 97%, which should give me overall inverter efficiency of 96% (the only other real losses should be 2x RDSon of the H-Bridge and the filter circuit).Quote from: T3sl4co1l on June 22, 2023, 06:11:47 pmThis is for academic purposes only, so there is no real budget and size limit, as long as it's still reasonable.I had a look at a commercially available converter that runs in interleaved mode (so they use 2x 200W to achieve 400W total output power) and they have quite some capacitors in use, aswell as a clamping circuit that seems to measure something? I attached what I reconstructed from the PCB so far, it looks like a flyback converter to me. As far as I am aware flybacks are less efficient than push-pull converters?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 22, 2023, 07:16:29 pm
content: Aha, that's a quasi-resonant or "lossless" snubber.MOSFETs, you're looking for "Coss". It varies strongly with Vds (page 3, right middle). Notice the tabulated value is only at high Vds (here, 50V) which doesn't tell you the whole picture.A mains half-sine is DC for purposes of the SMPS and control, don't worry about it. Current or voltage fed doesn't matter too much but you'll generally incur an extra stage -- a buck to maintain that constant current in the inductor. Whereas a choke-input rectifier at the output (forward converter)Notice the symmetry between these cases: they really aren't different cases at all. A forward converter must have one series inductor somewhere, which can be either primary or secondary. Causally speaking, if it's primary then it has to be controlled (switched) on the primary side, while on the secondary side its current will be measured (e.g. average current mode control) but diodes can handle the switching passively. To see it more directly, replace diodes with synchronous rectifiers.I gather you are still new to the topic, and especially since you say academic purposes -- by all means dig into the academic value of this topic. Understand where, how, and why switches and inductors and capacitors are used together, understand the equivalences that connect the standard topologies, and understand what happens in the instant of the switching edge -- and what other elements get involved therein (device capacitance, loop inductance, leakage, etc.). This can take -- and is well worth -- years of study, and there are still many device quirks I am unaware of, for example (though I "discovered" one of them this year!), having over a decade in the business.Tim

author: ManniW
author_rank: Contributor
timestamp: June 22, 2023, 08:33:28 pm
content: Quote from: T3sl4co1l on June 22, 2023, 07:16:29 pmDo you have any idea what they are measuring there with the OpAmp? Seems like some kind of voltage with the diode to VCC serving as an overvoltage protection?Quote from: T3sl4co1l on June 22, 2023, 07:16:29 pmAlright, I will keep that in mind when comparing available options. How "important" is it? I assume in my case I want to focus on a low RDSon first as I have quite a high current (about 10A)? I then looked for low Qg so I can switch as fast as possible. I did some comparison of the MOSFETs I considered so far and noticed the Coss is pretty constant at 1000pF at 50V, no matter if I use multiple FETs parallel to achieve the low RDSon (Coss adds up in that case I assume) or use different types with a slightly higher RDSon.Quote from: T3sl4co1l on June 22, 2023, 07:16:29 pmI was more thinking about having to turn off the converter entirely during the zero cross as I can't go infinitely low with voltage/current and need some time to switch around the output H-bridge. The current-fed versions seem to have an additional inductor before the transformer, so I assume the FETs need to be designed for higher voltages aswell in that case. I was worried that this inductor would make it difficult or impossible to do the short turn-off during zero crossing.Quote from: T3sl4co1l on June 22, 2023, 07:16:29 pmMakes sense, the series inductor is responsible for ensuring an (almost) constant current/avoiding fast changes. I am wondering if I actually need that as part of my DC-DC converter: In my case I will be basically driving the grid directly, of course I will have filters in place, but they will be after the H-Bridge. The commercially available inverter that I took the schematics from doesn't have any inductors between the DC-DC converter and the H-Bridge, just 2 film caps as buffer.Quote from: T3sl4co1l on June 22, 2023, 07:16:29 pmYes I am indeed new to switching mode power supplies and I spent the last 2 weeks reading different papers and looking at the diagrams where they explained the current flow in various operation stages of the inverter. I still haven't decided on which topology I will use, so far I considered a non-isolated approach first, ditched that approach after noticing I can't reach the wanted efficiency and after seeing that commercially available inverters can do the wanted efficiency with an isolated approach aswell. I then considered Flyback, LLC Converter and now I am considering the push-pull converter, probably with some kind of "extras" like resonancy added so the intended efficiency is reached somehow.If I manage to build a resonant push-pull converter, the resonancy would only be working at a certain frequency? So I would have to adjust the duty cycle to produce the sine by doing something like 25% FET1, 25% off, 25% FET2, 25% off?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 23, 2023, 02:53:29 am
content: Quote from: ManniW on June 22, 2023, 08:33:28 pmOn second thought, that's wrong. Similar, but the diodes aren't the right way. They're shown connecting the "snubber" inductor in parallel with the transformer, during flyback. Which seems very odd. Maybe the inductors are very large?The resistor and IC could be anything; between the partial schematic, and possible transcription errors, I could only guess.QuoteFar too early to say anything; there's no design, at all, as yet.As a hand-wave, a 40V input, push-pull converter develops a peak over 80V (for which 120-150V transistors would be safer), and 1nF at 80V is 3.2uJ. At 100kHz, that's 0.32W, hardly noticeable. 5mΩ at ~15A is 1.1W conduction loss. Switching loss likely dominates, or stray inductance or other matters of course.QuotePWM goes to zero as voltage goes to zero. 0% PWM is otherwise known as "off".How would you know?QuoteYou need an inductor somewhere to avoid hard-switching the transistors (from a constant voltage source / capacitors) into the output capacitors. That's basically short-circuit operation with extra steps; there are a few very limited converter applications where such can be acceptable (automotive power amplifiers are a typical case; transformer leakage plus MOSFET avalanche robustness allows a TL494 to soft-start the poor thing; once operating, it runs at "full throttle" and has zero regulation -- it's more a DC transformer than a converter), while in the vast majority of applications, an inductor is used to set dI/dt through the switching circuit and output filter / coupling network (e.g. transformer etc.).In resonant converters, the series inductance alternately stores energy (along with the transformer magnetizing inductance) versus the resonant capacitor; most of the energy delivered by the inverter flows to the output, but the rate (within a cycle, and from cycle to cycle) is dictated by the LLC network (LLC being the most common one, but there are others of course), and the energy so stored fluctuates around in the network where it can be reused next half-cycle.In flyback, the windings are coupled together, sharing the same core magnetization, which sets dI/dt. The leakage is equivalent to the stray inductance between switch and diode in a boost.In forward, the transformer couples primary and secondary together, as a buck with leakage equivalent to stray inductance; the output inductor sets dI/dt.In current-fed forward, the inverter and rectifier switch places, and an additional switch may be needed to set current (somewhat equivalent to the catch diode in a half-wave forward).There are also current/voltage series/parallel equivalents. Some of which are in common use (PP vs. half bridge), but some of which are... a bit bizarre just at a glance, until you realize what's going on. (Current-sourced series (half-bridge) I don'tthinkhas any application...)Most of the current-mode versions aren't too useful, because a true general purpose current-sourcing inverter must handle reverse voltage the same way a voltage-sourcing one handles reverse current. That is, instead of an antiparallel body diode, you need a series diode. The only devices intrinsically with this characteristic are SCRs, vacuum tubes (if you don't mind goingwayback in history), and some IGBTs (which are built with some similarities to SCRs, but the latching is avoided). To use MOSFETs or BJTs, series diodes must be added.(A pulse-type switching converter is a special case, where the load voltage can be always in phase or inductive, therefore MOSFETs can be used directly without much consequence. A resonant converter doesn't have the same trick, and indeed I've worked with an induction heating machine which used a current-fed H-bridge -- parallel resonant tank, so you can't use a voltage-sourcing inverter with it (the switch-into-capacitor problem again!). They used an enormous inductor, like 20 pounds of copper and ferrite. Granted it was a 10kW machine, but, needless to say it was NOT optimized for weight!QuoteI would suggest sticking with a pulse type, like a forward or flyback converter. The waveforms are easy to draw, and control is simple enough. Prefer current mode control where possible. Flyback is a bit of a stretch at 400W, but that can be eased with a two-phase interleaved system, if you're up for a more complicated controller. Flyback has the advantage of better behavior at high voltages; the output impedance (ballpark 400V / 1A = 400Ω) is on the high side [compared to normal circuit / RF impedances of say 50-100Ω], but still well within reach of forward as well.Anything touching mains must be isolated. If the converter is direct fed type, then the entire low voltage (battery? solar? whatever it was) section must be isolated for full mains voltage -- because it will have hazardous voltage (AC plus surge) on it.Isolated is also easier to deal with during development. Note that isolation can be as simple as a (mains frequency) transformer.Also, don't touch mains until you have all the inverter features properly in. Incorrect or glitchy phase tracking, high/low line or islanding protection, etc. Test with an AC source/load unit that's safe to use with other test equipment. Any misstep and your setup is toast (or worse..). Save yourself the frustration, do incremental development: fully describe and test each piece and connect together / scale up to eventually test it on mains.Tim

author: ManniW
author_rank: Contributor
timestamp: June 23, 2023, 05:02:44 pm
content: Quote from: T3sl4co1l on June 23, 2023, 02:53:29 amThe resistor is part of a voltage divider (I forgot to draw the other resistor to GND) and the IC is indeed an OpAmp that seems to act as a buffer. The inductors are very small (0805 or something like that) and the trace that connects them is super small aswell, so nothing for big current and just some signal apparently, the trace that connects the caps to GND is much bigger. I am not sure if that is actually GND though, the mounting of the transformers is connected to it, so I thought it's GND, but it could be VCC aswell. The diodes are definitely in the right way. I believe that would make a lot more sense as it forms a quasi-resonant flyback then, with the option to measure something there, possibly when to turn on the FET again? A quasi-resonant flyback's time to turn on is basically determined by the first dip in the voltage, right? And the time to turn off is based on the duty cycle needed, right?Quote from: T3sl4co1l on June 23, 2023, 02:53:29 amJust to get familiar with it a little I made my own calculations now: Putting 2 of those in parallel means 0.64W plus 0.55W, total of 1.19W. Not calculated are the gate charge losses here, they will double aswell. The SiRS5100DP has a lower RDSon but slightly higher Coss and Qg, calculations would be: 1.6nF at 80V are 5.12J, so 0.51W. RDSon of 2.5mΩ so 0.55W there, which brings it down to 1.06W. Gate charge is 102nC, so 510nJ=0.51uJ at 10V, so 0.05W. So 1.11W plus switching losses, looks pretty good to me.Quote from: T3sl4co1l on June 23, 2023, 02:53:29 amAnd I can do ZVS and ZCS, correct? So I could (theoretically) get away with only the 1.11W I calculated above on the FET? Plus core losses/inductor losses and so on when considering the entire converter. The actual operation frequency would then be dictated by the converter and I would have my controller "follow" it and do PWM on it to set the output current/voltage?Quote from: T3sl4co1l on June 23, 2023, 02:53:29 amI would need an interleaved design with a flyback anyways to reduce input current ripple. And I do have an AppNote with source code for an interleaved flyback converter, the efficiency is just not as good as I would like it to be and it is only for 200W. Can I reach the intended efficiency with a "normal" flyback without making it quasi-resonant? I think that would be a huge task?Quote from: T3sl4co1l on June 23, 2023, 02:53:29 amYes I am aware of that, it wouldn't be a problem but it's safer like this anyways. Also not having a huge DC-Storage at high voltage is something that I really like since it's not as easy to destroy the FETs by dumping in a too high currentIn this case the current is limited by how much the flyback can/does provide.Quote from: T3sl4co1l on June 23, 2023, 02:53:29 amI was planning on doing a test with a lightbulb and verifying on a scope that it is properly aligned with the grid and that it is indeed a proper sine coming out of it. If I can use code from the AppNote then I will have the anti islanding and phase tracking from a well-tested setup, so there shouldn't be any issues there.Thank you so much for your help and for kinda guiding me through this, your experience really helps me a lot as many things you told me aren't written in App Notes or research papers, they usually only say why their design is awesome and not where the downsides are, what can be improved and so on....

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 23, 2023, 07:09:12 pm
content: Quote from: ManniW on June 23, 2023, 05:02:44 pmPerhaps. Yes, QR can do "valley mode switching", more precisely any valley will do, which is one way in which frequency can be limited at light load. The other being burst mode operation (hysteretic control).On time is determined by power level. It's better not to think of it as PWM, because the frequency isn't fixed by an external oscillator.You could possibly run a UC3843 this way, (ab)using the RtCt pin to input the zero-crossing (as a pulse from a comparator, say). By clever choice of pulse amplitude, timing network and other things, I think one could make a reasonably complete burst mode / QR control that way. There are also just regular controllers purpose-made for it, of course (give or take further specialization; the attraction with old controllers like this is exactly their simplicity, being somewhat easier to bend their purpose, and much easier to understand overall).UC3843, just in normal operation, is worth understanding in great depth. Yes it produces PWM at fixed frequency, but that's not how it does it. And more importantly, that's notwhyit does it. PWM is the consequence of controlling inductor peak current. Limiting this currentwholly eliminates one mode of failure(switch overcurrent). Current mode control is extremely important for this reason alone. It's also important for separating the two dominant poles of the converter: this is more evident in buck mode, but boost/flyback has the same general behavior. By controlling inductor current directly, its state variable i_L(t) is separated from the output capacitor voltage v_o(t), and two control loops can deal with them independently. (More precisely, the loops are cascaded; but it's much easier to accommodate one loop of controlled behavior, within another loop, than to put both poles inside one loop directly, as in the voltage-mode control.)Put another way: current mode control enables loop bandwidth above 1 / (2 pi sqrt(Lsw Cout)). It's not just a safety feature, it performs better as well.QuoteQR/resonant with ZVS, yes.Note that LLC isn't very amenable to wide ranges of voltage ratios. It's probably out for the half-sine + polarity switcher you want.QR too; unless you have a way to force CCM, the valley voltage won't be very low, incurring some Eoss. This may be acceptable as the load is light near zero crossing.Oh, speaking of which, since this is an AC modulation thing -- note that it's actually an 800W peak design, with the output varying wildly from zero to 340V or whatever. Efficiency near full power (losses proportional to output) is strongly weighted in the total, but don't miss out on idle power (power dissipation while near zero output) either.Resonant topologies tend to have high idle power, if running in forced CCM. And you can't run too deeply in burst mode because those bursts are going right into the output -- either filter them, or they count against your THD+N or PF. And burst mode at say some ~kHz would need quite a sizable filter.QuoteWell, not HAVE to, the capacitors can simply be big enough to deal with it -- why, is left as an exercise for the student. But the size reduction going to 2-phase (or more) is often worth it. It's a practical more than academic motivation.QuoteOh dear...Consider: it will already be properly aligned, because it'll have a phase detector + PLL thing, and, maybe a relay to bridge it once it's in phase lock.If it's making its own waveform stand-alone, then it should match distortion, too. Maybe Vout is made as a follower of Vmains, something like that. (Notice a follower, at zero output, implies a synchronous converter: there has to be SOME way for energy to flow into/out of the output filter network, while going up and down.)And if it's not locked, it never, ever connects. This is an assertion: it must be verified and tested with code review and every combination of stimulus you can think of. (There may be standards for grid-tie inverters, I don't know, I haven't worked on one yet.)If it's not a stand-alone design, then the H-bridge might be polarity detecting only, and might even be open-circuit under adverse conditions (low line, island, etc.). Then you'renotgenerating a voltage with the converter, but simply sourcing some current into a variable (sine cusps) voltage load. This changes the control perspective significantly: you no longer need a nominal output impedance*, indeed it should be high.*A tracking inverter (or a kind of UPS, I suppose it could also be) would need a low enough impedance to, you know, meet output regulation requirements -- say within 5 or 10% of nominal Vout over 0-100% Iout -- while also being high enough that it doesn't just short-circuit (read: go into current limiting periodically) when it's being pulled around by the mains. And because mains voltage is typically distorted, it's not enough to track a sine VCO (or NCO / DDS or whatever) along with it, but you have to mimic the harmonics too. It'd be a huge PITA.I doubt the latter type actually exist, for grid-tie purposes, because of these issues; I would guess more likely is, they detect existing grid and current-source into it -- switching control mode (near-CC vs. near-CV output characteristic) based on configuration and status.Which is a highly nonlinear control scheme -- but realizing when and how to apply nonlinearities, is a key responsibility of system and control engineering.QuoteGood, you've already noticed a hint of it. In general, be critical of everything. App notes are hardly authoritative; even on their own domain / product specialization, they often makeMy favorite one to poke at is this,https://www.ti.com/lit/an/slpa010/slpa010.pdfthey claim to reduce the ringing of the system, but manifestly fail to grasp the variables in play; the "optimized" layout has room left to improve, and has basically no effect on the waveform. They apply an RC snubber but use incorrect expressions (it should be R = Zo = sqrt(L/C) and Cs >= 2.5 C) and don't show what value they measured in their circuit in the first place. Finally, they don't address ESL of the snubber itself -- the big problem with tight layouts like this is, anything you could hope to place around it has significantly more inductance than the thing you're trying to snub and therefore you get an inductor divider effect, greatly limiting the value of the snubber itself.The resolution? If layout literally can't be any better, then -- don't try! Don't be a damned fool about it. Run that one stage as fast as it reasonably can, without ringing, and then put in more. This is the other value of phase-interleave: you get a scalable design where all the phase legs deliver some controlled current to the common load point, and that's that.Put another way: you can't simply parallel transistors forever: as load impedance goes down and power output goes up, loop inductance will dominate (that is, sqrt(L_loop / Coss) will be higher than R_L). You can't put just one snubber in the circuit, rather you find you need one every couple of transistors, or even multiple per (so that their ESLs act in parallel, accounting for the snubber ESL mentioned above).Parallel transistors also suffer from transient current sharing, given by the stray inductance between them, and Rds(on), forming an L/R time constant. 5mΩ and 5nH is 1µs, a rather modest time scale compared to a typical 100kHz Fsw.So don't try. Make small tight converter stages, and connect those in parallel instead.Your impedances are quite modest (a few ohms input, ~100 ohms output) so this isn't a big deal here -- but it would be important say if your input was 10V or even less, or, consider the V_core supply on a PC motherboard, which is often made with a ton of phases (8, 10, even more these days) for these reasons.Tim

author: ManniW
author_rank: Contributor
timestamp: June 23, 2023, 10:15:31 pm
content: Quote from: T3sl4co1l on June 23, 2023, 07:09:12 pmThey do measure the inductor current with a current sense transformer aswell, both in the reference design and also in the actual inverter. In the reference design it seems to be for overcurrent protection aswell as "aligning" both flybacks as there apparently tend to be some slight differences in the current that are being compensated in software by slightly adjusting how they are switched. They use a DSP for control, which is what I am planning on doing aswell.Quote from: T3sl4co1l on June 23, 2023, 07:09:12 pmI kinda figured that out already.Quote from: T3sl4co1l on June 23, 2023, 07:09:12 pmBut apparently they are doing that in the commercial inverter. My schematics are basically the entire DC-DC converter (except for the current sense transformer), and if I can believe what the inverter is measuring and reporting the overall efficiency is always at 95%. Even at 4.2W there are just 0.2W loss, which is again 95%. I will verify the measurements though tomorrow, with such a simple design it simply looks too good to be true to me. Measuring voltage and current on the DC side is easy enough, and maybe that already shows a discrepancy between the inverters measurements and my measurement equipment.Quote from: T3sl4co1l on June 23, 2023, 07:09:12 pmThe transfomer can be designed for 400W though according to the AppNote, which makes sense as the primary peak current is set by the input current and can be artifically limited (it needs to be variable anyways for maximum power point tracking) and the rated power is apparently only for thermal purposes. I have contacted the manufacturer of the transformer to ask "why" there is a 100W limit on the transformer and they promised to check if that can be raised and what the actual limit is.Quote from: T3sl4co1l on June 23, 2023, 07:09:12 pmYeah, it makes sense to do it. The current into and out of the caps would be quite high, which will kill them quite fast. Also the caps and necessary filter will have additional losses and so on. For a solar inverter even a slight deviation from the wanted current would mean it leaves the maximum power point, and if it's oscillating around the target current it would be bad. Also at low input power one of the phases can be turned off, increasing efficiency .Quote from: T3sl4co1l on June 23, 2023, 07:09:12 pmI will have to verify that on my design though, and the lightbulb was the best idea I could come up with. I could connect the zero cross and voltage detector to mains and the output to the lightbulb I can verify on a scope if the PLL works properly. I don't want to have a mistake in my code and then the entire thing goes up in smoke on the first connection.Quote from: T3sl4co1l on June 23, 2023, 07:09:12 pmThere are, those standards specify frequency limits and voltage limits where the inverter is allowed to "connect". Also there are fault-ride-through cases that disallow disconnection when one of the patameters slightly goes out of range for a small time. It depends on the region, there is usually a "must stay connected", "may disconnect" and "must disconnect" for over/undervoltage and over/underfrequency for a certain time. So one second at 250V might be okay and the inverter must keep working, 10 seconds and it has to disconnect. That's (fortunately) out of scope for my inverter though, at least for now.Quote from: T3sl4co1l on June 23, 2023, 07:09:12 pmThere is a chinese design that has the H-Bridge connected with some resistors and diodes for automatically switching it properly. They only have to take care of generating the proper waveform then. The inverter I looked at and the AppNote control the H-Bridge from the DSP though, and I am planning on doing that aswell.Quote from: T3sl4co1l on June 23, 2023, 07:09:12 pmI found a design which I think should be superior to the one in the commercial inverter and the one in the AppNote. It features soft switching and an active clamp and is described athttps://www.mdpi.com/2076-3417/10/12/4220.Still it only reached about 90% efficiency. I verified the parameters of the FETs and they have a kinda high Coss and the design is for 110V so the output current is higher increasing loss on the rectifier diode, but I don't think that makes up 5% efficiency loss. Other than that FETs and Diodes look pretty good, could the low switching frequency of 20kHz be a reason for the low efficiency? Or maybe their transformer was not ideal (they don't describe in detail how it was built, which core was used and so on as far as I can see). They only did a single phase version though, which might lower the efficiency aswell. I believe they also picked the turn ratio wayy to high, as they reached peak voltage with a duty cycle of 0.325 already, shouldn't that be more like 0.5?They also have a mistake in their schematic I think, there is a P-Channel FET where a N-Channel FET should be.EDIT: I think I found a design that I will be going with, it is described athttp://studentsrepo.um.edu.my/8036/7/rasedul.pdfand I will be using the single stage version from that paper, with an efficiency of about 96-97% for a 250W converter over basically the entire operation range, but they are running it only at 110V AC. So my work will be bringing up the output power to 400W and the output voltage to 240-250V AC aswell, while keeping the losses as low as possible. In the paper it is already mentioned as "future work" that the inverter can be interleaved, so that should already solve the power issue and give me a total output power of 500W, more than sufficient and I will even avoid the less efficient area near 100% load.They use DCM and BCM in a hybrid mode to achieve optimal performance during the half-wave. In the design of their experimental prototype I already spotted room for optimization: The active clamp and main FET are the same type. According to TI and one of their AppNotes that is usually not a good idea as the Coss for the active clamp FET is unnecessarily high as a lower RDSon usually comes at the expense of a higher Coss and there is no need for a super low RDSon at that part as the current stress is significantly lower than on the main FET.