FPGA based Direct Digital Synthesis - Page 1
Forum section: electronics / general

author: knight
author_rank: Regular Contributor
timestamp: March 01, 2022, 08:12:49 am
content: Hello. I'm trying to generate a discrete-sine waveform using FPGA and then convert it to analog using a DAC and filter. I want to know how can I take the output from the FPGA I/O. The simulation works fine but it is parallel data for example sine[7:0]. I want to take it as a single output to give it to a DAC. Can anyone give any idea?

author: knight
author_rank: Regular Contributor
timestamp: March 01, 2022, 09:37:51 am
content: I got badly confused so sorry. Of course a DAC will have n-bit digital input, my bad. Actually, I don't have the target FPGA board yet so I just ran a power analysis in Xilinx Vivado. I was shocked to see that I/O consumes 7W of power! Now, I don't know if that is accurate as it was just software estimation. Hence, I thought to convert parallel data to serial but I was wrong.Can you tell me why such a simple implementation is consuming so much power? I don't understand. Thank You/

author: Someone
author_rank: Super Contributor
timestamp: March 01, 2022, 10:09:22 am
content: Quote from: knight on March 01, 2022, 09:37:51 amRead the power reporting, it breaks that down into the specifics. But in general something is very misleading/wrong in that figure, a dozen gigabit serdes wouldn't use 7W of power, and that would be driving a 10GS/s DAC.

author: knight
author_rank: Regular Contributor
timestamp: March 01, 2022, 03:56:55 pm
content: Thank you for the reply guys. Greatly appreciate it. I have attached the screenshots of the power breakdown and the power report text file. I don't understand what is going on. I think you will understand it.

author: Bassman59
author_rank: Super Contributor
timestamp: March 01, 2022, 04:04:45 pm
content: We need to see the entire report for the 1.8V rail.

author: nctnico
author_rank: Super Contributor
timestamp: March 01, 2022, 04:07:40 pm
content: Likely a constraint is wrong (frequency way too high) or something is self-oscillating -according to the power estimator- causing an excessive power prediction.The text file doesn't list any clock constraints which is a red flag.Please show us the place & route report which includes which timing constraints are applied to the design.

author: hamster_nz
author_rank: Super Contributor
timestamp: March 02, 2022, 07:11:35 am
content: You may know this already, but if you have a signal in Vivado's simulator you can right-click on it, and change it's "waveform style" to "analog". This might save you needing a DAC at all! (see attached picture)Excessive power will be due to not having a clock constraint. To add one, add an 'XDC' file to your project and add a line like this:Code:create_clock -add -name sys_clk_pin -period 10.0 -waveform {0 5.0} [get_ports clk]That adds a 100MHz clock to the pin called 'clk'. Just change the period (in nanoseconds) to be what you want.If your DAC needs are modest, you can implement a single bit DAC using just a pin!Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity easy_dac isPort ( clk : in STD_LOGIC;d_in : in STD_LOGIC_VECTOR(7 downto 0);pulses_out : out STD_LOGIC);end easy_dac;architecture Behavioral of easy_dac issignal total : unsigned(8 downto 0) := (others => '0');beginpulses_out <= total(8);process(clk)beginif rising_edge(clk) thentotal <= ("0"&total(7 downto 0)) + unsigned(d_in);end if;end process;end Behavioral;When d_in is 0x20, pulses_out will have a duty cycle of 32/256, at about 1/8th the clock speedWhen d_in is 0x80, pulses_out will have a duty cycle of 128/256 at about 1/2th the clock speedFollow it up with a simple low pass filter (a 200 ohm series resistor followed with an appropriately sized capacitor) and you have your DAC.

author: hamster_nz
author_rank: Super Contributor
timestamp: March 02, 2022, 07:16:27 am
content: PS. Oh, and ask how I'm calculating sin() and cos() from that phase value in that screen shot. I'ld love to show you another really neat FPGA thing...(https://xkcd.com/1053/)

author: knight
author_rank: Regular Contributor
timestamp: March 02, 2022, 07:17:10 am
content: I forgot to write the constraints file. So, I specified the input clock, reset and the output sine on GPIO of FPGA and the power went down to 127mW. I think it is possible to bring down the power under 100mW or maybe even less by efficient implementation. Thank you all of you.

author: hamster_nz
author_rank: Super Contributor
timestamp: March 02, 2022, 07:21:30 am
content: Quote from: knight on March 02, 2022, 07:17:10 amFPGAs have pretty high power draw even when doing nothing - there is a lot of idle logic leaking electrons.Even if your design doesn't use much power, the will use quite a bit at startup as the load the bitstream.If you care about power, then FPGAs are not the solution you are looking for.

author: fourfathom
author_rank: Super Contributor
timestamp: March 02, 2022, 07:39:21 am
content: Quote from: hamster_nz on March 02, 2022, 07:21:30 amWell that depends, doesn't it?

author: nctnico
author_rank: Super Contributor
timestamp: March 02, 2022, 11:52:13 am
content: Quote from: hamster_nz on March 02, 2022, 07:21:30 amMaybe not the Xilinx device the OP is using but I think there are FPGAs out there which target low power circuits that might be better suited.Recently I used a Gowin GW1N-1 FPGA in a design (clocked at 25MHz). The power estimator says the total power consumption is 13mW. When I increase the clock frequency to 100MHz, the dissipation goes up to 31mW.

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 02, 2022, 06:17:25 pm
content: Quote from: hamster_nz on March 02, 2022, 07:21:30 amIn general yes, but I don't think the OP really defined the max sampling frequency? If it's moderate, small FPGAs, such as in the iCE40 series, could be used, and power much under 100 mW can definitely be easily achieved. Of course, if you want to implement says 500 Msps DDS, you'll need something much beefier and the 100 mW will be hard to meet.

author: Someone
author_rank: Super Contributor
timestamp: March 02, 2022, 08:51:02 pm
content: Quote from: hamster_nz on March 02, 2022, 07:21:30 amPretty broad and poor generalization, more typically for power efficiency:"software solution" < bare metal on general purpose CPU < GPU/FPGA < ASICwhile the implementation effort is almost exactly the reverse of that ordering! Accelerators in CPUs/GPUs move out into the GPU/ASIC region, if they do the task you need.

author: BrianHG
author_rank: Super Contributor
timestamp: March 03, 2022, 02:41:18 am
content: With a typical 250Mhz DDS running on Altera's Cyclone IV or MAX10 FPGAs, properly written, the entire FPGA should operate within <1 watt. However, these FPGAs arent the fastest things out there, but for simple comm/audio/video apps, they can fit the bill. Low power Cyclone10's are slower, but, you can expect less than 0.5watts for the same specs.

author: hamster_nz
author_rank: Super Contributor
timestamp: March 03, 2022, 10:55:14 am
content: Quote from: BrianHG on March 03, 2022, 02:41:18 amGlancing at the AD9913 datasheet... 250MS/s with integrated 10-bit DAC, and less 100mW.Of course it isn't as flexible as an FPGA based solution, but who knows, maybe the OP only needs a basic DDS?

author: BrianHG
author_rank: Super Contributor
timestamp: March 03, 2022, 12:27:08 pm
content: Quote from: hamster_nz on March 03, 2022, 10:55:14 amThe numbers I specked are approximations based on past experience with altera parts. They include the use of 2 PLLs and some small additional sub-systems. You will not beat a dedicated DDS capable IC in power consumption with an FPGA, but, under 1 watt isn't terrible unless you have a battery powered app. The original Xilinx 7w just for the IOs sounds wrong, but I do know that Xilinx tends to run hot while many of my Alter apps run at room temp without any heatsink needed. Though, Xilinx can be made to run twice as fast.