Push-pull transformer imbalance, one mosfet gets hot the other very cool. - Page 1
Forum section: electronics / projects

author: jamhough22
author_rank: Newbie
timestamp: February 27, 2021, 05:29:42 pm
content: I am in the process of designing a push-pull boost converter, currently testing on breadboard. To boost 12v to 65v dc around 300w but im having issues with an imbalance on the mosfets, at around 50w input power one mosfet gets too hot to touch while the other stays cool, the core heats up, and the output voltage starts to drop, the duty cycle maxes out which is what i would guess is also the problem.The best frequency i have so far is 40KHz any higher and the power transfer is greatly reduced (and the duty cycle maxes out sooner). (Haven’t tried to lower the frequency any further than this) I have a sufficient dead time as i have seen on my oscilloscope. The output peak to peak after the filter is around 10-15mv under this load (perfect) which is where the voltage feedback is coming from.I have attached a schematic -For the purpose of testing the amount of input/output filtering caps has been reduced.The input overcurrent has not meen implemented yet nor has the snubber networks.The soft start circuit works very well. I have ran this project from a battery (after testing with a current limited supply).The mosfet gate resistors are currently 10 ohms, this keeps the switching speed high but stops them from overshooting / ringing.I am running this in single rail mode (see R1-3 below transformer / rectifier in schematic) so none of the -ve rail is in use.I have 2 + 2 turns on the primary and 8 + 8 turns on the secondary. The flux density is calculated at 0.24T The core is a ETD44 N87. The bobbin is wound primary 1 - secondary 1 - secondary 2 - primary 2Each primary has 44x 0.4mm diameter wire Each secondary has 8x 0.4mm diameter wire.Both mosfets see the same high peak voltage (which I’m having trouble keeping down) of about 90vThe core losses should only be around 2W, but appears to me more than this.I have also tested the leakage inductance from each primary and shorting the three secondary terminals (centre tapped) in different configurations at 10 and 100KHz, 1.4-1.5uH for primary 1 and 1.5-1.6uH for primary 2. Both primaries have a inductance of 24uH.* Is this leakage too high?* What is causing the imbalance and causing one mosfet to get too hot?* How can i reduce the high peak voltages without adding a snubber (yet)?I am planning to add a cycle by cycle current limit to the input in the future (it is in the schematic) but i need to get this side of things sorted before hand. Im getting tired of winding transformers in different configurations as they take soo long and its murder on the hands. Any tips on how i can proceed further?Thanks.

author: julian1
author_rank: Frequent Contributor
timestamp: February 27, 2021, 06:09:18 pm
content: Consider trying to bodge in current-sense resistors under the mosfets (source to gnd). You can then probe the current ramp on each fet. And check whether the transformer is drifting into core saturation.

author: Benta
author_rank: Super Contributor
timestamp: February 27, 2021, 07:02:32 pm
content: What you're seeing is most probably what we used to call "B walking" and is very common in this topology.Even though the MOSFET switching times are almost 100% equal, and their voltage drops as well, a small imbalance will cause aDCB-field in the transformer (which should ideally be 0) to wander in one direction, at the end causing core saturation. The saturation only occurs to one side.A very simple solution is to place a suitable capacitor in series between your VCC and the primary center tap of your transformer. This will result in a small DC shift that will balance out the asymmetry.In this case (without calculating it), I'd guess 2...5 uF with good high frequency properties, eg, polycarbonate.Royer converters don't have this problem, as the transformer is fully saturated on both cycles.

author: jamhough22
author_rank: Newbie
timestamp: February 27, 2021, 08:56:14 pm
content: Thanks for your speedy reply.It makes sense that the core is drifting into saturation on one side. After some (more) research, there are other ways to combat this drift, most of which are using transistors and suggest MOSFETs instead(the idea being the raising of the temprature would rais the RDSon and provide negative feedback to correct itself) other ways would be to gap the core (no idea on how one would calculate this) add some series resistance between the MOSFETS and the primary windings (more heat losses) or current control.I am however, intrigued by your suggestion, that is, your idea is to break the supply to the centre tap with a capacitor if i understand correctly?? or am i missing something?

author: schmitt trigger
author_rank: Super Contributor
timestamp: February 27, 2021, 09:12:51 pm
content: Many moons ago, there was a lengthy discussion on the DIYAudio forum:https://www.diyaudio.com/forums/power-supplies/53604-staircase-saturation-push-pull-smps.html

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 27, 2021, 09:43:35 pm
content: Oh god, wrong output filtering, no current control, and what is this feedback network?Alright, seriously though --The most immediate problem is probably that it's running saturated, the error amp that is -- giving full throttle (near 100% duty), and that's leaving no time for the transformer to demagnetize between pulses. So a small imbalance in timing causes a large imbalance in flux.This will be fixed with current mode operation, output choke-input rectifier, and probably a somewhat higher turns ratio to get regulation at a modest duty cycle, say 60-80% (i.e. 30-40% per gate).The filtering is easy to fix, just rip out C23, C42, etc. Possibly increase the 100uH's (and make sure they can handle the ripple), whatever to get reasonable response.Current mode operation is a little trickier. It can be done with the current sense amp, moved to the transformer CT. It's somewhat more traditionally, I guess, done with a shunt resistor in Q1+Q2 source. (Use several in parallel to keep inductance down!) Either way, this doesn't measure the inductor current, it's chopped by the duty cycle. It's only reading the on-state current. So it's an imperfect measure of actual output current flow. As long as duty cycle stays in the nominal range, this is okay, and you can feed back this signal to the error amp to regulate current, and add an external error amp to regulate voltage (which should become a TL431 on the secondary side, which is needed anyway for stable regulation -- handy).Now, with that, under fault or startup conditions, the low duty cycle will read a far lower average than the actual inductor current is, so you might consider some kind of peak-detect reading as well. You probably don't want a straight up peak reading to begin with, as turn-on transients will dominate the signal, and the nonlinearity and ugly time dependence of the response, make control very challenging -- most often, such schemes oscillate chaotically (emitting an angry hissing sound).A surprisingly attractive alternative: use a Hall effect sensor to measure the output inductor current directly (say just to the left of R6). Note this only works well, when there's one dominant output. Having the split output is a bit troubling. You could use two and sum their outputs.You could also use a separate inverting (buck-boost or other) converter, instead of the... linear regulator? for the negative output. I guess with that being enough, it's not too much power, so it's not like it would be a huge waste of space using a converter instead; it'll probably be smaller than the heatsink is. Just a bit of bother, putting in yet another stage.Some comments on transformer design.As you've noticed, it's not enough to toss some wire on a bobbin and hit it. I'm guessing your turns are just spread loosely about, no particular pairing or anything? (Gosh, 1.5uH, that's a ton, even for two turns of wire in air alone, no shorted secondary nearby. Are you sure?!)The trick here, will be interleaving the windings, and with so few turns, it'll be by using many in parallel.You can do this by making just, twisted sets of wires, including all the turns needed in one cable, then making series and parallel connections between wires, to get the desired primary and secondary turns and bulk. For 2+2:8+8 turns, that might look like:Make two turns of the cable around the core.Cable: 16 wires. Let the wires be numbered 0, 1, 2, ..., D, E, F.Connect 0, 1, 2 and 3 in parallel. Connect 4, 5, 6 and 7 in parallel. Connect 0123 and 4567 in series: this is your primary winding, 2+2 turns.Connect 8, 9, A and B in series. Connect C, D, E and F in series. Connect 89AB and CDEF in series: this is your secondary winding, 8+8 turns.Obviously, preserving polarity. Whenever connecting wires in series, connect start to end, start to end. In parallel, always start to start, end to end.Upsides to this construction: reasonably tight coupling between primary and secondary, and P/P and S/S halves; uses all the same wire; scales up easily (just repeat the same assembly, N times in parallel, to get the desired ampacity, or leakage inductance).Downsides: tedious, it's a lot of twisting, and sorting out wire ends, and tacking all the ends together, and doing it all over again for each unit.....Leakage inductance, by the way, will be simply the stray inductance of the wires, with respect to each other, in the cable as such. This is a transmission line transformer, so transmission line theory holds, and a property of TLs, at low frequencies and impedances, is inductance proportional to length. (It's also dependent on cross section, there's a geometry factor in there -- it varies with the relative size/spacing of wires in the cable, and which ones (P1/P2/S1/S2) are paired up together. Notice, it does NOT depend on the cross sectionalwidth-- you get identical inductance from tiny wire-wrap wire, or big fat mains wire, as long as the ratio of wire to insulation diameter is the same.) Since this will only need, what, <150mm of cable length per unit, and the inductivity will be around 0.6 uH/m, expect leakage around 90nH,divided by the number of units in parallel.Evidently, what you have now, is much worse than this -- so, you stand to benefit already just from putting all the wires in about the same place together, overlapping or whatever. But you benefit even more by getting even broader overlap, in the above case from simply using a lot of individual wires twisted together.For a method with a bit less work, consider copper foil. Laid flat, with wire or foil wound on top, this achieves quite good interleave. Prioritize interleaving the winding halves (P1 and P2, S1 and S2). The best you can get here, is probably making two foil windings on top of each other, same place, separate layers -- as they're both foil, they sit very close together, so there isn't much penalty from them being on their own layer. Put secondary on top of that, paired S1+S2 as usual, and continue alternating until you have enough ampacity. Insulate with tape between layers, of course. An annoyance of foils: hard to connect, you have to fold some over (or even splice it) to get an edgewise bend. It may help to make connections into the winding, by soldering a stout piece of wire between PC pins and foil ends.Or for a bit of a hybrid method, consider approximating a ribbon or foil, by winding a bunch of strands of enameled wire in parallel, laying flat. Make a single layer, the full width of the bobbin, and call this primary (or one section of it, anyway). This makes a conductor very much like foil, but you can actually bend it around corners (edgewise), it's flexible strands, yay! Downside, tricky to wrangle all the wires at once, still kind of a lot of soldering I suppose. Use tape to your advantage, hold wires in place, or even wrap up a bundle so you can use it like a single cable without worrying about individual strands. And again, do interleave the primary halves, and secondary halves, as well as you can -- you can assign half the strands in a given layer to either half of the winding, and wire them up in parallel-series like the cable construction from before. Preferably they should alternate (P1, P2, P1, P2, ...), but grouped (P1, P1, P1, P1; P2, ...) is still better than putting halves on separate layers.Tape is quite available; I would recommend polyester (in classic yellow of course),https://www.digikey.com/en/products/detail/3m/56-YELLOW-1-2-X72YD/1819325or polyimide,https://www.digikey.com/en/products/detail/3m/92-AMBER-1-2-X36YD/1630230Or polyimide with an acrylic adhesive, which is a bit tackier (and more tolerant of handling i.e. skin oils) than the silicone variety. I like the silicone type for its sheer badassery: it behaves 100% normal under soldering heat, doesn't move, doesn't blister, doesn't burn. Great for hacking and prototyping.Tim

author: Benta
author_rank: Super Contributor
timestamp: February 28, 2021, 01:18:03 am
content: Deleted

author: jamhough22
author_rank: Newbie
timestamp: February 28, 2021, 03:16:07 pm
content: Thank you Tim for that worthy post! this will help me out vastly.I will concentrate on the transformer design first and look at the other solutions afterwards, the idea of the foil is a great idea. It should make my life easier. Im thinking on having some 30mm wide x 0.05mm foil and trim down the centre to create 10mm tabs at each end, the winding width will be 20mm (effectively 1mm²), this will leave a good amount of width left on the bobbin to make series/paralel connections with the tabs at the edge of the bobbin, i will of course add some tape on each winding (not to short itself and other windings) and overlap each winding to create just over a full turn (say ~2.2 turns for the primaries and 1.2 for the secondaries). This is tedious but will help with the bending or soldering to each foil layer, but thin enough to cut easily.-My theory of interleaving to get the best coupling between primaries and both secondaries equaly, and reducing the leakage inductance and the magnetic field strength distribution swing would be to seperate into 8 banks and layer them as follows:P1 P2 S1 S2 P1 P2 S2 S1I have shown only 2 banks, i plan to make 8 banks total, again primaries in paralel, secondaries in series.Im not sure whether it is a good idea or not to alternate the secondaries to get the best coupling from each primary to each secondary?I have attached a picture of my design so far, i think this process takes longer but with each tape layer will make it much easier to make the transformer as a whole. The attached picture shows my calculations/layers/single winding example, current handling etc..By doing this there shouldnt be quite such a swing in the field strength which will help with saturation? My understanding is that by coupling the primaries on top of each other will reduce the voltage spike on the MOSFETS and interleaving will maximise the coupling primary to secondary and reduce leakage inductance and therefore overall efficienty.James.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 28, 2021, 04:26:57 pm
content: ExcellentNote you can do P-S-S-P, i.e. double up the middle layer, since it's surrounded by primary. Odd section counts perform a little bit better. Balance their dimensions: for example PSPSP might have half P in the middle, half and half S around that, and 1/4 P on the top and bottom.This might not be all that feasible or relevant with foil; even section count is still fine. Works best I suppose, when the sections are multilayer, as you might need for a high impedance transformer. (These techniques are common in tube amplifier transformers -- wide (audio) bandwidth is required, with high impedances, at least on the primary (ca. 5kΩ). They can be useful in HV SMPS as well, though the approach there tends to be towards resonant drive instead.)The improved transformer may help with flux balance, not sure. I strongly urge doing the other improvements as well.One factor actually works against you, without the other improvements that is: in the "charge pump" configuration (C-input filter, no series inductance in the switching loop), current is limited at low duty cycles, specifically by leakage inductance. That is, for short pulses, say the transistor turns on for 1us, the secondary side is clamped by a capacitor near zero volts (during startup or fault conditions), so the 12V is dropped across the 1.4uH leakage. In 1us, current builds to 8.6A, and so on. If the output voltage is rising while PWM is rising, the peak current can be limited to a modest range. (If P1/P2 coupling is good, this energy is returned to the supply via opposite side body diode. If not, it's burned in the RC snubbers, or avalanche in the transistors*.)Whereas with a very good performing transformer, even for a narrow 100ns pulse, with say 50nH of leakage, you've already got 24A peak. That's either going to charge the output capacitors in one hell of a hurry... or blow out the transistors in the process. (The soft-starter Q3 has the same issue, drawn out over milliseconds; if load current happens to start up before it's fully turned on, it's not going to last long.)So, a choke-input filter becomes mandatory. And then, current mode control is strongly suggested, for stability and protection.*I strongly recommend avoiding repetitive avalanche operation. It's a wear mechanism, only so much charge can be absorbed before the transistor fails completely. Single-pulse ratings are often given, but that's the catch, it's a one-time test, and they mean it. It can be acceptable to use this parameter in an emergency situation (say, opening an electronic fuse that, under normal conditions, never needs to open), but it's a strict lifetime limit if repetitive. Probably something like a, solenoid driver say, would be marginal; a switching converter, forget about it. Also, some types don't have avalanche ratings at all (current GaN FETs, IGBTs), so avoidance or additional protection is mandatory for them. Which is kinda to say: it's not just best practice to avoid it, but for reliability, it's pretty much the only practice!Tim

author: Medved
author_rank: Contributor
timestamp: March 09, 2021, 08:02:35 pm
content: I see there two possible problems:- DC bias of the core, leading to saturation. Inserting the gap, so reducing the main inductance may create enough magnetization current to maintain the DC operating point of the core (the average value of the magnetization) around zero by creating sufficient voltage drop across all the resistances. Otherwise you would need some core saturation detection circuit (detecting the knees of the primary current and comparing one halfwave with other), generating a correction imbalance into the driver timing so the sensed current remains symmetrical (way more complex, but low loss, so usable for really high power). Actually combining both could be the way to go: Add a gap into the core so about 5..10% of the normal load current flows as the primary magnetization current, design the transformer so the flux is below 50% of the saturation with symmetrical drive, then sampling the drop across the FETs while ON and comparing one with the other and regulate the imbalance so you get zero difference.Alternatively (if possible) keeping ~10% gap between both MOSFET conduction, when no current flows through any winding (so all diodes are off, so e.g. no inductive filter after rectifiers, so limited only to nonregulated converters), there the transformer will dictate what voltage will be there so it will tend to reset the magnetic field to zero. But not usable, when there is something constricting the voltage in the circuit, like e.g. inductor input filter after a rectifier or so.- Inductive overshoots on the drains due to leakage inductance between both primary sections. Make sure the primary is really wound as bifilar, plus use decent snubbers.