Looking for transistor-based 32kHz quartz test circuit - Page 1
Forum section: electronics / projects

author: VinzC
author_rank: Frequent Contributor
timestamp: September 23, 2024, 04:39:01 pm
content: Hi all.I must be completely dumb in that regard but I've been trying, in vain, to make a test circuit for my salvaged 32.768 kHz quartz crystals. Every single setup I try is just a masterful failure. Absolutely none of my attempts worked. None. The only way I could test these is with a CD4060 (or HEF4060, same thing). I could however test all my other crystals, of a few megahertz so its not completely hopeless.Lately I came acrossthis videobut, again, in vain. I tried a few resistors at the emitter, ranging from 12k to 47k, no friggin' way that damn thing would oscillate. I even waited about one minute (after powering it up, of course) as hinted in that video... nothing. I breadboarded the test circuit, which must not be worse than that used in the video. At least I hoped... Doesn't change anything.I must admit I probed the collector directly without the buffer stage, as well as through a 100pF (measured) capacitor between the collector and the scope probe in x10 position. Regardless this thing drives me nuts, really.Is it me or is such a struggle expected with those watch crystals? Is there any such test circuit at all?Thanks in advance.

author: Benta
author_rank: Super Contributor
timestamp: September 23, 2024, 05:26:59 pm
content: 32 kHz crystals are extremely sensitive to overdriving. Power limit is usually around 1 uW (yes, that's microwatt!).I suggest you use a 74LVC1GX04, it's made for the job.The crystal needs a series resistor to limit power, usually 500k...1Mohm.Two load capacitances are common, 12 pF and 7 pF.

author: VinzC
author_rank: Frequent Contributor
timestamp: September 23, 2024, 05:38:21 pm
content: Quote from: Benta on September 23, 2024, 05:26:59 pmYup, I know that indeed. But before being overdriven, it should start oscillating, right?Quote from: Benta on September 23, 2024, 05:26:59 pmWell, my 4060 implementation already uses current limiting and it works a treat. What I'd like to know is if there are transistor-based test circuits for those quartz.Here's the schematic from the video:How good is it?

author: RoGeorge
author_rank: Super Contributor
timestamp: September 23, 2024, 06:00:44 pm
content: Try this one:https://pdfserv.maximintegrated.com/en/an/AN982.pdfThe MAX931 is used to buffer the output of the transistor, a nice to have but not really needed for a test. Instead of Vref, I would use 2 series diode with a resistor, or just a red LED. Vref can be any 1.2V source, even a simple resistor divider should work.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: September 23, 2024, 07:48:21 pm
content: Quote from: VinzC on September 23, 2024, 04:39:01 pmThey can be fussy. I played with these a while ago, on Spice.eg this link is a starting pointhttps://www.zl2pd.com/xtalRefOsc.htmlbut you can see my notes, it needed some tuning.1M or 2M2 is a bit small for a parallel resistor, across the crystal, and some additional phase shift helps lower the start time and lower the Icc.Then I located a better starting point, using a NPN/PNP pair with a biasing scheme that has natural agchttps://www.radiolocman.com/shem/schematics.html?di=105602that used very old parts, but it works fine with a modern SMD single package transistor pair.It can be tuned for choices of Icc(run) and startup times. This circuit gives good output swings for low Icc.

author: ledtester
author_rank: Super Contributor
timestamp: September 23, 2024, 11:02:39 pm
content: You could try this circuit...http://www.discovercircuits.com/DJ-Circuits/ultralowpwrxtlosc1.htmClaimed current draw from a 3V battery is around a microamp.

author: Benta
author_rank: Super Contributor
timestamp: September 23, 2024, 11:34:57 pm
content: "Then I located a better starting point, using a NPN/PNP pair with a biasing scheme that has natural agc"So how is that different from a CMOS inverter (like the 74LVC1GX04)?And what does R9 do? Very odd.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: September 24, 2024, 12:03:18 am
content: Quote from: Benta on September 23, 2024, 11:34:57 pmIt is quite different, as the C3 is not present in 74LVC1GX04.The base-emitter junctions + C3 act as DC restoration diodes in the NPN/PNP pair and reduce the current, once oscillation starts.A 74LVC1GX04 CMOS inverter has a soft peak current, that relies on enough amplitude to slightly reduce the current once oscillation starts.Quote from: Benta on September 23, 2024, 11:34:57 pmThat's just a place keeper for a resistor fed variant. Reminds me what I tested.

author: VinzC
author_rank: Frequent Contributor
timestamp: September 24, 2024, 08:28:18 am
content: Thank you very much for all your suggestions. There are a few of these which I tested but I might have been not rigorous enough, so I'll try test them again and report here about my findingsQuote from: PCB.Wiz on September 23, 2024, 07:48:21 pmFrom what I see you went from an asymmetric stage to a push-pull stage, in order to make an inverter with two transistors, is that correct?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: September 24, 2024, 06:32:30 pm
content: Quote from: VinzC on September 24, 2024, 08:28:18 amYes, it is push pull, but there is more happening.The dampening effect of the collector resistor is gone, and the C3 gives automatic gain control, as the signal builds, the collector current drops.

author: VinzC
author_rank: Frequent Contributor
timestamp: September 25, 2024, 04:32:12 pm
content: Quote from: VinzC on September 24, 2024, 08:28:18 amQuote from: PCB.Wiz on September 24, 2024, 06:32:30 pmI'm quite sure I understand (almost) none of this, would you mind detailing this explanation? I'm extremely curious as to the problem you solved in the first place¹ and what gave you the idea to solve it.¹ At first I'd risk saying startup time is a concern, or maybe the sustainability of the amplitude...?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: September 25, 2024, 06:33:48 pm
content: Quote from: VinzC on September 25, 2024, 04:32:12 pmMeasure one, or sim it? Check the icc pre and post startup.I was looking for lowest power, Vcc tolerant with good output swing osc.A challenge to find a discrete ckt that was ‘almost as good’ as the dedicated oscillator chips.The circuit is not mine, I found it in the link I gave and I tuned it.It’s nifty in how it works, starts well, reduces icc as amplitude increases and has symmetric output.The base-base cap that makes this all work nicely, is not practical to integrate so it is a discrete only design, that you would use a SMD transistor pair to build.

author: ivo
author_rank: Regular Contributor
timestamp: September 27, 2024, 09:46:02 am
content: I made one using a standard Schmidt trigger 74hc14 pierce oscillator circuit. You just need to up the resistor values. 10M across the crystal, and 330k in series with it. 22pf load caps either side, and can use another Schmidt gate to buffer the signal. Was working with 3.3V and 5V.

author: NightMoth
author_rank: Contributor
timestamp: September 27, 2024, 01:02:18 pm
content: Hello,Sharing two my 32.768kHz transistor oscillators (+5V supply) i built few weeks ago, maybe it will be useful1)With Schmitt trigger2)Also my previous simplier one (only two BJTs) discussed herehttps://www.edaboard.com/threads/crystal-oscillator-circuit-based-on-bjts-in-collector-feedback-configuration-questions.411792/

author: VinzC
author_rank: Frequent Contributor
timestamp: September 27, 2024, 03:15:59 pm
content: Quote from: NightMoth on September 27, 2024, 01:02:18 pmWow, thanks a lot for sharing! That's interesting indeed. Out of curiosity, why the double buffering stage with Q3/Q4 ?I'm also wondering why the series capacitor C6 as I don't perceive it as the recommended load capacitor¹... unless I've missed something, of course.¹ which typically is mounted in parallel across the crystal to decrease the parallel resonant frequency, if I'm not mistaken.

author: jwet
author_rank: Frequent Contributor
timestamp: September 27, 2024, 09:06:07 pm
content: I wrote that Maxim app note many moons ago! Its a good circuit, not too finnicky. I was trying to keep current down and operate over a wide range for some customer's requirement- an odd notebook computer requirment. As rogeoge said, the ref and comparator can be sub'ed or eliminated- it won't drive much load- what C. The transistor should be something hot at ultra low currents like a 2N5088. The other magic here is that the input Z of the transistor is bootstrapped up to a high value.

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: September 28, 2024, 02:53:46 pm
content: Quote from: VinzC on September 23, 2024, 04:39:01 pmSome time ago I did a test oscillator for testing 32.768, 38.000 and 77.500 khz xtals (can and small can type). It was the single bjt type in common emitter setup. I couldn't make It work until i dropped the collector resistor from 10K to 1K. Modern BJTs have so much high HFE so that the smallest current going through the base-emitter keeps the transistor turned on forever.

author: NightMoth
author_rank: Contributor
timestamp: September 28, 2024, 03:23:26 pm
content: Quote from: VinzC on September 27, 2024, 03:15:59 pmHelloAll I know about loading capacitors I red from great technical notes #32 and #33 from Statekhttps://statek.com/technical-papers/According to my understanding, capacitors usually mounted across the crystal in Pierce oscillators or in other "parallel" configurations.but it also can be mounted in series as my C6.Main purpose of loading capacitors is to cancel crystall's reactance (so only crystal resistance left) and set phase shift made by crystal to zero at desired operational frequency. And if loading capacitance is not precise, actual operational frequency of a crystal will be somewere between series and parallel resonance frequencies.I'm avare that Pierce oscillator have much more tolerance to load capacitances, so it is better than my series oscillator, but I wanted to build my own "from scratch" and see whether it will work.As for double buffering: I wanted to isolate C5/C7 capacitors from C6. I'm not sure is it really was necessary, but when I drew AC model it looks so.Here is AC model of my oscillator I use to analyse it: C6 cancels reactance of the Crystal.Total shift in the loop is 359 deg, A*Beta>1:UPD:I just realised potential problem with my oscillator:Specified Crystall's drive level is 1uW, but it looks like my circuit drives it with ~6uW power.If Q2amp's Vout is 5Vpp, Q4amp's out is 0.95*0.46*0.76*1*5Vpp = 1.66Vpp or 0.6VrmsCurrent through crystall will be ~= 10uArmsSo dissipated by Crystal's resistance is about 6uW.Need to increace Q1amp's impedance and/or decrease feddback Beta...