5V CPLD , in DIP if you like.. Microchip CLB peripherals - Page 1
Forum section: electronics / general

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: June 05, 2025, 03:24:41 pm
content: I've just started looking at the Microchip PICs with their configurable logic block (CLB) peripherals for a new job.Seems this fills a nice little niche that most other CPLDs don't, especially in terms of wide supply voltage and low pin counts.Although it's a peripheral, the CLB can be treated as a CPLD with a free MCU, which after doing the config loading, you can ignore if not needed.4 inputs ( + another 4 via the CLCs, and anything you can sneak through any other peripherals) , 8 outputs ( again scope for more via CLC) , 32 logic blocks (comprising 4-input LUT and latch) plus a dedicated 3 bit 1-of 8 counter.Multiple oscillators available from the PIC, plus all the PIC peripherals & memory. 16MHz sync clock rate, 100MHz async switching rate. 1.8-5.5v supply & IO. Packages from 8 pins (DFN/SO/DIP) to 20 (SSO/SO/DIP).Pretty cheap - $0.50 -$1.50 1-offSchematic or Verilog design entry - including an offline and online version of the tools, that produces C source code to add to a project.https://www.microchip.com/en-us/products/microcontrollers/8-bit-mcus/peripherals/system-flexibility/clb

author: djsb
author_rank: Super Contributor
timestamp: June 05, 2025, 04:29:35 pm
content: Which one do you use the most? Thanks.

author: woofy
author_rank: Frequent Contributor
timestamp: June 05, 2025, 05:09:43 pm
content: It's a great idea. I bought some PIC16F13145's a while back to test out.Unfortunately I wasn't too impressed. I tried to write some verilog but there were very few examples at the time and I couldn't see how to define and use a clk, ie.Code:always @ (posedge myClk) beginAlso it gave very poor error messages, such as "insufficient resources to route design" (from memory, but that was the gist of it).I ran out of playtime for it and gave up, perhaps its better now.Keep us updated on your progress with it, maybe I'll have another go.Edit to add:I did try the schematic too, but it was just to tedious, and still gave the cryptic routing messages.

author: Andy Watson
author_rank: Super Contributor
timestamp: June 05, 2025, 05:17:28 pm
content: Quote from: mikeselectricstuff on June 05, 2025, 03:24:41 pmIs the datasheet really password protected or is my viewer too old to cope?

author: woofy
author_rank: Frequent Contributor
timestamp: June 05, 2025, 05:23:02 pm
content: Downloads fine for me.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: June 05, 2025, 06:45:10 pm
content: Quote from: djsb on June 05, 2025, 04:29:35 pmThey're basically all the same chip, but with different pin count & memory. My application will be targetting the 8-pin one, but using the 20 pin for development so I can output lots of debug signals.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 06, 2025, 04:05:40 am
content: Quote from: mikeselectricstuff on June 05, 2025, 03:24:41 pmOne PLD benckmark I recall was a standard 16 bit sync counter.The test was how many would fit inside the part and what MHz would it run at ?I doubt the 32 logic blocks would even manage 1 x 16 bit sync counter, tho they might manage a 16 bit ripple counterOne useful indicator would be to see how much of a 74HC590 Sync Binary counter/Latch could fit, and to what MHz ?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 06, 2025, 04:08:29 am
content: Quote from: mikeselectricstuff on June 05, 2025, 03:24:41 pmThe Silego (now Renesas) parts do wide supply and small packages. Schematic entry, most were OTP, tho erasable parts are being released.I think their new 'fpga' variant is only 3.3V.Addit :https://www.eevblog.com/forum/fpga/renesas-lowest-cost-forgefpga-low-density-fpga-free-eval-boards/msg5902810/#msg5902810and Avnet prices SLG47910V at $2.10, no stock showing yet.and thisNew update of Renesas "GoConfigure" app indicates a new FPGA chip SLG47921V, QFN-48 with 2.2K 5-bit LUTs, 64Kbit BRAM, and 40 GPIOs, which are in 2 Vddio domains from 1.71V to 3.3V.Datasheets are by request.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 10, 2025, 03:55:26 pm
content: I just finished implementing a design in one of these PICs. Half a day of dicking about with tools and a day to actually implement the design ( PLD and code).I found an insidious issue with using the online synth tool - when it outputs the bitstream.s file ( an assembler source file you include in your project containing the config data), it doesn't prefix the hex constants with 0x, so the XC8 assembler complains about illegal digits.The obvious fix of adding "radix hex" appears to initially work, however there is something very broken with this directive in XC8 ( 2.36 and 3.00) - it sometimes still complains about perfectly valid hex digits, and very occasionally ( file dependent) will emit a binary file with bits set which don't exist in the PIC's program memory words, leading to failure to program. I'm pretty sure it also sometimes outputs wrong data silently as I was seeing lots of weird stuff.However there is an easy fix - using global replace to replace "dw " with "dw 0x". Luckily MPLABX remembers seraches so this is just a single click for subsequent builds.Once I started doing this, everything worked as expected and the process was fairly manageable.To give an idea of complexity available, attached is the schematic I implemented - the bargraph indicated this used about 75%, though this is a very rough indication - sometimes adding a single routing to a PPS output would make it fail, but there was still space for more logic, so utilisation is very dependent on what you are actually doing. If you run out of space, the first thing is to try trimming out any unneccessary debug pin outputs.A CPLD in 8 pins for GBP0.40 1-off with a free CPU thrown in will definitely fill a few niches.

author: woofy
author_rank: Frequent Contributor
timestamp: July 10, 2025, 04:35:19 pm
content: By coincidence I had a meeting with a Microchip FAE this morning and I mentioned the PIC16F13145. He said that a PIC18 with a 128 cell CLB is on the way. Not much info yet but he did say it will come to life faster and not have to wait for the cpu to load the config file.So looks like Microchip is pushing ahead with the CLB.