Routing output of PLL to a pin on an FPGA(Artix 7) - Page 1
Forum section: electronics / general

author: gauravmp
author_rank: Regular Contributor
timestamp: July 20, 2016, 05:22:50 pm
content: Hi,I'm using the PLLE_BASE library from xilinx to use the PLL of the artix 7 device. I want to be able to route the output of the PLL to a pin. It's my understanding that there are specific compatible pins for the purpose. I have routed it to random pins and I always get an error when implementing. Could someone shed some light on this?Thanks

author: hamster_nz
author_rank: Super Contributor
timestamp: July 20, 2016, 06:46:33 pm
content: Inside the FPGA the signals for carrying clocks is separated from the rest of the fabric, as the clocking signal needs to be distributed with very low skew all over the chip. This makes it unwise to try and route the clock signal directly to a pin, as that pin's output will end up skewed from other external signals that are driven by the same clock.The solution is to use a DDR output register that is hard-wired with 0 and 1 outputs:Code:clock_fwd_ddr : ODDRgeneric map(DDR_CLK_EDGE => "SAME_EDGE",INIT => '0',SRTYPE => "SYNC")port map (Q => output_clk25Mhz,C => clk25MHz,CE => '1', R => '0', S => '0',D1 => '1', D2 => '0');This will give the clock output minimal skew w.r.t. any associated data signals.If you swap the '1' and '0' over in the D1 and D2 inputs, you can generate a clock signal that has the rising edge in the middle of the cycle - allowing the other devices that are consuming the data to latch the data on the rising edge of the clock.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 25, 2016, 02:44:39 am
content: Another thing to be aware of is that Xilinx tools have become more picky about clock buffers, so it's always a good idea to use them with a PLL. Here's some Verilog illustrating how to do it:Code:BUFG bufclk (.I(clk100mhz), .O(clk100mhz_buffered));PLLE2_BASE #(.BANDWIDTH("OPTIMIZED"),.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64).CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360).CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution.CLKOUT0_DIVIDE(80), // 10 MHz.CLKOUT1_DIVIDE(80), // 10 MHz.CLKOUT2_DIVIDE(8),.CLKOUT3_DIVIDE(16),.CLKOUT4_DIVIDE(32),.CLKOUT5_DIVIDE(16),// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT.CLKOUT0_DUTY_CYCLE(0.5),.CLKOUT1_DUTY_CYCLE(0.5),.CLKOUT2_DUTY_CYCLE(0.5),.CLKOUT3_DUTY_CYCLE(0.5),.CLKOUT4_DUTY_CYCLE(0.5),.CLKOUT5_DUTY_CYCLE(0.5),// CLKOUT0_PHASE -- phase offset for each CLKOUT.CLKOUT0_PHASE(0.0),.CLKOUT1_PHASE(0.0),.CLKOUT2_PHASE(0.0),.CLKOUT3_PHASE(0.0),.CLKOUT4_PHASE(0.0),.CLKOUT5_PHASE(0.0),.DIVCLK_DIVIDE(1),.REF_JITTER1(0.0),.STARTUP_WAIT("FALSE")) genclock(// Clock outputs: 1-bit (each) output.CLKOUT0(clk),.CLKOUT1(clk10mhz),.CLKOUT2(clk2_unused),.CLKOUT3(clk3_unused),.CLKOUT4(clk4_unused),.CLKOUT5(clk5_unused),.CLKFBOUT(clk_feedback),.LOCKED(clk_locked),.CLKIN1(clk100mhz_buffered),.PWRDWN(1'b0),.RST(1'b0),.CLKFBIN(clk_feedback));

author: Kilrah
author_rank: Unknown
timestamp: July 25, 2016, 05:28:54 pm
content: Just been through this but for an input, the appropriate "CCIO"s or Clock Capable IOs are labeled as MRCC and SRCC on the pin diagrams.Wasn't very straightforward to find in the myriad of docs. Not the same chip but I imagine it's the same for other 7-series.