DDS and PLL synthezizer clocking Skyworks Si53xx vs ADF4002  - Page 1
Forum section: electronics / projects

author: prutser
author_rank: Regular Contributor
timestamp: November 21, 2023, 06:13:52 am
content: I am working on a PLL synthesizer using an ADF5356. The idea is to use the ADF only in integer mode, to avoid integer boundary spurs. To use it only in integer mode I was planning to use a DDS (clocked at 400MHz) as the reference. But the DDS needs a clean 400MHZ clock (due to performance reasons I do not want to use the internal multiplier)When looking at various clocking options, all the reference designs of ADI use their own devices (e.g. ADF4002). This is what is also used on most projects around on the internet (probably copied from datasheets/appnotes)I was looking at Skyworks (former SiLabs), since clock generators is their core business. If I look at the Si5340-A it has specified RMS jitter in the fs range (lower than ADF4002) and if I compare the phase noise graph at 625MHz, it seems better as well compared to the ADF-4002. The Si5340 requires less external components and can be clocked with an external 10MHZ reference. It initially seems an ideal choice, the question is why I don't see it being used in this kind of applications ?Anyone experience here ? Or an idea why I should prefer and ADFxxx over an Si53xx (not considering price difference)After this, I also considered omitting the DDS and clocking the ADF5356 with the Si5340. ADF in integer mode, Si5340 for the 'fine' steps. I do not know how clean the output signal is of the Si5340 is (filtering might be an option), neither did I check (yet), if the frequency resolution of the Si5340 is sufficient for my application. Any insights here, whether using a Si5340 as a PLL reference clock would degrade performance (compared to low PN VCO with ADF4002) ?

author: S57UUU
author_rank: Regular Contributor
timestamp: November 21, 2023, 03:41:52 pm
content: Hm, I am not sure that the spurs you'll get with a DDS generated PLL reference will be lower than the integer boundary spurs of the ADF5356. Unless maybe you filter the DDS output with a very high quality (crystal) filter - and even then?ADF5356 has a maximum phase detector frequency of 125MHz, and the Si5349 works from 10Mhz. Does the Si chip really have so much better internal VCOs?I would just go with a low noise 125MHz crystal oscillator, and ADF5356 in fractional mode.

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: November 21, 2023, 04:31:06 pm
content: I went from ADF5356 to LMX2594 / 95 because if you need the doubler,there is no fundamental suppression worth speaking of. The 2594 has300 MHz comparator frequency for fract mode and 400 MHz for integer.I cannot yet measure phase noise above 30 MHz (Timepod).I use a 100 MHz ECS oven or Abracon OCXO phaselocked to anexternal 10 MHz reference. The 10->100 MHz PLL will be an adf4002.My current solution is 4046 + LVCMOS.Maybe with a tripler to 300 MHz.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 21, 2023, 05:06:13 pm
content: Quote from: S57UUU on November 21, 2023, 03:41:52 pmYou have to implement it correctly but using a DDS in place of a fractional generator is a pretty standard way to improve SFDR of a synthesizer. A good DDS can have very low spurs and it reduces the need to trade between a low loop bandwidth for better spur rejection and a large wide bandwidth for better phase noise.

author: prutser
author_rank: Regular Contributor
timestamp: November 22, 2023, 08:03:57 pm
content: Quote from: S57UUU on November 21, 2023, 03:41:52 pmI was planning to add a bandpass filter after the DDS (14 bit DDS clocked @ 400MHz) which should be able to provide a clean reference.Quote from: S57UUU on November 21, 2023, 03:41:52 pmThis is still something I have to look in to. Initially I aimed for 125MHz phase detector freq, however I just used ADIPLLSIM and when entering the desired frequency range(The full VCO range) it reports that it is not possible. The max pd freq. it allowed with the full VCO range was 80MHz.I am considering LMX2594 now, it has some advantages over ADF5356.

author: prutser
author_rank: Regular Contributor
timestamp: November 22, 2023, 08:12:02 pm
content: Quote from: Gerhard_dk4xp on November 21, 2023, 04:31:06 pmThe doubler of the ADF5356 is indeed not ideal, the fundamental feedthrough is a well known issue.The LMX has a higher VCO frequency, but divided down is easier to filter since the 3rd harmonics are often more stronger than 2nd.The 300MHZ reference relates to my original question. I still wonder how an Si53xx would be compared to an adf4002 solution for dircetly generating 300MHz.

author: jbb
author_rank: Super Contributor
timestamp: November 22, 2023, 09:34:36 pm
content: Not sure if it’s a viable approach, but I saw some Analog Devices app note which suggested clocking the DDS from the PLLoutput. The PLL reference clock would be fixed (eg by high quality XO) and the DDS would effectively operate as a fancy fractional-N divider.

author: paul@yahrprobert.com
author_rank: Regular Contributor
timestamp: November 25, 2023, 09:20:00 pm
content: I'm not real experienced with DDS chips but I find the idea of using a DDS output as a clock to drive a synthesizer chip a little unsettling. A DDS tries to make a good sine wave by driving a DAC at a high sample rate. But all the synthesizer chips I've used say that for the best phase noise the clock input should have a high slew rate, that is, should be a square wave. The DDS output will be sort of a sine wave with small bumps at its clock frequency. Those bumps travel along the sine wave at some speed related to the difference between the clock frequency and the DDS output frequency. So where on that waveform does the synthesizer chip sense the clock transition? Wherever it is, there will be some jitter in that sensing time due to those traveling bumps, and that will be a source of phase noise.

author: jbb
author_rank: Super Contributor
timestamp: November 25, 2023, 10:29:46 pm
content: I think the general concept is to go DAC output -> filter -> comparator -> whatever.But I suppose the performance of the comparator then becomes quite important, because it now has to deal with a (relatively) slow sine wave signal input.

author: ch_scr
author_rank: Frequent Contributor
timestamp: November 26, 2023, 10:55:31 am
content: To increase the performance of a comperator with a "slow" slope, a "Low Jitter Hard Limiter" is employed, it increases the slope speed of the zero crossing while remaining within the limits of the dynamic range (voltage limits) of the components."A Fresh Look at the Design of Low Jitter Hard Limiters"describes the optimum high-level generalized multi-stage design. An (earlier) design example (for 1Hz Signals) can be foundhere. KO44BB hasa pageon this, even with excel sheets at the bottom.