Poll: am i wasting my time ? - Page 1
Forum section: electronics / projects

author: Experimentonomen
author_rank: Regular Contributor
timestamp: August 31, 2013, 02:56:59 pm
content: I am working on a sensorless BLDC motor driver project and is worndering am i wasting my time doing in on a CPLD using schematic entry over just building up the same circuit with 4000 series logic ?I've been told schematic entry is cancer and the wrong way to do programming and that i should just go and learn how to code.This is the part of the circuit that will be going into the CPLD or would have been built up with 4000 series logic:

author: c4757p
author_rank: Super Contributor
timestamp: August 31, 2013, 03:06:47 pm
content: I find programmable logic "programs" make more sense as code than as schematic, but that comes from years of programming. If you're doing schematic entry for an FPGA, you're just silly, but a CPLD? I say go for it, if it's easy for you.

author: IanB
author_rank: Super Contributor
timestamp: August 31, 2013, 03:08:39 pm
content: Quote from: Experimentonomen on August 31, 2013, 02:56:59 pmI don't understand why anyone would say that. Drawings have been the right way to document and convey designs since forever. The deciding factor is not whether schematic entry is bad, but rather how well the design tool supports schematic entry as a programming method.

author: Experimentonomen
author_rank: Regular Contributor
timestamp: August 31, 2013, 04:57:11 pm
content: Both Xilinx ISE Design Suite and Altera Quartus II has schematic entry, i ended up going xilinx though as they were the only ones that had 5V compatible IO CPLD's.

author: Chipguy
author_rank: Unknown
timestamp: August 31, 2013, 05:42:21 pm
content: Whenever the design is as "simple" as yours, schematic entry is a good way to do it when you don't know VHDL or Verilog.I don't think you are wasting your time, keep going.

author: free_electron
author_rank: Super Contributor
timestamp: August 31, 2013, 07:00:35 pm
content: Quote from: c4757p on August 31, 2013, 03:06:47 pmeven for multimillion gate asics we still use schematic entry ... claiming it 'silly' is a sign of shortsightedness...sure, blocks are written in an HDL. no designer in his right mind would make a serdes or cordic as schematic. but, when the block is ready , a schematic symbol is generated showing the inputs and outputs. the block is then simulated and verified.when all blocks of the design are ready they may be stitched togeher using instances in another hdl file. but , at this point a schematic diagram is pulled showing the interconnects. to make sure nothing is forgotten in that textfile. an open input is immediately visible on a schematic as there is no line going to it ...then analog blocks are pulled in and wired up.then io cells are added. inverters for active low inputs are injected. all on top level schematic.the top level schematic is also used to navigate the complex project.when timing closure is done and drive strength has been calculated additional drivers are inserted on nets ... in the schematic ! because you can't add that in the hdl. there is no way to tell the synthesizer what net needs what strength as the final logic is unknonw prior to synthesis.the multimillion gate asic is placed and routed , with providin for injectors , net load is calculated and compared to the needed setup and hold times and then the software figures out which nets need extra drivers. the designer repsonsible for the backend then clicks the net , this opens the schematic view for that net , plonks in one or more drivers ( depending on how many forks there are in the net ) and the tool places them.so yes, schematic is not dead or silly.for designing a simple circuit : go for schematic.i got bocks in my fpga that are designed as pure schematic because making them in a hdl is simply too annoying. like a constant propagation delay multiplexer... ( independent from wich input you select the prop delay between in and out is fixed... ) . you'd have to design that as a netlist and tell the synthesizer : implement as given. do not optimize. you have to be nuts to write a netlist by hand.... gimme a schematic tool i'll draw it faster than you can write it.same for a delay cascade. or in input debouncer , or a circuit that needs to work on both clock edges. i can visualise immediately what such a thing needs to look like. exor gate on the clock input from an edge triggered d-flipflop exor input with q output. have you figured out already how to code that in hdl ?always at posedge or negedge ? aint gonna work ... or some other whacky cicruit that does not use a common clock....there simply are too many situations where schematic entry is faster than trying to coax the synthesizer in generating exactly what you need.

author: tszaboo
author_rank: Super Contributor
timestamp: August 31, 2013, 08:04:57 pm
content: Sch entry might not give you optimal code, therefore FPGA fans will tell you to go for VHDL or Verilog, because then you might save some bucks on the chip. They only forgot, that development time is way less for sch, hence the project cost might easily be less. I would say go for it.

author: nctnico
author_rank: Super Contributor
timestamp: September 01, 2013, 12:21:15 am
content: The truth is somewhere in the middle. Schematic entry is great for creating top-level diagrams to connect blocks like Free-electron already explained. For low level VHDL and Verilog are better because you can create designs which can are configurable and thus easier to re-use.

author: Experimentonomen
author_rank: Regular Contributor
timestamp: September 01, 2013, 11:09:40 am
content: If i wanned to implement FOC sinewave drive and such stuff, then yes Verilog or VHDL would quite literally be the only way to do it as you cant build up the ABC to QD FOC blocks with analog/digial components as they are purely mathematical and such fun stuff.But for a design that is mostly a jumble of 4000 series logic gates, schematic feels like a better way to go, sure you can go into the VHDL/Verilog code after the conversion and optimize the code if you feel like, but im not after optimized code to save space in my cpld's memory, im after having fun.I might actuallt think abour doing it in all 4000 series logic as well if it turns out this will actually work, that why i went with a cpld, i dident wanna assamble something this compex on a board only to find out it wont work, i've had too much of that in the past and its one reason im much less active now than i were a few years ago.

author: fcb
author_rank: Super Contributor
timestamp: September 01, 2013, 11:26:47 am
content: I use schematic entry on ISE - it makes perfect sense to me as I grew up on 4000B/74LS, also write all PIC code in assembler and have done for 20+years (12/14/16/17/18/30/33 series, still not needed the 24/32 series).I've done plenty of BLDC control, but never used a CPLD though (done it using 17C, 18F, 30F and 33F series).

author: Experimentonomen
author_rank: Regular Contributor
timestamp: September 01, 2013, 11:50:14 am
content: Schematic entry is what allows me to use a CPLD as programming languages like C, Verilog and VHDL are greek to me.

author: hlavac
author_rank: Frequent Contributor
timestamp: September 01, 2013, 05:28:08 pm
content: Schematic entry equals vendor lock in.With HDL you at least have some hope when you keep the vendor specific stuff pluggable.

author: Experimentonomen
author_rank: Regular Contributor
timestamp: September 01, 2013, 06:34:48 pm
content: Well this project is never gonna end up as a actual product or anything, its simply one of my "for fun" projects.

author: Experimentonomen
author_rank: Regular Contributor
timestamp: September 02, 2013, 04:00:19 pm
content: While waiting for the cpld and the programmer to arrive, i drew up a power board for the project and sent out an order to seeedstudio, should arrive around the same time as the rest of the stuff.