CPLD/FPGA design flow - Page 1
Forum section: electronics / general

author: c64
author_rank: Frequent Contributor
timestamp: October 06, 2023, 04:26:48 am
content: I'm using Prochip Designer from Microchip for ATF15xx CPLD and I don't really understand one thing.First, it runs Precision Synthesis RTL tool to generate EDIF file. It also checks for timing constraints.Then, it runs the fitter. Fitter may change how logic is implemented on the device. For example, it may decide to usefoldback logic, which will introduce extra propagation delay.But fitter knows nothing about timing constraints. It only has EDIF file as input.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: October 08, 2023, 10:28:19 pm
content: ATF15xx CPLD are coarse-timing device, with limited 'routing' choices.Their timings are also somewhat nominal, and the fitter can be controlled somewhat with 'keep' type keywords, if you really want to manage what nodes collapse.The fitter report file is going to give you the best information.Pin placement can also affect the FIT, and you will need to allocate pins at some stage in the design.You can float the pins, and the check the fit, and then if using WinCUPL, the fitter pin report is CUPL paste-able to lock pins for later revisions.Pin shuffle and refit is a bit iterative, as not all pin maps can fit.

author: c64
author_rank: Frequent Contributor
timestamp: October 09, 2023, 05:17:27 am
content: Fitter report file does say what logic was changed to foldback logic, because it could not fit it without it. I guess because some of my logic has too many inputs.My question is, how can I be sure my timing requirements are met, after fitter introduced extra delays?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: October 09, 2023, 05:37:05 am
content: The fitter can generate .VO and .VHO files, maybe Prochip designer can use those to check ?I've not used Prochip with ATF15xx, I use her WinCUPL flows.

author: c64
author_rank: Frequent Contributor
timestamp: December 12, 2023, 02:36:39 am
content: Fitter generates VO (verilog file, looks like describing what was actually generated) and SDO (timing for all primitives from VO). Precision RTL can not even compile VO.As I understand from the documentation, VO and SDO are for timing simulation. I don't have license for it, so can not check

author: c64
author_rank: Frequent Contributor
timestamp: December 12, 2023, 02:40:23 am
content: There is also this warning during synthesis, which confirms that timings may change after fitter reshuffles everythingPOST-SYNTHESIS TIMING REPORTS ARE ESTIMATES AND SHOULD NOT BE RELIED ON TO MAKE QoR DECISIONS. For accurate timing information, please run place-and-route (P&R) and review P&R generated timing reports.

author: c64
author_rank: Frequent Contributor
timestamp: December 12, 2023, 03:18:43 am
content: I created a 16 bit counter, in Prochip it compiles up to 24 MHz. Exactly same in Quartus compiles to 76 MHz.I guess now it's proven that Prochip timing reports are totally useless. Which is a shame. They created devices with some extra features (compared to compatible Altera devices), but no software to actually use these features. If you have timing constraints, you have to use Quartus.

author: BrianHG
author_rank: Super Contributor
timestamp: December 13, 2023, 02:32:47 am
content: Quote from: c64 on December 12, 2023, 03:18:43 amWhat was the difference in FPGA logic cell usage compared to the 2 different compilers?What was the compiler's optimization settings set for? (Area / Balanced / Speed) (These are Altera Quartus' compiler optimization settings)

author: c64
author_rank: Frequent Contributor
timestamp: December 13, 2023, 02:57:32 am
content: Both projects had timing constraints for 70MHz clock. And I tried both speed and area optimization in Quartus.I already deleted my VM with Prochip so can not check logic cell usage