buffer for digital signals - Page 1
Forum section: electronics / beginners

author: fady232
author_rank: Contributor
timestamp: April 18, 2025, 07:45:09 am
content: Hello all, i was simulating a buffer for digital signals , and i had some questions, if someone could help, thanks.First of all the first stage made of npn basically does this: I got a pulse wave that goes from 0 to 5V as VIN, and as output i got the same wave but with a drop of 0.7V ( so from 0-4.3V, for now the output doesnt see the capacitive load, so everything is fine, beside that i got this voltage drop)Now lets pass to second stage: in the second stage im giving a square wave that goes from 0 to 4.3V , what the pnp does? he shifts the wave up by 0.7so what im gonna see is a wave that goes from 0.7 to 5V, now my question is: is this way correct to analyze circuit? im looking at right things? am i missing something?Second question: why does the simulation dont show the distortion in the second stage vout? the stage with the capacitor?, when pulse wave goes low from 5V-->0V the voltage drops and the 100pF discharges via the 10k resistor with a tau given by tau=R*C, but in that way i shouldnt see a perfect square wave, cus it goes ''slowly'' to 0V or im wrong?Thanks for whoever gonna answer and sorry if im a bit newbie, but trying to learn as much as i can:D

author: PGPG
author_rank: Frequent Contributor
timestamp: April 18, 2025, 11:57:52 am
content: Quote from: fady232 on April 18, 2025, 07:45:09 am1. 10k*100p = 1000ns=1us while your pulse length is 2s. Your "slowly" is 1/2000000 of your pulse - at any screen it is less then a pixel.2. On negative slope 100p is not discharged with 10k*100p time constant but much, much faster.

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 18, 2025, 12:10:34 pm
content: The transistors are not perfect devices, and the simulation takes that into account, so that is good.The first stage of your circuit is an emitter follower, and has a voltage drop of 0.7V because the base emitter junction needs this to turn the transistor on. That is why the output voltage on the emitter is 0.7V lower than the input voltage. This voltage drop depends on the type of transistor used, and for this one has to read the datasheet.There will be a capacitive curve in this first stage too, due to parasitic capacitance. One has to zoom in on the edge to be able to see it, but it will be there.For the second stage basically the same applies. It is also an emitter follower, but now with a pnp transistor. This means that the 0.7V drop is near ground, because that is where the base emitter junction sits. It does not reach the full 5V due to the resistive divider made by R2 and R3. The high output voltage is therefore 10 / 11 * 5V = ~4.5V.The 100pF capacitor is charged to this max high output voltage through R2. It is being discharged to 0.7V through the pnp thransistor though and that will have a much lower resistance when turned on.With 1000 Ohm times 0.0000000001 Farad, the tau is very low, 100ns based on the calculation. It takes at least 5 tau to reach the ~99% charge point, so 500ns. Your time scale in the simulation is in 10ths of miliseconds. You won't see that curve.

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 18, 2025, 12:14:27 pm
content: Quote from: PGPG on April 18, 2025, 11:57:52 amAre you sure about this.Check the schematic, the capacitor is charged through R2 and discharged through Q1. R3 is insignificant in the discharge phase.My calculations are not perfect either, but close enough to come to the same conclusion. The time scale on the simulation is to slow to show any curve.One should use network calculations on R2, R3 and C1 for the correct result.

author: fady232
author_rank: Contributor
timestamp: April 18, 2025, 12:24:23 pm
content: hey why u say there is a voltage divider made by R2 and R3?, can u explain how these affect the signal? vcc is just power supply, i didnt get it tbh.how and why did u calculate the vout like that? 10/11 * 5?

author: fady232
author_rank: Contributor
timestamp: April 18, 2025, 12:27:32 pm
content: current has no other ways beside R3 to discharge no?

author: fady232
author_rank: Contributor
timestamp: April 18, 2025, 12:29:58 pm
content: when the transistor doesnt conduct, the only way for the capacitor to discharge is that way no? via R3

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 18, 2025, 12:49:42 pm
content: Quote from: fady232 on April 18, 2025, 12:24:23 pmYou have to seriously go and study electric networks. In your schematic V3 is the supply voltage, set to 5V.Not looking at Q2, this supply is connected to R2, and the other end or R2 is connected to Q1, C1 and R3. When Q1 is off, it can be discarded.This leaves R2,C1 and R3, where both C1 and R3 are connected to ground. This is a network of parts. When fully charged C1 can also be discarded.So R2 and R3 are now in series forming a voltage divider.Quote from: fady232 on April 18, 2025, 12:24:23 pmWith the above simplification of the schematic, the voltage over R3 can be calculated by V3 * (R3 / (R2 + R3)). So 5 * (10000 / (10000 + 1000)) which is 5 * (10000 / 11000), and this is the same as 5 * (10 / 11).Quote from: fady232 on April 18, 2025, 12:27:32 pmWhen Q1 is turned on there is current flowing from V3 through R2, Q1 and R3. Q1 has a very low resistance and makes the voltage at Vout2 0.7V. R3 and C1 are now at this level, so the current flowing through R3 is 0.7V / 10000 = 70uA.The capacitor C1 is discharged basically only by Q1 when it is turned on.Quote from: fady232 on April 18, 2025, 12:29:58 pmWhen Q1 is off, and does not conduct the capacitor C1 will not discharge, but it will charge to V3 via R2, but is limited by the resistive voltage divider made by R2 and R3.So for the capacitor R3 is almost irrelevant.

author: fady232
author_rank: Contributor
timestamp: April 18, 2025, 12:59:50 pm
content: ahh u mean voltage divider made by this when the p transistor is off ( not conducting ) right?

author: fady232
author_rank: Contributor
timestamp: April 18, 2025, 01:01:24 pm
content: during positive phase "5V" they charge and during negative cycle "0V" they discharge no?

author: fady232
author_rank: Contributor
timestamp: April 18, 2025, 01:05:14 pm
content: "When Q1 is turned on there is current flowing from V3 through R2, Q1 and R3. Q1 has a very low resistance and makes the voltage at Vout2 0.7V. R3 and C1 are now at this level, so the current flowing through R3 is 0.7V / 10000 = 70uA.The capacitor C1 is discharged basically only by Q1 when it is turned on."I dont understand, when Q1 is turned on, it means he closes to gnd, vcc is pulled to gnd via the 1k resistor, in this way what we will see in output is the square wave we give in the base of the p transistor, r3 at this point is in parallel to this voltage or im wrong?

author: SteveThackery
author_rank: Super Contributor
timestamp: April 18, 2025, 03:17:09 pm
content: Quote from: fady232 on April 18, 2025, 01:05:14 pmI'm struggling to fully understand your question, but what you've written doesn't sound quite right.First, there is no Vcc on your schematic. I assume you mean V3.When Q1 is switched on, the voltage at its emitter (notV3) is pulled down to ground (very close). Current will flow from V3, through R1 and Q1 to ground.The top of R3 is connected to Q1 emitter and the bottom of R3 is connected to ground, so it will always have the same voltage across it as Q1. In this respect, R3 is in parallel with Q1 (as is C1).VOUT2 is taken from the emitter of Q1, so yes - R3 and C1 are in parallel with the output voltage, which is taken between VOUT2 and ground.I'm sorry if this has not answered your question.

author: PGPG
author_rank: Frequent Contributor
timestamp: April 18, 2025, 03:48:03 pm
content: Quote from: pcprogrammer on April 18, 2025, 12:14:27 pmYes. I'm sure about what I have said, but I'm not sure what doubts do you have (I'm even not sure if you are questioning my point 1 or point 2).In my point 1:I did not refer to the operation of the circuit, but only to the time constant mentioned by the OP (he named it being "slowly") and I compared it to pulse time he used in simulation.In my point 2:I have only said that C1 is not discharged by R3 but faster. My intention was to make the OP think about which path this capacitor is being discharged through to be discharged much faster then he assumes. Any knowledge you get yourself is at once much better remembered then knowledge someone just tell you.

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 18, 2025, 04:02:09 pm
content: Quote from: PGPG on April 18, 2025, 03:48:03 pmSorry, I misread your reply, and now that you pointed it out, I see what you mean. And indeed knowledge that you acquire on your own will better stick, but for this to happen I feel the OP has to restart at base level. No offense intended, but this stuff is quite basic.

author: PGPG
author_rank: Frequent Contributor
timestamp: April 18, 2025, 04:05:17 pm
content: Quote from: SteveThackery on April 18, 2025, 03:17:09 pmQ1 is newer switched on in the sense it takes its emitter to be very close to its collector. It is working as emitter follower and voltage at emitter will never be lower than about 0.7V.To pull its emitter to be very close to ground you will have to have a negative voltage source to polarize its base but in this circuit you don't have it.

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 18, 2025, 04:11:18 pm
content: Quote from: fady232 on April 18, 2025, 12:59:50 pmYes the signal path you drawn shows the voltage divider I'm talking about.Quote from: fady232 on April 18, 2025, 01:01:24 pmI assume you are talking about the capacitor (C1), and yes, when the output is, what in the digital world is called, high, the capacitor is charged to V3 through R2. It only never reaches V3 due to the presence of R3. This is when Q1 is not conducting, so Vout1 is at V3 level.When Q1 starts to conduct, which is when Vout1 is at ~ground level, the capacitor discharges to ground level. (0V).If you want to see the capacitor charging curve in the simulation, raise the value of C1, such that tau becomes in the mili second range.You should now know how to calculate a new value of C1 to make this happen.

author: SteveThackery
author_rank: Super Contributor
timestamp: April 18, 2025, 05:02:13 pm
content: Quote from: PGPG on April 18, 2025, 04:05:17 pmThanks for correcting me, @PGPG. I shouldn't have said "very close". But for the sake of the explanation I was giving, it was probably meaningful enough to explain the basic principle.I've just re-read the thread, and it seems hard to understand exactly what the OP needs explaining.

author: Zero999
author_rank: Super Contributor
timestamp: April 18, 2025, 05:04:56 pm
content: Please upload the .asc file in future.Another two transistors are required to make a buffer with a low output impedance, both for rising and falling signals.When you simulate this circuit, you must also add some series resistance to the input voltage source, otherwise it's too perfect and isn't representative of a real life circuit.Note that the input is also distorted, because the voltage drops, due to the loading of the buffer's input stage.