criticize my design - Page 1
Forum section: electronics / projects

author: martinribelotta
author_rank: Regular Contributor
timestamp: March 18, 2021, 09:55:48 pm
content: Hi everyone, I'm design a little board with arduino-due compatible form factor and need some (constructive) criticism of the design:https://github.com/martinribelotta/h730duinoContext:I'm freelancer developerSome client ask me a cuestion about the posibility of an arduino compatible hardware but using the "most big and power mcu in the market"I start a previos design...The client not concrete anything about itI finish the design by my own impetuosityThe client is not interesting now in the design for comercial circumstances (financial problems and things like this)I see some potential in this design and decide to open the sourceCharacteristics (copied from readme):CPU Cortex-M7 at 550MHz.128K/1 MB of internal flash (depending on the MCU version).500 KB of internal RAM.8 MB of external QSPI PSRAM at 133MHz SDR.16/32/128 MB of external QSPI Flash at 133MHz SDR.10/100Mb Ethernet.USB 2.0 OTG Type-C with power switch control.USB CMSIS-DAP Debugger.micro SD Card slot.Arduino Due/Mega compatible pin headers (3.3V IO, 5V tolerant on some pins).Arduino API compatible (via STM32Duino project).Micropython support.Protected power inputs with ideal diodes and DC-DC converterPD0: The idea is to put in croudsupply when I have a prototype.PD1: The chip shortage played a trick on me because some parts (stm32f042 by example) is out-of-stock for a wilePD2: I'm not convinced around the power supply scheme... (maybe I made this some simple and robust?)PD3: This is not an industrial design, is for hobby/lab only (in the same spirit of arduino)PD4: MIT licence is the rigth way to make the hardware free to modify for any 3rd part?

author: Mecanix
author_rank: Frequent Contributor
timestamp: March 18, 2021, 10:35:57 pm
content: I think it looks killer!1. VCAP: change those two 100n for 2.2u (one 2.2u for each VCAP)2. RST: add a 100n to GND3. Why L2?4. SWDIO: pullup to 3V3 (10k)5. SWCLK: pulldown to GND (10k)6. USB: add one USBLC6-2SC67. Add series 0R on the transmission/data lines. Just so you can tweak that in the event of...8. few other things... might have a look again later

author: MikeK
author_rank: Super Contributor
timestamp: March 18, 2021, 10:45:46 pm
content: Why wouldn't people just buy a Teensy?

author: glentek
author_rank: Regular Contributor
timestamp: March 18, 2021, 11:19:23 pm
content: How do the specs compare side by side to a Teensy 4?

author: martinribelotta
author_rank: Regular Contributor
timestamp: March 18, 2021, 11:35:11 pm
content: Quote from: Mecanix on March 18, 2021, 10:35:57 pmDoing It... is reasonable... I only copy my design from stm32h750 without evaluato too much...Quote from: Mecanix on March 18, 2021, 10:35:57 pmBeside the already existent 1u capacitor?Quote from: Mecanix on March 18, 2021, 10:35:57 pmBecause originally I thing to separate AGND to DGND planes in geometrical form... with this design not have sense... I remove it in this design without injury...Quote from: Mecanix on March 18, 2021, 10:35:57 pmI take it!Quote from: Mecanix on March 18, 2021, 10:35:57 pmWhat is the advantage of USBLC6 over traditional diode suppression? I have worked with USB6LC-XXX before but I'm not sure if this have advantages...BTW: The routing with USBLC6-XXX is more easyQuote from: Mecanix on March 18, 2021, 10:35:57 pmIn the USB circuits?Quote from: Mecanix on March 18, 2021, 10:35:57 pmThank a lot!

author: Mecanix
author_rank: Frequent Contributor
timestamp: March 18, 2021, 11:53:03 pm
content: Missed that RST 1u capacitor, my bad (tired, maybe, sorry). Although 100n is enough really...That VDD -vs- VDDA is all depending whether the application rely on that ST's ADC. When ADC/sensor data is critical I normally use a 4layer stack with an independent analog plane just for VDDA. Might be omitted in your case though, that killer board don't appear to be just an ADC anyway0Rs on the QSPI data lines, you'll see why if/when you want this run at high speed eventually. Wouldn't hurt to have them on the USB lines too although that's all up to you really... always good to have a footprints there just in case!Looks good man, I think its nice work. Keep it up you're in the right vocation obviously.

author: martinribelotta
author_rank: Regular Contributor
timestamp: March 22, 2021, 01:31:16 am
content: Some updates...Rearrange pins to have QSPI flash and QSPI ram in two separated buses (previous, both share the same data bus and diferent CS. This improve soo-much the signal integrity enable me to match impedances correctly in PCB and make little IBIS simualtion.Match impedances better (the rule of thumb is 6mils/6mils for 50ohm in 0.2mm standard pcb 4layer separation) Now, I simulate the scenario and the estimated impedances is in tolerance rangePut pullups in microSD and match track length (this may be not necesary but reduce the posibilities of fail)In any case, the big issue at this moment to manufacture this board is LAN8742 (out of stock for long ago) and STM32F042 (commented in other threads)The STM32F042 is reasonably easy to replace by an other STM32F0 with USB (like STM32F048 in QFN28) but the LAN8742 is really problematic...Someone with more experience than my in ETH PHY can suggest me some replacement? Normally I place the reference design PHY for prevent problems (and maximize with STM32CubeMX that provide support only for this PHY... I really don't want to dive into the cubehal for reimplement this piece of software)