74HCxxx to 74HCTxxx conversion  - Page 1
Forum section: electronics / projects

author: VermontEE
author_rank: Contributor
timestamp: February 19, 2016, 03:46:41 pm
content: I've inherited a 5V system that I have to convert to 3.3V.There is no logic level conversion here it's straight up Vcc was 5V and now it's 3.3V.There is a logic section and my question is "Can I simply change the 74HCxxx to 74HCTxxx" and move on?I have looked at the switching standards for Vih, Vil, Voh, Vol and it looks like there isn't an issue for the swap from HC to HCT. The fanout is less than 5 gates.Is there something I am overlooking? Is there any reason to use 74LVTxxx parts? I want to make sure I'm not overlooking something before I go to copper.

author: wraper
author_rank: Unknown
timestamp: February 19, 2016, 04:20:50 pm
content: Why do you think 74HCT series are specified to operate at 3.3V? They are 4.5-5.5V with ttl level inputs. However 74HC series are specified to operate at 2.0-6.0V power. So most likely you don't need to change anything.

author: VermontEE
author_rank: Contributor
timestamp: February 19, 2016, 04:38:04 pm
content: You are right! I confused myself horribly. Originally, I specified HC parts then couldn't figure out for the life of me why. Thank you for straightening me out.

author: ignator
author_rank: Regular Contributor
timestamp: February 19, 2016, 04:39:29 pm
content: The big problem I found with logic family change was edge rate. This can have deleterious effects to digital circuit operation. If your PWB was designed with no signal integrity for fast signals, and your new part has super fast edge rates, you can get outputs that go many volts below ground or above Vcc.My example was an 74HC138 chip select which in 1989 had 8ns edge max. Someone in manufacturing blindly changed to LS and initially all was well, but then the parts started getting faster, the best scope measurement I made they were around .45 nanoseconds. So the chip select signal was transitioning 5 volts below ground and 5 volts above Vcc. The device it was selecting was a UART, this was supposes to be an input pin, but by going negative it sucked current from the substrate via the intrinsic diode. This cause the parity flip flop to trigger, which would throw the current receive data away. The processor was polling at .6x the word rate of this UART (it was a custom 32 bit ARINC429 bus). So half the data was tossed. It just happened that this was the longest signal trace of all the chip select signals on the board (about 7cm) which made sense from it's intrinsic inductance being just enough to cause this lenz's law induced voltage swings. The fix was to insert 25 ohm output resistors right at the 74138 pins in series, to limit the di/dt and dv/dt from the totem pole output driver to the circuit trace. During this manufacturing fault finding, all the microprocessor address and data bus signals from the buffers had this similar design problem, there I found pin compatible buffers that had the 25 ohm resistor built in.This processor was an 80186 running at 10Mhz, so it was not a speed demon design. So check your signal integrity before releasing this to the field.I never could figure out why factory test did not have this problem, other then the test adapters had long DC power connections to the EUT, and believe this damped the power rails to the 74138 that limited the very fast di/dt during test.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 19, 2016, 05:08:40 pm
content: Quote from: ignator on February 19, 2016, 04:39:29 pmThis sounds like source termination, which has nothing to do with limiting edge rates.What happens is that the output resistor matches the output impedance of the driver to the trace, so when the reflected signal comes back from the (unterminated) receiver, the energy in the reflected wave is absorbed into the resistor and dissipated as heat.Without it, a wave is launched from the driver, which travels the length of the trace, and when it hits the high impedance receiver, it doubles in (voltage) amplitude and changes sign. It then propagates back toward the driver, which is also poorly matched to the impedance of the trace, and so a second reflection occurs. The wavefront bounces up and down the trace repeatedly, and this is what results in the "ringing" at the receiver.With correct series termination, the wave (at the driver) is initially only half the eventual amplitude, because the termination resistor forms a potential divider with the impedance of the trace. That wave propagates to the receiver, and as before, it doubles in amplitude, so you get a single, clean, monotonic edge at the receiver. The reflected wave, meanwhile, sees no impedance discontinuity when it reaches the driver, so there's no further reflection, and the "ringing" doesn't occur.All this can happen fast; the terminating resistor doesn't (theoretically) limit the edge rate at all. Don't think of it as an R-C filter.

author: ignator
author_rank: Regular Contributor
timestamp: February 19, 2016, 07:39:36 pm
content: Yes they are source termination. But I've never bought into the idea of "reflected wave". In the end your driving a real transmission line, one that has capacitance, inductance, resistance, and leakage paths. That reflected wave is nothing more then energy being stored in the circuit trace L and C. And the source termination does limit the current di/dt, so the instantaneous energy transfer is damped. In this case it was the energy in the inductance that induced this voltage pulse.Others believe in "reflected pulse" I don't.

author: Zero999
author_rank: Super Contributor
timestamp: February 19, 2016, 08:26:05 pm
content: Yes, it's a reflected pulse. A transmission line is different to an LRC circuit because the resistance, inductance and capacitance are distributed throughout the line, rather than as discrete components.Back to the original question: the only issue with reducing the voltage is the propagation delay, rise/fall times and output impedance increase so the logic gates may no longer be fast enough and will not be able to source/sink as much current before the output voltage is no longer at a valid logic level.The 74HC family data sheet gives more information.http://www.nxp.com/documents/user_manual/HCT_USER_GUIDE.pdf