Suggestions for LLC Converter PCB Design - Page 1
Forum section: electronics / beginners

author: mundachakka
author_rank: Newbie
timestamp: March 09, 2023, 05:12:03 am
content: I have been studying LLC converter for a university project as a back-end DC/DC converter for a battery charger. I must make a PCB model for the converter operating in an open loop. I have made a PCB model and would like any suggestions to help make it better. Thank you.Specs :Input - 400vOutput - 60vPower - 500wBoth the inductor and transformer are to be placed externally.TLP250H-based optocoupler driver is being used.

author: mariush
author_rank: Super Contributor
timestamp: March 09, 2023, 08:10:53 am
content: Well, just looking at the picture... obvious changes would be flipping two rows of capacitors so that the positives are in the middle instead of loopingFor example flip c1-c9 , put a bit of spacing between columns and you have a nice thick voltage traceMaybe same for C24-C27 .. flip them and spread them to have the voltage trace between the capacitors.You have the whole bottom for grounds, and you can use lots of vias to connect top grounds to bottom layer.V- doesn't make sense at the bottom, it should probably be to the left of V+ input, do you want a cable potentially sitting over the capacitors or heatsinks, do you want different lengths of cable?If you need to you could flip the bottom mosfet so that the pin is closer to the capacitors.P1 and P2 would make sense to be closer.With V- gone from the bottom row, you could shift all a bit to the left, and put S2 near S1 ... in fact maybe it would make more sense to have C0 between S1 and S2, to reduce risk of someone accidentally soldering wires incorrectly.Also, may want to consider having footprint option for a 2-diode pack, like maybeSTTH6003CW(didn't exactly check the specifications, may not be suitable for your needs, but giving it as example)Why change to have the output voltage at the bottom layer on the output, it's confusing... keep it on the top and leave bottom for ground.Pay attention to heatsinks and traces going under them ... for example that trace going from C0 to the bank of capacitors, seems to be under heatsinsks of those mosfets. If the heatsink is at high voltage and there a mechanical shock or something causing the heatsink to scratch the pcb and touch the trace ... maybe better to not have trace go under that footprint of heatsink.May want to consider airflow ... for example if you align all your heatsinks so that air could flow from left to right (in the picture) then that bank of input capacitors could block airflow.May want to consider doubling the holes for C0 and S1 and S2, maybe you'll want to use thinner wires and common connectors instead of soldering. For example, maybe you could repurpose a 8 pin EPS or pci-e connector (miniFit Jr. series) and have 2 AWG16/AWG18 wires for S1, 2 for S2 , and 2-4 wires for C0

author: mundachakka
author_rank: Newbie
timestamp: March 09, 2023, 10:01:58 am
content: Quote from: karpouzi9 on March 09, 2023, 06:55:53 amI am from a remote place and the professors are less than helpful in PCB design and layout. I have also made a front-end pfc converter and mostly did it using trial and error.Quote from: mariush on March 09, 2023, 08:10:53 amThank you for this... I will look into it and make the necessary changes.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 09, 2023, 07:44:04 pm
content: No bypass between V+/V- is a no-go.Loop area is fine as long as you don't drive the MOSFETs too hard. Assuming a bypass placed like so:Bypass can be film or ceramic; preferably film, as ceramics are either small, or expensive, in high voltage ratings.Better still, can divide the resonant caps between +V/-V so they serve this job, AND reduce start-up transients because the capacitive divider will start charged to (V+ + V-) / 2.Both sets of caps are better connected with a pour on top and bottom, no need to route traces.I'd use larger capacitors, I don't get the teeny tiny footprint choice; but you certainly can use a bunch in parallel if you want to.Good luck!Tim

author: mundachakka
author_rank: Newbie
timestamp: March 13, 2023, 06:13:13 pm
content: Quote from: T3sl4co1l on March 09, 2023, 07:44:04 pmOperating frequency is around 50 Khz.Quote from: T3sl4co1l on March 09, 2023, 07:44:04 pmWill do this...thank you.Quote from: T3sl4co1l on March 09, 2023, 07:44:04 pmPCB's cost a bit much here and reducing the footprint eases that up a bit.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 14, 2023, 12:38:54 am
content: Quote from: mundachakka on March 13, 2023, 06:13:13 pmNot frequency---edge rate is what matters here. Rise/fall time, gate drive strength. If you're delivering 1A from a 400V supply for example, and that 1A switches off in 10ns (very easy to do with modern transistors), you have dI/dt = 100A/us, which flowing through an inductor generates a peak voltage of V = L * dI/dt. On-board inductances are in the < 100nH range which should be fine (may need an R+C snubber across the transistors to reduce the ringing though), but no bypass at all brings wiring into question which can be ~uH. Not to mention the wire being an EMP blast to anything nearby -- peak voltage might not be as much a concern as basic functional operation as the control or other nearby equipment gets confused by the intense emissions!Tim

author: dobsonr741
author_rank: Frequent Contributor
timestamp: March 14, 2023, 01:55:51 am
content: Why did you not use larger fills? Specially when paralleling the caps. The layout seems as there was an intention to avoid the top and bottom copper to overlap.