Anyone still using Mikrotik rb532A? (2006, mips32le router) - Page 1
Forum section: electronics / general

author: DiTBho
author_rank: Super Contributor
timestamp: January 21, 2025, 04:07:56 pm
content: When it appeared in 2006, it was the era of Linux v2.6, v2.6.22 to v2.6.32 were the kernels of greatest interest and support, especially by OpenWRT.When I write on { NetBSD, Linux/MIPS, ... } ML ... nobody replies. Sounds abandoned platform.Then came the RPI and other cheaper SBCs, and the rb532a took a back seat until the END of LIFE declared by the manufacturer.I can boot kernel 6.0x, but there are still many unresolved issues.First of all, the firmware has some undocumented quirks, sometimes it refuses to tftpboot elf binaries, but it doesn't explain why, nor does it provide an error message that can help.Second, the firmware refuses to accept some Microdrive, it doesn't explain why, it only says "CF not present", while you hear the motor spinng down.Third, the firmware requires you partition the NAND flash into two slices.Code:dev: size erasesize namemtd0: 00400000 00020000 "Routerboard NAND boot"mtd1: 07c00000 00020000 "rootfs"The first slice must be 4Mbyte size, and must be "yaffs" formatted. The linux kernel must be renamed "kernel", otherwise it won't load it.Here the first problem: 4-Mbyte is too small for a modern kernel v6, which is usually not less than 7-Mbyte with the minimal configuration.Secondly, the "yaffs" (flash-oriented) filesystem was never included in the linux kernel, worse still it is no longer supported since a while.Anyone still using it?

author: DiTBho
author_rank: Super Contributor
timestamp: January 21, 2025, 04:25:43 pm
content: based onIDT-79RC32434.A few interesting posts about its performancehereon the Forum.edit:Latest Rooterboot with fixes mentioned specifically for rb532a is v2.18, seechangelog

author: DiTBho
author_rank: Super Contributor
timestamp: January 21, 2025, 09:35:38 pm
content: "kernel out of range" during TftpbootThis error is not related to the binary dimension of the elf.I have not yet figured out what it is related to.Code:RouterBOOT booter 2.8RouterBoard 532ACPU frequency: 399 MHzMemory size: 64 MBPress any key within 2 seconds to enter setup..trying bootp protocol... OKtransfer started.......................................................... transferok, time=2.76ssetting up elf image... kernel out of rangekernel loading failed

author: Nominal Animal
author_rank: Super Contributor
timestamp: January 23, 2025, 12:58:34 am
content: Quote from: DiTBho on January 21, 2025, 09:35:38 pmI believe RouterBOOT 2.8 is very limited in what address ranges it can load a kernel at, and the "kernel out of range" error indicates the kernel image wants to be loaded outside that range. Simply put, it's RouterBOOT 2.8 being stupidly limited/limiting.(If the kernel image is compressed, then it could also be that RouterBOOT loads the compressed image to the same address range as the kernel wants to be decompressed to.)I fear your only options are to play with the kernel base address (CONFIG_PHYSICAL_START). I don't know if RouterBOOT allows changing where it loads the compressed image, what the 4MB range it has reserved for that is.

author: DiTBho
author_rank: Super Contributor
timestamp: January 23, 2025, 09:35:50 am
content: Quote from: Nominal Animal on January 23, 2025, 12:58:34 amYup, RouterBoot is full of quirks, and the user manual doesn't say anything.I emailed severally and several times to Mikrotik, they never answered.Over time, and by trying it myself, I discovered that it expectsThe first partition of the Microdrive/Compact Flash formatted with PC-partition scheme, the first partition must have part_type=27, contaning no filesystem, and the size must be equal to 8Mbyte, it will "raw load" into ram, and executed.The flash must be partitioned with a fixed scheme, and must contain two YaFFs v1 (v2 won't work) partitions. The first partition must be equal to 4Mbyte and must contain a file "kernel"Not yet understood if the tftpboot is limited below 8Mbyte, not clear, sometimes it works, sometimes it does notI could only speculate that RouterBoot opens an 8Mbyte window in the way it addresses RAM for the application.elf (the linux kernel in my case) to load and bootUnfortunately these things are not written anywhere, and that ... even in OpenWRT have never been clear.Patches are confusing, and, worse still, patches don't come with a note in their header.

author: DiTBho
author_rank: Super Contributor
timestamp: January 23, 2025, 09:36:58 am
content: Quote from: Nominal Animal on January 23, 2025, 12:58:34 amno, it's not compressed. Compression is one of the things that has never worked properly in the last ~20 years (2006-2025) on this board, and I don't have time to debug it at the moment.Better to run the kernel uncompressed, and eliminate another source of trouble.

author: DiTBho
author_rank: Super Contributor
timestamp: January 23, 2025, 09:41:27 am
content: Quote from: Nominal Animal on January 23, 2025, 12:58:34 amThis is one of the points of confusion, there are patches that force the first flash partition to 8Mbyte (kernel bult-in).I don't know if this thing works as a hack or if it ever worked.I've never seen it work in person as OpenWRT never officially supported it.There were random posts around the old web, 10 years ago, from random hackers, never confirmed.In any case it is not clear if there is really a constant to define that loading window.We know that every now and then something works, but it's all random.Except loading from the CF, which works quite reliable up to 8Mbyte.What worked, at the time, were kernels with sizes of 900Kbyte or at most 2.4Mbyte.Quote from: Nominal Animal on January 23, 2025, 12:58:34 amMy speculation, I guess is built-in defined in RouterBOOT.Frankly, I wish I could replace RouterBOOT with u-boot

author: Nominal Animal
author_rank: Super Contributor
timestamp: January 23, 2025, 07:13:08 pm
content: Quote from: DiTBho on January 23, 2025, 09:41:27 amCONFIG_PHYSICAL_START defines where the kernel will reside in physical RAM, it doesn't affect storage at all (even though the flash storage is addressed as memory also).I can't tell from OpenWRT whetherOpenWRT 18.06.9is the last version supported, or if you need to go back toBackfire 10.03.1. TheOldWikicontains related info. I woulddefinitelytest if these boot, and whether they have any unacceptable bugs in your use. DD-WRT2006 - 1203should also support RB532 (but unsure of RB532A); the latest sources for RB5xx were inrevision 22682(unchanged since 4767, I believe). The old docs arehere.(This is exactly why I appreciate companies like AMD, Intel, RockChip, Samsung, et cetera, that push support of their CPUs to vanilla Linux kernel support, instead of separate patches somewhere. Just think if you had someone collect and preserve these "historical" patches and their documentation at kernel.org, say in a timeline-like fashion you could limit to a specific architecture? Not just for those working on older devices, but also for recording the history of kernel patches for various devices.)

author: DiTBho
author_rank: Super Contributor
timestamp: January 23, 2025, 08:14:10 pm
content: Quote from: Nominal Animal on January 23, 2025, 07:13:08 pmMaybe I didn't explain myselfAll the kernels I've compiled have the same value of CONFIG_PHYSICAL_START.However:the slice0 of the flash can't be bigger than 4Mbyte -> you cannot physically store any kernel bigger than 4MByte in that slice.What I have stored here has always startedThere is no documentation telling you cannot tftpboot an elf bigger than 8MByte, but in practice it always fails. Smaller kernels usually boot.Except, kernels compiled with a built-in initramfs. They usually fail, no matter if smaller than 8Mbyte -> weirdThere is no documentation telling you cannot boot an elf bigger than 8MByte from the CF, but in practice it always fails, and you have to make the partition no bigger than 8Mbyte. Smaller kernels usually boot from the CF, including those compiled with a built-in ramrootfsSo ... same kernel, different booting methods, different results.

author: DiTBho
author_rank: Super Contributor
timestamp: January 23, 2025, 08:28:22 pm
content: I have several booting kernelskernel-2.06.032, legacy, it needs gcc-v4, it supports Yaffs-v1 -> size=~3.5Mbyte, stablekernel-2.06.037, legacy, it needs gcc-v4, it supports Yaffs-v1 -> size=~3.5Mbyte, stablekernel-4.04.197, can be compiled with modern gcc, it does not support Yaffs-v1 -> size=~7.3Mbyte, stablekernel-6.02.002, can be compiled with modern gcc, it does not support Yaffs-v1 -> size=~7.7Mbyte, experimental(optimized for space)However, I'm tired of wasting time with RooterBoot!I'm writing my own bootloader that will load the linux kernel.This way I bring the situation back to a deterministic state, where I know what happens under the hood.Today I've already written the bootloader skeleton and verified that RooterBoot loads it from the network and from flash, and starts it.It worksIn the next few days I'll implement the built-in lan, a udp/ip stack for the tftpboot, and a driver to access the CF.Different architecture, but for sure I will reuse some of the C code I wrote for the Soekris net5501(1) bootloader.(1) AMD Geode, x86-compatible

author: DiTBho
author_rank: Super Contributor
timestamp: January 24, 2025, 01:41:22 pm
content: This is the working status, after two days of work, just to get a 10 year old kernel back on its feetYaffs-v1 finally 100% worksCode:# mount/dev/sda3 on / type ext2 (rw,relatime,errors=continue,user_xattr)none on /sys type sysfs (rw,relatime)none on /proc type proc (rw,relatime)none on /dev/pts type devpts (rw,relatime,mode=600,ptmxmode=000)/dev/mtdblock0 on /mnt/mtd_p0 type yaffs (rw,relatime)/dev/mtdblock1 on /mnt/mtd_p1 type yaffs (rw,relatime)A lot of troubles to get at this pointa 10 years old OpenWrt-dev-kit does not work on modern GNU/linux, due to a lot of incompatibilities with the ecosystem, stating from gcc, to ncurses, to Makefiles, to perl, a lot of things have changed in 10 years and ... a I have a long list of patches that I created on the pathgetting started with yaffs-v1 is... hell. It's very difficult to be integrated into the kernel, confusing patches, too many revisions, no clean documentationCode:macmini2-intel kernel-2.06.032-mips-rb532 # ./mybuild-2024 2 compilingkernel-2.06.032(mips/rb532)| experimental Yaffs-v1| Use a Linux compiler or give up| Use gcc v4.* or give uptoolchain(mipsle-unknown-linux-gnu:2.21.1/4.5.3)-----------------------------------------------checking myhost as qualified_host ... successchecking .config ... successchecking blobs ... success-----------------------------------------------gadget_to_do(build) ... overlay/buildcleaning ............. donegadget_to_do(clean) ... kernel/cleanapp_machine=rb532building kernel ... success-----------------------------------------------gadget_to_do(binary) ... overlay/binarygadget_to_do(sweep) ... kernel/sweepapp_body =kernel.elfapp_size =3197011 byteapp_size_max=3900000 bytechecking size ... passedgadget_to_do(binary_report) ... kernel/binary_reportAs you can see, the final elf is smaller than 4Mbyte, so it can be copied to the first MTD slice mtd0Code:uc-rb532 /mnt/mtd_p1 # cat /proc/mtddev: size erasesize namemtd0: 00400000 00020000 "Routerboard NAND boot"mtd1: 07c00000 00020000 "rootfs"mtd0 (/dev/mtdblock0) is 4MbyteCode:major minor #blocks name31 0 4096 mtdblock031 1 126976 mtdblock18 0 990864 sda8 1 4336 sda18 2 16624 sda28 3 969360 sda3Code:mknod /dev/mtdblock0 b 31 0mknod /dev/mtdblock1 b 31 1Code:rb532 fix partition-info, set mtd0 to 8Mbyte, experimental--- arch/mips/rb532/devices.c+++ arch/mips/rb532/devices.c@@ -186,11 +186,11 @@ static struct platform_device nand_slot0static struct mtd_partition rb532_partition_info[] = {{- .name = "Routerboard NAND boot",+ .name = "kernel",.offset = 0,- .size = 4 * 1024 * 1024,+ .size = 8 * 1024 * 1024,}, {- .name = "rootfs",+ .name = "rootfs", /* ~ (128-8)8MB = 120MB */.offset = MTDPART_OFS_NXTBLK,.size = MTDPART_SIZ_FULL,}This is the patch I was talking about to resize /dev/mtdblock0 to 8Mbyte.Not yet tried

author: DiTBho
author_rank: Super Contributor
timestamp: January 24, 2025, 01:50:09 pm
content: I am working on Vanilla kernel v2.6.32, integrating patches from OpenWRT, and my own patches.The rootfs is made by Catalyst(Gentoo), using an old (2009) uclibc stage 1-3.I also have my super-stable 2009 stage4/glibc with gcc v4.1.2, and the new 2020 stage4/glibc with gcc-v7.The last one is more than suitable also for therbm33grouter-In the meantime I continue to develop my bootloader too.It will be installed in the first slice of the flash, mtd0But I need Yaffs-v1 to do this because Routerboot at startup expects ...... the flash to be partitioned as above and the first partition to be formatted Yaffs-v1Yaffs-v2 is not compatible with Yaffs-v1

author: DiTBho
author_rank: Super Contributor
timestamp: January 26, 2025, 04:53:52 pm
content: Anyone use it? Anyone interested?Let me knowfurther discussion on the development of { mtd, disk }, seehere

author: DiTBho
author_rank: Super Contributor
timestamp: February 03, 2025, 08:12:20 pm
content: The rb532a doesn't accept some MicroDrives.There is no documentation about.It seems the board turns off the motors if the MicroDrives doesn't match some criteria.I don't know which gpio/port controls the motor enable

author: DiTBho
author_rank: Super Contributor
timestamp: February 08, 2025, 04:00:57 pm
content: So, I traded in some of my old Turbo Pascal programming books for an rb564 daughterboard, which adds sixVia-Rhine ethernet chips, turning the rb532a into a "serious" router!Code:Board Info:Board type: 532AFirmware version: 2.12CPU frequency: 399 MHzMemory size: 64 MBeth1 MAC address: 00:0C:42:0E:9F:1Beth2 MAC address: 00:0C:42:0E:9F:1Ceth3 MAC address: 00:0C:42:0E:9F:1D-------------------------------------------------eth4 MAC address: 00:0C:42:03:58:FBeth5 MAC address: 00:0C:42:03:58:FCeth6 MAC address: 00:0C:42:03:58:FDeth7 MAC address: 00:0C:42:03:58:FEeth8 MAC address: 00:0C:42:03:58:FFeth9 MAC address: 00:0C:42:03:59:00However... there is one big problem with PCI ...Code:eth0: korinavia-rhine 0000:00:02.0: enabling device (0080 -> 0083)via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:00:03.0: enabling device (0080 -> 0083)via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000pci 0000:00:06.0: enabling device (0000 -> 0003)via-rhine 0000:01:02.0: enabling device (0080 -> 0083)via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:03.0: enabling device (0080 -> 0083)via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:04.0: enabling device (0080 -> 0083)via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:05.0: enabling device (0080 -> 0083)via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:06.0: enabling device (0080 -> 0082)via-rhine 0000:01:06.0: Insufficient PCI resources, abortingvia-rhine: probe of 0000:01:06.0 failed with error -5via-rhine 0000:01:07.0: enabling device (0080 -> 0082)via-rhine 0000:01:07.0: Insufficient PCI resources, abortingvia-rhine: probe of 0000:01:07.0 failed with error -5rb532 / # ifconfig -aeth0 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1bBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)Interrupt:40eth1 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1cBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth2 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1dBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth3 Link encap:Ethernet HWaddr 00:0c:42:03:58:fbBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth4 Link encap:Ethernet HWaddr 00:0c:42:03:58:fcBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth5 Link encap:Ethernet HWaddr 00:0c:42:03:58:fdBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth6 Link encap:Ethernet HWaddr 00:0c:42:03:58:feBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)lo Link encap:Local LoopbackLOOPBACK MTU:65536 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)rb532 / #eth0 is the SoC built-in ethernet.eth1 and eth2 are on the rb532eth3 to eth6 are on the rb564 expansionbut some of the new ethernets { eth7, eth8 } on the rb564 expansion are not initiazlied since the they return "Insufficient PCI resources, aborting"... umm, same behavior from kernel 2.6.32 to 6.02.*

author: Nominal Animal
author_rank: Super Contributor
timestamp: February 08, 2025, 05:09:00 pm
content: Dammit, that looks annoying, considering rb564 is specifically suggested as an add-on for rb532a.Do you happen to have the RouterOS (from Mikrotik) license for the rb532a, to compare the (verbose) kernel log and reports to? 6.32.2 (2015-Sep-17 15:20) is the latest version (routeros,packages; but also seewww.mikrotik-software.de/downloads/) with mipsle support, I believe. As I understand it, it should have full support for rb564. I suspect they do it by somehow overlapping the PCI resources, perhaps with kernel driver options.Heh, your kernel questions regarding rb532a pop up at lore.kernel.org/linux-mips.vger.kernel.org if one does a related search for Device Tree and such.(I've been seriously eyeingRadxa Rock 3B, with two GbE, a M.2 B-key with SIM socket (I'll need a plain passive mini-PCIe-to-M.2-B-key adapter though), and a M.2 M-key for NVMe on the backside. Rock 5 ITX and Rock 5T would be even nicer, dual NVMes and all, but they're outside my meager budget. This is to replace the Mikrotik RBM33G with MT7621A/MMIPS I have, being a 4G/LTE router with security cam storage on 1TB NVMe. The additional benefit with the Rock 3B is that it has a HDMI connector for a TV for nontechnical users to browse the stored footage. Anyway, if you only have an USB 2.0 connection,ADT-Link WS17is perfect for a mini-PCIe 4G/5G/LTE modem: the documentation includes the schematic, so one can up the voltage to 3.8V for lower current with higher power antennas by just replacing one SMD resistor! For USB 3.0, one must use WS18, though.)

author: DiTBho
author_rank: Super Contributor
timestamp: February 08, 2025, 08:01:14 pm
content: Quote from: Nominal Animal on February 08, 2025, 05:09:00 pmyup, very annoying considering how expensive the rb564 was (>>90 euro), also RouterOS is based on the Linux kernel, therefore I was expecting less troubles.The rb532a is full or problems, not only in recent kernel v6.02 branches, but also in those from the days (2006--2009) when rb532a was new.OpenWRT has been the only source of patches, it has done a great job, but you can expect only basic stuff to work.Quote from: Nominal Animal on February 08, 2025, 05:09:00 pmI have two rb532a boardsboard#0, fw-v2.8, bought in 2008, but I erased the NAND flash many years agoboard#1, fw-v2.12, fresh bought, 20 days ago, never used, routerOS should be in the NAND flashThis is a board in a sealed bag, unopened stock without box. There is no paper support included.I don't have any password/doc/whatever/license for RouterOS.I bought a second board because #0 has been working for many many hoursMTBF(2025 - 2008) =I've done everything with it, several thousand experiments, and I think it might die.I'm mostly concerned about the capacitors, but also the connector part.In addition to this, having two allows me to test solutions in parallel.#a - On one side the linux kernel, on the other the monitor I'm writing#b - On one side the linux kernel without the rb564, on the other the linux kernel with the rb564

author: DiTBho
author_rank: Super Contributor
timestamp: February 08, 2025, 08:17:31 pm
content: Quote from: Nominal Animal on February 08, 2025, 05:09:00 pm... feeling of abandonment, no one responding.I also tried to contact the names of the people I see signing the patches directly.No response.Dunno whyQuote from: Nominal Animal on February 08, 2025, 05:09:00 pmThe rbm33g is much much faster than the rb532a, however it doesn't have the samecharm.but it is the perfect "next step" with MIPS routers.I mean, if you want to write your own OS_less application, the rbm33g adds two cores to manage.Two cores means more complexity.

author: DiTBho
author_rank: Super Contributor
timestamp: February 08, 2025, 08:21:57 pm
content: the Ethernet chips on the rb564 are managed by drivers/net/ethernet/via/via-rhine.c(torvalds' linux github)

author: Nominal Animal
author_rank: Super Contributor
timestamp: February 08, 2025, 10:06:44 pm
content: Have youCompiled a test kernel withCONFIG_VIA_RHINE_MMIO?Modified the error todev_err(hwdev, "Insufficient PCI resources (%d and %d out of %d), aborting\n", pci_resource_len(pdev, 0), pci_resource_len(pdev, 1), io_size);?Disabled the sanity check that emits the error?indrivers/net/ethernet/via/via-rhine.c?I think 1. does not changes anything; that 2. would be informative; and that 3. might actually get it to work.For clarity, it would be useful to move the error to the actual pci region requests, ie. change the entire function intoCode:static int rhine_init_one_pci(struct pci_dev *pdev,const struct pci_device_id *ent){struct device *hwdev = &pdev->dev;int rc;long pioaddr, memaddr;void __iomem *ioaddr;int io_size = pdev->revision < VTunknown0 ? 128 : 256;/* This driver was written to use PCI memory space. Some early versions* of the Rhine may only work correctly with I/O space accesses.* TODO: determine for which revisions this is true and assign the flag*in code as opposed to this Kconfig option (???)*/#ifdef CONFIG_VIA_RHINE_MMIOu32 quirks = rqNeedEnMMIO;#elseu32 quirks = 0;#endifrc = pci_enable_device(pdev);if (rc)goto err_out;if (pdev->revision < VTunknown0) {quirks |= rqRhineI;} else if (pdev->revision >= VT6102) {quirks |= rqWOL | rqForceReset;if (pdev->revision < VT6105) {quirks |= rqStatusWBRace;} else {quirks |= rqIntPHY;if (pdev->revision >= VT6105_B0)quirks |= rq6patterns;if (pdev->revision >= VT6105M)quirks |= rqMgmt;}}pioaddr = pci_resource_start(pdev, 0);memaddr = pci_resource_start(pdev, 1);pci_set_master(pdev);rc = pci_request_regions(pdev, DRV_NAME);if (rc) {dev_err(hwdev, "Insufficient PCI resources (%d and %d out of %d), aborting\n",pci_resource_len(pdev, 0), pci_resource_len(pdev, 1), io_size);goto err_out_pci_disable;}ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);if (!ioaddr) {rc = -EIO;dev_err(hwdev,"ioremap failed for device %s, region 0x%X @ 0x%lX\n",dev_name(hwdev), io_size, memaddr);goto err_out_free_res;}enable_mmio(pioaddr, quirks);rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks);if (rc)goto err_out_unmap;rc = rhine_init_one_common(&pdev->dev, quirks,pioaddr, ioaddr, pdev->irq);if (!rc)return 0;err_out_unmap:pci_iounmap(pdev, ioaddr);err_out_free_res:pci_release_regions(pdev);err_out_pci_disable:pci_disable_device(pdev);err_out:return rc;}If that causes the last two Ethernet interfaces to fail with ioremap failed, or the two lock up during operation, a (better!) possibility is that the fourth interface per chip can still be used in PIO mode:Code:static int rhine_init_one_pci(struct pci_dev *pdev,const struct pci_device_id *ent){struct device *hwdev = &pdev->dev;int rc;long pioaddr, memaddr;void __iomem *ioaddr;int io_size = pdev->revision < VTunknown0 ? 128 : 256;/* This driver was written to use PCI memory space. Some early versions* of the Rhine may only work correctly with I/O space accesses.* TODO: determine for which revisions this is true and assign the flag*in code as opposed to this Kconfig option (???)*/#ifdef CONFIG_VIA_RHINE_MMIOu32 quirks = rqNeedEnMMIO;#elseu32 quirks = 0;#endifrc = pci_enable_device(pdev);if (rc)goto err_out;if (pdev->revision < VTunknown0) {quirks |= rqRhineI;} else if (pdev->revision >= VT6102) {quirks |= rqWOL | rqForceReset;if (pdev->revision < VT6105) {quirks |= rqStatusWBRace;} else {quirks |= rqIntPHY;if (pdev->revision >= VT6105_B0)quirks |= rq6patterns;if (pdev->revision >= VT6105M)quirks |= rqMgmt;}}// If MMIO mapping is not possible, use PIO.if ((pci_resource_len(pdev, 0) < io_size) ||(pci_resource_len(pdev, 1) < io_size))quirks |= rqNeedEnMMIO;pioaddr = pci_resource_start(pdev, 0);memaddr = pci_resource_start(pdev, 1);pci_set_master(pdev);rc = pci_request_regions(pdev, DRV_NAME);if (rc) {dev_err(hwdev, "Insufficient PCI resources (%d and %d out of %d), aborting\n",pci_resource_len(pdev, 0), pci_resource_len(pdev, 1), io_size);goto err_out_pci_disable;}ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);if (!ioaddr) {rc = -EIO;dev_err(hwdev,"ioremap failed for device %s, region 0x%X @ 0x%lX\n",dev_name(hwdev), io_size, memaddr);goto err_out_free_res;}enable_mmio(pioaddr, quirks);rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks);if (rc)goto err_out_unmap;rc = rhine_init_one_common(&pdev->dev, quirks,pioaddr, ioaddr, pdev->irq);if (!rc)return 0;err_out_unmap:pci_iounmap(pdev, ioaddr);err_out_free_res:pci_release_regions(pdev);err_out_pci_disable:pci_disable_device(pdev);err_out:return rc;}Note that it has beendecadessince I last played with Via ethernet drivers, so I could be way off base here. I do not believe the above can harm anything, though, because it just omits the "sanity check" and last one conditionalizes the PIO option.I did find a datasheet for VT6105M, and it is limited to 256 PCI addresses; and I suspect the PIO workaround is quite possible the solution Mikrotik used.Oh, and note that AFAIK RouterOS has a24-hour/30-day trial you might be able to usewith e.g. 6.32.2.

author: DiTBho
author_rank: Super Contributor
timestamp: February 09, 2025, 04:36:38 pm
content: Quote from: Nominal Animal on February 08, 2025, 10:06:44 pmdoes not changes anything

author: DiTBho
author_rank: Super Contributor
timestamp: February 09, 2025, 04:38:30 pm
content: Quote from: Nominal Animal on February 08, 2025, 10:06:44 pmCONFIG_VIA_RHINE_MMIO disabledCode:PCI host bridge to bus 0000:00pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]pci_bus 0000:00: root bus resource [io 0x18800000-0x188fffff]pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]pci 0000:00:00.0: [111d:0000] type 00 class 0x000000pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)pci 0000:00:02.0: [1106:3106] type 00 class 0x020000pci 0000:00:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:02.0: supports D1 D2pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:03.0: [1106:3106] type 00 class 0x020000pci 0000:00:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:03.0: supports D1 D2pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]pci 0000:00:06.0: [3388:0031] type 01 class 0x060400pci 0000:00:06.0: supports D1 D2pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hotpci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguringpci_bus 0000:01: extended config space not accessiblepci 0000:01:02.0: [1106:3106] type 00 class 0x020000pci 0000:01:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:02.0: supports D1 D2pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:03.0: [1106:3106] type 00 class 0x020000pci 0000:01:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:03.0: supports D1 D2pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:04.0: [1106:3106] type 00 class 0x020000pci 0000:01:04.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:04.0: supports D1 D2pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:05.0: [1106:3106] type 00 class 0x020000pci 0000:01:05.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:05.0: supports D1 D2pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:06.0: [1106:3106] type 00 class 0x020000pci 0000:01:06.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:06.0: supports D1 D2pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:07.0: [1106:3106] type 00 class 0x020000pci 0000:01:07.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:07.0: supports D1 D2pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3coldpci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]pci 0000:00:06.0: BAR 7: assigned [io 0x18800000-0x18800fff]pci 0000:00:02.0: BAR 0: assigned [io 0x18801000-0x188010ff]pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]pci 0000:00:03.0: BAR 0: assigned [io 0x18801400-0x188014ff]pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]pci 0000:01:02.0: BAR 0: assigned [io 0x18800000-0x188000ff]pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]pci 0000:01:03.0: BAR 0: assigned [io 0x18800400-0x188004ff]pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]pci 0000:01:04.0: BAR 0: assigned [io 0x18800800-0x188008ff]pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]pci 0000:01:05.0: BAR 0: assigned [io 0x18800c00-0x18800cff]pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]pci 0000:01:06.0: BAR 0: no space for [io size 0x0100]pci 0000:01:06.0: BAR 0: failed to assign [io size 0x0100]pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]pci 0000:01:07.0: BAR 0: no space for [io size 0x0100]pci 0000:01:07.0: BAR 0: failed to assign [io size 0x0100]pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]pci 0000:00:06.0: PCI bridge to [bus 01]pci 0000:00:06.0: bridge window [io 0x18800000-0x18800fff]pci 0000:00:06.0: bridge window [mem 0x50000000-0x500fffff]Code:via-rhine 0000:00:02.0: enabling device (0080 -> 0083)via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:00:03.0: enabling device (0080 -> 0083)via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000pci 0000:00:06.0: enabling device (0000 -> 0003)via-rhine 0000:01:02.0: enabling device (0080 -> 0083)via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:03.0: enabling device (0080 -> 0083)via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:04.0: enabling device (0080 -> 0083)via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:05.0: enabling device (0080 -> 0083)via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:06.0: enabling device (0080 -> 0082)via-rhine 0000:01:06.0: ioremap failed for device 0000:01:06.0, region 0x100 @ 0x50000400via-rhine: probe of 0000:01:06.0 failed with error -5via-rhine 0000:01:07.0: enabling device (0080 -> 0082)via-rhine 0000:01:07.0: ioremap failed for device 0000:01:07.0, region 0x100 @ 0x50000500via-rhine: probe of 0000:01:07.0 failed with error -5-----CONFIG_VIA_RHINE_MMIO enabledCode:PCI host bridge to bus 0000:00pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]pci_bus 0000:00: root bus resource [io 0x18800000-0x188fffff]pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]pci 0000:00:00.0: [111d:0000] type 00 class 0x000000pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)pci 0000:00:02.0: [1106:3106] type 00 class 0x020000pci 0000:00:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:02.0: supports D1 D2pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:03.0: [1106:3106] type 00 class 0x020000pci 0000:00:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:03.0: supports D1 D2pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]pci 0000:00:06.0: [3388:0031] type 01 class 0x060400pci 0000:00:06.0: supports D1 D2pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hotpci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguringpci_bus 0000:01: extended config space not accessiblepci 0000:01:02.0: [1106:3106] type 00 class 0x020000pci 0000:01:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:02.0: supports D1 D2pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:03.0: [1106:3106] type 00 class 0x020000pci 0000:01:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:03.0: supports D1 D2pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:04.0: [1106:3106] type 00 class 0x020000pci 0000:01:04.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:04.0: supports D1 D2pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:05.0: [1106:3106] type 00 class 0x020000pci 0000:01:05.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:05.0: supports D1 D2pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:06.0: [1106:3106] type 00 class 0x020000pci 0000:01:06.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:06.0: supports D1 D2pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:07.0: [1106:3106] type 00 class 0x020000pci 0000:01:07.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:07.0: supports D1 D2pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3coldpci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]pci 0000:00:06.0: BAR 7: assigned [io 0x18800000-0x18800fff]pci 0000:00:02.0: BAR 0: assigned [io 0x18801000-0x188010ff]pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]pci 0000:00:03.0: BAR 0: assigned [io 0x18801400-0x188014ff]pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]pci 0000:01:02.0: BAR 0: assigned [io 0x18800000-0x188000ff]pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]pci 0000:01:03.0: BAR 0: assigned [io 0x18800400-0x188004ff]pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]pci 0000:01:04.0: BAR 0: assigned [io 0x18800800-0x188008ff]pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]pci 0000:01:05.0: BAR 0: assigned [io 0x18800c00-0x18800cff]pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]pci 0000:01:06.0: BAR 0: no space for [io size 0x0100]pci 0000:01:06.0: BAR 0: failed to assign [io size 0x0100]pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]pci 0000:01:07.0: BAR 0: no space for [io size 0x0100]pci 0000:01:07.0: BAR 0: failed to assign [io size 0x0100]pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]pci 0000:00:06.0: PCI bridge to [bus 01]pci 0000:00:06.0: bridge window [io 0x18800000-0x18800fff]pci 0000:00:06.0: bridge window [mem 0x50000000-0x500fffff]Code:via-rhine 0000:00:02.0: enabling device (0080 -> 0083)via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:00:03.0: enabling device (0080 -> 0083)via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000pci 0000:00:06.0: enabling device (0000 -> 0003)via-rhine 0000:01:02.0: enabling device (0080 -> 0083)via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:03.0: enabling device (0080 -> 0083)via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:04.0: enabling device (0080 -> 0083)via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:05.0: enabling device (0080 -> 0083)via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:06.0: enabling device (0080 -> 0082)via-rhine 0000:01:06.0: MMIO do not match PIO  (1a != ff)via-rhine: probe of 0000:01:06.0 failed with error -5via-rhine 0000:01:07.0: enabling device (0080 -> 0082)via-rhine 0000:01:07.0: MMIO do not match PIO  (1a != ff)ata1.00: CFA: HMS360404D5CF00, DN4OCA2A, max PIO4ata1.00: 7999488 sectors, multi 0: LBAvia-rhine: probe of 0000:01:07.0 failed with error -5

author: DiTBho
author_rank: Super Contributor
timestamp: February 09, 2025, 04:44:03 pm
content: Quote from: Nominal Animal on February 08, 2025, 10:06:44 pmCONFIG_VIA_RHINE_MMIO disabledCode:PCI host bridge to bus 0000:00pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]pci_bus 0000:00: root bus resource [io 0x18800000-0x188fffff]pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]pci 0000:00:00.0: [111d:0000] type 00 class 0x000000pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)pci 0000:00:02.0: [1106:3106] type 00 class 0x020000pci 0000:00:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:02.0: supports D1 D2pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:03.0: [1106:3106] type 00 class 0x020000pci 0000:00:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:03.0: supports D1 D2pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]pci 0000:00:06.0: [3388:0031] type 01 class 0x060400pci 0000:00:06.0: supports D1 D2pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hotpci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguringpci_bus 0000:01: extended config space not accessiblepci 0000:01:02.0: [1106:3106] type 00 class 0x020000pci 0000:01:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:02.0: supports D1 D2pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:03.0: [1106:3106] type 00 class 0x020000pci 0000:01:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:03.0: supports D1 D2pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:04.0: [1106:3106] type 00 class 0x020000pci 0000:01:04.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:04.0: supports D1 D2pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:05.0: [1106:3106] type 00 class 0x020000pci 0000:01:05.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:05.0: supports D1 D2pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:06.0: [1106:3106] type 00 class 0x020000pci 0000:01:06.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:06.0: supports D1 D2pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:07.0: [1106:3106] type 00 class 0x020000pci 0000:01:07.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:07.0: supports D1 D2pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3coldpci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]pci 0000:00:06.0: BAR 7: assigned [io 0x18800000-0x18800fff]pci 0000:00:02.0: BAR 0: assigned [io 0x18801000-0x188010ff]pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]pci 0000:00:03.0: BAR 0: assigned [io 0x18801400-0x188014ff]pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]pci 0000:01:02.0: BAR 0: assigned [io 0x18800000-0x188000ff]pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]pci 0000:01:03.0: BAR 0: assigned [io 0x18800400-0x188004ff]pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]pci 0000:01:04.0: BAR 0: assigned [io 0x18800800-0x188008ff]pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]pci 0000:01:05.0: BAR 0: assigned [io 0x18800c00-0x18800cff]pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]pci 0000:01:06.0: BAR 0: no space for [io size 0x0100]pci 0000:01:06.0: BAR 0: failed to assign [io size 0x0100]pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]pci 0000:01:07.0: BAR 0: no space for [io size 0x0100]pci 0000:01:07.0: BAR 0: failed to assign [io size 0x0100]pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]pci 0000:00:06.0: PCI bridge to [bus 01]pci 0000:00:06.0: bridge window [io 0x18800000-0x18800fff]pci 0000:00:06.0: bridge window [mem 0x50000000-0x500fffff]Code:via-rhine 0000:00:02.0: enabling device (0080 -> 0083)via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:00:03.0: enabling device (0080 -> 0083)via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000pci 0000:00:06.0: enabling device (0000 -> 0003)via-rhine 0000:01:02.0: enabling device (0080 -> 0083)via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:03.0: enabling device (0080 -> 0083)via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:04.0: enabling device (0080 -> 0083)via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:05.0: enabling device (0080 -> 0083)via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:06.0: enabling device (0080 -> 0082)via-rhine 0000:01:06.0: MMIO do not match PIO  (1a != ff)via-rhine: probe of 0000:01:06.0 failed with error -5via-rhine 0000:01:07.0: enabling device (0080 -> 0082)via-rhine 0000:01:07.0: MMIO do not match PIO  (1a != ff)

author: Nominal Animal
author_rank: Super Contributor
timestamp: February 09, 2025, 08:27:59 pm
content: My suggestedrqEnMMIOquirk is invalid, because the bridge ran out of I/O addresses, not memory addresses.Quote from: DiTBho on February 09, 2025, 04:38:30 pmThe issue is that the bridge I/O address window is only 0x18800000-0x18800fff (4k), but the kernel needs to stuff eight 1k windows into it. (The I/O address alignment is 0x400 = 1024, i.e. each device will get their own I/O address range aligned to a multiple of 0x400 = 1024.)The solution would be to increase its I/O window to 8k, so thatpci 0000:00:06.0: BAR 7: assigned [io 0x18800000-0x18800fff]becomespci 0000:00:06.0: BAR 7: assigned [io 0x18800000-0x18801fff]pushing 0000:00:02.0 and 0000:00:03.0 upwards accordingly. The PCI root has been assigned [io 0x18800000-0x188fffff], so there is plenty of I/O address space left; the kernel just didn't assign enough to the bridge!There is no physical reason for such a small I/O address range; the bridge will be able to map at least 64k, if not more. The bug is kernel not accounting enough I/O addresses in the 0000:01 bus. One reason could be thatpci_hotplug_io_sizeis too small. Could you check by booting with kernel command linehpiosize=8192to verify?I'm not absolutely sure if 0000:00:06.0 is a hotplug bridge, so that might not fix the issue. As a cruder test, you could modifydrivers/pci/setup-bus.c:__pci_bus_size_bridges(), in theswitch (hdr_type),case PCI_HEADER_TYPE_BRIDGE:, just before thefallthrough;, addingadditional_io_size += 4096; // Add 4k I/O address space to the bridgeThe practical result of this change is that all PCI bridges in your system will reserve an extra 4096 I/O addresses.Both of these changes should only affect 0000:00:06.0 (plus the I/O address ranges for 0000:00:02.0 and 0000:00:03.0, pushing them higher in the address spaces); seeing the specific change in the I/O mapping would be very informative. Could you test these? 🤗

author: DiTBho
author_rank: Super Contributor
timestamp: February 16, 2025, 01:44:37 am
content: Code:Add 8k I/O address space to the bridge--- drivers/pci/setup-bus.c.original 2025-02-16 02:41:09.966000000 -0000+++ drivers/pci/setup-bus.c 2025-02-16 02:41:09.955000000 -0000@@ -1241,6 +1241,9 @@hdr_type = bus->self->hdr_type;}+ additional_io_size += 4096; // suppa Add 4k I/O address space to the bridge+ additional_io_size += 4096; // suppa Add 4k I/O address space to the bridge+switch (hdr_type) {case PCI_HEADER_TYPE_CARDBUS:/* Don't size CardBuses yet */Code:PCI host bridge to bus 0000:00pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]pci_bus 0000:00: root bus resource [io 0x18800000-0x188fffff]pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]pci 0000:00:00.0: [111d:0000] type 00 class 0x000000pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)pci 0000:00:02.0: [1106:3106] type 00 class 0x020000pci 0000:00:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:02.0: supports D1 D2pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:03.0: [1106:3106] type 00 class 0x020000pci 0000:00:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:03.0: supports D1 D2pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]pci 0000:00:06.0: [3388:0031] type 01 class 0x060400pci 0000:00:06.0: supports D1 D2pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hotpci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguringpci_bus 0000:01: extended config space not accessiblepci 0000:01:02.0: [1106:3106] type 00 class 0x020000pci 0000:01:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:02.0: supports D1 D2pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:03.0: [1106:3106] type 00 class 0x020000pci 0000:01:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:03.0: supports D1 D2pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:04.0: [1106:3106] type 00 class 0x020000pci 0000:01:04.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:04.0: supports D1 D2pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:05.0: [1106:3106] type 00 class 0x020000pci 0000:01:05.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:05.0: supports D1 D2pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:06.0: [1106:3106] type 00 class 0x020000pci 0000:01:06.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:06.0: supports D1 D2pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:07.0: [1106:3106] type 00 class 0x020000pci 0000:01:07.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:07.0: supports D1 D2pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3coldpci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]pci 0000:00:06.0: BAR 7: assigned [io 0x18800000-0x18801fff]pci 0000:00:02.0: BAR 0: assigned [io 0x18802000-0x188020ff]pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]pci 0000:00:03.0: BAR 0: assigned [io 0x18802400-0x188024ff]pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]pci 0000:01:02.0: BAR 0: assigned [io 0x18800000-0x188000ff]pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]pci 0000:01:03.0: BAR 0: assigned [io 0x18800400-0x188004ff]pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]pci 0000:01:04.0: BAR 0: assigned [io 0x18800800-0x188008ff]pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]pci 0000:01:05.0: BAR 0: assigned [io 0x18800c00-0x18800cff]pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]pci 0000:01:06.0: BAR 0: assigned [io 0x18801000-0x188010ff]pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]pci 0000:01:07.0: BAR 0: assigned [io 0x18801400-0x188014ff]pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]pci 0000:00:06.0: PCI bridge to [bus 01]pci 0000:00:06.0: bridge window [io 0x18800000-0x18801fff]pci 0000:00:06.0: bridge window [mem 0x50000000-0x500fffff]Code:via-rhine 0000:00:02.0: enabling device (0080 -> 0083)via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:00:03.0: enabling device (0080 -> 0083)via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000pci 0000:00:06.0: enabling device (0000 -> 0003)via-rhine 0000:01:02.0: enabling device (0080 -> 0083)via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:03.0: enabling device (0080 -> 0083)via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:04.0: enabling device (0080 -> 0083)via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:05.0: enabling device (0080 -> 0083)via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:06.0: enabling device (0080 -> 0083)via-rhine 0000:01:06.0 eth7: VIA Rhine III at (ptrval), 00:0c:42:03:58:ff, IRQ 141via-rhine 0000:01:06.0 eth7: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:07.0: enabling device (0080 -> 0083)via-rhine 0000:01:07.0 eth8: VIA Rhine III at (ptrval), 00:0c:42:03:59:00, IRQ 143via-rhine 0000:01:07.0 eth8: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000Code:rb532 / # ifconfig -aeth0 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1bBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)Interrupt:40eth1 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1cBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth2 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1dBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth3 Link encap:Ethernet HWaddr 00:0c:42:03:58:fbBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth4 Link encap:Ethernet HWaddr 00:0c:42:03:58:fcBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth5 Link encap:Ethernet HWaddr 00:0c:42:03:58:fdBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth6 Link encap:Ethernet HWaddr 00:0c:42:03:58:feBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth7 Link encap:Ethernet HWaddr 00:0c:42:03:58:ffBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth8 Link encap:Ethernet HWaddr 00:0c:42:03:59:00BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)lo Link encap:Local LoopbackLOOPBACK MTU:65536 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)Code:cat .config | grep HOTPLUG_PCICONFIG_HOTPLUG_PCI=y# CONFIG_HOTPLUG_PCI_CPCI is not set# CONFIG_HOTPLUG_PCI_SHPC is not setCode:rb532a # cat /proc/cmdlineconsole=ttyS0,9600 gpio=16383 mem=64M init=/bin/bash rootfstype=xfs ro acpi=off hpiosize=8192Note that the modified lines are a bit different from what you suggested.This way it works.It still seems like something is wrongCode:/* The root bus? */if (pci_is_root_bus(bus)) {host = to_pci_host_bridge(bus->bridge);if (!host->size_windows)return;pci_bus_for_each_resource(bus, pref, i)if (pref && (pref->flags & IORESOURCE_PREFETCH))break;hdr_type = -1; /* Intentionally invalid - not a PCI device. */} else {pref = &bus->self->resource;hdr_type = bus->self->hdr_type;}additional_io_size += 4096; // suppa Add 4k I/O address space to the bridgeadditional_io_size += 4096; // suppa Add 4k I/O address space to the bridgeswitch (hdr_type) {case PCI_HEADER_TYPE_CARDBUS:/* Don't size CardBuses yet */break;case PCI_HEADER_TYPE_BRIDGE:pci_bridge_check_ranges(bus);if (bus->self->is_hotplug_bridge) {additional_io_size = pci_hotplug_io_size;additional_mmio_size = pci_hotplug_mmio_size;additional_mmio_pref_size = pci_hotplug_mmio_pref_size;}fallthrough;

author: DiTBho
author_rank: Super Contributor
timestamp: February 16, 2025, 01:50:08 am
content: Anyway, very happy for all the things you can do with 9 network ports

author: Nominal Animal
author_rank: Super Contributor
timestamp: February 16, 2025, 11:04:52 am
content: Ah-ha, so it is just the PCI I/O bar size calculation that was the issue.Have you checked UDP traffic, using a short cable,nc/ncat(or bash script using/dev/udp/address/port) and link-local/fixed-IP addressing, to verify the Ethernet ports work?The hack is incorrect, because it adds to all bridges, including the root bridge; and root bridges are special as theymay not be sizable.Also, the kernel parameter to test (me fail, forgotpci=prefix) is actuallypci=hpiosize=8192If the log does not contain amax bus depth:Npci_try_num:Nline, then the kernel just doesn't trigger reallocation of resources, andpci=realloc=onmight fix it.It is possible you need both, i.e.pci=realloc=on,hpiosize=8192might fix it.(If so, then it is a system configuration matter, not an actual bug.)If none of the above on an unpatched kernel fixes the issue, addingpci_info(bus->self, "for bridge window %pR, size %llu, size1 %llu, min_size %llu, add_size %llu, children_add_size %llu\n", b_res, (unsigned long long)size, (unsigned long long)size1, (unsigned long long)min_size, (unsigned long long)add_size, (unsigned long long)children_add_size);tolinux-6.0.2/drivers/pci/setup-bus.c:pbus_size_io() line 922, andpci_info(bus->self, "bridge window at %pR\n", b_res);to just before the end of that same function, and seeing allpci 0000:lines from the boot log, would help pinpoint the issue.(If there is e.g. apci: 0000:00:06.00 bridge window at [io 0x0000-0x05ff](or similar, with a 0x600 aperture), then there is a bug in how bridge I/O address space requirement is calculated (not taking correctly into account that each device needs their own window in the bridge). If there is only onepci: 0000:00:06.00 bridge window at [io 0x0000-0x0fff](or similar, with a 0x1000 aperture), andpci=realloc=on,hpiosize=8192does not fix it, then the reallocation mechanism doesn't get triggered at all, and the fix is a simple early PCI quirk to PCI ID 3388:0031 for rb564.)If the above does not add light to the matter, the crude but minimally intrusive way to fix this would be to reuse the hotplug default allocation mechanism:Code:--- linux-6.0.2.original/drivers/pci/pci.c2025-02-16 07:18:17.722611122 +0200+++ linux-6.0.2/drivers/pci/pci.c2025-02-16 12:12:42.349706176 +0200@@ -84,6 +84,10 @@int pci_domains_supported = 1;#endif+#define DEFAULT_BRIDGE_IO_SIZE(0)+/* pci=bridgeiosize=nn can override this */+unsigned long pci_bridge_io_size = DEFAULT_BRIDGE_IO_SIZE;+#define DEFAULT_CARDBUS_IO_SIZE(256)#define DEFAULT_CARDBUS_MEM_SIZE(64*1024*1024)/* pci=cbmemsize=nnM,cbiosize=nn can override this */@@ -93,7 +97,7 @@#define DEFAULT_HOTPLUG_IO_SIZE(256)#define DEFAULT_HOTPLUG_MMIO_SIZE(2*1024*1024)#define DEFAULT_HOTPLUG_MMIO_PREF_SIZE(2*1024*1024)-/* hpiosize=nn can override this */+/* pci=hpiosize=nn can override this */unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;/** pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,@@ -6870,6 +6874,8 @@resource_alignment_param = str + 19;} else if (!strncmp(str, "ecrc=", 5)) {pcie_ecrc_get_policy(str + 5);+} else if (!strncmp(str, "bridgeiosize=", 13)) {+pci_bridge_io_size = memparse(str + 13, &str);} else if (!strncmp(str, "hpiosize=", 9)) {pci_hotplug_io_size = memparse(str + 9, &str);} else if (!strncmp(str, "hpmmiosize=", 11)) {--- linux-6.0.2.original/drivers/pci/pci.h2025-02-16 12:54:42.204863718 +0200+++ linux-6.0.2/drivers/pci/pci.h2025-02-16 12:55:03.924903542 +0200@@ -178,6 +178,8 @@extern const struct device_type pci_dev_type;extern const struct attribute_group *pci_bus_groups[];+extern unsigned long pci_bridge_io_size;+extern unsigned long pci_hotplug_io_size;extern unsigned long pci_hotplug_mmio_size;extern unsigned long pci_hotplug_mmio_pref_size;--- linux-6.0.2.original/drivers/pci/setup-bus.c2025-02-16 07:19:07.278591151 +0200+++ linux-6.0.2/drivers/pci/setup-bus.c2025-02-16 12:19:05.474162483 +0200@@ -1252,6 +1252,9 @@additional_io_size = pci_hotplug_io_size;additional_mmio_size = pci_hotplug_mmio_size;additional_mmio_pref_size = pci_hotplug_mmio_pref_size;+} else {+if (bus->self->io_window)+additional_io_size = pci_bridge_io_size;}fallthrough;default:so that to apply the fix, you supplypci=bridgeiosize=8192to the kernel command line, or define theDEFAULT_BRIDGE_IO_SIZEto(8192), so that each non-root, non-hotplug, non-cardbus PCI bridge that can do an I/O window always gets one of at least 8k wide.

author: DiTBho
author_rank: Super Contributor
timestamp: February 16, 2025, 01:32:23 pm
content: Quote from: Nominal Animal on February 16, 2025, 11:04:52 amYup, it's start moooooooooovingI tried that weird hack, because other tries failed.Not yet tested with a physical cable, because I am remotely accessing the router.I can reset, power cycle, but I need to go physically there.I am already ready with the bridge support + a FON2 machine to test each rb564 port!Will be likely done on Tuesday

author: DiTBho
author_rank: Super Contributor
timestamp: February 16, 2025, 01:59:30 pm
content: Code:./mybuild-2024 6 5 tools apply each patchapplying patches_my/NA_pci_02.patch ... success~ drivers/pci/pci.c~ drivers/pci/pci.h~ drivers/pci/setup-bus.cCode:PCI host bridge to bus 0000:00pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]pci_bus 0000:00: root bus resource [io 0x18800000-0x188fffff]pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]pci 0000:00:00.0: [111d:0000] type 00 class 0x000000pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)pci 0000:00:02.0: [1106:3106] type 00 class 0x020000pci 0000:00:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:02.0: supports D1 D2pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:03.0: [1106:3106] type 00 class 0x020000pci 0000:00:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:03.0: supports D1 D2pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]pci 0000:00:06.0: [3388:0031] type 01 class 0x060400pci 0000:00:06.0: supports D1 D2pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hotpci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguringpci_bus 0000:01: extended config space not accessiblepci 0000:01:02.0: [1106:3106] type 00 class 0x020000pci 0000:01:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:02.0: supports D1 D2pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:03.0: [1106:3106] type 00 class 0x020000pci 0000:01:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:03.0: supports D1 D2pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:04.0: [1106:3106] type 00 class 0x020000pci 0000:01:04.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:04.0: supports D1 D2pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:05.0: [1106:3106] type 00 class 0x020000pci 0000:01:05.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:05.0: supports D1 D2pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:06.0: [1106:3106] type 00 class 0x020000pci 0000:01:06.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:06.0: supports D1 D2pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:07.0: [1106:3106] type 00 class 0x020000pci 0000:01:07.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:07.0: supports D1 D2pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3coldpci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01pci 0000:00:06.0: (1) for bridge window [io 0x0000], size 1536, size1 0, min_size 8192, add_size 8192, children_add_size 0pci 0000:00:06.0: (2) for bridge window [io 0x0000], size 1536, size1 8192, min_size 8192, add_size 8192, children_add_size 0pci 0000:00:06.0: bridge window at [io 0x0000]pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]pci 0000:00:06.0: BAR 7: assigned [io 0x18800000-0x18801fff]pci 0000:00:02.0: BAR 0: assigned [io 0x18802000-0x188020ff]pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]pci 0000:00:03.0: BAR 0: assigned [io 0x18802400-0x188024ff]pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]pci 0000:01:02.0: BAR 0: assigned [io 0x18800000-0x188000ff]pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]pci 0000:01:03.0: BAR 0: assigned [io 0x18800400-0x188004ff]pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]pci 0000:01:04.0: BAR 0: assigned [io 0x18800800-0x188008ff]pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]pci 0000:01:05.0: BAR 0: assigned [io 0x18800c00-0x18800cff]pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]pci 0000:01:06.0: BAR 0: assigned [io 0x18801000-0x188010ff]pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]pci 0000:01:07.0: BAR 0: assigned [io 0x18801400-0x188014ff]pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]pci 0000:00:06.0: PCI bridge to [bus 01]pci 0000:00:06.0: bridge window [io 0x18800000-0x18801fff]pci 0000:00:06.0: bridge window [mem 0x50000000-0x500fffff]Code:/* suppa */ pci_info(bus->self, "(1) for bridge window %pR, size %llu, size1 %llu, min_size %llu, add_size %llu, children_add_size %llu\n",b_res,(unsigned long long)size,(unsigned long long)size1,(unsigned long long)min_size,(unsigned long long)add_size,(unsigned long long)children_add_size);size0 = calculate_iosize(size, min_size, size1, 0, 0,resource_size(b_res), min_align);size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :calculate_iosize(size, min_size, size1, add_size, children_add_size,resource_size(b_res), min_align);/* suppa */ pci_info(bus->self, "(2) for bridge window %pR, size %llu, size1 %llu, min_size %llu, add_size %llu, children_add_size %llu\n",b_res,(unsigned long long)size,(unsigned long long)size1,(unsigned long long)min_size,(unsigned long long)add_size,(unsigned long long)children_add_size);/* suppa */ pci_info(bus->self, "bridge window at %pR\n", b_res);(drivers/pci/setup-bus.c)Code:pci 0000:00:06.0: (1) for bridge window [io 0x0000], size 1536, size1 0, min_size 8192, add_size 8192, children_add_size 0pci 0000:00:06.0: (2) for bridge window [io 0x0000], size 1536, size1 8192, min_size 8192, add_size 8192, children_add_size 0pci 0000:00:06.0: bridge window at [io 0x0000]Code:via-rhine 0000:00:02.0: enabling device (0080 -> 0083)via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:00:03.0: enabling device (0080 -> 0083)via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000pci 0000:00:06.0: enabling device (0000 -> 0003)via-rhine 0000:01:02.0: enabling device (0080 -> 0083)via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:03.0: enabling device (0080 -> 0083)via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:04.0: enabling device (0080 -> 0083)via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:05.0: enabling device (0080 -> 0083)via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:06.0: enabling device (0080 -> 0083)via-rhine 0000:01:06.0 eth7: VIA Rhine III at (ptrval), 00:0c:42:03:58:ff, IRQ 141via-rhine 0000:01:06.0 eth7: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:07.0: enabling device (0080 -> 0083)via-rhine 0000:01:07.0 eth8: VIA Rhine III at (ptrval), 00:0c:42:03:59:00, IRQ 143via-rhine 0000:01:07.0 eth8: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000Code:#define DEFAULT_BRIDGE_IO_SIZE (8192) /* suppa *//* pci=bridgeiosize=nn can override this */(drivers/pci/pci.c)Code:rb532 / # ifconfig -aeth0 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1bBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)Interrupt:40eth1 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1cBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth2 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1dBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth3 Link encap:Ethernet HWaddr 00:0c:42:03:58:fbBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth4 Link encap:Ethernet HWaddr 00:0c:42:03:58:fcBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth5 Link encap:Ethernet HWaddr 00:0c:42:03:58:fdBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth6 Link encap:Ethernet HWaddr 00:0c:42:03:58:feBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth7 Link encap:Ethernet HWaddr 00:0c:42:03:58:ffBROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth8 Link encap:Ethernet HWaddr 00:0c:42:03:59:00BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)

author: DiTBho
author_rank: Super Contributor
timestamp: February 16, 2025, 02:34:46 pm
content: Code:[*] networking-bridgenetworking-devices[]={ eth0 eth1 eth2 eth3 eth4 eth5 eth6 eth7 eth8 }korina korina eth0: link up, Mbps, full-dux, lpa 0xFFFFFCode:rb532a ~ # ifconfigeth0 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1bUP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1RX packets:100 errors:0 dropped:0 overruns:0 frame:0TX packets:323 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:6966 (6.8 KiB) TX bytes:17094 (16.6 KiB)Interrupt:40eth1 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1cUP BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth2 Link encap:Ethernet HWaddr 00:0c:42:0e:9f:1dUP BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth3 Link encap:Ethernet HWaddr 00:0c:42:03:58:fbUP BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth4 Link encap:Ethernet HWaddr 00:0c:42:03:58:fcUP BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth5 Link encap:Ethernet HWaddr 00:0c:42:03:58:fdUP BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth6 Link encap:Ethernet HWaddr 00:0c:42:03:58:feUP BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth7 Link encap:Ethernet HWaddr 00:0c:42:03:58:ffUP BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)eth8 Link encap:Ethernet HWaddr 00:0c:42:03:59:00UP BROADCAST MULTICAST MTU:1500 Metric:1RX packets:0 errors:0 dropped:0 overruns:0 frame:0TX packets:0 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)lo Link encap:Local Loopbackinet addr:127.0.0.1 Mask:255.0.0.0UP LOOPBACK RUNNING MTU:65536 Metric:1RX packets:1039 errors:0 dropped:0 overruns:0 frame:0TX packets:1039 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:89196 (87.1 KiB) TX bytes:89196 (87.1 KiB)mybridge Link encap:Ethernet HWaddr 00:0c:42:03:58:fbinet addr:192.168.1.3 Bcast:192.168.1.255 Mask:255.255.255.0UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1RX packets:100 errors:0 dropped:0 overruns:0 frame:0TX packets:322 errors:0 dropped:0 overruns:0 carrier:0collisions:0 txqueuelen:1000RX bytes:5166 (5.0 KiB) TX bytes:17062 (16.6 KiB)bridge support, all ethernet { eth0 .. eth8 } connected to mybridgewe'll see if it works!

author: Nominal Animal
author_rank: Super Contributor
timestamp: February 16, 2025, 04:09:58 pm
content: Quote from: DiTBho on February 16, 2025, 01:59:30 pmBTW, the above is "normal" for 111d:0000 =PCI_VENDOR_ID_IDT:0000, as it predates evenPCI_DEVICE_ID_IDT77201(=0001); the above just says that second and third BAR on this PCI root behave in a nonstandard way. It can be silenced with a quirk, but I'm not sure it's worth the effort; there would be no functional changes.Quote from: DiTBho on February 16, 2025, 01:59:30 pmNice, the I/O window on the bridge (0000:00:06.00) now gets allocated the correct size, and everything is as expected.Quote from: DiTBho on February 16, 2025, 01:59:30 pm1536?Thatsize 1536means that the io aperture size is calculated as if all the devices under the bridge, i.e. 0000:01:02.0 through 0000:01:07.0, can be stuffed into a single window on the bridge: 6×0x100 = 0x600 = 1536. I do not believe this is true. I believe each device needs their own I/O window on the bridge, which is what the above (assumed working!) configuration shows. The correct way to account for the total bridge I/O window aperture size needed, I believe, would be to find out the maximum alignment first, then alignand padthe per-device window needed (but multiple I/O ranges for a single device I do believecanbe combined). The bridge I/O window size needed is the sum of those per-device window sizes.The simple reason is that I don't see how the Linux kernel could give half a window to one device, and half to another; yet it counts the needed space exactly like that: just summing the required I/O device window sizes together. Either I'm very stupid here (always possible), or this is a really, really old bug.Aaahhh... This could also explain the horriblehack with ISA/EISA I/O windows: If the total number of I/O addresses needed over the bridge isX, andCONFIG_ISAorCONFIG_EISAis defined, then the address count is fudged into (X&0x000000FF) + (X&0xFFFFFF00)<<2, i.e. "multiply the number of 256 address blocks by 4".Because Intel bridges (those supporting ISA aliasing) also support 1K I/O window sizes, and the ISA aliasing is typically for 256 addresses per device (as that is the maximum allowed for a non-bridge device), this ends up doing the above alignment in practice – but only when ISA or EISA is enabled!I think the root cause could be a silly "multiply by four" thinko in some early PCI documentation, where the need for reserving entire windows even though only part of each window ends up being used, was confused by Intel using 1k I/O windows instead of 4k ones, somehow leading to the magic multiply-by-four.I could be wrong, though. I'm notthatfamiliar with the Linux PCI subsystem, and you know me: me fail every now and then.I can generate an RFC patch to submit upstream (LKML) for discussion, but I don't have any x86/x86-64 hardware with non-root PCI bridges to test and verify it myself (that it does the right thing even on x86/x86-64 hardware with ISA devices under a non-root PCI bridge). Non-PCIe hardware would be best.. Hey, do you happen to know people with older x86 hardware, that might be willing to test a kernel patch, comparing the PCI logs between the patched and unpatched kernels? To get traction at LKML, one has to post under their own name after submitting a Developer Certificat of Origin, and I'm not sure I'm ready to give up my safety-blankie of a pseudonym yet.

author: DiTBho
author_rank: Super Contributor
timestamp: February 16, 2025, 05:36:50 pm
content: Quote from: Nominal Animal on February 16, 2025, 04:09:58 pmme neither, the PCI on Linux is something very "vague" for mesoon I will have to write a low-level driver for mymon/mipswhich will also be ported to a PowerPC 40xthat because it is the only non-x86 card with PCI and a PCI-CF interface that runs at 5VI will definitely write something to handle PCI directly.I will not follow the Linux kernel code, everything will be written from scratch.Quote from: Nominal Animal on February 16, 2025, 04:09:58 pmI don't know, I definitely have a feeling there are other problems with the Cryptoprocessor and quad-serials miniPCI devicesI would like to have on the rb532aThey can reveal other bugs and defects with the PCIWhat to do? Where to discuss?

author: Nominal Animal
author_rank: Super Contributor
timestamp: February 16, 2025, 06:30:40 pm
content: Oopsie! The windowing argument isn't generally true. On MIPS, it's caused byarch/mips/pci/pci-legacy.c:pcibios_align_resource()orarch/mips/pci/pci-generic.c:pcibios_align_resource().Essentially, onalpha,arm (32-bit),m68k, mipspci-genericandpci-legacy,powerpc,sh,i386andxtensaapply I/O address space adjustments not accounted for in the allocation, because some "external  I/O cards only decode the low 10 bits of the address". This is what applies the 1k window per device.First of all, this makes absolutely no sense whenCONFIG_ISA=n,CONFIG_EISA=n. If yourCONFIG_PCI_DRIVERS_LEGACY=y, could you check if modifyinglinux-6.0.2/arch/mips/pci/pci-legacy.c:pcibios_align_resource()intoCode:resource_size_tpcibios_align_resource(void *data, const struct resource *res,resource_size_t size, resource_size_t align){struct pci_dev *dev = data;struct pci_controller *hose = dev->sysdata;resource_size_t start = res->start;if (res->flags & IORESOURCE_IO) {/* Make sure we start at our min on all hoses */if (start < PCIBIOS_MIN_IO + hose->io_resource->start)start = PCIBIOS_MIN_IO + hose->io_resource->start;#if defined(CONFIG_ISA) || defined(CONFIG_EISA)/** Put everything into 0x00-0xff region modulo 0x400*/if (start & 0x300)start = (start + 0x3ff) & ~0x3ff;#endif} else if (res->flags & IORESOURCE_MEM) {/* Make sure we start at our min on all hoses */if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)start = PCIBIOS_MIN_MEM + hose->mem_resource->start;}return start;}or, ifCONFIG_PCI_DRIVERS_GENERIC=y,linux-6.0.2/arch/mips/pci/pci-generic.c:pcibios_align_resource()intoCode:resource_size_t pcibios_align_resource(void *data, const struct resource *res,resource_size_t size, resource_size_t align){struct pci_dev *dev = data;resource_size_t start = res->start;struct pci_host_bridge *host_bridge;#if defined(CONFIG_ISA) || defined(CONFIG_EISA)if (res->flags & IORESOURCE_IO && start & 0x300)start = (start + 0x3ff) & ~0x3ff;#endifstart = (start + align - 1) & ~(align - 1);host_bridge = pci_find_host_bridge(dev->bus);if (host_bridge->align_resource)return host_bridge->align_resource(dev, res,start, size, align);return start;}without any other changes I've suggested, fixes the issue? It should, assuming you haveCONFIG_ISA=n(or undefined) andCONFIG_EISA=n(or undefined).It should work, and cause the io windows to be packed consecutively within the 0x0000-0x05ff range for the 0000:01:02.0-0000:01:07.0 devices.

author: DiTBho
author_rank: Super Contributor
timestamp: February 16, 2025, 09:38:14 pm
content: Code:0 drivers/pci/setup-bus.c reverted to original~ arch/mips/pci/pci-legacy.c modifiedCode:# rb532a does not compile# with# PCI_DRIVERS_GENERIC# needs# PCI_DRIVERS_LEGACYconfig MIKROTIK_RB532bool "Mikrotik RB532 boards"select CEVT_R4Kselect CSRC_R4Kselect DMA_NONCOHERENTselect HAVE_PCIselect IRQ_MIPS_CPUselect SYS_HAS_CPU_MIPS32_R1select SYS_SUPPORTS_32BIT_KERNELselect SYS_SUPPORTS_LITTLE_ENDIANselect SWAP_IO_SPACEselect BOOT_RAWselect GPIOLIBselect MIPS_L1_CACHE_SHIFT_4helpSupport the Mikrotik(tm) RouterBoard 532 series,based on the IDT RC32434 SoC.(arch/mips/Kconfig, my notes)Code:PCI host bridge to bus 0000:00pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]pci_bus 0000:00: root bus resource [io 0x18800000-0x188fffff]pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]pci 0000:00:00.0: [111d:0000] type 00 class 0x000000pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)pci 0000:00:02.0: [1106:3106] type 00 class 0x020000pci 0000:00:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:02.0: supports D1 D2pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:03.0: [1106:3106] type 00 class 0x020000pci 0000:00:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:00:03.0: supports D1 D2pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]pci 0000:00:06.0: [3388:0031] type 01 class 0x060400pci 0000:00:06.0: supports D1 D2pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hotpci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguringpci_bus 0000:01: extended config space not accessiblepci 0000:01:02.0: [1106:3106] type 00 class 0x020000pci 0000:01:02.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:02.0: supports D1 D2pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:03.0: [1106:3106] type 00 class 0x020000pci 0000:01:03.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:03.0: supports D1 D2pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:04.0: [1106:3106] type 00 class 0x020000pci 0000:01:04.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:04.0: supports D1 D2pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:05.0: [1106:3106] type 00 class 0x020000pci 0000:01:05.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:05.0: supports D1 D2pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:06.0: [1106:3106] type 00 class 0x020000pci 0000:01:06.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:06.0: supports D1 D2pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3coldpci 0000:01:07.0: [1106:3106] type 00 class 0x020000pci 0000:01:07.0: reg 0x10: [io 0x0000-0x00ff]pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]pci 0000:01:07.0: supports D1 D2pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3coldpci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]pci 0000:00:06.0: BAR 7: assigned [io 0x18800000-0x18800fff]pci 0000:00:02.0: BAR 0: assigned [io 0x18801000-0x188010ff]pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]pci 0000:00:03.0: BAR 0: assigned [io 0x18801100-0x188011ff]pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]pci 0000:01:02.0: BAR 0: assigned [io 0x18800000-0x188000ff]pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]pci 0000:01:03.0: BAR 0: assigned [io 0x18800100-0x188001ff]pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]pci 0000:01:04.0: BAR 0: assigned [io 0x18800200-0x188002ff]pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]pci 0000:01:05.0: BAR 0: assigned [io 0x18800300-0x188003ff]pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]pci 0000:01:06.0: BAR 0: assigned [io 0x18800400-0x188004ff]pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]pci 0000:01:07.0: BAR 0: assigned [io 0x18800500-0x188005ff]pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]pci 0000:00:06.0: PCI bridge to [bus 01]pci 0000:00:06.0: bridge window [io 0x18800000-0x18800fff]pci 0000:00:06.0: bridge window [mem 0x50000000-0x500fffff]Code:via-rhine 0000:00:02.0: enabling device (0080 -> 0083)via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:00:03.0: enabling device (0080 -> 0083)via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000pci 0000:00:06.0: enabling device (0000 -> 0003)via-rhine 0000:01:02.0: enabling device (0080 -> 0083)via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:03.0: enabling device (0080 -> 0083)via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:04.0: enabling device (0080 -> 0083)via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:05.0: enabling device (0080 -> 0083)via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:06.0: enabling device (0080 -> 0083)via-rhine 0000:01:06.0 eth7: VIA Rhine III at (ptrval), 00:0c:42:03:58:ff, IRQ 141via-rhine 0000:01:06.0 eth7: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000via-rhine 0000:01:07.0: enabling device (0080 -> 0083)via-rhine 0000:01:07.0 eth8: VIA Rhine III at (ptrval), 00:0c:42:03:59:00, IRQ 143via-rhine 0000:01:07.0 eth8: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000Code:not CONFIG_ISAnot CONFIG_EISA(profile/config_check.list) -> my constructor checks if each entry in config_check.list is "set" or "not set" in the .config fileWhen an item is preceded by "not", it means the builder checks the item not be set

author: Nominal Animal
author_rank: Super Contributor
timestamp: February 16, 2025, 10:42:18 pm
content: Nice!The correct upstream fix is those two#if defined(CONFIG_ISA) || defined(CONFIG_EISA) ... #endifguards in the mips pci-generic/pci-legacy.Un-fucking believable: this idiotic bug –– nobody noticing the negative effects of an ISA workaround on an architecture with no ISA –– had stopped RB564 from basically ever fully working under Linux/OpenWRT. Well, there might be some version or patch where that "ISA workaround" is patched out or disabled on mips, but I haven't found one yet. I mean, the bug is there in 2.6.8 (arch/mips/pci/pci.c+drivers/pci/setup-bus.c) from 2004, through 2.6.20 (arch/mips/pci/pci.c+drivers/pci/setup-bus.c) through 2.6.39 (arch/mips/pci/pci.c+drivers/pci/setup-bus.c), through 6.13.2 (arch/mips/pci/pci-generic.c+arch/mips/pci/pci-legacy.c+drivers/pci/setup-bus.c), basically unchanged. Just an obvious preprocessor guard missing per file, all this time. This bug is over two decades old now.If you think it okay, I could create a properly formatted patch, and send it to you via email for your comparison/testing, and we could see aboutupstreaming the fix, at least for MIPS. As I listed above, other arches (including 32-bit ARM) suffers from the same bug, so some notifications are in order. In particular, your Tested-By: would be invaluable for traction... plus I'm pretty sure OpenWRT and others would be interested in this fix; they run exactly the kind of motley hardware that is susceptible to this bug.

author: DiTBho
author_rank: Super Contributor
timestamp: March 19, 2025, 05:18:51 pm
content: Umm, it looks like no one has responded to the patch yetIn the meantime, I bought a mini lot of 5 boards, one for each person in my friend group.As for mymon development, the pATA driver is stable enough to load stuff from the microdrive,so I'm working on PCI driver using the linux kernel source as referenceas I am not able to find any development SDK (other examples?) for the IDT SoC.

author: DiTBho
author_rank: Super Contributor
timestamp: March 19, 2025, 06:31:34 pm
content: Code:# help pci.*pci.scan............ brute force, checking every device on every PCI buspci.regsdump........ dump pci registersI implemented wildchars as library, it's used for both "hex-pattern-searching" and the help to list all the commands that belong to the same class.Code:# pci.scan0:0 magic=0x0000111d0:2 magic=0x310611060:3 magic=0x31061106Code:boolean_t pci_scan(p_pci_t p_pci){boolean_t ans;boolean_t is_ok0;boolean_t is_ok1;uint32_t dev_num;uint32_t fun_num;uint32_t reg_num;uint32_t magic;is_ok0 = p_pci->is_ok;if (is_ok0 isEqualTo True){fun_num = 0; /* dc, for now */reg_num = 0; /* dc, for now */for (bus_num = 0; bus_num < 256; bus_num++){for (dev_num = 0; dev_num < 32; dev_num++){magic = pci_config_read(p_pci, bus_num, dev_num, fun_num, reg_num);is_ok1 = (magic isNotEqualTo 0xffffffff);if (is_ok isEqualTo True){print_uint32(bus_num, "", ":");print_uint32(dev_num, "", " ");print_hex32(magic, "magic=0x", "\n");}}}}ans = is_ok0;return ans;}It took two days, because the Mikrotik firmware leaves therc32434 pciin a... emm "undefined state".So, the PCI registers have to be reconfigured before you can read the config space, otherwise mymon crashes.It starts moving

author: Nominal Animal
author_rank: Super Contributor
timestamp: March 20, 2025, 04:56:52 am
content: Quote from: DiTBho on March 19, 2025, 06:31:34 pmSimilar to, or a subset offnmatch(), also known as POSIXglobbing?I've only ever really needed?(any single character),*(anything, zero or more characters), and ranges (like[0-9A-Za-z]) where each range acts like a limited?, only "occupying" one character in the string. Implementation approaches are well known, andmuch, much simpler than e.g. regular expressions that really require a full state machine. (One often used approach is linear, but splitting the pattern at*'s and optimizing the sub-pattern search, essentially skipping any*parts. Very robust –– easy to avoid buffer overruns ––, and usually performance is more than acceptable, even if it is not the most performant approach.)Quote from: DiTBho on March 19, 2025, 06:31:34 pmEww. But not really surprising!

author: DiTBho
author_rank: Super Contributor
timestamp: March 20, 2025, 11:36:25 am
content: Quote from: Nominal Animal on March 20, 2025, 04:56:52 amUmm, I think it's similar toglobbing

author: DiTBho
author_rank: Super Contributor
timestamp: March 20, 2025, 12:27:36 pm
content: Quote from: Nominal Animal on March 20, 2025, 04:56:52 ambah, I got surprised, probably due to the specs I have for the things I do at work:"when you write a bootloader, never leave a bus in an undefined state before loading and booting the application"(my boss)I think she is right - "because" - she added - "it is typical to assume that the buses have already been initialized,there are kernels like WxWorks that do not bother to do any initialization at all."She made a gesture with her hand, -"It costs you little, but for those who come after you" -like the teachers at school who want to lecture you -"it could save them days or weeks of work."Ummm, and do you remember that bloody 40xPPC board I talked you about? u-boot had the same issue.And it took us several months before we understood why?!? the linux kernel had strange malfunctions with the sata HBA.The reason is that often in SoCs that integrate PCI, the various registers start in an undefined state,most likely because they are not reset by the physical reset signal.Some registers must be set by hand, you can't trust their default value, even if the manual doesn't explicitly say so.It's never a good idea to keep them as they are from a reset.Worse still, if the firmware doesn't do any initialization, believing that the kernel should do it,and the kernel then doesn't do it, because it believes that the firmware should do it ...In the end ... nobody does it and things don't work as they should.-In the case of the rb532, it is expected that at least the mac-address of the VIA-chip added by the rb564 expansion card should be listedI guess, to do this, it is necessary to go through the PCI, so the fw should initialize it, and then deactivate it before bootstrapping the applicationWhat I observe from the dump of the PCI registers is instead an indefinite mess ...... where the only right thing is a bit that activates the PCI, but all the other values ​​are wrong/undefined.Why they do it this way? It's anx-file...

author: Nominal Animal
author_rank: Super Contributor
timestamp: March 21, 2025, 05:55:42 am
content: Quote from: DiTBho on March 20, 2025, 12:27:36 pmIlikeher!Quote from: DiTBho on March 20, 2025, 12:27:36 pmWhen the same company does both hardware and bootloader and OS, and there is pressure to keep development costs down, such things inevitably happen. The hardware folks cut costs by shifting things like reset state to the software folks. Bootloader folks cut costs by limiting their responsibilities to the minimum that suffices for booting the device. The OS devs get stuck with the mess, so they minimize their own work by taking some older version of Linux and hacking that sufficiently to get stuff working.It's a messy situation that produces less than desirable results, but as long as it is saleable and the clients don't complain overmuch, Mikrotik doesn't care. I call it bad leadership and business management –– but then again, I'm never about the short-term bottom line, but always about the long term results. Most investors and shareholders and therefore company executives are satisfied with the short term profit. Thus, I did not find this at all surprising.

author: DiTBho
author_rank: Super Contributor
timestamp: March 25, 2025, 11:43:57 am
content: see, in the end, I ended up writing a full SDK for the rb532a.Yesterday one of the guys in my group of friends bought an rb564 (so now we have two), and in the same order I also received a "rb532 board" practically for free (+5 euros).It is the older version of the r532a.It has half the clock of the rb532a CPU and half the RAM, it also has no buzzer and has a slightly different routing for some GPIOs.Interesting and very useful for testingIt is far from where I am, but it connected to one of my friend's development miniPCs;so, over ssh, I can access the serial, do a hw reset and boot a custom elf image.Code:device="/dev/ttyS1"stty -F $device cs8 -parenb cstopb crtsctsscreen -R term $device 9600(on the remote computer)

author: DiTBho
author_rank: Super Contributor
timestamp: March 25, 2025, 01:42:36 pm
content: only one 5 hours (during WE) to add the WatchdogCode:# wdt regs0xb8030030: 0x00000007 status Watchdog timer status 0b1110xb8030034: 0x00000000 count Watchdog timer count 0b00xb8030038: 0x00000000 compare Watchdog timer compare 0b00xb803003c: 0x00000000 ctrl Watchdog timer control 0b0Code:# wdt.timeout=5# wdt.en=1# wdt.count5# wdt.count2#RouterBOOT booter 2.12RouterBoard 532aCPU frequency: 400 MHzMemory size: 64 MBI can add wdt.start to the shell module.So when it invokes a command of something exprimental that goes nut and doesn't return as it shouldthe wdt will isse a physical hw-reset to reset the board.Attached to the rb532a power-in line, I have a circuit that a hw reset to the routherboard.It uses a relay to temporaly (2sec) cut the 12V power. It uses the rs232 RTS signal as control.It works, wut with the wdt it is simply better and I will not lose the things saved in the dram.