Harvard Vs Von Neumann-we need some clarification here. - Page 1
Forum section: electronics / general

author: commie
author_rank: Frequent Contributor
timestamp: September 24, 2015, 06:41:43 pm
content: Hi Fella's,As far as I am aware, I believe, during 1950's, the US navy put out a request for a computing architecture to manage their ballistics calculations. Towards the end, there were two competing systems namely: Princeton(Von Neumann) and Harvard. Both had advantages and disadvantages. Well, the US navy went with the Princeton system because it offered the best flexibility at the lowest transistor count.When transistor count was critical(early to late 1970's), we saw the introduction of the MC6800,I8080,MC6809,I8085,Z80,I8051 and 6502 and there were a few others. All these early 8-bit CPU's were Princeton architectures.Then, during the late 1990's we see the first Harvard architectures arriving on the scene as in Microchip PICs and a little later AVR's, which went by the name of microcontrollers. Integrated on chip, was an 8-bit ram and 12-14-16bit rom for opcodes. Obviously, extending the opcode from 8 to 16 bits meant the device could get more of the job done, like 2 cycle multiply and post inc/dec memory pointers, although the 6809 had pre/post inc/dec on its pointers.Now, the point is,Harvard architectures are less flexible than Princeton, but then why would you want to expand a PIC or AVR?, memory capacity is stratified across price. Also, nowadays, Harvard, totally dominate the low end of the market and they are begining to creep towards into the top end. However, just supposing you wanted to develop a programmable device, like a PLC or plain 'interpreter BASIC' where would you put the user BASIC tokens?With a Von Neumann architecture like the Z80, you could load it with cpm and then load it with BASIC, save your program to tape and load it back at a later stage, you can't do this with Harvard.When I was at school, we were taught to make rom space as small as possible, whilst the ram space filled the rest of the entire memory space, just like a modern PC.So, Princeton contradicts Harvard architectures.

author: hamster_nz
author_rank: Super Contributor
timestamp: September 24, 2015, 06:59:33 pm
content: The old definition was along the lines of having a separate code and data address space.The BASIC tokens are data, so would live in the data space. The BASIC interpreter would be in the code space.Except for on smallest of micros it is all fuzzy now, You have large unified memory space, feeding multi-level caches, feeding down to a separate data cache and instruction cache, and the virtual memory system has was of tagging RAM as data or code. At the lowest layer the CPU looks line Harvard architecture, a few layers up it looks like Princeton architecture.Even on small Harvard architectures AVR you can usually address the code memory,although the compiler might hide the details.(FWIW, I did a port of TinyBasic to the AVr...http://hamsterworks.co.nz/mediawiki/index.php/Arduino_Basic- complete junk, but kept me amused for a night.)I suspect small systems switched to Harvard once the code store was on the same silicon as the CPU. A Harvard architecture CPU would need more external pins.

author: retrolefty
author_rank: Super Contributor
timestamp: September 24, 2015, 07:02:31 pm
content: QuoteI think the Intel 8048/8051 types from the early/mid 80s, preceded your rendition of Harvard type chip history.I think with most people programming microcontrollers in modern C / C++ compliers the major difference between one memory and separate program/data memories that it really doesn't matter much anymore. Other things direct the architecture decision.

author: commie
author_rank: Frequent Contributor
timestamp: September 24, 2015, 07:12:29 pm
content: Quote from: retrolefty on September 24, 2015, 07:02:31 pmDo you perhaps think the 8048/51 were/are Harvard?, because they are not, they are pure Von Neuman, with a single AND gate unifies opcodes/data into a single 64k byte space. It's opcodes and data pass through the same 8 bit data bus making it Von Neumann.

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: September 24, 2015, 07:56:02 pm
content: QuoteHmm, I think "citation needed" there.QuoteI think that is just wrong, most DSPs were Harvard well before that. TMS320 for example which has sold billions dates from 1983.I think your whole timeline and assertions here are a bit suspect. However, the distinction between Harvard and von Neumann has been pretty meaningless for quite a while, it's not worth worrying about it.

author: retrolefty
author_rank: Super Contributor
timestamp: September 24, 2015, 08:39:05 pm
content: Quote from: commie on September 24, 2015, 07:12:29 pmWell we can agree to disagree. From wikipedia:QuoteQuote

author: free_electron
author_rank: Super Contributor
timestamp: September 24, 2015, 09:09:47 pm
content: Quote from: commie on September 24, 2015, 06:41:43 pmWHOA WHOA WHOA ! SACRILIGE , we will revoke your electronics license. you will never be allowed to approach any electronic component close than 6 feet for the rest of your life !8051 is a purebred harvard machine. Not van VonNeumann crap. The internal databusses ARE split. The external databus is muxed to preserve pins on the package. That is why external code cycles take longer than internal code cycles. intel has NEVER made von neuman junk: flat memory space , everything crammed in , data can alter code spaces , io lives inside datas space ... yuck ..Harvard has everything neatly partitioned.And microchip PIC ... in 1990 ? PIC has been around since 1975 !!! it was General instruments that invented the Programmable Intelligent Computer (PIC) 1650.GI spun off their semiconductor group and that became Arizona Microchip.the PIC1650 dates back to 1975 !!! So expect Arizona Microchip to show up on your door too with pitchforks , tar and feather ...

author: nctnico
author_rank: Super Contributor
timestamp: September 24, 2015, 09:30:30 pm
content: Quote from: free_electron on September 24, 2015, 09:09:47 pmSeperate memory areas are total crap because you'll always need extra code (=slow) to determine where a pointer is actually pointing to. Not to mention extra complexity for special instructions which can read/write all those different memory areas (more silicon area).There is a good reason modern architectures have a singular flat memory space! BTW Intel is king of Von Neuman. Look at the 80x86 processors!

author: hamster_nz
author_rank: Super Contributor
timestamp: September 24, 2015, 09:33:07 pm
content: Quote from: nctnico on September 24, 2015, 09:30:30 pmPROGMEM FTW! (and for the RAM saving!)

author: Howardlong
author_rank: Super Contributor
timestamp: September 24, 2015, 09:57:25 pm
content: I may be mistaken, but bandwidth seems to be missing from the conversation: separate instruction and data busses increases bandwidth.As another poster mentioned, this whole concept can be blurred. Even some lower end ARM devices, for example with apparently linear address space, have a complex multiple bus arbitration arrangement internally, allowing multiple seemingly concurrent accesses (when they're not stalled, and that's a symptom of the linear address space without forced segregation).Seems weird now, they were talking about von Neumann vs Harvard when I was at university over 30 years ago, but in those days only von Neumann was commonly used.And I thank poster for referencing the 1650. The CP1600, from which the 1650 was spawned, was the basis of the second microcomputer I built. The first was based on the LP8000. All three devices were from General Instrument, who disappeared through a series of M&As years ago, one of which spawned Microchip, and for better or for worse, nearly 40 years later, there's at least some provenance still there in what I do day to day... although largely by fluke rather than design.

author: commie
author_rank: Frequent Contributor
timestamp: September 24, 2015, 10:06:29 pm
content: Quote from: free_electron on September 24, 2015, 09:09:47 pmEver heard of a 8051 ram bootloader?, if you/rd AND /psenand feed its output of this gate to external /rd pin of the external ram memory chip and /wr to /wr on the external ram chip then the 8051 has a single 64k memory platform and you can use either rom or ram.It no longer has separate program/data memories just a single flat 64k space.In otherwords, the 8051 is behaving like Von Neumann with a single data bus.The internal data bus is not shown to be split in manufactures block diagrams.

author: commie
author_rank: Frequent Contributor
timestamp: September 24, 2015, 10:16:08 pm
content: Quote from: Howardlong on September 24, 2015, 09:57:25 pmThat is correct, if you read my first post, i did say Harvard's 'get more done' per clock cycle, widening the program bus increases speed simply because 16bits carries with it more information than say 8-bits.There are a few ways of increasing bandwidth without the increasing the obvious clock frequency, widen the bus width of both data and opcode, minimal registers-speed up subroutine usage.

author: free_electron
author_rank: Super Contributor
timestamp: September 24, 2015, 10:18:26 pm
content: Quote from: nctnico on September 24, 2015, 09:30:30 pm80x86 systems are HARVARD machines ! An 80x86 has dedicated IORD and IOWR control lines. So they partition their memory domains, something a Von Neumann does not do.Simply having a flat memory model does not qualify a machine as harvard or van neumann.With a 80x86 you have to be careful. Even though the processor has to transport data over the same physical data pins to save pincount , the actual busses are split since they use dedicated access control lines (RD WR IORD IOWR ). The 80x86 has internal bus multiplexers. So at a certain point in the silicon the busses split out in their own pathways."Real" Harvard chips will bring the busses out over their own dedicated set of pins. ( like most DPS's do ). But time multiplexing the busses does not take away from the core being Harvard.

author: free_electron
author_rank: Super Contributor
timestamp: September 24, 2015, 10:25:57 pm
content: Quote from: commie on September 24, 2015, 10:06:29 pmThen you are transforming the machine into a Von Neumann "like" machine and wasting 64k of adressable memory. In any case the Processor core remains Harvard.Besides you are confusing 8031 with 8051. 8031 is romless 8051 ALWAYS has rom on board (which can be disabled by pulling the PSEN pin)The instruction set has dedicated XMOV ( for external memory )You can NOT execute anything that is stored in DATA space.An 8051 has 3 memory domains : 64K Code , 64K Data and 265 bytes IO/SFR domain. each has its own dedicated instructions. you can move from CODE to DATA but there is no instruction to move form data to code space.Code executing from ROM runs on its own dedicated bus so the prefetch can happen independent from internal ram access. Moreover, on a 8051 the address data bus is mulitplexed as well , the upper address bits are muxed with the data path AND with the IO register banks in case you need no external code space.Some 8051 use banked memory and there is even a 16 bit variant of the 8051 called a 80251. I;ve been using 8051 since 1985 .. i know my way around that puppy...

author: Howardlong
author_rank: Super Contributor
timestamp: September 24, 2015, 10:43:31 pm
content: As an aside, maybe it's just me age, but every time Harvard/von Neumann comes up I have to look up which one is which. I know the difference, just not which one is single bus and which is dual.

author: commie
author_rank: Frequent Contributor
timestamp: September 24, 2015, 10:49:50 pm
content: Quote from: free_electron on September 24, 2015, 10:18:26 pmThose IORD and IOWR are not rom/ram signals they are for I/O space for use with port chips like the 8255, peripheral interface adapters, etc they are not separating ram/rom spaces like you think they are.Can you explain how MSDOS and WINDOWS loaded into 8086 program space and ran, how can these programs load into rom?, given the 8086 was Harvard? Can't load into ram because Harvards can't execute from ram space.

author: hamster_nz
author_rank: Super Contributor
timestamp: September 24, 2015, 11:00:30 pm
content: Their has been so much cross-pollination between the two design models (Harvard vs Princeton) and technology has advanced so far (e.g. pin and transistor counts) that these are academic ideals are no longer seen in the wild...About the best you can say is that if at a particular level of abstraction you have separate data and code memory spaces, then at that level of abstraction it is more like one than the other.Maybe we should also have a CISC vs RISC debate too?ARM (Acorn RISC Machine) hardly counts as RISC any more - how many different instruction sets does it have now?

author: Howardlong
author_rank: Super Contributor
timestamp: September 24, 2015, 11:13:15 pm
content: Quote from: commie on September 24, 2015, 10:49:50 pmI agree, while there are segregated I/O and memory address spaces, there is no segregation of RAM and ROM in x86. Speaking as someone who wrote graphics drivers for Windows 2.x and 3.x, back in the days when we actually cared about and measured cycle count in our heads before we ran code, and had no hardware acceleration ;-)

author: rfeecs
author_rank: Frequent Contributor
timestamp: September 24, 2015, 11:17:38 pm
content: Quote from: commie on September 24, 2015, 10:49:50 pmMost people would consider the 8086 a Von Neumann machine. It has one address bus for both program and memory.The exception is that the 8086 can pre-fetch instructions. So it actually executes instructions from a separate bus from the pre-fetch queue. It can therefore execute instructions and fetch data at the same time, which a pure Von Neumann machine cannot do. So it might be called a modified Harvard architecture.

author: Howardlong
author_rank: Super Contributor
timestamp: September 24, 2015, 11:23:50 pm
content: Quote from: hamster_nz on September 24, 2015, 11:00:30 pmWhile I agree with the sentiment, the core difference in my mind is whether the architecture is register centric or memory centric. In ARM you are pushed towards doing everything in the zero latency CPU registers: there are only load and store operations allowed on memory. In CISC, you're allowed to do more than just simple load and stores on memory.The point from ARM was that in strongly pushing the compiler to be register centric, where bandwidth is at its maximum, you save time on aggregate.But yes, with multilayer cache, almost all instructions single cycle, and various multithreading technologies, the bandwidth thing becomes less and less the problem, just as long as you can throw transistors and energy at the problem... Which is why ARM is still the darling of the mobile device.

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: September 25, 2015, 12:17:42 am
content: Quote from: commieBut the address busissplit.https://en.wikipedia.org/wiki/Intel_MCS-51QuoteMOV @Ri, #datais a 2 byte instruction that takes 12 clocks (1 machine cycle) to copy a byte from ROM to RAM. It can do this because R0 addresses the RAM through a separate bus.MOVX @Ri, Ais a single byte instruction, but takes 24 clocks because external memory uses the ROM address bus - so it must wait until the next instruction byte has been read before it can gain access to the ROM address bus.

author: free_electron
author_rank: Super Contributor
timestamp: September 25, 2015, 01:13:17 am
content: Quote from: rfeecs on September 24, 2015, 11:17:38 pmand that is how intel refers to it as well. Actually the original processors were micro-coded. THat micro code sits in a dedicated rom with its own address and data bus , not accessible to data.As for an 8086 beeing able to boot : that is a simple matter of how the memory management is set up. you can do the same with an 8051. you can store a bootloader in rom, copy it into ram at startup , swap the banks around , reset the cpu and restart from ram. There is all kinds of trickery you can do.None of that trickery defines the processor being one or the other.A harvard machine uses different pathways for code and data in the core. a von neumann does not. This saves pathways and 'real estate'. drawback : when fetching data the bus is in use. in a Harvard processor the processor can alreay prefetch the next instruction ( provided the busses are split on the package as well.on an 8051 (optimised single or two cycle architecture running from internal rom) , where there is internal memory the core actually can do that. They pre-fetch the next instruction while data transport is happening to/from external ram.So on the first clokctick after the last XRAM operation the instruction is ready to go. the bus cycle there has already completed.If you retain the harvard setup throughout the architecture of the machine you end up with something that is much easier to debug.1) data can never overwrite executable code. so buffer overflows , wrong pointers etc cannot corrupt the code.2) Stack overflows cannot corrupt executable code3) when looking at a memory dump you never have to wonder what you are looking at. this makes tracing program execution a lot easier.4) when building a system you do not need to worry about memory layout and mapping. since data and code live in separate spaces you have both a data pointer and a code pointer. both start at zero. in von neumann one needs to be mapped after the other. if your code increases in size all the data needs to shift up (or down if code size shrinks )5) in the 'olden days' this partitioning was easy. code goes into rom , the rest into ram. This makes the compilers easiers, the chip layout easier (for rommable devices )6) when using memory backup ram or eeprom for nonvolatile storage you can overwrite the rom without having to worry about shifting stuff around.7) the above is the reason why, in von neumanns they grow stack space and data from topmem down , and code from bottom up so they don't have to worry about 'overlapping'. in harvard both map from 0 up.you can hotboot van neumanns without problems. Every ADSL modem (both sides of the wire) in the world does that , and i wrote the bootloader for that (the standard on how they load code) the principle is simple.At a very high memory address there is a bootloader code. The processors logic is setup that, when a cold start reset happens the CPTR is set to that address and the loader executes. The loader checks the flash area for a valid 'signature' (0x55aa) telling him there is a valid program image present.If the signature is there the bootloader initializes the sdram controller and starts copying the flash to sdram at absolute address 0. When done, a write-only register in the Reset system is set to indicate that we have successfully loaded the system image. Then a warm start is executed: The processor is reset again, but this time the CPTR is set to 0 (that write only bit indicates to preload the CPTR with 0 to run the code or preload with the 0xFFF00000 address to run the bootloader in rom. The rest system also alters the bus timing so the processor runs at low clockspeed from flash and high clockspeed form sdram ( the rom and flash have much slower bus timing than the ram)if there is no signature present the bootloader considers the system image missing , sets up a tftp-like connection over the datapipe and requests firmware from the host system. The datapipe can be switched to a simple serial port by pulling down an i/o pin. this is used to load the FLASH in circuit during the board test procedure. IF a valid code image has been receive , the checksums are correct then the signature is written.if a request comes from the system firmware to perform a firmware update then a routine is activated , in the firmware , to erase the signature field , and perform a warm start. Even at a warm start the signature is checked.coldstart : boot from FFFF0000 check signature . no signature : loader mode , signature : warm startwarm start : no signature -> enter bootloader , signature : set cptr to zero and go.This was on an ARM 7. the bootloader uses a simple ASCII transport mechanism you basically upload a intel HEX file with the system image. the loader has single character control commandsR = resetW = warm startO = offset ( sets the CPTR to this address )U = uploadand there were a few others. i don;t remeber the complete set. the loader was just short of 800 bytes and sits in hard rom inside the asic.

author: westfw
author_rank: Super Contributor
timestamp: September 25, 2015, 05:53:57 am
content: 8051 is a Harvard machine. Separate program and data address spaces; just because you cause them both to access the same external memory via the same external pins is irrelevant. (although, I'll admit that things like the PICs where the program and data space are different WIDTHS make the Harvard-ness very clear!) (likewise, nearly all 4-bit microcontrollers had harvard architcetures.)The Zilog Z8 (their initial "microcontroller" product) was also Harvard.Microcode machines are essentially Harvard.8086 is a von Neuman machine; Data and program share an address space. There is an ADDITIONAL "IO space", which I don't think has anything to do with the distinction. Lots of architectures had separate IO spaces, and "memory mapped IO" was quite the revolution when it started to be common.Do you argue that any CPU with separate instruction and data cache memories has a "Harvard architecture?" I suppose you could. True-RISC machines (MIPS of a certain vintage?) make you jump through a lot of hoops to keep the memories coherent.I suspect that Harvard architectures seemed quite natural for a chip with RAM and ROM on the same chip; a manufacturer would have to make a significant effort to put them on the same bus, since their construction was so different. Chips that accessed all their memory through external pins had different limitations...

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: September 25, 2015, 10:46:15 am
content: LOL, engineers love arguing about definitions, even when it Makes No Difference Whatsoever.Even when the difference is apparent at a programmer level, there is usually some simple workaround, like RETLW or PROGMEM. The "old" DSP I use has a way to access data on the code bus, and there is a section of RAM dedicated to code, so you can do "von Neumann" like things. The newer DSP simply maps FLASH and RAM into both code and data address space, so technically Harvard but can do anything von Neumann can.Nearly all the ARMs which are essentially von Neumann to the programmer have multiple busses which by a wave of the wand make them "modified Harvard". The programmer would never notice, nor even the hardware designer.And of course, there is no true RISC any more, but all CPUs incorporate RISC-like features.

author: commie
author_rank: Frequent Contributor
timestamp: September 25, 2015, 10:46:21 am
content: Quote from: westfw on September 25, 2015, 05:53:57 amOkay, I will be the first to admit I was wrong with the 8051, I've learned something new.It seems Harvard are best for small self contained inflexible microcontrollers whilst Von Neumann are good for large computers.

author: Howardlong
author_rank: Super Contributor
timestamp: September 25, 2015, 11:49:27 am
content: My opinion, for what it's worth, is that it's pushing it to consider a processor is Harvard just because it has a prefetch queue (all six bytes of it). The instructions still come from the the same bus that is shared with the data.At the end of the day it ends up being little more than a subjective academic exercise putting different processors into different buckets such as RISC/CISC or von Neumann/Harvard. In practice when implementing a solution on a given device, what notional arbitrary bucket they might or might not be in is irrelevant: a more detailed and granular understanding is of far more relevance.

author: commie
author_rank: Frequent Contributor
timestamp: September 25, 2015, 01:01:00 pm
content: TI83+,TI84+ and TI89,TI89Tprogrammablecalculators all use Von Neumann processors.I would be interested to know what was insideprogrammablePLC's

author: ale500
author_rank: Frequent Contributor
timestamp: September 27, 2015, 06:07:33 am
content: TI-(0, 82, 83 (all) 84 (all) 85 and 86 use a z80. TI-89 (all) use a 68000 like the TI-92 (all) and the Voyage 200.

author: commie
author_rank: Frequent Contributor
timestamp: September 27, 2015, 01:34:43 pm
content: Quote from: ale500 on September 27, 2015, 06:07:33 amThats correct, all Von Neuman processors, I wonder why?

author: ale500
author_rank: Frequent Contributor
timestamp: September 27, 2015, 02:01:55 pm
content: HP-35 till HP-41 use a Harvard arch.

author: commie
author_rank: Frequent Contributor
timestamp: September 27, 2015, 02:28:19 pm
content: Quote from: ale500 on September 27, 2015, 02:01:55 pmThe HP35/45 wasn't programmable but I'm not sure about HP-41?

author: madires
author_rank: Super Contributor
timestamp: September 27, 2015, 03:03:13 pm
content: Most CPUs today are modified Harvard architecture, i.e. separate data and instruction caches, but common RAM.

author: ale500
author_rank: Frequent Contributor
timestamp: September 28, 2015, 09:34:47 am
content: The 41 was programmable, the 67 and 97 too and a couple models more.