Top vs bottom boot flash  - Page 1
Forum section: electronics / general

author: Circlotron
author_rank: Super Contributor
timestamp: May 06, 2020, 07:27:27 am
content: I'm going to draw up a board that is a plug in replacement for a 1Mx8 EPROM and all it contains is a number of lookup tables, not executable code. Not familiar with flash memory. I see top and bottom boot version but all I want to do is put in straight data, as I said, lookup tables. Can I use either version of the flash device? They will be programmed externally in a programmer just like you would an EPROM.https://au.rs-online.com/web/cps/Not sure whether that link will work.Devices areMX29F800CBTI-70GMX29F800CTTI-70G

author: helius
author_rank: Super Contributor
timestamp: May 06, 2020, 07:45:22 am
content: An EPROM is a static memory device like an SRAM, all the address lines are decoded at the same time and nothing else affects them.Flash is more like DRAM by being divided into pages. The controller has to send a command to open a page (similar to RAS for a DRAM), and then it can read out of that page. So how do you use Flash to boot a device with a software programmed controller? The top-boot or bottom-boot Flash device automatically opens a certain page (either at the Top or Bottom of the memory) when it resets. Then the hardware can run out of that page while it installs code in the controller that knows how to send commands to the Flash to open other pages.If you don't rely on the Flash for cold-boot this way (i.e. you have code already burned into a MCU) you don't need to worry about top or bottom booting.

author: Circlotron
author_rank: Super Contributor
timestamp: May 06, 2020, 07:49:37 am
content: Quote from: helius on May 06, 2020, 07:45:22 amSo I can't simply apply an address to a parallel flash device and have the data appear on the data lines like happens with an EPROM??? This could be a deal breaker.

author: newbrain
author_rank: Super Contributor
timestamp: May 06, 2020, 09:12:18 am
content: Quote from: Circlotron on May 06, 2020, 07:49:37 amNo - there's no problem whatsoever in reading a parallel flash, as the ones you mentioned in your OP.The highlighted statement from helius is misleading at best - if not wrong.The data sheet for those parts makes it very clear.The difference for top and bottom boot is that some shorter sector is mapped to high and lower addresses (with some resulting hole) to facilitate storing a boot loader - and updating the rest of the FW - without wasting a bigger than necessary area.For word mode A18-A0 are used, for byte mode A18 to A-1.To program them, as for any other flash of this type, the algorithm specified by the manufacturer must be accurately followed.

author: Circlotron
author_rank: Super Contributor
timestamp: May 06, 2020, 12:28:19 pm
content: Quote from: newbrain on May 06, 2020, 09:12:18 amSorry, I still don't quite understand.I need a contiguous memory space of 1,048,576 bytes. Are you saying that with 20 address lines not every address can be accessed?

author: newbrain
author_rank: Super Contributor
timestamp: May 06, 2020, 01:03:04 pm
content: No difference for you - the whole 1MB is mapped sequentially - no holes in the map, I badly expressed myself!It's just when erasing-programming that one has to consider the sector sizes.

author: Circlotron
author_rank: Super Contributor
timestamp: May 06, 2020, 01:12:07 pm
content: Woohoo!Thanks newbrain!

author: TomS_
author_rank: Frequent Contributor
timestamp: May 07, 2020, 08:54:16 am
content: I would make sure that such a device is compatible with your programmer.Perhaps a special erase/programming sequence is required to work with the various sectors.If you want something a little more generic, check out the line of SST39SF010 parts for example, as these are just generic EEPROMs with no sectoring.Edit: sorry, those are 1mbit and I see you need 1mbyte.