Max clock for ADC on STM32F303 - Page 1
Forum section: electronics / general

author: eTobey
author_rank: Super Contributor
timestamp: May 05, 2023, 02:37:40 pm
content: Hi,i found out, that the watchdog is not running as expected, when the clock is somwhere about over 2MHz. Are there any information about the limitation?Cheers,Toby

author: wek
author_rank: Frequent Contributor
timestamp: May 05, 2023, 10:59:14 pm
content: As I've said over at ST's forum, the ADC run in Continuous mode won't stop at the watchdog event, and due to lengthy ISR you read out samples taken after the watchdog event.By decreasing the ADC clock you increase the time until ADC takes the next sample, so you give chance to the lengthy ISR to read the value which caused the watchdog event.JW

author: eTobey
author_rank: Super Contributor
timestamp: May 06, 2023, 11:35:56 am
content: As I've said over at ST's forum, i set it to preserve the data register. It is very dissapointing, that i cant find information about the adc wdt or any competence, that can explain this.

author: wek
author_rank: Frequent Contributor
timestamp: May 06, 2023, 03:50:49 pm
content: The setting you mention - ADCx_CFGR.OVRMOD - determines, whether upon overflow (i.e. when conversion ends but previous conversion's result was not read out from data register) the old data are discarded and newly converted data stored to ADC data register, or the new result is discarded and old is kept. This has nothing to do with the watchdog functionality. Even if you keep the new conversion result, given it takes several conversions' time from the watchdog event until you read out the ADC data register, the new conversions result have overwritten the old ones several times, and you are looking at the latest result. As you use a triangle wave to test, the voltage has already risen and has been sampled several times since it has crossed the watchdog threshold, and the data register reflects voltage one conversion time before the moment when you read the data register.As an experiment, toggle a GPIO pin at the moment when you read out the ADC data register, an observe it together with the input triangle waveform.As much as you would want or need it, there is no mechanism in the STM32 ADC which would preserve the ADC_DR value at the moment when the watchdog event is risen, nor a mechanism which would stop the conversions at that moment.JW

author: Siwastaja
author_rank: Super Contributor
timestamp: May 07, 2023, 01:48:01 pm
content: Geez, just:* Read the ADC->DR as very first thing in ISR to a temporary variable,* Make the interrupt higher priority than any other interrupt in the system,* If you want to keep the interrupt long and still keep reacting to more such events, divide the ISR in two parts: the short part, and the long part. Trigger the longer part by choosing any free IRQ number, setting the longer function as interrupt handler for that number, make it lower priority, and use NVIC->STIR to trigger the slower interrupt from the faster.* Link any other threads you have already made about this elsewhere, or tell us more about your problem so that we don't need to guess. There is nothing wrong with how ADC watchdog or OVRMOD are being documented IMHO; just read the relevant parts of manual carefully.

author: eTobey
author_rank: Super Contributor
timestamp: May 10, 2023, 07:40:16 am
content: I think i found the problem (probably, as there is a lot of code just for the ADC) in my case: The EOC interrupt cleared the EOC flag, which itself reset the preservation of the ADC dataregister. And i thought this would only happen when i would read the dataregister.I found this in the datasheet, which is not clearly stating this:"EOC flag is cleared by the software either by writing 1 to it or by reading ADCx_DR."At the relevant point in the datasheet there is no information about this:It is possible to configure if data is preserved or overwritten when an overrun event occursby programming the control bit OVRMOD:• OVRMOD=0: The overrun event preserves the data register from being overrun: theold data is maintained and the new conversion is discarded and lost. If OVR remains at1, any further conversions will occur but the result data will be also discarded.

author: Siwastaja
author_rank: Super Contributor
timestamp: May 10, 2023, 08:06:42 am
content: So are you having overruns or not? In your opening post you are talking about watchdog, which is a different thing? OVRMOD is usually irrelevant, just design your code so that overrun never happens. Rather configure overrun to cause interrupt and call some panic_report_error() thing in the handler.Usually there is no reason to clear EOC explicitly; just read out the data.Also consider using DMA as it will simplify things. You can still use the watchdog functionality - DMA takes care of reading the DR and putting the result in the correct place, just like during normal operation.

author: eTobey
author_rank: Super Contributor
timestamp: May 10, 2023, 08:57:06 am
content: Quote from: Siwastaja on May 10, 2023, 08:06:42 amNot in my case. But it will make the DR beeing overwritten in the HAL libs, even if it is set to be preserved!Yes, the DMA might be the best thing here. But setting the preservation to none, when using only the WDT would work too.