Target PDN impedance for analog circuits - Page 1
Forum section: electronics / projects

author: jmw
author_rank: Frequent Contributor
timestamp: March 28, 2024, 06:20:10 pm
content: I've skimmed parts of Larry Smith and Eric Bogatin's bookPrinciples of Power Integrity for PDN Designwhere they talk about how to derive an target impedance profile. It seems focused on digital applications (FPGA in particular) where they get into rail swing tolerance for PLLs, current with maximum number of gates switching, and so on.Is there an approach that works well for analog amplifier circuits, starting from some figures like the supply voltages, amplifier bandwidth & slew rate, output load, and noise figures, to get a good target PDN impedance profile?

author: tggzzz
author_rank: Super Contributor
timestamp: March 28, 2024, 07:08:58 pm
content: FPGAsareradio frequency analogue circuits, ones sufficiently sensitive+vicious that the package parasitics are specified in IBIS Spice models, and where the PCB tracks width/length/thickness are significant.Perhaps you are thinking of non-RF analogue circuits that don't interpret the input waveforms as digital signals?It might be wise to indicate whether you are interested in photon counting or electron counting (femtoamp) analogue circuits

author: jmw
author_rank: Frequent Contributor
timestamp: March 28, 2024, 07:15:38 pm
content: Yes, that's what I meant if I wasn't perfectly clear. The design procedure in that book is centered around those characteristics of FPGAs, but what's a good design approach for say, fast and wideband amplifiers?

author: uer166
author_rank: Super Contributor
timestamp: March 28, 2024, 08:14:11 pm
content: It shouldn't be any different than digital PDNs, other than frequency of interest and impedance spec required. E.g. if an amplifier has BW of 10MHz, then it should be sufficient to optimize PDN not much beyond that. On the other hand, if your amp has bad PSRR and you need a solid supply that doesn't move as the amp consumes current, then the impedance required might be lower than what an FPGA has to deal with.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 29, 2024, 12:20:23 am
content: Same rules apply -- what is the bandwidth in question? What is change, and rate of change, of Icc/Iee? What is tolerable change in Vcc/Vee?Supply pins of analog elements tend to be more reactive than digital, in that digital ICs have considerable on-board supply capacitance (whether by sheer number of transistors/junctions, or explicitly as capacitors piggybacked or on the interposer), with a consequence for example, that you can do tricks like the old "float an op-amp between two BJT bases to increase output voltage and current range", with obvious potential downsides such as unexpected CM/DM oscillation modes, or more generally speaking, poorly or un-documented supply port responses. Not that this probably matters at high frequencies, where you wouldn't expect such tricks to work anyway, or not very well, but the flip side of that is, we need to provide suitable supply port impedances, whether that's simply by way of being low enough, or by being unreactive (a higher impedance might be acceptable, as long as it's well damped?).Amps aren't usually documented in terms of supply port embedding impedances, unfortunately. At least, none that I've seen, but I haven't exactly looked at a lot of high speed types myself.Quote from: uer166 on March 28, 2024, 08:14:11 pmYeah, with the catch that, somewhere above 10MHz for such an amp, there might be rectification effects. It probably goes without saying,not to microwave your analog circuits via PDN-transmitted RF, but, just for completeness sake.Note that, if PSRR is bad, and the supply has long time constants, then you will read those time constants as secondary error in the output; this may be important for precision and fast-settling applications. It might well be preferable to use a modest impedance source, but ballasted to be very stable (resistive), to convert this into a flat gain error rather than numerous time constants.Which I suppose might be a point in favor of zener shunt regulation, Ri being quite small and zener/avalanche effect acting very quickly, and with proper choice of diode (i.e. ~6.2V or stacks thereof), thermal error can be minimized as well. Since any kind of active regulator necessarily has output time constants corresponding to loop response.But then, PSRR varies with frequency too (usually proportional to amp gain itself), so this probably doesn't mean much. It should be easy enough, at least, to choose an amp without quite such poor PSRR that such extremes become necessary.Tim

author: jmw
author_rank: Frequent Contributor
timestamp: March 29, 2024, 07:19:43 pm
content: Trying to work an example with some round numbers:VCC = 10 VVEE = -10 VLeakage current = 10 mALoad impedance = 100 Ω (doubly-terminated 50 Ω line)AC VCC tolerance = 5%DC VCC tolerance = 1%Plugging these numbers,Max transient I = (10 V)/(100 Ω) = 100 mATarget AC impedance = VCC*(AC tolerance) / (max transient I) = 5 ΩTarget DC impedance = VCC*(DC tolerance) / (max transient I + leakage I) = 0.9 ΩOverall, this seems pretty lax. Most any bulk capacitor + a .1 μF will stay under 5 Ω even at 1 GHz unless there is bad resonance between package inductance and on-die capacitance. Is this a reasonable result?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 30, 2024, 01:02:03 am
content: Idunno about that; 5Ω at 1GHz is 0.8nH. Even a small DFN with multiple parallel power pins, struggles to get that low from parallel bypass caps thru pads, pins and bondwires to the die. At some point we have to assume good enough will do, or that the IC has solved some of these issues itself (onboard bypass?).Case in point, these op-amps are kind of ludicrous, and it's a miracle they work at all.That's also something like a 0.5ns step, let alone if CW, so you're going pretty fucking fast there.Also depends if it's class A; obviously it can't be in this example (Io(pk) > Icc) but for smaller signals it could, and then Vcc and Vee act in parallel, which helps. That is, half the load current leaves the Vcc and Vee pins respectively. If there's on-chip bypass, then we have the same effect, and Icc/Iee imbalance accordingly has a bandwidth limit*. In an extreme case, we might have a choke supplying an MMIC, or PP transistor amp, etc., and Icc is explicitly steady over a cycle; it's no accident LC-coupled RF amps are a popular choice (or perhaps the only option) for power at such frequencies, heh.*Rather than rectified signal currents entering/leaving each supply pin, both share continuous current, and the current is allowed to reverse within the time constant of this package filter network. This doesn't actually break the op-amp-floating-between-transistors gimmick because a common-mode current will suffice there, and bias is stable over the long term, you can still get class AB operation, but this does change its immunity to supply ripple, because we can no longer assume the op-amp supply pins are constant-current. (And at these frequencies, even if we cascoded them, the cascoder's Ccb or Cdg might not offer much improvement!)Tim