Here is a trick to get rid of the RC rise bumb on a clock cycle why does this wo - Page 1
Forum section: electronics / general

author: Beamin
author_rank: Super Contributor
timestamp: November 01, 2019, 04:17:18 am
content: I'm watching a really interesting talk on some commodore guy and the things he had to do to make his boards work.I guess he was in the part where they were getting FCC compliance and other near end of production issues a few months before launch of one of the commodores.So his idea was to take 12 V and add five volts to the base to cut the top of the signal off. Why does this work, and it seems so simple why couldn't the other engineers figure this out?The graphic is pretty self explanatory but if you need more context I can link the video, but honestly he doesn't say much about it as the audience seems to be all EE's that would know this stuff.I think this ties into data transfer which is also why this post is brought to you by nordVPN,Sign up with the code BEAMIN!% and get 5% off your first five minutes of use and if it get hacked NORD has a "no worries for eight month guarantee: For eight months after they realize your data is hacked they won't tell you and you will have no reason to worry, or your worries are free of charge.Next time I think I should use squarespace for my security though. 5% OFF!!!!! :scared:Oh yeah and don't forget to like share subscribe patreon check out my twitter instagram, linked in my space and twitch streams along with my amazon affiliate links, if you are feeling cheap and are an asshole and just want to do a one time donation that's cool here's my bitcoin and paypal accounts. beamin@paypal BTC: dhd83kdb49dmsg50shwv58fjdmq73ndod0he72jnsgdnxk,e836fh59flewjxhd537df9f7f5s3sher7 And bitconnect: ged7je6wgd5dgr8nhrf5*see what I did there?

author: Beamin
author_rank: Super Contributor
timestamp: November 01, 2019, 04:28:15 am
content: 12v to base not 5. This must have a huge range of applications which makes me wonder why everyone didn't know this.Sorry to keep adding to this but on a related note I went to look up how to rearrange ohms law and got some crazy answers and now I'm more confused then when I started (totally forgot my math if I don't use it in a long time) :I'm trying to figure out all the math to make this work manually to brush up on my ohms lawSomeone posted this which doesn't make sense or does it?QuoteDoes this look like the person answering it has no idea what ohms law is and just applying their algebra skills to the incorrectequation where they meant to type "V=ir" and got confused and put E AND V then mistook a - sign for an quals and the math people answered it like it was an algebra test?I think that whole bit is wrong so my solution is down below.The equation only has three variables maybe that's why your confused it E (for voltage but sometimes V is used instead I will use V) So Ohms law is V=IR Voltage=Current (amps not mAmps) X Resistance in OhmsSo if I have known Volts and know resistance I am solving for R Which would be V/R=IR/R Where the R's cancel out leaving V/R=Icollector current: 5v/100ohm=I 50mAbase:12v/ 1200ohm =I 10maTo find the voltage coming out of the emitter of the Q6 I take 5V lower the voltage by 100 ohm/50ma (more ohms law? how do I find how much voltage it will drop after the resistor? I don't have my meter and power supply to try this manually right now so its math time!) Then take the <5v value and subtract 0.6v because its a silicon trans correct? Does the 12v source get added to the emitter output or is it just driving the transistor into saturation range (BJTs are voltage controlled devices)?I cant believe how much I have forgot in the last year or so.

author: oPossum
author_rank: Super Contributor
timestamp: November 01, 2019, 04:48:03 am
content: 5.45 volts to the base to compensate for base-emitter voltage drop. There are *many* ways to get a nice rail-to-rail clock using modern CMOS. That circuit may have been a useful hack in the 70s.

author: Beamin
author_rank: Super Contributor
timestamp: November 01, 2019, 05:08:20 am
content: Quote from: oPossum on November 01, 2019, 04:48:03 amSo instead of losing 0.6 he is gaining voltage? I didn't know you could do that. I'm trying to figure this circuit out with out building and measuring like I normally do, but do it just as a fun exercise in math. Does my above post make sense?Why two buffers and not just the one on top? Are those buffers getting current/voltage from a source not shown on the schematic that I need to account for?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 01, 2019, 07:11:34 am
content: Because the buffer pulls down hard.TTL has an asymmetrical output stage. Which is also why the input threshold is asymmetrical.You can do this say for gate drives, using slightly newer CMOS gates to start:The direct path gate has steady resistance to +V/GND, but relatively high resistance compared to a MOSFET gate capacitance. You'll end up with a waveform similar to what's pictured, except the top and bottom will transition slowly over the remaining 0.6-0V (low) and 4.4-5V (high); the trick is the rapid transition inbetween, which is where you need it, since you'd drive a 5V logic-level transistor with this circuit. (Or 12V if CD4000 logic is used, but there are less applications for that I think, versus just using a driver IC, or a few more transistors in a discrete solution. Also the remaining 0.6V doesn't matter at all out of a 12V drive, so why bother.)Which to come full circle: there should be no point in a classic computer circuit where a 4.0V threshold must be passed rapidly. TTL threshold stops at 2 or 3V, and CMOS at ~70% (or 3.5V). And if you were using CMOS back in those days, it was because you didn't need the speed. Finally, the circuit generates a faster rise time, which would seem to make it more likely to run afoul of FCC emissions, not less. But that's very situational, and what's quoted here doesn't say whether there were unusual circumstances that did dictate such measures (and, apparently they did, otherwise why bother?).Tim

author: vk6zgo
author_rank: Super Contributor
timestamp: November 01, 2019, 10:41:04 am
content: Quote from: Beamin on November 01, 2019, 04:17:18 amThis is an old trick used in sync pulse & data regeneration devices.The usual metnod was to amplify the distorted pulse, then clip the top off it, (or in some cases, both top & bottom).The resulting signal has a much improved rise time to the original, plus a nice flat top.The signal is then passed through an amplifier with a better rise time than required, to get it to the right amplitude.

author: Beamin
author_rank: Super Contributor
timestamp: November 01, 2019, 09:58:15 pm
content: Quote from: T3sl4co1l on November 01, 2019, 07:11:34 amAnother excellent post along with the one after this but as usual to fully understand it(and not pester the board with excessive questions) I need to do more reading. Can you point me in the direction I should "google it" to learn about this topic? Like would it be "buffer circuits" or "74H series parts"? That's where I always get lost; I don't know the terms to search for.

author: Beamin
author_rank: Super Contributor
timestamp: November 01, 2019, 11:14:30 pm
content: Here is the video pretty interesting he's like the Steve Wazniak of commodorehttps://youtu.be/-Zpv6u5vCJ4

author: NiHaoMike
author_rank: Super Contributor
timestamp: November 01, 2019, 11:25:07 pm
content: There's also the trick of connecting I2C pullups to a voltage higher than the logic supply voltage, with zener diodes to limit the voltage.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 01, 2019, 11:43:51 pm
content: Quote from: Beamin on November 01, 2019, 09:58:15 pmProbably just reading up on logic families in general would be a good path? Once you understand the equivalent circuits and their corresponding V,I characteristics, you can model things (in your head, or on paper), and see how waveforms like the OP arise, and whether they're important or not, and how to deal with them (say by selecting a bigger gate or faster family, or tweaking with special circuits like shown).Which to go one level lower, you'll also need to understand basic circuit analysis: resistors and capacitors, voltages and currents, frequency or time; node (or loop) analysis; etc. (I think you already have this knowledge, or most of it? So this shouldn't be a problem.)Tim

author: drussell
author_rank: Super Contributor
timestamp: November 02, 2019, 03:16:28 am
content: Quote from: Beamin on November 01, 2019, 04:17:18 amI think some may fundamentally misunderstand the relationship of these two matters.This kludge has to do with the design (on a very short timeline) of the C128. The clean pulses generated by the kludge were required for the Z80 that was being designed into the C128 so it could have the built-in ability to run CP/M, similar to the unreliable Z80 CP/M cartridge for the C64.The pulses in the original design by the chip guys and board guys that were being derived from the main 6502 (8502) clock generator and whatever VIC chip version they were building were still not sufficient to meet the Z80 clock requirements as intended, which is what was shown in your posted diagram. This had nothing directly to do with RF interference or passing FCC or anything emissions related. The design wasn't failing some test and then using this to pass or something.The issue, rather, was that they couldn't make any significant changes to the original design of the circuitry and PCB itself as due to the tight timescale, they had already started the FCC certification process long before a working prototype had been assembled and fully, thoroughly tested (especially advanced features like the on-board Z80 second processor.) They therefore could not change the major specifications of what they were trying to certify if they still wanted approval in time for their desired demo date. They couldn't go back at this point and start adding another clock generator and re-routing major sections of the board, or really have any major circuit changes, adding chips, etc., but they could still add things like decoupling caps or a transistor or two, etc. without messing up their certification timeline too severely.This circuit addition simply allowed them to clean up the clock signal to the Z80 without affecting the progress of their FCC certification process as significantly as other, more conventional approaches might have.

author: duak
author_rank: Super Contributor
timestamp: November 02, 2019, 07:05:29 pm
content: I remember this characteristic of the Z80. If memory serves, the minimum clock high time was important at higher speeds. A colleague had designed a board using a Z80 with a simple TTL oscillator and resistor pullup as per the app note but it wouldn't work at 4 MHz. I happened to have designed a couple of Z80 boards so I was able to help her out. I think a later app note showed another circuit for 4 MHz using a transistor for an active pullup.If you want to see interesting clock drive requirements look at the Intel 8080 & Motorola 6800. Both require biphase, non-overlapping clocks. Even more rustic are things like the 1103A 1K DRAM chip. I have a commercial board somewhere that has a bunch of discrete parts to generate the 12 Vp-p clocks for the array.

author: SeanB
author_rank: Super Contributor
timestamp: November 04, 2019, 06:16:54 pm
content: Z80 needed at logic 1 that was at least 300mV from 5V for the clock, and it was driving a pretty high capacitive load inside the chip, so had to have a good AC drive capacity. So if you wanted speed the driver had to pull up to 5V pretty fast, which most TTL could not do without external pull up, thus the clamped base drive to pull up fast to 5V.At least you did not have weird logic drives for clocks, like that on old CMOS memories, which needed a -9V clock drive, along with other odd things like needing a -20V substrate bias, along with a 12V rail along with the 5V IO voltages. Mostek MK4007 comes to mind, that was weird in the drive requirements, plus the very specific power rail sequencing to not blow it up either. That was a serial memory, 512 bits, with an overlapping clock required, but that at least would work with TTL drive with overlapping clock pulses