hybridfree/eevblog-posts huggingface dataset:
Trouble programming a lattice ice stick with diamond 3.10 programmer - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: May 28, 2019, 03:49:12 am
content: Hey!Just got an FPGA board from lattice.I am going through all the steps in the quick start quide to program a blinking led (Im using the icecube2017 user guide). I want to get familiar with this software to use fpga in my projects.I got through all the steps except programming the FPGA with diamond. the icestick just has a usb connector so I didnt use JTAG (i dont really know what that is tho)I have tried different USB ports, but they don't work.Here is the error message:INFO - Check configuration setup: Start.INFO - Check configuration setup: Successful (Ignored JTAG Connection Checking).INFO - Device1 iCE40HX1K: SPI-M25P10-A: SPI Flash Erase,Program,VerifyInitializing...IDCode Checking...ERROR - Function:CHECK_IDData Expected: h10 Actual: hFFERROR - Operation: unsuccessful.ERROR - Programming failed.A little research showed maybe my ftdi drivers need to be updated? What are these drivers? I am running windows 10.Any tips please?

author: Dmeads
author_rank: Regular Contributor
timestamp: May 31, 2019, 10:42:17 pm
content: Okay, I solved my own problem.I want to leave this here for anyone who will need it in the future.I was using the lattice IceCube2 quickstart guide to load an example sketch of a blinking LED to an Icestick (uses the Ice40HX1K fpga).This user guide was very out of date (from 2013 I think).Use this guide to make an LED blink instead:http://thebcfactor.net/electronics/programmable-logic/lattice-icestick/example-1/Most of the stuff is the same except for the flashing step.This should save you some major frustration haha.
Reasonably priced FPGA dev board that has RF i/o? - Page 1
Forum section: electronics / general

author: 0culus
author_rank: Super Contributor
timestamp: April 27, 2019, 11:30:32 pm
content: Does there exist a reasonably priced FPGA dev board with RF i/o other than the Altera/Intel Max 10 development kit? I already have one of those....it has 3 on board SMAs comprising 2 analog inputs and 1 DAC output. All of the RF FPGA dev kits I've found from the usual suspects cost a great deal more than I want to pay as a hobbyist.

author: TK
author_rank: Super Contributor
timestamp: April 27, 2019, 11:39:04 pm
content: Analog Devices Pluto has a ZINQ with additional components for RF input and output. Priced around $150

author: 0culus
author_rank: Super Contributor
timestamp: April 27, 2019, 11:43:50 pm
content: Oooo, that's almost exactly what I was looking for. Thank you!

author: lty1993
author_rank: Unknown
timestamp: May 10, 2019, 07:59:02 am
content: Ettus Research USRP B200 / B210 should be a good candidate too. Although the FPGA is kind of old (Spartan 6), and the cost is on the high side. AD936X FrontendLimemicro LimeSDR  should fit your requirement too. It has Altera FPGA and Limemicro LMS7002M RF Frontend.Both systems published enough documents so you can use them as FPGA + RF Frontend Dev Board easily.
Old Altera flex10K, looking for a board schematic - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: April 19, 2019, 09:59:21 am
content: So, I have an old Altera flex 10K, the chip is an oldEPF10K10L84(wow, it's removable, I like it!), mounted on a small board with just headers and the jtag port. I still have Altera QuartusII v5 installed in my old Windows XP laptop, and the software is able to see the chip via usb-blaster, and it also seems working.WOW, perfect, nice, excellent, awesomeWhat I'd like to do with this? Well, I'd like to replicate the fpga board in EagleCad in order to make an expansion board for my 68K board. This seems easier with Flex10K because chips are 5V tolerant.OK, bad news now: the board is all made in smd and it doesn't have any documentation, and there is no schematic, not even a piece of paper with something on it. Nothing at all!. It's a very simple circuit, FPGA, oscillator(1), decoupling stuff(2), headers, and jtag pins, plus a power block, but I'd like to see a working example.Anyone?edit:(1) 50Mhz. OMG!(2) this is what I find difficult to design by myself

author: ebastler
author_rank: Super Contributor
timestamp: April 19, 2019, 10:20:21 am
content: Would you have the type designation or a photo of the development board?Is it the one used here (figure 10)?https://iie.fing.edu.uy/investigacion/grupos/microele/iberchip/pdf/62.pdf

author: ebastler
author_rank: Super Contributor
timestamp: April 20, 2019, 02:55:27 pm
content: These guys show an “electrical scheme” for their eval board. Almost too simple to be true/complete?http://ldm-systems.com/doc/plis/DS-FLEX10KXXT144-1.2.pdf

author: legacy
author_rank: Super Contributor
timestamp: April 20, 2019, 02:56:19 pm
content: This board had a sort of built-in byteblaster, which uses the parallel port of the computer for programming the fpga. It's currently removed, and I am directly interfacing the jtag.I am not looking for the schematic of the board I specifically own, I am looking for a simple schematic for the minimal setup around Altera flex10K.

author: Scrts
author_rank: Frequent Contributor
timestamp: April 23, 2019, 12:50:36 pm
content: Seems like each pin is provided on the silkscreen. Why do you need the schematic?

author: NivagSwerdna
author_rank: Super Contributor
timestamp: April 23, 2019, 12:56:37 pm
content: I believe the Atera UP and UP2 CPLD dev boards had a Flex 10K... there will be schematics somewhere on the interweb...... but there won't be much to them.There was a book and a set of tutorials for the UP board somewhere.

author: legacy
author_rank: Super Contributor
timestamp: April 23, 2019, 01:29:04 pm
content: Quote from: Scrts on April 23, 2019, 12:50:36 pmto copy the decoupling stuff (on the the sideB of the PCB)Besides only a part of pins are reported on the silkscreen.

author: legacy
author_rank: Super Contributor
timestamp: April 23, 2019, 01:30:45 pm
content: the final purpose is creating a new board, to be integrated in a project where I need to deal with 5V devices.
Altera ROM M9k [Solved] - Page 1
Forum section: electronics / general

author: Wiljan
author_rank: Regular Contributor
timestamp: March 12, 2019, 04:29:05 pm
content: HiI have been using the Altera Rom M9k and M10k many times with and external Intel hex file and it have been working straight out of the box as 8 bitNow I deal with project with a M9k Rom 8 bit input and 9 bit outputMy question is how are the init memory map layout as 9 bit?When using 8 bit it just take a bin file eg in HxD and export it as Intel hex file and then use it in the M9k and it work straight for each 8 bit addressNow with the 9 bit I did find that it uses 8 bit from byte 0 and 1 bit (the 9. bit) from byte 1 so = 2 bytes for 9 bit... it makes some senseSo if my hex file looks likeCode:00 12 00 34 00 56 00 78 00 9A 00 BC 00 DE 00 0101 12 01 34 01 56 01 78 01 9A 01 BC 01 DE 01 01and I save it as Intel hex and use it in Quartus for the M9k and run fpga (I does send the data out by a simple counter going though the rom I getCode:0x0000x0120x0340x0560x0780x09A0x0BC0x0DE0x0010x0000x0000x0000x0000x0000x0000x0000x0000x1120x1340x1560x1780x19A0x1BC0x1DE0x101I do NOT expect all the 0x000'sSo basic my question is if the layout of the Intels hex are straight 2 bytes per 9 bit or is it packet in a different way?

author: Wiljan
author_rank: Regular Contributor
timestamp: March 13, 2019, 10:11:28 am
content: Some more investigation, if I make a memory file manually as 9 bit in quartus and save it as Intel Hex file it does work in the FPGA as expected, that great.Here is the Intelhex code for the 9bit dataCode::020000000011ED:020001000022DB:020002000033C9:020003000044B7:020004000055A5:02000500006693:02000600007781:0200070000886F:0200080000995D:0200090000AA4B:02000A0000BB39:02000B0000CC27:02000C0000DD15:02000D0000EE03:02000E0000FFF1:02000F000000EF:020010000111DC:020011000122CA:020012000133B8:020013000144A6:02001400015594:02001500016682:02001600017770:0200170001885E:0200180001994C:0200190001AA3A:02001A0001BB28:02001B0001CC16:02001C0001DD04:02001D0001EEF2:02001E0001FFE0:02001F000100DE:02002000015588:02002100015587:02002200015586:02002300015585:02002400015584:02002500015583:02002600015582:02002700015581:02002800015580:0200290001557F:02002A0001557E:02002B0001557D:02002C0001557C: 02 0000 00 0011 ED: 02 0010 00 0111 DCStart code Byte count Address Record type Data Checksum
EP4CE6E22C8N Development Board - Documentation Help - Page 1
Forum section: electronics / general

author: wibbes
author_rank: Newbie
timestamp: February 20, 2019, 10:32:39 am
content: Hi allIm new to the FPGA world so have brought a FGPA development board based on the EP4CE6E22C8N from Altera. only problem is i have had no documentation from the supplier, i was wondering if anyone else has one of these development board and had the pin out or anything. below is an image of the board.Thank youhttps://www.ebay.com/itm/Programmer-Kit-USB-Blaster-FPGA-EP4CE6E22C8N-Development-Board-Remote-Controller/382786492258?ssPageName=STRK%3AMEBIDX%3AIT&_trksid=p2057872.m2749.l2649

author: ebclr
author_rank: Super Contributor
timestamp: February 20, 2019, 12:37:44 pm
content: If you know how to use google translator this may helphttps://item.taobao.com/item.htm?spm=a230r.1.14.22.11c2397craK4Dl&id=35595282676&ns=1&abbucket=20#detailhttp://bbs.eeworld.com.cn/forum-209-1.html

author: ale500
author_rank: Frequent Contributor
timestamp: February 25, 2019, 06:12:27 pm
content: The FPGA in that board has very little decoupling... I think just one capacitor. on the 3.3 V rail. I never got VGA output working reliably,
FPGA Training Courses? Vivado and SystemVerilog? - Page 1
Forum section: electronics / general

author: Pack34
author_rank: Frequent Contributor
timestamp: February 20, 2019, 04:49:02 pm
content: I have the professional development funds set aside to do some self-paced or in-person training courses to get myself a bit more proficient on the FPGA side. The focuses would be SystemVerilog in Vivado.Are there any highly recommended places for this?
Heber Pluto 6 embedded gaming machine control board with Coldfire and FPGA - Page 1
Forum section: electronics / general

author: RayeR
author_rank: Contributor
timestamp: February 08, 2019, 12:08:19 pm
content: Hi,is there anybody familiar with Heber gaming machines?Last year I bought old Pluto 6 board on a fleamarket just for fun (vithout VGA extension cards). There was some interesting ICs on the board including Xilinx spartan FPGA that was attracted my attention.I found the manufacturer websitehttp://www.heber.co.uk/product/pluto-6/and downloaded SDK and demo applications. I don't have any peripherals for it but I hoped it will communicate via serial port to see if it is alive. I made power supply adapter to attach standard ATX PSU. I reflashed the boot FlashROM with demo bootloader (it containded some different custom bootloader) and put demo application binary on the FAT32 formatted CF card as was described (I didn't compiled just used the provided *.s19 binaries). I powered the board and some LEDs light up. The "DISK" LED flashed for about 1s. BUt I didn't get any communication on any of UARTs. I attached a scope probe directly to ColdFire UART0/1 TX pins but nothing is comming out there. Neither from dedicated UART IC. I can see there are running some acivity on data and address bus during boot but then the activity seems to not be much intensive, just running some refresh of DRAM or so.When I pull out the CF card the "DISK" LED blinks for a very short time (<0,1s) so this imply that at least the bootloader code must be working. The same if I delete the .s19 file form CF. Then I tried to use SDK to compile my own application where I stripped down the demo code and left only the UART init and put an inf. loop printing something there, I compiled it and put on CF but still nothing from UARTs.It seems to me that the application falls into some exception trap just before it enters main code - maybe some driver linked to application didn't init properly. I don't have the HW debugger tool for this board. Any idea?
VHDL SPI core - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: February 04, 2019, 06:42:36 am
content: Hi,It seems an obvious code,butI'm trying to interface the ADS131E08 to my Spartan6 FPGA, the problem is that when I implement my SPI bus, I can access some registers but when I try to verify the written registers some would fail, I want to know if you happen to know a good known source for a Master SPI code in VHDL that would support different modes of CPOL and CPHA modes.I have tried the FPGA4fun core and my own implementation, but both of them are not working in here.

author: DC1MC
author_rank: Super Contributor
timestamp: February 04, 2019, 06:49:03 am
content: You can try this one:https://opencores.org/projects/spi_master_slaveCheers,DC1MC

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: February 04, 2019, 07:00:38 am
content: QuoteThanks,I have already tried this one too, the problem is that the core would send and receive in both falling edge clocks, But I wanted to send in falling edge and receive in rising edge clock, also in the core it mentioned that it had a bug for CPHA =1

author: NorthGuy
author_rank: Super Contributor
timestamp: February 04, 2019, 03:17:51 pm
content: What is easier?(1) write 20 lines of VHDL codeor(2) figure out how somebody else's core works?SPI is just a sift register. You simply create a counter. Say if your clock is 100 MHz and you want 1.75 MHz SPI, you count from 0 to 56. When it is at 0 that's your rising edge, you set CLK high and shift out MOSI. When it is at 28, that's your falling edge - you set CLK low and shift in MISO. When it's 56, you reset the counter to 0. That's all there is to it.If the line is long, you can delay shifting MISO from 28 to a later count, or even move it to the rising edge.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 04, 2019, 04:11:39 pm
content: I second that. SPI is pretty easy, write that yourself. With a couple 'generic' statements, you'll make a decently generic SPI module for all modes in a couple of hours.The only thing to worry about for a completely generic SPI module though would be the clock domains, but that would matter only if you want to implement slave SPI, which is not what you're talking about here. Master SPI is very simple.
Lattice XO2 VCCJ voltage and external clock amplitude - Page 1
Forum section: electronics / general

author: Axk
author_rank: Regular Contributor
timestamp: December 01, 2018, 08:25:57 pm
content: Designing a simple breakout board for Lattice XO2-1200 (LCMXO2-1200ZE-1TG100CR1) (this particular chip because ebay has it).Planning to program it with a chinese JTAG cable which is apparently very similar to Lattice's HW-USBN-2B (https://www.ebay.com/itm/Lattice-FPGA-CPLD-USB-Downloader-Jtag-ISP-Programmer-ispDownload-Cable-HW-USBN-2/392173727886)Reading the Programming Cables PDF (FPGA-UG-02042-26.0) and it's clear but I'm not completely sure what VCCJ would be on the chip.Is it VCCIO of the IO bank that has all the JTAG pins?Another thing that I'm not sure about is what amplitude should the single ended primary external clock applied to a ACLKT pin be. Should it be VCCIO or the core VCC?Any other gotchas you know of with trying to program an XO2 with such cables? (I've seen the pull-up resistor recommendations, so I'm adding those)

author: Bassman59
author_rank: Super Contributor
timestamp: December 03, 2018, 05:07:01 am
content: Quote from: Axk on December 01, 2018, 08:25:57 pmYes.QuoteAlways the VCCiO of the pin's bank.
Lattice XP2 programming tool - Page 1
Forum section: electronics / general

author: jipihorn
author_rank: Contributor
timestamp: December 01, 2018, 04:18:52 pm
content: Hello,I'm desperatly trying to program a XP2 FPGA thgrough the Brevia eval board (using the usb cable), but I'm totally stuck with the programming tool.Everything is detected except that when programming is started, everything hangs and does nothing except displaying a "Programming XCF" window (see the attachment).I don't know what to do. It is exactly the same from Diamond or the separate tool.Is anyone had this kind of situation ?Thanks in adavance,Jerome.
FS: Nutaq ZeptoSDR = Xilinx ZedBoard (zynq 7020) + SDR module (300M - 3.8G) - Page 1
Forum section: electronics / general

author: tnt
author_rank: Regular Contributor
timestamp: December 01, 2018, 02:58:30 pm
content: Hi,It's a classic Zed Board from Xilinx (and can be used as such if you want) in nice meta enclosure and a FMC addon with SDR functions. It includes filter banks for interference rejections which most SDR do not.It has GNURadio drivers (or at least did at one point, I haven't checked if they're maintained, but a couple years ago I was able to use it just fine).See this for the details :https://www.nutaq.com/productszeptosdrradio420s-details/https://www.nutaq.com/blog/zeptosdr-architecture-and-apiAnd link to the ebay sale page :https://www.befr.ebay.be/itm/183563028449Cheers,Sylvain
Connect FPGA pins directly to LED matrix - Page 1
Forum section: electronics / general

author: ni9e
author_rank: Newbie
timestamp: December 01, 2018, 03:29:13 am
content: Hi,I want to control an 8x8 LED dot matrix using an FPGA. I know that there are chips like the MAX7219 that can do it for me, but I want to implement it myself as an exercise.Can I connect the pins from the FPGA directly to the LEDs?I am using the Cmod A7 board where the outputs are 3.3V. Here are the I/O characteristics taken from the datasheet:These are the LED characteristics taken from the FND-5882W4SM00BW35 dot matrix datasheet:

author: Ian.M
author_rank: Super Contributor
timestamp: December 01, 2018, 06:23:46 am
content: Nope. You need a LED matrix with a lower Vf to provide enough headroom for current limiting resistors. That will probably be a red, green or yellow one. If you try with your white matrix, the odds are it will be unusably dim, (compounded by the 1/8 duty cycle) but if any of its LEDs have an untypically low Vf, there's the possibility it may draw excessive current from the FPGA I/Os, which may damage them.

author: ni9e
author_rank: Newbie
timestamp: December 01, 2018, 06:35:18 am
content: OK, thanks.Then I will use a buffer or linedriver like this one:http://www.ti.com/lit/ds/symlink/sn74lvc245a.pdf

author: Ian.M
author_rank: Super Contributor
timestamp: December 01, 2018, 10:04:19 am
content: Nope. Still not suitable, as the problem is 3.3V logic doesn't have enough drive voltage for a LED with a Vf of up to to 3.5V.Use 4x 74LVC2T45 chips run from 3.3V VccA and 5V VccB as level translators and high current buffers into 8 series resistors to set the current between them and the display columns as your display is column anode.To multiplex the rows use discrete MOSFETs with a max Vgs threshold of less than 1.6V. When on, each has to handle the current for all lit LEDs in the row, and steady state that would be up to 0.2A, or pulsed it could be as much as 0.4A (the limit of what 4x 74LVC2T45 can output), so with only 3.3V on the gate, you are probably looking at 1A MOSFETs so they are on hard enough to handle the current without excessive Vds drop.
Cheapest zynq system-on-module? - Page 1
Forum section: electronics / general

author: xaxaxa
author_rank: Regular Contributor
timestamp: November 24, 2018, 03:01:00 am
content: The zynq XC7Z010 FPGA SoC IC can be had for less than $20, but routing a board with SDRAM is a major effort; there have been some system-on-module boards but they all either lack SDRAM or are really expensive. I'm looking for something on the order of $50 with at least 256MByte SDRAM that I can easily integrate into a system; does such a product exist or am I looking at designing my own?

author: helius
author_rank: Super Contributor
timestamp: November 24, 2018, 05:48:39 am
content: snickerdoodle one is $95red pitaya 1.1 ("STEMlab 125-10") is 239€, 159€ academicparallella Z010 is $99picozed is $213+; microzed is $178+; minized is $89zybo is $189

author: xaxaxa
author_rank: Regular Contributor
timestamp: November 24, 2018, 05:51:18 am
content: yeah these are the same ones i found... guess it's time for SDRAM routing and several prototyping rounds.

author: dcarr
author_rank: Regular Contributor
timestamp: November 24, 2018, 07:50:40 am
content: Where does one find a Zynq for $20? That's pretty cheap!

author: xaxaxa
author_rank: Regular Contributor
timestamp: November 24, 2018, 12:05:41 pm
content: Quote from: dcarr on November 24, 2018, 07:50:40 amhttps://item.taobao.com/item.htm?spm=a1z0d.6639537.1997196601.4.2b557484x1AzCg&id=569648024452https://detail.tmall.com/item.htm?spm=a230r.1.14.18.560e3ecbyL11hL&id=20232273771&ns=1&abbucket=17https://item.taobao.com/item.htm?spm=a230r.1.14.49.2e5545d2bNnctN&id=578300163743&ns=1&abbucket=17#detailprobably will need some baking though

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: November 25, 2018, 03:09:00 am
content: MyirMYIR ZTURN litehttp://www.myirtech.com/list.asp?id=565$USD 69-75MYIR MYC-Y7Z010/007s cpu modulehttp://www.myirtech.com/list.asp?id=583$usd 85

author: daybyter
author_rank: Frequent Contributor
timestamp: November 28, 2018, 10:21:53 pm
content: Are you interested in designing a PC card with an FPGA on it?

author: daqq
author_rank: Super Contributor
timestamp: November 29, 2018, 03:40:15 pm
content: Try looking at the stuff from Enclustra. Reasonably priced, easy to integrate.https://www.enclustra.com/en/products/system-on-chip-modules/
Black Friday and Xilinx have a bargain for you - Page 1
Forum section: electronics / general

author: TimCambridge
author_rank: Regular Contributor
timestamp: November 24, 2018, 01:40:23 am
content: Yes indeed, 2 sq cm of the purest silicon: XCVU13P-3FLGA2577E $88,766.64, qty 1I expect they offer a discount for serious volume.A Ferrari still cost a little more, between two and five FPGAs.Sort the table the other way and we get: XC3S50A-4VQG100C $8.05, qty 1. Coincidentally, that's the value of my car.

author: westfw
author_rank: Super Contributor
timestamp: November 24, 2018, 03:30:14 am
content: I have a box somewhere with about $60000 worth of Xilinx FPGAs that I rescued from a dumpster (looking at digikey prices near the date I found them.) I thought there might have been a mistake, so I asked around, but the answer was that they were old enough to be "no longer useful" and "even if they were, we couldn't move them from engineering to manufacturing." I guess they're worth a lot less now (another 6+ years have gone by), and I really should throw them away. (1156 pin BGAs. Not something a hobbyist is ever likely to use.) (also likely to be something that if you really needed, you wouldn't be buying from an individual, either. So eBay is probably useless.) Sigh.

author: ataradov
author_rank: Super Contributor
timestamp: November 24, 2018, 07:16:06 am
content: Looking at distributor prices on older FPGAs is counter productive. The price goes sharply up as devices mature.

author: legacy
author_rank: Super Contributor
timestamp: November 24, 2018, 12:39:36 pm
content: Quoteyeah, crazy stuff. My friend TheHalloween have recently seen a Lego kit to build your own scale model of Millennium Falcon Star Wars Spaceship, but the kit is listed for 88,900,000.00 euro qty=1 so we are both still wondering if Han Solo (Harrison Ford) is also included in the box for giving you instructions in person(probably the right price was 88.90 euro, and someone or something messed up with zeros)

author: technix
author_rank: Super Contributor
timestamp: November 24, 2018, 01:46:29 pm
content: What is that thing? (And I don’t expect US customs would allow me take it with me thanks to my Chinese passport.)
Altera 5M80Z CPLD programs ok but little current draw - Page 1
Forum section: electronics / general

author: alexig
author_rank: Contributor
timestamp: November 18, 2018, 11:56:53 am
content: Hi there,I've got an Altera 5M80Z CPLD which I've programmed via JTAG and it succeeds however there is almost no current draw and I'm using 56 LEs. I'm only seeing 1.5mA current draw which was also the case when it was blank (likely just the LDO).I have used the older style 3.3V EPM3064 CPLDs without issues and could see the current draw change when they were programmed.Is there something I'm missing with the new style of CPLDs? I just have the 1.8V LDO with 1uF caps, the 3.3V being feed in directly, no pull-ups/downs on any pins.Thanks!

author: Bassman59
author_rank: Super Contributor
timestamp: November 18, 2018, 09:46:55 pm
content: Quote from: alexig on November 18, 2018, 11:56:53 amIs your clock running?

author: alexig
author_rank: Contributor
timestamp: November 19, 2018, 08:53:11 am
content: Thanks for the reply!No clock is running as yet. I was just expecting to see a large difference in current like in the old ones, sounds like it's gotten way better now. Running a voltage on the clock line does seem to give 3.3V on the CPLD's outputs checking on the scope, so it's looking promising.I'll build up more of the board and see how it goes.

author: Bassman59
author_rank: Super Contributor
timestamp: November 19, 2018, 04:30:29 pm
content: Quote from: alexig on November 19, 2018, 08:53:11 amMost of the current consumption is dynamic, so without a clock, your quiescent current draw should be about what is indicated on the data sheets.
Xilinx Vivado Training Material. - Page 1
Forum section: electronics / general

author: mrpackethead
author_rank: Super Contributor
timestamp: October 28, 2018, 04:03:13 am
content: Any suggestions for good training material on using Vivado

author: Fred27
author_rank: Unknown
timestamp: October 28, 2018, 08:35:13 am
content: I'm trying to get my head round the MiniZed and I'm finding the Avnet Speedway stuff is helpful. It covers using Vivado at the start, but there may be more specific courses.

author: tggzzz
author_rank: Super Contributor
timestamp: October 28, 2018, 10:51:33 am
content: Won't teach you how to use FPGAs effectively, but...http://svenand.blogdrives.com/https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Adam-Taylor-s-MicroZed-Chronicles-Part-235-Multi-Channel-DMA-and/ba-p/828116
Xilinx Microblaze,  FreeRTOS + LwIP or  FreeRTOS + TCP - Page 1
Forum section: electronics / general

author: mrpackethead
author_rank: Super Contributor
timestamp: October 28, 2018, 04:00:20 am
content: Would there be any advantage in using FreeRTOS + TCP, over FreeRTOS + LWiP which seems to be the Xilinx standard way of implmeneting an IP stack in Microblaze. it seems that FreeRTOS + LWiP has been ported for Zync, but not for Microblaze.Hopefully someone with some experience might suggest a way forward.
c-program windows talk to pcie xilinx ? - Page 1
Forum section: electronics / general

author: sudo
author_rank: Newbie
timestamp: October 17, 2018, 09:01:12 am
content: HiI need an c-program that could be compiled (eg mingw on win) and run on a windows7 machine that reads, writes to a pcie (xilinx) cardattached to the pc. Are there any suggestions of a simple ready to use open c-program that I could start with and modify?Thankss

author: technix
author_rank: Super Contributor
timestamp: October 17, 2018, 11:20:46 am
content: You will have to refer to Windows DDK to create your kernel code since a direct FPGA attachment to PCIe usually requires drivers to go with it.Prepare a trash machine that you dont mind one BSOD every second and give both it and your main workstation some kind of RDMA support (IEEE 1394 or Thunderbolt) for kernel mode debugging.

author: dmills
author_rank: Super Contributor
timestamp: October 17, 2018, 11:54:04 am
content: Or cheat!Find a well documented something that is sort of kind of like whatever you are going to implement, and setup the PCIe endpoint on the FPGA to pretend to be it, then just use the normal kernel driver for whatever it is.I have used this to great effect with some custom AD stuff, by pretending to be a multichannel sound card, saved a lot of driver writing.Regards, Dan.

author: technix
author_rank: Super Contributor
timestamp: October 17, 2018, 01:15:21 pm
content: If you can live with not directly attaching your FPGA to PCIe (this will actually allow you use cheaper, non-SerDes chips) you can use something like a WCH PCIe-to-parallel bridge.
FS: Nios II Embedded Evaluation Kit, Cyclone III Edition - Altera - Page 1
Forum section: electronics / general

author: Aurelio
author_rank: Contributor
timestamp: December 19, 2016, 02:40:37 pm
content: Hi all,i'm selling my altera development kit. Due to other priorities i need to cut some of my projects ;-).Kit is just used to fiddle around a bit. all is in good shape and fully working.I'm able to send to European countries.Looking for250EUR150 EURbut will consider any reasonable offer.Pictures in attachement

author: Aurelio
author_rank: Contributor
timestamp: September 19, 2018, 06:52:37 pm
content: Price drop.
poblems with capturing the sine wave in xilinx chipscope! - Page 1
Forum section: electronics / general

author: javad2040
author_rank: Contributor
timestamp: August 26, 2018, 10:46:53 am
content: Hi guys,I designed a Data Acquisition system with ADS131e08 ADC and spartan6 FPGA.I config the ADC and read data from it by my vhdl code that it contains several States. In this states, the ADC first reset and then the Config registers sets correctly.I use xilinx Chipscope to capture the received data. when the Analog input of ADC is set to DC values, the received data in chipscope is correct and no problems, but when analog input connected to AC value(sine wave), the received data is not sine.I set the ADC parameters to:Fclk= 2.048 MHzFsclk = 18.432 MHzFchipscope= 2* FsclkData Rates : 1KSPSRESOLUTION = 24bitAVDD = +2.5vAVSS = -2.5vsine Wave (peek to peek = 4v) that is less than the ADC Vp-p = AVDD - AVSS.I guess the problem is related to the Chipscope settings?Rights?Please help me to solve this problem.regards,

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: August 26, 2018, 12:01:43 pm
content: javad2040 it would be way more helpful for us if you could share some codes or your chip-scope files

author: iMo
author_rank: Super Contributor
timestamp: August 26, 2018, 12:03:55 pm
content: It may work provided your Gain=1 and the 4Vpp sine signal is centered at 0V.The Signal_pp*Gain must fit into AVDD-0.3V .. AVSS+0.3V, afaik.

author: javad2040
author_rank: Contributor
timestamp: August 28, 2018, 06:23:08 am
content: Thank you for reply.The ADC Registers are:CONFIG1 = 0xD6 , CONFIG2 = 0xF0 , CONFIG3 = 0xC0CH1SET = 0x10 , GAIN1 = 1 , MUX1 = 000 (normal input)CHnSET = 0x90 , n = 2...8 this channel power downedandFclk = 2.048 MHzFsclk = 18.432I change the Fchipscope to new value that produced by this manner:I use sine wave with frequency 50 Hz that period of it is 20ms. I sample the sine wave 256 times with ADC that total frequency is 256 x 50Hz. I produce this frequency by counter and send it to the Xilinx ChipScope and received data is semi-sine wave (below figure) and should be sine wave because of ADC resolution (24 bit).I use oscilloscope to saw the sine wave that Vp-p of it is whole 4v that is safe and less than the ADC inputs Vp-p.Please help me to find the problem and ADC capture the sine wave correctly.best regards,
MAC for xilinx FPGA - Page 1
Forum section: electronics / general

author: rakeshm55
author_rank: Regular Contributor
timestamp: October 12, 2018, 11:55:51 am
content: I would like to have a 10/100 Ethernet link for an Artix FPGA.I guess there is no hard IP available for ethernet MAC.... Is there any free IP available from Xilinx for ethernet MAC...I have heard of AXI Lite Ethernet...Can it be interface with VHDL wrapper and do not indent to use a microblaze .... I need to have just MAC to MAC communication and not any ethernet protocol....has any one used this AXI Lite ethernet?? any suggestions.....

author: legacy
author_rank: Super Contributor
timestamp: October 12, 2018, 01:44:11 pm
content: I prefer using an external PHY and Netchip for the NIC. There are kits with SPI interfaces rather then 8bit/16bit/32bit asynchronous interface. Usually with a cost between 10E and 20E.

author: Morgan127
author_rank: Contributor
timestamp: October 12, 2018, 02:39:05 pm
content: I use theseEthernet FPGA cores. No processor is needed. You only add a netlist to your project.They work great. Both TCP/IP and UDP are supported.A bonus is that you get remote programming over Ethernet and a remote integrated logic analyzer.All is free to download and use if it is not commercial.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: October 12, 2018, 03:25:05 pm
content: Quote from: rakeshm55 on October 12, 2018, 11:55:51 amWhat exactly do you mean by that?If you want a device-to-device link over ethernet hardware that doesn't need to talk to other things, then it's quite easy to talk direct to a PHY chip and send raw packets.

author: rakeshm55
author_rank: Regular Contributor
timestamp: October 13, 2018, 12:42:33 am
content: I want to establish communication with a processor via ethernet link .... processor uses EMAC .... so want to have MAC at FPGA side....

author: hamster_nz
author_rank: Super Contributor
timestamp: October 13, 2018, 01:08:41 am
content: Quote from: rakeshm55 on October 13, 2018, 12:42:33 amHow do you propose to discover each other's MAC addresses? Or just use broadcasts or promiscuous mode?

author: rakeshm55
author_rank: Regular Contributor
timestamp: October 13, 2018, 05:39:47 am
content: I do not know about any of the above modes......I need to look up on this....Mine is just a one to one connection via ethernet link used for data exchange....this was proposed as a highspeed link 100Mbps...My guess was I will feed in data to processor MAC and data would be available at FPGA MAC & vice versa....
Xilinx XC2018. Useful or rubbish? - Page 1
Forum section: electronics / general

author: wilfred
author_rank: Super Contributor
timestamp: April 12, 2018, 12:44:08 pm
content: /.

author: ehughes
author_rank: Frequent Contributor
timestamp: April 12, 2018, 12:54:52 pm
content: Chuck them if you value your time.

author: james_s
author_rank: Super Contributor
timestamp: April 12, 2018, 06:03:31 pm
content: They might be useful for soldering practice, or someone's artsy-fartsy project, but I doubt they will be useful as FPGAs. They are likely less capable than many CPLDs on the market now.

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: April 13, 2018, 02:11:01 am
content: They must have known what year you were going to ask this.

author: pigrew
author_rank: Frequent Contributor
timestamp: April 13, 2018, 03:26:59 am
content: Sell them on evilBay? It looks like a few have sold this year for about $15 each.

author: westfw
author_rank: Super Contributor
timestamp: April 13, 2018, 06:39:17 am
content: I have a bunch of xc3142 and xc3042 awaiting a similar decision (for well past a decade, now...) :-(

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: April 13, 2018, 10:03:57 am
content: Stick them on ebay - there may be people who want to keep old equipment running. Waste of time trying to use them yourself. Even getting devtools running is likely to be a challenge - dos, extended memory, dongles etc.

author: james_s
author_rank: Super Contributor
timestamp: April 13, 2018, 05:03:52 pm
content: Maybe just put the whole lot on as one deal with a minimum bid just high enough to cover the fees? Or put them as a fixed price BIN listing for some low price and give it a couple weeks before you chuck them.

author: westfw
author_rank: Super Contributor
timestamp: April 14, 2018, 08:43:43 am
content: Also, I have XCV1600-8FG1156 chips that I've mentioned before. Worth about $3k each, back when they were current (2003?)34992 logic cells. 1156 ball BGAs. Even given tools I couldn't do anything with them :-(Alas, I feel funny selling stuff (even at giveaway prices) that I've dumpster-dived at work. Perhaps stuff "times out" eventually and it would be OK...
SOLD: Xilinx Zybo Zynq-7000 ARM/FPGA SoC Development Board - Page 1
Forum section: electronics / general

author: cowana
author_rank: Frequent Contributor
timestamp: December 31, 2017, 11:50:49 am
content: While sorting through my storage over Christmas, I came across aZybo Zynq-7000 ARM/FPGA SoC Development boardthat I never got round to playing with:"The 410-279P-KIT is a ZYBO Zynq-7000 development board. It is a feature rich, ready to use, entry level embedded software and digital circuit development platform built around the smallest member of the Xilinx Zynq-7000 family, the Z-7010. The Z-7010 is based on the Xilinx all programmable system on chip (AP SoC) architecture, which tightly integrates a dual core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. The ZYBO provides an ultra low cost alternative to the ZedBoard, for designers those do not require the high density I/O of the FMC connector and want to leverage the massive processing power and extensibility of the Zynq AP SoC architecture. The ZYBO is compatible with Xilinx's new high performance Vivado Design Suite as well as the ISE/EDK toolset."512MB x 32 DDR3 with 1050Mbps bandwidthDual role (Source/Sink) HDMI port, 16bits per pixel VGA output port and tri-mode Ethernet PHYMicroSD slot (supports Linux file system)OTG USB 2.0 PHY (supports host and device)Audio codec with headphone out, microphone and line in jacks128MB serial flash with QSPI interfaceOnboard JTAG programming and UART to USB converter6 pushbuttons, 5 LEDs and 4 slide switchesSix Pmod connectorshttp://uk.farnell.com/digilent/410-279/dev-board-zybo-cortex-a9-fpga/dp/2456788It's brand new and has never even been powered up. I also have theofficial Digilent 5v, 2.5Apower supply (which isn't normally included when you buy the board from a retailer). The plug is a US fitting, but it is 100-240v input, so that's just a simple adapter rather than anything more complex.Including VAT, the new price for the board and power supply is just over £180. Is there any interest at £90 including UK shipping for the pair?AndyEdit 19/01/18: price droppedEdit 24/01/18: sold

author: cowana
author_rank: Frequent Contributor
timestamp: January 19, 2018, 09:10:31 am
content: Update: Still available, price dropped
Xilinx FPGA: How to define "dummy" inputs in UCF file? - Page 1
Forum section: electronics / general

author: ebastler
author_rank: Super Contributor
timestamp: February 22, 2018, 06:38:51 am
content: I am currently tinkering with an FPGA-based project (using a Spartan 6). I use a modified board from an older project as my test bed for the moment, while getting the VDHL to work and confirming what I/O and user interface controls I want on the final PCB.The prototype board is lacking some features I will put onto the final PCB, including a few switches used for option selection. I can do without them for now, but need to feed the VHDL logic a defined pattern of 1's and 0's to enable the standard configuration I currently develop and test for.Obviously I could modify the VHDL to replace the external inputs with constants. But I would prefer to do this in the UCF file -- I might forget about the workaround in the VHDL, while the UCF will need to be modified for the final board in any case. I had hoped to find an option in the UCF syntax to define an input pin as "constant logic high" or "constant logic low", but have come up empty.Does such an option exist? If it doesn't, how would you handle a board variant with "missing inputs" in the cleanest way?Thanks!Juergen

author: Someone
author_rank: Super Contributor
timestamp: February 22, 2018, 07:21:19 am
content: If its mapped to a physical pin you can set a pull-up or pull-down. Or add a top level wrapper for your development that has all the test harnesses in place and maps through to the physical pine.

author: ebastler
author_rank: Super Contributor
timestamp: February 22, 2018, 07:59:59 am
content: Quote from: Someone on February 22, 2018, 07:21:19 amAh, right -- I do have unused physical FPGA pins on the old board, of course, and can map to these. Could have figured that one out myself, but I was too fixated on the "I want to define this as just a logic constant" approach... Thank you very much for helping me over that hurdle!
Xilinx PLL Mamimum output frequency - Page 1
Forum section: electronics / general

author: javad2040
author_rank: Contributor
timestamp: June 02, 2018, 11:28:27 am
content: hello guys.I design an FPGA board that contain Xilinx Spartan6 and Micron SDRAM. I wrote SDRAM Controller Code for transfer data. For testing the code i use Xilinx ChipScope. As i noticed the Chipscope samples data on twice the Desing-under-test frequency; so i use Xilinx LogiCORE™ IP Clocking Wizard core for generate related clocks that the input clock is 18.432 MHz frequency and i need three Frequency that they are 92.16Mhz phase=0, 92.16Mhz phase=180 and 184.32Mhz phase=0.When i select this frequencies in the clock wizard, the 184.32Mhz can't support and it is strange. can anybody help me to solve it?my purpose of 184.32MHz clock is to test my SD-RAM design with chipscope, which is not currently working

author: dmills
author_rank: Super Contributor
timestamp: June 02, 2018, 01:58:54 pm
content: The problem is the PLL input frequency, seehttps://www.xilinx.com/support/documentation/data_sheets/ds162.pdfwhich give the PLL input minimum clock frequency as 19MHz.....Can you replace the 18.432MHz osc with maybe one at twice that frequency which would then be easily within the PLL range?Failing that, and with the proviso that you would be running the thing out of specification so it may or may not work, just lie! Tell the clock wizard that you are running with a 20MHz clock and tweak the output frequency settings to suit, odds are it will still lock. I would not do this in a production design, but if this is a one off prototype, then whatever works....Regards, Dan.

author: hamster_nz
author_rank: Super Contributor
timestamp: June 02, 2018, 07:36:01 pm
content: ... however, if you use a DLL, the minimum input is 5MHz, so as log as you use the DLL you should be OK.The DLL can only generate a single frequency, Maybe first use a DLL to generate the 184,32 MHz, then use a PLL after that to generate the clocks you really want.

author: javad2040
author_rank: Contributor
timestamp: June 03, 2018, 05:36:52 am
content: hithank you for reply.fortunately my problem is solved. I use tow DCM for generate related clock signals that the first generates clocks with 92.16MHz and below frequency and second generates 184.32Mhz frequency.
WTB: PCI-X Altera fpga board - Page 1
Forum section: electronics / general

author: marshallh
author_rank: Unknown
timestamp: November 09, 2017, 10:52:59 pm
content: NOT PCIe - this is 64bit PCI.Altera made one with CycloneII - it's a long shot, but I'm really looking for one.

author: legacy
author_rank: Super Contributor
timestamp: November 10, 2017, 11:24:06 am
content: eh, me too ... last time i found one (on ebay dot com)it was listed at 500 USDgood luck

author: ebclr
author_rank: Super Contributor
timestamp: November 10, 2017, 11:35:03 am
content: Much lower grade, but may helpshttps://item.taobao.com/item.htm?spm=a230r.1.14.103.1ac54b96oa6hn3&id=38379285235&ns=1&abbucket=12#detail
Impressive Xilinx device - FPGA, ARM + RF DACs/ADCs - Page 1
Forum section: electronics / general

author: daqq
author_rank: Super Contributor
timestamp: October 25, 2017, 06:14:17 am
content: From the Xilinx news:QuoteI'm pretty sure that it'll cost a gazillion, will be subject to every known export control, will require a PCB from hell, but damn... that's impressive. Depending on the ADC specs you could build an impressive scope/function gen just from that alone.https://www.xilinx.com/news/press/2017/xilinx-delivers-zynq-ultrascale-rfsoc-family-integrating-the-rf-signal-chain-for-5g-wireless-cable-remote-phy-and-radar.html?utm_campaign=rfsooczu&utm_source=et&utm_medium=nl-en-r30&utm_term=&utm_content=nd-radar.html

author: ataradov
author_rank: Super Contributor
timestamp: October 25, 2017, 06:22:14 am
content: Those are for communications. Those ADCs may not behave well at DC. And their expected price is $5000-10000/device. So I doubt anyone will build a scope out of this.
[FS EU] Altera  FPGA Board etc - Page 1
Forum section: electronics / general

author: RoadRunner
author_rank: Frequent Contributor
timestamp: January 02, 2018, 10:51:53 pm
content: i have few items i would like to get rid of to buy component for next project. i may add more items to list in coming days.Altera Cyclone III FPGA Board DK-START-3C25N , barely used , 60 EURhttps://www.eevblog.com/forum/buysellwanted/for-sale-altera-cyclone-iii-fpga-board-dk-start-3c25n/msg958523/LCDTI boardHercules RM42x LaunchPad , new , 10 EURhttp://www.ti.com/tool/LAUNCHXL-RM42C2000 Piccolo MCU F28027 LaunchPad , new , 10 EURhttp://www.ti.com/tool/LAUNCHXL-F28027Stellaris® LM4F120 LaunchPad , new , 7 EURhttp://www.ti.com/tool/EK-LM4F120XLCC110L RF BoosterPack , New 12 EURhttp://www.ti.com/tool/430BOOST-CC110LfreescaleFRDM-KL25Z , new 8 EURArm® Cortex®-M0+ processorhttps://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25ZFRDM-K64F , new 19 EURhttps://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k2x-usb/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64FATMEGA16 BOARD with ,Expansion PORT for LCD , LED , Dual Temperature sensor and so on. 15 EUR . see schematic and images for detailsi can ship anywhere in the world (with few exceptions) , shipping starts from 1.5 EUR Depending on item , you pay original shipping , PAYPAL or SEPA transfer.please drop a personal message if any questions or suggestions in mind.
New generateur DDS with Altera cyclone IV. - Page 1
Forum section: electronics / general

author: Diabolo
author_rank: Regular Contributor
timestamp: July 16, 2017, 06:00:32 pm
content: Hello,Here is the new Feeltech DDS generator equipped with an Altera Cyclone IV clocked with SPXO 50mhz .The model I bought is 2300H-25 Mhz.Below the printed circuit there are 1xTHS3001 and 1xMC4558 with radiator fixed with one screw.What do you think ?Sorry for my English, I use a translatorRegards,Alain

author: eurofox
author_rank: Unknown
timestamp: July 16, 2017, 06:21:41 pm
content: Quote from: Diabolo on July 16, 2017, 06:00:32 pmDid you make some test to check if there is any improvement?Vous avez fait des tests pour vérifier s’il y a des améliorations?

author: Diabolo
author_rank: Regular Contributor
timestamp: July 16, 2017, 06:38:10 pm
content: Hello,The curves and signals are correct and do not distort.I have not done great testing, but it's okay and better than other low cost DDS generators tried in the blog.The blog specialists will do more tests than mine.I have no connection with the company Felltech company.Sorry for my English, I use a translator.Regards,Alain/Diabolo

author: Diabolo
author_rank: Regular Contributor
timestamp: July 24, 2017, 05:50:16 pm
content: Hello,Here are some curves with FY2300HSquare 10Mhz-Sinus 25 Mhz-Triangle 20 Mhz-Scie 10Mhz-Only everything is not perfect :Square 20Mhz-Scie 20Mhz-Regards,Diabolo