A DC power supply for 16-bit ADC - Page 1
Forum section: electronics / general

author: onemilimeter
author_rank: Frequent Contributor
timestamp: January 23, 2011, 12:35:30 pm
content: I wish to design a DAQ board with a 16-bit ADC and an input analog span of +/-5V.Thus, the resolution is 10/(2^16)=0.000153=0.153mV.In my opinion, the noise of the DC supply to the DAQ board may affect the effective resolution of the ADC.Kindly share your view and opinion on how to design a DC supply for high resolution ADC circuit.Thanks.

author: DaveW
author_rank: Frequent Contributor
timestamp: January 23, 2011, 01:06:25 pm
content: Have you considered using a separate voltage source for the ADC, a voltage reference chip can supply a small amount of current to a very high precision, +-2mv and under 10ppm temperature drift can be bought off the shelf? You can also use this to reduce the effect of the rest of the circuit on the voltage supply. Are you putting the input signal through any circuitry before it is fed into the ADC?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 23, 2011, 01:35:56 pm
content: Most ADC manufacturers have plenty of appnotes on how to get the best performance - take a read through these to get a n idea of what's required

author: Simon
author_rank: Unknown
timestamp: January 23, 2011, 03:53:35 pm
content: the simplest method might be to power the MCU with a linear reg like a 78L05, or as others say use a voltage ref if you need high acuracy

author: slburris
author_rank: Frequent Contributor
timestamp: January 23, 2011, 03:58:13 pm
content: There are voltage regulators designed to have very low noise,for RF and precision analog applications.I'm not much of an analog guy, so you probably want to readthrough the datasheets yourself :-)For example, National's LP3999 is an RF regulator with 10uV of noise:http://www.national.com/mpf/LP/LP3999.html#OverviewMaxim has an app note about reducing noise to 7nV:http://www.maxim-ic.com/app-notes/index.mvp/id/3656and finally Wenzel has a number of interesting noise cleanupcircuits:http://www.wenzel.com/documents/finesse.htmlThis might be overkill for a 16bit ADC though.Scott

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 23, 2011, 07:46:15 pm
content: I just dealt with that actually.http://www.cafelogic.com/articles-2/a-reflow-controller-for-soldering-with-a-griddle-or-toaster/See schematic/layout for analog module.I had no trouble getting full 16-bit on input of +/- 16mV so 5V should be a piece of cake (depending on output impedance).Bottom line is think about how your digital currents are going to return to the source and if they are going to return through your analog components. Remember that currents do not return in one piece meaning a portion will always flow through the analog section. The point being that if the digital return path is twice as good (1/2 the impedance), you'll still have 33% flow back through the analog.Don't run high speed traces across breaks in your ground plane. If you don't have a power plane, use traces at least three time fatter than normal for your power and consider using a separate linear regulator to power the analog.If you don't have a ground plane, you are going to have a hard to time achieving 16-bit.For the power-noise, use an external precision reference with good PSRR.Last thing, consider the bandwidth you need and construct an RC filter at the input of your ADC that filters out higher frequency.Oh yeah, big ass low-esr bypass caps on all ICs.

author: tyblu
author_rank: Frequent Contributor
timestamp: January 23, 2011, 07:47:32 pm
content: Quote from: slburris on January 23, 2011, 03:58:13 pmGreat links, Scott! (Great Scott, links!) I love app notes like these -- better than any textbook.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 23, 2011, 07:58:18 pm
content: Quote from: slburris on January 23, 2011, 03:58:13 pmI bookmarked these, thanks.

author: jahonen
author_rank: Super Contributor
timestamp: January 23, 2011, 08:03:06 pm
content: Walter Jung'sbootstrapped "super" regulatoris even better, but has some limitations.Regards,Janne

author: jahonen
author_rank: Super Contributor
timestamp: January 23, 2011, 08:14:17 pm
content: Another thing to consider is that low-data rate sigma delta ADC's are much easier to get 16 or more bits, since they naturally reject multiples of AC mains harmonics, if the data rate (modulator clock frequency) is suitably chosen. If one needs to sample much higher rate, then the job gets much harder, as there is no natural rejection of line noise.Also, one should also read Henry Ott's paper,Partitioning and Layout of a Mixed-Signal PCB. He shows that often best way is to keep contiguous ground plane, as any slots will create voltage differences across them. Lowest ground impedance and voltage differentials between different ground points is what you want. At least in EMC tests that has been usually the winning betRegards,Janne

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 23, 2011, 08:30:09 pm
content: Quote from: jahonen on January 23, 2011, 08:14:17 pmThis was a point of confusion for me because there are 100 papers that say do and 100 papers that say don't. It seems like there are some major themes agreed upon, like if you do, then don't run high-speed traces across the gap. One microchip note even said do for delta-sig but don't for SAR. I haven't read the one you referenced (that I can rmember) but I will when I have time. Generally, I have found that the EMC people are the ones that usually screen don't, not sure why. My normal method of dealing with conflicting information in any science is to accept the info with the best supporting evidence. I happen to like this paper:http://www.nxp.com/documents/application_note/AN10974.pdfI am not going to pretend to have all the answers on that one.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 23, 2011, 08:42:03 pm
content: Quote from: jahonen on January 23, 2011, 08:14:17 pmI actually have read this paper, it was one of the good ones I thought.

author: tweek
author_rank: Contributor
timestamp: January 23, 2011, 10:05:38 pm
content: Quote from: CafeLogic on January 23, 2011, 07:46:15 pmA bit off topic but that is a sweet controller. That display is really nice.

author: RayJones
author_rank: Frequent Contributor
timestamp: January 23, 2011, 10:24:25 pm
content: You have not stated the sampling rate you are using?If using a high sample rate, you may also wish to ensure the clock used for sampling is also ultra stable. This may require a separate supply just for the clock generator.The best way to evaluate you noise performance is to capture 2^n samples eg 1024. then perform an FFT on the results.This will reveal if you have any spurious signals getting in there, degrading performance.Even better to reveal spurious signals is to average multiple FFT's over time.Simply seeing one digit of noise is not always indicative of a good sampler.

author: onemilimeter
author_rank: Frequent Contributor
timestamp: January 24, 2011, 02:30:56 am
content: Quote from: RayJones on January 23, 2011, 10:24:25 pmThanks. The sampling rate is 10 MSPS.Let's say the PSRR of an adjustable LDO linear regulator is 50dB. If two such linear regulators are cascaded in series, what will be the effective PSRR? Is it 100dB?

author: onemilimeter
author_rank: Frequent Contributor
timestamp: January 24, 2011, 02:33:11 am
content: Quote from: DaveW on January 23, 2011, 01:06:25 pmThanks. Is it possible to parallel two voltage reference chips to supply ADC which requires higher supply current?

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 24, 2011, 04:11:45 am
content: Quote from: onemilimeter on January 24, 2011, 02:30:56 amLOL, probably something you should mention next time.Quote from: onemilimeter on January 24, 2011, 02:30:56 amThat's the magic of db.

author: Chasm
author_rank: Regular Contributor
timestamp: January 24, 2011, 04:52:41 am
content: Quote from: CafeLogic on January 24, 2011, 04:11:45 amWell, that only works if there are not other effects, say parts of the stabilized circuit acting as antenna.

author: tyblu
author_rank: Frequent Contributor
timestamp: January 24, 2011, 07:21:30 am
content: Quote from: onemilimeter on January 24, 2011, 02:33:11 amI wouldn't do this unless the chip was designed for it (ie: in the datasheet or manufacturer recommended), as there may be feedback stability and current hogging issues.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 24, 2011, 08:17:46 am
content: Quote from: onemilimeter on January 24, 2011, 02:33:11 amGenerally, you would not power the ADC with a reference. Your very expensive (40$?) 16-bit 10MSPS ADC will have a high and low reference pin. If you decide to use an external reference, you would direct the output to the high pin. Take a look at your datasheet, you can not use the power voltage for reference. On that type of ADC it will always be lower. The stability of the reference is more important than the stability of the power rail.Out of curiosity, what are you using to process these 20Mbytes/sec worth of data?

author: onemilimeter
author_rank: Frequent Contributor
timestamp: January 24, 2011, 10:41:26 am
content: Quote from: CafeLogic on January 24, 2011, 08:17:46 amI wish to design a general purpose control platform with similar concept to dSPACE. We've a dSPACE system in our department. I note that the dSPACE system uses several 16-bit 2MSPS ADCs.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 24, 2011, 10:52:05 am
content: Quote from: onemilimeter on January 24, 2011, 10:41:26 amDoes that mean you haven't decided what you are going to process the data with? I mean in the short term, right after it comes out of the ADC.

author: onemilimeter
author_rank: Frequent Contributor
timestamp: January 24, 2011, 11:11:22 am
content: Quote from: CafeLogic on January 24, 2011, 10:52:05 amAt the moment, I'm thinking of using TI floating-point processor, either C2000 series or C6000 series.Thanks.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 24, 2011, 11:19:32 am
content: Quote from: onemilimeter on January 24, 2011, 11:11:22 amNice. You might already be aware but if you use the XDS100 emulator ($79), you can use code composer for free with no limitations.Good luck with that sounds like a tough project.

author: RayJones
author_rank: Frequent Contributor
timestamp: January 24, 2011, 11:28:28 am
content: We use a 160MHz C6201 and a 14 bit 40Ms/s ADC.Swinging dual port memory and DMA is the only way to feed the DSP with the data due to the bus waits that would otherwise be inserted if you used programmed access (EMIF and all that).Using DMA still binds up the external bus, but once transferred inside the DSP - no wait states are required and the thing fliesThe result data is also DMA'd out.It does get very complex keeping everything fed and maintaining throughput, but the satisfaction factor is immense.

author: jahonen
author_rank: Super Contributor
timestamp: January 24, 2011, 03:31:53 pm
content: Quote from: CafeLogic on January 23, 2011, 08:30:09 pmMaybe I'll elaborate these issues a bit more. Somebody might be interested anyway.As far EMC is concerned, the main philosophy is to constrain the current loops as small as possible, and minimize high-frequency ground potential differences. Only way to do that, is to build the system on as low impedance ground as possible. Adding slots adds impedance between two parts of the ground plane, thus creating voltage differences between plane points. This will act as a source voltage driving a dipole antenna if there is cables connecting each part of the plane. One needs only µA's of common-mode RF-current into cables to violate the FCC/whatever imposed limits. Thus slots are not recommended. At high frequencies, it is absolutely futile to try isolate just about anything due to fact that inductive and capacitive coupling gets out of hand. It is far better and more practical to establish a controlled path for return currents. Failure to recognize this will lead to EMI failure.Interesting appnote from NXP. While I don't question that in that case, connecting ground planes directly leads worse ADC performance than direct connection. However, single point direct connection between planes is not good representation what happens if the plane would have been solid all the way. One would need two different boards with otherwise identical setup. At least I understood that connection was only at one point. One connection point creates huge loop (MCU is second loop point). That will certainly affect negatively the performance. BTW, how would one connect the isolated planes together using single point if there are several ADC's on the same board? How that would be handled in a system where there are several of those boards? Each ADC would like to be in the single connection point...For ordinary two-sided boards, it actually does not matter if you cross plane splits or not, since trace width should be about same than dielectric thickness for the flux coupling (current and return current) to happen. For example, the trace impedance of a 0.2 mm wide track on 1.6 mm dielectric thickness board, yields to trace impedance of 150 ?. That is way too high for logic applications, where the impedance should be something like 50-70 ohms. For standard 4-layer board, trace width of 0.2 mm at top/bottom and reference plane (VCC/GND) in next layer, yields about 75 ohms trace impedance. If course, two sided board can work if you make the board dielectric very thin, but that is mechanically unstable solution. For OP's board buildup, I wouldn't even try to squeeze it to anything less than 4 layers. Life is difficult enough even without the signal integrity and other issues. The main DSP (especially C6000) will rule probably anything less out.For practical evidence on my side, I have designed a board at work with 16 pieces of 65 MSPS 14-bit ADC's + FPGA & acquisition memories on the same board, and ground structure was just one solid ground plane (or, actually, the board had 8 layers of solid unbroken ground planes, and 16 layers total). Noise level was what one would expect, ±1 LSB.Another example where I witnessed the success of solid planes were when I rebuilt the Tripath based D-class audio amplifier on a 4-layer PCB. Previous layout was two layer design, with two separate grounds, what Tripath recommended. Main problems were noise and high EMI levels, which even interfered with the radio/TV reception. Original advice was that single point grounding would be used and AGND/DGND would be connected together only at the module. However, I ended up just making a 2nd layer a solid plane on the new layout, and just placed power and small-signal components into grouped sections. Result was that the new layout was not only much more EMI quiet (I could remove almost all common-mode filtering at the inputs) but also audible noise went down hugely. Ever since, I have been very suspicious when someone recommends plane splits. Another myth I have been lately busting is that one should parallel different capacitors for more wideband result, nothing could be farther from the truth when one measures the results with a VNA...Regards,Janne

author: Chasm
author_rank: Regular Contributor
timestamp: January 24, 2011, 03:39:32 pm
content: Quote from: jahonen on January 24, 2011, 03:31:53 pmThat would be very interesting, splitting bypass capacitors us often used/recommended in more complicated designs.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 24, 2011, 07:18:27 pm
content: Quote from: jahonen on January 24, 2011, 03:31:53 pmI am interested, thank you for your input. I am left with one option, do my own testing. Henry Ott suggests a test, I think ill start with that. Ill let you know if I get it all figured out.

author: onemilimeter
author_rank: Frequent Contributor
timestamp: January 24, 2011, 11:46:03 pm
content: Quote from: jahonen on January 24, 2011, 03:31:53 pmI always wish to design a high-speed ADC circuit. Hope you will help to clear my doubts. The analog input span of a high-speed ADC are usually very small, e.g. 2Vpk-pk. For a 14-bit ADC, 1-LSB represents 2/(2^14)=0.122mV. Would it be difficult to design a noise level lower than 1-LSB? Do you mind to share more about your build (e.g. component selection)?Thanks.

author: RayJones
author_rank: Frequent Contributor
timestamp: January 24, 2011, 11:58:36 pm
content: Noise is not always your enemy.Correctly introduced "out of band" noise can help improve the linearity of signals exercising the lowest values.This is external noise deliberately introduced with the signal, that is later removed by the DSP processing as it is outside the expected filtered bandwidth.It all depends really on if you need the full nyquist range or not for your application.We too at work are able to get the magical +-1LSB with a 14 bit device, but better than that due to processing gain of our FIR filter (bandwidth < nyquist) are able to achieve the full 90dB of our 16bit resultant.This also is on a 8 layer board with acquisition memory and controller.Pay attention to the recommended grounding pattern, and never run digital signals over the analog input area.

author: jahonen
author_rank: Super Contributor
timestamp: January 25, 2011, 09:31:51 pm
content: Quote from: onemilimeter on January 24, 2011, 11:46:03 pmThe ADC is TI ADS6142, and it is driven by fully differential opamp (can't remember the part number, but Linear Technology type), which also serves as single-ended to differential converter. That is preceded by VGA instrumentation opamp and some signal conditioning. Note that most high-rate high-resolution ADCs use differential inputs to reduce noise.BTW, grounding advice in ADS6142 datasheet is quite simple:QuoteI think that low-impedance ground system and proper partitioning (parts placement) are the most important things to get all the bits you have paid from the ADC. Not really magical, just some common sense.Yes, small amount of noise can be advantageous, it allows you to sample signals smaller than 1 LSB, provided that there are no spurious tones there, like RayJones already pointed out. But it depends upon application.Regards,Janne

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 25, 2011, 10:22:08 pm
content: Quote from: jahonen on January 25, 2011, 09:31:51 pmMaybe buy they chose to split it. From the EVM user guide listed in your post:QuoteThis is consistent the non-committal line TI tends to take, for example, from the ADS1271 (24bit 105ksps) sheet:QuoteI can't remember which one it was but another TI app note said split the ground planes, then when you are done with the design, connect them. I took that as their recommended way to enforce layout discipline.I am planning on doing some testing involving the circumstances that I am most interested in. I will publish my results whenever I get around to that. If I ever have to do a 16-layer board (not really qualified for that), I will definitely take your word and use solid planes.

author: RayJones
author_rank: Frequent Contributor
timestamp: January 25, 2011, 10:29:22 pm
content: Our design uses a "split" ground plane that joins beneath the ADC.I used quotes as in the PCB design it is all the one ground plane, but tracks have been added to cleave the plane into two areas.These tracks do not join under the ADC.Remember that anything you add to the ground plane removes copper, not retains like on signal layers.These cuts absolutely prevent stray digital currents passing across the "isolated" analogue ground plane area.

author: RayJones
author_rank: Frequent Contributor
timestamp: January 25, 2011, 10:36:11 pm
content: I should also add that the ADC we use has differential inputs, so the ground is not part of the input signal (30MHz IF).

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 25, 2011, 10:40:54 pm
content: Quote from: RayJones on January 25, 2011, 10:29:22 pmYou lost me a little bit. Are you saying you used a solid ground plane but added tracks to a different layer?

author: RayJones
author_rank: Frequent Contributor
timestamp: January 25, 2011, 10:48:24 pm
content: Solid ground plane, with tracks added to provide a psuedo split.Protel allows you to draw on the power plane layers, but the line drawn result in etched copper.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 25, 2011, 11:05:38 pm
content: Quote from: RayJones on January 25, 2011, 10:48:24 pmOh I see, thanks.

author: RayJones
author_rank: Frequent Contributor
timestamp: January 25, 2011, 11:19:03 pm
content: We also did the same on the actual power plane, but that was a 100% isolation, no gap under the ADC.It requires proper use of the design tools to actually make the following work.You can actually carve away the isolated area and make it part of the GND plane.You can then stitch the two planes together using vias.We actually ran our signal layer between these two planes, effectively in a "ground sandwich". I suspect this was overkill, but we got the desired lack of spurious signals and full dynamic range, and have never tried just signals layers above a single ground plane - "if it ain't broke, don't fix it".But as stated, you really are getting into the nitty gritty of Protel to do that.We were using Protel99SE for this design.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 26, 2011, 12:00:49 am
content: They do it a little different in the newer versions (Altium). The planes are filled polygons for which you can specify a net. They get automatically cutout for non-net objects. You can also draw your own polygon cutouts. If you want a split ground plane, you can either draw two different polygons or you can draw a single polygon and put a polygon cutout in the middle. A track always stands for positive copper on any layer (unless it's not a copper layer, like silkscreen). I didn't realize you were referring to the specifics of your software.

author: RayJones
author_rank: Frequent Contributor
timestamp: January 26, 2011, 12:12:01 am
content: Yeah I've only just started using Altium of late with simple double sided boards, but I'd be very surprised (annoyed) if drawn "tracks" on a power plane existed as copper.They have traditionally been a negative layer compared to the rest, as that is how the traditional photo plotter would work.Best thought of the isolation pads you need around unconnected holes.It is far far easier (faster and smaller in the gerber file) to define areas where you don't want the copper on the power planes with those machines.Signal layers, for sure copper = tracks, but power planes have always been treated in a special manner?Perhaps they have reversed this, I should import the design into Altium and see how much of meal it makes of the power planes....I know this is not an official support channel, but perhaps our forum host can comment?

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 26, 2011, 12:23:06 am
content: Well, that is what I seem to remember from the videos with "Marty". It certainly could have a different mode with negative layers.

author: RayJones
author_rank: Frequent Contributor
timestamp: January 26, 2011, 12:30:23 am
content: You can of course these days use polygon pours on a conventional signal layer to achieve the same end effect.The biggest difference however I could see with that though, by default, is the size of the isolation would be much larger, and actually include a copper land with an annular clearance ring.We often do polygon pours of GND on top and bottom layers of normal double sided boards to get a better earthy chunk of copper.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 26, 2011, 12:34:51 am
content: I just checked. If you place a line on an internal plane layer, it splits the layer. Sorry I told you wrong.

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 26, 2011, 01:00:08 am
content: That's the second time this week I was wrong about something I said on this board. I hate when that happens!

author: RayJones
author_rank: Frequent Contributor
timestamp: January 26, 2011, 03:23:37 am
content: hey, no problems, don't feel ashamed. Glad I was able to show there are other ways of doing things.The concepts are closely related, and polygon pours are really handy on normal copper layers.I don't know if Altium allows you to put one on a power plane, but I suspect the end effect would be a nice hole in the power plane!

author: jahonen
author_rank: Super Contributor
timestamp: January 26, 2011, 04:56:56 pm
content: Quote from: CafeLogic on January 25, 2011, 10:22:08 pmI thought that as an experiment, I can take a unetched board, and then create two terminated transmission lines into it. Then I could use my R&S FSV7 spectrum analyzer's tracking generator to measure the isolation between two transmission lines as a function of frequency (between 100kHz and 7 GHz).Of course, there will be some crosstalk due to mutual inductance between transmission lines, but I can always compare it with the situation where I have separated the ground planes of both transmission line structures. That should give pretty much good idea how severe the coupling is due to common ground.Regards,Janne

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 26, 2011, 05:32:47 pm
content: Since I lack the experience and fancy equipment for a test like that, I was thinking I would make two boards and see which one has the least noise.

author: jahonen
author_rank: Super Contributor
timestamp: January 27, 2011, 04:28:51 pm
content: Ok, here is a much simpler (I believe just about anyone can repeat this) but still very interesting test. I took a unetched PCB and soldered few wires into it. I don't know for sure how thick the copper was, but I am pretty sure that it is 35 µm. I used then a DC lab power supply in CC mode to feed 10 A across half of the copper plane, while measuring voltage between various points. One can think that points between I1 and I2 represent the digital noisy side, and p5-p7 represents the analog side. Excitation current was fed from point I1 to point I2. Measured voltage differences between points were as follows:p1-p2: 3.42 mVp3-p4: 5.643 mVI1-I2: 10.4 mVp5-p6: 208 µVp6-p7: ~0 (less than my Gossen-Metrawatt Energy could reliably measure @ 60 mV range)p5-p7: 213 µVDC is theoretically the worst case, since it spreads to larger area compared to higher frequency stuff. High frequency ground current tends to concentrate right under the trace, due to energy minimization principle (the path of least inductance).Now, we can compare this to ADC resolution. Using a NXP mentioned 12-bit resolution ADC, 1 LSB is 0.8 mV, so the measured voltage drop is about 4 times less than ADC LSB. So I think unless you want to drive ground plane currents of 40A just near your high-resolution ADC, the plane splits are not necessary (at least not for the NXP ARM).For OP's concern about noise of less than 0.153 mV, and for realistic currents in digital section in addition that ADC's are usually differentially driven (ground reference is even farther from the digital section), the galvanically conducted plane noise is IMO quite insignificant. Reducing ground current to 1 A (even that is quite a lot), all points except in "digital side" in this test setup is much less than 1 LSB. I guess that most problems usually come from fact that digital section ground is not stiff enough (not contiguous plane), thus disrupting the analog side.Regards,Janne

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 27, 2011, 05:11:16 pm
content: That is very interesting. I am guessing you measured on top of the solder lumps instead of on copper? It seems like the drop between I1 and I2 should be 7mV. Which gives me a good idea.**Forum Math Challenge**Calculate the exact size of the board from the information given (don't tell us Janne)I am not sure it is possible, maybe only the proportion of width to height.But anyway, first of all, thank you for the experiment. It is a really good way to illustrate the reasons behind recommended layout concepts. Your results are exactly consistent with what Henry Ott said which is that splitting the plane is only beneficial if your layout sucks. For example, if there where analog components at p1,p2,p3, or p4. I would also add that this depends on there being only a single return path for current, and having the digital components closest to that return path. However, we don't live an ideal world, and that can be difficult especially when the ADC is half digital/half analog in a single IC.Of course it is hard to argue against your point given the ideal layout that you have modeled.

author: onemilimeter
author_rank: Frequent Contributor
timestamp: January 27, 2011, 06:59:45 pm
content: Very good posting by jahonen... am really appreciate!

author: RayJones
author_rank: Frequent Contributor
timestamp: January 27, 2011, 09:23:38 pm
content: This is all very interesting, but spurious signals at DC (at least in our application) are dead simple to remove.Our primary concern was fast switching signals that radiate crap everywhere, they don't even need to be on the same board.When you deal with signals that exist in the noise, sampling purity is essential.Perhaps a solid plane could be OK, but when it comes to prototype 8 layers boards, and hand assembly of fine pitch SMD which could cost $1000's to produce in small quantities (factoring in labour), and the need to pull 90dB of usable dynamic range, you pull every trick you know to ensure optimum performance on the first (or second) attempt.Besides that, you did prove there is bleed beyond the end points.Yes it is small but if you are using out of band noise, it is highly possible you could expose those small signals as spurious signals.A cut amputates that bleed effect in a definite known manner.Redesigning our known good PCB with a solid plane is not beneficial for us to prove it may degrade performance.Cuts on the ground plane are so easy to place that it is hardly worth the possible "damn I wish I placed those cuts scenario".Finally, if the chip manufacturer recommended cuts, I know I would be following their advice closer than a primitive DC test conducted in an unknown backyard.

author: allanw
author_rank: Frequent Contributor
timestamp: January 27, 2011, 10:43:50 pm
content: I think I saw the same test in one of Howard Johnson's signal integrity videos.

author: jahonen
author_rank: Super Contributor
timestamp: January 28, 2011, 05:09:32 pm
content: I agree on the point that usually one does not experiment with expensive prototype boards. I was certainly not suggesting that anybody should re-design a working board based on my experiments. I wouldn't trust a comment from a random forum from somebody completely unknown either. Instead, my experiment was meant for food of thought. Yes, it most certainly does bleed measurably between p5-p6. But between p6-p7 there was no measurable voltage (below 1 µV). That indicates that most current is concentrated near point I1. Plane resistance is not trivial to calculate, thus it is difficult to estimate the resistive coupling without measuring.I do very well know that higher frequency signals have other sometimes very bizarre coupling ways, like mutual inductance, which is naturally completely absent in case of DC. Inductive coupling is perhaps the most difficult mechanism. Only way to reduce that is to reduce the area between signal and ground and increase distance between two signal loops. However, skin depth dictates that for example at 30 MHz, skin depth is about 12 µm. One could then even put different high frequency signals in each side of the plane and still get almost no cross-coupling. That would also suggest that for high frequencies, splits are not so effective, since coupling could be due to something else than due to the IR drop of aggressor signal. RF guys usually add more grounding or shielding if they need more isolation between signals, I do not know if anyone there uses splits to reduce coupling.That's why I am also going to do some experiments in the AC domain using a spectrum analyzer with a tracking generator, like I thought above. I'm not personally completely convinced that primary noise coupling mechanism for higher frequencies is through galvanic connection via the ground plane. If it is some other form of coupling, then the slot might possibly cause things to be worse unless the effect is understood. Another thing is that if the chip has two different ground connections, it is usually stated that they should be at the same potential. Now, better the split is, bigger the difference between potentials of these two grounds, thus inter-gnd current (like common-mode) flows through the chip. My primary interest is to understand the coupling mechanisms via measurements, so I can better understand what is the dominant mode of coupling and how much, by what means and where I can degrade the shielding in case of cost reduction situation and still get acceptable results. It also enables to optimize right things in case of performance maximization. It might also well turn out that either is acceptable if properly implemented, i.e. no dramatic difference between these two school of thoughts (my best guess is this).What also bothers me, is that the "split ground"-chapter in ADC/DAC datasheets seems to be copy&paste'd for decades from one datasheet to another without anyone bothering to actually make measurements and evaluate the results for both ground methods, especially evaluating the external interference immunity. That would be much more convincing than just simple chapter of old statements. Datasheets are not unfortunately always based on physical facts, but industry practices. Although I have been getting impression that newer datasheets do not unconditionally recommend splitting so often, instead they will emphasize the correct parts placement. It is a bit like of "Faraday cage"-advice that is certainly useless unless you know that direct radiation from the circuit in it is the actual source of problem. Usually, it is the common mode ground voltage induced currents in cables what cause EMI failures, rarely the circuit board itself. If all signals entering/exiting the cage are not filtered at the edge, they will conduct the noise outside with ease, thus the cage won't improve the situation at all.Finally,ADS5485EVMseems to be using single unified ground plane, and still achieving good results. The statement about grounding seems to be reversed: "The layout features a common ground plane; however, similar performance can be obtained with careful layout using a split ground plane." I can't believe that two different ADC's obey different set of laws of electromagnetism. Same seems to be the case with ADIAD9650/AD9268/AD9258/AD9251/AD9231/AD9204/AD9269/AD6659evaluation board.Regards,JanneQuote from: RayJones on January 27, 2011, 09:23:38 pm

author: CafeLogic
author_rank: Regular Contributor
timestamp: January 28, 2011, 05:39:12 pm
content: Quote from: jahonen on January 28, 2011, 05:09:32 pmLOL, now I am sure you can understand my original statement about it being a point of confusion.

author: jahonen
author_rank: Super Contributor
timestamp: January 28, 2011, 05:50:16 pm
content: Quote from: CafeLogic on January 28, 2011, 05:39:12 pmThat's why my bet is on that it does not make a huge difference performance-wise, if properly implemented. If either would be significantly better for performance and in all cases, then that particular one would be unanimously recommended solution. Probably even the chip manufacturers can't decide which one to recommend.Regards,Janne

author: RayJones
author_rank: Frequent Contributor
timestamp: January 28, 2011, 09:38:28 pm
content: Yeah without being a particle physicist there is a lot of gut feeling in the whole process.We actually stitched together the individual split plane edges with a fence of vias along the edge as prior design work with analog filters and a network analyser revealed the nominal grounds on top and bottom layers of the board would allow signals above a GHz or so back into the passbandIf we connected them together with solder braid around the edge, the response returned to that expected.It would appear that they were not actually as solid as they seemed and looked.Whether this was truly detrimental or not was certain, but given we were using the filter in a radar receiver that has pulsed RF in the 100's kW range floating about we felt it was better to keep it out.One thing we all agree on though us never run digital signals, or any other for that matter, across the analog input section as the induced return currents that hug close below the trace are what we are aiming to avoid with either a solid or split plane.

author: saturation
author_rank: Super Contributor
timestamp: January 29, 2011, 03:16:44 pm
content: Excellent posts as always, jahonen.

author: jahonen
author_rank: Super Contributor
timestamp: February 02, 2011, 04:24:27 pm
content: After some thinking, I thought that maybe I'll use some kind of noisy digital chip to generate the noise, instead of simple two transmission line crosstalk experiment. So I decided to put a crystal oscillator driving a clock fan-out buffer which drives 4 pieces of 15 cm long ~50-ohm terminated transmission lines (transmission line lengths are precisely matched). The victim trace is a 15 cm long (also matched) transmission line, with a SMA connector at the other end, so I can easily connect it to the spectrum analyzer, which should give a sensitivity below 1 µV. I expect something like 10-50 MHz oscillator to generate rich harmonics, which should be quite easy to detect. Clock buffers are usually quite noisy, thus it is used.Here are the layouts of the boards with I intend to experiment next, to compare two "schools of thought". Design is a 4-layer board, what one could use ordinarily. 2nd layer is solid ground, 3rd layer is VCC and bottom is also solid ground. The boards are exactly identical except board "B" has a 6.5 mm wide void gap in all layers between "analog" and digital sections, except for small bridge at the left edge. Via fences are placed in moat edges of both sections.I'll have to wait until we dispatch a group hobby PCB order at my work, but as soon as I get the boards, assemble them and do the measurements, I'll report my findings here. It will be interesting to quantitatively measure the difference (at least for me).Regards,Janne

author: CafeLogic
author_rank: Regular Contributor
timestamp: February 03, 2011, 04:39:51 am
content: Looks awesome, looking forward to the results.

author: scrat
author_rank: Frequent Contributor
timestamp: February 03, 2011, 03:35:46 pm
content: Yes, should be 100dB, theoretically, since the input to output gain is -50dB for noise.

author: jahonen
author_rank: Super Contributor
timestamp: March 17, 2011, 07:46:26 pm
content: Update on this thing, got the PCB's and assembled them today. I'll try to make measurements tomorrow. Picture of the test boards attached.Regards,Janne

author: scrat
author_rank: Frequent Contributor
timestamp: March 18, 2011, 01:35:32 am
content: Quote from: onemilimeter on January 24, 2011, 02:30:56 amQuote from: scrat on February 03, 2011, 03:35:46 pmHaving seen an update on the thread, I now realize I was answering a question posted a few pages before... And what a few pages I was missing! Very interesting and high level discussion. I apologize for my last post.BTW, I look forward to the results of the experiments.

author: jahonen
author_rank: Super Contributor
timestamp: March 18, 2011, 07:45:53 am
content: Okay, I have performed the measurements. Units are dBµV, so that 0 dB is 1 µV, 20 dB = 10 µV etc. Result seems to be that neither is very goodI can only draw conclusion that there are much more dominant coupling and resonance modes involved here than just the IR drop in the ground plane. And of course that it is difficult to predict the result before you go and measure the result.One with the split has about 2 dB less coupling in lower harmonics, but 8 dB higher coupling in some high harmonic (15th I believe, fundamental is 12.288 MHz). Also, there seems to be some kind of a resonance around 300-400 MHz in the board with no split.If we compare the coupling to the 16-bit ADC with full-scale range of +-1 V, then 1 LSB is about 30 µV, which is 30 dBµV (26 dBµV if we account for RMS value). Comparing that to what I measured, the coupling does not reach this level until above 100 MHz for both cases. Of course it depends what kind of application one has, time domain or frequency domain application.Regards,Janne

author: scrat
author_rank: Frequent Contributor
timestamp: March 18, 2011, 03:19:09 pm
content: It seems like at low frequencies the return current uses a wide portion of the ground plane, while this doesn't happen in the high range. Also, the plane is acting as a screen (at high freq), maybe letting currents loops to close and oppose to the generated field, and the split cuts those loops.This is my interpretation. I know it's too easy to say now, but I would have guessed right, when I thought about the board.The situation is maybe a little far from a real board, IMHO, since there you have signals which must cross the boundaries between two different gnd domains, too.

author: RayJones
author_rank: Frequent Contributor
timestamp: March 18, 2011, 09:17:21 pm
content: Hi Jahonen,I'm a bit bemused by your solid ground plane board.You included the "via fences".Without going back, my memory is that you are proposing the use of splits is unnecessary, but the via fence is used to bond the edge of the splits to avoid radiating from each plane.May I suggest you have tested a hybrid?Perhaps the resonance is an effect of the two fences interacting, C between the planes, L between the fences.You could drill out all the via's, but it still would not be a solid plane due to all the remaining holes.

author: scrat
author_rank: Frequent Contributor
timestamp: March 19, 2011, 01:18:10 pm
content: Quote from: RayJones on March 18, 2011, 09:17:21 pmThe plane is almost continuous, those vias are so small holes that you wouldn't mind until you reach several GHz (@1GHz, wavelength into FR4 is > 130mm, into air it's about 300mm). I don't know why he decided to put them there, but since there are so many vias, the upper flood is almost uniformly stitched to the bottom plane around the board.BTW, in my previous post I didn't congratulate with Janne. It's amazing the work he's done only for the will of experimenting this single fact!

author: jahonen
author_rank: Super Contributor
timestamp: March 19, 2011, 04:18:14 pm
content: I decided to put the vias in hope that it would block power plane radiating directly to victim side of the test board. On second thought, this might not have been entirely successful strategy.Yes, it can be called an hybrid. But for the frequencies we are dealing in here, I think it can be considered as solid. What I have heard from my friend who works with mobile phone base station etc. RF-things (LNA's in the mast etc.), they seem to put ground vias just about anywhere if they want to increase the isolation. They must optimize the noise coupling into their RF-signal, and the specs are typically very strict. I asked if they use splits to isolate the control side, and the answer was no. Thus the large via count. But it is certainly true that usually they do not exist in split edges in typical designs.As for explanation for resonances, I just thought that maybe it is not radiation of the signals which seem to cause excessive crosstalk at higher frequencies, but VCC layer capacitor. My current guess is that VCC plane capacitor return current travels top/bottom sides of the board, coupling the noise to victim trace side, swamping out ground noise. VCC layer has also a big slotted hole due to all those ground vias, creating a big loop (which may cause resonances). In split board, this loop does not exist, as the all the planes have been cleared. Fortunately, this loop is relatively easy to cut (only two narrow bridges exist at each side of the board). So more testing is in order, I think.Here are the images of GND and VCC layers attached from CAM350.Regards,Janne

author: RayJones
author_rank: Frequent Contributor
timestamp: March 20, 2011, 03:54:27 am
content: Ahhh, the "hidden" power plane.I'd definitely try cutting in at the edge of board at the bottom row of vias, thus isolating the VCC plane entirely.If you could, you should even try tying the floating copper to ground (easier at the PCB design level than post production)You wouldn't route stray digital signal lines over your analog input, likewise a full slot absolutely isolates noisy impulse currents from the power plane.This then returns back to the original question, slot or no slot on the ground plane.The logical extension is if you control the radiation from the power plane with a slot, should not also do so for the other half, the ground plane?Get more intriguing, keep on trying!

author: jahonen
author_rank: Super Contributor
timestamp: June 14, 2011, 05:11:59 pm
content: Sorry for late reply but here are the results with VCC plane cut. I also reduced the attenuation on the spectrum analyzer to minimum, to reduce the noise floor.It seems that the noise is dramatically reduced for both cases when VCC plane is cut. Coupling must have therefore been due to PCB antipad-plane capacitance. There seems to be some advantage (maybe 2-5 dB at best) for the slot, after all, but then, it is considerably worse in narrow frequency region, between 500 and 600 MHz, as you can see (last image shows the "advantage" of the slot, bigger number is better).There seems to be bigger advantage on even harmonics, but I guess that is not real effect in PCB, but a duty cycle variation between two different oscillators and clock skew variations on the clock buffer.It is therefore verified that digital power supply planes should not be poured in analog section, careful filtering is required in between.Regards,Janne