SPI Termination - head spinning, please clarify - Page 1
Forum section: electronics / general

author: jnz
author_rank: Frequent Contributor
timestamp: April 28, 2016, 09:54:51 pm
content: I'm laying out a part right now and want to try and adhear to best practices where possible.4 layer PCB, .33mm traces, ground and power planes, ARM master, 4 slaves, not daisy-chain compatible, 7" longest trace distance from master to farthest slave, 2-4Mhz SPI desirable. 3 devices are identical and require a pullup on the MISO line, the fourth device has it's own pullup but only when actively transmitting, my prototype has a 2.2k pullup on the line and everything works well enough.I've been reading about serial termination. Read a study that showed it's good to put a series resistor to stop reflections at the source/output, but not actually required to be there as long as it's in between someone it works well enough.See pic.My initial option put very little thought into termination except that maybe I'd put a 50-100ohm resistor at the source of each signal. First routing attempt I was mindful but a little loose. Holy crap though, after reading every single link on SPI Termination I can find, it's amazing SPI has ever worked for anyone at any speed ever! I'm not sure if I'm finding legit info, or I'm finding some "professor" who wants to prove how smart he is by over-inflating the issues.Option A: One site I read said to never use stubs / star, but always try and daisychain the connections in routing. This gets a little confusing because daisychain has a meaning specifically to SPI. But the short version was to never use stubs, always run each connection through the previous. Not sure if I believe this. Because each device will only ever be "talked to" exclusively with activation of the SS line, so what does it matter if X or Y device sees reflections so long as Z device is outputing?Option B: I read DO and DO NOT do this posts on this. Some people reported success by controlling the slew or rise time on the Clock and data lines.Option C: Someone highly recommended splitting each device's line into it's own trace only joining at the micro/master at the last possible second. Again, I have no idea what this is supposed to do because with the slave select pin, everyone else should be "off" when I'm talking to a specific deviceOption D: A highly recommended option was end of the line termination to 1/2 supply voltage. This is obviously wasteful with the recommended 100/100ohm ladder. But, since I need a pullup on the MISO line anyhow it kind of made sense.I've been reading too much on it, and understanding too little. Can someone just give me the for dummies version please!?

author: ade
author_rank: Unknown
timestamp: April 28, 2016, 10:48:03 pm
content: At 7" distance, I doubt you'll need to worry about reflections enough that you'll need to terminate the signal. Do you know the rise time of your SPI master? From there you can calculate the max length before reflections start to become a problem.

author: uncle_bob
author_rank: Unknown
timestamp: April 28, 2016, 10:58:40 pm
content: HiIs this a commercial product?Do you have an EMI / RFI requirement?Do you have a reliability spec?There are lots of reasons to terminate lines other than bit errors 100% of the time ...on the other hand, they don't apply to all the designs done by everybody.Bob

author: Apollyon25_
author_rank: Regular Contributor
timestamp: April 28, 2016, 11:10:05 pm
content: I put provision for an RC on all digital comms and control lines, purely so I can tweak offending signals, if required.I haven't ever encountered problems with SPI running various clock speeds though. Even with all manner of other clocks and high current transients around the board...You might be in danger of overthinking it. If you are worried, put a scope on the lines at each of the device termination points and have a look at the waveforms. You want to look for any ringing on your clock line sufficient to cross thresholds unintentionally, causing double-clock-edge instances. I use horizontal cursors placed at the logic level thresholds, then move the trigger location to these. Unless you have a scope able to detect and trigger on runt pulses.Suitable plane connections and decoupling would be the next points to check to make sure you arent coupling supply noise into your comms lines.As Bob has said, it depends on other factors as well...

author: jnz
author_rank: Frequent Contributor
timestamp: April 29, 2016, 04:28:54 am
content: Quote from: ade on April 28, 2016, 10:48:03 pmUm, 4Mhz ARM, I could figure the rise time but not sure yet. No, I agree 7" combined trace length at the last node isn't going to be a problem most likely, I just want to set it up "right" if I can. And since there are degrees of "right", maybe just get it 80-90% of the best practices way there and move along.Quote from: uncle_bob on April 28, 2016, 10:58:40 pmNo. I kinda just want to get a nice setup that I can use in any SPI implementation. One that works well and if I had to got to 8-10MHz wouldn't leave me head scratching. One that's like "well, that isn't perfect, but it's pretty decent". I'd like to know "BEST PRACTICE" but then scale that down to "reasonable solution" for my application.Quote from: Apollyon25_ on April 28, 2016, 11:10:05 pmSo you leave a spot for a resistor and cap. Does it matter where these are located on the line? Different than my crude example?QuoteI absolutely am. In 12 years I've never had an SPI issue. But I was dumb and searched for SPI termination and here we are!So, before I click order on my next board, I want to make sure I'm at least making an effort to plan and route something "a right" way. I have a working example with most of the parts this new project has, no issues that I know of.QuoteThe supply and each device is decoupled well. (Actually I have to make another post on that later) can you elaborate if you didn't mean device decoupling? And anything in terms to plane connection "suitability"?Thanks guys!

author: ade
author_rank: Unknown
timestamp: April 29, 2016, 05:08:49 am
content: QuoteAssuming you are using hardware SPI then the SCK min/max rise time should be specified in the MCU's datasheet, usually under the electrical characteristics section.I have seen some SPI hardware with relatively fast rise times (1.25ns) -- these might benefit from termination after only about 4 inches.

author: jnz
author_rank: Frequent Contributor
timestamp: April 29, 2016, 04:58:06 pm
content: Quote from: ade on April 29, 2016, 05:08:49 amYes, hardware SPI. STM32F103. Well, there is a MAX time listed, but not a nominal or a min. So I'm not sure if this helps me at all.

author: hans
author_rank: Super Contributor
timestamp: April 29, 2016, 05:33:04 pm
content: Look at the specs for the GPIO pins. On STM you configure GPIO's as alternative SPI, but can still set I/O drive strength.On a design I did that had 7" long traces, I eventually settled with low drive strength. I had 22 series resistors which helped till medium speed, but at high speed I saw overshoot. I had to resort to 39 ohm or higher to fix that. That was a 6-layer PCB by the way.Fortunately in that case I was able to avoid stubs to SPI slaves by assigning separate SPI peripherals to each device (had about 3). This has the added bonus of avoiding any software conflicts when dealing with parallel access.

author: Scrts
author_rank: Frequent Contributor
timestamp: April 29, 2016, 06:19:43 pm
content: I would personally put a pull-up only like in option D. Usually, I'd pull down, but apparently you need a higher rise time, so this is why the pull-up is there.On top of that, I also put 22ohm in-line (series termination) resistors on SCK, MISO & MOSI too.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 30, 2016, 02:36:47 am
content: First priority: Use a source termination resistor on each edge triggered (CLK) pin driver.Second priority: Minimize stubs, trace length on all signals.If you can afford enough source termination that the whole net acts as a capacitor (Rs >3*Zo, say), the risetime will obviously be awful, but you won't have to worry about anything because the whole net will act in unison.Load termination, other signalling methods: don't worry about it unless you need to throw it down a cable. A typical case is RS-422 transmitters and receivers, carrying SPI data over twisted pair cable to peripheral boards. Or LVDS for high speed signals. This can be load or source-load terminated, and point-to-point or bus routed (respectively).If you can't minimize stub lengths, and need risetime sharper than source termination can afford, consider a different topology. Instead of routing SCK, MOSI and MISO to everything, route them one at a time (point to point), using a mux at the MCU, or separate UARTs. Or use a hybrid approach, grouping the devices into neighboring sets, so that the stub length per group is small enough.HTHTim

author: jnz
author_rank: Frequent Contributor
timestamp: May 02, 2016, 04:44:22 pm
content: Quote from: Scrts on April 29, 2016, 06:19:43 pmJust to be specific, I need a pullup because 3 of my 4 devices are incapable of pulling up themselves. I don't know why. My one Freescale part works fine, but maybe when used in conjunction with three ON Semi parts, they require a pullup (currently 2.2k) in order to bring the MISO line high.