Is there practical advantages using a tri-state buffer VS and gate ? [FIXED] - Page 1
Forum section: electronics / beginners

author: tigrou
author_rank: Regular Contributor
timestamp: April 23, 2020, 05:23:50 pm
content: I'm currently learning abouttri-state buffersand their use to connect several devices to the same bus.Unlike other devices on that picture, "Device B" receive data from the bus but cannot output data.Is there any advantages in using a tristate buffer to achieve this instead of an AND gate ?AFAIK both the AND gate and tri-state can be implemented using 4 transistors with CMOS.Using the AND, when control line is not enabled, all pins of Device B will be put to low (logical 0)While with tri-state, those pins will be neither connected to low or high but rather in a Z-state.

author: Gyro
author_rank: Super Contributor
timestamp: April 23, 2020, 05:48:05 pm
content: AND gates (and others of course) always output a logic level, they either drive the output high or drive it low.If you just gated each output onto the bus using AND gates, each logic high bit that the enabled device was trying to output would be counteracted by all the the other AND gate outputs still driving the bus to logic low. It wouldn't manage to do this.With Tri-state buffers, the non-enabled outputs are high impedance, effectivelydisconnectedfrom the bus, allowing the enabled device to set the bus to the correct logic levels.P.S. I thnk I have misunderstood you - if your device B only has logic inputs then it doesn't actually need an enable or tri-state buffer at all. They are only needed for Output or Bidirectional signals onto the bus. It really depends what logic your Device B contains, and how it handles the interval between output devices being enabled. AND gates would provide fixed logic levels into your Device B logic whereas a Tristate buffer would give it floating signal levels instead.

author: jmelson
author_rank: Super Contributor
timestamp: April 23, 2020, 06:24:06 pm
content: Quote from: tigrou on April 23, 2020, 05:23:50 pmWith the tri-state buffer, you must make sure that one and ONLY ONE buffer is driving a particular line (bus).If more than one is driving to different logic levels, there will be a lot of current flowing along the bus, and when oneof the drivers turns off, there will be an inductive spike that can foul up other logic.Some logic families have open-collector or open-emitter drivers that can allow wire-and or wire-or logic functionsto be performed. All of this is pretty old-school, now.Jon

author: Gyro
author_rank: Super Contributor
timestamp: April 23, 2020, 06:33:40 pm
content: P.P.S. You are describing a rather unusual situation. In an implementation with three tristate outputs going into one input (Device B), then it would normally be the logic in Device B that would be controlling the output enables of the three other devices (not a separate address decoder).

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 23, 2020, 06:42:43 pm
content: It seems unusual, to me, that Device B is driven with tristate buffers. When the buffers are tristated, the inputs to Device B float. This is normally a bad thing for CMOS. Of course, we don't know what is in Device B. So, I would say that NAND gates would be the better choice.

author: tigrou
author_rank: Regular Contributor
timestamp: April 23, 2020, 07:05:46 pm
content: Quote from: Gyro on April 23, 2020, 05:48:05 pmYou are right about that. I was going to write a post about this for clarification but you were faster. To be honest, my OP could be more precise/clear.Thanks all for replies

author: Neomys Sapiens
author_rank: Super Contributor
timestamp: April 23, 2020, 07:18:36 pm
content: As this is an example and not a real device, it shows a momentary situation. In reality, each of those devices would have I/O buffers which are selected depending on their status.Disabling an input buffer means that the input buffer draws less current and, depending on the chip, loads the bus less than an active input buffer.Disabling an output buffer means that the buffer goes high-Z and does not influence the line, thereby making it possible at all to have multiple buffers on a bus. The other possibility is to have different drive impedances for H and L, so that one driver could overcome the non-dominant signal output of the others.But this places limitations on the bus and can lead to many problems. It is more common in serial buses, as doing so for 1 line is more practicable and less transient-prone.Also, the exemplary nature of the material might have omitted parts, because they are not what the author wants to explain. This refers to the comment about the floating inputs. If you asked, a designer would have satd that there would of course been pull-ups or pull-downs or that one driver must be active.

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 23, 2020, 07:42:54 pm
content: Quote from: Neomys Sapiens on April 23, 2020, 07:18:36 pmOh, I did not follow the link to the source of the figure to see that this was not a real circuit. The author does talk about transferring data to Device B but gives no justification for using a tristate buffer. Unless Device B inputs are part of a bus inside of Device B, it makes no sense to me.

author: David Hess
author_rank: Super Contributor
timestamp: April 24, 2020, 08:39:53 pm
content: No, there is no reason a gate cannot be used in place of a tri-state buffer if it is only receiving and never driving a shared bus.