Issue with I2C Master Read on SAMD20Xplained Pro - Page 1
Forum section: electronics / general

author: tfranco_apexar
author_rank: Contributor
timestamp: March 27, 2018, 03:37:31 pm
content: Perhaps someone has faced this issue but I have a SAMD20Xplained an am trying to use the Atmel START I2C sync master driver to test some I2C temperature sensors but there seems to an error in the read sequence. Rather than the 9 cycles per frame, the first data frame has only 8 cycles and then there seems to be an extra cycle after the final nack and before the stop bit but that might just be its way of avoiding a start condition.I'm using a TMP007 in the images. (I'm not attaching the images for the 2 Wr frames as they seem fine, they show a slight delay between frames that the first data frame doesn't)0x40 is the device Address, 00 the command and there should be 2By of data.I've also tried using the older drivers from ASF3.something but I get the same odd behavior. (I've attached some of the files)Main from ATMEL START:Code:#include <atmel_start.h>#define DATA_LENGTH 2#define SLAVE_ADDRESS 0x40int main(void){static uint8_t write_buffer = {0xAE};static uint8_t read_buffer = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05};volatile uint8_t read_result=0;struct io_descriptor *I2C_0_io;/* Initializes MCU, drivers and middleware */atmel_start_init();i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);i2c_m_sync_enable(&I2C_0);i2c_m_sync_set_slaveaddr(&I2C_0, SLAVE_ADDRESS, I2C_M_SEVEN);read_result=i2c_m_sync_cmd_read(&I2C_0,0x00,read_buffer,DATA_LENGTH);while (true){};}

author: tfranco_apexar
author_rank: Contributor
timestamp: March 27, 2018, 06:22:52 pm
content: It might have to do with the CTRLA.SCLSM bit that's mentioned here:http://ww1.microchip.com/downloads/en/DeviceDoc/60001504B.pdfbut not listed in the CTRLA register so I have no idea how to change it.

author: ataradov
author_rank: Super Contributor
timestamp: March 27, 2018, 09:57:52 pm
content: SAM D20 does not have CTRLA.SCLSM, that's just a downside of generic documentation.There seem to be clock stretching happening, but it is normal. I may be missing something, images are really small and hard to read. Can you mark up what exactly you think is wrong on them?

author: tfranco_apexar
author_rank: Contributor
timestamp: March 28, 2018, 12:30:36 pm
content: I'd expect clock stretching before the data frame not before the acknowledge, especially when the master is the one doing the ACK. Stretching should happen before the data frame as the slave holds the line until the data is ready not before the master's acknowledge.During WR the stretch is between frames not in the middle of one. I doubt this is just clock stretching at an odd moment, as much as that is the apparent answer to every I2C question, I don't see why the master would hold the clock before giving an ack when I'm not validating the data and the slave wouldn't hold the clock when doing the measurement.What I think is wrong is the second frame in the first picture. I.e. clock cycles 1-9 are ok, 10-18 are abnormal.ThanksIf none in the family have that control bit, how can I know which paradigm they operate with? and really... why even list it in the documentation...Maybe you're right and it's just the SCLSM=0 thing...

author: ataradov
author_rank: Super Contributor
timestamp: March 28, 2018, 05:37:12 pm
content: Quote from: tfranco_apexar on March 28, 2018, 12:30:36 pmIt is very hard to tell what is going on without seeing the whole transaction. Is there any way you can capture it on a logic analyzer?I know this does not help, but I2C issues like this are very hard to debug. And tiny pictures with no sharp edges and protocol decode make it much harder.Quote from: tfranco_apexar on March 28, 2018, 12:30:36 pmD21 has this bit. In D20 it is always 0.

author: tfranco_apexar
author_rank: Contributor
timestamp: March 28, 2018, 05:38:44 pm
content: Then it must be that.Thanks.PS: Sorry but that's the best I could capture with what I had at hand and found them easy enough to read. I am waiting on a replacement Logic 8 Pro from Salae.