How does audio ADC PCM1808 in slave mode know what rate to sample the input at? - Page 1
Forum section: electronics / general

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: June 08, 2015, 12:38:35 pm
content: The datasheet of PCM1808 contains table 1 found herehttp://www.ti.com.cn/cn/lit/ds/sles177a/sles177a.pdfon page 11. It lists the possible sampling rates as 8, 16, 32, 44.1, 48, 64, 88.2, 96 KHz. It then lists the master clock values required for these different sampling rates. If we look at it e.g 16.384MHz master clock can give 32KHz sampling frequency (512 fs) or 64KHz sampling frequency (256 fs). It then says that "The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS in slave mode" but it is not clear how.I have the following questions:Precisely what determines the sampling rate of the PCM1808 in slave mode? Why are there only such discrete values as 8, 16, 32, 44.1, 48, 64, 88.2, 96 KHz?If I connect a 16.384MHz crystal as master clock source for the PIC microcontroller as the master and PCM1808 as the slave, how will the PCM1808 know what rate to sample the input signal i.e 32KHz or 64KHz as both have 16.384MHz value in their respective row?When does the PCM1808 actually sample an input signal, is it when the LRCK is asserted low or is sampling the input signal contiously? i.e if I read the ADC at time T, which sample in time of the input signal am I reading?At what rate can one read the data from the ADC? e.g if sampling rate is 44KHz, does the PIC microcontroller being the master device need to leave everything else and just read the ADC at this rate? Can the ADC use timer interrupts for this purpose?

author: Andy Watson
author_rank: Super Contributor
timestamp: June 08, 2015, 01:00:00 pm
content: Quote from: matrixofdynamism on June 08, 2015, 12:38:35 pmPage 18 gives details of the synchronisation. LRCK and BCK must be within certain limits of the system clock - I guess the chip is monitoring these signals to determine the required sampling rate. It appears that in slave mode, your PIC will have to generate these signals.

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: June 08, 2015, 03:11:22 pm
content: At what rate will the PIC need to generate these signals? Also, what if the PIC is not going to read the ADC data all the time, will the ADC stop working as it will not recieve continuous LRCK and BCK signals?

author: Bassman59
author_rank: Super Contributor
timestamp: June 08, 2015, 04:31:35 pm
content: Quote from: matrixofdynamism on June 08, 2015, 03:11:22 pmIf you want 48 kHz sampling, you need to provide a 48 kHz LRCLK and a 64 * fs BCLK (because I2S always shifts 64 bits in a frame) so BCLK must be 3.072 MHz.QuoteI have no idea. Given that there is some sort of sample-rate detection circuitry in the part, there might be some kind of startup delay between when the clocks start and when it starts to output valid sample data.But why would you want to start and stop the clocks? If you don't want to read the ADC all the time, ignore the data.

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: June 09, 2015, 03:10:19 pm
content: Is it better to use the PCM1808 in master mode or slave mode i.e which is more convinient?What I understand from pg 18 of the datasheet is that if I do not keep reading the ADC by sending in BCK, the device will go out of sync and DOUT will goto 0. Then I will have to somehow bring it back to sync and read it. This looks like a problem.

author: Rick60
author_rank: Contributor
timestamp: June 10, 2015, 12:58:09 pm
content: The PCM1808 is an audio sampler , optimized to run at sample rates of 44.1Khz for CD 48Khz for DAT etc. so the figures quoted are needed if you want to create an audio file that can be played by windoze etc .if your app doesn't require that rate you can run it at any rate you like I quess , the important thing is the relationship between SCLK,BCLK,LRCLK and Dout ,as defined in the I2S standardif the PIC doesn't have an I2S port it will be difficult to do in software,for any sample rate fs , bclk = 64*fs ,sclk= 256fs , LRCLK =fsif you use master mode the chip will from sclk generate LRCLK,BCLK,DOUT for you but the software will need to sample LRCLK drop , then bit shift 32bit in sync with bclk wait LRCLK rise etc , so at 16.384Mhz , you get fs= 64Khz , bclk= 4.096Mhz have fun in software with that , or use a divided clock out pinor use an spi deviceif you need audio rates you will need a chip with a PLL to generate sclk from your clock , I used chips like wm8805 for spdif output , but that can from 12Mhz generate 12.288Mhz etc

author: diyaudio
author_rank: Frequent Contributor
timestamp: June 14, 2015, 09:30:49 am
content: Quote from: matrixofdynamism on June 08, 2015, 12:38:35 pmI'm busy with something similar however I'm using a STM32F4 Discovery Board, What PIC are you using?QuoteFigure 21. Audio Data Format (LRCK and BCK Work as Inputs) See datasheetQuoteThese figures are the sampling frequencies, I assume you don't understand Nyquist theorem and Shannon's theorem?QuoteThe Sampler will lock to the input master frequency and produce the calculated fs (sampling frequency)QuoteSee Figure 22. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs) The timing slots reveal this relationship, as you can see, depending on which of the two channels you want to read you use the LRCK High/Low to obtain the ether the left or right ADC acquisition, this is used as a frame sync for L/R (stereo).Note there are two data-formats used: You using a PIC and ive never seen I2S peripherals on them, so you limited to using Left-justified, 24-bit.