LVDS input on spartan6? - Page 1
Forum section: electronics / general

author: awallin
author_rank: Frequent Contributor
timestamp: November 20, 2014, 05:43:30 pm
content: Hi all,I want to prototype a counter/timer thingy and have some fast ADCMP604's for the inputs.They produce an LVDS output that I want to connect via a 'wing' to a PapilioPro/Pipistrello FPGA.http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdfHow should I choose the pair of pins on the FPGA for my LVDS signal?Does the LDVS pair need to be something like: LXXP / LXXN, for example will this work on the Pipistrello?LVDS pos -> WingA_1 -> IO_L51P_M1DQ12_1LVDS neg -> WingB_14 -> IO_L51N_M1DQ13_1or can any pair of FPGA pins make a differential pair? and how is that defined as one logic signal in a UCF file?thanks,Anders

author: hamster_nz
author_rank: Super Contributor
timestamp: November 20, 2014, 06:00:50 pm
content: Hi,You want to look for a pair of pins that are part of differential input that are close together on the wing header.In your constraints file you do this (this is on the Papilio Pro):Code:NET test_signal_p LOC = "P51" | IOSTANDARD = LVDS_33;NET test_signal_n LOC = "P50" | IOSTANDARD = LVDS_33;And then in you HDL you use a IBUFDS to convert the differential signals into the single ended signal used in the design:Code:library UNISIM;use UNISIM.VComponents.all;...-- Input bufferi_IBUFDS : IBUFDSgeneric map (DIFF_TERM => FALSE,IBUF_LOW_PWR => TRUE,IOSTANDARD => "DEFAULT")port map (O => test_signal,I => test_signal_p,IB => test_signal_n);Here are the four pairs I used for HDMI input (I know that it isn't the same as LVDS, but the pin locations are what you need....). Oh and due to PCB layout constraints some of the pairs are flipped around (with the _p connected to a N pin, and the _n connected to the P pin) - it would pay to cross-reference them with the datasheet - but here are four pairs that I can vouch for!Code:NET "hdmi_c2_p" LOC="P57";NET "hdmi_c2_n" LOC="P58";NET "hdmi_c1_p" LOC="P55";NET "hdmi_c1_n" LOC="P56";NET "hdmi_c0_p" LOC="P62";NET "hdmi_c0_n" LOC="P61";Code:

author: awallin
author_rank: Frequent Contributor
timestamp: November 20, 2014, 06:44:02 pm
content: Thanks for the great reply!As my board connects to the wing-connector, I can put a terminating 100R resistor across the LVDS pair there - or alternatively use the internal termination of the FPGA? Any opinions on that?This is roughly what I have, based on the input of a digital-IO board by CERN(ohwr.org).VREF would come from a 3V voltage reference.

author: hamster_nz
author_rank: Super Contributor
timestamp: November 20, 2014, 11:40:42 pm
content: You can do internal termination.... with a DIFF_TERM = TRUE constraint:See the image at the top of page 15 :http://www.xilinx.com/support/documentation/user_guides/ug381.pdf

author: langwadt
author_rank: Super Contributor
timestamp: November 20, 2014, 11:52:29 pm
content: Quote from: awallin on November 20, 2014, 05:43:30 pmyou have to use the pairs LXXP / LXXNdepending on your input levels you might be able to use the LVDS input directly, an LVDS input is a fast comparatorI alway instantiate LVDS input directly, i.e.IBUFDS #(.DIFF_TERM("TRUE")) ina (.O (a), .I (a_p), .IB (a_n));

author: Bassman59
author_rank: Super Contributor
timestamp: November 21, 2014, 04:50:41 pm
content: Quote from: langwadt on November 20, 2014, 11:52:29 pmTo use LVDS or other differential I/O standards, you have to instantiate the proper buffer in the sourcecodeand you have to choose the proper IOSTANDARD in the UCF.