Teardown - IC Amplifier - Page 1
Forum section: electronics / general

author: serik5000
author_rank: Contributor
timestamp: June 29, 2013, 07:46:38 pm
content: Hello guys! I got my hands on one of the old ceramic hybrid IC modules from a Tek scope and decided it would be fun to figure out how it works and to see if it is a variable gain Amp. The heart of it is a custom ASIC amplifier which was very easy to decap by popping ceramic cover off.Underneath is what appears to be 4 nearly identical circuits, so I tried to imaged only one of them due-to lack of proper imaging equipment. I assume it is a BICMOS IC.I am very far from being knowledgeable in the area of solid state devices and how they are built, and this is my first time popping an IC open, so I will definitely need some help identifying individual transistors and their types. Here is what I see so far:- 12 large stadium shaped structures which might be JFETs. Structure has 1 center leg, circular leg, 2 half circles and 1 rectangular leg on 1 side only.- 6 structures which might be RF NPNs (C shaped leg inside of 3 shaped leg, rectangular legs on top and bottom)- 1 more type of transistor "-" leg inside of C shaped leg and larger rectangular leg on the bottom- the last type of transistor NPN or FET (square middle leg, thin rectangular leg right next te it, larger rectangular leg on the other side)- lots of similar looking parts of different size(rectangular or square black middle with blue color on top and bottom) Could be caps?- 2 layers of metal interconnectWhat I found interesting, lots of components on the die seem to be not used/have no interconnect. Also some bond wire pads are not connected either. Does it mean they use same die for different applications by simply changing interconnect layer? Or am I missing something?Any help in trying to figure out how this thing works is greatly appreciated!

author: w2aew
author_rank: Super Contributor
timestamp: July 01, 2013, 01:05:04 am
content: I might be able to shed a little light on this.What you are looking at is analog semi-custom array. More on this in a bit, first a little background...Tektronix began producing their own custom integrated circuits in their own bipolar fab starting about 1967. The continued the development of their own semiconductor process development and semi- and full-custom IC throughout the 70s and 80s, and into the 90s. In about 1986 or so, they starting offering semi-custom and full-custom IC fabrication services to outside customers as well as continuing the use internally.In the late 80's, I used their fab services for several semi-custom and full-custom IC designs. The semi-custom designs were analog arrays. These were standard, pre-fabricated chips that were completed up to, but not including, the metal interconnect between the passive and active devices. The arrays consisted of a variety of transistors, resistors and capacitors arranged in a "tile". These tiles were then replicated n-number of times, depending on the size of the chip. The designer then used this "kit" of parts to design their circuits by defining the interconnection metalization layers. Tek offered a several different size "quickchips" over the years, which included new and revised semiconductor processes as time went on.Some example datasheets for the quickchip products that I was able to find are:http://pdf.dzsc.com/2008717/200807171411426230.pdfhttp://datasheet.seekic.com/PdfFile/QUI/QUICKCHIP7.pdfTektronix sold the Integrated Circuit Operation (ICO) to Maxim in 1994. Maxim continued to offer the semi- and full-custom foundry service into the 2000's.So, the chip you are looking at is clearly one of these analog array chips. These were often used for fast turn-around of custom integrated circuits. The designer simply had to define two metal layers, a via layer, and possibly a trimmable thin-film resistor layer. The pre-fab'd wafers could quickly be turned into working chips by finalizing these last few process steps. So, the "identical chips" pattern you see on the surface of the chip is really the "tile" layout.The devices you identified as NPN transistors are correct. Some are connected up, some are not. There are different sizes available. There are a lot of unconnected devices in the array.I was only familiar with a few of the Tektronix ICO processes, and nearly all of them were bipolar only. Most were "conventional" - meaning they had fast NPNs, and slow lateral PNP devices, no FETs. There were a few complementary processes which included fast PNP devices. There was also at least one SiGe bipolar process, and there may have been BiCMOS, but I don't know for sure. The only ones I did any design work in were the conventional bipolar processes, which used NPNs that looked like those in your photos. They also included both vertical/substrate PNP devices and slow lateral PNP devices which were mainly useful only as current sources/mirrors. These devices looked similar to what you have labeled as JFETs, but it's been 25 years since I looked at them, so I can't be too sure.

author: serik5000
author_rank: Contributor
timestamp: July 01, 2013, 04:11:07 am
content: Wow, that was super helpful! Did a quick search on quickchip and Bingo! Quickchip 6 is what we are looking here at:http://datasheet.seekic.com/PdfFile/QUI/QUICKCHIP6.pdfIt exactly matched the one I have!It does have 12 JFETS per tile, large NPNs(around the edges), guarded Schottky (around the edges) which I identified as ESD protectors, small and medium NPN, as well as PNPs and unguarded Schottkies.My question might be silly, but now, when I know each device type, how do I assign gates to pads?For small NPN I believe it is "C BEB"For medium NPN would it be "C BEBEB"? Medium is the one I called RF NPN.For the diodes, anode is the larger pad, correct?And for JFETs I don't know where to start as they look nothing like what you would expect a FET to look like.

author: w2aew
author_rank: Super Contributor
timestamp: July 01, 2013, 04:11:27 pm
content: Quote from: serik5000 on July 01, 2013, 04:11:07 amFor the NPN devices, your node assignment is correct. The larger devices have an additional collector contact, so the pattern is C-BEBEB-C. For the schottky diodes, the larger pad should be the anode. I don't have any physical design data for the P-channel JFETs, so you'll probably have to infer them from the general geometry and the circuit context.

author: serik5000
author_rank: Contributor
timestamp: July 01, 2013, 07:19:55 pm
content: Quote from: w2aew on July 01, 2013, 04:11:27 pmI found a few references to NPNs and it looks like C-BEB, C-BEBEB, and C-BEBEBEBEB-C are small, medium and large NPNs respectively.For JFET, I think it has to be a split drain version with Top and Back gates. What do you guys think about attached pin assignment? Makes sense to solid state experts?Now for lateral PNP, I am not that sure. Middle part should be emitter, but which one is base? Top slim line or a thicker one on the bottom?

author: w2aew
author_rank: Super Contributor
timestamp: July 01, 2013, 07:48:49 pm
content: Not sure about the PFETs. I think you might have the collector and base reversed on the lateral PNP. This is just a guess because the QC6 used a different process than the SH3 process I used on the QC2 designs I worked on, and the PNPs are laid out a little differently on that process.

author: free_electron
author_rank: Super Contributor
timestamp: July 01, 2013, 09:37:37 pm
content: Whoa . That brings back memories. Almost any small semifab in the 80's had these uncomitted arrays. AMI, Mietec , even LSI had those. At the same time we had the logic equivalents as well. Only spin the metal masks.Gone the way of the wind....

author: Smokey
author_rank: Super Contributor
timestamp: July 01, 2013, 10:02:00 pm
content: I'm really enjoying this thread. You guys are my new personal heros for the day.

author: serik5000
author_rank: Contributor
timestamp: July 02, 2013, 07:14:44 pm
content: Quote from: w2aew on July 01, 2013, 07:48:49 pmYou were right on the money, I had B/C reversed on PNPs. The narrow pad on top is collector and wider one is the base. Emitter is in the middle. Plugged the circuit in, what I thought was Out turned out to be Enable input. Makes sense as PNPs are too slow to drive output anyway.

author: serik5000
author_rank: Contributor
timestamp: July 03, 2013, 03:16:16 am
content: I noticed there are few single pads throughout the chip, all connected to each other. I encircled one of them with rectangle and called it "mystery termination" on the attached pic. I am 100% sure there is no resistors going to them. They are placed in some sort of a rectangular pattern at the same locations on every tile.Any ideas what would they be?

author: amyk
author_rank: Super Contributor
timestamp: July 03, 2013, 01:41:18 pm
content: Substrate?

author: w2aew
author_rank: Super Contributor
timestamp: July 03, 2013, 03:11:41 pm
content: Quote from: amyk on July 03, 2013, 01:41:18 pmamyk is right - likely substrate contacts.

author: free_electron
author_rank: Super Contributor
timestamp: July 03, 2013, 04:06:26 pm
content: It could be the well... Substrate contacts are typically a row of via's

author: serik5000
author_rank: Contributor
timestamp: July 03, 2013, 04:12:10 pm
content: Looks like they all go to V+, I read somewhere that epi layer should be connected to the most positive voltage, while substrate should go to most negative. That's what it probably is. Btw, die sits on a metal pad which is connected to V-.

author: w2aew
author_rank: Super Contributor
timestamp: July 03, 2013, 06:36:49 pm
content: Quote from: serik5000 on July 03, 2013, 04:12:10 pmYep, you're probably right. They are probably epi-tub connections.

author: serik5000
author_rank: Contributor
timestamp: July 12, 2013, 04:25:45 am
content: Found an interesting thing, those epi connection go to V+ on 3 tiles (X1, X10, and X100 preamps), while on the 4th tile (output buffer amp) they are connected to V-. Does it make any sense?

author: w2aew
author_rank: Super Contributor
timestamp: July 12, 2013, 02:31:33 pm
content: Quote from: serik5000 on July 12, 2013, 04:25:45 amHmmm - maybe they're using the Epi tub and it's devices as a large area ESD diode? :-)