Modern communication between components in a computer - Page 1
Forum section: electronics / general

author: nForce
author_rank: Frequent Contributor
timestamp: August 07, 2018, 09:18:09 am
content: Hello,I would like to know which are communication standards in a personal computer for communication between CPU and RAM and between CPU and video card and so on.For microcontrollers we use I2C, SPI and other. But do we use these also for a personal computer?

author: Berni
author_rank: Super Contributor
timestamp: August 07, 2018, 09:42:36 am
content: High speed has always been in the form of highly parallel buses in PCs. There used to be more verity of it in the old days, but all the modern stuff simply connects the DDR3 or DDR4 memory pins directly to the pins of the CPU since the memory controller is inside there for all modern chips, all the rest goes trough PCIe lanes.The other sorts of buses tend to all connect to the chipset IC (That connects back to the CPU over PCIe). From there on you might get things like normal PCI (That is essentially just a memory bus with address and data pins.), SATA, USB, PS2, Serial, LPT etc.. and even I2C. Even if the I2C bus might seam pretty low end its still heavily used in PCs today. Every RAM stick has a I2C EEPROM on it that the BIOS uses to identify what kind of memory it is and configure the memory controller correctly for it. Also all the little things like temperature sensors, fan rpm, fan speed control, voltage mesurement, RGB LEDs...etc are all sitting on I2C.Additionally I2C is even used outside as there are I2C pins on VGA, DVI and HDMI connectors that are used to identify what kind of display is connected and use set up the right resolution for it or to let windows populate that resolution selection dropdown menu with only resolutions that the display supports.

author: nForce
author_rank: Frequent Contributor
timestamp: August 07, 2018, 05:54:41 pm
content: You said for voltage measurements.How is a voltage measurement achieved on the motherboard of a personal computer? We need a tiny voltmeter on the motherboard.

author: tsman
author_rank: Frequent Contributor
timestamp: August 07, 2018, 06:06:39 pm
content: Quote from: nForce on August 07, 2018, 05:54:41 pmThere is no single standard for implementing voltage and temperature monitoring on PC motherboards. Some boards had a dedicated I2C sensor chip, some connected it to an onboard management controller and some just had it as part of a combined Super I/O chip that handles all the legacy stuff. The Super I/O chips hang off the LPC bus now but old ones were ISA. Look at the lm_sensors project.

author: asmi
author_rank: Super Contributor
timestamp: August 07, 2018, 06:37:05 pm
content: Every motherboard I've ever seen in last decade displays core voltage in BIOS (and most modern ones can display it even inside OS). So I'm not sure what's the point.

author: oPossum
author_rank: Super Contributor
timestamp: August 08, 2018, 01:55:28 am
content: Quote from: nForce on August 07, 2018, 09:18:09 amCurrently DDR4, previously DDR3, DDR2, DDR, SDRAM, EDO DRAM, FPM DRAM, DRAMQuoteCurrently PCI express, previously AGP, PCI, VLBUS, Microchannel, EISA, ISAQuoteSMBUS on motherboards is derived from IIC. It is used for memory identification, battery managment, temperature monitoring, voltage monitoring, and more.QSPI and previously SPI for BIOS Flash memory.

author: westfw
author_rank: Super Contributor
timestamp: August 08, 2018, 06:26:20 am
content: QuotePCIexpress is sort-of serial, isn't it? An x16 PCIe Video card has 16 parallel serial "lanes", but it's fundamental serial nature is what lets you easily use the xNN cards where NN varies, and permits things like Thunderbolt cables that send PCIe signally several meters. (Apparently, serial data behaves better over "transmission-line" like media, compared to highly parallel connections?)

author: Berni
author_rank: Super Contributor
timestamp: August 08, 2018, 07:18:10 am
content: Yes the PCIe lanes are individual serial lines and a 1x PCIe bus is a valid configuration. But what i meant with parallel is that the data is not sent over a single wire/pair, but over a large number of connections for the simple fact that more wires if faster. One PCIe x16 slot needs 33 differential pairs to work (16 TX, 16 RX, 1 clock) So in total that's 66 wiresThe reason that PCIe lanes are electrically treated as serial lines is to get around the problem of getting such a incredibly fast moving signal from A to B over a circuit board. This allows the lane to use differential signaling and for the PCB designer to route it as a differential pair across the board. This creates a very good high speed transmission line that does not push fast changing currents trough the ground layers. All of this is a big deal when the signals are moving at 8 GHz! At these speeds length matching is also very important, getting 16 pairs to precisely match would be very difficult and make the PCB much more expensive . But since PCIe treats each one as a serial link that is individually synchronized at the receive end means that they don't need to length match any of the pairs to each other. Once synchronized the bits are put back together.So PCIe is parallel bus made from serial pairs only as a trick to get the stubborn pixies in the wire to dance fast enough. For the same reason a lot of other interfaces used differential signaling. Some are truly serial like USB2.0, USB3.0, SATA and use only a single pair (Or separate pair for TX and RX), while others like HDMI, DVI, Displayport, Display LVDS take a similar approach to PCIe where chunks of data are sent over multiple parallel pairs and a separate clock signal is provided. It does kinda blur the line between serial and parallel a bit.The DDR memory bus does not use this trick and it makes designing PCBs for it a significant challenge. But since the bus is 64 bits wide for modern RAM DIMMs that would again be a massive pain in the ass to length match tightly enough. What is done instead is that RAM is actually used as 8 buses each 8bits wide. This confines the tight length matching to only the 8 lines + 1 control line. If you have dual channel memory then you have two of these 64bit sets of buses....yeah computers are getting very complicated these days in order to get around the speed bumps imposed by the laws of physics. No longer is a bus just some data and address lines.

author: nForce
author_rank: Frequent Contributor
timestamp: August 08, 2018, 01:46:32 pm
content: Quote from: tsman on August 07, 2018, 06:06:39 pmSo is then for example implemented in this way:We have multiple voltmeters and temperature sensors on a motherboard. Each has a dedicated I2C sensor chip, which is connected to the CPU which reads the data and displays in a BIOS?

author: NorthGuy
author_rank: Super Contributor
timestamp: August 08, 2018, 01:50:00 pm
content: Quote from: Berni on August 08, 2018, 07:18:10 amI think it's simply because each byte group goes to its own memory chip (or two). No-one worries about PCB designers

author: tsman
author_rank: Frequent Contributor
timestamp: August 08, 2018, 03:29:10 pm
content: Quote from: nForce on August 08, 2018, 01:46:32 pmIt'll be one chip that has multiple sensor inputs to monitor fan speed, voltage and temperature. An example of an old ISA/I2C attached one would be the Winbond W83782D which was popular in old PC motherboards. A newerLPC busattached integrated chip would be the ITE IT8720F which also handles legacy peripherals like serial ports, parallel port, floppy drives and PS/2 keyboard/mouse.The BIOS/UEFI firmware would have routines to talk the specific onboard sensor monitoring chip used.

author: legacy
author_rank: Super Contributor
timestamp: August 08, 2018, 03:49:25 pm
content: Quote from: Berni on August 08, 2018, 07:18:10 amexcellent review

author: Berni
author_rank: Super Contributor
timestamp: August 08, 2018, 06:41:00 pm
content: Well not all RAM chips are 8 bit. They do also commonly come in 4 or 16 bit bus sizes. If you look at DDR memory DIMMs you can find a varying number of chips on them. Some are populated with chips on both sides, some on one side and some might use only a 4 chips on one side. These groups of data pins are called DQS groups (After the data strobe pin) and there are also FPGAs that support DQS groups containing 4, 8 and 16 data pins. But the DIMMs in PCs are standardized to 8 pins, yet two 4 bit chips can be joined together on the same group or a 16bit chip often is available with two DQS pins.For DDR3 and later its also standard for the memory controller to have a special timing tuning mode where the DDR chips loop back the DQS signal so that the memory controller can adjust the phase shift of it until it finds one with the best timing margin. This improves timing accuracy and reduces the electrical noise due to not all data lines moving in sync to pump massive current transients into the ground lines. DDR3 also made PCB design easier by allowing the common address and control lines to be routed flyby style across the module from one edge to the other rather than needing balanced T junctions. This means that chips on one side have a lower propagation delay then the other side, but the memory controller is designed to compensate by having the timings move accordingly to compensate.I agree that sometimes digital chip designers are pure evil with there pinouts when it comes time to route a PCB, but at these speeds they have to start being at least a little nice to them or the stuff would never run at these speeds reliably.Oh and yes a lot of people think that BIOS is only there to load the OS into memory and then just disappears once you see the boot screen. But the OS continues to talk to it all the time and execute code from it in order to use a lot of the hardware, or even to power down the PC once its done shutting down.

author: asmi
author_rank: Super Contributor
timestamp: August 08, 2018, 06:45:11 pm
content: Quote from: NorthGuy on August 08, 2018, 01:50:00 pmNo. Some DIMM modules use x16 chips and so have two byte groups, but still each byte has its own data strobe (DQS). This is done purely for layout reasons so that each groups can be routed independently, and write leveling will take care of different propagation delays across byte groups.

author: NorthGuy
author_rank: Super Contributor
timestamp: August 08, 2018, 11:40:41 pm
content: Quote from: asmi on August 08, 2018, 06:45:11 pmThink about it. If you route each byte to a different chip then they've got to be routed independently.The whole idea of the fly-by topology is to allow the clock along with control and address lines to be routed together, passing by every chip and then terminated once at the end. Since the data lines are still parallel (each chip has to get its own data lines because they all work at the same time), such topology dis-synchronizes the clock and the data - thus you need write leveling and all these things you're talking about. The idea of the topology is not to run individual data groups to the individual chips (they got to be individual anyway, and were individual in DDR2 too), but quite opposite. They wanted a good way of sharing common clock/address/control lines between all the memory chips.