EMI Problem driving a solenoid PWM - Page 1
Forum section: electronics / beginners

author: Inkblack
author_rank: Newbie
timestamp: January 13, 2024, 12:49:39 pm
content: Hi everyone,I'm dealing with an EMI issue. Since I want my product to achieve CISPR 11 limits of conducted emission test (both avarage and quasipeak) I'm doing some test of it.I'm driving a solenoid with a mosfet (from here no problem, I'm under limits of normative seen by a receiver and using a LISN).When I put my pcb inside the metallic chassis of the soleoid and I repeat the test I'm out of the limits.What I am supposing is that the metallic chassis has a very high capacitive coupling vs earth and when the solenoid switch all the chassis is "switching" this obviously increase the noise seen by the receiver (since I'm "catching" L1-PE noise for normative).One of the solution that I tested to reduce a lot the EMI is to put a little capacitor between my GND of the board and the metallic chassis. Like that I reclose all the noise inside the chassis and the coupling with the earth is now my "GND" that has little noise.More information about the circuit:I'm working with 230VAC with PWM of 10kHz (I can choose from 10 to 7kHz) and I check that duty cycle is everytime between 2-3%.https://circuitdigest.com/fullimage?i=circuitdiagram/Solenoid-Driver-Circuit-Diagram.pngSupposing that duty cycle period I have that the "pulse" of t-on is about 3us and in frequency more or less (1/t-on) 350kHz.Supposing that for question of space I cannot use the solution that I found, My problem is that I'm out of the limits from 300kHz to 1MHz more or less. I suppose that they are the frequency of the pulses of the duty cycle and its harmonics.I'm trying my best to slow down the dv/dt of the switching working on the gate of the power mosfet that I'm using but with very low results. The good results are when I put a very big resistor (1k to 2k) on the gate of the mosfet but like that I see that the voltage gate is not reaching the gate driver voltage but remain on the Miller plateau (I dont like this solution).Do you have any suggestion to reduce this dv/dt on that frequency range?Should I have to work on gate of the mosfet or on other parts?Thanks in advance!

author: selcuk
author_rank: Frequent Contributor
timestamp: January 13, 2024, 01:10:21 pm
content: Can you connect your circuit ground to the metallic enclosure with a very low impedance connection?Does the 10k resistor series with the gate on the schematic works fine with PWM?

author: Inkblack
author_rank: Newbie
timestamp: January 13, 2024, 01:46:11 pm
content: No unfortunately I cannot because one of other tests of IEC is dielectric. So I have to withstand 2kV test between metallic chassis and pins of the connector of the mains. That is why I found to put capacitor (maybe Y2 safety 5kV impulse voltage Kemet) between gnd and earth.

author: selcuk
author_rank: Frequent Contributor
timestamp: January 13, 2024, 01:56:29 pm
content: I'm not an EMC professional so I don't know about that test. But is this a double insulated product? Aren't you going to connect PE to the chassis eventually? For the surge test on power pins, you can use varistors to pass.

author: Terry Bites
author_rank: Super Contributor
timestamp: January 13, 2024, 04:35:35 pm
content: Have you tried limiting the slew rate of the gate drive?

author: Inkblack
author_rank: Newbie
timestamp: January 13, 2024, 05:26:09 pm
content: In which sense? I'm trying a combination of resistor and capacitor added on the gate of the mosfet to reduce the rise time of the PWM but honestly I think the issue is that the duty cycle of 2% create a fundamental harmonic of 300kHz that I cannot reduce by working on it :/