translate the schmitt trigger level from datasheet - Page 1
Forum section: electronics / projects

author: ghoetic
author_rank: Contributor
timestamp: April 09, 2024, 08:21:55 pm
content: I am going to use a 4 channel NAND with schmitt inputs, 2-6v supply. In the datasheet i can find the min,max and typical switching thresholds for positive and negative going, but only specified for 2, 4.5 and 6v.I am planning to use 3.3v so how would i go about finding the typical threshold for that? if it even matters.What i have done so far is taken the typical values for positve and negative, 3 points (x,y) and regressed a two linear lines, putting in my value of 3.3v and taking the mean. I got a Vthreshold (1.485V) and a Vhystersis (0.393) which i simulated in LTspice for a schmitt trigger.My end goals is to get roughly 1 uS of delay between inner and outer signal with my logic, but i have to validate the R and C values according to the schmitt inputs.Is this the correct way? feels like there would be an easier way to do this?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 09, 2024, 09:52:44 pm
content: Quote from: ghoetic on April 09, 2024, 08:21:55 pmIf the data avoids your operating point, you have little choice but to interpolate.If doing RC delays you should verify by measurefrom the same vendoryou will use in production, and ideally from the same date code/reel of production parts.That should reduce your errors into the realm of device variations and temperature effects, with a usually slight negative tempco on the threshold.Quote from: ghoetic on April 09, 2024, 08:21:55 pmHow much it matters, depends on your values of 'roughly'Using a data sheet typicals should land you in the correct ballpark.Measurements help verify where you landed inside that ballpark.

author: Benta
author_rank: Super Contributor
timestamp: April 09, 2024, 09:54:59 pm
content: Your approach is fine and the way to do it.But if you expect any kind of precision... well, the data sheet speaks for itself.Those simple gates are not made for timing, but for squaring up "wobbly" signals.And where on earth did you get those weird symbols for a simple NAND gate? Must be a first.

author: Benta
author_rank: Super Contributor
timestamp: April 09, 2024, 09:57:26 pm
content: Quote from: PCB.Wiz on April 09, 2024, 09:52:44 pmSo, as soon as the first lot has been used and you order new ones, the design will have to be reworked?

author: ghoetic
author_rank: Contributor
timestamp: April 09, 2024, 10:09:27 pm
content: Quote from: Benta on April 09, 2024, 09:54:59 pmAh yes, in my simulation i test the function that i am sequencing with NAND gates, a AND and an OR. That i why.+- 100us is fine i guess.

author: Benta
author_rank: Super Contributor
timestamp: April 09, 2024, 10:32:24 pm
content: Quote from: ghoetic on April 09, 2024, 10:09:27 pmYou need 1 us delay, but now +/-100 us is fine? I'm lost now...

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 09, 2024, 10:33:37 pm
content: Quote from: Benta on April 09, 2024, 09:57:26 pmThat depends on how much you are pushing thingsThe idea is to centre yourself on the error bands, so that you can best tolerate variations.We've found same-vendor variations are usually very good, (single digit %) even over time as they have good process controls.That's in the same ballpark as temperature variations.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 09, 2024, 10:36:49 pm
content: Quote from: ghoetic on April 09, 2024, 10:09:27 pmI think you means 100ns ?That's ~ 10%, so you should be ok.Roughly speaking, I'd expect to get within ~20% with a paper exercise and better than ~5% after measurements.You can decide if you want to specify a 1% NPO capacitor and 1% or better low ppm resistor.

author: ghoetic
author_rank: Contributor
timestamp: April 10, 2024, 05:41:01 am
content: Quote from: PCB.Wiz on April 09, 2024, 10:36:49 pmYes thanks, i replied i bed and goofed, 100ns is correct. So the last thing to do then is choose some good 0805 package R & C for easier adjust IRL if i have to.Just for clarity, what are my options if i want more precision in the design stage, other options beside schmitt?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: April 10, 2024, 06:55:53 am
content: Quote from: ghoetic on April 10, 2024, 05:41:01 amYou can look at monostables.The better ones have two differential comparators and voltage dividers, so their tempco is much better and they will spec a data sheet band of 5-10% spreads.eg the 4000 series HEF4538 has this design, and specs very good tempco, but will struggle down at 1us.The HC4538 also explicitly shows comparators, which some of the other designs leave as blocks.They all tend to get worse spreads at smaller times like 1us area, but again you could interpolate the curves like you already did.eg TI's SN74AHC123A defines 866ns for 5V/10k/50pF, and then curves expect that to be +3% at 3v3, so you could hope for a typical value of 892ns, so 11.2k centres you on ~1.0usThe single gate 1G123 are another option.Addit: because you are in the less-defined corner of monostable operation with 1us timing, another larger leap would be to look at small MCUsParts like SiLabs EFM8BB50 run 49MHz calibrated Osc, so you get 20ns jitter from the OSC sampling, and need it always on so you run at idle Icc on ~ 2.2mA, you save the external 1% Cap and 1% resistors per timing, and some very few lines of assembler would give you 1us (49 sysclocks) delays from interrupt-idle-exit.I doubt you need that level of precision for a dead-band power sequencer.