verilator width warnings - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: December 03, 2019, 05:38:28 am
content: Could anyone advise about the verilator width warnings below ?QuoteCode:module in_buf_load(clk, reset, buf_address); // generates DDR address for the AWS guy codelocalparam MAX_J = 10;localparam MAX_K = 10;localparam GIGA = (1 << 9); // 10^9localparam BITS_PER_BYTE = 8;localparam NUM_OF_BITS_IN_TWO_GIGABYTE = (GIGA << 1)*BITS_PER_BYTE;parameter BUFFER_WIDTH = 16;parameter DATA_WIDTH = 4*BUFFER_WIDTH; // ap_uint<64> *i_data which contains 4 different 16-bit data// 2 Gigabyte of data, each contiguous chunk of data is 64-bitparameter NUM_OF_DATA_ENTRIES = NUM_OF_BITS_IN_TWO_GIGABYTE/DATA_WIDTH;parameter N = 4; // number of input feature mapsparameter n = 1; // input feature map index (just to identify map)parameter Tn = 4; // number of tiles for input feature maps (divide and conquer due to resource limits)parameter r = 256; // FEATURE_SIZE_WIDTHparameter c = 256; // FEATURE_SIZE_HEIGHTparameter IDX_N_WIDTH = ($clog2(N*100));parameter IDX_R_WIDTH = ($clog2((r+MAX_J)*10));parameter IDX_K_WIDTH = ($clog2(c+MAX_K));parameter Tn_WIDTH = $clog2(Tn);parameter r_WIDTH = $clog2(r);input clk, reset;output [$clog2(NUM_OF_DATA_ENTRIES)-1:0] buf_address;//wire signed [DATA_WIDTH-1:0] local_i_buf [N-1:0][MAX_J-1:0][MAX_K-1:0];//assign local_i_buf = ;assign buf_address = idx_n + idx_r + idx_k;// used for generating address indexesreg [IDX_N_WIDTH-1:0] idx_n;reg [IDX_R_WIDTH-1:0] idx_r;reg [IDX_K_WIDTH-1:0] idx_k;reg [$clog2(N)-1:0] index_i;reg [$clog2(10)-1:0] index_j;reg [$clog2(10)-1:0] index_k;always @(posedge clk)beginif(reset) index_i <= n;else if(index_i < N) index_i <= index_i + Tn[0 +: Tn_WIDTH];endalways @(posedge clk)beginif(reset) idx_n <= n*100;else idx_n <= index_i * 100;endalways @(posedge clk)beginif(reset) index_j <= 0;else if(index_j < 10) index_j <= index_j + 1;endalways @(posedge clk)beginif(reset) idx_r <= (r + 0) * 10;else idx_r <= (r[0 +: r_WIDTH] + index_j) * 10;endalways @(posedge clk)beginif(reset) index_k <= 0;else if(index_k < 10) index_k <= index_k + 1;endalways @(posedge clk)beginif(reset) idx_k <= c + 0;else idx_k <= c + index_k;end`ifdef FORMALinitial assert(reset);reg first_clock_had_passed = 0;always @(posedge clk) first_clock_had_passed <= 1;always @(posedge clk) if(first_clock_had_passed) cover($past(reset) && buf_address != 0);`endifendmodule

author: BrianHG
author_rank: Super Contributor
timestamp: December 03, 2019, 06:29:40 am
content: have you tried designating the exact bits at each step forcing the matter?eg:Code:warning line:assign buf_address = idx_n + idx_r + idx_k;to:assign buf_address[$clog2(NUM_OF_DATA_ENTRIES)-1:0] = idx_n[IDX_N_WIDTH-1:0] + idx_r[IDX_R_WIDTH-1:0] + idx_k[IDX_K_WIDTH-1:0];similar on line 51:else if(index_i[$clog2(N)-1:0] < N[$clog2(N)-1:0]) index_i <= index_i + Tn[0 +: Tn_WIDTH];Though this one may cause problems as if 'N" has more bits than [$clog2(N)-1:0]. You may also try:else if(index_i[$clog2(N)-1:0] < N[2:0]) index_i <= index_i + Tn[0 +: Tn_WIDTH];Assuming N is never greater than 7, however, you compiler seems to be saying that [$clog2(N)-1:0] for index_i is only = to [1:0], ie 2 bits and N being =4 is 3 bits.When comparing different number of bits together, some compilers want you to be explicit knowing that the < 'LT' will always hold true.Since I'm not decoding this code, I can tell you some of these warnings are important like the one with the second one I highlighted. There is no way index_i can be > or = 'N' since it is only 2 bits while 'N=4' is 3 bits already...

author: promach
author_rank: Frequent Contributor
timestamp: December 03, 2019, 07:28:46 am
content: Code:assign buf_address[$clog2(NUM_OF_DATA_ENTRIES)-1:0] = idx_n[IDX_N_WIDTH-1:0] + idx_r[IDX_R_WIDTH-1:0] + idx_k[IDX_K_WIDTH-1:0];No, this does not help. Same exact error

author: BrianHG
author_rank: Super Contributor
timestamp: December 03, 2019, 07:37:35 am
content: Your compiler is telling you that the size of your 'buf_address[$clog2(NUM_OF_DATA_ENTRIES)-1:0]' on the left hand side of the '=' in it's number of bits is too small for the total sum of the equation on the right hand side. It needs to be larger in bits, or information is lost.

author: promach
author_rank: Frequent Contributor
timestamp: December 03, 2019, 07:44:00 am
content: Code:localparam GIGA = (1 << 119);I changed the buf_address bitwidth length, yet still width warnings

author: BrianHG
author_rank: Super Contributor
timestamp: December 03, 2019, 07:51:15 am
content: What is the value of ' $clog2(NUM_OF_DATA_ENTRIES)-1 ' ?

author: promach
author_rank: Frequent Contributor
timestamp: December 03, 2019, 08:00:59 am
content: Code:localparam GIGA = (1 << 9); // 10^9localparam BITS_PER_BYTE = 8;localparam NUM_OF_BITS_IN_TWO_GIGABYTE = (GIGA << 1)*BITS_PER_BYTE;parameter BUFFER_WIDTH = 16;parameter DATA_WIDTH = 4*BUFFER_WIDTH; // ap_uint<64> *i_data which contains 4 different 16-bit data// 2 Gigabyte of data, each contiguous chunk of data is 64-bitparameter NUM_OF_DATA_ENTRIES = NUM_OF_BITS_IN_TWO_GIGABYTE/DATA_WIDTH;

author: BrianHG
author_rank: Super Contributor
timestamp: December 03, 2019, 08:11:57 am
content: What is the value of ' $clog2(NUM_OF_DATA_ENTRIES)-1 ' ?Give me the actual number...$clog2(NUM_OF_DATA_ENTRIES)-1Solve the equation...