And the warning is gone ... Simple DivClk by N  - Page 1
Forum section: electronics / general

author: tchiwam
author_rank: Regular Contributor
timestamp: February 01, 2023, 01:31:07 pm
content: Oh well, you work late one night and you get warnings about bad coding practice, then come back during the morning and you get... no warnings anymore... Anyway...I am playing with a SP605 spartan-6, a christmas present ...Next step, cleaning up the trailing clk on reset to at least end on the neg edge of the i_clk... and look at the schematic of the implementation.For some reason, Vivado can upload the bit stream, openFPGALoader and impact can't see the board...Code:`timescale 1ns / 1psmodule TestDivRN;module divRN #(parameter c_SIZE = 16,parameter c_DELAY = 0) (input wire [c_SIZE-1:0] i_N,input wire i_reset,input wire i_clk,output reg o_clk);initial o_clk = 1'b0;reg [c_SIZE-1:0] r_count = c_DELAY;always @ (negedge i_clk or negedge i_reset) beginif (~i_reset) begino_clk <= 1'b0;r_count <= c_DELAY;end else beginif (r_count == 0) begino_clk <= ~o_clk;r_count <= i_N;end elser_count <= r_count - 1'b1;endendendmoduleCode:`timescale 1ns / 1psmodule TestDivRN;// Inputsreg [15:0] i_N;reg i_reset;reg i_clk;// Outputswire o_clk;// Instantiate the Unit Under Test (UUT)divRN # (.c_SIZE(2),.c_DELAY(2)) uut (.i_N(2'b1),.i_reset(i_reset),.i_clk(i_clk),.o_clk(o_clk));initial begin// Initialize Inputsi_reset = 0;i_clk = 0;#50i_reset = 1;#105i_reset = 0;#150i_reset = 1;#195i_reset = 0;#250i_reset = 1;// Add stimulus hereendalways #5 begini_clk <= ~i_clk;endendmodule

author: TomS_
author_rank: Frequent Contributor
timestamp: February 13, 2023, 10:24:22 am
content: Speaking generically, and I dont know if its the same cause, but I have experienced similar kinds of things over time in a variety of languages/tools.Sometimes you have to do a "clean build" all the way from scratch, which may be a different menu/menu bar option to the standard "build" which perhaps only rebuilds parts of the code.Perhaps you made a change to the code which fixed the error, but the standard "build" didnt actually rebuild that code, maybe because it only rebuilds the file you are currently looking at or something. So the next build doesnt actually incorporate that fix, but a "clean build" would because it will redo everything.Thats just what I see from time to time.

author: jmelson
author_rank: Super Contributor
timestamp: February 14, 2023, 04:54:15 pm
content: Quote from: TomS_ on February 13, 2023, 10:24:22 amYes, I have seen this a few times with Xilinx Ise tools, sometimes you get crazy results, save thw whole project, close Ise, reopen and load the .v files and than it starts working again. This doesn't happen too often.Jon

author: tchiwam
author_rank: Regular Contributor
timestamp: February 17, 2023, 12:56:30 pm
content: I will try to post a new I am wondering issue. Made it work but this assumes a rise time will always be late on a state change. Simulation looks good so far but I know that in 74xx land I'd shoot myself in the foot and get tiny fractional glitch on the clk line.Also if I do an async reset circuit, it insists on an inverted buffer on the clr line. I am trying to convince the end schematic to have 1 inverter to drive all the latches but the compiler is having none of it.

author: tchiwam
author_rank: Regular Contributor
timestamp: February 17, 2023, 05:37:07 pm
content: This is doing the right thing in simulation... But in reality I am worried about the always @o_done edge... Again no warnings...Code:// Burst B o_clk then wait for a reset with flip every N i_clkmodule divRNRB #(parameter c_SIZE = 16, // Size of the counters in bitsparameter c_DELAY = 0 // start after c_DELAY*i_clk) (input wire [c_SIZE-1:0] i_N, // N*i_clk count before o_clk flipinput wire [c_SIZE-1:0] i_B, // B*o_clk then stopinput wire i_reset, // async reset , o_clk does not end on a i_clk edgeinput wire i_clk, // Input clockoutput reg o_done, // True means ready to start again.output reg o_clk // Clock burst out);initial o_clk = 1'b0;initial o_done = 1'b0;reg [c_SIZE-1:0] r_clkcount = c_DELAY;reg [c_SIZE-1:0] r_burstcount;initial r_burstcount= i_B;// Count of i_clkalways @ (negedge i_clk or negedge i_reset or posedge o_done) beginif (~i_reset) begino_clk <= 1'b0;r_clkcount <= c_DELAY;end else begin // Reset low state hereif (o_done) begino_clk <= 1'b0;end else beginif (r_clkcount > 0) beginr_clkcount <= r_clkcount - 1'b1;end else begino_clk <= ~o_clk;r_clkcount <= i_N;endendendend// Count of o_clkalways @(posedge o_clk or negedge i_reset) beginif (~i_reset) begino_done <= 1'b0;r_burstcount <= i_B;end else beginif (o_clk) beginif ( r_burstcount > 0 ) beginr_burstcount <= r_burstcount - 1'b1;end else begino_done <= 1'b1;endendendendendmoduleCode:`timescale 1ns / 1psmodule TestdivRNRB;// Inputsreg i_reset;reg i_clk;// Outputswire o_done;wire o_clk;// Instantiate the Unit Under Test (UUT)divRNRB # (.c_DELAY(4))uut (.i_N(16'd2),.i_B(16'd10),.i_reset(i_reset),.i_clk(i_clk),.o_done(o_done),.o_clk(o_clk));initial begini_reset = 0;i_clk = 0;#50i_reset = 1;endalways #5 begini_clk <= ~i_clk;endendmoduleIs there a way not generating warnings and errors that will simplify this schematic ?The async reset is nice as the burst may be triggered every 1 second and having to wait >1second is not ideal.If I use (reset) instead of (~reset) the synthesis is not happy at all...

author: BrianHG
author_rank: Super Contributor
timestamp: March 25, 2023, 10:26:35 pm
content: I'm curious why you just didn't make a proper everything synchronous to 'negedge i_clk' ?I mean, FPGA hate internal software generated clocks instead of enables and your potential FMAX would go through the roof while eliminating all compiler timing errors, warnings, clock domain crossings, wasted logic routing, ect...