CCP - capture - pic uc - Page 1
Forum section: electronics / general

author: arul
author_rank: Regular Contributor
timestamp: May 09, 2019, 12:59:25 pm
content: Hi All,Right now, i measuring the pulse width and time period of given input signal using CCP capture method. I have doubt about choosing the system clock frequency.Because i selected the system frequency as 8MHz. That time I didn't measure the time period of input signal i.e 100kHz frequency (10 us - time period). But after I select the system frequency as 64 MHz , I measured the time period of 100kHz frequency of input signal.One more thing, the CCP capture method worked along with timer. The timer clock frequency is Fosc/4. If system frequency is 8MHz mean the timer clock frequency is 2MHz, , timer period is 500ns to 32.768ms. I measured the 10us period time of input signal within the timer period, but didn't get the measurement. Is it correct? Why am i unable to measure?But the system frequency is 64MHz, then timer period is 62.5ns to 4.096ms, I measured the input signal time period of 10us. This way i measured. How is it?Right now, my task is to measure the 1000us(1kHz), 2000us(500Hz) and 10us(100kHz) time period of input signal. But 1000us (1kHz) and 2000us (500Hz) time period of input signal are measured with both system clock frequency.But another thing, In 1000us period time, I varying the pulse width from 1us to upto max level, that time I increased the pulse width above 400us, it takes some delay to change the pulse width and also it happen in 2000us period time. What is the reason for delay higher pulse width?What is reason and relationship between system frequency and CCP capture mode???Please let me know...Advance in thanks...!

author: NorthGuy
author_rank: Super Contributor
timestamp: May 09, 2019, 04:50:59 pm
content: Hard to see what you're doing.Many things depend on the timing.If you use a single CCP module: Once the rising edge is captured, you must read out the value before it gets destroyed by the falling edge. Running your CPU faster gives you more chances to be quick enough.If you use two CCP modules (one for rising edge and one for falling edge): This gives you more chances to catch a narrow pulse, but still you must read the rising edge value before the next rising edge arrives and destroys it.

author: arul
author_rank: Regular Contributor
timestamp: May 10, 2019, 04:40:37 am
content: I am using two CCP modules, i.e one for rising edge and another one is falling edge.My problem is when i go to higher pulse, that takes some delay to do measurement.In the data sheet instructed that timer must be clocked from instruction cycle (Fosc/4).Then i unable to measure the time period of 10us(100kHz) input signal when the system frequency is 8MHz. Because the time period of input signal lies between the timer period i.e 500ns to 32.768ms. This is the major doubt for me. Why it is not happen.

author: NorthGuy
author_rank: Super Contributor
timestamp: May 10, 2019, 12:35:35 pm
content: Quote from: arul on May 10, 2019, 04:40:37 amWhy not? Higher timer frequency gives you more accuracy, but even with Fosc = 8MHz, (Fosc/4 = 2 MHz) there's still 20 timer counts in your 10 us pulse, so you can measure it with 0.5 us resolution.

author: IDEngineer
author_rank: Super Contributor
timestamp: May 11, 2019, 04:49:19 pm
content: Quote from: NorthGuy on May 09, 2019, 04:50:59 pmThis is true, but in Capture mode the CCP modules also support setting an interrupt flag. ISR invokation has low latency, and the ISR can read the CCP's captured value with just two instructions. Thus it should be trivial to read the captured values before they are overwritten unless the incoming frequency is a significant percentage of the instruction clock's frequency.Idea: It's possible to share a single Timer with multiple CCP modules. This means if you're using a first CCP for rising edges and a second CCP for falling edges, their captured values will be automatically sync'd and all sorts of math operations will be inherently simple and straightforward. Just a thought....

author: arul
author_rank: Regular Contributor
timestamp: May 13, 2019, 07:35:27 am
content: Quote from: IDEngineer on May 11, 2019, 04:49:19 pmI am also used single timer for all CCP modules and using rising and falling edges have separate CCP module. If I am measuring higher pulse width, it takes some delay to change. The lower pulse width change immediately. In my case 1000us is time period, the pulse width can change from 1us to 980us. If i changing the pulse width from 1us to 500us, i got response immediately, but above 500us, it takes some delay to change. Sometimes only i got response quickly. So how will i improve that higher pulse width measurement?

author: IDEngineer
author_rank: Super Contributor
timestamp: May 13, 2019, 07:20:12 pm
content: Resolution is controlled by the clock rate feeding the Timer. It's odd that you say it has what appears to be different resolution depending upon pulse width.Are you reading the Timer values from an interrupt routine invoked by the CCP interrupts? Do that before anything else... you need to eliminate the varying latency that comes from what I presume is polling.Also, based on your original questions, I'm not sure you've really studied the architecture of the CCP module and associated Timer when in Capture mode. You really, REALLY need to study that and understand all the options. It's not practical to ask individual questions like yours, it will take forever to get things working. Invest the time to really understand the spec sheet first.There's your action item list:* Study the CCP section of the spec sheet* Study the Timer section of the spec sheet, especially all of the clock options and prescalers and such* REALLY understand how the Timer and CCP's interact* Study the CCP interrupt options* Write an interrupt service routine (ISR) that gets called when the CCP's capture the Timer value, and write an efficient ISR to do that...and THEN see what sort of pulse width values you are getting.

author: Dabbot
author_rank: Regular Contributor
timestamp: May 25, 2019, 04:36:15 pm
content: Alternatively, try the Timer 1 Module with Gate Control. This peripheral will let you capture an event and won't be triggered again until you set the T1GGO bit. "Single Pulse" mode or "Single Pulse and Toggle Combined mode".