Demodulation of a data - Page 1
Forum section: electronics / beginners

author: fateme mrbs
author_rank: Newbie
timestamp: August 20, 2018, 03:10:02 pm
content: I have created the first signal in my circuit and the second signal that you see in this picture is what I'm trying to get at the output.Can anybody tell me what circuit can demodulate the first signal and get the second one?

author: Benta
author_rank: Super Contributor
timestamp: August 20, 2018, 03:19:57 pm
content: Simple averaging of the signal (=LPF) followed by a clipping amplifier should get you close. Of course, a synchronous demodulation would be better.

author: fateme mrbs
author_rank: Newbie
timestamp: August 20, 2018, 03:35:55 pm
content: Thanks for your answer.I already tried low pas filtering. It doesn't give a neat pulse.

author: Benta
author_rank: Super Contributor
timestamp: August 20, 2018, 04:08:45 pm
content: Quote from: fateme mrbs on August 20, 2018, 03:35:55 pmThat's why you need to amplify afterwards. Otherwise you won't get a square wave.

author: mikerj
author_rank: Super Contributor
timestamp: August 20, 2018, 04:51:14 pm
content: Your post is showing the signal being demodulated before even the first pulse has been received, and returning back to '0' immediately after the last pulse has been received. It should be obvious that this will not be possible in practice, unless you have already built a time machine. There will always be some latency between input and output.If the amplitude and timing of the pulses is well defined as shown i.e. the logic 1 pluses are always significantly higher amplitude than the logic 0 pluses then you may be able to feed the signal into a (very fast) comparator with a suitable threshold set (somewhere between logic o and logic 1 values), and use the output to trigger a (re-triggerable) monostable with a period just slightly longer then the period between your pulses. The downside of this would be noise immunity, and getting the 0/1 duty cycle correct

author: mmagin
author_rank: Frequent Contributor
timestamp: August 20, 2018, 07:18:05 pm
content: This is FSK? You could build a demodulator with a PLL (e.g. CD4046). Although it looks like the two frequencies have a 2:1 relationship ... it would be a lot easier if they didn't have a harmonic relationship -- that will confuse some phase detectors.

author: ogden
author_rank: Super Contributor
timestamp: August 20, 2018, 07:25:53 pm
content: Quote from: fateme mrbs on August 20, 2018, 03:35:55 pmThat's because demodulator is more than just simple filter. Hint: you can/shall sample filter output at exactly middle of the symbol, if/when you know where middle of the symbol is. Next question would be - how to sync symbols. I would answer: it's easy when bitstream is encoded for easy bit sync. Google for Manchester coding and NRZ coding.

author: Benta
author_rank: Super Contributor
timestamp: August 20, 2018, 08:07:51 pm
content: Quote from: mmagin on August 20, 2018, 07:18:05 pmWith just three cycles to change lock, that's totally unrealistic.

author: mmagin
author_rank: Frequent Contributor
timestamp: August 21, 2018, 01:10:10 am
content: Quote from: Benta on August 20, 2018, 08:07:51 pmYeah, I suppose you're right.

author: fateme mrbs
author_rank: Newbie
timestamp: August 21, 2018, 08:23:08 am
content: Quote from: Benta on August 20, 2018, 04:08:45 pmthe problem is that the low level after low pass filtering is above zero and an amplifier will amplify both high and low levels. so again I won't get an square wave.

author: vk6zgo
author_rank: Super Contributor
timestamp: August 21, 2018, 11:12:37 am
content: Quote from: fateme mrbs on August 21, 2018, 08:23:08 amRetro style was to amplify the hell out of it, then clip it savagely both top & bottom.

author: Benta
author_rank: Super Contributor
timestamp: August 21, 2018, 11:49:31 am
content: Quote from: fateme mrbs on August 21, 2018, 08:23:08 amThat's not a problem, it's a featureImagine low pass filtering the signal so you get something sinewave-like. That's your demodulated signal.Low pass filter your demodulated signal until the sine wave is gone. That's your DC reference (in the middle of the sine wave).Feed both to a differential amplifier to make a square wave.

author: rhb
author_rank: Super Contributor
timestamp: August 23, 2018, 02:26:06 am
content: Two approaches come to mind:count pulses if that's applicablemeasure the time since the last pulseIn either case, use a delay line to synchronize the input and output. Fundamentally that's what oscilloscope trigger circuits do. The signal is delayed a bit so that the trigger logic has time to determine if it should start a sweep.If you absolutely can't tolerate the latency of the delay line, use two analog correlators and feed the outputs to a comparator.If the two signals are constant, sample and feed to a pair of shift registers wired to to do an AND of the two patterns.Or clock the samples through a shift register, use the contents as an address into a lookup table that gives the desired output. The latter approach has the advantage that you can populate the LUT to accommodate variable timing and amplitude. At the price of a larger LUT.

author: fateme mrbs
author_rank: Newbie
timestamp: August 25, 2018, 10:13:55 am
content: Quote from: mikerj on August 20, 2018, 04:51:14 pmthe latency is not important. but the width of the pulse is. it should only cover the higher level pulses

author: mikerj
author_rank: Super Contributor
timestamp: August 25, 2018, 12:11:27 pm
content: Quote from: fateme mrbs on August 25, 2018, 10:13:55 amMaybe we need to step back a bit here, as I'm not familiar with the way you are generating these pulses. Does each separate pulse represent one bit, or is one bit represented by many pulses (e.g. 8 pulses for a logic 1)? If the latter, if there always the exact same number of pulses and pulse timing for each bit?If there are multiple pulses per bit this will not be easy to demodulate to meet your requirement above, certainly a low pass filter and slicer isn't going to cut it.

author: fateme mrbs
author_rank: Newbie
timestamp: August 25, 2018, 03:30:51 pm
content: Quote from: mikerj on August 25, 2018, 12:11:27 pmthe latter. one bit is represented by 8 pulses.If the latter, if there always the exact same number of pulses and pulse timing for each bit?almost, when i monitored it over a longer time. sometimes one pulse was missed. (7 pulses for a logic 1)

author: fateme mrbs
author_rank: Newbie
timestamp: August 26, 2018, 11:58:27 am
content: Quote from: mikerj on August 20, 2018, 04:51:14 pmI have these pulses after the comparator. (first picture)I tried using a monostable without having those more widely spaced pulses, (they were supposed to represent a logic 'zero'). and the result is good.But when I use the same monostable WITH the more widely spaced pulses, the result is crazy!Why is that so?