Flipflop is unstable - Page 1
Forum section: electronics / beginners

author: ratatax
author_rank: Regular Contributor
timestamp: August 03, 2019, 01:29:26 pm
content: Hi,I made a clock divider using two flip-flops, which takes a GPIO from my raspberry Pi as input :It should divide the input clock by four.Problem : it mostly works but output is not reliable and very sensitive to any noise... Like it gets better if I put my fingers on some pins... and gets much worse if I try to probe it with my scope.Signal input is about 200Khz and output should be 50Khz (divided by four), I use NC7SZ74's from On Semiconductor :https://datasheet.lcsc.com/szlcsc/ON-Semicon-ON-NC7SZ74K8X_C128370.pdfIs there something obviously wrong I my schematic ? Should I put resistors between some lines ?

author: fourfathom
author_rank: Super Contributor
timestamp: August 03, 2019, 01:45:23 pm
content: Your schematic looks fine, except that you don't show any bypass capacitors on the VCC pins. This is probably why you are seeing the noise problems. Connect 0.1uF ceramic capacitors between VCC and GND as close to the ICs as possible. Make sure that your ground connections are short.There are easier ways to do a divide-by-four, but what you have should certainly work once you get your layout noise problems solved.

author: tggzzz
author_rank: Super Contributor
timestamp: August 03, 2019, 02:17:00 pm
content: You are using fast parts, and they will have very high frequency components in the output signalsdefined by the transition time not the clock period.If you are using solderless breadboards, you will fail due to the inductance of all the interconnection wires.If you are not using solderless breadboards, you may still fail unless you have decoupling capacitorsplusdirect connections (not wires, and preferably a continuous ground plane).Realise a wire is L=1nH/mm, then do the calculation of V=Ldi/dtand realise that V is added/subtracted to signal voltages. dt is the transition time (probably 1ns or less) and di=3.3C/dt, where C is the a load capacitance (assume 10pF) and 3.3 is the voltage swing.

author: ratatax
author_rank: Regular Contributor
timestamp: August 03, 2019, 02:57:25 pm
content: Quote from: tggzzz on August 03, 2019, 02:17:00 pmThanks, yes all of this is on a prototype board with a real mess of wires all over the place, I noticed disconnecting another chip on 3.3V made things better so yeah probably a noise problem that will be solved once put on a real pcb ! Bypass capacitors had no effect but I can't put them close to the IC pins, 0.5mm pitch by hand is a nightmareQuote from: fourfathom on August 03, 2019, 01:45:23 pm@fourfathom i'm interested by the easier way to do the frequency division, could you do this with only 1 component ?

author: Kleinstein
author_rank: Super Contributor
timestamp: August 03, 2019, 03:08:09 pm
content: There are slow chips that are less sensitive. They also get away with a slower rise time for the clock. The classic 74HC74 has 2 such flipflops in one case. 74AC74 would be a little faster than classic HC. 74HC74 usually still works on the breadboard.The are also ready made ripple counters that could be used, though usually not small than 74HC74, just more stages.

author: tggzzz
author_rank: Super Contributor
timestamp: August 03, 2019, 03:25:28 pm
content: Quote from: ratatax on August 03, 2019, 02:57:25 pmDo the arithmetic. L=150mm->150nH. C=20pF (scope probe). Assume dt=1ns. Hence di=66mA. Hence the induced voltage V=9.9V. While the details of all those numbers can be debated, clearly that voltage is sufficient to potentially cause maloperation.Solution: better construction and/or logic with a slower transition time and/or limiting the transition currents

author: fourfathom
author_rank: Super Contributor
timestamp: August 03, 2019, 04:30:57 pm
content: Quote from: ratatax on August 03, 2019, 02:57:25 pmI was thinking of something like the 74HC163 :http://www.ti.com/lit/ds/symlink/sn74hc163.pdfThis is a synchronous 4-bit binary counter (but you can use it as a divide-by-four) in a 16-pin package. At VCC = 3.3V it's a slow part (about 5MHz) so I don't know if it will be fast enough for you, but it will be fairly forgiving of layout and noise issues. The 74AC163 is a much faster version (Fclk = 73MHz @ 3.3V).I don't know if the layout is any easier, but in general I do prefer synchronous counters to ripple ones. However in many applications this detail will make no difference.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 03, 2019, 05:20:04 pm
content: Ripple counters tend to use less internal flip-flops and this way cause slightly smaller supply current spikes (lower power dissipation capacitance). They may also be a little faster for the same technology. So something like HC93 (4 bit ripple counter) could be a option.For a divider a ripple counter is usually good enough, though there could be slightly higher jitter with higher divider ratios. For just a factor of 4 it should not make much of a difference.

author: themadhippy
author_rank: Super Contributor
timestamp: August 04, 2019, 04:23:24 pm
content: my goto for frequency division between 2 and 10 is the good ole 4017

author: ratatax
author_rank: Regular Contributor
timestamp: August 06, 2019, 10:38:47 pm
content: Thank you all for the ideas, actually I need quite fast parts even if the signal is not of high frequency, since it's used as a 'frame indicator' for a much faster signal (6Mhz). For some reason, using a classic 74HC74 isn't fast enough even if it's rated for more than 20mhz if I remember correctly. I had a delay of about 1 clock @ 6Mhz with it

author: tggzzz
author_rank: Super Contributor
timestamp: August 06, 2019, 11:09:05 pm
content: Quote from: ratatax on August 06, 2019, 10:38:47 pmThe clock period is completely irrelevant. All that matters is the transition time. That is the "dt" I mentioned above.Do the arithmetic.

author: fourfathom
author_rank: Super Contributor
timestamp: August 06, 2019, 11:29:26 pm
content: Quote from: ratatax on August 06, 2019, 10:38:47 pmThis is one case where a synchronous divider can help. With your original ripple divider you have two clk-q delays in series. A synchronous divider will have just one clk-q delay.