Why does a 80C88 require decoupling capacitor between its two ground pins? - Page 1
Forum section: electronics / beginners

author: AndrejaKo
author_rank: Frequent Contributor
timestamp: October 14, 2025, 08:02:30 pm
content: While aimlessly browsing Mouser, I've stumbled upon 80C88 from Renesas (https://www.renesas.com/en/document/dst/80c88-datasheet) and I've noticed that the chip has 2 ground pins, number 1 and 20, on opposite sides of the die, and one Vcc pin, number 40, which is right next to pin 1 on the die.The datasheet mentions that the proper way to do decoupling is to have once 100 nF capacitor between pins 20 and 40, which follows the tradition of the era, but it also mentions that the pins 1 and 20 should be connected by a capacitor. Here's an illustration from the datasheet:as well as the written explanation:Now I've been exposed to the following teachings: Digital electronics have needs for large amounts of current when the chip switches, and therefore, we need to minimize the inductance (by minimizing current loop, picking low ESL capacitors and so on) between the power and ground pins, and their local source of energy, which would be a capacitor. This way, we ensure that the die has stable source of voltage when it switches.If I analyze the picture of the mask from the datasheet with that in mind,I would see that the pins 1 and 40 are the closest on the die, and that I should put a capacitor between the two of them, to minimize the loop. Yet, the datasheet recommends putting a capacitor on the opposite ground pin, and then connecting the two ground pins with a capacitor. Furthermore, I'm not really sure how would the current flow between the capacitor and the two ground pins in case of uneven ground bounce between them: The capacitor would be normally discharged, and in case of ground bounce, would it start charging, therefore minimizing the voltage spike between the two pins? If yes, is this a common technique? I'm not a PCB engineer, so I'm definitely missing something, but I've never before seen such a recommendation in a datasheet.

author: Whales
author_rank: Super Contributor
timestamp: October 14, 2025, 08:19:44 pm
content: I suspect this is a mistake.If pin 1 and 20 are both connected to a ground plane then they are effectively shorted. Any component between them will be bypassed and irrelevant, for both DC and AC.The only exception I can think of is if one of those pins isn't actually a GND and they have mislabelled it.

author: AndrejaKo
author_rank: Frequent Contributor
timestamp: October 14, 2025, 09:42:35 pm
content: Well, 8088 pinouts definitely match the two ground pins, and also the mask image has two pins labeled ground, so I do believe that there are indeed two ground pins.For the short, well we might have 50ish nH of inductance just for the shorting trace, plus there would be extra wires on the chip package itself.For example, output signals have maximum rise time of 15 ns, which gives us some 23ish MHz of bandwidth. At 23 MHz, the 50 nH trace would have impedance of around 7R, if my calculations are correct.So it could easily happen that we have 10R-20R of impedance between those pins when the at the moment clock changes state, or am I looking at this incorrectly?

author: ataradov
author_rank: Super Contributor
timestamp: October 14, 2025, 09:49:29 pm
content: This is not a mistake, since they also mention them in the description for the GND pins: "GND: Ground pins (both pins must be connected to system ground). A 0.1µF capacitor between pins 1 and 20is recommended for decoupling."My only guess is that they are trying to compensate for the possible internal ground level difference because of the pads being on opposite sides if the die. But this is really weak, and I have no idea how that would actually work.

author: Whales
author_rank: Super Contributor
timestamp: October 14, 2025, 10:05:05 pm
content: Two options that would take the same amount of board space:1. Place a short between the two GND pins (eg a 0-ohm resistor). A few nH of inductance, let's say 10milliohms resistance.2. Place a capacitor between the two ground pins. The same few nH of inductance, similiar 10 milliohms of resistance.Both will perform identically at higher frequencies (a short). As frequency drops the 0-ohm resistor will win out and be better.

author: David Hess
author_rank: Super Contributor
timestamp: October 14, 2025, 10:05:14 pm
content: The GND pins are so far apart that adding a decoupling capacitor between them would be useless; the decoupling capacitor is not going have a lower AC impedance than a trace, or more likely a thick trace or ground plane. I have no idea how that recommendation made it into the datasheets.Multiple 80C88 datasheets say the same thing, but the original 8088 datasheet says nothing about decoupling between the GND pins.

author: Psi
author_rank: Super Contributor
timestamp: October 14, 2025, 10:10:43 pm
content: Could be just one of those things you find that improves some aspect but no one can work out why and you just run with it.

author: Whales
author_rank: Super Contributor
timestamp: October 14, 2025, 10:12:54 pm
content: Perhaps the capacitor is social engineering, not electrical engineering.Picture: designers of two layer boards, smoking asbestos cigarettes, surrounded by desks of mixed through-hole components and ash trays. They see two "gnd" pins and go "oh that makes our job easier not harder". They proceed to do an awful grounding layout with thin, snaking traces from the ground pins. It takes 20cm of looping around the board before they converge, near a random LED and DB connector.Meanwhile at the 80C88 office, beneath a haze of cigar smoke and sentient floating antimacassars, the secretaries are flustered from handling constant calls on their plugboard PBXs from customers complaining that these CPUs don't work. Lawsuits are thrown around, management swells with fury, the engineers are pressed for answers.The engineering team asks the angry clients for samples of their boards. They get them and... oh. Oh no. How are they going to fix this?"Oi Dirk, what if we drew a jumper link on the diagram between those two parts?""Nah Geoff, people will just ignore it. 'Those already be two grounds' and all that.""Wot if it were a cap?""Huh. Oh yeah. People wouldn't skip that. They understand those. Gotta be near the chip as possible, high priority routing, yeah. Plus we'd see it on their boards so we'd know they actually read the manual."And thus, finally and in the weirdest way possible, the scourge of bad PCB layouts was tamed.

author: ataradov
author_rank: Super Contributor
timestamp: October 14, 2025, 10:14:25 pm
content: If it was a one-off thing that helped in some design and they just put it in the datasheet, it would be really sensitive to the capacitor package and board routing.I think we can all agree that just placing a shorted SMD capacitor somewhere on the ground plane will do absolutely nothing.

author: mikerj
author_rank: Super Contributor
timestamp: October 14, 2025, 10:15:10 pm
content: Quote from: ataradov on October 14, 2025, 09:49:29 pmIf both GND pins are tied to a solid ground plane it would be pretty safe to say a capacitor between these pins would do nothing, apart from maybe confuse anyone trying to reverse engineer the design.

author: Psi
author_rank: Super Contributor
timestamp: October 14, 2025, 10:15:14 pm
content: Maybe it gives them some legal protection, they can point to it in court and prove you didn't follow their design docs because you didn't put the cap there. So they're not liable.But TBH i think most people would put a cap there if they DS says to, just to play it safe, considering the cost is not an issue for one extra 0.1uF cap.

author: free_electron
author_rank: Super Contributor
timestamp: October 14, 2025, 10:24:17 pm
content: One of them is the substrate pin. Some of the earlier NMOS needed a negative voltage on the substrate. The double ground pin is a leftover from that era. (backward compatibility).original 8088 had a built-in charge pump for that purpose : 80c88 is cmos but for backward compatibility retains double ground pinhttps://www.righto.com/2020/07/#:~:text=The%20outputs%20from%20the%20ring,bond%20wire%20to%20the%20substrate.

author: Whales
author_rank: Super Contributor
timestamp: October 14, 2025, 10:25:07 pm
content: Quote from: free_electron on October 14, 2025, 10:24:17 pmThat makes sense. The negative voltage was replaced with GND, but the cap was never removed.

author: ataradov
author_rank: Super Contributor
timestamp: October 14, 2025, 10:27:05 pm
content: Having two pins on the opposite sides of the die is good regardless. But the capacitor makes no sense. I can see it being useful if substrate voltage is generated internally and it is just a bypass capacitor, but you would not be able to solder the old IC into the new board, it would just short substrate to the ground.I can see it not being removed on the schematic, but someone had to type that sentence in the description. How do you do that by accident?

author: free_electron
author_rank: Super Contributor
timestamp: October 14, 2025, 10:29:17 pm
content: Quote from: ataradov on October 14, 2025, 10:27:05 pmIt's not a direct substrate connection but the return for the charge pump. You don't want the switching current bouncing the real ground pin up and down.To keep the 80C88 pin compatible they labeled the pin as GND. Good old NMOS days ...https://www.righto.com/2020/07/#:~:text=The%20outputs%20from%20the%20ring,bond%20wire%20to%20the%20substrate.

author: amyk
author_rank: Super Contributor
timestamp: October 15, 2025, 01:49:14 am
content: The charge pump theory makes sense superficially, but even the original NMOS 8088 and the 8085 that came before were already single-5V-supply. The 8085 also has only one ground pin.

author: free_electron
author_rank: Super Contributor
timestamp: October 15, 2025, 03:04:02 am
content: Quote from: amyk on October 15, 2025, 01:49:14 amThey have an on-board charge pump that makes the negative rail. The pump is physically located close to the ground pin and bonded separately so the switch current does not create ground-bounce. The substrate is biassed negatively internally. No need for external negative supply.The first eeproms and micro's and pretty much all NMOS stuff required a negative supply to reduce leakage through the substrate. By using internal charge pumps they eliminated that.Several of the first NMOS ics like HP's nanoprocessor and the processor used in their calculators and multimeters like the 3455 had the required bias voltage written in pencil on the ceramic casing. The early NMOS processes were so unreliable that they measured the lowest leakage point and simply wrote the required voltage on the device.Go watch some CuriousMarc videos where he repairs an early HP calculator and digital multimeter. It's all explained in great detail . Ken Sherrif has done deep dive reverse engineering and given the full explanation on how this thing works.