XMOS Announces xCore will be RISC-V Compatible - Page 1
Forum section: electronics / general

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: December 13, 2022, 06:04:00 pm
content: Not much info yet...https://eenewseurope.com/en/xmos-announces-xcore-will-be-risc-v-compatible/

author: tggzzz
author_rank: Super Contributor
timestamp: December 13, 2022, 06:15:03 pm
content: There is a little more in the form of a flyer that you can get if you give them an email address (maininator is OK).As far as I can tell, they are simply replacing one ISA with another. The unique and important bits of the ecosystem stay unchanged: the cores/SMT/tiles, the i/o, the switching fabric, the comms, the languages, the design patterns, and most importantly the hard real time guarantees.If that's correct, it is a pretty good data point indicating how unimportant an ISA has become.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 13, 2022, 07:06:47 pm
content: And so I kinda fail to see the point, except to get a bit more hype due to the traction around RISC-V. Ah, marketing.(Now to be fair, XMOS doesn't get enough attention, so I don't blame. And piggybacking on the RISC-V toolchains - although I don't know how much the xC compiler has in common with existing tools - has some benefits.)

author: tggzzz
author_rank: Super Contributor
timestamp: December 13, 2022, 07:23:19 pm
content: It seems to me that the unique guarantees are derived from the everything except the ISA.The cacheless cores heavily SMTed into tiles, the message passing, the i/o structures, the xC language structures are all vital to fixed timing operation.The timing guarantees shown in the IDE are an analysis of the compiler's output. The ISA is merely an intermediate artefact.The LLVM compilers' front end is specifically for xC, but the optimisation is standard.TheSo there may be advantages to going to RISC-V, but nothing revolutionary.And don't I remember one of their chips having an ARM core as one of the 8 cores in a tile?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: December 13, 2022, 10:27:28 pm
content: Quote from: tggzzz on December 13, 2022, 07:23:19 pmYes, this looks exactly the same approach, as they say this"By combining xcore and RISC-V"The development looks quite slow, maybe COVID impacted ?Quote

author: brucehoult
author_rank: Super Contributor
timestamp: December 13, 2022, 10:44:15 pm
content: Quote from: tggzzz on December 13, 2022, 06:15:03 pmAll well-designed ISAs are basically interchangeable on a technical level, yes.Which is not the same thing as saying there is no such thing as a bad ISA -- there certainly is! FTDI's Vinculum-II ISA being an awful one, for example. Even modern x86 is very reasonable *except* for the instruction encoding, and Intel and AMD simply have to pay a tax on working around that.What this really says is that the cost of developing and maintaining the whole ecosystem for an ISA at a level competitive with other ISA's ecosystems is too much for any one company -- especially a small one -- to bear.

author: tggzzz
author_rank: Super Contributor
timestamp: December 13, 2022, 11:53:32 pm
content: Quote from: brucehoult on December 13, 2022, 10:44:15 pmI'm not sure how much extra work there is in the backend of a compiler, compared with the entire ecosystem.As for the hardware, the xCORE approach isn't a bog-standard RISC-V implementation blob that can be simply bought and then plonked down on the silicon. Their requirements are "non-standard" in that they must omit caches of any sort, and must include extra registers+wires for their heavy SMT approach (the same as Sun's Niagara T processors). Yes, I realise there isn't any such thing, but my point still stands