My power supply layout - Page 1
Forum section: electronics / beginners

author: bfrigon
author_rank: Contributor
timestamp: February 11, 2015, 08:00:39 pm
content: Hi!I'm working on a switching power supply design and i would like your opinion on the layout.I tried to make it as close as possible to the suggested layout in the ADP2302 datasheet. This is not easy, i only have about 1.1 sq inch of board space (1.25 x .875) to fit two regulators.Here is the question... Am i going to run straight into a wall with this design?Here are the specs :Input: 7v-12v, nom 9vOutput 1 : 3.3vMax. current : 2125mAOutput 2 : 5vMax. current : 1800mALayout :Top layer:Bottom layer:This is the schematic:

author: cjk2
author_rank: Contributor
timestamp: February 11, 2015, 08:15:07 pm
content: It may well work as is. Flipping C15 and C22 around will allow you to make the input supply bypass loop smaller. It's too bad that ground plane is cut up so much. Going to 4 layers or trying again might help.

author: bfrigon
author_rank: Contributor
timestamp: February 12, 2015, 06:10:45 am
content: Quote from: cjk2 on February 11, 2015, 08:15:07 pmThank you for your answer,I reworked my layout using 4 layers. The ground pour in other parts of the board was much worse (what was left of it anyway). So, it's an improvement already.I setup my layers this way :Top (1) : SignalLayer 2 : Ground planeLayer 3 : PowerBottom (16) : Signal / groundAnother question... Should i split the ground between the two regulators? Does that makes much of a difference or is it a bad idea?This is the new layout :Thank you

author: cjk2
author_rank: Contributor
timestamp: February 12, 2015, 02:30:27 pm
content: Your arrangement of layers is fine and typical.I doubt it will make any difference how you split the ground plane. My guess is it is slightly better to do it as you did in your first post, with each power supply on its own split section.

author: free_electron
author_rank: Super Contributor
timestamp: February 12, 2015, 03:02:11 pm
content: your pick off point for the 3.3 volt should be at the capacitor pins and not at inductor pad.there are pulsed currents running through the copper connecting the coil to the cap. you will have more noise if you pick it off at the coil as the resistance of the track essentially becomes series resistance for the cap ( it's like getting a cap with worse ESR )Now , on plugging many via's : that is a trap for young players. Avoid having any via's in the pathway chip-coil-cap .that should all be routed top layer.here is the problem with a sea of via's : via's have an inductance. two via's each to each other will couple into each other. For two via's that conduct the current IN THE SAME DIRECTION this behaves like a common mode chocke.you would expect that parallel inductance result in a lower total inductance , just like resistors. That is true , unless the magnetic fields couple.The rule is : via's carrying current in the same direction must be place 3 trace widths ( or via pad diamters ) away from each other to completely ( well, not completely but to the point there is no noticable effect anymore .. inverse of square rule ) get rid of this effect.so a sea of via's is good , but don't shoot them too close together.Note : this is ONLY true for via's carrying THE SAME current int he SAME direction. for two adjacent via's one with current flowing top to bottom and one with current bottom to top this is no longer the case. now the fields are canceling each other.

author: c4757p
author_rank: Super Contributor
timestamp: February 12, 2015, 03:15:33 pm
content: Quote from: free_electron on February 12, 2015, 03:02:11 pmThat is a good point. Got a source for that rule of thumb? I'm interested but can't be bothered to solve the equations for a sea of loosely coupled inductorsAlso, I'd argue that it's quite more likely to be dependent on the drill diameter than the pad diameter, as that's the part that forms the individual coupled inductors. Also makes more sense when you consider the case of vias stitching together pours...