When CPU's are made is each one slightly different? - Page 1
Forum section: electronics / general

author: Beamin
author_rank: Super Contributor
timestamp: September 05, 2018, 09:00:56 am
content: Since they are up to billions of transistors that are made from a small amount of atoms, there must be some that don't come out perfectly from impurities and other things. it seems as if to get all 1 billion right they would have to reject a huge number of dies. So do they build error correction into each chip where if a gate is bad in memory the chip can use a different one? Say they know that 0.000001% will be bad but need a minimum of 1,000,000 gates could they just make each memory cell with more gates and error correction then only reject the really defective chips?Or maybe they can get all 1 billion transistor correct almost every time and that's just amazing. But how much cheaper/faster could they make chips if they could use error correction and afford to have less then perfect chips? Also at what point did error correction become necessary? The 8502 was laid out by hand so I imagine that needed 100% to work but that chip had orders of magnitude bigger features on it.Isn't this how hard drives are made; they just expect so many bad sectors and this is sorted out by oversizing the drive and optimizing it down to spec during formatting and each herd drive learns its own platter? Would the same apply to SSD's as the gates become unusable?

author: Halcyon
author_rank: Unknown
timestamp: September 05, 2018, 09:26:49 am
content: Quote from: Beamin on September 05, 2018, 09:00:56 amKind of. Back in the day of MFM hard disk drives, manufacturers used to actually test and list bad sectors on a list stuck to the top of the drive itself. These were also mapped during low level formatting.Low level formatting doesn't really exist any more (at a consumer software level), I mean it does during hard disk manufacturing, but if you do manage to completely wipe a modern spinning rust drive (for example, by using a deguasser), you'll render that drive completely unusable.SSDs are also usually made with extra capacity, not seen by the host system. Internal wear levelling and error correction in the drive firmware itself will dynamically remap blocks which have become bad into this spare area.It's all basically designed to increase the serviceable life of the drive. These damaged areas (sometimes entire tracks) can be interesting from a digital forensics point of view, as once an area is marked bad and remapped by the controller, it's not longer accessible without special hardware. That means even if you try to overwrite that sector, you are actually overwriting the good (remapped) sector in the spare area, leaving whatever data behind in the bad area.

author: filssavi
author_rank: Frequent Contributor
timestamp: September 05, 2018, 09:52:56 am
content: What you say is already done extensively by the various intel/and/etc.Of course there a full test such as hard drives is not feasible since the structure is far too complex and a full test would take far to much time. Test and characterisation is however done at a higher level.For example let’s take intel lineup for familiarity, it’s well known that low to mid end Xeon, i9 and I7 use the same silicon die. They all start out as Xeon, the ECC memory and busses for dual cpu support are tested, if any of the two don’t work the die is downgraded to I9, now the cores are tested, if some of them aren’t working correctly the die is downgraded to i7 etcAlso another thing to note is that while we think to them as such mosfets are not digital switches, they are analog transistors, so it is quite unlikely that one isn’t switching at all, a far more likely defect is a transistor that cant switch at the maximum designed frequency.That is why in intel lineup there are dozens of SKU’s with marginally different frequency, so that defective xeons aren’t thrown away, just sold as low end I7’s for less profitEDIT: also error correction in general adds a lots of overhead so in order to add ecc logic to the whole design you might need to add 20 to 50% more transistors to the whole CPU, that could otherwise be put to much better use.

author: Beamin
author_rank: Super Contributor
timestamp: September 05, 2018, 10:05:51 am
content: Quote from: Halcyon on September 05, 2018, 09:26:49 amIn the days off das I remember stuff was never deleted but rather it put a ? in front of the filename and wrote over it when it felt like it. What does it do today? Is there an option in windows to hard delete things? I remember seeing an option to "shred" a file but I think that may have been an option with some antivirus software. Or is "hard deleting" only possible with special software and effort on part of the user?

author: Halcyon
author_rank: Unknown
timestamp: September 05, 2018, 10:23:47 am
content: Quote from: Beamin on September 05, 2018, 10:05:51 amThat was specific to the FAT file system. To mark a file as deleted, it would replace the start of the file with a hexadecimal value of 0xE5. This meant that the first letter of the file name was lost (and why running UNDELETE.EXE required you to input the starting letter when recovering a file). All undelete did was look for those files starting with 0xE5 and provided they haven't been overwritten, it would recover them (i.e. replacing E5 with something else)."Shredding" files is just overwriting all the clusters taken up by that file with other data (usually 1's, 0's or random garbage). That renders the file completely obliterated and unable to be recovered.Today's modern file systems aren't much different, most just remove the entry from the allocation table which marks those clusters free to be overwritten. Most operating systems these days come with an option to totally erase the file (as per above), but a normal "delete" command usually doesn't invoke this mechanism. With whole disk encryption, it's largely not too much of an issue any more for the average user. Erasing a large file takes time, deleting a file entry doesn't.Gees, you're taking me back to the good old days :-)

author: Berni
author_rank: Super Contributor
timestamp: September 05, 2018, 10:29:27 am
content: Yep they do that.AMD used to make 3 core CPUs back when multicore became mainstream. Seams like an odd choice to make a 3 core right? Well actually they are quad core CPUs where one of the cores has failed quality control so it was disabled and sold as a 3 core chip. Intel probably still does this with the high core count chips like the 18 core and up stuff because the more cores you have the higher the chance is that one of them is bad.But its not only cores. The variances in the manufacturing process result in some chips running slightly better than others. All the chips that come off the production line are tested beyond there spec to reveal how good the chip is. Depending on the results of the test they might stamp a bad one with a 3.2GHz model number while a good one gets stamped with a 4.4GHz model number. Additionally the particularly good ones also get the K on the end of the partnumber to designate them for overclocking (Intel specific).GPU vendors do the same thing. Graphics cards have a very high number of processing cores >1000 cores so the chance that all are working is slim. Additionally there are other processing blocks that they have multiple ones like the ROP(Render outout processor), Texture units or memory controllers. For chips that have a lot of these other processing blocks dead are sometimes repuposed as the model lower down. For example the Nvidia GTX 1070 is made from the rejected chips for the GTX 1080 (That actually caused issues at some point i think).

author: PA0PBZ
author_rank: Super Contributor
timestamp: September 05, 2018, 10:49:42 am
content: Quote from: Halcyon on September 05, 2018, 09:26:49 amG=C800:5Some things you never forget it seems

author: Halcyon
author_rank: Unknown
timestamp: September 05, 2018, 10:57:00 am
content: Quote from: PA0PBZ on September 05, 2018, 10:49:42 amI think that's the only time I actually used the DOS debug command.

author: PA0PBZ
author_rank: Super Contributor
timestamp: September 05, 2018, 11:05:03 am
content: D 0:400To see how many serial and parallel ports are available.

author: wraper
author_rank: Unknown
timestamp: September 05, 2018, 11:17:52 am
content: Quote from: filssavi on September 05, 2018, 09:52:56 amDisabling ECC and some other server grade features have nothing to do with die quality. The only things that are disabled due to faults are cache and whole cores (EDIT: I guess hyper-threading as well due to partially faulty cores). Also those often are disabled purely for marketing reasons, to supply necessary amounts of certain price range CPUs. It's like with oscilloscopes, same hardware but different software locked features and bandwidth.Speed grade can be binned by die quality or simply downgrading fast dies just to meet market demand.On the other hand faults in NAND is a normal thing and are managed by controller similar to HDDs.

author: amyk
author_rank: Super Contributor
timestamp: September 05, 2018, 11:40:57 am
content: Some of the Xeons have ECC cache:https://www.realworldtech.com/forum/?threadid=161949&curpostid=161951I believe all of them have parity, however.

author: Beamin
author_rank: Super Contributor
timestamp: September 05, 2018, 12:18:32 pm
content: Quote from: wraper on September 05, 2018, 11:17:52 amThat makes sense making all the dies the same and purposely down grading them since its the same price to make. But how do they tell the chip "don't run as fast as you can?" without physically altering it? Does it have some sort of secret memory in it like ROMs?I always thought they did the same thing with memory cards: Make them all 128G sell them at four different price points/capacity when they first come out 128, 64, 32, 16, but somehow disable some of the memory and when the company made enough money/ competitors start lowering price make a 512g and do the same thing. Seems like the SEC/FTC or some regulatory body wouldn't allow this but who knows they don't work for us they work for the sharehoders. It's like how food is priced in this country: Since there are only 4 chains to chose from in each town they all match each others price but up instead of down; unlike down instead of up you had the 4 local businesses to chose from. One store raises the price of eggs by 10 cents then they all raise them a week later by puttingthem on "sale": "Was 1.39 now 1.29". In reality they were 1.19 last week. I caught target doing this with other grocery stores many times. I try NOT to buy things on "sale".

author: David Hess
author_rank: Super Contributor
timestamp: September 05, 2018, 12:27:43 pm
content: Quote from: blueskull on September 05, 2018, 11:24:56 amCache structures are usually protected by ECC or just parity if the data can be fetched again like the instruction cache. The reason for this is that the highest performance SRAM has a soft error rate orders of magnitude higher than DRAM.Large regular structures like SRAM may have redundant rows to increase yield. As I recall, one of the reasons the original AMD K6-3 had poor yield was lack of enough redundancy in the level 3 SRAM cache.QuoteThis has nothing to do with anything except market segmentation. Intel disables ECC on processors intended for the consumer market which would otherwise compete with more expensive workstation and server processors. AMD does not so I have been using AMD since I retired my Intel Pentium 4 workstation.Quote from: Beamin on September 05, 2018, 12:18:32 pmThey do not generally include any programmable memory type structures because it would require a more complex process but in the recent past, jumpers were included as part of the packaging. I assume they are still using jumpers in one form or another. The clock multiplier configuration is controlled in this way.Some features may be tied to the support chips. With perhaps some recent minor exceptions, Intel for instance only allows ECC with workstation south bridges so you must have a workstation board and a workstation processor.QuoteThat would be silly to do because the cost of the chip is roughly proportional to area. 128G chips configured as 16G chips still cost the same as 128G chips.

author: Berni
author_rank: Super Contributor
timestamp: September 05, 2018, 12:34:27 pm
content: They do that sort of binning for memory chips to some extent.The process for making flash memory is really pushing density to the limits to get the most capacity for a given area of silicon. So you could get the reject 128GB chips sold as 64GB ones to make some money off the lost yield, especially if the particular batch had bad luck. But they certainly wouldn't be disabling 128GB chips to make them look like 16GB. A flash chip with 1/8th the memory size also takes 1/8th the silicon area to create so they can get 8 times more chips from the same wafer. Tho in practice its not quite 8 times since the memory controller takes up a little bit of area and the die cutting process destroys some silicon area around the die.

author: David Hess
author_rank: Super Contributor
timestamp: September 05, 2018, 12:43:00 pm
content: Quote from: blueskull on September 05, 2018, 12:31:17 pmParity can only be used with write through cache where a copy of the data is always available somewhere else as with instruction cache.Write back cache must use ECC unless it has a low enough soft error rate which is generally not the case.

author: rstofer
author_rank: Super Contributor
timestamp: September 05, 2018, 04:17:26 pm
content: There was a time when Control Data computers (6400, 6600) got us to the Moon (July 20, 1969). The machines didn't even have parity checks much less ECC.

author: SparkyFX
author_rank: Frequent Contributor
timestamp: September 05, 2018, 04:35:46 pm
content: Quote from: rstofer on September 05, 2018, 04:17:26 pmBut redundancy is quite usual in aeronautics, it allows to take 2 out of 3 signals as true. No idea if the moon lander had several backups in place, though.

author: David Hess
author_rank: Super Contributor
timestamp: September 05, 2018, 06:05:53 pm
content: Quote from: rstofer on September 05, 2018, 04:17:26 pmIt is certainly possible to make reliable systems without ECC; just lower the soft error rate enough. But this comes at the expense of speed and power.One of the big advantages of ECC is in addition to correcting errors, it also allows notification that there was an error and where. Otherwise how would you know short of data corruption detected later?

author: coppercone2
author_rank: Super Contributor
timestamp: September 05, 2018, 07:25:12 pm
content: this makes is a security nightmare. I destroy my old hard drives with a pick axenot gonna pay electrical power to melt it or spend alot of time on it, wipe and axe will keep most things away, otherwise use a kiln

author: jmelson
author_rank: Super Contributor
timestamp: September 05, 2018, 10:09:14 pm
content: Quote from: SparkyFX on September 05, 2018, 04:35:46 pmAbsolutely none! They had one of the first, ever, computers built with ICs. The size of a big shoe box, had to run continuously for THREE DAYS off batteries while sitting on the moon! No way they could have a triple-redundant lock-step voting system with those constraints.They DID have some pretty rigorous contingency plans for what to do if one of the computers broke, though. If they got settled on the moon and the computer died, they could use the written-down coordinates they took upon landing, and the computer on the Apollo command module could tell them when to launch, that would be radioed down as the command module orbited. I think if the command module computer died, the LEM could still link up to it by itself, then they could use the LEM computer to handle the orientation and timing to fire the retro engine. I think they actually did this on the Apollo 13 (right #?) mission where the Oxygen tank blew and they lost electrical power on the command and service modules.Jon

author: Cerebus
author_rank: Super Contributor
timestamp: September 05, 2018, 10:48:28 pm
content: Quote from: David Hess on September 05, 2018, 06:05:53 pmThe CDC 6600 was a 2 MIPS machine that consumed 30 kW. So, yeah, a tad slower than modern toothbrushes* and greedier on the juice too.It had a 100ns minimum memory access time, which was pretty damn fast for it's time.As to the claim that it didn't use parity or other error checking, I find that unlikely as it was pretty ubiquitous in mainframe designs of the time, but I'm not going to trawl through the documentation (available on-line andmassivelydetailed compared to modernnon-documentation) just to prove a strong suspicion.*A Braun Sonicare Platinum toothbrush has a PIC16F1516 microcontroller in it rated at 5 MIPS and runs from a battery that fits inside the hand-held toothbrush. It is not recommended that you use your toothbrush to plot earth-lunar orbit parameters.

author: duak
author_rank: Super Contributor
timestamp: September 06, 2018, 02:14:37 am
content: From Wikiquote on Seymour Cray and the CDC 6600 & 7600:"Parity is for farmers."On why he left memory error-detecting hardware out of the CDC 6600."I learned that a lot of farmers buy computers."After he did include error-detecting hardware in the CDC 7600.Back when mainframe computers had the CPU in one cabinet, the memory in another and I/O channels in various others it made a lot of sense to carry parity all the way from data in to data out. I read somewhere that was a sign that the designers were serious about reliable computing. I've never used an old mainframe so I don't know personally if it makes difference. I did use 800/1600 tapes and the drives would start to throw soft parity errors when it was time to clean the heads.Cheers,

author: Tom45
author_rank: Frequent Contributor
timestamp: September 06, 2018, 03:15:01 am
content: Quote from: Cerebus on September 05, 2018, 10:48:28 pmThe 6600 definitely didn't have memory parity checking.I worked with the 6600 in the late 60's and early 70's. When the Boeing 747 entered service in 1970, a coworker said he wasn't going to fly on it because Boeing had done the aeronautical design using a 6600 without parity. So he didn't trust the design results, or the plane. Back then memory reliability wasn't up to current standards.History shows that Boeing got it right anyway.

author: Beamin
author_rank: Super Contributor
timestamp: September 06, 2018, 08:47:20 am
content: Quote from: blueskull on September 05, 2018, 12:50:03 pm

author: Beamin
author_rank: Super Contributor
timestamp: September 06, 2018, 09:20:18 am
content: Quote from: blueskull on September 05, 2018, 12:50:03 pmIt's a shame that companies have to compete with this. It was fine when you went to a store and had the option of buying the cheap stuff made in china or spending a few dollars more to get stuff that was made else where and would last. But now you don't have that choice; unscrupulous companies found they could just brand the shit products from china and put the higher price tags on them. Since our market only goes off a companies stock price the other companies that didn't want to do this had to or face going under. This along with consumer ignorance/laziness started the race to the bottom. I used to try very hard to avoid buying things made in china but the last time I did that was for a pair of running shoes made in America. It literally took all day and when I did find the pair I wanted they only made one color in America, the one I didn't want but bought anyways. Now I still look at label but mainly to see if it is made in china is this product going to harm me because it contains toxic metals or chemicals which even the name brands can because there are so many steps in the supply chain. The only thing I will not compromise on now is hormones and food. Anyways....QuoteI thought when they made chips like memory chips it was like photo copying: where sure it costs more money to layout a higher Gb; say double, but if you have four size chips you want to market it makes much more sense to make the larger gb size and have one mask/layout then to have four. If I owned a memory chip company I would make the largest I could and start selling them at the highest price I could for as long as I could until competition forces me to start lowering the price. Memory isn't a normal market its artificial and if you apply common sense to these kinds of things you are making an error. So I'm not doubting you I'm asking if you are applying common sense or if you know this for a fact. Yes its going to cost way more to make a tb then a gb card but the devil is in the details when you go to one or two sizes bigger not orders of magnitude. So if you own a memory company and you design the new tb card you don't want to start selling it right away at your normal margins or even selling it at all, you want to hold it as high as possible until competition forces you down.IE if I just made a new tb card and the largest size currently is 128gb, and if I could "detune" it down I might release to the market 512gb (detuned to 50%) as the max and tell consumers "we are working on a tb prototype for next year" then only release it's full potential when you have to. Business is tricky and when companies say "innovation" it's not a new invention it's a new scheme for more profit. In one of my businesses you could sell more if you offered a "buy one get one free" sale and just charge 80% more for the first one, rather then sell both at 20% off normal price. You are still giving the customer a deal, and still cutting 20% off your profits, but your volume increased hopefully more then 20%. When I used to sell Freon/r134a I would stock up at 80.00$ a bottle in winter then sell it for 120$ ($130 regular price) in the summer instead of trying to sell for $90.00 in the winter.

author: Cerebus
author_rank: Super Contributor
timestamp: September 06, 2018, 12:36:23 pm
content: Quote from: Tom45 on September 06, 2018, 03:15:01 amI'll happily stipulate that it didn't usestoredparity on the main memory, but I'd be horrified if it didn't use parity on the memory bus, I/O buses etc. Then again, the quotes from Cray above indicate a degree of arrogance and later chagrin, so it's quite possible.For those without physical experience of old machines, it wasn't uncommon for peripherals and even memory cabinets to be connected to the main processor by parallel buses implemented in relatively long runs of multicore cable - 10 metres for a cable to a card reader or tape drive or disk cabinet isn't unrealistic. Think lots of inductance, capacitance, crosstalk, exposure to interference and so on. Running those without some form of transmission error detecting is/was risky.

author: Cerebus
author_rank: Super Contributor
timestamp: September 06, 2018, 12:50:47 pm
content: Quote from: Beamin on September 06, 2018, 09:20:18 amWhere apparent common sense breaks down here is around the issue of feature size and yield. If you want to make chips with higher capacities you have to use smaller feature sizes on the chips. Smaller feature sizes increases the probability that tiny defects in the silicon wafer will break something on a given chip and reduce your yield. So it makes sense to design your circuit so that it is tolerant to having part of it broken - so that a 2 Gb chip is made up of two 1 Gb sub-chips, or four 512 Mb sub chips. That way if one sub-chip doesn't work, you can still sell the whole chip, but as a lower capacity part. The only things thatmustwork for each chip to be saleable is one of the sub-chips and the controller part that interfaces it to the outside world. That way instead of only making 2 Gb chips and getting a yield of say 20% and throwing 80% away, you get 20% full specification 2Gb chips, 50% 1Gb chips, 10% 512Mb chips and only 20% of dud chips that you have to throw away. (Numbers made up for example and bear no relation to actual yield figures, except by accident.)

author: David Hess
author_rank: Super Contributor
timestamp: September 06, 2018, 02:04:43 pm
content: Quote from: Cerebus on September 05, 2018, 10:48:28 pmI was referring to a modern design comparable to an existing processor. An Intel processor which currently has ECC and parity protection of its cache could be redesigned to operate its cache at a higher voltage and with more charge stored per bit to lower the soft error rate enough to do without memory protection but it would cost considerable power and performance and cost more due to increased area.They do not include ECC and parity unless the application requires it or it makes the processor better compared to the alternative of not including them.The Flash memory quality thing really bugs me. I have tested various USB memory sticks and they all suffered from poor retention even when new of months to barely a year. Meanwhile I have floppy disks which never lost their data and are completely usable.I would not mind so much if I knew who made good Flash memory devices.

author: Beamin
author_rank: Super Contributor
timestamp: September 10, 2018, 04:45:38 pm
content: Quote from: David Hess on September 06, 2018, 02:04:43 pmOLd floppy disks.I last remember using them to store .jpgs and with time they would start to get green blocks half way down the image. It was like my porn was self censoring.

author: wraper
author_rank: Unknown
timestamp: September 10, 2018, 05:38:28 pm
content: Spectek chips are not necessarily worse than Micron parts. Micron may just reject whole wafers or batches of packaged ICs due to poor yields and that goes to Spectek for further testing/recovery of good parts. But there is much lower confidence in component quality. Often you can see Spectek logo printed over micron branded IC.

author: Beamin
author_rank: Super Contributor
timestamp: September 13, 2018, 02:31:07 am
content: Quote from: blueskull on September 10, 2018, 04:59:29 pm

author: hamster_nz
author_rank: Super Contributor
timestamp: September 13, 2018, 05:43:18 am
content: If you want to see how fast a CPU can run, you don't have to test every part of the CPU, just the paths that have the worst timing at various process corners (eg. hot or cold, or more easily high voltage / low voltage...).I think it would be easiest to include a little test design somewhere on the die (e.g. maybe a ring oscillator), which you can easily access to quickly test the likely performance. This would allow you to sort the best from the rest without having to package and power up the entire die.Or maybe intersperse test patterns across a wafer, to see where things are better/worse than average.

author: Berni
author_rank: Super Contributor
timestamp: September 13, 2018, 06:01:01 am
content: The problem is that you actually have to test the operation of the CPU not just its speed.From the billions of transistors in there it only takes a single dead transistor to render a whole CPU core dead. So they have to run a test that exercises all parts of the CPU. Also its possible that only a few transistors ended up out of spec but still working and this results in extra timing issues on that signal path resulting in the CPU running fine at slow clock speeds but making a miscalculation at high clock speeds.A rough test of the CPUs functionality can be done pretty quickly. I would guess they have a quick die probe test of the wafers as they come off the production line to make sure all the major parts of the CPU work (Perhaps even having dedicated testing hardware on the die to help in this process). This would reduce waste of packaging and wire bonding dead dies. The full test where they "speed bin" them likely done when the chip is already in a LGA package and doubles as a final quality control test to make sure they don't ship a dead CPU from the factory.

author: Beamin
author_rank: Super Contributor
timestamp: September 13, 2018, 06:31:38 am
content: Quote from: Berni on September 13, 2018, 06:01:01 amThat's crazy a single dead transistor can do that. I have no idea how they get the silicon that pure besides make a huge crystal and stretch it. How do they dope things when the boron/doping agent is one part per million to make a hole when your transistor is a few hundred atoms?Think we will ever run out of sand to get silicon? Its like aluminum the only reason we don't make everything out of it is because it takes massive amounts of energy to reduce or remove oxygen from things.

author: Berni
author_rank: Super Contributor
timestamp: September 13, 2018, 06:52:21 am
content: Oh and on the topic. GPUs failures can be more interesting because those tend to mostly munch trough raw data and not make many decisions along the way or make much use of pointers. Because of that miscalculations or data corruption don't tend to crash it catastrophically. Such failures tend to quickly lock up or completely crash a CPU, but a GPU will often just happily keep on munching data and spitting out wrong results.The effect in the video is likely caused by one of the graphics RAM pins being shorted out or loosing connection so its leaving streaks in the video output and reading the model and texture data wrong.You can get a similar effect when overclocking a graphics card too far(Usually the memory clock), but its usually less predictable than this and it might still eventually crash completely.

author: wraper
author_rank: Unknown
timestamp: September 13, 2018, 08:22:31 am
content: Quote from: Berni on September 13, 2018, 06:52:21 amCertainly not that. You'd most likely have some line or boxed artifact pattern over the screen in windows (if it works at all) and as minimum have immediate GPU driver crash as soon as launching 3D application. Artifacts in the video are caused by very minor data corruption.

author: Cerebus
author_rank: Super Contributor
timestamp: September 25, 2018, 01:41:27 am
content: Apropos the earlier discussion about parity in the CDC 6600. I happened to trip across a book on the design of the CDC 6600 online. Itdiduse parity for the Extended Core Store. Not for the Central Store, at least there is no mention of it, but for the extended store most definitely. There is also mention of handling parity errors in the peripheral controllers.Quote from: Design of a Computer The Control Data 6600 J.E.Thornton p 54The book is availableherefor any computer architecture aficionados out there. For those of a logic design bent, it goes down to transistor and gate level explanations of some parts of the machine's design.

author: Tom45
author_rank: Frequent Contributor
timestamp: September 25, 2018, 05:06:11 am
content: Quote from: Cerebus on September 25, 2018, 01:41:27 amThanks for finding and sharing the link to that book. Truly a trip down memory lane for those of us that worked with the 6600 back in the day.The hand written note from Thornton's wife giving permission to scan and make the book available was interesting. He must have been pleased that people still remembered and appreciated the work he did on the 6600 and the book. He died just 3 years later in 2005.His Obituary:https://www.legacy.com/obituaries/twincities/obituary.aspx?pid=3033494

author: tooki
author_rank: Super Contributor
timestamp: September 27, 2018, 04:19:45 pm
content: Quote from: Beamin on September 13, 2018, 06:31:38 amWired just covered this earlier this summer:https://www.wired.com/story/book-excerpt-science-of-ultra-pure-silicon/

author: mac.6
author_rank: Regular Contributor
timestamp: October 15, 2018, 08:47:04 pm
content: Quote from: Berni on September 13, 2018, 06:01:01 amToday Design For Testing (DFT) is a big part of chip design.You don't test chip functionality (as it will be mostly impossible to design such test), but you link every part to form a chain and issue test vectors to check that everything is interconnected up as it is intended to be.This is way more faster and you can catch error deeply buried into the core logic.And sometimes a perfect wafer is build (100% yield), but it very rare (Intel did their first in 1989, an 8051 wafer).