30% Duty Cycle using VHDL - Page 1
Forum section: electronics / general

author: Jaiko007
author_rank: Newbie
timestamp: May 21, 2016, 09:33:51 am
content: Hello,I want to design 30% duty cycle using VHDL from clock frequency 50MHz and my frequency divider is 500Hz. Please someone help me. I need your help.Thank you.

author: ale500
author_rank: Frequent Contributor
timestamp: May 21, 2016, 02:41:39 pm
content: Assuming that you have a bit of background on VHDL, meaning you took some courses, or read a book and did some basic stuff, you may have seen that signals have a a duty cycle. Using the rule of 3, and counting how many 50 MHz periods fit in a 500 Hz period... you have your answer. How you write that in VHDL... that were the courses for, have fun !

author: rstofer
author_rank: Super Contributor
timestamp: May 21, 2016, 03:57:42 pm
content: Declare a counter wide enough to hold a count of 100,000 (50 million / 500)Declare another decimal counter (4 bits)Define a process the has as inputs, clk and resetCode:On the rising edge of clkif reset = '1' then reset both counters to 0elseif the large counter = 99,9999large counter becomes 0if small counter = 9small counter = 0elsesmall counter = small counter + 1end if;elselarge counter = large counter + 1;end ifend ifend process;output <= '1' when small counter = 1,2 or 3 else '0'The above pseudo code is deliberately not written in VHDL - that's your job. The idea is pretty simple, construct a counter to divide 50 million by 100,000 to get 500 Hz. Then divide the 500 Hz into 10 parts and set the output true for 3 of them.

author: nctnico
author_rank: Super Contributor
timestamp: May 21, 2016, 04:34:20 pm
content: Oh and extra points for using the proper arithmetic libraries and types!

author: AndyC_772
author_rank: Super Contributor
timestamp: May 21, 2016, 04:46:23 pm
content: Top tip for if you're going to filter the PWM output to generate a voltage level (ie. as a DAC)...If you use a simple counter, then the output filter needs to be able to strongly attenuate the PWM repetition frequency (500 Hz in this case).You can, however, produce an output which contains higher frequencies that may be easier to filter, and in an FPGA it's trivially simple to do and occupies no resources. The only proviso is that the PWM divider must be a power of 2, which is fairly common (though not in this case unless we can use 512 instead of 500).All you do is reverse the order of the bits in your counter before comparing it with the duty cycle register. So, if you have code along the lines of:Code:if counter > duty_cycle thenoutput goes low;elseoutput goes high;end if;... you can just replace it with:Code:if reverse_bits (counter) > duty_cycle thenoutput goes low;elseoutput goes high;end if;You need to implement your own reverse_bits function, of course, but that's trivial to do with a loop and an intermediate variable.This change produces a lot more transitions in the output stream, which means that a gentler filter is needed to produce an output with a given ripple. Depending on the clock rate and signal quality, it may also have a less beneficial effect on the linearity of the output, but that may not matter especially if it's part of a feedback system.I've used this technique to control the voltage output to a VCXO. It worked really well.

author: rstofer
author_rank: Super Contributor
timestamp: May 21, 2016, 05:25:55 pm
content: And it kind of matters what the 500 Hz is all about. The pseudo code I gave creates a divider to 500 Hz but the divide-by-ten and decoding results in a 30% duty cycle waveform at 1/10 of 500 Hz or 50 Hz. If the result is supposed to be 500 Hz then divide by 10,000 instead of 100,000.

author: Rasz
author_rank: Super Contributor
timestamp: May 21, 2016, 05:50:41 pm
content: Quote from: ale500 on May 21, 2016, 02:41:39 pmhe is right now, you are solving his class assignment

author: AndyC_772
author_rank: Super Contributor
timestamp: May 21, 2016, 05:59:48 pm
content: To be fair, we're quite deliberately avoidingsolvinghis class assignment. Nobody has actually written a single line of valid VHDL.

author: hamster_nz
author_rank: Super Contributor
timestamp: May 21, 2016, 06:57:23 pm
content: I saw a good answer to this exact question over athttps://forum.digilentinc.com/topic/2151-create-a-variable-duty-cycle-using-vhdl/QuoteI wonder if Dan was his instructor?

author: rstofer
author_rank: Super Contributor
timestamp: May 21, 2016, 10:48:55 pm
content: Quote from: AndyC_772 on May 21, 2016, 05:59:48 pmBut I did implement my suggested solution on an Arty board, just for giggles.Actually, people get their education wherever they can. I don't really have a problem posting the answer I would give. I just didn't have it available. If I provided the solution and theOP took the time to understand it, he would gain something at no cost.In general, I find that most forum participants don't want to do homework. To some extent, I agree. But the other part of me wants to give back the help I got from others.Now, if there is a forum POLICY that says no homework, I would abide by it. I have never read the T&C...

author: blackbird
author_rank: Regular Contributor
timestamp: May 22, 2016, 12:23:39 pm
content: Quote from: AndyC_772 on May 21, 2016, 05:59:48 pmCode:end if;I see some lines of valid VHDL

author: andre_teprom
author_rank: Regular Contributor
timestamp: May 22, 2016, 05:41:49 pm
content: Quote from: hamster_nz on May 21, 2016, 06:57:23 pmUnfortunately it is a quite common attitude of these members:Spread the same question at different forums, make others waste their time, and never come again:http://www.edaboard.com/thread354800.html#post1517849