The Cheapest FPGA Development Board? - Page 1
Forum section: electronics / general

author: Toney
author_rank: Contributor
timestamp: December 28, 2020, 08:44:51 pm
content: I was trying to buy a Lattice MachXO3D breakout board, but unfortunately they ran out. Now the price for the development boards has tripled. It was a great looking board that only cost ~16$.Is there something similar by other manufacturers? I need the board for converting a 88.2kHz, 32 bit audio stream with separate left, right, clock and channel streams to SPIDF (at least 88.2 kHz, 24 bits, preferably with capacity for 192kHz). This does not require much resources, all current FPGAs are probably capable enough, if not an overkill. However, the clock has to be multiplied, so a PLL with preferably x4 capability is preferred, and there needs to be at least four inputs and an output. I would like to mount the SPIDF output direct to the board so this requires some space for few resistors also to get the output to the correct range.Are there any boards you would suggest?

author: langwadt
author_rank: Super Contributor
timestamp: December 28, 2020, 09:08:07 pm
content: Quote from: Toney on December 28, 2020, 08:44:51 pmQMTECH Xilinx FPGA Spartan6 XC6SLX16 is about that price on aliexpress

author: Toney
author_rank: Contributor
timestamp: December 28, 2020, 09:16:46 pm
content: Quote from: langwadt on December 28, 2020, 09:08:07 pmThank you for the suggestion.Do I recall correctly that Xilinx boards require a programmer though?

author: langwadt
author_rank: Super Contributor
timestamp: December 28, 2020, 09:26:20 pm
content: Quote from: Toney on December 28, 2020, 09:16:46 pmyes, a Xilinx programming cable (clone) is about the same as a board

author: Canis Dirus Leidy
author_rank: Regular Contributor
timestamp: December 28, 2020, 10:18:22 pm
content: Another variant:EP4CE15 core boardfrom QMTech ($19 without shipping) plusChinaBlaster programmer(approx. $3 or $4).

author: Toney
author_rank: Contributor
timestamp: December 28, 2020, 10:31:13 pm
content: Quote from: Canis Dirus Leidy on December 28, 2020, 10:18:22 pmThank you, I will check it out in more detail.I forgot to say, the board should be able to be powered without an adapter or USB, direct from a PSU.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 28, 2020, 10:55:21 pm
content: QMTECH boards are typically powered externally. (Power jack.)But given your project, I would also suggest an Upduino (iCE40 UP).https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/Probably more than enough for what you described, and includes the programmer.

author: Toney
author_rank: Contributor
timestamp: December 29, 2020, 02:50:14 am
content: Quote from: SiliconWizard on December 28, 2020, 10:55:21 pmOne more excellent suggestion. Smaller is certainly better, the only thing I am a bit worried about is whether the SPIDF connectors (optical/RCA) will fit on the board. For reference here is the RCA connector, optical transmitter is probably approximately similar sized, I am not sure yet which I will mount.

author: langwadt
author_rank: Super Contributor
timestamp: December 29, 2020, 03:07:36 am
content: if you are feeling adventurous,https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html

author: Toney
author_rank: Contributor
timestamp: December 29, 2020, 03:16:40 am
content: Quote from: langwadt on December 29, 2020, 03:07:36 amYes, I saw this one, the price quite likely can't be beat. Unfortunately, it's USB power only as I understand. Also, the documentation that I found was non-existent, which may cause a lot of trouble.

author: langwadt
author_rank: Super Contributor
timestamp: December 29, 2020, 03:20:22 am
content: Quote from: Toney on December 29, 2020, 03:16:40 amyou can power if from a psu, as long as it is 5V

author: Toney
author_rank: Contributor
timestamp: December 29, 2020, 04:04:35 am
content: Quote from: langwadt on December 29, 2020, 03:20:22 amThis is why the lack of documentation may be a problem. At a price cheaper than a hamburger I still almost want to dare.

author: BrianHG
author_rank: Super Contributor
timestamp: December 29, 2020, 04:20:33 am
content: Quote from: blueskull on December 29, 2020, 04:10:16 amHe need not go that high quality, however, even quality linear and cubic interpolation still require a number of multiply-add modules. Also, for the higher domain filters, make sure you have access to floating point multiply-add-divide as well some trig and root functions.Thankfully, Intel finally opened up all these floating point functions for free in Quartus. A decade ago, we had to pay for many of these as well as more of the advanced ones. Even the basic FIR filter compiler is now available for free.

author: Foxxz
author_rank: Regular Contributor
timestamp: December 29, 2020, 05:14:42 am
content: Excuse my ignorance on the subject. Going from 32bit audio to 24bits should be easy by just dropping the 8 LSBs. Optionally use them to decide if you want to round up the remaining MSBs.Going from 88.2khz to 192khz is going to be more difficult.192khz / 88.2khz = 2.1768707482 * 88.2khz = 176.4khz192khz - 176.4khz = 15.6khz1s / 15600hz = 0.000064103sSo I would start by sending every sample twice. And then do the calculation to slip in an extra third sample every 0.000064103 seconds. Should be easy to figure out based on your clock speed.Its not an upconversion. It won't make your audio sound any better like some of the more complicated schemes proposed by others might. Its mainly just a format conversion.

author: langwadt
author_rank: Super Contributor
timestamp: December 29, 2020, 05:17:15 am
content: Quote from: Toney on December 29, 2020, 04:04:35 amthere's a datasheet on that page with pinout showing two 5V pins

author: Foxxz
author_rank: Regular Contributor
timestamp: December 29, 2020, 05:28:18 am
content: Quote from: blueskull on December 29, 2020, 05:19:35 amCould you point me to a reference on the subject? I know DACs can be a tad more complicated but when I think of a DAC playing a low sample rate VS a DAC playing a high sample rate the low sample rate is simply holding the voltage at the specified level for a longer period of time.

author: langwadt
author_rank: Super Contributor
timestamp: December 29, 2020, 05:50:36 am
content: Quote from: Foxxz on December 29, 2020, 05:28:18 amholding the voltage at a specific level for a sample period (zero-order hold) is part of how the DAC (usually) worksthere's no DAC involved as long as you are just massaging numbers, you have discrete values at discrete timesthis has a very brief intro:https://homes.esat.kuleuven.be/~maapc/static/files/SYSTHEORY/Slides/Lecture13/Lecture13-Discretization%20and%20reconstruction%20of%20signals.pdf

author: BrianHG
author_rank: Super Contributor
timestamp: December 29, 2020, 06:20:28 am
content: Quote from: blueskull on December 29, 2020, 05:19:35 amWith Foxxz's comment, it sounds like simple resampling + a tuned low pass filter would be enough for him. This is not absolute junk, but it's a beginner's step and a properly tuned low pass filter will reject a chunk of the nasty band. Higher quality output filters would just begin to mimic existing DAC output analog reconstruction filters.Unfortunately, even a 1.50$ 32bit stereo audio DAC from TI has a higher quality internal up-sampling when it takes in 16/24/32 bit 44.1KHz source and up-samples the source data internally driving it's dac at 384KHz. This price-to-up-sampling quality will not be matched on a 1$ FPGA, not to mention the needed bootprom, 32bit DAC and powersupply which doesn't exist for anything less than at least 10$.This project should be taken as a FPGA learning experience and you should attempt to at least match the up-sampling quality of the bottom end TI DAC's internal one. This means full processing as blueskull has been touting and this also means an FPGA with some good strong core capabilities + a lot of work.If you want just the up-sampling quality, there are components much cheaper and all the mathematics have already been done. If you want the learning experience, go with the FPGA and make sure you can have some PC connectivity to sniff the data & set some controls. IE, at lease make sure your FPGA board has at least and additional USB/RS232 interface.

author: Toney
author_rank: Contributor
timestamp: December 29, 2020, 09:35:02 am
content: Quote from: blueskull on December 29, 2020, 04:10:16 amI am not changing the sample rate, it's a simpler format conversion from some ancient I2Sish (in spirit) standard to SPIDF. The clock is multiplied since the clock for SPIDF needs to be faster as there are two channels.

author: BrianHG
author_rank: Super Contributor
timestamp: December 29, 2020, 02:11:53 pm
content: Quote from: Toney on December 29, 2020, 09:35:02 amIf you plan on making a PCB for this in the future, and all you want to do is format conversion, an Intel MAX10 fpga is useful. You get 2 PLLs for increasing the source clock frequency (you will still need a trick or 2 to lift up a ~1MHz clock to the internal FPGA's minimum PLL 10MHz clock, but this can be done with a local crystal oscillator and using both PLLs), and the FPGA operates without a bootprom and only requires 1 single supply 3.3v. It's available in QFP 144pin or smaller 32pin BGA. They are not the cheapest at ~7$ each and overkill for your app.

author: Toney
author_rank: Contributor
timestamp: December 29, 2020, 04:37:10 pm
content: Quote from: blueskull on December 29, 2020, 02:27:13 pmIIRC, the jitter is not too much if it is within quarter of the unit interval. However, even at 88.2 kHz the clock needs to run at 88200*32*2*2 = 11.2 mHz. I believe on that board the crystal is not fast enough for the trick. What is the problem with using a PLL?Below is the code, where I assume having access to a double rate clock. Even then, SPIDF runs at double the rate by default because of the biphase-mark encoding and there are two channels, so the clock is four times faster (and if I wanted to get it to double that then 8x). However, it is possible to also use both the up and down tick of the clock, halving the requirement. Whether this actually works in practice is a other question, but the code below is implemented this way, it is assumed Clock2 runs at twice the frequency of Clock1 (the retrieved clock - which runs at ~3mHz).Quote

author: BrianHG
author_rank: Super Contributor
timestamp: December 29, 2020, 04:39:59 pm
content: Do you have access to the CPU's clock generating the I2S signal. This may be at a higher frequency, then all you need to do is divide.Not every FPGA has a PLL.Altera/Intel FPGA's internal PLLs need at least a 5MHz source clock to function within spec. Output can be as high as ~750MHz. With trickery, you can run them with a source clock lower than 5MHz.

author: Toney
author_rank: Contributor
timestamp: December 29, 2020, 04:57:25 pm
content: Quote from: BrianHG on December 29, 2020, 04:39:59 pmNo, unfortunately. The ~3 MHz (88200*32) clock needs to be multiplied.

author: BrianHG
author_rank: Super Contributor
timestamp: December 29, 2020, 05:05:28 pm
content: Quote from: Toney on December 29, 2020, 04:57:25 pmFind an FPGA with a PLL which can start as low as 3MHz. Or, use an XOR gate (can be one inside the FPGA) with an LC delay line from 1 input to the next to double your source 3MHz to 6MHz. (Note, without re-PLLing the 6MHz output of the XOR gate, that 6MHz won't have a nice 50/50 duty cycle unless the LC delay line has dead perfect tuning.)

author: Toney
author_rank: Contributor
timestamp: December 29, 2020, 05:18:31 pm
content: Quote from: BrianHG on December 29, 2020, 05:05:28 pmSo the clock is 2.82MHz. Turns out the $5 FPGA has the low limit of 3MHz, do you recon it will work mildly out of spec?https://alcom.be/wp-content/uploads/2018/09/GOWIN_100918_DS100-1.2E_GW1N-series-of-FPGA-Products-Data-Sheet-1.pdf

author: BrianHG
author_rank: Super Contributor
timestamp: December 29, 2020, 05:24:44 pm
content: Sorry, I never used Gowin.The limitation is usually set by the compiler & trying to trick the Compiler/FPGA can lead to PLL instability.

author: Foxxz
author_rank: Regular Contributor
timestamp: December 29, 2020, 06:00:28 pm
content: Thank you to everyone that took the time to explain the nuances of resampling, etc. That was helpful to know.

author: radiolistener
author_rank: Super Contributor
timestamp: December 29, 2020, 07:03:21 pm
content: Quote from: Foxxz on December 29, 2020, 05:14:42 amThese 8 LSB bits contains significant information which will be required for better quality upsampling from 88.2 to 192 kHz. These bits contains important information required for good signal reconstruction at higher sample rate.Quote from: Foxxz on December 29, 2020, 05:14:42 amUpsampling requires interpolation, if you just copy previous sample, you will have bullshit sound. And interpolation should use all 32 bits of original stream on the input.At a glance, there is needs upsample interpolation from 88.2 kHz to 28224 kHz and then downsample to 192 kHz.

author: Toney
author_rank: Contributor
timestamp: December 29, 2020, 10:48:11 pm
content: Quote from: Foxxz on December 29, 2020, 05:28:18 amCheck out the sampling theorem. Convolving by sinc functions gives mathematically "perfect" reconstruction (IE. with the same Fourier transform up to the prior Nyquist frequency and then all zeroes). So a sinc of n points is the usual choice for good quality interpolation - very expensive of course - and also not causal. A spline of four points can also be used, and linear interpolation works for 2 points. You can google the effect on Fourier transform of these, it's not very good.Holding points for two samples seems the same as convolving by a rectangle - which is how digital already works. As such yes the rate is faster, but now you have the mirroring of frequencies from the Nyquiest so the low pass filtering would still be needed (and indeed the sinc interpolation is a perfect low pass filter).The above is only the starting point, I am sure engineers have developed interpolation methods that work better in practice.

author: Toney
author_rank: Contributor
timestamp: December 29, 2020, 11:42:20 pm
content: Quote from: BrianHG on December 29, 2020, 05:24:44 pmInstalling the software. Unfortunately, I have not seen anything in the documentation yet on how to use the software, let alone set the PLL. But, according to the documents the oscillator can be set to frequency of 100MHz (or at least 50MHz), also enough to double the clock with acceptable jitter. If the PLL worked out of spec, that would be fantastic though.The documentation I am reading is for the GWIN-1, I wonder what the "LV" stands for in GW1N-1-LV.

author: langwadt
author_rank: Super Contributor
timestamp: December 29, 2020, 11:51:46 pm
content: Quote from: Toney on December 29, 2020, 11:42:20 pmI'd guess Low Voltage, 1.2V core voltagethis might help,https://www.gowinsemi.com/upload/database_doc/39/document/5bfcff2ce0b72.pdf

author: asmi
author_rank: Super Contributor
timestamp: December 30, 2020, 12:00:12 am
content: This thread is a good example of how NOT to go about FPGA project. What you should do is determine approximately how much of FPGA resources (LUTs, FFs, memory, DSP, etc.) your design will need, and only then proceed with selecting device and a board, instead of picking up a random board and trying to cram you design into it somehow. You've got to remember that FPGA and devboard is just a tool, so you pick the right tool for the job, and not take out a random tool and then try to use it for everything you can think of.

author: Foxxz
author_rank: Regular Contributor
timestamp: December 30, 2020, 12:52:37 am
content: Quote from: asmi on December 30, 2020, 12:00:12 amHe could have probably done it with a raspberry pi zero and a few command line programs strung together but where is the learning experience in that?

author: Toney
author_rank: Contributor
timestamp: December 30, 2020, 01:27:22 am
content: Quote from: asmi on December 30, 2020, 12:00:12 amI see your point. However, I am quite the noob and it's unlikely that I get all the details down even if I wanted. Nonetheless, here is the summary:- PLL (2.82MHz -> x4)- External power- Enough resources to run the code above. The report below.HDL Synthesis ReportMacro Statistics# ROMs : 18x6-bit ROM : 1# Adders/Subtractors : 101-bit adder : 510-bit adder : 13-bit adder : 15-bit adder : 16-bit adder : 2# Counters : 33-bit up counter : 16-bit up counter : 2# Registers : 1431-bit register : 1210-bit register : 12-bit register : 1285-bit register : 16-bit register : 1# Comparators : 25-bit comparator greatequal : 15-bit comparator less : 1Rasberry pi zero is an interesting option, too. I am not sure it's able to read four 88.2kHz streams and maintain the required precision though. I did look at some MCUs and that was the problem. FPGA seems to lend itself to the task more naturally.

author: BrianHG
author_rank: Super Contributor
timestamp: December 30, 2020, 01:52:28 am
content: If the gowin PLL wont cleanly lock onto your '2.82MHz' clock, just use 2 inputs programmed into a combinational XOR gate with an output feeding back into the gowin's CLK input. All you need is the right inductor/cap/resistor between the 2 inputs & you will have a 5.64MHz clock which it can safely lock onto. If you need tuning, the cap can be a varicap. You tune with a scope on the output looking for an approximate 50/50 duty cycle.There are other ways to do this as on another FPGA thread on this board, I've successfully made a an Intel FPGA's PLL lock onto a 15.7KHz source clock with a 42MHz output with a jitter less than ~ +/-250ps using 2 PLLs in the FPGA, if I recall.

author: langwadt
author_rank: Super Contributor
timestamp: December 30, 2020, 01:55:01 am
content: Quote from: BrianHG on December 30, 2020, 01:52:28 amthe pll might not like the jitter from using both edges, though the data sheet doesn't seem to mention it

author: BrianHG
author_rank: Super Contributor
timestamp: December 30, 2020, 01:57:49 am
content: Quote from: langwadt on December 30, 2020, 01:55:01 amI know in the Intel FPGAs, you can program the PLL loop filter bandwidth down to ~500KHz which you smear that out.Noise shouldn't be too bad as the jitter will only be really amplified if the source clock has jitter on one edge.

author: Toney
author_rank: Contributor
timestamp: December 30, 2020, 11:05:14 pm
content: I have been waiting for the license for the software, I believe they email it. I did not see any information on how to call the PLL in the documentation, but perhaps it is self-evident once the software becomes functional.

author: langwadt
author_rank: Super Contributor
timestamp: December 31, 2020, 03:11:16 am
content: Quote from: blueskull on December 31, 2020, 02:37:42 amlol, that doesn't sound sketchy at all

author: asmi
author_rank: Super Contributor
timestamp: December 31, 2020, 03:16:45 am
content: Quote from: langwadt on December 31, 2020, 03:11:16 amYea, I thought that tooBut even if you ignore that, there remains a practical question of what do you if you have other software that is tied to your current MAC address. Quite a bit of commercial software does that.

author: langwadt
author_rank: Super Contributor
timestamp: December 31, 2020, 03:36:59 am
content: Quote from: asmi on December 31, 2020, 03:16:45 amcan't have multiple interfaces (possibly virtual) with the needed mac addresses ?

author: asmi
author_rank: Super Contributor
timestamp: December 31, 2020, 05:09:38 am
content: Quote from: langwadt on December 31, 2020, 03:36:59 amNope, I don't get to control which interface licensing software uses. It always picks physical interface at least on my PC, even though I've got few virtual NICs as well.