PCB design question (crystal end ATmega) - Page 1
Forum section: electronics / general

author: tiger80
author_rank: Contributor
timestamp: March 28, 2024, 11:12:52 pm
content: Hello everyoneOk so I have finished laying out a board. I have an ATMega128A running with a 14,7456MHz crystal. The board has two layers and I have chosen the top layer and bottom layer as the ground plane (GND).Following design guidelines, I have kept the trace length between the crystal and the AVR minimal. Take a look at the layout and suggest any improvements if you can and also be sure to point out the faults.Sorry for my bad English

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 29, 2024, 02:30:00 am
content: I'm not sure a HC-49S-SMD is the cheapest/smallest anymore in 2024.Of course, if you have shiploads in stock, use them up

author: pcprogrammer
author_rank: Super Contributor
timestamp: March 29, 2024, 07:26:06 am
content: You can clean it up by putting the two capacitors on the same y location and ground them on opposite sides. Then the trace from the crystal won't pass underneath the capacitor and takes less space. I also don't think you need to block out the ground plane underneath the crystal.Another issue with SMD and a top ground plane might be with reflow based soldering where the heat dissipation for the pads of a component differs. Tombstone effect may happen. Not a problem when hand soldering.

author: tiger80
author_rank: Contributor
timestamp: March 29, 2024, 11:27:51 am
content: I will solder the PCB by hand.I changed the crystal and the arrangement of the capacitors.Can capacitors C5 and C8 be arranged this way?Where to place the ground grommets at the bottom?

author: pcprogrammer
author_rank: Super Contributor
timestamp: March 29, 2024, 11:47:48 am
content: Looks better, but why the blocking of the ground plane? I don't think it will add to much capacitance with the crystal traces fully surrounded by the ground.

author: bookaboo
author_rank: Frequent Contributor
timestamp: March 29, 2024, 01:02:29 pm
content: If you must have a 2-Layer solution then I'd flood bottom with GND and do everything else on the top, but you have to be very careful not to break the GND plane.Anything that needs GND just drop a via.Much easier if you can go 4-Layer with a SIG - GND - GND - SIG stackup (treat power and sig the same).Flooding the areas between signal traces won't be necessary with this stack-up.Lots of good youtube material on this from Robert Feranec, Phil's Lab and Zach Peterson.

author: temperance
author_rank: Super Contributor
timestamp: March 29, 2024, 02:11:42 pm
content: The idea is to place a guard trace around the oscillator signals to avoid nearby signals from disturbing the oscillator. A plane is ok but adds extra stray capacitance if the plane to signal clearance is set to minimum. I just use a thin trace with the largest clearance possible and no return currents are allowed to flow trough any of the via's or the trace itself.

author: tiger80
author_rank: Contributor
timestamp: March 29, 2024, 02:43:21 pm
content: Thank you very much for all your suggestions. They are very valuable to me. I took your suggestions into account and drew two more variants: pcb3 and pcb4.Which one will be the best?Robert Feranenc on YouTube says that the paths from the crystal to the microcontroller must be as short as possible.

author: temperance
author_rank: Super Contributor
timestamp: March 29, 2024, 02:57:38 pm
content: PCB3 is better than PCB4 because the stray capacitance to the plane is lower in PCB3. But C5 en C8 could be placed a little further apart in order to decrease the capacitance in parallel with the XTAL.A note about disturbance: a little disturbance is fine for a simple controller. But if the controller contains an RF section who's clock is derived from the XTAL in question then the rule to not disturb the XTAL must be implemented as best you can.

author: tiger80
author_rank: Contributor
timestamp: March 29, 2024, 03:17:37 pm
content: Ok, so we stay with option number 3.But which way should I move capacitors C5 and C8?

author: temperance
author_rank: Super Contributor
timestamp: March 29, 2024, 03:57:03 pm
content: That's easy: you must decrease the capacitance sow the distance must be increased.

author: tiger80
author_rank: Contributor
timestamp: March 29, 2024, 08:14:02 pm
content: Is this the arrangement you had in mind?Now is good?

author: temperance
author_rank: Super Contributor
timestamp: March 29, 2024, 09:29:15 pm
content: C5 should go to the left. C8 can stay where it is.

author: tiger80
author_rank: Contributor
timestamp: March 29, 2024, 09:50:09 pm
content: I corrected it.Will it be okay now?

author: pcprogrammer
author_rank: Super Contributor
timestamp: March 30, 2024, 07:15:52 am
content: Just to learn for myself, is there a reason for separating the ground plane near the crystal from the rest of the top ground plane?I can understand keeping it away from the two signal traces to reduce stray capacitance, but why the separation.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 30, 2024, 09:24:47 am
content: Don't worry about it.Like -- at all!Place the components, surround with ground, drop a few stitching vias, keep traces a modest distance away from them, and you're done.Your first layout is perfectly fine, as far as what is shown. If you want to avoid crossing the trace with one capacitor, rotating the one is fine. If this is a commercially fabbed board, traces under components will not violate any clearance issues, and soldermask will be effective insulation for this voltage. Ground keepout is unnecessary: you're literally putting extra capacitors to ground around the crystal, what difference would another ~0.8pF or so make to it? But neither will it hurt, so my above statement remains true.---I'm always a bit amused by crystal layout, because it's such a common, and frequent, topic for bikeshedding.Bikeshedding:definitionally--see the responses in this thread. Do this, do that, move components here, put traces there. It'sentirely superficial:: what the bike shed should look like, put this siding here, put that window there, paint it with this or that color.No one is discussing, or has yet even mentioned, any of the hard questions, like: "Where do we put the bike shed?" "How big should it be?" "How much will it cost and how will we budget for it?" "What permits if any do we need to build it?" That is: any matters of material importance, functionally necessary to actually build a bike shed.Hence the origin and meaning of this term. I don't think there was a literal, formative instance of a proverbial bike shed, but the example rings true time and again, as individuals or groups debate the easy and superficial aspects of a problem and leave the hard and awkward questions unturned.Nothing that has been mentionedwill have a measurable impact on EMC performance, or more than a dB's worth. It's just not that important of a thing to spend so much time or words on, and more importantly: anything that would make a difference, is an actualhard problem-- you need detailed datasheets for both MCU and crystal (and often, the MCU datasheet doesn't provide the necessary information to determine this anyway..!), sensitive probes to measure and verify operation, and other test equipment to evaluate EMC (e.g. RF amplifiers, signal generator, spectrum analyzer, probes and antennas, etc.). Meaningful effort is challenging, and poorly understood -- not to say there aren't those who understand how to design and test these circuits, or that it's particularly difficult when given the tools to do so, but merely that the knowledge itself is poorly distributed, few know it -- few need to know it, because crystals generallyjust work-- and so, responses largely avoid discussing anything of actual consequence, any elephants in the room.Finally, notice how 1. there is wildly insufficient information to make any kind of statement on EMC of this PCB to begin with (we see only a tiny excerpt, no idea what signals are and where they're going, how the rest of the board is laid out, what it connects to, the full schematic, and so on), and 2. no one has offered any quantitative -- not even qualitative, for that matter -- assertions about potential improvements or tradeoffs -- in terms of emissions, susceptibility, interference, jitter, you name it. Anything, that would be material to the topic, what it is you're actually accomplishing by moving things around, if at all -- and we can measure these, and while it's maybe not easy to calculate those outward effects from say board geometry alone, at least some ballpark figures can be given from experience, or by rough analysis.So you can see how this behavior can be problematic, creating extra busy-work when none is required, and distracting from issues of importance.---Now, I don't write this as an admonishment to any particular posters in this thread (but, if  can accept this as constructive criticism, then please, by all means-), but more as a warning to you [the OP], you will find this anti-pattern time and again in the world of human endeavors, and it will be up to you to cut through the smoke screen and realize for yourself when and where a lack of substance exists. And, I appreciate that  have so accurately portrayed this behavior, and created this teachable moment.On a similar note, I wrote this a bit ago:https://electronics.stackexchange.com/a/705405/311631you may find the comments on layout in general, and avoiding early optimization, and analysis paralysis, of interest.Tim

author: tiger80
author_rank: Contributor
timestamp: March 30, 2024, 06:45:29 pm
content: I'm already explaining what will be on my PCB.I didn't show you the design of my PCB because it is in the design phase. When I finish, I will show the project.The PCB will have 2 layers top and bottom. Both layers will be GND sewn together with many vias. On my PCB there will be an ATmega128A powered by +5V. SPI comes out of the MCU to the LCD connector. EEPROM 24C04 and a connector to ADUM1250 will be connected to I2C. My board will also have a Bluetooth module connected to the MCU via UART. There will be 2 encoders, several buttons and a 1-wire connector for DS18B20 connected to the PCB. Additionally, I plan to place an opamp with a transistor and several passive elements on this PCB to control the 12V fan. Two voltages will be supplied to the board, +5V and +12V for the fan and opamp.The PCB is not commercial. It will be for my use only.The arrangement of the crystal and capacitors from my first post was taken from "AVR186: Best Practices for the PCB Layout ofOscillators." Based on this study and several PCB designs found on the Internet, I came up with the idea of covering the crystal with a gnd island.My pcb will be near the 24V/7A transformer.

author: pcprogrammer
author_rank: Super Contributor
timestamp: March 30, 2024, 07:43:10 pm
content: Quote from: tiger80 on March 28, 2024, 11:12:52 pmJust out of interest, why the 14,7456MHz? Do you need it for a specific serial baud rate?

author: tiger80
author_rank: Contributor
timestamp: March 30, 2024, 08:06:48 pm
content: Yes.I think I will give up this separated island and place the crystal as close as possible, and place the capacitors on the paths to the MCU.So far, this has always worked in my other projects.The only problem is that next to the XTAL pins there are I2C and UART pins. And I2C paths will be run in the immediate vicinity of the crystal.What do you advise to do in this situation?In the article "AVR186: Best Practices for the PCB Layout of Oscillators." writes: "In case there is only one PCB layer, it is recommended to place a guard ring around the oscillator components and to connect it to the oscillator ground pin"I have 2 layers of mass, so I don't have to make a guard ring...Honestly, I'm lost and I don't know anything anymore...Or maybe we should completely avoid pouring GND on the TOP layer? What do you think?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 30, 2024, 10:57:01 pm
content: Quote from: tiger80 on March 30, 2024, 08:06:48 pmNormally, you try and have shield gnd trace or pour between CLK and any other aggressor signals.XTAL layouts are quite forgiving, I usually go for smallest area & shortest stubs, as there are other parts needing space too.

author: tiger80
author_rank: Contributor
timestamp: March 30, 2024, 11:40:41 pm
content: I did it as in the attached picture. The paths are symmetrical. So it will be fine?I have one more question - should I give up the ground plane on this PCB on the top layer? The mass plane would be uniform only on the bottom layer. How will it be better?

author: pcprogrammer
author_rank: Super Contributor
timestamp: March 31, 2024, 06:22:14 am
content: You are overthinking it.Like T3sl4co1l wrote, "don't worry about it", attached is a screenshot of a working PCB with a STM32F103C8T6 on it and an 8MHz through hole crystal. No top ground pour.Sure there are no switching signals nearby but on such short traces it won't be a problem.The guard ring mentioned in AVR186 is just a ground trace next to the signal lines and going round the crystal to shield if from other traces, which is basically the same as your ground pour.

author: aliarifat794
author_rank: Regular Contributor
timestamp: April 02, 2024, 10:33:54 am
content: What are C5 and C8 for? Are these decoupling capacitors? If yes, what are the values?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 02, 2024, 10:52:10 am
content: Crystal loading capacitors, typically 10s of pF.Tim