Vivado not trying hard enough? - Page 1
Forum section: electronics / general

author: Fantasma25
author_rank: Regular Contributor
timestamp: June 21, 2016, 02:12:27 pm
content: Hi all. At my job I'm currently working on huge multi-fpga designs with Synopsys tools for synthesis and Vivado for Place & Route. To run the jobs, we have dedicated linux systems that we request on demand based on our requirements (Num of cores, memory, etc.). Everything was ok until a couple of weeks ago. Then, more people were added to the project and the computing resources that we could get, started to decrease (Before, we could get 5 or 6 cores, and now we get 2 or 3). Then, around the same time, we started getting congestion errors in the Routing stage of Vivado. As far as I was concerned if Vivado had less computing resources it would only take longer to run, but now it seems that it also tries less alternatives and so it causes congestion errors.Do you know if this is true? Or my case is just a big coincidence?Thanks!

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: June 21, 2016, 03:48:26 pm
content: It's quite likely that it adjusts what effort it considers to be reasonable to suit the platform it's running on - there's probably an option buried somewhere.Maybe run the same design with different resource levels and look at the reports for a clue as to what may be happenning

author: nctnico
author_rank: Super Contributor
timestamp: June 21, 2016, 04:12:40 pm
content: I have been meaning to start a thread about Xilinx routing options for a while. In my experience the Xilinx map and place&route are very bad at determining how to best fit a design into an FPGA. I often need to tweak the placer cost value in order to make the design route. Tweaking this value can be the difference between the computer running for 8 hours and not get the design routed and routing the exact same design within 5 minutes with all constraints met.

author: Fantasma25
author_rank: Regular Contributor
timestamp: June 21, 2016, 04:34:02 pm
content: Quote from: nctnico on June 21, 2016, 04:12:40 pmThat sounds interesting. One of the bigger pains of our designs is that they take like 6-7 hours to run (just for the P&R stage). How do you tweak the placer cost?

author: nctnico
author_rank: Super Contributor
timestamp: June 21, 2016, 04:50:36 pm
content: Quote from: Fantasma25 on June 21, 2016, 04:34:02 pmThe placer cost settings are in the map settings in ISE. I don't know where they put them in Vivado but I guess under the hood Vivado uses the same command line tools for the actual synthesis, linking (ngdbuild), map, place&route, etc.

author: Fantasma25
author_rank: Regular Contributor
timestamp: June 21, 2016, 04:56:34 pm
content: Quote from: nctnico on June 21, 2016, 04:50:36 pmIt appears that cost tables are not available in Vivado (only ISE) due to the way Vivado's algorithms work. Apparently the closest thing available are the directives, which haven't completely solved my problem so far

author: rstofer
author_rank: Super Contributor
timestamp: June 21, 2016, 05:31:48 pm
content: What did Xilinx say when you asked?Somebody over there must know how Vivado works...

author: nctnico
author_rank: Super Contributor
timestamp: June 21, 2016, 05:43:26 pm
content: I suppose the OP already found this:https://forums.xilinx.com/t5/Implementation/implementation-error-due-to-routing-congestion/td-p/474578In really though cases it might be necessary to look at how the design got routed using the floorplanner and lock elements like blockrams or DSP slices to certain locations to steer the mapping process.