Alternatives to always@(posedge clk, negedge clk) - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: February 24, 2021, 03:51:53 am
content: How would usingthis Dual Edge FFresult in glitches ?Could anyone advise other alternatives circuit to trigger on bothposedge clkandnegedge clkin the case of DDR memory?Note: clk signal being 90 degrees phase-shifted is similar tonegedge clk

author: Daixiwen
author_rank: Frequent Contributor
timestamp: February 24, 2021, 08:25:25 am
content: No as explained in the post, this type of circuit will not result in glitches because each flip flop switch at a different phase. The problem with always@(posedge clk, negedge clk) is that it is usually not recognized by the synthesizer, as it can only synthesize flip flops with one clock input. That's why you need to go through the example code with two flip flops, one on each edge of the clock, and combine the results. You need also to be very careful in how you describe the timing requirements for the pin.Which target are you using? Most FPGA vendors provide small I/O blocks that you can use in your code to describe DDR I/O. They only use one clock phase and two I/O bits, one corresponding to the rising edge of the clock and one for the falling edge. This is preferable because you are guaranteed to use the dedicated DDR hardware on the FPGA, if available, will get better timing and it will make your code easier because you only have to deal with one clock edge.

author: BrianHG
author_rank: Super Contributor
timestamp: February 24, 2021, 09:15:02 am
content: Just PLL the FPGA at 2x. Now everything is 1 single posedge clock, better refined IO performance and no glitching.

author: promach
author_rank: Frequent Contributor
timestamp: February 24, 2021, 11:10:57 am
content: Wouldthis circuitwork well to emulatealways@(posedge clk, negedge clk)?Code:// Clock divider// 1. for developing correct logic first before making the DDR memory controller works in higher frequency,// 2. to perform 90 degree phase shift on DQ signal with relative to DQS signal during data writing stage// 3. to perform 180 degree phase shift (DDR mechanism needs to work on both posedge and negedge clk)// when we have two consecutive data// See https://i.imgur.com/dnDwZul.png or// https://www.markimicrowave.com/blog/top-7-ways-to-create-a-quadrature-90-phase-shift/// Might use https://stackoverflow.com/a/50172237/8776167 in later stage of the projectlocalparam DIVIDE_RATIO = 4;reg clk_strobe;reg [$clog2(DIVIDE_RATIO):0] clk_count;always @(posedge clk)beginif(reset) clk_count <= 0;else clk_count <= clk_count + 1;endalways @(posedge clk)beginif(reset) clk_strobe <= 0;else clk_strobe <= (clk_count == DIVIDE_RATIO);endreg clk90_strobe;reg [$clog2(DIVIDE_RATIO):0] clk90_count;always @(posedge clk)beginif(reset) clk90_count <= 1;else clk90_count <= clk90_count + 1;endalways @(posedge clk)beginif(reset) clk90_strobe <= 0;else clk90_strobe <= (clk90_count == (DIVIDE_RATIO + 1));end

author: langwadt
author_rank: Super Contributor
timestamp: February 24, 2021, 11:34:12 am
content: https://xyproblem.info/

author: promach
author_rank: Frequent Contributor
timestamp: February 24, 2021, 11:52:59 am
content: @langwadt So, what is your suggested solution to my original question of this thread ?

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 24, 2021, 02:12:49 pm
content: I found a flip flop style "both edge" circuit in a patent once, and have used it ever since. You take the clock input to an XOR gate. The output of the XOR gate clocks the flip flop which is in divide by 2 mode, so the data input comes from the opposite of the Q output. The output of the flip flop goes to the other input of the XOR.When the input to the XOR changes the output goes high, clocks the flip flop, which then changes it's state to match the other XOR input, so the output of the XOR goes low. It always works because the flip flop runs at the technology speed; as long as you don't clock it faster than the technology speed it's fine.

author: promach
author_rank: Frequent Contributor
timestamp: February 24, 2021, 02:15:01 pm
content: QuoteDo you have a picture (which is easier to comprehend) to describe your schematics ?

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 24, 2021, 02:17:31 pm
content: Look at US patent #5279181 Fig 2aI don't have the capability to draw it where I am at the moment.

author: promach
author_rank: Frequent Contributor
timestamp: February 24, 2021, 02:21:09 pm
content: https://patents.google.com/patent/US5279181/enis not related to this discussion at allDId you copy the patent number correctly ?

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 24, 2021, 02:22:08 pm
content: Sorry, #52971281https://worldwide.espacenet.com/publicationDetails/biblio?II=1&ND=3&adjacent=true&locale=en_EP&FT=D&date=19940322&CC=US&NR=5297181A&KC=A#

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 24, 2021, 02:25:33 pm
content: I got the number wrong again (can you believe it!) but the link is correct, go in two pages and it's there. The correct number is 5297181

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 24, 2021, 02:45:59 pm
content: In the case of DDR that's usually handled in the I/O block. For DDR they use a + edge clocked FF and a -ve edge clocked FF. You get two outputs and then handle the two bits together.https://www.latticesemi.com/view_document?document_id=47960Middle of page 13

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 24, 2021, 03:09:12 pm
content: Yeah, I was going to say, if what you really want to do is a DDR IO, then instantiate DDR directly. Many FPGAs these days have DDR blocks.The trick shown in the OP (DEFF) works if there's no DDR block available, but it will be (much) slower. Also, I highly doubt synthesis tools would actually infer a DDR block from this code.

author: promach
author_rank: Frequent Contributor
timestamp: February 25, 2021, 02:01:04 am
content: May I ask which circuit i better for verilog implementation for both FPGA and ASIC ?the DEFF circuit or @Chris_Mr suggested circuit in the US patent ?

author: gnuarm
author_rank: Super Contributor
timestamp: February 25, 2021, 02:23:38 am
content: Quote from: Chris Mr on February 24, 2021, 02:45:59 pmThat's odd. I thought they used a PLL to get a 2x clock and clocked the data into a 2 bit shift register, then a parallel load on every other cycle of the 2x clock. This is because clocking on the opposite edges of the clock requires a level of symmetry that is seldom available in a clock unless the clock is derived by dividing down a 2x clock. DDR circuits are working on a narrow margin of setup and hold time. The typical jitter spec of ±5% makes the timing tighter than desired.

author: Bassman59
author_rank: Super Contributor
timestamp: February 25, 2021, 02:30:31 am
content: Quote from: BrianHG on February 24, 2021, 09:15:02 amThis is the correct answer.

author: Bassman59
author_rank: Super Contributor
timestamp: February 25, 2021, 02:32:02 am
content: Quote from: Chris Mr on February 24, 2021, 02:12:49 pmHow does timing analysis work with this?Why is it better than using a PLL/DLL to double the clock frequency inside the FPGA?

author: Bassman59
author_rank: Super Contributor
timestamp: February 25, 2021, 02:37:31 am
content: Quote from: gnuarm on February 25, 2021, 02:23:38 amFor DDR output, the driver to the pin works as described -- two flip-flops next to each other, clocked by the opposite edges of the clock. Each flip-flop has its own D input, so it is important to drive them correctly. A mux selects which flop drives the pins. The clock level is that mux select.The DDR block runs at the "normal" FPGA clock rate, not doubled.You are correct that using both edges of the clock requires that clock be damn close to 50% duty cycle, but practically this is almost always the case, especially if you use an internal PLL/DLL to create the clock. (Remember you don't have to use the PLL for doubling the clock, you can use it for this sort of clean-up.)

author: Daixiwen
author_rank: Frequent Contributor
timestamp: February 25, 2021, 07:43:57 am
content: Quote from: promach on February 25, 2021, 02:01:04 amNone of those. Either use a double rate clock (which you said you couldn't use) or a ready made DDR I/O primitive from the manufacturer. It's a lot easier to implement, is optimal for your target and will save you a lot of headaches when coping with timing requirements.

author: langwadt
author_rank: Super Contributor
timestamp: February 25, 2021, 09:47:06 am
content: Quote from: gnuarm on February 25, 2021, 02:23:38 amwell if you have sink that expects data on each edge or a source that supplies data on each edge you better stick to to those edges or you will eat up you setup and hold time. If you sample on the edges any jitter on the duty cycle it won't affect the setup and hold it will only affect the time you to move the negative edge data to/from a positive edge flop

author: promach
author_rank: Frequent Contributor
timestamp: February 25, 2021, 12:21:56 pm
content: how to generate 90 degree phase-shifted (which is equivalent to negedge clk) clock using clock divider mechanism ?

author: langwadt
author_rank: Super Contributor
timestamp: February 25, 2021, 12:51:32 pm
content: Quote from: promach on February 25, 2021, 12:21:56 pmnegedge is 180 degree. you cannot generate 90degree with out 4x the frequency or 2x the frequency and both edges

author: promach
author_rank: Frequent Contributor
timestamp: February 25, 2021, 12:53:59 pm
content: I am trying to generate a 90 degree phase-shifted clock from existing clock WITHOUT pumping up the existing clock frequency, hence the clock divider.Someone told me the following, but I am bit confused with his sentence wordings.Quote

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 25, 2021, 01:32:45 pm
content: Take the thing I showed you yesterday, and take it's output into the clock input of two flip flops FFA and FFB.Q\ of FFA is the D input of FFB.Q output of FFB is the D input of FFA.Now you have all four phases. Sorry I can't do a drawing.

author: promach
author_rank: Frequent Contributor
timestamp: February 25, 2021, 01:38:37 pm
content: You mean feedingXOR_OUTsignal to the clock pins of FFA and FFB ?However, I am bit worried about the minimum pulse width of theXOR_OUTsignal which might interfere with each other

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 25, 2021, 01:45:31 pm
content: quadrature.pdf(3.9 kB - downloaded 125 times.)Ok, drawn with mouse so SET mousestate == jerkyand my first attachment so anything could happen.quadrature.pdf(3.9 kB - downloaded 127 times.)

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 25, 2021, 01:47:01 pm
content: Ah, I forgot to remove the extra bar from the first flip flop Q, but it should read ok apart from that.

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 25, 2021, 01:52:25 pm
content: What's interesting about this way, and by no means am I suggesting this for super high frequency work, is that the technology its self is what governs the pulse widths. So, the setup and hold times of that first FF PLUS the delay through the XOR is all within the technology limitations... as long as the clock input isn't faster than the technology.

author: promach
author_rank: Frequent Contributor
timestamp: February 25, 2021, 01:54:37 pm
content: you could have usedhttps://logic.ly/demoby the way, there is no labelling on the four rightmost outputs ?Thanks for the circuit though.

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 25, 2021, 01:58:11 pm
content: Top two are I and I\, bottom are Q and Q\ in that order, top to bottom.This is one way to generate I and Q in quadrature modulation / demodulation etc.

author: promach
author_rank: Frequent Contributor
timestamp: February 25, 2021, 03:03:51 pm
content: @Chis_Mr I suppose timing analysis will be more troublesome since it is not synchronous logic (the clocks are generated by logic),

author: promach
author_rank: Frequent Contributor
timestamp: February 25, 2021, 03:18:05 pm
content: Besides, it is difficult to translate your suggested circuit into verilog coding where the clk is not generated from combinational logic such as the XOR gate.Could you advise ?

author: Chris Mr
author_rank: Regular Contributor
timestamp: February 25, 2021, 04:09:09 pm
content: It rather depends on exactly what is it you are trying to do.Initially you asked for alternatives to ..... so I provided oneIn some devices you can instantiate a global clock buffer, which would connect to the newly generated double rate clock.All the other suggestions revolve around using a PLL, and you say you don't have one (at least that's what I thought I read).For me, it usually goes something like this:What am I trying to doHow am I going to do itWill this device do that, if not pick another deviceThat stops you getting to the point where you are trying to do something down a blind alley, where there is no way out.

author: gnuarm
author_rank: Super Contributor
timestamp: February 25, 2021, 06:40:52 pm
content: Quote from: promach on February 25, 2021, 01:54:37 pmlogic.ly does not let you save or share a design without buying the tool. I spent the time to draw this up and now it is pointless.

author: Bassman59
author_rank: Super Contributor
timestamp: February 25, 2021, 06:51:42 pm
content: Quote from: Chris Mr on February 25, 2021, 01:52:25 pmAnd the trick is to use the combinatorial logic as a clock in an FPGA -- older devices would allow that, but newer parts demand that flip-flop clock inputs be on global clock nets.

author: Bassman59
author_rank: Super Contributor
timestamp: February 25, 2021, 06:53:22 pm
content: Quote from: promach on February 25, 2021, 12:53:59 pmYou still haven't explainedwhyyou need to do this, or what you are trying to implement.

author: gnuarm
author_rank: Super Contributor
timestamp: February 25, 2021, 07:02:23 pm
content: Quote from: Bassman59 on February 25, 2021, 06:51:42 pmI've never seen an FPGA that won't let a logic signal drive a global clock net. The tools give warnings, but they give warnings about jaywalking!I suppose in a CPLD a logic signal would need to be routed out of the package and back into the clock net, but every FPGA I've used allows logic signals to drive global clock nets. They just don't tightly control the routing delay of the route prior to reaching the global driver and warn you of that. Clock routing is special animal with specific timing controls so all the clocking works.

author: BrianHG
author_rank: Super Contributor
timestamp: February 25, 2021, 11:10:52 pm
content: Quote from: gnuarm on February 25, 2021, 07:02:23 pmIt's worse than you think. Using logic to drive a clocked section or global clock actually shifts phase relative to the reference source clock based on silicon temperature change and VCCint voltage. It's completely useless junk for anything above ~100-200MHz as any timing critical goes by the wayside. The PLL clock generators and their phase comparators in FPGA have separate power supplies to deal with voltage deviation and are designed to be temperature compensated, it not just that the VCO itself is voltage sensitive, it's the phase comparator and primary dividers that feed the comparator which have specific silicon designed to deal with these issues.

author: Bassman59
author_rank: Super Contributor
timestamp: February 26, 2021, 02:26:41 am
content: Quote from: gnuarm on February 25, 2021, 07:02:23 pm

author: promach
author_rank: Frequent Contributor
timestamp: February 26, 2021, 02:49:03 am
content: @Bassman59For DDR3 memory controller. SeeDQSandDQsignal pair which is basically DDR (require both posedge clk and negedge clk)As forCKandCommandbus signal pair, I have a side question: do these two signal require 90 degree phase shift asDQSandDQsignal pair ?In other words, shouldCommandbus signal be strictly aligned withCK, not 90 degree out-of-phase with respect toCK?

author: gnuarm
author_rank: Super Contributor
timestamp: February 26, 2021, 08:53:46 am
content: Quote from: BrianHG on February 25, 2021, 11:10:52 pm"The lady doth protest too much, methinks!"The phase shifting you speak of is between the source of the clock and the destinations served by the clock tree. How is this any different from a clock generated off chip and coming in through a global clock? While the routing on the global clock lines are are consistently even, everything leading up to the routing and the routing itself is subject to variations of voltage and temperature. The point of global clock lines is to keep all the FF clocks consistent with one another. If you want some sort of consistent delay with respect to a clock source it requires using a PLL on chip and running a copy of the clock off chip and back on.There are many, many, if not all, then most applications that don't worry with such gyrations. The chip just needs a clock and it doesn't matter where it comes from, internal logic, external clock chip or from the national atomic clock bank run through a Kalman filter just for your design to display the time to the picosecond. A friend built such a device for the NRO some time back. Used a Lattice XP2. Maybe not to the picosecond, but it did compensate for various factors and triggered a 1 second strobe I believe. The strobe went to the Kalman filter which agglomerated some dozens of clocks with varying degrees of accuracy providing a common 1 pps signal that they all used to coordinate with each other.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: February 26, 2021, 10:23:53 am
content: Quote from: promach on February 26, 2021, 02:49:03 amThe timing diagram is a bit misleading when you are not used to it. None of the DDR signals use a 90 degree out of phase clock. It looks that way because they put the signal transitions way between the clock edges, but in practise they can happen a lot closer to them. What is important is that you follow the setup and hold requirements of the interface on the receiving end to be sure that the signals are read correctly at the clock edge.One of the ways to do that when you design a DDR interface, is to only use the CK clock internally. The command signals use the rising edge, and the DQ/DQS use both edges. Then you give to the design tool your setup and hold requirements, and it will take those into account when performing the routing inside the FPGA or the ASIC, adjusting the timing of each signal (including the clock) to ensure that those requirements are met outside of the chip. As the frequency increases it's not always possible, so you may need to use an out of phase clock. It's possibly not 90 degrees, but a phase shift adapted to the timing of your signals both inside the chips and on the PCB. The DDR3 interface has a calibration phase where the master tries several shifts and see which one is best. To do that you need a PLL with adjustable phase shift.Could you give a better description of the problem you are trying to solve, including the target(s) you are working on, the required frequency, and a timing diagram? It will make it easier to recommend you solutions.Quote from: gnuarm on February 25, 2021, 07:02:23 pmThere is a good reason they give warnings. Combinatorial logic can generate glitches if you are not careful and then using them as clocks will generate unexpected clock edges and possibly timing violations. You can of course do it but you need to know what you are doing and have a good knowledge of how your code will be synthesized on the specific target you are using.edited to include adjustable clock shifting through a PLL

author: promach
author_rank: Frequent Contributor
timestamp: February 26, 2021, 11:06:07 am
content: @DaixiwenI am coding a DDR3 memory controller in verilog, and I had not decided which FPGA to use yet.

author: NorthGuy
author_rank: Super Contributor
timestamp: February 27, 2021, 03:29:01 pm
content: Quote from: promach on February 26, 2021, 11:06:07 amThat's not a very good idea. DDR3 is way too fast to be handled in general fabric. FPGAs will have lots of tools you can use. Say, Xilix FPGA uses ISERDES, which can be used in MEMORY mode - you feed it the clock, DQS and DQ and it produces the sampled data.Everything needs to be properly phase shifted. The phase shifts are arbitrary - they depend on the length of the traces and on the specific DDR3 chip you work with. Therefore DDR3 controller will need calibration - either every time you start FPGA, or once. To accomplish fine phase shifts you need programmable high resolution (at least 100 ps) delay elements. All this will be vendor specific. Very little you can do with general Verilog.The DQ/DQS phase shifts are the responsibility of the controller. Naturally, it's easier to output DDR signal in phase with the clock. But when you sample DQ with DQS they have to be shifted by 90 degrees. The DDR3 chip does what's easy - it outputs DQ/DQS in phase and it expecs DQ/DQS to be 90 degree shifted when you write to memory. So, the DDR3 controller has to do the hard part - shift 90 degrees in both cases, which means you need to have separate 90 degree shifted clocks for DQ and for DQS. This also means that you have to use delays to shift DQS and DQ correctly relative to each other. And it happens very fast - the whole clock cycle might be shorter than the propagation delay through the input buffer.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 27, 2021, 07:04:23 pm
content: I agree with NorthGuy. A fully generic DDR controller is kind of a lost cause. If you're targetting FPGA's, it even doesn't make a lot of sense. Or at least, for all the structures you're wondering about here (such as DDR I/O). And most FPGAs these days have DDR controller IPs. But if you still think writing your own controller would be interesting, then keep all the critical blocks such as DDR I/O in black boxes. Then implement them instantiating the appropriate commponents for each particular FPGA. And with this approach, if you ever want to implement your controller directly on silicon, you'll also have the opportunity to implement those any way it's best for the process and PDK you'd be using. But even with this approach, you'll likely need to define appropriate timing constraints and those will likely be different for each FPGA vendor...But again, expecting synthesis tools to infer effective logic for DDR using dual-edge processes? Nah.

author: ejeffrey
author_rank: Super Contributor
timestamp: February 27, 2021, 07:53:00 pm
content: I can tell you from experience that directly working with the DDR IO primitives for a non-memory application where the provided memory controller IPs are not applicable is difficult and involves a lot of time spent staring at the FPGA reference manuals, along with data sheets for whatever exists at the other end. Its not really practical to do that in a generic way.

author: BrianHG
author_rank: Super Contributor
timestamp: February 28, 2021, 02:37:42 am
content: With such a gate-tied clock generation, how do you expect to perform read leveling?How do you expect the write leveling to always be centered at the 90degree phase in relation to the DDR3_CK/CK# clock during FPGA silicon temperature drift as you gate generated clock's response time cumulatively shifts?What about the read phase relationship as the temperature of the DDR3 ram chip shifts that relationship. Especially over wide buses where you have multiple DQS banks for every 8 bits.Quote from: promach on February 25, 2021, 02:01:04 amIf you have the budget for an ASIC, you are using professional dedicated hardware DDR3 function blocks hardwired for speed.

author: promach
author_rank: Frequent Contributor
timestamp: February 28, 2021, 03:00:42 am
content: @BrianHG I am planning to simulatehttps://patents.google.com/patent/US8023342in a week or two.But as for now, my verilog coding logic is still under development process. So, the slower the clock, the easier for the debugging process at theinitial logic coding development stageSo, someone suggested that clock divider could be used for the following 3 purposes:// 1. for developing correct logic first before making the DDR memory controller works in higher frequency,// 2. to perform 90 degree phase shift on DQ signal with relative to DQS signal during data writing stage// 3. to perform 180 degree phase shift (DDR mechanism of both DQS and DQ signals need to work on// both posedge and negedge clk) for the next consecutive dataNote: Usingalways @(i_clk)together with its internal always block logic usingck_stbandcounterwilldetermine which phase shift I need

author: promach
author_rank: Frequent Contributor
timestamp: February 28, 2021, 10:39:17 am
content: Quote from: Chris Mr on February 25, 2021, 01:45:31 pm@Chris_MrSomeone told me this circuit that you suggested would not be able to generate 90 degree phase shift.However, I am not convinced yet.I am planning to get it works with theD flip-flops hardware primitives in sky130 PDKsince pure verilog coding would not be able to model your circuit.By the way, when I research further, it seems that digital PLL might not be needed at all in this context. Please correct me if wronghttps://patents.google.com/patent/US9158873https://patents.google.com/patent/KR20050101864A/enhttps://patents.google.com/patent/US7443741B2/enhttps://patents.google.com/patent/US9001595

author: gnuarm
author_rank: Super Contributor
timestamp: February 28, 2021, 05:30:17 pm
content: Quote from: promach on February 28, 2021, 10:39:17 amThis circuit doubles the clock rate, then produces a 90° phase shift by dividing by four. So in effect it halves the input clock rate to achieve the output clock rate using what is 180° phase shift relative to the incoming clock.You can use the same logic without doubling the input clock rate and get an output clock rate that is a quarter of the input clock rate with 90° phase shifts.You can also get the same result of 90° phase shifts at half the clock rate without doubling the input clock by having one of the FFs operate on the falling edge of the clock.You can not get 90° phase shifts at the input clock rate by combining the clock rate doubling with the negative edge clocking because the frequency doubled clock does not have a 50/50 duty cycle or anything close to it. In fact, that circuit is not guaranteed to work in any logic family. It most likely is failing clock timing specifications and possibly voltage specifications.Oh yeah, you can simulate this from HDL inferred logic. First simulate in a language simulator which will produce infinitely narrow clock pulses. You can also simulate after synthesis using the primitives generated rather then instantiating primitives.

author: langwadt
author_rank: Super Contributor
timestamp: February 28, 2021, 06:19:44 pm
content: why so hung up on 90 degrees? nothing happens at 90 degree, everything happens at 0 or 180 deg after some delay that varies and will have to be accounted for in each implementation

author: Daixiwen
author_rank: Frequent Contributor
timestamp: March 01, 2021, 11:08:27 am
content: The dedicated DDR memory controller IPs in FPGAs usually use a PLL with the possibility to finely adjust the phase shift between an "intern" clock that is used in the FPGA and the "extern" clock on the PCB. Then the calibration algorithm will adjust that PLL shift to have an optimal timing. The PLL is of course a vendor dependent primitive so you won't be able to describe this in a generic way in HDL. You will need to choose your target first and then see what primitives or controllers you can use.Some FPGAs have ready made hardcore DDR3 controllers, and if you can use those it will save you a lot of time and pain.

author: NorthGuy
author_rank: Super Contributor
timestamp: March 01, 2021, 02:37:56 pm
content: Quote from: langwadt on February 28, 2021, 06:19:44 pmDQ and DQS are sent by DDR3 chip in phase. DQS is not a clock, really, but rather a strobe which accompanies DQ. DQ changes at 0 and 180 degrees, so the sampling window is somewhere between 0 and 180 (with the middle at 90) and another one between 180 and 360 (with the middle at 270). If you want to use DQS to sample DQ (that is DQ goes to the D input of flip-flop and DQS goes to the CLK input of the flip-flop), you need to position DQS edges in the middle of the windows (that is at 90 and 270). Hence, it's necessary to shift DQS by 90 degrees.

author: langwadt
author_rank: Super Contributor
timestamp: March 01, 2021, 04:11:25 pm
content: Quote from: NorthGuy on March 01, 2021, 02:37:56 pmstill doesn't make 90 a significant number. What matters is sampling at the right spot when taking into account the output, input and wiring delays on DQ and DQS and what the required setup and hold is on the flipflop

author: NorthGuy
author_rank: Super Contributor
timestamp: March 01, 2021, 05:41:30 pm
content: Quote from: langwadt on March 01, 2021, 04:11:25 pmOf course, it doesn't have to be exactly 90 degrees. 90 is nominal.DQS and DQ take different paths to the flop and thus encounter different delays with different uncertainties. These uncertainties may be far greater in magnitude than the phase shift you're trying to achieve. Therefore, by the time they arrive to the receiving flip flop, their phase relationship is not really known. The controller would typically use calibrated delays to align the signals to the middle of the window empirically.

author: langwadt
author_rank: Super Contributor
timestamp: March 01, 2021, 06:34:09 pm
content: Quote from: NorthGuy on March 01, 2021, 05:41:30 pmeven in the case where the delays are the same 90 would only be nominal if setup and hold are the same

author: NorthGuy
author_rank: Super Contributor
timestamp: March 01, 2021, 07:03:07 pm
content: Quote from: langwadt on March 01, 2021, 06:34:09 pm"Nominal, adjective - (of a quantity or dimension, especially of manufactured articles) stated or expressed but not necessarily corresponding exactly to the real value."

author: promach
author_rank: Frequent Contributor
timestamp: March 04, 2021, 11:13:27 pm
content: 1. Do I really needtdqsandodt?2. Another question is do I needtwrforwrite_AP?by the way, I had done an initial code for the DDR3 memory controller in verilog :https://gist.github.com/promach/2c477b1dbc39f04a1271fb229e6d678c

author: promach
author_rank: Frequent Contributor
timestamp: March 13, 2021, 12:57:45 am
content: ForData strobe enable circuitry, in Figures 4 and 5 , how exactly does theDQS_Cleanbeing phase-shifted 90 degrees with reference toDQS_PandDQS_N? Why do we need theCOUNTERmodule in which the circuit is described in Figure 5 ? What value should I assign forVref?