RISC-V Book Is Here - Page 1
Forum section: electronics / general

author: rstofer
author_rank: Super Contributor
timestamp: January 07, 2021, 12:57:33 am
content: At long last, "Computer Organization and Design RISC-V Edition" (2d ed) Patterson & Hennessy has finally arrived.https://www.amazon.com/gp/product/0128203315For the beginner in logic design, Appendix A provides a really good explanation in 86 pages.

author: hamster_nz
author_rank: Super Contributor
timestamp: January 08, 2021, 02:11:20 am
content: Nice! Maybe it has a concise explanation of how RISC-V exceptions and interrupts work....Although I think I have a handle on that now:Set 'mcause' CSR to reflect the cause of the exception, set 'mepc' CSR to the current PC, and then jump to 'mtvec' or mtvect+4*mcause, depending on if vectored exceptions are enabled (lset via the lowest bit of mtvec)Wish it was written that way somewhere...

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 08, 2021, 02:25:55 am
content: Quote from: hamster_nz on January 08, 2021, 02:11:20 amAs you understood, interrupts are just a particular case and are handled as exceptions (there's just one bit in mcause that tells it's an interrupt).mepc should be set to the PC of the instruction that has raised an exception(/has been interrupted) - that matters if your core is pipelined. The PC will be set to mepc upon the execution of MRET (/SRET/URET), which means the interrupted instruction will be executed right after xRET, and not the instruction following it. This also means the instruction raising an exception/being interrupted should NOT be executed to completion.You also need to take care of the mstatus register:* the MPP field should be set to the current privilege level,* MPIE field should be set to the current value of MIE field,* MIE field should be set to 0 (interrupts are always disabled per the spec before jumping to the trap/exception handler.The above is just for the 'machine' level, if you want to support all privilege levels you have to do this for all levels.The xRET instruction will essentially do the reverse and jump to mepc.When deciding to handle an interrupt, you need to check that interrupts are globally enabled (MIE for instance for machine mode), then mask the MIP CSR with the MIE CSR, and determine from there if an interrupt is pending.

author: bson
author_rank: Unknown
timestamp: January 10, 2021, 03:48:33 am
content: Can an ISR modify the mepc to return to a different context? If not, how do you implement a context switch? On ARM if an ISR unblocks a waiting thread it marks the thread accordingly (and might store a hint to the scheduler if its prio is higher or equal to the currently running one), then schedules a software interrupt. Hardware interrupts are processed first, and several ISRs may unblock waiting threads, so they may all trigger a software interrupt. The SWI is run once after all the HWIs, in it the scheduler looks to see if a context switch is needed, and if so returns to a different context from the handler. This means the instruction can't be half finished or anything like that, and needs to be completely restartable on return. There can't be any state in the pipeline that's not discardable.

author: hamster_nz
author_rank: Super Contributor
timestamp: January 10, 2021, 04:28:23 am
content: My understanding is privilege depends on the instruction used to return - mret, sret or uret. And yes, you can set the mepc to any value you need.

author: brucehoult
author_rank: Super Contributor
timestamp: January 10, 2021, 04:56:52 am
content: Quote from: bson on January 10, 2021, 03:48:33 amSure, of course.That's how you change to S or U mode code in the first place. That's how you emulate missing instructions or unaligned loads/stores etc (and increment mepc past them before returning)

author: brucehoult
author_rank: Super Contributor
timestamp: January 10, 2021, 05:12:28 am
content: Quote from: hamster_nz on January 10, 2021, 04:28:23 ammret, sret determine which registers the new pc, privilege, and interrupt enable are taken from.The new privilege level is set from MPP in MSTATUS for MRET (can be M, S, or U), SPP for SRET (can be S or U), and UPP for URET (which can only be U).

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 10, 2021, 05:20:26 pm
content: mepc is freely writable by software - as long as the code doing that is running at the machine level, of course. (The equivalent CSRs for the others levels are sepc and uepc.)Of course, for context switching, you need to save the current mepc before setting it to a different value, otherwise you'll never be able to return to the code that was interrupted. Probably obvious...