New wireless module announced with RISCV & USB interface - Page 1
Forum section: electronics / general

author: mon2
author_rank: Frequent Contributor
timestamp: December 29, 2022, 07:59:50 pm
content: By Sipeed:https://twitter.com/SipeedIO/status/1608366512083193857Quote

author: ataradov
author_rank: Super Contributor
timestamp: December 29, 2022, 09:22:21 pm
content: Just another completely undocumented chip. The USB chapter of the RM is literally empty. Not a single word.

author: martinribelotta
author_rank: Regular Contributor
timestamp: December 29, 2022, 09:33:58 pm
content: Quote from: ataradov on December 29, 2022, 09:22:21 pmBut is completelly documented:https://dl.sipeed.com/shareURL/Maix-Zero/M0P/6_Chip_ManualMore than other chinese chips... sure... is not a NXP datasheet with varios MBy of application notes but have the essential information into this...Aditionally, boufallo have a very open repository:https://github.com/bouffalolab/bl_mcu_sdk/tree/master/drivers/soc/bl616/std

author: ataradov
author_rank: Super Contributor
timestamp: December 29, 2022, 09:58:58 pm
content: Quote from: martinribelotta on December 29, 2022, 09:33:58 pmName one USB register based on this documentation.

author: martinribelotta
author_rank: Regular Contributor
timestamp: December 29, 2022, 10:06:25 pm
content: Quote from: ataradov on December 29, 2022, 09:58:58 pmTouche! Trully... the usb device lacks documentation completelly but the abailability of code:https://github.com/bouffalolab/bl_mcu_sdk/blob/master/drivers/lhal/include/hardware/usb_v1_reg.hhttps://github.com/bouffalolab/bl_mcu_sdk/blob/master/drivers/lhal/include/hardware/usb_v2_reg.h(and correspondign sources) mitigate this lack... normally the usb core is a canned IPCore from synopsis or similar provider...Lamentably, is an increasing practice in varios vendors like ST or NXP (and long date known from TI)

author: hans
author_rank: Super Contributor
timestamp: December 30, 2022, 09:30:15 am
content: Probably, I googled some register names and found this PDF:https://caxapa.ru/thumbs/655229/GM8136S_GM8135S_Data_Sheet_V0.2.pdfSee chapter 12.4. The in-depth explanation is sparse or non-existent. It does list the RTL in a slightly easier to read format than just C defines. It's clearly an IP core of some sort.. hoped to find which IP it is, because maybe that can point to more in-depth docs from the manufacturer (or to some Linux kernel driver if really desperate).The v1 RTL seems fairly simple to operate, e.g. PIC16 USB levels of complexity.

author: martinribelotta
author_rank: Regular Contributor
timestamp: December 30, 2022, 12:46:52 pm
content: Quote from: hans on December 30, 2022, 09:30:15 amIn my experience working with rtl-sw designs, normally the datasheet is internally and make references to testbenchs (normally in systemverilog)Its not surprising that many small vendors take this approach:- Create IPCore or buy to another vendor like synopsis- test in SV some functionalities and run syntathic tests with very common use cases- use this synthetic tests as a template to generate a C HAL with minimal functionalityYeeeeees, this is baaaad... but the time-to-market is incredible low and, from the point of sellers, have a minimal inversion on I+DMany engieers (including me) prefer the old way with a big datasheet or (even better) a separate IPCore datasheet but is extremelly rare even for a big sellers like NXP or STThe best way to do this thinks will be separate chip datasheet from IPCore datasheet and reuse both in many designs... this is far from reality

author: mon2
author_rank: Frequent Contributor
timestamp: December 31, 2022, 11:00:15 am
content: From the semiconductor's tech support group on the BL616:Quote