SR latch in a GAL 22V10 - Page 1
Forum section: electronics / general

author: banedon
author_rank: Regular Contributor
timestamp: August 05, 2017, 08:37:52 pm
content: Hi guysI'm trying to design a memory card for an old 8 bit computer for a bit of fun and have finally finished the circuit design.However it uses a few too many discrete logic ICs and I've decided to try and squeeze them into a GAL (22V10). Very easy apart from the fact that I have 2 SR latches.I have no idea how to go about getting these to work apart from have 2 x 3 nor gates with 3 pins each which is highly inefficient. From what I can see the 22V10 does not have built in SR latches.The attachment shows one of the latches (both are the same). Can anyone give any advice on how to get these to work in the GAL?

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: August 05, 2017, 09:06:03 pm
content: You can make a latch by feeding an output back into itself. How many external inputs and outputs do you need?

author: banedon
author_rank: Regular Contributor
timestamp: August 05, 2017, 09:59:39 pm
content: Quote from: Bruce Abbott on August 05, 2017, 09:06:03 pmHi BruceIt should have 2 inputs and 1 output. I've attached another image which I hope illustrates this. Everything inside the dotted lined box should be inside the GAL with the 2 inputs and 1 outputs (noted in red).

author: Andy Watson
author_rank: Super Contributor
timestamp: August 05, 2017, 11:03:10 pm
content: As Bruce pointed out, all of the 22v10 outputs have feedback terms available. You should be able to see that your original circuit gives (I think) \$ Q = \overline{((\overline{A.B}) ( \overline{B.Q} ))} \$ . Using a bit fo DeMorgan's theory you should be able to realise this as \$ Q = (A.B) + (B.Q) \$ , which is easily implemented in the GAL configuration. Where A and B are the two inputs.

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: August 06, 2017, 12:42:41 am
content: TheWinCUPLcode for a basic NAND SR latch looks like this:-Code:Device g22v10 ;/* ***************** PINS ************************/PIN 1 = SET ; /* SET input (active low) */PIN 2 = RESET ; /* RESET input (active low) */PIN 23 = Q ; /* Q output *//******************* EQUATIONS *******************/Q = (Q & RESET) # !SET;Though I have designated pin 23 as an output it is also an input, so we can use Q on both sides of the equation to create feedback. "Q = Q" holds the last state of the Q output. "Q & RESET" forces Q low if RESET goes low. "# !SET" (OR NOT SET) forces Q high if SET goes low.You have an extra NAND gate on the SET input. With your signal names this is:-Code:PIN 1 = 1MHZ_EB;PIN 2 = NPGFD_B; /* reset */NAND_out = !(1MHZ_EB & NPGFD_B) /* set */Adding the NAND gate to the latch we get:-Code:PIN 23 = OUTPUT;OUTPUT = (OUTPUT & NPGFD_B) # !(!(1MHZ_EB & NPGFD_B));which can be simplified toCode:OUTPUT = (OUTPUT & NPGFD_B) # (1MHZ_EB & NPGFD_B);

author: banedon
author_rank: Regular Contributor
timestamp: August 06, 2017, 12:49:28 pm
content: Many thanks guys - that seems to be doing the trick. Although WinCUPL in a bizarre twist won't accept having NPGFC and NPGFD as varibles/labels- it throwns an error. Rename one of them to anything else and it's fine. Eitherway, sorted