Quarter wave symmetry of sine wave using Verilog (SOLVED) - Page 1
Forum section: electronics / general

author: knight
author_rank: Regular Contributor
timestamp: October 12, 2022, 06:19:37 am
content: Hi all, I'm trying to create a sine wave using the quarter wave symmetry property. I have followed the attached block diagram and not getting output for 1MHz frequency, which appears to have small peaks during change from one quadrant to another. I have attached the Vivado project and the output waveform. Can someone please help me to debug the code?Edit: The issue is solved, and all files are in the zip file if anyone is interested in the project.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 12, 2022, 08:39:04 am
content: Their is a difference in latency between the 'pa_out' signal and the 's_lut_out', because the lookup table's output is registered.Code:lut_complementer # (.N(17))C2 (.clk(clk), .rst(rst), .msb_in(pa_out),.comp_in(s_lut_out), .comp_out(s_out));You want to delay pa_out by one cycle.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 12, 2022, 09:11:11 am
content: Oh and your LUT table is slightly wrong....Table entry x should beCode:table = sin((2*x+1)/(2*table_size)*PI/2)not the currentCode:table = sin(x/table_size)*PI/2)With the current LUT values, if you walks slowly around the circle you will get what looks to be 'crossover distortion':Code:11111111101101001 -table11111111110011011 -table11111111111001110 -table00000000000000000 -table00000000000000000 table00000000000110010 table00000000001100101 table00000000010010111 table

author: knight
author_rank: Regular Contributor
timestamp: October 12, 2022, 10:22:41 am
content: Quote from: hamster_nz on October 12, 2022, 09:11:11 am

author: knight
author_rank: Regular Contributor
timestamp: October 12, 2022, 05:18:48 pm
content: Quote from: hamster_nz on October 12, 2022, 08:39:04 amThe pa_out is also registerised if you check the phase_accum module. In top level ddfs, wire is just used to connect the internal signals.

author: knight
author_rank: Regular Contributor
timestamp: October 13, 2022, 04:08:51 am
content: Quote from: knight on October 12, 2022, 05:18:48 pmSorry, you were right. Delaying by two clock cycles fixed the "crossover" problem. I didn't change the LUT though.Code:reg dly1, dly2;always @(posedge clk or negedge rst)beginif (~rst)begindly1 <= 0;dly2 <= 0;endelsebegindly1 <= pa_out;dly2 <= dly1;endend

author: hamster_nz
author_rank: Super Contributor
timestamp: October 13, 2022, 07:15:02 am
content: Quote from: knight on October 12, 2022, 10:22:41 amReplaceCode:dec2bin((int)floor(0.5 + ((1 << (BITS-1)) - 0.50001) * sin(2 * 3.1415926535897932 / POINTS * n)));withCode:double scale = 0.5 + ((1 << (BITS-1)) - 0.50001);double angle = 2 * M_PI / (2*POINTS) * (2*n+1);dec2bin((int)(scale * sin(angle)));

author: knight
author_rank: Regular Contributor
timestamp: October 22, 2022, 03:55:17 pm
content: Quote from: knight on October 12, 2022, 06:19:37 amI completed the code for both sine and cosine wave and I'm getting output for all frequencies but not 1 MHz, as you can see, there is peaks when sine goes from one quadrant to another. The output is clean for other frequencies. The frequency tuning word or fcw is calculated as:FCW = (Fout * 2^(n))/FclkSo, for Fout = 1 MHz, n = 20-bits and Fclk = 100 MHz, FCW = 10486. In the testbench you can put any value for FCW (Fout less than 1/10 Fclk), and you would get a proper output, just not for 1MHz, that's my issue.Thanks.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 23, 2022, 02:07:05 am
content: I am pretty sure that 1,000,000 x 2^20 will cause an integer overflow.Could that be your problem?

author: knight
author_rank: Regular Contributor
timestamp: October 23, 2022, 06:52:06 am
content: Quote from: hamster_nz on October 23, 2022, 02:07:05 amPhase word is hard coded in the program and not calculated using the expression.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 24, 2022, 04:24:42 am
content: Quote from: knight on October 23, 2022, 06:52:06 amIf you are able to post a zip of the .v files, including the testbench that demonstrates the problem, I'll have a look at it..

author: knight
author_rank: Regular Contributor
timestamp: October 24, 2022, 09:29:08 am
content: Quote from: hamster_nz on October 24, 2022, 04:24:42 amEverything is in the Vivado project folder bro, you just need to open the .xpr file in Xilinx vivado and everything is there.You can find the .v files in srcs folder.By the way, I fixed the issue. I followed the block diagram, and you can see that PA complementor outputs (k-2) bits but I coded it to output (k-2+1) bits, so that was causing the problem. Now it works for all FCW values. I updated the .zip files if you want to try it out and maybe you can do a more thorough testing?