Problem with peak detector - Page 1
Forum section: electronics / projects

author: BorisRap
author_rank: Contributor
timestamp: March 24, 2023, 01:48:55 pm
content: Hello, I'm experimenting with a peak detector circuit for an impedance measuring device. The device generates a 10kHz sine wave it sends it through an unknown impedance and then measures de difference in peak voltage (of the sine) and then uses the impedance as one of the gain resistors of an inverting op amp to calculate the unknown impedance.To correct for gain error and linearity, etc... I measure both the peak voltage in the in the input of the unknown impedance and the output of the amplifier.It works pretty good, but there is a slight issue with the peak detectors.I use peak detectors because the sine wave is symmetrical and it's a simple way to capture the sine to be read from a micro controller.Here is a schematic of the peak detector I'm using.The problem I'm having is that there is a difference of around 65mV between the peak of the sine wave and the voltage captured in the PD, as shown in these images.The capture is right after a reset of the peak detector, meaning the Mosfet is just opening again.The yellow plot is the voltage right at R11, the input of the peak detector. The blue plot is the output of IC4G$3 (the test point PD_OR)The components shown in the schematic are the ones I used, OPA4197 is somewhat a precision amplifier with high impedance inputs and BAS716 diodes are low leakage diodes.Do you have any idea why I'm getting this difference?Thank you!

author: Andree Henkel
author_rank: Regular Contributor
timestamp: March 24, 2023, 03:38:40 pm
content: take picture with lower frequencymeasure voltage at storage cap and the other nodes inside of the peak detektor,most probably IC4G1 runs to negative supply saturation, and is not quickly enough back at new peak.D1 and R26 are most probably unnecessary, bridge D1, remove R26instead you need to add something to prevent that saturation of IC4G1 occurs

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 24, 2023, 03:38:53 pm
content: Consider the time constant of D1+D2 ESR + R23 versus C19?Why a peak detector (highly sensitive to ambient noise, more sensitive to harmonic distortion and filtering effects by the DUT) over a quadrature mixer (average the outputs, get resistance and reactance out directly; strong rejection of incoherent signals)?Tim

author: moffy
author_rank: Super Contributor
timestamp: March 25, 2023, 06:09:42 am
content: You might wish to try a much smaller storage cap and see how that affects the dynamic performance and peak offset. The fact as Andree mentions you are swinging all the way from -12V to the peak could be an issue, but the slew rate is 20V/us and it takes about 1us to recover from saturation, you still would expect better than 65mv, if that is accurate.P.S. Ran an LTSpice sim using the AD823 (16MHz BW, JFET, RRO, 800uV offset) and it ended up 13mv below peak for 2Vp-p signal @ 5kHz, seems the 13mv wasn't enough to drive the opamp out of -ve saturation.

author: moffy
author_rank: Super Contributor
timestamp: March 25, 2023, 07:59:22 am
content: Tried a slight modification to your circuit, which would be easy for you to try. The idea is to keep the driving opamp out of saturation. This led to a simulation result of just 800uV error, for the same conditions mentioned previously. Not sure if it will work the same in real life but might be worth a try.

author: Terry Bites
author_rank: Super Contributor
timestamp: March 26, 2023, 05:28:00 pm
content: It probably the first opamp going open loop. Note that the opamp is acting as a comparator here.You may have over/ undershoot and ringing that gets converted into an offset.Try these small mods.What kind of cap are you using?With pA of leakage and opamp bias current you probably don't need any where near 10u of storage.Keep the cap as small as possible for best response and premature death of the MOSFET.There's a lot more sag than I'd expect. Something is leaking more than it should. BS7002?The BS7002 can be very leaky. Up to 500uA on a warm day. Consider using a jfet (and smaller cap).You might want to protect the reset transistor by splitting the charging resistor.Ultralow leakage diodes wont give much better performance, you already use a leakge compensation scheme.More chaging current can be supplied if D1 is replaced with an npn transistor.Base to opamp output Collector to V+, emitter to D2 and 10k to gnd.In fact you can repace D2 with another npn as a diode B-C emitter open.

author: BorisRap
author_rank: Contributor
timestamp: March 27, 2023, 01:02:54 pm
content: Thanks to everyone for the input, I've been reading the suggestions and trying some things:I starting by lowering the value of C19 to 470nF, I noticed that the error voltage was way smaller, but then another problem was way bigger. The output voltage after the capture was very variable in every iteration, sometime it was exactly the value of the peak and some other times it was 20-100mV higher. I presumed that was the opamp overshooting. So I went to investigate how to prevent that. I read an article and long story short, the article proposed the same circuit thatmoffysuggested. So I gave it a try.The overshoot issue was sorted, and the measurement are now much more stable. The offset error was reduced, but not completely eliminated, as shown in the image below it is now reduced to around 30mV.The loading time of the capacitor is now way longer due to the series resistance, as shown in the image. I have to experiment to find the best values for each component.The circuit is performing acceptably well, but that offset voltage keeps bugging me.Below are the images of the oscilloscope as well as the current configuration.Quote from: Andree Henkel on March 24, 2023, 03:38:40 pmSadly I cannot lower the frequency, the sine wave is generated from a filtered square wave generated by the micro controller. The filter is calculated for 10kHzThanks to everyone

author: Kleinstein
author_rank: Super Contributor
timestamp: March 27, 2023, 04:06:16 pm
content: The storage capacitor is still very much on the high side. I would consider more like 100 pF to 1 nF, especially with the 2 diode solution that allows for very low leakage and a relatively high frequency. One could also add a small dicharge circuit, to that the voltage will slowly drop and thus not be effected by a single high value.One could reduce the overshoot a little by adding some offset to the opposite direction diode, e.g. with an NPN emitter follower. With a smaller dead band the overshoot could be reduced.For a Impedance meter, measuring a sine wave of a know frequency and phase the peak detector is not a good solution. The more reasonable way with a moder µC would be to directly sample the AC waveform. For 10 kHz excitation the µC internal ADCs are usually fast enough. If needed one could even use subsampling and a conversion frequency below the drive frequency.With a know phase to the excitation one can do a sine + cosine decomposition, just like in an lock-in amplifier. This way one can get the amplitude and phase with low sensitivity to noise. If needed longer averaging can be used to reduce the noise to rather low levels and suppress mains hum quite well.If one does not like the math - one could also do the phase senstive rectifaction in hardware with something like a Tayloe type mixer.