Self-resonant frequency of a decoupling capacitor - Page 1
Forum section: electronics / beginners

author: khatus
author_rank: Regular Contributor
timestamp: September 24, 2025, 02:16:02 pm
content: In this application notes i have some confusion. Here it is written that "Therefore, choosing a low-inductance but high-value capacitor (low impedance) is very important." My question is if I increase capacitance value C and decrease inductance of the capacitor L. Then the Self-Resonant frequency became same. So, what is the benefit of doing this? If we lower capacitance and lower inductance yield higher resonant frequency. Then it can improve effective performance of the capacitor in filtering high-frequency noise. Isn't it good to do this?

author: PGPG
author_rank: Frequent Contributor
timestamp: September 24, 2025, 02:50:44 pm
content: The text is about that what counts is not only capacitance but also self resonant frequency and you understood that only self resonant frequency counts.Find (or draw) charts of capacitors impedance as a function of frequency and compare 100nF capacitor with 1pF capacitor (1pF has higher self resonant frequency).

author: mtwieg
author_rank: Frequent Contributor
timestamp: September 25, 2025, 12:51:58 pm
content: That text is a bit unclear about one's design objective should be.Self resonant frequency isn't the bottom line. Otherwise using a 1pF bypass cap in a 0402 package would be the obvious result (SRF > 10GHz)!Compare a few hypothetical capacitors:1) C=100nF, ESL=1nH2) C=200nF, ESL=0.5nH3) C=200nF, ESL=1nH1 and 2 have the exact same SRF, but 2 will obviously have half the impedance of 1 at all frequencies, so is a better choice overall.3 has a lower SRF than 1. But it will also have lower impedance than 1 at all frequencies. So it's also probably better than 1 overall (but not as good as 2).Things get a lot messier when you look at combinations of different capacitors in parallel and how they interact to make a very messy impedance vs frequency plot.It's hard to give practical advice without knowing more about the application.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 25, 2025, 04:30:02 pm
content: Quote from: khatus on September 24, 2025, 02:16:02 pmIn this case, maybe. The examples mtwieg showed were universally better, but in this case you will be trading worse low frequency performance for better high frequency. That's often a good trade but not if taken to extremes, such as PGPG's example of a 1 pF capacitor.More generally, what doesn't help is to reduce capacitance and keep inductance the same. That increases SRF, but also increases overall impedance at most frequencies (i.e., away from the resonance itself).The best approach is to use the lowest inductance package you can, and then get the highest value of capacitance in that package you fan find (or are willing to pay for). Then put as many of those in parallel as you need to get the inductance down to what you need for high frequency performance. Now assess your low frequency (below SRF) impedance. Chances are, it will be good enough down to a few MHz, at which point the bulk capacitors at your voltage regulator can take over.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 26, 2025, 06:10:28 am
content: You may want to search for various discussion about the "multiple different capacitors in parallel" cargo cult.The key question is, for what purpose you are using the capacitors? For usual power bypassing where you want minimum impedance over widest possible frequency range, and there is no single, specific, narrow frequency which needs specifically even lower impedance, SRF is a completely irrelevant number and you can just ignore its existence.Take different MLCCs in the same package size (thus same ESL) and plot their impedanceson the same absolute Y axisand you will see they bypass the same at high frequencies (and larger C values bypass better at low frequencies).

author: Zero999
author_rank: Super Contributor
timestamp: September 26, 2025, 07:56:08 am
content: https://www.eevblog.com/forum/chat/decoupling-capacitors-and-perceived-wisdom/msg6027653/#msg6027653

author: iMo
author_rank: Super Contributor
timestamp: September 26, 2025, 09:04:14 am
content: Quote from: khatus on September 24, 2025, 02:16:02 pmThe answer is you cannot freely "increase C and decrease L" in reality. The capacitors have dozens of shapes, sizes, mechanical construction types (ie. number of layers used in an MLCC) and dielectric materials used. All that may influence the parasitic L. Thus it requires some experience to know what is the best compromise in order to achieve the lowest impedance for a specific frequency band..The optimal area is at the left hand side of the resonance curve (where the impedance drops down), near the SFR's minima (see below).The serial parasitic Ls is mostly given by the leads length and mechanical construction. Like 1mm of a straight wire is aprox 1nH. Even the MLCCs with the same shape/size but different capacitance may have different SFRs (thus it is not true an 1uF 0603 MLCC will give you a broader BW than a 10nF 0603 MLCC at a specific frequency of interest)..

author: hfleming
author_rank: Regular Contributor
timestamp: September 26, 2025, 09:51:59 am
content: Just as important is your PCB-layout… no point in spending hours analyzing the capacitor-datasheets from every manufacturer and your PCB-layout ads a large amount of inductance between the cap and what it is supposed to decouple, esp. those pesky little via’s…. And those thin tracks to get to the pins (balls) of the IC….

author: Terry Bites
author_rank: Super Contributor
timestamp: September 26, 2025, 11:15:02 am
content: I commend to you Hans Rosenberg's excellent videos on this and other component and pcb issues..

author: mtwieg
author_rank: Frequent Contributor
timestamp: September 26, 2025, 11:58:17 am
content: Quote from: Terry Bites on September 26, 2025, 11:15:02 amOverall a good video, though I would argue against a few of his points (i.e. his suggestion that when different capacitors are in combined in parallel, the smallest shouldn't be put closest to the chip).The key takeaway is that the common trope of "combine multiple capacitors with different capacitance/size" can lead to parallel resonances causing impedance peaks at odd frequencies. Though in practice it's rare for this to actually matter in a way that's noticeable.If you really want to analyze this stuff, you first have to define clearly what your requirements are (frequency range and maximum impedance across that range).

author: mawyatt
author_rank: Super Contributor
timestamp: September 26, 2025, 06:03:05 pm
content: Quote from: mtwieg on September 26, 2025, 11:58:17 amIf the chip has a high dI/dt such as modern small feature fast synchronously clocked CMOS digital chips, then one wants the decoupling capacitor with the lower ESR and ESL closest with minimumfulltrace inductance. This minimizes the VDD glitch/ripple asseenby the chip.Best

author: mtwieg
author_rank: Frequent Contributor
timestamp: September 26, 2025, 08:13:10 pm
content: Quote from: mawyatt on September 26, 2025, 06:03:05 pmNot sure what you refer to by "minimum full trace inductance". But for the capacitor itself, ESL and ESR do not trend together. One cap might have lower ESR but higher ESR (especially if it's a much smaller package).For example if I compare two caps with very different package sizes (but both with the maximum available capacitance in that package and voltage rating) from TDK: C1005X5R1E225K050BC and CGA8P1X7R1E226M250KC. See attached product comparison from their website. The C1005X5R1E225K050BC has an ESL of 0.506nH, while the CGA8P1X7R1E226M250KC has 1.83nH. The CGA8P1X7R1E226M250KC has a much lower ESR though (below its SRF, at least).My habit would be to put the C1005X5R1E225K050BC closer to the chip.

author: TimFox
author_rank: Super Contributor
timestamp: September 26, 2025, 09:27:20 pm
content: Per iMo's comment above:The self-inductance of a physical capacitor normally depends mainly on the overall length, including wire leads if present.One approximation is 6 nH/cm, for plate length plus leads. (fromhttps://content.kemet.com/datasheets/F3294_PHE426.pdf)This is consistent with the approximate value he quoted.

author: tggzzz
author_rank: Super Contributor
timestamp: September 26, 2025, 09:49:44 pm
content: Quote from: TimFox on September 26, 2025, 09:27:20 pmMinimal length and maximal width is especially valuable for PSU decoupling applications, since that minimises inductance. Hence 0603 and 0306 capacitors.

author: mawyatt
author_rank: Super Contributor
timestamp: September 26, 2025, 11:59:53 pm
content: Quote from: mtwieg on September 26, 2025, 08:13:10 pmFull trace inductance refers to the entire trace loop inductance to VDD and the return. Based upon expected worst case dI/dt one can make the decision IF the cap with lowerELSESL or ESR produces the least VDD glitch/ripple disturbance.Best

author: mtwieg
author_rank: Frequent Contributor
timestamp: September 27, 2025, 01:47:53 pm
content: Quote from: mawyatt on September 26, 2025, 11:59:53 pmOk, but I can't tell if you're agreeing with me or not... would you put the smaller C1005X5R1E225K050BC or the larger CGA8P1X7R1E226M250KC cap closer to the supply pins of the fast cmos chip?

author: mawyatt
author_rank: Super Contributor
timestamp: September 27, 2025, 02:51:37 pm
content: Quote from: mtwieg on September 27, 2025, 01:47:53 pmIf it's a fast clocked CMOS Digital chip, then the cap with the higher ESL will likely produce a larger glitch at the clock edges. As mentioned chips with a wider aspect ratio have lower ESL and ESL tends to follow and dominated by the physical chip cap length. ESR generally is lower with physically larger chip caps.Without the specifics of the CMOS di/dt (in large fast CMOS chips the aggregate di/dt can go well past GigaA/s, altho this gets distributed over the multiple chip VDD and Ground pads) it's hard to give a generalized solution. Here a good EM simulator can help with the PCB layout and details of the package/chip layout to create a model that is distilled into a lumped element equivalent and ported to SPICE along with accurate chip cap lumped element models.BTW the wider aspect ratio low ESL chip caps originated long ago in the MW world and when the CMOS became so fast edge-wise this wide aspect ratio low ESL chip cap construction migrated to chip cap decoupling. Ironically the very fast ECL/CML logic is much easier to properly decouple than modern CMOS because of the di/dt edge rate, whereas ECL/CML is more of an "analog digital" than fast digital CMOS.In todays advanced nanometer CMOS, the NMOS devices can have ~1/2 THz fmax. A few decades ago recall a researcher at University of Florida achieved a >400GHz NMOS oscillator in 32nm CMOS (clever measurement technique if interested), so this modern CMOS di/dt shouldn't be a surpriseBest

author: Siwastaja
author_rank: Super Contributor
timestamp: September 27, 2025, 03:06:08 pm
content: I don't think there is generic answer for "which to place closer" when using two different capacitor values in parallel. Let's remember, that's not the good default strategy for wide-band power supply bypassing to begin with. It is used for narrow-band extra bypassing at some specific problem frequency (at the SRF) and as such is very sensitive to both variations of L and C because SRF is inversely relative to sqrt(L*C). Exact placement of that smaller capacitor then affects the L and as such SRF. So while you tune correct value of C, you would also be tuning placement. In 99% of power bypassing needs we avoid doing this completely and use single largest possible capacitor value in smallest possible package, for minimized impedance over widest possible frequency range.

author: TimFox
author_rank: Super Contributor
timestamp: September 27, 2025, 03:25:59 pm
content: Quote from: mawyatt on September 27, 2025, 02:51:37 pmThe nice thing about old-style ECL logic is that much of it runs in "Class A" with a constant current drain from the power supply. To avoid saturation in bipolar transistors, the basic circuit uses long-tailed pairs where the transistors are always conducting.The bad thing about old-style ECL is that the power dissipation is huge due to the constant drain from the power supply. As stated above, they are easier to bypass due to the relatively-constant current drain.

author: MrAl
author_rank: Super Contributor
timestamp: September 27, 2025, 06:53:35 pm
content: Quote from: khatus on September 24, 2025, 02:16:02 pmHi,Usually the focus is on the inductance once you have chosen an appropriate capacitor value. For example, you might need 100uf, so you go out and look for a 100uf capacitor. Now since the inductance interferes with the ability of the capacitor to shunt unwanted signals to ground, you go for low inductance. So this means that the text of the article you read is a little misleading.Capacitors are good at shunting signals to ground because they have low impedance with increasing frequency, and any AC in this kind of application is unwanted. Inductors, on the other hand, have poor ability to shunt signals to ground. They actually try to prevent higher frequencies from being shunted and thus we don't want much inductance. We want as low of an inductance as we can get in series with the capacitor.If you hold the capacitor value constant and decrease inductance, you get a higher resonant frequency, and that is hopefully going to be beyond any frequencies in your system.PCB trace length also adds to the inductance. That is why capacitors have to be placed close to the devices they are trying to help reduce power supply variations for. The old TTL series logic was notorious for this and so the PCB had to be littered with 0.1uf caps to help shunt switching noise on the power supply lines to ground.

author: mtwieg
author_rank: Frequent Contributor
timestamp: September 28, 2025, 01:32:44 pm
content: Quote from: mawyatt on September 27, 2025, 02:51:37 pmAgreed. Once you have several groups of capacitors distributed across a power plane, things can get very messy. Fortunately, it rarely actually matters.I went ahead and did a rough simulation with the two capacitors I mentioned above, using TDK's SPICE models. Top plot shows the impedance of each cap alone. They are connected to each other with an inductance of 0.5nH. The bottom plot shows the impedance of that combination. Green is looking directly at the smaller cap, blue looking at the bigger cap:No surprise, connecting the smaller cap closer to the chip gives lower impedance at high frequencies. In the range of 1-4MHz, the impedance is actually higher, but unless you have something generating currents in that specific frequency band, it's still better overall.It would actually be very interesting if vendors offered "damped" MLCCs with slightly higher ESR, such that their self resonant quality factor is low. Here's that same simulation, but with the ESR on each cap increased by roughly a factor of three. Now which capacitor is closest matters much less:If you really wanted to avoid "peaks" in your supply impedance, this would an optimal way to get it. Hans Rosenberg's video above mentions this, but adding discrete resistors in series with each cap would add significant ESL, not really applicable to very high frequency.QuoteI think the difference comes down to differential vs single ended logic. Differential logic inherently produces less supply transients, and is less sensitive to them as well.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 28, 2025, 03:04:05 pm
content: Quote from: Siwastaja on September 27, 2025, 03:06:08 pmAlso with modern high density PCBs using power planes, capacitor placement doesn't matter that much. Inductance of a power/ground plane pair with a thin dielectric is very low and grows only as log(distance). For many reasonably situations the placement just isn't that sensitive.This is different on a 2 layer or 4 layer board, or if you don't have power planes for the relevant supply.

author: mawyatt
author_rank: Super Contributor
timestamp: September 28, 2025, 03:18:24 pm
content: Quote from: mtwieg on September 28, 2025, 01:32:44 pmThis was why tantalums were popular, and good ceramic chip cap and a tantalum made a good, simple decoupling combo."I think the difference comes down to differential vs single ended logic. Differential logic inherently produces less supply transients, and is less sensitive to them as well."Differential certainly helps, but ECL/CML is fundamentally a non-saturating logic that draws the same supply current in either state. This creates a somewhat constant supply current (a big disadvantage for power) and only has moderate "glitches" during edge transitioning. We had ECL/CML in SiGe approaching 100GHz rates and decoupling was relatively easy with a small on-chip decoupling cap followed by an in package ceramic chip cap and a local PCB ceramic cap. Granted we did chip/package/PCB EM and SPICE simulations to verify things as custom chip re-spins are expensive and career limiting (always trying to keep Murphy at bay!!).Best

author: TimFox
author_rank: Super Contributor
timestamp: September 28, 2025, 04:20:25 pm
content: I haven’t done this kind of work in years, but I remember at least one vendor offering “mode free” SMD capacitors with specific construction to eliminate resonant effects, compromising loss while achieving this.I designed one such component into a circuit to avoid problems on a high-speed data transmission coupling circuit.Initially, the manufacturer had difficulty keeping up with demand, but I haven’t had need for that since.

author: mtwieg
author_rank: Frequent Contributor
timestamp: September 29, 2025, 11:21:02 am
content: Quote from: mawyatt on September 28, 2025, 03:18:24 pmI was about to respond "would be nice if tantalum were available in 0402" but it looks likethey actually are now! But the ESR is more like 100x that of a similar MLCC, wish there was something "in the middle".Quote from: TimFox on September 28, 2025, 04:20:25 pmInteresting. I wonder if it actually had increased ESR, or had a very low ESL structure like X2Y caps or SLC.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 29, 2025, 11:53:22 am
content: Quote from: mtwieg on September 29, 2025, 11:21:02 amWondered too why "moderate-ESR MLCCs" so specialized and scarce. They would hit two birds with one stone: offer soft terminations for improved reliability against board flex / soldering, and those terminations would be resistive to offer controlled ESR to act as drop-in replacement for tantalums capacitors. Like, maybe 0805 or 1210 2.2uF part with 1 Ohm or so ESR would be pretty handy for some linear regulators, or hot plug dampers. And you really can't use tantalums for hot plug damping so the MLCC-equivalent would be even better. Only inferior in the capacitance DC bias, tantalums offer pretty stable capacitance but often you don't need that, you use them for their stable ESR.

author: mtwieg
author_rank: Frequent Contributor
timestamp: September 29, 2025, 12:31:38 pm
content: Quote from: Siwastaja on September 29, 2025, 11:53:22 amThis gave me an idea: maybe soft-termination MLCCs have higher ESR? Looked at a comparison of 100nF 0402 caps from TDK, and yes they are a bit higher, but not enough to be really damped. And three times as expensive in bulk. See attached document.