Very long shift register chips? - Page 1
Forum section: electronics / beginners

author: Infraviolet
author_rank: Super Contributor
timestamp: December 28, 2022, 11:18:19 pm
content: Do they exist? I'm pondering a project which would involve the use of a shift register several hundred bits long, it wouldn't have parallel output pins for all of those hundreds of bits, but I'd need to shift in several hundred bits (256 or 512 would be adequate suzes), then shift them out a little later. So in effect this would be like a cascade of 256 or 512 flip flop ICs. I would be shifting bits faster than a typical microcontroller clock speed, so using one to emulate this behaviour wouldn't do. One could buy a large number of shift register if flip-flop ICs, but that would get quite priecy quite fast (even though they are lower priced than a lot of other chiptypes) and take colossal board space, and likely have horrifically high power consumption too. Are there single chips which act like a several hundred bit shift register? What is the name for such types of IC if they exist?Thanks

author: langwadt
author_rank: Super Contributor
timestamp: December 28, 2022, 11:22:46 pm
content: how fast?

author: Kleinstein
author_rank: Super Contributor
timestamp: December 28, 2022, 11:34:14 pm
content: There were long shift registes in the old days, uses as momory in early computers. Not sure there were 256 bits, I vaguely remember 1024. One may still find some as antiques. Chances are they are rather slow, old CMOS logic.

author: ataradov
author_rank: Super Contributor
timestamp: December 28, 2022, 11:57:59 pm
content: How fast indeed? You may not be able to sample things fast enough with GPIO of the MCU, but using 2 SPI peripherals may give you enough time to process 8 bits at a time internally.And then there is RP2040 with PIO, which is almost certainly faster than any obsolete ICs you may find.If that's not fast enough, then FPGA is the way to go. There are some easy to use low pin count devices from Lattice that would certainly work.

author: jmelson
author_rank: Super Contributor
timestamp: December 29, 2022, 02:14:34 am
content: Quote from: Infraviolet on December 28, 2022, 11:18:19 pmProbably the best way to do this is with an FPGA. You could set up several thousand bits in a small FPGA chip as you want.Jon

author: Martian Tech
author_rank: Regular Contributor
timestamp: December 29, 2022, 03:14:13 am
content: Long obsolete and probably too slow:MM5057 (512 bits, 1.5MHz)Am2857 (512 bits, 2.5MHz)Would a FIFO work instead?SN74ACT2229 (Dual 256x1, 60MHz)or, if you need more than 1 bit wide:SN74ALVC7804 (512x18, 40MHz)others exist as well...

author: dobsonr741
author_rank: Frequent Contributor
timestamp: December 29, 2022, 03:29:51 am
content: A 4116 vintage DRAM! It was used in the EVL EG1000 digital echo as a delay line for serialized digitalized audio.

author: JustMeHere
author_rank: Frequent Contributor
timestamp: December 29, 2022, 07:34:25 pm
content: Does this 64-bit shift register I found on Digikey work?MC14557BDWGAlso see this, which is a "dual element" 64 bit. This one looks a bit faster. It's under a dollar. Don't know much about these things.CD4517BE

author: james_s
author_rank: Super Contributor
timestamp: December 29, 2022, 08:16:39 pm
content: A CPLD is a relatively trivial way of doing this.

author: langwadt
author_rank: Super Contributor
timestamp: December 29, 2022, 08:58:04 pm
content: Quote from: james_s on December 29, 2022, 08:16:39 pmisn't +256 FFs rather big for a CPLD?

author: AndyC_772
author_rank: Super Contributor
timestamp: December 29, 2022, 09:02:08 pm
content: I'd use a small FPGA for this. As a bonus, it could probably also soak up most of the other logic in the design too.

author: Infraviolet
author_rank: Super Contributor
timestamp: December 30, 2022, 03:27:26 pm
content: The RP2040's PIO looks a pretty good thing to try, thanks.I've looked at some SRAM chips' datasheets too, and think I can see how they might be used too.Thanks for the 64 bit shift register links, but 64 bits is too short for my usage, I could perhaps cascade them rather more easily than 8 bit registers, but it could still take quite a bit of board space.

author: ataradov
author_rank: Super Contributor
timestamp: December 30, 2022, 05:28:05 pm
content: What clock frequency do you need? You may be able to get away with a cheap and small MCU with SPI peripherals. And if combined with DMA, you may not even need to do anything in the firmware at all.

author: Infraviolet
author_rank: Super Contributor
timestamp: December 30, 2022, 05:39:13 pm
content: I'm uncertain about the exact frequency as yet, but it wold be in the 20MHz to 100MHz range. I don't think a microcontroller with SPI could do it because they are usually limited to taking in just a byte at a time on the peripherals? and I'll have a continuous stream of data for several hundred bits. I don't think a typical SPI peripheral in an MCU can store all this and then clock it out in to the MCU after the several hundred bits message has finished, I don't see any hope of getting the start of the message in to the MCU while the middle or end of the message is still arriving. Some of the SRAM chips I've looked at seem to be able to handle hundreds of bits being fed in so long as they are preceded by a few bytes indicating the address to start filling from.

author: ataradov
author_rank: Super Contributor
timestamp: December 30, 2022, 06:21:59 pm
content: One byte at a time gives you 8 times the SPI clock to process the data. And combined with DMA you may not need to do anything at all in the firmware.Your limiting factor here would be pad bandwidth and ability to get that signal into the device. And 100 MHz would be next to impossible on most MCUs, including RP2040. This also includes SRAM. There is no SRAM that would work at 100 MHz clock. Well, there are, but your choices would be limited, since you are going against the limit here.And 20 MHz is doable trivially on very cheap stuff. So, you'll have to narrow the range to get a better idea of what might work.

author: Terry Bites
author_rank: Super Contributor
timestamp: December 30, 2022, 06:29:16 pm
content: If you dont need to get at the taps, then what function is it performing.You can create very fast circular buffers with RAM controlled via a uC or dedicated address counters.Very wasteful though.You may find this of some interest.https://vhdlwhiz.com/shift-register/

author: fourfathom
author_rank: Super Contributor
timestamp: December 30, 2022, 07:08:07 pm
content: As has been mentioned, a small FPGA ca easily do the job. I'm using a Lattice LCMXO2-1200HC-6SG32C (QFN-32 package) in a project and it has plenty of RAM blocks available. I've got a part of my FPGA configured as a 32-bit wide FIFO, 1024 words deep, and am clocking it at 100 MHz with plenty of timing margin. That's 32-times faster than you are thinking about. Adding a serializer and deserializer shoulf be trivial. The part (when you can get it) costs about $8. There are smaller FPGAs in that series that could still easily meet your requirements. It looks like the BGA and high pin-count parts are more available than the lower pin-count non-BGA parts. I suppose other vendors will also have useful FPGAS.

author: Ground_Loop
author_rank: Frequent Contributor
timestamp: January 01, 2023, 12:50:38 am
content: I snagged one of these out of an old piece of equipment some time back. It's a dual 256 bit recirculating shift register and supposedly good to 2.5MHz. So yes, they exist.