Best ADC for low latency, audio frequency range - Page 1
Forum section: electronics / projects

author: rsridhar
author_rank: Contributor
timestamp: July 17, 2018, 10:06:51 am
content: Hi all,Im working on a project where speed is critical. I planned to use (and already ordered) Sigma-delta ADCs and DACs, but I now see a huge flaw in my plan: the filter delays. The delay on the ADC and DAC would cause over a 2 cycle delay at 2kHz! I want my usable range to be at least 2kHz; and over my usable range there can't be more than a 1 sample delay.What are my other options for ADCs and DACs? What type of ADC other than sigma-delta would you recommend? Essentially, Im looking for a combination of high conversion speed and data quality. Im assuming my fs will be ~48k; audio range but this isnt set in stone, if there are other better options.Thanks for the advice!

author: b_force
author_rank: Super Contributor
timestamp: July 17, 2018, 11:16:15 am
content: What other specs do you need?(SNR, THD+N etc)And why do you need such low latency?They don't always specify the latency in the datasheet.The mean reason for that is it's underneath 1-5ms, which is fast enough.

author: coppice
author_rank: Super Contributor
timestamp: July 17, 2018, 01:18:49 pm
content: At 48k sps, one sample delay converters up to 16 bits or so are readily available. Beyond that you are into specialised territory, and the price can rise rapidly. Because very few audio bandwidth applications care too much about delay, a high volume, low cost, market for this type of converter hasn't developed. Even in real time applications, like feedback control and musical instrument processors, the delay in the DSP is usually so great that the delay in the converters does not dominate.

author: JS
author_rank: Frequent Contributor
timestamp: July 17, 2018, 01:25:34 pm
content: At higher sample rates all happens faster, which means lower latency, then if you have the processing power and can deal with only old samples (output considering last samples and older, not wait a few more to take the decission) you can respond fast. Lets say you run at twice the sample rate, filters could still take 2 samples would mean half the time, even if you go 4 times the SR filter might take 3 or 3 samples. Now, sampling at 192kHz for a 2kHz response seems overkill but if you need to react fast might be your option.Now, what are the specs you are trying to reach?JS

author: rsridhar
author_rank: Contributor
timestamp: July 17, 2018, 01:47:35 pm
content: Im using this for feedback control of vibration (with an actuator), which is why I need the low latency. Im trying to implement an N-point FIR filter (time domain convolution, very computationally expensive) as the control loop. Im using an FPGA and fixed point math (optimized to maximize my dynamic range) to make things run quickly within one sample.I work for a company that makes dynamic signal analyzers and vibration controllers; but Im coming from the Mechanical Eng side and am really curious if this sort of controller is possible (this is a project Im doing on my own after EEVblog videos piqued my interest in HW design). My company use such filters for controlling complex mechanical systems; but they are implemented in the frequency domain so the application of the FIR filter reduces to N/2 multiplications every N time samples. This means they are much less computationally demanding and run fine on a DSP, but can't operate in true sample-by-sample realtime as everything is based on FFT blocks. We use sig-delta ADCs and DACs which give us great performance, but since we operate in FFT blocks w/ a 1 block delay the slight ~80sample delays added by the filters in the ADC/DAC are insignificant.Other specs arent as important; as from a control perspective even a few degrees of phase delay will make the system difficult to control. So, as far as other specs go, Ill take what I can get. The average delay (from the FIR filters in the ADC/DAC) on the sig-del ADC/DACs Ive been using is around 40 samples each; 80samples roundtrip at 48kHz.@coppiceDo you have an example of a 16bit 48ksps 1 sample delay ADC/DAC? This would likely do the trick...@JSMy complete data path is:ADC Sample->FPGA->Time domain convolution with N point filter h(n)->DACThis needs to happen in 1 sample; and as I mentioned Im running with fixed point math on an FPGA so increasing my sample rates wont throw anything awry. Ive considered running my ADC/DACs in 192kHz mode; their delays are around 18sample round trip if I do so, which is much better but still comes out to a 33deg phase delay at 2kHz. This may work for my needs...but the performance would not be optimal.I did actually purchase the ADS1675IPAG sigma-delta ADC yesterday (its still shipping) which runs at 4MHz; so its filter delay of 28sample is virtually insignificant for my purposes. But I was not able to find a sigma-delta DAC that runs at this speed; only 192kHz. If this ADC does the trick; I guess my problem is then only on the DAC side.

author: b_force
author_rank: Super Contributor
timestamp: July 17, 2018, 02:08:05 pm
content: You might try the ADAU1761 which is a a low latency DSP with ADC and DAC on board.Normally used for fast feedback systems in microphone arrays and such.Otherwise I would recommend using the FPGA and "building" your own fast ADC.Since you're already using one, that would be the best way to go.

author: rsridhar
author_rank: Contributor
timestamp: July 17, 2018, 02:16:20 pm
content: a DSP will likely not be able to keep up with the time domain convolution. My bigger goal though is to try and apply this to a multi-actuator system; in which case the number of computations per data sample can easily go into the billions. Im guessing that, if I do get to that point, Id be running on multiple FPGAs.Looking at the ADAU1761, its delay specs seem about the same as the ADC/DAC Im currently using, 23+11 samples for the ADC/DAC.@b_forceWhat do you mean by "building" a fast ADC? is this possible on an FPGA? Sounds like it woulndt be trivial though...

author: Marco
author_rank: Super Contributor
timestamp: July 17, 2018, 02:51:53 pm
content: Do you need 16+ bits? The Linear SAR ADCs can do that, for a price ... the SAR ADC in say a STM32F7 is zero latency as well.

author: Kalvin
author_rank: Super Contributor
timestamp: July 17, 2018, 02:56:19 pm
content: FIR filter with N taps has a delay of (N-1)/2 samples. Source:https://dspguru.com/dsp/faqs/fir/properties/

author: Marco
author_rank: Super Contributor
timestamp: July 17, 2018, 03:05:05 pm
content: Quote from: rsridhar on July 17, 2018, 02:16:20 pmAs usual in these topics I feel compelled to point out that time/frequency domain filtering are not mutually exclusive and you can do most processing in the frequency domain even with zero latency. You just take the first say 64 samples of the impulse response and implement it with FIR, then you do the next 64 with FFT, the next 128 with FFT, the next 256 with FFT etc.

author: b_force
author_rank: Super Contributor
timestamp: July 17, 2018, 03:21:03 pm
content: Quote from: rsridhar on July 17, 2018, 02:16:20 pmWell, I used to work for a company that makes a custom chip for PWM controllers with fast feedback loops.(and actually some kind of FIR filtering, out of band noise shaping etc)The original prototypes were just FPGAs, so yes it is definitely possible.Can't recall what the latency was, but it was pretty short.Don't forget to calculate in the time it takes for the FIR filters.

author: JS
author_rank: Frequent Contributor
timestamp: July 17, 2018, 03:57:55 pm
content: The DAC in the fpga is a option to consider, you need a bunch of outputs and matched resistors but it will output the signal as soon as it's there and you then need to consider the analog filter at the output as a delay, the order 0 filtering is already done by the fpga, next you might like to add one or two poles.How many bits do you need here? As input and output?JS

author: rsridhar
author_rank: Contributor
timestamp: July 17, 2018, 04:05:51 pm
content: Quote from: Kalvin on July 17, 2018, 02:56:19 pmI believe this is for linear phase filters; mine certainly will not be linear phase as the coefficients come from an impulse response (from an FRF measurement). I know I will have some delay; and at some point will have to make an engineering choice or simply accept that it only operates at lower frequencies. Im still doing experiments a mechanical to see how long the delay is, for various N and Fs's values. To do this test, Im generating a drive signal to send to my actuator based on the FRF and a desired reference time signal. Then, Im going to overlay the resposne that drive signal has when played back to the actuator with the original reference that was used to create it. Comparing the two should give me a sense of the delay introduced by the N point convolution.Quote from: Marco on July 17, 2018, 02:51:53 pmThat is exactly what I need. Definitely at least 16bits; the dynamic range of vibrating systems' FRFs can get into the 100+ dB range easily. I will take a look at some of these after experimenting with my sigma-deltas for a bit more.Quote from: Marco on July 17, 2018, 03:05:05 pmI have never heard of this sort of processing before (unsurprisingly); part in time part in frequency. Can you link me to an article or page describing it please?Quote from: JS on July 17, 2018, 03:57:55 pmI think the reconstruction filters should be significantly high in frequency 9above my 2kHz max freq) so that their effect is small; but yes I havent considered that as yet.I need at least 16bit; 24 would be ideal as some mechanical systems can require 130+dB dynamic range to quantify. Need it on the input and output.Thanks all! I think I have plenty to keep myself busy for the next few weeks.

author: Marco
author_rank: Super Contributor
timestamp: July 17, 2018, 05:06:09 pm
content: Quote from: rsridhar on July 17, 2018, 04:05:51 pmI have a couple of links inthis post.

author: MasterT
author_rank: Frequent Contributor
timestamp: July 17, 2018, 05:59:40 pm
content: 16-bits SAR:https://www.mouser.ca/ProductDetail/?qs=aGgfWYEhH7nvSWCBX8tnyA==

author: coppice
author_rank: Super Contributor
timestamp: July 17, 2018, 06:15:48 pm
content: Quote from: rsridhar on July 17, 2018, 04:05:51 pmWhether the filter is linear phase is largely irrelevant to the inherent algorithmic latency it introduces, and it really doesn't matter whether you are using an FIR or some other type of filter. An impulsecausesits impulse response. This issue of causality means all the interesting stuff that goes into your filter happens after the impulse. It might be the impulse response dies really quickly after the impulse, or it might die very slowly, but until it has dropped below the threshold that is important to you, you can't get an output from the filter. This kind of delay is usually far longer than the delays caused by sigma-delta converters, and so the converter is not the dominant source of algorithmic delay in most cases.

author: mark03
author_rank: Frequent Contributor
timestamp: July 17, 2018, 07:56:48 pm
content: Quote from: coppice on July 17, 2018, 06:15:48 pmThis is not true, if I am reading you correctly. You can produce the first sample of the impulse response the instant the impulse comes in. Think about how nature works. Linear systems in the natural world don't have to wait for the length of their impulse responses before producing first output, do they?The oft-quoted (N-1)/2 delay, as already mentioned, only applies to linear-phase filters. Linear phase implies (and is implied by) symmetry or anti-symmetry in the impulse response, which is where the (N-1)/2 sample group delay comes from.The real question is, how do you perform the convolution efficiently (that is, in the frequency domain) without imposing a latency equal to the block size. And the answer is what Marco said, partitioned convolution. If you'd like to learn more, a key google search term is "frequency delay line." I also recommend Frank Wefer's thesis, "Partitioned Convolution Algorithms for Real-time Auralization":http://publications.rwth-aachen.de/record/466561/files/466561.pdf.If you can live with, say, four or eight sample latency, you can do the whole thing in the frequency domain using one section of short FFTs and another section of long FFTs; this is called a "nonuniform partition."I'm using similar techniques right now to implement multi-thousand-tap FIR filters on a Cortex-M7 MCU for active noise cancelation. No coincidence, you see this stuff a lot in ANC and in your application, which is basically the same thing. Also in adaptive echo cancelers. Things get fun when you need to make your long FIR filter adaptive, using LMS or something even fancier.

author: coppice
author_rank: Super Contributor
timestamp: July 17, 2018, 08:49:33 pm
content: Quote from: mark03 on July 17, 2018, 07:56:48 pmIn an echo canceller you train an adaptive filter to match the impulse response from the transmit side to the receive side. You then apply this to the recent history of the clean signal, to obtain a hopefully good match for the current echo at the receiver. You then subtract that from the received signal, to remove the echo from it. In this you are creating the impulse response of the original signal, and subtracting it. Here, the current state of the signal depends only on its past - to depend on the future would break causality.In most control loops roughly the opposite occurs.You are filtering a dirty received signal, which has been modified by the impulse response of the system, to arrive at something close to a clean version of the signal. Since the clean signal caused the dirty signal, you can only filter back to the clean signal once you have a whole impulse response period of the dirty signal available - you have inherent algorithmic latency before you can create the output of the filter, because you cannot break causailty. If you look at most control loops, they use very elementary filters, purely to keep the algorithmic latency as low as possible, and allow the highest loop bandwidth to be used.As you said the (N-1)/2 delay comes from linear-phase filters, where the amount of signal in the filter window is balanced around the group delay point. Most FIRs don't have the group delay point bang in the middle, but they don't have it an one end, either.

author: JS
author_rank: Frequent Contributor
timestamp: July 17, 2018, 09:09:02 pm
content: The problem is to fill the buffer on start up, once in steady state youcan react as the signal is coming in. For this you can start slow enough, with some inital conditions setted, with a non linear response or with a different filter at start, then the steady state loop takes control.JS

author: rsridhar
author_rank: Contributor
timestamp: July 18, 2018, 02:04:29 am
content: Quote from: mark03 on July 17, 2018, 07:56:48 pmI will check those links out. This is quite interesting, I never took any advanced DSP courses so this is all new to me.Sound and vibration are; from a signals standpoint, ideitical (same freq range). But the extension Im gunning for here is for MIMO control; esentially using actuators to cancel out vibrations in solid structures. This is something my company does, but not in realtime (block based). In audio, this would amount to controlling the SPL at certain points in space, which may not be too useful since every other point will have sound. But because of the way structures vibrate, cancelling the vibration (modeshapes) in a MIMO fashion will make the whole body rigid at that frequency.QuoteHeh. funny you mention that, LMS happens to be one of my company's competitors, ill just say that my company's products are in the "something fancier" categoryMy ultimate goal is exactly what you said. If this project works, Im hoping to add it to my company's dynamic signal analyzer and have it automatically update the filter taps based on the realtime FRF measurement.Quote from: mark03 on July 17, 2018, 07:56:48 pmThat was exactly what I was thinking. I cant imagine how convolving with an impulse response of a mechanical system - for which last 4/5 of the filter taps are essentially 0 - could have the same group delay as a symmetric time pulse which takes up the whole window.

author: mark03
author_rank: Frequent Contributor
timestamp: July 18, 2018, 03:57:25 am
content: Quote from: coppice on July 17, 2018, 08:49:33 pmAh, I think I understand what you're saying now. I would argue that this is not algorithmic delay, because whatever delay is induced by the filter is *supposed* to be there. When such a filter is implemented on a DSP with what I am calling "zero latency," the input/output relationship perfectly matches a textbook signal flow diagram (often a box with a capital H in it): no latency is added by the details of the algorithmic implementation.

author: mark03
author_rank: Frequent Contributor
timestamp: July 18, 2018, 04:09:20 am
content: Quote from: rsridhar on July 18, 2018, 02:04:29 amActually, MIMO ANC systems are frequently used, for exactly the reason you state, that a SISO system can only control the SPL at a single point in space (actually a small region dictated by the acoustic wavelengths of the noise spectrum). With additional speakers and microphones you can extend "decent" noise cancelation over a larger volume. I was under the impression that MIMO ANC systems are standard in luxury cars, although I have no direct experience in that area (not automotive ANC systems, nor fancy cars).QuoteIf you would like to delve more deeply into the intersection of adaptive filters and partitioned convolution / frequency delay lines, I can recommend G.P.M. Egelmeers' PhD thesis:https://pure.tue.nl/ws/files/1510206/448298.pdf. Just beware, you're jumping into the deep end now! Have fun.

author: rsridhar
author_rank: Contributor
timestamp: July 18, 2018, 03:18:33 pm
content: Quote from: mark03 on July 18, 2018, 04:09:20 amMy company actually makes an acoustic controller which is used in high intensity acoustic tests (where they point loud horns at a spacecraft to ensure it can stand the acoustics of launching into space). Our specialty is vibration control, and mimo vibration control though. Doesnt get used much though; we really only have it because its esentially just a GUI wrapper over our vibration controller.Thanks for sharing. Ill definitely look into this as I progress on this project. Im still relatively new to hardware/fpgas so Im guessing it will be a few months before I can even get a prototype working. Then Ill get into the efficiency of the algorithm.

author: coppice
author_rank: Super Contributor
timestamp: July 18, 2018, 06:56:20 pm
content: Quote from: mark03 on July 18, 2018, 03:57:25 amThe usual term for this type of delay in DSP circles is algorithmic delay. In this case, if you choose to use a straightforward convolution for the filter, you get this much delay, which no form of implementation can get below. Of course, many implementations introduce another level of algorithm (e.g. bunching samples for efficient processing on many programmable DSPs) with its own algorithmic delay.

author: fonograph
author_rank: Frequent Contributor
timestamp: July 18, 2018, 07:26:55 pm
content: What kind of FIR filter have shorter preringing than 2 sample at 48 KHz samplerate and audio frequencies? Becose its FIR filter,you must wait the whole lenght of pre ringing,and that can I believe in your case and large bit depths like 16 or more bits be very long.

author: JS
author_rank: Frequent Contributor
timestamp: July 18, 2018, 11:38:49 pm
content: Quote from: fonograph on July 18, 2018, 07:26:55 pmI don't think he had decided the algorithm yet, but with FPGAs you can get the output quite shortly after the last sample comes in, as you already can have all the other samples pre processed, multiply the last one add and out it goes. It's only limited by the mesh size but she should be right.For working on the algorithm before having the hardware is possible with controlled signals, even if you have quite a bit of lag you could recreate the signal in the lab, so capture, process, recreate and use the processed signal. Or do a periodic signal and control a delay for n periods sync. Once you get the algorithm working this way you know how much processing power you need from your FPGA and how much lag you can live with. Then emulate in different FPGAs so you know which will cut it. That's good for design as you know with which FPGA you need to build the system and not trial and error till you get the fitting FPGA, which will be quite expensive and time consuming considering you need to make new PCBs for each FPGA.JS