Full bridge driver ringing problem - Page 1
Forum section: electronics / beginners

author: wlamb02
author_rank: Newbie
timestamp: October 28, 2018, 06:34:55 am
content: This is my first time designing a full bridge driver. I am experiencing problems with ringing on the output. I have made a pcb for it. This is a picture of the top side of the board.BacksideInput to L6498 Drivers, 250ns dead timeUnloaded output voltage of the full bridgeOutput with unloaded transformer attached showing lower frequency ringingCH1: Transformer Voltage CH2: Transformer currentFull setupThe problem I have is with the oscillation at the top of the output waveform when a load is attached. Applying a load to the transformer only makes ringing worse. I have tested the gates of all the mosfets and the waveforms are very clean with no spikes even when the transformer is loaded. The only problem is with the bridge output waveform. The board has a 1uf film capacitor in the center of the board. I have tried adding a 2200uf capacitor right at the main voltage rail next to the mosfet as shown in the image below. I also have a current transformer to measure the capacitor current.The output waveform improves with transformer still connected when electrolytic cap is added. CH1 : Full bridge output voltage CH2: Electrolytic capacitor current.The problem with this is: the electrolytic cap gets warm under very light loading of the full bridge. At high loads the current through the capacitor was about 30 amps at the peak. The capacitor was very hot. If adding more capacitance to the supply rail would improve the ringing, what kind of capacitor should I use? Would a larger film capacitor help the ringing? Is the ringing a layout problem? If so, should the pcb power traces be shorter?

author: mk_
author_rank: Regular Contributor
timestamp: October 28, 2018, 07:45:28 am
content: Quote from: wlamb02 on October 28, 2018, 06:34:55 ammuch to small and way to long wires between Driver and FETs (the ucc27714 dumps up to 4A in 30ns into and from a Gate), wrong measurement as you used your probe with the long gnd-wire instead of the spring. Gate-Resistor should be in a bigger housing (1210, 2512 or similar) as there could be a lot of power during charging and discharging the gates.Quoteother capacitors with better specs, _more_ capacitors to share the current (take care so that they are connetected with more or less same distance to your load), better cooling (some mm distance between capacitors so that air coud flow between them) place them ob both sides (left & right) of your print so that the current has "short" distances from C to FETRead Chapter 10 in the ucc27714-Datasheet and mind those words, read related Application NotesNever ever measure with 1:1 Probes, always with 10:1, better with differential probes as at those frequencies common mode problems are usual...good luck

author: Benta
author_rank: Super Contributor
timestamp: October 28, 2018, 09:11:09 am
content: Far too long wires between power stage and transformer.Shorten them and it should improve.I doubt that you can remove the ringing completely, part of it is probably due to inter-winding capacitance in the transformer. Careful winding layout could perhaps help.

author: filssavi
author_rank: Frequent Contributor
timestamp: October 28, 2018, 09:22:31 am
content: As others already said the main problem is high parasitic inductance in series with the gate since the traces are long and skinny, usually you want your driver as close as humanely possible to the gate pin.Also when talking about gate signals where you have significant di/dt and dv/dt from the switching transistors the correct probing technique becomes vital. As it could very well be that the ringing you see is not actually there but is picked up by the antenna (ground lead)So probing with a ground spring is the best choice, you only have to be extremely careful as it is easy to slip your hand and short stuff out. Alternatively you can use a piece of modwire(kynar insulated wrap wire) soldered in circuit and wrap it tightly around the ground connection on the probe (also keeping it as short as feasible). You should thus be able to balance the probe on itself and do the measurements hands free

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 28, 2018, 06:33:33 pm
content: Quote from: wlamb02 on October 28, 2018, 06:34:55 amYes, you have found precisely the problem.Consider this: the full AC current, from the load, must flow into and out of the supply rails (give or take phase). Any loop area, between DC+, switching nodes, and DC-, is inductance that must be accounted for. Any load current, manifest as DC supply ripple, must be accounted for.That the electrolytic gets hot, is proof that you need more of them, not less! A 30A load draws, well, about 30A from the supply, so you need 30A worth of capacitors there. (It's actually more like 15A because of switching back and forth, so that's nice at least.)Note that stray inductance is proportional to length (of the wires/traces used, for a given  cross-section between +/- wires), or roughly to enclosed area (of a generic loop). Every mm of trace length you introduce, is another nH or so of stray inductance, and that puts V = L * dI/dt right in series with that trace and anything connecting to it.The full bridge doesn't win you anything here. Treat it as two half-bridges sharing a supply. The supply ripple current is about the same. The dI/dt within each half bridge must be managed -- that's where your ringing is coming from. The two half-bridges can be kind of anywhere, as long as you mind that AC load current is flowing between them -- in one and out the other. I guess you aren't minding inductance in this path as much, given the long leads to the transformer, and the apparently simple windup of the transformer. (Or maybe that's the next issue to look at, I don't know.)The root problem is also a lesson: current does not simply flow in conductors. AC current flowsbetweenconductors, as a transmission line. There is always a nearest opposing conductor, which the "image" or return current flows in.The impedance of that transmission line can be easily calculated for standard cross-sections, and hand-waved for intermediate cases.The transmission line impedance and length directly gives the stray inductance of the design. (Stray inductance is usually the desired result, because the switching impedance, Vsupply / Ipeak, is a lot lower than the transmission line impedance, and so inductance dominates. But when it's the other way (in low current, high voltage applications), capacitance dominates!)You're probably running too low of an impedance even for this to be a slam-dunk solution, but it will still help greatly: rip up your layout, and change to a ground plane based design. Easiest, add internal layers for BUS+ and BUS-, and swallow the cost of a 4-layer board (which really isn't much at all, these days). Now the current loop is between, not side by side traces (the highest impedance geometry you can have!), but between a trace flat against a ground plane (the lowest you can have!). The side-by-side case might have an impedance of 100-150 ohms; the ground-plane case, more like 20. That a five-fold (or better) reduction, which means the ringing frequency will be at least sqrt(5) times higher, and maybe its impedance (the resonant impedance is sqrt(L/C), where L = stray inductance and C = Coss of the off-side transistor) will be low enough that it becomes better damped.If you insist on a 2-layer build, then reserve one layer for solid BUS- (say) fill, and route everything on the other layer if at all possible. You inevitably have to use vias to the opposite side to cross traces, which must be done away from the ground-return path, and with as little area cut out of the pour as possible. The geometry isn't as good here (it is flat-facing trace to ground plane, but the distance is the whole board thickness, not to an internal plane, so probably 40-100 ohms transmission line impedance), so you may not be able to see much benefit.Much better: place the capacitors in a row, in front of the transistors. Youcan'troute away the inductance here, the only thing you can do is improve the placement so the routing doesn't need to try.Again, you need about 15A worth of caps, so shop for low-ESR types that specify their ripple current, and buy enough of them to put in parallel to handle that.One final note: TO-220 transistor leads are about 10nH alone, soldered into the board. About double that, hanging out on those terminal blocks. This is significant already! There's not much you can do about this, except changing things much more dramatically. Example: using D2PAK or DFN package SMT transistors with little or no lead length (about 5 and 2nH respectively), and soldering them to the heatsink, which is also the PCB. This takes much more layout optimization, of course, and probably can't be done without 4 layers, as much for routing as for heat-sinking purposes. That would be the preferred modern approach (not that it's necessarily the easiest or best method for your application!).Tim

author: iMo
author_rank: Super Contributor
timestamp: October 28, 2018, 09:23:59 pm
content: Try with an RC "snubber". Serial RC wired between transformer's primary leads. Needs to be designed based on L, f_switching, V, I, ringing period, etc.