Cyclone V GX Starter Kit vs. DE1-SoC Board - Page 1
Forum section: electronics / general

author: TNb
author_rank: Regular Contributor
timestamp: February 20, 2014, 03:08:49 pm
content: Hi!First of all thank you all for your time.I finally ready to buy my first FPGA, this time for real, got money laying around just for this. I have experience with HDLs(both VHDL and Verilog), but never tried anything on real boards.And I'm having much struggle choosing between these two boards:http://www.altera.com/products/devkits/altera/kit-terasic-cyclone-v-gx-starter.htmlhttp://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=836&PartNo=1They are almost the same price(I can get academic price for SoC board), so this doesn't play a role in my opinion.I have a whole bunch of stupid newbie questions(sorry):1) In DE1-SoC board is it possible to use FPGA without any ARM processing at all? I mean can I do pure-FPGA projects with ARM hanging around doing nothing?2) Never had experience with Nios II and don't know really much about it - can it be used for stuff that usually done on ARMs or it is just small addition to FPGA?3) Starter Kit has really good thing with its Arduino headers, but I wonder what's the point? You can easily connect peripherals to any board, maybe not that fast, but anyway... or is there something I don't know? On TI LaunchPad for example it's not a problem to connect any kind of display, receiver or anything, just need some time to know what to do, I suppose it's the same for FPGA boards, right?4) FPGA specs. They are quite similar except one detail - the one with ARM does not have multipliers. Well, I don't know if it is a big issue, but I would like to hear some opinions.5 and most important) Does SoC Board really worth buying as a first board? I think it would be cool to make projects involving ARM in the future, but for first half or one year I probably will just play around with FPGA. So, yeah... I don't knowAnd for those who thinks that it's better to get DE0-nano - yeah, nice board, but just don't want it, kinda boring and doesn't save much money. I don't mind spending couple of hours configuring more complex board, I have enthusiasm and resources, so why bother buying DE0, I would need to buy a bunch of crap for it anyway.Sorry for long post.And there is thread for discussing the Starter Kit nearby:https://www.eevblog.com/forum/microcontrollers/cyclone-v-gx-starter-kit-the-ultimate-arduino/Thanks!

author: miguelvp
author_rank: Super Contributor
timestamp: February 20, 2014, 07:05:52 pm
content: I'm new to FPGAs as well but had the DE-0 Nano and now I have the Cyclone V GX just 2 days ago.I'm on my lunch break so I have to keep it short, but of the two you mention, the GX starter kit has Six 3.125G Transceivers 4 of those lanes exposed on the HSMC connector.I was contemplating both, but if I want to play with ARM I have old phones, a Transformer Prime (Tegra3), a Nvidia Shield (Tegra4) also an old TrimSlice (Tegra2). Would be fun to combine both but I want to get a solid hold on FPGAs before combining them.In the future if I can save the money I would get the $300 SoCKit. Also download all the resources for the kits you are interested on and check the documentation.Also even if you don't want the DE0-Nano, download the user manual, there are gold nuggets there about Quartus II and the Nios II on step by step instructions.They might be the same as the My First FPGA Tutorial and My First Nios II Tutorial that they have under Training/Tutorials.I'll follow up later after work and check if they are the same or more updated, the one in the DE0-Nano used Quartus II 10.1 and used the SOCP feature and Qsys was beta, now Qsys has replaced it. Qsys needs more detailed knowledge to connect the soft IP libraries (enable's etc)So my recommendation since I must go back to work, download the manuals and even the samples (requires free registration) if you plan to do high speed stuff or use their daughter boards, then the Cyclone GX Starter kit, or their $300 Soc kit.I haven't used the Xilinx Tool chain and have committed plenty of time to the Altera Tool chain, but the papilio board sure has a lot of user support and many sampleshttp://papilio.cc/.

author: JoeN
author_rank: Frequent Contributor
timestamp: February 20, 2014, 11:13:20 pm
content: Quote from: miguelvp on February 20, 2014, 07:05:52 pmI have a question that I have wondered about and will ask now since this was brought up. When Altera and Xilinx talk about these transceivers, what the heck are they talking about specifically? When a manufacturer says that their IC includes hardware I2C/SPI/CAN/U(S)ART/USB/Ethernet, they telling you more or less specifically what the capability is. "Six 3.125G Transceivers" sounds awfully generic to me. For them to be that fast, they must be doing a specific protocol, right? What is it? Is that meant for interfacing with JESD204B devices, or something else? Did older Cyclones have these transceivers or is this new for the V?Thanks for any help, this is a dark area for me, even though I have done some work with CPLDs and FPGAs, it has been more making state machines for my amusement or glue logic which CPLDs excel at.Edit: I think I may have found it.http://www.altera.com/technology/high_speed/protocols/all-protocols/hs-all-protocols.htmlI had no idea there were so many high-speed industry protocols and that one FPGA had built-in support for all of them. I know of SATA, SAS, DisplayPort, FibreChannel, PCI Express, SONET but not the others.Now I wonder why they have support for JESD204A listed, but not B. It seems like all the new devices supporting JESD have gone to B (e.g.http://www.ti.com/lsds/ti/data-converters/high-speed-adc-greater-10msps-jesd204b.page?DCMP=hpa_dc_jesd204b_en&HQS=jesd204b). In this video they claim JESD204B support:http://www.altera.com/technology/high_speed/protocols/jesd204b/je-index.html#yt-gal-1.I wonder why it is not on that list...

author: miguelvp
author_rank: Super Contributor
timestamp: February 21, 2014, 02:31:17 am
content: The transceivers allow high speed Current Mode Logic, Altera has it's own flexible flavor called Pseudo Current Mode Logic that is based on CML.On another note, the HSMC connector has a lot of LVDS (Low Voltage Differential Signaling) pins for high speed communications over twisted pair cables to drive an lcd panel directly for example. Provided that you know how the connector is setup and you can supply the voltages and differential pairs for data and clocks.About the training on the Terasic site, the myfirstFPGA and myfirstNios instructional videos use Quartus II 9.1 (very old since they are now on version 13.1) and they use the SOPC builder (obsoleted) now relegated by Qsys, so the Nios sample (and that applies to any usage of the provided intellectual property libraries that you can setup), is slightly different than the usage of the SOPC system. But Altera University has some samples on how to use Qsys and how to hook up the extra logical connections. Even if you don't use the Nios soft core, if you need to configure the PLL to give you a different frequency you have to use Qsys, so it's important.But since all FPGA dev boards are different and suit different needs, I would still recommend to download all the user manuals and compare them and see what do you need.All of them have sample code, but some manuals actually tell you how to go from beginning to end on creating a project. the othere just show you how to run a batch file to load and run the sof configuration file, that doesn't teach you how to create your own configuration.Again, even if you decide to get one that doesn't have the step by step, the old videos on the training or the DE0-Nano user manual have the step by step instructions from beginning to end.There is a lot this chips can do, just the input/output configuration options alone are incredible, do you need to interface to 3.3V on one pin and 1.2 on another? internal pull up/down configuration, TTL/CMOS/PCI/PCI-X? all configurable(varies depending on your chip, so download the datasheet too). LVDS pairs interfering with other pairs? you can move them to farther pins, it's all configurable.The supplied samples won't go there, but go to altera's training links, lot's of info there:http://www.altera.com/education/demonstrations/online/design-software/onl-design-software-demos.htmlhttp://www.altera.com/education/univ/software/unv-software.htmlWhatever you decide to get, just get one and play with it. They are amazing chips!.My take is the simpler the less distractions and frustrations. I wouldn't give my daughter an Aston Martin to learn how to drive.

author: lgbeno
author_rank: Frequent Contributor
timestamp: February 21, 2014, 03:37:25 am
content: I would recommend the SoC board over the GX unless you have a direct need for the high speed transceivers. Reason is that the HSmc header are expensive to deal with if you want to attach something and talk to it. Playing with the arm would probably be a more fun exercise.About NiosII it's basically a MIPS architecture CPU, it's pretty powerful, certainly not as much as the SoC ARM but it's a 32bit machine with floating point capability. We ran one at around 75mhz in stratixII I don't see why cycloneV couldn't do similar.About the transceivers, they are SERDES meaning it is 8b10b encoded streams with fancy stuff for signal integrity. I know in Cyclone IV GX the had a hardened PCIe MAC which was very easy to use. That was fun to develop with.Just a FYI on Cyclone V, I think it is the first in the cyclone family to drop support for 3.3v IO, hope you don't need that.It totally depends on what you want to do with the kit but IMO the SOC one or good ole DE0 would be best

author: JoeN
author_rank: Frequent Contributor
timestamp: February 21, 2014, 04:06:52 am
content: Quote from: lgbeno on February 21, 2014, 03:37:25 amhttp://www.altera.com/literature/hb/cyclone-v/cyclone5_handbook.pdfPage 5-10 is what I attached. Am I reading this wrong? It looks like all the common voltages are supported up to 3.3V, per bank. Core voltage is 1.07V-1.13V, 1.1V nominal.

author: miguelvp
author_rank: Super Contributor
timestamp: February 21, 2014, 05:25:19 am
content: I think he meant 5.0V was dropped on Cyclone V. Although some 5.0V ICs are 3.3V compatible, but you must check that's the case in the devices you want to mate.Edit: correction, the Cyclone IV didn't have 5.0V levels to begin with, so probably he meant 3.3V but the Cyclone V does support 3.3V CMOS and TTL levels, so not sure what he meant.Never had the original DE0 but for learning a Cyclone III might be as good as a Cyclone IV, I never got even close to use my Nano's total LEs (Logic Elements).Edit2: I guess my choice for the GX was biased because VGA is dead in my mind and HDMI is the way now.

author: JoeN
author_rank: Frequent Contributor
timestamp: February 21, 2014, 07:43:21 am
content: As far as I remember, and also with the help of a little research that I just did, no generation of Cyclone devices has ever allowed for 5V ports. Older Altera devices like the FLEX had 5.0V cores and ports. But as far as I can see, no Cyclone ever did. They all allow 3.3V ports, though. The core voltage has gone down from 1.5V (gen 1), to 1.2V (gen 2,3,4), to 1.1V (gen 5)

author: lgbeno
author_rank: Frequent Contributor
timestamp: February 22, 2014, 11:33:50 pm
content: Sorry it looks like I was mistaken on the Cyclone V not supporting 3.3 which I'm glad that it does!Yes 5V support never existed. It's really not relevant anywhere except for AVR and some PICs.

author: miguelvp
author_rank: Super Contributor
timestamp: February 23, 2014, 10:35:10 am
content: For 5.0V you can always level-shift the signal with a mosfet and a couple of resistors per data line if the signal is not too fast, although new sensors and devices that will operate at 5.0V are usually 3.3V compatible (might as well save power and run them at lower voltage).http://www.adafruit.com/datasheets/an97055.pdfOn the Cyclone V GX Starter kit, I was able to follow the myfirstFPGA tutorial from Altera's training, but the ALTPLL IP step, threw me a curveball. I did manage to finish it with the new Altera PLL 13.1 IP but couldn't get rid off the reset pin, so I had to map a button and invert it. I could have force it to high with an output pin, but that was the easiest way to deal with it.http://www.altera.com/education/training/courses/ODSW1010Without my short experience with the DE0-Nano this would have been a show stopper.The HDMI Qsys code, provided on the sample code, seems to trigger a license limitation because it's hooks with the Nios II soft core (even if not instantiated). I might be able to strip the dependencies and I'm not sure what is going on. Or I could drive the HDMI-TX myself, but implementing the EDID, I2C, hotplug and other capabilities doesn't look too trivial, the docs for the HDMI transmiter (ADV7513) amount to 3 MB and the programming guide is most of it, So for now I can only run my configuration tethered to my PC, but it's still a lot of fun.BTW there is an errata on the pinout in page 43 of the manual. It calls HDMI_TX_HS vertical sync and HDMI_TX_VS horizontal sync. The signal name (HDMI_TX...) is the right one.Edit: Right after posting this I decided to take out all of the nios2 references from the HDMI_QSYS.qip file and i'm untethered now.