What clearance is required from a via hole/barrel (no pad) to copper? - Page 1
Forum section: electronics / general

author: DutchGert
author_rank: Frequent Contributor
timestamp: January 22, 2016, 09:02:01 am
content: Hello guys,I know that a lot of PCB manufacturers remove unused (not connected) via pads's to reduce drill bit tear:My CAD package (Altium) has an option to do this when generating Gerbers or in Altium itself when routing is (almost) done.When I do this in the Gerber output I end up with copper the same as in my CAD package but with the unused via pads removed (see image 1). This is how a manufacturer would do this.But, when I order Altium to do this and repour my planes/polygons I end up with much more copper because it uses my clearance rule (100um) as a distance between the via barrel and the copper. (image 2). This is nice because this way I have much more copper on my planes = lower inductance = better SI and PI.But I assume (that is where u guys come in) using the normal 100um clearance between the via barrel and the copper is not enough clearance for the via plating process or is it? I cant find anything on this on the internet or on lets say the Wurth design guide (https://www.we-online.com/web/en/index.php/show/media/04_leiterplatte/2011_2/relaunch/produkte_5/012012_Basic_Design_Guide.pdf)So, what would be a reasonable clearance between an (plated) via hole with no pad on the particular layer and other copper on that layer?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 22, 2016, 04:15:56 pm
content: It's my understanding, manufacturers like to remove the unused pad rings to increase clearance.Obviously that's a benefit, but it also means they get a HUGE amount of clearance. The opening in a pour might be 30 mils across. If their process is that bad, well...And for sure, it sucks for BGA fanouts, because you have an entire grid of vias perforating all layers, wrecking impedances.A compromise might be to increase the clearance between (IsPolygon AND OnMid) and IsVia, say to 10 or 15 mils.Probably worth asking a PCB sales/engineer how much to use in this situation.Tim

author: DutchGert
author_rank: Frequent Contributor
timestamp: January 23, 2016, 09:49:43 am
content: Yes, increase clearance and reduce drill wear is what they told me.Well, if the rule you suggest i get problems with via's that still have a pad because it calculates it from the pad edge to the next copper area. Isnt there a way to define a clearance rule from the center of a hole/pad in Altium?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 23, 2016, 11:55:24 am
content: Ah.. is there a parameter or field for a removed pad?If it's doing it by setting a small diameter on a given layer, you wouldn't be able to query that, not with a single rule; but you could do "OnLayer('Mid Layer 1') AND (PadSizeLayer2 = 0)" or something like that, repeated for each layer.Tim

author: DutchGert
author_rank: Frequent Contributor
timestamp: January 23, 2016, 01:54:14 pm
content: I got a reply from the manufacturer of my boards:"Remove the non-functional pads on all internal layers is best, because it is reinforced adhesion of the hole copper ,and easy to drill process for the production,if remove the non-functional annular rings, you must be keeping the safety spacing 11mil(0.28mm) minimum to innerlayer copper for plating holes"If i keep those rules in mind i gain no extra copper so ill just let my output job take care of it by deselecting 'Include unconnected mid-layer pads ' here:On a sidenote: Wurth mentions this on here Multilayer FAQ:"Due to manufacturing tolerances, in particular the dimensional variations of thinner cores, an adequate isolation distance of 225µm around the via drilling in design is recommended.This ensures that the final product does not have isolation distances that are too small. Approximately, the same size is recommended if the pads on the signal inner layers, which are not connected, are removed."So if i would be using Wurth boards i could actually gain 50um between two 0,15/0,45mm via's with 100um clearance and have 200um copper in between them instead of 150um on a 0.8mm BGA grid. So for future designs it could be useful to do this.

author: dmills
author_rank: Super Contributor
timestamp: January 24, 2016, 01:21:46 pm
content: It can be done, but be a little careful using Wurths numbers if you might ever want that board made elsewhere, while there are plenty of others who can do the same thing, the number of low cost board houses who can pull it off reliably is somewhat limited (May or may not be an issue).Also 0.15 hole sounds like microvia to me and you will want to watch the aspect ratio there.Regards, Dan.

author: DutchGert
author_rank: Frequent Contributor
timestamp: January 24, 2016, 09:53:47 pm
content: Quote from: dmills on January 24, 2016, 01:21:46 pmI agree. About the hole size: its the finished hole size so tools size is .2 or even .25. Its still 'normal' TH via's for the .8mm pitch bga i am using. Board is 10 layer with DDR3 so its never going to be a very cheap board but i do want it to be a bit 'regular'.