Why don't we see more TDC based high-resolution ADCs? - Page 1
Forum section: electronics / general

author: nimish
author_rank: Regular Contributor
timestamp: May 03, 2024, 02:37:06 am
content: Stupid question but since it's easy to get an extremely stable clock source -- 0.05 ppm is like $50 retail -- and measuring long time intervals precisely is relatively easy (seconds to sub-nanosecond precision) why use a complicated multi slope ADC when bolting the voltage to time converter to a TDC gets you most of the way there? What am I missing here? Comparator noise?

author: bdunham7
author_rank: Super Contributor
timestamp: May 03, 2024, 03:08:37 am
content: Multislope can be much faster, for one thing.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 03, 2024, 04:34:04 am
content: A voltage to time conversions would be similar to a dual slope ADC.A dual slope like ADC is limited in the INL by the dielectric absorbtion of the integrating capacitor. Another point it the noise and using more of the time for actual input integration to get a low noise bandwidth for the input. E.g. the ICL7106 uses only 25% of the time to actually measure the input, while a MS ADC is usually at > 98% for not very fast conversions.The clock and actual time measurement are not really the critical points in a high resolution integrating ADC.A simple multislope ADC is actually not that much more complicated than a good dual slope ADC build from seprate parts.For the not so high resolution / limited INL end there are sigma delta ADC chips and good SAR type ADC chips, that can be pretty affordable (cheaper than a TDC chip).

author: nimish
author_rank: Regular Contributor
timestamp: May 03, 2024, 01:40:13 pm
content: Quote from: Kleinstein on May 03, 2024, 04:34:04 aminteresting -- didn't consider the speed. I was considering stuff like high precision multimeters, electrometers and such where 1sps might not be an issue.TDC chips aren't ultra cheap but are free with delay lines in FPGAs:https://www.sciencedirect.com/science/article/abs/pii/S0168900215003137can measure 7.5ms to 1ns precision which is ~6.8 digits (I think) and $6 ain't bad:https://www.mouser.com/ProductDetail/ScioSense/TDC-GP22-5K-TR?qs=DPoM0jnrROUYcAL0JSEuTg%3D%3DAlso they benefit from CMOS shrinking and are a hell of a lot easier to design than a high end ADC, as far as I can tell.

author: nimish
author_rank: Regular Contributor
timestamp: May 03, 2024, 01:55:18 pm
content: To spitball a TDC based DMM front end:Exactly the same as a regular integrator but uses high speed comparators to trigger at, say, 0V and Vref/2 and then measure the time to integrate. You could easily linearize this and calibration could be done automatically I'd assume. PVT probably kills you but for a fixed temp, voltage and process -- n=1 -- I suppose you could do quite well.

author: coppice
author_rank: Super Contributor
timestamp: May 03, 2024, 02:58:32 pm
content: Quote from: nimish on May 03, 2024, 01:55:18 pmYou will have a design limited by the noise performance of the high bandwidth comparator, and you will be disappointed. If you look at the ultrasonic flow applications for which the GP22 was designed, you will find they are characterised by needing to measure, to a few 10's of picoseconds, the time between 2 very distinct events. Its only that the 2 events are very distinct that the design works well. A somewhat fuzzy comparison, limited by noise, at very high speed, isn't going to do well.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 03, 2024, 03:19:06 pm
content: Quote from: nimish on May 03, 2024, 01:55:18 pmThat would be a kind of single slope converter. So 2 steps back from a multi-slope. The problems start with a integration time that is not fixed but depends on the signal - so no easy mains suppression.

author: nimish
author_rank: Regular Contributor
timestamp: May 03, 2024, 04:21:07 pm
content: Quote from: coppice on May 03, 2024, 02:58:32 pmSeems to work for CERN:https://indico.cern.ch/event/243655/attachments/415393/577145/elx-trigger-daq-p1.pdf(slide 30)Multislope would be the same, just toggle between polarities (I assume that's how that works) and measure the times.Actually thinking about it a multislope (inc dual) _is_ just an analog heavy VTC+TDC. It already measures voltage via time as an intermediary.Maybe there's a way to say, use the unknown voltage as an input to a very stable VCO (<= 10fs) and measure the phase difference with a reference clock, that's easy relatively.edit: welp, VCO-ADCs have existed for a while.

author: coppice
author_rank: Super Contributor
timestamp: May 03, 2024, 04:27:38 pm
content: Quote from: nimish on May 03, 2024, 04:21:07 pmHow does slide 30 disagree with what I said? Their "hit" is a "very distinct event". Not a noise soaked output of a high bandwidth comparator.

author: nimish
author_rank: Regular Contributor
timestamp: May 03, 2024, 04:35:26 pm
content: Quote from: coppice on May 03, 2024, 04:27:38 pmI would like to see your dual/multi-slope adc that doesn't involve a precision comparator/trigger somewhereok, this is just integrating ADCs 101. The multiple slopes is more or less the same as all digital vernier TDCs except time-interpolating in the analog domain. So in theory one could shift most/all the analog bits to digital ones: ramp generator+extremely high speed low noise comparator+edge detector measured as many times as possible against an ultra-stable time/frequency reference, calibrated with a precision voltage standard. So basically just a SERDES, and I guess delta-sigma style noise shaping could be involved too.

author: coppice
author_rank: Super Contributor
timestamp: May 03, 2024, 04:37:02 pm
content: Quote from: nimish on May 03, 2024, 04:35:26 pmHuh? I think you've lost the plot.

author: nimish
author_rank: Regular Contributor
timestamp: May 03, 2024, 04:46:37 pm
content: Quote from: coppice on May 03, 2024, 04:37:02 pmExactly how do you think an integrating ADC works?https://www.analog.com/media/en/training-seminars/tutorials/MT-027.pdf

author: David Hess
author_rank: Super Contributor
timestamp: May 03, 2024, 06:18:16 pm
content: Quote from: nimish on May 03, 2024, 02:37:06 amNational application note AN-260 describes a high resolution high accuracy single-slope converter.Single-slope converters can have excellent accuracy and resolution but their variable input ramp time has no 50/60 Hz rejection, leading to errors. Dual-slope and similar converters use a constant integration time which is a multiple of the full power line cycle, creating a null at the power line frequency and its harmonics.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 03, 2024, 06:35:05 pm
content: The classical MS ADC uses a comparator, but the comparator does not have to be super fast and the time measurement not very high resolution. An important point is to compensate much of the charge already during the integration. For the final charge reading is from a reduced reference level (e.g. 1/128 the main ref. in the Keithley 2000 and similar) and this way only a moderate timing resolution needed. The noise is usually more limited by the amplifier noise, resistor noise or jitter, not the timing resolution. A reduced speed of the comparator allows for less noise BW and this way more resolution.More timing resolution is of limited use. One may get away with a litter higher small ref. level and get a slightly faster conversion. However the difference is more marginal, not a big step up that is worth the extra effort.In some variations (e.g. HP Multislope 3 and 4, NI flex ADC or my ADC variant) the final charge reading is not with a comparator but and auxiliary (SAR type) ADC. I can get away with rather limited time resolution (e.g. 250 ns) and still have little quantization noise (e.g. 28 bits after 20 ms). More time resolution would not really help. It is more about getting low jitter (e.g. want better 5 ps) for the reference swiching - so accurate timing on the output side, not for the inputs.Some of the higher resolution TDCs go the other way around. The convert the residual time steps to an analog voltage and than use an ADC to improve on the timing resolution. Directly using an auxiliary ADC for a residual charge makes more sense. Than going to an intermediate time signal and back.

author: nimish
author_rank: Regular Contributor
timestamp: May 03, 2024, 11:22:36 pm
content: Quote from: Kleinstein on May 03, 2024, 06:35:05 pmThis makes sense. It doesn't really matter how fast or noise the comparator (to a point) since it's not conceptually difficult to calibrate and oversample out. A SAR ADC, of course, still uses a comparator internally fwiw, just a slower one.>More time resolution would not really help. It is more about getting low jitter (e.g. want better 5 ps) for the reference swiching - so accurate timing on the output side, not for the inputs.It's not hard to get <100fs jitter clocks for very low cost. Take the ones for common SERDES: the requirements are now <100fs for 112gbps+After digging it does seem that, were the commercial multimeters designed today, they would like use a high-resolution sigma-delta converter and use (even more) oversampling and better filtering. There's just no market.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 04, 2024, 05:15:17 am
content: There is not that much new developement for the high resolution meters. The last one is the Fluke 8858, with not that much details known, but this may still be just a slightly bigger iteration on the old ADC from the Datron 1271/1281. The updated 3458 version is still very close to the old one, mainly replacing some obsolete parts (especially the comparators) but otherwise very close to the original.The Keithley 7510 still looks like a decendent of the K2000/K2002 , though I only saw pictures of the PCB.For the more standard meters (3446x) Keysight uses it's multislope 4 ADC, that is more like a contineous time sigma delta ADC. This is not ideal for highest linearity, but it helps with good performance at high speed (AFAIK some 500 kSPS) that is used for the digital AC RMS mode. The sigma delta part uses oversampling to some degree, though not as much as more classic higher order ones.For the jitter ~1 ps is easy, lower gets tricky with more unusual logic chips and also the CMOS swiches may not be much better than this. This level is still good enough, at least when the modulation frequency is not very high. There are still a few point's where one could learn from the time nuts and the timing measurements, but a TDC makes relatively little sense. It is a thing about making sure that the delays and clocks are not effected by the comparator or similar. Unintendent modulations in the frequency or delays can cause INL and this is the more tricky part than the more minor noise contribution from jitter.

author: mawyatt
author_rank: Super Contributor
timestamp: May 04, 2024, 03:01:14 pm
content: Somewhat relevant since it's an ADC that employs Non-Uniform Time Sampling, or a Non-Uniform Sampling ADC (NUS). This unique ADC may not be directly applicable for DMM type high resolution use but still quite useful in higher frequency applications.The general idea is to utilize both amplitude and time to "quantize" the input signal and perform post digitization anti-aliasing filtering rather than conventional pre-filtering.We witnessed some impressive early work with the NUS ADC at USC by Dr Mike Chen around ~2010, he spearheaded this early effort and later we helped support efforts thru one of our DARPA programs.Here's something we just found with Google, I'm sure there's lots more.https://youtu.be/n25PmRhdqOgWould have thought this new type ADC might appear soon as it's over a decade old and this is usually the time length it's takes from the Research Labs to the commercial field. Recall Keysight was quite interested way back, but don't know if they are employing these ADCs anywhere.Anyone know if the NUS ADCs are being utilized anywhere?Also vaguely remember some work with Non-Uniform Sampling DACs at USC under Dr Chen, but never was involved or witnessed any direct work as we were heavily involved with our GaN based Direct Digital To Antenna (DD2A) developments then.Best,

author: coppice
author_rank: Super Contributor
timestamp: May 04, 2024, 03:24:24 pm
content: Quote from: mawyatt on May 04, 2024, 03:01:14 pmThat presentation shows the die of a working TDC + flash ADC device that looks too complex to be just an experimental project, and the video was posted 3 years ago.

author: mawyatt
author_rank: Super Contributor
timestamp: May 04, 2024, 03:54:52 pm
content: Quote from: coppice on May 04, 2024, 03:24:24 pmThis ADC scales with CMOS feature size, and of course one would expect much higher performance with modern sub 10nm CMOS!Here's an image of the prior work on the NUS ADC that we were involved with. This was over a decade ago and in 65nm TSMC CMOS. This was from the chip imaging technology we developed in-house starting around 2000.You might wonder where that image at 36:34 came fromhttps://youtu.be/n25PmRhdqOgBest,

author: coppice
author_rank: Super Contributor
timestamp: May 04, 2024, 04:01:44 pm
content: Quote from: mawyatt on May 04, 2024, 03:54:52 pmWhat was the purpose of NUS in the imaging application? Was this a similar sub-sampling setup to the communications ones in the presentation you posted, where NUS decorrelates the aliases and spreads them out as noise, and then you filter your way back to effectively uniform sampling?

author: mawyatt
author_rank: Super Contributor
timestamp: May 04, 2024, 04:13:39 pm
content: Quote from: coppice on May 04, 2024, 04:01:44 pmWasn't used in imaging, the images were just the ability to capture chip images of this detail (this is very low resolution, we have some with GigaPixel detail). This imaging technique was applied to all the chips we developed and a few others for folks, including IBM, DARPA, ITT, Excels, Harris, Keysight, USC, Cornell, MIT, and a few others we can't mention.Our interest in the NUS ADC was for Advanced Electronic Warfare use. Where a signal is intercepted, analyzed and a quick assessment of a potential threat, then particular counter-measures are invoked if necessary.Edit: Just reread your post, are you referring to the RF Spectral Imaging Chip?Best,

author: nimish
author_rank: Regular Contributor
timestamp: May 04, 2024, 05:57:11 pm
content: Quote from: mawyatt on May 04, 2024, 03:01:14 pmAh yes, his work on advanced ADPLLs inspired this ---- since it actually uses the strengths of CMOS scaling to the maximum advantage in compensating, noise-cancelling, and auto-calibrating. Digital logic and software are free compared to analog wizardry especially since the latter doesn't scale.Re NUS: also interesting, what you end up getting is a filter action baked into your sampling pattern. Might be worth it? IDK.Anyway, PCIe/Ethernet/SERDES require jitter <100fs so you can now buy jitter cleaners that guarantee that for $20.