GAL design software - Page 1
Forum section: electronics / general

author: ianc
author_rank: Newbie
timestamp: November 16, 2017, 02:04:58 pm
content: HiI've been lurking for a while and have found the information posted here most useful.I have a small project I'm working on which requires a small amount of glue logic and address/data latching which could be best achieved with some form of programmable logic. My thoughts were that I could use some small programmable devices e.g. 16V8 or 22V10 rather than discrete logic. I have a programmer (TL866A) which should program the devices but I'd like some guidance as to software for creating the .JED files to configure the devices.Ideally I'd like something I could draw the schematic for the required circuit and the software would process the circuit and spit out a .jed file for the programmer. I suspect this is not an option on my tiny budget (I'm a hobbyist not a professional). So I would be willing to write logic equations if that is all the available (free) software can cope with.My development environment is an ageing Core 2 duo laptop running Windows 10 at 1.75Ghz with 2GB of memory and a 250GB SSD so something fairly lightweight would be best.Does anyone have any recommendations?With thanks in advanceIan

author: capt bullshot
author_rank: Super Contributor
timestamp: November 16, 2017, 02:18:24 pm
content: Search for "PALASM". That's been the language / tool of choice when we used PAL / GAL back in the times ...

author: voltsandjolts
author_rank: Unknown
timestamp: November 16, 2017, 03:10:07 pm
content: You might find it easier to use a small CPLD like Xilinx XC2C64A.Small dev boards cheap on ebay (remnants of old PS3 hacking) and cheap programmers.Easy schematic entry with Xilinx tools but you can do that with Lattice etc...

author: technix
author_rank: Super Contributor
timestamp: November 16, 2017, 05:29:38 pm
content: Technically you can repurposeAtmel's free WinCUPLfor things similar enough with Atmel's offerings - GAL16V8 or GAL22V10... I have yet to find a UNIX version of this.

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: November 16, 2017, 06:37:00 pm
content: WinCUPL. It only works with equations, but that is the better way to do it. Drawing a schematic just meansyouhave to translate from logic to a circuit, then the GAL assembler has to convert it back again. You should treat the GAL as a 'black box' which performs the logical functions you need.Here's an example taken from myAquarius Micro-Expanderproject. It has address decoding for RAM and ROM, and I/O decoding to control a CH376 USB interface and set a latch which maps half the RAM over the ROM to emulate a game cartridge. I didn't even attempt to produce a schematic for this.Code:/* ***************** INPUT PINS ************************/PIN 1 = A6 ; /* Z80 A6 */PIN 2 = A7 ; /* Z80 A7 */PIN 3 = A14 ; /* Z80 A14 */PIN 4 = A15 ; /* Z80 A15 */PIN 5 = MREQ ; /* Z80 /MREQ */PIN 6 = RD ; /* Z80 /RD */PIN 7 = WR ; /* Z80 /WR */PIN 8 = IORQ ; /* Z80 /IORQ */PIN 9 = RESET ; /* Z80 /RESET */PIN 15 = LATR ; /* Latch reset */PIN 16 = A5 ; /* Z80 A5 *//* ***************** OUTPUT PINS ***********************/PIN 19 = RA14 ; /* RAM A14 */PIN 18 = LATCH ; /* Map upper RAM over ROM */PIN 17 = !RAME ; /* 32k static RAM /CS */PIN 14 = !ROME ; /* 16k ROM /CS */PIN 13 = PRST ; /* Peripheral RESET (active high) */PIN 12 = !CH376 ; /* CH376 /CS */RAME = !MREQ&(!RD#!WR)&(((A15&!A14&!LATCH)#(!A15&A14))#(A15&A14&LATCH&!RD));ROME = !MREQ&!RD&A15&A14&!LATCH;CH376 = !IORQ&(!RD#!WR)&!A7&A6;RA14 = A14&!(A15&LATCH);LATCH = LATR&((!IORQ&!WR&!A7&!A6)#LATCH);PRST = !RESET;The code structure is very simple. First you assign variable names to the pins, then describe the logic. Variables to the left of the '= ' sign are outputs, those on the right are inputs. WinCUPL takes care of the details.You can also simulate your design if you want, but I found it was easier to just put the chip in a breadboard and attach dip switches and LEDs to the inputs and outputs.Here's the compiler output listing for that code. At the end it draws an ASCII diagram of the chip with pin functions labeled. This is all you need to add your 'custom' logic to your main schematic!Code:===============================================================================Expanded Product Terms===============================================================================CH376 =>A6 & !A7 & IORQ & WR# A6 & !A7 & IORQ & RDLATCH =>!A6 & !A7 & IORQ & !LATR & WR# LATCH & !LATRPRST =>!RESETRA14 =>A14 & !A15# A14 & !LATCHRAME =>A14 & A15 & LATCH & MREQ & RD# A14 & !A15 & MREQ & RD# A14 & !A15 & MREQ & WR# !A14 & A15 & !LATCH & MREQ & WR# !A14 & A15 & !LATCH & MREQ & RDROME =>A14 & A15 & !LATCH & MREQ & RDCH376.oe =>1LATCH.oe =>1LATR.oe =>0PRST.oe =>1RA14.oe =>1RAME.oe =>1ROME.oe =>1===============================================================================Symbol Table===============================================================================Pin Variable Pterms Max MinPol Name Ext Pin Type Used Pterms Level--- -------- --- --- ---- ------ ------ -----A5 16 V - - -A6 1 V - - -A7 2 V - - -A14 3 V - - -A15 4 V - - -! CH376 12 V 2 7 1! IORQ 8 V - - -LATCH 18 V 2 7 1! LATR 15 V - - -! MREQ 5 V - - -PRST 13 V 1 7 1RA14 19 V 2 7 1! RAME 17 V 5 7 1! RD 6 V - - -! RESET 9 V - - -! ROME 14 V 1 7 1! WR 7 V - - -CH376 oe 12 D 1 1 0LATCH oe 18 D 1 1 0LATR oe 15 D 1 1 0PRST oe 13 D 1 1 0RA14 oe 19 D 1 1 0RAME oe 17 D 1 1 0ROME oe 14 D 1 1 0LEGEND D : default variable F : field G : groupI : intermediate variable N : node M : extended nodeU : undefined V : variable X : extended variableT : function===============================================================================Fuse Plot===============================================================================Syn 02192 - Ac0 02193 -Pin #19 02048 Pol - 02120 Ac1 -00000 --------------------------------00032 ----x----x----------------------00064 ----x--x------------------------00096 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPin #18 02049 Pol - 02121 Ac1 -00256 --------------------------------00288 -x-x--------------x--x---x------00320 ------x-----------x-------------00352 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00384 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00416 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00448 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00480 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPin #17 02050 Pol x 02122 Ac1 -00512 --------------------------------00544 ----x-x-x----x---x--------------00576 ----x----x---x---x--------------00608 ----x----x---x-------x----------00640 -----x-xx----x-------x----------00672 -----x-xx----x---x--------------00704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00736 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPin #16 02051 Pol x 02123 Ac1 -00768 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00800 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00832 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00864 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00896 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00928 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPin #15 02052 Pol x 02124 Ac1 -01024 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01056 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01088 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01120 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01152 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01184 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01248 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPin #14 02053 Pol x 02125 Ac1 -01280 --------------------------------01312 ----x--xx----x---x--------------01344 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01376 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01440 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPin #13 02054 Pol - 02126 Ac1 -01536 --------------------------------01568 ----------------------------x---01600 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPin #12 02055 Pol x 02127 Ac1 -01792 --------------------------------01824 -xx------------------x---x------01856 -xx--------------x-------x------01888 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01920 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01984 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx02016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxLEGEND X : fuse not blown- : fuse blown===============================================================================Chip Diagram===============================================================================______________| Aqu_mem |A6 x---|1 20|---x VccA7 x---|2 19|---x RA14A14 x---|3 18|---x LATCHA15 x---|4 17|---x !RAME!MREQ x---|5 16|---x A5!RD x---|6 15|---x !LATR!WR x---|7 14|---x !ROME!IORQ x---|8 13|---x PRST!RESET x---|9 12|---x !CH376GND x---|10 11|---x|______________|

author: technix
author_rank: Super Contributor
timestamp: November 16, 2017, 07:48:53 pm
content: I think the equation form used by WinCUPL is a good stepping stone from circuit diagrams to HDL. You can soon start wrapping your mind around the concept of describing hardware using code, and a few designs later you will start finding yourself getting larger and larger chunks of stuff done in FPGAs.

author: TK
author_rank: Super Contributor
timestamp: November 16, 2017, 08:38:59 pm
content: I had good experience with PALASM running inside a DOSBOX. The resulting JED file was used to program a GAL16V using TL866

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 16, 2017, 09:25:41 pm
content: It's maybe 20 years since I used it, but From memory. WinCUPL is a lot more powerful than PALASM, as it does logic reduction and some state-machine stuff, whereas palasm is basically a textual representation of the device structure.A bit like the difference between C and assembler

author: nctnico
author_rank: Super Contributor
timestamp: November 16, 2017, 09:32:05 pm
content: AFAIK PALASM can also do logic reduction and state machines but it has been 20 years since I last used it.

author: TK
author_rank: Super Contributor
timestamp: November 16, 2017, 09:36:34 pm
content: I implemented a state machine for an HP 8714B IBASIC activation 2 months ago using PALASM:https://www.eevblog.com/forum/testgear/how-to-activate-ibasic-on-vintage-hp-871xb-network-analyzers/msg1251274/#msg1251274I think WinCUPL is more powerful, but I found PALASM easier to learn from zero.

author: bobaruni
author_rank: Regular Contributor
timestamp: November 17, 2017, 01:21:02 am
content: Years ago, I used protel 99 SE.I created a schematic and then used the compiler to create a jed file, was easy and worked very well.Not sure if the newer Altium trial packages will allow this?

author: danadak
author_rank: Super Contributor
timestamp: November 18, 2017, 10:50:49 am
content: Depending on design you could always use PSOC.http://www.cypress.com/documentation/application-notes/an62510-implementing-state-machines-psocr-3-psoc-4-and-psoc-5lpFollowing URL, list of videos at bottom of page.http://www.cypress.com/documentation/application-notes/an82156-psocr-3-psoc-4-and-psoc-5lp-designing-psoc-creatortmDesign can be done from schematic or Verilog. IDE fee. In fact one of the manyavailable GUI components in library is a LUT component.Plus you get a GP processor, analog, DSP.....Regards, Dana.

author: martinator
author_rank: Contributor
timestamp: November 18, 2017, 11:39:07 am
content: PALASM can also do logic reduction. I don't think it's as powerfull as Wincupl, but it can do state machines. The simulator is better in WinCUPL as it's graphical. You lose track of which clock you are on in PALASM if you're doing a long simulation.If you wanted to go really old school and create a schematic you could use DOS ORCAD with the PALASM plugin but it won't do devices as small as a GAL, you would have to use a MACH110 or similar. (I may have a win3.11 image for virtualbox with all that already installed.)

author: xtech
author_rank: Regular Contributor
timestamp: November 18, 2017, 04:41:04 pm
content: I'm creating designs for GAL chips in VHDL using free Lattice ispLevel Classic. But I'm not sure if there is possibility to draw logic on the schematics (probably no).And remember - GAL22V10 are poorly supported in the tl866, 16v8 and 20v8 are ok

author: thermistor-guy
author_rank: Frequent Contributor
timestamp: November 22, 2017, 12:09:35 am
content: Quote from: ianc on November 16, 2017, 02:04:58 pmMy vote is for WinCUPL, freely available.A comment on your laptop, if you are still using a 32-bit processor. I still make use of a 10yo laptop with similar specs to yours, but I upgraded it with a T7600 64-bit processor so I could run Linux.https://ark.intel.com/products/27257/Intel-Core2-Duo-Processor-T7600-4M-Cache-2_33-GHz-667-MHz-FSBhttps://www.amazon.com/Intel-T7600-2-33Ghz-Fsb667Mhz-Fcpga6/dp/B000I77VESYou can still get T7600s from Amazon and other sellers. Check that you are running the latest BIOS for your laptop before upgrading, if you decide to do that.

author: technix
author_rank: Super Contributor
timestamp: November 22, 2017, 07:21:39 am
content: Quote from: ianc on November 16, 2017, 02:04:58 pmI have a spare T7400 (slightly slower than T7600 at 2.17GHz instead of 2.33GHz, but otherwise the same) I can sell you that if you want to.

author: jmarkwolf
author_rank: Regular Contributor
timestamp: November 22, 2017, 04:31:11 pm
content: Quote from: bobaruni on November 17, 2017, 01:21:02 amI also did this for many years. Worked great.Still have bundles of tubes of GAL's!