PCB layout simulation software - Page 1
Forum section: electronics / general

author: xzswq21
author_rank: Frequent Contributor
timestamp: February 02, 2019, 07:21:50 am
content: HelloActually I have designed an analog circuit but I want to simulate the layout bcoz the circuit is precision (the frequency range is only some MHz). the circuit has some op-amps and some passive components.Can I simulate the layout in HyperLinx? which software do u recommend me?Thanks

author: free_electron
author_rank: Super Contributor
timestamp: February 07, 2019, 01:46:58 am
content: What od you hope do extract from the PCB layout ? parasitics ? ANsoft but at MHz range ... there is not much you will learn.Your surface cleanliness is more important. ake sure you have guards in place to stop leakages.

author: xzswq21
author_rank: Frequent Contributor
timestamp: February 07, 2019, 07:27:25 am
content: Quote from: free_electron on February 07, 2019, 01:46:58 amYou are right.Actually at some sensitive area I have placed some non-plated holes to blind stray capacitance and I have removed some reference plane and solder mask resin. I should reduce the stray capacitance to keep them below than 1pF.you mean ANsoft Maxwell?sometimes I design high speed ADC/DAC boards. I have many problems with using of 3rd party software to perform SI analysis. I have looked ur comments in other posts. u recommended pads/Allegro/Expedition/…I don't know why I don't like Cadence's software! I checked Expedition and I found a few videos about it and I'm skeptical to use it. but about the PADS I found many professional PCB designers in "LinkedIn" that worked with PADS. what do u think?

author: free_electron
author_rank: Super Contributor
timestamp: February 07, 2019, 04:22:20 pm
content: Quote from: xzswq21 on February 07, 2019, 07:27:25 amMe recommending Cadence or Mentor ? Blasphemy ! Altium, yes !if stray capacitance is a problem : active guarding. look up the Keithley handbook of low voltage low current measurement.

author: xzswq21
author_rank: Frequent Contributor
timestamp: February 07, 2019, 05:05:22 pm
content: Quote from: free_electron on February 07, 2019, 04:22:20 pmhttps://www.eevblog.com/forum/eda/mentor-vs-altium/msg516890/#msg516890Actually I have been using Altium. but I have problem in SI analysis with Altium. have u ever converted Altium file to HyperLynx? all information will be lost so the converted file is useless.. I think I should use PADS but I'm skeptical... Altium is very convenient!

author: xzswq21
author_rank: Frequent Contributor
timestamp: February 07, 2019, 07:55:14 pm
content: Quote from: free_electron on February 07, 2019, 04:22:20 pmhou much stary capacitince do u guess is placed between these pads:it should be less than 1pF. is it a good layout? (solder mask free and many non-plated holes)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 07, 2019, 08:41:42 pm
content: Trying to reduce capacitance is probably a heroic, and ultimately futile, effort.When low capacitance is required, it can be bootstrapped away, at least to some extent (e.g., Phil Hobbs did an IC test probe with something like 0.1pF equivalent, despite the probe end being much larger than 0.1pF equivalent of transmission line). This isn't universally applicable, though.More often, you should just design in the capacitance. Compensate where necessary, harness where possible.For an op-amp circuit, typically capacitance loading the inputs (especially inverting input) is compensated with capacitance from output to inverting node.Tim

author: r0d3z1
author_rank: Regular Contributor
timestamp: February 08, 2019, 01:10:17 pm
content: Layout simulation is an interesting argoument, I also opened a topic about layout simulation some time ago:https://www.eevblog.com/forum/eda/pcb-layout-full-wave-simulator-and-spice-co-simulation/msg1401815/#msg1401815It would be nice to know what this hyperlinx can do.

author: xzswq21
author_rank: Frequent Contributor
timestamp: February 08, 2019, 04:34:55 pm
content: Quote from: T3sl4co1l on February 07, 2019, 08:41:42 pmActually I have invented a new topology for a current source. I have proved the performance in theory and simulation and I defended from it. I have designed the PCB accurately and reviewed lots of books and papers to consider anything. on the other hand I have designed and built a high speed data acquisition to produce and capture the signals. I will post the reslut later.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 08, 2019, 04:56:31 pm
content: The only "new" topology I'm aware of is the shunt CCS I invented back in 2010ish,which I put with this description,QuoteTim

author: xzswq21
author_rank: Frequent Contributor
timestamp: February 08, 2019, 05:11:12 pm
content: Quote from: T3sl4co1l on February 08, 2019, 04:56:31 pmHow much the output impedance of your current source is? tell me about the curent vs loading, linearity...(I think you have invented a DC current source) but my curent source works within some MHz with high output impedance to give u a high resolution. in opposite to other current sources, you can follow all safety CF/BF/B for IEC60601 standard with my current source due to its excellent performance. (it uses for Kelvin probe or Tetra Polar topology). I didn't add any extra ICs but I improved the current source.please give me DOI of ur paper.