Constructive Criticism for SPI master Verilog Code needed! - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: January 08, 2020, 10:11:58 pm
content: Hello all!I wrote this SPI master to interact with a MCP3202 12 bit ADC. It works great, but I would like some feedback on my code. I feel like this is the best product I have produced so far, but I would like to make it better.I have about 6.5 months Verilog/FPGA experience and 100% self taught! I want to know how I am doing in terms of architecture.If you see some things that need some work please let me knowalso if you see some things I am doing good can you please let me know too?Thank you!I am excited to read your comments!my code is here:https://github.com/dominic-meads/SPI-master-for-MCP3202-ADCEDAplayground link for simulation:https://www.edaplayground.com/x/3sLealso I made a youtube video to explain it a bit more:

author: ebclr
author_rank: Super Contributor
timestamp: January 08, 2020, 10:51:46 pm
content: 1st comment your audio level on the video is very low, try a better gain or speak loud next time

author: Dmeads
author_rank: Regular Contributor
timestamp: January 09, 2020, 12:15:29 am
content: gotcha thanks

author: Dmeads
author_rank: Regular Contributor
timestamp: January 09, 2020, 12:16:55 am
content: i just tried headphones and those worked well for me but will make sure to make it louder in the next vid

author: TomS_
author_rank: Frequent Contributor
timestamp: January 09, 2020, 01:38:46 pm
content: You may want to edit the github URL in your post, it has come out a bit trashed and doesnt work out of the box.Also, Im still learning a lot about verilog myself aswell, but are you litterally implementing a "shift register" at full system clock rate? I see a big block of if's that seem to shift in a bit at certain counts, presumably a scaled down clock rate?Surely some kind of clock divider feeding into a shift register "module" would be a better solution here? (Sorry, I havent watched the video, if that is covered in there, just browsing the code during my lunch break at work).Ive watched a few videos by SimplyEmbedded on YouTube which I have found to provide the best demonstration (in my own mind) of how to separate and link together various modules to build bigger more complex implementations.

author: Dmeads
author_rank: Regular Contributor
timestamp: January 09, 2020, 06:58:09 pm
content: hmmm ya very interesting idea about the shift register!Thanks!

author: Dmeads
author_rank: Regular Contributor
timestamp: January 09, 2020, 07:00:59 pm
content: github link should work okay now!

author: TomS_
author_rank: Frequent Contributor
timestamp: January 09, 2020, 07:32:52 pm
content: You have basically implemented one, but in a very roundabout way. I would envisage two modules:1. A clock divider to take your system frequency and divides it down to the rate you want for SCK2. A shift register module into which you feed that SCK clockEach rising or falling edge of SCK you can clock a bit into the shift register.This keeps the two functions, which are distinct in their nature, separated and nicely generic.There are in theory 4 different ways SPI can work in terms of when data is clocked in and out in relation to SCK, so if you are careful enough you can implement a generic shift register that you can use for any SPI requirements you have.