Why am not able to get a grasp of PCB designing? - Page 1
Forum section: electronics / beginners

author: redgear
author_rank: Frequent Contributor
timestamp: November 12, 2019, 09:56:34 am
content: I am trying to design a powerbank myself. This is my first electronics project.After completing the schematic and deciding on the components with a lot of help from this forum, I started working on the PCB Layout. I watched many videos but I just couldn't get started. Idk why.I just get blank when all the components gets populated with the messy rat's net. The datasheet has given some layout rules which I am not able to follow.DAE felt the same when you started? Do you have suggestions for resources that I can start with?

author: I wanted a rude username
author_rank: Frequent Contributor
timestamp: November 12, 2019, 10:10:07 am
content: Set yourself a series of tasks.For the first task, just push and rotate stuff around until the number of connections that cross each other is minimised. Don't even worry about being restricted to a board size/shape or routing any traces at this stage.Post a PNG of your layout at that point and ask for guidance on meeting the design rules.Make mistakes.

author: redgear
author_rank: Frequent Contributor
timestamp: November 12, 2019, 10:17:19 am
content: Quote from: I wanted a rude username on November 12, 2019, 10:10:07 amThanks! I will try doing it and post the png

author: Rerouter
author_rank: Super Contributor
timestamp: November 12, 2019, 10:21:01 am
content: My method is to break any design down to chunks, e.g. this is a charge IC, it has X number of components that belong to it, so lets group them together and lay them out as best I can, Then the next group, and so on,Then after they are all grouped up i start connectiong up and positioning those chunksThis way you never have to try and take the entire project in your head at once, Its always smaller and simpler chunks, It also helps prevent routing yourself into a corner as it usually results in the least connections needed between chunks.

author: redgear
author_rank: Frequent Contributor
timestamp: November 12, 2019, 10:30:07 am
content: Quote from: Rerouter on November 12, 2019, 10:21:01 amThank You.The component I working with is a SOC, so all the components in the schematics are connected to it. Is there an option to selectively populate the PCB from the schematic? May be I can try breaking into blocks and layout in groups

author: Rerouter
author_rank: Super Contributor
timestamp: November 12, 2019, 10:33:58 am
content: I use Kicad, which groups by schematic pages, don't know what your specifically using,Ok to follow my example, is there any 2 parts of the design you can split to reduce how much your working at once? e.g. power in / power out

author: redgear
author_rank: Frequent Contributor
timestamp: November 12, 2019, 10:37:54 am
content: Quote from: Rerouter on November 12, 2019, 10:33:58 amIm using Kicad too. I got everything in a single schematic.Yep, A boost network, output ports

author: Rerouter
author_rank: Super Contributor
timestamp: November 12, 2019, 10:55:24 am
content: Then any way to split it 3 ways? etc,And if not now that its half as big of an issue, pick the one your more compfortable with and start placing out those components. work to reduce crossings and keep lengths minimal,

author: redgear
author_rank: Frequent Contributor
timestamp: November 12, 2019, 10:57:11 am
content: Quote from: Rerouter on November 12, 2019, 10:55:24 amAlright, I will try it.

author: ebastler
author_rank: Super Contributor
timestamp: November 12, 2019, 11:05:29 am
content: Quote from: Rerouter on November 12, 2019, 10:55:24 amI may be underestimating the complexity of a powerbank -- but splitting it into multiple schematic pages seems a bit over the top to me. And if most of the components (or little functional blocks) are connected to a central microcontroller, then the placement of that controller and all the components interfacing to it is a central part of the layout task, and will need to be done with all relevant components in the picture.Also, the placement of connectors and user interface components (LEDs, buttons, or more complex parts) often creates an additional layout constraint. Again, I would want to see all these parts in context. It's OK to start with a larger-than-needed board, but I want to get an idea of what goes on the front and back, how much room the connectors take there, etc.Could you share your schematic and non-routed ratsnest to give us a better idea of the complexity? Preferably as a picture or PDF, since not everyone runs KiCAD. Thanks!

author: NivagSwerdna
author_rank: Super Contributor
timestamp: November 12, 2019, 11:11:04 am
content: Quote from: redgear on November 12, 2019, 10:37:54 amset PCBCAD_Wars ONTry DipTrace. Work through the tutorial.set PCBCAD_Wars OFFPSre: Layout... In my DIY hobby experience as long as the main current paths are nicely flooded it normally works.

author: Rerouter
author_rank: Super Contributor
timestamp: November 12, 2019, 11:20:24 am
content: ebastler, I did not mean split the schematic, I meant group up parts into smaller sections, and just attack section by section, to reduce how "overwhelming" the project feels to the OPNivag, Why would anyone want to lock themselves in with software that limits what they can do, e.g. pay $1000 USD to not be limited, vs spend an amount of time learning the tool like approaching diptrace would involve. I'm personally unclear what diptrace offers that would make me be willing to pay that amount + the time investment to relearn a locked down tool?To the OP, the other thing that may help is you can adjust how the routing works, my personal preference is in the attached image, when routing a wire, right click and you will see "Interactive routing settings"

author: redgear
author_rank: Frequent Contributor
timestamp: November 12, 2019, 11:28:03 am
content: Quote from: ebastler on November 12, 2019, 11:05:29 amYep! Almost everything is connected directly to the microcontroller. Sure, I'm attaching the schematic and ratsnest here.Quote from: Rerouter on November 12, 2019, 11:20:24 amThanks, I will see if that helps.

author: ebastler
author_rank: Super Contributor
timestamp: November 12, 2019, 11:39:55 am
content: Quote from: redgear on November 12, 2019, 11:28:03 amAlright, I can see how that looks intimidating at first.I would start by giving myself lots of room (i.e. pretend that the PCB will be huge), and roughly arrange the components: Connectors to the sides of the board where you want them, passives in loose groups (grouped by function according to the schematic). Roughly shuffle things around to untangle some of the wires.Quite a few of your ratsnest wires will be for GND connections. Not sure how KiCAD handles this, but I would create a GND layer early on to take care of these, to clear up the remaining picture a bit. You might even create a "temporary" GND layer on the top layer, such that KiCAD auto-connects all the GND pads and removes these ratsnest lines. (Eventually, you probably want your GND pour on the bottom, and most of the other connections on top. Then you will need to place vias near the SMD pads which need to be connected to GND.)

author: redgear
author_rank: Frequent Contributor
timestamp: November 12, 2019, 11:48:40 am
content: Quote from: ebastler on November 12, 2019, 11:39:55 amThanks... Let me try and post the progress.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: November 12, 2019, 12:43:28 pm
content: Quote from: Rerouter on November 12, 2019, 11:20:24 amUseability.But shockingly I just checked and it is no longer free! Not For Profit (500 pins, 2 signal layers) is still free if you ask them nicely.

author: cgroen
author_rank: Unknown
timestamp: November 12, 2019, 01:41:45 pm
content: Also remember that many times you can move I/O around on the CPU to get a cleaner layout!Other than that, experience, experience and experience. Start with something simpler, make a lot of layouts. Eventually you will "just do it"

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: November 12, 2019, 02:00:46 pm
content: Quote from: cgroen on November 12, 2019, 01:41:45 pmOP misspoke. It's not a SoC and it's not a microcontroller. It's just a switching converter with a lot more pins and power steering than one might be used to.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: November 12, 2019, 02:14:10 pm
content: OK... I'll try and be a bit more constructive...Looking at the datasheet and schematic suggests that you should (as some suggested earlier) forget about size constraints for now and work radially out from the chip.e.g. the LEDs all need to live on the side nearest their pins, etc. and likewise each output should be put radially out from where they connect... so put the chip in the middle and arrange the connections around them at an angle that reflects the majority of their connections.You can then squish it together laterI would aim to route all non-ground nets first and come back to a ground flood later.(The caps need to go where they are intended... so for example a decoupling cap should really be close to where it is meant to decouple... that can get lost in translation if you aren't careful)

author: rstofer
author_rank: Super Contributor
timestamp: November 12, 2019, 03:55:54 pm
content: ExpressPCB (classic) doesn't do autorouting but what it does do is link the layout to the schematic. So, when I click on a pin that might be Clk, say, all pins on that net are highlighted. All I have to do is lay down a trace. Inevitably, I have to reroute some traces but it usually works out fine.That rat's nest is useless. It provides no information about how to lay things out other than "it's a mess".I haven't used any of the more sophisticated PCB programs, I have always been happy with ExpressPDB (classic).

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 04:53:21 am
content: Quote from: ebastler on November 12, 2019, 11:39:55 amThis didn't work. I tried creating a ground fill on the top layer but the ratsnets is still the same.Quote from: jhpadjustable on November 12, 2019, 02:00:46 pmI might have been wrong but that is how the company calls it. Powerbank SOC. It has a boost converter, Charge Protocol Identifiers and a Battery Gauge built in.Quote from: NivagSwerdna on November 12, 2019, 02:14:10 pmCool. Just arranging the components properly is difficult to me. There are some layout rules on the datasheet(that I don't properly understand) which makes it more difficult.

author: tautech
author_rank: Super Contributor
timestamp: November 13, 2019, 05:52:03 am
content: Start again with a bigger PCB.Drag all components outside the PCB margins.Have the printed schematic handy or on a second display to constantly refer to while placing components.Place first components that must be in a certain place. Lock them.Then place the most complex components.Slowly add other active components while still shifting already placed components to make room for passives yet to come.As others have mentioned build and finalize circuit blocks of which you can select and move/rotate for best connectivity.All the time you need consider how any and all components will be placed, soldered or reworkedandrouted.Use autoroute often to see what you can improve with better placement then un-route and move/rotate stuff.Study old commercial PCB's......lots ! Understand signal/data connectionsandpower rail routing.Use a pour to connect to as many components as you can, orientate them so that you can.Eye up bigger components that might allow traces run under them and place them where this might help you.Be prepared to spend real time on a good layout and don't be too impatient to do so.After a couple of PCB's there'll be no stopping you and you'll spin them out in a fraction of the time your first one took.Post your progress layouts for marking.Daves good PCB guide:http://www.alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdfMore here:https://www.eevblog.com/wiki/index.php?title=Online_Electronics_Tutorials_and_Books#PCB_layout_and_CAD

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 06:20:54 am
content: Quote from: tautech on November 13, 2019, 05:52:03 amTried it, as all connections just go to a single IC it is very difficult for me.Thanks, I will be waiting for the link.

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 06:45:48 am
content: I have disabled ratsnet right now and started grouping components as per the schematic. Will post it once i am done for review

author: james_s
author_rank: Super Contributor
timestamp: November 13, 2019, 06:46:09 am
content: Maybe try some simpler PCBs first to get the hang of it? Lay out some stuff like 555 and transistor multivibrator LED blinkers, op-amp circuits, just easy stuff with a handful of components. Once you get the hang of the process it gets easier.Some people are also just better at visualizing spacial relationships, PCB layout came quite naturally to me but I've seen a lot of people struggle with it.

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 06:51:30 am
content: Quote from: james_s on November 13, 2019, 06:46:09 amOk, I will do that if I don't make any progress today.QuoteI'm honestly bad at those.Btw, I placed a No connection flag on a capacitor but it has still populated on the PCB new.

author: tautech
author_rank: Super Contributor
timestamp: November 13, 2019, 07:22:01 am
content: Quote from: redgear on November 13, 2019, 06:45:48 amDon't, you need it to help visualize future routing.While it seems like a curse and only confuses you it's a very valuable part of getting a PCB layout right.

author: tautech
author_rank: Super Contributor
timestamp: November 13, 2019, 07:32:25 am
content: Watch Dave:

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 09:57:27 am
content: Quote from: blueskull on November 13, 2019, 07:17:10 amI tried placing the parts as they were in the schematic, based on affinity and functionality, I wasn't able to route all traces. Should I connect the traces and place them inside the pcb?Quote from: tautech on November 13, 2019, 07:22:01 amI felt it was easier to arrange the components that way. But the routing became a problem.

author: tautech
author_rank: Super Contributor
timestamp: November 13, 2019, 10:14:19 am
content: Quote from: redgear on November 13, 2019, 09:57:27 amItalwaysis !More layers if there is no other way but there are tricks like using bigger passives so to be able to route traces under them. Jumper wires and zero ohm links are other tricks.Show us your efforts.

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 10:31:57 am
content: Quote from: tautech on November 13, 2019, 10:14:19 amThanks... Will see if I can use any of these.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: November 13, 2019, 12:21:25 pm
content: I am assuming to you are using both sides of the board for traces? Show us what you have got so far. From the datasheet it looks quite do-able with 2 layers.

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 02:45:50 pm
content: Quote from: NivagSwerdna on November 13, 2019, 12:21:25 pmGuess I made some progress. I have completely ignored the layout rules on the datasheet but it's now better than before.Here are the rules from the datasheet:QuoteWhat should be the trace length? For VSYS, VBAT, VOUT and GND it should be more than 100 mils. What about the other traces? What should be the gap between them?

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 03:08:54 pm
content: Quote from: redgear on November 13, 2019, 02:45:50 pmI feel routing this layout would be very difficult. What capacitors need to be really close to the IC? What capacitors can I afford to move to the other layer of the PCB(it's mostly unused). How do I create a pad to solder the battery connections?The components with a NC flag is also populated on the board, I don't really want to use them should I remove them from the schematic or just leave the component unsoldered?

author: NivagSwerdna
author_rank: Super Contributor
timestamp: November 13, 2019, 03:33:06 pm
content: I'm not sure you are listening to the advice being given to you... for example if you rotated the chip 90 clockwise the lines would be better organised radially.Start drawing some traces and see what happens.

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 03:37:03 pm
content: Quote from: NivagSwerdna on November 13, 2019, 03:33:06 pmSorry, i might have missed. But I am trying to follow and improve. I have rotated it now and here is a image.QuoteWhat should be the width of the trace?

author: grbk
author_rank: Contributor
timestamp: November 13, 2019, 03:58:29 pm
content: I don't think you're giving yourself nearly enough room for routing traces in that board. Is there a reason you can't make the board bigger and spread things out? That will make it a lot easier, especially for your first board. You can always make things more closely packed later on if you want to.Trace size will be dependent on where you're manufacturing the board. Many fabs these days have 6 mil minimum trace width and 6 mil spacing but check the design rules for the pcb house you're using. That's a minimum; I would use bigger traces unless you absolutely need tiny traces. I tend to use 8mil traces as default. Use bigger traces if you need lower resistance. Use a pcb calculator to calculate trace resistance for a given width/length. Combined with the expected current, the trace resistance will give you voltage drop and temperature rise. Kicad has a basic multifunction pcb calculator built in but there are others out there, some with more features.The NC flag in Kicad just means that you are not intending to connect anything to that pin. Normally the electrical rules checker will complain if any pins aren't connected to a net; the NC flag tells ERC that it isn't a mistake and that pin is intentionally disconnected. It does not tell kicad that you want that part excluded from the layout. If you don't want a part on your board, either remove the part from the schematic entirely, or edit its reference designator to start with a # (for example, if you didn't want R101 to be included in layout, call it #R101 instead). In this case I would recommend just deleting the part -- if you don't want it on the board, why is it in your schematic? You could also leave it in your schematic & layout, but not solder the part. In this case I would add a "DNP" (do not populate) note in the properties for the schematic symbol for the part to remind yourself or anyone else that the part should not be actually assembled onto the board.

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 04:21:12 pm
content: Quote from: grbk on November 13, 2019, 03:58:29 pmYep, I am targeting that as my final board dimension. The back side of the board is largely unused, if I could move some components there, I guess I can make enough space to accommodate everything with in this board dimension. But I am not sure about the components that I can move to the other side without affecting the performance. Decoupling caps need to be as close as possible to the IC, I am not sure if they can be placed on the other side of the board.QuoteCool, thanks. I will try using the calculators.QuoteOh, got it. Will make it a practice hereafter.

author: tooki
author_rank: Super Contributor
timestamp: November 13, 2019, 04:23:37 pm
content: You absolutely can put decoupling caps on the other side, it’s actually a really common technique that often lets you get the cap even closer to the pin than you would on the same side.

author: redgear
author_rank: Frequent Contributor
timestamp: November 13, 2019, 04:29:07 pm
content: Quote from: tooki on November 13, 2019, 04:23:37 pmOk. Thank you. I will try modifying the layout.

author: tautech
author_rank: Super Contributor
timestamp: November 13, 2019, 06:08:36 pm
content: Does Kicad have a single layer view/working mode ?Put all the big components on the back side plus any LED's and the IC and most passives on the other side.That alone should make this quite doable.

author: grbk
author_rank: Contributor
timestamp: November 13, 2019, 07:29:51 pm
content: Quote from: tautech on November 13, 2019, 06:08:36 pmYes, that's a good point. In Kicad you can turn off unnecessary layers by unchecking them in the layer pane on the right. This gives you complete control over which layers are displayed. There's also a "high contrast" display mode that I like a lot; when you turn it on the active layer is displayed as normal, but other layers are displayed in a unobtrusive gray color that helps them fade into the background. Like tautech says this can be very helpful for focusing on what's currently important, and I recommend you try it.

author: tautech
author_rank: Super Contributor
timestamp: November 13, 2019, 07:38:13 pm
content: Quote from: grbk on November 13, 2019, 07:29:51 pmYep.Still redgear has to get his head around working with multiple layers and assigning any components properties to the correct layer which when done lets you better see on which layer they actually are.Not the easiest project for first up but a little guidance will get him there.

author: james_s
author_rank: Super Contributor
timestamp: November 14, 2019, 02:53:02 am
content: I really try to keep all components on one side of the board unless I really need some on the back, the only time I ever have is decoupling capacitors on some relatively dense boards. It's just a pain to assemble boards that have parts on both sides, especially when doing reflow soldering.

author: redgear
author_rank: Frequent Contributor
timestamp: November 14, 2019, 04:58:06 am
content: Quote from: grbk on November 13, 2019, 07:29:51 pmThis feature has made working with the board easier. Thanks.Quote from: tautech on November 13, 2019, 07:38:13 pmI'm currently working on rearranging the components on different layer, will post a pic once I'm done.Thank you everyone for the amazing support.

author: redgear
author_rank: Frequent Contributor
timestamp: November 14, 2019, 05:07:06 am
content: Many resistors are beefier in this design. I haven't calculated the power rating required and used slightly bigger ones. Proper calculation of power rating of resistors can help me bring down the size of the footprints, providing more space for traces.P=V2/R, but what should be the value of the voltage? The voltage fed to the boost circuit? The maximum output voltage of the boost circuit?

author: redgear
author_rank: Frequent Contributor
timestamp: November 14, 2019, 08:15:26 am
content: Quote from: tautech on November 13, 2019, 07:38:13 pmI have now utilized both layers of the PCB. Is my design any better than it was? Can it be properly routed?

author: tautech
author_rank: Super Contributor
timestamp: November 14, 2019, 09:03:32 am
content: Quote from: redgear on November 14, 2019, 08:15:26 amYes.First thing I spotted, top 2 resistors by the switch....rotate them vertical for better connectivity/easier routing.While the purists like every device group orientated the same sometimes it's easier to flip and swap to make for easier routing.Apply similar thinking throughout the PCB and you'll be staggered how much easier things become.Shift some component designators off the device so it's easier for us to pick a # that should be moved/flipped etc.Stackthemalongsidesomehowlike this.

author: redgear
author_rank: Frequent Contributor
timestamp: November 14, 2019, 09:14:43 am
content: Quote from: tautech on November 14, 2019, 09:03:32 amThanks a lot! I am working on making the changes.

author: james_s
author_rank: Super Contributor
timestamp: November 14, 2019, 05:16:36 pm
content: Quote from: redgear on November 14, 2019, 05:07:06 amThe maximum voltage across the resistor. This of course depends heavily on where it is used, in most cases the power will be very low except for resistors used for current sensing and such.

author: redgear
author_rank: Frequent Contributor
timestamp: November 15, 2019, 04:42:17 am
content: Quote from: james_s on November 14, 2019, 05:16:36 pmOk, so I should calculate the power rating of each resistor.Just to check if I am doing it right,The resistor R11 on USB C is 10k. The maximum voltage it will see is 12v. The power rating of the resistor using the formulaP=V2/Rgives, 1/100 Watt. Is that correct?How do I determine the power rating for the resistors where I'm not sure about the voltage it will see, like the current sense resistor or the R2 114k on the RSET pin?Thanks

author: redgear
author_rank: Frequent Contributor
timestamp: November 15, 2019, 05:11:19 am
content: Quote from: tautech on November 14, 2019, 09:03:32 amDone. Here is a pictureAny more suggestions?Edit : After taking the pic, I rotated the resistors R5 and R9 to make connections easier.

author: ebastler
author_rank: Super Contributor
timestamp: November 15, 2019, 06:04:20 am
content: That latest placement looks pretty good, I think. Only change I would suggest: Give yourself a bit more room around the main IC by making the PCB larger in the vertical direction. The passives above and below are very close to the IC, so you might run out of room for the traces. You can always push things closer together later -- while I have not used KiCAD, I read that its push-and-shove router works quite well.Time to start the routing! (Which will probably lead you to some more tweaks in the placement once you look at the routing details.)

author: tautech
author_rank: Super Contributor
timestamp: November 15, 2019, 07:09:55 am
content: Quote from: redgear on November 15, 2019, 05:11:19 amQuoteLots, really lots.More of the above, much more.You are gaining the vision required but keep looking and looking and after an autoroute of two you will see more. Pick a net or two and focus on getting them the best you can the rinse and repeat with other nets.At a glance a few simple pointers.Flip and lower D6 so to run the GND trace around the top to J3.Flip TH1 and R8 then you have just one trace to sort out the routing for and lift it a little and run the trace along the edge of the board.Move Q2 to between Q4 and U1.Consider rearranging Q1-4 and associated components to allow for easier/better routing.Don't bunch SMD passives too close to bigger components. (later you'll thank me.)Tidy up labeling even though after routing you may need to do it again. Use same font size for all.That's an hour of two's work to sort out and enough for now so to not piss you off too much.

author: redgear
author_rank: Frequent Contributor
timestamp: November 15, 2019, 08:28:52 am
content: I really appreciate you taking the time to guide me. Thank you so much.Quote from: tautech on November 15, 2019, 07:09:55 amI planned to keep all the power FETs in one section. I will try rearranging it.QuoteAre you talking about the capacitor networks? Aren't they supposed to be as close as possible to the ICs?And the LEDs, I cannot rearrange them since I planning the mechanical enclosure to have LEDs at the center.QuoteOk

author: tautech
author_rank: Super Contributor
timestamp: November 15, 2019, 08:58:40 am
content: Quote from: redgear on November 15, 2019, 08:28:52 amNo probs, I just happened to the Johnny on the spot.I don't do much now but really got hooked on making a nice job of PCB's for a while as with a little bit of practice it gets quite addictive. After a bit you can pick holes in most ppls work and see how you might have done it better. You can spend days on even a modest PCB, layout correction after another then a heap of time interactive routing but guys that can really make CAD programs talk spend a bit of time on the global settings then the program does most of the work.Still you learn a lot doing it longhand as it were then with the good CAD programs let the settings made save you the hassle.Quote from: redgear on November 15, 2019, 08:28:52 amNo, it's just a general statement for C's and R's.Earlier I said always to consider rework so if placement doesn't allow getting an iron to a component how do you replace just that component should you need to ? For first up prototypes this can be important as there's often component substitutions to make the circuit work as planned.Yeah I know, drag out the hot air you'll say but what about all the surrounding components when you could have done it with an iron. BTW if you haven't got a K style Hakko type tip get one ! Some call them a skew but either way they allow the ability to heat both ends of SMD passives for shit easy removal.

author: Rerouter
author_rank: Super Contributor
timestamp: November 15, 2019, 09:11:32 am
content: The capacitors should be as close as reasonable, (minimizing inductance, loop area, all that jazz) but if the capacitor is so close to the IC or another capacitor that it is a right pain to prevent shorting or fit, then it kind of hurts the benefit of the closer positioning, `remember the loop for decoupling includes any via's, and the ground routing on the other side, this is why decoupling caps on really fast devices (high switching frequencies) will have the decoupling capacitor practically straddling the vias for a short run back to the pins that it needs to decouple, or in some cases routed with the return path coupled as close as possible,

author: NivagSwerdna
author_rank: Super Contributor
timestamp: November 15, 2019, 09:52:43 am
content: re: Image aboveMuch better. Imagine you are trying to unknot a ball of string...By flipping the components you can untwist the string... all 3 parts in the top left are obvious candidates.

author: ebastler
author_rank: Super Contributor
timestamp: November 15, 2019, 03:11:06 pm
content: Quote from: Ariousig on November 15, 2019, 12:41:04 pmIt's best to actually read the thread, not just the title of the first post, before replying.And no, I'm feeling fine, thank you very much.Interesting choice of user name...

author: redgear
author_rank: Frequent Contributor
timestamp: November 16, 2019, 05:31:44 am
content: Quote from: tautech on November 15, 2019, 08:58:40 amAfter I finish this PCB, I will see what all settings I can play with to make this job easier....In your last post you suggested me to consider rearranging the FETs, but I am not able to find a better place.QuoteThanks for the recommendation, I'm actually planning to invest on a good soldering station.Quote from: Rerouter on November 15, 2019, 09:11:32 amThank you, another reason for me placing them very close is they looked better that way.Quote from: NivagSwerdna on November 15, 2019, 09:52:43 amThanks, I can't move the USB ports and the switch, I placed them according to their mechanical orientation.

author: tautech
author_rank: Super Contributor
timestamp: November 16, 2019, 06:18:34 am
content: Quote from: redgear on November 16, 2019, 05:31:44 amWell, I hoped you could see the hole just begging for Q2 to be placed in it !

author: tautech
author_rank: Super Contributor
timestamp: November 24, 2019, 09:34:14 am
content: OK redgear, have you given up or too shy to come back and show off your efforts ?

author: max_torque
author_rank: Super Contributor
timestamp: November 24, 2019, 06:04:21 pm
content: Quite possibly a bit late, but one "trick" that seems to work repeatibly is to orient "square" micros at 45 deg, in this way, they can have traces come off in two directions without requiring as much "packing in" to the space. In reality, unless you have a perfectly square pcb, and can use all 4 sides around the micro, this 45 deg layout tends to be easier to route ime!

author: redgear
author_rank: Frequent Contributor
timestamp: November 25, 2019, 04:53:57 am
content: Quote from: tautech on November 24, 2019, 09:34:14 amNope, I haven't given up neither shy. I am making some changes to my schematic, replacing the controller with a better one. So, will post an update very soon.Quote from: max_torque on November 24, 2019, 06:04:21 pmBut I am able to make only 90deg rotations on Kicad.Edit: Just found out how to rotate footprints 45deg. Thanks for the trick

author: Rerouter
author_rank: Super Contributor
timestamp: November 25, 2019, 07:43:17 am
content: you can set the rotation step size to whatever you wish, I usually use 22.5 degrees, you can also draw curvy traces with kicad with a little work if you need to work around very compact spacing. (free angle mode, and replace the corner twice to get very close to a smooth curves

author: ebastler
author_rank: Super Contributor
timestamp: November 25, 2019, 09:29:18 am
content: Quote from: Rerouter on November 25, 2019, 07:43:17 amThat looks rather vintage! Just as wobbly as the classic taped layouts.I can see the benefit this might have in some tight spots. But without full support in the PCB layout software -- splines or such to create smooth curves, and precise matching of the shape of neighboring traces in push-and-shove mode -- it seems very burdensome, and the result is not as neat as I would like.

author: thinkfat
author_rank: Unknown
timestamp: November 25, 2019, 09:56:25 am
content: It seems you're routing some differential signals, going by the net labels on the top right socket (DPA1, DMA1). You'll need to give these priority during routing. Make sure you rename the nets to DA1_P, DA1_N, or KiCad will not be able to figure out the routing pairs. I'm guessing you are going for a standard FR4 board with 1.6mm final thickness, that'll make correct impedance nigh impossible, but you should at least get the lengths matched. Should not be a huge problem for USB1 class speeds.

author: redgear
author_rank: Frequent Contributor
timestamp: November 25, 2019, 10:09:16 am
content: Quote from: thinkfat on November 25, 2019, 09:56:25 amThanks. Why shouldn't I use the DMA/DPA labels?

author: thinkfat
author_rank: Unknown
timestamp: November 25, 2019, 10:41:30 am
content: Quote from: redgear on November 25, 2019, 10:09:16 amQuoteThe interactive router in KiCad has a special mode for differential pairs, but you need to name the nets of the pair accordingly. They must end in "_P" and "_N".

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: November 25, 2019, 10:43:02 am
content: + / - are also acceptable. e.g. A1D+ and A1D-

author: redgear
author_rank: Frequent Contributor
timestamp: November 25, 2019, 10:49:18 am
content: Quote from: thinkfat on November 25, 2019, 10:41:30 amQuote from: jhpadjustable on November 25, 2019, 10:43:02 amThanks

author: EEVblog
author_rank: Unknown
timestamp: November 25, 2019, 10:55:09 am
content: Quote from: tautech on November 13, 2019, 07:32:25 amI have another one:

author: redgear
author_rank: Frequent Contributor
timestamp: November 25, 2019, 10:56:54 am
content: Quote from: EEVblog on November 25, 2019, 10:55:09 amThanks Dave, I have watched both the videos. I am using KiCad and i'm finding it a bit different(and difficult) than Altium.

author: EEVblog
author_rank: Unknown
timestamp: November 25, 2019, 10:57:47 am
content: Quote from: redgear on November 15, 2019, 05:11:19 amFirst thing I noticed was the cross on the rats nets for Q2 and Q4/Q3, I'd swap these so the rats net don't cross, then you can route directly.

author: EEVblog
author_rank: Unknown
timestamp: November 25, 2019, 11:00:08 am
content: Quote from: redgear on November 25, 2019, 10:56:54 amYou've done 90% of the work, which is the schematic, netlist, footprints, and component placement. Actually routing that board takes the same amount of time in any package, they are all basically the same productivity at that point with manual routing.

author: redgear
author_rank: Frequent Contributor
timestamp: November 25, 2019, 11:04:04 am
content: Quote from: EEVblog on November 25, 2019, 11:00:08 amI'm just getting blocked at many points while trying to route. I think it will get better with practice. Also, they are traces that needs to be thicker than the rest and I'm just getting confused.

author: thinkfat
author_rank: Unknown
timestamp: November 25, 2019, 11:36:30 am
content: Quote from: redgear on November 25, 2019, 11:04:04 amI always found the ratsnet being the most helpful visual aid while placing components. Every "airwire" crossing another wire is a hint that something isn't quite right yet. You turn and shove components around until the tangle unravels. It's just a skill you develop by doing it over and over. After a while you just "see" paths for tracks while you place the components. Also, building little compartments helps a lot to reduce the complexity. It's like small fish following big fish: every major component has a zoo of smaller stuff following it around - decoupling capacitors, resistors, etc. You group them together, placing them with minimal crossing ratsnet lines of minimal length and then you move the whole group to their final place on the board. After you've done that for all the major functional blocks you connect them with tracks.Placement is the main work anyway, when you've done that properly, the rest is just "connect the dots".Regarding track widths and getting confused what is what, that's what "net classes" are for.

author: redgear
author_rank: Frequent Contributor
timestamp: November 27, 2019, 08:26:03 am
content: Quote from: thinkfat on November 25, 2019, 11:36:30 amYep, I am not telling it is not useful. But as a beginner looking at ratsnet is scary for me. And how much ever orientations I try I am not able to untangle them.

author: tautech
author_rank: Super Contributor
timestamp: November 27, 2019, 09:12:08 am
content: Quote from: redgear on November 27, 2019, 08:26:03 amYeah well you did take on something a bit complex first up.The ratsnest is you placement lifeline first then your eyes as to possible routing solutions.Something less complex and forcing yourself to do it on a single layer is the way to get your head around it along with a not too stifling PCB size until more experience is gained.It might seem I ramble on a bit but my posts are not just directed at you but for the wider audience that also follow this stuff.Still, do show progress as there's plenty of us here to help if you get really stuck.

author: redgear
author_rank: Frequent Contributor
timestamp: November 27, 2019, 09:26:47 am
content: Quote from: tautech on November 27, 2019, 09:12:08 amYour replies on this thread has been very informational for me. I have been following the advice you(and everyone else on this thread) have given me. Like I said, when I was about to start routing the older layout, I found a better IC and I decided to start from the beginning again. I have few DRC errors on the schematic and I'm trying to correct. I even created anew topicand got some advice from jhpadjustable but still there are a few errors. Once I fix them, I will start with the PCB design.

author: redgear
author_rank: Frequent Contributor
timestamp: November 28, 2019, 10:45:40 am
content: Quote from: tautech on November 27, 2019, 09:12:08 amStarted working on the new PCB.So far...

author: tautech
author_rank: Super Contributor
timestamp: November 29, 2019, 09:32:14 am
content: Quote from: redgear on November 28, 2019, 10:45:40 amHad a look at the new schematic and wondered why you have so many caps on the same rail and their purpose ?What's DS1 ? See how many ratsnest traces go to it from the tight side of the IC. Pop that IC on the other layer and it becomes flipped so that bundle of ratsnest traces will be easier to route.Several of the bipolar/FET traces come from the same side of the IC so they all might benefit from flipping it onto the other layer.BTW, don't embed the image, just keep it as a thumbnail then we can download it a blow it up larger more easily.

author: redgear
author_rank: Frequent Contributor
timestamp: November 29, 2019, 09:57:54 am
content: Quote from: tautech on November 29, 2019, 09:32:14 amI designed it based on the reference design on the datasheet. The capacitors are for reducing ripple and EMI. The previous design had an extra elcap which I have not included in this design. I am thinking if I should add it for extra stability.QuoteIt is a 7 segment LED Display. OkQuoteOk, will flip the FETs to the other side of the board.QuoteNoted.

author: tautech
author_rank: Super Contributor
timestamp: November 29, 2019, 10:06:40 am
content: Quote from: redgear on November 29, 2019, 09:57:54 am8x 22uF caps, that's nuts !Ceramic, right ?Sub them out for a couple of 100uF SMD tantalums.

author: redgear
author_rank: Frequent Contributor
timestamp: November 29, 2019, 10:10:58 am
content: Quote from: tautech on November 29, 2019, 10:06:40 amYeah, ceramic. This is my first project so haven't tried anything out of the datasheet.QuoteOk, so 100uF on both SW and VOUT networks,right?

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: November 29, 2019, 10:23:35 am
content: Quote from: tautech on November 29, 2019, 10:06:40 am"Nuts" is not an engineering justification. It's far from uncommon to see stacked ceramics in SMPS power supply applications. Personally, I would like to see some analysis of that change before counseling the addition of detonators into what are already not far from bombs.

author: tautech
author_rank: Super Contributor
timestamp: November 29, 2019, 10:24:53 am
content: Quote from: redgear on November 29, 2019, 10:10:58 amNope, a Net called BAT has 4x when 1 would do.BTW, see how Net Bat has a name but not a Net label like many others. Gnd for example....BTW they should always point down.When you use hidden connections like VCC/VDD for a IC be sure to assign them a Net label then the program does the rest and creates a ratsnest link whereas if you don't things become disconnected.

author: redgear
author_rank: Frequent Contributor
timestamp: November 29, 2019, 10:33:26 am
content: Quote from: tautech on November 29, 2019, 10:24:53 amI used the net label for it just like I did for others. By 'Point Down' do you meant the label should be at the bottom of the wire?QuoteYeah, I did that.Thanks

author: redgear
author_rank: Frequent Contributor
timestamp: December 02, 2019, 06:10:24 am
content: @tautechUpdate:I have managed to place the all components within my board boundaries and have made it less messy than before.Need sugggestions...I am attaching the png with this reply.

author: thinkfat
author_rank: Unknown
timestamp: December 02, 2019, 08:47:28 am
content: With C1/C2 right there, it's going to be tricky to route the differential traces to J6. If you turn the controller 45° clockwise, it might become easier.Also, what are all those net-ties doing there? They seem to serve no actual purpose. What nets to you need to tie together?Rotate Q1 90° anticlockwise to shorten some traces.Place C3 directly adjacent to the pads it's connecting to, move the whole group a bit to the right to make space.What's the purpose of Q3/Q4/Q6, VBUS switching? It looks like they'd better be place on the left side of the controller, and the controller moved towards the right to make space. This would also make routing to J6 easier. Or, if they actually do VBUS switching, they functionally belong the connectors, so move them over.Move C5 closer to the controller pads it connects to, reduces waste of board area.Giving hints on component placement is really hard if you don't provide schematics...EDIT: I found a PDF with schematics attached to a prior post, mango.pdf, is that the latest one?Update: Oh yeah, as others noted, DS1 must go away there. Flip it 180° and move it to the bottom of the board.

author: tautech
author_rank: Super Contributor
timestamp: December 02, 2019, 08:49:41 am
content: Thanks, that makes it much easier.My eyes are drawn to the components with the most ratsnest connections so I would endeavor to optimize their placement first.Passives with a Gnd connection are much easier as you really only have to find a routing path for one connection as a Gnd is generally always close by. Any you can easily rotate them to make for simpler routing.In the same way I look for crossed ratsnest connections like to D27 where you might have 2 choices, rotate either D27 or the IC 180 degrees.The big green pad bottom right has a trace that goes clean across the PCB whereas if it was shifted up near C16 there are better paths for it's other connections yet vias and other side routing might still be needed.Push, pull, jiggle and rotate one of two things at a time and pathways will open and become simpler, shorter and better.R2, 3 and 4 need rearranging. NT4 can be flipped. C5 can be vertical....and so on.Focus on the big stuff with lots of connections going to one place, especially if from adjacent pins all in a row as it's easy to simple route them rather than make things tight needing to find room for vias.It might help to go into single layer mode rather than have to look at the complete ratsnest and things should become clearer.Looking forward to your next iteration.

author: Rerouter
author_rank: Super Contributor
timestamp: December 02, 2019, 09:14:17 am
content: If you would be willing to zip the project files, I'd be happy to see what I can make of it,Also your DS1 component if going to be a real pain there as you cannot route through it

author: redgear
author_rank: Frequent Contributor
timestamp: December 02, 2019, 10:18:59 am
content: Quote from: thinkfat on December 02, 2019, 08:47:28 amDone.QuoteThe net-ties are for connecting the mosfets drains to the IC. I am attaching the schematic so you can have a look.QuoteYes, they are responsible for current sensing and act as a switch to the connectors.QuoteSorry! I'm attaching it with this reply.QuoteIt is a 7 segment LED display and that is where I want to place it mechanically.Quote from: tautech on December 02, 2019, 08:49:41 amDo you mean the DS1? I took thinkfat's suggestion to rotate the IC 45deg, I think its better than before now.QuoteDone.QuoteOk.I have been sketching the components on paper and arranging them, i feel easier that way.QuoteIdk if Kicad has a single layer mode, but I can make the either Back or Front planes invisible if that is what you mean.Quote from: Rerouter on December 02, 2019, 09:14:17 amThanks. Do you mind if I send you a private message?@thinkfat and @tautech I'm attaching the next iteration of the PCB. Please have a look.

author: thinkfat
author_rank: Unknown
timestamp: December 02, 2019, 10:59:55 am
content: Quote from: redgear on December 02, 2019, 10:18:59 amOK, so they're not serving a real purpose. Drop them, it will at least make the ratsnest connections more clear.Quote from: redgear on December 02, 2019, 10:18:59 amSeems you forgot.Quote from: redgear on December 02, 2019, 10:18:59 ambummer that... OK, well, you'll have to suck it up, then.Quote from: redgear on December 02, 2019, 10:18:59 amPress 'H' and see if the result helps you.Quote from: redgear on December 02, 2019, 10:18:59 amAre you hellbound on the placement of those connectors? The routing would become much easier if J4 and J5/J6 swapped places.

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: December 02, 2019, 12:07:52 pm
content: Quote from: thinkfat on December 02, 2019, 10:59:55 amThat was me. I suggested redgear add them so that the current/voltage sensing at the MOSFETs would be distinctly routable. Is that overkill?

author: thinkfat
author_rank: Unknown
timestamp: December 02, 2019, 04:03:38 pm
content: Quote from: jhpadjustable on December 02, 2019, 12:07:52 pmAh, OK! So you wanted them as attachment points for sense wires? I actually never thought of that.I'd probably not do it like that. IMHO it creates more constraints on routing and placement for the sake of having different net names.

author: tautech
author_rank: Super Contributor
timestamp: December 02, 2019, 04:44:37 pm
content: Provide a list of locked components.Move any designators so it's clear which component they belong to.Place some designators within the footprints of large components for the meanwhile.C17,18 appears to have the same net for both pads.If convenient on dumb components swap the nets to the other pad. (switches etc)Rotate IC 180otaking small passives with the rotate. (R2,3,4,7,8,9, C4,5)That's enough for now.

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: December 02, 2019, 05:06:01 pm
content: Quote from: thinkfat on December 02, 2019, 04:03:38 pmI'd gotten the impression from the datasheet (p3, attached inOP's other thread) that's what the VOUTA etc. pins were for. I'm not 100% sure what the chip maker was thinking, though. Maybe the net ties i recommended were intended to be actual resistors but not drawn as such on the typical application circuit (p23)?

author: thinkfat
author_rank: Unknown
timestamp: December 02, 2019, 09:10:25 pm
content: Quote from: jhpadjustable on December 02, 2019, 05:06:01 pmThe VOUTA VBUSA etc. pins are indeed sensing pins, to switch off the port when no load is connected. They're using the Rds_on of the gating mosfet as a current sense resistor. That's creative ;-)VOUTA pins are the same net as VOUTP. However, they should be connected close to the mostfets, and the mosfets should be placed close to their respective receptacles, just like you would do with a current sense resistor. You want to exclude the burden voltage of the traces from the measurement, though it won't matter a lot here, the Rds_on of the mosfets is whatever it is anyway. But we're still talking milli-ohms and a piece of trace will matter.But, as a first project, this is going to be a struggle. It's not just about placing the components and connecting them, there's a boost converter, differential signals, analog sensing, that's a lot of constraints to take into account. Don't forget the thermal design, this converter needs to dump the waste heat somewhere...

author: redgear
author_rank: Frequent Contributor
timestamp: December 03, 2019, 08:00:07 am
content: Quote from: thinkfat on December 02, 2019, 10:59:55 amPlease find it with this reply. Sorry.QuoteNo change.QuoteNope. Except DS1 and SW1 I am free to move anything anywhere.Quote from: thinkfat on December 02, 2019, 09:10:25 pmShould I ditch the Net-ties? I initially had thermal vias on the IC but removed it as became difficult to place components. Should I uses thermal vias?Quote from: tautech on December 02, 2019, 04:44:37 pmExcept for DS1 and SW1 in the new image(swapped J5 and J6 to the other side following @thinkfat's suggestion) below, I am free to move anything anywhere.QuoteHope they are better now.QuoteNo, there are two USBs on both sides of the board. They placed exactly opposite. So, in the image it looks like they have same nets on both pads.

author: tautech
author_rank: Super Contributor
timestamp: December 03, 2019, 08:36:36 am
content: Looking better.How do you feel about progress thus far ?Can you name the USB socket designator that's on both sides ?How do you feel about rotating the IC another 45oto the left ?

author: redgear
author_rank: Frequent Contributor
timestamp: December 03, 2019, 08:50:31 am
content: Quote from: tautech on December 03, 2019, 08:36:36 amThanks.This is cool! Awesome. What I once thought I could never do, I am almost there.Thanks a lot for everyone who helped.QuoteJ5 and J6.Let me try...

author: tautech
author_rank: Super Contributor
timestamp: December 03, 2019, 08:56:47 am
content: Quote from: redgear on December 03, 2019, 08:50:31 amThat's made my day.Really happy to see you getting your head around it and congrats for sticking at it.If the 45 anticlockwise doesn't look viable it don't matter as you've proved if it is by trying it.

author: thinkfat
author_rank: Unknown
timestamp: December 03, 2019, 09:00:12 am
content: I think it's getting somewhere now. Good job!Now, I think you can keep the net ties, if they help you staying close to the the sample schematic and if they don't confuse you, just keep in mind to treat them as a sub-part of the mosfets they're attached to and keep them close together.On the question of thermal vias - yes, you need them. And you need to keep a considerable area of copper below the IC so that the heat can go somewhere. Also, the power pad seems to be the main ground connection, you'll need to keep that in mind.There's a few other things to consider:- the VOUT portion is the main power rail for the USB connectors. You need a quite beefy connection there, placing the capacitors on the opposite side of the PCB needs some care taken. I don't know how many amps you plan to source simultaneously, but keep in mind that you need a significant trace width. If the capacitors are supposed to stay on the bottom side, you'll need plenty of vias to keep the inductance low.- I didn't see straight and suggested to keep J3 where it is, but if you look at the ratsnets, it'll be even easier if you swap J3 and J4.- Around the switching part of the boost converter, you'll need to think about keeping ground loops very tight. The copper area of the SW node should be kept small. Place L1 close to the IC pins and on the top side. The thing looks _huge_. Which component did you choose? Maybe you can find a different type that exchanges PCB area with height? But I'm not sure about the overall dimensions. Also, treat this area with care while routing traces on the bottom side, make sure to not cut or obstruct the ground loop of the boost converter part. There'll be high switching currents flowing, you need as low an impedance as you can get. It's a shame the chip vendor doesn't provide a layout suggestion.

author: redgear
author_rank: Frequent Contributor
timestamp: December 03, 2019, 09:51:18 am
content: Quote from: thinkfat on December 03, 2019, 09:00:12 amThanks.QuoteThe sample schematic does not use net-ties, @jhpadjustable suggested to add them and helped me around the DRC errors in schematics.QuoteOkQuoteThe max current will be 4A. I was considering something around 100-110 mils. I used a online trace width calculator and the result was 104mils. Nope the capacitors can be placed on the top side too. While the chip's datasheet gives no layout recommendations, a similar chip that i selected previously wanted those capacitors on VOUT network to be placed as close as possible to IC. So, I just put them directly underneath. There is still space for the capacitor to be accommodated on the top side of the board. If that is better, I will flip them to the top.QuoteDone, exchanged them.QuoteOk. Does it make sense to flip the mosfets to the back and get the inductor on top near the IC? I went with the one that was recommended in the BOM. Here is the datasheetSPM10102R2MESN. I was not able to find a footprint online so I created one myself, I might have made a mistake if that component looks unsually huge.Thanks

author: Rerouter
author_rank: Super Contributor
timestamp: December 03, 2019, 10:31:27 am
content: Had a play around trying to reduce how many headaches there where (e.g. trying to keep the switching node at least a little away from the USB differential, and how to lay that out with minimal crossing)seems to me the best result is if you treat the chip like a switch mode converter first, keeping loop area as small as possible and all that fun, then running the USB in the order you have it assigned (even if the USB is just for signalling, my mind is still clinging to routing it out with minimal crossings,Also had a play with your battery connection area to keep the connections as short as possible,next steps from here would probably be to shift the micro more central, to keep those battery connections short, while keeping as much distance as possible from the inductor switching node and the usb pairs.those 0201 components will be a right pain to solder, if you can, I would recommend larger parts for ease of assembly,I should also mention, the trace width calculations can be cheated a little, sometimes it is better to have a thinner but shorter connection than a wider but longer one, the big one may reduce the amount of heat per unit distance, but a shorter connection reduces that distance.

author: thinkfat
author_rank: Unknown
timestamp: December 03, 2019, 10:36:36 am
content: The correct land pattern is shown on p.83, if you used that one it's likely OK, but also the it's quite a huge component, 11mm x 10mm. Looking at their datasheet, you could likely go with a smaller device, like an SPM5050xxx. I've used Coilcraft XAL5030 inductors for switching converters with good results. For example, the XAL5030-222MEC, it's around 5mm x 5mm, could fit your design.About flipping the transistors to the other side - well, you need to make up your mind, I would put each of the transistors closer to the USB receptacles they will switch power to, but keep in mind that you also need to route the sense wires. You need to develop a general idea of where certain nets should go. For example, you could decide that the high-current stuff should stay on the top layer and that you'll route the sense wires on the bottom.It might be a good idea to route the VOUTP net as a beefy trace on the border of the PCB, out to the right and then up and then to the left along the top edge, and feed the mosfets from there. That keeps the power distribution out of the way of the USB signals that you also need to route. You could then drop the sense lines and the gate signals to the bottom layer of the PCB and route them back to the IC. They have no speed or current requirements and might not mind a few vias.

author: thinkfat
author_rank: Unknown
timestamp: December 03, 2019, 10:50:23 am
content: Quote from: Rerouter on December 03, 2019, 10:31:27 amThat looks pretty good already. I agree the controller should be more central, close as possible to the battery protection circuit. but still positioned so that the display socket doesn't obstruct the USB traces. Close to the bottom would be good I think.Also, I don't see a reason for putting all the high-power components on the bottom side, there's plenty of space between the USB receptacles to put e.g. the mosfets and there isn't much more that you need to place. As a general strategy I'd use "power distribution and usb signals on top layer, ground plane, slow signals and sensing on the bottom". The small jellybean stuff can go to the bottom side too.

author: redgear
author_rank: Frequent Contributor
timestamp: December 03, 2019, 10:59:54 am
content: Quote from: Rerouter on December 03, 2019, 10:31:27 amThanks. I will try to do it again from scratch.Quote@thinkfat suggested I keep the inductor on the top layer but I find it is on the bottom layer in your design. Should I place it on the top layer?QuoteBigger components takes more space, so I was thinking to go with reflow method.QuoteThanks for the tip...Quote from: thinkfat on December 03, 2019, 10:36:36 amYes, I used the same dimensions. Ok, I will try to look for components with smaller footprints. I tried using the Digikey filter before I started but sadly I did not find any.QuoteAlright, I will redo it. Hope I develop these over time so I could do it right the first time.QuoteOk, let me try this.Thanks.

author: redgear
author_rank: Frequent Contributor
timestamp: December 04, 2019, 05:09:10 am
content: Quote from: thinkfat on December 03, 2019, 10:36:36 amIf I choose to have the high current stuff at the top, should also flip the battery protection to the top layer?QuoteIf I am going to do this, can I remove the net-ties?

author: redgear
author_rank: Frequent Contributor
timestamp: December 04, 2019, 06:07:43 am
content: I managed to find a Design Recommendations for the chip in Chinese. The document gives me headache. Feels like I hit a roadblock again. I am attaching it with this reply.

author: tautech
author_rank: Super Contributor
timestamp: December 04, 2019, 06:52:01 am
content: Quote from: redgear on December 04, 2019, 06:07:43 amIf you can copy paste, drop it in here:https://translate.google.com/Build a new English doc in MS Word or similar.

author: redgear
author_rank: Frequent Contributor
timestamp: December 04, 2019, 07:08:05 am
content: Quote from: tautech on December 04, 2019, 06:52:01 amHereis the translated version.They have recommended to use a 4 layer board. Will it be possible to do it in a 2 layer board? I feel like it can't be done in a 2 layer board if I were to use the recommended trace width. Also, they recommend to use 8 mils or 10 mils as default trace width but if I use that, the traces won't connect to the ic pins.

author: Rerouter
author_rank: Super Contributor
timestamp: December 04, 2019, 07:34:17 am
content: It can be done on 2, you just need to avoid crossings under switching nodes or the differential pairs, It makes it harder, but it is still possible. as for the trace widths, it is a recommendation, but you can neck-down the traces where they enter the IC if you wishthere reference layout looks very weird, they have there switching node taking up half of the PCB.Working on the top layer, its quite possible to lay it all out, just a pain in terms of loop side, seeing as 8-27 need to be escaped

author: redgear
author_rank: Frequent Contributor
timestamp: December 04, 2019, 08:09:18 am
content: Quote from: Rerouter on December 04, 2019, 07:34:17 amok, Let me try. idk if i will be able to.Thanks.Working on the top layer, its quite possible to lay it all out, just a pain in terms of loop side, seeing as 8-27 need to be escapedYou mean all components on the top layer?

author: Rerouter
author_rank: Super Contributor
timestamp: December 04, 2019, 08:59:49 am
content: well they say that SW and VOUT should not change layer, which kinda nudges towards also having the BAT caps on the top side to, playing with it now, but very possible, main thing is I should shift it back towards the center, but I am thinking you can route a lot of the VOUT/VBUS traces under the plugs, and place the mosfets for each plug practically next to the USB ports.I have done the caps for the inductor a little weird, but this was to keep the smallest loop area I could find for this inductor, I would be feeding in the battery connection to both capacitor groups seperatly,edit: by loop area, you can treat it like drawing a line that shows where the current goes along the power trace, vs how it has to travel on the ground plane to complete that loop, anywhere it deviates from being directly next to or under that power trace is a possible EMI noise source for switchmodes, or a potential antenna for general signal traces (e.g. your KEY pin)

author: thinkfat
author_rank: Unknown
timestamp: December 04, 2019, 10:26:17 am
content: Quote from: Rerouter on December 04, 2019, 07:34:17 amYeah, having a large switching node is not a good idea, specifically for EMI. That thing radiates like crazy. The larger it gets, the more possible modes it has for forming resonances while you pump pulses of energy into it that are rich of harmonics.

author: thinkfat
author_rank: Unknown
timestamp: December 04, 2019, 10:46:55 am
content: Quote from: redgear on December 04, 2019, 07:08:05 amReading the layout recommendations made me smile a bit, they basically reiterate what I've already mentionedWill it be possible to use only two layers - well, you'll likely get all the traces connected, but as I see it, the question is more if you'll be able to get the thermal design right. Even though they claim 95% of efficiency, let's be conservative and only assume, like, 85% or so, which means at full tilt doing 22 watts, you'll need to get rid of about 3 watts of heat through a tiny 6x6mm chip. The center pad is even less than that, hence their recommendation to put 36 vias into the center pad. But that buys you nothing, if those vias are not connected to a huge amount of copper. With a 4 layer board, you can dedicate a full layer to being a ground plane and they still say you need to keep a considerable window under the chip as an unbroken copper area.The next aspect a 4 layer board helps with is that you have high-impedance sense wires for voltage and current sensing running around, those will very easily pick up dirt from the switching node. Putting them on the bottom layer and using ground the ground planes as a shield will definitely help here.

author: redgear
author_rank: Frequent Contributor
timestamp: December 04, 2019, 11:06:54 am
content: Quote from: Rerouter on December 04, 2019, 08:59:49 amThis looks great! Do you have the SW1 on the right side? I'm not able to find room for the IC if I have it there.

author: Rerouter
author_rank: Super Contributor
timestamp: December 04, 2019, 12:21:37 pm
content: Can do, just had to shift around the IC a little, whats mainly left is the mosfets and sense lines, but with some fiddling there silly guide can be followed for a 2 layer fitout

author: thinkfat
author_rank: Unknown
timestamp: December 04, 2019, 12:35:04 pm
content: Another hint: They want the battery terminals as far apart as possible, to avoid shorting them out during assembly or when a wire comes loose. That means two things: follow that advice, or use a battery with built-in protection and drop the protection circuit from your design.

author: Rerouter
author_rank: Super Contributor
timestamp: December 04, 2019, 12:49:45 pm
content: And this gets in to why the selection tools in PCB editors are such a nice thing, drag from left selects only what you fully overlap, drag from right selects everything the area overlaps,them "m" to move and "r" to rotate, or "f" to flip the entire group in one go, means shuffling around chunks is not as much of an issue. "backspace" removes only the segment under your mouse, "delete" removes that segment and any connected segments back to a pin or a junction,and finally you can edit traces by starting routing on an existing segment, if you end the trace overlapping a segment on the same trace it can auto-delete the old trace and replace it with your new one (button on the left side turns this on or off)

author: redgear
author_rank: Frequent Contributor
timestamp: December 05, 2019, 07:31:05 am
content: Quote from: thinkfat on December 04, 2019, 10:46:55 amSince this is my first board, I am afraid 4 layers will make it more complex.Quote from: Rerouter on December 04, 2019, 12:21:37 pmI am trying to duplicate what you did, How do you do those beefy traces? Do you draw polygons on the copper layer?I am not able to pour copper on the board. If i try fill it with GND I get only hatched lines and not solid green layers like yours.

author: Rerouter
author_rank: Super Contributor
timestamp: December 05, 2019, 08:28:06 am
content: some copper pours, but the BAT trace is a 2mm trace, trace settings are under file/board setupThe pours I have attached my usual settings,to change how the pour appears, there is a green button on the left hand toolbar, it and the 2 beneath it control what a copper pour looks like, as its easier to lay things out with it hidden sometimes,edit: you can also change your trace width and grid while routing by right clicking

author: redgear
author_rank: Frequent Contributor
timestamp: December 05, 2019, 09:57:45 am
content: Quote from: Rerouter on December 05, 2019, 08:28:06 amThank You!QuoteI tried toggling it but no change.

author: Rerouter
author_rank: Super Contributor
timestamp: December 05, 2019, 10:09:51 am
content: left hand side, click the green filled in copper pour option,right hand side, click essentially the same icon, go to the pcb and click, will ask you to select a layer, a net and edit any settings, once pressing OKContinue drawing the shape of the pour (would recommend a course grid for this to make things easier), then either get to clicking on the starting point, or right click and select "close zone outline", once done it should auto-fill the pour.

author: redgear
author_rank: Frequent Contributor
timestamp: December 05, 2019, 10:21:46 am
content: Quote from: Rerouter on December 05, 2019, 10:09:51 amThank You!I followed exactly the same steps but, its still hatched.

author: Rerouter
author_rank: Super Contributor
timestamp: December 05, 2019, 10:29:21 am
content: And the files I sent you, does that have copper pours showing up correctly?

author: redgear
author_rank: Frequent Contributor
timestamp: December 05, 2019, 10:35:23 am
content: Quote from: Rerouter on December 05, 2019, 10:29:21 amYes! They show up correctly. I tried moving the TH components and refilling, it works too.

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: December 05, 2019, 11:22:36 am
content: Quote from: Rerouter on December 05, 2019, 08:28:06 amI rarely do this unless I need to find some segment that got lost and is interfering with routing some other trace. For 2 layer layouts, usually I just set the transparency of my layers appropriately so that I can see enough of what's happening on the other side.(Thanks for the left-drag vs. right drag thing. I never knew that.)QuoteYou can also use W/w and N/n once you have set trace widths, or q to enter trace/space numerically. It's a major lost opportunity that the "List hotkeys..." window is modal.Quote from: redgear on December 05, 2019, 10:35:23 amIf it's hatched, it's not connected to the net. If you're sure there are pads etc. centered in the polygon, open the polygon editor and make sure it's on the correct net.

author: redgear
author_rank: Frequent Contributor
timestamp: December 06, 2019, 09:36:18 am
content: @Rerouter thanks a lot for taking the time to design the layout.I have few questions:1) The design recommendation says the BAT+ and BAT- should be on the opposite ends of the PCB. You have them placed very close to each other.Can I move the BAT- pad to the right side of the PCB and flip the Batter Protection circuit(they recommend the battery protection to be close to the BAT- to reduce copper impedance from BAT- to GND) to the bottom side? Can they be on different layers? Will punching 12 vias be enough? Do the traces connecting the R1 to BAT+ be fat?2) Can I route all differential pairs(except j5), mosfet current sensing and low current traces to the back side? If it's ok to do that, I can place the mosfets near the usb ports.3) What should be the width of traces that connect to VOUT of mosfets?4) They recommend atleast 12 vias to be punched on VOUT, SW, B+, B-. Do vias on VOUT (A,B,C) connecting to mosfets count? Can I use free space on the board to punch vias for GND?5) Do I need copper pour on top of the BAT+ and BAT- pads, shouldn't pads themselves be enough?ThanksEDIT: Added the layout by Rerouter

author: thinkfat
author_rank: Unknown
timestamp: December 06, 2019, 10:31:05 am
content: Quote from: redgear on December 06, 2019, 09:36:18 amThat is a safety measure if you plan to use bare Li-Ion or Li-Po battery cells without built-in protection circuit. Imagine the spark if the wires touch each other while you solder them to the board. Imagine you short the battery terminals with a solder blob.What batteries were you planning to use, 18650 cells? If you use cells with built-in protection, you can put the BAT+/- where you want and you can also drop the protection circuit completely. If you plan to use bare cells, follow their advice for your own safety and of those who will use the device.Quote from: redgear on December 06, 2019, 09:36:18 amI'd keep the differential pairs where they are and only drop the mosfet current sensing and gate traces to the back side.Quote from: redgear on December 06, 2019, 09:36:18 amThat depends on what you want each individual port to source. The main VOUT trace should be at least 2mm (80mil) for your 4A maximum current. The traces from there to each mosfet could be weaker, depends on what the maximum current there will be. BTW, KiCAD has a built-in PCB calculator that can do trace width calculations.Quote from: redgear on December 06, 2019, 09:36:18 amThat depends on how much current will flow through these vias. My own rule-of-thumb says 500mA is the maximum allowance for a single via. If you want to push 1A, put two.

author: thinkfat
author_rank: Unknown
timestamp: December 06, 2019, 10:39:36 am
content: BTW, how do you intend to charge the battery?

author: redgear
author_rank: Frequent Contributor
timestamp: December 06, 2019, 10:56:49 am
content: Quote from: thinkfat on December 06, 2019, 10:31:05 amYes, I am planning to use 18650s. And they don't come with built-in protection. Can I flip the Battery Protection circuit(they recommend the battery protection to be close to the BAT- to reduce copper impedance from BAT- to GND) to the bottom side? Can they be on different layers? Will punching 12 vias be enough? Do the traces connecting the R1 to BAT+ need to be >80mils?QuoteOk, but I still have to place 4 mosfets on the top layer, I got no space for them. Can I flip the mosfets to the bottom layer?QuoteThe combined max output current will 4A either through a single port(except micro USB) or all outputs combined. Low Voltage Direct charge mode is at 5V. From their datasheet:QuoteThe max charging current will be 5A. This is what their datasheet says, but I cannot understand it. Idk what do they mean by charge current in input current and battery current.QuoteQuoteOk, Say I need 6 vias on vout, placing vias any net that connects to vout is fine,right?QuoteThe USB connectors are bi-directional, acts as a source when sink is detected or acts as a sink when source is connected.Thanks

author: Rerouter
author_rank: Super Contributor
timestamp: December 06, 2019, 11:54:55 am
content: you can put the mosfets wherever you like, they don't even need to be next to the port, they can be closer to the micro,As per Vias, just throw down as many as your compfortable with, the 500mA per via is not a bad rule of thumb,As per exactly how to run the traces to the ports, get creative, same with the battery connection terminals, I just followed that as the files you gave me had them close to each other,

author: redgear
author_rank: Frequent Contributor
timestamp: December 10, 2019, 07:50:15 am
content: UPDATE:I have managed to route most of the components. I have also followed the recommendations given by the chip manufacturer. The only things left to route now are the GATE pads and VBUS pads from mosfets to ICs. I am not able to figure out a way to route it.I am attaching the image.ThanksEDIT:Managed to connect VCC network. Updating the image.

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: December 10, 2019, 07:19:25 pm
content: Not intended to be an exhaustive review, but I see some variations on a couple of themes you might want to fix:1. Use wide traces to carry appreciable current.The #5 pins on the USB A ports need to carry current. Widen those traces up. Or better yet, move your vias closer to the ground pin. The shield pins don't need nearly as many vias as you are giving them, as they will not carry appreciable current. (Nor do you want them to. Should a shield pin/foot come loose due to wear and tear, it will play merry hell with your device.)Likewise, the source leads on your MOSFETs are carrying the entire output current. Use a wide enough trace to handle it. The same goes for the VBUS caps. (VBUSB is good. Do this. But maybe turn VBUSB the other way to reduce distance and inductance to the absolute minimum.)The runt traces to the vias on the VOUT caps look bad and increase EMI slightly. You can put the vias in the fill using the via tool instead of the route tool.2. Low-current, low-speed traces can be routed together to reduce the fracturing of the ground plane. Try to keep the ground plane open and solid.On port C, pins 3 and 9 (counting from the left) appear to be also quite low-speed enough to travel together. Route them on top to somewhere near pin 3, just to the left of the VBUSC trace, then drop them and take them over to the IC. Maybe you could even keep them on the top layer, or sink them all and bring its MOSFET to the top side.The KEY nets are non-critical. They appear to be just dc logic input nets. You can route their traces closer together to keep the ground plane consolidated and gain more room to route other things. You can also take some of the vias off of the switch since they too will be carrying no appreciable current.Don't interrupt the ground plane between the northmost VOUT-GND cap and the southerly ones.The vias on DA2_(N|P) are poorly placed. Run the traces on the top layer alongside the DA1_(N|P) traces until you get to the connector, then sink them.Consider bringing the VBUS cap for port A1 to the top. You can squeeze the KEY trace between the pads.

author: redgear
author_rank: Frequent Contributor
timestamp: December 11, 2019, 06:03:11 am
content: Quote from: jhpadjustable on December 10, 2019, 07:19:25 pmThe #5 pins are GND pins on USB A. Do I need to beef up the GND traces connecting them? I am removing the vias now.QuoteI am using a 2mm(78.74mils) trace for the source leads on MOSFETs, aren't they enough? I removed the traces on VOUT caps, instead I used a zone fill and punched vias directly on them. Do I need to follow the same for GND vias in all caps?QuoteBut their recommendation say to punch vias on free space to strengthen the connection between the layers and to help in heat dissipation. By routing together, Do you mean reducing the clearance between adjacent traces and routing them as close as possible?QuoteOk, will try this.QuoteOk.QuoteCan you name the caps?QuoteOk. Let me try.Thanks.@Rerouter Where you able to download the zip that I sent you over PM?

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: December 11, 2019, 07:34:07 am
content: Quote from: redgear on December 11, 2019, 06:03:11 amBeefier and shorter. They're the return for the current flowing through the device and need to be at least as wide as the traces on the #1 pins. What you did for the #6 shield pins, you should be doing for the #5 pins instead. The shield pins are a much lesser concern.QuoteLooking at the MOSFET connected to VBUSA1 at the left, I see the drain trace is wide, which is good. The source trace connecting the two then heading east, which I presume is the big VOUTP bus, is still tiny.QuoteIt would be wise to connect all the power caps solidly to ground, as you have done for the four BAT-GND caps by the inductor.QuoteVias will help thermally just by being some metal, but would only help electrically if there's a ground fill on each layer to connect to, perhaps one that I'm not seeing because you turned it off for clarity for posting? (Aside, did you try setting the transparency of the copper layers to about 60%? I find that really helps me get a better idea of what's happening while laying out.)Not necessarily reducing clearance, in the design rule sense, but yes, I suggest you run them closer together to keep the ground fill "traces" fat.QuoteC9,C7,C11, I think, where the concern is that trace looping nearly to the right edge of the board and dividing the ground plane between as it comes back toward the chip and passes between two caps. The top silk got a bit muddy in the JPEG compression, and to be completely honest I didn't see it at first, sorry.

author: redgear
author_rank: Frequent Contributor
timestamp: December 11, 2019, 10:44:37 am
content: Quote from: jhpadjustable on December 11, 2019, 07:34:07 amOk.QuoteVBUSA1 is connected to the source of Q4. The connection on drain is VOUTA1. They are connected to the sense resistors.QuoteThey still have traces connecting the vias to GND pad.QuoteYes, I have GND fill on the entire B.cu layer. I have made the layer transparent now.QuoteOkQuoteNo prob. I don't get you. What do you mean by don't interrupt the ground plane between caps? Should I not run any traces under them on?Thanks

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: December 11, 2019, 07:29:53 pm
content: Quote from: redgear on December 11, 2019, 10:44:37 amOkay, I was reading the board backwards, and/or these are weird MOSFETs with the source on the one-pin side where the drain customarily lives. Disregard.QuoteProbably fine, as long as they're wide.QuoteI meant F.Cu, the red layer. If so, you're probably okay but it's a bit hard to visualize on the images.QuoteLight blue here:Even if there's a ground fill on F.Cu that I'm not seeing on the image, the vias just north of the blue-marked area wouldn't be connected to much in your screencap. I've sketched an alternate route for the port C pins to the chip which keeps the B.Cu fill more intact. You could bump C7 and friends a bit further down to make room if you like.Cheers!

author: redgear
author_rank: Frequent Contributor
timestamp: December 14, 2019, 05:07:59 am
content: Do I need to connect both VBUSC or is it enough if I just run power through one? I couldn't find a way to connect the VOUT and GATE nets ona 2-layer board. So, I switched to a 4 layer design.