how fast do frequency counters go? - Page 1
Forum section: electronics / beginners

author: Capernicus
author_rank: Frequent Contributor
timestamp: September 29, 2021, 09:41:34 am
content: I'm just about to get my ring oscillator going, and I thought a good 1st project before my computer would be a frequency counter!I was wondering if ppl here have one of these things, and how fast do they usually go? I saw on a short search on the internet, I saw them up to 3ghz, and they are pretty cheap, you can get them for $30 if u hunt around more. (for a pretty cut down lcd display on a little board.) - which is what im planning on doing, I wont be resetting every exact second, im just going to let the counter whizz and wrap itself continuously.Good enough.

author: theHWcave
author_rank: Regular Contributor
timestamp: September 29, 2021, 02:01:49 pm
content: Not sure what your are after.How fast = how high? That depends on what you need to measure and at what resolution / accuracyFrequency counters do not need to be resetAre you instead looking for an event counter?

author: Capernicus
author_rank: Frequent Contributor
timestamp: September 29, 2021, 02:34:31 pm
content: thanks for reply.I don't even really know what frequency counters are even used for specifically in the industry. I just need to know how fast my ring-osc is, for my count of I/O feedbacks, and it needn't be precise at all. Just ball-park is fine.Whats the dif between a freq-counter and an event-counter?My goal is a 21x21x21 adder pipelined asic, really going to town with this, show ppl what handmade computers actually can be instead of just ancient replicas of long gone past of slowdown.But um... maybe this is a bit of a pointless post sorry... I should just get on with my work. hehe

author: radiolistener
author_rank: Super Contributor
timestamp: September 29, 2021, 02:56:30 pm
content: Classic counters are too slow.As I remember, with classic counters there is about 400-450 MHz limit on FPGA EP4CE15F23C8N (speed grade C8).The problem here is a slow carry from a higher bits, it requires too much time to carry overflow over all bits.But there is a workaround, you can use pipelined counter to break wide counter into small parts.Here is example:https://github.com/PetteriAimonen/dso-quad-logic/blob/fpga_support/fpga/pipelined_counter.vhdlWith pipelined counter I got about 1 GHz limit with 1 Hz resolution on FPGA EP4CE15F23C8N (speed grade C8). I got the best result with 36 bits break into 6 parts (6x6). That's pretty cool, because this FPGA has a usual limit for a logic circuits about 450 MHz.Of course you can also use high speed pre-scaller (divider) to reduce input frequency, but it will also reduce resolution of the counter. But since usual frequency counter doesn't have stable enough frequency standard as a reference, there is no sense to keep 1 Hz resolution for GHz range frequency and you can add pre-scaller.Just for information, 1 Hz resolution at 1 GHz needs at least 0.001 ppm reference clock. While usual TCXO provide just 0.1 ppm. So there is no needs for 1 Hz resolution and you can add divider on the input as a pre-scaller.

author: Capernicus
author_rank: Frequent Contributor
timestamp: September 29, 2021, 03:23:28 pm
content: Pipelining is excellent, and easy to do! (Take out all the years experience it takes to get to that point of course...) gratz on the 1 gigahert!You carry to the msb, not from it, even tho I'm guessing that was just a typo.Down scaling it, is for when you want to count Really high ones I bet!!!0.001ppm - (parts per minute?) - thats 60hz right? what is a TCXO?If you make all the oscillators yourself required with ring oscillators u dont even need any of this necessarily right?Im planning on having my display output a separate clock from the internals, and just display at 60hz, doesnt matter if its out of synch as long as it doesnt stuff up.Its not going to be like a quartz watch or anything what im making, its going to be a little off, but hopefully a good (and high freq) one.

author: radiolistener
author_rank: Super Contributor
timestamp: September 29, 2021, 03:33:04 pm
content: Quote from: Capernicus on September 29, 2021, 03:23:28 pmNo. ppm is a Parts Per Million.0.001 ppm means that reference clock error is less than 0.000000001.If your reference clock is 10 MHz then it's error should be less than 0.01 Hz to comply with 0.001 ppm.But the best TCXO has about 0.1 ppm. For 10 MHz it will be 1 Hz error.This is why there is no sense to keep 1 Hz resolution when measure GHz frequency. Anyway your reference clock error cannot provide so high resolution.

author: Capernicus
author_rank: Frequent Contributor
timestamp: September 29, 2021, 03:46:10 pm
content: haha woops thanks.I've got something brewing, It may not involve a reference clock, I'm thinking about detecting positive edges instead, and make the counter logic run at this speed, I do have a Hz divisor planned, this is to get something related to a propagation delay fix, like pipelining. I'm going to slow the clock down so I can get a feedback loop for a pack of registers. normally this isn't possible with fast input oscillations, it wont be able to advance the state before the next pulse.But if u slow the clock down enough. then it might be able to. And I lose a good 30 or so binary positions resolution, but I dont mind, I just need the MSB's for this.