Voltage mode Controll question- Buck Regulator - Page 1
Forum section: electronics / projects

author: chimera_786
author_rank: Regular Contributor
timestamp: July 07, 2013, 05:19:23 am
content: Hello!I'm almost done designing a control scheme for a voltage mode controlled buck regulator.Input Voltage = 12V and Vo = 5 @ 2A. Fs = 250Khz. CCM mode and assume steady input voltageYes, there are controllers that do all of this for the user but where the fun in that?Assuming who ever is going to answer this will have some knowledge on BUCK VMCs, I have one question:What should be the amplitude of the Vramp. This is the ramp which is fed in the PMW comparator along with the Vcontrol from the error amp.The reason why this question is important (please ignore Voltage Feed Forward) is: The Vramp does affect the gain of the power stage (which is the PWM gain, the switch gain and the LC filter gain).As a back up, I have come to the conclusion that just pick a reasonable value for the max amplitude of the Vramp (around 2ish volts) and it should be enough to yield a min and max duty cycle.But, the designer in me is not satisfied with this.I want/need to know how do I determine the optimum value for the amplitude of the ramp voltage. Too much amplitude and it'll affect the gain of the power stage, too little and I risk oscillatory response.Any suggestions?

author: Paul Price
author_rank: Super Contributor
timestamp: July 07, 2013, 11:26:14 am
content: Don't quit your day job jet.Post a schematic of the power supply circuit and I think I can find that there is probably an easier, more effective, more reliable, let us say,betterway to do whatcha wanna do.

author: chimera_786
author_rank: Regular Contributor
timestamp: July 07, 2013, 04:02:25 pm
content: too late! Ive already cleared my deskThere is no schematic as I'm still working the control block for the design. I have simulations of the power stage but those don't directly relate to the Vramp question I am faced with. I can post those here if you think they would helpWhat amplitude should the Vramp be: an arbirtary one (with in reason) or a calculated one (directly or in directly)

author: Paul Price
author_rank: Super Contributor
timestamp: July 07, 2013, 05:34:53 pm
content: Controlling the SMPS in the way you aspire, seems to me like controlling a race horse with a sledgehammer.

author: chimera_786
author_rank: Regular Contributor
timestamp: July 07, 2013, 07:47:03 pm
content: Useless analogies aside, it doesn't seem like your willing to offer any help.Now, if you don't want to share your guidance and experience with me (and to any other member who might stumble across this thread), then why are you criticizing my approach with out offering any support.By posting a question on this forum, OP is asking for help and suggestions, not derby oriented points. Seems to me, the idea of shared/common knowledge is lost upon you.

author: lgbeno
author_rank: Frequent Contributor
timestamp: July 07, 2013, 09:23:30 pm
content: Quote from: chimera_786 on July 07, 2013, 07:47:03 pmAgree completely, I see a lot of this sort of insincere commentary on this forum and I think that it discourages people from posting ideas of designs and asking for help.I think that you are on the right track. Not everything about engineering needs to be scientifically calculated, there's always a gut feel that sends you in the right direction and then you test the crap out of it to validate your assumptions, tweaking along the way.I'm thinking that vramp is really going to dictate the resolution which you can reliably control you pwm so I think that it's better for it to be large.You mentioned gain in your power stage affected by vramp, do you mean that less vramp equates to more gain and greater vramp equates to less gain? Extreme gain(small vramp)=an unstable system...The question is what is the operating voltage of your opamps that you are implementing this control with. What does your feedback network look like? Details of your comparator and gate drives would be helpful too. I think this is was others are asking about.Don't be afraid to share more details like a simulation file or some of your sim results as they are right now.I don't really care about "the best way" to do something, it's all about learning something and trying stuff along the way. "Best" is a matter of perspective.Btw, in the new version of ViaDesigner there is a voltage mode buck regulator model written in Vhdl-AMS. This would also be a great project to share at community.viadesigner.com!

author: chimera_786
author_rank: Regular Contributor
timestamp: July 07, 2013, 11:07:41 pm
content: I will share designs once I have it consolidated into a working simulation. Right now, its scattered sims here and there.Regarding the whole Vramp and Gain business: From a buck converters power stage, the effective gain is what you deduced; small Vramp is huge power stage gain and large Vramp will yield a smaller power stage gain.When I commented "too small of a Vramp and I will experience an oscillatory response", I was referring to the two extremes which the amplitude of Vramp can experience. In this case, the lowest extreme could be an order of a few 100mV pk -pk. This amount of ramp would indeed yield an oscillatory response at low/DC frequencies, upsetting the DC operating point of the buck converter.My op amp is powered from a 5V source, single ended. Im guessing that a Vramp value of 2.5V should be sufficient. I'm drawing this number not from an analytical approach. Rather, this number is coming from the various controller datasheets Ive seen (and used).I will post back with a working discrete buck converter small signal and large signal analysis (transients and line variations).

author: planet12
author_rank: Regular Contributor
timestamp: July 08, 2013, 01:07:28 am
content: Your main constraints making Vramp large are going to be your 5V power supply in relation to how close your ramp generator can get to the rails, and what the input range of the comparator you're using to compare the ramp and the error signal is.At the small Vramp end, noise - keeping in mind a switching regulator is a very noisy environment - will probably be the limiting factor; if you start getting down so that the noise is a decent proportion of the ramp signal, you're going to get noise-induced jitter on the PWM output - and as much of the noise is going to be generated at various harmonics of your switching frequency, you may end up with strange control loop problems.

author: Paul Price
author_rank: Super Contributor
timestamp: July 08, 2013, 01:11:45 am
content: I misunderstood your question,I read your description too quickly and thought you were going to control a SMPS regulator by inserting some control circuit at the Vramp feedback point, which seemed to me, well, rather silly.If I try to guess what is going on in your circuit, the amplitude of the Vramp is compared to the error difference-amp output and the point at which they match determines the termination of the on-time of the duty cycle.Having a large Vramp amplitude requires making sure the amplitude doesn't exceed the input operational range of the comparator and the output max and min operating voltage of the error amp. Having a small Vramp peak amplitude decreases the slew-rate response time requirement of of the error amp and this factor would certainly be important to get the VMC to work well at very high switching frequencies(500KHz to 5 mHz).If we decide that the point at which the error amp and Vramp meet in amplitude determines the duty cycle in a fixed frequency VMC, then yoy should consider that decreasing Vramp peak amplitude increases the control loop's sensitivity to noise and a higher Vramp increases slew-rate requirements of the error amp, but so why not just increase the Vramp amplitude to climb to reach some max peak voltage that is still within the operating voltage capability of the error amp and comparator at the operating freq. of interest, while considering the voltage interface complexity of introducing perhaps some needed feed-forward compensation?.I don't quite get the idea of the power stage gain since it needs to operate as a switch, and if your circuit is just a simple buck converter, then you can consider the whole buck converter, and especially the output stage to just to be considered as an on-off digital switch that pumps current into a inductor. The most important consideration for the output circuit is not just so well characterized or defined by "gain" but, instead you must think in the concept domain of creating an ideal switch, where on resistance, saturation voltage, on/off switching speed and the problem of how to achieve the biasing for the on and off states to optimize for fast switching and lowest on voltage drop to achieve the lowest power loss.In the face of the mountain of complication any circuit offers us to imagine or work with and asked to question and solve some design specifics you don't offer much to work with. Is it a very simplest buck converter, or maybe some exotic Kuk type buck converter, you must have made a decision on your frequency of operation, whether your circuit is fixed frequency or not, transient response required, required power usage or wastage, current limiting, overload protection, input drop-out voltage, regulation requirements, input overvoltage protection, undervoltage startup protection, shutdown capability, load-dump protection, physical size considerations and limitations, cost and availability of parts and assembly, residual noise on the output, turn-on overshoot behavior, short-circuit tolerance, operating temperature range, slow-startup requirements, EMI requirements, etc.Ok, this list is too long, but maybe some of these things may be somehow effected by Vramp amplitude.For instance, I can easily construct a well functioning VMC type buck converter that does not use a Vramp at all, and has no fixed frequency of operation or one whose operation is completely controlled by a MCU.You are offering a very complex question and without even a block diagram, where a complete circuit would be most appropriate and needed to intelligently define what you are actually questioning about. Is this respectful or considerate to those engineers or hobbyists or psychics who might want to grant your wish for an answer?

author: chimera_786
author_rank: Regular Contributor
timestamp: July 08, 2013, 03:38:48 am
content: Hmmm. So my initial hunch was correct. The ramp is just arbitrarily sized to deliver noise immunity and ease of translation to PWM, resulting from the e.amp.As for Paul's concerns:1- Yes. I am observant of the CMVR, DMVR, Vcc max etc (the whole lot) of the op amp and the comp.2- Power stage gain. I feel your getting stuck on words here; Lets just call it the over all gain of the plant (You seem like the person who'd want overly-exact definitions). As now that its clear what gain I am referring to, the peak amplitude of the ramp DOES begin to matter.3- The ideal switch. Ah yes, eventually, the switch and its associated parameters and the required gate drive circuity will need to be identified..but in due time.4- The laundry list of things you mentioned: load steps, SC current, UVLOs, Pulse skipping, forced CCM, risidual noise and what have you.. it seemingly clear that if I wanted to have these advanced capabilities, I would just do what I have been doing: pick up a suited controller IC (LT, TI, MICREL, ONSEMI..the list goes on) and be done with it (with some reasonable freq. response analysis).5- You really do give things a quick glance. I did post requirements (albeit a small lot) but I don't have any requirements that I need to meet. This is just for a self brewed discrete design. NO MIL SPECS, NO ULs, NO FCCs.You know..I hope you have realized that your not the only one with power supply design experience in a real world application.Although I feel that your experience would have been useful, your words seem tainted with some arrogance. I can only imagine working with you on a team.The whole idea of asking for a simple question regarding a ramp amplitude stemmed out because there wasn't much info on the web (minus the IEEE papers..they always have way to graphs and derivations that would leave Nicolaus Copernicus scratching his head)But what did this thread end up with: me proving that your not as helpful as you think you are. Please redefine your strategy to help others.At any rate, I do appreciate your efforts. Maybe next time.

author: lgbeno
author_rank: Frequent Contributor
timestamp: July 08, 2013, 04:14:19 am
content: Nuf said, you're on the right track. Can't wait to see those simulations.So I have this idea, it's called the jump to conclusions mat. You see there's this mat with a lot of different conclusions on it and you... Jump to conclusions

author: Paul Price
author_rank: Super Contributor
timestamp: July 08, 2013, 12:21:08 pm
content: You're welcome!