Different VCCO sources for different banks on the same FPGA? - Page 1
Forum section: electronics / general

author: Pack34
author_rank: Frequent Contributor
timestamp: February 20, 2018, 05:16:34 am
content: I'm working with a Spartan6 that needs to talk to a sensor (SPI and LVDS) that runs at 1.8V and a microcontroller (SPI and I2C) that runs at 3v3.VCCO is rated for 1.2V to 3.45V. Would it be possible to power the banks individually so that I won't need level shifting? Or is VCCO shorted internally?

author: hamster_nz
author_rank: Super Contributor
timestamp: February 20, 2018, 05:33:31 am
content: yes, you can run different banks at different voltages.See around page 39 ofhttps://www.xilinx.com/support/documentation/user_guides/ug381.pdf

author: asmi
author_rank: Super Contributor
timestamp: February 20, 2018, 06:13:26 pm
content: Yes you can, infact this is exactly why IO pins are split into banks. Just be careful with this as some banks contain dual-use pins (like SPI/BPI Flash data pins), so if you want to power this bank with voltage that is different from what flash IC uses, you will need to have voltage translators (and that might limit the speed at which bitstream is read so configuration will take more time). I personally always leave these banks at 3.3V to avoid any issues, and use other banks when I need different voltage.Classic example of when different Vccio voltage is used - connecting DDR2/3/3L SDRAM to FPGA, as they need 1.8/1.5/1.35 V respectively.

author: Bassman59
author_rank: Super Contributor
timestamp: February 20, 2018, 10:04:21 pm
content: Quote from: Pack34 on February 20, 2018, 05:16:34 amThe VCCOs for each bank are separate. They are like that so you can do exactly what you propose.Make sure you set your IOSTANDARD appropriately for each pin in your UCF.

author: Scrts
author_rank: Frequent Contributor
timestamp: February 21, 2018, 04:26:25 am
content: And also be sure to use an oscillator that is compatible to the bank voltage. I once connected 3.3V oscillator to 1.5V bank and FPGA was working, but running extremely hot.

author: Pack34
author_rank: Frequent Contributor
timestamp: February 24, 2018, 05:23:45 pm
content: Thanks guys! I thought so.This is the first one of these split designs I've done. On two banks I'm talking to an ARM chip at 3v3. Then the SPI control signals to the sensor are 1.8V, then the last bank has subLVDS that I still have to level shift to work properly. Luckily a simple LVDS crosspoint switch has a sensitive enough input that it can detect the lower voltage LVDS and can be configured to be a pass-through so the output is essentially just a level shifted version of the input.

author: asmi
author_rank: Super Contributor
timestamp: February 24, 2018, 07:50:45 pm
content: Quote from: Scrts on February 21, 2018, 04:26:25 amThere is one exception to this rule for Xilinx chips - you can have LVDS input on any bank regardless of it's Vccio. The classic example of that is feeding LDVS clock to the bank that communicates with DDR. Infact this is the recommended way to provide clocks for MIG according to the user guide, and - I suspect - it the reason why Xilinx made such exception. For relatively low speeds you can get away with feeding in clock from just about anywhere, but for higher speed you will start getting timing issues.Here is a page from DS181 (see Note 1):

author: langwadt
author_rank: Super Contributor
timestamp: February 24, 2018, 08:15:08 pm
content: Quote from: asmi on February 24, 2018, 07:50:45 pmLVDS input is basically a comparator so it'll work at "any" voltage, with the caveat that the on-chip termination is only characterized with 2.5VThere's a trap if you think you can sneak some LVDS outputs into a bank powered with 3.3V, if the Vcco goes above ~2.9V the LVDS output transistors turn off to protect them from over voltage

author: Scrts
author_rank: Frequent Contributor
timestamp: February 24, 2018, 08:40:01 pm
content: Quote from: langwadt on February 24, 2018, 08:15:08 pmThis wasn't the case on Altera Cyclone II. Banks powered 3.3V were easily tricked in the software and worked as LVDS pairs. I think Cyclone III allowed the same.

author: langwadt
author_rank: Super Contributor
timestamp: February 24, 2018, 08:45:54 pm
content: Quote from: Scrts on February 24, 2018, 08:40:01 pmit may only be the latest families that use faster smaller transistors, this was on a Zynq