Track lengths made long on purpose. - Page 1
Forum section: electronics / general

author: G7PSK
author_rank: Super Contributor
timestamp: February 21, 2012, 06:26:17 pm
content: Not sure under what heading this should be, but having watched Dave's video on the power supply and the lengths he went to make tracks as short as possible and the import that he put to it, I was surprised today when looking at the motherboard for a Fujitsu Siemens laptop that considerable pains had been gone to to increase the length of tracks going to the RAM module sockets with the traces zig zaged up to twenty times in loops on many of the pins. The question is why, is it some form of deliberate delay on signals by increasing the length or what it is not something that I have seen before other than as on-board antenna, but this was obviously not for that purpose.

author: harnon
author_rank: Regular Contributor
timestamp: February 21, 2012, 06:28:41 pm
content: Do they do this to match the length of some traces?EDIT: i.e.http://www.pcb1001.com/2008/09/trace-length-and-length-matching.html

author: Balaur
author_rank: Unknown
timestamp: February 21, 2012, 06:34:55 pm
content: The primary reason is delay matching.The signals from the same group (i.e data buses and so on) are usually sampled by the receiving device at the same instant. There are some timing requirements to be met (set-up and hold): basically, the signals should be stable during a specific time interval.

author: caffeinatedbard
author_rank: Regular Contributor
timestamp: February 21, 2012, 06:41:43 pm
content: Indeed. For an easy example, look at the traces on the Beagleboard used for tranferring data from the TI OMAP to the DVI-D interface.The gerbers are available in the manual if you don't have one.Notice too the distance between the traces; none of those parameters are by accident.In fact, some of the more advanced layout tools have wizards that aid in length matching of traces to keep the sync in spec.

author: G7PSK
author_rank: Super Contributor
timestamp: February 21, 2012, 06:47:08 pm
content: Thanks for the reply's, delay matching is what I had surmised. it would be very difficult to measure the lengths of the tracks to compare them and as some just wiggle up and down and others circle around and come back on themselves and others are connected with via's it is hard to make a visual comparison but I would hazard a guess that some of them are, It is something that I have not noticed on other boards, But the my eyes had not been opened in the same way by Dave's video's at the time. I will have to pull some more computer boards and have a look.

author: wkb
author_rank: Super Contributor
timestamp: February 21, 2012, 06:52:28 pm
content: Quote from: G7PSK on February 21, 2012, 06:47:08 pmYou wil find it is a very common technique. Also on things like DIMMs, videocards etc.

author: tesla500
author_rank: Regular Contributor
timestamp: February 21, 2012, 08:39:55 pm
content: I had to do length matching on a recent design. With the tools built into good PCB packages, it's easy and relatively quick to do the matching. Most of the time is spent arranging traces to allow space for the added accordion traces.Here's a time lapse of the layout. Length matching starts at 1:06:25.

author: G7PSK
author_rank: Super Contributor
timestamp: February 21, 2012, 08:52:26 pm
content: 38 hours, Full week for the DDR3 how long for the whole board?

author: tesla500
author_rank: Regular Contributor
timestamp: February 21, 2012, 09:48:17 pm
content: Quote from: G7PSK on February 21, 2012, 08:52:26 pmI started layout in mid December, and the board was pretty much done by the end of January. The whole board took around 100 hours.Keep in mind that that 38 hours was 100% productive time, which you never achieve in the real world. I paused recording for breaks, schematic edits and other unproductive time.

author: metalphreak
author_rank: Frequent Contributor
timestamp: February 22, 2012, 03:57:16 pm
content: They are sometimes called Serpentine traces. The new Eagle v6 has support for them on differential pair signals.