[?] Pulsed 6 channel ADC design - Page 1
Forum section: electronics / projects

author: Quintq
author_rank: Newbie
timestamp: August 09, 2024, 08:52:25 am
content: Hey all!I'm in the sketching phase of a measurement system comprised of 6x ADCs to sample pulsed waveforms, but having never designed anything of this scale before, I'm looking around for some input whether I'm on the right track (or completely out of my waters).Pulses are ~6 µs long (RF 3 GHz, diode rectified), so I settled for 12-bit ADCs running at 65 MSPS (AD9235) fed by the datasheet recommended single-ended to differential op-amp AD8138. Absolute measurements are not the design goal here, but rather something that can run close to 24/7 to give an idea about stability, changes, etc. Input levels after rectifying is typically in the order of ~150 mV. Could also consider going down to the 10-bit AD9214.The board will receive an external trigger signal which I imagine can be used to toggle the WE pin of FIFO buffers, and the Full-Flag can then be used to disable WE and start emptying the buffers. In order to limit the number of I/Os, I'm thinking a few MUXes can be used to empty the buffers 2 at a time. ADCs clock out parallel data into the FIFOs which for 6 µs @ 65 MSPS, 0.5k should be enough, but to allow some overhead and jitter, I'm considering a 2k buffer.I have some experience working with Zynq-family chips, so I'm currently looking at interfacing to a Digilent Cora Z7 to handle all the board logic. >50 available GPIOs for data and control signals, DMA or AXI to send it to the on-board processor, and eth to pass the data onwards. Is it feasible to switch the GPIO headers at such high frequency?What other suitable options are there to sample synchronized pulsed data and pass it on via eth? A goal is to make it cheaper than chaining up a few RedPitayasIn the end, I will want 22 of these complete systems...If the entire signal chain can tolerate acquisition triggers of 10 Hz, I'd be happy enough. Maximum would otherwise be 100 Hz.I've also yet to consider topics such as power supplies and noise, additional input filters, opto-couplers for external signals etc...Does this approach even sound reasonable?Sketch of the potential setup

author: moffy
author_rank: Super Contributor
timestamp: August 09, 2024, 11:31:55 am
content: If I might summarise, you are looking at collecting around 6*400, 12 bit samples over a 6us period every 0.1s, they are then dispatched by ethernet. The samples are of a rectified 3Ghz signal of about 150mV level. Are you looking for variations within each group of samples or between groups of samples or both? I ask that because if you are looking for variations between groups of samples i.e. every 0.1s, you might be able to filter the pulses and reduce the required sampling rate.

author: moffy
author_rank: Super Contributor
timestamp: August 09, 2024, 11:53:52 am
content: The LPC4370 is a reasonably low cost MCU with a built in 80MSPS, 12 bit ADC and ethernet. If you had 6 of these each plugged into an at least a 6 port ethernet hub that could do the trick, but it would require a custom PCB and coding, but the same board could be used for each channel, just assign each a different port number for transmission.

author: David Hess
author_rank: Super Contributor
timestamp: August 09, 2024, 02:25:09 pm
content: Quote from: Quintq on August 09, 2024, 08:52:25 amInstead of using the write enable on the FIFOs, many ADCs have a strobe input which can be used to start and control the conversion cycle, so much slower ADCs could be used, and the sampling would be aligned with the strobe with no jitter. FIFOs would not be required either.

author: Quintq
author_rank: Newbie
timestamp: August 12, 2024, 09:10:37 am
content: Quote from: moffy on August 09, 2024, 11:31:55 amSummary sounds about right!In the grand scheme of things everything is connected together, but each group of 6 signals belongs to an isolated system. The variations we'd like to monitor is within each group, primarily sudden drastic changes (pulse-to-pulse) and long-term slow drifts (days/weeks).There is also structure within the pulses (which in a perfect world should not change), so the 65 MSPS was merely chosen to get enough temporal resolution to discern most of those features. So far we've used aging oscilloscopes for monitoring, but with increasing hardware failure, finicky network connections, and frankly a bit overkill for the purpose, has led me down this path to look for a dedicated replacement setup (+ it sounds like a fun project).The LPC4370 looks surprisingly capable for its price (though the BGA packaging scares me a bit..). Its ADC is even a"Six single-sided input channels or one differential input channel"so while not ideal, I guess it would also be possible to rotate between which signal to sample at each trigger with only a single MCU...I'll take a closer dig through its datasheet!

author: moffy
author_rank: Super Contributor
timestamp: August 12, 2024, 09:54:37 am
content: Quote from: Quintq on August 12, 2024, 09:10:37 amFor a BGA package I would probably use the in house assembly of someone like PCBWay, get the board and assembly from the one stop. There are some performance caveats for the ADC and AFAIK the one differential input channel gives the best performance. I would definitely use one LPC4370 per pulse channel. There is a project using the LPC Link 2 board, which has an LPC4370 and is low cost that turns it into a dual channel scope and logic analyzer, open source at:https://github.com/embeddedartists/labtoolP.S. About the ADC issue I might have that confused with another processor.

author: David Hess
author_rank: Super Contributor
timestamp: August 12, 2024, 10:24:25 am
content: Quote from: Quintq on August 12, 2024, 09:10:37 amI tend to avoid such specialized parts because they are more likely to have problems with availability.