LTspice behavioral dflop unexpected results - Page 1
Forum section: electronics / projects

author: dutch66
author_rank: Contributor
timestamp: July 13, 2022, 10:38:14 pm
content: I am trying to model a mixed circuit by using behavioral models from the digital section in LTspice. When using a dflop the output is not correct. I have PRE = L and vary CLR.With CLR = H the output at ~Q (inverted Q) should be L but my output is always 5V = H independent of the state of CLR. In the specific case D and CLK are both tied to VCC = 5V. I use 5V as H and have Value set to Vhigh = 5 Trise = 6n Ref= 2.0 Rout = 1.25k. I also tried to use a 74HC74 model with the same result.I am aware that this is not the most common use of a dflop but the circuit I'm working on uses many dflops this way and seems to work fine,What am I doing wrong? Any help is greatly appreciated.

author: Benta
author_rank: Super Contributor
timestamp: July 13, 2022, 10:53:37 pm
content: 74HC74 set and reset are active low.

author: moffy
author_rank: Super Contributor
timestamp: July 13, 2022, 11:00:54 pm
content: I just ran the model with PRE high and low and got the expected outputs at Q and /Q. From my understanding this is not a model of the 74HC74, CLR is active high and PRE is active high, CLR will only clear when high.

author: dutch66
author_rank: Contributor
timestamp: July 13, 2022, 11:54:58 pm
content: I work on an old schematic and the designer used flip flops like this a lot.. The ~CLR line is connected to a active low reset signal. When I try to model this in LTspice I don't get results that conform to the data sheet or to the real behavior. I have to admit that I also don't really see the point of this.Let's assume the circuit was cleared at some point in the past. Now reset = ~CLR is active high. When a signal, these are fault conditions, hits the AND ~PRE will go high. As the CLK is tied high there will never be a clock signal but nevertheless on the real circuit this seems to work.In the model even the initial state where ~PRE = L and ~CLR = H does not work.Any ideas?

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 14, 2022, 12:29:39 am
content: Have you read what moffy said?The dflop "special function" in LTSpice is a behavioral model with its PRE and CLR inputs active high, as opposed to the 74xx74 for which they are active low. So you need to invert those signals.As to the "74HC74" model you used, I have no clue what exactly it is, but I can tell you from experience that many of those models for LTSpice don't work properly, and I bet the one you tried just uses the dflop special function and also failed to invert the PRE and CLR inputs to make the model working as an actual '74.

author: dutch66
author_rank: Contributor
timestamp: July 14, 2022, 03:16:39 am
content: Thanks for your help!I added two inverters and the result is now is as expected.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 14, 2022, 03:25:33 am
content: If the 74HC74 model you had tried is the one that ships with LTSpice (I took a look earlier but I have a bunch of custom models so I was not sure if the 74HC74 was from LTSpice or a custom one, but now I think it came with LTSpice), it indeed looks like just an 'alias' for the dflop behavioral model, so no surprise it acts the same. I now seem to remember that this 74HC74 model has been there for a long time, so it looks like it never got fixed...(As an aside, while LTSpice is free and reasonably good, the bug report handling doesn't look good at all. I've noticed long-standing bugs in LTSpice that never get fixed. I admit I have never really *officially* reported a bug, as I don't even really know how to do this, and I'm pretty sure that's the case for most of us... explaining further why bugs don't get fixed.)

author: dutch66
author_rank: Contributor
timestamp: July 15, 2022, 02:22:51 am
content: Hello everybody.Today I took some time to look into the 74HC74 model in a bit more detail. The model I use is from 74hc.lib, an older Linear Technologies Library and it indeed uses the DFLOP model. But it does invert the inputs and if used correctly it does actually work. This file is not part of the current LTspice distribution. The last revision was: "Revision 0.63 11/13/2009 74HC533 added".Each input is first run through a subcircuit that essentially defines an RC input filter. Following that each input is run trough a behavioral buffer. The C and D inputs use the normal buffer output the R and S inputs use the inverted buffer output. The buffered signals are send to a behavioral DFLOP and finally the output of the DFLOP is send to an output filter again defined as a subcircuit.In essence the model definition does include inverters in the R and S inputs and seems to be fine. I attach a small test I did and the result is as expected.The question remains why I did not get this to work in the first place. It was clearly a problem with the user and not with the modelAgain thanks for your help.