SMPS buck converter - mosfet gate parasitic turn on - Page 1
Forum section: electronics / beginners

author: Tom199
author_rank: Newbie
timestamp: July 30, 2020, 01:08:11 pm
content: Hi everyone, I'm designing SMPS power supply in buck mode operation and i have some false turn on's at the gates of mosfets (yellow signal is high side MOSFET, blue is low side...)I'm using NCP 3020A synchronous controller:https://www.onsemi.com/pub/Collateral/NCP3020-D.PDFParts and schematic that I'm using is almost consistent with page 22 of the datasheet, except mosfets and some additional ceramics at I/O. In my case these are IRFB3607, same for both switches. I'm also attaching my PCB layout and schematic.Actually, at the output i have 1.6 Ohm resistive load for now. Tried the different load too, but spikes remains the same. The output voltage should be 3.3V, Input Voltage is 12V.Is this problem caused by a parasitic capacitances of mosfets or their body diodes parameters? PCB layout probably? or something else?Thanks for any help in advance.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 30, 2020, 10:10:54 pm
content: It's the controller, whatever it is. Transistors don't turn themselves on and off simultaneously.Try this?Cut the VCC trace and run a jumper over to the high side drain. Add a cap, >= 1uF 1206, at the location shown (scratch soldermask off the traces to create pads for it).Tim

author: temperance
author_rank: Super Contributor
timestamp: July 31, 2020, 11:19:44 am
content: That's a very bad board layout.-The feeback circuit should directly connect to the controller GND. Not doing so will create instability. R2 is connected to PIN1 of the controller by walking around the PCB.-The input caps should be as close as possible to the upper MOSFET.-Don't put GND directly under the inductor.-C6 and C7 should be close to the inductor....

author: Tom199
author_rank: Newbie
timestamp: August 06, 2020, 08:33:59 am
content: According to comments I have received about my poor PCB layout I decided to make another one. But the previous problem I had still occurs exactly as it was before...Here is my another PCB layout. Any suggestions?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 06, 2020, 10:23:48 am
content: C_IN3 is on exactly the wrong side.WHAT, THIS IS TWO LAYER AFTER ALL?Pour ground on the top layer and add stitching vias. Ugh!Tim

author: Tom199
author_rank: Newbie
timestamp: August 06, 2020, 10:46:04 am
content: errrr not the double layer, it is just a wire connection, where do i have to place C_IN3 please?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 06, 2020, 02:56:14 pm
content: Between Q2 drain and Q1 source.Tim

author: Tom199
author_rank: Newbie
timestamp: August 07, 2020, 07:58:31 am
content: Thank you Tim for your help, cap between drain and source of those FET's solved the problem. Looks like I had spikes at the input side of source which were amplified by upper FET? Am I correct?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 07, 2020, 01:43:37 pm
content: The spikes were produced by each transistor in turn. The loop inductance between the transistors and the nearest return path (+V to -V, i.e. the capacitor) is what matters.When the load current goes from flowing through one transistor, to the other, the inductance associated with each transistor must charge and discharge to the respective currents (one from zero to load, the other from load to zero). Even if there is very little load, there is capacitance in the transistors, and an LC resonant circuit is excited, to a similar end.An inductor is charged with current, by applying a flux, i.e., some voltage for some duration. This exactly mirrors how a capacitor is charged with voltage, by applying a charge, i.e., some current for some duration.Inductor: V = L dI/dtCapacitor: I = C dV/dtThus the pulse height and width depends on inductance, rate of change (which in turn depends on gate resistance, the driver's capability, etc.), load current and transistor capacitance.Reducing the size of the loop reduces these inductances, reducing the voltage proportionally.Inductance is roughly proportional to length, so a longer loop will have more inductance. Trace the current return path before moving the capacitor: it went all the way around the controller. Huge loop. After, it's very short, little more than the path beneath the two transistors.Tim