RISC-V Development tools - Page 1
Forum section: electronics / general

author: mikerj
author_rank: Super Contributor
timestamp: November 21, 2017, 03:27:22 pm
content: Are there any commercial tools for the RISC-V architecture (i.e. where a licence includes full support), or is the Eclipse/GCC toolchain the only option at present?

author: ataradov
author_rank: Super Contributor
timestamp: November 21, 2017, 05:21:14 pm
content: There is not any real RISC V hardware. Who would invest into making a commercial system? The best you will probably see in coming years is the same GCC/Eclipse + commercial support.

author: mikerj
author_rank: Super Contributor
timestamp: November 21, 2017, 05:53:58 pm
content: Thanks, that's pretty much what I expected. We want to get custom ASIC designed and ideally wanted a Cortex M4 core in it since we have plenty of experience and all the tools, but the licensing and royalty cost is a little eye watering but doable. ASIC vendor suggested we consider using RISC-V, so just looking at the options.

author: ataradov
author_rank: Super Contributor
timestamp: November 21, 2017, 05:57:13 pm
content: I've been doing some experiments with RV lately, and the GCC seems to be stable enough. I don't use Eclipse, so I have no idea how that works.SiFive also released the binary builds of the toolchain recently, and this makes life much easier. For me this closes a significant gap between RAM and RV. Now we need to wait for real silicon.

author: legacy
author_rank: Super Contributor
timestamp: November 23, 2017, 11:31:41 am
content: Quote from: ataradov on November 21, 2017, 05:21:14 pmThis is the problem I have with my softcore.Nobody would invest into making a commercial system.They have PIC-and-tons-of-MPUs and that's fine.(FSK)

author: brucehoult
author_rank: Super Contributor
timestamp: November 23, 2017, 01:05:05 pm
content: Quote from: mikerj on November 21, 2017, 03:27:22 pmWhat kind of support do you want? gcc and eclipse are mature technology and unlikely to be very broken compared to hacked-up proprietary tools, so the main support needed seems to be beginner hand-holding. I don't use eclipse, but gcc, gdb, openocd work fine for me.The SiFive forums are pretty helpful and they are investing money in the tools -- just a couple of people (Palmer, Drew, Megan a bit I think) at the moment, but I hear they're planning to increase that.Liviu Ionescu is also working on tools, including read to go packaged eclipse setups.

author: brucehoult
author_rank: Super Contributor
timestamp: November 23, 2017, 01:08:38 pm
content: Quote from: mikerj on November 21, 2017, 05:53:58 pmInteresting. Who is the ASIC vendor?Making custom ASICs with a RISC-V core in the Cortex M4 class is exactly the thing SiFive has already demonstrated they can do -- and want to do. Contact them if you haven't already.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 23, 2017, 01:11:16 pm
content: QuoteThat's so cool, what sort of prices does ARM want for cortex M4?

author: brucehoult
author_rank: Super Contributor
timestamp: November 23, 2017, 01:26:34 pm
content: Andes Technology is also doing quite a lot with RISC-V. They're contributing llvm support they've done internally (though as normal it needs cleaning up before it can be merged back to the main llvm project) and they just a few minutes ago put out a proposal (or the starting point for a proposal) for a RISC-V P "Packed SIMD" extension, which is pretty desperately needed to compete with ARM in a lot of areas.https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/vYVi95gF2Mo/25SALFsxBQAJ

author: mikerj
author_rank: Super Contributor
timestamp: November 24, 2017, 10:00:29 am
content: Quote from: brucehoult on November 23, 2017, 01:05:05 pmWe currently have a number of seats of the Keil tools, and I have to say that support has been excellent on the occasions we have needed it e.g. installation issues, target support and even a couple of compiler bugs (a few years back though).I have nothing against GCC given it's price, and have used it for many years on personal projects. There isn't much love for Eclipse amongst the team I work with however.The driver here is that timescales are quite tight, we need to be able to hit the ground running on the first iteration of silicon so we don't want to waste any of it trying to resolve any toolchain problems that may arise by ourselves.Quote from: brucehoult on November 23, 2017, 01:08:38 pmI'd rather not say right now, but the cost of ARM licensing has been brought up by most of the smaller vendors we have contacted and RISC-V was suggested by two of them.Quote from: ali_asadzadeh on November 23, 2017, 01:11:16 pmNot as cool as it sounds IMO; it's a huge amount of work with tight deadlines, and a considerable investment for a fairly low volume demand so the risk is high. However we need large reductions in the size of our current discrete solution, and we are already down to 01005 passives and chipscale ICs wherever possible, so not much choice really.We've not had an official quote yet, but my research suggests around $200k for licensing, no idea on royalties. It's relatively low compared to the total cost of developing the entire thing, but needs to be traded off against possible risks and time of using an unknown (to us) architecture and unsupported tools.

author: coppice
author_rank: Super Contributor
timestamp: November 24, 2017, 01:17:01 pm
content: Quote from: mikerj on November 24, 2017, 10:00:29 amNone of the successful stable MCU families you see came together quickly or cheaply, even if they licenced a core (e.g. the M4) to drop in. This is especially true if there are tight requirements in, say, the low power direction. If you don't want to tread the same ground they did, it can be a huge time and cost saver to work with someone who has all the key pieces running smoothly on an economical process, and only needs to integrate your special sauce to make a new part.

author: brucehoult
author_rank: Super Contributor
timestamp: November 24, 2017, 02:12:10 pm
content: Quote from: mikerj on November 24, 2017, 10:00:29 amGCC was sometimes a bit dodgy 20 years ago, or even 15. I remember the company I was working for in 2002 sticking with GCC 2.95 for a long time because it actually worked reliably, whereas the 3.0.x releases were awful.Now GCC is very reliable. The front end and optimiser are shared by everything, so that only leaves the RISC-V back end to cause problems. It's such a simple architecture that there isn't much chance of problems.I'd say the biggest sticking point would be what kind of instructions you need. Plain old integer code, great, no problem. Single and double precision floating point are there too, though there isn't yet a commercially buyable core implementing them -- SiFive's U54 quad core processor due early 2018 will have DP FP.RISC-V doesn't yet have SIMD instructions specified i.e. a competitor to NEON. If you need that soon then you're out of luck. RISC-V also doesn't have anything like count-leading-zeroes or population count or bit reverse or bitfield extract or insert standardized. There is a working group doing that right now. If you need some of those and are making a custom ASIC anyway then they're pretty easy to implement.

author: andersm
author_rank: Super Contributor
timestamp: November 24, 2017, 02:15:46 pm
content: Quote from: brucehoult on November 23, 2017, 01:05:05 pmOn the other hand, the RISC-V port is quite new, and there seems to still be a decent amount of bug fixing activity going on.

author: brucehoult
author_rank: Super Contributor
timestamp: November 24, 2017, 02:38:18 pm
content: Quote from: andersm on November 24, 2017, 02:15:46 pmEnhancements and optimisations, definitely. I'm not aware of too many bugs. It builds a linux kernel just fine, and I've personally built and used (in emulation) a small linux distro (riscv-poky) based on the Yocto distribution for embedded systems. Fedora built their complete desktop distribution, and say they are ready to do an official release as soon as the riscv changes to the Linux kernel and glibc are officially upstreamed and released (will be in Linux 4.15 in Jan for sure, and glibc should be in Jan or Feb too).It's new for sure, and there is always a possibility of something showing up, but the rate of progress is good and there are a lot of people contributing to it.

author: mikerj
author_rank: Super Contributor
timestamp: November 27, 2017, 11:14:02 pm
content: Quote from: brucehoult on November 24, 2017, 02:12:10 pmThe reason we wanted the M4 core over M3 was for the FPU, so this would need to be part of the RISC-V implementation as well. I'm told the IP is available for that.

author: brucehoult
author_rank: Super Contributor
timestamp: November 28, 2017, 12:24:48 am
content: Quote from: mikerj on November 27, 2017, 11:14:02 pmSiFive's U54 supports single and double precision FP. In the ISA "RV64GC" is shorthand for "RV64IMAFDC" with F and D being FP.https://www.sifive.com/products/risc-v-core-ip/u54-mc/They don't seem to be offering FP support in the off-the-shelf configuration page for the 32 bit E31 core designed for embedded systems.https://www.sifive.com/products/risc-v-core-ip/e31/If you ask them about it I'm sure they could add the FPU to one for you. It might be the case though that once you have an FP (especially a double precision one) you hardly notice the extra chip area for 64 bit integer registers and ALU instead of 32 bit.

author: brucehoult
author_rank: Super Contributor
timestamp: November 28, 2017, 10:08:43 pm
content: Some interesting developments at the 7th RISC-V Workshop Milpitas, CA, today.Western Digital announced that:1) they ship over one billion processors a year, and2) over the next several years they are switching them all to RISC-Vhttps://pbs.twimg.com/media/DPvgpwFUEAACBv-.jpg:largehttps://www.google.com/url?q=https%3A%2F%2Fwww.wdc.com%2Fabout-wd%2Fnewsroom%2Fpress-room%2F2017-11-28-western-digital-to-accelerate-the-future-of-next-generation-computing-architectures-for-big-data-and-fast-data-environments.html&sa=D&sntz=1&usg=AFQjCNF_IORI4uZ7cTIBHIigipq3KQmbGwAlso a startup called Esperanto Technologies came out of stealth mode.https://www.esperanto.ai/single-post/2017/11/28/Esperanto-Technologies-Plans-Energy-Efficient-Chips-for-Artificial-Intelligence-and-Machine-Learning-based-on-the-open-RISC-V-standard(these two are not completely unrelated)

author: coppice
author_rank: Super Contributor
timestamp: November 28, 2017, 10:20:05 pm
content: Quote from: brucehoult on November 28, 2017, 10:08:43 pmAre you sure they are shipping this quantity? The slide you reference seems to imply that after several years of transition they will be shipping a billion cores.

author: hamster_nz
author_rank: Super Contributor
timestamp: November 29, 2017, 01:02:07 am
content: Quote from: brucehoult on November 28, 2017, 10:08:43 pmWow - looks like metaphorical shot across the bows for ARM...

author: brucehoult
author_rank: Super Contributor
timestamp: November 29, 2017, 01:50:19 am
content: Quote from: coppice on November 28, 2017, 10:20:05 pmThey definitely said >1b today, several billion a year by the time the transition is complete.

author: voltsandjolts
author_rank: Unknown
timestamp: November 29, 2017, 12:58:28 pm
content: Yup.https://www.wdc.com/about-wd/newsroom/press-room/2017-11-28-western-digital-to-accelerate-the-future-of-next-generation-computing-architectures-for-big-data-and-fast-data-environments.htmlQuoteQuote

author: mac.6
author_rank: Regular Contributor
timestamp: December 01, 2017, 08:12:46 am
content: Quote from: brucehoult on November 29, 2017, 01:50:19 amwestern digitaltocontribute one billion coreWell I am not native english speaker but I understant they are moving to risc-v for their custom processors, not they have completely transitioned to risc-v.Remember that final specs are quite young considering that you need one or two test chips to master/iron out a new architecture.They are not alone, but other may stay quiet for now.

author: Scrts
author_rank: Frequent Contributor
timestamp: December 01, 2017, 07:26:51 pm
content: Do they also count multiple cores in one chip? 100M chips with 10 cores is 1B cores.

author: ataradov
author_rank: Super Contributor
timestamp: December 01, 2017, 07:28:46 pm
content: Quote from: Scrts on December 01, 2017, 07:26:51 pmI would assume so.I also don't understand why this metric matters at all. Who cares how many chips are sold. The important questions are: do they work? Do they serve a purpose? Are they at least breaking even on investments?

author: kfnight
author_rank: Regular Contributor
timestamp: December 04, 2017, 04:18:09 pm
content: Quote from: ataradov on December 01, 2017, 07:28:46 pmI would assume Western Digital cares if it saves them millions of dollars in licensing fees.

author: ataradov
author_rank: Super Contributor
timestamp: December 04, 2017, 04:40:09 pm
content: Quote from: kfnight on December 04, 2017, 04:18:09 pmOk, but in this case it appears to be presented as some sort of achievement for the ISA.

author: brucehoult
author_rank: Super Contributor
timestamp: December 07, 2017, 07:46:40 pm
content: Quote from: ataradov on December 04, 2017, 04:40:09 pm1) someone big decided the ISA is worth using vs ARM and/or x86 (WD uses both in different products)2) they are going to invest time and money into the software/tool ecosystem too. See the 2nd message in this thread.

author: brucehoult
author_rank: Super Contributor
timestamp: March 09, 2018, 01:36:24 am
content: A little personal news ... I'm putting my RISC-V money where my mouth is and I've joined SiFive and will be moving from Moscow to San Mateo.On Monday-Wednesday next week I'll be assisting Palmer in running a hackathon at the Embedded Linux Conference in Portland. There are three different categories. The winner of each category will receive a HiFive Unleashed quad core 1.5 GHz board, as well as a cash prize.We'll be taking 50 boards for people to play with.I've been playing with them in the office this week. They are very comparable on the integer tasks I've tried to an Odroid C2 (A53) at the same MHz, and definitely faster than Raspberry Pi 3 (also A53).Of course the boards are selling for a lot more than those A53 boards at the moment, due to newness and low production rate. That will change in time.https://www.sifive.com/blog/2018/03/03/all-aboard-part-11-risc-v-hackathon-presented-by-sifive/

author: Scrts
author_rank: Frequent Contributor
timestamp: March 09, 2018, 02:15:46 pm
content: Quote from: brucehoult on March 09, 2018, 01:36:24 amWhat a move! Good luck!I am watching RISC-V development very closely

author: kfnight
author_rank: Regular Contributor
timestamp: March 09, 2018, 03:53:46 pm
content: I wanted to go for just a day or two to the Embedded Linux conference, but they don't have single day admission.

author: brucehoult
author_rank: Super Contributor
timestamp: March 09, 2018, 07:44:41 pm
content: You could pop into the SiFive hackathon suite, no problem.Even the showroom floor is probably pretty easy. They usually only check tags for the meals and maybe keynote. If that. Just walk in like you own the place.

author: Boscoe
author_rank: Frequent Contributor
timestamp: March 13, 2018, 01:54:32 pm
content: Hi all,I'm interested in RISC-V as an Altera user there isn't a free softcore in the tools. I like the idea behind RV and it's possibilities.Now, I downloaded the source for the RISC V from SiFive but have no idea how to integrate it into a project and get it running on an FPGA, is this possible? Are there any guides?Thanks

author: andersm
author_rank: Super Contributor
timestamp: March 13, 2018, 03:26:04 pm
content: Quote from: Boscoe on March 13, 2018, 01:54:32 pmThe Nios II "economy" core is free (and low-performance), isn't it?

author: ataradov
author_rank: Super Contributor
timestamp: March 13, 2018, 03:31:05 pm
content: Quote from: Boscoe on March 13, 2018, 01:54:32 pmSiFive core is not really a softcore. It is a real core built to be implemented in silicon.For simple cores actually designed for FPGAs you need to look at something like PicoRV32 (https://github.com/cliffordwolf/picorv32), or my absolutely drop dead simple implementation (https://github.com/ataradov/riscv), which has projects for MAX 10 FPGAs, but easy enough to port to others.None of them are going to be in any drag and drop style system builders, since NIOS II is a far better choice for actual work, if you plan to stick with Altera. And that's the whole point of making NIOS II, so that you stick with Altera, so there is not a whole lot of incentive for them to use anything else.

author: brucehoult
author_rank: Super Contributor
timestamp: March 14, 2018, 05:18:36 am
content: About three times shorter source code than PicoRV32. Under 1000 lines. Nice. Although there are also fewer options.How many LUTs does it work out to?

author: ataradov
author_rank: Super Contributor
timestamp: March 14, 2018, 05:30:31 am
content: Here is a table from my notes, it may be a bit outdated, but the final numbers should be very similar. RVC - compressed ISA support, BS - Barrel Shifter, MUL - single cycle hardware multiplier.Code:Config | LE | REG | MUL |----------+------+-----+-----+RVC + BS | 2256 | 441 | - |RVC + MUL | 1807 | 410 | 8 |RVC | 1972 | 481 | - |BS | 1970 | 442 | - |MUL | 1511 | 410 | 8 |- | 1662 | 481 | - |----------+------+-----+-----+It synthesizes at at least 60 MHz in the slowest grade MAX 10.

author: mac.6
author_rank: Regular Contributor
timestamp: March 14, 2018, 01:39:25 pm
content: Quote from: Boscoe on March 13, 2018, 01:54:32 pmYou can try VexRisc from SpinalHDL project, bigger than PicoRV32 and other but nicely scalable (and there is a DE2 nano project). There is also microriscy from pulpino project which is a risc-v derivative.

author: ale500
author_rank: Frequent Contributor
timestamp: March 20, 2018, 08:25:39 pm
content: Hei Ataradov,I tried your RISCV, very impressive. I used the gcc I compiled for the PicoRISCV project and had to add an start file with a jump to the entry function. I massaged for a DE10-Lite board, very nice.Thanks for sharing !

author: ehughes
author_rank: Frequent Contributor
timestamp: March 20, 2018, 10:20:30 pm
content: Segger offers a commercially supported pckage for RISC V with Embedded Studio. There debugger is top notch so I would expect it to be a good tool.