Consequences of using a single ended clock in an fpga differential input - Page 1
Forum section: electronics / projects

author: maor
author_rank: Contributor
timestamp: October 29, 2012, 07:05:27 am
content: I am currently designing a system using an altera fpga, the cyclone IV GX series which also contains high speed transceivers.In the design, we decided to use a single ended clock where the positive terminal of the high speed clock is connected to clk_P and a termination resistor of 33ohms from clk_n to ground.while writing some code and testing it in quartus, I found out the block only works with a differential clock setting in the pin assignment.Now the question is, if I still use the single ended clock and define the input as a differential one, will it work?When I take it from the logic of differential signaling, it has to work since it will calculate (clk_p-0V) and should work fine, but does it work the same inside the fpga?, is there a forced vcm to ensure the proper voltage level is used?I added the circuit if it would help you guys understand, thanks in advance for the help.Maor

author: AndyC_772
author_rank: Super Contributor
timestamp: October 29, 2012, 07:37:16 am
content: If you ground clk_n then the FPGA won't ever see the clock, because (clk_p - clk_n) is always >0. To have a chance of working, you'd need to terminate clk_n to a voltage mid-way between the high and low levels used on the clk_p pin.Don't the transceivers in the GX series always get their clock from an internal PLL anyway, though? Can you not (say) instantiate a PLL with its input reference on CLKIO20, and then define it as single ended?

author: maor
author_rank: Contributor
timestamp: October 29, 2012, 08:00:32 am
content: They have their own designated clock inputs for their PLL's, while you can take it from the main clock, the fitter will work a lot better if the pll inputs are taken from those pins.So the differential summer in the clock inputs is a comparator?Because my natural thinking would be that it's a difference amp since you can reach more ideal control when you limit the gain

author: free_electron
author_rank: Super Contributor
timestamp: October 29, 2012, 04:35:46 pm
content: ? there is no comparator or opamp in the input stage... there is two level detecters centered around a centerpoint voltage with a specific hysteresis.in order to have a valid edge one must go positive while the other goes negative in respect to this reference voltage.if only one toggles : invalid edge.the centerpoint is derived from the common mode of the incoming signals , sampled and stored on a cap.essentially what the circuit does is this :Code:P--+-----|+\| | >------- -|-/ || | |---|-----|+---+---||---gnd | XOR |--- clock| | ---|_____| -|-\ || | >--------N--+-----|+/since the signals are always opposite polarity the centerpoint ismaintained at all cost. if a common mode signal comes in the entire system is tilted up or down so the detection still works. if a single ended distrubance occurs only one of the output will toggle and the XOR gate will not react as only combinations 01 and 10 are deemed valid edges.Now, altera may have implemented their system differently. the above is based on what i know about differential signalling using a differential clock. my representation with two resistors and a cap is also a bit off. there is a sampling element that only determines the centerpoint a given intervals ( derived from the clock )

author: maor
author_rank: Contributor
timestamp: October 29, 2012, 08:01:15 pm
content: So essentially I am forced to to get a differential clock converter/buffer, any help here people?