STM32F407 FIR and IIR Filter Capabilities? - Page 1
Forum section: electronics / general

author: rcbuck
author_rank: Frequent Contributor
timestamp: November 05, 2020, 09:51:45 pm
content: I have a STM32F407 Discovery board. I have never worked with digital filters. But thought I would investigate how they work. I have watched a couple of videos and read a few documents online. I have found code online to load into the 407 for testing but haven't done so yet.Before I go down this rabbit hole I need to ask if what I want to do can in fact be done.I would like to create a bandpass filter centered on 60 kHz. Can the 407 handle this frequency since it would need to sample the signal at 120 kHz minimum? Everything I have found online involves processing audio. What is the minimum bandwidth that is possible at this frequency? 10 Hz, 50 Hz, 100 Hz?If 10 Hz is possible, what would be a rough estimate of processor percentage time required? I can use a wider bandwidth if 10 Hz swamps the 407. If I understand what I have read, I can send the wideband signal into one of the ADCs and have DMA transfer it to the DAC. I will be using 12 bit mode on both the ADC and DAC. The transfer would generate DMA half complete and complete interrupts that I would use to process the samples. The wideband signal has noise that I am trying to eliminate.I think I would need to use a FIR filter since it has minimal effect on the phase of the signal. However, it requires more resources than an IIR filter does.Any suggestions as to good videos to watch or documents to read specific to the STM32F4xx family and digital filters?

author: MasterT
author_rank: Frequent Contributor
timestamp: November 05, 2020, 11:20:01 pm
content: There is : AN4841 Application note Digital signal processing for STM32 microcontrollers using CMSISI don't think 10 Hz FIR 'd be possible at 120 ksps, IIR seems feasible.

author: abraxalito
author_rank: Contributor
timestamp: November 06, 2020, 01:26:48 am
content: This presentation from DSP Concepts is useful to gauge the capability of various processors running DSP. It includes tables for how many CPU cycles are taken for various filter implementations :https://dspconcepts.com/sites/default/files/pd8_beckmann.pdf

author: voltsandjolts
author_rank: Unknown
timestamp: November 06, 2020, 09:14:29 am
content: Quote from: abraxalito on November 06, 2020, 01:26:48 amInteresting PDF. I'm gonna attach it here incase the link breaks.

author: Siwastaja
author_rank: Super Contributor
timestamp: November 06, 2020, 10:50:02 am
content: You need to sample the signal with twice the f of the highest frequency component theinput signalcontains.Seeing you want tofilter outsignals outside 60kHz +/- some 10 Hz, this surely means you have components over 60kHz (otherwise you wouldn't be asking how to filter them out)?If this is the case, you need way more fs than 120kHz.Start by determining the highest frequency component present in the input to properly choose fs.Then fire up Matlab or the free alternative, Octave. Filter design is fairly simple with the built-in functions, a lot of tutorials available. I bet your 60kHz +/- 10Hz filter requires a tremendously massive number of taps especially in FIR, say thousands, this is likely too much for the F407. Get the order of magnitude right: ballparking it, a F407 will some hundred taps at around 100kHz. Each tap is a multiplication and accumulation each cycle, so 100 taps * 100kHz would be 10M operations per second. I don't offhand remember if MAC instruction is available on F4, but if it isn't, one tap is approximately two memory loads (signal value, tap coefficient value), multiplication, addition, and one memory store. Roughly 10 clock cycles.But start with Matlab/Octave, see how the number of taps affects the steepness of the filter, or the stop band attenuation. If you only have performance for 100 taps, especially FIR will be quite compromised in this regard.The CMSIS DSP library may be optimized, but it's only efficient if your application uses exact same buffer types and batch processing, which often isn't the case. In any case,impementingFIR or IIR in C is approx. 5 lines of code and maybe 10 in asm so I don't see a point in wasting even a second of your time in said library.For example, the last time I did a FIR filter was adecimatingFIR filter which is WAY more efficient than running a FIR in batch with input & output buffers, then decimate as a separate step. Talk about over 10x difference in performance. I handcoded it in asm utilizing floating point registers as accumulators getting further performance increases and IIRC some 250 taps FIR @ fs=2MHz fout=250kHz was only some 20-30% maybe of the performance of Cortex-M7 at 400MHz.

author: ace1903
author_rank: Regular Contributor
timestamp: November 06, 2020, 12:31:00 pm
content: On 60Khz, bandwidth of 10 even 100Hz will require filter with huge Q factor.Even jitter on core clock (on F407) will ruin your results if you need 10Hz. I think that also numerical rounding effects matters when having huge Q factor.Think first about your application and if you really need 10Hz? Source signal can drift more than 10Hz if it is not produced from quality signal generator.

author: voltsandjolts
author_rank: Unknown
timestamp: November 06, 2020, 01:59:01 pm
content: If the OP just needs to measure the amplitude of a 60kHz signal, with narrow passband, using synchronous detection is probably the better way to go.

author: rcbuck
author_rank: Frequent Contributor
timestamp: November 06, 2020, 06:20:35 pm
content: Thanks all for the input and references to documentation.What I am actually trying to do is filter out noise around the WWVB signal. I have a RF front end I built made up of 6 stages of op amps. Four of those stages are bandpass stages centered on 60 kHz. The spectrum analyzer shows the 6 dB down points to be about 2 kHz wide. Most of the noise in a 20 kHz wide sweep is between 10 dB and 30 dB down from the WWVB signal. I have no issues receiving the WWVB signal easily during night time hours. I am in Phoenix so I am only about 600 miles from Ft Collins as the crow flies.I was curious if I could create a similar digital filter. The 10 and 100 Hz bandwidth was just a question to get opinions and suggestions.A digital filter with a 2 kHz bandwidth would be fine. I'm sure it would perform as well as the op amp filters. Probably much better because the edges would drop off much more sharply at the 2 kHz points. The maximum speed for the Discovery F4 board is 168 Mhz so I guess I am limited in the number of taps that can be used.Siwastaja, what is your estimate of the number of taps required for a 2 kHz bandwidth and estimate for the F407 CPU percentage? I could move to a Cortex-M7 if necessary since this is my one off project. I don't have a development board for the the STM32F7 series but Mouser has several inexpensive boards.

author: eliocor
author_rank: Unknown
timestamp: November 06, 2020, 08:12:39 pm
content: maybe this receiver can be of interest to you:https://www.i2phd.org/armradio/index.htmlsame project, but ported on gcc:https://hackaday.io/project/171053-arm-radio-for-system-workbench

author: jonroger
author_rank: Regular Contributor
timestamp: November 06, 2020, 10:24:42 pm
content: I run 12,000 taps on stereo 44.1khz signals using a teensy 4 MCU.

author: rcbuck
author_rank: Frequent Contributor
timestamp: November 07, 2020, 06:52:39 am
content: Iowa Hills FIR Filter designer shows this for a 100 tap, 2 kHz wide filter. Assuming 10 clock cycles per that would be 30,000,000 clock cycles. The maximum speed for the STM32F407 is 36 MHz. So I would be OK?

author: Siwastaja
author_rank: Super Contributor
timestamp: November 07, 2020, 07:24:22 am
content: Oh, you'lleasilyexceed the performance of 12th order analog (this is what I'm assuming from your description of "6 opamp stages") filter by digital.If nothing else, on analog it's quite hard to get exact pass frequency due to component tolerances and drift (unless you are a very seasoned analog filter designer, I suspect your analog filter performs far worse than simulated, already). On digital domain, that's not a problem.If you need exact group delay over the whole frequency range, then indeed use FIR, but otherwise, if you are performance limited and require steep filter, then IIR brings the number of taps down significantly. OTOH, IIR may require more bits for intermediate results to avoid quantization errors.Remember, IIR is more "equivalent" to the analog filter - it has feedback like analog, and the consequence of that feedback is that phase response becomes one part of the total compromise.FIR, on the other hand, is something you only have on the digital domain. With no feedback, the phase response can be perfectly linear, but you need alotmore coeffs to get the steepness and stop band attenuation of IIR.Limiting f_cpu to 36MHz limits your performance quite a bit. What's the reason for this limitation? The MCU supports up to 168 MHz.M7 has dual-issue pipeline meaning the CPU parallels load operations to some CPU registers while simultanously running arithmetic on other registers. Remember to utilize fast core-coupled memories; for example, put the code in ITCM and the coeffs in DTCM.Some hand assembly may be required for full performance but OTOH the actual filtering core is so small piece of code this will become an interesting exercise where the total complexity won't blow up.

author: rcbuck
author_rank: Frequent Contributor
timestamp: November 07, 2020, 05:22:22 pm
content: Siwastaja, 36 MHz is the ADC conversion speed. The CPU will be running at 168 MHz.I actually built the analog filter and it is a 12th order design. The performance I mentioned is what I see when I use the spectrum analyzer to sweep the filter stages. The filter isn't exactly centered on 60 kHz and it has some ripple. But it works good enough to enable me to receive WWVB.I do need low group delay so a FIR filter is what I will have to use.

author: Siwastaja
author_rank: Super Contributor
timestamp: November 07, 2020, 05:38:03 pm
content: Note that the group delay of the FIR is far fromlow, but it isconstant- namely 0.5 * 1/fs * n_taps.If you need absolutely minimum delay yet steep response and high stop-band attenuation, an IIR might still be better even though the phase response isn't perfectly linear and hence the group delay isn't exactly constant per frequency.No, 36MHz isn't ADC "conversion speed" whatever that means, it may be the max clock input to the ADC block, defining the internal conversion steps, many of which are required to get a single sample out. Themaximum sample rateis 2.4MSPS (or 7.2MSPS in interleaved mode but I wouldn't bother with it).It's a good idea to use as much sample rate as available to lessen the requirements for the analog input stage. For example, if the highest frequency component in input signal is 100kHz, you can choose adc_fs=200kHz and build a perfect brick-wall analog filter (which is impossible); or you can choose adc_fs=1000kHz and then your analog filter can slowly roll off to enough attenuation at adc_fs/2 = 500kHz. And in practice, it happens that today an ADC with higher sample rate (+ a CPU to process such high rate) is cheaper than building a 12th order analog filter. So usually, you build just a 1st or 2nd order analog filter,maybe4th order, then oversample enough so that nyquist is well over the highest filtered component * 2, then run FIR or IIR and decimate to final sample rate to save memory storage requirements. (For this purpose, a decimating filter implementation is much more efficient than first filtering a buffer, then decimating it, because a decimating filter does not need to output most of the data at all.)Added benefit in such oversampling, filtration and decimation is that the ADC noise goes down, and resolution goes up. Compare running the same ADC at 240 ksmps/s or 2.4 MSPS; the noise performance and resolution of the ADC is approximately the samefor each sample, but if you run the ADC at 2.4MSPS, the FIR or IIR basically averages many samples together, increasing equivalent number of bits somewhat (depending on how important linearity, which doesn't improve, is for your application).You might be able just to build an analog low-pass filter (solely for antialias purposes), instead of the band-pass, then do band-pass digitally. Analog band-pass filter may be required if out-band signals are so strong they would saturate the ADC input.

author: pigrew
author_rank: Frequent Contributor
timestamp: November 07, 2020, 05:55:18 pm
content: The analog bandwidth of the 'F407 ADC is about 6 MHz (datasheet shows 6 kOhm series resistance, with 4 pF sampling cap). ADC clocks can be plenty high (~6 MSa/s, 100 times higher than the carrier2 MSa/s in single-ADC mode)Another perhaps more major issue is the quality of the DAC. Its (full-scale) settling time is a few us, so will likely impact a 60 kHz output signal. You can try creating a DDS 60 kHz sine generator, and look at signal quality. An external clock might need to be used (or bypass the PLL for the ADC clock???).In terms of processing capacity, my guess is that it's good enough. The discussion so far in this thread well covers all the major issues.

author: rcbuck
author_rank: Frequent Contributor
timestamp: November 07, 2020, 08:32:17 pm
content: pigrew, thanks for mentioning that. I used the ADC/DAC combo last year to transfer audio over Ethernet. I seem to remember having issues when I tried to get the frequency above 24 kHz in that project.The data sheet shows typical settling time as 3 usecs, max 6 usecs. The 3 "might" be ok but 6 is more that 33% of a 60kHz signal cycle time. I'll fire up the discovery board and see what a 60 kHz sine wave looks like.

author: Siwastaja
author_rank: Super Contributor
timestamp: November 08, 2020, 09:28:48 am
content: Note that the "analog bandwidth" in ADC datasheet describes the -3dB point of the parasitic 1st order RC filter. This plays in your favor a little bit but doesn't replace the external anti-alias filter unless, of course, you know that there simply is no significant input signal over nyquist present in which case you don't need AA filter. Some noise is always there and filtering out-band noise out prevents it from aliasing in-band, but OTOH, adding filtering stages adds noise as well.