Inadvertent voltage divider with a MOSFET?  - Page 1
Forum section: electronics / beginners

author: horse_ebookmarklet
author_rank: Contributor
timestamp: October 01, 2022, 02:34:16 am
content: Hey,I am seeing a circuit behavior that I don't understand. I think I am forming a voltage divider but I don't understand why.Let me start with a schematic:The requirements of this circuit are:The FPGA and Buffer IC are in separate power domains; the purpose of this circuit is to isolate I/O between these domains.When the FPGA is OFF or not configured, pull the gate of the MOSFET lowWhen the MOSFET is not on, pull the BUFFER_ENABLE_N lowWhen the FPGA driving the MOSFET high, drive BUFFER_ENABLE_N highWhat I am seeing that is not expected, is when the MOSFET has 3.3V at the gate and 3.3V at the drain, I see ~1.65V at BUFFER_ENABLE_N.Here is the layout:

author: Peabody
author_rank: Super Contributor
timestamp: October 01, 2022, 04:22:36 am
content: An N-channel mosfet will turn on only if the gate voltage relative to the source voltage is at least equal to the Vgs threshold voltage shown in the datasheet. The 2N7002 shows a typical threshold voltage of 2.1V, but an individual part can vary a good bit from that. Yours appears to be 1.65V. I don't think it's a divider, it's just coincidence that it's half of 3.3V. If you change R11 to 100K, I think it will still be close to 1.65V.If you raise the gate voltage to 3.3V, the source voltage must be lower than that by the threshold voltage before any current will flow. So the source voltage will rise from ground only to the point where Vgs is equal to the threshold voltage. If the source were higher than than, the threshold would not be met, and the mosfet would be off. So your circuit doesn't work.So you need to move R11 and BUFFER_ENABLE_N up to the drain, and reverse the logic of the gate input.Alternatively, you could move R11 and BUFFER_ENABLE to the drain, connect the gate to the FPGA's 3.3V rail, and connect the FPGA output to the source. I think that would preserve your logic polarity.

author: ledtester
author_rank: Super Contributor
timestamp: October 01, 2022, 04:52:29 am
content: N-channel MOSFETs are generally used as a low-side switcher -- P-channel MOSFETs as high-side switchers.Quote from: Peabody on October 01, 2022, 04:22:36 amAfter moving R11 as specified you can also invert the output of Q5 by adding another low-side switching stage like this:(Image taken fromhttps://next-hack.com/index.php/2017/09/15/how-to-interface-a-5v-output-to-a-3-3v-input/)

author: Whales
author_rank: Super Contributor
timestamp: October 01, 2022, 06:45:54 am
content: Wrong arrangement of transistor and resistor.You have made a"common drain" (AKA common collector) amplifier. The output voltage will match the input voltage minus a few volts. You mostly use these in analog circuits, not digital circuits.What you want is a"common source" (AKA common emitter) amplifier. These act as an inverter that (for the most part) outputs either 0V or the full rail voltage (3.3V). You use these mostly in digital circuits, not analog circuits (unless you add more resistors but I won't go there).These two amplifier arrangements look very similiar but have dramatically different properties. The behaviour you are seeing is exactly as expected. Swapping the transistor and the resistor OR changing the transistor type (N vs P) will switch the type of amplifier. Using the transistor backwards will not work, it will blow up.N.B. you will want to use two common source amplifiers in series if you don't want an inverted signal. Either that or invert the signal being output by the FPGA. An actual "buffer" logic gate chip will internally implement two common source amplifiers in series, it's the simplest and most reliable way of buffering a digital signal in most circumstances.

author: Peabody
author_rank: Super Contributor
timestamp: October 01, 2022, 02:53:29 pm
content: The circuit below would preserve your logic polarity while still using just one mosfet. However, the output would be high if the FPGA is not present, or if its output is tristate.

author: horse_ebookmarklet
author_rank: Contributor
timestamp: October 01, 2022, 06:31:00 pm
content: Ok so I clearly had some misunderstandings. Thanks everyone. My first mistake was not understanding that for an N type the turn on threshold is the gate relative to the source. I'm going to spend some more time understanding P vs N and theory of operation.One thing I might not have explained well is this circuit is to isolate the FPGA from the buffer power domain; My board is an add-on to a commercial product, and I must bring my own power from an external source. Because of this the 3.3V domain is separate from the FPGA power domains (3.3V can be on but the FPGA can be off).If I re-arrange the circuit to be a low side, I am wondering if it is wise to pull an un-powered FPGA pin up via a pull up resistor. In the below, 3.3V is on (host power) and the FPGA is off (add on power), I would be concerned the FPGA's IO pins are going to do weird things to the circuit.So my options are:Move the resistor and signal, but I dont think this will work due to power domain issuesUse a P typeCascade n typesCleverness connect an FPGA IO to the source and tie the gate highUsing a P type mosfet seems more in line with my initial intentions. I don't currently have one on my BOM so I will need to evaluate if adding this part vs the next option.For the cascade solution, I need to keep my FPGA IO pulled to ground, so I can I use the second one as an inverter? Would this work?The main advantage I see is I already have a few other instances of the n type mosfet, so this would increase part count but keep BOM list the same.The clever option is too clever for me to fully grok at the moment.

author: ledtester
author_rank: Super Contributor
timestamp: October 01, 2022, 07:17:09 pm
content: QuoteWhich is your add-on board, the FPGA or the buffer?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: October 01, 2022, 07:55:06 pm
content: MOSfet theory simplified:You can treat a MOS fet as a voltage controlled resistor.If Ugs (Gate - Source Voltage) is below some threshold (usually 3 to 5V) then the resistance between source and drain is high (> Meg Ohm)If Ugs is above that threshold, then the resistance between source and drain is low.This works for both P- an N- channel MOS fets, but the polarities are reversed (not the pins).What happens in your first circuit:If "FROM_FPGA" is high, then the source drain channel "opens" (to a low resitance) however, because of the current though R11, the voltage on the source also rises, and this causes Ugs to get smaller. The voltage on the source will settle about "Ugs" lower then the gate voltage, because that is when the MOSfet starts to squeeze the current by increasing it's drain to source resistance.So your particular 2N7002 has an Ugs of 3.3 - 1.65 = (also) 1.65V.But it's not a voltage divider. Ugs will be (almost) stable.If you for example put 12V at the drain and 8.65V on the gate, then the source will settle at 7V.If I remember well, Wikipedia has a quite good explanation of MOS-fets (and other electronic components), but there is plenty of literature.Also:You can DIY a level shifter, but these are so common that you can get breakout boards for level converters quite cheap. Order some the next time you order some electronic stuff.Another note about KiCad:I see a little green (open) square on the gate of your MOSfet. This means an open wire end at that location. If wires end neatly at the connection points of schematic symbols, then you also do not see junction dots there (as with your resistors and the GND symbol)In your circuit it's not a real problem (although ERC may flag it). But such things sometimes cause problems, and when you use KiCad more, you'll probably become just as allergic to seing those squares as I have become. Those open squares always are an indication that the schematic needs a bit of cleanup.

author: Benta
author_rank: Super Contributor
timestamp: October 01, 2022, 08:14:34 pm
content: Just use a 74VHC1G66 with a pull-up or pull-down resistor as required.

author: horse_ebookmarklet
author_rank: Contributor
timestamp: October 01, 2022, 09:51:11 pm
content: Quote from: ledtester on October 01, 2022, 07:17:09 pmI am both the buffer and FPGA. The host system has ~25Mhz parallel lines (32 bit) that my buffers sample then go to my FPGA. I am hanging my buffers off the host system 3.3, the FPGA is derived from external power.Level shifters seem a good option. 74VHC1G66 too. A lot of options here for a new person to pick from. Hard to know what is best.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: October 02, 2022, 01:37:51 pm
content: You're never going to get 25MHz though a MOSfet with a passive pull up or down resistor on the other side.The resistor forms an RC constant with the cable capacitance which makes it inherently slow. So indeed, some voltage level converter IC is probably the way to go.But between which voltage levels are you converting? Both sides seem to have 3V3.When interfacing between different different logic families, you also have to consider their voltage levels carefully.Extra IC's for voltage level conversion can often be avoided by coosing your logic families carefully, but of course you don't have that luxury when interfacing with existing circuits.