Very low frequency (few KHz) PLL? - Page 1
Forum section: electronics / projects

author: saratoga
author_rank: Newbie
timestamp: January 09, 2023, 08:35:20 pm
content: I have been using the si5345 to generate a 100 MHz clock for an ADC from a 12 KHz mechanical oscillator with the goal of having a fixed number of ADC samples per cycle. The cycle trigger on the mechanical device is also a little jittery, so I regenerate it from the si5345 and use that to trigger the ADC synchronously with the mechanical oscillator. The si5345 works really well for this since it has a zero delay mode and so always has a fixed delay (so the trigger to the ADC is always at the same relative time of the cycle). I don't really need the extremely low jitter for an ADC, but it doesn't hurt.Recently I got a 7.9 KHz oscillator, which is a little flakey with the si5345 (minimum frequency of 8 KHz). It works, but has a little trouble locking. Doubling the 7.9 KHz to 15.8k would work, but it is also not ideal since the duty cycle is not quite 50% and the falling edge jitters a lot relative to the rising edge, so I'm a little hesitant to try that rather than just pick a better PLL. However, after a lot of digging around I'm at a loss for an alternative part for lower frequencies that I can actually buy. I don't even need zero delay, just deterministic delay and the ability to lock down to at least 7.8 KHz. Is there some family or class of parts I'm overlooking?

author: moffy
author_rank: Super Contributor
timestamp: January 09, 2023, 08:47:35 pm
content: 74HC4046.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 09, 2023, 09:08:35 pm
content: +1 for the 4046. It is at least a chip one should consider and know about. The VCO part as a relaxation type is not very stable though. The hard part is the PLL filter anyway and that is usually not part of the chips.If this works well depends on the system. Normally mechanical resonators tend to be relatively high Q and thus relatively stable. The read out may however by noisy and in some cases there could be coupled modes that can cause 2 close by resonances that can look ugly. In this case a PLL would not help - more like a mechanical redesign needed.If the oscillator is not very stable one could also build the oscillator in combination with the PLL chip. The "PLL" would drive the resonant system and regulate for a fixed phase between the drive and feedback. So there is no more separate PLL clock and oscillator clock - just 1 combined oscillator.

author: Benta
author_rank: Super Contributor
timestamp: January 09, 2023, 10:25:50 pm
content: I strongly doubt that the 74HC4046 VCO could generate 100 MHz.But the PFD (phase-frequency-detector) would work fine for this application, if you can live with around 50 ns jitter. Then, you just need a 100 MHz VCO (MC100EL1648?) plus a 100 MHz, 14-bit counter.All of it possible, but somewhat complicated.Honestly, I think your frequency-doubler idea is the best bet.

author: moffy
author_rank: Super Contributor
timestamp: January 09, 2023, 10:34:51 pm
content: Quote from: Benta on January 09, 2023, 10:25:50 pmYeah, good point, overlooked the 100MHz clock needed. But you could use the 4046 to double the 7.9kHz(i.e. divide by 2 counter out of VCO to the phase detector) then use the si5345 to lock onto the 15.8kHz output of the 4046 VCO. The 4046 filter can be quite narrow and help eliminate the mechanical jitter.

author: Benta
author_rank: Super Contributor
timestamp: January 09, 2023, 10:54:58 pm
content: Yeah, a 74HC4046, an opamp, a 74LVC1G80 and a handful of passives would work.This might help:

author: saratoga
author_rank: Newbie
timestamp: January 10, 2023, 02:53:46 am
content: The frequency doubler was my first thought too, but it has some issues. Besides the jittery falling edge which could be managed, it'd be 50/50 each time if it locked to the rising or falling edge of the oscillator, which would mean the ADC trigger would have a 50% chance of being wrong each time. I would need to design some kind of circuit to check which edge it had locked to and then try again if it was wrong.I also tried out the Si5326 (minimum input of 2KHz) and while it works, the phase delay of the generated clocks varies randomly ("Input to output phase skew after an ICAL is not controlled and can assume any value"), so it has the same issue as the doubler only much worse since it can take any value, not just 2.

author: KrudyZ
author_rank: Frequent Contributor
timestamp: January 10, 2023, 03:45:28 am
content: How about using an MCU?Use a VCO controlled by a filtered PWM output from the MCU to generate your 100 MHz. Divide by two or four and use that as the clock for the MCU.Use a counter to measure the low frequency clock's period and run a sw PID loop to adjust the VCO to always get the same counter reading.

author: moffy
author_rank: Super Contributor
timestamp: January 10, 2023, 05:24:56 am
content: Quote from: saratoga on January 10, 2023, 02:53:46 amUsing the 4046 as a times 4 PLL multiplier, divide your 7.9kHz by 2 on the leading edge (this will give 50% duty cycle and get rid of the jittery falling edge) and lock the 3.95kHz signal to the divide by 4 output of the 4046 using the XOR mixer(gives the best noise performance). If you use an integrator with some lead for the loop filter the divide by 4 output of 4046 will be 90 degrees phase shifted with respect to the 3.95kHz signal, which will be 180 degrees to the original 7.9kHz signal. Use the 15.8kHz signal from the 4046 VCO as the input clock to the si5345 and scale up to 100MHz. All you need to do is then create an index pulse at the start of each 7.9kHz cycle to tell when the first ADC cycle is.

author: CatalinaWOW
author_rank: Super Contributor
timestamp: January 10, 2023, 05:32:31 am
content: Quote from: moffy on January 10, 2023, 05:24:56 amI had typed this almost word for word and when I hit the post it warned me to read a recent post. It is a solid solution.

author: moffy
author_rank: Super Contributor
timestamp: January 10, 2023, 05:44:49 am
content: Quote from: CatalinaWOW on January 10, 2023, 05:32:31 amI would say "Great minds think alike." but I doubt my own soundness. But I agree it should work.

author: Benta
author_rank: Super Contributor
timestamp: January 10, 2023, 05:04:03 pm
content: Just use the PFD2. This will lock on the leading edge, no need to worry about falling edge jitter. And no need to pre-divide by 2 either.

author: David Hess
author_rank: Super Contributor
timestamp: January 10, 2023, 05:10:32 pm
content: Quote from: moffy on January 10, 2023, 05:24:56 amI was also thinking of multiplying the reference but instead of a PLL, injection lock a higher frequency oscillator to the 7.9 kHz reference which should be simpler than a PLL. Tuning of a low frequency LC oscillator would be difficult however but perhaps a gyrator based oscillator would be good enough. I wonder if there is a switched capacitor based oscillator which could be used.For applications where a truly stable low frequency is required, besides DDS and dividing down the output of a crystal oscillator, sometimes the outputs from two slightly different crystal oscillators are mixed to produce a low frequency output.

author: gf
author_rank: Super Contributor
timestamp: January 10, 2023, 05:38:08 pm
content: Quote from: David Hess on January 10, 2023, 05:10:32 pmIf I understand the the OP correctly, then the aim is not to generate a low frequency, but rather an integer-N synthesizer which generates a ~100MHz clock from a 7.9kHz reference.

author: Benta
author_rank: Super Contributor
timestamp: January 10, 2023, 06:00:00 pm
content: Quote from: gf on January 10, 2023, 05:38:08 pmYou understand correctly, but do not understand that the 7.9 kHz is too low. Thus the need for doubling it.

author: mawyatt
author_rank: Super Contributor
timestamp: January 10, 2023, 06:03:15 pm
content: Quote from: David Hess on January 10, 2023, 05:10:32 pmWe utilized a similar technique low ago and eventually were allowed to publish something that ended up also in custom lab test equipment to get very accurate and low phase noise (jitter) low frequency waveforms. Much later published in EDN and made front page of the 92 and 93 Design Ideas booklet.The idea originated with the need for a very stable but controllable low frequency sweep waveform for an Optical Phase Modulator which produced a Laser Frequency Shift based upon the Serrodyne principle (patent 5339055). Two very stable crystal oscillators were used. One was fixed, the other a Voltage Controlled and the Sweep Waveform frequency was the difference frequency between the two oscillators, works very well indeed!!One could use 74AC or faster logic and likely produce better results than the old 74HC logic shown.Best,

author: David Hess
author_rank: Super Contributor
timestamp: January 10, 2023, 08:00:49 pm
content: Quote from: gf on January 10, 2023, 05:38:08 pmThat is right, but if the reference was multiplied to a slightly higher frequency, then the existing PLL could be used. The problem is that 7.9 kHz is slightly too low for the existing PLL.

author: buta
author_rank: Contributor
timestamp: January 18, 2023, 02:53:10 am
content: Can si5345 generate 100 MHz and 15.8 kHz or 31.6 kHz (7.9 kHz x 2 or x 4) ? Then divide by 2 or 4, the 7.9 kHz signal should be 50/50.

author: BrianHG
author_rank: Super Contributor
timestamp: January 18, 2023, 03:36:07 am
content: If you are using an FPGA with 2 PLLs in it, you can synth lock to any low frequency reference to generate a 100MHz clock for your ADC.Also, if the signal you feed your ADC is below ~20Mhz, you do not need to PLL lock and you can software emulate the clock triggering alignment on the data output, though this takes a lot of gates.Read this thread about generating a video sampling clock from a H-sync : (This was a trick which allowed us to clock lock onto a 15khz reference sync with a jitter of +/- ~2ns, to generate a 100MHz clock, this can be improved to +/- 0.5ns with a Cyclone of Max FPGA from Altera.)https://www.eevblog.com/forum/projects/modern-equivalent-of-74hc4046-pll/By page 2, I illustrate how to manipulate the FPGA's PLLs to lock onto the 15khz sync and make the video sampling clock roasting the Jitter performance of the 74HC4046. Scope shots were done and source code is posted. Sample clock was perfected by page 4 and 2 of the FPGA's differential inputs were used as a 2bit ADC input making the chip an all in 1 solution. Though, the MAX10 fpga also has high speed ADC inputs.Links to notes on how to make a full scaler, sampler, lcd driver in page 4 of the above link. Source code are in those links too.

author: BrianHG
author_rank: Super Contributor
timestamp: January 18, 2023, 05:02:02 am
content: Sorry, I missed that your 12khz source was jittery. I don't know how you could generate a clean 100mhz from that, but if your goal is to get a clean number of samples between an averaged 12khz cycle. Both high speed MCUs with ADCs and FPGAs can do this via software / firmware.Sampling and re-sampling the data based of multiple rounded cycles of your 12khz source, IE a software simulated PLL is really powerful as you can set deliberate high and low cutoff response frequency ranges from your 12khz source.If you are looking at sampling signals from a helical or lidar scanner, unless you are generating the motion and just being a slave to someone else's raw sensor, to re-capture any quality, you may be stuck with low quality or doing it the hard way I mentioned above.