3 bit address dual port memory - Page 1
Forum section: electronics / beginners

author: fabiodl
author_rank: Frequent Contributor
timestamp: February 04, 2021, 03:17:54 am
content: What is the easiest/cheapest way to realize a 3 bit address, 8 bit data dual port memory? Actually one port only does writes,and the other only reads.The first thing which comes to mind is using a cpld, but I wonder if there are more specialized parts / tricks commonly used.

author: fabiodl
author_rank: Frequent Contributor
timestamp: February 04, 2021, 03:50:20 am
content: Indeed, an ice40 may be a nice idea. However, since anything else is 5V, I'd need level translators though (let's say some 74HCT245 or SN74CB3T16211).(this was recently discussedhere)

author: CaptDon
author_rank: Super Contributor
timestamp: February 05, 2021, 02:17:46 pm
content: It may seem wasteful, but there are 1kbyte dual port memory devices and they are not very expensive. They are a bit big having the data and address lines on both sides, I think maybe 48 pin DIP. It is a bit tough to get true 'write while read' or 'read while write' but I have done it. I had a pc board with 8 8-bit latches. The outputs were always enabled as was the chip selects. The write line was decoded by which latch I wanted to write to (write enable feeding the 'gate' pin and latch address feeding the normal address pins of a 74154) and the data input side of the latches were common. On the output side of the latches the outputs were always enabled and the 8 data lines went to a one-of-eight decoder. There were 8 decoders, one for each bit. All eight D0's to one decoder, all D1's to a decoder, etc. etc. Then I would feed the 3-bit 'read' address to the decoders to select which input data line was placed on the output of the decoders. This is nearly identical to what you are trying to accomplish and probably could be programmed into a CPLD but I would wonder about the synchronicity of the data transfers through the VHDL layout? I never got beyond Xilinx 'Schematic Capture' and all my CPLD work was done as if I was using TTL building blocks. In many cases you can pick-and-place actual TTL part numbers into your layout. I seldom got bad data readouts on my homebrewed dual port system. If there was an exact instant where you were reading as the bits were toggling from a write to the same latch you could get a cross sampling of old and new bits but the coincidence had to be so close since the bit toggle happened so quickly. I can't really say I ever saw a corrupted read!!!

author: Benta
author_rank: Super Contributor
timestamp: February 05, 2021, 03:30:45 pm
content: Quote from: fabiodl on February 04, 2021, 03:17:54 amSounds more like a FIFO to me.

author: Druzyek
author_rank: Contributor
timestamp: February 06, 2021, 03:49:49 am
content: How about chaining some 74HC670s?

author: fabiodl
author_rank: Frequent Contributor
timestamp: February 10, 2021, 08:36:16 am
content: Not a fifo, because each port can access in any random order.Druzyek's part is perfect,thank you!

author: RoadRunner
author_rank: Frequent Contributor
timestamp: February 10, 2021, 02:00:01 pm
content: Quote from: Benta on February 05, 2021, 03:30:45 pmQuote from: fabiodl on February 10, 2021, 08:36:16 amThey are called pseudo dual port ram in lattice documentations

author: jmelson
author_rank: Super Contributor
timestamp: February 10, 2021, 04:59:38 pm
content: Quote from: fabiodl on February 04, 2021, 03:50:20 amXilinx 95xxXL are 5V tolerant. You probably need more than the smallest version, as you need 64 FFs. But, this can all fit in one package.Jon

author: CaptDon
author_rank: Super Contributor
timestamp: February 10, 2021, 05:52:05 pm
content: The Xilinx solution is probably a good way to go and even more so if you can do VHDL/Verilog. I do the clumsy Schematic Capture but it works for me. I would suggest you go with CPLD and not FPGA. A CPLD knows what it wants to do on powerup with no delay, an FPGA is usually supported by a serial EEPROM or flash part and the FPGA must 'educate' itself on power up. It is just a dumb brick until the program/load cycle is complete. I love the flexibility of CPLD's over hardwire but there can be synchronicity problems if the data stream is not related to the master clock and you are trying to steer short transitional pulses or very short random pulses.

author: fabiodl
author_rank: Frequent Contributor
timestamp: February 11, 2021, 01:27:56 pm
content: Actually now, as I have no parts at hand, I am using a lattice cpld.The code is trivialCode:module dpram(aa,ad,awr,ba,bd);input [2:0] aa;input [11:0] ad;input awr;input [2:0] ba;output [11:0] bd;reg [11:0] storage[0:7];always @(negedge awr)storage<=ad;assign bd=storage;endmodule