High-Speed PCB layout challenges - Learning the dark art the hard way. - Page 1
Forum section: electronics / projects

author: rx8pilot
author_rank: Super Contributor
timestamp: April 19, 2017, 10:37:27 pm
content: I have finally arrived at some of my first practical high-speed PCB layout. This journey started about a year ago after winning the Keysight Test to Impress contest where I found myself with a very unique opportunity to learn a whole new set of skills. The last year was spent reading about high-speed digital and RF systems and saving money for the mandatory 6Ghz active probes to actually use the new scope to it's full potential. Well....I got the 1st probe a couple of weeks ago so here we go. I figured this is a good place to get me feet wet with the unique and detailed challenges in designing for high-speed signals. The industry is going toward 12Gbps serial data over coax with BNC connectors - crazy right? BNC connectors being tested out to 18Ghz.The first project is only an experiment in signal integrity. It is a simple 1x2 serial digital distribution amplifier that will run up to 6Gbps. It has a 75 ohm single-ended input on BNC and 2 outputs that drive 75 ohm coax on BNC. Internally the signals are moved around on 100 ohm differential lines. The chips are Gennum (now Semtech) that handle EQ, clock recovery, and line driving. The assumption is that I would make a number of beginner blunders, so I wanted to get my first PCB done even before I had any real confidence. I believe that will speed the learning curve for me to build some intuition while learning what I need to learn to actually be successful.Cable EQ: Semtech GS6042http://www.semtech.com/broadcast-video/equalizers/gs6042/Re-Clocker: Semtech GS6151http://www.semtech.com/broadcast-video/reclockers/gs6151/Cable Driver: Semtech GS6080http://www.semtech.com/broadcast-video/cable-drivers/gs6080/Semtech does not have too much detail on layout examples so I decided to just take a stab at it and see how far I have to go. PCB's are cheap and there is a lot of value in learning how far I have to go. The goal was to use standard FR4, 1oz, 4 layer, typical stackup with two 2116 prepreg and a .040" core. All signals on the top layer, layer 2 GND plane, layer 3 power, layer 4 GND2 with some low-speed control signals. The manufacturer indicates FR4 is no problem, especially with such a compact layout, assuming it is done well. The PCB is not impedance controlled by manufacture, so the trace impedance is only an estimate.The schematic is attached along with the layers 1, 2, and 3 of the layout. One of my biggest unknowns is how the differential signals should be handled and just how sensitive they will be. I used an online calculator to determine the trace width and spacing (with no way to simulate it). There are 2 differential traces on this design and they are AC coupled to deal with the differing DC bias between the chips. Was scratching my head on the proper placement of the caps (0402). I initially blended the trace into the width of the cap, but then just used a straight trace. Some online conversations suggested putting the caps close to the TX, others the RX, and still others said it did not matter since the impedance of the cap is so low at multi-ghz frequencies. I put them in the middle. The short diff-line is about 10mm total - 5mm on each side of the AC caps. The longer diff-line is about 19mm total with the AC caps in the middle.While the chips are capable of 6gbps data rate, I only have a 1.5gpbs signal generator on my bench at the moment. I assembled the first PCB yesterday, and to my surprise - it worked. It is not, however, working all that great. I made some quick measurements to get a sense of what was happening. The receiver is easily able to decode the data but there are clearly some impedance issues ringing the signal. The input measurement (before the equalizer) shows the expected amplitude and eye quality at the input of the GS6042. The differential output shows a rougher eye than I was hoping for. The output of the reclocking GS6151 is similarly distorted. Both have the expected amplitude so I guess the internal terminations are doing the right thing. I am not really sure what the most likely source of the distortions/reflections is. the AC caps? Return current problem? Something else?This is such a steep learning curve, but is also a lot of fun and very fascinating. Thanks in advance to anyone willing to offer some insight and critiques. I have thick enough skin to deal with harsh criticism as long as it is specifically targeted at building an understanding of this topic.

author: tggzzz
author_rank: Super Contributor
timestamp: April 19, 2017, 11:25:49 pm
content: A few thoughts, which are worth what you pay for them...You have 100ps transitions, corresponding to 20mm on a PCB. Your lines have to be terminated correctly. I presume the termination is inside the receiving chip.You have ~200ps ringing period, corresponding to ~10mm of unterminated (or poorly terminated) line; seehttp://www.edn.com/electronics-blogs/all-aboard-/4438918/What-is-the-ringing-period-on-an-unterminated-line--Rule-of-Thumb--26The impedance of the capacitors should take account of their inductance as well as their capacitance. Personally I would put them at one end, so all impedance variations are concentrated in one place.Which online calculator did you use, which models, what parameters, and what results? Many models don't have any "flood" groundplane nearby on the signal layer. If coplanar waveguide, I would expect to see many vias along the surrounding flood, providing the "fence" to the groundplane.Have you done a quick-and-dirty spice model of the outputs, transmission line and capacitors, and inputs?Did you consider having many more via connections "stapling" the flood to the groundplane all over the board?

author: rx8pilot
author_rank: Super Contributor
timestamp: April 20, 2017, 12:23:49 am
content: Quote from: tggzzz on April 19, 2017, 11:25:49 pmYes, the terminations are internal to the chips.I used:http://www.multek.se/engelska/engineering/pcb-structures-2/differential-microstrip-impedance-calculator-2With the settings in the attached image. At my early learning stage - I don't have enough understanding of whether or not this is good information.I have not done any SPICE sims and honestly don't know how to model this one.I have seen some other boards with ground stapling, but it seemed more common on longer traces. I guess it would help with any trace that is considered a transmission line? Do you suppose the top layer ground flood is a problem? Especially since it is not stitched to the ground plane.I am going to take a quick look to see if I can pull off a micro-bodge of the caps. It won't be anything like ideal, but I am curious how sensitive the placement is.

author: lem_ix
author_rank: Regular Contributor
timestamp: April 20, 2017, 01:22:52 am
content: The ground pour should probably be further away, if I remember correctly for a microstrip for example it was like 2-3 times the width of the controlled trace but don't take my word on it. Tggzzz linked an article by Eric Bogatin, if you search for more articles by him(Bogatin's rules of thumb) on EDN you'll find some simulations and recommendations. The pour stitching is there to reduce the inductance between the planes which is definitely significant for the frequencies you're playing at. There was a rule of thumb for the "stitching frequency" aswell. Doing my first rf board soon, so many things to consider

author: rx8pilot
author_rank: Super Contributor
timestamp: April 20, 2017, 01:32:09 am
content: A quick observation....I measured the ringing period on both of the differential pairs at the coupling capacitors, they both have the exact same period of 188ps. The short one is about half the length of the longer one so I would expect the ringing frequency to be different. I confirmed the termination schemes in the datasheets to make sure there was not an option to disable.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 20, 2017, 01:38:49 am
content: Quote from: lem_ix on April 20, 2017, 01:22:52 amI should take a look at Eric Bogatins other articles - I just read the one linked above. I always like the rules of thumb to help me get oriented in the general direction of success. Good luck on your first board. I am glad I did a PCB early on, I think it will be very helpful when I am neck deep in a signal integrity book by offering some real context to concepts.Photo is from a commercial device using similar, but somewhat older chips. The diff pair is surrounded by a large, un-stitched ground plane. The trace length is substantially longer as well. Still reading, pondering......

author: KE5FX
author_rank: Super Contributor
timestamp: April 20, 2017, 03:10:20 am
content: Those expanses of ungrounded copper scattered all over the place are definitely a problem. If you don't have good simulation capabilities, then whether they act as capacitors, antennas, or other unwanted circuit elements is a matter of luck. You should use vias -- lots of vias -- to ground those islands to a solid plane immediately underneath. It should look more like this:Vias are fun. They're your friends. They're free. We like vias.They aren't without parasitic properties of their own, of course, but you have bigger problems with all that unattached copper lying around.And yes, Bogatin's book is quite good... definitely put that one on your list. Henry Ott's latest edition, too, maybe?Finally, study board designs from places like Tektronix and HP/Agilent/Keysight, not whatever clown shop did the one in your photograph. (Exception: they might be stitching their ground planes together with blind vias.)

author: rx8pilot
author_rank: Super Contributor
timestamp: April 20, 2017, 06:07:00 am
content: Quote from: KE5FX on April 20, 2017, 03:10:20 amI cleaned up a few things, moved the AC coupling caps close to the TX pins, blended the traces into the 0402 footprint, fixed a few PDN issues, fixed an input termination mistake, and of course added a pile of guard vias.Still trying to figure out if the differential pairs need more room to the top ground pours to maintain the 100 ohm impedance. Thanks for the input so far.

author: hendorog
author_rank: Super Contributor
timestamp: April 20, 2017, 08:10:38 am
content: These comments are based on my experience fiddling with GHz circuits without really knowing what I'm doing. As that is what you said you are doing I feel qualified to commentI would have broken that circuit down into simpler modules first - e.g. connect eval boards together and use that as a reference to compare your own design with. Make single chip boards first and string them together and try to match the eval boards.Can you remove the downstream chip, terminate the differential pair with a low inductance 100 ohm resistor and then re-test. Then play around with the caps and get an understanding of what is going on.Other things:Vias have already been covered, but KE5FX (guru) mentioned 'islands'. i.e. _areas_ of copper should also be grounded by multiple vias, not just the microstrip lines. If there are small areas that are hard to put a via in then remove the copper pour there.One of the differential pairs takes a 90 degree turn, so the path length can't be the same for both lines in the pair unless you are doing something clever to correct for that. Maybe the difference is too small to matter.The width of the microstrip lines to the two output connectors is not the same.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 20, 2017, 08:22:18 am
content: Top side ground is not a problem, the impedance is just lower (for a given trace width). It's called coplanar waveguide (CPW).It does need to be stitched. It looks like there's about half as many vias as there should be.Tim

author: Twoflower
author_rank: Frequent Contributor
timestamp: April 20, 2017, 08:28:37 am
content: From the HS-Boards I see in the past I never saw GND pour below the devices. This could easily create jumps in the impedance. Also the inductors might have some playground for resonances.If possible use smaller R/C/Ls that don't change the tracewidth for the pad.I also would reduce the stubs for the biasing. Place the pad of the resistor directly on the HS-trace. Also try if you can place the parallel L-C combos closer together.The length adaptation between U2 and U3 must be as close as possible to where the mismatch appears. This reduces the time the signals (as they're coupled) run mismatched on the PCB. And if possible do just one meander.Also U2->U3 there's no ground-plane at parts of the trace. That most likely will hurt a lot.Also the design shows on some places no GND pour around the HF-Parts (lower part of the board).

author: AndyC_772
author_rank: Super Contributor
timestamp: April 20, 2017, 08:29:54 am
content: Talk to Lee Ritchey at Speeding Edge, he's the guru for high speed PCB design and layout. Get onto one of his training courses if you can, they're brilliant.http://speedingedge.com/

author: lem_ix
author_rank: Regular Contributor
timestamp: April 20, 2017, 10:46:11 am
content: Should probably recalculate the impedance with a different model or move the pour. No idea how much of a difference this makes in practice, hopefully someone with more xp can comment.Some commercial tool for Differential surface coplanar waveguide with groundMaybe someone knows a free calculator for this.

author: AndyC_772
author_rank: Super Contributor
timestamp: April 20, 2017, 11:24:49 am
content: Saturn PCB toolkit?

author: lem_ix
author_rank: Regular Contributor
timestamp: April 20, 2017, 11:47:12 am
content: Think it only has standard edge coupled microstrip under differential pairs (no top gnd). There is coplanar wave but not differential. Or am i missing something?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 20, 2017, 12:57:54 pm
content: Roughly speaking:Oh, let me abbreviate microstrip = MS, and differential = D.If you take the ratio of Z_CPW(d) / Z_MS(d), that will be the amount of impedance reduction due to the top side ground fill.Set d = 2*w + s, the width of the pair. (Gap D, height H, etc. all normal as shown.)The reduction is usually 10-20%, i.e., the ratio is about 0.8-0.9.Now apply half this ratio to the normal impedance of one trace in the DMS result. That is, "half" in the percentage sense, or "half" in the logarithmic sense (i.e., use sqrt(ratio), or percentage/2). That will be close to the impedance of DCPW.This method isn't based on anything rigorous, just a wave-of-the-hands estimation that should be more accurate than taking the extreme of either case (i.e., CPW for single traces and assuming DCPW has the same normal impedance; or using DMS and outright ignoring the contribution from ground fill).A more accurate answer seems unlikely to be necessary, given the gross tolerances we're concerned with in the first place (typically 20%for controlled impedancefabs).Tim

author: tggzzz
author_rank: Super Contributor
timestamp: April 20, 2017, 01:51:30 pm
content: Quote from: rx8pilot on April 20, 2017, 12:23:49 amIt is often worth using multiple calculators, since they sometimes have different situations (e.g. coplanar waveguide) and even different equations.As for Spice sims, you can always use them for a simplified situation. In this case I would have:a signal source with internal resistance Z0=50ohms, risetime 100psa length of perfect transmission line, Z0a capacitora length of perfect transmission line, Z0a terminating Z0And just see what you can see.You won't get the same results that you will see on the PCB, but you will get a feel for whether you are in "here there be dragons" territory.I'd then make a more sophisticated capacitor model, including parasitic inductances and capacitances - you could even nick them from resistors of the same size. There are suitable starting points in Vishay app notes.You should also add in the parasitic capacitances in the receiver (and maybe even inductances). You should be able to get these from the data sheet and/or IBIS models.

author: TiN
author_rank: Super Contributor
timestamp: April 20, 2017, 02:02:33 pm
content: What is your CAD? Isn't there integrated tools for differential pair routing?Currently it looks like you have manually done everything, and that might be more effort than should be. When routing HSD you need to maintain running skew (phase) and impedance.6Gigs is not much.If you want to go bit extreme - find somewhere dead not so old motherboard (one with PCIe Gen3 at least) and sand layers on my one, to see some good ideas.Modern USB 3.0/3.1 routing examples can be helpful too, and DEZ is around similar what you have. Make sure you have correct termination (enabled and set properly if it's onchip, populate termination components if it's external).Pay attention to coupling mode, sometimes differential are AC coupled, sometimes DC coupled, depends on your design. Try to avoid any reference plane voids under high-speed routing, maintain return currents.Vias are friends, but too much friends can ruin the party, so need to be careful, not to turn your planes into a swiss cheese.If you can give us your exact stackup (I guess 4 layer PCB?) and your PCB material, I can help to rougly check line parameters.

author: dmills
author_rank: Super Contributor
timestamp: April 20, 2017, 05:20:14 pm
content: One thing to watch with SDI which I am guessing you are playing with (Genum, 12G, 75 ohm, BNC, gives the game away) is that it does have pathological conditions so those caps typically need to be **MUCH** bigger then you would really prefer (4.7uF springs to mind for some reason, tends to make for interesting parasitics so place the caps right next to one end of the line is favourite).Why they did not do 8b10 or 64b66 or something similar is a legacy issue from the days of 270Mb SD that somehow never got fixed.My favourite approach is to observe that tracking you don't have does not give impedance problems, there is something to be said for getting the silicon close to the connectors and close together to minimise the problems.Going for a thin layer spacing is also helpful as is using high Tg FR4 (It tends to be better behaved).Regards, Dan.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 20, 2017, 06:00:30 pm
content: Quote from: dmills on April 20, 2017, 05:20:14 pmYes - this is HD-SDI as defined by SMPTE. Yes, the ac coupling caps are recommended to be 4.7u.Quote from: TiN on April 20, 2017, 02:02:33 pmSadly - EAGLE CAD is the tool. The support for differential routing is comedy gold - useless and hilarious. My strategy is to manually fight the marginal routing tools and then measure the length. If I end up going further down this road - Eagle is out. I can't imagine doing this type of design regularly with it.Quote from: TiN on April 20, 2017, 02:02:33 pmThe stackup is 4 layer, .062, FR4, 1oz. 2116 prepreg with .040" core. (chart attached as image). I did not specify impedance control and curious if the fab house just uses whatever prepreg/cores they had that day (PCBway, cheap-o service). In a production world, I wonder if this type of design will only see success with exotic high-speed dielectrics and impedance control. It makes a significant difference in price over FR4.Quote from: T3sl4co1l on April 20, 2017, 12:57:54 pmCurious if there is any practical reason to have the diff pairs setup as a DCPW at all. Do you suppose it will simplify the challenge to just lose the top ground fill (around the differential pairs)? I dug up some other designs using the same signals and chips at 12gbps and they have isolated diff pairs and use CPW only for the single ended 75 ohm. With that in mind - if a CPW configuration can improve the signal integrity in the long term, I will stick with it and deal with the learnig curve.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 20, 2017, 07:44:13 pm
content: Maybe this layout will have easier to predict the behavior of the differential signals?

author: Pitrsek
author_rank: Regular Contributor
timestamp: April 20, 2017, 08:18:39 pm
content: Quote from: AndyC_772 on April 20, 2017, 08:29:54 amWholeheartedly agree!For micro strip calculations I use TNT field solverhttps://sourceforge.net/projects/mmtl/files/You can sweep variables, see how much it moves with spacing, width, er...If you bother with measuring your material beforehand, it's actually very capable/accurate. Beware of asymmetry ratio problems(see manual). Another free field solver ishttp://openems.de/start/index.php,but i have not tried it yet. Actually I received boards today 46.5R, caclulated for 50. In a rush job prototype service(absolutely not "controled impedance"). It's not spectacular, but I can live with it. Er from manufacturer spec sheet, I did not made my own material specification this time.Biggest problem is getting right numbers from the PCB vendor and If you can trust them that they'll use same stuff. IMHO it's well worth spending time and money to make some test coupons to measure er/ verify your microstrip design. Actually it's a very good idea to put test micro strip on every pcb, so you can verify that your board is manufactured properly. If you are not space constrained, I very much recommend it.I don't think your BNC footprint is maintaining 75R.https://www.smtnet.com/library/files/upload/optimizing-bnc-pcb.pdfAlso check for stack-up - if it is really what you specified. Problem with controlled impedance traces on prepregs is that the thickness is quite variable. It depends on pcb processing and pcb itself(how much resin is going in between traces). You need your fab house to tell you how thick the prepreg will be in the end. Or you can design your design over core - there is no curing, thickness is precisely defined (compared to prepreg). Furthermore, if your trace is on core burried inside of the pcb, copper plating thickens is also very precisely defined. If you route on outside(top/bottom), you get thickness variance due to plating (a LOT of it actually). So if your trace design is sensitive to copper thickness this is something to keep in mind. Also having close track/plane spacing(thin prepreg) makes your design very sensitive on track width - so under etch/over etch hurts... If you increase your spacing/make your tracks wider, it's way better(relative change of width and thus impedance change is way smaller).You need to be able to measure it, otherwise you are just poking in with a stick, not really knowing what are you doing. Any chance to test it on TDR/VNA?With your high speed scope and some RF generator you might be able to to "check it", it won't be really accurate, but better than guessing.https://www.google.cz/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahUKEwj4jPW87LPTAhUBfRoKHdRwBVkQFggoMAE&url=http%3A%2F%2Fwww.edn.com%2FPdf%2FViewPdf%3FcontentItemId%3D4435822&usg=AFQjCNGN-cfl0fUGHrbISBJC9srE5y2YOQ&sig2=SDGr3hhWfir7C_7K3lld6g

author: rx8pilot
author_rank: Super Contributor
timestamp: April 20, 2017, 11:23:27 pm
content: Quote from: Pitrsek on April 20, 2017, 08:18:39 pmInteresting tool, I will check it out. I just downloaded Sonnet Lite and Saturn toolkit to have a look around.Quote from: Pitrsek on April 20, 2017, 08:18:39 pmLooking into that one.....I suspect it will prevent countless re-spins if I actually do it.Quote from: Pitrsek on April 20, 2017, 08:18:39 pmI could go with a controlled impedance PCB and let the fab do the TDR on coupons they generate. As for T&M, I am very limited in both equipment and the delicate skills to use them. When I first decided to go down this path, I was hoping to get started at bandwidths that were attainable as a business experiment. The problem is that in the TV industry 1.485gbps has been standard and 3gbps was the fancy high-speed option. 3Gbps serial data is now considered slow with 6gbps quickly becoming normal. 12G is already becoming a standard thing even though there is not yet much use for it. In the end, I need to be willing and able to design with 12G serial IO. That is like drinking from a 6inch fire hose. I was looking at VNA's and thinking that I could get somewhere with an older 6Ghz model with various used eCal, cables, and fixtures. That would not be helpful for long before I needed a 20Ghz system to effectively design clean 12gbps IO. At those rates, the test equipment, calibration, fixtures, and skills are quite a serious journey. The cost of everything skyrockets. The precision needed for success skyrockets.To finance that education and test gear, I am hoping to get through some relatively simple products that I can integrate into my existing products that are 6gbps max capable. My only real option is to make solid guesses based on simulation-intuition-best practices-online calculation, and expect a number of re-spins to get into spec using the only high-speed tool I have - an oscilloscope. The good news is that the Keysight scope has an excellent color graded eye application and jitter analysis. It does not tell me all that much about what exactly is wrong - but at least I can see if it is right or wrong. With that in mind, I did contact Samtec and they are able and willing to help with tests, footprint design, etc. They have a fully configured lab for practical testing. However much they charge for that, it will be a LOT less than me buying the gear and hacking through a long and very challenging learning curve. If that actually happens, I suspect I will learn a whole lot just as an observer of the process. Samtec will not help with the whole system, however, just the connectors.I am looking at the BNC footprints a lot closer now. Samtec engineers will be at a trade show next week where I can meet them.

author: basinstreetdesign
author_rank: Frequent Contributor
timestamp: April 21, 2017, 12:20:40 am
content: My 2cents:Get a copy of Johnson and Graham'sHigh Speed Digital Design, A Handbook of Black Magic. This is one book every engineer designing high speed logic should read cover to cover.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 21, 2017, 12:27:23 am
content: Quote from: basinstreetdesign on April 21, 2017, 12:20:40 amOn the way.....$30 is a no brainer. Thanks.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 21, 2017, 02:08:18 am
content: Something I probably should have done first.......I shaved a PCB and measured the stack up. Not what I asked forThe L1 to L2 dielectric thickness is 4.5mils and I was planning for 9mils. This takes the diff pair from 100 ohms to about 75 ohms. The coplanar ground fill makes that number even lower - perhaps 65 ohms? Anyway, I can add that to the top of the fix list and make sure I get a stackup guarantee on the next one. That is a nasty one, but not too surprising.When I started my EE journey....I never would have guessed that the dielectric thickness being 4.5mils thinner would trash the intended function. It is, however, a lot of fun to slowly see how the magic happens.In addition to the layout fixes so far, I think I will add ENIG finish which has far less thickness variation and hardly costs anything compared to tin plating. I will take another stab at the BNC footprint after I get some guidance from Samtec.Onwards - hope to go for spin 2 tomorrow if possible.

author: TiN
author_rank: Super Contributor
timestamp: April 21, 2017, 04:24:05 am
content: Is you input bandwidth 6gigs too? Maybe replace BNC with something more suitable, like SMA or N, which even cheap ones usually better up to 8gigs or so.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 21, 2017, 04:53:24 am
content: Quote from: TiN on April 21, 2017, 04:24:05 amYes - the input is 6Ghz. The signal is HD-SDI High Definition Serial Digital Interface and is defined by SMPTE along with the connector and its return loss limits. The BNC connector is the only option and the TV business does not seem to have anything different on the horizon. There is a smaller BNC called HDBNC for 'High Density'. That connector is higher performance but regarded as too fragile and not compatible with existing systems. They generally only see deployments in routers and similar fixed infrastructure installations. The BNC manufacturers are killing themselves to go out past 12Ghz with BNC to meet the newest 12gbps standards. Most of them are being tested out to 18Ghz which is really crazy for that type of connector.The connectors I am using are Samtec 'True75' specifically designed for 12Ghz applications. Amazing.

author: TiN
author_rank: Super Contributor
timestamp: April 21, 2017, 05:05:29 am
content: I see, excuse me my arrogance, I had back thought it's SDI, but didn't ring the bell.Here's stackup calculation results with specified and 4.5 mil prepreg thickness.I don't think that huge plane void would help you with anything at these speeds.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 21, 2017, 05:24:19 am
content: Yep, I am curious how much that mismatch would contribute to the observed ringing seen in the circuit the capacitor placement was likely significant contribution as well. It is not clear to me what tolerances I should be hoping to hold.

author: AndyC_772
author_rank: Super Contributor
timestamp: April 21, 2017, 06:26:46 am
content: There's a clue that I don't think has been fully exploited yet. You said the ringing period was the same on both transmission lines (188ps) even though they're different lengths? Surely that must mean that the ringing isn't due to an impedance mismatch, which would result in reflections propagating up and down the transmission line, which would vary depending on the length of the line.How, and where, are you connecting your probe? Could this just be a probing artefact rather than an actual SI problem when the scope isn't there?

author: Pitrsek
author_rank: Regular Contributor
timestamp: April 21, 2017, 06:52:19 am
content: look into TDR, way cheaper than vna, and fo your use probably better suited. you cen tell where is your mismatch located(if you spend enogh money..). I mentioned vna because that is what i have acess to...if you have rf sig gen, you might be able to find a trace resonance with your scope and calculate the impedance. (lastl link from my post, but use gener to sweep the frequency, instead of vna)Its usually possible to have your stuff measure at local uni. Or you can ask here:https://www.freelists.org/list/si-list , if there is somenoe with TDR in your vicinity. actually this is also one of the places where to ask for help with this kind of stuff.if you find out that your design is sensitive to track thickness, you can ask your pcb house to do panel plating, instead of pattern plating. with panel plating, panel is plated before etching, so the thiclness is better controlled.if you have board estate aviable, going with wider trace helps - coupling from the bottom is more dominant compared with coupling from edges, so thickness variance effect is smaller. also there is smaller discontinuity when you connect to capacotor pads.

author: Someone
author_rank: Super Contributor
timestamp: April 21, 2017, 12:10:58 pm
content: Quote from: rx8pilot on April 20, 2017, 11:23:27 pmThats all interesting when you're trying to build accurate RF designs but the nature of serial communications is a little more adaptable. If you're ok with the incremental build and test approach you can start with something much cheaper to validate the final result:https://www.omnitek.tv/ultraand worry about finessing the internal details if and when needed, but either way you'll still end up needing a protocol analyser and source to test against.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 21, 2017, 05:34:40 pm
content: Quote from: AndyC_772 on April 21, 2017, 06:26:46 amTotally - I have been wondering about that. I was measuring on the AC coupling caps since they are so easy to probe relative to the QFN's they terminate into. The only way to get the bandwidth out of the probe is to hand place it on the test points, the solder-in probe heads attenuate way too much. I will try to see if I can get the probe directly on the QFN pads. I would expect the period to change with the different lengths of the transmission line and presumably different impedances from the geometry differences - although I am a beginner in wave theory.

author: MagicSmoker
author_rank: Super Contributor
timestamp: April 21, 2017, 05:45:55 pm
content: Quote from: rx8pilot on April 21, 2017, 12:27:23 amJust chiming in to say this is hands down one of the best EE books I own. It has lots of practical tips on how to make good measurements in it as well. Really can't recommend it enough.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 21, 2017, 05:50:14 pm
content: Quote from: MagicSmoker on April 21, 2017, 05:45:55 pmSweet!

author: AndyC_772
author_rank: Super Contributor
timestamp: April 21, 2017, 08:48:54 pm
content: Quote from: rx8pilot on April 21, 2017, 05:34:40 pmIt's definitely worth reading up on how waves propagate up and down transmission lines, and how different kinds of termination (series vs parallel) actually work. The very short version goes something like this.Suppose you have:- a driver with low output impedance (let's assume 0R for the sake of simplicity), and zero rise time.- a long 50 Ohm transmission line, with no termination, and a high impedance receiver at the far end- logic levels denoted by 0V for a logic 0, and 1V for a logic 1- initial condition is that the entire transmission line is settled at 0V, and we consider what happens when there's a rising edge at the driver.At t = 0, the voltage at the driver output instantly changes from 0V to 1V. The wave begins to propagate away from the driver toward the receiver, at a rate determined by the inductance and capacitance per unit length. Energy is stored in the inductance and capacitance of the transmission line, and while the wave front is propagating, current is drawn from the driver. It's a 50 Ohm line, which means the current being drawn is simply given by Ohm's law, so I = V / R = 1 / 50 = 20mA.At any impedance discontinuity, part of the wave will pass through and the rest is reflected back. Conservation of energy is, of course, maintained.The wave reaches the receiver, where the 50 Ohm transmission line ends, and the impedance of the receiver input is effectively infinite. This means the coefficient of reflection is 1, so all the energy is reflected back toward the driver. The voltage at the receiver becomes 2V, which may even damage the receiver. Current continues to be drawn from the driver. The receiver's input impedance may change, since it's now seeing an input voltage that well exceeds the usual logic '1' level.The wave then reaches the driver, and this time it sees an impedance of 0R. This again means that 100% of the wave is reflected, but the sign also changes, and the negative going edge now propagates back towards the receiver. At the receiver, the voltage drops from 2V down to 0V. The wave reverses direction and continues to travel up and down the transmission line until it eventually dissipates, and the entire transmission line eventually settles at 1V.This, clearly, isn't going to work, and it may even damage the receiver. Bad idea.Now consider what happens if you put a 50 Ohm resistor across the receiver input.At t = 0, the voltage at the driver jumps to 1V and the wave begins to propagate. When it reaches the receiver, the impedance it now sees is equal to the characteristic impedance of the transmission line, so the coefficient of reflection is 0. All the energy in the wave front is absorbed by the resistor and turned into heat, and the driver sources 20mA indefinitely. The voltage at the receiver transitions cleanly from 0V to 1V and all is well.Note also that the voltage at every point on the transmission line switches cleanly from 0V to 1V. You can probe it anywhere and you'll see the same thing.As an alternative, now imagine a 50 Ohm resistor placed in series with the driver, located close to the driver end of the transmission line, effectively making the driver's output impedance 50 Ohms. (Some high speed driver ICs include this resistor, and may allow a choice of values to match different transmission lines).The voltage at the driver output, therefore, is divided down by the potential divider: 50 Ohms output impedance, and the transmission line itself looks like 50 Ohms to ground. So a 0.5V step propagates from driver toward receiver.At the receiver, the incoming wave sees a high impedance, so as in the un-terminated case, it doubles in amplitude and reverses direction. The voltage at the receiver switches cleanly from 0V to 1V, which is good. The wave propagates back towards the driver, where it sees 50 Ohms, and 100% of the wave is absorbed and turned into heat in the series resistor.In this case, current is only drawn from the driver while the wave is propagating. In the steady state (after 2 transit times - there, and back again), no current is drawn, as the receiver is high impedance. So, series termination means less dissipation in the driver. I generally tend to prefer series termination for this reason.But: the waveform you see depends on where you probe. You only get a clean 0-1 transition at the receiver. Everywhere else, the signal goes from 0V to 0.5V, then from 0.5V to 1V a moment later. How long it sits at 0.5V depends on the distance from the receiver.That's the ideal case. Real drivers have finite rise time, real transmission lines are lossy, and even the most expensive probes will distort the signal - so what you see on your scope may not bear much relation to what I've described.Series termination tends to be the better choice for point-to-point connections, where one end is always the driver and one end is always the receiver. Parallel termination is preferred on bidirectional links, because you can simply put a resistor to GND next to each transceiver, and the line will be correctly terminated for both directions. Parallel termination (resistor to GND at both ends) is also better for multi-drop buses which may be driven from any point on the bus, and received at any other point.It might be worth fabricating a PCB with a driver, receiver, a very long transmission line, and sites for series and parallel termination resistors. Drive a square wave, and probe at different places with different resistors fitted to see the effect.Read up on time domain reflectometry (TDR); it works by detecting reflected signals, so any good description of how it works should cover impedance discontinuities and their effect on forward vs reflected waves.

author: MagicSmoker
author_rank: Super Contributor
timestamp: April 21, 2017, 09:46:57 pm
content: A 3rd option for termination that is especially good for single transmitter, multiple receiver buses is to split the termination resistance into two resistors of double the characteristic impedance, one to Vcc and the other to ground. The loading on the transmitter is half that of parallel termination but signal fidelity along the bus is preserved.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 21, 2017, 09:52:34 pm
content: Nice write-up @AndyC_772 - thanks!I am slowly gaining ground on wave behavior. Your write up is exactly what is hard to find in general. A lot of the text and video sources of information dive right on into deep math models where I need to back up and get more of an overview first before getting tangled in the smaller details. I found a few old films that were helpful in setting the stage with physical demonstrations....some real gems.https://youtu.be/j2gOh39IyPMhttps://youtu.be/DovunOxlY1khttps://youtu.be/I9m2w4DgeVkNow, I need to step it up and dig into the details and how the math describes and predicts the behavior.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 22, 2017, 05:50:23 am
content: Quote from: AndyC_772 on April 21, 2017, 06:26:46 amI just did a quick experiment and probed the launch point - the coupling caps - and the receiver. The TX and RX were probed directly on the QFN itself - an interesting challenge. I am now very thankful for the voice commands on the Keysight scope. When you are probing .4mm QFN directly under a microscope without a probe positioner - it's nice to tell the scope what to do. The probe is differential and has adjustable width probe pins. Keysight N2752A. I only have one and wishing I had a second to double probe the circuit and see if the probe is doing much damage as a sanity check.Anyway - I learned that there is little visual difference and I need to actually get a better setup to capture the data and compare more accurately.

author: Dago
author_rank: Frequent Contributor
timestamp: April 22, 2017, 11:36:55 am
content: Quote from: MagicSmoker on April 21, 2017, 05:45:55 pm

author: Someone
author_rank: Super Contributor
timestamp: April 22, 2017, 12:08:50 pm
content: Quote from: rx8pilot on April 22, 2017, 05:50:23 amSimulation says the probing should have a small but measurable impact on the signal, which should be visible clearly in the frequency domain and cause quite different looking eye diagrams at each probing point. Did you have a consistent test signal?

author: Kalvin
author_rank: Super Contributor
timestamp: April 22, 2017, 12:23:50 pm
content: Another very useful and practical book on fast digital signal design: "motorola mecl system design handbook", 4th edition. Lots of oscilloscope pictures pointing out the effects of the PCB design and transmission lines. The book goes very well together with the "High Speed Digital Design: A Handbook of Black Magic".

author: tggzzz
author_rank: Super Contributor
timestamp: April 22, 2017, 02:09:56 pm
content: Quote from: Someone on April 22, 2017, 12:08:50 pmThere's a simple standard technique to see how much a probe is affecting a signal. You add a second probe alongside the first probe, and see the change in the signal measured with the first probe.

author: Kalvin
author_rank: Super Contributor
timestamp: April 22, 2017, 02:51:00 pm
content: The FR4 is not optimal choice for the PCB at gigahertz frequencies and wide bandwidth. The pulses will be distorted due to the frequency dependent dispersion as the different frequency components of the signal travel at different speeds and are attenuated differently (See chapter Layout Miscellany, pg. 286):https://books.google.fi/books?id=MLzPNpJQz9UC&pg=PA286&lpg=PA286The author of the High Speed Digital Design: A Handbook of Black Magic explains different probes and probing techniques:http://www.sigcon.com/Pubs/straight/probes.htm

author: rx8pilot
author_rank: Super Contributor
timestamp: April 22, 2017, 07:07:04 pm
content: Quote from: tggzzz on April 22, 2017, 02:09:56 pmI only have one high-speed probe. They are stunningly expensive with a list price of $5800.I agree FR4 is not the best choice but there is a long term interest in making the design workable in that material. The chip manufacturers have optimized the EQ for FR4 in an effort to keep the BOM cost low. Just about every manufacturer has figured out how to use it with reasonable results. If I move to a higher performance dielectric and also have the low-volume on all parts - I don't stand a chance at being competitive.Goal #1 is to work out a solid i/o on FR4Goal #2 use that general scheme to feed FPGA's reliably to process the data and send it back out.Goal #3 Make all of these skills marketable so I can add them to my business.With goal 3 in mind, I am conscious of learning how to keep costs managed.Sent from my horrible mobile....

author: John_ITIC
author_rank: Frequent Contributor
timestamp: April 22, 2017, 07:58:52 pm
content: Quote from: AndyC_772 on April 20, 2017, 08:29:54 amI doubt Carlos can afford to hire Lee Richey since he (Carlos) is a one-man shop. BUT I can strongly recommend buying the speeding edge books (on speedingedge.com), which discuss all you need to know with regards to PCB design for high-speed power and signal integrity as well as PCB physical design issues like choosing PCB materials, using plane fills to maximize power plane capacitance etc.I have a few high speed designs under my belt (2.5 Gbps PCIe Analyzer and 5 Gbps USB 3.0 protocol analyzer) and high-speed trace routing is not very complex at all as long as one follows some simple rules of thumb:1) Make sure to match trace impedance - reflections will occur at the point where the impedances matches, which causes "ringing" (which in reality are reflections that die out as the reflected energy dissipates after a few round-trips).2) Make sure to properly terminate, without stubs to termination resistors. That means; route past receiver pins and finish trace with terminator. Most HS receivers have built-in receivers these days so a non-issue, often.3) If you cross board layers (top to bottom, for example) using vias, make sure to use ground vias close to the signal transition vias. This allows the return current to jump from the ground plane close to the originating layer to the ground plane next to the destination layer (assuming ground plane under each signal layer, of course). For diff pair, use one GND via on each side. If none are used then the return signal will have to take a long detour on the PCB until it finds some remote GND via, which allows the return signal to transition to the target ground plane. Such long path ads inductance and you'll end up with "ringing" (which is not reflections - reflections look like steps, while inductance looks like ringing, which is exactly why a scope probe with long ground wire causes the signal to appear to "ring" on screen).Also note that proper POWER INTEGRITY Is required for HS design since HS ICs need proper PI design to work reliably. This subject is more complex since it needs advanced software such as Hyperlynx to simulate PI of the various power/ground plane layers. I have done such PI simulations for a few of my customers (on consulting basis) and it becomes more common that modern large ICs souch as SoC's and FPGAs don't work reliably due to incorrectly (under) designed power planes and decoupling capacitor placement. The speedingedge books explain this in detail but so do various app notes from Altera and other IC vendors. Bogatins and Peng Li's books also go into this subject ad nauseum...Make sure to check out Dave's video on PI, too (decoupling caps etc). Use the search button, Luke...

author: hendorog
author_rank: Super Contributor
timestamp: April 22, 2017, 09:01:14 pm
content: GS6042 Datasheet says:"The differential output can beDC-coupledto Semtech’sreclockers and cable drivers, as well as industry-standardCML logic by changing the voltage applied to theVCC_O pin. In general, DC-coupling to any terminationvoltage between +1.2V and +3.3V is supported."VCC_O is 3.3V so you don't need the caps at all, or what am I missing?I reckon there are still copper areas that are flapping in the breeze and need to be pinned down with vias.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 22, 2017, 09:35:35 pm
content: The GS6151 is 1.8v which is why I AC coupled them. It may be software switchable with Gennums oddball interface, but I was hoping to use the default and not count on being able to change the configuration registers.I think that fixing the ground planes and capacitor locations should make a drastic improvement. Meeting with Samtec next week about the BNCsSent from my horrible mobile....

author: rx8pilot
author_rank: Super Contributor
timestamp: April 22, 2017, 09:39:48 pm
content: oh wait..... I see what you are pointing out. Maybe you are correct, I may be able to simplify the caps out of the circuit altogether - getting rid of a bulky disturbance in the force.Sent from my horrible mobile....

author: hendorog
author_rank: Super Contributor
timestamp: April 22, 2017, 09:43:34 pm
content: Quote from: rx8pilot on April 22, 2017, 09:39:48 pmYeah - and I didn't realise it when I posted but you can connect VCC_O to the 1.8v as it is just for the outputs.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 22, 2017, 09:47:30 pm
content: That is a solid catch, thank you.Sent from my horrible mobile....

author: rx8pilot
author_rank: Super Contributor
timestamp: April 23, 2017, 01:33:21 am
content: Quote from: John_ITIC on April 22, 2017, 07:58:52 pmI will confirm that doubt and present it as absolute fact, lol. Books, app notes, You Tube, intellectually generous people are forums, etc are my primary strategy.Quote from: John_ITIC on April 22, 2017, 07:58:52 pmAbsolutely. I have spent the past couple of years doing DC power electronics and power management. I have not, however, developed any PDN directly for high-speed. My projects are all for primary power that feed a local PDN system. It is good and relevant experience to have - but I still have things to learn about powering this type of circuit.

author: Someone
author_rank: Super Contributor
timestamp: April 23, 2017, 02:29:14 am
content: Quote from: tggzzz on April 22, 2017, 02:09:56 pmI'm well aware of this rediscovered technique (care of Keysights recent marketing) but the OP specificallydoesnthave a second probe and said the signal looked the same at each location which it theoretically shouldn't. The important information is what the SI looks like at the receiver and the probing will be changing the measured result so its useful to have some other ways to assess its impact rather than buying another probe as a dummy. If the eye looked the same at all the probing locations then something is seriously wrong.

author: Pitrsek
author_rank: Regular Contributor
timestamp: April 23, 2017, 07:49:41 am
content: Two years ago the price of Lee Ritchey 3day seminar was cca 2200eur. Dunno what is price now. But it was packed with information. I don't know how much HS design you have in front of you, but it might be worth it. Take a look at his website, lot of good info there. Books are nice as well.Regarding the PDN, look at videos/articles from Steve Sandler, also literature from Istvan Novak is very nice. Last year Steve did a one day PDN bootcamp - price was 250eur. And it was really nice. Great guy who knows his stuff. I think he collaborates with Keysight - so you can ask your local contact if there is some training planned in your area.The thing is that for PDN(well, actually for everything you do...) you need to be able measure what you are doping. In this case it means SA with TG.Or better "low freqency" VNA - this one is more versatile, cheapest one I know is BODE 100. Actually having both will give you some serious measurement potential....

author: rx8pilot
author_rank: Super Contributor
timestamp: April 23, 2017, 11:26:01 pm
content: Quote from: Pitrsek on April 23, 2017, 07:49:41 amI met Mr. Sandler about a year ago. He was (no surprise) a wealth of practical information. Needless to say, I have his book which is a nice bridge from theory to practical reality in power supply design. I looked closely at the Bode 100 and nearly got one on eBay a couple of months ago - it disappeared before I could move on it. They rarely come up on the used market, at least at a good price. I have such an enormously long list of very important equipment needs - it is a challenge to manage that as funds allow. Right now, a Markforged 3D printer may have to be the next thing which will push EE gear down the road along with everything else.This book should help......arrived a few minutes ago.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 29, 2017, 02:32:10 am
content: Quick update -The book mentioned above is excellent so far. Very practical and easy to follow, but appears to have enough detail to be truly useful.I met with an engineer from Samtec, the company that makes the BNC connectors and gathered a wealth of information. He had a 20 Ghz Keysight PNA series VNA with a very rare 12Ghz 50 Ohm to 75 Ohm matching pad and cal kit. We were able to look at how to best launch a 12Ghz signal from the connector to the PCB. We looked at good and bad on the VNA. We talked about various PCB materials, RF simulation, etc. The real good part was that he and others at Samtec can take my project and model it as well as practically test it with their fully configured lab. the equipment and talent are miles out of reach for me so this is an amazing resource. He set up a demo where a 12Ghz signal was run through about 14 connections, cables, and PCBs - the eye was still open at the end and able to be decoded without errors. That was pretty impressive. I was expecting the signal to be mush by the time it went through that many transitions.I also met with engineers from Semtech, Texas Instruments, and Macom who were also a wealth of information on how to deal with the various challenges in high-speed digital. Semtech was the most generous about offering practical assistance and reference designs. TI was pleasant, but did not have or did not offer as much assistance. For example, Semtech can help review designs as well as validate the designs after they are built in a purpose built lab. TI offered design help, but did not offer any validation service. Macom (makes similar silicon) was the least friendly from a design perspective, but that may have been the person I was speaking with. It felt like he had not slept in weeks and was drinking since 9am.Anyway - the conversations I had with the collection of engineers this week and the various design assistance available leaves me encouraged that I will be able to get high-speed IO sorted out for my FPGA projects and other things. As difficult as the learning curve has been so far, it really is a lot of fun. Expecting to submit the next spin of the PCB tomorrow, fingers crossed I will at least see some improvements. If I can operate at up to 3Ghz, it will be marketable. If it is marketable, I can better pay for the various test gear and learning curve needed for the road ahead. I will try to post the latest PCB layout before I submit it.

author: KE5FX
author_rank: Super Contributor
timestamp: April 29, 2017, 02:47:51 am
content: Quote from: rx8pilot on April 29, 2017, 02:32:10 amThis would've made a killer video. It would certainly have made Samtec look good.

author: rx8pilot
author_rank: Super Contributor
timestamp: April 29, 2017, 03:10:22 am
content: No doubt, I wish I had my camera with me. The engineer was the one that designed the specific connectors I am using so there was no guessing. I think the VNA was $150k with all the accessories, making it the most expensive piece of test equipment I have ever touched. To be clear, I was lost on how to use it, but I did touch it just to say I did, lol.Sent from my horrible mobile....

author: rx8pilot
author_rank: Super Contributor
timestamp: May 01, 2017, 09:03:23 pm
content: The latest edits:Changed the BNC footprints to a better geometry. The dimensions are not perfect, but the general shape is in place. Hopefully, Samtec can provide some help this week. I did clean up the passive termination components quite a bit to get a better signal into the equalizer.Quote from: hendorog on April 22, 2017, 09:01:14 pmI changed the power distribution network to make VCC_0 1.8v and DC coupled the differential output to the reclocker GS6151 - obviously a lot less to go wrong with no impedance disturbing caps in the way. Thanks for pointing that out. I also read a bit more and figured out that I can DC couple from the reclocker GS6151 to the cable driver too, cleaning that up. The top ground fill is fenced with vias along the high-speed data and the distance between the microstrip and ground is about double the trace width.One of the biggest problems was that the stack-up on the PCB was not what I planned for. The actual impedance was off substantially. I pinned those down for the next round without going to a controlled impedance PCB process.There were a lot of other little fixes too, but probably not signal integrity related. I had to move to a switching supply to get the 3.3v because I needed a much wider range of input voltage. The original design was just LDO linear regulators and I was powering from 5v max. Now I can go up to 30v or so without smoke. I have some concern about the EMI of the new switcher, it is possible I will need some additional filtering. At this point, all I really have are input/output caps and ferrites on both ends. I have all the tools to measure power noise and response at least, so I can test it in a meaningful way.Hope this is going in the right direction.

author: AndyC_772
author_rank: Super Contributor
timestamp: May 02, 2017, 06:42:12 am
content: What are the components in series with your signals, right next to each of the three BNC connectors?I'm not saying it necessarily is in your case, but one trap which people do sometimes fall into, is treating a connector as though it's a driver or receiver, and placing termination components accordingly. But they're not, of course; the actual driver and receiver are just at the other end of the cable, and if the cable and connector have the same characteristic impedance as the trace, then from a signal integrity point of view, they're just an extension of the transmission line.

author: Rerouter
author_rank: Super Contributor
timestamp: May 02, 2017, 09:32:17 am
content: I'm seeing quite a few stubs in your top ground fill, most of them you should be fine to crop out and the ones that go to a component can be necked.down to the pads. Equally any pad that goes to ground should have atleast 1 via right next to it ideally towards the direction of the signal on the other side, or opposed, to keep your loop area as small as possible,At your speeds, return paths matter, even the low speed ones as a loop can be a recieving antenna as much as a transmitting

author: rx8pilot
author_rank: Super Contributor
timestamp: May 03, 2017, 12:37:02 am
content: Quote from: AndyC_772 on May 02, 2017, 06:42:12 amThose parts are the return-loss compensation and the termination. The top-left BNC area is the input and the bottom-left and bottom-right BNC's are the outputs. I have already made some changes to the layout since the last image, but the parts have to stay. In theory, the BNC's would be impedance invisible but the right angle through-hole models not so much. I am also stuck with routing the signal on the wrong side of the PCB which creates a stub as the center BNC pin goes through the board. The mechanical restrictions are getting in the way of signal integrity to some extent. The requirement for this first pass is only up to 3Ghz with fairly short cables - offering some forgiveness. I can work on 6Ghz and 12Ghz on a later revision where it gets more and more sensitive.Quote from: Rerouter on May 02, 2017, 09:32:17 amTrue - I went through and made some adjustments to the top ground fill to reduce stubs and added more stitching where it seemed to be needed. I blended the high-speed traces into the passive components and made sure there are GND vias next to each high-speed i/o pin. Per the suggestions of Semtech and a couple of other app notes - I used cutouts on the high-speed parts. Considering that the original layout actually worked, but just with some ringing - my guess is that the long list of improvements should make it pretty decent - at least up to 3 Ghz. To make the higher frequencies work, I will need to get the BNC launch dialed in a bit better. I recently found some parts that have the return-loss compensation built in and the the re-clocker / cable driver have been combined. That eliminates a lot of variables and drastically tightens up the layout.

author: rx8pilot
author_rank: Super Contributor
timestamp: May 13, 2017, 08:53:28 pm
content: Update with REV 2 PCB:Summary: Not much changed even after making a substantial number of changes to the PCB layout.Change highlight include removing AC coupling caps on high-speed differential lines, EQ chip GS6042 power was re-routed to drive the output at lower voltage, differential trace geometry updated to match the PCB stack up, added guard vias, lots of power related tweaks, BNC footprint fixes, 75 ohm single ended path layout fixes, and more.I initially went through to look at each power pin since the linear 3.3v supply was swapped for a switcher - Linear LT8607. The 3.3 is rather clean down to a few millivolts, filtered with SMD ferrites, and bypassed very close to all power pins. Seems to be working well enough for the task.The two high-speed traces are behaving almost identical to the previous revision - ~5Ghz ringing on over/undershoot. The signal is still readable at the end, but still quite a mess. I briefly had a commercially sold PCB with similar hardware on the bench. I was able to probe that to see if my probe was potentially causing the distortion - it was was far cleaner as expected. The single ended input looks good right at the termination point of the EQ chip - amplitude, rise time, and no ringing there. The output of the EQ GS6042 and RECLOCKER GS6151 look very similar and appear to have a rather severe impedance mismatch. Both of these chips are driving the signal into an internally terminated receiver. That only leaves the PCB traces to have a large impedance deviation (I think). I hope the via placements are good enough for signal returns.I was not expecting this iteration to be perfect, but am definitely surprised how little impact the layout changes made. It seems like a barrel if issues were addressed and at a minimum - it should behave differently if not better. Spending a lot of time learning how to determine the inductance of a via, but the issue may be much more fundamental than that. Something big is sitting right in front of my face?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 13, 2017, 09:18:56 pm
content: Evidently you changed everything BUT the one thing that has an electrical length of 5GHz.Tim

author: rx8pilot
author_rank: Super Contributor
timestamp: May 13, 2017, 09:57:43 pm
content: Quote from: T3sl4co1l on May 13, 2017, 09:18:56 pmYep - I am stumped and back into the data sheets, books, and app notes looking for the smoking gun. At the moment, I am setting up a SPI interface with a Bus Pirate to be able to change some of the GS6151 internal parameters. One necessary change is setting the input for DC coupling although I doubt that is part of the ringing problem. I will also have access to output swing, de-emphasis, pre-emphasis, internal eye monitor.If the issue is simply an impedance mismatch on the PCB traces, I am wondering how far off it wold have to be to ring the way it is.EDIT:I don't think the Bus Pirate can cope with 1.8v SPIIf anyone has a quick suggestion to send/receive some basic commands and data over 1v8 SPI. I don't have anything to build a level shifter - although I am digging through my spare silicon right now.

author: hendorog
author_rank: Super Contributor
timestamp: May 13, 2017, 10:24:59 pm
content: You could remove the components in the signal path one by one and terminate with resistors. Combined with your probing you should be able to isolate the issue.i.e. 75 ohm resistor instead of the BNC output and then 100 ohm resistor to terminate the diff pairs as you move back down the path.Good info that the probing is not causing the problem as that gives you confidence that there really is an issue somewhere.

author: rx8pilot
author_rank: Super Contributor
timestamp: May 13, 2017, 10:38:52 pm
content: This is a shot of the commercial reference PCB I had the other day. This is a middle of the road product overall. The signal integrity is much better than what I have on mine so far - but still not a model of perfection. The better the signal, the longer the cables can be and fewer repeaters will be needed. These systems are also regularly used with poor and abused cables among other challenges so have as much headroom as practically possible is important.EDIT: Added imageI overlayed the commercial reference with my circuit - the ringing on the commercial circuit is much lower in amplitude but similar in period.

author: KE5FX
author_rank: Super Contributor
timestamp: May 13, 2017, 11:09:35 pm
content: I haven't seen your schematic, but one quick suggestion is to look for places where you can/should be using source termination, but aren't. That kind of ringing happens when a slightly-mismatched signal path or transmission line (read: all of them) is driven harder than it needs to be. Series R at the driver end can help by improving the termination seen by the initial reflection.On the other hand, if this is an LVDS or other differential connection where source termination isn't appropriate, you may not have a problem at all, because the margins are better than they look.

author: rx8pilot
author_rank: Super Contributor
timestamp: May 13, 2017, 11:36:34 pm
content: Quote from: KE5FX on May 13, 2017, 11:09:35 pmThere is a schematic in the first post, first image. The only significant change is that the AC coupling caps have been removed. In theory - the EQ Chip GS6042 has internal source termination as well as the next chip GS6151. The whole family are CML logic on the high speed lines and the data sheet (as well as manufacturer reference designs) are connected directly to one another with no external slew rate or current control.I used a couple of differential microstrip calculators online and could have gone wrong there.1oz top copper - 6.9mil dielectric - 1oz GND PLANE copper - 44 mils dielectric - 1oz PWR copper - 6.9mil dielectric - GND/low speed signalsdielectric constant 4.29differential trace 8mil spacing 7 milsHoping that is close to 100ohm impedance

author: BrianHG
author_rank: Super Contributor
timestamp: May 14, 2017, 12:07:11 am
content: Your circuit appears to have a faster rise and fall than the commercial reference. When it comes to ring oscillation alone due to circuit design, I would expect to see the same speed, or, slower. With this faster rise and fall, which may be even faster hidden due to the influenced ringing, this may be happening within you probing setup or lowering the bandwidth of your HW or pcb would soften the blow to match the commercial reference matching it's ringing. This can happen alone just due to the thickness of you signal traces and the characteristics of the PCB itself. Can we see a picture of your probing setup & maybe a photo of the reference PCB.

author: Rerouter
author_rank: Super Contributor
timestamp: May 14, 2017, 12:08:51 am
content: At a glance I find it very odd that the ringing frequency looks very close on both circuits, i dont suppose you can measure that frequency and see if your test setup has lengths approaching those wavelegths?

author: rx8pilot
author_rank: Super Contributor
timestamp: May 14, 2017, 12:47:15 am
content: Quote from: BrianHG on May 14, 2017, 12:07:11 amJust to be totally transparent - the overlay was stretched vertically to match the amplitude a little better. The goal was to show the similarity in the ring period, but that may have made the rise time stretch a little as well. The rise time may is likely much closer than the altered image depicts. I thought I was going to have that device for a couple of weeks, but it had to go. I think I can get another one to compare in a more scientific and planned out manner. The one shot I saved was just a quick 'jam the probe in there and see what we see' kinda thing. The reference PCB was designed for 3Gbps and the chips I am using are capable of 6Gbps. I an only testing them with a 1.485Gbps test signal.Quote from: Rerouter on May 14, 2017, 12:08:51 amThe ring frequency is right around 5Ghz. I am manually probing with a Keysight N2752A with the browser tips as shown in the attached image. I am probing the pins directly on the QFN packages under a microscope - quite a challenge to hand probe .4mm QFN pins that are side by side. Adding any test points would never work so I guess this is how the big boys do it. The probe has solder-in wire tips but they roll off at 3Ghz so I would be attenuating the ring if I did that.....aaaaand yes, I did not expect to see the same thing. Another detail is that the ringing seen on both high-speed traces is nearly identical. The GS6151 chip in the middle of the chain re-clocks and recreates the signal before sending it through a longer trace into a different device. The differential microstrip structure is different in that area of course. Is it possible for the probe to damage the signal this bad? I REALLY wish I had a second high-speed probe.

author: BrianHG
author_rank: Super Contributor
timestamp: May 14, 2017, 01:27:15 am
content: Quote from: rx8pilot on May 14, 2017, 12:47:15 amEven with your resizing, the double speed chip does clearly depict a faster rise and fall time as the source is deliberately brought to as fast as possible rise and fall time even if the source is only 1.485Gbps.What's the bandwidth & load capacitance of your active probe?The ring is beginning to look like the inductance of your trace + capacitance of the probe as it is ringing in the 5GHz region driven from an IC capable of 6Gbps.It may be entirely possible that the ring you see may not be there on your PCB.Do you have access to a higher frequency probe?A few years back, I had a similar issue, though 750 Mhz and 1 Ghz, with my Tektronix active J-Fet probes, I had 1 which was 1.5Ghz and 3 at 1Ghz, both rated at less then 0.5pf. The 1.5Ghz had less bounce testing my DDR3 buss data lines on faster memory chips and apparently less capacitance at the tip.

author: rx8pilot
author_rank: Super Contributor
timestamp: May 14, 2017, 01:39:35 am
content: The probe is officially rated as 6Ghz but apparently does not hit 3db until 7Ghz. 200k differential and only 700fF capacitance.I am going to check and see how much the browser tip may add. Still, it could be a measurement error or at least exacerbated by the measurement.EDIT:The 700fF capacitance is with the browser tip I am using - that is rather low.Quote from: BrianHG on May 14, 2017, 01:27:15 amI am not positive, but I think the chips match the rise time to the supported data rates. As the data rate increases, the rise time does as well. Checking to confirm that.

author: Rerouter
author_rank: Super Contributor
timestamp: May 14, 2017, 03:13:27 am
content: Well i did the math, for a 5ghz resonance you only need 1.45nH of inductance, which i would say is in the right ballpark.That resonance also has a wavelength within 10 times your trace length so tansmission effects are out to play, (60mm)From the looks of things, the edge only rings twice, then stops, while at the same time those first 2 rings decay only a tiny amount impling to me that the termination is sending off a decent reflection,When i do the math that 700fF probe capacitance is almost 50 ohm loading at that 5Ghz resonance, which lines up with what we are seing, the fast signal meets with a 25 ohm load, kicks off an ugly reflection, its phase inverts, destructivly adds and kills the ringing.So it would appear that yes this one is mostly down to impedance errors.The probe is likely both adding the resonance and adding the spike aplitude,

author: Rerouter
author_rank: Super Contributor
timestamp: May 14, 2017, 03:18:23 am
content: You can actually use this info to your advantage, if you pull up some charts showing overshoot vs impedance difference and subtract out the probes contribution you should be able to say how close to the mark you hit on the traces

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 14, 2017, 05:54:10 am
content: Remember what frequency and impedance means:5GHz and 100 ohms is equivalent to 0.318pF and 3.18nH is equivalent to 2.5mm and 50ps. (That would be 1/4 wave at 5GHz, and the length assumes unity velocity factor: the maximum possible length in any medium. Microstrip gives about 0.7-0.8 times length.)The culprit can be nothing other than a geometric feature with these dimensions!Tim

author: rx8pilot
author_rank: Super Contributor
timestamp: May 14, 2017, 06:24:20 am
content: Quote from: T3sl4co1l on May 14, 2017, 05:54:10 amI wish I could fully grasp that - what am I missing? If the trace was a little longer it may not resonate?I did a quick measurement that was helpful to see. A short 12 inch piece of 75 Ohm coax was connected to the signal source and I roughly terminated the end of the coax with a single 0402 75 ohm resistor (like I said, rough). I wanted to compare the signal from the source and the output of the DUT with the exact same test fixture. The scope has EQ and clock recovery built in which makes this quite a bit easier. Looking at the DUT output on the end of the cable is not nearly as bad as what I see on the 100 ohm differential traces. There is still some ringing, but not the worst I have ever seen. Maybe some of the 5Ghz ring is simply filtered due to bandwidth limitations of my makeshift test fixture. sure wish I had a 3Ghz and 6Ghz signal source - but I have to wait for that.The screen shots have some erroneous traces and the cursor data is meaningless.

author: Rerouter
author_rank: Super Contributor
timestamp: May 14, 2017, 06:32:50 am
content: Hmm, still 5Ghz ringing, under quite a different setup. could you try changing your termination value with this setup, to say 120 ohms, again the scope loading will be quite high, and this can let you isolate it out.

author: rx8pilot
author_rank: Super Contributor
timestamp: May 14, 2017, 06:41:29 am
content: Is the probe loading really that severe? It seems it would be useless if it loaded high frequency circuits that much.Sent from my horrible mobile....

author: Rerouter
author_rank: Super Contributor
timestamp: May 14, 2017, 06:44:46 am
content: 3.125Ghz with a 700fF capacitor is 73 ohms of impedance, in reality being a square wave the frequency it will be far lower impedance, but as those higher frequencies are already lower in amplitude its not as much of an issue.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 14, 2017, 09:12:30 am
content: Quote from: rx8pilot on May 14, 2017, 06:24:20 amIt's so obvious, it could only be impossible to understand.Presumably, you have an unterminated or mismatched stub somewhere.The length of the stub is inversely proportional to the resonant frequency.Therecannot beany longer transmission line segments that produce that ringing.So, on the list of suspects, the long PCB tracesare right out.IC interconnects (trace taper/neckdown/fanout, if applicable; pad and bondwire equivalent circuits) could plausibly be on the list, but hopefully are taken care of by the manufacturer (pin models and internal terminations designed to tune that out), and are still on the short side (< 2mm).Also, the impedance of the suspected stub should be fairly high, since the amplitude of the ringing is much less than the total height of the transition. (Or fairly low, if it's a series stub, but that would be harder to explain.)The common element in all of this: the probe itself. Which looks like it has dimensions, and RLC equivalent specs, plausibly similar to the observed effect.You should drop the probe (not literally, that would be expensive~) and use a direct wired approach as your gold-standard reference. This will show if it is indeed the probe itself. Standard RF techniques apply: build a microstrip resistor divider/attenuator alongside the trace, to tap off some signal and route it to a coax cable. Use a wideband balun to resolve differential mode waves specifically (or matched lengths of cables and difference it at the scope -- precision matching probably not being required due to delay adjust in modern scopes).Tim

author: AndyC_772
author_rank: Super Contributor
timestamp: May 14, 2017, 09:53:39 am
content: I'm afraid I can't offer any further insight right now, but one very good thing has come out of this.You've learned that a whole host of PCB features, which may have been non-optimal, actually don't matter nearly as much as you might have thought!There's hope for us all here

author: BrianHG
author_rank: Super Contributor
timestamp: May 14, 2017, 05:10:16 pm
content: Quote from: rx8pilot on May 14, 2017, 06:24:20 amQ: Are you using a fixed EQ to compensate for your probe? This is OK.If you are dynamically equalizing the source signal, then what you are looking at is not what's truly going on at the PCB trace level. It's being filtered to get the best possible eye opening. Equalization like this may also hide a lot of fine issues with layout and all the testing/scope shots you've done to date may be faulty.

author: rx8pilot
author_rank: Super Contributor
timestamp: May 14, 2017, 09:46:59 pm
content: Good point to bring up. I only used the EQ in a fixed mode on the scope to get an idea of how well the data can be recovered after being launched into the coax cable.I was examining traces as an un-processed signal which shows me everything. Since I have little experience measuring signals this fast, I am looking at them in a variety of ways to build some intuition about the task. When I started down the path of power electronics a couple of years ago - I was seriously humbled at the difficulty of measuring those systems in a way that delivers useful information. Looks like high-speed digital will slap me in the face a few times.Sent from my horrible mobile....

author: rx8pilot
author_rank: Super Contributor
timestamp: May 15, 2017, 06:09:35 pm
content: Quote from: Rerouter on May 14, 2017, 06:44:46 amI looked closer (as much as I am able) at the probe loading and what you (and Tim) have been saying is starting to make sense. The probe manual has some solid data to go by and I clipped the impedance plot for reference. It shows that the impedance drops to a min of 220 ohms as the frequency goes much above the Gigahertz range. This, as mentioned, can certainly disrupt a differential trace and create the ringing. The question I end up with is how do you measure a differential trace as I am trying to do? Maybe it is not possible to directly probe it in circuit? Maybe an indirect measurement of the trace impedance like a TDR and a test coupon? Maybe removing the reciever chip and terminating the line with an appropriate value to combine probe loading and have a 100ohm load in the end? Keysight provides the SPICE model for the probe and the tip which makes it fairly easy to make a simple simulation to better understand what is happening.Quote from: Rerouter on May 14, 2017, 06:32:50 amIt appears that 120ohm termination plus the probe should be rather close to the Z0of 75 ohms. It is easy to try.Quote from: T3sl4co1l on May 14, 2017, 09:12:30 amThe BNC launch is questionable for sure. I am still planning to have Samtec help me get those launch structures dialed in. One known issue is that I am launching on the top side of the board and the recommendation of Samtec is to launch on the bottom with the connectors I am using. I was not confident in a bottom launch and then having to transit a via to get to the signal side of the PCB. Physical restrictions of the intended mechanical housing create this challenge. The stub is leaves maybe be enough at 2-3mm to cause a problem. The quick test is for me to trim the center pin of the BNC to remove the stub and see if it makes an appreciable difference. Samtec offers a custom service for connectors where they trim the center pin to allow launching on the top of the PCB. I would rather learn how to successfully use a via to avoid custom connectors if it is needed.At the moment, I am hypothesizing that there are issues with the design and the measurements - but closing in on a workable solution.

author: Pitrsek
author_rank: Regular Contributor
timestamp: May 15, 2017, 07:44:01 pm
content: Actually going trough via is better than keeping stuff on one layer and having a THT stub on the connector.If you go trough via, it behaves like a transmission line - with appropriate ground vias around it can be made +- correct impedance. If you do not travel trough the via, via behaves like a small capacitor. That's reason why are connectors back-drilled. More info in L.Ritchey books and most probably in some papers as well. Do you have a spare PCB sample so you could back drill the connector center pin?EDIT: Soldering the connector from the other side is probably way easier than back-drilling

author: rx8pilot
author_rank: Super Contributor
timestamp: May 15, 2017, 09:54:19 pm
content: Quote from: Pitrsek on May 15, 2017, 07:44:01 pmBack drilling definitely seems like the long road to the solution. All I need is some more learning and confidence to use a via properly in this case. I do have plenty of PCB's but not enough of the chips to make another board - only had two samples of each part. All layers were cutout on the PCB design except the top signal layer. I can trim the pin back on the assembled PCB to about 30mils of the top layer to see what difference it makes.To eliminate the probe artifacts - I connected the signal source directly to the 50ohm input on the scope with a 75 Ohm BNC cable. This is a 75ohm source and cable going into a 50ohm load, but for comparison of source and DUT, is not a terrible idea. Both ends are BNC which eliminates the need for any adaptors to physically connect them. If all was perfect, the DUT output would look identical to the original signal source.The signal source looks quite reasonable considering the mismatch. Looking at the DUT output - and it has a relatively small ring. Not nearly as much as we saw with the active probe on the differential PCB traces. Does this mean that maybe I am not as far off as I thought or is the cable simply acting as a low-pass filter that has the appearance of improvement?In the image - the blue trace is the signal source and the orange is the DUT output. A single pulse using the same cable and scope input.

author: BrianHG
author_rank: Super Contributor
timestamp: May 15, 2017, 11:56:58 pm
content: Once again, your output signal rises and falls much faster, even more now than before, than your source. This is to be expected of a re-clocker (this is the purpose of the re-clocker, make a clean new square wave, clocked cleanly to a new synthed PLL clock, remove timing discrepancies from long transmition cables, rise and fall as fast as possible). I bet if you place a series 25 ohm resistor, or series ferite/inductor to match slow down your output to match your source, I bet the ring will be almost completely gone.

author: Someone
author_rank: Super Contributor
timestamp: May 16, 2017, 01:14:43 am
content: Quote from: rx8pilot on May 15, 2017, 06:09:35 pmWell you can TDR the board with or without the chips in place, but what you are looking for and how to correct the eye is then relying on experience and understanding of the design. Lots of pretty pictures and some good information here:http://www.keysight.com/upload/cmc_upload/All/Download1.pdfBut the link seems brittle, its a presentation titled 'Measuring “Hot TDR” and Eye Diagrams with an Vector Network Analyzer?'But going back around again, once you know the probe loading you can put it back into simulation and see how its affecting the data/eye. Getting a probe with lower loading you'll soon run up against its limitations anyway so its back to simulation and modelling, or paying big money for automated de-embedding. In the end the only interesting parameter for your customer is the signal they receive at the end of the cable, so you can ignore a lot of the intermediate measurements and concentrate on what arrives at a properly terminated receiver having passed through cables.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 16, 2017, 01:18:43 am
content: The twiddle in the waveform may be mismatch at the join between cables.Ringing due to mismatch of long cables (>> 1mm) can only manifest as ringing at correspondinglylowfrequencies (many cycles!).Tim

author: Rerouter
author_rank: Super Contributor
timestamp: May 16, 2017, 02:18:26 am
content: There are actually differential probes out there with as low as 35fF of capacitance, these are what come out when you want minimal loading.However i expect it to cost as much as a house.In both cases, you use the difference between measuring styles to figure out the difference caused by the probes,To really hit the nail on the head you can follow approches like the following link, you would test each output with only the probe and matching circuit loading it.digitizers/impedance_and_impedance_matchingOnce you see that the signal is clean and the inpedance of the trace in spec, so long as the termination is correct within the reciever you can have a good idea on what the signal actually resembles

author: rx8pilot
author_rank: Super Contributor
timestamp: May 16, 2017, 02:30:17 am
content: Quote from: BrianHG on May 15, 2017, 11:56:58 pmYes, it is faster rise time for sure. The slew rate is limited at 1.485Gbps and will be faster at 3G and 6G when detected. At that point, the ringing would likely be faster than I can see. If I slow it down externally, it may cause problems with the faster slew rates when they are applied. Do you suppose the value of the inductors on the return loss network may need some re-considering? The output path is a 75ohm resistor in parallel with a small 4.7nH inductor just before the AC coupling cap. I have a slightly larger value and a slightly larger value but they both made things quite a bit worse. (did not grab any shots of that).I also back drilled the center pin of the BNC up to about 30mils of the top signal layer - that did not appear to change much. It may have helped, but compared to the bump I am looking at it was contributing very little.Quote from: Someone on May 16, 2017, 01:14:43 amBig money seems to be very helpful testing electronicsAutomated de-embed, RF sim software, and various other tools are still in dream territory right now. I love watching the various marketing videos from Keysight and Rode - and then I discover the amazing piece of gear they are showing is about $300k and I move on the the next best thing: GuessingSeriously though, I am looking at how to take advantage of the SPICE model provided by Keysight of the probe. I have only used SPICE for much more basic simulation, so that would be yet another software learning curveI have never tried to effectively de-embed a probe (or fixture) from a measurement. What is the magnitude of effort needed to accomplish what you are talking about for someone that has never done it?Quote from: T3sl4co1l on May 16, 2017, 01:18:43 amJust for reference - I am going to try various cables to see how they may be different. I have a variety ranging from short/good to long/bad and quite a few in-between.

author: rx8pilot
author_rank: Super Contributor
timestamp: May 16, 2017, 02:33:36 am
content: Quote from: Rerouter on May 16, 2017, 02:18:26 amYikes! I would be rather happy to have a second one of my 'low end' 700fF probesHopefully, I will have a 3G and 6G signal to try soon - very curious how the system will respond to faster rise/fall times.

author: BrianHG
author_rank: Super Contributor
timestamp: May 16, 2017, 08:12:12 am
content: Quote from: rx8pilot on May 16, 2017, 02:30:17 amArrg, an added inductor in a microwave speed signal path with a capacitive load.... Can you please draw a diagram of your output path filter, with the location on the PCB (just painting the probe points on your PCB screen capture would be fine). This can easily generate signal ring & if it is part of the manufacturer's recommended output, it may be there to limit or enhance the fine edge of the signal. You may just need to tune the inductor value to trim out your PCB's characteristics.

author: rx8pilot
author_rank: Super Contributor
timestamp: May 16, 2017, 05:15:51 pm
content: Quote from: BrianHG on May 16, 2017, 08:12:12 amHere is the data sheet and my layout. The data sheet clearly states the inductor values are a guideline only and need to be adjusted to compensate for the characteristics of the actual PCB. I am not sure how to know how to go about that. I went a little up and little down on each one and the result was worse. At the moment I have the datasheet values in the DUT. I only have 3 values available to me right now - 6.2nH, 4.7nH, and 2.7nH. On my next DigiKey order I will throw in an inductor range that allows finer steps.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 16, 2017, 09:04:05 pm
content: Try 0402 resistors and inductors (assuming the resistor power dissipation isn't a problem), and squash them as close together as possible. Keep trace width constant, rather than necking up and down all the time.Tim

author: BrianHG
author_rank: Super Contributor
timestamp: May 16, 2017, 09:59:07 pm
content: Arrrg, you are driving the +&- balanced output to 2 different track lengths... You do realize that the a balanced load on each output on the IC make a balanced equal load on the IC's power supply as well, canceling out internal the IC's VCC&GND current consumption equally making a flat consistent DC load on the die. The timing error you create by un-balancing the output perfectly will add a ring or bounce to both outputs as the designed neutral load no longer exists. Now, this is if you want the penultimate perfect signal achievable with the IC, this doesn't mean what you have done wont still create a great SDI signal.Next step, test: Short out 2.7nH to 0 ohm and re-scope & post images.Also, when doing your next PCB, the pullup inductor/resistors network with +/- outputs should match in physical size and structure being mirror like right up at the IC. This once again goes towards both the positive and negative outputs having a perfectly matching drive and load.

author: rx8pilot
author_rank: Super Contributor
timestamp: May 16, 2017, 10:48:37 pm
content: Quote from: BrianHG on May 16, 2017, 09:59:07 pmYa know - that was not even considered at all but makes sense. Thanks!Quote from: T3sl4co1l on May 16, 2017, 09:04:05 pmThe resistors are already 0402, but the L's are 0603. I was split on the tapered traces until I found an app note that specifically compared the various track geometry on a VNA. I am going to post it to see if anyone has an opinion on the information.

author: Gribo
author_rank: Frequent Contributor
timestamp: May 17, 2017, 12:52:01 pm
content: What sort of inductors do you use?

author: rx8pilot
author_rank: Super Contributor
timestamp: May 17, 2017, 03:01:14 pm
content: Quote from: Gribo on May 17, 2017, 12:52:01 pmI chose Murata LQW and LQG series inductors.https://www.digikey.com/product-detail/en/murata-electronics-north-america/LQW18AN4N7C80D/490-14722-1-ND/6606328https://www.digikey.com/product-detail/en/murata-electronics-north-america/LQG18HN2N7S00D/490-1103-1-ND/584549I was not entirely confident in the component choices since I had very little information about what is most important or what parameters need to be balanced in this application.

author: rx8pilot
author_rank: Super Contributor
timestamp: August 18, 2017, 01:53:44 am
content: I have finally returned to this project!Quote from: BrianHG on May 16, 2017, 09:59:07 pmThinking about this - there is no requirement for each output to be loaded at all and should not impact the adjacent 75 ohm output. Trying to get an answer from Gennum on this one.One of the biggest unknowns for me was how the probe loading may be impacting the circuit. Keysight offered to let me demo an N2752A probe to do some probe loading experiments. This was huge as I did not want to spend the nearly $6k on a probe just to understand the loading. It seemed possible that the impedance mismatch and resulting reflections could have been introduced by the probe. Huge thanks to Keysight for helping in that regard!As it turned out - the probe loading was measurable - but insignificant. A very happy moment to better understand that variable. Double probing the test point lowered the amplitude slightly (as expected), but had no meaningful impact on the ringing/reflections.What I did today was to measure the input and output of each stage - the receiver, the re-clocker, and the line driver. TheyALLhave really pronounced reflections even though they are all unrelated. For example, the output return loss network has no impact on the 100-ohm differential pair between the receiver and the re-clocker or the re-clocker and the line driver. Yet, they are all a mess and look similar. Good enough to be received and decoded, but still not very good. That leads me to believe that I may need to consider the PCB may be the weakest link OR the calculators I have used are totally wrong.The PCB's come from PCBway which most of you know is the bottom of the barrel in terms of quality. They do offer controlled impedance, but the prototypes would jump from $125 to about $650. I am willing to spend the money on a properly fabbed impedance controlled PCB - but would be disappointed if it made little to no difference. PCBway ensured me the published stack up is what I got, but I have no way to test that. I do not have a TDR or VNA rig to measure the PCB in any way. I can only cross my fingers. With that in mind - maybe it is a good idea to have the fab house verify the impedance, add in some test coupons, etc.As a side note, I eventually need at least one more 6Ghz probe to work out timing between two separate signals.

author: Rerouter
author_rank: Super Contributor
timestamp: August 18, 2017, 02:26:38 am
content: Your boards are tiny, why is it costing you $150 via pcbway? It looks to me like it should be costing you $150 via them for a batch of 10 with hard gold and impedance control, even for the higher spec FR4 substrate.Do you have screens of the reflections, the direction and magnitude will let you calculate how far off they are, you should then be able to bodge a terminator of the right value with smd resistors to confirm.

author: rx8pilot
author_rank: Super Contributor
timestamp: August 18, 2017, 02:46:49 am
content: I got 5 panels that were 3x5 plus a stencil in hopes that they would be ok and I could run 50 of them through the P&P line. 5 panels is about $170 (75 pcs), $20 for the stencil, plus shipping.I would love to better understand how to look at the end result and estimate how far off it is. These are .4mm QFN's which make it hard to bodge in a termination test - but I think I could do it. I have a full kit of 1% 0402 resistors ready.Image 1: 100 ohm differential output of the re-clocker measured at the pins of the QFN.Image 2: 75 Ohm single ended terminated on the PCB at the BNC mount.

author: rx8pilot
author_rank: Super Contributor
timestamp: August 18, 2017, 05:39:02 am
content: Ok - another update:I pulled the line driver QFN off the PCB and used 0402 resistors to terminate the 100 Ohm differential line going into it. I measured it open, and 200 Ohms. Other than the amplitude changing, the ringing is the same. That kind of rules out an impedance mismatch?Stumped.

author: Araho
author_rank: Regular Contributor
timestamp: August 18, 2017, 11:08:47 am
content: Maybe your layout needs more work? No clue about this, I just find it really interesting and want to design some HD-SDI-stuff myself in the near futureAre you having any vias in one of the tracks in the diffpair that aren't there in the other, or something?

author: AndyC_772
author_rank: Super Contributor
timestamp: August 18, 2017, 12:29:38 pm
content: What does the power supply to the driver IC look like?Is it possible that the driver IC is actually just not very good in terms of SI? Have you seen the exact same IC work better on another layout?

author: rx8pilot
author_rank: Super Contributor
timestamp: August 18, 2017, 03:36:49 pm
content: There is little question that this layout would pass detailed scrutiny by someone truly skilled in the art of high-speed design. I have done 3 iterations so far - each one making significant changes - but the end results appear similar. It feels like the design details I am studying and changing are not the dominant source of ringing / reflections.The power supply is a 3v3 switcher that seems to be performing quite well. Very low ripple and very low noise. The chips are bypassed with 100nf and 10nf caps at each Vcc pin. The reclocker uses its own 1v8 LDO.All signals are on the top layer so I did not introduce any vias to my long list of design variables.The original layout was all LDO power, but again, similar results. I am just not sure what to consider next.Sent from my SAMSUNG-SM-G890A using Tapatalk

author: Rerouter
author_rank: Super Contributor
timestamp: August 18, 2017, 04:00:40 pm
content: I sat down and had a go meddling with your design in Kicad (What i prefer), and my best guess for most of your issues is unintentional ground inductance on the supply capacitors, a number of them dont have a direct run between the negative of a supply and the ground of the cap for that rail, many passing through 2 vias to reconnect.The zip file is the entire kicad project, if you want to play with it. I just started from scratch using what made sense to me, then went back and thought about why there where differences.The references are the same as your original one,In this case I places the ground vias where i could to create the least inductive circuit for each part of it.The Traces for the signal path are 0.3mm wide, spaced by 0.4, which was the best happy middleground i could come up with, as being less sensitive to the height, while meeting as close to the specs as i could (ideally 100 ohms differential, about 55 ohms to ground, but the top layer ground pour should nudge it closer to 50.4) qnd all distances put it at under 1/10th of a wavelength, but i figured you would be wanting to match your original grouping, so planned out what the impedance likely needs to be.I could actually see this being done on a 2 layer (0.2 or 0.3mm thick board), as the supply rails are quite easy to route around the signal path, and all your programming connections end up on the same side of the signal path.

author: rx8pilot
author_rank: Super Contributor
timestamp: August 18, 2017, 05:08:54 pm
content: Wow! That is an extraordinary effort to help! Thank you very much for the time.The ground vias should be rather low inductance as they connect to a solid ground plane on layer 2, 9mils below the top layer. Attached is layer 1 (signal and GND fill), layer 2 (GND), layer 3 power 3v3 and 1v8, layer 3 GND and Programming Header. It is entirelty possible that a power integrity issue is the main contributor. I will take a close, mV level, look at the power rails at various points around the board.For the brief moment that I have the Keysight probe on loan - I should do some timing comparisons to see if the ringing is time correlated at different stages of the signal.

author: rx8pilot
author_rank: Super Contributor
timestamp: August 18, 2017, 06:19:49 pm
content: After a look at the power rails so far. Measured the 3v3 rail at the Vcc pin of the receiver chip GS6042 - across the bypass cap. The same with the 1v8 rail at the Re-Clocker chip GS6151. Both of them look very clean at full bandwidth with the differential probe - 5mV/div. No switching noise to speak of. I also ran an FFT on the rails and swept from 0 - 7Ghz and the noise is pretty flat - no noticeable spikes. If anyone thinks I should look at other power issues - I am all ears for sure. From what I see, the 3 chips in the design are being fed a steady diet of voltage. I could not see any evidence of too much inductance.I also did a quick test to look at the signal chain at the beginning and the end. The yellow trace is the differential receiver output and the blue trace is the line driver differential input (temporarily terminated at 200 Ohms with resistors, chip removed). The ringing is nearly identical at both positions with one being properly terminated at 100 Ohms and the other improperly terminated at 200 Ohms. I did not expect that. My guess is that the 200 Ohm trace would look totally different. If the termination being changed wildly does not impact the characteristics of the ringing - maybe I should not be looking for an impedance mismatch problem at all.

author: rx8pilot
author_rank: Super Contributor
timestamp: August 18, 2017, 08:04:39 pm
content: Quote from: Araho on August 18, 2017, 11:08:47 amGennum (Semtech) is one of the top manufacturers of HD-SDI receivers, re-clockers, line drivers, and more. TI and Macom are also well established and good at what they do. There are countless successful use cases, so I am going to keep the blame machine aimed at me (the newcomer to highs-speed design). The level of detail is mind blowing and the test equipment and skills are not trivial.

author: nctnico
author_rank: Super Contributor
timestamp: August 18, 2017, 09:52:16 pm
content: I'm wondering. The ringing is close to the maximum bandwidth of the oscilloscope. Can this be some issue with interpolation? Does the signal change when the scope is set to equavalent time sampling? Did you try to look at the signal with a spectrum analyser to see if you can see a spike at the frequency you get the ringing?

author: Leo Bodnar
author_rank: Frequent Contributor
timestamp: August 18, 2017, 09:54:06 pm
content: rx8pilot,I have noticed you are using power–IC–decoupling routing rather than power–decoupling–IC.Not sure how critical this is for the design.Have you played with decoupling capacitors choice?They have amazingly low self-resonance. Low as in tens of MHz for a typical 100nF.Leo

author: Someone
author_rank: Super Contributor
timestamp: August 19, 2017, 12:19:30 am
content: Quote from: Leo Bodnar on August 18, 2017, 09:54:06 pmOddly U2 has the capacitors after the via and before the pins, but not the other two chips. Could be worth capturing the correlated ripple at the bypass caps on each of the different chips to see if there is any measurable difference.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 19, 2017, 12:40:28 am
content: FYI, SRF is not an indicator of bypass capacitor performance.Total PDN impedance is.Tim

author: rx8pilot
author_rank: Super Contributor
timestamp: August 19, 2017, 01:18:32 am
content: Quote from: nctnico on August 18, 2017, 09:52:16 pmI did look at the impact of using ET - no change. I also did an FFT (I do not have an SA) and see a lump around 5Ghz - but all the fast edges mask the ringing tone so not much to see there (unless I am missing something). The test equipment and my own technique has not yet been ruled out. When Keysight offered to loan me a probe, that was a fantastic opportunity to eliminate the hypothesis that the probe may be introducing some inductance that would make the ringing or at least exacerbate it.Quote from: Leo Bodnar on August 18, 2017, 09:54:06 pmI have not yet fiddled with decoupling caps, but it is an easy experiment just to see if it makes a measurable change. Maybe piggy back some small values - 2700p to 1nf to see what I see?Another note - I got a response from the Semtech Application Engineer. He requested all the data - schematic, gerbers, etc. so I am hopeful that he will discover a smoking gun (hope he goes easy on the newbie, lol).

author: Rerouter
author_rank: Super Contributor
timestamp: August 19, 2017, 01:34:09 am
content: Keep us posted, would be nice to have an RF engineers insight,

author: rx8pilot
author_rank: Super Contributor
timestamp: August 19, 2017, 01:37:35 am
content: Quote from: Someone on August 19, 2017, 12:19:30 amI just realized that - not sure what I was thinking or why I would do that. U2 is the 1v8 part powered by the LDO.Quote from: T3sl4co1l on August 19, 2017, 12:40:28 amI believe the PDN impedance to be reasonably low. The measurements I took around the PCB appear to be very clean while signals are passing through.Quote from: Rerouter on August 19, 2017, 01:34:09 amYes, it will be nice to have an RF engineers insight indeed.

author: BrianHG
author_rank: Super Contributor
timestamp: August 19, 2017, 04:56:50 am
content: Quote from: rx8pilot on August 18, 2017, 06:19:49 pmWhen looking at your power supply signals, try locking 1 channel of you scope on the output signal at each stage while viewing the VCC & GND of each IC on a second channel on your scope. Looking at the phase and amplitude of the source signals in time VS the supply signals might help you narrow in on a worst location culprit section of your design before you go swapping every bypass cap and making a mess of the PCB.I know power supply noise will have a fraction the amplitude of the output, and the noise wont be due to regulation issues, but you may sniff out a slightly weak location in you PCB layout.

author: Leo Bodnar
author_rank: Frequent Contributor
timestamp: August 19, 2017, 01:05:09 pm
content: Quote from: T3sl4co1l on August 19, 2017, 12:40:28 amSure, I was highlighting the fact that parasitics are higher than most people (including me) expect.SRF is easier to evaluate in an average lab given a set of alternative parts.Leo

author: AndyC_772
author_rank: Super Contributor
timestamp: August 19, 2017, 01:44:07 pm
content: I'd also question the importance of the SRF of a particular component when it's used in a design. In any practical circuit, there's additional inductance added in series with each decoupling cap by virtue of the traces that connect to it, which tends to dominate the component's own self inductance anyway.There's quite a lot of confusion and bad science out there when it comes to talking about how best to decouple high speed designs.The object of the exercise is always to provide an IC with a power supply with as low an impedance as possible across a wide enough frequency range, from DC up to the highest frequency at which the circuit operates (which, of course, depends on the edge rate in terms of dV/dt, and not on the number of switching cycles per second).So, for example, it's often suggested that you should use caps of different values, because each has a SRF, and therefore a minimum impedance, at different frequencies, but this isn't really a good recommendation.It may be that, say, a 100n 0402 cap has a lower SRF than a physically similar 10n cap, and so its impedance stops falling with increasing frequency (capacitance-dominated) and begins to increase again (inductance-dominated) at a lower frequency point than the 10n cap.But: if the self-inductance of both caps is about the same (which it will be if they're of similar physical size), and the capacitance of the 100n cap is larger, then its total impedance is still less than that of the 10n cap atallfrequencies. Using the 10n cap, when you can get 100n in the same physical package size, is pointless.Instead, for high speed designs, I'd recommend- use the physically smallest decoupling caps that you can- add the absolute least possible series inductance between each cap and the device it's supplying that you possibly can- remember that the lowest inductance path between any two points is almost certainly through a plane, not through a traceThere's quite a good discussion on the subject here:https://www.eevblog.com/forum/beginners/how-much-noise-on-power-rail-is-normal/

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 19, 2017, 04:44:36 pm
content: Don't bother trying too hard, either: past a few hundred MHz, it's impossible to provide extremely low impedances on a PCB, even to a BGA package on a multilayer board. Chip designers must provide for that themselves (differential drivers are a fantastic boon, here, even if you only need the one output).Do avoid stacking caps of different values: you'll end up with a peak impedance that's worse than using just one or two. The impedance peak may not be noticeable unless you test your circuit at different clock frequencies, with PRBS data, or fuzzing at least. Or test the PDN with a network analyzer.You can very easily throw more caps at a design, and think smugly to yourself that you've done well, butit's only superstition until you've tested and verified it.Do use damping: a ceramic with external ESR, or a lossy bulk cap with internal ESR (most often tantalum, which have stable ESR, and can be selected from a wide range of C and ESR). You want ESR to dominate PDN impedance, so that no resonance peaks out from it, and the impedance is nice and stable.Tim

author: rx8pilot
author_rank: Super Contributor
timestamp: August 19, 2017, 10:04:39 pm
content: With the discussion of decoupling caps - I thought I would do a quick experiment - Just take it off and see what impact it has.On U1 (the receiver chip GS6042) - the differential output driver has a dedicated Vcc that I am running from the 1v8 LDO supply. I have a 10n 0402 X7R cap to decouple. There was little consideration here, I just used the value from the manufacturer app note.So on these scope grabs, you can see two traces both of them are the differential output of the GS6042 chip U1. The Orange is a REFERENCE saved that I took with the decoupling cap. The Yellow is the capture with no decoupling cap at all. Identical. I guess the internal on-chip decoupling is the only thing really working at these edge rates. I was kind of expecting to see a rise-time extension or some other impact by having no bypass at all.So - I am thinking that even if the choice or routing on the decoupling caps could be improved - there is clearly something else making the ringing. The party shall continue......EDIT:I attached another image to show the impact of probe loading. The ORANGE trace is a single probe on a termination point (taken originally with the YELLOW probe). The BLUE/YELLOW are on the same point at the same time. It is very difficult to probe these extremely tiny points with two differential probes - so the blue probe is actually on the yellow probe which partly accounts for it's apparent attenuation. Since my hands were full and this was happening under a microscope - the voice control on the Keysight is VERY VERY useful.The result is that double probing attenuates as expected but does not have an appreciable impact on the ring frequency or the dampening.

author: simmconn
author_rank: Regular Contributor
timestamp: August 21, 2017, 04:04:48 am
content: I would suggest an experiment - if you have multiple boards from the same build.Cut the diff pair traces in the middle and connect a termination resistor to the Tx side of the cut. Measure the waveform at the resistor and see if the ringing frequency changes. It may help you confirm the issue is with the diff pair trace impedance. In your case the solder-on probe tips with damping resistors may work better than the hand-held browser tip.One thing you didn't change from one build to another is ordering the fab without impedance control. For your design the impedance control is too critical to cut corner on. The low-cost fab house put your design with others who didn't order the impedance control on the same panel, where the layer stack up is determined by the one design that ordered the impedance control. If you think the NRE for the impedance control is too expansive, find a vendor that's cheaper.Typically on a multi-layer board that has single-ended RF trace, we prefer to adjust the trace width to the same as the component pad width, in order to reduce the impedance discontinuity (you've seen it on a production board). That often means to void the GND layer below such that the trace uses the 3rd or bottom layer as GND reference, and/or to design the transmission line as co-planar wave guide. It's common on high-density boards using 4mil trace width for majority of digital circuits (50 to 65 Ohm), where you can't achieve 75 Ohm impedance by reducing the trace width further while maintaining the board cost. YMMV.For the 75 Ohm RF trace I'd prefer arranging the components in the order that they appear on the schematic. Those un-shielded inductors can interact with each other and other components if placed too closely or in parallel. Component connections to the GND or VCC is not to be treated lightly, either. A via can add considerable parasitic to the circuit. I would even avoid thermal relief. Do you have to make the board that small such that you need to pack those components?I'd highly recommend that you get a TDR setup. They are not as expensive as you might think. The one that is closest to the modern-day setup while still within a hobbyist's budget would be the Tek CSA803A with an SD-24 plug-in and a pair of P6150 probes. With some patience and luck you can have them on ebay for less than $800. The SD-24 has two TDR channels that allow you to measure differential and common mode impedance.About 10 years ago I was working in a consumer video company. We were to design an interface card that converts SDI/HD-SDI to/from plain LVTTL using the NSC Rx and Tx chips. With all the high speed PCB design knowledge we had at the time, we just couldn't get it to work at all after two iterations. In the end we had to call Genum for help and get their eval board since this is a one-off use case. The apps engineer from Genum wasn't surprised at our story and said many people can't get it right the first time. Apparently he's seen it a lot.I never touched SDI since.

author: rx8pilot
author_rank: Super Contributor
timestamp: August 21, 2017, 05:49:31 am
content: Quote from: simmconn on August 21, 2017, 04:04:48 amI have quite a few to play with and destroy if needed. What may make this proposed experiment even easier is that the 1st spin of the board had AC coupling caps on the differential lines that can provide an easy access point to break the line and terminate it. Not a bad idea to get a sense of how much the impedance is impacting the signal. Easy one, thanks. I did, in a previous experiment, remove the receiving device (U3) at the end of the differential trace and terminated in various ways to see if the ringing changed. I measured it open, 100 Ohms, and 200 Ohms terminated and only saw the amplitude change - not the ringing. The led me to believe the trace impedance of the PCB was not much of a contributor. Your suggestion is better as it should impact the frequency of the ringing when the trace length is cut in half.The solder-on tips, unfortunately, roll off at 3Ghz which will falsely look like an improvement. The browser tip (as far as I know is the only way to ensure a full bandwidth although it makes it quite difficult to use without a high precision probe positioner.Quote from: simmconn on August 21, 2017, 04:04:48 amThe first reason I went with uncontrolled PCB fab, was simply to make sure the basics were working before I spent the money. I am glad I did that, because the 1st revision had a few silly mistakes that had me quickly ordering a new revision. The 2nd revision was partly an experiment to see how bad it could be if I got an uncontrolled PCB. The stackup is was the standard PCBway but the FR4 is likely bottom of the barrel with major Er variation among other variables. At this time, I was assuming that any/all problems were related to an impedance issue on the PCB. I fixed another round of little details like anti-pads under the inductors and other high-speed passives, cleaned up a lot of little details and ran the third revision. Still the low-cost, uncontrolled PCB just so see if the changes I made had any positive impact. On this 3rd try, the final output was actually not too bad - a definitive improvement from the 1st revision. The internal differential signals were still a mess, however.At this point, I was really wondering if it is time to spend the money on the impedance controlled fab. One of the last experiment I did was soldered a wire to a ground via at the beginning of the 100 Ohm differential trace. I probed the end of the trace at the termination while moving the wire on and off the trace (in parallel, right between the pairs) expecting this to disturb the impedance enough to see on the scope. I saw no change at all - nothing. Not even a little. I figured it would change the impedance enough to see it, but I guess not.So I am still thinking that there may be a more fundamental issue outside of PCB impedance that is dominating. Although I don't mind spending the money on a controlled PCB, it would be a bummer if it made little to no difference.Quote from: simmconn on August 21, 2017, 04:04:48 amI think you may be right about the CPW - it seems like it would be easier to control, especially on low-cost boards as well as matching the AC coupling caps width. The weird and super tight arrangement is based on the intended mechanical restraints if I can get this into production. I had the option of making a 'dev board' to learn the basics of high-speed design with some elbow room. Then I thought I should just design it to fit the mechanics from the beginning. That way, when/if I get it dialed in, I will be ready to sell it as it is on the final revision. The layout of the inductors and other passives in the high-speed path have been a considerable challenge. I have read a number of app notes and studied the designs from similar products that seem to have reasonable performance. Without surprise - there is no clear answer. The current arrangement is definitely an improvement on the 1st revision. On inductor choice, I have not found much information on what is best. I ended up copying the choices from another manufacturer that makes SDI IO gear. I have little to no confidence that I chose the best inductors for the job.Quote from: simmconn on August 21, 2017, 04:04:48 amI have been looking at TDRs for a while now - it would be fantastic to be able to verify the PCB's when they arrive and add test coupons. I am looking at Agilent 54120B with 20Ghz TDR set. That will be enough to deal with 6Gbps SDI and possibly 12Gbps which is the latest standard. If they are not too hard to use and the probes and fixtures needed are not too bad - it will be a no brainer. I have no idea how much of a challenge they are to get accurate information that is usable.I will post the results of the half trace termination experiment you suggested. Thank you.

author: rx8pilot
author_rank: Super Contributor
timestamp: August 22, 2017, 02:37:11 am
content: I got a response from the field applications engineer at Gennum - excellent.The first suggestion was to adjust the input EQ and output de-emphisis on U2 which is the re-clocker in the middle of the chain. The traces are very short, so both of those registers should be on the lowest settings. No problem, except it is a problem. To adjust that, you have to have access to the SPI bus on the chip. While I broke out the communications on the back of the PCB to a 2.54mm header - it is 1v8 SPI and I only have a 3.3v Bus Pirate that could do the SPI. Wondering if I can bodge something together to level shift it enough to push a few bytes of data.(shockingly) He said the layout looks ok, but then mentioned the GND guards around the signals were a little too close. I went with a 2.5x trace width on the 100 Ohm differential and 3x trace width on the single ended 75 Ohm which I read as a 'guidline' distance in some app note. It was not calculated, simulated, or tested.The next thing he said that was VERY interesting is that I can send a PCB to him and they will measure the impedance and return loss with their TDR and/or VNA rig. That gets some answers and kicks the can down the road without me having to buy, rent, or otherwise, contract the test.So.....if anyone has an idea how I should hack a 3v3 bus pirate to work with 1v8 without having to wait for a digi-key delivery, let me know. I have a variety of bits and pieces, but its all 3v3 or 5v logic.Overall - a good report. Anyway, I may find that having access to the internal registers will allow adjustment to get this dialed in with device parameters - not PCB changes.

author: AndyC_772
author_rank: Super Contributor
timestamp: August 22, 2017, 06:01:30 am
content: If you have a 3v3 SPI master, just stick a 1:1 potential divider on its outputs, and use the 1v8 inputs directly.If it works, that's great. It probably will, at least for a few bytes in the lab. If not, at least it's only taken five minutes, and nothing will be damaged.

author: rx8pilot
author_rank: Super Contributor
timestamp: August 26, 2017, 06:17:20 pm
content: Ok - managed to hack together a 3v3 to 1v8 level shifter out of some N-FET's that works. A bit of a pain because they are SOT-363 dual FET's and all I had was a random Spark Fun experimenter PCB from 2012, 0805 resistors. Don't want to do that again - but it works.It took a while for me to make friends with the Bus Pirate since I had not used it in quite a while. The DUT needs 16bit SPI commands with no delay - and the Bus Pirate SPI mode can only send 8bits at a time. I found that the 3 wire RAW mode allows 16bit sends and receives, but it took a few hours to discover that option.Either way - I now have access to the internal configuration registers on the re-clocker chip GS6151 (U2). There are a myriad of adjustable parameters, but I was mainly interested in the input trace equalization, termination, output amplitude (swing), and the output de-emphasis. The rotten part is that the chip is not responding to those commands. It responds to some commands, but not others. I can successfully set a register and read it back out with no errors - but the chip continues to operate with the default settings. I even swapped chips just in-case my various experiments and probing damaged it. No change was noticed. It operates in at default settings and only responds to some commands like MUTE, DISABLE, etc.I sent the full setup and data to Semtech, but have not received a response from them yet. My guess is there is something about my setup electrically or the way the Bus Pirate is timing the transmission - I really don't even have a guess. Totally unexpected that some registers respond and others do not, even though I can read any/all of the registers and see the changes that I have commanded.Lets say that I can dial in the signal integrity with the register changes, that will be great for sure! The next problem is that the chip has no nonvolatile memory to store a user setup. If this is the solution, I will have to add a microcontroller to load the settings each time the device is powered up. I really don't want to add parts to an already over-loaded PCB.On another note - anyone have an opinion if this HP scope with TDR is appropriate for measuring trace impedance on a PCB? Assuming I would need to add probes/fixtures, etc.HP 54120B scope with HP 54121A TDR Set.