Starting with FPGAs - Page 1
Forum section: electronics / projects

author: JuniorJack
author_rank: Contributor
timestamp: September 13, 2013, 08:50:43 am
content: Hello,My first post. Great forum, i also love the videos, this is off course the reason i am here.So my problem, i can do almost anything electronics related, but never done any FPGA design. So i am complete newbie in this. I have acquired second hand dev board with Spartan-6 and started to play with few example projects i have in Verilog.My main question is how do you actually code/debug your projects. For example in the microcontroller world, i can make countless complies and load into the internal flash, etc. On the Xilinx IDE it takes something like 4-5 hours to generate the final bitstream. So any small change to the project would be too long wait. It would take months to develop something useful really.Should i be super proficient in Verilog first - make 100 % foolproof design on paper first and then go to the ISEand generate the files ? And completely forget techniques from the mc world ? Or maybe have separate mini projects with each module and test them one by one, and finally combine them, to reduce generation time ? Thanks!Regards, Chris

author: tszaboo
author_rank: Super Contributor
timestamp: September 13, 2013, 09:08:00 am
content: Yes, FPGA implementation takes horrible time, but that is just how it is. You are not making anything wrong. If you are serious about it, than use simulation for all block before you implement it. Also, debugging for xilinx is using "chipscope". You add it to your project, select the signal you wish to see, and it becomes a logic analyzer. it communicates through JTAG. Very useful, if you are actually using the fpga for something other than calculating stuff. Ideally, you only press the implement button, when you go to sleep.

author: JuniorJack
author_rank: Contributor
timestamp: September 13, 2013, 12:01:54 pm
content: Hi,Thanks for your reply! I am still doing my first steps, so it will take some time. I assume there is no way to speed up the ISE by extra RAM(i already have 32GB) or CPU with more cores, video HW, etc ?BR

author: mrflibble
author_rank: Super Contributor
timestamp: September 13, 2013, 12:54:05 pm
content: Well, some parts of the process can run on multiple cores, and some parts don't. More than 32 Gb isn't going to do anything unless you happen to have a really really large project, which I doubt if you're just starting out. ISE can work with up to 4 cores, anything more isn't going to do much.If your project takes 4 hours to get to the final bitstream then I think it's time to testbench more and place & route less. Then you only do a full PAR run when you think you have a good candidate. As opposed doing a full PAR for every little change.

author: MacAttak
author_rank: Unknown
timestamp: September 13, 2013, 03:52:02 pm
content: Compiling for testbench simulation is fairly quick - not too different from a typical code compiler. And you can get a lot of things debugged and fixed during simulation sessions. So yeah, what the others have said - time to start getting familiar with that.It is very analogous to how (good) software developers make use of unit testing suites to exercise the modules of their design before attempting to integrate everything together and compile the larger application.

author: JuniorJack
author_rank: Contributor
timestamp: September 14, 2013, 10:28:27 am
content: Hi,Thanks everyone for the tips! I will do some more reading(seems needed) before going further with this project.Regards, Chris

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 11:02:40 am
content: Quote from: MacAttak on September 13, 2013, 03:52:02 pmAnd on top of that, incremental compilation tends to be a lot better for simulation as well. So if you only change one source file, the next simulation run will be done compiling in no time. Sim runtime of course is still about the same.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: September 14, 2013, 12:22:24 pm
content: QuoteThat depends a LOT on the complexity of the design.Assuming you have a reasonably up-to-date PC, compile times of a minute or two are more typical for designs that aren't too taxing. 20-30 secs for trivial designs.It also helps if you develop on a bigger and/or faster device than you are eventually targetting, as it has to work less hard to fit it.

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 12:45:49 pm
content: Quote from: mikeselectricstuff on September 14, 2013, 12:22:24 pmheh, no kidding. For a design I was doing at the time I had to wait for a little over 1 hour for that sucker to complete. So I had enough of it and bought a new system + overclocked the crap out of it and got it to 12-15 minutes. The moral of that story is ... if you are considering getting a new PC anyways now might be a good time if you are serious about doing fpga stuff. Oh yeah, and both the old and new system were quad cores. I went from Q9550 to i5-2500k at that time.The tip about using a bigger device is also a good one, since that way the place & route doesn't have to spend that much effort to meet timings. But, be sure to check every now and then to see if it fits in the target device.

author: NiHaoMike
author_rank: Super Contributor
timestamp: September 14, 2013, 01:16:06 pm
content: What PC are you using? Last time I checked, Xilinx ISE is single threaded (at least for the free version), so if your PC is too outdated, I suggest something like a 4770k for an upgrade. Use a 212 Evo heatsink, a high end Delta fan with Cindy Wu drive, and some good BIOS settings to really make it go.I actually went from a 1.6GHz Core 2 Duo to a 3930k (overkill for ISE, but I do plenty of other stuff) since I was able to get a great deal on it.

author: Fsck
author_rank: Super Contributor
timestamp: September 14, 2013, 01:25:21 pm
content: Quote from: NiHaoMike on September 14, 2013, 01:16:06 pmthe new ISE versions are multithreaded as far as I know

author: AndyC_772
author_rank: Super Contributor
timestamp: September 14, 2013, 01:27:11 pm
content: 4-5 hours?! Yikes. The biggest design I've ever done compiles in under an hour using Altera's tool (Quartus) on a reasonable PC. Something is very wrong here.Are you storing your project on a network drive? That can absolutely cripple performance. I always work on a local copy of any project, and copy it back to a network drive at the end of the day.A trivial design should take a couple of minutes at most. If it doesn't, I'd be seriously re-thinking my choice of development board and tool chain.

author: Fsck
author_rank: Super Contributor
timestamp: September 14, 2013, 01:30:23 pm
content: Quote from: AndyC_772 on September 14, 2013, 01:27:11 pmI didn't think the free ISE could do a design that complicated, assuming a relatively modern computer. (assuming a smaller spartan6)specs of computer?

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 01:38:26 pm
content: Quote from: AndyC_772 on September 14, 2013, 01:27:11 pmThat would depend on how stupid the tools are and how crap your network config is. Case in point, I have all my design files on an nfs4 share (over regular boring 1gbit network) and it makes no difference in compile time vs local files. Just for the fun of it I also checked ISE installed on SSD vs HDD and that didn't make a dent in compile time either, especially for subsequent runs. I was expecting some performance gain what with all the small files, but nope. So the ISE install is back on boring old spindle.And with 4-5 hours I was wondering what design he was doing, can't be that small. Either that or he's really over-utilizing the fpga. What percentage utilization are you getting?

author: nctnico
author_rank: Super Contributor
timestamp: September 14, 2013, 05:20:33 pm
content: Quote from: JuniorJack on September 13, 2013, 08:50:43 amLong place & route usually indicates the constraints are too tight. Try to relax the timing on parts of the logic which don't need to be fast. In my designs I usually have 2 or 3 clocks with a low, medium and high frequency. Often a lot of logic is just managing some slow stuff so there is no need to use a high clock frequency. By using this method I have always been able to pack huge amounts of logic into an FPGA with short P&R runs. The internal PLL/DPLL of an FPGA makes it easy to generate various clocks (*2 or /2) with closely related edges so clock domain crossing is just a matter of using the right constraints to make a signal jump from a slow clock domain to a fast clock domain.

author: JuniorJack
author_rank: Contributor
timestamp: September 14, 2013, 05:58:26 pm
content: Hi,As i said, i am complete newbie to FPGA design, so not everything suggested about using simulation makes sense to me yet. But my PC is kinda ok-ish, was top of the range last year - i7 3930k 3,20 Ghz, asus rampage extreme 4 mobo, 32 Gb of quad channel RAM, HD is Samsung SSD 830. My video card is not something worth mentioning, but i have few 5970's laying around, i can put them in, if this would help somehow. The project is on the local, SSD drive, not using network storage.A simple example like this:Code:entity ucecho isport(pc : in unsigned(7 downto 0);pb : out std_logic_vector(7 downto 0);CS : in std_logic;CLK : in std_logic);end ucecho;architecture RTL of ucecho is-- signal declarationsignal pb_buf : unsigned(7 downto 0);beginpb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z');dpUCECHO: process(CLK)beginif CLK' event and CLK = '1' thenif ( pc >= 97 ) and ( pc <= 122)thenpb_buf <= pc - 32;elsepb_buf <= pc;end if;end if;end process dpUCECHO;end RTL;will take something like 20-30 minutes. The example i was talking about (the one that took the whole morning) is here:https://github.com/fpgaminer/sha1_colliderIt has two instances of SHA-1 (unrolled) and some jtag debug and display control (as far as i can read the code).It is not my code, i was just curious to play with it, and learn, no pressure or deadlines.Regards

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 06:03:52 pm
content: No way that the aboveucechoexample should take 20+ minutes on a machine like that. Are you sure you don't use any over the top constraints? When you do a PAR run, check the logs to see if you see any messages indicating that it tries and retries and retries to find a mapping solution...

author: JuniorJack
author_rank: Contributor
timestamp: September 14, 2013, 06:07:32 pm
content: Quote from: mrflibble on September 14, 2013, 06:03:52 pmI am sorry, i was expecting when having example, with provided .xise project file - all those are somehow auto loaded.

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 06:10:07 pm
content: Can you attach a zip with the entire project? If you want I can take a look at it. Also, what version of ISE are you using?

author: JuniorJack
author_rank: Contributor
timestamp: September 14, 2013, 06:14:53 pm
content: Quote from: mrflibble on September 14, 2013, 06:10:07 pmI got it from here:http://www.ztex.de/downloads/ztex-121017.zipit's in the \ztex\examples\usb-fpga-1.15y\ucecho\fpga directory, ISE v is 14.4. Thanks!Update: I am sorry, my previous post was bit misleading, the clear example full generation takes 2 minutes (the 20-30 minutes was with an extra added file, my bad). But the SHA-1 project really takes 3-4 hours here.

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 06:26:33 pm
content: If the example you linked to is the one you posted AND that takes about 2 minutes .. then no need for me to download it.2 minutes sounds plausible, just the 20-30 minutes you originally mentioned would be excessive. So I guess it would depend on your extra added file...And crypto related projects taking 4 hours for a PAR, yeah that can happen. For the SHA-1 projects, the previous hints still apply:- check the synthesis logs to see if device utilization is high. if so, try again using a bigger device.- check constraints to see if they are not excessive.

author: JuniorJack
author_rank: Contributor
timestamp: September 14, 2013, 06:33:45 pm
content: Quote from: mrflibble on September 14, 2013, 06:26:33 pmThanks, sorry didn't wanted to waste your time, posted the link and then decided to re-check. Then i realized i have anextra file added.Going to bigger device is not an option for me, i got this board and was very curious how such board with 4 chips compare against ATI5970 with 3200 processing cores that do the same task in parallel.Will try to follow all suggestions off course.Regards

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 06:37:01 pm
content: Quote from: JuniorJack on September 14, 2013, 06:33:45 pmThe bigger device is just a sanity check. If the device you currently use (your real target device) takes 234986234 years to finish a PAR run, and then when you change it to a bigger device and that suddenly takes 3 minutes ==> big hint you are over-utilizing the fpga. And it's a bit of a shame to waste time waiting on PAR runs if that happens to be the case.

author: NiHaoMike
author_rank: Super Contributor
timestamp: September 14, 2013, 06:40:53 pm
content: What are your CPU temperatures under full load? The 3930k runs very hot and you won't get good results with cheap heatsinks and fans.(By cheap, I mean really cheap. $30 for a heatsink and $30 for a fan are good enough.)

author: JuniorJack
author_rank: Contributor
timestamp: September 14, 2013, 06:41:17 pm
content: Quote from: mrflibble on September 14, 2013, 06:37:01 pmWait, you mean just select bigger device in the project settings, not physically using it ? Then simulate all in the ISE, sowhen everything is completed to satisfactory level, select correct device and generate final bitstream that will be loadedin config memory ?

author: JuniorJack
author_rank: Contributor
timestamp: September 14, 2013, 06:44:28 pm
content: Quote from: NiHaoMike on September 14, 2013, 06:40:53 pmTo be honest i haven't checked temperatures during the long run to generate that project, but i will try to monitor the next time. I have some huge and heavy heatsink with two fans (can't remember the name), it is not the stock cooler that comes with the CPU. But will double check this next time.

author: NiHaoMike
author_rank: Super Contributor
timestamp: September 14, 2013, 07:01:11 pm
content: Also check your case temps and BIOS settings. The highest recommended operating temperature for a 3930k is 67C. Mine runs in the low 60s at full load during the summer.You can't use a stock cooler on a 3930k because there isn't one. (There is a reference design cooler, but that's not exactly a "stock cooler".) Also try using i7z to get detailed stats.

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 07:02:02 pm
content: Quote from: JuniorJack on September 14, 2013, 06:41:17 pmPrecisely. If your design just barely fits in the fpga then the Place & Route has to expend some serious effort to squeeze it all in. If you give it a nice bit of room to work with suddenly things are a lot faster. This approach is not the end-all solution for all cases, but sometimes it can save you a nice bit of time. Especially when you're just trying to figure out how everything works...

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 07:05:15 pm
content: And on the topic of overclocking & cpu temps ... for fpga work that takes to long I overclock my i5-2500k to 4.7 GHz with a non-stock cooler and it gets to about 60-65 degrees C. This one overclocks to just about 4.9 GHz but I like a bit of margin for stability.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: September 14, 2013, 07:09:27 pm
content: Quote from: JuniorJack on September 14, 2013, 05:58:26 pmThat simple example should take well under a minute - something is clearly very wrong.First suggestion would be to remove ALL timing constraints and see what happens.

author: marshallh
author_rank: Unknown
timestamp: September 14, 2013, 07:11:05 pm
content: Synthesis and fitting for one fully unrolled sha256 core (target is Arria IIGX) takes about 2 hours on my machine. Phenom II X4 @3.9ghz, 16gb ram.I use a disk filter driver called SuperCache that turns 8gb of my main RAM into a hard drive cache. After the first copmile all the files are living in RAM so after that my HDD is almost never even touched (it does delayed write flush too, fine if you have a UPS

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 07:15:25 pm
content: Quote from: mikeselectricstuff on September 14, 2013, 07:09:27 pmSeethis postlater in the thread."Update: I am sorry, my previous post was bit misleading, the clear example full generation takes 2 minutes (the 20-30 minutes was with an extra added file, my bad)."

author: JuniorJack
author_rank: Contributor
timestamp: September 15, 2013, 01:15:56 pm
content: Quote from: mrflibble on September 14, 2013, 07:02:02 pmThank you! That makes sense. Specially at this stage, where the only thing that makes sense to me is the RTL schematics,the Verilog syntax is still Chinese to me.