Please Comment On My Schematic And PCB Layout For This Small FPGA Project - Page 1
Forum section: electronics / projects

author: JoeN
author_rank: Frequent Contributor
timestamp: March 23, 2017, 04:31:42 am
content: The goal of this project is to implement an Altera MAX 10 FPGA into a small board with headers to use it is a digital pattern generator to exercise other circuits. It will have 32 outputs, well, because that is what I decided on. It will be controlled from a desktop app via USB. The MAX 10 part is a 3.3V part, to allow for 5V outputs I am using 75HCT541 buffers to do the 5V translation. Regulation via AMS1117-5.0 and AMS1117-3.3, 7V input. To keep the USB simple I am using a MPC2200 which is USB-to-GPIO. I plan to simply clock data into the FPGA. I don't want to use a USB-to-UART IC because then I am looking at some sort of UART state machine which I can't visualize as easily as a shift register. In general, the whole design is made to be similar to Altera's reference design with respect to the JTAG, bypass capacitors, clock design, reset circuit design, etc. The differences is that I am hanging the MCP2200 and four 75HCT541s off that design and using cheap linear regulators that I already have. At least that is the idea.Hopefully, my PCB layout doesn't suck. This is the most complex design I have done by hand. No auto-routing this time. I try to run similar signals together and with the same trace lengths. Four layers, top and bottom are signal, one ground, and one is split between 3.3V and 5.0V, with 5.0V running under the buffers as they are the only part that runs at 5.0V. Take a look at how I split that and run the output of my 5.0V regulator to it. Is that split copper pour and how I run the trace to 5.0V sane or not? Overall, is the design OK, sane, or could I do better? How is my decoupling situation around the FPGA, regulators, and buffers?Attached is what I think you need to see plus Altera's reference design. Thanks!Notes to self so far: Need silk-screen for the output section. Need to make my 3V3 via from the regulator to the copper pour on the inner layer bigger, at least as big as the one I did for 5V0.https://www.eevblog.com/forum/projects/please-comment-on-my-schematic-and-pcb-layout-for-this-small-fpga-project/?action=dlattach;attach=301808

author: ncoonrod14
author_rank: Contributor
timestamp: March 23, 2017, 04:53:52 am
content: Some best practices that your layout could do better. Yours may or may not be good enough for your application but these would improve it.-Pins 1&2 should have their own via to the power layer, not that dinky little trace-Your schematic has the right idea with decoupling caps, but most of them are far from the parts you're intending them for.For example, you've got a border of caps on two sides of the fpga, those would be more effective on the bottom side right beneath each power pin. Also on those shift registers, vcc is on pin 20, but your caps are clear on the other side of the part from there. Not going to do much good there. Same with the MCP2200, put that cap right next to the pin and get rid of that curvy trace.-GND vias on your regulators need to be way bigger, also bring those caps in closer-What's up with the crystal and usb port overlapping?-Why is the reset button on the bottom?Does it absolutely have to be that tiny? If it has a specific requirement then fine, but why design it with parts literally touching the connector silkscreen? Give em some room.

author: JoeN
author_rank: Frequent Contributor
timestamp: March 23, 2017, 05:05:20 am
content: Quote from: ncoonrod14 on March 23, 2017, 04:53:52 amAre we talking about the three pin power connector? The problem is that I reserved the whole power plane for 3V3 and 5V0, there is no room right now for VIN. Can't I just make the wider larger? I keep the regulators close to the power connector for a reason. And it's my biggest trace already.Quote from: ncoonrod14 on March 23, 2017, 04:53:52 amOK, I was very lazy here. Each capacitor's 3V3 pin is near a 3V3 pin on the FPGA. Obviously I messed up on the buffers. In a lot of cases I could add a copper trace there directly to the pin and make it even closer, I meant to do that and forgot. I have to think more about putting them on the bottom, that's possible too. Those vias do need to be made bigger, big mistake.Quote from: ncoonrod14 on March 23, 2017, 04:53:52 amThanks, that was a mistake.Quote from: ncoonrod14 on March 23, 2017, 04:53:52 amThat was intended, I can't figure out where else to put it and there is some room there and close to the reset pin too. It's a hobby project, I am not thinking of this sticking out of an enclosure. Maybe I should, maybe I will want one.Quote from: ncoonrod14 on March 23, 2017, 04:53:52 amI am cheap. $10 per in2at OSHPark. I was trying to keep it small. I would think small would help signal integrity anyway.

author: ncoonrod14
author_rank: Contributor
timestamp: March 23, 2017, 05:11:33 am
content: QuoteI was referring to the fpga pins 1 & 2 being tied to vcc through a trace from pin 144. Don't see an issue with your input connector or trace.QuoteFor a hobbyist project, you can probably get away with it. But still not best practice and the cost of doing it is free.

author: JoeN
author_rank: Frequent Contributor
timestamp: March 23, 2017, 05:17:01 am
content: Quote from: ncoonrod14 on March 23, 2017, 05:11:33 amI am definitely going to clean all that up and get them as close as possible, probably tomorrow, after getting all the suggestions together.Quote from: ncoonrod14 on March 23, 2017, 05:11:33 amThanks. I will clean that up too. The software was saying broken net there even though it had vias down to the power later and I put that trace in trying to remedy the problem and figure out if it was a bug in DipTrace or what. I figured out that it put the vias in blindly (I used the "fanout" feature in Diptrace) in some cases when the copper was gone underneath because of the big 5V0 trace, and then catching the problem. Now that I know what is going on with those pins I will get rid of that ugly trace and make sure each pin has its own via to the power layer.

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: March 23, 2017, 05:45:42 am
content: I like to make sure my FPGAs have some sort of clock brought in to a clock-capable pin. This lets me implement synchronous logic within the FPGA if the need arises. It also makes testing the FPGA easy (counter, output to an LED). An LED or two to a GPIO might be good too, for the same reason. Also, consider breaking out the UART signals to a header, they can come in handy during a debug session.Wise words from Bunnie:

author: JoeN
author_rank: Frequent Contributor
timestamp: March 23, 2017, 06:35:31 am
content: I have a 50Mhz clock going to CLK0p (pin 27). This is the same arrangement as Altera's reference design. Is that not sufficient? That extra header idea is not a bad one, I might find room for it somewhere. I'm starting to think I might want an external SRAM on this somewhere and I might just add that on too.

author: krish2487
author_rank: Frequent Contributor
timestamp: March 23, 2017, 08:41:45 am
content: One another suggestion I can think of is in the schematic area.The neat net wires look good but it is a industry practice ( for ease of explaining and detailing) to use buses for a bunch of related connections.In this case it is not important but improves readability quite a bit in general.

author: CM800
author_rank: Frequent Contributor
timestamp: March 23, 2017, 09:40:50 am
content: Nice job!I'd break out all the GPIOs with a high density board-to-board, something like this:http://www.te.com/usa-en/products/connectors/pcb-connectors/board-to-board-connectors/intersection/fine-pitch-connectors.html?tab=pgp-storyhttp://www.te.com/usa-en/products/connectors/pcb-connectors/board-to-board-connectors/intersection/free-height-connectors.html?tab=pgp-story... look nice.If you break them out in a style similar to this, as differential pairs: (throw some resistor pads on there if you want to do terminations or something.GND PAIR GND PAIR GND PAIR GND 3V3 3V3 GND PAIR GND PAIR .....then you could future proof in case you want something high speed.

author: Someone
author_rank: Super Contributor
timestamp: March 23, 2017, 09:45:47 pm
content: Quote from: JoeN on March 23, 2017, 04:31:42 amWith such a low density design there should be rare need for more than 1 via in any of those traces coming from the FPGA, you need to go back and do some pin swapping to untangle the routing.Quote from: JoeN on March 23, 2017, 04:31:42 amThis depends on the stackup of the board as to where the bypass caps are best situated and if vias or traces would be more appropriate for connecting them to the power pins of the FPGA. But that 5V supply being run across the 3V3 plane and cutting the bypass caps apart is obviously really really bad without needing to go into any simulations. Either put the 5V regulator where its needed or run the distribution trace around the 3V3 plane.This board would be a good candidate for a 2 layer design.

author: Scrts
author_rank: Frequent Contributor
timestamp: March 24, 2017, 12:08:43 am
content: Add all the pinout to the Quartus project, assign the pins and try to synthesize. Sometimes I've got VREF pins, that can't be used. Or CLK pins are inputs only... or whatever it is. Be sure to check before sending to the fab!

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: March 24, 2017, 12:55:46 am
content: All right, here's my comment:http://www.ebay.ca/itm/Mini-Core-Altera-Cyclone-IV-FPGA-EP4CE6E22C8N-4Mb-Flash-Development-Board-Module-/162276703486?hash=item25c871fcfe:g:1dsAAOSw44BYJU~XAnd that's with the parts. Assembled.

author: JoeN
author_rank: Frequent Contributor
timestamp: March 24, 2017, 02:28:25 am
content: Quote from: Alex Eisenhut on March 24, 2017, 12:55:46 amNeat, I guess I could just breadboard all the buffers and the USB IC and I'd be all set.

author: JoeN
author_rank: Frequent Contributor
timestamp: March 25, 2017, 06:51:59 am
content: On a circuit such as this, does it make sense to have output resistors to protect the output of the buffers? If so, should they be scaled such that if all outputs are shorted it protects the IC both with respect to maximum pin currents and also maximum supply currents? I am thinking that the answer to this question is an obvious yes, but what is the downside of protecting the outputs with resistors other than just increasing BOM costs and the size of the PCB a bit? Anything?