Strange ADC behavior at lower voltages using an MSP430  - Page 1
Forum section: electronics / projects

author: smoothVTer
author_rank: Regular Contributor
timestamp: December 19, 2019, 10:50:05 pm
content: I'm using an MSP430F5172 uC and reading a battery voltage at 500ms intervals. Here's the circuit below for sampling the battery voltage:When EN_VBATT_READ goes high, the voltage divider is active. The divider divides down at a ratio of 1:0.7848 so that a max input voltage from VBATT = 3.2V results in an output voltage of ~2.5V at VBATT_DIV. The MSP430 is set up with a VREF=2.5V so 3.2V input gives full scale 10-bit output of 0x3FFF. When EN_VBATT_READ goes low, the divider is off, no current is consumed.Cap C32 is there to act as a LPF but also to help hold up the voltage during the ADC sampling time. The relatively low values of the resistors in the divider allow me to achieve a low input impedance to the ADC.At VBATT input voltages between 3.2V ~ 2.1V, the ADC readings are spot on, within 1 or 2 counts. Nice. The scope shot below shows the resistive divider turning on ( YELLOW trace is VBATT_DIV ). There is a delay for settling on C32 to charge up; then the green trace goes high ( start of ADC conversion ), then the green trace goes low ( end of ADC conversion )As VBATT input goes lower, the VBATT_DIV waveforms gets weird. By weird I mean it doesn't reach the steady-state value I expect, and when the conversion is complete, there is a little hump. VBATT input for the scope shot below is 2.0V:And at 1.9V, the VBATT_DIV waveform is not stable at all and has a big dip:The end result is the low end of VBATT input voltage reads are far off from what is expected. My guess is that the ADC is loading the analog input pin more than I expected. Datasheet states ADC input impedance is anywhere from 36k to 96k & 3.5pF, which is much higher than the ~887 ohm impedance of the divider. So I don't see how this could be the case.Also, I don't understand why this effect wouldn't be seen for higher input voltages too. I've tried all combinations of sampling time and conversion clock...in the end it doesn't really matter. Lower input voltages also give this bumpy waveform in the VBATT_DIV analog input pin.Any ideas what might be the matter?

author: jmelson
author_rank: Super Contributor
timestamp: December 19, 2019, 10:53:20 pm
content: As VBATT decreases, the gate voltage available to turn on the transistor is also reduced, thereby leaving it less than saturated.Jon

author: smoothVTer
author_rank: Regular Contributor
timestamp: December 19, 2019, 11:00:36 pm
content: Sorry, I forgot to mention:The power supply to the uC is a TPS610994 boost regulator, run off of VBATT; even at an input voltage of 1.5V ( which VBATT can never reach) it outputs a stable 3.3V rail to the uC. In this test setup I am running from a benchtop power supply, and I am not hitting any current limits. Current consumption is about 5mA during active mode while the main program is running.Probing on the uC DVCC and AVCC pins shows a solid and stable 3.3V rail.

author: iMo
author_rank: Super Contributor
timestamp: December 19, 2019, 11:13:41 pm
content: Why not drive the gate of Q2B directly by EN_VBATT_READ (inverted in sw)??PS: it may not help you - as indicated above the Q2B's Vgs may not be high enough to fully open it (it is a pmos) with lower Vbatt.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 19, 2019, 11:37:24 pm
content: Vgs(th) max -2.6V.How the most negative number is "max", well, go figure, but that's pretty marginal -- consider an analog switch, or a lower threshold transistor.Could also use a bootstrapped N-Ch, since you're just reading pulses at a time. The bootstrap supply can be the 3.3V main supply, avoiding threshold problems entirely.Tim

author: iMo
author_rank: Super Contributor
timestamp: December 19, 2019, 11:39:08 pm
content: I used to use this "zero current divider" in past - with toggling the EN pin from log1 (idle) to log0 it opens the M1 for some milliseconds, during that time you have enough time to read the ADC, afterwards it closes the M1.PS: also the Vgs goes from Vbatt (idle) to Vbatt-3.3V after 1/0 transition, what is a pretty nice bonus

author: smoothVTer
author_rank: Regular Contributor
timestamp: December 20, 2019, 01:45:11 pm
content: Interesting, I'll have to try this at some point either in simulation or on the bench. Is this considered a "bootstrapped nfet"?

author: Kleinstein
author_rank: Super Contributor
timestamp: December 20, 2019, 03:38:23 pm
content: This is not a bootstrapped nfet. The MOSFET is still PMOS, but the gate is AC coupled. It is a nice idea, as long as the on time is only a small fraction of the total time.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 20, 2019, 05:25:24 pm
content: Even better actually, it doesn't require extra drive circuitry.It does assume the supply voltage changes much less than the sample pulse; which should be a fine assumption for a battery.Tim

author: iMo
author_rank: Super Contributor
timestamp: December 20, 2019, 06:25:00 pm
content: I've added your 10nF capacitor C2 to the divider. Also 2 diodes simulating the ADC input.In that setup from the 1->0 EN edge it takes about 130us to reach the max (within 1uV) at the C2 and then another 230us to drop by 100uV at C2.

author: smoothVTer
author_rank: Regular Contributor
timestamp: December 23, 2019, 06:24:37 pm
content: So it all turns out the NFET was turning on fully, but the PFET was not due to the lowered source-to-drain voltage when VBATT was low. The PFET in the DMC3400 device had a max Vth of -2.6V ! So, my bad on that miss.Luckily, I found another pin-for-pin compatible NMOS/PMOS pair in the same SOT-363 package: the DMG1016UDW which has a max Vth of 1.0V nmos / -1.0V pmos. So don't have to do another board rev, only a BOM revision.Thanks for chiming in everybody! When I have time I will look into doing this a bit simpler using one of the suggestions above.