hybridfree/eevblog-posts huggingface dataset:
suitable PCB strategy question - Page 1
Forum section: electronics / general

author: john23
author_rank: Frequent Contributor
timestamp: February 22, 2024, 02:24:16 pm
content: Hello, in the attached schematics i have multiple Ic's.In order to make the PCB optimal i have placed all IC bias PLUS's on one side and minuses on the aother side as shown in the attached photos and ALTIUM files.given this strategy what is the best place to put the connector?Thanks.

author: coromonadalix
author_rank: Super Contributor
timestamp: February 22, 2024, 03:23:30 pm
content: i think j1 should be the opposite sidewhen you get many crossing lines over items, some rework is needed if you want to keep pcb layers count low 2 layers vs multiplesparts placement / surroundings etc ... / rotation can help too

author: Doctorandus_P
author_rank: Super Contributor
timestamp: February 22, 2024, 06:54:41 pm
content: This is a very simple PCB. Combined with the fact that 2 layer PCB's are the same price as single layer PCB's routing is pretty much trivial in this case. For the connector, I would pick a place that is convenient for plugging in the connector in your applications.When PCB's get more complex the goal is to reduce the amount of ratsnest lines crossing each other. A much more important consideration is to use a good GND plane on your PCB. I've seen many PCB's with badly designed GND planes, for example by tracks cutting the GND plane into little pieces.

author: jpanhalt
author_rank: Super Contributor
timestamp: February 22, 2024, 08:05:39 pm
content: I'm just a hobbyist and don't deal with high frequencies. I generally route everything except VCC and GND first. In fact, I tend to hide those airwires. Once signals are done, placement is very important, I turn to VCC and make adjustments, if reasonable. Finally I do ground usually as a pour. VCC can be kept direct and wide on the bottom layer. I am sure others may disagree, but my boards have have worked OK for me.

author: john23
author_rank: Frequent Contributor
timestamp: February 24, 2024, 08:38:09 pm
content: Hello , I have added +15V and -15V and done polygon pour.also i added two resistors which are not in the schmatics (i changed the netlist :-) )I have signal and DC routing on the buttom layer.DC and signal needs ground on the top level to funcrion properly.Given my situation below, will the signal path which is routing from teh ground will function properly?PCB file is attached.Photos of the PCB and me explaining the pcb is attachedVideo of me explaining is attached in the link.Thanks.https://drive.google.com/file/d/1Hp9E77g35tRJYJtdxl_8wI2taxFJiWnV/view?usp=sharing
Understanding Low Noise Regulated Charge Pump DC-DC Converter - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: February 21, 2024, 03:52:35 pm
content: Hi,I need to understand the functionality of this device CAT3200, CAT3200-5 which is low noise regulated charge pump DC-DC converter. There is no inductor.The link to the datasheet is here.https://www.farnell.com/datasheets/1837060.pdfI was looking at Figure 15 and Figure 16 on page 3. I am wondering if the general principle of DC-DC converter that output power is something around 80 % of the input power also applies to this device as well or not ?

author: joniengr081
author_rank: Regular Contributor
timestamp: February 21, 2024, 04:34:20 pm
content: I mean if the output voltage is higher then the input voltage then the input current must be higher then the output current, right ?

author: thm_w
author_rank: Super Contributor
timestamp: February 21, 2024, 10:37:44 pm
content: Your question is efficiency which is given right in the datasheet you linked.Here is an explanation:https://www.allaboutcircuits.com/technical-articles/switched-capacitor-circuits-charge-pump-circuit-basics/This is more suited forhttps://www.eevblog.com/forum/beginners/

author: joniengr081
author_rank: Regular Contributor
timestamp: February 22, 2024, 08:51:42 am
content: Thanks for this article. I have read this article and understand how charge pump regulator it works. And comparison with switch mode regulators and linear voltage regulators.Basically, they are more efficient then LDO, cheaper, no inductor, but offer low output current and bit higher output voltage ripples.

author: joniengr081
author_rank: Regular Contributor
timestamp: February 22, 2024, 08:54:36 am
content: If we have 4 V and 30 mA from a buffer and we need 5 V and atleast 50 mA to drive a relay for example. Can I use charge pump regulator in this application ?In order words, can I get higher voltage and higher current at the output then input ? That's the main question.

author: Kean
author_rank: Unknown
timestamp: February 23, 2024, 12:36:22 pm
content: If that is the main question, then you really should be posting in the beginners forum.And the answer is of course not. You cannot have a component/circuit outputting more power than its input. That would be >100% efficiency!
LTpowerCAD shuts down for no reason? - Page 1
Forum section: electronics / general

author: Faringdon
author_rank: Super Contributor
timestamp: March 02, 2023, 08:46:53 pm
content: When i open LTpowercad to do a "supply design", i put in the vin , vout and fsw, then click "search"...then a list of controllers come up, and when i scroll down to them...LTpowerCAD just disappears off the screen and is closed.I use windows 10, 8GB RAM.Do you know whats wrong.?

author: reynaldogonzalez
author_rank: Contributor
timestamp: February 19, 2024, 09:17:12 pm
content: Not sure if this would help this specific case, (however replying in case it might help others with crashing).I was having a similar crash / shut down whenever I tried to open a saved file.After clicking Sync/Release in the main menu, and going through the update, it solved my crashing issue.
Simulating boards with multiple layers in QUCS Studio - Page 1
Forum section: electronics / general

author: ftg
author_rank: Frequent Contributor
timestamp: February 16, 2024, 04:45:15 pm
content: As it says on the topic, has anybody managed to simulate multilayer boards inQUCS StudioLike 4-layer boards with traces in the middle layers or openings in the layer 2 copper under pins in SMA edge launches?Even the different Er in the prepreg and core seems to be undoable?I would have asked on the QUCS Studio forums, but the registrations there seem to be closed, likely due to the tons of spam.
Altium to be sold - Page 1
Forum section: electronics / general

author: GreggD
author_rank: Regular Contributor
timestamp: February 15, 2024, 08:08:46 pm
content: Renesas to purchase PCB design software company Altium for US$5.9 billionhttps://www.digitimes.com/news/a20240215PD201/renesas-acquisition-altium-pcb-design.html

author: ataradov
author_rank: Super Contributor
timestamp: February 15, 2024, 09:02:32 pm
content: There are already multiple topics on this.
zig zag pad spacing for self clamping connector - Page 1
Forum section: electronics / general

author: lk.dgironi
author_rank: Regular Contributor
timestamp: February 07, 2024, 01:18:05 pm
content: Hello,I would like to add a self clamping connector using zig-zag pad (see "Connectorless-AVR-ISP-connector" image for reference, found online)On PCB I'm going to add three (or more) pads. My pad has 1mm hole drill, 1.8mm copper diameter, and 2.54 horizonal spacing, cause I'll going to use 2.54 pin header spacing male connectors (see image: "61300311121")I'm wondering how much vertical spacing dis alignment is good enough to self clamp the pin header connector (reference "?" on "Capture1" image), if any have experience on that.

author: Kean
author_rank: Unknown
timestamp: February 07, 2024, 02:46:48 pm
content: Sparkfun has footprint libraries with "LOCK" footprints like this. The offset they use is +/-0.127mm from the centreline.I've found they kind of work, in particular to ease assembly. But when used repeatedly, the mating connector will get bent out of shape and the locking effect decreases.

author: berke
author_rank: Frequent Contributor
timestamp: February 07, 2024, 05:07:34 pm
content: Quote from: Kean on February 07, 2024, 02:46:48 pmHow about getting one of these:https://www.pomonaelectronics.com/products/test-clips/soic-clip-8-pinThen you use some Dupont clips to go to your programmer, ~20 bucks.

author: lk.dgironi
author_rank: Regular Contributor
timestamp: February 08, 2024, 04:00:18 pm
content: I've check found the LOCK library. It's like you saying +-0.127mm, so 0.254mm horizontal spacing for the 2.54mm standard pin header.Thanks!I'm going to use this connector just once or two in the product lifetime, maybe it will never been used. Cause it's just a test point.
PCB Layout Critique - Page 1
Forum section: electronics / general

author: 2XL
author_rank: Newbie
timestamp: February 07, 2024, 03:00:22 am
content: Is there a place on this forum or another forum to post portions of my PCB layout for others to comment, critique, suggest improvements? Thank you.

author: jpanhalt
author_rank: Super Contributor
timestamp: February 07, 2024, 08:44:59 am
content: It looks like you are in the right place. One also sees such posts in beginners sections.

author: selcuk
author_rank: Frequent Contributor
timestamp: February 07, 2024, 09:16:50 am
content: This forum is the right place. People use "Beginners" and "Projects, Designs, and Technical Stuff" sections for that purpose. This section is mostly used when you have an issue with the CAD software.
IPC standards for PCB  - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: November 17, 2023, 02:58:29 pm
content: I am wondering about the IPC standards related to PCB design and fabrication. I found the standard names, see attachment but not their full documentation. I am not sure if they are free to download. I found at one website IPC 4101 which is not free to downloads. Is that true that these IPC standards are paid downloads ?

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 17, 2023, 09:58:05 pm
content: Yes.

author: joniengr081
author_rank: Regular Contributor
timestamp: November 18, 2023, 10:04:12 am
content: How about ESA standards ? Are they downloadable ? I am looking for standards on PCB materials and stackups. I have tried and found some ESA soldering standard ECSS-Q-ST-70-08. Do we have ESA standards on PCB materials and stackups ?

author: Hawaka
author_rank: Regular Contributor
timestamp: November 18, 2023, 11:07:38 am
content: Quote from: joniengr081 on November 18, 2023, 10:04:12 amThere is this website, but it's all pretty old and not maintained.http://esmat.esa.int/Specifications/specifications.htmlBTWhttp://esmat.esa.int/ecss-q-st-70-08c.pdfis pretty nice if you wanna learn a thing or two about soldering and mounting component

author: joniengr081
author_rank: Regular Contributor
timestamp: November 18, 2023, 01:01:35 pm
content: Yes, that's true.I also have looked at ECSS-Q-ST-70-38 whis is SMD assembly and soldering standard. It's also good.But do we have standards on PCB materials and stackup ?

author: Hawaka
author_rank: Regular Contributor
timestamp: November 19, 2023, 10:46:09 am
content: This two would probably be what you are looking for:http://esmat.esa.int/ecss-q-st-70-10c.pdfhttp://esmat.esa.int/ecss-q-st-70-11c.pdf

author: m98
author_rank: Frequent Contributor
timestamp: November 19, 2023, 02:15:45 pm
content: All ECSS standards can be accessed here:https://ecss.nl/

author: Damperhead
author_rank: Contributor
timestamp: February 07, 2024, 07:34:51 am
content: Yes, they are not free, but if you want to work professionally with PCB manufacturers and EMS, they are worth it.https://www.ipc.org/ipc-standards-related-resources

author: selcuk
author_rank: Frequent Contributor
timestamp: February 07, 2024, 08:46:15 am
content: The university libraries here have access to many international standards. They normally have an academic account connected to their IP address and you can read the online documents in the library. If you have a university close to you, I recommend to check out.
LTspice IF statement syntax - Page 1
Forum section: electronics / general

author: Faringdon
author_rank: Super Contributor
timestamp: February 04, 2024, 01:36:06 pm
content: Hi,The attached doesnt work in changing the duty cycle. Do you know the "IF" syntax which will unlock the required action?

author: berke
author_rank: Frequent Contributor
timestamp: February 04, 2024, 01:51:47 pm
content: You can't change the parameters of a PWL dynamically, but you can do what I think you're trying to do using a behavioural voltage source like this.

author: Kean
author_rank: Unknown
timestamp: February 04, 2024, 02:29:24 pm
content: I don't think the IF math function can be used just on its own, so you need to use it as part of the .param definition or as the expression on a behavioral voltage source.

author: Zero999
author_rank: Super Contributor
timestamp: February 05, 2024, 06:47:55 pm
content: Use a comparator to generate the PWM. The UniversalOpamp2 model can be used to make an ideal comparator. Note I upped the gain, slew rate and GBWP to mimic a very high speed comparator.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 06, 2024, 12:12:07 am
content: You can't step a *parameter* during simulation as far as I know anyway. Parameter stepping triggers a different simulation for each value and gathers all results after that.Use a behavioral voltage source instead to implement this, and look at the list of all functions available for these.

author: Ian.M
author_rank: Super Contributor
timestamp: February 06, 2024, 05:02:39 pm
content: Yep, anything in braces (required for .param parameter usage) is evaluated before the individual simulation run starts and treated as a constant for the duration of that run. .step causes multiple runs, changing the parameter before each.Only behavioral*component's user defined expressions are evaluated at each timestep during each run. Note that if the expression is discontinuous or to a lesser extent has a discontinuous derivative, the simulation is likely to drastically slow down near each discontinuity.I posted an example of how to do voltage controlled PWM here:https://www.eevblog.com/forum/eda/ltspice-pwm-input-signal-creation-for-motor-soft-start/Its very similar to Zero999's suggestion above.* Documented: behavioral voltage and current sources; Undocumented:behavioral resistors

author: Zero999
author_rank: Super Contributor
timestamp: February 06, 2024, 10:37:44 pm
content: I tried the differential Schmitt and the rise/fall times were slow. Changing trise and tfall to 10ns didn't help. I tried setting tau to 10n, but the made the output over/undershoot.
Collision Error - Page 1
Forum section: electronics / general

author: Spark-Doctor
author_rank: Contributor
timestamp: February 03, 2024, 01:04:24 pm
content: Hi AllI have a mPCIe connector and retainer on the PCB but i wanted to add the module that is going to be used. I created the module in Fusion 360 and imported it into my design successfully but now i get collision errors on the connector and retainer when i position the module. Can i turn off the collision errors some how??Edit, sorry i put this post in the wrong group, it should be in the Altium page. Can admins move it?

author: thm_w
author_rank: Super Contributor
timestamp: February 05, 2024, 09:53:47 pm
content: https://electronics.stackexchange.com/questions/39638/how-do-i-disable-clearance-check-for-a-layer-or-for-only-some-certain-elements
Holophase/CirCad Importer? - Page 1
Forum section: electronics / general

author: Chris56000
author_rank: Frequent Contributor
timestamp: September 27, 2023, 09:48:56 pm
content: Hi!A DIY Audio Forum Member sent me the Gerber and Native PCB files for Bob Cordell's THD Analyser, but when I attempted to import the Gerbers provided into JLC I ended up with a tiny pcb design in a huge blank area because whoever used Holophase CirCad "V4/Circad 98 I presume!) stuck a huge border round the design, which, altho' can delete in the Circad "demo", I can't even export a screenshot to something like Sprint Layout to retrace it as Holophase make sure all the export filters are removed, and I can't justify £1000 on this arcane software that looks like something from the 19th Century, let alone the 20th!Is there anything else that will import a Holophase Circad *.pcb file?Chris Williams

author: ataradov
author_rank: Super Contributor
timestamp: September 27, 2023, 10:08:44 pm
content: LOL. Their site looks like a parody of the early 90s sites.It would be easier to edit the original gerber files. If all you need to do is delete some elements, even free gerbv can do it. And for replication in a new cad, it may be easier to use the original gerbers rather than this obscure CAD nobody ever heard about.

author: Zoli
author_rank: Frequent Contributor
timestamp: September 28, 2023, 06:12:51 am
content: Quote from: Chris56000 on September 27, 2023, 09:48:56 pmIIRC, I have both Circuit Maker and PCB Maker '98 demos with the proper cracks; if you want to play around with them, I can dig them out over the next weekend.

author: Chris56000
author_rank: Frequent Contributor
timestamp: September 28, 2023, 12:48:00 pm
content: PM Sent to Member Zoli!Chris Williams

author: Zoli
author_rank: Frequent Contributor
timestamp: September 30, 2023, 11:57:23 pm
content: Files sent, awaiting feedback

author: Zoli
author_rank: Frequent Contributor
timestamp: January 20, 2024, 08:15:54 am
content: A couple of .pdf's printed out from the CircuitMaker demo.
Allegro .brd file to .alg or ASCII File convert - Page 1
Forum section: electronics / general

author: Yuvraj086
author_rank: Newbie
timestamp: April 03, 2024, 05:52:52 am
content: I need to import allegro file into altium but it is in .brd format and altium recommended in .alg or ASCII format.If anyone convert it then its very helpful for me .
Automotive Ethernet and GVIF2 Passthrough PCB Design Discussion - Page 1
Forum section: electronics / general

author: Unsanity
author_rank: Contributor
timestamp: December 27, 2023, 05:21:13 am
content: Hello,I am designing a passthrough PCB for Automotive Ethernet and GVIF2 communication lines. The reason why is because the wire-to-wire connectors are not available right now. So, I am making a PCB to connect two harnesses together. The wires of the harness are STP (Shielded Twist Pair), and I would like to continue the continuity of the shield between the harnesses. I assume the cable has an impedance of 100 ohm, but I do not have any specification to back that up.Each wire has its own shield. I decided to keep each shield plane separate to help prevent noise from traveling between shields. I have stitched the top and bottom layers together to create a cage around the signal traces. No idea if this will actually help, just felt good to do.If there are general comments, please feel free to share too. I am far from an expertSorry if I missed to add any important information needed for an informed discussion.QuestionIs it OK to stitch the top and bottom layer shields together?Layer InfoLayer 1: ShieldLayer 2: SignalLayer 3: -Layer 4: ShieldStackup InfoSee attached imagesInner Copper: 0.5ozOuter Copper: 1ozPrepreg Type: 7628Prepreg Dielectric Constant: 4.4Differential Pair Design InfoSee attached imagesZDiff: 100 ohm (Ethernet and LVDS)

author: nctnico
author_rank: Super Contributor
timestamp: December 29, 2023, 02:31:02 am
content: I'd crimp RJ45s on the cable and used a shielded RJ45 to RJ45 coupler.
Any way to simulate MT3608 (spice)? - Page 1
Forum section: electronics / general

author: shapirus
author_rank: Super Contributor
timestamp: December 31, 2023, 10:18:19 am
content: There seems to be no Spice model forMT3608at all.Does anyone know an alternative IC that is similar to MT3608, ideally being pin-compatible, for which a model would be available that could serve as a substitute for simulation?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: December 31, 2023, 01:08:18 pm
content: My first guess is that manufacturers of cheap chinese stuff don't bother with spice models.A second guess is that simulation would not be very useful. Parasitic properties due to PCB layout and of the used passives probably have an important influence on the end result.

author: shapirus
author_rank: Super Contributor
timestamp: January 01, 2024, 10:14:04 am
content: Quote from: Doctorandus_P on December 31, 2023, 01:08:18 pmYeah I kind of figured that out. That's why I'm looking for something that might be compatible and have a model.Quote from: Doctorandus_P on December 31, 2023, 01:08:18 pmThat's clear, I understand the limitations. Main idea is not to simulate it down to fine details to see how a real PCB would behave, but rather to avoid setting the "exclude from simulation" flag on a bunch of components and adding makeshift substitutes like the voltage source spice primitives instead, which won't even be sufficient in case when I to use e.g. a variable output feedback divider.I usually try to create a single nice schematic that works as such, works for simulation, and works for PCB design. Often it is quite feasible (for example, with MC34063A, if we speak about switching converters).
PCB Material Thickness  - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: November 26, 2023, 04:43:29 pm
content: I was searching for low loss high speed PCB material and found the datasheet of the following materials.1- MEGTRON6 Normal glass cloth: R-5775(K)/R-5775(G): Dk = 3.62 @ 13GHz2- MEGTRON6 Low Dk glass cloth: R-5775(N): Dk = 3.34 @ 13GHzhttps://industrial.panasonic.com/ww/products/pt/megtron/megtron6The above dielectric constant values Dk representing the Core material. What are the dielectric constants Dk for Prepregs R-5670(K)/ R-5670(N)/ R-5670(G) ?In which thickness (glass cloth style) these Core and Prepreg are available ? Are they available in 106, 1080, 2116 and 7628 ? The reason of asking this question is, we need to specify the thickness of Core and Dielectric in the Stackup Editor of the PCB Design Tool along with the dielectric constant value Dk.

author: ViaTech
author_rank: Newbie
timestamp: December 22, 2023, 11:50:48 am
content: Dk for Prepregs R-5670(K)/ R-5670(N)/ R-5670(G)They are available for 1035, 1078, 2013 and 2116 types.DK for 1GHZ is as follows:Type 1035--60um: 3.20; 68um: 3.16; 74um: 3.13;Type 1078--77um: 3.26; 89um: 3.22; 104um: 3.17; 118um: 3.13;Type 2013--98um: 3.40; 106um: 3.37;Type:2116--125um: 3.40; 132um: 3.37.But we need to know the different resin content. It is better to have the datasheet from Panasonic.

author: free_electron
author_rank: Super Contributor
timestamp: December 31, 2023, 06:44:00 pm
content: a quick word. dk is given for a specific frequency band. use the one that matches your signals ! using the 6ghz dk with a 500 MHz signal is nonsensebe aware of the weave and resin content. loose weave is very harsh on signal integrity. every time you leave the glass bundle you have a discontinuity.this is especially important if you have differential pairs. one trace may be over glass, the other over resin causing a huge delta in impedance.
Importing a model from one spice simulator to another - Page 1
Forum section: electronics / general

author: gopikagopikrishnan
author_rank: Newbie
timestamp: January 20, 2024, 12:43:22 pm
content: To model an FR-4 lossy channel for chip level desgning of high speed circuits.

author: Kean
author_rank: Unknown
timestamp: January 21, 2024, 10:02:45 am
content: A terrible use of the poll featureAnd how does this belong under open source hardware section?
Insertion loss budget on PCB - PCIe Gen 3 - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: January 03, 2024, 09:15:33 am
content: I found this article which deals with the insertion loss budget for PCIe. I am looking for the table in which the total channel insertion loss budget for PICe Gen 3 (8 GT/s) is 22 dB which is distributed as Root Package (3.5 dB), CEM Connector (1.7 dB), Add-in Card (6.5 dB), Remaining Budget for System Base Board (10.3 dB).https://www.electronicdesign.com/technologies/communications/article/21267698/astera-labs-how-to-manage-the-pcie-50-channel-insertion-loss-budgetRemaining Budget for System Base Board (10.3 dB): Is that the budget for PCB design ? Does it means that the PCB traces should not have more then 10.3 dB insertion loss ?
Pentalogix Viewmate Pro DXF to Gerber conversion , drill file how to ?? - Page 1
Forum section: electronics / general

author: Overspeed
author_rank: Frequent Contributor
timestamp: December 12, 2023, 07:14:19 am
content: HelloI use Viewmate ( not the pro version ) since years for minor Gerber modification , I have downloaded the Pro version to make some DXF to Gerber conversion for evaluation before to purchase .If Gerber files conversion works , I an stuck with the drill file as I create NCtool table , I declare my layer Vias as a PTH ( plated to the hole layer ) and the software provide me a message as no hole is locatedIf i try to convert by using the pad to hole tool as the soft declare '' no hole found '' , the answer is .... doesn't workI have try to contact Pentalogix without an answer from them and Pentalogix help files and training video are really poor.Perhaps someone can explain me how to convert DXF layer to drll ?RegardsOS

author: Overspeed
author_rank: Frequent Contributor
timestamp: December 13, 2023, 07:51:12 am
content: HelloSeveral days after my emails with screen prints to Pentalogix I have received an answer , I start to understand the specific method to convert polygon to pad and pad to holes .I will make tutorial asap that 100% provide a proven conversion .RegardsOS
Orcad Capture - repeating design with spreadsheet.... can it be done? - Page 1
Forum section: electronics / general

author: Stupid Bear
author_rank: Contributor
timestamp: December 10, 2023, 02:21:47 pm
content: I am working on a board that has a repeating circuit involving several relays, diodes and resistors. This is repeated about 60 times. Each has a net that turns on the relays and nets that correspond to the circuit pins for NO and NC on the relays. Is there a way to have the 60 instances of the circuit block driven by a spreadsheet, such that I would only have to specify which nets go to each block instead of having to actually create all 60 blocks on my schematic page(s).

author: nctnico
author_rank: Super Contributor
timestamp: December 10, 2023, 04:49:28 pm
content: You can export / import schematics as XML. So if you export an XML with 1 block and use some scripting to expand that schematic to have the number of instances you need, it might be doable. I don't know if this is effective time wise, but scripting sure does help to prevent mistakes so it is worthwhile to persue to avoid needing to spend time on a board respin / debugging. Python is likely a good choice as there are libraries available to deal with XML files in an easy way. I have used the XML export / import function in Orcad Capture to do mass font size modifications (search & replace) to make a schematic more readable.
Anyone have a library for OrCAD 9.X that has the 68HC68 RTC/RAM - Page 1
Forum section: electronics / general

author: scopeman
author_rank: Frequent Contributor
timestamp: December 18, 2023, 01:32:59 am
content: I am looking for a OrCAD 9.X Motorola library that has the 68HC68 RTC/RAM chip.Thanks,Sam

author: Doctorandus_P
author_rank: Super Contributor
timestamp: December 20, 2023, 04:59:56 pm
content: I don't use orcad, but any decent schematic drawing program has an editor to create your own schematic symbols. Usually it is so simple to make your custom symbols that asking for it or searching is barely worth the effort.An alternative way is to have a look at websites such as snapeda or PCB libraries. They have very big databases with schematic symbols, and they can generate symbols on the fly for a whole lot of different EDA suites.

author: nctnico
author_rank: Super Contributor
timestamp: December 26, 2023, 04:51:09 pm
content: Agreed. This chip has 20 pins at most. Writing the post to ask for the symbol is more work compared to simply creating the symbol.
Exporting Altium .PcbDoc as .pcb that is supported by PADS - Page 1
Forum section: electronics / general

author: rokspy
author_rank: Contributor
timestamp: December 05, 2023, 11:12:43 am
content: Hello.I would like to know if there is some way to export Altium .PcbDoc as .pcb file that is supported by PADS. I don't see any direct export option in Altium for it. I have tried "Save As" .pcb (PCB 4.0 Binary), but that is not supported. (It kind of did work before, but the design was a bit broken. With the latest Altium version, no luck at all). There is the PADS Logic Exporter, but with that only schematics can be exported as .txt

author: thm_w
author_rank: Super Contributor
timestamp: December 05, 2023, 10:20:42 pm
content: If it worked before, use the old version that was working.
pads pcb viewer - Page 1
Forum section: electronics / general

author: Otwin38BOH
author_rank: Newbie
timestamp: November 22, 2023, 09:20:19 pm
content: I have an old project that is getting resurrected. The PCB files are PADs from around 2005. I think they used Mentor Graphics 9.5 PADSDoes anyone have a viewer for this format?Thanks in advance,Kevin

author: casualrex
author_rank: Newbie
timestamp: April 07, 2024, 12:19:12 pm
content: Siemens has made their free PADS pcb viewer available on the web:account registration is required, which is also free.https://community.sw.siemens.com/s/article/PADS-Viewers
Can anyone share the PSPICE models that were available from ti.com? - Page 1
Forum section: electronics / general

author: shapirus
author_rank: Super Contributor
timestamp: November 30, 2023, 01:44:14 pm
content: TI's full set of PSPICE models used to be available athttp://www.ti.com/packaged_lits/pspice_files/ti_pspice_models.zip. Now this link is still valid (as in not returning a 404), but the archive does not contain any files, only directories.Does anyone still have it lying around? Care to share?

author: ledtester
author_rank: Super Contributor
timestamp: November 30, 2023, 02:29:53 pm
content: Couple of ideas:1. Ask on the LTspice@groups.io forum, i.e. see this post:https://groups.io/g/LTspice/topic/pspice_model_collection_from/404110802. Ask on the Ti E2E forum where you can talk with TI engineers:https://e2e.ti.com/

author: shapirus
author_rank: Super Contributor
timestamp: November 30, 2023, 03:39:32 pm
content: Quote from: ledtester on November 30, 2023, 02:29:53 pmYeah that's where I found that link originally. Alas, it expired since then.However, as I was writing this, I realized that archive.org might have preserved an older version. And guess what, it did! I'm now downloading it: 428 MB of something. Will see. This is a snapshot from 2019, and there's another from 2021, will check it after getting the older one....update: 2021 is already the empty one, and 2019 one lacks a lot of parts, including e.g. the older CD4000 logic ICs. They are still available as individual downloads on specific parts pages though, but who knows for how long more they will stay.Quote from: ledtester on November 30, 2023, 02:29:53 pmThat's a good idea to keep in mind. I don't like the idea of registering on yet another forum, but I may have to. It's actually possible that the TI guys don't even realize that this archive went bad and may want to fix it. OTOH, it's also possible that they may want to contact archive.org to remove the snapshots it saved, if they removed the data on purpose.

author: kripton2035
author_rank: Super Contributor
timestamp: November 30, 2023, 05:55:22 pm
content: there is one here (but seems from 2017 ?)https://kolegite.com/EE_library/useful_software/ti_pspice_models.zip

author: shapirus
author_rank: Super Contributor
timestamp: November 30, 2023, 06:03:33 pm
content: Quote from: kripton2035 on November 30, 2023, 05:55:22 pmYeah I can use google tooI found this one, however it's still lacking older parts, and it's much smaller than the 500+ MB one mentioned in the newsgroup post linked above.
QucsStudio 4.3.1  - simulation problem - Page 1
Forum section: electronics / general

author: katto01
author_rank: Newbie
timestamp: November 24, 2023, 02:37:33 pm
content: Hello,I am trying to simulate a simple circuit. I get this warning:"Ratio of adjiacent grids too large (2.09116) at y=0.0220684mm.=> Simulation might be innacurate"Q1: is there a way to modify the mesh in QucsStudio 4.3.1?Q2: Does QucsStudio 4.3.1 have a dedicated user forum? I googled it but not found oneThanks

author: djsb
author_rank: Super Contributor
timestamp: November 24, 2023, 03:30:59 pm
content: Forum is herehttp://qucsstudio.de/forum-en/Can't answer the question about grids.

author: katto01
author_rank: Newbie
timestamp: November 24, 2023, 04:00:45 pm
content: ThanksIt looks like the forum does not accept new members. Is this right or I have a connetivity issue?
Coaxial cable (which is not a PCB transmission line) - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: November 22, 2023, 09:44:48 am
content: I have read "coaxial cable (which is not a PCB transmission line)". Does this means that the coaxial cable is different then PCB transmission lines. But coaxial cable is not a transmission line at all ? Can someone please explain this a bit further. Thanks in advance.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 22, 2023, 01:38:37 pm
content: A little more context would be helpful. What else is said around it? Are you asking purely from a language perspective?If the latter, I would bracket it as:"[coaxial cable] which is not [a PCB transmission line]"[coaxial cable] subset of [transmission line][PCB transmission line] subset of [transmission line]Without context, I have no idea why it's relevant to contrast these, nor why it was said this way, instead of a more compact term that either implies its nature, or specifies it as such: "PCB traces" (implied: consistent width, and height over a GND plane), "microstrip" (defined as same); or a more direct difference ("unshielded traces which can radiate"), etc.Tim

author: joniengr081
author_rank: Regular Contributor
timestamp: November 22, 2023, 05:36:13 pm
content: I guess the term transmission line is referring to the transmission line effect for example cross talk, attenuation of high frequency components, increasing the rise time of the signal. We know that PCB traces if they are longer then 1/10th of the wavelength of the highest frequency content, usually approximated as 5th harmonics are turned into transmission line on outer and inner layers.Referring to "Coaxial cable (which is not a PCB transmission line)" does it means that the transmission line effects will no longer be applicable to the coaxial cable ?

author: tggzzz
author_rank: Super Contributor
timestamp: November 22, 2023, 07:16:51 pm
content: Quote from: joniengr081 on November 22, 2023, 05:36:13 pmThe highest frequency content dependsonlyon therisetime. The period iscompletelyirrelevant.For a little theory and some practical measurements, seehttps://entertaininghacks.wordpress.com/2018/05/08/digital-signal-integrity-and-bandwidth-signals-risetime-is-important-period-is-irrelevant/Alternatively, consult any textbook or application note on transmission lines.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 22, 2023, 11:54:11 pm
content: Quote from: joniengr081 on November 22, 2023, 05:36:13 pmI have no idea. Again, you'll have to providethe context around this phraseto better understand its role in the passage.Tim
LTSpice PWM Input Signal Creation for Motor Soft Start - Page 1
Forum section: electronics / general

author: electrovanga
author_rank: Contributor
timestamp: October 23, 2023, 10:16:07 am
content: Hello,I want to create a PWM signal start from 10% till 70% by increamenting 2% per cycle in LTSpice.My signal frequency is 980Hz. How can I model it in LTSpice?

author: Ian.M
author_rank: Super Contributor
timestamp: October 23, 2023, 10:55:58 am
content: That's fairly trivial - two voltage sources, one set up as a triangle wave of the desired frequency, and the other as a ramp, and a comparator. In the attached sim I am using UniversalOpAmp2 as the comparator as the A device differential Schmidt is prone to glitching and I didn't want to use a specific comparator IC.

author: iMo
author_rank: Super Contributor
timestamp: October 23, 2023, 11:07:34 am
content: In past I clocked in (with a pulse voltage source with your 980Hz freq) a digital counter and based on its output values (ie. "a DAC" in math like VAL=D0*0.01+D1*0.02+D2*0.04.. etc) I made other calculations which were then fed into the schematics where needed (as the "parameter" or directly as the "voltage")..

author: drago462
author_rank: Contributor
timestamp: November 21, 2023, 07:43:00 am
content: Creating a PWM signal in LTSpice can be a bit tricky since LTSpice doesn't naturally loop or increment values in a straightforward way. What you'll want to do is set up a voltage source with a pulse function. Start with your duty cycle at 10% of your signal's period (which is 1/980 seconds). Then, you'll need to manually adjust this in steps, or use the 'STEP' command in LTSpice to simulate different cycles with increasing duty cycles. If you're comfortable with scripting, you could even script the creation of a PWL file with your desired pattern and import that into LTSpice. It's a bit of a workaround, but it should get you that varying PWM signal you're after.
prepreg thickness and pattern in PCB layers  - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: November 23, 2023, 09:50:17 am
content: I have found a table in which prepreg styles vs thickness and the percentage of resin is given. For example in 2116 there is less percentage of resin compared to 106 having higher percentage of resin. What this has to do with percentage of copper ? It says 100 % copper.Do we have these styles / patterns (106, 2116 etc) only for prepreg or they are also for defining core materials ?
Stitching vias  - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: November 23, 2023, 01:31:24 pm
content: I have found some text regarding stitching via. I am wondering how about if the two reference planes are power planes with different voltages on them. Can we also use stitching via between them if a signal is routed over the split ? How about if we have 1.8 V and 3.3 V as reference power planes ?Can this be two ground planes ? for example analog ground plane and digital ground plane ?In case they are power and ground plane then it's fine to use de-coupling capacitors. But how about if both of them are power planes or both of them are ground planes ?

author: nctnico
author_rank: Super Contributor
timestamp: November 23, 2023, 03:20:22 pm
content: In case of ground planes, you can stitch the ground planes together. The construction in your image is used when a high speed signal travels across planes with different voltages on them. If you go between 1.8V and 3.3V, then you'll need a capacitor between 1.8V and 3.3V.

author: joniengr081
author_rank: Regular Contributor
timestamp: November 23, 2023, 03:27:38 pm
content: What if the ground planes are separated on purpose. For example analog ground and digital ground ?What if the two reference planes are power planes ? I guess we can't connect capacitor between them

author: tszaboo
author_rank: Super Contributor
timestamp: November 23, 2023, 05:12:55 pm
content: Separating grounds is no longer the recommended method, since the 90s. Unfortunately it still pops up sometimes as a recommendation but it is not good for EMI or accuracy. The only reason to separate it if you are dealing with very high currents.

author: joniengr081
author_rank: Regular Contributor
timestamp: November 23, 2023, 05:48:13 pm
content: Current is low but I think this is to isolate digital switching in high speed design from analog reference ground.
What CAD package creates SCH/HDF files? - Page 1
Forum section: electronics / general

author: gmc
author_rank: Regular Contributor
timestamp: November 02, 2023, 07:13:41 pm
content: I've found a schematic I'm trying to open that someone posted a good few years ago. There is no mention of the CAD package used so struggling to find something to open it.Tried Eagle and KiCad - no luck.Schematic file is here:I've looked through the content but can't find anything to identify the software used.http://www.zimmers.net/anonftp/pub/cbm/schematics/computers/pet/re/3008.schhttp://www.zimmers.net/anonftp/pub/cbm/schematics/computers/pet/re/3008.hdfCode:*P CAP4 60 00206537-2900, -2050, 13635, 9643, 50;*R PET3008*S2114600 8001,5,150,50,450,50,450,750,150,750,150,50;0,2,Any tips would be appreciated.Maybe a gif of the schematic might give some clues?http://www.zimmers.net/anonftp/pub/cbm/schematics/computers/pet/re/3008.gif

author: nctnico
author_rank: Super Contributor
timestamp: November 02, 2023, 07:30:32 pm
content: The GIF looks like it is from a very old package. Like 80's or 90's.

author: TimFox
author_rank: Super Contributor
timestamp: November 02, 2023, 08:17:34 pm
content: PCAD, maybe?

author: gmc
author_rank: Regular Contributor
timestamp: November 02, 2023, 09:07:17 pm
content: No luck - tried PCAD as well.At this rate I must just recreated the schematic from scratch.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: November 03, 2023, 01:36:41 am
content: That site claims the schematic was reverse engineered by Ruud Baltissen. You can try contacting him for more info. The link below pops up quickly after a general search and the site is about C64 stuff, so it may be the right person.http://www.baltissen.org/newhtm/index4.htm
How to find the .lib file for PSPISE? - Page 1
Forum section: electronics / general

author: wenyi
author_rank: Newbie
timestamp: October 24, 2023, 08:31:32 pm
content: What should I do when I can't find a .lib file for simulating a circuit on the official website (e.g. Texas Instruments)?like CD74HCT193E CTR.I use PSPISE for simulation, .lib file used to simulate. but i cannot find them in the offical webstite.Sorry I am new for circuit design. :'(

author: Simon
author_rank: Unknown
timestamp: October 25, 2023, 06:36:07 am
content: please don't double post, it really annoys people.https://www.eevblog.com/forum/beginners/how-to-find-the-lib-file-for-pspise-398331/msg5132445/#msg5132445
Hosing eDrawings - Page 1
Forum section: electronics / general

author: metrologist
author_rank: Super Contributor
timestamp: October 24, 2023, 04:08:47 pm
content: We would like to embed an eDrawing on our website pages but have not found out how.One example uses an iFrame but references drawings uploaded to 3dcontentcentral:https://www.3dcontentcentral.com/external-site-embed.aspx?format=3D&catalogid=171&modelid=421201&width=250&height=250&edraw=trueThe video below explains a way to convert the drawing to web code that would seem to load in a browser when emailed, but my version, latest version of eDrawing does not have the specific export format (Web HTML vs ActiveX HTML).
LTspice wont allow editing spice directive - Page 1
Forum section: electronics / general

author: Faringdon
author_rank: Super Contributor
timestamp: November 03, 2023, 07:14:14 am
content: Hi,Anyone know the fix for this?...i saw it from others after googling it..Often, when i want to change a spice directive, it wont let me....i have to convert it to a text statement, change it, then convert it back to a spice directive....thats a "fix" but takes time.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 04, 2023, 01:08:53 am
content: Not sure what exactly your issue is.A Spice directive is nothing else than a text statement. What are you after?I routinely add Spice directives in LTSpice schematics, for instance to add coupling coefficients between coils, or define initial conditions.Just go to Edit/Spice directive, or just type 'S', the dialog pops up, enter the directive, place it on the schematic, done.To edit one already placed on schematic, just right-click on it and the dialog pops-up with the directive you can edit.Is there anything more to it?

author: Faringdon
author_rank: Super Contributor
timestamp: November 04, 2023, 11:40:53 am
content: QuoteThanks, thats what i have been doing for the last 15 years...unfortunately, it now intermittently doesnt work

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 04, 2023, 11:36:25 pm
content: Quote from: Faringdon on November 04, 2023, 11:40:53 amI can't tell why it wouldn't. Been using LTSPice 17.x on Windows and now on Linux, updated to even the latest version, and it appears to just work.Are you using a recent version of LTSpice? Which OS?Note that, while I haven't run into this issue at all, LTSpice does have a number of UI bugs (most of them are in the Waveform viewer IME), so I wouldn't be surprised if it had this one on particular configurations.

author: Smokey
author_rank: Super Contributor
timestamp: November 05, 2023, 01:26:26 am
content: I had the same bug. It actually magically went away recently. No idea.
modeling s-parameters of firefly cable - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: October 17, 2023, 04:20:49 pm
content: I am modeling transmission lines in a pcb layout analysis in which I need to two pcb layouts that are connected through firefly cable by samtec. How can I get the s-parameter model file for the firefly cable ?
Q: Algorithms used for component placement to minimize crossing/trace length - Page 1
Forum section: electronics / general

author: m.elsayed
author_rank: Contributor
timestamp: October 16, 2023, 08:07:04 pm
content: Hello,A quick background, I am trying to design an LED matrix using Charlieplexing and looking for an approach where I can scale the design to any number of inputs.My first thought was to try to brute-force the layout, but the complexity is (N+2)! which is not practical.My guess is that graph theory can give a solution for this, by modeling the circuit as a directed graph with inputs as nodes and tracks as nodes, but I have no idea how to approach this.I know that there are already algorithms for routing but I was not able to find anything on component placement.So my question is, what are the algorithms that can be used for component placement so it would minimize tracks crossings(vias)?And is there any pointers or books that I can read that addresses this?Thanks.

author: Infraviolet
author_rank: Super Contributor
timestamp: October 18, 2023, 10:41:54 pm
content: My suspicion is that if such an algorithm existed, in any reasnably efficient form, we'd already have auto-routers which could select part positions for you as well as routing traces between them.Fortunately for you it looks like you've got a lot of space to play with for wiggling traces round one another and having vias, it might not be the optimum choice, but on a board like this it won't be difficult to fit.If keeping the back side of the board as clear as possible (for fairly solid ground plane, or for placing components and traces not involved in the charliplexing layout) matters for you, I'd suggest the following two tips:1. only go to the bottom layer for traces running vertically, traces which run horizontally should stay on the top layer. You could do this the other way round, but the trick is to reserve the back layer only for traces going in one of the directions, and only put traces of thatdirection on the back when routing on top isn't possible.2. when you need to swap the "order" (which is furthest left, next left, middle, right...) of a series of traces, have them undergo a 90 degree cornering in the area where you put your vias, you can often get a whole swarm of traces to swap order, in many diferent mappings using just one via per trace (some traces not needing a via at all) or two vias if all traces afterwards are to be back on the top layer.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: October 18, 2023, 11:22:05 pm
content: I simply avoid charlieplexing. It's just too much trouble (both PCB layout and software) for not enough gain (saving a few I/O pins). A rectangular matrix is easy to route on a dual layer PCB, and easy to control in software. For adding I/O pins if needed, the 74hc595 or 74ls138 or a slightly bigger uC are among the possibilities.