discrete LDO design- NMOS as a pass element - Page 1
Forum section: electronics / projects

author: chimera_786
author_rank: Regular Contributor
timestamp: June 09, 2013, 05:27:01 am
content: Hey guys!A couple of questions:1- When designing a discrete LDO,the region of operation I would like the mosfet to be is the saturation region. Is that a correct understanding?Reason: When its saturated, its behaving as a voltage dependent current source (Vgs). This implies that for a given Vout, there will be a minimum Vgs required to maintain that output voltage at a particular level and at a particular load current. I can continue to increase the input voltage but my output voltage will remain the same as the gate drive required to yield a particular voltage and current is present, but I will end up burning more power as heat in the pass element (NMOS)On the contrary, if I start decreasing my input voltage and if I keep a constant load on the mosfet, the Vgs will have to increase to maintain the desired output voltage. But there will reach a point where I will have maxed my gate drive voltage and further decrease in the input voltage will cause my LDO to fall out of regulation and eventually, turn off.When it drops out of regulation (i.e. the output voltage is no longer what is required), the mosfet has entered the linear region and is behaving like a resistor and the gate voltage will have no effect on the output voltage.I assume this is the basic theory behind the LDO. Please point out any basic points which I might have over looked.I am not talking the various pass elements and their associated supporting circuitry and please ignore the control loop aspect for this discussion.THanks!

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: June 09, 2013, 11:51:00 am
content: Hi,The challenge with using a N Channel MOSFET in a LDO regulator, is that the MOSFET gate voltage has to be the output voltage plus the gate - source voltage of the MOSFET.This is easy if you have a higher voltage bias supply.If you do not have a bias supply, here is a chip that use a small boost regulator to create one.http://www.linear.com/product/LT3150If you read the datasheet you may get some tips on how to make your own.Remember, that an LDO in dropout is pretty useless. It can not regulate and can not reject ripple.Jay_Diddy_B

author: chimera_786
author_rank: Regular Contributor
timestamp: June 09, 2013, 02:59:05 pm
content: Jay-You correct when you state that the gate drive votlage has to be higher. This value is Vgate= Vgs + Vs--> Vgate= Vgs + Vo.You are also correct when you state that an LDO operating in the drop out region is no good as it will just act as a resistor in series between the input and the output.For this discussion, I am assuming that I have all the right things present to have a working LDO design and would like to focus on just the theory of operation.It seems like I have not overlooked anything in the basic power stage analysis of an NMOS LDO. I have searched the web for good resources on LDO design but predominantly, I have found BJT and a few PMOS based articles.These articles are a good read and do provide insight on Voltage Regulators, but I would like to find and read a few articles based just on NMOS LDO design and things to keep in mind.Can you provide a good link to NMOS based LDOs which cover the operational theory?