MOS output loaded when CMOS gate added - help needed in understanding - Page 1
Forum section: electronics / projects

author: leonababy
author_rank: Regular Contributor
timestamp: November 01, 2020, 04:30:10 am
content: I have a circuit from the 1970's, which has an obscure MOS clock chip. A modification requires that two existing used output pins be connected to digital logic, to alter an existing control signal. Since the clock runs at 12V, my thought was to use CMOS since I need outputs of the added logic circuitry to interface to existing peripheral circuitry, which also runs at 12V. When I added one CMOS input to each of two outputs (having different functions and it is unknown if they have different drive circuitry), one of the outputs continued to work fine, but one did not.The pins of the clock chip in question currently drive a high-voltage capable inverter array, which drives a gas discharge display. Note there may be more details provided than necessary, but one purpose is showing some constraints to a possible solution. The plan is for the added logic circuit output to replace an existing control signal which in turn will alter the function of the clock (believe it or not, the clock IC manufacturer screwed up and AM and PM switch at 1:00 instead of 12:00!).There is a 4-page datasheet for the clock, and in one diagram equivalent circuits of various output pins are depicted next to each output. Unfortunately, there may be an error in the equivalent output diagram for the pin that continues to function (A in the attached diagram). Also unfortunate is there is no detailed data on the capability of the outputs. The equivalent circuit for each gate in the driver array is also shown. The signal that is corrupted is B. See the waveform depictions - with the new circuitry added, A is unaltered, but on the falling edge of B (which was sharp like A prior to adding the CMOS gates) the voltage drops like a capacitor discharging after an initial drop of a few volts. The actual logic circuit is not shown - I simply show A and B going into CMOS inputs, which they are.I realize there is not a lot to go on here. I do not have a firm grip on the current capability of the clock chip outputs, nor the load of the driver elements in this particular application (the datasheet has a wide variation in input currents). The frequency of the signals in in the 64 kHZ range maximum. I guess off the top would be whether someone has an initial suggestion based on the symptom. One of the issues of the slow drop in voltage on B is there is ghosting in the display as a result of a cathode that should be off. Not shown is signal B actually goes through some existing additional sections of the driver array (which is an inverter) so it isn't that A is one segment and B another. B actually ultimately feeds the AM and PM cathodes. For the curious, the clock chip is an AMI S1856, and the driver chip is a UHP-480 - these are from 1974.edit - datasheet excerpts addedThank you in advance for any suggestion you may offer.Don

author: Wimberleytech
author_rank: Super Contributor
timestamp: November 01, 2020, 02:04:02 pm
content: I am clueless as to why A falls so quickly with roughly 30K passive pull down and B does not with an active (p-ch) pull down. I would add 10k or so pull down on B and see what happens.BTW, the P-ch appears to be a depletion-mode device and thus acting like a current source pull down of 350uA. That should be enough, frankly...

author: floobydust
author_rank: Super Contributor
timestamp: November 01, 2020, 06:21:18 pm
content: I went through the same issues with my friend the MM5314 clock chip inthis thread.In thatLEDclock, it had inter-digit ghosting.In the mid-1970's PMOS was King, actually "P-channel low-threshold, enhancement-mode and ion-implanted depletion-mode devices". It's a bit of work to understand the old tech. The power supplies are also awkward, the most +ve rail is VSS usually 0V, and most -ve rail is VDD typically -6 to -16V. So negative rails used to make it even more fun.There are two output configurations - open drain, or open drain with weak (switched) pulldown or pullup. You must add pullup or pulldown resistors but not so low in value as to load down the wimpy outputs. Without them, the really slow switching time can be seen on the scope, which causes ghosting. I think it gets worse with older IC's for some reason.The digit drivers are open-drain, the segment drivers have a pulldown? Very low current and just sluggish switching, and they don't switch that close to either rail. The ULN2802 or ULN2002/2004 (50V) is used with PMOS with zener used to help ignore the large offset.I have a 1977 AMI databook with the S1856 and detailed output curves. I can scan later, but so many typos in that book. S1856 is direct-drive for LCD displays or Tung-Sol DT1704's vacuum fluorescent tubes.

author: Wimberleytech
author_rank: Super Contributor
timestamp: November 01, 2020, 10:06:02 pm
content: AMI calls the process for this chip: P-I² which is P-channel using ion implantation. Early pmos used higher voltages due to large threshold voltages. Ion implantation was the magic to get thresholds down and ultimately make CMOS a viable technology.

author: leonababy
author_rank: Regular Contributor
timestamp: November 01, 2020, 11:33:08 pm
content: QuoteI tried two things, but did not mention them. I tried a diode (realizing that it likely would cause a problem, not solve it), with the anode at B in series with the CMOS gate. This caused the falling edge of the signal at B to drop normally, but the signal at the input to the gate was not at all like that at B.I did try a pull down resistor - 20k (I didn't have a 10k handy), and it actually worsened the signal quality of the "tail". It lengthened it. I will try 10k but based on the 20k result I don't have a lot of hope. I see there are two other replies but this is my answer to your comment. Thank you.

author: leonababy
author_rank: Regular Contributor
timestamp: November 01, 2020, 11:42:46 pm
content: Quote from: floobydust on November 01, 2020, 06:21:18 pmI did notice the negative rail in the datasheet and found it odd. This application (Heathkit GC-1093) has Vdd = 0 and Vss = +12V. My memory from working with TTL in the 80's was Vss was usually ground.There are two output configurations - open drain, or open drain with weak (switched) pulldown or pullup. You must add pullup or pulldown resistors but not so low in value as to load down the wimpy outputs. Without them, the really slow switching time can be seen on the scope, which causes ghosting. I think it gets worse with older IC's for some reason.QuoteI was wondering if I could use another device to buffer these signals from the clock chip. Maybe one of these would work? Could you describe more fully what this would entail (you mention a zener). Would this be like a resistor divider, and then a zener following, across the input to the ULN device?QuoteI was confused by the two graphs in the datasheet I found. One showed a range of 0.5ma to 1A, and the other a much lower range of current (like an order of magnitude), and the only difference was Vdd was maybe 12V on one and 24V on the other.Thank you for the reply

author: Wimberleytech
author_rank: Super Contributor
timestamp: November 02, 2020, 12:59:44 am
content: QuoteThe history of supply notation is very sloppy. VSS refers to the supply attached to the source. VDD refers to the supply attached to the drain. This worked fine for single-channel technologies (p-ch or n-ch) but lost its way for CMOS. VDD now comes to mean the most positive supply and VSS the most negative. Quite often GND replaces VSS terminology.MOS memories flourished in the n-ch technology period where the transistor source was indeed ground.

author: floobydust
author_rank: Super Contributor
timestamp: November 02, 2020, 08:54:01 pm
content: This might be a bit awkward to fix - you actually want the digit switched off fast, and the turn-on delayed.A neon display as a single tube with multiple digits (i.e. Burroughs Panaplex) you need extra blanking time. I can't remember how long it takes. The MM5314 datasheet shows they pulsed the display output-enable to accomplish this.The clock IC's output is loaded down by the Sprague UHP-480, so the mushy signal is expected. A 4000 CMOS part ideally a Schmitt trigger like CD4093 but even then the thresholds would make it late turning off on the one edge.Where Heathkit put the delay... I think they pulse the nixie digit firing it on and use its properties to latch on? So I'm not sure how the digit gets turned off here.Check the tube voltages are ok, keep-alive cathode "W" -275VDC, and the mid-point bias at 160VDC and 120VDC. The capacitors might need to be replaced.Sprague/Heathkit UHP-480 is also Fluke 504795 for ref.

author: leonababy
author_rank: Regular Contributor
timestamp: November 03, 2020, 02:54:55 am
content: Quote from: floobydust on November 02, 2020, 08:54:01 pmeditI just looked at your thread on the MM5314, and immediately realized that I failed to indicate a time scale on my sketches of the traces - and it matters because the fall time could be anything. I can't say off the top of my head what it was. I will post some screen shots of the scope after doing some more experimenting. I have a UDN2981 here, which may or may not be of use. It seems the output limitations of the S1856 are going to come into play. I have to read the rest of your thread to see if something you did may apply. I honestly was hoping someone would have an easy answer - but I am coming to see that may not be the case and experimenting will be in order.Thank you for the reply. The voltages are OK, but Heathkit changed the design of the GC-1093 I believe twice, and one change is in the keep-alive circuit. I have a later manual on order, and I have two versions of the schematic - the original (mine) and some time later (undated). I have replaced the caps that needed it.I appreciate the cross reference information. The signal is crisp with sharp edges at A and B with just the UHP-480 connected as designed - both look like the top trace. It is when I add a CMOS gate load that the bottom trace occurs (on certain outputs but not others) and becomes what I would call "mushy". Could this simply be overloading of the output? My thought not knowing from experience was that a CMOS gate would not be much of a load. As I mentioned in another reply, I tried a pulldown and that made it worse. I separately tried a diode just to see what would happen in series with the additional load, and the signal out of the S1856 then was back to being a fast fall time but the input of the CMOS gate was corrupted. I was trying not to modify the original design by buffering the outputs, and just paralleling to them. Once the signals are through the UHP-480 it is too late, since the intensity adjustment occurs at the common substrate of the UHP device and the high voltage is on that side. I suppose I can try opening the input to the UHP and connecting a CMOS load and see how that the S1856 output compares. The UHP is socket mounted so it would be easy.

author: floobydust
author_rank: Super Contributor
timestamp: November 03, 2020, 07:04:47 am
content: 4011 is around 5-8pF input capacitance, not much of a load at all. The scope alone is more of a load. So that isn't making sense. The clock chip does have some very weak outputs (20uA for A1-F1, and A2-F2 ) but they are not used here. You might just have an old chip with weak outputs. The ion implantation seems to fade with age.The S1856 main segment driver outputs are 350uA/500ohm RDS on. The datasheet car LED clock circuit uses direct drive to NPN emitter followers to buffer the segment outputs. It might work better to first buffer the clock IC's outputs with CMOS 4050 or emitter followers, as the UHP-480 is a big load.In your schematic you have one 4011 input grounded, a "0" and anything is a zero. Unused input should go to +12V. It also needs an 0.1uF cap across power.