Hantek HDG2000 Series Firmware Enhancements - Page 1
Forum section: electronics / testgear

author: Scratch.HTF
author_rank: Regular Contributor
timestamp: October 11, 2017, 07:13:45 am
content: The interconnection between the soft FPGA (Xilinx XC6SLX16CSG324) and SOC (Samsung S3C2416 – 400 MHz) is a HS-SPI bus operating at 16.666667 MHz with three additional signals for FPGA code loading but should be able to operate on a faster HS-SPI data rate (up to 50 MHz as per the SOC specification), and the following enhancements can be added (usually without the need to reprogram the soft FPGA) but I am happy to provide a list of enhancements with FPGA reprogramming including waveform segmentation (different FPGA definition files can be reloaded without power cycling):* Binary format for waveform file while retaining text-based header format with a “binary” type flag included.* Address issue of slow loading of user waveforms (loading time increases exponentially every time the waveform size being loaded is doubled e.g. 1 minute for 250K points, 3 minutes 45 seconds for 500K points, 14 minutes 25 seconds for 1M points etc. - with the stock firmware, for each CPU-FPGA SPI bus cycle, a two-byte command is sent along with a maximum 128 byte payload.* Manager for frequently used sets of instrument settings (waveform types, frequencies, amplitudes, offsets and phase degrees, sweep etc. with a short description field)* FTP server (via USB Device or optional LAN)* Remote FPGA code loading (code can be reloaded without power cycling)* Remote firmware updating* Front panel key reading and LED indicator control via USB* Direct SPI bus control from the USB Device port while retaining original remote control commands

author: Scratch.HTF
author_rank: Regular Contributor
timestamp: October 29, 2017, 10:30:25 am
content: One more enhancement: Increase the video clock frequency to 33.333333 MHz (1/12 core frequency which corresponds to the typical DCLK value for the AT070TN92 display) along with changing the Horizontal parameters to correspond with VESA 800x600 @ 56Hz and the Vertical parameters to correspond with IBM 640x480 60 Hz resulting in a H/V frequency of 32.55kHz/62Hz and would be more compatible with LCD controllers and/or VGA-HDMI converters – due to the original DCLK frequency of 26.666667 MHz (1/15 core frequency) with H/V frequencies of 30.24kHz/56.94Hz with a low Horizontal blanking overhead (82 pixels) and short Horizontal Sync (8 pixels) may therefore have issues (especially size and positioning) when used with a simple VGA DAC (resistor based) and certain LCD panel controllers or VGA-HDMI converters (may be detected as either 800x480 57 Hz or 640x480 57 Hz).

author: Daruosha
author_rank: Regular Contributor
timestamp: October 29, 2017, 10:56:26 am
content: Thanks for the update, however have you manage to implement these enhancements and load the new firmware on the actual device? Is there any way we can test and use the enhanced firmware?

author: tridentsx
author_rank: Regular Contributor
timestamp: October 30, 2017, 06:31:15 am
content: Are you planning on setting up a public github repository? I think some reuse can be made from the code and build environment from this projecthttp://blog.weinigel.se/2016/07/16/sds7102-source.html