Difference Amplifier with MOSFETs - Page 1
Forum section: electronics / beginners

author: anvoice
author_rank: Frequent Contributor
timestamp: December 22, 2019, 02:53:28 am
content: Hello, I'm reading a textbook called Foundations of Analog and Digital Circuits, and have run into something I can't seem to understand. I am attaching a file with the schematic (right of page) and the beginning of the analysis of the circuit. It is a MOSFET-based difference amplifier and its small-signal model. What I don't understand is why the book is claiming that "assuming a negligible current drawn through the resistor Ri, by symmetry, I is equally divided between the two MOSFETS". Further, the text then states that the transconductance gm1 = gm2 = gm. To me it seems that these two conditions are satisfied only if VA = VB, (and the K values for the MOSFETS are the same), i.e. the the gate-to source voltages are equal and MOSFETs are identical. I can easily accept that the MOSFETs are identical and the gate-to source operating point voltages are identical, except it doesn't state that this is the case anywhere in the description of the circuit. Furthermore, the text also talks about the common-mode component VC = (VA+VB)/2 and difference-mode component VD = VA - VB, not stating anywhere that VD = 0 (a necessary condition for the operating point voltages and currents of the two identical MOSFETs to be identical).Now, it seems logical that the amplifier contain identical MOSFETs, and be operated with the same operating point bias VA = VB. Since the difference amplifier should have its useful signal encoded as the difference in the two inputd, it seems reasonable for the DC bias to be the same for the A and B inputs. In that case, the small signal model should work out to give some gain for a difference between Vx and Vy (the small signals to the A and B inputs) and 0 for Vx + Vx, resulting in a common-mode rejection ration of infinity. Is this what the text is implying? Any insight would be really appreciated! Thanks in advance.

author: Wimberleytech
author_rank: Super Contributor
timestamp: December 22, 2019, 03:45:40 am
content: By the end of your question, I think you caught on...this analysis is based on a small-signal approximation. Moreover, for ideal matched components and the tail current being purely a current (no resistor), the CMRR is infinity.Perhaps you are struggling with the small signal assumption...is it realistic? When a differential stage of this type is used in a practical situation, it is followed by an additional gain stage and then some form of feedback is applied. The feedback and the gain of the overall amplifier will try its best to force the two inputs of the differential stage to be equal. Thus, the small-signal approximation is perfectly valid, VA~VB.I hope this helps.

author: anvoice
author_rank: Frequent Contributor
timestamp: December 22, 2019, 04:45:16 am
content: Thank you for your reply!I am mostly confused not by the small signal model, but by the fact that the text, which is usually explicit about assumptions it makes, suddenly makes a claim like "currents are equally divided" without stating that the large signal bias VA is about equal to VB. In that case I can easily see how the small signal analysis can proceed.If my own assumption (that the book makes an implicit assumption that VA~VB and the MOSFETs are identical) is right then I can happily continue reading.

author: Wimberleytech
author_rank: Super Contributor
timestamp: December 22, 2019, 01:57:31 pm
content: Quote from: anvoice on December 22, 2019, 04:45:16 amYes, valid point. I have never seen this particular book, but I know that on any given topic, different authors will present in different ways. Thus, it us good, sometimes, to seek out another similar texts and see how the topic is treated.In this case, it sounds like you got it!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 22, 2019, 08:44:09 pm
content: They may not have worded it well, but the usual approach to this analysis is to look at the case for v_A = v_B (that is, the AC signal component of each, not counting DC bias), and for v_A = -v_B.In the former case, we get a wholly common mode input, and R_I is relevant: both outputs have a signal R_L / (R_I + 1/gm), in phase (same sign, and opposite the input sign). Note that, because there's no left/right difference, we can simplify the circuit by merging the sources and transistors, and now it looks like an ordinary common-source amplifier, albeit with an unusually large source resistance, so the gain is low (but finite).In the latter case, we get a wholly differential input, and the source voltage hardly changes at all, so R_I can be canceled out. Gain is then simply gm * R_L.Finally, because this is a linear circuit (in the small-signal case), we don't need to analyze these cases separately -- we can apply inputs v_A = v_CM + v_D and v_B = v_CM - v_D, and the outputs will similarly be the sum of CM and D cases. That is, the amplifier satisfies the condition,For Vout as a function of Vin,Vout(a(b + c)) = Vout(a) Vout(b) + Vout(a) Vout(c)In other words, all the usual friendly associativity-distributivity-etc. properties we like numbers to have.These are not true in general, for large signals -- nonlinearities violate these in various ways. The small-signal analysis assumes linearity, so it's a very handy tool when it can be used.Tim

author: anvoice
author_rank: Frequent Contributor
timestamp: December 23, 2019, 06:50:01 am
content: Quote from: Wimberleytech on December 22, 2019, 01:57:31 pmGood to know, thanks!Quote from: T3sl4co1l on December 22, 2019, 08:44:09 pmI believed for a differential input, the source voltage is actually 0, and that is what allows R_I to be canceled out (since it's a resistor connecting 0 to 0 potential)?I think I understand the rest. Basically as long as the total values of A and B inputs are about equal, we can assume MOSFETs to have identical characteristics. They, of course, can't be completely equal, as that would mean no useful signal can be encoded between A and B, but as long as certain conditions are met they can be close and the linear model is a good fit for reality.

author: Wimberleytech
author_rank: Super Contributor
timestamp: December 23, 2019, 03:27:16 pm
content: Quote from: anvoice on December 23, 2019, 06:50:01 amYes, for small-signal differential-mode (not common-mode) analysis.QuoteYes. The design process isroughlyas follows once you have the architecture established:1) Design dc conditions first taking into account desired signal swing (input and output), power dissipation, slew rate, and noise while taking into account open-loop gain requirements.2) Design in the compensation network based on load conditions and desired bandwidth.3) Simulate the design first in the small-signal domain checking for phase margin and bandwidth4) Validate design in the large-signal domain in the actual circuit configuration where the amplifier is used5) Lay out the design for silicon implementation6) Back-annotate parasitics from the layout and repeat 3-4 and possible tweak the layout if a parasitic is causing a problem.A good design procedure for the 7-transistor opamp can be found in CMOS Analog Design by Allen/Holberg chapter 6 (2nd/3rd) editions.