Why many SRAM has 9/18/36bit alighment? - Page 1
Forum section: electronics / projects

author: nathankwan
author_rank: Contributor
timestamp: October 24, 2023, 08:11:05 am
content: Recently I am trying to build a digital oscilloscope from scraped parts (EP4CE75, CY7C1371D, AD8138, AD9215), while looking at the datasheet of CY7C1371D, I noticed it's a 512K x 36bit SRAM, and became curious since most memory parts has the capacity in power of 2.I also looked at SRAM of ISSI, suprisingly they also have say 72Mbits density, byte width are also 9/18/36 etc. I wonder why it's like this, it's because of the hardware limitations? or it's because such alignment has other merits?

author: Andree Henkel
author_rank: Regular Contributor
timestamp: October 24, 2023, 08:32:54 am
content: read this:https://en.wikipedia.org/wiki/ECC_memory

author: nathankwan
author_rank: Contributor
timestamp: October 24, 2023, 09:19:37 am
content: I don't think the extra bit for one byte is for ecc. The fundamental principle for error detection asks for redundency, therefore the extra bit cannot be treated as a bit of storage space, since its value depends completely on the other eight bits. However these manufacturers obviously counts all 9 bits as storage space.The link of the datasheet of CY7C1371D is down below:https://www.alldatasheet.com/datasheet-pdf/pdf/112309/CYPRESS/CY7C1371D-133AXC.html

author: iMo
author_rank: Super Contributor
timestamp: October 24, 2023, 09:29:47 am
content: It is for the parity (or other) check, when the bit(s) is read as wrong parity it indicates there is an issue with the byte/word, afaik. And the CPU (or the MEM controller) has to do something with it (ie it tries to repair the byte/word if possible).

author: magic
author_rank: Super Contributor
timestamp: October 24, 2023, 09:54:22 am
content: Quote from: nathankwan on October 24, 2023, 09:19:37 amYou can use the bits for anything because they are there, but I suspect that ECC (implemented outside the RAM chip) would be the most likely application, anticipated by the manufacturer of this device.ECC memory modules for PCs have 72 bits per word instead of usual 64.

author: David Hess
author_rank: Super Contributor
timestamp: October 24, 2023, 03:31:59 pm
content: Quote from: Andree Henkel on October 24, 2023, 08:32:54 amAnd more commonly for parity support.Fast SRAM has a surprisingly high error rate compared to DRAM so error detection and correction is more likely. Slow low power SRAM never seems to include the extra bits.I think this comes about because high speed writes require a minimum of charge to be overcome in the SRAM flip-flop, and the low stored charge makes soft errors from things like radiation more common. This is also why microprocessor caches include error detection and correction, with some recent exceptions.

author: nathankwan
author_rank: Contributor
timestamp: October 25, 2023, 12:19:11 am
content: Quote from: David Hess on October 24, 2023, 03:31:59 pmI've heard DRAM bits can get scrambled since a single high energy particle can cause a bit in the capacitor to flip, but I never knew SRAM is even more likely to have errors. This is a 100MHz SRAM, is 100Mhz for SRAMs already fast enough for this phenomenon to occur?and also if there is no ecc circuit outside the memory, by convension is the extra bit ignored? or utilized as normal storage by increasing the data width?

author: nathankwan
author_rank: Contributor
timestamp: October 25, 2023, 12:29:31 am
content: Quote from: magic on October 24, 2023, 09:54:22 amby that the 1 extra bits per byte make sense. However I looked at the DDR4 sheet produced by micron, for DDR there is no such extra bits even for really high speed chips. I then have two more questions needs your help:1. Is it because of the structure of DRAM determines that the memory is not likely to have bit errors, so parity check is not needed even for high-speed high-density chips?2. If 1 is true, how does those ECC-DDRs for servers work? By using dedicated extra chip or other method? -And if 1 is not true, why don't use the similar design for DRAM as for SRAM?Thanks again!

author: magic
author_rank: Super Contributor
timestamp: October 25, 2023, 05:36:36 am
content: I doubt that DRAM has any inherent advantage in error rate. In fact, DRAM chips can only read/write their DRAM array by transferring whole rows to/from an extra SRAM row, where operations on individual words are performed.PC memory sticks use 4 or 8 bit wide chips (SODIMM sometimes 16) and ECC simply has an extra chip or two.

author: David Hess
author_rank: Super Contributor
timestamp: October 25, 2023, 07:14:15 am
content: Quote from: nathankwan on October 25, 2023, 12:19:11 amHigh performance SRAM can be more susceptible for the reason I gave, but low performance SRAM is practically immune.QuoteThe extra bits are ignored except in weird designs which actually do take advantage of 9 bit memory for data storage. The extra bits can be used for longer words or things like memory allocation.Quote from: nathankwan on October 25, 2023, 12:29:31 amYes, although many argue that ECC is not used as often as it should be for DRAM.QuoteFor DRAM, an extra chip is used to provide the bits for parity or ECC. DRAM has a huge economy of scale for non-ECC parts, so it is more economical to use a separate chip for the extra bits. Up to DDR4, usually each word was 64 bits and was commonly organized as 8 chips of 8 bits each, so adding the ECC bits just required another 8 bit DRAM chip for a total of 9 chips to make 72 bits. Note that there are other organizations more suitable to ECC like using 18 or 20 x4 chips. ECC for DDR5 uses 80 bit words to better support a narrower channel allowing two channels per DIMM.Quote from: magic on October 25, 2023, 05:36:36 amIt is not exactly an extra SRAM row, but a row of sense amplifiers, which are similar to a pair of unbuffered inverters making up a SRAM cell, but have extra functionality to precharge and then amplify the tiny charge from the DRAM cell. The relatively huge capacitance of the DRAM sense lines should make them immune to soft errors.I have a pretty good idea as to what is going on to make high performance SRAM more susceptible to soft errors than DRAM; it has to do with charge density.DRAM stores charge in a small capacitor and higher density DRAMs use physically smaller capacitors, however the charge per capacitor cannot be decreased below a minimum value. Instead the capacitors have been improved and made so that they take less area, which increases the density of stored charge over a large volume. (1) A radiation induced soft error is caused by charge distributed over a large volume but if each cell is smaller with the same charge, then that has *less* of an effect on an individual cell.The result is that radiation induced soft errors in DRAM leveled off many generations ago, or even decreased.SRAM did not have this advantage of storing more charge in a given area, so as DRAM geometry decreased, it became more susceptible. Intel apparently has a SRAM design in recent processors which does not require error detection and correction, however I do not know what is going on there.(1) This would also make them more susceptible to charge leakage between cells, resulting in Rowhammer?

author: Berni
author_rank: Super Contributor
timestamp: October 25, 2023, 07:50:23 am
content: For RAM chips the extra bits are typically for parity bits.It could be used as ECC even if it is just 1 bit because you can combine multiple bytes into one larger ECC block that has enough redundancy to correct errors rather than just detect them. Tho this is mostly popular for DRAM where things get read in large blocks anyway due to the way DRAM works. For DDR3 DDR4 DDR5..etc sticks this is typically done by simply placing 9 chips on a stick of ram rather than the normal 8 (where 8x8bits gets you the full 64bit bus). There is no need to store ECC in the same physical chip it is correcting. This way they can use the same chips to produce both ECC and non ECC sticks of RAM.In FPGAs you also get 9bit wide memory. You can use it as parity there too, but more often this extra bit is used to store control flags. Like for example if you had a 8bit FIFO that is buffering data from a 10 channel ADC you might set the 9th bit high on channel 0 samples, that way you could synchronize the other side of the FIFO. In one case i used the extra bit to indicate 'control characters' for controlling a state machine for initializing chips around the FPGA on boot over SPI and such, letting me use the same memory as instructions and data.But yeah most MCUs with external memory interfaces don't support parity or ECC, so the extra bit would have to be left unconnected.

author: iMo
author_rank: Super Contributor
timestamp: October 25, 2023, 08:45:46 am
content: https://en.wikipedia.org/wiki/Single-event_upsetFor example the sram based FPGAs (like Xilinx) are not used by military or aerospace for that reason (there is some max recommended altitude). The bigger the active structures on the chip the less prone to the SEU. Satellites and other space vehicles still use an old technology in a "radhard" versions therefore..https://en.wikipedia.org/wiki/Radiation_hardening

author: magic
author_rank: Super Contributor
timestamp: October 25, 2023, 10:32:04 am
content: It's not just cosmic rays, but also dodgy or marginal hardware.I had a Kingston RAM which passed memtest86+ but suffered bit flips under a particular computationally heavy workload. I don't know how and why, and they were relatively rare, maybe once per hour. Problem went away after replacing with new RAM, coincidentally - with ECC. Since then I have never seen evidence of an uncorrected bit error, nor a corrected one for that matter. You could say ECC was overkill, but at least I know errors aren't being ignored. (Yes, I tested that ECC works).I have an old laptop where if I send some file and save it to disk, reading it back doesn't give the exact same data, with noticeably nonzero probability. Is this one machine particularly exposed to radiation, or just dodgy? I suspect it's also RAM, or maybe SATA controller or HDD cache memory chips (do they use ECC?) or something like that.

author: David Hess
author_rank: Super Contributor
timestamp: October 25, 2023, 09:47:19 pm
content: Quote from: magic on October 25, 2023, 10:32:04 amI just retired my last system (except for my laptop) which lacks ECC, an Intel 870. I think I caught it generating a bad hash but the cause could be CPU, memory, SATA HBA, or hard drive and it would take too long to track down.QuoteI have not seen any hard drives or solid state drives which uses ECC RAM. My Areca RAID controllers use ECC DRAM, and so does myPC Engines apu2which I use as a router. Unfortunately the processors PC Engines uses are being discontinued and they will be leaving the market, so it will be time to find a new x86 board for routing.

author: coppice
author_rank: Super Contributor
timestamp: October 25, 2023, 09:52:39 pm
content: Quote from: David Hess on October 25, 2023, 09:47:19 pmI think they store the blocks as they go to/from the disk, with their error correction codes attached. So, they don't need ECC RAM to have good error protection.

author: David Hess
author_rank: Super Contributor
timestamp: October 25, 2023, 10:04:27 pm
content: Quote from: coppice on October 25, 2023, 09:52:39 pmThe SATA interface has error detection and the written data has error detection and correction, which I guess is Turbo codes or LDPC codes these days but used to be interleaved BCH codes, but what about buffered data in DRAM? Drives typically have megabytes of DRAM used for read and write buffering.

author: coppice
author_rank: Super Contributor
timestamp: October 25, 2023, 10:51:44 pm
content: Quote from: David Hess on October 25, 2023, 10:04:27 pmI think they check the block as it comes in on the SATA interface. They store it to RAM, generating the LDPC, or whatever, as they go. The LDPC is checked as the block is written to disk, so a RAM fault will show up there. On read they can reverse this process, so there is error protection at every step in the chain, except around the SATA interface, where one form of error protection is swapped for another.

author: David Hess
author_rank: Super Contributor
timestamp: October 26, 2023, 02:22:33 pm
content: Quote from: coppice on October 25, 2023, 10:51:44 pmI checked what is currently available about hard drive read channels and it implies that realtime correction is done in hardware before the data is stored in RAM unless an error cannot be corrected, in which case the entire thing is stored in RAM for more thorough software correction to be applied. During writes the LDPC would be generated in hardware as it is being written.I think if the data was protected in RAM there would be some mention of it. If it was protected, then only error detection would be required because bad data could always be read again from the source. Buffered write data does not need to be protected because the system should be keeping a copy until the write is reported completed.

author: coppice
author_rank: Super Contributor
timestamp: October 26, 2023, 03:04:42 pm
content: Quote from: David Hess on October 26, 2023, 02:22:33 pmI don't actually know how they handle RAM integrity. I'm just going by an off hand comment someone who would know said to me about 10 years ago. The implication was there is either integrity checking or correction through as much of the signal chain as is feasible.

author: David Hess
author_rank: Super Contributor
timestamp: October 26, 2023, 05:07:54 pm
content: Quote from: coppice on October 26, 2023, 03:04:42 pmIt makes sense that they would do that, but if so it has to be in-band, so no extra bits are required, and it will be some sort of fast checksum, like Ethernet or IP uses, rather than what the SATA or read channel is using.

author: tridac
author_rank: Regular Contributor
timestamp: October 26, 2023, 11:30:58 pm
content: In the old days, Sun workstations and server class machines. the ninth bit was for parity error detect, or error correction (ECC) , depending on the design. More likely to be for ecc now, as that can correct errors, not just detect them...

author: David Hess
author_rank: Super Contributor
timestamp: October 27, 2023, 11:03:07 am
content: Quote from: tridac on October 26, 2023, 11:30:58 pmMy home PCs that I use as workstations have had ECC going back to the Pentium generation. The Pentium era motherboards all failed when their embedded lithium CMOS batteries died, but my Pentium II and Pentium4 systems still work.They do not use ECC only because it can correct errors, but also because the cost for single bit error correction and double bit error detection is the same as parity when the word size is 64/72 bits, so ECC comes essentially for "free".

author: iMo
author_rank: Super Contributor
timestamp: October 27, 2023, 12:40:45 pm
content: Quote from: magic on October 25, 2023, 10:32:04 amYep, from my experience that had nothing to do with classic SEU, but rather with dodgy hw. Especially memories are pretty sensitive to motherboard hw, timing settings and voltages, we former active overclockers know well..My bet with different none ECC it might worked fine as well. Also the memory sticks are often faked and cheapo chips are deployed there with reflashed timing parameters. When at edge a sligt temperature increase or voltage change causes errors, also often it depends in which slot you put the mem stick (bus load).The real SEUs are extremely rare at normal altitudes we operate our PCs (like till 3000m, for example).PS: there is app for Win (and similar for Android) detecting cosmic particles via the ccd camera chip. I did with a cheapo usb camera and it worked (I put a weak radiation source in front of it and got nice color traces, sometimes Y shaped jet after after a collision, many pixels involved, say 5-10 hits per hour). I have not detected a cosmic particle, however..

author: coppice
author_rank: Super Contributor
timestamp: October 27, 2023, 01:34:50 pm
content: Quote from: magic on October 25, 2023, 10:32:04 amIts not just the RAM. There are many motherboards which are rock solid with one memory stick on each channel, but add a second and things get flaky. Go into the BIOS, slow down all the memory access parameters, and things are rock solid again. In the mid 90s Intel had at least 2 generations of chip set which would run Win 95 or Win98 all year long without a memory error, but would barely boot with SCO Unix or Win NT 3.11 or 4. That seemed to be a problem with the more complex access patterns of these more sophisticated OSes. I have also had issues with the actual ECC hardware being the source of flaky memory problems, rather than the cure.

author: David Hess
author_rank: Super Contributor
timestamp: October 27, 2023, 02:07:57 pm
content: Quote from: iMo on October 27, 2023, 12:40:45 pmWhen I checked during the DDR generation, at sea level it was like 1 error per GB per year, and an order of magnitude higher at 5000 feet, (1) and another order of magnitude higher at the altitude airliners travel which makes me wonder if computers critical to flight systems are required to use ECC memory. Some processors, including ARM processors, intended for embedded applications include ECC support.DRAM has not become much more sensitive since then, and may have gotten a little better, but there is a lot more of it. At that time my systems had 2 GB, and now they have 16 to 64 GB, but what really matters is the silicon area in total and all of my systems since even SDR used 4 doubled sided DIMMs with 9 chips per side. Big memory arrays use many more DIMMs, and with 18 or 27 chips per side.(1) Whether a computer is at the top of a tall building or in the basement also makes an order of magnitude in difference because of the shielding provided by the building's structure.

author: coppice
author_rank: Super Contributor
timestamp: October 27, 2023, 02:20:15 pm
content: Quote from: David Hess on October 27, 2023, 02:07:57 pmFlight safety systems are required to have multiple unit redundancy, so they don't really care if one unit has a memory parity error.

author: David Hess
author_rank: Super Contributor
timestamp: October 28, 2023, 07:12:10 am
content: Quote from: coppice on October 27, 2023, 02:20:15 pmBut without ECC or parity not all failures can be known.

author: Berni
author_rank: Super Contributor
timestamp: October 28, 2023, 10:08:55 am
content: For the critical systems they use a voting system (usually triplicate), so if one device fails and makes a mistake then remaining 2 will still agree and produce the same output, so that output is then used by the voting system.But yeah the devices themselves are usually designed to also try to self detect any major failures. For example even in automotive it is common to have 2 CPU cores running in so called 'lockstep' where they execute identical code, then any difference in results triggers a error handler.

author: coppice
author_rank: Super Contributor
timestamp: October 28, 2023, 12:28:29 pm
content: Quote from: David Hess on October 28, 2023, 07:12:10 amWith true replicated redundancy you don't care. If a bad memory bit causes one box to say something stupid, the other boxes won't agree and the bad one will be ignored at voting time. In systems like that you typically keep each copy as simple as possible. That keeps the size and cost down, and helps to compensate for the cost and size addition of using multiple units.

author: magic
author_rank: Super Contributor
timestamp: October 28, 2023, 01:07:28 pm
content: What matters is not the votes but who counts the votes

author: coppice
author_rank: Super Contributor
timestamp: October 28, 2023, 01:57:23 pm
content: Quote from: magic on October 28, 2023, 01:07:28 pmThis is true. The voting hardware, human or machine, can be the most serious SPOF in the system.