Proper measurement of the fast rise/fall time - Page 1
Forum section: electronics / projects

author: CodiJack
author_rank: Contributor
timestamp: May 22, 2015, 06:10:29 pm
content: Yesterday, I faced an issue - how properly measure fast rise/fall time of the signal directly on input gate of the chip?Specification of the measured chip says: 30ns max time for rise/fall edge.In series with the chip input there is a 1k resistor.Oscilloscope used is Tek 2Gs/500MHz.Using 1:10 probe (Tek, 10M, 8pF) I can see typical RC filter response.My probe adds then additional 8pF parallel to the input capacitance of the gate, so in order to calculate a real rise/fall time, I did following calculations:- generally tau of RC filter is R*C = 0,63 Umax- measured time to reach 0,63 Umax was 20ns- then from constant RC total capacitance is 20 pF (R is 1k)- chip capacitance is then 20pF-8pf (probe) -> 12 pFIs this way correct for determining input capacitance of the chip?Would it mean that if the scope measures rise time ~27ns (with the probe), the real rise time without probe (10M, 8pF) is ~18ns?Am I missing something or there is another way to calculate it?

author: tggzzz
author_rank: Super Contributor
timestamp: May 22, 2015, 06:58:33 pm
content: You should check the chip manufacturer's definition of input risetime. It is unlikely to be an RC risetime, possibly 10%-90% or 20%-80% or 30%-70%, and probably the time spent between Viland Vih.If the driver is current limited (unlikely with a 1kohm series resistor), then calculations are much more tricky.If you are worried about probe capacitance, you could always use a "low impedance Z0" probe, which actually has a higher impedance (typically 0.7pF//500ohms or 1kohm).And, of course, what does the chip manufacture say is the input capacitance?

author: CodiJack
author_rank: Contributor
timestamp: May 22, 2015, 08:45:39 pm
content: Chip rise time is defined as 10%-90%.My doubt is what do I observe and what is a real rise time?Let say generator is giving an ideal clock via 1k resistor to the input of the chip.Chip has some parasitic input capacitance Cx.If I have ideal probe I will see a real rise time. Right?By placing mentioned below probe parallel to input capacitance Cx I gues it increases total input capacitance.Now I measure rise time 27ns (with real 8pF) probe parallel with input.So what is a real rise time on the input without the probe?The probe is 1:10 Tek P6139A.

author: TimFox
author_rank: Super Contributor
timestamp: May 22, 2015, 09:23:45 pm
content: The usual approximation (it's an interesting mathematical problem to understand the exact solution) is to add rise times of cascaded circuits in quadrature: Ttot^2 = T1^2 + T2^2. For example, if the generator has a 10 ns rise time (T1) and you pass that through a R-C network with a 5 ns time constant (which then has a rise time 2.2 x 5 ns = 11 ns), the total rise time Ttot = SQRT(10^2 + 11^2) = SQRT(100 + 121) = SQRT(221) = 14.9 ns. The factor 2.2 is correct for the 10% to 90% rise time after a single pole.Working backwards, if the scope shows 27 ns after an R-C network (1000 ohms X 8 pF = 8 ns time constant or 17.6 ns rise time), then the quadrature difference T1 = SQRT(Ttot^2 - T2^2) = SQRT(27^2 - 17.6^2) = SQRT(729 - 310) = SQRT(419) = 20.5 ns.Quadrature sums or differences are dominated by the larger term. In this example, the terms are roughly the same, so both are important.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 22, 2015, 10:27:52 pm
content: Since the maximum is 30ns, and you measure less than 30nswith additional capacitance in circuit, you are guaranteed satisfactory rise time in practice.A better question might be: why are you using a series 1k resistor, on a pin that is clearly critical of rise time? (Is it a clock input?) Doing so is most likely only going to worsen performance (RFI susceptibility, jitter, propagation delay).Tim

author: CodiJack
author_rank: Contributor
timestamp: May 23, 2015, 06:55:49 am
content: 1k a front of chip input is empirical value which increases EMC robustness. I'm aware it's not perfect but it's working.I did a mistake in the problem description, I'm sorry guys:spec. says 20ns not 30nsThat is my concern - what is real rise time without probe?Inspired by TimFox I started to calculate it differently:Tonscreen^2 =Tsignal^2 + Tscope^2 + Tprobe^2, soTsignal = sqrt (Tonscreen^2 - Tscope^2 - Tprobe^2)As Tscope & Tprobe is 0,7ns and Tonscreen is 27ns it gives Tsignal = 26,9ns.In this approach probe and scope delays are neglible.That is far different when I consider RC approach:1k * 8pF(probe)*2,2 = 17,6ns -> only for probe.If scope is ommited then Tsignal = 9,4 ns.In this approach probe is significant factor.What is then the real rise time?

author: dom0
author_rank: Super Contributor
timestamp: May 23, 2015, 07:17:12 am
content: You don't need to consider rise time of the probe itself, since that is essentially specified by 50 ? shunted by the input capacitance, but only the rise time of the LPF formed by the 1k resistor and the probes capacitance.

author: CodiJack
author_rank: Contributor
timestamp: May 23, 2015, 08:25:19 am
content: Am I considering issue in a right way?RC of the probe and series resistor is 8ns (1k * 8pF), so the rise time (10%-90%) is 8ns * 2,2 =17,6ns.Measured rise time with the probe (10%-90%) is 27ns, so measured RC of the system is 27ns / 2,2 = 12,3ns.Thus capacitance of the system is 12,3pF, what gives 4,3pF as an input capacitance of the chip.Are these calculation correct?

author: Kleinstein
author_rank: Super Contributor
timestamp: May 23, 2015, 09:54:59 am
content: Adding the rise times as squares is an approximation for independent delays. This would be something like the rise-time from the scope and the rise time for the signal.With the 1 K resistor and capacitive loading, this is a single first order system and capacity adds directly. So the 8 pF the probe adds 8 ns to the RC time constant. This is in addition to the internal rise time of the scope.In this case there are 2 parts: the risetime of the signal before the resistor and the RC combination at the input. The probe adds linear to the capacitance and the risetime of the original signal adds as squares with the RC part and for the measurement also with the scope. Using a second probe (like the mentioned Z0 probe) is a good idea to have a second independent way of measurement.So the rise time acceptable as the probe capacitance should have added at least 8 ns to the measured. In addition the would be little from the scope itself.Calculation of capacitance looks good. However to get the RC constant the 10-90% time is less suitable than 0(10)-63%. Input capacitance should also be noted in the datasheet.

author: CodiJack
author_rank: Contributor
timestamp: May 23, 2015, 08:07:02 pm
content: Guys, based on input given above, approach witch RC calculations is the right one.Additional explanation is clearly explained in:http://teledynelecroy.com/doc/probes-probingThanks for your support.