Improving Bandwidth of Discrete ECL Logic - Page 1
Forum section: electronics / projects

author: WideBandwidth
author_rank: Contributor
timestamp: February 07, 2021, 06:00:54 am
content: Backstory:I'm trying to design a VHF frequency counter (0-300MHz), using only discrete components for the heck of it (please don't start recommending <insert IC here>). An integral part of the design is a series of frequency dividers made from D flip flops. I decided to go with discrete ECL gates in order to get the 300MHz bandwidth.As an example of one of the ECL gates, here's a OR/NOR gate that I put together in a simulator. Inputs (low = 3.2V, high = 4.2V) are fed to left half of the diff pair. The differential pair is biased to 5mA and the diff pair outputs are level shifted by two emitter followers (on the right)Its DC transfer curve is shown in the second image -- looks like a good enough OR/NOR gate to me.So that's all fine and dandy at DC, but I want this gate to function at 300MHz. Using the above OR/NOR gate, I fed in a 100MHz and 300MHz square wave to one input (keeping the other input pulled down) to see how fast this gate can switch. Unfortunately, it starts to fall apart at around 200MHz (see attachment images 3 and 4). I'm currently using the MMBTH10 npn transistor because that's what I have available, and it "boasts" an ft of around 650MHz, so I think the transistor itself is my bottleneck. Can this be confirmed? Also, there's some nasty overshoot and undershoot during input transitions. I'm guessing this is some Miller capacitance issue that likely won't manifest during realistic operation (currently I'm using a 0.1ns rise and fall time for the input).So my specific questions are as follows:What is limiting the speed of my ECL gates? Is the MMBTH10 just too slow of a transistor for this application if I want to reach 300MHz switching?If I'm not being limited by my transistor choice, can I do anything to this circuit to improve its speed (please suggest any analog goodies)? I've being thinking that potentially the Miller effect is killing my diff pair bandwidth, which would mean lowering the gain of the diff pair. That would mean lowering the output swing of the gate. Since I'm already at a +/-0.5V output swing, I fear going any lower would compromise the noise margin of this gate. Is this line a correct line of reasoning?Am I just barking up the wrong tree with this ECL stuff and should switch to another logic family? My understanding is that ECL is one of the fastest around which is why I chose it for this project.Thanks in advance!

author: Ian.M
author_rank: Super Contributor
timestamp: February 07, 2021, 06:17:21 am
content: MMBTH10 Ftis 650MHz, so at 300MHz you've working with an active device with an effective gain off approx 2! Back in the era of discrete transistor logic, 10MHz was considered to be pretty fast:https://cpldcpu.wordpress.com/2020/02/14/what-made-the-cdc6600-fast/

author: WideBandwidth
author_rank: Contributor
timestamp: February 07, 2021, 06:35:08 am
content: So what you're saying is that one of the cheapest RF transistors you can find on Digikey won't do the trick here... figures! Now that you point it out, it makes a lot of sense.So going by the fact that the circuit works reasonably well at 100MHz, do you think I can get away with a transistor with an ft around 3 * 650MHz = 1.95GHz?

author: Kleinstein
author_rank: Super Contributor
timestamp: February 07, 2021, 11:10:39 am
content: In the simulation a transistor 3 times the speed should get about 3 times the speed. In real world parasitic effects can limit the speed. So the simulation is not all - maybe try to estimate parasitive capacitance and add to the simulation.For a D flip-flop , which is likely a main element for the counter, there are several implementations. Some use also capacitors to separate the slopes - these often get away with less transistors. So early discrete logic used these instead of the usualy implemantations in ICs, where capacitors are expensive.

author: tim_
author_rank: Regular Contributor
timestamp: February 07, 2021, 11:41:21 am
content: From a discrete logic connoisseur perspective, I can only applaud this effort!If you only want to build a counter (or frequency divider?), the question is whether basing it on regular logic is the way to go. In the days of slow transistors, people built pulse triggered flip flops based on AC coupled diodes and other techniques. If you construct a T-flipflop from discrete logic gates you will need a very low tdp to achieve 200 MHz operation.But anyways, I used the MMBTH10 to achived sub 1ns tpd in a logic style that is somewhat similar to ECL:https://hackaday.io/project/176107/logsThere may be ways to speed up your circuit by tweaking the biasing more. For example reducing voltage swing. I also wonder whether the emitter followers should be biased higher. The 2 kohm emitter resistor looks quite high.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 07, 2021, 12:10:37 pm
content: The waveform seems to suggest a time constant of a ns or so. Those transistors are around a pF each, and the left side has two collectors and one base (common collector), for a total of about 3pF -- more when Miller effect is included (which is noticeable too, see the preshoot).Versus the 210 ohm load resistors, that's 610ps, not too bad, so Miller effect is probably dominant. Or fT.What are the sources, by the way? PULSE of some edge rate, and 50 ohms maybe?Easy enough to test Miller effect, just cascode the diff pair. Maybe want to change the biasing around a little, the inputs maybe around 2-3V. Can add diodes (or diode strapped transistors) to increase the voltage drop at the follower, of course, every added part brings more stray capacitance. High voltage drop helps anyway as fT is reduced and Ccb increases at low Vce.BFR92, 93, 181 etc. are available with fT in the GHz. Use carefully, they'll turn any little bit of microstrip into a resonator.If you can't get these, consider doing it the old fashioned way -- use a hack. Injection locked oscillators are a cheap way to get fast division -- they're also quite cantankerous, and sensitive to the source waveform. YMMV.Tim

author: Benta
author_rank: Super Contributor
timestamp: February 07, 2021, 12:35:46 pm
content: Do you have the book"MECL System Design Handbook", HB205/D from Motorola/ONI recommend it for bedside reading. Not available officially any more, but can be downloaded here:https://www.tiffe.de/Robotron/Bausteinuebersicht/MECL/HB205-D.pdf

author: WideBandwidth
author_rank: Contributor
timestamp: February 07, 2021, 10:17:56 pm
content: Thanks everyone for all the great suggestions! I think I figured out what was causing the main slow down of my circuit (see next post). New questions have arisen though...Quote from: Kleinstein on February 07, 2021, 11:10:39 amCould you elaborate on "capacitors to separate the slopes"? Are you referring to implementing the edge triggering with something like a capacitor differentiator?Quote from: tim_ on February 07, 2021, 11:41:21 amVery cool modification to the standard ECL circuit. I'll have a go implementing it when I get the chance!Can you elaborate on "pulse triggered flip flops based on AC coupled diodes and other techniques"? I'm be very interested to know if there are other/better solutions to this problem. I'll admit I'm not well versed in digital logic, this project is basically my first foray into the subject.I also considered the emitter resistor being too large. However, delay between the input to the followers and the outputs are pretty negligible compared to the overall propagation delay of the gate. As a result, decreasing the resistor doesn't seem to change the propagation delay much at all.I took your suggestion on lowering the voltage swing -- exciting results in the next post.Quote from: T3sl4co1l on February 07, 2021, 12:10:37 pmThe source is a square wave voltage source with a 0.1ns rise and fall time and no source resistance. Thank you for pointing this out... taking into account that source resistance definitely changes things (see next post).As per your suggestion, I tried cascoding the diff pair. With the cascode, the overshoots and undershoots got significantly better, however propagation delay also increased by a hundred picoseconds or so. So the overshooting is definitely tied to the Miller effect. But it seems to get a faster gate, I need to eschew the cascode.Regarding using higher fT transistors, I happened to have a model for the NXP BFU550XR (fT = 11GHz) already installed in ADS, so I gave it a go in this circuit. Sure enough, it switches faster (no surprise there) and is able to get up to 300MHz with no problem. What is a problem is that the darn thing likes to oscillate, just as you said (and this is without any PCB parasitics)! Should I want to go higher in frequency with this project, do you have any suggestions on how to tame oscillations? If I was designing a microwave power amplifier, I might have tried to lower the gain at out-of-band frequencies. But here, nothing is really out-of-band due to all the harmonics flying around.It's looking like I won't need to consider the injection locking approach this time, but I'd be very interested in trying them for another project. Do you happen to have any resources on their design, or are they too arcane?From what I've read, they also seem to be relatively narrowband dividers which wouldn't work too well in a wideband system. So would I need multiple injection locked oscillators for different frequency ranges?Quote from: Benta on February 07, 2021, 12:35:46 pmThanks for the reference. The ECL references seem to be pretty sparse!

author: WideBandwidth
author_rank: Contributor
timestamp: February 07, 2021, 10:29:16 pm
content: So I think I figured out the issue with my original circuit. If you were to think of the differential pair like a normal differential amplifier with single-ended input, you would normally have to AC ground the non-input side of the diff pair. So I did just that with this OR gate. I also reduced the signal swing (as per suggestions) and thus the gain to a +/-0.25V output swing. So now the input and output swing between 2.9V and 3.4V:And sure enough when I feed 300MHz into it, it performs (relatively) admirably with 600ps rise time!Still not perfect, but it looks like it might barely do the trick at 300MHz.I tried sticking the gate into a ring oscillator, treating the NOR output like an inverter.This 7 stage ring oscillator has a frequency of about 155.5MHz corresponding to a tpd of 460ps -- not too shabby, but we'll see how well it holds up on an actual circuit board.Now what's not so great is when I drive the input of a gate with fanout 1 (ie another gate hooked up to the NOR output of the first gate).So it looks like the output buffer of the gate is having a hard time driving the input capacitance of the next stage. This may not actually end up being a problem, but it sure doesn't look too pretty. Any suggestions of increasing the drive capability of the gate? If need be, I'll design a darn RF power amplifier for this gate! If a solution requires more transistors, so be it. I can get 500 MMBTH10s for $4 at LCSC

author: tim_
author_rank: Regular Contributor
timestamp: February 07, 2021, 10:43:38 pm
content: Quote from: WideBandwidth on February 07, 2021, 10:17:56 pmThis is an interesting book on discrete counting circuits:https://frank.pocnet.net/other/Mullard/MULLARD_Electronic_Counting_Circuits_Techniques_Devices_20160521-0002.pdfIf this is your first look into discrete logic, why not start with RTL? That is already troublesome enough to get to work in real life.

author: tim_
author_rank: Regular Contributor
timestamp: February 07, 2021, 10:45:27 pm
content: Quote from: WideBandwidth on February 07, 2021, 10:29:16 pmIn my experience, every single of those off-brand chinese transistors was worse (slower) than the ones from a reputable supplier, e.g. Onsemi or Nexperia.

author: WideBandwidth
author_rank: Contributor
timestamp: February 07, 2021, 10:50:48 pm
content: Quote from: tim_ on February 07, 2021, 10:43:38 pmThanks for the reference, looks like I got more readingMy understanding is that RTL is just too slow for this application given the transistors I'm using. Because the transistor is saturated every half-cycle in a simple implementation, I'd need to use something like a Baker clamp to stop the transistor from saturating if I wanted to get up to 300MHz.

author: WideBandwidth
author_rank: Contributor
timestamp: February 07, 2021, 10:53:25 pm
content: Quote from: tim_ on February 07, 2021, 10:45:27 pmThat's very good to know.However, LCSC also sells MMBTH10s from Diodes Inc at 100 for $4. So not 500 for $4, but close enough! I can only hope that the Diodes Inc transistors they sell areactuallyDiodes Inc.

author: tim_
author_rank: Regular Contributor
timestamp: February 07, 2021, 10:56:52 pm
content: Quote from: WideBandwidth on February 07, 2021, 10:53:25 pmI have never tried the diodes inc MMBTH10. You could try to use their spice model to test at first.

author: tim_
author_rank: Regular Contributor
timestamp: February 07, 2021, 10:59:00 pm
content: Quote from: WideBandwidth on February 07, 2021, 10:50:48 pmEven a baker clamp will not get you to 300MHz. You will need non-saturating logic indeed.Why do you want to go to such high speed? Some of the more modern logic ICs may be better suited, although even there one has to take care of high tpd and use a pipelined design or something like that.

author: WideBandwidth
author_rank: Contributor
timestamp: February 07, 2021, 11:13:53 pm
content: Quote from: tim_ on February 07, 2021, 10:59:00 pmThe reason for 300MHz is because I'm working on VHF communication systems... and 300MHz happens to be around the high-end of that band.I'd like to avoid ICs if possible, that would ruin the fun of it all!

author: Benta
author_rank: Super Contributor
timestamp: February 07, 2021, 11:55:26 pm
content: @WideBandwidth:I applaud your project. ECL has so many positive aspects technically, but also one downside: CMOS is much cheaper in manufacturing. Too bad.Logic using BJTs in their linear operating region is great: almost no power supply noise, no unwanted transients, no shoot through when switching, very clean switching edges, no charge storage etc. etc. etc.I always loved ECL logic, but the commercial viability got in the wayKeep us updated, please.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 08, 2021, 02:19:45 am
content: Two basic ways to look at injection-locked oscillators --1. By example. Consider a relaxation oscillator, where some state variable (typically capacitor voltage) ramps up, then on reaching a threshold, is discharged suddenly (or the ramp reverses, that's fine too). Well, suppose we superimpose some ripple on that capacitor voltage. At certain frequencies, it will cross thresholdin sync with the rippleon a rising edge. How many ripples go into one ramp? Who knows. It could be any integral number; it could also be half-integer or other rational ratios, especially if the discharge process behaves like a fixed charge impulse (resetting charge by some delta, rather than discharging to some other threshold). The key point here being, if charge is not reset to a fixed and known value each cycle, then state persists between cycles, and it might be that it trips the threshold near the peak of the ripple waveform, or the valley or even the falling edge, sometimes; it might not be so stable during those edges, but it may be that the leading edge(s) are still strong enough to maintain a phase lock in some oddball ratio. Or it might be straight up chaos, jumping between different periods erratically.And you can easily understand how important the amplitude and waveform are; a peaky waveform will lock better than a smooth sine, and a positive peak (positive, pushing towards the threshold) will lock better than a negative peak, etc.And if there are ripples on ripples (i.e., mixed non-harmonic frequencies), you can see it might just do whatever... now, in general, you can't really expect a frequency counter to be well-behaved under such conditions, so that's not so crazy at least. A spectrum analyzer is pretty much needed for that.2. As a nonlinear mixing process. If we consider the oscillator as an amplifier and tuned network, then, when the loop response has poles in the right half-plane, amplitude grows exponentially. This is physically impossible, and some nonlinear process causes amplitude to limit -- pushing those poles back to the vertical axis. The poles aren't important, but the nonlinear process is. It acts to mix the signal with itself, causing harmonic distortion; but it also mixes the signal with supply ripple for example, or device noise, introducing sidebands (obviously enough, supply voltage ripple will be mixed in as amplitude modulation -- when the amplitude limiting is due to supply voltage as in a class C self-excited oscillator, for example), or phase noise. Well, if we couple in an external signal, the resulting sidebands can overlap -- even from seemingly distant harmonic terms (IMD products), and one of those products might happen to land in the passband and be amplified.Tim

author: profdc9
author_rank: Frequent Contributor
timestamp: February 08, 2021, 05:30:53 am
content: If you want a fast transistor available at JLCPCB through their SMT assembly process, you could look at the 2SC3356:https://lcsc.com/product-detail/Transistors-NPN-PNP_RENESAS_2SC3356-T1B-A_2SC3356-T1B-A-S-YS_C9659.html/?href=jlc-SMTIt has fT=7 GHz. I have used as a UHF amplifier and mixer. I'm not sure how it would work in a logic circuit, whether or not it would osclilate.There are also various Chinese copies. Not sure how these work.

author: tim_
author_rank: Regular Contributor
timestamp: February 08, 2021, 06:41:02 am
content: Quote from: Benta on February 07, 2021, 11:55:26 pmI wonder, why in general terms is ECL better in power supply noise rejection? I see that the high and low voltage levels are not locked to the supply levels like in saturation logic, so noise margin issues may be reduced. But I would assume that noise at the threshold voltage is much more important as it directly contributes to jitter.. For ECL, you should have noise creeping in through the reference voltage in very similar ways to saturation logic. Well, that is unless you use it in a fully differential way...

author: WideBandwidth
author_rank: Contributor
timestamp: February 08, 2021, 07:00:31 am
content: Quote from: tim_ on February 08, 2021, 06:41:02 amThe trick I've seen is by using a negative supply instead of positive. So Vcc = 0V and Vee = -5V or so. Any noise on your -5V rail is greatly attenuated since the emitter voltage of the diff pair is held fairly constant by the diff pair bias. And assuming you got nothing funky going on your with ground, you shouldn't get much of the way of noise on Vcc (which would otherwise couple directly into the output, unless you are taking the output differentially like you said).The other thing is that ECL causes much less power supply noise in the first place. The current going through the diff pair is held constant by the tail current source and switching from one state to another hardly changes the current drawn from the power supply. No switching current -> winner.

author: srb1954
author_rank: Super Contributor
timestamp: February 08, 2021, 07:18:41 am
content: Quote from: Benta on February 07, 2021, 12:35:46 pmIf you want something more than light bed-time reading have a look at the Motorola High-Speed Switching Transistor Handbook (1963).https://archive.org/details/High-speedSwitchingHandbook

author: tim_
author_rank: Regular Contributor
timestamp: February 08, 2021, 07:26:51 am
content: Quote from: srb1954 on February 08, 2021, 07:18:41 amI didn't know this book before. This looks really excellent as it also goes into all the device details.

author: WideBandwidth
author_rank: Contributor
timestamp: February 08, 2021, 07:33:11 am
content: Quote from: T3sl4co1l on February 08, 2021, 02:19:45 amVery nifty explanation.I have a book on such nonlinear dynamics waiting for me to read it (Almudena Suarez's Autonomous Microwave Circuits) but I haven't had the chance yet. All in due time!Quote from: srb1954 on February 08, 2021, 07:18:41 amLike tim_ said, this looks excellent! Thanks for posting it.

author: WideBandwidth
author_rank: Contributor
timestamp: February 08, 2021, 08:11:29 am
content: New developments:I put together an ECL AND/NAND gate, and it performs similarly to the OR/NOR gate, if a little worse. For the schematic, see the first attachment.Now for the exciting part. Putting these gates together, I created a D flip flop. It's constructed using a gated SR latch (two NOR gates) with the gate (two AND gates) triggered by 1.5ns edge pulses at the RF input frequency. The 1.5ns pulses are generated from the positive edge of the input through a fairly basic delay line.Why 1.5ns? Well, it worked empirically. Also 1.5ns appears to be less than the propagation delay of the flip flop. The width of the pulse needs to be shorter than the time it takes for the D input to propagate to the output, otherwise this flipflop wouldn't work too well as a frequency divider.Do you actually call this a D flip flop? I dunno.To create a frequency divider from the flip flop, the output is simply fed back to the D input.Here's how the waveforms look like at 100MHz and 300MHz inputs. Clearly there's still work that needs to be done, but I think it's a start... There's some nasty undershoot and the pulldown doesn't seem to be as strong as the pull up. Somehow I'm doubting this circuit will perform nearly as good on the bench.The main issue right now seems to be the drive capability of the output emitter followers of each gate. If a gate isn't loaded by any other gates, then the gates switch at 300MHz no problem with minimal overeshoots and undershoots. As soon as I hook a single gate to the output though (fanout 1), I see significant ringing on the output during transitions (mainly on the high to low transition). I can only guess the Cbe and Ccb capacitances of the gate input transistors are killing me here. Assuming they are around 1pF, that's 530 ohms at 300MHz and only worse at harmonics.Also if someone has a suggestion of a way to generate the 1.5ns edge pulse without eating up an additional 4 gates, I'd be happy to hear it.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 08, 2021, 11:33:22 am
content: Try 10 or 20mA in the emitter followers?Can also try inductive peaking on the collector loads, which also, if you want to get into optimization hell, you could put peaking coils just about everywhere, good luck.But just a modest, like, 30% edge rate improvement should be doable.Tim

author: mawyatt
author_rank: Super Contributor
timestamp: February 08, 2021, 04:04:47 pm
content: To follow all the good advice from others, consider cheap fast Silicon Germanium Bipolar transistors, like the $0.30 BFU725. The first practical SiGe transistors (using UHVCD) were developed back in the late 80s at IBM for CML and ECL use in the next generation mainframe computer. The SiGe bipolar based computer was later abandoned in favor of multi-core CMOS, but the SiGe technology carried on in a BiCMOS process and became widely used in very advanced ICs. We developed many chips based upon various versions of this SiGe BiCMOS process (7HP, 7WL, 8HP, 8WL & 9HP) and had our own ECL and CML logic families that operated ~100GHz.With CML & ECL designs look out for entering physical transistor collector saturation where the transistor action at the collector can go into saturation even tho the transistor terminal voltages (B & C) do not. This is caused by the resistances to the transistor B, C & E where the actual transistor "sees" a voltage different than the terminals due to a resistive drop (also see Quasi-Saturation). These resistances are caused by many things including contact (pad), wire-bond, trace, diffusion (sub-collector) and so on. Another effect called the Kirk Effect causes the transistor to slow down at higher collector currents due to high current densities which increases the transistor transit delay. Well designed CML or ECL logic is biased to stay away from these effects for the highest performance.Elementary transistor models will not accurately convey these parameters, and you'll need higher fidelity models likely not available for these cheap discrete SiGe transistors, so some experimentation is in order to "squeeze out" the highest performance.An added benefit of SiGe transistors is the superb noise figure which also benefits logic (think ultra-low noise MMW frequency synthesizers where the feedback dividers contribute phase noise).Anyway, looks like a fun project, please keep us posted on your progress.Best,

author: David Hess
author_rank: Super Contributor
timestamp: February 11, 2021, 05:02:47 am
content: Quote from: WideBandwidth on February 07, 2021, 06:00:54 amThe MMBTH10 is too slow for operation up to 300 MHz. I should be good up to 100 MHz in this application which is what you observed but see below.QuoteThe transistors should not be entering saturation if the load resistance is commensurate with the tail current of the differential pair so the usual suggestion of Baker clamping does not apply.Cascode transistors added to the output of the differential pairs will remove the Miller effect allowing higher speed operation. This is done in analog designs with the MMBTH10 to get 100 MHz analog performance.QuoteNo, I think you are on the right path with ECL.

author: WideBandwidth
author_rank: Contributor
timestamp: February 12, 2021, 08:53:17 am
content: Thanks again for all the advice.I did some more reading and realized that my D flip flop implementation using logic gates was a little naïve. It turns out that a much more robust solution can be obtained by creating two D latches and connecting them in a master-slave configuration (see attached schematics).The D latch is formed by combining a ECL buffer and a cross-coupled differential pair, the latter of which essentially acting as an SR latch. A clock signal alternates whether the buffer or the latch is active. When the buffer is active (CLK is high), the D input passes straight to the output. When the clock signal flips, activity switches from the buffer to the latch. The current output of the buffer is transferred to the latch, locking in its value and the D input is disconnected from the output. See "D Latch Schematic.png".Two of these D latches are cascaded, except their clock signals have 180deg phase offsets from each other. Essentially, only a single D latch can transmit its input straight to the output while the other D latch merely holds the value of its previous input. And thus a D flip flop is born... Of course to make a frequency divider, the output of the flip flop is fed back to the D input. In the attached circuit, the flip flop is followed by a buffer/level shift stage ("Buffer Schematic.png") which differentially drives an ECL buffer ("Frequency Divider Schematic.png").Now the results. If I try feeding a 300MHz clock signal into the input (no source resistance, 0.1ns rise and fall times, 1Vpp), I actually get a relatively clean 150MHz on the output (see "300MHz Output.png"). And this is with MMBTH10s!It looks like that fact that this entire circuit is differential (inputs and outputs) helps a lot in achieving this result. If you take a look at the inputs to the output ECL buffer ("Differential Input to Output Amplifier.png" and "Plus and Minus Inputs to Output Amplifier.png"), they're not too pretty looking. But the output amplifier is basically grossly overdriven in both directions, which is how such a "nice" looking square wave can appear at the output. But hey... the output is what matters!And best of all,only19 MMBTH10s needed per divider! 9 dividers for <1Hz resolution at 300MHz means 171 transistors. ...I'll probably design a slower divider but with fewer transistors for the lower frequencies.Given that this design seems to work reasonably well, I'll try building it up if I have time over the weekend. Unfortunately I don't currently have access to a 300MHz function generator/oscilloscope (curse you, Covid!) so 20MHz is all I can test with right now -- basically DC! I might build up a 300MHz oscillator while I'm at it.Quote from: tim_ on February 07, 2021, 11:41:21 amQuote from: T3sl4co1l on February 08, 2021, 11:33:22 amLooks like I should have paid more attention to this advice, increasing the emitter followers' bias currents really helps. It seems to be a trade-off now between drive capability and input impedance. Somewhere around 18mA (200Ohm emitter resistor) bias seems to give optimal results.Quote from: mawyatt on February 08, 2021, 04:04:47 pmI've been trying to maintain >1V headroom for the Vce of each transistor in the circuit. I find it hard to imagine a ~0.8V drop across device parasitics when dealing with ~10mA current swings (corresponding to around 80 Ohms of parasitic impedance, about 42nH at 300Mhz). But I may be proven wrong in practice!When you mention model fidelity, I once worked on a microwave PA using a Wolfspeed HEMT. The manufacturer's device model provided access to the device's "intrinsic" channel current and voltage. In your experience, is this the kind of model fidelity that would let you know exactly when your transistor is being saturated, regardless of parasitics?

author: Kleinstein
author_rank: Super Contributor
timestamp: February 12, 2021, 10:05:29 am
content: Especially for the slower stages one could consider a simple logic, AFAIK the capacitor coupled gates could get away with 2 or 3 transistors.

author: David Hess
author_rank: Super Contributor
timestamp: February 12, 2021, 08:25:04 pm
content: Quote from: WideBandwidth on February 12, 2021, 08:53:17 amI forgot to mention in my post that faster MSI logic functions in TTL and ECL are not implemented with only gate level functions. For instance, transistor based bistable flip-flops are commonly used. While I have looked for it, I have never found any reference to these sorts of logic designs beyond detailed transistor level schematics in old datasheets so you might try finding something there. The old 10K and 100K datasheets might have something.

author: mawyatt
author_rank: Super Contributor
timestamp: February 12, 2021, 09:48:22 pm
content: Quote from: WideBandwidth on February 12, 2021, 08:53:17 amRemember the intrinsic emitter is being pushed up in potential, while the collector is being pulled down during switching. It's quite easy to think a transistor is well away from Quasi-sat only to be surprised as the intrinsic base collector junction becomes slightly forward biased on switching edges. Switching edges can produce much higher currents than the set point bias levels, and if the bipolar enters Quasi-Sat, or full saturation (hopelessly lost speed) it doesn't like to come out quickly.Conventional transistor models like Gummel-Poon and VBIC don't adequately model higher current and Quasi-Sat effects, you need to move to the higher fidelity models like Mextram and HiCUM. These models are very involved and quite expensive to develop and generally not available for discrete devices I'm aware of. When you are developing ~100GHz CML/ECL static logic dividers, 150GHz resonate dividers and 200GHz frequency quadruplers they become a requirement for achieving working silicon in the 1st chip design pass, so the cost is justified!!The cross-coupled D FF is the architecture we chose for the SiGe CML/ECL dividers, including the resonate dividers. These might be useful for a crude differential signal source since they naturally oscillate without an input at the peak frequency and produce Q and Qbar outputs. I suspect you could use the differential emitters current bias source to tune the frequency.Edit: I found a 2010 Kluwer Academic Publishers text "Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL, and SCL Digital Circuits" which has some related discussions. It's an OK source, but not something I would consider a "Reference Text".Best,

author: WideBandwidth
author_rank: Contributor
timestamp: February 16, 2021, 08:27:14 am
content: So I built a prototype of the divider and sure enough, it works to a certain extent. I attached pictures of the board itself (please excuse my crummy soldering and the large gash in the lower right of the board) as well as an input/output waveform.Unfortunately my testing abilities are currently limited by my function generator which is rated to 5MHz but really starts having trouble driving the divider at around 1MHz. I might end up sticking a buffer just before the input.So attached is the output for a 1MHz "square" wave input. Sure enough, 0.5MHz comes out as expected. However, there's a significant amount of ripple on the output. I'm pretty sure the 5V supply is the culprit here, as the 5V supply exhibits the exact same ripple that I'm seeing at the output (see attached image). I measured the 5V rail directly across the decoupling caps for the output amplifier, suggesting that they aren't sufficient decoupling. I'm currently using a 100pF in parallel with 1nF. Is there a good rule of thumb for choosing decoupling capacitance? It looks like based on the ripple frequency (roughly 15MHz by my inspection), I could use a ~10nF (1 Ohm @ 15MHz) in parallel.After fixing the decoupling issue, I guess the next step is to build a 300MHz source to actually test this thing properly.Quote from: Kleinstein on February 12, 2021, 10:05:29 amThe simplest I've found is a pair of cross-coupled RTL inverters forming a latch. The state of the latch is switched by a clock signal that is fed through a highpass filter in order to get edge-triggering. It doesn't seem like a very robust configuration though, since the reliability of the edge triggering is highly dependent on the rise/fall time of the clock as well as the speed of the latch. Do you have any references to a more robust circuit perhaps?Quote from: mawyatt on February 12, 2021, 09:48:22 pmWhen you say they tend to oscillate, is this with a resistive collector load? I know a cross-coupled pair is a very populator oscillator configuration in ICs, but don't they require the usual LC tank? In all the simulating I've done for this project, I haven't seen the the cross-coupled pair with resistors in the collectors oscillate just based on device parasitics, at least with the MMBTH10. I've tried using a transistor with a higher fT (=9GHz) which liked to sing like crazy, but I think that's due to the transistor itself, not the particular circuit configuration.

author: WideBandwidth
author_rank: Contributor
timestamp: February 16, 2021, 08:31:49 am
content: I'm not sure why my previous post wouldn't let me upload this image. Here's the supply ripple

author: Kleinstein
author_rank: Super Contributor
timestamp: February 16, 2021, 09:21:02 am
content: With ECL logic the positive side is usually the reference potential. So the ground plane should be at the postive side and the supply voltage is some - 5V.Because most of the ECL gates use a current source, decoupling is not as critical, as with CMOS.Personally I am not a big fan of parallel caps - more like extra extra low value resistors (e.g. some 10 Ohms - maybe a little less here because of relatively high currens) to isolate the main supply from the decoupling caps. This is a little like RF circuits are build.I think a better ground plane would be more important than using dual caps.As far as I see it, the mast slave configuration is like a 2 stage amplifier. They may easily oscillate like a normal phase shift oscillator. So not "parasitic" LC resonator needed.With no clock it may also work a little like a ring oscillator.The RTL, capacitive coupled FF are sensitive to the clock and may need an extra buffer for the clock as part of the FF - still a relatively simple circuit. I agree that the circuit is not very robust.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 16, 2021, 11:32:43 am
content: Does the same ripple appear on GND as well? If so, it's likely common mode.If not, then it could be ringing between capacitors -- easiest plan is to arrange the VCC network in a linear chain, with bypass caps placed periodically (in terms of trace length between them), and one or two bulk caps at either end (meaning, larger than the total capacitance, and having some ESR (= sqrt(L/C) where L is the stray inductance between caps and C is an individual bypass cap) to dampen the network).Tim

author: mawyatt
author_rank: Super Contributor
timestamp: February 16, 2021, 02:00:52 pm
content: Quote from: WideBandwidth on February 16, 2021, 08:27:14 amThe loads can utilize small collector peaking inductors which extend the frequency range. Resonate or Dynamic ECL/CML dividers usually operate ~50% beyond a static divider and will self oscillate without a clock input. Do a search on the IEEE Solid State Journal, also Circuits and Systems for ECL/CML Frequency Dividers for details, likely a number of papers on this subject.Here's a short paper from 2003 using IBM's 0.18um SiGe 7HP process, and early 0.12um 8HP process.https://www.researchgate.net/publication/3385373_100_GHz_dynamic_frequency_divider_in_SiGe_bipolar_technologyPhD thesis from Caltech.https://thesis.library.caltech.edu/2296/1/Dissertation_HuiWu.pdfAnother interesting divider topology is a passive mixer based divider which requires no active devices and based upon a frequency mixer, although can be done with an active Gilbert style mixer. With a symmetrical mixer which has ports RF1, RF2 and IF, then IF = RF1 +-RF2. If IF is feed back to RF2 thru a low pass filter, then RF2 = IF or IF = RF1 -IF. Thus 2IF = RF1, or IF = (RF1)/2. Usually an amplifier is required in the feedback path to boost the signal level since passive mixers are lossy.Best,

author: WideBandwidth
author_rank: Contributor
timestamp: February 21, 2021, 01:25:08 am
content: Thanks for the decoupling suggestions. I removed the two parallel 100pF and 1nF capacitors and inserted a 22nF capacitor (because that's the first value I found) in their place. The ripple across the decoupling capacitor is now gone, as is the corresponding ripple on the output waveform. So the issue was either not enough capacitance or some resonance interaction between the two. Either way, it's basically gone. I still am not powering the circuit from a -5V rail, but I will in the final product.There is still some residual ringing on the rising and falling edge, but I think those are a product of my probing setup. The attached image is from a 70MHz oscilloscope. The input waveform is channel 1 in yellow, which is supposed to be a 20MHz sine wave. The output is channel 2 in green.I'm using passive 10x probes with those ground spring things (not sure if there's a good name for them?). The probe+scope is around 12pF input capacitance. Combined with the 50Ohm output resistance of the divider, that's a 0.6ns time constant. Connecting two probes to the same output node makes the signal look significantly worse, so there is definitely some loading going on. Now the measured rise time is about 6ns. According to a Tektronix rule of thumb (https://www.tek.com/support/faqs/how-bandwidth-related-rise-time-oscilloscopes), I should expect about 6ns of rise time with the oscilloscope I'm using. So the numbers seem to add up...Going with the assumption that the divider actually performs better than what I'm seeing on the oscilloscope, I'll go ahead start designing/building the high-frequency part of the divider chain. I'm planning on cascading three of these ECL dividers, to bring a maximum of 300MHz down to 37.5MHz. From there, I'll move to slower, but smaller dividers (whose design I haven't worked out completely yet).Meanwhile, I've also been working on the RF input chain for the dividers. The input to the first divider needs to be at least 80mV amplitude (either sinusoidal or square) to function and continues working up to around 2V. The plan is to have a ~3dB pad to get a relatively good input match followed by a balun to differentially drive a differential pair. This differential pair provides some gain, but primarily shapes the waveform a little before it goes to the first divider.Given that the divider works only works down to 80mV amplitude, I was also considering adding an additional switchable gain stage. That got me wondering about adding an AGC leveler to get a little more dynamic range out of this counter. We shall see...Quote from: mawyatt on February 16, 2021, 02:00:52 pmI recall reading that a mixer-divider tends to significantly increase the phase noise of the input. I have no clue how it would compare to my little ECL divider though, and I unfortunately don't have the right equipment to measure phase noise (unless I can physically see a signal jittering on my oscilloscope screen!). I would be interested to know how they compare though.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 21, 2021, 01:49:37 am
content: DSOX2002A is only 70MHz? I think probes will soon be least of your worries.You may want to set up an output direct into 50 ohms (BNC cable, terminated at scope), or a 10x "low z" probe (450 ohms from probe point into same). With a coax cable or BNC connector soldered directly onto the breadboard, you don't have any worry about ground pin impedance.If a reflection, the bounce rate implies a transmission line length of around 1.2m (~4') (assuming c = 0.67 c0), and the rapid decay is suggestive of a slight mismatch.Tim

author: WideBandwidth
author_rank: Contributor
timestamp: February 21, 2021, 02:28:56 am
content: Quote from: T3sl4co1l on February 21, 2021, 01:49:37 amFair point. I did notice an appreciable difference between using a ground wire/inductor versus a ground spring so at least one bottleneck is cleared up. I'm working with what I got for now!Quote from: T3sl4co1l on February 21, 2021, 01:49:37 amThe reason I didn't probe with 50ohm terminations is I didn't build in any output buffers to the prototype. But maybe I can get away without any... I'll give it a shot.Just so we're on the same page, to get your 4' transmission line length figure did you approximate the delay between the rising edge and the bounce as 12ns? Then 12ns * 0.67ft/ns / 2 is 4ft.

author: jmelson
author_rank: Super Contributor
timestamp: February 21, 2021, 02:50:50 am
content: Quote from: WideBandwidth on February 07, 2021, 10:50:48 pmThe whole point of the ECL family was to see to it that no transistor ever saturated. Storage delay was the big killer with larger transistor geometries of the 1960s and '70s. The Baker clamp tries to fix this, but just adds a bunch of capacitance with the added diodes.ECL had a number of other nice features, such as minimal transients on the supply rails when switching, edge rates similar to the gate propagation delay, wire OR capability, etc.

author: jmelson
author_rank: Super Contributor
timestamp: February 21, 2021, 02:57:22 am
content: Quote from: WideBandwidth on February 21, 2021, 02:28:56 amIBM used their own version of ECL in the 370 series. They operated it from +1.2 and -3.0 V supplies so the logic levels were about +400 mV and -400 mV. With a bit stronger pull-down current, they could terminate into ground with about 91 Ohm. So, to look at a particular signal, they extended a piece of tri-lead out to the scope and had a 91 Ohm terminator fitting at the scope input.(Tri-lead was a 3-wire planar transmission line, with a signal conductor running between two ground wires. The whole computer was wired with this stuff. All internal far ends were terminated to ground.)You could always make up a 10:1 attenuator probe for 50 Ohm termination. That is basically a 450 Ohm (non-inductive) resistor that connects to a length of 50 Ohm coax straight into the scope.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 21, 2021, 05:04:38 am
content: Quote from: WideBandwidth on February 21, 2021, 02:28:56 amIf the collector load resistors are 50 ohms, you can wire it in directly -- assuming you resolve the DC voltage between grounds. (Another good reason to move to negative supply next?)QuoteIf it is a transmission line, then 12ns is two lengths, assuming a reflection at the far end. Exactly.It may not be a TL effect, it's hard to say with such little bandwidth of course -- but if it is, you'd be suspecting something on the order of this dimension.Alternately, it could be lumped equivalents of say 220nH and 62pF (or some other ratio, who knows what impedance is in play, between circuit and probe). 220nH could be about 10" of loose hookup wire, not sure what would be around 62pF.Most likely candidate I'd guess is just the probe and scope, either not being quite well matched, or just poorly tuned.Tim

author: WideBandwidth
author_rank: Contributor
timestamp: February 21, 2021, 05:28:10 am
content: Quote from: T3sl4co1l on February 21, 2021, 05:04:38 amYeah...the first time I tried probing with a 50ohm termination, stupid me forgot to insert an AC coupling capacitor between my scope and the circuit, shunting the output at DC to ground with 50ohms. I'll try again with the capacitor in place.Quote from: T3sl4co1l on February 21, 2021, 05:04:38 amMy scope probe is 48.5". It's almost like you were there with a tape measure!

author: WideBandwidth
author_rank: Contributor
timestamp: February 21, 2021, 06:50:36 am
content: I bodged in a BNC jack and measured with a 50ohm coax cable and 50ohm terminator this time. Sure enough, the "bounce" in the rising edge has disappeared. The waveform still has some ringing, but nothing that looks severe. The measurement seems to be completely limited by the scope bandwidth now, and there's not much I can do about that for the time being.Some of the residual ringing may be due to the other decoupling capacitors I haven't bothered to replace (100pF in parallel with 1nF) scattered throughout the board. In the final design, I'll change that up.

author: David Hess
author_rank: Super Contributor
timestamp: February 22, 2021, 07:45:19 pm
content: Quote from: jmelson on February 21, 2021, 02:57:22 amDoes that explain the existence of 92 ohm coaxial cable?

author: jmelson
author_rank: Super Contributor
timestamp: February 23, 2021, 02:09:34 am
content: Quote from: David Hess on February 22, 2021, 07:45:19 pmNo, I don't think so. I suspect 92 Ohm cable existed long before the 370. I think the 360 also used 91-92 Ohm coax to connect peripherals. The choice of 91 Ohms might have had to do with achievable impedances with the 3-wire transmission line, or maybe even because 92 Ohm cables were standard.

author: WideBandwidth
author_rank: Contributor
timestamp: February 28, 2021, 10:41:26 am
content: In a mild detour from the frequency dividers, I've been working on the RF input chain for the frequency counter. In addition to the 300MHz bandwidth, my goal is to support an input range of -30dBm to 23dBm. The frequency divider itself has a roughly 20dB dynamic range. To achieve a 53dB dynamic range, I employed a switchable 20dB attenuator as well as a variable PIN diode attenuator used in an AGC loop. The preliminary schematic is attached.The RF signal first sees a 3.5dB pad to ensure a good input match. The comes the switchable 20dB attenuator. A diode power detector samples the input power just before the 20dB pad. If the power is above 3dBm, then a comparator switches the 20dB pad in using a PIN diode switch. Otherwise, the 20dB pad is bypassed.Next is a variable PIN diode attenuator followed by an amplifier. The output of the amplifier is again fed to a diode detector which acts as the input to a feedback amplifier. (Note: in the schematic, I forgot to add a DC path to this diode detector -- I'll fix this.) The feedback amplifier controls the variable attenuator in order to keep the output of the amplifier at roughly 0.5Vpp into a load of 100 Ohms (except for low input powers, for which the amplifier output begins dropping off).The output of the amplifier is fed through a balun to a differential pair which helps to shape the RF input into a more square waveform. The differential output of the diff pair is what is fed to the first frequency divider in the divider chain.Some of the resistor and capacitor values need to still be tweaked, but they should all be coarsely correct (unless I mislabeled one of them). I have no idea what the noise performance of this circuit is, but I'm hoping that with a minimum power of -30dBm I'll be alright. I also just realized that I screwed up the output stage of the feedback amp in the AGC loop - the output can only rise up to 3.8V!Comments are welcome!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 28, 2021, 01:00:02 pm
content: Hmm, seems like a lot of work, for just increasing internal state! Maybe that's justified, I don't know.Would it be better to bypass R28-R29 and cut off R31, two instead of three switches? Think the downside would be, the stray capacitance of those nodes (either end of R31) would slightly increase HF loss, probably, who cares. The alternative is the several short stubs left by the diodes and C22, C25, C31, C32, which shouldn't be much impact either.Zin won't be very flat, that's for sure; a bit of an annoyance. Maybe VGA instead of variable attenuator? I suppose the worst case is if the particular VA state causes excessive loading on the input, and the input level is just on the 20dB atten threshold -- it oscillates. One of those problems with internal state.Hmm, Q43 is definitely never going to turn off, and a few other things. Maybe you meant Q34 to be PNP?Could also do a one of these,though it still needs complementary inputs of course. Which could be taking advantage of the diff pair's balanced outputs (so, would have to get rid of Q26-27 current mirror; a pair of equal current sources would do). Or really, since the output current requirement is rather modest, just a pair of common-emitter (PNP) would do, for pulling up anyway; pulling down could be just passive (a few mA extra of CCS's, or even resistors for all that really matters here), or maybe something cross-coupled so that it acts as a... current anti-mirror as it were, I guess: when one side gets pulled up (hard), that side load turns off and the other side load turns on.L2-L3-C27, probably won't work as well as hoped? -- again the impedance is all over the place, so the filter response will not be consistent. Also not sure if that's matched to the transistor, I'd have to model it, easy enough to figure out. Interesting putting neutralization over it.The transformer, could be replaced with... something, hmm, it's not like you need differential drive to the differential pair. Which could be cascoded too, to reduce coupling from inbalanced inputs for example. Heh, or a common mode choke... nah. Or cascade two diff pair stages to clean up balance the brute-force way.Oh, heh whoops -- C6 and Q20/21 are missing DC bias!BTW, have you noticed the BFU550 is order(s) of magnitude better than MMBTH10? Might consider using all that instead...Tim

author: WideBandwidth
author_rank: Contributor
timestamp: February 28, 2021, 06:30:27 pm
content: Thanks for all the great advice Tim, as per usual.Quote from: T3sl4co1l on February 28, 2021, 01:00:02 pmIf I wasn't looking for work, I'd be using actual opamps instead of my BJT abominations! Though for achieving the 53dB dynamic input range, I'm not sure of a simple solution. I suppose a single variable gain amplifier with gain range from roughly -20dB to 20dB could work, but designing such an amplifier is nontrivial. It would be difficult keeping the return loss flat over that range, I imagine. Unless something like a dual-gate FET were used perhaps so one wouldn't have to worry about input impedance change versus bias current? Something to consider for a future project maybe...The reason I'm using the 20dB switchable pad is due to the limited dynamic range of the variable attenuator. The VA PIN diodes start going haywire (read: stored charge runs out, output goes nonlinear) above about 5dBm input.Quote from: T3sl4co1l on February 28, 2021, 01:00:02 pmThis sounds like a better idea than my solution. I think any loss induced by the circuit topology would be dwarfed by the PIN diode's loss itself (a couple tenths of a dB typically).Quote from: T3sl4co1l on February 28, 2021, 01:00:02 pmFrom my simulationsTM, Zin should indeed be flat! I've attached a return loss plot of the variable attenuator which sweeps the tuning voltage across its entire range. Return loss is above 15dB over the entire range. At full attenuation, the shunt diodes of D3 and D4 act as 50ohm resistors (assuming proper biasing). And as the tuning voltage is increased, the combinations of all the diodes looks like PI pad. The trick is choosing the bias resistors correctly for the diodes correctly, which seems like it will end up being an empirical process. But assuming the diodes are anywhere near their SPICE model, the resistor values I have listed should be somewhat close.I also just now realized that R43 should be pulled down to -5V, not ground... whoops.And with the L-C-L matching network, the return loss for the amplifier is above 15dB from 1MHz to 300MHz (again, according to NXP's ADS model. Might need some tuning to get it just right). The switchable 20dB pad keeps everything in its linear regime, so the return loss should stay where it is as the input gets up to 23dBm.Quote from: T3sl4co1l on February 28, 2021, 01:00:02 pmBecause the return loss of the VA is >15dB over the tuning range, the load on the 20dB pad shouldn't change much at all?The comparator for the 20dB pad is also configured with some hysteresis. The 20dB pad gets switched in at about 3dBm and disconnected at about 0dBm. Hopefully that should stop any oscillatory behavior.Quote from: T3sl4co1l on February 28, 2021, 01:00:02 pmLet me attempt to explain the logic behind my BJT comparator concoction... Q26,Q27,Q39,Q40 of course is the comparator itself. However, the output can only swing from ~0V to ~5V. Meanwhile, I want to drive the PIN diodes from -5V to 5V (though now that I think about it, I can probably get away from 0V to 5V...). Q34 just to buffer the high output impedance of the comparator, while Q37 is used as a level shift, giving both 0-5V and -5-0V outputs. Q33 and Q41 invert the swing, turning giving 5V-0V and 0V--5V outputs. And these signals drive the H-Bridge Q28,Q29,Q43,Q44 transistors.The collector of Q37 actually swings from ~-0.3V to ~-3.5V turning Q41 off and on. The PNP is intentional!The reason I went with the current mirror load for the diff pair was because I wanted some fairly decisive comparator action. With only a resitive load, there's not enough gain to switch between states when the input RF power is just on the threshold. Two current source active loads would do the trick though... I'll take a lookAnd thanks for the H-bridge suggestion. Looks like I should be able to replace three transistors with resistors!Quote from: T3sl4co1l on February 28, 2021, 01:00:02 pmThe reason for the differential drive is that as the frequency gets dangerously close to the fT of the MMBTH10, they don't work so well anymore (surprise, surprise). When the diff pair is overdriven with a single ended input at a high frequency, the output waveform starts to distort significantly in a asymmetric manner. With a differential input, the distortion still occurs, but the distortion is symmetric (for both positive and negative swings). That's how I'm able to get away with MMBTH10s at 300MHz.I'll look into your cascoding suggestion though and see if that can clean up the asymmetry of a single ended input.I'm not sure if two diff pairs could do the trick though. The inbalance gets pretty bad (see some of my first posts in the thread, for example #24), and I'm not sure it can be recovered from by an additional stage.Quote from: T3sl4co1l on February 28, 2021, 01:00:02 pmD'oh! Thanks for the catch. I got too excited wiring up the last stage.Quote from: T3sl4co1l on February 28, 2021, 01:00:02 pmNo kidding! But as Spiderman says, with great fT comes great oscillatory behavior (or something like that). The BFU550 rings like crazy in the frequency dividers and needs some compensation to take the edge off the high frequency gain. The MMBTH10 by comparison is a pleasure to work with.I guess if I decide to take the max frequency up any further, I'd have to switch out the transistors.And also the BFU550 costs a whole 7 cents more in quantities of 100 from Digikey. I'm always up for saving $7!Keep the comments coming.

author: WideBandwidth
author_rank: Contributor
timestamp: February 28, 2021, 08:47:59 pm
content: And just for kicks, here's simulation results for the amplifier. The simulation includes the input matching network and assumes a 100 Ohm load (representing the input impedance of the diff pair). Due to the 50 ohm resistors on the diff pair, the input impedance is indeed fairly close to 100 ohms up to 300MHz.The gain is pretty flat all the way up 300MHz (the 3dB point is around 370MHz) and input return loss is below 15dB across the band. On the output side, the P1dB is at roughly -20dBm input power/5dBm output power (referenced to 100 ohms), or about 1.3Vpp output voltage. So more than good enough for this application since I need about 0.5Vpp into the 100 ohms.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 28, 2021, 09:28:56 pm
content: Quote from: WideBandwidth on February 28, 2021, 06:30:27 pmWell, any kind of cascode will do that -- a dual-gate is just a monolithic one really.I would think something like, steering signal current between common mode or differential (think single balanced 3-BJT mixer?), or into a load dump (Gilbert cell?), would be reasonably well behaved in terms of input impedance. The remainder can always be dumped into an attenuator (i.e. equalizing network), or you could just take the hit on noise factor with a high-Z input and terminator (FET follower I suppose?). You're not after so much dynamic range that noise is a huge problem, I think? Not that we should like to just throw away dynamic range, of course.But yeah, also can't say I've spent the time to design a proper high performance VGA; and the ICs of them tend to be rather pricey -- though that may be more due to small quantities than design/production/test difficulties, who knows?QuoteHuh... still unconvinced. Like, then if the bottom (shunt) halves go down to about 50 ohms each (If ~ 1mA according to the datasheet), how do the top (series) halves ever increase?Or... maybe the symbol is wrong, or the pinout? If control were on the midpoint and the anode was biased somewhere, that would maybe do it, I think?But if there's an arrangement that actually works -- yeah, that's fantastic, no problem with input voltage dependency or filter weirdness, scratch that!Only downside then, of course the PIN diodes don't work down to the low MHz or whatever. I suppose this is RF specific, or just a prescaler, or the low range can be done with ordinary comparators and logic (or their discrete say R/D/TTL equivalents, if you still want to be that way). Just nicer to have it all in a single range. Maybe later, or something.QuoteAh yeah, more matching than filtering, that kind of explains the odd values too I suppose. Just happens to also be a LPF.Quote-- Or for that matter, you're doing +/-5, a total of -10V in reverse, which is good up to almost 30dBm I think?Quote'Cuz I look at Q34+Q37, and see a zero-offset follower: if Q34 base can go down to about 0V, its emitter is about -0.7, and Q37 emitter back at 0. Actually they're a little off, because Q34 has less bias, so a smaller Vbe (by about 60mV, because Ic differs by about a decade -- R73 vs. R50), so Q37 emitter can be a little higher.This holds as long as Q37 doesn't saturate, which due to the symmetrical loads, is true until it goes below zero, where it'll stop just above zero on its emitter, and just below on its collector. Or, well really if we include full base current, which we can because hFE(sat) --> 0, then it could be about 5% below that, or say, -90mV or something (emitter).Anyway, the weirdness that jumps out at me is this: Q33+Q41 switch near GND, Q28+Q43 switch near the rails. There's a whopping 0.7 to 4.3V range where they overlap. And collector current is completely unlimited -- suicide bias, better hope hFE doesn't rise too much!Maybe the hysteresis is enough (it's about.. 25mV?) that it slews quickly, Idunno. It's not like it's spending a huge time in the linear range, at least if it's not oscillating.. or not exposed to AM straddling the threshold and slow enough to pass (R64-C38 time constant). It's just... kinda ugly tho.Also, earlier I misread the typo -- I now see Q43 base was supposed to be to Q37 collector, in symmetry with Q28.Is it possible that your circuit is, in fact, perfect, and all my concerns have been over damn typos?Low on sleep? Working hastily? Dyslexic?---well, not quite literally heh, schematics are a language, but a highly graphical one, is there a sort of dysgraphia that might occur here or is that still included? Not sure...Aside... I wonder how much dyslexia or similar conditions affect schematic performance, or layout too. Don't think I've heard anything about it, in this field specifically. Hmm!Oh, also also, it seems asymmetrical for C35-C36, and also C16, to be on +5, and nothing on -5. I tend not to pay much attention to bypass caps, they can be literally anywhere on the design, and if this is one page in a larger design (if not right now, then eventually?), who knows what else is there. If it was your intent to represent approximate physical location here, then that's something to look into.QuoteYeah. The transformer pops out at me, as it's one of those things that -- if you're doing this for yourself, by yourself, who cares; but if you ever want to make more of it, or invite others to do so, you're either forcing them to wind that transformer themselves, or, forced into whatever meager offerings you can find in suppliers' catalogs. Now, 100 ohms 1:1 1MHz+, something like that, probably out there -- probably not important in this case.Oh also hey, for that matter, since it's a transformer, you might as well centertap the secondary, that will help with CMRR. Don't need the double termination then, just one R. Commercial equivalent being just whatever matching transformer or balun you can find, and that shouldn't be much harder to find in these ratings, Ithink...QuoteAren't you glad I didn't suggest putting in a 60GHz PHEMT or whatever?Tim

author: WideBandwidth
author_rank: Contributor
timestamp: February 28, 2021, 10:52:55 pm
content: Quote from: T3sl4co1l on February 28, 2021, 09:28:56 pmCool, I hadn't thought of that method for this application! A definite advantage is that it would work down to DC unlike PIN diodes. Regardless though, I've got AC coupling capacitors everywhere which will also limit low-frequency performance. I was mainly intending this RF chain to work down to roughly 1MHz. For lower frequencies, I'm planning on a high input impedance buffer instead of this 50 ohm input circuit. Perhaps once I get the actually system working, I can rework the RF input a little. Something for the future.Quote from: T3sl4co1l on February 28, 2021, 09:28:56 pmYou got me again. The shunt diodes in D3 and D4 should be facing the other way... Had it correct in ADS but not in Altium. It's looking like I really need to sit down and make sure there's no mistakes in the schematic.Quote from: T3sl4co1l on February 28, 2021, 09:28:56 pmI guess what's happening here with Q34 is this: the output of the diff pair and Q34 are biased at a much lower current than than Q37. As a result, the diff pair and Q34 both have roughly 60mV less Vbe, like you mention. So the output of the diff pair can go down to roughly -400mV. The Vbe of Q34 at its low bias current is somewhere around 450mV, meaning the base of Q37 gets to around -850mV, enough to turn it on... just barely. Maybe a diode on the base of Q34 to give some more wiggle room, or maybe just a different configuration altogether.That Q34+Q41/Q28+Q43 issue does sound like a large problem -- I'd rather not smoke my poor transistors. It sounds like I need to think about this topology a little more.Quote from: T3sl4co1l on February 28, 2021, 09:28:56 pmYeah, I kinda halfheartedly stuck decoupling caps in some places but not others. I'll definitely have them on both rails!Quote from: T3sl4co1l on February 28, 2021, 09:28:56 pmI got a bunch of toroids lying around, might as well use them!I guess it shouldn't be too hard, once a board is made up, to swap the transformer in and out to see how much of an effect the differential connection to the diff pair makes.I do like the centertap modification.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 28, 2021, 11:54:57 pm
content: FYI, the H-bridge shoot-through thing is easily solved, for example using resistor dividers from the voltage gain nodes to the bases, so that each base sees a Thevenin voltage of say 1.4V or so (i.e., the voltage at the base, when the base is disconnected from the divider). It's just a lot of bother, almost doubling the resistors used in that area.And as long as you're using resistor dividers, it doesn't have to be driven from 0..5 and -5..0V, you don't need all four complementary gain nodes, -5..5 will do. That's why I like the CE stage after the diff -- besides increasing total gain (it's a comparator, it can have tons of gain), hanging one stage off each side (again, diff already makes the complements) gives you a full output swing, a faster swing, and more current besides.O'course, we don't need a whole lot of drive current, and already having a -5..5V swing and its complement, means we're done. Hey, we can lop off that output stage, nice!So, if you like, your version is certainly on the right track, it just needed some tweaking and optimization; it just happens that optimization was unusually effective here.Related things -- the extra level shifting and inversion can be handy when supply voltages are higher, so you want to save on bias current and voltage drop to the output transistors. The phase-inverter motif is nice for stuff like that, maybe cascoded with a higher voltage transistor for purposes like this. (The emitter side would have to be, well, it's not a cascode as such, but it would look like a complementary diff pair -- put some resistance between emitters, to set the transconductance.)Or flip it around, use an NPN and PNP, emitters to GND, bases together (input must swing +/- 0.7V, would need a little level shifting to work with the diff pair as-is here), collectors going wherever.Also helps for MOSFETs, where Vgs should be limited to save on gate charge, or to function at all (stay within Vgs(max)). MOSFETs would be a poor drop-in to your circuit as-is, both because of the weak drive (~10kohms, drop the base resistors obviously) and the misaligned/mistimed voltages. But again that's just a matter of shifting around voltages and thresholds, and the same sort of level shifting as above, would apply nicely here. (It wouldn't however be able to save you from the poor performance of PMOS.A discrete bootstrap NMOS driver is a bit of a different thing, as it has a source follower characteristic relative to its input pin (assuming noninverting gate driver) so you need a huge voltage swing to start with.)Tim

author: David Hess
author_rank: Super Contributor
timestamp: March 01, 2021, 12:31:48 pm
content: Frequency counters usually use differential limiting amplifiers rather than automatic gain control.

author: WideBandwidth
author_rank: Contributor
timestamp: March 03, 2021, 09:04:51 pm
content: Quote from: T3sl4co1l on February 28, 2021, 11:54:57 pmI've updated both the comparator and the AGC feedback amp.Taking your suggestion, I've replaced the level-shifting weirdness with a couple CE outputs. Looks like that'll work a lot better without an shoot-through issues.On the AGC side, I added a push-pull output stage. The issue I was having before was two-fold: first, the output wasn't the greatest; second, the current drive capability wasn't good enough. With the way it's setup now, I'm expecting roughly -4.2 to +4.2V swing and the capability to source/sink at least 15mA. That's enough current to the attenuator to get down to around 1dB attenuation.I also swapped out the 1:1 transformer from before with a Ruthroff 1:1 balun, which can be easily center-tapped with a trifilar winding around a toroid, also giving a convenient way to bias the diff pair.Quote from: David Hess on March 01, 2021, 12:31:48 pmFair point... I guess I wanted to experiment with an AGC since I've never built one before. Consider it an experiment.

author: tim_
author_rank: Regular Contributor
timestamp: March 04, 2021, 09:08:30 am
content: Quote from: WideBandwidth on February 28, 2021, 10:41:26 amJust wondering, maybe another option for the input amplifier would be a cascade of differential amplifiers with limiting behavior, like it is done in optical receivers. The benefit is that the output is a differential digital signal that can be directly fed into ECL logic. Also you can use various bandwidth enhancement techniques like cherry-hooper.Just a random example from image search:https://d3i71xaburhd42.cloudfront.net/aee30b9d1b7f93ad8f889ecb9a68051c68fed91b/1-Figure1-1.png

author: mawyatt
author_rank: Super Contributor
timestamp: March 04, 2021, 02:37:19 pm
content: Quote from: tim_ on March 04, 2021, 09:08:30 amWe used cascaded CML gates for the high frequency limited function, works well since they are really just wide bandwidth diff amps anyway.Interesting you mention the Cherry-Hooper amp, they are superb limited amplifiers (if carefully designed) with "clean" limiting waveforms and using high speed bipolar (like ~400GHz SiGe, or ~600GHz InP) devices the performance is outstanding. When I retired a few years ago we were working on an adaptation of the Cherry Hooper coupled with a Caprio-Cell in the core center, which created a unique device that had equal but opposite PN junction transitions for current mode operation. End result was amazing linearity at millimeter wave frequencies, kind of a fully differential input output op-amp with THz GBW product. We placed a commutating quad of bipolar devices on top this Cherry-Hooper/Caprio current mode cell for a Gilbert style mixer, simulations reveled nearly +50dBm TOI utilizing HICUM device models.Best,

author: tim_
author_rank: Regular Contributor
timestamp: March 04, 2021, 04:28:05 pm
content: Quote from: mawyatt on March 04, 2021, 02:37:19 pmWell, I learned about cherry-hooper limiting amplifiers from Razavis great book (Design of Integration Circuits for Optical Communications). I have seen the Caprio Quad before, but didn't know the name. Very interesting, thanks! Trying to hunt down the original paper.Your design sounds very impressive. That's certainly a couple oom beyond what we are discussing hereI feel itched though, how far one could push an MMBTH10 in a C-H limamp. I found an old C-H LNA I once tried in LTspice that went to 500 MHz 3db BW. (Please ignore the bad way of biasing the input).

author: mawyatt
author_rank: Super Contributor
timestamp: March 04, 2021, 06:01:36 pm
content: Quote from: tim_ on March 04, 2021, 04:28:05 pmTim,Great book indeed!!Your schematic doesn't look like any Cherry-Hooper amp I'm familiar with, although all we developed from 80s on were fully differential I/O. The CH amp is very tricky to get right, selecting the right size transistors (not all the same) and various impedance levels, device bias points and voltages, as well as the current ratios are very important. I'm not familiar with the MMBTH10 device, but past experience reminds me that you might expect something well into the fractional ft bandwidth at the bias of the minimum ft device in the direct signal path (this is from memory tho). Generally lower impedance levels reflect higher bandwidth, however you must pay close attention to saturation and quasi-saturation in all active signal path devices and do this for dynamic currents not just static bias levels (common design mistake). Watch the ft curve vs. collector current, once the current goes past the peak the ft falls off quickly due to Kirk-Effect (current crowding), also watch this ft vs. current with dynamic currents not just static. Selecting the device size is obviously important for the mentioned reasons, but if you are not doing an IC, then you are restricted to discrete devices, so paralleling becomes useful for critical devices.Caution, the simulations you get without the benefit of more involved transistor models like HUCUM and MEXTRAM will mislead and the AC simulations will be in error simply because these are steady state and do not represent the dynamic current-voltage behavior mentioned. Don't know what models are available for MMBTH10 but you might consider constructing circuits with LTspice to simulate various device parameters to verify the device model with the data sheet measured parameters. I'll wager that the model doesn't do an adequate job at higher relative collector currents.The Caprio cell dates back to the early 70s I recall, was used to help improve low frequency amplifier linearity. By cross-coupling the collector currents travel thru equal but opposite controlled junctions and the current voltage waveforms experience sum total equal but opposite perturbations in each path. Or put another way, the waveform currents are flow thru devices where the sum of all the base emitter voltages experienced in each differential path is equal, so the difference is nulled out.Best,

author: tim_
author_rank: Regular Contributor
timestamp: March 04, 2021, 06:42:45 pm
content: Hi Mike,it's basically half of a differential C-H (see appendix) with an additional emitter follower. Q10 is the voltage to current stage, Q9 plus the feedback resistor form the TIA-stage.Of course this is not very useful as it is, especially since the gain is quite instable.Yeah, LTspice certainly is not the best tool for HF design. I am using onsemis spice model of the MMBTH10 which seems to give somewhat agreeable results for the designs I tried so far (usually <400 MHz BW).

author: mawyatt
author_rank: Super Contributor
timestamp: March 04, 2021, 07:43:07 pm
content: Tim,Thanks, I see now!!LTspice should be fine if the device model is good enough.Edit: Just looked up the MMBTH10 transistor data sheet, it didn't show the measured ft vs. collector current plot. This is a very important parameter for selecting the bias point and dynamic current excursions for optimal performance. Did you find a data sheet that showed this plot?Best

author: WideBandwidth
author_rank: Contributor
timestamp: March 15, 2021, 06:14:58 am
content: So I reflected for a bit... and I decided follow everyone's advice and ditch the AGC in favor of the suggested solution of cascading limiter amplifiers. I took a look at Razavi's book -- very cool stuff in there.I took a shot at the Cherry-Hooper amplifier, and I attached my attempt. I've cascaded three limiting amplifiers for a combined small-signal S21 of 60dB in 50ohms, dropping to 53dB at 300MHz. It's certainly possible to get even larger bandwidth by tuning biases and resistances, but I've found that doing so either results in significantly decreased output swing and/or undesired peaking at high frequencies. I haven't yet gone through the in-depth analysis for these amplifiers, but that's for a time when I don't have finals the following week.Because of the low-ish bandwidth, 300MHz signals come out looking fairly sinusoidal. Thankfully that's not an issue for the frequency divider as I've designed it, so no further tuning is really required.I'm powering the amplifiers from -5V which yields -2.1VDC at the output -- perfect for driving the first frequency divider without any additional level shifting.As a side note, I'm planning to build the frequency counter in modules to make design and development a little easier. I.e. one board for the RF input, one board for the ECL frequency dividers, one board for lower frequency frequency dividers, etc. The plan is to connect everything up with 50ohm coax (RG316). Now because everything past the limiting amplifiers is operating at fairly high signal swings (+/0.5V or so), should I put in a lot of effort to shield each board from both the outside world and from each other? I was envisioning enclosing each module in a box made of blank copper-clad boards, but I'm not sure if that would be overkill here. I suppose the FCC would be happier if I did. Any suggestions?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 15, 2021, 10:04:52 am
content: That's a damn fine looking frequency response!Is that simulated or measured? What's the layout [going to?] look like?C36 seems to be in the wrong place, and also may pay to be distributed along the trace, much as the supply is well bypassed -- in my experience only 1nF is needed here, so a few of those will do a fine job. Bypassing the CCS base, introduces a pole-zero into its response; using a capacitor about this or larger, makes the step in frequency response small enough not to matter (<< 1dB).You're definitely going to need shielding, with that much gain available. I think it will be marginal on a 2-layer ground plane build without shields (assuming a linear layout so the input and output have maximum distance between), maybe just possible, or maybe prone to weird peaks and dips in the frequency response. Just something to cover it up, should do the trick.Tim

author: mawyatt
author_rank: Super Contributor
timestamp: March 15, 2021, 04:53:24 pm
content: Looks like you are getting ~ft/2 out of this single ended CH amp with MMBTH10 transistor, which is good but realistically think you'll be a little lower with actual hardware. The input transistor bias will be highly supply, temperature and device dependent as shown (no realistic DC feedback), which normally isn't a problem with the differential CH since the emitter tail currents are set by the emitter current sources. Might consider altering the base bias in some way for better DC stability. This will also allow you to investigate the effects of the inner and outer loop bias currents and how they affect the response. Since you are a student this would be a good exerciseOnce you get a handle on this single ended version consider the differential version, these are quite popular with high speed fiber-optic usage. If you are interested in the limits of these type amplifiers, Dr. Mark Rodwell @ UCSB is leading the charge.https://web.ece.ucsb.edu/Faculty/rodwell/default.htmlAs mentioned above circuit shielding at this gain level will be required, also watch the cables, the cheap stuff isn't double braid shielded and can corrupt measurements.BestEdit: Should add that one of the benefits of the CH is the smooth limiting behavior when setup (bias, transistor size) correctly, also the BW doesn't degrade as much as other type amplifiers when limiting.

author: WideBandwidth
author_rank: Contributor
timestamp: March 15, 2021, 05:59:34 pm
content: Quote from: T3sl4co1l on March 15, 2021, 10:04:52 amThis is all simulated, so don't get too excited yet.I'll probably have layout time this weekend, but as you mention, I'm envisioning a straight line from input to output to minimize any coupling paths.Regarding C36, wouldn't the bypass on the CCS base only introduce poles and zeros into the common-mode frequency response since that common emitter node of the diff pair is a virtual ground?Also any comments on the other decoupling caps in general? I mainly plopped two caps down next to each stage just to give me two sets of pads to experiment with different values. I fear the 4.7uF may be a little too much.Quote from: mawyatt on March 15, 2021, 04:53:24 pmJust so we're on the same page, I only see differential CH amps in my schematic. Are you referring to the DC bias of the first amp that's driven single ended? My understanding is that because transistors of the outer diff pair have the same Vbe, there will only be a DC offset in the output. Which means that the inner diff pair will not have the same Vbe...hmm. So what could happen is the diff pairs could be biased near the compression portion of the tanh gain curve?Do you think a few ohms (~10ohms given the 7.5mA bias current) of emitter degeneration of the outer diff pair would do the trick?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 15, 2021, 06:54:14 pm
content: Quote from: WideBandwidth on March 15, 2021, 05:59:34 pmIndeed, but what CMRR are we talking here? And, can you measure such from the simulation, given identical SPICE models? And will that be representative of real, unmatched devices? Ah, see, there's the rub...The input is especially sensitive, due to its unbalanced drive; it won't take much imbalance in the output to get problematic feedback to it.The stages could also be biased independently, which really, even just isolating the input stage in this way, might not be a bad idea. It's just another three parts!QuoteAside from being, probably several decades larger than needed for any significant effect? Wouldn't think that's a problem, in and of itself. Just route VEE in a regular manner, and add some damping at one or both ends, that'll keep it nice and quiet. Maybe even some chokes between stages, to help isolate them?Tim

author: mawyatt
author_rank: Super Contributor
timestamp: March 16, 2021, 03:45:48 pm
content: Quote from: WideBandwidth on March 15, 2021, 05:59:34 pmIt's your single ended schematic here:https://www.eevblog.com/forum/index.php?action=dlattach;topic=269568.0;attach=1186242;imageThis shows input being biased with a resistor to almost Vcc which is what I was discussing. Also in your design consider what the transistor currents will be during limited which is the intended usage I understand. Watch out for this current forcing the transistor into Quasi-sat or entering the Kirk Effect, both of which will severely reduce bandwidth (likely these are not accuratly modeled with MMBTH10). This can cause issues with the inner and outer loops entering a region where the the overall stability is compromised and may show up a ringing on the limited waveform.BTW a technique we developed in early Berkley SPICE days to evaluate closed loop stability without "breaking the loop" like you normally do with Bode plots was to "ping" the system at various nodes. You can create a simple Doublet Dirac function (PWL with a couple points for +- approximate impulse) which has no DC component but excites the system to produce a response, but make sure the "ping" doesn't overdrive any portion of the system. You can evaluate the system by looking at the response dynamics and if you understand the system order and relationship between time and frequency domain results, you can quickly evaluate the system stability. This technique came in very handy when looking how things behave when changing system parameters, temperature, signal level and such. For signal level evaluation we would artificially force the active devices bias into regions where they would enter during high signal levels, or use a very low frequency large amplitude signal and superimpose the "ping" on top of this low frequency signal. This technique became so useful we built a dedicated "pinger" to use around the lab. Don't remember the exact details but it had a pot driven variable frequency 555 timer driving a couple TTL gates (yes very long ago) which were configured with a simple RC network to produce the mentioned doublet, and with pin jumpers could make the doublet wider if needed for low frequency systems. Scaling was simply an output pot with a series injection resistor on a probe tip or something to that effect.Anyway, hope this helps.Best,

author: mawyatt
author_rank: Super Contributor
timestamp: March 16, 2021, 08:29:46 pm
content: Here's some examples of using the "Ping" concept mentioned above. This is a simple OP-07 with Gain of 2 (R=20K) with a shunt feedback cap of 0.1uF, Rload is 1K and Cload is 1nF & 10nF. This configuration produces a classic 2nd order system with Cload controlling the excess phase shift, thus directly affecting system damping. Also a good example of how capacitive loads on a typical Op-Amp can cause issues!!The "Ping" is a current source doublet with +-1ma connected to the Op-Amp output and ground (and to the negative Input and ground for another connection point example), also included Bode Plots that show phase margin of 41 degrees and 13 degrees with Cload 1nF and 10nF respectively. Note the classic 2nd order responses, even with the "Ping" injected at the Op-Amp output.Anyway, hope this help illustrate using the "Ping" concept to evaluate closed loop system response. If you have an AWG this doublet waveform could be used as a "Ping" source for low to moderate speed systems.Best,

author: WideBandwidth
author_rank: Contributor
timestamp: March 16, 2021, 10:40:08 pm
content: Quote from: T3sl4co1l on March 15, 2021, 06:54:14 pmWhen you say damping at one/both ends, are you envisioning something like series R and shunt C?Since all the stages combined draw something like 100mA, a 1ohm resistor would drop 0.1V. Seems like that's close to the max resistance I could afford to use on the supply rail. 1uF or so in shunt would give a pole near 100kHz -- seem reasonable?Quote from: mawyatt on March 16, 2021, 03:45:48 pmI think you're referring to tim_'s experiment in SPICE then, not my circuit. And to his credit, he writes, "(Please ignore the bad way of biasing the input)."I recall you mentioning the Kirk effect and others a few weeks back. I didn't see any ill effects with the frequency divider I rigged up, which runs at an even higher current (20mA) than the limiting amps. Hopefully not an issue? Though to be fair, I never actually measured at 300MHz.I recently made an acquisition of a nanoVNA, so I'll actually be able to characterize at least the small signal behavior of the limiting amps. Definitely not comprehensive, but better than nothing.Quote from: mawyatt on March 16, 2021, 03:45:48 pmSounds like you've been wanting to tell someone about this!If a doublet is the derivative of a delta, then the system's response to the doublet would be the derivative of the impulse response. So if our system was near instability, the impulse response would ring near the problematic frequency. The derivative of that ringing is...more ringing. What is the advantage here of the doublet over a simple impulse?Nifty idea though, the pinger -- another addition to the "project to-do list". It sounds like a difficult device to make for high-speed circuits. The additional capacitance of the pinger in-circuit could dramatically affect system stability, I imagine.

author: mawyatt
author_rank: Super Contributor
timestamp: March 17, 2021, 12:56:06 am
content: Quote from: WideBandwidth on March 16, 2021, 10:40:08 pmRegarding your PS decoupling of stages, use a "star" configuration so the series drop is just due to the single stage currents, not the entire amplifier stages current.That was the circuit I was referring to, and yes the mentioned bad biasing.The Kirk effect is easy to see if the data sheet has a measured ft vs collector current curve, without this and a simpler device model it will difficult to tell other than the performance will not be as predicted. We always maintained a peak signal collector current to left of the ft peak under all conditions including chip temperature, and remember just because the device terminals show reasonable voltages at B-E-C, the actual intrinsic device voltages will be different, especially so under high peak currents.Good work regarding the Doublet as the derivative of the Dirac Delta function, or commonly known as the impulse functionFor an analysis standpoint this can show more detail of the transient response, but the real advantage is that this function has zero offset, so it doesn't upset the low frequency integrating responses like an impulse, or even worse a step function. In many systems offsets can introduce a long tail to the response where the low frequency integration must provide feedback correction, and thus constant waveform movement with long tails, the doublet avoids this if properly applied.There are many ways to create a fast doublet, the simplest is just a EOR gate driven with one input slightly delayed (can use a gate delay), or a RS FF with a delay to R, then take the narrow pulse (~impulse) derivative with a RC network. 74AC logic should provide a reasonably fast pulse, other types even faster. The "Pinger" probe should be a approximation to a high impedance or current source to keep from loading the circuit, and can be just a series resistor. The resistor also helps reduce the signal level, but also creates a low pass filter with the circuit capacitance, so some adjustment may be in order to keep the amplitude low enough to not overdrive but high enough to excite the responses.One of my former colleagues worked with Larry Nagle (SPICE author) while at Bell Labs, and I got introduced to Larry at the IEEE ISSCC...what an honor to meet himBest,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 17, 2021, 08:03:46 am
content: Quote from: WideBandwidth on March 16, 2021, 10:40:08 pmSeries R would also be acceptable, from stage to stage (~20mA), but yes would be a bit much after a few. A star topology as mentioned above affords more resistance for less DC per resistor, or inductors can be used for even more attenuation per DC drop.I meant with the power distribution network as a ladder of L and C, the L being at least stray trace inductance (and with regular spacing between bypass caps, this inductance will be fairly equal between them), but explicit inductors can be used as well. In these cases, the network has a lumped equivalent transmission line characteristic, which must be terminated, and an R+C at one or both ends affords that termination. The C needs to be several times the total bypass capacitance, so that it acts as an effective coupling capacitor for any signals that might be bouncing around the network, and the R terminates those signals.Note that if you have bulk capacitance with ESR << Zo at one end, that end is effectively shorted, and R+C in parallel will have no effect. In this case, the damping must go at the opposite end. This situation often appears with switching converters, where a local bulk cap needs low ESR to handle the switching ripple. Alternately, the converter's source impedance can be effectively increased, by placing a R||L in series with it (with R = Zo and L = Zo^2 * C); but this is kind of wasteful, there are better places we could use an inductor. Or use a relatively large series inductor, so that AC voltage can be developed across it (also affording more filtering between the converter and subsequent chain of bypass caps and inductances), and place the shunt R+C there.A similar situation arises in star configurations, where the N-1 chains act in parallel against each respective remaining chain; the star node is a very low impedance, and a shunt R+C is ineffective there.PDN analysis shouldn't be too big of a deal here, as it's easy to get Fo and Zo much lower than the critical frequency range you're likely up against (i.e., within a decade or two of F(-3dB)). This analysis does give you some idea of what a good minimum L and C should be, and which direction to adjust values to improve things (i.e., more C, less L to lower Zo).Note that, at high frequencies, the network approximates either an inductor divider ladder (shunted by bypass caps' ESL and trace/via inductance, versus series trace inductance between caps, or inductors proper if used), or a transmission line network (since it's ultimately all microstrip or whatever); the latter shouldn't be relevant until low GHz, so the former should be the correct equivalent model near fT.Tim

author: mawyatt
author_rank: Super Contributor
timestamp: March 17, 2021, 01:47:20 pm
content: Quote from: WideBandwidth on March 16, 2021, 10:40:08 pmActually I had totally forgot about this "Pinger" concept, likely because few would spend the time to understand & appreciate it since this does involve some deeper understanding of closed loop and open loop system performance, the math and details behind this. Only recalled because of your interest in the Cherry-Hooper amp, which is somewhat difficult to understand with the inner and outer loops and how they interact. So considered this as a method to evaluate the effects of bias & device sizes without breaking the loop. Refreshing to recall this and find someone actually interestedBTW if you have a chance to try the Caprio cell with the CH amp, you will get a real surprise in the performance (linearity) even with discrete lower frequency devices. Once that is under your belt then take the top device differential collectors and pass thru a differential transistor current commutator (think Gilbert Mixer) to a BALUN for an active mixer with amazing TOI performance. This was a trade secret long ago, but Ok to divulge now (patent app rights long since expired), and was done with 350GHz SiGe (IBM 9HP) and 600GHz InPAnyway, have fun with these CH circuits, there are a few more that you might like but don't want to deviate from your thread.Best,

author: WideBandwidth
author_rank: Contributor
timestamp: March 21, 2021, 05:30:53 am
content: Another update!I updated the decoupling network for the limiter circuit using the above advice. Each amplifier stage is powered off its own -5V trace which all connect to a single point near the -5V input. Decoupling is achieved via a Pi RC network. I've put two in parallel on each side of the R just to have an extra set of pads, but I'll probably eschew the extra parallel capacitors.I've also put together a layout for the board, if you take a look at the attachments. I would definitely appreciate any comments!Quote from: mawyatt on March 17, 2021, 12:56:06 amI suppose one could also feed a sharp step through a couple differentiators instead of trying to approximate a Dirac delta through digital logic?And to approximate a current source, I was just envisioning using the collector of a transistor as the output. I guess a transistor tends to have a lower bandwidth than just a resistor though.Quote from: mawyatt on March 17, 2021, 01:47:20 pmI do recall reading about Caprio's quad in the AoE X Chapters where the authors, like you allude to, demonstrate an amazingly linear differential amplifier. I tried acquiring Caprio's original paper, but it looks like it's behind a paywall that not even my university can get past!Got any numbers you can share on what TOI you achieved and at what bandwidth? Must be fun working with transistors with transition frequencies three orders of magnitude higher than the MMBTH10. What sort of mixer conversion gain bandwidths could you achieve with 600GHz fT?Quote from: mawyatt on March 17, 2021, 01:47:20 pmNo, no, please keep them coming!Quote from: T3sl4co1l on March 17, 2021, 08:03:46 amVery interesting, I never really thought about the shunt capacitors along the DC bias in terms of transmission line theory. But yes, it definitely makes sense that adding the shunt caps along with the inherent trace inductance basically creates a periodic (or aperiodic as the case may be) structure transmission line. So making the shunt capacitance large makes the transmission line impedance Z0=sqrt(L/C) small -- closer to a short, assuming there is an appropriate load on the transmission line and the line is of proper length.So when you say one/both sides of the bias network should be terminated in the transmission line's impedance, the tricky part is determining the impedance. Supposing my trace was x mils long, it would have an effective inductance of say 1nH. Let's say I have a 1nF capacitor near my amplifier for decoupling. I don't quite have a transmission line, since I only have a single capacitor. But could I estimate a line impedance of Z0=sqrt(L/C)=1 ohm here and stick a 1 ohm resistor after my 1nF capacitor? Then the other side of that resistor would have a much large capacitor to act as a proper short?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 21, 2021, 02:25:22 pm
content: Quote from: WideBandwidth on March 21, 2021, 05:30:53 amRight, and if that structure isn't terminated into a resistance comparable to Zo, it will have an impedance peak (resonance) of Q times Zo -- not extreme with type 2 ceramic caps, but still, an increase of 10-20x is quite unwelcome if unexpected!The single LC unit approximates a parallel resonant tank at the load (C) end, and series resonant at the feed (trace) end.QuoteThe figure is in the ballpark of 1 nH/mm. The constant mu_0 is 1.257 nH/mm, the inductivity of free space -- it is reduced by geometry factors, hence trace impedances are typically lower than 377Ω, the impedance of free space. Likewise the capacitance is higher than e_0 (8.84pF/m), by a geometry factorand the dielectric constant.We can calculate the exact figure, given physical constants, impedance and dielectric constant. For FR-4 microstrip, e_r ~ 2, and say Zo = 100Ω, then Lo = 100Ω * sqrt(2) / c, where c is the speed of light. The units are ohm*s/m == H/m so we have the inductivity. For e_r = 1 we have 100/3e8 = 0.33 uH/m, or nH/mm. For e_r = 2, that goes up to about 0.5. 1 nH/mm is a pretty safe overestimate, including narrower traces or the length of components (especially THT parts, which have more height off the ground plane).So, if that route is about 30mm long (note 1 mil == 0.0254 mm), and about 100 ohms, say it's 15nH. Say it's got 0.1uF at the load end, where it will behave parallel resonant (and series resonant at the source end). That's 0.39 ohms Zo, and say it's got a Q of 20, we'd expect an impedance peak to 7.7 ohms (compared to circuit impedances of 50 ohms, this is looking pretty significant) at about 4.1MHz.The actual figure will be higher, because the source is not an ideal short, but itself composed of some bypass caps. Since the left branch is much longer than the middle and right (which are about the same length), we can approximate the two as being in parallel, so say they both have 0.1uF; and, assuming for a moment the source is worst case (C13 and C14 = 0, and a long power cable), then the total loop for the left branch resonance has that 0.2uF in series with its 0.1, so the total equivalent is 0.067uF and the frequency is 5.0MHz. Or maybe a bit lower, because we should account for the extra, whatever, 5nH or so going to C11/C17Regarding the layout -- probably this doesn't make much difference, this may be fast, but it's not stupid fast;- I don't like power routed under the input (L1/C6), nor the long sweeping trace (to R7, C7).- The super thin trace (Q1-B) can be avoided I think by flipping it around and placing it above Q2?- And the jumper is "how you doin" (Q2-B to Q5-B), though I'm not sure there's a solution to that, it looks pretty well stuck.- Speaking of CCS stuff, I wonder if Ccb from Q2 to Q5 has any effect; possibly it could be used to peak the CCS response, seeing as one into the other has a positive CM feedback loop. Kinda another reason I prefer the two-diode-stack with bypass, the bypass swamps Miller effect. (I'm not sure that this would have much if any effect, but it's worth simulating I suppose. Also, CCS go well with ferrite beads in the collectors, that can help relax routing and placement density, without compromising on balance. Simulate this as well -- a poorly chosen FB can end up resonating with collector capacitance and you get a zero (series resonance) in its output impedance.)- I think taking advantage of the symmetry of the diff stage, would be fruitful. This is already pretty close, or is already one axis of symmetry, perhaps -- Q3-Q9 look to be placed pretty symmetrically. There may be other orientations that are better balanced, and don't be afraid to expand distances between components, as long as trace lengths stay short, and most of all balanced.Remember, any imbalance here, is imbalanced capacitance on one or another node of the amp -- a place for CMRR to degrade, and for feedback to come in.Anyway, I know it's difficult with the asymmetrical footprint, you can't just swap B and E unfortunately. So, I'm not saying I know there's a better arrangement out there -- I would have to play around with it for some time, and see what I can find. Maybe you've already taken the time to do this, so this advice is redundant; I can't tell, looking at just the one version of course.- I also don't like the long traces between stages. Not sure that is actually a problem; it doesn't feel right on the emitter follower, but maybe it's a reasonably resistive output impedance anyway, so the line is well terminated (even if it's not long enough to be resonant within the passband). I wonder if there might be an arrangement with Q3, Q4 bases to the left, and Q6, Q9 emitters to the right, so they can be chained seamlessly. Possibly the biasing would have to be off to the side, which maybe isn't great for balance, or for avoiding bottom side jumper traces. Would be nice for biasing to be in the middle, but that kind of precludes getting the two phases close together---well, there isn't anything shared between them, is there, just the emitters right? There's no cross feedback or anything here. So maybe Q3+Q4 and Q7+Q8 can be paired more closely, and with either a local FB, or Q2/Q5 collector, directly to their emitters (whichever fits)? And then the Q6+Q9+R12-R15 part can stack outward from center, or lengthwise along the symmetry axis, whichever works best.Again, not sure, just thinking out loud!Tim

author: mawyatt
author_rank: Super Contributor
timestamp: March 21, 2021, 04:23:48 pm
content: WideBandwidth,Don't use a transistor for the Doublet output, a single resistor or series RC is all that's required, and make the RC time constant longer than the Doublet period so the Double couples thru.Your university should have IEEE access, think this will allow access to Caprio's original paper (I don't have the file tho). The only mixer number I recall from long ago were TOI of almost +50dBm at many many GHz, can't remember the gain either, probably 10~20dB. BTW active mixers can not produce noise results of passive mixers, sure you can buffer the mixer with an LNA, but the mixer is still the major noise source. If you study noise theory, then with an active mixer like the Gilbert commutates a bias current, this alone pushes the noise well up and limits performance. Recall active mixers NF of >10dB.You mentioned interest in "other" circuits, Google Gilberts Micromixer and note the details about the "unlimited dynamic range" assuming a transistor can be found to handle the current!! Also a very subtle comment about the theoretical limits of amplifier linearity related to modulating the amplifier input impedance by the signal itself!! The initial overall amplifier non-linearity begins at the amplifiers inputWe've designed many versions of the Micromixer since the 1st internal paper, with various processes and those mentioned, they worked very well.Regarding mixers, and since you are interested in "other" circuits, check out the PolyPhase Mixer or PPM as we've called them (also called N-Path). Check over athttps://www.eevblog.com/forum/rf-microwave/polyphase-or-n-path-mixer/Be sure to read the entire thread, and the references (Cornell Andrews & Molnar as a minimum), and prior thread on quartz filters to get a "feel" for this circuit. After the initial public disclosure by Andrews and Molnar at the IEEE ISSCC in 2009 it quickly spread to most major research institutions, soon after DARPA created a workshop around this (we presented), today it's likely in some advanced SDRs and Apples Products (Apple acquire Dr Andrews firm "passiff" a year after she got her PhD). This passive mixer has achieved sub 2dB measured noise figures by many (not in error!!), which defies fundamental mixer physics limits of 2/pi or 3.92dB, maybe time to rewrite the text books on mixers!!! The PPM is probably beyond the scope for this site (research topic), but since you are a student maybe something of interest. Beware this is deceptively simple looking, but incredibly complex and requires a deep dive and much study to appreciate what's actually going on, also requires a good understating of discrete time continuous amplitude signal processing and the frequency domain inter-relationships of such. Great topic for advanced graduate and post doctoral study for those truly interested.There's much more, but don't want to deviate your thread too much.Best,

author: WideBandwidth
author_rank: Contributor
timestamp: May 16, 2021, 07:33:14 am
content: I have once again found some time to work on this project.First of all, thanks again for the latest suggestions, Tim and Mike!I put an order in for the limiting amplifier board and built it up. Pictures attached.The first thing I noticed was that if the input amplitude became too large, the output would go all screwy. And by screwy, I mean the intended square-ish looking signal collapsed in on itself. After some investigation, I found out that the two input amplifiers to each amplifier stage were being driven into saturation. Why? I didn't bother matching any of the transistors in each diff pair, so the CMMR of these amplifiers isn't too hot. The emitter node of the diff pairs reaches a couple hundred mVpp of ripple which was clearly enough to drive those transistors into saturation. The problem gets worse (i.e. occurs at lower input amplitudes) as frequency increases, I imagine because the output impedance of the tail current sinks falls off which further decreases the CMMR.The solution to this involved sticking a parallel diode and bypass capacitor in series with the outputs of each amplifier stage. That just adds an additional diode drop to the base of the input transistors, giving an extra diode drop of margin before the transistors can enter saturation. You'll notice the bodge diodes and capacitors in the image...With my limited measurement equipment (20MHz function gen and 70MHz scope), I did some testing.First, I measured the differential output using two x10 probes (so no proper terminations anywhere). See "Differential Output.png". With a 0.5Vpp 1MHz input, the output looks pretty darn square. Even going down to 30mVpp input, the output is square-ish, though you'll note that the duty cycle starts deviating from 50%. I imagine this is due to differential pair mismatch and biasing mismatch. If I put in the time to match all the transistors, I'm assuming this problem will go away. And I'm not sure it's even a big problem, since all I really care is that the signal is square-ish and the amplitude is fairly constant -- which it is at 1Vpp.At 20MHz, the story is fairly similar. I'm measuring 4.1ns rise times even at 30mVpp input. It's likely even lower than that, since my oscilloscope only has a 70MHz bandwidth. These measurements were performed without any proper terminations at the oscilloscope, so the ringing is to be expected.I then put together one of those passive x10 50 Ohm probes, the one where you take a coax cable, solder a ~450 Ohm resistor onto the center conductor, and terminate the scope end in 50 Ohms. Probing one side of the differential outputs yields the scope plots in "Single Ended 50 Ohm Output.png". Note that the ringing in the 20MHz measurement is significantly attenuated. Otherwise, the takeaways are the same.The return loss at the input isn't spectacular. The design in ADS was getting >20dB from the lower cutoff frequency up to 300MHz. In reality, I'm getting roughly 14dB at 300MHz measured on a nanoVNA. Though considering the matching network inductor I used was just 3 turns around the first thin cylindrical object I could find, I'd say that's not too shabby. I'm sure with some more tuning, I could get it down even farther. The impedance at 300MHz looks significantly capacitive, so I imagine an extra turn of the inductor could do the trick.The other thing I'll note is that if I zoom into the rising or falling edge of the output, I see a pretty significant amount of noise near the middle of the edge. Since that's where the amplifier has maximum gain, I believe that noise is just input noise being amplified by the ~60dB of the total amplifier. Hopefully adding some shielding (and using better coax cables...mine are cheapies with paper-thin outer shields) will solve this particular issue.Well, this amplifier looks like it's working well, at least up to the limits of my measurement equipment. The next step is to work on the frequency divider chain. I believe I have the divider topology worked out (both for the high frequency ECL dividers as well as the lower frequency dividers). It's now only a matter of laying everything out onto a board.

author: WideBandwidth
author_rank: Contributor
timestamp: June 06, 2021, 12:29:07 am
content: Small update: I got my hands on a 400 MHz Tek 2465B. I'm measuring the rise time of the limiting amplifier to somewhere in the neighborhood of 1.2ns (with 300mVpp 20 MHz sine wave input). Since the 2465B has a rise time itself of 0.875ns, I'm calculating the amplifier rise time at around 0.82ns. Not too shabby with MMBTH10s, and it seems like the amplifier should function at 300 MHz as designed.