EEVblog #859 - Bypass Capacitor Tutorial - Page 1
Forum section: electronics / general

author: EEVblog
author_rank: Unknown
timestamp: March 10, 2016, 11:10:57 pm
content: Everything you need to know about bypass capacitors.How do they work?Why use them at all?Why put multiple ones in parallel?What effect does package type have on performance?Are there any traps?Dave measures some bypass capacitors with an impedance analyser to confirm the whiteboard theory and shows the complexities involved.Reverse geometry packages:https://product.tdk.com/info/en/catalog/datasheets/mlcc_commercial_lwreverse_en.pdfLow inductance chip capacitors:http://media.digikey.com/pdf/Data%20Sheets/AVX%20PDFs/LICC.pdf

author: dentaku
author_rank: Frequent Contributor
timestamp: March 10, 2016, 11:58:39 pm
content: Now there's a video Elecia White should be interested in watching. She's mentioned the mystery of bypass capacitors many times on embedded.fm.

author: apis
author_rank: Super Contributor
timestamp: March 11, 2016, 12:21:03 am
content: Nice to see reality as well as whiteboard.

author: papo
author_rank: Regular Contributor
timestamp: March 11, 2016, 12:26:54 am
content: Hum did Dave goof up the formula for C_IMP? This doesn't look quite right...

author: ROBOT
author_rank: Contributor
timestamp: March 11, 2016, 01:01:49 am
content: So if I know the noise on my power supply is say 20kHz how would I go about choosing a bypass capacitor value?

author: c4757p
author_rank: Super Contributor
timestamp: March 11, 2016, 01:22:09 am
content: Quote from: papo on March 11, 2016, 12:26:54 amYes, he did. Summing the real reactances doesn't work, they have to be complex impedances... He also mixed up terms for impedance, reactance, and resistance all over the shop...

author: EEVblog
author_rank: Unknown
timestamp: March 11, 2016, 01:50:13 am
content: Quote from: c4757p on March 11, 2016, 01:22:09 amI deliberately didn't want to get into the complexities of all the detail of that so I simplified it.I think I even mentioned it was a gross simplification at some point.Start introducing complex numbers into the explanation of this and you immediately start losing your audience.

author: leafi
author_rank: Regular Contributor
timestamp: March 11, 2016, 01:59:56 am
content: I have a question, if all of these capacitors have the same ESL 1nf, 10nf, 100nf 0402 and all are the same dielectric would a better bypass arrangement occur from having one of each or use 3 100nf caps in parallel. Basically when I look at kemet spice or TDK seat the ESL and ESR of the caps are pretty much the same for different values for some of them. Personally I would think if they all have lets say 1nH of inductance each that the XL reactance curve should all go up on the right in the same line. (minus Q related artifacts).

author: c4757p
author_rank: Super Contributor
timestamp: March 11, 2016, 02:01:55 am
content: Dave, with all due respect - if you wanted to simplify it, then I don't think you should have given the equation at all. That equation isn't simplified, it'swrong. It doesn'tworkwith real numbers. You could have explained the topic without giving people equations (which they are now going to remember and try to use at some point) that don't work.

author: uncle_bob
author_rank: Unknown
timestamp: March 11, 2016, 02:03:28 am
content: Quote from: ROBOT on March 11, 2016, 01:01:49 amHiWithout knowing a *lot* more than the frequency, picking a cap (or a bank of caps) is a bit premature.1) Is the noise a sine wave tone or a square wave ripple? Different approach for each of those.2) Is the noise broadband with a peak peak at 20 KHz? again a special case3) Is the noise from the load rather than the supply? Again a different set of things to look at.4) Is this some sort of massive supply current wise? (I have a 100A adjustable sitting over there .. some day I'm *sure* it will move it's self. I certainly am not picking it up ..).5) Is this some sort of very high voltage supply? (another bunch of odd caps to pick between)That's just the here and there questions. You will eventually get to:1) What is the output impedance of the supply at 20 KHz?2) How much noise do you have?3) How much noise do you want?If the supply has a 0.01 ohm output impedance and 100 whatever units of noise. You want 1 whatever unit of noise. Your cap needs to be 0.0001 ohms at 20 KHz. If you start with caps that have a 0.01 ohm ESR, you will need at least 100 of them in parallel. Since we have a hundred of them, they each will need to have a reactance of <0.01 ohms at 20 KHz. A thousand microfarads looks like a good bet.Yes those are bogus numbers. No they don't apply directly to *your* supply. You need the numbers for your device. It does illustrate that tossing caps at the problem *can* have it's downside. Even if you go to 0.1 ohms Zo, you still have a hundred caps with a pretty low ESR.Depending on your answers to all the goofy questions in the first part, your supply may not *have* a well defined output impedance or it's noise may come from a stability issue. Your giant cap bank *might* make things worse.Bob

author: EEVblog
author_rank: Unknown
timestamp: March 11, 2016, 02:04:54 am
content: Quote from: c4757p on March 11, 2016, 02:01:55 amYeah, fine, you won't get much argument from me. Maybe I shouldn't have, but meh.

author: ornea
author_rank: Unknown
timestamp: March 11, 2016, 02:30:22 am
content: I have always been curious as to why they did not put power pins close to each other to reduce the pcb trace length to the caps.I guess a tradeoff between making it easier to run power rails and longer traces like I see on old arcade pcbs.But still ...

author: c4757p
author_rank: Super Contributor
timestamp: March 11, 2016, 02:54:57 am
content: Power pins are distributed around the chip so they can deliver power to different areas of the internal circuit. Somewhat unavoidable. Many modern chips put the pins in nice power/ground pairs, which makes it much easier to place decoupling capacitors, and also reduces the effective inductance by way of mutual inductance between the two. That's about as good as you can get, I think.As for the placement of power pins on things like 7400 series that you'd see on old arcade PCBs - I have no bloody clue. The arrangement of power and ground on pins N and N/2 that 7400 series use seems really silly to me, I'd think using pins 1 and N would be much nicer.

author: EEVblog
author_rank: Unknown
timestamp: March 11, 2016, 03:15:07 am
content: Quote from: ornea on March 11, 2016, 02:30:22 amThat's quite common these days in modern chips, power pins are often side-by-side.But it's all a trade-off with the requirements for the die.

author: EEVblog
author_rank: Unknown
timestamp: March 11, 2016, 03:18:54 am
content: Quote from: c4757p on March 11, 2016, 02:54:57 amA lot of it might come from convention. And it was actually beneficial to have power pins on separate sides of the package back in the day's of designs all having hundreds of chips, you'd just run +/- routing strip down the centre of all the chips, with decoupling straddling that. Made double sided designs possible. You could also chose to have the power rails running across the top and bottom of your line of chips, it was a pretty flexible arrangement from a layout point of view.

author: orolo
author_rank: Frequent Contributor
timestamp: March 11, 2016, 03:40:10 am
content: It's very nice that you pointed out the problem of resonance between caps in the video: I was waiting for that from the beginning, and the experimental results were adequately horrific (as in 26:52, decouple with three caps and make it worse.) Since my beginnings as RF homebrew aficionado I've been reading about never decoupling with different cap values, unless you really know what you are doing, and instead parallel similar caps. I've even read about people demanding from manufacturers high ESR caps, or trying to spoil the resonances with series resistors. It's a very complex matter, and I think many people derive a false sense of security from these widely different decoupling caps.

author: EEVblog
author_rank: Unknown
timestamp: March 11, 2016, 03:54:11 am
content: Quote from: orolo on March 11, 2016, 03:40:10 amI've seen series resistors added. You must be pretty desperate to have to do that.

author: Brumby
author_rank: Unknown
timestamp: March 11, 2016, 03:56:59 am
content: Quote from: EEVblog on March 11, 2016, 02:04:54 amI must admit I did wince a little at the simplified math - but it does not take away from the principle being presented. I rationalised the expressions as beingrepresentativeof complex numbers and I had no problem with it. Besides, Dave has the overlay that states this simplification and the reasoning for it and, quite rightly declares: "The point is there is a total impedance that includes ESR, Xc and ESL."I do understand how there will be some who will be rather irritated by this, but clinically correct mathematics is not essential to the understanding of the fundamentals.

author: AustinTxBob
author_rank: Contributor
timestamp: March 11, 2016, 05:31:26 am
content: I really enjoyed that video and it fits in well with the AC class I am taking right now.So lets say I built a circuit. How would I see that I needed bypass caps and how would I determine the sizes and how many. I guess look for the ringing you mentioned? Then add caps until that was minimized?

author: strangersound
author_rank: Regular Contributor
timestamp: March 11, 2016, 05:47:46 am
content: Excellent class, Dave! Love the fundamentals series videos. Will definitely be reading the follow up exchanges here as well.

author: ElektronikLabor
author_rank: Regular Contributor
timestamp: March 11, 2016, 07:30:10 am
content: At work I useKemet Spiceto calculate the bypass capacitors:ec.kemet.com/toolsThey also got an web based version:ksim.kemet.com/Drawback: This simulator only KEMET offers capacitors

author: GK
author_rank: Super Contributor
timestamp: March 11, 2016, 08:30:23 am
content: I used to have a databook for a modified-package version of the high-speed (pretty sure) 74AC family. The pin count for each package was increased by 2 for an additional pair of VCC and GND pins. The power pins were placed in the middle with the pins of each pair (VCC, GND) directly adjacent, so that a parallel-pair power buss could be run right through the middle of the package, facilitating better high-speed layout/more effective supply-rail bypassing (ie a 14-pin DIP became a 16-pin DIP with pins 4 & 13 = VCC and pins 5 & 12 = GND).I couldn't find anyone at the time that sold these in small quantities. This was around about 1998-2000, about the time part of Motorola morphed into ON-semiconductor. I think it might have been a Motorola databook and initiative. That's about all I remember, besides the fact that the databook exclusively used that horrible revised IEEE logic symbol standard that no one seems to have adopted. I will never draw an (N)AND gate as a square box with an ampersand logogram in the middle!

author: tggzzz
author_rank: Super Contributor
timestamp: March 11, 2016, 08:54:13 am
content: Quote from: c4757p on March 11, 2016, 02:54:57 am74, 74LS, 74F series had well-controlled, relatively slow edge rates so that the inductance in the corner wires wasn't a major problem. Other 74 series with faster edge rates were more problematic, especially bus buffers w.r.t. ground bounce.Eventually packages got smaller, the problems got worse, and backward compatibility became untenable/unnecessary, and power pins moved somewhere sensible.

author: HAL-42b
author_rank: Frequent Contributor
timestamp: March 11, 2016, 12:08:11 pm
content: Can't we do something like a distributed capacitor? Supposedly a distributed capacitor may result in wideband operation.

author: bktemp
author_rank: Super Contributor
timestamp: March 11, 2016, 01:09:59 pm
content: Quote from: HAL-42b on March 11, 2016, 12:08:11 pmThat's the pupose of a ground+power plane on a multilayer board. A large power plane has a low inductivity and acts as a small capacitor. That simplifies decoupling capacitor requirements a little bit.Decoupling capacitors are an interesting topic. For examples FPGAs. I have read application notes about decoupling, but it is impossible to do on cheap 2 or 4 layer boards without burried vias and other expensive stuff you can't afford unless you make thousands of boards because you need the top layer for routing all the signals.I have compared many FPGA board from all kind of equipment (medical image processing, communication equipment) and the decoupling on all boards was much worse than the requirements from the FPGA manufacturer's application notes. One example is a board with a Virtex II FPGA and 8 DDR RAMs that has almost no decoupling capacitors except some larger ones. They are probably relying on the power planes for all the high frequency decoupling and only have some larger capacitors for bulk decoupling.

author: ConKbot
author_rank: Super Contributor
timestamp: March 11, 2016, 02:01:40 pm
content: Quote from: HAL-42b on March 11, 2016, 12:08:11 pmAs bktemp said, thats what power and ground planes are for, and you can get high dielectric constant(Dk) PCB substrates targeted at power planes, ie 1-2 mil thick to keep the planes close, not as well behaved or stringent characteristics as RF high Dk materials, but good enough for decoupling. Its also sort of whats going on in effect when you have a small grid of decoupling caps opposite of an FPGA or other large BGA device.Also mentioned was series resistors, which will stop resonances, but they also "De-Q" the capacitor, so it will be mediocre in a broader band of frequencies rather than really good at a narrow range. Parallel enough to get the total impedance down, and you have a broadband decoupling network. But as Dave said, that's a desperate solution.Ive seen arguments for and against using multiple value decoupling caps (resonances and whatnot) However one thing which most definitely benefits from multiple values is SMPS output filtering. While it seems like decoupling since its a bunch of caps from VCC to GND, your goal is to filter the output ripple. Ive had good luck on a ~2 MHz SMPS with using the TDK component characteristic viewer to select caps with their impedance minimum right on the odd harmonics of SMPS switching frequency. <20 miliohms between the 1st and 11th harmonics, only 3 cap values, and it wasnt 1u, 100n, 10nI wanted to try X2Y caps, but Johansens information about each specific cap is rather lacking, so I ended up going with 0306 caps for a low inductance option.

author: nctnico
author_rank: Super Contributor
timestamp: March 11, 2016, 02:27:05 pm
content: Quote from: EEVblog on March 11, 2016, 03:54:11 amNot really. Some LDOs like the LM1117 are designed for tantalum decoupling caps but since I hate to use tantalums for various reasons I always use a 0.47 Ohm resistor + 10uf MLCC otherwise the LM1117 will sing like a bird. If the board doesn't have a power plane I simply put the 10uf a few centimeters away from the LM1117 through a thin trace.Quote from: bktemp on March 11, 2016, 01:09:59 pmActually you can achieve a lot with a double sided board and an FPGA in a QFP package as long as the bottom layer isn't cut up too much so it can act as a ground plane. The power supplies can be routed as rings on the top layer under the FPGA and connected through links on the bottom layer. This way the decoupling capacitors can be on the top layer and provide excellent decoupling.QuoteI agree but those application notes usually assume different power supplies for various nets. If you minimise the number of different power nets and use a clever arrangement with power layers on a 4 or 6 layer board you can get away with much less decoupling and have all components on one side. I didn't watch the video so I don't know whether Dave has brought it up already: there can be huge difference between capacitors with the same base specifications. For example: '10uf 16V X5R size 0603' still says absolutely nothing about the characteristic of a capacitor. One type of X5R capacitors can have more or less voltage dependant change in capacity so it is absolutely necessary to check the datasheet if the capacitance needs to be a guaranteed minimum at a certain voltage.

author: tszaboo
author_rank: Super Contributor
timestamp: March 11, 2016, 03:33:59 pm
content: Quote from: medvedev on March 11, 2016, 07:30:10 amAnother, equally useful program is the TDK SEAT. It plots all the curves you want to ever know of any given TDK capacitor.Quote from: EEVblog on March 11, 2016, 03:54:11 amNot really. Linear regulators dont like low ESR, or some voltage reference noise reduction pins dont like low ESR. slyt339 from TI for example explains this.Quote from: HAL-42b on March 11, 2016, 12:08:11 pmIt is called 4+ layer PCB with GND an power plane. Works up to very high frequency, but capacitance is small. So you need the 10n, 100n. The bigger value 0402 and 0201 capacitors are becoming better at this also.I guess someone can make a triangle shaped capacitor...

author: c4757p
author_rank: Super Contributor
timestamp: March 11, 2016, 03:40:54 pm
content: Quote from: NANDBlog on March 11, 2016, 03:33:59 pmAgreed, decidedly not desperate. I've done it quite a lot when I wanted something in the form factor of a MLCC but with high DF. That's not abadthing, it's something that's quite often desirable. Hence why we even have a name for it in certain applications: "snubber"I usually try to put at least one chunky, lossy capacitor on every rail, it can go a long way to damp resonances.

author: apis
author_rank: Super Contributor
timestamp: March 11, 2016, 04:28:54 pm
content: What I find a bit discouraging though: what do you do if you don't have access to a network analyser, etc, so you can verify it actually works, and not only according to theory. Don't wan't to connect a resonator to the bus. Are your only option trial and error, prayer and faith in the datasheets?

author: kcozens
author_rank: Contributor
timestamp: March 11, 2016, 05:42:39 pm
content: When I received the email message about this video on Thursday I thought it was a topic for Fundamental Fridays. It turns it was. Darn timezones.Useful information, Dave. One thought that I had about the video is whether you would have seen any differences in the response curves if you had changed the order of the bypass caps. If some of the bypass caps can't be placed that close to an IC should I wonder how much, if any, difference it makes if you have the smaller value capacitors are closer to, or further away, from the IC.

author: German_EE
author_rank: Super Contributor
timestamp: March 11, 2016, 06:36:36 pm
content: One other thing that can be fun to try if you have a network analyzer is what happens when you use a solderless breadboard. A 50 ohm resistor placed across the test terminals will have a flat response, the same resistor at the end of 15cm of breadboard looks crazy.Nice video though.

author: Mr Simpleton
author_rank: Unknown
timestamp: March 11, 2016, 07:26:30 pm
content: Some say , parallelling caps of different value may worsen the thing...http://www.cypress.com/file/135716/download

author: MobileWill
author_rank: Regular Contributor
timestamp: March 11, 2016, 08:32:23 pm
content: Great video. Just in time for a STM32 project I am currently in the middle of designing. This video really helped clear things up.

author: Someone
author_rank: Super Contributor
timestamp: March 11, 2016, 09:01:22 pm
content: Quote from: apis on March 11, 2016, 04:28:54 pmTrial and error might be part of it, you can usually measure the first few harmonics of your system with an oscilloscope and with a long FFT window any problematic peaking will show up. Then try some combinations until you get the noise down to an acceptable level.

author: The Electrician
author_rank: Frequent Contributor
timestamp: March 11, 2016, 09:52:18 pm
content: Dave, can the Red Pitaya sweeps be shown with a logarithmic vertical scale rather than linear? That way the sweeps would look more like manufacturer's data for capacitor resonance.I showed this sort of thing at lower frequencies, but the results of interaction between mulitple capacitors is the same.It's shown in reply #9, #11 and #12 in this thread:https://www.eevblog.com/forum/projects/capacitor-measurements-on-an-impedance-analyzer/

author: Carrington
author_rank: Super Contributor
timestamp: March 11, 2016, 10:21:14 pm
content: This stuff can be quite complex.Sometimes I used this calculator, just as reference.http://www.ultracad.com/esr_calc.htm

author: c4757p
author_rank: Super Contributor
timestamp: March 11, 2016, 10:22:17 pm
content: Quote from: Carrington on March 11, 2016, 10:21:14 pmThis one gets one or two brownie points.

author: Carrington
author_rank: Super Contributor
timestamp: March 11, 2016, 11:00:12 pm
content: Quote from: c4757p on March 11, 2016, 10:22:17 pmWell, I think that isn't necessary to be an expert in the field, to know that, right?Guy! I had to use the "www.urbandictionary.com" to know what the hell is a "brownie points".Edit: Sorry, my English is not perfect, I had to edit it.

author: uncle_bob
author_rank: Unknown
timestamp: March 12, 2016, 01:01:18 am
content: Quote from: HAL-42b on March 11, 2016, 12:08:11 pmHiRunning through the answers the whole issue of planes has sort of been talked around, but not directly addressed:In a modern board, you can build a pair of planes with spacing in the 3 mil (call it 0.07 mm) range. The impedance of this plane (with normal materials) is quite low. Right up to the point that your current spike bounces off the edge of the board and returns to origin, they provide a very low impedance voltage source. Microwave layout rules can be used to make this true to quite high frequencies.If you then "distribute" your bypass caps all around this same plane, they can start to source current while things are bouncing back and forth. How it all works out in the end? Welcome to EM modeling ...Before you dash off ... The planes need to be pretty tight to get the impedance down. 40 mill / 1 mm spacing .. not a good thing. Your plated through hole inductance also matters. A 60 mill (1.5 mm) hole is an open circuit. A 2 or 3 mil hole (0.05 to 0.07 mm) hole is "useful". No this probably isn't what your $10 for 5 boards outfit is running as their standard process.Bob

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 12, 2016, 05:41:01 am
content: Errata:@13:40 ish: the scales are log-log in that type of curve, so, it doesn't go to DC and infinity.@18:10 ish he kicks; 18:45 misses the field goal.The 'sum' curvenecessarily must rise above the constituent curves, where they intersect.This is a real effect (central to the thesis), and cannot be ignored, whether invoking complex numbers or not!@ anywhere: although trace inductance is mentioned (so this point is fair game!), the inductance between caps, and from caps to the device pin, is not mentioned.Here's an example of the correct sum:I'm using pulled-out-of-my-ass numbers here, but they're approximately representative. The ESL is approximately proportional to geometry scale, typical for 1206, 0805 and 0603 or the like. The ESR is a typical guess; do look up the real values if you're going to do this. (Somewhat more accurate SPICE models are given by the usual database programs -- TDK SEAT and Kemet SPICE, and I think others have similar; but beware these produce fixed-frequency models, so you need to pick a representative frequency as a starting point. YMMV.)The impedance plot is:As you can see, the two peaks are prominent, over 0.3 ohm: greater than even the ESR of the smallest cap, and worse than a single ESL of 8.5nH. Even though, naively looking at the topology, there should be somewhat less than 4nH because of parallel combination.But in the real world, we cannot place capacitors in precisely the same place! There must be inductance between them as well. Trace lengths, as well as component body lengths and via lengths, count against both the capacitors' ESL, and introduce inductances between them.(Vias aren't relevant in the demonstrated example, with parallel strips on the same layer -- but they are relevant to most PCBs, where SMT pins are routed and bypassed on an outer layer, and ground is on an inner or opposite layer.)This looks like:Note I rearranged the source, and added another capacitor on the left side. The larger inductance represents a couple inches of trace length, and the higher ESR and C represent a bulk capacitor, like the bypass on a linear regulator for instance. The voltage source is serving as a probe, where the device pin would be, so we measure the impedance into that location only. (The plot computes V(V1) / I(V1), the impedance seen by V1.)Note also that ground is assumed ideal,which isn't the case, but a ground plane is close enough to ideal so I won't bother taking the time. Anyway, accounting for that (or, if your board is actually routed that way, as Ye Logic Boardes Of Olde, with VCC+GND routed beneath the rows of ICs), just adds more series inductance between parts, so it's not topologically important. (It does, however, introduce common mode inductance, which means you get ground bounce between ICs. All kinds of messy!)The impedance plot,is much higher (notice the scale change!), peaking around 2 ohms before running away again in the high frequency limit.Notice how it's flattening out at low frequencies. It plateaus to, you guessed it: about 1 ohm there. (At still lower frequencies, it rises again, but only because there's no regulator. A real regulator would show decreasing impedance to the left, giving good regulation near DC.)That it plateaus to something stable, is both interesting and useful!So, what can we do about the high impedances?One cannot escape the fact that, the power supply rail is a Power Distribution Network (PDN). As with any network, it can be approximated as an RLC equivalent. The basic RLC parts are the ESR, ESL and C from the capacitors, and series L from trace lengths and vias (and sometimes capacitance as well). (Dave kind-of mentioned trace capacitance: however, there is a much more interesting reason beneath that!)When looking at a network, we must observe two things: impedance Z and frequency F. The frequency response of a network depends on only these parameters, and how the impedance and frequency of a given stage (i.e., a single LC unit in the chain) vary from the mean value within the network. If we want to optimize for a particular goal (such as low impedance over a wide frequency range), we have to learn to work within this domain!How do Z and F correspond to the circuit? Very simply:\( Z_0 = \sqrt{\frac{L}{C} \)\( F_0 = \frac{1}{2 \pi \sqrt{L C}} \)Any time you have a chain of series L and parallel C (series meaning, spanning horizontally from branch to branch; parallel meaning, vertically from branch to GND), you have something that looks suspiciously like a transmission line.Traces are fundamentally transmission lines. At low frequencies, we approximate TLs as a single inductor or capacitor: which one we choose depends on how the circuit impedance compares to the TL's characteristic impedance. Lower and it looks inductive, higher and it looks capacitive.The frequency is "low" when it's below, say, 1/10th the electrical length of the TL. At 100MHz, this is 30cm. A 100 ohm trace, 30cm long, has about 115nH of equivalent inductance, and will measure this value over quite a wide range (about 3 decades: from ~100MHz down to ~100kHz, when DCR (~0.1 ohm?) takes over).PDNs are intentionally very low impedances, so we'll only be concerned with traces as inductors. For other circuits, like sensitive analog, or RF, signal impedances can be quite high (kohms, Mohms even!), and we would be concerned about equivalent capacitance instead. (All the same reasoning used here still applies, but you're getting caps instead of chokes!)PDNs also do their work in the "low" frequency range. Trace lengths between capacitors and devices are millimeters, while the frequencies of interest top out at 100MHz or so. (It's not practical to try to design a PDN beyond 100MHz, and most ICs do not require the PCB to be that good. Manufacturers have to deal with this range themselves, which is why very large CPUs have onboard capacitors. Furthermore, within the die itself, vast swaths of parallel metal layers provide very "fast" capacitance, to respond to the tens-of-picoseconds switching edges the transistors produce!)So we can approximate traces as inductors. Whoop de do. Where's the magic?The magic savior is resistance! Use ESR to your advantage. Any time you have loss (equivalent resistance) comparable to reactance, you have a well damped resonant circuit, and instead of peaks and valleys, you get humps and dips.You can solve for the ideal circuit, by calculating backwards from the pin itself.1. Suppose the pin is 5nH (a couple mm length from die to PCB pad). It's a VCC pin, adjacent to a GND pin, on, say, a TQFP packaged microcontroller. (There are probably four or more pairs of VCC/GND pins around the chip -- simply solve for one, and repeat the layout for all of them.)2. The microcontroller demands peak currents up to 100mA (per pin pair / IO bank), regulation better than 10% (i.e., no peaks or dips or ringing beyond +/-10%), and has a 3.3V supply. That means delta V <= 0.33V, and Z <= 3.3 ohms. This is required up to 50MHz.3. The pin itself has 5nH, which has a reactance of 3.3 ohms at \$ F_{\textrm{max}} = \frac{3.3 \Omega}{2 \pi 5\,\textrm{nH}} \$ or 105MHz, so we only have about 50% overhead for ESL to the first cap.4. We'll use an 0603 0.1uF cap near the pin pads: this will be around 3nH. Total inductance to the device is now 8nH, so we expect to achieve 2.5 ohms at 50MHz. At that frequency, the capacitor looks inductive (Xc = 0.032 ohms, less than the ESR even, so ESL is dominant), and the voltage dropped across the ESL is a modest fraction of the voltage at the pin (the pin ESL and cap ESL act as a voltage divider).5. We can resonate the ESL with another capacitor. Now here's the magic: if we can choose components so that the impedance \$Z_0 \leq \textrm{ESR}\$, we can have the ESR dominate, and the resonance will be damped! We're starting with about an ohm's worth of ESL, so we have to add an ohm of ESR somewhere.6. We could put a resistor in series with the cap, or we can put an R+C in parallel with it. A series resistor will itself have ESL, making things too much worse, so let's do the latter. R = 1 ohm and \$C \geq 2.5 \times \$ the other cap (i.e., 0.25uF -- 0.33uF or 0.47uF is the next closest value).This looks like:I've assumed an 0603 is reasonable for 0.47uF, which certainly is true for a 3.3V supply (I'd recommend a >= 10V X7R part, readily available).Note how flat it is (relatively speaking), and there are no peaks! Indeed, it flattens out to 0.5 ohms in the middle there, where the supply acts in parallel with the local "bulk" cap -- which itself isn't really very bulky, and could be smaller while still serving the same function.We don't even really need the 0.47uF at all -- in the <10MHz range, the supply itself is doing a fine job. With the 0.47uF removed, the curve stays flat at 0dB (i.e., 1 ohm) until the notch.The notch, by the way, is 3nH + 5nH and 0.1uF ==> 5.8MHz. Eagle eyed readers will have spotted this.8. What if we want to do better?We can't really raise the high frequency limit, because that's the manufacturer's problem, due to pin geometry. (With some series-resonant trickery, it can be pushed closer, but I won't go into that here.)If we wanted to make the 'mid-band' lower and wider, we can simply add larger capacitors in parallel. Because the frequencies are low, they can be placed at modest distances (10-30nH), which makes them very easy to place. But we can't go crazy, either: a few electrolytic or tantalum will improve things, because their ESRs will act in parallel, presenting a reasonable resistance (say 0.1-0.5 ohms) across a wide spectrum, without making things resonate. But ceramics or aluminum polymers, untamed by added ESR, will make things significantly worse...This is just removing the ESR from the 0.47uF, and shoving it a few cms away, so it's about midway between the supply and the pin. How horrible!However, it's noteworthy that we still haven't blown the spec. The supply will ring noticeably at the peak there (3nH + 3nH + 15nH and 0.47uF + 0.1uF ==> 3.8MHz), but with an impedance of 1.7 ohms, it won't ring worse than about 2.5% of the supply (~85mVpk), and that's if the MCU thrashes multiple simultaneous GPIOs at the resonant frequency!This is the reason why manufacturers and appnotes almost always suggest capacitor overkill: if you don't know any better, adding more caps isprobablynot going to make things critically worse. But it often won't make things any better, and a critical analysis of the network, and its properties, will show why that is true.Cheers,Tim

author: Carrington
author_rank: Super Contributor
timestamp: March 12, 2016, 06:15:30 am
content: That is why SIwave and similar SW exist.@c4757p: I'm waiting for my new brownie points now.

author: Fungus
author_rank: Super Contributor
timestamp: March 12, 2016, 12:41:40 pm
content: Dave: Goof at 31:29... you said the 0612 has 170puffof inductance.

author: Brumby
author_rank: Unknown
timestamp: March 12, 2016, 12:50:48 pm
content: Picky, picky, picky....

author: John_ITIC
author_rank: Frequent Contributor
timestamp: March 12, 2016, 08:32:06 pm
content: HyperLynx Power IntegrityAccurately model power distribution networks and noise propagation mechanisms throughout the PCB design processhttps://www.mentor.com/pcb/hyperlynx/power-integrity/

author: Fungus
author_rank: Super Contributor
timestamp: March 12, 2016, 08:40:52 pm
content: Quote from: Brumby on March 12, 2016, 12:50:48 pmJust to let him know so he can add a Youtube comment...

author: NiHaoMike
author_rank: Super Contributor
timestamp: March 13, 2016, 04:31:59 am
content: If making ceramic capacitors "sideways" makes them less inductive, why aren't all low voltage, high value ceramics made that way?

author: EEVblog
author_rank: Unknown
timestamp: March 13, 2016, 06:00:58 am
content: Quote from: apis on March 11, 2016, 04:28:54 pmYeah, pretty much.And any measurement is pretty pointless unless it's on the actual target PCB

author: uncle_bob
author_rank: Unknown
timestamp: March 13, 2016, 03:35:22 pm
content: Quote from: EEVblog on March 13, 2016, 06:00:58 amHiSimply tooling up to properly *make* << 1 ohm wide band measurements is far from trivial. There are a lot of gotcha's along the road to getting it right on a real target like a pc board. Grabbing a 10 KHz to 10 GHz network analyzer is the *easy* part of the process.Bob

author: nctnico
author_rank: Super Contributor
timestamp: March 13, 2016, 09:50:31 pm
content: How about using a 50 Ohm to 0.1 Ohm RF transformer connected to a test point on the board and use a directional coupler to look at the return loss in a frequency sweep?

author: uncle_bob
author_rank: Unknown
timestamp: March 14, 2016, 02:10:00 am
content: Quote from: nctnico on March 13, 2016, 09:50:31 pmHiOk so now we need a broadband 50 ohm to 0.1 ohm transformer ... hmm ... check Mini Circuits .. .not so much.Assuming you built such a beast, you would find that it is surprisingly narrowband. Getting a couple decades of "good response" only happens if you have a fairly liberal interpretation of "good". If you want to check over as many decades as a modern board is likely to need, you will have to do a *lot* of transformers.Next step is to calibrate both the transformer and the directional coupler. That involves "known good" standards at least for short / open / and load. Open always has issues on any calibration setup. Maybe a bit less so here. Short needs to be a short to << 0.1 ohms. That is true both in terms of absolute impedance and phase (non reactive). Your 0.1 ohm standard ... lots of fun.Now we need to connect those standards to the output of our test rig. Each standard needs to be connected in turn. Each needs to have the same "reference plane" as the others. APC-7 connectors take care of part of this at 50 ohms. Grab the catalog .. no 0.1 ohm connectors listed at DigiKey. Same thing with 0.1 ohm cable. Connector and cable impedance is a function of a few things, one is inner conductor diameter as a percentage of the inside of the outer sheath. For 0.1 ohms ... errr ... So we parallel a few cables we can get.... gee that's a lot of cables ...No that's not the whole story, but you probably get where this is leading off to.It's far more common to measure at a few spot frequencies and maybe over the top decade / octave than to sweep the entire board accurately. It's even more common to "try it and hope (maybe based on modeling)" than to measure a board before there is a problem.Bob

author: Ampere
author_rank: Regular Contributor
timestamp: March 14, 2016, 04:15:08 am
content: Great bypass cap tutorial. I learned a lot.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 14, 2016, 04:15:14 am
content: Er, well, you don't need to be taking 0.1 ohm out for a walk... just put it right there on the fixture. It'll all be hand made, and the transformer secondary will be a short 'C=' section of copper foil, the '=' being a wide, thin parallel plate transmission line. Primary (and core) fits inside the 'C', maybe using a pot core?What's more, 0.1 ohms is pretty arbitrary; 1 or even 10 ohms would still improve sensitivity without making things so aggressive.I've used matching transformers in this range for induction heating applications; you get bandwidth to a few MHz, which is more than enough for typical purposes. An optimized design might struggle to achieve under 1 ohm beyond 100MHz, but I suppose that would still be good enough here.Tim

author: jnissen
author_rank: Regular Contributor
timestamp: March 14, 2016, 06:42:33 pm
content: Most of the comments to date have been accurate and on target. I did do quite a bit of system level analysis in a past life with various IBIS modeling packages to predict resultant signal integrity. One of the better ones was Sigrity's tool flow. Used real package parasitics in addtion to the board file and localized decoupling. Could get you fairly close to real on die power droop and resultant signal integrity effects. Was insightful and provided fairly good results.Now that I do on die work I have always kept those analysis limitations in the back of my mind. The fundamental take away is that you have to have a local on die source of decap in high di/dt loading environments to overcome the limitations in the power delivery network of the package and board. I do significant sims to ensure that our package model parasitics can be overcome with on die decoupling. Sometimes the loads are just too fast and large that is nearly impossible to achieve enough on-die decoupling and in those cases you can attack the problem at the source. Perhaps re-architect your drivers and limit edge rates where appropriate.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 14, 2016, 07:11:24 pm
content: Quote from: jnissen on March 14, 2016, 06:42:33 pmHello,Do you work with digital / logic, or PMIC as well? I have a question about integrated switching regulators, if you've worked on 'em.Tim

author: uncle_bob
author_rank: Unknown
timestamp: March 14, 2016, 07:46:17 pm
content: Quote from: T3sl4co1l on March 14, 2016, 04:15:14 amHiWe obviously work on different things. The stuff I work on barely starts at 1 MHz and the planes need to be low impedance to well past a few GHz to be useful. Is that 0.1 ohms or something else? The 0.1 came from an earlier set of posts.Bob

author: apis
author_rank: Super Contributor
timestamp: March 14, 2016, 10:43:42 pm
content: It's funny how often a lot of theory in practice boils down to "try and see what works". It's like when you take a statistics course with a lot of calculus and algebra and in the end the most important result is that the arithmetic mean is a good estimate of most things.But anyway, a great video and lots of great comments.

author: nctnico
author_rank: Super Contributor
timestamp: March 14, 2016, 11:33:06 pm
content: Quote from: uncle_bob on March 14, 2016, 07:46:17 pmThe 0.1 Ohm is just a number to get some meaningfull results by injecting enough current into the DUT and perhaps there are better ways of making some kind of probe. Ofcourse it isn't going to be as easy as putting some wire on a core and attach a bunch of long wires/cables to it. Anyway you need to keep in mind that checking the behaviour of a power decoupling system isn't going to be exact science anyway so if you want to determine whether there is excessive peaking or not over a certain frequency range you could use a crude tool for a ball-park estimate. Ideally you'd need to have all the power rails at their operating voltages to include the effect of voltage dependant capacitance changes.

author: uncle_bob
author_rank: Unknown
timestamp: March 15, 2016, 12:11:16 am
content: Quote from: nctnico on March 14, 2016, 11:33:06 pmHiOk, we do (on average) a board a week. Doing a full blown measurement of that board (with all the calibration) is about six months per board. Yes, both are man hours. So off we go to the finance barons and say "we need to increase our board design costs by 24X". We then go to sales and say "we need to do a board / measure a board / redo a board" for each design. That will take the design process (and our delivery) out by ??X. Neither group is exactly what I'd call "happy".Bottom line, the money you save with a fancy / validated design (it needs 3 less caps) is a bit tough to sell up front. Overkill is a lot cheaper / faster / easier / more normal and it works.Bob

author: nctnico
author_rank: Super Contributor
timestamp: March 15, 2016, 02:06:44 am
content: I'm not quite sure where you are getting at. Do you expect to need 6 months to measure a board or are you currently needing 6 months to test a board?

author: uncle_bob
author_rank: Unknown
timestamp: March 15, 2016, 10:32:16 pm
content: Quote from: nctnico on March 15, 2016, 02:06:44 amHiIf you are going to do all that is involved in testing a board over a wide range of frequencies, it will take a long time. The last time I went down this road, 6 months was an overly optimistic time span for doing it. If you did it full time and already had some setups, you probably could do a full (measured) characterization of a board in 6 months. That's an un-acceptable amount of time when compared to the design process that I'm familiar with.Again, this is on fair sized boards that are running multiple rails, some at voltages like 1.2 or 0.9. Currents in the couple amps to tens of amps are not unusual. They have significant energy running around well into the 10's of GHz range. There's noting terribly crazy about them. They are running fairly normal FPGA's and DSP stuff. The internal edge rates of this stuff (and thus the current spike widths) can be amazingly fast. The current all comes from the power plane ...(not quite correct, but close).Bob

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 15, 2016, 11:43:30 pm
content: Er, well, all that nastiness is handled on the die, even. Large power planes occupy at least a few metal layers; some transistor junctions also serve to bypass those nearby. In the GHz, caps on the interposer handle transients that the PCB couldn't possibly handle directly. PDN bandwidths are only in the 100MHz range.Tim

author: uncle_bob
author_rank: Unknown
timestamp: March 16, 2016, 12:15:54 am
content: Quote from: T3sl4co1l on March 15, 2016, 11:43:30 pmHiWish that was true .... If it's a chip scale part, your are straight into the die.Bob

author: Fungus
author_rank: Super Contributor
timestamp: March 16, 2016, 10:56:10 am
content: Quote from: uncle_bob on March 15, 2016, 10:32:16 pmWhat would it achieve, exactly? What would be the benefit over the quick-and-dirty techniques?

author: uncle_bob
author_rank: Unknown
timestamp: March 17, 2016, 01:21:24 am
content: Quote from: Fungus on March 16, 2016, 10:56:10 amHiYou *would* know what the board actually did.It's expensive / complex enough that there really is little call to do it. With low voltage / high currents the impedances are indeed pretty low. The frequency ranges are quite wide .... it's a royal pain.Bob

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 27, 2016, 11:39:08 am
content: Ew, unit typoes...But yeah, your clues are here: "General Purpose", so you know they're going to be shitty, and "Dissipation Factor" (~0.2). If that's measured at 120Hz (typically the case), then a 100uF capacitor has a reactance of 13 ohms and ESR of 2.6 ohms.And no electrolytic in history has ever been rated for kiloamperes.Tim

author: David Hess
author_rank: Super Contributor
timestamp: December 01, 2016, 06:25:01 pm
content: Quote from: EEVblog on March 11, 2016, 03:54:11 amI have seen some designs go a step beyond adding series resistance to increase the ESR. Instead they selected a value of decoupling capacitance and adjusted the length of the traces so that the low impedance series resonate frequency was located on top of a troublesome switching harmonic. In this way they could notch out various harmonics generated by the clocking of the digital logic or switching power supply.

author: David Hess
author_rank: Super Contributor
timestamp: December 01, 2016, 06:33:14 pm
content: Quote from: NiHaoMike on March 13, 2016, 04:31:59 amThe greater force from the surface tension of the solder and the lower force from gravity makes the part more likely to suffer afailure.

author: David Hess
author_rank: Super Contributor
timestamp: December 01, 2016, 07:07:44 pm
content: Quote from: c4757p on March 11, 2016, 03:40:54 pmAudio amplifiers commonly require a series RC network for stability which illustrates what is going on in a more visible manner. Some comparators can be used as operational amplifiers if a suitable RC snubber is added to their output. Some seemingly intractable operational amplifier oscillation problems can be solved by adding a large high ESR output shunt capacitance.The RC network whether the R is part of the ESR or provided as a separate component is part of the frequency compensation network. Lower performance "high dropout regulators" with their emitter or source follower outputs have a low impedance so they are more tolerant of low ESR output capacitors than high performance "low dropout regulators" with their common emitter or source follower outputs which have a relatively high output impedance. You can still make a high dropout voltage regulator oscillate under the proper conditions though; the common old 7805 and 7905 linear regulator application notes show a low ESR decoupling capacitor at the input and *only* a small high ESR bulk capacitance at the output.Switching regulators have all of the same problems and can also be made to oscillate if the output ESR is too low. There is a trade off between output ripple and feedback loop stability.A bode plot which includes the output RC network can be very informative. I have occasionally varied the output capacitance and ESR while measuring their effect in order to derive unknown aspects of the of the feedback network using a bode plot. A network analyzer could always be used to measure it directly but one is not always convenient.QuoteThis is a common brute force solution. It becomes fun when you want to determine how little capacitance you can get away with or how much design margin is present.

author: VanitarNordic
author_rank: Frequent Contributor
timestamp: May 08, 2018, 07:47:41 am
content: What types of bypass capacitors must be used?All should be ceramic?

author: Fungus
author_rank: Super Contributor
timestamp: May 08, 2018, 08:10:59 am
content: Quote from: VanitarNordic on May 08, 2018, 07:47:41 amFor TTL circuits? Yes. Speed is essential.Electrolytic are much too slow, ceramic are in a good place on the fast/cheap graph.

author: VanitarNordic
author_rank: Frequent Contributor
timestamp: May 08, 2018, 08:50:05 am
content: Quote from: Fungus on May 08, 2018, 08:10:59 amNot just TTL, for any digital or MCU based circuit which might accompany analog parts or analog ICs such as Opamp. If we gonna use 3 capacitors, I was thinking to use tantalum for the biggest one (1uF). what do you think?10nF and 100nF => ceramic1uF => tantalum

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 08, 2018, 09:30:13 am
content: Quote from: Fungus on May 08, 2018, 08:10:59 amSlow in what sense? Is an electrolytic with approx. equivalents C = 100uF, ESR = 0.5Ω and ESL = 3nH "slow"? (Hint: it'll probably outperform most recommended combinations of ceramics!)The RC time constant is a small part of the story. Typically, the layout is a bigger part!Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 08, 2018, 09:33:29 am
content: Quote from: VanitarNordic on May 08, 2018, 08:50:05 amStacking up different value ceramic caps is foolhardy. Normally, it makes thingsworse. No one realizes this, because no one tests this!Tantalum are generally safe from an impedance standpoint, but 1uF may be too small, in that its ESR will be too high to be beneficial. Tantalum are also unsafe on high current power supplies -- they tend to catch fire.Tim

author: David Hess
author_rank: Super Contributor
timestamp: May 08, 2018, 11:36:17 am
content: Quote from: T3sl4co1l on May 08, 2018, 09:30:13 amBut it will be unlikely to outperform a combination of an electrolytic and ceramic capacitor.Usually a single larger electrolytic capacitor is use for bulk decoupling of many packages and to swamp out resonances of the higher Q ceramic capacitors. (1)QuoteWhich points to why one larger electrolytic capacitor can serve for bulk decoupling of several individually decoupled packages. The small capacitors do not have enough capacitance to work at low frequencies and at low frequencies, the relatively remote electrolytic capacitor is not that far away.Quote from: T3sl4co1l on May 08, 2018, 09:33:29 amSome application notes recommend this for specific parts like wideband operational amplifiers and converters. I wonder though if these date from the time when through hole layouts were parasitic inductance was greater. (1)It is not quite the same situation but one project I did involved a 50 ohm high power capacitive ground isolator which operated from 50 MHz to 1.2 GHz. It ended up with 4 x 1000pF, 4 x 0.01uF, and 4 x 0.1uF surface mount ceramic capacitors in parallel using a symmetrical coaxial transmission line layout. Just using 4 x 0.1uF capacitors did not work at all.QuoteThis sort of thing has always bothered me. Why isn't the output from the power supply better controlled to limit surge current or dv/dt?(1) At some point it pays off to model the power distribution circuit and if you have the proper equipment, test it. I suspect this is either foreign or infeasible for many engineers leading to a mix and mash of various rules of thumb for decoupling which usually work but not always. Jim Williams had something to say about decoupling in Linear Technology application note 47 but unfortunately did not test any polymer electrolytic capacitors.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 08, 2018, 07:03:13 pm
content: Quote from: David Hess on May 08, 2018, 11:36:17 amYup, a hybrid approach, where a high-Q cap is dampened by a low-Q bulk cap, is best. This gives low impedance at all frequencies, from DC (where the supply regulator dominates), to mid band (where the bulk cap ESR dominates), to high band (where the ceramic chip's ESR and ESL dominates).QuoteUsually, a bulk cap goes at the end of a chain of supply connections, where the chain is made of traces linking loads with bypass caps. It's a pretty safe topology, the ESL is easily estimated, and the required bulk cap C and ESR are easily calculated from that.When the chains are single links only, it can be tricky. When would that happen? When loads are individually bypassed, and draw power from a plane pair. In some cases, it can be better to not use local bypass in this situation, or to use longer traces from bypass cap to plane (so that ESL is large enough that it can be damped with a bulk cap).QuoteCould be.It does help if you use different sized chips -- ESL is proportional to length -- but you still must be mindful of damping, otherwise the worst-case impedance peak will rise above the required supply impedance, and you'll get spooky behavior at unlucky frequencies.QuoteRight. You needed 12 x 0.1 instead.I don't understand the topology from that brief description, so it's hard to say which way is better. (The only thing you gain from using just 0.1's is BOM reduction, mind.) Obviously, it worked out well enough your way, and that's what matters.QuoteI don't think it's a thing you can control. Surge can't be limited, on the time scale of the capacitor; current is drawn from all other bypasses and bulk caps, before the controller can do anything about it. dV/dt should be fine with modern DC-DC controllers, as long as you aren't hot-plugging to the supply. Apparently part of the problem is that, tants crack over time, and self-heal, and that self-heal process draws a huge gulp from the supply. Which can cause random upsets! And, of course, an unlucky self-heal that runs away, results in an exploded cap...So it's something that has to be used carefully, I guess preferably on small supplies or sub-nets. Fused caps can be used (that was an IBM thing, IIRC?). Overrated caps (2-3x voltage) is part of it, of course.Where long life, reliability and uptime is required, ceramic chip + ESR resistor is preferred. The ESL isn't even any greater, if "wide body" parts are used.QuoteYup. That we should be so lucky, that we work in a field where everything can be calculated and measured, if not always easily, but almost always with a hand-waving shortcut that is more than good enough!Regarding polymers: they are simply low-voltage film caps. Same energy density, same time constant (i.e., ESR * C), similar ESL (again, proportional to lead length, so, the chip styles are better than the can styles). They don't leak current, or reform, like electrolytics do (at least, not as grossly), and they may self-heal (I've heard that some can, though the ones I've tested, failed shorted at about 120% of rating).ESR is generally low, though a broad spectrum is available. About the same range is available between polymer and tant, with the tants clustering towards higher ESR (say 0.1 to 10 ohms), and polymers clustering low (say 10m to 1 ohm). There is plenty of room to shop around for ESR, in both types.Since ESR is generally low, polymers can make thingssignificantly worseby shorting transmission lines, leading to reflection rather than absorption of waves.They are of course an excellent choice for power supplies, where the low ESR is required for stability and low loss. This puts a very low impedance at one end of the supply, so that damping must be provided at the far end.Or the supply must be designed with a low enough impedance throughout, comparable to the low ESR. This is how most VCORE supplies are constructed -- a handful of polymers at the start and end of the VCORE plane, and a ton of ceramic chips spread evenly inbeteen. Inspect a laptop motherboard some time, and see how the experts do it.A good example where polymers shine, by themselves alone, is high power gate drives. Like IXDD614CI driving +/-15V into a big IGBT. A 100uF 35V poly across the power pins, is all that's needed to keep things happy! Notice this acts exactly like the ceramic cap across a TTL chip, just scaled down in impedance and speed (t_r ~ 20ns, easily 10 times slower), and up in power.Tim

author: David Hess
author_rank: Super Contributor
timestamp: May 08, 2018, 09:05:34 pm
content: Quote from: T3sl4co1l on May 08, 2018, 07:03:13 pm12 x 0.1 was the first thing I tried and it failed at high frequencies. 4 x 0.1, 4 x 0.01, and 4 x 0.001 worked so well that I stopped at that point. I was just using cheap 1206 size ceramic capacitors; maybe 4 (or 12) x 0.1uF RF parts would have worked but they would have cost much more than my final solution.Essentially this was a coaxial DC block with the DC block part on the shield rather than the center conductor. The capacitors were symmetrically placed around the periphery. It had to operate at 50 watts from 50MHz to 1.2GHz with a minimum loss. The final design worked great; loss was essentially too low to measure and consistent with the residual loss of the coaxial transmission line itself.QuoteMost of the failures I have seen happened at turn on and even more where there was a lack of current limiting, lack of soft start, or where dV/dT was not limited by bulk output capacitance.I no longer consider solid tantalum capacitor failures a mystery. The big problem appears to be stress cracks from thermal cycling during soldering; the same capacitors which have been burned in and tested before soldering have their infant mortality reset by soldering. The other failures are just straight dV/dT or surge current due to poor design (lack of derating) and then the rare mysteries where the capacitor is operating within its voltage specifications, has no ripple current, and just fails as you watch it. The last might be due to field crystallization around defects but NASA says this does not occur with low voltage parts. That I have not seen this happen with hermetically sealed parts suggests to me that it is related to stress induced by the epoxy packaging from humidity maybe?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 09, 2018, 01:28:22 am
content: Quote from: David Hess on May 08, 2018, 09:05:34 pmHmm, was that like a piece of hardline slit open (not through, leaving the center conductor and insulator in place)? Sounds really mechanically dubious, was there support elsewhere? What pattern were the capacitors, alternating values?QuoteHmm, could be.On that note, I'm glad I have a dozen or two 10uF 50V hermetic (dry) tants. Huge, quite heavy, though the ESR isn't terribly great. No wet-slugs though. (If I did I'd probably sell them, hah!)Tim

author: David Hess
author_rank: Super Contributor
timestamp: May 09, 2018, 05:04:43 pm
content: Quote from: T3sl4co1l on May 09, 2018, 01:28:22 amThis was not for production. I actually ended up using a length of RG-400 with the double braid cut away so that the surface mount capacitors were flush with the dielectric preserving the dimensions of the transmission line as much as possible. With so many capacitors handling the strain, it was actually pretty rugged but still what I would consider fragile. The length of RG-400 provided enough strain relief.The surface mount capacitors were mounted edge on and not flat to the dielectric which is not ideal but allowed many more of them to be used to fill the circumference making it mechanically stronger. There was no way that 12 would have fit if mounted flat although that was the original ideal. The thickness of the double braided shielded helped here and of course the Teflon dielectric allowed soldering and clean up without melting. I did not even consider trying this with anything other than solid Teflon dielectric. The largest problem was the high thermal conductivity and thermal capacity of the double silver placed copper braid but a good temperature controlled soldering iron was enough.Since 4 capacitors of each value were used, I placed each value at 90 degrees with respect to each other just like a 50 ohm coaxial termination might be made with 4 x 200 ohm resistors.QuoteThe hermetically sealed solid tantalum capacitors I have saved were not much larger than any other tantalum capacitor. I have not measured a significant difference in ESR (actually dissipation) between the various flavors but I lack a low frequency network analyser or multifrequency LCR meter to make a good comparison which makes me wonder why wet tantalum capacitors were ever used in bulk power supply decoupling applications. Maybe for higher ripple current and higher operating temperature?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 09, 2018, 05:59:50 pm
content: Quote from: David Hess on May 09, 2018, 05:04:43 pmAh, and that explains the question of scale as well. Crazy.QuoteDunno. Mil spec whatever they are, pretty sure no one else dares buy them -- except for the occasional test, apparently they (wet slug) have lower leakage than anything else but only after a week or two of "soak".There are mil spec electrolytics as well, and high temperature ones, presumably the lifetime failure rates differ between them and one happens to be better for certain applications, damn the price.Tim