Lattice MachXO3L FPGA starter kit pinout help - Page 1
Forum section: electronics / general

author: tamas1187
author_rank: Newbie
timestamp: January 25, 2016, 09:23:21 am
content: I'm hoping there is someone that's had experience with Lattice MachXO3L FPGA starter kit, or is better able to interpret the documents.I've been trying to figure this out for a while and looking up and down and all over, and can't find anything that answers my question. I will admit I'm university and new to FPGAs, so I'm still trying to work out the difference between my elbow and my knee... Incidentally, the very fact that I'm a student, and registered on LS's website as a student to download their software, attempts to ask for any help or clarification there were stopped because assisting a student is apparently against company policy.I've referred to the Lattice website, and I've found a CSV file  that shows the pinouts for the board and 5 different chip types. I'm confused by what is meant by I/O grouping, as there are only two categories (+ and - ). Furthermore, my understanding is that the pins are assigned as complementary pair inputs. That'd be fine and dandy but for the fact that after double-checking, there are pin pairs on the list that do not appear on my board, and there are pins on my board that do not appear on the CSV file. Looking into the data sheet/brochure for the device did not provide any clarification. Searching LS's website did not yield any further information.It's ambiguous as to whether the pinout capabilities refer to the board or the chip, and it is further ambiguous as to how the board is set up, whether the I/Os are all independent or whether they are complementary pairs. Is there anyone who can confirm for me how this board works? I'm trying to avoid bricking a bunch of boards in just trying to find out how this thing works.I'm just trying to avoid having to cough up $200 and burn through a bunch of FPGAs before I finally manage to figure out how to connect this properly. I sincerely appreciate any help.relevant links: latticesemi.com/en/Products/DevelopmentBoardsAndKits/MachXO3LStarterKit.aspx latticesemi.com/Products/FPGAandCPLD/MachXO3.aspx?ActiveTab=Reference+Design#_FAB1DF60223D4AFA8425413790E0F113(pin and package, MachXO3-6900 Pinout)

author: Tainer
author_rank: Contributor
timestamp: January 27, 2016, 05:48:13 pm
content: This board is organized pretty much like any other dev-board: most of the pins are routed directly to the break-out headers. Each header pin and corresponding FPGA pin/ball and their function is described in theuser guide, page 10.You decide which pins you need and then you declare them in your project's *.lpf file, for example:Code:LOCATE COMP "button" SITE "D7";Then you configure pull-up mode and I/O type:Code:IOBUF PORT "button" PULLMODE=UP IO_TYPE=LVCMOS33;I'm not sure what you mean by complementary pairs. There are four 2x20 headers available for user I/O. Their behavior depends on how you implement it in VHDL/Verilog.

author: Muxr
author_rank: Super Contributor
timestamp: January 27, 2016, 05:53:23 pm
content: Quote from: tamas1187 on January 25, 2016, 09:23:21 amIf you start a project in the Diamond software there is a package view as well as the spresdsheet view that tells you what the pins are and their capability. You can reprogram most of them. But all that info should be in the Diamond app itself. When I used the MachXO2 I remember looking to find default JTAG pins and I wasn't able to find it in their PDFs. I remembered downloading some CSV files as well, but forget all that, it's all nicely laid out in the Diamond app itself.

author: joy586210
author_rank: Newbie
timestamp: January 29, 2016, 06:24:42 am
content: Suggest you to read diamond user guide before use dev kit:http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/1D/DiamondUG_36.pdf?document_id=51419