Looking for routing advices of USB3 & PCIE - Page 1
Forum section: electronics / projects

author: hitech95
author_rank: Regular Contributor
timestamp: May 28, 2019, 04:15:29 pm
content: Hi,I'm tring to add an USB type C with PD (TPS65987D) to a Chromebook:The board would replace the io expansion board inside my Chromebook. Beeing a Chromebook the full firmware is available as open source code. (Both EC and BIOS, in this way I can enable the disabled gpios and the pcie lines on the PCH and add the power gates to the EC)I also have the mainboard schematic available taken from the NET. ( It looks correct after a few tests)In the same footprint I would add both a pcie USB 3.1 controller and the PD management chip, the data mux, and the accessory mux. (It already have some passives for the LEDs, an MMC/SD controller over USB2 and a USB2 so I also have to add that back)So far I have created a basic schematic of the circuit based on two reference design.The first reference design is the USB 3.1 controller from Asmedia (ASM1142 + SS MUX AMS1542) and the other is the USB-PD controller (TPS65987D + ACCESSORY MUX)After reading a few application note I have a couple of questions about the USB3 and PCIE busses.USB3 is a 90 ohm impedance matched diff pair interface. Each pair clearance should be at least 3 times the pair width. (The pair spacing or the whole 2 times track width + the pair space?) My board is quite small and I cannot mantain this clearance for all the board, is this so restrictive?Another question is, should I length match each section of the differential pair to make the signal travel together? (I know that TX and RX pairs can have different lengths)Due to the fact that I will hand solder this board I cannot solder passives smaller than 0402 (I don't have a steady hand and I don't own a micro soldering iron) but in this way the max unmatched length of 5 mils is not respected in tho places: The ESD diodes and the decoupling caps. Does you have some raccomandation?On the reference designs I've seen common inductors on the USB2 interface pair, and on SS pairs of USBA 3.0 (different type for SS and USB2) but on USB-C connector I haven't seen the inductors for the SS pairs. (I have no idea if I should add those and if I should place them before the mux or after it!)This is my schematic (USB-C After the Mux):PCIE is a 90 ohm impedance matched diff pair interface. But in some design the impedence is set at 100ohm for the clock pair. Is there a specific rule? I I'll have to connect this bus to some test point on the motherboard (Yes a full pcie is available via test point). Due to the limited space available my idea was to use a HDMI flat/fpc cable. As far I know the HDMI should have the impedance controlled pair matched at 90ohm. (I know that the best solution would be to use a SATA cable but it's too thick) any other solution other those two options?This was my idea:To connect to the test point (they are quite small) I've designed a custom 1.2mm pcb with castellated pads to match the shape of the motherboard! So I can glue the adapter board (double stick tape) on the motherboard and I cannot rip the pads with the floating wires. (The pcie ribbon is connected to the adapter board. No idea if there is a better solution other than being careful)Talking about the USB-PD I'm still trying to figure out if the controller can be programmed and than used without the external spi eeprom! (The space is running out!)(NO: I must add another external EEPROM)Another question that I have is if the TPS65987D can close the HV Synk mosfet only if the PDO#2 is negotiated so I don't have to use an external pair of mosfet. But after reading all the datasheet and the various application notes, working with the firmware configuration toolkit I still haven't figured out if it's possible)I'm waiting for a complete reply from TI about that.If you have any advice it would be wonderful!This is also my first full project using Altium, so far I've only used Circuit Maker!Have a nice day,Hitech95References & photoshttp://www.ti.com/product/TPS65987Dhttp://www.asmedia.com.tw/eng/e_show_products.php?cate_index=175&item=158https://photos.app.goo.gl/8GqGPYvLyZoVXrqU6https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices/acer-c720-chromebook/c720-chromebook-innards.png?attredirects=0

author: hitech95
author_rank: Regular Contributor
timestamp: May 30, 2019, 07:47:20 pm
content: I've seen that some Pcie extenders use standard ribbon cables, and they look working fine.So the FFC idea is not that bad, at least if I can find one with a shielded side it might be even better!