Implementing old PAL/GAL into HDL - Page 1
Forum section: electronics / general

author: caius
author_rank: Regular Contributor
timestamp: July 28, 2021, 05:13:43 pm
content: Hi all,I'm porting into Quartus some old schematics for CPLD/FPGA implementation.This old hardware made of TTL gates but there are also some PLDs (GALs and PALs) that I have fusemap of.Some of them are pure combinatorial logics and perhaps I know how to write a Verilog module (just matter of declaring the I/O and put equations for each output).But others PLDs are registered so they have sequential logics inside (a clock and an output enable pin).So, I'm looking for some help about.Thanks in advance for any tip/suggestion/example.

author: Bassman59
author_rank: Super Contributor
timestamp: July 28, 2021, 07:40:02 pm
content: Quote from: caius on July 28, 2021, 05:13:43 pmI suppose you should learn how to design sequential circuits in Verilog.

author: caius
author_rank: Regular Contributor
timestamp: July 28, 2021, 08:13:30 pm
content: Quote from: Bassman59 on July 28, 2021, 07:40:02 pmYes, obviously.But, as said,implementing a PLD with combinatorial logics is easy.Here's an example :Code:module PAL16L8_U8(input _MR, PIN14_U16, PIN13_U16, PIN12_U16, PIN19, PIN6_U12, PIN18,output PIN12_U8, PIN23, PIN25, PIN22, PIN27, PIN17_U8, PIN18_U8,inout PIN19_U8);assign PIN12_U8 = ~(_MR & PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN6_U12);assign PIN23 = ~(_MR & PIN14_U16 & ~PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12);assign PIN25 = ~(_MR & ~PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN6_U12);assign PIN22 = ~(_MR & ~PIN14_U16 & ~PIN13_U16 & ~PIN12_U16 & PIN6_U12);assign PIN27 = ~((~PIN19_U8) |(_MR & PIN19_U8 & ~PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN6_U12) |(_MR & PIN19_U8 & PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12));assign PIN17_U8 = ~((PIN19_U8 & ~PIN14_U16 & ~PIN19) |(_MR & PIN19_U8 & ~PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12) |(_MR & PIN19_U8 & ~PIN14_U16 & ~PIN13_U16 & PIN12_U16 & PIN19 & PIN6_U12));assign PIN18_U8 = ~((_MR & PIN19_U8 & ~PIN14_U16 & ~PIN13_U16 & PIN6_U12) |(_MR & PIN19_U8 & PIN14_U16 & ~PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12) |(_MR & PIN19_U8 & ~PIN14_U16 & PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12));assign PIN19_U8 = ~(_MR & ~PIN14_U16 & ~PIN13_U16 & ~PIN12_U16 & PIN19 & PIN6_U12 & PIN18);endmoduleHere's, instead, the disassembling of a registered PAL which I would like to port to Verilog (or VHDL) :Code:/** Inputs **/Pin2 = i2;Pin3 = i3;Pin4 = i4;Pin5 = i5;Pin6 = i6;Pin7 = i7;Pin8 = i8;Pin9 = i9;Pin12 = i12;Pin13 = i13;Pin14 = i14;Pin15 = i15;Pin16 = i16;Pin17 = i17;Pin18 = i18;Pin19 = i19;/** Outputs **/Pin12 = o12; /**(Combinatorial, Output feedback output, Active low) **/Pin13 = o13; /**(Combinatorial, Output feedback output, Active low) **/Pin14 = o14; /**(Registered, Output feedback registered, Active low) **/Pin15 = o15; /**(Registered, Output feedback registered, Active low) **/Pin16 = o16; /**(Registered, Output feedback registered, Active low) **/Pin17 = o17; /**(Registered, Output feedback registered, Active low) **/Pin18 = o18; /**(Combinatorial, Output feedback output, Active low) **/Pin19 = o19; /**(Combinatorial, Output feedback output, Active low) **//** Equations **/!o12 = o13;o12.oe = vcc;!o13 = o17 & o18# o16 & !o18 & !o19;o13.oe = vcc;!o14 .d !i2# i2 & !i4 & o14# i2 & i4 & !o14;o14.oe = OE;!o15 .d !i2# i2 & !i4 & !i5 & !o14 & o15# i2 & !i4 & i5 & o14 & o15# i2 & i4 & !i5 & o14 & o15# i2 & i4 & !o14 & !o15# i2 & i5 & !o14 & !o15# i2 & !i4 & !i5 & o14 & !o15# i2 & i4 & i5 & o14 & !o15;o15.oe = OE;!o16 .d !i2# i2 & !i5 & o15 & o16# i2 & !i4 & !i5 & o14 & o16# i2 & i5 & !o16# i2 & i4 & !o15 & !o16# i2 & !o14 & !o15 & !o16;o16.oe = OE;!o17 .d !i2# i2 & !i3 & i6 & o17# i2 & !i3 & o17# i2 & !i5 & i6 & o17 & !o19# i2 & i3 & i5 & !o17# i2 & i3 & !i6 & !o17# i2 & i3 & !o17 & o19# i2 & !i6 & !o17 & o19;o17.oe = OE;!o18 = i3 & o17# !i3 & !o17 & o19;!o19 = !i4 & o15 & o16# !i4 & o14 & o16;You can see four outputs are registered so there is a clock and a output enable

author: Bassman59
author_rank: Super Contributor
timestamp: July 28, 2021, 08:43:51 pm
content: Quote from: caius on July 28, 2021, 08:13:30 pmimplementing that combinatorial logic in Verilog or VHDL is similarly trivial.My point is that you have to learn the language before you can port the code to it.Once you do -- and the stuff you need to know will take you a day to learn -- you'll see that you can very easily do what you ask.

author: caius
author_rank: Regular Contributor
timestamp: July 28, 2021, 09:43:47 pm
content: If I had time I would gladly learn Verilog but sadly too many things to do in real life.That's why I asked for help here