SMP, Symmetric Multiprocessing, looking for a good book - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: December 19, 2015, 05:25:50 pm
content: so xmas is coming, I have a more free time and my hobby(1) gets involved in Symmetric multiprocessing (also known as SMP), which involves a symmetric multiprocessor system hardware and software architecture where two or more identical processors and I'd like to learn something about from a good book as currently I am learning from the linux sources, which is the worst way everFeel free to suggest me an idea, suggestion, a book title (or its ISBN) to be filled in the end corner of my wishlist in Santa Claus's letter, hopefully we are still in timethank you(1) I am dealing with two R12K MIPS4 64 bit, trying to fix a few troubles with linux

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2015, 12:42:35 pm
content: the wiki only provide jurassic references, such as:IBM System/360 Model 65 FunctionalIBM System/360 Model 67 FunctionalAlso, I do not understand the detailed difference between multi processors and multi coreLinux and symmetric multiprocessing

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2015, 12:46:46 pm
content: Unix Systems for Modern Architectures: Symmetric Multiprocessing and Caching for Kernel Programmers1994, by Curt Schimmelfound on amazon, what do you think about the above book ?

author: andersm
author_rank: Super Contributor
timestamp: December 20, 2015, 01:15:11 pm
content: You're going to have to be more specific about what you're looking for. Parallel algorithm design? Implementing SMP primitives? Something else?Is Parallel Programming Hard, And, If So, What Can You Do About It?is pretty low-level,The Art of Multiprocessor Programmingis more concerned with design and correctness of parallel algorithms.Quote from: legacy on December 20, 2015, 12:42:35 pmMulticore is a form of multiprocessing. A multicore processor has multiple cores(!) in the same processor (same die, or same module). This means they usually share L3 and L2 cache, and are more tightly coupled than processors in different sockets.

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2015, 02:14:05 pm
content: Quote from: andersm on December 20, 2015, 01:15:11 pmeverything! I do not know anything about SMP, nor hw, nor sw

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2015, 02:31:01 pm
content: Quote from: andersm on December 20, 2015, 01:15:11 pmI am playing with an SMP dual cpu module, 2xR12K processors (MIPS4, 64bit, they are not cores, they are physical chips, two R12K chips), and it uses a completely different method to "pass" commands between CPU0 and CPU1, it's different from e500 quadri-core.I do not know which kind of atomic instructions are used, e.g. 68000 uses TaS, Test and Set, as read-modify cpu-cycle, I do not know about the cache coherency algorithm. Snoop protocol ? just heard in my computer science course, 4 years ago, what else is used?and what about coherency algorithms ? I have found the following list in my R12K handbook, while linux implements and uses the 5th, cacheable, coherent, write-back, exclusive on write, sharable (even if … on my board it's not working at all)Code:/** MIPS3_TLB_ATTR (CCA) values - coherency algorithm:* 0: cacheable, noncoherent, write-through, no write allocate* 1: cacheable, noncoherent, write-through, write allocate* 2: uncached* 3: cacheable, noncoherent, write-back (noncoherent)* 4: cacheable, coherent, write-back, exclusive (exclusive)* 5: cacheable, coherent, write-back, exclusive on write (sharable)* 6: cacheable, coherent, write-back, update on write (update)* 7: uncached, accelerated (gather STORE operations)*/

author: helius
author_rank: Super Contributor
timestamp: December 20, 2015, 03:26:56 pm
content: MIPS uses LL/SC for atomic sections (Load Locked/Store Conditionally). A basic hardware mutex.algorithm #5 looks like a "MOSI"/"MESI" scheme, this is the most common for quite a while.I expect this stuff is covered in "See MIPS Run".

author: andersm
author_rank: Super Contributor
timestamp: December 20, 2015, 03:39:11 pm
content: Any decent college-level computer architecture textbook should explain the concepts.Hennessy & Patterson'sis one of the best-known.Like eg. ARM and POWER, MIPS implements atomic operations using load-linked/store-conditional pairs. An easy way to see them in action is to use GCC's built-in atomics and looking at the disassembly.

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2015, 05:38:39 pm
content: and what about the above coherency algorithms ?

author: andersm
author_rank: Super Contributor
timestamp: December 20, 2015, 10:32:38 pm
content: They will also be explained, or at least you will be better able to understand the documentation. Note that the meaning of the field is implementation-defined, and eg. the R10K manual has a substantially different list (the manual also has descriptions of the different caching algorithms.)

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2015, 11:21:10 pm
content: @andersmwhich is your practical personal experience with MIPS?SGI ? Atheros ?

author: legacy
author_rank: Super Contributor
timestamp: December 21, 2015, 08:45:36 pm
content: implementing smp properly on mips platform

author: legacy
author_rank: Super Contributor
timestamp: December 21, 2015, 09:38:52 pm
content: bookscaches

author: rsjsouza
author_rank: Super Contributor
timestamp: December 21, 2015, 10:05:19 pm
content: Years ago I learned something about SMP from one of Tom Shanley's books:Pentium Pro Processor System Architecture. I am not sure if it is really good or not, I just got the information I wanted at the time.

author: daybyter
author_rank: Frequent Contributor
timestamp: December 21, 2015, 10:19:15 pm
content: Maybe read some OpenCL tutorial?