VHDL: Comparing an integer and a std_logic_vector - Page 1
Forum section: electronics / general

author: Pack34
author_rank: Frequent Contributor
timestamp: September 16, 2015, 07:33:45 pm
content: Here's my situation. I'm reading in values over I2C and trying to set some switches in a top level process to configure a device.To do so, I'm reading in values over I2C and storing them in a std_logic_vector array. Then when I've read in the complete signal I throw a flag and trigger a process in my top_level file. This all seems to work, but when I attempt to compare this read-in value to some integer constants to then set my configuration I keep getting lots of errors, such as:Type error near setting ; current type integer; expected type std_logic_vectorWhen looking up my issue on the internet, the functions TO_INTEGER(UNSIGNED( ... )) keeps popping up as a solution but it just won't pass the compiler. I get the following errors:ERROR:HDLCompiler:432 - Line 982: Formal <arg> has no actual or default value.ERROR:HDLCompiler:541 - Line 982: Type integer is not an array type and cannot be indexed.ERROR:HDLCompiler:1690 - Line 982: This construct is only supported in VHDL 1076-2008Does anyone know what I can do to solve this? I'm completely stumped.

author: AndyC_772
author_rank: Super Contributor
timestamp: September 16, 2015, 07:53:55 pm
content: Have you tried:IF vector = CONV_STD_LOGIC_VECTOR (constant_integer, width) THEN...orIF CONV_INTEGER (vector ) = constant_integer THEN

author: Pack34
author_rank: Frequent Contributor
timestamp: September 16, 2015, 08:14:56 pm
content: Neither compile for me.I've resorted to writing my own function. But I'm getting syntax errors that seem to kick off on the first ":=" operator in the first IF statement.Code:function slv16_to_int (slv16_in: std_logic_vector(15 downto 0))return integer isvariable Rolling_sum_s : integer;beginRolling_sum_s := 0 ;if slv16_in(0) := '1' thenRolling_sum_s := Rolling_sum_s + 1 ;end if;if slv16_in(1) := '1' thenRolling_sum_s := Rolling_sum_s + 2 ;end if;if slv16_in(2) := '1' thenRolling_sum_s := Rolling_sum_s + 4 ;end if;if slv16_in(3) := '1' thenRolling_sum_s := Rolling_sum_s + 8 ;end if;if slv16_in(4) := '1' thenRolling_sum_s := Rolling_sum_s + 16 ;end if;if slv16_in(5) := '1' thenRolling_sum_s := Rolling_sum_s + 32 ;end if;if slv16_in(6) := '1' thenRolling_sum_s := Rolling_sum_s + 64 ;end if;if slv16_in(7) := '1' thenRolling_sum_s := Rolling_sum_s + 128 ;end if;if slv16_in(8) := '1' thenRolling_sum_s := Rolling_sum_s + 256 ;end if;if slv16_in(9) := '1' thenRolling_sum_s := Rolling_sum_s + 512 ;end if;if slv16_in(10) := '1' thenRolling_sum_s := Rolling_sum_s + 1024 ;end if;if slv16_in(11) := '1' thenRolling_sum_s := Rolling_sum_s + 2048 ;end if;if slv16_in(12) := '1' thenRolling_sum_s := Rolling_sum_s + 4096 ;end if;if slv16_in(13) := '1' thenRolling_sum_s := Rolling_sum_s + 8192 ;end if;if slv16_in(14) := '1' thenRolling_sum_s := Rolling_sum_s + 16384 ;end if;if slv16_in(15) := '1' thenRolling_sum_s := Rolling_sum_s + 32768 ;end if;return Rolling_sum_s;end function slv16_to_int;

author: Pack34
author_rank: Frequent Contributor
timestamp: September 16, 2015, 08:35:08 pm
content: I'm not sure why it didn't like the comparison opperator, but switching it to > '0' seemed to fix it.Now that I've implemented the function, added it to my top level code I get the following error:ERROR:HDLCompiler:1690 - Line 982: This construct is only supported in VHDL 1076-2008Checking the design properties and the CHDL Source Analysis Standard is set to VHDL-200X.... This is tarting to get frustrating...

author: AndyC_772
author_rank: Super Contributor
timestamp: September 16, 2015, 09:19:36 pm
content: := is the operator for variable assignment, it doesn't mean comparison. The comparison operator is just an = on its own.Don't forget to include the standard libraries at the start of your code:library IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.all;USE IEEE.std_logic_arith.all;

author: Bassman59
author_rank: Super Contributor
timestamp: September 16, 2015, 11:24:36 pm
content: Quote from: AndyC_772 on September 16, 2015, 09:19:36 pmor, less obsoletely,library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;

author: nctnico
author_rank: Super Contributor
timestamp: September 17, 2015, 05:49:03 am
content: I agree. I suggest using signed and unsigned types instead of std_logic_vector and casting later on. In my experience these cause less hassle with casting/conversion/mathematic operations.

author: Pack34
author_rank: Frequent Contributor
timestamp: September 17, 2015, 01:30:03 pm
content: Just to provide some clarity, the issue compiling seemed to be related to where I was using these functions and not the functions themselves.The initial configuration that was changing was using with/select statements and it seems that the compiler just didn't like them with the function being called inside the with statement. I ended up moving everything to a couple if statements and the code seems to be running fine, just need to update a test bench to verify. The actual error thrown by the compiler was odd and was leading me to verify the version of VHDL I was using but restructuring my code fixed it.With/Selecthttp://www.sigasi.com/content/signal-assignments-vhdl-withselect-whenelse-and-caseAs for signed and unsigned instead of std_logic_vector, is there a downside to just switching everything over? And for bit arrays there's no issue? Are there specific circumstances that it would be desired to use std_logic_vector over std_logic_unsigned?

author: Scrts
author_rank: Frequent Contributor
timestamp: September 17, 2015, 04:06:39 pm
content: Quote from: AndyC_772 on September 16, 2015, 09:19:36 pmNo nO NOOOO!Use numeric_std only!

author: AndyC_772
author_rank: Super Contributor
timestamp: September 17, 2015, 05:06:24 pm
content: Why?

author: nctnico
author_rank: Super Contributor
timestamp: September 17, 2015, 08:22:58 pm
content: With the libraries you mentioned you need to choose between having VHDL treat a std_logic_vector as signed or unsigned. Want to mix signed and unsigned? You are out of luck. Want to use a std_logic_vector signal as an array index? You need to cast it first. These problems largely go away with numeric_std.

author: AndyC_772
author_rank: Super Contributor
timestamp: September 18, 2015, 07:38:04 am
content: OK, I'll take a look and see if it's worth migrating. Thanks.