hybridfree/eevblog-posts huggingface dataset:
Xilinx ISE implementation stage issues - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: June 19, 2021, 03:20:03 pm
content: Could anyone help with theseries bufferandmultiple driversissues ?

author: hamster_nz
author_rank: Super Contributor
timestamp: June 20, 2021, 12:49:00 am
content: Possibly could, but could you post text and code rather than a link to an Instagram image? It's unusable on a phone...

author: promach
author_rank: Frequent Contributor
timestamp: June 20, 2021, 01:21:45 am
content: Did you not click the two github links instead of the picture ?

author: hamster_nz
author_rank: Super Contributor
timestamp: June 20, 2021, 02:34:03 am
content: Quote from: promach on June 20, 2021, 01:21:45 amNope, if I couldn't read the image to find out what is wrong why would I bother to go hunting without what is the most likely the most pertinent info?

author: promach
author_rank: Frequent Contributor
timestamp: June 20, 2021, 04:16:39 am
content: user_desired_extra_read_or_write_cyclesis not differential signal, why does the tool complain aboutIBUFDS?

author: promach
author_rank: Frequent Contributor
timestamp: June 22, 2021, 02:17:48 am
content: Seehttps://forums.xilinx.com/t5/Implementation/Xilinx-ISE-implementation-stage-issues/m-p/1255508/highlight/true#M30716
Simulating Gowin IP cores - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 20, 2021, 07:48:06 am
content: Hi,After several contacts with gowin about simulating their IP cores, these are the latest answers that I got from them, so The question is how to apply for modelsim simulation,

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 21, 2021, 05:55:46 am
content: what can we do, any Idea?

author: Bassman59
author_rank: Super Contributor
timestamp: June 21, 2021, 10:29:29 pm
content: Quote from: ali_asadzadeh on June 21, 2021, 05:55:46 amAssuming you have the source for their cores, simply compile them into the correct library.If you do not have the source, just the compiled library, you add the library to the list of visible libraries in your project, generally with the vlib command.
FPGA prices WTF - Page 1
Forum section: electronics / general

author: c64
author_rank: Frequent Contributor
timestamp: June 19, 2021, 12:42:09 am
content: I used to buy Cyclone 4 EP4CE6E22 for under 20 CNY on taobao. Last time I bought in December.Now the cheapest I can find is 60 CNY.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 19, 2021, 12:47:13 am
content: Have you heard of semiconductor shortage?

author: KE5FX
author_rank: Super Contributor
timestamp: June 19, 2021, 12:57:00 am
content: We're paying $200 for low-end Artix-7 FPGAs that normally cost about $60.Welcome to the new normal, I guess.

author: c64
author_rank: Frequent Contributor
timestamp: June 19, 2021, 01:05:57 am
content: Quote from: SiliconWizard on June 19, 2021, 12:47:13 amDoes it apply to older chips as well?

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 19, 2021, 01:12:52 am
content: Quote from: c64 on June 19, 2021, 01:05:57 amThe question is whether those chips you buy are old stock or if some chinese fab still produces them. I do not know.But even if those are just old stock, I wouldn't be surprised if sellers upped their prices just to follow the trend.

author: NorthGuy
author_rank: Super Contributor
timestamp: June 19, 2021, 02:05:39 am
content: Quote from: KE5FX on June 19, 2021, 12:57:00 amWhere do you buy them? They seems to be out of stock everywhere.

author: KE5FX
author_rank: Super Contributor
timestamp: June 19, 2021, 02:19:18 am
content: Quote from: NorthGuy on June 19, 2021, 02:05:39 amAre you sure you wouldn't rather know the neutron-capture cross section for uranium 235, the true origin of the SARS-CoV-2 virus, or what WD-40 isreallymade from?

author: NorthGuy
author_rank: Super Contributor
timestamp: June 19, 2021, 02:42:48 pm
content: Quote from: KE5FX on June 19, 2021, 02:19:18 amProtecting your liaisons, eh.Who would believe that it's possible to move from money-driven marketplace to liaisons-driven marketplace so quickly.

author: KE5FX
author_rank: Super Contributor
timestamp: June 19, 2021, 08:01:06 pm
content: No, just not authorized to share what suddenly amounts to privileged business information.It would ruffle some feathers.In all seriousness, Worldway still lists many 7-series parts, but our EMS facility refuses to use them along with quite a few other Far East brokers. If you're feeling lucky and/or desperate, you might try them.
Looking for resources, FIR filter design / coding - Page 1
Forum section: electronics / general

author: AussieBruce
author_rank: Regular Contributor
timestamp: June 30, 2021, 07:44:29 am
content: I want to implement a FIR LP filter in verilog. Is anyone aware of a free or economical resource for designing these and generating verilog code? I'd love to have the Matlab toolkit but the other half isn't too keen on the cost (this is a hobby venture).

author: BrianHG
author_rank: Super Contributor
timestamp: June 30, 2021, 11:27:56 am
content: Trywww.opencores.org.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 30, 2021, 11:55:32 am
content: https://zipcpu.com/dsp/2017/09/15/fastfir.html

author: asmi
author_rank: Super Contributor
timestamp: June 30, 2021, 01:40:36 pm
content: I don't know what FPGA are you planning to use, but I know for sure that both Xilinx and Altera IDE have free IP cores for these filters. Take a look at them and see if you can employ them.
Newbie looking for advice on small glue logic in CPLD/FPGA/... - Page 1
Forum section: electronics / general

author: softfoot
author_rank: Contributor
timestamp: June 11, 2021, 09:53:24 am
content: Hi, I need to put together a small microprocessor based controller that needs to be as small as possible, 5V based with some fairly complex external logic so I am thinking about a CMOS Programmable Logic Array (or such) that can be repeatably reprogrammed during development. I am probably talking about a 24 or max 32 pin package.It would need maybe 10 latches and 20 gates.I have considerable knowledge in electronics but not with these devices and want to gain some experience in using these, but the only thing is I am on a tight budget so free development and programming software is essential.Advice on programming hardware (cheap) is also neededCan anyone recommend a manufacturer/devices/programmer that meets this need ??I am happy with github/sourceforge software or free manufacturers tools.TIADave

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: June 11, 2021, 10:17:42 am
content: Have you looked at Cypress Psoc to integrate the logic and MCU?Lattice XO2 may be an option. Note the Lattice CPLDs need software that is no longer freeIf you really need 5V in & out, Atmel/Microchip ATV750 or ATV2500 might be worth a look.

author: Someone
author_rank: Super Contributor
timestamp: June 11, 2021, 01:04:07 pm
content: Quote from: evb149 on June 11, 2021, 10:38:44 amAbsolutely, along with the PSOC some of the modern Microchip (Atmel) parts have programmable asynchronous "events" that provide rich interconnect between not just pins and hardware peripherals but also to/from LUTs and registers. Sadly not much in the way of 5V parts there either! Finding the right micro with the perfect matching capabilities is some what of a task, but probably easier than finding 5V programmable logic

author: TomS_
author_rank: Frequent Contributor
timestamp: June 14, 2021, 06:37:58 am
content: Too much logic for something like a GAL, but should easily fit inside a small CPLD. Unless you were ok with multiple GALs...5V kind of limits the options. Altera and Xilinx had 5V products, but at least Altera doesn't produce them any more so you are stuck buying them second hand or new old stock if you are lucky enough. The EPM7000 series can be programmed in VHDL or Verilog and start from 32 macrocells in 44 pin packages.Atmel has a current 5V product line in the ATF150x family of devices which you can still purchase new. They are so similar to the EPM7000 parts that you can translate the design from Altera to Atmel using a free tool. Alternatively you can use WinCUPL to design the logic.
LFSR toggle rate? - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: June 21, 2021, 12:48:38 pm
content: I am using a LFSR that toggles one DFFs per clock cycle.Does this mean the toggle rate is:=1/total number of DFFsI am using a power estimation tool to figure out the dynamic power consumption.

author: cruff
author_rank: Regular Contributor
timestamp: June 23, 2021, 12:11:53 am
content: Unless something is unusual about it, all of the DFFs in the LFSR will toggle each clock cycle, unless you are gating the clock somehow.

author: steamedhams
author_rank: Regular Contributor
timestamp: June 23, 2021, 03:04:27 pm
content: Depends on the input though, if it is just passing a 1, then only 1 DFF should toggle each clock cycle as it passes through the chain.

author: rstofer
author_rank: Super Contributor
timestamp: June 23, 2021, 03:49:03 pm
content: I would hope that the XOR terms are clocked as well. Otherwise the chain is simply a shift register.Every schematic of an LFSR I have ever seen has all flops clocked simultaneously. I suppose it could be done some other way but why?

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 23, 2021, 05:05:59 pm
content: Additional thought.I suppose what the OP means by "a DFF not toggling" is that its output doesn't change state on a given clock cycle.I won't get into the implementation of a LFSR, but I'll just elaborate on the above point.Since, as someone said above, in a typical FPGA, all DFFs in your design (except if you managed to explicitely clock gate them, which is either not exactly possible or not guaranteed depending on said FPGA) will be clocked, what matters here IMO is down to the number of transistors that make up a DFF, and the number of them that will switch even when the output doesn't change state. You can refer to this basic design:https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#/media/File:True_single-phase_edge-triggered_flip-flop_with_reset.svgfor starters.
Some notes on building nextpnr on Mac - Page 1
Forum section: electronics / general

author: Omega Glory
author_rank: Regular Contributor
timestamp: June 03, 2021, 07:08:38 pm
content: I recently attempted to build nextpnr with its GUI on Mac, and ran into some issues with cmake not being able to find qt5. Assuming you have installed qt5 with homebrew, you can get things to build by running:QuoteFor some reason lots of people have this issue with qt5 and homebrew, but it took hours to find the solution. I thought I would post it here in case anyone else was trying to build an open source FPGA flow on Mac and had similar issues.Edit:Additionally mac users may encounter a linking error with the tbb library. This can be fixed by changing a line in the CMakeLists.txt file, changing:QuotetoQuote
generate SPI in verilog - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 01, 2021, 09:04:59 am
content: Hi,I have a 16Bit SPI master and I need to generate 9 of them,Here is my codeCode:wire wStart , wAdcDv;wire [15:0] wAdcData [8:0];// The for-loop creates 9 ADC statementsgenvar i;generatefor (i=0; i < 9; i = i + 1) beginSPI_Master SPI(.i_Clk(i_Clk50MHz),.i_Rst(1'b0),.i_start(wStart),.o_RXData(wAdcData),.o_DV(wAdcDv),.o_Busy(),//physical pins.i_MISO_pin(i_AdcSdo),.o_SCLK_pin(o_AdcSck));endendgenerateISE would complain aboutQuoteWhat am I doing wrong?

author: dtodorov
author_rank: Contributor
timestamp: June 01, 2021, 09:09:51 am
content: Not sure if it can help, but maybe you can try to explicitly defineCode:wire [8:0] o_AdcSck;

author: BrianHG
author_rank: Super Contributor
timestamp: June 01, 2021, 09:34:57 am
content: Quote from: ali_asadzadeh on June 01, 2021, 09:04:59 amUsually this means that somewhere else in your code, you have set or assigned 'AdcSck <=' to something. You cannot set 2 different values to the same IO pin or logic cell.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 02, 2021, 05:55:12 am
content: QuoteThanks, Stupid me, I have some typo in somewhere else

author: BrianHG
author_rank: Super Contributor
timestamp: June 02, 2021, 08:37:46 am
content: Quote from: ali_asadzadeh on June 02, 2021, 05:55:12 amBeen there, done that who knows how many times.Also, it took a few times seeing that same error message in Quartus before I knew what to look for every time it shows up.
Anyone has diagram for Cyclone IV demo board (link to image inside)? - Page 1
Forum section: electronics / general

author: IAmBack
author_rank: Regular Contributor
timestamp: May 26, 2021, 06:25:41 pm
content: A need a diagram for this one:https://pl.aliexpress.com/item/32535007308.htmlNot very complicated item, but I prefer diagram over checking with meter where are leds and buttons connected...Regards.Martin
2nm Chips - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: May 08, 2021, 12:59:59 pm
content: IBM has done it, any Idea what we could achieve with that?

author: woofy
author_rank: Frequent Contributor
timestamp: May 08, 2021, 03:35:22 pm
content: That's around 10 atoms. Amazing!

author: NorthGuy
author_rank: Super Contributor
timestamp: May 08, 2021, 03:53:45 pm
content: Quote from: ali_asadzadeh on May 08, 2021, 12:59:59 pmMore bloat.

author: ataradov
author_rank: Super Contributor
timestamp: May 08, 2021, 04:46:05 pm
content: We can achiever that as soon as any marketing person gets on the job.Their "nm" numbers are meaningless anymore. They just redefine what they measure to make numbers lower.

author: woofy
author_rank: Frequent Contributor
timestamp: May 08, 2021, 05:31:30 pm
content: Transistor density may be a better metric.Intel's 10nm node is about 100m transistors/mm2TSMC's 10nm node is 52m transistors/mm2and their 7nm node is 91m transistors/mm2So Intel's 10nm node is denser that TSMC's 7nm node.IBM's 2nm node is around 330m transistors/mm2

author: SiliconWizard
author_rank: Super Contributor
timestamp: May 09, 2021, 05:14:51 pm
content: Quote from: NorthGuy on May 08, 2021, 03:53:45 pmWhile nothing prevents us from using technology in a wise and efficient way, doing so doesn't seem to be our favorite indeed.That said, I wonder how things like leakage, heat management and even reliabilty are handled at this density.

author: bson
author_rank: Unknown
timestamp: May 30, 2021, 03:09:09 am
content: Quote from: ataradov on May 08, 2021, 04:46:05 pmIs it ever anything other than channelwidthlength? This of course is a key property.

author: BrianHG
author_rank: Super Contributor
timestamp: May 30, 2021, 03:22:12 am
content: Are there any density specs on TSMC's new 1nm node?
Vivado:  inferred exception to break timing loop: 'set_false_path -through ...' - Page 1
Forum section: electronics / general

author: hermitengineer
author_rank: Regular Contributor
timestamp: May 25, 2021, 02:01:17 am
content: Trying to track down the source of this warning. The full message is:[Synth 8-326] inferred exception to break timing loop: 'set_false_path -through i_48/i_54/O'The problem is, no search parameters turn up the above path component. How can I find the offending item(s)? (there are 14 of these warnings, each with a slightly different instance).
Alternative to system generator Xilinx Fpga - Page 1
Forum section: electronics / general

author: rakeshm55
author_rank: Regular Contributor
timestamp: June 02, 2021, 03:36:39 pm
content: I frequently use Xilinx FPGAs in our Projects.For signal processing application we make use of System generator + Matlab combo. This has been our traditional approach. We would like to have some open source alternative that can replace this Combo. Is there any tool chain we can adopt for replacing the combo? A tool chain that can finally generate HDL code that can be used with VivadoIt has become increasingly costly to update our Matlab licence every year?. How do other organization manage? What are available low cost approaches

author: RoGeorge
author_rank: Super Contributor
timestamp: June 02, 2021, 04:00:30 pm
content: Instead of Matlab there is Octave: free, open source, and Matlab compatible.Xilinx ISE or Vivado are proprietary, they do not have open source alternatives.I don't know to recommend a Matlab to HDL tool for signal processing, but I suspect there should be plenty if you do a search for "Octave to HDL DSP".

author: rakeshm55
author_rank: Regular Contributor
timestamp: June 03, 2021, 04:51:19 am
content: Quote from: RoGeorge on June 02, 2021, 04:00:30 pmI am not looking to replace ISE or Vivado. My intention was to adopt a design flow that is capable of generating synthesizable HDL for signal processing blocks/Signal processing design. I can easily port this design to Vivado.I have heard of Scilab => C code generate => finally Vivado HLSDont know how suitable these approaches are. Usually our Signal processing components consume 600+ DSP slices. Does any opensource framework/tool support such intensive development
Looking for advice on PAL/GAL programmer - Page 1
Forum section: electronics / general

author: eda8039
author_rank: Newbie
timestamp: May 22, 2021, 12:56:11 am
content: I'm interested in using some surplus PALs/GALs I have. So, I'm looking for a programmer that can handle a variety of PAL/GAL/CPLD devices.I'd want one that has a USB interface and works with Windows 10.I'd welcome all suggestions.

author: TomS_
author_rank: Frequent Contributor
timestamp: May 24, 2021, 04:54:32 am
content: TL866 II+ has quite an extensive list of supported devices, including many GALs (which also includes the modern and still in production Atmel ATFxxVxx parts).You would need to check the list for PAL and CPLD support.

author: joeqsmith
author_rank: Super Contributor
timestamp: May 24, 2021, 10:43:24 am
content: I bought one of those super low cost 866 programmers to try out. In some cases I've had to resort to selecting the wrong part to get it to program. In many cases it doesn't support the parts I use. I think the first part I tried was a 22V10 and ran into problems. No support for the old Altera and Xilinx serial proms. Same for the Atmel. Was going to use it to read an old 4-bit PROM out of a DMM I was working on, again, no support.Someone posted about a mid grade programmer that looked pretty decent.https://www.eevblog.com/forum/testgear/some-old-school-instruments-showing-how-its-done-(hp-3325a-and-fluke-8506a)/msg3473924/#msg3473924
Does an SPI to AXI Lite interface exist? - Page 1
Forum section: electronics / general

author: Boscoe
author_rank: Frequent Contributor
timestamp: May 18, 2021, 08:10:14 am
content: Hi all,I'm capable of writing such a thing but I'd like to stick to proven IP.I have some DMA IP inside an FPGA that requires configuring over AXI4-Lite. The FPGA does not have a hard processor and I'd rather not add a soft core which adds complexity to the FPGA design and addsanothersoftware project.I have a big/fast external MCU that I'd like to be able to access the internal FPGA AXI4-Lite bus for low throughput configuration steps without using all of the pins on the FPGA! Does anyone know of such a core? I have looked through Xilinx's catalog and through open cores but come to nothing.ThanksBoscoe

author: langwadt
author_rank: Super Contributor
timestamp: May 18, 2021, 08:17:27 am
content: close enough?https://github.com/ultraembedded/core_dbg_bridge

author: Boscoe
author_rank: Frequent Contributor
timestamp: May 18, 2021, 09:33:55 am
content: Looks great, thank you!
Altera on board USB blaster - Page 1
Forum section: electronics / general

author: Wiljan
author_rank: Regular Contributor
timestamp: May 23, 2021, 01:12:34 pm
content: I have a Cyclone V GT FPGA Development Boardhttps://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.htmlThe board had a broken MAX II and MAX V due to some short circuit some years ago and the MAX II and MAX V did short the voltage reg.The 2 chips was removed and all voltage went back to normal and the Cyclone V does work fine but need to be programmed with a external USB blaster, again that works fine...BUT it's very slow (JTAG) compared to the on-board Blaster (which does load in parallel).Link for schematic (page 19 shows the On-Board USB Blaster II)https://www.analog.com/media/en/technical-documentation/eval-board-schematic/c5gt_pcie_b.pdfSo I have got a new MAX II chip which I have soldered to the dev board and when using the USB cable to the board windows does recognize the uP which are on the dev board as USB interface the MAX II.So my question is... how is the MAX II programmed on the dev board?Is that done automatic via the USB driver and via the uP or does the it need to be programmed via JTAG somehow?In the dev board files there are images for the MAX V and the Cyclone but nothing for the MAX II or the uP CY7C68013A, it might be proprietaryHope it makes sense

author: aandrew
author_rank: Frequent Contributor
timestamp: May 24, 2021, 03:44:58 pm
content: It looks like the MAX II is programmed via the FX2LP (take a look at the lower-right corner of U49A and note how it runs to the FX2LP's PORTD pins.Altera/Intel have always kept the bitstream of the CPLD in their blasters proprietary, so it does not surprise me that you can't find it. I'm a little surprised that they don't have a way to update the bitstream "in the field"; you may need to contact your rep to see if they can share a tool to do so.On my own MAX10 designs I have included an FTDI FT2232 and use a specific config image for the FTDI. Along with a binary PC library that Arrow had provided, this allows me to have an on board JTAG tool which Quartus recognizes. This is great because I can use SignalTap without having to use an external debugger.

author: Wiljan
author_rank: Regular Contributor
timestamp: May 24, 2021, 05:02:46 pm
content: @ aandrew yes I did notice the JTAG connection between the MAX II and the FX2.So either a bitstream and a soft for the PC are required rto flash the MAX II onceOr the USB driver just download the bitstream each time it's loadedOr the FX2 (CY7C68013A) does have it in the flash and push it to the MAX III have DECA dev board as well and did see in the schematic that it's done with the same FX2 but a MAX V instead.I could try to look on the JTAG there and see is they push something on each power-cycleSure it could be worth to ask Intel for a solution
tRAS definition for DDR memory - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: February 13, 2021, 10:22:14 am
content: In Figure 3 ofhttps://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh, whytRASis defined as the max timing between two REFRESH commands ? This seems contradicts with Micron document.

author: AndyC_772
author_rank: Super Contributor
timestamp: February 13, 2021, 11:46:38 am
content: The Micron data sheet is for a DDR3L device, but the System Verilog spec is talking about a feature added to DDR4.Are you sure you're comparing like with like?

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 16, 2021, 06:21:41 pm
content: Yes this isn't the same type of memory. But I can't see any mention of "tRAS" in figure 3 of the page you mention anyway?

author: asmi
author_rank: Super Contributor
timestamp: February 16, 2021, 07:20:54 pm
content: 9 * tREFI isthe upper boundof tRAS, basically it's the absolute maximum time a row can be held open. 9 * REFI is because of this:Quote

author: promach
author_rank: Frequent Contributor
timestamp: February 17, 2021, 04:37:48 pm
content: @asmi but Micron document definestRASas the timing betweenACTIVATEcommand andPRECHARGEcommand.@SiliconWizard look at the Micron document on the left of the picture

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 17, 2021, 04:45:30 pm
content: Quote from: promach on February 17, 2021, 04:37:48 pmtRAS is mentioned in the Micron DS, not on the figure you mention. At least not directly. So that was confusing. And I think you got confused too.asmi gave you the answer. max tRAS is 9xtREFI, just because a longer tRAS would violate the refresh requirements. So that's not contradictory.

author: promach
author_rank: Frequent Contributor
timestamp: February 17, 2021, 05:35:06 pm
content: QuoteCould you be more SPECIFIC on which exact refresh requirements ?

author: asmi
author_rank: Super Contributor
timestamp: February 17, 2021, 05:39:26 pm
content: Quote from: promach on February 17, 2021, 04:37:48 pmYep. The row is opened by ACTIVATE command and stays open until you issue PRECHARGE command (either explicitly, or implicitly via auto-precharge flag of read/write commands). Since you need to precharge all rows before you can issue a REFRESH command, the maximum allowed interval between refresh commands places an upper bound on how long the row can stay open.

author: promach
author_rank: Frequent Contributor
timestamp: February 18, 2021, 12:38:22 am
content: there should be a value inside theMAXcolumn fortRCfor the Micron document though ?When I searched online abouttRC, why the following mentioned that noPRECHARGEis allowed in between ?

author: promach
author_rank: Frequent Contributor
timestamp: May 13, 2021, 09:46:50 am
content: how shall I understand Figure 4 ofhttps://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh?if there are 8 REF-Commands postponed, then it should be 7 x tREFI instead of 9 x tREFI
Pin like interruption on Altera FPGA - Page 1
Forum section: electronics / general

author: marcelogadotti
author_rank: Newbie
timestamp: May 11, 2021, 07:49:12 pm
content: Is there any way to emulate MCU interruption on FPGA using VHDL?My application needs a high response time, sending the modification of the pin status to the UART.

author: Bassman59
author_rank: Super Contributor
timestamp: May 11, 2021, 09:28:11 pm
content: Quote from: marcelogadotti on May 11, 2021, 07:49:12 pmLogic can respond to a change in a signal -- an "interrupt" -- pretty much immediately.

author: marcelogadotti
author_rank: Newbie
timestamp: May 12, 2021, 06:22:46 pm
content: I think I will use AND logic to check any pin change and trigger an UART event to send the value, like interruptions.

author: Palmitoxico
author_rank: Regular Contributor
timestamp: May 12, 2021, 10:02:04 pm
content: The concept of interrupts only makes sense when we are talking about something executing code. FPGAs typically don't execute 'code', unless you are implementing a MCU softcore into it.

author: hamster_nz
author_rank: Super Contributor
timestamp: May 13, 2021, 05:54:10 am
content: The UART will be much slower than the FPGA, so you run a risk of missing transitions, or at least introducing latency.Consider time stamping the events at putting them into a FIFO to be streamed through the UART.Oh, and pay due attention.to synchonizing and debouncing your inputs.
Pin assignment in SoC - Page 1
Forum section: electronics / general

author: moonz
author_rank: Contributor
timestamp: May 17, 2021, 11:46:03 am
content: Hello everyone, I study circuit SoC (for example Cyclone V).I'm a little confused about the pin assignment. Let's take a IC Cyclone V 5CSEBA2(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/5cseba2.pdf) for example.Do I understand correctly, that the HPS pin are indicated in the columns HPS Pin Mux Select 0..4, only owned by HPS? Or can they also be attributed to FPGA functions?I also want to clarify, I understand correctly that the DDR memory controller for HPC and FPGA is common and, as a result, the pin are also common. Is this a correct statement?Can you please tell me what is the purpose of the column for VREF?Thanks in advance!

author: ejeffrey
author_rank: Super Contributor
timestamp: May 17, 2021, 06:27:23 pm
content: Yes, the HPS pins are owned by the HPS and cannot be directly accessed by the FPGA fabric. The FPGA pins likewise are only accessible from FPGA fabric. You can really think of the whole system as two completely separate devices on the same die connected by an AXI bus. You can boot the HPS prior to loading a configuration bitstream onto the FPGA (which allows you to have the HPS program the image) or you can configure the FPGA before providing a boot image for the HPS (which allows the HPS to boot from an IO device present in the FPGA).I believe the model you are looking at does not have a hard memory controller in the FPGA fabric. The only memory controller is attached to the HPS and has dedicated pins reserved for it. You can tell by the 'B' in the part number that would be an 'F' if it has hard memory and PCIe controllers. So the FPGA cannot directly access DRAM.

author: moonz
author_rank: Contributor
timestamp: May 17, 2021, 07:09:48 pm
content: Quote from: ejeffrey on May 17, 2021, 06:27:23 pmFPGA has no direct memory access? I ask because I see figure 11 in the document:https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51001.pdfRefre by this diagram, both the FPGA and the processor have access to memory. Or are there mistakes in my reasoning?

author: Daixiwen
author_rank: Frequent Contributor
timestamp: May 18, 2021, 08:36:18 am
content: You are right, the FPGA fabric can directly access the SDRAM connected to the HPS SDRAM controller, through the FPGA-to-HPS-SDRAM interface. It can also use the FPGA-to-HPS memory mapped interface (on the left) to access any address in the HPS space, including peripherals and RAM.Some HPS pins can be accessed from the FPGA fabric, but their number is limited (32 total I think?) and don't expect high I/O timing performance from them. When you configure the HPS core in QSys, you can connect each HPS pin either to a hardware I/O controller inside the HPS (uart, spi, ethernet....), as a GPIO, or as connected to the FPGA fabric. In the latter case QSys will export a logic vector for you to use.
reading csv file for test-bench in verilog - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: April 27, 2021, 09:20:25 am
content: Hi,I have captured an SPI bus from a logic analyzer, and have saved the data in a csv file, Now I want to read the csv file in the test bench and input the data as stimulate signals to my DUT, how it should be done?I have done a simple task of reading plain text files with only one variable like this before,Code:reg [15:0] r_someData [0:1024];file1=$fopen("smoeData.txt","r");$fscanf(file1,"%d", r_someData );$fclose(file1);Please note that the csv file has multiple data on a single line, also the data is repeated 2 times because of the 2X sampling clock,How should I read multiple data from the csv file, and How should I apply the data to my DUT, because I want my DUT use exactly the i_clk and G_SCK from the input file, and I do not want to generate the clock from the code in test benchThe file is attached for your reference

author: dtodorov
author_rank: Contributor
timestamp: April 27, 2021, 02:33:00 pm
content: Hi,looking at the csv file, you have the formatCode:time unit: us, i_clk, G_MISO, G_SCK, G_MOSI, G_SS.Therefore you fscanf() should be a bit more complicated. Something like this:Code:for (i=0; i<2^16; i=i+1) beginr = $fscanf(file1,"%d, %d, %d, %d", t, s1, s2, s3 );endReading from a file with $fscanf() increments the file position index, thereby repeated $fscanf calls advance in the text processing. Depending on your CSV size, you may need to adapt the for(..) conditions.P.S. You may also youse while(..) loop and observe the result of the $fscanf(). I have named it "r" in the example and it will return a -1 upon EOF (end of file) condition. You may also just use $feof(file..); task.Hope that helps.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: April 28, 2021, 05:58:03 am
content: Thanks dtodorov for the tip.
Nandland go board with icestorm - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: April 29, 2021, 08:15:13 am
content: Has anyone successfully setup icestorm with the nandland go board?? I am unable to get it going.I think there is an issue with the constraints file... I know there is a video online of him doing it in 2016 but it needs an update.(Also, I am using nextpnr.)

author: Palmitoxico
author_rank: Regular Contributor
timestamp: May 05, 2021, 01:17:00 pm
content: I don't own a nandland's go board, could you be more specific about the issues you are experiencing? I can use yosys + nextpnr jut fine with my ICE40-HX8K board.
Vivado - strategies for resolving timing errors - Page 1
Forum section: electronics / general

author: JohnnyMalaria
author_rank: Super Contributor
timestamp: April 16, 2021, 11:07:35 pm
content: Hi,After a few weeks of developing an VHDL design that works as planned in the simulator, I now face my next new challenge - not meeting timing constraints. Although my design synthesizes okay (a miracle in itself), I'm getting timing issues as shown in the attached screenshot.These are all associated with a Xilinx FFT IP Core and its related DSP slices.Can you point me to some additional resources that explain strategies for understanding and solving these types of timing problems?Thanks.

author: asmi
author_rank: Super Contributor
timestamp: April 17, 2021, 03:09:08 am
content: There is no blanket rule applicable for all cases. Open failed paths' schematics and see what's going on there.In your case it looks like your failed paths contain a lot of levels of logic between FFs, you will probably want to pipeline such long logic chain. Also if you use DSP blocks, make sure you use internal pipeline registers (at the very least the one on the output side), or you will have huge routing delays.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 17, 2021, 09:08:23 am
content: What is the splt between logic delay and routing delay?Routing delays usually ends up as slightly more than logic delays and you can't make the logic run any faster.A reasonable assumption is that the current design, no matter how optimized, will never clock quicker than 2x the logic delays, unless heavily leveraging the underlying FPGA architecture.

author: NorthGuy
author_rank: Super Contributor
timestamp: April 17, 2021, 02:53:47 pm
content: You have too much combinatorial logic and this causes delays. You have 10 levels.There are 3 ways.1) Pipeline. That is, split your combinatorial logic, so that only few levels need to execute during the single clock. For example, instead of doing 10 levels in one clock, do 3, 3 and 4.2) Decrease your clock frequency. It doesn't run at 100 MHz, but should run at 40 MHz just fine.3) Re-think and change the design.

author: JohnnyMalaria
author_rank: Super Contributor
timestamp: April 17, 2021, 09:45:35 pm
content: Thank you all for your suggestions. I'm happy to report all timing constraints are now metMy design includes four Xilinx Multiplier IPs used to calculate the squares of the real and imaginary output from the FFT. I increased the level of pipelining from zero to 5.Another good learning experience.
Introducing delay between outputs on Max II CPLD - Page 1
Forum section: electronics / general

author: emptysamurai
author_rank: Newbie
timestamp: May 28, 2021, 11:00:22 am
content: Hi,I'm new to FPGA/CPDL design, but I'm trying to do the following. I want my EPM570 CPLD to act as a ring counter and demultiplexer that distributes incoming data to 8 connected devices sequentially. To do that I use ring counter as an output clock and pass data trough register to output. The problem is that connected device requires 0.5ns setup time and 1.5ns hold time. Is it possible to ensure this requirement, for example by writing constraint in Quartus?So far I wrote the following Verilog code (simplified):Code:module RingCounter(input clk,input rst,input data_in,output reg [7:0] counter,output reg data_out);always @(posedge clk)beginif (rst)counter <= {{7{1'b0}}, 1'b1};elsecounter <= {counter[6:0], counter};data_out <= data_in;endendmoduleAnd tried to add the following constraints:Code:create_clock -name clock -period 8.33 [get_ports {clk}]derive_pll_clocksset_output_delay -clock { clock } -reference_pin [get_ports {counter}] -min -0.5 [get_ports {data_out}]set_output_delay -clock { clock } -reference_pin [get_ports {counter}] -max 1.5 [get_ports {data_out}]But I got error:Code:Reference pin counter is invalid. It is not clocked by the clock specified in set_input_delay/set_output_delay's -clock option.

author: hermitengineer
author_rank: Regular Contributor
timestamp: June 03, 2021, 09:06:44 pm
content: Not an expert here, but I had trouble with assignment of a shift register using that idiom, even though I've seen it (or at least something similar) done before. If not using SystemVerilog, it failed. I replaced it with a for loop to assign each cell to its predecessor, then added one more assignment to rotate the last bit back to the first.Next, a synchronous always() block is typically associated with the production of a single logical element. I can't say for sure that it's wrong, but the data_out assignment is not related to setting the counter, and may be confusing the system. Maybe make it part of its own always block since it at least can be done independently.It's possible, I guess, that it might synthesize a delay to meet the constraints. Maybe by adding some gates for the outputs to filter through. For a full FPGA, I've also seen it create a maze of routing lines all over the chip in an attempt to meet a (mistakenly) large delay requirement. So yeah, once it's satisfied that your counter is clocked, it should be able to do something. But just a guess that the current code has created something that got optimized out.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: June 04, 2021, 06:38:19 am
content: You don't need the reference_pin argument, the tool will know how the signal is generated.There is a user made guide for timequest that gives a lot of good tips on how to constrain interfaces if you are interested:TimeQuest User Guide. It's a shame he never got to finish it. Section 1 has a chapter on how to get started with constraining an I/O interface.
48-bit unsigned integer to 32-bit IEEE-754 float for Xilinx 7-series (VHDL) - Page 1
Forum section: electronics / general

author: JohnnyMalaria
author_rank: Super Contributor
timestamp: April 14, 2021, 11:22:19 pm
content: Hi,I need to converted 48-bit unsigned integers to 32-bit IEEE-754 floating point format on a Zynq-based FPGA.The integers come from calculating the magnitude (hence unsigned) of a complex FFT using the Xilinx FFT IP. I want to transfer them to the PS via block RAM to do further numerical processing. Conversion to 32-bit float obviously reduces the RAM required by a third and saves the int-to-float conversion on the ARM processor.I am aware of the Xilinx Floating Point IP and that it can do conversion but, since I don't need to do any floating point arithmetic on the PL side, I was wondering if there is a simpler, more lightweight way in VHDL (not 2008).Thanks.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 14, 2021, 11:49:53 pm
content: Haven't looked at floating point for a long time, but you have two paths...x == zero: maps to floating point zerox > 0: shift left until a 1 drops off the end, and adjust the mantissa, might need to investigate rounding and corner cases too. The shifter might be a bit resource hungry.Maybe I'll write a little code to see if it works as I expect....

author: hamster_nz
author_rank: Super Contributor
timestamp: April 15, 2021, 12:34:23 am
content: Code checks out...Code:#include <stdio.h>#include <stdlib.h>#include <stdint.h>void u_to_f(uint64_t u, float *d) {int m = 128+48-1;uint32_t *p = (uint32_t *)d;if(u == 0) {*p = 0;return;}if((u>>(49-24)) == 0) {u <<= 24;m -= 24;}if((u>>(49-12)) == 0) {u <<= 12;m -= 12;}if((u>>(49-6)) == 0) {u <<= 6;m -= 6;}if((u>>(49-4)) == 0) {u <<= 4;m -= 4;}if((u>>(49-2)) == 0) {u <<= 2;m -= 2;}if((u>>(49-1)) == 0) {u <<= 1;m -= 1;}*p = (m<<23) + ((u >> 25)&0x7FFFFF);}int main(int argc, char *argv[]) {uint64_t u;for(int i = 0; i < 1000; i++) {u = rand() % 100000;float f = u;u_to_f(u, &f);printf("%10lu %10.1f %10.1f\n",u,(float)u, f);}}How to implement it in VHDL depends on your needs for throughput, latency, and so on.(and of course code is broken on machines with different endian).

author: JohnnyMalaria
author_rank: Super Contributor
timestamp: April 15, 2021, 12:41:51 am
content: Quote from: hamster_nz on April 15, 2021, 12:34:23 amThank you very much - it looks like I have a homework assignment for the weekend.
WinCUPL - need to create a 10ns delay - Page 1
Forum section: electronics / general

author: deanclaxton
author_rank: Regular Contributor
timestamp: February 15, 2021, 10:15:49 am
content: I need to delay an input for approx 10ns - one or two gate propogation delays. So far the things I've tried have been wiped out by the optimisation pass. I dont have a clock available.Does anyone have any WinCUPL examples on creating a small delay?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: February 15, 2021, 10:31:20 am
content: Depends what device you are targetting - if it's a simple GAL, the only way to put gates in series is to output the intermediate node on a pin

author: gnuarm
author_rank: Super Contributor
timestamp: February 23, 2021, 04:35:04 pm
content: Delays by running through logic usually indicate a problem in the design. But I will ignore that and simply point out delays in logic is typically not very typical. The delay has a wide range of variation over PVT (process, voltage and temperature). These delays are given as maximums, sometimes typical and very seldom as minimums. So if you still want to use a logic delay how to do that depends on the tool you are using. I'm not at all familiar with WinCUPL. There are often attributes to apply to a signal or to the logic creating the signal that will prevent optimization. I would need to look this up to be sure as the name doesn't always properly explain the operation. "Keep" is one that comes to mind.As Mike points out, this will in any event use a logic output, but I'm not sure it requires a pin. What device are you targeting? The more complex CPLDs often have internal logic terms that will do what you want.More importantly, what are you using the delay for?

author: apate26
author_rank: Newbie
timestamp: April 08, 2021, 07:07:11 pm
content: I am also looking for that because I have an RC circuit in the logic so that would be some delay I am expecting, but in the Wincupl I see there is no option for the delay, did you get the solution?ThanksAvi

author: gnuarm
author_rank: Super Contributor
timestamp: April 09, 2021, 12:12:20 am
content: Quote from: apate26 on April 08, 2021, 07:07:11 pmOf course there is no primitive for delay. How would you expect them to implement that? With a delay line?

author: deanclaxton
author_rank: Regular Contributor
timestamp: April 09, 2021, 03:57:30 am
content: I was able to delay a signal by passing it through a couple of registers. I was able to then XOR the delayed signal with its current state to produce a short pulse on pin change (this is without a clock present).Like this :PIN 30 = A0 ; /* A0 Input from Bus */PINNODE = Delay;PINNODE = DelayedA0;PINNODE = PulseA0;/* Create delayed A0 signal - A0 going high */Delay.d = 'B'1;Delay.ck = A0;Delay.ar = PulseA0;DelayedA0.d = 'B'1;DelayedA0.ck = Delay;DelayedA0.ar = !A0;/* Detect Change of A0 - XOR A0 with delayed A0 to produce a pulse on change of A0 low to high (low to high, high to low = also resets the delayed A0 signal */PulseA0 = A0 $ DelayedA0;Thanks for all the feedback - much appreciated
DDR sdc commands - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: April 04, 2021, 12:15:48 pm
content: Could anyone advise on1. Why useUFF0andUFF5in theset_multicycle_pathcommands ?2. Why use-divide_by 2,-edge {1 2 3}and-edge_shift {1.5 1.5 1.5}insidecreate_generated_clockcommands ?3. Why need two differentcreate_generated_clockcommands ?Quote
Intro using Xilinx Artix7 MIPI CSI IP - Page 1
Forum section: electronics / general

author: hal9001
author_rank: Regular Contributor
timestamp: March 30, 2021, 12:01:23 pm
content: How easy is it to get started with taking a picture from a csi camera using the Xilinx IP? Does the Ip actually configure the camera automatically and output data from the pixels without micro blaze?

author: hal9001
author_rank: Regular Contributor
timestamp: March 31, 2021, 09:03:41 am
content: Does any body know if there is a tutorial for the CSI IP?

author: asmi
author_rank: Super Contributor
timestamp: March 31, 2021, 01:30:06 pm
content: Have you read PG232? It should have all answers.

author: Scrts
author_rank: Frequent Contributor
timestamp: April 01, 2021, 12:00:04 pm
content: Quote from: hal9001 on March 30, 2021, 12:01:23 pmIn general: no. The image sensor must be configured separately, usually through I2C interface.
What is this board with ten Virtex FPGAs on it? - Page 1
Forum section: electronics / general

author: Bryce
author_rank: Contributor
timestamp: March 29, 2021, 11:56:04 pm
content: https://www.ebay.com/itm/284146993530I saw this on eBay while looking for FPGA things. This board has ten Virtex-6 FPGAs on it. Only one side is visible in the pictures, but I see no evidence of any off-chip RAM or any other high-speed interfaces. This is extremely curious to me - what on earth needs so many large FPGAs but has no high speed interfaces?My best guess is that it's maybe some kind of crypto miner, but I've never heard of a crypto miner using top-end FPGA families which are generally not cost effective. Of course, it's possible that these were obtained late in the 6th generation Virtex lifecycle cheaply and repurposed for this.Any other speculations?I kinda want to buy one to see if it yields more clues, but I'm holding back because I know that the chance that I will go to the trouble of spinning a new board to take advantage of an already old FPGA is pretty much nil, and I'd have to remove them from whatever this is first.

author: langwadt
author_rank: Super Contributor
timestamp: March 30, 2021, 12:31:48 am
content: for protyping an asic?

author: Bryce
author_rank: Contributor
timestamp: March 30, 2021, 02:00:39 am
content: Ah, okay, then that probably explains it - likely a crypto miner board.

author: Wiljan
author_rank: Regular Contributor
timestamp: March 30, 2021, 07:35:28 am
content: Maybe for a Brute Force project like thehttps://www.copacobana.org

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: March 30, 2021, 12:24:29 pm
content: Quote1800RMB is the right price?
lockup latch issue - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: April 15, 2021, 04:13:17 am
content: 1. Inhttps://vlsiuniverse.blogspot.com/2013/06/lockup-latches-soul-mate-of-scan-based.html, I am bit confused with the hold check and setup check waveform inside Figure 72. Inhttps://www.design-reuse.com/articles/37956/lockup-elements-the-timing-perspective.html, how does lockup latch solve hold timing issue in Figures 1, 2 and 3 ? Note: I was reading in one other edaboard thread that says lockup latch adds a half clock cycle to the hold timing check path ?

author: dtodorov
author_rank: Contributor
timestamp: April 15, 2021, 10:38:14 am
content: I did not get into the corner details of the articles, but I think this latch insertion is needed only for SCAN operations (e.g. during ATPG vectro scan-in/out). In such scan modes, the flip-flops are daisy-chained into a large shift register-like structure (reffered to as scan chain).Each scan FF has an input mux selecting normal data (comming from combo logic) or the output of the previous scan FF in scan mode.The problem is, that during scan mode, the test clock (which clocks the scan chain) is common, and this means timing paths now exist between domains which probably are irrelevant in normal (not scan) operation of the logic. These paths are likely to create setup/hold violations and tools will try to add balancing clock buffers, for instance.From what I understand, this article suggests that a latch is used instead to architecturally avoid timing path optimization.