hybridfree/eevblog-posts huggingface dataset:
Do you know why this code Keeps crashing! - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 01, 2020, 02:18:25 pm
content: Hi,This code Just keeps crashing in Gowin IDE,If I comment out one of the MISO or MOSI pins, it would Synthesize!But I need both of them to test my Design in real hardwareI'm pulling my hair to see what might be wrong, and I have no clue, do you happen to get this kind of error?

author: FlyingDutch
author_rank: Regular Contributor
timestamp: December 04, 2020, 08:35:06 am
content: Hello,I downloaded your code and it synthesize without errors (also implementation phase is without any errors). I am using "GOWIN FPGA Desiner" version 1.9.3 Beta for Windows. This code in zip archive attached to your post hasn't these pins (he MISO or MOSI pins) commented out?Best Regards

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 04, 2020, 02:25:39 pm
content: Thanks, the latest tools would crash, if you use Gowin Synthesizer.
Xilinx SP605 evaluation board question on ISE support - Page 1
Forum section: electronics / general

author: cncjerry
author_rank: Unknown
timestamp: November 28, 2020, 03:30:34 am
content: I'm new to FPGA systems. The measurement system I am building was developed on a Xilinx sp605 Evaluation board. The person that wrote the code said that he had tried it on the latest ISE 14.6 and then 14.7 but didn't mention the versions that came with the eval board kit which was 11.1 with the 11.3 upgrade. I'm trying to limit my questions to him to be about the system opposed to getting the foundation hardware running. I am downloading 14.7 but had read that the 11.3 and later versions as late as 13.x are locked to the eval board so I'm now wondering if I'll be able to use 14.7 on this board without a full license? The other question I have is that he provided the FPGA bit stream so I don't think I'll need anything other than the USB Jtag driver right?Said another way, I have ISE 11.3 and know that 14.7 will run on the board but don't know if I need a license for 14.7 or not. Part 2 is if I even have to worry about this since he sent me the FPGA bitstream that is loaded from the PC application he provides.Thanks for any help understanding this.Jerry

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 28, 2020, 07:03:58 pm
content: This board had a Spartan XC6SLX45T:https://www.xilinx.com/products/boards-and-kits/ek-s6-sp605-g.htmlXilinx ISE Webpack (the free version) supports all Spartan 6 up to 75T:https://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htmlhttps://www.xilinx.com/publications/matrix/Software_matrix.pdfSo there should be absolutely no problem using the latest ISE Webpack (14.7) with this board. Unless maybe the specific project uses some IP that is NOT free and has an additional license (and, if so, if said license would be tied to a specific version of ISE...) But if your colleague said he tried 14.7, then I guess there is no IP license issue. And you should be good to go.If all you need is configure the FPGA, you could use a number of other free tools. Digilent Adept comes to mind.

author: cncjerry
author_rank: Unknown
timestamp: November 30, 2020, 05:33:55 am
content: I have the Xilinx SP605 working with the custom application that loads the FPGA bitstream over the Jtag port. I've had an interest in FPGAs for quite a while and finally having one, I would like to learn some basic coding. I plan to go to the Xilinx site and look for a tutorial or something unless someone can point me at a more expeditious way to come up to speed.thanks,Jerry
Opening Gowin VCD files in Questa sim - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 16, 2020, 01:16:36 pm
content: Hi,Gowin logic analyzer would produce VCD files, I want to open them in QuestaAfter searching the web I found that the command inside Questa is thisCode:vcd2wlf FFT.vcd fft.wlfAnd this command would trough an error like thisQuoteDo you have any Idea what might be wrong?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 22, 2020, 11:09:37 am
content: Any Idea how to solve the VCDR_PHASE_ERROR?

author: ale500
author_rank: Frequent Contributor
timestamp: November 25, 2020, 09:09:47 am
content: I wonder if you tried the files on gtkwave. Just for curiosity. It seems that this vcd format exist in several flavors. Some synopsis tools emit also vcd files that seems a bit garbled on the eyes of gtkwave.It is a text file after all, you could open it and have a look at the given line, and the lines around it to see which command seems to cause problems. Maybe it needs to be "reparsed" and fixed

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 25, 2020, 10:26:39 am
content: gtkwave Can open it successfully,Thanks But I need to be able to open it in Modelsim too.
Is there any significant speed difference between Cyclone IV and 10? - Page 1
Forum section: electronics / general

author: mkaluza
author_rank: Contributor
timestamp: November 08, 2020, 10:00:37 pm
content: Hi guys!FPGA newbie hereI'm thinking about buying one of the altera dev boards- EP4CE15https://www.aliexpress.com/item/32949281189.html- 15k LE's- 10CL006https://www.aliexpress.com/item/1000006634063.html- "only" 6k LE'sThey are both similarly priced.My target is DDS - I'd like to play with building a function generator/AWG. Will there be any significant advantage of Cyclone 10? If not, I'll go with IV since it has 2,5x more resources for $$. I know that FeelElec AWG's are based upon the EP4CE6, so that's the reason I picked those two.Cheers,Marcin

author: ale500
author_rank: Frequent Contributor
timestamp: November 09, 2020, 08:17:49 am
content: You can get the latest quartus software and synthesize your design for both and compare the resource utilization as well as achievable max frequency. Cyclone IV is available in TQFP-144 packages the cyclone 10... too !, I just checked, I thought that would not be the case.Those are very nice boards ! loads of IOs (I happen to have the similarly designed xilinx version, great IO count for your buck !). If you are just starting, get the one with more resources for the same money.

author: BrianHG
author_rank: Super Contributor
timestamp: November 09, 2020, 09:23:19 am
content: Quote from: blueskull on November 09, 2020, 08:59:27 amAll the Cyclones, II, III, IV, V, 10, entry level versions are all just about identical except that V & 10 are a little slower in some scenarios as their VCCint is 1.1v instead of 1.2v. If you under-volt the the Cyclone IV / III from 1.2v to 1.1v, they actually perform the same though Quartus doesn't tell you that since you cannot change it's VCCint figure.Only entry level Cyclone V offer greater number of core M10k ram blocks and LE/gates & 18x18 multipliers for a lower price compared to all the other Cyclone variants.

author: radiolistener
author_rank: Super Contributor
timestamp: November 19, 2020, 04:58:05 am
content: I have this QMTECH board with EP4CE15:https://www.aliexpress.com/item/33007471265.htmlAnd this trenz.org/ARROW CYC1000 board with 10CL025:https://www.arrow.com/en/products/cyc1000/arrow-development-toolsI tested how they can handle max possible frequencies, and it looks that both have almost the same performance.10CL025 is a little worse than EP4CE15, but I'm not sure if the root of cause is FPGA chip or bad MEMS oscillator which is used on CYC1000 board. MEMS oscillator is real crap. It has very unstable frequency and high phase noise. So, if you buying the board select one with normal oscillator, don't use MEMS!According to my tests EP4CE 15 can handle about 480 MHz with usual counter and about 950 MHz with pipelined counter.If you choose QMTECH board, check available pins. For example, on my board just one clock pin is used for onboard oscillator. So, I'm unable to feed PLL from other sources than onboard oscillator.
JESD204B IP core on Artix FPGA  - Page 1
Forum section: electronics / general

author: rakeshm55
author_rank: Regular Contributor
timestamp: November 17, 2020, 11:45:21 am
content: Hi,i have board with Artix 7 FPGA - XC200T -FBG484 (4 GTP). FPGA has no softcore core invoked and has no DDR attached.I plan to connect an ADC with JESD204B interface (4 lanes) to this FPGA.Is there any free IP cores available for JESD204B specific to handling GTP in Artix 7 devices?? I have heard of LiteX project having LiteJESD204B. Can this be utilized/configured with custom logic (without softcore or a simple softcore with no DDR level requirements).i have also heard of analog devices offering JESD204B IP with GPL licenese. Have any one used it??
Can anyone program a PLS153 or a 82S153 from a good part/ - Page 1
Forum section: electronics / general

author: scopeman
author_rank: Frequent Contributor
timestamp: June 29, 2020, 04:14:01 am
content: I have a friend that has a good programmed 82S153 and a couple of blank chips that need programming.These particular parts do not have a security fuse feature so they should be able to be read.Is there anyone that could offer to program these parts for him? He is located in the U.S. None of the half dozen programmers that I have or have access to can either read or write these chips.I think if a JEDEC file could be also saved that these parts could be emulated with a 16V10 or 18V10 but that is only supposition on my part.Thank you,SamW3OHM

author: UncleBog
author_rank: Newbie
timestamp: October 05, 2020, 08:55:42 am
content: I have a Data I/O 2900 that has this part in its compatibility list. I have the DIP, 20 and 28 way PLCC adapters. I haven't run this for a while but can host it from a Tek LA which is stuck at Windows 2k. If this is still a live requirement let me know and I'll fire it up to check. Based in the UK.

author: coromonadalix
author_rank: Super Contributor
timestamp: October 16, 2020, 01:50:29 am
content: my programmer can are they plcc or dip package ?Im in Canada ?

author: Feberman
author_rank: Newbie
timestamp: November 09, 2020, 06:03:44 am
content: I think you need 82S153 programming data sheet or tutorial

author: coromonadalix
author_rank: Super Contributor
timestamp: November 19, 2020, 06:22:38 pm
content: http://www.jrok.com/hardware/ff_pls153/foodfight_pls153_to_GAL.htma nice 1981 "book"http://www.bitsavers.org/components/signetics/_dataBooks/1981_Integrated_Fuse_Logic.pdf.pdf
Edgeboard lite - Page 1
Forum section: electronics / general

author: ralphrmartin
author_rank: Frequent Contributor
timestamp: December 16, 2019, 03:38:55 am
content: Has anyone come across this:https://aim.baidu.com/product/dbb5272f-aff2-42fc-8bbc-382a53ef2c90from Baidu (China's main search engine).It seems remarkably cheap for a board like this (about half the price of the Avnet Ultra96, for example).It is intended for deep learning based image processing and comes loaded with tools and samples for that.Presumably it could be repurposed, although its docs say this is not supported (i.e. you are on your own).

author: colorado.rob
author_rank: Frequent Contributor
timestamp: December 16, 2019, 06:28:46 pm
content: Is the price the same when it is in stock?Do they provide documentation, including schematics for the board?Do they provide Vivado board support files?Do they provide English language support?If you are comfortable taking a risk and fending for yourself, it could be a really good deal. Ultra96 has lots of support resources for those that need it. You can get a Pynq distribution for Ultra96, for example. If you wanted to use Pynq on this board, you would need to roll your own.

author: ralphrmartin
author_rank: Frequent Contributor
timestamp: December 17, 2019, 09:02:24 pm
content: 1. I believe so - some Taobao sellers have it for slightly more, and probably do have stock.2. No - they seem to want you to use it for NN applications, using their code. It's not a general development board as such.3. See 2.4. Apparently not, although it could be worth asking them.2 and 3 are really why I posted this, to see if anyone knew otherwise on these points, or had rolled their own, etc.

author: cybero
author_rank: Newbie
timestamp: November 12, 2020, 10:44:00 pm
content: I bought it and I have run CNNs on it.But I'm having difficulties to create the Vitis platform for it.Did you buy it?

author: ralphrmartin
author_rank: Frequent Contributor
timestamp: November 14, 2020, 10:28:13 pm
content: Sorry, no, as it seemed no one else had used it for general uses rather than just NNs.
Kintex XC7K325T for $45 - Page 1
Forum section: electronics / general

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 22, 2020, 03:23:13 am
content: Found this interesting deal while searching Ebay, basically a FPGA based SSD minus the Flash board:https://www.ebay.com/itm/SSD-800G-XC7K325T-2FFG900C-FPGA-Solid-State-SSD-Drive/373031251427Sadly, the free tools do not seem to support it or I would have bought it right away.

author: miken
author_rank: Regular Contributor
timestamp: October 22, 2020, 04:45:32 am
content: I believe, though I haven't tried it myself, that you can rent a full Vivado image on AWS. It's in the list of AMIs (Amazon Machine Images).If you had a project that you could parameterize for a smaller device, and do most of the development on your own machine, perhaps it would make sense to rent such an AWS instance for a few hours on occasion.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 22, 2020, 01:43:28 pm
content: Quote from: NiHaoMike on October 22, 2020, 03:23:13 amThe listing says it's sold for parts and not working.

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 22, 2020, 01:56:50 pm
content: Quote from: NorthGuy on October 22, 2020, 01:43:28 pmMost likely because the Flash board was removed. There's a chance it could be made to work for some other purpose.

author: MadTux
author_rank: Frequent Contributor
timestamp: October 22, 2020, 04:33:26 pm
content: Without schematic, it's probably quite useless.And no connectors/pins for external I/O.Most things I did with programmable logic so far did fit well into small to mid sized CPLD, such a large FPGA is quite useless for small projects.
VHDLWhiz Advanced Course Sign-up - Page 1
Forum section: electronics / general

author: Evan.Cornell
author_rank: Regular Contributor
timestamp: October 19, 2020, 07:53:29 pm
content: VHDLWhiz has open enrollment this week for the Advanced Course:https://academy.vhdlwhiz.com/dotmatrix?utm_source=vw&utm_medium=main%20menu&utm_campaign=dot%20matrix%202020-10&utm_content=%2F

author: rstofer
author_rank: Super Contributor
timestamp: October 19, 2020, 09:34:48 pm
content: I have taken that course and it is excellent. I might just work along once again, just to reinforce what I was supposed to learn the first time. Yes, it costs money but education has never been free.I built up the final project including fabricating a PCB. Breadboarding that many components was just too grim to bear.I have also done the FPGA and VHDL Fast Track program.Both programs are worth every penny they cost.
Software for ACTEL FPGA A1020A ? - Page 1
Forum section: electronics / general

author: marcopolo
author_rank: Regular Contributor
timestamp: October 14, 2020, 10:37:53 am
content: Hi,Do you know if it is possible to find the software to develop on Actel A1020A FPGA?A friend of mine can get 25 for free in PLCC 5V.Thanks,Marc

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: October 14, 2020, 04:52:46 pm
content: For ACT1 devices like this one, you need to use Libero IDE (not Libero SoC).https://www.microsemi.com/product-directory/design-resources/1751-libero-ide#downloads

author: marcopolo
author_rank: Regular Contributor
timestamp: October 15, 2020, 11:35:55 am
content: Thanks for the information.I didn't know that an A1020 was a member of the ACT1 family.There is just a small problem, this software costs $2995

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: October 15, 2020, 02:43:08 pm
content: Quote from: marcopolo on October 15, 2020, 11:35:55 amYou only need a Gold License which is $995, not exactly cheap but still less than $2995!In saying that, the Arrow Everest Board is $549.00 and comes with a free Gold License, so this is a cheaper way to get the license, and you get a kit to play with!https://www.arrow.com/en/products/everest-dev-board-es/arrow-development-toolsEdit: Adding links for the ACT1 RevA and RevB datasheetsRevA:https://4donline.ihs.com/images/VipMasterIC/IC/MSCO/MSCOS04951/MSCOS04951-1.pdf?hkey=EC6BD57738AE6E33B588C5F9AD3CEFA7RevB:https://www.microsemi.com/document-portal/doc_view/130666-act-1-series-fpgas-datasheet

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: October 15, 2020, 03:21:40 pm
content: Are you aware that these devices are only one-time programmable ?

author: marcopolo
author_rank: Regular Contributor
timestamp: October 15, 2020, 03:40:30 pm
content: NO

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 15, 2020, 07:27:21 pm
content: Yeah. Besides those are very small FPGAs by today's standards. They are 20 years old. Unless you had a very specific reason for using them, don't bother.

author: marcopolo
author_rank: Regular Contributor
timestamp: October 15, 2020, 07:41:37 pm
content: Yes, you're right but it was just for the fun of using old FPGAs and because they were offered to me for free.But no free software and OTP, so I stop there.

author: amspire
author_rank: Super Contributor
timestamp: October 16, 2020, 12:14:41 am
content: I think I have a tube of them. Burning the fuses took a high current and anything less then perfect contacts with the chip in the programmer used to result in useless failed chips. Hurt when each chip was about $20 each.
Boot ICE40UL1K from NVCM - Page 1
Forum section: electronics / general

author: mon2
author_rank: Frequent Contributor
timestamp: October 08, 2020, 08:07:01 pm
content: Hi. Have a design based on the ICE40UL1K (16 ball WLCSP package) that is working fine using the CRAM or external SPI flash device to boot our IP (simple LED blinky code; pushbutton read code; tone generator code). Wish to embed the same into the OTP NVCM of the device and did this properly according to the Diamond Tool (powered the rails @ 3v0 to support the request from the datasheet and Lattice tech support). However, upon power up, the same FPGA is not boot loading from the NVCM. Any ideas on what could be wrong?The CDONE and SS pins each have a local 10k PU to +3v3. The CDONE pin remains low after a #RESET.The FTDI programmer is able to continue to make use of this OTP programmed FPGA using the CRAM region.Does the ICE40UL1K feature the "WARM BOOT" option? It was ENABLED (checked) by default in the toolchain and we did NOT make us of this feature. That is, perhaps this is the root cause preventing the boot from NVCM?Very confused and there appears to be limited documentation on this subject.Welcome any suggestions. Thanks!

author: mon2
author_rank: Frequent Contributor
timestamp: October 09, 2020, 03:23:01 pm
content: Answering my own post but what a learning experience! This is not documented but the issue is the DEFAULTWARM BOOT FLAGbeingENABLEDinside the ICECUBE2 compiler.We do not make use of this inside of our IP. If left with WARM BOOT = ENABLED, the OTP does NOT boot with our single IP block.Be sure that there are pull-up resistors on CDONE and SPI_SS pins - we are using 4k7 for each.The VPP voltage for the OTP process is +3v0 (not +3v3 as the +3v0 was suggested by Lattice FAE). After OTP programming, the FPGA and I/O can be ran @ +3v3.We did 2 things here before blowing another OTP, changed the FTDI prescaler timing to 31 (to slow down the SPI interface - just in case) AND removed the WARM BOOT flag. The same LED blinky IP is working 100% and is booting from the OTP.Hope this helps a future reader.These ICEPIK boards will be available soon to the general public - ICE40UL1K on a 8 pin DIP format. Also a supporting programmer to program this PCBA.Thanks!Kumar
Getting Started with a Alinx AN108 and Cyclone 2 Board Help - Page 1
Forum section: electronics / general

author: ihearta380
author_rank: Newbie
timestamp: October 15, 2020, 10:55:00 pm
content: Hello after purchasing a Alinx AN108 Board I am trying to pass data from the ADC to the DAC as a simple null modem or loop through which I am using one of the two fpga dev boards that I bought to get thing working.https://www.amazon.com/ARCELI-Altera-Cyclone-ES2C5T144-Board/dp/B07BVN2R7Xor thehttps://www.amazon.com/Module-Signal-Acquisition-Directly-pluggable-Development/dp/B07DFFQ9CSI tried to creating a divide by two counter to take in the global clock and divide it by two then pass that into the two AD/DA clock inputs. Then I tried to taking the input pins from the ADC and map them to the output pins on the DAC sequentially AD0 -> DA0... however I just get noise and a line on the output on a scope.I just need some help getting started with some HDL design to make it operable if anyone could ad in assistance with a design for the clock, pinouts, or whatever is needed to pass traffic from one side to the other thank you.
Can you use a uC's DACs for (low-power) FPGA power-supply sequencing? - Page 1
Forum section: electronics / general

author: andybrandi
author_rank: Contributor
timestamp: September 19, 2020, 07:09:52 pm
content: So I'm trying to figure out the minimum circuitry needed to power a low-cost FPGA like the Lattice iCE40 Ultra Lite. (Just for the fun of it.)Getting the power-up sequence and voltage levels right appears to be the hardest part. Given the low power requirements in the 100mA range (rough estimate based on the maximum I/O line current), I was thinking of simply using a cheap uC and do the power-up/reset sequencing in software with the built-in DACs and an opamp buffer. Is this a valid approach, or am I missing something obvious?(FYI, here's the datasheet for the FPGA:https://www.latticesemi.com/view_document?document_id=50945)Thanks!

author: tszaboo
author_rank: Super Contributor
timestamp: September 19, 2020, 08:07:38 pm
content: Just connect the power good signal from one power rail to the enable of the next power rail. It works most of the time. If it doesn't, there are 3 pin reset controllers for that. This tiny FPGA has very relaxed supply sequencing, there are no requirements for timing whatsoever. At least not at first glance.

author: filssavi
author_rank: Frequent Contributor
timestamp: September 19, 2020, 08:37:16 pm
content: In my experience the ice40 family is so simple and tiny to not require supply sequencing, case and point the lattice low cost demo board does not even bother having a real supply for the 2.5V rail just using a diode to drop the 3.3V to roughly the right ballpark.
Project Hierarchy: Create subdesign from Quartus project - Page 1
Forum section: electronics / general

author: RedLion
author_rank: Regular Contributor
timestamp: September 10, 2020, 10:07:50 pm
content: Hello everyone,This might be a very dumb question with a very obvious answer, but I couldn't for the life of me find an answer on Google.In Intel Quartus, if I wanted to create a "sub-project" from an existing project, so I can integrate it in a new one, say as a functional block in the block design file, how would one go about it?There has to be project hierarchy because it says so in the UI, but I can't find out how that works.Thanks
Visualize the PCIe communication protocol  - Page 1
Forum section: electronics / general

author: TheGreatNed
author_rank: Contributor
timestamp: August 28, 2020, 05:11:29 pm
content: Hello,I was wondering what the best way to visualize the PCIe protocol is. I know both Intel and Xilinx provide soft and hard ip for pcie drivers. However, these are closed source and I can only simulate their output -- not what goes on inside.I would love to be able to see what a packet looks like before it enters the PHY and how it looks coming out of the PHY. Does anyone have any advice on using the pcie opencores or ip to achieve this?Thank you

author: Someone
author_rank: Super Contributor
timestamp: August 28, 2020, 11:06:58 pm
content: You can see those specific details in the simulations provided by Altera, Xilinx claim to have similar but I haven't looked too deeply at their example.

author: asmi
author_rank: Super Contributor
timestamp: August 29, 2020, 02:01:51 am
content: Find a PCI Express specification - it describes what signal looks like on a line, what packet looks like as it passes through the stack. It's conceptually very similar to how Ethernet works and it's OSI stack, except that PCIE has less layers because it's much more simple.

author: KE5FX
author_rank: Super Contributor
timestamp: August 29, 2020, 02:31:15 am
content: Take a look athttps://github.com/enjoy-digital/litepcieand see if that helps. Alsohttp://www.xillybus.com/doc/xilinx-pcie-principle-of-operationis worth looking at. Even though it's a commercial product its inner workings are well-described.

author: tmbinc
author_rank: Frequent Contributor
timestamp: September 10, 2020, 03:23:56 pm
content: Not sure which layer you're mostly interested - if it's above PHY, then another way is to install a PCIe analyzer software (I like the Teledyne/Lecroy Summit one a lot, but there are different ones). They usually come with sample captures that work without hardware. It allows you to look at data on various levels, typically down to the bit level, and allows you to browse through TLPs.PCIe is surprisingly sane.The PHY "doesn't do a lot" from this perspective though - it's a SERDES with clock recovery. Perspective changes a lot of course once you look into the details.
set_multicycle_path questions - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: September 03, 2020, 09:04:37 am
content: Formulticycle path constraint, what is the difference betweenthe usage of -start and -end?Why "hold will return back to 0 cycle check" ?

author: NorthGuy
author_rank: Super Contributor
timestamp: September 03, 2020, 01:38:17 pm
content: Use -start to count cycles of the source clock.Use -end to count cycles of the destination clock.Doesn't matter if both clocks are the same.

author: promach
author_rank: Frequent Contributor
timestamp: September 03, 2020, 02:58:36 pm
content: QuoteThen the blue arrow in Figure 8 is wrong ?Besides, how to derive the equationHold cycles = <setup path multiplier> - 1 - <hold path multiplier>inhttps://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug903-vivado-using-constraints.pdf#page=79?
Structural design - Page 1
Forum section: electronics / general

author: Tamas1992
author_rank: Newbie
timestamp: August 12, 2020, 04:07:34 pm
content: Hi,I would like to practice logic design, preferably with real designs/projects.To give an idea about my level here are some examples what I've done so far: 1 bit full adder, Gray code up counter, 3 bit up-down counter.So fairly basic stuff, although I do not fear a good challenge.I can implement combinational logic in Verilog (using ModelSim - Altera). (learning the behavioral modelling is in progress, I've used some aspects of it in testbenches already)So if someone needs some logic functionality designed I'm happy to give it a try. (For FREE)Best regards:Tamas

author: tggzzz
author_rank: Super Contributor
timestamp: August 12, 2020, 04:21:28 pm
content: I don't need anything done!A suitable starting point is to design and implement a traffic light controller. Start with the basic red/amber/green sequence, then extend the design to include push buttons that allow pedestrians to cross.Pay attention to designing the finite state machine (FSM) and then implementing it. Think about how the implementation could make it easier or more difficult tocorrectlyextend the functions later.

author: rstofer
author_rank: Super Contributor
timestamp: August 14, 2020, 03:06:39 pm
content: The LC3 (not LC3b) project that seems to be a popular project at many universities. It implements a simple 16 bit RISC CPU. Given the state transition diagram in Appendix C, the FSM is pretty easy to write. The logic diagrams pretty much detail which components you need to create and how to interconnect them. It's actually a pretty simple project. A bunch of code is provided for testing.https://www.cs.utexas.edu/users/fussell/courses/cs310h/lectures/Lecture_10-310h.pdfhttps://www.cs.colostate.edu/~cs270/.Summer20/resources/PattPatelAppA.pdfhttp://people.cs.georgetown.edu/~squier/Teaching/HardwareFundamentals/LC3-trunk/docs/LC3-uArch-PPappendC.pdfThe book is:https://www.amazon.com/Introduction-Computing-Systems-Gates-Beyond/dp/0072467509I haven't gotten around to the LC3b project which changes the CPU to include 8 bit addressing instead of 16 bit. There are links on the Internet for this version.

author: Tamas1992
author_rank: Newbie
timestamp: September 07, 2020, 01:53:28 pm
content: Traffic light control logic with adjustable delay between transitions:Here is how I solved it:4 states - 2 JK ffs3 inputs from delay circuitryThere are 3 individual delay settings ( 1 for red, 1 for red-yellow and yellow, 1 for green)3 x 32 bit delay registers, each get their value from a serial to parallel shift register3 x 32 bit up countersEntering a state starts the associated counter.When the contents of a delay register and its associated counter register is equal, a trigger signal is set for the control logic and the FSM advances a state.The delay idea is from a PIC Timer module with comparator functionality, which works the same way.
Issues programming TinyFPGA AX2 - Page 1
Forum section: electronics / general

author: burko
author_rank: Newbie
timestamp: August 22, 2020, 11:59:07 pm
content: I have been trying to program a TinyFPGA AX2 (Lattice MachX02) using an ebay version of the Lattice HW-USBN-2A programmer (the tinyFPGA programmer seems to be out of stock everywhere).Using the lattice diamond programmer software it appears to try and do a JTAG scan but will just sit there forever and do nothing (yes i installed the drivers for the device).I downloaded an older version of the Lattice ispVM software and seem to get a little further as it will complete a JTAG scan and show there is a device. However, when i go to program a file it does nothing for a few seconds then comes back with: Failed to Load LSC Windows USB driver. I have tried reinstalling the driver and running ispVM as admin but still no luck.Any ideas as to what is wrong?

author: miken
author_rank: Regular Contributor
timestamp: August 24, 2020, 01:51:21 am
content: My memory is a little hazy but I think we had some odd problems with Diamond. Try a computer with a different Windows version if you have one around.

author: burko
author_rank: Newbie
timestamp: August 27, 2020, 11:34:00 pm
content: Thanks for replying. I didn't have another computer with an older version but i did have a VM that was running Windows 7 so i gave that a try. It still wouldn't work on Lattice Diamond but would work on Lattice ispVM, although painfully slow.I ended up getting a Adafruit FT232H module that is recognized as a HW-USBN-2B (FTDI) without any firmware changes. It still didn't work on Lattice Diamond but would work fine on Lattice ispVM on Windows 10. I would recommend this approach to anyone wanting a cheap programmer and avoid the HW-USBN-2A clones. Connections for the Adafruit module are:Adafruit Module | FPGAD0 TCKD1 TDID2 TDOD3 TMS

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 28, 2020, 01:36:56 am
content: I don't know really. Never had any problem programming MachXO2 devices with Diamond on Windows 7.

author: Bassman59
author_rank: Super Contributor
timestamp: August 28, 2020, 04:53:32 pm
content: Quote from: SiliconWizard on August 28, 2020, 01:36:56 amSame here -- in fact I run Win7 in a VMWare VM on macOS.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 28, 2020, 04:57:18 pm
content: Quote from: Bassman59 on August 28, 2020, 04:53:32 pmBut from what can be read here, it looks more like an issue with dodgy programming adapters than a problem with Diamond, Windows 7 or the TinyFPGA board anyway.
Altera JTAG UART output to GDB - Page 1
Forum section: electronics / general

author: Dago
author_rank: Frequent Contributor
timestamp: October 05, 2020, 05:12:39 am
content: I've been developing a project of mine which has an Intel FPGA running a NIOS processor. I've been using printf() for debugging from the NIOS side to the PC. This works ok when using the "NIOS 2 Software Build Tools for Eclipse". However after updating the toolchain to the newest 20.1 there seems to be some kind of bug causing me to not be able to do "run as" preventing me from running the code via Eclipse. The "Run configurations" menu correctly shows my programming cable but the "run" button stays grayed out. The old version of the toolchain I had before had the same bug but I could get around it by replugging the cable or something but not now...Anyway I'm not too attached to using the Eclipse for anything and I can run everything else from the CLI except I cannot get the JTAG UART printf() output to appear in gdb. Since this works when run from Eclipse I'm sure my project and code are configured correctly so I think I am just missing some command from gdb or gdb-server telling it to display/print the JTAG UART data. I know for some GDBs/processors this command is "monitor semihosting enable" but the NIOS gdb does not seem to know this command. Does anyone know what I need to do to get the printf() stuff to appear in gdb?

author: MarginallyStable
author_rank: Regular Contributor
timestamp: October 05, 2020, 07:07:02 pm
content: The jtag uart output comes from the terminal program nios2-terminal.exe You should be able to lookup the proper command line and attach using it in NiosII command shell

author: Dago
author_rank: Frequent Contributor
timestamp: October 06, 2020, 05:07:00 am
content: Quote from: MarginallyStable on October 05, 2020, 07:07:02 pmTHANKS! I haven't actually noticed that binary at all. I've just assumed the IDE must be reading the output from gdb somehow since it is using the JTAG.
how to work an instantiation template (verilog-Xilinx) into SV design? - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: August 19, 2020, 05:26:04 am
content: Okay, so I making a BRAM interface in System Verilog just for fun and to get to know the language a little. The actual instantiation template for a BRAM is in verilog, but Im not sure how to work that into my design, because I have never worked with a design with mixed languages. Im using Vivado, which supports SV for RTL so no issue there.Do I save the BRAM instance (with a wrapper around it) as a verilog file, then instantiate that verilog module in my SV file? I thought I have seen something like that done with VHDL and Verilog.(yes I know the tools could infer a BRAM but Im just curious about actually instantiating one, its how I like to do things most of the time).-Thanks, Dom
USB NRZI data encoding - Page 1
Forum section: electronics / general

author: promach
author_rank: Frequent Contributor
timestamp: August 17, 2020, 11:44:18 am
content: Why thefollowing USB signalling bitsdo not seem to follow NRZI data encoding ?

author: hexreader
author_rank: Frequent Contributor
timestamp: August 17, 2020, 12:11:47 pm
content: My guess is that you are looking at the "bits" field in your diagram rather than the waveforms at the top.NRZI applies to the waveforms on the USB bus, not the data bits.

author: promach
author_rank: Frequent Contributor
timestamp: August 17, 2020, 01:07:18 pm
content: what the spec labels "NRZI" is the signalling bits line in Sigrok, and what the spec labels "data" is the signalling symbols. ??

author: hexreader
author_rank: Frequent Contributor
timestamp: August 17, 2020, 02:48:22 pm
content: My understanding of "symbols" is poor, but I see that user FVM has answered you on the edaboard forum. I trust him to have given the correct answer.

author: voltsandjolts
author_rank: Unknown
timestamp: August 17, 2020, 02:59:29 pm
content: Cross ref to that post on edaboard:https://www.edaboard.com/threads/usb-nrzi-data-encoding.394296/

author: GeorgeOfTheJungle
author_rank: Super Contributor
timestamp: August 17, 2020, 04:17:12 pm
content: Low speed USB uses Manchester encoding IIRC.

author: ataradov
author_rank: Super Contributor
timestamp: August 17, 2020, 04:46:50 pm
content: You can see from the capture that it is NRZI encoded. Even in the SYNC sequence you can see that 0 is encoded as a transition between the states, and for the last "1" in the SYNC the state remain "K".

author: promach
author_rank: Frequent Contributor
timestamp: August 18, 2020, 02:04:23 am
content: Low speed USB uses Manchester encoding or NRZI encoding ?

author: ataradov
author_rank: Super Contributor
timestamp: August 18, 2020, 02:18:31 am
content: All of them use NRZI with bit stuffing to prevent long runs of 1s. There is no Manchester anywhere in USB. You can clearly see it on your log.
Industry going to SV for synth instead of verilog? NOT DISCUSSION ON WHIC BETTER - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: August 11, 2020, 07:28:12 am
content: My teacher said the industry is moving to System Verilog from Verilog for companies that use Verilog as their primary HDL. She doesnt have very much experience in FPGA design, but I am curious about this statement. I know SV is good for simulation and verification, but is the industry moving towards it for synthesis as well?Im not wondering on which is better (dont want to get that conversation started lol), I just want to understand her reasoning behind it. She just told me thats what she heard from some other professors.Thanks.

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: August 11, 2020, 09:29:06 am
content: People often think that Verilog is a hardware modeling language which is synthesisable while SystemVerilog is a verification language that is not synthesisable. This is not true.In 2009 the Verilog standard merged into SystemVerilog and since then the SV standard has extended both the verification and the hardware modeling capabilities of Verilog.Here is an interesting paper on Synthesizing SystemVerilog:https://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf

author: filssavi
author_rank: Frequent Contributor
timestamp: August 11, 2020, 09:43:56 am
content: While for the most part SV is concerned with verification, there are some additions that make it much better than plain verilog even for synthesis (in no particular order, and not exhaustive):-logic type- always_ff/comb- array of busses in module I/Os- Interfaces (this one is great, 1 like for an AXI bus instead of 20)While these are mostly quality of life things (there is no big core difference between the two) they make SV code much more readable

author: ejeffrey
author_rank: Super Contributor
timestamp: August 11, 2020, 04:16:33 pm
content: Quote from: Dmeads on August 11, 2020, 07:28:12 amExactly what EverydayMuffin said: SystemVerilog is now the new Verilog.But my limited experience is that this is true in a broader sense: companies are adopting new constructs from SystemVerilog into their style guides for synthesizable design as well as verification.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: August 11, 2020, 11:31:25 pm
content: Verilog is dead. Long live SystemVerilog!
Lattice Crosslink-NX and Certus-NX FPGAs - Page 1
Forum section: electronics / general

author: mark03
author_rank: Frequent Contributor
timestamp: July 31, 2020, 04:14:53 pm
content: I just ran across these new FPGA families and wondered if anybody here has opinions about them. No parts available yet, but there is a Crosslink-NX dev board in stock for ~ $130. They seem to be the first FPGAs built on an FD-SOI process (28 nm) and claim "up to 4x lower power consumption." Their "big" part (39k logic cells, 56 DSP blocks, 2.5 Mbit RAM) is available in a 72-pin QFN, which I thought was noteworthy. It appears comparable to some of the smaller Spartan or Artix 7's for which the easiest package option is 1-mm 196-ball BGA. This could be really nice for applications where you don't need a lot of IO.The "low cost" Certus-NX family is newer but appears to be the same dies. No QFN package listed yet but I imagine it might be added later.Documentation appears somewhat thinner than that provided by Xilinx or Intel. No support forum (they closed it and ask you to open a support case instead). For those who have used their software (Radiant), how does it compare with something like Vivado?

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 31, 2020, 11:09:15 pm
content: Quote from: mark03 on July 31, 2020, 04:14:53 pmI've used it with iCE40 parts.Radiant is much, much simpler and lighter than Vivado. Typical install size ~ 3.5GB on disk. Simple workflow, basic tools. Easy to use, and fast. If you need any of the fancy features of Vivado, you'll be disappointed, but if you need something light, fast and easy to learn, it's fine. For designs on small FPGAs, you don't need anything fancier anyway IMO.

author: mark03
author_rank: Frequent Contributor
timestamp: August 01, 2020, 12:10:42 am
content: Quote from: SiliconWizard on July 31, 2020, 11:09:15 pmFunny yet sad that we now live in an era where "only 3.5GB" is impressively smaller than the alternativeDoes it include a logic simulator?

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 01, 2020, 01:49:59 am
content: Quote from: mark03 on August 01, 2020, 12:10:42 amI know eh! But Vivado takes > 18GB on disk... and that's not with all parts enabled.Quote from: mark03 on August 01, 2020, 12:10:42 amYes, Radiant (as with Diamond) includes Active-HDL. And related to the above, it takes about half of the 3.5GB.

author: ejeffrey
author_rank: Super Contributor
timestamp: August 01, 2020, 05:36:37 am
content: Quote from: SiliconWizard on August 01, 2020, 01:49:59 amI just did a nearly full install yesterday. 48 GB!

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: August 01, 2020, 12:08:16 pm
content: Here's a white paper on the Certus-NX which I came across last month:https://www.latticesemi.com/view_document?document_id=52976
FPGAs using a wireless camera? - Page 1
Forum section: electronics / general

author: prophoss
author_rank: Contributor
timestamp: July 31, 2020, 01:48:52 am
content: This is way beyond anything I could do, but... can you connect a bluetooth camera to an FPGA. My intial idea would be to use an esp32 to record an image when movement is present then stream that to an FPGA for capture and possible analysis? I may be missing the whole point here but thought I'd ask.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 31, 2020, 01:54:41 am
content: Just link it with a second ESP32 or whatever to convert the Wifi signal back into SPI or something that's easy to interface with a FPGA. That said, for image analysis, a GPU or machine learning ASIC would probably be an easier and more cost effective way to do it.
Programming device for MACHXO2? - Page 1
Forum section: electronics / general

author: soFPG
author_rank: Frequent Contributor
timestamp: July 11, 2020, 03:52:32 pm
content: To the people who are using MACHXO2 FPGAs:Which device are you using for programming?

author: soFPG
author_rank: Frequent Contributor
timestamp: July 11, 2020, 04:10:48 pm
content: I am just ignoring the provocation and take the useful information, thank you.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 11, 2020, 04:16:49 pm
content: Not sure what the clone part was about - if it was about the FT2232H, I think it's moot as this chip was never cloned AFAIK. Only the cheaper UART-USB ICs like the FT232R were.Other than this, as said, any FT2232H or FT232H (single channel) breakout board will do if you work @3.3V. If not, you'll need extra level shifters. I have used a Bus Blaster V3 board for this, as it conveniently includes a CPLD which does the level shifting. Any JTAG adapter made of a FT2232H or FT232H you can grab should do.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 11, 2020, 04:46:45 pm
content: Quote from: blueskull on July 11, 2020, 04:20:53 pmOh OK. Well whatever he buys is up to him as long as it has the proper FTDI chip that Lattice handles (both FT2232H and FT232H, both tested). Certainly doesn't need to be the Lattice probes, whether they are genuine or clones.You can find a bunch of breakout boards apart from the official FTDI modules (you're probably thinking of the official FT2232H module which indeed needs some wiring for the power supplies IIRC) which are already properly wired and just need wires for the JTAG connection.Apart from the Bus blaster boards I mentioned (about $30-$35 IIRC), you can buy a FT232H breakout board from a reputable source (Adafruit) which has all you need for a JTAG probe (except level shifting if needed):https://www.adafruit.com/product/2264($15)

author: ebclr
author_rank: Super Contributor
timestamp: July 11, 2020, 04:47:03 pm
content: Don't be to acid "blue" we like you

author: soFPG
author_rank: Frequent Contributor
timestamp: July 13, 2020, 01:12:19 pm
content: QuoteDoes this mean it is also possible to re-purpose an Altera Clone JTAG programmer to act as a programmer for Xilinx FPGAs?

author: ale500
author_rank: Frequent Contributor
timestamp: July 30, 2020, 02:45:59 pm
content: I use a MachXO2 breakout board, it has a FT2232H on it, as programming cable. A FT2232H breakout board works as well, and yeah I used the EEPROM dump blueskull is talking about, I think it was his, to repurpose the (FT) breakout board so DIamond recognizes it. There are cheap clone cables in ali nowadays, too... Sadly shipping in taking 3 to 4 weeks to Germany these days...
Quartus tcl LogicLock member - Page 1
Forum section: electronics / general

author: Wiljan
author_rank: Regular Contributor
timestamp: July 28, 2020, 01:09:32 pm
content: When using the Quartus and having a lot of identical blocks running in parallel and pipelined then the place & fitter does not place the design element in a nice way like if you did a PCB layout where you would keep tracks short and logic symmetricalSo it's then possible to use the LogicLock and create logic lock partitions and assigning design elements to a fixed regionDoing this makes the Chipplan looking nice and symmetrical and if for sure rise fmax and even decrease compile timeIn the Gui of the Chipplan it works but are pretty slow and you need to use quite some time clicking around so I was looking into tcl script where it's pretty simple to create regionlock and make them fixed and placed whee I like them to be and in the right size.Code:set_global_assignment -name LL_ENABLED ON -section_id "test:round_01"set_global_assignment -name LL_AUTO_SIZE OFF -section_id "test:round_01"set_global_assignment -name LL_STATE LOCKED -section_id "test:round_01"set_global_assignment -name LL_RESERVED OFF -section_id "test:round_01"set_global_assignment -name LL_CORE_ONLY OFF -section_id "test:round_01"set_global_assignment -name LL_WIDTH 10 -section_id "test:round_01"set_global_assignment -name LL_HEIGHT 1 -section_id "test:round_01"set_global_assignment -name LL_ORIGIN X29_Y01 -section_id "test:round_01"This works fine but I need to add a members as well and try to do it withset_global_assignment -name LL_MEMBER_OF "chk_calc_32:chk_high" -section_id "test:round_01"The tcl are accepted not the member are still "none" in the Chipplanner if I go to the Project navigator and select the actually chk_calc_32:chk_high and right click and add to existing LogicLock Region it pop's up fine in the Chipplan and I can then click on test:round_01 and do a edit and get the member design member "chk_calc_32:chk_high"So what are I'm doing wrong to get the tcl script to do the same thing?I need to place over hundred's elements so I for sure would like to use the tcl

author: Wiljan
author_rank: Regular Contributor
timestamp: July 28, 2020, 07:01:46 pm
content: Ok Quite some search and found the solution it has to use "set_instance_assignment" and not "set_global_assignment"This does workCode:set_instance_assignment -name LL_MEMBER_OF "test:round_01" -to "chk_calc_32:chk_high" -section_id "test:round_01"https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-manually-place-a-component-with-Quartus-II/td-p/183335