Delta Sigma ADC Load Cell Voltage Divider Question - Page 1
Forum section: electronics / projects

author: 455Turbo
author_rank: Contributor
timestamp: March 16, 2022, 08:35:05 pm
content: I want to use a MAX11270 delta sigma ADC to digitize the output of a load cell. I want to maximize the system resolution so I'm trying to match the reference voltages and common mode voltage to the maximum and minimum expected load cell output voltage and common mode voltage.Is this a reasonable approach?A simple solution to generating the reference voltages is to use a three resistor voltage divider. It's shown in the attachment 'Load Cell Divider.png'The voltage divider uses three resistors, 6K2, 68, & 6K2. I've gone through the math and these values will set the reference plus and the reference minus to a window slightly larger than the expected load cell output, with the same common mode voltage. I've taken into account the load cell zero balance tolerance, the load cell rated output tolerance, and the voltage divider resistor tolerance and this should work as long as everything is within manufacturer's specs.Is this voltage divider a reasonable way to generate the reference voltages? Are there any concerns about the resistor values? Is there a better way to generate the reference voltages? I'm also trying to minimize component count.Thanks!

author: Kleinstein
author_rank: Super Contributor
timestamp: March 16, 2022, 09:39:30 pm
content: The ADC has a lower limit for the reference voltage of some 2 V.The ADC also has quite a lot of internal gain, that is more effective than reducing the reference. So just the DS circuit with the full bridge voltage as reference and than the gain at the ADC input is good enough. A load cell tends to be limited dynamic range anyway. So there is no real need to reduce the reference. With a divider like 220 - 1 K - 220 one would still get a relatively large impedance for the reference and burn quite some power.

author: thm_w
author_rank: Super Contributor
timestamp: March 16, 2022, 09:48:01 pm
content: Where is "excitation 3v6" coming from? Is it low noise?https://download.mikroe.com/documents/add-on-boards/click/load_cell_6_click/Load_Cell_6_click_v101_Schematic.PDFhttps://www.maximintegrated.com/content/dam/files/secured/design-tools/software/5985/maxrefdes75_sch_ra.pdfI guess the MAXREFDES75 is similar to what you are trying to do, although it seems overly complex.As Kleinstein mentioned, 1-128x PGA is available in this IC.

author: 455Turbo
author_rank: Contributor
timestamp: March 16, 2022, 10:14:17 pm
content: The 2V min for Vref makes this a dead end. I missed that.The 'excitation3v6' comes from a LT3042 powered by a 5V linear supply that is spec'd @ <1mv p-p ripple. Any thoughts?Thanks!

author: moffy
author_rank: Super Contributor
timestamp: March 16, 2022, 10:24:29 pm
content: Quote from: 455Turbo on March 16, 2022, 10:14:17 pmWhy does it make it a dead end? You can increase the size of your signal with low noise external amplification, without necessarily impacting resolution.What are the specs/requirements for your design?, from that a solution can usually be crafted.

author: 455Turbo
author_rank: Contributor
timestamp: March 16, 2022, 10:47:12 pm
content: moffy - I should have stated that the 2V min for Vref makes the voltage divider reference, as shown, a dead end. You are absolutely correct.

author: moffy
author_rank: Super Contributor
timestamp: March 16, 2022, 11:14:55 pm
content: Quote from: 455Turbo on March 16, 2022, 10:14:17 pmThanks for clarifying that. The regulator is low noise, so that is good, but the stability is not what you expect from a reference, 1% initial plus drift due to external 1% resistors etc. That will effect the overall gain of the conversion, so if it is not stable enough for your overall gain error budget then it is a problem.

author: 455Turbo
author_rank: Contributor
timestamp: March 17, 2022, 12:50:07 am
content: moffy - That's a great point about using a voltage reference. Thanks

author: Kleinstein
author_rank: Super Contributor
timestamp: March 17, 2022, 08:50:15 am
content: The bridge circuit with the reference from the bridge side is ratiometric. So ideally it does not care about the stability of the reference and also reference noise has very little effect (there can be a little from different filtering for the signal and reference path).Depending on what else is powered from the regulator and the legth of the cables, one may consider using 6 wire sensing for the load cell. So have 2 extra wires to the load cell to sense the reference voltage to the ADC directly from there. This would remove the voltage drop on the cables from the bridge drive. 6 wire connection is common for precision load cells.The ADC internal amplifiaction (up to 128 times) is already quite low in noise. Comparable quality (low drift, high CMRR and low noise) external amplification would be already quite challanging.

author: Terry Bites
author_rank: Super Contributor
timestamp: March 17, 2022, 09:34:09 am
content: To get true ratiometric operation: REF+ in shoud be connected at the load cell's +Ve exitation terminal and similarly REF- needs to connect to the cells -Ve exitation.Then variations in ref are nulled out- AVdd can be the REF+ and AVss ro REF-.

author: 455Turbo
author_rank: Contributor
timestamp: March 17, 2022, 01:06:31 pm
content: In this case the specification is to meet or exceed a competitive product's capabilities. The competitive product specifies counts (anywhere from 3,000 to 20,000) depending on the application. They also spec accuracy as +/- 1% (I assume this is % of reading). That's a lot of inaccurate counts.The load cell specs for hysteresis, temperature effect, & non repeatability, have consumed most of the error budget. I will map out the load cell non-linearity in software.Looking at the MAX11270 noise free bits vs. PGA gain led me down the path of trying to increase the signal from the load cell and minimize PGA gain. I studied MAXREFDES75. It seemed like a kludge, but I thought I could adopt the voltage divider reference idea. I missed the minimum Vref requirement.At this point I'm taking Kleinstein's and Terry Bites' advice and using my LT3042 to excite the load cell, provide REF+ and REF-, and power the MAX11270 AVDD. This is a simple solution. The wires to the load cell are only about 200 mm long so it will be a four wire setup.The MAX11270/LT3042 system error contribution is small in comparison to the load cell's. So I'll focus on finding a better load cell.Thanks everyone for all of the help.

author: voltsandjolts
author_rank: Unknown
timestamp: March 17, 2022, 01:19:35 pm
content: If your load cell is semiconductor based and has to operate over a wide temperature range, and you're going to calibrate it at different temperatures, you would also need to monitor the bridge temperature. So, if that is the case, you might want to use the kind of topology shownhere. Semiconductor bridge sensitivity varies with temperature but so does the bridge impedance, which is useful. R1 keeps the common mode in allowed range, which needs attention especially at high adc gain.

author: voltsandjolts
author_rank: Unknown
timestamp: March 17, 2022, 01:26:39 pm
content: Quote from: moffy on March 16, 2022, 11:14:55 pmAs long as you keep the measurement ratiometric (adc ref derived from bridge supply) you don't need an accurate reference. Time constant for adc ref and the load cell signal should be kept similar.