Need help on MCU selection - Page 1
Forum section: electronics / general

author: blueskull
author_rank: Unknown
timestamp: February 24, 2016, 03:41:24 am
content: I'm looking for a chip that can do real time control of a DC/DC controller. Any suggestions for this application?The system looks like this: MCU samples output voltage, does PI update, sends out new PWM control words to FPGA, then FPGA generates HRPWM.I know TI C2000 chips have integrated HRPWM, but one of the goal of this project is to build an entire 10MHz DC/DC converter from ground up and understand deeply.Since it switches at 10MHz, I want to update PWM at least 1M samples per second to maximize response time (this will be proposed as a next generation VRM).That implies my ADC must updating at at least 1Msps, and since most chips require ~20 cycles per interrupt (entry and return), I want to use a while loop to check CONVDONE flag.I need accurate, at least 12 bit ADC, at least 16Mbps SPI (for tx of PWM words, and reads back delay line calibration date from FPGA).The CPU must be able to calculate 1M PI or PID control words in fixed point or integer math per second, with extra CPU resource to control another DC/DC operating at lower Fsw.Any suggestions? Should I go for a M3/M4, C2000 or AVR32/PIC32? M0, MSP and AVR/PIC are not in my consideration.

author: ehughes
author_rank: Frequent Contributor
timestamp: February 24, 2016, 03:54:07 am
content: If you have an FPGA, use that!

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 24, 2016, 04:43:56 am
content: The FPGA is a good option. If you need an MCU anyway, take a look at the Infineon XMC4400 series.

author: AndrewDojo
author_rank: Contributor
timestamp: March 04, 2016, 09:21:11 pm
content: Maybe an XMOS chip option.http://www.xmos.com/products/silicon/xcore/a-seriesYou could prototype using they startKit board:http://www.digikey.com.au/product-search/en?keywords=880-1066-NDYou might find that you could also do the HRPWM with the same chip.

author: rsjsouza
author_rank: Super Contributor
timestamp: March 04, 2016, 09:55:25 pm
content: Quote from: blueskull on February 24, 2016, 06:25:21 pmblueskull, theF28377S Launchpadis ready to go and has plenty of horsepower (200MHz and built-in 1MSPS ADCs, but I would double-check its specs carefully)Another alternative would be a Hercules Launchpad, more specifically theRM46 Launchpadwhich also has plenty of horsepower (200MHz+).If you ever want to design it from ground up, theDelfinosmay be overkill due to the floating point, but a F28344 or F28346 can reach 300MHz which will give you plenty of horsepower to start experimenting. ThePiccolosare simpler and the big honking guy F28075 goes up to 120MHz.All of the above have FPU, which may be optional, but it seems this always comes joined to another feature you will certainly need: DMA (some Piccolos don't have it)

author: Howardlong
author_rank: Super Contributor
timestamp: March 05, 2016, 09:24:46 am
content: To quench my curiosity, why does it need to switch at 10MHz?Sounds to me like quite a difficult engineering problem in both the digital and analogue domains.

author: rsjsouza
author_rank: Super Contributor
timestamp: March 05, 2016, 12:05:22 pm
content: Quote from: blueskull on March 05, 2016, 12:08:41 amYes, the 28027 launchpad is a much more convenient device to work, but I still think it is underpowered for what you are trying to achieve - hopefully I am wrong.Quote from: blueskull on March 05, 2016, 12:08:41 amHehehe... You are in for self punishment, right?Anyways,this referenceshows a smaller number for minimal latency. I haven't tested its premises, though.

author: Brutte
author_rank: Frequent Contributor
timestamp: March 05, 2016, 12:56:29 pm
content: QuoteSuch PID control loop can be made with cheapest op-amp. No need for ADCs, DACs and FPGA for that.

author: retrolefty
author_rank: Super Contributor
timestamp: March 05, 2016, 02:08:36 pm
content: Quote from: Brutte on March 05, 2016, 12:56:29 pmIncluding ways to enter/modify the tuning variables for every possible application?I don't think so, direct ADC/DAC is the way to go. That leaves the user program only scaling in and out units to the integer calculations.

author: Brutte
author_rank: Frequent Contributor
timestamp: March 05, 2016, 03:38:35 pm
content: Quote from: blueskull on March 05, 2016, 01:58:09 pmOh, I did not get your intentions right.QuoteI thought you have reason to PID control something that is unstable under <1MHz control loop (~100kHz analog bandwidth). Of course if the aim is to write an article about PID by proving you have made something worthwhile then indeed sticking LM324 and a bunch of passives to a breadboard won't make you famous. Perhaps, if you were to use your feet only...

author: Phoenix
author_rank: Frequent Contributor
timestamp: March 06, 2016, 05:33:39 am
content: As much as I'm a big fan of the C2000 series...QuoteThat sequence is already about 100 clock cycles.A few more things to consider with the TI's, might help:Even if you don't need floating point the C280+FP chips can do faster calculations than in fixed point, because they can do a floating point arithmetic operation simultaneously with a fixed point memory operation. I think division is also faster, even. When you use the EINVF32 and 2 iterations of newton-raphsonA chip with a CLA can let you do "just in time" ADC sample reading and processing due to the fully deterministic interrupt response time.

author: amyk
author_rank: Super Contributor
timestamp: March 06, 2016, 05:51:47 am
content: Quote from: blueskull on March 06, 2016, 04:32:22 amOn the contrary, an analog control loop can respond essentially as fast as the physics of the design allow. I think the problem is more that we have a shortage of really good analog engineers...

author: Phoenix
author_rank: Frequent Contributor
timestamp: March 06, 2016, 06:58:26 am
content: Quote from: blueskull on March 06, 2016, 06:05:34 amI was more suggesting you'd need faster than a 60MHz processor to get your 1MHz sample rate. Seems ambitious to expect to run a fixed point PI controller plus the rest you want in 12? clock cycles (ADC conversion window), I'd be interested in the outcome of your attempts.Quote from: blueskull on March 06, 2016, 04:32:22 amQuote from: amyk on March 06, 2016, 05:51:47 amA basic digital PI type controller has an inherent bandwidth limitation around 1/10th to 1/5th the digital sample rate. This is simply due to the inherent "delay" in a sample and hold process reducing the phase margin and allowable control bandwidth. You can do some more fancy control (say full state feedback), but that results in very high state gains and thus incredible sensitivity to noise. Analogue controllers on the other hand need the switch mode output to be sufficiently low pass filtered before the signal can be fed back into the control path (or sufficiently slow control) to avoid attempting to act on the switching ripple, again reducing the control bandwidth. I'd expect that these limitations are quite similar in practice. A faster switching frequency is the only way to increase the control bandwidth.Quote from: blueskull on March 06, 2016, 04:32:22 amLinear regulators are a different beast. They are not limited by the low pass filter or sampling requirements of the SMPS. Their limitations are things like parasitic capacitance/inductance. Not sure this is a fair comparison for control of an SMPS.

author: Howardlong
author_rank: Super Contributor
timestamp: March 06, 2016, 07:49:14 am
content: My concerns earlier about how this works practically in the digital and analogue domains are to do with efficiency, particularly in lower power devices, although I accept technology is always improving. For example these were two practical issues I had with the proposal:O power required to make such a PID calculation so fast in the digital domain andO losses in the analogue domain for switching transistors at high speed, eg gate capacitance.While neither are insurmountable, the cost in terms of efficiency particularly in lower power systems might make this more of an academic exercise than a practical proposition, for now anyway.I remember designing a dsPIC based SMPS a few years ago for a hand held battery powered device. During the prototyping, I found that the dsPIC was drawing in excess of 100mA at 3.3V, about three times what I expected. This turned out to be mostly the high speed PWM peripheral I was using, and intrinsic part of the original design. At that point, it was back to the drawing board, an LDO would have been more efficient!

author: Kilrah
author_rank: Unknown
timestamp: March 06, 2016, 09:53:27 am
content: Quote from: blueskull on March 06, 2016, 07:05:04 amBut as has been pointed out:- Increasing response speed of an SMPS requires increasing frequency- Due to the nature of existing switching devices, increasing frequency significantly increases the power consumption of the switching device and its driving systems, to the point that in the end you pretty much get to the same efficiency or worse as a linear regulator... while still not doing as good in terms of performance.So I doubt there is much interest in the whole thing in the first place.A good question to ask yourself is "why isn't anybody doing it yet", especially in cases like this where there is nothing revolutionary in the approach - and running the numbers you'll probably find that with the currently available core elements it simply is useless, you can add as much intelligence and logic in FPGAs as you want you won't get a better performance than what's currently being used because the low level technology/components that would be needed don't exist.About as pointless as the efforts in designing battery powered devices that simply cannot deliver with current battery technology, nothing more than a loss of time/resources. Wait until something that allows for it gets there, and by that time with the concurrent evolution of the other technologies you need to use to make the device your job will be significantly easier.If the goal is higher performance SMPS it's someone designing switching devices and drivers who should tackle it, and design the components that will enable it. It most likely won't need anything fancier than what's already in use to drive it.And I'm with the others, analog control is simpler, performance limitations come from a small number of easily characterized parameters (mainly parasitic capacitances and inductances) rather than a long chain of complex devices with so many parameters for each.Digital control is "trendy", but IMO in super high performance applications you'd have more chances to actually get the desired results with an analog solution. So the question is probably whether you want to be published for having designed a working solution to a problem, or having researched in a trendy field and come to conclusions that it's not viable?

author: Phoenix
author_rank: Frequent Contributor
timestamp: March 06, 2016, 11:16:53 am
content: Quote from: Kilrah on March 06, 2016, 09:53:27 amI don't agree with this; digital control of SMPSs isn't actually that difficult to quantify/characterize. It also makes more complex control algorithms much easier to implement.Digital is the future for many applications. I don't think the OP mentioned his application, a DC/DC converter could be mW or MW - heaps of scope for digital control. And the whole point of PhD research is to contribute to the body of knowledge... I.e. do something nobody else has done.

author: Howardlong
author_rank: Super Contributor
timestamp: March 08, 2016, 12:45:32 am
content: Quote from: blueskull on March 06, 2016, 12:08:38 pmAnd that's the point, while it's impractical now, I can well see this a reasonable solution in a few years' time.As long as the limitations are clear at the outset, which it certainly seems to be, this kind of research with the caveats is to be applauded IMHO.

author: Brutte
author_rank: Frequent Contributor
timestamp: March 08, 2016, 08:58:49 am
content: Quote from: blueskull on March 06, 2016, 04:32:22 amIf I were to develop a control loop for 100kHz BW device (be it a DC/DC), I'd have picked a 200MHz FPGA + 100Msps ADC and DAC for hadware and not a uC. Not because FPGA is necessary but because it is a cheap, flexible, off-the shelf available development tool. Job done. Then, if the devised algorithm that satisfied the requirements could be implemented in analog domain in an end product, I'd go for it. If it were not then most likely that woudn't fit into a 100MHz uC in a tight round-robin loop. Of course your 1Msps PID (or any linear time-invariant setup) is a book example of such analog case.QuoteYou have missed the core of the discussion. OP wants to do a development on possibilities of substitution of a 2MHz gbw opamp and 3x100pF caps with a 100MHz uC + ADC and a bunch of other auxiliary stuff. I am sure such PID is doable in a tight loop and it can be mass produced and sufficiently mimic a $0,1 linear PID, however I neither see the economical value nor educational value of doing PhD research on that.Oh well, times change, everything goes digital.