Older logic analyzer question. - Page 1
Forum section: electronics / testgear

author: Dan Moos
author_rank: Frequent Contributor
timestamp: May 10, 2017, 02:02:10 am
content: I just picked up an HP 1631D logic analyzer on eBay. I don't have it yet, but it was 60 bucks (plus shipping), was advertised as working, and coming from a working environment. It's in many ways inferior to the cheap, 8 channel, Chinese knock-off Saleae clone I have, but it has way more channels, and it tickles my old gear soft spot. Current project is a 6502 single board computer build, and testing it with era appropriate great seems perfect.In skimming the manual PDF, I see it differentiates between "timing" and "state" channels. Best I can tell is that the state channels require an exterior clock source, whereas the timing channels are asynchronous.What are the limitations, advantages, purposes, ect, of the two types of channels?It will come with two "pods" for timing channels, and , 3 for state channels. In the pics, it appears each pod has 8 channels, so any way you cut it, I have a lot more channels than the fake Saleae.

author: helius
author_rank: Super Contributor
timestamp: May 10, 2017, 02:31:27 am
content: Timing and State are the two basic LA acquisition modes. They were developed for the parallel bus paradigm, where devices latch data onto an 8-, or 16-, or 32-bit wide bus in response to a clock signal. This was commonly done by bus transceiver chips like the 74LS245 and others. The memory bus directly connected to a microprocessor would be another example.The names Timing and State should be entirely self-explanatory, since checking the timing, propagation, or delay of signals is a basic engineering problem. Similarly, designing and testing state machines is another basic topic in electronics and computer science.If you use Timing acquisition to probe such a bus, the analyzer is armed and waiting until its trigger condition is satisfied (the trigger condition can be complex and depend on several events). Then when the condition is true, it begins sampling all of its inputs into memory at a programmed rate, asynchronous to the DUT. This means that with a fast enough acquisition, you can record signal integrity problems such as runt pulses or glitches. Analyzing the data content itself is not feasible in Timing mode (was that two ADDQ #4 instructions, or just one?)Using State acquisition, the analyzer waits armed until its trigger condition is true, and then records a sample each time the external clock transitions (the clock can be offset by a delay from the time the sample is taken). This is how you snoop the traffic over a bus and decode each word. It also can find defective components, by sampling the inputs and outputs (of an inverter, mux, or shift register) and comparing them. An additional clock qualifier can also be used (for circuits like flip-flops that use both clock and enable signals). State acquisition is not suited to pinpoint signal integrity problems.More powerful techniques use both State and Timing machines with shared triggers or use one to trigger the other.

author: ChuckDarwin
author_rank: Regular Contributor
timestamp: May 10, 2017, 04:55:32 pm
content: I'll add the when you power up the 1631D you get a menu to individually choose if pods 0 and 1 are in TIMING or join pods 2,3,4 in STATE, and/or use only state or no state at all. If it is a 31D, you also have a 2 channel 50MHz scope. The three state pods have a clock lead (J,K or L) to get the clock from an external source.The unit generates some heat and has a loud fan. Intake in the back and blows out the right side--keep it to your left in the winter. You can put a quieter fan in with some caution.If you want user & service manuals or a getting started sheet, PM.

author: james_s
author_rank: Super Contributor
timestamp: May 10, 2017, 04:59:15 pm
content: Grab the HP logic analyzer training manual, it will explain how to use timing and state modes. When I got my HP analyzer I used a cheap little FPGA dev board to roughly emulate the original training hardware. It's little more than a counter with an oscillator.

author: TK
author_rank: Super Contributor
timestamp: May 10, 2017, 05:43:37 pm
content: If you are working with 6502, there is an inverse assembler that works on old HP logic analyzers, in state mode.

author: james_s
author_rank: Super Contributor
timestamp: May 10, 2017, 06:04:52 pm
content: Quote from: TK on May 10, 2017, 05:43:37 pmI wouldn't mind finding that, I work on 6502 based arcade game boards now and then.

author: helius
author_rank: Super Contributor
timestamp: May 10, 2017, 06:05:12 pm
content: Another difference between Timing and State modes on some analyzers is support for sample compression in Timing mode. The idea here is that you want a fast enough timebase to catch transients, but still have a long enough capture window in case the transient is infrequent. So instead of recording each bit sampled, the analyzer records the delta-t to the last transition for each channel. This would not be done in State mode, as the transitions on each channel aren't what matter; what matters is the validity of all of the channels together relative to the qualified clock. Another Timing feature is called "glitch capture": it records transitions in each channel only if the delta-t is less than a specified threshold; so only if the required hold time wasn't satisfied.

author: gslick
author_rank: Frequent Contributor
timestamp: May 11, 2017, 09:02:44 pm
content: Quote from: james_s on May 10, 2017, 06:04:52 pmOne issue with using inverse assembler software on the 1630/1631 series is that you need either an HP-IL tape drive or an HPIB disk drive, depending on what version of firmware you have, to load the software. Look at the asking & selling prices of 82161A HP-IL cassette drives on eBay, more than you paid for the 1631D. If you have the HP-IL mass storage firmware you can replace the ERPOMs with an HPIB storage version, although HPIB drives are usually not cheap either.I have a 1630D that came with the HP-IL mass storage firmware. I don't have an 82161A HP-IL cassette drive so I replace the firmware with the HPIB mass storage version. I have 8085A inverse assembler software on 3.5-inch floppy that I was able to load on the 1630D using an HPIB floppy drive.If you don't have any logic analyzer and can pick up a 1630/1631 series cheap locally without paying for shipping it's a lot better than not having anything if you need one, but once you have to pay shipping for one and start moving near the $100 mark or more total you are around the point where you can sometimes pick up a lot more modern and capable 16700 series logic analyzer system.

author: james_s
author_rank: Super Contributor
timestamp: May 11, 2017, 09:43:55 pm
content: Mine is a 1660C which I got locally for $25, it was cheap enough that it just seemed like it would be cool to play with. Of course I'd spent 10 times that by the time I had a full set of pods and grabbers but I figure I can always keep those to use with a newer analyzer if the need arises. It has already paid for itself as I used it to repair a piece of vintage gear for someone.It would be great to have a list of symbols for the 6502, Z80 and other chips of the era. My unit has a floppy drive built in, as well as a hard drive and HP-IB. I'm a novice when it comes to using these things but I've managed to figure out enough for it to be useful.

author: TK
author_rank: Super Contributor
timestamp: May 11, 2017, 10:12:44 pm
content: Quote from: james_s on May 11, 2017, 09:43:55 pmI have a 16702B, 16500C, 16500B and the latest acquisition was the 1670G with pattern generator and 2Mb option. I like the 1670G because it has color LCD monitor (VS CRT on the 16500) and starts faster than the 16702B. I used 6502 inverse assembler and it works nice. I have the Z80 inverse assembler, but could not get a clean listing as the Z80 timing is more complex and involves several STAT lines. I am looking for the HP 10300B interface or at least the schematics to check how the 4-bit STAT signals are generated from the Z80 control signals.

author: Andy Watson
author_rank: Super Contributor
timestamp: May 11, 2017, 10:24:19 pm
content: This is an interesting site for HP163x logic analysers:http://www.rudiswiki.de/wiki9/HP1631InfoSomewhere on the web there is a project to emulate the external storage via the HP1360's GPIB interface. This allows you to load-up the inverse assemblers etc.. I thought the project was on the above site - but I can't find it now.

author: gslick
author_rank: Frequent Contributor
timestamp: May 11, 2017, 11:08:52 pm
content: Quote from: Andy Watson on May 11, 2017, 10:24:19 pmI have used HPDrive to emulate HP-IB storage devices. It requires a PC running Windows with a GPIB interface that the software supports. It tried it with a 1630D and got it to work for loading configuration and inverse assembler files.http://www.hp9845.net/9845/projects/hpdrive/

author: gslick
author_rank: Frequent Contributor
timestamp: May 11, 2017, 11:24:06 pm
content: Quote from: james_s on May 11, 2017, 09:43:55 pmI also have a 1660C. It is a couple of steps up from the 1630 series (with the 1650 series in between) with a lot of improvements in usability. Built in hard drive and floppy drive for saving configuration, inverse assembler, and data files, PS/2 keyboard and mouse ports, Ethernet interface for remote control and copying files to/from the system, ability to print the screen and data to disk files, deeper sample depth (although 4K can still be somewhat limiting). If you got one for $25 that's a decent deal, but as you say if it didn't come with pod cables and breakout leads you can end up paying a lot more for those.I have the following set of CPU preprocessor modules which mate with a 10269C interface. Some of these would also work with a 1630 series with a 10269A/B interface. The 10269 interfaces are easy to find, the preprocessor modules are not.10300B (64683A) Z8010304B (64655A) 808510305B (64653A) 8086/808810307B (64672B) 6800/680210308B (64671A) 6809/6809E10311B (64670A) 68000/6801010312B (64657A) 8028610314B (64659A) 8038610342B RS-232C/V.24, RS-499, HP-IB bus preprocessor interface.

author: TK
author_rank: Super Contributor
timestamp: May 11, 2017, 11:27:16 pm
content: Quote from: gslick on May 11, 2017, 11:24:06 pmDo you have the schematics for 10300B Z80 preprocessor? I am interested in knowing how to translate the control signals from Z80 to the 4-bit STAT bus that the Z80 inverse assembler needs.

author: Andy Watson
author_rank: Super Contributor
timestamp: May 11, 2017, 11:35:39 pm
content: Quote from: gslick on May 11, 2017, 11:08:52 pmInteresting link - I wasn't aware of that project.This is the nearest thing I can find to what I had in mindhttp://dalton.ax/hpdisk/I am sure there was a more polished version somewhere - perhaps my memory is going!

author: gslick
author_rank: Frequent Contributor
timestamp: May 12, 2017, 02:34:39 am
content: Quote from: TK on May 11, 2017, 11:27:16 pmThe 10300B STAT signals in least significant order are:/WR - CPU pin 22/IORQ - CPU pin 20/RFSH - CPU pin 28/M1 - CPU pin 27/WR is fed three times through a 74LS240 inverting buffer/driver for a STAT signal./IORQ is fed once through a 74LS240 inverting buffer/driver for clock signal, and twice for a STAT signal./RFSH is fed once through a 74LS241 non-inverting buffer/driver for a clock and STAT signal./M1 is fed once through a 74LS241 non-inverting buffer/driver for a STAT signal.Maybe the multiple passes for /WR and /IORQ are to delay those signals by a few ns.That is from theModel 64683A Interface Module Z80 Service Informationmanual part number 64683-90903. I only have a photocopy of the manual. I'll see if I can get it scanned when I have time.

author: TK
author_rank: Super Contributor
timestamp: May 12, 2017, 12:24:15 pm
content: Quote from: gslick on May 12, 2017, 02:34:39 amThank you gslick. This is the information I needed!!!

author: TK
author_rank: Super Contributor
timestamp: May 12, 2017, 12:28:10 pm
content: Quote from: gslick on May 12, 2017, 02:34:39 amI was using: /M1 /REFR /IORQ //WR (/WR inverted) and feeding the clock signal directly from the Z80, but noticed that Z80 inverse assembler was asking for 2 clock signals and did not know how to generate them. Will try the new interface.

author: gslick
author_rank: Frequent Contributor
timestamp: May 12, 2017, 09:36:17 pm
content: Quote from: TK on May 12, 2017, 12:28:10 pmThe 64683A / 10300B clock signals are:/MREQ - CPU pin 19 - fed once through a 74LS240 inverting buffer/driver for clock J/IORQ - CPU pin 20 - fed once through a 74LS240 inverting buffer/driver for clock K/RFSH - CPU pin 28 - fed once through a 74LS241 non-inverting buffer/driver for clock LThe default 10300B state configuration is to clock on (falling edge of J OR falling edge of K).To filter out refresh cycles the state configuration could be changed to clock on ((falling edge of J OR falling edge of K) AND L high)

author: TK
author_rank: Super Contributor
timestamp: May 12, 2017, 10:14:44 pm
content: Quote from: gslick on May 12, 2017, 09:36:17 pmImpressive... Thanks!

author: AndersG
author_rank: Contributor
timestamp: May 25, 2017, 06:48:19 am
content: QuoteCan you elaborate?

author: Andy Watson
author_rank: Super Contributor
timestamp: May 25, 2017, 07:47:47 am
content: Quote from: AndersG on May 25, 2017, 06:48:19 amI think I may have been confusing this with your GPIB to USB convertor.Great work on both accounts.

author: cyberbarter
author_rank: Newbie
timestamp: June 20, 2019, 04:18:15 am
content: Hi TKI have a HP1670G and would like to get my hands on a floppy that has the 6502 & Z80 inverse assemblers. Instructions on loading the Inverse Assembler would be helpful as well. Can you help with that request?Much thanksCyberbarter

author: AndersG
author_rank: Contributor
timestamp: June 20, 2019, 05:16:27 am
content: It has a floppy, right? Does it take both LIF-format and MSDOS disks? Does it have a serial or GPIB port? If so then you could possibly use the utility I wrote for my HP1631D to upload the files.http://www.dalton.ax/gpib/hp1631d.zipSee:http://www.dalton.ax/hp1631D

author: TK
author_rank: Super Contributor
timestamp: June 20, 2019, 12:52:16 pm
content: 1670G has ethernet port so you should be able to download the IA files and transfer them using ftp.Check this thread:https://www.eevblog.com/forum/testgear/hp-logic-analyzer-inverse-assemblers/msg1533053/#msg1533053

author: cyberbarter
author_rank: Newbie
timestamp: June 20, 2019, 05:03:38 pm
content: Thanks TK That's what I needed. Good link. It will get me started.Much thanksCyberbarter

author: kb5mu
author_rank: Newbie
timestamp: July 03, 2019, 05:29:47 am
content: Followup question on the Model 64683A Interface Module Z80 Service Information manual ... are they also buffering the address and data bus signals? That might matter for timing.A scan of that manual would be nice to have.Thanks!-Paul

author: gslick
author_rank: Frequent Contributor
timestamp: July 03, 2019, 10:22:21 pm
content: Quote from: kb5mu on July 03, 2019, 05:29:47 amAll of the Z80 signals are buffered once through a 74LS241, with the exception of /MREQ, /IORQ, and /WR which are buffered one or more times through a 74LS240. The buffer outputs are always enabled.Once through a 74LS241 Non-inverting Octal Buffer and Line Driver:PIN 30 A0PIN 31 A1PIN 32 A2PIN 33 A3PIN 34 A4PIN 35 A5PIN 36 A6PIN 37 A7PIN 38 A8PIN 39 A9PIN 40 A10PIN 1 A11PIN 2 A12PIN 3 A13PIN 4 A14PIN 5 A15PIN 14 D0PIN 15 D1PIN 12 D2PIN 8 D3PIN 7 D4PIN 9 D5PIN 10 D6PIN 13 D7PIN 16 /INT STAT BIT 7 (Not used by inverse assembler)PIN 17 /NMI STAT BIT 5 (Not used by inverse assembler)PIN 18 /HALT STAT BIT 6 (Not used by inverse assembler)PIN 23 /BUSACKPIN 25 /BUSREQ STAT BIT 4 (Not used by inverse assembler)PIN 27 /M1 STAT BIT 3PIN 28 /RFSH STAT BIT 2, CLOCK LOnce through a 74LS240 Inverting Octal Buffer and Line Driver:PIN 19 /MREQ CLOCK JOnce through a 74LS240 Inverting Octal Buffer and Line Driver:PIN 20 /IORQ CLOCK KTwice through a 74LS240 Inverting Octal Buffer and Line Driver:PIN 20 /IORQ STAT BIT 1Three times through a 74LS240 Inverting Octal Buffer and Line Driver:PIN 22 /WR STAT BIT 0Four 74LS241 total, one 74LS240 total.

author: gotcha
author_rank: Newbie
timestamp: May 20, 2023, 07:50:14 pm
content: Hi gslickI'd be very interested by a schematics (I read this thread but I have a difficulty to transform the text into something that I could build).Did you by chance scan the manual ?Thanks !

author: gslick
author_rank: Frequent Contributor
timestamp: May 21, 2023, 12:34:02 am
content: Quote from: gotcha on May 20, 2023, 07:50:14 pmI have an original copy of this manual, which includes a schematic of the preprocessor interface:Model 64683A Interface Module Z80Service SupplementHP Part Number 64683-90903I'll have to get my scanner set up again so I can scan it.The main thing is that all of the Z80 CPU signals are buffered through either 74LS241 Non-inverting Octal Buffer and Line Drivers, or 74LS240 Inverting Octal Buffer and Line Drivers.The complication for using the original Z80 Inverse Assembler is that the CPU PIN 22 /WR signal is inverted (routed three times through a 74LS240 Inverting Octal Buffer and Line Driver) when used as STAT Bit 0. If the logic analyzer is attached through flying leads instead of the preprocessor and the /WR signal is not inverted, the original Inverse Assembler will not function correctly.The original Z80 Inverse Assembler could be modified to work when the /WR signal is not inverted when used for STAT Bit 0. If I have never posted details here on how to do that, I'll have to do that when I make some time to do so.

author: gotcha
author_rank: Newbie
timestamp: May 21, 2023, 08:51:09 am
content: FYI, a Z80 preprocessor documentation (64683-90901) and few others have been given here yesterday:https://forum.vcfed.org/index.php?threads/hp-1650-1651-logic-analyzer-disk-images.53427/#post-1317744They are now stored in bitsavers :http://bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/It doesn't seem exactly the same as yours since the reference number differs a bit.

author: gotcha
author_rank: Newbie
timestamp: May 21, 2023, 08:57:13 am
content: @gslick do you know why /WR is routed 3 times through the 74LS240 ? A single time would have been sufficient to invert the signal.EDIT: apparently, it's to make sure (through a propagation delay) the right value is sampled by the analyzer.

author: gotcha
author_rank: Newbie
timestamp: May 21, 2023, 04:21:02 pm
content: Quote from: gslick on May 21, 2023, 12:34:02 amI see 3 things with the preprocessor interface that require a particular attention:/WR (STAT0) in indeed inverted by the preprocessor interface and this would require changing the IA 'program'.If you can explain how, it would be greatThe clocks used by the analyzer to sample data are also inverted by the interface (J=MREQ and K=IORQ).The data sampling must happen at the end of the read/write.In the Z80 IA config file, the sampling is then done on clocks falling edge and should be changed to be on rising edge.This change is easy to do in the Analyzer once we have loaded the config file/WR (STAT0) has 2 extra delays and /IORQ (STAT1) has 1 extra delays.I assume that the goal is to sample /WR and /IORQ values just before the triggering sampling clock (the delay is needed because they change almost at the same time as the clocks)Knowing that one of the clock (/IORQ) is itself as a value in STAT1, the delay looks mandatory to get the right STAT1 value.Without these delays, we may experience errors/noise in the disassemblyDue to item 3, I have the feeling that we can't really invert assemble safely the Z80 with flying probes.We may need an interface, even if we don't want all functionalities and the complexity of the original interface.My target now is to make experiments with a single 74LS240 just to invert /WR and delay a bit /WR and /IORQ signals for the STAT sampling.