Fast comparator frontend/wing for Papilio/Pipistrello fpga? - Page 1
Forum section: electronics / general

author: awallin
author_rank: Frequent Contributor
timestamp: December 07, 2014, 01:37:19 pm
content: Comments on this comparator frontend for papilio/pipistrello spartan6 fpga boards?The fuse, termination resistor, and protection diodes are copy/pasted from the FMC-DIO frontend at ohwr.orgThe comparator has a rather high +/-5 uA offset current - will that cause problems?Have I read the datasheet for the fpga right? will the differential pairs work as drawn? Should the trace-lengths be matched - to what tolerance?Anders

author: tggzzz
author_rank: Super Contributor
timestamp: December 07, 2014, 02:02:30 pm
content: Quote from: awallin on December 07, 2014, 01:37:19 pmI presume so, and preferably length-matched to a fraction of the risetime.My major concerns would be:ground continuity across the connector, to avoid reflections at an impedance discontinuity. Many amateur boards fall down on this point. The last thing you want to debug is pattern sensitivity in your test equipment!impedance mismatches across this type of connector. This won't be wonderful, but I suspect the previous point will be more significantmake sure the FPGA's inputs can be set to the type of load the comparator is expecting (LVDS)Out of curiosity, what are you going to use it for?

author: mrflibble
author_rank: Super Contributor
timestamp: December 07, 2014, 03:13:50 pm
content: Quote from: tggzzz on December 07, 2014, 02:02:30 pmHow does one go about making sure this is not a problem?QuoteWhat with the fpga in there and the "TDC-input" on the pcb, I guess it'll be a TDC (Time to Digital Converter).

author: tggzzz
author_rank: Super Contributor
timestamp: December 07, 2014, 03:46:08 pm
content: Quote from: mrflibble on December 07, 2014, 03:13:50 pmFirstly it is only an issue where you have fast transition times. The bitrate is far less important, except in the cases where the signal has had sufficient time to settle before it is sampled.If you are the board designer, ideally have an impedance controlled connector and one ground for each signal or pair of signals, located next to the signals. Stuffing many grounds at one end of the connector is "suboptimum".For suboptimum placement, see the grounds on the RedPitaya E1/E2 connectors, or the Open Logic Sniffer's external clock connection.See the MicroZed (et al) connectors for a better example. There are many other examples of decent grounding, typically on FPGA modules and boards that don't get much publicity amongst hobbyinsts because they are more expensive. The Ztex boards look reasonable, as do many of the modules sold by Trenz.If you are buying a board, then all you can do is look at the schematic and connector pinout. Bonus points to manufacturers that define each trace length and/or mention the design impedance. Obviously you vote and express approval with your wallet!If you are designing an attached board, match you board's tracks' impedance to that of the other board.

author: awallin
author_rank: Frequent Contributor
timestamp: December 07, 2014, 06:46:15 pm
content: Quote from: mrflibble on December 07, 2014, 03:13:50 pmI want to try this TDC designhttp://www.ohwr.org/projects/tdc-core/wikiit was tested on Spartan6 LX45, the same fpga as in the Pipistrello. The design includes floorplanning for the delay-line and associated ring-oscillator, so that part is probably quite specific to the LX45.An fpga in a hand-solder package would be nicer for DIY building. For example the state-of-the-art Agilent/Keysight 53230A has two Spartan3s - or maybe the design can be modified for the smaller Spartan6 LX9 in the Papilio Pro.

author: tggzzz
author_rank: Super Contributor
timestamp: December 07, 2014, 08:46:21 pm
content: Quote from: awallin on December 07, 2014, 06:46:15 pmLooks fun. Please let us know how you get on!