How to troubleshoot a CD40105 FIFO register - Page 1
Forum section: electronics / repair

author: Midphase
author_rank: Regular Contributor
timestamp: April 27, 2025, 05:08:04 pm
content: I posted this question on the project forum, but I'll delete that thread as perhaps this seems a better place for it.I am repairing a key-scanning circuit on a Matrix-6 vintage synthesizer which is not working and seems frozen, and I have narrowed down the course of the issue to a DIR (DATA-IN-READY) pin on the CD40105 which is staying low instead of going high as it should to signal that it's "open for business"If I route a high signal from somewhere else to the next point of the circuit (in this case a Gate 74HC32 IC), then the circuit jump starts and works as expected until I power the unit off and back on.The CD40105 seems to be receiving a proper Reset signal on powerup, but almost immediately the DIR voltage goes low, what else could be causing this behavior? Could one of the RAM IC's that is receiving information from this chip be causing it to lock?Here is the relevant schematic and Datasheet. Many thanks for any assistance on this.Oberheim Matrix 6 Keyboard Matrix.pdf(957.65 kB - downloaded 54 times.)

author: indeterminate
author_rank: Regular Contributor
timestamp: April 28, 2025, 12:14:16 am
content: Pin 15 shift out where does that cum from.DIR sounds like it is doing what it is supost towithout a 0v pulse on SO pin 15 it will not work.

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 28, 2025, 03:49:56 pm
content: I have to say that this is a very complicated system to do a keyboard scan. Have not looked at it too deeply, but it intrigues me.The DIR signal should stay high until some data is clocked into the fifo, and stay low when the fifo is full. But you state that it starts to work normally when you make another part of the circuit high. On power off and on, the problem returns. So something latches up at that time, but the question is what.In your other post in the project section you mentioned something about a 1MHz clock not getting through. Is this information still valid?Have to do some more investigation of the schematic and the datasheets to see if I can figure this out.Edit: I'm working my way through the schematic and noticed that only one of the four shift registers DIR signals is used. What are the states of the three other DIR signals after power up?The keyboard matrix does not show this, but am I correct when I say that there is velocity sensing? This means two switches per key activated at different positions of the key movement.

author: Midphase
author_rank: Regular Contributor
timestamp: April 29, 2025, 11:15:04 pm
content: Quote from: pcprogrammer on April 28, 2025, 03:49:56 pmThe DIR's on all of the IC's are low EXCEPT for U27 which is weirdly high (even though it's not connected to anything). On the other hand, the DOR on U27 is low while it's high on all of the other 40105's. I am suspecting that perhaps U27 could be malfunctioning by not sending a high DOR signal when it needs to, possibly creating a roadblock of sorts with the other FIFO registers....is that a possibility?I have socketed all four of the 40105's, and I have ordered new ones that should arrive in a few days in case they are failing.To answer your other question, yes, the keyboard is velocity sensitive, the two sensors are registered by U43 and U44 as far as I understand, and the difference in timing between the two switches is what is computed to be the velocity value by the CPU.

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 30, 2025, 05:37:13 am
content: I have been examining the circuit a bit more, and it is a quite clever setup to do the velocity sensing in hardware.The 2114 RAM ic's are used to store the status of the individual keys. U24 and U32 store the 8 bit velocity value and U38 stores a key status. The 8 bit counter formed with U25 and U32 is used to increase the value on every clock cycle if needed, based on the key status. The tri state buffers U26 and U33 are to direct the data back into the RAM.With the two JK flipflops from U40 are used to create the phases for the state machine that is created with all the different gates.The shift registers are used to create a buffer between the two asynchronous systems. This allows the CPU to get key information at it's earliest convenience. The problem most likely is indeed with one or more of the shift registers. The fact that the DIR of U28, U34 and U35 are low signals that these are full, while U27 signals to be empty. The fact that DOR on U27 is low is correct with the register being empty. Due to this DOR being low the CPU is not taking action into reading the key data.The DIR being low on U35 disables the clock on the two JK flipflops and no key events are being scanned.So either U27 is malfunctioning and not clocking in data, or U28, U34 and U35 are defective and go on full without having received any key data.

author: Midphase
author_rank: Regular Contributor
timestamp: April 30, 2025, 05:49:36 am
content: Here is a more detailed explanation of how the circuit works logically. It is rather fascinating, and decisively more complex than similar synthesizers from the era. Oberheim apparently felt that this was a more cost conscious decision than resorting to a second CPU. They were very clever engineers for sure.http://www.tauntek.com/M6keyscan.pdf

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 30, 2025, 06:05:03 am
content: Quote from: Midphase on April 30, 2025, 05:49:36 amAt the time it might have been cheaper, but with modern MCU's or FPGA's it can be done with a single chip.