Interfacing DDR3 Ram to FPGA without the use of a PHY - Page 1
Forum section: electronics / general

author: alexxk
author_rank: Newbie
timestamp: January 31, 2017, 02:57:43 pm
content: Hello!During the last semester I have been working on the topic of DDR3 memory controller and especially the PHY part of it.The question that came to my mind was if it was possible to use a single DDR3 chip without implenting leveling on your chip (whole topic is that the institute wants to produce a network on chip, but doesn't want to buy a ddr3 PHY IP). A single chip doesn't suffer from the different way of flight provided by the on-the-fly architecture. What i have found out, FPGAs normally have special pins for DDR3 signaling, but the proof of concept would be if it would be possible without any leveling!So I wondered if it would be possible because if it is, I could do a project to design a custom pcb with FPGA (I'm thinking of using an artix-7) together with a single DRAM chip (and some extra periphery) to have a prototype to test memory controllers.DDR3-800 would be awesome, but going down to DDR2 would also be a possibility.Thanks for your help!

author: suicidaleggroll
author_rank: Super Contributor
timestamp: January 31, 2017, 04:22:13 pm
content: Check out the Digilent boards. Since you're looking at the Artix-7 anyway, pay particularly close attention to theArty. Check out the schematics, is that what you're looking for? If so pick one up and do your experimenting there, no need for a custom board.

author: Scrts
author_rank: Frequent Contributor
timestamp: January 31, 2017, 04:29:26 pm
content: I'd say you shouldl ook into how the soft memory controllers are done.

author: nctnico
author_rank: Super Contributor
timestamp: January 31, 2017, 05:59:19 pm
content: I think it is possible if you can adjust the delay in the inputs on the fly for run time calibration. That way you could ignore the datastrobe during read (only drive it during write). It would require to write a known-good pattern into the DDR memory at low speed, switch the PLLs on and drive the DDR memory at the desired speed and do the time delay calibration. This is basically how high speed DDR controllers initialise the memory. I'm not a fan of the FIFOs found in many DDR controllers which take the datastrobe and use it as a local clock source. It largely obfustigates things. You already have a fully synchronous clock inside the FPGA which drives the DDR memory but you just don't know the delay between the incoming data and the clock (hence the requirement for calibration).

author: alexxk
author_rank: Newbie
timestamp: January 31, 2017, 07:31:53 pm
content: Quote from: suicidaleggroll on January 31, 2017, 04:22:13 pmOn the Arty, the DDR is hooked up to the PHY of the FPGA, and this would be about doing it without a PHY!Quote from: nctnico on January 31, 2017, 05:59:19 pmWell, adjusting the inputs on the fly is basically leveling :/ But what I have found out, thats how FPGAs do it. But getting an FPGA where I could adjust them on the fly would be really nice to get a prototype for a memory controller + PHY going. Do you have an idea what devices support those features?Time delay calibration could also be done using read leveling features of DDR3 (Multi Purpose Register, activatign it return 10101010 for every read command), right?Thanks so far!

author: suicidaleggroll
author_rank: Super Contributor
timestamp: January 31, 2017, 07:41:41 pm
content: Quote from: alexxk on January 31, 2017, 07:31:53 pmSo?This is an FPGA, don't use the DDR3 controller and they're just regular GPIOs.You do know the Xilinx DDR3 controller is free, right? Use it, write your own, do what you like. If you want to roll your own because you want to improve performance, or you want something portable, or you just want the experience, then knock yourself out, but that doesn't preclude you from using a board where the DDR3 module justhappensto be wired up to the pins necessary to use the internal PHY.

author: BrianHG
author_rank: Super Contributor
timestamp: February 01, 2017, 06:48:36 pm
content: A few years back, I did a home made 400Mhz DDR2 controller on an Altera Cyclone III. I made sure all my DQs and DQSs and controls used the IO pins DFFs, and clocked the memory with the PLLs dedicated differential outputs, and clocked the DFFs with set phases from the PLL. I used 666Mhz SODIMM module ram for the slightly wider eye pattern from the memory. After finally getting the memory power-up sequence & configuring correct, setting the PLL to get the right read and write timing, my ram controller, nothing more than a programmable sequencer which took in 8 read/write port addresses & data, with a command & priority encoded sequencer. Everything worked like a charm, however my code was optimized to huge 32/64/128 burst reads, no single byte writes supported making it all to easy to develop. If you don't need performance, 8 bit writes and reads are just as easy. A bit of the nightmare comes when you want to change bytes withing a burst, supporting read/modify/write & sophisticated bank interleaving to minimize RAS changes, or properly pre-charge interleaved banks to eliminate any wasted data clock cycles.If you can code VHDL, or Verilog, don't need the absolute tightest most efficient memory access cycles, good with defining your development tool's IO timing setup & PLL configuration, you should be able to make your own PHY, otherwise, you'll be stuck trying to get your memory working for months & you will need to do memory integrity tests galore. DDR2/3 memory can be a finiky thing, especially from manufacturer to manufacturer where some ram will be very forgiving and always work fine even if you violate a spec or 2 from the defined standards. You will also need to do a full temperature sweep test of your hardware and for 800Mhz, you are at a point where you need to take into account trace lengths on your PCB unless you use faster ram to give you a little extra timing breathing room.Since my memory was being used as video buffers, continuous reading/writing/displaying, any data corruption was immediately evident on the display output. You might not have this luxury especially if your ram also stores you functioning software. Your design may crash for unknown reasons.

author: julianhigginson
author_rank: Frequent Contributor
timestamp: February 01, 2017, 11:00:20 pm
content: Quote from: alexxk on January 31, 2017, 02:57:43 pmwait.. I'm confused.The whole point of what you are doing is you don't want to pay for a paid IP for some other specific project. Fair enough.But you plan to use an artix-7 (which has the PHY controller/IP for free? yes?)So.... why can't you use the free ARTIX7 PHY?is the actual requirement "full open source" rather than "free of cost"?

author: alexxk
author_rank: Newbie
timestamp: February 02, 2017, 08:36:30 am
content: Quote from: julianhigginson on February 01, 2017, 11:00:20 pmThe main goal is to produce an ASIC! So the requirement is full open source. I am currently trying to find out if it would be valuable and possible to test the PHY design on a FPGA. Sure this would only verify some of the features and a first step, since the IO pads would be missing, the variable delay chains would be the ones produced by the FPGA manufacturer and so on!

author: julianhigginson
author_rank: Frequent Contributor
timestamp: February 02, 2017, 09:13:03 am
content: aaah. fair enough. I must have missed that snippet of info. :-)Sent from my A0001 using Tapatalk

author: nctnico
author_rank: Super Contributor
timestamp: February 02, 2017, 03:30:21 pm
content: If it is an ASIC design I'm not sure how much value there is in an FPGA prototype. I think there are simulation models for DDRx memories out there you could verify your logic against. Also in an ASIC it would be way easier to use the data clocks to align the data edges so variable delays may not be necessary. IMHO FPGA and ASIC are too far apart to prototype a high speed hardware interface in an FPGA.

author: BrianHG
author_rank: Super Contributor
timestamp: February 02, 2017, 06:50:55 pm
content: Unless you are converting your design to an asic yourself, most ASIC conversion outfits will end up having their own ram controllers that are optimized for their silicon and their internal PLL capabilities.In the past, I know that a few ASIC fab houses told me that they had engineers who would convert from my Altera Quartus design, that the more my code was VHDL/Verilog, the better, but, high speed time critical items like PLL, ram, above 500Mhz serial ports, they would have to use their own modules, just like Altera has dedicated function IO pins and pin groups for these purposes which cannot be avoided if I want my FPGA version to achieve modern top ram and network speeds.