Wounded in Combat: Attacking DIY SMPS + Linear PSU Overshoot Under Load - Page 1
Forum section: electronics / beginners

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 13, 2019, 06:18:31 pm
content: hi, i built dual rail tracking PSU (the poorman emitter follower + opamp method). now debugging +ve rail only. this is version 2, earlier version 1 worked acceptably, but the trouble in newer version 2 is addition of smps preregulator. when under load (tested with 0.5 - 2A) there is about 1 volt voltage overshoot on the output for longer duration. when no load, the overshoot will be quickly recovered. the circuit is 1st attachment. if its difficult for you to understand i provided logical step from where it started in 2nd attachment. if components value is not given (*) it means its not populated.img622375here are few snapshots. when SMPS1 SWC (yellow) goes low it means SMPS turned on ie charging preregulation capacitor VSS+ (cyan), OCTL+ (purple) is opamp (uA741) control of output voltage VO+ (blue). you can see the 1V overshoot/spike there (6us the longest) on the 5V output..img622387here is 2nd snapshot probing uA741 inputs, but it doesnt show anything helpful on the cause of the overshoot...img622393so i was concluding its the slow uA741 respond to be blamed, so i switched opamp to TL071 (both are probably china cloned, but probably legit). TL071 shows quicker respond at recovering the overshoot, but its still there. here's the snapshot using TL071.img622399img622405now i can blame on both opamp abysimal performance and find better and faster more modern opamp but...1) the supply is ±20V not all my opamps support that. i have one faster opamp left OPA2604 (also sourced from China) but maybe i'm shooting at the wrong enemy anyway, it maybe still there (albeit shorter and shorter duration) even if using the fastest opamp in the universe. so i'm asking for ideas and thoughts here before moving to faster opamp.2) maybe there is something else i missed, maybe is this inherent to the bjt emitter follower + opamp topology that i did? or something else?. i beefed up gnd power return path by adding wires on bottom layer, pcb is single layer (see attachment), i want to save my double sided copper clad because nothing much on top layer, the top layer is just few connecting and power wires. i've added decoupling capacitors on each opamps power rails, i'm not sure if its necessary for slow opamp but i thought it improved smps spikes here and there. i used diy or custom probes to achieve shortest gnd clip possible to rule out probe gnd loop effect. i tried long and short gnd clip and directly to output's gnd wire. so i'm pretty sure the overshoot is not gnd clip loop. longer duration in micro second range also proved its not loop ringing.so guys what is it i'm dealing with? its been a week for this very simple crap. i'm wounded now (outta idea) need healing potion...

author: AnalogSteph
author_rank: Newbie
timestamp: January 14, 2019, 12:51:32 pm
content: Nothing wrong with a modular approach per se, but this schematic is a real pain to read like that. It is essentially the antithesis of a vintage Marantz receiver schematic (which also is very hard to follow but for exactly the opposite reasons - the optimum would be somewhere in the middle).Anyway... you didn't say what your testing conditions were (nor does your scope make it obvious where the 0 V level was for all the traces), but I guess these overshoots occur after removing the load, right?I think what's happening is the following:1. Your pre-regulator is much faster than the main regulator. If output voltage "snaps back" after the load is removed, this gets transmitted to regulator input voltage very quickly. In a way, you have bootstrapped your main regulator - meaning higher input impedance, higher output impedance. What you want is having the pre-regulator referenced to outputtargetvoltage rather thanactualoutput voltage.2. AFAICS, standing current through the output Darlingtons in a no-load scenario is going to be just about exactly zero. Therefore, B-E voltage drop is going to vary a lot depending on load - where under load both transistors operate, in idle one of them will be able to maintain voltage just fine. So the opamp output would have to make quite the jump. Also, your supply has no way of bringing the output down actively - current can only flow out but never back in. So when a load is being removed, the output transistor is still saturated and its base charge has nowhere much to go, and all the loop can do is pull base charge out of the first transistor.If nothing else, you should provide a minimum load on the output. (Alternatively, maybe even make the output stage AB push-pull. The "pull" half could be substantially weaker, of course. Maybe a CFP with BC547 + BD140. Or implement a low-dropout current source. Something like 30 mA should be plenty OK.) A Darlington with no standing current will bevery slow. Might explain why your output is not fond of capacitive loading either. Also consider going discrete rather than integrated Darlington, which would give you access to the internal nodes.BTW, your approach of transistor "back up" is just about completely broken. For one thing, you will have random current sharing between one TIP122 and the TIP142, and then transistors have a habit of failing short rather than open.Is your buck regulator circuit pre-tested? For as little as I know about SMPS, a switching MOSFET driver with a bunch of hysteresis doesn't strike me as particularly beneficial. You sure you can't spare one 1N4148 to go between the bases of 3904/3906 at least?What's the theory of operation for the tracking circuit? Why does it apparently involve a µA741 misused as a comparator? Is there no way it can be done in a linear fashion?Have you simulated any of this beforehand?

author: Kleinstein
author_rank: Super Contributor
timestamp: January 14, 2019, 12:58:53 pm
content: The circuit diagram is rather hard to read with so many just named signals. Usually most connections should be by lines.As it's only about the positive side, why not have a drawing with only the positive side.The capacitors C4 and C6 look like a bad idea.There is no need to get the full supply voltage to the OPs. E.g. the OP for the positive output would be happy with +25 V and - 5 V.There is no need for faster OPs.I see no short circuit protection. At least a crude current limit would likely be a good idea. The 0.1 Ohms emitter resistors are too small to do load sharing for the TIP122. For those small Darlingtons it would more about 0.5-1 Ohms.

author: coppercone2
author_rank: Super Contributor
timestamp: January 14, 2019, 01:02:41 pm
content: i hate giant schematics on one page.what you should do it make abstractions:1) block diagram with words2) block diagram without circuit elements, i.e. triangle with G=10 for a gain10 amplifier, triangle with a integral f3db=x for a LPF, and so on. If its passive then just put a box rather then a op-amp triangle3) advanced diagram that shows the component values etc but does not have repetitive circuit elements like decoupling caps4) play by play of every significant circuit junction where all factors can be taken into account if necessary, down to the decoupling capacitors with circuit notes about PSRR rejection curves, bias currents, etc.If you are comfortable with only 2, then skip 3 and put every single circuit thing on a different page so you can scan through it and put all the relevant equations etc on it.It sounds like alot of work but not really.I consider a big lumped thing like that something to put into a part replacement repair manual. You can't do serious analysis on that. It is not a engineering document. You don't even have a signal chain.It has to fit the desk form factor,If you had a giant touch screen table (think the table from the colony in Aliens that had the colony schematics on it) then you can get away with a A-giant size document where you have the entire circuit as its connected.Then it becomes a question of ergonomics if you like pressing a 'next page' button or if you prefer zooming. I think both have their place for different headspaces you might have during design.Do not ask people to trouble shoot documents that don't use connection lines. Or at least, don't expect them to work with them as is, you need to re-write that whole thing for yourself. If I get asked to deal with shit like that, to do a good analysis I would re-write it, then have a step 5 which is like four but with every single block on a separate page for notes. You dissect it and study every organ separately. Combine them into larger chunks when you are done if you please to study their interaction. I actually make separate analysis and description documents for every subsection.Then its much easier to look at something 5 years later if you need to increase performance, decrease suceptance, add redundancy, reuse parts, etc.If you have alot of different reuseable subsystems you put it into a bulk document that is attributed to all projects.Notes are useful because you can note your noticed peculiarities of the part/circuit (i.e. this design benefits from integrated thermal shut down, this op-amp is particularly unstable compared to most things I am used to, this circuit is a bit weird but it fits the form factor). This often prevents you from going around in circles or makes you realize you don't know enough about that part. Or you just write something like 'pulled directly from app note' to increase confidence.I highly recommend the top level diagrams are done with a program like Visio (not hard to learn it). rather then a PCBCAD program unless it has a top-level functionality, like those german programs but they are $$$$$$$$$$

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 14, 2019, 02:49:51 pm
content: Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmsorry i tried to cramp all those in one single sheet. but its actually a very simple circuit, not like other fully discrete transistors based linear regulator solution around here, i have to rotate head right and left to see where a transistor goes, its just my incompetence in transistor level design... when they tried to combat mV or uV of noises, i tried to combat V level of overshoot hereQuote from: AnalogSteph on January 14, 2019, 12:51:32 pmsorry i didnt see what you dont see, i was typing too much trying to explain it in the OP until i forgot what is what. 0V level is the same for all channels, you can see 0V for CH1, thats the same 0V level overlapped behind for CH2-4, except different V/div scale (you can see at the bottom of every capture)the capture/test is fully under load. 1A of load, using my diy constant current load. i checked current draw within the constant load its ok, its unrelated to the overshoot figure/shape. it recovered as it should be when overshoot or undershoot occured (see last attachment). when the circuit is not under load, the overshoot/ringing is very minimized or none at all.Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmthe circuit has active pull, see description below...Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmas i said, i'm incompetent in transistor level design. i know few transistors based PSU here (amspire's iirc is one of them), but i just dont understand how every bjt works and what their purpose. try to ask them i think is like a kid asking every single part in automotive, maybe will bore many big guys people...Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmi agree its not as robust and as stable as other PSU design, but 1V overshoot is just specifically unacceptable, this should be easy to tame i guess by most expert around here, its not like taming mV of spike, so thats why i published my query. earlier i put big capacitor 1000uF on the Vout, the 39 ohm pull down resistor (R6) is smoking like not so crazy, but its an unnecessary waste of power during idle, so i reduced capacitance to 10uF and its stable for now. but just in case end user will put capacitive loading on the output, i've reduced pull down resistor power as well (increase resistance) to 220 ohm.Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmthey are not meant to work together, either use a pair of TIP122s, or a single TIP142. i just provided the footprint in case i want to use TIP142 (but both TIP122 must be removed with redundant balancing power resistor R8, otherwise i guess some smoke will emerged)Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmtracking means, both +Ve and -ve rail will have same magnitude with a single potentiometer control, ie single voltage reference to control +Ve and -ve rail. the SMPS voltage output that feed linear regulator is set (adjustable) to be slightly higher 1 - 6 or so volt than the linear regulated output (VO+) but lets look at +Ve rail only for now to avoid further confusion.Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmthere is no opamp (uA741) is configured as comparator, every one of them has feedback from output voltage they are meant to control, in 5-6X gain configuration (since voltage control is 5-6X than TL431 reference, 2.5V max translates to 2.5 x 5 or 6 = 12 - 15V output max.Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmno, iirc. i dont trust simulation will reflect reality as i think i dont have every part model available in a sim, and i'm no sim (script) expert either. i will use sim for new topology/concept that i've never done before, but only rough estimate of performance and stability analysis, i dont expect them to match reality 100%. this topology in the OP has been working in circuit version 1, so i dont think sim is necessary. moving to "real world" performance is the stage i'm currently at. but maybe i'll consider SIMing it next time with this SMPS (spike and overshoot) addition.Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmits working as it should in my current circuit.its just the switching will propagate into linear output stage, its like the linear stage has 0% PSRR for a moment.Quote from: AnalogSteph on January 14, 2019, 12:51:32 pmi'm not sure why, can you explain?let me run through it for you and others fwiw... in step by step.the heart of this PSU (brought from version 1, except with added active pull down) is darlington emitter follower controlled by opamp feedback from output voltage divided by 5 on its inverting input and reference voltage on its non inverting input. as pictured below. i really dont know how to explain this any simpler, since in eevblog level, anyone who is eligible to give an advice, will quickly recognize this. its a very simple thing in the universe, not like many transistors upside down topology that makes my brain hurt.just notice, the opamp and darlington are feed from different power rails, VCC+ unregulated input voltage ±20V (going to ±15V or ±10V during loaded event, bigger input capacitor tank will improve 50Hz sag C1 and C2 in complete sch leftmost topmost) for opamp for maximum swing control and pre-regulation output VSS+ will power darlington and push pull driver. VSS+ may vary from 20V - 1V depending on Vout setting (15V down to virtually 0V). thats why there are clamp diodes on the push pull base. you can see the active pull Q5 (BC516) and weak pull 220 ohm resistor R6 are there in case of overshoot during idle operation (unloaded), during loaded event this pull mechanism should stay idle (pull is done by the external load) and not in the picture i forgot to edit, is 10uF output capacitor and protection diode. (D4, C7 in complete schematic in OP, rightmost)whats important not in the picture above is (1) VCC+ (2) Vref (3) VSS+ lets go VCC+ first. picture below, the battery symbol is connectors to mains 50Hz transformer 20Vac output, a smaller one, and then setup to give ±20V in voltage doubler config. done, thats easy.VCC+ will go to 2.2Kohm and TL431 for main 2.5V voltage reference. across the 2.5V reference is 10Kohm trimpot, this is the user interface to control output voltage VO+. from 0V to 2.5V, multiplied by 6 will be 0 - 15V output. the trimpot voltage level is buffered by opamp uA741. due to i sensed unstability, i've added 10ohm and 4.7nF (can be any value i guess but not too big) on the output and become Vref, the main control for smps voltage level, linear output level for both +ve and -ve rail. any question ask, any complaint shoot. do not hesitateVSS+ smps pre-regulation output will get its reference from this (picture below) Vrfs. a jellybean simple 2 diodes voltage increase, and another (internal) small trimpot across them to set how much excess SMPS compared to VO+ voltage, set by designer's desire (which is me) once and done, after everything are ok. its 0 - 1.4V increase 5X multiplication in control system will reflect in 0 - 7V bigger than linear output. please note i should buffer this Vrfs since its high impedance, it was my careless mistake, now my -ve rail is not symmetric, but leave that alone for now, thats another thing to tackle later (or maybe i have to respin pcb making with the better updated design)now we go to the new part, smps pre-regulation get its command from Vrfs reference... opamp will sense VSS+ output, in case less than Vrfs x 5.65, it will give less than 1.25V output (mc34063 smps internal reference, refer to datasheet) to CII compare pin and will force 34063 to turned on (low on SWC due to connection to SWE and resulting p-mosfet AO3401 to turned on) this should be pretty simple to experienced people, just how optimum is this setup i'm not sure, all i know is it works as i intended it to be. the end result, is smps regulation on VSS+ to be a little higher than VO+ (Vref x 5.65 or so), so less Vce on linear power element, less power dissipation, less heat less risk of damage, thats its purpose.man, i'm not sure if its worth explaining it all this long since there seems to be less interest with lack of respond after 100+ of view, or maybe spaghetti schematicsbut sorry guys i think i prefer this way for compact view all in one page for now, i hate many pages when designing things, altium is slow you know. but maybe noobs like me may benefit from this? fwiw...

author: coppercone2
author_rank: Super Contributor
timestamp: January 14, 2019, 03:08:05 pm
content: when I make my reference documents with altium I actually make 1 giant schematic on a oversized sheet and use MSPAINT for stitching together the diagrams. I also noticed altium is kinda laggy.Altium's circuit-studio program is actually really nice TBH.I think your circuit is interesting and rather complicated and I think it will take some time to analyze it. You need to give people lots of time for this beast.Also this is debatable, when drawing schematics some people (including myself) always put a separate ground and VCC for everything since then you can attack it in a totem pole fashion. This was a requirement for my university design classes and I stuck with it and I found it helps to clarify stuff. And always have the Power-connections come from top down and ground facing bottom, even if you need to put a stupid little bend.Too scared of bends = you flip a op-amp picture upside down for appearance sakes and it causes all sorts of messes with people that don't pay attention to the polarity markings.I think some people like to link them because they don't use power planes and it helps them think but I think on the schematic it should assume the best possible conditions as power planes and not force the person to think about the inductance from trace splitting when doing the top level analysis.The areas of debate would be flyback diodes on switching outputs and possibly tank circuits, but IMO thats a fairly isolated case. the loopy grounds here might make someone renember about the recycling going on, but not in the case of the state of a IC/decoupling pin.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 14, 2019, 03:22:18 pm
content: Quote from: Kleinstein on January 14, 2019, 12:58:53 pmthanks for the advice i will keep in mind and try my best laterQuote from: Kleinstein on January 14, 2019, 12:58:53 pmyes i agree it will lag opamp respond significantly, but luckily having expecting this, its not installed, its just provision.Quote from: Kleinstein on January 14, 2019, 12:58:53 pmit will complicate the circuit, i will need to add -5V and +5V rails for them. i try to make this KISS when not really necessary.Quote from: Kleinstein on January 14, 2019, 12:58:53 pmgood to know this, but still, not sure what causes the overshoot.Quote from: Kleinstein on January 14, 2019, 12:58:53 pm100% agree, i'm well aware of this. a brief short will probably smoke the TIP122 pair, i have to be very carefull. i'll see if i have room to add current limit feature when everything works later.Quote from: Kleinstein on January 14, 2019, 12:58:53 pmthanks for the advice, this is the kind of advice i need from more experienced people

author: David Hess
author_rank: Super Contributor
timestamp: January 14, 2019, 09:10:13 pm
content: The control circuit is driving the Darlington output transistors hard into saturation which by itself adds at least 2.5 microseconds to the recovery time.Slewing through the Vbe drops of the class-B driver stage takes an additional 1.2 microseconds. Converting the driver stage to class-AB with 2 more diode or transistors would remove this. Most designs use a class-A driver.The output capacitance is low for this type of design.The 741 is plenty fast for this application. The rest of the circuit needs work.

author: Cliff Matthews
author_rank: Unknown
timestamp: January 14, 2019, 10:18:50 pm
content: Lot's to learn here!

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 14, 2019, 11:41:20 pm
content: Quote from: David Hess on January 14, 2019, 09:10:13 pmlots of golden pointers here but very little to explain or hint what about. for example, i dont understand how darlington went into saturation when its in emitter follower mode. i've read class a,b,ab amplifier several times i thought i understand them but when some people talked about them i felt like clueless its like something big i've missed. for what i know, when the PSU is under load, it will be in class b mode, full conduction so to speak in quadrant I area. but well, whats certain, is i need to learn more about transistor behaviour esp under transient mode, and its slew rate or sort of propagation delay or internal capacitance and what not. thanks for the advice.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 15, 2019, 02:47:56 pm
content: i think i've found the problem. its Mr Murphy (the devil) came to have a peek a poke at me. while turning the board up and down, placing probes here and there, i didnt notice that Vrfs trimpot was accidentally turned so low, that there is not enough headroom for linear stage drop (i guess) hence opamp cant control it properly, thats why the opamp output skyrocketted earlier, due to this inadequacy, and darlington's Vemitter just followed the Vcollector swing mimicking 0% PSRR. with enough headroom, everything work back to normal. except there are still a bit of ringing inherent to every smps switching, but thats a different bit to tackle, for now the overshoot disappeared and its in acceptable region now. thanks guys for looking. this is just a waste of time for careless stupidityhere are the (reduced size to better see the overall) snapshots of different Vss+ level (cyan) and its effect on the linear regulated output VO+ (blue). left to right top to bottom numbered 1-4 (increasing Vss+ level) just look how nasty and hard the opamp output (purple) tried to stabilize things in snapshot 1 to no success... poor uA741... btw, time and break is a good healing potion... fwiw...

author: coppercone2
author_rank: Super Contributor
timestamp: January 15, 2019, 02:50:00 pm
content: people often add series resistors to trim pots to prevent then from operating in bad conditions you might want to update your circuit, its a easy way to blow something up

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 15, 2019, 03:01:49 pm
content: Quote from: coppercone2 on January 15, 2019, 02:50:00 pmlooking at Vrfs trimpot, there is no real harm if the trimpot accidentally turned to max low or max high, there is 4.7Kohm high impedance protecting it. the worst case is the poor output performance as we saw here, or there will be too much (Vrfs - Vref), too high Vss+ and hotter linear stage, even if Vss+ maxed out to Vcc+ (in case of burnt short smps stage), this is how it was working in psu1e (earlier version 1) without smps pre-regulation feature. in fact, this later version psu1g can be made like how version 1 was working, ie depopulating (disabling) smps components and just shorting Vss+ node to Vcc+. the version 1 blown after years of service.fwiw.

author: David Hess
author_rank: Super Contributor
timestamp: January 16, 2019, 12:01:16 am
content: Quote from: Mechatrommer on January 14, 2019, 11:41:20 pmWhen Vss is low, the operational amplifier drives the base of the Darlington pass transistor hard to raise the output which will never happen. This leads to the pass transistor and drive transistor in this case being saturated.QuoteThat would be class-a but what we have here is class-b because there is a 1.2 volt voltage difference or "dead zone" between the bases of the driver circuit. The output of the operational amplifier has to transition through this 1.2 volts before the output current from the driver reverses. A class-a design would replace the lower PNP transistor with a resistor or current sink so that the output of the driver always follows the output of the operational amplifier. A class-ab design would make both transistors of the driver always conduct at least a little bit so there is no "dead zone" for the operational amplifier to slew through to control the output.Note that the design example below has this same problem to come extent when switching between constant voltage and constant current modes.QuoteMost of the problems here are just caused by the large dead zone in the class-b driver and allowing the output pass transistor to saturate. Integrated linear regulators often include anti-saturation circuits to prevent exactly this sort of problem. A bench power supply might disable the output by zeroing the reference until the input voltage to the pass transistor is sufficient.The example shown below handles this problem in two ways:1. During startup, Q15 and Q115 directly clamp the outputs of the operational amplifiers until their supply voltages are high enough for proper operation. This is especially important in this case because during startup, the common mode input voltage of reference operational amplifiers U35 and U135 and voltage control operational amplifiers U45 and U145 is violated. All operational amplifiers in this design are 741s or 301As.2. Reference circuit VR25/Q25/Q30 ramps up slower than and is dependent on the supply voltage. When the output is disabled, it is the reference which is shorted and C34 controls its rise when it is enabled.