How can I kill this bug in my Data logger Code? - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 18, 2022, 09:09:01 am
content: Hi,I'm using Gowin FPGA, the part number is GW2AR-LV18QN88C8 which has 20K LUT and internal 64Mb SDRAM, I have designed a data logger, that would capture ADC data and saves it into internal SDRAM, the program should work as follow, it should save data a configurable amount of time for Pre and post trigger event, so I can see what was happening before and after the event,I have applied a sine wave to the ADC, and the ADC core is working perfectly, it spit out ADC data to the Recorder logic, I think I have some problems with the Reading logic, I got some distortion in the read data logic, here is my Recorder state machine logic code,I have tried many times to figure out what could be the problem?Do you have any Idea what I might have done wrong?Finally I have solved it!

author: mfro
author_rank: Regular Contributor
timestamp: January 18, 2022, 11:36:29 am
content: Quote from: ali_asadzadeh on January 18, 2022, 09:09:01 amI do.You missed to simulate your design. If you did, you would most likely already have found the problem.

author: Bassman59
author_rank: Super Contributor
timestamp: January 18, 2022, 05:22:39 pm
content: Quote from: mfro on January 18, 2022, 11:36:29 amThis is the way.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 18, 2022, 06:10:04 pm
content: Ditto. I can't even understand the idea of trying to debug a design written in some HDL without simulation. At best, this is usually terribly inefficient, and at worst, you may just never figure it out and claim that FPGAs are crap. (A less generalized variation of this would be to put the blame on the FPGA vendor. Yes, I've seen this.)

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 19, 2022, 07:31:45 am
content: I know the way to do it is simulationThe problem is that I'm using Gowin Internal SDRAM IP and unfortunately Gowin does not provide any means for simulation their IP.So Imagine that you have a Black box in your FPGA design that you can not simulate it, how do you solve your problems?

author: mfro
author_rank: Regular Contributor
timestamp: January 19, 2022, 08:29:49 am
content: Quote from: ali_asadzadeh on January 19, 2022, 07:31:45 amIf you have a black box in your design, you should at least have documentation on how this black box' interface is supposed to behave (at least it was good enough for you to attempt implementing a design around it first place, wasn't it?).

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 19, 2022, 08:42:49 am
content: I have attached the Documentation in the first post, I think I have done exactly like the docs, But do you suggest how it should be done?

author: mfro
author_rank: Regular Contributor
timestamp: January 19, 2022, 08:45:43 am
content: Quote from: ali_asadzadeh on January 19, 2022, 08:42:49 amWrite a simulation model based on this documentation and simulate, as you've been told already.

author: Bassman59
author_rank: Super Contributor
timestamp: January 19, 2022, 03:10:51 pm
content: Quote from: ali_asadzadeh on January 19, 2022, 07:31:45 amFPGA vendors that will not provide simulation models for hardware features of their devices are scratched off of the list.