Affordable Xilinx UltraScale+ Kintex dev board on CrowdSupply - Page 1
Forum section: electronics / general

author: agilmine
author_rank: Newbie
timestamp: October 05, 2019, 04:51:02 pm
content: HiI am the maker of UltraMiner FPGA, I’d like to introduce you to our project, which will be launched on CrowdSupply platform soon!https://www.crowdsupply.com/agilmine/ultraminer-fpga(please sign up for project update if interested!)Our FPGA board is designed with the latest Xilinx 16nm UltraScale+ Kintex, very high performance and power efficient. The TI PMIC (power management IC) on board is capable of supplying up to 60A constant load to the FPGA chip. It would be an ideal dev platform for any RTL designs requiring high processing power, you will never run out of logic resource or power.The Best part is the price, by cooperating with cryptocurrency mining facilities we are able to bring up the production volume so as to lower the per-unit price. The developer version is priced only at $429 I believe it is the lowest priced UltraScale+ Kintex dev board you can find in today’s market. Plus the Vivado license is for free, that saves you another $2k!Developer version: $429 (with PCIe)Crypto Miner version: $399 (bundled with CPU cooler)We promote Open Source, all the software and drivers will be open, including the cryptocurrency algorithm rtl designs, that you can use them for mining right away!Please shoot me email for any questions. I would be more than happy to answer them here as well:dev@agilmine.comTechnical Specifications• Processingo Xilinx Kintex UltraScale+ KU3P (TSMC 16nm FinFET+) System Logic Cells: 356K DSP Slices: 1,368 Memory: 26.2 Mbo 125 Mhz ultra low jitter crystal• Connectivityo 1x Micro USB to I²C, SPI and 2xUARTo 1x JTAG porto 1x SPI Flash (128 Mb)o 1x PCIe 6-pin Power Adaptero 2x GPIO pinout connectors (1528-1385-ND) 16 HPIO pins (1.8 V, higher speed, LVDS compatible) 17 HDIO pins (3.3 V, lower speed)o Developer Version: PCIe x4 Gen 3• Power Managemento TI high efficiency PMIC with 90 W Max power outputo Dynamic Voltage Control and monitoringo Cooler/Heatsink sockets compatible with LGA115X (90x90 mm) & North Bridge (40x40 mm)• Open Source Softwareo Free webpack license for Vivado Design Suite from Xilinxo Various pre-built algorithm bitstream files included, ready to useo Cryptocurrency algorithm bitstream design and host softwareo C library provided for power monitor and management, FPGA flash programmero Cross platform support on Mac OS, Windows, Linux and Embedded Linux (Raspberry Pi)

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 06, 2019, 01:09:47 pm
content: The number of high speed I/O interfaces is really low for that class of FPGA board, I can see it being interesting for really advanced amateur radio experimenters if there was a way to connect many high speed ADCs/DACs for MIMO SDR.I also don't see any mention of external DDR memory, so even for crypto mining it's liable to become obsolete as quite a few coins are making use of algorithms that require more memory in order to limit the advantage FPGAs and ASICs have.

author: agilmine
author_rank: Newbie
timestamp: October 07, 2019, 02:50:22 am
content: Hi Thanks, yes it is designed to be a miner only version to begin with, and later we think maybe it is good to make it available for developers.for now, based on the feedback i think the only interested group are the cryptography, which is essentially the same as mining in terms of operation.good point on the MIMO SDR, i will look into that as well.the memory bandwidth is always a bottleneck on the fpga, i don't think adding any memory would help, because it would be too slow, compared to the gddr.. only exception is HBM2, but the price would not justify the performance (for mining)...there will always be new coins coming out, not memory intensive ones, recent example is 0xbtc and ODOcrypt

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: October 07, 2019, 02:08:59 pm
content: The board would be useful for radio/SDR applications if it included one or more FMC connectors to which some of the high speed I/O is routed (for JESD 204B). Many high speed ADC/DAC or transceiver eval boards come with FMC I/O.

author: daqq
author_rank: Super Contributor
timestamp: October 07, 2019, 03:07:15 pm
content: Nice boardThough I would suggest what the others have already recommended: MORE IO!You wouldn't need to even add a connector, just a placeholder, holes for one or the footprint of a popular SMD one.

author: agilmine
author_rank: Newbie
timestamp: October 08, 2019, 03:03:48 am
content: hi thanks for the good comment. someone recommended adding many plain 2.54mm pin header GPIOs as differential pairs, so as to connect to an ADC/DAC chip breakout board like AD9363, would that be a good alternative to the FMC connector?thanks, i don't know much about SDR, trying to make this FPGA board be more useful to people who doesn't mine crypto!

author: agilmine
author_rank: Newbie
timestamp: October 08, 2019, 03:08:31 am
content: that's some good tip. thanks. do you have any suggestion on which connector should be added ?

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 08, 2019, 04:43:39 am
content: Something like a PCIe connector is cheap (mass produced) and designed to handle high frequencies. Or for fewer pairs, HDMI connectors, with the bonus that they can be used for HDMI if connected to compatible I/O pins.I specialize in energy efficient cryptocurrencies and I have some understanding of how those coins remain energy efficient. The most common schemes I have seen involve making the memory to processor ratio very high, using lots of sequential processes, and/or making use of the IP address to limit the number of parallel instances. All of those greatly limit the possible advantage of a GPU, FPGA, or ASIC over a CPU. (At one time, quite a few have asked why Swagbucks is ASIC resistant if it uses Scrypt, the answer is that it uses Scrypt with a very high "N factor" that requires too much RAM for Scrypt ASICs. The pools also limit the mining rate per IP.)

author: daqq
author_rank: Super Contributor
timestamp: October 08, 2019, 07:07:42 am
content: QuoteDunno. There are some "standards" that development board have, the Arduino style, a raspberry like layout, digilent pmod interface and an the FMC connector (though this would be very very difficult to solder post production). I don't think you have to adhere to any standard, but if you want inspiration, you can look at those.Or maybe a board edge type connector that the user can plug into a PCIE counter connector, or solder onto the pads as they wish?

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 08, 2019, 11:21:26 pm
content: I would forget about pin headers directly on the board for high speed I/O since they aren't too good for high frequency, even though it's often possible to get away with it. (Obviously, adapters from pin headers to whatever high speed connector should be available.) Specialized high frequency connectors tend to be expensive, hence the suggestion to use mass market high frequency connectors like PCIe and HDMI.

author: agilmine
author_rank: Newbie
timestamp: November 01, 2019, 05:13:16 am
content: Hi Guys thanks all for the good commentswe are happy to announce that our campaign is alive now! we decided to push out a developer version , which is essentially the crypto mining /basic version + about 100 gpio and pcie. more IOs!please check out the campaign page for more info. and if you are interested sign up for project updates!https://www.crowdsupply.com/agilmine/ultraminer-fpga