Power on reset without a reset : ATF1504AS - Page 1
Forum section: electronics / general

author: NivagSwerdna
author_rank: Super Contributor
timestamp: May 06, 2023, 07:58:07 pm
content: I have a design which does NOT have a reset input (it's a reproduction of an obsolete custom chip), it really really does not have a reset.But... I need the device to have a well defined initial state after power-up...I'm using Verilog with Prochip Designer (although I'll be swapping to Quartus when my 30 day trial expires!)So for example... I have some JK and D flip flops and I need to deterministically set them so I get the correct behaviour from the very FIRST clock.Now... The ATF1504AS datasheet suggests...QuoteBut what does that actually mean? And how do I get at that behaviour?Thanks in advance

author: c64
author_rank: Frequent Contributor
timestamp: May 07, 2023, 12:53:37 am
content: Have you tried to initialize your registers in Verilog? Like reg x = 1;

author: NivagSwerdna
author_rank: Super Contributor
timestamp: May 08, 2023, 02:59:47 pm
content: I'm not sure that is going to work...Code:# Warning: : "e:/ATMEL_PLS_Tools/Prochip/MyDesigns/X/X.v", line 149: Ignoring Initial value for this signal/variable as initial value is not supported for the specified technology.

author: AK6DN
author_rank: Regular Contributor
timestamp: May 08, 2023, 04:57:07 pm
content: That construction (reg foo = 1;) does work in the Quartus 13.0sp1 tools for the Altera EPM7K series that I use it with.Altho physically the register can only be set to '0' at initialization, Quartus is smart enough to invert the sense of the register if you do that,and make all the appropriate downstream changes, inverting the polarity of the register use, as now L means logic '1' and H means logic '0'.When I substitute an equivalent Atmel part (ie, ATF1504AS for the EPM7064S) POF2JED of course it works as expected as by then it is just logic.One reason why I continue to use the Quartus 13.0sp1 tool for ATF15xx series parts development.

author: BrianHG
author_rank: Super Contributor
timestamp: May 08, 2023, 05:15:08 pm
content: Quartus default power-up of all registers to default '0' and it is guaranteed so long as you make sure that the compiler setting 'Power-up Don't Care' is set to "false' or 'Off'. The majority of the time even with the 'power up don't care', all regs will still be '0' unless there is a priority for any particular set of regs which is required to save space or increase fmax because you have reached the end of the fpga size and speed limits.The other way is to specify it in your verilog code, eg:reg [7:0] counter = 8'd0 ;or:initial begincounter = 8'd0;... // Specify all your other 'CLOCKED' reg power-up defaults inside here.endThis also helps with ModelSim simulations as you alleviate the red 'x' undefined waveforms.

author: BrianHG
author_rank: Super Contributor
timestamp: May 08, 2023, 10:23:21 pm
content: Quote from: NivagSwerdna on May 06, 2023, 07:58:07 pmOk, for FPGA, the loading of the bootprom guarantees the startup state of the registers.PLD devices may not be as sound.For tiny devices, I would usually guarantee a reset via global reset input pin. (Remember, you still need to HDL code this as well as assign the global attribute to the reset line to ensure the use of the macrocell's dedicated RST net/fuse.)For devices where I can sacrifice 2 registers, the minimum for an internal power-on reset signal, I would use this route. Though this solution requires that you are providing an external or internal clock.This solution means a 2 bit counter set to default at '0' and count until a limit of 3. The reset out from this logic is a NAND gate which means until the circuit reaches 3, you provide/assert your required internal global reset to prevent dirty random toggling of JK, T and unclocked SR flipflops.

author: AK6DN
author_rank: Regular Contributor
timestamp: May 09, 2023, 12:08:50 am
content: From the Intel/Altera MAX7000 data sheet v6.7 of 2005:"Upon power-up, each register in the device will be set to a low state."From the Microchip/Atmel ATF1502AS data sheet of 03/2014:"At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will depend on the polarity of its buffer."I have really never come across a device datasheet where the vendor states that the contents of registers will be random after power up.If you know of one I'd like to see it.

author: BrianHG
author_rank: Super Contributor
timestamp: May 09, 2023, 01:14:40 am
content: Quote from: AK6DN on May 09, 2023, 12:08:50 amI do not know about the data sheets, but, I have seen it on GAL22V10s with an SR latch and inverter oscillator.

author: AK6DN
author_rank: Regular Contributor
timestamp: May 09, 2023, 02:10:26 am
content: Quote from: BrianHG on May 09, 2023, 01:14:40 amGAL22V10 (or any PAL/GAL for that matter) does not have an intrinsic SR latch element; that is a construct built from logic by an end user.PAL/GALs had proper register elements on some devices that would reset correctly.What you are citing as an example is IMHO a flawed implementation by an end user, and not a feature (or lack thereof) of a device.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: May 10, 2023, 06:38:25 pm
content: I have re-jigged my design so that a low state in all registers would work. I had to invert the D-flop input and swap the output.Sadly, the fitter did not like my pin layout so I will have to re-spin my adapter board, from a different design, so it will be a while before I find out if it works.

author: BrianHG
author_rank: Super Contributor
timestamp: May 11, 2023, 03:12:47 am
content: Also remember in Quartus compiler options that there is an auto 'not-gate-push-back' feature which can potentially smartly undo your manual efforts.

author: AK6DN
author_rank: Regular Contributor
timestamp: May 11, 2023, 03:33:53 am
content: Quote from: BrianHG on May 11, 2023, 03:12:47 amTrue enough, but it cannot and does not change the logical function of the design.