QFN package question - Page 1
Forum section: electronics / general

author: Karamel
author_rank: Regular Contributor
timestamp: July 23, 2016, 06:27:32 am
content: Hi everyone,As you know, almost all QFN packages have a big pad at bottom side (you can see it at bellow) and I know this pad must be ground but I am wondering that, every qfn package has GND connection at this pin?For example, I am working on with making library for FT812 ftdi chip but I did not see any explanation about this pin from datasheet

author: Rerouter
author_rank: Super Contributor
timestamp: July 23, 2016, 06:44:28 am
content: generally that pad is not electrically connected, rather it is intended to connect to a plane or similar that will dissipate heat more efficiently from the die that is bonded to it, in some cases it can be tied to the substrate and need to be connected to ground, but i have only found this on high speed chips, e.g. an NXP rfid chip,

author: Karamel
author_rank: Regular Contributor
timestamp: July 23, 2016, 09:17:46 am
content: I had always seen this pad is connected to ground. I gave a picture which have found from internet and also there are so many picture which thermal was connected to ground.and the last thing, I had seen that on a mother board, thermal pin was connected to ground (I had tested it with multimeter)There is a little bir confusing informations, am I right?

author: mrpackethead
author_rank: Super Contributor
timestamp: July 23, 2016, 09:20:21 am
content: read the data sheet for the chip. Never assume it is the same as another chip.

author: Rerouter
author_rank: Super Contributor
timestamp: July 23, 2016, 09:59:48 am
content: with the thermal vias its all about getting heat away from the chip, the most direct route is the opposite side of the board, however there is a downside to this, in that mass production like paste stencils tend to have most of that solder flow down the holes meaning a poorer thermal interface from pad to board,To get around this, you can either tent your vias under a chip (something i greatly dislike doing), or you can design your paste stencil to place a lower density of paste where it doesnt directly overlap a via, meaning it melts between the board and chip first, and then some excess can spread out the the vias afterwards,And yes, like unused pins on chips, always read the datasheet on exactly how they want you to handle the pad,

author: Karamel
author_rank: Regular Contributor
timestamp: July 23, 2016, 11:08:07 am
content: Okay. Now, I found it in datasheet. Exactly, I am shocked how I couldn't see that...at page 12 and that is back of the page.http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT81x.pdfthanks for all informations

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 23, 2016, 03:43:33 pm
content: I've only ever seen very few where the pad isn't "NC or GND", or required GND.One was a gyroscope, which, I think has a pad still, but recommends not connecting it, and removing copper underneath, to prevent straining the device. That makes sense. An unusual exception, with a reasonable explanation.I suppose a few RF devices might be VCC instead of GND (but never NC?), but for the vast majority of conventional CMOS ICs, it should say GND.Even if it has no connection, the preference is to connect it. This follows from the idea of connecting everything. Leave no pin floating. No, it doesn't matter much if it's a little island of copper, orphaned from a polygon pour by traces cutting through it -- but removing it (if possible) reduces coupling between traces, or grounding it increases shielding. The most common and most visible cases, merely happen to be the least consequential cases, of a much larger, and much more important, general approach!Tim

author: exmadscientist
author_rank: Frequent Contributor
timestamp: July 25, 2016, 03:57:51 pm
content: That same general principle also applies when you've got negative voltages in a system. The pads on negative regulators typically connect to VDD (that negative voltage) rather than ground, but it's exactly the same principle at work: the substrate connects to the most negative voltage the chip will see.There are also quite a few newer power devices with funky packages where large pads are connected to voltages other than ground, though those aren't properly called "QFN" devices anymore as they're, well, funky packages. Often a pad will be connected to the SW node, which makes lots of engineering sense as it's a very important, high load connection.

author: D3f1ant
author_rank: Frequent Contributor
timestamp: July 28, 2016, 07:22:45 pm
content: In my opinion, its is a mistake to put tents over via holes under thermal pads. Think about how solder forms a heal adjacent to a pad. If you don't wick some solder down into via holes, you risking the component floating on a bed of solder and not form a bond with the pads on the sides where the pad to paste ratio is considerably less. Worst case solder could squish out and bridge to the side pins, it has nowhere else to go.Having the via filled with metal will give a much better thermal pathway than an air filled one.I've never seen a datasheet that suggests tenting thermal vias. Stick to the design recommended in the datasheet and your not likely to run into any performance issues.

author: free_electron
author_rank: Super Contributor
timestamp: July 28, 2016, 08:30:15 pm
content: That pad is not always GND !!! some top side LED drivers use the pad is power supply.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 29, 2016, 12:21:49 am
content: Quote from: D3f1ant on July 28, 2016, 07:22:45 pmVias of 12 mils i.d. and smaller, rarely fill with solder (lead-free). Surface tension fights capillary action, to some extent. In my mind, at least: the amount of force feels like it should about balance with the tension of the QFN periphery joints pulling together, so that indeed, if there is excess solder on the exposed pad, it has some place to go, and will be squeezed into the vias as needed. And, that the vias only fill as much as they need to (rather than wicking too much and starving the joint).On the other hand, larger vias (20 mils and up) are good for heatsinking power components like DPAKs, assuming you can spare the extra solder necessary to fill them (which might not be available for paste reflow, but is fine for hand or wave soldering). A solder-filled via has about 1/3 to 1/2 the thermal resistance of a hollow one (at 1/2 oz. plating), so it's a worthwhile gain!Tim