Netlist versus gerbers - any free tools? - Page 1
Forum section: electronics / general

author: deanclaxton
author_rank: Regular Contributor
timestamp: July 09, 2025, 01:20:19 am
content: Hi all,I use Altium Designer and had a major issue with a board that I recently had fabricated at JLC. Initially I thought it was a manufacturing fault - I had a net shorted internally to the ground planes (4 layer with outer layers for signal, inner layers both ground planes).Initially I used a current injection tool and thermal camera to work out where the short was, then drilled out the via and wired around it - I was able to save the board that way. Later, (unfortunately AFTER raising a complaint at JLC) I checked the gerbers and to my astonishment there was a missing antipad on the ground planes (see attached image). JLC had made the board correctly. Somehow Altium's Gerber X2 generation had messed up.Now I've never experienced this before and to be honest, whilst I normally open the gerbers in GerberLogix for a quick sanity check, I've never checked them to this level of detail before submitting them to the fab.It's got me a little paranoid though, and I'm wondering if there are any free tools out there that can take in the gerbers, generate a netlist, and then compare the generated netlist with another? I guess if I use Altium to export both the gerbers and the comparison netlist then I could still get into trouble.Maybe its a once off - I hope so!

author: thm_w
author_rank: Super Contributor
timestamp: July 09, 2025, 10:30:36 pm
content: So if you open up the properties of that via in Altium, is anything off?If you export the same file, untouched, with regular gerber or ODB++, not X2, is the problem still there?What version of Altium?

author: tooki
author_rank: Super Contributor
timestamp: July 09, 2025, 11:14:36 pm
content: Out of curiosity, did you use ground plane layers, or normal inner layers with ground pours?And did you check the PCB layout in Altium itself? That is, are you certain it’s a Gerber export error, and not one already present at the Altium PCB stage of the process? If it’s there already, does repouring all pours fix it?

author: deanclaxton
author_rank: Regular Contributor
timestamp: July 09, 2025, 11:21:10 pm
content: The stackup is planes for the inner layers (not signal with pours). It's very strange and I havent asked Altium about it, but perhaps I should!I spent a bit of time trying to work out what the heck was going on with my board, and then a bit more pinpointing the short. In retrospect I should have looked at the gerbers BEFORE breaking out the current injection/thermal camera tools but at that point I thought it was a manufacturing issue.I regenerated the gerbers and its fine so a bit of a once off. I'll continue to look for a semi-automated way to check this - once bitten twice shy and all that. I guess for now I'll just have to be more thorough on manual checks.

author: deanclaxton
author_rank: Regular Contributor
timestamp: July 10, 2025, 12:16:03 am
content: Quote from: thm_w on July 09, 2025, 10:30:36 pmAltium 25.6.2 - there are updates so I'll install them. I regenerated the files and its all good. Hopefuly this is the last I'll see of this issue. At least I was able to work around it.

author: tooki
author_rank: Super Contributor
timestamp: July 10, 2025, 08:42:50 pm
content: Quote from: deanclaxton on July 09, 2025, 11:21:10 pmIt would be very interesting a) to see the via properties for the affected vias and how they compare to unaffected ones, and b) if the problem goes away or changes if you change the plane layers to signal layers with pours.

author: langwadt
author_rank: Super Contributor
timestamp: July 10, 2025, 09:02:20 pm
content: Quote from: deanclaxton on July 10, 2025, 12:16:03 amunless it is done automatically, did you forget to repour before generating gerbers?

author: thm_w
author_rank: Super Contributor
timestamp: July 10, 2025, 09:32:44 pm
content: I thought negative planes do not require repours, isn't that the advantage of them? Good for complex designs if you don't have the cpu horsepower. I never use them, since they are so inflexible and confusing.The same thing that happened to another person:https://www.reddit.com/r/Altium/comments/18m8hyw/why_did_altium_ground_a_via_on_this_gerber_export/

author: langwadt
author_rank: Super Contributor
timestamp: July 10, 2025, 09:40:52 pm
content: Quote from: thm_w on July 10, 2025, 09:32:44 pmafaict the only reason for negative planes is that in the old day it was easier, instead of having to fill out the plane with tape just put a dot when there should be no connection

author: deanclaxton
author_rank: Regular Contributor
timestamp: July 10, 2025, 10:33:35 pm
content: Interesting - I might switch to signal layers with pours for inner layers from here on.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: July 11, 2025, 10:31:51 pm
content: Just wondering. If you do a full DRC check on the version you used to create the gerbers, does it pass, or does it show these errors?Concerning negative layers... the solder mask is usually a negative layer. It makes much more sense to cut out all the clearances around the pads, then to attempt to define an object that covers the whole area of the solder mask, without defining the pads and their clearance.Edit: Oops. "Solder Paste" -> "Solder Mask". Thanks to Tooki for noticing the typo.

author: tooki
author_rank: Super Contributor
timestamp: July 12, 2025, 09:23:20 am
content: Quote from: Doctorandus_P on July 11, 2025, 10:31:51 pmSolderpasteor soldermask?

author: deanclaxton
author_rank: Regular Contributor
timestamp: July 13, 2025, 11:15:54 am
content: Quote from: Doctorandus_P on July 11, 2025, 10:31:51 pmI always run a DRC before gerber generation and it passed at that point in time. I'd have to go back in the history now to get my files back to that point in time as I've regenerated gerbers after finding the issue, and the newly generated files were ok.

author: jmelson
author_rank: Super Contributor
timestamp: July 14, 2025, 03:52:57 pm
content: Many years ago I had a bad PCB where the Gerber file had one crazy pad that was drawn HUGE. The fabricator caught the issue visually. Later that computer was retired to my house, and I tried to install Linux on it. Linux immediately complained about Signal 11 errors. It turned out the cache memory was bad but it only caused an error ONCE under Windows. I then ran memtest86 and it generated MANY errors. You might try running memtest86 on that computer for a couple hours to see if there is a hardware issue.Jon

author: thm_w
author_rank: Super Contributor
timestamp: July 15, 2025, 09:35:18 pm
content: In the other thread:https://www.eevblog.com/forum/altium/internal-power-plane-connection-not-detected-by-drc-in-altium/There is a link to altium with the recommendation:QuoteSo fab might have a tool to do it.

author: IconicPCB
author_rank: Super Contributor
timestamp: July 22, 2025, 01:30:24 pm
content: From faded memory, Altium used to generate erronious gerbers especially when it came to octagonal pads.The problem was the pad would be exported in correct dimensions hoever the rotation of the pad was incorrectly exported so causing potential shorts.I have seen problems with some CAM software as well where it would interpret zero size drawn features as circles again creating shorts within gerber exports.