Clock domain crossing synchronization question - Page 1
Forum section: electronics / beginners

author: pmbrunelle
author_rank: Regular Contributor
timestamp: March 06, 2018, 10:49:29 pm
content: I found this explanatory picture on the Internet.It shows clock domain "a", domain "b", and a pair of synchronizer flip-flops in domain "b". The idea of all this is to avoid propagating metastability to downstream logic, so I read.What I want to know, is why are both flip-flops in domain "b" driven by the samebclk? This type of schematic seems to be standard practice.Normally, on the rising edge ofblck,adatwill be copied tobdat1.At the same time asbdat1changes state, the second synchronizing flip-flop readsbdat1.Wouldn't this cause a setup time violation for the second flip-flop? It seems to me that the second flip-flop should be driven by a phase-shifted version ofblckto prevent a setup time violation.Or, is the propagation delay of the first synchronizing flip-flop sufficiently long enough that thebdat1transition occursafterthe hold time requirement of the second flip-flop has expired?What brought me to question these things in the first place (brewing doomsday scenarios in my head) is that I am hooking up asynchronous things (such as a rotary shaft encoder) to the GPIO of a microcontroller. How are the GPIO ports of microcontrollers generally handled with respect to propagating metastability from the GPIO to the microcontroller's innards?

author: Wimberleytech
author_rank: Super Contributor
timestamp: March 06, 2018, 11:01:51 pm
content: These are D Flip flops, not D latches.Data is read in on clock LOW, and read out on clock HIGH.There is no timing issue.Does this diagram help?

author: langwadt
author_rank: Super Contributor
timestamp: March 06, 2018, 11:14:22 pm
content: FFs will usually be made to have zero or slightly negative hold time, that makes it easy to make synchronous logic because then you only have to make sure everything gets clocked at the same time and that logic between FFS are fast enough to satisfy setup time at any given clock frequency

author: thermistor-guy
author_rank: Frequent Contributor
timestamp: March 07, 2018, 12:41:01 am
content: Quote from: pmbrunelle on March 06, 2018, 10:49:29 pmTwo F-Fs in domain b greatly reduce the probability of a metastable output. Occasionally the first F-F in domain b will go metastable, but it will have one clock period to recover before the second F-F in domain b samples it. And most of the time, one clock period will be enough. Three F-Fs in domain b would greatly reduce the probability even more.I have seen an experiment in a telecom lab where ten F-Fs in series were needed to reduce the failure rate to an acceptable level.In theory, you can't eliminate metastability. What you can do is design your system so the probability is extremely low - e.g. once every few hundred years (1E10 sec). Two F-Fs in domain b are often enough. See for example:http://www.interfacebus.com/Design_MetaStable.html

author: ejeffrey
author_rank: Super Contributor
timestamp: March 07, 2018, 04:21:31 am
content: There is always(*) a setup-and-hold violation possibility at the actual clock domain crossing -- that is, between the first (clka) and second (clkb) flip-flop. Violating setup/hold means you may get metastability where the output can flop back and forth between 0 and 1 multiple times. That means, if there are multiple flip-flops consuming the output of the second flip-flop (bdat1), eacn one might latch a different value which can totally mess up your logic.By adding extra flip-flop stages after the crossing (i.e., the third flip-flop), you reduce the chance of meta-stability. The second flip flop is likely to pick one or the other value -- it doesn't matter which one -- there is always ambiguity over which cycle the data transition happens. But any further logic in clkB domain will see a consistent value. The next clock cycle, flip-flop 2 will latch a '1', and everyone will get the updated value.Technically, additional stages don't eliminate the possibility of metastability. It is always possible that flip-flop 2 happens to be producing vcc/2 at the moment ff-3 samples the input. Its actually theoretically impossible to eliminate metastability. But each stage flip-flop exponentially suppresses metastability. Modern flip-flops have very narrow windows of metastability and are designed to settle very quickly, so a 2-stage synchronizer like you have drawn is normally sufficient.

author: pmbrunelle
author_rank: Regular Contributor
timestamp: March 07, 2018, 02:01:25 pm
content: Quote from: Wimberleytech on March 06, 2018, 11:01:51 pmI guess I need to study this.My problem with digital electronics is that I am learning it from a top-down datasheet black-box perspective, without fully understanding the primitives.