Weird Input Cap Waveform of a Buck Converter - Page 1
Forum section: electronics / projects

author: SteveLTN
author_rank: Contributor
timestamp: September 07, 2024, 04:43:07 am
content: [ Specified attachment is not available ]Hi all!I'm designing a Buck converter using LM5116 controller. Everything else works fine, but I have some problem tweaking the input and output capacitors.I was planning to use MLCCs. But later I found that at my voltage (36V in, 12V out) normal MLCCs' capacitance degrades too much. So I switched to solid electrolytic caps. But across my input caps, I see such weird waveforms which I do not really understand.In both oscilloscope screenshots, channel 1 (yellow) is SW node, and the channel 2 (pink) is the input voltage (AC coupled).The first image is when I use MLCCs. The waveform looks like expected, but unfortunately the capacitance became too small. So I wanted to use a larger Electrolytic cap. But I see the second image's waveform which I don't understand.I googled around but can't find exact keywords to describe my issue. Could you give me some hints? Thanks in advance!

author: PCB.Wiz
author_rank: Super Contributor
timestamp: September 07, 2024, 05:39:39 am
content: There is only one image ?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 07, 2024, 06:21:28 am
content: (It's two pictures, they're just crammed together.)The short pulses look like you're missing slope compensation, or component values are odd.The ripple seems to suggest high ESR, odd layout, not using a mix (you can mix and match, and should, actually).First call as always: schematic and layout.Tim

author: SteveLTN
author_rank: Contributor
timestamp: September 07, 2024, 05:21:29 pm
content: Thanks Tim! I will double check the slope compensation cap values.Here are the schematic and layout.I played around with input/ouput capacitors a bit. The layout shows the use of many 47uF MLCCs, but I actually soldered some polymer electrolytic caps (and kept some small MLCCs) on the pads for the second waveform.It's a 4-layer board. The 2nd and 3rd layers are both AGND. I put a via near any signal traces who needs to to the bottom side.One thing I'm not sure of is "connect all lower power signals to DIRECTLY to the AGND" in the datasheet. I assume using a solid ground plane does that?The PGND and AGND are connected together using a 0-ohm resistor. I used two networks to ensure the ground pour doesn't accidentally join PGND and AGND.

author: SteveLTN
author_rank: Contributor
timestamp: September 07, 2024, 05:42:23 pm
content: I did calculate the Cramp using the equation provided in the datasheet:Cramp = (gm * L) / (A * Rs) = (5u * 47u)/(10 * 3m) ~= 7.8nFAs I played around with the inductor value, I also made sure to change the value of this capacitor accordingly.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 07, 2024, 07:26:27 pm
content: Layout is compromised. Splitting grounds is almost invariably a bad idea; separation of ground loops is the superior method.Note that the typical application (https://www.ti.com/lit/ds/symlink/lm5116.pdfpage 21) schematically indicates all local small-signal connections (enable, sense, timing, etc.) signals return to local AGND, and the power section returns to PGND, *including EP*. Keep the local AGND small, and pour under it and stitch with vias. A wide join at the EP (and under) is good.Schematic does not match layout. At a glance, there are more output caps on layout, and an LMV358 thing, not shown. I guess that connects to FB but FB shows no other connections. Most of the layout grounds seem to be together but the schematic shows only two circle-grounds, one to Rsense of all things, which is...terrifying? Cramp (but it's not Cramp, I don't know what that is, but the nearest component would be C18) is apparently shorted out.Read up on topics: use of ground planes; stitching vias; switching current loop; stray inductance; etc.The physical design may or may not be salvageable but there are too many variances above to address it.Tim

author: SteveLTN
author_rank: Contributor
timestamp: September 07, 2024, 07:48:53 pm
content: Thanks again for the reply.I initially designed the board as a MCU-controlled variable power supply. But due to various issue, I decided to start with a fixed output power supply. Therefore a the LMV358 part (which is an RC filter followed by a voltage follower) on the PCB wasn't used at all. During some trial & error I modified the schematic (preparing for next layout) and forgot to state that part clearly.Thanks for pointing out the grouding issue. Somehow I was too focused on WEBench's output and overlook the connection of EP in the typical design. I did not really understand the wording in the Layout Guidelines section either.Attached was the exact schematic I used to layout the PCB. But many things were hacked on the PCB so I wouldn't say it reflects what I'm trying to test either. (I played around with inductor/capacitors etc, shorted CT node to GND to make it a fixed output supply)Just to double check: For a 4 layer board, should I keep local AGND on top layer, via stitch it to both of my inner PGND planes?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 07, 2024, 08:00:18 pm
content: Quote from: SteveLTN on September 07, 2024, 07:48:53 pmAgain, separation of current loops is better than splitting planes. But if you must, AGND can be filled under the relevant components and connections, and joined on vias under EP.Tim

author: SteveLTN
author_rank: Contributor
timestamp: September 08, 2024, 05:07:39 am
content: I think I got it after reading up on "separating current paths" and the LM5116 official evaluation board. Will make a new attempt. Thanks!

author: SteveLTN
author_rank: Contributor
timestamp: September 10, 2024, 01:52:25 pm
content: After doing a few things, it looks much better now:(1) use (a few) large MLCCs in place of the Poly caps.(2) Adjust the Cramp to a smaller value (although I calculated 7.7nF, I found 1nF works the best), it became stable. The sub-harmonic oscillation is gone.I'll make a new PCB anyway. Need to read up quite a bit more.

author: SteveLTN
author_rank: Contributor
timestamp: September 10, 2024, 03:55:16 pm
content: Looking at the LM5116 Evaluation board:What are the vias marked in red for? Are they only for heat dissipation?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 10, 2024, 07:59:17 pm
content: Yes, that's a four layer stack for heat spreading. It's actually worse than the alternative, particularly in that they excluded ground plane in the area.They even put a split between P2/P4, guaranteeing some ground loop (CM) emissions. Gotta love it??Preferred is solid GND pours on Mid1/2 and thermal pours top/bottom, with stitching vias placed near the heat sources (i.e. low-side drain, inductor pad), spaced such that GND still pours inbetween them. Particularly with fabs having thin outer dielectric (say under 10 mils), thermal conductivity thru-plane into the ground plane is pretty good (i.e., despite the poor thru-plane conductivity of fiberglass generally) and the planes greatly improve dissipation of the board overall.By putting thermal pour across four layers, they also nearly completely broke the loop around that node. Just one thin track on a mid layer wrapping around it, otherwise it would be a notch completely through the plane. As-is, E and H field around the pad will be pretty substantial, and I would want nearby boards at least a few inches away, let's say; more if they're sensitive/quiet.Tim

author: temperance
author_rank: Super Contributor
timestamp: September 10, 2024, 10:53:40 pm
content: QuoteUnless the PCB is made with >100 µm CU they only waste drills at the PCB manufacturing plant. The horizontal plane thermal impedance for a 35 or 70 µm PCB is too high for those vias to do anything useful.Edit: they must read their app notes:https://www.ti.com/lit/an/snva419c/snva419c.pdf?ts=1726009225855&ref_url=https%253A%252F%252Fwww.google.com%252FQuoteOn both sides that is. I have no idea about the split below the inductor. It seems they also added extra planes under the inductor because they needed more stray capacitance.What is going on with the bottom FET GND connection in the TI board?

author: SteveLTN
author_rank: Contributor
timestamp: September 11, 2024, 03:00:59 am
content: Actually according to their user's guide (page 7), the split between P2/P4 is on all 4 layers.https://www.ti.com/lit/ug/snva285a/snva285a.pdf?ts=1725936645707I guess it "forces" the current flow around the capacitors instead of directly goes between P2/P4 terminals?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 11, 2024, 04:11:00 am
content: Quote from: temperance on September 10, 2024, 10:53:40 pmWell, not none. But less. Or, depends if the extra thickness is due to plating (rare) or base foil (common).Or, if the outer prepreg is very thin, as many proto services use today.Quote...Less capacitance? They're the same net, four planes stacked up, capacitance only around the edges.Bottom FET has a pour back to the sense resistor. What's wrong with it?Quote from: SteveLTN on September 11, 2024, 03:00:59 amI think the intent was to make the nearby block of GND vias a star point of sorts, which is fine for referencing things at the base of the buck converter, right, but... then you've got different voltages going off away from it, as there's input ripple going up P1 and down P2, output ripple and switching noise (via L1 core loss + stray capacitance) going down P3 and up P4. And the far side of the board has the common mode related to its local (AGND) connection plus whatever drop arises between the "star point" and the controller; the half-bridge's current loop most importantly.So, the board radiates (no, not much, it's not huge or anything), the two (or more) cables radiate, the control test points radiate (if you plug anything onto them)...Tim

author: SteveLTN
author_rank: Contributor
timestamp: September 11, 2024, 04:29:40 am
content: QuoteOh, I see. Thanks!Following your suggestion, I drew up another PCB. Would you care to have a look?I used a 2-layer board this time, as this is just for evaluation (will be integrated into a larger board later).Used an adjustable resistor to simply my testing across different output voltage.I'm not sure what caps to use. So I left slots for both MLCCs and polymer caps. I ordered some Samsung 100V 100uF 1210 X7R MLCCs to test out. Better to leave plenty of slots for now.Bottom is a solid plane.AGND is now a small copper area that is stitched to the bottom GND plane.No split between input GND and output GND.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 11, 2024, 10:09:45 am
content: Hm, schematic should probably show input going to PGND as well.I would move a few things:- Pour SW on top only, increase area to compensate, pour GND underneath to minimize stray inductance.- CS can come out along the polygon edges I guess? Should probably turn it around though and get the controller closer, and to the gates. Can play around with orientation, maybe controller would be better towards the top right? But, stretch goals, it's probably fine as shown, this would be more about getting minimal layout area.- More vias to GND at the CS resistor. No need for multiple rows of vias, they do the most along the periphery of pours.- Move VIN trace to controller left, away from switching loop. Big peak currents and fields underneath the transistors, avoid that area, pour GND underneath.Tim

author: temperance
author_rank: Super Contributor
timestamp: September 11, 2024, 11:07:48 am
content: QuoteLateral thermal resistance:θ = L / K x AL= assume the VIA’s are placed about 5 mm away from the heat sourceK= for CU 400 W(m x K)A= assume the plane width is 30 mm x 35 µm CUθ = 119 kWOr 60 kW for 70 µm CU.Edit: one via is around 140...160 KW. Bonding two copper planes together with 25 VIAs won't do much to conduct heat to the bottom.QuoteThe switching side and the non switching side planes are extended under the inductor adding maybe 2 pF stray capacitance in parallel with the inductor. The inductor itself has around 10 pF stray capacitance.Quote

author: SteveLTN
author_rank: Contributor
timestamp: September 11, 2024, 02:23:19 pm
content: Done all that. Sending to the fab now. Many thanks for the help! I surely learn a lot!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 11, 2024, 09:19:45 pm
content: Quote from: temperance on September 11, 2024, 11:07:48 amNot sure what you're saying here. x is a variable? only K is in the denominator? (Order of operations, or use parenthesis to be unambiguous.) But what is k? Where did so many kilowatts come from? Or are you missing slashes and capitalization?We also have MathJax here, if you would like a prettier printing.$$ \theta = \frac{L}{K A} $$Not sure what a PC hardware company has to do with it -- do you mean vias? It's an improper noun, from Latin, no acronym, no capitalization.(I try not to be pedantic, but with so many variances here, I'd basically have to rewrite your whole point to understand it clearly and respond to, but then I'm not sure I'm even responding to what you intended. You were making a point here, but it's your duty to communicate that point clearly; sorry.)QuoteThose are pretty generous figures; but I don't see a part number anywhere in this thread. Did you PM Steve asking about what part it is--? Or characterize one yourself?I've seen various reasoning for avoiding pours under an inductor, but none of them are anywhere near as general as they're always presented.The only general truth is: it depends on type, and product requirements.I don't have any issueper sewith pouring under any generic inductor. A specific type, whose internal construction is known (may have to purchase and inspect; datasheets never describe this, and sometimes product photos aren't specific enough -- or even correct), may have little or no impact from pouring beneath (well shielded, ground pin available perhaps), or have reduced Q due to induction heating the foil.Most types of this rating, the coil axis is either perpendicular to the board, and a ferrite "spool" core is used (minor fringing at the board surface, some impact -- but little), or powder composite pressed around the coil (more or less self-shielded, though not as well as if a ferrite plate were underneath the part: the lower mu means more leakage out of the package -- in any case, small impact); or the coil axis is parallel (aligned, crossed, or at angle to the pad-to-pad axis), and the core is elevated above the board so has little to no effect (e.g. coil-mounted (round or flat wound) gapped PQ ferrite inductors). There are also horizontal PQs where the flat wire bends down to the surface for SMT mounting, and the core is an effective shield (negligible interaction results).Capacitance doesn't mean much in any case, as the winding to core capacitance already dominates, and while it would be best to ground the core (diverting some capacitive current to local GND, away from the output), that's rarely available, and a few pF (if it's even that) makes little difference: you aren't going to affect an order-of-magnitude improvement over the terminal-to-terminal responseAlso worth noting that most inductors don't have a simple capacitive response, but a dip, antiresonance, at some frequency above (parallel resonant) SRF, and then perhaps R, C or further complex behavior beyond there. It might act to couple harmonics into the output, but over just a modest range, not the whole cutoff asymptote (as a simple R- or C-dominant model suggests). Granted, the distinction isn't big, the same solution applies -- make a small-value LC at the output to kill upper harmonics as needed.Tim

author: temperance
author_rank: Super Contributor
timestamp: September 11, 2024, 11:19:36 pm
content: QuoteA correction to my sloppy writing:$$ \theta = \frac{L}{K A} $$But forgot to add the parenthesis in my original post.L= Length in meterK: thermal conductivity of CU, 400 W/m KA: surface area in m²If you place a heat source onto a plane, the lateral thermal resistance is 119 k/W for a plane with a length of 5 mm about 20 mm wide with a thickness of 35 µm.Placing vias to connect a top and bottom plane to create larger heats sink requires the vias to be placed as close as possible to the heat source and for a reasonably low thermal resistance you will need a lot of vias because one via has a thermal resistance between 140...160 K/W.QuoteGoing from this:https://www.we-online.com/en/components/products/WE-HCF#/articles/WE-HCF-2818I calculated C stray for two of those to be around 10 pF.QuoteFor me the idea is to maximize the impedance between the switching node and the "outside world" for harmonics from the switching node and switching node ringing in the 50...250 MHz range by reducing stray capacitance as much as possible. A complete plane underneath the inductor on an other layer is fine.The same applies to CM chokes. A CM choke with an impedance of 10 K at 100 MHz with 2 pF stray capacitance between the input and output places an impedance of 4 K into parallel with the CM choke at 100 MHz.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 12, 2024, 02:28:59 am
content: Quote from: temperance on September 11, 2024, 11:19:36 pmK/W*?That's way too high; that's like from the tiny chip inside a SOT-23, or TO-92, to ambient. Surely a wide (if thin) piece of copper does better?I get (0.005) / (400) / (0.02) / (0.000035) = 17.85.. K/W.QuoteOf course, for like 25 or whatever they have together there, that comes down to a quite modest 6 K/W. And less to inner layers: using the same calculation, say 1.6mm board thickness, 0.5mm diameter (1.57mm circumference), 35um thickness, comes to 73 K/W, and proportionally less for thinner dielectrics. Of course plating might be thinner in the barrel than on the surface; or it might be more (than 35um), depending as I said before. But resistance to an inner plane say 0.2mm away can be quite low.Whereas resistance thru-plane can be quite poor indeed, ballpark 0.2 W/(mK) or for a 10x10 mm D2PAK pad say, 80 C/W at 1.6mm, 10 C/W at 0.2mm. Vias make a huge difference in 2-layer board, and still help out in multilayer.A bit better in-plane, more like 1 W/(mK), but even the 8% fraction of copper to FR-4 in a typical 4-layer stackup is a significant improvement in spreading.Switching loop takes priority here, I'm not making that thing without solid copper underneath it. Thermal does whatever it can after that. If it needs thermal pads on top or heatsinks or whatever, consider dividing the thing into separate channels (with phase interleave as an option) so there's more smaller heat sources, or building on multilayer (including just a small module and building the rest of the circuit as whatever).QuoteCalculated--?*Shrug*, I see a ~5pF figure in the SPICE models, but they're not representative up there, just basic RLCR models. Calculating through ferrite is nontrivial: the material is at least moderately conductive at most frequencies. I don't see where they've documented construction details to make such a calculation from...QuoteYes, but at some point you can't increase series impedance. Don't think you can have more than a... kohm or two at 100MHz, maybe if it's a really small part, or narrow frequency of course. You have to sink the excess current and reduce transfer impedance instead.Hence more LC stages, grounding the core, shortening the wire length to raise series resonant frequency, etc.And what's different about copper on top, versus under 0.2mm of FR4? 0.8mm? 1.6mm? ...0.05mm? What about soldermask, or silkscreen, is that thick enough? At what point does it go from acceptable to not? It sounds very arbitrary to me.Tim

author: temperance
author_rank: Super Contributor
timestamp: September 12, 2024, 03:28:13 pm
content: I think we are talking about two different things when it comes to adding stray capacitance around the inductor.-Stray capacitance between the switching node and the GND plane: C1-Stray capacitance between the switching node and the output: C3The idea is to minimize C3 as much as possible in order to avoid coupling switching noise to the output by maximizing the clearance between the switching node and the output.Thermal resistance:Me bad, didn't calculate the thermal resistance correctly. What I wanted to point out is the rather high lateral thermal resistance and the spacing between the heat source and the vias must be kept to a minimum.