Output filtering in a DCM boost power supply - Page 1
Forum section: electronics / projects

author: jmw
author_rank: Frequent Contributor
timestamp: August 20, 2019, 02:32:17 am
content: I've been doing some more work on a power converter to drive Nixie tubes from USB level voltage power supplies (5 VDC to 150 VDC). My previous question was about input filtering, and after prototyping the board, I have another problem: the ESL on my output capacitor is killing me with spikes on the output from the switching dI/dt. I have a single 330 nF PP film capacitor for the ripple requirement I want, but it seems like I need a bigger network to keep the impedance down at high frequencies to suppress the spikes for EMC and general good design reasons.As a study, I put a somewhat arbitrary goal of trying to keep the impedance of the output capacitor network under 1 ohm from 1 MHz to 1 GHz and came up with a design that needs 9 capacitors with damping resistors, which ... just seems like a lot. Even though I'm just prototyping for a personal project, I want to be practical about BOM and cost. How is the output waveform quality goal set in commercial designs? Given the general design and requirements of the power supply (i.e. high conversion ratio DCM boost), is using 9 capacitors excessive?Btw, here is the capacitor network and impedance graph. ESR and ESL are derived from the looking at the resonant frequency in the manufacturer impedance chart. The 100 nF parts are PP film caps, the rest are 250 V C0G/NP0 ceramics.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 20, 2019, 03:12:06 am
content: You omitted stray inductance on the signal and ground lines between parts. In essence you've made a stack where nine capacitors are phased inside of each other somehow.Figure ballpark 1nH/mm equivalent for trace length. If you model the ground network as well, you can predict common mode noise to some extent.Paralleling different values is a commonly repeated trick but it's almost never productive (as you can see from the ~0.7 ohm mid range peak here).Much easier design -- put one relatively beefy ceramic as close to the rectifier and switch as possible, put the film in parallel with it for bulk, and add a series inductor to another ceramic capacitor. Finally, bring around the power input pin (assuming this is a non-isolated supply) and LC filter it to the same common ground point. These three connections, isolated from switching noise with inductors and coupled together with capacitors, approximate a point. A point, having zero dimension, also has zero voltage drop across it, so in this way you eliminate common and differential mode noises (to within whatever attenuation curve your filters exhibit).Tim

author: jmw
author_rank: Frequent Contributor
timestamp: August 20, 2019, 05:06:24 am
content: Thanks. Ok, just to be clear, you're suggesting a circuit like this?Vin is the input supply, L1 is the main boost inductor, C1 is a ceramic close to the switch node and rectifier, and C2 is the main output cap chosen for ripple requirements. If this is what you had in mind, what guidelines do you have with picking values for the other reactive components in relation to each other?edit: Also, should C3 be in series with some damping resistance (for the loop, Q = 1/R * sqrt(L2/((C1 + C2) || C3)))? With this filter in place, should the controller feedback tap before or after L2?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 20, 2019, 11:55:13 pm
content: Yes; I suppose I should note the FET, and its source shunt resistor if applicable, should also be "ACAP".C1 will probably be limited by available selection (ceramic caps that actually have any capacitance left at 200V are small or expensive), and will resonate with C2's ESL so it may be desirable to dampen the pair. (C1+C2) || C3 will resonate with L2 so you may employ damping to deal with that. Ditto C4 and the input filter capacitor (not shown?).(Mind, I use "parallel" ("||") to mean to use the parallel-impedance formula, as applies to capacitors in series; and addition to mean capacitors adding in parallel...)Tim

author: David Hess
author_rank: Super Contributor
timestamp: August 21, 2019, 02:03:05 pm
content: There are special low ESL capacitors which use wider terminals. Often multiple smaller capacitors are used in parallel just to lower the ESL. Using multiple LCR sections helps a lot.I remember one company which used carefully selected values for output capacitors along with deliberate lead and trace inductance to create notch filters at the harmonics of the fixed frequency switching regulator's output.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 21, 2019, 06:42:32 pm
content: Incidentally, when you connect capacitors in parallel (and there's negligible trace inductance connecting between them), their series equivalents all land in the same place (Fo, Zo). So you only need to represent such a blob as a single series network, with capacitance C * N, inductance ESL /N and resistance ESR / N. This gives same Fo and Zo' = Zo / N.This works when the trace inductances are small compared to ESL. Which can be reasonable for a small stack of film caps on a parallel plate bus. It may not be reasonable for a chain of ceramic caps wired by two linear traces.Tim

author: jmw
author_rank: Frequent Contributor
timestamp: August 21, 2019, 07:08:04 pm
content: I did some tuning on the gate resistor (left space for an 0603 but started off with just a jumper) - turns out cleaning up the gate waveform also suppressed a bit of the spiking in the output ripple. I don't think I bodge extra ceramics and a series inductor to complete the above circuit, so it will take a board rev, but excited to see I'm getting closer to a well-tamed DCM converter.