PCB Trace Thickening material - Page 1
Forum section: electronics / general

author: TSOL
author_rank: Contributor
timestamp: April 15, 2025, 02:28:52 pm
content: Hello! I have recently ordered some PCBs for making a high current motor driver. They should be adequately suited for my application as I have removed soldermask to tin the traces after I receive the boards.Given the massive expense of going with thick PCB traces ($400+ for 6oz/sqft and greater) This got me thinking about future projects, is there a better way of reducing trace resistance than just tinning the trace with solder? I had an idea about getting some 10mil thick copper foil (equivalent of 30oz/sqft iirc) and cutting it to shape, adding a thin layer of solder paste to the PCB and flattening the copper foil on top of that, then throwing it in an oven or hitting it with a hot air gun. I kinda feel that if it isn't done perfectly, there may be air gaps between the copper foil and PCB trace, but it may be worth it for the overall increase in current capacity I'd think, right? People already solder busbars and the like to their PCBs, and this would allow the material to conform to the trace.Or am I overthinking and should just get some bare copper stranded wire to solder to the trace instead? Thanks!

author: ajb
author_rank: Super Contributor
timestamp: April 15, 2025, 02:57:04 pm
content: This idea has been discussed here before. One challenge is distortion due to CTE mismatch between the copper foil and the board. How much of an issue this is depends on the geometry involved, and there are some strategies for mitigating the problem.In some cases, it may be more economical to go to a higher layer count and duplicate the high current tracks on inner layers. It's hard to get to the equivalent of 6oz that way, but will be much less expensive, and you can still do fine-pitch features on the outer layers that you wouldn't be able to do on a heavy copper board.Just adding some wire is certainly an option that shouldn't be too easily dismissed -- solid wire may be easier to deal with, since it can be bent to the exact shape you need.

author: TSOL
author_rank: Contributor
timestamp: April 15, 2025, 03:17:45 pm
content: I was certain it had been discussed before but I couldn't find a post pertaining to it so I made a new one.It is not a method I have dismissed, in fact it is my plan with my current boards if tinning the traces doesn't resolve heating issues. I shouldn't have to worry but I'm new to PCB manufacturing so it's my backup plan.I'd only have a planned rise of about 30c so it shouldn't expand too much thermally, but it may expand a little. I'm not opposed to copper wire but copper film seemed to rectify the problem a little cleaner. Just trying to find cost effective options.Soldering is nice but it's so much higher resistance that you need to use a lot to get a noticeably better ampacity. 10mil copper film is 30oz/sqft which is massive overkill for all but the most demanding pcbs and its relatively cheap.

author: b177
author_rank: Contributor
timestamp: April 15, 2025, 06:28:18 pm
content: I have a device on my desk here that I did a partial teardown. The device is for switching up to 40A current @ 12V, so the traces must support at least that much. It has a 0.09" diameter solid wire soldered on the top side of the PCB. ~10 AWG. Also improves heat dissipation due to increased surface area.1oz copper is 0.5 mR/sqand if did the math correctly, 10AWG wire is 0.0075 mR/sq, but the "squares" are always 0.09" wideor equiv to ~66 oz copperOn this device, the wire is ~2" long. Is it possible to reflow this? or is it a second soldering operation?

author: b177
author_rank: Contributor
timestamp: April 15, 2025, 06:30:57 pm
content: Also, change the pcb layout / footprint so the fab removes the soldermask from the top of the trace

author: thm_w
author_rank: Super Contributor
timestamp: April 15, 2025, 08:54:43 pm
content: "Cost effective" solid core copper wire is going to be the cheapest. Would also allow easy bends if needed.Cleanest would probably be SMD bus bars.Foil seems like more work to cut up, but could make sense if you have wide areas you want to cover.https://www.eevblog.com/forum/manufacture/bolt-on-copper-on-standard-pcb/https://www.eevblog.com/forum/manufacture/high-current-pcb-options/https://www.eevblog.com/forum/manufacture/searching-for-high-current-smd-bus-bar-component/(you can see tesla uses a lot of SMD bus bars)

author: TSOL
author_rank: Contributor
timestamp: April 16, 2025, 04:45:23 pm
content: Quote from: thm_w on April 15, 2025, 08:54:43 pmThis is most likely my best option. I'm seeing if it's better to get bare copper wire to run along the traces or if stranded copper wire that has been stripped is more time effective. Bare wire is nice because it has enough mass to clamp it to the trace and solder it down without much solder getting in between the wire and the trace, keeping the path low resistance, while offering a good amount of surface area due to the circular shape of the wire.Quote from: thm_w on April 15, 2025, 08:54:43 pmThe thing about bus bars if I'm understanding you right, is that, while they are low resistance because they're designed to be PCB mount, they aren't continuous. Any break in continuity from one bus bar to the next means that the full current is experienced across the trace and not the busbar, and current density kills. I could guarantee foil is continuous by patching any breaks with more foil. I can't guarantee it gets properly clamped to the trace though, that's the tradeoff I guess.

author: ajb
author_rank: Super Contributor
timestamp: April 16, 2025, 07:42:36 pm
content: Quote from: TSOL on April 15, 2025, 03:17:45 pmIt's not just a matter of operating temp rise. If the added copper is locked into place when the solder solidifies at ~220C, then that is the temperature where CTE stress is zero. At 25C you'll have 195C worth of CTE stress, and at 55C operating you'll have 165C worth of stress. The maximum stress will occur at the minimum temperature your device experiences.Quote from: TSOL on April 16, 2025, 04:45:23 pmUsing many small bus bars like in the video linked in the third thm_w linked to (https://youtu.be/fUCgLCbX_18) helps reduce the CTE stress, since thermal expansion is a function of length, less length means less stress. Obviously it also reduces cost, since they can use a bunch of the same part rather than needing a custom part for each path they want to reinforce. It doesn't really matter if the added copper is firmly clamped to the trace: note that the added bus bars in that video are only soldered at the ends. You could get rid of the traces entirely as long as you have an adequate connection between each end of the bus bar/wire and whatever it needs to connect to. Using relatively thick material for the bars also increases the surface area, which improves heatsinking, which reduces the temp rise of the board. Remember that copper has a positive tempco of resistance, so reducing the temp rise also reduces I²R losses, which further reduces heating.

author: DerekG
author_rank: Frequent Contributor
timestamp: April 17, 2025, 12:20:31 am
content: Quote from: TSOL on April 15, 2025, 02:28:52 pmWe use 2oz copper boards which are a reasonable compromise cost wise. Add wide tracks to both outside layers (if possible) & open the bottom solder mask on the bottom current carrying tracks. As our boards are wave soldered, this automatically adds thickness to those bottom tracks.Depending on the length of your tracks, another option is to used tinned copper wires. In the past we have used the tinned wire on 3A through hole diodes. These are quite cheap. We simply discard the diode body after using the leads.

author: TSOL
author_rank: Contributor
timestamp: April 17, 2025, 04:38:23 pm
content: Quote from: DerekG on April 17, 2025, 12:20:31 amI haven't started wave soldering yet, I am currently hand reworking all my boards, because I only order 3-10 of them at a time.I have a few questions for how you'd go about that. My biggest concern for doubling the traces by using top and bottom layer is: How do you connect those two layers together? Some people are a fan of via stitching layers together like that, where you just place vias randomly throughout the trace to stitch them together. You could also place vias at the beginning and end of the trace to kind of emulate what was talked about above, where you only connect the beginning and end of a wire to the trace you're trying to thicken.My biggest concerns are twofold:I've heard vias aren't terribly low resistance (duh), so how do you prevent a low-resistance connection to another trace when using vias? Just use a ton of them? Would it also be a good idea to make the vias slightly larger than a known gauge of bare copper wire (say 22 gauge) and fill them in with copper wire by hand afterwards? I'm a bit apprehensive to using those tiny vias to carry potentially multiple tens of amps without frying. I think there might be an "Ampacity per via per size" chart somewhere, I'll have to find it.Since this is a switching converter and certain traces will be in the di/dt path (a lot of them will be), inductance is also a factor that needs to be considered. I've heard vias are pretty high inductance as well (idk how that makes sense cause inductance is supposed to involve a loop, but whatever). There may be a lot of induced ringing due to using vias, and is the solution again to just use a ton of them? I don't see anyone else doing this, but maybe my case is different.As an aside, I haven't done wave soldering because I am actually uncertain if JLC/PCBWay would take part numbers from Digikey or if they only use LCSC parts. I remember having issues in the past trying to use Digikey. If they can order from Digikey, I would imagine JLC would have to order the parts from the US, ship them to China, solder them on the board, and ship the boards to the USA. Not only would that be expensive (moreso than pick-and-place already is), it'd take months to get these boards (it takes 2-3 weeks to get my boards using PCBWay on both the cheap shipping option and UPS shipping, never used JLC). It already takes too long using vendors that aren't JLC in my opinion, so adding more wait time will make me get uninterested in the project before it arrives.

author: ajb
author_rank: Super Contributor
timestamp: April 17, 2025, 06:14:42 pm
content: Quote from: TSOL on April 17, 2025, 04:38:23 pmVias (or PTH component pads) are pretty much your only option. There's not likely to be much benefit to additional vias along the lengths of the tracks, since they don't really add to the amount of copper in the direction you care about, and in fact they may *reduce* the cross-sectional area. As long as the ends and any branch points are solidly connected, the two tracks will behave like parallel wires, more or less. All-over stitching is normally used to tie copper pours on separate layers together, especially where those layers also contain tracks. In that case, it helps the two incomplete pours behave much more like a single contiguous plane. The via placement should be strategic rather than random, although with large pours you can sometimes get away with just placing a grid of stitching vias, which some CAD tools can do automatically.QuoteVias are used for tens of amps all the time. There are calculators out there that will help you establish how many to use, but there isn't really a set current capacity per via. A better approach is to look at the resistance of the via(s) and then figure out how many you need to keep power loss (and therefore heating) to an acceptable level. It is possible to fill vias, you can estimate the effect that this will have on the electrical resistance and decide if it's worth the effort/expense vs just using more of them.Similarly for your inductance concerns, vias are used for high di/dt paths all the time. It's hard to see due to the low bitrate on that tesla teardown video, but there are absolutely tons of vias used to connect all of those S08 FETs, caps, etc to tracks/pours on other layers -- it's the only way you could possibly route a board like that. As you point out, inductance is really about loop area, so how you route the connections is much more important. Using vias to jump to another layer can produce an overall lower inductance path than sticking to a single layer and having to take a more circuitous path, especially if you don't have a solid plane underneath to handle the return currents. Speaking of solid planes, one thing to watch out for with via stitching is that you don't end up creating large slots or cutouts in your copper pours. It may be necessary to play with the spacing and placement of your via arrays to allow the plane to pour around them properly. Hopefully you do have a solid ground plane somewhere in your layer stack, that is generally the best way to ensure that your signal paths have minimal inductance.If you want more specific advice, you can always share your schematic and layout for review.

author: TSOL
author_rank: Contributor
timestamp: April 18, 2025, 03:53:03 pm
content: Alright I'll shoot my shot, let me know what you guys think!A disclaimer, this board was made with the assumption that stitching the ground plane is a good idea. I may have overdone it *a little* lol. There are also some traces routed on the back ground plane for the inputs to the gate drivers. I was torn when routing them as, on one hand, I wanted to have the IO for these pins on the same side of the board as the power is, but I kinda fumbled the routing on these traces. I routed them between power and GND, but I should have just routed them near GND so that the decoupling capacitors by the FETs have a short ground path. Live and learn, I suppose.If it is as you say, and using vias is acceptable (especially for a thing as high-frequency as gate driving), then I definitely would have put the gate drivers on the back for a practically nonexistent loop size for gate drive, and that would have been an astronomically better layout. There are so many weird rules in PCB design that even some of the big manufacturers in their whitepapers say. I have included a few excerpts from the Motor Driver PCB layout document I was referencing: (https://www.ti.com/lit/an/slva959b/slva959b.pdf)It is also worth mentioning that my VCC pour is de-masked and so is a sizeable chunk of the ground plane below. There are two ground planes, one on top layer and one on bottom. No part of the bottom layer is de-soldermasked, but the top one has a large unmasked area. The two points to connect the motor leads to are also unmasked obviously lol.

author: ajb
author_rank: Super Contributor
timestamp: April 21, 2025, 07:52:43 pm
content: Sorry, you're likely to get more traffic posting for a new thread for design review in the projects forum.What is your target current, voltage, and switching frequency for this?Where are your power in and motor out connection? Are they meant to be soldered directly to the planes? Soldering to that much copper will be challenging, especially the stitched ground plane.It's hard to say without knowing how much current you're actually trying to handle, but there's so little routing length for your high current paths and they're already so wide here that it's hard to imagine much benefit to laminating extra copper or soldering on wires. Here's a trick for analyzing resistance in a sheet material: if you divide the bulk resistivity of the material by the sheet thickness you get a value of Ohms per square, which is the resistance from one edge of a square of the material to the opposite edge, regardless of how big that square is. So for 1oz copper, 1.7E-8Ωm / 35μm = 486μΩ/sq. Now you can divide up any path into squares, and multiply the number of squares you need to traverse by that value to get the path resistance. So from your electrolytic caps, for example, you have about 3.5 squares to Q3/Q4, so that's 3.5*486μΩ/sq = 1.7μΩ, or about 4.3W of dissipation at 50A.A few other comments:There's no point in all the via stitching under the FETs if there's no copper on the other layer. You could add pours to the bottom side to get better heatsinking, but all of those vias are going to suck up a fair bit of solder and may not leave enough for the FET connection.You should have ground connections on the signal header, otherwise you're relying on a signal ground connection through the power supply wiring, which is liable to introduce noise into the PWM signals.Get the signal tracks on the bottom side away from the power routing area, if you move them to the top layer you can have a nearly continuous ground pour under the important parts and they won't be as in the way of the high current paths.You can absolutely use (physically) smaller gate/bootstrap resistors, which will make things a bit easier to route. I'd recommend starting with all of your parts spaced out a bit more, then start connecting things up with simple tracks (not too small, maybe 0.5mm or so to start with) to get a sense of how everything connects. Play with different arrangements and orientations of the parts to see what gets you the cleanest routing, prioritizing the loop areas on critical paths (in this case, between the gate driver and the gates/Vs nodes in particular). Once you have the topology figured out, you can start thickening up the traces that need it (or replace them with pours) and tightening up the part placement.

author: thm_w
author_rank: Super Contributor
timestamp: April 21, 2025, 09:26:52 pm
content: Quote from: TSOL on April 18, 2025, 03:53:03 pmSome of those rules are bullshit, right angle traces are fine (just will make you look more of an amateur), teardrops aren't needed in most cases.The other stuff is good, but unless you are pushing the limits of the PCB design, they may not matter for your design.

author: Accu-Sembly
author_rank: Contributor
timestamp: April 21, 2025, 10:06:34 pm
content: Quote from: b177 on April 15, 2025, 06:30:57 pmThis is the most common budget friendly version I see. During assembly, we cut up the stencil over the traces into segments and add solder paste during the screen printing process.

author: DerekG
author_rank: Frequent Contributor
timestamp: April 21, 2025, 11:52:11 pm
content: Quote from: TSOL on April 17, 2025, 04:38:23 pmBecause we have our boards wave soldered, we leave the vias exposed & make the hole size 0.8mm. When wave soldered, these holes fill with solder automatically. Don't make the holes too big, otherwise the solder will splash through the holes onto the top side of the board. And yes, if you are hand soldering, using thick component leads (or tinned copper) can manually end up with the same result. Remember, vias are only good if you need the current to move from one layer to another. They are not for moving it further along a track on the same layer. Never leave tracks with no soldermask unless you are going to cover them with solder. Otherwise they will (over time) oxidize & corrode, eventually failing.

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 22, 2025, 12:44:32 pm
content: Overall I agree with all of ajb's comments above. All the high current nets visible on this layout already have very low aspect ratio (i.e. they are short and fat), which means "reinforcing" them with additional conductors has dubious merit. And the paths by which these high currents enter and leave the circuit apparently aren't defined (that might be where trace resistance actually matters).In addition to ajb's other comments on component sizing/selection, I would suggest using a separate gate resistor for each MOSFET, rather than connecting the gates directly together. This helps balance switching losses between FETs. Also I have the gut feeling that you'll need a lot more bus capacitance than what is shown on the layout...

author: TSOL
author_rank: Contributor
timestamp: April 22, 2025, 01:03:37 pm
content: Quote from: ajb on April 21, 2025, 07:52:43 pmOops, its for switching at 20khz and yes, soldering directly to the copper. I've got a Metcal soldering iron and haven't had much an issue soldering to big piles of copper like these in the past. Haven't tried soldering a ground plane like this though. Current is somewhere between 30A and 50A as a worst case scenario. The motor being driven has a 120A stall current, but it pops like a balloon if actually driven at that. It is majorly undersized for 120A drive. Even 50A would likely fry it, I just wanted to oversize my driver. Motor is a Vex 775 Pro. Voltage is 12V.Quote from: ajb on April 21, 2025, 07:52:43 pmI'm assuming you meant 1.7 milliohms. According to quite a few online calculators, 4.3W is very much enough to cause significant heating in the trace. According to this trace ampacity calculator from Digikey: (https://www.digikey.com/en/resources/conversion-calculators/conversion-calculator-pcb-trace-width), a trace that is a little shy of half an inch wide, 1oz copper will cause a 4.3W loss at 1.7mOhms, causing a 170 deg C temperature increase over ambient. This PCB ampacity calculator from Advanced PCB corroborates this: (https://www.advancedpcb.com/en-us/tools/trace-width-calculator/). There are other factors too, the wider the trace, the more radiating surface area and the more efficient the cooling of said trace. However, for my example I think this is a useful point to make. Also, good thing my board is 2oz copper instead of 1oz...Quote from: ajb on April 21, 2025, 07:52:43 pm1) Yeah something seemed fishy when I was making that, because the vias don't actually connect to any copper on the other side. Its all ground plane. Speaking of ground plane, how are you supposed to have both a contiguous ground plane AND a significant amount of copper for those vias to attach to? Aren't those contradictory?2) Ah crap you're right. I forgot.3) I was thinking about this, believe me, I just had no idea where to route them. The right half-bridge driver needs to be routed on the ground plane because its completely boxed in, and I did that to have as short of a routing for the decoupling capacitor as possible. In theory I could have put it on the back and used vias, but again I was under the impression from the TI whitepapers I've read that vias add some significant enough inductance to be concerned.4) I suppose you're right, I must have done my math wrong. I was assuming I'd need the 1 Watt power dissipation because it needed an amp or two for gate drive current. I forgot that I designed the rise times to be 1/100th of the on-time, so I can divide the power dissipation by 100. Instead of 2W, I need 0.02 W. Live and learn I suppose.Quote from: mtwieg on April 22, 2025, 12:44:32 pmThe intention was to have very low "aspect ratio", so that is good. However, the current passed through the board (dozens of amps, as listed above) will certainly cause the base copper to heat far more than intended, if I was designing for a 30 deg C rise.As far as bus capacitance, this was the only one I wasn't really sure how to calculate. I figured I'd be well off if I just "put a ton of it" on there, so I did. It is worth mentioning that the schematic is actually incorrect here and the capacitance is NOT 470uF. That was my bad. I found a physically slightly larger capacitor on Digikey that will fit because of all the exposed copper and is 1000uF. So my total bus capacitance is 2mF, not 940uF.

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 22, 2025, 05:51:40 pm
content: Quote from: TSOL on April 22, 2025, 01:03:37 pmSo motor current is up to 50A, but supply current will depend on speed x torque.QuoteIf you're basing your expectation on IPC-2152 or IPC-2221 (which is what all the online trace current calculators are based on), then you might be surprised. Those standards are only really applicable to traces which are much longer than they are wide (like 100x). And even then they tend to be quite conservative.

author: TSOL
author_rank: Contributor
timestamp: April 22, 2025, 06:35:54 pm
content: Quote from: mtwieg on April 22, 2025, 05:51:40 pmYeah the supply current is discontinuous but I still wanted to design it to be able to handle 50A, as 50A continuous at 12V nominal will easily fry the motor with the amount of waste heat.This is the datasheet for the Vex 775 Pro. At 50 Amps sustained draw, that gives me a max torque of 0.25 NM pre-gearbox. It also drops the overall speed by 33%. I'd be outputting 325 Watts at that point, and at ~53% efficiency, 300 Watts of waste heat is easily enough to fry that motor lol. Not that you were disagreeing with me, though.Quote from: mtwieg on April 22, 2025, 05:51:40 pmThat's interesting to know. I am very aware that, when making standards like these, the estimates tend to lean rather conservative as they would like to provide results that are within spec for a variety of end users, but I suppose I will have to see how conservative they are. You wouldn't happen to know of any estimates that would be better suited for wider traces would you?Also curious if you know if the ratings for wire ampacity is conservative like this? Because the numbers I see don't make a whole lot of sense.Certainly 4/0 wire should be able to handle more than 230 Amps before reaching 75 deg C, right? Granted, this is at an ambient temp of 35 deg C () and is within conduit with other current carrying conductors... but still, 4/0 is some monster-grade cabling, and I see much smaller cables on Battery Pile testers and welders, and I haven't heard anything about those cables getting to 100 deg C or anything ridiculous like that. Even busbar ampacities seem a little strange... I can't be the only one thinking there has to be some level of discrepancy when this chart claims I need ~450 KCMil to carry 400 Amps at a 55 deg C temperature rise, meanwhile Tesla (and others) are happily carrying that same amount (AC, RMS) on their PCBs made of literal copper foil that I'd imagine is a millimeter thick or less, and (relatively) thin copper busbars. I get there is cooling in an inverter, but surely they aren't cooling the BUSBARS too?

author: thm_w
author_rank: Super Contributor
timestamp: April 22, 2025, 09:37:59 pm
content: Quote from: TSOL on April 22, 2025, 06:35:54 pmThose are power transmission current ratings, in an enclosed space. So long distances, worst case, with safety factors included.https://electronics.stackexchange.com/questions/292777/why-do-some-wire-gauge-ampacity-charts-state-vastly-different-current-ratingsYou can see 000 AWG in free air temperature rise here:https://www.is-rayfast.com/news/wire-cable/temperature-rise-by-current/https://www.remingtonindustries.com/content/Remington%20Copper%20and%20Magnet%20Wire%20Data%20Chart.pdfQuoteThe video linked was just the front controller unit, it dealing with: pumps, fans, etc. fairly low current stuff, in the 5-20A range.If you look at the actual drive unit PCB/inverter, there is liquid cooling on the bottom connected to the FETs, and very large thick copper busbars. Little if any current goes through the PCB itself.

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 23, 2025, 01:21:58 pm
content: Quote from: TSOL on April 22, 2025, 06:35:54 pmIf you want to understand these standards more, I'd recommend readingthis paperwhich gives an overview of what the standards are actually based on and how they should be used.QuoteNo, and I don't expect one to exist. Too many degrees of freedom.QuoteLikewise, these numbers are derived based on a narrow set of assumptions, which are given at the top of the table. If you look around, you will find wildly different numbers based on different assumptions. Again, lots of degrees of freedom to consider. It's up to you to decide if the assumptions match up with you application.