Edge-triggered "custom" logic - Page 1
Forum section: electronics / projects

author: rs20
author_rank: Super Contributor
timestamp: February 22, 2014, 11:18:36 pm
content: Greetings y'all,I'm trying to find parts to make a circuit that has two inputs (A, B), one output (Q), and no clock. The output Q should be modified by edges on A and state of B as follows:A rising: Q --> BA falling: Q --> 0B low: Q --> 0For context, it's part of a hand-spun flash capacitor charging circuit; Q goes via a driver to a FET gate, A is the PWM that is fed through to Q, except pulses are cut short (or prevented from ever going through) by B (active-low hold-it-right-there conditions like overcurrent or overvoltage). I'd appreciate any advice at all; but the specific conditions are 5V or 15V (either is fine), operation maybe up to 1MHz (so delays of at most 100ns is what I'd prefer), DIP packages preferable. I came close with the following:SN54HC74 (D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP)_________A ------| CLK || | ___ |AND--| CLR Q |---- Q| | |B ------| D |`---------'But a) it's pretty weird using A as a clock in this way; I have to also use A to clear the flip flop as well which b) doesn't work, because it violates the requirement that the rising edge of CLK must be 8ns after CLR going high.Any good references on how to go about designing arbitrary edge-triggered logic, or even a few example jellybean part numbers for parts I might find interesting would be greatly appreciated, as well as suggestions specific to my problem.

author: tautech
author_rank: Super Contributor
timestamp: February 22, 2014, 11:30:31 pm
content: Have a play at this site, I found a XNOR configuration that solved a problem I had.http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/chapter.html

author: Marco
author_rank: Super Contributor
timestamp: February 22, 2014, 11:43:57 pm
content: Why can't you just AND A and B and call it a day?

author: Phroon
author_rank: Contributor
timestamp: February 22, 2014, 11:50:30 pm
content: I may be missing something, but isn't this just an AND?Code:A | B || Q==========0 | 0 || 01 | 0 || 00 | 1 || 01 | 1 || 1

author: rs20
author_rank: Super Contributor
timestamp: February 23, 2014, 12:17:21 am
content: Thanks tau, looks like an interesting reference. Will look into in due course, sure to be interesting at the very least!Regarding the AND suggestions; not quite, I don't want a rising edge on B while A is still high to turn Q back on again. That's what AND would do, but not my given set of transitions. (And in practice, this means using AND would cause the overcurrent case to just drive the switch at 100MHz and destroy it through switching losses.)

author: tautech
author_rank: Super Contributor
timestamp: February 23, 2014, 12:31:10 am
content: Quote from: rs20 on February 23, 2014, 12:17:21 amYep its been great over the years, especially when your mind is cluttered and you "can't see the wood for the trees".The interactive and visual simulations it offers are great. Here is the root link:http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/index.html

author: Psi
author_rank: Super Contributor
timestamp: February 23, 2014, 12:51:56 am
content: Cheap 8pin MCU running at 10Mhz could do what you want. It would be simple and quick to make but im guessing you want to stick with discrete logic.

author: ajb
author_rank: Super Contributor
timestamp: February 23, 2014, 01:00:43 am
content: It sounds like what you want is an AND gate with a as one input and a buffer that latches to 0 when B goes low as the other input. The latching buffer is a simple non-inverting buffer with a high value resistor from output to input and a diode with anode at the buffer input and cathode connected to B. But you haven't defined a state or transition that would reset the latch state. As laid at you haven't provided a complete truth table so it's hard to discern what functionality you're going for.

author: Marco
author_rank: Super Contributor
timestamp: February 23, 2014, 01:38:30 am
content: Attach B directly to not-CLR and use AND to get A&Q for the output.You could just use plain AND and semi low pass B (use a diode to charge a capacitor with a parallel resistor to discharge it) to get similar functionality.

author: rs20
author_rank: Super Contributor
timestamp: February 23, 2014, 03:05:04 am
content: Quote from: Marco on February 23, 2014, 01:38:30 amA+ with distinction! The first idea has exactly the behaviour I was after, and the second is a very interesting option that I'll consider too. Thank you!