"Best" FPGA for CPU design - Page 1
Forum section: electronics / general

author: richardman
author_rank: Frequent Contributor
timestamp: October 06, 2015, 10:13:01 pm
content: All compiler people want to design their own CPU eventually. I have done a few instruction sets "prototype" (nee. daydreaming). Now is the time to put some into actions.So for a hobbyist CPU hack, what is the current best FPGA to play with? Low cost tools a must of course. Have they settled on whether it's Verilog or VHDL yet, or is there something newer and better?32-bits, with complexity of a Cortex-M0 or so.Thanks

author: langwadt
author_rank: Super Contributor
timestamp: October 06, 2015, 10:27:08 pm
content: Quote from: richardman on October 06, 2015, 10:13:01 pmThe big players Xilinx, Altera, etc. have free tools for FPGAs in sizes with a reasonable prize tagThe also have their own softcore processors so you can get cheap dev boards with the stuff needed for CPU development i.e. an FPGA, memory and a few interfaces

author: nctnico
author_rank: Super Contributor
timestamp: October 06, 2015, 10:32:51 pm
content: What I would like to have is a good 16 bit softcore with good GCC support. The MSP430 for example. However that CPU isn't that easy to implement in an FPGA though. Personally I don't care about execution cycle accuracy, mimicing all the peripherals, where the code starts. Just as long as the core is compatible with the MSP430 instruction set. A nice extra feature would be to allow the stack pointer to be initialised from one of the interrupt vectors just like the Cortex Mx CPU cores do. It saves a lot of hassle with startup code written in assembly.Oh, and please don't use Verilog. VHDL offers many ways to do things more clever and write less code (functions, arrays, enumerations).

author: legacy
author_rank: Super Contributor
timestamp: October 06, 2015, 11:07:29 pm
content: Quote from: nctnico on October 06, 2015, 10:32:51 pmwhy 16bit?what do you think about MIPS/16?they look like R2K, but their ISA has been compressed to 16bitdo you want 16bit because of thecode density?

author: langwadt
author_rank: Super Contributor
timestamp: October 06, 2015, 11:21:25 pm
content: Quote from: nctnico on October 06, 2015, 10:32:51 pmVHDL might be less code but it's so verbose that it'll take the same typingboth will get the job done

author: legacy
author_rank: Super Contributor
timestamp: October 06, 2015, 11:36:08 pm
content: Quote from: richardman on October 06, 2015, 10:13:01 pmI started something similar 1 year ago, but then I focused on thedebug processor, I have realized adebug protocoland I am studying its impact on thesoftcore, but I have also trying to complete the software side, interfacing gdb (GDB <---> SWI_DBG, bridge), and implementing theTAPefficiently in vhdl. I am also limited by the transport, which is uart driven overusb-bulk, I am using a FT2232 chip and the maximumbandwidthI am able to achieve is 1Mbit/sec ~100Kbyte/sec, while the debug protocol has an efficiency of 64K/(64K+8) ~99% when it has to download/upload things from/to the ram, while it's 4/(4+8) ~33% when it has to set/get a register of 32bit, but it supports hwbreak/watchpoints,code injection.Different motivations, one of them is that theTAPis extremely good to validate thesoftcore, because it helps a lotQuote from: richardman on October 06, 2015, 10:13:01 pmmy current best FPGA to play with isSpartan6, what do you think about thePapilo/Proboard ? (~100 euro, with SDRAM)Quote from: richardman on October 06, 2015, 10:13:01 pmit's a lot ofcomplexity, I would not suggest it to redesign your boundaries but …mysoftcoreis amashupbetweenR2Kand88K(eight eight key), withoutpipeline, withoutcache, and ignoring thecode density(which, I can assure, is a crap in myISA design).I do not have aC compiler, but I have already implemented a asm compiler, unfortunately it's not able to produce an object that can be linked byldofGNU/binutils, so my assembler uses a trick and includes all the sources in order to build up the final binary, assembling and linking them directly, in aone shot.

author: nctnico
author_rank: Super Contributor
timestamp: October 06, 2015, 11:39:45 pm
content: Quote from: legacy on October 06, 2015, 11:07:29 pmYes and less FPGA resources. I looked at several open cores projects but nothing there is really useful.

author: miguelvp
author_rank: Super Contributor
timestamp: October 06, 2015, 11:49:59 pm
content: ARM already has Cortex M1 soft core, maybe they have other softcores, I think they do favor Altera but not sure.Also I'm unsure about pricing, but it's not free.

author: 6thimage
author_rank: Regular Contributor
timestamp: October 07, 2015, 12:06:53 am
content: Quote from: richardman on October 06, 2015, 10:13:01 pmThat is a never ending question - both are equally good, but people who use them will tell you that their one is the best (I use verilog, so you can guess what I like!).Quote from: richardman on October 06, 2015, 10:13:01 pmJust because I have these numbers to hand - a Cortex M0 with the 32 cycle multiplier (smaller, but slower than the single cycle multiplier), with 1 KB of RAM (implemented as block RAM) and a simple AHB-lite GPIO peripheral (I think it had 32 IOs) takes around 984 registers and 3,519 LUTs on a spartan 6 (for the lx45 part this is around 1.8% and 12.9% of the total available, respectively).I am currently using a pipistrello board (frompipistrello.saanlima.com) and I think it is a fantastic board - but which board really depends on what you want to do and how you want to do it. The pipistrello isn't particularly great for user inputs (it only has one button), but has a micro SD card, which is pretty essential to my current project. A lot of the digilent board are great for human interactions, but can make it incredibly difficult to interface your own hardware with.

author: legacy
author_rank: Super Contributor
timestamp: October 07, 2015, 12:11:45 am
content: Quote from: nctnico on October 06, 2015, 11:39:45 pmI understand, and it's the reason why I switched to the Papilo/Pro board: I can't use the BRAM as ROM due to the bad code density I have in my ISA, so the DRAM can save methe best of the best is achieved by CISC, e.g. if you compare Z80 (which has a few registers) or HC11 (which is almost a stack machine with 1 accumulator), MIPS/16 seems to be good, but there is a problem with that: the copyright, I do not know if MIPS.INC ( I do not know how they are called now ) allows us to use it for free.umm, but I guess we'd better look forarm-thumb, they should be a good tradeoff, and fully supported by gcc. Not checked yet on opencores dot org

author: nctnico
author_rank: Super Contributor
timestamp: October 07, 2015, 12:26:11 am
content: ARM would need 32 bit registers. That means less speed and more flipflips. A 16 bit adder is easier to route and meet timing than a 32 bit adder. Add the complexity of a complete ALU to that and you'll see the difference between 16 and 32 bit is huge.

author: richardman
author_rank: Frequent Contributor
timestamp: October 07, 2015, 12:42:55 am
content: One notable point is that existing compiler support is not important, because... I write compilers :-)

author: nctnico
author_rank: Super Contributor
timestamp: October 07, 2015, 12:51:36 am
content: Perhaps but GCC support makes life a lot easier because of the eco system around it and could spark a softcore which is actually useful. At the moment the only freely useable softcore is the LM32 from Lattice.

author: ehughes
author_rank: Frequent Contributor
timestamp: October 07, 2015, 01:08:30 am
content: Arm gives a version of the M0 away (design start program). It is free. They even have example projects for the Digilent Basys 3 board.The whole soft CPU thing is dying. It is a waste of silicon. Accelerate your function with logic...The only softcore I like is the Picoblaze as it is a dirt simple design that is great for functions that don't need dedicated logic.

author: richardman
author_rank: Frequent Contributor
timestamp: October 07, 2015, 01:17:00 am
content: Quote from: nctnico on October 07, 2015, 12:51:36 amI have some weird ideas about CPU, doubt it would be generally useful, and I can hack my compiler a lot faster than I can hack GCC. In anycase, if it's actually interesting to someone else, certainly I will open source it etc. and people can go wild with GCC port...

author: legacy
author_rank: Super Contributor
timestamp: October 07, 2015, 01:38:18 am
content: Quote from: richardman on October 07, 2015, 01:17:00 ami'd like to see your C compiler, is there a repo ?can you tell a bit about your softcore's ISA ?

author: legacy
author_rank: Super Contributor
timestamp: October 07, 2015, 01:40:37 am
content: Quote from: nctnico on October 07, 2015, 12:51:36 amhave you forgotten NIOS/2 and ZPU?

author: richardman
author_rank: Frequent Contributor
timestamp: October 07, 2015, 02:14:26 am
content: Quote from: legacy on October 07, 2015, 01:38:18 amDear Legacy, compiler site ishttp://c4everyone.comRight now, the soft CPU is just a daydream, hence the initial question. Also there's the dangerous condition known as "copious free time". :-)re: HC11 CPUThat is so cool. Thanks for sharing. We were THE affordable HC11 compiler vendor. Even made it into a few text books.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 07, 2015, 06:30:44 am
content: If you are after tinkering with CPU design, then anyboard with the pperipherals you are interested in will be OK.Unless you will get a bundled license I world avoid Xilinx as you don't get a virtual logic analyser.A Terasic DE0 Nano might be a good fit, but IIRC you will need to make your own SDRAM controllet.If you want more memory than is on the FPGA chip.The Arty does look pretty good though, and it doescome with a node+device locked llicense for Vivado.....

author: tggzzz
author_rank: Super Contributor
timestamp: October 07, 2015, 08:59:06 am
content: Quote from: richardman on October 07, 2015, 01:17:00 amThat is a key differentiator between what you might achieve and most of the softcore designs. If you can capitalise on that then you might just be able to produce something that is more than a hobbyist project.If you can understand the key advantages in FPGAs that cause them to be used in systems, and can adapt your compiler to take advantage of them, then you might have something interesting. A few key differentiators: large scale parallelism and dataflow, preexisting "libraries" (e.g. DMA engines, FFT processors) or blocks instantiated directly in hardware (e.g. MACs typically for DSP functions), non-C arithmetic operations for DSP (e.g. saturating arithmetic), different memory spaces (e.g. in FPGA RAM vs external DRAM).Note that some softcores come in "pluggable families" where, for example, you can insert/omit features such as multipliers depending on your system's requirements.When choosing a board, look for the onboard peripherals (e.g. DRAM) and ignore boards that skimp on the number of ground connections - because other aspects of their design are likely to be "suboptimum".

author: langwadt
author_rank: Super Contributor
timestamp: October 07, 2015, 09:19:52 am
content: many years ago I looked at this one,http://www.fpgacpu.org/xsoc/xr16.html

author: legacy
author_rank: Super Contributor
timestamp: October 07, 2015, 09:24:00 am
content: Quote from: richardman on October 07, 2015, 02:14:26 amso it's closed softwareQuote from: richardman on October 07, 2015, 02:14:26 ameven if you complete the softcore, the C support is closed, so again here we are with the gcc?/lcc?/sdcc?/... need.Quote from: richardman on October 07, 2015, 02:14:26 amno doubt about that

author: legacy
author_rank: Super Contributor
timestamp: October 07, 2015, 09:35:38 am
content: Quote from: langwadt on October 07, 2015, 09:19:52 amthese articles are 15 years old, and they seem gone lost. Do you know if there is an archive, or where to find them ?Quote

author: Kalvin
author_rank: Super Contributor
timestamp: October 07, 2015, 10:00:57 am
content: Have you looked athttp://opencores.org/projects? Under the section "Processors" there are quite a few examples. Some of those are actually synthesized and implemented on different FPGAs.The best FPGA would be the one for which you have the development tools, which is large enough to fit your design and which doesn't cost you a fortune.

author: langwadt
author_rank: Super Contributor
timestamp: October 07, 2015, 10:05:52 am
content: Quote from: legacy on October 07, 2015, 09:35:38 amthis one is still there:http://www.fpgacpu.org/papers/xsoc-series-drafts.pdf

author: ehughes
author_rank: Frequent Contributor
timestamp: October 07, 2015, 12:22:15 pm
content: Here is the MSP430 already implemented....http://opencores.com/project,openmsp430

author: nctnico
author_rank: Super Contributor
timestamp: October 07, 2015, 06:29:35 pm
content: Quote from: ehughes on October 07, 2015, 12:22:15 pmBut it sucks very bad last time I looked or is this a different project? I want something lean & mean! Overall the quality of the designs on Opencores is so poor I stopped looking at Opencores.What you want is a design which is an open source by-product of a bigger project which then can be extended and used as a part of other projects. That way you share resources without competing.

author: legacy
author_rank: Super Contributor
timestamp: October 07, 2015, 08:51:06 pm
content: Quote from: joeqsmith on October 07, 2015, 02:01:47 amwell done, it looks better than an originalHandyBoardrunning a genuine 68hc11

author: andre_teprom
author_rank: Regular Contributor
timestamp: October 11, 2015, 09:09:54 pm
content: As @legacy has already pointed out, I also agree that the NIOSII archicteture should be considered.

author: Scrts
author_rank: Frequent Contributor
timestamp: October 13, 2015, 07:46:39 pm
content: Have a look to these:http://www.arm.com/products/tools/development-boards/