Does XC2C64A CPLD Have Internal Memory For the Storage of the Code? - Page 1
Forum section: electronics / general

author: 2X
author_rank: Frequent Contributor
timestamp: January 11, 2025, 08:03:33 pm
content: Hello,I have the CPLD (XC2C64A-7VQG100C) where is shorted. I am a little bit confused about the program/code where is stored. After reading on the internet I read that some CPLDs especially the “old” ones have an internal EEPROM where the program is stored but some new CPLDs where is like a small FPGAs don’t have internal EEPROM in order to store the program and they want an external Flash memory. The FPGAs also as I understand each time they power up are reprogramed with the program that is stored in an external flash memory and they reprogramed using SPI protocol. Maybe I am totally wrong; please correct me.At the below datasheet of the (XC2C64A-7VQG100C) I didn’t find something that is referred on an internal memory or any specifications about the size of it. Also, on the PCB around the area of the CPLD I didn’t find any memory so I assumed that has been stored a program in it but I can’t confirm from the datasheet the existence of an internal memory.Datasheet XC2C64A-7VQG100C:https://docs.amd.com/v/u/en-US/ds311What are CPLDs, do they still play a role, how to program them?shttps://www.eevblog.com/forum/fpga/what-are-cplds-do-they-still-play-a-role-how-to-program-them/

author: ataradov
author_rank: Super Contributor
timestamp: January 11, 2025, 10:17:03 pm
content: Yes, those old true CPLDs have internal memory. Not only that, the memory is distributed across the chip, so there is no loading, the device is almost immediately ready from the power up.They don't mention the size because you don't need to worry about it, it is just enough to configure all the configurable things. There is no user memory or multiple alternative images or anything like that.The new devices sometimes are called CPLDs, but really they are FPGAs.

author: 2X
author_rank: Frequent Contributor
timestamp: January 12, 2025, 12:58:07 am
content: Quote from: ataradov on January 11, 2025, 10:17:03 pmThanks for your time to reply.I have three questions if you please.As I understand the new CPLDs is like FPGAs from the side of the processing power but they don't need an external memory for the cofiguration code. Also, in the memory of a CPLD you can't store data like on a microcontroller and If you want then you have to use a microcontroller combined with a CPLD or there is another way?Second, what do you mean with "multiple alternative images"?Third, because I have a similar PCB can I read the "cofiguration code" (I don't now if this expresion is right or what is called the program of an FPGA formally... please correct me) from a working CPLD and program a new one (like on the microcontrollers can be done)?I apologise, but my knowledge about CPLDs & FPGAs are almost zero.

author: ataradov
author_rank: Super Contributor
timestamp: January 12, 2025, 01:53:23 am
content: CPLDs have way fewer resources compared to the FPGAs. They are very limited in terms of processing power. What they are really good at is fast startup time and low propagation time. They are ideal for complicated routing with some minor side functions.You can do a lot of things it all depends on what you need to achieve.Many FPGAs support booting multiple images. Since they use external flash that is usually really big, they can start booting at multiple offsets if necessary. This may be used to recover default factory state or something like that.If it is not locked, then you can read the configuration and program it into an identical device. If security bit is set, then there is not much you can do.

author: xvr
author_rank: Frequent Contributor
timestamp: January 13, 2025, 05:56:15 pm
content: QuoteThis is CoolRunner II series of CPLD. It contain onchip EEPROM and programmed over JTAG. Official way to program it is iMPACT (part of ISE suite). iMPACT can use any supported Xilinx programming cable (real list of cables can be extracted from installed iMPACT - from its Propgramming menu). But it also can program CPLD indirectly by any JTAG cable and programmer. It can generate programming file in one of external formats (SVF, XSVF and Stapl (not sure for the last one)). These files could be processed by separate JTAG programmer (OpenOCD for example)