Polygon pours (grounded) - to pour or not to pour? That is the question! ;) - Page 1
Forum section: electronics / projects

author: krisRaba
author_rank: Regular Contributor
timestamp: November 02, 2018, 05:20:53 pm
content: Hello,I originally posted my question on elektroda.pl but despite of many views there was no single answer :-/ I have no idea why. Maybe here are users keen to share knowledge.Recently I keep thinking about do and don'ts of polygon pours on PCBs.There are interesting articles about various issues, where eg in the chamber someone tests different PCB variants and compare how the placement of components, tracks routing, pours etc. affects the emission. There are also case studies, where the influence of some factor (eg the shape of the pad) is measured across specific parameter (eg the voltage drop across the shunt resistor).But I have not been able to find such a study about polygon pours yet which I find very interesting.1. The first thing. Is the hatch polygon of ground functionally any different from the solid one? I use solid ones myself, but I have a friend who passionately uses hatched polygon pours on the PCB. I heard that hatched polygon pours were easier to manufacture and full surface was more difficult to obtain. It could be true in homemade thermotransfer and etching, but was it also true for mass production? I do not know. Other differences are heat capacity and impedance. But I am not sure if using hatch was popular because of them.Have you met hatch polygon pours in any modern, mass-produced circuit? Or do you know specific cases when it is more desirable than a solid plane?2. Does in the multilayer circuit, where we have power and ground planes inside, pouring the signal layers makes sense?For example, part of a Rigol DS1054Z pcb doesn't have polygon pours on signal layer...... but another part doesIn what aspect adding ground planes (pours) in multilayer pcb will help? Because I know that it can spoil, for example, the impedance of trace when it is too close. Or increase the trace capacity. It seems to me that for these reasons, the ground polygon pours on the signal layer was abandoned in selected parts on the Rigol pcb.Here is the question for antenna specialistsDoes a trace above the ground plane form an antenna? Or this plane shields the trace and "spoil" the antenna?The case seems obvious in two-layer plates, where the ground planes reduce the impedance of the ground leads to the elements, shield them, reduce the signal loops (when the current can come back through plane under the path), etc.3. Planes and via stiching..This fragment has loosely placed polygon pours (without vias, like in lower left corner), and I do not believe that underneath there is no ground plane to connect it in several placesIn other places, they use many vias...I have also heard different opinions here. Some say that such a plane/pour grounded only in one point becomes a transmitting / receiving antenna itself and you should stitch it wherever possible, like on boards with RF modules (via shielding). Others approach it carelessly and save vias as if every one cost a fortune;)What is your experience in these areas? Maybe you have any case studies or whitepapers to share?More of Rigol photos you can find here -https://www.flickr.com/photos/eevblog/albums/72157646442125864What I find very interesting, there is a magic border... The whole "fast-digital signal area" has no additional ground planes/pours, but it appears below ADC at differential pairs (analog)...but only above the screening cans. Inside the can, the traces are routed without pours...However, the other side of the board is all pouredAnd now be wise here. Does the first side not require ground pours because it is still under the shielding back cover, or is it simply not needed at all?The additional ground pour does not cost anything, so it was intentionally eliminated. Maybe they didn't want to spoil the traces impedance and increase the capacity on high-speed digital buses.In turn, there is no metal plate from the front ... visually there are rather slow signals such as switching AC / DC relays on inputs, UART, power supply, etc.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 02, 2018, 09:15:14 pm
content: Quote from: krisRaba on November 02, 2018, 05:20:53 pmInteresting idea. To me, I don't like it as a comparison, because -- while, ultimately, you're merely changing the impedance and coupling between traces, the fact that you're changing it so dramatically (from sizable-fraction to ~negligible) presents more of a structural change, than a continuum change.Consider a PCB as a network connecting pads (ideal ports) together. The coupling between any given pair of ports, at any frequency, is a matrix. Presumably, we want direct connections to have nearly 1.0 coupling, and 0 elsewhere. In reality, there will be nonzero coupling. In some cases, it may be large enough to be significant, or useful even (a microstrip coupler). If the intent is still to have zero, then we can't simply hope for the best!Practical reasons introduce nonlinearity to an otherwise linear situation. Consider a pair of oscillators at close frequencies: if poorly shielded, they will lock together. We went from an intended design to an unexpected result, due in turn to the failure to anticipate how much shielding was necessary.Ultimately, theonlything you're doing, is putting down metal to block waves going through some path. There is no such thing as an electric or magnetic field insulator: you cannot have a permittivity or permeability less than 1 (except in contrived circumstances -- metamaterials). So the only thing you can do is block them. (You can insulate DC, but DC is boring. By definition, nothinghappensat DC. And AC cannot be insulated, as such.)Which necessitates a current flow to block magnetic fields (Faraday's law), and a charge to block electric fields.A metal carries both.Metals also absorb. They have finite resistivity, so waves penetrating into them will get weaker and weaker before coming out the other side. They also have very high index of refraction (dominated by resistivity, which manifests as imaginary permittivity or permeability), so they are very good reflectors.(Superconductors are a special case, where the resistivity is practically zero, and the effect is total reflection. The difference is they are very good reflectors all the way down to DC.)Note that this is a perfectly equivalent description of wiring: in that case, you are shielding some signal from going in any direction but the direction of the wire. A design that needs low coupling between wires, also needs a lot of metal between wires to shield them. So really, you need to apply both approaches for a good design.QuoteI've only seen hatch in a multilayer digital logic board. Probably they didn't care about its exact impedance, and had higher priorities, like manufacturability or planarity. (Or maybe it was thieving that I was seeing -- the opposite of hatching -- I don't remember.)A trace running over a hatched pattern (not aligned to the grid lines) gives what's called an electronic bandgap. Less fancifully: a bandstop filter. Periodic gaps in the ground are equivalent to periodic narrowings of the trace, giving a transmission line lowpass filter. Except, it's only LPF around the 1/4 wave frequency, and it becomes transmissive again by 1/2, and so on (roughly speaking), hence it's only a bandstop function.Where does the energy go? Well, if the hatched pattern is shielded by another layer, it doesn't have anywhere to go, but if not, you've got a leaky ground, and some wave energy radiates.QuoteI rarely pour outside layers, partly because I'm almost never working on designs like this, and it's an awful hassle to place components AND vias AND copper on four (or more) layers and resolve connectivity (and good grounding, and good thermal connection if the motivation is more for thermal conductivity rather than EMC performance).What does it do? More metal.Consider one trace over a ground plane. It's surrounded by metal on almost an entire half-sphere. That's good shielding already, so the coupling to free space is small. Yes, you can still make an antenna this way, but the low coupling dictates equally low bandwidth: you have to make a resonator to drive up coupling at one particular frequency. And then your efficiency sucks because of board losses.Consider one trace over, and within, a ground plane (i.e., surrounded with ground on the same layer: coplanar waveguide). It's surrounded by ground on slightly more than a half-sphere, so the shielding is even better.That's basically all you get.The change in trace impedance, and increase in capacitance, are just derived aspects of the general case: a reduced trace impedance for a given width. This can be advantageous as you can use a slightly narrower trace for the same impedance (assuming it can still be fabricated with good yield), and you have ground traces shielding between the signal traces. The total width probably increases (for a given bus of traces, at the minimum design rules, you've doubled the number of conductors because every other one is ground), but when you need that isolation, it's more effective than simply putting distance between microstrip traces.So, it seems likely what Rigol was doing, was getting that extra bit of shielding, where they could, basically for free -- no parts cost, no shield cover, just PCB fab -- and where it was easiest to do so, i.e., where nearly no components are present. Whereas, under the RF shields, there is a ton of components, and even trying to pour ground between them would be a waste of time!QuotePersonally, I stitch at no more than ~2cm between vias, near circuitry. (Far from circuitry, I don't really care, and I'll sprinkle a few in, particularly at corners and long stretches.) That's probably overkill for most, but would be marginal for power switching, higher speed (say 74LVC family and up) logic and RF.Via density is proportional to upper cutoff frequency times desired attenuation. You might need a dense, multi-row via fence to ensure adequate isolation between traces in an RF mux (>100dB isolation), but digital logic isn't going to give a shit if you route microstrip together (trace separation ~= height above ground plane giving maybe 5% coupling, not even enough to screw up a logic threshold -- assuming it's not a timing-critical clock trace or something, mind).Tim

author: DaJMasta
author_rank: Super Contributor
timestamp: November 02, 2018, 09:38:47 pm
content: Not by any means an expert, but I think the general idea for the scope you're looking at is: flood fill around the analog parts for improved shielding, none near the higher speed digital stuff because there the parasitics could actually degrade signal quality slightly (all that copper capacitvely couples to the signal lines). You can see that they never leave the ground planes floating, cause that can cause reradiation issues, and the via stitching is more dense when close to analog sections, especially when operating at low levels (before input amps). Given that the planes and via stitching are pretty low impedance, they are unlikely to be significant reradiators when grounded, but if you don't have many vias or the ground path is long (higher inductance and resistance), then you could get a high enough impedance of that 'stub' of a ground plane to act as an antenna at high frequencies. These extra ground planes can also add a bit of capacitance to your power rails, which can be useful in reducing noise, but since they add capacitance in the same way to signal lines, the extra attenuation is probably not desirable on the low level front end path. As for using the bottom and not the top, it could just be that the power plane is closer to the bottom of the stack, so to get the decoupling benefits it was better to put there - or maybe they just didn't have too much on the back layer so a fill could have fewer interruptions and be somewhat more effective as a direct low impedance path.As for crosshatching, it's sort of gone out of style. It doesn't really do as good a job of shielding as a solid plane and doesn't offer the extra current carrying capacity for a really low impedance ground... but there are some potential peripheral benefits. It's physically lighter, when using a design where that matters, especially with thicker copper layers (maybe if you're very concerned with the amount of copper used?), and it has lower thermal mass, so it's easy to solder on pads directly connected (but thermal relieves do a fine job on regular flood filled planes). Since it doesn't have the same physical surface area, you don't get the capacitance benefits, so it sort of falls into a category where it has small benefits, but not as many as a flood fill... so most cases you'd consider it, a flood fill offers the same plus some extra, and otherwise it doesn't perform like an area left empty.I think a lot of the design you see is just a result of good practice rules and whatever the layout designer's experience has told them would likely work. I think you could probably design the same board with very different fill areas or crosshatching and still get pretty similar performance, but if the cost is going to be the same and there are potential benefits of using a ground plane as added decoupling or shielding of sensitive areas, why not? When looking at the pours, it's probably worth considering where the breaks in the pour are - you can see that the analog frontends have 'their own' area of the ground plane - it still looks continuous, but the path has been directed away from, presumably, some of the higher speed digital sections.

author: krisRaba
author_rank: Regular Contributor
timestamp: November 03, 2018, 10:45:58 am
content: Thanks for your answers.Quote from: T3sl4co1l on November 02, 2018, 09:15:14 pmI like the idea of couplingInteresting point of view.Quote from: T3sl4co1l on November 02, 2018, 09:15:14 pmOk, this all make sense. One thing I am not sure is the ground "pollution". I know there are situations where high current paths should be routed in controlled way. This is because of voltage drops and noise "injection" casued by current spikes (resulting in dynamic voltage changes across path) etc.So I really don't want to route such high current paths (or even planes) under sensitive circuits.Now lets assume we have POWER + GND high current tracks to such noisy load. They are placed on TOP layer. Should I use a ground plane underneath them? GND is the same ground potential I use for logic. I think that this GND track should be connected with plane only in one point, near board power connector to avoid high current flow through that plane and keep it in dedicated track. Plane should shield these noisy tracks. But if it is one big plane (on BOTTOM layer or internal ground plane) won't it be "polluted" and cause noise injection to other circuits? Can plane act like that? Or it should be always considered as low-impedance, dominating distributor of potential?In mentioned example ground plane underneath high current tracks could be also separated by gap and connected in one point but I am not sure if it would be better or worse solution.I have seen in many boards additional gaps in ground plane to cut current paths and force them to go around some section. It can be also seen on Rigol's photos on side with BNCs (vertical gap).From this I presume that noisy current flow has to be avoided near or underneath sensitive circuits but shielding capability dominates over receiving noise from outside of ground plane.Quote from: T3sl4co1l on November 02, 2018, 09:15:14 pmOk, so if I get it right, polygon pours on signal layers have more to do with supressing crosstalks than with shielding outside world.Quote from: T3sl4co1l on November 02, 2018, 09:15:14 pmHere I am not so sure. For me it looks like plenty of space. With CAD soft available nowadays you only draw the outline and software does the magic. Add some vias to ground plane and voila, you are ready.I think under the cans there is plenty of things to avoid for high bandwidth small signals. Any polygon pour influence could ruin your design performance and it seems to be easier to avoid pours at all than keeping them in spec. Differential tracks outside the cans are already low-impedance outputs of front-end op-amps so can handle additional capacity easier. And grounded polygon pour supress crosstalks between channels here, I think.Quote from: DaJMasta on November 02, 2018, 09:38:47 pmIf it is 4 layer board you may be right. TOP layer high-speed tracks are over ground plane for controlled impedance so power plane is deeper in stack, which means closer to BOTTOM.BTW. I wonder where front panel USB differential signals disappearedOn top side only power and ESD protection can be seen, on bottom side there is only USB connector and ground plane. Are they routed on power plane? Interesting.Quote from: DaJMasta on November 02, 2018, 09:38:47 pmI don't use it as I can't see any benefits over solid fillBut I asked in case of missing something importantQuote from: DaJMasta on November 02, 2018, 09:38:47 pmYeah, experienceI try to avoid some voodoo-stuff and this is why I always try to understand what I doSometimes things require extra effort and it wouldn't be good to implement solutions that I have seen somewhere but are inadequate to my particular design, like nervous via stitching and fencing in low-frequency designsSuch things will work with and without that effort so by doing it you wouldn't know that it has no senseOn the other hand, I don't want to intentionally omit everything to see that it doesn't work as expected or fails EMC measurements, then {add one thing, fail again }(loop here), oh.. now it passedHurray!

author: spec
author_rank: Frequent Contributor
timestamp: November 03, 2018, 12:07:42 pm
content: Wow! some interesting information on this thread.On a very mundane point, doesn't hatching a large copper area relive the differential expansion and thus reduce board distortion too?(hope this point hasn't already been made, and I missed it)

author: krisRaba
author_rank: Regular Contributor
timestamp: November 03, 2018, 02:07:55 pm
content: I think that thermal mass difference between board sections could result in increased board/components stress for fast temperature changes (if this is what you meant). But in such circuits I would probably prefer slowing down local changes by putting board into larger thermal mass (eg metal case) than look for solutions like crosshatching where unexpected behaviors could defeat me

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 04, 2018, 01:38:19 am
content: Quote from: spec on November 03, 2018, 12:07:42 pmThat's right!Expansion could be a reason to use hatching.For high-frequency designs, they can cause issues though for impedance reasons.I've never seen a good reason to use hatching on copper areas on conventional FR4 PCBs in ages.I have for flex PCBs though. Solid copper areas can make a flex PCB way too rigid.

author: spec
author_rank: Frequent Contributor
timestamp: November 04, 2018, 04:09:16 am
content: Thanks for confirming.At work we did a bit of high speed stuff and built development circuits on PCB material with solid copper planes. After a few weeks the boards would often warp a bit.Perhaps a touch off topic, but as the parametric aspects of PCB design are being discussed, there is some fairly good info in this book:http://www.bitsavers.org/components/motorola/_dataBooks/1989_Motorola_MECL_System_Design_Handbook_4ed.pdf