Wien Bridge project - Page 1
Forum section: electronics / projects

author: richlooker
author_rank: Regular Contributor
timestamp: February 09, 2021, 03:12:07 pm
content: I have embarked on designing and building a wien bridge based sine wave generator, with the following desired characteristics;10Hz-100kHz frequency range, divided into four decade ranges (using 1% PP capacitors 1nF, 10nF, 100nF, 1µF)Low distortion and fast settling time26 discrete & precise frequency steps per decade (I intend to put to use an old 26-position two-deck rotary switch I have had lying around for ages)Output 1.55V-1.55mV adjustable in 10 6dB stepsI have been playing around with breadboarding of various designs. To have the frequency scale as intended with the capacitors, I need a fairly high bandwidth amplifier; a plain NE5532, TL072 etc. won't do. I found this design (https://sound-au.com/project179.htm) interesting:It has the bandwidth required, attains the theoretically correct frequencies, but amplitude bounces badly on frequency change and takes too long to settle. Any attempts to replace the feedback network with a higher-impedant one more suitable for electronic stabilization resulted in self-oscillation at 7-8MHz.Here it is on breadboard - using Global Specialties breadboards exclusively, after endless frustrations from working with cheapo Chinese no-name ones.I tried this design:https://sound-au.com/project174.htm- instead of TL072 or NE5532 as suggested, I used the higher-bandwidth LT1253; this is dubbed a "video amplifier" but I thought; an amp is an amp.The breadboarded sample&hold peak detector. This design has several limitations, but I was hoping it would work for my purposes.I couldn't make the sample&hold peak detector work below 100Hz or above 10kHz, so I parked that and went for the "precision full-wave AC-DC converter described here:https://www.nutsvolts.com/magazine/article/op-amp-cookbook-part-4After endless tinkering to make the optocoupler feedback stabilize the amplitude, getting nothing but squegging, probably because of the slow response time from the LDR, I gave up and tried the JFET-based stabilization circuit described here instead:https://sound-au.com/articles/sinewave.htm#s44I failed in adapting the dual-opamp oscillator design from the "free-floating" LDR stabilized feedback to the ground-referenced JFET design, so I tried a simpler oscillator design, based on this reference design from Linear Technology:https://electronics.stackexchange.com/questions/274570/wien-bridge-oscillator-lt-super-low-distortion-variable-sine-wave-oscillator-dOK, now I could get the frequency to extend to 100kHz, but stabilization vs. distortion vs. settling time is still a challenge, and I really need different values per frequency decade for the integrating capacitor in the rectifier circuit.To be continued...

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: February 09, 2021, 05:43:54 pm
content: I think a certain amount of bounce comes with low THD. IMO, everything you might want to know is here-https://www.diyaudio.com/forums/equipment-and-tools/205304-low-distortion-audio-range-oscillator.htmlIt's understandable if you just conclude ;TLDR!

author: Benta
author_rank: Super Contributor
timestamp: February 09, 2021, 06:01:41 pm
content: The amplitude bounce problem is well known with Wien bridge oscillators and stems from the gain regulation.The gain is critical for low distortion and oscillator start and is classically done with either a self-heating NTC, or in your case an incandescent bulb.Both are slow.There are more modern ways of gain control that stabilize faster, eg, JFET control, but the distortion characteristics are usually not as good.For a really good high speed op amp, I can recommend LM6171/6172 from TI. I have have used these with success.

author: richlooker
author_rank: Regular Contributor
timestamp: February 09, 2021, 06:15:49 pm
content: Quote from: Conrad Hoffman on February 09, 2021, 05:43:54 pmThanks for the input, Conrad. Alas, I have read that thread and everything it references already. My requirements for frequency range 10Hz-100KHz go beyond the capabilities of any of these designs, many of them are theoretical and/or untested, and stating "no settling time" for a lamp-stabilized oscillator is IMHO a lie. Also, seeing the data for the commercial/professional lamp-stabilized designs - HP200[A-CD] and General Radio 1316 - the distortion rises sharply below 100Hz.I believe the only way to achieve low distortion at low frequencies is by using peak detection / sample and hold. I am experimenting with modifications to the ESP design at sound-au.com; I am pretty sure it can be improved upon to handle 10Hz well, and probably also the upper decade 10kHz-100kHz.Quote from: Benta on February 09, 2021, 06:01:41 pmAnd thanks for your input, Benta. I will check out these opamps. I have decided to stick with JFET control, with the distortion-minimizing tricks applied in the design I showed in the initial post.Cheers, Richard

author: Benta
author_rank: Super Contributor
timestamp: February 09, 2021, 06:28:12 pm
content: The problem is, that at very low frequencies, the gain control natural frequency is close to the oscillator frequency and thus suddenly becomes part of the oscillator itself.Your peak detect approach sounds interesting, let us know your results.Cheers.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 09, 2021, 06:44:51 pm
content: Is the bounce really that bad? I always got the impression that was normal, and these things weren't supposed to be agile or anything, just set it and wait for it to stabilize.If you wanted an agile source in that era (60s tech), you might go for a dirtier oscillator followed by a filter. Switched-cap filters are pretty cheap and effective, and the clock frequency is readily available here so it's no big deal to make a variable filter in this way. (Whereas using OTAs for a variable continuous-time filter is a PITA. Also, "just make it good in the first place" would be the HP approach, endless optimization of a circuit to balance performance at all corners. That's the final-boss PITA that you're up against, here, I think.)So, speaking of OTAs, I found this to be pretty effective:OTAs are certainly contemporary, if not in IC form then they're easy enough to make discrete as well.If you've taken higher level EE courses, you may recognize this as an implementation of the differential equation of an oscillator. IC1A and IC2A are integrators, R10 introduces a damping term, and IC1C provides a controlled negative damping term. The differential equation equates the second integral of the signal, to itself, with a first integral term having a coefficient of zero for no damping (stable amplitude), or positive or negative for decay or growth respectively.The components are nonideal, so there will be some poorly-defined amount of damping in the system, varying with operating point; effectively, this makes damping biased towards decay by default, with a variable amount of growth on top of that. Exactly how much growth is needed to reach stable (constant amplitude) operation, that depends, but we can solve that with a feedback circuit.My intent with this circuit was to get reasonably low distortion, and stable (or even controllable) amplitude, with frequency variable over a modest range. It seems the amplitude is quite controllable indeed, which is at odds with the theoretical basis -- the trick is the OTA's tanh(x) transfer curve, only linear for very small inputs (~10mV). As amplitude rises, average gain drops, gradually turning the integrator output towards a more triangular shape (it's nonlinear, it introduces distortion of course), but also limiting the amplitude. So it happens that I could measure the circuit as shown, with just a trimpot for amplitude control -- I didn't have to implement AGC. (I did add that later, using a simple precision rectifier and error amp; alas I don't have the schematic handy.)The best part about this circuit is it produces quadrature (or, very nearly so, again given that the damping terms cause a little phase error). A downside is, because there's a fixed integrator in the loop, the amplitude of one channel varies against the other, while varying frequency. So it's not a constant amplitude quadrature oscillator. That could be fixed by changing IC2A to another OTA (hmm, and R10 might have to be variable as well?), or adding an amplitude regulator to the quadrature output.Also, the noise performance probably isn't great (the impedances are quite high, and the voltage dividers can't be helping), but I'm not trying to do precision audio testing with this. YMMV.So, this is commonly called a quadrature oscillator, or state variable oscillator (state variables meaning, the integrals of the signal).This is rather beside the OP question (Wien bridge), but it sounds like you're more interested in any good oscillators, than in that type specifically, so that's okay.And, as for that -- you can implement the gain control element in much the same way, i.e. using an OTA as a variable resistor or gain stage. Then you can control the dynamics however you like.The problem with the lamp is, while its thermal time constant is largely diffusion based (which is good, that should leave about 45 degrees phase margin at any frequency in the asymptotic range), it's limited in size (the asymptote doesn't extend to infinite time, it has a longest time constant somewhere in there), so will naturally go unstable at low enough frequencies. To solve this, simply use a bigger bulb, of course! But then settling will be obnoxiously slow at high frequencies, taking thousands of cycles say.There can be no simple solution to this -- you need the amplitude control function itself, to be controlled proportionally alongside the oscillator.So we might solve that, by using both halves of a dual OTA, one for the variable resistor in the oscillator loop, one for a variable term in the control loop. A third (normal op-amp) does error amp duty. Varying the second OTA, in step with the oscillator setting, the control loop response can be made to track the oscillator frequency.Also, you don't want the control to respond too quickly, because it will convert some of the detector's ripple into amplitude ripple -- distortion. In general, disturbance in the control loop is mixed into the oscillator response, so for example if the control has some 60Hz injected into it, you'll get 60Hz sidebands on your output. Same for any other noise, including input noise of the error amp itself, etc. This sets a limit on possible settling time versus distortion, and on the noise floor, phase noise, whatever.A possible solution is an ideal detector, i.e., given a waveform A sin(w t), it returns the amplitude A regardless of phase t. The easiest way to implement this is using the Pythagorean identity, sin^2 t + cos^2 t = 1. For which you need an ideal quadrature circuit -- which is a point in favor of the quadrature oscillator. You then need a pair of squarers, then the sum is the amplitude --with zero ripple, no filtering required-- which can then control the amplitude exactly over time. (Which, if this is starting to sound like more of a PITA, you're right. Now you understand why analog computers went out of favor...)Otherwise, the problem with tracking the control response is, it has to track with the oscillator rate. Presumably you'd use a double ganged potentiometer to set the Wien bridge resistors; a third gang I guess could be added to get a control voltage, which can be offset as needed, to at least match the required response at two points. Hopefully a linear response matches nicely -- it's not obvious to me offhand if it would be linear, or follow a curve. If it actually needs a curved response (like, a hyperbolic section often shows up in situations like this, i.e., the gain needs to vary inversely with control level), then it can be tuned to match at two crossing points, and it'll settle worse away from those points. (Hopefully not so much worse that it oscillates.) Maybe it's a narrow enough range, and the tolerance is loose enough (say +/-20% of ideal settling), that it's fine. Anyway, the point I want to get at is, wouldn't it be great if the Wien bridge itself were variable, by that same control voltage, and proportional to it? So you could transform the resistors or capacitors with OTAs, or some other kind of analog multiplier.At this point, it's just a little rearrangement, really, to make a state variable oscillator with OTAs -- so, one might argue it's still semantically correct, assuming one allows the above transformations. (Which is just a really technical way of saying, "I know you said Wien; well, teeeechnically...")Anyway, despite the exponentially greater semantic complexity... this is really making a DDS look attractive, isn't it?Tim

author: RoGeorge
author_rank: Super Contributor
timestamp: February 09, 2021, 07:19:15 pm
content: ThisWien Bridgeis fast settling and very low distortions:https://www.eevblog.com/forum/projects/low-distortion-audio-oscillator-stabilized-via-trigonometric-identity/

author: blackdog
author_rank: Frequent Contributor
timestamp: February 09, 2021, 07:25:37 pm
content: Hi richlookerFirst of all, my compliments on the way you put the components on the breadboard!Except for myself, I don't see that often.Below you see two links of a sine wave oscillator project by the designer J.S. Tregellas.I built the schematic with LME49860 opamps.With a well chosen ratio of the LED current and series resistance of the LDR, the distortion is less than 0.001%.which I measured with my Audio precison measuring set in the middle of the audio frequencies.You can get the distortion in the low frequencies a little lower by increasing the RC time of the rectifier.Those are the 100 Ohm resistor and the 100uF 16V capacitor.A well-chosen LED / LDR combination will give almost no bounce.That was very noticeable about this circuit.Schematichttp://www.users.on.net/~endsodds/aocct.jpgProject pagehttp://www.users.on.net/~endsodds/ao.htmKind regards,Bram

author: richlooker
author_rank: Regular Contributor
timestamp: February 09, 2021, 07:28:38 pm
content: Quote from: T3sl4co1l on February 09, 2021, 06:44:51 pmI did indeed take higher level EE courses, but I did not recognize this. Might have something to do with the fact that my university years were 1989-1993, and I have never touched stuff like that since then. Thanks for taking the time to write all this; interesting concept, but it's going to be wien bridge until I succeed or am forced to give up.Quote from: T3sl4co1l on February 09, 2021, 06:44:51 pmNope, I prefer doing it the right/hard way in the first place.Quote from: T3sl4co1l on February 09, 2021, 06:44:51 pmI'm in fact really, really interested in making a good wien bridge based design, I have been playing with it on and off for years, but now I am determined. David Packard and Bill Hewlett designed the HP-200CD in 1955, how hard can it really be to make a 10Hz-100kHz wien bridge with modern components? And is fast settling time _and_ low distortion really to much to ask for???Quote from: T3sl4co1l on February 09, 2021, 06:44:51 pmNever. The digital domain is devoid of beaty and eleganceQuote from: RoGeorge on February 09, 2021, 07:19:15 pmInteresting concept - albeit not a wien bridge - but I will pursue the peak detector solution first, which if I can get it right will output a "D.C. voltage whose amplitude is proportional to the amplitude of the outputs and independent of frequency"Cheers, Richard

author: Benta
author_rank: Super Contributor
timestamp: February 09, 2021, 07:47:47 pm
content: As you're planning to use a decade switch anyway, an approach could be to use this to set the gain control loop's natural frequency as well (making a double or ganged decade switch necessary, of course).This would give you relatively slow settling at low oscillator frequencies, but fast settling at high ditto.The second issue is the gain loop's damping ratio. If you can set it to critical damping, the amplitude settling time would be low.The third is the gain loop's "own" gain. If this is set to be low enough to allow the oscillator to start, but no higher, this would also limit the amplitude bouncing.

author: richlooker
author_rank: Regular Contributor
timestamp: February 09, 2021, 07:49:39 pm
content: Quote from: blackdog on February 09, 2021, 07:25:37 pmMy brain works like that; I don't trust anything that looks like a rat's nest - it has to be neat and orderly, and I have to be able to spot easily how everything is connected. Also, aestheticsQuote from: blackdog on February 09, 2021, 07:25:37 pmOK, a phase-shift oscillator. I might try that later. But I am very skeptical towards the LED/LDR feedback, at least I have not been able to tame it, especially at frequencies <100Hz.

author: RoGeorge
author_rank: Super Contributor
timestamp: February 09, 2021, 09:35:16 pm
content: Quote from: richlooker on February 09, 2021, 07:28:38 pmOoops, entangled memories! Not Wien, sorry.Just that when I found out about the idea of summing the square of quadrature signals in order to control the amplitude, I thought maybe it'll worth trying that to stabilize a Wien bridge. Never put that into practice yet.So far I've tried to stabilize a Wien Bridge in two ways- with a miniature incandescent light bulb; that worked unexpectedly well- with a JFET (as a resistor controlled by a diode peak detector) it also worked, but with higher distortions caused by the little ripple after the diode peak detector and because of the JFET nonlinearity with Vds (at high amplitude the distortions were so big that they were visible even on the oscilloscope).Found that breadboard!There use to be decoupling 10uF||100nF on each power line, near each IC (not present any more in this pic), but a mandatory add for low distortions and stable oscillations. ThatAD509KHdriving the Wien Bridge is a beast of an opamp, best opamp I've ever had.Later edit:Wow, I see only now you updated the OP with lots of pics and details, nice project!

author: Vovk_Z
author_rank: Super Contributor
timestamp: February 09, 2021, 11:44:20 pm
content: Quote from: Benta on February 09, 2021, 06:01:41 pm+1.Here is a good stable one in an attachment. Not a Wien bridge, so very stable with live frequency changing. Doesn't need stereo potentiometers. It has 0.006% as is but can go up to 0.001% with some small changes (R3 can be decreased up to 22-27k). I used 2N5484 instead of 2SK30.

author: Vovk_Z
author_rank: Super Contributor
timestamp: February 09, 2021, 11:51:05 pm
content: Here I found my 50 Hz project (43-53 Hz). Very cheap and reliable:

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: February 10, 2021, 12:26:47 am
content: Another thought, though probably not a Wein. Have a look at the oscillator used in the Bob Cordell THD analyzer project published in Audio many years ago. I don't remember it having much bounce, but probably a bit.http://www.cordellaudio.com/papers/build_a_thd_analyzer.shtmlIt gets down below 0.001% and has decently wide bandwidth. The downside is it needs multi-deck switches that aren't as widely available as they used to be. Some people have used small relays and such.

author: RandallMcRee
author_rank: Frequent Contributor
timestamp: February 10, 2021, 01:31:43 am
content: The thread that Conrad first recommended over on diyaudio has much, much more information...Anyhoo, here is a very good one that I have built and settled on some years ago...it has some nice features and is quite stable. This basic design (courtesy of Janas Card) is in that thread, but, of course, is hard to find.http://www.janascard.cz/PDF/An%20ultra%20low%20distortion%20oscillator%20with%20THD%20below%20-140%20dB.pdfGood luck!

author: David Hess
author_rank: Super Contributor
timestamp: February 11, 2021, 01:47:31 pm
content: Jim Williams has an extensive discussion of Wien Bridge oscillators starting on page 29 of Linear Technology application note 43 including the need for common mode suppression.

author: jonpaul
author_rank: Super Contributor
timestamp: February 11, 2021, 02:14:57 pm
content: Hello all:Jim Williams Lin Tech note is the best, he was a scion in the industry and had studied and restored the old HP 200s.The incandescent lamp has been replaced by optocouplers and balanced FETs in some designs.Finally the THD, and output V requirements affect the design, many tradeoffs.Kind Regards,Jon

author: RoGeorge
author_rank: Super Contributor
timestamp: February 11, 2021, 02:37:46 pm
content: Quote from: David Hess on February 11, 2021, 01:47:31 pmSome extra tails and details in the chapter 7 of Jim Williams' book "Analog Circuit Design Art, Science and Personalities":"7. Max Wien, Mr. Hewlett, and a Rainy Sunday Afternoon"http://www.introni.it/pdf/Williams%2007%20-%20Book%20Chapters.pdf

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: February 11, 2021, 09:07:48 pm
content: I believe some of that material is copyrighted and shouldn't be there.

author: richlooker
author_rank: Regular Contributor
timestamp: February 11, 2021, 11:15:35 pm
content: Quote from: Conrad Hoffman on February 11, 2021, 09:07:48 pmDang. That didn't occur to me. You are probably right, thanks for pointing that out. I'll contact the owner of sound-au.com and ask for permission.Cheers, Richard

author: MikeK
author_rank: Super Contributor
timestamp: February 11, 2021, 11:17:56 pm
content: I was just reading in "Timer/Generator Circuits Manual" by R.M. Marston that the bounce problem of variable Wien circuits can be minimized with diode stabilization (two diodes in anti-parallel in the feedback path). See page 19. Can also be done with back-to-back Zeners (page 20).

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: February 12, 2021, 12:14:43 am
content: Actually, it was the Jim Williams book chapters I suspect shouldn't be up there. I have the book and highly recommend it.

author: JoeyG
author_rank: Regular Contributor
timestamp: February 12, 2021, 01:02:19 am
content: How about digitally ?This example goes to 24KHz @ 0.6% distortionhttp://archive.siliconchip.com.au/cms/A_111885/article.html

author: richlooker
author_rank: Regular Contributor
timestamp: February 12, 2021, 11:52:43 am
content: Quote from: Conrad Hoffman on February 12, 2021, 12:14:43 amWith respect to the diagrams I copied from the sound-au.com site, I received this response from Rod Elliott, the owner:QuoteRichard

author: richlooker
author_rank: Regular Contributor
timestamp: February 12, 2021, 11:58:53 am
content: Quote from: JoeyG on February 12, 2021, 01:02:19 amThat kinda defeats the purpose. For me this is more a research project than a practical one. I specifically want to use a wien bridge oscillator, hoping I will learn something along the way, and IMHO the digital domain is lifeless and boring. ANyone can hook up an Arduino and load a program from a website, but where's the fun in that?Cheers, Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 12, 2021, 12:01:33 pm
content: Quote from: MikeK on February 11, 2021, 11:17:56 pmDefinitely, yes. And, as the feedback is non-linear, it also introduces more distortion than any of the linear VGC methods.Richard

author: Vovk_Z
author_rank: Super Contributor
timestamp: February 12, 2021, 12:26:28 pm
content: Quote from: richlooker on February 12, 2021, 12:01:33 pm- Hm?

author: richlooker
author_rank: Regular Contributor
timestamp: February 12, 2021, 01:45:30 pm
content: Quote from: Vovk_Z on February 12, 2021, 12:26:28 pmI know, not really linear as in linear, but with a time constant that makes them behave linear or near-linear at the oscillator frequency; a filament lamp, FET or optocoupler will stabilize amplitude based on averaged amplitude, while diodes will stabilize based on immediate amplitude, ie. for each positive or negative peak.

author: David Hess
author_rank: Super Contributor
timestamp: February 12, 2021, 06:39:12 pm
content: Quote from: jonpaul on February 11, 2021, 02:14:57 pmThere is a tricky compromise in the gain control. The common Wien bridge has one side grounded which grounds one side of the gain control element simplifying things. But when common mode suppression is added to the Wein bridge which eliminates the distortion caused by limited common mode rejection of the amplifier, the gain control element is no longer grounded and must be floating which is easy to do with an incandescent lamp or optocoupler but not so easy with FETs.There *are* ways to make a balanced FET gain control but I have never seen them used with a Wien bridge so it may be worth looking into if you want to do something new. Take a look atschematic 7 of the Tektronix 7D20for an example of a balanced JFET gain control; it uses a dual JFET because its control is open loop but a closed loop control only requires a single JFET.The better alternative now is to use a VCA as shown in the oscillator designed by Dale Eagar which can be found on page 26 ofLinear Technology Magazine of February 1994where he uses an LT1228 transconductance amplifier. If you do not want the ultimate of performance using his design, then adapt the LT1228 gain control to a simpler design without the "super" gain blocks. This is what I would do.

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: February 12, 2021, 08:26:33 pm
content: One should also be aware of the vacuum thermistors used for gain control in the GR and various other oscillators. They were a tiny spec of thermistor in an evacuated glass tube, which allowed them to run hot with minimum power. Great device but AFAIK, no longer in production.http://electrojumble.org.uk/DATA/STC_B_&_R_Thermistors.pdf

author: richlooker
author_rank: Regular Contributor
timestamp: February 13, 2021, 01:23:44 am
content: Quote from: David Hess on February 12, 2021, 06:39:12 pmCode:An Ultra-Low-Distortion,10kHz Sine-Wave Source forCalibration of 16-Bit orHigher Analog-to-DigitalConvertersThere has now been posted > 10 suggestions for low-distortion oscillators, but not one of them are designed for operation over four decades, as is my requirement.Cheers, Richard

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 13, 2021, 01:53:24 am
content: I suspect that, given:- Enough OTAs- Enough decks of switches- Enough ganged potentiometersYou've listed / seen enough designs that, I suspect, given the above -- such is possible. All that's left is, y'know, "draw the rest of the fucking owl" as the meme says.As I mentioned earlier -- such is the realm of the highly-optimized classic-HP design, and there's really not much to substitute for that -- given that digital solutions are specifically excluded! You've seen a number of designs, of varying complexity, that handle their (necessary, as noted from a theoretical basis) nonlinearities, in various ways, time-dependent or not; with consequential compromises in distortion and settling. These are designs in vary degrees of completeness, for various purposes; to make a truly general purpose unit, plenty of work will be required, doing all that refinement and optimization. Free lunches and all that.Tim

author: richlooker
author_rank: Regular Contributor
timestamp: February 13, 2021, 01:54:08 am
content: There are three distinct problems for me to tackle;A basic oscillator with inherent bandwidth high enough that a given resistor value of the RC element will yield close enough to the theoretical frequencies with the four different capacitor values (1µF-100nF-10nF-1nF)A gain control element which introduces minimal distortionAn amplitude-to-DC converter with fast and frequency-independent settling timeI will concentrate on the latter for now, and I have decided to stick with the sample&hold peak detector concept until either I'm satisfied or I have to conclude it's not feasible. As I wrote in the initial post, there are a number of shortcomings with the design suggested at sound-au.com, and I have tried to address these.COmponent designations in the following description refers to the original diagram, from this article:https://sound-au.com/project174.htmThe diode D2 introduces a voltage drop, unavoidable with this circuit topology, but I have replaced the basic diode with a Schottky to reduce the voltage dropThe antiparallel diodes D2/D3 are supposed to let C9 hold the peak for a while, until D3 starts to conduct and C9 discharges, tracking the input voltage. This means there is a small and frequency-dependent time window where the sampling has to occur, and it also means the further circuitry has to handle both positive and negative voltages. I have removed D3, and instead added a comparator that, as the input signal falling edge crosses zero, opens a JFET that discharges the capacitor. This capacitor is shorted by the JFET for the entire negative half waveThe buffer JFET Q1 is nonlinear in this configuration, and DC across R15 restricts the input voltage tracking range. The secondary comparator U2B shorts the hold capacitor C11 through Q3when the input peak is below a given level to compensate for this; I have replaced the single JFET buffer with a JFET input opamp, making the comparator/transistor arrangement redundant. This also helps with droop, as C11 would discharge through CE leakage current in Q3The LM2903 comparators are too slow for operation at 100kHz; I have replaced them with LM311P which has a response time of ~150nSThe peak tracking capacitor C9 is connected directly to the input of comparator U3A, increasing droop; I have introduced a JFET input opamp between theseThis is my modified/enhanced circuit:The VM/AM meters are there for transient analysis; I will shortly post my results.Cheers, Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 13, 2021, 02:06:02 am
content: Quote from: T3sl4co1l on February 13, 2021, 01:53:24 amI will employ plenty of decked switches. One challenge I have to overcome is I need to make a three-deck/6-pole 4-position switch out of two dual-deck/four-pole ones.Ganged potmeters are out of the question; if such ones with the needed precision even exists, I'm sure they are way beyond my budget. I have a dual-deck 26-position rotary switch I will fit with a resistor ladder to get 25 discrete frequencies per decade - for now I have calculated the values and prepared resistors to get (for the second decade) 100, 110, 120, 130, 145, 160, 175, 190, 210, 230, 250, 275, 300, 330, 360, 400, 440, 480, 525, 575, 630, 690, 760, 830 and 910 Hz +/- 0.075% (theoretically)Cheers, Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 13, 2021, 11:18:14 am
content: I have established that, in order to keep settling time fairly independent of frequency, I need different values of the sample pulse timing capacitor C2 for each decade. Here are the waveforms with a 1kHz signal and C2 at 10nF.The sampling switch T2 exhibits a couple of anomalies I don't understand;It has a voltage drop drain-source of about 0.3-0.4 V - not a big deal considering I'm not that concerned with the absolute value of the peaks, but can it be avoided?During sampling, Rds must be as low as possible, so Vgs has to be 0V or slightly higher. As both drain and source are floating, the voltage at source is not known, so I just have to ensure that Vgs is high enough. This means the base-substrate diode will be forward biased and start to conduct, this leads to a current that contributes to the capacitor charge, shown as the little peak on VM4. What I don't understand is that it discharges again when the sampling pulse VM3 falls, how can this be?Cheers, Richard

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 13, 2021, 12:11:46 pm
content: Usual way to drive JFETs is to pullup gate to source. The enhancement going to positive Vgs isn't substantial, and if you need lower Rds(on) just choose a bigger JFET.Kind of related: JFETs should possibly behave as UJTs, i.e. enhancing significantly under charge injection (forward gate bias). I haven't observed any significant effect in switching JFETs -- perhaps UJTs have much lower doping, and much longer base length, exaggerating the effect?With a J110, Rds(on) shouldn't be a problem. The max 85pF Cg(on) is a pretty big fraction of 1nF though. Perhaps a smaller one would perform better.May also find better results (less charge injection) using balanced CMOS switches.Tim

author: richlooker
author_rank: Regular Contributor
timestamp: February 13, 2021, 04:44:13 pm
content: Quote from: T3sl4co1l on February 13, 2021, 12:11:46 pmI know, but there is no way to pullup gate to source, or maybe - can I use the output of U6 in some way? Maybe through an analog switch?Quote from: T3sl4co1l on February 13, 2021, 12:11:46 pmYou mean a JFET with lower Cg(on)? Suggestions?Quote from: T3sl4co1l on February 13, 2021, 12:11:46 pmI have considered this, but that will require higher gate voltage, ie. minimum Rds for a MOSFET requires Vgs > 4V, right?/Richard

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 13, 2021, 07:04:25 pm
content: Quote from: richlooker on February 13, 2021, 04:44:13 pmPull to the low impedance: T1 to ground, T2 to U1b output.I wonder what LM311 output capacitance is, or in general how its output switching depends on load current and capacitance. Its output capacitance isn't specified. D3 probably isn't useful in the end, but I wonder if a cascode would be (e.g. a 2N3904 with R + 2 x diodes voltage divider for base bias, maybe with a Baker clamp as well). In other words, keep the LM311 output voltage swing small, assuming its current swings faster. It can also be biased up to run at higher current (mind to put in a voltage limit so it doesn't pull the 3904's emitter into breakdown).As for generally faster comparators, I don't have a good recommendation offhand; the next faster option in my box is MCP6561 which is 5V max (and CMOS output). I'm sure there is something available; I do recall there's a big gap between classic parts (~100s ns response time) and fast ones (<10ns), just don't be alarmed if it happens to be far faster than you expected.QuoteWell, J112 and friends, kind of the next step down I guess; PN4391 similar; or the few remaining RF JFETs (be careful not to make them oscillate) with Rds(on) around there. 2N5486 might be on the small side, BF862 (or its newer replacement CPH3910) is probably about right.Rds(on) far below 100 ohms doesn't seem all that useful, as the TL072 isn't capable of much more current than an equivalent resistance around there. For T2 at least.I think the required sample window (essentially 3*Rds(on)*Csample, say) versus charge injection (ΔVg * Cg(on) / Csample) is a roughly constant amount. There isn't much performance difference among JFETs, it's mainly about how wide the channel is; and a wider channel has proportionally more capacitance and less resistance. The main difference is in fine optimizations, matching channel width to circuit impedance (hence ~100s ohms or ~10s mS parts are most practical at RF), and how much extra capacitance comes from wiring/pad connects, I think.QuoteYes, well you have +/-9V supplies so that's no problem at all.DG401, DG612, TC4W66FU, even the bog standard 4066 may do.CMOS switches work over the full supply range. At low voltages (near VSS), the NMOS is doing the work, at high voltages (near VDD) the PMOS. There is an peak in the middle, in Rds(on), particularly exaggerated at low supply voltages -- IC MOS are more like Vgs(th) = 1-2V, so for supply voltages around twice that, they stop working (Rds(on) just too high at middle voltages). At 18V supplies, Rds(on) will be pretty stable, and as low as it gets for most parts.Tim

author: MikeK
author_rank: Super Contributor
timestamp: February 13, 2021, 07:51:20 pm
content: This project is on my to-do list. Uses an LED/photoresistor for gain control. Claims low THD. Perhaps it could be expanded to include your needed range?http://redcircuits.com/Page82.htm

author: richlooker
author_rank: Regular Contributor
timestamp: February 14, 2021, 12:06:29 am
content: Sampling pulse timing capacitor per frequency decade:10Hz-100Hz: 100nF100Hz - 1kHz: 10nF1kHz - 10kHz: 1nF10kHz - 100kHz: 100pFA close look at T2 gate current, sampling pulse and output voltage at 10kHz, C2=1nF:For some reason there is a small "pre-pulse." The positive gate current inrush is probably insignificant, but the reverse current flowing out from the gate when Vgs goes negative approaches 60mA, I assume this is the source-gate on-capacitance (J110: max 85pF) discharging./Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 14, 2021, 12:42:53 am
content: Increasing the hold capacitor C3 to 10nF all but eliminates the ripple on the output voltage. In the original design, this capacitor is 100nF; I reduced it in an attempt to make do with a single C2 value across the entire frequency range, and I could bring it down to 1nF without droop as I removed the "output shorting" BJT, but 10nF should be OK and still give fast settling times.

author: richlooker
author_rank: Regular Contributor
timestamp: February 14, 2021, 02:26:44 am
content: At 100kHz, C2=100pF, things are getting problematic. U1a gets current limited, making the positive half triangle-shaped. The sampling pulse does not get high enough, limiting Vout to just above 4V.(I put meaningful names on the curves; Tina-TI sorts them alphabetically so i named Vout "Vvout" to make it appear lastScope display of the same:

author: richlooker
author_rank: Regular Contributor
timestamp: February 14, 2021, 11:14:15 am
content: Reducing R6 to 10k fixes that, and also fixes the voltage drop over T2. Now I wonder if R5 and D3 fill any purpose at all; will try without them.I am a little worried about the 75mA T2 Ig spikes, whether this may damage the JFET./Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 14, 2021, 12:11:53 pm
content: Using an LM6171B as input amp fixed the current limiting. Happy with the design for now; time to breadboard and do real tests.

author: richlooker
author_rank: Regular Contributor
timestamp: February 14, 2021, 10:38:09 pm
content: I had to do a couple final simulations before building the circuit.First, verifying that it performs well at lower frequencies. In all instances Vout settles at the first peak, and peak voltage tracking is spot on. Iout U1a shows a ~60µA spike at the input signal zero crossing, indicating that T1 shorts C1 while D1 is still conducting. I'll pull the + input of comparator U2 one schottky drop below ground to avoid that.100Hz, C2=10nF:100Hz, C2=100nF:10Hz, C2=100nF:/Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 14, 2021, 10:54:47 pm
content: Finally a closer look at the currents flowing through T2.This simulation is at 10kHz with C2=1nF. The three upper waveforms are currents where the positive direction is inwards to the JFET, and the fourth one is the sum of these. Interesting that the sum stays within +5/-4 pA, indicating that any charges are the same after the Ig peak as before it. It also seems Idrain i current-limited by U1b. Would be interesting to see what happens if I replace U1b as well with an LM6172; maybe Idrain - and thereby also the little Vout drop - will be reduced. I won't find out before I receive my order of LM6171/6172 from mouser, as Tina-TI reports a convergence problem with LM6171/6172 instead of TL072./Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 14, 2021, 11:28:33 pm
content: Modified sample&hold peak detector breadboarded, ready for testing. For now it's using TL072 until I get my LM6172s, meaning it's not very usable beyond 20-30kHz.

author: richlooker
author_rank: Regular Contributor
timestamp: February 14, 2021, 11:47:50 pm
content: I got the simulation / transient analysis working with LM6172 for both U1a and U1b. TL072 output impedance was clearly a limiting factor. Now it's wickedly fast - this is at 100kHz; peak voltage tracked (minus 300mV schottky drop) after first peakQuote from: Benta on February 09, 2021, 06:01:41 pm- this really did the trick (in simulation, at least) and they're not crazy expensive either; thanks againAnd here is the final schematic:Testing and scoping tomorrow./Richard

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 15, 2021, 12:09:47 am
content: Nice!I wonder if it would be worthwhile, to add another op-amp to assist the schottky? It's clearly the weak link, as a tempco offset.I think the approach would be... wire U1a as a precision rectifier, but not actually because its buffered (well, amplified too) signal is needed elsewhere -- so it would add another op-amp. Also, it needs to be rather fast slewing (even with the diode-from-output-to-input clamping trick).It would be nice to not discharge C1 all the way as well, both giving U1a (or the precision recitifier) an easier time and reducing required voltage changes; I'm not sure exactly how to do that here. It would be nice if the peak can be sensed by comparator, without having to differentiate it (which would likely add yet another wafer to the switch).I mean, you're already differentiating it, that's effectively what U3 is doing -- which means that might be a good section to investigate further. Specifically, D1 leakage is the limiting factor, and C1 reactance rises at low frequencies so noise goes up as well, which introduces phase noise which I guess puts a bit of variance on the output (earlier/later sampling results in an incrementally lower voltage, either during the rising edge before C1's voltage has reached peak, or the falling edge as C1 discharges into leakages?).I suppose that's another nice thing about quadrature, you have zero and peak crossings available implicitly. Wonder if any node, or branch , in the Wien bridge does? I'd have to think about it..Tim

author: richlooker
author_rank: Regular Contributor
timestamp: February 16, 2021, 12:04:28 am
content: Thanks for the suggestion, TimQuote from: T3sl4co1l on February 15, 2021, 12:09:47 am- I have pondered over this. And simulated it. It resulted in a hell of a lot of osillation, since the peak tracking voltage - as the input signal rises from zero towards peak - is almost the exact same voltage as the input signal, and the comparator that is supposed to detect that the input signal has passed the peak and is falling, now goes crazy. It can probably be solved, but I think the circuit is already somewhat overkill for the purpose, so I'll leave it at that.Quote from: T3sl4co1l on February 15, 2021, 12:09:47 amI may experiment with these suggestions at a later time, but right now the precision I could gain is not needed. But whenever I need a precision peak detector, I know where to start tweaking/Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 16, 2021, 07:40:13 am
content: Device under test.It draws something like 20mA from both positive and negative supplies (I <= 15mA < 25mA).First test, with a 10kHz signal. 3Vpp signal (amplified from 1Vpp by U1a) and output:6Vpp signal and output. What you don't see here is that the output changes instantly and with no wobble whatsoever.Sampling pulse with C2=1nF: (wish I had more than two scope channels, so I could see more things at once)And with C2=100pF:

author: richlooker
author_rank: Regular Contributor
timestamp: February 16, 2021, 07:48:59 am
content: 10kHz - 100kHz doesn't work very well, and it won't until I get the faster opamps. The lower end of the frequency range did not work at all with the original design. Here is what it looks like now.10Hz signal, 6Vpp, C2=100nF, this is what the peak tracking wavwform looks like:The sampling pulse:Input signal and sampling pulse:Output at 6Vpp:And at 3Vpp:Again, output level change is instant - stable at first peak - and frequency change does not affect output level.

author: Vovk_Z
author_rank: Super Contributor
timestamp: February 16, 2021, 09:01:50 am
content: Quote from: richlooker on February 16, 2021, 07:48:59 am- it's cool for Wein Bridge type oscillaltor.

author: richlooker
author_rank: Regular Contributor
timestamp: February 16, 2021, 09:03:17 am
content: The goal was to to design a peak detector where;Output level is constant/stable over the frequency range 10Hz - 100kHz (this is required in order to have constant amplitude from the oscillator over the frequency range)Output level is unaffected by frequency change - no peaks, troughs or wobblingOutput level changes linearly with input level, over 1V-6V peak-to-peakInput level changes are instantly reflected and immediatly stable on outputSo far it looks like all these goals are achieved, even though the frequency range 10kHz-100kHz is not yet tested.I'll put this - the source for feedback signal to the AGC circuit - to rest for now and concentrate on the oscillator circuit itself.As I wrote in the first post, I was considering either an amplifier design based on discrete BJTs or using high-speed opamps. I bought a couple of LT1253 - a "low cost dual current feedback amplifier for video applications" with 90MHz GBW and 250V/µs output slew rate, according to the datasheet - but this turned out to not be a good choice; the LT1253 is not unity-gain stable and the noise and harmonic distortion figures are not exactly great. LM6171/6172 should be much better suited, so I'll try a couple of different configurations with those once I get my hands on them. Until then, I will give the discrete circuit another go; I think it should be possible to configure a JFET-based AGC operating at a low enough Rds range to be usable as a substitute for a filament lamp based stabilization circuit./Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 16, 2021, 09:20:21 am
content: As this is a practical project, with an assembled and working sine generator as the final, desired result, my posts will be a mix of theory, simulations, practical testing and physical build considerations - one of these being how to switch all the things that need to be switched. The need for poles/decks in the frequency range/decade switch has exceeded what I have available, I have ordered two (I always buy twice what I need for a project, thereby building a component stock :-)) of these 4-pos/3-deck/6-pole switches:Five of the poles are already occopied:Two for switching the timing capacitorsTwo for switching "phase compensating" resistors per decade - these will ensure that the upper frequency of each decade is exactly 100Hz/1kHz/10kHz/100kHz, then a common 26-step resistor ladder operated by a 2-pole/26-pos switch (photo below) will select the lower frequencies in steps with good enough accuracyOne for switching the sampling pulse timing capacitor of the peak detector circuitI'll probably figure out an application for the remaining pole along the way./Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 22, 2021, 07:11:08 pm
content: As I wrote initially, I was hoping to learn something from this. And I have learned a lot. About JFET characteristics and how JFETS behave in real life. I have learned to use a simulation tool - I chose Tina-TI over LTSpice, because I use lots of TI opamps - out of necessity, so I can test different devices without having to buy them first. I bought a handful of LT1253 opamps, as I believed this was an affordable way to get the bandwidth I need. Then I realized that there is more to an opamp than FET or BJT input, GBW and slew rate. I learned that there is such a thing as a current feedback opamp, and that LT1253 is such an opamp. By properly dimensioning the nfb resistor network I managed to make a somewhat stable oscillator from it, but at a gain of just 3 it's bordering on instability, and it really, really wants to self-oscillate at around 12MHz.Today I received what I thought would solve all my problems - a handful of LM6171 and LM6172 opamps. Unity gain stable, 100MHz unity-gain bandwidth, 3000V/μs slew rate and 50mA of output current, sounds really good, and looked very good in the simulations. I am sure these will be golden in the oscillator, but in the S&H peak detector I ran into problems. Using 1/2 LM6172 to buffer the input voltage peak hold capacitor worked great, except not at low frequencies. Turns out it has an input bias current of 1.2µA (typical) up to 4µA (max), and at below 100Hz this current charges the 10nF faster than the input voltage rises, both confusing the peak detection and producing a ramp that hits the max output voltage at 6Hz. At 10Hz, with a 4VPP input, this is what it looks like. The red curve is supposed to be a schottky drop below the input voltage, and to stay flat from the input peaks until it crosses zero. There must be something wrong with my LM6172 SPICE model, as this worked 100% as it should during simulation.The comparator thinks the input signal has passed the peak but in reality it's the capacitor voltage ramp that has risen above the input:As the S&H tries to sample a rising voltage instead of a constant one, an anomaly is generated on the output voltage (which is supposed to represent the peak of the input)Solution? I have to insert another JFET input opamp between the peak hold capacitor and the LM6172 input - this should be just fine, as the latter was chosen for it's ability to dump current to the S&H capacitor. New diagram and simulation coming up./Richard

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 22, 2021, 08:28:42 pm
content: Could also add a JFET source follower, if you don't mind the potential drift and offset (10s mV?) -- typical strategy is to use a matching JFET as current-regulating diode, thus holding the follower at Vgs=0 and tracking alright with temperature.Alternately, use a unity-gain buffer instead of another opamp; there aren't as many of these to choose from though, I think? So probably a bit on the expensive side. Dunno, I forget which ones are common.Tim

author: richlooker
author_rank: Regular Contributor
timestamp: February 23, 2021, 12:43:33 am
content: Quote from: T3sl4co1l on February 22, 2021, 08:28:42 pmCan you show me schematics for this circuit element?Quote from: T3sl4co1l on February 22, 2021, 08:28:42 pmThanks for the suggestions. I can only find one such device - AD8244 quad unity-gain buffer - which costs a fortune. But I have a simpler solution; as I am using a single opamp (TL081), I'll swap that out for a dual (TL072).Here is the modified peak detector circuit. Added U2a to buffer the C1 voltage; JFET input means bias current in the picoamps range, so should not cause any trouble. I also modified the differentiator circuit; decreased R3 from 10K to 2K, shortening the rise time of U4 output to make it close to a pulse wave, and added D3 to short R4 when U4 output goes high; without this, the negative input of U4 will rise to over 20V as C2 is reversed, and will take several µS to settle at Vcc+.Simulation at 100kHz, now the sampling/gating pulse is much better defined than before the R3/D3 modifications, making me think this may actually work for 200kHz and beyond. Maybe I should reframe the project to 20Hz-200kHz instead/Richard

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 23, 2021, 05:06:52 am
content: Like this:https://www.planetanalog.com/wp-content/uploads/media-1304480-Image1.pngOh, there's also a configuration with two opamps cascaded, which increases phase flatness, and might be relevant here (not that phase flatness specifically would be useful, but some combination of that and frequency response would), something to try; or if nothing else you can put U1b in U2a's loop to cancel its offset. Any time you're putting amps in loops, you need to mind compensation, of course!Tim

author: richlooker
author_rank: Regular Contributor
timestamp: February 23, 2021, 05:28:25 pm
content: Looking at the nice 1µs sampling pulses, and how the hold capacitor gets charged to 95% of the peak value at the first sample, I'm wondering, why can't I make this same pulse width work for lower frequencies?In the original design, the timing capacitor is 1nF, and this worked well for 100Hz-10kHz. Above 20kHz, it failed to produce a sampling pulse, because the capacitor, when the first comparator output went high, pushed the input of the second comparator to well beyond 20V, and it failed to discharge below 0V again in time to trigger a pulse. My diode trick with D3 solved this. 1nF produces a pulse of approx 10µS, which is obviously too wide for 100kHz operation, so 100pF was needed for the upper frequency decade. But the hold capacitor did not reack the full voltage from the peak hold capacitor during the sampling window of 1µs, so several pulses were required for the output to settle. No problem at high frequencies, but this would also mean that the settling time increases with lower frequencies. Hence the rationale for timing capacitor value anti-proportional to the frequency decade.Once I realized that the charging of both capacitors was current-limited by the opamps, and found a faster, higher-current opamp (LM6171/6172), the hold capacitor consistently charges from zero to 99% of the peak value during one sampling pulse, regardless of input frequency. Now, what's the use of wider sampling pulses at lower frequencies? 100pF timing capacitor / 1µs pulse worked fine down to a couple hundred hertz, then problems arose. After some investigation I found the cause: For the lower frequencies, the input signal rises relatively slow, and as it passes zero - and the voltage at the peak hold capacitor C1 - the comparator U4 is tricked (probably noise contributes to this); the output goes high, then the positive input momentarily appears lower than the negative one, so the output goes low, triggering a sampling pulse, before it goes high again, allowing C1 to charge. In effect, it triggers sampling when the input is a zero. In the original circuit, there was hysteresis added to this comparator, in the form of positive feedback. Removing this was the first modification I made, as I thought it would delay sampling slightly, thereby increasing the voltage drop of the output with respect to the input, due to the LED in antiparallel with D1 that let C1 follow - but lag - the input signal during the entire cycle. Now, with that diode/LED arrangement gone, The hysteresis can safely be added again. Values of R6 and R7 adjusted to accommodate for the smaller pull-up resistor at the collector output of U4.Now the sample&hold peak detector works 100% flawlessly, across the entire intended frequency range, the output immediately reflecting the input peak, with a fixed sampling pulse width of 1µs. Done, now it's oscillator time/Richard

author: richlooker
author_rank: Regular Contributor
timestamp: February 27, 2021, 11:20:39 pm
content: I have spent several hours fiddling around with two different oscillator configurations; variations of single opamp with FET AGC plus dual inverting opamp with optocoupler AGC. The latter is actually less challenging to get oscillating across 10Hz-100kHz, but the gain seems very frequency-dependent, and I have been unable to achieve anything resembling constant amplitude over the frequency range. The FET stabilized circuit seems a lot less frequency-dependent with respect to amplitude, but I have yet to find a resistor combination that will let it start oscillation across the entire frequency range. I also discovered that the instant response of the sample&hold peak detector may lead to problems; I sometimes had the oscillator enter a state where a peak resulted in increased feedback, which made the next peak attenuated, and the immediate feedback made the next peak higher etc. - in other words, the amplitude alternated between two values for every other period. Seems I may have to include an extra time constant in the feedback.I decided to stop wating hours trying and failing, and try a systematic approach instead. I realized that none of the articles I have found on the internet mention much about variance in JFET characteristics and how to compensate for these. Each and every one of the proposed circuits may oscillate - and without saturation - for one instance of a specific JFET, and not for another one. Rds(on), transconductance and Vgs(off) in general are specified only as typical and maximum values, with very high variance. A practical circuit that depends on these parameters must be tuned for a specific JFET.While I was measuring the characteristics of a BF245C, my oscilloscope died on me. No big deal, it's an old Picoscope 2204 USB scope, and I immediately ordered a new one (2204A), but while waiting for this to arrive I have to work with simulations.Tina-TI refused to simulate the sample&hold peak detector with the oscillator, so I put in a simple rectifier circuit for the purpose of simulation. The time constant of this will influence the values, but probably not the gain or the oscillation conditions.Before my oscilloscope gave up the ghost, I managed to measure the gain of the oscillator amp stage - with the positive feedback elements removed - every decade from 10Hz to 100kHz, and it stayed within 1% except for at 100kHz where it rose with 3%. Still I suspect that with the positive feedback/timing elements the gain will fall off significantly at the higher frequencies. I have been thinking of using an error amplifier with input from a reference peak voltage and the actual oscillator output, but I'm not sure how to do this.P1 and P2 will allow adjustment for Vgs where Rds starts to rise and Vgs(off), to achieve a certain amplitude (P1 lower setting = higher feedback gain = lower amplitude) but significant Rds(on) variance may require scaling of the negative feedback network of the opamp./Richard

author: Sengcid
author_rank: Regular Contributor
timestamp: March 03, 2021, 09:12:51 pm
content: Hi guys.For fast amplitude control I use a pair of zeners in the feedback loop (see attached). They clip fairly gently so that the distortion is quite low (OK for a test signal). For very low distortion add a variable resistance in parallel and adjust for borderline oscillation (when you need it). For ultralow distortion use two-stage high gain blocks. For 100kHz you will need some very fast op-amps and careful layout (proto-board not ideal). It seems that the only way around the relationship between frequency and settling time is direct digital synthesis (expensive). Herewith two circuit ideas you could try. For more detail on the theory see my collection of monographs (part 4 monographs 1 and 3).ChrisSorry chaps. I have had to remove the link to the cloud. If interested pls pm me.

author: richlooker
author_rank: Regular Contributor
timestamp: March 04, 2021, 06:12:05 pm
content: Got my new Picoscope, so here we goI guess I have hit the downside of ultrafast peak detection. The blue trace is tthe oscillator output, red is output from the peak detector:This behaviour is consistent, regardless of frequency. Only by adjusting down to peak below 1V can I get a stable signal. Tried all kinds of filtering/integration of the peak detector output, but it remains unstable when peak approaches 1V.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 04, 2021, 07:19:18 pm
content: Hah, is that a stable limit cycle with period 7? No, it's not quite back where it started, must be more than that...Welcome to the wonderful world of chaotic sequences.Presumably, it will help to reduce loop gain, and add a compensation term, so that the amount the amplitude is changed by, is relatively small from sample to sample, but has an overall integral term to give low asymptotic error.One thing you didn't measure, is response time versus amplitude, or also gain, I think? If these vary with amplitude, that's a perfect place for nonlinearity to arise, and hence chaos. In addition to the oscillator's transfer function, which probably isn't very orderly either (if its natural damping coefficient is very small, then the control varies between negative and positive integration).Tim

author: richlooker
author_rank: Regular Contributor
timestamp: March 05, 2021, 12:42:31 am
content: I found the trick was to reduce the gain range the VGC circuit controls, by making R5 as small as possible while also ensuring that oscillation occurs across the entire frequency range when the JFET is fully on (Rds = Rds(on)), and likewise that no oscillation occurs when it is off (Rds = Rds(off)). With the chosen values, gain will be between 2.95 (assuming Rds(on) = 100 ohms) and 3.1. I also found out that the adjustment of feedback gain was not very useful, and fixed gain around 4 gave the best results. Gain is tunde by varying the negative feedback offset with P1. I also found that C4 had to be larger to allow oscillation at the lower frequencies. Currently it shuts down around 30-40Hz, as the impedance of the capacitor becomes high enough to reduce gain below oscillation condition. I have ordered some 6800µF bipolar electrolytics, thinking maybe 13600µF will enable oscillation down to 10Hz, where the impedance will be 0.8 ohms.This worked nicely at all frequencies down to 50Hz; here is a trace at 100kHz (almost) where the red trace is the feedback DC offset.There is some noise present, and tendencies to spurious oscillations at 6-25MHz, but not bad for a breadboard circuit. Here with spectrum plot.And 100Hz with spectrum.

author: richlooker
author_rank: Regular Contributor
timestamp: March 05, 2021, 01:24:50 am
content: As long as I kept the timing components on the same breadboard and close to the oscillator opamp, everything behaved very nicely. When I switched to the arrangement here, to be able to switch frequencies by just moving jumper wires, things got more problematic - more noise and more prone to spurious oscillations, but still workable.When I added this rotary switch for fast frequency switching, the stray capacitances and inductances became too much, and I got severe spurious oscillations, affecting the operating points of the active components such that I could not get the desired oscillation at any frequency. A reflection; I have earlier stated that breadboarding should be unproblematic as long as you work with relatively low frequencies, eg. f <= 100kHz, but I did not consider that the circuits themselves would be induced to oscillate at much higher frequenciesIt's now clear to me that the rotary switch and the timing capacitors have to be on the oscillator PCB. I guess I'll have to get the circuit onto a PCB before I can decide on the final component values. Next step: PCB design

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 05, 2021, 03:02:12 am
content: Why C4 at all? It's ground referenced on both sides, and the JFET shouldn't be rectifying at signal levels (and if it is, reconsider how and where you're using it!).Which is one of the difficulties of using JFETs as variable resistors, they don't have a wide variable range. The useful range of Vds is the difference between Vgs and pinch-off; so as Vgs approaches pinch-off, it looks more and more like a symmetrical constant current source with a small resistive step near zero. Or something like that. So, high Vgs (near zero) is preferable, and Rds is best varied over a modest range like 1:3 or something like that.You'll have the same fundamental problem with the fixed time constants in the feedback path -- since your precision detector is discrete-time, so also should be the feedback network. Use switched-capacitor filters!Tim

author: richlooker
author_rank: Regular Contributor
timestamp: March 05, 2021, 07:39:01 am
content: Hi Tim, thanks for the negative feedbackQuote from: T3sl4co1l on March 05, 2021, 03:02:12 amI have used the configuration from this article:https://sound-au.com/articles/sinewave.htm#s44Just tried to simulate with and without C4, and there is no discernible difference. Re-reading said article, and scrutinizing the circuit, I can only assume that the cap is there to make it compatible with DC-biased feedback networks. Great tip, I will remove this. Maybe you need a couple of 6800µF bipolars?Quote from: T3sl4co1l on March 05, 2021, 03:02:12 amYou are right, but for this specific application, linearity is only required over a very limited range, or so I believe. It seems to do the job well anyway. What alternatives are there for variable resistors?Quote from: T3sl4co1l on March 05, 2021, 03:02:12 amNow there are no time constants in the feedback path except the ones arising from stray capacitances - or am I wrong?/Richard

author: salbayeng
author_rank: Frequent Contributor
timestamp: March 05, 2021, 08:15:12 am
content: Sorry for jumping in late.What did they do in the old days?, e.g. the HP200https://people.ohio.edu/postr/bapix/HP200CD.htmThis seems to have 3 capacitors, so guessing it was phase shift rather than Wein, AGC probably with light bulb.Distant memory from the late 70's is that we used lightbulbs for AGC and back to back zeners, normal operation being about a volt less than the zeners, zeners were only active when you changed ranges, back then 1% was low distortion, although you would generally do better with valves than transistors.The FET as a control element works but is a bit asymettric, maybe two FETs in series , or a RF type dual gate FET.

author: Kleinstein
author_rank: Super Contributor
timestamp: March 05, 2021, 11:01:35 am
content: With only a single frequency, the amplitude control part can work with a rather small range and the FET should work with no problem. One has to compromis on the voltage seen by the Jfet. With high votlage the FET gets nonlinear and this can get through to the output. With to little votlage the control range gets small and the osciallator must be trimmed quite well to be just at the right gain.With a variable frequency there is naturally more control range needed, as the the variabel capacitors / resistors may not be that accurate. So one may have to compromise here and look for good matching in the frequency setting.In addition the AGC control loop also changes gain with frequency. So one may have to also change C5/R6 depending on the frequency - with a low frequency the loop must be slow and with a high frequency the control must be faster to still get a stable amplitude.

author: richlooker
author_rank: Regular Contributor
timestamp: March 05, 2021, 12:03:40 pm
content: Quote from: salbayeng on March 05, 2021, 08:15:12 amThe problem with light bulbs and thermistors is that they have a time constant that will introduce nonlinearities at low frequencies. I aim for low distortion down to 10Hz, so these are out of the question. And I regard 1% as HIGH distortionWhen it comes to zeners, I am skeptical as to whether they are "only active when you change ranges" - without active and continuous feedback, I don't see how you can keep gain at the correct level across different frequencies.Quote from: salbayeng on March 05, 2021, 08:15:12 amQuote from: Kleinstein on March 05, 2021, 11:01:35 amI have made the voltage seen by the JFET as low as possible, while still having enough control range. The control range requirements are reduced through the use of high-speed opamps and switched 1% capacitors and resistors - no variable resistors here. The effect of JFET channel width modulation from the AC is minimised by ensuring that gate sees exactly 1/2 of the AC voltage applied to drain.Quote from: Kleinstein on March 05, 2021, 11:01:35 amThe AGC control loop with the sample&hold peak detector does not change with frequency. The integrating element in the diagram - C5/R6 - is there to enable simulation of the circuit; Tina-TI chokes on the complete oscillator with S&H peak detector.

author: richlooker
author_rank: Regular Contributor
timestamp: March 05, 2021, 12:52:42 pm
content: A little simulation at 100kHz, just to illustrate the operating conditions for the JFET and my hypothesis that it introduces extremely little distortion.Here are all the voltages, overlaid, with a calculated trace Vdist = (Vd/2 - Vg + Vfb/2) - this will be zero as long as AC at gate is exactly half the AC at drain, in practice it's in the ~1mV range.Vout, Vd and Vg on separate scales - peak-to-peak 9.47V, 206.5mV and 104.9mV, repsectively.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 05, 2021, 03:29:00 pm
content: Quote from: richlooker on March 05, 2021, 07:39:01 amWell, like I said, they're fine over a modest range, just a matter of biasing them there. Which is just choice of R4/R5. Hm, probably worth making one of those a trimmer, with calibration being, getting Vg near, but just below, 0V for all ranges.Like, the simulated Vg ~ -0.7V should be fine, I expect Vpo isn't exactly -0.8V so the 0.1V drain swing is a small fraction of available range, and linearity will be good. (Easy enough to confirm in the simulation, just plot i_d.)If you can't avoid that on all ranges, then you aren't getting the full value of the intended variable resistance. A nonlinear resistance might as well be a pair of diodes/zeners on R3.QuoteI mean C5-R6, granted that's just for sim, but also to add a cap in series with R8 to get asymptotic settling.If you're okay with the fixed gain solution, that's fine, but it won't be as stable.Hmm, what kind of amplitude stability would be desirable anyway, say if Vg varies from -3..0V, then an error amp gain of 10 gives an input span of 0.3V, which is, well, 10% stability out of a 3V peak amplitude for example. Maybe that would be good enough?Tim

author: richlooker
author_rank: Regular Contributor
timestamp: March 18, 2021, 08:33:04 am
content: AFter endless experimentation, I have found that it's really difficult to find an operating point for the JFET where I get oscillation (and not saturation) across the entire frequency range. Then I thought, you know what, this is supposed to be an experimental device anyway, so why not make the relevant controls available on the front panel?This is my current concept for the front panel; the actual knobs laid out on a printout. I have not figured out how I can get the text/markings printed on the front plate. Any tips?

author: richlooker
author_rank: Regular Contributor
timestamp: April 04, 2021, 12:19:20 am
content: I found a reference to schaeffer-ag.de in an older thread, downloaded Front Panel Designer and found this can clearly do the job. It's going to cost around €60 for the front panel, so I'll wait with that until I'm sure I have a working build.Things move slowly, lots of simultaneous projects, but I have finally gotten around to designing the oscillator PCB. I didn't have the patience to figure out KiCad or Eagle PCB, so I made it in PowerPoint - my go-to universal drawing toolI am not going to make the peak detector PCB in PowerPoint, though, so I'll just have to take the plunge and learn a proper PCB design tool. KiCad, Eagle, or something else - any suggestions?I used a three-deck rotary switch for the frequency multiplier switch, and removed one deck to make space for some PCB in front of the upper deck.PCB, 101.25x57.5mm, component side, courtesy of Microsoft PowerPointSolder side.

author: RoGeorge
author_rank: Super Contributor
timestamp: April 04, 2021, 12:48:44 pm
content: Kicad.

author: richlooker
author_rank: Regular Contributor
timestamp: April 08, 2021, 09:29:58 am
content: This is a tedious process;Print solder side image 1:1 on paperTape paper template to PCBPuncture every solder pad with awlRemove paper template and draw traces by hand (the PCB marker pen is a b**ch to work with, it leaks drops which need to be cleaned up)EtchDrill holesI use ammonium persulphate; less messy then ferric chloride.In process...And the result, not beautiful but usable.

author: richlooker
author_rank: Regular Contributor
timestamp: April 08, 2021, 09:47:44 am
content: It's taking shape.

author: richlooker
author_rank: Regular Contributor
timestamp: April 08, 2021, 11:11:06 am
content: Oscillator board done. Now I need to crimp some connectors and wire up some stuff to test it.Or semi-done. There will be 2x2x4 resistors in front of the rotary switch, selected to get as close to 100Hz/1kHz/10kHz/100kHz as possible for each switch position. The exact values cannot easily be calculated - that would have to account for all parasitic/stray capacitances and inductances in the circuit - so I will have to rely on successive approximation. The theoretical value, disregarding parasitics, is 1591 ohms, and the per-range resistor pairs are in series with the 1500 ohms resistors just behind the switch.

author: richlooker
author_rank: Regular Contributor
timestamp: April 12, 2021, 03:10:18 pm
content: Wired, powered and ready for testing.Quite happy with the first frequency reading - bullseye98 resistors for 26 discrete frequency steps per decade.

author: richlooker
author_rank: Regular Contributor
timestamp: April 15, 2021, 11:08:19 am
content: One evening's work, one out of two rotary switch decks done. Tedious work, but rather satisfying to see the result and verify that it measures as designedHoping to have the complete setup ready for testing this evening.

author: richlooker
author_rank: Regular Contributor
timestamp: April 19, 2021, 09:24:20 am
content: It's nearing completion. But I'm not really satisfied with THD - 2nd harmonic is approx -54dB and 3rd harmonic ~-60dB, I was hoping for a cleaner sine. With the topology set, is there anything I can do to improve upon this?(the results are similar over the entire frequency range)

author: RoGeorge
author_rank: Super Contributor
timestamp: April 19, 2021, 10:42:41 am
content: Quote from: richlooker on April 19, 2021, 09:24:20 amCould the distortions be from the sound card? My guess is the soundcard can not cope with 1V amplitude.Is the ratio of harmonics preserved if you put an attenuator (say a 1/10 resistor divider) at the input of the measuring soundcard?Another question is the -83dB components at the left and right of the 1kHz fundamental. That looks like an amplitude modulation. How far are the two spikes from the fundamental?

author: richlooker
author_rank: Regular Contributor
timestamp: April 19, 2021, 01:17:58 pm
content: Quote from: RoGeorge on April 19, 2021, 10:42:41 amGood point; will redo the test at -6dB - 0.3875V RMS / 0.548V PPQuote from: RoGeorge on April 19, 2021, 10:42:41 amThese are both exactly 50Hz from the fundamental, probably power supply ripple modulating amplification (non-infinite PSRR).

author: RoGeorge
author_rank: Super Contributor
timestamp: April 19, 2021, 01:46:45 pm
content: A -6dB is a good start, I'll try at -20dB, too.Maybe the 50Hz AM will vanish after putting the audio side in a shielded enclosure. If you have a mains transformer keep it in a separated enclosure far away audio part. Ideally will be to power the generator from a battery.Otherwise a toroidal transformer (preferably covered in a permaloy magnetic shield) might be very expensive and still have a measurable influence through its magnetic field leaks. While electric field is relatively easy to make, magnetic shielding is much, much harder.E+I core transformers ("square core") will be a no go, even when shielded in permaloy they still have terrible magnetic field leaks.

author: richlooker
author_rank: Regular Contributor
timestamp: April 19, 2021, 08:39:02 pm
content: You were right about the audio interface not coping well with 0dB; reducing the level to -6dB reduced the 2nd harmonic a fair amount, while the 3rd harmonic stays put. Further reducing the level to -20dB changes nothing.The two peaks between 7 and 9 kHz, plus the two smaller ones between 10 and 20 kHz, must be some nyquist/aliasing phenomenon; they are not harmonics of the fundamental, and they move about independently in a seemingly random manner as I change the signal frequency. Seems like I need a better audio interface

author: RoGeorge
author_rank: Super Contributor
timestamp: April 19, 2021, 09:14:46 pm
content: Quote from: richlooker on April 19, 2021, 08:39:02 pmChances are a brand name external soundcards (e.g. USB or Firewire) would do better, at least in terms of noise.Beware that some of the so called 24bits/192kHz cards can only play at that resolution/sample rate, so look for the recording specs, too, they might differ badly.LATER EDIT:A big part of the remaining 2nd and 3rd harmonic seen in the last charts could still be because of the soundcard.

author: richlooker
author_rank: Regular Contributor
timestamp: April 19, 2021, 10:00:50 pm
content: I have two USB audio interfaces; a Propellerhead Balance (2011), and a Native Instruments Audio Kontrol 1 (2007) - both give similar results, and I just found out that both of them - even though they are capable of 192, 96, 88.2 and 48kHz sampling rate - behave nicely only at 44.1 kHz; now everything above the 3rd harmonic has vanished.2nd and 3rd harmonic are the same for both audio interfaces, do not change with sampling frequency, are more or less equivalent at -6dB and -20dB, and more or less the same regardless of fundamental. THD measures 0.06-0.1% over the entire frequency range.I am extremely happy with the performance at low frequencies; eg. THD less than 0.09% at 11Hz - this is simply impossible to achieve with thermistors or filament bulbs, and also impossible without a fast and precise peak/RMS detector.

author: RoGeorge
author_rank: Super Contributor
timestamp: April 20, 2021, 12:59:21 am
content: Nice results!Have you tried making the FFT with other types of windowing, too?Hann is altering most of the samples, depending on the implementation it might add numerical artifacts.https://en.wikipedia.org/wiki/Hann_functionI don't have any experience about how much this will affect the final result, so this is just shooting in the dark, but I'll be tempted to record and manually cut the samples so the whole recording will fit an integer number of sinusoids (manually trim the recorded samples to start and end with a 0V sample on the raising slope), then apply a rectangular window. (some thumb rules about windowing at the end of this pdfhttps://download.ni.com/evaluation/pxi/Understanding%20FFTs%20and%20Windowing.pdf)Asking because I am intrigued how Jim Williams got in the end ~0.0003%. I wonder if it's the measuring method, FFT vs. analog Distortion Analyser (many distortion analyzers have a notch filter to get rid of the fundamental), or it's the op-amps, or the topology of the schematic described in "Max Wien, Mr. Hewlett, and a Rainy Sunday Afternoon"?It might be just a coincidence, butccktekmeasured about the same range of 0.0003% distortions with his generatorhttps://www.eevblog.com/forum/projects/low-distortion-audio-oscillator-stabilized-via-trigonometric-identity/, thought that's a different approach.

author: Messtechniker
author_rank: Frequent Contributor
timestamp: April 20, 2021, 06:17:44 am
content: Just to give you an idea what to expect from a good sound card.In this case a M-Audio Delta 192 PCI. Unfortunately long out of production.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 20, 2021, 08:07:17 am
content: To see how much if the THD is from the generator, one could add a low pass or notch filter between the generator and sound card. If low pass filtering does not reduce the harminics, chances are they come from the sound card.An alternative way would be a kind of classic THT analyser / notch to reduce the main signal and look at the residual with the sound card.The harmincs ratio looks similar at 11 Hz and 1 kHz, so it looks like it is not the limited OP GBW and thus gain at higher frequency.

author: richlooker
author_rank: Regular Contributor
timestamp: April 20, 2021, 08:57:15 am
content: Quote from: Messtechniker on April 20, 2021, 06:17:44 amHow could I forget; I have at hand a superb audio signal generator: Tektronix ASG-100!1kHz from Tek ASG, Propellerhead Balance, exact same parameters as you used, signal at -6dB because distortion increases with the Balance above that:

author: richlooker
author_rank: Regular Contributor
timestamp: April 20, 2021, 09:31:09 am
content: I get the lowest distortion from the Propellerhead audio interface at -12dB input; will see what I can get from the Native Instruments one later.This means the practical limit for THD measurement is probably around 0.01%

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 20, 2021, 11:20:19 am
content: Quote from: richlooker on April 19, 2021, 09:24:20 amI don't remember your circuit (and I'm not very good at circuit design), but I can tell that for Wien-Bridge topology a THD depends much on an amplitude control circuit setting. From my experience, it may vary by 20-60 dB with a relatively small AGC change.

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 20, 2021, 11:31:37 am
content: Quote from: richlooker on April 19, 2021, 10:00:50 pmYou need something with a 24 bit ASIO. Otherwise, you'll stack somewhere at no lower than 0.005 (+-) % THD.

author: RoGeorge
author_rank: Super Contributor
timestamp: April 20, 2021, 12:48:03 pm
content: I guess ASIO is not crucial here. ASIO is about low latency in drivers (musicians can easily detect a few ms of extra delay while mixing or playing live), thought most of the true 24 bits cards are made for pro users which also need low latency, hence they are often called 24bits ASIO cards.

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 20, 2021, 12:55:55 pm
content: It worked for me, and for others, so I think it'll work for all. ASIO is not only for low latency, but it is totally another audio path. For measuring purposes it gives much lower noise and THD for my card. It's like 16 bit vs 24 bit (Windows MME vs ASIO).

author: RoGeorge
author_rank: Super Contributor
timestamp: April 20, 2021, 01:15:40 pm
content: Quote from: Vovk_Z on April 20, 2021, 12:55:55 pmNot trying to argue, just to learn if this difference can be measured indeed (and not just an audition placebo effect).I always thought ASIO is about latency and Windows drivers only, so at least in theory it shouldn't make any difference in noise or THD. (unless the non ASIO Windows drivers are in fact 16 bits only, and can not take advantage of the full range of a 24bits ADC).Do you have any link, or measurement charts of ASIO vs non ASIO noise/THD, please?

author: richlooker
author_rank: Regular Contributor
timestamp: April 20, 2021, 02:44:17 pm
content: I think the case is that a WDM driver _may_ resample the signal, but not necessarily so. I tested Audio Kontrol 1 with ASIO driver, a measurable but minimal difference. No difference between bespoke ASIO driver and ASIO4All. Balance ASIO driver won't work with Audiotester, but AAIO4All works. Again, a minimal difference. WDM gave THD 0.0016-0.0019%, ASIO gave 0.0014-0.0017%.

author: richlooker
author_rank: Regular Contributor
timestamp: April 20, 2021, 02:59:18 pm
content: Quote from: Vovk_Z on April 20, 2021, 11:20:19 amTo my knowledge, the trick is to minimize the influence of the JFET, to minimize Vds, and to strive to reduce channel modulation by feeding half of the AC at drain back to gate.The latter is accomplished by the voltage divider R9/R10 (R10 is connected to U2 output, which has a stable DC, so in signal terms it equals ground.)I will try to replace R3 & R4 with 33k and 16k, respectively, which should reduce Vds by a factor 3, and also restrict the possible operating range of the JFET. Hopefully it will not be too restricted to allow oscillation across the entire frequency range.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 20, 2021, 03:50:40 pm
content: Quote from: RoGeorge on April 20, 2021, 01:15:40 pmASIO gets your the most direct access possible to the supported sound card. MME, definitely not. It goes through the whole Windows audio subsystem including mixers allowing shared use of the sound card. ASIO has exclusive access. And yes, for a long time, you could only get 16-bit samples through MME. We're talking over 20 years ago. Also, ASIO was the only way of getting access to more than 2 channels.Things have evolved on Windows. I think starting with Windows 2000 (or NT?), the only way to get equivalent "direct" access to the sound card was to use Kernel Streaming. It wasn't that well documented though, but it worked.These days, the best option on Windows, apart from ASIO, is to use WASAPI. It gives you the same level of performance and can get you exclusive access as well.Whatever solution you choose, if it can't guarantee exclusive access to the sound card, then you can't fully control what it is that is going in and out. MME, even with recent Windows versions, can't ensure exclusive access AFAIK, so it's best avoided. It can allow > 16-bit samples though, through "extended formats".If your sound card doesn't have ASIO drivers, definitely use WASAPI. Most of the recent audio software supports it.

author: richlooker
author_rank: Regular Contributor
timestamp: April 20, 2021, 05:01:57 pm
content: Quote from: SiliconWizard on April 20, 2021, 03:50:40 pmQuote from: RoGeorge on April 20, 2021, 01:15:40 pmQuote from: Vovk_Z on April 20, 2021, 12:55:55 pmOK, I have established that it makes a really, really minute difference in my case. Enough ASIO for now

author: Kleinstein
author_rank: Super Contributor
timestamp: April 20, 2021, 05:48:36 pm
content: I don't think using much larger resistors in the feedback is a good idea. The LM6172 is not made for a high impedance input and may show nonlinearity and definitely more noise.One may be able to add some more trimming to R4, so that the FET would operate in a better range. A smaller or trimmed R5 may also be an option.One could consider adding some one sided loading to the OP, to make the output stage run in class A mode. This may reduce the distortion of the OP.some resistor directly at the output of the osciallor may also be a good idea, to reduce the effect of capacitive loading.

author: richlooker
author_rank: Regular Contributor
timestamp: April 20, 2021, 06:26:04 pm
content: Quote from: Kleinstein on April 20, 2021, 05:48:36 pmI really doubt the opamp is a factor yet. I also don't consider 33K/16K to be "high impedance"; I'll try and see what happens.Simple things first; I adjusted P2 to trim the oscillator RMS out down from 3.1V to 0.775V; this is the result. Definitely a big improvement; THD below 0.02% and the 2nd harmonic is now 76-77dB below the fundamental.

author: RoGeorge
author_rank: Super Contributor
timestamp: April 20, 2021, 07:57:31 pm
content: A side note, add a capacitor between the cursor of the voltage reference and the ground. As it is now, the impedance of that node is in the range of 10k, so very susceptible to noise and hum.Add e few tens of uF parallel with yet another 0.1uF. This will lower the impedance of the voltage reference at lower frequency like the 50Hz hum, the higher RF or other noises in general.So far the FET nonlinearities seems to be the main contributor at the end distortions. Try to look again at the steps explained in the article of Jim Williams I linked in the first page or so, and apply those techniques to your schematic.Do not dismiss the content because of hand-drawing schematics in that pdf or because of the title, the dude is legend, one of the best analogue engineers ever.

author: richlooker
author_rank: Regular Contributor
timestamp: April 21, 2021, 06:59:41 am
content: Quote from: RoGeorge on April 20, 2021, 07:57:31 pmDo you mean decoupling capacitors between power pins at the opamp and ground? WHile not in the schematic, I have 100nF ceramics close to the IC, and I will add a couple 47µF as well.Quote from: RoGeorge on April 20, 2021, 07:57:31 pmI am not dismissing it, not at allBut I arrived at the current circuit through a stupid design mistake; I started out by considering ways to reduce distortion, but then I got sidetracked by the frustrations of having to deal with parasitic capacitances on the breadboard, and fast-tracked making a PCB. Now I have to make the best out of it. Replacing R3/R4 with 33k/16k did not work very well, the operating range of the JFET became too small, yielding an unstable circuit. I'll revert this, and try to replace R10 with a 91k resistor in series with a 20k trimpot.Once I have everything assembled, I can start working on an alternative circuit, maybe revisit the optocoupler feedback, and incorporate the servo from Williams' circuit to eliminate common mode swing.

author: richlooker
author_rank: Regular Contributor
timestamp: April 21, 2021, 12:51:12 pm
content: 95k-105k trimmer to replace R10.

author: RoGeorge
author_rank: Super Contributor
timestamp: April 21, 2021, 01:49:25 pm
content: Quote from: richlooker on April 21, 2021, 06:59:41 amI've seen on your breadboard (didn't had the time to look at the PCB version at all) there was no decoupling between the node named "Voffset" (the positive input of the U2 feedback amplifier) and GND.You want that voltage (Voffset) to be rock solid, or else any induced noise or hum will go to the FET's gate and modulate the amplitude of the oscillations.Adding extra 47uF over the already existing 0.1uF near each IC couldn't hurt either, not sure if this will make a measurable difference or not (unless there are ground loops in the PCB, I hope there aren't any).

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 21, 2021, 08:24:49 pm
content: Quote from: RoGeorge link=topic=269822.msg3553164#msg3553164It is easy to measure. I'll take the screen a bit later.My PC with a good sound card is remote now, so I can take only a noise measurement at the moment.Possibly it is only for my sound card, but it is seen on the screen that WDM drivers stack somewhere at 16-bit depth. And there is no input signal. With a signal applied the screen becomes noisier and the THD becomes worse.Sory for off-topic.

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 21, 2021, 08:29:48 pm
content: Quote from: richlooker on April 20, 2021, 02:44:17 pm0.016% is quite a 'large' THD value. I'm talking about smaller values.

author: richlooker
author_rank: Regular Contributor
timestamp: April 21, 2021, 09:43:00 pm
content: I'm getting somewhere. Oscillator RMS 0.775V, 0.0125% THD; 2nd and 3rd harmonics are both 82dB below the fundamental. But I made the asjustment margin on R10 too small; THD went down as I reduced the value of R10 until the minimum value of 95k. I'll have to make it adjustable further down, eg. to 75k, and see where that leads.The 50Hz peak at -90dB plus the fundamental +/- 50Hz sidebands drop if I shield the PCB with my hands, so I expect these to be significantly reduced when I put it in a metal enclosure.

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 21, 2021, 09:48:22 pm
content: Quote from: Kleinstein on April 20, 2021, 05:48:36 pmThe distortion of LM6172 with a reasonable load (>100R) is much lower than 0.010 % (it is rather somewhere <=0.001%), so there is no need for a one-sided loading.

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 21, 2021, 09:53:07 pm
content: Quote from: richlooker on April 21, 2021, 09:43:00 pmYou may play with R9, R10 in a large range, I mean you may try R9 = R10 =10k, or even 1k both.

author: richlooker
author_rank: Regular Contributor
timestamp: April 21, 2021, 10:42:40 pm
content: Quote from: Vovk_Z on April 21, 2021, 09:53:07 pmIs there theory behind this, or just "play with"?With R5 at 560 ohms, gain will exceed 3 and the oscillator will saturate when Rds and (R9 + R10) in parallel gets smaller than 1.4k. Plus, smaller R9 and R10 will attenuate the feedback signal from the TL081, further pushing the system towards saturation.R4, R5 and R9 are carefully selected to minimize Vds while allowing enough (very small) gain control range. The only function of R10 is to feed back (ideally 1/2 of) Vd to gate, to eliminate the effect of channel modulation.

author: richlooker
author_rank: Regular Contributor
timestamp: April 21, 2021, 10:49:41 pm
content: Quote from: RoGeorge on April 21, 2021, 01:49:25 pmThanks, a very good point, especially since the potmeter will be connected here via 12" unshielded leads. Ill add a couple of caps

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 21, 2021, 11:29:08 pm
content: Quote from: richlooker on April 21, 2021, 10:42:40 pmPossibly there is a theory, but I don't have it. :-) In this case, it's just an experience.

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 21, 2021, 11:32:06 pm
content: Quote from: richlooker on April 21, 2021, 10:42:40 pmOf cause, there can be a need to decrease R5 too (or R3-R5).

author: richlooker
author_rank: Regular Contributor
timestamp: April 24, 2021, 05:03:32 pm
content: With tweaking of resistors, and keeping oscillator output at 1V RMS, I managed to get THD down to 0.01%. But it should be possible to get much lower.Jim Williams wrote:From that I assume that this should be achievable on a solderless breadboard. As I had already built the oscillator from this article:https://sound-au.com/project174.htm- I shortened all leads, fitted it with ceramic 100nF power bypass caps, and tested. Disappointing; 0.1% THD, way worse results than with my finished PCB.I assume that harmonic distortion is mainly caused by semiconductors and other, nonlinear components. The parasitic resistances and capacitances on a breadboard may add (non-harmonic) noise, affect amplifier bandwidth and cause spurious oscillations, but not increase THD, right?When it comes to the nonlinearities of a JFET, and in particular the channel-length modulation, I have only read that Vds should be kept as low as possible, but nothing about currents and/or whether some JFETs are better than others. Would I eg. gain anything by replacing the BF245C with a (genuine) 2SK170BL?Next up is breadboarding of Jim Williams' final circuit:I don't have a VTL5C10, only a DIY optocoupler, and I don't have the opamps he used, but I hope LM4671/4672 works all over.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 24, 2021, 07:24:13 pm
content: For the JFET choice it should help to have a symmetric fet - most if the JFETs are, but a few (espeically RF types) are not fully symmetric.I would look for some with a relatively long channel, so more like types with with that much transconductance relative to the capacitance and probably more like high voltage types and not specially low noise low votlage ones (e.g. like SK3557)The right choice probably also depends on the resistance range needed. The BF245 is more for higher resistance, a J113 ( ~2N4393) would be more like lower resistance.The Fairchild AN6609 suggest process 50 / 51 / 55 for vairable resistance. The BF245 is process 50, J113 / 2N4393 would be typical porcess 51.A point is to keep the adjustment range from the fet small, which requites rather good matching of the capacitors / resistors to set the frequency. If needed one could do some coarse trim with mechanical switches / relays or similar.

author: richlooker
author_rank: Regular Contributor
timestamp: April 24, 2021, 07:33:23 pm
content: Quote from: Kleinstein on April 24, 2021, 07:24:13 pmThese are the ones I have at hand: 2N5458, BF256B, BF245C, 2SK170BL, 2SK81, J110

author: David Hess
author_rank: Super Contributor
timestamp: April 24, 2021, 07:36:50 pm
content: Quote from: richlooker on April 24, 2021, 05:03:32 pmEven when that was published, I could not get the VTL5C10.The LT1006 is precision single supply, effectively a precision 324/358. The LT1028 is fast precision low noise. The LT1022 is fast low input bias current but since it is inverting, its common mode rejection is not important; it is suppressing common mode operation of the LT1028. The LT1010 could be replaced by a diamond buffer.I never understood why the LT1022 was used instead of another LT1028, but it was the fastest JFET part LT made at the time. The newer and faster LT1122 should work as an improved replacement.Quote from: Kleinstein on April 24, 2021, 07:24:13 pmOr do what I suggested and add the common mode suppression from this circuit to the earlier circuit from Jim Williams which uses a JFET for gain control. When he was designing these, he tested a circuit which corrected for the channel modulation of the JFET getting the distortion down to 0.0018%, but did not include common mode suppression like with the photocell version which got down to 0.0015%, an apples to oranges comparison. The virtue of the optocoupler is that no adjustment is needed but it might not perform any better.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 24, 2021, 08:26:36 pm
content: The common mode suppresion works for the OP, but does not change much for the FET or optocoupler. In the simple circuit the JFET is relative to ground. In the 2 OP version the FETs is with one end at a virtual ground - so not much change.

author: David Hess
author_rank: Super Contributor
timestamp: April 24, 2021, 08:44:43 pm
content: It has been so long that I have looked at it, 20+ years, that I forgot that, and forgot that I had a plan to get around it by making the JFET gain control floating. But you are correct, that is obviously why Jim Williams did it that way.Incidentally, I was looking at the LT1122 datasheet and they do recommend it as an improved replacement for the LT1022 in this application.And I am sure someone else mentioned it but I will again, figures 47 and 48 are swapped in the application note.

author: richlooker
author_rank: Regular Contributor
timestamp: April 24, 2021, 10:22:02 pm
content: Quote from: Kleinstein on April 24, 2021, 07:24:13 pmI will try with J110, which according to the datasheet is drain/source symmetrical (the BF245 is apparently not)Quote from: Kleinstein on April 24, 2021, 07:24:13 pmI ensure _very_ good matching of the timing capacitors/resistors; only 1% components, but I also measure a handful of each and select pairs which differ less than 0.5%. And I have chosen the neg feedback resistors to minimize the adjustment range for the JFET; if the JFET had Rds(on) = 0, the minimum gain would be 1 + 12k/5.6k = 3,143 - this should be high enough that even with reduced opamp open loop gain at 100kHz the gain should be above 3, enough to ensure oscillation. With the JFET fully off, the gain is 1 + 12k/(5.6k + 0.56k) = 2.948 - low enough to ensure no oscillation. 5.6k + 0.56k is chosen to keep the voltage over the JFET as low as possible; it should be about 1/30 of the opamp output swing.Quote from: Kleinstein on April 24, 2021, 07:24:13 pmI have not figured out how to make the JFET VGC floating, but I would be more than happy to achieve the 0.0018% THD Williams did with ground-referenced VGC.

author: richlooker
author_rank: Regular Contributor
timestamp: April 24, 2021, 10:36:20 pm
content: Quote from: David Hess on April 24, 2021, 07:36:50 pmQuote from: David Hess on April 24, 2021, 08:44:43 pmI have these opamps at my disposal: LM4671/LM4672, NE5532, TL072, LT1253, LM837

author: David Hess
author_rank: Super Contributor
timestamp: April 24, 2021, 11:04:42 pm
content: Quote from: richlooker on April 24, 2021, 10:22:02 pmIt comes down to doing exactly what you might suspect, bootstrapping the gate signal to follow the input. Examples are difficult to find on the internet because it is found in old circuits.A pair of operational transcendence amplifiers can also do it.Quote from: richlooker on April 24, 2021, 10:36:20 pmLT1028 - NE5532 or LM837LT1022 - TL072LT1006 - TL072 but with negative supplyLT1010 - Discrete diamond bufferYou can still buy CdS photocells so get one and make the linear optocoupler with some black heat shrink tubing and an LED or bulb.Or for the JFET version of Jim William's circuit:LT1115 - NE5532 or LM837LT1055 - TL072Now I have to wonder why he replaced the LT1115 with the LT1028. Were two different projects from different times combined into one application note?

author: richlooker
author_rank: Regular Contributor
timestamp: April 24, 2021, 11:07:04 pm
content: This is the circuit fromhttps://sound-au.com/project174.htmAnd this is the result:

author: richlooker
author_rank: Regular Contributor
timestamp: April 24, 2021, 11:16:07 pm
content: Quote from: David Hess on April 24, 2021, 11:04:42 pmI have made an optocoupler like this:https://sound-au.com/project200.htmAnd I made a typo - I meant LM6171/LM6172 (not LM4671/LM4672)Discrete diamond buffer? Won't an LM6171 do?

author: David Hess
author_rank: Super Contributor
timestamp: April 25, 2021, 12:23:08 am
content: Quote from: richlooker on April 24, 2021, 11:16:07 pmI do not think the LM6171 will work as well as the NE5532 or LM837 because of lower open loop gain and precision as a replacement for the LT1028 or LT1115, but try it.QuoteThe LM6171 might not need it because it has lower precision anyway but better operational amplifiers benefit from using an output buffer to prevent thermal feedback from their output stage to their input stage. The LM6171 might be suitable as a replacement for the LT1010 or diamond buffer though. It could also be used as part of a composite amplifier in a super gain block like the Linear Technology part-per-billion oscillator.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 25, 2021, 09:24:56 am
content: The LM6171 does not have the high DC loop gain of the NE5532, but it is quite a bit faster. At more than a few 100 Hz the actual loop gain is set by the GBW and no longer the DC gain.With the fast LM6171 using an extra buffer can be tricky with stability. So the high GBW also comes with a disadvantage.The extra buffer is to reduce thermal effects, but also to reduce distortion from loading the output stage (e.g. output stage cross over).

author: richlooker
author_rank: Regular Contributor
timestamp: April 25, 2021, 01:25:47 pm
content: OK, I'll settle with LM6171 for now, assuming that CMRR is not (yet) the main contributor to THD. As the LM6171 has a much lower output impedance / higher current drive capability than NE5532, I'm skipping the buffer for now. Thinking about it, I will use an LM6172, so I can swap it for an NE5532 and compare distortion figures directly. If the NE5532 chokes on the capacitive load, I will try buffering it's output with an LM6171.Upon closer look, I see that the LM6172 CMRR is no worse than NE5532 - typ. 105db / min 70dB vs. typ. 100dB / min 70dB. The most important criteria for my application is that gain should fall off as little as possible 10Hz -> 100kHz; in that department the LM6172 wins. But testing will showLinear Technology Application Note 43: Bridge Circuits, figure 45, seems to be a refinement of the circuit in the Jim Williams book; I'll start there:"Figure 46 shows results. Distortion (Trace B) drops to 0.0018% and is composed of 2f, some gain loop rectification artifacts and noise. For reference the circuit’s output (Trace A) and the LT1055 output (Trace C) are shown."With the S&H peak detector, I will have a ruler-flat trace C, so potentially the THD should be significantly lower.With respect to JFET selection, I consultedFairchild Application Note 6609: Selecting the Best JFET for Your Application:2N5458 is listed as a prime choice for voltage variable resistor, it's forward transfer admittance is in the same ballpark as 2N4338, it's listed as symmetric (drain and source interchangeable), the range for Vgs(off) is a bit wider but that should be OK. I'll use this one.With the negative feedback network resistor values as specified in figure 45, gain of 3 (assuming opamp open-loop gain = ∞) will be achieved when the parallel of 560Ω, 20k (assuming the 20k trimmer in middle position) and Rds equals 400Ω. This happens when Rds is ~1.5k, which should be a good operating point for 2N5458.I would like the oscillator to have an adjustable RMS from 0dB/0.775V (for lowest distortion) to +12dB/3.1V - I will replace the LT1004 reference with a variable reference based on TL431C (or a simple voltage divider potentiometer, assuming the voltage supply is sufficiently accurate and stable)

author: RoGeorge
author_rank: Super Contributor
timestamp: April 25, 2021, 03:18:42 pm
content: It has 18 ppm distortions instead of only 3 ppm.Why is that considered a refinement?

author: richlooker
author_rank: Regular Contributor
timestamp: April 25, 2021, 05:19:32 pm
content: Quote from: RoGeorge on April 25, 2021, 03:18:42 pmI want to see what I can achieve with a JFET, so I'm referring to this:Not this:

author: richlooker
author_rank: Regular Contributor
timestamp: April 25, 2021, 09:51:41 pm
content: Does not work. It saturates. The circuit is incapable of driving gate to a sufficient negative voltage:This is designed for 2N4338, which has a particularly high Vgs(off):2N5458 is not compatible here:

author: richlooker
author_rank: Regular Contributor
timestamp: April 26, 2021, 10:29:37 am
content: Snippet from the datasheet for the LT1055, used as integrator/servo in Jim Williams' circuit:Looking at this arrangement again, it's clear that it's severely limited in it's ability to drive the gate negative. With +/-15V supply, the LT1055 can (best case) swing to about -13.5V. Assuming the trimmer is in center position, the resistance between gate and ground is ~5k, which means -13.5V at A2 output gives -0.643V at gate. Maybe Williams just by chance used a 2N4338 with particularly low Vgs(off), towards the minimum specification, and did not deliberate around this, as he quickly moved on to the optocoupler.Now consider the arrangement described in this article:https://sound-au.com/articles/sinewave.htm"A FET used as a variable resistance, and these are convenient, cheap, and work well enough so long as the (AC) voltage across the FET is kept to a minimum. Providing an AC signal at the gate which is exactly half the voltage on the drain helps dramatically, and even harmonics (2nd, 4th, 6th, etc.) are effectively cancelled, leaving only the small odd harmonic residuals. C2 would normally be connected in series with R5, but that creates a second time constant.To prevent this JFET 'feedback' from creating two time constants, one based around each capacitor - C1 and C2 (the latter shown in grey), it's better to direct-couple the JFET gate to C1, and use C2 in the drain circuit as shown (in series with the feedback circuit).[C1 here is the integrating capacitor after a rectifying diode]C2 needs to be a relatively high value, such that there is little or no voltage across the cap at any frequency selected. This means it will be an electrolytic because a value of at least 220µF is needed, based on 'typical' feedback resistance values and a minimum frequency of 10Hz. Lower frequencies require a larger capacitor. Doing it the way shown does add a small perturbation as the JFET's gate voltage changes, but as there's only a few microamps available through R4 and R5 it has a minimal effect on the output.While there are countless JFET stabilised oscillator circuit to be found on the Net, almost none are wired properly. Many don't include the drain to gate feedback at all (so distortion will be unacceptably high), and a few get tantalising close, but get the feedback path wrong.Done properly, a JFET can provide distortion performance that is as good or better than a lamp or thermistor. In simulations (real life will be worse), I've managed to achieve less than 0.001% THD, using both Wien bridge and state-variable topologies, but it's not known how well that will translate to reality. Remember that the lower the voltage across the JFET, the lower the distortion can be"This exploits the fact that the servo opamp output presents a low-impedance DC point, which for AC is equivalent to ground, making R4 and R5 a 1:2 voltage divider, achieving the exact same result as Williams' circuit, but without the extra gate-to-ground resistor.The 560Ω resistor drain-source in Williams' circuit is already optimized to reduce the impact of the JFET, so the "distortion null" pot is not necessary.With respect to C2, I don't understand what purpose it serves, as the feedback point it will connect to is ground-referenced, and simulation has shown no difference with/without, but I will try distortion measurements to see whether it makes any difference in practice.

author: bsfeechannel
author_rank: Super Contributor
timestamp: April 26, 2021, 09:43:49 pm
content: Quote from: richlooker on April 26, 2021, 10:29:37 am1970's HP209A, 4Hz to 2MHz oscillator, from where Jim Williams may have drawn inspiration for the use of a JFET in the AGC loop, has a capacitor between the drain and the gate of Q8, probably to avoid messing with Q1's bias.

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 27, 2021, 02:41:10 am
content: You may decrease 100k resistor to 47-51k, and you'll get -1.1VDC.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 27, 2021, 07:03:17 am
content: Quote from: richlooker on April 26, 2021, 10:29:37 amAC coupling for the variable resistor JFET may be a good idea if the amplifier in the oscillator has a significant offset, e.g. as shown in the HP circuit. With an OP amplifier for the osciallator there is susually very little DC offset and thus no real need for the large C2* on top of the FET. C2 at the "alternative position" is for a different reason. It may help with a FET that needs a relatively high negative bias for the operation point, so that one can still use a divider between the gain control OP and the FET and thus get away with a smaller cap at the OP. With a 2N4338 one would likely not need C2, the 2N5458 may need it. The 2 positions for C2 and C2* are not fully equivalent.C2 also effects stability of the control loop. Here it can be different between the simple peak detector with a diode and other amplitude measurement modes.

author: richlooker
author_rank: Regular Contributor
timestamp: April 27, 2021, 12:14:27 pm
content: In simulation, a large C2 "on top of" the JFET makes no difference. C2 in series with the drain-gate resistor, on the other hand, turns out problematic, it leads to amplitude bounce/oscillation. Too small and the drain-gate feddback gets frequency-dependent, eg. not effective at lower frequencies. Too large and the amplitude takes forever to stabilize.WIth respect to THD, I have been thinking about a new approach; I have seen that THD is something like exponentially proportional to oscillator RMS. What if I use the lowest-noise opamp I have - NJM2114L (forgot this earlier, as SIP-opamps live in their own drawer) - and tune the oscillator for -6dB/0.3875V RMS, and use the second opamp to amplify the signal 18dB/8x ?

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 27, 2021, 05:30:53 pm
content: Do you mean a composite amplifier? If not, then it doesn't help. Still, you can try.

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 27, 2021, 05:39:29 pm
content: Quote from: richlooker on April 27, 2021, 12:14:27 pmIf we'll look at your oscillator spectrum at your post « #111 on: April 21, 2021, 09:43:00 pm », then we see there that noise is not your problem. The main THD contributor is a non-linearity.

author: richlooker
author_rank: Regular Contributor
timestamp: April 27, 2021, 06:20:44 pm
content: Quote from: Vovk_Z on April 27, 2021, 05:39:29 pmExactly. Non-linearity in the JFET voltage-controlled resistance. I saw as I reduced the oscillator amplitude that THD fell dramatically; when reducing the fundamental by 6dB, 2nd and 3rd harmonic dropped by 12dB. The reason I am thinking low noise opamp is that by reducing amplitude, the fundamental also gets closer to the noise floor, ie. S/N is reduced. And I need to amplify the signal to get the +12dBu output level I need.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 27, 2021, 06:56:02 pm
content: One can reduce the voltage at the JFET with the parallel resistor. The downside is that this also reduces the adjustment range, so one needs the resitors / capacitors to set the frequency to be better tuned.One the other side on could add adjustment range by switching in some resistors digitally, e.g. with relays or low R MOSFETs. This would add digital coarse trim, so one can get away with less analog trim via the JFET. With 2 digitally switched resistor one could reduce the needed range from the up to 4 times.Having the resistor in parallel to the FET absorbes some of the variable part. So it maybe better to use more like a lower resistance fet (e.g. 2N4393 or the like).It is not just the nonlinearity from the JFET, the amplifier can also contribute to distortion.

author: richlooker
author_rank: Regular Contributor
timestamp: April 27, 2021, 09:57:11 pm
content: Quote from: Kleinstein on April 27, 2021, 06:56:02 pmThe parallel resistor - P1 and R10 in this diagram - is selected to give the lowest possible voltage over the JFET while still allowing sufficient regulation range at all frequencies. If we assume Rds(on) is 100Ω;Min gain, when Rds ~ ∞, is: 1 + (5.6k / (2.4k + 0.47k)) = 2.95Max gain, when Rds ~ 100Ω, is: 1 + (5.6k / (2.4k + (470 * 100 / (470 + 100)))) = 3.25Gain of 3 is when Rds in parallel with 470Ω equals 400Ω; this happens with Rds ~ 2.7kThe difference from Jim Williams' value of 560Ω for R5 is quite large; then gain of 3 happens with Rds = 1400Ω, which means twice as much current through the JFET.Quote from: Kleinstein on April 27, 2021, 06:56:02 pmI don't want to go down that route. If required, I could add a deck to the rotary switch for frequency range to switch resistors, but I hope the use of a sufficiently high GBW opamp the gain variance with frequency will be small.Quote from: Kleinstein on April 27, 2021, 06:56:02 pmI doubt that; while the voltage over the JFET determines it's distortion, the current through it determines how much this contributes to the signal.Quote from: Kleinstein on April 27, 2021, 06:56:02 pmI know. First I will see how I can reduce THD from the JFET; then, if I am not satisfied, I may explore opamp type and amplifier topology options.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 28, 2021, 06:52:13 am
content: The variations in the required feedback setting with frequency are not so much the GBW of the OP. A main part are just tolerances of the capacitors / resistors to set the frequency. There is nothing magic about a gain of 3. Depending on the R and C in the frequency setting network, the required gain can be from some 2.7 to 3.3. So one can trim the resistors to get a more uniform gain.The relatively low value resistor in parallel to the JFET limits the adjustment range and may help to get a more uniform response for the amplitude control loop. However it requires a higher voltage at the FET to get the same trim range.A lower resistance FET and less effect of the parallel resistance could help to operate the FET with less voltage across. The difficulty is that the control side gets less linear and thus the stability of the amplitude control loop gets slightly more difficult. One may have to adjust R4 slightly different and possibly limit the voltlage at the gate, not to turn the FET off too much.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 28, 2021, 08:09:28 am
content: How much adjustment range are we looking at here?My understanding of JFETs is, they're most linear for |Vds| < Vgs - Vp. So, for a given peak amplitude |Vds|, higher Vp is desirable, and Rds should be varied from Rds(on) to maybe a few times higher, before the above limit is reached. The important thing being, Rds is not, in general, adjustable all the way from Rds(on) to infinity, in a linear manner, for any given |Vds|.(I don't think that's modified by the linearization (resistors from D to G to bias), but I would be interested to see evidence otherwise.)We shouldn't need to hand-wave and empirically study this system; we need only know the range of resistance required, and this can be found by measuring the bias / control voltage while varying only a series resistor in the path (and not trying to reduce Vds or adjust resistance range with a series-shunt resistor divider before it). By plotting Rs vs. operating conditions/settings (frequency and temperature I suppose?) we can determine the minimum and maximum required values. Further, we can tweak ranges as needed to tighten up this spread. Finally, we can design a JFET circuit to deliver the required adjustment range, and that should simply be it. With the JFET operating in, whatever its most linear range is (if not Vgs ~ 0 then wherever -- this can also be measured independently by setting up a voltage divider with it).I suspect series/shunt resistors are just a hack, as if you don't need that adjustable range in the first place, why use that JFET at all, or why not change all resistor values to simplify the circuit? (Given that the feedback resistance can't drop too far due to op-amp capacity, nor rise too much due to capacitance and leakage.)I haven't been following this thread in great detail so I may've missed this, but I don't recall this having been performed, or proposed, yet.Tim

author: richlooker
author_rank: Regular Contributor
timestamp: April 28, 2021, 01:51:58 pm
content: Quote from: Kleinstein on April 28, 2021, 06:52:13 amTo my best knowledge, there _is_ something magic about a gain of 3, which is the gain that will sustain oscillation for a Wien bridge with perfect and perfectly matched timing components. The tolerances of the capacitors play a role, but this is easily controllable. I use only 1% components, and select matched pairs from a larger pool, to ensure they match to within 0.5%. BTW the required gain will never be below 3, except when the control loop needs to reduce amplitude the gain will be lowered until it stabilizes. And I have tested the amplifier without positive feedback across 10Hz-100kHz, and overall gain drops noticably (but not significantly) over the 10kHz-100kHz decade. This was measured with an LM6172; NE5532 or similar will drop off earlier.Quote from: Kleinstein on April 28, 2021, 06:52:13 amThe point is that the trim range need not be great; at 2.95 oscillation will stop, and at 3.25 there is just enough headroom so that oscillation can start and be sustained acros the entire frequency range. I don't know why a low value parallel resistor should require a higher voltage range across the JFET.Quote from: Kleinstein on April 28, 2021, 06:52:13 amThe key is really that you need to balance three interdependent concerns;Ensure sufficient (but not more than sufficient) control rangeMinimize JFET VdsOperate the particular JFET within it's linear rangeAnd then further minimize the impact of channel length modulation through drain-gate feedback.

author: richlooker
author_rank: Regular Contributor
timestamp: April 28, 2021, 02:00:47 pm
content: Quote from: T3sl4co1l on April 28, 2021, 08:09:28 amThe problem I am trying to solve here is not to get a fast and stable AGC feedback loop; this is already understood and achieved. The challenge is how to minimize the harmonic distortion from JFET channel-length modulation. The most important concern is not whether the JFET is operating within the linear range (this is most important for the control loop) but that Vds is as low as possible.The required gain adjustment range is approx 2.95-3.25. The JFET - or some other AGC mechanism - is an absolute requirement; the oscillator cannot stabilize without it. You are welcome to try stabilizing a Wien bridge by tweaking resistors, but don't hold your breath while waiting for it to become stableJFET drain-source current equations, fromhttps://www.multisim.com/help/components/jfets/jfet-model/For the linear region, if Vds = 2*Vgs, the equation becomes:-2*β*Vto (1 + λ*Vds)- and Ids gets a linear relationship to Vds (ie. ohmic) as opposed to exponential; this is why feeding 50% of Vds back to gate is crucial.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 28, 2021, 03:42:35 pm
content: Well yeah, I already know AGC is required, that's the point...So 2.95-3.25? Why not 3.05?Is the difference the aforementioned drop in loop gain at the high end?Why not tweak out a frequency-dependent gain error using an RC network? (This will introduce phase shift -- indeed, complementary to the op-amp's own phase shift, which is part of the effect as well!)Note that that formula works for the SPICE component. But real devices aren't piecewise functions, they fade smoothly between regimes. How should we express this fact? And do we know whether it's responsible for the dominant part of distortion under whichever conditions?Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: April 28, 2021, 04:11:44 pm
content: The factor 3 applies to the case of equal reistors and equal capacitors for the frequency setting network. With the series connected R and C at 1/2 R and 2*C as the parallel pair the stable oscillation would be at a gain setting of 2 instead of 3.The case with equal values is easier to calculate and may have slightly better stability, but at least small deviations do not change much. So with R and C with some 10% tolerance the required gain could be about in the 2.7 to 3.3 range.The required adjustment range deopends on the accuracy of the RC networks to set the frequency. The better the parts are selected there, the smaller the AGC range can be.2.95 to 3.05 would need relatively tight tolerance, though not imposible. For a given frequency setting the required range could be quite a bit smaller and it does not have to be exactly around 3. Accurate chosen resistors alone are not enough to get a stable amplitude, but they can reduce the needed AGC range. The automatic part only needs to overcome tolerances, drift and have enough range to get the amplitude up and stable in reasonable time. So for a given RC network the actually needed range could be something like 3.14 to 3.141 - more gain may be better for a fast start up.The larger usually required adjustment range is no just a general trend to need more gain at higher frequency, it is likely more due to some not so well chosen RC networks for the frequency.

author: richlooker
author_rank: Regular Contributor
timestamp: April 28, 2021, 06:26:55 pm
content: Quote from: T3sl4co1l on April 28, 2021, 03:42:35 pmBased on my experience during this project. Gain will not exceed the theoretical value assuming perfect opamp, so going much below 3 is not needed. Gain will drop below the theoretical value, so a certain margin is needed.Quote from: T3sl4co1l on April 28, 2021, 03:42:35 pmA theoretical possibility, but probably not worth the effort. If it was, someone would have done it before and published the result; eg. "Parasitic capacitance compensation for 1Hz-1MHz constant gain opamp"Quote from: T3sl4co1l on April 28, 2021, 03:42:35 pmSpice models are the closest approximations to real components mere mortals can afford. There are enough credible sources stating the model reflects actual behaviour for me to trust it. The models are certainly not perfect. But the conditions are not "whatever", they are controlled and specific. The JFET itself is the biggest contributor of (theoretical) uncertainty.Richard

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 28, 2021, 09:38:53 pm
content: Quote from: richlooker on April 28, 2021, 06:26:55 pmI mean... what's there to publish? That just sounds like another day in the office at Tektronix, back in the day.Like---humor me, how about some basic feasibility calculations? Simulations? Is this even in the right order of magnitude to be a relevant effect? Should we just all sit in the dark, spitballing rumors until we all get tired and go home every day?..The pursuit of high levels of precision, seems like a very worthwhile application of a little analysis here, but it doesn't seem to be gaining any traction, or even any recognition? I'm just confused how that should be...QuoteAlright fine, but then, what's the point of low THD if 0.01%, heck, 0.1% is good enough for "mere mortals"? Have I grossly misunderstood the priorities of this project?Tim

author: richlooker
author_rank: Regular Contributor
timestamp: April 28, 2021, 10:13:56 pm
content: Quote from: T3sl4co1l on April 28, 2021, 09:38:53 pmDesign goals:11Hz-100kHz frequency range in four switchable decadesFixed/discrete frequencies, 26 per decade, per 26-position rotary switch (derived from requirement 1: I want immediate and precise frequency selection; dual-ganged pots won't do; and 2: I have this switch and want to use it)Super-fast settling time at frequency change, no amplitude wobble+12dBu / 3.1V RMS output & 11-step attenuator 0db - -60dBTHD < 0.01% 100Hz-10kHzLearn a lot & have funMake an awesome looking and practically usable deviceThe gain variance caused by RC network tolerances is minimal, as I have ensured capacitors and resistors match to within 0.5%. Phase shift in the opamp at increasing frequencies is adequately handled through different compensation resistors per frequency decade. The remaining challenge is the THD one; the rest is just work. From my - admittedly limited - knowledge and what I have experienced so far, it's JFET channel length modulation that stands between me and the THD < 0.01% goal. If someone convinces me that frequency-dependent gain compensation will help, I will certainly look into that. But until then I'm focused on taming the prickly JFET

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 28, 2021, 10:31:52 pm
content: Quote from: richlooker on April 28, 2021, 10:13:56 pmHave you tried different Fets? One of them may lead you to <=0.01%.It has to be not very hard to go under 0.01% at some frequency. But it can be quite hard to have <0.01% in the whole frequency range.

author: richlooker
author_rank: Regular Contributor
timestamp: April 28, 2021, 10:57:05 pm
content: I have concluded that none of the JFETs I have are optimal for this application. I have a few on order; the 2N4338 used by Jim Williams plus some 2N5484 as this was used by ESP/sound-au.com. The former achieved 0.015% but without tweaking resistors to reduce it further, and measured at the resolution limit of the THD meter - meaning the actual result may have been even better - while the latter claimed < 0.01% in simulations, also without further tweaking. This gives me hope I can achieve the same result by replicating what they did, and maybe further improve upon that through patience and perseveranceRichard

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 29, 2021, 12:33:33 am
content: Quote from: richlooker on April 28, 2021, 10:57:05 pm:-) I don't want to say that, but "I told you" at the very beginning that Wien-Bridge is not the best topology if you need both low distortion, high amplitude regulation, and wide frequency range.

author: richlooker
author_rank: Regular Contributor
timestamp: April 29, 2021, 10:22:46 am
content: Quote from: Vovk_Z on April 29, 2021, 12:33:33 amIt's certainly not the easiestRichard

author: richlooker
author_rank: Regular Contributor
timestamp: April 29, 2021, 09:52:39 pm
content: It dawned on me; the distortion from the JFET in the neg feedback network is a completely separate problem from oscillation conditions and regulation. Why not do some measurements with the complicating factors removed from the equation?This is the amp exactly as it will be in the oscillator, just with the positive feedback network removed:Until I get the 2N4338 and 2N5485 I have ordered, I will test BF245C, 2N5458, 2SK170BL and J110;Apply a 1kHz 0dBu/3 signal at U1A positive inputStep through 6 different combinations of R3, R4 and R5Tune in Vgs with P2 for U1A gain=3 - ie. Vout = 12dBuMeasure VgsTune P1 for lowest THDThe first three resistor combinations are the values from Jim Williams' circuit plus two variants keeping Vds approximately the same but with double and half the Ids. The next three combinations get approximately half the Vds, and again three different Ids values.I have approximated Rds(on) at 100Ω; deviations from this value will just impact max gain - eg. J110 will probably have a much lower value, but this does not matter as it will not be operated in this region anyway.Richard

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 29, 2021, 10:09:10 pm
content: THD of LM6172 itself both non-inverted or inverted mode is very low (ultra-low). It is somewhere near 0.001%. It depends somewhat on feedback resistors resistance.The most and the only one non-linear element of this circuit is JFET.That's why some designers use opto-resistors (as more linear) for ultralow distortion oscillators.But it is hard to get them these days at the market.

author: richlooker
author_rank: Regular Contributor
timestamp: April 29, 2021, 10:26:00 pm
content: Quote from: Vovk_Z on April 29, 2021, 10:09:10 pm

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 30, 2021, 07:55:37 am
content: Quote from: richlooker on April 29, 2021, 09:52:39 pm- I make a bet that the first combination has the lowest THD.(I don't have any deep theory about that, it's just a guess from my engineering experience with my own Wiene-Bridge project).

author: bsfeechannel
author_rank: Super Contributor
timestamp: May 02, 2021, 02:36:18 am
content: Quote from: Vovk_Z on April 29, 2021, 10:09:10 pmLDRs?

author: Vovk_Z
author_rank: Super Contributor
timestamp: May 02, 2021, 05:04:18 pm
content: Yes, somebody use combination of LDR plus LED, but it is not very convenient.

author: 2N3055
author_rank: Super Contributor
timestamp: May 02, 2021, 05:17:39 pm
content: Some posts are missing...There are optocouplers that combine LED and LDR as ready made units.For instance NSL-32SR3 (now Luna Innovations Incorporated) as member Blackdog mentioned in missing posts...You can easily make one by yourself from green LED and LDR, but will have to characterise it by yourself too.

author: blackdog
author_rank: Frequent Contributor
timestamp: May 02, 2021, 06:02:10 pm
content: Hi,This is strange...My post about the NSL-32SR3 opto coupler has disappeared....That's not because of my interference I just looked back on the forum and couldn't find my post anymore, what's going on?Kind regards,Bram

author: RoGeorge
author_rank: Super Contributor
timestamp: May 02, 2021, 06:06:29 pm
content: Quote from: 2N3055 on May 02, 2021, 05:17:39 pmYes, Dave told us that it was some database incident, so most probably it was necessary to roll back a day or so, in order to fix the issue. Looking at my own posts, it seems like only about one day is missing, but IDK for sure how.In this topic I was suggesting to put a photo-resistor together with a white LED and a few layers of black shrinking tube in order to improvise an optocoupler, and later from other replies it was suggested a green LED would be even better than white, and that many resistor based optocouplers can be ordered from Mouser or Farnell.

author: David Hess
author_rank: Super Contributor
timestamp: May 02, 2021, 07:19:54 pm
content: Quote from: RoGeorge on May 02, 2021, 06:06:29 pmIt is a glitch in the Matrix. It happens when they change something.

author: richlooker
author_rank: Regular Contributor
timestamp: June 19, 2021, 10:39:24 pm
content: It's been a long time. That's the way it is when you have too many simultaneous projects :-)I finally got my FETs - 2N5484 and 2N5486 (Fairchild, eBay seller littlediode components, UK) and 2N4338 (unspecified, eBay seller nikkoelec, UK).Did a quick check of Vgs(off) and measured the 2N4338 to -6V, very clearly a fake, just a rebadged generic TO-72 JFET.Then I discovered Siliconix Application Note 105: JFETs as Voltage-Controlled Resistors:https://www.interfet.com/jfet-datasheets/siliconix-an105.pdfThis AN was very informative. It states that the JFET is most linear as a VCR when operated close to Rds(on), and that distortion rises significantly when Rds exceeds 10 x Rds(on). It reiterates that Vds must be kept low to minimize distortion, and that applying 1/2 of (AC) Vds to the gate keeps distortion at minimum. And then the crux:- There are JFETs that are purpose-made for VCR application!The VCR4N seems most suitable for my requirements. I ordered one from mouser, along with a genuine 2N4338.I made a circuit to measure Rds(on) plus Rds at different Vgs and corresponding distortion when applying a 775mV 1.3kHz signal. To avoid the interdependency between the Vgs DC bias and the AC signal fed from drain, I introduced an opamp.This provided some interesting learnings;VCR4N and 2N4338 don't actually have a Vgs(off) or Vp, they reach a max Rds at a certain Vgs which then does not increase with lower Vgs (approx 7.5 x Rds(on)VCR4N is substantially better than the RF/general-purpose JFETsMy VCR4N has an Rds(on) at approx 430Ω, which is quite ideal for my applicationAt Vds (AC) above 200mV, distortion rises sharplyThe 2N4338 is not very well suited to my application, with an Rds(on) around 1.2K and much higher distortion than VCR4N

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 19, 2021, 11:56:31 pm
content: Quote from: richlooker on June 19, 2021, 10:39:24 pmWell gosh, this must've been mentioned only about a dozen times in the thread!QuoteFor reference:http://www.farnell.com/datasheets/40047.pdfNote that they hardly give any data, and no curves besides the extremely up-close drain curves -- which look reasonably controllable, but of course they do within such a small region, and it's not clear where cutoff lands (despite the label on the plot).If they aren't some weird special design, they should be nothing more than devices selected for high Vgs(off), I think.QuoteHmm, this is not possible, or something is funny about the interpretation?The datasheet clearly says Vgs(off) at Vds = 10V, Id = 1uA or whatever. It has cutoff like any other JFET, and so Rds(on) will go towards infinity as Vgs falls -- and within a decreasing span of drain voltage for which the response is linear, or else increasing distortion at fixed drain voltage. The drain-gate divider cannot fix this, as inevitably Vgs < Vgs(off) must occur at some point, and as it crosses the threshold, Id goes to ~0 resulting in distortion. (Which should be, mostly a zero-crossing sort of thing, due to the effect of the divider? Effectively as signal voltage goes negative, drain and source swap positions, so Vgs has the same response as for positive signals -- hence the half divider: the strategy is to put the gate "in the middle" between D and S, making the distortion symmetrical I think. It's not that it's halving drain voltage, it's that it's averaging both drain and source voltages together. Ah, I never noticed that before and merely took the trick for granted, makes sense.)Are you measuring current exactly as indicated in the schematic, or actually Vds in which case Rs makes a divider with R4+R3 and anything else hanging off the circuit (presumably the probe is over a meg though)? That could have that kind of effect.Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: June 20, 2021, 03:43:40 am
content: As shown the circuit adds the full drain votlage to the gate, not half as it should be for lowest distortion.

author: richlooker
author_rank: Regular Contributor
timestamp: June 20, 2021, 11:50:39 am
content: Quote from: T3sl4co1l on June 19, 2021, 11:56:31 pmNot exactly. It has been mentioned that the "linear region" is where Vds < Vgs(off) - Vgs - but this linearity is in fact only very linear when Rds < Rds(on) x 10, and according to my measurements it's best to keep Rds < Rds(on) x 5Quote from: T3sl4co1l on June 19, 2021, 11:56:31 pmVCR2N is specified for Vgs(off) between -1 and -3.5V, not very high?QuoteQuote from: T3sl4co1l on June 19, 2021, 11:56:31 pmI am measuring Vds, with a 10M probe. For 2N5458, 2N5486 and the fake 2N4338, Rds reaches Rds(on) x 50 at Vgs ~-3V. VCR4N and 2N4338 refuse to increase Rds beyond Rds(on) x 8 - for a pure AC signal in the < 1V peak range. There may be something fishy about my measurement setup; I'll try with larger R3 and R4, and buffer Vd with a TL072 to avoid loading the circuit.Richard

author: richlooker
author_rank: Regular Contributor
timestamp: June 20, 2021, 11:53:07 am
content: Quote from: Kleinstein on June 20, 2021, 03:43:40 amThis is a simulation of the circuit. Measurements match this.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 20, 2021, 02:06:25 pm
content: Quote from: Kleinstein on June 20, 2021, 03:43:40 amHow so, the diff amp has gain 0.5?Quote from: richlooker on June 20, 2021, 11:50:39 amSame same? Rds, V(linear) and Vgs are all related. Think I've also said, more qualitatively, that it's only useful over a narrow adjustable range, I might've said like 3x or something. So that fits nicely with the above finding.QuoteCheck the datasheet I linked, Vishay's are -3.5/-3.5/-2.5 for the series.The InterFET version shows otherwise:https://www.mouser.com/datasheet/2/676/jfet-vcr2n-interfet.r00-1649182.pdfBeware, YMMV?Tim

author: richlooker
author_rank: Regular Contributor
timestamp: June 24, 2021, 10:20:03 pm
content: New test circuit, with a couple of extra opamps to isolate Rs & T1 from the feedback network and probe impedance, and to keep the load on the generator constant (zero).Will redo the tests and see if VCR4N has a proper pinch-off or not. (2N4341 was the closest thing I found in the Tina-TI spice library)

author: Kleinstein
author_rank: Super Contributor
timestamp: June 25, 2021, 06:48:33 am
content: In the simple circuit with a constant resistor from the source, one would also change the voltage on the DUT when changing the resistance. So at a higher fraction of R_on the test would be at a higher voltage and thus naturally more nonlinear.For the application one more needs a certain level of voltage at the FET to have enough control range. So a fair comparison would be with changing the R_on of the fet, or comparing 2 fets in parallel to a single FET.With the divide by 2 and a relatively high pinch-off, the circuit may not reach the fully off state in the practical circuit, but this is just a limit of the supply / circuit.

author: richlooker
author_rank: Regular Contributor
timestamp: June 27, 2021, 12:32:56 am
content: Quote from: Kleinstein on June 25, 2021, 06:48:33 amThanks for pointing that out; how about this circuit, where i can plot Vgs and Id with different, constant Vds settings? With no series resistor, I'll have to rely on the AC current accuracy of my Fluke 287, though. The 500µA range specification: Resolution 0.01µA, accuracy 0.6% + 20. The internal resistance is not stated, but I assume it's negligible.Richard

author: Kleinstein
author_rank: Super Contributor
timestamp: June 27, 2021, 04:26:50 am
content: For chcing linearity it is not enough to measure the current with a DMM. The DMM can not distinguish between the excitation and the harmonics.I would more consider a test with a kind of inverting amplifier, where the FET is the input resistor. The ouput would be inverting and one can thus easy subtract the approximate driving signal with just 2 resistors.The resistor R9 would be chosen to the restance value to test, so maybe switchable to a few values of interest.RV1 sets the DC gate level (some -10 V to -2 V) and would be adjusted to get low / minimal signal at the output.RV2 (some 1 K) is for adjusting the symmetry of the JFET to trim the 2nd harmonic. To be fair with a single setting for the DUT.The ouput should mainly give half the harmonic contend, with the excitation suppressed depending on how good the gate voltage is set.

author: richlooker
author_rank: Regular Contributor
timestamp: August 19, 2023, 06:55:55 pm
content: It's been a while since I worked on this project. That's how it is when you have too many projectsI have modified the sample&hold peak detector a bit; originally I used schottky diodes, but the reverse leakage current of these proved problematic as I also made the hold capacitors smaller to reduce the current required to charge them - plain old 1N4148 does the job better, and the drop is compensated in the output buffer stage. Also added a circuit to detect a stalled oscillator - which may happen when changing frequency - as without this, the peak detector will continue to hold the last peak, and the oscillator will not start again. Lastly; a Sallen-Key 2nd order low pass filter on the output, to tame the little peak from the sampling pulse (explained at sound-au.com as "gate charge transfer"; not a problem for optocoupler stabilization, but with JFET stabilization it modulates Rds and contributes to THD)Also done some modifications in the oscillator itself; it needs extremely low input leakage current to avoid interfering with the positive feedback network, but also high current / low impedance output to drive said network without lag or sag. A TL072 with the output buffered by an LM6172 fits the bill. The 50% feedback from drain to gate of the AGC JFET is isolated from the DC gate bias through a TL072 configured as a differential stage.

author: richlooker
author_rank: Regular Contributor
timestamp: August 19, 2023, 07:18:09 pm
content: The complete circuit breadboarded and under test.The audio interface I used earlier (Propellerhead Balance) has developed a lot of noise and THD contribution, so I had to use the even older but still better NI Audio Kontrol 1.As reference I am using my Tektronix ASG 100 audio signal oscillator.Quite happy with the results now. Right/red curve is DUT, left/blue is ASG 100. I am obviously operating close to the limits of the audio interface, as 96 kHz sampling works best; going either up or down in sampling frequency produces poorer results. The specified THD for the Audio Kontrol 1 is 0.003%, so this makes sense. The DUT is quite sensitive to any touch, THD jumps up and down just by slightly moving decoupling capacitors, -88.1dB / 0.0039% is the best I can get with this setup, but I believe better than -90dB should be obtainable with careful PCB layout, placing ceramic & electrolytic decoupling capacitors close to the opamps and comparators, and by proper shielding.

author: RoGeorge
author_rank: Super Contributor
timestamp: August 20, 2023, 05:21:11 am
content: That's one of the most elaborated!

author: Messtechniker
author_rank: Frequent Contributor
timestamp: August 20, 2023, 07:38:45 am
content: With Audio Tester it is - among other math - possible to subtract two curves; i.e. measured curve minus loopback curve, for example. See help file.

author: Datman
author_rank: Regular Contributor
timestamp: August 20, 2023, 08:34:24 am
content: Experimenting is good, but you should also experiment various solutions and chose the best and simplest one! Try with an Arduino Nano and a cheap DDS AD9833 module from Aliexpress or Ebay: start by copying a simple project on the net, then study it, understand how it works and make it how you like. Arduino forum is very useful for learning programming.

author: RoGeorge
author_rank: Super Contributor
timestamp: August 20, 2023, 09:27:59 am
content: The struggle in this topic was to get the lowest possible distortions at 1kHz.By its datasheet, AD9833's distortions are about 100 times higher than this.

author: Datman
author_rank: Regular Contributor
timestamp: August 20, 2023, 10:58:18 am
content: The discussing started with a variable audio oscillator...

author: Datman
author_rank: Regular Contributor
timestamp: August 20, 2023, 11:30:03 am
content: Using a fast microcontroller, you could read a 20 or 24bit sine table...

author: richlooker
author_rank: Regular Contributor
timestamp: August 20, 2023, 01:03:23 pm
content: Quote from: Datman on August 20, 2023, 10:58:18 amIt did indeed. And, as the name of the thread indicates, I want to solve it with a wien bridge oscillator. Furthermore, to use a JFET as the AGC element.Quote from: Datman on August 20, 2023, 11:30:03 amI work with digital stuff for a living. Analog nerding is my hobby. Microcontrollers and DDS are boring and devoid of soul. I find sophisticated analog solutions intriguing, elegant and sexyDesign goals:11Hz-100kHz frequency range in four switchable decadesFixed/discrete frequencies, 26 per decade, per 26-position rotary switch (derived from requirement 1: I want immediate and precise frequency selection; dual-ganged pots won't do; and 2: I have this switch and want to use it)Super-fast settling time at frequency change, no amplitude wobble+12dBu / 3.1V RMS output & 11-step attenuator 0db - -60dBTHD < 0.01% 100Hz-10kHzLearn a lot & have funMake an awesome looking and practically usable deviceFor simplicity, I have kept the frequency at 1kHz while chasing the lowest possible THD. I expect THD to increase slightly towards higher frequencies, and probably a bit more as the frequency approaches 10Hz.There is still one unsolved challenge; the aforementioned "gate charge transfer" artifact induced by the gating/sampling pulse. I cant't show a scope trace of this, as my scope just died, but simulation shows the exact same sharp "bump" on the sampled voltage. Unfiltered, this gets through to the JFET gate and causes a significant increase of 2nd harmonic distortion. I have - for now - tamed it with a low pass filter, but this will be optimal for a specific frequency, and as the oscillator frequency is lowered down towards the cutoff frequency, the filter itself will be a contributor to THD. I don't have the possibility to add more decks to the frequency range switch, but I could add another rotary switch to control the filter cutoff frequency.In the article that inspired the start of my project: (https://sound-au.com/project174.htm)"Small 10µs pulses appearing on the AGC line are due to 'gate charge transfer' in the sampling switch, but again this is not an issue because thankfully the LDR is too slow to see them."No problem with an LDR, but a problem for JFET stabilization. I would like to understand what this phenomenon really is, and how it's avoided/compensated in precision S&H circuits.A 10ms simulation of the sample&hold circuit with 1kHz input:And zoomed in to the problem area; as the gating pulse drives the gate of the J110 sampling switch high, a 23mV bump appears on the sampled voltage. The low pass filter tames it quite OK, but it smears the pulse out as a slow wobble, which may lead to problems as the oscillator frequency (or 2nd or 3rd harmonic) approaches the filter cutoff frequency.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 20, 2023, 01:45:36 pm
content: The circuit uses the JFETs as switches in an unusual (wrong) way. When on the gat voltage should be at the signal voltage, not much higher. So the resistors should ideally go to a buffered signal that is switched and not the +Vcc. This should reduce the switching spike quite a bit.Another shouce of some switching spike is the gate capacitance. Ideally one would compensate with an opposite moving signal and a small capacitor to an opposing spike.One could reduce the spike by using smaller / lower capacitance JFETs. The J110 noted in the plan is rather high capacitance. Something like J202 or J112 would be lower capacitance, though also higher on resistance.

author: RoGeorge
author_rank: Super Contributor
timestamp: August 20, 2023, 03:39:00 pm
content: Quote from: richlooker on August 20, 2023, 01:03:23 pm2nd harmonics means something that affect differently the upper vs the lower half semialternance of the waveform. Maybe if you sample for both the positive and the negative peaks, then the influence of the sampling circuit will be symmetric, and thus less distortion of the 2nd harmonic type, plus the amplitude control might react even faster if the reading is on both the negative and the positive peaks of the waveform (instead of sampling only on the positive peak).

author: richlooker
author_rank: Regular Contributor
timestamp: August 20, 2023, 08:08:41 pm
content: Quote from: Kleinstein on August 20, 2023, 01:45:36 pmI tried referencing the output of the pulse-generating comparator to the peak voltage through a buffer. Not much difference; still a bump at a little less than 20mV.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 20, 2023, 08:11:18 pm
content: Quote from: richlooker on August 20, 2023, 01:03:23 pmHehe, I like that sort of requirementIt also means you avoid the issues of pot tracking, and can use precision / matched resistors.Precision caps would be interesting...Quote from: richlooker on August 20, 2023, 01:03:23 pmYou can also filter using pulse timing, but that adds more parts.PLLs can have similar impulse problems, where a narrow pulse decides the information, but you want a smooth control.They add a second sample and hold, that isdisabledat and just after the impulse time, and enabled during the hold time.That removes the bulk of the impulse, and you filter the rest.

author: richlooker
author_rank: Regular Contributor
timestamp: August 20, 2023, 08:31:00 pm
content: Quote from: RoGeorge on August 20, 2023, 03:39:00 pmInteresting idea, but I am inclined to shy away from the complexity of sampling the negative peaks also. It means duplicating at least 2/3rd of the circuit, finding a reliable way of negating the sampled negative values, and compensating for any DC offset that will otherwise lead to a square wave superimposed upon the output. But your answer is also pointing me towards another potential improvement: Timing capacitors in the oscillator feedback network. I have relied on 1% tolerances with no further matching, but maybe I should buy eg. 10 of each value required and pick the pairs that matches most closely.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 20, 2023, 08:46:00 pm
content: The filter / compensation in the AGC part does not provide a lot of low pass filtering. There is the 2nd order active LP filter for the V_out signal, but the regulator is a simple proportional one.The more normal way is to have a more PI type regulator and thus a kind of integrator (capacitor in series to R13) to control the JFET for the amplitude regulation. This way the pulse at Vput may have less effect.20 mV is about the order of magnitide expected for the gate charge of T2 and the 10 nF hold capacitor. A smaller JFET for T2 could improve things.

author: richlooker
author_rank: Regular Contributor
timestamp: August 20, 2023, 08:52:12 pm
content: Quote from: PCB.Wiz on August 20, 2023, 08:11:18 pmI found this paper:https://www.uio.no/studier/emner/matnat/ifi/INF4420/v11/undervisningsmateriale/INF4420_V11_0208_2.pdfIs this what you are suggesting? And would MOSFET's be a better choice than JFET's?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 20, 2023, 10:26:50 pm
content: Quote from: richlooker on August 20, 2023, 08:52:12 pmYes, the first drawing, has series anti-phased switches (missing is an actual second hold cap, after M2 )Quote from: richlooker on August 20, 2023, 08:52:12 pmYou would need to check the linear regions.Many of the JFET info's on the web are just plain wrong.This is one of the better oneshttps://www.allaboutcircuits.com/textbook/semiconductors/chpt-5/active-mode-operation-jfet/tho here they do not plot into the 3rd quadrant.This is the bit that matters :A contrast of the JFET’s characteristic curves against the curves for a bipolar transistor reveals a notable difference: the linear (straight) portion of each curve’s non-horizontal area is surprisingly long compared to the respective portions of a BJT’s characteristic curves:ie you want a device with 'longest straight parts of the curves', and with a useful resistance operate region.MOSFETS tend to be lower on resistance, (aka 2N7002), but there are modern high voltage mosfets, that could be worth exploring.eg I find a AO3160 that is 600V 300 ohms tho the curves stop before they show your AGC operating region, so you would need to curve-trace those.JFET optocouplers are another control option ?The other control element you could look at, is the Operational Transconductance Amplifier ? ( NE5517, LM13700, LT1228, LT1256 ... )These have a low linear input region (sub 100mV) but they drive a multiplied current output that is a fraction of the active current, as it's just needed for gain-variation correction.Addit : I also found this from onSemi AN-6603 A Linear Gain Controlled Amplifier, which shows small injection used from drain into gate, to lower distortion.https://www.onsemi.cn/pub/collateral/an-6603cn.pdf

author: David Hess
author_rank: Super Contributor
timestamp: August 21, 2023, 12:09:02 am
content: Quote from: PCB.Wiz on August 20, 2023, 10:26:50 pmThe Linear Technology part-per-billion Wien bridge oscillator used the LT1228. This is the design to use for *testing* 24 bit ADCs.

author: jonpaul
author_rank: Super Contributor
timestamp: August 21, 2023, 12:45:05 am
content: See the papers on low THD, audio gen, esp Hewlett and Packard 1930s, Jim Williams, and Audio Rpecision.The variable element must be totaly reisitive and isolated from the contl loop, only a CdS photoisolator and thermistor or incandescent lamp have suceeded.The JFET, work but do not give a great THD over the freq band.J

author: PCB.Wiz
author_rank: Super Contributor
timestamp: August 21, 2023, 01:07:56 am
content: Quote from: jonpaul on August 21, 2023, 12:45:05 amNot quite.The variable element must be linear, it does not need to be resistive. (see the very low distortion LT design mentioned above using LT1228 )It also helps if the variable element is nulled, so it manages only unbalance, (as per LT design) as that can slash the distortion contribution.That means fixed frequency oscillators can have better specs, than ganged-pot variable designs.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 21, 2023, 04:48:02 am
content: The charge inection compensation is what is wanted for the sampling pulse. Discrete MOSFETs are a bit tricky to use, as there are very few with a separate substrate connection. So the choice is mainly between JFETs and CMOS switch chips (e.g. CD4066, DG211). As the pulse is essentially fixed (fixed voltage when stable) and can be reduced with a smaller JFET, one may not need the full program.

author: richlooker
author_rank: Regular Contributor
timestamp: August 21, 2023, 09:41:16 am
content: Quote from: Kleinstein on August 21, 2023, 04:48:02 amThanks a lot for the "smaller JFET" tipAssuming the TINA-TI models are representative, this did wonders. With J112, the clock feedthrough was reduced (from approx 23mV with J110) to less than 10mV. The ripple is also more rounded, so it's easier to filter:As for J202, the pulse was further reduced to less than 5mV, as is rounded even more, but now Rds(on) is too high, so almost 10 samples is required before the output stabilizes (not shown in this trace). Not a problem with high frequencies, but more of a problem in the 10-50 Hz area: