How to Test Dynamic Power of (PLLs, LUTs, DFFs...etc)? - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: April 27, 2021, 03:34:06 pm
content: I am currently undertaking an internship in an FPGA company. The company have given me this task because it isnt mission critical but I still get my hands dirty. It is actually pretty cool because I get to try out a whole bunch of stuff as long as it is related to power estimation of an FPGA.My goal is to figure out a way to model the dynamic power usage of the FPGA. I will attempt to measure the dynamic power of the variables aspects of theFPGA through whatever approach makes sense.I am still waiting on a test board so I will mess around with an ice40 HX1K beforehand (I am going with the SymbiFlow route) to figure out the best way to capture this information.At the end of the day, I would like to build an estimation tool similar to Xilinx XPE (Eg Series 7).Any ideas on how to best estimate the dynamic power use of a single DFFs?However, I will just have a OSC/DMM, nothing too fancy.

author: NorthGuy
author_rank: Super Contributor
timestamp: April 27, 2021, 05:53:47 pm
content: You build a shift register of length X, and a shift register of length X+N. You drive "10" signal through it continuously. Then you measure the difference in power consumption dP. The consumption of one FF will be dP/(N x f) where f is the frequency. There will be some power loss in interconnect though, but it's the same as in the real life.

author: steamedhams
author_rank: Regular Contributor
timestamp: April 27, 2021, 06:47:41 pm
content: Bloody legend!Any thoughts on LUTs? PLLs? DSPs? RAM? ...etc?

author: NorthGuy
author_rank: Super Contributor
timestamp: April 27, 2021, 08:21:59 pm
content: Quote from: steamedhams on April 27, 2021, 06:47:41 pmSame way. Add bunch of them to the design and measure the difference.But there are peculiarities. Say, 4-input LUTs have 4 inputs which are all the same logically and tools may interchange them as they please, but these 4 inputs are dramatically different in terms of power consumption.

author: ogden
author_rank: Super Contributor
timestamp: April 27, 2021, 08:23:58 pm
content: Quote from: steamedhams on April 27, 2021, 06:47:41 pmReally asking or kidding? - Fill whole FPGA with STUFF, run at some clock frequency, then fill 1/2 FPGA with same STUFF, test at same frequency, then fill 1/4 and test again. Look for static consumption in the consumption curve to substract it out of results. You may need more than three measurements of various fill levels to get meaningful consumption calculation for one element of the STUFF. Well... and pray that your employer do not find out how you came to solution

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 28, 2021, 12:10:12 am
content: Yeah, as above, I suggest doing measurements with a very significant number of LUTs/DSP blocks/BRAM blocks/etc to make your measurements relevant, and make negligible the fact a few of those resources may not be fully utilized, or may not be utilized exactly all the same way. Forget about measuring the power consumption of individual LUTs, BRAM or whatever. Design to make use of a large number of them, measure, and divide.Obviously measure at different clock rates too.Do not forget to think about temperature. Depending on resource use and clock rate, the die temperature may rise significantly, with a definite impact on current draw. So I suggest either adding a cooler of some kind, or at least monitoring the chip temperature and logging it along with your current measurements.

author: NorthGuy
author_rank: Super Contributor
timestamp: April 28, 2021, 03:41:34 am
content: Simply filling the FPGA with stuff and running it at certain clock frequency won't give you good estimates. This is because power is consumed when something switches. Two designs with the same number of elements and same clock frequency may differ from each other by several order of magnitude.Even the same design, such a shift register - say 50000 flops long. If you feed it alternate pattern - "101010 ...", you'll get 50000 switches every clock edge. If you feed it with constant '1' or '0', you'll get no switches at all.Therefore, building a model of power consumption is rather difficult, and the results will not be very accurate. For practical purposes, people just measure the actual design, or just watch the temperature.

author: ogden
author_rank: Super Contributor
timestamp: May 15, 2021, 09:14:20 pm
content: Quote from: NorthGuy on April 28, 2021, 03:41:34 amWell, Mr.Obvious - suggestion to fill FPGA with stuff andrun it at certain frequencymeans exactly that - all that stuff is actually switching and not standing still