Programmable logic for mortals - Page 1
Forum section: electronics / general

author: McPete
author_rank: Regular Contributor
timestamp: November 22, 2011, 02:30:07 am
content: Hi all,I'm just finishing up a unit on FPGA/HDL design at my college (CIT) and while I now have a reasonable basis for writing VHDL, I'm not even close to claiming to be able to implement an FPGA in a design.My employer doesn't have the facilities or real need for such a high density device, but I'd like to keep my hand in HDL type work, for future projects. I've been looking at the various CPLD/SPLD systems on the market, looking for a nice, simple way to implement programmable logic in my designs.I'm really after something in a hand-solderable package (DIP, SOIC, PLCC or (T)QFP, with 5v tolerant I/O and a reasonable suite of development tools... I'm using Altera Quartus II at the moment, for reference.I'd be using the devices for "glue" logic applications, combinational logic, and maybe some small synchronous designs. Has anyone else found a suitable system?Thanks,Peter

author: joelby
author_rank: Frequent Contributor
timestamp: November 22, 2011, 04:46:18 am
content: I would recommend buying an off-the-shelf development board rather than bare chips if you're getting started. 5v I/O will constrain you to older devices - what sorts of things are you planning to interface with?Digilent sell a relatively inexpensive C-Mod board that breaks a Xilinx CPLD into a DIP form factor:http://www.digilentinc.com/Products/Detail.cfm?Prod=CMODFor FPGAs, check out my list of cheap boards:http://tristesse.org/CheapFPGADevelopmentBoards

author: McPete
author_rank: Regular Contributor
timestamp: November 24, 2011, 04:44:18 am
content: Most of the things I'd want to be interfacing would be microcontrollers (I'm planning on learning the MSP430, my colleagues use Arduino systems and the odd PIC-AXE) and sensors- Some point contact stuff like float switches, ADCs, and other odds and ends. I can't really describe a typical project for me, because the nature of my work (research support) means that every job is so different!My main concern with FPGAs is that the implementing (fan-out, different supply voltages, configuration memory, etc) would make implementing them a bit too demanding for most of my projects. I do have Terrasic DE0-Nano development board though.I did see the Altera MAX 7000S had 5V I/O though, that looks promising.

author: slateraptor
author_rank: Frequent Contributor
timestamp: November 24, 2011, 05:35:10 am
content: Quote from: McPete on November 24, 2011, 04:44:18 amA word of caution: Unlike most of your typical microcontrollers out there, properly designing even a low-end FPGA platform is comparatively non-trivial and more expensive.Don't let it deter you from traveling the less traveled path. You'll find that the learning experience, success of fail, will give you a significant upper hand over your peers. If anything, you'll gain a deeper appreciation for the complexity of the device class.

author: amspire
author_rank: Super Contributor
timestamp: November 24, 2011, 06:16:56 am
content: Are there any modern equivalents of the old PEEL and GAL 16, 18 and 22 pin programmable chips? I used to love these because you could design and program glue logic extremely quickly without needing any development board. They look too simple, but you could do a lot with them. They were not trivial.They did the job if you needed some port expansion, or needed some extra logic between a micro and a board input pin. Simple designs literally took 5 minutes.I just went to Mouser and saw that Lattice GAL's are still available, but at ridiculous prices ($5 to $10 for just 10 macrocells). PEELS were gobbled up by Diodes Inc who then buried all evidence in a very deep hole somewhere. Diodes even thoroughly purged the Internet of all copies of the free development tool just to prevent any scoundrel from actually trying to use a PEEL.Modern FGPA's are great, but every time you use one, you are starting a major job and the packages aren't the best for prototyping.Richard.

author: joelby
author_rank: Frequent Contributor
timestamp: November 24, 2011, 06:24:21 am
content: The PIC microcontrollers that have configurable logic cells may do what you want, when you require a little bit of extra logic.The smallest CPLDs these days seem to be in QFN32 packages, which I don't think are too tricky to deal with in prototypes. They only require appropriate voltage regulation and a JTAG header.

author: amspire
author_rank: Super Contributor
timestamp: November 24, 2011, 12:51:33 pm
content: Quote from: joelby on November 24, 2011, 06:24:21 amI will have to take a look at those PIC microcontrollers. Sound interesting.I did find that Atmel is still making some 16V8 and 22V10 electrically eraseable-type SPLD ic's for around $0.60 to $2 each, so my suggestion is to add these to your programmable logic toolkit. They are available in SMD and DIL, 3.3V and 5V, and definitely no development board is needed. They are often enough to add that fast hardware logic when you cannot do everything using software and interrupts. They also work well as port extenders so they allow a board to use a smaller processor chip, and less tracks have to be routed from one part of the board to another. To get the most out of them, you often cannot enter logic in in an abstract form and let a compiler translate it to logic - you have to direct how the macrocells will be interconnected. But with a very small number of macrocells, it is not hard.When you need the complex programmable logic, the SPLD chips are no replacement, but when the micro has more then enough processing speed given a little hardware help, and when you want to be able to develop fast, the SPLD's still have a place.Richard.

author: mark2112
author_rank: Contributor
timestamp: October 14, 2012, 08:41:02 pm
content: Quote from: McPete on November 22, 2011, 02:30:07 amHi McPete!My friend and I were looking for just that: an FPGA in a DIP package with 5-volt tolerant I/O pins. We weren't satisfied with what was on the market, so we made our own!Check it out at:http://micro-nova.com/mercuryWe packed a Spartan-3A onto a 64-pin DIP package - perfect for use on a breadboard, or for hand-soldering into your own project. It is USB programmable, has 5-volt tolerant I/O pins, and has more goodies like an onboard ADC and 4-Mbit SRAM!And it works great with Xilinx's free and awesome ISE WebPACK design tools!Mark

author: mark2112
author_rank: Contributor
timestamp: November 23, 2012, 04:45:17 pm
content: Quote from: mark2112 on October 14, 2012, 08:41:02 pmIf any of you are interested, this module is currently on Black Friday sale!https://www.eevblog.com/forum/buysellwanted/fs-mercury-dip-fpga-module

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 23, 2012, 07:36:39 pm
content: Quote from: amspire on November 24, 2011, 06:16:56 amLow-end CPLDs in the 36-72 macrocell range are the closest - very cheap, but typically 3.3v only. Unfortunately AFIAK all the vendors bundle support into their humungous milti-gig software packages instead if having a simple CPLD-specific compact package.I used to like using CUPL for GALS - something similar for CPLDs would be nice - I have a deep distrust of the the whole "tell us how you want it to behave and we'll figure out what you intended the hardware to look like" method of inferring hardware from HDL. I've not used HDL on CPLDs (only FPGAs) yet, so don't know how efficient it is, or how often you need to write stuff in specific ways to make it do what you know the simple(ish) hardware will do.

author: free_electron
author_rank: Super Contributor
timestamp: November 23, 2012, 08:41:04 pm
content: Quote from: mikeselectricstuff on November 23, 2012, 07:36:39 pmAh, that's because of three things1) nobody explained you how a logic synthesizer works2) nobody explained you how to use the synthesizer to do EXACTLY what you want it to do.3) nobody explains what scheduling is. It is the most powerful part of both Verilog and VHDL yet it is almost never covered ... For some reason they want to teach you procedural programming and treating this as a software language bolted on hardware. Scheduling is the real hardware access.I agree that most logic course, if not all, handle only the abstract part. There is ZILCH attention to the synthesis part. There are two extremely good books that can teach you how it works:Bhasker's Verilog HDL for Synthesis <- make sure you get this one. he has another one that is just plain verilogSmith's HDL programming. This one is out of print. it is a humongous book printed on A4 format that covers Verilog and VHDL side by side. it contains tons of examples and shows you the schematic output for each of the constructs. it pops up from time to time used on amazon but is very expensive.In short :Here is how a synthesizer works :Code:module counter (input [3:0] data_in, input clk,reset,load,preset, output reg [3:0] data_out)i just defined a counter that has a bunch of inputs and outputs : data_in0 to data_in3 , clk reset load preset and the 4 outputs data_out0 to data_out3The synthesizer reads this block and plonks down the inputs and outputs. since the outputs are defined as REG it will plonk down a flipflop per output and tie the Q output to the pin.Code:module counter (input [3:0] data_in, input clk,reset,load,preset, output reg [3:0] data_out)always @(posedge clk) begindata_out<=data_out +1;if (preset) data_out <=9;if (load) data_out <=data_in;if (reset) data_out <=0;endendmodulethe synthesizer reads the next line : always if you see a rising edge of CLK you need to do something. so it will take CLK and connect it to the flipflops already placed ( the output ones) it does not do anything else as it has not had any other instructions.then it reads the next line : data_out = data_out + 1.so it will take the output of the flipflops , send them through an adder logic and feed that back to the D inputs of the flipflops.then it reads the next line if "(preset)" so it plonks down a multiplexer under control of the preset signal. and it reads on "data_out <= 9"so it snips off the wires going to the flipflop's D input and connects them through the multitplexer. if preset is 0 then the mulitplexer connects A to X so whatever logic was already created still works perfectly fine. if preset is 1 then the B input is connected to X and the descirption said to apply '9' in this case. so it hardwires 1001 to that mux input. done.next line : if (load) data_out <= data_in. ah. we snip off the data_inputs of the flipflops again and throw in another mux the A inouts come from whatever was there , the B inputs get tied to Data_inso essentially you keep cascading multiplexers. multiplexers are a very simple logic equation A.EN + B.not(EN)so this cascade of multiplexers becomes a very simple logic equasion after minimizing. there are no secrets, no hidden paths. everything is defined and it will work exactly as you have described it.

author: djsb
author_rank: Super Contributor
timestamp: November 24, 2012, 11:29:17 pm
content: Have you got the full title of the Smith's HDL programming book mentioned above? Is this the same book that Jeri Ellsworth mentions in one of her youtube video's?I keep trying to learn this stuff too.David.

author: mark2112
author_rank: Contributor
timestamp: November 25, 2012, 10:49:10 pm
content: Quote from: free_electron on November 23, 2012, 08:41:04 pmThere are also some great resources available from the FPGA vendors themselves, dealing with how best to write HDL for use with their logic synthesizers:AlteraRecommended HDL Coding StylesXilinxHDL Coding Practices to Accelerate Design PerformanceGet Smart About Reset: Think Local, Not GlobalGet your Priorities Right – Make your Design Up to 50% SmallerMost of the hardware you describe for an FPGA gets implemented using configurable LUT (look-up table) and FF (flip-flop) elements. These elements are configurable, but they have some limitations! An awareness of these limitations can allow you to write HDL that will yield smaller, faster hardware when run through synthesis. For example, the last Xilinx white paper I listed talks about how to properly set the priorities of signals in a VHDL process.Here are two code snippets from the paper. Below is a process with 4 logic inputs (a,b,c,d), along with register control signals (set, reset, and a clock enable). Looks perfectly reasonable, right?Code:process (clk)beginif clk’event and clk=’1’ thenif reset=’1’ thendata_out <= ’0’;elseif enable=’1’ thenif force_high=’1’ thendata_out <= ’1’;elsedata_out <= a and b and c and d;end if;end if;end if;end if;end process;Compiling this code in Xilinx XST will consume two LUTs and one FF.Code:process (clk)beginif clk’event and clk=’1’ thenif reset=’1’ thendata_out <= ’0’;elseif force_high=’1’ thendata_out <= ’1’;elseif enable=’1’ thendata_out <= a and b and c and d;end if;end if;end if;end if;end process;The above code has the same register control signals in a slightly different priority. This code will consume only one LUT and one FF! Why is this?While the LUTs and FFs are configurable, they have some limitations. The FF elements inside Xilinx FPGAs have (alongside data-in), extra inputs for reset, set and clock enable, but these have a fixed signal priority:- reset has highest priority- set has second priority- clock enable has lowest priority(These priorities vary with vendor, device family, etc. Check the documentation for your programmable logic device!)If you describe a process that does not agree with this priority, then this behavior you described will be emulated using additional LUTs (rather than using the extra inputs on the FF element). The hardware you described will certainly work, but it will consume more resources and will have a lower operating frequency. And this is just one example! Read those papers for a lot more!

author: dfnr2
author_rank: Regular Contributor
timestamp: November 26, 2012, 07:12:20 pm
content: Those are really useful links. I think the principle is the same as f_e is talking about above. I actually prefer his more succinct notation--I think it is easier to understand at a glance, and probably easier to get right and to optimize.