Best practices for glue logic for surface mount components? - Page 1
Forum section: electronics / beginners

author: MrD
author_rank: Contributor
timestamp: October 27, 2019, 10:40:16 pm
content: I'm designing my first surface mount board (used to through-hole hand soldered projects) and I've got a question about glue logic.In my schematics, I've got my signals from node to node combined through logic gates: address decoding, device selection, transceiver direction selection etc. My first project has a few 3-input OR gates, some 2-input NANDs, some 2-input ANDs, and runs at 3.3V.Is it best to implement these with single gate devices like74LVC1G00GW,125, minimizing trace length as much as I can, resolving signals into their final useful form as early and as locally as possible, etc? Or should I be trying to look for surface mount versions of the multi-gate 74 series devices and minimizing the component count instead of having lots of small gates dotted about the board?Advice or links to reading material appreciated

author: tautech
author_rank: Super Contributor
timestamp: October 27, 2019, 10:51:26 pm
content: Routing for multi gate SMD packages is always the issue as you don't have the room to slip traces between pads like you do with DIP however reassigning gates to best suit routing can be the savoir with SMD.Using multi gate packages will certainly keep your board more compact if you're prepared to spend the time on routing.I break it down to circuit blocks and then arrange them to get best routing and when that doesn't work reassign gates to get the result required. I'll even drop in a TH resistor so to provide pathways for routing but you can do the same with big SMD resistors or zero ohm links, even a wire jumper if you're desperate.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 28, 2019, 12:56:50 am
content: Just use however many you need. If the required gates pack into quads effectively, go for quads. Note you can get duals of 2-in's and triples of 1-in's in the "tiny" formats. (And maybe there's duals of 3-in's and triples of 2-in's, I don't recall offhand.)Singles are irritating for the relative wasted space and extra power/ground routing (which goes away if you're using 4-layer with VDD/VSS internal layers) so strike a balance between both extremes.Tim

author: MrD
author_rank: Contributor
timestamp: October 28, 2019, 02:13:01 pm
content: Thank you both, I'll let you know how it goes. It did seem strange to be able to select single gates, but if that's how it goes...

author: NivagSwerdna
author_rank: Super Contributor
timestamp: October 28, 2019, 03:07:15 pm
content: As above. Try and minimise number of packages unless there are cost reasons not to. Where you have unused gates follow the datasheet rather than just let them float.

author: tggzzz
author_rank: Super Contributor
timestamp: October 28, 2019, 05:28:40 pm
content: I like the 74lvc series, but the output is fast and has a high drive current.Make sure you have adequate decoupling, and preferably a ground plane.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 28, 2019, 05:45:44 pm
content: Yeah, worth mentioning. I prefer 74HC where possible, the transition speed and propagation delay are reasonable. Where you need speed, or have limited choice of family in a type of gate, the 74LVC (and TinyLogic equivalents, I forget which families) are probably next best.You may have such a decision here, i.e. needing speed over ease, so choose accordingly.LVC is fast enough that you may need to take signal quality precautions (termination resistors, filtering, local bypass) even for on-board signals. HC you usually don't have to worry about this until much longer lengths (i.e., by the time a signal has to leave the board on a cable).LVC is rated for 5V, but I think may not be reliable up there? Prefer 3.3V or less, if you have the option.LVC also lacks VDD side ESD diodes, which is nice for power management with bus applications (powered-down devices won't load the bus), and great for level shifting (a 3.3V gate will receive a 5V signal just fine), but use it carefully when receiving external signals -- don't forget to add clamping and filtering.Tim

author: tggzzz
author_rank: Super Contributor
timestamp: October 28, 2019, 06:01:53 pm
content: Quote from: T3sl4co1l on October 28, 2019, 05:45:44 pm(Snipped good points about HC)What might be the source of such unreliability? Just overshoot and the lack of ESD diodes, or other factors?

author: wraper
author_rank: Unknown
timestamp: October 28, 2019, 06:07:58 pm
content: Quote from: T3sl4co1l on October 28, 2019, 05:45:44 pmIf there are no high side diodes to VDD does not mean there is no clamping. It just means that clamping is made differently to allow input voltage to exceed VDD.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 29, 2019, 02:09:44 am
content: Yeah, they use a zener (or something like that; it might actually be a snapback diode structure for example) so it still meets whatever ESD rating it does.I forget where I read it, but it may be that there is aging due to hot carriers, or electromigration, at high voltages? Will have to find that again.If nothing else, the peak current flow (during transition) is that much higher, on a chip that's already pretty fast, so it invites more problems with switching noise.Tim

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: October 29, 2019, 04:26:33 am
content: Quote from: tautech on October 27, 2019, 10:51:26 pm1.27mm SOIC footprints, with 0.6mm wide pads, leaves a whole 0.57mm between pads. There's room enough for one trace on a 7.5mil design rule, and a very high probability the board house will leave the solder mask on top of it.