2.4GHz RF pcb layout - your judgement is welcomed - Page 1
Forum section: electronics / rf-microwave

author: ck4t5e
author_rank: Newbie
timestamp: January 17, 2021, 11:56:17 am
content: Hello,I designed a pcb around the STM32WB55CE (https://www.mouser.de/datasheet/2/389/stm32wb55cc-1588841.pdf). The RF design is meant the capabilities needed for 2.4GHz bluetooth. I looked at the available AN's and did my first shot with the design. Please keep in mind, that this is my first RF circuitry.For the RF matching, I chose the IC provided by STM (https://www.mouser.de/datasheet/2/389/mlpf_wb55_01e3-1551209.pdf). As an antenna I thought I'd go with a ceramic one, because I want the pcb to be small and also reliable.For the PCB itself, it's a 4 layer stackup (see the attached pictures) with:top layer(red) -> signals + groundinner layer 1(yellow) -> ground planeinner layer 2(orange) -> power planebottom layer(blue) -> ground + signalingThe area around the antenna that is suggested to be kept free of metal is the silkscreen on the pcb pictures.In general the bluetooth should work only within 2-3 metres.The signals that are broken out are all digital with 3 exceptions. PA10, PA11, and PA12 will be used for analog readings .Is it likely that it'll boot with the RF working ?Any suggestions are appreciated-c

author: AE7OO
author_rank: Regular Contributor
timestamp: January 18, 2021, 11:47:47 pm
content: Greetings,This is just off the top of my head. I'll post a more detailed answer after I look at the data sheet(I added edits for things that I should have included to begin with).I also have some samples of this part and all of the design docs that STM put up as of about May of last year.Correction, I have samples and design docs for the STBlueNRG series, but that's close enough.Before anything else, please include the BOM for this board.A) Run both a ERC and DRC check. With any decent ruleset it should catch the major errors.B) From what I can see, you have VERY little isolation between those pins on your breakout and GND.1) I would loose the thermals from the top layer.2)Unless I'm reading these diagrams wrong, it seems like a LARGE number of your vias from your first layer do not connect to any other layer. I'm making the assumption here that black means no copper.I had to zoom in on the diagrams to see the vast majority of the connections As an example, your 3.3V connection to your power layer, what size are thoseTINYconductors? The same also applies to your GND on that same connector.3) I'm fairly sure that the MCU uses that ground pad as a heat sink. You need some vias here as heat pipes, top to bottom.Unless the design documents call for a ground island here,You need those vias to connect to ground.4) You really need more vias tying the grounds together. RF is not like DC. It is for just this reason that I save my used de-soldering wick. On my one off boards, I fold it around the edges of the board, and it gives a low inductance connection between the two sides(I also have multiple vias over the board). As it is, I suspect that you have more than one antenna on that board and that means noise, lots of noise.5) I would make sure that the size and shape of your vias are consistent between layers.The vast majority of time your best bet when your dealing with RF(especially above HF) is to copy the chip makers demo board as much as you can.Unless I'm mistaken, the Gerber's for the '55's demo board are available for download.They do have the design files for various reference boards availablehttps://www.st.com/en/microcontrollers-microprocessors/stm32wb-series.html#cad-resourcesPlease check outhttps://www.st.com/resource/en/application_note/dm00504903-development-of-rf-hardware-using-stm32wb-microcontrollers-stmicroelectronics.pdf, this is the hardware bible for these MCUs.Now mind you I'm not an RF Engineer, just an ET(with delusions of grandeur I like to say) who has been working with RF for long time.GBAE7OO

author: ck4t5e
author_rank: Newbie
timestamp: January 19, 2021, 11:36:35 am
content: Hey,Thanks for the thoughts.A) Yes there are errors, but all of them are neglectable. Maybe an important information would be that I plan to manufacture them at JLCPCB. I adjusted the DRC to be compatible with their requirements. The ERC says that PB3 and PA5 have only 1 pin in their net. Which is expected, because I break them out with a via only. I don't want them to be on a pin, because I don't need them that often. If I need them at all I will solder a thin wire to the via. The DRC doesn't complain about anything really. The thing it's not happy with is only stuff which is unrelated to manufacturing problems. For example I placed vias on the big ground pad of the STM32WB. But that's only bad for the DRC, because it's not how you should do it in Eagle, but you can.B) I'm not positive what exactly you mean. The board is operating at 3.3V, is it a problem that the ground pin is close to a data pin for example ? The board will also be coated in a soldermask. Doesn't that help a little ?1) I don't think I had any thermals in the design presented above. I mean, not consciously2) I guess you are talking about the vias ? The drill size of all of them are 0.35mm, which is well above the 0.2mm for multilayer pcb, JLCPCB can manufacture. The other throughhole connections are for standart pin header. But I may have misunderstood that ^^3) Yes!, thank you for pointing that out.4) I would like to place more ground vias, but the space is getting tight. But I think I will shield the board to ground. That way the noise shouldn't be a problem, right ?5) They should be already ?Did you find any inconsistency in that ?NOTE: I redesigned the board according to your suggestions, and a few suggestions from other people aswell. I will attach the new board here. The main difference is that I will use a pcb antenna, as oppsed to a chip antenna. Since I read that a chip antenna needs to be free of metal "left" and "right" of it, it doesn't save a lot of space anyway. But any thoughts about which antenna of those both to use are appreciated. Another thing I did is, I placed the capacitors a little bit nearer to the board, since someone pointed out that the HSE doesn't need that much space.NOTE2: I also plan to use the option to get a 1mm board thickness PCB at JLCPCB. I think that would make the trace going to the antenna neglectable, and I don't need to match the trace to 50 ohms. Any thoughts on that ?-c

author: ck4t5e
author_rank: Newbie
timestamp: January 19, 2021, 02:54:18 pm
content: Here is a picture of how I would do the shielding. The pin headers I would solder upside down. So that way, the shorter pins are on the top side and the shield fits hopefully.-c

author: richard.cs
author_rank: Super Contributor
timestamp: January 19, 2021, 03:53:15 pm
content: Looking at your top layer I am dubious about how close your top GND comes to the RF tracks. Your RF tracks are short enough that it barely matters, but having ground come in so close adds capacitance and lowers the impedance. Or have you calculated it as co-planar waveguide rather than microstrip?The end of your PCB antenna, which is a high-impedance point because it's a monopole, also comes very close to the GND planes of the board. It is possible that is intentional and intended to act as a little bit of top-loading, but check how that compares to the reference design for that antenna - that small gap and the consequent capacitance between antenna end and GND will have a significant effect on tuning.You could do with more ground vias local to your top-side components. Supply decoupling for the chip could stand some improvement, both adding local vias to the GND side of the capacitors and fatter, lower-impedance tracks to the supply pins of the chip, though it is probably good-enough to work.Finally I would always put pads for matching components at your antenna feed, perhaps two no-fit 0402s and a 0R as a pi network. Then you can use it for antenna tuning if you need it.

author: Gribo
author_rank: Frequent Contributor
timestamp: January 19, 2021, 03:56:10 pm
content: One point: You want the antenna GND connection to be solid, you don't need thermal relief with a trace antenna. Also, that via there adds inductance which you don't really need.

author: ck4t5e
author_rank: Newbie
timestamp: January 19, 2021, 08:35:33 pm
content: Alright, so I changed some things according to your suggestions.1.) pulled the top GND layer down to where it's supposed to be. The antenna, had a marking for where the ground should start.2.) removed the via at the end of the antenna (to remove the additional inductance) and connected it to the ground plane.3.) added some local ground vias, and I also did a shielding track to add a shield later on. The vias on the track hopefully act as the local vias for the cap bank on the left. Does it work, or is it too far away ?4.) made the supply traces fatter.