Poor man's FPGA DAC - Page 1
Forum section: electronics / general

author: nimish
author_rank: Regular Contributor
timestamp: August 18, 2022, 09:02:04 pm
content: Has anyone used a high-speed fpga serdes (xilinx GTX, GTH) as an ad-hoc 1 bit DAC? I have some wasted serdes that I'd like to use to synthesize < 150MHz sine waves with low jitterI know xilinx has a an app note that shows how to use them as precision clock cleaners/VCXO:https://support.xilinx.com/s/article/56136?language=en_USso I figure there's some way to hack them to work.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 18, 2022, 09:22:00 pm
content: Nope but that should be doable.I have implemented sigma-delta DACs on FPGA just using regular IOs, for higher sample rate, yes I guess I could just aggregate the output in wider chunks and pass it to a SERDES.Thing is, the sigma-delta part would have to run fast enough and would probably need to be written differently.

author: langwadt
author_rank: Super Contributor
timestamp: August 18, 2022, 09:30:23 pm
content: Quote from: SiliconWizard on August 18, 2022, 09:22:00 pmcould possible make the sigma-delta with multi bit output and the turn those bits into PWM

author: tom66
author_rank: Super Contributor
timestamp: August 18, 2022, 10:01:51 pm
content: A friend of mine had an idea similar to this using MASH (noise shaping, essentially) to shift as much of the D-S noise into the high frequency domain. It doesn't seem to be widely used outside of audio, but I'd be curious how well it works for a DDS.A mid-performance FPGA can easily get 1.5Gbit/s on a pin, so a pair of pins driving a 2-bit current source could presumably get ~12 bit resolution at ~20MHz -- approaching a low-end DDS generator.

author: tszaboo
author_rank: Super Contributor
timestamp: August 18, 2022, 10:03:20 pm
content: Given, that an FPGA usually has more pins than needed, an R-2R DAC makes sense.We did that with 4 bit R-2R, generating VGA signal for monitors, Spartan 3, so it wasn't even that fast. That's ballpark the same frequency.

author: BrianHG
author_rank: Super Contributor
timestamp: August 18, 2022, 11:08:54 pm
content: Quote from: tszaboo on August 18, 2022, 10:03:20 pmA simple R2R dac for a 150Mhz sine wave?Good luck on flatness, overtone, third harmonics, power supply interference adjacent pin cross-talk, ground bounce...

author: Someone
author_rank: Super Contributor
timestamp: August 19, 2022, 12:32:10 am
content: Quote from: BrianHG on August 18, 2022, 11:08:54 pmBut at the same time, the serdes is optimized for eye opening (usually with rounded/slewed edges) so is going to be hard to treat as a perfect output for a modulator. I tested some Xilinx OSERDES for DAC use and they were already worse than ODDR for lower frequency (128x oversampling) content.As in previous threads....https://www.eevblog.com/forum/projects/generating-a-clean-10khz-sine-wave-from-pwm/?allIf its only a single (or narrow) frequency sine, get out the textbooks and design a bandpass filter, together with modulation. They are multiplicative effects.

author: nimish
author_rank: Regular Contributor
timestamp: August 19, 2022, 02:20:56 am
content: They are 12.5Gbps (maybe 16 ish) SERDES. Bandwidth is 1Hz -- just need the pure tone or a very narrow approximation thereof.PDM seems fine. I don't think the transmitter would like PWM, doesn't it need transitions for DC balance?Seems wasteful to not use the very powerful PLLs and such baked into the chip.

author: betocool
author_rank: Regular Contributor
timestamp: August 20, 2022, 03:49:08 am
content: I just finished about a week ago a PDM DAC running at 49 MHz on a Cyclone IV. The input is 48 KHz. Mind you, I have not yet filtered the incoming 48KHz, instead just squarely extended it.It works, that's all about I can say without going into the possibly woeful performance of a first pass try. I will get a FIR filter running in some time, and lower the output frequency to 6.144 MHz (48KHz x128) to try a few things out.Here's the code if you're interested (based on a 0x0 - 0xFFFF 16 bit value).Code:PDM_process: process(dac_clk_i, dac_enable, data_fifo_out, err)beginif(dac_enable = '0') thendac_pdm_o <= '0';err <= X"0000";y_out <= X"0000";elseif(rising_edge(dac_clk_i)) thenif (unsigned(data_fifo_out) >= unsigned(err)) thendac_pdm_o <= '1';y_out <= X"FFFF";elsedac_pdm_o <= '0';y_out <= X"0000";end if;err <= std_ulogic_vector(unsigned(err) + unsigned(y_out) - unsigned(data_fifo_out));end if;end if;end process;I got an image somewhere from a scope... nothing to boast though...Cheers,Alberto

author: tszaboo
author_rank: Super Contributor
timestamp: August 21, 2022, 08:52:55 pm
content: Quote from: BrianHG on August 18, 2022, 11:08:54 pmThe same issues arise using one pin, or similar issues. Plus jitter, eye diagram cleanness, difference for rise and fall times, etc.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: August 25, 2022, 08:26:16 pm
content: This topic was discussed here a while back:https://www.eevblog.com/forum/fpga/artix-7-gtp-transceiver-as-delta-sigma-dac/At that frequency you might want to consider doing what a lot of RF equipment does. Take the square wave and filter the odd harmonics.

author: dmendesf
author_rank: Frequent Contributor
timestamp: August 25, 2022, 11:18:01 pm
content: If you want a single frequency output then SHE (selective harmonic elimination) is a better idea. You can see a dumbed down version by looking for "Magic Sines" from Don Lancaster.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 25, 2022, 11:25:45 pm
content: For a fixed frequency output, you can also (better because more flexible) just generate the 1-bit sequence for one whole period of sine outside of the FPGA, store it in EBR and replay the sequence in loop through a SERDES. That eliminates the issue of running a sigma-delta DAC in real-time @several GHz.

author: dmendesf
author_rank: Frequent Contributor
timestamp: August 25, 2022, 11:59:37 pm
content: That's the idea with SHE (generate a bitstream offline, play It endlessy). SHE is just a way to generate the bitstream minimizing the low order harmonics.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: August 26, 2022, 03:45:49 pm
content: Quote from: SiliconWizard on August 25, 2022, 11:25:45 pmI like this. Then just adjust the clock driving the output to get the output frequency you want.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 26, 2022, 06:25:42 pm
content: Quote from: dmendesf on August 25, 2022, 11:59:37 pmOh, OK. I don't know much about SHE, so I'm not sure about the benefit here, for generating bitstreamsoffline. If you have any reference material...I would personally just implement a sigma-delta modulator (that then can be made as good as required) in C (use your preferred language) and generate bitstreams for a specific frequency (and possibly amplitude too) for single periods. The nice thing with this approach is that it can be used for actually any periodic signal, as long as the required number of samples for a period is within what's available on your FPGA in terms of EBR.

author: dmendesf
author_rank: Frequent Contributor
timestamp: August 26, 2022, 11:25:53 pm
content: The fundamental Idea is as follows: Sigma-delta is a simple enough algorithm that can be used in real time to compute a bitstream with the same low order harmonics than the input waveform, shifting the imperfections to higher harmonics that will be filtered with a low pass filter. Assuming the input waveform is a sinewave, SHE is a way to compute a better bitstream but it's very computationally intensive so usually done offline. A good reference:https://vtechworks.lib.vt.edu/bitstream/handle/10919/35333/Chapter4.pdf%3Fsequence%3D5&ved=2ahUKEwj9p7bVzOX5AhWMGbkGHZlmDSYQFnoECDQQAQ&usg=AOvVaw2oHwFneCGJRmEQEH-YQgwK

author: SMB784
author_rank: Frequent Contributor
timestamp: August 27, 2022, 12:34:10 am
content: A ways back I implemented my own second order Sigma-Delta DAC (with CIC low pass filter for test benching) in verilog. All of the code is provided in the link below, and some performance verifications are provided in the subsequent posts:https://www.eevblog.com/forum/fpga/2nd-sigma-delta-digital-to-analogue-converter-(sd-dac)-in-verilog/msg3119924/#msg3119924