Math in VHDL - Page 1
Forum section: electronics / general

author: hamster_nz
author_rank: Super Contributor
timestamp: August 03, 2016, 09:12:58 pm
content: If anybody is starting out with VHDL and is finding math confusing, or wants a refresher with a few tricks, have a look at:http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdfI quite liked this one - addition with carry in:Rather thanCode:Y <= A + B + CarryIn;Use this (where Y5 is a variable one bit longer then Y):Code:Y5 := (A & '1') + (B & CarryIn);Y <= Y5(4 downto 1) ;I'm going to have to try it tonight to see if it the tools do this for you auto-magically anyway, rather than using two adders.

author: nctnico
author_rank: Super Contributor
timestamp: August 03, 2016, 09:35:35 pm
content: In a modern FPGA you have DSP slices which can do this (and a whole lot more) in one clock cycle. Recently I did an FPGA project with involved some 2's complement math (filtering / scaling) and the synthesizer optimised it just fine without needing this kind of obfustigation.

author: hamster_nz
author_rank: Super Contributor
timestamp: August 03, 2016, 09:58:14 pm
content: Quote from: nctnico on August 03, 2016, 09:35:35 pmYeah, but a DSP slice is a limited resource on hobby-sized FPGAs, and it seems a waste to use one of them to add a couple of 4 bit numbers. The proof of the pudding will be in the eating tonight, when I see how it synthesizes...

author: Kilrah
author_rank: Unknown
timestamp: August 03, 2016, 10:01:53 pm
content: Obviously if you used all of your DSPs that could go to better use it would be kinda stupid, but on the other hand if they're sitting there unused why not make advantage of them.I.e. we're not in your design and don't even know what architecture you're using, advice is pointless.

author: nctnico
author_rank: Super Contributor
timestamp: August 03, 2016, 10:07:39 pm
content: And even if the expression is synthesized into two adders made from generic logic the optimisation phase will deal with the excess logic.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: August 03, 2016, 10:44:32 pm
content: Quote from: hamster_nz on August 03, 2016, 09:58:14 pmEven the low-end Artix has 45 DSP slices. Use 'em or lose 'em.

author: hamster_nz
author_rank: Super Contributor
timestamp: August 03, 2016, 11:32:21 pm
content: At least at the synth stage it does give you a different design depending on what you ask for,However, as expected during implementation this gets optimized away. I wonder if this would always be the case.I am going to have to play a bit with the SIMD modes on the Xilinx DSP48E slices a little more. (The carry chains in the 1 x 48-bit adder in the DSP block can be split to give 2 x 24-bit adders or 4 x 12-bit adders)....

author: Someone
author_rank: Super Contributor
timestamp: August 04, 2016, 04:26:24 am
content: Quote from: hamster_nz on August 03, 2016, 09:58:14 pmThe carry in resources of fabric adders are routable on modern FPGAs, and xilinx went one further to support compact ternary adders:http://www.google.com/patents/US7274211Don't add complexity unless its needed, just like compilers, synthesis and mapping optimisation is almost always better than you are at optimising maths.

author: legacy
author_rank: Super Contributor
timestamp: August 04, 2016, 07:29:35 am
content: Quote from: nctnico on August 03, 2016, 09:35:35 pmit's not obfuscation, it's a low level way, also the ghdl simulation has some trouble with those DSP-slice's tricksI prefer the low level way, when rationally applicable

author: exmadscientist
author_rank: Frequent Contributor
timestamp: August 04, 2016, 04:53:57 pm
content: In my experience and opinion, the DSP slices are not worth wasting on any operation that doesn't involve a multiply. Adders are very well suited to implementation and optimization in the device fabric. Multipliers, not so much.The best way to do it is to write the code in the clearest possible way, so it is easiest to understand and maintain. The tools will optimize it for you; they really do manage a good job of it. If you need a DSP slice, whenever possible just write it naturally and let the tools infer a DSP slice for you. This may involve contorting your specific signals and data flow a bit, but it's no worse than an explicit implementation. Only bother doing it explicitly if the tools aren't understanding what you need or are doing something stupid.