HaasoscopePro open-source 2 GHz oscilloscope! - Page 1
Forum section: electronics / general

author: haastyle
author_rank: Regular Contributor
timestamp: November 22, 2024, 05:40:49 am
content: You may recall the infamous Haasoscope, king of the worst schematics in history. (Dave did a 2 hour video based on it, just to explain how NOT to draw a schematic!)Well I've learned a bit in the past 6 years, and now I've designed the Haasoscope Pro, quite the upgrade - now with 2 GHz of analog bandwidth. Each has 3.2 GS/s, but (before you go all Nyquist on me), you can sync 2 of them, to get to 6.4 GS/s interleaved.It's now in pre-launch on CrowdSupply...https://www.crowdsupply.com/andy-haas/haasoscope-proSign up there with your email to get updates as the project launches (next month?), and get first dibs on the introductory pricing for early backers.All the designs are athttps://github.com/drandyhaas/HaasoscopePro/Let me know what you think... What could be added or changed... Skepticisms about whether it could actually work... 😁

author: lfldp
author_rank: Regular Contributor
timestamp: December 22, 2024, 10:25:33 am
content: Quote from: haastyle on November 22, 2024, 05:40:49 amVery interesting project, I wanted to ask a few questions related to it. Do you plan to add a 10mhz clk input to synchronize signals from tested devices? If not, is the current hardware version of this oscilloscope suitable for such a modification? Can you give an estimated cost of making 5 pieces of pcb in JLPCB? Is making them very expensive? Does this pcb have to have gold-plated paths?

author: nctnico
author_rank: Super Contributor
timestamp: December 29, 2024, 02:31:32 pm
content: The schematics are still horrible! The key to good schematics is to connect the signals so people can follow the signal flow. Stuff like power and SPI / I2C can be put on a schematic as labels (or made part of a bus) but the signals should really be drawn between the parts in a schematic.

author: haastyle
author_rank: Regular Contributor
timestamp: January 02, 2025, 11:13:49 pm
content: Quote from: nctnico on December 29, 2024, 02:31:32 pmPlease look at the latest ones. They've come a long way.https://github.com/drandyhaas/HaasoscopePro/blob/main/adc%20board%2Fhaasoscope_pro_adc_fpga_board_schematics.pdfI'm happy to take specific suggestions!

author: haastyle
author_rank: Regular Contributor
timestamp: January 02, 2025, 11:41:33 pm
content: Quote from: lfldp on December 22, 2024, 10:25:33 amThanks. There is an external trigger in (SMA on back panel), which could be driven with an external 10 MHz square wave. You would then still be triggering off of the internal ADC clock (800 MHz), but immediately after an edge of your 10 MHz clock. So you'd have ~1 ns of jitter with respect to your external 10 MHz clock edges.If that is not acceptable jitter performance, there is an external clock input (SMA) that could be used to drive the whole scope, replacing the 50 MHz oscillator on board. But I hadn't planned to route that connection to the back (or front) panel. It's just sitting next to the FPGA.I'm actually not so familiar with the use cases where syncing with an external device is required, or the specifications of such a setup. Can you elaborate on your setup and requirements please?The PCBs are not expensive, 5 of them cost about $300. This was only possible by completing the routing on "only" 10 layers, and without blind or buried vias. Not easy, given the 1mm and 0.8mm BGAs with 16x16=256 and 22x22=484 pins, and 56+8 LVDS pairs needed! I *think* you're joking about gold-plated paths - there is standard gold-plated ENIG finish on the boards, but that's not very costly. The usual FR4 does just fine up to a few GHz. Of course you want to specify the stack up and design the traces (and differential traces) to be 50 Ohm, but nothing special is required.The main cost of the device is the components. Things with 2+ GHz of bandwidth are not cheap. The ADC alone is $180, in quantity 100. Even the relays are $15 each. But it's still going to be *much* cheaper than any other scope out there with 2 GHz bandwidth. Pricing will be announced soon when the CrowdSupply campaign goes live. And early supporters will get a good discount. Sign up on that page for updates.

author: PlainName
author_rank: Super Contributor
timestamp: January 03, 2025, 09:51:33 pm
content: Quote from: haastyle on January 02, 2025, 11:13:49 pmI had a (very) quick look before giving up. On page 3 there is an airwire 'INPATH2' which goes... where? Surely not to INPATH24. Then OUTPATH2 on K4 goes to OUTPATH2 on K5, but there is white space taken up by an arrow which would be better served as a wire connecting OUTPATH2/K4 to OUTPATH2/K5 - it is literally a straight line of minimal length. Instead ofeasilyseeing that one is connected to the other, I had to look over the entire sheet to a) find the connection, and b) make sure that was the only connection (but maybe the airwire connects on another sheet?).Air caps with airwires to power. Just join the + and - rails. They are right next to each other after all! And if they must physically sit close to the relevant chip/relay/ whatever then either directly connect them thus (so it is obvious) or put a note by them.Q4 and Q5 - what drives them and what do they drive? Is it on this sheet? Life's too short to try and find out.I suspect there are quite a few more things to be found on that sheet, and then there are another five similar sheets. I think you still have quite a way to go, sorry.

author: KE5FX
author_rank: Super Contributor
timestamp: January 03, 2025, 11:05:54 pm
content: Quote from: haastyle on January 02, 2025, 11:13:49 pmIgnore further suggestions, at least of this particular nature, and ship it.Your schematics are fine.

author: haastyle
author_rank: Regular Contributor
timestamp: January 04, 2025, 03:57:50 am
content: I made some fixes along the lines you suggest. Have another look if you dare. Thanks for your feedback.There are unfortunately a ton of control lines coming from the FPGA that simply must be on another sheet. Not sure how to indicate that's where they come from, other than with some text.

author: PlainName
author_rank: Super Contributor
timestamp: January 04, 2025, 10:44:16 am
content: IMO that simple change has made it much better - the flow straight through is obvious at a glance. I would suggest connecting the transistor wires to the relays instead of having them floating. It's not like you pay extra to have lines cross, and the won't create an unholy mess. Instead, you won't even have to think what they are doing or what to.QuoteSure, that's normal for a decent project. This is with Kicad, right? I am not au fait with it's capabilities but with other packages you would have off-sheet ports. If you must have airwires on a sheet (sometimes it is complex enough to warrant a couple) then differentiating on-sheet and off-sheet connections would mitigate the airwire issue a lot.Where you split a project into multiple sheets, if you can compartmentalise the sheets then a top level overview sheet helps to manage things. That will show sheet to sheet connections and will dramatically simplify things for the schematic reader. The problem you have here is a huge number of I/O on the FPGA, and consequently the connections between sheets can make the top level look like it needs airwires. But this isn't unusual and the normal resolution is to use buses. A bus would work well if you have many lines going from, say, sheet A to sheet B and keep the top level clean but informative.

author: tggzzz
author_rank: Super Contributor
timestamp: January 04, 2025, 11:22:46 am
content: Here'soneold-school way of doing it for a 350MHz scope.Key techniques (which are explained in the manual)each schematic is alogicalcomponent, and is implemented on several boards and the front panelthe numbers in the diamonds refer to schematics number. This is schematic 9a boundary line indicates what's on each board, the board name is given next to the boundary lineconnections going elsewhere are shown "penetrating" the boundary linesconnections going to other schematics are annotated with where to find the "other end"connections going off-board are annotate with the connector and pinother annotations indicate circuit operationnote how complex mechanical components (relays, switches) are shown in a way that does not hide the circuit's overall operationCoupled with the explanation of the circuit in the manual, all of that makes itveryeasy to visualise how the circuit works.I understand that some modern tools may actively thwart such understanding. That is unfortunate.

author: haastyle
author_rank: Regular Contributor
timestamp: January 04, 2025, 02:51:02 pm
content: Ok, I connected the relay signals, and some others. Thanks.I also figured out how to do PORT symbols in Eagle, to show which signals are coming or going from other sheets. I haven't added them on all sheets yet - it will take a while.Updated the pdf in GitHub.

author: Kean
author_rank: Unknown
timestamp: January 05, 2025, 07:46:10 am
content: If you are using Eagle, there is also a setting to display page & grid coordinates on the PORT symbol for cross referencing. A PORT is typically intended for use as a label with Xref enabled.Of course, for that to be useful you will need to add a frame to each page with the grid style. I think a frame does generally make a schematic look better organised, and it also helps you to more effectively use the page canvas so that it can be printed at a readable size.

author: PlainName
author_rank: Super Contributor
timestamp: January 05, 2025, 09:20:39 am
content: QuoteNot to mention that you can see the limits of where to search for things (that, perhaps, something is hidden because it is off-screen).

author: haastyle
author_rank: Regular Contributor
timestamp: January 05, 2025, 04:44:45 pm
content: Ok, thanks for the suggestions!I added frames and the "next sheet number" on the xref labels.I'm still adding more xref labels, but I think this is a good start.https://github.com/drandyhaas/HaasoscopePro/blob/main/adc%20board%2Fhaasoscope_pro_adc_fpga_board_schematics.pdf

author: PlainName
author_rank: Super Contributor
timestamp: January 05, 2025, 05:06:47 pm
content: Much nicer job

author: Kean
author_rank: Unknown
timestamp: January 06, 2025, 02:49:26 pm
content: Yes!I think that has made a significant improvement to first impressions and overall readability, and believe that it will help when you officially launch the project on CS.

author: lfldp
author_rank: Regular Contributor
timestamp: February 02, 2025, 08:15:44 pm
content: Quote from: haastyle on January 02, 2025, 11:41:33 pmQuoteSome oscilloscopes are equipped with ext clk input. This allows you to synchronize the clock of the device under test, which is supposed to allow for a lower demand for sampling rate. One such oscilloscope is the rigol DHXXX series. That's why I asked. So I would have to connect the clock of the device under test to the point where the signal from the 50mhz oscillator reaches the pcb from your project?QuoteI have never made multilayer pcb to order in China that's why I asked. From what I see the minimum order quantity is 5 pcb in jlpcb. I just asked because I don't want to screw something up while placing the order or I can consider buying a ready device from you.Quoteok thx I added my email address via crowdsupply

author: haastyle
author_rank: Regular Contributor
timestamp: February 03, 2025, 09:44:27 pm
content: Thanks for signing up for updates.This is the page where others can sign up for updates:https://www.crowdsupply.com/andy-haas/haasoscope-proExpecting to launch this month.Quote from: lfldp on February 02, 2025, 08:15:44 pmYes, sort of. You would connect your external clock to the SMA input near the FPGA on the PCB. The firmware / software can select between the internal 50 MHz oscillator and an external clock input.(Usually the external clock input is the LVDS signal from another Haasoscope Pro. This is how syncing of multiple units is done. But it's easy to take the external clock input from any source you like.)

author: sdouble
author_rank: Frequent Contributor
timestamp: February 06, 2025, 02:48:11 pm
content: My 2 cents :1)foresee a rack mounted card to accomodate many more than 1 module2) a 2 channel module is rather limited. Think about a 4 channel version.3) an external clock or synchronization signal would be nice to snchonize many cards. You may think about a "master" clock or sync board for that purpose.4) syncronization should allow 50- 100 ps jitter between boards.5) ENOB is a key parameter.6) You may want to integrate a low noise VGA in the input stage to accomodate for different input signal range.7) you may consider a SMA input option.

author: nctnico
author_rank: Super Contributor
timestamp: February 09, 2025, 12:36:09 am
content: Quote from: haastyle on January 02, 2025, 11:13:49 pmDidn't see your reply until now...For clarity, I'd draw the relay contacts as seperate symbols in the schematic instead of big blobs with many contacts. That way you can really make a clear diagram on how the analog signals flow. And it also groups the control signals together in a logical way as a consequence.

author: haastyle
author_rank: Regular Contributor
timestamp: February 10, 2025, 01:47:02 pm
content: Quote from: sdouble on February 06, 2025, 02:48:11 pmThanks for all these ideas! I think we're already on the same page. Expandability was a key design element from the beginning, even for the original Haasoscope.1) The aluminum case has internal rails that the board slides into. A rack would just need to be a larger version of the case.2) To get 4 channels, you just combine 2 haasoscope pros. They can stack on top of each other or side by side.3) Syncing units is done through a sigle cat5 "Ethernet" cable that goes between units. The clock from the first board is replicated to downstream units.4) The board to board jitter is at the 10-20 ps level already, limited by the Altera Pll jitter.5) So far I've specified the same info via noise floor and input range, which seems to be more standard in the scope specs for other brands. Enob is about 10 at max sample rate, limited by the adc, but approaches 12 as the rate is lowered, thanks to sample averaging.6) There is a vga, the lmh6401.7) I did consider sma. They are easier, cheaper, and better bandwidth. But bnc is the standard for scopes, and we seem to be stuck with it.

author: nctnico
author_rank: Super Contributor
timestamp: February 12, 2025, 01:48:59 pm
content: I don't see how you want to interleave two ADCs on different boards using a clock with 20ps jitter. Actually, a typical clock from a DPLL in an FPGA is useless for an ADC due to the excessive jitter. You'll need an external, low phase noise (analog) PLL. Some ADCs have clock cleaners inside them but you'd need to phase-sync these somehow when interleaving several ADCs. AFAIK this is already hard to do on a single board, let alone two seperate boxes.

author: haastyle
author_rank: Regular Contributor
timestamp: February 12, 2025, 02:13:52 pm
content: Quote from: nctnico on February 12, 2025, 01:48:59 pmThe FPGAs will have up to 20 ps jitter between boards, but the ADCs are driven by a PLL chip on each board - the ADF4350, which has <0.5 ps of jitter at 1600 MHz. Works great.

author: nctnico
author_rank: Super Contributor
timestamp: February 13, 2025, 07:55:06 pm
content: Quote from: haastyle on February 12, 2025, 02:13:52 pmBut how can you align the phases in a deterministic way between the ADCs on different boards over power cycles?

author: haastyle
author_rank: Regular Contributor
timestamp: February 13, 2025, 08:06:41 pm
content: A test signal is generated by the board, the 1 kHz square wave used for probe calibration. It has a rise time of about 0.5 ns. This signal (from a single board) is measured by both boards, and the time offset is calibrated out. It then remains stable, until power off, as you correctly presumed.

author: haastyle
author_rank: Regular Contributor
timestamp: February 19, 2025, 01:39:02 pm
content: Doing a YouTube Livestream next week on CrowdSupply with Q+A, demos, etc...https://www.youtube.com/live/iFVRcHPmOKk?si=uV00BP1ANXJQ_4-S

author: haastyle
author_rank: Regular Contributor
timestamp: February 26, 2025, 01:29:58 am
content: Project is now live on CrowdSupply...https://www.crowdsupply.com/andy-haas/haasoscope-proThanks for your support!

author: nctnico
author_rank: Super Contributor
timestamp: February 26, 2025, 06:24:06 pm
content: Congrats! I did spot a typo in the description though. It says 50 Ohm and 1 Ohm input setting. I guess an M went awol.And what is the DC offset range?

author: haastyle
author_rank: Regular Contributor
timestamp: February 26, 2025, 10:58:52 pm
content: Yes, 1 MOhm, thanks 👍The DC offset is +-1.5V (at 16 bit resolution).

author: haastyle
author_rank: Regular Contributor
timestamp: August 07, 2025, 01:23:03 pm
content: FYI - these have now shipped. You can get one from CrowdSupply or Mouser.https://www.crowdsupply.com/andy-haas/haasoscope-pro/updates/good-news-products-have-shipped-to-our-distributor

author: Whales
author_rank: Super Contributor
timestamp: September 19, 2025, 09:23:11 pm
content: Found this page via hackaday. Woah, niceI had checked this topic previously, but I only saw the discussions of the schematic and not the specs & software support, so I've been blind.I was recently wondering if there was a step up from a Hantek USB scope but with open source (Linux) drivers. For fun I've been tempted to throw an ADC at a USB FIFO (skip the FPGA & triggering) and do the rest in software, see what happens, but I don't have the time.Questions for @haastyle:Q1. Can it do continuous (zero gaps, streamed) capture and if so then at what max rate? (this makes hardware triggering unimportant)Q2. Why are most of the input relays actual relays, but then at the end you have an opto-fet (TLP3475) for the AC coupling cap?

author: haastyle
author_rank: Regular Contributor
timestamp: September 20, 2025, 12:20:35 am
content: 1. No, it's not continuous, except at lower sample rates). At 3.2 GS/s and 12 bit samples, that's about 40 Gb/s (after error correction overhead etc.). That would challenge even a USB 4 connection. There is another open source scope, Thunderscope, yet to be released, which does this but at 500 MS/s and 8 bits.2. The opto-relay is a traditional choice for AC coupling. It is cheaper ($1 vs $10), smaller, has less insertion loss, uses less power, has less capacitance, etc. than a mechanical relay. And it does NOT have to have large bandwidth - the high freq part is always carried by the parallel capacitor. The opto-relay just switches through the low freq part of the signal, down to DC. Good question! Dave should do a video on this.

author: tggzzz
author_rank: Super Contributor
timestamp: September 20, 2025, 08:48:26 am
content: Quote from: Whales on September 19, 2025, 09:23:11 pmIf you need that, this might be a suitablestartingpoint.https://www.ti.com/tool/ADC12DL2500EVM

author: flamin1q
author_rank: Newbie
timestamp: September 25, 2025, 07:46:39 am
content: Dave Jones tested the HaasoscopePro :Also I've noticed that the probes you sell seem to be an exact copy of:https://hackaday.com/2024/06/13/this-open-source-active-probe-wont-break-the-bank/Made by:https://jmw.name/projects/active-probe/These probes are released under a : CERN-OHL-S-2.0 license, if you've made any changes to these probes you have to release them fully opensource and under the same license. I think it would be cool if you credit the original maker of these probes for his design! (Sorry if I overlooked it somehwere)My bad design is released here:https://github.com/drandyhaas/oshw-active-probe!Nice project will be following this to see how this unfolds!

author: thm_w
author_rank: Super Contributor
timestamp: September 25, 2025, 08:40:58 pm
content: I was expecting those active probes to have a Type C input so it could be powered directly from the scope. But I guess they are 12V in? So you could just have a splitter cable (digikey sells them) going from the barrel jack off to the probe.