Which EDA Software for high speed project - Page 1
Forum section: electronics / general

author: AutomationGuy
author_rank: Contributor
timestamp: June 23, 2015, 07:49:18 pm
content: I am planing to design a 4 or 6 layer board including a 400pin BGA SoC processor with 800Mhz clock and 400Mhz (32data/28address) memory bus a 1GB Lan phy and PCIe connector plus more high speed stuff.I have done some projects with KiCad but it took me lots of time.At the moment my choice is Eagle due to cost constraints. Diptrace would be fine as well but I am not sure if it is suitable for high speed designs.Does anyone have experience with projects like this one?Thanks for your advice in advance

author: Wilksey
author_rank: Super Contributor
timestamp: June 23, 2015, 08:18:26 pm
content: Before you get an onslaught of why Eagle is crap and Diptrace is the best thing since Altium, and KiCAD is amazing etc etc, allow me to mention a few things.Eagle - for all of it's faults (and there are not that many, just features that are not present that are in other pacakges...) works well for high speed, there are plenty of examples of this (take a look at the Olimex github repository for example at their A20 board), and they work well.DipTrace has no high speed, and even when they do add it I have read that it is not going to be all that great.KiCAD works, it can take a while to do, and it sounds like you have already tried and put it aside, which is perfectly fine.If you want an open design, you can try the new Circuit Maker, not sure if it has the AD high speed stuff though, but it is free with limitations (cloud based).For a truly "professional" approach you would use a package like Altium.Personally, given all of the facts I would choose Eagle, but I am absolutely sure someone will wholeheartedly disagree.

author: poorchava
author_rank: Super Contributor
timestamp: June 23, 2015, 08:55:48 pm
content: [flame mode on]Eagle is shit[flame mode off]DipTrace is not much better for high speed - same as in Eagle it simply doesn't have it.Never thought I'd say that, I but maybe KiCad is an answer? I think I saw a video from CERN crew demonstrating length tuning functionality. I don't know if it has already been added to official releases yet.Aside from that - Altium is the way to go.Sent from my HTC One M8s using Tapatalk

author: miguelvp
author_rank: Super Contributor
timestamp: June 23, 2015, 09:04:18 pm
content: For real high speed nothing beats Allegro from Cadence but it's very expensive, for medium speeds like what the OP is talking about then maybe this is where Circuit Maker can make a difference. And if you don't want the project public then get Altium Designer if you can talk them down on the price.I wouldn't even bother with Circuit Studio if I want to pay a bit under $4K at least give me some export capabilities.

author: nctnico
author_rank: Super Contributor
timestamp: June 23, 2015, 09:17:43 pm
content: Actually you don't need a fancy package for high speed design. The ability to measure the length of a trace and putting two parallel traces on a board are all you need from a PCB package. There are numerous online calculators for calculating the width and distance of a differential pair. Add routing guidelines to that and you are set.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: June 24, 2015, 01:23:27 pm
content: Quote from: nctnico on June 23, 2015, 09:17:43 pmYou don't need a computer either. The ability to peel tape and putting it on a Mylar sheet on a light table is all you need.I'm hilarious.

author: AutomationGuy
author_rank: Contributor
timestamp: June 24, 2015, 05:12:29 pm
content: Thanks for your hints.Altium is much too expensive for me. Eagle has a good price. I read Circuit Studio has an Eagle project import. No clue how good it works.Circuit Studio would be my next choice. But its more expensive than Eagle.As far as I know one can create parallel and length defined traces in Eagle.One problem with KiCad is stability. I often lost work and had to repeat traces. You start to save your work every minute.My expectation on a comercial tool is to decrease design time. I am not sure how that would work so I would like to try a comercial tool for that.A quick check of a trial version does not realy say anything about the design effort.

author: Wilksey
author_rank: Super Contributor
timestamp: June 24, 2015, 07:20:52 pm
content: Yeah, I would stick with EAGLE, it works.

author: ehughes
author_rank: Frequent Contributor
timestamp: June 24, 2015, 09:38:03 pm
content: You may want to rethink if you really want to layout this type of high speed board. A DDR memory interface and PCIe is not trivial.It every case I have seen for low volumes (<1000), you will not be able to beat some sort of COTS module for this. I have seen a couple projects spend a lot of money thinking they were saving money buy designing their own.If you can't afford more than Eagle means that you may not have the budget to absorb the problems you may encounter.Consider something like this:https://www.toradex.com/The BSPs are already done, etc. Professional support, etc. (there are certainly other options as well) For low volume you will simply not be able to beat the price. Making your own baseboard will be an order of magnitude easier.If you are planning a custom high volume product and can't afford a high speed tool (i.e. not Eagle or KiCAD), you may want to rethink what you are doing. I don't think you will be prepared for the other costs involved.If this is just for fun (a one off), then just go for it with what you know...

author: AutomationGuy
author_rank: Contributor
timestamp: June 25, 2015, 07:40:34 pm
content: I am a software engineer with some electronics expierience. Porting linux to a new board should be no problem. Programming a memory controller or any hardware module is no problem.I have been using such COTS modules often and there are lots of companies doing such modules. I have seen abouts 10 companies each with different modules.Look at the pin count and you see many signals are missing. If you want to connect special hardware to a cpu you always end up with compromises. Usualy those modules using a bootloader which configures the hardware and its hard to modify the bootloader in case you need different hardware configuration.Puting everything on one PCB is often the best solution.If I fail with my design I will come back to your advice.When I started with KiCad in 2004 many people underestimated what you can do with simple tools.When Altium would sell their designer for less than 6K€ I would buy it. I am sure I can save design time with Altium.

author: nctnico
author_rank: Super Contributor
timestamp: June 25, 2015, 11:54:07 pm
content: Quote from: ehughes on June 24, 2015, 09:38:03 pmJust follow the layout guidelines. I've seen people making these kind of boards (fast SoC + DDR memory + I/O) with Geda + PCB. Dunno how much time they spend on it but getting the geometry right is key. Yes that could also be done with tape and transparant sheets. Spending more money on a layout package could make routing quicker but then again how much money are 3 or 4 differential pairs worth? Maybe you save 1 hour by letting the PCB package deal with them. People should stop spreading FUD that high speed design is black magic. It is simply a matter of following the instructions (read the manual!). In the end a PCB is just a bunch of copper strips and plastic.QuoteI've been down that road a couple of times. The bootloader and kernel always need lots of work before they are ready for any real production work. A BSP sounds nice but they are nothing more than unstable demos and if you have a real problem then you are still on your own even if you spend 5 digits on hardware. All in all a module doesn't save that much time. For 100 units or more it already makes economic sense to create your own PCB design with a SoC on it.

author: AutomationGuy
author_rank: Contributor
timestamp: June 26, 2015, 09:02:32 pm
content: Is there certain literature you can recomend on high speed designs?

author: free_electron
author_rank: Super Contributor
timestamp: June 26, 2015, 10:21:44 pm
content: Quote from: nctnico on June 23, 2015, 09:17:43 pmthere is not a sane pcb designer alive that does it that way. this is the sure way to drive people insane. the moment you hit tuned buses , tuned diff pair busses with mathed impedances you need bigger iron. you need to be able to feed rules per layer depending on the board buildup. prepreg thickness can be different from core thicknesses. it may even be different materials. the router (i'm talking interactive routing) needs to understand that as you hop layers it needs to adjust trace width and clearance. the router also needs to give you automatic snaking so you can do the tuning on busses and diffpairs. attempting to do that by hand is nuts. It may work but you are going to spend weeks try to do something.if the board has any kind of density you are dead in the water.and we haven't looked into creating laser / buried stacks yet. for that technology you even need to define more parameters.

author: nctnico
author_rank: Super Contributor
timestamp: June 26, 2015, 10:46:23 pm
content: That may be true for a motherboard with many PCI expres, Sata and USB interfaces but a SoC design usually has 1 or 2 pairs for USB, 2 for ethernet and maybe another 2 for Sata or Mipi. These designs typically have a 6 layer stackup with 3 inners layers for power, one inner layer for non critical signals which leaves the outer layers for matched impedance traces. I hope this shows you can make things simple for yourself.

author: Dago
author_rank: Frequent Contributor
timestamp: June 29, 2015, 06:03:39 am
content: Quote from: AutomationGuy on June 26, 2015, 09:02:32 pmDefinitely High Speed Digital Design: A Handbook of Black Magic by Howard Johnson:http://www.amazon.com/High-Speed-Digital-Design-Handbook/dp/0133957241/

author: AndyC_772
author_rank: Super Contributor
timestamp: June 29, 2015, 08:03:30 am
content: I'll hazard a guess that the memory bus in question is DDR2 or DDR3.If that's the case, it's unlikely to end up a 4 or 6 layer board, unless you ignore the rules about keeping byte lanes together, and not having them cross plane breaks.The minimum tool I'd consider for a job like this is Orcad PCB Designer Professional. You can rent it by the year if you don't want to buy outright.Alternatively I'd subcontract the job to a design house.Don't try and lay out the board with hobby tools unless you have a great deal of spare time.

author: Wilksey
author_rank: Super Contributor
timestamp: June 29, 2015, 11:24:09 am
content: You could possibly shoe horn DDR3 into 4 layers, but I went with 6 on mine and found it worked out well.Commercial reasons mean I can't show anything but it was done in Altium Designer.You can also do it with "hobbyist" tools, I did another, not commercial as such, but non open source hardware as a freelancer for someone using Eagle and put down DDR3 on a 6 layer board.Yes AD has more advanced tools making it easier, but other tools work just takes a bit more time, but if you know how to use them then it's not a problem.

author: free_electron
author_rank: Super Contributor
timestamp: June 29, 2015, 11:49:36 am
content: Quote from: nctnico on June 26, 2015, 10:46:23 pm400MHz isn't exactly chicken feed anymore. this is the point where a board stops being just a bunch of copper strips and plastic'.PCIe and Gigabit lan are even beyond that.Sure you can do that with a drawing program just like you can do all calculations using slide rulers and trigonometric tables ....The problem with things like DDRx and PCi buses is that your timing budget is so narrow you start dropping in the 5 to 10 millimeter range ... If the control signals are not snaked correctly you will get all kinds of strange behavior. maybe not a t 25 degree c but heat or cool the darn thing , throw some humidity in the mix and things will go sour very quickly. you want to keep the impedances constant as well. at 1.2 volt pp there's not much margin in that eye ... So you need to know the stackup of the board exactly so you can figure out what signals couple to what plane and how far they are apart and which one is dominant. that is going to determine your trace width and gap. this will be different dependent on the layer. so for any trace that needs to do a layer hop these parameters change.You really need the help of software that can juggle all that stuff for you. Sure you can do it mspaint if you want to... after all the inca's built whole cities using knotted ropes ... then again , they had lots of people and time ...

author: AutomationGuy
author_rank: Contributor
timestamp: June 29, 2015, 05:34:45 pm
content: Thanks for your inspirations.From your hints two more questions come up.Does any one use Circuit Studio for high speed design and which experience you made?I should leave high speed lines on the top layer to avoid vias? Address bus and data bus on the top layer without vias?I personaly don't think high speed design is black magic. I might fail with my first design but I will improve it.The design of my PCB is not meaned to be final. I want to test different hardware variations on it. Hiring a design house for that seems not helpfull to me.

author: AndyC_772
author_rank: Super Contributor
timestamp: June 29, 2015, 06:08:49 pm
content: I wish you the best of luck, but there are a few things to be aware of.Depending on the package and pinout of your processor, there may be a minimum number of layers that are required in order to escape all the traces. The layer count of a complex board is often dictated by a requirement like this, not just to provide enough routing capacity.Memory problems can be very hard to diagnose. You may, for example, find your board works just fine when it's cold, but has random crashes when it's hot.You don't need to keep traces on just one side of the board, and you won't physically be able to anyway, there's not room. You do, however, need to restrict each trace to a via at the processor and a via at the memory device, and every trace must be impedance controlled (which means different widths on different layers). There are length matching rules you must adhere to as well.

author: nctnico
author_rank: Super Contributor
timestamp: June 29, 2015, 08:46:18 pm
content: One of the first steps for a succesful SoC design is getting the power distribution right. Try to minimize the number of power nets and think about how the copper pours should be placed to distribute power.It also helps to optimise connections at the schematic entry stage and choose packages wisely. Make a few dry runs with several different component placement variants. In some cases there are larger BGA packages which allow easier routing or vias underneath the BGA. In some cases you can route all the memory data connections on the top layer which makes life a whole lot easier because vias eat up precious board space quickly.

author: free_electron
author_rank: Super Contributor
timestamp: June 29, 2015, 09:48:23 pm
content: Quote from: AutomationGuy on June 29, 2015, 05:34:45 pmWhat board technology will you use ?You first need to look at the required impedance for the DDR's and see if you can meet that in terms of line width and spacing on the to layer.The required trace parameters may be such that you cannot route between the balls of the BGA. You can get away with local discontinuity if it is not too bad and you are not pushing the envelope ( like DDR3 and GDDR5 )IF that does not work you will need to change board technology and go to a laser drilled board. ( don't be afraid, laser drilling is actually cheaper than mechanical drilling. Mechanical drills can do about 2000 holes an hour or less depending on drill size , Laser drills do the same 2000 holes in a minute . )Using laser drilling you get to control how deep you burrow.The advantage is :-no via stubs so no reflections-very small via's, that fit in a pad or in a trace, so no discontinuities there... a 4 plug in an 11 mil pad is no problemo for lasers.once you start burrowing you can be creative with the layer stack . you will have sequential lamination anyway- top- prepreg < thin so top will couple to ground----------------------------------------------- ground- prepreg < thin so signal 1 will couple to ground---------------- signal 1- core <-thick so no coupling between signals layers- signal 2---------------- prepreg < thin so the signal 2 will couple to power ( power and ground planes are very low impedant. for all means and purposes a power plane is a ground plane. )- power--------------- prepreg < thin so bottom will couple to power- bottomyou can burrow from top to signal 1 by placing two laservias on top of each othersame for bottom to signal 2you can have complete thru-board via's for things like power nets , or you use the buried from signal 1 to signal 2 ( you get that one for free )if you create the via stacks like snowmen ( and not old fashioned dogbones) you can get tremendous routing density on the signal layers.This board would be constructed as follows- double sided core , drill holes , plate , pattern. now you have a panel holding signal 1 and signal 2- apply prepreg and copper foil above and below, laser drill , plate , pattern . this becomes your planes- apply prepreg and copper foil above and below. laser drill , mechanical drill for the thru's , plate , pattern. board ready.so you have two lamination cyclesyou can do 3 if needed but production time increases with each lamination cycle , it is cheaper to build multiple cores in that case.You really don't want to be faffing about with simply 6 layer thru-only boards. Modern SOc's are designed for HDI technology ( Laser / blind and buried ). It solves so many problems ( impedance, routing density , connectivity ) in an elegant cost effective way.But you DO need the tools that understand this technology and help you.. otherwise it's all sliderules and chalkboard ...so first : figure out your impedances and margin, derive from that the trace widths and clearances and see if you can break out the SOC.If not , adjust the buildup until you get something that works. if you can't make it work : switch to HDI (High density interconnect , basically laservia's in a blind and buried stackup) to solve the problem.

author: nctnico
author_rank: Super Contributor
timestamp: June 29, 2015, 10:55:25 pm
content: I've also been down that road. For medium volume products (batches less than 1000) the prices of the PCB skyrocket. In the end I redesigned that particular board to use a SoC and PMIC in packages more suitable for common PCB manufacturing techniques.

author: AutomationGuy
author_rank: Contributor
timestamp: June 30, 2015, 11:36:27 am
content: Here is some information on high speed designs:https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an528.pdfMy PCB manufacturer has impedance information on his PCBs as well.

author: nctnico
author_rank: Super Contributor
timestamp: June 30, 2015, 01:33:37 pm
content: That appnote assumes that every trace is a transmission line. A rule of thumb however is that a conductor which is shorter than 0.1 * wavelength does not need to be treated like a transmission line. At 0.25* the wavelength a trace could resonate at the given frequency. In other words: if you keep the edge rates low (lowest drive strength) you can go a long way without having to really care about transmission line effects. Keep that in mind because it is a good reason to choose a single device memory solution over a solution with multiple devices.

author: funkathustra
author_rank: Regular Contributor
timestamp: June 30, 2015, 11:23:57 pm
content: You'll need a minimum of 6 layers to fan-out most modern BGAs, and if you've got other peripherals or a lot of power domains, you may need a lot more (the i.MX6 REX project is done on 12 layers, for example). If your SoC is smaller than 0.8mm pitch, you'll need via-in-pad technology, laser-drilled microvias, and/or 3mil traces.Manufacturing and assembling prototype quantities (10 or so) of a 6- or 8-layer board with a custom stack-up, plus assembly and BOM could cost $10k or more, depending on board complexity, turn-around time, and if you're going to China or not. Considering you'll probably need to run two or three prototypes to get the design nailed, you're talking about a $30k investment in materials.Designing and routing a DDR memory bus by someone new to high-speed routing could take 50 hours or more of engineering time. Budgeting $100/hr, means you're at $5000 in personnel costs, just for the memory bus.And you're quibbling over the price of an EDA tool that costs less than $10k? Just buy Altium and do it the right way.

author: AutomationGuy
author_rank: Contributor
timestamp: July 04, 2015, 09:23:19 am
content: According to this which is a usefull Altium vs Circuit Studio comparison:http://www.element14.com/community/docs/DOC-76216/l/circuitstudio-by-altium-vs-altium-designer-feature-and-specification-comparisonCircuit Studio has no trace length tuning.Eagle and KiCAD have this feature.Altium seems to have a high speed design rule check as well.