PCB via current - Page 1
Forum section: electronics / projects

author: Ultra67
author_rank: Newbie
timestamp: August 04, 2017, 11:47:15 am
content: Hello,I'm designing a 4 layers PCB that will have 20A current going through. I have thick traces (width of 13mm) and I need to put vias to link all the pads. Do you know how much current can handle a via ? Depending on its size of course. Is it better to put several vias on a same trace or put a big one?Thank you.

author: Rerouter
author_rank: Super Contributor
timestamp: August 04, 2017, 12:00:49 pm
content: Its more or less down to your plating thickness,Try downloading staturn PCB toolkit, its free and has a calculatorfor 0.5mm via holes, and 1 mil thick plating you would be looking at 10 vias to stitch through a 1.6mm board. you want them to more or less fan out in a line, if you have them in rows then the trace is thinner where the adjacent via hole is.

author: fcb
author_rank: Super Contributor
timestamp: August 04, 2017, 12:21:49 pm
content: Interesting thread.I do boards with 32A on 2x9mm traces (top & bottom) - had no problem with 10x1.5mm vias in 1oz. Probably the more the merrier though.

author: Ultra67
author_rank: Newbie
timestamp: August 04, 2017, 12:30:33 pm
content: Thank you for your interesting replies. Is this a good way to place the vias or should I change the design? I'm struggling designing this PCB with such thick traces (first PCB ever).

author: Rerouter
author_rank: Super Contributor
timestamp: August 04, 2017, 12:42:13 pm
content: Make it 2 rows horizontally, about 1/3rd in from the edge of your trace, increase the spacing so that the plane can get in the gaps, and change the vias to solid vias, so there is no reliefs to the plane. you still want it to have as low resistance as possible.This was for a 15c temperature rise, you could always add a few more if your layout allows it to reduce the temp rise.

author: Ultra67
author_rank: Newbie
timestamp: August 04, 2017, 12:52:28 pm
content: I made some changes but I'm not sure about solid vias. I didn't find it in the via properties, could you tell me how to change it ? I guess it's related to the copper plane that stick to the via?

author: alm
author_rank: Super Contributor
timestamp: August 04, 2017, 01:27:35 pm
content: Look up how to disable thermal reliefs for the PCB package that you are using. That is the term you should be searching for.

author: Ultra67
author_rank: Newbie
timestamp: August 04, 2017, 01:30:56 pm
content: Thank you very much. I could change it. If anyone is looking for the solution, here it is.

author: tszaboo
author_rank: Super Contributor
timestamp: August 04, 2017, 03:05:25 pm
content: Lots of smaller vias is better. For the same area. I usually do 0.3-0.5mm ones. I actually tested this, but it is simple mathematics.A 1mm via has 2 x 1mm x pi x plating thickness copper. 4 x 0.3 mm fits the same area, and it has 4 x 0.3 x 2 x pi x plating thickness copper. 4 x 0.3 > 1 x 1.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 05, 2017, 01:36:31 am
content: Quote from: NANDBlog on August 04, 2017, 03:05:25 pmYup, smaller holes --> more perimeter.Fab is often restricted on how closely the holes can be packed, so there is some advantage for slightly larger holes. They can be placed with higher density. Again, 0.3-0.5mm is about as good as possible.Very small vias rarely fill with solder, even if they are exposed to solder (via-in-pad or wave). This is a problem below about 0.3mm. If you're doing a solder wave process, it can be worthwhile to use somewhat larger (say 0.5 to 0.8mm) vias, untented, so they fill with solder.Solder is a poor conductor of heat and electricity, about 10 times worse than copper. This is made up for by the much greater volume: instead of a ~35um layer of copper inside the hole, the hole is filled solid with metal!Worth remembering for SMT power devices too (thermal vias).Tim

author: aandrew
author_rank: Frequent Contributor
timestamp: August 08, 2017, 02:19:31 am
content: Quote from: T3sl4co1l on August 05, 2017, 01:36:31 amOr, if you're using VIP intentionally, a very good thing! My typical via is 0.2mm (8mil); I drop them down on pads with impunity.The old IEC standards recommended against it, supposedly because the concern was that solder would get sucked down into the via, causing a poor(er) solder joint, and so recommended filling or plugging the vias to prevent this. The newer specs don't seem to mention this anymore, and a design a few years back seemed to prove it out for me.

author: floobydust
author_rank: Super Contributor
timestamp: August 08, 2017, 02:45:22 am
content: Your PCB stackup is important. I experienced hassles getting 32A on a 4-layer PCB.Vanilla PCB base-copper (laminate) is 1/2oz and they plate-up 1/2oz to result in 1oz finished copper.Notice this gives 1/2oz copper in your vias but 1oz on outer-layers. Your inner layers will typically be the 1/2oz base laminate.Be careful your PCB spec sheet tells the PCB house to plate-up X oz. over your base copper to set your via copper.Small via holes plug up if they plate-up too much. There are limits and I would ask the PCB vendor.Sometimes it's easier to use a through-hole part as a via.