Variable delay of a digital signal - Page 1
Forum section: electronics / projects

author: ataradov
author_rank: Super Contributor
timestamp: June 03, 2017, 07:39:08 am
content: I'm working on a project, and I need to delay a digital clock signal by a variable amount in the range ~0-50 ns. ~1-2ns resolution will work.What I have is a CMOS logic gate output that carries ~20 MHz clock. Delayed signal will go into the input of another logic gate (inverter) for conditioning, so any introduced imperfections are not important, as long as they are compatible with CMOS input.For control I can have DAC output, or a few digital signals fro the MCU, or anything else within reason.Stability over voltage range or temperature is not important, it will be tuned before each use anyway. But this should not introduce more than 1-2 ns of jitter.I'm looking for the cheapest and simplest solution possible, so programmable delay lines for $10 (and even $2) are out of the question.I was thinking about simple RC filter. I assume varicaps can be used here somehow, but I never worked with them, so I really have no idea if they will work for this.Any ideas?

author: Rerouter
author_rank: Super Contributor
timestamp: June 03, 2017, 08:33:49 am
content: the quick and dirty way if your not too concerned about temperature influence is a string of buffers and a mux, or an open collector shift register with near binary steps, playing RC to a schmitt trigger,

author: ataradov
author_rank: Super Contributor
timestamp: June 03, 2017, 08:36:24 am
content: Quote from: Rerouter on June 03, 2017, 08:33:49 amThe board area occupied by all this is going to be huge, too many extra components to get necessary range.

author: ataradov
author_rank: Super Contributor
timestamp: June 03, 2017, 08:44:22 am
content: Quote from: blueskull on June 03, 2017, 08:36:33 amAnd I'm definitely don't want to introduce a new programmable part.All of this competes with MAX 10, which would pack inside some other hard logic, and allow for more flexibility. So if there is going to be another programmable part, it would be FPGA.

author: Someone
author_rank: Super Contributor
timestamp: June 03, 2017, 10:41:13 am
content: You're probably looking at multiple cascaded phase shifting stages based around the resistance modulation of a FET or PIN diode.

author: Kalvin
author_rank: Super Contributor
timestamp: June 03, 2017, 11:15:04 am
content: Dirty hack: Cascade or-gates or buffers of two different logic families, and tap out from each stage: You should get a selectable delay. Select something fast with 2 ns propagation delay and something sloooow with 10 ns propagation delay.

author: Ian.M
author_rank: Super Contributor
timestamp: June 03, 2017, 11:51:33 am
content: Another dirty hack - use a CMOS logic family with a wide Vdd range like 74HC for the chain of buffers, with a level translator before and after the chain, and vary their Vdd to fine adjust the propagation delay. Handle tapping the chain with an analog switch so you only need one pair of level translators. A ring oscillator using gates in the same packages as the delay chain could let you autocalibrate the delay.You aren't going to be able to get a fine delay down to 0ns that way, but if you can delay from 20n to 70ns, does it really matter if your effective 0ns to 20ns delay is really 50ns to 70ns and a whole cycle behind?

author: MagicSmoker
author_rank: Super Contributor
timestamp: June 03, 2017, 01:46:56 pm
content: Probably a varactor diode (aka varicap) as part of an RC integrator in between two Schmitt buffers; see attached pic for a rough idea of the circuit. D1 is the varactor diode whose junction capacitance is inversely (and non-linearly) proportional to DC bias - which needs to be supplied by an RF blocking choke, L1 - while C1 is the necessary DC blocking capacitor and should be at least 10x larger than the max junction capacitance of D1. A typical range of junction capacitance is 10:1 so should be more than enough to cover your delay range.Note, however, that the hysteresis levels in Schmitt logic gates is not terribly well defined or repeatable, nor is the junction capacitance from varactor to varactor. You can solve the former problem with a high speed comparator and a few resistors while the latter really needs some form of feedback loop which will be somewhat tricky to implement at 20MHz.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 03, 2017, 02:05:47 pm
content: If it is a stable clock, one could use a PLL with adjustable phase shift. To get low jitter the VCO might need to be at least and LC type, but could be a VCXO as well. However the price might end up higher than with commercial delay lines.For a super low cost version the varicap in an RC delay line (might need more than one RC element) might be the best option. However I somewhat doubt one could get the jitter low enough.If it is only one slope that needs to be delayed, one could also use a transistor inverter stage with a variable level of overdrive and thus delay. Adjustment could be through the current at the collector side.

author: ataradov
author_rank: Super Contributor
timestamp: June 03, 2017, 05:50:13 pm
content: Quote from: MagicSmoker on June 03, 2017, 01:46:56 pmThis is the kind of stuff I was looking for.But given all the complexity, I feel like FPGA will be a way to go.

author: Neomys Sapiens
author_rank: Super Contributor
timestamp: June 05, 2017, 10:14:07 pm
content: Maybe of use:Delay, Timing AD AN-260 Using Digitally Programmable Delay Generators 1998 6pgsDelay, Timing AD AN-261 Programmable-Delay IC's control System Timing 1988 8pgs

author: ataradov
author_rank: Super Contributor
timestamp: June 05, 2017, 10:16:06 pm
content: Too late, I've routed half the board with MAX 10It is much easier, and adds some useful functionality. All that discrete logic stuff is way too expensive and hard to use in the end.

author: BrianHG
author_rank: Super Contributor
timestamp: June 05, 2017, 10:29:53 pm
content: Quote from: ataradov on June 05, 2017, 10:16:06 pm?? A discrete 10 cent tuning or zener diode, 5 cent inductor and a 15 cent 74HC14 logic buffer, giving you a voltage tuned digital delay line is more expensive than a MAX 10 PLD?

author: ataradov
author_rank: Super Contributor
timestamp: June 05, 2017, 10:33:32 pm
content: Quote from: BrianHG on June 05, 2017, 10:29:53 pmThat clock is only a part of the circuit. There are also associated data bus latches. And as I said, FPGA will let me implement some things that I had to sacrifice with discrete solution. For a less than $10 device, it is not that bad of a deal. The only downside is huge board area, but that's fine.

author: ataradov
author_rank: Super Contributor
timestamp: June 05, 2017, 10:42:19 pm
content: Quote from: blueskull on June 05, 2017, 10:37:39 pmTheir Diamond software is very picky about version of Linux they work on. I know, that's not a real problem for production use, but for half-hobby use, I'd like to stick with convenient development environment.Quote from: blueskull on June 05, 2017, 10:37:39 pmThey lack PLLs, and PLL is the way to implement this delay at the moment.Configuration time does not matter. MCU is master in the system, and it can wait until FPGA is configured.