STM32F103 ADC supply config - Page 1
Forum section: electronics / general

author: Khashayarfn
author_rank: Newbie
timestamp: April 15, 2018, 08:41:21 pm
content: Hi to alldatasheet 13587 Rev 175.3.1 table 9 says: Vdda must be same potential as Vdd with a maximum diff of 300mV (footnote).5.3.18 table 46 says: Vdda must be between 2.4 - 3.6 and not mentioning anything about Vddand AN2834 2.2.12 says: it is desirable to have separate analog and digital supplies.so the question is: how can i manage Vdda - Vdd <= 300mV with different supplies during opration and especially during power up?and 2 other question about Vref,AN2834 suggests using linear regulators but usually they have errors in different temperatures,do you suggest using reference voltage ICs?also about using a separate 3.3v voltage reference ic for Vref: in table 46 of datasheet max rate for Vref is mentioned Vdda, and using different 3.3 supplies doesn't guaranty exact same 3.3000 voltage for both Vref and VDDa, is this difference going to be a problem or can i forget about it?my supply is: SMPS DCtoDC 12-5 and in next level two separate LDOreg 5-3.3 for Vdda and Vdd

author: ogden
author_rank: Super Contributor
timestamp: April 15, 2018, 08:51:16 pm
content: Quote from: Khashayarfn on April 15, 2018, 08:41:21 pmConnect both supplies using diode. Make sure that @max VDD current voltage drop on that diode does not exceed 300mV.

author: julianhigginson
author_rank: Frequent Contributor
timestamp: April 24, 2018, 09:32:32 am
content: Can't you just run them off the same supply, but filter Vdda with a suitable chip ferrite and a collection of ceramic caps?

author: iMo
author_rank: Super Contributor
timestamp: April 30, 2018, 06:48:57 pm
content: Which F103?The Vref input is available only with large 144pin packages, afaik.Otherwise the Vref input is connected internally to Vdda.When using two different 3.3V LDOs for Vdd and Vdda there is only a little chance they will be off by >300mV..

author: ogden
author_rank: Super Contributor
timestamp: April 30, 2018, 08:58:35 pm
content: Quote from: imo on April 30, 2018, 06:48:57 pmDepends on what you consider "little chance" and "for how long", especially considering that VDDA consumption is much lower than VDD.

author: iMo
author_rank: Super Contributor
timestamp: April 30, 2018, 09:09:03 pm
content: An ordinary 3.3V LDO will give you 3.3V +/- 0.05V max. If not, it is broken.The Vdd or Vdda current consumption have nothing to do with the voltage levels at the outputs of the LDOs, unless the Vdd or Vdda currents exceed the max allowed currents of the LDOs. If the currents exceed that value, the STM32 is broken.

author: Jeroen3
author_rank: Super Contributor
timestamp: May 01, 2018, 05:37:25 am
content: Vdda and Vdd must be the same power supply. You're supposed to add additional decoupling because the clocking circuitry is also powered from Vdda.(Don''t want this noise running over your board)If you want to use a Vref on the 103 <144 pin count you will have to add this on an ADC channel and correct after sampling.

author: iMo
author_rank: Super Contributor
timestamp: May 02, 2018, 03:14:13 pm
content: FYI, the most complicated stuff to solve is the pcb design when talking F103 ADC.With 2 layers pcb you most probably will get +/- 20 noise, whatever ADC supply config (including well made decoupling) you may create.A quieter readings are, imho, possible only with 4 layers and pretty careful design, especially the stuff around analog and digital Vdd and Gnd routing.