Multi project wafer runs for the masses? - Page 1
Forum section: electronics / general

author: sweesiong78
author_rank: Contributor
timestamp: October 27, 2014, 09:47:17 pm
content: Today we can get cheap and accesible custom PCB's thanks to manufacturers aggregating multiple pcb projects into a single board. How long is it before cheap and accessible multi project wafer services (along with the VLSI design tools) filter down to the mainstream? Whats the cheapest foundry rate like for those already providing this service in the older processes/ larger feature sizes (microns, etc?)http://www.mosis.com/what-is-mosis

author: Scrts
author_rank: Frequent Contributor
timestamp: October 28, 2014, 09:28:40 am
content: How much is cheap for you? I think Toshiba already offers this for 50k USD.

author: a210210200
author_rank: Regular Contributor
timestamp: October 29, 2014, 11:35:57 pm
content: Quote from: sweesiong78 on October 27, 2014, 09:47:17 pmI think right now the cheapest for low runs is FPGA to ASIC conversion but it isn't ideal and the costs are still quite high with for hobbyist at least absurdly high min qty.PCBs are made using much larger and cheaper processes I think it will be a few years at least before it is even remotely accessible to a single person to make one custom die. Unlike PCBs each ASIC is going to require testing or improvements to the process so no testing is required as PCB mfg can get away with not testing the boards at all (I've gotten boards with floating tracks smeared across and all manner of random defects but they are rare or non-noticeable, on an ASIC flaws can cause problems much easier and even batching designs together could cause problems in mfg)For hobby or very low run FGPAs are a good match. In our university labs we use Altera but I find the IDE for it to be a big bloated mess and am looking at other major mfgs.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: October 29, 2014, 11:44:15 pm
content: It will never happen. The masses simply don't need their own custom chips enough for it to be viable.There are very few things that can't be done with some combination of MCUs, purpose-made chips and FPGAs, and for low to moderate volumes, that will be the cheapest way to do it.The only time ASICs become viable is where you have high volumes, and in some cases extreme space/size constraints.

author: Araho
author_rank: Regular Contributor
timestamp: November 01, 2014, 11:52:40 pm
content: As a matter of fact, there used to be a MPW-service ("Multi Project Wafer"-service) right here in Norway, for use both by students in IC design and commercial interests. Geared mainly towards MEMS design, the last run was sometime in 2009, IIRC. For students, the cost per project was from 1000€ to 1500€ for at least 100 dies, depending on size, and from 4000€ to 6000€ for commercial interests.This is the website of the project, courtesy of SINTEF, the largest independent research group of Scandinavia:http://www.sintef.no/Projectweb/Microbuilder/SiliconGlass-Multi-Project-Wafer-services/

author: mazurov
author_rank: Frequent Contributor
timestamp: November 02, 2014, 01:07:57 am
content: I used to date a process engineer at microfabrication research facility. She was not able to fab large chips like a memory but MEMS devices, VECSELs, MIIMs, as well as ITO patterns deposited on glass were very easy to me to get. Don't know how well this solution would scale though :-).

author: Marco
author_rank: Super Contributor
timestamp: November 02, 2014, 01:24:34 am
content: Quote from: mazurov on November 02, 2014, 01:07:57 amWas there some quota for personal research or employee discount or something?How automated are these prototype facilities? Can you just shove a maskset and process parameters in one end and get the diced wafers out the other? Or do the machines have to be babysat?

author: RobinF
author_rank: Newbie
timestamp: November 02, 2014, 08:10:48 am
content: Europractice (the European equivalent to MOSIS) does offer quite reasonably priced MPW runs. You can check out the schedule and price listhere. For example, you can get 30 samples in OnSemi's 0.7 micron 2M/1P for €1800.

author: tszaboo
author_rank: Super Contributor
timestamp: November 02, 2014, 09:34:34 am
content: Custom digital is boring. Show me someone with custom analog. Or someone who can put multiple TI tested wafer into one carrier.

author: cloudscapes
author_rank: Regular Contributor
timestamp: November 02, 2014, 02:12:10 pm
content: I'd much rather see the option to put existing silicon in more convenient packages for those of us who can't handle BGA.

author: tggzzz
author_rank: Super Contributor
timestamp: November 02, 2014, 03:47:21 pm
content: Quote from: sweesiong78 on October 27, 2014, 09:47:17 pmThere are two answers...I first saw such a service 30 years ago, in that case using e-beam writing of the wafers. Clearly there is only a minor requirement for such a service.Most of the reasons for wanting cheap low-volume custom silicon can be satisifed by FPGAs and/or CPLDs and/or MCUs.The questions for you to answer are "what customer requirements cannot be satisfied by the existing commercial options?" and "in what way will custom silicon be better?" and "what is necessary for custom silicon to be technically and commercially viable?".

author: RobinF
author_rank: Newbie
timestamp: November 02, 2014, 04:43:12 pm
content: For digital stuff it will never make sense to produce custom silicon. Even in commercial devices there are fewer and fewer cases in which it's worthwile.For analog, there will always be applications where you can save significant board space by going custom. But for hobbyists (or small-scale commercial products), the investment in time, skills and money is rarely worth it. Unless you're just bored with PCB design and looking for an interesting project

author: Rufus
author_rank: Super Contributor
timestamp: November 02, 2014, 05:04:43 pm
content: Quote from: mikeselectricstuff on October 29, 2014, 11:44:15 pmAnother major issue is the huge set up costs for testing custom parts so the fab will just package good and bad die and leave it up to the customer.A bit before FPGAs became really viable I inherited a stupid design with a custom digital ASIC. We couldn't afford to set up to test them properly either. About 30% were obvious functional failures and went straight in the bin. The rest seemed to work and fingers were crossed. Lumps of the design were faulty as well and they couldn't afford to re-spin. The whole thing got scrapped in the end.