GND "peninsula" - Page 1
Forum section: electronics / general

author: Manul
author_rank: Super Contributor
timestamp: April 03, 2024, 10:54:28 pm
content: Hi,As an example, I have 4 layers: signal - ground - signal - ground. And on the second ground layer I want to create a peninsula (for the lack of a better word). If ground vias located inside the area of peninsula would connect to the Bottom ground layer that would defy the purpose of making that peninsula. So they must connect only to the second layer. On the other hand, I want ground vias in other locations to connect to both ground layers. I don't want to use blind vias or cut an equivalent shape on the Bottom ground layer. How would you do something like this in Altium? Is the only way to define the peninsula as a separate net and use a net tie?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 03, 2024, 11:22:11 pm
content: Two whys:1. Why asymmetrical stackup?2. Why slot a ground? What's around it, will anything cross the gap, are you really improving the design by increasing ground impedance?Slotted grounds create many more problems than they solve. Thus, very many questions are worth asking, and answering, before using the process.Note this doesn't mean theycan't be used ever, the point is, if you don't know what you're doing... you're 99.9% better off just not doing it, pour everything and be good.From my own experience, out of dozens of designs on my CV, there's been... maybe one? One design, that I could at least hand-wavingly justify having added a slot to; and even then, I'm almost certain it didn't make any difference in the particular design. If I did more analog, low noise / sensitive, etc. projects, maybe I'd have a few more, but mostly, it can be designed around with more careful placement and routing, and that's that.More importantly: what's around? Where are signal and ground currents flowing? Why can't you solve those ground-return paths by improving component and trace placement? Is there a mechanical restriction forcing this (otherwise-, or potentially-) suboptimal design approach?Keep in mind, the fringing field around the slot is intense, and you typically need a few board thicknesses' clearance -- around signal traces to ground edges, and between ground edges themselves -- to get adequate attenuation of those fields. You can waste a *lot* of space using a slot properly -- much more than you would spend with cleverer placement and routing.Likewise, thinking in terms of magnetic fields or transmission lines/waveguides (depending on impedance and frequency range), the proposed method is likely ineffective or worse: you're still projecting those fields (from top/mid signals, and around the peninsula) into the otherwise-unbroken plane. Which is to say one of the points from earlier: if you'd left both planes whole and stitched them, you'd have lower ground impedance than by splitting and cutting them up -- less ground-loop voltage due to currents in the local area.But again, without knowing what's routing on top of it -- no idea which of these (and many more) factors is most relevant. I could imagine some scenarios where such a construction is worthwhile, but it's mostly going to be at LF/DC, and there are probably better ways to design that, too.As for Altium, in the event where all these checks pass and I do in fact need such a structure -- I would reach for a net bridge, yes. Otherwise you'd doing tedious hackery like cut-outs stacked on vias, or worse using weird polygon settings/rules (like "Don't pour over same net objects") or worst of all un-repoured polygons, to implement it.Note you can use place-on-layer for a copper-only (use tented SMT pads) footprint and thus tuck the net bridge onto a mid layer; it doesn't have to be surface only.Tim

author: Manul
author_rank: Super Contributor
timestamp: April 04, 2024, 12:16:53 am
content: Thanks a lot, Tim, great post.First of all, it's just one of the options I'm considering and more like a "know your CAD tool" question. But still, I feel, that it might be the best option, hence the question. I'm joggling various compromises, asymmetrical stackup is one of them too. In the end, everything is in some way imperfect. The purpose of the peninsula is that I want to avoid any voltage gradient in that area. I have high DC (well, this current might slowly change, so lets classify as LF) current going vertically and "poisoning" the ground plane so to speak. I need an area which is calm. I'm aware of the effects of signals going over the ground slit, there are in fact no signals crossing that gap. So I don't really care much about impedance, I just want uniform potential. I completely agree that there are/could be better ways. I'm iterating through different placements and routing and already scrapped many. Not sure where exactly I will end up, but feeling some progress.

author: Someone
author_rank: Super Contributor
timestamp: April 04, 2024, 02:47:34 am
content: Quote from: T3sl4co1l on April 03, 2024, 11:22:11 pmThe rules in Altium are one of the most powerful parts and well suited to this task.PolygonConnect is "No connect" where InNet("GND") AND polygon by name or class.Assuming you add a set of small special polygons under the island for this purpose and the regular (lower order) polygons flow over those special polygons edges.Probably also solvable with a layer AND room

author: Andree Henkel
author_rank: Regular Contributor
timestamp: April 04, 2024, 09:25:02 am
content: it has been 6-7 years since I used altium (job change) but maybe this "workaround" still works.I used it to connect different net ground polygons at exactly and only the positions in layout where I wanted them to be connectedinstead of using "starpoint" devices which only make point connectionso different nets in schematic like "analog" ground, digital, power, connected in pcb to one plane with all the nets, cuts where wanted and wide connections where wanted.It worked like this*create net "GndConnect"*create net Class "Ground"*give your peninsula polygon another net name somehow*add desired nets to be connected to class*implement rule: allow short between element in Net "GndConnect" and element of Net in NetClass "Ground"Now draw tracks of net "GndConnect" from only the Vias of your ground (you want to connect) to the "insula Ground" INTO the insula polygon.Problem now: as soon as you repour the poygon, it will pour around the "GndConnect" trace according to spacing rulenow you need draw overlapping tracks with netname of insula Polygon covering polygon edge and "GndConnect" traceResult is: have connections exactly where and wide as intendedyou can show all places in layout where you did it by: show net "GndConnect"