Can power FETs driving long wires accidentally turn into oscillators? - Page 1
Forum section: electronics / beginners

author: incf
author_rank: Frequent Contributor
timestamp: April 14, 2025, 03:33:52 pm
content: Can power FETs driving loads through long (highly inductive) wires accidentally turn into oscillators?If so, what can you do to mitigate it?I suppose not having a good mathematical model of FET, the PCB, the cable, and the remote load make a lot of things possible. Maybe inserting impedances into the correct places would result in an unconditionally stable system.

author: TimFox
author_rank: Super Contributor
timestamp: April 14, 2025, 04:03:02 pm
content: Quote from: incf on April 14, 2025, 03:33:52 pmYes.Try drawing the full circuit, replacing the long cable with an equivalent circuit, with at least an inductor and capacitor, and including the interelectrode capacitors of the FET, and it probably looks like a potential oscillator.Whether it actually oscillates depends on the gain and feedback magnitudes.An old rule of thumb for three-terminal devices is that “stopper” resistors are needed in series with at least two of the terminals to prevent parasitic oscillations.

author: dietert1
author_rank: Super Contributor
timestamp: April 14, 2025, 04:17:06 pm
content: Same as with bipolar transistors. When using mosfets in linear mode (near threshold), it is often a good idea to insert a resistor between gate and its driver, like 10 to 100 Ohm.Many power mosfets work down to time scales of 50 nsec. So that would be a bandwidth of about 60 or 70 MHz and one needs a spectrum analyzer to detect the oscillation. The resistor reduces Q of the resonator formed by the mosfet input capacitance and the inductance of its connection wires/traces. Besides producing EMI and extra heat a mosfet oscillating in linear mode will exhibit unstable threshold and less gain.Regards, Dieter

author: incf
author_rank: Frequent Contributor
timestamp: April 14, 2025, 04:37:27 pm
content: Can anyone recommend an application note that provides a mathematical* treatment of the issue? ie. preventing oscillation of FET outputs in industrial applications.*(providing quantitative criteria, something like Zg and Zs >= g_FS * K )edit: I guess I should have googled that exact phrase, I found somehttps://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00066.pdf?did=59456https://fscdn.rohm.com/en/products/databook/applinote/discrete/sic/mosfet/oscillation_countermeasures_for_mosfets_in_parallel_an-e.pdf

author: Terry Bites
author_rank: Super Contributor
timestamp: April 14, 2025, 05:02:19 pm
content: I'd say the Tosh provides a very thorough treatment of this issue. And the Rohm offers practical solutions.You could do bit of network analysis of your own. Model the long line as lumped components and analyse that on its own.Its essentially an LC tank and peak will be seen at the resonant point. So pushing the q down, limiting the feedback and gain of the circuit all contriubute to killing off the oscillation.

author: David Hess
author_rank: Super Contributor
timestamp: April 14, 2025, 07:08:05 pm
content: The proper lossy ferrite bead, parallel LC section in series, or series RC section in parallel with the output can prevent oscillation. A Zobel network is a more thorough solution and often found in class-AB amplfiers:https://en.wikipedia.org/wiki/Zobel_network#Practical_sections

author: incf
author_rank: Frequent Contributor
timestamp: April 14, 2025, 07:42:08 pm
content: A guide says "reduce the source and gate inductance, increase the gate resistance"Would it be ill-advised to add a 1nF ceramic capacitor (with series 1 ohm resistor I guess) between the gate and the source to bypass any inductance that may exist?At 80MHz a 5pF parasitic capacitance has an impedance of roughly 400 ohms.Shown below is what I imagine to be a typical sort of high side switch setup (although it's missing a gate zener)