Options for flexible digital signal routing: Crosspoint switch vs FPGA - Page 1
Forum section: electronics / beginners

author: magicmastja
author_rank: Contributor
timestamp: April 08, 2023, 12:08:00 pm
content: Hello, so ive been trying to map out a design for a carrier board that would accept a standardized SOM based compute implementation. Where I'm having trouble is figuring out how to manage the PCIe signal routing, the current revision of the SOM pinout is designed for a max of PCIe 3.0 x4 lanes config, but many of the modules currently on the market vary between 1-2 PCIe 2.0 x1/x2 or just 1 PCIe 3.0 x1. Ideally, I want to make sure its possible so that if the module only has 1-lane it can be addressed to two different M.2 ports, either wifi or flash storage, based on user preference. I can also tell I'm probably going to want some similar flexibility with video and maybe USB outputs so that's a consideration as well.Given their flexibility, is this the sort of thing an FPGA would be well suited for? Or would I be better off going for individual crosspoint switches for each of my signal types? This would be my first foray into FPGAs and I'm aware of the challenging learning curve, but I don't mind working through the long learning process if need be. Board space and noise are priorities of greater concern than cost, but ideally trying to keep the solution under $30 if I can, my initial overview of anything to do with highspeed PCIe is that it greats pricy fast.

author: Infraviolet
author_rank: Super Contributor
timestamp: April 08, 2023, 05:07:30 pm
content: I know PCIe can be quite fast in terms of signals, but for slower signals where you switching rate isn't hugely fast either a 4066 type switch IC can be useful, you can make an array of them to handle one-to-many, many-to-one or many-to-many signal routing scenarios. Or perhaps a more recent successor to the 4066 chip (the 4066 is quite old), infact a digital only switch or multiplexer might work for you and be faster still. You might be able to get more suggestions if you can work out both how fast the signals travelling through your system will be as well as how quickly and often you'll need to use your system to change their route.

author: magicmastja
author_rank: Contributor
timestamp: April 08, 2023, 07:00:44 pm
content: Thanks for the suggestion, I hadnt considered drafting a small-scale tree/array-type solution with a few simpler ICs. Ill have to do a more deterministic eval of if I'm going to do similar routing with USB and video. If for the sake of argument I did include those signals, ball-park estimate of about 5-Gbit/s as my ceiling for vid + USB, after that its really just if I want to try to fully saturate an M.2 interface connected to PCIe 3.0 x2 data lines to future-proof around later advances on wifi-6 modules or not (I think they cap out at about 3-Gbit atm?).

author: magicmastja
author_rank: Contributor
timestamp: April 09, 2023, 08:45:32 pm
content: Ah found my answer, the PI3DBS16222Q by Diodes is perfect. Room to grow too with its 20gbps, priced at about $5. Cant wait for it to sell out by the time I'm ready to build the board haha.

author: fchk
author_rank: Frequent Contributor
timestamp: April 10, 2023, 10:50:38 am
content: There are PCIe Packet Switches for adding multiple devices to a single port. You would one of these:https://www.diodes.com/products/connectivity-and-timing/pcie-packet-switchbridges/pcie-switch/Simple crosspoint switches won't work.Remember that you also need clock buffers for the PCIe RefClk.https://www.skyworksinc.com/Products/Timing/PCIe-Clock-Buffersfchk

author: magicmastja
author_rank: Contributor
timestamp: April 12, 2023, 12:27:21 am
content: Ah yeah I see now after getting more into the woods with PCIe interfacing + layers. Kind of a rough state of affairs for the availability and pricing of PCIe 3.0 capable packet switchers, or FPGAs with either hard IP transmitters that exceed 5gbps or an internal PLL capable of clocking high enough for the input/output. I assume externalizing just the transceiver portion of the PCIe stack so you can generate a higher data rate than the FPGA can drive natively, and then using the FPGA for the remaining parts of the PCIe routing/switching layers would be a no-go?