efficient PDM to PCM conversion for precision audio - Page 1
Forum section: electronics / projects

author: davegravy
author_rank: Regular Contributor
timestamp: April 18, 2022, 02:42:27 am
content: I've been exploring MEMS microphones and MCU-based audio DSP recently. My goal is to create a power-efficient MEMS-based sound level meter. I've built a prototype using an I2S MEMS mic and STM32U5 - it functioned and had good power performance but I decided the mic's low-end frequency response wasn't adequate.Seemingly the only MEMS microphones that are up to par have PDM output so now I am learning about PDM->PCM conversion.I found the STM32U5 has hardware-based digital filtering using a peripheral called Multi-function Digital Filter (MDF) which I was optimistic about until it dawned on me that the decimation filters are SINCx. I believe this means I will have unacceptable attenuation in the upper audio frequencies. I did notice there is aReshape Filterwhich is closer to appropriate for this application but the passband ripple and the stopband attenuation is marginal.It seems I can:Implement software-based conversion (wideband FIR+decimation)Use anexternal conversion ICSwitch to a different low power MCU, one that has integrated wideband digital filteringAre there any other good options I'm missing?At least #1 and #2 will have a power cost compared to the I2S MEMS I was using but is anyone able to give an educated guess which of them will be better? Any recommendations for #3?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 18, 2022, 02:58:40 am
content: Sinc response means it's a sliding  averaging window. Simple to implement, good enough for, well, some things.If you have enough power handy (most STM32s should be able to do more than a bit of audio?), why not compensate with a corrective filter? Which can also give a sharper cutoff if you like.FWIW, I implemented such a filter (or totalizing counter or sigma-delta receiver, however you like to call it) on an AVR, using hardware resources (configurable logic (CCL), event system, and two timers). That was 12MHz clock input, though taking a 16-bit count for a mere <90Hz bandwidth, more than fine for the thermocouple I used it for. I don't know what all is available across STM32 families but likely something similar can be made. Maybe that's exactly what the hardware filter does, I don't know. Obviously you'll get less count (and so SNR) at higher bandwidth, or will need a faster clock; this may be fine (for SNR purposes) if the signal source has noise shaping.Maybe their SNR and bandwidth are simply exclusive; is it feasible to use two mics?Tim

author: moffy
author_rank: Super Contributor
timestamp: April 18, 2022, 11:27:14 am
content: A while back I built my own SigmaDelta modulator, 2nd order, with a couple of opamps, passives, comparator, FF and clock. I wanted to test its accuracy so I took the digital bit stream, and fed it into a SINC_3 filter, done on an Arduino UNO or Nano, which then fed the digital result to the PC via Serial_USB. It seemed to work fairly well so I'll include the code for reference. Not really what you are looking for as I didn't compensate the SINC_3 filter, but it might be of some interest. I did use Atmel Studio to compile the project.

author: Hideki
author_rank: Frequent Contributor
timestamp: April 18, 2022, 01:24:00 pm
content: You may find find some useful information herehttps://tomverbeure.github.io/2020/12/20/Design-of-a-Multi-Stage-PDM-to-PCM-Decimation-Pipeline.html

author: davegravy
author_rank: Regular Contributor
timestamp: April 18, 2022, 03:20:33 pm
content: OK so it seems the hardware SINC filter may be useful for initial decimation stages and reducing the degree of software filtering necessary but there will still likely be some software filtering needed. Thanks, this gives me another avenue to explore.My passband requirements are more stringent than Tom's - I need the full audio spectrum not just sub 6kHz - but I get the concept of what he's doing.

author: jonpaul
author_rank: Super Contributor
timestamp: April 18, 2022, 04:58:22 pm
content: To OPhow do you define "precision audio"Frequency response 20 hz..20 kHz?ENOB 16, 24, 30 bits?SNR? Dynamic range?THD? IMD?The tiny MEMS mic area limits LF response to perhaps 100..300 HzFor high quality audio eg studio, pro cinéma, measurement I doubt if any MEMS can meet the specificationsSuggest you first research the requirements more deeply.Fine non MEMS mics are dynamique, ribbon or condenser.we use General Radio 1/2" instrument mics on sound level metersB&K, Aco Pacific make similar calibrated mics.Fine studio mic brands are Neumann, AKG, Shure, etc.All need a good microphone preamplifierBon chanceJon

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 18, 2022, 05:00:54 pm
content: For #2, you also have stuff at TI:https://www.ti.com/product/PCMD3140For #3, there are very few MCUs that I know of that support PDM input without requiring fancy software-based filtering, but I have worked with Ambiq MCUs, that I just remembered supported PDM.Those MCUs are extremely low power, yet embed a Cortex core, so nothing exotic programming-wise.https://ambiq.com/apollo3/Sparkfun happens to have dev boards and modules for them:https://www.sparkfun.com/search/results?term=apollo3, if you want to evaluate them. Otherwise, you can order the chips from Ambiq directly:https://www.ambiq.top/en/apollo3-mcu-66pin-csp-package

author: davegravy
author_rank: Regular Contributor
timestamp: April 18, 2022, 05:37:07 pm
content: Quote from: jonpaul on April 18, 2022, 04:58:22 pmFor this application B&K, PCB, and similar measurement mics are overkill, as are many studio grade microphones, and I believe these all require a considerable amount of power for biasing.I need to cover roughly 30->110dBA SPL range, so 80dB dynamic range, and really only need 20-30dB of SNR which is easy. More challenging is frequency response flatness - tolerances depend on the frequency band but are as tight as +/- 1.1dB around 1kHz, and less restrictive at the extents especially >10kHz.https://cdn.shopify.com/s/files/1/0510/7489/1973/files/class-1-and-class-2-tolerance-in-smaart1.png?v=1643229911I need to be +/-3dB @ 20Hz, and there are MEMS devices which come very close - they can be equalized with DSP to achieve this (with some minor loss in LF dynamic range which I think I can live with).

author: jonpaul
author_rank: Super Contributor
timestamp: April 18, 2022, 05:59:14 pm
content: Rebonjour Cher DavidUnderstand perfectly, bravo for your initiative....By the way, I had invented the first digital microphone and procecuted a patent in 1989..1991, which applied to MÊMS mics,,among others.The work was recognized by the Audio Engineering Société, I was on the digital microphone standards comitee, AES-42.bon courageJon

author: moffy
author_rank: Super Contributor
timestamp: April 18, 2022, 11:54:06 pm
content: Just for completeness I have run across some good quality condenser capsules, some just $12.95 at:https://www.jlielectronics.com/microphone-capsules/jli-2555bxz3-gp/@jonpaul I would be very interested in hearing the story of the first digital microphone.

author: jonpaul
author_rank: Super Contributor
timestamp: April 19, 2022, 09:03:16 am
content: In 1980s, We used OEM ECM capsules from Primo Microphonewere 3/8" and cost perhaps $0.50 ea Jon

author: RJSV
author_rank: Super Contributor
timestamp: June 09, 2022, 09:00:03 pm
content: WOW, this is very helpful, thanks!I'm actually looking for some techniques that involve mixing of digital with analog, kind of long-winded, but involves some optical switching.(Please also see posts, in DODGY tech section,'Yard LED Lights...etc. for optical bench experiments'

author: RJSV
author_rank: Super Contributor
timestamp: June 09, 2022, 09:57:26 pm
content: I'd be interested in hearing more about thatPDM to PCM conversion, but for now will try WIKI, etc.Interesting, that a signal (like audio) would / could be sent, short-distances. If, somehow, send PDM (via low pass filter), and mix the 'Weighted PCM', with any old ANALOG (voltage). It's a bit lengthy explanation, but it seems the PDM (input signal) is, still, MIXER-READY, in a sense.However, certain input values need peak limiting ?Otherwise a '100%' value isn't a pulse anymore, (just a DC value, unchanging).

author: gf
author_rank: Super Contributor
timestamp: June 10, 2022, 06:45:32 am
content: STM has published an application note for interfacing digital PDM microphones:https://www.st.com/resource/en/application_note/dm00380469-interfacing-pdm-digital-microphones-using-stm32-mcus-and-mpus-stmicroelectronics.pdf

author: gf
author_rank: Super Contributor
timestamp: June 10, 2022, 07:39:56 am
content: Quote from: RJHayward on June 09, 2022, 09:57:26 pmIf you have a "clean" PDM signal (i.e. nice rectangular pulses with well-defined constant amplitude and exact timing of the edges) then all you need is a low-pass filter in order to reconstruct the analog signal. OTOH, a digital PDM signal does not need to be perfectly clean in this sense -- it is just sampled at the clock edes, and it is sufficient that the level at each sampling point can distinguish high and low. So the latter may not be "good enogh" for direct usage as analog signal after filtering, although it is perfectly OK as digital bit stream.QuoteI see basically no difference to an overdriven analog signal which gets clamped to a particular maximum and minimum level.

author: RJSV
author_rank: Super Contributor
timestamp: June 10, 2022, 09:25:56 pm
content: Thanks, gf, I'm trying to transmit, through a 'lossy medium', in my case using light, but could be ultra-sonic (remotes). So it's a problem, going beyond10 cm or so, just from simple attenuation, when a simple wire pair does that short-distance, without losses to worry about.By converting to PDM, or better, PWM, I can insert repeaters, to transport an analog value, without the loss factor introduced, by a little more distance.For example, picture shows 2 'gates' at 3 cm distance to receiver, while the 3rd gate is more distant, (but not by much); at 8 cm, from receiving sensor.For doing a D to A converter, that sort of distance-weighing can supply a direct 'weight' to a certain bit.But in the current example, it is wanted that each input have equal 'weight' to influence the receiving sensor.Could be acoustic system, with similar question, about how to 'move' an analog value around, while avoiding complicated analog 'repeaters'.

author: RJSV
author_rank: Super Contributor
timestamp: June 10, 2022, 10:32:38 pm
content: This latest diagram helps show how, using PWM type modulated (LED light) can transport an analog light level. In this case, that first gate, (lowe rt. in diagram), is converting to PWM as an output. No problems there, as there exists a Comparator along with independent 222 khz clocked output. Output is, for each gate, 2 usec. off / 2.5 usec. on.But, to move a signal, AFTER changing to pwm, can be done,...keeping careful that the final gate is spaced same, as other sources of light, into that upper gate.

author: RJSV
author_rank: Super Contributor
timestamp: June 10, 2022, 11:42:21 pm
content: Actually, my question is really with digital handling, of PWM signals. I'd think, for best extraction, a '100 %' signal would not have any low portion...just a steady DC value. Whereas, a '95%' signal still has that substantial low portion, for running a phase-lock loop, for example. It just seems, like some small upper limit, like 98 % of 6 volts (that being 5.88 v) would allow for easier tracking.

author: gf
author_rank: Super Contributor
timestamp: June 11, 2022, 02:51:52 pm
content: Quote from: RJHayward on June 10, 2022, 11:42:21 pmRegardinghttps://www.eevblog.com/forum/projects/efficient-pdm-to-pcm-conversion-for-precision-audio/?action=dlattach;attach=1508014:Mixing of two PWM signals with a simple binary OR works only If all (initial) PWM transmitters are synchronized, and if you can assign a dedicated time slot to each transmitter. I.e. each transmitter can only utilize a fraction of the total PWM period then.QuoteYou aim at clock/timing recovery? The interface of microphones with PDM output (that's what the OP was considering) typically has both, clock and data lines, so this is not an issue for the OP's use case. Sure, if the clock needs to be recovered, then NRZ is possibly not the best choice for the line code. Not utilizing the full range certain helps, in order to force a PWM or PDM signal to return to low and high at lest once during each period.QuoteWhy do you think it were better?Sometimes PWM may be more convenient, and most microcontrollers have hardware to generate PWM out of the box. But the most frequent use case of PWM is IMO not digital -> digital transmission, but rather simple D/A conversion, when the bandwidth * dynamc range product of the analog signal is not too high. However, at some point the required timing resolution becomes too high to be feasible. For instance, I see no chance to encode 24-bit audio data @48kSa/s with PWM in practice, as it would require 1.2ps (!) time resolution for the pulse width.IOW: As encoding for transmission to a digital receiver, PWM is very bandwidth-inefficient (particularly if a high dynamic range needs to be encoded), i.e. it can require a very fast link. OTOH, with PDM, the same bandwidth * dynamc range product of the analog signal can be encoded with a moderate oversampling factor, due to noise shaping, requiringsignificantlylower bandwidth and timing resolution for the encoded PDM stream.The above leads to the questions:What bandwidth and dynamic range of the original analog signals do you have in mind? (What is actually the origin of the signal you want to transmit?)How fast and how reproducable is the timing of your optical transmitters and receivers and other components in the signal chain (rise time, fall time, jitter, propagation dely)?How many different signals do you want to transfer to the common receiver?Is it possible to synchronize the (initial) PWM transmitters, and assign a time slot to each of them?Is a summation of multiple signals only required at the final receiver, or also at repeater nodes?

author: jonpaul
author_rank: Super Contributor
timestamp: June 11, 2022, 03:03:56 pm
content: Very fine discussionA bit of history please....In 1986..1989, I worked on the first digital microphone designed for NexT computer of Steve JobsWe filled a patent on the concept and built prototypes.I sat on Audio Engineering Société AES-42'standards committees to help write the standard for digital microphones.ST Micro was also there.We were finally granted a US patent years later.Bon SoiréeJon

author: RJSV
author_rank: Super Contributor
timestamp: June 11, 2022, 09:52:45 pm
content: Thanks for your help.The 'switching means' is slow, but I'm trying for 0 through 120 hz, that sort of thing, better for servo control, etc.I believe it takes, 500 usec average, so basic on-off rate limit of 1 khz, and...1/16 th of that would be about the 'performance' speed. That's, some 100 cycles that has to be 'illuminating' the sensor, before output switches to OFF state.The output is, literally, switched AC,...(Yeah...I know, lol),...so that 'presense' of signal is a digital 'ONE', while lack of signal, is a digital signal 'ZERO' state.The system has a 'sort-of' 'MODULATED DIGITAL' ideal, where, for example, a 'SET' signal input, to a FlipFlop, might occur, like, 12,000 times...Probably helpful when there is noisey lines, but...Incredibly, the latest round of improvements leads to a much simpler system, at least with less geometric problems, (fitting things in 3-D space).With the PWD format, should be easy, to implement 5 buts of D to A conversion, that is in optical terms, the intensity as analog parameter.

author: RJSV
author_rank: Super Contributor
timestamp: June 12, 2022, 02:53:03 am
content: Of course, the first goal, (with doing optical switching) is to experiment with making an A to D converter...kind of ironic now, since a key part could be, the single-bit form, of just that.Now, having PWM available, makes it possible to build an ANALOG MULTIPLYING DAC, by driving each bit not by the 'maximum' LED light intensity, but by the equivalent brought into the equation, via a PWM for each bit.Additionally, is the possibility, of building each PWM signal directly, skipping the steps. For example, if 'bit 1' in the D to A, is 25% of full scale, then every 4th pulse would be enabled.The A to D method, successive approximation, works by a, successive, 'Set and Test' for overflow, by the optical sensing 'gate'. Each time, a smaller bit istested, until the answer is resolved.(Sorry, that's a separate example, from the 'Multiplying DAC.)A very nice bonus, of all this is that any one gate can be run with 2 inputs, or 3, without forcing putting all the bits (likein one stage, (hard to fit).And, don't forget, that 'multiply and accumulate' thing is at the heart of FOURIER ANALYSIS.

author: RJSV
author_rank: Super Contributor
timestamp: June 13, 2022, 12:46:27 am
content: Here is a glimpse of how easy a PWM signal could be built:Viewing the diagram, that 'green' arrow dipicts an optical D to A Ramp generator. A 4 - bit counter runs upward, 0000 to 1111 binary, while a set of 4 pathways have the attenuation, appropriate. So there would be 50% of total, as bit3, etc. Let's assume, 1 LUMEN is 100 %....or is that way off for a 40 watt lamp, etc ?For the next bit lower; bit2, that's at weight equal 25 % and last two bits are 12.5 %, 6.25 %.So, anyway, the comparator operates, somewhat backwards in that the DtoA ramp generates a 'complement', rather than directly exact value.The ramp value is going to be 'twos complement'.At any rate, in the diagram, those two arrows, your input being the red, and the counter generated ramp being green arrow input, the device will stay ON until the ramp triggers it, very much like a simple circuit would use a ramp to time a pulse width.Of course, in all this, there must be an OPTICAL inverter, as the above gate, actually, goes to an OFF state, that being logical inverter.

author: RJSV
author_rank: Super Contributor
timestamp: June 14, 2022, 08:23:49 pm
content: This photo helps show my thoughts, about generating a varying width pulse, using the comparator built-in. A ramp generator adds to the 'sample' input, basically until the combination, of all inputs adds up, to cross threshold...then the inverted output goes 'low', (dark).The point is here, that the D to A doing the ramp can be split up; at lower rt. you can see, three gates do the low weights, of bit0, bit1, and bit2. Meanwhile that combination is converted, to pulse-width. Of course a controller / sequencer starts -stops these repeating cycles.The PWM conversion allows simple geometric 'fit' and spacing to not be so critical, especially when getting into some wider, more sensible Analog result values, like 8 bits resolution.The diagram shows, the 3 lowest bits, of a 5 - bit A to D, can be 'packed' and brought to the upper gate, there in the diagram. The upper gate then combines in the 2 upper bits, bit3 and bit4. Each bit weight can be modified, according to distance the optical signal is placed, or using other means, such as a light attenuating film, (more attenuation on lowest bits).So the use of PWM in a repeating cycle, right now thinking at 50 hz sample period. Each cycle, the ramp starts up, in 32 steps (5- bit D/A ) until threshold, then the pulse output ends. Needs simple inversion to do positive PWM output, optical.

author: gf
author_rank: Super Contributor
timestamp: June 14, 2022, 09:13:56 pm
content: Sorry, dont understand. You say it is supposed to be a SAR ADC.Where is the analog input which is supposed to be converted?Where is the analog comparator required by a SAR ADC?The DAC can be realized via PWM, but where is a low-pass filter in order to convert PWM to analog so that it can be fed into the comparator?

author: RJSV
author_rank: Super Contributor
timestamp: June 16, 2022, 04:27:51 am
content: It's a bit roughed out so far. The analog is the light being applied to surface of solar cell, that being also used as a sensor...with comparator, for shut-off at top end (of ambient light intensity).The whole thing is, admittedly, a bit hokey, but still interesting. The A to D works by putting weights on each bit...whether by a 'film' cutting down a certain amount of light (like to 12% for example).The sequence is, to SET a bit, (starting at highest), then test for 'overflow' and conditionally CANCEL. Then, move on, to repeat, for each bit.The use of the 'comparator true' condition, seems a bit of a trick...but it works.

author: RJSV
author_rank: Super Contributor
timestamp: June 16, 2022, 05:16:35 pm
content: Thanks for the question. One goal is to be able to 'move' an analog (light intensity) signal, as conveniently and naturally as WIRES do, or some semblance of that. The 'gates' being mentioned are those common, simple 'yard lights'...Solar lights that resemble 'Hockey Pucks', little disks. Trying out arrays in larger bunches, 60+ >>.The D to A bit weights can be done by simple distances, but it still gets tedious, above about 4 inputs, in terms of 3-D fit, but also requires surrounding logic elements to fit some 'layout' that is undesirable for whatever reason...By going to PWM transmission, even for ridiculously short hauls, some more organized layouts can be accomplished. That means various FlipFlops and counting registers, along with signal switching on BUS structures.

author: RJSV
author_rank: Super Contributor
timestamp: June 18, 2022, 09:20:15 pm
content: Here is a diagram, showing what is needed, just to do one optical switched bit. (Apologies to OP, if this post getting too much).The typical circuit is for simple copy, of INPUT flipflop to OUTPUT stage FlipFlop. A highlighted signal shows where a signal (or pulse of light) would be, when reset is about to occur...of the output stage.This kind of two-stage arrangement gets around the thorney issues, of switching speed, some 1.2 mSec. average.To build a 4-bit ramp counter would take 32+ of these gates, if you figure (at least) 8 per counter bit.For this and other reasons (speed), a ramp timer doesn't seem too efficient. But...the counter logic is still needed elsewhere.That diagram helps give a sense, for how the gates get spaced, relative to each other. Actually, the cheap small solar cells are quite weak, so device spacing is critical - kinda sucks.

author: RJSV
author_rank: Super Contributor
timestamp: June 18, 2022, 09:29:54 pm
content: It's hard to notice, tracing through the tedious inverter actions, at each gate, but the arrangement here is for Toggle type action, so the wrap-around signal pair is reverse connected, so a '1' gets copied as a '0' and a '0' gets copied as a '1', that being done by (separate) clock edge.For each counter stage, a typical falling edge circuit will toggle each next counter bit stage, for a typical ripple style counter.

author: RJSV
author_rank: Super Contributor
timestamp: June 20, 2022, 05:02:03 pm
content: Doing some homework-study, on YouTube, on the subject: 'Delta Sigma Modulator Basics',The 6 minute, by Fernando Zigur, is a good start,Plus Hackaday has produced informing video.

author: RJSV
author_rank: Super Contributor
timestamp: June 25, 2022, 10:53:00 pm
content: gf thanks, I've seen your questions, but need more (study) time.But can give tentative answer, no proof yet, but I'm leaning towards thinking that a fairly 'random enough' process, could substitute for PWM that is Synchronized perfectly...similar to how an audio speaker can be sent 'multiple modulated' waveforms. Sending a fixed 2 khz 'beep', while modulating the digital beep-enable line at, say, 200 hz, will allow that lower tone sound to be audible.So I'm thinking, on average, to try just ignore the obvious requirement, and evaluate what possible cr#p or not is result.