Generic questions about SDRAM controllers - Page 1
Forum section: electronics / projects

author: betocool
author_rank: Regular Contributor
timestamp: June 11, 2022, 02:16:00 pm
content: Hey all,I've been reading some lately about SDRAM controllers, my interest triggered by my increased use of FPGAs and Risc-V processors.In the past I'd only used SDRAMs as a PCB designer and firmware person. I was happy to be able to run a 233MHz SDRAM with an STM32F7, using the F7's SDRAM controller. Once you make sure it works, you forget about it!But now I'm considering implementing an SDRAM controller for an FPGA dev kit. Intel/Altera have removed their SDRAM controllers in their latest revisions, so I'm looking at different open source options, as well as giving it a crack myself. I'm in no particular hurry, so all good.So far what I understood is this (an feel free to quote and correct where it's wrong!).SDRAM chips are slower than SRAM chips, but they can pack a lot more information in the same space, due to their differences in cell build. SDRAM chips have in bank-row-column addressing scheme.Commands must be sent using the RASn, CASn and "other" pins (I forget the details). Example, before a read, I have to send a "read" command by setting those pins correctly. Additionally, reads usually take 2-3 cycles to complete, whereas a write is on the same cycle.Because of how the SDRAM is build, it's necessary to "recharge" the memory bits by sending a "refresh" command every so often, usually 8192. refreshes every 64 ms. That comes to 1 refresh every 7.8 us. Or you can decide to refresh all every 64ms. The SDRAM internals take care of what needs to be refreshed.Depending on the model, it's possible to set x1, x2, x4 and x8 "burst" write or read commands, increasing performance slightly.Ok, worst case then is a read command individually, which is about I'd say 25% efficient, on a 100MHz memory you "only" get effectively 16 bits at 25MHz, which still is a pretty decent 400Mbps.My questions are regarding controllers then. Without knowing much about the application, how does it know if it bursts data in or out? How would it know if the data is still on the same bank, column or row? How does it know it will finish before it needs to refresh? My guess is a very simple controller would just go worst case for all and read/write 1 word at a time and screw efficiency. But to achieve higher throughputs, how do they increase efficiency? Unless you program a defined transfer a la DMA, there's no way of knowing how much data will come and if I can burst it or not...Basically, where do you draw the line between the firmware and the hardware?If anyone can point out good information about Verilog or VHDL controllers with good documentation as well, that be great!Cheers,Alberto

author: ataradov
author_rank: Super Contributor
timestamp: June 11, 2022, 04:47:23 pm
content: Generic controllers often provide SRAM-like interface to the rest of the system. You set the address, provide the data for writes and control signals (read/write). The controller internally keeps track of the page it has open, refresh times, and all the rest. It provides an acknowledgment signal when the requested operation os over. This type of interface makes it trivial to integrate into the system and you don't have to worry about anything.This is the only way to implement it if you want SDRAM be memory-mapped (as in STM). All the commands must be issues by the SDRAM controller itself. Once it is configured, there should be no need for firmware interaction.