Help Needed To Set Clocks with PIC16F18456..I'm totally confused! - Page 1
Forum section: electronics / general

author: Salome2
author_rank: Regular Contributor
timestamp: October 07, 2024, 05:44:19 am
content: The 16F18456 seems to have so many clock settings.The attached RefClkEnigma shows Fosc as a clock source when Fosc is always turned off in sleep!In particular, I want to use the Reference Clock for the clock for TMR1 because it will still run in SLEEP mode.If I set TMR1CLk to Fosc or Fosc/4 system clock, TMR1 works as expected, but when I switch the setting to Reference Clock I get aclock that quits after about a minute..just stops!From what I see on my scope, I seem to have set Fosc to 64mHz!I need help setting up aninternal clock sourcefor TMR1 to work at highest speed in sleep mode.//-------------------------------Configuration Words-----------------------------------#pragma config CLKOUTEN=1 //CLKOUT is Disabled#pragma config FEXTOSC=4 //External Osc Disabled#pragma config RSTOSC=0 //HFINTOSC 32MHz startup osc//------------------------------------------------------------------void Init_TMR1(){ // TIMER1 overflows at 65536 clocksT1CKPS0=1; // Set TMR1 prescaler 1:8 HFINTOSCT1CKPS1=1; // 0x11 = 1/8 PrescalerTMR1CLK=0x01000; // Reference Clock Output(stays awake during sleep)CLKRCON=0b10010000; //HFINTOSCCLKRCLK=0b00000001; //RefClk 50%DC No prescaleT1CONbits.RD16=1; // 16-bit read and write of TMR1 doesn't work?TMR1IF = 0; // clear TIMER1 interrupt requestTMR1IE = 0; // disable TIMER1 interruptPEIE = 1; // enable peripheral interruptsTMR1ON = 0; // Disable TMR1 until started by bell detection routineTMR1H = 0;TMR1L = 0;}void Init_PIC(){OSCCON1=0x10; //32-MHz 2xPLL of 16MHz HFINTOSC (bits 0-3 are Clk Div)OSCFRQ =0x110; //16Mhz HFINTOSC selected to feed 2x PLLHFOEN =1; //HFINTOSC explicitly onPEIE = 1;}I have attached copies of the specsheet pages applicable to setting up clocking.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 07, 2024, 03:57:20 pm
content: The timer is not an independent clock source. It simply counts pulses of an underlying clock source. If the underlying clock source stops, the timer stops too.

author: Salome2
author_rank: Regular Contributor
timestamp: October 07, 2024, 05:27:23 pm
content: NorthGuy, Thanks, but I know that a timer doesn't work without an oscillator clock source. I just stated my question poorly, but I have edited my opening post and fixed that path to misunderstanding.With the 16F18456, there are a lot of possible settings (and not so obvious missteps) to setting up clocks and oscillators.My Question:What am I doing wrong in configuring the Reference Clock for Timer1?Is the code below at fault?OSCCON1=0x10; //32-MHz 2xPLL of 16MHz HFINTOSC (bits 0-3 are Clk Div)OSCFRQ =0x110----------------------------------Is the CONFIG 1 setting wrong?#pragma config CLKOUTEN=1 //CLKOUT is Disabled#pragma config FEXTOSC=4 //External Osc Disabled#pragma config RSTOSC=0 //HFINTOSC 32MHz startup osc--------------------Is my TMR1 clock setup for the Reference Clock source wrong?T1CKPS0=1; // Set TMR1 prescaler 1:2 HFINTOSCT1CKPS1=1; // 0x11 = 1/8 PrescalerTMR1CLK=0x01000; // Reference Clock Output(stays awake during sleep)CLKRCON=0b10010000; //HFINTOSCCLKRCLK=0b00000001; //RefClk 50%DC No prescale

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 07, 2024, 10:20:53 pm
content: Quote from: Salome2 on October 07, 2024, 05:27:23 pmYes. The value for OSCFRQ is wrong. I think you got confused between values in hex and values in binary. OSCFRQ is an 8-bit register with only bits 2:0 used. 0x110 is a hex literal requiring 9 bits. With this value, it actually sets bits 2:0 to all 0, which is a reserved value.The correct value for a 16 MHz frequency for HFINTOSC (which will give 32 MHz with the 2xPLL option) is 101 (binary), so 5 in decimal or 0x05 if you prefer hex.So that should be:OSCFRQ = 0x05Quote from: Salome2 on October 07, 2024, 05:27:23 pmIt appears correct. Note that for RSTOSC, this defines the startup config. But you change it later on to 2x PLL, so this setting could be also 1, or 6 (slower) or even 5 (slower yet). Doesn't really matter as long as you use an internal oscillator, the oscillator will be reconfigured when you set OSCCON1 and OSCFRQ.Also note that there are two ways of setting 32 MHz from HFINTOSC. Either directly, or via the 2x PLL (the latter being what you set with OSCCON1 and OSCFRQ). There is no 64 MHz setting possible from HFINTOSC.Quote from: Salome2 on October 07, 2024, 05:27:23 pmYou seem to have again mixed hex literals with binary for TMR1CLK. '0x' prefix is hex, '0b' is binary. So, another thing to fix.'TMR1CLK=0x01000' will actually set 0 to TMR1CLK.You seem to have swapped the comments for CLKRCON and CLKRCLK.CLKRCLK sets the clock source, CLKRCON set the base divider and duty cycle. Other than comments, the values seem correct here.

author: Salome2
author_rank: Regular Contributor
timestamp: October 07, 2024, 10:56:40 pm
content: SiliconWizard, I seem to be more of a Germanium Goof! I didn't realize how bad my misunderstanding of hex, binary and literals are.Thank you so much for helping me out and pointing out my coding has such beginner's errors.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 07, 2024, 11:22:22 pm
content: Quote from: Salome2 on October 07, 2024, 10:56:40 pmDoes it work now?

author: NorthGuy
author_rank: Super Contributor
timestamp: October 07, 2024, 11:47:11 pm
content: You don't need to manipulate OSCCON. The chip will set it to 32 MHz for you once you configured RSTOSC. You only need to do this if you want to switch clock frequency in run time. But, this sets the CPU clock - FOSC - which is shut down during sleep no matter what it is. Hence these settings don't matter during sleep.If you want to use something during sleep, you need to run it from one of the oscillators, not from FOSC. The highest frequency would be HFINTOSC (High Frequency Internal Oscillator), with the frequency regulated by OSCFRQ register up to 32 MHz. However, the faster you run it, the more energy it consumes.If you also run CPU from HFINTOSC (as you do), the HFINTOSC's frequency will affect the CPU as well.

author: Salome2
author_rank: Regular Contributor
timestamp: October 08, 2024, 01:33:13 am
content: SiliconWizard, Thanks for your valuable attention.I changed:OSCFRQ=0x110; 0x110--------> =6;OSCCON1=0x10; 0x10---------> =2;TMR1CLK=0x01000; 0x01000 ----> =8;Unfortunately the ship yet does not stay afloat. TMR1 flatlines after about 10-secs now!

author: Salome2
author_rank: Regular Contributor
timestamp: October 08, 2024, 02:00:11 am
content: Thanks NorthGuy for the heads up! I will switch frequencies.My Bubba method to identify a consistently fixed waveform doorbell tone is to put everything to sleep except Cmp1 (comparator) to detect a tone burst.At the start of doorbell tone burst, amplitude detection by CMP1 triggers C1IF and this must wake up the system and TMR1 must startup to record the raw value TMR1 counts of Cmp1 Interrupt triggers and store each value in an integer array to be analyzed after 65535 TMR1 counts ends the sampling period.So, the Reference Clock is only required to provide a high speed clock for Cmp1 while the MCU sleeps, awaiting a doorbell ring sound.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 08, 2024, 03:39:33 am
content: Quote from: Salome2 on October 08, 2024, 02:00:11 amBy your description, it doesn't sound like you need a timer during sleep because you start it only upon wakeup.Quote from: Salome2 on October 08, 2024, 02:00:11 amThe Reference Clock is a clock divider which takes an existing clock and produces a different lower frequency clock. It is of no use to you.

author: Salome2
author_rank: Regular Contributor
timestamp: October 08, 2024, 04:19:25 pm
content: NorthGuy, thanks for pointing out to me the the Reference Clock is not needed.All I need to use is HFINTOSC with prescalers when appropriate. I had the wrong idea that HFINTOSC was turned off during sleep.I still have bad clock setup and I must go back and study the specsheet again to try to understand what I am attempting to do!

author: Salome2
author_rank: Regular Contributor
timestamp: October 09, 2024, 11:11:56 am
content: Update, now getting to clearly understand how to set clock resources and how code can request a clock freq. change and pole status regs to know when the freq. change is complete.My biggest problem was confusing 0x with 0bwhich allowed me to make absurd clock and TMR1 settings and yet wonder why things were working truly screwy.i went back to studying the specsheet again to finally have a clear understanding of the simplified TMRx and Osc block diagrams.Many more thanks to SiliconWizard and NorthGuy!