DipTrace: nets and routing bypass capacitors - Page 1
Forum section: electronics / projects

author: Jacky_88
author_rank: Contributor
timestamp: March 02, 2018, 10:01:34 am
content: Hello engineers,currently I'm working on a pcb. Since there are severeal ICs I'm using bypass capacitors. The image attached to this post shows the schematic of these capacitors. In my pcb design the +3V3 derives from a power plane (4 layer design) and turns to VDDIO which is fed to the IC. Two vias are needed to do so:(+3V3 plane)-->(via)-->(caps)-->(via)-->(VDDIO IC)My problem is, that +3V3 and VDDIO are seen as one net since they are connected in the schematic. In the pcb design both vias are connected to the power plane and by updating the copper pour the capacitors are shorted.So, how can I tell diptrace, that the capacitors are no longer to be connected to +3V3 but are a new net?

author: Ash
author_rank: Regular Contributor
timestamp: March 02, 2018, 10:51:33 am
content: Hi Jacky,The problem is you don't have different "nets". The labels are connected to exactly the same logical circuit point and so the behaviour is what is expected.If you want to separate the nets you would actually need to place a part between them. For instance a zero ohm link (resistor). You might also consider a ferrite bead if you are attempting to isolate sections of power to aid in noise suppression.The real question is what are you trying to do in the circuit that needs the isolation as that will better inform us so we can suggest a good solution.Hope that helps.Cheers,Ash.

author: Jacky_88
author_rank: Contributor
timestamp: March 02, 2018, 12:48:27 pm
content: Hello Ash,thank you for your help. The actual pcb design is not subject of my question. It's a arduino like thingThe solution you suggested requieres additional physical parts thus requiering more precious space. If there is no "easy" solution for my problem, I can route it manually. But since this might be a quite commen problem there might be solution. On the other hand I could symply use a power trace as gap between via and power plane..

author: Bassman59
author_rank: Super Contributor
timestamp: March 02, 2018, 07:48:17 pm
content: Quote from: Jacky_88 on March 02, 2018, 12:48:27 pmLike Ash, I’m confused about what you’re really trying to do.First, you tied the +3V3 to the VDDIO by putting two net labels/power symbols on the same wire. In general, that’s a bad idea. Usually that indicates the person drawing the schematic made a mistake.But more to the point. You said this was an “Arduino-like thing.” Does that mean that you attach another board to yours, and that other board has +3V3 and VDDIO signals which drive yours? In that case, the two signals must be separate, and you do need separate decoupling caps on the relevant pins on your chip.If your design supplies both VDDIO and +3V3 to the other board, and VDDIOis+3.3V, then you connect +3.3V to the VDDIO pins. On your board, they are just one net.More details will allow us to help.

author: sleemanj
author_rank: Super Contributor
timestamp: March 02, 2018, 10:45:46 pm
content: I think the problem is you are trying to dictate layout in the schematic, this is not typically done to any degree more than putting a note on the schematic or some document so the person doing the layout knows to lay it out like you want.In terms of connection, all the varieties of ways those capacitors can be layed out are equvalent, in terms of connection your two net labels are directly connected and reference therefore the same set of connections, what is connected to one, is connected to the other. But in terms of layout and wrangling electrons where you want them, you might indeed have more demands. A trivial example is decoupling caps being "near" to an IC, the schematic does not say this, it's extra information, usually unsaid because the layout designer just knows, but they could put that cap on some long and windy trace all the way over the other edge of the board and the net connectivity test would still pass.One situation where what you want is common for example is splitting your ground into digital and analog grounds, they are both ground at the supply eventually but you want them separate until some specific point, so you create as well as your real "Gnd" net labels an "AGnd" for the analog things and connect the analog one to the real one via a component (ferrite, 0-ohm link, solder bridge...) to separate them.If a component to seperate is undesirable, you can always put in a placeholder component and then replace it by a trace in the pcb layout as the last thing you do, or use a component with two pins and a pattern that has two very small surface pads and a copper line between them as a faux-trace, it would be flagged as a drc fail is all.

author: CraigD73
author_rank: Contributor
timestamp: March 07, 2018, 05:36:50 am
content: Don't put two names on a net that will cause you all sorts of grief in DipTrace. Call the net one or the other. Don't let diptrace name your nets from the symbol pin name the libraries are not always consistent. Name the net manually and connect it to the pin you want -- nothing magic about power nets they are just named nets. Also learn how to use connect "connect nets by name"Craig

author: Neilm
author_rank: Super Contributor
timestamp: March 07, 2018, 07:16:35 pm
content: Quote from: CraigD73 on March 07, 2018, 05:36:50 amIt will cause all sorts of problems in any PCB package.