D-Latch immunity to ESD - Page 1
Forum section: electronics / projects

author: brumbarchris
author_rank: Regular Contributor
timestamp: November 24, 2022, 02:37:03 pm
content: Hello,I have difficulties with the lack of immunity to ESD of a 74LVC2G74 D-type latch. The latch is mounted on a small PCB with quite a lot of components on it, which is placed in a metallic housing. The GND of the PCB is also electrically connected to the housing itself. The whole thing is battery powered. An FPC cable, about 5cm long, is routed outside of the housing with some pads at its far end, which represent the landing pads of some pogo pins of another piece of equipment (which, nevertheless is not currently attached, so the pads are fully exposed at the moment).Whenever we do contact discharge with +/-4kV on some of the pads available on this FPC (including a GND pad), the latch output inadvertently changes state. Its output is driving the Enable pin of a TI LM73100 smart-switch which is then inadvertently activated/deactivated (depending on its previous state). Curiously enough, when air discharging against the metallic housing, nothing happens.As you can see in the schematic below, the D and CLK lines of the latch are connected to GND. The latch is operated by momentarily asserting LOW its CLEAR and PRESET inputs which are connected to two output pins of the microcontroller. I can confirm that in case of the ESD event the microcontroller is not actively driving the pins, we have indications it keeps its intended state all throughout the occurring of the ESD event.So for we have tried the following:- added a1uFdecoupling capacitor for the latch itself, straight across the VCC and GND pins (yeah, I know what your're thinking about it being absent to begin with)- adding some capacitance on the CLEAR and PRESET inputs of the latch;4.7nFdid not help,100nFdid not help. Admittedly, such capacitance is not really healthy for the microcontroller pins themselves, without some additional series resistance, but it did not solve the problem anyway; the speed with which the micro actuates the latch output is not important.- configuring the microcontroler pins as push-pull or open-drain makes no difference- decreasing the pull-ups on the CLEAR and PRESET inputs to 10k did not help- making a stronger GND connection between the CLOCK and DATA pins and the GND pin of the latch did not help either; these pins are connected to the underneath GND plane with dedicated vias, and I added a 0.25sqmm wire directly on the pins of the IC. But as I said, it did not workI am running out of ideas on what else to try, so help on the matter is welcome. The schematic and relevant layout portion are attached below.Regards,Cristian

author: mag_therm
author_rank: Frequent Contributor
timestamp: November 26, 2022, 03:22:20 am
content: It might be necessary to remove the D FF as being un-necessary and not appropriate for the HV test.Change to a device that recovers to the correct initial state after any transients.Add filter so that short time transients do not get through.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 26, 2022, 04:41:04 am
content: Show the rest of the board. The tiny excerpt here tells us nothing of how the ESD is getting to the chip.The extremely high impedances (100k) around it wound seem to be a target; but they might be driven elsewhere (an MCU?), we have no idea.Tim

author: David Hess
author_rank: Super Contributor
timestamp: November 26, 2022, 01:40:35 pm
content: How do you know that it is not the microcontroller outputs which are glitching?

author: jkostb
author_rank: Regular Contributor
timestamp: November 26, 2022, 01:59:28 pm
content: The ESD is probably coupled into your board at the cable. Place on all inputs TVS diodes and add if signal permits ceramic capacitor (e.g. 0805 10nF). Also add some resistance in series. Ensure that your PCB is also connected to metal housing in neighboorhood of where the cable enters the housing.

author: mag_therm
author_rank: Frequent Contributor
timestamp: November 26, 2022, 03:47:08 pm
content: In my experience with cmos in high noise, the D FF was used but only in conjunction with close by on-board packages.BrumbarChris indicates the Q can toggle toeitherstate during the event, which may be indicating activity on the D and CP ground tracks.Assuming that the hardware latch is actually needed on the microcontroller output, try a crossed nand latch,preferably the Schmidt version if available in 3.3V. That latch was successfully used for incoming noisy signals.It requires the incoming line to transition across the threshold for a gate delay, and the delay can be augmented if necessary.

author: brumbarchris
author_rank: Regular Contributor
timestamp: November 28, 2022, 09:00:52 am
content: QuoteWe did add up to 100nF capacitors on each of the CLR and PRE inputs, with not help.QuoteLatch inputs are driven by the MCU. Initially we had the MCU outputs set to open drain configuration, but changing them to push-pull did not help either. Nor changing the R68, R69 pull-up resistors to 10k (from 100k)QuoteThis could be something. but having added 100nF on the latch inputs we hoped any microcontroller "glitching" would be suppressed. I will cut off the tracks to the micro and see if that helps, we should then know for sure if it is the micro causing it or not. It is low probability, as everything else on the board still operates correctly, I would imagine we would see many other failures if the micro pins would be "glitching"QuoteWe suspected that too. Therefore I have soldered a supplemental short wire wire between these two pins and the GND pin of the latch itself, again, with no success.Regards,Cristian