Do I need an OR Gate? - Page 1
Forum section: electronics / beginners

author: sci4me
author_rank: Regular Contributor
timestamp: June 17, 2015, 05:42:07 pm
content: Hey guys! Quick question about the highlighted node in the image below:Do I need to use an OR gate? Or will it work by just connecting them like I have?

author: MatthewEveritt
author_rank: Unknown
timestamp: June 17, 2015, 05:45:00 pm
content: You need an OR gate, otherwise when one is high and the other low they're fighting each other, which is a good recipe for damage. You might be able to get away with it (datasheet might tell you), but IMO it's not worth it. A couple of diodes would be OR-gate enough.

author: c4757p
author_rank: Super Contributor
timestamp: June 17, 2015, 05:57:24 pm
content: You're making a mistake I see from beginners quite frequently in digital logic: assuming that there is a "default" logic level. That is, if one of them is outputting 1 and the other 0, 1 will "win" because there's something special about a 1. Similarly, I often see people assume that disconnected inputs are zero (also not true).It's equally possible that the one outputting 0 will win. Another likelihood is that it'll sit somewhere in between, giving an invalid logic level to the next stage and risking damage with excessive power consumption (as the one outputting a 1 tries to pull the 0 upwards, and the one outputting a 0 tries to pull the 1 downwards).

author: Yansi
author_rank: Super Contributor
timestamp: June 17, 2015, 05:58:55 pm
content: Put there 7406 with pullup.

author: c4757p
author_rank: Super Contributor
timestamp: June 17, 2015, 06:00:55 pm
content: Quote from: Yansi on June 17, 2015, 05:58:55 pmErm... that makes AND, not OR.

author: sci4me
author_rank: Regular Contributor
timestamp: June 17, 2015, 06:03:55 pm
content: Alright so that makes sense. About the diodes, this is what you mean?Also, that was just a random value diode I picked - what kind of diode should I be using?

author: dfmischler
author_rank: Frequent Contributor
timestamp: June 17, 2015, 06:06:03 pm
content: If you actually build it with real LS TTL parts as shown then low will win because TTL gates won't source much current, but can sink quite a bit. So that means the pair of inverters wired that way acts just like a NOR gate. Bets are off if you actually used CMOS parts.

author: sci4me
author_rank: Regular Contributor
timestamp: June 17, 2015, 06:09:38 pm
content: Yeah, I am using 74LS parts. So the configuration posted will do what I want then...

author: dfmischler
author_rank: Frequent Contributor
timestamp: June 17, 2015, 06:11:59 pm
content: The way you connected the diodes they will only pass current sourced by the inverters (not much for real TTL). It might work that way, but an experienced TTL designer back in the day would not be likely to do it that way. If you turn the diodes around then they will pass current sunk by the inverters and you will have your NOR function. I very highly doubt that any damage would result from leaving the diodes out.

author: sci4me
author_rank: Regular Contributor
timestamp: June 17, 2015, 06:14:46 pm
content: Quote from: dfmischler on June 17, 2015, 06:11:59 pmWell from what was previously said, the way I understand it is that if one of the outputs of the inverters was 0 and one was 1, it could become an invalid state right?So I need to do something don't I?

author: dfmischler
author_rank: Frequent Contributor
timestamp: June 17, 2015, 06:24:56 pm
content: Quote from: sci4me on June 17, 2015, 06:14:46 pmNo. Look at the circuit for aTTL totem pole output.When the output of the 74LS04 is low the bottom transistor is pulling the output to ground though the lower NPN transistor. When the output is high there is a transistor, and a resistor in the path to Vcc. Low will win every time. Thedata sheetsays an LS04 can sink about 8 mA, but can only source 400 uA. You are theoretically supposed to use open-collector parts for wired-OR gates like this, or for pulling down serious current, but it is very unlikely that anything will be damaged in your circuit.If you were using CMOS parts the answers would be different because then the outputs would be pulled right to the rails and something would probably burn up.

author: sci4me
author_rank: Regular Contributor
timestamp: June 17, 2015, 06:29:50 pm
content: Quote from: dfmischler on June 17, 2015, 06:24:56 pmOkay so that makes sense - why low will win. But I still don't quite see why that means I can just do nothing (use the original configuration I posted).

author: suicidaleggroll
author_rank: Super Contributor
timestamp: June 17, 2015, 06:35:40 pm
content: Quote from: sci4me on June 17, 2015, 06:29:50 pmHe's just describing why it won't self-destruct. It still won't be an OR gate though. Since low wins, it's going to be a NOR gate (the output will only be high if both inputs are low).

author: Yansi
author_rank: Super Contributor
timestamp: June 17, 2015, 06:41:34 pm
content: Quote from: c4757p on June 17, 2015, 06:00:55 pmNOR, to be exact. Let's draw a truth table: A, B being the inputs, X,Y outputs of the two opendrain gates and Q the two tied together. That is aNOR.A B | X Y | Q0 0 | 1 1 | 10 1 | 1 0 | 01 0 | 0 1 | 01 1 | 0 0 | 0

author: c4757p
author_rank: Super Contributor
timestamp: June 17, 2015, 06:48:31 pm
content: When combined with the inverters, yes. That's not what he asked about.

author: dfmischler
author_rank: Frequent Contributor
timestamp: June 17, 2015, 06:48:47 pm
content: Quote from: sci4me on June 17, 2015, 06:29:50 pmLook at the data sheet. The short circuit output current for the 74LS04 can be up to 100 mA for 1 second as long as only one output from the package is shorted at a time (I OS on page 6). Even if you were pulling the totem pole output directly to ground the current would be limited by the collector resistor on the upper transistor to around 30 or 40 mA. So the package would survive and continue to function.And yes, it will be a NOR function as I originally said.

author: sci4me
author_rank: Regular Contributor
timestamp: June 17, 2015, 06:54:28 pm
content: Quote from: dfmischler on June 17, 2015, 06:48:47 pmOkay I think I get it. If I were to just connect the outputs of the inverters to the input of the AND gate it would act as a NOR gate - the input of the AND gate would be the NOR result of the two inverters because Lo wins (hope I got that right).But this is not what I want. I want the input of the AND gate to be the result of an OR operation on the outputs of the two inverters.

author: Yansi
author_rank: Super Contributor
timestamp: June 17, 2015, 06:59:29 pm
content: Quote from: c4757p on June 17, 2015, 06:48:31 pmOK, pulldown with two diodes is also a way to go. (if speed isn't the issue).

author: dfmischler
author_rank: Frequent Contributor
timestamp: June 17, 2015, 07:07:50 pm
content: It sounds like you really want a NAND function on the inputs to the inverters. Adding an OR gate would do it, or removing the inverters and using a NAND gate.QuoteYou will never see a good TTL circuit using diodes and pulldowns in this way because the gates can't supply enough current for reliable operation. It can work well for CMOS, though.

author: sci4me
author_rank: Regular Contributor
timestamp: June 17, 2015, 07:12:24 pm
content: Quote from: dfmischler on June 17, 2015, 07:07:50 pmI want 3 inputs (A, B, C) and 1 output (Y) and I want the value of Y to be 1 if A OR B is 1 AND C is 1.The two inputs, A and B are theinputsoutputs to the inverters. The C is the other input to the AND gate, the one that goes off the screenshot.

author: Yansi
author_rank: Super Contributor
timestamp: June 17, 2015, 08:15:01 pm
content: Quote from: dfmischler on June 17, 2015, 07:07:50 pmSorry, I haven't noticed the LS logic. I wouldn't use that in yr 2015 anyway, unless you want to build a TTL museum.

author: tautech
author_rank: Super Contributor
timestamp: June 17, 2015, 08:51:46 pm
content: I've found these applets handy to give guidance when "you can't see the wood for the trees".https://tams.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/chapter.htmlThey've even helped me to select a better logic device for a project