Are there any affordable, multi-channel PWM generator chips available? - Page 1
Forum section: electronics / beginners

author: LinuxHata
author_rank: Frequent Contributor
timestamp: June 21, 2025, 05:10:45 am
content: Hello.I was looking for a chip, which can be interfaced to MCU via SPI/I2C/Whatever and can output different duty cycle PWM signal at different pins. To my amusement, there are only couple of such chips, all made by Linear (LT8500 as example), so all of them have prices that are not hobbyist friendly. So, the question is, whenever there are such chips, but in a cheaper region?Yes, I know I can use MCU for that, and I'm currently doing so. However, generating 32 channel PWM signal with even dedicated MCU is quite tricky, and you will only get relatively low PWM frequency, which might lead to flicker or hum in final application.So if there's any other chips, capable of at least 24 independent channel PWM output, besides LT8500, I'd be very glad to hear about them.

author: BadeBhaiya
author_rank: Regular Contributor
timestamp: June 21, 2025, 08:26:12 am
content: What's your application btw? Im assuming the PWM need to be adjustable? Is it okay if they're duty cycle adjustable but not frequency adjustable?

author: tszaboo
author_rank: Super Contributor
timestamp: June 21, 2025, 09:56:25 am
content: You can try something like the PCA9685 for slow PWM signals. They make very cheap boards for it.

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 21, 2025, 03:00:28 pm
content: Yes there are lots of options out there, like the one tszaboo mentions above. Some are tailored to certain applications like LED drivers or motor control. Hard to recommend anything specific without knowing more about your application.

author: LinuxHata
author_rank: Frequent Contributor
timestamp: June 22, 2025, 06:08:52 am
content: Thanks, my requirements are as follows:1. No BGA or DFN packages - it should have pins, SOP, SSOP , SOIC is ok.2. Output should be able to both source and sink current as needed. Up to 5mA current per output pin.3. PWM resolution 8 bits, no need for 10-12-16 etc.4. PWM frequency should lie above hearing range - >18kHz, but no higher than 50kHz.5. If there will be ability to sync PWM pulses across several chips - very good.6. I only need to adjust duty cycle of each output independently, no need to have separate frequencies.7. More outputs per single chip - better it is. I need 48 outputs total, so I'd prefer to go say, 2x24 chips than 3x16, but latest is also ok, if it's cheap.

author: ledtester
author_rank: Super Contributor
timestamp: June 22, 2025, 10:12:24 am
content: Have a look at the "Serial Wombat" SW8B - a very recent Kickstarter that claims to be OpenSource:https://www.kickstarter.com/projects/bwci/serial-wombat-8b-i2c-i-o-boards-big-features-small-moneyExplanatory video:64 Analog Channels for $6. Or 64 PWM, or 64 Servo or... SW8B 8x board, PCB0035 - I2C to ADChttps://youtu.be/kDrOC3F2tO4The Kickstarter is over but the video mentions that the board should be available on Amazon by late summer/fall. The guy has other "Serial Wombat" offerings on Amazon.

author: Nominal Animal
author_rank: Super Contributor
timestamp: June 22, 2025, 01:15:07 pm
content: NXP PCA9685that tszaboo mentioned has 16 channels per chip, but is limited to 24 Hz .. 1526 Hz.It is very hard to beat CH32V006 (CH32V006F8U6 QFN20 = $0.14 apiece in sets of 5at LCSC, which gives you 4+3 hardware PWM outputs (two separate timers), leaving I²C (master or slave), UART, and SPI usable, needing only one 1µF or so supply bypass capacitor, and can work from 2.8V to 5.5V. With exact 8-bit PWM (duty cycles 0..255), you're limited to frequencies 187.5kHz/N, i.e. 23.4kHz, 26.8kHz, 31.3kHz, 37.5kHz, 46.9kHz, 62.5kHz, 93.8kHz, 187.5kHz. The timers and counters are 16-bit, so adjusting the maximum period (from 256) per timer you can achieve better frequency accuracy. (For example, for 25.0kHz, you could just set the dividers to minimum and use period 1920, to get about 10.9 bits of precision for the duty cycle –– the internal clock is 48 MHz, but you could also use a common external clock (or the clock output from one for all others) to get all slaves' frequencies in sync. Obviously, if you don't want to do such calculations, the slave can always scale the duty cycle from any range you decide to standardize on.)I would consider using a set of slaves that you control via I²C or UART (connecting master TX to all slaves' RX). For 35 outputs, using 10 timers over 5 slave CH32V006, you'd need about $1 worth of parts and a simple PCB.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: June 22, 2025, 02:22:54 pm
content: Does it have to be pure PWM?If it's for or LED driving, dithered PWM or binary code modulation are easy ways to do lots of channels on an MCU

author: Nominal Animal
author_rank: Super Contributor
timestamp: June 22, 2025, 05:09:55 pm
content: Quote from: mikeselectricstuff on June 22, 2025, 02:22:54 pm100kHz at 8-bit precision requires "only" a 25.6 MHz clock. If you have a 32-bit MCU that exposes all 32 bits of one GPIO port, and supports DMA at 25.6 MHz to a GPIO port, you'd only need 256×32-bit = 1024 bytes of DMA buffer (cyclic, auto-restarting), to generate arbitrary duty cycle and synch PWM on each of those 32 bits –– in fact, an arbitrary 256-bit sequence on each of the 32 channels.To adjust the PWM frequency between 20kHz and 100kHz, you need to vary the DMA clock between 5 MHz and 26 MHz.Something like a CH32V203 in QFN-48 (CH32V203C8U6) or LQFP-48 (CH32V203C8T6) should be able to do so (or close to), for a total BOM cost of under $1 in singles, since they run at up to 144 MHz. (I believe the available SRAM bandwidth is the bottleneck.)One trick in generating the needed 32×256 bits is to first fill it with zeroes, then set the bits where they change state. Then, a single pass over the entire array, exclusive-ORing the new input with the previous output, generates the bit sequences. Keeping a separate 1k array with only the bits where each channel changes state, and separately the indexes where they are (so they are quickly modified), allows one to regenerate the DMA data quite efficiently.

author: AndyC_772
author_rank: Super Contributor
timestamp: June 22, 2025, 05:40:10 pm
content: This would be a perfect application for a small FPGA. Personally I'd probably use an Efinix Trion T8 or T13, which come in a TQFP (among other packages).

author: LinuxHata
author_rank: Frequent Contributor
timestamp: June 25, 2025, 05:48:36 am
content: All that is great, but all that requires programming/development, while I'm looking for "Ready to buy" solution.

author: tszaboo
author_rank: Super Contributor
timestamp: June 25, 2025, 10:55:18 am
content: Quote from: LinuxHata on June 25, 2025, 05:48:36 amYes and I want a pony.

author: BadeBhaiya
author_rank: Regular Contributor
timestamp: June 25, 2025, 11:13:19 am
content: Okay a stupid ideaYou build 32 different 555 circuits and use two 16x channel SPI/I2C DACs to set their duty cycle

author: AndyC_772
author_rank: Super Contributor
timestamp: June 25, 2025, 11:57:45 am
content: Quote from: LinuxHata on June 25, 2025, 05:48:36 amWe all must learn new skills when the ones we already have no longer allow us to do all the things we need to do.An FPGA is literally a device that can produce whatever signals you want; you just need to program it. It's a good fit for your current need, and the only barrier is the learning curve.I admit, the curve is steep, and yes, learning some VHDL or Verilog, and (muchmore importantly) timing analysis, is necessary.This is OK. I've made a good living by having FPGA design capability within my skill set, and you could too.

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 25, 2025, 06:04:04 pm
content: Closest thing I can find is the PCA9635, but this uses a fixed frequency of 96kHz.Some chips like the PCA9685 support an external clock so you could get exactly the same frequency across multiple chips. But the PCA9685 only supports output frequencies up to 1526. I haven't seen anything that would allow you to synchronize the phase across multiple chips.