VERILOG: Equality test with don't cares - Page 1
Forum section: electronics / general

author: AussieBruce
author_rank: Regular Contributor
timestamp: May 14, 2022, 05:10:11 am
content: Hello, I’m having trouble getting a simple frequency dividing loop to work. Here’s a minimal test fragment, if the comparison wire has any don’t care bits in it the test fails, if I don’t include them it works fine. I’m obviously specifying the don’t cares in the wrong way, can anyone help?In case it matters, IDE is Quartus-II. Thanks in advancereg [24:0] TBdiv;reg LEDreg ;wire Roll = (TBdiv == 25'b1111111111111111111111111) ; // This workswire Roll = (TBdiv == 25'b111111111111111111x111111) ; // This doesn'talways @ (posedge clk)beginif (Roll)beginLEDreg <= ~LEDreg ; // Test LEDTBdiv <= 25'd0 ;endelsebeginTBdiv <= TBdiv + 25'd1 ;endendassign LED = LEDreg ;

author: Foxxz
author_rank: Regular Contributor
timestamp: May 14, 2022, 05:25:00 am
content: What about something like...wire Roll = (TBdiv{24:7} == 18'b111111111111111111) && (TBdiv{5:0} == 6'b111111);This might not be exact I'm a little rusty. But basically cutting out the don't care bit by splitting up the comparisonwire Roll = (TBdiv == 25'b111111111111111111?111111);I think this is also valid

author: BrianHG
author_rank: Super Contributor
timestamp: May 14, 2022, 05:35:55 am
content: Try :wire Roll = (TBdiv == 25'b111111111111111111?111111) ;Please double check in your simulator. I'm a bit rusty in this area.When placing an 'x', this means your source reg needs to be unknown or un-initialized 'x' to return a high value. This does not tend to work in FPGA hardware but only in simulators.

author: AussieBruce
author_rank: Regular Contributor
timestamp: May 14, 2022, 07:36:46 am
content: Thanks for the comments folks. Since then I’ve done some more testing as well as googling, and now realise that I’ve stumbled on a can of worms. All I was trying to do was to reduce the footprint of the wire by anding only the bit positions that indicate that the target has been reached. I would have thought having convenient syntax available for that function would be a nobrainer, whereas in fact it seems that there are issues all over the place with the notion of ‘don’t care’.It’s probably good that all this has come to light, up to now Verilog has looked pretty unbreakable. If I ever come across a ‘what would you like added to Verilog?’ website I’ll add that to it, although I have no doubt that it would have already been suggested. Cheers

author: AndyC_772
author_rank: Super Contributor
timestamp: May 14, 2022, 08:22:54 am
content: I'd implement this with a bit mask, ie.if (value AND mask) = (target AND mask) then <stuff>This doesn't add any extra logic to the final gate list, because if the mask is fixed, the results of the AND operations are known at compile time - either the original bit value or zero, neither of which requires any additional logic to derive.The tests for "does 0 equal 0" can also be omitted and will optimise out, leaving behind just the comparison between the bits you're interested in.

author: Someone
author_rank: Super Contributor
timestamp: May 14, 2022, 11:57:34 am
content: Quote from: AndyC_772 on May 14, 2022, 08:22:54 amVerilog code golf:&((value ~^ target) | ~mask)... and to continue the holy wars, VHDL has a function: std_matchwhich is apparently now also an operator: ?=

author: emece67
author_rank: Frequent Contributor
timestamp: May 14, 2022, 01:04:07 pm
content: .

author: rstofer
author_rank: Super Contributor
timestamp: May 14, 2022, 02:48:34 pm
content: They should add a 'Maybe' operator to go along with these. Perhaps expand the concept to include a 'Once in a while' operator.I'm getting old...

author: BrianHG
author_rank: Super Contributor
timestamp: May 14, 2022, 02:57:28 pm
content: Quote from: rstofer on May 14, 2022, 02:48:34 pmWell, the triple '=', or the === and !== operators exist...

author: josuah
author_rank: Regular Contributor
timestamp: May 18, 2022, 11:58:43 am
content: Would it not work to sliceTBdivto exclude the bit you do not care?Foxxz already proposed:Code:if (TBdiv[24:7] == 18'b111111111111111111 && TBdiv[5:0] == 6'b111111)...This is slightly more compact (but not too much):Code:if ({ TBdiv[24:7], TBdiv[5:0] } == 24'b111111111111111111111111)...This9'b1111?1111syntax is nifty! I did not know about it...From thestandard:Quote

author: free_electron
author_rank: Super Contributor
timestamp: May 18, 2022, 01:27:30 pm
content: logically OR incoming data with a mask. Set bit to 1 if don't care. now you can reduce to bitwise and