Searching a high-side driver ic for a p-channel MOSFET, do you know any? - Page 1
Forum section: electronics / projects

author: Jajaho
author_rank: Contributor
timestamp: August 04, 2019, 03:29:55 pm
content: Hey guys,thank you for tuning in.I'm on a project controlling a valve with a high side switch using PWM.I have these requirements:Supply voltage: 8 - 32VSwitching current: up to 10ASwitching frequency: up to 10kHzI already have a suitable p-channel enhancement MOSFET.What I'm still looking for is a suitable driver for it.There is plenty of ic' for NMOS high side switches, but I can't find any suitable for PMOSFETs.Since I also have to hand solder them so TQFN ones are not an option.I was wondering if you guys have an ic I wasn't able to find.Your help is much appreciated.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 04, 2019, 03:56:12 pm
content: I've used the LTC1693-5 for that, but it's only 13.2V max.As you noticed, there are far fewer options for PMOS gate drivers.What's the PMOS transistor you selected? Could you post the reference so we can suggest solutions? (For instance its max VGS could be a criterion...)

author: Jajaho
author_rank: Contributor
timestamp: August 04, 2019, 04:09:18 pm
content: Hello,I also took a look at that one, but yeah since I'm working with a Vcc of up to 32V it's unfortunately not an option.The MOSFET is an Infineon one with an absolute maximum gate voltage of +/-20V.I don't have the exact name at the moment, but I could post that tomorrow.

author: IconicPCB
author_rank: Super Contributor
timestamp: August 04, 2019, 09:03:11 pm
content: there are high side smart fets which may be suitable in their own right (no need for a separate driver.

author: langwadt
author_rank: Super Contributor
timestamp: August 04, 2019, 09:38:40 pm
content: Quote from: IconicPCB on August 04, 2019, 09:03:11 pmand it'll be protected against most types of faults and abuse

author: darrenb
author_rank: Contributor
timestamp: August 05, 2019, 02:22:38 am
content: As you are getting a driver and there are plenty of options for N channel, would it be better to use an NMOS instead. They generally have better specifications including RdsOn which will result in less heat.

author: sourcecharge
author_rank: Regular Contributor
timestamp: August 05, 2019, 04:35:03 am
content: you could try something like this...(edit optional diode part number changed to 1n4001)

author: planet12
author_rank: Regular Contributor
timestamp: August 05, 2019, 05:00:22 am
content: A high-side PMOS can be controlled relatively easily, as you just need to pull the gate towards ground (with appropriate clamps so as to not exceed maximum Vgs). For fast switching, active switch-off can be done with a BJT, diode and a resistor set up to discharge the gate (searching "MOSFET gate drive circuit" should find plenty of helpful information).I suspect you'll find few IC options for driving a high-side PMOS, as most high-side drivers are designed for using an NMOS at the top (NMOS generally have better specifications overall due the the physics involved), normally by using a bootstrap capacitor (aka flying capacitor) to charge the gate positive with respect to the supply rail. Bootstrap versions have duty cycle limitations too, as you need to be able to regularly recharge the capacitor.

author: Jajaho
author_rank: Contributor
timestamp: August 05, 2019, 08:48:46 am
content: Thank you all very much for taking time out of your day to answer my question.The MOSFET I was planning on using and that I already have on hand is this AUIRF4905 (IRF not Infineon as I preveously stated ofcourse).I also drew up this driver cicuit with a push pull configuration. The Problem with that is my wide range of supply voltages (from 8 - 32V) So when I set the turn on gate voltage to be 1/2 Vcc in order to not damage the gate at a supply voltage of 32V this comes around and bites me in the ass when I only have a Vcc of 8V as it wouldn't turn on the MOSFET all the way. I guess I could use a zener to clamp the gate voltage to the suppply, but I'm not so sure about that.I will now look into smart switches (those are these Infineon thingies, right?) and using a N-channel FET.Again thank you all for your suggestions so far.If you have any other Ideas be sure to let me know.Greetings from Germany

author: Jajaho
author_rank: Contributor
timestamp: August 05, 2019, 11:29:28 am
content: Behold, I found the one to rule them all!I present to you:BTS6163D, Smart high side switch from Infineon!It has all the bells and whistles.Wide operating voltage from 5,5 - 62VInternal current sensing, overtemperature shutdown and so onI think she is the one.What I found interesting however is the way they listed the nominal load current in the datasheet.They have two listings, one according to some automotive ISO norm and a second refering to mounting it on a pcb.

author: Ian.M
author_rank: Super Contributor
timestamp: August 05, 2019, 11:38:15 am
content: Try the attached high side PMOS driver circuit (LTspice sim). It gives fractionally under 7.5V of gate drive at 8V Vcc, rising to 10V at 12V Vcc, and limits the drive to 12V at 36V Vcc. If built with careful attention to layout, decoupling and parasitics, it should be brutally fast. Sub 100ns edges are possible.N.B The input must swing rail-to-rail of your logic supply. If it doesn't go below 0.2V you wont get a fast enough turnoff and any droop in its high level will result in reduced gate drive.

author: Jajaho
author_rank: Contributor
timestamp: August 05, 2019, 11:52:26 am
content: Well you know what they say about celebrating to early...The smart switch I mentioned earlier is terribly slow.Turn on time: typ. 150µs & max. 300µsTurn off time: typ. 200µs & max. 550µsI have to switch it at up to 10kHz...Naive calculation:1 / 850E-6 = 1176Hz, so that won't workIt's back to the drawingboard.I will try your recommendation and simulate the discrete p-channel driver.The AUIRF405 should be fast enough with 99ns rise time and 64ns fall time.But since I'm planning on using a jellybean attiny to controll it all I'm pretty sure it won't do rail to rail.Do you have any suggestions on what to do about that?

author: Jajaho
author_rank: Contributor
timestamp: August 05, 2019, 12:04:35 pm
content: Hello Ian M.,first of all thank you for your answer.But I tried running your attached .asc using LTSpice and got this instead (see attached photos).It can't find the models you used. Are they your custom ones maybe?EDIT: Never mind, the problem was on my side. I reinstalled the thing and now it shut up.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 05, 2019, 12:35:10 pm
content: Can you explain why you're not going for an NMOS transistor instead? As said above, it'll be much easier to find one with better specs than a PMOS and the gate drivers are easy to find.

author: Jajaho
author_rank: Contributor
timestamp: August 05, 2019, 12:53:34 pm
content: Hello Silicon Wizard,the BTS6361D is just that. A n-channel MOSFET with a driving circuit, all in one package (plus some).But since it requires a charge pump to boost the supplied voltage above the operating voltage in order to turn on the MOSFET it is much slower at it compared to a traditional driver.This is a problem since I have to modulate it using PWM up to 10kHz.In addition the AUIRF4905 is a very well performing p-channel MOSFET that can keep up with the N-channel guys.I think you could also use an isolated photo-driver of some sort and if you have a specific recommendation I am more than willing to look into it.I hope I made my reasons clear and that I'm not overlooking something.Thank you very much for your question though and please let me know what you think about it.Greetings from Germany.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 05, 2019, 01:28:38 pm
content: You're mentioning an integrated switch, with of course its own limitations and compromises, but I think it won't be too hard to find a separate gate driver that can handle switching @10kHz.

author: Scrts
author_rank: Frequent Contributor
timestamp: August 05, 2019, 01:36:41 pm
content: Check TI, e.g.:http://www.ti.com/lit/ds/symlink/tps22990.pdfBut in general... switching 10A @ 10kHz is quite a challenge

author: Jajaho
author_rank: Contributor
timestamp: August 05, 2019, 02:21:10 pm
content: Hello guys,in order to shine some light on the task at hand I want to explain what I am actually doing.The pcb I'm designing is for use in a testing/evaluation laboritory.We are testing valves/clutches. In this context they use a technique called "peak and hold" where first you drive the valve at full power (which could be up to 10A) in order to bring it in position. After this first phase the duty cycle is reduced to say 30% -40% in order to hold it in place.Since I do not know exactly what kind of valve will be connected I need to plan for a wide range of supply voltages (8 - 32V), pwm-frequencies (0 - 10kHz), duty cycles (0 - 100%).The testbox Im building will take to analog voltages from 0 - 10V in order to set the frequency as well as the duty cycle. Im planning to use some avr mcu like the attiny for this task.Answer to Scrts: Unfortunately the operating voltage range is only up to 6V. But thank you very much for bringing it to my attention anyway.Cudos to Ian M.I took a look at your suggested driver circuit and was blown away.Clearly you are a very experienced analog engineer. The suggested circuit far exceeds my limited knowlege.It features extremly fast switching times which I think are in this case to fast. I'm worried about EMV and since I only need to switch at 10kHz maybe 100kHz this circuit seems to be a bit overkill.On the other hand I would be very interested in how the circuit works.If you could ever so kindly find the time to explain to me the reason for implementing the matched pair, the two schottky diodes aswell as the general idea, I would be very thankfull.Thank you all for your time and have a good day.Greetings from Germany

author: Scrts
author_rank: Frequent Contributor
timestamp: August 05, 2019, 02:50:37 pm
content: The question is: if you are doing a tester for a device, then what chip drives that device in the real application? Reusing the same circuitry would make your tester even better.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 05, 2019, 02:59:01 pm
content: Another tip for an integrated gate driver is to look for half-bridge drivers instead (and obviously just use the upper driver and a NMOS transistor, although you may find some use for the lower switch as well). I think you'll have more options for fast switching (which means higher peak output current) than with single gate drivers, as half-bridge drivers are specifically targeted at PWM applications such as motor driving, so fast switching.

author: Ian.M
author_rank: Super Contributor
timestamp: August 05, 2019, 03:43:33 pm
content: I assume one terminal of the valve or clutch coil is commonly grounded to their bodies so you cant simply use low-side switching using a N-MOSFET.The Q1,Q2 matched pair forms a basic current mirror, applying a current set by R1 and the input logic level to the driver stage pullup resistor R2. The ratio of R1:R2 therefore sets the max gate drive voltage swing. It needs to be a current mirror with a low voltage drop to get as close as possible to rail to rail gate drive so one cant use the more accurate Wilson current mirror there without compromising gate drive at low supply voltages.D2 speeds up discharging the junction capacitances in the current mirror at the end of the pulse to get a crisper turnoff. However that means that the total of its Vf drop and the logic output '0' voltage must be less than Q1, Q2 Vbe. If not it wont do any good. This shouldn't be a problem for any SSI or MSI CMOS logic or MCU with reasonably robust pin drivers.Schottky diodes are use for speed, and also in the case of D1, for low Vf drop as it + the Vbe drop of Q3 determine how close the output can get to the supply rail.The driver stage Q3,Q4 buffers the resulting waveform, with bootstrapping to the top end of R2 (via R3,C1, with D1 letting it momentarily swing above the supply rail) to get a reasonably square rising edge rather than the slowish exponential that a plain resistive pullup would give. R5 helps isolate the driver from the MOSFET gate capacitance to allow the bootstrapping to be more effective. Q5 or Q6 turn on if there's more than about 0.6V across their base pullup/pulldown resistors which only happens if Q3 or Q4 are passing more than 6mA collector current. As the load is capacitive, with negligible DC current, this can only happen during edge transitions, and they act to dump a lot of current into the gate capacitance during each transition to speed it up.If you want less brutally fast gate drive, simply delete D2, Q5 and Q6 and replace R4 and R6 with short circuits. You can then also increase R5 if you need to 'slug' it even further.A completely different 'Electronic LEGO' style option that would be viable for a one-off would be an isolated 1W DC-DC converter to get a floating 12V supply from your 5V logic supply, an ordinary NMOS low side gate driver IC running from the floating 12V supply (with *LOTS* of decoupling) and a fast optocoupler to get the pulse signal up to the gate driver input. Tie the positive side of the DC-DC converter output to the main supply if driving a P-MOSFET, or the negative side to the MOSFET Source if driving a N-MOSFET as a high side switch.In all cases, if you want it to be robust, and you aren't using a 'smart' high side switch with built-in protection, you'll need a fast current sensor on the supply to the MOSFET, and logic to prematurely terminate the drive pulse if the current exceeds a threshold determined from the MOSFET's SOA graph, with a largish safety margin. It should also light an over-current indicator light. You may need to add an air-core inductor in series with the output to slow down the current rise time if its operating into a dead short, just enough for the over-current protection circuit to operate before the MOSFET is at risk. Reset the over-current trip circuit either manually or automatically between pulses.

author: langwadt
author_rank: Super Contributor
timestamp: August 05, 2019, 04:36:52 pm
content: Quote from: Jajaho on August 05, 2019, 02:21:10 pmwith PWM and those current you'll need a beefy flyback diode, I'd consider a halfbridge instead

author: sourcecharge
author_rank: Regular Contributor
timestamp: August 05, 2019, 10:23:52 pm
content: Quote from: Jajaho on August 05, 2019, 08:48:46 amThe only thing you have to worry about is the current through the zener. The above schematic works fine up to about 50khz. The design has only the limitations of the components. You don't have to use the irf9530 pch mosfet or the 2n7000 nch mosfets..any mosfets will work, but their limits determine the limit of your voltage output. The two resistors can be decreased to speed up the signal to about 10 Mhz, if your mosfets can go that high. The only thing is that the current through the resistors and the zener is increased, so approprate wattage resistance above the nch mosfet is required. Lastly, zeners can be paralleled to increase their overall current capacity.There is nothing as simple and as variable as this design, good luck though, and I hope you find what you are looking for, but I'm not sure why everyone has such a hesitation with using zeners.

author: AndersJ
author_rank: Frequent Contributor
timestamp: August 05, 2019, 11:35:15 pm
content: I’m on a iPad, no LTspice in sight.Can someone attach a picture of Ians circuit?

author: Mechatrommer
author_rank: Super Contributor
timestamp: August 06, 2019, 01:44:05 am
content: while Ian.M circuit is more featurefull, attached can be a simpler bjt push pull driver that can maintain -5V Vgs down to 6Vs using 15V zener clamp (shown Vgs dark red traces for Vs 6V and 50V). suggestion welcomed i may have missed something, its a 10 minutes sketch, zener current @ 50Vs should be around 50mA. ymmv.Quote from: AndersJ on August 05, 2019, 11:35:15 pmsee last attachment.

author: Ian.M
author_rank: Super Contributor
timestamp: August 06, 2019, 02:02:31 am
content: @Sourcecharge,The problem with Zener clamping is excessive junction capacitance. Its not a major problem if you are directly clamping the MOSFET gate as its almost invariably swamped by the gate capacitance, and its effect is limited by the highish drive currents required to charge/dicharge the gate, but if you need to clamp a higher impedance node earlier in the driver circuit to limit the gate voltage without excessive dissipation in the driver circuit, having what approximately looks like 75pF in parallel when you add a small 12V Zener like the BZX84C12L is *really* not helpful if you want reasonably fast transitions.See attached LTspice sim of Zener clamping and of simple limiting by pulse current control through a known resisto, which also has (near) ideal clamping and the same with 75pF in parallel for comparison. It also shows the vital importance of having a low enough resistor in parallel with Zener to discharge it if the drive is unidirectional.There are workarounds e.g keep the Zener continuously biassed to provide a clamping rail then use a fast low capacitance diode to clamp to it, but they all add significant complexity.

author: Jajaho
author_rank: Contributor
timestamp: August 06, 2019, 05:27:04 am
content: For me here in Germany a new day of work has started and I'm just blown away by your dedication to this issue, thank you all very much.Spezial thanks to Ian for taking the time to explain his cicuit.The capacitance of the zener is also a thing to keep in mind.I will take every post here into consideration and once my circuit is done I will upload it here.Best regards.

author: Jajaho
author_rank: Contributor
timestamp: August 14, 2019, 06:52:23 am
content: Hello everybody it's me again, reviving this thread.I have finfished my schematic aswell as the layout (except for some minor things ofc.)I would really appreciate it if some of you guys could review it and give me your two Cents about it.Thank you all in advance.Greetings from GermanyPS: As I mentioned earlier in this thread this sucker has to switch a maximum of 10A at a maximum PWM frequency of 10kHz. Altough be it for a short duration (say maybe 1 sec), I undoubtably will need some beefy caps to support this switching action. I'm asking if anybody has any experience values he/she can recommend or alternatively an actaul way of determining the required capacitance.Thank you very much.

author: Jajaho
author_rank: Contributor
timestamp: August 22, 2019, 08:33:30 am
content: Hello to anybody who still gives a,I have now ordered the pcb's posted above and I am expecting them to arrive in 2-4 days.On the other hand I am still intriged by Ian's circuit posted earlier and so I'm giving that one a shot too.Due to a limited choice in distibuters I am forced to swap the matched 2N3904 pair for something else.The choice I'm currently planning on going with is the BCM847BS.I looked through the datasheet and found it to be a fitting replacement.I wouldn'T mind if anyone could double check that however.I'll be shure to post my post my results here.Greetings from Germany.

author: Ian.M
author_rank: Super Contributor
timestamp: August 22, 2019, 09:35:59 am
content: Matching is fairly non-critical, so you don't need a precision matched pair. All parts in my design were fairly generic so there shouldn't be any problems with substituting broadly similar transistors. The BCM847BS Vceo and Ic ratings look suitable. At 32V, in my circuit, it will dissipate 100mW during the PWM on time, which is well within its ratings. and its certainly preferable to hand selecting individual 2N3904 or similar to match them then having to improvise some sort of thermal coupling for the pair.N.B. it absolutely needs *GOOD* decoupling, as close as possible to the complimentarydriver stage collectors and theoutput stage emitters. Remember, its trying to throw sub 1us 800mA current pulses around (if you don't tame it by deleting the output stage).Edit: *DON'T* attempt to decouple the driver collectors as that would FUBAR the output stage base drive!

author: Dubbie
author_rank: Unknown
timestamp: August 22, 2019, 10:05:03 am
content: I always thoroughly enjoy reading Ian.M’s posts. You can always bet on a clever and well thought through solution to the problem as presented. I have been fortunate enough to have benefited from his patient assistance on more than one occasion. One of this forums hidden treasures. Thanks Ian!

author: Jajaho
author_rank: Contributor
timestamp: August 22, 2019, 11:36:18 am
content: I can absolutely agree with that.Thank you very much for your time and effort.I am currently working on a layout for Ian's proposed design using Pulsonix.But I'm wondering how good decoupling would look like in this case.Do I just lay down a couple of 100n's from V+ to GND next to the transistors?Do I need any bigger caps when powering the circuit from a good laboratory power supply?Do you, in general, have any kind of application notes regarding this topic I could read through?Much appreciated.

author: Jajaho
author_rank: Contributor
timestamp: August 23, 2019, 06:36:56 am
content: Hello,here is my current layout for Ian's proposed driver design.I would really appreciate it if you guys could take a look at it.Thank you very much.PS: C4 is supposed to be 100uF

author: IconicPCB
author_rank: Super Contributor
timestamp: August 23, 2019, 06:49:44 am
content: Would someone care to walk me through the schematic (as shown in the PDF file above)?

author: Jajaho
author_rank: Contributor
timestamp: August 23, 2019, 06:57:40 am
content: Of course but I am not the one who came up with it so you will find that Ian M. can and has done a much better job at doing so earlier in this thread.Quote from: Ian.M on August 05, 2019, 03:43:33 pm

author: Ian.M
author_rank: Super Contributor
timestamp: August 24, 2019, 07:15:31 am
content: Please note edit to reply #29All component references in this post refer to the schematic from reply #32, not those from my sim.It looks basically sane, but I'd tighten up the layout as much as possible to reduce trace lengths and thus stray capacitance and loop area. I'd also beef up the collector and emitter traces to Q3,Q4 (and out to the gate) even to the point of having to neck them down to transition to the pad. It would also be beneficial to reduce the length of the gate trace to the MOSFET. I'd also put a footprint for an optional series gate resistor or ferrite bead in case the MOSFET breaks into HF oscillation while sweeping through its linear region on each transition. Bridge it with a trace you can cut, or populate with a zero ohm jumper.Also the large hole in the ground plane is problematic, and likely to seriously increase its radiated emissions. Maybe re-do with most of the MOSFET driver circuit traces on the other side, but be careful to avoid long slots in the ground plane. More vias are definitely preferable to long slots. The only place you may *WANT* a hole in the ground plane is under the node driving the bases of Q1,Q2, where stray capacitance is very detrimental to the rise and fall time.On the subject of decoupling. Its somewhat of a black art*unless you can consider the effects of all the parasitics involved (both internal to the caps and trace inductance and resistance) in detail. Unfortunately I don't have a good reference for a tutorial that will get you up to speed with high current HF and pulse circuit decoupling as I learnt what little I know of the art#well before internet tutorials. Minimising loop area is key to keeping trace inductance under control.Its desirable for all the gate charge required to switch the MOSFET to come from the nearest decoupling capacitors to the emitter of Q4 without significant voltage shift at the emitter. If the capacitance was numerically equal to the total gate charge, with no other decoupling, you'd get a 1V + I*ESR voltage shift at the emitter. You probably want far less than that, so try an order of magnitude more capacitance. You may have to split it into multiple capacitors to reduce ESL. Minimise track length to the decoupling and if on the opposite side to the ground plane, use two vias for each decoupling cap ground pad to reduce the effect of the via inductance.* far less so nowadays, as simming the parasitics involved can be done in a few minutes in a SPICE program on your desktop without deep knowledge of mathematical programming rather than having to write a Fortran program to model the network and submit it as a batch job to a mainframe.# Others here are far better equipped to advise on it, as I don't have the benefit of recent hands-on experience in a well equipped lab with a VNA and fast enough DSO to make quantitative measurements of the effects of apparently minor chances to decoupling layout and component choice. The principles are the same, but I haven't kept up with the effects of ever-shrinking SMD construction on its practical implementation.

author: Jajaho
author_rank: Contributor
timestamp: August 25, 2019, 07:47:56 am
content: Thank you very much, Ian. I'll be sure to check it out as soon as I'm back in the lab.