I2S to EIAJ glue-logic digital-audio converter -- help needed! - Page 1
Forum section: electronics / projects

author: 13hm13
author_rank: Frequent Contributor
timestamp: January 06, 2014, 12:58:52 am
content: I2S is a digital-audio transmission format mostly supported by Philips. You can read about it on Wikipedia, Philips' own White Paper, and other resources:http://en.wikipedia.org/wiki/I%C2%B2Shttps://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdfhttp://www.eng.auburn.edu/~nelson/courses/elec5260_6260/Inter-IC%20Sound%20(I2S)%20Bus2.pdfVery similar to I2S is EIAJ ( a Japanese audio transmission format). here is the basic diff. between the two:I'm trying to create thesimplest(fewest parts count) ckt for I2S to EIAJ conversion.To convert between two formats involves some glue-logic manipulation. But this can get a bit messy.I know that the following ckt works as I have built/tested it:The following "simple" I2S to EIAJ converter supposedly also works but I can't seem to do so (It may be flawed as the designer never tested it):And finally, the following I2S to EIAJ, using 3x74HC174flip-flops and a single 74HC125 buffer (optional), is supposed to work, but I can't seem to do get it to do so ...For the ckt above (and neglecting the optional 74HC125 buffer chip on the far right), all that is supposedly needed are those three74HC174F-Fs.As far as I can tell... DATA enters the first chip (pin 3) and then is daisy-chained to add delay:Starting at the 1st 74HC174 (far left):DATA (IN) --> 3 (D)2(Q) --> 4(D)5(Q) --> 6(D)7(Q) --> 11(D)10(Q) --> 13(D)15(Q) --> 2nd 74HC174 3(D)2(Q) --> 4(D)5(Q) --> 6(D)7(Q) --> 11(D)10(Q) --> 13(D)15(Q) --> 3rd 74HC174 3(D)2(Q) --> 4(D)5(Q) --> 6(D)7(Q) --> 11(D)10(Q) --> 13(D)15(Q) -->OUTCLK (9) is common to all three 74HC174sVcc (pin 16, +5VDC)CLR (pin 1, "HIGH", on all three, tied to Vcc)I'm using TI's SN74HC174 (DIP size, not SOIC like in photo above)PROBLEM:On the 'scope, I'm seeing the DATA (signal) reduce in amplitude by about 1/2 as it goes from Q to D (from one logic sectionwithinthe chip to the next). Not sure why this is happening. By the time the signal makes its out of the FIRST chip, it's almost dead.I must be doing something wrong because this ckt is supposed to work -- it is sold as a kit PCB (shown). Unfortunately, a schematic is not avail.

author: 13hm13
author_rank: Frequent Contributor
timestamp: January 06, 2014, 06:07:23 am
content: Perhaps the orig. post was a bit too much all at onceSo, let me make things a bit simpler...Just take ONE 74hc174 flip-flop (FF) device....Feed it a square-wave input (D) ... and osc. pulse (CLK) ... and tie its (CLR) pin to Vcc (+5v).Why does FF's channel output (Q) degrade?(Note that there are four channels for each 74hc174 chip)Thx!

author: Rerouter
author_rank: Super Contributor
timestamp: January 06, 2014, 07:26:56 am
content: I greatly have to wonder why you are doing this with 3 D flipflop chips as opposed to 2x 8 bit shift registers, or 1 16 bit SIPO shift register?as for the problem i would greatly check your supply voltages, as being a cmos type you should not be loading the outputs past there limits,equally on your final stages or where the signal drops to noting, confirm no shorts to ground.

author: jeremy
author_rank: Super Contributor
timestamp: January 06, 2014, 07:41:10 am
content: Is anything hot? Have you checked the rails (directly on the pins of the chip) ? Seeing a 74 series chip outputting at half screams power problems to me

author: 13hm13
author_rank: Frequent Contributor
timestamp: January 06, 2014, 11:44:06 am
content: Thx for all your feedback thus far.No (and I should've noted earlier)... nothing running hot (first thing I checked).In fact, I made several continuity checks -- GND, Vcc, CLK, etc.-- BEFOREin stutesting, for risk mitigation AND to increase confidence of a successful build. That does not mean there are no problems (obviously); rather less chance of smoke!Rerouter: I've tried the single shift-register approach (see the second ckt in OP); asInoted, I could not get it to work. That does not mean it cannot work.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 06, 2014, 11:46:29 am
content: If you want fewest parts then a CPLD or FPGA would be the way to go, probably the latter looking at how many registers you have. The smallest Lattice XO2 in a 32QFN may be a good fit, as it has onboard config memory and core voltage regulatorYou might also be able to do it with an MCU that has I2C support (e.g. PIC32MX)

author: jeremy
author_rank: Super Contributor
timestamp: January 06, 2014, 12:08:40 pm
content: Ok, just gotta mention the easy stuff first sorryThe FFs should be buffered on both Q and D so I can't see why this isn't either a> dead chips or b> incorrect biasing in the IC (aka supply problems)How about some of these strategies (in order of drastic-ness):-> Look at the power rails with the scope. Anything weird?-> Feed in all ones to the flip flops and see if you can discern a pattern using both a multimeter and oscilloscope. I sometimes make silly mistakes with the scope that can mess with readings, so that's what I would check first.-> Remove the regulator and send in your own power at the correct voltage from a lab supply-> Remove an FF, wire it up somewhere else and check if it worksbest of luck

author: Andy Watson
author_rank: Super Contributor
timestamp: January 06, 2014, 12:11:30 pm
content: Quote from: Rerouter on January 06, 2014, 07:26:56 amDitto, I would check the power supply voltages, both Vcc and GndOn the pins of each IC.

author: 13hm13
author_rank: Frequent Contributor
timestamp: January 07, 2014, 11:41:00 am
content: Solved the main problem: bloody solder bridge (connecting pins 11 + 12). That's what one gets for using cheap Veroboard!I've got signal (i.e., music, audio, whatever) -- on the L/R OUT of the DAC chip -- but very distorted (sounds like pink noise. I've seen (heard) this before, and it was due to poor ground. But ground is fine and the signal looks clean on the scope. Wonder if it's a sync issue. That is, three things have to "mesh", based on the EIAJ spec, for the DAC to work:DATA (both L and R channels, in two's compliment. Some older formats use two separate DATA lines: L and R)WS (aka LRCLK. This switches the DAC from reading L to R and R to L. Inverting WS is like reversing stereo channels)BCK (osc. clock)

author: PA0PBZ
author_rank: Super Contributor
timestamp: January 07, 2014, 12:28:45 pm
content: Your diyaudio pictures are not visible for people not registered there.

author: 13hm13
author_rank: Frequent Contributor
timestamp: January 09, 2014, 12:02:11 pm
content: If you look at the Universal Shifter (shown in OP)...... you'll may note that two of the three lines that go to the D/A (aka DAC)don't go thu the shifter at all(i.e, BCK and WS); so, only DATA is "shifted". This shifter is based on six 74HC164 shift-register ICs, and two more 74-series logic chips. I'm not sure why there are so many needed, but (as noted in OP) this whole messy topology work!The Black Crow (also shown in OP) is claimed to work for same shift application, but somehow usingonlythree 74HC174 F-F's (the incorporated 74HC125, on far right-hand side, is only a buffer, and not really needed).Black Crow shown here again:This works but with very distorted audio ... and I can't quite figure out why.Aargg!!!Again, BCK and WS are not shifted ... only DATA line goes thru converter.BASIC QUESTION:Why use a Shift Register (74HC164) instead of F-F (74HC175)?