Copper pour clearances for 30 and 60V? How tight do you dare to go? - Page 1
Forum section: electronics / beginners

author: incf
author_rank: Frequent Contributor
timestamp: March 31, 2025, 01:14:40 pm
content: I've got a design with 30 and 60V rails. (DC, fuse protected) It's a standard 4 layer PCB. No conformal coating or anything.For thermal reasons there are large 30V and 60V copper pours that surround 3.3V and 5V logic signals.How tight would you dare to make the copper pour clearances for 30V and for 60V?I've seen tables online from various standards  and it varies a whole lot. Is there any objective way to know what is "too tight" and what is "too loose" ?In my case I've got some SMT components that connect to the rails that are so tiny that they can't respect any given net-to-net clearance (but they go into high impedance nets so it's fine).edit: I suppose clearance zones for pad (not covered by solder mask) might vary from traces and vias (covered by solder mask). And maybe may depend on how clean the board is. What type of solder/flux is used. etc.edit: https://www.protoexpress.com/blog/importance-pcb-line-spacing-creepage-clearance/

author: tszaboo
author_rank: Super Contributor
timestamp: March 31, 2025, 02:04:39 pm
content: The standards I have to use would call for 3mm separation, clearance and creepage for open air.So I'm guessing that much.

author: incf
author_rank: Frequent Contributor
timestamp: March 31, 2025, 04:07:37 pm
content: If I understand IPC-2221 correctly it suggests something like:A tented GND via inside of a 60V copper pour requires a clearance of 0.13mm (doesn't that seem really small?) Am uncoated SMT pad at ground inside of 60V copper pour requires a clearance of 0.5mm  Column B4 - polymer coated external conductors, 51-100V peak Column A6 - uncoated component terminations, 51-100V peakBut it seems other common standards specify larger clearances

author: TimNJ
author_rank: Super Contributor
timestamp: March 31, 2025, 04:44:01 pm
content: Between two exposed copper points on FR-4 with solder mask between them, I've typically measured about 1KVdc/mm at normal atmospheric conditions, and no surface contamination. The theoretical distance required is very small, <0.1mm. In reality, when the distance between traces is very small, you may need to consider what happens if contaminants of roughly the same size bridge the gap.I would not flinch at using 10mil spacing for 60V. Depends on where it will be used, and what reliability you are expecting, though.

author: mtwieg
author_rank: Frequent Contributor
timestamp: April 02, 2025, 11:32:46 am
content: Quote from: tszaboo on March 31, 2025, 02:04:39 pmI'm assuming the OP is asking about functional isolation, not protective isolation. So standards like IPC-2221 apply, not safety standards.Anecdotally, I do a lot of work with 48V bus power, and often have clearance of ~9mil, mainly due to footprints of ICs. Pollution degree 2 IIRC, no conformal coating.

author: tszaboo
author_rank: Super Contributor
timestamp: April 02, 2025, 11:51:15 am
content: Quote from: mtwieg on April 02, 2025, 11:32:46 amWell sure. But the point is that if you have to sell your product, then some standards will apply to it, that can be higher or lower isolation distance. And engineers often don't have a decision on this.

author: Solder_Junkie
author_rank: Frequent Contributor
timestamp: April 03, 2025, 06:30:53 am
content: Conformal coating, even if just the low cost poly varnish type, is something I use on all my print boards that have SMD parts or narrow gaps. While not common, it only takes a tiny sliver of metal or similar, to cause a problem.SJ