Implementation of toggle flip-flop - Page 1
Forum section: electronics / projects

author: pmbrunelle
author_rank: Regular Contributor
timestamp: November 14, 2017, 04:56:46 pm
content: Presently, I have a 1 MHz 5V CMOS oscillator (Maxim MAX7375), but its duty cycle can vary a lot (45% to 57%). I am looking for a precise 50% duty cycle, so I figured that I could get the 4 MHz version (2 MHz not available), divide the frequency by 22, and get my precise 50% duty cycle.I am looking for a "small" PCB footprint, so I found this dual D-type flip-flop:http://www.ti.com/lit/ds/symlink/sn74lvc2g80.pdfSo while I have seen (on the Internet) T-type flip-flops constructed from routing the not-Q output to the input of a D-type flip-flop, is this a good practice?thHold time, data after CLK?MIN 0.6 nstpdFROM CLK to OUTPUT not-QMIN 0.9 nsMy concern is that when the output changes, it happens so fast that it may come close to violating the hold time requirement.On the other hand, if the output changes to the correct value, then the level at the Data pin is not longer relevant...Also, the output will have a capacitive load, so I'm not sure what that's going to do.I could also get JK flip-flops that are designed to toggle, but that would imply many more pins (and thus more PCB real-estate)...

author: Benta
author_rank: Super Contributor
timestamp: November 14, 2017, 05:07:58 pm
content: All the D-FFs I've seen have timing (setup/hold vs clock-output delay) that allow you to use them as dividers as you plan to do.

author: David Hess
author_rank: Super Contributor
timestamp: November 14, 2017, 05:42:11 pm
content: The propagation delay is always greater than the hold time so wiring the -Q output to the D input is not a problem under any circumstances.

author: duak
author_rank: Super Contributor
timestamp: November 14, 2017, 06:50:11 pm
content: I recall encountering this on some other D-FF many years ago. It was explained away by reasoning that prop delays within one part tend to track - if the part was faster than typical then it would have a shorter input hold time requirement and thus compensate in this application. It could be a problem if the output was used by another part that used the same clock, especially if the receiving part was much slower. The output itself is fine, it's just that it may not meet the hold time requirements of the receiving part.I would think that any extra loading of the output will tend to slow it down and buy a bit of margin.Cheers,

author: pmbrunelle
author_rank: Regular Contributor
timestamp: November 14, 2017, 10:20:04 pm
content: Quote from: David Hess on November 14, 2017, 05:42:11 pmFundamentally, this seems to make sense.Quote from: duak on November 14, 2017, 06:50:11 pmThat's true about the margin, it will add a delay. On the other hand, the slowly-changing voltage will remain within the Data pin's VIL-VIHno-man's land for longer, but it may not matter by then, as the hold time will have long expired.But I think I might find a flip-flop with complementary outputs, and use the Q output to drive my capacitive load... to avoid messing with the feedback signal.

author: Benta
author_rank: Super Contributor
timestamp: November 14, 2017, 11:22:44 pm
content: You're overthinking this. It's just a couple of MHz. With GHz, the discussion might be relevant.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 15, 2017, 11:45:54 am
content: A 74HC74 or even CD4013 will do just fine here, or the 74LVC part if you want the fastest fuckin' edges possible at 5V.On that note, I'm rather surprised a dual inverting D-f/f exists, good to know.There are a couple of things that are only available in 74LVCnG (n = 1..3) and not HC versions or such, which is great because LVC is super fast -- when you need it -- and still capable of running at 5V. But it's also bothersome to havethat much speedwhen you don't need it. It's a huge potential RFI burden.On the off chance you'd like a discrete solution, it can be done with just a pair of transistors, actually. You make the usual bistable flip-flop (two NPNs, say), but cap-couple CLK into both bases (such that R(base pull-up) * C(couple) is more than the switching time, and less than the CLK pulse length). It's still not going to beat a logic solution in terms of size, pin count or final cost.Speaking of logic, CD4047 might be another to look at.Tim

author: pmbrunelle
author_rank: Regular Contributor
timestamp: November 15, 2017, 03:49:02 pm
content: Quote from: Benta on November 14, 2017, 11:22:44 pmIt's the delays between the edges that matter, not the clock rate, right?Quote from: T3sl4co1l on November 15, 2017, 11:45:54 amHere is what the overall system looks like:Oscillator -> Flip-Flop -> Small MOSFET inverter (having a total 1 nF gate capacitance) -> Big MOSFET inverter -> 1.6 VA series RLC load (878 kHz resonant frequency, want MOSFETs to see an inductive load)MOSFET inverter architecture:https://courseware.ee.calpoly.edu/~dbraun/courses/ee307/F02/02_Sales/Image1.gifSo the reason I am inclined towards the LVC family rather than HC (or discrete with pull-ups) is that the outputs seem to have a lower RDS(ON), from what I can infer based on the VOH/IOHand VOL/IOLspecifications. IthinkI need this to drive the capacitive load, a.k.a. the following inverter stage.But from the potential pitfalls of LVC, I may also try an HC part (a pin-compatible substitute), and using an oscilloscope, observe the rise/fall time of the next stage's gate voltages.I didn't know about the CD4047; it seems to combine the oscillator and flip-flop. Interesting. It appears to have a pronounced, but somewhat well defined temperature drift (automotive temperature excursions) in the 1 MHz range, so I might be able to compensate the drift with some thermistor nonsense, but that's a can of worms.I am also considering a CMOS 555 timer, however, the 2 MHz frequency range seems to be near the maximum feasible frequency for RC charging/discharging type oscillators.Yet, this frequency range is below the frequencies of oscillators intended for microcontroller clocks. I'm also trying to avoid something programmable due to the administrative burden that is placed on the assembly process.

author: Benta
author_rank: Super Contributor
timestamp: November 15, 2017, 05:07:00 pm
content: QuoteRight. What I was pointing to was, that at GHz speeds your PCB routing and other factors would influence the analysis. That's not the case here.Be assured that your D-FF will do the job.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 16, 2017, 09:29:38 am
content: Quote from: pmbrunelle on November 15, 2017, 03:49:02 pm1.6 VA isn't very much, or did you mean kVA?It can be better to use a fairly modest CMOS gate, followed by a BJT complementary emitter follower, then the bigger transistors. Saves shoot-through current.Note that, when the gate voltage is greater than NMOS Vgs(th) and less than PMOS Vgs(th), both transistors are on. This is dangerous for transistors less than a few ohms (i.e., it's not very practical with anything bigger than say 2N7002/BSS84), for which it's better to use separate gate drives (with deadtime). And if you're going to do that, you might as well make one a bootstrap type driver, and use a pair of NMOS for the main switch -- better performance than PMOS.QuoteWell, if you're doing a resonant circuit anyway, a fixed oscillator is the last thing you can use. A CD4046 (or 74HC4046) PLL will be very helpful indeed!Tim

author: pmbrunelle
author_rank: Regular Contributor
timestamp: November 16, 2017, 03:49:54 pm
content: 1.6 volt*amps. A small product, shooting for less than $3 (less is better) of oscillator/driver/coil parts on 1 sq. in. of PCB, so I don't want to go all out with a high-side NMOS and making things complex.Actually, my first version of this circuit used a resonant Royer architecture, but then the frequency could drift with my poorly understood "L". This coil will be used as the excitation for a sensor, so if the frequency can shift at the mercy of my mystery "L", it just transfers a bunch of headaches over to the demodulation side (which I don't want).Therefore, I decided to use a fixed oscillator, drop the Q of the RLC down to ~2.5, and then with a good quality C0G series capacitor, I think I can have a reasonably flat (enough) amplitude.I think I'm going to use the 4 MHz Maxim silicon oscillator, divide by 4 using two cascaded D flip-flops, then the complementary emitter follower, then the MOSFET pair, followed by the RLC.Fundamentally, I'm also wondering how bad it is to drive an RLC with a non 50% duty cycle. But now I am in the early development phase, so I'm trying to remove variables that may confuse/distract me from debugging the core product, such as a possible 57% duty cycle.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 16, 2017, 07:05:40 pm
content: Different duty cycle just introduces even harmonics and a DC offset. The DC offset only matters to startup transients. Which is a good reason to split the capacitor, as a capacitor divider from +V to (inductor common) to GND.1.6 VA is small enough you only need one stage (logic output --> N+PMOS, 2N7002/BSS84 would be enough). Or if that's reactive power, not necessarily real power, heck, it might even be enough to drive it straight from the logic pin...What's wrong with detection -- is it not on the same board? Synchronous detection would seem very easy if so, and still not that hard otherwise, unless there's more to the problem.Tim

author: pmbrunelle
author_rank: Regular Contributor
timestamp: November 16, 2017, 10:56:51 pm
content: It's about 1 W of real power; the series 2512 resistor I added to drop down the Q is quite toasty! I figured that for the next version, I should use two resistors to spread the heat more.My sensed values (which are modulated by physical phenomena) are low-pass filtered, and the filter has a phase which changes with frequency. The "physical phenomena" itself applies a phase shift, which I have not yet studied.I measure the current in the exciter coil, low pass it (phase shift), send it to a comparator (propagation delay), and use this digital signal for demodulation with analog switches.Essentially, I have two signal chains, and each one has to have a similar amount of phase shift so that my sensed values are in-phase with the comparator's output.So I feel that with a variable frequency, I'll have more trouble getting the phase shifts of both chains to track each other.Of course the detection may seem very easy to you, but you are rather experienced, while I am a grasshopper 3 years out of school (and I didn't study EE)!It would be fun to talk more about the application, but my employer and customer would not agree!