OPA2388: peak-hold detector circuit affected by opamp input leakage current - Page 1
Forum section: electronics / projects

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 03, 2020, 03:40:40 pm
content: Hello,I am struggling with a peak detector circuit based on the OPA2388, and it just does not want to work!I have eventually reduced it to the schematic in the first attachment. The second attachment indicates what I get from it, when appropriately stimulated with a repeatable input signal.I do not understand why the C331 capacitor is not holding the charge, and the only thing I can blame it on is on the input leakage current of the opamp input. The datasheet indicates am input bias current of less than 1nA, but it indicates this is with an Ri=100kOhm. I am not sure what this Ri is referring to, is it an additional series resistance that needs to be added to the input of the opapm? If I consider the leakage of both opamp inputs connected to the C331 (about 1nA each) and the maximum reverse current of the diode (30nA) I estimate the decay on the capacitor must not be greater than 35mV during the 1ms period (which is the repetition rate of the input signal).I must mention that I am explicitly not probing the capacitor voltage directly with the oscilloscope, to prevent the probe impedance from discharging the cap. I am only able to look at the output of the second opamp (which is in buffer configuration.So any ideas? Is it not the OPA2388 the right one for the job? I have replaced both the opamp IC and the diode, just in case I was dealing with a faulty one, but that was not it.Best regads,Cristian

author: Kleinstein
author_rank: Super Contributor
timestamp: March 03, 2020, 04:35:25 pm
content: The diode may not be the very best choice. Like other very fast diodes it has a significant leakage current. However the choice is not that easy. Low leakage diodes tend to be slow and fast diodes have quite some leakage. So its about finding a good compromise. The choice depends on the application / speed and hold time needed. For the relatively fast cycle like show the diode may be OK.The input bias current for the OPs is valid with the OP in linear mode - in this case the first OP would no longer be in linear operation and can have a much higher input current. The OPA388 does not look like it has the common protection diodes, but there can still be additional current.The usual way would be to have the feedback for the 1 st OP from the output of the first OP. To make this work, one may have to use 2 different OPs, with the 2nd OP considerably faster than the 1st. For the 1 st OP one may have to look for good capacitive drive capability.To speed up the reaction one may have to add an alternative feedback parth with a diode and resistor, so that the OP does not start from saturation, but something like 1 V below the peak.It usually also needs some kind of reset circuit, if there is not that much drift downwards.

author: awallin
author_rank: Frequent Contributor
timestamp: March 03, 2020, 04:37:46 pm
content: what capacitor are you using? Try a 'plastic' PP or PTFE low leakage capacitor?electrometer op-amps have maybe 10s of fA input bias currents..electrometer datasheet or app-notes probably have guard-ring ideas explained, to minimize leakage of the charge through the PCB material.

author: Kleinstein
author_rank: Super Contributor
timestamp: March 03, 2020, 04:55:09 pm
content: For the capacitor 1 nF is already quite large for a fast peak detector, but it can be Ok. Anyway this effects the response to short pulses and not the hold time. On the scope pictures the rise looks quite fast - so maybe the capacitor is much smaller than planed ?The observed discharge (some 400 mV in 400 µs and thus some 1 µA) is way more than the usual board and diode leakage.There is usually no need for PTFE caps. NP0 ceramic should be good enough: about as good as PP. With TDK brand ones I got a loss factor even about 5 times lower, not much different from what PTFE caps should be.If fast reaction and a long hold time would be needed one can use 2 stages in series: a second slower one with a larger cap for a longer hold time.

author: StillTrying
author_rank: Super Contributor
timestamp: March 03, 2020, 05:00:00 pm
content: Probably something to do with this, page 20.www.ti.com/lit/ds/symlink/opa2388.pdf

author: duak
author_rank: Super Contributor
timestamp: March 03, 2020, 06:21:23 pm
content: The 3rd paragraph of Kleinstein's reply should start with: "The usual way would be to have the feedback for the 1st OP from the output of the SECOND OP". As StillTrying points out, as drawn, the iinput clamp diodes of the first op-amp will try to drag the hold voltage up or down depending on the input voltage.There is usually some sort of reset circuit, either a discharge resistor to ground or a switch to set the hold voltage to a low value.I would also add a bounding clmap to prevent the first op-amp from going too far into saturation when the input is much lower than the hold voltage.

author: Benta
author_rank: Super Contributor
timestamp: March 03, 2020, 07:36:47 pm
content: My guess is that you've bought the parts from China, and that they're fake. Your circuit is fine as it is.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 03, 2020, 08:53:26 pm
content: Thank you all for your replies.I got parts from Mouser. Although soon Mouser will not be distributing TI parts anymore, I do not believe that what I have is fake, at the moment.The capacitor is NP0/C0G dielectric.QuoteQuoteInitially this is what I had, indeed. I had a 20k resistor from the output of the 2nd OPAMP to the inverting input of the 1st opamp. In addition, I also had a diode from the inverting input of the 1s opamp to its own output. I also had a mosfet discharging the capacitor, between 2 input signal cycles, but it "did not work" and I wanted to simplify the circuit as much as possible. I will post tomorow more details about what "did not work" means, probably I will set up a different thread.However, based on Fig42 mentioned above by StillTying, I realize this simplified variant of the circuit is conceptually wrong. The input diodes protection indeed affect the capacitor charge. Even if the difference between the the inputs of the 1st opamp becomes smaller than the internal protection diodes voltage drop, the output of the 1st opamp still works in saturation, as the existing diode in my circuit effectively breaks the feedback loop. Consequently, I cannot rely on the input bias current values indicated in the datasheet, as these are only valid for the linear region, as Kleinstein correctly pointed out.In the circuit variant with the feedback of the 1st opamp being taken from the output of the 2nd opamp, there is no connection between the capacitor and the inverting input of the 1st opamp, hence the stored charge is not being affected.Best regards,Cristian

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 04, 2020, 09:45:54 am
content: OK, so having understood why the schematic in the original post is not functioning correctly, I decided to revert to the original schematic, which was a bit more complicated, "not working" and which I wanted to simplify. As the simplification is obviously flawed, I am back to square one, and I attached the schematic of the original, unmodified circuit, to this reply (Schematic.pdf).This one has indeed the feedback at the 1st opamp taken from the output of the second opamp, through a 20k resistor, and it also has the additional diode (D331) which helps the 1st opamp not to saturate.It also has a MOSFET through which I reset the charge on the capacitor.As can be seen in the attached screenshot, I get some weird behavior, with the output of the overall circuit peaking, but not always at the correct value (see Fig1.png). I am also a bit uneasy about the oscillations at the OPAMP_OUT node during the time the capacitor is held in RESET (uC_PEAK_RST is HIGH), but I suppose these are due to the limited output current capability of the opamp, which would like to be HIGH but cannot source that much current permanently through the 10Ohm resistor and through the RESET mosfet. So while not really liking these oscillations, I am not sure if it is actually related to the output not peaking at the right value when uC_PEAK_RST goes LOW, or if that is due to some other limitation of the opamp. I have also attached some more close-up screenshots of what is happening with the OPAMP_OUT node when uC_PEAK_RST goes LOW (Fig2.png, Fig3.png, Fig4.png).As a side note, I must say I had an earlier version of this circuit, based on the ADA4891-2 opamp from Analog Devices,which was working. I was unhappy with the offset voltage rating of that opamp (10mV), and I wanted to change to something better. I had originally selected the ADA4891-2 based on its extremely low input bias current to minimize storage capacitor voltage decay, but it seems it is difficult to find opamps with such low bias currentandlow offset rating. Anyway, I realized that it is most likely not the opamp input bias current which is the dominant leakage path, as it is a couple of order of magnitudes compared to the leakage current through the reset mosfet (I was using the 2N7002 as a reset MOSFET back then). So I changed the opamp to the current Texas Instruments OPA2388, which also has a reasonable low input bias current, but a much, much better offset voltage; I have also changed the reset mosfet to the smallest leakage one I could find (PMZB600UNELYL). Yet, it seems the change is working against me. I still have some samples of the ADA4891-2 around, but they are SOIC footprint and do not match the footprint on my current board (I have selected the OPA2388 in VSSOP footprint). However, I suppose I can order some ADA4891-2 in a VSSOP compatible footprint version and give it a go in the current circuit. But I am really put off by its large offset voltage, and I would really like to make somehow the current schematic work.Of course, there is the possibility to change the opamp to an even third alternative, but unless I cannot pinpoint what is wrong with the current OPA2388, there are no guarantees I might not be running in the same issues with a new one.There fore...help!Best regards,Cristian

author: StillTrying
author_rank: Super Contributor
timestamp: March 04, 2020, 10:58:38 am
content: In the latest pdf the feedback resistor 20k seems high to me, I'd probably have gone for 2k2 as a first guess to keep the feedback delays as short as possible, but I don't know the answer.https://youtu.be/5Pz7Mx0WRUk?t=138Fromwww.eevblog.com/forum/projects/500khz-peak-detector/

author: Kleinstein
author_rank: Super Contributor
timestamp: March 04, 2020, 11:27:28 am
content: The circuit with the 2nd OP inside the loop of the first OP ideally wants the 2 nd OP to by considerably faster than the 1 st OP. One also has to be careful with the size of the capacitor, as this acts as capacitive load. The resistor as drawn does not help here as it is inside the loop.To some degree it can help to have a transistor as emitter follower instead of the diode.It helps if the 1 st OP is chosen for good capacitive drive capability. The 2nd OP does not need a low offset. The 1 st OP would correct the offset of the 2nd OP, even if large.The easy point to try would be reducing the capacitor to something like 100 pF. One may be lucky and get away without the oscillations.With some OPs is may help to give the 1 st OP some additional current loading to stay on one side of the output stage.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 04, 2020, 12:24:21 pm
content: Thank you for your replies and simulations!I'll try to play a bit with the 20k feedback resistor value, to see if I get some different results.QuoteI am aware of that scheme, but I need to try and make something out of the current PCB layout. Equally, this means I am stuck with using a dual-in-package opamp, so they will both have the same speed. Although, I would suppose the capacitive load of the 1st opamp artificially makes it slower anyway, right?QuoteThe oscillations are not there because of the capacitor. They are there while uC_PEAK_RST is HIGH, which means the reset MOSFET is active and shorts out the capacitor. I am pretty sure they appear because the limited output current capability of the 1st opamp, which must constantly source current through the 10 Ohm resistor and through the MOSFET.Regards,Cristian

author: exe
author_rank: Unknown
timestamp: March 04, 2020, 12:36:38 pm
content: Quote from: brumbarchris on March 03, 2020, 08:53:26 pmCan you please share a link describing the situation?

author: Kleinstein
author_rank: Super Contributor
timestamp: March 04, 2020, 12:47:19 pm
content: The reset phase should not be much longer than needed. Especially there should be a little time between the reset phase and the peak to come. The OPA388 needs some time to recover from effective short at the output and thus recovery for the AZ part of the OP. There is a chance that the oscillations are not classical loop instability, but possibly some residual from the internal chopping. A non AZ OP may be better behaved in this respect.A capacitor at the OPs output would not help - it would make things even worse, as there would be additional phase shift / delay. If at all it would be an extra capacitor in feedback.

author: fcb
author_rank: Super Contributor
timestamp: March 04, 2020, 01:06:12 pm
content: Quote from: brumbarchris on March 03, 2020, 08:53:26 pmAre you sure?AVNET/Farnell have been running stocks down for a year+, and I received this from TI earlier this week:"As you may know, we (TI) are in the process of winding down our business relationships with certain distributors. We are writing today to help ensure you continue receiving the products you need, when you need them. Please see below, and forward this email to your procurement and purchasing colleagues as appropriate.Actions our TI customers should take to ensure business continuity of TI productsIf you currently purchase TI products through Avnet, Compel, Eastronics, MT, Telsys, WPI or WT, we encourage you and your supply-chain partners to immediately start transitioning your new and existing TI business to our long-term supply-chain options:• Arrow Electronics, our authorized broadline distributor in all regions except Japan.• TI.com.• DigiKey or Mouser, our authorized catalog distributors.• TED or Macnica, our authorized broadline distributors in Japan."

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 04, 2020, 03:52:47 pm
content: QuoteWhat does AZ stand for?Cristian

author: Kleinstein
author_rank: Super Contributor
timestamp: March 04, 2020, 05:24:04 pm
content: The AZ stands for auto zero.For an alternative OP one would look for a good JFET OP with good capacitive drive capability.Another point would be a really good phase reserve, like > 60 degrees, as there are 2 OPs in the loop. So 45 deg. Phase reserve would already be too little.If it would not be for the case the OPA1642 could be a possible candidate.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 04, 2020, 06:19:47 pm
content: QuoteAs mentioned before, I had an earlier version of the circuit, using the ADA4891-2 opamp from Analog Devices; that one worked fine. I was unable, however, to find a JFET input opamp with a reasonable good offset voltage. That is why I eventualy selected the OP2388. However, it seems indeed that having this internal auto-calibration feature, while good for offset, is detrimental for a peak-detection circuit. I will have to select another one. I will check OP1642.Regards,Cristian

author: Poe
author_rank: Frequent Contributor
timestamp: March 05, 2020, 12:35:33 am
content: 1. Linearly ramp the input signal down to 0V over 1mS. If the output signal remains the same, the leakage isn't through the diode.2. Add a DC offset to the input and see if the discharge rate changes.3. With the input grounded and the 'ground' pin of the capacitor disconnected from ground and instead attached to the positive rail, does the output trend up or stay low? If it raises, it's the cap.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 05, 2020, 04:46:41 pm
content: Hi,I have clarified the leakage is not through the diode. As I reverted back to the original schematic (see my third post in this thread) I disconnected the feedback of the 1st opamp from the storage capacitor. Now it can hold the charge, but the "jumpiness" in following the peak is what is not good at the moment.Regards,Cristian

author: Kleinstein
author_rank: Super Contributor
timestamp: March 05, 2020, 05:24:42 pm
content: During the reset phase the OP is seeing a near short. Maybe one could consider an additional signal from the reset gate drive to the OP, so that the OP does not have to fight the reset. This could be a diode + maybe series resistor from the gate to the inverting input of the 1st OP.

author: StillTrying
author_rank: Super Contributor
timestamp: March 06, 2020, 01:45:17 am
content: Or an LM292 is a comparator plus opamp, the only one with all the pins in the right order,but not very good specs. 2mV and 1MHz.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 06, 2020, 07:52:19 am
content: This is a good idea and I will consider implementing it. It will be beneficial for current consumption regardless of the OPAMP that I will eventually select.I will also adjust the driving circuit so that the capacitor charge reset duration is limited and only applied briefly just shortly before the expected peak.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 06, 2020, 10:53:48 am
content: I believe I have found the parameter of the OPA2388 which is making it impractical for this circuit. My current guess is that it is its slew rate. It is relatively low, at only 5V/us.The repetition rate of my signal is 1ms, so I always thought about it as of a 1kHz signal. But I've just measured the rise time of my signal and it is some 6us. That's the equivalent of a whooping 60kHz signal (considering the bandwidth * risetime = 0.35 formula). So then, it is not a trivial peak detector that I have to make (which is what I have always regarded it as), but a rather more advanced one.I was watching this EEVBLOG video:Dave never takes the precision variant of the circuit (demonstrated in the second part of the practical demonstration) above 1kHz, pure sinewave. That is how I can explain that a very low slew rate opamp, like the TS912 that he uses works. But here I need to look for something faster, I suppose. I guess that is why the ADA8491 opamp used to work in my older version of the circuit: it is rated as 170V/us. I can probably get away with something in-between.Cristian

author: Kleinstein
author_rank: Super Contributor
timestamp: March 06, 2020, 11:57:19 am
content: For the OPA2388 the limited slew rate is a a weak point. Between the operation through the 2 diodes there is a dead zone of around 1 V. So the detection is behind by something like the time it needs to slew 1 V. However BW is also important: especially with FET input OPs the maximum slew rate is valid with a large signal at the input. So the OPA2388 with it's relatively high BW is not that bad compared to other OPs. So the AD711 with 16 V/µs but only 3 MHz GBW would be even worse.A fast peak detector is indeed not trivial and some 6 µs rise time is fast.With less than 1 ms required hold time one can likely reduce the capacitor - the faster the OPs the less they like capacitive loading.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 06, 2020, 01:02:29 pm
content: I do not really need 1ms of hold time, as I plan to sample the peak detector output with an ADC in a 200us window after the peak. But I would obviously like the cap charge degradation in this window to be as small of possible, below 1mV, if possible.So yeah, I will need to look at faster opamps.I went through this article (https://www.analog.com/en/technical-articles/ltc6244-high-speed-peak-detector.html), which discusses some higher speed (200kHz max) peak detector using the LTC6244. Whereas using the "improved" topologies suggested in the article is not practical for us (due to the necessary -8.5V negative biasing voltage required, I take it from the article that the LTC6244 would be suitable at these speeds. It has a limited Vcm to 3.5V though, and I will need to detect peaks as high as 4.5V.I have also watched this video suggested in the posts above (https://www.youtube.com/watch?v=5Pz7Mx0WRUk&feature=youtu.be&t=138), and this guy is proposing replacing the 1st opamp in the loop with an actual comparator (so this is something I will also look into,although first ever best preferred approach is to find out a suitable opamp that will work in my current schematic)

author: StillTrying
author_rank: Super Contributor
timestamp: March 06, 2020, 01:45:23 pm
content: Quote from: brumbarchris on March 06, 2020, 07:52:19 amThe first one I drew is near enough what Kleinstein said on the last line of his post.Quote from: brumbarchris on March 06, 2020, 10:53:48 amFrom that I'm not sure a large speed increase is needed. The op amp output having to change by about 2.5 V in 6 us is only about 0.4/us, and less than 1mA charging a 1nF, even if the output has to come out of saturation 2.5V/usseemslike enough, but you do have to stay long way off the data sheet's max. slew rate because there's usually quite a few things it hasn't said about what happens there such as a large loss of GBW at least!From your last post the ADC'ssample timesounds like the most important, for most digiltalADCs it doesn't matter if the input droops while it's converting because it's then using it's own sample.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 06, 2020, 02:08:22 pm
content: HiOur ADC will sample at about 2us intervals and will take in a 200us window 3 samples that it will average.Coming back to the peak detector: I have also found somethting else in the datasheet of the OPA2388 that might make it unsuitable, apart from the relatively low slew rate: it is the phase shift (see attached graph).It seems that it introduces a phase shift of -90 degrees across quite a large portion of the bandwidth, including the 60kHz I am dealing with. And considering that I have two opamps, somewhat in series (the feedback of the 1stone taking the feedback from the output of the 2nd one) this can result in a rather nasty 180 phase shift. Of course, the graph is only showing the open loop phase shift, I am not sure how to relate that to my current circuit, as I have the overall circuit operating with a unity gain, more or less.Regards,Cristian

author: Kleinstein
author_rank: Super Contributor
timestamp: March 06, 2020, 02:16:33 pm
content: The "improved" configuration in the AD article is using the diode outside the loop. So this is a 2 sided change: it makes things faster, but it also reduces the precision.At high speed the classical version is also not perfect - because of delays and the limited BW. So it depends on the length of the pulses which version is actually better.For the high speed range I also remember some discrete transistor based versions that may be an option.I would not expect 1 mV accuracy to be possible. Some droop from the capacitor may be more acceptable than high capacitive loading to the OP. So I would definitely consider a smaller capacitor - more like 20-100 pF for high speed, as this can allow a faster OP.The 90 deg. Phase shift is normal for open loop operation. The curve for the OPA2388 is actually quite good, as even at unity gain the phase shift is only 90 degrees and not more like 120 as with many other OPs.However those phase shift plots have to be taken with a grain of salt: they can change with load current and also a capacitive load.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 06, 2020, 02:43:14 pm
content: QuoteWhich figure in the datasheet did you see that in? I am having trouble finding it myself.And even if it were 90 degree, would this not give me trouble with two cascaded opamps? Is that not a sumation that I need to make (meaning 90degree from 1st opamp + 90degree from 2nd opamp = 180degree -> oscillations)?Regards,Cristian

author: Kleinstein
author_rank: Super Contributor
timestamp: March 06, 2020, 04:06:42 pm
content: The diagram is the one attached. The 2 nd OP is working with feedback. The feedback reduces the phase shift for much of the lower frequencies. even the about 90 deg. Phase shift near 10 MHz is still critical and chances are the circuit is still at the edge of oscillation. This is why it would really help if the buffer is faster than the 1 st. OP. One may be able to slow down the 1 st OP a little with some capacitance or RC between the inputs. I am still not sure how much this help with the nonlinear FB.One could consider a solution with a single OP and a JFET as buffer amplifier - chances are the JFET as a source follower is quite fast compared to the usual OPs. DC errors from the FET are still compensated by the OP.

author: AE7OO
author_rank: Regular Contributor
timestamp: March 14, 2020, 04:20:51 am
content: Hi,I did not see a posted speed(or I missed it), so I'll go ahead throw my goto sample and hold into the mix.Years ago I picked up a couple of tubes of NS LMC660's at a hamfest. You'll have problems finding anything with a lower input bias current(2fA) or input offset current(1fA). There is an app note floating around detailing the problems trying to measure them. It's offset voltage of 1mV is not too bad. Common mode input range includes ground or below.When combined with a decent CMOS switch on the input(one of the 4066's is what I use) and a PP (or one of my horded Sprauge(sp) mil-spec hermetic polystyrenes, also hamfest) cap, and using deadbug construction makes a very low leakage S&H.I've used it up to about 200Khz.I just use the diagram from the datasheet.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 26, 2020, 02:43:10 pm
content: QuoteActually, I really need a peak detector, not just a S&H; unless, that is, if there is a way of determining when the maximum in the waveform occurs, in order to open the switch off the S&H at that particular moment.QuoteI eventually got it to work...sort of; using an Analog Devices AD8656ARMZ, which is foot compatible to the OPA2388. So it does work, but the error is unacceptable high. So I conclued that it is probably better to go and use to different opamps, as you suggest above. As I determined it with my experience in this circuit so far, the characteristics required for these to opamps are:- first opamp in the chain (the one charging the cap) must not necessarily be a CMOS /JFET input one, but it must have:- low offset voltage- extremely good slew rate- high output current- RRIO (my input signal range is some 0...4.5V)- second opamp in the chain must definitely be a CMOS / JFET input one and it must have:- low input bias current- lowest possible phase shift; this is actually critical. Every bit of phase shift will result in a delay in the feedback loop which essentially delays the first opamp to "sample" the input signal and recharge the capacitor; actually, this is a big problem I have, because I am not sure how to infer the phase shift of an opamp at Gain=1 from the information available in the datasheet. Most datasheets provide a graph with the phase shift in open loop conditions.- RRIOBest regards,Cristian

author: Kleinstein
author_rank: Super Contributor
timestamp: March 26, 2020, 02:56:51 pm
content: Low phase shift in closed loop operation as a buffer kind of means high speed. So the 2 nd OP should be at least as fast as the 1st one, ideally more like > 5 times faster.How critical the leakage current is depends on the hold time needed. So how long until the result is read. Depending on the application there can even be an advantage of there is a defined bias current (for one application I used an LF356 together with an LM318 - with the BJT intentionally as the buffer, as the bias provides a defined drift in the right direction). For a short time leakage is not that bad.If long time analog hold is really needed one can add a second, slower stage.The AD8656 is not such a bad choice.

author: brumbarchris
author_rank: Regular Contributor
timestamp: March 26, 2020, 03:21:47 pm
content: I am not sure why you indicate the second opamp should be faster relative to the first one. I suppose low phase shift is something generally referenced vs the input signal frequency, rise time, etc. I mean, the voltage at the input of the second opamp will have about the same change rate as the signal at the input of the first opamp, so in this case I would consider the second opamp to be as low as possible in phase shift, period. If the first opamp is faster, then even better! Not so?Cristian

author: Kleinstein
author_rank: Super Contributor
timestamp: March 26, 2020, 03:31:40 pm
content: Low phase shift in close loop comes with high bandwidth. The speed is mainly needed for stability, not because the signal actually changes so fast.The first OP may want good driving power for a capacitive load - this does not necessarily need high current. In parts one could get around this by using a transistor as emitter follower instead of the diode. Also the memory capacitor may need to get smaller at high speed.For high speed rail to rail operation is often a problem. So if the signal is 0 - 4.5 V, one should consider a supply that can go a little higher. With RR OPs there often is a cross over range at something like 1.5 V below the supply. In this range the OP is slowed down to correct internal errors.