Need PCB placement EMC advice for analog/digital 4 layer board - Page 1
Forum section: electronics / projects

author: Axk
author_rank: Regular Contributor
timestamp: June 15, 2019, 01:32:48 pm
content: I'm doing an e-bike power meter as a hobby project.The design might be a bit of an overkill for what I'm doing, but this is a hobby project and I need to learn something so it wouldn't be fun to do the simplest and most practical thing. Max current - 20A, ADC - 12bits (1LSB - 5mA), (over)sampling rate - 1.5Msps, bandwidth - 100KHz, digital clock - 50MHz.I would like to get as good resolution as possible, down to the limits of the ADC if possible.I'm planning to use a 4 layer board, 2 signal layers (preferably all signals on the top) and 2 power planes.The design contains a 5 mOhm shunt resistor and a current sense amp with a unity gain buffer between the output of the current sense amp and an ADC.A voltage divider to measure the voltage (54.6V max) with a unity gain buffer (a double op-amp shared with the current sensing) and the same (dual channel simultaneously sampling) ADC (1.5Msps, 12 bits). The opamp's negative rail is powered from a negative charge pump to get a true zero output.The current sense amp is powered directly from the 50V supply while everything else from a 3.3V regulator (with a discreet heat-sinked TO-220 NPN, the whole board will be attached to a 3mm aluminum plate with the TO-220 bolted to the plate directly off-board).From the ADC it goes to an FPGA (Lattice Mach XO2) and then a Bluetooth module to send the info to a phone.I've done a project with an FPGA so I should be able to pull the FPGA part off.My main concern is analog signals and EMI between the digital and analog sections of the board.I've done some reading on EMC, low frequency vs high frequency ground plane signal return paths, ground loops, bypassing and so on on learnemc.com/tutorials but I'm a bit overwhelmed as to what is more or less important in my particular case.Besides digital/analog signal return paths crossing on the ground plane I'm also concerned about analog and digital circuitry sharing the same voltage regulator (50V -> 3.3V) and CMOS transistor switch (1 Ohm). The digital FPGA and Bluetooth module sharing the regulator with the Buffer amp and the ADC, the current sense amp is powered directly from the 50V supply but is still sharing the switch with everything else.I'm attaching the screenshots of the schematics and my first placement attempt.The board in 10cm long, the smallest passives are 0603s.The current is going from the bottom connector to the top on the left of the board.POWSW - power switch, supplies everything else with 50V (the connector in this section if for external switching);CS - current sense amp;R6/R7 - the voltage sensing divider;VREG - 50V-3.3V regulator (with holes for wires to go on the bottom to an externally mounted TO-220 just off the left edge of the board)BUF - the unity gain buffer dual op-amp;NEGV - the negative charge pump for the op-amp's negative rail;In my understanding the most EMI sensitive connections would be from the shunt to the current sense amp (0.02 mV/LSB) and from the current sense amp (the voltage across R10, 1mA full scale) to the buffer (0.6mV/LSB) so these should be as short traces as possible and away from digital currents.Thus I'm placing the current sense amp right next to the shunt and the buffer right next to the current sense amp.I'm placing the digital portion's connections at the top so that the digital high frequency currents flow from right to left across the top of the board to the regulator on the top left not interfering with the currents between the regulator and ADC/buffer.I would put a slot in the ground/power planes horizontally on top of ADC/buffer to further separate them from the digital currents but this then creates a loop for the return signal currents going between the FPGA and ADC so the digital currents will go near the analog sections currents anyway.Any advice is appreciated if my placement is any good.

author: DannyTheGhost
author_rank: Contributor
timestamp: June 15, 2019, 02:33:01 pm
content: I think you are too concentrated on EMC problem that you don't see more important details to your project.First of all, you don't have that much components and almost no high-speed signal lines to go for 4-layer boardSecondly, if I were you, I would worry for PCB traces handling 20A of current more that EMCIn your case I'd rather go for star-ground configuration (digital and analog power planes and traces are connected only near power supply) which will deal with all noise almost perfectlyAlso, no need for components to be so far from each other

author: Axk
author_rank: Regular Contributor
timestamp: June 15, 2019, 02:41:33 pm
content: @DannyTheGhost, I think a short 1 cm wide (3cm long) trace should handle the current.I'm going to have a 50MHz digital clock for the ADC, I thought it qualified as high speed.

author: Axk
author_rank: Regular Contributor
timestamp: June 15, 2019, 02:57:38 pm
content: One thing I've just noticed is the current sense amp is between the regulator and the switch so all the current from the switch to the regulator and back will go under the most sensitive current sensing amp area...Need to move the switch to the top somehow so that it's next to the regulator I suppose...

author: DannyTheGhost
author_rank: Contributor
timestamp: June 15, 2019, 03:00:29 pm
content: Ground plane right under 'high-speed' digital lines should be enough for your application.By the way, are you really sure that you need that kind of bandwidth for current sensing? You won't see much more with this bandwidth except additional noiseEdit: if you reconsider your bandwidth requirements you could also lower your clock speed

author: Rerouter
author_rank: Super Contributor
timestamp: June 15, 2019, 03:21:29 pm
content: Do you want to measure the Raw PWM induced noise, or the average current at that given moment, as that will influence how I approach this,First up, I would group the current sense and buffer as close to the current shunt as within reason, the smaller your loop areas the harder it is to pick up noiseIf you only want an averaged current, I would be filtering it down with some capacitance at the current sense amplifier (after its series resistors), to trim it to what the amplifier can produce, then possibly at its output to lower to what the ADC can measureThat area of the board will be getting quite hot, so I would have them floating on there own little Via enclosed island, to keep the temperature gradient pretty low across the CS and buffer,I'm assuming you don't really care about the lowest of the the low currents, as with no offset from ground you will likely see issues with low currents where the amplifier and ADC don't really have any means to quickly drag the signal that close to ground,Now that the current signal is filtered to what you can measure, and buffered to a low output impedance, your more free to route it furthur away from the current shunt, I would not go too crazy, but a few cm's will be OK, just treat the buffer ground as the negative of a differential signal and don't join it to your main ground plane at the ADC, As for fancy ground planes, Have the branch close to the ADC, then run to the CS/Buffer run your signal / return for the signals over the plane connection between them,For the FGPA / Bluetooth stuff, spinkle decoupling caps like the datasheet recommends, place them as close as you can to there respective power pin groupings, the back side of the PCB is always an option, and for your ADC-FPGA data lines, you may want to throw some 50-220 ohm resistors on the output for that data line to reduce the bandwidth of the radiated signal edges, your near something really noisy, but no need to make more noise.And finally, data lines always over an unbroken ground plane, if you need to hop with a via to another layer, slap a via to ground close by, so the return current can follow it, (path of least impedance)

author: Axk
author_rank: Regular Contributor
timestamp: June 15, 2019, 04:14:51 pm
content: @Rerouter, I considered low-pass filtering the current signal but then was not sure if the filtered signal would give as accurate a result as over-sampling the raw PWM induced saw-tooth current waveform, so I decided to go with the oversampling. With filtering it would be an easier project, but less fun.I thought I could also measure low currents, like the controller's quiescent current. With the op-amp's negative rail pulled a bit below ground (with the charge pump) I thought the op-amp's output could go down to true zero and then I would only be limited by the ADC's offset which is (+/-)10 LSB max, (+/-)1 LSB typical in my case.The current waveform that I measure can be seen here:https://electronics.stackexchange.com/questions/415750/low-pass-filtering-effect-on-accuracy-of-power-measurement

author: Axk
author_rank: Regular Contributor
timestamp: June 15, 2019, 04:22:50 pm
content: Considering the high currents and finite internal resistance of the battery the voltage will be also more or less repeating the current waveform albeit with a lower amplitude. With both voltage and current averaged I'm not sure how this affects the accuracy of the power measurement.Again, this is probably an overkill, but too easy = not fun.

author: Rerouter
author_rank: Super Contributor
timestamp: June 16, 2019, 12:17:01 am
content: All op amps struggle when it comes to getting within a few mV of there rails, there output stage is built out of transistors or mosfets, and they have some non zero resistance. so you take the current the ADC is gulping each sample, times that by the resistance and you get your minimum output voltage, To better measure close to ground you can bias the op amp output with a resistor to the rail you want to get close to, e.g. 1K to ground would mean the op amp has a load to drive into and can bring its output to essentially off to get down closer to 0,To help this cause was why I recommended chaining your power from the ADC out, this means any supply current and trace resistance of the CS/Buffer will raise the ground at that point to hopefully drag the low current measurements out of the noise.I would still say filter things down, but in this case to about 3-5x the sampling rate maximum, this way your not forcing the CS and buffer to amplify signals faster than you need them, e.g. your CS amplifier has a maximum bandwidth, you want the signal its measuring filtered down to below its maximum to make sure your readings are meaningful.