Modifying an OLED laptop to work with an IPS panel (Displayport Troubles) - Page 1
Forum section: electronics / projects

author: Kinsi
author_rank: Contributor
timestamp: August 06, 2025, 06:36:53 pm
content: I've been working on this project for a month or two now, for those that want the long yappy story, theres that:https://www.reddit.com/r/hardwarehacking/comments/1lkdg3i/replacing_a_laptop_oled_panel_with_an_ips_lcd/The TL;DR Version: I bought a Laptop which by default comes with a 4K Samsung OLED Panel (ATNA60YV05) - That one is broken and a replacement is costly, so I decided to try and replace it with a much cheaper IPS panel instead (NE160WUM-NX2).With a bunch of detective work / educated guesses and painstaking continuity measurement I eventually figured out (What I assume to be) the pinout of the original Panel (The Datasheet is unobtainium) and created a PCB whose purpose is to adapt the pinout (The flying differential pair here is the AUX channel which is low bandwidth and everything unpopulated is intended for backlight PWM control which I dont need for testing):Now, this shows signs that it would work, but clearly it doesnt:The acer logo is recognizable within the static, so something is making it through, but its off-center and once I get into the OS the screen turns blank - amdgpu will then log that enabling the link 0 failed with errorcode 15. The same error persists no matter the refreshrate or resolution that I try.I then proceeded to try and put Kapton tape on the last two DP lines because my assumption is that on bootup it would only use the lower two lines, this results in no picture whatsoever - Same deal if I try taping off the other two lanes.Essentially this boils down to one ultimate question I hope somebody would be able to answer:Would I even get anything like the image in attachment 3 if..- I swapped N and P of the differential pairs- I swapped lane order entirely (3=0, 2=1, ...)I'm waiting on a test board that I can use to make sure the eDP cable and replacement screen are known good, if thats the case I'm kind of out of ideas and would probably proceed to connect two lanes with flying wires and test that with a low resolution to see if maybe I did actually swap lanes / polarity.Thanks!

author: coromonadalix
author_rank: Super Contributor
timestamp: August 06, 2025, 09:55:12 pm
content: could theses pinout fit or help ? edp 4 layers 40 pins google search ?https://hackaday.io/project/179868-all-about-laptop-display-reuse/log/209701-common-edp-laptop-panel-pinoutshttps://novoselovvlad.ru/2019/04/17/%D1%80%D0%B0%D1%81%D0%BF%D0%B8%D0%BD%D0%BE%D0%B2%D0%BA%D0%B0-edp-30-pin-2-lanes-%D0%B8-40-pin-4-lanes/https://github.com/FrameworkComputer/Framework-Laptop-13/tree/main/Display#pinout

author: Kinsi
author_rank: Contributor
timestamp: August 06, 2025, 10:41:11 pm
content: That is the "Standard" pinout which is known / used for 99% of panels - All but (Samsung) OLED ones anyways. Thats the one I used for the "output" of my PCB for the replacement screen and I'm pretty certain that ones correct.In my case I had to correlate the pins on the Laptop to the ones on the original OLED panel (They're not mapped 1:1) and then used this picture of a breakout board thats compatible with that panel and the traces visible on it combined with some measurements on mine to figure out which pin is whatThe displayport socket ofc has a known pinout which Is the one I referred to for deciding which pin is what lane / polarity. Assuming I'm on the right track, the diff. pairs would be (from left to right) lane 0-3 and then the AUX pair, with all of them being +/-. It is then flipped horizontally by the cable (The pairs are on the left side on the original panel)

author: amyk
author_rank: Super Contributor
timestamp: August 07, 2025, 02:32:00 am
content: What laptop is it? Have you managed to find a schematic? That should tell you the exact pinout.The fact that you're getting a faintly recognisable signal at boot (where it should be operating in a low-resolution mode), but none thereafter, suggests that the GPU may be changing to a high speed mode that your display doesn't support. Also, given that it's an internal display, the parameters may be hardcoded in BIOS.AMD has some (Linux) GPU tools that may be able to diagnose / dump the DP parameters including forcing link retraining etc. so you can see what exactly it doesn't like.

author: Kinsi
author_rank: Contributor
timestamp: August 07, 2025, 03:17:42 am
content: The Laptop is a Acer Swift Edge SFE16-42, unfortunately I was not able to find a Schematic or Boardview for it / any related models.Yes I do get a signal at boot but clearly it is heavily corrupted. The AUX channel is functioning properly and the displays EDID is read out properly (Freesync is detected as available, etc) - I dont believe the parameters would be hardcoded but obviously cant rule it out, maybe on boot but I dont see that being the case once in the OS (I figure at that point the driver should take over and work in accordance to the displays EDID). Given that originally, it is a 4K panel, the acer logo would be significantly bigger if it was (trying to) output at the native original resolution.Even going for its base resolution 1920x1200@60Hz (Its a 165Hz Panel and 60Hz is supported) leads to no image.Given these circumstances, I believe one of these to be the culprit:- Polarity is swapped (Tho, if that is the case I doubt I would get any image at all?)- Lanes flipped, on boot the laptop uses only 1/2 lanes and the signal *somehow* makes it over passively to the correct lanes (When its sent to the wrong ones), but in OS it tries to always use 4 lanes and thus never outputs anything- The 40 pin cable is bad in one way or another- The panel is faultyThe last two points I will be able to confirm when I get my hands on the test board (probably tomorrow).For what its worth, I am on Linux for testing - Changing the Display resolution / Refreshrate does try to retrain (And subsequently logs the afformentioned error in dmesg)

author: amyk
author_rank: Super Contributor
timestamp: August 07, 2025, 05:04:31 am
content: I just gave the DP spec a quick read, and from that it's pretty clear that if only some of the lanes were misbehaving / swapped, you'd see vertical lines of corruption as the pixel data is striped consistently across them, repeating every 4 pixels.The fact that you get no image at all if you physically disconnect any of the lanes can be explained by the DPCD: it's identifying as a 4-lane panel, so the DP source tries to enable all 4 lanes, and the disconnected lanes won't link up, so it fails completely.As DP is a packet-based protocol, the link speed is independent of the resolution and refresh rate. If you can, try forcing the lowest link speed that still has enough bandwidth for the lowest resolution.I suspect you ultimately have a signal integrity issue. Try connecting the lanes using twisted pairs (with slightly different twist intervals), and not via a PCB.

author: Whales
author_rank: Super Contributor
timestamp: August 07, 2025, 06:01:37 am
content: These signals are many gigabits/second, so they're very sensitive to a number of things.1. Impedance. How did you calculate the trace width and spacing for the high speed pairs? I can double check it for you if you provide a link to the manufacturer's page on stackup (copper thickness, insul thickness, insul material).2. You will want an uninterrupted ground plane beneath the pairs, but it looks like it is cut by lots of different traces. I'm not sure if it's possible to solve this with a 2-layer flat flex, so it might be worth accepting the need for more flying wires.3. Power. I only see one via or no vias next to capacitors. Bad power delivery can exhibit the same symptoms as bad signalling.4. Pair skew correction. I notice you're adding extra length to half of each pair to compensate for them going around corners. I'm not sure if it matters at this scale, but it might be worth splitting that skew correction into two halves (one near each of the 2 corners the pairs take) so the corrections are closer to the causes of the skew.

author: Kinsi
author_rank: Contributor
timestamp: August 07, 2025, 08:58:02 am
content: Quote from: amyk on August 07, 2025, 05:04:31 amThank you for those details - Having triple-checked everything I was pretty sure that my lanes and polarity is correct and I figured I wouldnt get any recognizable image whatsoever if anything was incorrect.I will try and see if I can somehow force a lower link speed or even lane count somehow, hopefully that should give me more clues - Should I not find a way to accomplish that I dont think that I would get anywhere by just handwiring twisted pairs given the fact that the spec calls for <5mil of skew on each pair and <50mil between all pairs but I was indeed going to try that. Ofc a spec is a spec and I'm not sure how "give or take" that is here but I dont think I could get anywhere near with botched wires.Quote from: Whales on August 07, 2025, 06:01:37 amI wont lie, this is my first time dealing with signals that are remotely as fast as this, I'm certain I made errors.1: I'm not exactly sure what my reference was anymore unfortunately. For what its worth, my traces are 5 mil wide and they have 7 mil spacing. I ordered with JLCPCB, it is a 2-Layer w/ 25µm dielectric thickness and 1/3 oz copper:https://jlcpcb.com/capabilities/flex-pcb-capabilitiesFor what its worth, as I use the edge connector on the PCB itself to plug into the laptop I had to make it more rigid, to accomplish that a piece of plastic is superglued to the back of the PCB - I'm not sure if that matters here but I'm mentioning it to be sure.2: The ground plane beneath the pairs is indeed cut but only by one other diff. pair (The AUX pair)3: That its true, for what its worth I initially tested without those capacitors and hoped adding them would make my issues go away, in my observation they changed nothing whatsoever with observing the exact same behavior with or without them4: While I do not remember the source for (1) anymore, that same source mentioned I will want to correct the skew near the source of it. In my case the pair skew is <1mil, the biggest difference from one pair to another is 1131 vs 1115 - Given that the spec calls for <50 mil I do have to wonder if the difference on the laptop pcb itself in addition to mine might kick it out of specThanks a lot to you two

author: Whales
author_rank: Super Contributor
timestamp: August 07, 2025, 10:00:22 am
content: QuoteHow dare you you! You are now forbidden from electronics! I will inform the guild as soon as they forgive meQuoteTy for the links and numbers.I'd appreciate it if someone else checked if I'm entering my numbers into KiCad's impedence calculator correctly, but assuming that I'm correct:Your trace sizes are for 50-ohm differential impedance (last number at bottom right of screenshot); but displayport expects 100-ohm. I've used two different dielectric constants here (the exactly 50-ohm result is if you use the constant for FR4, which is wrong, but 57 ohms and 50 ohms are _probably_ within manufacturing error anyway).I don't think it's actually possible to get 100 ohm impedance with your particular choice of stackup, 2 layers and JLC's track thickness rules for this medium. I struggle to get anywhere close with my calculatorEDIT: Yay I might not be the only one, seehttps://electronics.stackexchange.com/questions/663304/flex-pcb-controlled-impedanceQuoteYeah, my comment about skew probably isn't useful.

author: Whales
author_rank: Super Contributor
timestamp: August 07, 2025, 10:17:06 am
content: Would the 50um thick PI version of the flat flex ribbon work for you instead of the 25um thick version? Total overall finished thickness is apparently about 0.19mm and most flat flex connectors I've seen expect either 0.3 or 0.2mm100-ohm impedance pairs look doable with the thicker core:

author: Kinsi
author_rank: Contributor
timestamp: August 07, 2025, 12:12:03 pm
content: Quote from: Whales on August 07, 2025, 10:17:06 amThanks a lot for those details.If it is in any way avoidable I would prefer to stick to the 25µm for the sheer reason of cost, going for 50µm over 25µm increases the cost from just 2€ to 25€.Am I understanding it correctly that this here is mainly about the distance between the ground plane to the lines? If that was the case, at JLC any PCB up to 10x10cm is the same price - What I could do is *not* have a ground plane behind the data lines on the main PCB and include a second mirrored pcb of the same shape which is just a ground plane and then glue that back to back making for a cursed 3-layer pcb which I've basically already done for this first order to have a breakout / test PCBQuote from: Whales on August 07, 2025, 10:17:06 amThe connector in my case is ~0.55mm thick, its not a flat flex but some cursed 40 pin connector that as far as Google is concerned doesnt actually exist (attached)For what its worth, as I was writing this I got the test PCB in the mail and hooked it up to my PC (Native DP connection thats just passed through to the Panel on the PCB), the panel itself and cable are perfectly fine and work flawlessly at native settings (1920x1200 165Hz)

author: wraper
author_rank: Unknown
timestamp: August 07, 2025, 12:29:45 pm
content: Quote from: Kinsi on August 07, 2025, 08:58:02 am"only". FWIW it basically has no continuous ground and at signals this fast, current will jump over the gap, not go around. Also it makes no sense screwing up all 4 fast differential pairs because you could easily route it around. And if you did not want to put traces under metal part of the connector, you could run it either on bottom side or around the connector on top side and jump over the rest of the traces on bottom side (less desirable due to GND interruption under AUX, but it's a slow lane, so does not really matter).

author: Kinsi
author_rank: Contributor
timestamp: August 07, 2025, 12:39:18 pm
content: Well yeah you live you learn, as mentioned before I never dealt with signals of this caliber before and now I know better. I'll definitely change that when I order the next revisionI've also now tried to use a custom resolution of 800x1200 with low total pixel count and thus low pixel clock and put kapton tape on all but lane 0 - At least on my PC / Nvidia GPU this still delivers an image onto the panel with just that one lane, should be good for testing (I'll try that on the laptop later)Edit:Okay I have now reinstalled Windows because testing custom resolution / EDID stuff is, somehow, much easier on Windows.What I have found is that by default the Driver will try to drive the display with 4 Lanes at 4.32gbps (HBR2-ish?) - This is what yields a blank screen. It keeps this lane count and data rate no matter what resolution I pick.If I then however download a utility that allows me to intercept / customize the EDID (Custom Resolution Utility) and delete all the default info / create my own entries there I do finally get an output. It is corrupted in the same way as the bios / bootup screen, but it is an output (Video attached for reference, you can vaguely make out one of Windows 11s default backgrounds). In this state the driver uses 4 Lanes at 1.62gbps (RBR). Oddly enough, when I try the narrow resolution that worked on my PC / Nvidia GPU the driver tries to use 2 lanes rather than 4 but I am back to a blank screen.Given that I probably need to reorder a new PCB anyways I have also tried something stupid and scatched off the soldermask where the ground plane is broken up and bridged over it but this also make zero difference.Edit2:Well then, heres the idea. I've re-routed the data lines, they're now 3 mil wide with a 3 mil gap with no ground plane behind them - All the pairs are now also within 3 mil of each other with each pair being ~1mil to itself. Additionally theres a second PCB, that one has a full ground plane, both combined makes for ~50µm - Since the laptops connector has pins on both sides and the pcb is screwed in place on the laptop at grounded points, ground of both seperate PCBs is is connected. Obviously vias arent a thing here. I'm unsure of how much importance that would be.I might have to redo the tracks and make them wider as my overall thickness needs to be closer to 0.5mm to work as a connector but the general idea is there - Not sure if increasing the distance to the ground plane this much would then come with its own issues as increasing the thickness past a certain point seems to not make a dent in the impedence, best bet probably would be only increasing the connectors thickness and leaving the rest of the pcb as is.

author: amyk
author_rank: Super Contributor
timestamp: August 08, 2025, 06:13:29 am
content: Quote from: Kinsi on August 07, 2025, 08:58:02 amTrue, 5 mils is not much but if you cut a set of wires in parallel you should be able to get them to match in length within that tolerance; then simply twist them together. Note that the existing cable on the panel with its wires may already have more variance than that, if the connector was soldered on the board very slightly askew or mated just slightly off. Since you have already confirmed that the panel works with your desktop, you can try plugging in the connector not-fully-seated, with some slight skew, etc. and see what difference that makes to the signal, to get an idea how much tolerance you actually have. Ultimately, a short adapter cable may be easier to get working than a PCB.

author: Kinsi
author_rank: Contributor
timestamp: August 09, 2025, 10:48:05 pm
content: I think I'll just wait for the new PCB - My hopes of it just having been an issue of incorrect impedence is high. The bottom left part will just flip over and be glued back to back to the main pcb to make for ~50µm to ground for the data lanes, additionally I can let solder flow through the bigger pads so the grounds are connected well.Gonna take two weeks or so to get here, I'll report back with the results. Thanks a lot for all the help!

author: wraper
author_rank: Unknown
timestamp: August 09, 2025, 11:00:56 pm
content: Where are vias to GND plane? There are GND connector pins between differential pairs for a reason. Placing a single via somewhere far away from the pin, or from an opposite side of where signal comes form does not cut it. Also do not use one long wiggle for trace length matching. Use a few small ones, preferably distributed over the length.

author: Kinsi
author_rank: Contributor
timestamp: August 09, 2025, 11:08:47 pm
content: Its the bigger Pads next to the connector and between the data lines / and matching on the bottom part that will flip over which I'll then link up / solder together.I used JLCPCBs EasyEDA (Pro) for making this PCB and I am probably blind but I couldnt find a way to make the wiggles tighter which is why they are the way they are, I would've preferred them to be tigher myself too even just for layouting reasons. FWIW I already ordered yesterday so its too late to adjust now anyways.

author: wraper
author_rank: Unknown
timestamp: August 09, 2025, 11:29:52 pm
content: Quote from: Kinsi on August 09, 2025, 11:08:47 pmThat is absolutely worthless for signal integrity. Actually it's an insane abomination which most likely is even worse than it was initially with split GND. BTW did you ever calculate impedance of those differential pairs? I really doubt that if you decided to do something like this.

author: Kinsi
author_rank: Contributor
timestamp: August 09, 2025, 11:44:22 pm
content: Mind helping me to understand why that is so? How would "real" vias (Unachievable with my solution) be any better than what I am doing here? I mentioned before that this is my first time dealing with signals of this class - If this was my profession I probably wouldnt be here asking for help.Yes I have now, or rather Whales has pointed me in the right direction above. 50µm with 3mil traces spaced 3 mil apart is about 100 ohm accoding to the calculator.

author: wraper
author_rank: Unknown
timestamp: August 09, 2025, 11:49:57 pm
content: Quote from: Kinsi on August 09, 2025, 11:44:22 pmInitial solution obviously was a 2 layer flex PCB, which is all you need for proper differential pairs with approximately right impedance (you calculate trace dimensions based on material thickness an permittivity). Running GND separate from those traces is a dog shit with impedance randomly depending on how close those two sandwich layers will touch in any place under the differential pair, not to say there is no straight GND path anyway.

author: Kinsi
author_rank: Contributor
timestamp: August 10, 2025, 12:10:15 am
content: I implemented it this way purely for cost saving, this PCB cost me 3.50€ shipped - If this solution doesnt work, oh well, then I can still re-order it with 50µm thickness which would then however cost me 10x as much.I will be glueing the layers together with thin superglue and have it sit in a vice while curing - I cant see the difference across the board being of much relevance but again, I am new to this.Quote from: wraper on August 09, 2025, 11:49:57 pmNow this is the main part that I fail to understand, on both ends (Incoming connector and exiting i-pex socket) the extra ground is connected to the main ground / ground pins on the ends through the pads - What makes this solution worse than using actual vias?

author: wraper
author_rank: Unknown
timestamp: August 10, 2025, 12:19:51 am
content: Quote from: Kinsi on August 10, 2025, 12:10:15 amVia locations. They're all over the place, not as if this was a high speed circuit. You need to understand that those GND pours between differential pairs are basically useless.

author: Kinsi
author_rank: Contributor
timestamp: August 10, 2025, 12:30:05 am
content: So given the circumstances, this is then primarily about not having vias right next to the exiting socket like I have on the incoming plug? If so I reckon I could fix that up by just punching through a small hole and linking them up right there as well or is that not good enough?

author: moffy
author_rank: Super Contributor
timestamp: August 10, 2025, 12:50:37 am
content: Though this is an Altium specific document it also explains the basic principle of 'via stitching':https://www.altium.com/documentation/altium-designer/via-stitching-via-shielding-pcb

author: Kinsi
author_rank: Contributor
timestamp: August 23, 2025, 10:50:01 pm
content: I got the new PCB today, glued the flipped over part on in a vise and soldered together the matching vias. I gave it a try and... I get the exact, and I do meanexactsame behavior / corrupted image on RBR and nothing on speeds higher than that.Sure this solution might not be perfect but in my head the now much closer-to-spec impedance and much tighter length matching should at least makesomedifference shouldnt it?Given these circumstances I've also tried to manually link together the flipped over part close to the output socket not just on the input and that also made zero difference.I'm starting to wonder if I didnt afterall possibly flip lanes in one way or another (Altho based on the spec that should yield no recognizable image at all?) or if its just outright incompatible for some reason beyond me. Given these findings I also dont really wanna try and order a "proper" 50µm pcb to see if that resolves my issues because I dont have faith in that doing it. Kind of out of ideas at this point unfortunately

author: amyk
author_rank: Super Contributor
timestamp: August 24, 2025, 02:21:31 am
content: Just try twisted pairs.

author: Hydron
author_rank: Super Contributor
timestamp: August 24, 2025, 12:02:31 pm
content: I would start by trying to make a test board with the connectors parallel to eachother - that way there's no intra-pair length matching issues. Inter-pair length matching might be able to be ignored entirely - check the DP spec (PCIe and ethernet have very loose specs for this for example, as everything is lined up again within the receiver). You should be able to hit the required 100R diff (make sure that SE impedance isn't too far off 50 as well), and just ditch the copper pours on the top layer and concentrate on having good connection to the bottom ground later close to the connectors.

author: squadchannel
author_rank: Frequent Contributor
timestamp: August 24, 2025, 12:19:44 pm
content: I found it quickly. Taobao, 18 RMB

author: Kinsi
author_rank: Contributor
timestamp: August 24, 2025, 02:22:10 pm
content: Quote from: Hydron on August 24, 2025, 12:02:31 pmThe top layer pours are mainly there because I didnt remove them, I believe they dont do anything for me here (Negative or positive). Just to be sure that what I have done here is clear, the flap is glued on (To make for ~50µm dielectric thickness) and then the bigger pads are soldered together to connect the two halves. Originally I hadnt done that on the output side but I (attempted to) fix it up as per my previous post which also made no difference. Obviously this isnt as good as if I had been able to just use vias but is it completely useless as suggested by wraper earlier?As for length matching, the spec calls for 5mil intra and 50mil inter pair, in my case I have no more than .5 mil intra and 2mil inter so that should be more than good.Quote from: squadchannel on August 24, 2025, 12:19:44 pmThat indeed looks to be the connector! I dont think I'd be able to use such a breakout cable tho given that its not micro-coax (At least by appearance) nor twisted pairs, probably wouldnt be able to order one singular custom cable either from anyone unfortunately.Edit:Actually I've found a couple of sellers / sources that list a small or no MOQ at all for custom cables, I'll see what they quote. Given that possibility I could get one cable for all 4 possible combinations (Flipped +/- & flipped lane order) and just try those out.Edit2:I've just done some testing that I should've done much sooner, given that this new PCB shows the **exact** same corruption I wasnt positive on it being signal integrity, so using custom resolution utility I've played around a bit and found these things:- Any resolution that tried to negotiate a link above RBR yields a black screen- Any resolution that negotiates at RBR with 4 lanes yields a corrupted image-Any resolution that negotiates to only 1 or 2 lanes yields a black screenEven setting 800x600 @60Hz (1 lane RBR) yields a black screen. Despite having triple-checked all my resources, the last point makes me believe that I literally just flipped the lane order (I have checked that the screen works with <4 lanes on my PC / breakout board). I will try to manually flip lane 3 to 0 and cut the others.Edit3:I was finally able to source the actual pinout of the ATNA60YV02-0 (I have the YV05 but they are equal). Turns out while my aux pair is correct, the polarity and order of my data lines is flipped. Its astonishing this gives any output to begin with, but I suppose this now makes for a third revision of my PCB that then should hopefully work. I will try to manually fix up this one with thin magnet wire but given the tight length matching and signal integrity requirements I dont have a lot of hope for that.Edit4:Well, what can I say. Turns out all along the signal integrity was probably okay enough and the root issue was that I flipped the line order and polarity. Obviously this is almost certainly not even close to spec and the image flickers but its stable enough to say that this was the root issue. Funnily enough I initially had the PCB setup in this lane order & polarity but "fixed" it to be in the (What should be) correct order which is actually wrong.Thanks for all the help from everyone, if anything I learned a lot about high speed signalling