Help! Linear 'Surge Stopper' Oscillating itself to death - Page 1
Forum section: electronics / projects

author: rx8pilot
author_rank: Super Contributor
timestamp: February 02, 2017, 09:26:52 pm
content: Part: Linear LT4356-3 Surge Stopperhttp://cds.linear.com/docs/en/datasheet/43563fb.pdfThis is a controller IC that monitors voltage and current and uses an N-MOSFET to regulate or turn off the circuit in the event a programmed over-voltage or over-current condition exists. I have used this device in another design and did not have any issues. Recently, I laid out a new PCB with this controller. A simple 2 layer design is setup to limit the voltage to 18v and the current to 15A. The expected behavior is that when the voltage rises above the programmed point, it will use the MOSFET as a linear regulator for a short time. If the over-voltage persists past a user defined period of time - it pulls the gate low on the MOSFET to completely turn off the load before the MOSFET heats up and is destroyed.The circuit is simple, but clearly not immune from a layout issue or possibly a bad/damaged component. Testing the over-voltage behavior with no load or very light load appears to work just fine. If the load is above 2A or so when it gets an over voltage event - it oscillates continuously instead of latching off. The stability is worse if the over voltage fault is higher.The scope grabs show:Yellow - output voltagePink - output currentGreen - is the comparator error voltage (TMR pin 1)LT4356_A2 image shows the normal operation. When the yellow output voltage rises above the fault level - the TMR capacitor starts charging. When the TMR gets to 1.35V, the MOSFET is turned off and is not supposed to turn back on without a power cycle of the circuit.LT4356_A1(2) shows abnormal operation after the load current is increased or the incoming voltage is higher. In this shot the load was 2A on an electronic load and the voltage was 30v. This is far less than the 15A the over-current is set for and about 12v over the voltage fault level of 18v. You can see the error amplifier is oscillating.I have tried a number of changes, gate resistor, TMR capacitor, swapped components, and a few other things. There are not many components to check.Anyone want to take a stab at this one? Scratching my head at the moment.

author: Marco
author_rank: Super Contributor
timestamp: February 02, 2017, 09:41:45 pm
content: That schematic is making my brain oscillate, output in the middle, the "high side" power supply transistor on the bottom, all the decoupling capacitors sideways. Escheresque.

author: rx8pilot
author_rank: Super Contributor
timestamp: February 02, 2017, 09:57:11 pm
content: Quote from: Marco on February 02, 2017, 09:41:45 pmI expected some crap for all of that - I was in a hurry, working out of town on a laptop over VNC and did not have a requirement to share with anyone. Time is money, and I did not want to waste it on vanity that offers nothing in return.Now that I am asking for help, all that is out the window. Hopefully the rest of the audience can get past that.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 02, 2017, 09:58:21 pm
content: If the chip is working as a linear regulator, it might have a problem with too much low ESR capacitance at the output. This is something linear regulators usually don't like. In addition a SMPS might look like a negative and thus unstable load impedance - so even a perfectly stable voltage regulator can turn oscillator.It might help to a some output capacitance with sizable ESR (e.g. electrolytic).It could also be important to have capacitance at the input side too. At least normal linear regulators do not like to have no input decoupling - an old rule of thumb even wants at least as much decoupling before than behind.The transconductance of the FET goes up with the current. So it makes sense the circuit is more prone to oscillation at higher currents.

author: rx8pilot
author_rank: Super Contributor
timestamp: February 02, 2017, 10:51:25 pm
content: Quote from: Kleinstein on February 02, 2017, 09:58:21 pmExcellent points, thank you.I can try to remove the caps and place 1-2 electrolytics for a test. The space where this is going to be installed is too small for bag caps which is why I put the bank of 10uf MLCC's in there. Although the schematic is hard to read - there are 3x input decoupling caps C25, C30, and C31 with not-so-great placement on the PCB. I have another design with this same controller and the same schematic. It seems to work as expected but the layout is considerably different - 4 layer PCB and the caps are split on both sides. Maybe the slight alteration of the ESR from the layout itself is enough to de-stabilize it when it trys to go into the linear regulator mode.Going to the bench to re-configure the caps to see if it changes anything. Thank you for the notes, really appreciated.

author: rx8pilot
author_rank: Super Contributor
timestamp: February 02, 2017, 11:38:02 pm
content: The caps came off and clearly make the difference. Added 3x of the MLCC 10uf caps to the input for a total of 6x, but not sure that makes much of an impact.In the scope grab, you can see the BLUE trace is the input voltage rising past the fault level up to 30v. When it does, the YELLOW output voltage is seen regulated at 18v for a period of time. The GREEN trace is the input to the error amplifier rising to its error threshold at which point the the MOSFET is turned off completely. This was done with a 3A load.I had pulled 3 caps at a time and tested each time with oscillations. It was not until I removed all the caps that is worked as seen here. Not sure how to get any output caps on the PCB since space is so restricted.Going to do some higher current tests now. The primary goal of the tests was to try to ensure the SOA requirements are being met at max current/voltage faults but I got hung up with the oscillation. Thanks!EDIT:The higher currents seem to work well, but the lower current <2A has the same oscillation issue.EDIT_2:Added a 100uf electrolytic from the spare parts box, not sure what ESR it is. The circuit seems to be stable under the full range of voltages and currents. I am not sure how to mathematically arrive at the ideal capacitor, so this is a guess based on experiments.The end result is pretty cool. It can deal with substantial voltage spikes while the load continues to operate. If the spike lasts too long it will shutdown. A pre-fault signal is sent to the microcontroller allowing it to gracefully prepare for shutdown too. Adding another MOSFET provides reverse polarity protection if needed.

author: Andy Watson
author_rank: Super Contributor
timestamp: February 03, 2017, 01:16:10 am
content: Quote from: rx8pilot on February 02, 2017, 09:57:11 pmI admire your optimismYour schematic has the gate resistor, R24, with a value is 0 (at least that's what it looks line on my browser) - is this correct?

author: rx8pilot
author_rank: Super Contributor
timestamp: February 03, 2017, 01:34:58 am
content: Quote from: Andy Watson on February 03, 2017, 01:16:10 amYes, that was there just to have the option of altering the gate charge speed if needed. It also makes an easier probe point.With a 0 Ohm resistor, there is no ringing, over-shoot, under-shoot at all so I just left it alone. The gate driver in the IC seems to have good control. The MOSFET is and extremely low Rds(ON) at .4 mOhms (point 4!) That comes with a big gate capacitance with relatively high ESR so it is already fairly slow to charge and discharge.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 03, 2017, 01:49:44 am
content: Quote from: rx8pilot on February 03, 2017, 01:34:58 amAnd you're wondering why it's oscillating?There is ALWAYS such a thing as "too big". It's a commonly committed offense in both linear and switching circuits.Tim

author: rx8pilot
author_rank: Super Contributor
timestamp: February 03, 2017, 01:52:14 am
content: What do you mean? The low Rds(on) value? Or the resulting big gate capacitance?Sent from my horrible mobile....

author: Andy Watson
author_rank: Super Contributor
timestamp: February 03, 2017, 01:53:06 am
content: Quote from: rx8pilot on February 03, 2017, 01:34:58 amAre you sure ? The gate resistor is useful to spoil the Q of the potentially oscillatory circuit of the fet and its lead inductance. If it is even slightly unstable your driver IC is going to be struggling to control it in the linear mode. Since you claim that the gate resistor has an insignificant effect, would it hurt to test, say, a 10 ohms gate resistor ?

author: rx8pilot
author_rank: Super Contributor
timestamp: February 03, 2017, 02:03:02 am
content: Quote from: Andy Watson on February 03, 2017, 01:53:06 amI did try a few values up to 91 Ohms starting with 10 ohms and did not see a noticeable change in behavior. I put the 0 back in as I looked at the other areas. One of the things I was worried about is a slow turn off that could push the MOSFET outside the SOA. I still have not got to the point where I can look at the SOA to make sure it can tolerate faults on a regular basis.

author: chrisbrown
author_rank: Contributor
timestamp: February 03, 2017, 02:19:39 am
content: Does anything change if you remove or drastically lower C24? I don't think you want such a slow filter on your SNS feedback.

author: rx8pilot
author_rank: Super Contributor
timestamp: February 03, 2017, 02:22:31 am
content: Quote from: chrisbrown on February 03, 2017, 02:19:39 amThat was the first change - I took it out completely and found it to be more unstable. I anticipated it would need a lower value, but have not yet experimented much with it.That is another component I put in as an option - not sure if it would be needed.EDIT: Correction - I thought C24 was the FB network filter - I just glanced at the schematic and realized you were talking about the current sense.The intention of this capacitor is to allow inrush current delay with some capacitive loads. This avoids false trip from over-current. I wanted to respond relatively quick to over-voltage and somewhat slow for over current.

author: chrisbrown
author_rank: Contributor
timestamp: February 03, 2017, 03:47:34 am
content: See what happens if you replace it with a wire. If the SNS pin only controlled the fault timer you could probably make it work the way you intended, but it also controls the FET's gate so you are also delaying the current control feedback and I suspect that's causing the oscillation.

author: rx8pilot
author_rank: Super Contributor
timestamp: February 03, 2017, 06:17:46 am
content: Quote from: chrisbrown on February 03, 2017, 03:47:34 amThe fault mode being tested at this stage is the over-voltage so the SNS pin is not doing anything at the moment. The OV fault is being detected by the FB pin that triggers the part to go into the linear regulation mode.The circuit is presently setup with a current fault threshold of 15A which is exactly what my HP 6653A PSU can deliver. Tomorrow I will parallel another 6653A to get a single 30A supply and that will allow me to do over current tests.After looking at the notes on values I changed, I wanted to down to what was actually contributing to the solution. I put all the original values back into the circuit including all the MLCC output caps. It oscillated as expected. I only added the the 100uf electrolytic cap on the output ( in parallel to the existing 10x 10uf MLCC's and it appears to work as expected. I did an OV test by delivering 35V and it handled the fault properly at any current up to what my electronic load could handle. I was a little surprised that the add of the cap and leaving the MLCC's made all the difference. The gate resistor stayed zero - the gate exhibits no ringing or other issues. The fall time is reasonably quick to avoid an SOA violation when it is under a 15A load. When the part goes into its linear regulation mode, there is no overshoot and the timing is nice and consistent.This will allow me to adjust the timing to accommodate the SOA of the MOSFET and get the most time allowable for an OV spike to dissipate. I can slowly test at higher and higher currents to make sure the MOSFET can deal with repeated faults.The vast majority of the time, the FET will only see DC and the ulta-low Rds(on) is fantastic. At 15A it is dissipating 90mw and dropping 6mv. Clearly, no thermal management is needed. The only stress it sees is die limited since it is far too fast to make use of a heat sink.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 03, 2017, 10:51:47 am
content: There still is capacitor in the FB network (C27). It is not in the DS circuit.Form linear power supplies I would more expect an RC combination to speed up the other direction for a certain frequency range. So C27 could cause quite some trouble.

author: DutchGert
author_rank: Frequent Contributor
timestamp: February 03, 2017, 03:23:33 pm
content: Quote from: rx8pilot on February 02, 2017, 09:57:11 pmSpending 2% more time on making a schematic more readable has nothing to do with vanity...... And if you want people to help you or want to know what the circuit does 6 months from now its absolutely necessary......Your timer capacitor seems a bit low but then again i only used the LT4363 variant of it

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: February 03, 2017, 03:57:05 pm
content: Hi,There are lot of differences between the circuit you have and the circuit used on the Linear Demo board and schematic shown on the datasheet.The demo board does not have a filter on the SNS pin.The demo board does not have a filter capacitor on the bottom of the FB divider.The demo board does have a 10 Ohm resistor on the gate of the MOSFET.I would try and get you circuit closer to the demo board schematic.Regards,Jay_Diddy_B

author: Andy Watson
author_rank: Super Contributor
timestamp: February 03, 2017, 04:10:04 pm
content: Quote from: rx8pilot on February 03, 2017, 02:22:31 amHave you re-visited C24 - i.e. the current feedback network? The time constant (220 x 10µF) is suspiciously in the same ball park as the frequency of oscillation that you have shown. Can you test it with the current feedback disabled (without releasing the magic smoke)? - This would eliminate one possible source of problems.

author: rx8pilot
author_rank: Super Contributor
timestamp: February 03, 2017, 05:47:45 pm
content: Quote from: DutchGert on February 03, 2017, 03:23:33 pmI will agree with you on the point of including others for help and decoding the circuit myself down the road. I do have a bad habit of conceptualizing various circuits where the end solution is wildly different from where I started. After a few waves of halfway starting over and discovering new ways to accomplish the end goal - it is a mess. At that point, I am usually needing to get on with the layout to make the schedule work. Once the layout starts, it makes a total reconfigure of the schematic much more difficult. All that on top of the fact that I am not very good at drawing schematics under the best circumstances. Considering that, it is probably a bit more than a 2% increase in effort - for me at least. For this type of discussion or any other outside help, it is clearly worth working to improve my skills in that area.Quote from: Jay_Diddy_B on February 03, 2017, 03:57:05 pmThank you for taking a look at this. There are indeed some deviations, but they at least have been considered.The filter on the SNS pin was one that I worked out with LTspice and a few conversations with my local LT FA Engineer. The purpose of that filter is to slow the over-current response of the circuit to allow large inrush currents expected from the loads. If that filter is removed, it will falsely trigger the overcurrent and shut down every time the load is powered up or plugged in. The SNS input is only to trigger the fault response where the controller starts charging the TMR cap and totally shuts down the MOSFET when it reaches 1.35V. Most of the testing where the circuit was failing was done without this filter in place. It had no impact because the current sense was not triggering the fault response, but rather an over-voltage on the FB pin. The application essentially needs a fast response to over voltage and a sluggish response to over current. On this part, the timing of both faults is controlled by a single TMR capacitor. Over current events charge that cap much faster too, making even small current spikes enough to shut the MOSFET off.The filter on the FB divider was a 'just in case' placement. The thinking behind this one is that the circuit will be operated in a noisy environment and fairly close to the over-voltage threshold. I did not want noise to cause the part to falsely switch into linear regulation mode. This pin is also the feedback for when the part goes from fully on to linear regulation - at that point a filter can be a problem. I am experimenting with values to see what may offer some noise immunity while allowing the feedback loop to remain stable. It only has to be in linear regulation mode for 5-15ms before it will shut off completely. If it is gong in-out of linear mode because of noise, the FET could heat up which is what I was trying to avoid. It seems to be stable with the 1000pf in place - but only when the output has an electrolytic 100uf cap. Not sure if that is offering much in the way of noise immunity. Still trying to figure out how to test that. The real world use will be close proximity to commercial walkie-talkie's, servo motors, high-current AC switches, etc. Some of that can be handled with the enclosure and ferrite beads of course. I kind of wish there was a separate pin for OV sense from the feedback loop of the linear regulation.The gate of the MOSFET has a 0 ohm resistor. That was again placed as a 'just in case' part which also serves as an easy way to probe the gate. It may add a bit of inductance, but the gate driver is not fast enough to make that an issue.Overall, the only real change is the current sense filter - but like I said even that was removed during the tests trying to sort out the oscillation. At the moment, the SNS filter is removed, the FB divider filter is removed, the gate resistor is 0 ohms, and the 10x 10uf MLCC's are in place on the output. It oscillates every time an over-voltage fault puts it into linear regulation mode. Adding the 100uf electrolytic in parallel on the output, it never oscillates. Not sure why that is yet, but at least that is very repeatable observation.Hopefully my datasheet deviations make sense. I knew that they are all easy to disable by simply removing parts or changing values - so worth a try to get what I wanted out of the circuit.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 03, 2017, 06:07:20 pm
content: A linear voltage regulator circuit quite often behaves like a more or less ideal inductor over quite a frequency range. Together with a low loss capacitor at the output, this makes a low damping resonator. It just takes a minute extra phase shift to make it oscillate.The extra electrolytic cap (with some ESR) adds damping to the resonator and thus can reduce ringing or stop oscillation.

author: rx8pilot
author_rank: Super Contributor
timestamp: February 03, 2017, 06:31:05 pm
content: Quote from: Kleinstein on February 03, 2017, 06:07:20 pmBased on what I see - that makes sense. I am going to try this in simulation as well to see what happens. I can also sweep through some values on the FB filter to see if I can get some pre-fault noise immunity without collapsing the feedback loop.

author: rx8pilot
author_rank: Super Contributor
timestamp: February 03, 2017, 07:52:33 pm
content: Just read this app note from TI - what timing.http://www.ti.com/lit/wp/snoa842/snoa842.pdf

author: rx8pilot
author_rank: Super Contributor
timestamp: February 08, 2017, 06:53:45 pm
content: I needed to put this circuit into a new PCB layout, so I decided to clean up the schematic. Not exactly award winning, but a big step up from the random/scratchpad look at the previous in the first post.

author: Andy Watson
author_rank: Super Contributor
timestamp: February 08, 2017, 07:14:33 pm
content: Isn't C15 now coupling any noise on your input directly into the current sense amplifier?

author: rx8pilot
author_rank: Super Contributor
timestamp: February 08, 2017, 07:38:44 pm
content: Quote from: Andy Watson on February 08, 2017, 07:14:33 pmYou are correct, it should be like this. The value is still TBD, but the functional intent is to delay the current sense to allow transients to pass. Thank you for noticing that.