Why is there three capacitors across the power rails in Ardunio? - Page 1
Forum section: electronics / beginners

author: abdullahseba
author_rank: Frequent Contributor
timestamp: April 10, 2017, 10:15:08 am
content: HiProbably a noob question but what is the purpose of these caps?Thanks in advance.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 10, 2017, 10:25:34 am
content: Because two would be too few, and four would be too many?I haven't looked at the PCB but I suspect two of these are decoupling capacitors, which stop high-frequency noise from the ICs getting onto the power rails where it can upset other chips. At AVR speeds they are placed as close to the power pins of the chips. You can look at them a a couple of different ways- They act as a local reservoir of power, giving the chip extra power when it needs it most, with out needing to suck it all the way from the source- They act as a high-pass filter, allowing the noise to pass through to ground rather than running all the way to the power supplyBoth points of view are about as valid as each other.I suspect the 4.7uF one is the output filter on the voltage regulator.EDIT: Arduino schematics I just looked at have 0.1uf for decoupling - your 1.0uF caps are not the normal value (not saying they are wrong, just that a lot of other boards use 0.1uF)

author: Avacee
author_rank: Unknown
timestamp: April 10, 2017, 11:03:36 am
content: Some further info for the OP, Dave's done an video on Bypass Capacitors and how different ones filter different frequencies.Further watching on why they're in parallel.

author: David Hess
author_rank: Super Contributor
timestamp: April 10, 2017, 06:55:04 pm
content: C5 is a bulk (low frequency) decoupling capacitor which will normally be located at the output of the regulator or where regulated power enters the printed circuit board.The other two small value capacitors are for local decoupling and will be located close to the circuits they decouple. At high frequencies if they were located further away, the inductance of the traces would defeat their purpose. I actually have fun doing the analysis to calculate how large the high frequency decoupling capacitors need to be but most designs just brute force them with 0.01 or 0.1 uF values.I hate when schematics are divorced from the layout requirements. It is not unheard of for the layout to be done without realizing that the decoupling capacitors have specific location requirements so they all get put together. The layout requirements should be shown or at least implied in the schematic. This problem also shows up with ground loops in switching regulators and mixed signal designs. And a solid ground plane does not always solve this.I saw one design where someone (Bean counter? Manager?) saw the single 10uF bulk decoupling capacitor next to a pair of 0.1uF high frequency decoupling capacitors and had the schematic changed to a single 10.2uF capacitor. Unfortunately the purchasing manager did not question this in time and the boards were made before anybody noticed the problem.

author: james_s
author_rank: Super Contributor
timestamp: April 10, 2017, 06:59:46 pm
content: I usually group all the decoupling capacitors together on the schematic, it's just common sense that each IC gets a decoupling cap, well, it ought to be common sense anyway. I can get away with it at least because I'm doing both the schematic and the layout of my own boards.

author: David Hess
author_rank: Super Contributor
timestamp: April 10, 2017, 09:00:46 pm
content: Quote from: james_s on April 10, 2017, 06:59:46 pmI have seen it done in several different ways:1. Put the decoupling capacitors and power connections into the schematic showing their relationship. This is problematical when you have multiple functions in one package like dual/quad operational amplifiers and separate gates but in some cases it still works if the parts are numbered well. This is the only way to do it if you are using the supply pins for other purposes and want someone else or even yourself to understand what is going on. (1) It is also important for understanding return currents. High performance mixed signal circuits especially need to be drawn this way but it also applies to the lowest jitter digital circuits where the power supply layout determines performance.2. Show the power *and* decoupling based on package instead of function in a separate part of the schematic. I really like this method as an alternative to #1 although less so when a separate page is used but sometimes it is the best way.3. Group all of the decoupling capacitors with no relationship to the packages or functions. I hate this. It works when the same person lays out the schematic and board but it encourages layout errors and even worse, it conceals the power supply return currents leading to errors in the schematic even before the layout is done. Digital designs do not need to worry about this (except low jitter designs) but it leads to complacency. (2)I also tend to mark passive parts on the schematic for type; MF=metal film, CF=carbon film, WW=wirewround, Z5U, X7R, PP, PET, Al, Ta, etc. but I am used to mixed signal designs where this can be important.(1) Operational amplifier power pins can be used as output pins with the normal output being used as a third current mode input. What if you bootstrap an IC? I have also seen this done with CMOS inverters to make high performance synchronous rectifiers with the outputs being the inputs and the supply pins being the outputs.(2) I see this kind of thing often on EEVBlog where someone has a switching regulator that does not work and supplies a schematic which shows nothing about the layout restrictions; they fooled themselves into thinking the layout did not matter when in reality it was critical. You see it done properly in some Linear Technology schematics where they show Kelvin and single point connections and distinguish power and signal connections. Why bother if it is common sense? Because it is not.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 10, 2017, 09:57:25 pm
content: Quote from: David Hess on April 10, 2017, 09:00:46 pmThis is worthy of a post - with sketch schematics- I think I can draw out what is being suggested, but is seems like such an interesting "off label use" of these parts that would be fun to investigate.

author: w2aew
author_rank: Super Contributor
timestamp: April 11, 2017, 04:11:51 pm
content: Lots of good info presented already.My latest video demonstrates some of the reasons that multiple capacitors (of different types) are used, and why it is important to understand why their placement is important:

author: rdl
author_rank: Super Contributor
timestamp: April 11, 2017, 09:46:15 pm
content: Quote from: David Hess on April 10, 2017, 06:55:04 pmI don't like to see this done either. To me it just seems to add an unnecessary layer of confusion. It's maybe okay in a company environment where everyone is familiar with the device in question, or in a situation where the circuit designer is also the one doing the layout, but if the schematic is to be distributed publicly and used by others it would be better if the schematic resembled the layout as much as reasonable. If all the decoupling and filter capacitors are going to be dragged off to some corner of the schematic and placed in a cozy little group, at least add a note for each that indicates where it should actually be located on the board.

author: Len
author_rank: Frequent Contributor
timestamp: April 12, 2017, 09:52:09 pm
content: Quote from: rdl on April 11, 2017, 09:46:15 pmYes, please. I've seen schematics where the number of decoupling caps off in the corner is different from the number of ICs so you have to guess where they're supposed to go.