Why do they have to make it so difficult to use their products? - Page 1
Forum section: electronics / general

author: tom66
author_rank: Super Contributor
timestamp: October 20, 2012, 05:05:12 pm
content: I want to play around with Xilinx and Altera FPGAs so I'm downloading their tools. I'm a CPLD/FPGA noob - and wanting to get some experience.First off... 6 frigging gigabytes? Each? How the hell do they make them so big!?OK, so I finished the download of the Xilinx software overnight (luckily the university network is reasonably fast here.) Launch it. 30 day free trial. I don't understand why they want the average user to pay for it -- after all, they will be buying hundreds, if not thousands of their FPGAs, if it is found to be useful and easy software to use -- so why make me make a significant upfront investment? After licensing it (for the webPACK edition - with no clear explanation of the differences) I have to jump through several hoops and still haven't found an easy "enter VHDL here" and "click to make the file you need" button. There's options for loading IP cores, which I guess you have to pay for, but no easy way that I can see to enter code. Oh, there is a C compiler. I don't know why you would put C on an FPGA? It's not an easily paralleled language, or is it modified for FPGAs?What am I missing??I'm trying the Altera software now, the installer is eating up 100% of my dual core machine, I will see how this compares to Xilinx stuff.Any easy getting started guides written for people who just want to use a HDL?

author: free_electron
author_rank: Super Contributor
timestamp: October 20, 2012, 06:16:31 pm
content: licences are free. you get 30 days of the FULL tool. after that it falls back to a -base- tool . no support for the large devices, incremental compilation turned off , advanced optimizer turned off , ip cores stop working etc etc ... still perfectly usable for small to medium designs. ( when i say medium : you can still do a mulitliion gate design in a 484 pins bga without problems. just the 1500 ball devices are disabled. )6 gigabytes. yes. becasue this tool supports ALL the devices they have. and the toolchain is enormous. these are not toys ... serious software has a serious footprintfile -> new project , follow the wizard.file -> new sourcefile -> select verilog or vhdl ->start typingon the risk of opening a huge can of worms : go for Verilog (most notably V2005 standard) and forget 'Very Hard Design Languge'.There is simply too much 'overhead and typing involved in VHDL. Productivity in Verilog is an order of magnitude higher and for the FPGA or synthesizer it doesn't matter. You can always learn VHDL later. it's just a matter of syntax ( which involves a lot morekeystrokes to do the same in Verilog, simply becasue of the more 'strict' stuff. VHDL comes from the military, Verilog comes from people that want a tool to make designing chips easier. Here's the 'dirty laundry on VHDL' : VHDL or short for VHSIC HDL is a 'bolt-on' to HDL. The military commisioned a Hardware description language that could describe ANYTHING, whether mechanical , electrical , even a paper document could be described in it. think of it as a sort of XML. someone made a 'descritpio' of what a logic one and a logic zero is. and then went on describing the gates and other logical constructions using this language. All that stuff was slapped into a library ( two actually ) and that is how you can use the HDL to do logic work . without those libraries the HDL has no concept of logic high low , undefined or anything else ... Needless to say is that , using a generic language with bolt-ons requires a bit more work to get anything done. think of it as having to make a webpage using <html> tags. that is what coding in VHDL involves.Verilog on the other hand was designed form the get-go to do logic and ONLY logic. you define logic and that's it. no need to add all the 'curly' bits.VHDL has evolved ofver the years and some of the 'rough spots' have been removed but it is till bloody annoying not to be able to use generated signals back to read form without intermediaries , having the devine both a process and entitiy description and having the have for every block half a page of 'boilerplate bullshit' to get it to do anything. i don't like keyboard pounding, i want to write the logic.anyway, all a matter of perspective. but to begin : verilog is syntactically easier and involves less keyboard pounding.second : you are writing LOGIC , NOT CODE ! this is key difference between a sequenced system like a processor where one instruction happens after another. and a block of logic where every block executes at the tick of a clock.Now, to make life easier you need to understand how a synthesizer works. this is something that 99.99% of the textbooks on VHDL and Verilog skip and it is absolutely important that you know this little bit as it makes life so much easier.How do you translate a list of instructions ( which is our description of the logic ) into a parallel operating engine ? where is the 'magic' ?the magic is simple.you begin at the top where you find the definition of input and output and registers and you plunk those down.and then you evaluat the first line of source. and you put down some wires and some gates, and then you read the next line and you cut some wires and throw in some more stuff and add some wires , and you keep doing that. and you grow TOWARDS the output. Meaning that :a statement that is LATER on your page sits CLOSER to the output than e previous statement.an example:a counter with reset , preset , load , updown and enable. I'm using a 'hypothetical synthesis language without any 'curly' bits to make reading easiersignal names are CAPITALCode:always @ CLOCK beginif RESET then OUTPUT =0elseif ENABLE thenif LOAD then OUTPUT = INPUTelseif PRESET then OUTPUT = 9elseif UPDOWN then OUTPUT = OUTPUT +1else OUTPUT = OUTPUT -1end ifend fiend ifend ifend ifabove is the 'traditional way of coding done by someone who has no idea how a synthesizer works. a pile of if-then-else spaghetti. if they tell you preset needs priority over clear, or clearing can only work when enable , but preset can work without being enabled you have to dig in and see what you need to chunk around and mess with things...here is how you write this stuff 'scheduled'Code:always @ CLOCK beginif ENABLE then beginif UPDOWN then OUTPUT = OUTPUT +1else OUTPUT = OUTPUT -1end ifif LOAD then OUTPUT = INPUTif PRESET then OUTPUT = 9end beginif RESET then OUTPUT =0so how does this work ?well i look at enable first. if the counter is not enabled , i do nothingif a reset occurs : i wipe the counter.if both were to happen at the same time : reset will take priority as it sits LOWER in the source file and thius CLOSER to the outputif ENABLE is true then we will avaluate UPDOWN and go up or down.if LOAD is active then we will LOAD. since this statement sits closer to the output than the 'if UPDOWN' it takes priority. LOAD will have priority over the act of counting.likewise PRESET has priority over the act of both LOAD and UPDOWN !if someone telly ou that PRESEt has to work even when the counter is not ENABLED you simply cut that single line of code and move it outsde of the block that looks at ENABLE :Code:always @ CLOCK beginif ENABLE then beginif UPDOWN then OUTPUT = OUTPUT +1else OUTPUT = OUTPUT -1end ifif LOAD then OUTPUT = INPUTend beginif PRESET then OUTPUT = 9if RESET then OUTPUT =0done. PRESEt takes priority over whatever happens under control of ENABLE.oh and preset needs priority over reset .. simply swap the last two lines. of and we wanted paralle load also outside of enable but with lowe rpriority than preset : you know the drill by now ...you begin by giving the 'default' operation. when nothing else is in effect : do this...unless ,,, blablabunless blablaunless blalblaunless blabla ...and so on :Code:if enabled thenif updown then +1 else -1end ifunless load then out = inunless preset then out = 9unlesss reset then out =0you are not going to find this in any textbook on Verilog for VHDL unless it is a textbook specifically written for SYNTHESIS. Most textbooks begin with the 'hello world' example. YOU CANNOT SYNTHESIZE THAT INTO LOGIC. you can simulate it , but you cannot drop this in an fpga or on silicon ! and that is boneheaded.The technical name if Scheduled logic and it is partof the offcial Verilog AND VHDL standard. Any synthesizer out there needs to adhere to the rule that 'Logic shall be implemented in the order it is written.' simply because this is how the synthesizing process works. no escaping.You can squash massive blocks of spagetti code to a few simple lines of code if you use the base principle of synthesis. It has an additional advantage : there are no undefined paths that lead to unpredicatbility , and there is no risk of latch inferral unless explicitly defined by you.

author: free_electron
author_rank: Super Contributor
timestamp: October 20, 2012, 06:56:11 pm
content: Quote from: Mechatrommer on October 20, 2012, 06:41:45 pmwhat are you complaining about ?the toolchains are FREE (as in gratis, not as in the utopian 'free' open sauce , grilled chicken flies in your mouth) unless you want ot use the extreme devices ( which cost like 500$ a pop or way beyond that. the largest Stratixes in fastest speedgrade top 4K$ and you don't stand a chance as hobbyist as they have 1500 + balls in bga and need 16 layer boards to route them ).so both the xilinx and altera toolchain are free. yes you need to register ( fill in some stuff on a webpage ) so they can do some statistics on their audience. but yo immedatiely get a licence key to run the software without having to fork over any 'dinero'and xilinx or altera are not going byebye. no matter what you smoke or what you dream. you don't stand a chance entering that market as a new company. in the last couple of years 2 companies have tried:Tabula -> deadBlueLogic -> dead ( absorbed by someone else and slaughtered )and there is not going to be a thrid party compiler for those devicese either. only the manufacturer knows how to translate a netlist , optimize it and convert into a fusemap. that is the secret sauce. xilinx will always need xilinx tools just like altera needs altera tools, lattice needs lattice tools, actel needs actel tools atmel needs atmel tools quicklogic needs quicklogic tools ( are they still around ? ) .you can get various front-ends like Aldec , Altium, Synopsys and plenty of others. simulaotrs like Veritak and Modelsim. but once the synth is done and the bitmpa needs to be made you NEED the manufacturer tools. no escaping. and those are the 6 gig downloads.... simply because there are fitters for each and every device they make.so stop whining, download the file install and go.diskspace , memory and cpu's are cheap. so is bandwidth

author: free_electron
author_rank: Super Contributor
timestamp: October 20, 2012, 07:18:35 pm
content: the reason the download is so massive is that they essentially give the entire tool. it is the licence key that decides what you get to use. you have 30 days of unlimited usage. after that it falls to whatever your licence allows.sure, they could do a stripdown version but building and verifying all the variations is simply more work for them.just like a microsoft office cd holds every office product and it is the key that determines what gets installed.

author: Bored@Work
author_rank: Super Contributor
timestamp: October 20, 2012, 07:39:43 pm
content: VHDL is popular in Europe, Verilog in the US. So if this is for a job, and you accept the fact that the UK is in Europe, sort of, then learning VHDL makes sense.

author: tom66
author_rank: Super Contributor
timestamp: October 20, 2012, 07:40:53 pm
content: I'm open to learning either.Hmm. Installed Altera software. Launched Quartus II. New project. 5 mins later I have compiled my basic 8-bit counter.I used Verilog. I'll use whatever does the job.I'm just playing around with it. HDL is 4th year MEng, so I've got a while before I get to learn it - but getting some experience before hand can't hurt.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: October 20, 2012, 10:59:53 pm
content: Last time I looked, a substantial part of ISE (like 1G+) was device-specific files.It would be really, really easy for them to have a build version that only included the basic low-end devices.However they probably don't consider that customers that have a problem with stupidly large downloads to be serious enough to be worth the effort...

author: free_electron
author_rank: Super Contributor
timestamp: October 21, 2012, 04:29:24 pm
content: Quote from: Bored@Work on October 20, 2012, 07:39:43 pmkind weird especially since VHDL was ordered by the US military ..anyway it doesn't matter as synthesizers read and use both and the end result is the same.VHDL tends to be more 'verbose' and needs more keyboard pounding , which is why i don't like it.

author: Bored@Work
author_rank: Super Contributor
timestamp: October 21, 2012, 05:27:15 pm
content: Quote from: free_electron on October 21, 2012, 04:29:24 pmI don't know how that happened. In the civilian area VHDL was one of the things that "suddenly" happened. At least that is how I experienced it. People here didn't pay much attention to the development of VHDL, until there "suddenly" where these ASICs available, and VHDL to program them.Maybe it was because of the military. If you wanted to sell to the US DoD you had to use VHDL, and that trickled down into the civilian sector. Also, when one bought advanced weaponry from the US, like fighters, they only came with half the firmware, other parts being a secret. So the buyer had to write their own stuff, probably using the same VHDL tools.

author: nanofrog
author_rank: Super Contributor
timestamp: October 21, 2012, 06:17:29 pm
content: Back when I was still in Uni (Orlando, FL), the existence of Verilog was mentioned, but all that was taught was VHDL. Though there was NASA as well as DoD contractors in the area, so that may have been the reasoning behind it.

author: ftransform
author_rank: Frequent Contributor
timestamp: October 21, 2012, 07:50:43 pm
content: do not give in to the code monkey!!!!!!!!!!!!!!!!!!

author: perfect_disturbance
author_rank: Regular Contributor
timestamp: October 22, 2012, 12:09:59 am
content: Ok so I don't know anything fpga's etc but as a software engineer 6 gigs is huge for any piece of software that doesn't have loads of audio video stuff. A whole windows install is 6 gigs. Windows isn't exactly a lean piece of software. I can install a Linux box with a webserver, Oracle, and eclipse ( oracle and eclipse both being renown for their fatty ness) in under 6 gigs. So I like I said 6 gigs is a pretty big program regardless.

author: digsys
author_rank: Unknown
timestamp: October 22, 2012, 02:38:06 am
content: Since the first PALs, Alteras EPLDs, then all the bigger Altera / Xilink FPGA / CPLDs we've always used schematic entry.They've often tried to move us off to the "fancier" packages, but we like and prefer SE !! Not sure if the newer IDEsstill support SE, since we gave away using programmable logic. Too much power, always glitchy and temperamental.Even made a school development kit for them once.

author: joelby
author_rank: Frequent Contributor
timestamp: October 22, 2012, 02:41:17 am
content: Schematic entry is still supported, but it can be a little quirky. I don't think many professional designers would ever consider using it when HDL is generally so much more concise and maintainable.

author: westfw
author_rank: Super Contributor
timestamp: October 22, 2012, 07:32:32 am
content: I think what happens is that you get a pretty verbose "device description file" that describes each pin and perhaps each internal gate, for every possible chip. Probably in something wordy, like XML.For instance, if you install Microchips PIC32 C compiler, you end up with about 50MB of include/proc files, one for each chip, with each file being between 500k and 1.8MB. Pretty inefficient, but also pretty easy to machine-generate in an "almost certainly correct" fashion.

author: AndyC_772
author_rank: Super Contributor
timestamp: October 22, 2012, 07:37:40 am
content: Quote from: perfect_disturbance on October 22, 2012, 12:09:59 amIt's crazy. Altera's software used to fit on a single CD, but then a few years ago they gave it a major overhaul: they rebuilt the Windows product based on their own Linux version, and at the same time, the code became enormously bloated. They also removed the extremely useful built-in simulator, so now it's ModelSim or nothing.Every time they release a new update, I get the dubious pleasure of being "the guy who's eating all the bandwidth" on our office network for half a day. Oh joy, what fun.

author: deephaven
author_rank: Frequent Contributor
timestamp: October 22, 2012, 08:00:15 am
content: Quote from: AndyC_772 on October 22, 2012, 07:37:40 amThat's why I'm stuck on Quartus 9.1, that simulator is so easy to use. ModelSim does my head in!

author: andersm
author_rank: Super Contributor
timestamp: October 22, 2012, 10:10:51 am
content: Quote from: joelby on October 22, 2012, 02:41:17 amI don't know if it's fixed in the latest versions, but in ISE 11-12 or so schematic entry was seriously broken (at least for CPLDs). Overall Xilinx seems to have the policy of letting their tools bit-rot rather than maintaining them, so you're almost forced to figure out the "best" release for whatever chip you're using and hold on to that until the end of time. Now that they've introduced their new "Vivado" design software I'm guessing that's it for ISE, and if there's some critical bugs there well too bad (which seems to be Xilinx' general attitude towards their customers if you're not in the million- to billion-dollar class).Quote from: AndyC_772 on October 22, 2012, 07:37:40 amBut the Quartus installer is still only a third the size of ISE's, and is not distributed as an uncompressed TAR archive on Windows (seriously, what's up with that?) And to download the Web Edition you only have to enter a random email address into a field and click the button, none of that mandatory-registration-with-address-and-phone-number-validation with added license files crap that Xilinx forces you through.