Linear Adjustable Load; Two Op-Amps vs One Op-Amp? - Page 1
Forum section: electronics / beginners

author: LooseJunkHater
author_rank: Frequent Contributor
timestamp: April 04, 2025, 03:04:25 pm
content: Probably a simple question, but I recently came across this video,where a linear power supply was made usingtwo op-amps(simulatedhere in Falstad; one op-amp for current-sensing, the other for driving the FET/BJT), while most designs I've seen only usedone op-amp(simulatedhere in Falstad; the op-amp does the current-sensing + FET/BJT driving)._____________________________________________________________________________What would be the advantage/disadvantage of one circuit design vs the other? Would one-design be better suited for certain op-amps vs others?Thanks!

author: Kleinstein
author_rank: Super Contributor
timestamp: April 04, 2025, 03:16:02 pm
content: The 2 OP-amp circuit could be a little faster, but is also prone to oscillation. One could fix this with additional capacitive FB and related modifications.It may have a slight advantage when multiple channels in parallel are used as it can get independent 4 wire sense at the resistor.It would be better to use the 1 OP-amp version and include the stabilization against oscillation with difficult (e.g. inductive) sources.

author: LooseJunkHater
author_rank: Frequent Contributor
timestamp: April 04, 2025, 03:31:01 pm
content: Quote from: Kleinstein on April 04, 2025, 03:16:02 pmCan you elaborate on what you mean by this, in regards to the dual op-amp config?

author: Kleinstein
author_rank: Super Contributor
timestamp: April 04, 2025, 03:57:38 pm
content: With just one channel one can still get correct 4 wire sensing for the current setting resistor. It still need some care on where to connect the ground side of the DUT / external voltage source. It should be directly from the current setting resistor.With more channels in parallel, like to get higher power, it is no longer to get correct 4 wire sensing for multiple channels so easy. With the 1 OP per channel circuit some of the trace / wire resistance will likely be included with the resistor. With the 2nd OP-amp circuit, the extra amplfifier acts as a differential amplifier and can get correct 4 wire connection, even with the low sides not ideally connected.

author: BillyO
author_rank: Super Contributor
timestamp: April 04, 2025, 05:10:52 pm
content: Quote from: LooseJunkHater on April 04, 2025, 03:04:25 pmIt's not actually a power supply, but a power sink - or load.I personally don't like what he did here. The offset in the op-amps could mean the mosfet is fully turned on when a voltage source is applied. If the current capability of that source is sufficient it could easily end the MOSFET. I preferer to use single op-amps per channel that have offset null and split supplies to make sure this won't happen. I also think the differential sense amplifier is unnecessary and a potential source for instability.

author: LooseJunkHater
author_rank: Frequent Contributor
timestamp: April 04, 2025, 05:22:13 pm
content: Quote from: BillyO on April 04, 2025, 05:10:52 pmAside from using aMCUto keep the FET non-conductive until ready & then ramp-up current, is there ananalogmeans to slowly ramp-up the current to the desired value, but otherwise, keep the FET non-conducting?

author: BillyO
author_rank: Super Contributor
timestamp: April 04, 2025, 05:57:11 pm
content: Quote from: LooseJunkHater on April 04, 2025, 05:22:13 pmI'm not suggesting an MCU. Just use an op-amp like a lowly LM741 or a TL081 that has an offset null capability, power it from a split supply and adjust the offset to make sure the gate of the MOSFET receives 0v when the load is powered up and turned all the way down, but with no test voltage applied.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 04, 2025, 06:11:14 pm
content: Quote from: LooseJunkHater on April 04, 2025, 05:22:13 pmThere is a way to limit the ramp up when no voltage is applied. A good idea is combining the current regulation with a constant resistance limit. So the effective resistance gets limited by limiting the set voltage for the current to a fraction of the voltage at the drain. This way zero voltage leads to a zero set point. A suitable offset can make sure that the current regulator turns off with zero set point.

author: Zero999
author_rank: Super Contributor
timestamp: April 04, 2025, 08:14:33 pm
content: Sorry, I don't like this video. At no point is the entire circuit in frame and lots of waffle.Here's the schematic, to save others the trouble of watching it.Why have all of that gain?Add a potential divider to the input and use one op-amp.

author: LooseJunkHater
author_rank: Frequent Contributor
timestamp: April 05, 2025, 09:56:44 pm
content: Quote from: Kleinstein on April 04, 2025, 06:11:14 pmHmm, for the "constant resistance limit", wouldn't that still mean that the FET gate is always partially-conductive, instead of being non-conductive? Maybe if you provided a reference for your common or a schematic, I would understand it better?I was also thinking that maybe I could have an additional op-amp detecting when a voltage is applied to the circuit, at which point the FET will be allowed to become partially-conductive until it reaches the desired current? However, I then wonder if this will somehow create an oscillation between the load being conducting-nonconducting? I then also wonder if I'll need to incorporate a latching circuit?

author: Kleinstein
author_rank: Super Contributor
timestamp: April 06, 2025, 09:26:30 am
content: Using just the drain voltage to hard switch between active and off can lead to oscillation if there is a weak current source as DUT (external voltage source).The idea of limiting the resistance is to enable the load slowly. So if the voltage is low the maximum current is limited to a small amount roughly proportional to the voltage. This reduces the chances to get oscillation. A current proportional to the voltage would be resistive load. So the circuit would emulate a resistive load. If wanted one could also adjust the simulated resistance to higher values, than just the lowe limit.The cross over is a little like with lab supplies that have a constant voltage and constant current mode and switch over when either limit is exceeded.For the electronic load the logic version is constant current or constant resistance. To make sure that the FET would turn off when no voltage is applied a small offset would help - so some minimum voltage (a few mV) for the current to flow at all and it would not be a perfect resistance emulation.The point of avoiding the FETs to turn on all the way when there is no external voltage is already a bit advanced. It looks like many commercial loads don't have this. They rely on the user to only turn the load active after the voltage is applied, with maybe a latching protection against user error.The way to solve this by a lower resistance limit would be an advanced solution, though no overly complicated. A possible constant resistance mode would be an extra.

author: Vovk_Z
author_rank: Super Contributor
timestamp: April 06, 2025, 09:49:04 am
content: I use a comparator with quite low voltage threshold to get rid of this parasitic short-circuit effect. With some small amount of a positive feedback for trigger effect of cause. Suggested theshold is somewhere near 0.4-1.0 V. It can be fine for most designs (I work with 5-250 VDC supplies), and may be set lower for low-voltage ones.

author: Zero999
author_rank: Super Contributor
timestamp: April 06, 2025, 12:29:29 pm
content: The calculation in the video is wrong. The current with a 9V reference is 3.9A, not 2A.The amplifier has a gain of 46, not 45.AV= 1 + R3/R2 = 1+45/1 = 1 + 45 = 46The voltage across the sense resistor is divided by 2, by R2 and R3, before it goes to the input of the amplifier, so the voltage across the sense resistor is doubled, because the op-amp keeps both of its inputs at the same voltage.LTSpice simulation. The voltage to the input of the amplifier V(in+) is divided by R2 and R3, making it half of V(sense). Note that I(PSU) is negative because current is being taken away from the PSU.

author: LooseJunkHater
author_rank: Frequent Contributor
timestamp: April 22, 2025, 08:00:48 pm
content: Quote from: Vovk_Z on April 06, 2025, 09:49:04 amSo I decided to simulate a circuit in Falstad, somewhat-based on this comment. Isthiskinda what you did?It seems to eliminate the short-circuit effect upon initial load connection, as well as reduces the risk of a short-circuit effect, if the load is quickly connected-disconnected-connected (as the FET gate would still have some charge after load disconnection).I'm curious how others feel about this circuit? I spent about 3 hours trying to design it in Falstad and get it working smoothly. It's (clearly) based around 2x LM358's, with the 1.3v reference voltage being generated by a TL431.

author: LooseJunkHater
author_rank: Frequent Contributor
timestamp: April 22, 2025, 08:52:24 pm
content: For funsies, I decided to make the circuit into a composite amplifierhere(I think this is correctly designed, to be a composite amplifier?), so that ultra-low offset op-amps can be used for measuring the current flowing through the sense-resistor, with an LM358 being used to actually power Q1.

author: MarkF
author_rank: Super Contributor
timestamp: April 23, 2025, 12:17:57 am
content: I believe the object of having two op-amps is to allow the use of a small value sensor resistor. The low voltage drop across a small sense resistor more likely than not needs to be amplified in order for use in the single op-amp load configuration.Perhaps drawing the circuit differently will make this clearer.Here is an extract of one-of-eight parallel circuits used in the HP6060 Electronic Load:

author: LooseJunkHater
author_rank: Frequent Contributor
timestamp: April 24, 2025, 05:02:48 pm
content: Quote from: MarkF on April 23, 2025, 12:17:57 amI tried making thiscircuit in Falstad, but I can't seem to get it to work. I did exclude the "TURNON" and "IMON*" lines, as I'd imagine they're not necessary? I'd imagineTURNONnotifies the MCU when the load is active, andIMON*notifies the MCU about how much current is flowing.________Edit: Nevermind, took a look at the schematichereand realized it actually needs a negative voltage to get the circuit to work.

author: LooseJunkHater
author_rank: Frequent Contributor
timestamp: April 24, 2025, 05:15:15 pm
content: Quote from: LooseJunkHater on April 24, 2025, 05:02:48 pmPer thefalstad simulation, it does look like the the analog design experiences a significant current spike whenever a load is connected, before it becomes regulated again, and it does look like there's quite a bit of oscilliations? I know the circuit was designed to initially be used with an MCU and isn't intended for a strictly-analog design, as I was looking into.Simply based on the Falstad simulation, it looks like the earlier post in this thread, #14, that Imade in Falstad here, may be a better design for an all-analog DC current load? But maybe I'm wrong.