Is it possible use a formula for electrical clearance in Altium? - Page 1
Forum section: electronics / general

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: May 19, 2022, 11:05:02 pm
content: In Altium Designer we can specify the electrical clearance between all sort of objects, esepcially between nets and between net and other objects.Often we have to specify rules that specify minimum distance between one net and another as a function of the net width. This has confused me a bit. If two nets have different widths, and we have specified clearance based on net width (e.g clearance value is twice the net width), which of the two will take precedance?There is a bigger issue. The track width of impedance controlled tracks is determinedautomaticallyby the Altium designer through input from the impedance profile. When such a track moves from one layer to another, the width of the track will change, due to law of physics, in order to ensure the same characteristic impedance. Now the question arises here, how does one automatically specify to Altium designer, to use the dynamic width of the track that depends on which layer it is on as it travels from sourch to destination, for the clearance rule? In other words, since the width changes as the signal travels from one layer to another, if the clearance is specified as twice the track width, Altium will need to re-evaluate the value of clearance since the clearance is a function of the PCB track width.I hope my question is clear. I am not sure how Altium deals with this. I think that for things like DDR tracks, there must be some sort of special mechanism to assign rules that make the whole task easier. The design rules concept in Altium Designer is neat but I fear that for complex designs, it might become a big mess (containing query langauge instructions) that is difficult to navigate for normal humans.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 20, 2022, 12:26:04 pm
content: If you're setting width by net and layer, then simply use the same selection rules in the other rule class, and enter the respective clearances.Diff pairs specifically are their own rule, including clearance, spacing and width. They require a plane to calculate impedance, or you enter the dimensions verbatim. Planes suck, so, that's the usual way.Unless this was overhauled in more recent versions, but I don't think so?Tim

author: KaneTW
author_rank: Frequent Contributor
timestamp: May 20, 2022, 01:27:11 pm
content: No planes needed anymore:

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: May 20, 2022, 10:17:59 pm
content: I think my question was not clear. Often the clearance between net and other objects is supposed to be specified as twice width of the net. Thus, the clearance is a function of the net width. Now if a net has multiple tracks across multiple PCB layers and these tracks differ in their width so the target impedance can be achieved on all layers, how does one specify the clearance value?As far as I know, the clearance value is a static number. We cannot specify it as a formula as far as I am aware. Please see the attached image, it shows what exactly I am talking about.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 20, 2022, 11:04:16 pm
content: Right, rules are fairly simple, they don't permit relational or referential expressions like "IsTrack AND (Width * 2)". Likewise there's no expression like, set comment to the value of some component property; or set X/Y to something nearby or touching, etc.The next best thing you can do is something like, OnLayer('each layer') AND (IsTrack OR IsArc) AND (Width > 10) AND (Width < 15) and set 20 to 30 clearance, and so on for each class you want.Just how often are you routing a huge spectrum of trace widths, anyway? And what does it matter that any of them have very particular clearance? Edgewise coupling is very small so it makes little difference to impedance (clearance to ground fill) or crosstalk (to neighboring traces).Probably, some / a lot of this can be automated with scripts if you like, but I don't know of any offhand for a task like that.Tim

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: May 21, 2022, 11:06:43 pm
content: What I am trying to figure out is, how does the user decide what value to specify for clearance in this case? There will be dozen of tracks, all going through a few vias between souce and destination. It is certainly something that needs extra care. I am not sure if you have done a lot of high speed board designs that involve high speed DDR memory devices.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 22, 2022, 02:41:45 am
content: Just do a InNetClass('DDR') and set the preferred/min/max trace width (it's only going to be the one width for each allowed layer), and clearance to others in same class, or in general. No problem.Tim

author: nctnico
author_rank: Super Contributor
timestamp: May 22, 2022, 06:14:31 pm
content: Quote from: matrixofdynamism on May 21, 2022, 11:06:43 pmIn general you set this up once together with the PCB stackup as fixed numbers. I don't see how it can be usefull to change the stackup during the design causing different clearance values. You might need to reroute large parts of a dense board.Also a word of advice: from what I've seen the impedance calculations in Altium are off quite a bit when you use thin dielectrics which are typically used for SOC designs. If you want to have accurate values, you will want to use a tool based on a field solver. So in the end you'll want to input fixed numbers anyway.The number of different constraints for high speed signals is not high (5 or 6) anyway so it isn't much work to type the numbers manually.

author: KaneTW
author_rank: Frequent Contributor
timestamp: May 24, 2022, 04:04:17 pm
content: Quote from: nctnico on May 22, 2022, 06:14:31 pmI just did a design with 50-120um dielectrics and Altium's solution coincided perfectly with the field solved solution from the PCB vendor. Altium supposedly uses a field solver internally, so it's not too surprising.

author: wgfeller
author_rank: Newbie
timestamp: June 02, 2022, 01:05:56 pm
content: Using formulas for setting values in a rule is not only interesting for calculating clearances, also for length matching in a DDR4 design. CLK should be longer than the Strobe signal. So min and max length for CLK depends from the DQS length.A notice from NXP AN5097: