What's happening in the world of MIPS? - Page 1
Forum section: electronics / general

author: Whales
author_rank: Super Contributor
timestamp: October 12, 2018, 02:21:49 pm
content: Traditionally I've seen MIPS have a stronghold in the consumer router market, mainly through Broadcom. I recall hearing a rumour about this being due to licensing costs being lower than ARM. That and they don't really have to care about power consumption, the customer pays.Now I'm seeing some home routers come out using ARM based chipsets, and I'm wondering is MIPS SoCs are losing their financial edge.Q1:Are there any new MIPS chips coming out?Q2:Who are still using them? Any other stronghold markets?

author: NorthGuy
author_rank: Super Contributor
timestamp: October 12, 2018, 02:29:06 pm
content: Microchip uses MIPS in PIC32. They bought Atmel, which used ARM in their MCU. I think they're about to drop their MIPS line and will rename Atmel SAM chips into PIC32.

author: legacy
author_rank: Super Contributor
timestamp: October 12, 2018, 02:52:31 pm
content: Probably future MIPS will be found only in Chinese products based on the successors of the Dragon chip. And they will be MIPS64-LE.

author: kfnight
author_rank: Regular Contributor
timestamp: October 12, 2018, 02:54:06 pm
content: It lives on in RISC-V.

author: legacy
author_rank: Super Contributor
timestamp: October 12, 2018, 03:15:06 pm
content: Quote from: kfnight on October 12, 2018, 02:54:06 pmand in our computer science's books

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 12, 2018, 03:35:54 pm
content: I believe this has been discussed several times in other threads, so you may want to do a little searching in the forum which will avoid people repeating themselves endlessly.That said, this is some kinda recent news that could change matters completely for the future of MIPS:https://www.mips.com/press/wave-computing-extends-ai-lead-by-targeting-edge-of-cloud-through-acquisition-of-mips/

author: westfw
author_rank: Super Contributor
timestamp: October 13, 2018, 04:05:31 am
content: I think MIPS has had happening what I am afraid will happen to ARM after the Softbank acquisition. Probably some high management guru decided "enough with all this diversification, trying to be everything for everyone. Focus exclusively on THIS "highly profitable" market segment (I think it was network appliances for MIPS. It'd probably be phones for ARM.) :-(It may sound good on paper, but it tends not to be what ends up providing innovation in CPU technology.

author: Whales
author_rank: Super Contributor
timestamp: October 13, 2018, 07:41:03 am
content: QuoteI had no idea those were MIPS, I presumed they were their own fancy arch. Thanks.Quote from: kfnight on October 12, 2018, 02:54:06 pmDoes RISC-V use a lot of MIPSy content, or do you mean spiritually?QuoteHey, are you trying to tell me you prefer RETs over JMP loops?I'll have a hunt

author: Whales
author_rank: Super Contributor
timestamp: October 13, 2018, 08:15:21 am
content: Ironically in a SPARC topic:https://www.eevblog.com/forum/microcontrollers/sparc-is-it-dead/?all

author: technix
author_rank: Super Contributor
timestamp: October 13, 2018, 09:05:00 am
content: Quote from: westfw on October 13, 2018, 04:05:31 amFor ARM both the phones and microcontroller markets are at least equally profitable. A good portion of the world’s CPU supply last year is Cortex-M. The Cortex-R line might see the axe drop, as those chips feature-overlap Cortex-M, and it won’t be too hard to port lockstep to Cortex-M33F or Cortex-M4F.As of MIPS, the problem is that people has realized that Cortex-A is as good in routing IP packets as MIPS, especially with the recent push by various vendors to build server-centric Cortex-A chips; meanwhile the talents accumulated in developing smartphone software is easily transferable. This enabled Cortex-A to encroach on the market segment previously dominated by MIPS.As an practical example, the ATSAMA5D36 chip has two Ethernet interfaces. Connect the RMII to a PHY and RGMII to an Gigabit Ethernet Switch chip like RTL8367, add 128MB DDR2 and 16GB eMMC and you get a reasonable and highly expandable router.

author: brucehoult
author_rank: Super Contributor
timestamp: October 13, 2018, 09:38:14 am
content: Quote from: Whales on October 13, 2018, 07:41:03 amRISC-V assembly language is very close to MIPS assembly language. The binary encodings are completely different.RISC-V rearranged the instruction encoding to:provide a huge amount of room for future extensions, even within the standard 32 bit opcode formatprovide uniform support for versions with 32, 64 and 128 bit integer registersprovide integrated support for optional 16 bit opcodes (like Thumb2) and for 48, 64, 80 ... 192 bit opcodes for future extensions. You can tell the length of an instruction by examining the low-order bits of the first byte: 00/01/10 for 16 bit 00011-11011 for 32 bit, 011111 for 48 bit, 0111111 for 64 bit, nnnXXXXX1111111 for 80+n*16 bit (the XXXXX is for the register to put the instruction result inAll this was achieved, basically, by shortening the field for immediate constants, load/store offsets, and conditional branch offsets from 16 bits to 12 bits. To compensate, the field for LUI and AUIPC is increased from 16 to 20 bits so you can still load any 32 bit constant or refer to anywhere in a 32 bit address space (absolute or PC relative) with two instructions. Unconditional branches also have a 20 bit offset.The downside is literals and offsets between +/-2k and +/-32k need two instructions instead of one in MIPS. If you use things like the standard "LI" pseudo-instruction then this is transparent.As well as this, in RISC-V you can compare two registers for EQ/NE/LT/GE and branch in a single instruction (recent MIPS has this too), and load and branch delay slots were removed.For anyone who knows MIPS it's very very familiar, just improved. And free for anyone to use.In May, MIPS announced a new 32 bit chip with a new "NanoMIPS" encoding that has 16, 32 and 48 bit opcodes. That looks pretty good too, but it's proprietary as hell and late to the party.

author: legacy
author_rank: Super Contributor
timestamp: October 13, 2018, 11:33:12 am
content: Quote from: brucehoult on October 13, 2018, 09:38:14 ameven in m88k, but at the cost of a bubble in the pipeline.do you know how is it implemented in RISC-V?

author: NorthGuy
author_rank: Super Contributor
timestamp: October 13, 2018, 01:49:31 pm
content: Quote from: brucehoult on October 13, 2018, 09:38:14 amThe delay slot is a good thing. The cycle is lost anyway. Why not to execute an instruction?

author: andersm
author_rank: Super Contributor
timestamp: October 13, 2018, 02:15:59 pm
content: Quote from: NorthGuy on October 13, 2018, 01:49:31 pmIt's an exposed pipeline implementation detail, which makes high-performance implementations more difficult. On the software side it also complicates exception handlers and debuggers.

author: legacy
author_rank: Super Contributor
timestamp: October 13, 2018, 02:37:59 pm
content: Quote from: NorthGuy on October 13, 2018, 01:49:31 pmfor several reasons, starting from the fact that it usually drives your crazy with hw-debuggers and ICEs.You can handle it, in theory, but at the end of the day, it's ... annoying.edit:for the record, it's what makes the use of SPIM (MIPS-R2K PC-simulator) very comfortable in computer science classrooms and laboratories, and it's *the* reason why Motorola put a bit in the configuration register of their m88K in order to disable the delayed slot. It has been appreciated by everyone has ever needed to use an ICE.

author: nctnico
author_rank: Super Contributor
timestamp: October 13, 2018, 03:02:44 pm
content: Quote from: legacy on October 13, 2018, 02:37:59 pmI totally agree. The delay slot cures your lust to program MIPS assembly quickly.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 13, 2018, 03:50:03 pm
content: Quote from: nctnico on October 13, 2018, 03:02:44 pmYou can always put "nop" into the delay slot if you don't like it. However you often can find something better than "nop" for the delay slot.MIPS architecture is very good for C compiler. Therefore, using assembler doesn't give you much advantage over C on MIPS. Regardless, the vast majority of users write in C/C++ and most of them know nothing about delay slots. The complier, though, behind their back, can utilize the delay slots to increase performance.

author: legacy
author_rank: Super Contributor
timestamp: October 13, 2018, 04:35:10 pm
content: Quote from: NorthGuy on October 13, 2018, 03:50:03 pmemmmm

author: brucehoult
author_rank: Super Contributor
timestamp: October 14, 2018, 12:03:51 am
content: Quote from: legacy on October 13, 2018, 11:33:12 amRISC-V is an instruction set. There are already dozens of different implementations at varying levels of performance, so they don't do things the same way.

author: brucehoult
author_rank: Super Contributor
timestamp: October 14, 2018, 12:22:50 am
content: Quote from: NorthGuy on October 13, 2018, 01:49:31 pmThe cycle may or may not be lost. On a simple implementation at low clock rate with only SRAM the result of a load might well be available to the next instruction. On a more complex implementation with scoreboarding or reservation stations etc the load might take several (or even many) clock cycles and the instruction using its result is put aside until the result is ready. This has been common in the x86 world since at least the Pentium Pro in 1995. On intermediate implementations the load might take several clock cycles (even from SRAM or cache) and if the result is needed by the immediately following instruction then the pipeline stalls -- in this case yes it's a good idea to put another instruction (or more) between the load and the use, if one is available.Thee problem with delay slots baked into the instruction set (and you have to put a NOP there if you don't have anything more useful to do) is that they assume one particular implementation point -- probably the first one you do -- while being totally inappropriate for both higher end and lower end implementations later on.As for branch delay slots, they have been made obsolete for 99% of branches by modern branch prediction techniques, even on microcontrollers such as the SiFive E31 (in the HiFive1) and E51. One those CPUs when the prediction is wrong you get to eat 3 clock cycles of stall, but it doesn't happen often. On the very low end E20/E21 (Cortex M0 competitor) there is no branch prediction and taken branches simply take 2 clock cycles. But you get compare-and-branch in one instruction.

author: Marco
author_rank: Super Contributor
timestamp: October 14, 2018, 01:47:09 am
content: On DSP loops anything but data based branch prediction always gets it wrong once every loop.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 14, 2018, 02:11:29 am
content: Quote from: brucehoult on October 14, 2018, 12:22:50 amI understand. Delay slots make sense only when you fetch instructions one by one. When you have "far" DDR3/DDR4 memory and a system of caches, the delay slot certainly doesn't help much. It may even be harmful, for example if it is located beyond the cache line boundary and would require fetching the whole new cache line. Thus, it has been removed from the low end systems simply for uniformity reasons. Makes sense.

author: brucehoult
author_rank: Super Contributor
timestamp: October 14, 2018, 03:17:33 am
content: Quote from: Marco on October 14, 2018, 01:47:09 amAren't most DSP loops controlled by a counter (e.g. array size) not by the data?

author: westfw
author_rank: Super Contributor
timestamp: October 14, 2018, 06:47:37 am
content: Heh. Look what showed up elsewhere...

author: coppice
author_rank: Super Contributor
timestamp: October 14, 2018, 11:42:22 am
content: Quote from: westfw on October 13, 2018, 04:05:31 amWhen ARM were developing the M3 and M0, MIPS was trying hard to go head to head with them, as they knew they could only survive by broadening their appeal across the whole of the embedded space. A number of MCU vendors evaluated the MIPS small core options, and found they had some pretty good qualities. In the end only Microchip signed up.

author: nctnico
author_rank: Super Contributor
timestamp: October 14, 2018, 11:59:01 am
content: Quote from: coppice on October 14, 2018, 11:42:22 amThis probably also had to do with the large ecosystem ARM already had created. Long (20 years ago) before ARM cores turned up in microcontrollers there was already a lot of support for the ARM based SoCs. Years ago I had to work with a MIPS based SoC. It was like being in friggin no-one's land. Every piece of software had ARM optimisations but nothing for MIPS. IMHO MIPS has missed the boat. If Broadcom and Microchip stop using MIPS then it is probably game over.

author: coppice
author_rank: Super Contributor
timestamp: October 14, 2018, 12:05:31 pm
content: Quote from: nctnico on October 14, 2018, 11:59:01 amPerhaps more relevant to MCUs is the old ARM7TDMI. It only got into a few (mostly really lousy) MCUs near the end of its life, but from the mid 90s it was doing a LOT of MCU like jobs embedded in larger parts, like hard disc controllers, GSM chips, and automotive parts.

author: brucehoult
author_rank: Super Contributor
timestamp: October 14, 2018, 12:22:55 pm
content: Quote from: coppice on October 14, 2018, 12:05:31 pmIn 2006-2008 I was working for a company selling a Java compiler for mobile phones. At least 90% were using the ARM7TDMI then.

author: technix
author_rank: Super Contributor
timestamp: October 14, 2018, 12:45:37 pm
content: Quote from: coppice on October 14, 2018, 12:05:31 pmAnd, y'know, Game Boy Advance. It is the ARM7TDMI that gave it SNES-level game experience without touching the helper chips like SuperFX and being power restricted by the handheld form factor. Nintendo stayed with ARM ever since on handhelds, even recently axed the PowerPC-based home consoles and merged it with the handhelds in the ARM-based Nintendo Switch hybrid console.I wonder if Nintendo is one of the driving forces behind Japan-based SoftBank buying out ARM...

author: Marco
author_rank: Super Contributor
timestamp: October 14, 2018, 03:01:37 pm
content: Quote from: brucehoult on October 14, 2018, 03:17:33 amFor most non-DSP architectures the difference is academic, they have no loop instructions, they can only branch on data comparisons. They don't know the data is a counter, so they can't anticipate what the comparison will be, they have to predict it and get it wrong once every loop. The x86 loop instruction is translated to branching too, so that doesn't help.Zero overhead looping was one of the common distinguishing features of DSPs.PS. there are ways to avoid it without loop instructions, prepare to branch instructions and manual BTB loading for instance ... but those are rare in modern architectures.

author: legacy
author_rank: Super Contributor
timestamp: October 14, 2018, 03:08:35 pm
content: Quote from: technix on October 14, 2018, 12:45:37 pmprobably, but ... Japan is weird since they are also supportingSuperHitachichip which they like to use their GPS, and it's not clear why they like to do so, but they do

author: legacy
author_rank: Super Contributor
timestamp: October 14, 2018, 03:13:46 pm
content: Quote from: Marco on October 14, 2018, 03:01:37 pmbranch prediction

author: Marco
author_rank: Super Contributor
timestamp: October 14, 2018, 03:19:09 pm
content: It is better to know than to predict, with branch prediction you often know ... but have no way to tell the processor. You just have to sit there seeing it waste cycles.

author: legacy
author_rank: Super Contributor
timestamp: October 14, 2018, 04:03:15 pm
content: well, dealing with Branches in the processor pipeline has been solved by several branch prediction techniques, fromStatic Branch Prediction(the cheapest) toDynamic Branch Prediction.in every conditional branch Instruction, the branch is taken only if the condition is satisfied, and the branch target address is stored in the Program Counter (PC) instead of the address of the next instruction in the sequential instruction stream.The branch that is guessed to be the most likely is then fetched and speculatively executed. If it is later detected that the guess was wrong then the speculatively executed or partially executed instructions are discarded and the pipeline is flushed and it starts over with the correct branch, incurring a delay.In short, the smarter the branch prediction goes the fewer penalties are in computation being.Therefore the point is: enhancing the prediction is a good point, and within the class of Dynamic Branch Prediction we are able, in theory, to collect a deep history of instructions and conditions running in the CPU in order to apply advanced statistics and even AI algorithms to predict branches with a low failure rate, it's called hyperdynamic branch prediction, which sounds exciting (so they said in Intel, "hyper" comes from the need of using a hyperplane, a matrix with 3 dimensions, to keep the information) except this introduces more complexity in the design of the chip, it potentially slows down the CPU ( it doesn't scale well on frequency) and more area needs to be taken in the silicon.So ... we all prefer the KIS approach, and we have resolved the problem with the compromise of accepting a smaller pipeline. The smaller the pipeline goes (which means fewer stages) the shorter the delay of penalty goes on wrong branch predictions.oh, reintroducing instructions like "do loop until this counter is greater than zero" would be great, but ... again it costs more complexity in RISC design.umm, to be honest, not so much, and "Arm" stands for dvanced ISC achine therefore if it wishes it can copy this feature from whatever implementations we have seen in CISC CPUs, even take the challenge of implementing thehyperdynamic branch predictionthat will turn a CPU into a Skynet AI-driven chip(1), but ... for sure it's not compliant to the pure and minimalistic approach of MIPS processors(1) kidding. The chip mentioned in Terminator movies.

author: brucehoult
author_rank: Super Contributor
timestamp: October 14, 2018, 04:30:54 pm
content: Quote from: Marco on October 14, 2018, 03:01:37 pmNo, that's not correct.Modern branch prediction techniques -- which started with the Pentium MMX and Pentium Pro in the mid 90s and are now incorporated into even mid-range microcontrollers -- are capable of executing loops with trip counts of up to maybe 20 or so with *zero* mispredictions after the first couple of times.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 14, 2018, 04:40:03 pm
content: Quote from: Marco on October 14, 2018, 03:01:37 pmEven naïve branch prediction (e.g. take it if it jumps back and don't take it if it jumps forward) works reasonably well and won't create much overhead on tight fast loops.However, all these heuristic methods (caching, re-ordering, branch prediction) are good when you want to optimize average speed, but at the same time, they make the worst case worse.

author: legacy
author_rank: Super Contributor
timestamp: October 14, 2018, 04:46:33 pm
content: Do you know? we have reached a level of artificial intelligence in our algorithms able to predict people's purchase wishes before people actually decide to do any purchase.These algorithms are used byAmazon,eBay, and many others for many other applications which need to predict something by identifying common patterns.I have recently done some personal researching by applying these algorithms to my softcore with the specific purpose of reducing the failure rate at branch predicting and it has actually made by several orders of magnitude, which is extremely good! Unfortunately, the downside is that these algorithms need to learn, they need time for this, and they consume a lot of memory.My softcore runs as a software HDL simulation, while the branch prediction unit is an external module written in C and able to interact with the HDL simulator , and every plan for a hardware translation of its algorithms has always come into the need of more ram than the FPGA can provide(1), and no less than 90 cycles to speculate on the branch prediction.Which is definitely too crazy even for a hobby, it slows down the clock by two orders of magnitude (1:100), therefore it has been abandoned, but it has been a crazy cool show(1) more than 8Kbyte of BRAM on my little Spartan3 considering a prediction matrix to speculate on 2Kbyte of instructions.I would infer two points on a hypothetical corollary1) these algorithms can only be applied to small RAMs, like an L1 cache2) judging by my implementation, 1Mbyte of L1 cache needs 4Mbyte of space for the matrix

author: legacy
author_rank: Super Contributor
timestamp: October 14, 2018, 04:50:00 pm
content: Quote from: brucehoult on October 14, 2018, 04:30:54 pmyup, These algorithms are on made on second order statistic, and they work well for loops.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 14, 2018, 04:59:45 pm
content: Quote from: legacy on October 14, 2018, 04:46:33 pmMarketing doesn't work bypredictingpurchaser's wishes. It works bycontrollingpurchaser's wishes, which is much more efficient approach.

author: legacy
author_rank: Super Contributor
timestamp: October 14, 2018, 05:59:57 pm
content: Quote from: NorthGuy on October 14, 2018, 04:59:45 pmno doubt they make us more prone to purchase by well-done advertisements, but this is psychology matter, while computer science it's more interested in predicting algorithms based on statistics. They used these algorithms to increase the efficiency of warehouses in the first place. These algorithms are also used by the police, e.g. the "big brother" project used in the UK.there was a crazy and funny fact happens when an artificial-intelligence-driven data analyzer predicted a sixteen years old girl was pregnant by suggesting her several purchases for a baby before her consciousness was aware of what was happening.Oh, you could even think the data analyzer was pushing the young girl to be pregnant, but this for me sounds more "mind control" than how it should be. Why? it's just software, without any human intervention, and it keeps analyzing where you click, and for what

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 14, 2018, 08:56:42 pm
content: Quote from: Whales on October 13, 2018, 07:41:03 amI was suspecting we'd get to read it all over again, the quirks of the dated MIPS architecture, how it's more of an academic learning tool than a practical one, how ARM has been eating MIPS alive, and a pinch of RISC-V. And finally how MIPS is dead without being really dead. Turns out that's pretty much what we got.The acquisition of MIPS by "Wave Computing" may not bode too well for the future of MIPS. AI and deep learning is all the rage, but this is just some kind of start-up as far as I got it, and this kind of acquisitions often have a bad ending.Quoting them:QuoteAhem.

author: brucehoult
author_rank: Super Contributor
timestamp: October 15, 2018, 12:08:30 am
content: Quote from: NorthGuy on October 14, 2018, 04:59:45 pmMostly I find that I see ads on every site I visit for a product or service I need once or once a year AND BOUGHT YESTERDAY.Right now, I'm seeing ads everywhere from booking.com for a hotel in Fiji that I already booked on expedia on Saturday. I had checked the price on booking.com as well, just in case it was better.

author: NorthGuy
author_rank: Super Contributor
timestamp: October 15, 2018, 02:10:19 am
content: Quote from: brucehoult on October 15, 2018, 12:08:30 amThis is an example of good marketing. You didn't have any desire on checking prices for what you already have. Google showed you the ad. This inspired a desire to click and check prices. You clicked, Google got the commission for the click. Brilliant marketing.It certainly doesn't matter for the Google if your click was of any use to the advertiser.

author: brucehoult
author_rank: Super Contributor
timestamp: October 15, 2018, 03:42:40 am
content: Quote from: NorthGuy on October 15, 2018, 02:10:19 amNo, I checked the price on booking.com before I booked it on expedia.Google showed me the ad for booking.com after I already had the hotel booked.I didn't click the ad, google didn't get click commission.

author: Marco
author_rank: Super Contributor
timestamp: October 15, 2018, 04:41:16 am
content: Quote from: legacy on October 14, 2018, 04:50:00 pmFor loops which loop twice and are still in the BTB next time they loop ...

author: legacy
author_rank: Super Contributor
timestamp: October 15, 2018, 02:35:12 pm
content: anyway, the intriguing question is now: what happened to R8K? what?!?you know what! it was that big chip in the prototype suit offered by SGI!it was a strange beast, with a weird branch prediction unit

author: srce
author_rank: Regular Contributor
timestamp: October 18, 2018, 07:51:00 pm
content: Quote from: brucehoult on October 13, 2018, 09:38:14 amA RISC-V fan talking about being late to the party?

author: legacy
author_rank: Super Contributor
timestamp: October 20, 2018, 06:49:04 pm
content: I wonder who has ever used or seen one of theeval boardsmade by IDT.This one was manufactured around the 2000's and looks funny

author: nctnico
author_rank: Super Contributor
timestamp: October 20, 2018, 06:55:01 pm
content: Offtopic: someone had fun while combining a TQFP and BGA footprint

author: legacy
author_rank: Super Contributor
timestamp: October 20, 2018, 06:56:03 pm
content: Quote from: nctnico on October 20, 2018, 06:55:01 pmLOL

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 20, 2018, 07:08:16 pm
content: Quote from: legacy on October 20, 2018, 06:56:03 pmLooks funny indeed, but they were probably unsure of the short-term availability of either package when they designed the board and were probably pressed by upper management to release it ASAP.

author: Whales
author_rank: Super Contributor
timestamp: October 21, 2018, 05:52:28 am
content: That's a very interesting looking board. Thanks for the high-res picRAMThree types:- 1 DIP for 8-bit (occupied)- 4 DIPS for 32 bits- more traditional SODIMM (occupied)I'd guess the 32bit memory bus is split across four 8-bit DIP rams so that it can access them all in parallel, rather than sequentially. Presumably this is an alternative to using the SODIMM.The 8-bit slot is however more interesting -- did someone mention these processors booting up in an 8-bit mode? Maybe the entire addressing system changed electronically as well as logically, so this processor required an 8-bit RAM chip for boot.I/OUnless you use some PCI I/O cards you are limited to just RS-232.By golly that MAX23 at the top-right has a lot of big caps attached, they were not taking any chances about it not being able to charge pump.EDIT: It comes with an OS built into its EEPROM too. Lots of curly details.https://www.idt.com/document/mae/79s334a-evaluation-board-manual