comparator datasheet interpretation - Page 1
Forum section: electronics / beginners

author: hirada
author_rank: Regular Contributor
timestamp: November 15, 2017, 11:25:54 am
content: Hello,on my hopeless search for a comparator I have come across some figures from the datasheet I would like to have clearified or I am missing. Maybe.1)For open collector / open drain comparators, is there something like a minimum current limit? Usually the pull up resistors in the datasheets are rather low values, geared more towards the maximum allowed sink current. Understandably. But if the load I want to drive is like a cmos and I only need a very few uAmps, are there any problems to be anticipated when the sink current is really low due to a very high value pull up resistor?2)Differential input voltage. This one really scares me, but maybe I get it wrong.Usually the common mode input (I presume that referes to the max. voltage I can safely apply to either the inverting or noninverting input? Still fighting that common mode terminus) is around or slightly below the supply voltage. Some notable exceptions, like the LT1116, allow input voltages to be massively above the positive supply voltage, but those are rather scarce.So I assumed the invertig and the noninvering outputs may as well be on either side of the supply voltage, so if I had ±12V supply, I could have a reference of -11V @ the inverting and +11V @ the non inverting input. Would make for a 22V difference. But that is not automatically to be implied?If a differential voltage of 5V is given, then I could only apply -6V to the non inverting input in above example? Is the differential voltage an additional input restriction? Or am I completely off track?Because the AD790 specifies common mode as +VS-2V, while the differential voltage is specified @ full +/-Vs. So its larger than common mode input.3)Some TI datasheets mention a VIDvalue. But I have so far not been able to find out its meaning. Like the TI lmv7219 datasheet talks about an Output High Swing (why not simply output voltage?) at IL=4mA (I suppose the output current current drawn) with VID=500mV. Now for this example the Differential Input Voltage equals supply voltage, so I do not assume the "D" in VIDstands for differential [input voltage.]4)Some have a strobe pin. I have not been able to find out, what that practically means. I sure do not need it, but would like to understand its use, while we are at it.5)Additionally I have found latching and shutdown pins. I wonder, wether there is also a known model that features a reset switch? Like, as long as this pin is high, the output is low regardless of the inputs?Or could I even rely on Voutbeing definite groundlevel (V-), when SHDN is high and the device therefore disabled? With the help of a pulldown resistor maybe? Referring to the TI tlv3501 here, in case someone has experience with that particular chip.6)The output low voltage is usually specified @ around 0.1-0.4V But since this is still above GND, why are some then sinking current? I understand sinking to be current flowing into the device? So occasionally you read somethig like Ioutfor low output swing is -15mAThat's for all for now. But more to come I am afraid and thanks for reading this tale, if you made up to here.

author: danadak
author_rank: Super Contributor
timestamp: November 15, 2017, 12:07:40 pm
content: 1) For open collector / open drain comparators, is there something like a minimum current limit? Usually the pull up resistors in the datasheets are rather low values, geared more towards the maximum allowed sink current. Understandably. But if the load I want to drive is like a cmos and I only need a very few uAmps, are there any problems to be anticipated when the sink current is really low due to a very high value pull up resistor?Min would be leakage considerations, which could affect noise margin, logic levels, if Rpullup and/or leakage too high.2) Differential input voltage. This one really scares me, but maybe I get it wrong.Usually the common mode input (I presume that referes to the max. voltage I can safely apply to either the inverting or noninverting input? Still fighting that common mode terminus) is around or slightly below the supply voltage. Some notable exceptions, like the LT1116, allow input voltages to be massively above the positive supply voltage, but those are rather scarce.So I assumed the invertig and the noninvering outputs may as well be on either side of the supply voltage, so if I had ±12V supply, I could have a reference of -11V @ the inverting and +11V @ the non inverting input. Would make for a 22V difference. But that is not automatically to be implied?If a differential voltage of 5V is given, then I could only apply -6V to the non inverting input in above example? Is the differential voltage an additional input restriction? Or am I completely off track?Because the AD790 specifies common mode as +VS -2V, while the differential voltage is specified @ full +/-Vs. So its larger than common mode input.CM and Vdiff are two separate considerations. CM is referred to ground, whereas Vdiff just refered to input pins. Has to do with breakdown limits of on chip input diff amp structure.3) Some TI datasheets mention a VID value. But I have so far not been able to find out its meaning. Like the TI lmv7219 datasheet talks about an Output High Swing (why not simply output voltage?) at IL=4mA (I suppose the output current current drawn) with VID=500mV. Now for this example the Differential Input Voltage equals supply voltage, so I do not assume the "D" in VID stands for differential [input voltage.]Vid is usually a test condition, which specifies overdrive conditions to trip the comparator. For speed and delay specifications.4) Some have a strobe pin. I have not been able to find out, what that practically means. I sure do not need it, but would like to understand its use, while we are at it.From a representative datasheet (not necessarily the one you decide to use) -A low-level input at either strobe causes the outputto remain high regardless of the differentialinput.When both strobe inputs are either open orat a high logic level, the output voltage iscontrolled by the differential input voltage.5) Additionally I have found latching and shutdown pins. I wonder, whether there is also a known model that features a reset switch? Like, as long as this pin is high, the output is low regardless of the inputs?That would be a strobe pin.Or could I even rely on Vout being definite groundlevel (V-), when SHDN is high and the device therefore disabled? With the help of a pulldown resistor maybe? Referring to the TI tlv3501 here, in case someone has experience with that particular chip.6) The output low voltage is usually specified @ around 0.1-0.4V But since this is still above GND, why are some then sinking current? I understand sinking to be current flowing into the device? So occasionally you read somethig like Iout for low output swing is -15mAThe output low voltage is usually refereed to negative rail. Not ground unless negative rail grounded. The source current is telling you, for an output taken close to negative rail what you can anticipate getting out of the high side output driver in the output structure.The output low is referred to negative rail. So the output transistor to ground in the output driver circuit is hardon sinking any current coming from load referred to ground. The -15 mA is telling you, if your load is pullingto ground (more appropriately the negative rail), but comparator is driving high, what current you can expect to sourceout of the output high side transistor driver.Here is a general reference (OpAmps and Comparators similar in many respects) -http://www.ti.com/lit/an/sloa011/sloa011.pdfRegards, Dana

author: Benta
author_rank: Super Contributor
timestamp: November 15, 2017, 01:37:30 pm
content: For 1, switching speed is an issue. At low currents, the output can get really slow.

author: danadak
author_rank: Super Contributor
timestamp: November 15, 2017, 03:06:27 pm
content: To the point about speed vs Rpullup value.. Also in extreme situationsif the risetime is very very slow, you can put a connected CMOS inputinto oscillation as you will spend a lot of time in the active or linearregion of the CMOS gate. Noise in system will make it unstable. Statedanother way there are min values of risetime that must be considered.I think the rule of thumb is you want Trise << Tph (prop delay) of the gate.I will defer to someone else if this is an incomplete or wrong statement.Regards, Dana.

author: hirada
author_rank: Regular Contributor
timestamp: November 16, 2017, 07:11:01 pm
content: Thanks very much for your detailed explanations. Despite that fact, that I cannot yet really comprehend the leaking and speed issues, I'll take with me, if I do not intend to use at least 1/10 of the sinking current, I'll stick with push-pull. Better idea anyway, but limits choice quite substantially.Quote from: danadakNow that's quite fundamental. Thanks for clearifying.Quote from: danadakNope. According to the example you have given, the strobe can uncondtionally set the output high, I could need to force it low. Can of course be archieved otherwise, but this would save a part or two. I'll play with shutdown, once I have decided what comparators to buy for evaluation.Quote from: danadakAnother important heads up, I've got trapped into some datasheets are providing data for both single or dual supply and I have been biased towards a 0V output, as that is what I need - for an AC inputsignal.Quote from: danadakGreat link. Thanks

author: danadak
author_rank: Super Contributor
timestamp: November 16, 2017, 10:35:27 pm
content: The speed issue is simply if you have an open collector output with apullup R, when the comparator goes high, the R supplies the current tocharge any stray C or Cin of other logic connected to comparator output.The higher the value of Rpullup will cause longer times for the outputto achieve the logic level intended. R x C time constant, charging.The leakage issue concerns when the op[en collector output is off, sothe R is supposed to pull it up to the rail. But leakage in the output,flowing thru the Rpullup, can cause Vout to drop to the point it lookslike a logic low, which is what was not intended. So high values ofRpullup can aggravate this problem.Regards, Dana.

author: hirada
author_rank: Regular Contributor
timestamp: November 20, 2017, 07:25:35 pm
content: Again, thanks very much for this insight! Very helpful for my slowly growing general understanding. Especially since I tend to go a little over the top with high value resistors and the whole capacitance issue - outside actual capcitors - is still a little abstract. Well, inside, too, but thats for another thread.