Front-end design for a 12 bits precision ADC  - TI's ADS7250 - Page 1
Forum section: electronics / projects

author: ealex
author_rank: Frequent Contributor
timestamp: August 21, 2015, 04:03:44 pm
content: HelloI want to play with an embedded software defined radio capable of receiving voice and some basic digital modes or act as a spectrum analyzer : quickly jump between a list of specified frequencies, make a "snapshot" and send the FFT back to be displayed on a PC as an image.The cpu will be a cortex M4F - more than enough power for the second part, at least ( 1024 points complex fft takes ~ 1 ms with the core pushed at 168MHz and not optimization enabled )The plan is to use a "Tayloe" front end - based on this one :https://s3.amazonaws.com/files.qrz.com/l/w6jl/LSB_ONLY_TAYLOE_5_17_2013.jpg. This type of front-end is quite low-noise if properly built - i have a Rx ensemble II module and it's dead quiet with it's input shortedThe main problem is to get the analog signals from the front-end into the M4F cpu without adding too much noise or using expensive components.Initially I thought about using the internal ADC's but they are useless for this type of application.The analog bandwidth will be 20kHz => the sampling rate will be of 40-50kSpsI decided to use TI's ADS7250 12bit simultaneous sampling ( important ) DAC :http://www.ti.com/lit/ds/symlink/ads7250.pdfI can extend the dynamic range by adding a BF998 AGC amplifier ( as i already use in my set-up ).The datasheet contains, starting from page 26, some typical applications that i intend to follow in my circuit.I can understand why they are buffering the reference with the OPA2350 in figure 55.I can't understand why, in figure 56 they are using VCM = VREF/2 for biasing the input driver op-amp. Should't it be biased at 2.5V so it will be able to swing symmetrically from 0 to 5V around VREF ?I will have toAlso, why are they using OPA836 for the driver and OPA2350 for the reference buffer ? OPA836 has a greater bandwidth - will it oscillate when driving capacitive loads ? I would like to get rid of the OPA2350, if possible because of it's price.Another question is where to place the anti-aliasing filter. From the ADC's datasheet i understand that the RC network after the driver is important - especially having low R values, so adding it there is not an option.Can I add a simple unity gain buffer and a RC or LC low pass filter before the driver ?Another question: can I use some other low-noise op-amps that do not have such a high bandwidth ( and price ... ) for this application ? What should be the limiting parameter ?I'll also add here info about the front-end ( design, measurements, etc) once I can get get the boards out of Customs and make some basic checksThanks,alex

author: coppice
author_rank: Super Contributor
timestamp: August 21, 2015, 04:27:33 pm
content: I assume you are saying the MCU's internal ADC is useless because it has only a single sampler. Since you only need to sample at 50ksps per channel, you could use an external dual sample and hold, and the internal ADC.

author: ealex
author_rank: Frequent Contributor
timestamp: August 21, 2015, 06:40:06 pm
content: There are 2 independent ADC's on the chip i have - i think i can make them sample at the same time by triggering them from a timer.i've had ~ poor results with on chip adc's. especially on the low end of the input range - the sample rate is not the limiting factor.I would like to use as much of the available ADC resolution as possible on the input signal and not add noise, etc from the digital sidethe entire domain is black magic for me, so i'm trying to gather as much info. as i can before i start working on a board.i'll start using the on-chip adc's to start the software, and compare the results with the external sound card i use - capture raw data while inserting some test signals to compare noise, etc, at least to get a general ideai've attached a piece of the stm32f4's datasheet regarding the ADC's