Unstable electronic load design - Page 1
Forum section: electronics / projects

author: jpk42
author_rank: Contributor
timestamp: April 25, 2017, 05:06:20 am
content: Hi all,My background: junior electronics engineer at a power electronics company, dabbling in some home projects. <2 years industry experience.I have designed an electronic load for use in CC, CV, CR and (quasi) CP modes. The basic functionality is thus:Microcontroller powered via an ATmega2560. Micro reads trimpot, current shunt, voltage and temperature (via NTC) values and limits operation accordingly. Trimpot value is spat back out as a PWM into a low pass filter signal which is then used to set the current/voltage/resistance demand value (TRIM into IC101B as shown). There are four legs of FETs - Q101-Q104 inclusive, all with individual shunt resistors, current shunt amplifiers and controllers that are driven via the TRIM value, with the idea that the PI controller around IC101B controls the gate of the FETs. The current shunt amplifier is to obtain a 0-5V value from the low value shunt resistor, with approximately a 300mV offset. IC105 is used in conjunction with other parts to set the operating mode.Schematic of relevant parts:I have managed to get the firmware to a functional point where adjustment of the PI gains is required. With just the one FET leg in circuit (Q101) and operating purely in CC/constant current mode and providing a voltage input in the range 5-30V, 3A current limited from a bench power supply and monitoring the gate signal to Q101, winding the 10 turn trimpot up does not turn the FET on until a certain point. After this the current draw quickly rises over the next quarter turn until it reaches 3A, where the supply collapses and everything goes wrong. Furthermore, the gate signal oscillates frequencies >100kHz at this point, usually by +/-4V or so. I've fiddled with the PI gain values of R109, R161 and C101 via some process of trial and error, but nothing seems to cure the instability. Replacing R111 (the gate resistor) with a 40ohm ferrite bead in an attempt to remove the high frequency oscillations didn't improve things, nor does soldering a 100k resistor across pins 6 & 7 of IC101B. Presently with R109 = 1k, R161 = 180k and C101 = 1.5uF, I get the following Q101 gate waveforms at the given load currents:12Vin, 0.5A load12Vin, 1A load12Vin, 2A loadMy questions are, am I missing a fundamental part of my circuit to ensure stability? How do I determine the gain values I need? My simulations in TINA-TI don't show this oscillation with the same components. I have used the top answer by scorpdaddy athttps://electronics.stackexchange.com/questions/237099/op-amp-pi-controlled-electrical-loadto approximately set my present gains, but still to no avail. Any suggestions would be greatly appreciated.Just a wild guess at what could be the problem, do I need an emitter follower style circuit on the output of IC101B to drive the gate of the FET if the output drive capability of my OPA2376 isn't enough? I somewhat doubt this seeing as many others have successfully used this configuration before.Thanks.EDIT: fixed image links.

author: theatrus
author_rank: Frequent Contributor
timestamp: April 25, 2017, 05:52:13 am
content: Are you sure you want an integrator for IC101? Thats a fairly unusual design decision here and likely the source of your issues.

author: jpk42
author_rank: Contributor
timestamp: April 25, 2017, 07:24:20 am
content: Quote from: theatrus on April 25, 2017, 05:52:13 amI thought it was normal to remove the steady state error in the response? What is the problem here? Nonetheless, I will test this.

author: tszaboo
author_rank: Super Contributor
timestamp: April 25, 2017, 08:49:26 am
content: Try removing C110 and C111. C101 should be a lower value, try it in the few nF range. Place a high value, Mohm resistor parrallel with R161+C101. R111 should be approximately 47 Ohm, it is there to isolate the gate charge from the opamp's output. And maybe place a zener in the integrator, just to limit the output signal max value. The FET looks OK.It takes some time and effort to make circuits like this stable. Sometimes a lot of time.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 25, 2017, 12:10:47 pm
content: The shunt has a really low value. So parasitic inductance can by very important there. It get easier with a higher shunt value - not really need to go much below the on resistance of the FET.C112 is likely doing more bad than good. With so much gain this stage is usually stable anyway.The input side (drain of the FET) might need an RC snubber to ground, at least with an inductive load.

author: tszaboo
author_rank: Super Contributor
timestamp: April 25, 2017, 12:37:36 pm
content: Oh, yes, 1 mOhm is small. Your gain is 67 I think, and your setpoint is 0-5V. So do you expect 70A from this circuit? You need 4-5V VDS on the FET for that current, which would mean 300W. You have at least 0.42 K/W thermal resistance junction to sink in that FET. Which is 125 degrees above ambient and everything. Little bit too warm.

author: theatrus
author_rank: Frequent Contributor
timestamp: April 25, 2017, 04:00:28 pm
content: Quote from: NANDBlog on April 25, 2017, 08:49:26 amThis would be my advice as well. Integrators are fine, but its a pretty large integration value.

author: jpk42
author_rank: Contributor
timestamp: April 26, 2017, 12:43:01 am
content: Thanks for all the advice. Plenty of things to try this evening. Will report back with results of each suggested change - will likely just practically test each, as they don't take much time.Quote from: NANDBlog on April 25, 2017, 12:37:36 pmAbout 60A at 3.3V (so about 83 degrees over ambient etc), I formulated the following characteristics for each common voltage/current setpoint, using a maximum power dissipation of 250W per FET. I have a 80x80x300mm heatsink with a 80x80x38mm fan attached to the front for cooling. The FETs are screwed directly to the heatsink here. These are just ballpark, as I will scale everything accordingly once I've done some practical testing with thermocouples and the microcontroller running some sort of thermal limiting control via the NTC.

author: jpk42
author_rank: Contributor
timestamp: April 26, 2017, 12:41:05 pm
content: I removed C110, C111, C112, and changed C101 to 4.7nF. R109 was 1kohm, and R161 was 10kohm at this point. Added a 1M0 across the sum of C101 and R161 as suggested. This controller was still unstable.Changing R109 to 15kohm made everything stable, even with C110-C112 added back to the circuit and without a 1M0 resistor. Is the 1M0 to increase the DC gain of the controller?I still have further testing to ensure this combination is stable, but it appears sufficient for now while I move forward with other things.

author: tszaboo
author_rank: Super Contributor
timestamp: April 26, 2017, 03:08:03 pm
content: Quote from: jpk42 on April 26, 2017, 12:41:05 pmOK I was pretty close with C101.The 1M resistor places a DC offset for the opamp, so if you have an offset variation, it does not let the opamp turn on automatically. You have a trim voltage, makes it unnecessary, 1 less production step. You can actually remove the resistor.I'm not sure why would you need C110 and C111 in the first place. I think it slows down the feedback, so it reduces stability, without any actual benefit. Is there a reason for it?So if you do everything the best you can control, it is 0.42 K/W and you pump in 200W in... With a huge heatsink, forced air cooling... I guess it can work. You are on the edge though. I had water cooling when I worked with similar power. Put 75W in a TO220. Actually, put thousands of watts into a bunch of TO220s.Actually, congrats for getting it stable. Try it with different voltages. Do you have any requirements for rise/fall times?