ADC from 1 MegaOhm source at room temperature vs 70C? - Page 1
Forum section: electronics / general

author: incf
author_rank: Frequent Contributor
timestamp: March 04, 2025, 10:20:48 pm
content: I have a commercial application where an ADC is sampled once per minute from a source with a 1 megaohm output impedance (with 100nF capacitor at ADC pin).It works great at room temperature. But in the future it might have to operate at 70C.We can't use a buffer op-amp due to certain constraints.My STM32 is rated for a maximum of 70nA input pin leakage at 20C ("max by design, not tested in production").There is a rough rule of thumb that leakage might increase by a power of 2 for every 10C increase in temperature.I estimate:max_offset(20C)=70mVmax_offset(70C)=2240mVDoes this estimation seem accurate? (leakage is to ground, leakage proportional to 2^[Delta_T/10C])We don't need a very accurate measurement, but I am concerned that I might get wildly unpredictable results that vary unit to unit in the field.Does anyone have any experience with (ab)using an ADC like this?I sort of wish I could calibrate each unit in the factory at 70C (put a SMD resistor under the chip to heat it during testing? I feel like even 500mW would not be sufficient to raise the temperature of a 4 layer PCB to 70C)

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 04, 2025, 11:31:01 pm
content: Quote from: incf on March 04, 2025, 10:20:48 pmIf it really matters, you are going to need to test this.Yes, you will need a lot more than 500mW to heat a PCB, but heating is an easy problem.PCB leakage may matter as much as the IC leakage and that means moisture and moisture history become important. Is the unit sealed?If you have spare ADC pins, you could add a 1M ohm to 2 (or more) ADC pin's each side of the measuring pin, which will give you an indication of variation and tracking.

author: incf
author_rank: Frequent Contributor
timestamp: March 04, 2025, 11:40:11 pm
content: Quote from: PCB.Wiz on March 04, 2025, 11:31:01 pmIt is unsealed. Are you saying that FR4 absorbs moisture in a manner that meaningfully affects it's insulation resistance?I've done some tests on PCBs submerged in water - and that definitely affects insulation resistance. But, I'd like to think that normal humidity levels would not have a large enough effect to matter.But I guess, I'd just have to test it in an environmental chamber. (Which I cannot readily do at the moment)Quote from: PCB.Wiz on March 04, 2025, 11:31:01 pmI don't think I fully understand this. Would these other two pins be fed from independent 1M sources? And run as if it was a guard ring around the "real" 1M trace?I suppose the goal would be to independently measure IO pin leakage current, and PCB insulation/contamination/tracking. The first one seems easy enough, the second seems quite difficult to do.edit: maybe the unit will have to attempt to calibrate itself in the field if moisture/insulation resistance/PCB contamination are to be accounted for.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 05, 2025, 12:08:24 am
content: Quote from: incf on March 04, 2025, 11:40:11 pmYes, the idea is to have a closed case and easy run time check on the actual leakage. You would pick a mid-scale voltage to bias those pins to.In your lab tests, you would feed the external signal thru the known external 1M and record all 3 signals.That gives you data on tracking and variations.In the field, you can then use the sanity-check pins to indicate possible errors.Addit : google find this paperhttps://www.circuitinsight.com/pdf/moisture_measurement_in_pcbs_ipc.pdf

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 05, 2025, 12:18:21 am
content: Quote from: incf on March 04, 2025, 11:40:11 pmYes, if you find those 3 pins track reasonably or somewhat, you can use that to auto-correct in the field.

author: incf
author_rank: Frequent Contributor
timestamp: March 05, 2025, 12:24:24 am
content: Is FR4 moisture absorption a reason why checkered ground planes are present in some test equipment? (I always though it was an etching/plating related thing)

author: thm_w
author_rank: Super Contributor
timestamp: March 05, 2025, 12:51:56 am
content: What part number specifically? Some STM32 have built in opamps.Quote from: incf on March 05, 2025, 12:24:24 amIt is an etching thing to balance amount of copper on each layer. But better to just have a full ground plane.

author: incf
author_rank: Frequent Contributor
timestamp: March 05, 2025, 01:53:30 am
content: No internal op-amp (not that their input leakage characteristics would be much better). It's parts from the STM32G0 family.

author: David Hess
author_rank: Super Contributor
timestamp: March 05, 2025, 02:10:55 am
content: Quote from: incf on March 04, 2025, 10:20:48 pmCan you use discrete transistors? Discrete transistors can buffer a signal with millivolt accuracy.QuoteThe leakage is very likely to be consistently much better than the testing specification. If you run some environmental tests, you will likely find that there is nothing to worry about even with the leakage doubling every 10C.Working with the maximum test limits is good for a sanity check, but seldom represented real world performance.QuoteAs the other post suggests, there is a way to calibrate the leakage. Apply a calibrated voltage to another ADC input through a 1 megohm resistor to measure the leakage. The voltage can be calibrated by applying it directly to a third ADC input, so the difference between the measurements divided by the resistance is the current leakage.Quote from: incf on March 04, 2025, 10:20:48 pmI have abused low bias current analog designs like this. I had one design which had to operate in the Texas sun while maintaining leakage significantly below 50 picoamps. The solutions which worked included low input bias current bipolar parts where input bias current does not increase with temperature, and CMOS parts where typical input bias current started in the femtoamps.

author: incf
author_rank: Frequent Contributor
timestamp: March 05, 2025, 02:32:04 am
content: I don't think discrete transistor amplifiers are suitable either. It's a slow moving DC signal where we "sort of" care about DC offsets.It's mostly a matter of power, board space, cost, and most importantly of all "inertia" - we already are doing it without an amplifier and would like to avoid changing too much with an already "known good" design if at all possible.

author: MathWizard
author_rank: Super Contributor
timestamp: March 05, 2025, 03:49:41 am
content: Well if you can't use a buffer, this is way worse, but what about enclosing the thing in a heated box that maintains 70C ? Or can you use cooling, to keep the IC temp down ?Or is all that too expensive, or too late or too big ?

author: schmitt trigger
author_rank: Super Contributor
timestamp: March 05, 2025, 05:17:33 am
content: I fully understand your desire to not change a successful design, but you are now asking the circuit to perform at conditions which were not originally considered.We can discuss and argue this for the next 1000 posts and we wouldn’t be any closer to absolute certainty. I don’t see a way out of your conundrum other than to actually test and validate via statistical analysis the assumption.Data is your best friend.

author: woofy
author_rank: Frequent Contributor
timestamp: March 05, 2025, 09:33:54 am
content: Re-design your circuit and use a buffer op-amp.Its no good putting this in an environmental chamber and calibrating it. Process variations during production can wipe that out. What flux did the contract house use. What cleaning system? Any remaining contaminants will effect the performance individually depending on temperature, humidity and which particular module you are looking at. What happens when the contract house changes flux, or moves from wave to selective soldering? Do yourself a favour and eliminate the issue now.

author: Kleinstein
author_rank: Super Contributor
timestamp: March 05, 2025, 10:33:07 am
content: The actual leakage performance is likely quite a lot better than the max specs. Testing for low leakage is expensive and is thus usually not done.The 20 C leakage specs may include parts that don't depend much on temperature. Some parts are actually checked for leakage at a higher temperature (like 60 or 85 C) and 20 C leakage may be estimated the other way around.The leakage is not necessary to GND there are also chip internal FETs towads the positive supply.For testing the leakage (e.g. on a separate pin) one could also use a capacitor (e.g. 1 nF C0G) and look at the drift. This way one could check the leakage current under different conditions.Using a separate OP-amp alone helps relatively little with PCB leakage - it would need a guard trace from the OP-amp to make a difference.A seprate OP-amp may at least have enough pin spacing for a guard - this could get challanging with a LQFP case.PCB leakage is usually less temperature dependent. It tends to go up when the RH is high enough to form a surface water layer. At which RH this happens depends on cleaning and material. Humidity in the bulk PCB has more a slow mechanical effect and via stress may effect resistors and amplifier offsets to some degree. A patterned ground can help to reduce PCB bending.

author: JoeyG
author_rank: Regular Contributor
timestamp: March 05, 2025, 10:44:22 am
content: +1 buffer (opamp) as close to the 1M source

author: peter-h
author_rank: Super Contributor
timestamp: March 05, 2025, 11:28:50 am
content: I would use a buffer op-amp.You can provide isolated power with just an LED and a photodiode, etc.

author: incf
author_rank: Frequent Contributor
timestamp: March 05, 2025, 11:53:53 am
content: One last thought,Is there any almost zero quiescent power, zero cost ways of implementing something like a low leakage SPST switch on a ~3V design using jellybean parts?. (I think near-obsolete JFETs probably won't work without significant effort, but maybe I'm wrong)Since sampling occurs once per minute, maybe the source could be buffered with a capacitor and a switch, and then briefly connected to the MCU ADC signal trace/pin for sampling.It's unfortunate that commodity FETs like the 2N7002 (or rather, low threshold version variants of the same part) "seem to leak like a sieve" even at room temperature if their worst specifications are to be believed. (Maybe I'm wrong, and high temperature rated FETs might not leak much at 70C?)Something like 100nA of leakage at 70C would the the target for a FET switch - which seems totally unreasonable.

author: Kleinstein
author_rank: Super Contributor
timestamp: March 05, 2025, 12:01:27 pm
content: FET switching is tricky as they usually need a voltage outside the signal voltage range for control.There would be 74HC1G66 switches as a kind of generic small one, but they need a little power (typ 1 µA).There are also low power OP-amps for a buffer: e.g. MCP6041 with some 0.6 µA of supply current.

author: incf
author_rank: Frequent Contributor
timestamp: March 05, 2025, 01:07:41 pm
content: Quote from: Kleinstein on March 05, 2025, 12:01:27 pmI ended up starting a thread "Projects, Designs, and Technical Stuff » ~50nA low-leakage FETs that don't use 'satanic tiny little DFN packages.' ? "There is a P-Channel FET the PMZ950UPEL which has 25nA of leakage (max guaranteed) at room temperature and has a gate threshold voltage of 950mV. It looks great, but I don't like the package.I'm pretty sure a low-leakage FET like that would make quick work of my problem without any quiescent power consumption.

author: David Hess
author_rank: Super Contributor
timestamp: March 05, 2025, 03:46:30 pm
content: Quote from: incf on March 05, 2025, 02:32:04 amIf the transistor buffer adds 2 millivolts of offset, but the leakage adds from 70 to 2240 millivolts of offset depending on temperature, the transistor buffer seems like a better option despite adding 2 millivolts of offset, but see below about an operational amplifier used as a buffer.QuoteThere are plenty of inexpensive SOT sized low-power and micro-power operational amplifiers which could be used in this application. The OPA990 is an example of such a part at $1 and 130 microamps but there are even better options.Quote from: Kleinstein on March 05, 2025, 10:33:07 amIf the operational amplifier used as a buffer is placed where the signal enters the board, then most of the board leakage becomes irrelevant.QuoteAs you know from my recent experiences with printed circuit board leakage, it can be both large and very temperature dependent. I have one remaining broken DM501 that seems to be suffering from 3 nanoamps of board leakage when warmed up, which as you pointed out is a large amount of leakage for a board.Quote from: incf on March 05, 2025, 11:53:53 amI was going to suggest that. There are CMOS switches available in SOT-23 sized packages which draw practically no power and can easily meet your leakage specifications. Use one to disconnect the input pin from the capacitor and then activate it during the conversion.

author: incf
author_rank: Frequent Contributor
timestamp: March 05, 2025, 04:00:25 pm
content: Quote from: David Hess on March 05, 2025, 03:46:30 pmI'd like to learn more about this circuit.What (single?) transistor buffer introduces a 2mV offset?Surely not a NPN emitter follower which introduces ~700mV of offset.And a NFET source follower which often introduces ~2500mV of offset (depends on threshold voltage).

author: David Hess
author_rank: Super Contributor
timestamp: March 05, 2025, 09:32:15 pm
content: Quote from: incf on March 05, 2025, 04:00:25 pmA single JFET can produce zero offset, but what I had in mind required several transistors. A single SOT package micropower operational amplifier would be better and take up less space.

author: peter-h
author_rank: Super Contributor
timestamp: March 06, 2025, 02:02:30 pm
content: QuoteI struggle to imagine a circuit which gives you a x1 gain with zero offset, using a single JFET.A JFET (e.g. 2N3819) is a depletion mode device with a Vgs of a few volts, negative.The only way I can see a bipolar circuit giving a small offset is a discrete op-amp i.e. a long tail pair, but you won't get 1mV unless you match the two transistors, plus couple them thermally. Gosh that takes me back to the old days of the MAT100 etcNow I see the MAT01https://www.analog.com/en/products/mat01.html.

author: David Hess
author_rank: Super Contributor
timestamp: March 06, 2025, 02:51:09 pm
content: Quote from: peter-h on March 06, 2025, 02:02:30 pmJust have to set the JFET source current to the proper value. Some JFETs will not allow this because the current will be too high.QuoteDiscrete transistors from the same lot usually match better than a millivolt. A larger problem would be dealing with a 1 megohm source resistance, although it can be done. There are some inexpensive dual matched transistors available.The micro-power or low-power operational amplifier configured as a follower is really the way to go. Power can easily be low enough to power off of an output pin if necessary. Bandwidth is not a concern with a 1 megohm source.