Lattice CPLD fails to verify. - Page 1
Forum section: electronics / general

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: May 31, 2017, 04:13:44 pm
content: Just wondering if anyone has seen this and has some thoughts.I have an LC4256ZE on a board and am using the Diamond Programmer software with an official WH-USBN-2B cable. I am able to verify the Chip ID OK but when I attempt loading the jed I get this.Code:INFO - Check configuration setup: Start.INFO - JTAG Chain Verification. No Errors.INFO - Check configuration setup: Successful.INFO - Device1 LC4256ZE: Erase,Program,VerifyERROR -Failed in Function VERIFY (see log file for more details)ERROR - Process Operation Failed.INFO - Elapsed time: 00 min : 02 secERROR - Operation: unsuccessful.ERROR - Programming failed.The JED file is built to the same device LC4256ZEI readthe manualand tried increasing the TCK Divider up to 30, and adding a pulldown resistor between TCK and GND on the board.I've double checked all the connections, and the fact that the Chip ID verifies at least proves that.If I've fried the chip somehow I'll replace it if I have to.Log File.Code:Connected to Lattice Cable Server.Lattice HW-USBN-2B cable detected.Check configuration setup: Start.JTAG Chain Verification. No Errors.Check configuration setup: Successful.Device1 LC4256ZE: Erase,Program,Verify--------------Row1--------------:HDR 0TDR 0SDR 1592 TDI(00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000)Expected TDO(5FF87E0318C6318C619CEBFFFFFE3FFFE3FFC7F87FFFFDFFFEBFFF8BFF10842108421BD7FFF17FE2F884213FFF17FFFFFFBD7FFF1FFE7F9CE739DEFFAFFC3F18CC6318C6318C7DFFFFFFFAFFFFFFFC3F17C5F18CE75FFFC5FF8BE2108421085FFFFFFEF5FFFC1F098C6318C6318CBFFF8FFF3FCE77BDE37FFFFEFFFFEBFFF83E5318C6318C67B97FFF17FE2F8842117FF7FFFFFFFBD7FFF1FFE6F98E73BDEFFAFFFE6FFCDF318C6318C5FFFFFF7FAFFFE2FFC42109EF19FFF5FFFCFFF986739CE77BDFFFFFFFFD)Received TDO(FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000)Bits Error 1592: Expected: 0 Received: 1Bits Error 1590: Expected: 0 Received: 1Bits Error 1579: Expected: 0 Received: 1Bits Error 1578: Expected: 0 Received: 1Bits Error 1577: Expected: 0 Received: 1Bits Error 1576: Expected: 0 Received: 1Bits Error 1569: Expected: 0 Received: 1Bits Error 1568: Expected: 0 Received: 1Bits Error 1567: Expected: 0 Received: 1Bits Error 1566: Expected: 0 Received: 1and more...Execution time: 00 min : 02 secFailed in Function VERIFY (see log file for more details)Process Operation Failed.Elapsed time: 00 min : 02 secOperation: unsuccessful.

author: daveshah
author_rank: Unknown
timestamp: May 31, 2017, 05:57:28 pm
content: Try putting about 10-30pF, I use 18pF, capacitance from TCK to ground. I've needed this to successfully program Lattice FPGAs (MachXO2 series) otherwise I get a similar problem, although that was with a compatible FTDI MPSSE cable rather than the official Lattice one.

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: May 31, 2017, 06:49:04 pm
content: Thanks Daveshar I'll try that and report back. You don't use the pull down resistor as well?

author: daveshah
author_rank: Unknown
timestamp: May 31, 2017, 08:21:26 pm
content: I've never found a need for a pull down resistor, although as mentioned I am using a different cable and target so the requirements may be different.

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: June 01, 2017, 09:04:59 am
content: Well I put an 18pF cap on the clock to ground and it is much the same. I'll put the scope on the signal lines tonight otherwise might just have to accept it's poked.