How to add automatic polygon cutout under pads belonging to certain net? - Page 1
Forum section: electronics / general

author: ManCave
author_rank: Regular Contributor
timestamp: February 26, 2020, 10:47:57 am
content: Hey,I'm working on an RF design and I want to add polygon cutouts to the GND plane under pads which belong to the RF 50ohm nets. I can do that manually but I would like to know whether there is a way in altium to define a rule to do this for me.Here is what I mean:Thanks!

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: February 26, 2020, 11:30:54 am
content: Hmm, dunno if that's recommended for an RF design?From what I have always seen you want your reference plane plane right under the RF trackwork, not in-between like you are trying to do right now

author: ManCave
author_rank: Regular Contributor
timestamp: February 26, 2020, 11:46:31 am
content: ANTALIFE, that's correct. However, pads are not your 50ohm trace width. They are larger and cause excessive capacitance between the pad and the plane which (in my case) is 0.1mm underneath. A single 0402 pad, 0.1mm from the nearest GND plane, can be as much as25pF0.25pF capacitor. Removing the pad area underneath, providing vias for the return path to couple to the next plane down solves this.Have a look at this document from intelhttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an530.pdfas you say, you still need to carefully consider your return paths...

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: February 26, 2020, 12:00:12 pm
content: Quote from: ManCave on February 26, 2020, 11:46:31 amOh wow the more you know, never really though about pads that wayBack to your question, I can see two ways of doing this:Program up a rule for the polygon you want to "cookie stamp" in the PCB editorMake a custom footprint for all RF related components in PCB library editor, and define a keepout area thereKnowing how finicky Altium can get, especially if you decide to revisit the project later on and generate the Gerbers again, I would be more included to go with option 2. That way you are in full control defining the keepout areas. For example, make a copy of the 0402 footprint and call it 0402-RF, and in there make a keepout area (covering all layers) under the pads

author: ManCave
author_rank: Regular Contributor
timestamp: February 26, 2020, 12:32:24 pm
content: I thought of making the custom footprints, but sometimes I just want one pad to have the cutout, sometimes both.. and then there are LNA chips and receiver, etc... they'd all have to be custom. This seems laborious. I'd much prefer a method where I have rule which is tied to pads on certain net, but I have no idea how to make it do a polygon cutout on a separate layer.This would ensure that- only pads of components tied to that net have cutouts underneath- when I move the component, the cutout moves with itI'm not with you on the suggestion number 1. Can you elaborate please?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 26, 2020, 01:22:22 pm
content: 0. Do you know that you actually need to do this?I see a GPS net name. Is this only 1.5GHz? It won't mind a few 0402s. Place them close to the receiver, I suppose. Include footprints for impedance matching if possible. (Likely you'll never need to adjust them?)1. Is this narrowband? Have you simulated the signal path?For example, a thinner trace connecting to the offending pads does the same thing, making an LC filter of sorts. Make it resonate at Zo, Fo to eliminate return loss over whatever bandwidth the structure has.More likely you'll simply adjust the impedance matching network slightly, and that's that.2. This was a typo, right?:Quote from: ManCave on February 26, 2020, 11:46:31 amNo one makes laminate with κ = 1000...Note that the intended capacitance of 0.7mm trace length at 50 ohms is pretty damn close to 30fF, so 0402 pads really are quite a good deal.Note that the Altera/Intel document is talking about considerable bandwidths (over 20GHz), and small gain errors (<1dB). These are relevant to extreme precision timing applications, but not very important even to most high-speed protocols. For example, USB, PCIe, SSTL, etc. all have modestly wide eye diagrams, use compensation tricks to deal with FR-4 and losses and microstrip dispersion, and are timed with separate clocks with adequate setup and hold times, or are self-clocked, immune to small changes in delay).2. Altium doesn't have any relational mechanisms between layers, except for the very specific operations cooked into certain layers and objects. You're probably best off putting the poly cutout or keep-out in the footprint itself.Tim

author: ManCave
author_rank: Regular Contributor
timestamp: February 26, 2020, 02:44:46 pm
content: Thanks T3sl4co1l!!not a typo, a stupid miscalculation! Turns out the calculator units were in cm and I was inputting mm. So it's 0.25pF not 25 with dk=4.8... apologiesIt is GPS. I haven't simulated it. I have matching network in place, the thing is the traces are so short, it's basically pad after pad after pad.......so I'll have to match it afterwards anyways as the traces are almost non-existent.OK, seems like there's no shortcut for what I wanted to do in altium but also as you say, there might not be a need at this frequency. Just wanted to follow best practicesThanks all for taking time to help!

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: February 26, 2020, 10:35:29 pm
content: Quote from: ManCave on February 26, 2020, 12:32:24 pmAh those pesky units ;^)Also attached might give you an idea. Here I make a simple rule to not add a thermal relief to pads/nets that meet a certain condition

author: ManCave
author_rank: Regular Contributor
timestamp: February 27, 2020, 08:57:00 am
content: Thanks! I could define the condition for what I needed just wasn't sure if you can have inter-layer rule and couldn't find any rule that would do what I wanted. As T3sl4co1l said chances are that was an impossible task to start with and altium doesn't have that functionality.