FPGA expected lifetime - Page 1
Forum section: electronics / general

author: sasa
author_rank: Regular Contributor
timestamp: August 31, 2017, 06:31:47 pm
content: What exactly is expected lifetime for modern FPGA? Is there some reliable study about?Comparisons with recent and older technology (7 years ago perhaps)?I can find some old infos (from 2010 on altera forum) that that depends moderately of FPGA grade and it is from 1 to 10 years or more.According to EEPROM (firmware) and SRAM lifetime, temperature and stable power supply, lifetime of modern devices based on FPGA (TVs, standard HDDs and similar consumer products) is usually no more than 4-5 years in average.

author: legacy
author_rank: Super Contributor
timestamp: August 31, 2017, 06:55:58 pm
content: I guess the "MTMF" in the datasheet can give an idea

author: rstofer
author_rank: Super Contributor
timestamp: August 31, 2017, 07:01:44 pm
content: If you want the right answers, go to the source:https://www.xilinx.com/support/documentation/user_guides/ug116.pdfFigure at least one million hours... About 114 years and that's probably with TJ=125 deg C.The other manufacturers probably publish the same kind of information.

author: KE5FX
author_rank: Super Contributor
timestamp: August 31, 2017, 07:38:49 pm
content: Your configuration PROM is probably the weak link in this particular chain.

author: dmills
author_rank: Super Contributor
timestamp: August 31, 2017, 08:48:23 pm
content: That or overshoot on the IO pins, this is usually a critical parameter especially on 3.3V banks, and FPGA pin drivers are usually more then fast enough that you need to pay attention to that stuff.Regards, Dan.

author: rstofer
author_rank: Super Contributor
timestamp: August 31, 2017, 08:49:34 pm
content: Quote from: KE5FX on August 31, 2017, 07:38:49 pmAnd production boxes will write the PROM once and read many times. OK, there may be some firmware upgrades over the lifetime but the PROM is not a serious consideration.

author: KE5FX
author_rank: Super Contributor
timestamp: August 31, 2017, 08:57:13 pm
content: Quote from: rstofer on August 31, 2017, 08:49:34 pmThat's not how that works.

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: August 31, 2017, 10:26:47 pm
content: Quote from: sasa on August 31, 2017, 06:31:47 pmHow did you figure that? If true, many manufacturers would be in trouble because having half your products fail in less than 5 years would not be good for your reputation.And do TVs, HDDs and other similar products actuallyhaveFPGAs in them, or do they mostly use custom ASICs? I doubt that FPGAs are used much in cost-sensitive consumer products.

author: rstofer
author_rank: Super Contributor
timestamp: August 31, 2017, 11:37:37 pm
content: Quote from: KE5FX on August 31, 2017, 08:57:13 pmAccording to Spansion, their S25FL128S, as used on the Digilent Nexys5_DDR board has a 100,000 write cycle endurance and 20 year data retention. If it is a matter of charge bleeding off over time, firmware upgrades would be a good thing.I didn't stumble across a reliability report. OTOH, I didn't specifically look for one.

author: KE5FX
author_rank: Super Contributor
timestamp: September 01, 2017, 12:49:41 am
content: Quote from: rstofer on August 31, 2017, 11:37:37 pmSorry, I thought by "the PROM is not a serious consideration" you were disagreeing that the PROM is more likely to fail before the FPGA. Seems safe to assume that it will be, in most real-world scenarios.Kind of a shame, too, as 20 years isn't all that long. Most of them will last much longer than that, but still...

author: joeqsmith
author_rank: Super Contributor
timestamp: September 01, 2017, 01:51:18 am
content: Quote from: sasa on August 31, 2017, 06:31:47 pmInteresting topic depending how deep down the hole you want to go. I still have a copy of 217 (?) laying around. It was a bit too conservative for automotive and PREL was born. I doubt you would even find information on PREL. No idea what best practice is today for calculating FITs.

author: Jeroen3
author_rank: Super Contributor
timestamp: September 01, 2017, 07:08:39 am
content: Quote from: rstofer on August 31, 2017, 07:01:44 pmThats not how manufacturers write their spec. Everything is 25C, unless explicitly written otherwise.

author: sasa
author_rank: Regular Contributor
timestamp: September 01, 2017, 08:07:54 am
content: Thank you all for comments.The pointed ug116.pdf is really informative document. Thank you very much!The main interest for me currently is program/erase endurance test under room and hight temp(! that table seems to miss), HTOL and TH/THB tests data. Then data for non-hermetic and hermetic packages, reliability data for certain packages, etc...Some data seems to me quite strange. For instance, Actual Device Hours at TJ>=125°C and Equivalent Device Hours at TJ=125°C of 61,012 / 1,208,215 for XC4VxXxxx devices...All in all, quite a bit of useful data to analyze...Thanks to all very much again.

author: David Hess
author_rank: Super Contributor
timestamp: September 01, 2017, 05:35:39 pm
content: Quote from: rstofer on August 31, 2017, 08:49:34 pmFloating gate memory, especially high density floating gate memory and especially especially NAND Flash, has a finite retention time. In the past this was not a problem however I have become rather suspicious that some modern consumer level hardware with firmware stored in Flash based memory has failed this way. Fuse based memory can have problems where the blown fuses "regrow". Anti-fuse based memory seems to be more reliable and is found in some FPGAs.http://www.fpga-site.com/faq.html#Memory_Technology

author: VHDLwhiz
author_rank: Newbie
timestamp: September 02, 2017, 12:07:09 pm
content: Apart from the lifetime of the chips, there is also obsolescence problems that you might want to take into consideration. Especially for defense applications, this is a huge problem. If you can't get your hands on any more chips, you will have to redesign.Another problem with supporting designs in the long run is that also the software tools get obsolete. For example, Xilinx' new Vivado software only supports Virtex-7 and up. If you have Virtex-6, you are stuck with the older ISE tool. I've seen examples where old designs could only be revised on old software which would only run on Windows XP. Microsoft has ended the support of Windows XP and most companies have banned the OS by now. Truly a nightmare for the unfortunate who gets assigned with the task of implementing a small feature.

author: dmills
author_rank: Super Contributor
timestamp: September 02, 2017, 03:21:41 pm
content: We are playing the ISE for old things and Vivado for new stuff shuffle at the moment (The changes to the constraint files are annoying).I especially like old VHDL that only works with a specific set of placement constraints, in one specific (OLD) version of ISE (Yea there is a bug in the VHDL somewhere) and which does not have a testbench.... Grumble.For real 'fun' old GALs programmed in CUPL, what a pain.Regards, Dan.

author: alm
author_rank: Super Contributor
timestamp: September 03, 2017, 03:31:14 pm
content: Quote from: rstofer on August 31, 2017, 07:01:44 pmThat's not how these numbers work. Just because only 5 ppm of devices failed within 1000 hours (giving you a frequency of one failure per 200 million device hours) does not mean that after a million hours, you'll only have 0.5% failures. If you did the same with people: if out of 1000 people aged 40 ten years ago, 990 survived to this day, does that mean the average 40 year old has a life expectancy of 1000 years? Failure rates are only meaningful within the expected life expectancy. Any kind of bathtub curve will mess up your prediction.