pic 18f4620 pwm (enhanced) half bridge mode - Page 1
Forum section: electronics / general

author: spidermanIIII
author_rank: Newbie
timestamp: March 02, 2016, 09:50:59 pm
content: hi, i want to make pwm and its complementary for half bridge so i choose pic 18f4620 but it give me one pwm but the complementary doesn't appear i read the datasheet he datasheetwhat is the problem please help meQuote

author: sarepairman2
author_rank: Frequent Contributor
timestamp: March 03, 2016, 05:03:39 am
content: http://www.linear.com/product/LTC6992-12$http://www.ti.com/lit/ds/symlink/sn74lvc1g04.pdf0.5$lack of compiler errors ? pricelessfor everything you don't want to get grey hair from, there's analog.

author: Howardlong
author_rank: Super Contributor
timestamp: March 03, 2016, 07:00:18 am
content: I don't have an 18f4620 but I do have an 18f4550 which also has the ECCP and looks, from the DS, to be an identical peripheral. I breadboarded it up and your code works (although I re-wrote it to use the standard Microchip XC8 peripheral definitions). It generates contra-signals on P1A and P1B as expected.I note that some silicon revisions of your chip have a reasonably extensive errata including with the ECCP, I don't know if that affects your revision.Code:// PIC18F4550 Configuration Bit Settings// 'C' source line config statements#include <xc.h>// #pragma config statements should precede project file includes.// Use project enums instead of #define for ON and OFF.// CONFIG1L#pragma config PLLDIV = 1 // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))#pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])#pragma config USBDIV = 1 // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)// CONFIG1H#pragma config FOSC = INTOSC_HS // Oscillator Selection bits (Internal oscillator, HS oscillator used by USB (INTHS))#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)// CONFIG2L#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)#pragma config BOR = ON // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))#pragma config BORV = 3 // Brown-out Reset Voltage bits (Minimum setting 2.05V)#pragma config VREGEN = OFF // USB Voltage Regulator Enable bit (USB voltage regulator disabled)// CONFIG2H#pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)// CONFIG3H#pragma config CCP2MX = ON // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)#pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)#pragma config LPT1OSC = OFF // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)// CONFIG4L#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)#pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)#pragma config ICPRT = OFF // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))// CONFIG5L#pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)#pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)#pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)#pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)// CONFIG5H#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)// CONFIG6L#pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)#pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)#pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)#pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)// CONFIG6H#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)// CONFIG7L#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)#pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)#pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)// CONFIG7H#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)void main(void){TRISA=0;TRISB=0;TRISC=0;TRISD=0;CCP1CON=0b10001100; //enable half bridgeTMR2=0;PR2=124; //for 500 HzCCPR1L=20;T2CONbits.T2CKPS1=1; //prescalar 16T2CONbits.T2CKPS0=0; //prescalar 16T2CONbits.TMR2ON=1; //timer 2 onwhile (1){NOP();}return;}

author: spidermanIIII
author_rank: Newbie
timestamp: March 03, 2016, 08:03:14 pm
content: Quote from: Howardlong on March 03, 2016, 07:00:18 amfirst of all I wanna thank you for your help. can you please attach the hex file i need and can you explain what you mean by I note that some silicon revisions of your chip have a reasonably extensive errata including with the ECCP, I don't know if that affects your revision.

author: oilburner
author_rank: Contributor
timestamp: March 04, 2016, 02:31:27 pm
content: Quote from: sarepairman2 on March 03, 2016, 05:03:39 amThanks for the giggle, I love this post!

author: Howardlong
author_rank: Super Contributor
timestamp: March 04, 2016, 04:25:23 pm
content: Quote from: spidermanIIII on March 03, 2016, 08:03:14 pmYou need to check your chip's errata. As for giving you a hex file for a chip I don't have, I'd rather not, debugging in the blind isn't a speciality of mine! Why can you not take the source code I've offered?