LTC4006 stange Mosfet drive signal behavior. Am I missing something basic? - Page 1
Forum section: electronics / projects

author: Electr0nicus
author_rank: Regular Contributor
timestamp: November 25, 2012, 04:06:29 am
content: HiI and my buddy have built up the Li-Ion Charger circuit with the charger IC LTC4006, discussed here:https://www.eevblog.com/forum/projects-designs-and-technical-stuff/battery-charger-with-ltc4006-design-question/LTC4006 Datasheet:http://www.linear.com/docs/1961We've followed the suggested design- rules in the LTC4006 Datasheet as much as possible. And came out with alayout, which is very good in our opinion. As there are some changes in the final layout compared to the layoutposted in the above mentioned thread, I'll post the final here:And of course the schematic:The key specs of this charging circuit are:Input voltage: 20VCharging current: 4A maxBattery end of charge voltage: 16.8VAfter manufacturing and populating the pcb at home, a first test was performed.The strange thing is, that without any battery connected, the circuit consumes approx. 6W at 20V. Also the top P- Channel Mosfet of the synchronous Step- Down converter stage gets very hot. So it is obvious, that a great part of these 6W are dissipated in that tiny SO8 package. Also the bottom MOSFET (for synchronous rectification) gets warm, but not as warm as the top, switching MOSFet, because it has a lower On- resistance. I can't run the charger for more than 10 seconds, because the top Mosfet gets so hot, that the risk of it going up in fumes is very high. And this with no battery connected.So I started investigating. Fist of all I measured the gate drive signals of both MOSFETs seperately.I got really ugly waveforms for both MOSFETs, with very much oscillation.My first thought was, that some EMI from the inductor or the high current paths of the circuit are coupling into the gate drive signals. To prove that assumption, I desoldered the inductor from the pcb. Now the current consumption of the circuit shouldn't be more than 5mA, (this is the max. current the LTC4006 can consume), because there is only the MOSFET Bridge connected between Vin and GND. If the MOSFET bridge works properly, there should be no chance, that current can flow from Vin to gnd. (refer to schematic for details).Well, I enabled the charger again. Now the current consumption is a bit lower, but the circuit still consumes 4.5W, and the Mosfets still get very hot.So I looked closer on the datasheets of the used Mosfets. The top- MOSFET, a TPC8128, has a Total Gate Charge of 115nC and a Gate Capacitance of 4800pF. The bottom MOSFET, a NXP PSMN8R3-40YS, has only 20nC and 1215pF.Datasheets:TPC8128http://www.semicon.toshiba.co.jp/info/docget.jsp?type=datasheet&lang=en&pid=TPC8128PSMN8R3-40YShttp://www.nxp.com/documents/data_sheet/PSMN8R3-40YS.pdfIRFMH9331pbfhttp://www.irf.com/product-info/datasheets/data/irfhm9331pbf.pdfSo I thought, that the high Gate Charge of the Top- Mosfet is loading down the LTC4006's MOSFET driver circuitry. So I happend to have a P-Channel Mosfet with a lower Gate Charge and Capacitance at home, but unfortunately not in a suitable package (PQFN 3x3mm). So I soldered it on the pcb manhattan style, instead of the TPC8128.Finally the drive waveforms looked much better, but there was still a short period of time where both MOSFETs conducted at the same time, and obviously shorted out the Vin voltage rail to GND. I've measured both drive signals and added some commentary:As you can see the top- MOSFET drive signal, after it transitions to its off- state it suddenly turns on again by a huge spike, when the bottom- MOSFET is already conducting, thus shorting out the supply voltage for a short period of time. I've measured 5A peak.NOTE: This oscilloscope image is madewith the inductor desoldered,so there should be 0 current flowing.See the attached image of the homemade pcb as a referenceI've tried with another LTC4006 device, same result. Unfortunately in the datasheet, the maximum drive current of the LTC4006's internal MOSFET drivers is not specified. Only rise and fall times for a Cload of 3000pF are specified. As I'm using low input capacitance (<1500pF) MOSFETs now, this shouldn't be a problem anymore. Also I don't think, that the pcb traces from the LTC4006 to the mosfets have such a high inductance, that it really matters that much.Maybe one of you guys/girls here in the forum can help us, we are really stumped where the problem lies. Please help.Cheers Gregor & Michael

author: Skimask
author_rank: Super Contributor
timestamp: November 25, 2012, 05:00:52 am
content: No pullups (P-channel) or pulldowns (N-channel) on the MOSFETs. Gates are floating.

author: Electr0nicus
author_rank: Regular Contributor
timestamp: November 25, 2012, 05:15:21 am
content: Quote from: Skimask on November 25, 2012, 05:00:52 amI'll give that a try, although, I don't think, that there are pullups needed, because the gate drivers are proper drivers, which can drive either high or low. I only can recall using pullups on open collector outputs. I've also had a look on the demoboard's schematic and there are also no pullups used.But anyways, I'll try it out and report back.

author: Electr0nicus
author_rank: Regular Contributor
timestamp: November 25, 2012, 05:46:07 am
content: Quote from: Skimask on November 25, 2012, 05:00:52 amOk I've tried using pullups, but with no noticable effect on the signal quality. Have a look yourself:Signal of top- MOSFET without pullupSignal of top- MOSFET with 42k pullupSignal of top- MOSFET with 21k pullup

author: amyk
author_rank: Super Contributor
timestamp: November 25, 2012, 06:52:17 am
content: From the datasheet:QuoteYour traces look really long.QuoteThat trace could've been made smaller too.Look at the demo board's layout to see just how close they've put the FETs and the IC:http://www.linear.com/demo/DC495A

author: Electr0nicus
author_rank: Regular Contributor
timestamp: November 25, 2012, 07:28:58 am
content: I've looked at the demo board layout, but there they are using a four layer board (which we don't want to use), and the demo circuit is designed only for 2A, which results in smaller components, and thus a smaller layout size and shorter trace length. In our design we gave the critical signals like all the high power stuff and sense resistor wiring priority. The Top- and Bottom- MOSFET signals were considered as "not so critrical", because they are relatively low impedant (compared to sense signals) and the switching frequency is not very high. Yeah I know, frequency says nothing, but a rise time of minimum 50ns shouldn't have that much effect, or am I wrong?Btw. trace lengths are as follows:Top- MOSFET: 31mmBottom- MOSFET 36mm.Having the trace lengths in mind, it is even more surprising, that the longer trace for the bottom MOSFET has lower distortion than the shorter trace for the Top- MOSFET.

author: Kremmen
author_rank: Super Contributor
timestamp: November 25, 2012, 07:53:49 am
content: You don't seem to have any gate resistors in your circuit. The block schematic of the driver circuit is not very specific but if the outputs are plain totem poles or similar, there could be some overdrivng taking place. Now it is the idea to switch on and off as fast as possible, but grossly overdriving the gate does induce heavy ringing in the switch, especially at turn-off. Adding some gate resistance might improve the ringing but whether that is the root cause of your heating problem i cannot say offhand.

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: November 25, 2012, 08:34:14 am
content: Kremen beat to it - gate driveseriesresistors of about 10 to 20 ohms. Gate ringing isn't 'strange' it is a direct consequence of a parasitic LC oscillator and is present in just about every naive implementation of fet drivers.

author: HackedFridgeMagnet
author_rank: Super Contributor
timestamp: November 25, 2012, 01:36:08 pm
content: Here's a link to an app-note talking about this.http://application-notes.digchip.com/009/9-12721.pdfUnfortunately I may have just done the same thing in one of my new boards. I thought the gate resistors were put in only for thermal considerations.I didn't put the gate resistors in because Linear didn't and I am using the LTC4449.I will find out the extent of the problem in a couple of weeks. The boards haven't arrived yet.

author: lewis
author_rank: Frequent Contributor
timestamp: November 25, 2012, 06:22:52 pm
content: It looks like the gate of the P-fet is being dragged low exactly when the N-fet turns on due to its gate charging current. (Took me a while to notice CH1 was inverted). Looks to me like a supply bypass issue - the 'input caps' are miles away from the IC, you might need another 10-22uF ceramic between CLN and GND right at the IC. (The gate drivers are powered from the CLN pin).The path length from the 2x10uF input caps, through the kelvin sense on the output side of the 0.027R, then through the thin trace to the CLN pin is huge, and therefore very inductive. All the gate charge current comes down this line, so it needs a decent bypass cap right at the chip.

author: qno
author_rank: Frequent Contributor
timestamp: November 26, 2012, 10:19:25 am
content: Congratulations, you have found the cross current pulse.Due to fast voltage rise on the drain of the lower mosfet, the gate is opened via the internal Cgd for a couple of nanoseconds.Remedy: do not use logic level mosfets. The higher the Ugs for turning on the MOSFET the less problems you have.Try to limit the dv/dt on de drain.

author: Electr0nicus
author_rank: Regular Contributor
timestamp: November 26, 2012, 05:35:35 pm
content: Quote from: Kremmen on November 25, 2012, 07:53:49 amThat's actually the problem. I've cut both traces to the MOSFETs and inserted different values of resistors. Here the results:2.2Ohms: The spike amplitude is slightly reduced3.3Ohms: The spike amplitude is reduced a little bit, more than the half of that it was before. Also the drive waveform looks much smoother now.4.7Ohms: The spike on the top- MOSFET is nearly gone, instead the drive waveform of the Bottom- MOSFET looks more and more ugly the more resistance i put into the drive signals trace. The signal which should be one rectangulat pulse, looks now like three capacitor charge and discharge curves in a row.With 4.7Ohms the Power loss without any load (no connected battery) and soldered in inductor is approx. 1.4W, which is good compared to the original conditions.But this fact changes immediately when a battery is connected. The really good looking drive waveform of the Top- MOSFET without a load, looks very ugly when there is a battery connected and is charged with approx. 60W. I'll post some scope images when i get home.I also tried higher value resistors. All resistors above 10Ohms resulted in destroyed Top, or bottom Mosfets, practically instantly after enabling the charger. This was due to the fact, that those resistors smoothed out the gate drive waveform that much, that the area under the signals where both MOSFETs conducted was actually much larger.So I decided to reject the actual layout, because up to now, I've wasted many hours (7+) troubleshooting that thing and to get it work. With no reasonable success. So I'm currently relayouting the board, and will post a screenshot here, once I'm finished, to hear your opinion.Quote from: HackedFridgeMagnet on November 25, 2012, 01:36:08 pmThere actually lies the benefit of homemade pcbs. If a board doesn't work, I can toss it away and after 4-5h of work I have a new one.Your PDF Link is very helpful. If I only had known that before.Quote from: chickenHeadKnob on November 25, 2012, 08:34:14 amAfter reading HackedFridgeMagnet's linked PDF it makes sense. The traces to the gates are long, thin and inductive. In my new layout they will be 15mm max.. Shorter isn't possible, when using higher power MOSFETs, not those small ones the use in the 2A reference design.Quote from: lewis on November 25, 2012, 06:22:52 pmThis I found out myself before. I added 2 10µF caps directly near the IC, but that had little effect. Actually the oscilloscope images, where I tested using pullup/pulldown resistors on the gates of the MOSFETs, are made with that 20µF of decoupling capacitance in place.Quote from: qno on November 26, 2012, 10:19:25 amI'm afraid that that's not possible. Even in the datasheet logic- level Mosfets are recommended, because the drive voltage can be as low as 4.5V for the bottom MOSFET and -4.5V for the top MOSFET. So using non logic level MOSFETs will result a circuit that will not function at all.Cheers, Gregor

author: Electr0nicus
author_rank: Regular Contributor
timestamp: November 27, 2012, 07:23:10 am
content: I'm done relayouting the board. I've rearranged some components, so that the following open issues are met:The traces to the switching MOSFETs are shortened to a maximum length of 15mm.Both traces to the gates of BFET and TFET are the same lengthAdded gate resistorsrearranged the position of the current sharing sense resistor (CSSR), so that the trace to the CLN Pin is really short, and near the input caps.Thinkened the trace from the CSSR to the CLN Pin for lower trace resistanceCondensed the power switching section even more.reduced the area of the switch node to a minimum.But all those benefits are archieved at the expense of the length of the Buck converters sense resistors (R9) trace lengths. In this new design, I have to route these signals around the edge of the PCB to the pins of the IC. Lengths are 56mm and 63mm. I made some sort of guarding pour, routing the "cold end" of the inductor all the way up close to the IC. If this is complete nonsense please let me know!!Here is a screenshot of the pcb:Now your opinion is beeing in demand. What is good, what bad and what can be done better.Thanks, Gregor

author: Electr0nicus
author_rank: Regular Contributor
timestamp: November 27, 2012, 07:52:21 am
content: A in depth google research on the Cgd/Miller capacity phenomenon, which my circuit obviously suffers from, revealed a really interresting PDF:http://www.irf.com/technical-info/appnotes/mosfet.pdfAfter reading this PDF, it makes sense that the TFET had a really ugly drive waveform,whereas the BFET had a relatively good looking rectangular waveform.The TFET is a TPC8128, which has a Vgs(th) of -0.8 to -2.0V, which is really lowThe BFET is a PSMN8R3-40YS which has a Vgs(th) of 4V

author: HackedFridgeMagnet
author_rank: Super Contributor
timestamp: November 27, 2012, 11:03:31 am
content: Didn't occur to me before but this is I think a well respected app note on gate drivers.I can't say I understand it all.http://www.ti.com/lit/ml/slup169/slup169.pdfI'll just throw in a few thoughts, disregard if you want.The other thing is didnt one of you fets have a massive gate charge? That would be another thing that could be improved.Do you need D1? I'm not sure you don't but my understanding is the body diode of the Fet can cope with any short transients, It probably doesnt carry much current if the dead time is set correctly.I notice some of the other driver chips monitor the voltage at the node q1 and q2, I think they adjust the dead time accordingly.

author: mamalala
author_rank: Unknown
timestamp: November 27, 2012, 05:31:11 pm
content: Quote from: Electr0nicus on November 27, 2012, 07:23:10 amA few things. Between L1 and IC1 you have an quasi-orphaned area of the top GND polygon. It is only connected with three vias to the bottom GND poly. It is not connected anywhere where it would be useful.From L1 you have the poly connected to the bottom pad going upwards on the left side, connected to nothing there. This just makes a good antenna to emit noise!From R9 you have the two traces to IC1 routed at the far left side, running next to that antenna. This will very likely become problematic.Here is what i would change in regard to these things:Right at R9 change the layer for the two traces going to IC1. Route them at the bottom layer straight under D1, BFET, TFET and then change layers again to have them end up right at the proper pins of IC1. This will shorten the traces, provide more distance to the inductor, plus more distance to other signals, since it is on the bottom layer now.Reshape the poly that connects to the bottom of L1, to avoid that antenna construction. Instead, let the top GND poly float into the newly-won space due to removal of the antenna and traces from R9. That will in turn also connect to the quasi-orphaned GND area with the three vias that is currently bottom-left of IC1.Speaking of that, you also have pin 14 of that IC going to a small piece of GND poly, using two vias to have that connect to the bottom GND poly. That surely should be connected to that quasi-orphane GND area there as well then after the changes.Greetings,ChrisEdit: I also think that there should be no problem to remove the restrict area under L1 on the bottom layer. At least so far i never had any problems with having a GND plane on the bottom layer under inductors mounted on the top layer.

author: Electr0nicus
author_rank: Regular Contributor
timestamp: November 30, 2012, 06:21:35 am
content: Quote from: mamalala on November 27, 2012, 05:31:11 pmOK, I had a feeling that extending this poly on the lower pad of the inductor was a bad idea. So I removed it.Well my question now is:Is it really good to route the sense signals from R9 on the bottom- layer directly under the switch node?? Up to now, I thought this traces should be as far away from the SW- node as possible.Finally here is my new layout:Quote from: HackedFridgeMagnet on November 27, 2012, 11:03:31 amThank you very much, HackedFridgeMagnet. This PDF is very informative! The diode should actually conduct during the dead- period, where the BFet is still off, so the current from the boost converter has to flow trough the body diode of the Fet which has approx. 0.7V Vf. If I use a schottky diode parallel to this body diode, the overall efficiency of the circuit will be improved. Actually there is a note in the LTC4006's datasheet about that.Greetings Gregor

author: HackedFridgeMagnet
author_rank: Super Contributor
timestamp: November 30, 2012, 06:45:10 am
content: It is a good app note, I have read it more times than any other app note.I just got my boards back, thankfully my waveforms are good. So I am happy about that. My gate traces are actually very short, 5mm and 10mm. Because I used LFPaks and DFN packages it was easy.I didn't know it was better to have them the same length but it seems a reasonable proposition. I have counted at least 5 other mistakes on my board, and one of the mistakes was just using a DFN package, which was a bugger to solder especially as the solder mask was removed from near the pads. I guess the tolerance was too small.I might try a FAN73711 which is a high side only gate driver with a boost converter so I can use N channel fets high side.Anyone got a different recommendation?Requirements: high side only gate driver with a boost converter so I can use N channel fets high side. SOIC preferably.Low side I will use a shottky because it is for a battery charger, and I want to be sure I never conduct accidentally the battery to ground.

author: mamalala
author_rank: Unknown
timestamp: November 30, 2012, 10:48:38 am
content: Quote from: Electr0nicus on November 30, 2012, 06:21:35 amWell, at some point it's always about compromises. You could put those trace a bit more to the right, then it would be mostly GND on the top and only a small area of VIN. Also, you can turn R9 by 180° (and of course rewire it) so that the sense lines come out at the other side. Right now they come out at the bottom edge, only to run underneath R9 towards the top edge then.The two GND vias at the bottom of IC1 could be arranged horizontally, moving the upper one to the left of the lower one. That way you get some space to route these two traces there. So it would run like this at the bottom layer:From the top edge of R9, along the right side of D1, BFET and TFET, making a left-turn under R10/R11, along the bottom of the pin-row of IC1, to the two pins in question.Greetings,Chris

author: Electr0nicus
author_rank: Regular Contributor
timestamp: November 30, 2012, 01:16:05 pm
content: Quote from: HackedFridgeMagnet on November 30, 2012, 06:45:10 amMeanwhile I've also found some additional mistakes on my pcb, which maybe contributed to the gate drive problem. Not only the length of the gate drive traces is important, but also the loop area. The current flowing into the MOSFET gate has to flow back to the driver somehow. If this return path is far away from the actual drive signal's trace, then these two traces form a big loop area, which increases the trace inductance. So the goal is to minimize this loop area, which I've done in my new layout as much as possible. In my old layout the loop areas were really large.I would recommend the SOT669 (also called LFpack, PowerSO) package for power MOSFETs if possible. They are the same size as approx. SOIC8 but they have a Drain lug which is better for thermal performance.http://www.nxp.com/documents/leaflet/939775016838_LR.pdfYou can use a Mosfet for rectification with quiet conscience. It is so much more efficent. If you are afraid of the MOSFET shorting out your battery, place a fuse between charger and battery. F.e. using a 4A fuse and 16A Mosfets will be fine. Most MOSFETs can handle multiple times their rated current for a short time, and a 4A fuse will trip in microseconds when f.e. a current of 32A flows trough it. And a that short pulse will be very unlikely to destroy the mosfet. Also the battery will not be harmed by such a short pulse, even if it's over its maximum discharge current. But not knowing your particular application this is only recommendation, maybe you are using a weak battery which is not able to deliver that much current, so that the fuse can't trip in a short period of time. As I'm using a BQ78PL114 as a BMS Chip my battery- pack is protected against nearly everthing, even dead shorts.Quote from: mamalala on November 30, 2012, 10:48:38 amOK thanks very much.Yeah it's always a thing of tradeoffs. When you read the LTC4006's layout recommendations, you get the feeling that every single component should only be millimetres away from the device.It's clear, that this is not achievable for every component (Maybe when using Manhattan style)So here is my changed layout:

author: mamalala
author_rank: Unknown
timestamp: November 30, 2012, 01:58:58 pm
content: Quote from: Electr0nicus on November 30, 2012, 01:16:05 pmWell, it surely _is_ possible to put all the parts in better positions, and have shorter traces in some places. However, it would probably also mean a different geometry of the PCB itself, and using more via's to put signals on the other side of the board. For example, rotating IC1 90° clockwise, swapping the positions of BFET and TFET. Then you can move down IC1 so that the gate drive lines end up in a rather straight and short way. The VIN would then go under the TFET and extend upwards. L1 could be rotated 90° CCW and be placed directly under D1. Then the sense resistor lines would have a shorter path to IC1 at the new position.But then, you also have to move around all the circuitry that is now at the top-left, probably ending up at the middle-right instead. In short, a major redesignI found it always to be a good idea to start with the more critical switching-part of the layout, making it as compact as possible. Control lines don't care if they are a bit further apart, so the connections to those parts can be a bit longer, change PCB sides more often, etc.But then again, you may have constraints as to the shape/dimensions of the board, for example if it has to fit into a certain enclosure, etc. So yes, it's always a big "trading this for that" process.Greetings,ChrisETA: Heck, it just occurred to me that with the replacement of IC1 that i spoke of, one could rotate L1 by 180° instead, then the sense-resistor would be even closer to IC1, and thus the traces from the resistor to it even shorter. Ahh well, the joys of layout work

author: HackedFridgeMagnet
author_rank: Super Contributor
timestamp: November 30, 2012, 11:18:28 pm
content: QuoteQuoteFrom looking at your layout I would say it could be moved around a bit too. (Warning opinionated Newbie)What I did was layout all the ground connections last and used vias to the ground plane for all the returns, if there then was a direct path on the front side of the board I also used supplemented with that.I see no reason why the gate drive routes under the chip. Maybe these should routed first straight to the resistors and straight to the fets. I think the fets should be aligned in the same direction with gates near the resistors.QuoteI am using the LFPak like you, similar to PSMN012-60YS but for some strange reason that I cant remember I went for 30v versions. The specs of these things are fantastic, and so far so good.I wanted the Soic for the gate driver.

author: Electr0nicus
author_rank: Regular Contributor
timestamp: December 21, 2012, 02:14:36 pm
content: Excuse the late reply, but university exams ate up all my timeFinally the charger works.It was a combination of different problems.1. The Topmosfet.I used a TPC8128 MOSFET, which is a nightmare of MOSFET for that application. It has a total gate charge of 80nC @ -6Vgs, which results in 1.6A of current needed to switch it on within 50ns.I've calculated the maximum drive current of the LTC4006's gate drive and @ 6V it can deliver around 360mA. So that value was far to low for that MOSFET.This TPC8128 also had a very very slow fall- and turn- off time. 140ns fall time and 420ns turn off time. This is more than 10% of the LTC4006's duty cycle, so cross- conduction of the power stage was pre- programmed. Also this MOSFET has a very low Vgs(th) voltage, making it prone for turn on via the fairly large Cdg.2. The Bottommosfet (PSMN8R3-40YS):This was a nearly perfect device for the job. But it has a property which isn't very good for my application. As the LTC4006's gate drive voltage could be as low as 4.5V this MOSFETs Rds(on) shoots through the roof at 4.5V.3. The Totem- Pole drive stage:In my despair on that circuit, I decided to make a new layout with dedicated totem- pole driver circuits for every MOSFET. I used the standard BC848 and BC858 complementary transistors for that purpose. At first glance, I didn't find thing wrong using only 100mA Ice devices, because at that time, I hadn't calculated the actual drive current needed by the Top- MOSFET, I was just randomly trying different things, what's never a good idea to find a complex problem.Of course nothing worked as expected. The cross current conduction of the power stage still persisted. A current measurement of the gate drive signals of the LTC4006 revealed, that there are still large currents drawn from the LTC4006's gate drivers. This was my first acquaintance with the high dependency of the transistors hfe vs. the collector current. Because the peak current trough the C-E- path of the transistors was much higher than 100mA the hfe decreased drastically, so that the base current the LTC4006 has to deliver was very high, by what the whole purpose of that totem pole driver was inhibited.To solve those problems, I went through the following steps:1. Select a new TOP- MOSFET.I choose the SQ4431 P- Channel MOSFET. It has a relatively high Rds(on) of approx. 50mOhms @ -6V Vgs, but otherwise very excellent properties. It has only 15nC total gate charge @ -6V Vgs and very fast turn on and turn- off times. So to switch that MOSFET a current of 300mA @ -6V Vgs is needed and that's within the driving capabilities of the LTC4006.2. For the Bottom- MOSFETI selected a PSMN8R0-30YLC, which already at 4.5V has a very low Rds(on).3. For the totem pole- driver stage I selected 2A capable transistors.I built the whole thing up, using the external Totem- Pole drivers and the first time got no cross- conduction trough the power stage, and only little 12mA power consumption without a load. I hooked up my oscilloscope to the gates of the MOSFETs, and got a really clean drive waveform, with no overlapping.Although I was not entirely satisfied with the gate drive waveforms, as the top- waveform looked really good, but the bottom waveform instead looked like a capacitor charging and discharging. This was funny because the Bottom- MOSFET had nearly the same gate capacitance than the Top- Mosfet. The oscillation at the beginning of the signal is coming from measuring the signal with a BNC cable directly connected to it, without any compensation or anything. Unfortunately I only have one working oscilloscope probe.If I connect my oscilloscope probe to that signal the oscillation vanishes, but the signal still looks like a capacitor charging and discharging. I thought never mind, lets do a load test. So I hooked up some power resistors which are able to dissipate approx. 70W. The signals still looked the same like with no load (of course the duty cycle changed) but were a bit more distorted but still very good. The charger also delivered 65W constant power into the load over 5 minutes only getting slightly hot (not too hot to touch).This gave me confidence so I tried to connect the MOSFET gates directly to the LTC4006's pins. This was done via a very ugly construction of flying leads directly soldered on the pcb tracks. Many tracks and pads got separated due to many times of soldering and desoldering components during testing with the old inappropriate MOSFETs. So my PCB looked like this afterwars. (Attention!! If you are easily offended by really ugly PCBs you shouldn't look at the photo)I actually expected the worst with this construction, but the oscilloscope image, measured at maximum output power, told a different story:This is measured without any gate resistors in place.Later I made some charge tests with a actual battery pack, no problems at all.I also measured the efficiency of the charger and it was around 94% most of the time, and corresponded to the efficiency graph in the datasheet.So what's left to do, is to make a final PCB with soldermask and then that's it for that project.Although it took me many hours of frustration, however I'm glad, that I had to troubleshoot this thing. Beause I've learned very much doing so.Cheers Gregor.

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: December 22, 2012, 12:46:23 am
content: An ugly circuit that works is still better than a pretty one that doesn't. Along the same lines I was once walking with my father (as a young boy) and pointed out a remarkably ugly woman, he said "son, there is no such thing as an ugly woman!" I did not understand the multiple meanings of wisdom at the time. In hindsight it may have been better to prototype manhattan or what I call high-line air wire style - sort of a combination of dead bug and manhattan.Thank you for a comprehensive summary post, it is a forum courtesy that isn't always followed.

author: Electr0nicus
author_rank: Regular Contributor
timestamp: December 24, 2012, 05:52:52 pm
content: Thanks for your advice chickenHeadKnobOk yesterday I've made a "beautiful" version of the charger board. Took me about 7h from printing out the layout films to the finished and populated board.Etching the PCB: 1hApplying soldermask dry laminate, exposure in UV- light, developing and hardening: 4hPopulating the PCB: 2hAnd I think the result is presentable (click to enlarge):The charger PCB is actually a essential piece of a Battery Management System for a portable embedded Linux LAB- PC. Here is a image of the test setup.Left you can see a array of power resistors. Different resistor values could be tuned in via switches. Those power resistors represent the System Load, meaning the embedded Linux System.In the bottom right corner you can see the 2800mAH 14.4V Li- ION battery.This battery is connected to the Battery Management System above, which uses a TI BQ78PL114S12 BMS Chip.Right next to the BMS PCB you can see the self built TI USB/GPIO Adapter, which connects to the BMS via SMBus. Battery information can be displayed on a PC connecting it to the USB/GPIO PCB via a USB- cable.On top in the middle you can see the actual charger PCB.(click to enlarge)After all tests are completed the layout will be redone using 4 layers, so the smallest possible PCB size should be possible...With best Christmas wishesGregor

author: cwalex
author_rank: Frequent Contributor
timestamp: December 25, 2012, 04:24:39 am
content: That board looks sweet! Very nice work.

author: Electr0nicus
author_rank: Regular Contributor
timestamp: December 27, 2012, 02:30:28 pm
content: Quote from: cwalex on December 25, 2012, 04:24:39 amThanks!I can also post the documentation (when finished), if someone wants me to.Cheers Gregor

author: qno
author_rank: Frequent Contributor
timestamp: December 28, 2012, 06:54:02 pm
content: Hi Gregor,Good job, thanks for explaining what you all did to come to the satisfacionary results.Did you do some high temperature tests?My experience is that wat works at a normal operating temperature of 50°C can go wrong @ 80 or 90°C.Thanks

author: jfmateos
author_rank: Newbie
timestamp: February 12, 2013, 05:44:18 pm
content: Hi electronicus,I have a question about LTC4006... powering the load through the lipo battery (the power adapter is unplugged), does the LTC4006 switch off the power when the battery voltage drops below a configurable level?It would be nice to look over your project´s documentation.Congratulations.

author: yann4905
author_rank: Contributor
timestamp: October 31, 2014, 09:46:16 pm
content: Hi Elect0nicus,I know this is an old topic, but I'dlike to know if you would eventually share your documentation about your charger?Best regards.

author: albertomaria
author_rank: Newbie
timestamp: May 18, 2017, 06:06:23 pm
content: hello, I know it's way far in the time, but do you still have this project in hands? Is there any possibility to share your ressources? Thanks in advance. Alberto

author: VitaliyK
author_rank: Newbie
timestamp: October 17, 2017, 03:12:12 pm
content: Would it be possible to post or send me your CAD files for LTC4006 board. Hope they are in Eagle format.