MIPS Goes Open Source - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: December 17, 2018, 08:12:30 pm
content: OMG,ithappenedQuote

author: legacy
author_rank: Super Contributor
timestamp: December 17, 2018, 08:16:58 pm
content: Wonder if this might result in a renewed interest in MIPS in general?

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 17, 2018, 08:31:06 pm
content: Great news!I was wary of the MIPS buyout and am glad they took this decision which will help prevent MIPS from dying. As I said earlier, Wave Computing certainly didn't look like it had the shoulders to give MIPS a sustainable future on its own.

author: ataradov
author_rank: Super Contributor
timestamp: December 17, 2018, 08:52:31 pm
content: Nope. There is really no point with RISC-V out there. It may prolong the death somewhat, but I doubt MIPS is ever coming back strong.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 17, 2018, 08:56:36 pm
content: I think they did it because there was no real way of profiting from MIPS. The only path is to oblivion.I don't know about other vendors, but since Microchip bought Atmel, they moved their focus to SAM. I don't know if they are coming along with this, but they even wanted to rename SAMs into PIC32C, and even SAMs used in their new programming tools are marked as PIC32C. This doesn't look like Microchip is sticking with MIPS as the article seems to imply.

author: brucehoult
author_rank: Super Contributor
timestamp: December 18, 2018, 02:21:02 am
content: Great news! A bit of open-source competition will be good for everyone.I really like the new nanoMIPS ISA (or at least encoding, with 16, 32, and 48 bit instructions, including instructions with embedded 32 bit literals) they introduced in the I7200 in May:https://www.anandtech.com/show/12699/mips-announces-i7200-32bit-cpu-with-new-nanomips-isaHowever I hear the MIPS compiler team was laid off before they could upstream any binutils or gcc support for nanoMIPS. They apparently sent a message to the mailing list saying they had patches ... and then they were gone.They also laid off a half dozen (?) person debug tools team who I happen to know are now working on RISC-V stuff.I just hope they haven't left this a year or three too late.

author: brucehoult
author_rank: Super Contributor
timestamp: December 18, 2018, 02:36:29 am
content: Looking at the announcement, it's including "the open source version" of MIPS r6 (whatever that means!) and microMIPS, but not nanoMIPS.MIPS r6 is a very nice improvement over earlier MIPS versions, providing branches without delay slot, branch on comparison of two registers (like RISC-V) and some other good stuff. MicroMIPS is pretty meh though and doesn't have anywhere near as good code density as Thumb2 or RISC-V, let alone what nanoMIPS is claimed to provide.

author: legacy
author_rank: Super Contributor
timestamp: December 18, 2018, 12:26:03 pm
content: I happen to know a couple of guys inside the old MIPS company when they were in business. I got a printed copy of the R10K (mips-4) user manual, but I am still looking for R12K, R14K and R16K (mips-5).R10, R12, and R14K were used in the SGI IP30 workstation, which on DTB we are still supporting for Linux (and recently for XINU, but it's extremely experimental).Hope someone will release these UMs!

author: NorthGuy
author_rank: Super Contributor
timestamp: December 18, 2018, 06:43:50 pm
content: Quote from: brucehoult on December 18, 2018, 02:36:29 amThe branch on comparison (such as BEQ) was in the MIPS from the beginning (or close to the beginning). It would be hard to get by without it when there's no flags. Even their unconditional branch is built as "BEQ zero,zero,target".

author: David Hess
author_rank: Super Contributor
timestamp: December 18, 2018, 07:58:28 pm
content: Are they going to sue people which implement their ISA over patent infringement again?Open source does not mean free of intellectual property encumbrance.

author: andersm
author_rank: Super Contributor
timestamp: December 18, 2018, 09:19:50 pm
content: Patent issues are covered in the EETimes article.

author: andersm
author_rank: Super Contributor
timestamp: December 18, 2018, 09:43:45 pm
content: Quote from: brucehoult on December 18, 2018, 02:36:29 amIn my own code size tests I did some years ago, microMIPS generally produced smaller code than Thumb-2. I used the SQLite3 amalgamated source, since it's a single, large, self-contained source file that was simple to build. The test wasn't very scientific, and the output size difference varied rather wildly with optimization level, but apart from -O0 the result was in favour of microMIPS. I didn't spend the time analyzing where the difference came from, but I would say they are at least comparable.

author: brucehoult
author_rank: Super Contributor
timestamp: December 19, 2018, 10:24:45 am
content: Quote from: NorthGuy on December 18, 2018, 06:43:50 pmI mean ordered comparison.You can get by without condition codes if you have even as much as "Set Register to a LT b" and "Branch if register is zero" (or nonzero). Which is exactly what you did on MIPS until recently.

author: legacy
author_rank: Super Contributor
timestamp: December 19, 2018, 11:27:31 am
content: Quote from: David Hess on December 18, 2018, 07:58:28 pmit happened in 2004, it should be passed

author: NorthGuy
author_rank: Super Contributor
timestamp: December 19, 2018, 07:25:28 pm
content: Quote from: brucehoult on December 19, 2018, 10:24:45 amWhat is "ordered comparison"?

author: brucehoult
author_rank: Super Contributor
timestamp: December 20, 2018, 01:29:51 am
content: Quote from: NorthGuy on December 19, 2018, 07:25:28 pmIt is when you compare two registers and are interested in numeric ordering, not equality.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 20, 2018, 02:24:50 am
content: Quote from: brucehoult on December 20, 2018, 01:29:51 amI see. They didn't have this in older MIPS. Nice addition. It's always nice when you can do something with one instruction which required two instructions before.I'm afraid it may be too late for improvements

author: brucehoult
author_rank: Super Contributor
timestamp: December 20, 2018, 03:19:28 am
content: Quote from: NorthGuy on December 20, 2018, 02:24:50 amThey added branch on ordered comparison of two registers (with no delay slot!) in MIPS r6 in 2014.As I said in the original message.

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2018, 11:05:21 am
content: can you give an example of these "ordered comparisons"?

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2018, 11:27:37 am
content: Saint Google says it's for FloatingPoint "An ordered comparison checks if neither operand is NaN. Conversely, an unordered comparison checks if either operand is a NaN".NaN => Not a Number => FloatingPoint stuff

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2018, 11:31:00 am
content: LOL, digging into gcc error messages (-Werror=extra), I find this"error: ordered comparison of pointer with integer zero"

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2018, 11:48:24 am
content: Ordered means that neither operand is a NaN.Unordered means that either operand may be a NaN.In brief, fcmp&predicates does this:Ordered comparison expects both operands to be numbers.Unordered comparison returns true if one of the operands is NaN.I am working with FixedPoint numbers, I have never used/implemented anything similar.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 20, 2018, 03:57:07 pm
content: Quote from: legacy on December 20, 2018, 11:48:24 amI've got confused the same way. "ordered" and "unordered" are standard terms for floats. But MIPS branches work with integers. What Bruce meant are comparisons other than equality/inequality, such as (a > b) or (a < b), as opposed to (a == b) or (a != b).

author: legacy
author_rank: Super Contributor
timestamp: December 20, 2018, 04:32:26 pm
content: Code:* Equality* [==] teq equal* [!=] tne not equal** Relational* [<=] tle less equal* [< ] tlt less than* [>=] tge greater equal* [> ] tgt greater than

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: December 20, 2018, 07:52:50 pm
content: Sounds like it's not actually Open Source, just royalty free :QuoteNo doubt there will be an upsell to commercial paid-for proprietary stuff, e.g. for Waves special AI extensions etc.