Anyone try repeating this guys genetically evolving FPGA experiment? - Page 1
Forum section: electronics / general

author: cur8xgo
author_rank: Regular Contributor
timestamp: June 06, 2019, 04:13:31 pm
content: Always wanted to try this...what would happen if you got 100 of these in parallel?What would it cost in 2019 dollars to repeat what this guy was doing?https://www.damninteresting.com/on-the-origin-of-circuits/

author: ralphrmartin
author_rank: Frequent Contributor
timestamp: June 06, 2019, 05:12:24 pm
content: There's quite a field of research into evolving hardware. Seehttps://en.wikipedia.org/wiki/Evolvable_hardware

author: Mechatrommer
author_rank: Super Contributor
timestamp: June 06, 2019, 06:44:35 pm
content: Quote from: cur8xgo on June 06, 2019, 04:13:31 pmnot that expensive. maybe around $100-200+ in ebay or amazon. just google Evolutionary algorithm book. buy one and it should be a good 10 years reading. maybe 1-3 years if you are really persistent.maybe this can be a start...http://www.geatbx.com/download/GEATbx_Intro_Algorithmen_v38.pdf

author: cur8xgo
author_rank: Regular Contributor
timestamp: June 06, 2019, 07:28:14 pm
content: Quote from: Mechatrommer on June 06, 2019, 06:44:35 pmnice thanks will be reading that at some pointis the $100 to $200 mostly for the programmer?Ive done lots of MCU stuff but never done FPGA development

author: NorthGuy
author_rank: Super Contributor
timestamp: June 06, 2019, 09:09:21 pm
content: Quote from: cur8xgo on June 06, 2019, 04:13:31 pmNot counting your working hours, you only need one rather small FPGA. You can buy an FPGA board for well under $100.

author: Mechatrommer
author_rank: Super Contributor
timestamp: June 06, 2019, 10:51:30 pm
content: Quote from: cur8xgo on June 06, 2019, 07:28:14 pmfor book only to understand how its done. once you understand it, i think you will know what hardware you will need. having all the hardwares without understanding it is useless. please understand from the article you provided, the evolved program only works on FPGA under test, cant even work on other FPGA even the same exact model. so if you have 1000 products, you will need to evolve all of them 4 millions times, not to mention time needed to evolve one chip x number of chips.btw this proved you need some intelligence to evolve something to something useful, random algorithm cant. so nature must be more intelligent, but how cant it exist? some "intelligence" must exists creating all this<see my signature below>

author: cur8xgo
author_rank: Regular Contributor
timestamp: June 06, 2019, 11:12:37 pm
content: Quote from: Mechatrommer on June 06, 2019, 10:51:30 pmThis would be just for fun, I don't have a product idea for it. I'd like to do what he did, recognizing the sound, then see how far I can take it to recognize other things.The part I think is the most interesting is how the chip is wired strangely inside..with unconnected gates that are critical to it working. So..what if you attach inputs like photodiodes or other things, and those too, get exploited in unusual ways to solve problems?For instance a question could be asked "Is there more information available from a point detector like a photodiode than just magnitude?" Could you recognize different shapes or something? Maybe if you connect a photodiode in a very high-bandwidth way to an array of FPGAs, they figure out how to extract that info.Similarly for maybe a microphone..can you tell what direction a sound is coming from using a single microphone?Of course problems like this might get trained to only work in the exact environment they were trained in. Still would be fascinating to "pop the hood" and see how the FPGA is wired once something works.My next question would be, how has the scale of things changed since that guys 2009 article? For the same price can his setup be increased by 10 times the number of gates? 1000000 times? Where do things standCan you somehow create an image from a single non-moving photodiode?"..seems at first glance its impossible. B

author: NorthGuy
author_rank: Super Contributor
timestamp: June 07, 2019, 03:54:59 am
content: Quote from: cur8xgo on June 06, 2019, 11:12:37 pmYou can get FPGAs up to 500,000 logic cells before it starts getting very expensive.

author: Mechatrommer
author_rank: Super Contributor
timestamp: June 07, 2019, 05:27:55 am
content: Quote from: cur8xgo on June 06, 2019, 11:12:37 pmyou have to ask him or the people in the field.Quote from: cur8xgo on June 06, 2019, 11:12:37 pmit starts with the algorithm, if you know what directive for the algorithm, and selection criterias, maybe you will know how many gates required. maybe the simplest solution if you want to replicate his experiment is ask the code from him since he has not made it open source, and ask a brief explanation how it works. if you ask the details, it will probably same explanation as the mentioned books above.

author: Berni
author_rank: Super Contributor
timestamp: June 07, 2019, 06:46:26 am
content: Well you can buy a 100 tiny FPGA chips for about $120https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40UL1K-SWG16ITR1K/220-2228-1-ND/9764642And that's at expensive Digikey pricing, At 100 you could probably get a nice deal from a Lattice distributor.It is quite an interesting experiment of what hidden secrets the AI can find inside the chip. It was obviously mostly running the chip in weird metastable states where cross-talk from the interconnect buses can cause interactions between screamingly unconnected gates. But obviously these things are not characterized by the manufacturer so when you load this into a different FPGA of the same partnumber it stops working because the amount of cross-talk and the gate speed is ever so slightly different. Heck even warming the FPGA up by 30°C would probably make it stop working because that would slightly change the characteristics of the gates inside.I think how he did it, was just have the learning algorithm flip bits in the FPGAs configuration bitstream. On a tiny FPGA this is only a few KB, he likely also locked down the bits that configure other parts like the IO pins so that the genetic algorithm would only mess with the pool of 100 gates that its supposed to mess with.And yes we can now certainly scale up the experiment to 1 000 000 gates, but the problem is that this would likely slow down the learning process to taking years, centuries, maybe even milenia to complete. It massively raises the number of possible states that the genetic algorithm has to roam trough, so it will have to do a lot of trial and error to even figure out how to get the input to affect the output. Once it has figured that out, it then wants to improve this bad solution by still flipping random bits around. In such a large number of gates it will most of the time be flipping gates that are far away and have no effect on the output result, this will likely give you lots of generations of essentially identically performing solutions. Genetic algorithms aren't really smart at all, they simply stumble into solutions by accident trough pure trial and error.

author: NorthGuy
author_rank: Super Contributor
timestamp: June 07, 2019, 01:53:43 pm
content: Quote from: Berni on June 07, 2019, 06:46:26 amI don't think metastability would be a working mechanism - it's rather unpredictable. Even if metastability developed in some individuals, it would be like a genetic disease and would be eliminated fast.Quote from: Berni on June 07, 2019, 06:46:26 amI also think it's a big problem. If the temperature varied in his tests, then his creatures had to adapt to it by being stable over temperature range. Judging by my own designs, variations in temperature can produce significant delays - 100-200 ps. For that reason, I don't 100% believe his results.Quote from: Berni on June 07, 2019, 06:46:26 amI think more genes would mean faster evolution. Of course, it'd be very slow at first. I would expect that most of the "original" designs would produce stable outputs which never change. You would be lucky to get anything changing. But, once you get some changes, you can apply selection criteria, and the ball gets rolling. It certainly takes many generations to form some sort of inheritable structures.If you can program and test one creature in 1s, and your population size is 1000, then you can do 4 generations per hour, roughly 100 generations a day. According to the original parer, you should expect some sort of progress within few months. Sounds reasonable. Although, with higher population size, the progress will be too slow - may take years.Quote from: Berni on June 07, 2019, 06:46:26 amVery unlikely. There's also recombination. Even with severe inbreeding, there's no two individuals which would be completely the same.Quote from: Berni on June 07, 2019, 06:46:26 amSelection is actually very "smart", and getting smarter as complexity increases. For example, capitalism is driven by selection, while communism is driven by planning. You know the results.

author: Berni
author_rank: Super Contributor
timestamp: June 07, 2019, 04:35:55 pm
content: Well yes once you have a few breeds of these 1 000 000 gate designs then the genetic algorithm can start combining them in different ways and get progress, its getting there that is the problem. Even when it finds a way for the input to affect the output, it will suddenly have this breed dominate because doing something is better than doing nothing. Then it will take again quite a while for random mutations to make this basic breed to do something different to the output, again taking many many generations to produce some sort of competing breed before crossbreeding can get going. But there are ways around it like incremental learning, Maybe just give it 100 gates to start with and figure out how to do things, then give it 1000 gates, then 10 000 gates... by the time you get to a 1 000 000 there already are lots of diverse breeds to criss cross together.Oh and metastable states can actually be surprisingly predictable. Especially when a large block of it is being clocked from the same signal. I had an example of a parallel bus to a CPLD garbling only certain values perfectly repeatably. To the point where i thought there was a problem in the code. It actually ended up being that enough lines on the bus needed to toggle simultaneously to cause a glitch in another line(Much of it was from ground bounce due to using a ribbon cable).The researcher has likely been using only one FPGA to run all the tests on since he did comment that loading the same thing into a another FPGA of the same type made it not work. Also since it was likely running 24/7 inside a typical room means that the chips temperature has likely stayed within 5°C. So using these sensitive states was fair game. You could probably discourage the genetic algorithm from using these solutions if you had a bank of 10 FPGAs to run the test and spread your bitstream creatures randomly across them. That way if any of them does start using weird metastable states means it will fail horribly as soon as its assigned to a different FPGA.It sounds like a cool project to try myself, but i don't really want to figure out how to correctly manipulate bits in configuration bitstreams on more modern FPGAs since they tend to be big, proprietary and non documented.

author: NorthGuy
author_rank: Super Contributor
timestamp: June 07, 2019, 05:04:13 pm
content: Of course, it'll be very slow at the beginning, but once it gets structured, it'll get faster. For example, once you have a structure, the mutations which destroy the existing structure will be lethal. Thus, when something starts working, it won't take long to make it more sustainable. However, the creation of the original structure may take thousands of generations to form. The beauty of this thing is that it will create a structure where none existed, all by itself. If it is all true, of course.At least you give it breeding and inheritance from the start. Real life didn't even have that, which made the process extremely slow, but eventually it started anyway.

author: cur8xgo
author_rank: Regular Contributor
timestamp: June 08, 2019, 12:59:15 am
content: Okay so hear me out, I know I mentioned this a bit, but now I am really wondering.So something I'd want to try is to see if I can get the evolving FPGA to do something which I can't explain. For instance, take a cheap thermopile sensor, and somehow, generate an image from it.Yes yes, I realize that seems impossible. But if you think about it, those photons hit the sensor, maybe there is some unknown way to generate an image from it.To train it very selectively, you can copy what that guy did. Have a binary training set where you setup two "thermal" posters in front of the sensor that would look identical if you can only sense average magnitude but which are in fact different in that different areas (opposite?) are emitting. Like a black and white checkerboard but thermal and where the square "colors" change. Etc.etc..Anyways..lets say you try this, and it fails. Okay, so then move up a notch. Say you mount the single sensor on a motor so its spinning in a circle (still facing your target). Maybe then the FPGA can do it.Or..make it two or three sensors.Etc..etc..And yes of course you may end up evolving something that is environment specific and is not really discriminating between the signals in the way you think it is, and cant go up in resolution or what not.But thats just part of the fun. Would be fascinating to see what FPGA's could evolve to detect from simple sensors. Microphones, photodiodes, vibration, temperature, pressure..etc..etc..Why is it $100? I can't just get an FPGA and some way to program it for much less? No FPGA development kits for $10 or what not?

author: OwO
author_rank: Super Contributor
timestamp: June 08, 2019, 02:50:00 am
content: The laws of physics still apply. Maybe with lots of sensors and random movements you could get an image.The hardware is cheap. You can easily make a Spartan 6 LX9 board and at $4/chip you can make a 4-chip board that fits into 10x10cm for maybe $50 total. The Spartan 6 is also one of the very few FPGAs with reverse engineered bitstream format.

author: NorthGuy
author_rank: Super Contributor
timestamp: June 08, 2019, 04:15:49 pm
content: Quote from: cur8xgo on June 08, 2019, 12:59:15 amOr perhaps millions of sensors. Put them in a rectangular grid, add some optics ...

author: cur8xgo
author_rank: Regular Contributor
timestamp: June 09, 2019, 05:49:52 pm
content: Quote from: OwO on June 08, 2019, 02:50:00 amThanks that is now on my shopping list. Why is the reverse engineered bitstream format important here? Is it so I can very rapidly modify the FPGA during the evolution without having to use its designer development environment?

author: NorthGuy
author_rank: Super Contributor
timestamp: June 09, 2019, 06:05:27 pm
content: Quote from: cur8xgo on June 09, 2019, 05:49:52 pmModifying bitstreams is the only option whether you re-program the whole FPGA or a local area.The tools will not let you create a design which doesn't make any sense from their viewpoint. Even if they could, it's at least several minutes to generate a bitstream, most likely much longer.

author: Berni
author_rank: Super Contributor
timestamp: June 09, 2019, 06:08:06 pm
content: Well one thing is that compilation in a IDE takes way way more time than it the time it takes to load a new bitstream into a FPGA. But even then the vendors tools are not really meant for letting you route individual connections between logic blocks. Yes you can stick a logic block into your verilog/vhdl code and wire it up however you want, but the compiler will choose a different block every time and route the connections to it differently every time. They do allow you to freeze a area of an FPGA to prevent the compiler messing up the timings, but that means you also can't rewire that part.But a bitstream image for a FPGA is essentially the raw bits that flip all the routing switches and set up the logic block configurations. This allows you to flip individual routing muxes in the fabric without upsetting anything else. But bitstreams are pretty large so you don't want to have the genetic algorithm also figure out how to make a valid bitstream file that actually boots successfully. Ideally you would make a basic design in the IDE, compile it into a working btstream and then choose an area of the FPGA that is allows to mutate, making sure it has all the required IO signals passing trough it. This brings down the genetically mutating mass of bits down to under a kilobyte as opposed to potentially megabytes.Because modern FPGAs are so big you could probably run 100 or even 1000 of these experiments in a single chip. Making sure each one is in its own area surrounded by dead unused fabric and making sure that the AI is not allowed to connect onto any of the long distance routing buses. Since the genetic creature ends up living on a different part of the chip each time would also discourage the use of these metastable state designs as those would break as soon as they run on another part of the FPGA.

author: cur8xgo
author_rank: Regular Contributor
timestamp: June 09, 2019, 08:57:44 pm
content: Quote from: Berni on June 09, 2019, 06:08:06 pmThanks this is helpful.I'm very used to embedded workflow with microcontrollers but FPGA is all new to me.I'm really excited about this. What a fun experiment this will be. I've been wanting to do this for years. Plus wouldnt be bad to get some FPGA experience and this will certainly qualify as that

author: rstofer
author_rank: Super Contributor
timestamp: July 14, 2019, 03:45:43 pm
content: Quote from: NorthGuy on June 06, 2019, 09:09:21 pmOr, buy a modest board and run hundreds of experiments in parallel. No doubt there will be some interaction but that's ok. It's all part of the evolution.Cellular automata is a similar idea (a very small subset of the evolution idea) and these fit naturally into an FPGA. Each cell sources and consumes data from it's neighbors. A trivial example might be Conway's Life algorithm:https://en.wikipedia.org/wiki/Conway%27s_Game_of_LifeNeural networks is also a similar idea and these too fit into FPGAs, albeit larger chips. 3Blue1Brown has a couple of videos on using neural networks to recognize handwritten digits. These really do expect a snowstorm in New York because of a Butterfly in China flying south instead of north (chaos theory).

author: iMo
author_rank: Super Contributor
timestamp: July 14, 2019, 04:56:29 pm
content: The today's FPGAs are designed explicitly for synchronous operation (clocked).For asynchronous designs a new FPGA devices have to be created.Those could be much better candidates for those evolvable hardware experiments, imho.https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-468.pdf

author: Berni
author_rank: Super Contributor
timestamp: July 14, 2019, 06:28:00 pm
content: Modern FPGAs are certainly capable of doing asynchronous circuitry.The only tricky part is that the way asynchronous logic transitions from one state to another is not really designed for. You can make a asynchronous 7 segment decoder in a FPGA just fine and similar asynchronous logic is used to decide on transitions in state machines. These sort of asynchronous blocks are designed to have a given state put on its inputs, these states propagate trough the logic and result in a given output state. The issue is that during that propagation the outputs become undefined and might flip between states randomly, but since FPGA designs tend to also use synchronous designs around it means that this weird undetermined state doesn't matter as long as the circuitry settles down by the time the next clock edge comes around.The kind of designs that are indeed not easily implemented on a FPGA is a asynchronous logic circuit with memory. Once you start forming feedback loops to create memory flipflops inside the logic you run the risk of the memory blocks being flipped at random by the undetermined states during transition. So to make such a circuit behave reliability one would need to take care in designing the propagation delay of every path to make sure the transitions of state happen in a nice controlled way and FPGA tools as they are today don't make any attempt in doing it. Why that is so i have no idea. Perhaps its because digital was historically done this way, perhaps its too unreliable to trust propagation delays of logic, maybe there is no performance or transistor count benefit to doing it... etcBut a AI that is running its program on the same FPGA chip on the same area, at roughly the same temperature can design these just fine because the chip has consistent enough propagation delays. Id assume that if you forced it to run on different FPGAs and FPGA areas then these weird unstable designs would die off and it would end up making a more traditional synchronous design that works reliably.

author: NorthGuy
author_rank: Super Contributor
timestamp: July 15, 2019, 12:50:23 am
content: Quote from: Berni on July 14, 2019, 06:28:00 pmYou can design combinatorial logic to avoid any glitchy switching, or you can even design logic which uses glitches on purpose. There's no tools for this, so it's not very easy, or practical, but it's certainly possible.

author: Mr. Scram
author_rank: Super Contributor
timestamp: July 15, 2019, 01:05:29 am
content: I've always loved that story. It's a modern iteration of the genie that gives you what you wish for, but not what you wanted or needed. Maliciously compliant technology.

author: iMo
author_rank: Super Contributor
timestamp: July 15, 2019, 06:45:27 pm
content: Field Programmable Quantum Gate Array would certainly helphttps://en.wikipedia.org/wiki/Quantum_logic_gate