Poor QC on JLCPCB 4L boards - Page 1
Forum section: electronics / general

author: mon2
author_rank: Frequent Contributor
timestamp: September 27, 2024, 08:05:44 pm
content: Has the quality of the PCBs gone to a newer low at JLCPCB? On a received batch of 4L boards, had a fallout of a number of boards after the PCBA (done in-house). Most of our PCIe adapters enumerated fine. Wanted to focus on the non-working boards this afternoon.The Vcc (3v3) PCIe finger trace was not reaching our 1v5 LDO that is onboard. The trace from the PCIe finger was not reaching the Vin of the 1v5 LDO.Wasted a great deal of time in this review. Fluxed and reflowed the PCIe controller (2 times) using our automated Seamark BGA rework station. No dice.After manually wiring the PCIe 3v3 finger direct to the Vin of the 1v5 LDO that is required to power the PCIe controller, only then does the board now work 100%.That is just crap if the board was truly 100% tested. Needless to say, will consider working with other PCB shops after this experience.Has anyone else noticed the lower quality standards at JLCPCB?

author: thm_w
author_rank: Super Contributor
timestamp: September 27, 2024, 08:32:32 pm
content: - Post photos- Report issue and photos to JLCPCB and let us know what they decideFor 2 layer 50pc or more you must choose "flying probe test". But for 4 layer they claim always 100% tested.Its been reported that testing has been missed in some cases. Again, we'd need some microscope photos of the pads to know for sure.https://www.eevblog.com/forum/manufacture/jlcpcb-is-amazing-but-do-they-really-e-test/https://www.eevblog.com/forum/manufacture/jlcpcb-bbt-(not)/

author: mon2
author_rank: Frequent Contributor
timestamp: September 27, 2024, 08:44:33 pm
content: Issue is down to a blown via that feeds the LDO Vin. Will do with the pics. The chat with our support claims these 4L boards were 100% e-tested.Now very concerned about the 6L and other 4L boards that are in the queue to be assembled. Can they be trusted at all??

author: langwadt
author_rank: Super Contributor
timestamp: September 27, 2024, 09:06:04 pm
content: Quote from: mon2 on September 27, 2024, 08:44:33 pmmaybe it was tested, but marginal so first time it saw the (much larger I assume) current feeding the LDO it blew

author: mon2
author_rank: Frequent Contributor
timestamp: September 27, 2024, 09:16:26 pm
content: See attached.Each review is of the via that feeds to the local 1v5 SOT223 LDO (3v3 input from PCIe fingers) to 1v5 for the PCIe core.This same via does not reach to the 3v3 pcb plane that is feeding the other circuits @ 3v3 fine (confirmed).You are suspecting in-rush current blew out this via? We have other PCBs from this same batch that are testing fine.

author: Smokey
author_rank: Super Contributor
timestamp: September 27, 2024, 09:29:03 pm
content: Here is a thought. I have no idea if this is actually what's going on, but it's possible.If you made a card edge connector interface by drawing traces to the edge of the board and then removing all the solder mask at the edge of the board over those traces, I bet they don't show up as pads in the eTest software so the flying leads didn't check continuity over those traces.That's not an excuse for broken vias, but if it's repeatably the same via, there might be some reason why it's broken that may be a manufacturing problem or a design problem. The drill looks pretty centered.

author: thm_w
author_rank: Super Contributor
timestamp: September 27, 2024, 09:30:08 pm
content: Do you have any unpopulated PCBs left to see if the pads were e-tested with probes (have marks on them)?

author: mon2
author_rank: Frequent Contributor
timestamp: September 27, 2024, 09:58:34 pm
content: We do not have bare pcbs in the building from this batch. So far, 2 assembled boards show exactly the same fault. Have started a discussion with JLCPCB to better understand if this exact via was even tested. In hindsight, discovered the fault of the 2nd board in seconds after the initial review but really concerned about the many other batches of bare boards from pending projects which are 4L and 6L. I do know that they are using other factories - not sure if they are owned by JLCPCB or not but overall, the quality and appearance has been very good. Not as good as the larger firms like Suntak / Tiefa / Yaxinda / Kingford and others but then again, JLCPCB is able to supply with a much shorter lead time and at fair pricing. Just this e-test failure is a thorn. About to travel to HK for the pending electronic fairs and will scout for other proto shops. There are many 'front' companies that just have a shiny website and work with random pcb factories behind the scenes. Trying to avoid those.Had a lengthy chat with our PCB designer and he has confirmed that this via is not a 'bicycle wheel spoked fanout' to the copper plane so the in-rush current is not the fault here, if that was of concern. It should have been a solid copper connect to the via insert. Regret that we do not have an in-house x-ray machine and do not plan to purchase one.

author: langwadt
author_rank: Super Contributor
timestamp: September 27, 2024, 10:05:39 pm
content: Quote from: mon2 on September 27, 2024, 09:16:26 pmI mean, I don't know if e-test would necessarily detect a via that hasn't been plated properly so it has electric connection but can't carry much current

author: Smokey
author_rank: Super Contributor
timestamp: September 27, 2024, 11:30:27 pm
content: Quote from: langwadt on September 27, 2024, 10:05:39 pm... my intuition says that if there was a via plating problem, it would not always be the same via (and only that via).If you didn't do this up front (I always do this up front with JLCPCB and PCBWay, etc), request to see the actual production gerbers they used. See if they made a change from your design files to that via. They do that sometimes.

author: mon2
author_rank: Frequent Contributor
timestamp: September 27, 2024, 11:52:08 pm
content: QuoteExcellent idea. Will do.Thanks to everyone that replied. Perhaps the law of averages but truly thought that as we are not using the lowest cost PCB vendor in the industry so expected perfection every time. Our designs are only getting more complex with WLCSP devices and most future layouts will be with blind and buried vias, HDI designs so proper QC is critical.

author: langwadt
author_rank: Super Contributor
timestamp: September 28, 2024, 12:26:16 am
content: Quote from: mon2 on September 27, 2024, 11:52:08 pmI suspect +4 layer HDI PCBs are generally done to higher standard than dirt cheap common 2/4 layer

author: thm_w
author_rank: Super Contributor
timestamp: September 28, 2024, 12:45:09 am
content: Quote from: mon2 on September 27, 2024, 11:52:08 pmJLC is dirt cheap, not sure why your expectations are so high IMO.

author: schmitt trigger
author_rank: Super Contributor
timestamp: September 28, 2024, 01:03:38 am
content: An excellent advice I once received; after analyzing some failures that I got from a different vendor.For the current carrying tracks, always utilize redundant vias.

author: Chalcogenide
author_rank: Regular Contributor
timestamp: September 28, 2024, 06:30:30 am
content: You can pay an extra and get 4-wire Kelvin Test as opposed to the usual flying probe test, which would most likely catch marginal connections on the PCB.

author: mtwieg
author_rank: Frequent Contributor
timestamp: September 28, 2024, 01:24:03 pm
content: Do you know specifically where the connection is broken? Is the issue insufficient wall plating in the via? Or is it that one or more specific traces doesn't connect to the via (breakout)? External photos won't tell you anything, but some more careful continuity measurements might reveal something (for example if there's no continuity between opposite ends of the via, that means it's a plating issue).Did you specify anything about plating thickness or breakout when ordering? Anything about IPC 6012 class?

author: mon2
author_rank: Frequent Contributor
timestamp: September 28, 2024, 02:00:51 pm
content: Will check on the plating thickness with our PCB designer but fairly sure they were left as defaults.Most of the batch of PCBs and others to date have been fine.On 2 of the boards, so far, this exact via is not mating to the PCIe 3v3 power plane. The top of this via conducts to the bottom side of the same via. Confirmed on both non-working boards. For now, the only work around is to steal the same 3v3 power from a nearby SOIC and feed onto this Vin pin of the LDO.

author: dotman852
author_rank: Newbie
timestamp: September 28, 2024, 05:29:58 pm
content: Hi Folks...... I am the PCB designer for Mon2's subject PCB..... The via in question is a 40 mil pad with a 20 mil platedthrough hole to be connected to the 3.3V power plane on layer 3 of the 4 layer board. This connection to the powerplane is a direct connect. i.e - no spokes for thermal relief. The Saturn PCB calculator gives a steady state current drawcapability of 1.25A with a 3°C temperature rise over ambient. I seriously doubt the inrush current would "fry" the via. I had Mon2 check continuity from the component side to the solder side of the via in question - and there is continuity. So the via has been plated through, there is just no connection to the power plane. Not sure how this could occur....Isuspect some dirt or contamination was present during the exposure for the 2 defective PCBs? All the other assembled boards work perfectly and restoring the regulator source voltage using a wire for the 2 defects restores proper operation. Hopefully this is a rare event ( from ANY PCB board house ).

author: glenenglish
author_rank: Frequent Contributor
timestamp: September 28, 2024, 11:25:42 pm
content: Please paste your (zipped up) gerbers so we can have a look at the pad-trace connections etcMost failures come from not using teardrops for narrow traces hitting the vias.

author: JLCPCB Official
author_rank: Regular Contributor
timestamp: September 29, 2024, 11:16:02 am
content: Hello,Thank you for your feedback, and we are sorry for the issues with your recent batch of PCBs. At JLCPCB, we take quality very seriously. Could you provide your order#? Or, you can directly submit a quality complaint on our website. We will thoroughly investigate the issue for you, and if the issue is casued by us, we will take the responsibility.Regarding testing at JLCPCB:At JLCPCB, all PCBs undergo comprehensive AOI(Automated Optical Inspection) to ensure quality. AOI detects any breaks or imperfections in traces. PCBs tested with AOI achieve a quality rate of 99% or higher.Flying Probe Test: This is the final checkpoint for circuit continuity. It can test for open and short circuits.- Full Test: 100% pass rate, but is slower and incurs a fee due to it is time-consuming.- Random Test: Free of charge, ensuring a minimum pass rate of 99%.E-test Fixture: Provides rapid testing and is suitable for mass production, although it requires a high material cost.For any advice or problems , please feel free to contact us , support@jlcpcb.com

author: mon2
author_rank: Frequent Contributor
timestamp: September 30, 2024, 03:40:46 pm
content: Updates:1) Found another 2-up panel and both circuits on this panel are also defective at the same via.2) Total of 4 circuits have been found with the same defect.3) Have an open complaint against this order with JLCPCB as of this morning.4) For this order # W202309020200248 - can the factory confirm ifEACH PCBof this order was 100% E-tested? If not, and only a sample batch of PCBs are tested then there is a misunderstanding of the ordering system. In the past with other PCB vendors, when we have paid for E-testing, we had each PCB 100% E-tested. Please advise if this is the same with JLCPCB.

author: mon2
author_rank: Frequent Contributor
timestamp: September 30, 2024, 03:51:21 pm
content: The submitted gerbers have been compared to the JLCPCB working gerbers and they both match. This via was not modified for production.Order details are attached.

author: Smokey
author_rank: Super Contributor
timestamp: October 01, 2024, 04:27:10 am
content: Check the pads for flying probe dimples under a microscope. You can see if they were tested

author: mtwieg
author_rank: Frequent Contributor
timestamp: October 01, 2024, 12:57:08 pm
content: Quote from: dotman852 on September 28, 2024, 05:29:58 pmWhat's the inner layer annular ring?QuoteThis is reasonable if the via/trace were perfectly formed in the first place. If the connection was initially just a sliver of plating...QuoteSimplest explanation isbreakout, which is why I'm asking about inner annular ring.

author: mtwieg
author_rank: Frequent Contributor
timestamp: October 01, 2024, 01:03:35 pm
content: Quote from: JLCPCB Official on September 29, 2024, 11:16:02 amAOI can't detect this sort of problem.QuoteFlying probe can detect this issue, but it depends on which pads are selected for testing each net. For nets with many pads (like a power rail) testing continuity between two random pads is not sufficient. If a net has 50 pads, do you check continuity from one pad to each of the other 49 pads? What if all pads are not on the same side of the board? Genuinely curious about this, I've asked this of other fabs about this and never got a clear answer

author: thm_w
author_rank: Super Contributor
timestamp: October 01, 2024, 09:06:43 pm
content: Quote from: mtwieg on October 01, 2024, 01:03:35 pmIts standard to test every pad. So continuity check would have to be done from pad 1 to 2, 1 to 3, etc. Or whatever the flying probe software determines is most optimal.JLC has and uses double sided flying probe testers (15:34):https://youtu.be/_XCznQFV-Mw?t=934Whether its on all boards, no idea.

author: bson
author_rank: Unknown
timestamp: October 05, 2024, 11:18:20 pm
content: Quote from: thm_w on October 01, 2024, 09:06:43 pmPresumably it picks a good first pair, tests them, and then as it tests additional pads it's always against one that has already been tested. Or comparable. Otherwise you could get the equivalent of testing 1 to 2 and 3 to 4...

author: Kasper
author_rank: Frequent Contributor
timestamp: October 07, 2024, 10:54:34 pm
content: Can you make the others fail? Thermal cycle, pressure change, vibration, etc.Maybe they passed testing but with a weak connection and that connection failed during shipping.Maybe the ones that pass now will fail after a bit more stress.