Push Pull Transformer Driver design - Page 1
Forum section: electronics / projects

author: 741
author_rank: Frequent Contributor
timestamp: December 08, 2020, 11:50:14 am
content: Are there any good discussions or LTSpice demos which explore in detail the way saturation is avoided in for example the SN6505? It seems it is common to sense current in both sides of the push-pull driver and thus provide negative feedback to ensure the core does not slowly drift into saturation. The DS for this device has a brief discussion of this issue.It would be nice to create, and understand the issues with an LTSpice design of my own which is suitable for driving eg Wurth MID-PPTI Push-Pull Transformers (these transformers are specially designed for compatibility with TI drivers).The links I have found so far are fairly high level rather than circuit design oriented.BH magnetisation curves - good discussion herehttps://electronics.stackexchange.com/questions/94744/what-is-the-difference-between-the-magnetic-h-field-and-the-b-field

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 08, 2020, 03:50:05 pm
content: The answer lies in the datasheet, though it's not marked as such, and you have to infer a bit from what they provide:https://www.ti.com/lit/ds/symlink/sn6505a.pdfBlock diagram page 16:1. ÷2 block suggests the oscillator may have crummy duty cycle (e.g., pulses from a ramp generator). Halving it, gives 50% duty cycle, as perfect as the timing constraints (of the logic used) will provide.So, first off, the imbalance is small.2. In the proceeding paragraph, they say dead time is inserted. This allows operation so that, when one transistor turns off, the rate-of-rise depends on load current, and therefore on (unbalanced) magnetizing current. Which puts slightly more or less flux into one side of the waveform.The amount is even actually specified, t_BBM typ 115/90ns. This is 3-7% of an on-pulse width. Probably the pulses are matched within 10s of ns.Which, curiously, they do specify this, in the most political way possible... "DMM" (average Drain MisMatch?) is given as 0%typical. With no error bars, or variance, or min/max bounds. In other words, it doesn't mean a fuckin' thing!3. R_on of 0.2 ohms or so, gives a small amount of "squish" as well. If one phase pulls 1A more than the other, it's seeing 200mV less voltage, and 200mV out of say 5V total is another 4% difference.4. And if that isn't enough, they have current limiting. How this is implemented, does not seem to be documented. It could be a peak-current-mode response (i.e., terminating the pulse early when exceeding threshold), or a continuous analog current limit (drain voltage is allowed to rise, out of saturation). I'm inclined to suspect the latter; there's also a "soft start" mentioned, which sounds like it's literally just ramping up the internal gate voltage, thus ramping up the current limit as well.Which if true, means the transistors are probably never that far from desaturation, which has implications for efficiency, but they never show efficiency (or other performance aspects) up near or beyond current limiting, and it's not like it's supposed to be setting records or anything, it's just a dumb chopper, so who cares.(The actual internal drive circuit, might be a CMOS current mirror -- you source a current into a "diode-strapped" FET of small size, so it drops whatever voltage related to its size, and its transfer function (which will be quadratic in this range, i.e. I ~ V^2). This voltage is then tied with the output transistor's gate, whose channel is N times wider, so has the same transfer function but draws N times more current as a result -- if N = 1000, it only needs 1mA of drive to do 1A of current limiting. In other words, a current mirror. Alternately, it might be an active circuit, that behaves in a similar way from the outside, but has some extra drive strength inbetween the "reference" "diode" and the output transistor, saving on supply current while keeping drive speed fast. Or it might be a feedback circuit, where Vgs(on) = Vdd outside of current limit, but an error amp monitors current draw and pulls Vgs down into the linear range when it exceeds the threshold. You could actually measure this from the outside, because the error amp takes some time to respond, which manifests as a capacitance on the pin -- when short-circuited, the drain draws a lot more than nominal current, for a brief moment (probably 100s ns?) as the error amp kicks in.)Anyway, if magnetization current peaks somewhere over an ampere, that'll pull the active transistor out of saturation, reducing flux on that side of the waveform. Effectively, the transformer has decided when to end the pulse, and the controller just has to deal with it. Which, it's a dumb hardly-a-controller, it doesn't really respond at all, it just happens.Downside, this greatly increases dissipation. Well, see #1, just don't generate severely lopsided pulses in the first place, y'know?Bizarrely, they mention flux "creep" at the end of the section (8.3.2), but nothing explaining how they've addressed it, or if you need to take any additional precautions!In any case, this is NOT a subtle, refined controller; it's not even a regulator! It works well for tiny stupid things where you just need some volts "out there", and don't particularly care how stable or clean it is. It doesn't work well for varying supply or load voltages (it has no regulation, that's why they show examples paired with LDOs), or at higher power (obviously, with its 1.some A current limit and low voltage rating).If you want PP operation with those features -- consider UCC3808 (oddly rather pricey (also, maybe obsoleting?) but has per-half-cycle peak current limiting -- works much like the classic UC3845, if it were wired for dual outputs), or, I'm not sure what else but there must be a bunch of them out there? -- and also a bunch of ADI iCoupler and isoPower parts, like ADUM3070 (or the ones with digital isolator channels too, e.g. AD4470-series quad channel).The highlights you're looking for, are current mode operation, and an input or output filter choke required: these will be true PWM regulators, and won't be making compromises on duty cycle, or conduction losses (like the 6505's ~full duty cycle and analog? current limiting / soft starting). Bonus points for internal or external compensation (depends what you're doing, important part is to know which, and use it accordingly), external error amp (usually for isolation you'll have a TL(V)431 on the secondary side, with an opto back to the controller), etc.But also, if you're looking for regulated power in small wattages, flyback is generally better. No filter choke is required, only one diode, no taps on the transformer. These are typically what you find in regulated DC-DC modules. (The unregulated, 1W or thereabouts, modules are typically the same sort of thing as SN6505, or even more basic i.e. a two-transistor chopper circuit with no protection of any kind at all -- use them carefully!)Tim

author: 741
author_rank: Frequent Contributor
timestamp: December 08, 2020, 04:58:31 pm
content: Many thanks for your comments Tim. I'd like to have 12V out at about 100mA, and input 5V. Efficiency is not an issue.Here (https://e2e.ti.com/blogs_/b/powerhouse/archive/2015/11/23/power-tips-a-simple-circuit-for-driving-gate-drive-transformers) I have the impression thatProvided the reset is from the same supply as the drive and alsoT(reset) > T(drive)"the transformer is guaranteed to completely reset". I do not quite see that, as we have deliberate drive asymmetry, so why does that not result in "flux walk"? Is it simply that flux base line can only go so far, and if you fully reset it, you know it cannot go further that way?I came across the chip mentioned via the transformer, which looked quite small and neat. If I look on Mouser, Farnell etc, should I look for "flyback transformer" ?Also, in this thread (https://www.eevblog.com/forum/beginners/why-does-transformer-flux-need-to-be-reset-in-every-half-cycle/) you posted a saturable inductor model - can I use that along with "M" (Mutual inductance) to create a transformer model?I'm also wondering whether I can simply plot the V.t product for a standard LTSpice inductor, although I gather flux walk is not an issue for flyback (?). This page (https://www.microsemi.com/document-portal/doc_download/125463-lx7309-active-clamp-forward-reset-technicques) statesQuoteP.S. Why does a normal mains transformer not saturate. After all, nothing is perfect, even mains cycle time matching?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 08, 2020, 06:22:53 pm
content: That's a variant of the two-switch inverter:https://www.maximintegrated.com/images/DI21Fig01a.gifNote that DRV has two transistors, one pulling up to VDD and one pulling to GND (assuming it's traditional CMOS). It's a half-bridge driving one end of the winding (which effectively acts as synchronous rectification in place of one of the diodes), and the other end is the transistor and catch diode.So, that's where the waveform comes from, it's driven high for a pulse, then driven low for a pulse.The key is, the low pulse is determined by the transformer itself, continuing until flux returns to zero. When flux returns to zero, magnetizing current drops to zero, the diode turns off and winding voltage returns to zero.Flux is unbalanced in the sense that it averages nonzero, but that's not what matters, what matters is that it returns to zero every cycle. (It's voltage that averages to zero. Flux is the time integral of voltage. We don't care about the second integral: that doesn't mean anything.)The reset pulse could be shorter if the reset voltage is allowed to be higher; this might be done with a zener clamp diode instead of the two-switch scheme used here. (You do of course need to beware of Vgs(max) ratings when doing this.)Quote from: 741 on December 08, 2020, 04:58:31 pmYou'll want to look under a few categories: pulse transformer, power transformer, SMPS... They're not always well categorized. Still one of those places where browsing the catalog might not be that bad an idea; or checking out major manufacturers' catalogs and cross-checking availability.QuoteNo; use it in parallel with an ideal transformer, and also add on leakage inductance, etc. as needed to fill out a model of something.Just kind of... playing with it, I'm not sure I'd recommend? It's not based on physical parameters, so exactly what turns, core geometry, etc. it relates to, may not be all that obvious. I'd recommend studying theory to cover that.QuoteWell of course you can, it's a straight line.I'm not sure which axes you meant to plot, but V.t vs. t is simply integral(V dt), which for a fixed voltage is a straight line. V.t vs. I is a straight line (slope = inductance). SPICE inductors are ideal, you won't find any kinks here.QuoteNon-answer: because the mains is supplied from a transformer, which filters out DC, duh.A good follow-up question though, is what happens when a DC load (like a half-wave rectifier -- these were somewhat common back in the day) is plugged in? Well, that DC bias flows through the distribution transformer, putting some bias in its core; I don't know their exact specs but I assume they're made to withstand a certain amount of DC for this reason, and as long as it's within ratings, it's fine.Tim

author: jonpaul
author_rank: Super Contributor
timestamp: December 08, 2020, 07:10:39 pm
content: Hello driven push pull center tapped inverters were popular in 1960s..1970s.Poor transformer utilization and core sat means most were Royer inverters, seld driven and self bvalancing.IBM had a patent on an anti sat balancing ckt.Nowadays, most inverters are bridge, half bridge or double forward and have NO core sat issues with unbalance.Finally making the CT transformer is more costly than a single pri single sec.Advise to avoid the CT inverter.Jon

author: mag_therm
author_rank: Frequent Contributor
timestamp: December 08, 2020, 11:11:29 pm
content: I think the push pull inverter still has uses in the high power electronics.The available high speed switches and antiparallel diodes with forward voltage ratings of 2 kV+ mitigate the inherent disadvantage of push pull, which was the doubling of the forward voltage.I took photos on a vintage oscilloscope of the operation of a push-pull saturating ferrite inverter as a test circuit for core parameters.The inverter has a ferrite toroid, gapless and two transistors TIP31C . Frequency approximately 40 kHz.There are feedback resistors to isolate the hard switched collectors from the winding.The load is disconnected so that the feedback transformer is driven harder into saturation than normal, for the photos of the waveforms.The first image below is of the voltage ( Y axis) versus current (X-axis) in the primary winding of the saturating transormer.The core runs to saturation symmetrically on each side of the B-H curve,allowing for approximate measurement of core parameters.The 2nd and 4th quadrants are at high speed ( dimmed trace) of the transistor collector currents commutating,ending at zero on the Y axis.The main time of the cycle is in the 1st and 3rd quadrant.The voltage falls as the current rises. The region of higher permeability at low H is visible ( I think) near the Y axis.At the bright peaks, the core has suddenly saturated causing commutation... repeating around the loop etc...The second and third images are winding voltage and current respectively, in time.The fourth image on the 466 'scope, of the transistor base voltages, shows how the commutation occurs.Top trace is on a base and bottom trace is on a collectorThe off transistor turns on slowly with the core in saturation until overlap starts. Then regeneration takes over with theoverlap time being about 500 ns for this core and transistor combo. The overlap time is quadrants 2 & 4 of the first image,and the steeply falling current of the third imageThis circuit will maintain electrical symmetry even when the core is heavily magnetized with DC Field.I was surprised when placing supermagnets near/on the core. The frequency increased a lot (3X), but the transistors stay in balance.Have to look at that further.

author: 741
author_rank: Frequent Contributor
timestamp: December 09, 2020, 09:50:10 am
content: A nice read (reminds me of Jim Williams's book "Analog Circuit design, Art, Science and Personalities")The cheapest flyback on Farnell is this (http://www.farnell.com/datasheets/2868806.pdf) by Bourns "SM13117EL - PoE Flyback Transformer". Out of interest, I looked at the datasheet, and I was immediately surprised by the way the thing is specified. They show mainly DC voltages and currents.Also they have a winding annotated by "36-72 VDC 250 KHZ". What I do not see is the way perfomance drops either side of 250 kHz. This (somehow) relates to the fact that HF transformers can be smaller.When I started looking into this, I wrongly imagined that inductance would be a key parameter. It seems in fact that inductance is (typically) an unwanted characterisic and is known as Leakage Inductance. That being so, I'm unsure what sets the preferred operating frequency, although core characteristics would be part of that.For an ideal transformer: Is frequency is wholly irrelevent? Would I see (say) a 1:1 primary to secondary voltage conversion at 1Hz just as well as working at 5kHz? Is this true at very light loads? As I see it, the inductance is 'removed' due to the secondary extracting energy.On a flyback transformer, why is it important that the windings are wound opposite ways? Would the flyback principle work with a 'forward wound' transformer given suitable circuit modifications - perhaps to the primary side?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 09, 2020, 04:08:30 pm
content: They give, let's see:- Magnetizing inductance, primary referred, measured at 250kHz, 0.1V (probably small signal regime)- LL, primary referred (almost missed this, it's in the sidebar!), doesn't say which secondaries shorted though (all of them?)- Voltage and frequency range, which doesn't help directly- DCR, giving some estimate of current ratings and efficiency (but ACR will be somewhat higher, who knows by how much)- Output current, so the peak current is probably ~4x that (assuming BCM), which puts a limit on saturation flux- Power, which doesn't help directly- Hi-pot, with no insulation type specified; assume functional type (i.e. don't hang this off the mains and expect the far end to be safe to touch)- No idea on capacitance, winding length, etc.So you can fill out about half a 2nd-order transformer model from these data, maybe. The remaining half have to do with HF cutoff, leakage between pairs of windings, accurate figures for losses, etc.Also, it would be kind of unbelievable for a part that size to dissipate more than a watt, so hopefully that 13W figure means efficiency is over 92%. From which you could make some estimate of losses.So, the voltage, current, frequency and power figures give some ideas:- Turns ratio is 2:1 so secondary-referred magnetizing inductance is 127/4 = 31.7uH. 4A peak * 31.7uH = 127uVs (secondary referred). Presumably saturation is higher than this; 250kHz is kind of high to be running near saturation and I'd expect peak flux density is more like 100, maybe 200mT (whereas ferrite saturation is typically 300-450).- Also, 12V for 2us (half a 250kHz wave) is 24uVs... which is fully a fifth of the above value. Even with an odd duty cycle (which seems likely from the ratio and recommended voltages), that's off by a lot, or it implies it's supposed to be in CCM, which is pretty shitty for a flyback...- Typically you design around flyback peak equal to input, so the primary side switch runs around 50% duty and is rated >= 2*Vin. At 36V and 2:1 ratio, well, 36V flyback * 1/2 = 18V secondary, so that's not quite it. It's definitely intended for a lower duty cycle, especially up at 72V (max 25% duty). Seems like it would be better suited for 24V input, or 18-36 say; but maybe it won't handle as much power under that condition (due to DCR? -- it is interesting that Rpri is 6*Rsec, not the 4x you'd expect from the turns ratio).We could keep going and come up with some estimates of a reverse-engineering; again, there's not nearly enough data to figure out, say, the exact winding schedule -- but we can take some guesses at the core (looks to be EP13), gap, number of turns, and maybe assume they took the laziest possible way out (no interleaving, just whole layers for each winding).Anyway, for lower power levels you can definitely use it, at pretty much any voltage you like, and any frequency so long as stray capacitance doesn't screw you over too badly.**Which heh, I made a 150V isolated converter recently, using a 600kHz boost regulator IC and a transformer salvaged from a 5V charger. Driving the former-secondary at 12V, the reverse-peak voltage is rather high (200-300V), and the flyback voltage being much lower (the 150V nominal output) forces a somewhat low duty cycle -- like the above transformer, really. Well the catch is, at 600kHz, and with the high voltage winding being as many turns as it is, the self-resonant frequency is rather close (a few MHz), so it burns up a lot of power just shoving that around. Fortunately I only need a watt or two from it, so the efficiency being shite isn't a big deal.Tim

author: 741
author_rank: Frequent Contributor
timestamp: December 09, 2020, 04:56:46 pm
content: Again thanks.I had a quick look at TI's web Bench tool, mainly to get a feel for typical transformer part numbers. One particular thing interests/puzzles me here - illustrated by this example (taken from the design tool)Pulse Transformer, 1:1:1:1:1:1, 500 V, WE-FLEX Series, 27.4 µH, 0.344 ohm, 32.9 VµsRecommended Limits:Lp: 26 µH - 28.6 µHRp: 100 µO - 59.71 mOLeakage_L: 114.4 nH - 572 nHThey have a lower limit for this thing called Lp, and Lp is distinct from Leakage (which also has a lower limit).My initial thought is that one (or both?) of these inductances are used to limit drive current. However that strikes me as contradictory to the 'message' that a good transformer has little inductance.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 09, 2020, 06:04:58 pm
content: Lp is commonly "primary inductance" == "magnetizing inductance, primary referred". (Which might also be symbolized "L_m,p" or something like that. Mind, "Lm" might also be used for "mutual", though "M" is more common for this. Mutual inductance isn't used much outside of theory, though.)As for a "good" "transformer", that depends what you're using it for.So -- a useful (but not always used) distinction, is to separate them intocoupled inductors, where magnetizing inductance is important, transferring energy; andtransformersused for transferring power (coupling voltage and current ~instantaneously), storing a minimum of energy.Coupled inductors can be further refined into tight and loose coupling: tight, the LL should be small (if not necessarily "as small as possible"). Loose, LL might be modest (example: SEPIC inductors, some CMCs, notwithstanding the below), or very significant indeed (e.g. RF tuning coils, wireless power).Transformers generally have magnetizing inductance ashighas possible, and low leakage. For a given signal frequency and amplitude, large Lp stores the least energy / draws the least current from the source, a desirable trait in a transformer that should be approach the ideal (infinite Lp, zero LL).Exercise: what is a "common mode choke" under this categorization?Typically, LL is low (though not necessarily "as low as possible"), and Lp very high ("as high as possible"). It's a transformer!This is actually pretty sensible if you turn your head sideways -- you're transforming the voltage drop, or current flow, 1:1 between the two (or more) lines. Which, yeah, has the effect of raising the CM impedance, hence "common mode choke". True, you aren't (usually) coupling much power with one, but so what, neither are signal transformers, right?So, keep in mind that,1. This is a functional classification, not a generalization; and2. Always make clear when you're using it, because conventional terms don't always line up with it.(And, the general model, is just the nonideal transformer -- Lp, LL (or M or k), and Np/Ns are all free parameters, no distinction needed. And you can add on whatever parasitics as you like: DCR, Cp, etc.)So, because flyback stores significant energy, it uses a "coupled inductor". Whereas a forward converter uses a "transformer".So the listed transformer above, would be a fine option for flyback and such. Its magnetizing inductance is modest, and tightly specified. It can also store a fair amount of energy (presumably, the flux given, is the saturation limit, corresponding to I = Phi / L = 1.22A; which sounds about right given the DCR and typical size of that, if it's the kind I think it is).A forward converter transformer's inductance might still be important, but it's usually parasitic in nature, and usually better the higher it is. Whatever energy is stored in magnetization, has to be dumped back into the supply in the case of the two-switch forward, or completely wasted as snubber power in the one-switch case. In practical circuits, we still might need to specify a modest value, and the reason is because the magnetizing current drives turn-off dV/dt (commutation), and we don't want that so slow that we have to wait forever for it to discharge. Or for full-wave converters (bridge/PP), so that there's enough current to correct for "flux walking" (as described a few posts ago). In both cases, the power cycled through Lm (and Coss and other capacitances it drives) is a fraction of total power.Tim

author: mag_therm
author_rank: Frequent Contributor
timestamp: December 09, 2020, 06:56:30 pm
content: Hi 741, I am not sure if your intention is still to model the transformer's parameters in a push-pull.If so,I've attached scrots showing the position of Lp, Rp, and L_Lk. I have just added them to an existing push pull model in qucs transient solver.In this case a 60 Hz inverter, but it would be similar up to 100 kHz and higher.I do not try to include models of the power IGBTs , instead just using a modified ideal transistor and diode.that are known to run to a stable solution.For symmetry , I estimated Lp and Rp values to be placed across the total centre tapped winding.Similarly, L_Leak is split and placed in the collector leads.

author: 741
author_rank: Frequent Contributor
timestamp: December 10, 2020, 02:28:35 pm
content: Thank you doing that...I've located Lm, Rm, L_lk1, L_lk2 but have not found Lp yet. Out of interest, how would you deal with saturation effects in this simulation?

author: mag_therm
author_rank: Frequent Contributor
timestamp: December 10, 2020, 02:55:00 pm
content: Quote from: 741 on December 10, 2020, 02:28:35 pmOh sorry, My Lm ( L_magnetic) is Lp on the data sheet. ( I think they refer L_parallel)However, because I put that Lm across the full centre tapped primary which will be across two windings of the transformer on your datasheet, Lm has to be adjusted. If I understand the brief data sheet, then my Lm would be adjusted by the turns ratio as follows:Lm = ( N^2) * LpLm = (2^2) * LpLm = 4 * LpTo date I have not been able to model saturation effects in qucs.Using a fixed Lm value across the transformer will just give a triangular magnetising current, which is very different to the measured current shown in my earlier postI have used Curie-Weiss function along with non-linear functions for Ur in 2D FEM, and in my own numerical simulation software.I am about to update a new computer here with Fedora 32 and go to the new version of Qucs-sSome info about what they have now for magnetic cores is here, about 3/4 down the page:https://qucs-s-help.readthedocs.io/en/latest/SPICEComp.html

author: 741
author_rank: Frequent Contributor
timestamp: December 11, 2020, 12:02:01 pm
content: QuoteLooking at the remarks from jonpaul - and in view of what I've picked up, the real circuit will likely be flyback, just for simplicity's sake. I am still interested in the push-pull situation though, especially insofar as it teaches me about transformers/magnetics.About the BH Curve screet shotQuoteI can see that current should equate to field H. But I wonder if there are any difficulties when equating voltage to flux density because (I am assuming) voltage is itself dependent upon inductance. It seems that real world inductances do have some frequency dependence (of actual inductance value in Henries that is).In a textbook BH curve, I think there is no restriction upon the rate at which the field changes, it's just field vs flux.I had been assuming these non-ideal inductance effects (ignoring parasitic capacitance here) worsened a frequency rose, but a quick look shows people sayingQuoteGiven the actual circuit, would it be practical to derive a formal BH curve - with the usual units - from this image do you think?

author: 741
author_rank: Frequent Contributor
timestamp: December 11, 2020, 12:22:21 pm
content: Incidentally, why are flyback transformers always depicted with "opposite polarity dots" - is this contruction (with primary would the opposite way to secondary) essential for a flyback design?Equally, are "same polarity windings" essential for a forward converter?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 11, 2020, 01:24:41 pm
content: Quote from: 741 on December 11, 2020, 12:02:01 pmVoltage is the time derivative of flux. So the top and bottom slopes, you need to imagine integrating them; going clockwise from bottom left, instead of jumping up then sloping down, imagine it moving diagonally up-right, then slowing down to nearly flat; which sounds a lot more like the usual B-H hysteresis curve you see.This loop is dependent on frequency. If voltage remains constant, then width shrinks as frequency goes up (and saturation quickly becomes less severe); if width remains constant, then voltage goes up.The B-H curve also depends on frequency, gaining more or less hysteresis (or the equivalent thereof) and changing its average slope. This is equivalent to the small-signal parameters changing with frequency, typically mu' dropping and mu'' peaking around some cutoff frequency. The loop area corresponds to mu'', while the slope corresponds to mu'.Typically it's measured at lower frequencies, where mu' is dominant, and mu'' is obviously present, but is mostly true hysteresis (area ~independent of frequency). (Note that mu'' is calculated as an inductance component, whose reactance depends on frequency; so a constant loss fraction looks like a steeply changing imaginary-inductance parameter: this is why mu'' drops asymptotically at low frequencies.)Quote from: 741 on December 11, 2020, 12:22:21 pmInteresting question, actually -- the answer often depends on EMC. As such, this may be more advanced than you were expecting, and on a more basic level (transformer flux and overall winding voltages/turns/etc.), no, it doesn't matter, just so long as the polarities are correct.Consider a 1:1 transformer, primary and secondary are single layers on a cylindrical form, same size wire. This looks very much like a twin-lead transmission line, wound edge-wise, and the characteristic impedance will be around 100 ohms (assuming magnet wire and a couple layers of insulating tape between them). The instant the primary switches off, the secondary switches on, magnetizing current is transferred. If the start end of both windings is switched (primary transistor, secondary diode), and the far end of both is common (primary DC bus, secondary GND), then we have a current pulse applied to one end of this transmission line -- the primary was carrying Ipk and the secondary 0, and suddenly they've swapped, to 0 and -Ipk -- and this wave propagates down the transmission line (in the space between windings).On the primary side, we observe a spike -- normally attributed to leakage inductance, which is really the LF equivalent of the TL's inductance. (Which, if we're using this at an impedance much lower than 100 ohms, is most likely the best way to express it. Like a 12V 1A (DC) converter, that'll be closer to 4A peak, so down to 12V/4A = 3 ohms at the switch node, well into the inductive range!)On the secondary side, we observe the dI/dt being modest, complementary to the primary-side spike -- the voltage has to spike up to drive that current into the secondary. This is easier to see with the tee or pi equivalent of the transformer,the series element(s) manifest as leakage, and going from zero to full current over some time, requires some voltage pulse, simply enough.And between primary and secondary, that is, the common mode -- we see at one instant, primary DC bus and output GND are steady (on the winding finish ends), while a spike is happening on the switch nodes (winding starts). After that wavefront propagates through the windings (transmission line), it reflects off the finish end and bounces back and forth (again, if the switching impedance is very low, this bouncing manifests as inductance). Meanwhile, the common mode voltage is driven apart by half the step voltage -- we get a big injection of common mode noise here.If we ~short out the common mode voltage with a capacitor between grounds (DC bus to secondary GND, or primary GND which is bypassed to DC bus with a much larger capacitor already), we can reduce the CM voltage, confining most of the imbalance (leakage inductance spike) to the switching nodes. Hence this is a first line of defense against common mode emissions.If the windings were counter-wound, then the primary switching edge would couple directly to secondary GND, and the diode doesn't see anything until after one transmission line delay. This situation puts 100% switching edge into the common mode, which is much worse -- remember in the first case it was just the leakage inductance spike, much shorter than the full pulse.Well, these are convenient approximations, mind -- typically the switching edges are 10s or 100s of ns, while the transmission lines are just a few ns. We aren't working with ideal wavefronts that ping back and forth, we're working with sloppy waveforms that work more with the LF equivalent properties of the transformer (LL and Cp). The actual tradeoff need not be quite as bad as these examples show.But it also gives you some idea of how to optimize transformer design, both to reduce LL and Cp (to reduce losses), and to help reduce EMI. If we can interleave P and S across multiple parallel layers, we can effectively make multiple TLs in parallel, which therefore have a lower total Zo, closer to Zsw -- LL goes down, at the expense of Cp going up. (When Zsw is so much lower than Zo, the rise in Cp isn't nearly as important. Conversely, when Zsw is higher than Zo -- typically the case in low power or high voltage converters -- Cp is more important, and looser winding geometry can pay off.)Or we can balance operation, keeping the DM switching in the DM -- we can note this is a DM-CM conversion problem, so by reducing that conversion factor, we reduce EMI proportionally. This is an advantage of the two-switch converter: both ends switch at the same time (give or take variation in propagation delays), one going up, one going down; leakage manifests on both at the same time and common mode is ideally zero. Even if it's not (the delays, or edge dV/dt rates, don't match perfectly), it's a hell of a lot easier to filter because the fundamental balances out; we really only have to filter the high frequency crap that didn't balance out.If the winding ratios are very different, we might end up with a situation where the shorter winding practically acts as a ground plane, with respect to the other -- this is most explicit in the case of 1-turn foil windings against N-turn wire windings. Here, it doesn't matter as much what the short winding is doing, but we are very concerned about the N-turn winding. We might treat it as a balanced winding over ground plane, just ignoring for now the fact that the "ground plane" is itself at an average 1/2-switching-node voltage. So, if we use two switches, one at each end of that winding (primary 2-switch inverter, secondary just two diodes), we can balance out its transients (which may be quite substantial -- a 400V step, say, on a 100-ohm TL, is a lot of peak current (~4A) and ringing!), and then only have to filter out the shorter winding's switching waveform.Or we can insert a shield layer, which has the same effect as a one-turn foil winding: it acts as a ground plane, except that once again because it has to be slitted, there's some voltage across it, but at least it's only one turn, not, a hundred or whatever. And if we're careful about how we wind and wire up the primary and secondary, we might still be able to cancel that out (namely, if the shield is grounded on one side of the bobbin, and the windings come out the other side -- this works for double-opening EE cores for example, we can position it effectively 1/2 turn away from the windings; not so much for, say, EP cores).Tim

author: 741
author_rank: Frequent Contributor
timestamp: December 17, 2020, 10:02:37 am
content: Re Reply #3QuoteIs this a true exact zero? My concern is that (for instance/analogy) an RC decay never actually hits zero. I can't see how a passive load can achieve this.QuoteI can't even quite see how an active reverse drive can solve flux walk because there is still the symmetry of the drive to consider (and allowances for energy extracted). How do I know the flux passed through, or hit exactly 'zero'. With no load on the output, I see (conceptually) a need for ever larger drive swings just to guarntee the flux goes back through zero.Out of interest, could a "two-switch inverter" be designed open-loop, just assuming a stready current draw, but realising the drive energy will not be perfectly matched. I suppose not?Also:If I drive a transformer push-pull, with bi-directional current limit chosen less than the transformer's V.t limit, will that avoid flux walk?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 17, 2020, 10:23:26 am
content: Simple: if flux is nonzero, that means magnetizing current is nonzero.Into a nonlinear load like a pair of diodes (the transistor is also a diode, when not driven), the voltage is +V/-V when current is nonzero, and 0 when zero. Only thing that would give an intermediate value (at DC) is leakage current, and the magnetization decays very quickly through that scale.If you must -- node capacitance (and also diode recovery) causes it to overshoot, so that 1. it doesn't relax instantaneously, but swings through some voltage range first; and 2. flux actually reverses slightly, then overcorrects and goes positive, etc. (For the usual case when tank Q >> 1.) This is just ordinary ringdown, and once its amplitude is a fraction of +V, we needn't concern ourselves with the nonlinearity of the diodes; it's just an RLC tank. Which will return to zero along the usual exponential decay.Point is, once it's into that ringdown phase, the current/flux is only ever orbiting zero -- indeed, crossing it multiple times. It's perfectly safe to turn on the transistor(s) again at this point (indeed it might be desirable to do so, to get lower switching loss -- zero-voltage or valley switching). If you happen to turn on while the flux has a slight positive excess, so what, it gets a little more total during the on-pulse, and discharges that much faster during the off cycle.Quote from: 741 on December 17, 2020, 10:02:37 amDesigned for what? Like, a regulated CV output, an ordinary PSU application? Matching what energy?You can design something however you like; you can do primary-side voltage sensing, you can measure the flux or charge or current or power delivered, you can calibrate out all sorts of errors (timing, supply voltage (PSRR), leakage inductance and DCR, etc.), just a matter of how accurate you need vs. can get (reproducibility vs. required calibration steps), and how much trouble you want to spend to get there (these sorts of solutions are usually complicated enough that it's cheaper to use an aux winding or secondary side feedback).QuoteYou'll have to define what you mean -- you can't just smoosh two different units together!Tim

author: 741
author_rank: Frequent Contributor
timestamp: December 17, 2020, 10:38:50 am
content: QuoteBut IMHO, an RLC tank never hits zero in ringdown. It just gets so miniscule we cannot see it. To truly hit zero needs an abrupt stop. Its like stopping a train surely, practically it stops still, but theoretically it keeps ringing. If it truly ever hits zero and stays there then there must be an explicit formula, if only to prove it is so. For the RC analogy, we usually say oh, it's pretty low after 5RC.e^(-Infinity) is  zero.QuoteI think this is key, that starts to make some intuitive sense to meDesigned for what?For simplicity - but I was also just wondering what would happen.QuoteAttached is a vague idea. Its not great, just trying to get used to this kind of thing.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 17, 2020, 06:44:13 pm
content: Quote from: 741 on December 17, 2020, 10:38:50 amNot sure what's supposed to be going on here, some sort of Circlotron thing but there's only one source?It's two crispy diodes (D4, D6), and not a lot of useful behavior I can think of?Why ground on the AC signal?Tim

author: 741
author_rank: Frequent Contributor
timestamp: December 18, 2020, 12:10:09 pm
content: I do not know what "crisy diode" means I'm afraid.The Schottkys were meannt to be there to protect the current source when current goes the wrong way. I did not realise they were also bypassing the 'right way' source. ooops.Anyway, here is what I was trying to do: Create a simple bi-directional current limit. I had thought about 'current diodes' but gave up when I saw these only seem to cover a few mA.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 18, 2020, 09:24:21 pm
content: Crispy, burnt.Depletion MOS is a good way to do a current limit, see the last image inhttps://electronics.stackexchange.com/questions/473310/using-a-depletion-mode-mosfet-as-a-current-limiting-device(weird, they show external diodes in parallel with the body diodes, well, just ignore that)A simple way in SPICE is to put a CCS into a FWB's DC pins; current is limited across the AC pins. No need to select (or find and install) FET models.Tim

author: jonpaul
author_rank: Super Contributor
timestamp: February 21, 2021, 05:11:19 pm
content: a few random old reference books.Steve Smith is an old friend....McLyman is oriented towards cut cores eg for avainoics and space ..I didnt find Hunt, Static Electromagnetic Devices, my text from City Colleg in 1966Kind Regards,Jon

author: jonpaul
author_rank: Super Contributor
timestamp: February 21, 2021, 06:25:07 pm
content: Basic college EE text:Static Electromagnetic DevicesWilliam t Hunt and Robert Stein. 1970ISBN-10 : 125843654XISBN-13 : 978-1258436544Enjoy,Jon

author: niconiconi
author_rank: Frequent Contributor
timestamp: December 17, 2022, 10:09:00 pm
content: Today I've stumbled upon a pin-to-pin compatible replacement of the SN6505 chip from China - VPS8505. In its datasheet, it contains an extra paragraph that provides a small hint of how volt-second balance is implemented, which is not found in the TI datasheet.Then I remembered this old thread.Consider that the VPS8505 looks like a clone of the SN6505, it's at least also a partial description of how the original chip worked at well.Basically, T3sl4co1l's guess of R_on was spot on.QuoteWhich is roughly translated to:The MOSFET is used as the main switching transistor of the push-pull converter, which can have the characteristic of automatic "imbalance correction" during its operation. In practical applications, the on-time of two transistors in a push-pull converter cannot be guaranteed to be 100% completely symmetrical, and the slight deviation of the turn-on time Ton still causes the volt-second products of the push-pull transformer unable to be exactly equal, resulting in an imbalance of magnetic flux. This imbalance process leads to an increase in the operating current of its corresponding circuit, and the corresponding MOSFET generates additional losses, causes its temperature to rise. Due to the positive temperature coefficient of MOSFET's R(on), the voltage drop during MOSFET's conduction increases accordingly, this eventually causes the voltage amplitude Vp in the turn-on circuitry - obtained via voltage division from the primary winding of the transformer - to decrease, hence achieving automatic "imbalance correction".

author: mag_therm
author_rank: Frequent Contributor
timestamp: December 17, 2022, 11:17:41 pm
content: Yes, but since that time in 2020 I have made a few more hobby push pull pwm inverters.I am using the IXGH32N60C IGBT (without antiparallel diode). Current range 12 Amp DC, up to 24 Amp peak/side.Take a look at Fig 4 of its datasheet which shows anegativeVce tempco in that current range.I am using no airgap in the ferrite transformers. The inverters have perfect current balance, as measured.I do remember the olden days. With 50 Hz UPS fundamental scr inverters in 30 ~ 100kVA range,we used a low grade lamination (like motor grade) as part of keeping the currents even.As the inverter heated up on full load, the current at end of conduction would start to curl up on one side.Further indication of an offset in the core was to hang a steel wrench (spanner) above the yoke.With a little offset the wrench would start to swing like a compass in the yoke flux. Great Fun?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 18, 2022, 04:28:40 am
content: Quote from: niconiconi on December 17, 2022, 10:09:00 pmInteresting, suggests they have output sensing. Or maybe it's just because the die is heated locally which affects the nearby drive circuitry, but that seems like it would be VERY minor.Thanks, have been curious about equivalents, SN6505 is, either obsolete or poorly available.Tim

author: niconiconi
author_rank: Frequent Contributor
timestamp: December 18, 2022, 05:45:53 pm
content: After further investigation, this paragraph actually came from TI SN6507 datasheet, or another SN-series chip datasheet from TI (unsurprisingly, the same company also cloned other transformer driver chips in the same category).https://www.ti.com/lit/gpn/sn6507Here's the uncorrupted original text:Quote

author: Zoli
author_rank: Frequent Contributor
timestamp: December 18, 2022, 06:12:58 pm
content: Quote from: T3sl4co1l on December 18, 2022, 04:28:40 amTake a look on LCSC for VPSC:https://www.lcsc.com/brand-detail/12739.htmlThey have a family of 6 in this category. One warning: all the products are MSL-3.

author: niconiconi
author_rank: Frequent Contributor
timestamp: December 19, 2022, 12:42:00 pm
content: Quote from: T3sl4co1l on December 18, 2022, 04:28:40 amChip shortage. SN6501 is out of stock, SN6505 is out of stock, SN6507 is out of stock, MAX258 is out of stock, MAX13253 is out of stock, LT3439 is available but it's a premium chip...Mouser says a new batch of SN6505 will arrive in 2024. I guess SN6505 was already a low-demand but still in-production chip before the shortage and the supply got a hard hit. The SN6507 looks better, as it's a new chip and a batch should arrive in January 2022.On the meantime, the clones are the solution.