Simple SPI question - Page 1
Forum section: electronics / projects

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: September 15, 2014, 03:44:38 pm
content: Why is there a CS signal on a serial protocol with addressing? Isn't the idea to hang a bunch of chips on a serial bus and have the address pins determine who you are talking to?Or are there situations where there are so many SPI devices you need to chop up the bus to reduce capacitive loading in the lines?

author: max_torque
author_rank: Super Contributor
timestamp: September 15, 2014, 04:04:12 pm
content: SPI at it's lowest level doesn't' have Addressing. You may be using a higher level protocol, which uses SPI as it's hardware level, that DOES have addressing, but that's nothing to do with SPI......

author: tonyarkles
author_rank: Regular Contributor
timestamp: September 15, 2014, 04:10:17 pm
content: Maybe you're mixing up SPI and I2C? I2C definitely does addressing.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: September 15, 2014, 06:33:01 pm
content: Quote from: max_torque on September 15, 2014, 04:04:12 pmSo you're saying SPI is just a set of pins, and everyone does whatever they want after?From a datasheet:"The SPI write operation is started by lowering CS. The Write command (slave address with R/W bit cleared) is then clocked into the device."

author: Sebastian
author_rank: Regular Contributor
timestamp: September 15, 2014, 06:55:33 pm
content: You are mixing up SPI and I²C.There is no addressing in normal SPI and there is not R/W bit either. SPI uses separate Rx and Tx lines.But I think you are right about that there is no real standard for SPI. At least I have seen a lot of different implementations.

author: David Hess
author_rank: Super Contributor
timestamp: September 15, 2014, 06:58:35 pm
content: SPI replaces an asynchronous parallel bus but keeps the separate chip select line which would usually be decoded from the address bus outside of the device. I like using an external 2-to-4 or 3-to-8 decoder to expand 2 or 3 microcontroller output lines into 4 or 8 SPI chip select lines.It is certainly possible that the SPI interface would need to be split up to support the highest speeds but that has nothing to do with using a chip select signal. Since the SPI inputs and outputs are not multiplexed, this is easy to do.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: September 15, 2014, 07:58:50 pm
content: Quote from: Sebastian on September 15, 2014, 06:55:33 pmNot me; Microchip. But I think I see what is going on, the chip is actually a I2C device that can get data mashed into it via SPI as well. I2C over SPI?

author: mjkuwp
author_rank: Unknown
timestamp: September 15, 2014, 08:42:45 pm
content: no, it's not i2c over SPI. It could be that the chip lets you choose the communication protocol. Maybe with another pin or pins that get pulled low or high to tell the chip what to be. I have a design that works this way. I wrote spi code and i2c code and used them interchangeably in software without any hardware change. Both the micro and the device did spi and i2c using the same lines but obviously not both at the same time. I had pull-up resistors on the lines to enable i2c but in the end I only used SPI and so I eliminated the pull-up resistors.with i2c you send an address first. With SPI you pull the specific chip select line before communicating.

author: David_AVD
author_rank: Super Contributor
timestamp: September 15, 2014, 09:05:08 pm
content: The "slave address" they are referring to is the register address inside the chip, not the chip itself. ie "addressinthe slave chip", not "addressofthe slave chip".

author: dannyf
author_rank: Super Contributor
timestamp: September 15, 2014, 09:29:05 pm
content: :Not me; Microchip.:the difference between smart people and dumb people is that smart people know what they don't know, and dumb people don't.

author: sacherjj
author_rank: Frequent Contributor
timestamp: September 16, 2014, 12:49:20 am
content: Some chips have address pins to control a few bits of the address for I2C as well. This is more common in chips you would be likely to multiples, like memory, etc.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: September 16, 2014, 01:28:02 am
content: Quote from: David_AVD on September 15, 2014, 09:05:08 pmOdd that the chip would have three address pins. I also don't quite see how you can interpret "slave address with R/W bit cleared" the way you do.Here's the whole thing:"The SPI write operation is started by lowering CS. TheWrite command (slave address with R/W bit cleared) isthen clocked into the device. The opcode is followed byan address and at least one data byte."Clearly, you clock in a device address, THEN you clock in the opcode and the address and the data of the register.Here's the read command : "The SPI read operation is started by lowering CS. The SPI read command (slave address with R/W bit set)"Quote from: dannyf on September 15, 2014, 09:29:05 pmThanks for removing the doubts I had about you.

author: Mr.B
author_rank: Unknown
timestamp: September 16, 2014, 01:38:56 am
content: For the benefit of the thread, could you link the Microchip datasheet you are referring to...Thanks.

author: David_AVD
author_rank: Super Contributor
timestamp: September 16, 2014, 01:53:25 am
content: I didn't read it that way at first. Some SPI chips do support addressing in conjunction with a few external pins. A lot don't.The CS pin is still required to indicate the start and end of the data exchange though. I2C does it through the start and stop timing/sequences.

author: mikerj
author_rank: Super Contributor
timestamp: September 16, 2014, 12:21:10 pm
content: For starters, never assume anything that Microchip has implemented is a good way of doing something. Without mentioning the specific device you are talking about (why not?) I can only guess, but I have come across devices that either have both I2C and SPI interfaces available, or are available in I2C or SPI variants with only the die bonding changed. Internally the register structures are arranged identically both both interfaces so you get this kind of oddity where an SPI device requires an I2C style slave address.It should be quite obvious that when you have a chip select per device that device level addressing is superfluous. Effectively the device level address deciding is performed by the master device when using SPI.

author: dannyf
author_rank: Super Contributor
timestamp: September 16, 2014, 12:51:42 pm
content: QuoteThat approach is quite common for chips with multiple internal registers.The OP is just confused.

author: timb
author_rank: Super Contributor
timestamp: September 16, 2014, 01:21:07 pm
content: Quote from: mikerj on September 16, 2014, 12:21:10 pmThis.I've encountered a number if devices with a selectable I2C or SPI interface. When in SPI mode you still have to send the I2C address (with R/W bit) first, before selecting the register you want to access.The reason it's done this way is fairly simple when you understand how I2C actually works. Essentially, every I2C device on a bus listens to *all* traffic *all* of the time. They only respond when the pattern of that traffic happens to match their specific address.So, when you address an I2C device, you're not performing any special handshaking or anything; all you're literally doing is broadcasting a single byte.Master: Start; 0x11 (Address of the slave with R/W bit.)Slave: ACKMaster: Transmit data, one byte at a time; Slave acknowledges each byte; StopSlave: NACKSo, in some if these dual mode SPI/I2C devices, you have to send the address even in SPI mode, as it doesn't require the designer to program a different access protocol in. Register access works the same, just over a different bus.A little more information for you: I2C is a mature protocol based on a well defined standard that covers the electrical and timing characteristics. It was created by Phillips, now NXP. A lot of times it won't be referred to as I2C in data sheets for copyright reasons. Another common name is Two Wire Bus.There is no single defined standard for SPI (AKA Microwire, Three Wire, Four Wire and Synchronous Serial Bus).Sent from my Smartphone

author: dannyf
author_rank: Super Contributor
timestamp: September 16, 2014, 01:26:07 pm
content: QuoteNo SPI chips allow addressing (other than via the CS pins) natively.However, that doesn't prevent you from implementing a protocol that allows for addressing individual chips.Similar things are done via uart for example.

author: David_AVD
author_rank: Super Contributor
timestamp: September 16, 2014, 09:20:54 pm
content: Quote from: dannyf on September 16, 2014, 01:26:07 pmI was sure that I'd seen a chip that did, but could very well be mistaken. Maybe it was not addressing as such, but something related.

author: mikerj
author_rank: Super Contributor
timestamp: September 16, 2014, 09:25:19 pm
content: Quote from: dannyf on September 16, 2014, 12:51:42 pmTo be fair he shows an SPI frame that clearly has separate device and register addresses.

author: hans
author_rank: Super Contributor
timestamp: September 16, 2014, 09:55:20 pm
content: I know that Microchip has I/O expanders (MCP23S17) that have addressing in it's SPI protocol, which is practically identical to the I2C protocol.With that chip you have 3 HW address lines so you can control 8 chips from a single chip select. That can be really useful for remote I/O switching applications with swappable daughter cards.As for the protocol.. well maybe they could have picked something more "legacy" SPI instead of copying the I2C, but for them it probably makes sense to reuse existing silicon (that parses commands), plus (the way I see it) there aren't many other ways to do it. The first byte needs to contain the chip address of those (Up tochips of a single CS line.

author: David_AVD
author_rank: Super Contributor
timestamp: September 16, 2014, 11:56:32 pm
content: Yes! I knew I'd seen it somewhere. It was on a MCP23S08 I/O expander where I used the addressing pins instead of separate CS lines.

author: dannyf
author_rank: Super Contributor
timestamp: September 17, 2014, 01:47:15 am
content: QuoteThat's a protocol implemented over SPI - the devices will only respond to the master if the right address, sent over the spi bus, is received. As far as the spi receiver is concerned, it is always receiving "data", which could be device "address", register address, or actual data.You can contrast that to i2c (which does support addressing natively): there is a frame that's dedicated to sending slave addresses under all conditions.

author: clifford
author_rank: Regular Contributor
timestamp: September 18, 2014, 08:23:18 am
content: Quote from: Alex Eisenhut on September 15, 2014, 03:44:38 pmSince no one mentioned this so far (afaics): The CS signal in SPI is not only used to select a slave. It is also used to determine the start of a transaction. Not only makes it a difference for some devices whether two bytes are transmitted with a single CS pulse or in two separate CS pulses. Without the CS signal you would also not know which bit is the first bit of a new byte. So the leading edge of the CS pulse is also used to synchronize byte boundaries between master and slave.

author: Scrts
author_rank: Frequent Contributor
timestamp: September 18, 2014, 10:20:57 am
content: Looking deeper into hardware: you need a CS pin for synchronization of internal registers. UART has stop bits, I2C has start/stop conditions, where you reset your registers in case there was something wrong in the transmission line.I've written a couple of communication cores for FPGAs. You need to re-synchronize the incoming data. Let's say for UART, if you'd use 2 stop bits, it would increase the effectiveness of synchronization and stability of the communication.

author: SirNick
author_rank: Frequent Contributor
timestamp: September 18, 2014, 07:40:09 pm
content: Quote from: clifford on September 18, 2014, 08:23:18 amYes, this and one other crucial thing:For SPI -- at least, with devices where communication is two-way -- you also need the CS pin to tell the receiving device to tri-state its transmitter. Otherwise, the selected device's reply would be clobbered by all the other devices that are holding the MISO line in idle state.For i2c, this isn't required, since it's an open-drain bus with a pull-up to keep the idle state. Devices only pull the bus low to signal a bit when they have something to say, and arbitration and hold-off timers resolve conflicts.

author: David_AVD
author_rank: Super Contributor
timestamp: September 18, 2014, 09:38:56 pm
content: Quote from: clifford on September 18, 2014, 08:23:18 amActually, I mentioned it about 10 posts ago:Quote