New GoLogicXL logic analyzer - Page 1
Forum section: electronics / testgear

author: BBledsoe
author_rank: Contributor
timestamp: December 17, 2014, 07:22:32 pm
content: Greetings EEVBlog Forum!This is Brian, a newbie with his first post. Please be gentle in case I'm being too pushy.I've been looking around the forums and reading the rules, but I didn't see a proper location for product announcements/discussions, so I thought to just roll the dice here in the TestGear category. Redirect me as needed.Anyway, I'm the engineer who's created all the software and analysis tools for NCI logic analyzers since 1992. We've released a new logic analyzer product, retired our old GoLogic, updated our web site with pretty photos and eye candy, and I wanted to get some feedback on all my hard labor if anyone is willing.I'm very curious: How many professional designers are here at EEVBlog? Can I get opinions from you folks on high-end logic analzyers (and especially mine)? Our tools compete against the super expensive benchtops rather than the lowest-cost tools that get all the web fanfare. I may be crazy, but I suspect the maker/hacker crowd has very little interest in GHz sampling rates and sample depths in the hundreds of millions.On the other hand, I've just produced and posted a bunch of tutorial videos on YouTube. Most of them cover the GoLogicXL software specifically, but a few videos use simple animations to describe basic ideas that apply to all logic analyzers and oscilloscopes. Specifically, hobbyists may be interested in my video on sampling methods. Even many professional EEs don't understand features like Transitional Timing or Glitch Triggering...I also plan to add more technical videos on how specific issues are captured and analyzed. For example, triggering issues with DDR state mode clocks, or differential signalling, or how to remove noise and glitches from trace captures, and so forth.Anyway, any feedback/suggestions is greatly appreciated. Thanks in advance.

author: marshallh
author_rank: Unknown
timestamp: December 17, 2014, 08:07:22 pm
content: Not sure how I didn't know about this. Anyway, it looks very well built and capable.I guess I could be considered a professional, this would've been really handy debugging 250MHz PIPE bus for USB3 phys. Ended up scoping a few signals and using a FPGA ILA for the rest.The problem with all the crappy low end analyzers like the Saleae and various chinese knockoffs is they are all but useless except for the simplest serial bus stuff. 16 channels is pretty much useless, since you can't even watch a 16 bit bus with it. No room for bus arbitration/control signals.At bare minimum you should be able to tap a synchronous 32bit bus. I am glad to see that your product does all that quite well. The most annoying part of using an LA like that is the probe connection. Again a problem with the cheap analyzers is they have 0.1" headers on flying leads with maybe one ground return for 8 signals. You need the return path to closely follow the signal as much as possible. You have it covered there (at some expense).Many of us here are small business guys, or loners that would have a more difficult time expensing a $5k analyzer. Personally, I would get a used 16500B mainframe instead.I think there is room in the market for a solution between $500-1000 that may not be as capable, but much better than the 8bit junk that sells for $100. One can get a basic FPGA board and use it to tap 50-100 signals with configurable I/O.

author: rx8pilot
author_rank: Super Contributor
timestamp: December 17, 2014, 08:18:09 pm
content: I am torn between a nice dedicated LA and an mixed signal scope. For my applications, I need to see the time correlation between data and analog to make it a perfect solution. I am a small business owner and make 100% of my living designing and manufacturing. Lowest cost is not my goal, but cost effective is. Many hours have been lost as I try to find some curious event and try to cross correlate data with the analog that started it all or resulted from it. So, if the cost is less than the hours I save in the next few months - sold. I have a Saleae, but rarely use it.trigger on defined data?possible to output a trigger for an external oscilloscope for time correlation?

author: tmbinc
author_rank: Frequent Contributor
timestamp: December 17, 2014, 09:20:38 pm
content: Oh, Wow! I was a very happy GoLogic-72-8M user a few (wow, 10?! already) years ago. It rocked. Unfortunately I had to give it to be used in a project, and never received it back. I got a Tek logic analyzer instead, and I hated it every minute.Unfortunately I currently can't shell out another few k for a logic analyzer, but if I could, it would most likely be a GoLogic. What I do these days is to either use an FPGA ILA, or some custom logic. I wrote different SDRAM-backed FPGA-based logic analyzers, but they were never great, mostly limited by the slow memory on my FPGA boards (DDR-2 @ 200Mhz doesn't let you capture very fast). I'd love to see a teardown of the GoLogicXL for some inspiration. Want to share any photos?If I remember correctly the first GoLogic used a Virtex-2 with SRAM and passives for the frontend.Now I'm seriously impressed how you get 4GHz. Likely not by using transceivers (for 72 channels) - maybe interleaved ISERDES?

author: rx8pilot
author_rank: Super Contributor
timestamp: December 17, 2014, 09:54:23 pm
content: I went to the web page and read and watched the videos. The scope link is interesting. Question, is it possible for an analog trigger on the scope to trigger/correlate with the LA data capture?

author: jeremy
author_rank: Super Contributor
timestamp: December 17, 2014, 09:54:52 pm
content: Interesting, but one thing to note: I can only hear the voice from the video in my left ear?

author: rx8pilot
author_rank: Super Contributor
timestamp: December 17, 2014, 10:04:02 pm
content: Quote from: jeremy on December 17, 2014, 09:54:52 pmUltra-Stereo. Key feature of the oxygen free helical wound gold plated probes.

author: BBledsoe
author_rank: Contributor
timestamp: December 17, 2014, 10:32:09 pm
content: Quote from: rx8pilotHm, I've never tried the reverse. I'll have to give that some thought. Of course, a scope with a trigger *out* signal permits you to connect a LA channel and trigger on the edge as needed. That time-correlates the LA and scope data. I would just need to download the scope data and ensure it's time-aligned.However, ScopeLink could not be used the way it works right now. ScopeLink automatically sets the scope for external trigger mode with the source on the GoLogicXL's trigger-out signal. ScopeLink also starts the scope running first, then the GoLogicXL, which must be reversed to make the way you envision the setup to work.On the other hand, the XL trigger is so much more flexible than most scope triggers that there's usually some way to make it work the way I envisioned.

author: BBledsoe
author_rank: Contributor
timestamp: December 17, 2014, 10:41:19 pm
content: Quote from: jeremyI know, I know. Sounds awesome on my speakers at work. Sounds awesome on my headphones at work.It took about 4 days just to upload those videos to YouTube in 720p. 81 tutorial videos. Eighty. One. Typing in all those titles. Copying the transcripts to the descriptions. Arranging and ordering the playlists. 81.And 4 days later I go down to the local cigar shop to have a stogie and test things with my iPad. And I get nothing but left-ear mono in my headphones. Grrrr.My work PC apparently has a sound card with "room effects" enabled, so I never knew. I recorded them all not knowing Camtasia was set to "mono" on my system.I may change my username to "LeftEar". Because, yeah, I meant to do that. It's my trademark. My thang. Email me at leftear@notamistake.com.Just don't make me re-do those dang videos.Seriously, the left ear thing is only slightly annoying with headphones. The audio quality is good enough to keep it from being truly awful. The greatest danger is falling asleep from my boring voice. So don't drive and listen.

author: BBledsoe
author_rank: Contributor
timestamp: December 17, 2014, 10:52:10 pm
content: Quote from: tmbincGood to hear from you! I know this is naive, but running into old customers didn't even occur to me when I started this thread. I hope only the happy ones remember me!We only recently stopped selling the original GoLogic. It's specs aren't that impressive any more. The new XL model is a much better performer.Quote from: tmbincThat's another good technical white paper I need to write: "How to use an external LA inside your FPGA".Quote from: tmbincTeardown?! My baby?! Nooooo! Seriously, I know teardown's are David's whole thing, but I cringe at the thought of anyone ruining an XL just to see how we did it. The FLIR camera teardown made me cry, especially when I looked up the price. Owie!Quote from: tmbincI'm a software guy, so 100% the wrong person to address that question. Besides, my boss would k-kill me if I disclosed any design secrets.But your "for 72 channels" makes me think I need to correct a misconception...SampleRate Channels Depth500MHz 72 134M1GHz 36 268M2GHz 18 536M4GHz 9 1BThis speed/channels/depth "resource scaling" is typical for all logic analyzers, and we take it far as practical with the XL. The original GoLogic did the same, just not so fast. It's also standard for logic analyzers to list the mostest, fastest, and deepest in the product synopsis without confusing tradeoffs. Our specs and brochures are very specific on how it all breaks down.At 4GHz or faster across more than 9 channels, I think your only option is a Keysight 16852A 68-chan running in half-channel mode. Or perhaps a Tek 7000 series mainframe. I'm no expert on their product lines though.

author: TiN
author_rank: Super Contributor
timestamp: December 18, 2014, 03:46:58 pm
content: Looks nice specced unit , but not sure for price point. 300MHz state and 1G timing might not be so great for 2015, as more and more speedy buses arrive, as well as more highspeed I/O today is serial.And still for 4K$ there are "solutions" on market, for those in need of faster/more channels LA, like used Tek 700/7000 series, on which even single 7AA4 module gives 136 channels at 800MHz state / 2G (8G) timing. It's totally possible to get frame and module for half of this budget. Yes, it's big and noisy and heavy, yes software on it is user-unfriendly (but still usable via remote PC connection), yes, probes are expensive (but it's a common rule for any decent LA, most of cost is in probes).Not saying portable LA is not needed, sometimes I find myself in situations where having LA which able just put into backpack is kinda necessary, but not as much to justify buying even Saleae Pro16Would like to see internal pics of it as well, teardown does not mean breaking everything.

author: free_electron
author_rank: Super Contributor
timestamp: December 18, 2014, 05:18:00 pm
content: Don;t tell me you guys are the OEM for the 32 channel logic analyzer bolt-on that LeCrap (LeCroy) uses. the box an probes look strikingly similar ...

author: BBledsoe
author_rank: Contributor
timestamp: December 18, 2014, 10:59:06 pm
content: Rx8pilot, I've been looking at scope models from Keysight/Agilent/Tek. It's very tough to find out which scope models offer trigger-out signals. It appears that the lower-price scopes do not (my Agilent 161024A lacks a trigger-out signal for example), while the mid-to-high range scope usually do offer a trigger-out signal (Tek MSO3000 has one).I'll talk to my boss about adding "reverse" mode to our ScopeLink wizard. I don't think it will be difficult, although I must think about the user-interface effects. For example, I'll have to "lock out" the GoLogicXL TriggerForms any time the "reverse" ScopeLink mode is active. Most of my time will be researching how the various models output their trigger signals. TTL, rising edge, falling edge, etc.Question for you Rx8pilot: I'm very curious about the kind of scope triggering you need that LAs don't offer. Can you give me some idea about the application? I'm guessing that it's some type of analog qualifier like a specific voltage level. Or is it something like a setup/hold violation?

author: BBledsoe
author_rank: Contributor
timestamp: December 18, 2014, 11:08:05 pm
content: Quote from: free_electronNot recently. Our original GoLogic product was indeed rebadged as their "MS-32" option back in 2004(ish?). Looong time ago. I believe that was their first stab at an MSO solution. But they dropped the MS-32/GoLogic years ago and we have no connections right now. Naturally, I'd love for LeCroy to adopt the new XL as a higher-end MSO solution.Quote from: free_electronDo you have an old MS-32/GoLogic? I just looked at the Teledyne LeCroy web site and didn't see any resemblance between the GoLogicXL and the LeCroy "LogicStudio" which only has 16 channels.

author: rx8pilot
author_rank: Super Contributor
timestamp: December 19, 2014, 12:01:49 am
content: Quote from: BBledsoe on December 18, 2014, 10:59:06 pmMy little world deals with digitally monitored and controlled power conversion and distribution. In my current power related project, the system has a lot of analog circuits that interface with an MCU based command and control. It is looking at fairly complex analog events that have to trigger a digital reaction of some sort. So, in this case, the instigating event is usually some unpredictable analog event. It is rather challenging with the independent (and low-end) LA and scope to work out a trigger that allows me to time align the event and correlate the digital reaction and analog result of that action. If my circuit is missing an event and I was triggering off of the digital data, I would never know that I missed something.I have been looking at Tek, Keysight, and LeCroy scope upgrades - all mixed versions. All have strengths and weaknesses in performance and user experience. They all have a significant cost associated with the LA integration and would never fully displace a dedicated solution. But, you can't argue with the ease of triggering and time correlation. On the other hand, the small display and 16 channels makes a solution like yours very interesting. More channels than I would ever need, fast, big memory, high-end analysis. As I move toward FPGA dev, a GoLogicXL looks rather interesting.As I am just about to make a scope purchase, this is timely. A mixed scope that is reasonable performance 1Ghz, 5Gs/s, large-ish screen is probably going to be in the ballpark of $15k++ . There are a TON of great high speed scopes only a few years old that are not mixed at around $5-7k. That would leave a solid budget to get a GoLogicXL with some probes. In theory, this would be a relevant configuration as I go into FPGA projects where I would need far more than 16 channels. The only thing is trying to figure out a bi-directional triggering solution so it behaves more like in integrated scope.

author: nctnico
author_rank: Super Contributor
timestamp: December 19, 2014, 12:11:22 am
content: Quote from: BBledsoe on December 17, 2014, 10:52:10 pmI have a Tektronix TLA704 + TLA7AA4 module (total investment $1000). This setup can sample at 8GHz and record 16k samples at that speed and 64 channels at 2GHz in half channel mode. Single channel depth is 32Msamples, half channel depth 64M samples. But the kicker is that it can be put in a mode where it samples only when the input changes because each sample has a >50 bit timestamp. This allows extremely long recordings with a lot of detail.I'm not sure whether using a PLL to synchronise to an external clock is the best option. In many cases the clock will be irregular. Tektronix doesn't use an external clock; they just use the 8GHz clock and an ASIC to derive the clock events from the input signal.However... IMHO the era of logic analysers has been over for a long time. High speed interfaces all use special serial protocols and FPGAs have too many internal signals to be probed efficiently with a logic analyser (for an FPGA you'd typically simulate and do logic analysis with a logic analyser inside the FPGA). An MSO will cover 99.9% of all logic analysis tasks leaving zero market for any logic analyser unless it is really cheap.

author: BBledsoe
author_rank: Contributor
timestamp: December 19, 2014, 11:57:52 pm
content: Quote from: rx8pilotThe first requirement to time align the logic analyzer and scope data is that the device which triggers on the event must pass along a notice to the other device via a trigger-out signal. This syncs both devices at a known point and is used as an alignment reference. The scope data and timing diagrams are aligned pretty close just by this technique. But there is always some prop-delay that requires further alignment.The second requirement is that the scope and logic analyzer must capture a common signal with some distinguishing features (ie - not a flat line). These signals are known to be the same in both the analog waveforms and timing diagrams, so I can use the edges and pulses to fine tune the alignment via software.Since you mentioned power, I wonder about high voltage/current. Can a logic analyzer probe and capture at least one of the analog signals your scope captures without being damaged? If so, then I don't see a problem with aligning the data.

author: BBledsoe
author_rank: Contributor
timestamp: December 20, 2014, 01:06:26 am
content: Quote from: TiNGranted, used gear is practically free on Ebay. I wonder how much gold might be inside those things? For that matter, I wonder why Tektronix doesn't buy up every old TLA7xxx module and accessory on Ebay and just crush them? It would make perfect business sense for Tek to remove them from the marketplace.I also find it very interesting that the older TLA7xxx prices are still OMG expensive at rental/refurb companies. Don't they ever visit Ebay? Is there some reason they don't buy up all the old stuff, crush it, or even resell it at a higher price?That subject aside, the GoLogicXL's specs compare pretty darn well against older TLA7AAx mainframe modules even when they are optioned out to the max. Things are a little confusing because the new mainframes are still called the "7000" series. For example, I'm pretty sure the 800 MHz State spec cited actually applies only to the newer modules. The older modules could be upgraded to 450 MHz, but the other state clock options were below our 300 MHz spec. I would also like to point out that the maxed sample depth for any module was 32M samples, which is oursmallestmemory option.It takes some digging around, but the max timing spec you cited was the "MagniVu" feature only (unless you meant the new modules which don't really apply). Tek tended to cite this feature as their max timing speed, which is technically true, but it's very confusing to me. The sample depth for "MagniVu" is very limited. The true timing sample rates for the full memory depth are 2 GHz across 1/4 channels, 1 GHz across half channels, and 500 MHz across all channels. The GoLogicXL doubles all those values to 4GHz, 2Ghz, and 1GHz. The XL also doubles the max TLA7AAx Glitch capture rate. It's unclear what the older TLA7AAx Transitional sample rates actual were. The new modules are at 1.6 GHz, so the old ones were likely at either 250 MHz or 500 MHz for Transitional mode.The TLA7AAx "MagniVu" feature provided 16K samples at 8 GHz centered around the trigger. That's a 2 microsecond time-window overlaid on the regular trace data. The GoLogicXL offers a high-resolution feature similar to Tek's (and Keysights), but we don't spec that feature as our max timing rate. Our trace overlay is captured at 4 GHz rather than 8 GHz.Quote from: TiNFor us, portability was only a secondary benefit to our design approach. Another extra benefit is that you can easily upgrade your logic analyzer's CPU and OS so the timing diagrams paint faster. But the main reason we "went small" with the original GoLogic-EPP 14+ years ago was to put the logic analyzer front-end close as possible to the signals. We can sample fast and get superb signal quality without using expensive active probes.

author: nctnico
author_rank: Super Contributor
timestamp: December 20, 2014, 02:56:22 am
content: Quote from: BBledsoe on December 20, 2014, 01:06:26 amThe reason is simple: nobody buys high end logic analysers anymore so there is no sense in raising the prices further beyond what is sensible. Many sellers on Ebay just look at the original list prices and think they can ask 50% of the original price where going prices are more like 2% of the original list price.QuoteYou better gathered some detailed information on the TLA7AA4 modules instead of making assumptions; these do up to 1.25Gb/s for double datarate acquisition. Glitch capture is 500ps but dependant on the probing solution. Transitional storage works at 500MHz however unlike other logic analysers that doesn't impact the memory depth because Tektronix added 30% more memory to hold a timestamp for each sample. But all these numbers don't mean much if you don't take probing into account. Tektronix' P68xx series probes load a signal with less than 1pf which allows to make meaningfull measurements at high speeds.BTW: the more recent mainframes from Tektronix are nothing more than a VXI bus to network adapter. I'm using my TLA704 in a similar way. The software runs on my PC and the TLA704 just obeys to what it is beying told over the network.

author: BBledsoe
author_rank: Contributor
timestamp: December 20, 2014, 05:46:50 am
content: Quote from: nctnicoThanks for your clarification! You are correct that the TLA7AAx modules can handle a 625 MHz state clock in 1/4 channel mode, 800 MHz in half-channel mode, or 450 MHz in full channel mode. The specs state that the 625 MHz state clock produces a 1.25 Gb/s value you mentioned.When TiN fist mentioned the TLA7AA4 modules, he stated 800MHz as the max state clock speed. Before my response to him, I downloaded the datasheets on the TLA7AAx modules and then did my best to digest the numbers. It's not easy. With the higest state speed options, the specs stated a maximum state clock of 450 MHz. The data was presented in a table and I simply overlooked the double and quarter channel modes to the right. The current generation TLA7AC3 module spec 800 MHz State which made me suspect he had confused the models.Quote from: nctnicoThanks again! I was unable to find that spec in the datasheet and had to guess Transitional storage was the same as the regular timing mode. I was unsure if the TLA7AAx supported Transitional sampling in half or quarter channel mode for faster speeds. I will be surprised if Trans mode is not supported at double/quad speeds since the State mode at 800 MHz on half channels is supported.Quote from: nctnicoWe've debated the same design approach over the years. From a documentation view, it's a wonderful idea because I don't have to explain why the the sample depth is reduced by half in Transitional mode. The side that always wins the argument is that we've put the memory in there, and the customer paid for it, so we might as well make good use of it when Transitional mode isn't used.Quote from: nctnicoTransitional Sampling cranked to the max rate is my preferred mode whenever possible. You always come out ahead in the trace time-span, even with less sample depth.Quote from: nctnicoWe offer two distinct State modes for high and low speed clocks. The PLL mode is intended for high speed clocks, although it can also be used with slower clocks provided of course they are regular/symmetrical. But for slower State clocks, we offer a mode that oversamples the clock signal and derives the sample rate indirectly. This mode is more flexible allowing up to 8 signals to qualify when the data is latched.Quote from: nctnicoIt's possible, although a Mux core is needed inside the FPGA. I hope to make this approach practical someday. Using an external logic analyzer for FPGA debug does have advantages...Preserve FPGA resources.Get a much better debug tool: more resolution, depth, triggers, etc. In other words, internal LAs are limited by the FPGA.Simultaneously capture inside the FPGA and outside signals.External LAs can be used for random tasks away from the FPGA. A high-end analyzer can always sample slower or reduce its trace depth.The main disadvantage is obvious. Spare BGA pins must be routed to a debug port on the PCB. It doesn't add significant cost to the PCB, but it requires care so that the signal routes are exactly the same length back to the debug port. And for some designs, it's simply impossible because either every BGA pin is allocated or there's no spare room near the FPGA for a debug port.

author: nctnico
author_rank: Super Contributor
timestamp: December 20, 2014, 12:02:07 pm
content: Unfortunately several features of the TLA7AA4 are described in the software manual. The Tektronix logic analyser software also requires to load firmware in the module for that software version.Regarding FPGA debugging:The way I have been doing that for over a decade is to have a multiplexer which can select which debug signals are output to 8 or 16 debug pins. Recently I inherited a very large VHDL project (Xilinx FPGA) which doesn't have that facility. One of the problems I have is that the design takes over an hour to route so changing something and testing it is a very lenghty process. I looked into Chipscope but it seems that changing which signals to probe needs a rebuild of the FPGA as well.All in all I'm reconsidering going the multiplexer+debug pins route. One of the downsides is that the debug signals need to be routed throughout the hierarchy of the design which makes things messy. I did find something which may allow to bypass the hierarchy: create a package with the debug signals. Where required the debug package can be 'included' and signals from the debug package can be assigned to the debug package directly. At the top level the debug signals can be picked up and fed into a multiplexer. This is supposed to work in simulation but it might be possible to synthesize it as well. I haven't tried it yet.About length matching to the debug pins: I wouldn't bother. If you want the debugging to be lightweight the routing from the source of the signals must be unconstrained from the internal flipflop to the pin. This will cause the FPGA software to choose a slow routing resource instead of using an 'expensive' fast one and possible cause a timing constraint to fail. There will be some skew on the debug pins but in my experience this skew is small enough to clearly see what is going on inside the FPGA. Most of the logic in an FPGA usually runs at speeds between 50 and 80 MHz anyway.

author: BBledsoe
author_rank: Contributor
timestamp: December 21, 2014, 07:31:59 pm
content: Quote from: nctnicoMy vision is an open-source MUX core with a defined standard available at OpenCore.org. I want Xylinx and Altera support of course, but hopefully other vendors would participate as well. I'd like the core to have these features...34 signals per MUX output.MUX has a 3-bit control register accessible from outside the FPGA via JTAG or whatever.2 bits in the control register offer 4 input selections per MUX. Route up to 136 signals to the MUX inputs. Select which group is active with the 2 control bits.1 bit in the control register is a test mode flag. Setting this flag disables all MUX inputs. The MUX automatically outputs a "walking one" bit to each output pin using the internal FPGA clock. This allows the signal paths from BGA pin to logic analyzer probe to be tested.Development platform integration from Xylinx/Altera/etc so that the JTAG/whatever port is used to define the MUX control register.Why 34 outputs? This matches up with standard logic analyzer probe types (Mictor, etc). Really nice to have when lots of signals are captured. If fewer are needed, then don't use them. If more than 34 must be captured simultaneously, add more MUX cores. I expect two MUXes would be the more than 99.9% of designers would ever need.Besides the MUX design itself, the only big hurdle may be getting Xylinx and Altera on board for integration into their platforms. It would be so nice to just pick an LA MUX option in the dev system, load a new logic analyzer project file in the LA software, then run and debug the design with no rebuilds or hassles. If the big guys aren't interested, I suppose the control bits could be defined via 3 FPGA pins routed to a header for jumpers. For obvious reasons, I'd prefer to use the fewest BGA pins possible. Another brute force approach would be to hardcode the control bits inside the FPGA. This is much quicker than carefully re-routing all the internal signals you need, but it would still require a project rebuild.

author: nctnico
author_rank: Super Contributor
timestamp: December 21, 2014, 07:44:11 pm
content: In my designs there usually -in the end- is some way to control a mux from a command line through a serial port. If that is not possible a dip-switch or jumpers could do the job. IMHO controlling the mux through JTAG just makes things more complicated. JTAG is definitely not the easy interface some people think it is. JTAG is just a physical layer interface. It needs a lot of software on top to make it do something useful.

author: BBledsoe
author_rank: Contributor
timestamp: December 29, 2014, 04:33:10 pm
content: Quote from: nctnicoI was thinking that since Xylinx/Altera toolkits use JTAG anyway, their software would control the MUX via the same port used for JTAG programming and debugging. That's what I meant by integrating the MUX control into their development systems.

author: free_electron
author_rank: Super Contributor
timestamp: December 29, 2014, 06:54:47 pm
content: Quote from: BBledsoe on December 18, 2014, 11:08:05 pmYep. The MS32. I had a shitstorm with LeCroy about that thing. They completely bodged the integration. Traces would disappear, zooming in on an area would display a different area etc ... Not your fault , Lecroy's fault.

author: BBledsoe
author_rank: Contributor
timestamp: December 29, 2014, 09:03:33 pm
content: Quote from: free_electronWow. That's the first time I've ever heard anything bad about their combo. I never used or tested it personally. It won product of the year for the now-defunc Test & Measurement magazine (for what that's worth).Our GUI works with the MS-32. So if you still have the analyzer, you can download the GoLogic v5.42 software from our web site. It's been a long time, but I'm pretty sure the MS-32 leadset lacks the dedicated clock input channels CA0 thru CA3. This means you can't do state mode or use the I2C triggering features. But all the other features should work fine.

author: Bassman59
author_rank: Super Contributor
timestamp: December 29, 2014, 09:26:37 pm
content: Quote from: BBledsoe on December 29, 2014, 04:33:10 pmI don't see how this "mux" concept is any different from Xilinx' ChipScope or the Altera equivalent. ChipScope works, and works well. Sure, you pay a penalty in terms of resources (especially BRAMs), but any other method of monitoring internal FPGA signals also has that penalty.

author: free_electron
author_rank: Super Contributor
timestamp: December 29, 2014, 09:29:01 pm
content: Quote from: BBledsoe on December 29, 2014, 09:03:33 pmtoo late. we shipped that hing , and the scope back and got our money back. anyway i don't work there anymore. -happy dance-

author: BBledsoe
author_rank: Contributor
timestamp: January 05, 2015, 05:10:53 pm
content: Quote from: Bassman59I guess it's a matter of degree. How much FPGA resources are used by a full logic analyzer vs. a simple MUX or two?If you have X resources left over after your design layout is done, then that's the internal logic analyzer (iLA) space available. Will the iLA core fit that space? If so, will you be have reasonable sample depth and/or triggers after routing the signals?The same resource issue applies to a MUX core. However, I'm pretty sure a simple MUX core is more likely to fit. An external LA offers better sample rates, sample depths, and triggering features than any iLA. The hassles involved are mainly one-time external PCB routing and internal MUX input issues.I suspect on a relatively small, quick FPGA design, an external LA wouldn't be worthwhile. But on more complex projects, it would be a very useful debug tool. Supporting this approach has been on my mind for a while, and when Nctnico mentioned the technique, I wanted to get some feedback if possible.Somewhat off topic, but a friend noticed that I linked to the wrong video in my original post. That "basics" video discusses how LAs operate, which I expect everyone here already knows. I intended to post a link to the video on how more advanced sampling modes operate, specifically Transitional Timing mode...