Lattice ICE40 instantiating RGB/IR pins as regular user IOs. - Page 1
Forum section: electronics / general

author: da075
author_rank: Contributor
timestamp: September 28, 2019, 12:35:07 pm
content: Hello..the ICE40 family has 3 dedicated pins for LED/IR connectivity (highlighted in the attached image), and they mention that these pins can be used as regular user IO pins. they even provide a verilog example (also attached) for using one of the pins as an output on page 34 (appendix b) oftechnical note TN1288, they also referencetechnical note 1253but none of these clearly explain how to use these 3 special pins as regular IO in a vhdl project.the code synthesizes correctly when adding the SB_IO_OD instantiation, however no matter which combination i try, i keep getting the very same error message during placement:Error during constrained IO placementE2792: Instance ipInertedIOPad_sadc0_4 incorrectly constrained at SB_IO_OD locationI2723: placment information file is dumped at : G:/work/icecube2/FPGAe/FPGA/FPGAImplmnt\sbt\outputs\placer\tmpTL.pcfI2709: Tool unable to complete IOPlacement for the designE2055: Error while doing placement of the designand this is how the module is instantiated in my vhdl codeCode:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;library sb_ice40_components_syn;use sb_ice40_components_syn.components.all;PIN39: SB_IO_ODgeneric map ( NEG_TRIGGER => '0',PIN_TYPE => "000001" ) -- << indicates an input pin.port map ( DOUT1 => open,DOUT0 => adc0(4),CLOCKENABLE => open,LATCHINPUTVALUE => open,INPUTCLK => clock,DIN1 => open,DIN0 => open,OUTPUTENABLE => open,OUTPUTCLK => open,PACKAGEPIN => sadc0(4));it would be really appreciated if anyone has worked on this FPGA before and could give me a pointer in the right direction as to how to make these pins behave like regular input pins using VHDL.

author: iMo
author_rank: Super Contributor
timestamp: September 28, 2019, 01:51:13 pm
content: Afaik there is a "rule" how the RGB pins are routed. Can't remember details, however..

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 28, 2019, 01:54:47 pm
content: Show us your top-level ports.

author: da075
author_rank: Contributor
timestamp: September 28, 2019, 02:14:32 pm
content: alright i think i have figured it out.the sb_io_od port documentation in icecube2' technology library is clearer on how to setup the parameters, so in order for instance to use the pin as input, we need to do 3 things,1- include the specific libraries.2- instantiate the SB_IO_OD module3- setup the proper parameters (can be figured out form the attached sb_io_od diagram from the technology library in icecube2 help)it is quite a big file, i was using the signal straight from the input pin (PACKAGEPIN) elsewhere in my vhdl code, and that caused the placement hickup, once i changed that and replaced it by the corresponding signal from (DIN0), the placement proceeded correctly.and thus, to use one of these 3 pins as input, the code to be inserted in the vhdl is the following:Code:-- first add the library referenceslibrary sb_ice40_components_syn;use sb_ice40_components_syn.components.all;---- .....--signal s_signal := std_logic := '0';PIN39: SB_IO_ODgeneric map ( NEG_TRIGGER => '0',PIN_TYPE => "000001" ) -- check the diagram for the input type you want and set the 2 LSBs accordingly.port map ( DOUT1 => open, -- leave openDOUT0 => open, -- leave openCLOCKENABLE => open, -- leave openLATCHINPUTVALUE => '0', -- i do not want to latch the input.INPUTCLK => open, -- leave openDIN1 => open, -- leave openDIN0 => s_signal, -- the internal signal to process and work with.OUTPUTENABLE => '0', -- disable the output.OUTPUTCLK => open,PACKAGEPIN => TopLevelInputName);but at any rate, this is not very documented online and this thread will maybe help someone in the futurethanks to the members who read and replied

author: iMo
author_rank: Super Contributor
timestamp: September 28, 2019, 02:21:50 pm
content: https://hackaday.io/project/6592-dipsy/log/25325-how-to-use-the-led-driver-pins-as-user-io

author: iMo
author_rank: Super Contributor
timestamp: September 28, 2019, 02:25:04 pm
content: BTW you may use the SPI programming pins as the user i/o too.I read/write the bitstream flash off the fpga's userland that way (load/store the FORTH dictionary).

author: da075
author_rank: Contributor
timestamp: September 28, 2019, 02:41:00 pm
content: IMO, true, i am using them as well, i however need all the IO pins i can get on this chip, so it is crucial that i let no pin go unused

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 28, 2019, 02:42:13 pm
content: Well, those FPGAs have a very limited number of IO's, so you can hardly waste any.

author: iMo
author_rank: Super Contributor
timestamp: September 28, 2019, 06:18:20 pm
content: Anyhow, in the above link is the verilog version from hackaday (not tested by myself yet)..