MCU ADC input overvoltage tolerance - Page 1
Forum section: electronics / projects

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2016, 05:28:16 am
content: Hi all,I'm designing the front end for an ECG data acquisition system as part of my senior design project. We're using an ADuCM360 microcontroller which has 2x 24-bit ADCs. It says its input range is 0-1.2V (Vref). So, I've designed the front end thus far to amplify and provide the appropriate DC offset to get the signal to fit neatly into that envelope under normal operating conditions. However, the parts in the front end are powered off 3.3V, which means the ADC could potentially see ~3.3V.To mitigate that problem, I designed a diode clamping circuit with a 1.2V shunt reference. However, using low leakage diodes like 1N4148s means the clamping range is ~-0.6-1.8V.I can't find any absolute maximum ratings about how tolerant the pins are, but would would this be an acceptable range?Thanks a lot,Tim

author: trophosphere
author_rank: Frequent Contributor
timestamp: November 03, 2016, 06:16:59 am
content: Per the datasheet, the absolute Absolute Input Voltage Range of the ADC for unbuffered mode would be from AGND to AVDD. For buffered, it would be (AGND+0.1) to (AVDD-0.1). What is your voltage on AVDD?

author: danadak
author_rank: Super Contributor
timestamp: November 03, 2016, 01:06:01 pm
content: The spec for the A/D pins of 100 mV outside rails is "usually" a spec oflinear operation for the A/D input stage, not a limit or destruction occurring.Usually pins have a ~diode drop absolute max rating, that would triggerparasitic SCR that exists on I/O pins and shorts internally the supply rails,typically blowing open the power supply bond wires to the die. Anotherissue is charge injection into the substrate affecting circuit operation, if SCRnot triggered.Best way to protect pin is a pair of schottkys' on pin. Or limit current with Rso that SCR triggering does not occur.Regards, Dana.

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2016, 02:43:32 pm
content: Quote from: trophosphere on November 03, 2016, 06:16:59 amAccording to the datasheet, AVDD = VREF = 1.2V (provided you use the internal reference).

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2016, 02:47:14 pm
content: Quote from: danadak on November 03, 2016, 01:06:01 pmThanks Dana. That's kind of what I figured. It seemed that the specification was referring to what range of voltages would be accurately converted, not so much the tolerable voltage range.Ideally, I'd like to use a shunt regulator with Vz < 1.0V so that the theoretical cutoff would be closer to VREF...but 1.2V is about as low as they make them.Hoping that a cutoff a half volt above the upper limit of the ADC won't be a problem.

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2016, 02:48:48 pm
content: Quote from: blueskull on November 03, 2016, 01:09:15 pmThanks for that info.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 03, 2016, 03:07:21 pm
content: FYI, avoid using a diode clamp because the knee will be rather soft, causing significant distortion at much lower signal levels. It may not be much, but I can only assume you got the 24 bit ADC for a reason, and that that reason has quite severe demands!Likewise, low voltage zener diodes are less than useless, and not really available low enough anyway.A biased diode is okay, i.e., set a voltage reference at the maximum threshold, then use a clamp diode into that. The actual clamping voltage will be Vf + Vref, but the leakage will be small for voltages below Vref.You can also arrange the buffer amp (if there is one) to drive the ADC input through a resistor, with that resistor included in the feedback loop. Feedback ensures zero voltage drop across the buffer+resistor as long as the buffer can supply whatever current (through the resistor) is required; but as current rises (as the clamp diode conducts), the buffer output will saturate, and the signal will clamp much more sharply.Or as long as you're saturating op-amps -- you can simply put a voltage divider on its output, so it saturates to +V/GND at the same point where the ADC input saturates (well, a little beyond that, rather).Tim

author: ajb
author_rank: Super Contributor
timestamp: November 03, 2016, 03:44:06 pm
content: Another option is to use an additional op-amp in a comparator configuration as a precision clamp. See this post:https://www.eevblog.com/forum/projects/limiting-op-amp-output/msg440944/#msg440944Or maybe look for an above-the-rail input/RR output op amp that you can power at 1.2V as a final buffer stage. Not sure if there are any such parts that would be suitable for your 24 bit application.Note that with any solution that involves saturating op amps, the time it takes for the op amp to come out of saturation will limit the response/recovery time.

author: trophosphere
author_rank: Frequent Contributor
timestamp: November 03, 2016, 04:57:21 pm
content: Quote from: TimNJ on November 03, 2016, 02:43:32 pmI don't think that is quite right because the allowable range for AVDD is from 1.8-3.6v. In addition, the difference between AVDD and IOVDD must be less than or equal to 0.3v. Hence, I was asking what the input voltage to your AVDD pin was as your front-end is being fed a 3.3v supply rail and why can't you use that as AVDD and not worry about any damage from over voltage.

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2016, 05:26:32 pm
content: Quote from: trophosphere on November 03, 2016, 04:57:21 pmThank you. Great catch. AVDD is definitely 3.3V according to the schematic for the dev board we are using (EVAL-ADICUP360).From page 22 of the Hardware User Guide, under the section PGA Gain Configuration,"When the PGA is enabled, the PGA output voltage must not exceed 1 V... To determine if the ADC input is about to exceed the 1 V PGAoutput threshold, the ADC comparator can be used."So it looks like the ranges they specify might be more to do with the PGA than the ADC input. I don't think we were planning on using the PGA...so it looks like the ADC can be used safely with voltages up to AVDD (3.3V). In that case, I should probably adjust my the front end circuit for for a higher gain...That being said, does it still make sense to use my 3.3V rail for the diode clamp? Perhaps a 2.5V reference like an LM431 so that the cutoff is around 3.0V. (The lower end will unfortunately still be clamped below 0V though). By the way, to clarify, this is the type of clamp circuit I'm talking about.

author: senso
author_rank: Frequent Contributor
timestamp: November 03, 2016, 05:41:04 pm
content: Quote from: T3sl4co1l on November 03, 2016, 03:07:21 pmI once did that with a clc1011 with a 1k resistor on the output and I oscilated with a dc-input, yay :/

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 03, 2016, 05:48:06 pm
content: Quote from: senso on November 03, 2016, 05:41:04 pmWell sure, if you have a capacitive load, you need to compensate it!Ideally, the feedback time constant R2*C1 equals the output time constant R3*C3. Different values lead to lower frequency response, or peaking.Tim

author: trophosphere
author_rank: Frequent Contributor
timestamp: November 03, 2016, 05:51:05 pm
content: If you are still going with a 3.3v single supply for your analog front end then the maximum voltage that could be ever be present to your ADC input would be 3.3v as your gain stage(s) would go into saturation for a larger than expected input signal. Theoretically you would not need a voltage clamp between your analog front-end and ADC at all.That being said, the voltage clamp you have designed would do the job for protecting against over-voltage. A small amount of voltage above or below the limit is acceptable as long as you have current limiting which you have done with the resistors. If you want to protect against defibrillation then that is a whole other thing in itself.

author: senso
author_rank: Frequent Contributor
timestamp: November 03, 2016, 06:04:15 pm
content: Quote from: T3sl4co1l on November 03, 2016, 05:48:06 pmThe load was an SPI or i2c cheapy adc(not that capacitive, and I got the idea from some high performance TI ADC datasheet), I had the habit of designing pcb's for the sake of designing pcb's and then trying the results, not everything would work first try..

author: Siwastaja
author_rank: Super Contributor
timestamp: November 03, 2016, 07:17:06 pm
content: As a side note, I just accidentally had a 5V powered faulty amp inject 4.7V, without any current-limiting resistor, to an ADC input of STM32F334, which further lifted the AVdd supply (3.6V nominal) to around 4.1V through the protection diodes. This violated maximum AVdd of 3.6V, maximum input of AVdd+0.3V, and maximum DVdd to AVdd difference of 0.3V quite seriously and I had it powered up like this for minutes while looking for the issue. Very surprisingly, the MCU seemed to survive just fine; after changing the faulty amp, the ADC works just like before. I'm somewhat surprised; there must have been quite some current flowing through the protection diodes.

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2016, 08:21:42 pm
content: Quote from: trophosphere on November 03, 2016, 05:51:05 pmWow I'm an idiot. It looks like there was never a problem to start. Thank you.

author: TimNJ
author_rank: Super Contributor
timestamp: November 03, 2016, 08:26:38 pm
content: Quote from: T3sl4co1l on November 03, 2016, 03:07:21 pmWe chose an MCU with a 24-bit DAC for no good reason other than the board was priced right, seemed to have a solid analog section, and had an ARM core which we are familiar with.We are considering switching to a less powerful MCU but we're not sure if it's going to be beefy enough to handle some DSP duties. I wonder how terrible an MSP430 would be doing filtering on a single datastream...We're also crunched for time and with limited knowledge so keeping it simple (Energia perhaps) is somewhat compelling.Sorry to change topics.

author: trophosphere
author_rank: Frequent Contributor
timestamp: November 03, 2016, 10:09:42 pm
content: @TimNJ: It's all good. We all have made mistakes and learn from them. I once killed a couple thousand dollar board because I set my voltage too high as I thought I was dialing in 3.3v but instead put in 33v on the keypad and that was without thinking of setting a current limit.As an aside of an aside, if you have a bit of time, you can make more use of your microcontroller by using its on-board DAC to vary the virtual ground of your analog front-end to do two things: (1) Compensate for baseline wander secondary to respiration (2) Dynamically set your baseline so that you can use the full range of your ADC's analog input range in case one portion of the signal, such as the QRS complex, causes saturation.