[solved, I think] Altium, Differential Signals, Harnesses and Net Labeling - Page 1
Forum section: electronics / projects

author: aandrew
author_rank: Frequent Contributor
timestamp: August 27, 2018, 06:50:57 pm
content: I'm at my wit's end trying to figure out how to *efficiently* route differential signals from different schematic sheets.Overview:I have an FPGA connected to five digitizers. Each digitizer has a clock in, clock out, data bit out, start and end signals. Each of these signals is a differential pair. I've put the digitizer subcircuit on its own schematic page, and have the toplevel schematic sheet with a single digitizer sheet with REPEAT(DIG,0,4) representing the five copies of this circuit. The sheet entries for those signals are straightforward enough: each is named and placed in a REPEAT() command, e.g. REPEAT(CLKIN_P), REPEAT(CLKOUT_P).These sheet entries are then brought out to wires with net labels, and those wires are gathered into buses and fed into a harness. The other end of the harness breaks them out into buses and those buses (not individual nets) are fed into the FPGA sheet.Problem #1 is that the digitizer-side of the harness has six harness entries, one for each PAIR (not individual signal): e.g. one entry is "CLKO_P[0..4], CLKO_N[0..4]", another is "CLKI_P[0..4], CLKI_N[0..4]" etc., etc., but on the FPGA side, I'm trying to break that out to make use of sheet entry buses, so one harness entry on that side is "CLKO_P[0..4]" and "CLKO_N[0..4]". Altium complains of this, and I can get around it by breaking the digitizer-side harness entries into 12 instead of 6.Problem #2 is the naming of the nets. Altium wants to see FOO_P and FOO_N for differential pairs, but you can't use repeating entries and get those. You get FOO_P0, FOO_P1 etc. I don't see a way to name them that way using [#..#] and I really don't want to use net ties to rename the nets. Altium's not a hobbyist tool; I must just not know the correct way to do this, but the online documentation from Altium is garbage when it comes to anything beyond the simple stuff.Pictures always help:The toplevel schematic page, showing me trying to connect 5 digitizer sheets to an FPGA sheet through a harness. I know I'm naming the buses wrong on the FPGA sheet entry, I'm trying to make Altium name things differently but it's not working:The digitizer schematic page, repeated 5 times in the toplevel:And the FPGA page, where I'm trying to rename the nets from the bus format FOO_P[0..4] to something which makes more sense here, which would be FOO_P0, FOO_N0, FOO_P1, etc.:I've clearly got myself painted into a corner here. Can anyone help me untangle myself?

author: free_electron
author_rank: Super Contributor
timestamp: August 27, 2018, 07:13:40 pm
content: Try thisuse CLKO_P[4..0] counting down !and you need to keep the positive and negatives in separate buses.

author: aandrew
author_rank: Frequent Contributor
timestamp: August 28, 2018, 02:07:19 am
content: Quote from: free_electron on August 27, 2018, 07:13:40 pmI'm not sure what this is going to achieve; the bus is defined correctly using CLKO_P[0..4] and CLKO_P[4..0]; but if I try to get the "iterator" in the middle of the net name, the bus name ends at the iterator. e.g. CLKO[4..0]_P will show the bus as "CLKO[4..0]" (no _P).QuoteThis definitely cleaned up the harness errors, thank you! Now if I can figure out a way to rename a bunch of nets without calling each individual one out in a net tie... this would be ideal.

author: jbb
author_rank: Super Contributor
timestamp: August 28, 2018, 06:37:59 am
content: Quote from: aandrew on August 28, 2018, 02:07:19 amFind and replace :-)Also, if you want a plain rename, I suggest you review the changelist in the ECO before pressing 'Execute' (or whatever it is) to make sure you've done it right.Stragglers can be easier tp clean up by filtering, e.g.OnCopper and Not InNet('*')

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 28, 2018, 11:26:42 am
content: Also, something about REPEAT not working at zero, you have to start at 1 for some reason?Tim

author: aandrew
author_rank: Frequent Contributor
timestamp: August 28, 2018, 04:06:59 pm
content: Quote from: jbb on August 28, 2018, 06:37:59 amNo, I don't mean like that.The bus entries MUST be named CLKI_P[0..4], for example (with the index at the very end), but on the digitizer page, I'd like to have then named CLKI0_P/N, CLKI1_P/N (e.g. the index inside the name, not at the end).I'm not sure how/if I can do that.I can create a harness with CLKI_P[0..4], but I can't "join" that harness to another harness that has those five signals in a bus broken out to five individual signals: CLKI_P0, CLKI_P1, CLKI_P2, CLKI_P3, CLKI_P4. If I could do that (with a monster harness) then I could just wire up each individual signal and name it accordingly within the digitizer sheet.I can't create a bus named CLKI[0..4]_P because the array specification must be at the very end of the signal name.I could break out the bus to individual wires, use net ties to another set of wires with the names how I want them, but... ick.It's hard to imagine that Altium doesn't have a way to do this.

author: aandrew
author_rank: Frequent Contributor
timestamp: August 28, 2018, 04:07:43 pm
content: Quote from: T3sl4co1l on August 28, 2018, 11:26:42 amI am definitely not having any trouble with the repeat starting at zero, perhaps this is an old bug?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 28, 2018, 06:31:41 pm
content: Interesting, they must've fixed that finally.Tim

author: aandrew
author_rank: Frequent Contributor
timestamp: August 29, 2018, 06:30:38 pm
content: So I think I got it.I placed each diffpair into a diffpair harness, then brought those harnesses into a larger one. I could then bring that harness over to an intermediate schematic sheet which just broke things out so that I could then get the individual _P and _N signals into buses which allowed me to bring them into a REPEAT(..)ed schematic sheet.Toplevel:Interconnect/intermediate sheet (no parts, just signal breakout and recombination):And finally, the connection to the FPGA:Thank you everyone for your suggestions and your help. I find it interesting that the Altium 18 docs say that index 0 is not supported, yet I'm not having any issues with Altium 17.1.

author: Lautaro
author_rank: Newbie
timestamp: November 06, 2019, 09:46:14 pm
content: in Altium 19 I just short the nets , the outputs of the repeat with the diff pairs. The compiler didnt complain.