Optical Rotary Encoder - Page 1
Forum section: electronics / projects

author: MuchMore
author_rank: Contributor
timestamp: August 20, 2019, 11:15:29 pm
content: HeyI was planing on using some Bourns EM14 encoder. However they are using 5V on VCC and my µC is on 3.3V. So I was wondering if the output signals are open collector type, than I can just pull them up to 3.3V and have no problems. But if they are internally pulled to 5V I will have to level shift.Has someone used them before?Thanks

author: Ian.M
author_rank: Super Contributor
timestamp: August 20, 2019, 11:22:30 pm
content: RTFM! Hint: seedatasheetspec VO(HI)

author: langwadt
author_rank: Super Contributor
timestamp: August 20, 2019, 11:25:45 pm
content: Quote from: MuchMore on August 20, 2019, 11:15:29 pmdoesn't look like open collector, put series resistor or voltage divider on the output

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 20, 2019, 11:30:41 pm
content: This encoder does not just contain passive switches, it requires a 5+/-0.25V power supply to operate (see datasheet). It contains a LED/photodiode or phototransistor and a small ASIC.

author: mark03
author_rank: Frequent Contributor
timestamp: August 20, 2019, 11:34:11 pm
content: The requirement for 5V on [virtually?] all optical encoders is one of those marketplace mysteries which defies explanation. There's nothing inside the package that needs 5V, and it makes interfacing with most modern systems slightly annoying. Presumably, manufacturers are using 5V because all of their peers are too. (This is possibly related to the "we don't implement feature X because there's no demand for it" fallacy, with the 'evidence' being that no one else offers feature X either)

author: MuchMore
author_rank: Contributor
timestamp: August 21, 2019, 05:07:32 am
content: RTFM I did, but was not able to say how to connect it.So if the manual states: "Output Voltage High 4.0V minimum" it is an activ output so I have to level-shift.

author: Ian.M
author_rank: Super Contributor
timestamp: August 21, 2019, 05:23:48 am
content: Yes, the VO(HI) spec indicates that you can expect a minimum of 4.0V @Vcc=4.75V. That's slightly over one diode drop below Vcc, which means the output stage probably has a bipolar active pullup. Also note that although its specced to sink up to 25mA when at logic '0', no spec is given for how much current it can source at logic '1', so using a simple potential divider for level conversion would be unwise.I'm assuming your MCU doesn't have 5V tolerant inputs (which would be the easiest), so either you will need to use active level shifters (e.g. 74LVC2T45), or in some way block the logic '1' level from the encoder from reaching your MCU. allowing you to use a pullup to 3.3V to provide a safe logic '1' level to the MCU. This could be as simple as a Schottky diode, cathode towards the encoder, + a pullup to 3.3V on the MCU input, but if that doesn't give you enough margin on the logic '0' level once you've added the Schottky diode Vf drop, you may need to resort to a N-MOSFET, gate to 3.3V, source to the MCU + pullup and drain to the encoder in place of the diode, as is commonly used for I2C level shifting.

author: MuchMore
author_rank: Contributor
timestamp: August 21, 2019, 08:27:19 am
content: I was planing on useing 820/1500Ohm divider. and 10k pullup on the GPIOat 5V that only needs source ~3mAat 0V it need to sink ~0.3mAlogic low would be at 0.25V (ESP32 < 0.8V)logic high at max 3.3V (ESP > 2.4V)Do you have any arguments why this should not work?

author: Ian.M
author_rank: Super Contributor
timestamp: August 21, 2019, 09:41:14 am
content: I strongly suspect the EM14 cant source the >1.8mA your idea needs when its output is at logic '1'. Its fairly obviously designed to have a bipolar TTL compatible output and typically their IOHsourcing capability is poor, e.g. a 74LS00 output is only good for 400uA and at that load current the output voltage may drop as low as 2.7V. *IF* you are going to use one, I would strongly recommend increasing your potential divider resistors by an order of magnitude.Also, if you are using a potential divider, you don't need a pullup to 3.3V on the MCU side. It can only compromise your logic '0' level.

author: MuchMore
author_rank: Contributor
timestamp: August 21, 2019, 01:29:21 pm
content: okok I will put two IRLML2502TRPBF according to : NXP AN10441

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 21, 2019, 02:17:30 pm
content: Quote from: MuchMore on August 21, 2019, 05:07:32 amSince it's just outputs and rise/fall times are probably absolutely not critical here, you can just use resistive dividers to level-shift. No need for anything fancy. If you have doubts about the output current, use higher values for the divider. They state "Output Current I(SINK), per Channel = 25mA max". At 1/10 or even 1/100th of that you should get perfectly workable thresholds. Don't hesitate to experiment though, will be pretty easy to do.Now I must insist (probably obvious though). This encoder requires a 5V supply, so this is not just a matter of level-shifting the outputs. You need a 5V supply in your system. If it's just for the encoder, that may not be very practical. If your power supply source is below 5V (such as a battery), you'll need a step-up converter just for that. Sorry if this is obvious.Just a couple questions. Are you sure you absolutely need an optical encoder? A mechanical one would not have this limitation. Mechanical encoders are used everywhere. So except if you need exceptionally high reliability, is it worth it?For 3.3V optical encoders, you can take a look at the Grayhill 62A series:http://www.grayhill.com/assets/1/7/Opt_Encoder_62AVD.pdfNot cheap though.

author: MuchMore
author_rank: Contributor
timestamp: August 21, 2019, 03:19:34 pm
content: The rise and fall times are absolutely critical here.I tried an mechanical encoder (Alps) however the signal was too polluted.Digital debounce was not possible because there is not enough steady state time, at fast rotation. Including an smoothing cap was not possible because the esp32 will trigger 1000 times on slow edges. an analog read takes to much time, and is too noisy.I already need an 12V supply for an 0-10V output. So I will get an IRM-03-12 followed by an TPS56339 buck converter and an LP2985A-50 LDO for clean 5V to an MCP4728 ADCSo I already have 3 different voltages.... adding another LP2985 does not matter anymore.I excluded the Grayhill ones because they are >45€ while the Bourns is ~30€

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 21, 2019, 04:37:34 pm
content: Quote from: MuchMore on August 21, 2019, 03:19:34 pmI don't know what your application is exactly and what you're trying to do, but I don't see how rise/fall times could be *that* critical. The DS states 200ns typ. for the outputs. Adding a resisitive divider even with relatively high resistors values, considering the input capacitance of the MCU I/Os, will maybe lead to a couple µs. Multiplying by like 10 the values you were considering would not lead to slower that this IMO. How bad is that for a rotary encoder, even if it's rotating very fast?Quote from: MuchMore on August 21, 2019, 03:19:34 pmHow fast is it going to rotate? If your system can rotate it at very slow to very high speeds, I understand that usual debouncing techniques (be it analog or digital) will be tricky to pull off.And anyway, I was more thinking about manual rotation. If the encoder is constantly rotated at high speeds, I agree that an optical encoder is the obvious solution."Interestingly", The Grayhill encoders in 5V version are around 20€ and over 40€ in 3.3V version... Completely nuts.

author: Ian.M
author_rank: Super Contributor
timestamp: August 21, 2019, 06:24:30 pm
content: I agree. Lets do the math.Even if you use the 64 pulse/rev variant, and put a spinner knob on it so you can twiddle it maybe up to 10 revs/s, its only going to give you 2560 edge events per second so you shouldn't have any problems as long as rise/fall times are of the order of 200us or better.N.B. its life is specced at 30 RPM so its almost certainly unsuitable as a high speed shaft encoder. 10 revs/s is 600 RPM and even if the high speed doesn't drastically shorten its life, the non-detent version is only rated for 2000000 revs operating life, which you'd exceed in under 56 hours at that speed.Consider a resistive divider of 82K upper and 150K lower resistors, driving an input capacitance of 50pF. That divider, worst case only needs 215uA of IOHso is fine driven by *ANY* TTL output and gives you a Theivenin equivalent resistance of approx 51K, and a time constant of 2.65us (which is a 5.8us risetime). That should be plenty fast enough if its being sampled by a MCU.OTOH if you are using a fast hardware QEI module that has a sub us spec for maximum rise & fall times, you can still use a passive divider. The raw rise & fall times of the encoder are specced at 200ns, so there isn't much more than an order of magnitude improvement to be had. Dropping the divider resistors to 8K2 upper, 15K lower get you down to a time constant of 265ns, at the cost of a worst case IOHrequirement of 2.15mA. If it craps out before you draw 2mA, a 470R pullup at the encoder output will fix that as it has plenty of IOLsinking capacity, but will be a power hog. Calculating the rise time when the time constant is comparable to the input waveform time constant is a PITA, so I simmed it in LTspice with .measure statements for the risetime and got 608ns.If you *still* need faster edges stick a speedup capacitor across the upper resistor of the divider, of approx double the input capacitance, to form a capacitive divider with the input capacitance.

author: dom0
author_rank: Super Contributor
timestamp: August 22, 2019, 11:45:19 am
content: Quote from: Ian.M on August 21, 2019, 06:24:30 pm21.5 µAQuote from: Ian.M on August 21, 2019, 06:24:30 pm215 µA

author: Ian.M
author_rank: Super Contributor
timestamp: August 22, 2019, 11:56:48 am
content: Thanks for the correction. Sorry about the bad maths. With those revised figures, it makes sense to go straight to the 8K2, 15K divider and it definitely wont need a pullup on the encoder output.

author: arduinew
author_rank: Newbie
timestamp: May 11, 2020, 10:36:38 am
content: sorry but cant seem to find a current topic re Optical encoder logic..Am trying to solve a puzzle - to divide the o/p of an optical encoder rate by 2, using logic gates, currently at 2400 ppr, down to 1200 ppr.Simply feeding A&B signals into D latch FF doesnt work- it ends up with a 45 degree phase shift, not 90 degrees.Logic must cope with reversal without missing a single step.Much searching has revealed nothing concrete yet.(I suspect that reducing it down to 1800 ppr would be much harder!)

author: Ian.M
author_rank: Super Contributor
timestamp: May 11, 2020, 11:34:28 am
content: @arduinew,Hi-jacking old topics is not a good way to attract expert replies here. Next time, *PLEASE* start a new topic for your query or preferably whole project in the most appropriate sub-forum you can find.With that out of the way, you are going to need to implement a state machine locked to the original A and B signals, that update the divided A and B signals every other state transition to get 1200 PPR. If the encoder outputs are clean, you may be able to make it self-clocking, but that would be considerably more complex vs an external clock. I haven't analysed the problem in detail yet, but I would expect it to take up the better part of aEurocardof LSI logic chips. A better solution would be to implement the state machine in a CPLD or small FPGA, or if the maximum shaft speed isn't too high, in a small 8 bit MCU.Getting 1800 PPR would be *MUCH* harder, due to the non-integer division ratio, and doing so without angular jitter would be impossible unless the original encoder has sinusoidal analog outputs that could be used to increase its effective resolution. You've got 9600 input edges per turn, and to generate 1800 PPR outputs, you need one output transition every 2.6666 input edges. That's just possible as the ratio is greater than 2 but the relative phase of the quadrature pulse train will jump to and fro by one interval between input edges, i.e. 0.0375 degrees of jitter.