KiCAD - NPTH vs. Cut out? - Page 1
Forum section: electronics / general

author: Time
author_rank: Frequent Contributor
timestamp: March 28, 2012, 03:15:43 pm
content: Ok, so I guess let me explain what I am trying to do here:I am using an RF mosfet driver, the DEIC420 (http://www.ixysrf.com/pdf/driver_ics/deic420.pdf), and I'd like place a cutout around the body of the device so it settles down into the board - allowing for me to get at it from both sides for heat sinking. Plus I wouldn't have to bend the legs down to meet the board and I could minimize their lengths even further.I am using KiCAD and at first I made the footprint for the device and placed a non-plated through hole (NPTH) specified in the pin placement settings, I believe it was. I made it the correct dimensions and positioning. After bringing this into the layout environment I noticed it was a weird color. I couldn't really tell what layer it was on. It was kind of a gross green/brown color (top and bottom layers super imposed?). I tried spitting out some gerbers and viewing them but the area seemed like it showed up as a big copper pad on the top and bottom layers. This is not what I was going for, obviously.My question is: is this the correct way of achieving this kind of cut out in your design with regards to KiCAD? Does this sort of thing have to be done in the layout environment or can it be specified in the footprint design? I would prefer the cutout just be part of the footprint itself since its orientation and positioning with regards to the rest of the pads is important. Additionally, I would like to reuse the footprint without having to do the cutout manually in the layout every time.Any advice or thoughts will be much appreciated. I can provide some screen shots later this evening (PST) if needed.

author: madworm
author_rank: Frequent Contributor
timestamp: April 02, 2012, 10:15:19 pm
content: Could you post an image?It's unfortunate that currently you can't add routing / milling / tracks to footprints in KiCad. You can add copper, but it doesn't get recognized as a valid track and DRC may throw errors.

author: Time
author_rank: Frequent Contributor
timestamp: April 03, 2012, 06:50:26 pm
content: Sure, let me do it this evening if I can remember.

author: madworm
author_rank: Frequent Contributor
timestamp: April 04, 2012, 07:58:49 pm
content: In your own time ;-)

author: Time
author_rank: Frequent Contributor
timestamp: April 05, 2012, 02:40:05 pm
content: Its going to have to be this weekend because I am quite busy this week - sorry.I really want some advice still though!

author: Time
author_rank: Frequent Contributor
timestamp: April 07, 2012, 01:33:07 am
content: see attached screenshots.

author: madworm
author_rank: Frequent Contributor
timestamp: April 09, 2012, 08:14:44 pm
content: Hmm. Didn't get a notification again :-(So the center part should be milled out, right? With that assumption I've put together a footprint. See the attachment.Process of creation:* draw cut-out area in module editor as outline* place pads* ...* export module to file* change layer of the outline from 21 (top silk) to 28 (pcb edges) in a text editorCode:[...]$MODULE xPo 0 0 0 15 4F834212 00000000 ~~Li xSc 00000000AR xOp 0 0 0T0 0 -2283 600 600 0 120 N V 21 N "x"T1 0 2756 600 600 0 120 N V 21 N "VAL**"DS 0 -1575 1575 -1575 150 28 <--DS 1575 -1575 1575 1575 150 28 <--DS 1575 1575 -1575 1575 150 28 <--DS -1575 1575 -1575 -1575 150 28 <--DS -1575 -1575 0 -1575 150 28 <--[...]I think you must have a talk with the fab-house to make sure they use the right size of router-bit, or the pads will be damaged. I don't know how they would interpret that inner cut-out line. Either as the outline of the area or as the routing path (bad).

author: Time
author_rank: Frequent Contributor
timestamp: April 09, 2012, 11:14:29 pm
content: Great, thanks for your suggestion.

author: madworm
author_rank: Frequent Contributor
timestamp: April 10, 2012, 10:49:11 am
content: On 2nd thought, I think it might be wiser to put the internal routing into a separate layer (like e.g. ECO1 - layer #26) and add some more text there to specify router bit size etc. and how the information should be interpreted.Otherwise they might feel inclined to use their standard router bit size for the board edges, which is likely too large. That may or may not lead to edges with a too large internal radius.