reading op-amp output with ADC strange delay - Page 1
Forum section: electronics / beginners

author: doobedoobedo
author_rank: Regular Contributor
timestamp: November 28, 2015, 01:40:43 am
content: I'm using an LTC2050 (http://cds.linear.com/docs/en/datasheet/2050fc.pdf) as a low side current sense amplifier with a 0.5mohm shunt. I'm measuring the current using an atmega328p ADC which is using PWM on a mosfet to regulate power delivery to a load. I'm also sensing the high side voltage.Readings are triggered by an interrupt in order to sync with the PWM signal. I can read the high side voltage at any time during the duty cycle and I get a very consistent value, however I have to wait approximately 200us before reading from the LTC2050 otherwise the reading is low (the earlier, the lower) I don't have a proper scope yet. I've modelled it in LTSpice and according to that I should get full output from the opamp after 3us.Any pointers/ideas as to what might be going on?

author: Simon
author_rank: Unknown
timestamp: November 28, 2015, 07:26:27 am
content: by high side voltage do you mean the supply voltage ?, could it bee that you need to wait for the current to start flowing in your load ? what is your load ? the best thing to do is low pass filter the output of the opamp and take readings off the average current at any time, do you actually need cycle by cycle readings ?

author: Kleinstein
author_rank: Super Contributor
timestamp: November 28, 2015, 10:03:53 am
content: Auto zero OPs need quite some time to get out of saturation. This can be on the order of 100 µs. As the output may not reach negative values of even all the way to V-, it is possible that the OP goes into saturation if no current is flowing.

author: doobedoobedo
author_rank: Regular Contributor
timestamp: November 28, 2015, 12:12:18 pm
content: Quote from: Simon on November 28, 2015, 07:26:27 amThe load is a low resistance heating wire. I do need cycle by cycle readings. High side voltage is the battery voltage which is being read through a voltage divider.Quote from: Kleinstein on November 28, 2015, 10:03:53 amThe opamp is supposed to be rail to rail according to the datasheet (linked in the first post). When no current flows both inputs and the output should be at 0V. You think this is the problem? Can you suggest a way to get around it?

author: Kleinstein
author_rank: Super Contributor
timestamp: November 28, 2015, 12:40:11 pm
content: Rail to Rail may only work to something like 1 or even 50 mV to the rails at the output. So at zero current the OP could be just in saturation even less than 1µV of offset voltage or some load the OP has to drive can cause this.A way around this would be adding a small offset (e.g. 10 µV at the positive input) so that the output will not need to go below somthing like 10-50 mV.

author: doobedoobedo
author_rank: Regular Contributor
timestamp: November 28, 2015, 02:39:01 pm
content: Thanks.I must admit I'm not keen on introducing an offset, so I'm thinking using something like a TC1044S (http://www.farnell.com/datasheets/129144.pdf) might be a better option so it doesn't hit the negative rail.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 28, 2015, 04:18:44 pm
content: I would avoid the charge pump - they produce quite some ripple on the supply up to rather high frequencies. A small offset will only loose something like 1% of the ADC range. The ADC might have an offset of +- 1 LSB anyway so digital correction is not making things worse.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: November 28, 2015, 04:43:21 pm
content: Hi,You can try this:The modification introduces an offset equivalent to 2A.This is the modelling results:I have attached a zipfile with the LTspice model.Regards,Jay_Diddy_B

author: doobedoobedo
author_rank: Regular Contributor
timestamp: November 28, 2015, 06:54:02 pm
content: Quote from: Kleinstein on November 28, 2015, 04:18:44 pmI did wonder if it would introduce unwanted noise/signals@Jay_Diddy_B Cheers I adjusted my spice model to match yours. If I change the 499k to 10M the offset (50uV) produces an output below the resolution of the ADC which I can certainly live with. Can anyone foresee a problem with that?

author: Kleinstein
author_rank: Super Contributor
timestamp: November 28, 2015, 08:52:14 pm
content: Depending on the load, the small offset might be enough. But at about 3 mV output the OP can not sink much current.The carge pumps use relatively low resistance FET switches to charge the caps. So the current flow it not continineous, but in short pulses (e.g. 10 µs) at about 1 kHz clock. Peak current are thus somthing like 100 times higher than output current. There is also the bucket capacitor with a full 5 V rectangular swing, that can cause electrostatic coupling if not properly shieded.

author: doobedoobedo
author_rank: Regular Contributor
timestamp: November 28, 2015, 11:13:51 pm
content: Thanks for your input. I'll do some experimenting.At least I have an idea of the cause of the delay and a couple of different options to fix it.