PSU design, a compensation network question - Page 1
Forum section: electronics / projects

author: Yansi
author_rank: Super Contributor
timestamp: February 10, 2016, 07:42:17 pm
content: Hello,I have dug out one of my older projects - a regulated PSU with somewhat not-so-much common topology. I'd like to consult with you the output power stage design.Consider a situation like this: As the opamp supply voltage is low (or cannot be high enough to use only simple voltage following common emiter stage on the output), we need to amplify the opamp's output voltage a bit, using a discrete stage. What I have done... er.. wanted to do was to use a voltage controlled current sink (T1). This current sink pulls a PNP darlington stage (T2+T3) in sziklai-pair configuration (as it is much easier and common to use NPN power device). The opamp supply will be about 12-15V, the collector voltage of T3 could be up to 40V or so.The resulting circuit is atatched. It is not complete, I have omitted all protection circuitry, so I know that T1 has to be current limited, T3/T2 reverse bias protected, etc... The schematic has only a principle-purpose, and I have added some component values of roughly what I think they should be in the final design.The question is, how to make such topology stable. I have drawn all places where a cap could possibly be added, and denoted such places as Cx. The question is, how to figure out what place is the correct one and how should it be done.From a small circuit breadbording session, I conclude such output configuration can be used. I have observed, that by placing an output capacitor Co of about 100uF, the circuit is stable, no problem. By removing Co, the circuit oscillates.What is the required procedure to figure out the correct compensation networks? Or do you suggest using another more reliable discrete amplifier stage?Sorry, I am not such advanced circuit designer to write down all transfer function and compute all compensation networks according to control theory requirements. If I could do that, I wouldn't be asking such stupid questions.The circuit is only partial and the whole supply design will require more labour.Thank you for your help,Yan

author: Kleinstein
author_rank: Super Contributor
timestamp: February 10, 2016, 08:31:37 pm
content: Stabilizing this design does not look easy, as there are two transistor (T1 and T2) stages with gain.Normally I would use a simulation like LTspice to check on this - it's rather simple. So no need to calculate transfer functions by hand.You will definitely need C1. I don't think C4 is really helpful as this is a emitter follower stage.C2 would make the output of T1 a voltage controlled signal and would thus compromise PSRR. So I would prefer not using C2.There are several possibilities for compensation, not just one.Using C3 would make the design more like a conventional supply with an emitter-follower output. As there should not be two integrators active at the same time C1 would need a series resistor in a way to have C3*R1 at about 1/10*C1 and the extra Resistor. My initial guess would be C3 = 5 nF and C1 = 10 nF + 10 K.Without C3 the output stage is more current controlling, like a LDO. In this case C5 (with a resistor of about R6/10 in series) is likely needed.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 11, 2016, 11:35:51 am
content: Enhance for readability:Don't leave current protection as an afterthought -- and don't just expect the circuit to behave itself, because most likely it won't! Provide limits for it, right away, so that everything is bounded to only the range of values it needs to cover. Then, determine the amount of gain required to transform from one bounded range (namely, the op-amp output) to another (the driver/follower).So, if your op-amp has a 10V range, you need T1-T2 to amplify that to 0-40V, say. T1 can cover the full range, and if it does 0-1mA over that range, R3 should be 10k. (As shown, it's got a gain of 15, which is *way* more than the total gain needed here, so you're already inviting oscillation with that!) Now V and I are bounded, so there's no worry about limiting anything!T2 is tricky. It has to have voltage gain, because of two things:1. You can't waste gain on emitter degeneration, because that would waste saturation voltage. That's why R4 is small.2. It has to drive T3, and not much else. The divider R5-R6-R7 is high resistance, and bootstrapped by T3; any additional load at Vo will directly affect voltage gain.So we should probably not design this stage as a voltage gain stage, anyway. It's a current source.Supposing we want, say, 3A output current, and if T3 min hFE is 20, then we need max 150mA from T2 (which by the way, will have to dissipate up to 6W, and T3 up to 120W, so you better use beefy devices with lots of heatsinking!). If we want max 1V dropout from T2, then we have to use R1 = (1.7V) / (1mA) = 1.7k (so T1 actually has <1 voltage gain, but that's fine, it's only doing level shifting), and R4 = (1V) / (0.15A) = 6.7 ohms. (4.7 isn't far off, and 6.8 would be the closest standard value.)So that looks pretty reasonable. Now for compensation. We need to get the loop voltage gain under 1 by the op-amp's GBW (and probably sooner than that, due to phase shifts). Cx3 is probably the best candidate, because it's where the voltage gain is happening, and by applying NFB here, we can somewhat turn the CCS into a CVS, which is good for Zo, and for keeping gain stable against load variations.If the loop gain should be 4, and the divider is 1/4, then we should have unity gain around GBW, let's say 3MHz if it's something like an LM358. T1 drives 1mA/10V of transconductance into Cx3 (which we're assuming is dominant at this frequency, so we can ignore R1, and assume T2 is simply following along as an integrator due to Cx3), so we'll have a voltage gain of 4 when X_Cx3 = 4 / (1mA/10V), or 1.3pF. (Which isn't much, so we might increase T1's transconductance. Which should probably be done anyway, because 1mA max assumes T2's min hFE is 150, which is plausible but kind of optimistic.)To help with phase margin, some Cx1 can be placed across the op-amp, but with a resistor in series, of value comparable to R6 || R7 (give or take how much gain/phase margin is actually needed; takes some tweaking to decide).So the full changes should be:R3 --> 1k (let's say)R1 --> 220 ohms (optionally, with a diode in series to get a more linear transfer function on T2)R4 --> 6.8 ohmsCx3 --> 22pF (for starters?)Cx1 --> 10k + 100pF?If you also want to try a Cx5, put a resistor in series with it, so it doesn't dominate over Cx3. This gives you a lead-lag compensation, where the two RC networks can have different time constants, kind of twisting/shearing the Bode plot, allowing for more phase margin, or compensating much more ornery loads (such is common for voltage mode SMPS, where the two pole (LC) output filter is fully in the loop).Tim

author: Yansi
author_rank: Super Contributor
timestamp: February 11, 2016, 02:21:26 pm
content: Thank you guys for the analysis. However, it is not as easy as I've drawn it. Maybe too much simplification.The power rail was denoted as "up to 40V" as there will be a tracking switchmode pre-regulator, supplying this circuit with about Uo+5V. (let's say the power rail voltage will be in between 5 to 35V). Output current will be 2A maximumum.So due to the tracking preregulator, no "beefy devices" are required and those two seleced will do very well, considering the thermal characteristics.The protection circuitry is not an afterthought, it was only omitted in the schematic diagram for clarity. I can draw them, if needed.A small correction: R5-6-7 is not divider, R5 is Rbe resistor for T3 and only R6-R7 is the feedback divider. (or... I don't get it what you've ment with that)The power stage was calculated very similarly to what you have done, my values are pretty close to yours. (R1 about 1.5K, R4 about 5ohm). Your insight into the circuit helped me understand some things little clearly. I will now describe my "thinking process" again, and try to implement some of thoughts:The reason why I chose R3 to be so low is more obvious, when we consider operation at 5V power rail supply (I should have specified more clearly the presence of pre-regulator). We need to have enough voltage margin to fully open the power stage, so considering 1V drop over T2 means 4V left, so obviously we cannot have R3=10K for 10V/1mA, as that wouldn't work, so we have to limit voltage drop accross T1 to about few volts. Then R3 has to have a drop of 2V max.If I remember right, I have calculated the circuit considering gain of T3 to be 20, gain of T2 to be 50. That means at least 2mA of pure base current of T2 is needed, therefore the T1 operating current has to be more than that, let's say 5mA which still gives reasonable power dissipation on T1 (about 175mW at full rail voltage of 35V and full output load).Now let's calculate the minimum required voltage gain for the discrete stages. We know due to the minimum rail voltage of 5V, we need to limit the R3-T1 voltage frop to only about few volts. We need 30V full output, that means we need a gain of about 15.Now how can I deal with this? As I am still getting same values for all those resistors. R3 can't be any higher, as it would limit the ability of proper function at low rail voltage of 5V.Thank you for help,Yan

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 11, 2016, 03:41:04 pm
content: For lower dropout, T1 can't have so much voltage across it, so it needs to operate over a smaller voltage range.Which means a smaller voltage swing from the op-amp as well.Using an op-amp with 10V supplies would be silly, because you're wasting, say, 5V or more of its range. However, we can limit its range, by using a R2R op-amp and a supply of 5V (or whatever it needs to be limited to), so it simply doesn't have the voltage to swing outside of our desired limit range; or by using a resistor divider on its output, yes, to reduce gain before increasing it again. Nothing wrong with that, and it neatly solves the bounded-range problem for the whole system.It could also be placed on a negative rail, so the transistor's base has a maximum value of GND, thus allowing the pre-reg supply to go very nearly to zero.Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: February 11, 2016, 04:31:37 pm
content: The circuit shown will have a rather poor PSRR. So it may not be the best choice in combination with a preregulator.If current consumption is not that critical, I would consider using just a constant current source instead of T2 - thus a completely different (inverting) output stage.For the current regulation it would be important to know where the shunt is, as this resistor also has an influence on stability of the voltage control loop.

author: Yansi
author_rank: Super Contributor
timestamp: February 13, 2016, 10:57:54 am
content: T3sl4co1l: We have probably misunderstood each other:You suggest decreasing gain of T1 wildly, by placing R3 as 1 to 10K. I tried to explain it as impossible to do, because of voltage drop constraints on the T1 collector with respect to ground. So only dividing the opamp output by a divider can be done (if it helps the stability??)The problem with large R3 is that too much base-to-gnd voltage for T1 would be required to pass enough current for T2. That would limit operation below certain voltage.Negative OPamp supply or rail-2-rail type aren't allowed for this design, as I am targeting a lowcost hybrid PSU design using a buck preregulator and linear pass element. The OPamp was chosen to be LM324. (I know, it is a shit for most of you, but I am not trying to design a high-spec supply, only a basic one, but with still reasonable performance and durability) But maybe I'll add the negative rail, haven't really figured out some aspects of the circuit.I will try to breadbord the compensation networks and see, what I can do with it (if anything...)Kleinstein: Using current aource instead of T2 - I understand what you mean. But it'd be better to add another tranny for that purpose and change the current T2 to NPN (to form a darlington pair with T3).But I'm rather unsure how woul'd it help the circuit to stabilize or improve PSRR, as loading T1 with current source instead of R1 will cause very rapid increase in gain of that stage.

author: Yansi
author_rank: Super Contributor
timestamp: February 13, 2016, 11:16:01 am
content: Kleinstein, did you mean doing this? Or what current source have you though of? (psudesign2.jpg)One more idea, what about a local feedback? Would it help anything or would it only introduce next level of instability? (psudesign3.jpg)Similar output stage with such local feedback was also used in a TEXAN amplifier...PS: The current shunt will be located in the negative output terminal.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 13, 2016, 12:41:21 pm
content: The circuit of psudesign2.jpg is what i thought of. Compensation is still not easy, but looks easier than the original circuit. as there is only one gain stage.Local feedback like in psudesign3.jpg can be a good idea, but it will also cause a higher level at the input of T1. This could be avoided if using the local feedback for higher frequencies only (capacitor in series to the resistor). The local feedback can also improve PSRR, as it can counteract the signal around T2 being referenced to the upper supply. With sufficient local feedback the output stage would be a low impedance output.

author: PChi
author_rank: Frequent Contributor
timestamp: February 13, 2016, 01:00:56 pm
content: Adding gain within the feedback loop of an operational amplifier could be tricky.How about using an LM723 that includes a reference and a current limit circuit rather than an LM324?

author: Yansi
author_rank: Super Contributor
timestamp: February 13, 2016, 05:38:51 pm
content: LM723 is an old dog that cannot be taught to new skills,easily. It can't work from 0V output, it is not ready for variable current limiting, it cannot be easily wired for remote voltage sensing. But all of these can be done easily with just 3 opamps and using the 1 left for preregulator control. Quad opamp is really what I need here.Kleinstein: Okay, I will test that too, but won't be easy I think.EDIT!! Sorry, dumb me did draw the psudesign2.jpg wrong, the polarity of feedback of course should be inverted.By the way, I have the circuit with the current source currently on my breadbord, and oh! Very little tweaking was required to make it stable :-O But still, haven't done thorough tests of stability and overall behavior.

author: Yansi
author_rank: Super Contributor
timestamp: February 13, 2016, 11:33:18 pm
content: So what I have breadborded this evening was this circuit. Behaves quite well, but only about 1uF loading, sometimes it goes into low frequency oscillation (about 160Hz), which I don't have explanation for. Strange. With 20uF or more, it looks stable (but almost every circuit with large capacitive load looks stable).What is the correct way of using compensation networks for this circuit? Use miller capacitor on T1 or T2? Use feedforward cap accross R5? How to figure out the time constants of those against each other?I have tried to measure some step responses with load changes (loads appropriate for the T2 being BC547, I was lazy to connect another bunch of current gain stages), getting nasty overshoots (mostly with ringing afterwards) even with the larger 20+uF output cap. Not good. Compensation/damping wrong or not enough of it.There's only one bit I don't like about this circuit: The inverted polarity of the feedback. This way I need a buffer on the reference input, i.e. another opamp, which I don't have spare, or I'd have to add one (4+1) into the design. (you cannot drive the 2K7 input with variable imepdance source, as that'd change the time constant)PS: The current source was a BC557 with a red LED as a reference, sourcing about 4,5mA.Thanks,Yan

author: Kleinstein
author_rank: Super Contributor
timestamp: February 14, 2016, 09:49:27 am
content: There may be no extra compensation needed for T1,T2. Just the input impedance T2 might be enough. One can see this as a voltage controlled current source, just as in a LDO. One might add a RC combination from the collector of T1 to ground or the base of T1, but not much, not to interfere with the compensation at the OP.Like with a LDO one could use an additional lead stage with a RC combination in parallel to R5.With a smaller capacitor one might get away with more than the 2.7 K at the input (e.g. 10-20 K range), so that driving by a pot should be possible without to much of change in time constant. Also changing the divider R1/R2 might help to use a larger time constant at the OP.As an addition there should be a diode to protect the output transistor from excessive negative base emitter voltage. This will than requires a kind of current limiting for T1, as T1 will than work as a kind of down programmer.The most difficult load for most regulators are large low ESR capacitors (e.g. 10 µF ... 10 mF) combined with a constant current sink.

author: Yansi
author_rank: Super Contributor
timestamp: February 14, 2016, 11:05:45 am
content: Okay, will have a play around with those two compensation networks. By the way, what is the correct procedure (step-by-step) to tune the compensations?I'd like to have a 100uF output cap (seems reasonable to me) in the final design. With such cap connected, it is "just" stable without any compensation attempts. But that is not correct, I think.What I usually do is to measure step responses and try to make them better. Is it correct? Or do I need to tune those without the output cap or.... just how? Is there some rule of thumb how to proceed?Sure, I can change the ratio of R1:Cc near the opamp to get higher input impedance. But still I think it is kind-of silly to have the circuit dependent on impedance source. The potentiometers will not be present on the PCB itself, so there is a risk of someone connecting a different than suggested value. (As I will make the design public, if it happens to work)Of course T1 needs to be current limited an those BE junctions reverse-bias protected. As I've mentioned, some parts of the schematic were omitted for simplicity.So here's the more complete schematic as what I think it should be like with all the protection circuitry:T1 being current limited to a safe level of not being burnt, BE junctions protected by a small diode D2. And the whole protected by two beefier diodes of D1 & D3.

author: Kleinstein
author_rank: Super Contributor
timestamp: February 15, 2016, 07:55:20 pm
content: The way I look at a supply is first looking at the transistor part only, and check / tune for a reasonable well behaved ouput impedance and a good trans-conductance (Output current into a AC short = large cap as a function of controlling voltage).It also depends whether you do tuning in real hardware or based on a simulation.For tuning with a real hardware, the early rule of thumb was trying a small output capacitor first, than reduce the compensating capacitor at the OP to the point where it starts oscillating and than increase the capacitor by a factor of about 5 for the final setting. One may also increase the output cap, or add a second in parallel. It's a little like tuning a PID controller with classical Nichols Ziegler rules.In a simulation I prefer looking at the output impedance. The step response is than the final check.

author: Yansi
author_rank: Super Contributor
timestamp: February 20, 2016, 06:35:23 pm
content: So finaly I got some spare time to continue with this supply. The las topology (with the current source from top above T2) seems to work. But I have interesting "problem" going on:No load the output is fine and stable, noise is below what my scope could catch. After loading the output, a noise appears. About 6mVpp of that. Isn't that too much? Something might still be wrong with the circuit topology. (see my previous post and psudesign5.jpg).Could you please advice, if such noise is expectable, or something is wrong? I think due to the current fed voltage amplifier stage, too much gain is present inside the feedback loop.Thank you, YanEDIT: 7mVpp / 1,7mVrms of noise present on the output after decent loadingEDIT2: After adding some tens of puff accross CB junction of T2 (the current source), the noise was further reduced to about 4mV pp and 1,2mVrms. But I still think something have to be wrong, the circuit should not produce such noise, should it?