LTspice stability of control loop - Page 1
Forum section: electronics / projects

author: golaz123
author_rank: Newbie
timestamp: April 03, 2017, 07:54:43 pm
content: Hi,I am trying to design a constant current source and am having troubles with simulating open-loop gain and stability of the control loop. I've used 2nd technique from this video:.This is the circuit:and this is the open-loop gain plot:Is this correct approach to simulating open-loop gain? How can I intrepret the results? Why does it start at negative gain?Phase at 0dB point is -137°. From transient analysis I know this solution is unstable, but how can I "see" this on the plot? I know that system is potentialy unstable if phase margin is less than 45° and gain margin less than 20dB.So these are my calculated values (as I see it): phase margin is |-180-(-137)|=43° and gain margin is 3.1dB (gain at -180° phase shift). Is this correct? Both phase and gain margins are below minimum acceptable values?Why is there a 450° (5x90°) phase shift? 90° from U3, 90° from M1 Cgs, 90° from M3 Cds, 90° from U1, 90° from where?Once I have a valid plot, how can I know what to do to increase the stability, obvious solutions are C1 from U3 output to its inverting input, C2 from U1 output to its inverting input and R in series with U4 to U3 inverting input. But how do you know what each element adds to stability?I know there are alot of questions here, but I just really want to understand whats going on here :-DI really appreciate your help!

author: danadak
author_rank: Super Contributor
timestamp: April 03, 2017, 09:44:12 pm
content: An approach w/o breaking the loop -https://sites.google.com/site/frankwiedmann/loopgainhttps://sites.google.com/site/frankwiedmann/loopgain/GFT_SPICE.doc?attredirects=0http://www.intusoft.com/gft.htmRegards, Dana.

author: tombi
author_rank: Regular Contributor
timestamp: April 05, 2017, 05:19:41 am
content: Ok not an expert at this but...Shouldn't you bias it into operation when checking the loop gain?So I thought you would want to set V6 to turn on some current flow through the MOSFET. Then you can see the effect of perturbations on the loop at different frequencies.Tom

author: Zero999
author_rank: Super Contributor
timestamp: April 05, 2017, 10:32:22 am
content: Quote from: tombi on April 05, 2017, 05:19:41 amYes, I've been bitten by that one before.https://www.eevblog.com/forum/projects/better-ltspice-tl072-model/msg1003248/#msg1003248

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 05, 2017, 06:01:59 pm
content: I will see if I can help, but first a few questions.- Are you really intending to use Nch transistors?- What are you using to simulate the opamps (voltage-controlled voltage sources)?I do not use LT Spice (I use B2.Spice) so am not familiar with a resistor value of "11k4" as shown for R5.As far as accounting for five poles, you will need to draw an ac equivalent circuit including all of the capacitance of the active devices (Cgs, Cgd, Cds, etc.).You need to show me quiescent voltages (the .op voltages) on all nodes. It appears to me that the circuit is biased improperly (thus no low-frequency gain).

author: Zero999
author_rank: Super Contributor
timestamp: April 05, 2017, 06:06:13 pm
content: Quote from: Wimberleytech on April 05, 2017, 06:01:59 pmLTSpice recognises prefixes such as k, R and Meg (not M which is milli as it's case insensitive, hence Meg is used for mega), used as the decimal place, so 11k4 is 11 400Ohms.

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 05, 2017, 06:53:01 pm
content: Ah! How cute for LTSpice to offer that XkY nomencature. Looks like you can turn it off in the control panel.

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 05, 2017, 07:23:20 pm
content: "Why is there a 450° (5x90°) phase shift? 90° from U3, 90° from M1 Cgs, 90° from M3 Cds, 90° from U1, 90° from where?"You are misreading the phase plot. It goes from -90 to -360 for a total of -270 degrees phase shift. Looks like one zero and three poles.

author: golaz123
author_rank: Newbie
timestamp: April 06, 2017, 01:20:32 pm
content: Quote from: tombi on April 05, 2017, 05:19:41 amThanks for the info. I've set V6 to 0.1V and got a completely new plot (that looks way way more correct).Quote from: Wimberleytech on April 05, 2017, 06:01:59 pm- Yes, I want to use N-channel MOSFETs because input voltages can range anywhere from 1V to 60V.- I am using a universal (more or less ideal) op-amp models.This new plot has a phase margin of -57° so its completely unstable and a gain margin of +43dB, again unstable. The system has two poles, one at about 10Hz (dominant pole of op-amp?) and one at about 60kHz or there about. How can I get rid of these problems and create a stable system? What would be a thought process behind this?Best regards!

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 06, 2017, 02:17:07 pm
content: Remove R4 and short R3. Run it again.

author: golaz123
author_rank: Newbie
timestamp: April 06, 2017, 02:32:08 pm
content: Quote from: Wimberleytech on April 06, 2017, 02:17:07 pmI need U1 to have 124x amplification.

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 06, 2017, 02:44:52 pm
content: U3 offers another 100dB (more or less) of amplification. You do not need 140dB loop gain.

author: golaz123
author_rank: Newbie
timestamp: April 06, 2017, 03:40:31 pm
content: Voltage across R2 will be from 300uV to 30mV. Output of U4 goes to ADC and V6 represents DAC. I need 124x amplification to scale voltages to full range of ADC/DAC.

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 06, 2017, 06:37:03 pm
content: OK, put a cap across R5. Create a dominant pole.