EasyPath FPGAs - Page 1
Forum section: electronics / general

author: Stonent
author_rank: Super Contributor
timestamp: November 09, 2015, 10:01:22 pm
content: So I was reading about these today. For those who don't know about them, Xilinx will sell you a cost reduced "identical" FPGA when you need to go into production. They seem to be using as a step between FPGA and ASIC. The claim is that once you go into production, you will no longer need a general purpose do-it-all FPGA and can instead do with one that's guaranteed to do what you've programmed it to do.My first thought was rejected silicon that may have failed part of a test that doesn't apply to your situation, or binning like they do with processors, (sort of like the 486DX and SX processors, the FPU either failed or was disabled in the SX), but some further reading on some other sites indicate that the wafers roll off the same equipment, but instead are only tested against your code and not all possible variations. It may be a perfectly fine Virtex 7, but they only run the tests that will apply to your code. The other claim is because it is the same silicon from the same line, you won't have to re-qualify and re-test the final design like you would have done with the design redone as an ASIC.What I didn't see was do they do anything to prevent these from being reused, or are the still fully re-programmable?Are these EasyPath chips something that is commonly used in the industry or do most people just use the full FPGA or stamp out an ASIC?More Info:http://www.xilinx.com/publications/prod_mktg/easypath-7-frequently-asked-questions.pdfhttp://www.eejournal.com/archives/articles/20080527_easypath/

author: photon
author_rank: Frequent Contributor
timestamp: November 10, 2015, 01:03:51 am
content: My understanding of the cost reduced FPGA is that it is no longer programmable. What is done to reduce the price per part is to make a mask of the FPGA with all logic tied off. So, unlike an FPGA, there is an upfront cost (NRE) for the mask which is cheaper than the NRE for an ASIC, but per part cost is less that a regular FPGA per part cost. It only makes sense for a larger number of parts. If you need a really large number of parts, then an ASIC beats it on all fronts (power, speed, die size) except NRE.

author: marshallh
author_rank: Unknown
timestamp: November 10, 2015, 03:23:15 am
content: Altera have done this for a while (i think they quit) with the HardCopy parts. It's $50k to get started or so, which is pretty cheap.

author: amyk
author_rank: Super Contributor
timestamp: November 10, 2015, 06:29:29 am
content: Quote from: photon on November 10, 2015, 01:03:51 amIn other words, it's like an FPGA with mask ROM.

author: coppice
author_rank: Super Contributor
timestamp: November 10, 2015, 06:56:35 am
content: From the descriptions I have read Xilink offer you their defective parts, with the bits your design needs guaranteed to work, as EasyPath devices. You get about a 35% discount for this. Altera use a totally different die, optimised as a mask programmable ASIC. That die will be massively smaller than the equivalent FPGA, as the vast majority of an FPGA's silicon is dealing with programmability, rather than the actual logic of your product. You pay the NRE for a metalisation mask set, and you effectively get ASICs.I wonder just how equivalent the Altera masked parts are? Coming from a different die, there will be timing differences.Your simulation should have achieved timing closure before you finalise a design, so any timing difference should be on the "better" side. However, any change in timing to the outside world might potential have unexpected effects.

author: photon
author_rank: Frequent Contributor
timestamp: November 10, 2015, 06:48:39 pm
content: Interesting. It may be that the full-blown FPGA has low yield and EasyPath is a means of improving their yields. What I don't understand is the name. What does "Easy" refer to?

author: coppice
author_rank: Super Contributor
timestamp: November 11, 2015, 03:20:20 am
content: Quote from: photon on November 10, 2015, 06:48:39 pmThe hard path to cost reduction would be moving to an ASIC. Easypath is the, er, well, you get the idea.

author: Stonent
author_rank: Super Contributor
timestamp: November 12, 2015, 05:56:52 am
content: Quote from: photon on November 10, 2015, 06:48:39 pmWell an ASIC will technically be a completely different chip which could have its own quirks that you may have to work with or design around. A custom ASIC should almost always be faster than an identically configured FPGA which could cause some problems if the rest of the hardware isn't expecting it to respond faster.If you're designing a product that may be subject to some kind of regulation (RF Emission, Medical, Vehicle, Intrinsic Safety), you may be required to have it retested or re-certified which could add additional cost and time to your product's launch.

author: coppice
author_rank: Super Contributor
timestamp: November 12, 2015, 06:18:26 am
content: Quote from: Stonent on November 12, 2015, 05:56:52 amAn ASIC will usually be faster, but not always. If you get a cheap deal on a last generation process for the ASIC it could actually be slower than a leading edge FPGA. Its not just about speed, though. The different drive strengths of your new chip might produce interesting differences in both interactions with other parts of the board, and EMI. The different behaviour of the power pins might produce interesting decoupling issues. The bottom line is a new chip takes you almost back to square one in qualifying a board.