Datasheet layout directions on sense resistor - Page 1
Forum section: electronics / projects

author: jmw
author_rank: Frequent Contributor
timestamp: March 29, 2020, 07:23:08 pm
content: The datasheet for TI's LM5155 switching controller has this PCB layout advice:Connect the [current sense] pin to the center of the sense resistor. If necessary,use vias.Use a wide and short trace to connect the [power ground] pin directly to the center of the sense resistor.If you look at the example layouts and evaluation boards, they follow at least the first point closely. They tap the trace from the other side of pad running under the center of the resistor, instead of from the side of the copper pour it is sitting on. I'm struggling to understand the electrodynamics of why it matters where you make the connection. Frequencies seem too low (2.2 MHz max on this controller) for transmission line effects to be significant. What motivates this advice?Another question: why the distinction between having an "analog ground" for some connections and a "power ground" for others? In these examples, the analog ground is a small copper pour that connects to the power ground under the chip. Why do this instead of having a solid ground plane and dropping vias? The evaluation boards follow this layout even though they have a ground pour on the bottom side. Most of what I have read says that trying isolate one part of your ground plane from the other is bad.

author: georges80
author_rank: Frequent Contributor
timestamp: March 29, 2020, 07:55:16 pm
content: For the current sense resistor connections, google "kelvin connections" and toss in resistor as part of the search.It's not a frequency issue, it's the voltage drop issue of where you take the sense connections from on the current sense resistor. There are also special current sense resistors that have 4 connection points, 2 for the current path and 2 for the sense path.Separate grounds are to prevent 'switching ground noise' coupling into the sensitive analog sense areas. Stitching one big ground plane together is quite likely to create all sorts of nightmare artifacts.cheers,george.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 29, 2020, 08:54:43 pm
content: Kelvin connection, more or less, yes. It's a little more significant than the basic case, because you want low ESL in the sense path, as well as the correct resistance. Taking the sense trace back under the resistor maximizes coupling with the resistor (heh, well, if there were no ground plane inbetween; is this 2 or 4 layers by the way?), potentially canceling out some of its ESL.The ground connection could be made in the same way, though it may be more important to have a wide, low inductance connection there, and simply tolerate what ESL it gives. It is about as short as can be.Note that stray inductance is proportional to trace length. There is a geometry factor, of course: a wide trace has ~proportionally lower inductance than a narrow one. Also proportional to height over ground plane, so a 4-layer board with closely spaced inner planes (close to the outer layers, that is) is very superior to a 2-layer board, even a fairly thin (say 0.8mm) one.The same is true of components, so wide-body resistors and capacitors are preferable over their regular lengthwise variants. Note this isn't a gimme, as resistors are typically trimmed by notching the material with a laser cut; the best current sense resistors are made with multiple cuts, effectively several normal (lengthwise) resistors in parallel on the same chip. (You can do the same yourself, of course, using multiple long-style resistors in parallel.)Quote from: georges80 on March 29, 2020, 07:55:16 pmI wouldn't be quite so, alarmist about it... The motivation is to keep switching loop currents, and their associated voltage drops, away from the analog control signals. That's all. If you've not put the transistor, diode and cap on that side, there won't be much to worry about. They're just being careful.There's nothing wrong with putting that switching loop on the ground plane, without cuts, either. You just have to take all the signals (input, output, control, whatever) back through a common path and point, so that the voltage drops cancel out. Add filtering to take care of what's left that doesn't cancel, and you can get quite low EMI levels already, say 40dBuV. Achieving lower, probably requires shields over the switching nodes/loops anyway; which is maybe notheroiceffort, but still a significant step up.Tim

author: georges80
author_rank: Frequent Contributor
timestamp: March 29, 2020, 09:06:43 pm
content: Quote from: T3sl4co1l on March 29, 2020, 08:54:43 pmBeg to differ, maybe not in this case (haven't looked through the datasheet), but I've got some experience with LTC (ADI now) switcher IC's (high power LED drivers) and you have to be very careful with where ground paths are, which are tied together with vias and which should be isolated from current paths that could travel through the analog ground floods. Often multilayer is required for these and also care on where the grounding is performed on the sense traces leading back to the switcher controller. You can go from a non-functioning/unstable driver to one that is rock solid, by choice of where the power/analog grounds are cut/isolated and how and where they join together.What I was stating is that you can't just assume that flooding a big area and calling it ground will lead to a stable implementation of a schematic.cheers,george.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 29, 2020, 09:10:14 pm
content: You can't ignore where the currents are flowing, that's for sure.Tim

author: jmw
author_rank: Frequent Contributor
timestamp: March 29, 2020, 09:57:37 pm
content: Sounds like a good checklist item is to draw out the high-current and low-current loops and make sure they stay separated. Sometimes I have trouble visualizing how current returns back from ground - for the switching frequency and harmonics is it typically through the input and output capacitors?High-current loops (the datasheet example layout looks like a boost converter):gate driver pin - MOSFET gate - Rs - PGND - input caps & power terminals - controller supply pin - gate driver pinVsupply - inductor - MOSFET drain - Rs - PGND - input caps & power terminals - Vsupply (MOSFET on)Vsupply - inductor - diode - output cap & load - PGND - input caps & power terminals - Vsupply (MOSFET off)Vout - load - PGND - output cap - Vout (MOSFET on)Low-current loops:Vout - feedback resistors - AGND - output caps & terminals - Vout (this has switching frequencies present but it's low current so it shouldn't matter?)Vin - UVLO and timing resistor pins - AGND - input caps & terminals - Vin (these are probably at DC)Vout - feedback resistors - controller error amplifier - compensation network - PGND - output caps & terminals - VoutThe last one (compensation components) seem to violate this: the datasheet wants them connected to PGND but this is not a high current path. Is the idea that it should be connected to the ground plane away from other parts with vias so it's "quiet"?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 30, 2020, 02:58:26 am
content: Close. Because the inductor is, well, an inductor, it doesn't carry nearly as much high frequency current as the rest. The voltage drop in that path can still be significant (e.g., an industrial power converter might drop some volts across wiring -- a combination of the large scale of the build -- because again, length is stray inductance -- and the high currents, 100s or 1000s of amperes), but at least can be considered separate from the switching loop, which is the critical path (highest dI/dt).Again, simply a matter of putting units to it and drawing the equivalent circuit -- you will quickly see which terms are significant and which are not. The inductor (~uH) isn't significant to the switching loop (~10nH), but is significant to, say, output ripple/noise (a 10V switching waveform, into 1uH, divides into 5nH ESL to give 50mV rippleregardless of that capacitor's value).Hence why we might add additional loops, of LCs, to give good attenuation at switching and harmonic frequencies.The last one is either referenced to PGND because it is (perhaps not so much to PGND for the sake of PGND, but because PGND is the CS ground reference), or is an incidental connection because AGND and PGND need to be joined at some point and this is the best location to do so.Tim