AD9283BRS-100 vs AD9283BRS-80/50 - Page 1
Forum section: electronics / beginners

author: Traceless
author_rank: Frequent Contributor
timestamp: March 10, 2025, 07:47:49 am
content: Hi everyone,I was just looking at the datasheet for the three variants of the Analog DevicesAD9283BRS. At first glance the -80 and -100 version seem to be the same part as the -50 just with higher sampling rates (80/100 MSPS instead of 50). Most properties are identical or similar, a minor difference for instance is the Signal-To-Noise Ratio (46.5dB for the -100 vs 47dB for the -80/-50). Harmonic distortion seems to be mostly lower as well on the -100 (one exception being the 2nd Harmonic at 27 MHz). However there is one property "Integral Nonlinearity" which is +1.50 LSB for the -50/-80 but + 2.25 LSB for the -100. "Nonlineraity" sounds like an undesireable property for an ADC - so now I wonder what does that mean in practice and does that make the -100 unsuitable as replacement for its lower speed brethren? If the higher Integral Nonlinearity makes the -100 unsuitable would the -80 be a suitable replacement for a -50?Cheers Traceless

author: benj38
author_rank: Frequent Contributor
timestamp: March 10, 2025, 08:29:52 am
content: First, obviously the -80 would be a suitable replacement for the -50.Second, the INL specs of the -100 are identical to the -50/-80 versions at room temperature. It is only that the worst case guarantee at the full temperature range of -40 to +85 degrees C is a bit worse.It all depends on your application if this is an issue, but I would venture to say that in almost all cases this is a non-issue.If you let us know more about your application, it would help.

author: Traceless
author_rank: Frequent Contributor
timestamp: March 10, 2025, 08:45:42 am
content: Hi benj38,thanks for the reply, the application would be the replacement of U607 in a Keysight 34465A.I think I'm a bit confused in general about that spec. Judging by the name it measures how many least significant bits may jitter. What is odd to me in that context is measuring fractions of bits. Either the least significant bit (lsb) is non linear or the the last lsbs are non linear. So naturally I'd round up 1.5 to 2 and 2.25 down to 2, then again if you look at the distance you're at 0.75 bit ~ 1 bit which suggests that the -100 has one extra non-linear least significant bit potentially causing more noise?--Cheers Traceless

author: benj38
author_rank: Frequent Contributor
timestamp: March 10, 2025, 12:12:43 pm
content: First, I have never analyzed the role of U607 in the 34465A, so I guess somebody else may contribute with respect to how critical is this spec in this application. Given that the 34465A is a relatively high precision instrument, you may want to do your best not to deteriorate the specs in any way (though I still suspect that, in practice, variations between individual units of the ADC may have a larger influence than this spec difference).As for how INL is given, and why it may be a non-integer value of LSBs, I will try to explain.If you draw a graph with the x-axis being the input (analog) voltage, and the y-axis being the binary (digital) output, an ADC transfer function will give you a staircase shape (I am ignoring noise issues here). Note that the basic unit of measure of the x-axis is a voltage unit (say one volt), and the basic unit of measure of the y-axis is 1 LSB.The two most popular ways to define INL (I do not know which is used by Analog Devices in this case) are as follows:Mark the left-most point of the horizontal tread of each step (some use the middle point of the tread) and connect all these dots. For an ideal ADC this will give you a straight line, whereas for a real ADC (aftercorrecting the staircase for offset and gain errors) you will not get a line, but some curve. Now find the line that is closest to this curve (using the least-squares method), and measure the vertical (i.e., y-axis) maximal distance between your curve and this line, and you get the "best straight line method" INL spec.If instead of drawing the closest line to your curve you simply draw a line between the first and last points on the curve (the points on the all zeros and all ones treads), and then measured the maximal vertical distance between your curve and this line, you will get the "endpoint method" INL.Notice that, in both cases, the vertical distance you get is a continuous quantity that can take any real value in the y-axis unit of measure, which is LSBs.

author: benj38
author_rank: Frequent Contributor
timestamp: March 10, 2025, 08:24:53 pm
content: Let me just add the following clarification.Quote from: Traceless on March 10, 2025, 08:45:42 amWell, no.INL is not a measure of jitter or noise, but of a specific inaccuracy callednon-linearity,which means how far is the ADC transfer function is from alinearfunction (i.e., a line) obtained by one of the ways I explained in my previous post.

author: Traceless
author_rank: Frequent Contributor
timestamp: March 11, 2025, 06:42:13 am
content: Hello benj38, thank you for the explanations, that clarifies how they did come up with fractions of bits for the INL property. Since it is still unclear what the practical impact of the INL difference between the -100 and the lower sample rate versions is, I agree that picking one of the lower end versions to replace U607 would be the safest approach.

author: xvr
author_rank: Frequent Contributor
timestamp: March 11, 2025, 01:24:15 pm
content: My guess is that all 3 versions of the AD9283BRS use the same die, just sorted with post-production testing. And since the 2.25/1.5 bits difference appears in the Level VI test ("guaranteed by design and performance testing for the industrial temperature range"), it wasn't actually tested at all. The difference could be explained by the higher clock speed. If so, you should get the same 1.5 bit from the -100 part if you run it at 80 (or less) MHz

author: Kleinstein
author_rank: Super Contributor
timestamp: March 11, 2025, 05:25:47 pm
content: It looks like the INL is a function of the actual conversion speed. So the fast version used at a lower speed should be as good as the slow version. It just has the option to also go faster, where the slow version could fail (very large error), while the fast version only gets a slightly higher error.From the plan of the HP34410 it looks like the ADC is used for the feedback part of the SD ADC. For this purpose the actual performance of the ADC should not be that critical. I would not expect problems from a slightly worse ADC, more like all fine until really bad (e.g. 10 LSB INL) and than maybe some error messages from excessive swing of the integrator, exceeding the linear range of the other ADC. It would be the other ADC chip that may be a bit relevant for the performance. It should be less of an issue for the slower conversions.

author: Traceless
author_rank: Frequent Contributor
timestamp: March 12, 2025, 08:04:29 am
content: Thank you xvr and Kleinstein, if you're correct the AD9283 would be a suitable replacement despite the difference in the datasheet. However there is one thing I don't understand with respect to the speed:Quote from: xvr on March 11, 2025, 01:24:15 pmQuote from: Kleinstein on March 11, 2025, 05:25:47 pmIf INL is a function of the conversion speed why do AD9283-50 and AD9283-80 with a speed difference of 30 MSPS have theexactsame INL (+1.5), where AD9283-100, which is "only" 20 MSPS above 9283-80 suddenly specifies a 50% increase in INL (+2.25)? Shouldn't we observe a higher difference in INL between the -50 and -80 version than between the -80 and -100?

author: Kleinstein
author_rank: Super Contributor
timestamp: March 12, 2025, 08:42:03 am
content: In the DS is a curve showing the INL error as a function of the converion speed. It is relatively flat to some 80 MSPS and than shows more error going faster. It's the question of waiting long enough for the stages to settle. It looks like up to some 80 Msps works well, just faster needs to compromise INL for speed. Chances are that the parts are graded from how much the INL and DNR gets worse at 100 Msps - those that perform acceptable go to the 100 Msps bin and those that show large errors go to the 50 or 80 Msps bin.I would not expect the 100 Msps part to perform worse than the slow grades, though a few of the production tests seem to be a bit less stringent.I don't expect the performance of this ADC in the DMM that critical - there should be enough reserve for a little more INL or noise.

author: Traceless
author_rank: Frequent Contributor
timestamp: March 12, 2025, 09:24:56 am
content: Thank you for the clarification Kleinstein. Binning sounds plausible and is very much in line with what CPU vendors do with their chips. So in summary: Any of the AD9283 versions with a high enough sample rate will do, the lower specs of the 100 MSPS is an artifact of its higher speed and likely won't be observed if it is operated at lower speed.