How to describe a 74HC74 as part of a Spartan-6 - Page 1
Forum section: electronics / general

author: dietert1
author_rank: Super Contributor
timestamp: October 30, 2023, 07:46:13 am
content: Some unexpected difficulty happened when i try using an OBUFDS primitive to get two complementary outputs with no gate delays between them. I tried various IOSTANDARD specs yet couldn't get the full 3.3 V output swing needed to drive mosfets. As a patch i am using two assignments likeCode:..output oSignal;output oNSignal;..reg rSignal;assign oSignal = rSignal;assign oNSignal = ~rSignal;As the two outputs are constrained to p and n pads of one output unit there is a chance it's ready. A first measurement was inconclusive. It shows a 0.6 nsec timing difference that depends on trigger level, so it's below the limits of that scope. The reflections will disappear once the mosfets will be placed.Regards, Dieter

author: hamster_nz
author_rank: Super Contributor
timestamp: October 30, 2023, 08:09:11 pm
content: From your description I'm not exactly sure what you are attempting...If there is no clocked I/O register inside the FPGA's I/O bank then difference in the internal routing delays will be exposed to the outside world.You could also tune out this delay/skew by using the ODELAY primitive, but this would be problematic to calibrate.

author: BrianHG
author_rank: Super Contributor
timestamp: October 31, 2023, 01:03:57 am
content: I not sure about Xilinx, but even Altera will most likely do the same thing with the way you have set things up.With Altera, there are 3 ways to fix this.A) Just drive your positive output and tell the compiler to use a differential output when defining the pins.B) Define and use the IO Pin primitive for the device you are using and set the output to a differential output. The output of that primitive should have a positive and negative pin pad.C) (Usually called software emulated LVDS differential) Make 2 sets of your logic clock feed 2 normal clocked outputs, one positive and one negative. Then you will need to make sure that you set your compiler's directive for that output to 'NOT remove duplicate logic' so that the compiler may not accidentally re-create your original code and make sure you logic's output flipflops are the ones right at the IO pin for best timing instead of being a flipflop somewhere random on the FPGA. (When I say flipflop, I mean logic cell...)EG for #C:Code:(*preserve*) (* useioff = 1 *) output reg positive_out; // note that the *preserve is Altera Quartus's directive which tells the compiler to not simplify out this logic(*preserve*) (* useioff = 1 *) output reg negative_out; // It means that these regs are forced to follow what I have written, no simplification even if the compiler sees it can do so.// The *useioff Altera Quartus directive ensures that the clocked FlipFlop generating the output will be the one at// the IO pin instead of using an clocked flipflop somewhere optimum on the FPGA fabric while routing that// FlipFlop's output to the IO pin via asynchronous routing creating random delay timing unless you create// a proper .sdc timing constraints file.always @(posedge clk_in) beginpositive_out <= (A_in==B_in) ;negative_out <= ~(A_in==B_in) ;endRemember, each '<=' is another 74LS74 DFF clocked by the 'clk_in'.What you wrote takes the output results of 'rSignal' and places it through an inverter causing a delay before outputting you negative version.Using a differential output primitive as I describes in options #A or #B is the proper way to get a perfect differential output.Another example of #C:Code:(*preserve*) (* useioff = 1 *) output reg positive_out;(*preserve*) (* useioff = 1 *) output reg negative_out;always @(posedge clk_in) beginpositive_out <= signal_in ;negative_out <= ~signal_in ;endIf you haven't used a differential pair IO for your design, this may still work with Xilinx, even without the Altera specific directives. If you did use a differential pair IO,then do it rightand use the proper IO buffer primitive.

author: BrianHG
author_rank: Super Contributor
timestamp: October 31, 2023, 01:33:23 am
content: Did the 'OBUFDS' primitive not give you 2 output pins? Did you read and understand the datasheet?EG:Code:OBUFDS #(.IOSTANDARD("DEFAULT")) OBUFDS_inst (.O(oSignal),.OB(oNSignal),.I(rSignal));Careful, this will only work with specific sets of paired IO pins.Now if you messed up and didn't use the premo differential IO pairs, then you will need to switch to this 'Pseudo Differential SSTL' io standard...Code:OBUFDS #(.IOSTANDARD("DIFF_SSTL3_I") // or .IOSTANDARD("DIFF_SSTL3_II")) OBUFDS_inst (.O(oSignal),.OB(oNSignal),.I(rSignal));This change in differential IO standard should allow you to use almost any 2 paired IO pins on the entire FPGA.Funny enough, Altera's differential IO buffer has the similar features and limitations except they call their any pin differential IO 'emulated differential' instead of 'pseudo differential' as read in Xilinx's 'Spartan-6 FPGA SelectIO Resources User Guide (UG381)', page 26.The 'pseudo differential' should give you the full 3.3v swing on un-loaded outputs like a normal 3.3v LVTTL output with near 0 delay between the N&P outputs with the possible exception that the rise and fall speed will slightly differ due to differences in sink and source current capabilities of the IO pin. This is where the true-differential outputs are king, except, for those IO standards, you require specific load and termination to get that balanced output, hence, the loss in output voltage swing.

author: dietert1
author_rank: Super Contributor
timestamp: October 31, 2023, 06:42:01 am
content: Thanks for your comments.I chose a pair of differential output pins and the two output pins worked with the OBUFDS primitive. The unexpected difficulty was getting the full 0 V to 3.3 V output swing. As you wrote this is unusual and probably unsupported for differential output.Meanwhile i improved the patch and the final schematic shows two LUTs, two FFs and two OBUFs with all LUTs and FFs in one slice and the OBUFs next to each other. So there is no more gate delay from clock to output pin and fanout and routing differences should be small. I repeated the measurement with a better scope and it confirms the residual timing differences are 0.6 nsec or below.Probably i will fit the mosfets to see them in action.Regards, Dieter

author: hamster_nz
author_rank: Super Contributor
timestamp: October 31, 2023, 07:08:30 am
content: If you get random failures of your MOSFETs this might be the cause.If your signal transition is close to the clock edge, one FF might latch a the correct value as it was before the transition, the other might latch the correct value after the transition.This will be more likely to happen of one path has a LUT between the input pin and the FF (to do the inversion).Also, if setup and hold time is violated on either FF then the could both become 1 or 0 at the same time.It's not likely that it will happen, it might take 10e12 transitions or more, but given long enough it most likely will happen.

author: dietert1
author_rank: Super Contributor
timestamp: October 31, 2023, 07:30:01 am
content: No, this isn't a power device and no bridge. The hardware is safe against timing errors. This is more about precision.I am using debouncers for all asynchronous input and the design is all synchronous, capable of about 140 MHz but running at 50 MHz. Really a 74HC74 cannot compare.Regards, Dieter