Digital Phase Shifter Impedance Problem (6 Layer JLCPCB Stackup) - Page 1
Forum section: electronics / rf-microwave

author: MrBalthazar
author_rank: Contributor
timestamp: April 20, 2023, 09:00:21 pm
content: HelloBecause the Phase Shifter(MAPS-010144) I used had a narrow pin, it needed a thin 50 ohm microstrip trace. I used the 6 layer 3313 stackup of JLCPCB.Phase shifting is happening, but I don't understand the reason for the impedance mismatch. I'm curious about your thoughts on this subject.Not : newbie:)Thanks.My StackupS11S21

author: MrBalthazar
author_rank: Contributor
timestamp: April 20, 2023, 09:14:11 pm
content: Up! I forgot to add the dielectric coefficient.JLC's er = 4.05 for prepreg 331354 Ohm its OK for me.

author: Weston
author_rank: Regular Contributor
timestamp: April 20, 2023, 09:37:40 pm
content: A few possibilities: Is the trace sized correctly? Lots of the calculators can be wrong and non-standard aspect ratios, but that trace seems reasonable. You seem to be using Altium which I has a EM solver in recent version which should be an accurate match.Is the trace etched to the right size? I don't know what post-fab verification JLC uses for their controlled impedance PCBs.Possibly most likely: Did you optimize the connector launch with a cut-out the ground plane under the SMA connector or anything? If you did not that area will have a lot of capacitance / be a quite low impedance and cause a mismatch.Plotting the input impedance on the smith chart might be useful to see if the impedance is too low or too high. You can also transform the S11 data into a synthetic time domain reflectometry response which would show you where you have an impedance mismatch. (it could aid in narrowing down if its the connector launch or not). If you are familiar with python, here is an example using the scikit-rf libraryhttps://scikit-rf.readthedocs.io/en/latest/examples/networktheory/Time%20domain%20reflectometry,%20measurement%20vs%20simulation.html

author: MrBalthazar
author_rank: Contributor
timestamp: April 20, 2023, 09:45:51 pm
content: "cut-out the ground plane under the SMA connector". I don't understand this process. Could you give an example?I did the analysis for 0.15mm trace using CST microwave and it comes out about 50 Ohm.I soldered the connector from both the bottom and the top.S11 SmithS22 Smith

author: Weston
author_rank: Regular Contributor
timestamp: April 21, 2023, 08:51:29 am
content: The solder pad for the pin of the connector can itself be thought of as a section of microstrip. Its many times wider than your 50 ohm microstrip and the added conductor area of the pin additionally lowers inductance, so you have a section of very low impedance transmission line. Ignoring transmission line effects, its just a big area adding a lot of capacitance.The general term is "connector launch", the transition from the connector and its solder pads to the transmission line geometry of the PCB. For PCBs with a thicker dielectric layer you can typically get connectors with a center pin that is narrower than the geometry of the transmission line (or have a very short pin and a very short pad). Beyond that you need a bunch of RF simulations and possibly a few test PCBs to get it right. For commercial products they throw a bunch of simulation software at the problem.There is some information of the forum about it, but you are not going to find many rules of thumb, because the geometries are all refined in simulation. You should be able to simulate this with the free version of Sonnet EM. Right now you have a really bad launch due to the thin PCB lamination and large pad. You could do better without simulation just by cutting out the L2 ground plane and reducing the length of the center pin pad and trimming the pin on the SMA.You would also get a smaller total mismatch if you used a thicker prepreg laminate on the PCB and tapered the transition to the phase shifter IC, thats a much smaller discontinuity than the SMA footprint.https://www.eevblog.com/forum/rf-microwave/edge-mount-sma-center-pin-and-trace-width/https://www.eevblog.com/forum/projects/sma-rf-end-launch-transitions/

author: langwadt
author_rank: Super Contributor
timestamp: April 21, 2023, 10:05:31 am
content: https://www.we-online.com/components/media/o563287v410%20ANE012b%20EN.pdf

author: BigBoss
author_rank: Regular Contributor
timestamp: April 21, 2023, 06:27:08 pm
content: There might be 2 issues that effect the result.-Calibration-Manufacturing Tolerances-To my understanding, the calibration (SOLT) should be done on the same PCB-->see application PCB of the IC-The thickness is relatively low (approx. 0.18mm) and therefore manufacturing might be pretty erroneous.If I were you, I'd use a substrate with a relatively low di-electric coefficient ( Rogers , Taconic ) to increase the width to prevent from mfg. tolerances.Principally, I'd use more professional manufacturer in this type of critical applications. A small parallel capacitor may be used to match at mid-frequency.

author: szoftveres
author_rank: Regular Contributor
timestamp: April 22, 2023, 12:48:53 am
content: I would probably do this project on a stackup where the 50ohm microstrip width would be (nearly) as wide as the SMA pad (reasons explained above).As the microstrip getting narrower as it's going into the IC, the decreasing capacitance can be compensated for by bringing the surrounding ground plane closer (i.e. coplanar mode).By doing these two things, the 50ohm can be maintained for nearly the full length.

author: profdc9
author_rank: Frequent Contributor
timestamp: April 24, 2023, 05:37:01 am
content: You might want to consider a different end-launch connectorhttps://www.amphenolrf.com/132414.htmlYou can see how tiny the pin is on the connector. This would help minimize the capacitance of the pad its soldered to on the board. The pictured connector has a fairly large pin on a large pad. If the layer is 0.1 mm thick, the pad is 1 mm and 6 mm long dielectric constant 4.2, that's on the order of 2 pF of capacitance, or -j80 ohms at 1 GHz.

author: Marsupilami
author_rank: Frequent Contributor
timestamp: April 25, 2023, 02:18:20 pm
content: Quote from: Weston on April 20, 2023, 09:37:40 pmSeconding this.Your pad size seems to be 3.5*1.5mm. Assuming there is continuous ground plane under, using 0.09mm layer thickness and Er=4 that is about 2pF capacitance. At 2.4GHz it appears as a j33Ohm shunt capacitor to ground, which in parallel to an otherwise perfectly 50Ohm network after results in ~4dB return loss.What I would try to verify is to cut and scrape off as much as possible of the signal contact pad and have only the tiniest bit of solder connecting to the pin.This should get rid of the bulk of the extra capacitance. It's not going to be perfect but it will give you an indication if you're on the right track.Assuming your phase shifter is very low insertion loss so don't forget to do it on both connectors.Good luck!Edit:Yessir, there is your problem:

author: MrBalthazar
author_rank: Contributor
timestamp: April 29, 2023, 09:43:35 pm
content: Thanks for great replies!I verified your suggestions by simulation. The problem seems to be entirely related to the input capacity. (wide pad)Added few result from CST Simulations. You can interpret the consistency of the results.I used taper for solution and I'm going to reproduce the PCB but for now I want to experiment with taper by cutting small pieces with copper tape.Do you think this would be a good method?PCB GeometryPCB Simulation ResultFull GeometryTaper GeometryTaper Result

author: MrBalthazar
author_rank: Contributor
timestamp: April 30, 2023, 11:41:39 pm
content: I just wanted to use a thin dielectric. Because the 50 ohm path will be thin and I can easily connect to the pad thickness of the IC. If I use a thick dielectric the 50ohm quite the line becomes quite wide. that will make the connection to the integrated difficult, right? I preferred ENIG as the coating. A 6-layer PCB with Enig coating was quite cheap to manufacture. because they made such a campaign ($2). the top of the layers is just RF and the bottom of the dielectric is completely ground. the other layers consist of feed and control signals. I added the stack up structure at the top.

author: MrBalthazar
author_rank: Contributor
timestamp: May 01, 2023, 12:22:17 am
content: yes, I have examined these attachments, but what should be considered in order to connect the thick transmission line to a narrow road? Assuming we're going to do this as a taper, does this taper have to be very narrow, or should the classic quarter-wave converter length be used?I was undecided about this. I think it would be useful to do a few more simulations.

author: mtwieg
author_rank: Frequent Contributor
timestamp: May 11, 2023, 12:16:09 pm
content: The use of a 6 layer stackup to get a thinner 50ohm line width is understandable. It's possible that the large size of the center pin pad for the connector is the main culprit. Yes the line itself will have higher insertion loss, but it seems the trace is very short so it's unlikely an issue (at least on this small test board).MrBalthazar, have you tried simply whittling the width of that pad with a blade? Should be more straightforward than all this simulation.

author: MrBalthazar
author_rank: Contributor
timestamp: May 15, 2023, 09:05:23 pm
content: At the moment, I am waiting for the tapered 6 layer design to reach me.When the new PCBs come, I will try to reduce it with a knife, but I know that I cannot shrink it much because the connector pin is quite thick.I'll try this anyway and let you know the results.