1st try at SEPIC charger layout - Page 1
Forum section: electronics / projects

author: ratio
author_rank: Regular Contributor
timestamp: November 23, 2018, 12:57:39 am
content: I'm working on a charger that will charge a 12V 5AH SLA from an automotive source, so input could be anywhere from 'key off low battery' to 'full charging current'. I found a Linear part, LT1512 (datasheethere), which seems to fit the bill.Does the attached layout look like it will work? Any pointers or suggestions?The schematic is taken directly from the data sheet until I have a better feel for what's going on. The size of the board is just something I picked for no special reason--eventually it will be shrunk to whatever size is appropriate. The component are again taken from the data sheet more-or-less verbatim; and sized for a manual process.

author: viperidae
author_rank: Frequent Contributor
timestamp: November 23, 2018, 02:23:39 am
content: Has that c2 in the tiny package you have on your layout got enough ripple current rating?They have recommended layouts in the data sheet.

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: November 23, 2018, 02:26:54 am
content: Yea your trackwork looks a bit small for what it's going to do. As always pays to refer/copy the layout examples from the datasheet (pg 9)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 23, 2018, 03:14:27 am
content: No ground plane / flood fill?Tim

author: ratio
author_rank: Regular Contributor
timestamp: November 24, 2018, 12:41:30 am
content: I'll double check C2. I just went through the BOM one at a time & did a parametric search at Mouser, I'm sure the parts could be better selected.I'll go over the trace sizing. I was trying to figure out KiCad's net classes & spent less time thinking about the current than I should have.And there is a ground pour, I turned the display off to make it a little easier to see the traces.So, looks like it's possible it'll work then? I read a few articles about laying out power supplies & converters & was working on minimizing current loops around the inductors. I thought about putting vias in the pads & putting some components on the back side, but maybe that's not a good idea? Or would that be less of an issue with a manual soldering process?What about C3 right in the trace like that? Done all the time? 'What was he thinking'?

author: Tomorokoshi
author_rank: Super Contributor
timestamp: November 24, 2018, 06:21:29 am
content: 1. The Vsw and Vin nets off U1 look a bit scrawny.2. Starting on page 8 of the datasheet it talks about the input capacitor. It starts out specifying a "low ESR 22μF, 25V solid tantalum capacitor" which then changes to a "2.2μF ceramic capacitor such as the one used for the coupling capacitor". I'm not quite sure what they're up to, but I recently had to deal with an LT SEPIC converter where I also used similar guidance provided by the datasheet. It would be nice if there was more explanation about such a big change.I wasn't using their exact circuit. I turned the 2.2 uF input capacitor into the inside of a PI filter, with another 2.2 uF ceramic (see a theme here?) on the input, with a small inductor in between.The design failed the Conducted Emissions EMC test, which was tracked down to discontinuous shutdown / restart operation of the switcher because of the runaway voltage drop at the input caused by the LISN impedance. My 2.2 uF inside ceramic capacitor, which at my nominal input voltage of 24 V was now derated to around 1 uF, was run down to a voltage low enough that the switcher would reset.The solution was to replace the outside capacitor with a 47 uF electrolytic, and to upgrade the inside to a 10 uF ceramic.I did verify that my PI filter wasn't the cause of my EMC issues with the LISN. The PI filter allows for bypassed DC power from the electrolytic, with the ceramic taking up the high speed switching. Best use of each type without trying to roll it all into a tantalum.

author: charliehorse55
author_rank: Contributor
timestamp: November 24, 2018, 06:35:45 am
content: How well does the design handle voltage spikes? They are common in an automotive space - the input rails may easily see 100V+ during a load dump.Ref.http://www.ti.com/lit/an/snva681a/snva681a.pdf

author: ratio
author_rank: Regular Contributor
timestamp: December 15, 2018, 06:38:39 pm
content: The next try. A board shrink, we're now about 1-3/4" square. The power traces are 50 mils, the Saturn toolkit says that's good for over 3 amps, which should be fine. Ground pour on the top & bottom, not displayed. I moved a few parts to the back side to shorten up the high current path. This resulted in vias in the pads, but I figure that's not going to be a real issue with hand soldering.After looking at it again, I think I might be too scant on clearances between the inductor and C3. I'll bring in the components & lay it out on a printed sheet to dry fit everything before I send the board out.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 15, 2018, 07:09:52 pm
content: Using via-in-pad, even if you're strictly going to use this board for hand-soldering, may still cause you some issues. Quite a few PCB manufacturers may frown upon this and force you to have plugged vias (which can be expensive) otherwise that would violate their DRC. Especially the low-cost ones which usually don't waste more than a couple minutes validating a PCB design before sending it to production...

author: ratio
author_rank: Regular Contributor
timestamp: December 17, 2018, 01:09:58 am
content: Thanks for the heads up. The uploader at OSH Park didn't seem to mind, they show up clearly in the rendered view. I suppose they might not make a complete DRC pass this early in the process though, I guess a call to support is indicated.This is just a personal project, I can't currently imagine a need for more than one or two of them.