You get more copper between Pads/Vias using a true Power Plane instead polyfill. - Page 1
Forum section: electronics / general

author: BrianHG
author_rank: Super Contributor
timestamp: May 07, 2018, 02:36:49 pm
content: Ok, this came up on a recent EEVBlog2 video on Kicad. A little confusion for some on why there is a difference between a real 'Power Plane' assigned to a net, whether split or not, VERSUS a 'Polygon Fill' of a net.Now, let it be understood that some of the latest cad software out there may offer the ability in the polygon fill to erase out the pad around the drill hole around the unconnected filled region, but, it wasn't happening in Dave example video. For those who know the inside-out of Kicad who may have a way to do this erasure to gain maximum copper fill around unused pads, please add to this thread, however, my numerous versions of Protel versions cannot perform this feat in any automatic means when using a polygon-fill.Taking a look at this screenshot, we can see a polygon fill, where traces won fit between pads.Now look at this power plane. NOTE this is anegativeimage, so, the black is copper and green is void, no copper.You can see that the copper between unwired pads is double to 0.8mm space, but, why?For the answer, take a look at this screenshot to reveal the reason. Again, it's anegativeimage, so, the black is copper and green is void, no copper.The spacing is still 0.45mm, but, there are NO PADS on a power plane, just the drill holes, and either copper flows over the hole, or it doesn't.Note that the orange is the drill hole size. On the upper images, white is the drill hole size and grey is the PAD copper around the drill hole.(Please excuse a minor mistake in the GND connection on the power plane, the green relief voids should have been set further away from the drill hole plus a little thinner.)Polygon fills may be OK for general large circuits, but, when doing RF and you want maximum unbroken GND plane, or, BGA FPGA with vias so close to one another, the true power planes become necessary for generating unbroken GND&VCC fill around all those compact close together vias which would at many times get broken and chewed up with a polygon-fill like my first example image.

author: langwadt
author_rank: Super Contributor
timestamp: May 07, 2018, 05:13:37 pm
content: some CAD tools have that as an option "remove non-functional pads"/"remove unused pads" on inner layersand I've heard some board houses will do it by default because apparently it gets a better yield, though that sound abit dangerous and won't give the added routing space if that is what you are after

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 07, 2018, 07:56:52 pm
content: I sometimes set custom pad stacks for this reason.One example was thermal vias under a QFN, where I also had to route a power pour, on an inner layer, to the far side of the device. I removed the inner layer pads manually (vias configured for full pad stack), which freed up the space needed for pouring between them. (Note I still had a generous inner layer clearance set, so the layer registration + drilling tolerances were not violated.)Tim

author: BrianHG
author_rank: Super Contributor
timestamp: August 22, 2018, 12:34:43 am
content: KiCAD cant do it, without some special tricks: Optimizing Annular Rings of Vias in Inner Layershttps://forum.kicad.info/t/optimizing-annular-rings-of-vias-in-inner-layers/1514Good luck with it. It doesn't work on newer KiCAD. Any high density design, or BGA design actually really needs this as an automatic on/off function unless you want your inner layers looking like chopped up broken Swiss cheese under a BGA chip. This also counts for DIP ICs inbetween the pads like my photo examples above.

author: Psi
author_rank: Super Contributor
timestamp: August 22, 2018, 07:54:06 am
content: Altium has a global option for this where you setup your gerbers.Draw unconnected midlayer pads. Or something to that effect.You dont need to use the global option or have power plains to get the extra copper though. You can set any via or TH to full stack control and then change the pad size on a layer by layer basis in the properties of the viaIts useful when breaking out a bga. If you remove a pad on a inner layer you can fit a trace in between vias where it otherwise would not fit

author: BrianHG
author_rank: Super Contributor
timestamp: August 22, 2018, 06:49:55 pm
content: Quote from: Psi on August 22, 2018, 07:54:06 amJust removing the pads, like you are suggesting doesn't effect the copper pour around that pad. You need to see this on the editor, not the gerber output. Otherwise, I man not see if there is an open, or closed circuit between 2 vias when just pushing one a fraction of a millimeter would close the circuit. It is already automatic if you use a power plane, my example images came from Protel 99SE, Altium handles this part the same way. In Protel 99SE's DRC under manufacturing constraints, you can setup 2 rules to get approximate automatic angular ring size on mid layers, but, I never got it to do exactly what I wanted.

author: Mattylad
author_rank: Regular Contributor
timestamp: August 26, 2018, 11:02:44 am
content: Change the width of the copper used for the fill and it will easily fill between those pads.It's a balancing game to get the right values of spacing, width etc. However it can be done using fill.Many still prefer a negative powerplane still though as it is a smaller filesize, less to plot etc.However it can also be harder to see where you have problems, where you have not got copper because the negative plane cannot get into an area, so perhaps pour a fill first, make sure it gets to all areas then remove the fill and use a negative plane for the final.