Understanding this reset (nrst) nand gate circuit - Page 1
Forum section: electronics / beginners

author: Danno78
author_rank: Newbie
timestamp: July 13, 2023, 05:19:54 am
content: Hi all I've just signed up and am an amateur in electronics.Am getting started with arduino and am learning about nand/nor gates in reset (nrst pins etc) on microcontrollers gate arrays, multiplexing etc.I've come across this circuit and would like to understand how the output is derived and what it would look like to the reset pin on the gate array chip pin 30. I've learnt about basic nand and nor truth tables and Sr latching circuit.It's from an older keyboard organ. Sns is coming from the main power supply(linear) at +23v unfiltered and unregulated after a 10k resistor, the lower nand circuit is for a mute which will switch on a +15v to the main preamp and power amp, when ground is lifted on a headphone jack the +15v output is cut via a pnp from the amp board.D3 is 5.6v zener, the other diodes are switching types, IC18 is nand chip is M74HC00FP data attached, IC18-3 connects to an NRST pin on a proprietary technics chip gate array for the keyboard.At this stage I'm mostly interested with how this circuit functions. Is the output of the nand a stable high when power is on? The inputs are tied and and also fed back to the output, is this a latch? I understand this to be a typical reset circuit, is it on a rising edge?? however I'd like to understand if a pulse is generated by the capacitor/Resistors in series to ground, or is it a low voltage stableoutput that is sent to pin 30 of the gate array on the key bed.I hope I'making some sense, Thanks for any help to understand the circuit I've attached screen shots of what I think would be helpful

author: RoGeorge
author_rank: Super Contributor
timestamp: July 13, 2023, 07:00:31 am
content: Quote from: Danno78 on July 13, 2023, 05:19:54 amThe general rule for naming wires (signals) in digital schematics is to give them very short names, a mnemonic. In this case RST stands for "Reset". When the names starts with "N", means it's a negated signal. So here, NRST letters means Negated ReSeT.For example, an integrated circuit that has a pin named RST, will go into reset when a "1" is applied to the RST pin ("1" means +5V for TTL gates like the 400 NAND used in that schametic).If it were for the pin to be named NRST, that means the integrated circuit will go into reset when a "0" is applied to the "NRST" pin. (the logic level to activate the reset is inverted/negated, that is why it was named NRST instead of RST).Sometimes, instead of the letter "N" prepended to a name, a bar is drawn above the name, like this: \$\overline{RST}\$, which means the same thing as NRST, a negated RST. A name with a bar is another convention to tell a signal is inverted, active on 0, not on 1.Usually, a reset state is kept (lasts) as long as the signal isasserted. So usually we use a short pulse to reset a circuit, then the signal is deasserted."Asserted" means active, so asserted for a signal notated with RST would mean heaving a "1" on that wire, while for a signal called NRST asserted would mean heaving a "0" on that wire.For the gate array in your schematic, if the signal is called NRST, it means the chip will reset when a "0" is present on that wire ("0" logic is represented by zero volts on that wire). After a short reset, we need to deassert the NRST, so the circuit can run and do its job. Deasserted for a signal called NRST means a logic "1" (+5V in that schematic).This means "NRST" will be "0" for a short time when the organ is powered up, then the NRST will stay at "1" (+5V) until the power is unplug. That is usually called a power-on reset, and it does not need a mechanical button. The reset pulse is formed (most often) by a capacitor at the input of a logic gate, a capacitor that charges when the power is applied, then remains charged until the power is unplugged.Usually there is a manual reset, too, with a dedicated reset switch, that will form a reset pulse each time the switch is pressed. The attached schematic is cropped so can not tell for sure if there is a manual reset switch, or just the power-on reset. If possible post a link/full picture, or at least tell the organ model to search for the complete schematic.What do you mean when you say "the output is fed back to the input"? Name the connected pins you say they fed back the output to the input. I don't see any latch in the reset circuit.

author: Danno78
author_rank: Newbie
timestamp: July 13, 2023, 08:10:53 am
content: Hi RoGeorgeThank you very much for your detailed reply, it has greatly help me understand the topology of these circuits.What I was referring to when I said the output is fed back, was where pin 4 of IC18-2 is connected via a 4k7 resistor to pin 8 of IC18-3 however I see now that there is c18 0.1uf capacitor, would this be the cap that forms the pulse, or does c17?There is no manual reset in the form of a switch that i have seen other than the power on the organ, i will take another look if i can find something. However the midi does provide a type of note reset in a hanging event called a panic reset, it may be related? In the image showing cn12 at the bottom of the image the JK connector has a label MRES coming from the circuit.

author: Danno78
author_rank: Newbie
timestamp: July 13, 2023, 10:13:46 am
content: Sorry ignore my comment about midi as it is an external input.

author: RoGeorge
author_rank: Super Contributor
timestamp: July 13, 2023, 12:14:13 pm
content: IC18-2 and 3 certainly don't make a latch. Could be an oscillator (because C18 will make a positive feedback but with some delay), but I'm not sure. Could be a monostable as well (to generate a single pulse). Could be as well for dealing with the order in which different voltage sources come to their stable/expected voltage (there is always a transient of less determined sequence when many power sources with different voltages powers up all at once, or when they are unplugged).Hard to say for sure, particularly because those are digital circuits used in an analog manner. If we were to be pedantic, we would never mix logic gates with resistors and capacitors, though that is an accepted practice to form a reset pulse for cheap. Logic gates were not meant to mix with RC circuit, so the exact values of the R, and C, and voltages, and the TTL family matters a lot relative to the outcome. Can't say for sure if IC18-2 and 3 will make an astable (oscillator) or a monostable (single pulse), not without simulating, or without building the circuit with the specified R and C values from the schematic.More elaborate designs will usually have dedicated integrated circuit for reset, ICs that can generate logic signals to reset and/or to power up the voltages in a certain sequence (for example, in a FPGA the power up sequence must be in a certain order for each voltage source, and the voltage stabilisers have a turn-on pin, so the exact timing and the order in which each voltage is powered up can be determined by a dedicated IC).