Transient negative voltage on NMOS gate causing channel to open? - Page 1
Forum section: electronics / projects

author: jdavis
author_rank: Newbie
timestamp: May 04, 2023, 03:05:09 pm
content: Hello World. This is my first post here. I am an electrical engineer looking to cure my madness because a 2N7002 NMOS is doing things I cannot explain. If you look into the attachments, you will see some screen shots of a schematic, simulation plots and LTspice file, and real scope plots of this issue.INTENDED DESIGN:A push button controller to turn on and off power to a system that can also be turned on when plugging in a USB cable. We can trick the push button controller by pulling the PB_L line down when you plug in a USB charging cable. This part is working well, and the system turns on when a USB source is plugged in. The combination of C123, R84a and Q15 create a timer that pulls the PB_L line low for as long as the RC curve remains above the Vgs threshold of the 2N7002 mosfet. This ends up being about a second of time or in other words, plugging in USB looks like someone pressed the button for about a second. The push button controller has a 100k internal pullup on pin 2 to a regulated 1.9V supply from the VSYS supply.UNINTENDED DESIGN:When unplugging the USB, the 5V charge (USB is 5V) from the C123 capacitor discharges backwards through the rest of the circuitry. The pulls current from ground through R84a creating a negative voltage on USB_ON_H which is the gate for the NMOS. This means that Vgs is negative. The simulations show that this voltage could spike down to ~ -5V but in reality the spikes are only dropping to about -700mV. For this reason I added in the diode in a second simulation to clamp this voltage such that the result of the simulation more closely matches what I see on my PCB.MADNESS BEGINS:Notice how in the simulation the negative transient has no effect on the PB_L signal. This is expected because a negative Vgs should not trigger the NMOS. However, in my circuity, the negative transient is somehow opening up the channel and pulling the PB_L line to ground.SEARCHING FOR CLUES:I tried resolving this by several means. I change the pull up on PB_L from an internal to an external to VSYS... Nothing. I tried adding capacitance on Vusb to ground to try to slow down the discharge... nothing. I tried changing the RC timer to see if it would affect the results and it did change the timing but PB_L was still getting pulled low. This was still affecting me on an emotional level.HYPOTHESIS:I think that maybe instead of current flowing through R84a to create the negative voltage, it may be flowing from the SOURCE to the GATE. This could maybe open the channel causing this issue. The other thing I suspect could be the VSYS voltage having a transient when changing from battery to USB power. I haven't seen VSYS bounce around in my scope plots.TLDR; My NMOS is triggering with a negative Vgs and it makes me sad.

author: Andy Watson
author_rank: Super Contributor
timestamp: May 04, 2023, 04:03:06 pm
content: Double check the footprint of the mosfet. The oscilloscope traces suggest the source and gate are swapped.

author: jdavis
author_rank: Newbie
timestamp: May 05, 2023, 01:54:48 pm
content: Thanks for the suggestion. I went back and looked and everything seems to be correct. I included some screen shots that attempt to show that the Gate, Source, and Drain are all laid out correctly. The other reason I assumed it was correct was because everything worse as designed with the positive voltages. It is only the short transient that is opening up the NMOS channel.

author: jwet
author_rank: Frequent Contributor
timestamp: May 05, 2023, 02:25:52 pm
content: My best guessWhen you insert USB, you've put a 5v charge on that cap. On pull out, that 5v can only go through that 1 meg- that current flow (to the left to ground) will develop a voltage on the 200k which will turn on the FET briefly.Its best if these circuits have a kind of latching (positive feedback) on rising and falling. In this circuit- this would be additional circuitry running on the negative edge (pull out) that could crow bar the cap charge.Its kind of a small issue, maybe just live with it if its a one off and then turn unit off manually.The reason spice doesn't see it is that you're using a generator that has a low Z out- the real world is low Z high on entry and float on exit. Put a diode or swtch in your model and you'll see it.Having MOSFET gates through big caps into the real world like a connector is not good for ESD.Good luck.