A two-channel (sub-)nanosecond pulse generator - Page 1
Forum section: electronics / projects

author: sigma_xi
author_rank: Contributor
timestamp: May 07, 2023, 09:01:20 am
content: Here's a modular, (sub-)nanosecond pulse generator design with up to 6.5 Vpp differential output.Backstory: I am working at a research lab developing analog/mixed-signal ICs. My chips need 1 ns pulses at a period of 10 ns and an amplitude of 1.8 V. These pulses must be synchronized to an external return-to-zero (RZ) pseudo-random bit sequence (PRBS). Since this was my first IC design, I thought single-ended signaling at full amplitude should be fine.As I know now, it is obviously not trivial to generate and distribute synchronized pulses this fast. We have lab equipment that could generate pulses with the right timing, but less amplitude. Also, synchronization is not so easy and/or not possible. So I spent the past two months "quick" fixing the issue by designing a modular, fast pulse generator & delay line system with remote (serial) control for measurement automation.This post is intended as a partial project dump and as a reference for the community. I won't update the design in the near future if it works for our lab. I have a Keysight MSOV204A (20 GHz) scope available, which I used to take a look at the internal (LVPECL) signals, and the final output signals.Circuit overview (see block diagram):The core module (III) has two identical, independent channels. A 1 Vpp sine wave between 10 MHz and 200 MHz is fed to a comparator (MAX40026) that generates short pulses. To achieve impedance matching and fork the sine to each channel, it is passed through an RF transformer. Thereby the sine loses quite some amplitude, which affects the shortest possible pulse width due to comparator hysteresis/offset. During testing at 100 MHz, I increased the input amplitude to 1.5 Vpp to achieve roughly 1 Vpp at the transformer's secondary. The comparator reference voltage is obtained from an RC-filtered PWM signal, coming from the Raspberry Pi Pico. In hindsight, this was a bad design decision, as the tradeoff between resolution (necessary for short pulses) and voltage ripple became apparent. Furthermore, the comparators have µA input current, which limits the series resistor of the filter because of voltage drop. In the current configuration I am using a 10 kOhm/47 µF filter for 13 kHz PWM frequency. With the LVPECL output of module III set to an average pulse width of 1 ns, I measured a standard deviation of roughly 20 ps across 20000 samples taken.Two cascaded programmable delay lines (SY89295U) shift the pulses in steps of 10 ps. There is a minimum delay of 6.4 ns and a maximum delay of 29.6 ns. On paper, the SY89295U only works between 45% and 50% duty cycle. Some testing prior to design verified that it can be used outside this operating range, down to sub-ns pulses (i.e. <10% duty cycle at 100 MHz); most likely because it can handle 1.5 GHz clock signals anyway.However, testing shows that the delay influences pulse widths by a few hundred picoseconds. For example, a pulse width (FWHM) of 900 ps at minimum delay reduces to roughly 700 ps at maximum delay, without changes to the comparator inputs.A second signal path in my design takes care of modulating an incoming (100 Mbps) non return-to-zero (NRZ) PRBS to a RZ PRBS. The input signal level can be 3.3 V single-ended CMOS, in which case module I (containing MC100EPT22DT) is needed to convert to LVPECL. Another possibility is to input LVDS/LVPECL levels. In this case the NRZ signal can be fed to module II without conversion, but watch out for termination/biasing! The RZ signal is generated within module II by a fast AND gate (MC100LVEP05) connected to the output of channel 2 of the delay line (module III).Both, the RZ PRBS and channel 1 delay line output, are amplified by a 6.5 GHz, 24V/ns fully differential amplifier (ADL5569BCPZ) with fixed voltage gain of 10, contained in module IV. This is to achieve the desired amplitude. Depending on the application, RF attenuators (module V) and bias-T must be used to set the final voltage amplitude and offset. Unfortunately, I was not able to verify the specified slew rate of the amplifiers. The output slope of module IV (driven by module III) peaks at roughly 10 V/ns during rise, and -15 V/ns during fall. It's either my PCB layout/measurement setup, or due to the input voltage differential, which causes the amplifier to hit its maximum output swing. I ran another test cascading two of the amplifiers, i.e. driving the second amplifier with 10 V/ns 3 Vpp pulses, which resulted in even less amplitude and severely worse slew-rate.The complete system operates from a single 6.2 V supply at roughly 1.5 A. Most of the power is going to the delay lines (700 mW each) and their respective 3.3 V LDOs (640 mW each). I determined the package temperatures using type-K thermocouples. In still air (23°C), the package temperature of the LDOs stabilizes at 60°C during a 90 min test. The package temperature of the delay lines stabilizes at 50°C. The package temperature of the ADL5569BCPZ stabilizes at 40°C during a 150 min long test driving signals into 50 ohm. All heatsinks are mounted on the bottom of the PCBs, so I'm sure there is potential for improvement, if necessary.Due to the selection of components, the pulse generator should also work for input frequencies above 200 MHz, maybe 1 GHz, but the RF transformer for the two-channel design only works up to 450 MHz.Known issues: If the Raspi Pico is connected to USB and no other power supply is present (e.g. for flashing), the USB port will supply the complete system (approx. 1.5 A). This is due to the reverse diode in the LM1117-5.0 routing power to the system rail. So far it hasn't killed my laptop or PC, but it's definitely something to watch out for.

author: sigma_xi
author_rank: Contributor
timestamp: May 07, 2023, 09:02:17 am
content: The PCB images and some waveforms of the amplifier outputs.

author: pardo-bsso
author_rank: Frequent Contributor
timestamp: May 09, 2023, 01:37:00 am
content: Nice.What was your process to develop and simulate this before committing to a final design?

author: sigma_xi
author_rank: Contributor
timestamp: May 09, 2023, 08:21:18 am
content: Good question. I'd say there are three main approaches that I used:1) Initially I wanted to build the whole system using analog circuits (phase shifters,...) only, but it quickly showed that this would require much more effort and probably more money. What remained from this phase is the sine input+comparator to generate the variable pulses. I simulated the MAX40026 in LTSpice using the model provided by the manufacturer. I also simulated the RF transformer and transmission lines, but only on a very basic level. Given my input frequency range, I then estimated the sine amplitude necessary.2) The phase-shifting design was driven by the circumstance that a colleague of mine had used SY89295U before for a different purpose, and he recommended them for my system. We were able to explore this part of the design experimentally in the lab, and concluded that they can handle other duty cycles than 50% at the given frequencies just fine. From there on, the design choice was made and design was concerned with implementing all the terminations and cascading exactly as specified in the datasheet. It just so happens that LVPECL is compatible with LVDS signalling, which allows the MAX40026 to directly drive the delay lines.3) The amplifier design was driven by the availability of parts and specifications necessary (slew-rate, bandwidth). There is another Analog Devices chip that is cheaper and has a bandwidth of 3 GHz, but they only specify group delay up to 1 GHz in the datasheet, as if they're hiding something. I didn't want the amplifier to change the shape of my pulses drastically, so in the end I just went with the faster, more expensive option. Unfortunately there is no simulation model available for the ADL5569, so it was up to testing to verify its performance.As for the microcontroller, I picked the Raspi Pico board to avoid having to implement clock/power supply/USB myself. Making everything modular definitely helped testing and also makes adaptations easier (if necessary).