Connecting different grounds in mixed analog and digital circuit - Page 1
Forum section: electronics / projects

author: prasimix
author_rank: Unknown
timestamp: August 05, 2015, 10:57:04 am
content: I'm currently working on redesign of post-regulator PCB where both analog and digital section exists. I'd like to see this time how to properly connect different grounds to ensure minimum measurement error or at least to have a error offset value that can be easily correct in calibration process. Please find below simplified circuit where I put on the same place various paths from both analog and digital side.We have here the following: PGND comes from pre-regulator connector (X3) and that signal will be main ground plane on bottom side of the PCB and it's used for supplying analog section. DGND represents another ground plane which will be an "island" in main ground plane (PGND) and will cover area where digital devices resides (ADC, DAC, I/O expander). Post-regulator output "minus" is connected to the current sense resistor R37 which is with its another end connected with thick trace (150mil) directly to the input ground (PGND on X3). I'm using here a SH1 as a trick to avoid Eagle to automatically connect that resistor end to the main ground plane.Two ground planes are connected together in the point close to the ADC using ferrite bead FB (or that can be a zero-ohm jumper). What is remain is a signal labeled as COM which represent reference ground point. Again it is planned to be connected closely to ADC with other ground and for that SH2 is used. On the same signal I presume that will be good to connect ADCs REFN0 which exists onADS1120separately from AVss input.I put here also supply ground from voltage reference (REF5025) and DAC (DAC8552). Not so sure about that and I'd like your inputs about such proposal and comments in general about presented approach.Many thanks in advance.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 05, 2015, 03:10:03 pm
content: Unless there is lots of noise comming from the digiatal part, I would not hat the ferrite bead in the DGND-PGND connection. There is no need to introduce extra differences here.Normally its better to have one good star point, and have things like FB on the supply rails.Things like DGND just use one common connection to the starpoint, for things that are not critical.At the reference, DAC and other ICs, the local supply decoupling still needs to be with the GND of the chip. So if the device like the DAC has only one GND Pin, this pin has to be used for decoupling. To reduce noise coupled from the supply a FB or inductor from the +5 V rail to the cap / VCC pin can be used. In extrem cases one may need an extra electrolytic cap for decoupling, if the chips are drawing more current with LF component.AREFN0 at the ADS1120 is part of a differential input. So connect it to GND at the reference.An important part missing in planing GND layout are the volatge regulator for the 5 V supply and less important the supply to the OPs.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 05, 2015, 07:33:42 pm
content: Please don't split grounds. If you aren't absolutely certain about what you are doing, you are absolutely better off using one, massive, continuous ground plane underneath everything (or for 2-layer construction, pours on top and bottom, stitched liberally with vias).Alarm bells that go off immediately:(and by that I mean, not just yellow warning flags, not just bright red error flags, but big clanging bells!)- VREF has local bypasses, but GND isn't returned to same net!- op-amp supplies, bypasses not shown- DAC has no AGND. Is bypassed to PGND, but GND isn't returned to same net!- ADC has DGND and AVSS on separate nets!About that last case: chips with multiple ground pins are usually constructed so that, in reality, all the grounds are "shorted" internally by the substrate, or a ground metallization layer or whatever. It doesn't look like a good short at circuit-level, because ICs aren't as conductive as copper foil. These pins usually have < 10 ohms between each other, and I think 0.3 ohms is typical. It's not < 0.01 ohm as you'd get from copper foil spanning the pins. That means any current flow or noise across those grounds, appears across the IC, internally, which will likely cause problems. Under fault conditions, it will easily destroy the IC!No, grounding is not a netlist problem. Not in general. It cannot be solved through an abstract netlist assignment. It is spacial, and can only be controlled by placement of devices. Learn the nature of "path of least resistance" and "path of least impedance", and arrange functional blocks so that they don't have intersecting current paths. When you do this, and follow logical practice, it makes very little difference if the ground plane is slotted or not (because you will never have signals crossing the slot), and you will never have to worry about splitting grounds around analog signals (because it's a dumb idea in the first place; thing is, one must know why, and all those appnotes that suggest it... usually don't know why!).Tim

author: Jeroen3
author_rank: Super Contributor
timestamp: August 06, 2015, 05:44:40 am
content: Basically you want to make sure the path first reaches the cap before the via to the ground plane. Thus: chip - cap - ground, and not: gnd, chip, gnd, cap, gnd as happens a lot when you apply the top fill. You might need to play around with the Restrict layers for this.I wouldn't put a ferrite in the ground split, instead, I would use the ferrite at the source for the ref. But I don't know how efficient that will be. However, ferrites make more sense if put in the signal path after the connector. That is where all the noise is able to enter the system.Also, the splitting the ADC ground is not the best practice. They've developed two Vdd's for Analog and Digital, but they did not develop two GNDs, they are internally connected. You might force unnecessary noise and currents through the adc. If you're using only 1 supply, I wouldn't bother splitting the decoupling.The Vref will need local (almost on-chip) decoupling though.Funny how you've put 1uF's at the ADC, but not at the DAC.At the end it stays a bit of black magic, only really understood by few.

author: piranha32
author_rank: Unknown
timestamp: August 06, 2015, 06:30:48 am
content: First of all, remember that each signal line *MUST* have corresponding return ground path. Therefore the best way to route ground is to have large ground plane. If you must achieve 24 bit precission, and really have to split grounds, make them connect at the points where the analog and digital signals meet. In your case these would be A/D and D/A converters, however with common Vref it will be difficult (if possible) to split the ground in a way which guarantees good separation without loops. One of my "to go" resources when it comes to EMC issues is the website of Henry Ott Consultants. Here is what they have to say about ground planes: partition the design, but do not split the ground plane (http://www.hottconsultants.com/techtips/split-gnd-plane.html). TI recommends to start with split grounds, route all signals over corresponding ground planes, and in the final step remove the split:http://www.ti.com/lit/ml/slyp167/slyp167.pdfYour circuit looks simple enough to route all signals on one side. If you care about signal integrity, spend a dollar or two more and order double sided PCB with solid ground plane on the bottom, and connect all ground leads directly to the bottom side using track as short as possible.

author: prasimix
author_rank: Unknown
timestamp: August 06, 2015, 10:38:41 am
content: Many thanks to all that post so many useful comments and references. Maybe to start with a sentence found in Henry Ott's article recommended by piranha32:QuoteThere are two useful keywords:partitioninganddiscipline. Actually in previous revision of this PCB I followed routing discipline 100%: that no analog traces cross digital plane and vice versa. I'll continue with such practice. I didn't aware of partitioning but it's connected to mentioned discipline, it seems that at the end when everything is routed properly it's question of merging two planes into single one. But, it seems that there is still some exception from above mentioned rule of single plane (thanks T3sl4co1l to highlight that at the very beginning!). Henry continue saying:QuoteFew technical details from previous layout that address some of your comments:A double layer PCB is usedAll supplies comes from nearby pre-regulator PCB: +5V is supplied from LP2951 while +/-15V comes from another LP2951 and LM337LADC's Dgnd and AVss are on separate nets but that DGND and PGND are connected just next to ADC's Dgnd and AVss to ensure low impedance pathAll op-amps are decoupled with 100nF against +15V and -15V power rails.I'm understand that it is hard to discuss such complex topic without presenting details about PCB layout. I'd like to post it soon at least general idea about ground plane(s) and positioning of presented analog and digital devices with power traces. Before that I'll be free to post another version of schematic that take into account some of your suggestions. I planned to "strengthen" decoupling of current sense monitor (it could be OP27 or OPA227). Currently it works fine with only 100nF. SH2 and SH3 remains to have more control of grounding while (manual) placement and routing is performed.

author: prasimix
author_rank: Unknown
timestamp: August 06, 2015, 10:44:17 am
content: Quote from: Kleinstein on August 05, 2015, 03:10:03 pmI forgot to include this detail in the previous post. That possibly will require adding another "SH" in the schematic or moving existing SH2 from DGND to PGND.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 07, 2015, 10:04:25 am
content: A well planed ground is important for 4 purposes:- keeping HF emissions down- matched impedance lines- reducing HF coupling between circuit parts.- avoid LF / DC coupling to sensitive lines.Here it is likely more about the last two, especially the last.When it comes to DC and LF errors the best scheme is usually a star ground. The single solid ground plane is often the best when it come th high frequency noise an emissions. The version with seperated ground planes is a try to get the best of both, but it's difficult to make it right.May suggestiong would using some kind of ground plane for the digital part (not shown in diagramms) and a star GND scheme for the rest. Form the central GND point there would be connections for:- the supply (5V, +-15) from regulators- the high current supply (if not allready connected at preregulator)- the digital part- the anlog signal GND, possibly more than one- the anlog supply to circuit / decouplingFor drawing one might have the jumpers at the central GND point and thus different name for the nets.In this context the DAC and also the ADC should be treated as analog parts. So GND at the DAC should not be DGND. The Ref to the ADC is differential, so no need to go though the star point, but connect directly to the reference.

author: prasimix
author_rank: Unknown
timestamp: August 11, 2015, 08:25:46 am
content: Hi everyone, here is how PCB layout currently looks like:You can see on the picture digital section (cyan) which is designed with partitioning in mind so no analog line is crossing that area. Voltage reference is closed to digital section but again,Vrefoutput is routed "around" and connected to DAC and ADC. I also marked with white circles three grounds that is now connected via ground plane and not using separate net connected in single point with the ground plane. This is something that I didn't have in previous version of PCB and wondering if I have to proceed with that or not. If I reverse that to separate net that will be closer to star ground that Kleinstein suggested for the analog part. Result of deploying strictly star ground for the analog part on this PCB with only two layers possibly will results with heavily fragmentation of the current ground plane. It that case maybe we could talk about ground plane but in lower area (around digital section) and the rest to do with star ground. Both of them will be connected then on light green point (input connector) and that looks effectively to me as two grounds.Anyway bottom layer currently looks like this:Digital power line is marked in the following picture. Voltage reference is supplied from the same line. I don't know if that is optimal. Another possibility is to draw power from +15V and use dedicated LDO to step-down to +5V for that purpose.Analog power lines are visible on the following picture:Thanks in advance for all your further comments and suggestions.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 11, 2015, 10:18:56 am
content: The analog part does not need a ground plane - a ground plane is good for HF signals, but not LF µV signals.A ground plane might be a good idea to reduce EMI from the µC part or other high frequency digital part. The ADC and DAC usually do not see much data trafic - so even they can live without GND plane. In ADC/DAC area, the current layout does not have a GND plane, that deserves this name.There are two more week points:There is no decoupling of the input side of the high current supply - linear regulators often need these to work stable.The ground line to the shunt and the positive output current through the transistors form a relatively large loop this effectively adds quite some inductance (about 100nH) - too much for a fast regulator.

author: prasimix
author_rank: Unknown
timestamp: August 11, 2015, 10:46:11 am
content: Quote from: Kleinstein on August 11, 2015, 10:18:56 amDo you mean that current plane beneath digital section is too much fragmented to deserve name ground plane?Quote from: Kleinstein on August 11, 2015, 10:18:56 amHow to make such decoupling? I didn't notice yet any instability withexisting PCBwhich is very similar to this one.Quote from: Kleinstein on August 11, 2015, 10:18:56 amTrue. It predicts then also slow response with existing PCB that I probably can measure. How to check that? Perhaps with load transient testing?

author: Kleinstein
author_rank: Super Contributor
timestamp: August 11, 2015, 06:19:42 pm
content: The "ground plane" under the ADC is to fragmented to be called a ground plane. It's more like using ground poor to get ground to all the points, without giving much thought to GND. Anyway the ADC/DAC does not absolutely needs a ground plane, unless you control it via a very high slew rate signal or do something like dithering. Something like a busy µC controlling als graphic LCD or USB 2.0 Interface is something that should have one.The large Loop adds something like 100 nH (maybe a little more), not having a capacitor (or two) at the input side of the high current supply adds the inductance of the external wiring. Having a cap on baord would use the wire inductance as extra HF filtering (though with some emissions) instead of having it on the down side. It would be a good Idea to have something like 1 µF ceramic and something like a 100 µF of low ESR on board, close to the final regulator.Its similar the the simple 3 pin chips llike 7805 - they also like to have a cap at the input, close to the chip and not on an extra baord.How bad the extra inductance is, depends on the regulator - the faster (and thus lower impedance) the more critical. Extra inductance can also eat away reserves for critical loads and may be how low the ESR of the output capacitor may be.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 11, 2015, 08:07:15 pm
content: I would have to take quite some time to figure out where everything is; this also appears to be far more than the schematics posted above so you need to provide a complete one of those, too.There is never any reason to remove ground pour. If anything, add more. You have many resistors, etc. that have short stubs to a via: those can be removed when a full top-side pour is used. Or better yet, the vias can be moved around (possibly more added, even) for better stitching of both top and bottom grounds.If digital is one small corner, then I don't see that it should be any concern with regards to the rest of the circuit. The reference being down there might perhaps be subject to noise, but if it's only being used by the ADC/DAC, it belongs there.I would be concerned about possible ground loops. If you have power (+/-) and load (+/-) from connectors on opposite sides, you can have ground loop currents between those connectors, which generates a voltage drop across your board (which will be particularly important, because your bottom pour is sliced vertically by several traces, which are not stitched over).Microvolt, low bandwidth circuits are much more susceptible to high frequency noise, because small rectification effects result in much more important errors. This is also an excellent reason to sanitize all inputs, as well as possible, filtering out frequencies that you don't need to consider.Tim

author: prasimix
author_rank: Unknown
timestamp: August 12, 2015, 08:24:49 am
content: Quote from: Kleinstein on August 11, 2015, 06:19:42 pmHm, ground plane is fragmented to some extend under I/O expander not ADC nor DAC. Please find below their position on the PCB with bottom layer visible. There is only one diagonal trace that goes beneath ADC that I didn't succeed to route on the top player.I also added another 1u decoupling capacitor close to the input power connector. I also put back a 22u elco that is planned to be mounted on the chassis output binding posts.

author: prasimix
author_rank: Unknown
timestamp: August 12, 2015, 08:28:58 am
content: Quote from: T3sl4co1l on August 11, 2015, 08:07:15 pmPlease find in attachment the complete schematic. I tried to avoid that for sake in simplicity at the beginning.I'll try to make few another variants to explore both yours (as much as possible ground on the both side) and Kleinstein approach (star ground for the analog section).

author: Kleinstein
author_rank: Super Contributor
timestamp: August 12, 2015, 10:48:11 am
content: I don't think the digital/ ADC/DAC part will be a problem - it's not perfect, especially form EMI perspective, but should work.With the analog part, I see one problem in the circuit with the 22 µF output capacitor going to PGND. Normally the output capacitors should be toward the neg. output - thus at the other side of the shunt. The shunt helps the compound outputstage to be stable as it allways has the shunt, and no low ESR capacitance to GND. Its very unsual to need a cap to the GND before the shunt.Having the cap before the shunt also makes it more effective to provide a low impedance output at high frequencies.The current layout for the 22 µF an 470 nF/1 Ohm is also a problem: The GND currenc couples somewhere to the "GND plane" used for the volatge regulator - so it can interfere with regulation and worst case cause instability. With a plane, especially with some cuts, its very hard to predict what happens.The large high current loop over the upper analog part will also inductively coulple to the ground plane: very hard to predict what happens - instability is possible, though not likely. So it would be really better to have the connectors rather close to the upper end, and the shunt close to the output stage. Even the output connector would be better Out+ Out- Sense+ - .Though this is only a DC supply, layout should really minimize inductance for low impedance parts, as at 150 kHz a 100 nH inductance has allready an impedance of 1 Ohm and thus is important for a low impedance output.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 12, 2015, 11:52:04 am
content: FYI, Q4 gate is coming out the wrong side (note on Q1, it's drawn exiting from the source side). Also, BSS84 would be more traditional there, though it won't make any difference if you don't mind the extra capacity of the IRLML2246.If you want a more accurate near-zero threshold for IC4, you can replace R53 with a pair of resistors to GND. This anchors the middle of the divider (indeed, splits it into two separate dividers), so that ratio differences in R50/R55 have less effect.Also, the output resistors as chosen (R48, R49, R54, R56) are such that D12, D13 don't do anything. The diodes might be relevant if the supplies come up at different rates (though, within ratings, the MOSFETs will never be in danger). Or if you want to make use of them, it would be perfectly fine to reduce the resistor ratios, so that the diodes become forward biased while the comparators are on. Really doesn't matter, it's very mildly redundant.(I guess what I'm feeling, philosophically, is: if you have the choice between two nearly equivalent options, you must be near -- but not on -- a local minima; this is a sign that you perhaps should rethink the thing, until you find an even better local (perhaps even global) minima. At least, when it's something that's actually worth the work.)The voltage compensation (around IC1) seems odd. There's a mess of lead-lag compensation (C4-C7, C9, C10), which seems to suggest you're trying to beat causality. Which is impossible, of course. A resistor in series with C8 would help (some pole-zero action, presumably to cancel a different pole, maybe that due to Q1's gate capacitance?), and probably slowing down the whole thing so it's not so much on the knife-edge of stability.It also wouldn't hurt to have some raw C-to-ground on those feedback nodes, just to take the edge off.Which segues into the other filter thing: the shunt sense IC3 should have some filtering on its inputs. This is a bipolar op-amp, at very small signal levels, so it will be doubly important to keep HF noise (anything over perhaps 500kHz) well away from it. R35, R38 are also rather low values, which are something of a fault hazard to IC3 -- short circuit current through the shunt can deliver quite a bit of current into the IC's input protection diodes. I'd suggest >100 ohms, perhaps split in half (2 x 51 ohm each?) with a 4.7nF to ground (in the middle) for filtering.IC1B should also have some filtering, for similar reasons: suppose you have a heavy, nasty switching load connected to this thing (maybe it's an unfiltered DC-DC converter drawing nasty current spikes, or a high voltage generator spewing out common mode interference). That noise goes straight into your op-amps, which respond asymmetrically to RF inputs, resulting in shifted bias points and DC error. Now, TL071/2 is a FET amp, which is less susceptible to interference, but I'd still add a 1MHz or so LPF to be sure.BTW, you might swap IC2 for 1/2 TL072, just to save a BOM item. The extra half can simply be grounded (+in = out, -in = GND).Going back to IC1 and IC2, it seems rather odd to use +/-15V supplies, yet use only about the -2 to 0V range. You should use only as much as needed, so the outputs don't have to slew so far when they go into the linear range. This reduces integrator windup, which is a significant limitation on the speed of this type of control circuit. Simple solution is to increase R24 and/or R18 dramatically, so the gain is lower and the useful op-amp range is wider.Alternately, you could rewrite much of the circuit to use, say, +/-5V supplies (which would eliminate one supply), and use a R2R type amp like TLV2372.ZD2 seems kind of out of place. I don't like to see zener diodes chained in series with things, used as afterthoughts for burning voltage; it's a lazy method that often leads to problems arising from side effects. I'd just as well clamp Q6 collector to ground with another BAS316, which seems to be fine as it's already current limited. Also won't need D2, as D3 prevents backflow from anything else (Q2 and stuff are always below Q1 source, so aren't going to turn it on, ever).The Q4 pulldown stuff seems odd (it's like Q1 and Q4 act as a complementary source follower pair), but I guess it's really only being used as a turn-off discharge. Beware that it won't operate very happily if you were charging a battery pack then hit the "disable" switch! (That said, 50V maximum and ~0.3A limit suggests a modest 16W maximum dissipation, which is fine for a TO-220 MOSFET like that. As long as you have the load current displayed, the user will be able to see their battery charge being pissed away, too.)Note that Q5 can beat the shit out of Q1 gate (in the turning-on direction), but nothing is there to discharge it (just measly little R3). So you'll get the weird situation that, if it's on the verge of oscillation, it's able to rise much more quickly than it falls, and this can lead to weird load- or state-dependent compensation, and possibly chaotic behavior. A more symmetrical driver would clean that up, and also raise the cutoff frequency of that node, easing compensation for the gain stage (i.e., Q9 and related parts) and error amps.Note that Q5 doesn't have a nearby bypass cap, which may make things ugly for that bias supply (I don't know what's plugged into it, a board-to-board or a cable or who knows).Anyway, on to the PCB:As mentioned, you've got tons of slots going vertically along the bottom ground pour, so all those traces crossing them on top (Q10, R27; and by extension, the power going up to IC1 -- note that the PSRR of an op-amp is more dominant than RF susceptibility!), as well as extending downward until those loops close up (so this includes injecting noise into C11-C12-C14 and IC3).The power circuit makes a grand loop, from X1 around Q1-R1 down to X2, then back through R37, over split ground. If this circuit is exposed to ground loop current, it will feel every little bit of it in this loop here. The voltage sense amp is right there, which kind of sucks. Like I said, it's somewhat less sensitive, but it's still not desirable for accuracy.Ideally, all the grounds (especially on connectors) should all be joined together, as closely as possible, thus minimizing ground loop areas, and keeping any ground loop currents away from your main circuit. This would require moving X1, X2 and R37 near each other, perhaps making the return path above Q1, Q4 (they could be changed to horizontal orientation, parallel to the board, installed on the bottom side but facing up, perhaps?), and moving the connectors somewhere up near a corner, or along the top edge.I'm guessing the rest of the circuit isn't a big deal. X3 has some grounds, which might be worth looking out for (minimize possible ground loop areas!). I'm hardly concerned about SPI and digital; those are hiding in the corner, well away from the analog parts.But you should follow much the same idea, for the analog part as well: so the small-signal parts (op-amps and all) are isolated in their own group, away from the power path (Q1, Q4 and etc.), to keep them out of the way of stray currents and such.And, again: top side pour, and lots of stitching! For example, stitching over the slots in the ground pour (formed by the supply traces coming off X3 and running vertically for most of the board) just about eliminates that concern, so that the R37 path can be almost as good as the most suitable alternative (curving back above Q1, Q4). But avoiding signal and power trace crossings altogether is even better, so try for that first.HTH,Tim

author: prasimix
author_rank: Unknown
timestamp: August 12, 2015, 02:50:49 pm
content: Quote from: Kleinstein on August 12, 2015, 10:48:11 amHuh, you're right. It's wrong placed in schematic and as I said it was planned to be connected over binding posts that means in parallel with Out+ and Out-. I'll correct that in next revision.Quote from: Kleinstein on August 12, 2015, 10:48:11 amGood point, thanksThat swap will be visible also in next revision.

author: prasimix
author_rank: Unknown
timestamp: August 12, 2015, 03:15:58 pm
content: Quote from: T3sl4co1l on August 12, 2015, 11:52:04 amA massive thanks Tim for such review. I'll try to comment as much as possible soon. But before that I'd like to hear what you think about merging X1 and X2 together. That should improve electrical characteristics since op-amp bias supply will not require such long vertical traces. Main return (power ground) is anyway planned to be on X1 connector only.The post-regulator is directly connected to the pre-regulator PCB with that two connectors. Using one will somehow weaken mechanical strength but not so much since main mean of fixing both PCBs is using four screws on the corners.Quote from: T3sl4co1l on August 12, 2015, 11:52:04 amPlease let me know if 1uf ceramic is enough here? This bias comes from rectified and filtered by 470uF 48VAC main power.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 12, 2015, 07:05:16 pm
content: For Q5 1 µF is plenty decoupling. Even 100 nF should be enough if the line is not very long.I think there are two problems:First there still seem to be a few (hopefully minor) weak spots in the circuit. Some of this is more than changing values.And than the layout is not good.Usually it's best to fix the circuit first, as this might give some changes (e.g. resistor in series to C8 is a good idea) - even if only minor.I also agree that the compensation at the input side of the differental amplifier needs a makeover: Because of the differential stage its essenstally double. Still I think it can be simpler: usually one cap per side might be enough - mainly for the switchover from DC feedback from the Sense inputs to high frequency feedback mainly from the outputs. This is needed to prevent oscillations if power and sense lines are not closely coupled. There is essentially no other way to prevent oscillations with poor external wiring to a capacitive load. Even than a very poor configuration of the sense wires will oscillate - but that is close to using transformers.A llittle higher impedance at the current sense amplifier is a good idea to make it survive surges and may be even a burned / loose shunt. Some filtering is OK, but not to much, as this makes regulation more difficult. The most important point for filtering is a low ESR/ESL cap directly at the input therminals and small extra caps to the case.For the layout, its usually best to start with the critical connetions. With this circuit this is first the main current path and the return ground. The next in importance is ground. It is Ok to show only partial layouts e.g. with just the critical part - here groundfill makes it hard to follow, having true lines for GND is clearer, even if later ground fill is used.Usually using ground fill with a plane cut into small pieces is not helping with EMI or cross coupling. So either have a closed ground plane that deserves the name (high currents still need to be handelt separately) or have separate GND lines and GND fill or lager GND areas mainly for thermal reasons. For the signal quality such partial fills usually don't help.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 13, 2015, 02:04:06 am
content: How long is the connector/cable route expected to be? Figure 10nH/cm times the length of traces/connectors/cables between the bypass cap and the main bulk cap. The ideal ESR is sqrt(Lstray / Cbyp). If this ESR is present in the bulk cap, you're golden. If not, you might want a series resistor for Cbyp, or add a lossy bulk cap across it (Cbulk >= 2.5 Cbyp) with that ESR.Merging the connectors would be helpful; this goes under my suggestion of putting them nearby.Tim

author: prasimix
author_rank: Unknown
timestamp: August 13, 2015, 08:33:04 am
content: I finished a part of my homework initiated by comments from Kleinstein and Tim (T3sl4co1l). The first sheet (in attachment) from schematic is now includes the following changes:1. Decoupling capactitor C4 is added2. IC2 is changed to half of TL072 to reduce BOM items and price (I found that TL072 is cheaper then TL071).3. Input section of IC3 is now redesigned. I have to use two resistors to get 4.080K required to get gain ov 40V/V in combination with 102R (2x51R).I run by mistake renumbering so please note that items numbers is now different.I finished the first remake of PCB layout which do not include merging of two input connectors (X1 and X3). I deliberately limit ground plane to bottom half of the PCB to have a clear picture of ground net in the upper part. I didn't experiment yet with adding ground plane on the top layer. Three solid area on the top layers represents heatsinks for Q4, Q6 and Q8. You can also see that I remove huge loop by moving return trace (Out-) up, next to Out+ (each traces are ~90mm long). Here is how both layers looks with ground plane cut to half:Bottom layer with ground plane cut to half:I spent some time to color code important paths on the bottom layer:Now if we extend the ground plane to cover complete bottom layer again it looks like this:It looks pretty good to me and the question is with which bottom layer layout to proceed?In this moment I'd like to address multiple warnings about possible instability of the circuit with asking the following question again: what types of test cases can be used to sport such instability? I made until now a lots for testing with various combiantion of set voltage and current to cover full range (50V, 3A), going back and forward between CV and CC mode and made that with various loads such as different power resistors, halogen lamps, DC motor, capacitors and inductors.

author: prasimix
author_rank: Unknown
timestamp: August 13, 2015, 08:43:04 am
content: I have one question about using multiple vias to connect one leg of current sense resistor (R39) to bottom layer: does 8 vias is sufficient for 3A current (possibly up to 5A)?I am thinking about remove protection mask from them to make it solderable and fill it additionally using soldering iron.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 13, 2015, 09:22:43 am
content: The layout looks much better. How much current the vias can stand depends on the manufacturer. They should have numbers. having the option to solder is a good idea, just in case.For stability testing, the critical tests for voltage regulation are:Sinulations should include realistic parasitic inductance for the shunt / GND path (here maybe 50 nH).The voltage set to do the test should not make a difference with this circuit. Usually the extremes are worst.1) just a current souce (Spice part), as load. DC current near 0 + AC Current -> effectively look at output impedance2) same as before, but higher current (e.g. 2/3 of max.)The output impedance should not have any phase shift larger than +-180 deg.For the range around 1 MHz, adjustung the output capacitor and possible series resistor might helpThis 2 test can test most cases of instability. Idleally one wants a low impedance and enough distance to the +-180 deg. bounds, at least where impedance is not very low. So getting very close (e.g. 175 deg.) at something like 100 Hz is normal, but the 100 kHz - 10 MHz range should have much more reserve (e.g. > 30 deg). However there may still be poor regulation - especially if one only looks to frequency domain and trys to defeet causality by adding more and more RC combinations.So the final test is in time domain:3) Testload of pure cap + current source with steps of something line 10 mA / 1 A and back with something like 1 µs rise/fallCaps at something like 10µF , 100µF, 1000µF and 10000µF with low or 0 ESR and possible realistic values.Quite some ringing at 10 mF (or more) and 0 ESR is more or less normal. Just a few mohms of ESR

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 13, 2015, 11:18:55 am
content: Ground plane looks good. Some routing tips:Observe the negative space, which is filled by the pour. Try to have it wrap around every trace (or grouping of traces) if possible. Examples (pour has been colored cyan for clarity):On the bottom left, these are a good example. The ground fill keeps the traces isolated, and somewhat reduces their impedance / inductance (if this is useful). Downside: takes up a lot of space, so it's not so handy to do for a bunch of signals at a time (say, a parallel data bus?).Here's a tiny hiccup, of sorts. If the via can be moved, allowing the pour to close around the pads, you might as well. The loop in this case isn't very big (the peninsula is only a cm or two long), so it won't be "flapping around" with much inductance, certainly not enough to notice in a circuit like this. These kinds of details get more important in switching or precision or RF, so it's a practice-makes-perfect sort of thing to be prepared when/if you do work on such circuits.Where you have a bunch of traces, it can be handy to group them, or hug along routes -- but mind that, in doing so, you trap and isolate the pour where the traces gather. If there isn't much advantage to gathering traces, say over a short run, you might as well give more clearance to everything, so the ground can fill. A possible re-route is shown in red.Remember that every trace is cutting a slot into the pour. Around this trace, there may be slightly different voltages on the left/outside and right/inside bits of pour. You could fix this with a hack, by adding a two vias and a short trace to jumper over this splitting trace, or better still, stitch it with top side pour wherever possible.Tim

author: prasimix
author_rank: Unknown
timestamp: August 13, 2015, 02:24:59 pm
content: Quote from: Kleinstein on August 13, 2015, 09:22:43 amThanks Kleinstein. I realize that in fact my question is off-topic and that will be better to continue with such discussion in the mainthread. I expected some real-world testing and I'll definitely will need some further assistance how to conduct proposed tests (both as simulation and in real world).

author: prasimix
author_rank: Unknown
timestamp: August 13, 2015, 02:29:22 pm
content: Quote from: T3sl4co1l on August 13, 2015, 11:18:55 amYes, its much better when more pairs of eyes looks into it. I spent so many hours that I became temporarily blind to red and blue (and yellow).I'll add on few places mentioned hack with vias since that seems better then top side pour, or maybe not. I have to check that (does not cost a lot to try).

author: prasimix
author_rank: Unknown
timestamp: August 13, 2015, 03:04:46 pm
content: hi Tim, here are some replies to your recent review:Quote from: T3sl4co1l on August 12, 2015, 11:52:04 amYes, thats strange. I used some existing devices from Eagle library where PMOS symbol was not correct. I've fixed that by creating my own device.Quote from: T3sl4co1l on August 12, 2015, 11:52:04 amTrue, it's used on another PCB that belongs to this project and I just copy and paste it. It's overkill here and can be replaced with i.e. BSS84.Quote from: T3sl4co1l on August 12, 2015, 11:52:04 amAlready done. I tried to save one THT resistor place on the PCB in the past but now that is completely pointless.Quote from: T3sl4co1l on August 12, 2015, 11:52:04 amThat was also something that was really old and as you said D12 and D13 doesn't make sense. With replacing +/-15V with +5/-5V rail supply it should looks like this:Quote from: T3sl4co1l on August 12, 2015, 11:52:04 amI put that in the latest revision of the PCB. Using small resistors was inspired by some schematic of current monitor mentioned in LTC2057 datasheet (pg.23).Quote from: T3sl4co1l on August 12, 2015, 11:52:04 amWhy +/-15V is still here I really cannot remember. It was required for some of the first version and when I decide to make adaptation of Liv's circuit where +/-5V is also used, its really don't need to be here anymore. Especially because stepping down with existing pre-regulator where bias supply is located should not be a problem at all.Quote from: T3sl4co1l on August 12, 2015, 11:52:04 amThat is a so-called "down-programmer" (DP). It helps to set faster new value that is lower then current one. DP as OE will be controlled by MCU and mentioned scenario will not be allowed. But, controlled battery discharge will be one of the possible scenario. If someone like to use post-regulator without MCU board it simply has to connect OE and DP switches in serial:

author: Kleinstein
author_rank: Super Contributor
timestamp: August 13, 2015, 06:55:32 pm
content: The down-programmer may also help to have some bias current, so that the output stage is not starting to operate from idle. This helps to get a fast and stable regulation, as the parameters of the output stage don't change that much. So having a minimum current from the down programmer will likely alow for a faster response. So the option to turn of den DP is two sided.However it migher be neccesary to replace the 6.2 V zener diode with something adjustable, as to control the idle current and compensate for varying U_GS of the MOSFETS.However the downprogrammer looks relatively complicated compared to a classic complementary follower.For those who want to charge batteries, just add a second output with diode and fuse, specially for charging. This might save the circuit in case of reversed voltage.In checking stability from output impedance, the limits are no more than +-90 deg. of phase shif of cause, thus something like a passive load.I did a quick simulation of the circuit - though with some parts exchanged to types where LTspice has models. It looks generally Ok, if C15 (extra FB to voltage regulator) is removed. Input to the differential amplifier can be simplified to 1 cap each.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 13, 2015, 08:44:01 pm
content: Quote from: prasimix on August 13, 2015, 03:04:46 pmOf course, you aren't using an LTC2057, and you aren't using the same circuit type either.I think they just did that for brevity: to get a ~1k load on the output (so the diode works, if present), they need a 1k feedback network. Which needs 10 ohm resistors for a gain of ~100 (well, 101). The other resistor (to +in) I think is just a formality, i.e., you always want similar or equal Thevenin resistances to both inputs, so that input bias current (which is likely to be equal when everything is settled in equilibrium) doesn't induce an offset.Which is a funny example, because with <1nA of bias, 10 ohms will produce <10nV of offset, well below Vos, and down in the noise floor where you may not be able to see it at all (over any time scale, because 1/f noise directly interferes with DC measurements).Now, it is worth noting that some current sensors do find this very important. The AD8210 current sense amplifier exhibits a large input bias current when the inputs are somewhere below VCC. It also has a high voltage tolerance, so it's fine to have the inputs riding well above VCC, and it's just fine to connect it directly to a power rail (high side current sense). It's a very special kind of differential amplifier. Most general purpose diff amps won't be so inviting, and you need traditional precautions.QuoteCool, that'll probably save a fraction of a watt besides (hey, it's something?). Always nice to cut down the number of supply rails needed.Cheers,Tim

author: prasimix
author_rank: Unknown
timestamp: August 15, 2015, 11:44:25 am
content: Here is the latest revision where two previous input power connectors are merged into single one. The voltage reference is also moved up.Ground plane is now looking like this:Some manufactures recommend that ground plane should be omitted with certain op-amps due to possible negative effect of stray capacitance. Don't know if such thing is applicable here. If that is the case, a "star-ground" in top half can be still created.I'd also like to hear your opinion about ground on the pre-regulator PCB which (schematic is in the attachment) looks like this:On the bottom layer I connect ground return to the bulk capacitor minus terminal (that is not the case if three smaller capacitors is used to have better ripple current figure):

author: prasimix
author_rank: Unknown
timestamp: August 15, 2015, 12:04:04 pm
content: Quote from: Kleinstein on August 13, 2015, 06:55:32 pmHi Kleinstein, please let me know what did you find out about C15. How it affects the whole circuit?

author: prasimix
author_rank: Unknown
timestamp: August 15, 2015, 12:20:56 pm
content: Quote from: T3sl4co1l on August 13, 2015, 08:44:01 pmThere is a still one possible obstacle to move from +/-15V to +/-5V. Down-programmer circuit require negative voltage which has to be a little bit over -5V or logic level p-ch mosfet for Q5 has to be used. Unfortunately it seems that such device is a rare animal in TO-220 package and at least -55V. Until now I found just a few: IRF'sIRLIB9343or Vishay'sSUP53P06-20andSUP90P06-09L. Another possibility is to extend input power connector for another two pins and bring -8V from pre-regulator that is used for -5V LDO.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 15, 2015, 12:49:35 pm
content: Quote from: prasimix on August 15, 2015, 12:20:56 pmAh, but it's not hard switching, is it? And it doesn't much matter if it does, as long as it's able to pull the output reasonably low with enough current (100mA? amperes?). All of these seem to be overly large, in fact! Though you might have to simply roll with it, to get the power dissipation.I'd avoid the IRF part: just at first glance, Vgs(th) is not in a guaranteed range, and that's no good for a linear or semi-linear sort of application. The SUP53 seems nice, and is also guaranteed for switching at Vgs = -4.5V, so you know without a doubt it's more than overkill. The '90 is most likely a scaled up version, so unless you need the sheer switching capacity, you're just paying more for no benefit. You can probably go much smaller, if availability and dissipation are still there.Board layout looks generally good. You've got good conservation of ground continuity and all that, I see more use of vias, and the main current paths are either routed closely, or bypassed nearby (in the case of the power supplies).A note: I see the ground "jumpers" you've placed, but they're used a little inconsistently: that is, the longest bottom side trace has one jumper over it, splitting it into two spans...which in turn still have lengths several times of any other slots!If you are limited to one jumper, placing it towards the middle is probably the best idea (which I think has been followed), but if not limited -- the more, the merrier.The purpose is partly to address the inductance (or the RF resonances) of the slots, but equivalently as well, the sources that might induce currents into those slots -- namely, any top side traces crossing them. To keep current loops smallest, the jumper(s) should be placed alongside the most sensitive, noisy or high-power traces that cross the slot. So you're not only shorting across the slot (making it a shorter electrical length), but providing a current path, directly where it's needed, preventing that offending current from inducing currents elsewhere in the first place.I'd also suggest using wider copper (in most cases I think you have enough space to go at, say, the via OD?), since the main hazard to a power supply application will be low impedance ground loop currents, and a thin trace isn't much better than a slotted pour, even if it's pretty deep.Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: August 15, 2015, 04:19:36 pm
content: If negative supply for the down programmer is a real problem, one could also change vom a PMOS to a PNP. Something like a MJE15029, (BD140 is rather low in maximum power) might be an option - just the zener diode needs to be adjusted to a lower voltage. At least resonable fast PNPs are relatively easy to get, and U_BE is lower and rather well defined.I did a few more simulations (much of it just variations of the output stage):In the regulator C15 (old numbering) is usually just causing trouble - the best results where whithout it. This is also clear, as it trys (not working this way anyway) to compensate for the drop at the shunt at high frequencies. However having the shunt and thus some resistive part is actually very good at high frequencies - this one known way to stabilize with capacitive loads.With a MOSFET output stage it's really a bad idea to run without or a low bias current. At low currents MOSFETS get much slower than they are at high currents. So the in principle fast MOSFET looses it's advantage over a BJT power stage. Without any bias through the downprogrammer the loop would have to be tuned really slow - thus resulting in rather poor regulation or instability at low volatges (current throug resistors goes down). BJT also tend to get slower at low currents, but the effect seems to be not that strong. So a BJT power stage miight run with lower bias - though the driving stage will need more power, so the savings may not be large.So I really see no use i turning the down-programmer off - the regulator is just not working well without it. If really needed an extra optional diode at the output might be an option that causes less trouble to regulation - in this case one might have the option to have a slow regulation only at low currents, getting resonable fast if more than some 100 mA are used. Having something like 100mA bias may mean up to 4 W of waste heat - not good, but still viable mains powered.If no need to turn the down programmer off, the output stage could be simplified a little, using less diodes etc.

author: prasimix
author_rank: Unknown
timestamp: August 17, 2015, 10:41:20 am
content: Quote from: Kleinstein on August 15, 2015, 04:19:36 pmYou're right. Down-programmer (DP) should be active most of the time. There is two possible scenarios for switching if off independently of Output enable (OE) control: one is when charging a battery. Another is when two channels are connected in parallel. It seems that is better to have only one DP active.

author: prasimix
author_rank: Unknown
timestamp: August 17, 2015, 10:44:09 am
content: Quote from: T3sl4co1l on August 15, 2015, 12:49:35 pmI decide to extend input power connector. In that way I can bring -9V from pre-regulator to DP and don't narrow a mosfet selection to the few "exotic" devices.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 17, 2015, 12:15:26 pm
content: The bias current of the MOSFET influences the regulator speed - possibly down to near 0. So there needs to be some bias current even if only in the sub mA range. The current plan may need even more, as at currents below about 1 mA R33 will bypass the MOSFET. At volatges above 5 V this might be just one of the dividers at the output - but this does not work all the way down to 0 voltage. So even the down-programmer running to GND might not be enough, below a few 10 mV.So I really see no good solution to avoid a bias current in the outputstage - though this could be small and in addition to the down-Programmer.I did some simulations with a simplified output stage (more like a classic audio amp. ). Like in the original version bias changes the speed, but at least for this version the lokal loop (no feedback through OPs) is stable over a wide range of currents (e.g. 1 mA .. >1 A), just with different speed. So It might work to run on a rather low bias. However I stilll have some kind of large signal instability - it can oscillate in a nonlinear mode, triggered by a large current step. The original circuit is likely even worse in this respect, as there are currents compensating and possibly reaching 0.The transistor part and a small output capacitor (e.g. 100 nF + 100nF/1Ohm) take care of the higher frequency part. Except that it is not compensating for the shunts, it allready is quite a powerful regulation. Below about 50-100 kHz it's limited by the shunts, the higher frequency part depends on the current, and can be below 1 Ohm even at higher frequencies.So the OPs only need to fix the lower frequency part, e.g. below about 5-50 kHz. Here no fancy extra timing adjustments are needed, just the one integrating capacitor can be enough. Having a little "gap" between the output stage and the OP part is actually positive as this ensures damping. So finding the right tunig of the system can be rather straigt forward: Adjust R23/C9 as to make the transistor part stable, even at low load and as little output caps (especially the one with damping) as possible. R23 ist likely not that critical so a value from simulation should work. The cap. in the OP part is rather simple: reduce until it oscillates, and than increase be a factor of something like 2 to 4.Using the OP all the way to higher frequencies gets tricky, as the output stage is current dependent in this range. Thus a low bias would require a rather slow regulation. Also tunig in real word could get tricky, as this is all one system, no simple separation in 2 subsystems.

author: prasimix
author_rank: Unknown
timestamp: August 21, 2015, 07:37:32 am
content: Hi Kleinstein and thanks again for spending time analyzing the circuit. Is it possible for you to post here some simulation results that shows impact of i.e. C15? I'm not able to replicate your findings (nor I'm so skilled to follow all your suggestions). Also I'll appreciate if you can post schematic/spice model with modifications that you think can improve performance of the existing solution. I'm ready to order a new PCB prototypes but I can wait a bit and make another revision if this make PSU even better.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 22, 2015, 09:59:00 pm
content: I did not get lucky with the output stage from above. There are 4 weak spots:1) Turning the mosfet on is faster than turning it off. The other way around is more helpful.2) It needs quite some negative supply - a PNP would save something like 2-3 volts3) the down pragrammer is only loosely coupled, and needs quite some bias currents - still no adjustment for the output bias.4) the MOSFET stage is rather slow at low currents - so some current is needed to keep a reasonable speedSo a did simulations with a slightly modified output stage, without the option to turn of the down programmer. It still is somewhat similar, but not that much. I still need a little more time. Currently only a simplyfied (no sense inptuts) voltage regulation is working. Still there is some nasty large signal oscillation after large steps.

author: prasimix
author_rank: Unknown
timestamp: August 23, 2015, 02:14:05 pm
content: As I understand with DP that is always active in parallel with Out enable (what is a case with the original Liv's circuit) and -9V that I bring from pre-regulator that mentioned weak points are solved in good enough manner. Or we shouldn't be satisfied with good enough and try to improve it further?Looking forward to see your model and simulations when you find a time to play a little with them.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 24, 2015, 10:04:59 am
content: Looking at the small signal (e.g. AC analysis) the circuit kind of works - though not very fast, good.The big problem is still have, is that there is this kind of large signal oscillation, when the output reaches saturation. This could turn out to be a real show stopper, though it mainly apears at large capacitive load (e.g. 1000 µF low ESR) and still rather moderate voltage amplitude. To me it looks more and more like a principle problem when having two nested loops, but no special anti-windup provisions.Having two DP parts in paralle active is not a problem, the output stages should still have there amount of bias. Of cause there still should be the option to turn of the output entirely. However the current circuit still has the divider as a kind of minimum load, allways connected - so even if the DP is turned off there will still be some slow discharging. The rather high impedance of that devider is one point that makes the output stage difficult.