Getting Started MAX V - VHDL support - Page 1
Forum section: electronics / general

author: CM800
author_rank: Frequent Contributor
timestamp: October 12, 2016, 10:28:29 am
content: Hi All,I could really do with some assistance, I have an Altera MAX V development board.I have installed the studio, but I am having some trouble getting movign with it, has anyone got a good guide they could suggest on how to get my first 'invert button' working. From there I can probibly move on using other tutorials online, but I'm having trouble understanding the file layout system and how to get moving.

author: rstofer
author_rank: Super Contributor
timestamp: October 12, 2016, 02:47:57 pm
content: There are a number of tutorials. I don't use Altera so I'm not up to date on how it works but I found a quick 'getting started' tutorial:https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/tt/tt_my_first_fpga.pdf

author: obiwanjacobi
author_rank: Super Contributor
timestamp: October 12, 2016, 03:55:46 pm
content: Quote from: CM800 on October 12, 2016, 10:28:29 amDo you mean Quartus?[not shure at what level you're stuck]You start by creating a new project. You can skip most steps (press next) but you have to make sure you select the correct device (exactly!).After the project has been created add a new file to the tree (you can select "Files" from de drop down list above the tree - by default its on "Hierarchy") and add a file with the exact same name as the project name. This is the top level file (root). The type of file you create depends on the language you prefer. You can use for instance Verilog, VHDL or Schematic and many others (I know nothing about).I have seen YouTube videos that demo this also. Perhaps on an older version of Quartus, but most of it will be usable in the latest version (it is not a part that changes must I think).Is that what you need?Hope it helps,Marc

author: CM800
author_rank: Frequent Contributor
timestamp: October 12, 2016, 09:33:05 pm
content: Thanks for those pointers.I have moved forward and managed to get an LED blinking, basic logic etc.however I'm a little stuck here:Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity VariableFrequencyTest isPort (CLK: in STD_LOGIC;LED_0: outSTD_LOGIC);end VariableFrequencyTest;architecture Behavioral of VariableFrequencyTest issignal pulse : std_logic := '0';signal count : std_logic_vector (23 downto 0) := X"0";begincounter: process(CLK)beginif CLK'event and CLK = '1' thenif count = X"16777216" thencount <= X"0";LED_0 <= pulse;pulse <= not pulse;elsecount <= count + 1;end if;end if;end process;end Behavioral;I get the following error:Code:Error (10327): VHDL error at VariableFrequencyTest.vhd(26): can't determine definition of operator ""+"" -- found 0 possible definitionscorresponding to this line:Code:count <= count + 1;

author: hamster_nz
author_rank: Super Contributor
timestamp: October 13, 2016, 12:58:15 am
content: Hi!You want to include the following library:use IEEE.NUMERIC_STD.ALL;You want to make the counter an "UNSIGNED" type:signal counter : unsigned(23 downto 0) := (others => '0');You might want o be using:if rising_edge(CLK) thenrather than:if CLK'event and CLK = '1' thenYou want to be sure that when you assign count to zero, you assign all the bits:counter <= (others => '0')orcounter <= to_unsigned(0,counter'length);orcounter <= x"000000";This looks wrong:if count = X"16777216" thencan a 24 bit value ever equal a 32 bit hex constant? This might be a more workable alternative, (which you can now do as 'count' is unsigned):if count = 999999 thenYou can also move the LED_0 <= pulse out of the process, and make it run concurrently if you like.Code:ibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity VariableFrequencyTest isPort ( CLK : in STD_LOGIC;LED_0 : out STD_LOGIC);end VariableFrequencyTest;architecture Behavioral of VariableFrequencyTest issignal pulse : std_logic := '0';signal count : unsigned(23 downto 0) := X"0";beginLED_0 <= pulse;counter: process(CLK)beginif rising_edge(clk) thenif count = 9999999 thencount <= (others => '0');pulse <= not pulse;elsecount <= count + 1;end if;end if;end process;end Behavioral;

author: CM800
author_rank: Frequent Contributor
timestamp: October 13, 2016, 11:06:26 am
content: Quote from: hamster_nz on October 13, 2016, 12:58:15 amThanks for your response, I've got to the point now where I'm able to progress quite well with learning VHDL... however I've fallen into another pit of confusion:Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity Tests isPort ( CLK : in STD_LOGIC;LED_0 : out STD_LOGIC;PULSE_OUT: out STD_LOGIC;SW_0 : in STD_LOGIC);end Tests;architecture Behavioral of Tests issignal pulse: std_logic:= '0';signal led: std_logic:= '0';signal count: unsigned(23 downto 0) := (others => '0');signal count2: unsigned(23 downto 0) := (others => '0');signal compareValue : unsigned(23 downto 0) := to_unsigned(500, 24);beginLED_0 <= led;PULSE_OUT <= pulse;counter: process(CLK)beginif rising_edge(clk) thenif count = compareValue thenpulse <= not pulse;count <= (others => '0');elsecount <= count + 1;end if;if SW_0 = '1' thencompareValue <= to_unsigned(500,24);elsecompareValue <= to_unsigned(250,24);end if;if count2 = 999999 thenled <= not led;count2 <= (others => '0');elsecount2 <= count2 + 1;end if;end if;end process;end Behavioral;I'm using SW_0 to half the time period / double the output frequency, but for some reason, (seemingly randomly or dependant on how long I wait until pressing or releasing)the frequency output just -stops- for about a second, then continues on. I have a suspecien it's something to do with the 1 second counter, however I changed it to 100ms and it's still about the same wait...What's going on?

author: hamster_nz
author_rank: Super Contributor
timestamp: October 13, 2016, 05:47:30 pm
content: Quote from: CM800 on October 13, 2016, 11:06:26 amWhat happens where "compareValue" changes from 500 to 250 (because of the button), when the count is 251?Why do you think I suggested using 999999 and not 1000000 as the max value for counter2? and does that mean anything for your choice of 250 and 500?Why did you use a 24 bit counter for things that will only go from 0 to 500? How many bits to you really need?

author: CM800
author_rank: Frequent Contributor
timestamp: October 13, 2016, 06:04:14 pm
content: Quote from: hamster_nz on October 13, 2016, 05:47:30 pmThe counter will eventually work on a value that is fed into it via shift registers.The application is a stepper motor driver, we want to be able to set any velocity, 10RPM, 1000RPM, 43.5RPM and have the frequency output drive our stepper motor at the specified RPM.I am having a few problems in the design nature due to the nature of how a counter works, I only get a finite resolution, and it get's dramatically worse as I get closer to the input frequency.I will be trading up to a 60MHz input clock (mostly because I dropped a motor on the board and it broke the 10MHz Oscillator.)What's the best way of generating a variable frequency.The final product will be able to do Velocity and Position with encoder feedback / auto-correction. I will likely end up using a micro controller next to the CPLD.A stepper motor typically has 200 steps per rev, which can be divided upto 51200uSteps per rev (51200 ppr)The encoder feedback would likely have around 512 to 4069 ppr.Judging from that application, what could you recommend?I'm still trying to work out the best control system for this.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 13, 2016, 07:51:44 pm
content: With any digital system you get finite resolution, it is just a question of how finite do you need it to be?My generic solution would be...- Have a 'n' bit counter (i.e. with bits from n-1 down to 0)- Connect counter(n-1) to one input on stepper driver.- Connect counter(n-1) XOR counter(n-2)) to the other input on the driver.- That will generate either "00,01,11,10..." or "00,10,11,01..." depending on if the counter is counting up or down, with one step every 2^(n-1) cycles when you are counting.Once that is tested, make the counter longer, and rather than counting by one, add or subtract a pre-calculated constant that are calculated as 2^(n-1)/desired_clock_cycles_per_step-1. You can then increase the counter to get whatever resolution you want, just as long as you increase the length of your constants and counters.The user interface (e.g. switches) then just needs to select between these constants, and you avoid a lot of ugliness which can occur (runt pulses, lack of 50% duty cycle and so on).

author: CM800
author_rank: Frequent Contributor
timestamp: October 13, 2016, 08:34:25 pm
content: Quote from: hamster_nz on October 13, 2016, 07:51:44 pmReading through your suggestion I'm a little confused as to what you mean and how it's supposed to work in terms of giving me the desired result.Take for example one product on the market, it allows you to send RS485 commands to it, telling it to 'slew at 153233 pulses per second', it does exactly that.A higher end product on the market, for example:https://www.acsmotioncontrol.com/pdiclThe specifications for their drive feedback and output are as follows:QuoteI'm curious how they manage this and what kind of systems they have in place, I'd like to do something similar, however to a lower frequency / more cost effective (say, 16MHz encoder input max, RS-422 quadrature only and 2MHz stepping output)I believe I can figure out the motion control side of it (telling the CPLD what frequencies to go at etc.) with a seperate ARM controller.The other point is I want to be able to do acceleration, possibly even JERK control in the future (Rate of change of frequency and Rate-of-Rate-of change of frequency)Even if it's out of my reach with what I have here, I really want to figure out how they are doing this and if a scaled down solution is available. The workings have me stumped.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 13, 2016, 09:22:36 pm
content: Your problem seems to be the more general "You can't implement what you have yet to design", and as CPLDs are working at a low level, it is much harder to design on the fly.Once designed, a VHDL solution can get control of the count, duty and phase of pulses down to the designs clock rate.What you really need to define is how you want your design to work:- what your user interface looks like (switches, serial, I2C, whatever, and the protocol)- what your motor interface looks like (e.g. microstepping, full stepping, half stepping, duty cycles, max/minimum pules rates, resolution, ramp up/ ramp down rates)- how you map the input into your desired output.- what you will do when things go wrong (e.g. watchdogs, protocol data errors)If you can't define that, then you won't be able to implement a solution that gives you what you want, because you don't know what you really want.It might be an iterative process, in that you might find that by changing your user interface slightly you can make implementation much easier.

author: CM800
author_rank: Frequent Contributor
timestamp: October 13, 2016, 09:57:14 pm
content: Quote from: hamster_nz on October 13, 2016, 09:22:36 pmI'm basing this on existing products in the market, I'm doing this for my Final year HNC project.My current plan is to have the motion tightly controlled in the CPLD or possibly FPGA and then have the motion controller in an ARM processor (or even end up using an Arduino as the programmable block with a custom IDE and library)

author: hamster_nz
author_rank: Super Contributor
timestamp: October 13, 2016, 11:56:56 pm
content: I think you are missing something... This thread was about getting started on MAX V. I do have the time to help you with relatively simple VHDL issues, but I really don't have the spare time to research your application, evaluate various options and produce a design for you that is equal to commercially available products with full R&D cycles behind them.Earlier on in the thread I asked you three (hopefully) insightful questions, that would help you understand things about working in VHDL that may help you avoid mistakes that were present in your code:QuoteOne of these is directly responsible for the undesired behavior in your design - and if you can't put the work/thinking/leaning into getting a simple design correct, you will not progress well with your complex designs.

author: rstofer
author_rank: Super Contributor
timestamp: October 14, 2016, 12:32:50 am
content: You also need to read up on DDS (Direct Digital Synthesis). You won't be adding 1 to an counter, you will be adding some larger value to a phase accumulator and the overflow of the accumulator will be driving the step logic. Add a big value and it overflows sooner. Add a small value and it takes longer.Google has a lot of refernces for 'fpga dds frequency generator' or something similar. 'Phase accumulator' is another good search.http://fpga4fun.com/DDS1.htmlETA: Here's another page at fpga4fun:http://fpga4fun.com/CNC.html

author: CM800
author_rank: Frequent Contributor
timestamp: October 14, 2016, 07:00:49 am
content: Quote from: hamster_nz on October 13, 2016, 11:56:56 pmSorry for the misunderstanding, I didn't mean it to come across like that, I wasn't asking you to research my application, quite the opposite, it's my project, I want to develop it and say 'I did this myself' not 'I had 10 people write code for me, I hit the compile button' I was more hoping someone might have a clue in how such things are often implemented, what kind of mechanism is being used, if you or someone else here had came across such digital mechanisms before. Right now I'm trying to look inside a black box and get an understanding of it.Thanks for your pointers with what's going on, that does sound likely. My replacement oscillator crystals will arrived today so I hope to fix it and solve that issue.With regards to the actual questions, I'll show I'm not a complete idiot, they brought out some interesting points that slipped my mind.QuoteQuote from: rstofer on October 14, 2016, 12:32:50 amOkay! This is the kind of thing that I was looking for, Thanks for sharing this with me, I'm going to try experiment with it today. Should prove interesting...