Generic Clock sam d - Page 1
Forum section: electronics / general

author: losst
author_rank: Contributor
timestamp: September 19, 2016, 04:13:12 pm
content: Hello everybody,I like to have some clarification concerning the clocks used on series microcontrollers SAMD D from Atmel .I'd like to know why there is as many clock and how are they configured it there huge differences between Generic clock generator 0, 1, 2?I will also need to know if during the configuration modules in a project, use the same type of clock?Faced with all these clocks, I am lostThank you

author: ataradov
author_rank: Super Contributor
timestamp: September 19, 2016, 04:49:12 pm
content: Quote from: losst on September 19, 2016, 04:13:12 pmWhat are the differences? The only difference that I know of is number of bits in the prescaler. And that's probably to save on hardware while still providing enough flexibility.There are different clock sources (Xtals, RC oscillators, PLLs, etc), those will be present on any MCU. SAM D adds flexibility of being able to route any of those clock sources to one of clock generators (possibly prescaling it). And peripherals attach to clock generators.Quote from: losst on September 19, 2016, 04:13:12 pmYou can use the same clock, if this works for your project. A lot of project require more flexible configuration and SAM D lets you do that.

author: losst
author_rank: Contributor
timestamp: September 19, 2016, 04:59:58 pm
content: If I have a XOSC32 oscillator on PA08 and PA09 pines , then it is possible for me to use it for all my modules?So I can use it to initialize the system and replace the generic clocks as in this initialization using XOSC32K ?For example in :Code:GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(RTC_GCLK_ID) |GCLK_CLKCTRL_CLKEN |GCLK_CLKCTRL_GEN_GCLK0; <==HEREBut do I keep them clean clocks to each module such RTC_GCLK_ID?But on the Atmel Studio software is it possible to get the frequency value and the period of the clocks in one place?

author: ataradov
author_rank: Super Contributor
timestamp: September 19, 2016, 05:08:06 pm
content: Quote from: losst on September 19, 2016, 04:59:58 pmIt is possible, but you really should not do this. You will slow down your whole system to 32 kHz. That's like 100x slower than first processorsQuote from: losst on September 19, 2016, 04:59:58 pmI don't understand what do you mean here.It goes like this. Each and all peripherals can use any of the GCLK generators. So total number of frequencies used in the system is limited to number of GCLKs. But the most complex system I've seen used only 3, so you have plenty.Each GCLK can have one of many clock sources as an input.A system configuration may look like this, for example:1. Internal RC [8 Mhz] -> GCLK -> all peripherals that need to run fast.2. Xosc32 -> GCLK -> RTC for accurate time-keeping.3. Internal RC [8 Mhz] / divided by 3 -> GCLK -> some weird peripheral that needs 2.666 MHz clock.

author: losst
author_rank: Contributor
timestamp: September 19, 2016, 05:27:16 pm
content: The RTC for accurate time-keeping must use GCLK.But to use this clock I need to configure the XOSC32K before because when I change the configuration GCLKby GCLK  the RTC module doesn't work

author: ataradov
author_rank: Super Contributor
timestamp: September 19, 2016, 05:31:22 pm
content: Quote from: losst on September 19, 2016, 05:27:16 pmWhy do you think so? RTC is just a weird counter designed around human understanding of time, it can be clocked from any clock you like. It will give you accurate time if you clock it from 32kHz.Here is a quote from the datasheet:QuoteQuote from: losst on September 19, 2016, 05:27:16 pmYes, you always need to make sure that clock is there before you try to use it. This is kind of logical, all other MCU do it exact same way.Quote from: losst on September 19, 2016, 05:27:16 pmI don't understand this.

author: losst
author_rank: Contributor
timestamp: September 19, 2016, 05:41:02 pm
content: Yes, but in my case the clock isn't there so for me it's not possible to use the GCLK and I fear that this is the GCLK clock (0) is the source of a strange phenomenon in the program. This is why, I would like to know how to configure a clock GCLK (1) because I have always use the GCLK (0)

author: ataradov
author_rank: Super Contributor
timestamp: September 19, 2016, 05:42:37 pm
content: You are mixing things up. If clock is not there, then enable it and make sure it is there.

author: ataradov
author_rank: Super Contributor
timestamp: September 19, 2016, 05:47:02 pm
content: Also, for testing just use ULP32K. It is always there and always enabled.I don't know what board you are using, but D10 Xplained Mini does not have 32 kHz crystal.

author: losst
author_rank: Contributor
timestamp: September 19, 2016, 05:56:01 pm
content: Well I explain my problem:I initialized the system clock using the function:Code:void sys_init(void){SYSCTRL->OSC8M.bit.PRESC = 0;// Enable interruptsasm volatile ("cpsie i");}This means that the clock of 8 MHz.Then in the PSTN module I use GCLKtherefore 8 MHz and a divider 256 therefore the frequency is about 32kHz and with RTC-> MODE0.COMPreg = 1000; every second I make an interruption with RTC-> = MODE0.INTENSET.reg RTC_MODE0_INTENSET_CMP0;:Code:void init_RTCvoid){GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN(1) |GCLK_CLKCTRL_CLKEN |GCLK_CLKCTRL_ID(RTC_GCLK_ID);RTC->MODE0.CTRL.reg = RTC_MODE0_CTRL_SWRST;while (RTC->MODE0.CTRL.bit.SWRST);while(RTC->MODE0.STATUS.bit.SYNCBUSY);RTC->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE_COUNT32;while(RTC->MODE0.STATUS.bit.SYNCBUSY);RTC->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR |RTC_MODE0_CTRL_PRESCALER_DIV256;while(RTC->MODE0.STATUS.bit.SYNCBUSY);RTC->MODE0.COMP.reg =1000;//1 swhile(RTC->MODE0.STATUS.bit.SYNCBUSY);RTC->MODE0.READREQ.reg |= RTC_READREQ_RCONT;while(RTC->MODE0.STATUS.bit.SYNCBUSY);RTC->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE;RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;NVIC_EnableIRQ(RTC_IRQn);}So far my focntions look right?

author: ataradov
author_rank: Super Contributor
timestamp: September 19, 2016, 06:01:24 pm
content: Quote from: losst on September 19, 2016, 05:56:01 pmNo, they do not. You have never initialized GCLK, so you can't use GCLK_CLKCTRL_GEN(1). Replace it with GCLK_CLKCTRL_GEN(0).In this case you are not setting prescaler value in the GCLK, but in the peripheral itself. Your peripheral still must be clocked from 8 MHz.

author: losst
author_rank: Contributor
timestamp: September 19, 2016, 06:11:42 pm
content: I must use this:Code:GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN(0) |GCLK_CLKCTRL_CLKEN |GCLK_CLKCTRL_ID(RTC_GCLK_ID);GCLK->GENDIV.reg = GCLK_GENDIV_DIV(7);// the clock source divided by 2^(GenDIV.DIV+1)GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0) |GCLK_GENCTRL_DIVSEL;What is the interest ofCode:RTC_MODE0_CTRL_PRESCALER_DIV256;?

author: ataradov
author_rank: Super Contributor
timestamp: September 19, 2016, 06:17:13 pm
content: Quote from: losst on September 19, 2016, 06:11:42 pmYou can't use 0 in this case, because 0 is attached to 8 MHz source. If you want to do prescaling with GCLK, then you need to pick another GCLK.Quote from: losst on September 19, 2016, 06:11:42 pmHere you also need to specify the GCLK ID, which you want to divide.Quote from: losst on September 19, 2016, 06:11:42 pmAgain, you can't use 0 here. You also need to enable it (GCLK_GENCTRL_GENEN).Quote from: losst on September 19, 2016, 06:11:42 pmThat is additional divider, giving you more flexibility. If the range of this divider is enough to get the required resulting frequency, then just use this.Just change GCLK_CLKCTRL_GEN(1) to GCLK_CLKCTRL_GEN(0) in your original code.

author: losst
author_rank: Contributor
timestamp: September 19, 2016, 06:25:08 pm
content: I use this function but it's not correct I don't have the clock:Code:void Initialization_RTC(void){GCLK->CTRL.reg = GCLK_CTRL_SWRST;while (RTC->MODE0.CTRL.bit.SWRST);while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN(1) |GCLK_CLKCTRL_CLKEN |GCLK_CLKCTRL_ID(RTC_GCLK_ID);GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(8) |GCLK_GENDIV_ID(1));GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |GCLK_GENCTRL_ID(1)|GCLK_GENCTRL_DIVSEL);while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}RTC->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE_COUNT32;while(RTC->MODE0.STATUS.bit.SYNCBUSY);RTC->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR |RTC_MODE0_CTRL_PRESCALER_DIV256;while(RTC->MODE0.STATUS.bit.SYNCBUSY);RTC->MODE0.COMP.reg =1000;while(RTC->MODE0.STATUS.bit.SYNCBUSY);RTC->MODE0.READREQ.reg |= RTC_READREQ_RCONT;while(RTC->MODE0.STATUS.bit.SYNCBUSY);RTC->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE;RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;NVIC_EnableIRQ(RTC_IRQn);}Now I do not know what is the frequency of the clock source

author: ataradov
author_rank: Super Contributor
timestamp: September 19, 2016, 08:26:03 pm
content: Quote from: losst on September 19, 2016, 06:25:08 pmYou are attaching a peripheral to a clock source and after that you are configuring that clock source.And even reset of the peripheral should happen after you configured all the clocks.Also, now you have both dividers enabled, so your final clock will be 8 MHz / (256 * 256).Also, how do you know that your clock is not correct? I have not checked that RTC code, I really don't know if it works. Start with my TC code that is known to be correct, and experiment with its clocking.Why do you want that RTC in a first place? It is a special and weird timer, for time keeping. Just use a normal TC.

author: losst
author_rank: Contributor
timestamp: September 19, 2016, 08:32:13 pm
content: Sorry but I do not understand where I realize that:QuoteandQuote

author: ataradov
author_rank: Super Contributor
timestamp: September 19, 2016, 08:43:08 pm
content: Quote from: losst on September 19, 2016, 08:32:13 pmGCLK_GENDIV_DIV(and RTC_MODE0_CTRL_PRESCALER_DIV256.Quote from: losst on September 19, 2016, 08:32:13 pmGCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN(1) | GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_ID(RTC_GCLK_ID);And again, start any experiments with clocks from a known functioning peripheral (normal TC in my example). This way you know that if you have a problem, then it is with clock source, not with your peripheral code.