SPI over 1.5m distance - Page 1
Forum section: electronics / projects

author: ricko_uk
author_rank: Super Contributor
timestamp: October 08, 2024, 12:20:07 am
content: Hi,what are some reliable solutions to interface between multiple micros and devices over SPI over a distance of 1.5 meters?Initially I thought of differential but that would not work with multiple devices on the bus because it would create bus contention.There is an interesting LT part that is differential and has multiple CS but it costs £ 6 (for quantities) and in this system 12 are needed, so it would cost £ 70 per system which is not realistic.Any suggestions or clever solutions?Thank you

author: Nominal Animal
author_rank: Super Contributor
timestamp: October 08, 2024, 12:38:19 am
content: Dual or triple optical Toslink, with idle low; one cable for clock, plus one per data direction. Price really depends on whether you can find the cables and transceivers for cheap. You may want to do 8b/10b, depending on the transmitters used; some don't like to be 100% on.Tongue in cheek answers aside: What's your expected/required SPI clock frequency range? Can you use a pre-set, fixed SCK frequency?

author: ricko_uk
author_rank: Super Contributor
timestamp: October 08, 2024, 01:53:47 am
content: The clock as high as reasonable. The compromise is finding a balance between high enough to be acceptable to transfer maybe 20 MB of data (just from time to time) without annoying the user and low enough to work reliably over that 1.5m distance (possibly even 2m). The first constraint is much less critical then the second. So speed can be decreased but reliability and distance cannot be compromised.Yes I can fix the clock but why does that matter?What ideas/suggestions are you thinking about?Thank you

author: Smokey
author_rank: Super Contributor
timestamp: October 08, 2024, 02:07:08 am
content: I've done single master / single slave SPI over cabled LVDS that was longer than 1.5m. Should also work over something higher voltage like RS422. With multiple devices on the bus that would get interesting through. Maybe you could have the SS also enable the transceiver or something?Unless you have a multi-master spi bus (is that a thing?) I'm not sure where the contentions would come from.

author: ricko_uk
author_rank: Super Contributor
timestamp: October 08, 2024, 02:37:37 am
content: Thank you Smokey.The bus contention would come from the multiple slaves output (MISO) signals driving the same line (that goes to the master).

author: Smokey
author_rank: Super Contributor
timestamp: October 08, 2024, 04:42:07 am
content: The SS enable thing might work then. Does rs485 not handle multi-node bus trasmissions in the transceiver?

author: Nominal Animal
author_rank: Super Contributor
timestamp: October 08, 2024, 05:23:48 am
content: Quote from: ricko_uk on October 08, 2024, 01:53:47 amWeird things, as usual. Like using cheap MCUs to convert between SPI and Ethernet transport. Low BOM cost but high software development cost, really.TI DP83825I10/100MII/RMIItransceivers cost 0.20€ apiece at LCSC. The MII/RMII interface fixes the clock (to 25MHz or 50MHz).Instead ofNslave selects, you could use ⌈log2(N+1)⌉, and have them encode the currently selected slave in binary.Three lines for up to 7 slaves, four lines for up to 15 slaves, five lines for up to 31 slaves, and six lines for up to 63 slaves.If you use open collector bus for the slave selects, you can easily make it a multi-master instead, although you do need a bit of logic at the selection: only assert when bus is free, and detect when the bus state matches the node number (even when pulled down by self).

author: moffy
author_rank: Super Contributor
timestamp: October 08, 2024, 06:01:47 am
content: If you have individual CS for the slaves, then that can be used to enable/disable a tristate buffer.

author: Smokey
author_rank: Super Contributor
timestamp: October 08, 2024, 07:57:26 am
content: Quote from: moffy on October 08, 2024, 06:01:47 amthat's a great idea

author: langwadt
author_rank: Super Contributor
timestamp: October 08, 2024, 08:03:57 am
content: why SPI?

author: bookaboo
author_rank: Frequent Contributor
timestamp: October 08, 2024, 10:20:42 am
content: Perhaps a small micro with SPI and Canbus on each node? Then its just a 4-wire solution.Or an RF enabled micro on each node, do the comms over RF, just bring power to each node.

author: Smokey
author_rank: Super Contributor
timestamp: October 08, 2024, 10:23:36 am
content: Quote from: bookaboo on October 08, 2024, 10:20:42 amCANBUS transceivers have an ack bit after transmissions. That would probably mess up SPI unless you were really careful.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: October 08, 2024, 10:45:17 am
content: UART over RS485, small MCU at each node to convert and handle addressing.

author: Jon_S
author_rank: Contributor
timestamp: October 08, 2024, 11:22:21 am
content: Quote from: ricko_uk on October 08, 2024, 12:20:07 amWe actually tried pretty much this length at 1MHz with bussed traces, with the result that the clock got into the MISO and buggered things up. A small bodge cap at the far end 'fixed' that, but we binned the idea and replaced it with CAN as cost wasn't a limitation for that application (and the processors had CAN engines anyway).Otherwise I'd vote for mikeselectricstuff's suggestion of UART over RS485/422 as a robust solution.

author: David Hess
author_rank: Super Contributor
timestamp: October 08, 2024, 12:17:06 pm
content: Quote from: moffy on October 08, 2024, 06:01:47 amExactly, for mulitiple slaves sharing an SPI bus, a CS (chip select) signal going to each slave enables its output. Unfortunately this means adding another signal for each slave to control CS.An alternative is to multiplex the SPI signals at the master and run a separate set of SPI signals to each slave.

author: Nominal Animal
author_rank: Super Contributor
timestamp: October 08, 2024, 02:13:45 pm
content: How about using 4 lines for node select for up to 14 nodes? With its own timing restrictions, not clocked to the clock line?A 74HC85 can compare the four lines to a hardcoded or dip-switched number, and a 74HC154 can expand it directly to 16 parallel active low slave selects. Zero is reserved for "none", and node 15 the master.Using open collector logic for the four node select lines, each node asserts its own number to send a message on the bus. It will detect a collision by comparing the actual state of the node select lines to its own number: if 74HC85 A inputs are the actual line states and B inputs encode current node, then QA<Boutput of the 74HC85 tells if this node needs to back off. That way higher node numbers get higher priority, with node 15 always winning all races.Use the first 16 data bits on the bus to encode the recipient map (one bit per node), and each node can send messages to any subset of nodes. Only needs one clock line, one data line, and 4 much lower frequency node select lines.If the winning node also generates the clock line, then you have a multi-master half-duplex bus, I believe.

author: David Hess
author_rank: Super Contributor
timestamp: October 08, 2024, 05:45:20 pm
content: There are all kinds of ways to do it. Small microcontrollers are so cheap now that I would consider using asynchronous serial on the bus, maybe even CAN or microwire, and having a cheap microcontroller at each node to handle addressing and convert to SPI. The idea here is that now no chip select signals are needed, and no clock signal either.

author: Nominal Animal
author_rank: Super Contributor
timestamp: October 08, 2024, 07:24:01 pm
content: Very true.In fact, I'm waiting on some WCH MCUs right now to do some experiments:CH32X033(QingKe RISC-V4C running at 48 MHz in TSSOP20 with 20k RAM and 64k Flash for about 0.34€ apiece), mostly because the built-in two-pin PIOC; might be interesting to do PDM experiments at some point. I'm also looking at someCH32V203(QingKe RISC-V4B running at up to 144 MHz) for USB-SBC interfacing, especially CH32V203F8P6 (TSSOP20, 20k RAM, 64k Flash, 0.36€ apiece in lots of 72 or more at LCSC) and CH32V203C8T6 (LQFP48, 0.44€ apiece in lots of 100 or more at LCSC, one USB device + one device/host). At this point, for a hobbyist like myself, the WCH RISC-V MCUs are as cheap as their E8051 ones are, but much more capable.I mention this because those CH32X033/CH32X035 and CH32V203 RISC-V MCUs have hardware SPI slave support, which I believe (but have not verified) should work at up to quarter/half the frequency of the main clock (so 12 MHz/72 MHz, respectively). They can also output their system clock on a dedicated pin (MCO). It might be possible to use the PIOC RISC8b processor on the CH32X03x for 8b10b encoding or decoding, for example. If interested, seeWCH's openwch github, ch32x035 repo.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 08, 2024, 10:48:42 pm
content: Quote from: Jon_S on October 08, 2024, 11:22:21 amI second that, if you want something robust and that will work at a few Mbits/s, I would recommend CAN FD. Up to 8 Mb/s IIRC, robust, easily available (many MCUs now support CAN FD), cheap. If max 1Mb/s is OK, standard CAN will work too and will be even cheaper.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: October 08, 2024, 11:38:09 pm
content: What about using quad SPI and make it resemble GPIB and using HDMI cables for the differential bits?As you are dealing out all the cards yourself it should not be too difficult to put those things together into something affordable, speedy and reliable.I am not sure at what point things like clock de-skewing becomes an issue. And instead of all the slave selects, maybe you can pass around a token on the bus, i.e. poll the devices in some sort of sequence.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 09, 2024, 12:08:33 am
content: 1.5m isn't very long. If you can afford a shielded cable, do that. Tie shield tightly to circuit ground plane at both ends, as you are extending the reference plane into the cable and the signals are referenced to that. A generic multiconductor cable will also have some reference between lines, which can create interference like so,Quote from: Jon_S on October 08, 2024, 11:22:21 amThe problem is that, for risetime on par with electrical length, the coupling between lines becomes significant (say, > -10dB). Bused traces over ground plane shouldn't be a problem, but it does depend on the relative spacing and height above plane; likewise the multiconductor cable, how the wires are arranged within it: consider a 7-core cable where the center wire is surrounded by six others, it has no ground reference except by the 1/6th electric field per surrounding conductor, making crosstalk inevitable. Maybe 1/7th is still within margin, but be careful that multiple signals aren't transitioning at the same time, coupling a bigger total bump into the neighboring wire.If you can afford filtering to reduce signal bandwidth below the cable's resonances/cutoffs, that greatly improves crosstalk -- at low frequencies, crosstalk manifests as mutual capacitance between lines, and you can just drive them strong enough and filter it down enough that remaining crosstalk doesn't exceed the valid logic threshold level (for typical CMOS pins, about 30% -- on par with the -10dB figure I gave above). This is very likely satisfactory, for max 1.5m length, below say, 10Mbps or so, maybe even up to 20.Or, if you can choose twisted-pair cable, shield is still needed, but crosstalk can be improved by grounding every other wire -- so each signal is twisted with GND. This, at worst merely halves the crosstalk (in the middle of a long cable, the twisted pair looks differential again, CM coupling with neighbors occurs; then CM-DM mode conversion happens when one of the pair is grounded at the other end), but for a short cable, or with CMCs at either end to pseudo-differential drive the pairs (sort of, using the CMCs to pre-crosstalk the signals, so they come out the right way at the final end), crosstalk can be much less.For long cables, shielded or not, I would just as well suggest RS-422 or 485.For unshielded cables, choose twisted pair, and use differential even for short lengths or low bitrate. Filtering may still be necessary; and note that ground wires must be provided, as RS-422/485 isn't isolated, it has a finite working input voltage (CM) range.SPI can trivially be sent over RS-422 with transmitter/receiver pairs.Unshielded, non-twisted cable can be used only at very low bitrates -- say, under 1Mbps; filtering is required at both ends, and perhaps a schmitt trigger to recover sharp clock edges. UART may be preferable to SPI.If you don't mind the increased complexity (packet framing / bus state / sequencing, escaping/coding, timeouts, etc.), UART over RS-422 (unidirectional per pair) or 485 (bidirectional; of course, you have to solve bus arbitration as well) is promising.Also, may be of interest: 485 can be used to save power, even if it's used unidirectionally.Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: October 09, 2024, 08:45:32 am
content: One problem with a digital signal over a long distance is signal reflections and thus ringing, especially with the clock signal. It depends on the devices how sensitive they are. Some µCs can be quite tolerant and simple shift registers are easily fooled by ringing.One way would be some at least approximate impedance matching with the clock line. Depending on the configuration also clock buffers further down may be an idea, depending on the configuration.Another option could be BW limiting of the clock signal and where needed schmidt triggers at the devices.This can get tricky with multiple masters.

author: ricko_uk
author_rank: Super Contributor
timestamp: October 09, 2024, 02:02:56 pm
content: Thank you all for all those good ideas and suggestions, much appreciated!!I am now looking into pros and cons (board space, conenctor/cable impliactions, cost, complexity etc.) of several of them.CAN bus might be an option, I am checking now with the client to see if it is acceptable.I never used CANbus and when I looked into it almost 20 years ago it was not that easy to work with, especially during debug. Things might be much better nowadays.Quote from: T3sl4co1l on October 09, 2024, 12:08:33 amHow do you find a cable's resonant/cutoff, just by checking signal integrity with an oscilloscope, or some other way?And what kind of filtering / order?Thank you

author: varjag
author_rank: Contributor
timestamp: October 09, 2024, 02:54:38 pm
content: Did you consider use of extenders?https://no.mouser.com/new/analog-devices/adi-ltc4332-extenders/Tho I agree with T3sl4co1l, at 1.5m it may well work just fine at a reasonable clock.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 09, 2024, 10:46:41 pm
content: Quote from: ricko_uk on October 09, 2024, 02:02:56 pm1. A terminated cable has no resonance, it's matched at all frequencies.With CMOS drivers, this can be achieved with a source termination resistor; a typical output pin is 30-70 ohms internal resistance, so a typical 70-100 ohm trace (or wire in a ribbon cable, every other wire GND) needs 33 ohms in series, give or take. More can be used to reduce risetime further, approximating the cable as a shunt capacitance and thus an RC filter is had.For the shielded multiconductor cable case, Zo may be lower (a given wire surrounded by many wires, and/or shield -- approximately a coaxial construction), and perhaps a bus driver (stronger output) is desirable, or even a proper transceiver setup (source (series) termination + load (shunt) termination + precision threshold receiver IC -- for example, analog comparator or perhaps LVDS receiver, vs. a set threshold; 74HC7014 precision schmitt buffer; etc.).For reasonably well isolated signals (like alternating signal-GND in a ribbon cable, modestly spaced microstrip over GND plane on PCB, or individual coax), with termination, operation is limited only by the effect of propagation delay on the protocol (e.g., MISO might be delayed by a whole clock time) and the attenuation rate of the medium.2. A poorly terminated cable, or the bandpass coupling due to crosstalk, or the potential for emissions on a poorly or unshielded cable, may find filtering desirable. The electrical length of the cable is its length divided by its velocity factor (including the speed of light), t = l / (c c_0). Typical cable is 60-85% c_0 so 1.5m is 6-8ns. Note that a full reflection travels the length and back, or 12-17ns. The corresponding frequency is this half-wave period, or 30-43MHz, and harmonics thereof.For good square pulses, we want to operate less than, say, 1/5th the cutoff frequency, so under 10Mbps will be fine; pushing towards 1/3 might also still be fine, which is as I said before, a bit more may even be acceptable.The nature of that filtering, can take on many forms:A simple (single pole) RC filter provides gentle attenuation vs. frequency, so we might prefer it to cut off much lower, to get adequate attenuation near resonance, but that limits baud rate even further.An LC filter can have sharper response, making cutoff just below cable resonance feasible, and a Bessel characteristic can be chosen to maximize pulse clarity.An RLC filter is probably best, so that damping resistance is available to absorb resonances on the cable, as well as soften the cutoff characteristic. A series ferrite bead is a typical choice here, and then some 100s pF shunt. The ferrite bead may be before, after, or both, the capacitor -- note that FB between cap and cable provides resistance necessary to terminate/dampen its resonance.We might also choose a series L, then shunt (C || (R + C2)) circuit: we have C2 > C, so that R is dominant in the transition band, terminating the filter even if the source is high or low impedance, or the load is high impedance.The shunt capacitor is also a good place to put a clamp diode/TVS, for ESD purposes.Tim

author: ricko_uk
author_rank: Super Contributor
timestamp: October 10, 2024, 12:01:28 am
content: Thank you Tim for both details explanations, much appreciated!@varjag, yes I did as mentioned in the O.P. That was the whole point of posting here asking for other suggestions. They are very expensive for that project.

author: varjag
author_rank: Contributor
timestamp: October 10, 2024, 05:14:04 pm
content: Oh my apologies: it's ridiculous that I somehow missed this.

author: David Hess
author_rank: Super Contributor
timestamp: October 12, 2024, 10:15:50 am
content: I have just a couple comments:1. When used point-to-point, the transmission line does *not* have to be terminated at both ends to prevent reflections. Driving one end with a voltage *or* current with the other end parallel terminated produces a clean full level transition at any point.2. Source termination halves the output level which would be a problem if logic levels have to be preserved. The implication is that if no source termination is used with a logic level driver, logic levels will be preserved and a normal gate can be used as a receiver.3, In a bus application, both ends of the transmission line must be terminated, however current or voltage drive at any point along the transmission line can be used without series termination. The driver sees two parallel transmission lines so drive impedance is halved.A couple years ago I had a remote GPS timing receiver that used RS-232 levels and I needed a level shifter for the long cable. I did not have any suitable ICs handy, so I designed and built a discrete level shifter using 2N3904 and 2N3906 current mirrors to drive the output which would saturate at their compliance voltage producing the proper levels. The constant current driving the cable capacitance produced an incredibly clean ramp waveform despite the lack of any cable termination. With the current chosen and the cable capacitance, transitions were about 50 nanoseconds, but I could have increased the current to make it faster.My point here is that there are slightly more complex discrete solutions for the drivers which simply the transmission line and termination requirements.

author: ricko_uk
author_rank: Super Contributor
timestamp: October 12, 2024, 03:06:12 pm
content: Thank you David

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 12, 2024, 04:48:24 pm
content: LVDS driver over UTP cable definitely seems a good idea. Cheap and common, can use a simple ethernet cable found anywhere.TI made some testing here:https://www.ti.com/lit/an/slla053b/slla053b.pdf

author: Siwastaja
author_rank: Super Contributor
timestamp: October 12, 2024, 05:42:01 pm
content: First try something like ribbon cable with groun - signal - ground - signal - ground pinout and 47R series termination resistors (resistors at driving pins, which on SPI is easy since every signal is unidirectional; MISO resistor is at slave, other resistors at master). Maybe that gives good enough signal integrity with bog standard single-ended signalling. That is how computer systems were built for decades, think about IDE and other clocked parallel buses. 1.5m is of course longer than typical IDE cable but not like different order of magnitude.

author: uer166
author_rank: Super Contributor
timestamp: October 12, 2024, 07:01:54 pm
content: Quote from: David Hess on October 12, 2024, 10:15:50 amIs this really true though? It halves the output level *at the transmitter*, but that voltage is doubled when it hits a high-impedance receiver, at the end of the transmission line so you do get 100% of it back where it matters. If the receiver is also terminated, then it will get 50% of the swing.

author: Smokey
author_rank: Super Contributor
timestamp: October 12, 2024, 10:09:54 pm
content: Quote from: DavidAlfa on October 12, 2024, 04:48:24 pmThis sounds like a great idea!

author: David Hess
author_rank: Super Contributor
timestamp: October 13, 2024, 12:43:38 am
content: Quote from: uer166 on October 12, 2024, 07:01:54 pmYou are correct, but let me explain.If the transmission line is open, then the series termination at the source divides with the transmission line impedance to make a half level incident wave, which doubles restoring the original value once it reflects off of the open end of the transmission line. If the transmission line has a parallel termination on the end, then there is no reflection and the level remains at half.The problem with the first case is that the signal level at the receiver starts out at half, and then doubles to full once the reflection gets back, which makes detecting the level tricky unless the receiver is only at the end. The trouble with the second case is that the signal level is halved so likely will not work with logic level receivers.In a party line application with a bus where multiple receivers are present, series termination is not used. Standards like LVDS, RS-485, 10Base-2, and GTL (Gunning transceiver logic) work this way.My weirdo compliance limited current output RS-232 driver that I described worked this way also, but managed without termination at all. I never followed up in detail, but I suspect saturation of the current mirror output presented the proper series termination impedance once the output reached full voltage. There are some tricky terminations which use the non-linear impedance of a diode this way.

author: coppercone2
author_rank: Super Contributor
timestamp: October 13, 2024, 12:45:12 am
content: SPI over 1.5 mile distance.Is it possible?

author: David Hess
author_rank: Super Contributor
timestamp: October 13, 2024, 02:29:40 am
content: Quote from: coppercone2 on October 13, 2024, 12:45:12 amEven with a physical interface that can work at that distance, it would be awfully slow, like 50 kHz, because the clock has to wait for propitiation of the data. It could be pipelined, but then it is not really SPI.RS-485 can do 100 kb/s at 4000 feet, so sure, 1.5 miles is possible for SPI using the right drivers and receivers. It would not even be all that difficult.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 13, 2024, 03:03:33 am
content: Quote from: DavidAlfa on October 12, 2024, 04:48:24 pmI see absolutely no study of CM immunity, and the EVM is common-ground. Presumably the cable is set on the bench with minimal/no source of CM noise as well. Wouldn't be surprised if that's still what dominates the received noise?CAT5 has no ground wire or reference plane defined, so this is a terrible idea in practice.Tim

author: ejeffrey
author_rank: Super Contributor
timestamp: October 13, 2024, 03:04:09 am
content: Quote from: coppercone2 on October 13, 2024, 12:45:12 amOnly at low speed. SPI requires the slave to drive transitions on the falling edge of the clock and the master samples on the rising edge. That means the round trip time has to be << half the clock period. For typical cable (velocity factor 0.7) that would limit you to under about 20 kHz. If you are ok with that then SPI should work fine as long as you can control the ground potential offsets.

author: Smokey
author_rank: Super Contributor
timestamp: October 13, 2024, 03:04:42 am
content: Quote from: coppercone2 on October 13, 2024, 12:45:12 am(not a super long distance transmission expert... )You probably want a current loop for signaling over that distance right, with some pretty high compliance voltage at the transmitters?

author: Smokey
author_rank: Super Contributor
timestamp: October 13, 2024, 03:08:22 am
content: Quote from: T3sl4co1l on October 13, 2024, 03:03:33 amDifferential SPI would only need three pairs (6 wires) and a chip select per slave. If you could still run the chip select single ended, then you could use the 8th wire in a cat5 as the ground reference maybe. Don't some of the higher speed cat ratings spec shielded cables?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 13, 2024, 03:10:08 am
content: Quote from: David Hess on October 13, 2024, 02:29:40 amIf you have a CLK return line, the round trip delay evens out; you need a second SPI channel to receive it, it won't be in sync with the source. Depending on length and delay matching, synchronizers may be required along the way (which can also counter line loss).Undersea telephone cables (analog) I think had amplifiers every couple of miles? And significant compensation filters of course. That was a few MHz of BW, up to a few 10s in the later generations before fiber took over i think.Tim

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 13, 2024, 03:29:43 am
content: Quote from: coppercone2 on October 13, 2024, 12:45:12 amHow about 250,000 miles?

author: Nominal Animal
author_rank: Super Contributor
timestamp: October 13, 2024, 03:32:50 am
content: When the distance exceeds 100m, I go for fiberoptics. SFP transceivers are quite affordable.Quote from: Smokey on October 13, 2024, 03:08:22 amWell, no, it's a separate cable classification. Basically, S/FTP = foiled twisted pair with shield (each pair with a foil shield with a common wire mesh shield), F/FTP = foiled twisted pair with foil shield (each pair with a foil shield with a common foil shield), U/FTP = foiled twisted pair unshielded (each pair with a foil shield, no common shield), F/UTP = twisted pair with foil shield (only one common outer foil shield), U/UTP = unshielded twisted pair (no shields, most common cheap type). The category refers more to the frequency characteristics of each individual pair.For example, if you intend to install some Ethernet cable for use with security cameras powered over Ethernet, you might choose outdoors-rated Cat 6A S/FTP cables, and make sure the conductors are not CCA (copper-clad aluminimium). Some of them are rated for direct underground installation, too.Quote from: SiliconWizard on October 13, 2024, 03:29:43 amLaser link. "Traditional" SPI at such distances makes absolutely no sense, unless you use star-sized emitters and Very Low Frequencies.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 13, 2024, 05:21:49 am
content: You might not consider it SPI anymore, but joining clock with data as Manchester coding for example, negates differences in propagation delay, and then you can modulate it on light as above for example.Tim

author: langwadt
author_rank: Super Contributor
timestamp: October 16, 2024, 02:08:32 pm
content: Quote from: ejeffrey on October 13, 2024, 03:04:09 amdoesn't have to be, SPI is very losely defined to say the least, and how your use the clock edges is a matter of the trading setup for hold