Input bias current and DC errors - Page 1
Forum section: electronics / projects

author: trevortjes
author_rank: Contributor
timestamp: March 02, 2020, 12:57:49 am
content: Hey all,I am working on understanding the error caused by input bias currents of opamps. Now I know that fet input opamps have way lower bias current than bjt input opamps, so I took the TL081 and LM358 to experiment with. In this case the circuit I am working with is an AC coupled non inverting amplifier with a DC offset of VCC/2. To create this DC offset, a simple voltage divider is used as visible in the attached image. To improve on this design, an extra resistor can be added which "injects" the bias current onto the AC to add the offset. This is ofcourse so the lower halve of the voltage divider can be turned into a low pass filter, eliminating some power supply noise from entering the opamp.I've been experimenting with different values for the voltage divider resistors and the injection resistor to see when some kind of DC error starts showing up. The tests were for each opamp:1) Voltage divider 2x1k, 2x100k, 2x2M without injection resistor.2) As above but with injection resistor of 1k, 100k, and 2M tested with each voltage divider pair.I cranked the sinewave at the input until it almost clips at the headroom of the opamp at the output, and then scoped the output while conducting experiment (1) and (2). But while doing this, it seemed like none of the experiments had any dramatic effect on the quality of the sinewave output. The 1k divider significantly reduced the amplitude as expected, but by adding the injection resistor, this was solvable.My expectations was a great shift in DC offset resulting in heavy assymetrical clipping, but that didnt happen. Am I not understanding this problem well? Is my experiment wrong (too low gain for it to have effect?) Does input bias current not matter with AC coupled signals (doubt...)?To further read upon this issuehttps://www.analog.com/en/analog-dialogue/articles/avoiding-op-amp-instability-problems.htmlunder "Decoupling the Biasing Network from the Supply"Please enlighten me!

author: jbb
author_rank: Super Contributor
timestamp: March 02, 2020, 01:22:03 am
content: Your 2x 2Meg divider will have an impedance of 1Meg, which is quite high.In an ideal world, there should be little difference between a divider+series resistor (3 resistors total) and divider only (2 resistors total) when you calculate the overall resistance.Let's have a look at the data sheet for a TL081...The "typical" input bias currents iB seem to be around 30pA (i.e. 30*10^-12 A). If we multiply that by 1Meg, we get: 30*10^-6 V, i.e. 30uV. This is pretty small.The "maximum" input bias currents over temperature seem to be 10nA to 50nA. This would result in 10mV to 50mV DC offset, which might become relevant but probably isn't very obvious either.Oh yes, look out for the TL081 input and output voltage ranges; unlike the LM358, it won't work down to the negative rail.

author: Zero999
author_rank: Super Contributor
timestamp: March 02, 2020, 11:56:06 am
content: Quote from: jbb on March 02, 2020, 01:22:03 amYou forgot R4, which is also 2M, bringing the total DC impedance up to 3M.Quote from: jbb on March 02, 2020, 01:22:03 amI agree, the DC offsets are of no consequence for the TL081 or the LM358, in an AC-coupled applicationThe only issue with such a high input impedance for the LM358 is noise, because it has a BJT input and will have a much higher current noise density, than the TL081. At signal frequencies the impedance of V1 will be dominant, which would presumably be quite high, but with the C2 and R1 having a lower cut-off than R2||R3+R4 and C1, 1/(2π×10k×100µ) = 0.16Hz vs 1/(2π×3M×100n) = 0.53Hz, more low frequency noise will appear on the output.

author: Wimberleytech
author_rank: Super Contributor
timestamp: March 02, 2020, 06:37:23 pm
content: It appears to me you experiment is an LTSpice simulation. Is that correct?

author: trevortjes
author_rank: Contributor
timestamp: March 06, 2020, 04:59:11 pm
content: I have conducted the experiments in real life with the LTSPICE simulations as starting point and visual aid.

author: graybeard
author_rank: Frequent Contributor
timestamp: March 07, 2020, 10:01:16 pm
content: The input currents of FET input op-amps are primarily due to ESD protection diode leakage. Typically there is a reverse biased PN diode connected to both the positive and negative rails of the op-amp from each input pin.Leakage currents are not as well matched as other device characteristics on most processes, so there is no reason to expect the input currents to match, or even have the same polarity.Luckily at room temperature these currents are usually small, 10s of pA to 10s of nA. However they can become significant at elevated temperatures.