DA112S1 Diode Array - what's occurring weirdness? - Page 1
Forum section: electronics / projects

author: max_torque
author_rank: Super Contributor
timestamp: April 29, 2017, 03:59:12 pm
content: I'm using a 12 diode input protection array, the DA112S1:http://www.st.com/content/ccc/resource/technical/document/datasheet/group1/9d/94/61/93/d5/7c/4c/80/CD00000826/files/CD00000826.pdf/jcr:content/translations/en.CD00000826.pdfThis device has 6 sets of diodes between two common rails, Low and High:I have the Low rail pulled to 0v and the High rail pulled to 5v. So, should one of the 6 IO pins go below 0v, or above 5v, then the requisite diode will start to conduct, and bleed off the excess current to the low or high rail respectively.However, what i am seeing is that when one diode starts to conduct the reverse leakage of the other channels seems to increase markedly. I have to be missing something, but at the moment i can't see why this should occur? I've checked and neither rail is moving (is the 0V rail stays at 0V, and the 5V rail at 5V when measured at pin 6 or pinso the excess current is being correctly bleed away to the rails.By way of example, if i increase IO1 above the High rail and with IO2 having an impedance to ground of 168K i get the followingV IO1 V IO2 Calc I IO2  5000 1.3 0.015100 1.3 0.015200 1.3 0.015300 1.3 0.015400 1.3 0.015500 2.4 0.015550 7.3 0.045600 38.2 0.235650 170 1.015660 250 1.49So, whilst that reverse leakage is in-spec according to the data sheet (which says max reverse leakage of 2 uA) i can't quite see why one IO channel should change the leakage on another channel when the rails aren't moving??So, what i am missing??

author: Nauris
author_rank: Regular Contributor
timestamp: April 30, 2017, 02:34:49 pm
content: I dont know the exact mechanism that causes this but I have seen the same thing happen on some PIC micros. Maybe it has some parasitic bipolar transistor structures or some charge carriers get injected somehow into other diodes. Does it affect only adjacent channels or whole chip?

author: max_torque
author_rank: Super Contributor
timestamp: April 30, 2017, 09:15:50 pm
content: I think it affects the whole chip, but i haven't measured the cross coupling for each channel tbh!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 01, 2017, 04:46:10 am
content: Very cool!That means it's a monolithic diode array!So... what?A couple of nearby diode junctions, on a common substrate, are simply a bunch of P-N, P-N, P-N structures. If they're close enough together, they start looking like P-N-P structures -- transistors!It seems they're designed so that the hFE is very low, approx. 0.0001 or thereabouts. Small, but nonetheless present!This can also happen in logic chips -- the ESD protection diodes at the input of a 74HC00 have similar hFE. Beware of this if you're using gates for a low-leakage application, like timing a capacitor against a gated pulse, or something like that. (A capacitor-coupled pulse might intentionally use the ESD diodes for "reset" current; in that case, some leakage into the timing capacitor would occur, distorting the timing slightly.)Tim

author: Ian.M
author_rank: Super Contributor
timestamp: May 01, 2017, 07:06:36 am
content: Yes, Substrate carrier injection from forward biassed protection diodes is a significant problem. It isn't a good idea to rely on normal operation of *ANY* device when any of the input protection diodes are passing current unless it has a spec. for max. protection diode clamping current in normal operation. e.g. on 8 bit PIC MCUs with ADCs, apart from messing up ADC readings on other channels is known to cause such weirdnesses as drastically shifting the internal oscillator frequencies - a factor of two isn't unheard of - and shifting the bandgap reference (if present), causing unexpected BOR resets. If your PIC's doing weird s--t, start by eliminating inputs being taken outside the raiils!

author: max_torque
author_rank: Super Contributor
timestamp: May 01, 2017, 11:38:58 am
content: Wow , interesting stuff! I wish that effect was mentioned on the datasheet though.........(i've got one high impedance channel 'protected' by one set of diodes in the die, with the other didoes used for (relatively) low impedance channel voltage limitations, and when the diodes start conducting it offsets my high impedance channel, DOH! )File that under "things you learn through experience" eh

author: SeanB
author_rank: Super Contributor
timestamp: May 01, 2017, 12:28:58 pm
content: In the older paper manuals it was mentioned in the front, under the "general handling and operating requirements" section.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 01, 2017, 02:27:16 pm
content: Lesson learned: use single or pair dies for stuff like that.I'm not sure offhand if BAV99 is a single die, or two in one package. (Thermal coupling of dies in a package is never good -- so this is an effective way to tell. Heat up one diode and see how fast the other's Vf drops. If it changes rapidly, within ~1ms, it's monolithic; if over 10-100ms or more, it's separate.)There are also quad diode packs, which are handy from time to time. The "two pairs" kind (six pins -- like a double BAV99) are certainly at least two dies, because they don't make any remark about isolation voltage between diode pairs. (Monolithic diodes have a common substrate, so inevitably have some peculiar restriction, like 30V between commmon terminals, because they aren't actually isolated, but there's an intrinsic diode junction between there.)Evidently, some ESD protection arrays are monolithic, like yours -- so avoid those for independent-diode-array duties.Tim