Tang Nano 9K issue with FF - Page 1
Forum section: electronics / general

author: VadimChuskov
author_rank: Newbie
timestamp: October 11, 2024, 12:04:41 pm
content: Hi! I'm experiencing some strange behavior with my Tang Nano 9KRequired: press the button to make the LED light upFact: the LED lights up only after thesecondpressAfter a long search and debugging with a logic analyzer, I got it working. It turned out that to fix it you just need to add a line "assign debugPin1 = s1Out;"Why?Code:module main (input bit clk,input bit btn1,output bit led1,output bit debugPin1);bit s1Out;// = 1'b0;debounce key1Debounce(.clk,.in(btn1),.out(s1Out));initial beginled1 = 1'b1;end//assign debugPin1 = s1Out; // <-------- Fixalways_ff @(posedge s1Out) beginled1 <= 1'b0;endendmoduledebounce:Code:module debounce #(parameter CLK_F = 27000000)(input bit clk,input bit in,output bit out);localparam deadPeriodTicks = int'(CLK_F/100) - 1;bit debouncedIn, debouncedInShifted;bit [$clog2((deadPeriodTicks)):0] cnt = 1'b0;assign out = debouncedIn & ~debouncedInShifted;always_ff @(posedge clk)beginif (~in && ~&cnt)cnt <= cnt + 1'b1;elseif (in && |cnt)cnt <= cnt - 1'b1;if (~|cnt)debouncedIn <= 1'b0;elseif (&cnt)debouncedIn <= 1'b1;debouncedInShifted <= debouncedIn;endendmodulecst-fileCode:IO_LOC "debugPin1" 70;IO_PORT "debugPin1" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;IO_LOC "led1" 10;IO_PORT "led1" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;IO_LOC "btn1" 4;IO_PORT "btn1" PULL_MODE=UP HYSTERESIS=NONE BANK_VCCIO=1.8;IO_LOC "clk" 52;IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;

author: rtv
author_rank: Contributor
timestamp: October 12, 2024, 09:56:40 am
content: "assign debugPin1 = s1Out;" -> Fix didn't work with gowin ide V1.9.10.02Try adding "CLOCK_LOC "s1Out" LOCAL_CLOCK;" to the cst file and it should work.But my limited experience with gowin ide is that clocks generated by combinatorial logic will fail and should be avoided.

author: VadimChuskov
author_rank: Newbie
timestamp: October 12, 2024, 01:18:22 pm
content: IDE 1.9.9Yesterday I accidentally came across a video from a conference where the speaker was talking about the same problem. It turned out that the problem is in 'glitch-free' mode of DCS. Disabling this mode, for example, as below, solves the problem.Code:module main (input bit clk,input bit btn1,output bit led1,output bit debugPin1);bit s1Out;// = 1'b0;debounce key1Debounce(.clk,.in(btn1),.out(s1Out));/////////////////////////////////////// Fix/////////////////////////////////////bit s1OutGlitchless;Gowin_DCS dcs(.clkout(s1OutGlitchless), //output clkout.clksel(3'b0001), //input [3:0] clksel.clk0(s1Out) //input clk0);/////////////////////////////////////initial beginled1 = 1'b1;endalways_ff @(posedge s1OutGlitchless) beginled1 <= 1'b0;endendmodule

author: Rainwater
author_rank: Regular Contributor
timestamp: October 15, 2024, 07:39:28 am
content: Should this sectionCode:debounce key1Debounce(.clk,.in(btn1),.out(s1Out));Be defined like soCode:debounce key1Debounce(.clk(clk), //edit here.in(btn1),.out(s1Out));It looks as tho your debounce module has no driving clock.

author: VadimChuskov
author_rank: Newbie
timestamp: October 15, 2024, 09:39:21 am
content: Quote from: Rainwater on October 15, 2024, 07:39:28 amNo. Verilog implicitly connects a port to a signal with the same name. If you don't declare the signal, Verilog implicitly creates a wire for you with the same name as the port.Although, it depends on the version of Verilog. I use System Verilog

author: asmi
author_rank: Super Contributor
timestamp: October 15, 2024, 03:15:19 pm
content: Quote from: Rainwater on October 15, 2024, 07:39:28 amThe code is correct if it's interpreted as SystemVerilog. SV allows to omit adding wire name if it's name is the same as a port name. This is super useful in testbenches where it typically is the case.