Failure Modes for Synchronous Boost Low-Side MOSFET? - Page 1
Forum section: electronics / projects

author: TimNJ
author_rank: Super Contributor
timestamp: May 05, 2021, 05:44:29 pm
content: Greetings,I'm looking for some input on possible failure-modes for the low-side MOSFET in a synchronous BOOST converter. I am using LM5122:https://www.ti.com/lit/ds/symlink/lm5122.pdfOut of 50 units built, 2 units failed in a similar way, taking out the same 5 or 6 components. My most plausible explanation is that the low-side MOSFET failed first, and the subsequent parts failed as a results. Other parts were the controller IC, and a few parts in the IC's external VCC supply circuit. I think the MOSFET failed drain-to-gate and the rest is history.So far the following testing has been done:1. Check IC's VCC voltage is within acceptable range for all input voltage, and output load conditions---- Constant 13V across all conditions2. Check for excessive drain-source voltage at low-side MOSFET shut-off--- Never observed higher than 50V at the peak, many line/load conditions, 60V rated3. Check for excessive gate-source voltage during switching--- Essentially matches VCC voltage @ 13V, 20V rated4. Check for excessive dv/dt across drain-source during switching--- 1 to 3V/ns maximum, many line/load conditions, manufacturer states ~10V/ns minimumAlthough the details are a little shaky, supposedly the 2 units that failed (during ATE testing), failed while (or shortly after) transitioning the input voltage from 0 - 15V (unit #1) and from 15V - 36V (unit # 2). I've heard of things like low-side MOSFET reverse current failure in synchronous buck converters, but I am not sure if similar scenario is possible in syn. boost. In summary, it seems related to the input voltage transitioning, or some other transitory state, as the steady state operation looks fine, from what I can tell.Any ideas?Thanks!Tim

author: TimNJ
author_rank: Super Contributor
timestamp: May 06, 2021, 09:35:45 pm
content: A few ideas. Not sure if they hold any water:1. Inductor saturation during start-up inrush into output caps at the same time as low-side FET starts switching...looks like VIN short to ground through low-side FET. But, does not make sense for unit #2 which seemed to fail after 15-36V input voltage step.2. Negative voltage spike on switch-node in excess of controller rating... LM5122 says -5V is most it can go below 0V. For the bootstrap to switch-mode, the maximum voltage is 15V. As VCC = 13V, a 2V negative spike puts BST to SW @ the limit. But again, not sure why something like this would be initiating by input voltage stepping.All ideas are greatly appreciated. Thanks.

author: harerod
author_rank: Frequent Contributor
timestamp: May 06, 2021, 10:08:16 pm
content: Try to measure what happens during the supply step. If you can't sync/phase shift the power step to the converter cycle, try to trigger on the power step. Perform several steps and measure at critical points, e.g. the transistor nodes.For starters I would be curious how your bias supply behaved, depending on when during the cycle the power step occurs.

author: TimNJ
author_rank: Super Contributor
timestamp: May 06, 2021, 10:35:13 pm
content: Quote from: harerod on May 06, 2021, 10:08:16 pmThanks! I'm not sure what you mean by "sync/phase shift the power step to the converter cycle". Can you explain? Do you mean timing the input voltage step to the switching edge of the boost converter? In general, the input voltage slew-rate is something like 10V/ms or something on that order, while the switching edge is like 1V/ns with a switching frequency of 100KHz...so the converter goes through many cycles by the time the input voltage has transitioned fully.The low-side drain-source voltage never goes over 50V. When the input voltage is modified, there is short settling time where the drain overshoot peak value stabilizes at a new value. i.e. At low voltage input, the overshoot tends to be higher due to higher currents, while at high voltage input the overshoot is lower. It doesn't change that much, stays within the range 47-50V regardless of input voltage.The bias supply is a constant 13V regardless of input voltage. It is strikingly well behaved. I have not seen any aberations during input voltage switching..It has a 100uF electrolytic cap to keep it pretty stable.

author: jmelson
author_rank: Super Contributor
timestamp: May 06, 2021, 10:43:18 pm
content: Quote from: TimNJ on May 05, 2021, 05:44:29 pmAre you sure this is enough margin? That's only a 17% safety factor.Jon

author: TimNJ
author_rank: Super Contributor
timestamp: May 06, 2021, 11:09:24 pm
content: Quote from: jmelson on May 06, 2021, 10:43:18 pmWell, IPC-9592B suggests only 10% derating for power MOSFETs rated < 200V. Not saying it's a perfect recommendation. But, given they are name-brand Toshiba MOSFETs, I'd expect they should be able to hold up to 50V. But, of course, who knows.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 06, 2021, 11:46:22 pm
content: What's the equivalent circuit between power source and switcher? What ATE power source?There's no possible way you have transient overvoltage protection with that little headroom. Maybe with a crowbar, but definitely not with plain old TVSs.It doesn't take much wiring ESL and supply dV/dt to exceed that rating.Still, very suspicious from only a 36V supply. Possible.Tim

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 12:14:49 am
content: Quote from: T3sl4co1l on May 06, 2021, 11:46:22 pmATE power source was Agilent 6030A. The stated "programming response time", which is the only specification I find about dv/dt, doesn't seem too fast, 100ms max for 2V to full scale.The wiring ESL is about 5uH total, which does seem like it could be problematic. In between the input cable and the boost converter was a over-voltage protection circuit (attached). This circuit was not designed by me, was done a few years aback. I feel it is a little dicey (tbh). I want to move to a more integrated surge stopping solution like LT4356 or something like it.Once Q2 is triggered off an OVP event, R9A & R9B go in series with TVS1. If the detection reaction time (i.e. shut off Q2) is not fast enough, effectiveness of clamp is not as good. SMC36JA states 58V clamping voltage @ Ipp = 25A, FYI.Thank you.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 07, 2021, 01:18:04 am
content: Wait, 36V TVS? How is the inner net "45VDC"?Tim

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 01:34:59 am
content: Quote from: T3sl4co1l on May 07, 2021, 01:18:04 amThe input range is 9-36V. This input voltage has a SMCJ36A across it. (Maybe SMCJ40A would make more sense anyway. As I alluded to, original designer left the company so not 100% sure all design decisions that went into this.) The boost output voltage is 45V. No TVS on the output. 45V rail is actually an intermediate rail feeding resonant LLC stage.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 07, 2021, 02:13:37 am
content: OH. Right, I was reading it backwards.So boost is ~45V and independent of input transients (give or take controller behavior).Have you scoped it while doing the step input stimulus? Something funky with the controller might be a possibility.Tim

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 03:40:11 am
content: Quote from: T3sl4co1l on May 07, 2021, 02:13:37 amAll good.Yes, 45V all the time. I've looked quite thoroughly during input step up and down. The amplitude of the positive-going spike on the low-side MOSFET changes slightly depending on the input voltage (input current I suppose is the driver, really). But the transitory state is seemingly well behaved, smooth transition from, say, 3V spike to 6V spike, and vice versa...Here are some fun clues that I never quite got to the bottom of:1. Production line these were built and tested on is in China. (That's where the Agilent 6030A source is.) The ATE department is really busy so engineering doesn't have much time to get in there and use the equipment to try to replicate the failures. (Can get like 30 minutes every once in a while.)2. My initial thought was "it has to be something with the test setup, equipment, etc." as I'd never seen any issues like this before. Test equipment in the US is different. I figured maybe China equipment has very fast dv/dt capability, but US equipment does not. Ran input voltage stepping a million times with the GWInstek PSU 60-25 source we have. No faults.3. Ignorantly, I tried to power this power adapter from a programmable *AC* source (with DC offset capability) which, mind, has essentially zero output capacitance of it's own, and can change the voltage quite quickly, but also maybe unstable? Lo and behold,the unit failed in same way as originally reported...but stupid me did not have an oscilloscope probe on the input voltage to see what it looked like. Then I read the Chroma manual and it basically said in flashing red lights **do not do this**. Well actually, it said do not use DC capability without first "isolating" the DUT with a bridge rectifier in between source and DUT. After installing a bridge rectifier in between and running more testing, the unit did not fail.Now, I hate to jump to conclusions that it's *definitely* related to the source and that the bridge rectifier *definitely* prevented the issue...but I feel like the answer has to be hidden in there somewhere.Thank you!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 07, 2021, 04:18:54 am
content: Hm, maybe the power supply is as glitchy as the polarity protection (that gate bypass cap has smell written all over it)?Tim

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 04:40:21 am
content: Thanks. By polarity protection, I suppose you are talking about Q2? Q2 is really intended for inrush limiting and over-voltage limiting (once Q2 is off, TVS clamps with 50 ohms in series). Indeed, I feel a bit queasy about the whole circuit. About 3 or 4 discrete circuit blocks kind of whacked together. What kind of smell you think the gate source capacitor might reek of? I believe it's there to keep the gate nearly off at start-up so that the inrush current goes through the 50 ohms.Just trying to imagine what that circuit's potentially glitchy nature has to do with the low-side boost MOSFET.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 07, 2021, 05:41:25 am
content: Oh right again, I should probably look at the actual schematics when posting...Anyway, the two things with the inrush/OV are:1. Cap at gate is a big no-no, it'll oscillate for sure when transitioning. Easy fix, series ferrite bead or resistor.2. No current limiting, so if the load doesn't come up in time, or enables too soon, or is already faulted etc., the transistor just turns into lava.Hmm, is that internally powered BTW? It needs Q11 for enable, but it's not depletion mode. Maybe the other line taps enough bias to start that up..? Well, if nothing else enables, everything precharges through the resistors, it's fine...I'd much prefer one of those wired-OR controllers / hot-swap / OV limiters like LT (I think a few nice ones from TI too?) makes... they aren't necessarily great for accurate current limiting or precharging (basically, putting enough energy into capacitors to get them charged, without smoking the transistor under control) but maybe that's alright here.The next best thing is unfortunately not much of an option; I'm not aware of any integrated solutions for a switching current limit / startup / etc. thingy. I've designed one myself, it's not something you really want to bother with discrete (~50 components I think it was?). So, eh.And yeah, still no explanation for the sync boost.Tim

author: harerod
author_rank: Frequent Contributor
timestamp: May 07, 2021, 07:43:14 am
content: TimNJ, yes, you read me correctly. This syncing would let you see the device's reaction depending on the switch phase. However, since the power supply slew-rate is orders of mangnitude slower than the switcher cycle - never mind.Reading your further information, especially about the remoteness and uncertainty of that test station, I have not any specific ideas. I instantly had some bad feeling about the rather low margins in the ratings, but didn't want to voice them before seeing measurements. (We German engineers have a "bad" reputation of wearing belts and suspenders at the same time, e.g. "overengineering" things. My personal solution for that was to work on projects where a few cents BOM don't matter.)If it was the gate voltages, maybe that bias circuit could use some clamping.All I can suggest is to try and duplicate the test setting and and see if you manage to kill some devices.If you have enough (potentially floating) oscilloscope probes, you could try and connect those to the transistor nodes (changing total capacitance in the process). Try and trigger on the Vgs or Vds of the low-side MOSFET.As the mighty Tim T3sl4co1l suggested, ringing in the supply lines would have been another candidate for trouble, but at that low slew rates?Sorry, not enough data. And no easy way for you to provide that data. Bummer.

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 03:35:51 pm
content: Quote from: T3sl4co1l on May 07, 2021, 05:41:25 amThanks for your inputs. Interesting about the gate-to-source capacitor. I would figure the larger effective Ciss/Cgd ratio would be beneficial to keeping the from some sort of dv/dt induced turn-on? So, what oscillation mechanism are you talking about?Regarding current limiting, not sure how the load coming up too late would be a problem, but I can definitely see why ~too soon~ would be an issue, or if the downsteam converters failed short.At this point, I should just post the whole schematic. What IP am I really protecting here?As I understand it here, Q11 enables the Q2 gate driver as long as LM393 circuit asserts/pulls high, which happens after an inrush timer reaches the TL431 threshold, and when the OVP is not triggered. Again, a little bit of a hackjob, from my view. During a fault condition, VCC is provided by auxiliary NPN regulator (Q13), direct from input rail. I agree with you that I think the LT and similar chips have the fault conditions and corner cases better accounted for, and should overall be more robust.LT4356:https://www.analog.com/media/en/technical-documentation/data-sheets/LT4356-1-4356-2.pdfRT1720GF:https://www.richtek.com/assets/product_file/RT1720/DS1720-01.pdfLM5069:https://www.ti.com/lit/ds/symlink/lm5069.pdf?ts=1620320358819&ref_url=https%253A%252F%252Fwww.google.com%252FSorry to probe you so much here, but when you say, these controllers are not great for precharging...you mean controlling inrush current into DC/DC input capacitors? Controllers above use a very small turn on current, like 50uA to bring the gate voltage up slowly, through the MOSFET's ohmic/linear region. It's interesting you made a comment about the gate-source capacitor, as from the LT4356 datasheet, they actually recommend adding extra gate capacitance if you need gate slew rate to be lower:QuoteThanks again.

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 04:32:59 pm
content: Quote from: harerod on May 07, 2021, 07:43:14 amThank you. If I cannot directly find the issue in a reasonable amount of time, I will probably resort to some sort of DFMEA approach, where I layout a bunch of possible failure modes, try to remediate for them, make those changes and see how it goes from there. Like you said, it might be worth it to put some sort of TVS/zener across the VCC rail just in case its hitting some excessive voltage at an event that I can't quite replicate. (That could be one DFMEA line.)And, I work with plenty of German customers. Rigorous is the word I'd use. Overall, being rigorous is great, but I wonder, is there something about German culture which promotes this sort of fine attention to detail, or do you think part of it is the stereotype imposed from the rest of the world, and German folks feel somehow pressured to live up to that standard?I think I'm going to run with some extra ESL on the input wires, maybe put a big-ass contactor/relay on the input and see if I can make some sparks fly.

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 04:57:54 pm
content: Quote from: TimNJ on May 07, 2021, 03:35:51 pmAh, actually they do not! The capacitor is from gate to ground/reference...not gate to source. Interesting.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 07, 2021, 05:49:42 pm
content: Aaaand, all together for the people at home: <attach>I noticed the CLC filter part changed slightly between screenshots so, mentally stitch together whichever part of that applies. Looks to be just simplified labeling and better condensed wiring, but there is a cut off something-pin-22 in the one, absent elsewhere?Interesting, using a window comparator when the chip has UVLO already; maybe for higher accuracy? Else, just the OV would need to be added (perhaps using a single LM397/TL331?).Can you share the layout (particularly around the inverter)?Quote from: TimNJ on May 07, 2021, 03:35:51 pmNah, not a transient problem, unrelated. Only during turn-on/off, it may oscillate in the 100s MHz.QuoteYeah, those. I've used one of them before, might've been the LM5069? Worked fine, albeit with less load capacitance. I see your total is/should be around 560uF, within the realm of possibility I think? The trouble is, if your transistor isn't big enough (in terms of die and mounting base volume), it won't have a big enough SOA to handle precharge by itself. It's hard to find SMTs big enough to do that -- you're basically limited by physical size, DPAK is too small for much of anything, D2PAK is alright but maybe marginal or too small here, D3PAK does exist but takes up more space and cost -- so, YMMV.Not that that's a problem in and of itself either, as you've got resistors in there -- but the resistors themselves should be protected in that case. Actually I bet you could ab/use one of those controllersas the resistor, and just put a comparator on the hard switch -- so it pulls in only when the voltages are nearly equalized (within 5 or 10% say). That should be a good enough sign that the load isn't faulted, and the precharge has done its job. Meanwhile, the precharge starts up and tries to do its thing, and if it can't, it just sits there disabled and nothing further happens. Fail safe.Alternately, use a depletion MOS big enough that it can handle inrush (assuming precharge isn't a required spec), and turn it off for OV. Hm, "big enough" might not exist -- well, if an enh. mode turns on by Vgs(th), at least it's not as jarring as turning on into the full 36V or whatever. So, that'd be basically mirroring the polarity protection part, with the zener clamp (oh hey, that can be the same 9.1V zener from aux, no need for 16, unless that's also used somewhere else?) except also turning it off when OV is triggered.Oh, OV circuit needs to be ground-referenced to input or the common-source of this back-to-back pair... that's not great. When Q2 is turned off, GND voltage is allowed to rise relative to input GND or the common-source node. Again, maybe not much because the boost is off and resistors are pulling down. But if GND does rise relative to that, then the OV condition can apparently stop, and it starts cycling. (For sure, OV threshold must be below TVS1 clamping voltage; and it looks to be so.)Hm, what is R9 anyway, it's dual?QuoteWant to say I've seen that with an R+C as well. Definitely safer with some damping resistance in there...I think LT in general, has a bad habit of omitting gate resistors, perhaps assuming that the reader knows better? Not sure.Anyway, easy enough to review all the stuffother thanwhat's actually probably going bad... Hopefully some new data can get you closer to your solution.Tim

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 08:00:14 pm
content: Thank you good sir. Oh, the CLC changed slightly because I mistakenly copied one screenshot from a new (tentative) schematic with the IC solution. Sorry. See the new full tentative schematic attached. The white box is the placeholder for a small daughter board with the IC and related parts on it. This is due to RT1720 0.5mm pin pitch not being compatible with wave soldering. Pin numbers (e.g. 22) are nonsense.It's actually not a window comparator. I know the lines are crossing over all over the place there...1/2 LM393 is RC charge circuit, which after some pre-determined time, reaches TL431 2.5V. This is the inrush time-delay circuit. Other 1/2 of LM393 is the over-voltage detection, with about 2V hysteresis. Yeah, I also noticed that the OV reference is the other side of Q2, which means it's not truly the input voltage. Actual testing shows that it seems to sort of work okay with slow voltage ramp up (above OV) and back down.I can share some part of the layout, but can you clarify what you mean by "inverter"? DC-DC boost converter? Input protection? Thanks!Quote from: T3sl4co1l on May 07, 2021, 05:49:42 pmR9A and R9B are two high surge 2512 resistors. (Ohmite AS25)They blasted during the failure too...but that makes sense, because VCC was lost, so gate drive to Q2 was lost so short circuit current had to go through two unsuspecting 2512 for much too long.The nice thing about the IC solution is they almost always have power good pin which only enables once drain-source voltage is almost 0V. When interfaced correctly with downstream controller, it makes sure that the load doesn't try to turn on until the caps are actually charged up. I'm not sure if that's what you were suggesting by the comparator across the MOSFET.For the MOSFET, it is TO-220 bolted to a heatsink. Mind, heatsink is shared with 5 other TO-220 devices, so it will get toasty after it's been running. Here's one option I'm considering based on price, availability, and pretty decent stated SOA:http://www.orientalsemi.com/upload/pdf/prod/SFG180N10PF.pdfI ran a quick simulation with a similar-ish Infineon MOSFET. I need about 15-20A max inrush current. So, I slowed down the gate rise time to ~80mV/ms (i.e. from 0 to 4V in 50ms), which gave about 16A max. Then for the power dissipation, I found it was about 100W average for 6ms and about 200W average for the 1-2ms around the peak. So conservatively, if it can meet 200W for 10ms, then it should be okay. The SOA of the linked MOSFET shows 600W dissipation @ 10ms. This is at Tc = 25C. I'm not actually sure the proper way to derate to say Tc = 65 or 85C.As I mentioned, I am strongly convinced there is some relationship between the power source (ATE, DC source) and the failure, as the only replication of the failure happened when using the AC source in DC mode, without a diode bridge in between. Maybe some issue with reverse current back into the source (which they advise against).As always, thanks for helping to push me in the right direction.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 07, 2021, 08:38:03 pm
content: Inverter, the Q3-Q4 loop, and U1, C21-C23, etc.Tim

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 09:24:17 pm
content: Just to document, if anyone is interested, tried with a current source instead of voltage-source on the gate...which is closer to reality (in terms of the above ICs).3.3nF from gate to common gives the target inrush current of about 16A. Shows roughly the same average power requirement of ~200W for ~3ms, but supposedly the peak power requirement is higher, about 500W for 500us. Linked MOSFET can supposedly do 1500W @ 1ms @ Tc=25C.I then tested (not shown) the shut off performance. With about 10A through the MOSFET, 55mA gate shut off current, 3.3nF slew-rate limiting cap, 10V gate zener... total drain current shut off takes about 2.2us. Hmm. I think that's a little slow given the typical ISO7637 transients have a rise time of about 1us. The target should be <1us. Maybe the TVS + input capacitance will take the edge off.Another alternative is to reduce the gate-drive zener clamp...but I need all the gate drive I can get, given a number of thermal/efficiency concerns. Changing from 10V to 9.1V appears to shave off about 400us...so now we're at 1.8us. Hmm.

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 09:29:43 pm
content: Layouts. Thanks.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 07, 2021, 10:14:14 pm
content: Hmm, looks alright.Tim

author: TimNJ
author_rank: Super Contributor
timestamp: May 07, 2021, 11:07:44 pm
content: Thanks for looking. Well, if I ever figure this one out/get a definitive answer, I’ll leave a reply here.