Generating a 600KHz clock with 10ps Jitter - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 11, 2019, 03:29:47 pm
content: Hi,I have used AD9517-3 in a ZYNQ project before, Now I have a new project, which I need to sample a low speed ADC with 600KHz sample clock, but the problem is that, my customer needs a maximum 10ps jitter sample clock. I told them I will use AD9517 with the fs jitter, But I will divide the generated clock inside the FPGA to achieve the low speed clock with low jitter. But they told me they had a problem with this Technic and spartan 6 before, the Flip-flops inside the FPGA and in the last stage will determine the over all jitter, and they would add so much jitter (in the range of 100-200ps) to the generated clock. so do we have a way of creating a low speed clock with low jitter?

author: Kleinstein
author_rank: Super Contributor
timestamp: November 11, 2019, 04:12:57 pm
content: One could add an additional external sync stage outside the FPGA, so another last flip-flop with a suitable low jitter clock (before the divider / PLL). It depends on the clock if this is possible.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 11, 2019, 09:06:26 pm
content: Yeah, running through an FPGA will definitely introduce jitter. How much depends on exactly how you do it and which pins and IO standard you use. Furthermore, there will be a static propagation delay that depends on the compilation, so if you need the timing to be constant even under updated bitstreams that adds another level of problem.If you need to use the FPGA to produce the clock for some reason you can use an external D flip flop clocked by your high speed clock to generate a low jitter version. Alternately just use a discrete clock divider.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 12, 2019, 06:46:56 am
content: QuoteThe clock generation inside the FPGA is not a must, reading the ADC and doing some DSP on it, should be done in the FPGA, so I thought generating the clock inside the FPGA would ease the problem, the Sample clock should be adjustable, so I thought I could use FPGA and the external AD9517 to achieve the desired clock frequency, But if it can not be done in the FPGA, I can use external parts, what discrete solution or parts do you suggest?

author: BrianHG
author_rank: Super Contributor
timestamp: November 12, 2019, 07:01:11 am
content: Quote from: ejeffrey on November 11, 2019, 09:06:26 pmIt's possible to tell you FPGA compiler to use the IO pin's dedicated flipflop register which would guarantee pin timing every build no matter the logic. This exists usually for the DQ pins for DDR/QDR memory IO pins as their timing is crucial when operating above the 1GHz range.If you use a SERDES pin in the serdes mode to drive your clock output, especially if the FPGA has 12/25GBps outputs, the timing constraints do improve vastly and will be guaranteed every compile as well.However, I don't believe the OP will be using a 2-20K$ FPGA for a 600Khz clock.+1 on using just an external D-flipflop with picosecond jitterles output while using the FPGA to feed it's data input, and using the flipflop's data out as your clock. Obviously the D-flipflop clock input would share the AD9517-3 clock output with the FPGA.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 12, 2019, 09:57:23 am
content: I'm intended to use this puppy,XC7Z020-2CLG400I also I have already told you the clock chip, But I can change the clock chip, so I could achieve my desired goal, so what do you suggest then?

author: Marco
author_rank: Super Contributor
timestamp: November 12, 2019, 11:29:51 am
content: What's wrong with Kleistein's suggestion? Do clock division inside the fpga and add a single external logic IC to reallign it with the undivided low jitter clock.Just need to make sure the edges aren't too close together to keep it deterministic.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 12, 2019, 11:55:30 am
content: Is this clock generator satisfying? si5391 from silicon labs, it has fs jitter spec and can produce from 100Hz to 750MHz, but the jitter is only specified for some frequencies (in the 100 to 200MHz! is it any good for 600KHz?

author: NorthGuy
author_rank: Super Contributor
timestamp: November 12, 2019, 06:44:17 pm
content: The least jitter you can get is by feeding the original clock to a clock-capable pin, and use two ways - (a) to produce the divided signal, and (b) to feed BUFIO which will clock the final stage (e.g. OSERDES or ODDR) forwarding the divided signal to the outside. Whether this would be good enough for you, hard to tell.

author: Marco
author_rank: Super Contributor
timestamp: November 13, 2019, 08:17:51 am
content: AFAICS you want pll bypass if you really want to use a synthesizer, you just need to divide a 48 MHz crystal clock by 80.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 13, 2019, 09:06:29 am
content: QuoteThe jitter is my main concern! the Si5391 claims it can do it, my customer has negative feedback on the use of FPGA, it would add jitter in the range of 100-200ps, have you done it before?

author: Marco
author_rank: Super Contributor
timestamp: November 13, 2019, 10:48:53 am
content: No, but I can think logically. A PLL/VCO is an unknown, it will never improve over the longer time scale stability ... why seek trouble?So if you want to use a synthesizer, pick another one with PLL bypass.

author: BrianHG
author_rank: Super Contributor
timestamp: November 15, 2019, 02:36:27 pm
content: That 10ps jitter spec on a 600KHz sampling clock. Never mind the AD9517 PLL, but, do you have the skills and background to make a PCB, surrounding support circuitry and shielding required to achieve this specification? (IE: ensure that the AD9517 PLL you are using will not receive any external interference at any time diminishing it's jitter performance) Do you have the appropriate testing hardware to prove you have met this specification. Do you know the price of such test instruments which may be used to confirm this specification as such instruments would require sampling clock circuitry with jitter in the sub-picosecond range.No insult intended, but, if I was told I had to guarantee 10ps jitter, I could not do so without the test hardware to back up my claim. I cannot have my client come back to me a year later with a lawsuit for millions lost in revenue due to a portion of their PCBs having 11ps jitter on their 600KHz clock.

author: BrianHG
author_rank: Super Contributor
timestamp: November 15, 2019, 03:00:12 pm
content: Good Luck:https://www.idt.com/us/en/products/clocks-timing/jitter-attenuators-frequency-translation/8t49n240-femtoclock-ng-universal-frequency-translator

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 16, 2019, 06:33:32 am
content: QuoteThanks, i do not have the test hardware, But hopefully the client had it! so I can test it for free in their lab.Thanks for the IDT link though, I have saw that, But I think silicon labs part, Si5340 is easier to work with. Also in page 11 of this IDT device it told that the minimum output clock is around 15.25MHz with the maximum Div setting.

author: BrianHG
author_rank: Super Contributor
timestamp: November 16, 2019, 07:23:42 am
content: Quote from: ali_asadzadeh on November 16, 2019, 06:33:32 amThe are 2 banks of outputs. The fast ones for the high frequency, multiple outputs and the slower one. See what the 'fractional' divider for that port can do can do.

author: NorthGuy
author_rank: Super Contributor
timestamp: November 16, 2019, 02:32:37 pm
content: Quote from: ali_asadzadeh on November 16, 2019, 06:33:32 amThen you can test the jitter introduced with FPGA. Connect the original clock to a clock-capable pin, then feed BUFIO, then forward the clock out with ODDR (google "clock forwarding" if you don't know how to do it).Certainly, PLL and other clock managing things inside FPGA would introduce jitter. So, your client didn't like it. The tiny BUFIO loop may introduce some jitter too, but certainly not as much as PLL. It might be Ok for you.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 16, 2019, 04:45:47 pm
content: Wouldn't testing < 10ps jitter require some serious lab equipment?

author: Marco
author_rank: Super Contributor
timestamp: November 16, 2019, 08:28:09 pm
content: Is the jitter of even the lousiest 48 MHz crystal over 80 cycles going to get near a single ps? I kinda doubt it.

author: dmills
author_rank: Super Contributor
timestamp: November 19, 2019, 01:55:41 am
content: As to measuring such things, measure phase noise instead...Build two of em, lock them in quadrature then a mixer, low pass filter and a low frequency spectrum analyser (Sound card for the close in stuff), turning phase noise into RMS jitter is annoying maths, but it is just maths.600kHz is annoyingly too low in some respects, and picosecond jitter is not going to be easy down that close to DC.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 24, 2019, 07:43:17 am
content: QuoteThanks for the hints, would you explain more, I did not get it fully.

author: Ditiris
author_rank: Contributor
timestamp: November 26, 2019, 01:48:36 am
content: If you're already spending the money on the Si5391 and external PLL, use the Si5391 to generate a clock for a real ADC. Downsample to 600kHz. Doing this with a SAR ADC through the FPGA is asking for trouble. You're not going to get <10ps jitter involving the FPGA in the ADC clocking.

author: edigi
author_rank: Regular Contributor
timestamp: November 27, 2019, 12:53:36 pm
content: Quote from: ali_asadzadeh on November 11, 2019, 03:29:47 pmDDS chip synthesizing sine and creating clock from it with fast comparator like in case of AD9954 (maybe something simpler does it as well)? You don't need to divide anything in FPGA...

author: Marco
author_rank: Super Contributor
timestamp: November 28, 2019, 01:06:04 am
content: Quote from: dmills on November 19, 2019, 01:55:41 amCan't you just XOR them? You are kind of committing yourself to pulling a crystal with a varactor at that point though. Which is a lot harder than just taking say a1.2 MHzcrystal oscillator and dividing by 2 with a single discrete flipflop, which you can't pull into quadrature.Or use a faster oscillator with multiple flipflops for power of 2 or 4 bit presettable counter for non power of 2 divisions, if that helps as edigi suggests. Still, you can't build two and force them into quadrature.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 28, 2019, 05:58:49 pm
content: Quote from: edigi on November 27, 2019, 12:53:36 pmThat's a good approach for higher frequency but not for 600 kHz. The slew rate of a 600 kHz sine wave is too low to get the best jitter performance. A 2V pkpk sine wave only slews about 30 uV in 10 ps. Noise, drift, and crosstalk on your comparator input all need to be under that to reach 10 ps drift. That's achievable with careful filtering and component selection but unnecessary trouble.It's much better to produce a higher frequency square wave -- possibly with a DDS like you describe-- and divide it down. The square wave has high slew rate regardless of frequency.You could use a DDS to produce a "square" wave with a controlled rise time followed by a filter and comparator to clean it up but I don't know of any off the shelf DDS chips that do that.

author: cksa
author_rank: Regular Contributor
timestamp: December 02, 2019, 12:19:42 pm
content: You can't use a clock gen chip which supports down to 600kHz?e.g. Si5348?https://www.silabs.com/documents/public/data-sheets/Si5348-D-DataSheet.pdf

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 03, 2019, 06:22:13 am
content: Quotewhy?

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 06:39:35 am
content: FPGA has very high jitter. If you want low phase noise clock for ADC, you're needs to use external low phase noise oscillator and feed it directly to ADC clock input.You can try to find 600 kHz quartz crystal and use it with with no PLL and no synthesizer to achieve low phase noise. But such crystal oscillator has significant temperature drift, so it may be worth to use some kind of oven to stabilize crystal temperature, like it is used in OCXO.Also it may be worth to look for ultra low noise LDO as a power source for low phase noise oscillator.Low phase noise is not so easy to achieve and it's not cheap, so it may cost you a lot of money, include solutions and test equipment.

author: dietert1
author_rank: Super Contributor
timestamp: December 15, 2019, 11:14:19 am
content: Kleinstein wrote above how to do it (the correct solution). You can use any high frequency low phase noise clock module and a single fast D-Type flipflop chip to sync. Clock generator and sync device should sit close to the ADC, that's how others have done it.We don't know which ADC was going to be used and i am not saying that 10 ps or 100 ps clock jitter makes a difference when sampling at 600 KHz.Regards, Dieter

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 11:55:53 am
content: Quote from: dietert1 on December 15, 2019, 11:14:19 amLet's assume ADC is 20 bit and has 0.1 ps jitter, 0.41 LSB DNL, 0.9 LSB effective noise and we use 300 kHz signal on the ADC input, then1) when oscillator has 10 ps jitter, we have 10.0005 ps combined jitter and 27.75 dB dynamic range degradation2) when oscillator has 100 ps jitter, we have 100.00005 ps combined jitter and 47.67 dB dynamic range degradationSo, the difference between 10 ps jitter and 100 ps jitter will be about 47.67-27.75 = 19.92 dB.Of course it will depends on ADC specifications.For 16 bit ADC, the difference will be about 12.35 dB.For 14 bit ADC, the difference will be about 3.42 dB.For 12 bit ADC, the difference will be about 0.32 dB.Also we don't know if topic starter planning to use undersampling. If yes, then the difference will be much higher.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 12:14:21 pm
content: Quote from: dietert1 on December 15, 2019, 11:14:19 amthe jitter of fast D-type flipflop chip will be added to the oscillator jitter.Logic gates have about the following jitter:- 74LS00 - 4.95 ps- 74HCT00 - 2.2 ps- 74ACT00 - 0.99 ps- LC100EL16 PECL - 0.7 ps- NBSG16 Reduced Swing ECL (0.4V) - 0.2 psSince topic starter talking about 10 ps jitter, the jitter of the logic gate and self-jitter of ADC both needs to be taken into account.

author: dietert1
author_rank: Super Contributor
timestamp: December 15, 2019, 12:23:34 pm
content: Certainly a 20 Bit ADC isn't of the flash type, but includes some kind of sample and hold, which will be affected by the states of other signals of the system, similar to logic timing inside a FPGA chip. I would guess acquisition at 20 bit accuracy is not possible within 1 nsec or less. Here we should be talking about a microsecond or so and i doubt that timing will be accurate to 0,1 psec. If i am wrong, i'd like to know what ADC we are discussing here.Regards, Dieter

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 12:31:13 pm
content: Quote from: dietert1 on December 15, 2019, 12:23:34 pmFor the jitter, we're needs to take into account the frequency of the input signal. Don't confuse it with ADC clock frequency. My calculations above performed for 20 bit ADC working at 600 kHz sample rate. Since it is working at 600 kHz I assumed that the maximum input frequency is 300 kHz. So, for 300 kHz the difference in dynamic range between 10 ps and 100 ps jitter oscillator will be about 20 dB.But the actual ADC bandwidth usually several times higher than the first Nyquist zone. Undersampling may be used to digitize input signal with much higher frequency. In such case the difference will be much higher.So, there is needs to know the maximum frequency of the input signal, and ADC specifications.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 02:47:17 pm
content: Quote from: dietert1 on December 15, 2019, 11:14:19 amThat's how FPGA output is generated - fast D flops. They're already there, inside FPGA. You only need to clock them wisely.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 03:56:22 pm
content: Quote from: NorthGuy on December 15, 2019, 02:47:17 pmThe only problem with FPGA is that it has pretty high jitter. As I remember Cyclone 4 has about 100-200 ps jitter or even worse. So, you can't get 10 ps jitter on FPGA.Even if you will use low phase noise oscillator with 0.1 ps jitter, if you wire it through FPGA, the combined jitter will be:Tjrms-combined = sqrt(Tj-osc^2 + Tj-fpga^2 + Tj-adc^2) = sqrt(0.1^2 + 100^2 + 0.1^2) = 100.0001 psThis is why you can't get lower jitter than the jitter of FPGA. Also you will needs to add jitter of the logic implemented in verilog for the clock. If you use PLL for that, you're needs to add PLL jitter, etc.And this is why ADC with high dynamic range is clocked directly from oscillator and FPGA is not used to produce clock source for ADC.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 15, 2019, 04:25:23 pm
content: Thanks radiolistener for the info, what's the jitter of Spartan 6 flip flops or the PPL output divide down by the internal logic?

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 04:32:07 pm
content: Quote from: radiolistener on December 15, 2019, 03:56:22 pmI guess by "gate" you mean input buffer. It certainly depends on the FPGA. Moreover, it is different depending on which pin you use and what input standard. I don't think FPGA would have worse input buffers than logic ICs.Quote from: radiolistener on December 15, 2019, 03:56:22 pmThe flop timing only depends on the clock, not on the data. If you clock your output flops with the original clock, then what happens in your logic doesn't really matter. What matters is only the clock which has very short travel:Input buffer -> Clock buffer -> flop -> Output bufferIf you have 500 ps rise time at 3V, it is only 60 mV change during your 10 ps period. Any 60+ mV noise or variation in power level (such as not-ideal bypassing) will put you out of your 10 ps. If you have your low jitter at some point, it's very easy to lose it. I'd say keeping the clock inside FPGA may be better than using lots of traces, connections, vias etc.Feeding the clock to FPGA is rather unusual design. Normally, you would feed clock to ADC, and ADC would provide a source-synchronous clock to FPGA to receive data. This way you have very short straight clock line. This would give you much better accuracy and lower jitter. If you need very low jitter, it's crazy to do otherwise.However, if you do feed the clock to FPGA for some reason, I would expect that feeding ADC clock from FPGA outputs would give you somewhat better result compared to external divider.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 04:40:24 pm
content: Quote from: ali_asadzadeh on December 15, 2019, 04:25:23 pmI don't know, needs to read datasheet. But I think it will not meet 10 ps requirement. Even fast 74 logic has about 5 ps. I think with Spartan 6 you will get something like 100-200 ps.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 04:44:12 pm
content: Quote from: NorthGuy on December 15, 2019, 04:32:07 pmFPGA has much-much worse jitter for output buffers than fast 74 logic IC.This is why fast logic IC is used to produce clock for ADC with high dynamic range. Just because if you wire clock through FPGA you will destroy high dynamic range by adding high jitter from FPGA.That's the reason why FPGA never used to produce clock for jitter critical applications such as clock source for high dynamic range ADC.Use FPGA to produce jitter critical clock is very bad idea. I think the best jitter you can get with FPGA is about 100 ps or something like that. For many applications critical to phase noise level this is not acceptable.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 05:06:37 pm
content: Quote from: NorthGuy on December 15, 2019, 04:32:07 pmThe dynamic range of ADC depends on the frequency of the input signal and ADC clock jitter.Just because clock jitter determines ADC aperture uncertainty. Aperture uncertainty leads to non-linear distortions and it reduces ADC SNR performance.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 05:17:05 pm
content: Quote from: radiolistener on December 15, 2019, 04:44:12 pmNon-sense. Any datasheet reference?Quote from: radiolistener on December 15, 2019, 05:06:37 pmWhat this has to do with anything, and how is it related to my sentence that you have quoted?

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 05:22:02 pm
content: Quote from: NorthGuy on December 15, 2019, 04:32:07 pmIf you put 300 kHz sine on the ADC input, on the 20 bit ADC you will get ideal SNR=122 dB.But taking into account clock jitter and non linearity, in reality you will get:- for 0 ps clock jitter: SNR = 111.5 dB- for 1 ps clock jitter: SNR = 109.7 dB- for 10 ps clock jitter: SNR = 94.4 dB- for 100 ps clock jitter: SNR = 74.5 dB- for 500 ps clock jitter: SNR = 60.5 dB- for 1000 ps clock jitter: SNR = 54.5 dBAs you can see if you switch from 1 ps clock jitter to 500 ps clock jitter, you will lose 109.7 - 60.5 = 49.2 dB dynamic range.49.2 dB equals to 8 bits.So, you lose 8 bits of your ADC just because you're using ADC clock with 500 ps jitter instead of 1 ps.This is actual for 300 kHz sine on the ADC input and don't depends on the clock frequency.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 05:24:32 pm
content: Quote from: NorthGuy on December 15, 2019, 05:17:05 pmADC clock input needs low jitter to keep dynamic range according to specification.ADC clock frequency doesn't matter. Jitter matters, not frequency.Topic starter declared 10 ps jitter limit. This is impossible to achieve with FPGA.At least with popular Cyclone 4 or Spartan 6 you will get about 100-200 ps for better case.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 05:41:05 pm
content: Quote from: NorthGuy on December 15, 2019, 04:32:07 pmYou're wrong. In practice DDC receiver which wire clock through FPGA has much worse dynamic range. You can see noise floor raising around carriers and typical high jitter behavior with reduced dynamic range.When clock is wired directly to ADC (or through external high speed divider), the dynamic range is much better. Because clock with no FPGA has better jitter performance and it leads to better dynamic range.You can use clock with jitter on digital domain, but analog signal should be captured with ADC clocked with low phase noise clock source. Low phase noise means low jitter.Jitter leads to uncertainty of ADC aperture and it leads to higher noise. As result it leads to SNR degradation.As you can see on the picture, it depends not only on the clock jitter, but also on the signal frequency on ADC input. Because different input signal frequency leads to different slew rate. The higher slew rate the higher noise will be produced for fixed jitter value.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 06:01:10 pm
content: Quote from: radiolistener on December 15, 2019, 05:24:32 pmYes. That's digital signal. It has rise and fall times. It might be around 500 ps (50 times longer than 10 ps). Whatever samples this digital signal (presumably ADC, but it doesn't really matter) detects the clock edge every time when the signal passes through a certain threshold.If the overall voltage level of the signal varies, the transition curve moves up and down.When voltage rises, the curve moves up, so it will pass through the threshold earlier and the ADC will detect the clock edge earlier.When voltage falls, the curve moves down, so it will pass through the threshold later and ADC will detect the clock edge later.This is the mechanism which creates jitter (and adds this jitter to the pre-exosting jitter). Thus, if you don't control voltage variations, the jitter will become worse. This is primarily the question of stability of power supply, correct bypassing, PCB design etc. The more parts you add into your chain, the harder it is to control voltage variations and the worse jitter you are going to get.Another factor is temperature. If it varies, the propagation delays change. Although this is a very slow change, it too depends on the number of components on the way of the signal.Quote from: radiolistener on December 15, 2019, 05:24:32 pmI don't think it's possible with anything.However, there's no reason why 74 series ICs should be any different than FPGAs - they're built on the same technology and there's no reason to believe they would have dramatically different characteristics.Although you probably cannot achieve 10 ps, you can try to do the best you can. If you use more components, more PCB traces, more legs, more vias etc., you will get more jitter because each of these elements can only add jitter, but cannot remove it. Thus the key is to use less of everything - straight PCB traces, good bypassing, less components, less things that can add jitter. In this respect, FPGA wins because everything is compact and you already have your signal inside FPGA.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 06:06:33 pm
content: Quote from: NorthGuy on December 15, 2019, 05:17:05 pmYou can find it in the "Cyclone IV Device Handbook":Quote

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 06:10:32 pm
content: Quote from: NorthGuy on December 15, 2019, 06:01:10 pmThis is possible with low phase noise oscillator and high speed logic IC.As I mentioned above, 74LS00 has jitter about 4.95 ps.14 GHz D-flip-flop high speed IC has jitter specification about 2 ps.More fast logic IC has 0.2 ps jitter.ABRACON ultra low phase noise oscillators havemaximum guaranteed 75 fs rms jitter over 12kHz to 20MHz BW.As you can see, you can get 5 ps jitter with 74 series TTL logic.Or 0.25 ps jitter with more fast high speed IC (not TTL, but RSECL or PECL).This is at least 60 times better than you can get on dedicated clock output of FPGA and even 130 times better than regular FPGA I/O.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 06:14:21 pm
content: Quote from: radiolistener on December 15, 2019, 05:41:05 pmThat's what we're debating. If you stick "because" in front of it, it doesn't make it true. Clock which comes through FPGA will certainly gain some jitter. The clock which goes through the set of 74 logic ICs will gain some jitter too.We're not debating the influence of the jitter on the ADC performance, and you're already posted 3 times about this.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 06:27:59 pm
content: Quote from: NorthGuy on December 15, 2019, 06:01:10 pmyes, exactly. Low phase noise source requires low noise power supply and low jitter components.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 06:35:21 pm
content: Quote from: NorthGuy on December 15, 2019, 06:01:10 pmFPGA is an array of configurable gates. 74 series IC is a dedicated (non configurable) hardware circuit. This is much easier to layout simple and easy logic element on the crystal and optimize it for high speed and low jitter than do the same for a highly complicated and highly configurable array with high density of elements.As I quoted Cyclone 4 datasheet above, FPGA has 300-650 ps jitter.74HC series has about 4.95 ps jitter.As you can see, 74HC has much-much better jitter performance than FPGA

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 06:39:56 pm
content: Quote from: NorthGuy on December 15, 2019, 06:14:21 pmsorry, I just confused you with other guy who doubted the influence of jitter on the the ADC performance

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 07:28:53 pm
content: Quote from: NorthGuy on December 15, 2019, 06:01:10 pmunfortunately the opposite - FPGA fails.FPGA has much more components inside and much more complicated and configurable circuit than simple and fast hardware D flip-flop. This is why FPGA has 300-650 ps jitter and 74HC IC has just 4.95 ps jitter.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 07:29:42 pm
content: Quote from: radiolistener on December 15, 2019, 06:35:21 pmThe 300/650 ps is the PLL jitter. Since you do not use PLL, this is irrelevant. FPGA has lots of things inside, and the performance depends on things you actually use. I don't know about Altera, but on Spartan-7 (and 6 too) it's a very short path from the external input clock to the output flops. It's done by design to improve IO performance. There's no specs, but I would certainly expect it to be similar to discrete ICs.Quote from: radiolistener on December 15, 2019, 06:35:21 pmIf you want to compare to 74HC then Spartan-7 is likely to have much better characterisics. If you look at the switching frequency, 74HC series are rated for 50 MHz or so, while Spartan-7 is rated for 800 MHz (and can produce 1.6 GHz DDR). I would expect jitter to be better too, but there's no specs. I couldn't find jitter in 74HC74 specs neither.Of course, 12 GHz flops probably have less jitter, but one of them costs like 5 Spartan-7 FPGAs. But then there are some 7 nm FPGAs which cost more than my house and I guess they might be even better.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 07:33:25 pm
content: Quote from: NorthGuy on December 15, 2019, 07:29:42 pmaccording to my tests, it has about 200-500 ps with no use PLL. Unfortunately I don't have equipment to measure it precisely, but I know that it is much worse than 100 ps. Other peoples have the same experience.External 74HC gives much better jitter performance.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 07:38:20 pm
content: Quote from: NorthGuy on December 15, 2019, 07:29:42 pmAs I know, the minimum jitter which can be achieved on Spartan-6 is 177 ps.Quote from: NorthGuy on December 15, 2019, 07:29:42 pmdon't confuse electronic delay and jitter. Electronic delay may be some nanoseconds with jitter smaller than 1 ps. The opposite is also possible - femtosecond delay with nanosecond jitter.Electronic delay (propagation delay) doesn't equate to jitter. Don't confuse these.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 07:48:05 pm
content: Quote from: NorthGuy on December 15, 2019, 07:29:42 pmI don't know about hi-end 7-nm FPGA, may be it has better performance. I don't have it and I don't know people who worked with them. But I have Cyclone 4 and it has 100 times worse jitter than 74HC. And I know other peoples who got the same result. Also I know that other people get 177 ps jitter at best case for Spartan-6. So, it looks like both Cyclone-4 and Spartan-6 have similar jitter.Quote from: NorthGuy on December 15, 2019, 07:29:42 pmIt cannot have the same jitter with discrete IC, because FPGA circuit is much more complicated, it has much more elements, much more complicated crystal layout, more gates, more noise sources. So, this is not surprise that it's output has much more phase noise than plain and simple 74HC. More phase noise means higher jitter.if you don't believe me, just hold the receiver antenna close to the FPGA chip and then to 74HC. You will hear much higher noise near FPGA chip. This noise leads to higher phase noise/jitter, no wonder.Regarding to 74HC, there are different measurements by different peoples, some give 4.95 ps, some 5 ps, some 6 ps. Since different source give almost the same result around 5 ps, we can assume 5 ps per gate for that IC.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 08:35:05 pm
content: Quote from: radiolistener on December 15, 2019, 07:48:05 pmFPGA is a diverse thing. It has lots of stuff inside, and everything is programmable. You cannot characterize all the designs by a single number. A crappy design will have lot more jitter than a good design. You certainly can design something with extraordinary levels of jitter. If you did that, it would be preposterous to say that FPGAs have inherently high level of jitter.It's like if you said that PCs are slower than dedicated calculators because 100 people have tried a cloudy JavaPython calculator program on them and found that this was slower than a real calculator.It's all in the design.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 08:45:13 pm
content: Quote from: NorthGuy on December 15, 2019, 08:35:05 pmYes, but the best reported jitter obtained with FPGA is about 100-200 ps. A lot of people with different design have similar results - about 150-170 ps. And datasheet specification also shows the same values - 300 - 650 ps. All results corresponds to each other and corresponds to the datasheet. And there is no way to get jitter bellow 100 ps on FPGA.This is well known problem that FPGA output has too high jitter, which prevents to use it as a clock source for a high dynamic range ADC.Quote from: NorthGuy on December 15, 2019, 08:35:05 pmNo, I just know that many peoples tried it and there is no success. All results shows that it is higher than 100 ps. And datasheet shows much higher values. So there is no sense to expect that the jitter will be less than 100 ps.Regarding 74 series I was seen one science work with jitter measurements for some IC series. And it also show the same jitter level about 5 ps. Unfortunately cannot find it now. But found at least 4 different sources with similar results (4-6 ps).For example:https://www.sciencedirect.com/topics/engineering/sampling-clockQuotehttps://www.diyaudio.com/forums/digital-source/24908-buffer-choice-iis-direct-4.html#post293292Quote

author: Someone
author_rank: Super Contributor
timestamp: December 15, 2019, 09:56:55 pm
content: Quote from: radiolistener on December 15, 2019, 06:10:32 pmQuote from: radiolistener on December 15, 2019, 06:06:33 pmPerhaps you have no idea what you are talking about?FPGA specifications are worst case guaranteed cycle-cycle (period) jitter.Everything else you are quoting are RMS figures.The 75fs you quote is a band limited measurement.Having measured clocks (including FPGA structures and PLLs) for these parameters I know you are just talking nonsense, come back with some RMS figures for FPGAs when they were optimised for that. FPGAs can be a low noise frequency reference but you need to know both what the actual requirements are (this thread is a mess here), and how to use FPGAs effectively.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 10:12:23 pm
content: Quote from: radiolistener on December 15, 2019, 07:33:25 pmI can give you an idea. Attach two separate oscillators to the FPGA. Forward one out of FPGA, connect it externally to a different pin, and sample it with a clock from the other oscillator. Since the oscillators are a little bit different in the frequency, one will be slipping relative to the other. There will be a long period of '1' then a long period of '0', then '1' again etc.If there were no jitter, the transition would be momentary - you get '1', and then you get '0'. However, because of the jitter, there will be a transitional period - where '1' and '0' are mixed. You just record the length of the transitional period Tt. And you compare it to the full cycle Tc. Then, you calculate the estimate of jitter:J = P * Tt/Tcwhere P is the clock period and J is the jitter.For example, you have two 50 MHz clock sources. If they are 10 ppm, say one is 50.0005 MHz and other is 49.9995 MHz. So, the fast one will outpace the slow one by the whole cycle in approximately 1/(50.0005 - 49.9995) = 1 ms (if you're lucky, this may be much longer giving you better resolution). Say, you detected the period where '1' and '0' were mixed which lasted 250 samples = 5 us. Then you have:Tc = 1 ms = 1000000000 psTt = 5 us = 5000000 psP = 20 ns = 20000 psJ = 20000 * 5000000 / 1000000000 = 100 psIf the period is longer than 250 samples, the jitter is more than 100 ps. If the period is less than 250 samples, the jitter is less than 100 ps.Then you repeat the experiment, but take the FPGA output out of the loop - you enter one oscillator as data into FPGA and sample it with the clock from the second oscillator. This way, you get jitter value without FPGA involved - J0. Then you calculate how much jitter can be attributed to the FPGA:Jfpga = sqrt(J^2 - J0^2)Similarly you can test your logic ICs and various frequencies.All you need is an FPGA board with footprints for 2 different MEMS. This would seem to be a common thing, but I looked through all mine and I haven't found any.

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 10:29:54 pm
content: Quote from: Someone on December 15, 2019, 09:56:55 pmWhat do you mean "when they were optimized for that"?For example I have oscillator connected to the FPGA. Let's say, I want to divide it by 2 and feed it into ADC clock. What do I need to do in order to get 10 ps RMS jitter on the output? FPGA is EP4CE22E22C8

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 11:02:12 pm
content: Quote from: radiolistener on December 15, 2019, 10:29:54 pmRead the datasheet, especially the part on clocking. Find out how to route an external clock to the flip-flop closest to the output pad. Do this. Then write some logic clocked with the same clock which feeds a fixed pattern to the above flop, such as "10" if you want to divide by 2, or "111000" if you want to divide by 6 etc. Or, you can use a SERDES if your FPGA has them - then you don't need the logic as SERDES will feed the pattern for you. Then measure the jitter.Edit: This would give you the best jitter, but nobody knows what it is

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 11:02:22 pm
content: Quote from: NorthGuy on December 15, 2019, 10:12:23 pmThat is interesting, I have board with two places for oscillators, but unfortunately don't have two equal oscillators. Does this approach really allows to measure jitter? Could you please suggest me some article about that, just want to understand how it works

author: radiolistener
author_rank: Super Contributor
timestamp: December 15, 2019, 11:10:12 pm
content: Quote from: NorthGuy on December 15, 2019, 11:02:12 pmDo you mean something like useioff synthesis attribute in verilog?

author: NorthGuy
author_rank: Super Contributor
timestamp: December 15, 2019, 11:28:12 pm
content: Quote from: radiolistener on December 15, 2019, 11:10:12 pmI don't know, I use VHDL, but this sounds like a correct word to select IO flop. It is also important to use the best clock buffer. Say, in Spartan-6 it's called BUFIO2. In Spartan-7 it's called BUFIO.Quote from: radiolistener on December 15, 2019, 11:02:22 pmMore like rough estimate. I don't have an article. You just select the period when the clock edges are very close to each other, close enough so that the jitter is able reverse them (this way you get '0' in the middle of '1's or vise versa). As soon as the clock edges move further apart, the jitter cannot harm the sampling (this way you get all '1' or all '0').They don't have to be the same. It's enough for one to be a divide for another, say 10 MHz and 50 MHz (you then sample with the slower clock), but they must be accurate enough to stick close together long enough to make the measurements.

author: BrianHG
author_rank: Super Contributor
timestamp: December 15, 2019, 11:35:11 pm
content: Quote from: radiolistener on December 15, 2019, 10:29:54 pmYou should be getting better than 43ps jitter as long as you are using a dedicated PLL, have proper low noise power supplies with proper analog ground planes and capping for the PLL, plus, you must have that IO's assignment setting set to 'Fast Output Registers' enabled, with NO asynchronous clocking/resets/presets for that output D flipflop. With that IO's neighboring twin producing a a negative mirror image of the signal, again with 'Fast Output Registers' set for it, you should hit somewhere below 30ps jitter except under poor power supply conditions, or if you diverted from my above specifications. Also, the PLL clocking that flipflop should be at a high frequency. The assignment settings must be done separate and are not specified within verilog source code.

author: ejeffrey
author_rank: Super Contributor
timestamp: December 15, 2019, 11:47:17 pm
content: Quote from: NorthGuy on December 15, 2019, 06:01:10 pmYou absolutely can do 10 ps, it isn't even terribly good. High quality clock distributors have under 100 fs of added jitter (although these use ECL not CMOS). Single digit picoseconds is no problem with standard CMOS.There are several reasons FPGAs are worse althoughh how bad depends very strongly on how you use it. For instance the onboard PLLs are not great. The clock distribution networks are ok, bit still go through multiple gates. Best is to use a fast output register clocked by a dedicated clock coming in from the same bank as the IO. Even so it probably has more gates than a single flip flop. In addition by being inside an fpga you are subject to the temperature and supply voltage variations from the FPGA which affect trigger threshold and delay. If your fpga isn't doing anything else that may not be a problem but then why use an FPGA at all? If you are doing the clock generation on the same FPGA that is collecting the ADC data and processing it then you likely will suffer from these sources of added jitter.QuoteBut you can subtract jitter by retuning the signal with a dedicated flip-flop that has its own low jitter clock that doesn't travel through the FPGA.QuoteAll of that is correct except the last sentence which is inverted.

author: nctnico
author_rank: Super Contributor
timestamp: December 16, 2019, 12:49:30 am
content: Quote from: ali_asadzadeh on November 11, 2019, 03:29:47 pmYour customer is not informed properly. If you clock the FPGA from the AD9517 the jitter of the output signal will have slightly worse jitter but not much. Certainly not 100ps. I think your customer is mistaken by the internal DPLLs in the Xilinx FPGAs. These do introduce tens to hundreds ps of jitter but as long as you don't use these to divide the clock signal you should be OK.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 16, 2019, 07:57:49 am
content: The ADC is LTC2378, I need to do another design though! it's acceptable to use 150ps jitter with a 200Khz sample clock, so I think I should the external clock chip for this design too.

author: nctnico
author_rank: Super Contributor
timestamp: December 16, 2019, 09:48:34 am
content: Don't make your design more complicated than it has to be. Just be sure to read the specifications. If your ADC doesn't need a 50% duty cycle square wave then it is even easier to make a divided clock inside an FPGA without using the internal DPLLs. You can clock everything from a standard oscillator module (but check the jitter specs to make sure). Likely you can use standard 74HC / HCT CMOS logic chips to make the divider if you are only after a divider. Chances are that the internal PLL of a standard microcontroller is up to the task as well so you could use a timer output to generate the clock. I have done this in several designs.

author: iMo
author_rank: Super Contributor
timestamp: December 16, 2019, 10:13:38 am
content: Quote from: radiolistener on December 15, 2019, 06:06:33 pmI ran through the document searching for "jitter". I have not find any reference to something related to the jitter of the logic itself. Everything there is related to PLLs, or various on-chip transceivers..

author: dietert1
author_rank: Super Contributor
timestamp: December 16, 2019, 03:46:39 pm
content: This is an evaluation kit schematic from LT/AD using one of those ADCs. Can you find the sync flip-flop?https://www.analog.com/media/en/technical-documentation/eval-board-schematic/710-dc2289a_rev01_pca_schematic.pdfThe ADC datasheet says aperture jitter is 4 ps typical. No need to be much better than that.Regards, Dieter

author: Marco
author_rank: Super Contributor
timestamp: December 16, 2019, 04:50:42 pm
content: Just need to use a clock which is a multiple of 600 kHz instead of the 100 MHz.