Low power, low noise clock source for precision ADC - Page 1
Forum section: electronics / projects

author: davegravy
author_rank: Regular Contributor
timestamp: January 05, 2022, 10:31:37 pm
content: Having looked at a few datasheets I can fairly confidently say there's generally an inverse relationship between power consumption and noise when it comes to things like ADC drivers, ADC ICs, clock sources, and voltage regulators. Why, I'm not exactly sure, but the pattern is there. The highest precision systems tend to be at least a few watts, not exactly friendly to handheld battery applications.I'm trying to get the best performance I can out of about 50mW. Hopefully 18 or 19 effective bits limited to audio frequencies.I'm focused now on crystal oscillator clock sources. Phase noise seems to decrease with higher power consumption. What are some considerations/strategies to achieve optimal phase noise per watt?It seems that power consumption doesn't increases with clock frequency, and I think I read that if you reduce the frequency of a clock signal you gain a phase noise advantage. Is this true? Does it depend on the method used to reduce frequency (eg counter circuit versus other methods) and if so, how?A reference design I saw appeared to be using a precision 100MHz crystal oscillator and a clock output from an FPGA (presumably pretty noisy) fed together to a D flipflop, then the flipflop output into the ADC. The ADC had a max clock rate of 1MHz so presumably this is getting the precision of the higher clock with the lower FPGA-controlled frequency. Otherwise the FPGA clock could have been used directly. Is this a common technique I should try to leverage? How does it work?

author: moffy
author_rank: Super Contributor
timestamp: January 06, 2022, 12:35:06 am
content: With regard to phase noise, as long as it is random, I think you are basically averaging the noise over the division:https://www.planetanalog.com/how-division-impacts-spurs-phase-noise-and-phase/#Power and noise are related in devices. BJT's have optimum currents at which they run for low noise, also speed tends to be related to current and impedance within devices. We all know that low impedance is less noisy than high, so for a given voltage swing for low noise you need to burn more current than for higher impedance and more noise. That at least is how I would understand it.

author: davegravy
author_rank: Regular Contributor
timestamp: January 06, 2022, 05:55:02 am
content: Thanks for the links. From this, it seems that clock division can reduce phase noise but not jitter.However SNR in an ADC seems to depend on jitter as opposed to phase noise (jitter being the area under the curve of phase noise). So am I correct in concluding that there's generally no advantage from an SNR perspective to using a 100Mhz crystal oscillator and dividing it by 100x versus using the direct output from a 1Mhz oscillator, all else being equal?

author: moffy
author_rank: Super Contributor
timestamp: January 06, 2022, 06:21:34 am
content: I think you are right, in fact I would expect it to be a little worse because the divider will have jitter as well, which will increase the overall clock jitter of the divided signal.https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/white-papers/Clock-Division-WP.pdf

author: Terry Bites
author_rank: Super Contributor
timestamp: January 06, 2022, 02:00:59 pm
content: Something to read under the duvet by flashlight.https://www.analog.com/en/analog-dialogue/articles/analog-to-digital-converter-clock-optimization.htmlHave alook at Renasas Femtoclock® products low jitter oscillators and jitter attenuators.

author: davegravy
author_rank: Regular Contributor
timestamp: January 06, 2022, 03:08:50 pm
content: Quote from: Terry Bites on January 06, 2022, 02:00:59 pmThanks, skimmed it this morning and it seems to contradict my earlier understanding, suggesting clock division is a good strategy. I'll have to comb through it more carefully.Those Femtoclock products are pretty high power, no? The parameteric search doesn't have supply current as an option but I opened a few datasheets and they were >250mA supply.

author: davegravy
author_rank: Regular Contributor
timestamp: January 06, 2022, 06:22:51 pm
content: I found the discussion on filtering in the AD article particularly interesting. A few questions about it:Based on Equation 4 it seems to be talking about a sine-wave oscillator as the source. Looking on Digikey the vast majority of crystal oscillator ICs output CMOS or some variation, there are very few sine-wave output options. Is the article talking about sine-wave types because they're discussing the use of a bandpass filter that's effectively going to yield a sine wave output anyways (if a square wave source were used)? Or is there some other inherent reason for wanting to use a sine-wave source in this application?Am I correct that you could use the same approach with a square wave source, the filter would remove the higher order harmonics but also the phase noise, the clipping circuit would ideally restore the harmonics without the noise?I'm still struggling to wrap my head around why a reduction in phase noise due to clock division doesn't translate into a reduction in jitter and therefor ADC SNR.

author: Terry Bites
author_rank: Super Contributor
timestamp: January 06, 2022, 06:27:27 pm
content: Massive current, thats PECL for you.I read this earlierhttps://statek.com/wp-content/uploads/2018/03/tn35-Rev-B.pdfThe PLLs ability to regenerate a cleaner clock from a very jittery clock is great but as a stand alone device the PLL as clock source can't compete with a binary divided XTAL. Or so I understand.Have you had a look at TIs clock thingyhttps://www.ti.com/tool/CLOCK-TREE-ARCHITECT

author: davegravy
author_rank: Regular Contributor
timestamp: January 06, 2022, 11:32:54 pm
content: Quote from: davegravy on January 06, 2022, 06:22:51 pmI think I figured it out, when dividing by 2 the phase noise curve will drop by 6dB (except at far out frequencies it may be only 3dB) however the carrier frequency will half (in the divisor of the phase noise -> jitter formula) and so the two effects cancel. This raises a new question for me.Here's the datasheet for the crystal oscillator IC I selected.It's a single datasheet for the whole series of oscillators which covers 1 to 75MHz. The typical phase noise curve shown appears to be for a 50MHz model. If I'm instead using a 5MHz unit, would I expect the phase noise curve to be reduced compared to the datasheet, such that the jitter works out to be the same? Or will the phase noise be constant across the series which means the jitter is effectively higher for the lower frequency oscillators?In other words, if I want 5MHz clock, is it better to buy the 5MHz oscillator, or the 50MHz and div by 10?