My Stackable Z80 project... - Page 1
Forum section: electronics / general

author: alank2
author_rank: Super Contributor
timestamp: March 15, 2018, 03:10:36 am
content: I was originally thinking of making a SBC with SMD parts, but even at that I'm not sure if I could fit it all within 10cm x 10cm board like I'd like to. In the meantime I definitely want to get it off of breadboards and onto some real pcb's so I decided to switch to making it a stackable project like the whole shield thing with arduino. This would let me develop each one on its own, troubleshoot and/or correct each one on its own, etc. I'm going to have a left side 2x20 header (all 40 z80 pins) and a right side 2x20 header (aux pins) and use stackable header to join all the boards together. A board for the Z80, one for SRAM, one for the AVR, one for the serial ports, etc.I plan on using an ATMEGA64A to eliminate many of the traditional Z80 SBC peripherals such as EEPROM (the AVR will preload SRAM), SIO, DMA, DISK (microSD via FATFS), RTC, etc.Once I get at least the Z80, SRAM, and AVR boards done, I should be able to then just put smaller with considerably less items on breadboards using the headers easily. That should reduce my bread boarding nightmare.I've got the Z80 schematic done so far, but no board layout yet if anyone wants to review it (attached PDF). It basically is a DC barrel power in with power switch that has some main caps and a TVS, the Z80 basically wired to the left bus (z80 bus), and the only pins it uses from the right bus (aux bus) are two signals to control the speed. It will be software switchable between either 16/8/4/2 or 20/10/5/2.5 MHz controlled from the AVR so it has some logic to split and select the clock on board as well. If you see any bugs or problems let me know!Perhaps one day after everything is tested and mature, I'll try my luck at a single board version.

author: Bud
author_rank: Super Contributor
timestamp: March 15, 2018, 03:44:14 am
content: Not sure if anyone would want to review an unreadable schematic.....it is a 101 example of how Not to draw schematics, sorry.

author: Ian.M
author_rank: Super Contributor
timestamp: March 15, 2018, 04:06:09 am
content: There aren't enough grounds on the Z80 bus header so signal integrity will suck.The original S-100 bus ran at a couple of MHz only had one ground pin, and as it was developed into an industry standard (IEEE Std 696-198) they had to steal back three rarely used signal lines to get good enough grounding to get it up to 10MHz.If you want to keep the Z80 bus on a single connector, consider using 50 way headers to get enough spare pins for well distributed grounding. I'd also use multiple paralleled pins for +5V, as otherwise you are likely to get problems with the +5V contacts overheating.

author: alank2
author_rank: Super Contributor
timestamp: March 15, 2018, 12:05:26 pm
content: Bud - I understand your comment - yes I took the easy way of connecting things with reference labels.Ian - I couldn't get 50 pin connectors for any reasonable price (= they were not on eBay and cost 6 times as much at Digikey/Mouser). I can move some signals to open spots on my aux connector to make room for grounds/vcc's every so many pins on the left one. How many do you think would be smart?

author: alank2
author_rank: Super Contributor
timestamp: March 15, 2018, 12:09:48 pm
content: If I add more GND's, should the VCC's be balanced with them? 8 gnd's and 8 vcc's. Or would 12 gnd's and 4 vcc's be better.

author: medical-nerd
author_rank: Regular Contributor
timestamp: March 15, 2018, 12:12:04 pm
content: HiyaShouldn't the signal lines going to the connector be buffered? I recall this as been standard practice in the electronics magazines cpu boards from the 80's and 90's.Cheers

author: ealex
author_rank: Frequent Contributor
timestamp: March 15, 2018, 03:41:11 pm
content: look over the PC/104 standard(page 10 shows the 64 pin only variant ):https://www.winsystems.com/wp-content/uploads/specs/PC104Spec.pdfyou can find stackable 64 pin headers on ebay, and that will allow for an 8 bit ISA bus:https://www.ebay.com/itm/2Pcs-2-54mm-2x32-Pin-64-Pin-Female-Double-Row-Straight-Long-Pin-Header-PC104/170842981842?hash=item27c70905d2:g:jMkAAOSwiIxZ-yDDmaybe you can keep the expansion pin-out and layout close to the ISA bus - that might allow you to use 8 bit ISA cards in your project

author: matseng
author_rank: Frequent Contributor
timestamp: March 15, 2018, 03:51:21 pm
content: Have you looked at the rather successful RC2014 project? It uses a plain 1x40 pin header onto a passive backpane with 5/8/12 slots without any issues....Using the same pinout/order of pins might make it easy to jus use a simple wiring adapter for connecting their daughter boards to your stack.https://rc2014.co.uk/modules/backplane-pro/

author: alank2
author_rank: Super Contributor
timestamp: March 15, 2018, 03:55:41 pm
content: Absolutely - the RC2014 is pretty cool, and I noticed he only has one ground in his bus. I think there is another ground on the extended bus.Am I better off with 8 grounds and 4 vcc's or 6 of each?Each board will have a proper main cap and bypass caps. Does that make the number of vcc's less important as long as they can all share the overall current. Is it more important to have more grounds than a balance of both?

author: alank2
author_rank: Super Contributor
timestamp: March 15, 2018, 05:14:50 pm
content: And while I'm asking this question about the number of GND's to VCC's, I have a secondary question.With the grounds, I plan to mix them every so many pins, for example, if I have 5 grounds on the left 2x20 connector, I'll put them in even numbered pins so they will be to the right and have good connections to the bottom layer (all ground plane). So perhaps at pins 6, 14, 20, 28, 34.Do the VCC's benefit from being some in a similar distributed fashion, or can they just be put in the center, next to each other, say at pins 22 and 24 for each routing. They are going to some main caps anyway and then to the power devices. (2 layer, so top layer, and I'll use fatter traces).

author: Ian.M
author_rank: Super Contributor
timestamp: March 15, 2018, 05:46:50 pm
content: Group the Vcc pins so they all go to one fat trace - local decoupling to the ground plane will sort out any dynamic issues, You only need multiple pins to get enough current capability with minimal voltage drop for a large stack of boards. Distribute the grounds as evenly as possible - I wouldn't want to go below one in ten pins, or twice as many as the Vcc pins, whichever is greater.

author: alank2
author_rank: Super Contributor
timestamp: March 15, 2018, 11:49:57 pm
content: Thanks Ian - I've updated the sch - certainly fit more GND's along the way.I also organized it so that the GND/VCC pins would be on the inside of the double row. So on the even pins for the left side and the odd pins on the right. This should allow the grounds to connect to the ground plane more directly.

author: alank2
author_rank: Super Contributor
timestamp: March 18, 2018, 01:52:24 pm
content: I added a SRDBL# to allow disabling SRAM if it is ever needed and more BANK signals to be able to access up to 4M.

author: leisergeist
author_rank: Newbie
timestamp: March 19, 2018, 02:43:18 pm
content: Quote from: Ian.M on March 15, 2018, 05:46:50 pmI'm doing a similar project and definitely would have fallen into the same traps. Thanks for the tips!I had written up a pin map using old 64/96 pin DIN-41612 connectors I got for pennies at the surplus, and I only had a VCC and GND pair at both sides of each row, oops!

author: alank2
author_rank: Super Contributor
timestamp: March 22, 2018, 01:30:41 am
content: Do I need to be concerned about buffering or loading for the busses? How many Z80 systems used buffering? Is it still necessary with the different logic families that are available now?

author: David Hess
author_rank: Super Contributor
timestamp: March 22, 2018, 02:39:00 am
content: The ground and power pins do not need to be balanced. Only the voltage drops produced by the currents matter. Sometimes parallel pins are used to lower inductance.If thebypassingis done correctly which includes bypassing at the connectors, then all power and ground pins serve as "grounds" for the various signals. For simplicity though often the grounds are distributed with the signals and the power pins are grouped together.Ideally every signal has an adjacent "ground" which could be ground or power to minimize the loop area but at slower transition (rise and fall) times this is not necessary so there might be a "ground" every 3 or 4 signals or more. Note that it is the transition time and not the frequency which matters.

author: alank2
author_rank: Super Contributor
timestamp: March 22, 2018, 03:35:33 pm
content: That is quite a link. I got through the first couple of pages understanding most of it. Are you suggesting that I need a cap near the VCC on the 2x20 header basically? I plan on having a fat trace to both the left and right VCC pair of pins and having a single 220uF cap along with a 10uF ceramic cap somewhere in the middle.

author: David Hess
author_rank: Super Contributor
timestamp: March 22, 2018, 06:38:31 pm
content: Quote from: alank2 on March 22, 2018, 03:35:33 pmI am suggesting at the power and ground connections should be high frequency bypassed at the connectors just like an integrated circuit would be. This is separate from the local bulk power supply decoupling capacitors which are usually located near the connector if it is used for power.But a Z80 is not all that fast so this should not really be necessary. I would do it anyway to improve signal integrity or at least leave space for the parts just in case.

author: alank2
author_rank: Super Contributor
timestamp: March 22, 2018, 08:14:42 pm
content: Here is what I have so far. The first picture shows the VCC pins and there is some room to the right or I can make some to bypass with a ceramic easily. Should it be 10uF, 100uF, both?The grounds are also shown in the second pic.

author: David Hess
author_rank: Super Contributor
timestamp: March 22, 2018, 10:25:47 pm
content: Quote from: alank2 on March 22, 2018, 08:14:42 pmThe large (it is only large in comparison to the bypass capacitors) bulk decoupling capacitor is usually a higher ESR part like tantalum or aluminum electrolytic to provide dampening over a wide range of frequencies and is normally located where power enters the board. Using a ceramic part for this requires more care because its low ESR can cause some odd resonance problems. For large boards several might be scattered across the board.In an extreme case, every power pin if used for signal integrity across the connector has a small ceramic bypass capacitor to ground. As far as I can see, you are not doing that so you only need one as close to the connector as possible between power and ground and of course likely one at the IC package.Does that Z80 really only have one power pin? Wow, I have just gotten used to seeing lots of power pins on packages like that.

author: alank2
author_rank: Super Contributor
timestamp: March 22, 2018, 10:43:55 pm
content: Quote from: David Hess on March 22, 2018, 10:25:47 pmYes and only one ground. This and they have 4 extra pins on the QFP-44.

author: alank2
author_rank: Super Contributor
timestamp: March 22, 2018, 10:57:04 pm
content: Do you think I should put a 100nF on each VCC set then? or 1uF ceramic or 10uF ceramic...

author: David Hess
author_rank: Super Contributor
timestamp: March 22, 2018, 11:19:13 pm
content: Quote from: alank2 on March 22, 2018, 10:57:04 pmDo you mean other than the local bulk decoupling capacitor? I might include a small ceramic bypass capacitors for each via to take advantage of it where performance at any cost is required but in this case it would really be overkill. You have two Vcc vias so I would use one for the bulk decoupling capacitor and the other for the ceramic bypass capacitor. Later if it is determined that one or both are not needed, they can be left off.The detailed rules for selecting values are beyond the scope of a forum discussion at least for me but a 0.1uF ceramic or smaller and a 10uF solid tantalum or larger part would be typical. I would just use the same ceramic bypass capacitor that you are using for the Z80 for parts commonality.The rough rule for bulk decoupling capacitors is something like 47 to 100 microfarads per amp for aluminum electrolytic and 10 to 22 microfarads per amp for solid tantalum. The rule for ceramic bypass capacitors has to do with capacitive load and worst case switching of the outputs of the IC and 0.1uF or even 0.01uF is larger than necessary for SSI (small scale integration) and MSI (medium scale integration) parts. The Z80 is larger than that but I suspect 0.1uF is still much larger than necessary for it.There is nothing here that is likely to go massively bad because the wrong value was selected unless you use a ceramic capacitor for bulk decoupling and even then, you would probably get away with it.

author: alank2
author_rank: Super Contributor
timestamp: March 22, 2018, 11:34:46 pm
content: Only one board in the stack will be powered and this will be the one. It will have a DC 5V switching adapter powering it on the back, PTC, switch, bulk cap 220uF, smaller 10uF, and a TVS.For this board, do you think a 100nF on the left and right by the each VCC pair will be good.The secondary boards will be powered only from the left and right bus VCC pins. For these, should I put a bulk cap on only one side or both?Part of me doesn't like having VCC on both sides because I have that fat trace cutting the top of the board in half basically. Would it be a better idea to move those 2 VCC pins on the right to the left as well and have no VCC pins on the right? If I did that, then I could put the bulk cap for secondary boards right there on the one side.

author: David Hess
author_rank: Super Contributor
timestamp: March 23, 2018, 12:11:21 am
content: Quote from: alank2 on March 22, 2018, 11:34:46 pmJust one should be sufficient.QuoteJust one side is sufficient.QuoteThat is a good idea if otherwise the ground plane gets cut in half.

author: Ian.M
author_rank: Super Contributor
timestamp: March 23, 2018, 12:24:45 am
content: It may be easier for layout to put a nice wide Vcc trace right round the edge of the board. Move those two Vcc pins to the other pin row of the connector to facilitate that.I specifically don't like the layout to the Z84C0020's Vcc pin. It should have a decoupling cap with two vias to the ground plane right next to the pin. Angle the traces to adjacent pins to make room for that. The other option is to put the decoupling on the back right next to the via that goes to the pin.

author: alank2
author_rank: Super Contributor
timestamp: March 23, 2018, 02:00:57 am
content: Quote from: Ian.M on March 23, 2018, 12:24:45 amI should have mentioned - the Z80 bypass cap is not in place yet, but it will be. I need to do a package/device for it in my library.How much current can a 0.025" square pin carry? I am thinking this will be 1A maximum. I read something about these pins taking 3A! I wonder about the connectors they plug into though. Can I drop from 4 VCC pins to just 2 or 3?

author: Ian.M
author_rank: Super Contributor
timestamp: March 24, 2018, 09:09:47 am
content: Yes you can push 3A through some reputable brands of header pins and mating contacts, but that rating will assume the pin is soldered to a heavy ground plane, both parts of the connector are brand new, and probably that there is a 'R' in the month!In a real world application, with the risk of elevated ambient temperatures, skinny traces, contacts that may have been mated/unmated repeatedly and have a little tarnish on them and possibly the female contacts may be off-brand (worst case: thinner metal and reduced contact force and area), as a rule of thumb, I wouldn't expect trouble with overheating under 1A.However, it isn't usually the connectors burning up that's the big issue, its the voltage drop across them under load. If your ground pins are carrying significant current and if you have any TTL or TTL compatible CMOS on the board, or I2C stuff, their asymmetric logic thresholds make the logic '0' level particularly sensitive to ground offset and excess noise.Worst case, if you are short of pins, you can use as many as possible for Ground and distribute power at a higher voltage on fewer pins, regulating it down to the logic Vcc using a local LDO regulator on each board so the positive supply voltage drop is compensated for.

author: alank2
author_rank: Super Contributor
timestamp: March 25, 2018, 03:55:37 pm
content: Thanks Ian - I went with 4 VCC pins which should be way overkill.I'm adding the schematic for the SRAM board.My "MMU" is very simple. 32K lower bank selected by the BANK signals, 32K higher bank is common.

author: alank2
author_rank: Super Contributor
timestamp: March 27, 2018, 03:44:07 pm
content: Layouts for the Z80 board and SRAM board.Yes...I forgot that you can mix/match address and data pins on the SRAM... Looking at it though, I'm not sure a whole bunch would be gained from redoing it now.

author: alank2
author_rank: Super Contributor
timestamp: April 10, 2018, 08:54:24 pm
content: A couple boards came in from Elecrow. This should hopefully simplify my breadboard and make development easier when I can get back to this project (which won't be for a bit!)

author: alank2
author_rank: Super Contributor
timestamp: April 16, 2018, 09:55:18 pm
content: Does all of this make sense?This is the flip flop circuit I plan to use to allow Z80 IN/OUT/DMA with an AVR.Z80 executes an OUT to 0x80-0x8F:"0111" A7/A6/A5/A4 along with IORQ# asserted and FFCLEAR# deasserted trigger the flip flop through PRE#.The flip flop output goes to a logic level N mosfet to assert WAIT# causing the Z80 to wait.The AVR will notice FFSTATE# asserted on the flip flop and knows it is being addressed.The AVR evaluates RD# or WR# to determine IN or OUT.IN instruction:The AVR grabs A8-A15, A0-A3 (we already know A4-A7) and determines what command the Z80 is trying to input.The AVR sets data port to output and provides the data on D0-D7.The AVR asserts BUSREQ# and then asserts FFCLEAR#.The Z80 will be released from the wait, capture the data IN, and hold at BUSREQ# by asserting BUSACK#.The AVR waits for BUSACK# assertion, then sets data port back to input.If command requires DMA, the AVR can do it here.The AVR deasserts FFCLEAR# (IORQ# is released now and it won't retrigger), then deasserts BUSREQ#.OUT (with DMA):The AVR grabs A8-A15, A0-A3 (we already know A4-A7) and determines what command the Z80 is trying to input.The AVR grabs the data on D0-D7.The AVR asserts BUSREQ# and then asserts FFCLEAR#.The Z80 will be released from the wait, and hold at BUSREQ# by asserting BUSACK#.The AVR waits for BUSACK# assertion.The AVR can do the DMA here.The AVR deasserts FFCLEAR# (IORQ# is released now and it won't retrigger), then deasserts BUSREQ#.OUT (without DMA - if this works):The AVR grabs A8-A15, A0-A3 (we already know A4-A7) and determines what command the Z80 is trying to input.The AVR grabs the data on D0-D7.The AVR asserts FFCLEAR#.The Z80 will be released from the wait.The AVR quickly waits for IORQ# to be deasserted and then deasserts FFCLEAR# before any other possible IN/OUT instruction can execute.

author: alank2
author_rank: Super Contributor
timestamp: April 17, 2018, 02:28:49 am
content: PDF for the AVR board and all of its connections. If anyone is still with me, take a look!

author: alank2
author_rank: Super Contributor
timestamp: April 24, 2018, 12:45:33 am
content: I got the board laid out. When I started I was having my doubts as to whether I could do this with a 2 layer or would have to do 4 layer!Hopefully with this I'll finally be able to get some development going on the software side as I get time.

author: alank2
author_rank: Super Contributor
timestamp: May 05, 2018, 05:54:16 pm
content: I got the AVR board in and built - finally hooked it up to my logic analyzer so I can do some development on it.

author: Ian.M
author_rank: Super Contributor
timestamp: May 05, 2018, 07:11:21 pm
content: Great. Nice to see its coming together. I see you've got another topic:https://www.eevblog.com/forum/projects/10k-pullup-on-signal-takes-1us-to-take-it-back-high/related to the AVR board.

author: alank2
author_rank: Super Contributor
timestamp: May 05, 2018, 07:27:53 pm
content: Thanks Ian.I'm going to try changing the 10K pullups to 3.3K and see if that cleans up the signals a bit.