Inexpensive VCO for a 2GHz clock generator? - Page 1
Forum section: electronics / projects

author: gxti
author_rank: Frequent Contributor
timestamp: September 20, 2012, 01:22:57 am
content: I'm looking to make a 2 GHz clock generator to run a counter that will be used as a time-to-digital converter, measuring time between pulses down to the nanosecond. There are lots of PLL ICs in this frequency range but you have to bring your own oscillator and loop filter. What kind of tunable oscillator would be cheapest and occupy little board area? Frequency stability matters but phase noise does not, if I'm understanding things correctly. I've been browsing lecture notes and papers all night but they're scant on details, and tend to focus on RF where phase noise is paramount. One interesting idea I saw was using a ring oscillator but I'm unsure of how to turn that into a full VCO.

author: AndyC_772
author_rank: Super Contributor
timestamp: September 20, 2012, 07:04:00 am
content: A ring oscillator isn't something I've ever seen used in a practical circuit, though I stand to be corrected if I've missed something. The only time I've ever seen them used is as a test circuit or as a metric for comparing the capabilities of wafer fabs. Whoever's ring oscillator runs the fastest is the winner.How are you going to implement a counter that runs at 2 GHz?For the clock, take a look at TI's LMK series, such as:http://www.ti.com/lit/ds/symlink/lmk04906.pdfIf I were trying to do something like this, I might use an FPGA with (say) 4 counters each running at 250 MHz, with a deliberate phase shift between each of the four clocks. By looking at which counters had incremented and which hadn't, it would be possible to theoretically determine the pulse width with 1ns resolution.Good luck specifying all the timing constraints and getting it to work, though, it's not a job I'd relish. If the pulse widths are reasonably consistent and predictable, I might even consider doing it in the analogue domain with an integrator and an a/d converter instead - but that's just trading one can of worms for another.

author: Codemonkey
author_rank: Regular Contributor
timestamp: September 20, 2012, 08:48:09 am
content: FWIW, I just did something similar to the above suggestion with an Altera Cyclone IV (DE0-Nano dev board). The device has on chip PLL's that can generate multiple clocks all with specified phase shifts. My implementation (My first ever Verilog project!) is clocked at 50MHz which then uses one of the 4 PLL's to create 4 x 90 degree phase shifted clocks to get an effective 200MHz count rate, though the PLL's can also be used to up the clock rate and each one is also capable of creating 5 phase shifted clocks. If you do go down this route, you have to be quite careful with clock gating to make sure you don't sample the multiple counters as they transition.I think you should in theory be able to use all 4 PLL's to create 20 phase shifted clocks!

author: ejeffrey
author_rank: Super Contributor
timestamp: September 20, 2012, 10:59:09 am
content: What counts as 'inexpensive'? A number of manufacturers have clocks synthesizer chips that can make 2 GHz out of something in the 100 MHz range. They have the full PLL on chip.A ring oscillator should work, but I have never tried it. I don't know how fast you can make a discrete ring oscillator. On-chip ones should go a lot faster since the bonding wire / lead inductance doesn't slow down the feedback.If you need or want something discrete rather than a PLL on a chip, I have made a 3 GHz optical PLL using a chain of x4 ECL dividers from ON semiconductor (rated up to 4.4 GHz or so). 3 dividers in series gave a total division factor of 64. I AC coupled the 3 GHz input and transformer coupled the complimentary outputs with a mini circuits balun. The balun then went to a mini circuits 0-100 MHz phase detector. It worked pretty well, and was fairly simple.

author: gxti
author_rank: Frequent Contributor
timestamp: September 20, 2012, 02:55:41 pm
content: I meant to link to the counter but it somehow escaped during the editing process:http://www.digikey.com/product-detail/en/SY10E137JZ/576-2491-ND/1617512I saw at least one article that suggested a 2GHz ring oscillator was possible. The part I was missing is how to tune it, I presume a varactor would be used but would I just stick it in the middle of the ring with no additional parts? My theory-knowledge is really weak which is a big disadvantage to learning stuff as I go along. There are also integrated VCO in this range but they're $25+ each which is beyond my definition of "inexpensive". The clock conditioner chips mentioned earlier also seem to be in the same price range. I did find one promising app note last night using a Colpitts-style oscillator with two varactors, I will fab that one along with some type of ring oscillator and see what happens. If it works then I'll build it out into a full PLL, etc.I did at some point look at building everything out on a FPGA and that is also an option. I had 8x 125MHz counters in simulation, but I think the glue logic to combine all the individual outputs needed some work. This is definitely still an option, because even with the 2 GHz counter I will probably still need a CPLD or FPGA to act as an arbiter and possibly to act as a coarse counter. It would also be easier to transition to an even more complex detector like a Vernier TDC. But while I'm also interested in ways to build a smarter TDC, I'm mostly just curious what it takes to build a cheap 2GHz PLL.

author: Zad
author_rank: Super Contributor
timestamp: September 20, 2012, 04:04:03 pm
content: Any sort of home-brew oscillator at that frequency is going to be really tricky.Is this too big/expensive/cheating?http://uk.farnell.com/crystek/cvco55be-1650-2150/osc-vco-1650-2150mhz/dp/1582086At £13 each it seems pretty reasonable. Consider how many engineer hours it might take to make your own version. On a 1-off or small production run it isn't worth the effort of rolling your own.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 20, 2012, 04:56:41 pm
content: Quote from: gxti on September 20, 2012, 02:55:41 pmYou can tune a ring oscillator by adjusting the supply voltage which changes the propagation delay.

author: gxti
author_rank: Frequent Contributor
timestamp: September 20, 2012, 05:29:24 pm
content: Quote from: Zad on September 20, 2012, 04:04:03 pmProportional to the amount of performance I need, that costs way too much. If I were making a radio transmitter then I'd definitely pony up. It's not that my time isn't worth money, but I'd like to have the option to mass-produce this thing and the total for the rest of the parts, including the PLL chip, would be less than the price of just that VCO.Quote from: ejeffrey on September 20, 2012, 04:56:41 pmGood thinking. I've got some pretty fast dual inverters around here somewhere, maybe I'll breadboard one when I get home. Problem is I don't have a frequency counter, and my scope bandwidth is only 70MHz. Oh well, let's see what happens :-)

author: Zad
author_rank: Super Contributor
timestamp: September 20, 2012, 05:35:00 pm
content: I can't wait to see what sort of frequency stability you get on a 2GHz oscillator!

author: SeanB
author_rank: Super Contributor
timestamp: September 20, 2012, 05:47:06 pm
content: Most ring oscillators are "trimmed" by adjusting the supply voltage fed to it. You need a separate chip to get the output without affecting the input though.

author: Mechatrommer
author_rank: Super Contributor
timestamp: September 20, 2012, 05:52:36 pm
content: 2ghz signal and 70mhz scope is a serious black magic action.

author: Lukas
author_rank: Frequent Contributor
timestamp: September 20, 2012, 07:27:22 pm
content: TDCs don't really require a that fast clock; there are other options:a) Dual slope interpolator, you charge a capacitor with a current for the time you want to measure, than you discharge it with a current some orders of magnitude smaller. This obviously takes longer by the factor of the currents. HP achieved picosecond resolution back in the late 80s by using multislope topologies.b) two startable oscillators and a phase detectors: The start of the event you want do digitize starts one oscillator, the stop starts another oscillator with a slightly offset frequency. After some time, both oscillators will be in phase. This time is proportional to the time difference from start to stop. In the late 70s HP used this principle in a time interval meter; they put the startable oscillators under control of a PLL to prevent them from drifting around and have (had) a patent on that.c) special TDC ASICs such ashttp://www.acam.de/products/time-to-digital-converters/tdc-gp2/, no idea where to orderd) FPGA: You feed the input through a chain of gates and take samples at the the intermediate stages using clocked DFFs. By determining 'how far' the signal has propagated through the chain of gates, you can interpolate between clock cycles. Feed your favourite search engine with "FPGA TDC"

author: gxti
author_rank: Frequent Contributor
timestamp: September 20, 2012, 07:28:45 pm
content: Quote from: Mechatrommer on September 20, 2012, 05:52:36 pmSpoilers: it's not going to work. Bandwidth issues aside, the true sample rate on my scope is only 1Gsps, and the 25Gsps equivalent time sampling is not likely to work either. I need to buy a frequency counter anyway, no time like the present.

author: gxti
author_rank: Frequent Contributor
timestamp: September 21, 2012, 12:46:03 am
content: Just for personal amusement I wired up a NC7WZ14P6X (dual inverter). It's a ring of 1 with the other as a buffer. At 0.9V it oscillates at about 10MHz, 75mV peak-to-peak. At 1.1V it goes up to roughly 50MHz at 20mV. Beyond that it seems to collapse from both too little gain (just a single inverter) as well as hitting the limits of my scope. Still an amusing way to spend 30 minutes. Will have to build something with a longer chain and hopefully a faster inverter if I can find one.

author: nctnico
author_rank: Super Contributor
timestamp: September 23, 2012, 01:57:01 am
content: An ADF4350 should be usefull. Analog also has versions with a more limited frequency range.