FPGA high speed data processing? - Page 1
Forum section: electronics / general

author: steamedhams
author_rank: Regular Contributor
timestamp: July 04, 2021, 07:47:29 pm
content: How do FPGAs handle large amounts of data processing?

author: radiolistener
author_rank: Super Contributor
timestamp: July 04, 2021, 08:02:06 pm
content: You can do things in parallel on FPGA. For example if you configure it as a 100 parallel add blocks it will do 100 addition at one step simultaneously. While usual CPU needs to execute at least 100 cycles to do the same job. So FPGA version will do this job 100 times faster, than usual CPU.

author: steamedhams
author_rank: Regular Contributor
timestamp: July 05, 2021, 06:33:31 am
content: And what about protocols like UDP?? Do these FPGAs have large FIFOs to ensure they capture everything??

author: rstofer
author_rank: Super Contributor
timestamp: July 05, 2021, 07:47:38 am
content: There is usually some BlockRAM and it often dual port so it can be read and written simultaneously even to the same address. Clearly one operation of one or the other will have to block for a cycle if the addresses are equal. You get to choose which is more important.FPGAs that I have used do not have FIFO hardware. Rather, you write code for a FIFO component that uses BlockRAM when it is large enough or some external memory if required.Don't forget to synchronize the incoming signals by passing them through 2 D-flops in series. This adds a little latency but may not be important because the next input value is just 1 flop behind and so on. The edge detector design includes both synchronization and edge detection.https://www.eng.auburn.edu/~nelsovp/courses/elec4200/VHDL/VHDL_SeqModels.pdfhttps://www.doulos.com/knowhow/fpga/synchronization-and-edge-detection/

author: rstofer
author_rank: Super Contributor
timestamp: July 05, 2021, 07:56:26 am
content: Implementing higher level protocols in hardware seems a bit over the top, to me. There are simply too many of them. I would implement a CPU and write protocol code in some higher level language, even if it is just assembly language. But it has been done in hardware.Hamster_nz has a web server that runs protocols in hardware. The goal was absolute security of the server. Mike does some really excellent work.https://github.com/hamsternz/FPGA_Webserver/tree/master/hdl

author: dtodorov
author_rank: Contributor
timestamp: July 05, 2021, 08:09:32 am
content: Quote from: steamedhams on July 05, 2021, 06:33:31 amIn my previous company we worked on hardware-based eth packet parser. We had the packet header digested in few clock cycles using a FSM with no CPU intervention needed.Sure, it costs quite some flops, but it was blazing fast compared to CPU accessing RAM and processing in SW. And of course, some support for fancy protocols (like encapsulation, FCoE and so on) were not implemented and still handled by SW.

author: tggzzz
author_rank: Super Contributor
timestamp: July 05, 2021, 08:21:06 am
content: Quote from: rstofer on July 05, 2021, 07:56:26 amThe High Frequency (share) Trading mob have been known to puttrading business rulesin FPGA hardware. In that business you are counting the microseconds.They have also bought up the microwave towers between Chicago and New York, because the speed of light in air is ~50% faster than that in glass fibres. They have also laid dedicated transatlantic fibres.

author: steamedhams
author_rank: Regular Contributor
timestamp: July 05, 2021, 08:22:23 am
content: You have made my day, this git has some really good stuff.

author: nfmax
author_rank: Super Contributor
timestamp: July 05, 2021, 08:49:42 am
content: Quote from: tggzzz on July 05, 2021, 08:21:06 amI'm surprised myself they haven't got round to putting their FPGAs at the bottom of the North Atlantic, at an equal delay from London & New York. Or maybe they have...