How do I include a differential pair line in a bus structure? - Page 1
Forum section: electronics / general

author: hkBattousai
author_rank: Regular Contributor
timestamp: January 28, 2017, 02:58:04 pm
content: There are several sub circuit blocks in my project, whose some of the input/output ports communicated with buses. And, some of those buses include differential pairs.I attached a minimal demo project to illustrate the problem.When I compile this project, I get the following errors.Code:Top Sheet.SchDocCompilerMissing Negative Net for differential pair , positive net Top Sheet.SchDocCompilerMissing Negative Net for differential pair , positive net Top Sheet.SchDocCompilerMissing Negative Net for differential pair , positive net Top Sheet.SchDocCompilerMissing Negative Net for differential pair , positive net Top Sheet.SchDocCompilerMissing Negative Net for differential pair , positive net Top Sheet.SchDocCompilerMissing Negative Net for differential pair , positive net Top Sheet.SchDocCompilerMissing Negative Net for differential pair , positive net Top Sheet.SchDocCompilerMissing Negative Net for differential pair , positive net And, when I try to update the PCB document, I get the following error messages.Code:Number of nets in differential pair Input3 is 1 instead of 2Number of nets in differential pair Input4 is 1 instead of 2Number of nets in differential pair NetP2_7 is 1 instead of 2Number of nets in differential pair NetP2_8 is 1 instead of 2Number of nets in differential pair NetP2_19 is 1 instead of 2Number of nets in differential pair NetP2_20 is 1 instead of 2Number of nets in differential pair Output1 is 1 instead of 2Number of nets in differential pair Output2 is 1 instead of 2What is the proper way of putting differential pairs into buses in Altium Designer?Top Sheet.SchDocSub Sheet.SchDocPcb.PcbDoc

author: Gribo
author_rank: Frequent Contributor
timestamp: January 28, 2017, 10:59:41 pm
content: Differential nets require _P and _N suffixes for Altium to treat them as a differential pair.

author: hkBattousai
author_rank: Regular Contributor
timestamp: January 28, 2017, 11:44:22 pm
content: I was able to pass differential pairs between sheet blocks by using harnesses instead of buses.But, I still get these compiler warnings:Code:Top Sheet.SchDocCompilerNets Wire Input1 has multiple names (Net Label Input1,Sheet Entry Sub Sheet-Input.1(Passive))Top Sheet.SchDocCompilerNets Wire Input2 has multiple names (Net Label Input2,Sheet Entry Sub Sheet-Input.2(Passive))Top Sheet.SchDocCompilerNets Wire Input3_N has multiple names (Net Label Input3_N,Sheet Entry Sub Sheet-Input.4(Passive))Top Sheet.SchDocCompilerNets Wire Input3_P has multiple names (Net Label Input3_P,Sheet Entry Sub Sheet-Input.3(Passive))Top Sheet.SchDocCompilerNets Wire Input5 has multiple names (Net Label Input5,Sheet Entry Sub Sheet-Input.5(Passive))Top Sheet.SchDocCompilerNets Wire Input6 has multiple names (Net Label Input6,Sheet Entry Sub Sheet-Input.6(Passive))Top Sheet.SchDocCompilerNets Wire Input7_N has multiple names (Net Label Input7_N,Sheet Entry Sub Sheet-Input.8(Passive))Top Sheet.SchDocCompilerNets Wire Input7_P has multiple names (Net Label Input7_P,Sheet Entry Sub Sheet-Input.7(Passive))Top Sheet.SchDocCompilerNets Wire Input9 has multiple names (Net Label Input9,Sheet Entry Sub Sheet-Input.9(Passive))Top Sheet.SchDocCompilerNets Wire Input10 has multiple names (Net Label Input10,Sheet Entry Sub Sheet-Input.10(Passive))Top Sheet.SchDocCompilerNets Wire Output1_N has multiple names (Net Label Output1_N,Sheet Entry Sub Sheet-Output.2(Passive))Top Sheet.SchDocCompilerNets Wire Output1_P has multiple names (Net Label Output1_P,Sheet Entry Sub Sheet-Output.1(Passive))Top Sheet.SchDocCompilerNets Wire Output3 has multiple names (Net Label Output3,Sheet Entry Sub Sheet-Output.3(Passive))Top Sheet.SchDocCompilerNets Wire Output4 has multiple names (Net Label Output4,Sheet Entry Sub Sheet-Output.4(Passive))Top Sheet.SchDocCompilerNets Wire Output5 has multiple names (Net Label Output5,Sheet Entry Sub Sheet-Output.5(Passive))Top Sheet.SchDocCompilerNets Wire Output6 has multiple names (Net Label Output6,Sheet Entry Sub Sheet-Output.6(Passive))Top Sheet.SchDocCompilerNets Wire Output7 has multiple names (Net Label Output7,Sheet Entry Sub Sheet-Output.7(Passive))Top Sheet.SchDocCompilerNets Wire Output8 has multiple names (Net Label Output8,Sheet Entry Sub Sheet-Output.8(Passive))Top Sheet.SchDocCompilerNets Wire Output9_N has multiple names (Net Label Output9_N,Sheet Entry Sub Sheet-Output.10(Passive))Top Sheet.SchDocCompilerNets Wire Output9_P has multiple names (Net Label Output9_P,Sheet Entry Sub Sheet-Output.9(Passive))Some of these warnings can be fixed by removing the unnecessary net labels. But, the net labels ending with "_P" and "_N" suffixes are required, so they will keep generating warning messages. Is there a way of fixing these warning messages without silencing them from the project options?Top Sheet.SchDocSub Sheet.SchDocPcb.PcbDocI still want to learn it if there is a way of doing this buy using buses.

author: ajb
author_rank: Super Contributor
timestamp: January 30, 2017, 04:12:18 pm
content: A net that connects to a harness entry gets implicitely named HarnessName.EntryName, so for instance the net that connects to pin 1 on P1 would wind up named Input.1. But then in your subsheet, you explicitly name that net Input1, hence the multiple names. In the Project Options you'll find a few different options for net naming schemes that you can play with to affect how this gets resolved.In the end, whether or not you permit multiple net names is up to you; it shouldn't cause any problems other than possible confusion when you go to lay out the PCB and the net name you see there may not be the one that you expect. If you look at the schematics for ST's Discovery boards, for example, they have up to three or four names on each net. It's ugly and annoying to read, but it does work.If I were you, I would probably try defining the differential pair names in the harness entries, so instead of 1,2,3..., name them things like DP1_N, DP1_P, DP2_N, etc. This also gives more clear indication of the functions of the nets within the harness. (That's the whole point of using Harnesses instead of Buses anyway!) Then you should be able to leave off the explicit net names you have in the subsheet and let the port names define the harness names. That should give you the suffixes you need without any redundant net names.

author: tszaboo
author_rank: Super Contributor
timestamp: January 30, 2017, 04:19:16 pm
content: Buses are really buses in Altium, meaning that D1..D8 is a bus, but D1,D2,D3,CLK is not. Also, you can place as many input and output on a block, as you want. I never understood why people make a bus or a harness for something they only going to use once.

author: technotronix
author_rank: Regular Contributor
timestamp: January 31, 2017, 10:26:33 am
content: Here is a patent for your reference. This maybe helpful to you.https://www.google.com/patents/US7312639