Translating differential nonstandard ECL signal to single-ended 3.3V - Page 1
Forum section: electronics / projects

author: ZaneKaminski
author_rank: Contributor
timestamp: March 18, 2017, 09:59:51 pm
content: Hi everyone, first post here.Today I received an item I was very excited for, an HP 16500C with two 16556 100/400 MHz state/timing cards and one 16522A 200 Mbit/sec pattern generator card. I had to run out the door right after receiving it, but I did note a few things about the pattern generator before I left.Firstly, I made a slight oversight with my purchase. Looks like, in order to get a standard 5V or 3.3V single-ended signal out of the pattern generator, I need to use these active data pods. Unlike the passive pods for the HP logic analyzers, which are cheap, these pods are expensive: $75-100 each. One 16522A can use up to 5 data pods in addition to the single requisite clock pod, so that's quite a bit of money for me, a poor student.Now, the pods have two sides. One connects to the pattern generator through a long cable, and the other side connects to your system under test. On the SUT side, the 10466A 3-state 3.3V data pod has an /OE input, TristateData[7:0] output, and Data outputted always, independent of /OE. HP says they use a 74LVT244 to drive the output, so that half of the pod is easy.The hard part is translating the signals coming from the pattern generator card into something which the 74LVT244 will understand.QuoteI quickly put my scope on the lines and found the common-mode voltage to be around -2V, with a relatively small voltage swing, less than 500 mV. I will verify these values since I did this really quickly, but I'm pretty sure that's about right.Okay, so I need to put a comparator on these signals to get a single-ended output, but there is a problem. I need to feed the comparator's Vee the provided -5.2V, or at least something below -2V, otherwise the inputs will be out of range. But then the comparator will will be outputting a negative voltage when the V- > V+, and this is not what I want. I want 0V in that case, since the 74LVT244 can't handle a negative voltage.What do I do about this? I see a few options, no idea which are appropriate and which are not (forgive me, I'm a programmer, not an EE):Try and find a comparator that supports voltages well below Vee, then connect Vee to GND and Vcc to 5V. Do these exist?Use op-amps to shift the signal upward. Sounds slow/expensive. This is supposed to do 200 Mbit/sec.Use some kind of zener diode scheme to clamp negative voltages to GND. Is this a good idea? Seems like it would draw too much current when clamping.Am I on the right track with any of these?

author: MagicSmoker
author_rank: Super Contributor
timestamp: March 18, 2017, 10:06:27 pm
content: You might be able to use a standard RS-485/RS-422 receiver IC to translate it. Like, say, Intersil ISL3280, which is good to around 20Mbps.

author: ZaneKaminski
author_rank: Contributor
timestamp: March 18, 2017, 10:22:50 pm
content: Hmm... doesn't sound right. Plus, I would need 8 RS-422 receivers, and I imagine they're sizable. 20 Mbit/sec is also too slow for it to be a serious solution.I see the right way now. It's obvious in retrospect. Goes to show, I don't know the basics.I need to make a push-pull driver using two mosfets/channel. Right?

author: MagicSmoker
author_rank: Super Contributor
timestamp: March 18, 2017, 10:41:18 pm
content: Quote from: ZaneKaminski on March 18, 2017, 10:22:50 pmNo... You really need a proper differential receiver IC, and if you need the full 400MHz then you are in for a world of hurt in regards to maintaining signal integrity. That said, I did a little Googling for you and came up with OnSemi part number MC100EL17 - a differential ECL to 5V TTL translator that can operate up to a blistering 1.75GHz with a propagation delay in the half-ns range. Oh, and there are 4 of them in one SOIC-20 package and they are in stock at Mouser for about $6 each.

author: ZaneKaminski
author_rank: Contributor
timestamp: March 18, 2017, 11:02:53 pm
content: Hmm... the part looks to be correct for my application, but if I use it in NECL mode, with Vcc=0V and Vee=-5.2V, then I still have a negative output, same as before with the comparator, which was where I figured the push-pull driver would be applied.MC100EL17 outputs a single-ended ECL signal, so I could send that into an ECL-to-LVTTL translator/buffer. Is that what you're suggesting?

author: David Hess
author_rank: Super Contributor
timestamp: March 19, 2017, 02:11:48 am
content: Quote from: ZaneKaminski on March 18, 2017, 09:59:51 pmComparators which have a ground or uncommitted output like the LM311 and MC3430/MC3431 line receiver can do this. Or a comparator operating between Vcc and Vee can drive a common base NPN transistor which drives a TTL pullup. Line receivers are just a specialized form of these and are sometime used as fast general purpose comparators.A pair of NPN transistors configured as a differential amplifier can level shift differential NECL to TTL. The collector load of the transistor driving the TTL gate operates as a pullup to Vcc and the tail resistor to Vee and input voltage sets the current.

author: Marco
author_rank: Super Contributor
timestamp: March 19, 2017, 05:52:19 am
content: With the cost of that negative voltage range input LVDS receiver evb149 linked it hardly seems worth the bother to go discrete.

author: ZaneKaminski
author_rank: Contributor
timestamp: March 19, 2017, 07:15:42 am
content: Yeah, Marco, I was just about to say:SN65LVDS33 looks to be the best solution, I think. The OnSemi app note was helpful too, but it only recommended an older chip going for $4+ even in 1000's quantities, and I would need 8. So the quad SN65LVDS33 chip for $2-3 wins, especially since it has built-in tristate output.I was looking for a comparator with a ground like you describe, David, but none are as cheap as the chip evb suggested. I will consider your other alternatives though if the SN65LVDS33 doesn't work out.I measured the signals again and actually, I was a bit off with my initial measurements. The levels are closer to canonical ECL than I thought but are still not quite right. The 1 voltage is off. I attached a screenshot from my scope. Excuse the ringing; I didn't have anything convenient to terminate it.Anyway, from what I can tell, the SN65LVDS33 will work fine. Only problem is that its output source/sink current is not quite as good as the original HP part's "74LVT244-equivalent" outputs. Whatever, it's fine for my needs. I could buffer it again but I'd rather minimize the propagation delay and cost. I'll do a schematic and PCB sometime soon.I dunno if it will stand up to 200 MHz operation though. I (think I) understand fouler analysis, impedance matching, (at least for single-ended signals, maybe I need some help with the NECL-ish differential pairs), how to address ringing, etc., but I am not sure how to apply these techniques to this general device that may be connecting to anything. (Actually, I am hardly sure of how to apply these techniques at all lol, but especially not in this case.)The standard clock pods use 0.1" headers. I've attached a screenshot from the pattern generator manual showing the connector. I was always under the impression that it would be really difficult to properly run a 200 MHz 3.3V signal on one of these, but I guess I was wrong ...?Thanks everyone for all the help so far. I will update once I do some real work, at least doing a schematic.