First time laying out a PCB. Questions regarding power and ground planes. - Page 1
Forum section: electronics / beginners

author: electrodoot
author_rank: Newbie
timestamp: May 01, 2018, 12:51:16 am
content: Hey everyone. I've just joined the forum and have some questions about laying out power and ground planes the proper way on a PCB. This PCB is a power supply.My first thought was to draw a large ground plane on the bottom layer of the PCB and use vias to connect all the ground pins to the plane, but then I realized that the LM2576HVS voltage regulator I was using has a large tab which must be connected to ground. Is it correct to connect that tab to the ground plane using a via as well?And while I have your attention I'll ask about the power rails. This board needs 9VAC and 5VDC rails. I was just going to place these on opposite sides of the top layer of the board. Is this the right way of doing this?EDIT: I forgot to mention, I am using surface mount components.If it is relevant, I am using KiCAD.Thanks in advance!

author: Jwillis
author_rank: Super Contributor
timestamp: May 01, 2018, 01:12:52 am
content: Up to you but I don't see it necessary to use a double side board for such a simple design.Even most manufactured Switching supplies that size are single sided.But I suppose theirs no reason why you couldn't put your output rails on one side .Also your main variable output should have no less than 2mm wide traces.I could be wrong on that but I usually over build things anyway.

author: daubmaso
author_rank: Contributor
timestamp: May 01, 2018, 01:15:02 am
content: Don't worry about the ground plane until after you've routed everything. And I wouldn't put vias everywhere, instead just have a ground plane on the top and bottom of the board. Definitely make sure the tab is directly connected to a ground plane, it will act as the heat sink for the regulator. A via will just add extra thermal resistance and your regulator might over heat.You don't need the power rails to be separated across the board, just put them where it is most convenient.

author: electrodoot
author_rank: Newbie
timestamp: May 01, 2018, 01:22:58 am
content: Thanks to both of you! I really wasn't sure what the best practice was.Does it make sense to draw the ground plane to be the size of the board layer? When I draw the traces not connected to ground it should separate them from the ground, correct? At least that's what I saw KiCAD doing when I was playing around.

author: daubmaso
author_rank: Contributor
timestamp: May 01, 2018, 02:02:47 am
content: I haven't used kicad before, but in eagle you make it larger than the board. Just make sure you name it gnd so that the software knows it's supposed to connect to the ground net. After that it should auto-fill everything and connect the ground nets together, while leaving clearance for other traces.

author: electrodoot
author_rank: Newbie
timestamp: May 01, 2018, 02:08:01 am
content: Awesome. Thanks!

author: james_s
author_rank: Super Contributor
timestamp: May 01, 2018, 02:50:00 am
content: These days most of the hobby oriented board houses don't charge any more for double sided than single sided, so you may as well pour a ground plane in most cases whether you need it or not. I agree though, lay out the board first then pour the ground when you're finished. Otherwise it's easy to end up with a situation where everything is nicely grounded to the plane but the plane itself is actually two or more islands connected by narrow points.

author: pigrew
author_rank: Frequent Contributor
timestamp: May 01, 2018, 04:50:19 am
content: For two layer boards, I like using the bottom for a ground plane, and the top for routing all other signals (as much as possible). I put at least one ground via next to every component ground pin.On the other hand, I've seen some Burr-Brown example boards using the top for ground, and the bottom for signals/power. It's really up to you to (unless you start using signals >50 MHz or so).For non-production PCBs soldered with an iron, feel free to put vias inside the tab pads, it'll help with heatsinking (though that makes soldering more difficult without a preheater).However, for switching power supplies, I'd suggest very closely following the datasheet's suggested layout (and ignore most of what I said above). You have to pay very careful attention to loop currents in order to reduce EMI.

author: Eka
author_rank: Regular Contributor
timestamp: May 01, 2018, 11:47:56 pm
content: Quote from: pigrew on May 01, 2018, 04:50:19 amKeep those loop currents as short as possible.Check the copper layer thickness requirements for your device. Often it is 70um or 2 oz or more. This is so there is enough thickness in the copper layer to transfer the heat fast enough.As for vias. With a high heat generation part, multiple vias arranged under and around the heat tab can be used to move heat to a ground plane/heat sink plane on the opposite side or even into the middle layers or core of the board. I mention heat sink plane because sometimes the voltage potential of the pad used for heat dissipation isn't at ground potential. In one design I made over a decade ago I had both positive and negative heat sink planes, as well as 30 isolated heat sink areas that bounced around voltage wise depending on what the state of the FETs connected to them were. On that board I had power components on both sides to get them directly onto their heat sink flood fill area if possible. Otherwise they used lots of vias to dump their heat into a middle PCB layer with nearly three times the flood fill area.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 02, 2018, 02:18:09 am
content: Place planes on about half the layers in your stackup. Prioritize ground, and fill the other(s) with whatever supplies are dominant by region. (So, the digital area needs 3.3V, the analog area needs 12V. Cut accordingly.)So, on a two layer build, that's just one layer, right? Well...Consider a trace on the bottom layer. Except for very rare or contrived situations, you MUST route signals on the bottom, sooner or later. This cuts the ground plane, putting a slot in it. A trace crossing this slot, on the top side, sees the image of that slot: effectively, a series inductance, which radiates over the area of that slot. This is bad for anything running power, and it's bad for signal quality.So, the easy solution, stitch the ground plane. Everywhere you have a trace on the bottom, add vias and a trace to "jumper" over the slot, stitching it up.Well, what if your design is a bit more involved? If you have a sizable fraction of bottom-side routing, you probably can't afford to add all the jumpers needed to stitch it back up. You probably don't have the space to route buses cleanly around crossings and between components.So, make the stitchings wherever you can. Don't add jumpers, just add vias, and pour both sides.The effect is this: because both pours are considerably chopped up from components and routing, together they act as an average one pour. So that'll be your one.That leaves no room for any VCC, so it must be routed as a normal signal. You may use a wider trace width, certainly if it has to handle more current. Point-to-point routing, with frequent bypass caps, is the simplest topology, and the easiest to get right.The best part is, then you can determine what bulk caps are needed to dampen the network. Take the average routed distance between bypass caps, and the average trace impedance. This gives the typical stray inductance, and now you have a CLC... network, which has a characteristic impedance Z = sqrt(L/C), which is exactly the impedance needed to terminate it. Use a bulk capacitor at least 2.5 times the total bypass on the supply.For example, if a VCC route has six drops, each bypassed with 0.1uF, an average 38mm between drops, and a trace impedance of 60 ohms (typical for about a 20 mil trace), then the inductivity is around 0.28 uH/m, the average inductance per route is 11nH. So the impedance is sqrt(0.011uH / 0.1uF) ~= 0.33 ohms. The total bypass is 6 * 0.1uF = 0.6uF, so 2.5x or 1.5uF. Thus, we need >= 1.5uF, with 0.33 ohm ESR, at either end of the supply. And you're set, no peaky response, solid impedance. (Normally you'd probably choose an electrolytic of 10-47uF, to get the ESR in the right target.)Tim

author: Lt_Flash
author_rank: Regular Contributor
timestamp: May 02, 2018, 06:07:12 am
content: You can also use VCC polygons where you can do that, usually on one side of the board, that's better than using traces, even thick ones. Even when you have to connect that power polygon to a single contact of small IC in QFN package - it's still better than to have a 10mil trace going to that contact.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 02, 2018, 03:37:59 pm
content: The problem with that is, you can't pour both sides independently, and then stitch them independently. Maybe if it's low density, so you have a lot of room for 'jumpers'? But with so much extra space, you're probably worse off due to stray inductance, which again, is proportional to length. Depends what.So the result is, you still need a bypass cap per pin (more or less), to ensure good power quality.You also get maximum distance (and therefore inductance) between planes, which is annoying on 1.6mm proto builds. You can get 1 or 0.8mm protos just as cheaply, which gets you practical trace widths for controlled impedances, and naturally, half the via/plane inductance; but the result is flimsier.Keep in mind the one electromagnetic benefit of plane pairs: you can reduce the number of bypass caps in the design. Everything acts like one big connection. Planes are as ideal as we can get on a PCB. If you aren't doing it to save caps, it's not doing anything beyond the convenience of simply not having to route that net.Also, if you're saying a point-to-point route isn't good enough, you are saying a 0.33 ohm (from my above example) supply impedance isn't good enough. How do you know? Does your logic require very stable supply (say 1% or less variation)? Does it exhibit step changes over 100mA? (Maybe -- 74AC shoot-though is about that bad, for all gates in a chip switching simultaneously.)A step change of 100mA * 0.33 ohms = transient of about 33mV peak. Or worse, at resonant frequencies, if the network is poorly damped -- hence the importance of ESR damping. Without an intentional (or accidentally useful) bulk cap, expect a peak Q around 3-6, or a peak supply impedance up to 2 ohms. Still, if you need 1% ripple, and have much quieter gates of say 16mA peak draw (maybe typical of 74HC with a few gates switching simultaneously), you're set!Justified by arguments like this, you might even consider increasing the distance between bypass caps in a linear-routed design. That is, bypassing every other load, for example. 74HC without strict timing requirements is fine like this. CD4000 you hardly need anything at all in the design, it's so slow. Or you might choose a star or multi-star arrangement, where the bypass cap is central to a group of loads. The trace length to each load might be an inch or two, but is that added 20nH really going to kill it? 5% drop is 8 A/us, or 20mA in 2.4ns. That's safe for 74HC!The power supply is a network like any other, and subject to straightforward engineering design, like any other. There is no need to ignore it, to blindly say "we need a plane", or "we need a sea of bypass caps!" It can be analyzed very easily and roughly, as my above hand-waves show, or simulated in great detail for not much more trouble.The one restriction on this type of analysis: it assumes independent traces, with no coupling. You can't get away with this analysis if there isn't a solid plane in the design. That's why stitching is critical. Coupling, or cross talk, can also be estimated, and it should only need to be considered for signal quality purposes. (If you're doing it to figure if there's a possible functional problem in the first place, or to check if it's okay to run this trace under the switching supply -- no, don't do that.)Tim