hybridfree/eevblog-posts huggingface dataset:
Tang Nano 9K FPGA Board - No USB Cable Connection - Page 1
Forum section: electronics / general

author: iry100fan
author_rank: Newbie
timestamp: November 13, 2022, 02:34:48 am
content: Hi Everyone,I just received my first two Tang Nano 9K FPGA boards. I am having trouble trying to program them.When I run the programmer I get the error message "No USB Cable Connection". I have tried both Linux and Windows plus both boards I purchased but no combination changes the problem. Linux detects the boards as "Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC" and Windows detects it at "SIPEED JTAG Debugger" and two USB Serial Converters show up under device manager. In Windows I have tried installing the driver located in the GoWin Programmer folder but that also made no difference.Does anyone have experience with this and can help?Thanks in advance.-Brian

author: kmike
author_rank: Regular Contributor
timestamp: November 13, 2022, 07:15:42 am
content: I also had problems with older versions of the Gowin programmer, but the newest version works for me (Win10 and Gowin 1.9.8.09)Anyway, Sipeed recommends using their programmer, that worked every time for me, you can download it on the bottom of this page (Attention / point 2):https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html

author: iry100fan
author_rank: Newbie
timestamp: November 13, 2022, 04:12:45 pm
content: Hi kmike,I upgraded from version 1.9.8.08 to 1.9.8.09 and the USB cable was immediately detected in Windows. Thank you for the information.Linux still doesn't see the cable, but as you stated, Sipeed recommends a different method. I will try that out a little later and see how that goes under Linux.Again, thanks for the help.-Brian

author: kmike
author_rank: Regular Contributor
timestamp: November 14, 2022, 09:12:16 am
content: Hi,for Linux, you could also use openFPGALoader, the Tang Nano 9k is on the list of supported boardshttps://github.com/trabucayre/openFPGALoaderbr,kmike
Cheap and easy way of converting Altera HSMC to Xilinx FMC? - Page 1
Forum section: electronics / general

author: TopQuark
author_rank: Frequent Contributor
timestamp: October 26, 2022, 09:08:29 pm
content: Hi, I have been looking at the DC2390A eval board from ADI (https://www.analog.com/media/en/technical-documentation/user-guides/DC2390AF.PDF), and it suits my needs perfectly in every way for the task at hand.The only problem is the board comes with a HSMC connector that is more often found in Altera dev boards, but my experience, tooling and existing dev boards are Xilinx based and only supports FMC connectors.My question is then: anyone aware of cheap and easy to source adapters or simple hacks I can use for the conversion? I mean if I am desperate I can just solder mod wires and connect the eval board to my FPGA dev boards, but Ireallydon't want to go that way.

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: November 09, 2022, 04:39:27 pm
content: Looks Kaya Instruments have an adapter which I think will do what you want.https://www.skyblue.de/en/legacy-and-exotic/legacy-kaya/kaya-ky-fmc2hsmc-kaya-fmc-to-hsmc-adapterhttps://dsp-tdi.com/Kaya/FMC2HSMC.pdf
Lattice XP2 daisy chain failed to program - Page 1
Forum section: electronics / general

author: ryantran
author_rank: Newbie
timestamp: November 07, 2022, 05:46:14 pm
content: HI All,I've been stuck on this problem for weeks and could not figure out why. I am unable to program 2 LFXP2-8E- PQFP208 connected in daisy chain on a prototype board.I made sure TDI, TMS is pulled high with a 4.7K resistor and TCK is pulled low with a 68Ohm (I even tried adding another 47pF cap). Both are configured in Self-Download-Mode (CFG0 pin is set to 1). PROGRAMN, INITN, DONE are left floating. I'm using JTAG programmer TE0790-03L and Diamond Programmer. The Diamond Programmer was able to consistently scan 2 devices (with a warning that it cannot recognize the package). But when I start programming, sometimes I received the error "Failed to verify ID" during configuration setup. other times the JTAG chain verification pass, Erase pass but failed during program with errors "failed PROGRAM_STATUS" or "failed in READ_ID". So even the errors are not consistent. Furthermore, on our system we have another MachXO2 sitting by itself having its own JTAG connector and I was able to flash the MachXO2 perfectly fine with the same hardware and software. So it can't be the JTAG programmer.Before working on this prototype, I created a simple dummy board that has LFXP2-8E-PQFP208 and MacXO2-640UHC-144 connected in chain. Using exactly same JTAG programmer and software, I am ABLE TO consistently program the 2 FPGAs on this board without any problems. Of course I've been trying to match all configuration on this prototype with the dummy board. So I'm confused why it does not work in the case of 2 LFXP2 connected in chain.Any suggestions are really appreciated! Thank you!Huy

author: mon2
author_rank: Frequent Contributor
timestamp: November 07, 2022, 06:54:17 pm
content: No direct experience with this setup but:Quotesounds extremely aggressive. Remove this resistor and test again. Suggest 10k or higher if you wish to park this line in IDLE states. Fairly sure that JTAG TCK will be push-pull type so even this external resistor is of no value.
Buying a Microsemi/Microchip Libero lisense - Page 1
Forum section: electronics / general

author: Daixiwen
author_rank: Frequent Contributor
timestamp: November 02, 2022, 10:51:07 am
content: Buying Microsemi licenses has never been easy, but since Microchip bought them it got really ridiculous...I need to renew a license with two seats. Arrow sent me first an offer with only one seat, and needed 10 days to update it with two seats, stating problems between their order management system and Microchip's. Now that I sent the order, this is the confirmation I received:3 weeks to generate a license? And a renewal even?I hope I get it hand engraved on a marble slab with gold plating.I could order directly on Microchip Direct and bypass Arrow, but as far as I know you don't get the license directly either but get contacted by a distributor that will happily generate it for you, so I'm not sure it will be any faster. Has anyone any experience with that?

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: November 04, 2022, 11:03:27 pm
content: You can buy and manage licences without a distributor on Microchip Direct.The licence file is then emailed to you directly from Microchip.
Nesting arrays - Page 1
Forum section: electronics / general

author: kakemoms
author_rank: Newbie
timestamp: November 02, 2022, 07:11:42 am
content: HiI have a few arrays of 256 bytes that are defined like this:Code:reg [7:0] array1 [0:255]reg [7:0] array2 [0:255]and so on..Now, I refer one array inside another for certain conditions to occur (and I do this several places):Code:(array1[array2]==validvalue)?Yes:No;The thing is that my fpga code gets huge unless I limit the array size. So it seems its not a good idea.. but why does this happen? Its only 256 bytes per array.. but it consumes like 20000+ LUT4's.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: November 02, 2022, 12:08:07 pm
content: You can use the RTL viewer to see what kind of logic is generated from your code, but the main problem is probably that the synthesizer can't use the hardware RAM blocks in the FPGA and have to implement the arrays using LUTs only. It means already one LUT per bit, so 4096 LUTs plus the address decoding logic. If you do this in several different places, and they each run in parallel, each implementation will have its own set of address decoding logic LUTs. And if it gets too complicated, the synthesizer may in addition be required to duplicate some logic to meet the timing requirements.If you need to reduce LUT usage you'll have to look into using the RAM blocks to store the arrays. Depending on the synthesizer you use, you may have to write your code in a certain way (for example register the input and/or the output, and limit access to two ports or less) or use a pre existing RAM ip block that you instantiate in your code. You will probably have to redesign your code around those lines, to adjust to the extra latency from the input/output registering, and try to centralize access instead of spreading it in several places.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 02, 2022, 07:51:00 pm
content: HDL is not like (sequential) software programming.If you're addressing "arrays" in naive ways, it gets extremely expensive very fast, because basically what you wrote expresses a combinatorial access to memory.One way of doing this much better is to pipeline it. Pipelining will also enable synthesis to possibly infer block RAM, while as expressed here, it will never infer that.Pipeling here will consist in registering 'array2' and use that register to address 'array1'. Of course this will introduce a 1-clock latency which you need to account for. And all this needs to be put inside a clocked process.

author: kakemoms
author_rank: Newbie
timestamp: November 03, 2022, 02:32:30 pm
content: Thank you for good answers.I used this as a part of a state machine, so pipelining is already there... then you want to accomplish something, and just enter it without too much thought about what is actually going on...Looks like I have to analyze his thoroughly before I reimplement the arrays (in an unnested form).Thanks again!
New Gowin Tang Primer 20K board from sipeed - Page 1
Forum section: electronics / general

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: August 22, 2022, 10:21:22 am
content: I just found this on sipeed's store, I am guessing it is new:https://www.aliexpress.com/item/1005004653308809.html?spm=a2g0o.productlist.0.0.328a1cda6smDev&algo_pvid=9cb12bbe-49b6-4bf1-93e2-b5a0f0bacbe8&algo_exp_id=9cb12bbe-49b6-4bf1-93e2-b5a0f0bacbe8-0&pdp_ext_f=%7B%22sku_id%22%3A%2212000029997195117%22%7D&pdp_npi=2%40dis%21CAD%2143.7%2143.7%21%21%2111.74%21%21%402103399116611626204054768eb616%2112000029997195117%21sea&curPageLogUid=b5IGLRVeaXQOalso on sipeed's github:https://github.com/sipeed/TangPrimer-20K-example

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: August 22, 2022, 06:29:32 pm
content: This has just changed a project design for me. Thank you so much

author: davorin
author_rank: Unknown
timestamp: October 13, 2022, 01:44:43 pm
content: Hmmm...the 20K dock isn't available yet it seems....at leadt not listed there just pictured...

author: mon2
author_rank: Frequent Contributor
timestamp: October 13, 2022, 07:17:39 pm
content: QuoteCorrect. Believe they mentioned this month or next for the ETA. You can chat them during their normal business hours (middle of the night for us)

author: davorin
author_rank: Unknown
timestamp: October 14, 2022, 11:52:28 am
content: Seems to be available now on AliExpress:https://de.aliexpress.com/item/1005004653308809.htmlGonna order two of those combos now (o;

author: davorin
author_rank: Unknown
timestamp: October 29, 2022, 07:48:07 am
content: Good morning (o;Received my two Tang Primer 20K boards...and could upload the HDMI example from their github onto it....But on Linux you have to use openFPGAloader as the Gowin programmer fails on finding the FTDI cable.Code:sudo openFPGAloader -b tangprimer20k -d dk_video.fsTo make sure it did program successfully I changed the example (o;
Gateware for the ECP5 to determine connections, howto? - Page 1
Forum section: electronics / general

author: cedric!
author_rank: Contributor
timestamp: October 22, 2022, 07:17:26 am
content: I have bought a Colorlight 75E FPGA board containing an ECP5 FPGA. I noticed I have version 8.0 of the hardware, and that one is not yet documented on this repository .I would like to create gateware that shows what ball of the FPGA goes to what point on the headers.On each pin, I would like to output a train of pulses, that indicate the ball. First a preamble, and then 2 burst indicating the row and column That way I can look at an LED to figure out the connection.For example:A2: 10101010101010000010000010010000 (and then repeat)G4: 10101010101010000010010010010010010010000010010010010000C4: 10101010101010000010010010000010010010010000Has this already been done?Where can I find a file that defines the balls of the FPGA package?https://github.com/q3k/chubby75

author: hve
author_rank: Regular Contributor
timestamp: October 25, 2022, 01:18:16 am
content: Yes here's some code for the pin scan:https://github.com/q3k/chubby75/tree/master/5a-75b/pin-scan
The History of the FPGA - Page 1
Forum section: electronics / general

author: BrianHG
author_rank: Super Contributor
timestamp: October 20, 2022, 11:37:01 pm
content: The History of the FPGA

author: cedric!
author_rank: Contributor
timestamp: October 22, 2022, 07:18:28 am
content: Worth the watch. Thanks.
GPIO inputs on Altera MAX10 - Page 1
Forum section: electronics / general

author: Vivis
author_rank: Contributor
timestamp: October 14, 2022, 05:30:08 pm
content: Hi all,I have a Terrasic DE10 Lite w/max 10 that I'm attempting to use a digilent PMOD I2S2 audio in/out board with. The example is for xilinx/vivado, so thats not going to be a straight one to one with quartus, but I was able to use the verilog from the example and generate a new project with system builder. The example was pretty straight forward, just looping the input to the output. All the clocks look correct (I used a PLL ip to make the master clock and the rest are derived from that) in Model Sim but I don't think I'm getting the input side correct. I used another I2S board with just output and was able to get audio out, so I think that portion is working correctly.My main questions revolve around the MAX10's GPIO pins used as inputs:Can I use other pins on the same bank as the output gpio pins as an input or would I need to put those on a different bank?When I define an input pin on the same bank as an output and measure the voltage on that pin, it's ~1.8 volts. Should I pull the pin to gnd if using it as an input? I thought the pin should read 0v if it was an input, I'm under the impression that it's not a great idea to push 3.3v into a pin thats already reading 1.8v but I'm not %100 clear on how the whole tri-state thing looks in practice.I'm definitely trying to err on the side of caution as I don't want to burn up anything, most of all the DE-10 Lite. They're not expensive, but they're not free either!Tips about GPIO as inputs would be greatly appreciated.

author: Vivis
author_rank: Contributor
timestamp: October 17, 2022, 01:18:14 am
content: Found some code from DigiKey that got the PMod I2S2 board to work with the DE-10 Lite:https://forum.digikey.com/t/i2s-pmod-quick-start-vhdl/13065This page is probably more informative than the page/datasheet from digilent. It got me up and running.

author: TomS_
author_rank: Frequent Contributor
timestamp: October 18, 2022, 07:09:58 am
content: I don't think I've heard of a concept of "input or output only banks" (yet), you are generally free to mix and match as desired. Sometimes the odd pin can be input or output only, however.Inputs are high impedance, so they shouldn't read any voltage (i.e. floating) unless there is some kind of pull up/down enabled within the chip or installed elsewhere on that signal.The voltage on an output may be determined by the family of logic it is configured as, and/or may depend on the voltage supplied to the VCCio (or equivalent) for the IO bank it lives in. It may also be a physical limitation of the chip whereby it can only supply a certain voltage on some pins.Unused inputs should generally be tied to something. It doesn't have to be ground, it can also be VCC. But they generally shouldn't be allowed to float. Sometimes, as hinted above, you can enable an internal pull up/down. Sometimes you can pull pins down to ground and use them as additional ground pins for the device, etc etc.This should all be covered in its datasheet, it may just take some bedtime reading to discover. 🙂
New Gowin IDE does not detect my DIY JTAG adaptor any more - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 04, 2022, 12:18:49 pm
content: Hi,I have a simple FT2232H JTAG adaptor that used to work with Gowin tools, I have updated my tools to the newest version and it does not recognize the Cable, Does anyone have the same issue? is there any work around?

author: hw
author_rank: Newbie
timestamp: October 05, 2022, 12:26:38 am
content: My RV Debugger Pro from Sipeed works with the latest Gowin IDE after flashing it's firmware to reflect "Dual RS232-HS" in it's product descriptor.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 05, 2022, 01:38:51 pm
content: Thanks for the update,Maybe it's the eeprom content attached to the FT2232H part, can you read the content and share it here?Also Is there any scheamtics for your board?

author: up8051
author_rank: Frequent Contributor
timestamp: October 05, 2022, 02:55:48 pm
content: RV Debugger from Sipeed is based on BL702. It emulate FTDI Chip.Full info:https://github.com/sipeed/RV-Debugger-BL702

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 05, 2022, 03:14:51 pm
content: QuoteThanks for the update, But the generic FT2232 has an external eeprom too, please try using FT_PROG tool from FTDI website, to see what you would get from reading the EEPROM, (the EEPROM should be emulated insfotware there)

author: hw
author_rank: Newbie
timestamp: October 06, 2022, 06:16:01 am
content: Here's the content from the source code:Code:const uint16_t ftdi_eeprom_info[] ={0x0800, 0x0403, 0x6010, 0x0700, 0x2D80, 0x0000, 0x0000, 0x0A9A,0x1CA4, 0x0000, 0x0000, 0x0000, 0x0046, 0x030A, 0x0046, 0x0054,0x0044, 0x0049, 0x031C, 0x0044, 0x0075, 0x0061, 0x006C, 0x0020,0x0052, 0x0053, 0x0032, 0x0033, 0x0032, 0x002D, 0x0048, 0x0053,0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x368D};

author: mon2
author_rank: Frequent Contributor
timestamp: October 06, 2022, 11:45:51 am
content: @ali, as a test, does your tool function with the older programmer version?Test with a short USB cable. Confirm device manager shows the device. Try a slower clock speed in the programmer tool configuration.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 06, 2022, 09:44:28 pm
content: QuoteThanks for the feedback.QuoteYes, Actualy it's a digilent HS2 Clone, and it's working nicely with xilinx tools and older version of Gowin software.
Zynq Ultrascale+ RFSoC data converter port help - Page 1
Forum section: electronics / general

author: knight
author_rank: Regular Contributor
timestamp: September 22, 2022, 11:00:00 am
content: Hello. Can anyone help me understand the port functions of the RF data converter IP? I tried reading the product guide but it is badly written in my opinion.I have attached the IP block and the settings configuration. So, the adc_clock is 2GHz and AXI_stream_clock is 250MHz. What exactly is axi_stream_clock? Is it the frequency at which FPGA fabric will communicate with RF-ADC? If not, then what is the FPGA frequency required.Need help with understanding these ports: sysref_in, s_axi_clk, m0_axis_aclk, clk_adc0 and irq.Link to product guide:https://docs.xilinx.com/r/en-US/pg269-rf-data-converterThanks.

author: Mario87
author_rank: Frequent Contributor
timestamp: September 22, 2022, 12:08:03 pm
content: Reference clock is just that...an external clock used as a reference, what speed is the oscillator on your board?axi_stream_clock is the clock speed of the data stream within the FPGA fabric itself.sysref_in - not checked the product guide, so not sure, but try clicking on the + to expand and see what is there, it might give you a clue.s_axi_clk - slave AXI clock, this is the clock at which the blocks within your FPGA fabric will operate at to communicate to one another and send basic information back and forth (like commands to adjust operational modes from the CPU), this in particular is a slave input and would connect to a master of some other device (CPU for example).m0_axis_aclk - Master AXI Stream Clock, this is the clock speed of your actual data stream within your FPGA fabric, like for example with HD video this might be 148.5MHz, but your AXI clk for comms between modules might be something differentclk_adc0 - This looks like the clk speed of your ADC?? Not checked the manual, but I would say a pretty safe guessirq - Interrupt Request
Synchronizing intermittent clock sources - Page 1
Forum section: electronics / general

author: bonelli
author_rank: Contributor
timestamp: September 19, 2022, 02:18:38 pm
content: Hello,I have 2 reference clocks, both are precise (+/-1µs) and give pps output. They suffer from different problems:- The first one is intermittent (GNSS PPS signal)- The second one is intermittent and also sometime strongly wrong: every few minutes, 5-6 consecutive pulses are far away from the "reference" clock. They are so wrong that they are easily detectable (error in tenth of µs to tenth of ms).Adding a good TCXO in the loop, it must be possible to build something that always give a PPS, switching between the 2 external clock sources when available and falling back to TCXO when needed.I need a precision in the µs range.I'm more familiar with CPU than FPGA but I believe that for this application, a tiny FPGA will be more appropriated.To your opinion, what will be the best approach: classical logic using counters and basic logic blocks, or a more smarter design using PLL?Thank youRegards

author: ejeffrey
author_rank: Super Contributor
timestamp: September 19, 2022, 06:51:32 pm
content: Yes this is totally feasible. A small FPGA would be an easy way to implement this. Is the second pps source also ultimately linked back to GPS time? Or can it skew arbitrarily over long enough time?The pps that is both intermittent and sometimes wrong is a bit of a concern. Your design should handle the case where the clock is missing for a while and then comes back with the first clock pulse is 10 us delayed. That won't necessarily be more than the tcxo could have drifted in the time it was off.One possibility is to consider if you can use an OCXO and if that would be stable enough to use only the GNSS system? Or does this have to work indoors where the GNSS signal can be missing quasi permanently?

author: bonelli
author_rank: Contributor
timestamp: September 20, 2022, 08:29:53 am
content: The second PPS source is contained in a few µs from the GNSS reference. It is intended to replace the GNSS PPS when working indoors (what will happens most of the time).OCXOs consume a little bit too much power...QuoteYes!Assuming I have already a STM32H7 on my design, a good implementation of the timers may also do the job.

author: tggzzz
author_rank: Super Contributor
timestamp: September 20, 2022, 08:57:18 am
content: Can I suggest you might like to define a few more points.How long does it take to determine that a pulse is actually missing? When is the missing pulse re-inserted, and does that time delay affect your application?If you have two sources of ppm pulses and the pulses occur, say, 456.789ms apart, how are they "combined" in a PLL?I suggest that detecting and ignoring spurious pulse that is "tenth of µs" away from expected pulse is not easy. That's 1 part in 107, which has implications for the lock-in time of a PLL.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 20, 2022, 08:12:09 pm
content: I'm pretty sure that was supposed to be 10s of microseconds because the overall resolution is only supposed to be +/- 1 microsecond
Nanoboard 3000 - Page 1
Forum section: electronics / general

author: Biggie
author_rank: Newbie
timestamp: September 13, 2022, 08:37:47 pm
content: So I recently bought a used Nanoboard 3000 for 85 eur and I cant get altium designer 9 (the one included on the CD) to recognize my Xilix 14 installation and I cant get any Xilix installation lower than that to work - I am on Win10. So I just end up with a "could not find Xilix ISE" error when I try to build. I know its an old board - I am a student and thought that this was a pretty good deal and accepted that it would be a challange to get to work. The altium support was very helpful by reminding me of my lacking license therefore I dont know what to do next. I tried using the newest altium designer and couldnt even get documentation on how to connect to the board - if it is even possible or I am just stupid. Do you have any ideas on what to do next? My last resort would probably be to make a win7 vm or install it on some laptop and try the lower versions of Xilix. I found some guy using Altium Designer as far as version 16 - will try that next. If you have any ideas - and know if for example if altium designer 22 is compatible with the nanoboard 3000XL then that would be extremely helpfull.If it isnt clear my only real HDL experience is logism and I never owned a fpga before :|
Programmer Suitable for both EPROMs and GALs  - Page 1
Forum section: electronics / general

author: ChewChew
author_rank: Contributor
timestamp: September 04, 2022, 06:00:53 pm
content: Hey,Can anyone suggest a budget device that can program GALs (16V8x, etc) and EPROMs (27C160, 27C400, 27C800, etc) if one exists?My Google foo is failing me just throwing up random programmers suited to just PICs, AVRs and such.The TL866 looks promising, but on closer inspection I see it doesn't natively support the size of EPROMs I'm using. There are third party adapters for the EPROMs, but they aren't a great solution in that you need to program the EPROMs in segments which is a bit clunky.This is a call for suggestions before I whiz down to AliExpress.Thanks in anticipation.

author: oPossum
author_rank: Super Contributor
timestamp: September 04, 2022, 06:31:15 pm
content: There is some support for 27C160, 27C400 and 27C800 in the new T48 (TL866 successor)http://www.xgecu.com/MiniPro/T48_List.txt

author: TomS_
author_rank: Frequent Contributor
timestamp: September 05, 2022, 06:56:13 am
content: I know someone with a Wellon VP798 who programs things like 27C322 EPROMs as well as GALs. I think it's a more e expensive programmer compared to the TL866 et al, but perhaps worth a look at to see if it works for you.

author: ChewChew
author_rank: Contributor
timestamp: September 13, 2022, 10:51:19 am
content: Hi just a quick note to thank TomS and oPossum.I went for the T48 and also ordered the XGecu 27C adaptor which is needed to program the 27C EPROMs. Although the adaptor was almost 50% the price of the T48 its a much better solution than that for the TL866 because you can program the 27C EPROMs in one go Vs in banks when using the adaptor for the TL866.It arrived within one week and I am happy with its performance so far.
A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs - Page 1
Forum section: electronics / general

author: llkiwi2006
author_rank: Regular Contributor
timestamp: April 19, 2020, 03:18:20 pm
content: https://www.usenix.org/conference/usenixsecurity20/presentation/enderQuoteEpic fail by Xilinx?

author: amyk
author_rank: Super Contributor
timestamp: April 20, 2020, 02:56:59 am
content: Epic win for everyone else.

author: brucehoult
author_rank: Super Contributor
timestamp: April 20, 2020, 04:39:12 am
content: Quote from: amyk on April 20, 2020, 02:56:59 amWould love to be able to use Open Source tools on my Arty / Zynq boards!

author: llkiwi2006
author_rank: Regular Contributor
timestamp: April 20, 2020, 12:45:15 pm
content: Quote from: brucehoult on April 20, 2020, 04:39:12 amThere seems to be good progress on that with the SymbiFlow project, although not directly related to bitstream encryption. What we can get out of this is being able to modify / create custom bitstreams for products that employ bitstream encryption. Which I reckon is still a win for open source.

author: asmi
author_rank: Super Contributor
timestamp: April 20, 2020, 01:34:00 pm
content: Quote from: brucehoult on April 20, 2020, 04:39:12 amWhat does bitstream encryption have to do with OS tools? This is an optional feature which I'm yet to actually see used in the field.

author: gnuarm
author_rank: Super Contributor
timestamp: September 24, 2022, 06:41:50 pm
content: I'm not sure I understand the significance of the second part, that the key is in the encrypted bit stream. This key can only be read if you can "circumvent the encryption mechanism". Isn't that the point? If you can circumvent the encryption mechanism, do you care about the key? I guess decrypting the bitstream "only" allows you to read the existing bit stream, while having the key lets you load a new one?

author: kmike
author_rank: Regular Contributor
timestamp: September 26, 2022, 08:30:41 am
content: 1.: You can decrypt the whole bitstream and make clones of the device.2.: If you can forge the HMAC, you can load a manipulated bitstream to the FPGA. This way you could install a backdoor, or change the program (in BRAM) of an instantiated CPU. If the manufacturer of the device using a compromised FPGA would use the same keys for all devices manufatured (very common...), you could make a malicous firmware update and install it where you can...br,kmike

author: NorthGuy
author_rank: Super Contributor
timestamp: October 01, 2022, 04:18:00 pm
content: If you want the key, there's a different, older method, which involves sniffing current with EMI probe. This doesn't require access to JTAG pins. Once you have the key, you can build and sell any number of fake devices which will work with manufacturer's bitstreams, so they will be indistinguishable from the originals.
Xilinx ISE Design Summary Is Blank? - Page 1
Forum section: electronics / general

author: hal9001
author_rank: Regular Contributor
timestamp: September 09, 2022, 11:11:18 am
content: Im working on a new Xilinx ISE project. The top level .v file is in the project folder but some .v files are added from other folders outside of project folder. The design synthesis and implements but the Design Summary is blank and shows "Implementation State:New" similar tohttps://support.xilinx.com/s/article/38702andhttps://support.xilinx.com/s/question/0D52E00006hpSqqSAE/launching-design-summaryreport-viewer-emptyChanging the top level module to another module like suggested by xilinx and then changing it back does not work. I tried removing the top level file and added it back with no help.Any ideas what to do to fix that?Cheers!

author: rstofer
author_rank: Super Contributor
timestamp: September 09, 2022, 11:11:33 pm
content: Do you have inputs and outputs defined in the top module and are they carried through to the constraints file?If the logic doesn't do something to/from the outside world, it will be eliminated by the synthesizer.

author: hal9001
author_rank: Regular Contributor
timestamp: September 10, 2022, 12:45:37 pm
content: Quote from: rstofer on September 09, 2022, 11:11:33 pmYes all are defined and in the constraints file.I fixed this by renaming the top level file then adding this to the project again.
Error: I/O standard TTL is not supported for selected device family - Page 1
Forum section: electronics / general

author: GTT95
author_rank: Contributor
timestamp: September 06, 2022, 01:11:44 pm
content: Hello,After selecting EPM7256AETI100-7 with quartus 9, I'm getting this error. I am not aware of any settings where standard TTL could be defined as under "Device and Pin Options", Default I/O standard is set to 3.3V LVTTL.What could be the reason for this issue?Note: before selecting EPM7256AET, there was a device from MAX7000S family (which has standard TTL) selected.
Xilinx Schematic Capture  Additional building blocks? - Page 1
Forum section: electronics / general

author: CaptDon
author_rank: Super Contributor
timestamp: October 19, 2022, 05:25:32 pm
content: Xilinx schematic capture has some basic 74XX I.C. building blocks (pick-n-place so to speak). Is there a repository or library available for download where someone has expanded and added more basic 74XX or 4XXX parts to 'drop in'? We are working exclusively with the smaller CPLD devices for signal routing, latching, counting, etc. No one in house at this point is VHDL/Verilog literate but have been creating working sub-systems with Schematic Capture. Thanks!! (Due to several problems with platform cables not being recognized and the small scale of the CPLD's we use we are running ISE versions prior to the '14.X' release)

author: TomS_
author_rank: Frequent Contributor
timestamp: October 20, 2022, 08:00:26 pm
content: For simple logic like replicating 74/4000 series logic, Verilog is a piece of cake to learn. Really! You should just look at some basic examples of how to create counters, shift registers, combinatorial logic, etc.I think I picked up the basics in an afternoon, and can now string together much more complicated logic without being restricted to what was available in those logic families.I have no experience with VHDL, but I'd imagine for simple logic it would also be very easy to learn.And if ISE is anything like Quartus, then it should be able to show you a "schematic" version of your Verilog/VHDL, so you can still compare it at that level.
Two Frequency Dividers on a GAL16V8 - Page 1
Forum section: electronics / general

author: ChewChew
author_rank: Contributor
timestamp: August 29, 2022, 03:01:04 pm
content: I’m very new to WinCUPL and PLDs. My only previous experience with logic was over 20 years ago at uni using Xilinx FPGA so forgive me if I’m missing something obvious.I’m attempting to implement two independent frequency dividers on a 16V8. I see from the datasheet that all the D flip flops on the chip share the same clock so I tried implementing a simple D type using the logic array. This seems to work in simulation, but when I feedback nQ to D to make a toggle I get both compilation and WinSim errors.A few days of struggling and Googling hasn’t helped. Much of the WinCUPL stuff I can find is pretty basic.Has anyone got any hints or tips they can share?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: August 29, 2022, 03:04:33 pm
content: The global clock makes GALs rather limited for some applications - what sort of frequencies and divde rations are you trying to get ?

author: ChewChew
author_rank: Contributor
timestamp: August 29, 2022, 03:09:15 pm
content: Sorry, I should have included this - 1MHz and 7MHz. Both /2

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: August 29, 2022, 03:15:00 pm
content: Quote from: ChewChew on August 29, 2022, 03:09:15 pmIf the sources are asynchronous then you can't easily do it in one device. You probably could do 0.5 and 3.5 from a common 7M source though.I suppose you may be able to implement an independent DFF in async logic for one of them, but an external HC74 may be a better solution.

author: ChewChew
author_rank: Contributor
timestamp: August 29, 2022, 03:52:15 pm
content: This is what I’m trying to recreate.It's a HD PC FDD modified to work in an Amiga. The trick required to get it working with HD floppies is to send a 32 bit sequence (0101….) clocked by drive select to identify a HD disk has been inserted and to halve the motor driver frequency when reading the disk. Hence the need for two independent dividers.I’ve got this working using a couple of 74 series ICs on a breadboard and now looking to migrate to a neat small package.Owners of these FDDs advise the device is a 16V8. I have a few spare, so I took on the challenge......
Resources for learning the FPGA implementation process in detail - Page 1
Forum section: electronics / general

author: Arsh ahmad
author_rank: Regular Contributor
timestamp: September 18, 2022, 07:04:18 am
content: Hi there,I am new to FPGA Programming and I am currently using the Vivado Tool, But want to learn about the complete FPGA Implementation process in detail I read the Runme.log files to understand the process but I am not able to understand the process from there. And I am also not able to find any detailed documentation. It will be very helpful if I can get detailed documentation or resource regarding the implementation process.

author: rstofer
author_rank: Super Contributor
timestamp: September 19, 2022, 05:57:32 pm
content: Xilinx has large documents on just about every topic that could possibly come up.Here is a concise 298 page document on Vivado Synthesis - there are many other documents, you just need to search around.https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2021_2/ug901-vivado-synthesis.pdfhttps://docs.xilinx.com/r/en-US/xilinx-documentation-portal
Kria SOM Carrier with Dual FMC? - Page 1
Forum section: electronics / general

author: frasdoge
author_rank: Contributor
timestamp: August 17, 2022, 03:10:34 am
content: Hi, I'm taking a look at the Kria SOMs at the moment to create my own carrier for an SDR project.I would need to be able to fit 2 FMC connectors to interface with an RF front end I have in mind,the FMCOMMS5. For that I'd need 160 user IO pins by the looks of it.However, taking a look at theSOM datasheetit looks like there's only 127, the rest are hooked into PS via MIO.Am I simply out of luck on this front? Is there an alternative / competitive SOM that will do the job for me? I'd like to keep similar or better available resources if possible, but I'm not sure there's anything close to being cost competitive to the Krias.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: August 26, 2022, 06:05:30 pm
content: Do you need an Ultrascale+ part, and a Zynq SOC? Or can you live with a Kintex-7 FPGA?Is this for personal/hobby use only? Or are you looking to develop a commercial product?The Analog Devices board is already $1300+.ULTRAZED-EG4 seems to fit the bill. It's about $600.Also, it is likely that the AD board is not using all IO pins on the FMC. You don't need to connect those.
Texas Instruments Bipolar TIBPALs Programming Algorithms - Page 1
Forum section: electronics / general

author: Beta_vulgaris
author_rank: Regular Contributor
timestamp: August 17, 2022, 10:10:22 am
content: You can find them by Googling ti.com for "inurl:hirel/mltry".

author: Beta_vulgaris
author_rank: Regular Contributor
timestamp: August 25, 2022, 03:47:44 pm
content: Also, TICPAL devices! 22V10 and 22V10Z.
ICE65 software (ICEcube2 Version 2012-03) for ICE65L04F-TCB132C FPGA - Page 1
Forum section: electronics / general

author: kipper2k
author_rank: Newbie
timestamp: August 19, 2022, 05:37:21 pm
content: Hi All.I bought some of the ICE65 BGA FPGAs for a project not realizing how old these chips are. They were originally made by Siliconblue and then sold off to Lattice. Lattice has abandoned them and they do not support them at all now, not even entertaining requests to the support staff.So, the issue is i cannot find any software to develop/program these things. Apparently the software required is ICEcube2 Version 2012-03 or Older, anything newer does not support the ICE65. Lattice archive goes back to 2012-09 which does not support the ICE65. Does anyone have or know where i can obtain it..Many thanks

author: mon2
author_rank: Frequent Contributor
timestamp: August 25, 2022, 09:31:48 am
content: See if the attachment helps.
Gowin GW1NSR-LV4C - using CM3 with HperRAM ref design - Page 1
Forum section: electronics / general

author: mon2
author_rank: Frequent Contributor
timestamp: August 19, 2022, 11:57:38 am
content: Hi. Anyone manage to synthesize the factory ref design that is for the CM3 + HyperRAM ?MCU -> Keil code compiles fine.FPGA -> Gowin_EMPU(GW1NSR-4C)_V1.1.2\Gowin_EMPU(GW1NSR-4C)_V1.1.2\Gowin_EMPU(GW1NSR-4C)_V1.1.2\ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_QN48P_V1.1\gowin_empu_hyperramfails with 'Multiple GSR are initiated'factory ref designs can be downloaded from here:https://we.tl/t-qjwmIgavaqThe fault is linked to their encrypted EMPU IP. Had previously a VCO out of range error from the same project but resolved it by updating our EDA to the current 1.9.8 version that is on their website.Why would a known good factory ref design fail to synthesize ??Welcome any pointers. Thanks!

author: FlyingDutch
author_rank: Regular Contributor
timestamp: August 19, 2022, 03:47:58 pm
content: Hello,Has you seen these blog and github repo:https://justanotherelectronicsblog.com/?p=986https://github.com/riktw/tang4KramblingsMight be helpful in this subject.Best regards
In Verilog, is it possible to define XXX only if a parameter is set? - Page 1
Forum section: electronics / general

author: BrianHG
author_rank: Super Contributor
timestamp: August 16, 2022, 11:39:52 am
content: In Verilog, is it possible to define XXX only if a parameter is set?I have a bunch of portions of my code where I include or exclude using `ifdef XXXX, `else XXXX, endif.However, instead of globally `define XXXX, for each instance of my module, I wish for that `define to be turned on or off based on a parameter. Is there a way to do this?

author: cruff
author_rank: Regular Contributor
timestamp: August 16, 2022, 12:43:33 pm
content: Not sure what you need to accomplish, but can you just use a regular parameter and use if statements within a generate block and test for parameter equal to zero or not?

author: BrianHG
author_rank: Super Contributor
timestamp: August 16, 2022, 01:07:24 pm
content: That will only work for code I have inside the 'generate' & 'endgenerate'.I have too may little snipets of code all over the place which are either there or not there depending on the option of the `define.I'll stick with the good old `define for now unless I want to re-engineer the code.My other choice is to have 2 version of the module, 1 with the enhanced features, one with the vanilla layer.

author: langwadt
author_rank: Super Contributor
timestamp: August 16, 2022, 01:26:15 pm
content: Quote from: BrianHG on August 16, 2022, 01:07:24 pmmake a file that contains `define XXXX use generate and param to conditionally include that file where you need it?

author: Bassman59
author_rank: Super Contributor
timestamp: August 16, 2022, 02:40:32 pm
content: Quote from: BrianHG on August 16, 2022, 01:07:24 pmWith VHDL, you could create two (or more) architectures for one entity, and select which one is used with a generic or a configuration. Just sayin'.
Found Xilinx XC9500/XL CPLDs Programming Algorithms from Xilinx - Page 1
Forum section: electronics / general

author: Beta_vulgaris
author_rank: Regular Contributor
timestamp: August 27, 2022, 09:59:37 am
content: From AppLINX CD-ROMs. Also, XC17V00 configuration EEPROM for FPGAs.

author: DiTBho
author_rank: Super Contributor
timestamp: August 27, 2022, 11:23:45 am
content: outstanding!!!thanks!!!

author: YetAnotherTechie
author_rank: Regular Contributor
timestamp: August 30, 2022, 02:46:31 am
content: Thank you!Apparentely files named Add.dat and/or address.dat are also necessary, do you have them?

author: Beta_vulgaris
author_rank: Regular Contributor
timestamp: September 03, 2022, 09:45:15 am
content: Quote from: YetAnotherTechie on August 30, 2022, 02:46:31 amNot included in the CD-ROM.
FPGA based unknown circuit application - Page 1
Forum section: electronics / general

author: mo.glmdi
author_rank: Newbie
timestamp: August 28, 2022, 05:40:31 am
content: Hello Everyone.I'm analyzing a piece of circuit that have FPGA in its core to understand its operation. But I've encountered a part of this circuit that I have no idea about it. There is an input signal from a pick-up coil with 2.5V offset DC after amplification stage and a comparator that compare this signal with a 2.5VDC reference voltage and outputs a pulse train that just fluctuate like a noise. I'm wondering what is the main idea behind this section? Is it for noise removal? If yes, What is the main algorithm to do this?I attached the schematic of circuit in this post and really appreciate if anyone can help me to resolve this problem.

author: hamster_nz
author_rank: Super Contributor
timestamp: August 28, 2022, 06:13:11 am
content: This is most likely the error signal in a control loop. The signal is ikely to be samples and filtered to generate the error term..

author: mo.glmdi
author_rank: Newbie
timestamp: August 28, 2022, 07:04:36 am
content: Thanks @hamster_nz . I think so. It can be an error predicting routine for removing error or noises and finally reaching higher resolutions in pick-up coil signal. But I have no idea about existing algorithms and methods. Do you have any thought about methods of such control loop?

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 28, 2022, 08:07:35 pm
content: You may or help us figure out what this signal is for if you told us what this coil is picking up exactly. Maybe a partial schematic or something.
Video Upscaling and Overscan - Page 1
Forum section: electronics / general

author: Mario87
author_rank: Frequent Contributor
timestamp: August 09, 2022, 06:46:54 am
content: Hi all,I am working on a project where I am taking in a 720x576, 50Hz, interlaced video feed and then de-interlacing and upscaling to 1920x1080, 60Hz, progressive video to be output over HDMI.I have used the Xilinx VPSS IP and I have this working really well at the moment. However, the device I am capturing video from is from an era of CRT displays, so there is significant overscaling which results in a black border all the way around the screen.The systems does not have a DE (active video) signal to feed into the 'Video In to AXI Stream' IP, so I am using the VBLANK & HBLANK signals to tell the IP when the active video is available using the following logic:active_video <= ~vblank & ~hblankHowever, I can see that to fix the overscaling issue I need to use some other method to identify to the 'Video In to AXI Stream' IP where the active video I want to display actually is.What I was thinking is to generate my own custom VBLANK & HBLANK signals by looking for a fixed point (beginning of HBLANK for example), then counting clock cycles, setting my custom HBLANK high when I need it, counting clock cycles while high, then setting it to low when I no longer need it and repeat.The same could also be done for VBLANK.Is that a sound way to go about this, or is there a different, more efficient way? With my way it just relies in a single known point such as HBLANK / VBLANK going high for 1 time, then after that it is just counting clock cycles over and over.Any thoughts / suggestions appreciated!

author: NiHaoMike
author_rank: Super Contributor
timestamp: August 09, 2022, 01:44:39 pm
content: For VBLANK, you'll want to count HSYNC pulses instead, but you got the general idea.
DINI Group DNV7F2A - Page 1
Forum section: electronics / general

author: Foxxz
author_rank: Regular Contributor
timestamp: August 11, 2022, 04:05:20 am
content: I came into a neat piece of ASIC prototyping hardware - the DINI DNV7F2A system. I've found brochures for it and seen a few videos of the support software interfacing with it but can't find much more on it. Anyone know where I can get docs or software for it? It seems like its not an uncommon piece of hardware in engineering circles.Much thanks.
New Zynq based SOM  - Page 1
Forum section: electronics / general

author: Boscoe
author_rank: Frequent Contributor
timestamp: July 24, 2022, 09:31:38 pm
content: I just came across a new product of Octavo Systems called the OSDZU3. It looks great and one of the only SoMs that can be incorporated into compact, portable electronics as existing SoMs tend to be at the PCB scale. Sure this SoM is a PCB however is similar in surface area to a large packed FPGA.What do you guys think? I expect the price to be around €300 but that’s really a guess.https://octavosystems.com/octavo_products/osdzu3/

author: Someone
author_rank: Super Contributor
timestamp: July 24, 2022, 10:54:23 pm
content: Still a BGA package, so its mostly saving the cost/area of routing the DDR (+ new design risks). Would have to be pretty cheap to compete with a bare chip.