MOSFET inductance - Page 1
Forum section: electronics / beginners

author: Shocker
author_rank: Contributor
timestamp: October 14, 2015, 01:55:37 pm
content: Hi,I've read from multiple sources that the source inductance of a MOSFET package counteracts the dv/dt of the gate? Which, slows down the rising and falling edges, and reduces the overshoot and oscillations observed on the output. In one particular paper, i read that the gate inductance is reduced by the same magnitude of the source inductance. Ie. Inductance at gate = Lg-Ls. How does this work?I know that an inductor restricts AC signals from passing through it and therefore the source inductance would limit the magnitude of di/dt. But would this reduce overshoot and ringing? Also, does the drain-source reflect on the gate of the MOSFET? I know that electrically the gate and the drain-source are isolated but if the drain-source is oscillating, would this somehow reflect on the gate? And if so, how?Also, i've read that the source path provides negative feedback to the MOSFET. How does this work? I thought feedback in any shape or form had to be combined with the input signal?The circuit that was shown in the paper was very similar to this.Thanks

author: Performa01
author_rank: Super Contributor
timestamp: October 14, 2015, 03:02:54 pm
content: Think of the most popular negative feedback scheme for BJTs - the emitter degeneration.Now as a first step, replace the emitter resistor with an inductor. You now get a frequency dependent feedback, i.e. you get an active 1st order lowpass frequency response.As a second step, just replace the BJT with a MOSFET, and there you are...The FET source inductance is in series with the input signal (so Vgs will be the sum of the two) and there is the source current flowing through the inductor. The voltage drop across this inductance will be subtracted from the gate voltage, as the current through the FET is out of phase with regard to the input signal. This is clearly a frequency dependent negative feedback, lowering the gain for higher frequencies. Thus it can be expected that high frequency phenomena like overshoot/ringing will be reduced accordingly.

author: Shocker
author_rank: Contributor
timestamp: October 14, 2015, 04:54:07 pm
content: Quote from: Performa01 on October 14, 2015, 03:02:54 pmI'm not familiar with the emitter degeneration. I've just had a read of it, the impression that i get is that it alters the gain of the transistor with frequency due to the impedance of the emitter capacitor.Does the source inductance of the MOSFET form a first order filter with the impedance of the MOSFET?The inductor is in series with Vgs because of the current loop? Regardless of the fact the Vgs and the inductor is connected to ground?May you explain why the current through the MOSFET is out of phase of the input signal? Because the source inductance adds a phase shift?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 14, 2015, 08:58:51 pm
content: The equivalent input impedance of a follower, at high frequencies (near the cutoff frequency of the device, typically limited by node capacitances, and variously by device geometry (e.g., gate spreading resistance in MOSFETs) or physics (recombination in BJTs)), is roughly a 90 degree rotation of the common terminal (source/emitter) impedance. Resistor shifts to capacitor; inductor to resistor; capacitor to negative resistor. (The last one is why gate damping resistance is often desirable. The source might not be capacitive as such, but a sufficiently low impedance can look the same way, giving rise to a negative input resistance at unlucky frequencies.)Tim

author: Performa01
author_rank: Super Contributor
timestamp: October 15, 2015, 08:42:52 am
content: Sorry if my answer was a bit sloppy...Let's start with the basics of a (N-)FET.1) The drain current is a function of the voltage between gate and source: Id = f(Vgs);2) The source current equals the drain current - it is actually the very same current.If you have a resistor from source to circuit common, and the input voltage is between gate and common, then the FET will see the difference of the input voltage minus the voltage drop on the source resistor: Vgs = Vi - Vrs;Since the voltage over the source resistor depends on the drain (=source) current: Vgs = Vi - Rs * Id;That means that a part of the output signal is subtracted from the input, which is one of several ways to implement negative feedback.That's what I wanted to express by 'out of phase', but it was not correct as the signal at the source pin actually is in phase with the input signal, absolutely speaking, but it still subtracts - hence 'out of phase' - with regard to the gate/source terminals, i.e. the actual control voltage for the FET.Anyway, by subtracting a part of the output signal (=output current that is converted to a voltage by means of a resistor) from the input signal, thus reducing the control signal Vgs, we reduce the effective gain of the stage. This is not the only effect, we also increase input and output impedances, make the transfer curve more linear and increase the bandwidth - but that's only as a side note.Now if we combine the resistor with a reactive element, capacitor or inductor, we make it frequency dependent. In case of an inductor (there is no explicit resistor, but the inductor will have some losses and the FET itself has some intrinsic resistance too) the total impedance in the source line rises with frequency, so the negative feedback gets more effective at higher frequencies as well. As a result, there is no negative feedback at all at DC (=steady state), but at AC (transitions) the gain drops with frequency.For squarewave pulses, the entire high frequency content sits in the transitions, this is why we suppress overshoot and ringing by smoothing the edges if we reduce the gain at high frequencies.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 15, 2015, 11:31:47 pm
content: This is true for asymptotically low frequencies, when the source inductance is quite large and the reactance is dominant over its series resistance and other nearby impedances.However, at the high frequency limit (perhaps >30MHz for most general purpose parts and circuits; mind this is a very loose, circuit-dependent figure), your very first assumption is already blown out: source current is the sum of drain and gate currents. Cgs ~= Cds ~= Cdg, perhaps ~10pF e.g. for a PN4392 (so Xc is on par with 1/Gm by, oh, 50-100MHz or so). It is this contribution that gives weird impedances at the input.Tim

author: Performa01
author_rank: Super Contributor
timestamp: October 16, 2015, 09:30:14 am
content: Quote from: T3sl4co1l on October 15, 2015, 11:31:47 pmYou're undoubtedly correct on that.The particular impedances presented by the transistor terminals at high frequencies are a somewhat tricky business however, and I'm not sure if it makes much sense to discuss these effects when the op is not yet familiar with the most basic feedback principles like emitter degeneration.You already started giving some clues in your first post; I just doubt the op would make too much sense of it before digesting some of the more basic principles of transistor operation.