Overcoming BGA FPGA, perhaps... - Page 1
Forum section: electronics / general

author: Chris Mr
author_rank: Regular Contributor
timestamp: January 28, 2021, 10:45:14 am
content: BGAs are such a pain. I've ended up making a vapour phase reflow oven which guarantees they solder properly.And then I was struck with an idea, which needs more thinking about, but worth a mention as someone will likely tell me it's already been done..If I were to make say 6 layer boards with the FPGAs and power supplies already on, ready to mount into a SODIM (204 pin) connector, that would make it easier for anyone to add FPGA to their projects, because the SODIMM pins are 0.6mm apart (easier than LQFP).I was thinking that the power supply input might be via something other than the SODIM, like a 0.1" header / flying lead (not sure yet).The other side benefit being that the complicated task of getting all the pins out is in a relatively small package. The "user" board could then get away with 2 layers (maybe) but certainly 4.I've been using LFE5U (Lattice) which have 64 pairs of LVDS (going at 800MBPs!) which are ideally suited to this approach.I suppose the next problem is going to be that each application requires other things adding (SDRAM for example) which starts to make it more complex / expensiveJust an idea at the moment....

author: Berni
author_rank: Super Contributor
timestamp: January 28, 2021, 12:06:31 pm
content: Congratulations you have just re-invented SOMs (System on module) such as thishttps://www.criticallink.com/product/mitysom-5csx/In reality BGAs are not quite as horrifying as it might seam. If you use the largest 1mm pitch BGA package then you can use one of the standard cheep 4 layer boards from PCBWay or JLCPCB. The vias fit in there no problem and the layers are enough to get a sizable amount of IO out of it (As long as you don't need to utilize almost all the pins)Soldering them down is also not as hard as a lot of people think. Order the 10$ solder paste stencil with the board to paste up the board, place the BGA down and run it trough the regular toaster-y reflow oven.You can get things done with 0.8mm pitch BGAs too if the footprint is reasonably friendly. The ones that are to avoid at all costs for DIY are the 0.65mm, 0.5mm, 0.4mm etc... chips that are a huge pain in the ass to deal with. The boards for it are ridiculously expensive for prototypes and its not easy to reliably solder them.

author: Chris Mr
author_rank: Regular Contributor
timestamp: January 28, 2021, 12:21:49 pm
content: Yes Berni, like a system on module, but not a complete system, just the BGA (and power supply).In the opposite way, not expensive either..If it's so easy to make BGA PCBs, why aren't there lots of them out there?ECP5's are 0.8mm. I use a template made of PCB with accurately cut square holes for the BGA parts to "sit into" when assembling prototypes. The template needs to be 0.5mm above the PCB to avoid the solder paste. You get no alignment issues that way, and just two holes in the PCB to align the two. I put the BGAs on first with the jig and then the rest of the bits after.

author: asmi
author_rank: Super Contributor
timestamp: January 28, 2021, 12:36:53 pm
content: Quote from: Chris Mr on January 28, 2021, 12:21:49 pmHmm what? There are lots of them out there. I've soldered 100's of BGAs and so far hadn't had any issues with them. Which is why I strongly disagree with the premise "BGAs are such a pain." To me QFNs cause much more grief. I will take BGA over QFN any time.

author: Berni
author_rank: Super Contributor
timestamp: January 28, 2021, 12:43:31 pm
content: Quote from: Chris Mr on January 28, 2021, 12:21:49 pmWell this is what SOM modules are. The BGA chip + everything needed around it to make it run (PSU, Clocks, Boot memory, Reset..etc) Its just that often they also include RAM on these modules because its a pain to connect yourself (needs a huge number of pins, uses up a lot of potential GPIO on the SODIMM, possibly needs length matching) and a lot of the small size RAM chips in the megabytes or low gigabytes are cheap anyway (In the range of a few dollars per chip)But yes these SOMs typically are not very cheep since a lot of the times the FPGA chips on there are pretty expensive themselves and the company making them typically doesn't sell them in huge volumes, so they have a high profit margin to recoup the development costs quicker.Quote from: Chris Mr on January 28, 2021, 12:21:49 pmYep did ECP5s and MachXO2 from Lattice before. No fancy alignment jig needed. All you need is placing markers in the corners of the chip on the top copper layer of the PCB. Just place the chip on there and check under magnification that the corner lines up on all sides.I also replaced a 0.5mm BGA chip on a board by hand before. It had no PCB markings to let me align it to. So i placed the board under a camera microscope, placed markers on the screen where the corner PCB pads are, then placed the chip on top, making sure the corners are all the same distance from the marked pad locations. Take a hot air gun to reflow it while checking the microscope to see that it is still aligned and done. Worked a treat, granted it was a fairly small 64 pin BGA, not the 1000+ pin monsters that big FPGAs come in.You do see people doing large BGAs at home there or there. But it is rare since its still a BGA in the end. More difficult to route, more difficult to solder, impossible to properly inspect, impossible to probe the pins etc. So one would still use a more regular package such as a TQFP or QFN if at all possible. One would only go BGA if you really can't find the chip you need in any other package, but if you have to it can be done. Certainly takes more skill than soldering a SOIC, but a lot of people who have lots of SMD soldering experience can do it, but it does look intimidating for sure.

author: Chris Mr
author_rank: Regular Contributor
timestamp: January 28, 2021, 12:57:08 pm
content: Well asmi, of course there are lots of BGAs out there, it's what large manufacturers do! But for someone wanting say a development board for ECP5 there are very few. Even fewer if you don't include the Lattice boards which force you to get the time limited development tools, because they're wired up for the SERDES.Part of the problem is that the development boards don't bring out lots of pins, just a few for playing with. The other part being that they commit some pins which you might want for your own design.It was, just an idea.I also wondered about 50 way (0.5mm) FFC connectors on each side of a square, with very short FFC cables they would fold under to take up the same footprint. A bit like a 200 pin LQFP.

author: Chris Mr
author_rank: Regular Contributor
timestamp: January 28, 2021, 01:05:35 pm
content: I would be interested, Berni, to find out how you make sure that the FPGA "goes down" flat, never moves (so that the solder paste doesn't smudge) etc.I found that one of the hardest parts without some other tool / jig.I have my own CNC milling machine so making the jigs is easy, and it's super quick to assemble. The part won't go into the hole until it's lined up and then it just drops in there.

author: Berni
author_rank: Super Contributor
timestamp: January 28, 2021, 01:26:27 pm
content: I just careful place it down with tweezers (Ones that open far enough to actually grab it properly). Its okay to move it around a bit after it is already down. Sure it smudges the paste around a bit but not that badly since the solder balls have a pretty small contact area. The little smudging that happens fixes itself upon reflow as the paste clumps together into a molten ball.What causes shorts is having too much paste on the pads. That can be caused by dragging the paste spreader over the mask too enthusiastically, pushing the paste down into the mask holes so much that it oozes outwards under the mask.

author: Chris Mr
author_rank: Regular Contributor
timestamp: January 28, 2021, 01:29:37 pm
content: I think I must be a bit shakeyIt'll be the beer that's the problem, either too much or not enough

author: asmi
author_rank: Super Contributor
timestamp: January 28, 2021, 01:57:17 pm
content: Quote from: Chris Mr on January 28, 2021, 12:57:08 pmWell, take a look at the project in my signature for example of a very simple devboard. I've designed it in KiCAD specifically to make it easy for beginners to design their own boards if they so desire. I've done all the hard bits (DDR2, PDS, HDMI and other misc connections which are required for FPGA to work), so that others can add other things they want without too much effort.I'm thinking about designing another board with 6G SERDES connections, but I haven't settled yet on what exactly I would like to have on that board.

author: asmi
author_rank: Super Contributor
timestamp: January 28, 2021, 01:58:25 pm
content: Quote from: Chris Mr on January 28, 2021, 01:29:37 pmYou don't have to be perfect with placement, BGA will self-align during reflow to some degree.

author: Berni
author_rank: Super Contributor
timestamp: January 28, 2021, 06:06:46 pm
content: Yep, it's not critical to get the BGA spot on those pads. As long as you are within about 1/4 of the pin pitch you are fine. Just needs so that the correct ball is slightly touching the correct pad, then during reflow the surface tension pulls it over and centers it perfectly. Due to the large number of pins this surface tension can be surprisingly strong.Trust me once you do more work with FPGAs you will love having memory sitting there all ready to use. It's not like the memory chips are taking up any hugely valuable pins. Modern FPGAs come in huge pin count packages that give you many times more pins than you need, any special IO functionality is also spread out, so even if a RAM chip uses up some of it, there is still more of it remaining on some other pins.It's just that FPGAs are still a bit of a niche thing. They are not used in huge volumes because customers that want milions of a chip do also have the budget to order a custom ASIC for the job that costs orders of magnitude less than a FPGA. Hence why there are so few FPGA vendors that put so little effort in actual development (Hence why HDL languages are sort of stuck in the 1980s) and they have to all sell expensive chips to be profitable. The electronics community has little interest in them because most projects out there can be done using a dirt cheap arduino or raspberrypi, so dev boards with FPGAs also don't exactly sell like hotcakes. It's simply a niche area of electronics that operates with the accordingly steep niche prices. Also militairy loves them so ChaChing $$$

author: langwadt
author_rank: Super Contributor
timestamp: January 28, 2021, 06:23:02 pm
content: Quote from: Berni on January 28, 2021, 06:06:46 pmXilinx recently announced they had passed 1 billion spartan devices sold. The HDLs used for FPGAs are the same as used for ASICs.making and ASIC carries risk because fixing any errors cost months of time and lots of money andthe NRE for modern processes are eye watering expensive, FPGA manufacturers can take advantage of the cheaper higherperformance modern processes and spread the NRE thin over many more devices

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 28, 2021, 06:46:34 pm
content: Yep. ASICs usually also have the edge for power consumption, max speed and system integration.But given the risks, except if you don't have a choice (for the above reasons), it often makes more sense to release the first version of some product with an FPGA, let it mature and iron out all the issues, and later on switch to an ASIC, when implementation is stable AND the device(s) using it actually sell well enough that you know exactly where you're going.

author: Berni
author_rank: Super Contributor
timestamp: January 28, 2021, 07:18:19 pm
content: Quote from: langwadt on January 28, 2021, 06:23:02 pmI'm not saying that "nobody uses FPGAs" and that every guy in a garage has ASICs made for them.But as soon as a big customer has a need for a chip that does a particular thing in volumes in the many milions the eyewatering NRE costs of an ASIC become cheaper than buying that many expensive FPGAs. This is why people did pay the big bucks for an ASIC that does something a FPGA could do too. Things like the bitcoin mining ASICs, the long line of Agilents MegaZoom digital oscilloscope ASICs, down to less prominent chips hiding deep inside consumer electronics like a PCIe to PCI bridge chip on a motherboard that wants to support PCI on a modern chipset without it. Things like a 2 lane MIPI to 4 lane MIPI video converter inside a phone because the SOC chip in there didn't have the matching number of lanes to drive the particular LCD display. All things a FPGA is perfectly capable of doing, but at the large volumes is simply not cost efective.So the people that end up buying FPGAs are people who operate in small volumes that could never justify the cost of developing an ASIC. These tend to be more niche products that also sell for high prices so these customers are prepared to pay $2000 for a single FPGA since it's still cheaper than making an ASIC. So the FPGA vendors are making chips for these kinds of customers at the prices they are prepared to pay.I can buy a $150 complete graphics card in retail that contains a GPU with 10 bilion transistors. While if i wanted to buy a FPGA in the similar sort of ballpark by transistor count (Tho does a lot less since yeah its a FPGA, not a ASIC) say a Xilinx XC7V2000T that is rumored to have 6.8 bilion transistors making up a rather beastly FPGA with 2000K LEs would cost me about $20 000 . The sorts of FPGAs i can get for 150 bucks are in the few milions of transistors. I can get a >500MHz ARM MCU from NXP at $10 in single piece quantity(despite distributor markup at these volumes) looking deeper than just digikey gets you a Linux SOC for that. The sort of FPGA i can get for $10 is pretty shit, those are the kind of FPGAs that are barely a step above being glue logic.Sure they sell a lot of FPGAs, but they don't hit the sort of volumes it takes to trigger a race to the bottom in price between vendors. For example, look at the kind of technology and precision manufacturing that goes into making a harddrive. Most other machines made to this sort of precision cost as much as a car or a house. Yet the large volumes and manufacturer competition has forced them to optimize the manufacturing process so much that you can buy a hard drive for 50 bucks in a retail store, and yet this is with the retail store's large profit margin, taxes, transport etc on top, the actual hard drive vendor managed to produce that harddrive for much less than that.

author: asmi
author_rank: Super Contributor
timestamp: January 28, 2021, 07:41:20 pm
content: Quote from: Berni on January 28, 2021, 07:18:19 pmAnd that is a GOOD thing. Race to the bottom rarely benefits customers.Quote from: Berni on January 28, 2021, 07:18:19 pmAnd what did it do to the quality of these products?You are looking at the wrong place. FPGAs biggest customers are military, aerospace and communications. And it just so happens that none of these customers really care about the price of components because their markups on a finished products are so insane. These kinds of customers want the best no matter the price. So if Xilinx can sell a chip for $50K, why would they want to sell it for $100? This is a boutique market, and it's much easier to serve it as opposed to mass-market.THIS is why Xilinx manager can come out on stage and announce with the straight face "affordable" devices for $600/each, and get away with it. Because we are not their customers. We only receive spoils from somebody else's table.

author: Berni
author_rank: Super Contributor
timestamp: January 28, 2021, 07:49:31 pm
content: Yep that is exactly my point. The only reason FPGAs are expensive is because the customers that use them have deep pockets.Hence why they are rare to be seen in DIY projects

author: asmi
author_rank: Super Contributor
timestamp: January 28, 2021, 08:00:38 pm
content: Quote from: Berni on January 28, 2021, 07:49:31 pmI don't think the price is the only reason, or even the most important one - at the end of the day, it is a general knowledge that FPGA vendors often give deep discounts and subsidize various development boards to make them more accessible (Xilinx even advertises other vendors' boards on their website!).I suspect device complexity is much harder obstacle. FPGAs have incredibly steep learning curve, and not many typical hobbyists can commit enough time and, frankly, attention/dedication to make it to the other side of that hump.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 28, 2021, 08:51:03 pm
content: QuoteFIY China always have a solution, for your recorded you can get Xilinx V7 @800USD in china, still high, but way under 6K-20K$ also I think the market for FPGA's would be in Chinese hands soon enough, while sleepy joe is in the office! Gowin and other Chinese FPGA manufacturers would do it for us, like they do it with WIFI and ESP series, like they do it with 8bit padauk and CortexA parts from allwinar etc.. they are behind the US tech, agreed, But their price strategy will defeat them some how and force the giants to lower their prices.Tough it may take another 10 years, but we will get there. At least I hope so.By the way I hope Gowin 28nm FPGA's that blueskull told us, would have SERDES and LUT's in the the order of 100K to 200K @ around 10$ each in single QTY

author: NorthGuy
author_rank: Super Contributor
timestamp: January 28, 2021, 09:53:28 pm
content: Quote from: Chris Mr on January 28, 2021, 01:05:35 pmI just use flux, no solder paste, so I can move it back and forth a lot until it fits perfectly. Perhaps this has long-term consequences, but my prototypes do not need to survive longer than 2 months, so that's not a big deal for me.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 29, 2021, 12:35:40 am
content: Quote from: NorthGuy on January 28, 2021, 09:53:28 pmI don't know if there are definite benefits of using solder paste as opposed to just using flux and letting the balls reflow on the PCB pads - they fill reflow anyway. With added solder paste, you're just adding more solder. Is the amount of solder in the solder balls enough to guarantee long-term reliability? (And yes for just prototypes it probably won't matter anyway, but I'm still wondering.)

author: asmi
author_rank: Super Contributor
timestamp: January 29, 2021, 12:44:39 am
content: Quote from: SiliconWizard on January 29, 2021, 12:35:40 amI think more solder means package will be higher away from PCB, which makes it less likely to receive mechanical damage from repeated temperature cycles (FPGAs can get pretty toasty), as well as less mechanical stress when PCB itself flexes (say when you connect something to a board, or when you push buttons).

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 29, 2021, 01:49:57 am
content: Quote from: asmi on January 29, 2021, 12:44:39 amIt will sit higher. Does that make it really better mechanically? What about QFNs then? Not sure if that really helps that much. Maybe.The point anyway is really about non-automated reflow. For automated reflow, you don't really have a choice. Stenciling solder paste over BGA pads like any other component is the way to go. Dispensing flux instead would be VERY unpractical, so this is not an option. And without added flux, this wouldn't reflow properly.One thing to note is that a lot of flux under the BGA will make a mess and will be very hard to clean too. So, that's another point against doing that for long-term reliability, as even with no-clean fluxes, it's not the best idea not to clean the boards at all IMHO. With solder paste, the amount of flux under the BGA is much smaller, and since the BGA indeed sits higher, it's also easier to clean.Another thing that comes to mind is that solder balls are mostly SAC these days (except possibly for very niche ICs), so they require a lead-free process (with higher reflow temperature). If you're using a leaded process, you may use leaded solder paste, which I think would then require a lower temperature overall (please correct me if I'm wrong though...) If you're not using solder paste, then you WILL need a lead-free temperature profile for sure.

author: langwadt
author_rank: Super Contributor
timestamp: January 29, 2021, 01:59:26 am
content: Quote from: SiliconWizard on January 29, 2021, 01:49:57 amafaiu it was at one point done by dipping the balls of the part in sticky flux, the amount of flux controlled by how deep the dip

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 29, 2021, 02:23:41 am
content: Quote from: langwadt on January 29, 2021, 01:59:26 amOh, I forgot about that. You're right, I remember having witnessed this too. I can't remember the details - isn't this what has to be done for flip chips with very fine pitch (such as 0.2 mm), for which stenciling solder paste would be nearly impossible?

author: gnuarm
author_rank: Super Contributor
timestamp: January 29, 2021, 06:24:14 am
content: Quote from: asmi on January 28, 2021, 07:41:20 pmNo the biggest market, the most profitable. Like luxury cars, they make more money on the biggest devices which is what the customers with deep pockets buy. They make the lower end devices because that is what they sell the most of providing the gravy with the meat.I worked for a test equipment company once and they were building a new box with a $15,000 Xilinx part they were only using 20% of! They wanted room to expand. Really. That and the box the FPGA went in sold for $100,000. They were only counting on selling 10 of them... ever.QuoteYes, but the boutique market won't last forever. Just like Intel's server market is shifting to ARM devices, the high end telecom market will jump in a minute when they find something more cost effective. At some point that will simply mean they don't need to continue to pay for bigger and bigger FPGA devices. Meanwhile the big dogs are ignoring the scraps at the low end and other companies are starting to come out of the woodwork. We'll see how this shakes out over the coming decade.

author: gnuarm
author_rank: Super Contributor
timestamp: January 29, 2021, 06:31:39 am
content: Quote from: Berni on January 28, 2021, 07:49:31 pmThey aren't all expensive. Lattice makes very affordable devices and some new Chinese companies are doing even better.I find it odd that FPGAs don't really advance at the bottom end like other devices, such as MCUs. I designed a product 13 years ago paying about $10 for a 3 kLUT device. Considering this has been more than 6 Moore jumps I would expect to be able to get a 200 kLUT device for that price. We are nowhere near that. The bottom end Spartan 7 is 6k 6LUTs and costs over $15. Well, I don't know what they really cost, I've not gotten a quote yet.That's the other difference. You can't get anywhere near a real price for an FPGA online. I can get very competitive pricing for an MCU or most anything. But FPGAs are still priced at lunches and private meetings.

author: Berni
author_rank: Super Contributor
timestamp: January 29, 2021, 06:34:27 am
content: Quote from: SiliconWizard on January 29, 2021, 12:35:40 amSolder paste is just the method i prefer to use to maximize the reliability of the soldering process. When there are hundeds of pins to solder having even a 0.1% chance of a pin not soldering can drop the total reliability of a whole chip getting soldered down properly to a coil toss. The paste on the pad makes sure the PCB pad wets properly and make a nice molten ball of solder on it that will for sure love to grab on the BGAs molten ball of solder. I use solderpaste to assemble all of my larger prototype boards anyway (masks are dirt cheep from china, its faster to just tweezer pick and place the parts on there, end result looks much more professional ..etc)Just putting some flux on the PCB, placing down the BGA and reflowing it on there works perfectly well too. Just have to make sure you don't use too much flux, this can cause the flux trapped under the chip to start boiling so violently that it starts lifting the whole chip up and tossing it about, making it get misaligned. Plenty of solder there to get the job doneYou can get a BGA to solder with even less solder. I have transplanted BGAs before where i pulled a chip off a board. Used a soldering iron to make the balls on the bottom uniform, but this doesn't actually make proper BGA balls but just little bumps of solder (you need a reballing kit for that). Did the same make uniform balls on the PCB, flux it up then reflow the BGA on there, give it a slight tap on the head to make sure it sits down well and done. This puts way too little solder on the balls, on a microscope you can clearly see the balls look more like fat pancakes and the whole chip sits way lower. So low that you can't even use the trick of looking down the gap between the row of balls and shining a light trough to make sure there are no bridges. Its not how a BGA is supposed to be soldered but i got it to work anyway.

author: gnuarm
author_rank: Super Contributor
timestamp: January 29, 2021, 06:50:16 am
content: Quote from: asmi on January 28, 2021, 08:00:38 pmI don't think FPGAs are any harder to design than MCUs. I think that is an often perpetuated myth. The difference is simply that people learn about programming sequential machines even before they program in schools. Middle school students program their calculators. Every engineering or computer science student learns to program in some language. FPGAs are programmed in an inherently parallel language, a data flow language that simply is alien, but not inherently harder or more difficult, in fact, I submit a languageeasierto learn!Sequential processors try to make it look like multiple things are happening at once, but in reality a processor does one thing at a time.Thatis hard to learn and easy to screw up! We are just used to it. Much like electric cars vs. gasoline. Gasoline cars have been improved by 100 years of progress and support so that now they are easy to fuel. It takes 5-10 minutes at a gas station. But an EV will be charged at home 99% of the time eliminating the trip to the gas station entirely and saving money on fuel to boot! But people are not aware of how easy it is to fuel the EV. They are mind stuck in the gas station paradigm just as most people are mind stuck in the MCU programming is easy and FPGAs are hardparadigm. The only thing holding them back are their minds.

author: NorthGuy
author_rank: Super Contributor
timestamp: January 29, 2021, 05:14:46 pm
content: Quote from: gnuarm on January 29, 2021, 06:50:16 amThey're not. And I don't think the learning curve is steep. It's just nobody tries to learn. Instead of learning underlying principles, they try to learn the language (Verilog, VHDL, or whatevere), whatever this means. Then they wonder what's the difference between a register and a wire. They also see huge difference between languages.It's like if you wanted to learn electronics by studying schematic symbols. You would have really hard time understanding the difference between resistors and capacitors. It would be really important to you if resistors are drawn American way or European. The leaning curve would be really steep. But if you started from the underlying principles, things would make much more sense, and you wouldn't give a shit how the resistors are drawn.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 29, 2021, 05:23:54 pm
content: I do not agree with you two. Digital design IS relatively hard. For one thing, it's highly "parallel" - in fact it's almost exclusively that in a way. And designing "parallel" systems is inherently much harder than sequential programming, which is basically what beginners are dealing with.Most of us have a hard time thinking about several "tasks" running in parallel (which is true in other aspects of our lives as well), whereas it's much easier to focus on one task with steps running one after another. I do no buy this is just a "cultural" thing and that proper, early exposure to parallel concepts would reverse this. Just MHO though.

author: asmi
author_rank: Super Contributor
timestamp: January 29, 2021, 05:28:00 pm
content: Quote from: SiliconWizard on January 29, 2021, 05:23:54 pmYea, I also think this way. What is ironic is that our brain is essentially a big biological FPGA, meaning massive-parallel processing unit. It's just doing many things at once goes against our nature because we only have so many hands, eyes and feet so we can't really multitask in a physical sense, and all of that highly parallel processing in a brain is happening "in the background" without us realizing it, so we don't even think of any of that as tasks that we are doing.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 29, 2021, 05:38:38 pm
content: Quote from: asmi on January 29, 2021, 05:28:00 pmOur nervous system in general is indeed a huge "parallel" device. But our conscious thoughts are only a very small part of what happens, and what we can consciously process at any given time is relatively limited.

author: asmi
author_rank: Super Contributor
timestamp: January 29, 2021, 06:28:57 pm
content: Quote from: SiliconWizard on January 29, 2021, 05:38:38 pmI think we just don't think of majority of those tasks as actual tasks - like for example processing signals from our eyes to form the kind of 3D world perception as we see. It's a big and very complicated processing task, but since it happens autonomously, we just don't even realize how much are we really doing at a single moment. And the same goes for autonomous tasks like regulating internal organs' functions. There is a joke that someone once asked centipede how does it know which feet to move, and after than it couldn't move anymore because it doesn't know how to decide which ones to move, and we also have a lot going on in the background.And that is what makes it similar to FPGA - there is usually quite a bit going on at the same time, but since FPGAs don't have reflexes, we have to think about all of that. And this is why I think good decomposition is a key to successful design.Also I think HDLs did us all a bit of disservice by having some code which synthesizes into hardware, and some other code (which looks pretty much the same) which is actually executed as a "normal" software code. I suspect many of us at some point did write a code which worked perfectly in a simulator, but then synthesizer choked on and refused to produce any hardware. The prime examples are loops - the way they work in synthesizable code and in simulation are fundamentally different. To the point that it's generally advised to avoid loops in the synthesizable code until you fully understand all implications of their usage in this scenario.

author: NorthGuy
author_rank: Super Contributor
timestamp: January 29, 2021, 06:43:01 pm
content: Quote from: asmi on January 29, 2021, 05:28:00 pmFPGA may do everything simultaneously (in a sense), but it doesn't mean that the designer must design everything simultaneously. You separate one thing - which is usually a combinatorial block which takes inputs from a set of flops and feeds the outputs to another set of flops. While working with the block, you only need to describe how to calculate/derive the outputs from the inputs. Then you move to a different combinatorial block and do the same. There are certainly some quirks, such as memory, IO, clocking etc. , but anyway all you need to do is to describe your design sequentially, block by block.

author: rstofer
author_rank: Super Contributor
timestamp: January 29, 2021, 06:51:34 pm
content: Quote from: NorthGuy on January 29, 2021, 05:14:46 pmI have a book that spends all of the pages on designing small FPGA gadgets. MUXen, Decoders, Counters, Registers and so on. The idea is to code each of these gadgets in several ways and then look at the resulting schematic. Does it look like what you expect? Maybe if you used an alternate coding...It is vitally important to understand the lower level blocks in great detail. Then there is no doubt about the difference between a register and a wire. Complex systems are nothing more than an interconnected assembly of lower level blocks.The code is given for Verilog and VHDL, side by side."HDL Chip Design" Douglas J SmithI have several books on FPGA design but, for somebody just starting up, this is the book I would recommend as a starting point.It still doesn't substitute for a course in logic design followed by one or more courses in system design. But it's a great start!

author: Miti
author_rank: Super Contributor
timestamp: January 30, 2021, 11:16:25 am
content: So, to recap. BGAs are such a pain... or are they?And we’re talking about hobbyists here, the industry has decided. They are everywhere. Imagine an iPhone made with QFPs.

author: gnuarm
author_rank: Super Contributor
timestamp: January 30, 2021, 07:25:08 pm
content: Quote from: SiliconWizard on January 29, 2021, 05:23:54 pmOdd how we both clearly see opposite sides of this issue. It is seldom that a useful embedded program does not include parallelism. I think we are often blind to it because we have adopted methods of dealing with it that aren't labeled as "parallel" execution. Also, even when we have parallel processes, they are not actually parallel unless there are multiple processors. Interrupts are a good example. Use one and the methods are simple and well understood. Use more than one and you are in a domain where you might get away with it fine, but the reality is the analysis and implementation get much more complex. Analysis that most people skip and so leave their systems open to faults.In FPGAs parallel processes are part of the landscape and create no analysis problems. There are logical problems, but not because of parallel design. Many designs use nothing but parallel statements without giving it a thought. It's just not an issue.

author: Berni
author_rank: Super Contributor
timestamp: February 01, 2021, 08:49:03 am
content: I would say it is a bit of both.Large parallel systems can be hard to visualize how they work because you have to keep a lot of things in mind, but at the same time most people are used to classical programming where things happen sequentially, so going into HDL from something like C is confusing.Some inherently sequential algorithms are easy in C but in HDL turn into a big messy state machine. So it makes HDL seam like its really hard for that task. While other more parallel tasks are cleaner in HDL because in C they might require some sort of scheduler.Debugging a FPGA is also more annoying since you can't halt the whole chip and single step trough it, looking at values etc... like you can on a MCU. You only get this sort of flexibility on FPGAs inside a simulator, so that is again something that people are not used to from MCUs.So id say yes FPGA development is more difficult than MCUs, but the difficulty is overhyped and made to seam a lot worse than it actually is, just because they do everything differently so everything looks unfamiliar to people.So combine the extra difficulty and unfamiliarity with the fact that FPGAs are expensive as hell compared to MCUs means that people will only really use a FPGA only if they are forced to in some way. If you need lots of flexibility, speed, bandwith etc... then you gotta go FPGA, if not then the cons outweigh the pros.

author: NorthGuy
author_rank: Super Contributor
timestamp: February 01, 2021, 03:51:37 pm
content: Quote from: Berni on February 01, 2021, 08:49:03 amYou cannot halt the whole FPGA, but you certainly can halt huge regions of it by disabling the clock. You can also clock regions with an external clock, and, by controlling the external clock, you can move as fast or as slow as you want. Meanwhile, you can instantiate ILA and monitor the internal signals.

author: gnuarm
author_rank: Super Contributor
timestamp: February 01, 2021, 07:25:44 pm
content: Quote from: NorthGuy on February 01, 2021, 03:51:37 pmI have used the single step capabilities of debuggers, but to put it mildly I found it wanting as a useful debugging technique. With FPGAs I use simulation which makes every point in the design accessible with many forms of viewing possible. The step from simulation to running on the bench is typically a small one with few problems if the overall debug process is given adequate attention. I am a firm believer that an ounce of prevention is worth a pound of cure.Having to debug in real time with real inputs is that last thing I want to do, literally the last thing and I want to keep it as short as possible. More of a blessing or approval process than debug.I've never used the ILA type features of vendors' tools. I just bring signals of interest out to a header and connect bench tools. So far my designs have been low speed enough for that to work. ILA requires capturing data into buffers and then reading them out over a JTAG or USB port. I find a scope probe to have much higher bandwidth and very low latency. I suppose for very complicated problems the triggering capability of the ILA can be useful.

author: gnuarm
author_rank: Super Contributor
timestamp: February 01, 2021, 07:37:58 pm
content: Quote from: Berni on February 01, 2021, 08:49:03 am"Expensive as hell"!?? That fact is not in evidence. I can get FPGAs as cheap as $3. That's pretty competitive.People talk about speed as the reason to use FPGAs when I use them because of the ease of development. The only exception to this is when you need to roll your own peripheral that might be a standard part of an MCU. Even then I don't find it hard to make an SPI port or a UART. I have tested, working IP for a UART. If it needs something special I can add it. Anyone ever had trouble sending UART data over an RS-485 port because they couldn't turn off the driver at the right time in software? No problem in an FPGA, not because FPGAs are fast, but because they are flexible.Anyway, I'm not going to change anyone's mind. There was a recent thread about power controllers where people talked about having 2 MSPS ADCs in the MCU/DSP parts at the same time as talking about having 24 bit ADCs. You don't get both in the same part!!! Pick one. lol Whatever. I'm happy with my choices. Right now my problem is preferring easy to use QFP packaging. Gowin is a good provider in that vein, but they have been designated a CCMC by the US government and I'm not sure where that is going. It may make it impossible for me to use their parts and I'll be back to using a 256 or 196 pin BGA. That's the one area where FPGAs suck for me.

author: Berni
author_rank: Super Contributor
timestamp: February 01, 2021, 08:38:40 pm
content: Quote from: NorthGuy on February 01, 2021, 03:51:37 pmYep you can but it is not as simple as on an MCU where you plonk down a breakpoint in code, it halts and you single-step lines from there.The built in logic analyzer can be useful at times, I did like the one Altera made, but i often still leave an unused connector for connecting to a real logic analyzer. I prefer to get the design working in simulation first just because debugging it is a lot easier that way. I never used an MCU simulator for any modern chip before, i just run it on the real thing since they can debug easily in circuit.Quote from: gnuarm on February 01, 2021, 07:37:58 pmYes you can get cheep FPGAs but as i said earlier in the thread they are so tiny that they are barely more than glue logic and a few KB of memory. At the same time the 3$ price point gets you a pretty capable 32bit ARM microcontroller running in the three figure MHz ballpark with 10s of 100s of KB of memory, capable of doing some very advanced tasks. If you just need a simple low power MCU those can be had for 10s of cents even at expensive distributors like Digikey. If you want to build a complex product with no extra external MCU involved you get to FPGAs that cost a few 10s of dollars per chip or sometimes even into the low 100s.So for tasks that a MCU is capable of handling you will almost always find a MCU doing it in that design. Im not saying FPGAs are useless. There are some things where they really come in handy. Heck, i put a CPLD(well its actually a tiny FPGA marketed as one) into a design that could be done using a dozen 74xx chips, but didn't want to deal with such a big pile of logic.I love the flexibility that a FPGA offers in a design and i really want FPGAs to become competitive with MCUs. Bigger FPGAs for the cost of a MCU, perhaps also include a small hard ip 32bit processor with dedicated RAM. So i can stick one as a single chip solution into a design that targets a total 10$ BOM cost. But so far as i had explained FPGAs are far behind moores law, there is barely any advancement in what you can get for the price, since the FPGA vendors rather focus on the customers with deep pockets that buy the four or five figure price tag chips.

author: Bassman59
author_rank: Super Contributor
timestamp: February 01, 2021, 08:43:29 pm
content: Quote from: Berni on January 28, 2021, 07:49:31 pmWell, your point #1 is wrong because not every engineer who designs in an FPGA has deep pockets. Sometimes the reason to use the FPGA is because there is no other way to solve the problem. You have to think outside of whatever bubble you live in.As for point #2, "rare to be seen in DIY projects," well, exactly what relevance does that have?See, there's the difference between "DIY projects" and "product design."A DIY-er will use an Arduino and mount that onto a little board to do whatever silly little thing. One or two will be built, and that's that. The DIY-er takes advantage of an existing firmware code base that runs on an existing platform to do something of use. But here's the thing. Without the Arduino being made by the tens of thousands (I don't know the real number), that code base wouldn't exist and there's no way the DIY-er can buy something as powerful for as cheap.For product design, you choose the best approach to solve the problem at hand. I could not design our products if FPGAs did not exist. Tell me where I can find a processor that can manage 16 LVDS DDR serial data channels from ADCs, a gigabit full-duplex communications link to a remote host, manage sensor bias settings, manage housekeeping to monitor system operation (including a temperature-control loop) and local storage of operating parameters. And it all fits into an envelope the size of a Campbell's soup can (if the can was rectangular).I'm sure others can post examples of actual product design that can't be done with a microprocessor/microcontroller and an FPGA is used. Sometimes the FPGA is used in addition to the micro!I'll give one more example. For the hell of it, I did a little DIY project -- a "mastering quality" audio ADC and DAC. I figured I could spend $1000 on someone else's design or spend the $1000 on boards and parts and get the same result but with more fun. Originally I was going to use an 8-bit micro to manage configuring the ADC chip, the DAC chip, the SPDIF/SRC chip and the clock generator chip, as well as dealing with front-panel buttons select operating modes. I was going to use the micro's onboard ADC for input metering. Then I figured: well, there's already an ADC in the design, so why not use a micro that has an I2S interface that can connect to the ADC and go with that? And at the time I did this the handful of ARMs I looked at which had I2S support couldn't handle 192 kHz sample rates (limiting factor was bit clock input when the I2S port worked as a slave). So I decided to do the whole thing in a Lattice MachXO2 FPGA, which cost about the same as the ARM M3 I was going to use. The great thing about FPGAs is that you're not limited to the micro feature set. Need a bunch of SPI ports? Just add them. Need an I2S receiver? Just add it! Meter calculations? Oh, easy. Lookup table for the clock synthesizer config registers? Just instantiate it. Need a detector to work out whether an external word clock is connected, and if so, what frequency is coming in? Easy.Yeah, I could have done all of that in a micro (I'm looking at a LPC546xx part for something else and it will do I2S in at the rate I need) but my point is that itcouldbe done in an FPGA for about the same cost as doing it in a microcontroller. But for the next version I want to do the ASRC in the FPGA, so I trade off a larger FPGA against not spending $18 on a TI chip and I still don't need the micro ...I suppose all of this is to say, just becauseyoudon't have product applications for FPGAs doesn't mean that the devices aren't used by others.

author: gnuarm
author_rank: Super Contributor
timestamp: February 02, 2021, 12:11:40 am
content: Quote from: Berni on February 01, 2021, 08:38:40 pmActually, a logic analyzer is exactly that simple, except you don't need to single step. The device has continued to run at full speed while the history was captured. I tried single stepping in the early days of in circuit emulators when they really were emulators. It sucks. An MCU runs at MHz and I am not going to see much of use looking at one instruction at a time unless I already know where the problem is and for some reason I don't understand my code or the procdessor. I've never used single stepping since then. It's just too pointless. I get information dumps of one kind or another.With FPGAs, 99.975% of my debugging is in the simulator. The problems you get in the field have to do with not understanding the problem you were given or errors in the definition of the problem. Neither those offer up much insight from single stepping. System level tools are required.QuoteWow! If you think single stepping is easy, you need to try simulation on an FPGA. The simulation runs, you've selected all the relevant signals and boom, there they are on a logic analyzer-like display without touching hardware. The length is not limited by the buffer in the chip or the attached logic analyzer. It's limited by your PC RAM possibly. Just scroll and view. It's all there. Like every system it is best to start small, testing each piece in detail before moving on. $10 per bug in the lowest level unit. $100 per bug at the next functional level. $1000 per bug at integration and $10,000 per bug running on the final hardware. Field failures are more like $100,000 per bug. After that there's no way of saying how much the bugs cost as they can impact sales and company reputation.QuoteI think you are making up your data. A $3 processor does not have 100s of kB of RAM, Flash maybe, but a processor doesn't run full speed from Flash. I've yet to see a $0.10 ARM device. I guess you mean the Atmel AVR type devices. Yes, they exist. Is that the goal of this discussion?I don't know what you are talking about with FPGAs and MCUs. Maybe you aren't aware of everything out there.QuoteWe are talking about exactly that, the fact that people use MCUs because that is what they are accustomed to when an FPGA will often do the job as well if not better than an MCU.QuoteWhen you say "bigger FPGAs", do you have a size in mind? Do you have any idea what size FPGA is required for any given job?The ideas you express in this paragraph is exactly the sort of bias I have been talking about in this discussion. Here we have already presented the facts and these facts have still not changed your opinion.That's fine. There are options available. No one says you have to use them.

author: gnuarm
author_rank: Super Contributor
timestamp: February 02, 2021, 12:38:36 am
content: Quote from: Bassman59 on February 01, 2021, 08:43:29 pm

author: Berni
author_rank: Super Contributor
timestamp: February 02, 2021, 06:45:03 am
content: Are you arguing just for the sake of argument?I said in the post you are replying to that i use simulation to debug my FPGA designs. The ability to compile in a fraction of a second, look at any signal, stop at any point and flip register values etc... Make it so much easier to find the bug. By single stepping i mean stepping a clock edge at a time, that's pretty much the equivalent to single steeping code on a MCU.And yes my very point the whole thread is that you use a FPGA when there are no alternatives. When you have to interface a weird oddball bus at 100MHz you need a FPGA to do it. Also MCU+FPGA designs are totally a thing, most of the boards i designed with FPGAs also had some sort of MCU or SOC on there too. But the only reason FPGAs are on those boards is because the MCU alone could not do it.The MCU is the default solution for most digital control tasks because they are cheap and easy to work with. You don't really go at it with the approach "Yeah a FPGA can do this task so no need to look at other solutions" while its normal to go "Yeah my usual 32bit MCU can do this so no need to look at anything else". You can implement an entire MCU in a FPGA as a softcore, but this doesn't even remotely fit into these 3$ FPGAs.Yes the 10s of cent MCUs are tiny 8bit things, but sometimes that is all you need. Step up a bit and you get a 32bit ARM MCU with a decent amount of memory and peripherals on a easy to solder QFN for 60 cents in single quantity on digikey:https://www.digikey.com/en/products/detail/microchip-technology/ATSAMD10D13A-MUT/5226468My point is that if you pick up random electronics devices around a house and look at what is inside, you will almost never find a FPGA inside. But its difficult to find electronic devices that do not have some sort of MCU inside. And i was explaining the reason for this.I used FPGAs from Altera, Lattice, Xilinx, put together boards with them, had the boards go into mass production. I like the power and freedom that FPGAs provide. But due to being cost constrained i can't just plonk down a FPGA anywhere i would like one, the design has to have a very good reason for needing one before it actually becomes a viable solution.

author: gnuarm
author_rank: Super Contributor
timestamp: February 02, 2021, 07:14:43 am
content: Sorry if I've upset you Berni. I will try to remember not to reply to your posts in the future.

author: Berni
author_rank: Super Contributor
timestamp: February 02, 2021, 07:34:57 am
content: Quote from: gnuarm on February 02, 2021, 07:14:43 amSorry didn't mean it like that. Its just that you seamed to repeat back most of the points from my post as if i said the opposite.My only gripe with FPGAs is that the prices of nice decently sized chips have not come down much at all in the last 10 years, still putting them out of reach for any of my cost constrained designs. While the processing power of cheap MCUs has went way way up in the last 10 years.

author: dolbeau
author_rank: Regular Contributor
timestamp: February 02, 2021, 10:11:44 am
content: Quote from: asmi on January 28, 2021, 08:00:38 pmI thought like you, but I think this is less and less true. I'd never used a FPGA before, or written HDL, but when I found myself with a hobby project (and a professional need to better understand the HW designer lingo as an additional excuse ;-) ) needing a FPGA, I managed to get a bitstream that would talk to the existing hardware reasonably easily, through a custom-designed adapter board. KiCad was very usable, and Vivado was a fairly accessible tool, including the simulator - I had a visual representation of my signals that matched what what is in the bus specifications before I even ordered the FPGA boards. Getting the basics working turned out to be much easier than I had expected.The fact there's also a lot of HDL examples of various sizes online helps a lot. I didn't design the AES block or the polynomial multiplier (or the sd-card controller but I've yet to get that one to work...), I just used what was publicly available.

author: gnuarm
author_rank: Super Contributor
timestamp: February 02, 2021, 11:04:50 am
content: Quote from: dolbeau on February 02, 2021, 10:11:44 amPolynomial multiplier... is that a polynomial division such as in a CRC calculation? The hard part of CRCs would be figuring out all the bit order and complementing that has to happen. There's 2^N combinations and often you get it right on the last one. Exhaustive tree search is a bitch.

author: dolbeau
author_rank: Regular Contributor
timestamp: February 02, 2021, 11:31:58 am
content: Quote from: gnuarm on February 02, 2021, 11:04:50 amNo, as in GCM mode for AES; There's online code from a book that includes a lot of examples:Hardware Implementation of Finite-Field Arithmetic.I currently use a full 128bits multiplier with the proper modulo for GCM; combinatorial code works fine single-cycle for me... so I need to change it, as it's much faster than the bus it's hooked up to and takes a *lot* of space in the FPGA :-)

author: gnuarm
author_rank: Super Contributor
timestamp: February 03, 2021, 06:48:54 am
content: Ok, but the same sort of thing where "multiply" defined by an XOR operation and no carry between bits, no?

author: dolbeau
author_rank: Regular Contributor
timestamp: February 03, 2021, 07:40:00 am
content: Quote from: gnuarm on February 03, 2021, 06:48:54 amSame sort of thing; _addition_ is XOR - multiplication ismuch more complicated (unoptimized version). So complicated that modern CPU have dedicated instructions to accelerate them (e.g.pclmulqdq in SSE, various PMUL inArm NEON).

author: gnuarm
author_rank: Super Contributor
timestamp: February 03, 2021, 09:12:14 am
content: Quote from: dolbeau on February 03, 2021, 07:40:00 amConventional addition is XOR. Polynomial division in finite fields is XOR, such as in CRC calculations.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 08, 2021, 10:06:16 pm
content: Quote from: asmi on January 29, 2021, 05:28:00 pmProgramming an MCU is like playing a wind instrument: one note at a time. With an FPGA, it's more like playing an organ where you can play ten notes simultaneously with your fingers and additional notes with your two feet.

author: gnuarm
author_rank: Super Contributor
timestamp: February 09, 2021, 04:19:07 am
content: Quote from: Sal Ammoniac on February 08, 2021, 10:06:16 pmThat makes it sound like it is hard to do. I'd say it is more like a one man band compared to a symphony. The one man band is working very hard to play all the instruments and get them to sound good together. It takes practice and skill and the result is often just barely good enough.A symphony is many instruments being played truly simultaneously allowing music to be created that is so rich it is hard to even imagine until it is heard.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 09, 2021, 04:23:33 pm
content: Quote from: gnuarm on February 09, 2021, 04:19:07 amThat's because it is. An organishard to play well. You're playing three lines of music simultaneously in two different clefs and each may have a different rhythm and you often need to change stops while playing.

author: gnuarm
author_rank: Super Contributor
timestamp: February 09, 2021, 07:49:11 pm
content: Quote from: Sal Ammoniac on February 09, 2021, 04:23:33 pmThat's why it is a poor analogy to programming in HDL.In many ways programming parallel tasks in HDL is like using a Ronco Rotisserie, "Set it and forget it!" Being a part of the language means it doesn't require much thought to use.A <= B or C;D <= E and F;There, two parallel tasks. Wait, here's a third.G <= A xor D;See, not at all like playing an organ. :-)

author: NorthGuy
author_rank: Super Contributor
timestamp: February 09, 2021, 08:37:42 pm
content: These are bizarre analogies. You're not playing anything. You build a program which then "plays" on your device, as a music would play on a mechanical piano. With FPGA, you build the program by interconnecting logic elements. With MCU, you build the program by filling memory with executable instructions and initial data.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 09, 2021, 08:44:13 pm
content: Quote from: gnuarm on February 09, 2021, 07:49:11 pmThat's because you chose three extremely simple operations. Real-world FGPA applications often have many complex modules interacting in complex ways.

author: asmi
author_rank: Super Contributor
timestamp: February 09, 2021, 08:48:38 pm
content: Quote from: NorthGuy on February 09, 2021, 08:37:42 pmThis is what happens when you push analogies a bit too far.

author: gnuarm
author_rank: Super Contributor
timestamp: February 09, 2021, 09:14:42 pm
content: Quote from: Sal Ammoniac on February 09, 2021, 08:44:13 pmThat is the complexity of your design, not a complexity of the tool. No tool is going to make a complex problem simple. The best you can hope for is that it doesn't add any complexity which is what FPGAs do. They let you implement your design without adding unneeded complexity.Implement your complex problem in sequential software and now you have to deal with the complexities of real time multitasking with prioritized interrupts, possibly on multiple processors.Do you know what they call "real time multitasking with prioritized interrupts, possibly on multiple processors" in FPGAs? Programming.

author: Bassman59
author_rank: Super Contributor
timestamp: February 10, 2021, 07:02:34 pm
content: Quote from: Sal Ammoniac on February 09, 2021, 08:44:13 pmTruth.I think it's worth remembering that FPGA design is digital logic circuit design and it's nothing more than clever packaging of what we used to do in boards full of 74xx TTL or 4000-series CMOS logic chips. The "code" we write is in a hardwaredescriptionlanguage because it describes what the logic must do. We don't do FPGA design in a "programming language" because we are not programming the devices. (Programming in this context means "loading configuration data into non-volatile storage.")Microprocessors are sequential-execution machines that ultimately do one thing at a time, and the languages used in programming are designed with that paradigm in mind.YES, we know there are people trying to do "FPGA design in C" (so-called "high-level synthesis"). And YES, there are people who are trying to design or extend sequential-execution processor programming languages for parallel tasks.Look at it this way:A processor is just one example of digital logic circuit design. That's why we can implement a processor in an FPGA. (We could do it in MSI logic like TTL or 4000-series CMOS. We could do it in discrete logic with transistors. Or vacuum tubes.)But we cannot implement an FPGA with a processor.

author: glenenglish
author_rank: Frequent Contributor
timestamp: May 26, 2021, 04:51:12 am
content: BGAs are super easy and super reliable.They are SOOO easy to get right, as long as you have enough heat, and you only get ONE chance when you drop them on the board.Xilinx make some 196 ball Spartan7s with 1mm pitch. These can be fabbed with el-cheapo PCB on say a 6 layer.1mm self solder paste stencilling is a doddle.if you put the planes all in the top 3 layers and have a super thin PCB, say 0.1mm prepreg, you can get away without bottom side caps.....(plane capacitance doing the work)Also, the 0.5mm Spartan7 - look at the footprint- all the busy stuff is around the edge actually quite easy to route out without crazy PCB tech- but your stencil paste work must be good !Spartan7 is good bang for your buck and 7S25 and higher have fast multi channel differential input ADCs.Now, you can go Lattice. Lattice is a good company, and their devices are excellent, and the documentation is good. But the tools are not as polished. If the design is simple, Lattice in QFN might be your best bet. But honestly, a 0.5mm QFN and a 0.8mm BGA are easy peasy- except that the QFN might be easier to route on on a low tech PCB.Glen.(disclaimer : Xilinx Alliance Partner)