MachXO3LF Starter Kit: Interaction with PC - Page 1
Forum section: electronics / general

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 05, 2018, 06:59:10 am
content: I'm trying to run before I can walk so this is a harsh learning curve... !I would like to derive a gadget from the MachXO3LF Starter Kit with the interesting hardware functions being done on the FPGA or beyond and controlled via the PC.The MachXO3LF has hardware SPI so this is a definite possibility to drive the board as SPI slave but this would require additional hardware on that side. The board itself has a FTDI chip which drives the JTAG pins (primarily used for programming and presumably also by Reveal)Is it possible to use the JTAG for the PC/FPGA interface at run-time (presumably with a FIFO across the interface)? Are there any known examples/reference designs for doing this? (The board seems to come with Blink only!)I found a reference to ORCAstra but nothing recent??Thanks in advance

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 05, 2018, 09:30:26 am
content: UART communication between the FT2232H (B channel) and the MachXO3.See signals RS232_Rx_TTL and RS232_Tx_TTL.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 05, 2018, 09:37:11 am
content: Quote from: SiliconWizard on June 05, 2018, 09:30:26 amThat's an answer to a different question.Although, trying to be more open minded....The board does have the potential to interface either RS232 or I2C on the BDBUS of the FT2232H...I know nothing about FT2232H... can that be configured from the PC side or does the Serial EEPROM need to be reprogrammed out of circuit using some complex SDK of some kind?I was trying to simplify the FPGA side, since I am new to this stuff, so I thought SPI would be easiest (a write to a register would trigger a FPGA function with result later back in a register).Using RS232 sounds harder, in fact RS232 perhaps needs some kind of intelligence on the FPGA side... e.g. Mico8? and that sounded hard!

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 05, 2018, 10:14:19 am
content: It allows interaction with a PC. What's missing?

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 05, 2018, 10:18:00 am
content: Quote from: SiliconWizard on June 05, 2018, 10:14:19 amOur posts overlapped... See ^I foundhttps://numato.com/kb/configuring-ft2232h-usb-serial-converter-saturn-spartan-6-module/which seems to suggest reconfiguring the FT2232H Port B is feasible and then to use the UART... interesting....

author: NorthGuy
author_rank: Super Contributor
timestamp: June 05, 2018, 01:48:26 pm
content: FTDI has a DLL which you can use on either channel. So, you can use either UART or SPI. Either is very easy to implement in the fabric. Depending on the OS, there may be driver entanglements.I know Xilinx's FPGAs let you use JTAG. You can instantiate a special object which directly exposes JTAG signals to the fabric. Look at the docs for your FPGA. On the PC side, JTAG on FT232H is implemented through MPSSE, which is originally developed for SPI, but it's very easy to do JTAG with it.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 05, 2018, 02:01:59 pm
content: Quote from: NivagSwerdna on June 05, 2018, 10:18:00 amThe B channel can be configured as RS232 UART using FTDI's FT_Prog utility.Then you can access it as a COM port from the PC side. You can also use the D2XX library. Your choice.Implementing an UART in HDL is not much more difficult than SPI. And in both cases, you'll have to write code to interpret the incoming data.There is one pitfall to be aware of though. In both cases (at least in the UART case, and most likely in the SPI slave case too), you will have to deal with two clock domains, so you need to properly synchronize signals that cross domains. Overlooking that will give you erratic behavior and a lot of headaches.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 05, 2018, 02:33:24 pm
content: I am yet to understand fully the PIC hardware support on the MachX03... It does seem to have some support for crossing the clock domain into and out of the deviceMy clock strategy is still being formulated.Thanks

author: NorthGuy
author_rank: Super Contributor
timestamp: June 05, 2018, 02:43:31 pm
content: Quote from: NivagSwerdna on June 05, 2018, 02:33:24 pmUsually people just use 2-3 consecutive flops clocked by the receiving clock domain. There are some quirks, such as on Xilinx you need to set the ASYNC_REG property to prevent the tools from converting your flops into a shift register.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 05, 2018, 03:05:56 pm
content: "MachXO3L/LF devices support two types of PIO logic cells..." they seem to have some double flop magic in-built... it's on my TODO list to try and figure that out.

author: Bassman59
author_rank: Super Contributor
timestamp: June 06, 2018, 12:38:30 am
content: Quote from: NivagSwerdna on June 05, 2018, 03:05:56 pmThe PIO block supports SDR and DDR input and output, as well as a "gearbox" or serializer on the output and deserializer on the input.SDR inputs and outputs are inferred from code as you would expect. The DDR and gearbox inputs and outputs are instantiated IP cores, which is easy enough.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 06, 2018, 09:36:49 am
content: Quote from: Bassman59 on June 06, 2018, 12:38:30 amHence I don't feel I have to worry unduly about the nature of my inputs.I do have a lot to learn though! I plan to drive a 16bit address bus and a 8bit data bus... seems that the hardware can provide some support to keep everything nicely lined up (even though my target frequency is only 4MHz)A lot of this is very challenging... I know what a clock is... I know what an edge is... but "edge clock".... hm.... no idea how 'edge clock' is derived if I don't define anything...

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 06, 2018, 09:39:23 am
content: I played with FT_CONFIG last night... looks very do-able. Seems both ports are currently 245FIFO but I can easily change Port B to be UART and I am warming to using Mico8... at least I can then talk to the board using Putty/Terraterm etc and my data rates across the link are very low.

author: Bassman59
author_rank: Super Contributor
timestamp: June 07, 2018, 12:05:59 am
content: Quote from: NivagSwerdna on June 06, 2018, 09:36:49 am"Clock edge" -- the rising (or on occasion, the falling) edge of your flip-flop's clock is when the flop's D input (and enable input) are sampled and then driven on the Q output some short clock-to-out time later. The magic here is that the D inputs can change at any other time and the flip-flop output does not get affected. The D input has to be stable around the time of the clock edge (that's called setup time before and hold time after) for the output to be assured.If you do your design in VHDL, the code to infer an edge-triggered D flip-flop is simple:Code:myflop : process (clk, rst) isbeginif rst = '1' thenQ <= '0';elsif rising_edge(clk) thenQ <= D;end if;end if;end process myflop;Obviously there is a whole lot more to it. But the template above tells the synthesizer to generate a flip-flop. Whether it is in the fabric or the I/O, it's the same.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 07, 2018, 06:56:47 am
content: Quote from: Bassman59 on June 07, 2018, 12:05:59 amThat's not the same as "Edge Clock".The device I am using is a MachXO3L-6900C which has various hardware features for I/O such as PIC, sysIO buffer pairs, ... The basic PIO cells have a double D-latch arrangement. Where possible I will try and use the features available in the hardware. Maybe I will try and be explicit and see if it infers the edge hardware.

author: Bassman59
author_rank: Super Contributor
timestamp: June 08, 2018, 04:48:15 am
content: Quote from: NivagSwerdna on June 07, 2018, 06:56:47 amOh, sorry, misread what you meant. The edge clock is used by the serializer or deserializer in the I/O. It runs at the high-speed (serial) rate and is usually generated by a PLL from the parallel (word) rate. This means you need to instantiate the PLL to get the serial-rate clock, and you need to instantiate the library element for the I/O logic (serializer, deserializer). Seehere(pdf). The synthesizer won't infer anything more complicated than a simple single-edge-triggered flip-flop in the I/O. You also have to instantiate differential I/O buffers if your design needs them.If your design uses simple DDR, then you don't need an edge clock, but you do need to instantiate the correct DDR I/O element.(I mean, it would be really nice if the synthesizer was smart enough to infer at least a simple DDR interface, but I haven't seen one that does, across Xilinx, Altera, Microsemi and Lattice devices using vendor synthesis tools and Synplify.)

author: Tighermine83
author_rank: Newbie
timestamp: January 26, 2021, 03:49:13 pm
content: Hello,I've just bought this kit, also I am beginner on FPGA programming. Is there any examples for MachXOLF Starter kit ?If anyone can share some projects it will be very appriciated.Many thanks .

author: mon2
author_rank: Frequent Contributor
timestamp: February 03, 2021, 02:28:57 pm
content: Yes. Start with the docs and examples on the lattice website and search for this kit.Have the same kit here. Write back if you have questions or get stuck. May be able to help.Suggest that you review fpga4fun.com and also nandkand.com websites.Consider to study about Verilog which we found easier to digest.Not an expert but getting more and more comfortable with FPGA devices.

author: asmi
author_rank: Super Contributor
timestamp: February 05, 2021, 08:48:40 pm
content: Quote from: SiliconWizard on June 05, 2018, 02:01:59 pmIf your system clock is much higher than UART/SPI clock, you can use oversampling and avoid the need for the second clock domain. As long as incoming signal is reasonably clean, you should be able to find a sampling point without too much trouble.P. S. I think this thread belongs to FPGA section.