High speed input protection - Page 1
Forum section: electronics / general

author: bal255
author_rank: Newbie
timestamp: January 09, 2018, 08:20:39 am
content: Hello guys,I have a problem.I have got a FPGA which needs to operate in a 24V and 3.3V environment, so I need some input protection. The requrements are:Bidirectional signals3.3V bidirectional I/O, protected up to 24V (max input voltage of FPGA is 3.4V)20 MHz square waves8 mA output current from the FPGAI have tried the following circuit (see attachment) but I cant get it to work. I calculated the resistor on the input (before the diodes) can have a maximum of 2.5 Ohm, which limits the output current of the FPGA.Does anyone else has any idea how i can get this to work?

author: Marco
author_rank: Super Contributor
timestamp: January 09, 2018, 08:28:30 am
content: Quote from: bal255 on January 09, 2018, 08:20:39 amAcross what kind of cable/length?

author: bal255
author_rank: Newbie
timestamp: January 09, 2018, 08:34:30 am
content: Quote from: Marco on January 09, 2018, 08:28:30 amIt will probably be 2 meters at max, although it is but not specified

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 09, 2018, 09:29:54 am
content: 20MHz is not crazy; RS-422/485 goes up that high, and is easily filtered and protected for robustness and RFI purposes.Use schottky diodes (BAT54S typical).Are these inputs, outputs, or both?Do you actually need 8mA output current?What kind of source/load will be attached to these pins?It would be typical to add a buffer circuit to an output, which can be as simple as a sacrificial 74HC245 or whatever.If you need a low output resistance AND 24V capability, you may find you need a custom buffer circuit. Example, adding a diode in series with the pull-up transistor, so that the output can be pulled above VCC without damage (but the pull-down transistor might still overheat, so a fold-back current limiting circuit might be used?).Tim

author: Marco
author_rank: Super Contributor
timestamp: January 09, 2018, 09:09:41 pm
content: Quote from: bal255 on January 09, 2018, 08:34:30 amAt 2 meters you're already at the breaking point where unterminated signalling will start distorting the signal too much to be useful ... if you want to be able to support longer cables than that, definitely move to terminated differential signalling.That said, assuming 100 pF capacitance and 50 MHz required bandwidth only allows you about 30 Ohm series resistance. I assume you don't want to dump 1A into your power rails when someone attaches 24V, so you're going to have to reconsider your plans. One option isa Bourns TBU. Another option is to design your own bidirectional buffer circuit out of high voltage devices which simply blocks the current, google can probably find something.PS. your FPGA can't drive a 100 pF cable at those speeds, needs more in the neighbourhood of 100 mA peak current.

author: David Hess
author_rank: Super Contributor
timestamp: January 10, 2018, 12:49:07 pm
content: A two transistor depletion mode FET AC series current limiter may work.If you have a negative supply, then there is a very high performance solution. Use a 4 diode sampling bridge and drive the top and bottom nodes with the maximum current of 8 milliamps in this case. Now the current in either direction is limited to 8 milliamps and the overload protection extends to the reverse breakdown voltage of the diodes. Offset voltage is limited to the mismatch between the diodes.