PSFB converter makes a loud audible noise - Page 1
Forum section: electronics / general

author: Ashwin619
author_rank: Regular Contributor
timestamp: March 24, 2022, 06:58:25 am
content: Hi, we are trying to design a 2kW onboard charger using a PSFB topology which will be based on the LTC3722-1 PCM IC. This will be an offline supply with a boost PFC front end and a center tap diode rectification. The design is expected to provide a Vout = 84V and Iout = 23A. A prototype PCB with all the power components and a daughterboard (containing LTC3722-1) has been made for this purpose.Currently, we are testing the board with an input supply of 100V dc and an output of 18.8V by making the appropriate changes to the output voltage divider and UVLO config. The converter seems to work fine and achieves regulation for loads up to 100W. However, there’s a very loud and audible squealing kind of noise coming from the transformer. The transformer is based on an ETD 49 core with a turn ratio of 3:1 (np/ns). The cores are held together by a homemade metal clip (might not be suitable but it seems to do its job)There’s also an issue of heating of one diagonal pair of MOSFET. at very low load (around 60-80W) which seemed somewhat abnormal. The switching frequency is 75kHz although for some reason the minimum I am able to get (with an addition of trim pot) is around 91kHz.I would also like to point out that we had done several simulations for this particular application and it seemed to have worked quite fine (although I do believe that simulation and real-life application are quite different). I have understood the basic working of this topology on how it achieves ZVS using the leakage inductance, the freewheeling period, the significance of having sufficient leakage energy as compared to the energy required by the Coss of the MOSFETs, etc. although this is my first time dealing with PSFB converter in practice. Our main objective right now is just to get it working in the right way at moderate loads.I am attaching the pictures of the various waveforms of the converter along with the schematic and the calculation files that I have used to arrive at the various component values.I would appreciate it if someone could shed some light on the probable cause for these issues. Any help or suggestion is highly appreciated.Regards,Ashwin619.1) gate waveforms of same leg2) gate waveforms of the diagonal leg3) CS pin waveform4) SS pin waveform5) Simulation waveforms6) Full bridge (primary)7) Secondary side and regulation part8 LTC3722-1 daughter board schematic[ Specified attachment is not available ]9) Video link which shows the audible noise coming from the converterhttps://drive.google.com/file/d/1F3y3-BwA51rDZmFIJV1mWtMo8W1LwsvU/view?usp=sharing10) LTSpice file

author: Ashwin619
author_rank: Regular Contributor
timestamp: March 24, 2022, 07:18:34 am
content: Some of the other points worth mentioning are as follows:-1) Earlier we were facing an issue with the mosfet driver mismatch where the L6388 driver was adding an additional delay of around 400n sec to the input signals. This was causing quite some shoot through events which then later rectified by removing the DPRG resistor which ensured max dead time between the Mosfets of the same leg and by also replacing the mosfet driver with a 2ED2106 driver which doesn't feature any internal DT.2) We have tested the converter with the mains supply of 230V (via an isolation and auto transformer). the converter was able to achieve regulation at 84V (at around 100W of power), however a similar problem of noise and irregular heating was taking place. We had also blown some FET's and drivers in later testing stage (probably due to over heating or ringing)3) In the current test setup (Vin = 100V, Vout = 18.8V), I am trying to vary the RLEB and RSLOPE resistor's as they are crucial for proper PCM control. Changing RLEB helped to remove the noise at very low loads(20 -30W), however it starts again at higher loads (around 100W)4) Soft start (SS) pins shows quite some distortion which perhaps indicates some faults wrt to high (shoot though ?) current. The (CS) pin also has quite some ringing in the RAMP signal.5) I am assuming that this might not be a case of flux walking as PCM controllers are perhaps somewhat immune to this issue.

author: Circlotron
author_rank: Super Contributor
timestamp: March 25, 2022, 04:57:11 am
content: Admitteldy i haven't messed with SMPSs professionally since 2005 but 2kW sound like a LOT to push through an ETD 49 core...

author: Ashwin619
author_rank: Regular Contributor
timestamp: March 25, 2022, 05:28:39 am
content: Hello Circlotron,I have used a software called ExcellentIT for core selection which shows that ETD49 is suitable for this power level. The original design was intended for a 2.5kW converter however we don't have plans to go to that level even in peak condition. Currently I just want the converter to provide upto 1kW of power without any issues as mentioned above.Please Note :- The software provides values for a full bridge converter, however I am assuming that this would work for a PSFB too considering that I have changed the N(np/ns) from the suggested 4:1 to 3:1 in order to accommodate the Duty cycle loss that's inherent in the PSFB due to the freewheeling period. I also understand that a sufficient leakage inductance and low winding capacitance in the transformer is quite desirable for PSFB as compared a regular FB converter.Let me know if I have made some noob error over here.1) Values obtained from the software

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 25, 2022, 05:42:49 am
content: Don't know much about the chip offhand, but I see peak current mode in the headline. What ripple fraction did you design this to? The sudden change in pulse width looks like subharmonic oscillation, suggesting insufficient slope compensation for the ripple fraction (inductor too large).Also quite a lot of ringing; what's the layout look like?Tim

author: Ashwin619
author_rank: Regular Contributor
timestamp: March 25, 2022, 08:02:14 am
content: Hello Tim,Thanks for your suggestion,I had considered a current ripple fraction (IL p-p / IL RMS) of around 0.2 or 20% for the output inductor. This gave me an inductance value of around 65uH considering the Vin = 390V, Vout = 84V, Dtyp = 0.66 and Fsw = 75kHz. However considering that there was no off the shelf inductor available for these values I had to use a 47uH one which thus gives me an current ripple fraction of around 0.135 or 13.5%Please note that I have used the design note for UCC28950 (also utilizes PCM control) in order to arrive at these values.As far as the slope compensation is concerned It has been achieved in the LTC3722-1 ic via a resistor which is connected in between the current sense resistor and the current sense (CS) pin which is R26 and R10 in my case. I have arrived at these values using the formula provided in the datasheet (it happens to be around 85Ω and 357Ω for a Vout of 18.8 and 84 respectively).I would also like to point out that I have increased the Lead edge blanking time from 150ns to 250ns as I felt that to ignore the initial ringing in the ramp signal to CS, this would be needed. I would also like to point out that for some reason the Fsw is 91kHz and not the targeted 75kHz even though I am trying to adjust the trim pot accordingly.I believe that these ringing and distortion on the CS pin are the main culprits behind this problem. I am attaching some waveforms of the Vgs, Vds and diagonal pair FETS gate overlapping waveform. Will soon post the images of the PCB layout.Regards,Ashwin619.1) Diagonal pair overlap2) Diagonal pair overlap zoomed3) Vds of Qd4) Vds of Qa5) LTC3722-1 datasheet ->https://www.analog.com/media/en/technical-documentation/data-sheets/LTC3722-1-3722-2.pdf6) UCC28950 datasheet ->https://www.ti.com/lit/ds/symlink/ucc28950.pdf?ts=1648182142132&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FUCC289507) Slope compensation in LTC3722-1

author: Ashwin619
author_rank: Regular Contributor
timestamp: March 25, 2022, 09:50:55 am
content: Hi,I am attaching some images of the converter PCB layout here.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 25, 2022, 03:59:47 pm
content: Is that showing all layers? Just 2 layers then?There are many issues.Planes are not well used, sacrificing the low inductance of opposite layers, instead joining both layers in parallel just to win a little more ampacity. You're better off using 3oz+ copper, or multilayer, to gain ampacity without sacrificing low inductance of a ground plane design.The lack of planes also severely impacts EMI. The plane under the control/management section (bottom-right) means it will probably not affect function of the circuit itself, but it may well be loud enough to affect nearby circuitry.This is also a problem endemic to the phase shift PWM scheme: the transformer is driven full wave in the common mode, even at zero power output (both phases in sync). Thus imposing a constant ping of 400V across the transformer's interwinding capacitance, every 75kHz. (Well, 150kHz, but alternating, so whichever. Or, when the two phases are shifted, twice that again really, where each contributes to its respective end of the primary winding.)I've highlighted some illustrative examples:1. The secondary side peak snubber is essentially irrelevant. Due to the narrow traces, long trace length, and circuitous return path, the total loop inductance here will be about 30nH. The 1A diodes aren't likely to appreciate the peak currents, either, assuming a capacitor large enough to matter -- which, 1nF is surely not enough.The value of this snubber depends on the leakage inductance between the secondary halves. If the transformer is wound naively, then these will just be single layers/banks of wire (hopefully, litz cable!), and, what is that, three turns on a ETD49, so like half a meter of wire length each? In a typical transformer design (i.e. one not intentionally made extremely leaky), leakage inductance is proportional to wire length, so can be estimated quite easily in this way. A typical inductivity of 0.3uH/m applies, with the exact figure depending on the geometry (conductor width, spacing to other windings). So expect 150nH here.The leakage inductance is relevant when the inverter applies differential voltage to the transformer. The primary side inductance is also involved, in a three-way network between source (inverter) and the two diodes (one staying on, one forced into reverse recovery), so the total inductance involved may be lower. When the inverter turns on, first loop current builds (to some amount greater than I_L2, because recovery is not instantaneous in PN junction types), then the one diode begins to turn off (current drops and voltage rises). The voltage continues to rise, overshooting due to these stray/leakage inductances, at a rate determined by drive strength, inductance, and node capacitance. So, for ballpark 150nH and 200pF, this will ring at around 29MHz. If driven to full magnitude (i.e. step change of 30A), this would develop a peak voltage of Ipk * sqrt(L/C) ~= 820V, plus transformer output voltage; likely due to inductances (like L1) and drive speed, the actual peak is lower, and well within the 600V rating of the diodes. Some damping to reduce ringing (i.e., R38, C30 -- R38 will probably be more like 22 ohms, I'm guessing these are placeholder values) will suffice.Anyway, the peak clamp snubber (D22, D23, R36, C29) acts in parallel with this loop, at best reducing the inductance to ~30nH; an improvement, but not nearly as good as it can be. If moved to the edges between pours (transformer pins and nearby GND), this could be reduced to about 5-10nH, with the capacitors returned to GND because that's a supernode, and the resistor can be placed wherever, it doesn't participate in the high frequency loop.2. Similarly for the inverter, Vbus and CS are extremely far apart, making an enormous loop. A bypass cap between Vbus and CS, directly in line between high side drain and low side source, would be able to solve this. But much better to redo the layout with 4 layers, interleaving Vbus, Passive, Active and CS all in the same place, with a bypass cap nearby.3. What is C61 doing? Is that an EMI capacitor as suggested by its isolation remark? It's... there's a long, piddly trace connecting it back to the ground pour under the transformer/output capacitors. Alongside another ground trace, terminated beside it, going to I think the 12V/aux winding on the transformer?Needless to say, any EMI filtering such a capacitor might provide, goes away entirely at rather modest frequencies. If its value is 4.7nF, the ~200nH stray trace inductance gives it a cutoff of a mere 200kHz, above which it's entirely inductive, and compared to the ~50 ohm impedances typical in EMI environments, will be of questionable utility by just a few MHz, and irrelevant by 40MHz (where XL = 50 ohm).4. And what's up with the mounting? I see mounting holes for the TO-247s, I guess they'll be placed horizontally beneath the board, clamped against a heatsink. But there's no room for a screw head, there's traces top and bottom hugged right up against almost every hole. Will these be insulated with washers or something then? Maybe they're actually standing up, and bolted to heatsinks on top of the board. But then why waste so much layout area using an inappropriate footprint?I'm afraid there isn't much I can do to help; the more I look at it, the more errors I find. And this is just a cropped-down section of the whole board. The only solution is a complete rip-up. Use 4 layers, and minimize loop areas. Recognize switching loops and place the respective components close together. Use appropriate rated components, and size EMI resistors and capacitors based on expected loop L/C. Layout extends up into the transformer as well: preferably, use a shield around the primary winding to absorb switching EMI, and use multiple layers of interleave, with bifilar secondary, to minimize leakage inductance.Good luck,Tim

author: Ashwin619
author_rank: Regular Contributor
timestamp: March 29, 2022, 07:03:04 am
content: Hello Tim,Sorry for the late reply.I appreciate the effort that you have put into making this reply post which contains such great suggestions and feedback. Surely learned a lot through it.Here are a couple of points that I would like to add1) I would surely agree that the planes are somewhat longer in length, thus adding a little bit of stray inductance which perhaps would cause some noise/ringing for high dI/dT signal or power paths. We have used 3oz copper considering the current requirement and thermal dissipation.2) Not having a continuous ground plane below the high switching power planes surely affects the radiated and conducted EMI noise. Although I would like to add that EMI-related issues are not our main concern right now.3) The snubber requirements as mentioned by you and their dependence on the primary and secondary side leakage inductance are quite intriguing and I'll surely consider them while deciding the values of R and C's. Would also replace the 1A diodes with something beefier.4) I believe the trace lengths of the CS and Vbus pins are quite fine. I have tried my best in keeping the length of the return paths as small as possible although I may have missed some places. Will add a bypass cap as suggested by you.5) The ground loop for the C61 class Y cap is surely a little lengthy, I'll try to botch some wires in parallel to reduce the stray inductance. As far as the EMI is concerned, again not a major priority for me at the moment.6) The Mosfets and the diodes will be placed on the bottom side with tabs facing up and a custom-made heatsink for them. A big sil pad will be placed between the tabs and the heatsink. The bolts will be mounted from the top side and their heads will be placed onto an insulated washer.We haven't interleaved the windings of the transformer as I was under the impression that a leaky transformer would help to get the sufficient leakage energy that is required for ZVS. A complete overhaul of the board design is probably not an option right now. I'll try implementing some of the corrections you have mentioned above. will let update you if it works.I am also planning to use a Voltage mode control ic (LTC3722-2) which has a similar pinout and would remove the need for a ramp generated from the primary current waveform. Flux walking might cause an issue and I may need to add a series blocking cap to solve this. Would like to know your view on this.Regards,Ashwin619.