Issue interpreting AC phase plot - Page 1
Forum section: electronics / beginners

author: promach
author_rank: Frequent Contributor
timestamp: January 29, 2019, 03:42:33 am
content: I am having some issue interpreting the following AC phase plot.The AC gain plot is ok, rolling off at high frequencies, but what about thewhich increases from 0 towards 180 degrees at higher frequencies ?Note: The current input stimulus and feedback resistor is configuring the inverter as a transimpedance amplifier. It’s to avoid disturbing the dc bias.test_cmos_inverter.ascCode:Version 4SHEET 1 2264 2956WIRE 256 -48 240 -48WIRE 528 -48 256 -48WIRE 240 0 240 -48WIRE 256 48 256 -48WIRE 256 48 240 48WIRE 192 80 160 80WIRE 160 160 160 80WIRE 240 160 240 96WIRE 240 192 240 160WIRE 272 192 240 192WIRE 384 192 272 192WIRE 112 224 0 224WIRE 160 224 160 160WIRE 160 224 112 224WIRE 240 224 240 192WIRE 0 272 0 224WIRE 256 272 240 272WIRE 528 288 528 -48WIRE 160 304 160 224WIRE 192 304 160 304WIRE 240 352 240 320WIRE 256 352 256 272WIRE 256 352 240 352WIRE 0 416 0 352WIRE 256 416 256 352WIRE 256 416 0 416WIRE 352 416 256 416WIRE 384 416 384 272WIRE 384 416 352 416WIRE 528 416 528 368WIRE 528 416 384 416WIRE 352 448 352 416FLAG 352 448 0FLAG 112 224 inFLAG 272 192 outSYMBOL nmos4 192 224 R0SYMATTR InstName M1SYMATTR Value TSMC180nmNSYMATTR Value2 l=3u w=1.2uSYMBOL voltage 528 272 R0SYMATTR InstName V1SYMATTR Value 1.0SYMBOL pmos4 192 0 R0SYMATTR InstName M2SYMATTR Value TSMC180nmPSYMATTR Value2 l=3u w=0.4uSYMBOL current 0 272 R0WINDOW 123 24 102 Left 2SYMATTR Value2 AC 1SYMATTR InstName I1SYMATTR Value 0SYMBOL res 256 144 R90WINDOW 0 0 56 VBottom 2WINDOW 3 2 135 VTop 2SYMATTR InstName R1SYMATTR Value 1MegSYMBOL current 384 192 R0WINDOW 123 39 50 Left 2WINDOW 3 68 23 Left 2SYMATTR Value2 AC 0SYMATTR InstName I2SYMATTR Value 0TEXT 864 176 Left 2 !.opTEXT 872 200 Left 2 !.ac dec 100 1 10gTEXT 816 328 Left 2 !.include tsmc180nmcmos.libTEXT 808 256 Left 2 !;.dc I1 -165n 165n 1ntsmc180nmcmos.libCode:* PSPICE TSMC180nm.lib file RWN 04/18/2010* library file for transistor parameters for TMSC 0.18 micron process* uses BIM parameters added 01/15/98* can configure and attach to Nbreak and Pbreak transistors in PSpice********************** 180nm TSMC parameters **************T14B SPICE BSIM3 VERSION 3.1 PARAMETERS* downloaded from MOSIS 04/18/10*http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/* tsmc-018/t92y_mm_non_epi_thk_mtl_params.txt*SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8* DATE: Jun 8/01* LOT: T14B WAF: 06* Temperature_parameters=Default*$.MODEL TSMC180nmN NMOS ( LEVEL = 7+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.354505+K1 = 0.5733393 K2 = 3.177172E-3 K3 = 27.3563303+K3B = -10 W0 = 2.341477E-5 NLX = 1.906617E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 1.6751718 DVT1 = 0.4282625 DVT2 = 0.036004+U0 = 327.3736992 UA = -4.52726E-11 UB = 4.46532E-19+UC = -4.74051E-11 VSAT = 8.785346E4 A0 = 1.6897405+AGS = 0.2908676 B0 = -8.224961E-9 B1 = -1E-7+KETA = 0.021238 A1 = 8.00349E-4 A2 = 1+RDSW = 105 PRWG = 0.5 PRWB = -0.2+WR = 1 WINT = 0 LINT = 1.351737E-8*+XL = -2E-8 XW = -1E-8+ DWG = 1.610448E-9+DWB = -5.108595E-9 VOFF = -0.0652968 NFACTOR = 2.4901845+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 0.0231564 ETAB = -0.058499+DSUB = 0.9467118 PCLM = 0.8512348 PDIBLC1 = 0.0929526+PDIBLC2 = 0.01 PDIBLCB = -0.1 DROUT = 0.5224026+PSCBE1 = 7.979323E10 PSCBE2 = 1.522921E-9 PVAG = 0.01+DELTA = 0.01 RSH = 6.8 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 7.7E-10 CGSO = 7.7E-10 CGBO = 1E-12+CJ = 1.010083E-3 PB = 0.7344298 MJ = 0.3565066+CJSW = 2.441707E-10 PBSW = 0.8005503 MJSW = 0.1327842+CJSWG = 3.3E-10 PBSWG = 0.8005503 MJSWG = 0.1327842+CF = 0 PVTH0 = 1.307195E-3 PRDSW = -5+PK2 = -1.022757E-3 WKETA = -4.466285E-4 LKETA = -9.715157E-3+PU0 = 12.2704847 PUA = 4.421816E-11 PUB = 0+PVSAT = 1.707461E3 PETA0 = 1E-4 PKETA = 2.348777E-3 )**$.MODEL TSMC180nmP PMOS ( LEVEL = 7+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.4120614+K1 = 0.5590154 K2 = 0.0353896 K3 = 0+K3B = 7.3774572 W0 = 1E-6 NLX = 1.103367E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 0.4301522 DVT1 = 0.2156888 DVT2 = 0.1+U0 = 128.7704538 UA = 1.908676E-9 UB = 1.686179E-21+UC = -9.31329E-11 VSAT = 1.658944E5 A0 = 1.6076505+AGS = 0.3740519 B0 = 1.711294E-6 B1 = 4.946873E-6+KETA = 0.0210951 A1 = 0.0244939 A2 = 1+RDSW = 127.0442882 PRWG = 0.5 PRWB = -0.5+WR = 1 WINT = 5.428484E-10 LINT = 2.468805E-8*+XL = -2E-8 XW = -1E-8+DWG = -2.453074E-8+DWB = 6.408778E-9 VOFF = -0.0974174 NFACTOR = 1.9740447+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 0.1847491 ETAB = -0.2531172+DSUB = 1.5 PCLM = 4.8842961 PDIBLC1 = 0.0156227+PDIBLC2 = 0.1 PDIBLCB = -1E-3 DROUT = 0+PSCBE1 = 1.733878E9 PSCBE2 = 5.002842E-10 PVAG = 15+DELTA = 0.01 RSH = 7.7 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 7.11E-10 CGSO = 7.11E-10 CGBO = 1E-12+CJ = 1.179334E-3 PB = 0.8545261 MJ = 0.4117753+CJSW = 2.215877E-10 PBSW = 0.6162997 MJSW = 0.2678074+CJSWG = 4.22E-10 PBSWG = 0.6162997 MJSWG = 0.2678074+CF = 0 PVTH0 = 2.283319E-3 PRDSW = 5.6431992+PK2 = 2.813503E-3 WKETA = 2.438158E-3 LKETA = -0.0116078+PU0 = -2.2514581 PUA = -7.62392E-11 PUB = 4.502298E-24+PVSAT = -50 PETA0 = 1E-4 PKETA = -1.047892E-4 )**.ENDS*$

author: Ian.M
author_rank: Super Contributor
timestamp: January 29, 2019, 05:52:09 am
content: You've got the two traces mixed up. Add a cursor to the plot of V(out)/V(in) and you'll see that the phase starts at 180 deg at low frequencies (as it should be for an inverter) and starts decreasing at about 1MHz, crossing 90 deg at 64MHz and becoming close to 0 deg from about 1GHz upwards. Meanwhile the gain is about 7.5dB at low frequencies, increasing above 1MHz to 13.8dB at 64MHz and 20dB above 1GHz.I am perplexed by the increasing gain . . .

author: promach
author_rank: Frequent Contributor
timestamp: January 29, 2019, 03:32:07 pm
content: The increasing V(out)/V(in) gain magnitude is surprising. I have no idea why. Any idea why ?the V(out)/V(in) phase is due to V(in) and V(out) acted together.I have the following an updated AC plot :

author: iMo
author_rank: Super Contributor
timestamp: January 29, 2019, 06:47:38 pm
content: I can get some amplification out of it with different L and W and Vcc.The ac analysis shows crap. The dc sweep looks ok.It could be the spice models you have imported do not match the model levels in the LTspice.

author: MrAl
author_rank: Super Contributor
timestamp: January 29, 2019, 06:49:11 pm
content: Quote from: promach on January 29, 2019, 03:42:33 amHi,Why dont you have any load connected? You should probably connect some resistive load like maybe 1k or something.With no load you might be seeing the effects of parasitics.

author: promach
author_rank: Frequent Contributor
timestamp: January 30, 2019, 01:03:01 am
content: The AC gain issue is solved by using supply voltage of 2.0V instead of just 1.0V.Could you guys comment about it ?

author: Ian.M
author_rank: Super Contributor
timestamp: January 30, 2019, 01:58:28 am
content: Its a lot saner with some parasitics added. Even 50 femtofarads across the feedback resistor makes a major difference.Here's a single file version (MOSFET .lib embedded) of the sim that steps the supply voltage over the range 1.0V to 2.0V. Its much better behaved with 50fF across the feedback resistor. I am still suspicious of it having 1.7dB gain at 10GHz, but maybe calculating appropriate parasitics for the physical layout and adding them would help with that.

author: promach
author_rank: Frequent Contributor
timestamp: January 30, 2019, 01:31:12 pm
content: See the following modification done by others

author: Ian.M
author_rank: Super Contributor
timestamp: January 30, 2019, 02:42:16 pm
content: So, that's with more parameters for the MOSFETs, which hopefully are the result of measuring off masks or die photos, not random guesswork. I assume the default parameters in the models weren't well matched to the channel dimensions you initially entered.However its still got some issues - increase the supply to 1.2V, and its still got 0.3dB gain right up at 1 Terahertz which is patently ridiculous for real silicon MOSFETs. Maybe filling in realistic values for the source area and perimeter parameters would help?

author: promach
author_rank: Frequent Contributor
timestamp: February 04, 2019, 06:13:47 am
content: The middle plot is theinput impedance, why does it start low ?

author: Ian.M
author_rank: Super Contributor
timestamp: February 04, 2019, 10:01:11 am
content: Scaling off the low frequency gain from the plot I get about 31dB, which is a voltage gain of about x 36. The feedback resistor is effectively divided by (1+gain), giving an effective input resistance of about 37K. That's not quite consistent with your input impedance plot, but is no more than one pixel out, which could be rounding errors in the plot. Use a cursor and check both the gain and the input impedance properly!You do make this hard on us by just posting screenshots, without even using measurement cursors on the waveforms. Next time if you want a quicker better answer attach the sim .asc file. If it needs any 3rd party symbols or libraries, zip them up with the asc file, so its ready to run. If it needs 3rd party models you have added to the LTspice standard model files, you need too identify them and place them as dot commands on the schematic.

author: promach
author_rank: Frequent Contributor
timestamp: February 04, 2019, 12:46:25 pm
content: See the attached asc file and mosfet library

author: Ian.M
author_rank: Super Contributor
timestamp: February 04, 2019, 01:21:15 pm
content: Yep. Changing the gain plot y axis to linear for easy measurement and using cursors, I get gain=21.36103 and input impedance=44.720659Kohm, both at 1Hz, which are consistant with the formula I posted above.If you are having difficulty understanding it, divide the feedback resistor into two series parts, one of 44720.659 ohms connected to the input and the other of 955279.341 ohms connected to the output, and consider the voltage on the node in the middle!Hint: you can share your waveform view by saving the plot settings and including the .plt file in the zip with the sim. Don't include .raw files as they get very big and are regenerated on every run.

author: promach
author_rank: Frequent Contributor
timestamp: February 06, 2019, 11:17:38 am
content: Rin = R1 / (| Gain | +1). At higher frequencies, the output capacitor reduces the gain and Rin -> R1.but why Rin drops again after 2MHz ?

author: Ian.M
author_rank: Super Contributor
timestamp: February 06, 2019, 11:41:46 am
content: You'd have to do a detailed mathematical analysis including modelling the MOSFETS to be certain, but I'd certainly expect a dropoff with increasing frequency due to the gate capacitance.

author: promach
author_rank: Frequent Contributor
timestamp: February 06, 2019, 12:41:48 pm
content: true, the small device parasitic capacitance make a pole near 2 MHz with R1=1MegBy the way, why all three waveform plots changes so much by just increasing supply voltage from 1.0V to 1.8V ?

author: promach
author_rank: Frequent Contributor
timestamp: February 09, 2019, 08:26:17 am
content: Removing the large output capacitance C1 (1n) makes more sense.1) But why input impedance starts with 44kOhm at low frequencies range ? Any way to calculate this value ?2) Besides, why the phase of the input impedance starts rising again after 200MHz to 150 degrees ?3) How would I measure overall transconductance (Gm) of this CMOS inverter using input AC current source stimulus (I1) and feedback resistor (R1) ?