strange vias in pcb design board from chinese website ( - Page 1
Forum section: electronics / projects

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 08:16:01 pm
content: I bought this PCB design (http://www.cirmall.com/circuit/3910/%E7%94%B5%E8%B7%AF%E5%BE%81%E9%9B%86%20%2B%20RGB%E8%BD%ACMIPI%E6%89%8B%E6%9C%BA%E5%B1%8F%E6%8E%A5%E5%8F%A3%E6%B5%8B%E8%AF%95%E6%9D%BF%E5%8E%9F%E7%90%86%E5%9B%BE%2BPCB%E6%BA%90%E6%96%87%E4%BB%B6)(that was very difficult. getting UK funds into a Chinese AliPay wallet).All the AliExpress sellers are out of stock of working SSD2828 boards, so I thought I'd give it a punt, since my breadboard + ssd2828 on a proto-advantage board wasn't doing anything.(turns out I can't even get an rgb-tft working from my dev board though.. sdram issue I think).Anyway, my question is, wtf is going on here ? Should I just throw this away. Why are they double-via'd and then, on the reverse side of the vias, it's not even a complete track ?Is this a total failure in PCB design, or is there a good reason for this and I'm all good to go with this PCB ? I've had a stencil and 10x PCBs made, by JLC PCB, who by the way were awesome. It got to about 03:15 am, and I just realised I had no time to think about anything any more and just wanted to send the money and get something on the way, since the AliExpress boards were unavailable, and I wasn't confident my google-translate taobao order would ever arrive (another thing I've ordered.. no sign yet).here's the pics of my main concern: sorry about the dodgy quality. it's a great microscope, but the camera is shit.

author: hendorog
author_rank: Super Contributor
timestamp: August 09, 2018, 08:29:32 pm
content: It's just the jumper track on the bottom side of the board. What am I missing?

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 08:31:17 pm
content: I just don't understand why the horizontal track in the first picture would be broken - and why have two vias through a track at all?some cad pics:

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 08:33:34 pm
content: isn't the track broken here? :?

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 08:34:51 pm
content: The jumper should only take one via shouldn't it ?

author: hendorog
author_rank: Super Contributor
timestamp: August 09, 2018, 08:36:22 pm
content: Ah the black circle? Thats just a layer of solder mask on the top isn't it?If you were to scratch all that crap off there should be copper underneath.

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 08:41:26 pm
content: Quote from: hendorog on August 09, 2018, 08:36:22 pmooh right. Is it ?Now you mention it.. yes I think you're right! So maybe it's OK!Why would the designer double-up the vias though? Two next to each other on each side? I understand it will give more copper on the insides of the PCB, but it will leave a really thin conductor around the vias won't it?

author: ataradov
author_rank: Super Contributor
timestamp: August 09, 2018, 08:48:41 pm
content: Quote from: carl0s on August 09, 2018, 08:41:26 pmIncreased current handling capability, decreased resistance. And if you have the board space, why not?And there is clearly a segment missing between the two vias, that's just an oversight, happens sometimes.Quote from: carl0s on August 09, 2018, 08:41:26 pmWhat do you mean?

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 09:16:50 pm
content: Quote from: ataradov on August 09, 2018, 08:48:41 pmWell those vias are almost as wide as thetrack itself, and leave a slither around the circle to continue to make contact with the next via?

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 09:20:08 pm
content: For some reason I was thinking light green was solder mask, and dark green was 'void'

author: ataradov
author_rank: Super Contributor
timestamp: August 09, 2018, 09:20:14 pm
content: Quote from: carl0s on August 09, 2018, 09:16:50 pmOn the pictures vias are wide enough. The thinnest part of the via is actually the transition from the horizontal to the vertical surface. The actual annular ring just has to hold itself to the board, it does not need to be huge.

author: ataradov
author_rank: Super Contributor
timestamp: August 09, 2018, 09:21:31 pm
content: Quote from: carl0s on August 09, 2018, 09:20:08 pmThe whole board is covered with solder mask here. Light green is copper (track) and dark green is the base PCB material.The place circled in red is the missing segment of the track, it is a routing mistake, nothing more.

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 09:28:25 pm
content: Quote from: ataradov on August 09, 2018, 09:21:31 pmSo that track is broken at the end? I know it shouldn't affect functionality because there is a second via before the break, but, that track is broken where it shouldn't be?

author: ataradov
author_rank: Super Contributor
timestamp: August 09, 2018, 09:39:54 pm
content: Quote from: carl0s on August 09, 2018, 09:28:25 pmCorrect. Effectively you only have one via at this place of the track.

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 09:47:22 pm
content: Quote from: ataradov on August 09, 2018, 09:39:54 pmOk that's what I first thought, and didn't inspire confidence. I would have noticed that if I was selling the design.But two vias side by side is a common thing? Rather than just making the track wider and putting a larger via?

author: wraper
author_rank: Unknown
timestamp: August 09, 2018, 09:47:56 pm
content: Quote from: carl0s on August 09, 2018, 09:28:25 pmWhen you are placing multiple vias, it's very easy to miss lacking trace between the vias. One trace is covering other when you are creating layout and connectivity check won't detect any issue as well because there is a connection already.

author: Bud
author_rank: Super Contributor
timestamp: August 09, 2018, 09:48:21 pm
content: You can see in the Altium screenshot the net name VDDIN, so appears to be a power supply trace so the current capacity was increased by placing additional vias at the ends. One via was not connected because of either designer mistake or an Altium rule which removes redundant connections and was overlooked by the designer.

author: ataradov
author_rank: Super Contributor
timestamp: August 09, 2018, 09:51:22 pm
content: Quote from: carl0s on August 09, 2018, 09:47:22 pmYes, it is better to place multiple smaller vias. You save on the number of different drill sizes. And you can put as many vias as needed. To achieve the same result with one via, you will have to multiply the diameter by the number of smaller vias, which takes up much bigger area.I do it all the time if I have to jump tracks that carry any sort of current.

author: Bud
author_rank: Super Contributor
timestamp: August 09, 2018, 09:53:21 pm
content: And by the way, welcome to the wonderful world of Chinese electronics. A run of the Design Rule Check routine would have caught the error but i guess they did not bother doing it.

author: carl0s
author_rank: Unknown
timestamp: August 09, 2018, 09:53:54 pm
content: Thanks guys! I learned a lot. It should still work + I'll make one of them, and if I see any use to make more, I'll fix that.

author: wraper
author_rank: Unknown
timestamp: August 09, 2018, 09:55:57 pm
content: Quote from: carl0s on August 09, 2018, 09:47:22 pmLarger via will take more space. Yes it's common to place multiple vias. Copper in vias is much thinner as it contains only electroplated copper while track contains both rolled copper foil and electroplated copper. Not to say electroplated copper has higher resistivity than rolled copper.

author: ataradov
author_rank: Super Contributor
timestamp: August 09, 2018, 09:56:07 pm
content: Quote from: Bud on August 09, 2018, 09:53:21 pmI doubt it. What rule is violated here?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 09, 2018, 09:59:57 pm
content: Probably they were lazy / hasty and didn't check for the little trace segment getting removed automatically during manual routing.Tim

author: langwadt
author_rank: Super Contributor
timestamp: August 09, 2018, 10:18:04 pm
content: Quote from: blueskull on August 09, 2018, 10:01:51 pmyeh, DRC wouldn't complain, it does look like pilot error rather than automatic since it only happened in one of four places

author: JS
author_rank: Frequent Contributor
timestamp: August 09, 2018, 11:08:56 pm
content: Quote from: langwadt on August 09, 2018, 10:18:04 pmLuckily, if it happened in all there wouldn't be a connection, or even in two of the same side.If the current is really needed you could scrap the mask and apply solder, vias plating is quite thin and hence they can't carry that much current. I guess it should be ok but if you spot a problem take a look at that.JS

author: langwadt
author_rank: Super Contributor
timestamp: August 10, 2018, 12:10:16 am
content: Quote from: JS on August 09, 2018, 11:08:56 pmthen DRC would complain of a missing connection

author: Siwastaja
author_rank: Super Contributor
timestamp: August 10, 2018, 07:07:42 am
content: Board matches the designer's CAD image exactly.The designer messed this up.Altium, for example, doesn't detect such an issue. You could probably configure it to detect this with a custom rule if you wanted to.

author: ConKbot
author_rank: Super Contributor
timestamp: August 10, 2018, 08:18:48 am
content: Altium loop removal is moody at times. Sometimes I can stitch away at a trace. Sometimes it's very stubborn about removing something if it's not locked. Occasionally when you're re-routing a trace on a different path and letting it clean up your mess, it gets overly aggressive, will "clean up" a branch running elsewhere and either put an airwire/ratsnest back in, or more comically, put an antenna DRC error on it.For me it's still useful enough to leave on, you just have to keep an eye on if you're doing stitched power traces. If I did more high power stuff with a lot of heavily stitched traces, it would probably get turned off for that portion.

author: carl0s
author_rank: Unknown
timestamp: August 10, 2018, 10:00:02 am
content: I had a closer look at the board today and that VDD in does run everything - two TPS7301QD adjustable LDO regulators (one down to 3.3v and one down to 1.8v), and an AZ1117CH-1.2 1.2v LDO regulator. So it's a pretty important one to reduce down to a single via like that.However there are big test points all over the board and it's easy for me to patch in at the top of a resistor or something if need be.I think he even runs a backlight at 3.3v off of that, although I won't be doing that - I just want something to help me get to grips with an SSD2828 parallel RGB to MIPI bridge. I have separate backlight drivers.

author: Siwastaja
author_rank: Super Contributor
timestamp: August 10, 2018, 10:16:06 am
content: I always turn off the Altium loop removal. It may work for a very simplistic approach where everything is a simple point-to-point connection and every signal is equal, with equal impedance requirements - i.e., no low-impedance power nets. Even in this case, I fail to see its purpose. When you do a design without loops, you have no loops to remove. If you add a "loop", you are doing it on purpose anyway, and don't want it to be removed. It should be off by default IMHO.It's very difficult to configure the DRC to catch everything and give no false positives. You could spend weeks creating your perfect rule set - in this case, you'd want to check that each via has copper connectivity on at least two layers, but it'd still fail to see intended connection onthreelayers -, and then you still want to do something in a different way. Manual checking is paramount and cannot be completely replaced.In an ideal world, this would be all driven by complex signal integrity analysis tools with SI models of all active components, all traces and vias; this would automatically tell you if one via is enough, or not, or select the trace width for power automatically. I guess we are still far from this, even with the most advanced (and expensive) tools on the market.

author: Hydron
author_rank: Super Contributor
timestamp: August 10, 2018, 05:00:10 pm
content: It would appear that all Altium users here know this issue far too well. Drives me nuts too, Altium clearly needs better heuristics for determine when a double via or similar loop is deliberate vs something that should be pruned. Is probably not an easy task but maybe the developers should tune it to be a bit more conservative.

author: daveshah
author_rank: Unknown
timestamp: August 10, 2018, 05:02:33 pm
content: Not just Altium either, had exactly the same problem with KiCad's auto-ripup in the past - I now disable it whenever doing anything like via stitching.

author: carl0s
author_rank: Unknown
timestamp: August 11, 2018, 03:03:32 am
content: Quote from: Hydron on August 10, 2018, 05:00:10 pmbut I'm sure once you know it happens, you know how to deal with it. I have done one tiny PCB design in Altium, and I quickly realised that every time I needed to re-route something, I shelved the polygons (ground in my case), did what I needed to do, then I re-poured the ground polygons, but then I had to check over everything, and re-do teardrops and things. I think I would have spotted this at the 'check all the teardrops and track connects' stage..

author: carl0s
author_rank: Unknown
timestamp: August 11, 2018, 03:05:46 am
content: Maybe I should just share the whole schematic and PCB, since I as a total newbie has found a problem.. it's hardly copyright infringement - more safeguarding ones time and investment in a supposedly professional design.

author: exmadscientist
author_rank: Frequent Contributor
timestamp: August 11, 2018, 04:48:47 am
content: For what it's worth, a Net Antenna rule in Altium will usually catch things like this, as well as various other kinds of stub.

author: Siwastaja
author_rank: Super Contributor
timestamp: August 11, 2018, 04:59:35 pm
content: Altium is full of traps "for young players". I think it takes about a year of professional daily usage on several complex projects to get past the most basic issues. I don't see a big issue with loop removal - just turn it off. It's one of the many "the defaults suck, you need to remember to change this setting on a new installation" cases. It's the things you cannot simply configure that cause more grieve.Really, it's the same for any EDA.When I'm frustrated, I have found that blaming the "broken piece of shit" software for a few minutes makes it a bit more manageable in a stressful situation, but in the end, it's the user who needs to find the workarounds and learn to use the software the way it just is.Any EDA tool development team treats its users and the bug reports like shit. Clear bugs, and lack of crucial everyday features, which would be fairly easy to fix directly in the codebase, but require enormous amount of collective workaround work, take years to get fixed. Developers take pride in their work, and it's difficult to admit being wrong. In commercial software, this is hidden behind the scenes (and multiple layers of management - I can imagine how much it sucks!), but KiCad exposes this process, and it's funny to take a look at it even if you are not an user. Look how long it took - and how much belittling the user base it took - to admit that free insertion of stiching viasisa totally basic feature, lack of which is a total showstopper; only the developer pride and impossibility of admitting of being wrong stopping this technically trivial piece of code from being accepted to the project.You just need to live with this. With Altium, you at least know it has been succesfully used in gazillions complex projects, so things work out in the end, and you'll learn.

author: carl0s
author_rank: Unknown
timestamp: August 11, 2018, 05:41:26 pm
content: Quote from: Siwastaja on August 11, 2018, 04:59:35 pmI presume the free stitching of vias thing was accepted in the end? I have installed KiCad, and made a little donation at the same time, but I haven't tried to use it yet.

author: Siwastaja
author_rank: Super Contributor
timestamp: August 12, 2018, 12:38:50 pm
content: Quote from: carl0s on August 11, 2018, 05:41:26 pmI have heard it's there now.