Custom S-parameter measurement jig for THT transistors - Page 1
Forum section: electronics / rf-microwave

author: Yansi
author_rank: Super Contributor
timestamp: May 06, 2018, 02:12:27 pm
content: Hello,due to the lack of design data for most (if not all) small signal universal and some older RF transistors, especially those older types I have loads of, I would like to measure them myself and possibly gather a small database of the s-parameters.As I can get access for some time to a decent commercial VNA, I would like to make a measurement jig for transistors. They have already one such thing there, however that is for SMT components and I am now interested more in the THT stuff.I am interested in measurement at the frequency range of 1MHz up to a few hundred, 500 at most.The plan is to make a custom PCB for that: I know that a rogers substrate would be nice, but that would not be nice to me income, so no.I will have to stick to a common "FR4" pcb type. The plan is to integrate both the short, load and through calibration kits on the same PCB, together with the measurement kit. What I do not know, if it can be done on FR4 (I guess so) and if it would be better to use CPWG (1.6mm PCB) or microstrip (0.8mm) for the signal connections. Of course I will try to keep them the shortest possible and will use SMA edge connectors. I am currently thinking of that the CPWG will be better (at least I have suitable SMA connectors for that board thickness).The supply for the base and collector circuits will be done through a pair of coaxial power feeds (MiniCircuits ZFBT whatever suitable I will get).Now the question is, how to connect the THT transistors to the PCB. Soldering is of course one way, however not if you want to test like 50 different pieces. I think I could use the hollow pins from the precision IC sockets. These could be soldered directly to the board, by the thick section, while the thin pin will get cut off (to minimize the parasitic length).I will draw some first sketch of the design and post it here for review. What do you think of this idea? How tolerant will it be about the imprecision of the impedance of the FR4 board?Thank you for any hints,Y.

author: yl3akb
author_rank: Regular Contributor
timestamp: May 06, 2018, 02:30:50 pm
content: If You have access to VNA which supports it (all professional/commercial should), check out TRL calibration. It is used especially for Your case.Example:https://www.coppermountaintech.com/content/docs/library/Design_and_Fabrication_of_a_TRL_calibration_kit.pdf

author: yl3akb
author_rank: Regular Contributor
timestamp: May 06, 2018, 02:57:21 pm
content: Although in case of low frequencies TRM calibration would be more suitable

author: Yansi
author_rank: Super Contributor
timestamp: May 06, 2018, 03:03:36 pm
content: Quote from: yl3akb on May 06, 2018, 02:57:21 pmQuote from: yansiIn fact I want to design in the TRM calibration, I wrote about it already in the first post.

author: yl3akb
author_rank: Regular Contributor
timestamp: May 06, 2018, 03:07:37 pm
content: Okay... Then I dont understand worries about FR4....

author: Yansi
author_rank: Super Contributor
timestamp: May 06, 2018, 04:48:30 pm
content: Well, if for some reason the impedance of the on board traces is marginally off (which is almost always a fact when using FR4), wouldn't that affect the measurement accuracy, even though the reference plane was calibrated to the DUT? I think it will certainly have some effect on it, won't it?Here is a sample screenshot of the PCB, used a CPWG: 1.26mm / 0.25mm on a 1.5mm thick "generic FR4" substrate. Need to add the SMA edge connectors also.The question though is, if the "through" should not be shorter by the DUT size, i.e. the hole distance for the DUT legs?

author: yl3akb
author_rank: Regular Contributor
timestamp: May 06, 2018, 05:13:19 pm
content: If You would simply extend reference planes by simple delay model, then, yes, impedance of the lines would affect the accuracy. But LMR/TRM/.. procedures are used to calculate true 12-term (or more) error model at reference planes. In other words - all imperfections within limits of reason (line Z0, loss, connectors, etc) are calibrated out.In this case 'through' is assumed to be connection with zero length. So I guess You mean correct. You should make PCB shorter accordingly for through standard.

author: Yansi
author_rank: Super Contributor
timestamp: May 06, 2018, 05:22:59 pm
content: Okay then, I can make it shorter by milling a piece of the PCB out.

author: dcarr
author_rank: Regular Contributor
timestamp: May 06, 2018, 05:37:23 pm
content: FWIW---at 500MHz (max) I think you can just use standard SOLT calibration at each port and then simple reference plane extension and get a perfectly valid result. As long as your traces are reasonably short they will be << wavelength and even low cost SMA connectors will likely be quite close to 50 ohms.

author: tfr000
author_rank: Newbie
timestamp: May 19, 2018, 11:07:42 pm
content: The jig would be nice to have, however...I have had pretty good luck tracking down old data sheets for old transistors on the web. Usually the original manufacturer published considerably more data than the current terse "voltage, current, ft, beta" listings that you see for common transistors. For instance, Motorola's original datasheet for the 2N2222:https://www.datasheets360.com/pdf/-5625760806631439232

author: Yansi
author_rank: Super Contributor
timestamp: May 21, 2018, 10:31:09 am
content: That does not list s-parameters either. And I do not know of any other way to model a transistor at moderate RF frequencies. At the low RF end (say under 30MHz??) I have heard of somy hybrid Y model. But never found how to put one together based on the datasheet figures (if it is possible at all).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 21, 2018, 02:33:44 pm
content: If you have the h-parameters, they are equivalent to any other two-port parameters.h-params are usually measured at DC or LF, so add terminal capacitances and recalculate the 2-port.You also want to make hFE a function of frequency, so that it has a pole at fT / hFE(DC) and a magnitude of 1 at fT.There are formulas for this, of course! Easiest will probably be transformation to a 2-port model where connecting impedances in parallel with respective port combinations is easier, then converting back to the Y-params, or whatever you wanted in the first place. (BTW, s-params are not quite equivalent, because they're normalized to a system impedance. Still, easy enough to convert, given that parameter.)That should give the best datasheet guess. I would not expect lead inductance to come into play for most, but you can include that of course. At such low frequencies, and with fT in a similar range, it should be negligible enough, except for precision phase or frequency uses (of course), and for ridiculously long leads (pigtails even?), and maybe for high current parts as well. (Those hot-rod audio output types, with Ic(max) = 20A, fT peak ~50MHz, and 2-3cm long leads, would be a concern here!)I've never been worried about params at low frequencies, personally. The high frequency hybrid-pi model (i.e., as described above, accounting for fT and C) seems to work out well. If you take a close look at the parameters of RF types, when they're given to lower frequencies (under 100MHz, say), and also of JFETs, the curves are very much asymptotic, corresponding to the device capacitance and DC parameters. It's simple stuff, trust me.Tim

author: Yansi
author_rank: Super Contributor
timestamp: May 21, 2018, 03:41:56 pm
content: It is not as simple to trust that, never found any useful application note, or anything about that. Typically, they start by "obtain the h-parameters" or whatever other parameters, that seem for them like to grow on trees.S-parameter measurement is for me the only option I understand enough to make use of.If you know how to for example match input/output impedance for example of a "fakin BC547" or "plan old BF199" at 100MHz, I would like to see how it is done, without using the VNA measurement. Could you give an example please?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 21, 2018, 08:53:18 pm
content: Here's an example, I guess:Note that it uses MMBTH10s, which are "RF", though not too too different from '3904s. I mainly chose them for the low Ccb (low s12 if you prefer). The higher fT is of course a boon. The oscillator is 100-130MHz; if it were scaled down to 50 or 30MHz, the circuit would work very much the same with 2N3904s (in terms of equal h_fe).Maybe not the best example, as a common-base amp is used for improved isolation; and the final (~CE) amp has low gain and wide bandwidth.For example, the filter was tuned in part by varying R13 (which varies gain as well).Performance was confirmed between measurement and simulation. The Thevenin output impedance of Q1 is very close to 10k || 1pF (represented by R1 and C1, as the part model didn't quite fit this parameter), and the filter values and Q2 input impedance were close as well (I forget what, something like 4pF || 400 ohms -- alas, I wrote it on a sheet somewhere).I mean, if all you know how to do is make pretty circles on a Smith chart...I guess you'll have to make pretty circles, and never do circuit analysis?That's all youcando, that's what you're asking for!That, or do it empirically with a jig and two bias tees.I'm sure many would be grateful for the confirmation, of having s-params for common devices. Especially for devices that are sometimes useful beyond their intended bandwidth. Like the aforementioned audio power transistors, or say, PN2369 (a switching transistor) used as RF preamp, or 2N4401 as medium power RF amp. Or noise figure data, at frequencies not normally covered, like 2N5486 at HF or LF (only VHF+ is documented), or an audio or switching JFET at HF.So, you're not at all wasting your time, I think. But it will be a lot of time to nail things down tightly, and run several parts and types, and process and package the data.Personally, I begin a design like the above pictured, by assuming the collector output is a Norton AC source: current, in parallel with a fairly high resistance and a capacitance. If grounded-base (or gate) or cascode, I ignore (AC) feedback (Ccb), and h_re is always quite small so that it isn't important at DC either. That leaves Zin, of the first base (cascode) or emitter (GB), which is modest or very low, respectively. (It doesn't take much base capacitance to turn the emitter impedance negative; it's unclear to me how you're supposed to match to this, so I ballast it up with a series emitter resistor, which also serves as termination.)Collector load impedance is matched either to the small-signal collector impedance (maximum power gain), or the operating point (maximum power output). I think I designed the above filter as a one-end-terminated prototype, though it evolved into a strange mixture of things (I have the real PCB in front of me; it has a number of tweaks missing from the schematic), due to consideration of parasitics, and ultimately, by improved experience with filter design, in part because of this example.This approach also works just fine for tetrodes and pentodes, if you're into that sort of perversion. The feedback term is quite small (usually fractional pF, even in sweep tubes), so it is only important at quite high frequency, or high gain (low bandwidth). (That said, I've seen 6AK5s needing shielding and neutralization -- they're not really IF tubes, and that circuit showed why.) The grid input is capacitive and resistive, due to the combination of cold interelectrode capacitance (datasheet value), electron beam mass (about doubles the grid capacitance between operating/cold, for high-Gm and frame grid types), and transit angle (grid resistance -- example, E180F is around 1kohm equivalent at 100MHz and 10mA Ip).Many datasheet values are inexact, or absent entirely (how often do you see excess grid capacitance, or grid conductance, specified? -- not often, and E180F is one of the few cases!), and real parts typically have enough variance that you can't possibly design a circuit, from scratch, with the most gain and selectivity possible, and no trimmers. That's why my prototypes have been refined iteratively, using the coupling/filter networks themselves as a probe to determine the amplifier's impedances, passing this data into SPICE, making further changes there, then implementing and confirming those changes IRL. This is a perfectly fine design method too, as long as allowance is made for component tolerances, and trimmers are added, when needed, and with enough adjustable range to accommodate everything.Speaking of probe networks -- for this project,https://www.seventransistorlabs.com/Images/FMRadio2.jpgI built pluggable tuning/filter/coupling networks,https://www.seventransistorlabs.com/Images/FMRadio4.jpgincluding (not pictured) some wideband, low impedance dummy networks: a 50-ohm pass-through for the input, a balun for the mixer, and a balun (180° combiner) and a common mode (0° combiner) network for the mixer output (to measure balance, LO power, feedthrough and gain). Using all of them together, the system gain is a pitiful -14dB, though when you consider that's at 50 ohms (into a ~1k grid, then out of a ~10ka-a plate), that's pretty good for these poor tubes. The bandwidth is also something like 250MHz...Incidentally, that 6J6 delivers harmonics all the way up to 800MHz. The LO is driving it nice and hard, and it's chopping pretty good. Hardly anything left up there, mind -- it's many dB down. But it's not nonexistent. It's defined by the physical limits of a tube of those dimensions, I think: where transit angle is falling over, therefore gain is nil, or even inverting. (Better is certainly possible -- see planar triodes -- which have far tighter interelectrode spacing, and proportionally higher limits. Even more still is possible, but only with distributed, free-electron methods -- TWTs.)Tim

author: G0HZU
author_rank: Super Contributor
timestamp: May 23, 2018, 12:05:05 am
content: QuoteI don't really understand what you are getting at here but taking an s parameter based model of a BJT with a VNA (even a jellybean BJT like a BC547B or 2N3904) is a classic method in RF design. I've been doing it for decades at work and I get great results when comparing simulated designs vs the real thing.The only downside is that you ideally have to take models across various voltages and collector currents. So this can easily mean taking 25 VNA models for just one BJT. If decent sdata is taken for the BJT you can do all sorts of small signal analysis on it and the sdata can be used to create or check other model types as well. Usually, the s parameter based model is king when it comes to producing an accurate small signal model of an RF BJT like this.I think Yansi should go ahead and measure that sdata and gain the experience from doing itNote that C13 (and C11?) seems to have a large value in your VCO.... typos?

author: Yansi
author_rank: Super Contributor
timestamp: June 08, 2018, 10:29:22 pm
content: Finally finished the measurement jig, added the SMAs as advertised.The through is shorter by the length of the DUT, which I suppose is the correct way it should be. Short is short, load is two 100ohm in parallel, DUT is just DUT.I will probably send it manufactured on Monday.//Yes it probably is a via overkill for those few hundred MHz, but why not?

author: G0HZU
author_rank: Super Contributor
timestamp: June 08, 2018, 11:02:24 pm
content: My advice would be to also make another mini PCB for SOT23 parts and another for the passive 0603 footprint. Also, make two mini PCBs that can be configured as bias tees. I think the coaxial bias tees from Minicircuits will be quite lossy at LF and not something I would choose to use even though the VNA can largely calibrate out the bias tee.Also, check the rear panel of the VNA at work. Does it already have bias tee ports? Usually there will be a BNC connector for the external bias for each port and a dedicated screw in fuse for the bias tee connection.

author: Yansi
author_rank: Super Contributor
timestamp: June 08, 2018, 11:42:09 pm
content: I don't think the VNA I have access to supports such biasing, but will check. There was already someone's setup for SOT23 and 0603 (but he didn't want to let me use it. I will make my own.Yes, there are MiniCircuits bias tees. I don't know exactly which ones, but I remember they were rated up to 3GHz, so no good at LF probably. I have a bunch of mine, that are I think 1MHz to 1GHz rated. A bit better. Still not pretty, may be good enough.

author: G0HZU
author_rank: Super Contributor
timestamp: June 08, 2018, 11:44:31 pm
content: Quote from: dcarr on May 06, 2018, 05:37:23 pmFor jellybean BJT parts I've done it that way quite few times. I used SMA PCB end launchers with a known time delay and I didn't even bother with a PCB for some transistors. I did a basic full two port SOLT calibration and took out the delay in the SMA end launchers to set the reference plane right at the legs of the BJT.eg see the plot below for a classic old AF117 Germanium BJT. Earlier this year I measured s2p data for this device at various operating points and then processed the data to produce a prediction for beta vs frequency and Ft and the predicted max (stable) gain vs frequency.The image below shows how I quickly used my s2p data for the AF117 at 7Vce and 2mA to design a basic RF amp at 70MHz. Then I built the amp for real and compared the results on Genesys. The plots show predicted plots for gain and input and output impedance alongside plots for real measurements of the real (complete) 70MHz amplifier measured on a VNA. The results agree very closely and the traces almost overlap perfectly for the simulation using my s2p model and for the real 70MHz amp built on a PCB and biased at 7Vce and 2mA Ic.Each plot has 4 traces even though it looks like there are only two. On the Z complex plot for the output impedance the traces don't agree up at 150MHz but that will be because I only used a basic model for the inductor in the collector.