Advice on high-speed ADC layout - Page 1
Forum section: electronics / projects

author: mbless
author_rank: Regular Contributor
timestamp: January 11, 2021, 09:17:09 pm
content: I have a 12-bit 66 MSPS ADC (ADC12L066,datasheet) that I’m interfacing with a STM32H730VB MCU (datasheet). The MCU will use the DCMI peripheral to read the data from the ADC. Both the ADC and DCMI will be driven by a 50% duty cycle PWM timer output producing the clock signal. The ADC requires fall/rise times < 2 ns, so that puts the edge frequency at 500 MHz. The MCU datasheet shows rise/fall times down to 1.5 ns and 80 MHz sample rate for the DCMI peripheral. I have not worked with anything this high-speed, so I am seeking input on the layout.Here is the preliminary version of the layout. Top layer (green).Bottom layer (red).It’s a 4-layer board with solid ground planes on the 2 inner layers, so it can have better signal quality and use impedance control on the top and bottom layer. The MCU is on the top layer with the ADC on the bottom. The data lines are the 12 upper traces, and the clock is the lower trace. The ADC has all 12 data pins in consecutive order, but the MCU’s DCMI interface is out of order. Here are some questions I have encountered.• Trace impedance: I set all the traces to have 50Ω impedance for consistency, but I don’t know if that is necessary or not. Neither the MCU or ADC specifically list output/input impedance but using output voltage and current specs to calculate to the impedance it is 50-100Ω for the MCU and 250-360Ω for the ADC. I put in source termination resistors, but I would just be guessing what value to use. (The ADC datasheet just says to use 100Ω resistors.)• I haven’t found anything definitive on via impedance. There are some articles like this one fromKeysightthat show using multiple ground vias around the signal via to maintain consistent impedance.• Is any of this really necessary for <1 GHz? From what I have seen, and according to the ADC datasheet, I don’t need termination if the trace length is less than t_rise / (6* t_propagation), which is 5.5 cm for 2 ns rise time and 2.7 cm for 1 ns rise time. My longest trace is the clock at 2.1 cm. Presumably I don’t need matched trace lengths either then.• Data line trace clearance: For the data lines I did not increase clearance between the other data lines. Normally it is recommended for high-speed signals to have more clearance due to crosstalk, but since all the data are simultaneously driven that should not be an issue. Is that a correct assessment?• The clock line is a separate signal, so I believe I need more clearance for it. TI says 5*trace width, but the trace width is 0.29 mm, so the clearance would be a ridiculous 1.45 mm. I could use a stackup with closer planes that would reduce the trace width to 0.15 mm and the 5x clearance to 0.73 mm.• Right angles in a trace are bad for high-speed signals. Does that also apply when the trace pass through a via? This image shows a trace being at right angles on the top and bottom layer. Is that bad so that I change it to be like the top right trace where the top and bottom traces are not perpendicular?

author: thm_w
author_rank: Super Contributor
timestamp: January 11, 2021, 11:28:10 pm
content: QuoteRight angles not going to matter at 80MHz. With the via its more about inductance/trace length matching.https://www.nwengineeringllc.com/article/right-angle-pcb-traces-its-time-to-kill-the-myths.phpQuote from: mbless on January 11, 2021, 09:17:09 pmThey specifically say why the 100R resistors are used in the datasheet:QuoteI would be tempted to place the two ICs further apart, unless there is some need to make a tiny board.

author: mbless
author_rank: Regular Contributor
timestamp: January 12, 2021, 02:46:39 am
content: Quote from: thm_w on January 11, 2021, 11:28:10 pmThat was a good, quick read. Thank you.Quote from: thm_w on January 11, 2021, 11:28:10 pmYes, but it doesn't address trace impedance matching. Should the trace impedance be 100, 150Ω, etc.?Quote from: thm_w on January 11, 2021, 11:28:10 pmCan you expand on why? So they don't overlap? Unfortunately I only have a millimeter or 2 that I can shift things around, but I'm curious to hear what you are thinking.

author: thm_w
author_rank: Super Contributor
timestamp: January 13, 2021, 11:10:39 pm
content: 80 MSPS on data output likely not high enough that impedance is going to matter much. 50-100R seems reasonable.Quote from: mbless on January 12, 2021, 02:46:39 amIf the space isn't available yeah nothing you can do. Just have to build it and see.I was concerned about any switching/noise coming from the micro coupling to the ADC. That was with the assumption you'd be running a bunch of other signals off the micro though (USB, etc).

author: Siwastaja
author_rank: Super Contributor
timestamp: January 14, 2021, 07:12:47 am
content: Using R = transmission line impedance gives maximum possible edge rate without overshooting (remember to subtract the CMOS driver Rds_on, use minimum possible value, 10-15 ohms would be a good start, so some 33 ohms external for 50 ohm traces). Neither of the ICs are actually impedance matched, though. Using higher R is only good for EMI, as long as the slowed-down edges are still fast enough. Experiment and measure for optimum R. If 100R is recommended, start with it, and use a smaller value only if you measure an issue with too slow edges for reliable communications. You can also increase the R on the prototype until communication stops working and then step back - quite a bit! For example, if it fails on lab table with R=470 ohms, 100 ohms would be a good idea, likely.Fast digital return currents run in the ground plane right below the MCU. That's why a different placement would be better for analog noise performance.

author: mbless
author_rank: Regular Contributor
timestamp: January 15, 2021, 03:00:51 pm
content: Quote from: Siwastaja on January 14, 2021, 07:12:47 amThose are some good ideas! I don't have a scope capable of capturing the edges, so I would have to do it experimentally like you said.Quote from: Siwastaja on January 14, 2021, 07:12:47 amQuote from: thm_w on January 13, 2021, 11:10:39 pmFortunately the only other fast signal in the area is the clock. The MCU essentially just runs the ADC.

author: Marchewa
author_rank: Newbie
timestamp: January 15, 2021, 08:02:31 pm
content: First of all, its only 66MHz Cmos. There is only few things that could go wrong. You probably dont need to care about length maching etc. Remember to place ground VIAs for return current close to signal VIAs. Resistors are there for the less reflections and noise, so they should have the same resistance (+ device output resistance) as impedance of the tracks. If you are using 50ohm tracks, than you can use 50ohm resistors. With tracks this short bigger resistance may be ok but i still prefer to match the impedance. You dont want to have reflected signal in your tracks.Another thing.This ADC is from "SNAS153I –NOVEMBER2001–REVISED MARCH 2013". Its basically an antique at this point so you dont need to do the same thing as datasheet tells you to do. A lot of this info is outdated. For example if it were me i would do power part in a different way and think if i rly need separate GND.Ps. 1.2ps jitter

author: jonpaul
author_rank: Super Contributor
timestamp: January 15, 2021, 09:29:16 pm
content: Best references are from Dr Howard Johnson: High Speed Digital Design: A Handbook of Black Magic 1st Editionby Howard Johnson (Author),https://www.amazon.com/High-Speed-Digital-Design-Handbook/dp/0133957241http://www.sigcon.com/Jon