Sanity check regarding transformer design, please - Page 1
Forum section: electronics / general

author: Sniper1
author_rank: Regular Contributor
timestamp: June 24, 2025, 06:06:39 pm
content: So this is my first time designing a high power transformer, last time it was like 10 W and i was like way off in terms of inductance ( math was off ).So i am posting here since this time this is way more dangerous and it is in a larger design so i am sort of want to have something at least functional this time, first try maybe not full power maybe not full voltage range but at leat to work at nominal at lets say 50% . Last time i had like 1/2- 1/3 the inductance i needed and tons of leakage inductance and it ended in a mess.So here is the design details:topology Full bridge 500 kHz switching ( so fets work at like 250kHz) transformer is planar designVin 300V+ mostly 380-410vDc 390Vdc nominal ( 300vdc since it will start with that and then powers the APFC stage that gives 390v nominal, the APFC stage works and it was tested a bit already in another design)Vout 48V nominal maybe 55-60V to compensate cables @ 5A ( i would be happy with 1A min first try)On the secondary i will have a centre taped winding and there is a bias winding that feeds the APFC with about 12 V ( it accepts max 22v but i sort of need 10.5-11.5 min to be same so maybe 12 is a bit to close )So according to my math at nominal i would need 6: 1 :0.25 transformer or rather 24 pri / 4 sec / 1-2 auxAccording to TI datasheet i would need about 2.5 mH. So i want to did the math for a ton of cores that fit my size restrains and are available online.Here is what i ended up with : EI Core: ELP 22/6/16 Material: N95https://www.tdk-electronics.tdk.com/inf/80/db/fer/elp_22_6_16.pdfhttps://www.tdk-electronics.tdk.com/inf/80/db/fer/elp_22_6_16.pdfwhy N95 , because the winding number looked great on paper : 20.2 → 20 3.4 → 3BUT if i round up i get 22 / 4 ( 5.5 / 1 ratio ) and that looks way better since it can be made symmetrical and have 2 winding per layer.IF i redo all the math in reverse i get 2.95 mH primary inductance withBpeak​=Np​⋅Ae​V⋅ton​​Bpeak=400⋅1×10−622⋅78.5×10−6=4001.727≈0.232 TBpeak​=22⋅78.5×10−6400⋅1×10−6​=1.727400​≈0.232 T​So i dont think it will saturateBUT now my ratio is 5.5/1 i am not sure if this is ok on one hand yea i can compensate a bit more in terms of loses but then again will i even have loses that big?So here is the alternative: 24 / 4 here i keep the ratio and increase the primary winding number.So here is what i get ( with the same core and material) :Lp​=Np2​⋅AL​=242⋅6100=576⋅6100=3,513,600 nH=3.51 mH​Bpeak​=Np​⋅Ae​V⋅ton​​=24⋅78.5×10−6400⋅1×10−6​=1.884400​≈0.212 T​More inductance on the primary should be a good things since it will theoretically enable me to lower my switching frequency or deliver more power. but for now ill be very happy to just get part of what i design for.So here is my dilemmas:A) Should i use 22 or 24 wingdings on the primary? I sort of excluded 23 since i cant get that with a symmetrical transformer design . Or maybe have 23 and also have the bias winding on that layer instead of an additional primary winding?B) Regarding the aux i am again not sure if i should use 1 or 2 winding, 1 m,ay be to little to power my APFC but 2 is a bit to much tho i can use a resistor and zener to clamp it to 20 V ish but i am afraid not to make a heating element . Here i am sort of leaning heavily on 2 windings but i am still sceptic since it is low power i have a bit more options.C) What PCB trace width should i use for the transformer ? Should i go with 1mm/ 1 Arms?D) Am i even close to reality? Last time i was way of in winding number ( tho then i had air gap and that might have also been part of my problems since i might have also added extra air gap with glue.NOTE: Transformer is planar since i have 10 mm height for the entire design due to mechanical constraints ( and it also helps with electrical safety since it is easier to check since stuff is not touching randomly).I find it easier to design and it sort of makes me feel safer, since hand winding something like that makes me super nervous and 400 Vdc is SUPER DANGEROUS.With that core i have 3.2 mm so basically 2 PCBs will have all the windings, based on width i think i can get away with 6-8 layers per PCB .Sorry of my tone sounded sad or to pessimistic, i am just coming from a few failed designs and i sort of lost my confidence + this time the voltages are also dangerous so there is even less margin for error.THX in advance for your help.

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 25, 2025, 01:21:49 pm
content: There's a lot to go over there, I'll just start with the turns ratios.You mention using a center tapped secondary. Therefore with a 6:1 turns ratio, the voltage ratio will actually be 12:1, so with a 400V primary you can't possibly get 48V out.Even with full wave rectifier on the secondary side, a 6:1 turns ratio does not leave you with much headroom for responding to transient conditions.Do you have a holdup spec? That can also necessitate more headroom on turns ratio.Quote from: Sniper1 on June 24, 2025, 06:06:39 pmSo you're saying the PFC front end won't start operating until the DCDC is active to provide its aux supply? That's odd, I hope you have thought thoroughly about your worst case starting conditions... I agree that with 300V in, a 24:1 ratio for the aux winding is quite marginal...

author: Sniper1
author_rank: Regular Contributor
timestamp: June 25, 2025, 06:40:37 pm
content: Quote from: mtwieg on June 25, 2025, 01:21:49 pmYes the APFC IC is powered from another later stage in all reference designs , i also added some footrpints for effectively a high voltage LDO to help with start up if things dont go well.Regarding how all fits together i attached the datasheet simplified schematic.Also when i am talking about the secondary as being 6:1 i was referring to 2 of them so yea it also can be called 12:1 if you count turns between the 2 ends that get rectified.With 6:1 i was thinking it was ok since at nominal i get 390/6 = 65 way way more then nominal 48 with a lot of headroom for loses even if i go for 60V out ( or so i think in my mind).I am bad at explaining so in a way i am posting a picture since i cant express in words well this stuff.Regarding: ``` Do you have a holdup spec? That can also necessitate more headroom on turns ratio.``` more or less 10ms there are is like 660uF capacitance at 390V on the DC buss i calculated that for my APFC stage and should* be enough , then again adding more capsis way easyer but yea i sort of understand what you mean that at power loss i need to run at lower voltages and still deliver max power.I sort of forgot about this since i am a bit on the overwhelmed side as of now and would be super happy to get this to run at max power first try.So yea i am not in the best shape as now.....

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 26, 2025, 12:12:02 pm
content: QuoteHere are a few acceptable ways to describe a transformer with 24 primary turns and a center tapped secondary with 8 turns total:24:8CT24:4+424:4:4 (if the secondary is split into two separate windings on the bobbin).Describing it as "12:1" or "6:1" is confusing because it doesn't describe the actual turns ratio.QuoteIf the max output power is ~240W then 660uF at 400V should hold up fine for 10ms.Do you have a simulation model of the converter? If not, I strongly suggest creating one, it would be very useful for many purposes besides transformer design. Depending on what you want to do, the model does not have to be very detailed. Simulations are usually how I gain confidence in my designs. In many cases simulation is more useful than actual experimentation. Breaking a simulation is much less costly than breaking real hardware.

author: Sniper1
author_rank: Regular Contributor
timestamp: June 26, 2025, 06:42:24 pm
content: Quote from: mtwieg on June 26, 2025, 12:12:02 pmOf so to reiterate:My transformer is 24:8CT i got the 6/1 ratio from TI calculator and then based on that did math to determine the turns needed for inductance in the primary and then that TXT wall at the beginning and i got 22:8CT or 24:8CT as potential results.I honestly got so used to N:1 transformer type from uni and all alth in datasheets so i didnt even think abot why i should not simplyfy the fraction, BIG off on me.Regarding APFC caps yea i expected to be fine since this part was designed with 500W in mind and TI had a capacitor calculator , besides the SMPS that i am making now there is another one that draws power from that same APFC it is a LLC and i cant get it to work .There is no TI spice model and only an XCEL calculator that i followed , as of now it is not my main priority since TI will release soon a better version of that LLC chip that is also pin compatible so maybe there was something off in it to begin with .Also that new one may have a SPICE model.So as of now APFC is way overbuilt and i didnt bother to downscale it since.Regarding simulation of this design i am trying but failing TI provided Pspice model that i am trying to migrate to LTspice or Qspicehttps://www.eevblog.com/forum/projects/help-migrateing-spice-model-from-psipe-to-qspice/new/#newIt does not error out but still nothing happens , nothing even tries to switch.Even if it starts to work the data regarding the transformer will be based on the transformer i calculated here, and last time i tried to design a transformer i was waaaay of in terms of inductance ( it was flybacks well distance inaccuracies may be been a part too but if i remember well it was systematically 1/ or 1/3 of what it was supposed to be so i heavily suspect a calculation problem on my side). GPT thinks math is correct but it hallucinates on may simpler stuff so it is not that comforting.I got primary inductance value from TI calculator so should be ok but man my transformer design scares me since it is planar it is not that easy to adjust later.

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 27, 2025, 03:46:21 pm
content: Quote from: Sniper1 on June 26, 2025, 06:42:24 pmOh yeah that was your thread. I did actually get a simple LTspice model working, based on figure 19 of that LM5046 datasheet. See attached. Overall it seems to function, but there are definitely some convergence issues which make the simulation run very slowly, and sometimes stall completely. Not sure if it's in the LM5046 subcircuit, or in the external circuitry.

author: Sniper1
author_rank: Regular Contributor
timestamp: June 27, 2025, 08:34:44 pm
content: Quote from: mtwieg on June 27, 2025, 03:46:21 pmWOW THXill play with it this week end,Inside i didnt see anything that wild maybe it was the Pspice syntax ( not sure yet what u did in there)Slow is still ok since i can leave a few running in parallel and get progress , i expect it is a few floating nodes that have some odd transient behaviour.

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 27, 2025, 09:16:26 pm
content: I did not change anything inside the lib file. I didn't see any Pspice-specific syntax. But it's possible there is something in there which should change and I missed it (usually I would expect LTspice to emit an error though).But there's something about the way the model was implemented doesn't play nice with LTspice's solver. The simulation speed frequently dropped from ~10us/s to <100ns/s. I'm betting this depends on subtle factors like the solver settings, and maybe even the version of LTspice being run (I'm running 24.1.9). I also tried using the debugtran option and it reports to stuff inside the LM5046 model as the main challenge with convergence.

author: mzzj
author_rank: Super Contributor
timestamp: June 28, 2025, 09:46:44 pm
content: Your flux density and frequency seem rather high on quick glance. Have you checked you core losses and cooling?

author: Sniper1
author_rank: Regular Contributor
timestamp: June 29, 2025, 05:21:32 pm
content: Quote from: mzzj on June 28, 2025, 09:46:44 pmEI set parameters:Magnetic characteristics (per set)l/A = 0.33 mm –1l e = 26.1 mmAe = 78.5 mm2Amin = 77.9 mm2Ve = 2050 mm 3Primary Inductance 3.51 mHPeak Flux Density 0.212 TAnd based on the material datasheet that is 3000 kW/m^3So Core loss = 6.15 W +- something not even sure if that is a lot of not since at max power i will be at like 250W so that is like 2.4%Then again my Lmag target was 2.5mH and i get 3.5mH i have some leeway and i could potentially drop my switching frequency to 400-450kHzThen again i am not even sure if i chose the right curve for my math since 500kHz is that the output inductor will experience but my FETs will switch at half that and IF i look at 250kh in the loses table it is about 1/2 the loses tho i am not surprised about that.This is very arcane territory for me .Regarding cooling plann as of now it mostly convection but the enclosure has a 12V fan that is like 10cm diameter so i think it should work ok ish.....This is also my first high power transformer design so maybe i am forcing or streaking performances here and there. then again i can reduce frequency if need be.My main problem is that i am not sure what frequency to use when calculating core loses so i went with the worst case.In a way lets sau i enter the transformer as a sine with 400 Vpk 800 Vpp at 250 kHz, and then after rectification i end up with DC+ ripple at 500 kHz.Should i use 250 or 500Khz for transformer loses? in a way it is not a sine and the FSFB waveform is sort of complex but not near as bad as 500KHz.What would you do in this instance when it comes to math?https://www.tdk-electronics.tdk.com/download/540200/0fe9e667e8e8afa649f776a2a5a7eb0a/pdf-n95.pdf

author: Sniper1
author_rank: Regular Contributor
timestamp: June 29, 2025, 06:30:32 pm
content: Quote from: mtwieg on June 27, 2025, 09:16:26 pmI tried to run the files u sent but somehow it tries to find a file somewhere in YOUR downloads folder .I ll try a few more things .And yes it is in the same folder and i uset unarhived the file in a folder.Also when i tried to convert the model i looked at:Code:*subckt.MODEL Dnom D IS=100n RS=30m CJO=10p VJ=0.5 EG=0.6.MODEL S5K VSWITCH RON=1 ROFF=100E6 VON=1V VOFF=0.0V.MODEL SWCLAMP VSWITCH RON=0.001 ROFF=100E6 VON=10m VOFF=0.MODEL SdriverT VSWITCH RON=2.7 ROFF=1E6 VON=2.6V VOFF=2.4V.MODEL SdriverB VSWITCH RON=1E6 ROFF=1.6 VON=2.6V VOFF=2.4V.MODEL SdriverSRT VSWITCH RON=17 ROFF=1E6 VON=2.6V VOFF=2.4V.MODEL SdriverSRB VSWITCH RON=1E6 ROFF=5 VON=2.6V VOFF=2.4V.MODEL NOMNPN NPN RB=350 RC=600 RE=20.ENDS LM5046*$* RSFF.SUBCKT RSFF5K R S Q NQEff1 PSTATE 0 VALUE { if(V(R)>2.5 & V(S)<=2.5,0,if(V(R)<=2.5 & V(S)>2.5,5,2.5)) }Rff1 STATE PSTATE 500Cff1 STATE 0 9p IC=0Eff2 PQ 0 VALUE {if(V(STATE)>=4.5,5,if(V(STATE)<=0.5,0,if(V(FFMEM)>2.5,5,0))) }Rff2 Q PQ 500Cff2 Q 0 12p IC=0Eff3 PNQ 0 VALUE {if(V(STATE)>=4.5,0,if(V(STATE)<=0.5,5,if(V(FFMEM)>2.5,0,5))) }PS useing same LTspice version

author: Sniper1
author_rank: Regular Contributor
timestamp: June 29, 2025, 07:02:01 pm
content: AND i did some math regarding the heating of the code at 32 C/W amn it will get for fast at 6W even at 3W it can get super hot......So i am again stuck . Should i try another material and estimate the loses?Also is my inductance math even ok to begin with?

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 30, 2025, 02:14:38 pm
content: Quote from: Sniper1 on June 29, 2025, 06:30:32 pmHmm that's weird. When I tried to run the files I also saw that there was an absolute path in the netlist... not sure how, since I removed it from the symbol file....Try the files attached, it solved that problem for me.Quote from: Sniper1 on June 29, 2025, 07:02:01 pmYeah as mzzj pointed out, a Bpk of 0.2T (Bp-p of 0.4T) is very high for 500kHz. IIRC N95 is more for 100-200kHz range. Something like N49 or 79, or maybe even PC200 or 80, would probably give a decent improvement. But you will still have to reduce Bpk.

author: Sniper1
author_rank: Regular Contributor
timestamp: June 30, 2025, 07:41:38 pm
content: Quote from: mtwieg on June 30, 2025, 02:14:38 pmThis time it runs like 10us/ s on my CPU, man that is slow but it is running. THXI think i have a few ides why it runs so slow: Vcc was suposed to be tied to 12-15V but it floats and there is an LDO inside so probably that acts oddly since technically it should be just for the start and Vcc fluctuates around 7-8Venough to switch FEts but maybe it is messing with stuff inside since Vcc min is 10V so maybe something inside is not that happy and maybe browning out periodicallyBesides that there was the current FB that is implemented with a current source not a shunt/ transformer that might have to do something with it all + the 1 ohm resistorAnyway now i have something that runs! Again hwo did u even make that run LOLRegarding the transformer yea maybe not the best material choice, i used this paragraph when picking material:```For many standard applications up to 100 kHz, materials N27, N41 and N72 can be used. For therange up to 500 kHz, materials N92, N87, N88, N95, N96 and N97 are suitable. N49 covers the rangefrom 300 kHz to 1 MHz, PC200 to 4 MHz e.g. for DC/DC (resonance) converters.```I ll do the math and see what i get with another material ( i dont have that much hope when it comes to reducing switching frequency, or rather not enough ) so new material it is.Regarding my math for this core i chose , was it at least correct? asking since IF my process is correct then it is just a repeating thing i need to test.PS based on the thermal C/W i can afford to have loses of about 2W max +- something and some extra cooling

author: Sniper1
author_rank: Regular Contributor
timestamp: June 30, 2025, 07:59:05 pm
content: added 13V for on the Vcc rail with a diode like the datasheet, may the simulation faster but still averaging like 30us /sAlso the 2 sync rectifier outputs overlap and i dont think it should be like that .....Then again i didnt check the passive valuesAnyway my HDD and CPU can work and i can test stuff + might also try to also do magnetic simulation to calculate the real flux density

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 01, 2025, 05:09:04 pm
content: Quote from: Sniper1 on June 30, 2025, 07:41:38 pmYeah I tried sourcing Vcc with a separate voltage source but didn't notice any improvement.QuoteGenerally I try and replace things like transformer and optocouplers with dependent sources in order to simplify the simulation. Depends what sort of behavior I'm actually interested in simulating. For example if I want to simulate feedback stability but don't care about realistic power efficiency then I might replace the power semiconductors with voltage-controlled switches or ideal diodes.QuoteGetting the LM5046 model itself to run (slow and janky) was trivial. Again, just needed to create a symbol and include the .lib file. On the other hand, I spent a couple hours trying to prevent its output from overshooting terrible at startup. Still sucks but probably not a big deal for your purposes.QuoteAlternatively, you could increase the number of turns (on all windings) to reduce Bpk. I expect you will need to do this even if you pick an optimal material (unless you also choose a core with a larger Ae).QuoteI hadn't looked at the core selection math. That's usually a messy optimization, one I don't bother with until other basic things like turn ratios and switching frequency are locked down.Regarding the SR signals, they look fine to me. Overlap is expected, per the datasheet.

author: Sniper1
author_rank: Regular Contributor
timestamp: July 01, 2025, 07:46:01 pm
content: Quote from: mtwieg on July 01, 2025, 05:09:04 pmAt page 19 in Fig 13 it shows clearly they should be mostly out of phase with each other , or at least mostly .Anyway regarding the transformer: ill iterate and see what i getAs of now i have 24/4+4 i have inductance to spare so i can try a few other cores in the same shape and or play with lowering the frequency .Alternatively ill go to 30/5+5 ( not sure how practical this is for planar tho i can see myself putting the aux here easyer.) or 36/ 6+6 ( man that is a lot of turns on the primary)Well with more turns there will be more inductance to use so lower frequency too so in a way that can help too)I ll have to make an excell with all the combinations and see what is best at the end...PS transformer experiences 250kHz not 500kHz so i am at 3W loses so about 100C temp rise so i might be fine with just some small adjustmentsI ll write in a few days here my NEW* optimised transformer.Regarding current sensing i was thinking of a shunt like on the low side on the H bridge. ( might not the best in practice but simple for SPICE).Regarding simulation speed: i think it may have to do something with how GND is tied , there is no GND pin and inside 0 is the real GND note, ill try to make a very modified copy with 0 node renamed to GND and an extra pin.Actualy now i remember that i did that change in th einitial posted file, ill try to then add GND to the symbol u made and see how it goes

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 02, 2025, 01:21:39 pm
content: Quote from: Sniper1 on July 01, 2025, 07:46:01 pmRight, out of phase, but they also overlap. In the LTspice sim, I see that once the circuit reaches steady state (SS and SSSR both have finished charging), all the waveforms match up exactly with figure 13.However, if you look at the SR waveforms while SSSR is still charging, they look like figure 14a. I'm not sure why the chip operates like this, but the model seems to agree with the datasheet.QuoteLowering the switching frequency (while making no other changes) will increase core losses, not decrease them.Have you attempted to estimate winding losses? Not sure how one would approach this for planar transformers. Most nomographs of winding loss and Rac will be derived from round wire or foil wound on bobbins, and won't apply to PCB traces on a planar transformer...QuoteYes, spreadsheets are good.QuoteOh duh, had the transformer confused with the filter choke. So yeah N95 might be fine.QuoteI really doubt that will help. It's pretty normal for subcircuits to use the global 0 net everywhere. It's only an issue if you need to reference the model to another net (which will make things much more complicated and slow).I did find one major improvement: if you change the definition of SWCLAMP to have RON=0.1 instead of R=0.001, this makes things run much more smoothly, and AFAIK has no significant impact on simulation results. Still not super fast, but it doesn't get snagged at random points.

author: Sniper1
author_rank: Regular Contributor
timestamp: July 06, 2025, 08:33:30 pm
content: Quote from: mtwieg on July 02, 2025, 01:21:39 pmHere is the spread sheet :( also ateched fo easyer reference since man formating went bad here)core material Ve [mm^3] loses [kW/m^3] turns Primary inductance  Flux density  Loses  Delta temp CELP 22/6/16 N95 2050 1500 24:4 3,5 0,21 3,075 101,475ELP 22/6/16 N95 2050 600 30:5 5,5 0,17 1,23 40,59ELP 22/6/16 N95 2050 500 36:6 7,9 0,14 1,025 33,825ELP 22/6/16 N97 2050 1600 24:4 3,5 0,21 3,28 108,24ELP 22/6/16 N97 2050 1000 30:5 4,7 0,17 2,05 67,65ELP 22/6/16 N97 2050 700 36:6 6,8 0,14 1,435 47,355TLDR N95 seems the best but i need to add an extra turn on the secondary, tho 40 C temp rise is not the best it is safe since i will have a fan anyway and ambient is sort of cool anyway .so 30:5+5 seems to be the winner , as for the secondaries i was wandering if i should use 1 or 2 now it is heavy bias on 2 since i would get 48/5*2 so about 19V - loses and diode rectification i should be ok , if need be even add LDO or zener regulator to drop it to safe gate voltages , also alternative is 9.5v so a bit low for gate drives but enough it need be , maybe ill use a resistor to add or remove a turn...Also i need these bias windings for both sides .What do you think should i continue with 30:5+5 ?

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 07, 2025, 12:17:24 pm
content: Quote from: Sniper1 on July 06, 2025, 08:33:30 pmHere's what I get for just the first row:1. For Bpk and core losses, need to first establish the volt-time product. For Vin=400V, Vout=48V, Np/Ns=6, and fsw=250kHz, I get vt=5.76e-4 v*s. Ae=78.5 mm^3. So for Np=24, I calculate Bpp = 0.307 T and Bpk=0.153T.2. Even assuming your Bpk=0.21T is correct, the Pv at 250kHz should be more like >2000 kW/m3 (actually need to extrapolate the N95 datasheet curves in frequency a bit). At Bpk=0.153T, probably more like 1100 kW/m3.3. For Pv=1100 kW/m3, total Pc would be 2.26W.4. Datasheet doesn't provide a way to estimate temperature rise, but suggests a maximum Pc of 1.25W at 25C ambient.For the second row I get Bpk=0.123T, Pv=600 kW/m3, and Pc=1.23W. More in line with the datasheet's suggestion.

author: Sniper1
author_rank: Regular Contributor
timestamp: July 07, 2025, 07:43:53 pm
content: Quote from: mtwieg on July 07, 2025, 12:17:24 pmI found some data regarding thermal resistance and cores here:https://www.e-magnetica.pl/doku.php/thermal_resistance_of_ferrite_cores... as for cooling i will have a fan so i have some more marginSo you say row 2 is a reasonable transformer design ? or at least something that will work decently most of the time?If yes then i can try and use that for simulations and see how stuff goes from there . i effectively have 2 1.6mm PCB for windings so ill think how to spread the turns and see how it goes , JLC seems not to change price if i go for 1mm so 3 1mm PCB are also on the table tho this way will be way harder to assemble and properly design .

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 08, 2025, 12:31:02 pm
content: Quote from: Sniper1 on July 07, 2025, 07:43:53 pmAt this point one would normally also estimate winding losses and check that they are similar to core losses before moving forward. However for planar designs it seems that there isn't a wealth of nomographs available that one can use to estimate/optimize winding losses... so you may have to make your best guess on winding design and measure it experimentally.I personally would go for a 24:5+5 or 30:6+6, to allow for better handling of line dips and/or load transients. Also will reduce core losses a bit more.Also if this is for a real product I would strongly look into safety/certification aspects before going too much further (I'm guessing this transformer is going to comprise the protective insulation in a AC-DC power supply, meaning this will be necessary). One does not often see planar transformers used as protective insulation, and I'm not familiar with what tricks designer pull off to meet safety standards with planar designs. But it may throw a wrench in your plans at some point...

author: Sniper1
author_rank: Regular Contributor
timestamp: July 08, 2025, 05:30:32 pm
content: Quote from: mtwieg on July 08, 2025, 12:31:02 pmWhy 24:5+5? and 30:6+6? my turns ratio would ideally be 6n:n +n and what you propose it like 5n:n+n i dont understand the logic.Can you please explain why i should go for 5n:n+n and not 6n:n+n? what is your train of thought? Regarding winding loses, well it depndsTM i need to design and then use estimate ESR and parasitic to estimate losesRegarding safety yea and now, i did study some high voltage safety requirements but not for AC-DC specifically. I saw some planar transformer in some GaN USB chargers so why not ?And yea this revision is mostly for learning since i never designed something this powerful before yet alone transformers but it it works it could be a good starting point. As for personal safety yea i am taking care of that.As of now the most concearning part for me is the inductance value for the primary since there i messed up big time last time. Since it is PSFB leakage inductance is not a problem it is actually good up to some point.

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 08, 2025, 10:43:52 pm
content: Quote from: Sniper1 on July 08, 2025, 05:30:32 pmFor your nominal conditions (Vin=400V, Vout=48V), that means your duty cycle would be 0.72 (referring to the secondary side). But you mentioned also wanting Vout up to 60V. And realistically you should be capable of operating at just 90% of your nominal Vin (to meet holdup time). So that would mean at worst case your duty cycle would be exactly 1.00. No headroom for handling load transients at all. Also if you plan on using a current transformer for sensing bridge current, you need to reserve some duty cycle for CT reset. And I assume you intend to use peak current mode control, in which case you want to avoid operating near 100% to make transient response faster. Using a 5:1+1 turn ratio should allow more headroom for such things.QuoteSure it's definitely possible, but depending on what level of insulation you need (basic, reinforced, etc), you may need to drastically change the implementation of the windings.QuoteTrue, PSFB is tolerant of more leakage inductance. Magnetizing inductance is important for maintaining soft switching under light load conditions though. In the worst case, if you Lmag is too high then you can put a large inductance in parallel with the primary to help.

author: Sniper1
author_rank: Regular Contributor
timestamp: July 09, 2025, 06:40:46 pm
content: Quote from: mtwieg on July 08, 2025, 10:43:52 pmYea i totally forgot about 60V since i got scared of the core loses and went on a long optimisation path. In a way 5:1+1 mean less turn on the primary so easyer to design.As for isolation my aim if basic (1500V) but if i get it to be reinforced ( 3kv) then great , since for now this is a 1 off i have a few ways to make it better, with Kapton.Anyway now alas i can take this transformer and resign the other parts, and i hope that untill the end of the mounth i can finish all the design work and order a PCB.THX for the helpI am still a bit afraid of primary inductance but that may be just my PTSD from the past.Ill post updates here as work progresses.

author: Sniper1
author_rank: Regular Contributor
timestamp: July 27, 2025, 07:55:30 pm
content: Quote from: Sniper1 on July 09, 2025, 06:40:46 pmHiits been a while, i return to simulations and i am sort of stuck atm.I modified your file so that it works with 390V dc input but i have 2 problems:1) the SMPS seems to not start well2) Vout is 12v not 48v tho this may be because it is not starting wellFor 1) i suspect Overload is starting somehow since i saw current going over 710 mV, BUT for the transformer and resistors i used the TI calculator. I am still not sure what is the problem here but i suspect it is something regarding the current sense or input decoupling capacitance. I also tried to add a diode since that is like 0.5-0.7V of voltage drop but it did not help but Vout got a bit higher2) might be because of 1) BUT i dont understand well the emulated optocoupler to begin withAny ideas?

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 28, 2025, 01:20:16 pm
content: I think you forgot to attach your simulation file(s)?

author: Sniper1
author_rank: Regular Contributor
timestamp: July 28, 2025, 04:35:47 pm
content: Quote from: mtwieg on July 28, 2025, 01:20:16 pmOPS now i hope they are there

author: Sniper1
author_rank: Regular Contributor
timestamp: July 28, 2025, 07:42:40 pm
content: ok so i made another file and this time i used a real transformer for modelling and i got similar results.I thought that the parallel 10k and diode will help but they did not.Also it gets stuck at like 7.2ms then goes with 2-6us/s , also it generated 3GB of data.So in a way the emulation you did was very good.

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 28, 2025, 09:51:39 pm
content: A few things I changed:1. Changed all the power semiconductors to higher voltage ratings2. Adjusted the snubbers (this seemed to make a big difference)3. Adjusted the compensation network a bit4. Increased the soft start caps (helps Vout settle faster)5. Changed the model of D5 from a 3V LED to a 1.2V pn diode (helps prevent overshoot at startup)Seems to work ok now. Feedback compensation still needs work. I tried to set up an FRA simulation but for some reason it wouldn't converge, seems to be an LTspice bug.

author: Sniper1
author_rank: Regular Contributor
timestamp: July 30, 2025, 07:44:27 pm
content: Quote from: mtwieg on July 28, 2025, 09:51:39 pmWhat is FRA?I saw it its working even tried with 12 OHM load and it was not even noisy at the output. I didnt test transient loads but ill test that too.found 2 problems:1) there is a overshoot up to 60V at start up, i tried to play with SS capacitor didnt work but i didnt touch the opto coupler circuitry so maybe i can fix it from thereIf the load is high this overshoot is lower at 4A it is 55V, probably some type of FB compensation problem2) while checking the datasheet for the 100th time i noticed that the high side drivers work up to 100Vdc so i need to make some changesthe other controller chips are with encrypted models so that is a no goThere are half bridge gate drivers that i could put in the middle and yes they accept-20V input signals. Since they were probably designed for stuff like this.Or i could try and use a gate drive transformer for the high side mosfets , never used something like this before but since the IC gate drive strength is 1.5A i think we can use the transformer directlyAlso for primary side FET i was looking at this:https://eu.mouser.com/datasheet/2/196/Infineon_IPL60R160CFD7_DataSheet_v02_01_EN-3362451.pdfTho it might be a bit overkill but not so many to chose from since there are a few that work at 500+V and there is also size and other parameters, for the isolated size am not sure yet might use same one or find something rated for 250-300V , technically i need 2*400/5=> 160V +20%=>192-20 but i see like 220-200V in the simulation and 20% over math seems about of ok , then again maybe there is something from diode reverse recovery or something.What do you think?

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 31, 2025, 02:54:32 pm
content: Quote from: Sniper1 on July 30, 2025, 07:44:27 pmFRA stands for "frequency response analyzer," something that was added to LTspice in the last few years. Nominally it injects a stimulus into the feedback loop during a transient simulation, and automatically creates bode plots of the loop gain and displays stability margins. It's poorly documented though, and for some reason it doesn't work in this simulation... not sure why. But was hoping it could help with optimizing the compensation.QuoteYeah the overshoot is bad. Likely just a matter of slowing down the soft start (making the simulation take longer), or optimizing the compensation, which is tedious since the FRA doesn't work...QuoteSure for the real circuit you'll need some solution for gate drive. But the LTspice model probably doesn't care. I would hold off on making the simulation more complicated until you've answered your transformer concerns.Regarding other models being encrypted, I actually wouldn't let that deter you from looking at other PWM controllers. As we can see, models from vendors aren't perfect. Personally, I would rather the manufacturer provide a clear description of how the controller works, enough that I can create my own simulation model from scratch. TI in particular often does provide sufficient details, though not always.QuoteThose FETs would definitely be one of the best choices aside from SiC or GaN FETs. Nice thing about the PSFB is that, when designed well, you can get away without needing extremely good FETs.For evaluating power semiconductors in simulation, I would abandon the LM5046 model entirely (slows things down too much) and instead just generate gate drive signals with arbitrary timings. Will make iteration much faster.

author: Sniper1
author_rank: Regular Contributor
timestamp: July 31, 2025, 07:06:02 pm
content: Quote from: mtwieg on July 31, 2025, 02:54:32 pmi even doubled that soft start capacitor and i didnt help, tho i didnt do like x10 or something extreme like that , might do that at the end.From what i see there are a lot of options from a lot of manufacturers, the fact that FSFB has ZVS helps a lot since i can use a worse gate driver IC. So in a way finding a driver is a non problem.BTW i checked again how i was getting those huge voltages on the secondary: it was some spike at the rise of the signal, might not even be real IRL.As for the controller I want to keep this one since i am not that good with spice so modelling another one is something i will find as a challenge in itself. Also professionally i have a few use case for this one 100Vdc is more then enough for a lot of non AC-DC stuff and the built in gate drivers are a great thing for simplified design.As for the FET infineo provides a spice model ill add it to the simulation and see what happens , also I started on the PCB transformer design not sure what the leakage inductance will end up at but more is better up to a point , i am mostly after the DC resistance so i can better simulate the transformer .Sic and GaN are a bit overkill for this power LVL and since this is a glorified toy / test platform ill stick to the traditional Si since i want something i worked with before and i already am taking a lot of steps in the unknown.

author: Sniper1
author_rank: Regular Contributor
timestamp: August 02, 2025, 04:30:43 pm
content: Quote from: Sniper1 on July 31, 2025, 07:06:02 pmOK so i added the official FET model and with L0 model i get 0.67W poses on low side and 0.8W on the high side this like with the 4A load ( and a bit less in steady state operation) . ( 7GB file...)Whit these loses and no large thermal pad ill be at about 50C temp rise at 4A load so not that bad so i think ill heave heat problems + IRL i might bet more cooling with a the PCB designL1 model seems to have convergence problems and to blame there is a current source from inside the controller model, might also be why the model is sort of slow .L3 also does not converge because of the same node.( Device Convergence Difficulty Score:u1:Gvref1 : 10.990991u1:Eosc3 : 1.711712 ) but runs without the start up option but ruin here is like 0.1ps/s or something like absurdly slowin the controller model:Gvref1 VCC REF TABLE { V(VREF3, REF) } ( (-0.7,-1)(0,0)(0.15,0.015) ) not sure why this is needed , might be some sort of ESD diode that is modeleld as a current source or something to do with some voltage referenceAlso you can use the REF pin for optocouplker bias .

author: Sniper1
author_rank: Regular Contributor
timestamp: August 02, 2025, 07:41:30 pm
content: ok so i changed the diodes to the same FET but i cant get the system to be stable with synchronous rectification .BTW that .71V voltage is soi that i can check CS pin vs a line and see where it was triggered.And the driver is a random one since the synchronous rectifier outputs 5V signals, should still work but simulation was not happyProbably was turning on to slow and entering linear region or something since i even saw negative voltages on the gates.Any idea on how i can deal with the instability ? And or how to make the model begave with L1 L3 models for the FETS ?

author: mtwieg
author_rank: Frequent Contributor
timestamp: August 05, 2025, 01:04:24 pm
content: I believe you've mixed up the drivers for the SR FETs.Also, trying to make use of these Infineon models is going to make things very painful for you... Infineon creates their models to be accurate, not to be fast. Try using the alternate solver, if you haven't already. That should help, but these models will still be very slow.Again, only make the simulation as complicated as it needs to be to answer the specific question you are asking. I don't think including synchronous rectifiers or realistic FET models are necessary to investigate transformer design (except maybe accounting for drain source capacitance).

author: Sniper1
author_rank: Regular Contributor
timestamp: August 05, 2025, 07:00:48 pm
content: Quote from: mtwieg on August 05, 2025, 01:04:24 pmYea i inverted the SR signals and it works much better now.Normal solver seems a bit faster.After i corected the SR signals it works with 1A load but it did not with 4A load. Trying a few things now , increasing the SS cap since CS pin experienced a overload* current.tho i have a few other leads too.BTW yea simulation time is long but often i also work in kicad or at something so it is not that bad

author: Sniper1
author_rank: Regular Contributor
timestamp: August 06, 2025, 08:00:54 pm
content: ok i am sort of sure now it is something from the CS pin since that is the only thing that systematically entered error* mode.I have no idea why TI xcel calculates with 75% or resistor needed for max current .Application note tells us to mat it so that it is like 0.2V under threshold.RC filter that goes to CS pin seems not to help, neither increasing that 1nF cap that is a filter .Also transformer primary will be like 1 ohm and i also added that in the simulation, nothing important changed.Ill see what resistor value i end up with and also try that.Good night.PS resistor did the trick at least with a quess value, xcel said 60 ohm i tried 40 ohm and it was ok

author: Sniper1
author_rank: Regular Contributor
timestamp: August 09, 2025, 10:58:34 am
content: In current mode control i noticed there is somewhat a discrepancy between how the current sense load resistor in calculated between the UCC application note and TI XLS calculator. For me it is 60ohm using XLS ( here it is 75% of ideal* steady state resistor for max current) .IF i use the formula form the UCC28950 ( also change the peak current on CS pin voltage value from 2V to .75V) then i get 38.5 OHM.But for the LM5046 the slope is with current 0-100uA through slope resistor R13 in XLS and that translates to 0.24V for me , and if i do the math with this value i get 35.66 OHM.I tried and simulated with 36 OHM and it was all good even at max load. Also i changed the compensation a bit and got rig of that large overshoot and now i have a monotonic ramp up.ill also try with 39 OHM and see how it behaves.And now i think ill focus a bit more on the real schematic and maybe replace the FB circuit with a simple opto model since i sort of need to tun the FB+comp for a certain opto

author: Sniper1
author_rank: Regular Contributor
timestamp: August 12, 2025, 08:46:58 pm
content: Quote from: mtwieg on August 05, 2025, 01:04:24 pmOK so when building a real FB circuit i hit a real WALL: i dont understand ho it works :'( .Regardless if it is at 1A load or 5A load Voltage at comp in is about .9V and the current through the FB diode is about the same.Worst of all i have no idea how you set it all up on the primary side , on the secondary i sort of understand the standard circuit .Well datasheet is also not great from what i understand 1mA corresponds to 0% duty cycle but no data on that is 100% duty cycleCould you please demystify the FB for me

author: mtwieg
author_rank: Frequent Contributor
timestamp: August 15, 2025, 01:02:53 pm
content: Quote from: Sniper1 on August 12, 2025, 08:46:58 pmThe datasheet is fairly transparent regarding this, see the functional block diagram, and section 7.3.8:The COMP current is fed to a current mirror, the output of which connects to the 5V REF via a 5K resistor. In the subcircuit, this is node COMPI. So this voltage will be V(COMPI) = 5-1000*I(COMP).COMPI is is also clamped by the SS pin voltage, so in reality you get V(COMPI) = min(V(SS), 5-1000*I(COMP)).Some more circuitry then reduces COMPI, first by subtracting 1V from it, then cutting it in half with a resistor divider. The result (node COMP2PWM in the model) is what is applied to the inverting input of the PWM comparator. The noninverting input to this comparator is the RAMP pin, which comes from your current sensor. Basically, power will be delivered to the transformer until V(RAMP) = V(COMP2PWM). Or, putting all those equations, V(RAMP) = (min(V(SS), 5-1000*I(COMP)) - 1.0)/2. This all may look bizarre, but I've seen the same sort of circuitry used in many PWM converters.One thing to keep in mind is that the datasheet describes ways to use the chip for pure voltage-mode control (I(COMP) directly controls duty cycle) or current-mode (I(COMP) controls peak transformer current). Which control mode is used depends on how the RAMP pin is connected.In the case where the RAMP pin is connected to a sawtooth waveform with constant slope (i.e. from the SLOPE pin, not from your current sensor), then you end up with is pure voltage-mode control. Figure 17 also shows a way to generate the ramp from Vin, which provides some useful feedforward compensation (but it's still voltage-mode).In the case where the ramp pin is only connected to your current sensor (no connection to the SLOPE pin), then you instead end up with simple peak current-mode control.However, with current mode control you will run into subharmonic oscillations when operating at duty cycles above 50% (in continuous conduction mode, that is). The fix for this is to inject some fixed sawtooth waveform into the current-sense signal. This is shown in fig 11 of the datasheet. Basically what you end up with is a combination between pure current mode and pure voltage mode control. The higher the duty cycle you operate at, the stronger your slope compensation must be. The stronger the slope compensation, the stronger the influence of the voltage-mode control. This was one of the reasons I was suggesting you change turns ratio, so that you don't have to operate near 100% duty cycle.Also, these tradeoffs are not something particular to the LM5046, or to this SPICE model. Same thing will apply to 99% of PWM controllers (excepting some that use very esoteric control schemes).

author: Sniper1
author_rank: Regular Contributor
timestamp: August 15, 2025, 07:13:25 pm
content: Quote from: mtwieg on August 15, 2025, 01:02:53 pmTHX most of i i did understand but how to implement in practice this with real components in my problem.And yes it is very odd when u see it coming from mostly LDO buck SMSPI also read that 0 current through COMP pin is 100% duty cycle or what is practical maxAnd 1ma through COMP pin is 0% duty cycle.The part that scares me the most is the real optocoupler since as of now i only managed to make them work in a digital signal context and the other isolated SMPS i made did not work at all so this is primarily from where i am coming.On the non isolated part i only have a pull up resistor that i need to tune a bit but the other side is what waries me since i saw how much compensation can change start up .I found some resources to study but i am still reading. Ill post my final circuit after i am done.As o f now i am looking at opcouplers , do u happen to know a few part numbers with public SPICE models or where i can find something about the compensation network that they need?As for the main transformer i am not done with layout or rather i am not satisfied but it is slowly taking a nice shape

author: mtwieg
author_rank: Frequent Contributor
timestamp: August 16, 2025, 11:59:47 am
content: Optocouplers are a completely different can of worms. I'd suggest making a new topic, maybe in the Beginners or Projects subforums. I'm not an expert on optos and you'll probably get more answers that way.

author: Sniper1
author_rank: Regular Contributor
timestamp: August 17, 2025, 10:36:53 am
content: Quote from: mtwieg on August 16, 2025, 11:59:47 amI will ask in another thread. Transformer primary is sort of done, with what i think is enough isolation.Now doing main PCB where ill have the aux windings and the secondary.When i am done with that too ill improve the simulation tho beside the opto i am sort of close anyway and 300 mOHM more then what i simulated with ( 1 OHM ) connections will probably add mode so i am sort of confident here.Well this is all according to Saturn PCB calculator..... sot at max load ill need to dissipate about 2WThis is JLC 0.5 OZ copper on internal layers if i go for 1 OZ then my loses will be about 1W , this is DC resistance.at my 250 KHz skin depth is 132 um so if i use 1 or 0.5 OZ should still matter since 1 OZ is 35 um so i think it will be fully utilised.As for leakage inductance i have no idea what i will get.

author: mtwieg
author_rank: Frequent Contributor
timestamp: August 17, 2025, 01:21:24 pm
content: Quote from: Sniper1 on August 17, 2025, 10:36:53 amI don't think SaturnPCB is going to be very helpful for designing the transformer windings (unless they added some fancy new features recently). You may want to review literature regarding winding design:https://www.ti.com/download/trng/docs/seminar/Topic4LD.pdfhttp://focus.ti.com/lit/ml/slup198/slup198.pdfKeep in mind that there are different strategies for winding optimization for different design objectives. For example, some strategies prioritize lowest leakage inductance, while others may prioritize lowest interwinding capacitance. Don't adopt a method unless you know it fits your application (the interleaved approach in the first link above is probably a good start).QuoteFor you I would suggest not trying to make the transformer provide all the leakage inductance required for soft switching. Shoot for a lower leakage in the transformer, and add an external inductor to provide most of the effective leakage. This makes the design process much more forgiving.

author: Sniper1
author_rank: Regular Contributor
timestamp: August 18, 2025, 05:53:09 pm
content: Quote from: mtwieg on August 17, 2025, 01:21:24 pmTHX but i already read them , i did a refresh now and it seems ok, my copper is on the low side but there again i have a thinner PCB so it can sort of cool easier but also lower thermal mass.So it should be ok but might get hotter... Then again depending on how it goes it well get used in another revision.Now it is mostly DIY hobby from 3 PCB so it is cheaper at JLC but if i go with a more serious design i might need to actually quote different combinations to see what is cheaperBut it needs to run in the first place and run ok, hot is good enough since it is on a budgetAnyway probably for the rest of the month ill figure the main PCB and other parts.As for leakege inductance ill measure it after i make it, if i expect it to be like in the simulation .99 coupling then it is 60uH but ill leave a footprint for a discrete iductor since this is a wild guess ( ill calculate what i need exactly overall later)