This is becoming quite a challenge, but I managed it. - Page 1
Forum section: electronics / projects

author: technix
author_rank: Super Contributor
timestamp: November 17, 2018, 10:40:33 am
content: This challenge is fitting an A3P060-VQG100 FPGA on a two-layer PCB the size of an Arduino Uno, and make use of all of the available I/O in some way, shape or fashion. Also all components must be placed on one side only.This proved to be quite a squeeze here. I have managed to fit:* A3P060-VQG100 FPGA,* AS6C4008 512Kx8 SRAM,* MX25L12835 QSPI Flash,* STM32F103TBU6 ARM Cortex-M3 microcontroller,* 12V to 5V and 5V to 3.3/1.5V regulators,* 4 LEDs, one power indicator, two connected to the MCU, one connected to the FPGA,* Arduino Uno headers,all on the component side of the boardThe FPGA and the ARM MCU are bridged using 4-wire SPI and UART serial interfaces, an interrupt line and a clock line. The MCU generates a 36MHz clock for the FPGA from its internal PLL. Since I have filled up the component side to the brim with traces and components, the usual pin number silkscreen is placed on the bottom this time. That 4K render took me 252 seconds to finish.

author: tkamiya
author_rank: Super Contributor
timestamp: November 17, 2018, 04:38:32 pm
content: I have to get this SUSHI BITS! Sounds tasty

author: jmsigler
author_rank: Regular Contributor
timestamp: November 17, 2018, 11:18:48 pm
content: What was this 3d model done with?

author: sokoloff
author_rank: Super Contributor
timestamp: November 17, 2018, 11:24:13 pm
content: Quote from: jmsigler on November 17, 2018, 11:18:48 pmLooks like KiCAD.

author: technix
author_rank: Super Contributor
timestamp: November 18, 2018, 05:20:37 am
content: Quote from: sokoloff on November 17, 2018, 11:24:13 pmQuote from: jmsigler on November 17, 2018, 11:18:48 pmKiCad 5.0Quote from: tkamiya on November 17, 2018, 04:38:32 pmI will make it available on my Tindie store for you, after the boards arrived and assed tests. Just do expect it being a bit expensive though, FPGA's aren't exactly cheap.

author: tkamiya
author_rank: Super Contributor
timestamp: November 18, 2018, 05:14:30 pm
content: I'm budget challenged.....

author: technix
author_rank: Super Contributor
timestamp: November 18, 2018, 06:11:08 pm
content: Quote from: tkamiya on November 18, 2018, 05:14:30 pmIt won't be that expensive though: US$99. 1/6 the price of an official Microsemi kit, while having two chips to play with (FPGA and STM32 MCU) Being a FPGA kit it is a bit expensive than my usual ARM kits, most of them around the $25 mark.

author: Bassman59
author_rank: Super Contributor
timestamp: November 18, 2018, 08:41:17 pm
content: Quote from: technix on November 17, 2018, 10:40:33 amOne question: Why the ProASIC3 part?

author: technix
author_rank: Super Contributor
timestamp: November 18, 2018, 10:11:16 pm
content: Quote from: Bassman59 on November 18, 2018, 08:41:17 pmI happen to have some A3P060-VQG100 samples, and I just bought a FlashPro and want to test it. Should the situation calls for it I can upgrade that FPGA to an A3P125 or M1A3P250 with the same package.

author: james_s
author_rank: Super Contributor
timestamp: November 18, 2018, 10:48:19 pm
content: Quote from: technix on November 18, 2018, 05:20:37 amI was just looking at the state of things this morning and was a bit shocked at just how cheap they've become. The lowest end Cyclone 10 part for example is under $8 each in single quantities and it has quite respectable specs. I've been using the same older parts for quite some time now and had not bothered to check on the current offerings in a while.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 18, 2018, 11:13:01 pm
content: Quote from: technix on November 18, 2018, 10:11:16 pmI've grown to hate Actel parts and Libero even more.But YMMV.

author: technix
author_rank: Super Contributor
timestamp: November 19, 2018, 05:09:43 am
content: Quote from: james_s on November 18, 2018, 10:48:19 pmThey are still fairly expensive in China, as people are still using Spartan 6 and Cyclone IV. Also FPGA in TQFP-100 is a bit of rarity too.Quote from: SiliconWizard on November 18, 2018, 11:13:01 pmIs there any reason for that?

author: james_s
author_rank: Super Contributor
timestamp: November 19, 2018, 05:11:53 pm
content: I don't really care too much about TQFP. It's nice for prototyping but BGA is no longer the non-starter it used to be for personal projects, especially when you can buy $20 dev boards from China. With an FPGA it's nice to have gobs of IO.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 19, 2018, 05:50:37 pm
content: Quote from: technix on November 19, 2018, 05:09:43 amFrom my experience with the Proasic3 line, they consistently tended to draw more power than expected and it was often a fight to meet timing constraints compared to other vendors' FPGAs in similar ranges. Usually switching to Xilinx or Lattice was an instant relief.As for Libero, recent versions may have improved, but back when I was using it (few years ago), it was one of the most atrocious pieces of software I'd ever usedUltra slow, cumbersome, confusing... programming with Actel "pods" was also nightmarishly slow as I recall.This is just my experience though - don't let that deter you from trying and get your own opinion.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 19, 2018, 05:53:20 pm
content: Quote from: james_s on November 19, 2018, 05:11:53 pmGobs of IO is nice but that can be a nightmare to fan out and route to headers, and there's an ultra small probability he would have managed to route that on a 2-layer board as seems to be his challenge here.

author: technix
author_rank: Super Contributor
timestamp: November 19, 2018, 08:01:36 pm
content: Quote from: james_s on November 19, 2018, 05:11:53 pmBGA = no bueno on a 2-layer board with little exceptions. This whole point of this challenge is to route that TQFP-100 FPGA fully out to various peripherals while being constrained to the Arduino Uno form factor and use only two layers.Quote from: SiliconWizard on November 19, 2018, 05:53:20 pmI have already routed every pin on that FPGA out - Arduino headers, parallel SRAM, QSPI, two different interfaces to the MCU, etc. On this two-layer board there is already little space left, and I had to snake the power traces quite a bit.

author: technix
author_rank: Super Contributor
timestamp: November 19, 2018, 08:06:09 pm
content: Quote from: SiliconWizard on November 19, 2018, 05:50:37 pmThis is literally my first ProASIC board... The first Duplex POC (STM32L432 + XC2C32A) failed, and I just bought a FlashPro 5 and has some ProASIC3 samples so this is my second Duplex POC.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 19, 2018, 08:10:05 pm
content: Quote from: technix on November 19, 2018, 08:06:09 pmDo not hesitate to report back once you get your board working.

author: technix
author_rank: Super Contributor
timestamp: November 19, 2018, 08:38:11 pm
content: Quote from: SiliconWizard on November 19, 2018, 08:10:05 pmI am still not 100% clear what can this thing do after the initial POC though.Having external SRAM and QSPI Flash does allow me to implement soft core processors in it, but will it be worthwhile to do that? If not, what kind of experiment can I do with that MCU and FPGA combo?

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: November 19, 2018, 10:53:39 pm
content: Quote from: technix on November 19, 2018, 08:38:11 pmI don't think that part is big enough for any kind of soft core other than a minimalist barely turing complete stack machine (zero operand). Yesterday I looked up that part on find chips and saw a price of about $10 and 060 in the part number and though wow, cheap. Thinking 060 referred to macrocells or luts instead of gates. Only 1500 "versa-tiles", which are finer grained units than typical fpga fabric, and no dsp tiles or MAC units. Soft cores don't make much sense these days when there are inexpensive ARM mcu's and there already is one included in your design. A better target fpga would have been ice40up5k. Has a growing hobby-open source following and greater capacity, although it is slow as mud and has fewer I/O.

author: xaxaxa
author_rank: Regular Contributor
timestamp: November 20, 2018, 01:44:09 am
content: I think XC6SLX9 remains the most cost effective FPGA at $5 each and 9000 LEs equivalent.On a $99 product it doesn't make much sense to use a 2 layer board; the unit price of a 4 layer PCB is insignificant compared to the rest of the parts, and you get the advantage of a smaller board and less EMI emissions. I've even considered making a $20 product that uses a 4 layer board.

author: technix
author_rank: Super Contributor
timestamp: November 20, 2018, 02:19:20 am
content: Quote from: xaxaxa on November 20, 2018, 01:44:09 amI think so too. I won't be running a XC6SLX9 based Duplex though since I have my sights on Zynq.Quote from: xaxaxa on November 20, 2018, 01:44:09 amAt least on JLC's Chinese-facing pricing, 4-layer boards costs 2x as much as 2-layer boards at smaller quantities.

author: Bassman59
author_rank: Super Contributor
timestamp: November 20, 2018, 11:24:30 pm
content: Quote from: SiliconWizard on November 19, 2018, 05:50:37 pmI am fighting that fight. 100 MHz is a challenge. There are a lot of things that trip you up. Some of it is because of what Synplify does, others are purely fabric-related. I have a list of things about the fabric that make it so. The lack of a CLB/LUT means you don't get free shift registers or small RAMs. The lack of a synchronous reset can make things like counter clears painful. There's no carry chain so "wide" adders and counters won't meet timing. Convincing the tools that those flip-flops need to be in the I/O is quite the challenge; instantiating them as DDR in and out flops seems to be the most reliable way to do so. Getting it to meet hold-time requirements on internal flops -- hold time! -- can be a challenge.When something doesn't meet timing, it's worth looking to see what the synthesizer did with the code. In my current design I have to mux the outputs of sixteen 16-bit-wide block RAMs down to one 16-bit bus, and I had to pipeline the shit out of it because routing around the multiple 16:1 muxes never met timing. And then the tools decided that one of the mux selects was too heavily loaded so that line was put onto a global buffer -- and the routing to and from the global buffer (which is at the edge of the chip) made the timing worse!QuoteI had to stop using the Libero project manager. Every time I updated my source it would decide to spin off a new "implementation," when meant a new Designer database. It hid too much from you, so you never quite knew what to do. So I run Synplify and the Designer place-and-route standalone.Designer is stupid. When you create placement and timing constraints, they are buried in their big .adb file, which is the project database. You have to export them to text files (.sdc and .pdc) if you want to do something reasonable, like keep them in your source-code repository. And then when you change the text file and re-import it into the project, it wants to merge your new file with the existing constraints in the database. Who the hell knows exactly what has priority? So i just got into the habit of not checking those "merge" boxes. And then I noticed that sometimes nothing I did would make the design meet timing -- and it would grossly off from a previous run. I discovered that simply blowing away the .adb and creating a new Designer project gave me better results. (Thankfully creating the new Designer project is as simple as selecting the family and the directory in which the design will live, then selecting the exact part, then importing the EDN synthesis result, the PDC and the SDC, and letting it chug.) And when I let it run, I have to have the advanced options all on and let it do multiple placement attempts. It's ridiculous.Oh, and good luck understanding the timing constraints, especially how to set up multi-cycle paths.QuoteWe have a FlashPro 4 and a couple of FlashPro 5s here, and the 5 is much faster.It's not all shit ... the Identify debugger, while not as slick as Xilinx' ChipScope, does work well enough, and doesn't kill timing (too much).

author: Araho
author_rank: Regular Contributor
timestamp: November 21, 2018, 10:52:05 pm
content: Isn't it very sketchy to run FPGA I/O straight to headers on the board like that? First EMI-event happening (or hot-plugging a cable!) and you'll fry some of the input circuity, won't you?

author: james_s
author_rank: Super Contributor
timestamp: November 21, 2018, 11:45:01 pm
content: I have a bunch of FPGA boards with the IO run straight to the headers, never had any trouble at all. Some of them are little Cyclone II boards which are so cheap I never worried about it at all, I frequently toss one in my laptop bag without any ESD protection, and abuse it doing things like driving a speaker directly from IO pins. I've yet to kill one, they seem to be quite robust.If it was a $500+ FPGA then I'd be a lot more careful but for cheap stuff? Whatever.

author: Siwastaja
author_rank: Super Contributor
timestamp: November 22, 2018, 07:33:09 am
content: Simple series resistors (say 47R) offer the benefit of providingsomeprotection while being almost as cheap as no protection at all. 47R series + external schottkys to rails was used in Terasic's DE2 development board, for example, which we used extensively.These small resistors protect from short circuits which IMO are the most probable way of killing IO on the "lab table". They alsomayprotect from overcurrent damaging things through substrate diodes when you accidentally put a voltage on an IO pin of turned-off device - they also protect from small overvoltages such as 5V on 3.3V input, by limiting the IO cell diode current.They won't properly protect from ESD, or severe overvoltages. But these resistors are almost free, and they prevent ringing of fast output signals by working as series termination, without slowing down the signal too much.

author: technix
author_rank: Super Contributor
timestamp: November 22, 2018, 08:24:30 am
content: Quote from: Siwastaja on November 22, 2018, 07:33:09 amI have 22R and ESD clamp diode packs, but those won’t fit here.The boards arrived and preliminary testing suggests it works.

author: technix
author_rank: Super Contributor
timestamp: November 22, 2018, 11:31:33 am
content: That board came back finally, and my first unit survived a tour in the city in my pocket.I wonder what should the MCU provide to the FPGA? USB CDC is an easy one, ditto the 36MHz core clock. Now how should I make use of the SPI interface?

author: technix
author_rank: Super Contributor
timestamp: November 28, 2018, 04:39:33 am
content: Quote from: james_s on November 18, 2018, 10:48:19 pmHere it is:https://www.tindie.com/products/maxtch/sushibits-duplex-mini-2/

author: technix
author_rank: Super Contributor
timestamp: November 28, 2018, 04:40:07 am
content: Quote from: tkamiya on November 18, 2018, 05:14:30 pmHere you go:https://www.tindie.com/products/maxtch/sushibits-duplex-mini-2/