Differential Bi phase Level Decoder - Page 1
Forum section: electronics / general

author: man_marius
author_rank: Contributor
timestamp: October 18, 2018, 07:04:19 am
content: What is the easiest way to go about make a Differential Bi phase Level detector circuit board, with discrete components or FPGA,The decoding works in two steps, first translating phase shift bit shift into A letter, this happens in the center of each bit cell, a change from -1 to 1 is encoded as "A" and a change form 1 to -1 is encoded as "B".The second step is to compare the current letter to the previous oneX current = X previous -> 1 is encodedX current != X previous -> 0 is encodedI have attached the encoder schematic

author: man_marius
author_rank: Contributor
timestamp: October 18, 2018, 07:12:37 am
content: The input signal is a polarity insensitive differential line 120 characteristic impedance and at a datarate of 564.48 kbit/s

author: Dubbie
author_rank: Unknown
timestamp: October 18, 2018, 07:17:38 am
content: I have just done a biphase mark decoder using an stm32 micro. I just start a timer on an edge interrupt and then add the timing of the last edge to a fifo buffer that gets processed in the main loop. Seems to be reliable. However I am only decoding up to 4kb/s. I am doing a lot of other stuff on the micro such as drawing an oled screen and writing to an sd card and everything plays well together.

author: man_marius
author_rank: Contributor
timestamp: October 18, 2018, 07:26:09 am
content: That would work, but that is dependant on how fast the micro controller is running

author: Dubbie
author_rank: Unknown
timestamp: October 18, 2018, 07:45:41 am
content: Have you got any experience with fpgas? This would be pretty simple to implement on one. Kinda seems like overkill almost though. Maybe a cpld? Or get one of those soc micros with the built in clpd.

author: man_marius
author_rank: Contributor
timestamp: October 18, 2018, 08:11:38 am
content: I have one, but I want a standalone system, the board I have is zynq and it will be overkill

author: man_marius
author_rank: Contributor
timestamp: October 18, 2018, 08:12:33 am
content: can it be done use discrete components, it is better

author: Dubbie
author_rank: Unknown
timestamp: October 18, 2018, 08:20:50 am
content: You could make it out of a fistful of 74 series logic

author: KrudyZ
author_rank: Frequent Contributor
timestamp: October 18, 2018, 08:56:40 am
content: If you have a synchronous clock, then it's trivial.In the likely event that you don't have that, you would either need to do clock recovery or oversampling.Since your data rate is fairly low, I would suggest to oversample the data to recover the bits.Use a couple of flops to remove metastability from the synchronizing stage.Then detect edges by comparing two consecutive samples.Start a counter when you see an edge and measure clock cycles to the next edge.Use a window comparison to figure out if you just saw a short or long pulse width.If it was long then you saw a zero.If it is short set a flag, unless the flag is already set in which case you detected a one.Make sure to reset the flag when you see a zero as well and capture weird pulses as errors, which will help with debug.You should aim to get at least three to four samples on the short pulse width, more is better, so the sample clock frequency should be above 4 MHz.Easy to do inside a CPLD or FPGA.You could also do this on a dedicated timer pin of an MCU, but you would be spending a lot of time in the interrupt routine and might not get much else done.

author: man_marius
author_rank: Contributor
timestamp: October 18, 2018, 09:06:42 am
content: Does anybody know how to translate a finite state machine into logic gates,

author: man_marius
author_rank: Contributor
timestamp: October 18, 2018, 09:11:10 am
content: thanks @KrudyZ, I will make the design and share it with you guys just for verifications

author: nctnico
author_rank: Super Contributor
timestamp: October 18, 2018, 04:46:41 pm
content: What is the signalling rate of the signal?The easiest way is to sample with 6x (or more) the transmission clock rate and then use a state machine to decode the bits. You can make this auto-align by resetting the statemachine when it detects an illegal combination. IIRC I made an NRZ decoder using two GAL22V10s back in school >20 years ago so a simple CPLD should be able to do it.

author: JS
author_rank: Frequent Contributor
timestamp: October 19, 2018, 07:26:58 am
content: Isn't that differential manchester encoding?Nobody mentioned it in the thread so you can go to google and get useful results, I bet you can find vhdl code for that!JS

author: cv007
author_rank: Frequent Contributor
timestamp: October 19, 2018, 02:25:25 pm
content: http://ww1.microchip.com/downloads/en/appnotes/01470a.pdfa PIC16F15323 (<$1) has 4 clc's and an nco