Curtailing transistor leakage and noise - Page 1
Forum section: electronics / beginners

author: altaic
author_rank: Unknown
timestamp: March 23, 2016, 10:00:36 pm
content: Hi all, I've been doing some research on eliminating current leakage (sub pA) and noise in FETs for a precision measurement instrument, so I started this thread to gather and document information and ideas on circuit design to minimize transistor leakage and noise in general. I'm currently focused on off-state leakage, but comments about on-state leakage are most welcome (on-state leakage will be next for me). And, of course, please correct me if I'm wrong about anything.Regarding reducing off-state drain-source leakage (I_DSS), a simple method is to put a couple transistors in series. This is referred to as transistor stacking, and is similar to cascoding. I_DSS is proportional to the voltage across the drain and source, so when two transistors are used in series, the off-state leakage will drop exponentially. A further advantage is that one of the transistors can be lower voltage; the other transistor acts as a barrier and its breakdown dominates. There are (at least) two caveats to using a relatively low voltage transistor in series with a higher one, assuming the potential across them is equal to the high voltage spec:1) The high voltage transistor must switch off before (or switch on after) the low voltage one. Pretty simple.2) The R_DS(ON) of the low voltage transistor must be lower than the high voltage one by at least the same proportion as the difference in breakdown voltage. So, if you've got a 1000V 100m? FET and you want to use it in series with a 10V FET, the 10V one has to have an R_DS(ON) of less than 1m?.I'm not sure if off-state gate-source leakage is even a problem; all data sheets I've come across define on-state gate-source leakage (I_GSS). Considering ultra-low noise circuit design, does current flow through the gate when it's at very low potential?Will

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 24, 2016, 03:04:58 am
content: Uh, JFETs or MOSFETs?What kind of voltages and currents and circuits and topologies are we talking here?If Idss is proportional to Vds, then using N transistors in series gets N-fold reduction in Idss. Not exponential.JFETs have lower leakage (especially gate leakage) at lower voltages; there's a hot-carrier injection effect or something. I think 3-6V D-S is typical to avoid this.The only guaranteed, orders-of-magnitude effects you can harness are: device scale, and temperature.Obviously, using a smaller device to begin with, is a big win. RF MOSFETs may be suitable for this, or the old 2N4117 and related JFETs (Rds(on) in the >>kohms, very small geometry parts indeed!).Junction leakage goes as exp(T_abs), so cooling is a huge win, if it's an option. JFETs I think will behave okay down to modest temperatures (maybe dry ice, but maybe not LN2 or below?). MOSFETs I think go down to cryogenic temperatures without much trouble (but the voltages do shift a lot).Circuit design is a huge contributor. Servoing offsets to null leakage is an option:Suppose you have a diode-protected input stage (a conventional op-amp IC design): instead of VEE-diode-input-diode-VCC (a clamp diode architecture), you could clamp the output of a follower, and use back-to-back diodes across the follower. The follower enforces 0VDC across the back-to-back diodes, bringing their leakage to zero, but the B2B diodes clamp into the output diodes under surge conditions.Some devices exhibit variable leakage with voltage (including crossing through zero). I'm not sure if JFETs do. I've heard that PHEMTs do (again, RF devices, small geometry -- might be useful, who knows).Old school vacuum tubes do: at low (negative) grid voltages, grid emission (due to it being warm from proximity to the glowing cathode) is negative, acting to pull the grid up; at higher voltages (above -2V or so), cathode emission can be absorbed by the grid and leakage goes positive (acting to pull grid voltage down). A typical healthy tube, with open-circuit grid, will self-bias at -3 to -1V.Electrometer tubes were a thing. These used special construction (glass or ceramic insulators over conventional mica) and design (small structures, low temperatures, low currents, low voltages) to achieve sub-pA leakages. Typically a device would be operated in a bootstrap circuit with only 5-50V on the plate, and a few uA of cathode current. Subsequent amplification and feedback is needed to increase sensitivity and drive a meter. (Since, hey, they're vacuum tubes, they just don't have much gain per device!)As for noise, the most obvious problem is this: if you reduce leakage currents to zero, you can eliminate current noise, but what price do you pay on voltage noise, and how low do you need it? Small MOSFETs (e.g. LMC6001 input stage) have vanishingly low leakage, but much more voltage noise. (Although as noise goes, LMC6001 does very well indeed: ~20nV/rtHz is comparable to any MOS amp, which is only a few times worse than a jellybean JFET type.)Tim[Ed: that was a bigger edit than I was expecting.]

author: Marco
author_rank: Super Contributor
timestamp: March 24, 2016, 03:33:03 am
content: Quote from: altaic on March 23, 2016, 10:00:36 pmNoise and drain source leakage are going to be fighting each other for a signal switch, lower noise => lower switch resistance => larger area => larger leakage.Gate source leakage current on an unprotected small signal MOSFET is pretty much irrelevant.

author: altaic
author_rank: Unknown
timestamp: March 24, 2016, 03:17:41 pm
content: Thanks for the comments, guys.Quote from: T3sl4co1l on March 24, 2016, 03:04:58 amI'm still deciding between the two, though I'm leaning towards MOSFETs since I'm not all that familiar with JFETs.Quote from: T3sl4co1l on March 24, 2016, 03:04:58 amUp to 1kV, and at lower voltage, up to 10A (due to heat dissipation constraints). The current piece of my circuit I'm working on only really needs to act as a solid state relay-- if it's off, I need to make sure current offset/noise to other signal paths is minimized. It doesn't have to switch often or particularly fast.Quote from: T3sl4co1l on March 24, 2016, 03:04:58 amI'm basing my claim of the exponential reduction of I_DSS on various papers [1, 2]. Apparently the pair will self-reverse bias; to quote one of the papers:"If only one NMOS device is off, the voltage at the source node of off transistor would be virtually zero because all other on transistors will act as short circuit. Thus, there is no self reverse biasing effect, and the leakage across the off transistor is large. But if more than one transistor is off, the source voltages of the off transistor, except the one connected to ground by transistors, will be greater than zero, and the leakage will be determined by the most negatively self-reverse biased transistor (because sub-threshold leakage is an exponential function of gate-source voltage). The reverse bias makes the leakage across the off transistor very small."Interesting about the JFETs; the only HV device I'd considered is the IJW120R070T1, which has relatively low I_DSS, but quite high I_GSS.Quote from: T3sl4co1l on March 24, 2016, 03:04:58 amRegarding smaller device size, are you talking about the process node and VLSI path length, and/or package size (incl. leads, etc.)? I've considered using bare dies with direct bond copper for the critical signal path, though I'd like to avoid it if possible. As far as cooling goes, unfortunately I'm stuck with more conventional types involving air and drift compensation.Quote from: T3sl4co1l on March 24, 2016, 03:04:58 amAh, nice, thanks! That's exactly the type of stuff I'd like to have in my mental toolbox.Quote from: T3sl4co1l on March 24, 2016, 03:04:58 amI am a big fan of HEMTs, though I haven't come across any devices that match the criteria for the SSR part of my circuit (though I do use them elsewhere). I'll have another look at them shortly.Quote from: T3sl4co1l on March 24, 2016, 03:04:58 amHmm, I'm not much of a tube guy. I'll probably avoid them given the relative difficulty of sourcing them, as well the voltages necessary to drive them.Quote from: T3sl4co1l on March 24, 2016, 03:04:58 amVoltage noise at low signal levels is definitely a problem in other parts of my circuit, and I've learned a lot (relatively speaking, given the subforum this thread is in!) about reducing it recently. I'll post some of my findings on it later-- any tips/tricks in the meantime are of course welcome!Quote from: Marco on March 24, 2016, 03:33:03 amWhile I thought the same about noise vs. leakage, I was somewhat startled to find that off-state leakage may be reduced exponentially [1, 2]. I will unfortunately have to compensate for on-state leakage, and, yeah, have more noise.Quote from: Marco on March 24, 2016, 03:33:03 amGood to know.Thanks,Willhttp://www.iosrjournals.org/iosr-jvlsi/papers/vol4-issue5/Version-1/A04510105.pdfhttps://mixsignal.files.wordpress.com/2010/04/circuit-techniques-for-leakage-reduction.pdf

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 25, 2016, 05:02:22 am
content: Quote from: altaic on March 24, 2016, 03:17:41 pmWait, what? That's a potential 10kVA of switching area. How the hell do you care about pA leakage on that?If you truly need that much range, then well and truly, there is absolutely nothing better than a good old fashioned mechanical switch! There is no semiconductor that can perform as well at DC. Leakage is limited by packaging (hermetically sealed glass reed relays basically leak due to cosmic background radiation only) and conductivity is limited by material (which is to say, milliohms, not the ~ohms you'll get from a semiconductor).There are HV reed relays available. They aren't cheap, but it sounds like you're not doing something cheap, so that's fine.Also, what's "beginner" about this project..? This sounds advanced, even for an expert.QuoteOh, so assuming Vgs(th) is low, and there's no negative supply. Well you can just drive negative Vgs into the bottom one, problem solved.Also, 1kV rules out JFETs. I had imagined you were thinking about pA at modest voltages...(There are a few SiC JFETs for power switching applications, but they're boutique. I haven't seen a single one in the wild, and the few that are available are seriously expensive.)QuoteJust junction area. Package doesn't matter, as long as it's low leakage.From what little info you've provided so far, it looks like your problem is impossible. MOSFETs have a fundamental tradeoff between breakdown voltage (channel length and doping gradient), leakage (channel width) and Rds(on) (the ratio of the two).To get 1pA leakage, you need a device that's, I don't know, probably 2N7000 sized, but rated for 1kV. So it'll need about 10 times lighter doping / longer channel, leading to higher resistance (~10 ohms). If you need 10A at a low voltage drop (<1V?), you need Rds(on) quite low; 0.1 ohms is a big device at 1kV. The best compromise might be 1nA and 1 ohm, or something like that: neither one being actually good enough.I suppose I assume you need a low voltage drop because you're talking FETs over IGBTs (which have a more constant voltage drop, around 1-3V, rather than a resistance). I don't know about IGBT leakage, but I assume it would be comparable to MOSFETs of the same rating. Maybe you don't know about IGBTs; I don't know!QuoteWell.. now that you're talking Medium Voltage (in the power utility sense), they're definitely out...There are some higher voltage GaN devices coming into the market, which probably could do the job. Higher mobility than silicon means lower Rds(on) for the same size, and higher bandgap means smaller saturation currents.I don't know of any rated >1kV so you'll still have to cascode them, and none are actually specified in leakage (because it doesn't matter in switching duty). So you'd have to measure them yourself.QuoteWell, since I guess you're not just measuring pA anymore, that's definitely out. Tubes have rather poor specs: ~10^6 on/off ratio (i.e., ~uA leakage for ~A conduction), rather low gain (needs 100s V drive, though the capacitance is low at least), and high 'on' resistance (a 1A, 7kV device will exhibit about 30 ohms "Rds(on)"). Not to mention the absence of P devices (although there are very few PMOS over 200V anyway) and the conspicuous need for a power-hungry heater (~20W of wasted power for such a device).Tim

author: altaic
author_rank: Unknown
timestamp: March 25, 2016, 05:46:52 pm
content: Quote from: T3sl4co1l on March 25, 2016, 05:02:22 amI think there's been a misunderstanding. The HV transistor must handle up to 10A at low voltage, not at 1kV. At 1kV, it'll handle something like 10mA. The pA spec is so other signal paths that branch off earlier aren't disturbed when this is switched off, or otherwise for when I need to measure high impedance sources. There are many power devices that have a safe operating area that fit this criterion. The C2M0025120D or IJW120R070T1, for instance. The "beginner" aspect is that reducing transistor leakage and noise isn't difficult, and I started this thread to talk about it.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 25, 2016, 06:02:00 pm
content: That's only more confusing...Do you have a schematic?Tim