Advice: Properly connect MCU to DB25 - Page 1
Forum section: electronics / beginners

author: rthorntn
author_rank: Frequent Contributor
timestamp: March 05, 2018, 09:25:24 am
content: Hi,Sorry to bother you all.I have a Gecko G540 to control a CNC (not really relevant):http://www.geckodrive.com/g540.htmlAnd a DE0-Nano-SoC (not really relevant either):http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=941Basically for testing I want to use jumper wires to setup communication between the G540 DB25 (I have a DB25 breakout) and the DE0 GPIO pins, so that's easy with the F/F jumpers.Say all I want to do is send a 3.3v (GPIO) signal to the DB25 pin 1 (enable OUTPUT 2 relay on the G540), do I only need one jumper cable, or do I need to connect anything else (GND), if you could explain the reasoning that would be awesome also?I have read that the G540 signal paths are opto-isolated.I will be doing some PWM and reading pins on the DB25 later but first things first I want to enable this relay.Thanks for looking.Richard

author: Ian.M
author_rank: Super Contributor
timestamp: March 05, 2018, 10:08:20 am
content: The G540 is intended to be controlled by a PC's IEE 1284 host parallel port.Seehttps://web.archive.org/web/20040616170240/http://www.fapo.com:80/1284elec.htmfor electrical specs.You must *ALWAYS* connect Gnd. For short jumpers you can probably get away with a single Gnd wire, but if you are using a longer cable all Gnds should be connected for good signal integrity.Although outputs using 3.3V logic levels *may* be compatible with a IEE 1284 device port's input lines, it isn't certain if your SoC board can supply enough current - a non-isolated logic input wont load it heavily, but if the interface is actually optoisolated, significant drive current may be required - the standard calls for +/-14mA, but the original IBM implementation (pre-standardisation) Data Out pins were originally driven by a 74LS374 octal latch, which could source 2.6 mA and sink 24 mA.You may need to measure the current one G540 input draws, using a 3.3V supply with a 50R series resistor. Also, check that any output lines don't exceed +3.3V when high, before connecting them to a SoC input.If the electrical specs aren't compatible, or if you want to use a long DB 25 cable, you'll need to use level translating line drivers.

author: rthorntn
author_rank: Frequent Contributor
timestamp: March 07, 2018, 12:09:47 am
content: Thanks Ian.The opto isolator inputs on the G540 require 1-2ma to drive them. So I should be ok.The outputs from the G540 into the DE0-Nano are open-collector outputs. So I have been told I need a pull-up resistor on the line to the microprocessor and that some MCU's have have internal ones that can be enabled through its software, how do I check this, how does that effect the voltage between the G540 and the DE0-Nano, does an open-collector on the G540 source it's voltage (reference) from the DE0-Nano (3.3V)?This has some interesting info on FPGA pull-ups (the DE0-Nano is an ARM SoC connected to an FPGA connected to the GPIO)https://electronics.stackexchange.com/questions/248248/altera-fpga-i-o-weak-pull-upsBasically the above link says use seperate resistors to pull-up even if your board has them as the board ones are "weak".How do I wire it if I have to add a pull-up resistor?Thanks again.Richard

author: Ian.M
author_rank: Super Contributor
timestamp: March 07, 2018, 01:15:26 am
content: The pullup reistor for an open collector or open drain output simply goes from the signal to the supply rail with the voltage you want for logic '1'.The pullup resistor forms a RC filter with the capacitance of the cable or track linking the output and input, which can significantly delay rising edges. Internal pullups are generally approximately equivalent to resistors in the 50K to 100K range depending on the I/O design of the specific device, so with a typical 100pF of interconnect capacitance, could result in a delay of the order of 7us. 10K external pullups (which I would recommend for this application) would knock that down to under 1us.Of course the actual delay depends on the logic transition threshold of the input which is almost invariably not closely specified - I assumed 50% for this example. If you needed an even faster rising edge you could use a lower value pullup at the expense of more power dissipation and subject to the output's current sinking capability.Open collector/drain outputs with the pullup located at the corresponding input are absolutely horrible for fast signals over long cables due to the high cable capacitance and typically very poor match to the cable's characteristic impedance.