Required oscillator stability for multislope ADC? - Page 1
Forum section: electronics / general

author: julian1
author_rank: Frequent Contributor
timestamp: January 28, 2017, 10:57:02 pm
content: I have been playing with a homebrew dual-slope ADC design controlled from an fpga development board. I just realized the on-board oscillator is a mems type. Specifically a Discera 12Mhz MEMS oscillator but without a part number.I have found alternate design-notes for clocking the fpga using a crystal oscillator. I am considering using something like a HC-49Shttp://www.farnell.com/datasheets/1497894.pdfwhich states a 10ppm freq tolerance and 10ppm freq tempco over operating temperatures.My questions are -- I don't have experience with oscillators or crystals. The dev board really only needs enough clock stability for implementing uarts and has probably been built with that in mind. So I suspect that replacing the mems oscillator with a crystal type is an obvious first-step for timing improvement. Is that a reasonable assumption?- Is it possible to do better for the oscillator - without resorting to ovenized devices which cost hundreds of dollars?- At first glance, 10ppm freq stability doesn't sound very good - eg. 100uV measurement change over a 10V range. But perhaps the freq stability variation is more like noise and will average out across the duration of the integration interval. And perhaps more importantly cancel out - over the two (run up/down) phases?- the circuit has the crystal hung across two 27pF caps tied to ground and is fairly typical. Can I just use ordinary ceramics or are NPO types preferred?- Any ideas for other things to watch in terms of clocking and timebase accuracy?

author: Kleinstein
author_rank: Super Contributor
timestamp: January 28, 2017, 11:31:13 pm
content: The usual integrating ADCs don't need a very stable clock. Accuracy of the clock essentially does not matter. The line frequency is not that stable any more. So even PSRR will not suffer much if the clock is something like 1000 ppm off.It is only the short time stability and jitter that really matters. So an FPGA internal PLL could be a problem if this is not that good, but it still might be OK.So absolutely no need for a oven stabilized of super low drift / TC oscillator. So just normal 100 ppm tolerance is good enough, even for the 3458. I don't know how good the mems based clock is - a crystal clock could be still worth it, as it usually is low cost. The usual small caps (20 pF range) are NP0 - even than it would not matter if they had a higher TC. Ready made crystal oscillators (e.g. those 4 pin metal cans) are less prone to external noise pic up and might be the better (at least more reliable) choice.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 29, 2017, 09:54:54 am
content: There are better clocks than jelly bean crystals, but for a typical integrating ADC you don't need it. The jitter in switching the currents is more likely set from switches. Unless you want more than 9 digits you don't need much better than 0.1 ns jitter. The jitter that does matter is at something like 1-100 kHz offset from the carrier, so the sometimes problematic close in jitter does not matter that much.Even when the 3458 was designed there were much better oscillators available, but the settled for a jelly bean caned oscillator without any extras.The tricky parts are more about charge injection, capacitive coupling, dielectric absorption, leakage current, 1/f noise, temperature fluctuations and amplifier speed / settling. Clock jitter comes somewhere after supply stability, board vibrations and cosmic ray background.

author: David Hess
author_rank: Super Contributor
timestamp: January 29, 2017, 04:10:46 pm
content: I ran across this problem once.The design had a 40k count Intersil or TI dual-slope integrating converter and the RC oscillator used had enough jitter to cause noise in the last digit. Changing it to an LC oscillator fixed it. So as a practical manner, any resonator source is more than good enough.Don't some high resolution multi-slope designs phase lock to the power line frequency?

author: Kleinstein
author_rank: Super Contributor
timestamp: January 29, 2017, 04:29:07 pm
content: The old Solartron DMMs used a PLL to lock to the power line frequency. However they also used a relatively low frequency for there reference modulation and thus had a slightly different jitter requirement from more modern integrating ADCs that switch there currents more often. So even with a not very good LC based PLL they got up to 8 digit resolution (though slow).The main effect of clock jitter is, that the reference current from the positive and negative side don't compensate perfectly any more. In a typical case one might have 1000 reference switching events over 100 ms for 1 conversion. So a 1 ppm signal change would corresponds to something like 50 ns. This would be something like 1.5 ns of random jitter for the 1000 events. As correlated errors would compensate, the low frequency (low offset) phase noise would be even suppressed. So one would like to have a phase noise of less than about -40 dBc for a 10 MHz carries at a 10 kHz offsets to get a 1 ppm resolution. AFAIK normal low cost crystals are more like -100 dbc, that would be good to ppb level.So chances are that even the mems based oscillator is good enough - but I can't say for sure.