Making hsync from clk?  - Page 1
Forum section: electronics / projects

author: Nasdrasil
author_rank: Contributor
timestamp: July 02, 2021, 06:20:17 pm
content: Hello electronic nerds!This is my first post on here. Long time reader, now also a member :-)I am toying around with a retro computer that has an off spec hsync most of my tv's won't sync to. There is a 4 Mhz clock and I know all the hsync timings I need to make things work.I was wondering... would it be possible to use this clock signal, divide it, put it through something like a pair of ltc6994s to correct the duty cycle and timing and use that as hsync? Or am I totally looking in the wrong direction and is there a much better solution?I'm not looking for a ready-made solution but if some people could point me in the right direction that would be great!

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 02, 2021, 06:24:29 pm
content: I am assuming the original sync signal would need to be shifted in time, and/or its pulse width modified?If so, yes, sure, you can do this relatively easily. But first, you may want to give us some more details...

author: Benta
author_rank: Super Contributor
timestamp: July 02, 2021, 06:27:36 pm
content: I suspect the problem is that the retro computer doesn't provide serration/equalization pulses. But more info is needed.

author: Nasdrasil
author_rank: Contributor
timestamp: July 02, 2021, 08:08:05 pm
content: Indeed the original machine is missing serration and equalization pulses. There is nowhere I can pick those up. I have vsync. My plan was to recreate hsync and combine it with vsync into csync. I've just never done this. I was thinking to use an 8bit divider to get the right frequency and then adjust pulse width and timing with an ltc6994-1 and an ltc6994-2 to get correct hsync.

author: Bud
author_rank: Super Contributor
timestamp: July 02, 2021, 08:29:46 pm
content: What machine is it? Maybe an easy way is to buy a VGA or HDMI converter for it.

author: Benta
author_rank: Super Contributor
timestamp: July 02, 2021, 09:28:30 pm
content: Exactly what signals do you have, and what are their frequencies?You must have Hsync and Vsync already, otherwise this thing makes no sense. Interlaced or progressive scan? What's the vidoe format? RGB or combined?Your question is so vague and nebulous that an answer is practically impossible to give.

author: Nasdrasil
author_rank: Contributor
timestamp: July 03, 2021, 05:36:46 am
content: I'll try to give some more info then...It is a computer I am trying to modify to output rgb. My mod uses 3 bit rgb colors. (This is also what the system generates internally and uses create the stock rf signal) It's a pal system in progressive scan. I own a Framemeister, an ossc and a retrotink 5x. The Framemeister is able to lock on to the original sync signal the device creates. It gives me a wonderful rgb image but I'd like to use my ossc. This linedoubler does not like the original sync without pulses around and in the vertical interval.So yes... I do have hsync and vsync. Hsync just missing pulses that I am unable to get out of the system, which is why I'd like to create it from scratch by using the 4 Mhz clock frequency that is present. Hsync occurs every 64 us. Pulse lasts for 4.75 us.If I divide the 4 Mhz clock by 256 I get to 15625 khz, which could be my hsync frequency. I was thinking to adjust pulse width and timing until it matches the original hsync and use this new signal to create csync.

author: Ian.M
author_rank: Super Contributor
timestamp: July 03, 2021, 07:56:16 am
content: You should be able to do the whole thing in a smallish 8 bit MCU, albeit probably programmed in assembly language so you can get cycle accurate timing. It would be clocked by your external 4MHz signal to avoid dot crawl Choosing one with a PLL in its clock tree would give you more instructions per scanline permitting finer control of sync pulse timing.Existing Hsync and Vsync would go to interrupt capable pins. The MCU would be interrupted by the Hsync, and the ISR would do all the processing required to output the desired Csync. The Vsync interrupt would be disabled and the interrupt flag polled in the Hsync ISR to detect the start of a frame, The Hsync ISR would also count lines in the frame so it can divert to outputting equalizing pulses and vertical sync etc. on the proper lines in the inter-frame interval.

author: Benta
author_rank: Super Contributor
timestamp: July 03, 2021, 04:55:01 pm
content: Just a thought: if it's progressive scan, you probably won't need double-frequency equalization/serration pulses. Just inserting normal Hsync pulses during vertical blanking should be enough.That would make things simpler.

author: Nasdrasil
author_rank: Contributor
timestamp: July 04, 2021, 01:36:41 pm
content: Quote from: Benta on July 03, 2021, 04:55:01 pmThis is also what I thought. I ordered some LTC6994-1 and 2 IC's to play around with and see if I can control pulse width and timing. Then again... It might also be something that could finally lure me into trying something with an fpga. I know it's a long shot but I assume with a decent fpga there could even be the possibility for a linedoubler to output vga. With the level of knowledge I'm at regarding fpga's and programmable logic that'll be at least a year away before I could do something like that probably...