Implementing In-Situ Leakage Current Measurement into HTRB Testing System - Page 1
Forum section: electronics / projects

author: r1ch13
author_rank: Newbie
timestamp: September 21, 2022, 08:25:46 pm
content: Hello all,I am currently designing an automated High Temperature Reverse Bias (HTRB) system to conduct reliability testing/electrical characterization of diodes. I've designed the system to support reverse-bias testing from 0 to 5kV DC, using an SRS PS-350 (5kV, 25W) HV PSU for the reverse bias "stress" and a B1500A for the periodic device characterization. I have been trying to implement an In-Situ reverse leakage current measurement solution into the system capable of measuring leakage current from 1nA to 1mA (really only up to ~500uA as 100uA will be my non-destructive DUT failure threshold). My plan has been to use a TIA for this measurement but I've been running in circles trying to figure out how to stabilize it. I have been simulating with an LT1464https://www.analog.com/media/en/technical-documentation/data-sheets/146465f.pdfand will be using an AD974 (16-bit ADC)https://www.analog.com/media/en/technical-documentation/data-sheets/AD974.pdfto collect leakage current measurements. Plan is to do low-side measurement using the LT1464 as a TIA with a second LT1464 in an inverting unity-gain configuration, I've attached my overall circuit design and general schematic for the TIA measurement solution.Any help and guidance would be greatly appreciated!More than happy to answer any questions.

author: Terry Bites
author_rank: Super Contributor
timestamp: September 22, 2022, 06:18:41 pm
content: Its usually capacitance on the input that creates instability in TIAs. It may not be modelled or modelled correctly in your simulation.If its a contant value, you can compensate for it or compensate the worst case. You have to include all the stray capacitance wiring to the input.eghttps://e2e.ti.com/blogs_/archives/b/precisionhub/posts/how-to-get-the-best-performance-from-your-transimpedance-designs.Minimisethe bandwith of the measurment.If you have shielded cables and groundplanes in your jig you can neutralise this capcitance with a bootstrap circuit.https://www.edn.com/remote-photo-sensingNo potential difference, no Cdv/dt. Stray currents at the TIA input much reducedTriax cable is ideal. You drive the inner shield. It may be necessary connect the shield driver form potential divider to bring the gain a little below unity.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 22, 2022, 07:48:36 pm
content: If a fast response is not needed, one can add some resistance (e.g. 100-1000 Ohms) / inductance between the DUT and the TIA to isolate the TIA from the capacitance. In comparison to the relatively high test voltage the drop on the resistor should not be that bad.

author: r1ch13
author_rank: Newbie
timestamp: October 02, 2022, 09:16:13 pm
content: Thanks for the recommendations, I went back to researching TIA stability and learned how to go about quantitatively stabilizing TIAs by analyzing phase margin at the intersection of the open loop gain and 1/Beta curves. Ran through simulations again in LTSpice, determined appropriate pole/zero combos for the various ranging resistors I was thinking about using, and I've now got 80+ degrees of phase margin. I'd also been simulating total voltage noise and was averaging ~23uV RMS (~150uVp-p) on the LT1464s. Had to choose a different OA due to supply issues and settled on the ADA4530-1, re-ran all of my simulations and everything performs even better now, total voltage noise has dropped to ~15uV RMS (~100uVp-p).Great links that go through the technical foundations of TIA design:https://www.jensign.com/stability/index.htmlhttps://www.jensign.com/noise/https://www.jensign.com/tznoiseAD/index.html#cfequationsNow I'm currently working through figuring out how to design a PCB for this circuit with the appropriate connections, guarding/shielding, etc.I'd love to use triax for the entire run. This is difficult given the 5kV design requirement and PSU's SHV connection. So I'll be using coax for the run from the PSU to the DUT during the stress cycle, keeping this short to minimize capacitance, and then running triax from the DUT to the measurement circuit. The force/sense lines during the measurement cycle will be connected via triax.

author: r1ch13
author_rank: Newbie
timestamp: October 02, 2022, 09:24:25 pm
content: Thanks for the tip. I tried this out in LTSpice and it didn't provide a justifiable difference to my outputs or response characteristics. I designed the input capacitance for the worst case scenario that I'm expecting and even then still gave myself plenty of wiggle room with my phase margin. Doing some transient analysis shows a nicely critically damped response with a 2.5ms settling time!