Suggestions on first PCB Design. - Page 1
Forum section: electronics / projects

author: kicken
author_rank: Contributor
timestamp: January 22, 2017, 05:45:42 am
content: Greetings everyone. I've finally moved on to designing a PCB for mybinary clock projectafter having successfully breadboarded the circuit and fixed a few issues. After many iterations I think I've finally come up with a PCB layout that I'm reasonably happy with.If anyone has a few spare moments to take a quick look at the layout, I'd like any feedback you can give regarding it's design. For example, are there any major things I've overlooked that would cause problems or are just bad pratice?I'm not sure the best way to share the design. I managed to create a few images via KiCad of the top and bottom layers of the board, hopefully that will work. I've also attached an updated schematic. Higher resolution imagesare available on imgurTop:Bottom:Schematic:

author: PMOS
author_rank: Newbie
timestamp: January 22, 2017, 07:08:14 am
content: A partially-transparent front+back overlay (like [img=https://i.stack.imgur.com/rbhkY.png]http://this) can be nice, also.What is going on with that one trace from U12 that loops halfway around the board and then some? I'd try to re-route that.Ditto, you've got a couple of places where multiple traces go through vias where you could have only one do so. Unless it's a particularly high-speed signal, I'd do it the other way around.If you swap R1 & R2 you won't have to do that awkward "work the trace around the pin of R3" thing.I'd make power (and ground, not that that's applicable here) traces larger, generally speaking. Even if it isn't required here, it's good habit, and also makes things easier to comprehend when poking around later.I'd be inclined to keep the traces to the outputs on the front, and push other traces down when necessary, over your current arrangement.What exactly is the trace that loops from the ground pin of U10 around the minutes output supposed to be doing?

author: DTJ
author_rank: Super Contributor
timestamp: January 22, 2017, 10:48:35 am
content: Personally I think the the layout generally looks fine, very good for a first board layout. A few quirks but everyone has their own style.As PMOS says larger pwr tracks can't hurt, I generally use reasonably large tracks for signal traces even if they aren't needed.Is there a decoupling cap for each logic IC? This is generally done as a rule of thumb but often works fine with less caps.Maybe a cap on the board where the power enters.While you are at this stage is it worth considering changing the resistors / caps to SMD?Maybe a few test points (power, clock, ..... )and a ground clip test point.Maybe also add some 3.5mm mounting holes in the PCB corners if needed.I always triple check through hole drill sizes just in case I made a mistake.

author: mariush
author_rank: Super Contributor
timestamp: January 22, 2017, 12:09:22 pm
content: Just from the image of the pcb :move R4 below R5 , move D1 above R5 ... so you have now D1 | R5 | R4Move Q1 down under C3 since there's no real need for it to actually be there between those capacitors. Leaves you room to move C5 to the left and move the C3 up a bit between C5 and C1You could rotate R3 90 degrees to the left, flat side to the bottom.move U1 above the R1 and R2 resistors.don't break three traces with that trace going to C1. Could use a jumper link (0 ohm resistor, you get 0805 or larger 0 ohm smd resistors) to make the design look niceIf you have smd components in your design, why not replace C1, C2, C5, C6 with some SMD ceramic capacitors (in the case of that 47uF capacitor, you could use maybe 2 x 1210 22uF 25v+ in parallel, or a bit more, depending on how critical that capacitance is)

author: kicken
author_rank: Contributor
timestamp: January 22, 2017, 03:35:46 pm
content: Quote from: PMOS on January 22, 2017, 07:08:14 amI started with making the power traces a bit bigger but it seemed like they caused routing to be more difficult so I cut them back in size. According to the calculate in KiCad the 8mil tracks were fine for the level of current I would be using. I ended up just making everything an 8mil trace for consistency.If I make them larger what would be a good size? 10mil? Or maybe make the signal traces 6mil an leave the power at 8? I plan to have these done by OSHPark which says 6mil is the minimum. Somewhere online I read that 8-mil was a good minimum that would allow one to get a board done pretty much anywhere so that's why I went with that size.As far as the weird trace it looks like that's just an artifact of a previous attempt that I overlooked. At one point the ground plane wasn't able to fill into that area so I had to run a trace over. Now it's unneccessary. I also noticed after posting my ground trace on U11 was a unnecessarily wonky.Quote from: DTJ on January 22, 2017, 10:48:35 amNot quite one per IC, I did one per logical section of the circuit. There is one for the four ICs that handle seconds, 1 for the four minutes, 1 for the two hours and one for the 555-timer. Breadboard testing seemed to work fine so I suspect that is plenty. Since I'm using through-hole I wanted to save space on the board and cutting the number of caps seemed the way to go.I already have a good pile of through-hole resistors and capacitors so I figured I would just use those. I'll likely only ever make the three board that I get back from the first OSHPark run and I wanted to avoid ordering more parts than necessary to keep the costs down. I'm also not sure if I want to tackle the small SMD caps and such just yet for soldering. I'm still fairly new at soldering still and sometimes struggle with the SOIC chips I do have.Quote from: mariush on January 22, 2017, 12:09:22 pmThanks for the suggestions, I will give those a try.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: January 22, 2017, 03:46:39 pm
content: Your board is quite small and a funny size, this might be intentional.... if not I would be tempted to grow it a bit and put mounting holes in the corners. I tend to look at the pricing from the PCB supplier and use a board that is close to their pricing point... also having a say 50x70 board might be easier to remember when you come to the physical design of any box it will subsequently go in... but it all depends on the application.(You could design a laser cut or 3D print case in Fusion 360?)

author: Dajgoro
author_rank: Frequent Contributor
timestamp: January 23, 2017, 11:44:23 pm
content: Little note/suggestion: When doing 2L boards, I try to stick with the horizontal traces on one side and vertical traces on the other side method, which was very popular(most 80' computers are done like that).Using that method you can always route boards quickly without running into collisions, and the ground plane is still kinda intact.It might get bit tricky when using it where its mostly smd components, the method works best with trough hole components.

author: steaky1212
author_rank: Regular Contributor
timestamp: January 24, 2017, 10:11:19 am
content: Have you read this ->http://www.alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdfYou have lots of traces with less than 90deg angles to pads (specifically your power traces). This can cause acid traps whereby the track is over-etched - leading to potential yield issues. I always aim to have a minimum of 90deg but this might be quite old-school advice.I would second beefing up power traces. Not only does that reduce the voltage drop (and temperature rise) but it also lowers the trace inductance (a good habit to get into even though this is a low speed design).I would be also be tempted to include more decoupling capacitors. In the event of a change in current demand, where does this current come from? Is there the likelihood that you will get erroneous "ticks" due to transient voltage drops or induced signals?You've got SM technology already, so don't be afraid of using 0805 (or 0603) sized components. (Just read previous thread - you're already ordering parts and 100x 0603 or 0805 100nF caps won't cost that much).How are you protecting against reverse voltage (you will plug the power lead in the wrong way round)?

author: Zom-B
author_rank: Regular Contributor
timestamp: January 24, 2017, 09:22:42 pm
content: Decoupling caps don't look like they are close enough to the chips. The point of those is to absorb high frequency pulses, but you connect them via teeny 8mil traces which are quite long, and which resist the pulses (so they are not absorbed). A breadboard is basically a huge multi-cap, so your argument "it worked on the breadboard" is not correct.Common decoupling capacitors take only 300x90 mil area on the board so I'd look for smaller footprints.Tie the input of the unused logic gate to +5V. For CMOS no change, for TTL prevents current drain.

author: james_s
author_rank: Super Contributor
timestamp: January 25, 2017, 06:34:21 am
content: That looks really good for a first PCB, after a few boards I think you'll really have the hang of it. You've avoided one of my pet peeves that I see a lot with amateur PCB layouts and that's where traces are strung around at weird angles and inconsistent spacing or have sharp 90 degree bends. It looks so much nicer the way you've done it with only 0, 45 and 90 degree traces, bends 45-45 bends rather than 90, and relatively consistent spaces.My only advice is to fatten up the traces used for power and ground, there's really no reason to go thin when space for thicker traces exists. I rarely go smaller than 10 mil for any trace unless I have to, and for power I try to use at least 30 mil. Also if you can move the reference designators so that they're not directly under the component wherever possible it makes it easier down the road to tell which part is which once the board is assembled.

author: PMOS
author_rank: Newbie
timestamp: January 25, 2017, 02:58:43 pm
content: Quote from: steaky1212 on January 24, 2017, 10:11:19 amThis is, in fact, overly old-school advice. It's useful to keep in mind if you're home etching, but with modern board houses you really don't have to worry about that sort of thing unless a) you're dealing withreallynarrow traces, and b) the board house tells you to.There is another reason to avoid 90-degree+ bends, namely if you have a signal with a fast rise / drop (e.g. clock, serial data, etc) they are hideous for both signal integrity and EMI. They present themselves as an impedance mismatch, with all of the associated issues that causes. This is not specific to acute angles, but a 90 degree bend is worse than two 45 degree bends in a row. Also, there are ways around this by narrowing the trace, etc.Also, if you've got a trace carrying a lot of power, the narrow portion of the bend is the first to overheat and die. But that's not significant unless you're talking about absurd currents.

author: kicken
author_rank: Contributor
timestamp: January 25, 2017, 10:34:23 pm
content: Thanks for the suggestions everyone, I'll definitely take them all into account for v2.I went ahead and implemented some of the easier/minor improvments to the layout and sent in an order to OSHPark for some boards. I'm eager to test things out and play with some real boardsand I know it'll probably be a month or two before I'll have time to really refine the design and re-layout the board using SM resistors/capacitors. I can use these first round boards to see how well things work currently and know where I need to make improvements for the next round.For v2 I am thinking I'll go ahead and switch to SM resistors and capacitors, try and add some reverse-voltage protection and look into the 12/24 hour suggestions from the other thread. I'll probably just scrap the current layout and start over from scratch at that point and go ahead and increase the trace widths for the new layout.