ADC configuration setting - Page 1
Forum section: electronics / general

author: Kittu20
author_rank: Regular Contributor
timestamp: November 20, 2023, 04:24:06 pm
content: Hello Everyone,I'm using J type thermocouple and PIC18F45K80 to measure room temperature. It has a built-in 10-bit ADC in microcontroller. The room temperature changes slowly, maybe hourly. With the 10-bit ADC, we get 1024 steps.For 5V reference, 1 step = 5 / 1024 = 4.88 mVSo in this case what would be the step size and what would be the resolution of ADC?Does step size is 4.88 mV and the resolution 10 bits. ?

author: DavidAlfa
author_rank: Super Contributor
timestamp: November 20, 2023, 06:23:35 pm
content: Usually yes, unless the ADC is using a different voltage reference.PICs normally work with VDD, so VDD/1024.A type J will output millivolts, so won't be able to measure anything useful with the adc.You'll need a dedicated ic that provides signal conditioning and cold junction compensation, like the max6675.A simple op-amp will be able to amplify it, but won't provide compensation, though you could roughly compensate it in software.

author: Kittu20
author_rank: Regular Contributor
timestamp: November 20, 2023, 06:46:02 pm
content: Quote from: DavidAlfa on November 20, 2023, 06:23:35 pmThank you for confirming the information about the step size and resolution. I've noticed some referring to the step size as resolution, which caused some confusion on my end.

author: DavidAlfa
author_rank: Super Contributor
timestamp: November 20, 2023, 07:08:49 pm
content: The adc has 1024 steps, but the voltage step is actually VDD/(1024-1), thus 5/1023 = 4.88758mV.It's a minor difference, but the correct one.Wrong!

author: Kittu20
author_rank: Regular Contributor
timestamp: November 21, 2023, 02:16:23 pm
content: Quote from: DavidAlfa on November 20, 2023, 07:08:49 pmSo when we need to configure the ADC it's important to know about the resolution, step size and sampling interval so I know the two things now step size and resolution so what would be sampling interval in this case of temperatures example?

author: DavidAlfa
author_rank: Super Contributor
timestamp: November 21, 2023, 06:23:50 pm
content: The sampling or adquisition time depends on the adc and the external impedance, the adc charges an internal capacitor (Sample and hold), then starts the conversion.This capacitor is just few picofarads, but enough to cause issues if you feed the adc input with a resistor (Like 1K) and set the sampling too fast, the capacitor won't fully charge and you'll get inconsistent readings.Sanpling time is basically a RC constant, you want to fully charge that capacitor.Adquisition time (TAD) is often measured in ADC clocks, this depends on the ADC clock frequency, thus the same sampling time (Let's say 10us) will need need more ADC cycles as the ADC clock gets faster.Read the datasheet ADC section entirely!

author: mikerj
author_rank: Super Contributor
timestamp: November 22, 2023, 11:16:19 am
content: Quote from: DavidAlfa on November 20, 2023, 07:08:49 pmThis might be the case for some very specific ADCs (I've never seen one) but for typical SA type ADCs the LSB voltage step is Vref/2nand the full scale voltage is Vref*(2n-1)/2nand not Vref. The OP's LSB would therefore be 5/1024 volts if he had a 10 bit converter. However the PIC he states he is using has a 13 bit differential or 12 bit single ended ADC so his LSB would be 5/4096.Similarly for R/2R or string type DACs the full scale output voltage is one LSB below Vref(not Vref) and the LSB is Vref/2n. This seems to be a very common mistake.

author: Siwastaja
author_rank: Super Contributor
timestamp: November 22, 2023, 12:49:04 pm
content: Quote from: DavidAlfa on November 20, 2023, 07:08:49 pmNo, definitely incorrect. A classic mistake beginners usually make, but when you try to help, you should know better, or consider not boasting with "correctness" of your advice.(If you do find an ADC which specifies it like that, I would be quite worried about if it's really a special snowflake ADC design, or did they actually make that stupid mistake in documentation, to the point of contacting the manufacturer, but so far I have seen this mistake only on user side - and obviously made it myself, too.)

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: November 22, 2023, 05:46:48 pm
content: That mistake is very understandable because minimum voltage step depends upon the converter topology and one can think that every topology behaves the same way when converting analog to digital or viceversa but this might not be the case (i will assume that ADCs have inverted behaviour of DACs) and most features of a certain topology can apply to both ADCs and DACS.I think we can talk about linear converters (those which conversion complexity grows proportional to the maximum converted value), and log converters where their complexity grows with log(value), that is, linear to the amount of digits (i will refrain of talking about binary converters as they are just a very popular special base-2 case of general converters)Linears would include Vref at full scale because converted states do not represent points of conversion but intervals or segments. Think of pure PWM DAC (not a comditioned PWM in which its output can't reach 100% duty): 0% duty means 0V and 100% duty means Vref. If you set 1024 states, then you will set 1023 intervals between 0 and Vref, thus Vstep is Vref/1023.If you think of the most basic log converter, It is just a resistor divider (or multiplier in case of a reversed conversion). They can't reach Vref because there is always a resistor tied or referenced to ground (or to the next conversion stage in a modular Converter), that's like thinking that if you have one decimal digit, you can't count up to 10 because 10 needs 2 digits. In this case, if Vref is 10000000000b*Vstep, then Vfs will always be 1111111111b*Vref=Vref-Vref/1024.My two cents regarding log converters (in this video i use a nonbinary, noninteger DAC and a step sequencer to perform inverse ADC function).https://youtu.be/vPVH0n-kGaA

author: Nominal Animal
author_rank: Super Contributor
timestamp: November 22, 2023, 05:56:23 pm
content: As Siwastaja and mikerj described above, the quantization step of an \$N\$-bit ADC or DAC is normally \$V_\text{ref} 2^{-N}\$, with the maximum input/output voltage one step below the reference voltage \$V_\text{ref}\$, and minimum either zero or the minimum reference voltage \$-V_\text{ref}\$.While the data sheet for PIC18F45K80 does not explicitly say, Microchip ADCs datasheets do tend to explicitly or implicitly confirm this. I've checked the datasheets for MCP300x, MCP3021, MCP3201, MCP3221, MCP342x, MCP346x, MCP355x, MCP331x1, TC850, and TC7109, i.e. all Microchip ADC series sold by Mouser as of 2023-11-22, and they all have the aforementioned quantization step and minimum and maximum input voltages for their corresponding counts.(Some, like MCP355x, a 22-bit (21.9 ENOB) ADC, can read a couple of counts above and below the reference voltage; for these, the non-overflow maximum and minimum readings correspond to one step below the positive reference voltage, and the negative reference voltage, respectively.)The reason for this scale comes directly from the structure of standard binary weighted DAC (including R-2R ladder DACs), as it is at the core of both delta-sigma and successive-approximation (SAR) ADCs, the two most common ones currently available.For a standard R-2R ladder DAC with \$N\$ control lines at either zero or \$V_\text{ref}\$ potential, the output is between \$0\$ and \$\left(2^N-1\right) \, 2^{-N} \, V_\text{ref}\$, i.e. between zero and one step below reference voltage; it cannot reach the reference voltage.

author: eutectique
author_rank: Frequent Contributor
timestamp: November 22, 2023, 06:26:19 pm
content: Quote from: Nominal Animal on November 22, 2023, 05:56:23 pmHere is the MicrochipWhite Paperwhich claims differently.Also, the Equation 1-1 there contradicts the paragraph just above it.

author: Nominal Animal
author_rank: Super Contributor
timestamp: November 22, 2023, 07:04:08 pm
content: Quote from: eutectique on November 22, 2023, 06:26:19 pmNo, it actually does not.Per equation 1-1, when \$V_\text{in} = V_\text{ref}\$, \$\text{ADC} = 2^N\$. However, an \$N\$-bit ADC cannot produce that value, as the largest value it can produce is \$2^N - 1\$. If you solve \$2^N - 1 = 2^N \, V_\text{in} / V_\text{ref}\$ for \$V_\text{in}\$, you get$$V_\text{in} = V_\text{ref} (2^N - 1) 2^{-N} = V_\text{ref} - 2^{-N} V_\text{ref}$$exactly as I described: the maximum discernible input voltage is one step below the reference voltage.Yes, the text does have an error, in that \$V_\text{ref}\$ actually corresponds to ADC reading \$2^N\$, and not to \$2^N - 1\$ as the text claims.However, both the single-ended and differential section math equations agree with my claims (and contradict with the claim in the text), as well as the Microchip datasheets for their discrete ADC's.We could note that dividing the ADCrangeby 2 in the differential section is also an error, because for example MCP355x are marketed as having22-bit range, and that covers both positive and negative voltages. That is, applying Equation 2-1 to MCP3550 yields incorrect results. In particular, figure 5-1 in the MCP3550 datasheet explicitly lists \$\pm V_\text{ref}\$ corresponding to ADC reading \$\pm 2^{21}\$. Nowhere does anyone claim MCP3550 has "21-bit range".Because of these two errors, I claim that the author, Kristian Saxrud Bekken of Microchip Technology Inc., has repeated the same mistake DavidAlfa and yourself have made. Like I said, all Microchip ADC series currently sold by Mouser explicitly agree with my interpretation, either by explicitly listing the zero and maximum count input voltages, or by implicitly listing the equation for the ADC reading. Feel free to pick any of those datasheets, and I'll show you exactly where.

author: nctnico
author_rank: Super Contributor
timestamp: November 22, 2023, 07:09:12 pm
content: Actually it depends on the ADC itself so you have to check the specs of each ADC carefully. The ST and NXP microcontrollers I checked specify the ADC conversion range asVref / (2^n -1).Edit: 1 LSB = Vref / (2^n -1) so full-scale (FS) = Vref. So with Vref at 5V and a 12 bit ADC, you'll get a resolution of 5V / 4095 = 1.22mV per bit.

author: eutectique
author_rank: Frequent Contributor
timestamp: November 22, 2023, 07:23:50 pm
content: Quote from: Nominal Animal on November 22, 2023, 07:04:08 pmCouldn't agree more.Quote from: Nominal Animal on November 22, 2023, 07:04:08 pmAlso agree, and merely pointed to the fact that a vendor's datasheet can be wrong.Quote from: Nominal Animal on November 22, 2023, 07:04:08 pmYes, I was trawling the datasheet ofPIC18F45K80mentioned by the OP. Could not find the right formula or value.

author: Nominal Animal
author_rank: Super Contributor
timestamp: November 22, 2023, 07:47:46 pm
content: Quote from: nctnico on November 22, 2023, 07:09:12 pmThat makes absolutely no sense at all, as it would imply the range is a tiny fraction of the reference voltage. Are you sure you didn't confuse it with the PGC setting?STMicroelectronics ADC1283 explicitly lists LSB = AVCC/2¹² (which is in line with my claim). ADC120 datasheet does not say (either implicitly or explicitly).As to microcontrollers, all Nexperia ones I have have a successive approximation ADCs, and these have by their very structure \$\text{LSB} = \frac{V_\text{refH} - V_\text{refL}}{2^N}\$, and are limited to input voltages one step or LSB below the reference voltage (but including the negative/zero reference on the minimum).We do need to be very careful in interpreting the wording, too. For example, if the text specifies the valid range of input voltages from \$0\$ to \$(2^N - 1) \, 2^N \, V_\text{ref}\$, inclusive, it is fully in agreement with \$\text{ADC} = 2^N \, V_\text{in} / V_\text{ref}\$.This is excarberated by the fuzzyness in how humans denote intervals. The most commonly used interval in binary and programming includes the lower bound, but excludes the upper bound, because this has the most useful properties. Humans, however, vary in whether they include or exclude either bound in their description. So, even when they mean the exact same thing as above, a human may still describe the valid range of input voltages as being from \$0\$ to \$V_\text{ref}\$, because the difference is just one LSB and probably within full-range dynamic error anyway.(There are N+1 integers in range [0, N], N integers in ranges [0, N) and (0, N] each, and N-1 integers in range (0, N). Another common notation convention uses [0,N], [0,N[, ]0,N], and ]0,N[, respectively. Even the fact that there aretwocommon notations for ranges shows how "tricky"/easy to err in ranges are.)Quote from: eutectique on November 22, 2023, 07:23:50 pmThat's why I explicitly listed the Microchip discrete ADC chip series I had verified by my own eyeballs, and above place more weight on different sources agreeing than any single spot disagreeing.As you found, thePIC18F45K80datasheet does not give the formula or any examples one could infer this. I didn't even find a mention whether the converter is a SAR, sigma-delta, or something else. This is why I looked at the discrete ADCs instead: they tend to be better documented, but probably use very similar silicon as the integrated ones by the same manufacturer (barring acquisitions involving silicon designs).

author: nctnico
author_rank: Super Contributor
timestamp: November 22, 2023, 08:27:21 pm
content: Quote from: Nominal Animal on November 22, 2023, 07:47:46 pmNo, wrote the text in a hurry. You snipped the calculation that shows exactly what I mean. Bottom line is: there is no consensus among ADCs so check the datasheet. Things get even more interesting for 2's complement ADCs where +FS is vref - 1LSB value, while -FS is Vref.

author: DavidAlfa
author_rank: Super Contributor
timestamp: November 22, 2023, 09:58:50 pm
content: Yeah, I knew I was possibly screwing it up, my thinking changed to, hmmm, adc max is 1023 for 5V...?Your correction makes sense, to my understanding SAR ADC works in the "is the value higher than X ref?" principle, thus it can't measure absolute VDD, but ine step under.Am I correct?Yeah sorry for the mistake, I'm really getting home with total brain overload, I can't even remember driving home.Hopefully this will be the last weeks doing extended hours !Thanks, angry programmer horde straight from Mordor!

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 23, 2023, 12:23:11 am
content: Some (many) datasheets are confusing. But as others have already said, the usual for DACs and ADCs is to have a 1/2^N step. Now I have indeed seen implementations that would scale the result so that the effective step would be 1/(2^N-1), allowing it to reach Vref for the max value 2^N-1. Yes, it can be a big mess. So yes, I agree, RTFM.Note that in practice, it will matter only for the lower resolutions (low bit count). The error between steps of 1/2^N and 1/(2^N-1) is between 1/2 and 1 LSB over the full range, which is usually within the specs of ADCs and DACs unless they are very low bit count, or very high accuracy. In other words, it matters only on rare occasions.

author: Nominal Animal
author_rank: Super Contributor
timestamp: November 23, 2023, 01:45:37 am
content: Quote from: nctnico on November 22, 2023, 08:27:21 pmWhat do you mean? That is exactly the case I described for all Microchip discrete bipolar ADC chip series available at Mouser: the minimum is inclusive the minimum reference voltage, analog ground for unipolar ADCs; and the maximum is one step less than the maximum reference voltage.I have yet to see a single ADC that yields conversion value \$2^N-1\$ for the positive reference voltage (as opposed to for one step or LSB below positive reference voltage). I have found some ADCs (like the built-in one on the PIC at hand) that do not explicitly or implicitly define the conversion, but all datasheets I can find that do define it, define the positive reference voltage as corresponding to ADC conversion value \$2^N\$, i.e. \$\text{LSB} = V_\text{ref} 2^{-N}\$.Quote from: DavidAlfa on November 22, 2023, 09:58:50 pmNah, we all make mistakes; it's just a good idea to explore the region where such a common error occurs, and why.(No anger at all at least on my part, just trying to show what I am basing my current understanding on, because opinions aren't interesting but the reasons behind those opinions are.)PWM generation has a surprisingly similar issue. When you define the PWM period asNcycles, there are actuallyN+1 possible transition points per period. Most implementations have a delay or restriction, so that there must be two separate transitions per period, in which case onlyN-1 different duty cycles are possible – from one cycle high andN-1 cycles low, toN-1 cycles high and one cycle low.Some implementations do not have such limitations, so that with a PWM period ofN, zero yields an always low output, andNyields an always high output, both with a possible "glitch" spike (narrower than a clock cycle) at the beginning of each period. When the PWM register isN-bit, the maximum period length where both always-low and always-high is possible, is \$2^N-1\$; not \$2^N\$. That corresponds to TOP counter value of \$2^N-2\$, not \$2^N-1\$.At the root of these both is the mathematical fact that the range from \$0\$, inclusive, to \$N\$ exclusive or \$N-1\$ inclusive, has exactly \$N\$ integers.A successive approximation ADC uses a DAC and \$N\$ steps to find the DAC value that corresponds to the ADC sample voltage at \$N\$-bit precision, using a binary search. At each step, the DAC output corresponding to the middle value in the current range is compared to the sample. If larger, the upper range is chosen; if smaller or equal, the lower range is chosen. \$N\$ steps provides exactly \$2^N\$ different possible values.There are only three ways how a SAR ADC could yield code \$2^N-1\$ for the upper reference voltage: one is by choosing the upper range is equal or larger, and lower range if smaller. That leads to an ADC that cannot discriminate between lower reference voltage (ground) and one step or LSB above it. The second is to prescale the reference voltage by a factor of \$2^N / (2^N - 1)\$ somehow. The third way is to use an additional step, but instead of doubling the range of ADC values, only use it to discriminate between two ADC values.For delta-sigma ADCs, like MCP346x that use 5-level quantizers (\$+V_\text{ref}\$, \$+V_\text{ref}/2\$, \$0\$, \$-V_\text{ref}/2\$, and \$-V_\text{ref}\$), the modulator output (intermediate representation)candescribe input having either positive or negative reference voltage. It is the digital decimation filter phase that determines the output code range. However, filter window sizes and outputs that are composite numbers having only small factors are the easiest to implement, requiring the least amount of silicon, because the typical decimation filter stages (first- and third-order sinc filter integrators and differentiators) are very simple FIR or IIR filters consisting only of coefficients +1, -1, +3, and -3. Powers of two are the easiest, but for the exact same reason as the PWM with power of two period, cannot represent both minimum and maximum at the same time.The simplest method to obtain an ADC that does yield code \$2^N - 1\$ for \$V_\text{in} = V_\text{ref}\$ and code \$0\$ for \$V_\text{in} = 0\$, is toskipthe middle-range code. That is, for intermediate code \$0 \le x \le 2^N\$, the actual output value \$y\$ is \$x\$ iff \$x \lt 2^{N-1}\$, and \$x - 1\$ for \$x \ge 2^{N-1}\$. This increases the mid-range "glitch" (step size between codes \$y = 2^{N-1} - 1\$ and \$y = 2^{N-1}\$), but allows the output to cover the entire range. Note that this is exactly \$y = x \times 2^N / (2^N - 1)\$ with proper rounding!

author: DavidAlfa
author_rank: Super Contributor
timestamp: November 23, 2023, 08:14:33 am
content: Just joking Nominal Animal!I always find funny when someone having issues posts forbidden/sacrilege code (Bad pointer casting, integer overflow, etc)...I set the kitchen countdown to 2 minutes and run away to stay safe from the incoming rushIt's gonna blow!!

author: Siwastaja
author_rank: Super Contributor
timestamp: November 23, 2023, 08:45:42 am
content: I'm quite confident to bet that if any microcontroller datasheet claims that (largest_value - 1) corresponds to reference voltage, that is in error, not the actual behavior; so I would proudly give theoppositeadvice: donotcheck the datasheet, instead assume!eutectique's example is ... exemplary, as it contradicts itself and offers both wrong and correct information.Microcontroller datasheets tend to havea lotof errors, especially ST's. Like, if you check 100 "this is how this configuration bit works" claims, at least 10-20 of them are slightly wrong and a a few completely bogus. The documentation is written in hurry, not checked by others, and usually not maintained, it's fire-and-forget, many manufacturers simply have no processes in place to allow customer feedback to ever reach the documentation writers, and they have no proper document revisioning, so all they actually do is to add a note in aseparateerrata document, and they don't do this when a peripheral does not work as described in the primary documentation, they only do it if it does not work as theyintendedit to work.

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: November 23, 2023, 11:31:14 am
content: Quote from: SiliconWizard on November 23, 2023, 12:23:11 amThere is another situation in which the full scale output value differs substantially from Vref. That's when the digits base approaches 1 (base must be over 1 because 1^N is always 1 whatever the Nth digit is). Because Vmax=Vref(1-1/K^N), then, for example, if K=2^(1/12), for 12 digits DAC, Vmax=Vref/2.https://tinyurl.com/2fl5k6oj

author: Siwastaja
author_rank: Super Contributor
timestamp: November 23, 2023, 07:55:31 pm
content: Quote from: SiliconWizard on November 23, 2023, 12:23:11 amKinda sorta yes, but the error is awkwardly close to something that really matters. For example, 10-bit ADCs are not rare, and there error from the wrong formula would be at most 0.1%. It would be not weird at all to use a voltage reference with accuracy spec of, say, 0.2%, or 0.1% resistors (they are still cheap and plenty, unlike 0.01%) for something mundane such as li-ion voltage sensing. Sure, a sane designer does not count on the LSB being accurate, but given some software noise filtration and a $0.50 external reference it's not wrong to expect +/- 2 LSB performance from a 10-bit or 12-bit ADC, and 1 LSB error is then already half of your error budget!