FPGA EEVBlog segments / Xilinx buyer's remorse - Page 1
Forum section: electronics / general

author: rs20
author_rank: Super Contributor
timestamp: May 20, 2014, 09:49:41 am
content: Now I know Dave's busy, and he doesn't need to explain anything because he's always got many things on his plate, but there was mention of some FPGA segments for the EEVBlog. I wonder if licencing/development issues stunted that idea, for the same reason that he's indicated that he won't do Altium Designer tutorials. (Note -- I fully 100% support this reasoning -- no point doing hobbyist videos that start with "fork out a few hundred dollars" as step 1).Many (specifically, six) years ago, I bought a Xilinx Spartan-3E starter kit for a hobbyist-friendly $180 or thereabouts. I opened it up, played with it for a bit, and discovered that the software that came with it was an evaluation that expired after some set period. This disillusioned me, and put me off playing with it any further once that period elapsed.Fast-forward to 2014, and I find this thing sitting in the cupboard and I think to myself, "I was young back then. Maybe I misunderstood the licence period issue, maybe I can still develop with this thing." So I download Xilinx ISE Webpack (or something), and 6GB and only a little effort later, I've implemented and testeda circuit of mind-blowing complexitytwo NAND gates! Hooray! Now, on to the most important part of most (?) FPGA projects: the soft-core. It strikes me that most FPGA solutions (indeed, most digital circuits these days) require some kind of CPU somewhere to oversee the operation of the system (whether it be a dedicated MCU/CPU, or a soft-core onboard the FPGA). This is the bit that stuns me: in order to use Microblaze, Xilinx's soft core, I apparently have to shell out $500+ for a Xilinx EDK licence. I just can't justify that for playing around; but if I can't play around, I can't discover what this board is capable of. In other words, it's a $180 catch-22 doorstop.This Spartan-3E starter kit has the unenviable distinction of being the only thing I've ever bought that has hit me with buyer's remorsetwice.What's particularly perplexing to me is that Xilinx makes less than 5% of its revenue* from development tools. How does this even make sense as a corporate strategy? Even well-implemented licencing systems** create road-blocks for everyone involved. It must cost money for them to maintain a licencing system, it'll cause no end of headaches and lost productivity amongst the companies using Xilinx tools, and any companies out there using Altium tools won't be able to freely experiment with Xilinx tools. Does it really make sense to suggest that the increased adoption of Xilinx FPGAs resulting from a free*** software ecosystem might be less than the 5% increase in hardware revenue it'd take to cover the hypotheticaltotalloss in software revenue?Time to turn this rant into a pragmatic question. Has anyone succeeded in developing a Xilinx FPGA solution with a soft-core without forking out hundreds? How? Eval licenses and vouchers with dev boards don't count. Can you generate 30-day eval licences over and over again, or does it only allow one eval per product per MAC address?*Source-- and they've got a healthy margin on hardware production costs, so this can be translated as very approximately 5% of profit.** the Xilinx licence system involves receiving licences by emails and having to download and manually install them, so not well-implemented then*** Free as in beer.

author: jeremy
author_rank: Super Contributor
timestamp: May 20, 2014, 10:05:03 am
content: I hear you. Not only do you pay through the nose for the IC, it's then a big chunk of money for the dev tools (which are pretty counterintuitive anyway...)I have been planning to try this:https://github.com/m-labs/lm32but haven't got around to it yet. I know the MiSoC guys have it working though.Oh, and the LM32 has gcc supportedit:http://www.xilinx.com/products/intellectual-property/picoblaze.htm?

author: hamster_nz
author_rank: Super Contributor
timestamp: May 20, 2014, 10:23:36 am
content: Hi RS20.The 'free' stuff is out there, you just have to look away from the vendor's own solutions - the exception beinghttp://en.wikipedia.org/wiki/LatticeMico32,which can run on pretty much any FPGA (not sure if you actually should be doing that though!).Have a look at ZPUinohttp://www.alvie.com/zpuino/- 32-bit micro with an Arduino interface.I've also played around with the AVR8 core (http://papilio.cc/index.php?n=Papilio.ArduinoCore), and put a character mode VGA interface onto it. Might be a good use case for those who like the Arduino / AVR stuff.I've ported socz80 (http://sowerbutts.com/socz80/) to a new board in an evening for that old time CP/M feel - however a 125MHz Z80 with 8MB RAM is a bit OTT.Mike

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 20, 2014, 10:43:45 am
content: A processor is a fairly inefficient use of FPGA resources, which is why we are now starting to see embedded ARMs.Unless you have the spare FPGA space available (e.g. you need the pin count, which dictates die size) it will often be cheaper and simpler to use a seperate processor.As regards EDK, a while ago there was a devboard that came with a version of EDK that was locked to the device type on the board - not sure of there was any time or other limitations on this.

author: nctnico
author_rank: Super Contributor
timestamp: May 20, 2014, 10:49:40 am
content: Look at the LM32 softcore from Lattice. I recently did a project with that softcore on a Xilinx Spartan 6 using the free Xilinx Webpack ISE 14.7. It has GCC toolchain support. All in all it is pretty cool.http://www.ohwr.org/projects/lm32http://blog.tkjelectronics.dk/2011/02/porting-the-latticemico32-to-a-xilinx-fpga/

author: FrankBuss
author_rank: Unknown
timestamp: May 20, 2014, 12:46:42 pm
content: There are dozens of CPUs onhttp://opencores.org/projectsUsually they are not as well integrated as the ones from Altera or Xilinx and mostly without debugger, but many of the projects provides a toolchain to compile C code and if you don't need much memory, using the internal BRAM of the FPGA makes it even easier to use it. And can be interesting to look at the source code to see how it works or even modifiy the core.But as Mike said, a softcore is inefficient on FPGAs. Good for playing with devkits, but if you design a product, you can get a small ARM microcontroller for some dollars, which would require a FPGA costing hundreds of dollars. Use FPGAs for high speed, high IO and time critical tasks, and an additional microcontroller for the rest.

author: nctnico
author_rank: Super Contributor
timestamp: May 20, 2014, 01:24:55 pm
content: A seperate controller is easier for development but let's remember that the first Rigol scopes used the Microblaze softcore. A softcore in an FPGA is not very efficient indeed but you can greatly accellerate lots of stuff. If you attach a DMA engine to the softcore you can create extremely fast memcpy (memory to memory copy) and memset (initialize memory) functions. The same goes for things like CRC, a-law/u-law, JPEG compression, etc, etc.

author: rs20
author_rank: Super Contributor
timestamp: May 20, 2014, 01:27:36 pm
content: Thanks for the awesome responses everyone! Looks like LM32 (which I hadn't heard of) is getting a lot of upvotes; it looks quite impressive. I like how it's configurable, and it's got the whole wizard thing going on (I'm a Makefile kind of guy, but sometimes I just need that wizard for baby steps...). Seems like there's some difficulty on running it on a Spartan-3E (I don't even know how many LUTs I have, I should look that up) but apparently it can be done with some degree of tinkering. I now have a warm fuzzy feeling towards Lattice.I know half my LUTs are going to be burned on the soft-core which may be a bad idea in an end-use scenario, but it should be good for initial playing around with the devkit. I don't have a particular project in mind (except, of course, for the classing FPGA 'Hello World': VGA pong), but when I reach that stage I'll definitely look into getting a chip/devkit with a hard core (whether or not it shares a package with the FPGA). The Xilinx Zynq parts look amazing (and almost certainly too high-end for anything I'll ever do), but last time I really shopped around for FPGAs was 2008 so it's probably run-of-the-mill by now...Has anyone dealt with FPGAs on their own PCBs? The other pain point is those BGA packages... I've seen some 1mm pitch BGA packages that might be hot-air-gun friendly? I need to play with CPLDs too *mind explodes*

author: Scrts
author_rank: Frequent Contributor
timestamp: May 20, 2014, 02:02:57 pm
content: They have changed the politics now.If you'd buy ZedBoard, they would include a device-locked license, so you can do anything you want on that board.Anyway, I am Altera guy... I've started with the same Spartan-3E board you had, but the MIG (Memory Interface Generator) was terrible back then. Also Virtex-4 PCI-e hard ip had longer errata sheet than its datasheet. Switched to Altera pretty fast.Now my work requires to go back to Xilinx againHopefully, they've made some improvements.

author: FrankBuss
author_rank: Unknown
timestamp: May 20, 2014, 02:06:23 pm
content: Right, the Zynq chips look interesting. I think theParallella boardis one of the cheapest devkits you can get with it, and it has this parallel thing chip, too. I got mine from the Kickstarter campaign, now I need some time to play with itQuote from: rs20 on May 20, 2014, 01:27:36 pmYou can get many FPGAs as TQFP, too. I used a MachXO2 for myCrazy Cartridge prototype. Easy to solder, and some versions need just one 3.3V supply voltage and have integrated configuration flash, like a CPLD, but which is updatable from within the running FPGA. Pretty nice chips for smaller projects.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 20, 2014, 02:27:33 pm
content: Quote from: FrankBuss on May 20, 2014, 02:06:23 pmIt is sometimes possible to do QFPs on 2 layers - one thing I like about the Lattice XO2 is the onboard core voltage regulator, so you only have one rail to route, which you can do under the chip. Dual rails can sometimes be doable but depends on the location of the pins. A nice thing about FPGAs is you have huge flexibility on pin placement, which greatly simplified PCB layout.

author: marshallh
author_rank: Unknown
timestamp: May 20, 2014, 08:15:09 pm
content: If the first thing you try with an fpga is do a softcore... You're doing it wrongWorry about that later once you know what you're up to

author: nctnico
author_rank: Super Contributor
timestamp: May 20, 2014, 09:26:14 pm
content: The biggest problem with QFP is that the larger FPGAs are not available. Putting a QFP FPGA on a 2 layer board is very doable. I usually have the various supply voltages as rings underneath the FPGA on the top layer. A short trace goes to the pin and a decoupling capacitor from the pin to ground does the rest. The trick is to keep the bottom layer as a mostly solid ground plane. The freedom of choice for the pins (beware some pins can be input only) allows for very clean PCB layouts.

author: Bassman59
author_rank: Super Contributor
timestamp: May 20, 2014, 09:30:34 pm
content: Quote from: rs20 on May 20, 2014, 09:49:41 amMy guess would be that many professionals start to think, "Oh, it would be great to integrate a soft-core processor into the FPGA ..." and then they actually do it once, and realize that it's a disaster for a whole lot of really good reasons, and never do it again.Really Good Reasons include: vendor-provided cores changing with each tools release for No Good Reason, vendor deprecating one processor bus for another for No Good Reason, vendor-provided IP cores that are buggy and/or have poor performance, tool chains that are cantankerous, etc.Another really good reason is that you can use a less-expensive FPGA next to a standalone processor and have the whole solution be a lot less expensive than the processor-in-FPGA.QuoteWell, I have that board, and it's quite capable of doing a lot of things without a having a processor. Many FPGA designs simply don't need a sequential-execution C-programmable processor.Having said that, certainly Xilinx could have chosen to give away the EDK, but I have to ask: why? For companies who do that kind of work professionally, the cost of the license is in the noise. (It would be nice if the cost of the license included real support, though.)

author: rs20
author_rank: Super Contributor
timestamp: May 21, 2014, 01:05:22 am
content: Quote from: marshallh on May 20, 2014, 08:15:09 pmRead my original post, I have done my two NAND gates, so I'm ready for soft cores! (Jkz)But seriously, as I hint at below, I've never had a moderately interesting digital PCB without a micro on it, so I can't currently conceive of doing a moderately interesting digital solution without a sequential processor of some sort. As my dev kit doesn't have a standalone MCU, I have no choice.Quote from: Bassman59 on May 20, 2014, 09:30:34 pmEnlighten me: how do you drive that LCD without a sequential-execution processor? It seems to me that converting integers to decimal, performing string processing, and iterating through each char and pushing it out to the LCD would be incredibly obtuse to write in Verilog/VHDL. Am I wrong/missing something? I agree in principle, I want to avoid using a soft core if there's areasonableway of avoiding it.QuoteYou're exactly making my point: the cost of the licence is noise to both Xilinx and the purchasing company, but the impediment to developement/pain-in-the-backsideness of dealing with licenses is not (I claim). It seems like a lose-lose for all involved.

author: SirNick
author_rank: Frequent Contributor
timestamp: May 21, 2014, 01:22:32 am
content: Quote from: Bassman59 on May 20, 2014, 09:30:34 pmI don't know that I've ever worked at a shop where something with what should be a trivial cost, wasn't still a pain point. I don't work in the EE industry, so while things could be different, I recall once ordering six Sun database servers, and finding no one that would allocate enough from their budget to buy a sack of RJ-45 ends to cable them up. Similarly, management wouldn't conceive of using free software that would remove the need to license a Windows server on every CPU in a VMware cluster, while we also had to buy support contracts for secondary hardware because it was easier to pay $10,000 once a year than $250 to replace a PSU if it failed.Ridiculous? Yeah, absolutely. But man.. you can't tell me there hasn't ever been a workbench with a crate full of FPGAs still sealed in their anti-static bags, and no one willing to spend money on a license to use them. That $500 is gonna stick insomeone'scraw. If it isn't a major profit center, it just makes no sense.

author: hamster_nz
author_rank: Super Contributor
timestamp: May 21, 2014, 01:58:12 am
content: Quote from: rs20 on May 21, 2014, 01:05:22 amI made a Reflow Controller for a domestic toater oven using a FPGA with:- Fully stand-alone operation - with a USB power pack- A reasonable amount of control over the heating profile within the design (e.g. ramp up, soak, peak and so on)- RS232 serial interface to host for logging - updates every second.- 4-digit seven segment display, with intellegent autoscaling- Thermocouple ADC interface using a MAX31855All without any soft CPU. Sure, I could have grabbed an Arduino and a few libraries, but what is the fun in that?The big problem with most HDL development is that unless you use pre-designed parts then you have to do it all yourself. No Arduino user would need to or bother reading the datasheets or studiying the timing diagrams, we just borrow use somebody else's library. With FPGAs you are designing logic to talk directly to the chip, so that stuff on the datasheet matters - setup times, hold times, max/min clocks, command latencies...There are a lot of things you can do in HDL that make what seems stupid to do in software actually a reasonable solution.If you have a 6 digit decimal display that needs updating once per second? If so, you don't use division - you can just count in decimal and binary at the same time to do the conversion in under 1,000,000 cycles. Or if you want to do it quicker, count off the thousands and then the units, it will use a little more logic, but will do it in 2,000 cycles.Or you can use this non-obvious solutionhttp://www.eng.utah.edu/~nmcdonal/Tutorials/BCDTutorial/BCDConversion.html,and convert the number in about 20 cycles, in what would be completely silly way to do it in software.I guess I am trying to say that early on in your HDL experiments everything is hard, even if you are an experienced programmer. Can you remember how hard it was to first convert a number to ASCII without using a library function? Or how hard it was to print out a string backwards?That is how hard you should expect using a HDL to be, until you build up the the experience to follow your gut instinct to the solution.

author: Someone
author_rank: Super Contributor
timestamp: May 21, 2014, 02:10:59 am
content: Quote from: rs20 on May 21, 2014, 01:05:22 amWell you probably don't need a 32 bit processor running at 100MHz with MB of ram to do that processing. The picoblaze from Xilinx is free, and they had a tiny fixed config microblaze for free at one point.But those tasks are easy enough to do in the FPGA using a series of state machines (the fundamental building block of most FPGA systems). Probably best you buy a book or find a online course focused on FPGA design and work through that.

author: jeremy
author_rank: Super Contributor
timestamp: May 21, 2014, 02:44:41 am
content: Quote from: hamster_nz on May 21, 2014, 01:58:12 amRight, but this seems like it is probably a very inefficient way to do it. For the features you described, doing everything (plus PID) with a microcontroller is almost trivial. While I do appreciate you were doing this for fun, I think the OP is looking for the simplest solution possible.If for example, you are doing some complicated filtering of some ADC signal in the fabric and then you just want a way to display a graph on a graphic LCD module and log the results to an SD card, I think that a soft core would be a very good idea? Doesn't really make sense to write a whole bunch of verilog to do that (at least to me anyway), when you can quite simply and easily do it in C

author: miguelvp
author_rank: Super Contributor
timestamp: May 21, 2014, 04:15:37 am
content: Surely you can do sequences in HDL, you cant avoid being sequential in most cases. For the LCD you have a pixel count that increments every clock, that's your memory buffer address and position in the screen. Sure you can do things in parallel but most of the times everything is a sequence of events, and you can't get to the next event until the previous one is done.Otherwise I would do all my coding in VHDL if it only took one cycle to get the final resultYou don't need a soft core to drive an LCD or access memory etc..Edit: and you don't have to use counters or state machines either (although they are better) you can just program sequences that will execute one after the other and you can put delays between them if needed.

author: jeremy
author_rank: Super Contributor
timestamp: May 21, 2014, 04:44:48 am
content: Sure you can use the graphic LCD, but I'd hate to be the person who has to implement graphic lcd *and* SD card (with FAT) support in a HDL.

author: miguelvp
author_rank: Super Contributor
timestamp: May 21, 2014, 04:48:49 am
content: Quote from: jeremy on May 21, 2014, 04:44:48 amWhy do you hate hamster_nz, he has done that and more I believe

author: hamster_nz
author_rank: Super Contributor
timestamp: May 21, 2014, 05:41:09 am
content: All I've done is read blocks from an SD card.... only a nutter would build a FAT state machine.Let me see... read partition table... read block zero... jump ahead to the directory... look for file.... jump back to fat table... follow cluster chain.... stream audio....Yeah.... nah. CPUs have some use!

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 21, 2014, 08:51:42 am
content: Some people seem to be losing sight of when you should use an FPGA, i.e. when it's too time-sensitive to do on a processor. If you can do it on a processor, then do so - only do stuff in HDL when the processor can't do it fast enough, or when an MCU's I/O isn't a good fit for the interfacing requirement.Writing a UI or FAT file system in HDL would be ridiculous, but in these examples an FPGA could help accelerate things, to render fonts to an LCD, or handle the raw datastream from an SD card once the FAT software on the MCU has worked out which sectors to read. (Actually I think a read-only FAT SD card implementation wouldn't be that hard to do in an FPGA, but writes would get very messy very quickly)HDL is much harder to write and debug than code. Everything you do in HDL takes up far more physical space on silicon than code in flash, so you should only use FPGA resources where necessary.In most cases an external MCU+FPGA will give the best balance between cost, power, and development effort. There will be cases where it makes sense to put the MCU on the FPGA, e.g. if you need tight coupling or a small MCU in a big FPGA, but I suspect these will represent a small minority of applications.Something else to consider is that you will often want a way to update the FPGA config - having a seperate MCU to handle this, not dependent on the FPGA to operate, will make this a lot easier.Another approach that can be appropriate in some cases, if you have some spare block memory, is to use this as ROM to implement a simple sequencer to do some sequential type stuff, though you may need to write your own tools to generate the data.

author: amyk
author_rank: Super Contributor
timestamp: May 21, 2014, 12:07:53 pm
content: Quote from: hamster_nz on May 21, 2014, 05:41:09 amEssentially you would be implementing most of a CPU if you tried that... which isn't necessarily a bad thing, some people like the challenge after all; but I agree with everyone else here saying that FPGAs are not the best way to do this.

author: Fsck
author_rank: Super Contributor
timestamp: May 21, 2014, 12:48:31 pm
content: Quote from: mikeselectricstuff on May 21, 2014, 08:51:42 amthis isn't a "some people" thing, it's a "quite often" thing. people go "oooh, we can put everything in one package, let's do it!"and then you also have the people who use a softcore with just a couple of trivial pieces of digital logic in an fpga instead of using something like a psoc.

author: legacy
author_rank: Super Contributor
timestamp: May 21, 2014, 01:06:28 pm
content: Quote from: hamster_nz on May 20, 2014, 10:23:36 amIt is known to be not really working

author: legacy
author_rank: Super Contributor
timestamp: May 21, 2014, 01:32:36 pm
content: about VHDL and learning VHDLwhat do you think aboutthistool ?(green mountains direct vhdl, editor and simulator)

author: miguelvp
author_rank: Super Contributor
timestamp: May 21, 2014, 02:45:52 pm
content: Quote from: legacy on May 21, 2014, 01:32:36 pmI took a look and for $49 seems like a good price but their vhdl tutorials pale compared to resources available out thereFor example you could get a DE0-Nano or other lower cost FPGA dev kit and get Quartus II for free. or just use Quartus II for free without an FPGA and simulate all you want.Plus Altera's training has a lot of material, this is just part of it:http://www.altera.com/education/training/curriculum/fpga/trn-fpga.htmlWas tempted to download the Green Mountain software to see if they have a trial period, but didn't do it.

author: legacy
author_rank: Super Contributor
timestamp: May 21, 2014, 07:33:04 pm
content: mmm they are offering you "VHDL studio" for eval, 15 days for free.i Altera and Xilinx are missing a good editor, SIGASI seems to be a valid one, unfortunately the free-license is limited to 32Kbyte of VHDL code for the whole project which is too poor for me.About Modelsim … well i'd like to tryout the Mentor's one, never done, but i am tempted

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 21, 2014, 08:19:28 pm
content: Quote from: legacy on May 21, 2014, 01:32:36 pmBear in mind you can write and simulate VHDL & Verilog with any of the FPGA manufacturers' toolchains without needing any hardware.

author: miguelvp
author_rank: Super Contributor
timestamp: May 21, 2014, 08:36:37 pm
content: Quote from: legacy on May 21, 2014, 07:33:04 pmAgreed on Quartus II editor not being better, I mean it's good enough but what gets me is that I can't do a simple find in project unless I open every single file.I have not tried to override the text editor yet, but I guess I should try that one of these days. It's under Tools/Options/Preferred Text Editor, with Sigasi being on that list, but since I have Notepad++ I might see what I can do with that, just tried it and it work but haven't really use it just know it works.I've even looked at the Notepad++ API and it's simple enough for Windows. But Np++ has already Verilog and VHDL support as a language and it's free. No SystemVerilog (.sv) support yet but adding new language support is possible and probably already on the net.As for the simulation modelsim-altera is fine for my needs and it's free as well, but you can override all that on a per project bases and plug in the tools you prefer for synthesis and/or simulation.But my point is that for $49 you can get this:http://parts.arrow.com/item/detail/arrow-development-tools/bemicrocvand actually use it instead of just simulateEdit: Ha, I convinced myself to get one even if I already have a Cyclone V E dev kit but this has standard GPIO's for LVDS instead of the high speed mezzanine connector that cost an arm and a leg. Well it's just a grade 8 speed so 333MHz max, and my Nano is grade 6 (faster) but for $50 had to get it

author: nctnico
author_rank: Super Contributor
timestamp: May 21, 2014, 11:25:51 pm
content: Quote from: legacy on May 21, 2014, 07:33:04 pmI have used Sigasi + Eclipse for a big project and it works excellent. Much better than the utterly useless 'notepad' clone in ISE. So far I used the trial license but if I need to continu the project I'll shell out €70 for using Sigasi another month.I'm using GHDL + GTKwave for simulation. I know the newer IDEs have simulation but GHDL and GTKwave where there sooner for me. And I don't simulate entire FPGA designs; only partial blocks of logic to keep simulation time down.

author: legacy
author_rank: Super Contributor
timestamp: May 21, 2014, 11:38:40 pm
content: Quote from: nctnico on May 21, 2014, 11:25:51 pmthat's fun for me, toothank you for the suggestioni am emerging them in my gentoo box=)

author: legacy
author_rank: Super Contributor
timestamp: May 21, 2014, 11:41:27 pm
content: about gentoo & VHDL projecting using GHDL and GTKWaveyou simply should have to emerge these twoCode:sci-electronics/ghdlHomepage: http://ghdl.free.frDescription: Complete VHDL simulator using the GCC technologyCode:sci-electronics/gtkwaveHomepage: http://gtkwave.sourceforge.net/Description: A wave viewer for LXT, LXT2, VZT, GHW and standard Verilog VCD/EVCD files

author: legacy
author_rank: Super Contributor
timestamp: May 22, 2014, 12:29:16 am
content: Seecommentsfrom sigasi blogFrom my point of view, no problems at alleven if .. GHDL is written in ADA and GNAT is not so friendly (especially on gentoo)i am successfully emerging the whole

author: nctnico
author_rank: Super Contributor
timestamp: May 22, 2014, 12:41:15 am
content: Quote from: legacy on May 22, 2014, 12:29:16 amIf you read the last remark on that page you'll see the article is outdated.

author: miguelvp
author_rank: Super Contributor
timestamp: May 22, 2014, 12:52:08 am
content: Downloading Sigasi Starter Edition because:http://www.sigasi.com/sigasi-starter-editionSigasi Starter Editionbeats any existing VHDL editorforever freegreat editor for any size projectfully functional features from Sigasi Pro, for small projectsAnd I can configure Quartus II use that editor instead of the built in one, seems the 32K limit doesn't apply to the editor part of it.

author: alex.forencich
author_rank: Frequent Contributor
timestamp: May 22, 2014, 04:37:29 am
content: Quote from: nctnico on May 21, 2014, 11:25:51 pmI use Kate for editing, then iverilog + gtkwave for simulation. I'm actually looking at MyHDL for Python based testbenches right now; should be a lot easier to write a good Python testbench and then do a cosimulation with iverilog as opposed to writing the testbench in pure verilog, especially for things like DMA over PCIe or Ethernet/IP/UDP/TCP. Unfortunately, this won't work with the serializers and deserializers, only the interfacing logic. I also have makefile toolchains for Xilinx ISE and Altera Quartus 2, along with Xilinx Coregen and Altera QSYS. Good 'ole 'make' and 'make program' takes care of business. Although for one design, it still takes about 4 hours to complete place+route (targeted to a Virtex 6 HXT 565).

author: legacy
author_rank: Super Contributor
timestamp: May 22, 2014, 12:10:07 pm
content: Quote from: nctnico on May 22, 2014, 12:41:15 ambut VHDL is still written in ADA, and the most of things they have written are still valid.btw interesting points, after allyahoooooo i have emerged gnat-gcc on my co-nix (unix for windows, using gentoo-portage)and i can use ghdl (which is written in ADA, so to compile ghdl you need gnat-gcc)wonderful !!!i also emerged GTKware, so i am fine on Windows, and linux too =)

author: legacy
author_rank: Super Contributor
timestamp: May 22, 2014, 12:19:57 pm
content: Quote from: miguelvp on May 22, 2014, 12:52:08 amare you sure about this ? i am toying with a vhdl project about a tiny SoC composed by these modulesCode:+ top_level+ cpu+ ram+ bram_s3e+ rom_boot+ bram_s3e+ uart+ rx+ tx+ baud_gen+ timer+ port IO+ LCD+ LEDvery easy and tiny project, but Sigasi is telling me that i am out of 32Kbyte limitit may be cause the cpu module is very long about lines of code

author: miguelvp
author_rank: Super Contributor
timestamp: May 22, 2014, 02:37:13 pm
content: If you enable talkback when it comes with the dialog to put a license then next time it will open it.But it will bring a dialog about reaching the limit or something and to upgrade which you can dismiss and it opens a webpage for getting a license. But if you tick the dont show this again it wont open that web page every time you open a project.Works for me even on big projects. If you don't want to enable talkback then you are out of luck as far as I can tell.Edit: but I don't think I have a single file that will generate 32K by itself. Will try to lump a bunch off modules into a single file later.Edit2: so for large projects the standard edition goes into baseline mode. But it doesn't loose integration with Quartus II although it does with Xilinx, lucky me I use Quartus II.http://www.sigasi.com/sigasi-pro-vs-starter-editionI'm still trying to figure out what the talkback mode sends, maybe i'll do a packet capture.

author: NYEngineer
author_rank: Contributor
timestamp: May 22, 2014, 02:51:10 pm
content: Quote from: miguelvp on May 22, 2014, 12:52:08 amShame it doesn't support SystemVerilog and Verilog.

author: Bassman59
author_rank: Super Contributor
timestamp: May 22, 2014, 06:26:09 pm
content: Quote from: legacy on May 21, 2014, 07:33:04 pmA lot of us still use emacs and its excellent VHDL mode for source code editing.

author: Bassman59
author_rank: Super Contributor
timestamp: May 22, 2014, 06:35:12 pm
content: Quote from: rs20 on May 21, 2014, 01:05:22 amI think there's a disconnect here.If the right tool for the job is a microcontroller, then use a microcontroller and not an FPGA. If you want to drive an LCD or communicate over Ethernet or a UART or you want to run a PID loop or drive a motor, use a microcontroller. Can you do all of those things in an FPGA? Yes. LCDs and UARTs are trivial, and doing an Ethernet stack in VHDL would be punishing.If you need to interface to a high-speed image sensor or ADC then you will need to use an FPGA.That you can implement a processor in an FPGA is interesting, but as I noted, those of us who've actually done it usually go back to a system with a standalone processor connected to the FPGA.

author: alex.forencich
author_rank: Frequent Contributor
timestamp: May 22, 2014, 06:54:33 pm
content: Actually, an Ethernet stack on an FPGA is not that bad of an idea. I implemented a UDP/IP stack in verilog in about a week that can run at 1G line rate, and it is very useful for getting data into and out of an FPGA. The only annoying part was the dang UDP checksum in the header, necessitating some FIFOs.

author: miguelvp
author_rank: Super Contributor
timestamp: May 22, 2014, 07:26:06 pm
content: Quote from: alex.forencich on May 22, 2014, 06:54:33 pmCheck Microsoft Network Monitor and check their UPD parser implementation in npl (Network Monitor Parser Language) it's kind of strange get your head wrapped around that language as is kind of like in between C and HDL of some sort. But it would be easy to translate their udp.npl to VHDL.They use it to display the details on the packet capture and it's 529 lines of code. And that's just one protocol out of 385 they haveHardware layer Teredo anyone?Edit: Or better yet, hardware http server for your connected device

author: nctnico
author_rank: Super Contributor
timestamp: May 22, 2014, 11:08:46 pm
content: Quote from: Bassman59 on May 22, 2014, 06:35:12 pmI'm not quite sure you can speak for everyone and technology is advancing rapidly. The more you put into an FPGA the bigger the demand for a CPU which does simple housekeeping tasks. You can also save a lot of gates because software re-uses logic much more efficiently. Another problem is transferring data between a host processor and an FPGA fast. A parallel memory bus will eat lots of pins and PCB area. PCI express, ethernet (direct MAC connection) or USB have their own set of problems. In the past the amount of memory blocks in an (entry level) FPGA was limited so you'd have to think twice about using a memory block to store software but modern ones have plenty of memory inside. IMHO the biggest hurdle is to setup a development eco system which allows easy debugging and uploading new software. In the project I mentioned earlier I use Xmodem to upload a binary image of the software into the processor's memory.

author: miguelvp
author_rank: Super Contributor
timestamp: May 23, 2014, 01:12:15 am
content: Quote from: legacy on May 22, 2014, 12:19:57 pmSo after allowing the talkback under Window->Preferences->Sigasi->TalkbackIt allows you to open projects beyond the 32K. More info about what Talkback is:http://www.sigasi.com/sigasi-talkbackWhere you enable talkback it has a link into what is sent to the server too, nothing to scary it seems.Once you are past the 32K it goes into baseline mode like I mentioned on a previous post. More info about baseline vs free under 32K or Pro, here:http://www.sigasi.com/sigasi-pro-vs-starter-editionBut as you can see in this popup when I hover over the 100% in red it shows this:And one of the files in the project contributes to 55K by itself.But I can use all the baseline features.Edit: if I disable talkback then I get this every time I try to open a window.

author: rs20
author_rank: Super Contributor
timestamp: May 23, 2014, 01:32:05 am
content: Quote from: Bassman59 on May 22, 2014, 06:35:12 pmThere is indeed a disconnect, but the disconnect is from my original question as OP. I have a devkit (Spartan-3E starter) without a hard CPU anywhere onboard (AFAIK, a correction on this pointwouldbe useful), so a microcontroller just isn't an available choice. Chucking a soft-core on there may well halve my available gates, and be ridiculous as an end-use solution. But for a dev-kit, it's different. At least I'm not punishing myself by trying to write string manipulation in Verilog, and I can focus on real FPGA-appropriate stuff once I have a basic soft core going.

author: Scrts
author_rank: Frequent Contributor
timestamp: May 23, 2014, 08:01:42 am
content: Quote from: alex.forencich on May 22, 2014, 06:54:33 pmYou can write 0x0000 there (or 0xFFFF - I don't remember) and this will pass as a valid checksum. It's specified in RFC standards and some of the devices doesn't generate the checksum at all.

author: legacy
author_rank: Super Contributor
timestamp: May 23, 2014, 08:11:16 am
content: @miguelvpunderstood, thank you

author: alex.forencich
author_rank: Frequent Contributor
timestamp: May 23, 2014, 08:25:37 am
content: Quote from: Scrts on May 23, 2014, 08:01:42 amAll zeros is also an option, yes. I had to calculate the length anyway, which is also in the header, so I figured I might as well implement the checksum as well. The module I have will accept a framed data input of indeterminate length on an AXI stream bus (series of bytes with a tlast signal indicating the end of the frame), add a UDP header with the specified ports, fill in the length and checksum as computed from the data, and then send the result to the next module on another AXI stream interface. The only trick is that the data neds to be stored in a FIFO while the length and checksum are calculated, then the header can be attached via a second parallel header FIFO and the packet sent on its merry way.

author: Scrts
author_rank: Frequent Contributor
timestamp: May 23, 2014, 09:57:37 am
content: Quote from: alex.forencich on May 23, 2014, 08:25:37 amI did that on UDP reception using Altera