Length matching + impedance matching questions - Page 1
Forum section: electronics / general

author: VEGETA
author_rank: Super Contributor
timestamp: September 21, 2021, 06:47:18 am
content: Hello,I am working on a design using high speed stuff like HDMI 2.0 (6 Ghz) and stuff in the 600 MHz maximum range. ICs used (under NDA) have different requirements as follows:1- HDMI 2.0:to be routed in impedance of 100 Ohms differentially without vias. Of course, from IC to protection diodes from ESD, then to HDMI connector.I made those as straight and short as possible (still no actual routing though, but tests and placement). However, how to determine 100 Ohm differential impedance between each differential pair using kicad? all videos I saw choose something like 50 ohms for each trace but how to get 100 diff. impedance as required?2- other stuff like 600 MHz:they also need to be length matched but I saw the reference board (under NDA) routing some of them on top layer without vias, and others using vias to bottom layer in 6-layer configuration.3- DDR3 memory ICs, 4 of them. 1600 class speed total of 16Gbits.Main IC used which will have all 600 MHz signals is a big BGA, therefore it will have vias to fan out its balls...Here are my questions:1- how to determine 100 ohms diff. impedance? also with ensuring same track length.2- what effect do vias have in this? with respect to impedance and length matching. How to ensure all signals are routed good and the same despite some of them through vias and some others are not. this is important to know since I have to use them due to space constrains.3- what is the difference between normal impedance matching of diff pairs and diff. impedance?regards,

author: nctnico
author_rank: Super Contributor
timestamp: September 21, 2021, 11:04:32 am
content: How much is your time worth? If this is for work then I suggest to get Orcad PCB designer (at least professional level). This has tools that can largely automate doing the length matching and doing checks for length, phase, impedance and crosstalk. You'll not only need length matching but also phase matching. Likely your large BGA chip also needs compensation for length differences between the chip and the BGA balls.Ofcourse it is doable with Kicad but it will take a lot more extra time.Where it comes to determining the differential impedance: you'll need to use a field solver tool for this (included in the Orcad package). From my experience most of the software which uses formulas is way off.

author: VEGETA
author_rank: Super Contributor
timestamp: September 21, 2021, 11:12:04 am
content: Quote from: nctnico on September 21, 2021, 11:04:32 amIt is my own project which I hope I can sell it one day, kinda ambitious. I cannot use anything but KiCAD though.I am interested first to get answers to my questions, then learn how to do the required thing in KiCAD.I guess in KiCAD I can do length matching and impedance matching by using some website calculators as shown in phill's lab video, if it is reliable enough. but I need to understand how stuff work first, especially vias. vias will be a must in my design due to space constrains, so i need to know.thanks

author: nctnico
author_rank: Super Contributor
timestamp: September 21, 2021, 01:48:29 pm
content: Vias are just vias... the routing guidelines for the chip should tell you how many vias are allowed. What is also important is to have a return plane under your impedance matched traces. The best is to have ground but when you go from one plane to the other using a via, there also has to be a via nearby for the return current. If you use a power plane, then you'll need to place decoupling capacitors near the via to handle the return currents. For high speed designs it is recommended to suppress pads on unused layers. Another thing that is important is that the length of the vias should also be taken into account for length / phase matching. You likely need to match to a few tenths of a millimeter so the via length can not be ignored.But still I ask you to look at this design from a financial perspective: how much is a board spin going to cost you? Are there software tools available to test the quality of the DDR memory interface? For example: NXP has a special tool to verify memory interfaces on their SoCs. Alternatively you can run memtester under Linux (if the device runs Linux).The layer stackup and geometry are also important. You will want a so called HDI stackup which usually consists of a thin dielectric between top/bottom and ground planes. I recommend to go for a board with 0.09mm width / clearance on all layers for this design. This is doable for most PCB manufacturers but usually not available for pooling. From there you can determine the smallest via you can make. I usually add 5% to the size and go 1 drill size up to get extra margin. You'll likely need 10 layers: top, ground1, signal1, ground2, power1, power2, ground3, signal2, ground4, bottom. In my designs ground2, power1, power2 and ground3 are usually a mixed bag between signal routing, power and ground. You might be able to do without ground2 and ground3 to get an 8 layer design but it will complicate DDR3 routing because you have to use power as the return path.

author: VEGETA
author_rank: Super Contributor
timestamp: September 21, 2021, 02:23:36 pm
content: My approach is to have 4 layers (ref board had 6 but it contains many stuff I don't require). stack is top-gnd-gnd-bottom. most traces are on top layer of course while most caps\resistors may go to bottom layer except those required for top traces. not a strict rule anyway.power is done via a 20 watts recom ac-dc power module which delivers 5v, then I make 1.1v, 3.3v, 1.5v using TI switchers + 2.5v, 1.8v, and 1.0v using LDOs since they are rated so little. it is difficult to have a power plane for all of those anyway. most used is 1.1v for the main ASIC and also 1.5v for ram ics.as for ddr3 memory, no need for what you said. the ASIC requires certain type of ram ICs and i got it exactly as reference board and by the support of the manufacturer. all I need is just connecting the 4 ram ICs to the ASIC and write the SPI software to do the initialization.I was asking if I for example wanted to route 8 differential pairs @ 600MHz each... I started from the main ASIC on top layer after faning it out, then went through a bit to find I need vias... then I put vias... so far it is length matched and also impedance matched (still to find how to do it deferentially)...I assume once I put vias, I consider the vias to be a fresh start by themselves, meaning I need to do length matching stuff as if the vias are the true start of the signal. is this correct?Also, will the vias affect length matching? how about impedance matching? I keep reading that vias are a no-go in this... even in datasheets of my ICs to be used, they write it as not recommended but the reference board used them everywhere on these high speed signals.The design is a video scaler device which is capable of up to 4k @ 60 fps from various analog and digital sources. it has one main scaler ASIC (very big BGA) + 2 HDMI transmitters + 1 HDMI receiver (2 ports HDMI to one port 60-bits parallel). all under NDA and capable of 4k60 which is pretty rare till now.4k60 in this design uses a certain high speed digital video protocol which has 8 differential pairs (lanes) running at 600 mhz each. board size is very limited but will fit if I got vias properly done and so on... using Takachi PF13-4-19W enclosure since I cannot afford custom one.MCU is going to be RP2040 as raspberry pi pico running arduino bootloader and code which is easiest and can be directly upgradable via usb.

author: VEGETA
author_rank: Super Contributor
timestamp: September 21, 2021, 08:37:31 pm
content: Hello,I have tried length matching via kicad and the result in attached pics. pic 1 is the HDMI TX IC, length is 35mm from it to the ac coupling caps (0.1uF X7R), pic 2 is from the caps to the main ASIC which is the input or source of those signals. pic 3 is the fanout portion of the ASIC showing the signal sources. blue is top layer, green is bottom layer in a signal-gnd-gnd-signal configuration.notice that I never did any impedance matching stuff, just assumed trace is 0.1mm (I guess fab houses can do that) and clearance between 2 diff pairs is 0.2mm. I adjusted the board setup to make clearance small so that signals can pass through the BGA package. Kicad diff. pair routing tool is not always good since sometimes I need to manually route the signals a bit then it can take over.please inform me of any useful tip.best regards to all of u

author: nctnico
author_rank: Super Contributor
timestamp: September 21, 2021, 10:47:25 pm
content: The usual method is the create a via breakout structure on the BGA pins you can't reach from the outside. The way you are routing now likely ends up with not being able to reach the inner pads. Also keep room for phase matching. In the bottom picture: the signal from R32 is shorter than R31 so signal R32 will need extra length added to make the phase match. The amount of phase matching required should be in the routing guidelines of the chip.

author: VEGETA
author_rank: Super Contributor
timestamp: September 22, 2021, 05:22:16 am
content: Quote from: nctnico on September 21, 2021, 10:47:25 pmthey way I understand phase matching is that it is length matching between the 2 individual traces. Please correct me if I am wrong. after posting the pictures, I went back and made the phase matching of all these signals, they were adjusted from the upper side near the hdmi tx ic.most inner pads are ground and I can even route them using the ground plane if I needed.my concern is that is it good what I did in the pics? most importantly, will vias affect length matching and impedance matching? is my approach of length matching before vias then after vias independently ... is it correct?I am afraid that vias will ruine the effort but I saw them in the ref board which uses the same ICs... also, they are inevitable due to BGA and small space. routing some of them using layer 2 which is ground plane is doable since it will also have a very near and close ground plane under it which is layer 3.

author: Fronberry
author_rank: Contributor
timestamp: September 30, 2021, 09:15:53 pm
content: Quote from: VEGETA on September 22, 2021, 05:22:16 amIn general there are two categories of phase matching, 'static' and 'dynamic'. Static is mainly to do with overall time of flight/trace length, while dynamic is concerned with "local" matching of signal trace lengths, using fiber weave, serpentine routing, etc. to make sure the electrical signal matches between the pair as close as possible along the entire routing.As nctnico said, vias are vias, in terms of phase matching they behave similar to traces. Some things you would need to watch out for are (in no particular order):1. Via 'stubs', when you route a signal to an inner layer, you can end up with a "stub" of via that is unused at the end, that can cause unwanted signal integrity issues.2. Different velocity of signal between inner and outer layers (microstrip vs. stripline signals have different velocities due to the different surrounding media)3. Ground plane matching/return path. Like nctnico said, you need to make sure your signal has a complete and unbroken return path on the capacitively coupled GND (or in some cases power) plane. Not heeding this can cause some bad signal integrity issues.Since you said your board is just 4 layers this makes it easier, just make sure there is a solid ground plane coverage.In regards to your images:1. Are those meant to be AC caps in image 1? Usually those should be place as close as possible to the transmitter source.2. You should consider using smoother angles for high speed routing instead of 45 degree, but some suites don't let you do this.3. The vias under the BGA look good, but the other vias look awkwardly routed. You should try to make sure that your traces are entering the via perpendicular to the side, rather than at an angle. This is mainly for production reasons. Attached is what they normally look like.

author: VEGETA
author_rank: Super Contributor
timestamp: October 01, 2021, 11:23:27 am
content: I have ac coupling caps yes, and they are in a distance similar to that of reference board.However, should I make the entire distance equal? like from (ASIC to cap + from cap to TX IC) to be the same for all signals? right now from cap to TX IC is 45 mm but from ASIC to cap is either 13.8mm or 17.8mm depending on cap placement.Skew is 0mm well defined, no worries.Should I make the entire length is the same despite the cap placement?what if I want to take one diff pair and feed it into an IC which duplicates it, so that one duplicated pair goes to TX IC like previously... and the other one goes somewhere else... how is that gonna affect me and how to do it?

author: VEGETA
author_rank: Super Contributor
timestamp: October 01, 2021, 04:15:38 pm
content: I have re-worked it again and now everything should be perfect.Distance from ASIC to Cap (L1) = 20mm.Distance from Cap to TX IC (L2) = 47mm.^ this is for all signals for both TX ICs. All length matched now, and impedance matched to be 100 ohms differential impedance with at lease 0.5mm distance between each pair like mentioned in design guide itself. skew is matched as well.I have made re-arrangement for HDMI signals from TX ICs to TVS and from TVS diodes to HDMI connector. lengths are mentioned on image for HDMI stuff, I matched the lengths for all signals. ref board only matched them from TVS to connector only but from TVS to TX IC are short in general.Please see attached images.

author: Fronberry
author_rank: Contributor
timestamp: October 01, 2021, 04:28:43 pm
content: Matching the ASIC -> CAP + CAP -> IC is a good idea, and following the design guide inter-pair distance is good too.To my understanding, the reasoning behind placing the caps/TVS diodes close to the transmitter source is to keep the reflections within one data cycle. Since the components tend to create an area of impedance lower than the controlled impedance of the transmission line, this can create reflections. The reflection should be controlled to be within the baud rate of the signal, hence placing close to the transmitter.

author: VEGETA
author_rank: Super Contributor
timestamp: October 01, 2021, 06:36:45 pm
content: Quote from: Fronberry on October 01, 2021, 04:28:43 pmSo I did good? anything else I need to worry about?I don't understand what "reflections" are. Also, AFAIK about "phase" is the use of skew feature to match the 2 pairs together which I did here.what if I want to take 1 diff-pair into an IC (which is a duplicator), then feed one duplicated output pair to the TX IC as regular here... and the other one somewhere else unrelated. What should I do in terms of length matching and Z matching? actually I might need 2 diff pairs to be like this not just one.I assume since from cap to tx ic is 47 mm... I put the new duplicator IC on the road, and make sure the lengths from cap to new IC + from new IC to old TX IC = 47mm. How about that?speed of each pair can be 600 mhz up to 4 gbps if you wanna know.

author: nctnico
author_rank: Super Contributor
timestamp: October 01, 2021, 07:45:09 pm
content: I have a remark on the length tuning: it is better to have 3* width between the differential length tuning. Now the traces run way to close to eachother. Even closer than the distance to the counterpart making up the differential pair.

author: VEGETA
author_rank: Super Contributor
timestamp: October 01, 2021, 10:43:04 pm
content: Quote from: nctnico on October 01, 2021, 07:45:09 pmI didn't get what distance you mean.distance between the 2 traces of the pair is 0.2mm while their width is 0.1mm, this is from calculation software for impedance matching.if you mean the distance between the pairs themselves, meaning between one pair and the other, it is 0.5mm which is the recommended by manufacturer.please see attachment.

author: nctnico
author_rank: Super Contributor
timestamp: October 02, 2021, 10:00:22 pm
content: I mean the distance between the same signal should also be 3 times the width (or more).

author: Fronberry
author_rank: Contributor
timestamp: October 04, 2021, 05:19:48 am
content: Reflections happen any time there is an impedance discontinuity in the signal path. The passive components we add to the signal path often have impedances which are different (usually less) than the controlled impedance of the trace, so there will be some reflections. These reflections can travel back to the source and cause signal integrity issues. Hence the goal is to keep this reflection within one baud rate (essentially one "bit" of the datastream) so that it will minimize the risk of actually changing data.

author: VEGETA
author_rank: Super Contributor
timestamp: October 04, 2021, 07:21:42 am
content: Quote from: nctnico on October 02, 2021, 10:00:22 pmthe reference board used 0.2mm distance so I used it, also 0.1mm trace width. with these, and the dialect thickness of 0.122 mm it gives 100 differential resistance.Quotewhat are reflections to begin with?Also, how to know their amount on my current design? vias are necessary to use in this design, and even in the reference board so I cannot avoid them.

author: nctnico
author_rank: Super Contributor
timestamp: October 04, 2021, 08:55:53 am
content: Quote from: VEGETA on October 04, 2021, 07:21:42 amI'm not talking about the distance between the members of the pair, but one trace (same net distance)! Look carefully at your traces near the BGA!

author: VEGETA
author_rank: Super Contributor
timestamp: October 04, 2021, 09:55:08 am
content: oh you mean how close the blue traces to the BGA pins near it? it does look so close but I have to check the ref board since I am sure I did copy what they did and recommend.if this is the issue then I can just make the close trace a little bit away... gotta modify the trace length stuff too.

author: VEGETA
author_rank: Super Contributor
timestamp: October 05, 2021, 04:28:00 pm
content: I adjusted the routing from the BGA pins as seen in pictures, also made skew + length matched as before. Should be perfect now.I asked the manufacturer if I can break 2 transmission lines (2 pairs), each pair into an IC which duplicates it... so that one pair goes as default here and the other pair goes elsewhere unrelated (for making analog video output)... they suggested making this for all 8 pairs to avoid timing issues. it will be very pricey though and totally useless since I only need 2 pairs not all 8. I am trying to see if I can just getaway with just 2 ICs for 2 pairs.if that is the case, how can I route them in order to avoid any signal timing problem?

author: Fronberry
author_rank: Contributor
timestamp: October 07, 2021, 03:28:27 am
content: Quote from: VEGETA on October 04, 2021, 07:21:42 amThink about what a signal *really is*, a wave of energy traveling through electrons in a medium. Waves share a lot of physical properties between material/media/modes of transfer. Whether it's energy traveling through water (waves on an ocean). waves traveling through electrons (electricity), or waves traveling through air (sound).Now, think about what happens when a wave hits an area of uneven resistance to its motion. Like a wave of sound hitting a wall, it will reflect. Electricity/signals share this property. When you have an area of non-constant impedance, some of the energy will reflect backwards along the transmission line, causing all sorts of effects.It's hard to measure the exact values of reflection and distortion due to it, even with high end simulation. The most common approach is to follow design rules (such as the placement of AC caps) based on past experimentation.https://en.wikipedia.org/wiki/Signal_reflection

author: VEGETA
author_rank: Super Contributor
timestamp: October 07, 2021, 05:54:19 am
content: Quote from: Fronberry on October 07, 2021, 03:28:27 amThanks for explanation.So the summary is that I should place the caps as close to source IC as possible right? I think I have put them correctly, I've done as reference board which actually made and works. Caps are not far from source IC, they are physically about 15mm from it. traces are 20mm length matched.Do you know what should I do about the question in last post? meaning adding the distributor IC for 2 transmission lines (pairs) along the way after the caps to TX IC.this distributor IC requires its own AC coupling cap on its output too.

author: Fronberry
author_rank: Contributor
timestamp: October 07, 2021, 06:48:24 am
content: Is this the standard you are dealing with?https://www.thine.co.jp/files/user/img/corporate/VBOSTD-V1P52-0000_Abridged%2BEdition.pdfIt seems like you should refer to section 3.3, which doesn't seem to be available in my brief Google search...

author: VEGETA
author_rank: Super Contributor
timestamp: October 07, 2021, 08:12:53 am
content: Quote from: Fronberry on October 07, 2021, 06:48:24 amYes this is the one, how did you know about it? are you Skynet?It seems like section 3 is not in the document you linked.However, in the HDMI TX IC which takes VBO-HS inputs, it says this:it is recommended to separate at least 3 times the dielectric thickness between thesignal layer and the reference layer to any other adjacent signal or GND plane in order to reduce noiseinference and jitter. (or 25 mils is enough space in almost PCB stack)the dialect is 122um, so distance between any of the 2 signals of the pair vs any other signal is about 0.5mm in my layout which is very good as they recommend. About the pair itself, it is 100 ohms differential with 0.1mm width and 0.2mm distance between the pair traces exactly as the reference board.what do you think?

author: Fronberry
author_rank: Contributor
timestamp: October 08, 2021, 12:24:55 am
content: Not SkynetI just looked up "VBO HS TX" and that was the first thing that popped up.I think the question you asked earlier (about adding distributor ICs) has to do with the allowable inter-lane skew (Skew in this context is the difference in lengths between data lanes).In the document I linked, I saw that:Allowable inter-lane skew is defined as tRISK. Refer to section 3.3.However it seems like THine is keeping that one non-public. Have you talked with your vendor contact about this?