Open-source software for Verilog synthesis - Page 1
Forum section: electronics / general

author: Unixon
author_rank: Frequent Contributor
timestamp: September 13, 2013, 04:12:43 pm
content: Recently I was looking for an open-source toolchain to synthesize a low-level ASIC description (i.e. gate level or even switch level) from a Verilog source.A part of software was found athttp://opencircuitdesign.com/site, other tools are notably the VTR (Verilog-to-Routing)http://code.google.com/p/vtr-verilog-to-routing/and currently a part of it, the Odin-II projecthttp://code.google.com/p/odin-ii/,the GNU Electrichttp://www.gnu.org/software/electric/for the lowest silicon cell level, also the Yosis packagehttp://www.clifford.at/yosys/for high level synthesis.As far as I understand, altogether these tools should allow for complete ASIC development cycle.Well, using Odin-II I've managed to get to a netlist stage with respect to some generic FPGA and then a lot of questions came up.Does anybody have any experience with mentioned software?

author: clifford
author_rank: Regular Contributor
timestamp: September 13, 2013, 07:00:29 pm
content: Yes. I'm actually the Author of Yosys.The Yosys manual  contains an Appendix (atm it's App. E) titled "Evaluation of other OSS Verilog Synthesis Tools". I evaluated the synthesis feature of Icarus Verilog, VTR / Odin-II, HANA and VIS. I was not pleased. So I wrote my own tool.If you are interested in ASIC synthesis, Yosys will get you from Verilog to a gate level netlist. From there you can use tools like ABC  for gate-level optimization and technology mapping.Atm I'm working on extending the Yosys features for FPGA synthesis (including mapping of high-level cells like DSP cells and block RAM). I also have a half-finished projects in which I'm using Yosys to reverse-engineer a sequential logic netlist from the MOS6052 transistor netlists provided by the Visual6502 project.The aim on Yosys is to provide a framework for all kinds of logic synthesis and analysis work, by providing a (ever growing) set of basic algorithms and an entry point to utilize lower-level tools such as ABC.http://www.clifford.at/yosys/files/manual.pdfhttp://www.eecs.berkeley.edu/~alanmi/abc/

author: Unixon
author_rank: Frequent Contributor
timestamp: September 13, 2013, 07:47:07 pm
content: Great!I have some ideas for ASICs, but, prior to digging into depths of Verilog implementations of various circuits and running them on FPGAs, I want to step aside of this mainline and do few  things about synthesis.1) Learn how to synthesize an ASIC all the way down to GDS cells to understand this design flow well; Maybe, play around a bit with low-level simulations.2) Synthesize Verilog source into discrete elements / standard CMOS ICs as elementary cells, this should be similar to inventing a custom FPGA architecture;It should be possible to load the output of this stage into EDA tool like Eagle or KiCAD and then turn it into a real device on a PCB. There's not much practical sense in really doing a hardware like this, but this might be a great way for people learning stuff. I find fascinating the very idea that one can make a non-FPGA prototype of an ASIC with just the same approach and tools as a real chip.3) Take the design flow developed in (1) and (2) and go back to implementing ideas, equipped with tools for producing a virtual IC or even a real prototype (not FPGA based);Currently I'm stuck at the stage of producing gate-level description without complex blocks like adders, multiplexers, LUTs etc., just with bare gates.

author: clifford
author_rank: Regular Contributor
timestamp: September 13, 2013, 10:00:19 pm
content: Let me address your last point first: Producing a gate-level netlist using yosys is really simple. A step-by-step howto for exactly this basic application is included in the README file:https://github.com/cliffordwolf/yosys/blob/master/READMEThe paper  I wrote for the Austrochip conference contains examples for gate-level synthesis, fpga synthesis (luts) and coarse-grain synthesis (adders, etc.). I will put it online on the yosys website after the conference (mid. october).Regarding 2) and 3): There is a lot in yosys that can help you there. Yosys is design with so-called coarse-grain synthesis in mind. (Coarse-grain synthesis is synthesis for architectures with coarse-grain cells like addders or even more complex cells such as ALUs.) I co-authored a book chapter  on using yosys not only for synthesis for coarse grain architectures but also using yosys in designing such architectures by analyzing example designs. It is to appear in fall and I will also put a copy of this book chapter on the website when it comes out.Regarding 1): Yosys purely operates on a netlist level and does not do physical layout. I think this is good, because layout synthesis requires a fairly different set of algorithms and data structures and therefore is best done in a separate tool. There are some open source tools that can do layout (gnu electric, alliance), but I have no experience whatsoever with this tools and do not know if they can do layout synthesis and if so if they are any good at it. Clifford Wolf, Johann Glaser. Yosys - A Free Verilog Synthesis Suite. Austrochip 2013. to appear. Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. In Jan Haase, editor, Advances in Models, Methods, and Tools for Complex Chip Design — Selected contributions from FDL’12. Springer, 2013. to appear.

author: Unixon
author_rank: Frequent Contributor
timestamp: September 13, 2013, 11:07:53 pm
content: Quote from: clifford on September 13, 2013, 10:00:19 pmYes, this is exactly what I tried first. After "write_verilog synth.v" I end up with another verilog source, writing ilang doesn't really help either and I still didn't see anything in intersynth format, that thing seem to dislike trivial verilog examples. Flattening a design looks promising, only D flip-flops are left out of complex components. But how do I convert this to any usable form? Odin-II at least gave me BLIF file which I was able to convert further into SPICE netlist with some success. I can't figure out what should I do with Yosys output.

author: clifford
author_rank: Regular Contributor
timestamp: September 14, 2013, 07:29:36 am
content: Quote from: Unixon on September 13, 2013, 11:07:53 pmwrite_verilog gives you a verilog netlist. Thats quite different from a real verilog source as it limits itself to only basic constructs for instanciating cells. Many low-level tools are capable of reading verilog netlists. Some tools don't like it when verilog netlists contain attributes. In this cases you should use the -noattr option to write_verilog. If you don't perform technology mapping, write_verilog per default outputs short verilog expressions for all internal cell types. This is useful if you want to use Yosys as a pre-processor for dumb tools like Odin-II that don't understand real Verilog buit only a trivial subset of Verilog. Use the -noexpr option to write_verilog if you also want Verilog netlists for internal cell types.write_edif writes EDIF netlist. This is probably the most popular netlist format in the industry. Unfortunately it is also the one with the most "flavors". So it is likely that when you want to use EDIF, you might need to add an option to the write_edif command to support the exact flavor of edif that you need. At the moment write_edif writes edif files that are excepted by the Xilinx place&route commands.Adding backend commands to yosys is pretty easy. Let me know what you need and if it's not too much trouble I'll add it. (I can add SPICE if you want, although it is a very unusual output format for a synthesis tool. But I'm all for adding exotic features to yosys. If you have an example of what you think the output should look like, that would be pretty helpful.)

author: Unixon
author_rank: Frequent Contributor
timestamp: September 14, 2013, 08:27:08 am
content: EDIF looks interesting, it's effectively from a LISP world and I at least can read and understand what's inside. Good, but questions still remain.1) How Yosys is intended to communicate with the rest of toolchain? If one is about to synthesize an ASIC and starts processing his Verilog source with Yosys, what kind of Yosys output should be transferred to what next tool?2) I would be happy with any output similar to what is written to EDIF that I can: (a) easily parse and convert into schematic for an EDA; (b) use as an input for place&route tools.Also, where can I get cell library file and Liberty format specs? (anywhere buthttp://www.opensourceliberty.org/, they ask for personal information).

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 11:08:55 am
content: Quote from: Unixon on September 13, 2013, 11:07:53 pmStupid question: why would you want to run your verilog code through spice? Doing mixed signal or something? For just regular logic simulation you'd be better of using modelsim etc...

author: clifford
author_rank: Regular Contributor
timestamp: September 14, 2013, 11:51:57 am
content: Quote from: Unixon on September 14, 2013, 08:27:08 amIn most cases this will either be EDIF of a Verilog netlist, whatever the next tool does understand. In general I would prefer Verilog netlists as EDIF has the "multiple flavors" problem.Many free tool use BLIF as exchange format. But BLIF is usually used as exchange format for logic-level netlists (BLIF is basically a netlist of LUTs) than cell-level netlists. At the moment there is no BLIF support in Yosys. BLIF has also the "multiple flavors" problem - but not as much as EDIF.Quote from: Unixon on September 14, 2013, 08:27:08 amIf you have a good suggestion for a really easy to parse netlist format to be used as interchange format I'd be happy to implement a write_* command for it in yosys. Just write a formal definition so we can discuss it.Quote from: Unixon on September 14, 2013, 08:27:08 amyes. also, the standards text is not written very well imo. Keep reading for a working example that also includes a simple liberty file:I've now implemented a simple SPICE backend (write_spice) that can be used to create SPICE netlists from Yosys (check out the latest sources from github). I've also included a simple example in the techlibs/cmos/ directory in the Yosys source tree. It's a simple 3-bit up-counter with synchronous reset and enable. Here is the Verilog:module counter (clk, rst, en, count);input clk, rst, en;output reg [2:0] count;always @(posedge clk)if (rst)count <= 3'd0;else if (en)count <= count + 3'd1;endmoduleI synthesized it using the liberty file quoted above and simulated it with ngspice. A screenshot of the simulation result is attached.This whole example (Verilog Sources, Liberty File, Synthesis Script, Spice Cell Library, etc.) can now be found in the techlibs/cmos/ directory in the Yosys source tree.https://github.com/cliffordwolf/yosys/tree/master/techlibs/cmos/

author: Unixon
author_rank: Frequent Contributor
timestamp: September 14, 2013, 01:12:36 pm
content: Quote from: mrflibble on September 14, 2013, 11:08:55 amNo, I don't particularly want to run Verilog code through SPICE (interesting topic in its own rights), I just was looking for any possibilities to convert Verilog source to something tangible. Odin-II and BLIF is just what I found in the process of figuring out what each tool can do.

author: Unixon
author_rank: Frequent Contributor
timestamp: September 14, 2013, 02:53:19 pm
content: Quote from: clifford on September 14, 2013, 11:51:57 amOh, this is getting very interesting. I hoped to use one of standard formats, but I think I can come up with something better for one of things I want to experiment with. How about an XML-based format? I can write a DTD for that.Also, I pulled changes from github. It's all OK but one thing. My installation of Yosys doesn't have a yosys-abc binary and fails to execute abc command. I have the ABC itself inside VTR but this is not what Yosys seem to want from me. I guess I haven't compiled something.

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 03:01:10 pm
content: Quote from: Unixon on September 14, 2013, 02:53:19 pmPleeeeaaaaase resist the diabolical urge to re-invent the wheel.For better or for worse, I suspect you'll have better luck getting tools like this adopted when you use an actual industry standard.

author: clifford
author_rank: Regular Contributor
timestamp: September 14, 2013, 03:33:11 pm
content: Quote from: Unixon on September 14, 2013, 02:53:19 pmOh no no no.1.) The container is not an issue. You could simple write a S-expression to XML converter and convert EDIF to XML. The question is how you organize the data _within_ the container. For an "as easy to process as possible" format I would expect something line-based with whitespace separated tokens or maybe JSON.2.) It must provide a unique advantage. I understood (but maybe I understood wrong) that you wanted something that is easy to parse and process and that you therefore are unhappy with the existing options (Verilog Netlists, ILANG, EDIF and now SPICE).You should look at this formats and understand why they have a certain complexity and if you can come up with something that is significantly less complex while still providing all the relevant functionality, _then_ it is an interesting option.Otherwise its just yet another format and benefits none.Quote from: Unixon on September 14, 2013, 02:53:19 pmYou also need to run "make abc" and "make install-abc" in the yosys source tree.

author: mrflibble
author_rank: Super Contributor
timestamp: September 14, 2013, 03:36:54 pm
content: Quote from: clifford on September 14, 2013, 03:33:11 pmPhew, common sense shall prevail!

author: Unixon
author_rank: Frequent Contributor
timestamp: September 14, 2013, 04:25:21 pm
content: Quote from: clifford on September 14, 2013, 03:33:11 pmI don't insist on inventing a new format, indeed, I think it would be better if it is something already being used in practice.My suggestion of XML was due to good impression of working with Eagle CAD XML-based format. This is not about ASICs at all, I just liked the approach.Quote from: clifford on September 14, 2013, 03:33:11 pmOK, let's look at what is already there.1) Verilog Netlists : it's still a valid Verilog source may contain any of valid Verilog language elements, not very trivial syntax, no cell definitions; Maybe this is OK, but I need to see how it looks for more complex input.2) ILANG : clear syntax, contains additional information for entities; Same as above, but I like this more for regular structure.3) EDIF : complex syntax, language-specific elements; I don't have a library like TinyXML to deal with LISP structures.4) SPICE : easy syntax, but it doesn't contain cell descriptions, has implicit assignments of wires to cells' ports; Simple, good, but lacks some info.I think ILANG wins here, maybe I should work directly with RTLIL by writing a backend for Yosys.

author: clifford
author_rank: Regular Contributor
timestamp: September 14, 2013, 09:19:59 pm
content: Quote from: Unixon on September 14, 2013, 04:25:21 pmYes. This would definitely be the best thing to do, if you are willing to make yourself familiar with the RTLIL API. Let me know if you have any questions or have feedback regarding the documentation. (The Yosys Manual is a good starting point, but as you know about RTLIL I assume you have already found it.)

author: Unixon
author_rank: Frequent Contributor
timestamp: September 14, 2013, 09:42:08 pm
content: By the way, does ILANG cover all of contents of RTLIL structures ?Would you consider feasible implementing a binary image format for RTLIL for fast data exchange between RTLIL implementations without generating and parsing ILANG ?

author: clifford
author_rank: Regular Contributor
timestamp: September 15, 2013, 09:00:38 am
content: Quote from: Unixon on September 14, 2013, 09:42:08 pmOnly if you find an actual application where ILANG parsing time is an issue. Parsing a file format like ILANG is an O(n) problem. Building the RTLIL data structures is an O(n*log(n)) problem because everything is indexed with binary trees (std::map). And many synthesis algorithms are O(n^k) with k > 1."Premature optimization is the root of all evil." -- Don Knuth

author: Unixon
author_rank: Frequent Contributor
timestamp: September 15, 2013, 10:52:34 am
content: It's not about time to parse ILANG, it's about time for me to implement a parser for ILANG.I know it is already there in Yosys as a frontend, but, well... Flex, Bison, STL and C++11-only features is not what I really want in my code.Anyway, great thanks for developing Yosys and for quick and active response.Actually I was thinking about my next steps in the direction of processing netlists from Yosys and found that reading netlists is a tiny fraction of this work.So, any integration with Yosys will be after I deal with tools for further processing.

author: clifford
author_rank: Regular Contributor
timestamp: September 15, 2013, 11:43:51 am
content: Quote from: Unixon on September 15, 2013, 10:52:34 amYou think a parser for a binary format with the same flexibility will be faster to implement?However, I've now also added a BLIF backend (see latest master on github), and I've added some options to create simpler variations of BLIF for cases where one wants to process the output with a custom tool (just don't call the resulting file *.blif then). I think you will like the format generated with 'write_blif -subckt -conn -impltf'.

author: Unixon
author_rank: Frequent Contributor
timestamp: September 16, 2013, 05:16:58 pm
content: Quote from: clifford on September 15, 2013, 11:43:51 amI wouldn't call it a parsing... The following is not related to previous discussion in any way.For many purposes I use one simple binary format: a sequence of records (uint32 type_class, uint32 type_size, uint32 data_count, byte data) preceded by uint64 record_count. Here, type_class is a constant ["SINT", "UINT", "REAL", "CHAR", "BOOL"] which is perfectly human-readable even in the rest of binary garbage, type_size is the size of one data element in bytes. A hierarchy of classes that wants to have binary imaging implements reading and writing methods in every class that just cycles through fields and pushes/pulls them to/from a binary stream with type checking.Quote from: clifford on September 15, 2013, 11:43:51 amI'm speechless... This is truly incredible how fast you are.

author: clifford
author_rank: Regular Contributor
timestamp: September 17, 2013, 04:48:34 am
content: Quote from: Unixon on September 16, 2013, 05:16:58 pmYou said its unrelated, but nevertheless: This is pretty much how the ILANG format works, just not with binary but with text:Each ILANG statement is a line with white space separated tokens. So first implement a read_line() function that reads a line, splits at whitespaces and returns a list of strings.Now you implement a top-level parse() function that reads lines. Whey they start with 'module' they pass it to a parse_module() function, otherwise it produces an errors. The parse_module() function now knows what function to call for "wire", "cell" or "process" statements and so on. When parse_module() function reads an "end" statement it returns.Attributes are best parsed using a little hack: parse attributes directly in read_line() and push them to a container. whenever a function is called that creates an object that can have attributes attached (such as parse_module()), copy all attributes from the container to the new object and reset the container.PS: You might like google protocol buffers:https://developers.google.com/protocol-buffers/

author: Unixon
author_rank: Frequent Contributor
timestamp: September 21, 2013, 08:23:01 am
content: Quote from: clifford on September 17, 2013, 04:48:34 amYes, I also found GPB some time ago. The idea sounds interesting, but the code of GPB is huge and it's 3rd party code copyrighted to Google.I had a somewhat similar project in this area, but it has been left behind in favor of other urgent projects. Maybe I'll pick it up again later.So, back to the topic of this thread... There are two(three) major directions of further movement:1) Producing PCB-based device by converting Yosys output to EDA project. Here I see the the road going two ways: (a) implement placement and routing for components' symbols in schematic and packages' footprints in PCB layout. This placement and routing information is not in netlist as it is excessive for a netlist and should be generated somehow. I thing it is somewhat similar to visualizing graphs. As far as I remember, BLIFexplorer from VTR does something like that. I'm working with Eagle CAD and have a C++ library for managing contents Eagle files, the plan is to use it to generate valid schematic and PCB layout from Yosys netlists. (b) draw an entirely new cell library which will have packaged ICs/transistors/etc instead of what is usually put in silicon and make TimberWolf and Qrouter do the job, then convert this output back to EDA project with already placed and routed device layout.2) Producing virtual ASIC at transistor level. Qflow suggests to continue with TimberWolf for placement, Qroute for routing and Magic for layout. I also had a thought to make use of GNU Electric, but I have no clear idea where and how it may connect to the design flow. At the current moment I'm trying to build TimberWolf, but it doesn't compile entirely, so I can't use it yet.3) Going back to CPLDs/FPGAs. That's practical, but fairly boring. I'll be there anyway so I don't want to rush to this point.First one is most interesting to me as I see nobody has done it before.

author: clifford
author_rank: Regular Contributor
timestamp: October 11, 2013, 08:47:21 pm
content: I've now uploaded the paper for Austrochip 2013 to the Yosys website:http://www.clifford.at/yosys/documentation.htmlClifford Wolf, Johann Glaser. Yosys - A Free Verilog Synthesis Suite. In Proceedings of Austrochip 2013.My co-author (who did the presentation) also made a screencast for the presentation. I've uploaded the plain screencast (without audio) to my Youtube channel:I'm not sure how useful the screencast is without additional explanations though. Maybe we will make a voice-over version later.

author: tim
author_rank: Newbie
timestamp: October 15, 2013, 03:14:31 pm
content: I'm about a month late to this discussion, but I'm Tim Edwards, the author and maintainer of the tools on the Open Circuit Design website. I have been working for the past several months on an open source toolchain to synthesize to an ASIC target. I started with VIS/SIS, which was so limited as to be basically useless, and then moved up to Odin-II. Odin-II (with ABC) is considerably more flexible than the VIS/SIS combination, but I had to write extensive amounts of pre-processing code to get it to compile anything off the Open Cores site, and last week I sort of admitted defeat for compiling the OpenMSP430 microcontroller. So I am currently looking into yosys as a replacement/alternative for Odin-II in the synthesis flow.

author: tim
author_rank: Newbie
timestamp: October 15, 2013, 04:00:35 pm
content: Oh, and by the way, yes, TimberWolf can be a pain to compile. I'd rewrite the whole installation process if the thing weren't such a bloated beast. If you have specific problems with the TimberWolf compile, just tell me what they are and I can probably get you through the compile stage.

author: Unixon
author_rank: Frequent Contributor
timestamp: January 09, 2014, 10:42:14 pm
content: Thanks a lot,Clifford. I've been away from this forum for quite a long time due to total mess at day job and other activities usually occurring at the end of year. Currently I'm working on few microcontroller projects and specific tools for managing gerbers and EDA files, but I think I still can advance in small steps with respect to declared plans.Tim, thank you for support, I will definitely need your help in dealing with these tools. I will see what is exactly wrong with that build as soon as I get near my workstation, probably next week.

author: Unixon
author_rank: Frequent Contributor
timestamp: January 09, 2014, 11:01:26 pm
content: Quickly browsed through Clifford's papers about Yosys. Brilliant. This looks like something I've been missing so much while trying to wrap my head around Yosys workflow.