High frequency, High Impedance, Unity gain buffer - Page 1
Forum section: electronics / projects

author: moffy
author_rank: Super Contributor
timestamp: November 29, 2016, 11:33:49 pm
content: I have just finished my design for a High bandwidth (750MHz), High input impedance (0.25pf), DC accurate buffer. I would be interested in any comments.It is a composite buffer with an op amp handling the DC accuracy. I haven't built it yet, but would like to in the near future. The only results I have are from LTSpice simulations, but they look good.

author: moffy
author_rank: Super Contributor
timestamp: November 30, 2016, 01:12:46 am
content: Silly me, I can get rid of Q4 by connecting R17 to the base of Q3, and swapping the 10M/100nF inputs into the op amp U3a.

author: David Hess
author_rank: Super Contributor
timestamp: November 30, 2016, 05:47:14 am
content: Your design does not have very much input protection. Active probe designs commonly either include an attenuator before the FET (Tektronix P6202A) which also increases the input range, AC couple the FET input with a separate low frequency DC path (Tektronix P6201), or both.If you use a x5 attenuator before the FET, then double terminating the output will yield a convenient x10 attenuation factor. Otherwise double termination divides the output by 2 unless you include a fast x2 gain stage which is not easy.One problem with using DC correction is that it makes overload recovery even slower because of integrator windup. Dual JFET designs and dual path designs have an advantage here.

author: moffy
author_rank: Super Contributor
timestamp: November 30, 2016, 11:01:03 pm
content: David Hess, thank you for your comments!1.) With regard to input protection I deliberately haven't put it there as it will compromise the input impedance, unless of course the diodes are bootstrapped. It's for the user and application to provide any protection deemed necessary. I look at this as just a building block which can be adapted to applications.2.) Yes if the integrator saturates there will be a recovery time, but I find that acceptable.3.) "Dual path designs..." I assume you mean separate AC/DC paths that you then add together? They can be quite tricky to get a flat response over the whole frequency range. My latest revision is flat to within 0.1db to 185MHz and BW of 950MHz, but of course that is only SPICE. If you mean something different I would like to hear it.Thanks again.

author: Marco
author_rank: Super Contributor
timestamp: December 01, 2016, 08:04:35 am
content: Quote from: moffy on November 30, 2016, 11:01:03 pmAdding some series resistance with a bypass capacitor won't harm it much, the built in BF998 diodes could suffice for being able to probe mains without blowing it up.

author: David Hess
author_rank: Super Contributor
timestamp: December 01, 2016, 08:20:54 am
content: Quote from: moffy on November 30, 2016, 11:01:03 pmNeither of the examples I mentioned use protection diodes (except for the junction of the JFET which only protects in one direction) for the reason you identify; they add capacitance. The P6201 uses a 100pF coupling capacitor to isolate the FET gate. The P6202A has a x5 compensated attenuator with an 8 megohm series resistor on its input.QuoteThe P6201 is a complex dual path design with separate AC and DC paths but the compensation needed is pretty simple requiring only two adjustments; the gain and frequency break point have to be matched. The 2235 series of oscilloscopes shows an alternative where the FET path is DC but the signal to the integrator is attenuated (because of the extra input protection and to maintain a flat 1M input) so it has a gain and compensation adjustment. Yours relies on the matching of the 0.16 Hz time constants leading to the integrator.I had not noticed before but on yours, the input impedance has an extra pole-zero pair because of the tap going to the integrator. Why did you include R5? That neatly explains why oscilloscopes and probes do not do it that way but it would not matter in an ATE (automated test equipment) type of application which is sort of what Jim Williams had in mind.

author: moffy
author_rank: Super Contributor
timestamp: December 01, 2016, 11:06:29 pm
content: Quote from: David Hess on December 01, 2016, 08:20:54 amIt's a little bit more complicated than that, as the time constant of the integrator has to have a fixed value based upon the 10M/0.1u low pass filter. To the -ve side it's kind of a bootstrapped integrator(the 1k), to the other side the + it's a psuedo differentiator, it's not symmetrical. Trust Jim Williams to have levels of subtlety in a seemingly simple design.Quote from: David Hess on December 01, 2016, 08:20:54 amYou are correct, but again for my purpose I don't mind that extra pole/zero. R5 a guess is my one concession to input protection, making sure the gate doesn't float if there is no input signal, but as you suggest it is not necessary.I will have to look into the designs that you have mentioned, I am sure that I will learn something. Tektronix scope designs are the epitomy of good engineering.Thank you again for your comments.

author: moffy
author_rank: Super Contributor
timestamp: December 01, 2016, 11:08:57 pm
content: Quote from: Marco on December 01, 2016, 08:04:35 amYou are quite correct, it is an excellent suggestion and I will incorporate it into my design. Thank you.