STM8S103 trigger standard mode, reset mode , gated mode , request help - Page 1
Forum section: electronics / general

author: Sajeev
author_rank: Contributor
timestamp: August 07, 2024, 03:48:50 am
content: Dear Forum members,I am trying to test the trigger standard mode , trigger reset mode and gated trigger mode on stm8S103 TSSOP20 version. I initialized the registers as described in RM0016 manual . The Timer1 counter keeps on counting on its own and doesnt wait for the trigger to happen on TI1 or TI2 inputs (PC6 & PC7). The AFRO0 option byte was enabled to make timer1 chanel 1 and chanel 2 available. Request help form informed members on how to realise the trigger modes. Please find below the code I used. I have used the TIMER1 _ chanel2 as input and timer1 overflow interrupt to toggle an led on PD4. The led is supposed to toggle when the PC7 goes high but I see the LED toggles when power is applied to the chip even when PC7 is supplied ground.RegardsSajeevmain_loop.lmov CLK_CKDIVR,#$00 ; cpu clock no divisor = 16mhzbset PD_DDR,#4 ; set PD4 as outputbset PD_CR1,#4 ; set PD4 as pushpulltimer_setupbres TIM1_CR1,#0 ; disable timerbres TIM1_SR1,#0 ; clear update interrupt flagmov TIM1_SMCR,#$66 ; TS = 110 and SMS = 110 , TI2 input , trigger standard modebset TIM1_IER,#0 ; enable update interruptbset TIM1_CR1,#0 ; enable timerRIMwaitjra waitinterrupt TIM1_ISRTIM1_ISRbres TIM1_SR1,#0 ; clear interrupt flagbcpl PD_ODR,#4 ;toggle led piniret

author: rhodges
author_rank: Frequent Contributor
timestamp: August 07, 2024, 01:43:49 pm
content: It looks like you want to use "Trigger Gated Mode". Did you read that part of 17.4.5 and figure 51? The text says to set SMS=101 (and TS=101 for T1).Go to 17.7.3 for the TIM1_SMCR register.Quote

author: Sajeev
author_rank: Contributor
timestamp: August 07, 2024, 03:01:20 pm
content: Dear Sir,Thankyou for the reply. The above code is actually for testing trigger standard mode. The registers are furnished based on the steps provided in the RM0016 manual section 17.4.5 page 155/467. Unfortunately I couldn't make it work. On connecting logic analyzer on PD4 it shows a 50% dutywith 4ms width without triggering TI2. I was expecting no toggling on PD4 till a high edge is detected on PC7 (TI2). Am i not doing it right?RegardsSajeevTrigger standard modeThe counter can start in response to an event on a selected input.ProcedureUse the following procedure to start the up-counter in response, for example, to a risingedge on the TI2 input:1.Configure channel 2 to detect rising edges on TI2. As no filter is required in this example, configure an input filter duration of 0 (IC2F = 0000). The capture prescaler is not used for triggering and does not need to be configured. The CC2S bits select the input capture source and do not need to be configured either. Write CC2P = 0 in the TIM1_CCER1 register to select rising edge polarity.2. Configure the timer in trigger mode by writing SMS = 110 in the TIM1_SMCR register. Select TI2 as the input source by writing TS = 110 in the TIM1_SMCR register.When a rising edge occurs on TI2, the counter starts counting on the internal clock and theTIF flag is set.The delay between the rising edge on TI2 and the actual reset of the counter is due to theresynchronization circuit on TI2 input.

author: rhodges
author_rank: Frequent Contributor
timestamp: August 07, 2024, 04:02:29 pm
content: C6 and C7 are pins for channels 1 and 2, not clock triggers. The only clock trigger I see is B3.

author: Sajeev
author_rank: Contributor
timestamp: August 07, 2024, 07:22:58 pm
content: Dear Sir,Thanks for the reply. Finally I got it working. I didnt follow the example in the RM0016 properly, thats why it didnt work. In the example ,its not mentioned to enable the timer1 by writing 0 bit of TIM1_CR1. I was enabling the timer1 in my code and it started counting directly without the need of a trigger on TI2. I removed that line and found that the PD4 doesnt toggle on power up. It starts toggling only when 5v is applied to TI2 (PC7). It seems that CEN bit of TIM1_CR1 need to set only in reset-trigger mode and gated-trigger mode. Please find below the corrected version of the code I used. Thanks once again for the advice.Thanks & RegardsSajeevmain_loop.lmov CLK_CKDIVR,#$00 ; cpu clock no divisor = 16mhzgpio_setup:bset PD_DDR,#4 ; set PD4 as outputbset PD_CR1,#4 ; set PD4 as pushpull;bset PC_CR1,#7 ; enable input and pull up, uncomment if falling edge neededtimer_setup:bres TIM1_CR1,#0 ; disable timerbres TIM1_SR1,#6 ; clear trigger interrupt flagmov TIM1_SMCR,#$66 ; TS = 110 and SMS = 110 , TI2 input , trigger standard mode;bset TIM1_CCER1,#5 ; TI2 polarity falling edge , uncomment if falling edge neededbset TIM1_IER,#0 ; enable update interruptbset TIM1_IER,#6 ; enable trigger interruptRIMwait:jp waitinterrupt TIM1_ISRTIM1_ISRbres TIM1_SR1,#0 ; clear interrupt flagbres TIM1_SR1,#6 ; clear interrupt flagbcpl PD_ODR,#4 ; each update interrupt at 4.09ms after counting 65535iretinterrupt NonHandledInterruptNonHandledInterrupt.liretsegment 'vectit'dc.l {$82000000+main} ; resetdc.l {$82000000+NonHandledInterrupt} ; trapdc.l {$82000000+NonHandledInterrupt} ; irq0dc.l {$82000000+NonHandledInterrupt} ; irq1dc.l {$82000000+NonHandledInterrupt} ; irq2dc.l {$82000000+NonHandledInterrupt} ; irq3dc.l {$82000000+NonHandledInterrupt} ; irq4dc.l {$82000000+NonHandledInterrupt} ; irq5dc.l {$82000000+NonHandledInterrupt} ; irq6dc.l {$82000000+NonHandledInterrupt} ; irq7dc.l {$82000000+NonHandledInterrupt} ; irq8dc.l {$82000000+NonHandledInterrupt} ; irq9dc.l {$82000000+NonHandledInterrupt} ; irq10dc.l {$82000000+TIM1_ISR} ; irq11dc.l {$82000000+NonHandledInterrupt} ; irq12dc.l {$82000000+NonHandledInterrupt} ; irq13dc.l {$82000000+NonHandledInterrupt} ; irq14dc.l {$82000000+NonHandledInterrupt} ; irq15dc.l {$82000000+NonHandledInterrupt} ; irq16dc.l {$82000000+NonHandledInterrupt} ; irq17dc.l {$82000000+NonHandledInterrupt} ; irq18dc.l {$82000000+NonHandledInterrupt} ; irq19dc.l {$82000000+NonHandledInterrupt} ; irq20dc.l {$82000000+NonHandledInterrupt} ; irq21dc.l {$82000000+NonHandledInterrupt} ; irq22dc.l {$82000000+NonHandledInterrupt} ; irq23dc.l {$82000000+NonHandledInterrupt} ; irq24dc.l {$82000000+NonHandledInterrupt} ; irq25dc.l {$82000000+NonHandledInterrupt} ; irq26dc.l {$82000000+NonHandledInterrupt} ; irq27dc.l {$82000000+NonHandledInterrupt} ; irq28dc.l {$82000000+NonHandledInterrupt} ; irq29end