Altera Quartus - please help a novice to make timing simulations - Page 1
Forum section: electronics / general

author: Yansi
author_rank: Super Contributor
timestamp: October 30, 2015, 04:25:50 pm
content: Hello,let me first say a little bit of my backround...I have very shallow knowledge and experience with VHDL and PLD stuff. I'd like to learn more about CPLDs (and maybe FPGAs). But I have some trouble, which I cannot overcome now, with the Quartus evil.Some time ago (year or so), I have made a few simple projects on Xilinx PLDs, simple combinatorial logic and some Moore FSMs. I have done that in some older version of Xilinx ISE, which was available for me at that time. In the Xilinx ISE, I was able to make logic and timing simulation very easily. Just created the VHDL testbench file, run the simulator, simulated. Piece of cake.But for whatever reason, I have chosen to continue my projects with Altera devices (I like them, at least for the good availability for me and also the lower pricepoint). So I have downloaded Altera Quartus II (64bit version 13.0 SP1 I think). It works fine, the enviroment looks friendly nice and clean. I am able to compile some VHDL code, programm it into a CPLD and it works. But when it goes to simulations... F***K. I can't simply get it working.I have found, that I need Altera Modelsim. So fine, downloaded that and successfully installed. (There was a bit of magic with setting the correct path to the tool, but finaly it seems it is fine now).The question:Can somebody please explain me, how to do simulation in Quartus? I'd like to make a VHDL test bench and the simulate the timing of the result.Yes, there is a fuckton of step-by instruction manuals how to do that, but none worked. Most of them also involve writing some scripts into some evil command line, involve tens of things to click on there or elsewhere. Crazy rubbish. Am I doing it wrong, or the Quartus evil really cannot make life simple, as was in Xilinx ISE? Just a few clicks and simulation was going...Can you please point me to some instructable, how to make (timing) simulations in Quartus "the easy way"? (if such way exists) Without the need for preparing ton of scripts, writing tens of commands each time you make a new project? Or really is the Quartus user required to have at least page long step-by-step manual where to click, what command to write in and so to be able to simulate a trivial design?Maybe I am missing some basic facts, but I am really stuck now. I have succesfully forced the ModelSim to produce some output once... but that was not timing, only logic function sim... and only once.Thank you for any helpYan

author: John_ITIC
author_rank: Frequent Contributor
timestamp: October 30, 2015, 09:41:45 pm
content: Instructable? No, but I can refer you to some very good books of how to get started with Altera CPLDs, FPGAs and simulation in Modelsim:http://www.amazon.com/Rapid-Prototyping-Digital-Systems-Quartus%C2%AE/dp/0387277285/ref=sr_1_4?s=books&ie=UTF8&qid=1446240977&sr=1-4&keywords=VHDL+quartus+VHDLIt is much better to buy a proper book to learn something this complex. The author has spent gobs of time preparing the content such that it can be consumed easily. Trying to learn this stuff from web posts is doomed to failure (in my opinion...).Regarding timing; you don't simulate timing. You use 'Static Timing Analysis' to make sure that your timing meets the requirements. This is another complex field of study:http://www.amazon.com/s/ref=nb_sb_noss_2?url=search-alias%3Dstripbooks&field-keywords=static+timing+analysishttps://en.wikipedia.org/wiki/Static_timing_analysisAs you've found, Modelsim only simulates the functionality of your design.

author: Scrts
author_rank: Frequent Contributor
timestamp: October 30, 2015, 09:45:26 pm
content: Quote from: John_ITIC on October 30, 2015, 09:41:45 pmIt wasn't really clear for me. Does he want gate level simulation?There's an example for that too:https://www.altera.com/support/support-resources/design-examples/design-software/simulation/modelsim/exm-timing-vhdl-msaltera.html

author: AndyC_772
author_rank: Super Contributor
timestamp: October 30, 2015, 10:57:28 pm
content: Quartus automatically calculates worst case timing for every internal path when you synthesize the design. It has to do this in order to work out whether or not a given fit will actually work. The tool is called TimeQuest, and although you can run it as a separate task, it has a component which is part of the Fitter too.You need to specify the external constraints by creating a .sdc file. This is how you specify things like the speed of any external clocks, and the setup/hold relationships between clocks, data and strobes.When you synthesize the design, its internal timing is simulated as part of the process, and the specifications for the finished design are made available as part of the compilation report. You can also query any data path you like in TimeQuest, and it'll show you the worst-case timing for that path.ModelSim is a very capable logic simulator, but it's used for functional simulation of your VHDL. Unless I'm very much mistaken, although it's provided with functional libraries that describe the internal hardware (memories, PLLs and the like) of the FPGA, it doesn't contain a timing model of the device.

author: Yansi
author_rank: Super Contributor
timestamp: October 31, 2015, 02:41:47 am
content: Okay, that would explain a lot. Better to study the TimeQuest then.(But still, if I want a VHDL testbench and simulation result with all simulated time properties of the device? Possible or not?)Also thanks for the tips for books. The first one looks promising enough. I will try to get one.I'll be back when I get the book and try to make some steps forward...Yan

author: AndyC_772
author_rank: Super Contributor
timestamp: October 31, 2015, 09:51:30 am
content: The timing report you get at the end of synthesis will tell you any worst-case timings you need.It's not meaningful to say "the delay from A to B will be X nsec", because X depends on temperature and varies from device to device. What you can do, though, is specify in the .sdc file that the delay needs to be no more than X, and TimeQuest will tell you whether or not the device is guaranteed to meet that constraint.