EEVblog #1176 - 2 Layer vs 4 Layer PCB EMC TESTED! - Page 1
Forum section: electronics / general

author: EEVblog
author_rank: Unknown
timestamp: February 02, 2019, 12:02:44 am
content: What difference does a 4 layer PCB make to EMC radiated emissions compared to an identical 2 layer PCB? And why?Dave does H-Field near-field probe testing on two otherwise identical PCB's.Electromagnetic waves and the difference between near field and far field, and H-Field and E-field probes and wave impedance is also explained.The PCB layout is then examined to look at loop area and by-passing and what effect this has.

author: MT
author_rank: Super Contributor
timestamp: February 02, 2019, 12:53:38 am
content: Would be interesting to see emission differences between same designed boards in which one is smt the other dip.

author: EEVblog
author_rank: Unknown
timestamp: February 02, 2019, 12:56:17 am
content: Quote from: MT on February 02, 2019, 12:53:38 amWouldn't be any different if the layout remains otherwise identical.Would anyone be interested in a 6 layer version with grounds on the outside layers?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 02, 2019, 01:05:23 am
content: Can you stop bloody calling it "radiated" when you're measuring with a near field probe? THANKSTim

author: Matty
author_rank: Contributor
timestamp: February 02, 2019, 01:36:41 am
content: Hello - I'm confused about the spectrum shown. The harmonics are greater than the fundimental?Is it because the higher frequency is traveling though the air better? or the switching are all out-of-phase a little bit and making the noise?

author: abeyer
author_rank: Frequent Contributor
timestamp: February 02, 2019, 02:01:28 am
content: Is there a design rule or analysis type thing in any layout tools that helps identify loop areas? Seems like it would be amenable to to automated analysis.

author: MT
author_rank: Super Contributor
timestamp: February 02, 2019, 02:11:29 am
content: Quote from: EEVblog on February 02, 2019, 12:56:17 amI argue it would for the "higgelypiggelywoppdiidoo"2 layer.QuoteAs prior life PCB dude, yes please, on teflon!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 02, 2019, 02:52:50 am
content: Quote from: Matty on February 02, 2019, 01:36:41 amThe H probe reads dI/dt, so the spectrum of a square current (harmonic amplitudes go as 1/f), as read by the probe, is ~flat (an ideal periodic impulse).Connected to an integrator, you get ~the original current waveform again, uncalibrated of course (this isn't a current transformer, the gain will be arbitrary with distance!). This can help recognizing sources when probing in the time domain (on the scope).Tim

author: satblip
author_rank: Unknown
timestamp: February 02, 2019, 10:45:35 am
content: Superb video !I have two questions in mind:1) Does anyone have a reference for the probes and the preamp?2) I have always had trouble to understand why we put the ground plane and VCC in the inside layers and not the outside layers. It is definitely the right way as every good designer does it, but I would have though that if the ground layer was on the outside plane, it would have act as a shield?Thanks !

author: KaneTW
author_rank: Frequent Contributor
timestamp: February 02, 2019, 11:12:45 am
content: When you have signal layers on the inside, there's crosstalk for parallel signals on opposite sides. Having a DC plane prevents that.Ideally you want your noisy signals buried in a stripline pattern, i.e. covered with ground/vcc above and below.

author: johnlsenchak
author_rank: Frequent Contributor
timestamp: February 02, 2019, 02:35:02 pm
content: Information overload on the one ! LOL

author: Neilm
author_rank: Super Contributor
timestamp: February 02, 2019, 05:37:51 pm
content: I wasn't suprised by this at all.Many years ago there was a big change in the EMC regs for test equipment that affected the company I worked for. Many of there older instruments needed to be fix and as new instruments were in development, they didn't want to change any of the board test fixtures. I was given the task to fix these and was unofficially told to "add ferrites until they pass". Many of the failures were 2 layer boards with split power and 0V. Only one needed the split (for safety reasons).I got a grudging agreement to go try 4 layer boards with common 0V - grudging as "this will push up the board cost". It fixed all but 2 instruments (that we didn't sell many of anyway so they were obsoleted).For one instrument - it ment we could replace 2 ferrites that cost about £4.00 with one that cost £0.70 more than covering the cost of the PCB.Since then, 4 layer boards have been pretty much mandatory on all new products.

author: mcinque
author_rank: Unknown
timestamp: February 02, 2019, 09:36:45 pm
content: This is a great demonstration.And yes, I (and probably many other people) would be much interested to know what changes with 6 layers and ground outside!

author: mrpackethead
author_rank: Super Contributor
timestamp: February 02, 2019, 10:11:48 pm
content: EMC aside, designing a four layer board is just SO much quicker than a two layer.

author: Ribster
author_rank: Frequent Contributor
timestamp: February 02, 2019, 10:23:19 pm
content: Loved the video!

author: Barny
author_rank: Frequent Contributor
timestamp: February 03, 2019, 06:45:16 am
content: Quote from: satblip on February 02, 2019, 10:45:35 amIts to get more capacity betwen VCC and Gnd.The closer the layers, the higher the capacity.(Plate capacitor)

author: Doctorandus_P
author_rank: Super Contributor
timestamp: February 03, 2019, 07:49:29 am
content: I wonder what kind of design rules you used for the inner layers.Did the rows of the dip IC's cut big slots in those layers, or are the power layers sneaking between all pins?This is an area where SMD is better than THT. Smaller SMD chips also are closer together, hence smaller loop area's and less ratiation. (And the near field radiation is also radiated, even though not very far, it certainly is not conducted).I also would have loved to see a comparison with the board where you snapped off all the decoupling capacitors. What does that do with radiated noise?Also not a single word about distributed capacitance between the power planes, but I think this only becomes really usefull in the GHz range.15dB is a significant difference, but I do not find it shocking, it sort of gives me the idea that the original layout indeed is not too bad. The traces on that board are very coarse. It seems to be designed for home-etching. Any PCB factory can work with much finer design rules, and that would leave much more room for ground fills and via stitching.I would love to see a teardown of those blue probes. Tear those down!Is there any magnetics in there, or only an inductor? How much wiring?Many loops of very thin strands?Is the coil shielded? How about inter winding capacitance?I know the're bloody expensive, but a detailed teardown & analysis is much more interesting than a blab about a dumpster dive.I also would not be surprises if a piece of thin enameled copper wire wound on a corc would give comparable results. Coils of 230V relays are an easy source of thin wire if it's not glued together. A quality comparison between such a homebrew and the blue probes would also be very intersting. The blues are simply out of reach for almost all hobbyists.Also, you've got CNC machines (mill, 3d printer) and a robotic arm.You can attach the near field probes to one of those and then let a PC generate a "height map" or the radiated field. Especially if the resolution is high enough to see individual traces this can be a very usefull tool during pre-compliance testing of the first board revisions.You can get nearer to the traces (higher resolution) on the bottom of the board.If you want to do a follow up on this, I would also like to hear your opinion about dividing the budget between GND and Vcc planes on a 2-layer board.I think it is best to:1). Put decoupling caps as close to the IC's as feasible.2). Connect the decoupling capacitors (not the IC's) to the power planes.This way the Capactitors filter more of the noise generated by the IC's.It keeps the GND plane cleaner.3). Use Either GND (more traditional) or Vcc (uncommom) with as big an area as feasible.4). Use lots of via stitching, every trace should have a small loop area with the GND plane.5). The other Power net: Use some decent grit, but not too much area.

author: EEVblog
author_rank: Unknown
timestamp: February 03, 2019, 07:52:34 am
content: Quote from: mrpackethead on February 02, 2019, 10:11:48 pmYeah, no need to worry about power placement, it "just happens" at the end.

author: EEVblog
author_rank: Unknown
timestamp: February 03, 2019, 07:53:33 am
content: Quote from: Doctorandus_P on February 03, 2019, 07:49:29 amYou can watch the video:It didn't flow through the pin pads, and still the performance was hugely better.

author: mrpackethead
author_rank: Super Contributor
timestamp: February 03, 2019, 08:47:01 am
content: Quote from: EEVblog on February 03, 2019, 07:52:34 amPerhaps a little simplified, and true when you only have one power rail. When you have six it needs a bit more help.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: February 03, 2019, 10:37:23 am
content: I did watch through the video, and find it astounding that you can get any work done while simultaneously & continuously talking & reading & responding to that text thing on the left.If you had 5% of the experience with KiCad compared to Altium this would have been 2 minutes of work.To Try to keep short I will only comment on one thing, because I found it too painfull to watch (as you also predicted @12:53 in the video).You spend almost 10 minutes (From 49:25 to 58:09) talking about a feature KiCad presumedly does not have, and then at 58:09 you accidentally do exactly what you want and even more, but you do not recognize it because you are talking too much and distracted by commenting to the others.Another reason you did not recognize it is because the design rules are set much smaller than what they were originally routed on. So KiCad does not only straighten 3 traces with one mouse swoop, adjusts the trace spacing to the current design rules. It has also placed those traces off grit. Design rules take precedence over grit settings, as you are explaining @51:30. I appreaciate you want to give constructive feedback to the KiCad team, but it will not be necassary for this feature.I even managed to capture a screenshot of the straightened & off grid routed traces.This works so well that I only use a grid for placing components and holes and such, and ignore the grid for routing traces. Trace widhts should be defined by DRC rules, not by some grid. You say Altium users keep changing the Grid all the time. I just ignore it (or set to < 1mils).Note 1: If you do not want the traces hugged so closely you should edit the design rules for those traces, and not use the grid.Note 2: Traces can also be locked.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: February 03, 2019, 11:42:34 am
content: I've also used many different PCB programs in the last 30 years. Mostly for hobby projects, I'm not a "professional designer" (whatever that means).And they all have their quircks.I've also read and seen many reviews, and the common thing is that reviewers tend to like and appreciate the programs they are familiar with, and have difficulty with adjusting to the idiosyncracies of software they do not know wel. A classical example of this is the mouse rant in the beginning of the video.I found that a nice way to pan is to zoom out on one section of a board, and then zoom in on another section, both with the scroll wheel, not even a need to laboriously push a button. But as everything, it takes some time to get used to it.

author: nctnico
author_rank: Super Contributor
timestamp: February 03, 2019, 01:06:23 pm
content: Quote from: Doctorandus_P on February 03, 2019, 11:42:34 amI agree with that. Every PCB package has a certain work flow and idea behind it. I'm currently learning a new PCB package and even though the old one is from the same vendor (Cadence) it works completely different. Not so different compared to other packages I have used but nevertheless it is going to take time to get to the level of productivity I could achieve with the old package. Fortunately the new package has a very easy way to create shortcuts so I re-created the most used short cuts from the old program.

author: German_EE
author_rank: Super Contributor
timestamp: February 03, 2019, 08:05:28 pm
content: I can think of only one advantage of two layer boards over four, removing devices during repair is a lot easier.If whilst replacing a chip on a two layer PCB you remove a plated through hole then the repair can be easily done, even on a power pin. Sure, you might need to drill a 1mm hole and pass a wire through to link a couple of traces but it can still look good.Now switch to a four layer PCB and pull out a plated hole by accident. It's impossible to remake the connection without a jumper wire to the nearest power or ground pin, thereby destroying your EMC work.Yes, I know that it's possible to remove any part using professional equipment without damaging the PCB, but not all of us have that professional equipment and after using braid or a manual solder sucker on the same pin for the fifth or sixth time you may hit problems.

author: mrpackethead
author_rank: Super Contributor
timestamp: February 03, 2019, 10:17:52 pm
content: Are through hole parts even a thing still

author: tszaboo
author_rank: Super Contributor
timestamp: February 03, 2019, 10:35:35 pm
content: Quote from: Neilm on February 02, 2019, 05:37:51 pmPretty much. I havent designed a 2 layer PCB in this decade, unless I could keep the entire bottom side as ground. Most of the stuff I design nowadays require some impedance control, and making a 50 ohm trace on a 1.5mm thick board is just ... inconvenient.

author: mrpackethead
author_rank: Super Contributor
timestamp: February 04, 2019, 12:19:29 am
content: Quote from: NANDBlog on February 03, 2019, 10:35:35 pmyeah, 2.5mm wide tracks are possibly going to make it hard!

author: EEVblog
author_rank: Unknown
timestamp: February 04, 2019, 02:05:45 am
content: Quote from: Doctorandus_P on February 03, 2019, 10:37:23 amIt was not meant to be a work video, it was just me playing around with KiCAD whilst doing some live chat whilst I just happened to do what I want. It is what it is, and no, you can't effectively get work done whilst doing such a thing, that's why it wasn't about me getting work done in any kind of effective way. You don't have to like that style of video, and that's fine. And there is no point telling me the issues with that, trust me, I know.BTW, I did make some very valid usability points in the video and someone on the KiCAD team actually thanked me for that.

author: Neilm
author_rank: Super Contributor
timestamp: February 04, 2019, 07:55:55 pm
content: Quote from: German_EE on February 03, 2019, 08:05:28 pmIt is also cheaper. If I can make a board that passes EMC requirements on 2 layers then why would I want to make it 4 layer? I will admit the only boards I have ever done 2 layer were electrically very simple but I have done them.

author: boffin
author_rank: Unknown
timestamp: February 05, 2019, 03:22:00 am
content: Quote from: EEVblog on February 02, 2019, 12:56:17 amI'd actually be curious to know if it's any better if you place the power/ground on the outside layers, and run the data tracks on the buried layers.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 05, 2019, 03:36:54 am
content: It would be, though a design like this is still dominated by the size and thru-hole shape of the DIPs used.An SMT build isn't much better, because you still have via rings on the back side.In both cases, VCC will be chopped up by inevitable too-good-to-miss-out-on routes, between adjacent and nearby pins.For DIP, pour around all pins is quite feasible, but hard to maintain for SOIC (plus a via per pin, on average, more or less), and impossible for TSSOP or smaller. So the rows of pads in the latter case will cause a void in the VCC pour.Consequently, you'll want to space things out somewhat more than you would even for a 2-layer build (with no particular attention to EMC, that is), which means you aren't saving any size going to four layers here. So, your motivation is now, just to say you could, more than anything.The best you could do, is to opt for blind vias ($$). Then you could build top side components and VCC on top layer, drop vias to Mid1 for priority routes, then route intersections and low priority routes on Mid2+. Ground vias are regular thru vias or pads. This would give you 100% solid bottom ground (except for vias), which is excellent shielding for frequencies well above the skin depth of that copper thickness (so, for 2oz, some MHz).One possible advantage of this kind of construction: the majority of traces/routes are fully encapsulated, making corrosion a somewhat lower risk. Vias, pads and connecting traces are still vulnerable; vias can be plugged/capped (for another dollarsign more; we're already not caring about fab cost, so what the hey), and we can do double layer of soldermask, or fill silk everywhere*. Or both, why not. And obviously, there's always the boring answer, conformal coating.*Oh that's something I should try some day, do an inverted silk board. Text can be drawn with inverted labels, and the negative space inbetween can be filled without too much futzing (possibly a polygon can fill it, but I kind of doubt that Altium at least calculates poly clearances that way, on non-copper layers that is, hmm).Tim

author: srce
author_rank: Regular Contributor
timestamp: February 15, 2019, 03:34:37 pm
content: A while ago, I was playing around with COMSOL to get a feel for how a 4-layer PCB reduces crosstalk. You can model any combination of materials you want:Then calculate the electric potential. Here for 2-layer PCB then 4-layer, both with the same thickness (1.6mm):The closer ground plane on the 4-layer PCB considerably reduces the potential on the parallel wire (from about 0.15V to 0.01V). You can get better results for the 2-layer board by making it thinner.Going back to the subject of this thread, if we look at the field in the air above too, we can see how that is also reduced:Obviously, it's better still if you have 6 layers and can sandwich it between two planes:

author: WanaGo
author_rank: Regular Contributor
timestamp: January 28, 2020, 02:55:05 am
content: Quote from: satblip on February 02, 2019, 10:45:35 amSorry for the dig up on this, but does anyone know the answer to this?I saw the spectrum analyser he used is the Rigol DSA815, but I didn't spot the pre-amp or what the probes are exactly.We are wanting to get a test setup like this at work so the engineers can do some testing before sending them off to the lab, it might save us some time and money being able to see real problem areas of the prototypes.Thanks

author: EEVblog
author_rank: Unknown
timestamp: January 28, 2020, 03:35:16 am
content: Quote from: WanaGo on January 28, 2020, 02:55:05 amhttps://www.tekbox.com/product/tekbox-tbps01-emc-near-field-probes/Near field testing can help detect issues, but nothing beats a proper far field antenna test which is what they will do at the lab. A decent far field antenna will cost more than the entire near field rig including the spectrum analyser though.This is one of the cheapest ones you can get:https://www.aaronia.com/products/antennas/BicoLOG-30100-X/

author: nctnico
author_rank: Super Contributor
timestamp: January 28, 2020, 10:54:07 pm
content: Quote from: WanaGo on January 28, 2020, 02:55:05 amThe 'RF explorer' near field probes are even cheaper compared to the ones from Tekbox.But still don't expect much from doing near field probing to check whether your device will pass EMC testing. The biggest problem usually is emissions from wires and in some freaky situation the casing. So you better get some current clamps to measure RF leakage going through cables. A LISN is also a good investment to check conducted emissions in the power supply. I never needed to use a pre-amplifier for EMC trouble shooting.When it comes to emissions you really should do a pre-compliance measurement at a test lab. Then you can get a graph with the problem areas in the frequency spectrum. From there you can hunt down the source using near field probes and current clamps. Otherwise you will be literally taking a stab in the dark.

author: julian1
author_rank: Frequent Contributor
timestamp: April 09, 2024, 11:29:09 am
content: At 5.20min, for the test setup-up,For someone who knows little about spectrum analyzers - what is the reason both attenuation (to prevent input saturation) and the pre-amplifier (to add gain) both turned on?

author: thm_w
author_rank: Super Contributor
timestamp: April 09, 2024, 08:36:09 pm
content: Quote from: julian1 on April 09, 2024, 11:29:09 amAs you said, attenuation is first which can prevent input saturation, or maybe damage to the instrument.https://electronics.stackexchange.com/questions/345515/what-does-the-attenuation-setting-do-in-an-rf-spectrum-analyzerhttps://saving.em.keysight.com/en/used/knowledge/guides/spectrum-analyzer-buying-guide/how-to-read-a-spectrum-analyzer-like-a-prohttps://www.keysight.com/blogs/en/tech/rfmw/2020/05/28/spectrum-analysis-basics-part-2-whats-in-a-spectrum-analyzer