Using IC Parallel DAC, clock, and matching impedance - Page 1
Forum section: electronics / beginners

author: Anthocyanina
author_rank: Frequent Contributor
timestamp: November 06, 2021, 01:19:16 pm
content: A few months ago i started working on designing an amplifier to use with the raspberry pi pico, to make a simple AWG. I designed a 3 transistor class A amplifier, and was using an R2R DAC. The amplifier was able to drive a 200 ohm load, which was great, but in the higher frequencies(10-20MHz), it was very messy; i attributed that mostly to the R2R DAC as i don't have a good multimeter to measure resistance in order to match the resistors properly, and also think at those frequencies the parasitic capacitance and inductance of the R2R circuit starts really affecting the waveform shape. So i decided i want to build the awg with integrated circuits instead of doing it all with discrete components. This would be my first time using an integrate DAC so i have a few questions.The DAC i plan to use is the AD9750, which has a parallel interface, which is great as i wouldn't need to change the code of the pico. I noticed while reading the datasheet they mention the clock a lot and seemingly interchangeably talk about it in terms of MHz and MSPS. Since the pico doesn't necessarily always push out 125 MSPS, I wonder how i should drive the DAC, should the clock always match the sampling rate of the pico? Would it be ok if i just run the clock at 125MHz all the time?I also noticed in its datasheet the output impedance is >100K. As i plan to use the THS3091 as the amplifier, which throughout its datasheet is shown as getting input from a 50 ohm source, I would like to know how i can match the impedances, such as the output of the DAC matches the input of the amplifier. Impedance matching is something i know very little about, we practically just skimmed thru that in class, so it's not very clear how to do it. Tutorials i've found online regarding that describe the use of LC networks, but those have a limited bandwidth from what i've seen, and are mostly used to match impedances at a specific frequency. I would like to avoid using an emitter follower circuit if possible. So i would like to know, are there any integrated circuit devices made for impedance matching? Could i just directly connect the DAC output to the amplifier input and not have to worry about the impedance mismatch? another thing that isn't clear is if the amplifier input is 50 ohm or if it's just the way they configured it with the external components that require a 50 ohm source, so maybe connecting a 100k+ output to its input isn't actually a problem at all?Any help with this questions will be appreciated, specially if you know of a guide or any other resource which explains these things, as i would like to understand them in depth and not just know what to do in this specific case.Thank you all!

author: radiolistener
author_rank: Super Contributor
timestamp: November 06, 2021, 03:26:01 pm
content: Quote from: Anthocyanina on November 06, 2021, 01:19:16 pmIt is not only should match, but also should be precisely synchronized. It means that your pico should change parallel output on each edge of a DAC clock. So your pico should be able to be clocked from 125 MHz clock from DAC. I don't know much about raspbery pi, but I suspect your pico will be unable to handle 125 MHz clock.If you want to build AWG, then CPU is unable to handle DAC due to very low speed.You're needs to use FPGA which is able to calculate sine wave at 125 MHz sample rate.The schematic is very easy. You're needs to put 125 MHz clock to the DAC and FPGA. FPGA will produce waveform (for example sine) at clock speed. You're needs to implement NCO inside FPGA for that. In order to avoid phase delay issues, you can use DAC clock from FPGA, so the DAC data and clock lines will be driven by FPGA output. This is much more easier, but FPGA output pins have pretty high jitter, so this is not the best solution if you want to get very clean output.Also, it is better to calculate sine wave at higher frequency (for example at 4 x 125 = 500 MHz sample rate) and then decimate it with interpolation to get more clean sine.Of course you can try to play with DAC using CPU, but your output frequency will be very limited with CPU speed and output frequency will be very unstable. You can get 1-2 kHz at max on the output in such way.

author: radiolistener
author_rank: Super Contributor
timestamp: November 06, 2021, 03:57:44 pm
content: I recommend you to buy some FPGA starter kit board if you want to experiment with high speed DAC for AWG.5-15 kLE will be enough, but it also should have hardware multipliers. Cyclone IV or Cyclone 10LP will be enough for your needs.

author: Anthocyanina
author_rank: Frequent Contributor
timestamp: November 06, 2021, 04:32:18 pm
content: Quote from: radiolistener on November 06, 2021, 03:26:01 pmHi! Thank you! The pico's PIO state machines allow for pretty fast switching of the output pins. this screenshot for example shows the fastest changing bit generating a 15MHz sine wave, and it goes from low, to high, to low in 15ns. I only need the output frequency to be at most 20-25MHz so this seems adequate enough for that. Now i wonder, does low count as a sample too? if not, then this is 62~MSPS hmmmQuote from: radiolistener on November 06, 2021, 03:26:01 pmIn this case you're using 500MHz sample rate for a 125MHz sine wave output?Again, thank you!

author: Anthocyanina
author_rank: Frequent Contributor
timestamp: November 06, 2021, 04:41:34 pm
content: Quote from: radiolistener on November 06, 2021, 03:26:01 pmHmm, this is the output i get from the R2R DAC on the pico, while fairly distorted, i think this is still useable, specially with a better DAC at those frequencies, why would it be limited to 2KHz?Thank you!

author: radiolistener
author_rank: Super Contributor
timestamp: November 06, 2021, 09:59:37 pm
content: Quote from: Anthocyanina on November 06, 2021, 04:32:18 pmit's a long story. CPU cannot do it because it's output is not synchronous and can be delayed for random time. For DAC you're needs to put the next sample with a fixed time interval. This time interval should be very precise. Even 10 ps error will be noticeable on the output as a waveform distortion. In your case the error will be about 50000-100000 ps. This is too much.Even if your CPU can generate 15 MHz square wave carrier on the port, such output will consists a bunch of very high random jitter. So, the result will consists a lot of harmonics and spurs.Note that 15 MHz in your case is not a output sine. This is a max clock rate and it is not stable, sometimes it takes 33 ns, sometimes it takes 66 ns and more. In order to get a sine waveform you're needs at least 8-16 points per period. So the max sine frequency in your case will be 15 MHz / 16 = 0.93 MHz.If you're want to get clean sine, you're needs to update data lines on each clock edge synchronously. CPU cannot do this. And this is why CPU is never used for AWG, they using FPGA to control the DAC.Quote from: radiolistener on November 06, 2021, 03:26:01 pmSorry there is my mistype, I wanted to say that it's better to upsample it from 125 MHz to 500 MHz with interpolation. But you're needs to use a DAC which supports 500 MHz clock. Some DAC chips already have internal interpolator, so you can work with it at lower clock speed.This is needed to reduce harmonics and spurs on the output. When you use 500 MHz DAC it's Nyquist zone is 250 MHz, so you're have a gap between 125 MHz and 250 MHz which can be used for antialiasing filter with a more smooth slope.Quote from: Anthocyanina on November 06, 2021, 04:41:34 pmtry to put values from 0 to max value with incrementing by 1 for each next sample at max speed. It should produce sawtooth wave. And show the result waveform...Here is example what I get onDAC904driven by STM32F103 with 72 MHz core and 100 us software delay between clock pulses. Unfortunately don't have screen without delay. It looks like what you want to achieve, but I got very limited max frequency with that installation and very dirty output due to a high clock jitter generated by CPU port pin. Just played with DAC to test it.

author: Anthocyanina
author_rank: Frequent Contributor
timestamp: November 07, 2021, 01:44:50 am
content: Quote from: radiolistener on November 06, 2021, 09:59:37 pmHmm, i think there might be a misunderstanding about what i'm using. I know the raspberry pi single board computers are not good for this task, as i'ev seen the jitter on its GPIO pins. I'm not using a raspberry pi single board computer. The pico is a board based on the RP2040 microcontroller. It is running at 125MHz and it has very fast programable IO, which is also very precise. With the R2R DAC i have i can get an ok enough triangle wave of 1.25MHz, like in this screensthot. The pins can switch at over 50MHz (screenshot 1)Quote from: radiolistener on November 06, 2021, 09:59:37 pmOh, sorry, i uploaded a screenshot of it at 10MHz and another one at 15MHz what's in the screenshot is at the output of the R2R DAC, not at one single pin of the microcontroller. It is quite distorted after a few MHz but it is pretty stable, time-wise. I'm attributig that distortion to the DAC and not to the microcontroller itself, as when i probe each pin withthe R2R DAC unplugged, it looks the same as in lower frequency waveforms, just faster. Here is what the 10 MHz sine looks like when completely zoomed in. Jitter is at most 3ns.(screenshot 2)Quote from: radiolistener on November 06, 2021, 09:59:37 pmI've attached here a screenshot of the faster triangle wave i can get without it getting too distorted. It can get to 1.25MHzI think eventually i will make one with an FPGA but for now the pico is what i have to work with, and it looks like a reasonable device to be able to generate a few MHZ of various waveforms.Thank you!Edit: have not figured out how to attach images as part of the message yet

author: radiolistener
author_rank: Super Contributor
timestamp: November 07, 2021, 03:18:18 pm
content: Quote from: Anthocyanina on November 07, 2021, 01:44:50 amAccording to your screenshot, the jitter is about 40 ns (see a falling slope). This is too much. It should be below 0.001 ns in order to get clean output.Yes, your CPU is fast enough to play with it, but don't expect clean non-distorted output on the DAC. Because GPIO on your CPU has very high jitter. Non linear distortions are caused due to this jitter on GPIO. As I said before, this is normal behavior for CPU. In order to eliminate it you're needs to use FPGA.Also I see that there is different phase delay between data lines on your sine screen (it has powerful even harmonics), probably because you're using wires with different electrical length, but it also can be due to different phase delay on GPIO lines. This issue can be fixed by using DAC chip with clock input.But the main issue is a jitter of your GPIO buffer.

author: Anthocyanina
author_rank: Frequent Contributor
timestamp: November 07, 2021, 11:42:23 pm
content: I really don't see the 40ns jitter you mention, could you please draw it on my screenshots so i can see it? thank you!Here's the falling edge of the triangle wave zoomed in as much as i can. zoomed in vertically as well as with those slow edges it looks almost like a flatline at the fastest time base if not zoomed in vertically too. highest jitter is at most 5.1ns. I'm not seeing 40ns anywhere

author: radiolistener
author_rank: Super Contributor
timestamp: November 08, 2021, 05:28:35 pm
content: Quote from: Anthocyanina on November 07, 2021, 11:42:23 pmYou cannot see jitter on a single sweep.You're needs to run continuous mode on oscilloscope and enable persitence mode in order to see it.And don't look near the trigger point. Trigger point never shows the jitter, because this is the point for ocilloscope sync, oscilloscope always shift waveform in such way to get zero jitter at this pointAdd at least 40-50 ns delay for the triggerOr look for a second edge after trigger pointPS: also avoid oscilloscope ADC overload, your signal min and max should fit into the screen, otherwise you can get unexpected distortions

author: Anthocyanina
author_rank: Frequent Contributor
timestamp: November 08, 2021, 05:49:46 pm
content: Quote from: radiolistener on November 08, 2021, 05:28:35 pmso where are you seeing the 40ns jitter?anyway. let's assume i want it to be jittery, anyone has any thoughts on the impedance matching part of the questions? Thank you!

author: radiolistener
author_rank: Super Contributor
timestamp: November 08, 2021, 06:18:46 pm
content: Quote from: Anthocyanina on November 08, 2021, 05:49:46 pmYour oscillogram screenshot is taken incorrectly, you cannot see the jitter at trigger point. And you cannot see the jitter at single sweep.There is two way to see the jitter:1) Setup trigger delay for a half or one signal period2) Setup time/div in such way to see at least half or one signal period. This way is not usable to see the jitter for a low frequency signal.And don't forgot to enable countinuous sweep mode with persistence mode on your oscilloscope.

author: Anthocyanina
author_rank: Frequent Contributor
timestamp: November 08, 2021, 07:44:14 pm
content: Quote from: radiolistener on November 08, 2021, 06:18:46 pmThank you, i see what you mean now. I didn't consider that as i've seen the line thickness has a limit, even at a slower timebase it will visually appear just as thick, because pixels are discrete so it decides if it will fill it or not. I also realized i wasn't probing it well enough, so i changed my probing setup, on the same DAC output, and now, at the same timebase, measuring at almost 2 periods away from the trigger point, with the cursors i can see 16ns. at a faster timebase, it's much easier to get cloer to the actual time and i can measure 10.4ns (running, not stopped). and when going to the fastest timebase, without vertically scaling it, i measure 9.5ns. Also note intensity is at 100%. But without scaling vertically, the slope is too shallow, and still, at each timebase, while being about 1.2-1.6µs away from the trigger, the time shrinks the faster the timebase as you now get more pixels per time unit. I'm still happy with the digital output of the microcontroller for what i need this, and even the R2R DAC i'm using isn't horribly unusable for my purpose, but i would like a better DAC and amplifier, hence my original questions. thanks again!