Lattice Radiant for iCE40UP FPGA series - Page 1
Forum section: electronics / general

author: iMo
author_rank: Super Contributor
timestamp: March 07, 2018, 10:16:22 am
content: As the new "Lattice Radiant" development system tailored for the iCE40UP3k/5k series has been mentioned briefly in other topics let us start a separate thread..I've spent a few days comparing a verilog design (j1a cpu) under IceCube2 and Radiant. They changed the names and parameter's formats with all primitives in Radiant, thus you have to migrate an existing design from the IceCube2 (or IceStorm) to the Radiant first. It requires a lot of reading, howeverAs an example I've compared the building of an "identical verilogdesign" under IceCube2 and Radiant - a j1a (forth) cpu utilizing all bram and spram and 27 pins, running at 24MHz w/ internal oscillator (iCE40UP5k UPduino board):Code:Tool Size(LUTs) Time to build maxClk est. ==========================================================IceCube2 2703 2:56 35 (34-36)Radiant 2741 3:30 19 (15-20)Note: time to build is +/-10secs, SynPro w/ default IceCube2 and Radiant setup, ring-osc commented out.The Radiant provides rather conservative timing's estimates (similar to the IceStorm's ones), while IceCube2 is always pretty optimistic.On silicon the Radiant binaries with 15-17MHz max clockestimatesare not working properly, thus it seems the Radiant providesmuch more realistic estimates.Some first glance findings:1. The Radiant offers a new INV primitive, therefore I've tried to create a ring oscillator made of 3 INVs (a part of a random generator). It does not synthesize with SynPro, it does with LSE (and it works on silicon).Edit: Tech Support proposed a workaround, it works.2. The Reveal Analyzer inserts an JTAG module into your design (together with an LA) - here the synthesis stops with an error indicating an unknown primitive "INV_c" wired in jtck signal.3. The Reveal Analyzer knows the FT232HCode:INFO - cable=FTUSB-0,USB2,Single RS232-HS Location 0000The logic analyzer has not been tested yet, see point 2.

author: ehughes
author_rank: Frequent Contributor
timestamp: March 07, 2018, 01:45:09 pm
content: QuoteForgive my ignorance as I am new to Lattice products, are they using the FT232H as a JTAG interface?

author: iMo
author_rank: Super Contributor
timestamp: March 07, 2018, 01:47:45 pm
content: Yes (hopefully, they offer a box, most probably with FTxxxx inside, the Programmer works with FT232H too). Afaik the Reveal Inserter configures your on-chip Logic Analyzer (you set the LA buffer depth, signals to watch, triggers) and creates a verilog/vhdl module with JTAG interface and LA for you.You have to add the file into "Debug" folder, set the JTAG pins as you wish (?), and run the build. You have to create a sampling clock as well (via PLL for example, max 200MHz). Currently it uses EBR for the LA buffer, perhaps they will do with SPRAM as well (ie. the UP5k has got 15kB of EBR and 128kB of SPRAM).Then you run the Reveal Analyzer.It is something similar to the ChipScope (Xilinx).

author: iMo
author_rank: Super Contributor
timestamp: March 07, 2018, 10:34:34 pm
content: With FT232H - the session (counter_reveal example, with different JTAG pins):Code:INFO - runProject on device  using C:/Lattice/counter_reveal/my1.rva [insert.rvl]INFO - Connecting cableserver to run Reveal debugger....INFO - Connecting core0....INFO - Configuring core0....INFO - pattern readout passed!INFO - signature from core0 passed!INFO - Configuring in burst mode....INFO - finished configuration of core0INFO - Starting all active cores....RvaThread: running...INFO - Running all active cores....INFO - Polling trigger memory of core0....INFO - Downloading trigger memory of core0....INFO - Uploading in burst mode....INFO - finished download trigger memory of core0INFO - All messages logged in file C:/Lattice/counter_reveal/impl1/reveal_debug.logCode:Wiring FT232H <-> Reveal AnalyzerFT232H FPGA pin* softJTAG FPGA pin dir====================================================AD0 26 TCK inputAD1 27 TDI inputAD2 31 TDO outputAD3 32 TMS input*User may define, other pins not tested yet..And the picture below..

author: Cerebus
author_rank: Super Contributor
timestamp: March 08, 2018, 01:46:00 am
content: Quote from: imo on March 07, 2018, 10:16:22 amConfused. You say the conservative timings are more realistic, but then you say that a physical clock that meets those estimates does not work.

author: iMo
author_rank: Super Contributor
timestamp: March 08, 2018, 06:51:57 am
content: As I wrote above 24MHz internal clock was used with the tests.. Those were 15-17MHz max clock "estimates".. Fixed above. Thanks.

author: PartialDischarge
author_rank: Super Contributor
timestamp: March 22, 2018, 05:25:55 pm
content: I can't download Icecube2, web is not working, anyone can get through the download link on this page?http://www.latticesemi.com/iCEcube2

author: Cerebus
author_rank: Super Contributor
timestamp: March 22, 2018, 05:47:06 pm
content: It's a problem at their end, give it a day and try again.

author: iMo
author_rank: Super Contributor
timestamp: March 22, 2018, 06:01:15 pm
content: Works fine here.Btw you have to click on the "IceCube2..." (see below) in order to start downloading."Download Selected as Zip File" does not work here..

author: PartialDischarge
author_rank: Super Contributor
timestamp: March 22, 2018, 06:17:59 pm
content: Quote from: imo on March 22, 2018, 06:01:15 pmNot here, What OS/browser are u on?I'm on Macos 10.13, Safari 11 and Firefox 59 and it doesn't load.

author: iMo
author_rank: Super Contributor
timestamp: March 22, 2018, 06:35:53 pm
content: Win7 64bit, Firefox 59.0.1

author: Cerebus
author_rank: Super Contributor
timestamp: March 22, 2018, 06:42:43 pm
content: Gentlemen, it may depend onwhereyou are, it's probably going through an edge caching content delivery network at some point. When I try to access over HTTPS(which is where you were having a problem, during login) I get an explicit reset sent by the far end. HTTP (without the S) goes through fine. That makes we think there's a far end problem that will probably go away of its own accord.

author: helius
author_rank: Super Contributor
timestamp: March 22, 2018, 06:42:56 pm
content: They may have enabled TLS1.3 onlywhich, indeed, causes special problems for middleboxes

author: iMo
author_rank: Super Contributor
timestamp: March 22, 2018, 06:47:22 pm
content: The pages I mess with are http: and the file download is from http:

author: PartialDischarge
author_rank: Super Contributor
timestamp: March 22, 2018, 08:45:08 pm
content: Thanks people, Cerebus u were right, after a few hours problem solved itself

author: Cerebus
author_rank: Super Contributor
timestamp: March 22, 2018, 09:56:14 pm
content: Quote from: MasterTech on March 22, 2018, 08:45:08 pm[ Breathes on nails, buffs them on shirt. ]

author: Scrts
author_rank: Frequent Contributor
timestamp: September 04, 2018, 04:47:25 pm
content: Hello,I've started to work on these FPGAs a little bit (up5k) and going from Altera to Lattice seems to be going back. A lot.First of all, I've installed Diamond, which was my mistake - the ice40 devices are not supported. Then I've installed IceCube2, which doesn't even have a color coded editor. They didn't even bother to put menu item to instantiate an on-chip oscillator. However, at least I could instantiate I2C/SPI core going through the menu.Now once I had to do some on-chip debug, I've started to look into Reveal logic analyzer, which documentation says that it fits into up5k FPGA. Now the problem is that you cannot instantiate it in IceCube2 and need Lattice Radiant software.Ok, downloaded that. The editor seems to be good, the menus are nice, the compile time is also quick and I see that I can run Reveal Inserter. But wait, where is the I2C/SPI or On-chip oscillator inserters? None. It doesn't even recognize the old instantiation in the code from IceCube2. So you need two independent software packages to run two features, but you cannot get compatibility between the project files and source codes? This sounds like 80s...

author: iMo
author_rank: Super Contributor
timestamp: September 04, 2018, 04:59:41 pm
content: Yes, the IceCube2/IceStorm and the Radiant are not compatible anymore. It has been discussed in a different thread, afaik.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 04, 2018, 05:11:26 pm
content: They have changed a lot of stuff between the two - for the better IMO, but I realize it would be an annoyance for people having to use older projects.Radiant's online help helps figuring out the new names/components. Taking a look at the hdl libraries can also help: you can find the source code with the components declaration in the following directory:Code:C:\lscc\radiant\1.0\cae_library\synthesisBut there is no "porting guideline" as of yet that I know of.

author: Scrts
author_rank: Frequent Contributor
timestamp: September 04, 2018, 05:39:42 pm
content: So which one you use? It seems like IceCube2 + Notepad++ seems to be the best option for design so far.

author: iMo
author_rank: Super Contributor
timestamp: September 04, 2018, 05:44:36 pm
content: They issued SP1 for Radiant recently, so it seems they mess more with Radiant than with IceCube..The changes are not huge, however - there is an example comparing IceCube/IceStorm/Radianthere..

author: Scrts
author_rank: Frequent Contributor
timestamp: September 04, 2018, 05:45:32 pm
content: Quote from: imo on September 04, 2018, 05:44:36 pm5MB patch on 600MB software doesn't sound like an SP... Probably just a quick bandaid on something urgent.

author: ilik
author_rank: Contributor
timestamp: December 20, 2018, 08:31:13 am
content: Anyone messed with Reveal Analyzer? it doesn't seem to work. gives errors "incorrect pattern readout" when trying to collect data. everything else works fine, fpga gets programmed and everything.

author: iMo
author_rank: Super Contributor
timestamp: December 20, 2018, 05:57:19 pm
content: See Reply N3 in this thread..

author: ilik
author_rank: Contributor
timestamp: December 20, 2018, 09:23:14 pm
content: yes but on comment 3, you discuss ice40 ultra plus 5k breakout board where FTDI is already soldered. i have my own PCB and am trying to JTAG it by HW-USBN-2B programmer. i did followed HW-USBN-2 pinout manual, and connected soft jtag pins according to it. but when i try to analyze it by reveal analyzer it gives error: "incorrect pattern readout" . error log file shows readout:#pattern readout = ffff#pattern expected = A5A5i have read in the reveal troubleshooting guide that all ffff mean there is a clocking problem:"The third cause for the incorrect signature error message is when the sampleclock is not correctly connected to the debug logic. This can occur if aproblem happens in the implementation flow. The signature read from thedevice will be all ones in this situation. To resolve this, the post-map netlistneeds to be viewed directly to determine the root cause."reeeally? now i have to mess with netlist and figure out which clock should go where? for this i will have to study entire soft jtag protocol how else will i understand how to clock it properly. (my sample clock is basic onboard HSOSC 48mhz and yes, it is turned on, checked on testpoint).PS. Lattice refuses to Tech support individuals that are not registered to their organisations list.

author: Bassman59
author_rank: Super Contributor
timestamp: December 21, 2018, 04:44:54 am
content: Quote from: ilik on December 20, 2018, 09:23:14 pmIs the FPGA programmed with a design that includes the Reveal debug logic?

author: ilik
author_rank: Contributor
timestamp: December 21, 2018, 05:46:21 am
content: yes, by a .bin progrmming file that gets generated in the impl_1 folder where the design resides; and i can see it in a netlist viewer (both soft jtag and reveal are observable).there is huge lcell use in the floorplan editor; timing analysis passes without violations.if it really is a synthesis problem then compiling the project by LSE and Synplify should have given different results. but both end up the same way so i doubt that it is syntheis related.i also tried example project that came with Radiant. a counter with reveal already set up in it. project compiles, programs, the LED blinks, Reveal analyzer gives same "incorrect pattern readout" error.changing soft jtag input pin's pull-up internal resistors from 100k ohm to 10k ohm gave zero results (tried it just in case).does it matter if the programming file is a binary (.bin) or a raw bit file (.rbf)? both should be ok with reveal analyzer no?since the pcb was developed by me, i must assume that it is an electrical or pin connection problem that sneaked out somewhere on the design stage((i should have checked the Tech support unavailability before messing with lattice (intel is a same donkey regarding tech support).

author: ale500
author_rank: Frequent Contributor
timestamp: December 21, 2018, 06:23:28 am
content: You mention the internal oscillator as your clock source. At least in the MacoXO2, the system clock of your design has to be higher than the jtag clock. If you are clocking your logic with say 1 MHz, reveal analyzer doesn't work. Could it be an issue ?

author: ilik
author_rank: Contributor
timestamp: December 21, 2018, 07:23:26 am
content: as i recall it from yesterday evening, JTAG clock coming from the programmer was ~12.2MHZ. internal oscillator runs at 48MHz.i knew that reveal's sampling clock must be at least twice or more greater than soft jtag clock.i'm telling you i thought about everything. that's why i have no other choice to ask for help, i'm out of ideas:((((PS. lattice won't bother to help developing engineers like me, then they complain that their sales won't grow,they fall; and try to sell themselves to chinese, then congress bans the acquisition and puts them down back on their place. then a fool like me put's he's hands where he shouldn't and here is the result)

author: iMo
author_rank: Super Contributor
timestamp: December 21, 2018, 08:44:52 am
content: QuoteI was using a plain 5k board (UPduino v1) with an external cheapo FT232H breakout board, afaik. There is a wiring description you may see in Reply #3.As indicated you may define the pin layout of the soft-jtag (and build with your own). Doublecheck your setting again and try with the example project. It simply worked first time..PS: Their tech support - simply register yourself and you will get the support. I had about a dozen of requests to the TS. They started to deal with the tickets always within 24h.

author: ilik
author_rank: Contributor
timestamp: December 21, 2018, 10:19:36 am
content: Quoteokay....their tech support gives this warning:"Thank you for contacting Lattice Technical Support.Our system has identified your email ID as a public domain email ID or an university email ID.To obtain Lattice Technical support, you must register under your company namewith your official company email ID and other company details.If you do not have an official (company) email ID, you can use our extensive online resources to address your queries.We do not provide technical support to tickets with public (e.g. gmail.com, yahoo.com etc…) or university (.edu) domains. "i don't own any company. besides, i live outside of US, and they have some legal restrictions on working with non US individuals.but thanks for the help anyway. i guess i'll have to continue without internal debugging capabilities.

author: iMo
author_rank: Super Contributor
timestamp: December 21, 2018, 10:42:41 am
content: A good engineering practice is not to use high clock freqs when you see some issues. Start with 24MHz internal oscillator, and set jtag clock to 100kHz or something like that. Again, do not expect messing with FPGAs is as simple as blinking the led with an arduino..I got similar issues many times, spending weeks debugging a pretty simple stuff, while messing with Actels/Xilinxes/Lattices, and the problem wasalwaysat my side..

author: ilik
author_rank: Contributor
timestamp: December 21, 2018, 11:10:59 am
content: Quote from: imo on December 21, 2018, 10:42:41 ameh... True, True,Quotehmm..., i am using a HW-USBN-2B programmer, there is no way to tell it to lower it's output TCK frequency.

author: iMo
author_rank: Super Contributor
timestamp: December 21, 2018, 11:16:15 am
content: My lesson learned - doalwaysreview the reports after a build, line by line (!!).It happens the system tells you "we have done this and this because of that.." and it happily builds a bitstream for you.A single typo in verilog source (in the inputs/outputs signal "name", for example, and always with missing clock wiring somewhere between the modules) may lead to a situation the system optimizes a part of your design out, whileyou will not get an error message, and the resulting bitstream builds fine.

author: iMo
author_rank: Super Contributor
timestamp: December 21, 2018, 11:29:15 am
content: Quote from: ilik on December 21, 2018, 11:10:59 amOpen the "Radiant Programmer" (from inside the Radiant) and try to set the TCLK divider.

author: ilik
author_rank: Contributor
timestamp: December 21, 2018, 11:55:54 am
content: WOW THANKS MAN! i'm coming from altera and am not familiar with lattice's tips and tricks. one more issue i'd like to mention here:ice40 ultra plus is programmed by SPI, not JTAG. so the programmer boots it up in a SPI mode. my SPI SI,SO and SCK pins come from programmer and enter the fpga. the thing is that SI,SO and SCK 's JTAG equivalent are TDI TDO and TCK which interestingly enough are one and the same pins on the programmer. so inside Radiant software i have targeted soft jtag's TDI TDO and TCK on same pins as the dedicated SI,SO and SCK pins are. datasheet states that after programming ends, and fpga enters a User mode, these programming pins may be used as regular IO pins. that is why i decided to target TDI TDO and TCK to these pins. this way i don't have to relocate programmer's pins after programming, and try to take the analyzer sample straight away.so if we follow the logical thinking:first, these programming pins serve as a dedicated SPI programming pins, i program the device, then the fpga switches to user mode and these pins become connected to soft jtag's TDI TDO and TCK right? (because i connected them this way inside the project). now i try to use reveal analyzer and the error comes. of course i also have TMS signal connected on one of the pins on the fpga, i did not left it out.is there something wrong with this design?

author: iMo
author_rank: Super Contributor
timestamp: December 21, 2018, 12:06:02 pm
content: I can confirm the 4 SPI programming pins are accessible off the userland (I've been using them in my design for writing/reading user data into/from the external SPI bitstream flash, different location than the bitstream, of course).After the UP5k reads the bitstream it "boots itself", then it waits 100clocks, and then it enables the 4 SPI programming pins for the user.I cannot remember whether I used the SPI programming pins for the soft-jtag (look at my wiring above), though.Doublecheck your wiring as the UP5k may work during the reading the bitstream (called "configuration") as the "SPI Slave" or "SPI Master" .BTW, do you use an external SPI bitstream flash memory for storing the bitstream??The iCE40UP5k has not got an internal flash for the bitstream (nor any iCE40xxx)..Anyhow, I would highly recommend you to read the programming/configuration app note - "Technical Note TN1248" carefully

author: ilik
author_rank: Contributor
timestamp: December 21, 2018, 01:39:58 pm
content: QuoteHuH?!document TN1248 on Page 11 tells that:This section applies to iCE40 LP, iCE40 HX, iCE40 Ultra, iCE40 UltraLite and iCE40 UltraPlus devices only.All standard iCE40 devices have an internal NVCM. The NVCM is large enough to program a complete iCE40 device,including initializing all Embedded Block RAM. circuitry.isn't NVCM a Non Voletile Configuration Memory? so it has it -no?

author: iMo
author_rank: Super Contributor
timestamp: December 21, 2018, 02:06:03 pm
content: Yes, NVCM is one time programmable..

author: ilik
author_rank: Contributor
timestamp: December 21, 2018, 02:10:23 pm
content: Quote from: imo on December 21, 2018, 02:06:03 pmoh you mean that. ook ok.

author: iMo
author_rank: Super Contributor
timestamp: December 21, 2018, 02:26:08 pm
content: For a development work you may:1. attach an external 8pin SPI flash (ie. the one UPduino is using) and the iCE boots from it automatically upon reset or power-on (your programmer can program the external SPI flash),2. use an MCU which uploads the bitstream into the iCE (volatile),3. use the programmer to upload the bitstream into the iCE (volatile).When you flash your bitstream into the NVCM, you cannot overwrite it anymore..

author: ilik
author_rank: Contributor
timestamp: December 24, 2018, 06:10:08 am
content: one time programability is fine for me. i have a little different headache, Floor planner.Floorplan view Grouping. i have grouped a whole instance in a single group (called "grp"), anchored it somewhere in the middle of the IC. and it says:WARNING - The group 'grp' constraint has more than 32 comps in the group.This group will not be applied to placement.INFO - LOCATE GROUP 'grp' constraint is removed because it is not placeable.i'm 100% certain that the group is large enough to accommodate all the lcells.can't believe Radiant's floorplan won't group instances that contain more than 32 logic cells in it. i guess a word "comps" mean something else that i'm not aware of.any thoughts what it might be?unfortunately lattice did no release their error/warning explanations document where i could read what does this warning mean and how can i defeat it.

author: kjertil
author_rank: Newbie
timestamp: March 27, 2019, 02:02:14 pm
content: *EDIT*Shortly after posting a rant i think i now understand the problem with Reveal in Radiant using the ICE40 UP5 breakout board:The problem is that the board doesn't connect the FTDI to JTAG, there's only the SPI bus for flash programming.My solution:1. Add the Reveal IP (Inserter)2. Compile (synthesize)3. IMPORTANT -> set the JTAG pins to the pin headers for connection to an external JTAG connection4. Export bit stream file (full compilation)5. Use on board USB FTDI to upload bit stream(as normal)6. Connect yet another ispDownload cable (HW-USBN-2B from Ebay) and start Reveal AnalyserThis solution requires an external JTAG / ispDownload cable / programmer. If anyone knows a short cut to use the on board FTDI chip, please feel free to fill in!If there's no way to use the FTDI chip for JTAG on the ICE40 UP5 break out bard i must say Lattice won't get any of my bonus points today. How ever, they provide very affordable FPGA chips so i guess this is what we have to live with.

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 27, 2019, 04:49:24 pm
content: If anyone's interested, a while ago I ported (and slightly modified I think) a very simple test project for the Upduino 2.0 (RGB controller) for Radiant using VHDL. Maybe that could get some people started.Top (VHDL):Code:library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;library iCE40UP;use iCE40UP.Components.all;--******************************************************************************entity TestRGB isgeneric(nPWMCounterBits : integer := 13);port(RESETn : in std_logic;LED_REDn : out std_logic;LED_GREENn : out std_logic;LED_BLUEn : out std_logic);end TestRGB;--******************************************************************************architecture Behavioral of TestRGB issignal LF_Clock : std_logic;signal nPWM_Cnt : unsigned((nPWMCounterBits - 1) downto 0);signal PWM_Red, PWM_Green, PWM_Blue : std_logic;begin-- On-Chip Oscillator (LSOSC): Low Frequency Oscillator, 10 kHz.LSOSC_1: LSOSCport map (CLKLFEN => '1', CLKLF => LF_Clock, CLKLFPU => '1');-- RGB Driver.RGB_Driver_1 : RGBgeneric map(CURRENT_MODE => "0",RGB0_CURRENT => "0b000001",RGB1_CURRENT => "0b000001",RGB2_CURRENT => "0b000001")port map(RGBLEDEN => RESETn, CURREN => RESETn,RGB0PWM => PWM_Red, RGB1PWM => PWM_Green, RGB2PWM => PWM_Blue,RGB0 => LED_REDn, RGB1 => LED_GREENn, RGB2 => LED_BLUEn);-- PWM Counter.PWM_Counter: process (RESETn, LF_Clock)beginif RESETn = '0' thennPWM_Cnt <= (others => '0');elsif rising_edge(LF_Clock) thennPWM_Cnt <= nPWM_Cnt + 1;end if;end process PWM_Counter;-- PWM Control.PWM_Red <= nPWM_Cnt(nPWMCounterBits - 1) and nPWM_Cnt(nPWMCounterBits - 2);PWM_Green <= nPWM_Cnt(nPWMCounterBits - 1) and (not nPWM_Cnt(nPWMCounterBits - 2));PWM_Blue <= (not nPWM_Cnt(nPWMCounterBits - 1)) and nPWM_Cnt(nPWMCounterBits - 2);end Behavioral;--******************************************************************************.pdc file:Code:ldc_set_location -site {37} [get_ports RESETn]ldc_set_location -site {39} [get_ports LED_REDn]ldc_set_location -site {40} [get_ports LED_GREENn]ldc_set_location -site {41} [get_ports LED_BLUEn]ldc_set_port -iobuf {IO_TYPE=LVCMOS33 PULLMODE=100K} [get_ports RESETn]

author: Ice-Tea
author_rank: Super Contributor
timestamp: April 16, 2019, 06:32:22 pm
content: Code:library iCE40UP;use iCE40UP.Components.all;Had been looking for that.. But it still doesn't work for me. Synplify gives me:ERROR - Tek_impl_1.vm(5829): instantiating unknown module HFOSCLattice LSE:child killed: segmentation violationFail to run synthesis -f Tek_impl_1_lattice.synproj -gui -msgset {C:/Users/Kris Verbeeck/Dropbox/Projects/PAL/Lattice2/Tek/promote.xml}Done: error code 1Tried to include the Ice40Up.vhd file to the project, no dice. What am I missing? How do I make sure the package is included?

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 16, 2019, 11:08:57 pm
content: Don't know why LSE crashes (that's bad), but if you copied and pasted your error message verbatim, then your mistake is that there is no "HFOSC" primitive indeed.You need to take a look at the Radiant's new primitives (can be found in Radiant's help.)The primitive name of the high frequency oscillator is "HSOSC".You don't need to explicitely include the Ice40Up.vhd file in your project.

author: Ice-Tea
author_rank: Super Contributor
timestamp: April 17, 2019, 06:52:56 am
content: I think I'll just go jump of a bridge nowEDIT: to be clear, because I made a typo (HFOSC iso HSOSC). Not because Siliconwizards suggestions were not helpfull.