Learn FPGA from scratch - Page 1
Forum section: electronics / general

author: suzhiming
author_rank: Contributor
timestamp: April 23, 2025, 04:39:58 pm
content: Learn FPGA from scratch,I don't know anything about FPGA.I like these very much. Simulate using the chip EF2L45LG100B.There are Chinese characters in the picture. Please don't report it.video:https://www.bilibili.com/video/BV1TELazsEgs/?share_source=copy_web&vd_source=cc85b342080f282f8270cd6a82b94532fn_sw.zip(128.35 kB - downloaded 72 times.)

author: suzhiming
author_rank: Contributor
timestamp: April 23, 2025, 04:42:59 pm
content: Code:`timescale 1ns/10psmodule fn_sw(a,b,sel,y);inputa;inputb;inputsel;outputy;assigny=sel?(a^b):(a&b);endmodule/******************testbench of fn_sw*************/module fn_sw_tb;rega, b, sel;wirey;fn_sw fn_sw(.a(a),.b(b),.sel(sel),.y(y));initialbegina<=0;b<=0;sel<=0;#10a<=1;b<=0;sel<=0;#10a<=0;b<=1;sel<=0;#10a<=0;b<=0;sel<=1;#10a<=1;b<=0;sel<=1;#10a<=0;b<=1;sel<=1;#10$stop;endendmodule/**************************************************/

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 23, 2025, 04:57:53 pm
content: And what is your specific question about this?If you are at the beginning of working with FPGA's you can find lots of information on the internet about them.The Anlogic IDE does not support simulation directly for as far as I'm aware. To do simulation one needs a tool like for instance Modelsim, which has a free version supplied by Altera/Intel as part of their Quartus IDE suite.In simulation there are levels on which one can simulate. There is logic level, which just takes your verilog or VHDL and simulates the logic in it based on the given test bench. Then there is gate or primitive level, where the low level elements of the FPGA are taken into account into the simulation. And there is full timing simulation, where the timing parameters of the low level elements are also taken into account. For the last two types one needs specific files from the manufacturer to be able to do those simulations. I have not done this for Anlogic FPGA's yet, so no idea on where the needed files are.

author: iMo
author_rank: Super Contributor
timestamp: April 23, 2025, 05:57:06 pm
content: The best way how to learn from scratch with a lot of fun is following, imho:1. buy a cheap fpga board with an fpga chip supported by your development software2. take an existing verilog example, learn how to build it and how to program the bitstream into your fpga3. learn how to edit the verilog sources (there are several files usually) of that example4. make small changes in the example sources (learn to add/remove a functionality, use more i/o, rewire something, etc.), program the fpga and watch the results, step by step..5. goto 4.

author: pcprogrammer
author_rank: Super Contributor
timestamp: April 23, 2025, 06:54:14 pm
content: Quote from: iMo on April 23, 2025, 05:57:06 pmIf you watch the video, you would see that the first two steps are taken care of. The OP has some nice board with a couple of 7 segment displays and push buttons.https://www.bilibili.com/video/BV1TELazsEgs/?share_source=copy_web&vd_source=cc85b342080f282f8270cd6a82b94532I checked it and it seems to be safe. The video itself is not giving information on what the original post really is about.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: April 25, 2025, 09:57:15 pm
content: Does Tang Dynasty support SystemVerilog? If so, consider switching to that rather than the old version of Verilog syntax you're using.

author: zapta
author_rank: Super Contributor
timestamp: April 26, 2025, 03:39:27 am
content: Quote from: suzhiming on April 23, 2025, 04:39:58 pmAccording to the log screenshot you were able to build and upload the design to the FPGA. What do you want to know?

author: suzhiming
author_rank: Contributor
timestamp: May 10, 2025, 03:14:57 pm
content: Draw a development board by hand.an easier eda experience lceda.cn version:v6.5.46

author: suzhiming
author_rank: Contributor
timestamp: May 10, 2025, 03:19:09 pm
content: JPEG

author: suzhiming
author_rank: Contributor
timestamp: May 10, 2025, 03:30:54 pm
content: an intact project

author: zapta
author_rank: Super Contributor
timestamp: May 10, 2025, 04:03:39 pm
content: Is it related to EasyEDA? They seem to use the same logo with a cloud symbol and a switch.https://easyeda.com/images/System-Integration.png

author: zapta
author_rank: Super Contributor
timestamp: May 10, 2025, 04:05:07 pm
content: Quote from: suzhiming on May 10, 2025, 03:14:57 pmIf lceda.cn is a cloud tool, why do they have a 'Download' button?

author: suzhiming
author_rank: Contributor
timestamp: May 11, 2025, 03:10:46 am
content: installation of the collaborative version

author: LovelyA72
author_rank: Regular Contributor
timestamp: May 11, 2025, 11:29:36 pm
content: LCEDA is basically the Chinese version of EasyEDA. LC stands for JLC's LC. They offer an offline build that you can download. I am not sure why it's not an option for the overseas version.

author: LovelyA72
author_rank: Regular Contributor
timestamp: May 11, 2025, 11:30:57 pm
content: He's just wanna share his Anlogic FPGA learning process. He's trying his hardest to use English since he's in China. (fyi I am his friend!)

author: radiolistener
author_rank: Super Contributor
timestamp: May 12, 2025, 03:24:24 am
content: 您可以使用AI聊天机器人来帮助改善翻译并纠正语法错误。如您所见，我可以用中文写作且没有错误，即使我不懂汉字

author: pcprogrammer
author_rank: Super Contributor
timestamp: May 12, 2025, 06:38:58 am
content: Quote from: radiolistener on May 12, 2025, 03:24:24 amTo save others some work:Quote@radiolistener, how can you know for sure that it is correct Chinese without knowing the Chinese characters.

author: zapta
author_rank: Super Contributor
timestamp: May 12, 2025, 01:56:01 pm
content: Quote from: LovelyA72 on May 11, 2025, 11:29:36 pmI tried EasyEDA once or twice for small circuits. It worked but it didn't feel solid like let's say Kicad. If done right, web based engineering applications can be very competitive, for example, Onshape, a commercial web based mechanical design software competes very well with non web applications and feels very 'native'. (Free for makers if anybody wants to try).As for your friend, there are open sources FPGA design tools that were designed for ease of use and students in mind. For example, these two from an academic team in Spainhttps://fpgawars.github.io/:IceStudio - a graphical FPGA design tool where you design by drawing schematics.Apio - a command line FPGA design tool that was inspired by Platformio and provides simple commands such as 'apio build', 'apio sim', 'apio upload'.(I use apio myself and also contributed some code, I recommend it installing from the nightly builds that are available herehttps://github.com/FPGAwars/apio/actions. I use it with Visual Studio Code as an editor but that's a personal choice. Let me know if you have any questions)

author: suzhiming
author_rank: Contributor
timestamp: May 16, 2025, 04:35:14 pm
content: The model library is the highlight of this software.All goods of Lichuang.

author: suzhiming
author_rank: Contributor
timestamp: June 08, 2025, 03:49:44 pm
content: The second counter is finally written, but there are many grammatical errors.

author: tggzzz
author_rank: Super Contributor
timestamp: June 08, 2025, 04:42:57 pm
content: Quote from: pcprogrammer on May 12, 2025, 06:38:58 amVibe translation, of course

author: suzhiming
author_rank: Contributor
timestamp: June 10, 2025, 03:42:50 pm
content: The second counter is ready.The third version is correct.I always make grammar mistakes.

author: zapta
author_rank: Super Contributor
timestamp: June 10, 2025, 05:15:38 pm
content: You have a lot of cycles in that simulation. One way to make the simulations easier to read is to reduce the count constants with a #param.For examplehttps://github.com/FPGAwars/apio-examples/blob/ec7da6db0ed17c9d22abc36a527b2a501e7cada0/examples/icefun/blinky/main.v#L3https://github.com/FPGAwars/apio-examples/blob/ec7da6db0ed17c9d22abc36a527b2a501e7cada0/examples/icefun/blinky/main_tb.v#L14

author: suzhiming
author_rank: Contributor
timestamp: June 12, 2025, 12:11:35 am
content: toggle <= !toggle;This is right.But it's not what I want.

author: suzhiming
author_rank: Contributor
timestamp: June 15, 2025, 04:09:27 pm
content: tri_gentri_gen.zip(0.65 kB - downloaded 12 times.)

author: suzhiming
author_rank: Contributor
timestamp: July 27, 2025, 04:23:43 pm
content: maichong2.zip(1.36 kB - downloaded 14 times.)power =60;

author: suzhiming
author_rank: Contributor
timestamp: July 27, 2025, 04:31:12 pm
content: modelsim simulation.

author: suzhiming
author_rank: Contributor
timestamp: August 01, 2025, 02:59:05 pm
content: 我只是太无聊了，所以我添加了按钮。[/*************脉冲发生器, 100hz_2路互补****************//*************EPM240T100C5N*************************//*************ID:共同学习FPGA************************//*************20250715*****************************///系统时钟100Mhz,设定频率100k,定时时间0-511个脉冲,死区时间32个脉冲;//B+----------------------------------直径1mm*5镀银丝35T// | | | |// s1| s3| S5| s7|// |---L1---| |---L2---|// s2| s4| S6| s8|// | | | |//B-----------------------------------//num |0___________________511|//num |__________50%__________|100%//num |12345|6789a|12345|6789a|//L1 |___0-255___|___________|//L2 |___________|_256-511___|//s1 |¯¯¯¯¯|_________________|//s2 |_____|¯¯¯¯¯|___________|//s3 |_____|¯¯¯¯¯|___________|//s4 |¯¯¯¯¯|_________________|//s5 |___________|¯¯¯¯¯|_____|//s6 |_________________|¯¯¯¯¯|//s7 |___________|¯¯¯¯¯|_____|//s8 |_________________|¯¯¯¯¯|// -|-k_jia //加键// -|-k_jian //减键//`timescale 1ns/10psmodule maichong(clk, //系统时钟100MHz;res, //复位信号,低电平有效;k_jia, //按键加k_jian, //按键减s1, //桥臂1上管;s2, //桥臂1下管;s3, //桥臂2上管;s4, //桥臂2下管;s5, //桥臂3上管;s6, //桥臂3下管;s7, //桥臂4上管;s8 //桥臂4下管;);inputclk;inputres;inputk_jia;inputk_jian;output regs1;output regs2;output regs3;output regs4;output regs5;output regs6;output regs7;output regs8;reg[8:0]num; //计数器;reg[8:0]power; //功率;reg[8:0]k_num; //按键计数器;parametersiqu =16; //死区时间;parameterzuixiao =128; //最小数50%-100%;parameterxiang1 =5; //第一相起始点;parameterxiang2 =260; //第二相起始点;parameterk_max =200; //按键消抖阈值;`defineshu (zuixiao +power)`defineshu_ban ((zuixiao +power) >>1)always@(posedge clk or negedge res)if(~res)begins1 <=0;s2 <=0;s3 <=0;s4 <=0;s5 <=0;s6 <=0;s7 <=0;s8 <=0;num <=0;power <=60;k_num <=0;endelsebegin/**************************************************///计数器num<=num +1;/**************************************************///第一相if((num >xiang1) && (num <(`shu_ban -siqu) ))//前半个周期begins1 <=1;s4 <=1;endelsebegins1 <=0;s4 <=0;endif((num >`shu_ban) && ( num <(`shu -siqu)))//后半个周期begins2 <=1;s3 <=1;endelsebegins2 <=0;s3 <=0;end/**************************************************///第二相if((num >xiang2) && (num <(xiang2 +(`shu_ban -siqu)) ))//前半个周期begins5 <=1;s8 <=1;endelsebegins5 <=0;s8 <=0;endif((num >(xiang2 +(`shu_ban -siqu)) ) && (num <(xiang2 +(`shu -siqu))) )//后半个周期begins6 <=1;s7 <=1;endelsebegins6 <=0;s7 <=0;end/**************************************************///511时更新按键;if(num ==511)beginif(!k_jia || !k_jian)begink_num <=k_num +1;if(k_num ==k_max)beginif(!k_jia && power <100 ) begin power <=power+1; k_num <=0; endelse if(!k_jian && power >40 ) begin power <=power-1; k_num <=0; endendendelsebegink_num <=0;endend/**************************************************/endendmodule/******************testbench of maichong***********/module maichong_tb;regclk, res, k_jia, k_jian;wires1, s2, s3, s4, s5, s6, s7, s8;maichongmaichong(.clk(clk), //系统时钟100MHz;.res(res), //复位信号,低电平有效;.k_jia(k_jia), //按键加.k_jian(k_jian), //按键减.s1(s1), //桥臂1上管;.s2(s2), //桥臂1下管;.s3(s3), //桥臂2上管;.s4(s4), //桥臂2下管;.s5(s5), //桥臂3上管;.s6(s6), //桥臂3下管;.s7(s7), //桥臂4上管;.s8(s8) //桥臂4下管;);initialbeginclk <=0;res <=0;#20 res <=1;#1000 k_jia <=0;#1000 k_jia <=1;#1000 k_jia <=0;#1000 k_jia <=1;#1000 k_jia <=0;#1000 k_jia <=1;#120000 $stop;endalways#5 clk <=~clk;always#10000 k_jia <=~k_jia;endmodule/**************************************************//**************************************************//**************************************************//**************************************************/[随员=1]]

author: suzhiming
author_rank: Contributor
timestamp: August 01, 2025, 03:03:37 pm
content: codmaichong2.zip(1.36 kB - downloaded 7 times.)

author: zapta
author_rank: Super Contributor
timestamp: August 01, 2025, 04:33:08 pm
content: Code:The forums software removed the indentation. Try to use the [#] button (code).begin...end

author: suzhiming
author_rank: Contributor
timestamp: August 19, 2025, 03:40:13 pm
content: pcb_bmp

author: suzhiming
author_rank: Contributor
timestamp: August 19, 2025, 03:41:54 pm
content: pcb_json

author: suzhiming
author_rank: Contributor
timestamp: August 31, 2025, 03:09:18 pm
content: Continuously upgrading

author: suzhiming
author_rank: Contributor
timestamp: September 09, 2025, 03:05:49 am
content: new02

author: suzhiming
author_rank: Contributor
timestamp: September 11, 2025, 05:01:14 pm
content: /*************EPM240T100C5N************************///`timescale 1ns/10psmodule led4(clk,led);input clk;input res;output reg[11:0] led;reg[24:0] num; //numled4.zip(227.44 kB - downloaded 11 times.);//reg[11:0] led; //;always@(posedge clk or negedge res)if(~res)beginnum <=0;endelsebeginif(num ==6_000_000)beginnum <=0;endelsebeginnum <=num +1;endendalways@(posedge clk or negedge res)beginif(~res)beginled <=12'b111_111_111_110;endelsebeginif(num ==6_000_000)beginled <={led[10:0], led };endendendendmodule

author: suzhiming
author_rank: Contributor
timestamp: September 14, 2025, 12:29:16 pm
content: The Second Optimization

author: suzhiming
author_rank: Contributor
timestamp: September 17, 2025, 03:11:09 pm
content: UP,2.2version

author: suzhiming
author_rank: Contributor
timestamp: September 18, 2025, 03:53:05 pm
content: 0-99 display:Code:/*****************数码管****************************//*************EPM240T100C5N************************//*************ID:共同学习FPGA************************//*************20250915*****************************/module led5(inputclk,//系统时钟24MHz;inputres,//复位信号,低电平有效;outputreg led_1,//led_1;outputreg led_2,outputreg[7:0]x_c1,//数码管1,低L;outputreg[7:0]x_c2,//数码管2,低H;outputreg[7:0]x_c3,//数码管3,高L;outputreg[7:0]x_c4//数码管4,高H;);reg[24:0]num;//num计数器;regnum1;//秒脉冲尖;/**************************************************/always@(posedge clk or negedge res)//1.计时if(~res)beginnum<=0;num1<=0;endelsebeginif(num>=12_000_000 -1)beginnum<=0;num1<=1;endelsebeginnum<=num +1;num1<=0;endend/**************************************************/reg[7:0]x_a1;//数码管寄存器0-99;reg[3:0]x_b1;//数码管低;reg[3:0]x_b2;//数码管高;//reg[7:0]x_a2;//数码管高0-99;//reg[7:0]x_b3;//数码管低;//reg[7:0]x_b4;//数码管高;always@(posedge clk or negedge res)//2.显示beginif(~res)beginled_1<=0;led_2<=0;x_a1<=0;x_b1<=0;x_b2<=0;x_c1<='b1111_1001;//1;x_c2<='b1111_1001;//2;x_c3<='b1111_1001;//3;x_c4<='b1111_1001;//4;endelsebeginif(num1)beginled_1<=~led_1;led_2<=~led_2;x_a1<=(x_a1 >=99) ?0 : x_a1 +1;x_b1<=x_a1 % 10;//个位x_b2<=x_a1 / 10;//十位endcase(x_b1)//个位;4'd0: x_c1 = 8'hC0; // 04'd1: x_c1 = 8'hF9; // 14'd2: x_c1 = 8'hA4; // 24'd3: x_c1 = 8'hB0; // 34'd4: x_c1 = 8'h99; // 44'd5: x_c1 = 8'h92; // 54'd6: x_c1 = 8'h82; // 64'd7: x_c1 = 8'hF8; // 74'd8: x_c1 = 8'h80; // 84'd9: x_c1 = 8'h90; // 9default: x_c1 = 8'hff; // 默认不显endcasecase(x_b2)//十位4'd0: x_c2 = 8'hC0; // 04'd1: x_c2 = 8'hF9; // 14'd2: x_c2 = 8'hA4; // 24'd3: x_c2 = 8'hB0; // 34'd4: x_c2 = 8'h99; // 44'd5: x_c2 = 8'h92; // 54'd6: x_c2 = 8'h82; // 64'd7: x_c2 = 8'hF8; // 74'd8: x_c2 = 8'h80; // 84'd9: x_c2 = 8'h90; // 9default: x_c2 = 8'hff; // 默认不显endcaseendend/**************************************************/endmodule/**************************************************/

author: powersupply
author_rank: Contributor
timestamp: September 24, 2025, 06:10:36 am
content: I really fell in love with PSOC design environments. I think I bought all of them. Their IDE has a design palette where preconfigured components can be dragged and dropped onto a schematic, analog and digital designs can be created. They include 16 8 bit aclu’s which can be cascaded for up to 32 bits. You use VHDL to write code for the aclus. The only code you have to write is code to configure and activate each component. One of my favorites is the filter design built in component. You can literally draw your response curve and the component will act accordingly. You have to know digital and analog electronics, but it is such a powerful tool I have designed computer nodes that perform back propagation neural nets that take analog inputs filter appropriately and provide desired output. All in one chip. Very few external components are needed if you so desire. Your multipage schematic is inside the chip. It’s amazing. Infineon purchased PSOC and now focuses on PSOC 6, I prefer the PSOC 5LP. There design boards are about 60 dollars and the IDE is free. You get 159 preconfigured components of various complexity. I’m not affiliated with them but wish I was.

author: suzhiming
author_rank: Contributor
timestamp: October 03, 2025, 02:02:19 pm
content: Code:/*****************数码管****************************//*************EPM240T100C5N************************//*************ID:共同学习FPGA************************//*************20251003*****************************/module led5(inputclk,//系统时钟24MHz;inputres,//复位信号,低电平有效;outputreg led_1,//led_1;outputreg led_2,//led_2;outputreg[7:0]x_c1,//数码管1字模,个位;outputreg[7:0]x_c2,//数码管2字模,十位;outputreg[7:0]x_c3,//数码管3字模,百位;outputreg[7:0]x_c4//数码管4字模,千位;);/**************************************************///1.计时reg[24:0]num;//num计数器;regnum1;//秒脉冲尖;reg[7:0]shi;//时reg[7:0]fen;//分reg[7:0]miao;//秒always@(posedge clk or negedge res)beginif(~res)beginnum<=0;num1<=0;shi<=8'b0001_0010;fen<=0;miao<=0;endelsebeginif(num==1_000_000 -1)beginnum<=0;/**************************************************///时间计算;if(miao[3:0] > 4'd8)beginmiao[3:0]<=0;if(miao[7:4] > 4'd4)beginmiao[7:4]<=0;if(fen[3:0] > 4'd8)beginfen[3:0]<=0;endelsebeginfen[3:0]<=fen[3:0] +1;endendelsebeginmiao[7:4]<=miao[7:4] +1;endendelsebeginmiao[3:0]<=miao[3:0] +1;end/**************************************************/num1<=1;endelsebeginnum<=num +1;num1<=0;endendend/**************************************************//**************************************************///2.显示reg[15:0]x_a1;//十位,个位;reg[15:0]x_a2;//千位,百位;reg[3:0]x_b1;//数码管1数字,个位;reg[3:0]x_b2;//数码管2数字,十位;reg[3:0]x_b3;//数码管3数字,百位;reg[3:0]x_b4;//数码管4数字,千位;/**************************************************/parameterseg_0=8'hc0,//0seg_1=8'hf9,//1seg_2=8'ha4,//2seg_3=8'hb0,//3seg_4=8'h99,//4seg_5=8'h92,//5seg_6=8'h82,//6seg_7=8'hf8,//7seg_8=8'h80,//8seg_9=8'h90,//9seg_A=8'h88,//Aseg_B=8'h83,//Bseg_C=8'hc6,//Cseg_D=8'ha1,//Dseg_E=8'h86,//Eseg_F=8'h8e,//Fseg_off=8'hff;//熄灭/**************************************************/always@(posedge clk or negedge res)beginif(~res)beginx_a1<=0;x_a2<=0;x_b1<=0;x_b2<=0;x_b3<=0;x_b4<=0;x_c1<='b1001_1001;//4;x_c2<='b1011_0000;//3;x_c3<='b1010_0100;//2;x_c4<='b1111_1001;//1;end/**************************************************/elsebeginif(num1)beginled_1<=~led_1;led_2<=~led_2;x_b1<=miao[3:0];x_b2<=miao[7:4];x_b3<=fen[3:0];x_b4<=fen[7:4];/**************************************************/case(x_b1)//个位;0:x_c1=seg_0;// 01:x_c1=seg_1;// 12:x_c1=seg_2;// 23:x_c1=seg_3;// 34:x_c1=seg_4;// 45:x_c1=seg_5;// 56:x_c1=seg_6;// 67:x_c1=seg_7;// 78:x_c1=seg_8;// 89:x_c1=seg_9;// 910:x_c1=seg_A;// A11:x_c1=seg_B;// B12:x_c1=seg_C;// C13:x_c1=seg_D;// D14:x_c1=seg_E;// E15:x_c1=seg_F;// Fdefault:x_c1=seg_off;// 不显endcase/**************************************************/case(x_b2)//十位;0:x_c2=seg_0;// 01:x_c2=seg_1;// 12:x_c2=seg_2;// 23:x_c2=seg_3;// 34:x_c2=seg_4;// 45:x_c2=seg_5;// 56:x_c2=seg_6;// 67:x_c2=seg_7;// 78:x_c2=seg_8;// 89:x_c2=seg_9;// 910:x_c2=seg_A;// A11:x_c2=seg_B;// B12:x_c2=seg_C;// C13:x_c2=seg_D;// D14:x_c2=seg_E;// E15:x_c2=seg_F;// Fdefault:x_c2=seg_off;// 不显endcase/**************************************************/case(x_b3)//百位0:x_c3=seg_0;// 01:x_c3=seg_1;// 12:x_c3=seg_2;// 23:x_c3=seg_3;// 34:x_c3=seg_4;// 45:x_c3=seg_5;// 56:x_c3=seg_6;// 67:x_c3=seg_7;// 78:x_c3=seg_8;// 89:x_c3=seg_9;// 910:x_c3=seg_A;// A11:x_c3=seg_B;// B12:x_c3=seg_C;// C13:x_c3=seg_D;// D14:x_c3=seg_E;// E15:x_c3=seg_F;// Fdefault:x_c3=seg_off;// 不显endcase/**************************************************/case(x_b4)//千位0:x_c4=seg_0;// 01:x_c4=seg_1;// 12:x_c4=seg_2;// 23:x_c4=seg_3;// 34:x_c4=seg_4;// 45:x_c4=seg_5;// 56:x_c4=seg_6;// 67:x_c4=seg_7;// 78:x_c4=seg_8;// 89:x_c4=seg_9;// 910:x_c4=seg_A;// A11:x_c4=seg_B;// B12:x_c4=seg_C;// C13:x_c4=seg_D;// D14:x_c4=seg_E;// E15:x_c4=seg_F;// Fdefault:x_c4=seg_off;// 不显endcaseendendend/**************************************************/endmodule/**************************************************/[attachimg=1]

author: suzhiming
author_rank: Contributor
timestamp: October 04, 2025, 03:38:45 am
content: Improved the clkCode:/**************************************************///时间计算;if(miao[3:0] > 4'd8)beginmiao[3:0]<=0;if(miao[7:4] > 4'd4)beginmiao[7:4] <=0;if(fen[3:0] > 4'd8)beginfen[3:0] <=0;if(fen[7:4] > 4'd4)beginfen[7:4] <=0;if(shi[3:0] > 4'd2)beginshi[3:0] <=0;if(shi[7:4] > 4'd1)beginshi[7:4] <=0;endelsebeginshi[7:4] <=shi[7:4] +1;endendelsebeginshi[3:0] <=shi[3:0] +1;endendelsebeginfen[7:4] <=fen[7:4] +1;endendelsebeginfen[3:0] <=fen[3:0] +1;endendelsebeginmiao[7:4] <=miao[7:4] +1;endendelsebeginmiao[3:0] <=miao[3:0] +1;end/**************************************************/

author: suzhiming
author_rank: Contributor
timestamp: October 04, 2025, 01:56:37 pm
content: he key function has been added, though it's not quite perfect.Code:/*****************数码管****************************//*************EPM240T100C5N************************//*************ID:共同学习FPGA************************//*************20251003*****************************/module led5(inputclk,//系统时钟24MHz;inputres,//复位信号,低电平有效;inputk_jia,//加;inputk_jian,//减;inputk_ent,//确认;outputreg led_1,//led_1;outputreg led_2,//led_2;outputreg[7:0]x_c1,//数码管1字模,个位;outputreg[7:0]x_c2,//数码管2字模,十位;outputreg[7:0]x_c3,//数码管3字模,百位;outputreg[7:0]x_c4//数码管4字模,千位;);/**************************************************///1.计时reg[24:0]num;//num计数器;regnum1;//秒脉冲尖;reg[7:0]shi;//时reg[7:0]fen;//分reg[7:0]miao;//秒always@(posedge clk or negedge res)beginif(~res)beginnum<=0;num1<=0;shi<=8'b0001_0010;fen<=0;miao<=0;endelsebeginif(num==24_000_000 -1)beginnum<=0;/**************************************************///时间计算;if(miao[3:0] >4'd8)beginmiao[3:0] <=4'd0;if(miao[7:4] >4'd4)beginmiao[7:4] <=4'd0;if(fen[3:0] >4'd8)beginfen[3:0] <=4'd0;if(fen[7:4] > 4'd4)beginfen[7:4] <=4'd0;if(shi[3:0] >4'd2)beginshi[3:0] <=4'd0;if(shi[7:4] >4'd1)beginshi[7:4] <=4'd0;endelsebeginshi[7:4] <=shi[7:4] +4'd1;endendelsebeginshi[3:0] <=shi[3:0] +4'd1;endendelsebeginfen[7:4] <=fen[7:4] +4'd1;endendelsebeginfen[3:0] <=fen[3:0] +4'd1;endendelsebeginmiao[7:4] <=miao[7:4] +4'd1;endendelsebeginmiao[3:0] <=miao[3:0] +4'd1;end/**************************************************//**************************************************///按键if(k_jia ==0)//分钟加beginif(fen > 8'd88)beginfen<=8'd0;endelsebeginfen<=fen +8'd1;endendif(k_ent ==0)//分钟减beginif(fen > 8'd89)beginfen<=8'd89;endelsebeginfen<=fen -8'd1;endendif(k_jian ==0)//小时beginif(shi > 8'd34)beginshi<=8'd0;endelsebeginshi<=shi +8'd1;endend/**************************************************/num1<=1;//刷新标志位endelsebeginnum<=num +1;num1<=0;endendend/**************************************************//**************************************************///2.显示reg[15:0]x_a1;//十位,个位;reg[15:0]x_a2;//千位,百位;reg[3:0]x_b1;//数码管1数字,个位;reg[3:0]x_b2;//数码管2数字,十位;reg[3:0]x_b3;//数码管3数字,百位;reg[3:0]x_b4;//数码管4数字,千位;/**************************************************/parameterseg_0=8'hc0,//0seg_1=8'hf9,//1seg_2=8'ha4,//2seg_3=8'hb0,//3seg_4=8'h99,//4seg_5=8'h92,//5seg_6=8'h82,//6seg_7=8'hf8,//7seg_8=8'h80,//8seg_9=8'h90,//9seg_A=8'h88,//Aseg_B=8'h83,//Bseg_C=8'hc6,//Cseg_D=8'ha1,//Dseg_E=8'h86,//Eseg_F=8'h8e,//Fseg_off=8'hff;//熄灭/**************************************************/always@(posedge clk or negedge res)beginif(~res)beginx_a1<=0;x_a2<=0;x_b1<=0;x_b2<=0;x_b3<=0;x_b4<=0;x_c1<='b1001_1001;//4;x_c2<='b1011_0000;//3;x_c3<='b1010_0100;//2;x_c4<='b1111_1001;//1;end/**************************************************/elsebeginif(num1)beginled_1<=~led_1;led_2<=~led_2;x_b1<=fen[3:0];x_b2<=fen[7:4];x_b3<=shi[3:0];x_b4<=shi[7:4];/**************************************************/case(x_b1)//个位;0:x_c1=seg_0;// 01:x_c1=seg_1;// 12:x_c1=seg_2;// 23:x_c1=seg_3;// 34:x_c1=seg_4;// 45:x_c1=seg_5;// 56:x_c1=seg_6;// 67:x_c1=seg_7;// 78:x_c1=seg_8;// 89:x_c1=seg_9;// 910:x_c1=seg_A;// A11:x_c1=seg_B;// B12:x_c1=seg_C;// C13:x_c1=seg_D;// D14:x_c1=seg_E;// E15:x_c1=seg_F;// Fdefault:x_c1=seg_off;// 不显endcase/**************************************************/case(x_b2)//十位;0:x_c2=seg_0;// 01:x_c2=seg_1;// 12:x_c2=seg_2;// 23:x_c2=seg_3;// 34:x_c2=seg_4;// 45:x_c2=seg_5;// 56:x_c2=seg_6;// 67:x_c2=seg_7;// 78:x_c2=seg_8;// 89:x_c2=seg_9;// 910:x_c2=seg_A;// A11:x_c2=seg_B;// B12:x_c2=seg_C;// C13:x_c2=seg_D;// D14:x_c2=seg_E;// E15:x_c2=seg_F;// Fdefault:x_c2=seg_off;// 不显endcase/**************************************************/case(x_b3)//百位0:x_c3=seg_0;// 01:x_c3=seg_1;// 12:x_c3=seg_2;// 23:x_c3=seg_3;// 34:x_c3=seg_4;// 45:x_c3=seg_5;// 56:x_c3=seg_6;// 67:x_c3=seg_7;// 78:x_c3=seg_8;// 89:x_c3=seg_9;// 910:x_c3=seg_A;// A11:x_c3=seg_B;// B12:x_c3=seg_C;// C13:x_c3=seg_D;// D14:x_c3=seg_E;// E15:x_c3=seg_F;// Fdefault:x_c3=seg_off;// 不显endcase/**************************************************/case(x_b4)//千位0:x_c4=seg_0;// 01:x_c4=seg_1;// 12:x_c4=seg_2;// 23:x_c4=seg_3;// 34:x_c4=seg_4;// 45:x_c4=seg_5;// 56:x_c4=seg_6;// 67:x_c4=seg_7;// 78:x_c4=seg_8;// 89:x_c4=seg_9;// 910:x_c4=seg_A;// A11:x_c4=seg_B;// B12:x_c4=seg_C;// C13:x_c4=seg_D;// D14:x_c4=seg_E;// E15:x_c4=seg_F;// Fdefault:x_c4=seg_off;// 不显endcaseendendend/**************************************************/endmodule/**************************************************/

author: suzhiming
author_rank: Contributor
timestamp: October 05, 2025, 01:28:33 pm
content: Improved the key value limitationCode:/*****************数码管****************************//*************EPM240T100C5N************************//*************ID:共同学习FPGA************************//*************20251003*****************************/module led5(inputclk,//系统时钟24MHz;inputres,//复位信号,低电平有效;inputk_jia,//加;inputk_jian,//减;inputk_ent,//确认;outputreg led_1,//led_1;outputreg led_2,//led_2;outputreg[7:0]x_c1,//数码管1字模,个位;outputreg[7:0]x_c2,//数码管2字模,十位;outputreg[7:0]x_c3,//数码管3字模,百位;outputreg[7:0]x_c4//数码管4字模,千位;);/**************************************************///1.计时reg[24:0]num;//num计数器;regnum1;//秒脉冲尖;reg[7:0]shi;//时reg[7:0]fen;//分reg[7:0]miao;//秒always@(posedge clk or negedge res)beginif(~res)beginnum<=0;num1<=0;shi<=8'b0001_0010;fen<=0;miao<=0;endelsebeginif(num==24_000_000 -1)beginnum<=0;/**************************************************///时间计算;if(miao[3:0] >4'd8)beginmiao[3:0] <=4'd0;if(miao[7:4] >4'd4)beginmiao[7:4] <=4'd0;if(fen[3:0] >4'd8)beginfen[3:0] <=4'd0;if(fen[7:4] > 4'd4)beginfen[7:4] <=4'd0;if(shi[3:0] >4'd2)beginshi[3:0] <=4'd0;if(shi[7:4] >4'd1)beginshi[7:4] <=4'd0;endelsebeginshi[7:4] <=shi[7:4] +4'd1;endendelsebeginshi[3:0] <=shi[3:0] +4'd1;endendelsebeginfen[7:4] <=fen[7:4] +4'd1;endendelsebeginfen[3:0] <=fen[3:0] +4'd1;endendelsebeginmiao[7:4] <=miao[7:4] +4'd1;endendelsebeginmiao[3:0] <=miao[3:0] +4'd1;end/**************************************************//**************************************************///按键if(k_jia ==0)//分钟加beginif(fen > 8'd88)//88是58分beginfen<=8'd0;endelsebeginif(fen[3:0] >4'd8)//当个位为9时beginfen[3:0] <=4'd0;fen[7:4] <=fen[7:4] +4'd1;endelsebeginfen<=fen +8'd1;endendendif(k_ent ==0)//分钟减beginif(fen > 8'd89 ||fen ==8'd0)beginfen<=8'd89;//89是59分endelsebeginif(fen[3:0] ==4'd0)//个位是0beginfen<={fen[7:4] -4'd1,4'd9};endelsebeginfen<=fen -8'd1;endendendif(k_jian ==0)//小时加beginif(shi > 8'd34)beginshi<=8'd0;endelsebegin//shi<=shi +8'd1;if(shi[3:0] == 4'd9)//9进位beginshi <={shi[7:4] + 4'd1,4'd0};endelsebeginshi<={shi[7:4], shi[3:0] + 4'd1};endendend/**************************************************/num1<=1;//刷新标志位endelsebeginnum<=num +1;num1<=0;endendend/**************************************************//**************************************************///2.显示reg[15:0]x_a1;//十位,个位;reg[15:0]x_a2;//千位,百位;reg[3:0]x_b1;//数码管1数字,个位;reg[3:0]x_b2;//数码管2数字,十位;reg[3:0]x_b3;//数码管3数字,百位;reg[3:0]x_b4;//数码管4数字,千位;/**************************************************/parameterseg_0=8'hc0,//0seg_1=8'hf9,//1seg_2=8'ha4,//2seg_3=8'hb0,//3seg_4=8'h99,//4seg_5=8'h92,//5seg_6=8'h82,//6seg_7=8'hf8,//7seg_8=8'h80,//8seg_9=8'h90,//9seg_A=8'h88,//Aseg_B=8'h83,//Bseg_C=8'hc6,//Cseg_D=8'ha1,//Dseg_E=8'h86,//Eseg_F=8'h8e,//Fseg_off=8'hff;//熄灭/**************************************************/always@(posedge clk or negedge res)beginif(~res)beginx_a1<=0;x_a2<=0;x_b1<=0;x_b2<=0;x_b3<=0;x_b4<=0;x_c1<='b1001_1001;//4;x_c2<='b1011_0000;//3;x_c3<='b1010_0100;//2;x_c4<='b1111_1001;//1;end/**************************************************/elsebeginif(num1)beginled_1<=~led_1;led_2<=~led_2;x_b1<=fen[3:0];x_b2<=fen[7:4];x_b3<=shi[3:0];x_b4<=shi[7:4];/**************************************************/case(x_b1)//个位;0:x_c1=seg_0;// 01:x_c1=seg_1;// 12:x_c1=seg_2;// 23:x_c1=seg_3;// 34:x_c1=seg_4;// 45:x_c1=seg_5;// 56:x_c1=seg_6;// 67:x_c1=seg_7;// 78:x_c1=seg_8;// 89:x_c1=seg_9;// 910:x_c1=seg_A;// A11:x_c1=seg_B;// B12:x_c1=seg_C;// C13:x_c1=seg_D;// D14:x_c1=seg_E;// E15:x_c1=seg_F;// Fdefault:x_c1=seg_off;// 不显endcase/**************************************************/case(x_b2)//十位;0:x_c2=seg_0;// 01:x_c2=seg_1;// 12:x_c2=seg_2;// 23:x_c2=seg_3;// 34:x_c2=seg_4;// 45:x_c2=seg_5;// 56:x_c2=seg_6;// 67:x_c2=seg_7;// 78:x_c2=seg_8;// 89:x_c2=seg_9;// 910:x_c2=seg_A;// A11:x_c2=seg_B;// B12:x_c2=seg_C;// C13:x_c2=seg_D;// D14:x_c2=seg_E;// E15:x_c2=seg_F;// Fdefault:x_c2=seg_off;// 不显endcase/**************************************************/case(x_b3)//百位0:x_c3=seg_0;// 01:x_c3=seg_1;// 12:x_c3=seg_2;// 23:x_c3=seg_3;// 34:x_c3=seg_4;// 45:x_c3=seg_5;// 56:x_c3=seg_6;// 67:x_c3=seg_7;// 78:x_c3=seg_8;// 89:x_c3=seg_9;// 910:x_c3=seg_A;// A11:x_c3=seg_B;// B12:x_c3=seg_C;// C13:x_c3=seg_D;// D14:x_c3=seg_E;// E15:x_c3=seg_F;// Fdefault:x_c3=seg_off;// 不显endcase/**************************************************/case(x_b4)//千位0:x_c4=seg_0;// 01:x_c4=seg_1;// 12:x_c4=seg_2;// 23:x_c4=seg_3;// 34:x_c4=seg_4;// 45:x_c4=seg_5;// 56:x_c4=seg_6;// 67:x_c4=seg_7;// 78:x_c4=seg_8;// 89:x_c4=seg_9;// 910:x_c4=seg_A;// A11:x_c4=seg_B;// B12:x_c4=seg_C;// C13:x_c4=seg_D;// D14:x_c4=seg_E;// E15:x_c4=seg_F;// Fdefault:x_c4=seg_off;// 不显endcaseendendend/**************************************************/endmodule/**************************************************/[attachimg=1]

author: bson
author_rank: Unknown
timestamp: October 06, 2025, 08:05:01 pm
content: Quote from: suzhiming on October 04, 2025, 03:38:45 amI'd suggest learning to use 'generate' and then rethink how you keep state.

author: suzhiming
author_rank: Contributor
timestamp: October 09, 2025, 03:46:09 am
content: Verilog is not executed line by line like C language. Currently, there are many bugs, so the code has been rewritten.Code:if(miao[7:4] == 8'd5 && miao[3:0] == 4'd9)beginmiao<= 8'd0;fen<= fen +8'd1;endelse if(miao[3:0] == 4'd9)beginmiao <= {miao[7:4] + 4'd1,4'd0};endelsebeginmiao<= miao + 8'd1;end

author: suzhiming
author_rank: Contributor
timestamp: October 09, 2025, 03:47:02 pm
content: It's better to write the program this way.Code:/**************************************************///秒进位if(miao[7:4] == 4'd5 && miao[3:0] == 4'd9)beginmiao<= 8'd0;/**************************************************///分进位if(fen[7:4] == 4'd5 && fen[3:0] == 4'd9)beginfen<= 8'd0;/**************************************************///时进位if(shi[7:4] == 4'd2 && shi[3:0] == 4'd4)beginshi<=8'd0;endelse if(shi[3:0] == 4'd9 )beginshi <={shi[7:4] +4'd1,shi[3:0] <= 4'd0};endelsebeginshi<= shi +8'd1;end/**************************************************/endelse if(fen[3:0] == 4'd9)beginfen <={fen[7:4] + 4'd1,4'd0};endelsebeginfen<= fen +8'd1;end/**************************************************/endelse if(miao[3:0] == 4'd9)beginmiao <= {miao[7:4] + 4'd1,4'd0};endelsebeginmiao<= miao + 8'd1;end/**************************************************/endendend

author: suzhiming
author_rank: Contributor
timestamp: October 10, 2025, 02:21:24 pm
content: That's better, using the bit concatenation operation.Code:/****************时钟*******************************//****************EPM240T100C5N*********************//****************ID:共同学习FPGA********************//****************20251010**************************/module shizhong(inputclk,//系统时钟24MHz;inputres,//复位信号,低电平有效;inputk_jia,//加;inputk_jian,//减;inputk_ent,//确认;outputreg led_1,//led_1;outputreg led_2,//led_2;outputreg[7:0]x_c1,//数码管1字模,个位;outputreg[7:0]x_c2,//数码管2字模,十位;outputreg[7:0]x_c3,//数码管3字模,百位;outputreg[7:0]x_c4//数码管4字模,千位;);/**************************************************///1.分频;reg[24:0]num;//num计数器;regnum1;//秒脉冲;regnum2;//按键脉冲;always@(posedge clk or negedge res)beginif(~res)beginnum<=0;num1<=0;num2<=0;led_1<=0;led_2<=0;endelsebeginif(num ==24_000_000 -1)beginnum<=0;num1<=1;led_1<= ~led_1;led_2<= ~led_2;endelsebeginnum<=num +1;if(num ==10)beginnum2<=1;endelsebeginnum2<=0;endnum1<=0;endendend/**************************************************///2.计时;reg[7:0]shi;//时reg[7:0]fen;//分reg[7:0]miao;//秒always@(posedge clk or negedge res)beginif(~res)beginshi<= 8'b0001_0010;//12:00fen<= 0;miao<= 0;endelsebeginif(num1)begin/**************************************************///秒进位if(miao[7:4] == 4'd5 && miao[3:0] == 4'd9)beginmiao<= 8'd0;/**************************************************///分进位if(fen[7:4] == 4'd5 && fen[3:0] == 4'd9)beginfen<= 8'd0;/**************************************************///时进位if(shi[7:4] == 4'd2 && shi[3:0] == 4'd4)beginshi<=8'd0;endelse if(shi[3:0] == 4'd9 )beginshi <={shi[7:4] +4'd1,shi[3:0] <= 4'd0};endelsebeginshi<= shi +8'd1;end/**************************************************/endelse if(fen[3:0] == 4'd9)beginfen <={fen[7:4] + 4'd1,4'd0};endelsebeginfen<= fen +8'd1;end/**************************************************/endelse if(miao[3:0] == 4'd9)beginmiao <= {miao[7:4] + 4'd1,4'd0};endelsebeginmiao<= miao + 8'd1;end/**************************************************/end/**************************************************///按键if(num2 == 1)beginif(k_jian == 0)//小时加beginif((shi[7:4] == 4'd2) && (shi[3:0] == 4'd4))//24小时beginshi <= 8'd0;endelse if(shi[3:0] == 8'd9)beginshi <= {shi[7:4] + 4'd1,4'd0};endelsebeginshi<= shi + 8'd1;endend/**************************************************/if(k_jia == 0)//分钟加beginif((fen[7:4] == 4'd5) && (fen[3:0] == 4'd9))//59分钟beginfen <= 8'd0;//shi <= shi + 4'd1;endelse if(fen[3:0] == 8'd9)beginfen <= {fen[7:4] + 4'd1,4'd0};endelsebeginfen <=fen + 8'd1;endend/**************************************************/if(k_ent == 0)//分钟减beginif((fen[7:4] == 4'd0) && (fen[3:0] == 4'd0))beginfen <= {4'd5,4'd9};endelse if((fen[7:4] > 4'd0) && (fen[3:0] == 4'd0))beginfen <= {fen[7:4] - 4'd1,4'd9};endelsebeginfen <=fen - 8'd1;endend/**************************************************/end/**************************************************/endend/**************************************************///3.显示;reg[3:0]x_b1;//数码管1数字,个位;reg[3:0]x_b2;//数码管2数字,十位;reg[3:0]x_b3;//数码管3数字,百位;reg[3:0]x_b4;//数码管4数字,千位;/**************************************************/parameterseg_0=8'hc0,//0seg_1=8'hf9,//1seg_2=8'ha4,//2seg_3=8'hb0,//3seg_4=8'h99,//4seg_5=8'h92,//5seg_6=8'h82,//6seg_7=8'hf8,//7seg_8=8'h80,//8seg_9=8'h90,//9seg_A=8'h88,//Aseg_B=8'h83,//Bseg_C=8'hc6,//Cseg_D=8'ha1,//Dseg_E=8'h86,//Eseg_F=8'h8e,//Fseg_off=8'hff;//熄灭/**************************************************/always@(posedge clk or negedge res)beginif(~res)beginx_b1<=4'd0;x_b2<=4'd0;x_b3<=4'd0;x_b4<=4'd0;x_c1<='b1001_1001;//4;x_c2<='b1011_0000;//3;x_c3<='b1010_0100;//2;x_c4<='b1111_1001;//1;endelsebeginif(num1)//秒脉冲beginx_b1<=fen[3:0];x_b2<=fen[7:4];x_b3<=shi[3:0];x_b4<=shi[7:4];/**************************************************/case(x_b1)//个位;0:x_c1=seg_0;// 01:x_c1=seg_1;// 12:x_c1=seg_2;// 23:x_c1=seg_3;// 34:x_c1=seg_4;// 45:x_c1=seg_5;// 56:x_c1=seg_6;// 67:x_c1=seg_7;// 78:x_c1=seg_8;// 89:x_c1=seg_9;// 910:x_c1=seg_A;// A11:x_c1=seg_B;// B12:x_c1=seg_C;// C13:x_c1=seg_D;// D14:x_c1=seg_E;// E15:x_c1=seg_F;// Fdefault:x_c1=seg_off;// 不显endcase/**************************************************/case(x_b2)//十位;0:x_c2=seg_0;// 01:x_c2=seg_1;// 12:x_c2=seg_2;// 23:x_c2=seg_3;// 34:x_c2=seg_4;// 45:x_c2=seg_5;// 56:x_c2=seg_6;// 67:x_c2=seg_7;// 78:x_c2=seg_8;// 89:x_c2=seg_9;// 910:x_c2=seg_A;// A11:x_c2=seg_B;// B12:x_c2=seg_C;// C13:x_c2=seg_D;// D14:x_c2=seg_E;// E15:x_c2=seg_F;// Fdefault:x_c2=seg_off;// 不显endcase/**************************************************/case(x_b3)//百位0:x_c3=seg_0;// 01:x_c3=seg_1;// 12:x_c3=seg_2;// 23:x_c3=seg_3;// 34:x_c3=seg_4;// 45:x_c3=seg_5;// 56:x_c3=seg_6;// 67:x_c3=seg_7;// 78:x_c3=seg_8;// 89:x_c3=seg_9;// 910:x_c3=seg_A;// A11:x_c3=seg_B;// B12:x_c3=seg_C;// C13:x_c3=seg_D;// D14:x_c3=seg_E;// E15:x_c3=seg_F;// Fdefault:x_c3=seg_off;// 不显endcase/**************************************************/case(x_b4)//千位0:x_c4=seg_0;// 01:x_c4=seg_1;// 12:x_c4=seg_2;// 23:x_c4=seg_3;// 34:x_c4=seg_4;// 45:x_c4=seg_5;// 56:x_c4=seg_6;// 67:x_c4=seg_7;// 78:x_c4=seg_8;// 89:x_c4=seg_9;// 910:x_c4=seg_A;// A11:x_c4=seg_B;// B12:x_c4=seg_C;// C13:x_c4=seg_D;// D14:x_c4=seg_E;// E15:x_c4=seg_F;// Fdefault:x_c4=seg_off;// 不显endcase/**************************************************/endendend/**************************************************/endmodule/**************************************************/