Accessing PCI bus on a computer - how? - Page 1
Forum section: electronics / projects

author: Yansi
author_rank: Super Contributor
timestamp: January 03, 2015, 01:23:09 am
content: HiI have recently come across this very interesting project:http://elm-chan.org/works/pci/report_e.htmlThe HW side of the PCI bus looks straightforward and is relatively well described through the internet. But I have found very difficult to find any information, how to access the PCI bus. Or to be exact here - how did he possibly made read or write transactions with his diy PIO card?I am still amazed by this project and definitely want to try something similar. Only fit all the logic inside signle PLD chip.But how to communicate with the card? Possibly also under Windows environment?I have already found some fragmentary info, how to do that. I have discovered the $0CF8 and $0CFC IO mapped registers, and stuff like so... This possibly shoud be done in DOS or other direct port access granting system... The really big question is, how to deal it under windows.It would be nice, if such thing like "libusb" existed for the PCI bus. Or does it?Thank you for your opinions and help,Yansi

author: nctnico
author_rank: Super Contributor
timestamp: January 03, 2015, 01:32:09 am
content: A good start is a program called PCItree (http://www.pcitree.de/)I have no idea if there is an easy way to create some generic Windows driver for a PCI device...

author: Yansi
author_rank: Super Contributor
timestamp: January 03, 2015, 02:55:01 am
content: Thank you for that advice. I have sucessfully installed the PCItree. Looks useful for PnP debugging. But I'd like to start with something simple (I know, PCI developers now facepalming and fainting), just forget the PCI's PnP capability for a while and try something like elm-chan did. Cruel, but one must proceed little steps to make big achievements.I will build a separate computer just for this purpose - heaps of old computer crap laying in my garage, so no worries of possible destruction of some mainboards when things might go horribly wrong.I have just spoken with my friend, and wow, he has got his own tool possibly capable of bombarding the PCI with any transaction possible. And the bonus is, if I will need to add any functionality, he possibly could help me programming that in. Just go on his site and check the SMB.EXE tool - looks veeeery useful!http://rayer.g6.cz/programm/programe.htm#SMBSo at least one good thing - we have debugging tools on the software side available. So one variable is out, we can start developing the hardware part... bud wait.. when? Thats is the question... But stay tuned, i will share. I will possibly use EPM240 CPLD with some level shifters and a bunch of IOs such as LEDs to play with. Nothing fancy.

author: free_electron
author_rank: Super Contributor
timestamp: January 03, 2015, 03:01:36 am
content: There is a similar project out thhere made by a german company, they use lattice cpld. Keep in. Ind that neither that one, or the one you found is pci compliant. The config registers are missing and they dont play well with dma or multimaster environments.If you really want to work on pci : get the altera max-Ii devkit with the pci card.They give you the real pci core and a proper driver that handles all modes.It can run in reasonably small max-ii cpld and it is a full implementation.The source is documented

author: Yansi
author_rank: Super Contributor
timestamp: January 03, 2015, 03:23:07 am
content: What exactly do u mean by "reasonably small"? I have downloadded some lattice application note for their CPLDs, where they have made a PCI target controller on their CPLD, utilizing 120 macrocells. That looks reasonable I think. I'd like to use EPM240, so twice that amount and my funny implementation might fit in there fine.I havent read that lattice appnote much in detail, but the implementation was meant with a help of external MCU, the CPLD worked only as an PCI to some sort of asynchronous parallel bus. I like that the PCI has those "busy wait" signalling and you can possibly use like a stndard "slow" MCU for handling that communication... maybe, if I got that right. I havent searched yet for how much time the target can hold the bus, so how much time it has to eat a single transaction.I am not a company and possibly never be, too much stupid badass for doing so. So I will not try to make PCI compliant target - because it is almost impossible for a beginner like me. But I will try my best.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 03, 2015, 05:42:26 am
content: Isn't this kind of irrelevant now? Meaning: if you're looking to plug in custom hardware to a new consumer grade computer, you are unlikely to have PCI slots anymore. If you're buying old hardware, you might as well find an old Pentium II or something like that, with ISA slot(s), and a copy of Win95 or 98. Assuming the low bandwidth of ISA isn't a problem.But then, you might as well write it for USB, since Full Speed handles pretty well as much bandwidth as ISA. High Speed offers comparable bandwidth to PCI (at the expense of near-real-time access -- have fun buffering, eh?).FWIW,PCI-eis a bitch: proprietary (you can't write a bridge yourself, you must pay the licensing fee!), serial, high speed, and very high latency (bus cycles can take microseconds -- which is fantastic if you're unloading megs or gigs at a time, but ridiculous if your naive application need lots of small accesses).On the plus side, all the major FPGA vendors offer chips with hard cores integrated (they absorbed the license cost and bridge logic themselves, passed on as amortized cost in the chips), so you only have to deal with their interface side in VHDL, which is probably where you'll be beginning your project anyway. And that gives you plenty of opportunity to fix up the data for packetized transmission -- buffering, time stamping, preprocessing, etc.Tim

author: Rasz
author_rank: Super Contributor
timestamp: January 03, 2015, 08:42:37 am
content: yay, neat topicPCI is 33MHz at 32bits = 132MB/sproblem is accessing your hardware, you need custom OS specific driversAfaik you talk to your hardware over the busmaster, there are no IO ports where your hardware lands automagically like in ISA daysThis is the best software for experimentation:http://jacky5488.myweb.hinet.net/you can touch every bit of hardware, even on modern PCs on modern OS. Whats more its scriptable, you can write .bat script to flip bytes(peek/poke). For example this tool is used by a set of scripts to overclock wide selection of otherwise un_overclockable laptopshttp://forum.techinferno.com/general-notebook-discussions/2755-setpll-pll-overclocking-tool.htmlagain, biggest problem is driver, setting up your device and so onNow to the good part, attractive alternative is IDE:PIO0 1.6MHz at 16bits = 3.2MB/s...UDMA100 IDE device uses 25MHz DDR at 16bits = 100MB/sUDMA133 IDE device uses 33MHz DDR at 16bits = 132MB/shttp://webcache.googleusercontent.com/search?q=cache:cJqVlPU_T7cJ:www.ybet.be/en-hardware-1-10/hard-disk-ide.htmhttp://www.retroleum.co.uk/ide_interface.htmlhttp://www.students.tut.fi/~leinone3/ide/ata-r32.txtdifference from PCI:+no drivers+SUPER simple to interface in software+hotplug+no need for fast design, can go as slow as 1.6MHz (pio0)+$4 PATA-SATA converters are a way of making this design future proof+$4 PATA-USB 2.0 converters are a way of making this design future proof and mobile+$15 PATA-USB 3.0 converters are a way of making this design future proof, mobile and fast-cant signal / initiate data transfer from device, needs poolingBasically you get 1/2 speed of USB 3.0 (Cyprezz USB FX3 tops out around 250-300MB/s), but you dont need no stinking drivers.Trick is to make your device emulate a small harddrive, it requires implementing few essential ATA commands, data exchange between your program and your device will simply look like writing/reading a file, standard IO every OS on the planet can handle without drivers/privilege escalation/certificates/etc.I know of two projects that used IDE bus to a lesser extend, both programmers.http://www.loet.de/flasher_en.htmlhttps://web.archive.org/web/20130729052750/http://eds.dyndns.org/~ircjunk/tutorials/elex/ata2isp/main.htmlthe second one uses brute force method of simply treating IO mapped IDE port as IO mapped LPT port under linux, all it takes is this one liner:Code:modprobe parport_pc io=0x170 irq=none,none,noneBoth are pretty old and simple. Nowadays it should be easy to just grab $10 STM32 F4 and force it into pretending its a hard drive with one file on FAT16 partition.

author: Yansi
author_rank: Super Contributor
timestamp: January 03, 2015, 12:14:41 pm
content: Thank you for your replies, but the question was different, than what bus is futureproof. If I wanted to make a IDE device or USB one, I will ask that, not PCI. Please stop bitching around, if you'd like to help with PCI, please do it, I will appreciate your help very much, because there are very few people with such experience.FAQ Summaryfor others:1) I will not make USB device here. I want PCI. For whatever reason...2) I am not interested in interfacing IDE.3) I will not make any attempts trying to build PCIe bitch.4) I will not play with ISA bus, that is pretty much obsolete, unlike PCI which all computers I target have that inside. And those which haven't, bad luck for them.5) I am not designing commercial product, nor will I sell it.6) I simply don't care how futureproof PCI is or isn't, I will just try that for fun.Rasz, PCI is also 66MHz at 64 bits, so four times that. But I am not interested in that anyway. I like 32bits and 33 megs.I am starting to think, that there is no need for OS specific driver. My friends SMB tool uses no custom OS drivers, yet it can access the PCI bus. But I haven't consulted with him all the things about PCI accesses yet. Will be interesting.But those IDE projects - I will check them too, curious to see, what they've done with that. Thank you for posting the links.T3sl4co1l: Isn't making teslacoils irrelevant too? One buld teslacoils, other one builds PCI cards. Whats the difference? Everyone has a hobby. So why to bitch around that? And also again no for USB. I haven't asked that. I want to try something different, something which simply don't do every embedded designer on the planet.I will not stick with hardcore in an FPGA. I want make my own core. If the whole PCI target could be fit inside cheap relatively small CPLD, why the hell on earth would I use FPGA, for such a fun project?If you don't like projects like this, you can tell me, I will stop developing this thread any further, we (or just you) can stick with arduino, if it is more suitable for public forum or is mor futureproof. I know my ideas are dumb and not mainstream, if you don't like em, I'll stop that.And there is a small note from latticesemi:http://www.eetindia.co.in/ARTICLES/2002DEC/A/2002DEC20_PL_AN01.PDF?SOURCES=DOWNLOADfree_electron: This might be the case the german company uses, isn't it? Looks like we could possibly port that to altera's CPLD, because I like them and have them available in my shack.

author: free_electron
author_rank: Super Contributor
timestamp: January 03, 2015, 02:14:57 pm
content: Keep in mind that the lattice design will respond to any and all pci transaction ,you will need to add a decoder to only react when the data is for you /requested from you.It's a good starting point. Check out alteras implementation. They have a nice pci card with the cpld on it , an lcd display and a byteblaster and so e ram and a bunch of io pins.You get complete sourcecode for the pci engine and the card is properly layed out , terminated and length tuned. At least you wont be chasing misery with improper levels and such ...

author: Yansi
author_rank: Super Contributor
timestamp: January 03, 2015, 03:30:00 pm
content: Sure, I give em $1000 for that. Holy fuck.That altera's dev kit I don't like even the smallest bit. It is exactly a presentation of how things can be done extremely expensive. Sure enough, I am not interested in making anything like that. And I am not interested in buying any kits.I wish I haven't mentioned this PCI project here. One only gets thousand bitches how he is doing obsolete stuff, two thousand advices to buy overpriced kits or reuse someone else's work with almost copypaste. I thought we were on diy forum, where people make custom stuff. But it seems, that this era has completely gone and was replaced by making all things with arduino by el stupido libraries for anything.So please forget that I've mentioned PCI experimenting here. Going to study it myself the hard way. Better stop at the best, than making another useless thread full of bitchin' how obsolete and dumb stuff is being made, when someone actually tries to learn something, rather than use ready-made stuff.I might have born to the wrong age.

author: jahonen
author_rank: Super Contributor
timestamp: January 03, 2015, 03:52:21 pm
content: Maybe this will help a bit:http://www.fpga4fun.com/PCI.htmlRegards,Janne

author: amyk
author_rank: Super Contributor
timestamp: January 03, 2015, 04:00:59 pm
content: If you can write a Windows kernel driver you can access your card without PnP, just read/write to the right memory/IO ranges directly from it. The ports CF8/CFC are for configuration access, if you don't plan on implementing configuration-space you don't need to worry about them.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 03, 2015, 04:06:28 pm
content: Quote from: Yansi on January 03, 2015, 03:30:00 pmWell gee, if you snap every time someone offersfreeadvice, it's no wonder you're just pissing on everything...If you had calmly explained the nature of your interest, I and probably others would've been happy to share our knowledge of the subject, practical or theoretical... but now I see no reason to continue this thread...Have a good day,Tim

author: nctnico
author_rank: Super Contributor
timestamp: January 03, 2015, 04:36:00 pm
content: Quote from: Yansi on January 03, 2015, 12:14:41 pmOne of the things to keep in mind is that PCI transfers are quite slow. IIRC 5 to 8 clock cycles for one transfer. With short (one 32 bit word) transfers the bandwidth of 132MB/s sinks to 20MB/s or so.

author: mikerj
author_rank: Super Contributor
timestamp: January 03, 2015, 04:48:52 pm
content: Quote from: Yansi on January 03, 2015, 03:30:00 pmIf you are going to cry like a girl then I suspect everyone else wishes you hadn't mentioned it either.You asked for free advice, free advice was given. What is your problem?

author: Yansi
author_rank: Super Contributor
timestamp: January 03, 2015, 05:05:45 pm
content: jahonen, thank you, will help.amyk: fake cfg space could be implemented for easy HW testing. Simple LED output could show what is written there. Simple, dumb, but would made me better mood if it would work.T3sl4co1l: Free advices like purchasing $1000 kit with FPGA, or advice like "fuck you PCI is obsolete, go USB" are maybe free, but absolutely pointless. Sure there is no need to continue this. My interrests were described in the first post, with a simple question (demanding rather complex answer). You haven't answered it by any means, propably even haven't read that. So have a nice day too and sorry, that I've asked.nctnico: Elm-chan like PCI target wouldn't need much bandwidth.But good point.mikerj: My problem is with everyone which bitches around things I haven't asked for. Question was how to send data to elmchan-like HW, not how or with what make the hardware. Nor wasn't the question about PCI futureproofness or irelevantness.

author: free_electron
author_rank: Super Contributor
timestamp: January 03, 2015, 09:48:45 pm
content: Quote from: Yansi on January 03, 2015, 03:30:00 pm162$ ... it ain't 1000$. And if you are a student it can be got cheaper than that.http://www.digikey.com/product-detail/en/DK-MAXII-1270N/544-2380-ND/1596439Quoteyou are. we live in an age where everything evolves so quickly that all you can do is take existing building blocks and slap em together. that is why we need a billion transistors to turn on an led now ... there is software bloat and silicon bloat...and then there is the economical aspect as well. material stuff no longer holds any 'value'. one square millimeter can hold a single power diode , or it can hold a hundred thousand transistors doing some very complex function. it will be sold at the price per square millimeter of silicon. that is why i left the semiconductor industry. there is no more money to be made to reinvest in getting some real development done. budgets are cut and we have evolved to a slap-it-together world.

author: Yansi
author_rank: Super Contributor
timestamp: January 03, 2015, 10:56:23 pm
content: I've found some PCI card development kit on alteras pages, that was for around $900. Was a qick search, took first what it puked. But this one seems different. But $162 is also too much for such a thing. I am sure, it can be done much cheaper. As for a hobbyist, development time doesn't matter much. If I spend a few days making the board for that, it is worth it. And it will be well under $20 and probably satisfies the requirements.I've already begun to develop a "PCI board", so we will see, what will it do. Some people actually helped me a lot, so thanx for them and sorry for others, that I do not (and will not) make things by slapping'em'together. It is simply not my style.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 03, 2015, 11:20:26 pm
content: Here's my free advice: get a PCI POST card on eBay, at least you'll be able to figure out if your garage computers still have working PCI buses in the first place. No sense in plugging in a card into a PC with a burnt bus, eh?http://www.ebay.ca/itm/PCI-Analyzer-POST-Diagnostic-Test-Card-FOR-PC-Computer-/351270676139?pt=US_Motherboard_Diagnostic_Cards&hash=item51c95d26aband it looks like it could act as a basic logic analyzer too.Also PCI reference books are quite cheap on eBay.

author: Yansi
author_rank: Super Contributor
timestamp: January 04, 2015, 12:18:01 am
content: A lot of garbagge in my garrage, but I remember quite a few computers actually working, no need to test PCIs. By garbagge I haven't meant burnt computers, but ooooold stuff from 286s to something like Pentium III or Celerons. Most of them were working, when I've put them there. But true, murphy is an asshole.PCI reference books, huh? What is that? I'll check that out. Seems useful to have one. Thank you for ur advice.//PCI board 50% finished//

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 04, 2015, 01:49:43 am
content: Quote from: Yansi on January 04, 2015, 12:18:01 amWell you can get a lot of PCI reference info on wiki but when a book is 5$, it's fun to have, check your local university/public library as well.http://www.ebay.ca/itm/PCI-System-Architecture-1995-by-Shanley-Tom-Anderson-Don-0201409933-/351266763163?pt=US_Fiction_Books&hash=item51c921719bI think the POST card can also help to validate what's going on on the bus. Can save time if you are working with two unknowns at the same time.

author: Yansi
author_rank: Super Contributor
timestamp: January 04, 2015, 03:10:30 pm
content: Thanx for everybody who helped me, simple PCI crap bord was finished and layed out. Now we must wait... wait, and wait, for the boards being made and some parts which I don't have to arrive. Maybe a month or two. Perverse, but what can we do with the extremely slow post company in our country? 14days from china to our country, month from our customs or whatever to ur home. Absolute classic here.I give it 12% chance, that it will work... somwehere in the future, when/if the boards and parts arrive.

author: Yansi
author_rank: Super Contributor
timestamp: January 04, 2015, 10:06:08 pm
content: One little curious question though: Presence detect pins on PCI? I can find easily on the web, that they are used to detect the presence of the card and also it's power requirements, by the actual combination of which pins are grounded.One pin tells the motherboard, the card needs 12W, second identifies 25W and both grounded means 7,5W. That seems straight. But... !I am looking at an old S3 Trio graphic card now, no presence pin is grounded! ("no card inserted") What the hell? Did some older PCI spec used not these pins?PRSNT1# PRSNT2# Add-in Board ConfigurationOpen Open No board presentGround Open Board present, 25W maximumOpen Ground Board present, 15W maximumGround Ground Board present, 7.5W maximum

author: free_electron
author_rank: Super Contributor
timestamp: January 04, 2015, 10:09:15 pm
content: Did you follow the layout rules ( clock being longer than the other signal lines ) , length matching the ad lines , properly terminated. and 4 layer board ?or it;s going to flaky ... and a waste of your money

author: Yansi
author_rank: Super Contributor
timestamp: January 04, 2015, 10:15:32 pm
content: Do you know, what delay makes 1cm of 10mil trace on a 1.5mm substrate, ground below? So how many picoseconds do I need to delay the clock?

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 04, 2015, 10:43:32 pm
content: Quote from: Yansi on January 04, 2015, 10:15:32 pmhttp://www.saturnpcb.com/pcb_toolkit.htm

author: Yansi
author_rank: Super Contributor
timestamp: January 04, 2015, 10:50:55 pm
content: I already have that and know the value. But I've asked free_electron, for an explanation, he seems to know something which I don't understand.So how many centimeters of wire do I need to start having problems with clock beeing slow?

author: Yansi
author_rank: Super Contributor
timestamp: January 05, 2015, 01:22:33 am
content: So here is the properly terminated and length tuned PCI kit from Altera. My board must be all but wrong, after seeing that. A complete waste of money (about $10 and a few days of work if it would happen).It seems they couldn't even do proper level shifting, they made two ways how to deal with it: Slap there series resistor for clamp current limiting, or put there some interesting "5 ohm bus switch with level shift" (in which I just can't see any proper level shifting functionality in the part, maybe too much tiredness, past 2 AM here now), the part is also rated for 20MHz bandwidth, here it is used at 66MHz. (That is written on TI's pages, haven't found anything about this in datasheet)And I think they haven't even layed the board as written in the schematic, as an "overlaid footprint" for the two variants of levelshifting, if we could call that a levelshift. There is nothing more in the path between the PLD and PCI slot connector, only the circuit in tha last image.Here's the sheet for the bus switch:http://www.ti.com/lit/ds/symlink/sn74cbtd3384.pdfI just can't understand, how should I use that part as a bidirectional level translator.Board also looks mostly autorouted.At least they have fit your "4 layer requirement" which I consider useless for a simple LED IO experiment. And sure enough, I slapped all of that on a doublesided board. That must be wrong. The S3 Trio PCI graphic card laying in front of me must be also wrong.Now tell me something about lengthmatching, termination, impedances and moneywasting for making a custom board for under tenth the price of the kit.Or I am just too much stupid to see the special properties of the Altera's board over the mine, sorry for that.Note: Inner two layers are GND and VCC only, none signal paths there, nothing interesting to see.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 05, 2015, 02:05:06 am
content: Wow.

author: Yansi
author_rank: Super Contributor
timestamp: January 05, 2015, 02:12:20 am
content: I don't know for what that wow belongs, but to be exact, I extracted that board layout and shematics from the documentation of this $150 kit.http://www.altera.com/products/devkits/altera/kit-maxii-1270.htmlI had to install an application too see the stuff - I hate those things, really annoying.//EDIT: The levelshift functionality might work as a standard "slap there a mosfet" technique, but that only converts 5V down to 3 as a Vcc minus Vgsth, i quite cannot understand then, how does it work with 3V PCI bus, because the Vcc is hardwired to 5V for that circuit. I'd rather take a nap, clearer head morning.

author: free_electron
author_rank: Super Contributor
timestamp: January 05, 2015, 02:19:31 am
content: The level shifting is not done by the buffers. it is under control of the clamp rails. that chip is merely an analog mos being turned on. you can use series resistors or a bunch of those cbtd chips. the advantage is with the chip you can flick the card in isolation mode.that mechanism is explained in detail here :http://www.ti.com/lit/ug/scpu008a/scpu008a.pdfthe PCI spec for daughter cards calls for the following numbers :connector to device max : 1.5" max to the connector. the device re-samples the edges under control of the clock to eliminate skew.Clock is 2.5" (matched length),And the 64-bit extension signals spec 2" maximum. Exceptions include interrupt lines and the reset signal as these run much slower and use a handshake mechanism.What you fail to account for that the total bus length is not just the length of the wires on your board but also the length of the traces on the motherboard ! A bus is a point to point connection. So that signal originates in the pci controller on the motherboard and the total length of that motherboard trace , the connector and the traces on your board needs to be looked at. a Mother board has several PCI connectors sharing traces. These are all stubs and create problems with ringing and setup/hold time limits due to the edge not being as sharp. The PCI-SIG has a document that specifies the allowed boundaries under worst case conditions ( the MAx amount of slots and max tracelengths ). if you design according to those rules your board will work. they have done all the modeling and calculation to guarantee that any given system that follows those layout rules will work properly independtly of how many cards are plugged in and what is the position of your card in respect to the PCI controller.But feel free to throw all this stuff in the wind. i have only made over a couple of dozen designs using PCI, PCIe , Sata and other fast buses that went in mass production, so you may know better than me.

author: LaurentR
author_rank: Frequent Contributor
timestamp: January 05, 2015, 03:07:36 am
content: Quote from: Yansi on January 04, 2015, 10:06:08 pmFunny, I did a research project almost identical to what you're doing (PCI FPGA board, Windows drivers...), just exactly 20 years ago. One of the first PCI implementation on FPGAs (Xilinx 3k/4k).As far as PRSNT, AFAIK, desktop PCs never supported those. That's a lot of pins for not much information. It is required by the HotPlug spec (only applicable to hotplug systems), along with a way for sw to read that state, but that's about it. A standard OS enumeration code will read all buses and all slots and if the VendorID reads FFFF, it will decide the slot is not populated. It doesn't use the PRSNT pins.

author: Yansi
author_rank: Super Contributor
timestamp: January 05, 2015, 03:36:53 am
content: Lets talk about that a little bit in a detail:What clamping? I talked about 3V only CPLD being connected to the 5V PCI, through the bus switches. So where has the level translation gone for the CPLD? How the PCI bridge is dealing levels was NOT the subject, but thanks for the PDF.connector-to device lengths - that must be the length from the connector, to the FIRST device input/output on the board, it does NOT concern wires connected AFTER level shifters. I've used proper bidirectional level shifters, which are not directly seethrough as are those 5ohm switches. Length between the end of connector pin and a pin of the level shifter I have pretty under these requirements. As a reference, I've taken the S3 Trio graphics card - the wiring there is much longer than mine and I am concerned, that it is actually longer than your specs. For example, AD1 pin is over 45mm long. Clock trace is almost 50mm from tip to pin. So again, tell the S3 designers, how they are stupid.What you fail to account... Thats why I have traces short from tips to levelshifters. And a chunk shorter, then our Altera's friends, for obvious rasons: Nontransparent levelshifters with friendlier pinouts - each side with different voltage levels, no PCI bus traces go for the other side of the package. I guess that is also wrong.QuoteYes Mr. Your first design was utterly perfect. Instead of appreciating that someone tries to design something a little more complicated than standard arduino crap, only bunch of bitches disrespecting other's work. Do you know how long do I do PCI? No? Doesn't matter really. That only supports my opinion, that going public with anything which isn't arduino, is simply a waste of effort, because noone cares. With your type of attitude, noone will likely deal this kind of projects as a hobby in the future and everyone will stict with that arduino crap, in an age full of way better and more interesting cheap hardware, than an old 8bit crap MCU with crap code libraries.I will do my best to make the card working. But we really got off the origin with which I created this topic. That was the software access on elm-chans hardware. But I might have figured that out, at least I know two ways how to force a transaction on the BUS without having custom driver.LaurentR: Thank you for useful answer.

author: free_electron
author_rank: Super Contributor
timestamp: January 05, 2015, 04:19:27 am
content: Quote from: Yansi on January 05, 2015, 03:36:53 amthe mos in the cbt takes care of that. that chip is NOT a buffer. it is a bunch of mosfets that sit with their drain on one end and their sources on the other end. the gate is turned on from an internal reference voltage.That mos is turned on as soon as there is more than 1 volt gate-source differential. Let's say the source hangs at the cpld and the drain at the connector.if i set 0 volt ( logic low ) the mos is turned on from the internal gate voltage so it the drain and source swap places. and the cpld sees a hard logic low ( the drain and source of a mosfet are not 'static' elements. they are in 3 pin mosfets where the bulk is toed to the source. inside a chip we can connect the bulk a different way and then the drain and source are 'modeless' carruent can flow either way.so in case of applying a logic zero. the source hangs at the connector , the drain at the cpld. the gate sits at roughly half a volt under the vcc of the chip ( about 4 volt)if you apply a logic 1 or 5 volts. the drain and source swap places the mos will conduct and its output will sit at roughly VT below the gate level . these mosfets have a vt of about 1 volt as well. so their output hangs roughly 5v - vt or about 4 volts. for such a low VT the mosfet 'on' resistance is relatively high ( about a hundred ohm ). the internal clamp diodes in the cpld do the rest.if you were to measure across the mos you will see the drop stands across it. logic low passes through unaltered. logic high gets shifted down or up.for pci the logic high level is 2.7 volt so when driving from the 3.3 volt domain to the 5 volt domain it works as well.QuoteYou have not posted your design , nor ever said you use active buffered level shifters. I am working of the altera desing using the series mos level shifting technique. In that case the total line length is from pci controller on motherboard , through connector ,through the mos to the cpld pin.even if you use active latching buffers prior to the cpld then you still need to meet the PCI requirements in terms of max length. the distance between your latching buffer and the cpld no longer plays a role, the motherboard still does play a role.Quotelook who's talking.You start atopic with a question how to design a PCI slave . So the assumption is : you have never done this. I give you a bunch of valuable information , first you moan about 1K boards without having done your homework. Then you state yuo have not read the hardware app notes yet, or not in detail. I point out that PCI has some requirements to trace length and impedance matching. So you moan and groan again. then i tell you about the layout criteria and you moan and groan again. then you start picking apart the Altera design without knowing some of the basic techniques such as using mos arrays to level shift, make remarks about how the board looks autorouted ( it doesn't ) and other hand waving about the ALtera board. All the while you have not shown YOUR layout ...Fine with me. I was only offering advice and pointing out possible traps if this is the first time you are attempting to make something that deals with a reasonably fast, wide bus that has some timing criteria. All from the perspective from someone who has done these things years ago and has made the mistakes and learned from them, and has produced PCI boards , that passed the PCI certification test. All i get for my effort is a pile of bitching from your end. so who has the attitude here ? Troll

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 05, 2015, 04:30:49 am
content: Grabs bag of popcorn.

author: Yansi
author_rank: Super Contributor
timestamp: January 05, 2015, 08:15:08 pm
content: So there is really no level conversion. Only clamping with some series resistance. Lets's use your numbers: 100ohms for the FET. Now imagine all of the 32bit AD lines high. That gives lets say 18 miliamps clamp curent each. Or did I used the ohms law wrong? 18 miliamps times 32, gives ... wow, over half an amp clamping current injection in the 3V3 IO supply for the CPLD. Looks interesting. What about latchup stuff? What about exceeding tha absolute maximum rating of the device a few times? I think the max VCCIO group supply current is 170mA.QuoteThank you. This was helpful. My friend came with same conclusion. (VinHmin=2,0V, VoutHmin=2,4V).QuoteTrue, I haven't posted it. I thought, it wasn't neccessary. And I am glad that we can both agree on this paragraph. But I must've done that wrong.QuoteNot much to say. Starting question was a little bit different. About software. Not hardware. I clarified the goal of this project. Still it didn't help. Yes, I haven't read anything, because everthing I need for this shit project is on elmchan's page. I only want to reproduce his experiment, but with a little bit modern components, than DIP ICs and GALs. Still it doesn't stop you for showing off how good you are and what a moneywaste I am. And yes, it is a monewaste. The whole electronics hobby is a moneywaste and effort waste.Maybe if you (not only you) started conversation with me the other way than crapping my work as irrelevant and talkin about flakiness and moneywasting, the thread would also look different. But I do not blame you of anything, I shoud have expect this to happen.If you think that I do not understand MOS level shifters, then I do not understand, why I wasted $1.15 times 10 (5spare) for them. You nicely explained me, that the only level conversion there is clamping - but I did highlighted that before and also that my design doesn't inject hudreds of miliamps through the clamp diodes to the 3V3 IO supply, because I have used another type with dual supplies, but based on the similar MOS level shifting technique.Why I've took the board apart? Well, that was unnecessary waste of effort too. My action wasn't recognized. I wanted you to show me where has all the lengthmatching gone, because it looks like not much thought didn't go in. But maybe I am wrong again, as is my board, which definitely won't work. Magicaly, the elmchans wire nest with DIPs did work. I am damn sure it wouldn't be published, if it would't work. And sure it was lengthtuned and impedance matched. Maybe I am still wrong and looking on the wire nest from an bad angle.I appreciate your help, sure, but I just can't understand your attitude for my simple project.Alex Eisenhut: I hope you have had fun. I learn't a few new things about PCI, designed completely wrong non-working board (without anyone seeing it or asking too see it) .. (we will see in a month I think, if it will or not work) and wasted under twenty bucks for the parts and the board. If my board will not work, you can make fun of me, if you want. I am fine with that.Also I am fine if some of you think that I am dumb, can't understand what level shifting and clamping is, the effects of current injection and design of not so much fast board. You can think that, it is ur right.Now I am leaving this thread, until I have working prototype. Maybe I will post a photo in a future.Yours sincerely troll (if you think that).

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 05, 2015, 08:32:46 pm
content: Quote from: Yansi on January 05, 2015, 08:15:08 pmAren't you the one who said you "[...]do not (and will not) make things by slapping'em'together. It is simply not my style."??So far, all you've done is slap things together, rush out a PCB, then complain.I guess that's a "style".Read the damn specs and stop slapping together stuff from ten year old web pages.

author: Yansi
author_rank: Super Contributor
timestamp: January 05, 2015, 08:49:39 pm
content: That's missunderstandment. I will not use any prefabricated bulding blocks like kits. I always make my own.I will make whatever circuits I want, regardless of what you think. If you have too much energy to bitch around my stuff beeing oldschool, go away and find another thread. There are plenty of way more useless projects.If you don't like that I try to make my own stuff instead of using any PCI kit, what can I say you? Go and buy yourself a kit. I will not force anyone to build or replicate my stuff, neither am I going to publish that anywhere.And just one for those curious:

author: miguelvp
author_rank: Super Contributor
timestamp: January 06, 2015, 02:27:29 am
content: Are you trying to revive one of those old video cards? I don't even think it can do transform and lighting and it's probably too slow for MPEG decoding by today's standards.I'm curious what do you want to do with that card.

author: Yansi
author_rank: Super Contributor
timestamp: January 06, 2015, 01:38:57 pm
content: Quote from: miguelvp on January 06, 2015, 02:27:29 amJust took that for inspiration of what to do with some PCI signals, such as those JTAG ones or PRSNT pins.I've consulted my design with a friend and we talked about proper supply decoupling. So look at the S3 card designed by professionals. I haven't investigated it further.

author: free_electron
author_rank: Super Contributor
timestamp: January 06, 2015, 04:20:25 pm
content: Quote from: Yansi on January 05, 2015, 08:49:39 pmThere is nothing wrong with wanting to build that stuff yourself. The pointers we give you here are so you can make the best choices and something that has a more than good chance of working. just throwing parts at the ceiling and hoping they stick doesn't work.you seem to be dissing the design of that old trident card. There is nothing wrong with that design. it is withing the PCI spec.the AD bus is routed within the 1.5 inch requirement of the connector.If you look at the clock line you will see that they meander it and it goes up to the side if the trident chip. The people making PCI chips DELIBERATELY stick that clock pin at the side or the far end of the package in respect to the AD bus to force the board designers having a clock that is 2.5 inch long. Even with such large package the board designers still had to snake the clock to get there.The same goes for the altera layout. the layout is properly done. Yes they pump quite a bit of current ( and altera actually has a note to that effect somewhere in the documentation that what they are doing is not exactly 100% kosher ) but they meet setup and hold times and the transport works.PCI is a finecky thing.. if the bus artbiter sees any kind of bus contention it will slam on the brakes faster than you can say bluescreen. you won't even get a bluescreen. the computer will simply reboot. Any kind of bus contention on PCI is fatal.stuff like that can be very difficult if you are trying to develop software. if the hardware reboots the machine randomly because your signal levels ar e out of spec ( voltage and timing wise ) ..but, go ahead, don't listen to anything said, don't read anything, just throw parts at the board. it's your waste of time. not mine (anymore). i am done here.

author: Yansi
author_rank: Super Contributor
timestamp: January 06, 2015, 05:27:04 pm
content: You said, taht AD bus must be shorter than 1,5". My design is compliant with that. And it was before you bitched me out.The only thing I still don't get from your text is, if the clock must be exactly 2,5" or shorter than 2.5". The CLOCK trace on the card is NOT measuring 2.5". It is shorter than that. It is 49mm from the chip's leg to the beginning of the gold connector pad. about 49mm is 2". If the length requirement includes lead-to-chip wire length, it might be exactly 2.5".AD lines must be shorter than 1.5" - completely fine with that and understand the reason.Clock line must beexactly2.5" ?But simple question then - why exact length? If there is no card in the slot, there is no loading on the clock network. If I add there shorter trace why would that not work? If AD lines can tolerate loads of < 1.5", why clock has different rules of physics?If you'd explain me that, I'd really find that way useful, seriously.How does bus contention correlate with trace length?//I've just found that the S3 card is also not PCI compliant because its PRSNT pins aren't used and also"All +3.3V, unused +5V, and +V I/O pins are present and decoupled?"- no they are not. But that requirement is interesting, to decouple unused supply pins.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 06, 2015, 05:57:01 pm
content: Quote from: Yansi on January 06, 2015, 05:27:04 pmhttps://books.google.ca/books?id=tbIvDKSZbR0C&lpg=PA18&ots=s9RgWUgEsl&dq=pci%20clock%20architecture%20-pcie%20-%22pci-express%22&pg=PA34#v=onepage&q&f=false

author: Yansi
author_rank: Super Contributor
timestamp: January 06, 2015, 06:03:46 pm
content: and is this rule achieveable ...... edit, deleted, it is, my faulty calculations.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 06, 2015, 06:26:32 pm
content: Quote from: Yansi on January 06, 2015, 06:03:46 pmYeah, one of many.You wrote : "At least they have fit your "4 layer requirement" which I consider useless for a simple LED IO experiment. "You're the one who thinks that the PCI bus and the computer will know that you just want a simple LED IO experiment, and will suspend physics at your whim.Can you explain why you think physics is different because you're using a LED?

author: Yansi
author_rank: Super Contributor
timestamp: January 06, 2015, 06:37:22 pm
content: If a complete graphics card has been done on 2 layers, why simple PIO shouldn't? If ChaN's PIO was made using DIPs and wires, it didn't work? O0QuoteI've asked first. ;-)

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 06, 2015, 06:43:34 pm
content: Quote from: Yansi on January 06, 2015, 06:37:22 pmSo youdothink physics is different because you're using a LED... or do you think maybe those people took the time to understand what is going on to see what they can do?

author: Yansi
author_rank: Super Contributor
timestamp: January 06, 2015, 06:55:57 pm
content: Will you answer my question please or will you continue making crap out of this thread? If no, please stop visiting this thread!

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 06, 2015, 07:01:12 pm
content: Because they had a team of engineers that understood the spec correctly in order to know what to do.*you* decided it was "simple". Who told you it was simple?What is it you don't understand? You have done no research, demonstrated no understanding, and no willingness to listen.You simply slapped things together and then loudly complained, and demanded answers from people that owe you nothing.Answer your own questions from now on.

author: nctnico
author_rank: Super Contributor
timestamp: January 06, 2015, 07:05:48 pm
content: Quote from: Yansi on January 06, 2015, 05:27:04 pmThe clock line is longer to allow for better setup and hold timing. But... if your chip expects different setup and hold times you could end up needing a shorter or longer clock line. Without the datasheet of the S3 chip there is no way to tell why they choose a shorted clock line. Do yourself a favor and read the PCI specification and check whether the setup and hold timing for the CPLD or FPGA you want to use can match the PCI specification. The timing between the PCI bus and your chip should make sure the setup and hold timing of the PCI bus side and the CPLD/FPGA are met.It is definitely possible to have a 2 layer PCI board. With an FPGA or CPLD you can define the PCI pins so you don't need vias. You can create a solid groundplane on the solder side and have a copper pour (or rings) with power underneath the CPLD/FPGA. My former employer sold thousands of PCI boards which where designed this way.

author: Offensive username removed
author_rank: Newbie
timestamp: January 06, 2015, 07:12:32 pm
content: If you don't need to access PCI bus you could buy a PCI-USB card, then solder your device to one of USB ports and mount its PCB to USB card with hot glue.

author: Yansi
author_rank: Super Contributor
timestamp: January 06, 2015, 07:21:48 pm
content: Alex Eisenhut, go away, I have really no interest of continuing conversation with you.Who told you it was simple?Me! And I also emphasized the goal of this project.What is it you don't understand? You have done no research, demonstrated no understanding, and no willingness to listen.I ask A and you aswer B. None of you answered A, no wonder I am pissed when you bitch about things I haven't asked for!You simply slapped things together and then loudly complained, and demanded answers from people that owe you nothing.If you have a problem with free help, why are you visiting this forum? One must owe you something to get relevant answer from you?Answer your own questions from now on.Sure I will, because in this thread still I got no answer for my main question.nctnico, thank you for nice explanation. Now I owe you something :-) I just cannot understand why others are not willing to help. I will try to correct my design in the next version, if there will be any. Now I will just test what I've made in accordance with ChaN's experiment. Not much worse than ChaN's, so hope it to work. The PLD I've used is fast enough and PCI 66 compliant. But there's the catch with the levelshifters' prop delays, which I tried to count with.If I will make another version, I probably will use 5V capable PLD (MAX7k or XC95?) to get rid of the levelshifting stuff.HardcoreAnalFisting- That looks interesting idea.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 06, 2015, 07:42:08 pm
content: Quote from: Yansi on January 06, 2015, 07:21:48 pmSo you believe that your goal changes the physics of the signals.Quote from: Yansi on January 06, 2015, 07:21:48 pmWe have no idea what you are asking because you toss a bunch of stuff at us, run away when you don't like the answer, then change the subject.Quote from: Yansi on January 06, 2015, 07:21:48 pmTypically, people are friendlier and calmer than you. Pleasant, in fact. You, are not.Quote from: Yansi on January 06, 2015, 07:21:48 pmWhat *IS* your main question? Can you stick to maybe one specific thing at a time? Maybe post a schematic? Not pictures of commercial boards?Quote from: Yansi on January 06, 2015, 07:21:48 pmWe can't understand why you can't see we are helping.Quote from: Yansi on January 06, 2015, 07:21:48 pmDirect contradiction of your initial stated goal."If I wanted to make a IDE device or USB one, I will ask that, not PCI.""1) I will not make USB device here. I want PCI. For whatever reason..."" Everyone has a hobby. So why to bitch around that? And also again no for USB. "Can you see that you're difficult to follow?"PCI experimenting here. Going to study it myself the hard way."You certainly are.

author: Yansi
author_rank: Super Contributor
timestamp: January 06, 2015, 07:53:31 pm
content: Yes, I am complicated. So is stopping your spam injection in my thread.Is that readable or not?Quote

author: rob77
author_rank: Super Contributor
timestamp: January 06, 2015, 09:29:42 pm
content: i just noticed this thread....back in time, i've been developing linux kernel modules (aka. device drivers) for several custom PCI cards.my few notes1. make a PCI is not trivial/easy2. yes it's perfectly doable as DIY, but be prepared for way too many man-hours invested.3. PCI card can be 2 layer - no problem at all, but things are more reliable with 4layers with a dedicated ground plane4. you have to have a driver in OS - simplest approach is to have a small memory region mapped from your PCI card and write a driver which will present that region as a character device - then you can use starndard read & write syscalls from userspace to communicate with your PCI card.5. you need a PCI vendor ID/product ID to make it work - if you're planning just to play at home with it, the you can use any vendor/device ID.6. Xilinx Spartan3 is good enough to make the PCI interface in FPGA, but any modern better/faster FPGA will do as well.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 06, 2015, 09:37:13 pm
content: Quote from: Yansi on January 06, 2015, 07:53:31 pmYou obnoxious pest.

author: rob77
author_rank: Super Contributor
timestamp: January 06, 2015, 09:43:04 pm
content: Quote from: Yansi on January 03, 2015, 01:23:09 amhad a look at that webpage with the "PCI card" you linked above - please forget that web page... you'll save yourself a lot of frustration. the author of that page got absolutely no clue about PCI specs... he was trying to approach it like the ISA bus.. but things don't work like that with PCI.

author: LaurentR
author_rank: Frequent Contributor
timestamp: January 06, 2015, 09:58:40 pm
content: Quote from: rob77 on January 06, 2015, 09:43:04 pmThis is obviously an incredibly narrow view of PCI, and non-compliant in so many ways, but it can be made to work within a very specific scope. If that's the OP's only goal, then why not.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 06, 2015, 09:59:57 pm
content: Quote from: rob77 on January 06, 2015, 09:29:42 pmPCI cards also often have their own BIOS so that you use those system calls to use the card's hardware. Lots of programming required!

author: nctnico
author_rank: Super Contributor
timestamp: January 06, 2015, 10:10:37 pm
content: ROMs on a card only work in x86 backward compatibility mode to augment the system's BIOS during startup. Useless for any virtual mode OS.

author: rob77
author_rank: Super Contributor
timestamp: January 06, 2015, 11:45:57 pm
content: exactly... BIOS is not used anymore to communicate with hardware (it was used for that back in the times of DOS), that's the reason why you need to have a driver in OS which is handling all the communication between the hardware and userspace application(s). the BIOS is only "configuring" the hardware before control is passed to OS loader and is providing basic access to the boot device (bios drive #80) for legacy OS loaders.BIOS is being replaced by UEFI nowadays.