SMA phase adjuster construction? - Page 1
Forum section: electronics / rf-microwave

author: rhb
author_rank: Super Contributor
timestamp: April 02, 2019, 11:02:49 pm
content: Does anyone know the construction details of these things?https://coaxicom.com/product/sma-male-for-rg402-semi-rigid-phase-adjuster-3/https://storefront.brackemfg.com/storefrontCommerce/itemDetail.do?item-id=8940&order-quantity=1&item-index=0&customer-item=BM12000&order-uom=EA&warehouse-id=1&item-number=BM12000They're rather pricey, so I'm wondering if a simplified version is possible. I would expect that they are air dielectric, tube in tube construction with a solid inner conductor sliding inside a tube for the center conductor and tapered walls.I can get a ~1.5 ps variation by moving a loose SMA to 3.5 mm connection, but I want about 10-20x that.I'd potentially need enough of them to pay for a Sherline lathe to make them with money left over.I found the attached photo on eBay.

author: KrudyZ
author_rank: Frequent Contributor
timestamp: April 03, 2019, 09:49:15 am
content: The principle is a sliding fit of a trombone mechanism.Colby Instruments makes these with much larger delay ranges.https://www.colbyinstruments.com/You can probably find their patent to see how it is done.The difficult part is to maintain the impedance in the two sections and minimize any step effect between the two sections.I would imagine this requires very tight machining tolerances to get low VSWR.

author: rhb
author_rank: Super Contributor
timestamp: April 03, 2019, 01:55:06 pm
content: I would expect that the outer wall of the inner conductor is tapered and that the inner wall of the outer conductor is tapered. But that might not be necessary.If you have two 50 ohm air lines that slide together then the only discontinuity is the fringing effects at the edges.I've been trying to determine what is used to support the center conductor in a 3.5 mm connector I'd prefer not to buy one to cut in half. And even if I did, I'd still have the issue of identifying the material.The Tek 11801 is a pretty amazing instrument. I can see the ringing from the calibrator step reflecting off the sampling head and calibrator ports and measure the ringing in the calibrator and head at 25 GHz. No way, though, to tell if it's the head or the calibrator without getting an SD-32.I'd love to get a dead SD-24 to take apart and map out which segments of the circuit are producing which reflections. Reflection seismology at the speed of light :-)All of this is in pursuit of my FOSS DSO FW project. With two sources and two receivers I can solve for the ringing in each and correct for component variations in the AFE. I'll need to add that to the "To Do" list.

author: coppercone2
author_rank: Super Contributor
timestamp: April 04, 2019, 02:58:05 am
content: I suspect these things might be made with a CNC jig grinder. I have been thinking about how someone might make these sorts of parts quite a bit.https://www.mmsonline.com/articles/z-axis-opens-new-doors-for-jig-grindingon precision cones:https://www.practicalmachinist.com/vb/abrasive-machining/jig-grinding-tapered-lead-similar-countersink-265772/

author: rhb
author_rank: Super Contributor
timestamp: April 04, 2019, 11:54:27 am
content: A Sherline lathe is more than adequate, takes less space and is much cheaper.

author: coppercone2
author_rank: Super Contributor
timestamp: April 04, 2019, 02:27:17 pm
content: well if their made to extreme precision you need some kind of grinder. the surface finish from the lathe is going to be poor in comparison. Thats how they get those tolerances in the millionths and very high quality surface finishes that won't degrade from repeated insertions etc.I think the inside cone is harder to. here is someone doing a exterior cone face

author: rhb
author_rank: Super Contributor
timestamp: April 04, 2019, 05:40:01 pm
content: In the late 40's, Dave Broadhead made screws for the ruling engine being built by John Strong. The initial trial screw, done in 1947 as a warm up exercise, was within 0.000 002". It was made on a Southbend lathe that Broadhead had trued up by removing all periodic errors an rescraping the ways to 0.0001".You can find more in the June & July 1952 Amateur Scientist columns.However, for phase adjusters, 0.001" is good enough. That's not easy, but not all that hard either. It's not like trying to meet 0.0001" tolerances.

author: PaulAm
author_rank: Frequent Contributor
timestamp: April 04, 2019, 05:53:01 pm
content: Although you can cut threads on a Sherline (if you buy the attachment), it's not my idea of fun. I would definitely not want to cut threads in steel. In general, you may run into rigidity and chatter problems if you try to use something other than aluminum or brass on a Sherline.I'd use a slitting saw and spin fixture to cut the collet grooves. You could do that with a hand saw but repeatability might be an issue. I wonder how burrs would affect the performance. Seems to me when you get over 1GHz and look cross eyed at a component you can affect performance (usually adversely).I'm not saying you can't do it, but making decent repeatable phase adjusters in a decently equipped machine shop would still be a challenge. There's a reason they're expensive.Personally, I would look for some surplus (unless you really want to get into precision machining - that is not an afternoon's task). Trying to make your own is a much bigger detour from your project goal than you seem to think.For the record, I do have a decent machine shop and I'd still think long and hard before making my own. Then I'd buy them and get on with my project

author: rhb
author_rank: Super Contributor
timestamp: April 04, 2019, 08:21:36 pm
content: I also have a good machine shop. But i certainly would not claim to be a good machinist. I would not considering duplicating the designs pictured unless I had a CNC machine.I have in mind modifying some Chinese SMA connectors to fit suitable tubing, soldering tubing to them, sliding the tubes together, adjusting to length and soldering in place to create a fixed delay.I'd much rather do that on a Sherline than on my 10" x 20" Clausing. However, I might go with a Chinese 7" x 12-14" machine. The better ones have become quite good and I can make a hand crank for fiddly threading jobs.Any lathe can turn steel. The chip size simply gets smaller for steel than for brass and aluminum. If it's got good spindle bearings, you can make watch parts on a wood lathe. It would be clumsy is all.

author: rfeecs
author_rank: Frequent Contributor
timestamp: April 04, 2019, 09:13:58 pm
content: Quote from: rhb on April 03, 2019, 01:55:06 pmCould be Rexolite:http://www.rexolite.com/This gives an idea of some of the APC-3.5 tolerances:https://www.maurymw.com/pdf/datasheets/5E-062.pdf

author: rhb
author_rank: Super Contributor
timestamp: April 04, 2019, 10:06:08 pm
content: Thanks. I'd looked at several datasheets, but they were not as detailed as Maurey's are. Small wonder they're expensive. Holding .0002" in production is not easy. That requires temperature controlled flood coolant and probably a good bit of experimentation with feeds and speeds. I doubt that a computer program could calculate the exact amount of heat carried off by the coolant accurately.I've been using the calibrator output of my 11801 fed to a tee at the input of a 20 GHz SD-26 to look at reflections from various connectors and cables. The firmware is awful, but what an instrument! Because of my reflection seismology background, interpreting time domain data is very comfortable. I can translate the trace directly into an impedance profile.

author: mrflibble
author_rank: Super Contributor
timestamp: April 05, 2019, 01:14:17 pm
content: Quote from: rhb on April 02, 2019, 11:02:49 pmJust give in to the dark side, and get that optical table. You know you want to...That would neatly solve several of your side-sidetrack projects.1) 1.5entirepicoseconds equates to ahuuuuuuugedistance traveled in photon country, and as such is trivial to adjust for.2) Once you have all that laser goodness going, you might as well slap on a few gratings & prisms to do some of that pulse stretching & compression. That should easily take care of your desire for shorter-than-short pulses.Personally I'd just buy a used phase adjuster at ~ $100 on ebay, and get the rest of the project done. You can probably sell it after you're done with it for a similar price if you treat it nicely.

author: coppercone2
author_rank: Super Contributor
timestamp: April 05, 2019, 03:29:28 pm
content: i still think your surface finish will be poor on a lathe. I think you would need to grind those threads after you cut them optimally.

author: rhb
author_rank: Super Contributor
timestamp: April 05, 2019, 04:28:24 pm
content: Err, uhmmI need 7 phase adjusters, not just one. If I only needed one I'd have ordered a new one from Bracke.As for turned finishes, you've apparently not seen good work or don't know what to look for to distinguish turning and grinding.

author: coppercone2
author_rank: Super Contributor
timestamp: April 05, 2019, 04:31:33 pm
content: are you going to get comparable surface roughness from turning vs a 300+ grit stone?

author: coppercone2
author_rank: Super Contributor
timestamp: April 05, 2019, 04:32:21 pm
content: I go by this (as is practical to do with the black bars)

author: rhb
author_rank: Super Contributor
timestamp: April 05, 2019, 04:41:10 pm
content: Both turning and grinding provide the same surface finish at the minimum roughness end of your chart your chart.

author: coppercone2
author_rank: Super Contributor
timestamp: April 05, 2019, 05:47:50 pm
content: not typical resultsneeding 9 of them with cost sensitivity you need typical results.I think with a engineer doing this your going to get some where to the left haha. maybe a experienced machinist can wing it.And I honestly have trouble imagining that surface finish for a taper. I think it means for shaft.

author: rhb
author_rank: Super Contributor
timestamp: April 05, 2019, 07:11:46 pm
content: The requirements for the best quality surface finish are a sharp tool ground at the correct angles, a very fine feed and a light cut. It is much easier than you think. Amateurs do it all the time. The fact that it is not typical simply reflects the surface finish requirements of the enormous quantity of fasteners made by turning using automatic screw machines. The sole reason for preferring grinding over turning in order to meet a surface finish requirement is speed. The fine feeds required are much slower than grinding.I can't think of any RF connector that *could* be made by grinding. You can't grind a 0.036" hole.I've watched the machines used to make ball point pen tips to tolerances of millionths of an inch in operation. They are very impressive. Someone is almost certainly using the same machine I saw to make RF connectors. The sales and marketing guy that gave the machinist's club to which I belonged a tour simply mentioned BIC pen tips as an example of the sort of part the machine made.

author: coppercone2
author_rank: Super Contributor
timestamp: April 05, 2019, 07:45:09 pm
content: video of that?

author: rhb
author_rank: Super Contributor
timestamp: April 05, 2019, 10:15:20 pm
content: This was 25 years ago. I don't even remember the company, though I think they were Swiss.You can't see anything when they are running. The coolant flood makes the loading door look like a front loading washing machine. They are the modern version of a screw machine. CNC instead of cams. And the parts don't just drop into a hopper.I'd bet they are the devil to get tuned to produce things to the specs of the Maury 3.5 mm connector. And almost as much work to keep them in tune. At 0.0002", temperature control while turning is critical. Just a little heating of the part and it will be under size.

author: dcarr
author_rank: Regular Contributor
timestamp: April 06, 2019, 02:06:40 am
content: RHB,Would it work to just make a set of microstrip or CPWG lines and then tap them with .085 hardline at the point you need to achieve your delay? Yes, there will be a little impedance bump and you'll have to cut the line after the tapping point, but really cheap, easy, and decent performance. I've heard that careful application of grease to the coax-microstrip transition can be used to tune out the mismatch, too.David

author: joeqsmith
author_rank: Super Contributor
timestamp: April 06, 2019, 12:44:05 pm
content: Quote from: dcarr on April 06, 2019, 02:06:40 amI was wondering how two microstrips butted face to face would work. Slot the PCB to make it adjustable. Crude but I am really not sure what OPs requirements are outside the delay.

author: rhb
author_rank: Super Contributor
timestamp: April 06, 2019, 01:17:41 pm
content: David,Thank you. I think you just solved my problem.Here's the situation:The FPGA boards use a 2x6 0.100" IDC F header (PMOD) to bring out 8 signal lines. It doesn't appear that anyone makes a male cable header, so I'll have to use an IDC F connector and M-M header pins to mate them if I use a cable connector as I had been planning. However, by laying out a 2x6 M header on a board with microstrip lines I could adjust the electrical length before tacking the 8 coaxial lines in place with solder and then trim the excess stubs with a knife and peel them off. That should be a lot less work. Then I can epoxy all the cables at the edge of the board to secure them without putting any strains on the solder joints.I also need to make a 9 port resistive splitter to feed the calibrator signal to the head inputs to align the head skews. So I actually have to solve the delay matching problem twice. But matching lengths on a board should be a lot easier than matching cables.I'll also need to feed a test signal in which is synchronized and the resistive splitter alone will not meet that requirement as the levels will be too low I'm going to be learning a lot more about microwave construction than I had intended.

author: joeqsmith
author_rank: Super Contributor
timestamp: April 06, 2019, 01:29:30 pm
content: If the signals are digital, does the FPGA you are using allow a fine enough trim to do what you need?

author: rhb
author_rank: Super Contributor
timestamp: April 06, 2019, 01:31:51 pm
content: My objective is to verify FPGA simulator timing vs reality prior to really pushing the FPGA to the limits doing DSP operations.

author: joeqsmith
author_rank: Super Contributor
timestamp: April 06, 2019, 02:04:51 pm
content: Quote from: rhb on April 06, 2019, 01:31:51 pmSimulator timing from the circuit board layout side of things? It would be interesting to know more about the test setup and what you are attempting to validate with it.

author: RoGeorge
author_rank: Super Contributor
timestamp: April 06, 2019, 02:29:24 pm
content: AFAIK FPGA simulators are digital simulators only. They do not take into account propagation time at all. They simulate only the logic behavior of a circuits, and the unit time is the circuit clock.Meting the timing/speed parameters of a circuit is not the simulator's task. The simulator is for testing only the logical mistakes in a circuit, not the timing.

author: OwO
author_rank: Super Contributor
timestamp: April 06, 2019, 02:35:10 pm
content: To add to the above, the way the timing analyzer works is by tracking delays of every signal and checking the setup and hold time of every register and synchronous element. All the FPGA vendors have characterized every wire, LUT, register, and other resources rigorously and added margins to account for process variations. You should not run logic faster than the timing analyzer indicates, to do so would be overclocking and you won't get any guarantees the design will work on every chip at every temperature and allowed Vccint voltage range.

author: joeqsmith
author_rank: Super Contributor
timestamp: April 06, 2019, 03:40:41 pm
content: The tools will provide you with post place and route timing information which will include the propagation delays to the selected pins. This can then be fed into the layout tool to trim the lengths if needed.Depending on the part, the I/O can be trimmed internal to the device.

author: rhb
author_rank: Super Contributor
timestamp: April 06, 2019, 05:08:53 pm
content: I am not designing a board. I'm writing a reliable and I hope portable FOSS DSO FW stack for Zynq and Cyclone V based DSOs. I have a Zybo Z7-20 and a Terasic DE-10 Nano to use for the dev work. The PMOD interface is not available on the Terasic board, so I'll actually have to build two test fixtures.I fully understand that the vendors have characterized their parts. But the timing calculations for a particular topology are done in software. After many years of dealing with complex, expensive software packages I have *no* confidence that they produce the correct answer. I have constructed test cases that broke far too many codes. My concern is testing a filter configuration and getting a timing result which the part cannot reliably meet.A key feature I want to implement is the ability to apply an arbitrary series of FIR and IIR filters and math operations to any input trace and display the result in X-T, X-Y or do anything else the user wishes in real time for 8, 12 & 14 bit ADCs e.g. the HMCAD1520.In short, I am fed up with crappy DSO FW. To keep what little bit of sanity I have left, I need a project which presents a serious technical challenge. This is the project I have chosen. Because I want the code to be portable, I want to know with absolute certainty that a filter topology actually will run properly at design speed on both parts. The only way to achieve that is to measure the behavior of the various elements and arbitrary combinations thereof. This is a multi-year project.

author: joeqsmith
author_rank: Super Contributor
timestamp: April 06, 2019, 05:42:00 pm
content: I did a search and assume its related to the attached following threads. Sounds like an interesting and fun project. I still don't understand how the delay lines fit into it.https://www.eevblog.com/forum/projects/open-source-instrument-firmware-project-104048/https://groups.io/g/LeCroyOwnersGroup/topic/29601845?p=,,,20,0,0,0::recentpostdate%2Fsticky,,,20,2,0,29601845

author: rhb
author_rank: Super Contributor
timestamp: April 06, 2019, 09:20:26 pm
content: If I'm going to accurately measure FPGA propagation delays, I need to align the 8 channels of the 11801 w/ 4 SD-26 heads installed. I can adjust the delay for a head, but not for individual channels.I'm assuming a priori that I can't make cables which are close enough to the same electrical length. The need for phase adjusters is imposed by the limitations of the 11801.Who knows? I might get lucky. I'm about to crimp my first coaxial cable. Fortunately this one is not length critical. I just hope I don't ruin too many connectors.Except for the mathematics of signal processing, everything I'm doing is new. Or else something I haven't done in 30 years. So I'm expecting a *lot* of failures.

author: joeqsmith
author_rank: Super Contributor
timestamp: April 06, 2019, 10:08:18 pm
content: Perhaps use one reference and compare that using the same test cable with each channel. Get that torque wrench out...

author: rhb
author_rank: Super Contributor
timestamp: April 07, 2019, 12:36:01 am
content: I'm going to *try* to build matched cables. But making just one was defeated by none of my BNC connectors for another project matched either of the two crimpers I bought. So I need to order 2-3 more die sets from China.I'm already using a torque wrench on the SMAs.

author: joeqsmith
author_rank: Super Contributor
timestamp: April 07, 2019, 01:17:48 am
content: I guess I don't understand the need for any matched cables. Just one for a reference and one to sample each port. Perhaps there is a reason you need to look at all the pins at the same time. Are you trying to tie two of these eval boards together? One ADC the other the FPGA and you want to run the bus across with these cables? I'm lost....

author: rhb
author_rank: Super Contributor
timestamp: April 07, 2019, 01:32:56 pm
content: The purpose is to examine propagation delays across the output of an adder or multiplier. In a DSP filter pipeline you have to add latches between stages to retime the bits in an output word. This imposes a fundamental limit on how fast you can clock the filter. Adding latches increases the area, power and latency.My concern it that a software bug might underestimate the skew across the output word and lead to not having a latch where one is needed. If the skew is such that most of the time the full word is valid at the start of the next clock cycle, but not always, it leads to incorrect output that is very hard to track down and fix.In addition, the skew varies with the input. So I plan to generate all possible inputs to an adder or multiplier and identify the worst case.@dcarr's suggestion solves the alignment problem very neatly and should be easy to implement. I can press the center conductor to the board with a non-conductive probe and move it along the trace while watching the scope. When the timing matches I solder it in place and remove the stub. A more elaborate arrangement would be to slide an SMD vertical SMA-F connector with the through hole pins cut back to locate the correct point, then drill holes and mount an unmodified connector. That would avoid reflections caused by an asymmetric shield connection that soldering the cable to the board would produce.I bought a bunch of U.FL to SMA jumpers, so I might be able to use those for the fixture if they test out OK. That should improve the transition BW. And a dab of epoxy will make the connection permanent.

author: OwO
author_rank: Super Contributor
timestamp: April 07, 2019, 04:00:17 pm
content: Quote from: rhb on April 07, 2019, 01:32:56 pm1. The synthesis tools do not add registers (assuming we are talking about ordinary HDL based design and not HLS). Any register stages are your responsibility and if there is too much combinational delay your design will simply fail timing.2. The delay depends on the exact placement and routing of your logic. If you try to "probe" an internal signal in your design by bringing it onto an IO pin, the placement of logic resources (and routes chosen) will be completely different from before. Therefore trying to measure internal logic delay on the IO pins is completely futile. Besides how will you account for routing delay to the IO pin and IOB delay?3. The timing analysis part of the code is the simplest part. All it has to do is add up all the delays of an existing (already computed) route and check setup and hold times. The actual place & route is orders of magnitude more complex and is where I would expect bugs to be. However as mentioned above just the presence of "debug" logic can alter placement drastically, so anything you verify becomes completely moot when you remove the debug logic.

author: OwO
author_rank: Super Contributor
timestamp: April 07, 2019, 04:07:07 pm
content: If you really suspect Xilinx's timing analysis code the best way to verify is to take the post-route netlist and run your own timing verification. You still need to know the specifications of each logic resource and guess at route delays, but if you don't trust Xilinx's device characterization either then your best bet is either characterizing using test designs or wafer level probing.

author: rhb
author_rank: Super Contributor
timestamp: April 07, 2019, 05:57:48 pm
content: I just looked at the HiRose U.FL datasheet and did a TDR test of the eBay U.FL plug to SMA-F jumpers I bought for about $0.50 each. They should work perfectly following the suggestion made by @dcarr. The only issue left to resolve is whether I can get 50 ohms with a single sided coplanar waveguide or whether I'll need to use a 2 layer board to meet the HiRose footprint.

author: joeqsmith
author_rank: Super Contributor
timestamp: April 07, 2019, 10:21:00 pm
content: Quote from: rhb on April 07, 2019, 01:32:56 pmBut once you route it out, you will need to consider those effects as well (pin choice and such plus the layout). You may want to consider Chipscope.Adding pipe stages will add a delay but normally I will do this because I am trying to get higher performance (clock it faster).

author: rhb
author_rank: Super Contributor
timestamp: April 07, 2019, 11:11:18 pm
content: I will be using every tool I can. But I can only work so fast. I've got another 750 pages of "Planar Microwave Engineering" by Thomas Lee to read before I make a board layout for the phase adjusters. And I might well read Johnson & Graham also.I've had the FPGA boards for well over a year. However, I'm still working on basic infrastructure and background reading. I spent my career doing things I'd never done before. I have a hard rule.I never write code until I've run out of excuses for not writing it.The only time I ever got in trouble was the one time I ignored that rule because the task seemed so familiar that I overlooked that the particular use case was different. I spent a very miserable 2 weeks being reminded that the discrete Fourier transform is defined over a semi-closed interval.

author: tomato
author_rank: Regular Contributor
timestamp: April 08, 2019, 01:46:18 am
content: Quote from: rhb on April 05, 2019, 10:15:20 pmHeating of the part isn't a big issue when the parts are that small.