Got my new batch of faulty PCBs ! - Page 1
Forum section: electronics / projects

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 23, 2012, 08:26:21 pm
content: The problem is not with the PCB fabbing, but the layout itself.Mylayout. Yep, total fail on my part.So I receive a couple prototypes, a second version of a project I'm working on (nearly fresh layout) and am wondering why I can't clock my PIC32 faster than 40MHz (if I'm lucky). I should also mention that I have no EE training or education whatsoever, only self-taught. And that I'm fairly new to PIC32's, though I've been making projects using AVRs for a few years.So I'm probing for hours and trying to figure out the problem. One of the decoupling caps was a little far from the pins to make room for the oscillator so I dead-bugged it as close as I could. Still no dice. At 20MHz the pic ran fine, but at 80, it seemed to reset after a few uS. Not being really familiar with the architecture, this really confused me. I was also looking at my compiler and debugger settings, in case I had mis-set those as well.Eventually, I came across this thread:http://www.microchip.com/forums/m453315.aspx..which explains vcap needs to be as physically close to its pins as possible, and the type of cap is important too. Or else one gets the type of instability that I was seeing. I really had no idea! Having no training, I saw this pin needed a 10uf cap so pffffftttt just slapped a random electro on there. The first version of this board ran well because that cap just happened to be close enough to the pin! But look at the distance now (green trace). For something that Inowunderstand has to be practically on top of the pins, that's huge! Never had that problem with AVRs, though in makes sense now, with the much slower speed.Learn something new every project I guess. Gonna order some 0603 10uf 16v ceramics and adjust the layout a bit. The worst out of all of this is the 3-week turnaround for the boards.

author: johnmx
author_rank: Frequent Contributor
timestamp: September 23, 2012, 08:44:09 pm
content: That information is very explicit in the data sheet:Section 2.1: “Basic Connection Requirements”Section 2.3: “Capacitor on Internal Voltage Regulator (VCAP/VCORE)”Figure 28-2: “Note: It is important that thelow-ESRcapacitor is placed as close as possible to the VCAP/VCORE pin”.low-ESR -> Electrolytic not good

author: mariush
author_rank: Super Contributor
timestamp: September 23, 2012, 09:01:26 pm
content: Uhmm... watch out with the high capacitance ceramics. The capacity varies with heat and if they're not x7r or something equivalent, they'll suck.I don't have a lot of experience with high clocked stuff, but it seems to me the trace length is just too big. You actually have room right above the green pin for a ceramic cap.The esr has to be low ... but the papers say less than 5ohm ... the current modern 10-22uF electrolytics can have less than 1-2 ohm esr

author: Baliszoft
author_rank: Frequent Contributor
timestamp: September 23, 2012, 09:11:53 pm
content: Maybe you should try to relocate the load caps for the quartz too, so they are from the same distance.

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 23, 2012, 10:15:15 pm
content: So which type of cap would you guys reccomend? 10uf tantalum?I don't really know anything about ESR. Like I said, untrained and uneducated. Things just sort of always worked with AVRs. Live and learn.Yeah at this point I'm pretty much resigned to having all my decoupling caps, and the crystal's caps as SMD. Only way I'm gonna get them close enough. Maybe right under the pic, under the board.

author: nctnico
author_rank: Super Contributor
timestamp: September 23, 2012, 11:31:23 pm
content: Quote from: mariush on September 23, 2012, 09:01:26 pmThats overstating the problem. Its not like the value falls down to zero. Just run them at half the specified voltage and you'll be fine. Just assume the value isn't very accurate. For decoupling that is just fine.@cloudscapes: I strongly recommend using SMD ceramic caps. Another good trick is to have a VCC plane under the chip on the top layer and a ground plane on the bottom layer and route as many signals on the top layer as possible.

author: richcj10
author_rank: Unknown
timestamp: September 24, 2012, 12:35:53 am
content: Having as copper pour that is at any potential other than ground is a bad idea. You have more chances of a issue than having both at ground.

author: IanB
author_rank: Super Contributor
timestamp: September 24, 2012, 12:42:24 am
content: Quote from: cloudscapes on September 23, 2012, 08:26:21 pmSince it's a prototype, learn how to bodge! Just because you found one problem with your board layout, doesn't mean you have found every problemPiggy back that cap right on top of the pins any way you can and then continue testing. Don't order a new board until you are nearly confident you have found all the issues with the current one or you will have a heap of scrap boards as high as the ceiling!

author: richcj10
author_rank: Unknown
timestamp: September 24, 2012, 01:29:56 am
content: IanB, Very good point!

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 24, 2012, 01:42:46 am
content: Quote from: IanB on September 24, 2012, 12:42:24 amyeah I bodged the 10uf electro right on top of the pins. Didn't really help. For what it's worth, bodged and unbodged, the pic seems to work all right in debug. Just not simply flashed and run.Here's an earlier proto board:Worked just fine this one! I essentially locked the net connections, unrouted everything and remade the layout. The vcap obviously much farther in the new one, then not knowing it would make a difference. Aside from a few new unused connections (new test pads for the pic) and a new pot, the schematic is the same. Because the first board worked without any bodges, it's really really tempting to just do a 3rd revision board keeping the caps in mind. After making tripple-sure the net connections are good, though.Ugh, decisions!

author: Psi
author_rank: Super Contributor
timestamp: September 24, 2012, 01:54:19 am
content: Forget the electro, try some ceramics or tantalums, even if you have to parallel 4 up to get the 10uf.The first part of the faultfinding process is to confirm that this cap is indeed the reason for the problem.So just use what ceramics/tantalum you have around and see if you can fix it.Then you can worry about sourcing a new single cap for the design.(check that you have the right polarity for any tantalums you use)

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 24, 2012, 01:59:46 am
content: Quote from: Psi on September 24, 2012, 01:54:19 amI've got a few SMD 10uf tantalums. I'll try right away......bodging pitch this small ain't easy.And I have to check for shorts after ever bodge to make sure I'm not creating problems when fixing others.

author: Psi
author_rank: Super Contributor
timestamp: September 24, 2012, 02:09:17 am
content: even soldering the tantalum across the 10uf electro where it currently sits may help

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 24, 2012, 02:30:33 am
content: Yeah, still not really working.I removed the electro, lifted the vcap pin up and onto the tantalum piggybacking the pic (polarity is okay), and then the cap to ground of course. Not gonna get any closer than that even in a well-optimized layout. The tantalum is closer to the pic than the pic is to the board.No shorts around the bodge area. I don't have a magnifying glass, but I used a little hand loupe and continuity checking.Like I think I mentioned earlier, if I divide the PLL down to 30 or 20 MHz, then it starts working again, so that leaves out bigger problems elsewhere in the layout. The problem is when it's clocked at high speed.It might be the decoupling caps, then. Don't have any 0.1uf in SMD (I actually only have 10uf and 22pf in SMD), but I do have one other fresh proto board. This one is too messy and bodgy to give me much confidence, so I might populate part of the other one with cleaner bodges and see. And if that other one doesn't work, and I've compared my routing against the 1st layout that did work, then I might as well go ahead and layout the caps and crystal again.

author: MaxPower
author_rank: Newbie
timestamp: September 24, 2012, 07:12:08 am
content: Dose that track with the 10 uF capacitor have anything to do with the internal PLL and Clock???

author: T4P
author_rank: Super Contributor
timestamp: September 24, 2012, 07:56:23 am
content: Quote from: cloudscapes on September 23, 2012, 10:15:15 pmThrow the tants out of your book, they are expensive now and aren't any better than they were compared to MODERN LOW ESR electrolytics plus if you got the dry slug types they can blow up after a short while ( the wet ones can also go boom even fiercer ) And stock up on 10uF 0603 X7R ceramics + 100pF caps along with 0.1uF and 10nF, as well as 1nFA great combo for PSU bypassing, 10uF for the lower frequencies, 0.1uF for about 20MHz, 10nF for 50MHz, 1nF for 100MHz and you can guess 100pf .... but i guess if the datasheet says 10uF Low-ESR cap well then, by all means just remember to get X7R not those Y5V cheapie shits that only have 20% capacitance left at full voltage

author: JuKu
author_rank: Frequent Contributor
timestamp: September 24, 2012, 08:34:47 am
content: - At these frequencies, you really, really want a solid ground plane. You might not have much chances without, sorry. At 80Mhz, you can't afford the inductance from PCB tracks. If you must have a double sided board, minimize routing on the ground layer, make those routes short and place those away from the high speed chips; a few isolated half-inch long tracks away from the processor is ok. But do your homework for four layers. I often find that four layers is only 30-40% more expensive, but at four layers, the board is easily 30-40% smaller. On a hobby project, the setup might tip the scales otherwise, though.- With a chip trying to run at tens of MHzs, all decoupling caps have to be within a few mm from the Vcc pin. As said, you can't afford the inductance. At least one ceramic SMD 33-100nF per pin, and one ceramic SMD 10uF per chip. On a bigger chip (more than an inch or so across) one per side. You might get away with a tantalum if you know the details, but why bother, ceramics are cheaper and easier. And they need to be SMD. Did I mention the inductance already? At 80MHz, you can't afford the inductance from the component leads.- Your first layout for the crystal (I suppose he rectangle on the right is a crystal) is much better than the second one. You want a symmetrical layout here.- Now is a good time to switch to SMD.Your chips are SMD already, so you only need the Adafruit books (or similar) to get a pretty good start:http://www.adafruit.com/products/441,http://www.adafruit.com/products/442and some 10uF.

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 24, 2012, 11:45:52 am
content: Thanks for the wealth of tips, guys.I'll redo the layout around the MCU tonight after work. I'll try to avoid 4-layers for now, unless I'm really stuck in a corner. Here's what I'll try.1. Ground plane on top side.2. Vias connecting the top to bottom, where I'll put the decoupling caps and vcap along the edge of the MCU's outline. Something like this:Sound okay?

author: EEVblog
author_rank: Unknown
timestamp: September 24, 2012, 12:07:51 pm
content: Quote from: johnmx on September 23, 2012, 08:44:09 pmIIRC I did a video on a similar PIC VCAP/VCORE problem ages back.I installed a 1uF cap instead or 10uF or something and it caused the sleep current to go through the roof! (but otherwise worked I think)Had me scratching my head for ages.Dave.

author: JuKu
author_rank: Frequent Contributor
timestamp: September 24, 2012, 12:21:35 pm
content: A ground plane should cover the whole board, not just a part of the chip. This shows what I meant. The image is from an old board, so two layers and electrolytics, but shows the point. Blue= bottom layer; red= top layer; light blue dots= vias directly (no thermal reliefs) to the plane. Note C104 and the array of caps on the left side. This is not a high frequency part, so I could have this much routing on the ground plane layer. For a processor, I would have routed all tracks away from the part and do the crossovers elsewhere than under the part. So, even this is NOT good for high frequencies, there is too much routing under the chip. For a few hundred kilohertz that this runs at, the layout is fine. You want better ground than this!Try: Route all you can on top layer. Route Vcc first, as direct as you can. Put caps as close to the chip as you can get, with a via to bottom. Then route the rest, all an top. If you can't stay top side all the way, make crossings at inch or so away from the part.

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 24, 2012, 04:07:54 pm
content: Quote from: JuKu on September 24, 2012, 12:21:35 pmAlright, I'll cover the digital portion of the layout with a ground plane, not just under the chip itself. It'll be tough moving things away from the MCU. I can increase the height of the layout if I need to, but the width is pretty much dead fixed (it goes in an aluminum box). I'll move the analog stuff on the far right closer to the edge for some extra mm's.Thanks JuKu. Can the caps be inside the MCU's footprint as long as vcc between them are kept as minimal as possible? I know I've seen commercial boards where decoupling caps were on the inside, flipside.

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 24, 2012, 04:08:28 pm
content: Quote from: EEVblog on September 24, 2012, 12:07:51 pmI'll have a search for it later, might prove useful! Thanks Dave.

author: nctnico
author_rank: Super Contributor
timestamp: September 24, 2012, 04:28:14 pm
content: Quote from: richcj10 on September 24, 2012, 12:35:53 amIf that where true then no multilayer PCB wouldn't work. What you want is the lowest possible impedance between the power pins. When you use a power and ground plane the impedances of all the directly connected capacitors can be seen as being connected in parallel. Besides that the capacitance between the planes also helps a little bit.

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 25, 2012, 01:48:07 am
content: How does this look?1. Moved decoupling caps and vcap under board as SMD. As close as they'll go inside the MCU's outline. If they were outside the outline, they'd be much farther to allow connections to other pins, etc.2. No crossing traces under MCU.3. Components other than crystal kept at a distance.4. Copper fill out several mm's from MCU. I hesitate to make it go farther as there is a bunch of audio nearby and I don't want audible noise seeping through. I might be able to push the pour a couple mm's farther.

author: mariush
author_rank: Super Contributor
timestamp: September 25, 2012, 02:14:28 am
content: Why don't you move the programming header all the way to the left bottom corner, with the MCLR on the far left ?This way I think you could put the 10uF capacitor directly above the location of that pin needing decoupling, if you move that single trace going horizontally to the other side of the boardyou'll no longer have that Y between the capacitor, the resistor and the pin, and you can flip the resistor on the other direction, towards the bottom, over those traces, and it will be basically a few mm away from the MCLR pin. A lot of those traces in that corner will go away if you move that header.ps. There's a trace there going towards the top of the board that's almost at 90 degrees at the corner. Shouldn't matter much electronically but some pcb manufacturers may have issues with that.

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 25, 2012, 02:28:24 am
content: Quote from: mariush on September 25, 2012, 02:14:28 amYeah I know about the y-junction and the 90-degree trace. The layout can be optimized in other places too, but didn't go there yet in case i was doing something massivly wrong with the caps and had to start a bunch over. I'll def spend time polishing up trace neatness once I'm happy with the layout and basics.Well the 10uf vcore cap *is* pretty close to the pin that needs it, it's on the other side of the board as an SMD part. The 10uf through hole electro that's a bit higher is just a general purpose filter on the rails I put there by default. It's not the vcore cap.I may move the programming header around, yes. But I want to make sure I understood the decoupling correctly mainly....

author: vk6zgo
author_rank: Super Contributor
timestamp: September 25, 2012, 03:45:55 am
content: At high frequencies,the biggest contributor to the series impedance of Electros is Inductive Reactance.The construction even looks like an inductor,so in most cases with RF equipment,they are not trusted,& if used,are paralleled with a ceramic or silver mica cap.

author: JuKu
author_rank: Frequent Contributor
timestamp: September 25, 2012, 07:11:08 am
content: You don't really get the function of the ground plane. You want to minimize the supply current - chip - return current loop inductance. An _unbroken_ solid ground plane has the nice feature of taking the optimum return path (says Kirchoff). In this layout, it looks to me that the Vcc comes to the 10uF and 10k to a power pin on the left side of the chip. The return current starts from a ground pin on top of the Vcc pin. This current does not have a good path back.A ground plane is benefical on audio as well, since the potential interference picking loops automatically get the smallest possible area.You can have the same solid ground plane cover both analog and digital sides without needing to worry about interference. If you don't cross the signal lines, the return currents take care of themselves, no need for split ground planes. With good routing, the ground plane will have a virtual analog-digital dividing line, where no current flows. You could have a split there or not, it would make no difference. There would be a small area where digital control or converter data lines go to the digital side, and the ground plane carries the return currents. This area would be the optimum place to connect split planes, if there would be a split. But as illustrated, the split is unnecessary, and the beauty of the solid plane is that all this takes care by itself, even when the optimum solution might not be the same for all signals or all frequencies. You just have to be careful in routing the signals.Look again at my example. As said, it is NOT a high frequency processor chip. But imagine removing some of the traces from the plane (especially the four on the left side) and then, how the return currents would then (freely) flow, and you get the idea. The four lines on the right are digital control, and you can see how I could route those directly away from the chip. There are some crossing traces but these are in straight angles, not much chance for interference there (and the lines were static in normal operation anyway).Btw, you have a couple of 45deg corners. Those could be a problem. (Google PCB acid trap)

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 25, 2012, 12:42:45 pm
content: Quote from: JuKu on September 25, 2012, 07:11:08 amHi JuKu, thanks for the reply. I know about the 45 degree corners. I'll fix those later when I have the basics right.Let me start in saying that I'm aware I don't really know what I'm doing when it comes to high-speed electronics. You're probably right in what you're saying. But I'm still wrapping my head around this and to be honest, some of what you wrote has me even more confused than before (due to my fault and lack of education, probably). Let's see..If I understand your first paragraph correctly, you thought power came from the left of the board, through the programming header? I should have mentioned I'm not supplying power to the circuit from the programming header. Power comes from above the 10uf electro, the thick trace and the thinner trace alongside it, so the path to and from the programming header is relevant only when I'm programming, so I'm not sure I understand when you say I have a problem with current path? It goes down into the electro from the top, then down and to the right on the L trace (90 degree shapes I'll try to avroid in the final layout), supplies the MCU, and then connected to the ground plane and back through the lower-left, up, and through the electro again.Here's a different view of the ground plane I have. I colored in broken parts of the plane, but since these don't have any connection to anything else...... is that a problem? I can ground those isolated parts through vias. The ground plane is however unbroken from the power supply and to the chip, and then back. As well as being under support circuitry like the decoupling caps and crystal. I thought that was the point of a ground plane, shielding?I will fully admit I probably don't get the function of a ground plane (rf shielding initially, I never thought impedence had anything to do with this)No need to reply just yet. I've just woken up. I'll go over your reply again a few times later today and I'm sure something will click.I still hesitate to put a ground plane around the analog audio stuff. That part isn't broken. I've designed and used loads of analog-ish layouts with circuits like this without a ground plane, and they work. Once however, on another project, I had an AVR driving a matrix display, and analog audio parts on another section of the board. The board worked fine (no noise) and I decided to fill a ground plane on the entire board for a later revision. The other tweaks were too minor to have an impact and were mostly tweaking mounted pot placement by a few mm's. Anyways, I got the boards with the ground plane back and there was newly added audible noise from the matrix display bleeding into the audio. That's why I kind of want to avoid putting ground planes under sections of *this* board that aren't broken.I'm sure full ground planes in well-designed digital/audio boards work well. But I'm still in beginner zone and past experience says they don't work well for *me*. At least not under the analog components. For now, anyway. Obviously the digital components need them (much more than I thought just two days ago, even).I can do like the example you posted (minus the traces under it) later tonight. I'll reread your reply later today as there are still a couple things I'm not getting.Thanks again!

author: JuKu
author_rank: Frequent Contributor
timestamp: September 25, 2012, 03:00:23 pm
content: A quick clarification: For you, a broken plane means area of unconnected copper. For me, a plane is broken if return currents (two points of a plane) don't have a line of sight (or close) path from one point to another. In your new picture, the plane is broken in the middle, only a narrow bridge on bottom connecting the two sides. Ok?

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 26, 2012, 04:18:43 am
content: closer? thanks for the broken ground fill correction.

author: JuKu
author_rank: Frequent Contributor
timestamp: September 26, 2012, 06:08:41 am
content: MUCH better. :-) Now move some vias and tracks a bit so you get the plane flow around the few tracks you have there and get rid of the track between the crystal and the PIC, and you are good to go, as far as the layout is concerned. Any high frequency problems after this are unlikely PCB related.

author: amyk
author_rank: Super Contributor
timestamp: September 26, 2012, 09:02:11 am
content: This might be a minor thing but I noticed a lot of the application notes for various MCUs have a recommended layout with the two load caps closer to the IC than the crystal, like this:

author: JuKu
author_rank: Frequent Contributor
timestamp: September 26, 2012, 11:51:05 am
content: Quote from: cloudscapes on September 25, 2012, 12:42:45 pmNo, in high frequency digital electronics the function of a ground plane is to provide a low impedance return path for the currents. When a signal changes state, there are capacitances and inductances involved (from chip itself, component leads, PCB tracks etc). This causes oscillations on signal edges, ground bounces and all kinds of nasty effects. The more impedance in your signal and ground connections, the worse. At some point, the effects are so bad that the circuit does not function anymore: Imagine a signal going down. Impedance on the lines essentially means slowing down changes, so when the signal reaches zero, it continues going down. In most digital chips, funny things start to happen when the bounce goes more than 0.5V or so negative... Then it bounces back up, but again, more than desired, sometimes enough for the receiving end to see a double pulse. You've seen ringing waveforms on a square wave edges. A good ground plane makes great job minimizing these effects.The bypass caps function as local reservoirs of charge. When a signal changes state, the driving transistor turns on and wants current. The power supply is way too far (again, the impedance of leads and wires, and the speed of light), so the current (= moving charges) is taken from the caps. And you'd like the ground pin to stay put. If there would be a wire from the capacitor ground end to the chip, it wouldn't, since the inductance would slow down the return current. Again, a good, solid ground plane is the solution.Btw, on a chip that runs at 80MHz the signal edges are really fast. As you noted, you do need to worry about grounding and bypass caps, but signals are still usually manageable. At a hundred MHz range, you start to worry about impedances of the signal lines and matching lengths; at gigaHertz things get really interesting... ;-)Further reading:http://www.edn.com/design/analog/4394761/Successful-PCB-grounding-with-mixed-signal-chips---Part-1--Principles-of-current-flowhttp://www.edn.com/design/analog/4395817/Successful-PCB-grounding-with-mixed-signal-chips---Part-2--Design-to-minimize-signal-path-crosstalk

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 30, 2012, 01:57:56 am
content: I hadn't forgotten this thread!removed/spaced out more bottom traces. moved the oscillator caps. some other tweaks.I just want to thank all of you (especially) JuKu for the help and patience. I took the opportunity to revise a couple other boards as well. one PIC32100TQFP board I hadn't yet ordered, and an AVR board which already worked perfectly fine but I guess could use the extra stability bonus from a proper fill.thank you for the extra reading material!

author: Baliszoft
author_rank: Frequent Contributor
timestamp: September 30, 2012, 09:38:15 am
content: How about the trace under the sonic crayon logo? It does quite a journey on the board. :-)

author: T4P
author_rank: Super Contributor
timestamp: September 30, 2012, 09:49:00 am
content: That's like going from Perth, WA to Sydney, NSW! *In relativity

author: Rerouter
author_rank: Super Contributor
timestamp: September 30, 2012, 09:54:35 am
content: while that power trace (along with quite a number of others but thats another matter) could be shortened, it has local decoupling so the argument is slightly moot,

author: Baliszoft
author_rank: Frequent Contributor
timestamp: September 30, 2012, 10:32:29 am
content: If one can do it with half its original length and spare some vias its never moot in my opinion.

author: cloudscapes
author_rank: Regular Contributor
timestamp: September 30, 2012, 06:50:23 pm
content: yeah, that trace isn't ideal, but it's functional. there are just so many traces between the power supply and where it's going that I'd need a thousand vias.eventually I'll neaten up the spaghetti of traces in the mid-left region, which will allow easier power traces.

author: chrisc
author_rank: Unknown
timestamp: October 01, 2012, 06:41:47 am
content: Quote from: cloudscapes on September 23, 2012, 08:26:21 pmI've done a fair bit of work with PIC's and my experience when using the on-chip voltage regulator is that the proximity of VCAP to the device isn't hugely important. However as others have stated the type definitely is. I generally use 4.7 or 10uF tant's.

author: cloudscapes
author_rank: Regular Contributor
timestamp: October 23, 2012, 07:46:53 pm
content: Hey all, just an update,Just got a couple of the new boards (fabbed by OSH Park, excellent quality boards!) and the new layout is working great! I'll fix the long power trace on rev3 but for now this is perfect.Thanks again everyone!