vhdl, fast divider and fast multiplier, without instantiating DSP slices - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: August 23, 2016, 09:18:30 pm
content: guys, I am looking for algorithms implemented in vhdlexamples, tips, advices, and keyworks to google forlet me know, thanks in advanceI am going to (re)implement my 32bit ALU (1)for an hobby project (arise-v2/r5 softcore)(1) it will be tested under ghdl

author: rstofer
author_rank: Super Contributor
timestamp: August 23, 2016, 11:46:32 pm
content: Almost every modern FPGA has a bunch of fast (1 cycle) multipliers which may, in fact, be DSP blocks but single cycle multipliers were available before DSP came along.Division is a completely different issue.I took a class on this stuff in grad school and it must have slipped away. I didn't use the information for a very long time.If you insist on doing multiply the hard way, look into Boothe's Algorithm, it deals with more than 1 bit at a time but it is still iterative.https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithmWhen I wanted to do non-restoring division on signed integers (2's complement), I had a heck of a time getting from what was in the textbook down to something that resembled VHDL. Then I stumbled across a book that had some microcode for the operation and just copied it. I wish I had seen this paper back then:http://www.ijareeie.com/upload/2013/july/59_VHDL.pdfThere are hundreds of web sites and text books that cover computer arithmetic.

author: nctnico
author_rank: Super Contributor
timestamp: August 24, 2016, 12:43:40 am
content: I'd use the * in VHDL and let the synthesizer deal with it. Doing it yourself is likely similar to try and come up with better code than a C compiler / standard library does.

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2016, 05:43:37 am
content: reasons to do so: don't underestimate the didactical purpose

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2016, 05:47:15 am
content: Quote from: rstofer on August 23, 2016, 11:46:32 pmgood, that's a key to google for

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2016, 06:01:35 am
content: Quote from: nctnico on August 24, 2016, 12:43:40 aminteresting, I am looking at some projects in OpenCores, and it seems they have different ideas and behaviors about that, e.g. the Plasma's author used a "*", whereas the Ion's author did something strange which I can't understand, and so on

author: legacy
author_rank: Super Contributor
timestamp: August 24, 2016, 06:04:59 am
content: @rstoferVHDL Implementation ofNon Restoring Division AlgorithmUsing High Speed Adder/Subtractorinteresting, that's another key to google for and a good lecture, thanks

author: nctnico
author_rank: Super Contributor
timestamp: August 24, 2016, 09:33:58 am
content: Quote from: legacy on August 24, 2016, 06:01:35 amDon't take Opencores projects as examples. Actually the amount of really clever VHDL code you can find is very small.

author: rstofer
author_rank: Super Contributor
timestamp: August 24, 2016, 01:38:57 pm
content: Looking back, I just used the Xilinx multiplier gadget:Code:MULT18X18_inst : MULT18X18port map (P => Product,-- 36-bit multiplier outputA => Multiplicand,-- 18-bit multiplier inputB => Multiplier-- 18-bit multiplier input);In my case, I was using 16 bit 2's complement so I just extended the sign bit two places to the left. Notice that the multiplier is not a clocked process. It must be one big ball of logic. I didn't check the datasheet to see how fast it can run nor did I look to see how long the operands are stable before I snag up the result. If I were pushing the Spartan 3 I would probably have to do some research.

author: legacy
author_rank: Super Contributor
timestamp: August 25, 2016, 03:17:39 pm
content: which is the fastest division algorithm ?

author: coppice
author_rank: Super Contributor
timestamp: August 25, 2016, 03:36:58 pm
content: Quote from: rstofer on August 23, 2016, 11:46:32 pmThe key feature of Booth's algorithm is not that it deals with multiple bits. All the algorithms I know of can do that. Booth is distinctive because its naturally 2's complement. Wallace, and other approaches, generally work with unsigned numbers. You need to wrap them in extra logic, with extra delays to achieve a 2's complement multiplier. This can be good or bad. For most DSP you only want a signed multiplier, so Booth is a natural choice. For an ALU you might want both signed and unsigned modes. Wallace might then be a better choice.

author: rstofer
author_rank: Super Contributor
timestamp: August 25, 2016, 04:53:54 pm
content: Xilinx doesn't say how they build up the 18x18 multiplier in the Spartan 3 but it may very well be a Wallace tree because it is unclocked. The Wallace tree is just a big fur ball of logic.http://www.xilinx.com/support/documentation/application_notes/xapp467.pdfIn my case, I was only interested in 16 bit 2's complement arithmetic because the computer I was emulating used only that format.As to division, there are 3 broad approaches: Shift and Add/Subtract, High Radix and Convergence. Of the Shift and Add/Subtract type, non-restoring is probably a bit faster but if it is, it will only be by a cycle of two. Both obtain k bits in k cycles plus something for overhead and this is where things will vary.High Radix is trying to do multi-bit division that I haven't thought much about.Look for SRT algorithms because they try to do multi-bit division using a lookup table.Convergence uses an iterative Newton-Raphson scheme (or similar) to converge on a solution. It will use a lot less cycles on a large word size. One application is when instead of dividing as n/d, they first find 1/d and then multiply by n. Clearly, that gets into some kind of fractional notation.There are MANY discussions on the Internet and a couple of books seem to be useful:"Computer Arithmetic Algorithms and Hardware Design" - Behrooz Parhamihttp://www.alibris.com/Computer-Arithmetic-Algorithms-and-Hardware-Designs-Behrooz-Parhami/book/8234663?matches=42I don't think I would buy the $600+ offering. They like that book more than I do!"Synthesis or Arithmetic Circuits" - Deschamps, Bioul, Sutterhttp://www.alibris.com/Synthesis-of-Arithmetic-Circuits-FPGA-ASIC-and-Embedded-Systems-Jean-Pierre-DesChamps/book/28466467?matches=16A little more reasonable! This book has a lot of pseudo code that makes the algorithm more clear.There are many other books on the subject.The thing about division is that it is seldom used. It is worth spending a little time researching solutions but, in the end, non-restoring 2's complement gets it done. Especially for short word lengths. For a 64 bit machine, maybe the Newton-Raphson approach is a lot better.

author: coppice
author_rank: Super Contributor
timestamp: August 25, 2016, 05:03:44 pm
content: Quote from: rstofer on August 25, 2016, 04:53:54 pmBoth Wallace and Booth can be inplemented as a ripple through logic array, typically with some carry speeds ups. They can also both be implemented as a partitioned tree, with one or more registers creating a pipeline.Quote from: rstofer on August 25, 2016, 04:53:54 pmThe are more than 3 broad approaches. If you have a single cycle multiplier you can wrap a successive approximation register (SAR) around it, just like many ADCs are a DAC with a SAR wrapped around it. You can spin that into a square root unit, too. Just feed the same number into both multiplier inputs.

author: legacy
author_rank: Super Contributor
timestamp: August 25, 2016, 05:33:42 pm
content: that's my toy division algorithm, it calculates correctlybut for a word of 32bits it takes 35 clock's ticksit needs "some" work( oh well, a completely erase and rewindI'd better go for the newton_raphson's method)

author: legacy
author_rank: Super Contributor
timestamp: August 25, 2016, 05:36:18 pm
content: @rstofer@coppicethanks for your advice

author: rstofer
author_rank: Super Contributor
timestamp: August 25, 2016, 07:25:42 pm
content: Quote from: legacy on August 25, 2016, 05:33:42 pmNot necessarily...Nevertheless, here is a paper on the Successive Approximation Algorithm:http://www.ijiee.org/papers/173-E0005.pdfThe algorithm takes as few as 2 states, as many as 34 states but averages around 4. That's pretty fast!They also show restoring as being 1 state faster than non-restoring but I wonder if that is just for unsigned.

author: exmadscientist
author_rank: Frequent Contributor
timestamp: August 26, 2016, 04:23:08 am
content: As a point of comparison it might be worth looking at DIV instruction latency on modern CPUs, for example as tabulated by Agner Fog for x86 in his optimization manuals, section 4:http://www.agner.org/optimize/#manuals. Now admittedly this is a very biased sample -- dedicated designs with large teams, plenty of gates to burn, targeting very high clock rates -- but suddenly 35 clocks does not look so bad at all!

author: legacy
author_rank: Super Contributor
timestamp: August 26, 2016, 11:44:46 am
content: is there an ALU's source code to look for, as example of *good* implementation ?it seems there are no examples about the integer division

author: legacy
author_rank: Super Contributor
timestamp: August 26, 2016, 12:18:21 pm
content: ideas to Speed up the slow integer division algorithmMore difficult problem -- you have no hardware divider, you can't use built-in hardware multipliers because you don't have/can't use them, and traditional division methods like the Grade school algorithm: long division are just too slow, so, what to do?Find alternative solutions: Multiply by the reciprocal A / D = A * (1/ D) looks interesting !!!(1/D) ---> Use Newton's method for calculation of the reciprocal of Dit's calledNewton-Raphson,it uses Newton's method to converge to the quotient, its strategy is to find the reciprocal of D, and multiply that reciprocal by N to find the final quotient Qit sounds great, it can also be Pipelined, and it's very fast (quadratic convergence), and so on ...... unfortunately it requires conversion to/from fractional or still worse floating-point

author: rstofer
author_rank: Super Contributor
timestamp: August 26, 2016, 04:39:03 pm
content: Quote from: legacy on August 26, 2016, 12:18:21 pmI don't think you need to find the reciprocal of N, only D. N * (1/D) => N/DWhat device are you using that doesn't have a multiplier? In fact, how did you decide to do multiplication?Pipelining helps if you are doing lots of consecutive divisions but it does nothing to help one division in a long sequence of other instructions unless, by chance or clever application coding (compiler code generation), you don't need the result immediately.Successive Approximation looks good except for the bit where it only works for unsigned division. I'd have to think about how to use it with 2's complement. Having to convert to unsigned is a PITA because it takes extra cycles on both ends of the algorithm.MIPS used the same sequential hardware for both multiply and divide. See "Computer Organization and Design" - Patterson and Hennessy. I don't see a clear description of how they handled both signed and unsigned but they did.http://www.alibris.com/search/books/isbn/9788181475343I had to buy my copy from India! I'm not sure why the publishers sell books in foreign markets for FAR LESS than they sell here. Kind of like pharmaceuticals.SRT is also interesting. It is discussed here:http://people.irisa.fr/Nicolas.Veyrat-Charvillon/files/articles/SPIE_2005.pdfMore on 'divgen' discussed in the paper above:http://lipforge.ens-lyon.fr/www/divgen/

author: legacy
author_rank: Super Contributor
timestamp: August 26, 2016, 04:47:38 pm
content: Quote from: rstofer on August 26, 2016, 04:39:03 pm(1/D) is fractional_tyou have to convert N into fractional_t: N --> N~then you can multiply N~ x 1/D, and you get a fractional_t number, Q~then you have to convert Q~ into integer, Q~ --> QQuote from: rstofer on August 26, 2016, 04:39:03 pmalready implemented, it takes 2 clock's ticksQuote from: rstofer on August 26, 2016, 04:39:03 pmI don't need itQuote from: rstofer on August 26, 2016, 04:39:03 pmI have already implemented something similar, and the integer-division takes too long, 36 clock's ticks for 32 bit, anyway I have solved the unsigned/signed problemQuote from: rstofer on August 26, 2016, 04:39:03 pmyup, thanks for the link

author: rstofer
author_rank: Super Contributor
timestamp: August 26, 2016, 07:12:29 pm
content: I'm not convinced you need to convert N. It is a whole number. OTOH, I haven't tried every possibility.6 / 4 = 1 with a remainder of 21 10 -- 6 as a whole number, I just aligned the digits for giggles0.01 -- 1/4===1.10 => quotient is 1, remainder is 1/2 which when converted is 2I only tried a few test cases and I certainly don't know how to mechanize the creation and extraction of the fractional parts but it seems to work. Maybe it breaks down for negative numbers...Unless there is some super fast way to create reciprocals, I'm not sure I see any benefit to the algorithm.

author: hamster_nz
author_rank: Super Contributor
timestamp: August 26, 2016, 10:23:54 pm
content: Quote from: rstofer on August 26, 2016, 07:12:29 pmEarly Cray supercomputers used reciprocal then multiply. They were pretty smart designers.....

author: legacy
author_rank: Super Contributor
timestamp: August 26, 2016, 11:35:26 pm
content: I have also *a lot* of problems withcordic/16bite.g. cos(0) is -1, because 0x8000 is -10x7fff is +1, just 1 bit of difference makes the difference(those problems are common with fractional_t)

author: rstofer
author_rank: Super Contributor
timestamp: August 27, 2016, 03:53:05 pm
content: Quote from: hamster_nz on August 26, 2016, 10:23:54 pmI wonder if the CDC 6000 series also used it. Considering the 60 bit integer word size, anything that works in log(n) versus linear in n would be a really big deal.The thing is, CDC converted fixed point operands to floating point before performing the multiply/divide operations and then converted back to fixed point. This took several steps in software. Page 3-21 here:http://www.textfiles.com/bitsavers/pdf/cdc/6x00/60100000D_6600refMan_Feb67.pdfCray does pretty much the same thing. See 2240004 3-18 here:http://ed-thelen.org/comp-hist/CRAY-1-HardRefMan/CRAY-1-HRM.html#p3-19The CDC and Cray computers were designed for scientific computing. Integer arithmetic was a side issue, the CPUs were designed to expedite floating point. Both computers had long and short integers. The floating point accumulator in the CDC was 96 bits wide!The CDC machines were impressive! I have often wondered how many FPGAs it would take to replicate one of these machines and how performance would compare. Lacking software to run on the new machine makes the project pretty much worthless.

author: rstofer
author_rank: Super Contributor
timestamp: August 27, 2016, 11:12:06 pm
content: Back to division: For restoring division, skipping over zeros saves a bit of time if shifting is essentially free. I haven't seen an article re: skipping zeros for non-restoring because we are delaying the correction for having subtracted erroneously.

author: legacy
author_rank: Super Contributor
timestamp: August 28, 2016, 02:08:10 pm
content: Xilinx DSP48 has 24bit multiplying inputSpartan3 and Spartan6 are interesting

author: rstofer
author_rank: Super Contributor
timestamp: August 28, 2016, 04:22:46 pm
content: Quote from: legacy on August 28, 2016, 02:08:10 pmhttp://www.xilinx.com/support/documentation/white_papers/wp277.pdf

author: Rasz
author_rank: Super Contributor
timestamp: August 28, 2016, 07:00:54 pm
content: Quote from: rstofer on August 25, 2016, 04:53:54 pmThis reminds me of 3DFX. Texture mapping requires division per pixel (perspective correction).Gary Tarolli:https://youtu.be/3MghYhf-GhU?t=45m

author: rstofer
author_rank: Super Contributor
timestamp: August 28, 2016, 09:55:40 pm
content: Quote from: Rasz on August 28, 2016, 07:00:54 pmA very interesting video. I bookmarked it for some time next week when I have more time.One thing they brought up about division is that for 3D graphics, you don't have to have a perfect answer. Approximations can be good enough. This is not going to be the case for numeric processes.

author: Rasz
author_rank: Super Contributor
timestamp: August 28, 2016, 10:02:58 pm
content: Quote from: rstofer on August 28, 2016, 09:55:40 pmdepends, its perfectly fine for neural networksthere is whole R&D movement for probabilistic computinghttp://www.nature.com/news/modelling-build-imprecise-supercomputers-1.18437

author: hamster_nz
author_rank: Super Contributor
timestamp: August 28, 2016, 10:07:23 pm
content: Quote from: rstofer on August 28, 2016, 09:55:40 pmBut isn't that the great thing about FPGAs? Unlike designing a CPU's division unit, with an FPGA you don't have to do things perfectly, only perfect enough to meet your needs. For example:http://ieeexplore.ieee.org/document/7393152/Accurate forecasts of future climate with numerical models of atmosphere and ocean are of vital importance. However, forecast quality is often limited by the available computational power. This paper investigates the acceleration of a C-grid shallow water model through the use of reduced precision targeting FPGA technology. Using a double-gyre scenario, we show that the mantissa length of variables can be reduced to 14 bits without affecting the accuracy beyond the error inherent in the model. Our reduced precision FPGA implementation runs 5.4 times faster than a double precision FPGA implementation, and 12 times faster than a multi-threaded CPU implementation. Moreover, our reduced precision FPGA implementation uses 39 times less energy than the CPU implementation and can compute a 100×100 grid for the same energy that the CPU implementation would take for a 29×29 grid.

author: rstofer
author_rank: Super Contributor
timestamp: August 28, 2016, 10:25:01 pm
content: Quote from: hamster_nz on August 28, 2016, 10:07:23 pmReal world problems are often like that. You can't measure to as many places as you can calculate. It's pretty silly to carry around 15 digits after the decimal. Maybe I can measure with a micrometer to 4 fractional digits. And I'll still be off unless I am in an environment that mimics the calibration lab in terms of temperature.OTOH, 4 / 2 still has to come out as 2. We don't tolerate approximations for integer arithmetic.

author: nctnico
author_rank: Super Contributor
timestamp: August 28, 2016, 11:02:16 pm
content: Quote from: hamster_nz on August 28, 2016, 10:07:23 pmWhen reading this I can only think of one thing they missed: CUDA!

author: legacy
author_rank: Super Contributor
timestamp: August 29, 2016, 07:39:21 am
content: Quote from: Rasz on August 28, 2016, 07:00:54 pmI wonder about Silicon Graphics/SGI (1)what they implemented in hwI know how fast it is, I own an IP30a machine made by them in 2002(1) today they are HP(e)Hewlett Packard Enterprisebought SGIfor ~275 million of dollars