Signal inegrity analysis - Page 1
Forum section: electronics / general

author: xzswq21
author_rank: Frequent Contributor
timestamp: January 20, 2018, 07:26:18 pm
content: HelloI have designed a PCB included ADC,DAC, OP-amps, Clock chip ,... in Altium Designernow I want to analysis the bus to check the cross-talk, impedance and ....How should I analyze it?Thanks

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: January 22, 2018, 04:30:28 pm
content: Few options, depending on your budget and accuracy of the results you need. You can run it through some parasitic extraction tool and simulate with that. It will map the rough parasitics to regular spice lumped components (resistors, capacitors, inductors, etc.) which you can then just simulate with your regular SPICE simulator.Alternatives are EM simulators, like the things CST, HFSS, ADS offer. But these are very, very expensive and very complex.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 22, 2018, 05:51:59 pm
content: Not so crazy -- if you have IBIS models on all components, and you're licensed for the Signal Integrity module (which I think comes default, maybe it's not ever done separately), just run it and you're good!Read the official Altium documentation for use.Some constraints:- Impedance only works over a plane. You need to use planes, not signal layers with polygons, for ground references.- It doesn't check if the planes are split (AFAIK). You shouldn't be running traces over splits anyway (note, splits in a single layer are fine, as long as there's a contiguous plane nearby in the stackup).- It only works for traces, and assumes all traces are transmission line structures.- I don't recall if it does crosstalk.- If you have cables between boards, say; well, if IBIS models support that sort of thing, and you can synthesize a model of the cable, then you're good; I'm guessing not, though?- If we're talking fast (fractional ns edge) signals, FR-4 loss is a factor, which, I don't know if it can model it or what. Keep this in mind when targeting eye diagrams.Tim

author: xzswq21
author_rank: Frequent Contributor
timestamp: January 24, 2018, 08:00:47 pm
content: Quote from: T3sl4co1l on January 22, 2018, 05:51:59 pmYes I have placed some unified and solid ground/power planes.there are IBIS models only for ADC, DAC, clock distributor and similar ICs not for Op-amps.... But I think I can do signal integrity analysis for the passive filters on the PCB. (between the Op-amp and ADC)have you worked with HyperLynx?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 24, 2018, 10:23:14 pm
content: Analog paths are about frequency response and linearity, signal quality is more specific to step response for digital signals.In other words, you'd model the analog section separately in SPICE.There's not much point in doing a whole-board simulation. PDN analysis is another one, which might be done as part of signal quality, or modeled during/after layout.Tim

author: xzswq21
author_rank: Frequent Contributor
timestamp: January 25, 2018, 11:12:41 am
content: Quote from: T3sl4co1l on January 24, 2018, 10:23:14 pmThanksactually I have a filter between between a high speed Active buffer (FDA) and ADC. I want to see the frequency response of the filter's layout.which software should I use?I'm very satisfied with LTspice for spice simulation but it doesn't support the layout.Thanks

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 25, 2018, 06:59:54 pm
content: Do it the old fashioned way: measure trace lengths and pad sizes, and add those parasitics to the simulation. Pads can be capacitance to inner plane; traces may be L or LC links if much shorter than the highest harmonic of interest, otherwise you can go all out and use transmission lines. Don't forget to use correct models of the components too. Resistors might be reasonably resistive, but capacitors have notable ESL and inductors have ESR, EPR and EPC. (Some inductors can be modeled very accurately with Coilcraft's simulation model, which however doesn't work directly in transient simulation, but a conversion is possible.)Tim