Calibration of a hig resolution ADC with differantial input stage - Page 1
Forum section: electronics / general

author: Cake
author_rank: Newbie
timestamp: March 02, 2025, 04:28:00 pm
content: Hello there,i have a little project, in which i build my own version of the HPM7177:https://ohwr.org/project/opt-adc-10k-32b-1cha/-/wikis/HomeIts basicly the same differential input stage, a modified reference voltage delivery and a ADS1219 instead of the AD7177-2.Im now starting to characterize the acquisition system.The nonlinearity seems not as expected around zero, see the attached images. I asume this is coming from of my PDV2 Mini Calibratior, as it only works above a view mV from zero (?). Can anyone tell me what the closest is can go to zero with the PDV2 Mini?Also, would there be a alternative, but similar in price, calibratior system which covers the negative range as well?Right now i measured the negative region by switching the input terminals.Could the measured nonlinearity also originate from not yet fully optimized balance of the differential stage?Also, is the overal shape of the nonlinearity i measured usual afor a ADC? I thiink the nonliearity is 80/2^24=~5ppm, which is in the specification range of the ADS1219.cheers

author: Kleinstein
author_rank: Super Contributor
timestamp: March 02, 2025, 05:13:42 pm
content: The jump at zero could be from an residual offset of either the PDV mini or the voltmeter-system to test.There are several ways to instroduce nonlinearity. One may already be at the limits of single OP-amp as amplifier and see output stage cross over errors that may give a few µV. The graph does not show a scale, but judging from the noise the INL error is quite large.The ADS1219 specs don't show very low INL - so it may not be the best choice to start with. Another problem is that the actual INL of those SD ADC chips, especially the lower noise ones also depends on the signal driver and reference circuit and possibly the mayout around the ADC. The actual sampling at the chips is rather fast and the impedance in the 10s of MHz range can matter. So testing the INL of the full system is kind of needed as there can be a contribution of the layout and no so easy parts around the ADC.INL testing is a difficult topic, especially at the low level. The PDV mini is already a reasonble start. A possible extension would be getting an additional stable 1 V range ref. source that could be added in series. This way one can measure around 0 and also test if localized errors come from the source or the meter.One could likely extened the range of the PDV to lower voltages with a divider (like 1:100).One could test the linearty around 0, especially the jump there from recording a slowly changing ramp voltage (e.g. -100 mV to 100 mV over a few hours). This could be a RC discharge/charge or capacitor and current source. After subtracting a smooth background, like a fitted exponential and maybe additional linear and square parts one gets an idea of the so called hard INL (that is the INL with smooth parts like 5th order polynominal removed). If needed one may have to use a few runs for noise. This also helps to see how much is reproducible. This way one can see more localized errors, like a jump around 0 V quite well. There is a chance that much of that jump is only offset and not really INL of the system. It is still possible to actually have a jump at 0 V. So one can not dismiss this without a test.

author: Cake
author_rank: Newbie
timestamp: March 02, 2025, 06:55:17 pm
content: Thanks for the quick reply.In the dataset shown i did not consider the offset of my voltmeter or the offset of my PDVS 2 mini. The calibration table states a offset of -1.87 µV, so the offset of the calibrator allone might not be a dominant effect in this case.I will try to eliminate the offsets in my voltmeter next.