current PCB design best practices are stone-age - Page 1
Forum section: electronics / general

author: FrankBuss
author_rank: Unknown
timestamp: May 25, 2016, 07:06:10 am
content: I just watchedan interesting presentationabout new ideas for circuit and PCB design. He created small building blocks and then wrote some Python scripts to automatically create a Spice model, run a simulation and verify output values, similar to test driven development in software engineering. He can combine the blocks to larger blocks as well and write a test case for it. And other scripts automatically places the blocks on a PCB and connects them according to some higher level description.This reminds me very much to VHDL (hence the title of the presentation, "reinventing VHDL badly"). Back in the old days you had to design logic with lots of logic gates. Later there were PLAs, GALs etc. and ABEL, which made it easier and you didn't have to care about placement and connections anymore. Now we have VHDL and Verilog, and powerful FPGAs, which allows even more high-level descriptions of circuits. And nobody cares about the placement of the gates anymore, or how the lookup tables are configured to implement the function (except for some special cases, like high speed designs, where you want to place some functions near the pins).PCB design is still pre-PLA, where you have to place and route individual resistors etc., at least with the programs I know like Eagle or Altium Designer. Is there a professional PCB EDA program, where you can easily create blocks, test it with test cases in a circuit simulator, combine it to bigger blocks and automatically place all components on a board and auto-route it (like VHDL synthesize), including constraints, like don't route the big power supply trace near the 24 bit ADC inputs (like VHDL timing constraints) ?It would be nice to have something like VHDL for circuits. You would describe a circuit in a high-level language, then hit the compile button and you get the routed board. Write a testbench and hit the simulate button to create a Spice circuit, simulate it and the testbench verifies it.

author: ataradov
author_rank: Super Contributor
timestamp: May 25, 2016, 07:16:11 am
content: Quote from: FrankBuss on May 25, 2016, 07:06:10 amAuto routers and auto placers existed for decades. The quality of the output varies, but so does the quality of VHDL synthesis tools.For a tight and heavy FPGA project you will do a lot of manual placement and baby sitting the placer.

author: FrankBuss
author_rank: Unknown
timestamp: May 25, 2016, 12:19:09 pm
content: I worked on a FPGA project with a big Cyclone IV, which was over 90% full, with 100 MHz signals, and didn't need to do any manual placement. And there was never a problem with the VHDL synthesis, when my testbench worked and all timing constraints were right (except occasional bugs of the tools). Of course, it is not a Stratix or Virtex and not very fast. I guess this can change with really complex projects with faster signals. I know of only one project where manual placing was necessary for some high speed serial decoder near the pins.Do you have examples for auto placers? Looks like Cadence can do it, even with constraints to do something useful for analog components, but I've never used this program. I know, some people here hate auto-routers and auto-placers and think it is some kind of art and not just another mundane engineering task that will be automated somedayhttps://www.eevblog.com/forum/suggestions/future-content-suggestion-auto-placement-(not-auto-routing)/

author: nctnico
author_rank: Super Contributor
timestamp: May 25, 2016, 03:11:01 pm
content: IMHO it depends a lot on how easy these tools are to drive. In many case you'll need to set a lot of parameters which come into play when creating a PCB like controlled impedances, maximum crosstalk coupling, currents, heat dissipation, maximum resistance between components, etc, etc. By the time you have set these you are probably far along by just placing the components by hand.

author: batteksystem
author_rank: Regular Contributor
timestamp: May 25, 2016, 03:17:01 pm
content: One problem with the auto router is it require too much configuration to provide an acceptable output. This is because different from logic, when we place components they have different kind of characteristics which is not understood by the auto router. Therefore, you need to input a lot of information to tell the auto router like what "class" the trace is belong, how width it need to be, and how far or how tight a group of decals need to be put close to each other.On the other hand, our brains already know all this and can place them directly without thinking. I think auto router do have benefit when you are routing >1000 traces.

author: tszaboo
author_rank: Super Contributor
timestamp: May 25, 2016, 03:37:51 pm
content: http://www.altium.com/video-how-employ-snippets-design-reuseI will just put this link here, so it does not get lost.

author: FrankBuss
author_rank: Unknown
timestamp: May 25, 2016, 03:59:02 pm
content: Quote from: nctnico on May 25, 2016, 03:11:01 pmMany of these parameters could be set automatically. For example you could create a testbench with the required input voltage and the software could even choose a 1206 resistor because of the higher heat dissipation and chose 16 mil traces instead of 10 mil. Might be useful to override the defaults for some cases, but it should be possible to automate many things.

author: FrankBuss
author_rank: Unknown
timestamp: May 25, 2016, 04:03:42 pm
content: Quote from: NANDBlog on May 25, 2016, 03:37:51 pmThis looks painful. 6 minutes to use a snipped, manual renumbering etc. Imagine you would have a Verilog for circuits and you could just write "include powersupply; supply1=new 5Vsupply(); supply1.in = header-in; supply1.gnd = header-gnd; supply1.out=amplifier1.vcc;" in a few seconds, hit "compile" and you get a nicely drawn circuit and the fully layouted board.

author: ataradov
author_rank: Super Contributor
timestamp: May 25, 2016, 04:14:01 pm
content: Quote from: FrankBuss on May 25, 2016, 12:19:09 pmI never had to do it myself, but I've seen Xilinx MicroBlaze source code and quite literally everything there is manually tied to specific locations. MicroBlaze is a reusable component, of course, but still. I've also worked with a team of people doing highly structured designs (like banks of filters, correlators, specialized signal processing stuff) and they always did manual placement of main components for this stuff, since automatic placer was not good enough.Quote from: FrankBuss on May 25, 2016, 12:19:09 pmVHDL deals with relatively simple basic blocks and there is no real penalty for using a bit more than needed, you don't pay extra (unless you have to use a bigger FPGA, of course). In a real world you pay extra for every component and making automated tool smart enough is just not going to happen.Quote from: FrankBuss on May 25, 2016, 12:19:09 pmNot really. I never used them, but I've seen one as early as P-CAD 4.5 (for DOS), so I assume in one way or the other all tools like this must have this functionality.

author: tszaboo
author_rank: Super Contributor
timestamp: May 25, 2016, 04:40:13 pm
content: Quote from: FrankBuss on May 25, 2016, 04:03:42 pmI dont think I would like for any machine to automatize my job (robots, everyone run!).There are few automatizable parts of a schematic. I never had dozens of opamps in series, doing filtering. I had complicated designs though, where the architechture phase was months to complete, even after we know all the building block possible.I dont know what part of the layout you want to automate. The design I'm working on now has 3G modem and DDR ram. My previous job had LTZ1000 and high power opamp which was dissipating heat. Even before that I was re-designing a PCB for lower cost. Tell that to a machine. And then there is DFM, DFT and everything else, which I'm really not sure how would you translate.I never had 10000 uniform "whatever" component to be routed.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 26, 2016, 04:15:43 am
content: Quote from: FrankBuss on May 25, 2016, 04:03:42 pm[Jokingly,]Ahh, you digi-kiddies are so naive. You have it easy: a digital signal propagates down a wire, and dead-ends. It goes into some gates, and that's end of story.Real white-beard burly-man analog signals go back and forth. Wires obey reciprocity: there is never action without reaction. You can't simply place a power supply, without knowing how much current might be drawn from it! You can't place an RF amplifier, without a specified system impedance! You can't tune a filter without a defined frequency!...But seriously, it would seem the sheer magnitude of complexity, and relative lack of demand ("screw it, we'll just throw it in a DSP!"), has obviated attempts at synthesized analog circuitry. At least, that we know of...They even tried analog computers, where between the frequent use of buffering amplifiers, and circuits with lightly-loading inputs, they can avoid reciprocity for the most part. It didn't last long, though. (Scarily: mechanical computers had been in use for quite some time as well, and usually have to obey reciprocity even more strongly than analog circuits! Designing some of those beasts must've been such a chore, nevermind machining the thousands of tiny parts needed to build them!)FWIW, IIRC, Verilog or one of the HDLs canspecifyanalog circuitry just fine. Perhaps more to the point: SPICE netlists specify circuitry just fine, too. But AFAIK, neither one provides much semantic assistance, beyond compartmentalizing building blocks (blocks, instances, subcircuits, whatever) and basic type checking. Strong typed languages are one thing, but the equivalent for analog circuitry must include the source's load characteristics as well as the load's sourcing characteristics!A little more background on reciprocity:Newton's law (action and reaction) is a succinct statement of the mechanical version. More broadly, it's a conservation law; a symmetry of the medium. In circuits, we have Kirchoff's laws. In any case, any input and outputs from a system (whether it's a black box full of cogs with shafts on the outside, or a black box full of components with wires on the outside) must obey these rules.Now, if we have an external source of power, we can conditionally divert some of the input or output "force" (force, torque, pressure, voltage, whatever..) to the supply, and violate reciprocity between any remaining set of shafts.A digital logic gate does this by drawing supply current to force the output around. In turn, some of the output voltage is fed back to the input, through various physical means (most often capacitance). Which means, a change in the load characteristic can still have some effect on the input characteristic, though less than if the gate were not present. Example: a 74HCU04 (unbuffered, so, a single CMOS inverter stage) will read less input capacitance when the output is shorted (held at a constant voltage), than when it's allowed to move on its own (where Miller effect takes place). But a regular 74HC04's input characteristic will change only imperceptibly, because it contains three inverter stages in cascade. Each stage is nonreciprocal (allowed because output power is sourced from the supplies rather than the input), but not completely so; for N stages in cascade, the nonreciprocity goes as R^-N, so if the one stage is at least modest, then feedback, from the output proper, very quickly becomes negligible!This is what's so easy about digital logic. You can click pieces together without a care in the world for anything going "backwards". If nothing else, the synthesizer knows to keep limits on the number of gates connected together, and to add buffers as needed, to transparently maintain that rule for you.A lot of analog circuitry is about this, too, though. One of the challenges of RF circuitry is building an amplifier with good isolation, i.e., low backwards feedback. Indeed, if backwards feedback were zero, the available (stable) gain from a stage could be infinite! Instead, such circuits oscillate, or are only stable with very particular input and load impedances. It's desirable to have isolation between antennae (so internal signals don't go back out on the air), filters (so the filter's frequency response isn't upset by reflected power), mixers (so the undesired frequencies don't go where they're unwanted), and so on.Tim

author: batteksystem
author_rank: Regular Contributor
timestamp: May 26, 2016, 06:10:38 am
content: Quote from: NANDBlog on May 25, 2016, 04:40:13 pmOn the other hands, there are definitely semi-automation like you can repeat some of the hand-drawn schematics (example: input stage, output stages of a mutli-channel data acquisition device). However, it is only possible if you standardized that circuit, while majority of the circuit have to be thought and drawn by engineer which would be and need to be different each time.

author: Ian.M
author_rank: Super Contributor
timestamp: May 26, 2016, 06:44:13 am
content: Then you've got stuff like unexpected electromagnetic, thermal, and even mechanical interactions between components. The EM stuff can be modelled, but the component manufacturers usually don't provide enough data to do so. The thermal stuff is trickier - without a good model of the airflow over the board, and a deep understanding of what components and subsections are thermally sensitive, its impossible to make intelligent placement decisions. Mechanical issues are extremely intractable. e.g. you have a relay on the board or SMPSU magnetics, and you have sensitive nodes with large ceramic capacitors, you may have to switch to a capacitor type that has a less pizeoelectric dielectric if it is being excited by vibrations from the relay or magnetics. Move a mounting hole half an inch, add a heavy or large area component, or change the switching frequency slightly and the mechanical vibration nodes and antinodes move round the board unpredictably, changing which capacitors will be affected by the vibration.A GOOD human designer is aware of potential interactions, and tries to minimise their effect on the circuit. Short of a revolutionary breakthrough in true A.I, I don't expect it will ever be possible to automate this.

author: John Coloccia
author_rank: Super Contributor
timestamp: May 26, 2016, 08:25:23 am
content: Quote from: ataradov on May 25, 2016, 04:14:01 pmXilinx's software generates all of that for you. It's actually quite slick.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: May 26, 2016, 08:58:34 am
content: I had worked with Orcad in the 80's and when I took up electronics a couple of years ago and looked at Eagle, my heart sank. Nothing had changed!I would envision a model-based tool where all relevant information is specified in related models. The current way of working (for most tools/all tools I know) mix too much different information domains in the same model, for example the schematic. Why not have a logical schematic that has the entire circuit spelled out. Then a related model that specifies constraints on those nets and a separate model that defines how the circuit is 'deployed' - how many pcb's how they are connected etc, - the physical schematic. Case design etc could be integrated. A model for simulation (input stimuli, output validation), one for thermal stuff, a model for footprints etc. Then the design of the individual PCBs that can draw on all these models to determine how to layout the components.This is how I would do it...

author: tggzzz
author_rank: Super Contributor
timestamp: May 26, 2016, 09:17:05 am
content: Quote from: FrankBuss on May 25, 2016, 04:03:42 pmAh. Someone that thinks their circuits are digital and that wires are wires and that ground exists. The former is only true in femtoamp and photon-counting circuits, and the latter only has any validity under very restricted circumstances.As an illustration that wires are more complex than most people imagine, what's the transfer function between each of the connectors in this circuit:http://paginas.fe.up.pt/~hmiranda/etele/microstrip/hybrid_ring_cpl_1.jpg(assume a solid groundplane on the underside of the PCB).And, obviously google for terms such as "signal integrity" "ground bounce" "EMI/EMC", and then readhttp://www.thehighspeeddesignbook.com/The core problems aremodels (e.g. as expressed in an HDL or Spice) are models; by definition they are a simplification that omits many detailseven if the CAD systems could take all constraints into account, it will take a very long time to specify all the necessary constraints and to ensure the constraints do permit a solution

author: ataradov
author_rank: Super Contributor
timestamp: May 26, 2016, 04:04:53 pm
content: Quote from: John Coloccia on May 26, 2016, 08:25:23 amYes, but behind the scenes, there was a Xilinx engineer who manually placed logic and registers in specific slices. This part is typically encrypted and closed from your eyes.

author: rfeecs
author_rank: Frequent Contributor
timestamp: May 26, 2016, 09:51:31 pm
content: Keysight ADS does co-simulation of Schematic, Layout, EM and Electro-thermal simulation:https://youtu.be/ChZcUpH0rmkNational Instruments Microwave Office is similar.I believe several of the high end simulators have these capabilities.

author: altaic
author_rank: Unknown
timestamp: May 26, 2016, 10:05:33 pm
content: The thoughts and arguments in this thread come up time and time again, but it seems everyone focusses on the tool being crap. Tools for FEM/FEA  are not crap, and good ones have existed for ages; automatic EM, thermal, and mechanical analysis is not impossible, nor improbable even in the next few years. It will be a great day when FEM, device simulation, and auto-routing come together in a sensible manner. But, as Ian.M pointed out, the crux here is that device manufacturers generally do not provide good enough models, or even decent data sheets in most cases.The solution is obvious: force manufacturers produce good models. How? Make better tools for producing good models cheaply. Then let capitalism do its thing: the value of the better (cheaper, faster, and higher quality) auto-routing process rewards supporting manufacturers with business, and punishes non-supporting manufactures with loss of business. Alternatively, 3rd parties may produce good models and sell them.As other processes (e.g. Occam ) emerge, manual layout will become much more difficult and the benefits of automatic layout will be overwhelmingly clear. I see automatic layout becoming the conventional practice as an eventuality, not a mere possibility as most suggest.https://en.wikipedia.org/wiki/Finite_element_methodhttps://en.wikipedia.org/wiki/Occam_process

author: John Coloccia
author_rank: Super Contributor
timestamp: May 27, 2016, 12:03:47 am
content: Quote from: ataradov on May 26, 2016, 04:04:53 pmI'm afraid I don't understand what you mean. At some point, something has to put everything somewhere, and presumably someone had to write some sort of compiler/synthesis/whatever tool to do it. Actually, if you look at the output from the synthesis it's different every time. Normally, you save the output as part of your source control because it's not guaranteed to be the same (and usually isn't), and you don't want to risk some timing problem or other problem you overlooked creeping into your system.You can't just toss a pile of silicon in a bucket and expect transistors to pop out because you will it. I don't see why someone would expect to toss a bunch of components at a computer and expect it to figure out your design intent either. Yeah, you can write a bunch of rules to explain the intent, and maybe that's even useful for some limited, repetitive or very similar tasks, much like software engineers do, but often it will be simpler and quicker to just do the task than try to explain how to do the task. It's not like the engineers behind these products are stupid. It's a far more difficult problem than you might imagine.

author: ataradov
author_rank: Super Contributor
timestamp: May 27, 2016, 12:08:47 am
content: Quote from: John Coloccia on May 27, 2016, 12:03:47 amNot in case of Microblaze. The MicroBlaze source code fixes registers to specific locations (relative, not absolute).It is written in VHDL, but that code is actually full of explicit placement directives and direct instantiations of primitives. There is not a single MicroBlaze code, there is one for each FPGA architecture. The right one is selected at the time you put it into the project.

author: John Coloccia
author_rank: Super Contributor
timestamp: May 27, 2016, 01:45:30 am
content: You're configuring a specific piece of hardware to make a processor. Do you expect that the best processor you can make comes from randomly scattering stuff all over the place? Is that how Intel makes a processor?There's a huge difference between software and hardware. When you're dealing with hardware, you're dealing with physical devices that have to respect the laws of physics. With software, I have the option of basically designing the rules, and as long as I design good rules and apply them properly, everything works. With hardware, the laws of physics are the rules, and you must respect them.

author: ataradov
author_rank: Super Contributor
timestamp: May 27, 2016, 01:50:31 am
content: Quote from: John Coloccia on May 27, 2016, 01:45:30 amIf this is directed at me, then no, I don't expect this.But they could have easily created it in pure VHDL and trusted placer and router to do their job. They obviously did not trust them enough and number of times this design is reused justified some manual fiddling.That is basically the same as OP's problem with PCB design - really good results still require a lot of manual input whether it is PCB or VHDL.

author: John Coloccia
author_rank: Super Contributor
timestamp: May 27, 2016, 02:14:09 am
content: Quote from: ataradov on May 27, 2016, 01:50:31 amBut that's the point. How can the tool do the best job when it doesn't understand the design intent? How could it possibly know the most efficient way of laying everything out? How could it possibly know how the APIs are written? Or how all of the various pieces and parts that are configurable are configured? Everyone says that they want to just give it some rules to explain the intent and it should just go do it. Isn't that exactly what they did?

author: ataradov
author_rank: Super Contributor
timestamp: May 27, 2016, 05:37:27 am
content: Quote from: John Coloccia on May 27, 2016, 02:14:09 amThat's my point exactly. And that's the reason why there will never be a good auto-placer and even auto-router.

author: tggzzz
author_rank: Super Contributor
timestamp: May 27, 2016, 07:26:12 am
content: Quote from: John Coloccia on May 27, 2016, 01:45:30 amActually, there are analogous problems with software...Statically compiled languages (especially C/C++) can only optimise based on what can be determinedat compile time. There are many hints that can be given by the programmer, but the compiler may or may not be able to use them. C/C++ is full of problems w.r.t. optimising in the presence of aliasing. I remember the "should we allow the possibility of casting-away-constness" wars for a couple of decades ago. Dynamically compiled languages (e.g. Smalltalk, Java, Self) can make optimisations at runtime that C/C++ cannot.Then look at the hand-written optimisations for inner-loops in, e.g. high-performance computing (HPC) and cryptography.And, of course there are cache problems. Often the HPC mob rearrange their entire program so as to minimise cache misses. (Consider latencies: "cache is the new RAM, RAM is the new disk")And then there are NUMA and network characteristics to be dealt with.Nope, software doesn't "just work".

author: chris_leyson
author_rank: Super Contributor
timestamp: May 27, 2016, 07:48:12 am
content: Quote.Probably spent the best part of a week shuffling small circuit blocks around on a pair of PCBs that are stacked one on top of the other, generate 3D model, inspect 3D model for clearances, move or rotate circuit blocks, repeat etc. Some scripts would probably speed up the 3D file generation but it would be nice if I could lay out both PCBs simultaneously in 3D and then click a button and generate a map showing the clearance between components.As far as 3D layout goes my PCB design tools are stone-age. The 3D modeling constraints probably wouldn't be too difficult to set up, just put bounding boxes around things that have to be constrained to an aproximate area or constrain things to a single axis if things needed to line up, quite a lengthly procedure with todays PCB tools and I would still have to generate a 3D model. Then there are the electrical constraints to consider but I've taken care of most of those by grouping things into small blocks, I've got three switched mode power supplies and 1000Base-T ethernet to consider, thank God there isn't any high performance low noise analog or RF stuff.It's all constraint driven and with todays tools it's quicker to do it manually.

author: tggzzz
author_rank: Super Contributor
timestamp: May 27, 2016, 08:57:26 am
content: Quote from: chris_leyson on May 27, 2016, 07:48:12 amConsidering EMI from SMPSs and that the 1000base-t PHY uses 5-level PAM plus adaptive equalisation, I would have thought youdidhave analogue and RF circuits!

author: chris_leyson
author_rank: Super Contributor
timestamp: May 27, 2016, 09:25:22 am
content: Power supplies sit on the lower PCB and ethernet differential pairs are routed on the top layer of the upper PCB. Transformers are shielded and there are two 35u ground planes between the transformer and ethernet routing, so that should help reduce the effects from leakage inductance. My biggest worry is using 0.5mm flat flex as co-planar wave guide.

author: FrankBuss
author_rank: Unknown
timestamp: May 27, 2016, 01:17:12 pm
content: Quote from: John Coloccia on May 27, 2016, 01:45:30 amThat's only a limitation of the synthesizer. There are many CPU designs on OpenCores which work without problems and which are pure VHDL or Verilog. I guess the tweakings for Microblaze optimize some parts to allow a higher clock rate. I wouldn't be surprised if they are not even needed anymore with improvements in the synthesizer, but of course, nobody changes a running system.Quote from: John Coloccia on May 27, 2016, 01:45:30 amThere is not much difference, just other rules. With (current) software you have some kind of linear processing unit with limited parallel capabilites, temporary (RAM) and permanent (flash/harddidsk) storage, with its own sets of rules how it works and interacts. When you write software, you design it on top of these rules and you can test it on computers if it runs.With something like Keysight ADS, you can design circuits, and simulate and verify it in depth with testbenches. The rules are the physical attributes of the components and how they interact, but you can create a lot of interesting things by combining these components. It is a bit more complicated than software, because it is all parallel and software is more flexible, because software can change software, or learn (neuronal networks etc.) but this is not possible (so far) with circuits: a resistor can't clone and wire itself at runtimebut then most software is very boring and not flexible, too.

author: FrankBuss
author_rank: Unknown
timestamp: May 27, 2016, 01:27:14 pm
content: Quote from: altaic on May 26, 2016, 10:05:33 pmNot very related to the topic, but Occam sounds very cool. Would be nice to see a video of it in action, it's a bit difficult to visualize all the steps described on the Wikipedia page. Does it already work or is it just a concept, or is there a prototype? Does it work for multilayer high density PCBs with big fine pitch BGAs?

author: tggzzz
author_rank: Super Contributor
timestamp: May 27, 2016, 02:04:43 pm
content: Quote from: FrankBuss on May 27, 2016, 01:17:12 pmA key difference is theorderof the complexity, and of emergent behaviour (classic example: which "rule" defining individual grains of sand leads to sand piles being conical with a half-angle of 35 degrees?)1) In the kind of software system you outline, complexity rises vaguely proportionately to the number of components. There are exceptions, of course, especially in a large system made from many components produced by multiple manufacturers , e.g. banking, telecoms, (i.e. more like a typical hardware system)2) With hardware-on-a-PCB system or inside an FPGA, however, the complexity rises as a power (min 2!) of the number of components, simply because there is, in general, a much higher "random" interconnectivity between components. There are exceptions, of course, especially where there is a uni-directional dataflow in the architecture, (i.e. more like a simple software system).(For simplicity, I've ignored the important "abstraction leakages" which make the issues even less tractable. Software examples: cache capacity, page thrashing, NUMA, resource contention. Hardware examples: high clock fanout switching problems, speed of light, analogue effects in nominally digital circuits, component parasitics, non-lumped component behaviour)But don't worry, other people with lots of money to spend have noticed the same routing problems. So,if it is a soluble problem, new tools are just around the corner.But note that caveat!