What Can I Improve on my PCB Design Pt. 2? - Page 1
Forum section: electronics / beginners

author: electroman
author_rank: Newbie
timestamp: October 11, 2024, 05:39:36 am
content: Hello,Thank you to all who have given me advice on the first iteration of my PCB. I have added things like a ground plane, mounting holes, 100nF capacitor in parallel with the 10uF one, organized the wires and ensured none of them weren't too long, thickened power traces, and made sure the copper traces didn't get to close to the edge of the board. I was wondering if there is anything else y'all can spot in the PCB design that shouldn't be the way it is before I try to order it and tinker with it? Any advice for when the testing doesn't go as plan (bc it never does lol).Thank you so much for your help!Attached are the new PCB picturesLink to old post:https://www.eevblog.com/forum/beginners/what-can-i-improve-on-my-pcb-design/msg5671875/#msg5671875Images of new PCB:

author: selcuk
author_rank: Frequent Contributor
timestamp: October 11, 2024, 06:55:58 am
content: -You may place GND vias under the ICs to pour more ground plane on top layer.-Check the silk screen since there are texts on pads.-Did you run DRC? There are tracks very close to pads.-There are unconnected nets. Check the rat's nets and connect all you can see.-When you name a net like 5V2, it may mean 5.2V. Not a problem if you are the only designer on the project. Otherwise confusing.

author: PGPG
author_rank: Frequent Contributor
timestamp: October 11, 2024, 10:17:58 am
content: Quote from: electroman on October 11, 2024, 05:39:36 amBeing too close to the edge refers not only to tracks but to all copper (including zone).

author: tooki
author_rank: Super Contributor
timestamp: October 11, 2024, 10:37:20 am
content: Quote from: PGPG on October 11, 2024, 10:17:58 amIndeed, which is why my suggestion actually deliberately said “copper” and not “traces”.

author: tooki
author_rank: Super Contributor
timestamp: October 11, 2024, 11:04:08 am
content: Quote from: electroman on October 11, 2024, 05:39:36 amSome comments, numbered for ease of replying:1. So… you have a ground plane, but almost nothing connects to it?!? Most of the MLX chips seem to have no ground connections.2. The decoupling caps on the PCA9548 are far from the power input pin where they belong. The idea is to have the caps by the power input, with the other side of the caps dropping down a via to the ground plane. Then the chip’s ground pin also drops down with a via. The ground pour should be kept as uninterrupted as possible. You can additionally use vias to “stitch” the top and bottom layer ground pours, giving it additional integrity. For example, the area just to the left of the MCU connection pads. Via stitching also lets you fix ground “islands” like the ones around MLX6/7/8.3. Additionally, the 5V drops through vias en route to the input pin, so a signal line can make it through. Generally speaking I’d do it the other way, since power traces conduct more current than signal traces.4. Many traces, like Trig6/7/8, take unnecessarily circuitous paths which chop up your bottom ground plane. Some scooting around of top-layer traces would let you make those much shorter. (For example, the ridiculously loopy I2C traces for MLX6.) Also, leave space between bottom-layer traces so the ground can pour between them.5. At the left, there’s a trace that connects MLX6/7/8 that is kept on the top layer, forcing you to drop a power trace (and some other one) to the bottom. Again, I’d do this the opposite.6. Are you sure the MLX pin numbering is correct? It’s hard to tell due to the extremely low resolution of your screenshot, but it looks like they’re not numbered counterclockwise. Double-check this.7. You didn’t follow the advice to abandon 45-degree trace layout for the components at non-45-degree rotation. So you have a lot of really messy traces as a result.8. It’d be a lot easier to check the layout if we had a higher resolution image of the layout, either using transparency so that top-layer copper doesn’t obscure bottom-layer features, and/or with additional, separate images of the top and bottom layers. Similarly, a schematic makes it much easier to understand what’s going on. Best case scenario you even provide the KiCad files.9. It is absolutely unnecessary to start a new thread for a follow-up. You can, and should, reply to your own threads when they pertain to the same question/issue/project/device.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: October 11, 2024, 12:13:21 pm
content: Quote from: tooki on October 11, 2024, 11:04:08 amI would not call this a GND plane. It's just loosely coupled sections of copper. For a "proper" GND plane it has to be a continuous piece of copper with only small interruptions (via holes and short "hop overs" of at most 3 tracks)What a good GND plane is and why it is important does take some study. It's not just pouring ins some copper and calling it good. Rick Hartley has made an excellent video about designing a good GND plane, It's over two hours long and it's important enough to watch it at least twice.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 11, 2024, 12:51:42 pm
content: In addition to tooki his reply,the bottom layer ground plane needs to be redrawn, assuming it is an automated poor. There seems to be a trace added later on that is not cut out in the plane like the others. It runs from U2 down to a pin on MLX1, I guess, as the text is hard to read due to the traces on top of it.Yes it is indeed an improvement on the first version, but still not there.Play with component layout a bit more to optimize on needed track length, like you already did in comparison with the first version. Also try to envision better paths for some of the tracks by looking at the bigger picture. For instance, the 3.3V power supply can be taken from R20 to R1? (near the top mounting hole) via the outside instead of how it is done now. Swap the GND and 3.3V connection pads and bring the supply via the top to R1? Make the trace a bit wider and it will be fine. Brings the need to change the 5V routing too, but can also become easier if you can bring that pad to another spot.Why the big pads for the connections any way?But giving proper advice is not easy with just the PCB layout. Like tooki mentioned schematics can help a lot.I also second tooki his advice to not start a new thread for every iteration of your PCB, but post the new versions, if any, in this thread. This way members that gave advice on earlier drafts see the thread in their "Show new replies to your posts" list and can reply to it if they want.I only noticed your new thread just now and could have easily just missed it as I scan the "Show unread posts since last visit" more quickly on subjects I might find interesting.Edit: fixed some textual errors.

author: temperance
author_rank: Super Contributor
timestamp: October 11, 2024, 01:04:36 pm
content: Quote from: pcprogrammer on October 11, 2024, 12:51:42 pmInputs and outputs of the I2C IC are going to be connected to wires or something to an other board. I don't see any kind of protection on those connections.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 11, 2024, 01:46:23 pm
content: Looking back at the first design, the shape of the PCB has also been changed, so does not seem to be that important and might even be possible to make it less angled and only have the part of a circle cutout at the left bottom.As written in my other post and having looked again at the design,it seems that the MLX ic signals connecting to U2 have pullup resistors, and it is probably easier for the routing to place them near each MLX is instead of near U2.What are these MLX ic's anyway?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: October 11, 2024, 03:30:24 pm
content: The copper zones also seem to extend to the edge of the PCB, and this is not good. Especially for multilayer PCB's (4 or more layers) it is possible that a bit of copper gets smeared out on the sides during routing the PCB out of the big panel during production and this can (and will) create short circuits.It was a small bug in KiCad that this setting was set to zero for a while. This has been corrected a bunch of months ago, but apparently KiCad still uses these settings sometimes. I guess it does not change the defaults after KiCad was installed. You can change it in:PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to edge clearanceSetting this to 0.5mm is plenty, 0.2mm may even be good enough, but in this design there is no need to push it to the limits.

author: tooki
author_rank: Super Contributor
timestamp: October 11, 2024, 05:52:58 pm
content: Quote from: Doctorandus_P on October 11, 2024, 12:13:21 pmI would think that my subsequent comments on how to preserve the integrity of the ground plane would be an indicator that I understand this.

author: dataescher
author_rank: Newbie
timestamp: October 13, 2024, 02:14:30 am
content: Is it designed for test? It's typically good practice to include testpoints on all nets - EXCEPT for high-frequency nets like oscillator pins, USB signal lines (or hf communication nets), sensitive nets around switching regulators. Something you can at least hit with a scope probe if you ever need to. This is in case you need to do any tests in-circuit.