Bandwidth of Logic Analyzer - Page 1
Forum section: electronics / beginners

author: NaxFM
author_rank: Regular Contributor
timestamp: August 05, 2019, 12:54:15 pm
content: Hi guys, I have finally decided to buy an "high end" logic analyzer, specifically the Digital Discovery from digilent.The thing is that I'm very unsure of what the actual bandwidth specification means.I know that usually the bandwidth is the frequency at which a sine wave gets attenuated by 3db, but speaking about logic analyzers, we are talking only about digital signal, so I'm really not sure if the bandwidth follows the same definition as before or it actually means the max digital frequency at which the analyzer works reliably.The digital discovery can sample at 800Ms/s and it has a bandwidth of 100Mhz, so the sample rate is really plenty for the max bandwidth (at least using only 8 channels)Now, my doubt is: what if the bandwidth follows the same rules as with oscilloscopes? In this case I could only reliably use it only for square waves of up to 20 Mhz, so that at least the third harmonics stays within the bandwidth. If that's the case, what's the point of having such high sample rates if 200 or even 100Ms/s would be enough for the job?So, after this unnecessary rant, my question is: what does the bandwidth figure means in logic analyzers?And if the bandwidth follows the same rules as oscilloscopes, do I really need to have at least the third harmonic within the bandwidth or it doesn't really matter since we are talking only about logic states, so the actual waveform is not important?Inviato dal mio Moto G (5S) Plus utilizzando Tapatalk

author: tggzzz
author_rank: Super Contributor
timestamp: August 05, 2019, 05:17:13 pm
content: The significant (time) parameter for logic analysers is the number of samples per second per pin.

author: Gyro
author_rank: Super Contributor
timestamp: August 05, 2019, 05:43:09 pm
content: Thinking of it in bandwidth terms is not very helpful when looking at logic analysers. as tggzzz says, it's all about samples per second.Take a 100MHz logic analyser for example. This will be sampling its inputs every 10ns. This is the minimum time interval that it can resolve.If you want to know the timing relationship between two signals, if they transition within the same 10ns timing window, then it will say that their transition are simultaneous. If they transition in two adjacent timing windows, then their timing relationship can be anywhere between approximately zero (if they occur just before and after a sample) to a maximum of almost 20ns (one at the beginning of one sample window and the other at the end of the adjacent one) but it will report them as being 10ns apart. The same situation applies for individual signal pulse-widths.Some LAs have glitch detection which will flag that a signal has gone from one state to the otherand backwithin one sample period, but this requires significant extra complexity and is not that common.P.S. If the analyser has an external clock input, then it can reduce uncertainty by synchronising the analyser to the system clock of whatever you're looking at. External clock capability is often specified at a lower maximum frequency though.

author: NaxFM
author_rank: Regular Contributor
timestamp: August 05, 2019, 05:53:04 pm
content: Quote from: Gyro on August 05, 2019, 05:43:09 pmThanks for the reply. I understand that, but my doubt is still the same: what does the bandwidth figure means in logic analyzers?If the only thing that matters is sample speed, then with the 800Ms/s of the digital discovery I could measure a 200Mhz square wave without any problem, or even an higher frequency signal, if I want to trade off precision.But the specifications say that the bandwidth is 100Mhz, so my thought is that after that frequency the signal gets so attenuated that maybe it can miss some pulses. After all, there must be an attenuation at higher frequencies at the input of the analyzer.Inviato dal mio Moto G (5S) Plus utilizzando Tapatalk

author: Gyro
author_rank: Super Contributor
timestamp: August 05, 2019, 06:02:36 pm
content: I'm not familiar with the digital discovery spec in particular but it sounds as if the inputs are not capable of toggling faster than 100MHz even if the internal FPGA is sampling at 800MHz....This is not really surprising, it is pretty impossible for ordinary clip leads to toggle at that sort of frequency without glitches, crosstalk and ground bounce (not to mention capacitive loading effects). High-end LAs (eg. Agilent or Tek) have an awful lot of cost tied up in probe technology and terminations, individual screening and ground referencing and minimal loading, to achieve reliable probing at high frequencies. This is not something that you are going to find on low-end LAs. I'm afraid the Digilent doesn't count as high-end in this context.EDIT: Looking at the Digilent Digital Discovery page, I see that they reference a "High Speed adapter" it looks as if this includes twisted pair individually grounded leads with 100R resistors in series at the source end. This is their alternative to High-end probes.https://store.digilentinc.com/digital-discovery-high-speed-adapter-and-logic-probes/

author: tggzzz
author_rank: Super Contributor
timestamp: August 05, 2019, 06:31:51 pm
content: Quote from: NaxFM on August 05, 2019, 05:53:04 pmWhat do you mean "measure a 200MHz square wave" and "trade off precision"? I think you are completely misunderstanding what a logic analyser will do.I suggest you physically draw a 200MHz signal on a piece of paper (1), i.e. with a period of 5ns, 2.5ns high, 2.5ns low.On a separate piece of paper(2) draw a series of dots with a period of 1.25ns (to the same scale, of course!) along the edge of the paper. This is the logic analyser's clock.Put the piece of paper (2) on top of the piece of paper (1).Wherever you see a dot, note whether the corresponding 200MHz signal is high or low; that is what the logic analyser will display.Slide the piece of paper (2) along the 200MHz signal, and repeat.So far, so boring.Now repeat the above, except draw the signal so that it is the same period (5ns), but 1.5ns high and 3.5ns low. That is typical "200MHz" digital signal.Pay particular attention to thepatternof highs/lows you record when the paper (2) is in differing horizontal positions. The pattern will vary.Now reconsider what you might mean by "measure" and "precision".

author: ogden
author_rank: Super Contributor
timestamp: August 05, 2019, 06:50:43 pm
content: Quote from: tggzzz on August 05, 2019, 05:17:13 pmBandwidth of the frontend, connectors and probes is important as well. They use 2.54mm pitch connectors which usually are not speed-specified. Some 2.54 pin headers are specified for PC/104 which is "just" 66MHz. They are using "way too cheap" connectors, could be so that they can't match specs of proper 800MSPS analyzer - that's why there is safety pillow in a form of 100MHz bandwidth. You may be lucky to sample 200MHz signal (using optional "high speed adapter"), but when you are not - remember the specs

author: NaxFM
author_rank: Regular Contributor
timestamp: August 05, 2019, 06:54:56 pm
content: Quote from: tggzzz on August 05, 2019, 06:31:51 pmEnglish is not my first language, I know that sometimes i may seem a bit confusing and confused, I'm sorry.I know what logic analyzers do, I've debugged many microcontroller project with one. When I'm talking about square wave, I always mean a square wave with 50% duty cycle,i should have said that.That is because the only rule of thumb I could find for logic analyzers is that for a square wave with 50% duty cycle, if you want a somewhat precise visualization, you need at least a sampling frequency 4 times that of the wave. That's why I was talking about a 200MHz square wave: the digital discovery has a max sampling rate of 800Ms/s.I know that if one pulse is so short that it's between two samples, then I will totally miss it.So, let me ask again the starting question in a (I hope) more clear way.Does the 100MHz bandwidth of the digital discovery means that I can reliably visualize a 100MHz square wave at 50% duty cycle?My doubt started from the thought that to view a 100MHz square wave on an oscilloscope, you need at least a bandwidth of 500MHz, but that's to see the actual wave, not the logic state.Inviato dal mio Moto G (5S) Plus utilizzando Tapatalk

author: Gyro
author_rank: Super Contributor
timestamp: August 05, 2019, 07:02:01 pm
content: Quote from: NaxFM on August 05, 2019, 06:54:56 pmI would say, yes, youshouldbe able to visualize it, using their High Frequency Adapter, even if you won't have much measurement accuracy. Remember that your system and the LA form a combination though - you will need to provide a good local ground for the twisted pair.Remember that the LA works on Logic thresholds. Even a (correct amplitude) 100MHz sinewave will transition through those logic thresholds.

author: tggzzz
author_rank: Super Contributor
timestamp: August 05, 2019, 07:17:30 pm
content: Quote from: NaxFM on August 05, 2019, 06:54:56 pmI have no idea where they get the 100MHz from; I suggest you look at their forums. If necessary ask the question there.BTW, the analogue bandwidth required to observe a digital signal depends only on the rise/fall time, not the period. The usual rule of thumb is BW=0.35/t, but 0.4 or 0.45 is also used.

author: magic
author_rank: Super Contributor
timestamp: August 05, 2019, 09:57:04 pm
content: Quote from: NaxFM on August 05, 2019, 06:54:56 pmI'm afraid you will only get this answer from somebody who owns that hardware.I can testify that analog bandwidth can be an issue in those USB gadget analyzers. I used to have one, it had some RC networks for input protection and didn't work at bit rates faster than about 30% of its sample rate. I don't remember if the manufacturer specified it for input BW or not and how that spec (if any) translated to the maximum bitrate I observed.If I were to guess, I would say that 100MHz is the -3dB point. A 3.3Vpp square wave still has some significant 100MHz sine component (say, quite likely more than 2Vpp) so even after 1.4x attenuation we are still left with 1.4Vpp swing, which will likely be sufficient for reliable detection by the input buffer, if it uses the usual CMOS threshold of 50% VCC.Quote from: NaxFM on August 05, 2019, 06:54:56 pmYeah, message posted with Firefox from my laptop computer

author: radiolistener
author_rank: Super Contributor
timestamp: August 06, 2019, 02:24:24 am
content: Quote from: NaxFM on August 05, 2019, 06:54:56 pmno, you can only visualize 100 MHz which is synchronized with sampling oscillator of the analyzer. If it will not be synchronized, or if the frequency will be different (even for 0.00001 Hz or less), you will get a jitter. The mistake will depends on sampling frequency. Higher sampling frequency = smaller jitter. But sampling oscillator has it's own jitter, which will affect results for high frequency. So, all depends on what precision you're needsAccordingto the site, Digital Discovery works at 800 MS/s. It means that you can capture up to 400 MHz frequency. But it doesn't means that it will be nice waveform. It just means that you can still measure frequency of the signal up to 400 MHz. All frequencies above 400 MHz limit will be measured incorrectly. They will be captured with aliases.The jitter will be about 1.25 ns. Your 100 MHz signal has 5 ns pulses. But you will see random duty cycle on captured waveform due to the jitter. It will vary within range 37-63% duty cycle.