Concurrency in HDLs (and FPGAs) - Page 1
Forum section: electronics / beginners

author: jeremy
author_rank: Super Contributor
timestamp: January 05, 2014, 06:04:34 am
content: Hi guys,I've managed to confuse myself into a circle here; my understanding of concurrency comes from a more software basis (ie threads) and I could really use some help into decoding what would happen here.I am basically having difficulty understanding how blocking and non-blocking assignment works in terms of the signal cascading through the circuit.Some pseudoverilog I tried to write to demonstrate my problem:Code:module spi_recv (clk, data, d_ready)output data, d_ready;input clkreg [7:0] data;reg d_ready;wire clk;always @(posedge clk)beginif (some_data_is_ready && d_ready == 1'b0)d_ready = 1'b1;end else begind_ready = 1'b0;endendendmodulemodule display_on_leds(clk, leds)output leds;input clk;reg [7:0] leds = {8{1'b0}};wire clk;wire data;wire d_ready;spi_recv spi(.clk(clk), .data(data), .d_ready(d_ready));always @(posedge clk)beginif (d_ready) beginleds[7:0] = data[7:0]; // at what clock cycle does this happen?!endendendmoduleMy question is this: say the spi_recv module sets the d_ready reg to 1 at clock cycle 15 and back to 0 at clock cycle 16. Would the data be sent over to the LEDs register at clock cycle 15? Or 16? or something else entirely? Is that behaviour guaranteed? Would this change if I were to use <= (nonblocking) assignments instead?Thanks in advance for any help, I've been struggling with this one for a while now. I will probably have a whole lot of other questions to add to this depending on the answer

author: Balaur
author_rank: Unknown
timestamp: January 05, 2014, 02:38:33 pm
content: Hi,First, the "&& d_ready == 1'b0" part is not needed nor useful, get read f it.You are not concerned by blocking vs non-blocking in your example.HDL are best understood when looking at the physical implementation.Both "always @(posedge clk)" processes in your example will be synthesized as clock-edge-driven sequential cells, most likely D Flip-flops in sane implementation technology.How did they work? When the clock edge arrives, they sample the data input and at some point after that, they will set the output to the correct value.Now assuming that the some_data_is_ready gets active somewhere inside the clock cycle 14 (i.e. after the clock edge 14), the d_ready gets set at the beginning of the clock cycle 15 (i.e. after the clock edge 15). The clock-edge-driven process (i.e. flip-flop) from the display_on_leds module will sample the d_ready signal on the next clock edge and will see that the d_ready is 1 on the clock edge 16. Thus, the leds will be driven after this clock edge and will be active on clock cycle 16.Basically, you have a pipeline composed of two flip-flops with a latency of 2.If you want to reduce latency, either:- d_ready should be combinatorial, i.e.wire d_readyassign d_ready = (some_data_is_ready) ? 1 : 0;- or a single always process contains everything using blocking assignments (similar to a software program):always @(posedge clk)beginif (some_data_is_ready)d_ready = 1'b1;end else begind_ready = 1'b0;endif (d_ready == 1) leds = ...end

author: jeremy
author_rank: Super Contributor
timestamp: January 05, 2014, 11:38:34 pm
content: Thanks Balaur, that makes sense. If that is the case, how do blocking and non-blocking operators get synthesised? I kind of assumed that non-blocking would somehow involve a pipelined approach, but clearly this is not the case!Also, what is the cost of using non-blocking operators? I presume it limits the maximum clock speed of the design?

author: Balaur
author_rank: Unknown
timestamp: January 06, 2014, 11:40:43 pm
content: Hi Jeremy,If you want to be proficient in HDLs, imagine the circuit and describe it as you see it in your mind.I think that this document will be much better than me in explaining some golden guidelines for a quality implementation:http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=synth-verilog-cummins.pdf''Best regards,Dan

author: marshallh
author_rank: Unknown
timestamp: January 07, 2014, 03:21:01 am
content: Don't mix blocking and non blocking inside the same always block. In synchronous blocks i tend to use <= only.Code:// this is my preferred methodwire [7:0] test = some_signal ^ other_signal;// this is the same thing, but more verbosewire [7:0] test;always @(some_signal or other_signal) begin// this will be a non-blocking assignment// because there were no clocks in the sensitivty list,// this will be combinationaltest <= some_signal ^ other_signal;endNow if you were to include that "test" signal inside a clocked (synchronous) always block like most of the stuff out there, you'd do:Code:reg flag;always @(posedge some_clock) beginflag <= 0;if(test) flag <= 1;end// the synthesizer basically expands the combinational// term "test" inside doing a substituition, so it's like this:reg flag;always @(posedge some_clock) beginflag <= 0;if(some_signal ^ other_signal) flag <= 1;endRead this toohttp://retroactive.be/verilog_tips.pdf

author: jeremy
author_rank: Super Contributor
timestamp: January 07, 2014, 08:21:36 am
content: Wow thanks guys, that helps a ton. Also, nice tips marshallh, worth having that one stashed at my desk I think.

author: codeboy2k
author_rank: Super Contributor
timestamp: January 07, 2014, 09:35:05 am
content: Quote from: Balaur on January 06, 2014, 11:40:43 pmI'm going to fix that for you...if you want to be proficient in HDLs read everything by Clifford E. Cummings, including the link given above by Dan.I think he has a wealth of experience and has produced many documents detailing best practices in all aspects of FPGA and ASIC design using HDLs (although he is mostly a Verilog and SystemVerilog advocate, while I still prefer VHDL)He has co-authored a 31(!) page paper on synchronous and asynchronous resets, and a followup 38(!) page paper aptly named "...., Part Deux ". I didn't really give much thought to resets before reading his papers, but now I realize that an improperly coded reset can add delay, can introduce metastability issues or can turn into loads on a follower FF that you might not actually want.http://www.sunburst-design.com/papers/[many documents are here]Synchronous Resets? Asynchronous Resets?I am so confused! How will I ever know which to use?[31 pages]Asynchronous & Synchronous ResetDesign Techniques - Part Deux[38 pages]