DDR LVDS on Altera Cyclone V - Page 1
Forum section: electronics / general

author: Boscoe
author_rank: Frequent Contributor
timestamp: November 19, 2017, 12:18:28 am
content: Hi all,I have fairly good experience with FPGAs now from the past couple of years. In that time, though, I haven't hit DDR LVDS and deserialisation. In an upcoming project I will be hitting those so would like some pointers.I'm going to be interfacing with a Sony image sensor that has 4 serial data outputs each running at 297MHz DDR, pretty quick. But I don't think I can use a regular LVDS input on the Cyclone V to do this - it's too fast. But the dedicated transceivers on the GX series require a minimum input speed of 614Mb/s so I'm not quite sure how that works.Also, all the data synchronisation and validity signals are embedded in the serial data streams which I need to decode. What are the best techniques to go about this?Thanks for any help.Boscoe

author: nctnico
author_rank: Super Contributor
timestamp: November 19, 2017, 12:24:00 am
content: I guess this would make a good subject for an application note. High speed ADCs have similar interfaces so I would look into that direction. It sounds much like a LVDS ADC interface I worked with using a Xilinx Spartan 6. The Spartan6 has de-serialisers for each pin. Maybe the FPGA you are using has something similar.

author: Someone
author_rank: Super Contributor
timestamp: November 20, 2017, 12:35:46 am
content: Quote from: nctnico on November 19, 2017, 12:24:00 amLacking the dynamic delay compensation that Xilinx offer, there isn't much to describe so Altera put a short section in the Device Handbook for source synchronous interfaces.Quote from: Boscoe on November 19, 2017, 12:18:28 amThere are some good posts on forums around the internet discussing oversampling with the transceivers, probably the only option for that interface speed on a Cyclone V.

author: Boscoe
author_rank: Frequent Contributor
timestamp: November 20, 2017, 11:22:17 am
content: So, having read a little more about the Cyclone hardware and played in Quartus, only 10bit deserialisation is supported. I was thinking of trying to get around this by putting a DDR to SDR block in between the input and the SERDES however the SERDES must be directly connected to the FPGA LVDS pins, makes sense. Looks like I'm going to have to look at other FPGAs unless anyone here knows something I don't.

author: dmills
author_rank: Super Contributor
timestamp: November 20, 2017, 03:41:51 pm
content: The usual way is to follow the 10 bit serdes with a 'gearbox' that takes a few 10 bit words and reorganises them into a 16 bit (or whatever) wordlength is appropriate at 10/16th of the clock rate.Your 297MHz DDR gets converted into a 59.4MHz 10 bit parallel bus (By the IO serdes) which then gets converted into a 37.125MHz 16 bit parallel bus by the gearbox implemented in fabric logic (Or whatever parallel width makes sense for your application, it is just registers, muxes and a small state machine to select the appropriate bits to switch to the output).Now generating the clocks for this whole mess, that is the trick....Regards, Dan.

author: jbb
author_rank: Super Contributor
timestamp: November 21, 2017, 02:20:20 am
content: I think the Cyclone 5 supports LVDS DDR up to 320MHz in -C8/-A7 devices (Cyclone V data sheet, switching characteristics, High-Speed IO specs) with demuxing to parallel data internally. This of course assumes that your data source can be clock synchronised to the FPGA (if not proper Serdes blocks will be required.)

author: jefflieu
author_rank: Contributor
timestamp: November 21, 2017, 11:20:43 am
content: Usually in 500-600Mb/s is achievable by IO. The datasheet of Cyclone V says it can do upto 875Mb/sSo you'd need 2 parts:- Generating fast clock (serial clock) and the slow clock parallel clock. If 8b10b is used, then usually the slow clock is 1/5th of the fast clock. The fast clock is used to sample data at DDR. Fast clock = 1/2 line rate. Slow clock = 1/10th of line rate.- The second part is to sample at the middle of the data eye. Some FPGA provides input delay block where you can shift individual data lane and check the 8b10b code errors. Or you can shift the clock. But It'll be slower and more troublesome.Seems like cyclone V has serdeses with dedicated hardware that convert serial to parallel. (pg. 166 ofhttps://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5v2.pdf