What's All This TDC Stuff, Anyhow? - Page 1
Forum section: electronics / rf-microwave

author: branadic
author_rank: Super Contributor
timestamp: December 06, 2016, 07:05:36 pm
content: As many people might know Time-to-Digital-Converters are becoming cheaper and cheaper, while resolution increases. This is thanks to continuous improvements in CMOS technology.Inspired by the paper "The ? counter, a frequency counter based on the Linear Regression" I thought a comparision of TDCs might be interesting.https://arxiv.org/pdf/1506.05009v1I have currently two TDCs on the table in my lab, GP22 and TDC7200. Links below:http://www.pmt-fl.com/tdc/tdc-time-to-digital-converters.phphttp://www.ti.com/product/TDC7200Both devices are available for <10€ so it's interesting how they perform compared to each other, right?So here is a first simple comparision with the given example on page 10 in the manuel of TDC7200EVM:Setting the Dual Channel Function Generator (for example: Tektronix’s AFG3102):(a) Set channel 1 of the dual function generator to as follows (see Figure 5):(i) Pulse 1-Cycle(ii) Burst mode(iii) Freq = 40kHz(iv) Delay = 0s(v) Amplitude = 3.3Vpp(vi) Offset = 1.65V(vii) Duty = 20%(b) Set channel 2 of the dual function generator to as follows (see Figure 5):(i) Pulse 1-Cycle(ii) Burst mode(iii) Freq = 40 kHz(iv) Delay = 19us --> this is the time-of-flight (TOF)(v) Amplitude = 3.3 Vpp(vi) Offset = 1.65 V(vii) Duty = 20%Both devices are in Mode 2 and as far as I currently know with the best settings, which means quad resolution on GP22 and with the given settings described in TDC7200EVM manuel.First resultGP22: 4933 samples in 30.2s; mean= 19000.7790687205ns; std=0.0451478954351179ns; max-min=0.336999999999534nsTDC7200: 998 samples in 30.33s; mean=19000.0621584899ns; std=0.233032667622456ns; max-min=0.917114999996556nsPretty interesting results. I guess I need other TDC models to compare with.

author: branadic
author_rank: Super Contributor
timestamp: December 07, 2016, 08:19:19 pm
content: I did another test today, I was interested in what influence the signal form at the inputs of a TDC has. Obvisously a very big. I tested combinations of sinus (S) and rectangle (R). Maybe someone can explain the different results, that where proven to be reproducable? Here are the result of GP22 & TDC7200.ConditionsCH1: 3.3V amplitude, 1.65V offset, 40kHzCH2: 3.3V amplitude, 1.65V offset, 40kHz, Phase 180°Continuous waveTDC7200: Trigger Update Frequence: 100msGP22 was measured to trigger every 6ms, so much faster than TDC7200Maybe someone can explain the differences?

author: branadic
author_rank: Super Contributor
timestamp: December 08, 2016, 09:39:00 am
content: Comparing two sinusoidal waves, the first one 40kHz, the second one 40.0001kHz. What you see is the difference in sampling time between both TDCs.

author: awallin
author_rank: Frequent Contributor
timestamp: December 08, 2016, 04:49:19 pm
content: I guess you saw the arduino-shield with a TI TDC7200http://tapr.org/kits_ticc.htmlhave you looked at FPGA-based TDCs? There is potential for more resolution there. Something that competes with the ~13 ps RMS for time-intervals of the Keygilent 53230A would be interesting...

author: branadic
author_rank: Super Contributor
timestamp: December 09, 2016, 08:01:37 am
content: Yes, I saw that TICC before but as I have TDC7200 and TDC7201 eval boards I don't need a TICC anymore.A TDC7201-ZAX-EVM board goes for 76,22 €:http://de.farnell.com/texas-instruments/tdc7201-zax-evm/eval-board-zeit-digital-wandler/dp/2664492and the necessary MSP-EXP430F5529LP Launchpad for another 12,77 €:http://de.farnell.com/texas-instruments/msp-exp430f5529lp/evaluationskit-usb-launchpad/dp/2357895So this is 88,99€ for the hardware, half the price of a TICC. Sad to calculate this way, but they are to late as TDC7201 is available now.FPGA based TDC's are not of my interest, but there are chips available with <10ps resolution. I guess I will have some more TDC eval boards soon at hand and a 53230A at the beginning of next year in lab.

author: doktor pyta
author_rank: Frequent Contributor
timestamp: December 09, 2016, 12:30:17 pm
content: Typical TDC need well defined start and stop signals (sharp edges). We used ultrafast comparators to do this. Constant Fraction Discriminator is often used to minimize "time walk".

author: Theboel
author_rank: Frequent Contributor
timestamp: December 09, 2016, 02:44:15 pm
content: Hi Branadic,Do You know how to made the combo of TDC7201-ZAX-EVM with MSP-EXP430F5529LP can work with Timelab software ?

author: branadic
author_rank: Super Contributor
timestamp: December 09, 2016, 06:52:59 pm
content: To be honest, I have no idea, but I'm sure there is an offline way to import data to Timelab software.Ordered MAX35101 EVM board today, another interesting candidate to play with and to compare to.

author: branadic
author_rank: Super Contributor
timestamp: December 11, 2016, 03:05:10 pm
content: Yes they are and I will order both EVM boards too. You can't trust datasheets and to get the downsides of each chip you better run own tests.As you can see on the photo and extract from the datasheet there is just the sma connector and a series resistor in front of the TDC7200.http://www.ti.com/tool/tdc7200evmFurthermore the EVM board uses a Abracon Corportation ASFLMB-8.000MHZ-LY-T oscillator with 8MHz.I used Tektronix AFG3022B and performed one test after the other. The rise time of a square wave on this unit is specced to be <18ns. I could have used AFG3102 with <5ns but as both tests are equal for each TDC this makes no real different. So yes, you could use ultra fast comparators or low jitter pulse sharpening buffers to improve performance.I could also have used a GPSDO as a clock source, which I do have at hand, but then I would have needed a /2-divider as GP22 needs a clock between min. 4 ... typ. 6 ... max 8MHz.What do you mean by discrete TDC? Using discrete logic gates?Well, I haven't planed something like this as high resolution TDCs are available and I'm pretty sure you won't reach their performance in a discrete setup, won't you?And while this TDCs are cheap too it makes no sense for me to use FPGAs unless you have special requirements. Maybe some cheaper CPLDs are interesting, but that's not my business.

author: Theboel
author_rank: Frequent Contributor
timestamp: December 13, 2016, 05:23:43 am
content: Hi Branadic and AllI try to understand what TIC/TDC specification mean the most I like to understand is ps Time interval mean.what I like to understand what the important this ps.for example : I want to compare 2 signal with 10Mhz freq with first signal expected stability 10e-9 and the second signal 10e-12 if I use TIC with 50ns or 250ns or 600ns what I will get ?

author: awallin
author_rank: Frequent Contributor
timestamp: December 13, 2016, 05:53:16 pm
content: Quote from: Theboel on December 13, 2016, 05:23:43 amFWIW, 53230A noise-floor plots for 1PPS measurements in time-interval mode:http://www.anderswallin.net/2015/04/keysight-53230a-noise-floor-test/in time interval mode the ADEV will be roughly sqrt(3)*(RMS-single-shot-noise), and I got ADEV(1s)=1.8e-11 for a 1PPS measurementand for frequency measurements with 1s gate time in either defaut (CONT) or reciprocal pi-counting (RCON) mode:http://www.anderswallin.net/2015/06/cont-vs-rcon-mode-on-the-53230a-frequency-counter/for the RCON mode I got around 3e-11 at 1s. The default CONT mode does some averaging or reduction of bandwidth which isn't very well documented AFAIK.The counter noise itself is white phase-noise, and averages down as 1/tau. So let's say you want the counter noise to be 1/10th of your real signal (i.e. frequency difference of two oscillators). That means a 1e-9 difference between two oscillators is measurable immediately, at 100ms or less gate time. But to see a 1e-12 difference you need to average (or increase the gate time) to around 100s.This assumes your frequency sources are stable during that 100s also...

author: awallin
author_rank: Frequent Contributor
timestamp: December 21, 2016, 10:01:39 am
content: Quote from: awallin on December 08, 2016, 04:49:19 pmhere's a talk about the TICC:

author: Bruce G
author_rank: Contributor
timestamp: February 23, 2017, 05:07:00 am
content: Measuring the period of a function generator output to evaluate the performance of sub 100ps TDCs is essentially pointless (as all one ends up doing is characterising the function output signal period generator jitter) unless one simultaneously measures the same period with another TDC with 10x lower noise and INL etc. One needs to use a signal known to have lower noise than the TDC being evaluated. Synchronous dividers clocked by a low noise OCXO (for longer term stability) usually suffice for TDCs with a resolution of a few tens of picosec. For TDC's with sub 10ps noise cascading a pair of LTC's low jitter programmable divider evaluation boards can be useful.The statistical fill the buckets technique using a noisy oscillator can be useful in evaluating the INL and DNL of a TDC.A Trombone style variable delay line can be useful in evaluating the TDC performance when measuring time intervals of a few ns.Whilst interesting the TDC-GPX2 datasheet is somewhat light on performance detail when measuring time intervals beyond 100ns or so. Ultimately for longer time intervals the TDEV of the reference clock will determine the performance. With a 1MHz reference clock the TDC jitter may increase by a factor of 3, the datasheet omits anything about the performance variation with different reference clock frequencies.Discrete TDCs with sub picosecond jitter do exist.However the measurement rate is low due to the number of calculations required. These TDC's use an RF ADC to sample the output of a SAW filter excited by a narrow pulse.Keysight/Agilent used to sell a discrete TDC with 5ps resolution and noise. It should be possible to do a little better than this.

author: awallin
author_rank: Frequent Contributor
timestamp: February 23, 2017, 09:47:41 am
content: Quote from: Bruce G on February 23, 2017, 05:07:00 amI noticed this work by CERN on the ADC + correlation approach was posted quite (?) recentlyhttp://www.ohwr.org/projects/r19-tdc-del-a/wiki

author: Bruce G
author_rank: Contributor
timestamp: February 23, 2017, 10:42:19 pm
content: The original technique from which this was derived is outlined in:https://cddis.nasa.gov/lw16/docs/papers/las_4_Prochazka_p.pdfand many similar papers on the same theme.One problem with this technique is that one can't quickly damp the signal when sufficient samples have been obtained. Other variants using helical resonators or other bandpass filters suffer from the same issue. However they do circumvent some "interesting" issues that arise when a SAW bandpass filter is employed.The other major problem is the time that it takes to compute each timestamp from the ADC samples.An Italian group proposed the damped sine technique some years ago but their implementation was inept. Far too many switches were employed. Done correctly only a single switch with an appropriate on resistance is required. This minimises the parasitic effects seen by the Italian group.A few years ago I built a simplified version using only passive components powered direct from the signal being measured just to see if the technique actually worked as stated. The tuned circuit was connected directly to my 14bit scope input. Unfortunately the high baseline noise, probably due to the less than ideal setup, limited the standard deviation of the measurement of the period of the test square wave signal to about 10ps or so. Some of this can be attributed to the divider chain used to produce the test signal, principally the comparator used as a sine to square converter.I achieved a much higher tank Q (~250) by using T50-7 inductor core and a silver mica tank capacitor. The switch parasitics were also quite low. An air cored inductor with a Q~400 is possible but together with the shielding required to prevent crosstalk would have been quite bulky.A dc coupled tank driver is required for general use.The discontinued Keysight/Agilent Aqiris TC842 used a damped sine TDC interpolator.One advantage of such TDC's is that they are largely self calibrating apart from the delay from the signal transition to the begining of the damped sine.