A bit stumped by this open collector circuit - Page 1
Forum section: electronics / projects

author: nali
author_rank: Frequent Contributor
timestamp: February 10, 2016, 10:12:09 am
content: This is a design I've inherited, and I'm struggling to understand the complexity of this little bit of circuit.It's an open-collector output interface, the output is designed to pulse on for about 1 second when an event occurs so there's not exactly a speed issue here! The input to this is the IO pin of a PIC 16F device, the output isn't specified but usually would go to a GPIO input of a controller of some description.I really can't see the purpose of Q2/D4/C29 etc. Could someone a bit more enlightened than I offer me a clue?Thanks,N.

author: Ian.M
author_rank: Super Contributor
timestamp: February 10, 2016, 10:20:18 am
content: Its a failsafe circuit. If the input is disconnected or steady high, C29 charges up and the extra transistor forces Q1 off. As long as the input pulses low often enough, C29 is kept discharged (via D4) below Q2's minimum Vbe, Q2 stays off and Q1 comtrols the losd normally.

author: nali
author_rank: Frequent Contributor
timestamp: February 10, 2016, 12:56:25 pm
content: Thanks Ian. But...Forgive me for being a bit obtuse, but if the input is latched high (3v) then where is C29's charge path? Q1 collector should be ~0.5V (depending on the load) so C29 will only see 100mV after R10/R14.Or am I getting it completely wrong?

author: Ian.M
author_rank: Super Contributor
timestamp: February 10, 2016, 01:05:25 pm
content: You are right. As-is, because R10 isn't fed from a supply rail, it only protects against open-circuit inputs and is over-complex for that. It looks like its a broken by design failsafe circuit!

author: jeroen74
author_rank: Frequent Contributor
timestamp: February 10, 2016, 08:27:02 pm
content: I think a relay (or any low ohmic load) is supposed to be connected on the output and some supply voltage. If the output is not energized C9 is charged through R10 through the load.

author: nali
author_rank: Frequent Contributor
timestamp: February 10, 2016, 09:05:29 pm
content: Quote from: jeroen74 on February 10, 2016, 08:27:02 pmI can tell you that the intended use is to interface to a GPIO or optocoupler to provide a trigger input to a host controller. But even so with the output not energised the input will be active low so D4 will prevent the capacitor charging more than D4's forward voltage drop. Even if C9 did manage to get charged it would only be driving Q2 which would clamp the base of Q1 - which is already off.As Ian mentioned Q2 would help force Q1 off if the input was open-circuit - which may be the case when the PIC is in reset, blank or faulty - but none of those are really legitimate.What I was really after was a sanity check, after staring at this bit of circuit but not really seeing the point of it. Especially as my analogue skills are pretty rusty after some 20+ years and I was doubting my own abilities to analyse a circuit

author: bobcat
author_rank: Regular Contributor
timestamp: February 11, 2016, 01:36:56 pm
content: That is for the 1-shot timing.When the input is high, D4 is reverse biased, allowing C29 to be charged through R10. When the voltage on C29 gets high enough through the R-C time constant, it forward biases Q2, turning off Q1.When the input is low, D4 is forward biased, and discharges C29, preparing for the next cycle.

author: Ian.M
author_rank: Super Contributor
timestamp: February 11, 2016, 01:57:09 pm
content: No. that idea has already been rejected, as when the input goes high, Q1 collector goes low, and assuming it saturates, Vce will be less than the minimum Vbe for Q2.It could however be half-assed overload protection for Q1. Assuming 5V logic level at the input: R9 limits Q1 Ib to 3.6mA, which limits the collector current to under Ic_max due to the HFE. If Q1 Vce remains above about 3.5V, C29 charges up and Q2 starts to turn on, diverting base current from Q1, increasing its collector voltage and diverting more base current until Q1 is off and Q2 is full on. Half-assed because it relies on the max HFE of Q1 being low enough to keep the dissipation of Q1 within the abs.max limits and I don't thing the datasheet characterises it well enough to guarantee that at elevated temperatures.

author: mikerj
author_rank: Super Contributor
timestamp: February 11, 2016, 03:21:46 pm
content: Quote from: Ian.M on February 11, 2016, 01:57:09 pmI'm pretty sure it's a protection circuit. Using Vce to sense current means the threshold won't be well defined, but it's probably only designed to protect from serious over-current conditions (e.g. Q1 collector shorted to the supply rail).