How to calculate resistor to discharge gate nanocoulombs with P-chan MOSFET - Page 1
Forum section: electronics / projects

author: SuzyC
author_rank: Frequent Contributor
timestamp: September 21, 2018, 04:02:43 pm
content: If I have a 19V supply on the source of a power P-chan power MOSFET and a resistor from source to gate, and from the datasheet I see that the gate charge is about150 nCwhen the gate is switched to ground,what value of resistorwould pull up the gate to 95% of VDD (19V) in 1-uSec when the NPN transistor switch(<50nSec turn-off time) allows the gate to be pulled-up to VDD by the Source-Gateresistordischarging the gate charge?It is a simple question for a MSEE, no doubt, but can someone tell me the equations to do the math?Now, if I was just working with voltage, current and capacitance, I know the formulas for T=RC time constant calculations, but in this case I am working with coulombs and this is where I am having trouble doing the math.The datasheet is attached below for the MOSFET I am working with in designing a step-down switching converter. The idea here is that the MOSFET must turn off quickly enough to have low power loss, but not so quickly as to have too much current flowing through the G-S resistor while the device is turned on and thus also waste power.The datasheet shows, that With V (gate to source)=0 CiSS=3500pF measured at 1 MHz, but I'm talking about the gate charge at -19V when the MOSFET is turned on, then off.The charge/discharge curve of any MOSFET is not linear and there is an interval of voltages for Vg-s approx 2.0 to 2.5V, where the MOSFET on/off threshold is, where gate charge remains almost constant, then increases somewhat linearly again as the gate gets to higher G-S voltages.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 21, 2018, 06:13:40 pm
content: You can completely ignore Ciss for switching purposes -- it does not include the excess charge due to Miller effect.Instead, use the average capacitance. This is Cavg = Qq(tot) / Vgs(on).This will be close enough, like within 30%. To get more accurate, you'll have to account for how much time is spent discharging the gate at different times, but it will also depend on drain voltage and transistor variation at the same level, so it's not very useful or interesting to get more accurate.Tim

author: CJay
author_rank: Super Contributor
timestamp: September 21, 2018, 06:21:24 pm
content: Coulombs are a unit of charge storage and as you know the voltages, it's not that difficult to convert into more useful units (Farads) which plug into the various equations you've already got to derive a mathematically correct answer.But!If this isn't a homework question then it's not critical to calculate it to the nth decimal place and I am confident T3sl4coil's answer will get you where you need to be.

author: MiDi
author_rank: Frequent Contributor
timestamp: September 22, 2018, 12:17:04 am
content: Quick thought (it's late here):The charge does not change for one switching, no matter how fast it switches.But it matters for energy loss calculations for switching frequency, the higher the more losses.You have to get a balance of losses for driving the MOSFET, the losses for switching speed and Rdson losses when on.Driving is affected by switching frequency, the Switching speed will affect EMI, Rdson is affected by the current.As you can see, this turns out not to be a simple question for a MSEE

author: rfeecs
author_rank: Frequent Contributor
timestamp: September 22, 2018, 03:12:50 am
content: An MSEE would throw it into the simulator have the answer.Or if all else fails, Google it:"Power MOSFET Basics: Understanding Gate Charge and Using it to Assess Switching Performance":https://www.vishay.com/docs/73217/an608a.pdf"MOSFET Gate-Charge Origin and its Applications"http://www.onsemi.com/pub/Collateral/AND9083-D.PDF

author: SuzyC
author_rank: Frequent Contributor
timestamp: September 22, 2018, 03:23:44 am
content: No, I am not matriculating, just calculating using the capacity of my knowledge I've accumulated over the years to be in charge to design my own circuits.Thanks Tim, for the EE's perspective. Your answer is not explained, and the idea of using the average G-S capacitance value in calculations is somewhat still somewhat unclear and counter-intuitive to me, but thanks for this certainly helpful advice.My idea of using a P-Chan MOSFET means a single transistor can pull down the gate to Vss and all that is needed to achieve fast turn on, but since the pass switching element is driving a series inductor, and current rises from 0 at turn on, fast turn on is not important for efficiency. A fast turn off is needed for efficiencywhen the sawtooth inductor current is at a peak value at the end of a PWM switching cycle.Of course, I could always use my scope and cut and try different resistor values to achieve a well-working circuit, but I wanted to know how an EE would approach this design problem.I also realize from looking at datasheets for newer simple buck converter chips I sse that the power switching element seems to be always a N-Chan MOSFET(rather than an NPN BJT). I also see now that driving the gate of any sex of MOSFET involves more complicated active circuitry, and no doubt this approach yields higher efficiency than just using a resistor from gate to source and using a P-Chan device. I also see that a N-Chan device requires a bootstrap capacitor, at least one diode and a transistor or two to develop the bias voltage and drive the N-Chan gate.But I also see that in older buck designs, likely less efficient, that common circuits just use a base-emitter resistor with a PNP power transistor switching element to achieve a fast enough turnoff. So, I thought that I could try using a low RdsOn P-Chan device and fewer components to create an efficient buck converter.

author: SuzyC
author_rank: Frequent Contributor
timestamp: September 22, 2018, 03:31:01 am
content: Thanks rfeecs for those links. As often said, getting the right answer is mostly knowing how and where to ask the right question.However, Googling doesn't have the advantage of being able to learning about something from others in this excellent environment.

author: MiDi
author_rank: Frequent Contributor
timestamp: September 22, 2018, 07:10:46 am
content: In addition to my answer regarding power losses, there are alot useful docs and videosout there.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 22, 2018, 07:21:32 am
content: Quote from: SuzyC on September 22, 2018, 03:23:44 amWell, it's a nonlinear system, so a straightforward answer isn't possible (as for the linear capacitor case). You'd have to integrate it to find the average. Doing that symbolically would suck (if it's possible at all). You can have SPICE integrate it for you, which will show the waveform, and you can calculate the total charge that way. The gate charge curve given in the datasheet is a cartoon of this -- smoothed out, and usually drawn as three line segments with sharp corners, but actually the corners are soft and the middle segment isn't perfectly horizontal but tilted slightly.In any case, more time is spent around Vgs(th), where Vds is changing, and that skews everything. Moreover, Ciss and Crss depend on Vds, which is why the slopes above and below the flat region are different. That's why we use Qg(tot) instead of Ciss or such.QuoteAh. So it sounds like you need to flip your entire approach!You will probably find, at least using a resistor, it takes an extremely small value (< 100 ohms?) to get even passable rise time into the gate. You can start by boosting this resistor with an emitter follower: the equivalent resistance at the emitter is R / hFE, but the voltage at the emitter can be controlled by the voltage at the base with only R loading it.Typically a complementary emitter follower is used, to boost the pull-down current in the same way, so the driver transistor only needs to deliver, say, twice the current drawn by the pullup, not a massive gulp of current.That looks like this:https://www.seventransistorlabs.com/tmoranwms/Circuits_2010/Regen_Motor.pngThe problem shifts from a matter of providing current, to a matter of shifting a logic level from near ground, to near the supply voltage. This is especially important when the supply voltage is much higher than the logic level, and when the supply voltage is variable. Say you have a 12V logic level (from some analog or CD4000 CMOS circuits), and a 24-48V supply: you need to apply [12 to 24] to [36 to 48] volts on the high side gate (for Vgs(on) = -12V, Vgs(off) = 0V).A good way to handle that, is communicating the logic state with a constant current. The current doesn't depend on the supply voltage, so you can convert that current back into a logic voltage (referenced to Vsupply) with a resistor.A single transistor CCS still has one catch: output capacitance. Suppose Vsupply changes suddenly: the change in voltage induces a current through the capacitance, I = C * dV/dt. Basically, this approach has zero PSRR at high frequencies. At the very least, you need to ensure a wide logic voltage range and a small supply noise voltage, so that the one doesn't upset the other.Matters can be further improved by using differential drive. A constant current is "steered" back or forth between two lines, rather than one; both CCSs have the same capacitance, but when the currents are combined at the high side, using a current mirror, the capacitive currents cancel out, leaving only the desired signal current. That looks like this:https://www.seventransistorlabs.com/Images/CMBuck_Output.pngQ301-2 are a diff pair that steer the current from R308 into the two lines (here, cascoded with Q305-6 for better performance, because this high-side Nch driver is subject to the whole switching transient). The lines are received by Q311 (saturated switch, pulling up) and Q312 (current mirror) then Q314 (saturated switch, pulling down). Q314 follower boosts output to drive the gate.Hmm, that's a little backwards, Q312 should be driving Q311 base to cancel out the currents. Ah well, it still did okay (I actually built this one, years ago, and I don't remember problems from the driver itself).At this point, you would more than gladly use a bootstrap gate driver IC.QuoteSeems like I've seen NPN based buck switchers by LT more often than anyone else. They are out there, it's just a bit annoying because Vbe(on) is small and Ib requires current to maintain saturation. Normally, the bootstrap cap is supplied from the main supply, which might be 5 to 12V, or more; Vbe(on) ~= 1V, so the 4-11V is wasted and has to be dropped with an internal resistor or current source. Ib also means a larger capacitor is required for a given maximum on-time. So, it's partly an impedance matching problem (lower voltage, higher current), and partly a power problem (having to supply -- and waste -- more drive power).But it follows that such devices are quite reasonable at low voltages, say a converter with a 3V input or output (drawing the controller's supply from its output saves efficiency once it's running, but doesn't always work out).A lot of applications just use higher voltages (5-12V) where it's not so economical, so MOSFETs are used.Another discrete comparison you might find interesting:Discrete boost supply (4 BJTs plus error amp),https://www.seventransistorlabs.com/Images/Deadbug_Sch.pngDiscrete flyback supply (8 BJTs, MOSFET, error amp),https://www.seventransistorlabs.com/Images/Discrete_Tube_Supply.pngNote that the latter could use a BJT in much the same way as the former does (R + RC network to supply base drive), probably eliminating the complementary emitter follower (thus using a total of... seven transistors, if you will?). Not much change is required in this case -- but the efficiency will suffer, unless the supply voltage is reasonably low.QuoteIt's not really many more components -- transistors are free if you're building a chip -- while the benefit is dramatic, NMOS having ~2.5x better performance than PMOS.PNP vs NPN is a pretty small difference, with PNPs being a little slower and lossier (like 20%, I forget what exactly). Back in the days when transistors actually cost something, they took advantage of using the switch as its own level shifter (i.e., supply base current and you're done, no further level shifting to worry about), not minding the low switching speed. The advantage back then was saving heat in higher power applications: a linear supply might be below 50% efficient, dissipating over 10W in a microcomputer, say, versus 70% in a switcher. Hardly efficient by modern standards, but a necessity to save costs and space on heatsinks inside a cheap, tacky plastic enclosure!Tim

author: SuzyC
author_rank: Frequent Contributor
timestamp: September 22, 2018, 02:17:19 pm
content: Thanks T3sl4co1l for clarifying your previous comments with your enormous reply!It has taken me some good deal of time to try to digest all you've written here, but I seem to get the idea of you admire circuits of shameless complexity while I like the idea to create a circuit having the qualities of best performance(incl. efficiency, reliability and robustness) are combined to achieve the least complexity, footprint and cost.To me, the idea of circuit design is like composing a good poem, so the fewest of parts rhyme(work) together to produce an amazing result.At the same time, I easily realize how the circuits you've linked might have a great advantage by being constructed from easily found parts which might lead to lowest cost( achieved by using discrete parts), but all these circuits seem to be a challenge to minimize into a small PCB footprint and might present a quagmire to troubleshoot or repair(as if that idea was even in style).For instance, regarding the last circuit you've linked to, that for a flyback converter, could so easily be simplified by using something like a ULN353x chip to replace all of the parts to the left of '3055 MOSFET.With the help of all of the posts here, I've come to the conclusion that my initial question seemed to be best answered by using circuit simulation tools and/or trail and error part selection and discovered my idea of using a single resistor is to discharge the gate is too simplistic to be efficient, thus impractical.I've learned from you that a better drive circuit is a npn/pnp complementary pair gate driver interfaced to control logic by a common-base npn. This is the efficient gate drive circuit needed to create a simple buck converter using a P-Chan MOSFET using discrete components, while importantly, not using a SMPS chip.