Ethernet MAC in FPGA  - Page 1
Forum section: electronics / projects

author: rakeshm55
author_rank: Regular Contributor
timestamp: November 17, 2019, 11:55:33 am
content: Hi,I am looking for an Ethernet MAC that can be implemented in FPGA. I tried using AXI ethernet Lite IP core from Xilinx.My requirement was to communicate between a processor and FPGA via ethernet interface . FPGA implements Ethernet MAC core and uses an external 10/100 Ethernet PHY (MII interface).We use point to point raw socket communication Ethernet 802.3 MAC packets for data exchange. Destination/Source will have fixed MAC ID (will not change board to board).With the above background I started with AXI Ethernet lite core from Xilinx. I was able to communicate with PC. Here the issue is data read speed. I use a 100MHz clock.The IP core has an AXI lite interface with 32 bit data width. It also has a Rx ping pong buffer. My data access speed is limited to about 12 clock cycles to acquire a 32 bit data from RX buffer.Now if I try sending a 1500byte Eth packet. It takes about 45us to acquire data from the Rx buffer. This implies that if there is a continuous data traffic like 1500bytes followed by 60bytes followed by 60bytes . I am bound to miss the 3rd packet as I will not be able to clear the Rx buffer.I am still unable to resolve this issue. I guess that user should read 1500bytes within 6us once Rx buffer has valid data or he will miss the next packet unless sufficient delay is provided between packetsIs there any working /proven free Ethernet MAC core with MII interface available?? Has any one used it?? Please advice

author: FenTiger
author_rank: Regular Contributor
timestamp: November 17, 2019, 12:06:27 pm
content: It's not at all unusual for devices to contain Ethernet interfaces that won't run at the full line rate. Usually this is handled by using a higher level protocol such as TCP that can use flow control to adapt to the actual bandwidth available.What throughput do you actually need for your project? If you really need to run at line rate then your whole Ethernet subsystem, not just the MAC, will have to be designed to run at this rate. (This gets interesting at 100Gbps as I'm sure you can imagine... luckily few people need this kind of speed.)Would more buffering help? Perhaps you can add some logic to read the incoming packets as quickly as possible into a larger buffer which the CPU can access at its leisure. This might not help with your throughput, but could allow you to absorb a larger burst of packets without dropping any.

author: rakeshm55
author_rank: Regular Contributor
timestamp: November 17, 2019, 01:29:27 pm
content: I am using low level programming (vhdl) to access data from IP.... Rx buffer in MAC ip is DPRAM kind of implementation... I am issuing axi lite bus signalling to access this port... It does not support burst access.... So in order to access 32 bit bus data I have to issue these many cycles... Packet loss is happening at MAC level.... As long as this bus access remains I may not be able to achieve throughput speed unless I increase clock freq... So I look forward to a different ip with faster data port....

author: Daixiwen
author_rank: Frequent Contributor
timestamp: November 18, 2019, 08:50:21 am
content: I don't really know Xilinx' IP modules but nevertheless 12 clock cycles to read a data word is a lot, even if bursting is disabled. Are you sure this is correct?The Opencores Ethernet MAC works quite well and has been tried and proven on several architectures:https://opencores.org/projects/ethmacIt uses a Wishbone interface, which is quite easy to use

author: OwO
author_rank: Super Contributor
timestamp: November 18, 2019, 11:00:49 am
content: Quote from: rakeshm55 on November 17, 2019, 01:29:27 pmYou can do pipelined accesses even without burst support; just issue more requests before a response arrives (that's the point of AXI). 12 cycles latency is a bit on the high side but still reasonable because it probably has to cross many clock domains. You don't need low latency to achieve high throughput.