hybridfree/eevblog-posts huggingface dataset:
Seeking Book and Library Recommendations for FPGA Networking Projects - Page 1
Forum section: electronics / general

author: fpganoob
author_rank: Newbie
timestamp: February 19, 2024, 04:48:49 pm
content: I hope this message finds you well. As I venture into the exciting realm of FPGA-based networking projects, I'm seeking recommendations for learning resources and libraries to enhance my knowledge and practical skills.Firstly, I am considering the book "Computer Networking: A Top-Down Approach" by Kurose to build a solid theoretical foundation. If any of you have experience with this book or can suggest alternative resources, I would greatly appreciate your insights.Additionally, I've come across the "verilog-ethernet" library by Alex Forencich on GitHub (https://github.com/alexforencich/verilog-ethernet). While it seems to cover the Ethernet stack, I would like to know if it is sufficient for my goals. I am particularly interested in High-Frequency Trading (HFT) applications and want to ensure that I have the necessary networking capabilities.Questions:Does the "verilog-ethernet" library cover only the link layer of the OSI model, or does it include higher layers such as TCP/UDP?If it's limited to the link layer, would it be advisable to implement the entire TCP/UDP stack on top of the Ethernet stack for comprehensive networking capabilities?Moreover, if you have alternative library recommendations or other networking resources that you found beneficial for FPGA networking projects, please share them.Thank you all in advance for your expertise and guidance. I look forward to learning from your experiences.

author: Forty-Bot
author_rank: Contributor
timestamp: March 06, 2024, 06:14:59 am
content: QuoteQuotemaybe you should read the readme

author: Brociall
author_rank: Newbie
timestamp: February 07, 2025, 04:15:21 pm
content: Do you consider short essays or videos for learning? Sometimes books can be too complicated or contain a lot of unnecessary information. I often usehttps://ca.edubirdie.com/when describing something in more detail or structuring the material. If you want to network with FPGAs, look at practical examples and open-source libraries, such as P4 for programmable networks or HDL descriptions of Ethernet controllers. You should also consider Coursera courses or YouTube lectures. This will help you to understand the topic faster without the need to read big books.
Latest version of Anlogic IDE? - Page 1
Forum section: electronics / general

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 29, 2022, 02:05:41 pm
content: I have been looking into if there is a new version of the Anlogic IDE (Tang Dynasty) for working with their FPGA's and it seems there is a new one.QuoteBut to get it from their websitehttps://www.anlogic.com/support/tools-downloadsyou have to have a login, and the problem is I don't understand Chinese. No idea what to fill in where and on the with google translated site the download does not show up.It is not available on the Sipeed site where the older versions can be found. But they do have a license file for up to half way next year.https://dl.sipeed.com/shareURL/TANG/Primer/IDEhttps://dl.sipeed.com/shareURL/TANG/Premier/IDESo my question is if anyone has this version and can put it up for download somewhere?

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 29, 2022, 09:32:03 pm
content: It shows fine with the integrated translator in Chrome.The only problem is you need a chinese phone to receive the code, the typical online disposable numbers seems to be down or blocked.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 30, 2022, 05:23:17 am
content: I'm using firefox and with a later try I did see the sign in screen but not completely correct like yoursAnd the need for a Chinese mobile makes it a mission impossible for me.

author: mopplayer
author_rank: Contributor
timestamp: December 06, 2022, 03:11:35 am
content: Quote from: pcprogrammer on October 30, 2022, 05:23:17 amYou do not need the new version, the stable version is 5.0, my Anlogic partner says there are bugs in that new version.

author: pcprogrammer
author_rank: Super Contributor
timestamp: December 06, 2022, 06:19:39 am
content: Hi mopplayer,thanks for the update. I did manage to figure out that the version I have is sufficient.

author: pcprogrammer
author_rank: Super Contributor
timestamp: December 19, 2024, 01:04:14 pm
content: I know this is an old thread, and probably not of interest for many, but I needed a new license for the software, and it has not been renewed on the Sipeed site. Instead it is available on the Anlogic site in the download section for the software. But you do need a login for it.https://www.anlogic.com/en/support/tools-downloads

author: pcprogrammer
author_rank: Super Contributor
timestamp: February 12, 2025, 07:47:41 pm
content: Here is a license for the Anlogic IDE that is valid until January 2026.
Kintex Transceiver Init - Page 1
Forum section: electronics / general

author: jjoonathan
author_rank: Frequent Contributor
timestamp: January 13, 2025, 04:45:30 am
content: Hi! I'm working on a broken oscilloscope implemented as a Kintex XC7K325T connected over PCIe to an Intel PC. The FPGA used to show up on the PCIe bus and then one day it stopped, shortly (but not immediately) after I disassembled and reassembled the scope to grab EEPROM. Here's what I know:Power buses are ok - there are many, this was a pain tovalidatebut so it goes.Bitstream loads. INIT_B, DONE, and PROG_B are all high (yellow, green, yellow LEDs).Checksum passes. (rto2044-jtag.txt)Early SPI bus tasks are completed by FPGA (3x ADF4360 VCO/PLLs program and lock - green, green, green LEDs)SYS_PWROK and PLTRST# go high (inputs from system to FPGA)PCIe REFCLK appears (input to FPGA) but heavily distorted. I actually have a before/after on this one. Distortion is consistent with an open circuit at FPGA, not a short, not a decoupling capacitor or connector issue.REFCLK (capacitively coupled) has a common mode voltage of 8mV (measured) instead of 800mV (expected) at FPGA.There are two things I would appreciate advice on from people wiser in the ways of FPGAs (my own experience is very elementary):From REFCLK_diagram.png and IBUFDS_GTE2.png it sure looks like the termination settings come from the bitstream rather than an enable line from the fabric. Since I know that MGTAVCC is up and the bitstream is loaded, I would expect this to enable termination, but it doesn't. Vcm is 8mV, not 800mV. I am likely missing something, but I don't know what. Any ideas?I don't see any debug interfaces for the Multi Gigabit Transceivers in the Vivado JTAG tool. Evidently they weren't baked into the design. Is there any other way to get a status out of the MGTs or PCIe IP?I'm about ready to throw in the towel on this -- I can order a replacement, it just means admitting defeat, but I'm still down for pulling on another thread or two if someone can point me in a possible direction. Thanks in advance!

author: jjoonathan
author_rank: Frequent Contributor
timestamp: February 12, 2025, 03:19:15 pm
content: Problem solved: the Kintex was fried, replacing it restored functionality. It does indeed put common mode voltage on REFCLK about 3ms before DONE is asserted. I'm still not entirely sure what happened. ESD made it marginal and normal operation tipped it over? In any case, here are some diagnostics to check if you are in a similar situation:* Broken Kintex: both MGTREFCLK pads are open circuit* Working Kintex: both MGTREFCLK pads are 1.24V under 1mA diode check
Finite State Machine Programmable Logic Controller - Page 1
Forum section: electronics / general

author: monsonite
author_rank: Newbie
timestamp: February 05, 2025, 08:59:16 am
content: Dave,Many moons ago (2000) you produced a design for a Finite State Machine Programmable Logic Controller.You mentioned that there was a compiler for it PLC10.exe. I wondered if any of that work is still accessible online?Thanks in advanceKen

author: zapta
author_rank: Super Contributor
timestamp: February 07, 2025, 04:23:54 am
content: Just in case it interests you. Open source PLC.https://autonomylogic.com/docs/openplc-overview/

author: __greg__
author_rank: Newbie
timestamp: February 07, 2025, 11:20:01 am
content: http://electronics-diy.com/electronic_schematic.php?id=702Files:http://electronics-diy.com/schematics/702/plc10.zip
Help converting JED to VHDL or ABEL - Page 1
Forum section: electronics / general

author: pablofg
author_rank: Newbie
timestamp: January 18, 2025, 04:24:55 pm
content: I recently read some old xc9536 chips that I wanted to modify. I could do this using ISE and Impact via JTAG. I read the xc9536 in jed format and burnt it to different new xc9536 to check that the dump was good.Now I'd like to modify the contents and add one or two things. Appartenly Xilinx or DATA I/O Abel is able to do that. I have been trying to find the software but it's nowhere to be downloaded. I found some version on archive.org inside some maganize CD that has an evalutaion version. Unfortunately this evaluation version does not support the xc9000 family and goes up to xc7000 only. Apparently the file that I need is called jed2abel.exe which seems to be there and work well, but it complains that it needs the .dev file for this family and I can't find it anywhere. I only need to convert 2 jed files to something that can be edited / understood and then I'll "compile" again using Impact / ISE 10.1, but I need those equations first. Can someone help me to find that library or could someone convert those files for me? Apparently only version 6 o ABEL supports that family.Thanks in advance!

author: pablofg
author_rank: Newbie
timestamp: January 18, 2025, 09:29:16 pm
content: Small correction. The program seems to be JED2AHDL.EXE, someone has it or can do the conversion for me? V6 seems to be the right one.

author: AK6DN
author_rank: Regular Contributor
timestamp: January 19, 2025, 12:13:47 am
content: Quote from: pablofg on January 18, 2025, 09:29:16 pmAppears to be a .zip file here:http://ebook.pldworld.com/_semiconductors/Atmel/Databook%20CDROM/Atmel/prod180.htmsearch the page for 'jed2ahdl'

author: pablofg
author_rank: Newbie
timestamp: January 19, 2025, 11:26:19 am
content: Hello @ak6dnthanks for response.I downloaded but this is what I get. What am I doing wrong? I guess that I need the right libraries for that device. Or should I type something different like xc9500 ?I guess I need the .dev files, right?

author: AK6DN
author_rank: Regular Contributor
timestamp: January 19, 2025, 05:54:58 pm
content: Quote from: pablofg on January 19, 2025, 11:26:19 amYou need a valid DataIO ABEL and/or SYNARIO installation as well that supports the devices you are using. This is just the disassembler program.
Andratech AR-28 EPROM Programmer Manual and Software Needed - Page 1
Forum section: electronics / general

author: scopeman
author_rank: Frequent Contributor
timestamp: February 06, 2025, 11:20:29 pm
content: Hello,I have an old AndraTech AR-28 EPROM programmer (not the EPROM+) that I built in the 1980's and I need the manual and the software for it. I believe that this unitcan program TMS2716's. IIRC they either sold the PCB and parts as a kit with a manual or perhaps it was just the PCB and a manual I don't recall as Ihave slept a lot since then!I did find some MSDOS software for it but it is on 5 1/4" floppies and I no longer have any hardware that can read those floppies.I would appreciate any help on this.Let me know also if you think I should post this request in another forum.Thank you,SamW3OHM

author: scopeman
author_rank: Frequent Contributor
timestamp: February 07, 2025, 12:55:29 am
content: I have the software but the company says they do not have a PDF of the manual. So I am still looking for that. All I need is to know what the dipswitches are for andhow to set them for a particular device.Thanks,Sam

author: GWeezy
author_rank: Newbie
timestamp: February 16, 2025, 06:12:04 pm
content: Hi,Not sure about the model AR-28 but I have one that is called Multi-Type that is the one they sold as a kit in the mid 80’s. I still have it and the manual. I did update it in 1986 (I was using CP/M and did a mod to it to enable programming 27512’s and started using it with MS-DOS. I can’t find AR-28 anywhere on it so it may not be helpful but I do have the manuals for both OS’s.gweezy
A question for HDL developers. Where do you place your source and testbenches? - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: December 07, 2024, 07:52:15 pm
content: A question for HDL developers. Let's say that you have a verilog file named my_module.v and a testbench for it called my_module_tb.v.1. Do you place both files in the same directory or in separate directories?2. If you answered 'seperate directories', is the testbench directory under the source directory or do you use two independent directories trees, one source source files and one for test files?

author: AK6DN
author_rank: Regular Contributor
timestamp: December 07, 2024, 11:39:59 pm
content: I use multiple directories to keep files.Under my PROJECT directory, I typically have SRC and TESTBENCH directories, with project specific source and testbench files in each.I also have LIBRARY SRC and TESTBENCH directories, where the files are shared across multiple projects.

author: pcprogrammer
author_rank: Super Contributor
timestamp: December 08, 2024, 07:18:20 am
content: Just as for software development it does not matter from the computer perspective.For the developer and coworkers (company) it is good to have a fixed structure across work. So using a similar directory structure for all your projects is good sense.A lot of the proprietary IDE's for FPGA development force some directory setup upon you for their IP (intellectual property) stuff, and can write a load of work files to the top directory cluttering the perspective. So having a dedicated source directory within the project directory makes it easier to keep the important stuff separated from the less important stuff.

author: gael
author_rank: Newbie
timestamp: January 17, 2025, 09:19:15 pm
content: In our practice, everything in VHDL/Verilog is sources, under some common root tree, and we put the synth intended ones under <root>/synth and the sim intended ones under <root>/sim.
ChipScope waveform viewer application - Page 1
Forum section: electronics / general

author: priimak
author_rank: Newbie
timestamp: February 12, 2025, 12:52:15 am
content: Hello.I have created open source tool called "Trace Tool" to view, record, annotate and transform/analyze waveforms generated by the ChipScope.Minimal instructions are here:https://github.com/priimak/ttAnd latest tutorial is hereIt is still a work in progress but perhaps some of you might find it useful. Let me know if you have any questions.Please let me know if this post is not appropriate for this forum. If so, I apologize.
FPGA & CPLD Marking & Part Number - Replacement - Page 1
Forum section: electronics / general

author: 2X
author_rank: Frequent Contributor
timestamp: January 16, 2025, 11:02:35 pm
content: Hello,I have the below FPGA and CPLD. The CPLD writes on it some codes as the FPGA as well. Could you tell me if the part numbers where I have found are right? Also, the FPGAs from the AliExpress and ebay are trusted or it depends or absolutely No?CPLD Part Number: XC2C64A-7VQG100CFPGA Part Number: XC4VSX35-11FF668C (can I will use the XC4VSX35-11FF668I(I = Industrial) where it has Temperature Range: (TJ = –40°C to +100°C) or it has and other differences?XC4VSX35-11FF668I- aliexpresshttps://www.aliexpress.com/w/wholesale-XC4VSX35%2525252d11FF668I.html?g=y&SearchText=XC4VSX35-11FF668I&sortType=price_ascXC4VSX35-11FF668C- ebayhttps://www.ebay.com/sch/i.html?_nkw=+XC4VSX35-11FF668C+&_sacat=0&_from=R40&_trksid=p2332490.m570.l1313

author: jocjosoe
author_rank: Newbie
timestamp: January 17, 2025, 07:09:07 am
content: XC4VSX35-11FFG668C & XC2C64A-7VQG100C,This is the correct PCN. Our company often uses WHL to test it. It is relatively safe. The ones on these shopping websites are not reliable. If you need, we can communicate more.

author: 2X
author_rank: Frequent Contributor
timestamp: January 17, 2025, 07:46:58 am
content: G is lead FREE as I read on the datasheet, so if I buy this XC4VSX35-11FF668C without G it will be a problem? I believe the only difference is the soldering temperature profile because this part number without G will have lead on soldering balls.

author: jocjosoe
author_rank: Newbie
timestamp: January 17, 2025, 08:05:31 am
content: It depends on your country's environmental regulations.
Integrating a Custom DCP into a Vivado Project - Page 1
Forum section: electronics / general

author: alimousios98
author_rank: Newbie
timestamp: January 09, 2025, 11:02:50 am
content: I have created a clock glitch generator circuit and I am using RapidWright in order to place it in specific tiles of my device and the end result is a dcp file. My problem is how can I merge this dcp to my existing Vivado project which is a simple aes. Is there a way to create a vivado project using a dcp file or is there another way to create this circuit to my final project directly and somehow choose what resources it will use exactly ( LUT etc).
ECP5: Setting Vref off recomended limits. Any experiences? - Page 1
Forum section: electronics / general

author: bsccara
author_rank: Contributor
timestamp: January 07, 2025, 07:45:31 pm
content: On a design I'm doing with a ECP5U I'm planning to have a bank of IO set as SSTL18 to use as inputs for LVCMOS signals between 1.2V and 3.3V. For that I'll need to set the external Vref up to 1.65V, which is outside the recomended range. According to the datasheet on table 3.1 the maximum voltage on any IO pin is 3.63V, which includes the pins used for routing the Vref into the FPGA, while the recomended Vref range stated on table 3.2 is 0.5V to 1.0V, but with a note that states:QuoteAlso, table 3.12 states that the maximum Vih for SSTL18 is 3.465V. To me it seems that it should be safe to do but I'm not sure if a voltage over 1.0V on Vref or a voltage difference on the inputs over 0.9V will overload the input comparators in the IO pads and degrade their AC response. Has anyone tried this or has any opinion on the matter ?
[SOLVED] EPM240 and boundary scan - Page 1
Forum section: electronics / general

author: Watseup
author_rank: Newbie
timestamp: December 29, 2024, 07:00:36 pm
content: Hello Everybody,I discover the world of CPLD with EPM240 Evalboard and i love thatBut im blocking when i try to use JTAG with Quartus..I want to read the state of IO with quartus and boundary scan but even though I set pin 37 to GND or '1', i have the same result: "000..0040555"(see image)... Do you have an idea to help me please ?In the future, i would like to read the state of I/O of EPM240 with Arduino and JTAG boundary scan. Do you think it's possible ?Thanks for your help,Max

author: Watseup
author_rank: Newbie
timestamp: January 03, 2025, 04:46:21 pm
content: Hello,Little Update:i couldn't do JTAG with Quartus chain Jtag debugger...But with a little FTDI "CJMCU-232R" and python script i'm able to boundary scan$ python finalcommente.pyResult of Boundary Scan: 240:00100100 10010010 01001001 00100100 10010010 01001001 00100100 10010010 01001001 00100100 10010010 01001001 00100100 10010010 01001001 00100100 10010010 01001001 10100100 10010010 01001001 00100100 10010010 01001001 00100100 10010010 01001011 00100100 10010110 01001001.retval: 0x155BYPASS sent: 24: 00001111 01100000 11110110, received: 24: 00011110 11000001 11101100 (should be left shifted by one).IDCODE (reset): 0x20a10ddMax
problem with AXI bus - Page 1
Forum section: electronics / general

author: e0ne199
author_rank: Regular Contributor
timestamp: December 31, 2024, 05:52:15 am
content: Hello everyone, i have a problem with sending data over AXI bus. The data I want to send is an array of int (392 row and 30 column), but when I try to send it with AXI stream, the AXI stream throws an error...do you know what to do in this situation? any response is really appreciated, thx before.

author: Someone
author_rank: Super Contributor
timestamp: December 31, 2024, 06:10:58 am
content: Quote from: e0ne199 on December 31, 2024, 05:52:15 amWhich error?You will need to share many more details to get help/advice.An AXI Stream endpoint/sink provides no status/error/reporting, it is either accepting data or it is not.

author: Siwastaja
author_rank: Super Contributor
timestamp: December 31, 2024, 12:27:32 pm
content: IfCode:if (status != XST_SUCCESS)is failing, then the obvious thing to do is to print the value ofstatusand compare it to the documentation of XAxiDma_SimpleTransfer(), which can be found with 5 seconds of Googling:https://xilinx.github.io/embeddedsw.github.io/axidma/doc/html/api/group___a_x_i_d_m_a.html#ga32ca6099d7926297a4c17cdb4a19511bCode:ReturnsXST_SUCCESS for success of submissionXST_FAILURE for submission failure, maybe caused by: Another simple transfer is still goingXST_INVALID_PARAM if:Length out of valid range [1:8M] Or, address not aligned when DRE is not built in

author: e0ne199
author_rank: Regular Contributor
timestamp: December 31, 2024, 01:45:27 pm
content: Quote from: Siwastaja on December 31, 2024, 12:27:32 pmyes I am aware of the error..my problem is i don't know why i am unable to send arrays larger than 30x10 to the PL side...i am still very new to verilog especially AXI communications, and i am not sure if the AXI faces bottleneck or something like that when i try to send large data using AXI stream..do you have any suggestions about that, for example where to look for this kind of problem? or do i have to do some configuration (or add some IP block) on the PL side?

author: Someone
author_rank: Super Contributor
timestamp: December 31, 2024, 01:55:16 pm
content: Where is the AXI stream in this? The code example supplied is using some high level software to interact with a DMA engine.Quote from: e0ne199 on December 31, 2024, 01:45:27 pmSo you want to send data to the PL, but dont have anything on the PL side? This sounds like you're just throwing stuff at a wall with no plan of how it should function.

author: e0ne199
author_rank: Regular Contributor
timestamp: December 31, 2024, 02:18:07 pm
content: Quote from: Someone on December 31, 2024, 01:55:16 pmI am sorry but do you want to have a look at the PL side too?

author: glenenglish
author_rank: Frequent Contributor
timestamp: January 01, 2025, 01:10:37 am
content: please post the waveform from the simulator output. pre-synthesis is a good start.or , post the chipscope / ILA output
[ANNOUNCEMENT] Apio support for Gowin FPGAs is available for testing. - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: January 10, 2025, 03:46:16 am
content: Apio support for Gowin FPGAs boards such as Sipeed Tang Nano 9K is now available for testing (on mac, linux, and windows).Apio is a non commercial and open source framework that brings platformio's simplicity to verilog and FPGA programming.Apio covers all the aspect of FPGA from formatting, compilation, linting, testing, simulating and programming, all with simple command such as 'apio build', 'apio test', 'apio sim' and 'apio upload'.Installation is easy, just have python 3.10 or newer installed on your computer and then run:Code:pip install --force-reinstall -U git+https://github.com/FPGAwars/apio.git@develop#egg=apioThis will install the apio python package (latest dev version) and will make the command 'apio' available. Type 'apio -h' for help.Then you can fetch for example a Sipeed Tang 9k sample project using the command:Code:apio examples fetch sipeed-tang-nano-9k/blinkyand build it using the command :Code:apio buildor simulate it usingCode:apio simMore details herehttps://github.com/FPGAwars/apio/wiki/Apio-development-environment#just-trying-the-latest-apio-dev-versionA list of all the commands and their help text is available herehttps://github.com/FPGAwars/apio/blob/develop/COMMANDS.mdPlease let me know here if you have any questions.
Anyone using Xilinx XC2k XC3k XC4k FPGAs? - Page 1
Forum section: electronics / general

author: peter-h
author_rank: Super Contributor
timestamp: December 26, 2024, 03:54:06 pm
content: I used to do FPGA design consultancy many years ago, finally getting out of it in 1996. Also did some ASIC design, prototyped on XC3090 FPGAs.I still have the tools, comprising of Viewlogic/LCA v4 and XACT 5. In those days they were dongled but some Russian guy did patches so the tools will run standalone, on a DOS 6.2 machine. They may also run in a VM but VL4 works best with an ATI 8514-emulating video card which may not work in a VM. I also have one of these video cards. That toolset cost about $20k back then but is worthless now.I also have the user manuals scanned to PDFs. I think all my designs are in there too.So if anyone is interested, PM me.This stuff would be handy for opening an old FPGA based product, to do a mod, etc. I know the XC3064 and XC3090 devices were still manufactured 10 years ago, and the 4k devices probably later. I never did any work with the XC2k devices.I did some fun work in those days, e.g. pulse generators for some flight sims, a funky interface card for a Hitachi PLC protocol which used a high power manchester coded physical layer for extremely severe EM environments (64 bit packets) with an RS232 interface on the other end, some crypto stuff... Gave up FPGAs because they tools kept changing, and frankly most of the jobs could now be done with a 168MHz ARM32 CPU. Xilinx did not maintain backward compatibility so old designs could not be imported; the sales guy said "you have to break some eggs to make an omelette" and that was it
Mixing verilog and system verilog? - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: December 17, 2024, 08:40:31 pm
content: A question for experience designers. Is it common or useful to mix verilog and system-verilog files (RTL and testbenches) in the same project?Also, is it common to distinguish between verilog and system verilog files by the extension? E.g. .v and .sv.

author: AK6DN
author_rank: Regular Contributor
timestamp: December 18, 2024, 06:37:20 am
content: Quote from: zapta on December 17, 2024, 08:40:31 pmVery common. Your HDL tool might support Verilog syntax only (or more likely the synthesize-able subset of the Verilog language, as defined by the vendor).Or your vendor tool might support SystemVerilog (or again a synthesize-able subset of it) language input as well.For your testbench, if your simulator supports SystemVerilog, then your testbench might be written in that dialect, and it references your design in Verilog).The vendor synthesis tools will never see the testbench code, so they can be written in whatever dialects of Verilog your simulator supports.Heck you could even write your testbench in VHDL if your simulator supports mixed language input on files.For most tools it is general practice (and may be required, depends on the tool) for Verilog files to be .v extension and SystemVerilog files to be a .sv extension.

author: Berni
author_rank: Super Contributor
timestamp: December 18, 2024, 06:57:02 am
content: You can even mix VHDL, Verilog and SystemVerilog in the same project for most cases.But yeah as usual in the FPGA world, the details are very tool specific. Every vendor does things slightly differently and might support a slightly different list of features as actually being synthesizeable.

author: xvr
author_rank: Frequent Contributor
timestamp: December 18, 2024, 01:30:35 pm
content: BTW, from 2009 Verilog and SystemVerilog are officially the same language. Last Verilog standard IEEE Std 1364-2005 was superseded by IEEE Std 1800-2009 (which is the SystemVerilog standard)

author: AK6DN
author_rank: Regular Contributor
timestamp: December 18, 2024, 10:11:48 pm
content: Quote from: xvr on December 18, 2024, 01:30:35 pmWhich helps now if you are using current FPGA/CPLD design software, but if you are using legacy 90s/00s software as I do there is still Verilog vs SystemVerilog to deal with.

author: asmi
author_rank: Super Contributor
timestamp: December 19, 2024, 03:52:13 pm
content: Nowadays I only use Verilog to create a wrapper for Vivado IPI components because it still doesn't support SystemVerilog (which is a shame really). SystemVerilog is better in every way you can think of, so I see no reason not to use it.
XC9500XL : using "Timing driven" macrocells power setting - Page 1
Forum section: electronics / general

author: Sassa
author_rank: Newbie
timestamp: September 25, 2024, 07:56:37 pm
content: Hi,I am playing with a Xilinx XC9500XL CPLD.My design is basically a bridge between a "high" speed and a low speed parallel bus, and some control logic.Since it is getting quite warm I am experimenting with the macrocell power setting.Setting the global power flag to low makes this design not work, I guess because of the high speed side timings.I am now trying to use the "Timing driven" setting in the Fitting properties, in order to set the macrocells to low power on the low speed side only.Setting constraints on the clocks made the fitter to set a couple of internal signals to low power, but everything else remained "standard" power. Constraining slow timings on periods and offsets does not seem to change the power of most macrocells.I have the CPLD timing xapp1047 and the Xilinx Constraints Guide ug625. I foundhttps://adaptivesupport.amd.com/s/article/2717?language=en_USbut the said "Xilinx Answer 2146 is not available anymore" (and the URL was not indexed in the wayback machine). Yet I could not find a solution, neither a good example on the net.By chance do you have a clue about this "Timing driven" power setting ?

author: JimboJack
author_rank: Regular Contributor
timestamp: November 21, 2024, 02:22:30 am
content: 9371 has alternative but similar info, which by looks like it line (1) is already have tested.9371 - CPLD XC9500 Family - Suggestions for lowering power consumptionhttps://adaptivesupport.amd.com/s/article/9371?language=en_USSolution1. Set the device to Low Power mode. This is done by setting the macrocell power setting to "Low" in the implementation options.2. Use global resources instead of product terms whenever possible3. Set the unused I/O to ground. You can accomplish this by setting "Create Programmable Ground Pins on Unused I/O" in the implementation options.4. For XC9500 5-volt devices, ensure that you have pin and local feedback enabled in the implementation options.Understanding XC9500XL CPLD Power Xapp114.pdfhttps://docs.amd.com/v/u/en-US/xapp114Using the XC9500XL Timing Mode Xapp111.pdfhttps://docs.amd.com/v/u/en-US/xapp111

author: Sassa
author_rank: Newbie
timestamp: December 07, 2024, 04:28:38 pm
content: Hi.The manual way I found to do it is to add the PWR_MODE attribute before each output, inout and reg declaration inside my verilog code.Code:(* PWR_MODE = "LOW" *) reg myreg=1'b0;
Salvage board for sale on ebay - Page 1
Forum section: electronics / general

author: nth_degree
author_rank: Regular Contributor
timestamp: October 21, 2024, 03:52:27 pm
content: worth buying? could it be REed I wonder if worth the timehttps://www.ebay.com/itm/196738340707

author: coromonadalix
author_rank: Super Contributor
timestamp: October 21, 2024, 05:19:59 pm
content: if you don't have a way to test it before dismantling it, and have proper tools to remove them, and reball them to other boards ...stay away

author: mark03
author_rank: Frequent Contributor
timestamp: October 21, 2024, 08:34:24 pm
content: What does the seller mean by "unlocked"? I wasn't aware FPGAs could be locked. Certainly you'll need a $$$ license to program these things, assuming the reverse-engineering gets that far.

author: tggzzz
author_rank: Super Contributor
timestamp: October 21, 2024, 09:22:45 pm
content: Quote from: nth_degree on October 21, 2024, 03:52:27 pmThis is one of those things where, if you have to ask the question, the answer is "avoid"

author: thm_w
author_rank: Super Contributor
timestamp: October 21, 2024, 10:17:47 pm
content: Seller started looking into it then didn't persue I guess:https://github.com/wirebond/nyanritsu_322u17954They bought it for $200 and try to sell for $1,100? hell no. Offer $200 if you really want it.

author: nctnico
author_rank: Super Contributor
timestamp: October 21, 2024, 11:08:43 pm
content: Quote from: thm_w on October 21, 2024, 10:17:47 pmI'd offer $10 if shipping isn't super expensive. Just for the RF connectors and attenuators IF I would need those. Scrap the rest. There is zero worth in this board.

author: Murphy86
author_rank: Newbie
timestamp: December 05, 2024, 06:15:41 pm
content: FPGA can be locked, Burn EFUSE bits and you have encrypted firmware. Without key its unusable brick.
Trying to create accelerator with vivado + SDK - Page 1
Forum section: electronics / general

author: e0ne199
author_rank: Regular Contributor
timestamp: November 27, 2024, 03:15:34 pm
content: Hello everyone, I have a question about FPGA acceleration with vivado..Currently I am working on an accelerator project using minized as the main platform. Here is the block diagram that I have built so far :The modules are all connected through AXI master-slave bus. The PL will be controlled by the PS which will be programmed with C language using SDK (I am using vivado 2018.4), However I am confused about how to control the "sel" input and the "start" input on the "mat_mul_0" module or how to interface them so that they can be controlled through SDK..Do you know how to control those two pins through SDK and where to connect them in vivado?Any response for this problem is really appreciated, thanks before

author: ejeffrey
author_rank: Super Contributor
timestamp: November 27, 2024, 03:51:55 pm
content: I'm it sure exactly what you are trying to achieve, or how that matrix multiplier block is meant to be used. If you just need to asynchronously toggle those pins from the PS, the easiest way is to instance an AXI-Lite GPIO module and connect the output pins to those signals. If you need to trigger them at specific times relative to the data stream you probably need some glue RTL that detects the conditions based on the AXI-Stream data, or maybe some of the control signals from the DMA controller.

author: e0ne199
author_rank: Regular Contributor
timestamp: November 27, 2024, 05:54:26 pm
content: Quote from: ejeffrey on November 27, 2024, 03:51:55 pmThe RTL block is used as a matrix multiplication module and the "sel" input is used to select either "bram A" or "bram B" inside the block..once it is selected, the "start" input is used to start the data transmission to selected bram..btw, as far as I know, AXI-Lite GPIO is used as interface to hardware pins on the board, is that okay if it is used to signal the RTL block?

author: ejeffrey
author_rank: Super Contributor
timestamp: November 28, 2024, 12:51:29 am
content: Quote from: e0ne199 on November 27, 2024, 05:54:26 pmYes you can use an axi lite gpio to signal RTL blocks. It's just a way to control signals, you can connect them to external pins or internal nets. That definitely seems like the way to control the sel input.Normally I would expect the "start" input to be derived from stream fields like tuser or something. But maybe you can just use a GPIO signal.
Lattice XO2 clock pins/signals - Page 1
Forum section: electronics / general

author: sw_guy
author_rank: Regular Contributor
timestamp: November 23, 2024, 06:52:49 pm
content: Trying to understand clock signals - mainly how to use Diamond. The device is XO2-1200, package QFN32 and the software is Diamond.I have an external input signal TTLIN which was routed to a pin 4. Pin 4 is a clock signal pin. I moved the signal to another clock signal pin 12. I get this warning:61061008 WARNING - Signal "TTLIN_c" is selected to use Secondary clock resources. However, its driver comp "TTLIN" is located at "12", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.On the Clock Resource tab the signal has Secondary clock as an option for both of the pins. I am unable to find any explanation how PCLKC2 is different than PCLKT3.Another, probably very easy task to do, is that the signal DIVIDER0/1 is determined as a clock signal. I assume there is a way to tell that the signal is not a clock signal but the Pin Assignments tab does not allow to change the Signal type (it is readonly). I assume that can be done in LPF file but it is surprisingly difficult to find information how to do that.And I know: those are only warnings and everything works. I am trying to learn how to set parameters correctly.sw guy

author: ataradov
author_rank: Super Contributor
timestamp: November 23, 2024, 09:06:38 pm
content: Only true (T) sides if the differential clock pair is connected to the clock routing network. Complimentary (C) side is just a regular pin if the clock is single ended.Everything will work to some extent, it is just going to be routed though the fabric.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 23, 2024, 09:33:30 pm
content: Yes, that's it. PCLKCx is a complementary clock input for differential clocks. A single-ended clock can't use it as a global clock input.

author: sw_guy
author_rank: Regular Contributor
timestamp: November 24, 2024, 07:32:43 am
content: Thanks. This is clear.How about signals DIVIDER0/1. Is there a way to tell those are not clock signals or is that inevitable outcome of the synthesis (based on the code)?

author: ataradov
author_rank: Super Contributor
timestamp: November 24, 2024, 03:47:23 pm
content: That does not matter. It is just a tool figuring out that it is beneficial to route that signal over the global clock network. They are there anyway even if not used, so might as well use them to route signals that require tight timings or have large fanouts.
JESD204C over Optical Fiber - Page 1
Forum section: electronics / general

author: yifeng.yuan
author_rank: Newbie
timestamp: November 22, 2024, 04:13:55 pm
content: Hello fellow engineers!I have a project that requires me to design an interface solution between my data converter and FPGA board. The data interface is JESD204C. I know FMC connect is a standardized connector for this purpose. However, I am considering using optical fiber to replace the FMC connectors. Does anyone have experience with this approach? I wish to learn from the pioneers.I am aware of another posthttps://www.eevblog.com/forum/fpga/jesd204b-over-fiber/msg4673455/#msg4673455. But this post focuses on JESD204B.Thank you.
Searching for Launch Diagun firmware from EPM240 Chip. - Page 1
Forum section: electronics / general

author: junkandshitandjunk
author_rank: Newbie
timestamp: December 07, 2022, 04:57:42 pm
content: Hello, i need firmware from Launch Diagun 2 obd unit, chip model is EPM240T100C5N (Altera CPLD) maybe some of you have it. Dump is possible to make via parralel port prograammer, or altera usb blaster. Software for dumping Altera Quartus.My chip has short on gnd and VCCINT pins, so i cannot make a dump from old bad chip. Some of these Launch Diaguns have security bit enabled on these CPLD , then its not possible to make dump, but i know its not in all models, chinese clones does not have it.There is nearby pins for dumping (T1-T4)

author: Mihai85
author_rank: Newbie
timestamp: November 20, 2024, 02:26:28 pm
content: Hello! I am facing the same problem, the software for EPM240T100C5N. The chip is short-circuited.
does exist a mirror of ftp.altera.com? - Page 1
Forum section: electronics / general

author: gfernval
author_rank: Contributor
timestamp: November 08, 2024, 10:27:51 am
content: I´m searching the files 90sp2_dsp_builder_windows.exe (106,965,748 bytes) and 71_dsp_builder.exe (50,216,225 bytes)Does someone know if exist a mirror repository of ftp.altera.com? A partial listing for ftp.altera.com files is inhttps://mbb.eet-china.com/blog/1324799-237580.html

author: RoGeorge
author_rank: Super Contributor
timestamp: November 08, 2024, 10:58:54 am
content: If you know from what package/installer version those files were part of, maybe you can guess the name for the exact download path. The ugly thing is that you'll have to guess the exact package name that will redirect to the current Intel URL, it is not possible to browse those locations.Some download file URLs (from the old download.altera.com) might still be available, see the links format from this post, and try to adapt that to your file, maybe you guess the correct URL:https://www.eevblog.com/forum/fpga/arrow-deca-max-10-board-for-$37/msg3646726/#msg3646726

author: gfernval
author_rank: Contributor
timestamp: November 08, 2024, 11:50:40 am
content: I have tried, does not work, doubt these URLs works with versions before 10.0

author: ZigmundRat
author_rank: Regular Contributor
timestamp: November 19, 2024, 05:01:18 am
content: Check the DataIOEPROM group at groups.ioSupposedly the V9 file was uploaded to the files area. See the thread:https://groups.io/g/DataioEPROM/topic/altera_quartus_9_0_sp2_files/109264316I couldn't find the other file, but maybe this helps.
building analog devices ADC HDL examples - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 28, 2024, 03:26:34 pm
content: Hi,I have found this repo from analoghttps://github.com/analogdevicesinc/hdlI want to build some example projects to see how their HDL drivers for their ADC's works, I'm using win11 and I have installed Cygwin64 and have followed the repo instructionsI run Cygwin64 and then typed these commandsQuoteQuotethen this oneQuotethe make would complain that there is no makefileand this command has no makefile eitherQuotethen I try to build some examples using vivado so I tried these commandsQuoteQuoteI would get some build errors and there is a log file and in the log file it saysQuoteBut I have vivado 2023.1 installed on my win11 machineDo you have any Idea how to build the sample projects?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 29, 2024, 12:23:26 pm
content: Has anyone used thier repo in here? I think if we could use it, it has the driver for many ADC's there.

author: iMo
author_rank: Super Contributor
timestamp: November 30, 2024, 09:28:09 am
content: Quote
Ise Would not detect XC6SLX45 - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 26, 2024, 12:24:30 pm
content: HiI have designed a board with XC6SLX45-2FGG484I and ISE would not recognize the part, it would say an unknow device, I have checked everything and it seems the config schematics is ok, I assigned a spartan6 device bsdl file from C:\Xilinx\14.7\ISE_DS\ISE\spartan6\data folder, so the impact would let me read device id etc..when I read device ID I would get something very similar, only two bits that should be 1 are 0, do you have any Idea what might have caused it or what's the problem?

author: xvr
author_rank: Frequent Contributor
timestamp: December 26, 2024, 12:34:06 pm
content: Wrong FPGA (package)? You mentioned XC6SLX45-2FGG484I, but in iMPACT selected CSG484 package. ID could be different.

author: langwadt
author_rank: Super Contributor
timestamp: December 26, 2024, 12:45:36 pm
content: try scoping the signals and/or change the jtag frequency

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 26, 2024, 02:37:38 pm
content: QuoteI have changed that and got the same resultsQuoteI have tested all the frequencies from 250Khz to 30Mhz, the same result.I have assembled two boards and both have the same issue, I'm pulling out my hair and I have no clue what might be wrong.Some other parts of the schematics

author: xvr
author_rank: Frequent Contributor
timestamp: December 26, 2024, 03:02:08 pm
content: Counterfeit chip? ID read do not belong to Spartan 6 family

author: langwadt
author_rank: Super Contributor
timestamp: December 26, 2024, 04:44:54 pm
content: where did you get the part?https://adaptivesupport.amd.com/s/question/0D52E00006hpPYwSAM/unknown-jtag-id-code-for-xilinx-xc6slx752ffg484i?language=en_US
Advice for my graduation project - Page 1
Forum section: electronics / general

author: HasanSyr
author_rank: Contributor
timestamp: November 02, 2024, 04:54:09 pm
content: I'm creating an FPGA development board (around a carrier card, hardest parts like DDR and SMPS already done) for my thesis graduation project, I'm under the presumption that using Altium would be better for more complex designs like this. I tried Altium and I'm really not liking it (maybe I'm not used to it yet) so I'm wondering if it's feasible to create a project like that with KiCadThe main issues in KiCad for me are the mechanical tools (board outline etc) and the alignment of components, when I select more than 1 thing and try to align one of them KiCad aligns the part relative to the part I don't want to be aligned. This is a big issue for me when trying to center things or space things apart equally.

author: zapta
author_rank: Super Contributor
timestamp: November 11, 2024, 08:53:06 pm
content: Did you try to change the 'magnetic points' in the PCB Editor settings?Also, you can force any x,y that you want by opening the device priorities and typing them in.EDIT: In the PCB Editor, when you right-click, the popup menu also has 'positioning tools' that can help you moving any way you want.

author: bson
author_rank: Unknown
timestamp: November 12, 2024, 10:25:38 pm
content: In KiCad when you align objects they're aligned to the one selected first. So explicitly select the one you want to align to first, then add the rest to the selection.

author: gavin199
author_rank: Newbie
timestamp: January 06, 2025, 07:10:24 am
content: Maybe you can try EasyEDA, in which you can find plenty of OpenSource Project in the cloud and you can just Clone like a code to your space. Besides, you can send your PCB to the fabric, and get the PCBA in one click, they will send you the boards, and you just need to power on, and it works..., just like online shopping, but with your design.

author: Smokey
author_rank: Super Contributor
timestamp: January 06, 2025, 07:33:06 am
content: Presumably you are in an EE program. If you want to get a job that has anything to do with PCB design, use Altium if you have access to it. Almost no jobs will care if you list "KiCad skills", but real companies use Altium.Two question through. You said you are "already done" with the DDR and power supply. What did you use for that? And if you actually did a DDR layout you are happy with, how are you still having issues with the board outline and component alignment?
Lattice CrossLink FPGA configuration using I2C - Page 1
Forum section: electronics / general

author: bachehkaraji
author_rank: Newbie
timestamp: November 05, 2024, 10:08:53 am
content: Hi,I have a Lattice LIF-MD6000 FPGA based board and I am currently trying to program the CrossLink through I2C with Lattice Diamond Programmer and HW-USBN-2B download cable. In any of the ways I get an ERROR but I don't have any problem when using SPI.can someone help me?