Editing Default Pin Input Value in Quartus II - Page 1
Forum section: electronics / projects

author: zdelarosa00
author_rank: Regular Contributor
timestamp: October 10, 2016, 04:49:49 am
content: Hi!, I had designed a simple VHDL component for a class, its a BCD adder-substractor, 2 operands, 12 bit each (3 digits, 4 per digit)... And had come to various enigmas while finishing...My chinese kit board has a Cyclone I, and 2 6-dip-switches, none of wich has pull up/down resistors, one connects the pins to GND and the other to VCC (see attachement), the thing is, the one connected to VCC gives me trouble because if I change the sw position nothing changes, that is because the open input is "defaulting" as 1 (thus, acting as 1111, not even valid in bcd), so toggling between 1 and 1 is making my operations non-possible, here comes the interesting part...I did some research and learnt that as I expected, you can configure a "Default Input Value" for an input pin, Vcc or GND, the thing is, the altera help pages make you go to a "Pin properties dialog" to change it, to go there you have to right-click a pin in a *.bdf file (block design) and go to properties, in the "General" tab you can change the said setting.... I had no *.bdf, I started my desing in a VHDL file, so with some research I learnt that in my vhdl file I have to click file->create->create symbol file, wich then gives you a *.bsf (Symbol File), and after messing around and finding no related answer, I discovered that theres no way you can convert the *vhdl or the *bsf file into a *bdf, what I did was Create a new *bdf from scratch from the new file dialog, and then imported (right clicking empty space) my *bsf into it, but then, nor in the symbol editor or the block editor (opening the files) I can edit this pin properties, I have tried with no success a number of strange procedures, the help page says that I can only edit this "Default pin value" in the low-level block design, inside my then non-existent *bdf, so this is the point where I am lost.... How can I create my low-level (I have the top-level) block design file, or another way of changing this setting?... This is an structural/modular component so its functioning is divided into frec divider, main adders, mux/deco for the 7-seg displays, adjusters and such... How can I edit this pins settings or create a low-level block design file?https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07131998_7491.htmlhttp://quartushelp.altera.com/15.0/mergedProjects/design/ged/ged_com_pin_prop.htmhttp://quartushelp.altera.com/15.0/mergedProjects/design/ged/ged_pro_create_symbol.htm

author: AndyC_772
author_rank: Super Contributor
timestamp: October 10, 2016, 06:45:37 am
content: Cyclone FPGAs contain weak pull-up resistors, which can be turned on and off, but not pull-down. You can't have a pin which reliably reads 0 when floating.To enable a pull-up, go into the Assignment Editor and apply the property Weak Pull Up = Yes to the physical pin.I've never used a BSF or BDF file; I presume they're something to do with schematic entry, which you don't need because you're already programming in VHDL. Whatever they are, they can't overcome the physical limitations on the chip.If you have an input pin which needs to read 0 when unconnected, you need to fit a real physical pull-down resistor to the board.

author: Siwastaja
author_rank: Super Contributor
timestamp: October 10, 2016, 07:40:49 am
content: Default pin value is totally irrelevant to your issue.Default pin value means a VHDL or block diagram property which decides the pin value in cases where you don't connect a port signal at all. If you know C or C++, you can think it as analogous to default value on a function argument.Your signal, naturally, is connected to the pin, so it doesn't take the default value, but the electrical value in the pin.What you want to use is a HW feature of the IO port cell, not a port default value. You can use the Assignment Editor to enable the weak pull-up resistor, but in this case, you appear to need a pulldown resistor, which, IIRC, doesn't exist in cyclone series FPGAs, so the only option is to solder pulldown resistors (anything around 5 to 50K is fine) on the DIP switch, which, of course, will be super easy to do.