Estimating time spent on Miller Plateau (maths) - Page 1
Forum section: electronics / projects

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 10:08:20 am
content: I really wish I was better at maths, but I have to live with my shame. IthinkI'm doing this right, but would muchly appreciate if someone could confirm my method - or point out what I'm doing wrong!I'm trying toestimatethe time spent on the Miller Plateau when PWM switching asmall-ish MOSFET(ID~2 A, VDS~12 V) at ~30 kHz. I know the gate capacitance is useless for this, and total gate charge is what I should be looking at - which is listed as QG(tot)11 nC. I also know VGS(th)is equally useless (listed as 1.5 V), and that I need to look at the VGS/ RDS(on)plot to see when the MOSFET is fully conducting, which I think means VGS(on)~3 V. Then I do this:Effective gate capacitance CG(eff)= QG(tot)/ VGS(on)= 3.67 nFGate resistance RG= 1 Ω (guesstimate)External gate resistor RG(ext)= 100 ΩMCU pin resistance RG(drv)= 25 Ω (guesstimate)Total gate resistance RG(tot)= RG+ RG(ext)+ RG(drv)= 126 ΩGate charge time TG(on)= CG(eff)× RG(tot)= 462 nsTpwm= 1/30 kHz = 33.3 usIf this is correct I estimate the time spent on the Miller Plateau to be:% Miller T @ 100% duty = (TG(on)/ Tpwm) x 100 = 1.39%% Miller T @ 50% duty = (TG(on)/ Tpwm) x 200 = 2.78%% Miller T @ 25% duty = (TG(on)/ Tpwm) x 400 = 5.55%% Miller T @ 12.5% duty = (TG(on)/ Tpwm) x 800 = 11.1%P.S. This isnotcoursework but an attempt at determining whether I can get away without a dedicated gate driver for a homebrew project. If my calcumulations are correct-ish I guesstimate that Ican.

author: xvr
author_rank: Frequent Contributor
timestamp: June 12, 2024, 10:45:58 am
content: QuoteWhy not use LTSpice (or similar) to get rid of doubts?

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 11:02:27 am
content: Quote from: xvr on June 12, 2024, 10:45:58 amI've done a few simulations inQUCSbut not often enough that I don't find it both time consuming and confusing. It would take me hours to do and I still wouldn't know if the result was accurate, because I don't really understand how it works. I can and want to understand the calculations above, so if my method is correct that would give me enough confidence to get some boards made. Ultimately I can only be sure by testing a completed PCB in a real world application - which would include things like cable runs, enclosure and heatsinking.

author: ArdWar
author_rank: Frequent Contributor
timestamp: June 12, 2024, 11:06:07 am
content: Are you trying to calculate only the plateau (QGD) or the entire switching period (QG(tot))?For the plateau it's quite simple actually.Tp= QGD/ IG= QGD/ (VPL/ RG(tot))= 4.6 nC / (2.3 V / 126 Ω) = 230 nsSome reading:https://www.ti.com/lit/an/slpa009a/slpa009a.pdf

author: xvr
author_rank: Frequent Contributor
timestamp: June 12, 2024, 11:09:41 am
content: QuoteBut if result of your caslculation is the same as from QUCS than you can trust your result. If not, then you should find out the culprit - your calculation or QUCS

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 11:19:52 am
content: Quote from: ArdWar on June 12, 2024, 11:06:07 amI'm just after aroughestimate of the proportion of time spent in the ohmic region relative to duty cycle at 30 kHz PWM. The objective being to determine whether I can turn on the MOSFET quickly enough to avoid excessive power losses (and heating) without needing a dedicated gate driver.Quote from: ArdWar on June 12, 2024, 11:06:07 amI'll see your PDF and raise you one from Vishay:https://www.vishay.com/docs/73217/an608a.pdf

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 11:45:04 am
content: Quote from: ArdWar on June 12, 2024, 11:06:07 amHaving stared at it for a while I think I understand your method, but I have a few questions: IGin my case is 40 mA (max) so with QGD= 4.6 nC Tp= 115 ns. But you're calculating the gate current differently - why use VPLinstead of VG(drv)? And why QGDinstead of QG(tot)? Does this represent the charge needed to getpastthe plateau, or toreachit?Edit:A quote from that Vishay PDF:QuoteThis seems to suggest that in order to calculate the time it will take to exit the plateau I should be using QGS(1.6 nC) + QGD(4.6 nC) = 6.2 nC. Correct?

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 01:01:56 pm
content: While no one has answered my original question directly, I think I've gleaned enough from@ArdWar's reply to feel I'm at least on the right-ish track - though my estimated time accounts for fully switching on the MOSFET rather than just passing the Miller Plateau (i.e. I based it on QGin the graph above). This indicates that at low-ish (10-15%) duty cycles at 30 kHz only about 10% of the time will be spent outside the fully on state. That's good enough forAustraliame!Edit:Reading my first post again I see I actually askedthe wrong question, and that this was in fact answered100%by @ArdWar. My apologies! What I meant to ask (and thought I did) was whether I was correctly calculatingthe time it will take to exit the Miller Plateau from the start of each PWM pulse- not just the duration of the Miller Plateau itself.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 12, 2024, 01:09:20 pm
content: What's drive, a current limited source? Or resistor and voltage source?If resistor, current is Vdrv - Vpl pulling up, or Vpl pulling down, divided by the total loop resistance.Plateau voltage is more or less Vgs(Id), which at your 2A condition, will be barely above Vgs(th) (see Fig.6), though there's also a rate factor due to the source inductance common between gate and drain circuits. Which means, given a resistive load, the rising and falling Vpl's differ by +/- L dI/dt.Plateau duration is given by gate current and G-D charge: Q_GD specifies this, for Vds(initial) = 44V, and as you can see from Fig.14, it varies with Vds. For any other voltage, you'd have to integrate C_rss (Fig.16) up to the voltage of interest. If that's too much trouble, just guard-banding the design (design for at worst so-and-so performance, and make everything else handle the best-case result) is fine.Tim

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 02:25:58 pm
content: Gate is driven directly from an MCU, which can deliver 40 mA (at 5 V). Hence 100 Ω gate resistor. The gate is pulled down with a 10k Ω resistor, to keep it from floating during start-up. While switching losses mainly occur during the plateau, I need the time from cycle start to know how large a percentage of the PWM pulse will be spent before the MOSFET is fully on, so I will use QGS+ QGDto estimate the capacitance that needs to be satisfied before the end of the Miller Plateau (instead of QG(tot)). To convert this to time I will use Vgp(2.3 V) rather than VGS(on). With these changes I get:Effective gate capacitance CG(eff)= (QGS+ QGD) / Vgp= (1.6n + 4.6n) / 2.3 =2.7 nFGate resistance RG= 1 Ω (guesstimate)External gate resistor RG(ext)= 100 ΩMCU pin resistance RG(drv)= 25 Ω (guesstimate)Total gate resistance RG(tot)= RG+ RG(ext)+ RG(drv)= 126 ΩGate charge time TG(on)= CG(eff)× RG(tot)=339 nsTpwm= 1/30 kHz = 33.3 us% Miller T @ 100% duty = (TG(on)/ Tpwm) x 100 =1.02%% Miller T @ 50% duty = (TG(on)/ Tpwm) x 200 =2.04%% Miller T @ 25% duty = (TG(on)/ Tpwm) x 400 =4.08%% Miller T @ 12.5% duty = (TG(on)/ Tpwm) x 800 =8.16%This is actually a slightlybetterresult than my initial attempt.Quote from: T3sl4co1l on June 12, 2024, 01:09:20 pmIt might not be to others, but yes, to me it is. I'm happy with a an estimated "worst case", which I think the above gives. I'm also happy with 10% of the pulse width at 10% duty being spent before the MOSFET is fully on. Seems low enough that I shouldn't need to worry too much about switching losses?

author: iMo
author_rank: Super Contributor
timestamp: June 12, 2024, 02:29:31 pm
content: I do not have your exact BUK model handy, but basically the LTspice shows some results..

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 02:39:41 pm
content: Quote from: iMo on June 12, 2024, 02:29:31 pmThanks for that! It looks almost three times slower than my estimate, assuming the PWM pulse starts around the 133.2 us mark?That said, the BUK7Y8R7-60E is a considerably beefier MOSFET (87 A IDvs. 7 A ID). It has a combined QGS+ QGDof 23.8 nC, which is four times higher than my part...

author: iMo
author_rank: Super Contributor
timestamp: June 12, 2024, 02:50:36 pm
content: The first mosfet is not logic level one, but standard one (will not work at 3.3V input).I added above a logic level trench BUK mosfet (pictures A and B), the rising/falling edge plateaus are aprox 200ns long. The input pulses are 3.3V, 3ns edges, 30kHz.In LTspice I can see around 100 BUK models (see below) but not yours..Perhaps you may decide to use a BUK logic level mosfet which is in the LTspice as well..

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 04:34:52 pm
content: Quote from: iMo on June 12, 2024, 02:50:36 pmThanks! I've looked through theBUK selection chartand mine is the smallest one. There are no equivalents in the LTSpice list. These seem quite similar:IRLL024ZSQ3426RSH065RSS070DMN6068

author: iMo
author_rank: Super Contributor
timestamp: June 12, 2024, 05:00:27 pm
content: Only this one in my LTspice..568ns/83nsPS: mind at the falling edge of the Vgs (picture b) the plateau is only 83ns long, but the Vds "linear" region (power loss or heat at max) is much longer..

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 12, 2024, 05:44:58 pm
content: Keep in mind, the exact results depend on the models used; I'm inclined to suspect very basic (usually LEVEL=3 modified with external nonlinear capacitors) models, which I commonly see from IR parts. (I haven't checked, myself, what LTSpice uses for these.)There's no linear range on a real component, to be clear; it looks like they're using a breakover function, to change the capacitance, probably when Vdg < 0, which is also erroneous as it doesn't depend on Vgs at all, it's purely a Vds dependence in all vertical devices I've tested. But whatever, it's close enough to release as a model, right.The general caution is, do take care not to trust in the simulation models very much. They're always approximations by definition, but how crude of one, varies widely with age and source.It's noteworthy that Crss increases steadily as Vds drops, meaning most of the plateau is spent at low Vds, where Pd is also lower. Another commonly quoted approximation is to calculate switching loss as the triangular region between Vds falling (linear ramp) and Id rising (or vice versa), usually one after the other (inductive load switching) so the area is simply \$\frac{V_\text{DS} I_\text{D} t_\text{on}}{2}\$. But this is at best only a crude approximation even for devices contemporary with the method (i.e. IR appnotes/databooks from the 80s and 90s), and modern highly optimized designs only get wilder as time goes on. (Some hardly have a plateau at all: TI NexFETs use a sort of cascode structure to nearly eliminate Crss!)Tim

author: coppercone2
author_rank: Super Contributor
timestamp: June 12, 2024, 06:06:53 pm
content: this is when you finally get a miller and it was so expensive that you don't want to buy argon anymore.

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 06:14:13 pm
content: Crude approximation is fine by me - I only wanted to establish withrelativeconfidence that despite not using a dedicated gate driver 1) switching losses will not pose a problem wrt heating and 2) switching speed will be sufficient to operate at 10% duty at 30 kHz without losing a significant amount of power. I think the calculations we've done in this thread, as well as the simulation results kindly provided by@iMoindicate that both these things are likely to be true - if anyone thinks otherwise I would love to hear why!

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 08:29:12 pm
content: After some tinkering I've managed to get an Ngspice simulation running in KiCAD. I had to upgrade to KiCAD 8 to get it to work, and downloadthe SPICE modelfor the IRLL024Z MOSFET, which I think is the closest match to the BUK9880-55A that there is a model available for. It does have a lower gate charge of QG(tot)7 nC, vs 11 nC for the BUK part, but otherwise fairly close. I have to say I would beextremelyhappy to see this sort of performance once I put my scope on the real thing:For the purpose of this simulation I upped the frequency to 90 kHz and set the pulse width to 3.3 us - just so I could get a few cycles on screen and get a feeling for the slope widths relative to the pulse width (equivalent to 10% duty at 30 kHz). Here is the circuit used:Zoomed in view of the transition:

author: Lomax
author_rank: Frequent Contributor
timestamp: June 12, 2024, 08:53:19 pm
content: I thought I could be clever and edit the model file to increase the gate charge, but when I open it in my text editor I cannot find any of the relevant parameters (qgs, qgd, qgb, qbd, qbs), in fact I cannot find a single "q".Code:.SUBCKT irll024z 1 2 3* SPICE3 MODEL WITH THERMAL RC NETWORK*************************************** Model Generated by MODPEX **Copyright(c) Symmetry Design Systems** All Rights Reserved ** UNPUBLISHED LICENSED SOFTWARE ** Contains Proprietary Information ** Which is The Property of ** SYMMETRY OR ITS LICENSORS **Commercial Use or Resale Restricted ** by Symmetry License Agreement **************************************** Model generated on Aug 2, 04* MODEL FORMAT: SPICE3* Symmetry POWER MOS Model (Version 1.0)* External Node Designations* Node 1 -> Drain* Node 2 -> Gate* Node 3 -> SourceM1 9 7 8 8 MM L=100u W=100u.MODEL MM NMOS LEVEL=1 IS=1e-32+VTO=2.68037 LAMBDA=0 KP=50.9433+CGSO=3.45542e-06 CGDO=1e-11RS 8 3 0.0526075D1 3 1 MD.MODEL MD D IS=3.47862e-10 RS=0.0385371 N=1.3551 BV=55+IBV=0.00025 EG=1 XTI=1 TT=1e-07+CJO=9.646e-11 VJ=4.92267 M=0.603074 FC=0.5RDS 3 1 1e+07RD 9 1 0.0001RG 2 7 2.04568D2 4 5 MD1* Default values used in MD1:* RS=0 EG=1.11 XTI=3.0 TT=0* BV=infinite IBV=1mA.MODEL MD1 D IS=1e-32 N=50+CJO=1.41556e-10 VJ=0.5 M=0.369812 FC=1e-08D3 0 5 MD2* Default values used in MD2:* EG=1.11 XTI=3.0 TT=0 CJO=0* BV=infinite IBV=1mA.MODEL MD2 D IS=1e-10 N=0.4 RS=3e-06RL 5 10 1FI2 7 9 VFI2 -1VFI2 4 0 0EV16 10 0 9 7 1CAP 11 10 7.11958e-10FI1 7 9 VFI1 -1VFI1 11 6 0RCAP 6 10 1D4 0 6 MD3* Default values used in MD3:* EG=1.11 XTI=3.0 TT=0 CJO=0* RS=0 BV=infinite IBV=1mA.MODEL MD3 D IS=1e-10 N=0.4.ENDS irll024z*SPICE Thermal Model Subcircuit.SUBCKT irll024zt 3 0R_RTHERM1 3 2 5.339593596R_RTHERM2 2 1 19.88146552R_RTHERM3 1 0 19.77062808C_CTHERM1 3 0 0.000150761C_CTHERM2 2 0 0.035240360C_CTHERM3 1 0 1.052065717.ENDS irll024ztAny ideas?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 12, 2024, 11:10:22 pm
content: Oh god, yeah it's even worse than I remembered... LEVEL=1 MOSFET, just not very good at all. Good enough for gross switching purposes, but convergence may be problematic with the discontinuities in the model, and not very good for low current or small-signal purposes. (In particular, subthreshold isn't modeled at all, I think?)Charge parameters are encoded in the dependent capacitances, particularly CGSO, CGDO (if they used more than a token negligible value I guess), and MD1-3 CJOs. You'll want to sketch out the netlist as a schematic and see what components go where. I believe they model it as a nonlinear capacitor from D to G, which is erroneous, but not wildly so.Tim

author: iMo
author_rank: Super Contributor
timestamp: June 13, 2024, 07:24:36 am
content: FYI - this is the model I've found in my LTspice..Code:.SUBCKT irll024z 1 2 3* SPICE3 MODEL WITH THERMAL RC NETWORK*************************************** Model Generated by MODPEX **Copyright(c) Symmetry Design Systems** All Rights Reserved ** UNPUBLISHED LICENSED SOFTWARE ** Contains Proprietary Information ** Which is The Property of ** SYMMETRY OR ITS LICENSORS **Commercial Use or Resale Restricted ** by Symmetry License Agreement **************************************** Model generated on Aug 2, 04* MODEL FORMAT: SPICE3* Symmetry POWER MOS Model (Version 1.0)* External Node Designations* Node 1 -> Drain* Node 2 -> Gate* Node 3 -> SourceM1 9 7 8 8 MM L=100u W=100u.MODEL MM NMOS LEVEL=1 IS=1e-32+VTO=2.68037 LAMBDA=0 KP=50.9433+CGSO=3.45542e-06 CGDO=1e-11RS 8 3 0.0526075D1 3 1 MD.MODEL MD D IS=3.47862e-10 RS=0.0385371 N=1.3551 BV=55+IBV=0.00025 EG=1 XTI=1 TT=1e-07+CJO=9.646e-11 VJ=4.92267 M=0.603074 FC=0.5RDS 3 1 1e+07RD 9 1 0.0001RG 2 7 2.04568D2 4 5 MD1* Default values used in MD1:* RS=0 EG=1.11 XTI=3.0 TT=0* BV=infinite IBV=1mA.MODEL MD1 D IS=1e-32 N=50+CJO=1.41556e-10 VJ=0.5 M=0.369812 FC=1e-08D3 0 5 MD2* Default values used in MD2:* EG=1.11 XTI=3.0 TT=0 CJO=0* BV=infinite IBV=1mA.MODEL MD2 D IS=1e-10 N=0.4 RS=3e-06RL 5 10 1FI2 7 9 VFI2 -1VFI2 4 0 0EV16 10 0 9 7 1CAP 11 10 7.11958e-10FI1 7 9 VFI1 -1VFI1 11 6 0RCAP 6 10 1D4 0 6 MD3* Default values used in MD3:* EG=1.11 XTI=3.0 TT=0 CJO=0* RS=0 BV=infinite IBV=1mA.MODEL MD3 D IS=1e-10 N=0.4.ENDS irll024z*SPICE Thermal Model Subcircuit.SUBCKT irll024zt 3 0R_RTHERM1 3 2 5.339593596R_RTHERM2 2 1 19.88146552R_RTHERM3 1 0 19.77062808C_CTHERM1 3 0 0.000150761C_CTHERM2 2 0 0.035240360C_CTHERM3 1 0 1.052065717.ENDS irll024zt

author: ArdWar
author_rank: Frequent Contributor
timestamp: June 13, 2024, 10:26:31 am
content: Quote from: Lomax on June 12, 2024, 11:45:04 amIt's the charge between one end to the other end of the plateau. Since it is charging at a constant voltage differential then the charging current can beroughlyapproximated to be constant. Sure it isn't that simple and the width of the plateau itself isn't constant either.By the way if you need some SPICE of random FETs to play with you can go to Diodes, they usually have level 3 models of their parts.By the way, that IR model looks quite sophisticated with parasitics manually modelled outside of the actual NMOS model itself. Certainly not a simple level 1 model.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 13, 2024, 11:14:07 am
content: Quote from: ArdWar on June 13, 2024, 10:26:31 amWell, I wouldn't say "quite"; they're modeling the nonlinear capacitance better than the MOS intrinsic, but they could do a better job without much work. Set up a test harness yourself and compare a real part to the model; you'll see the weirdness in the curves, discontinuity in the model, etc. Is it wildly out? Nah, but depends on what regime you're interested in, and the exact switching edges aren't quite right, the gm isn't quite right, the C curves aren't quite right, it's close enough for many purposes but you poke around the edges and see lots of unrealistic or missing behavior.Probably the most elaborate models I've seen are from Infineon, it's been a while since I checked as I haven't had any need to model things in such detail, but some of them anyway, the whole thing was a pile of behavioral sources, no primitive/built in models at all; it ran very slowly, but looked very well behaved, highly detailed. I forget if that was IGBT, SiC MOS or which, but probably both.I don't know that anyone has an accurate model of SJ MOS yet, including the snappy behavior and effective dielectric losses. To be fair, the snappy behavior is just a disaster to simulate, better left alone, but the losses are relevant. Maybe not too relevant anyway, just because simulating switching losses accurately is a pain itself.Of course there's also the BSIM level-whatever models that fabs use, that are highly detailed and accurate, and representative of actual fab devices-- but I have yet to touch those, they're closely held secrets. It's bad enough that encrypted models are so pervasive these days (HSPICE, now LTSpice, probably others too), go figure.Tim

author: mawyatt
author_rank: Super Contributor
timestamp: June 13, 2024, 03:02:39 pm
content: The models used in IC design and fabrication are required to be highly representative over a wide range of uses, as one is "betting" an expensive IC design on such.Generally test "breadboards" of circuit sections as often done with discrete designs are not used as they can't do a good job of mimicking the IC design as package parasitics come into play.Also, these models must represent various individual device configurations/parameters such as doping profiles, crystal orientation, length, width, fingers, proximity and layout effects (thru back annotation) which discrete models don't deal with.Best,

author: Doctorandus_P
author_rank: Super Contributor
timestamp: June 13, 2024, 07:40:20 pm
content: Some notes:The root cause of the Miller effect is that the gate-drain capacitance gets multiplied because of the voltage change over the drain node, and I do not really see that in formulas working with gate charges.As soon as the miller plateau ends, the drain - source voltage is low. When the gate voltage gets higher, the drain - source channel resistance get lower. It can be reduced to about 1/3 with a gate voltage or 12V or so. I don't know whether that is significant in your application.To simulate an uC output pin, a 5V "ideal" voltage source combined with a series resistor is a not very good approximation. From what I have seen, a resistor works quite well as approximation until there is around 2V over it. After that the uC just can't source more current and it starts acting as a constant current source. But of course this depends on the exact uC used, and even revisions (die shrinks) This is probably one of the bigger sources of error in your simulation.Simulation is a good way to test a lot of things quickly, and get test theories, but it remains an additional tool. It is no substitute for real life testing. I still use breadboards quite a lot. Putting crystals (for an uC) on a breadboard is a *&^%$#@! but plenty of uC's have breakout boards that fit in a breadboard. For High current connections, I used to use banana plugs just like anyone else, but I switched to using silicone insulated wires, stripped by around 15mm and then the strands soldered together just enough to keep them together, and combine that with Wago 222 (or the smaller rectangular 221 series) or similar. These can handle 30A, are quick to connect and disconnect, and you can re-use them around 200 times before the spring fatigues and the spring pressure gets noticeably low, and that is a good indicator for when to replace them.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 13, 2024, 09:28:31 pm
content: The Miller multiplication is specifically about capacitance -- hence why the plateau is so flat, the incremental capacitance dV/dQ is very large. The total charge however is irrelevant for Miller's theorem -- all that's needed is a linearizable range where the theorem applies. In cutoff and saturation, gm --> 0 and those conditions no longer apply, thus starting and terminating the plateau.Tim

author: Lomax
author_rank: Frequent Contributor
timestamp: June 13, 2024, 10:37:39 pm
content: Thanks for the interesting discussion! I would like to understand the theory well enough that I can calculate the behaviour with some level of confidence, but despite spending many hours digesting some pretty dense (to me) application notes etc, and trying to replicate some of the calculations outlined in them, I don't seem to be making much progress. I still plan to use the BUK9880-55A MOSFET for the actual circuit but decided to work with the IRLL024Z to practice on the calculations, since I've got a working (if crude) SPICE model for it running in ngspice, which gives me the ability to double check my results.I would like to be able to predict the switching losses with reasonable accuracy, and as a baseline I generated a full PWM cycle's worth of samples of the power in the MOSFET at 30 kHz, zeroed all the values outside the switch-on and switch-off regions and averaged the list of 30k+ samples. This gave me 0.034 W, which doesn't seem entirely unreasonable. Then I did the same at 10 kHz and got 0.013 W, which also seems reasonable. To test some different formulas against these baselines I made a spreadsheet with the known values from the datasheet, and the known values from the circuit, and used these values as inputs for three different switching loss formulas - all of which look incomplete to me since they do not take the gate resistance RG(tot)into account, which I know has a profound effect on the switching time and hence the switching losses. I would also expect all of them to rise by a similar amount when increasing the PWM frequency, but as you can see below they're all over the place. And yes, I have double checked the spreadsheet formulas. I'm tired and despondent but still determined to make sense of this - can anyone help?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 14, 2024, 12:55:34 am
content: Hm, something's missing in the top-right calculation 'cuz all three are proportional to Fsw and I don't know which one it was calculated with but if it's similar to "DMC" it should be around 5/15 or 6/18mW or whatever, but it's not changing at all.I_G slipped a multiplier, it should be mA. Also maybe worth noting it's average / DC supply, for clarity.Incidentally, I don't have the part in question but here's a IRF510PbF with 1050Ω gate resistor and 15Ω drain resistor (somewhat inductive at this rate). The capacitance kinda sorta seems two-segmented but it's definitely smoother inbetween than the SPICE model has it.Tim

author: Lomax
author_rank: Frequent Contributor
timestamp: June 14, 2024, 08:17:03 am
content: Quote from: T3sl4co1l on June 14, 2024, 12:55:34 amWell, itischanging, but not enough to show on the three digit (display) precision I'm using. Clearly not right though! I got the formula frompage 3 here- though QGS2is not known, so I'm using (QGS/ 2) as a rough approximation, just to be able to test it.Quote from: T3sl4co1l on June 14, 2024, 12:55:34 amAh, good catch! The units are only cosmetic unfortunately (if someone knows how to make LibreOffice Calc play nice with SI prefixes I would love to hear about it). Instead I multiply the values by the correct powers; you type "10" in the fpwmbox and under the hood it's treated as 10*10^3.Edit:Actually, hang on, IGshouldbe in amps otherwise I have to transpose this as well when I use it. Things like G4*G3*(G8*10^3)*((((D8/2)+D9)*10^-9)/G13) gets old pretty quickly. I agree about the average; How about relabelling it IG(avg)? Seemsa shady valueanyway, since (again) it doesn't take RG(tot)into account?Edit2:I think a possible way forward would be tocalculatethe rise and fall times rather than use the numbers from the datasheet, and use these times with the DMC formula. When changing rise time to 60 ns and fall time to 40 ns (which is what the simulation shows) the DMC formula gives me 0.036 W at 30 kHz and 0.012 W at 10 kHz which is extremely close to my baseline values. These times correspond to t2-t1and t6inthis Vishay application note(p2-3).

author: Lomax
author_rank: Frequent Contributor
timestamp: June 14, 2024, 09:43:20 am
content: I'm trying to get tr~60 ns here, but I get 129 or 27...They do not say where they get VGS, so I can only assume this is my VG(drv). Their Cissis also a little unclear because they never explain how Cgsand Cgdare calculated:I have tried using both Cissfrom the datasheet (380 pF) and the calculated effective capacitance CG(on)from (QGS+ QGD) / Vgp= 1.83 nF. These are obviously wildly different values, but hey ho, I never geteven closeto the observed (in simulation) ~60 ns rise time.Edit:I'm sorry, I had an error in my simulation: the measured rise time should be ~50 ns,not60.Edit2:I've managed to prove (to myself - I'm sure this isobviousto anyone who speaks math) that both of Vishay's methods for calculating trproduce exactly the same result when using the same value for the gate capacitance. The only problem is that using Cissit's about half of what it should be, and using CG(on)it's two and half times too large:Not sure if that qualifies as progress, but it's at least nice to know.Edit3:Maybe I'm calculating the gate capacitance during t2incorrectly; using (QGS+ QGD) / Vgpgives the Miller Plateau (t3) capacitance, which is where the gate capacitance reaches its maximum - but I'm interested in what happensbeforethat, at the threshold voltage. So perhaps QGS/ VGS(th)is more accurate for t2?Edit4:I think that might have been correct; using QGS/ VGS(th)to calculate trand Cissto calculate tfI get a rise time of 71 ns and a fall time of 33 ns, and plugging these into the DMC formula for power loss I get 0.037 W at 30 kHz and 0.012 W at 10 kHz. The power loss rises and falls with the value of the gate resistor by amounts that don't look totally wrong. I'll now try to double check this with additional simulation runs.Edit5:Raising the gate resistor to 200 Ω (RG(tot) = 226 Ω) I get a 10 kHz switching loss of 0.019 W from the simulation, while the formula suggests 0.022 W. At 30 kHz the simulation gives 0.049 W, and the formula 0.067 W. Hmmm.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 14, 2024, 12:14:42 pm
content: Ciss is a small-signal parameter, and not relevant here. It varies: it's a function of operating conditions (and, notice the condition it's measured at in the table). At best, you would integrate its value over the switching edge (\$Q_G = \int C_\text{iss} dV\$), which has the convenient byproduct that Miller effect manifests and all that, but, now you're bringing in enough data (you need the C(Vds) and gm curves) that you're better off doing it in SPICE, and needless to say, a brief closed-form relation is not applicable.Given the tabulated Qg's, and assuming you're running at the same overall V, I as the test condition, you can calculate td/tr/tf from that; but varying Vgs(on), Vds, even Id, requires more effort: extracting Q(Vds) from the C curves, adjusting for transfer function (different Id), etc.Tim

author: Picuino
author_rank: Super Contributor
timestamp: June 14, 2024, 02:09:51 pm
content: The time spent on miller plateau is only a part of the total switching time when inductive loads are present.First the voltage switches at the drain between GND and Vdd (miller plateau). Then the drain current decreases until it becomes zero.The two times are important for calculating the heating of the mosfet by switching.In the first case the power dissipated by the mosfet will be:P = 2 * fc * T1 * Idd * Vdd * 0.5In the second case the power dissipated by the mosfet will be:P = 2 * fc * T2 * Idd * Vdd * 0.5With:fc = Switching frequency .T1 = Time of miller plateau [ s]T2 = Time of complete switch off or switch on (decrease or increase current to Idd) [ s]Idd = Drain current = Inductor current Vdd = Supply voltage. 2 = 2 transitions per cycle. On and Off0.5 = Triangle area formulaeTherefore the switching time must also take into account the time during which the current is reduced to zero or increased to the inductor current (for both on and off switching).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 14, 2024, 03:19:49 pm
content: BTW, note that this is energy, but not actually power. It's power dissipated, when it's current flowing through the channel. You can also have the channel just turn off fast enough, and drain voltage rises on its own. It's energy, but it's not power, it's energystored in Cossand not yet dissipated.This is the trick of ZVS, switch fast enough, and have something magically return Vds to ~0 before the next cycle, and that's it, you've won, efficiency is yours.Which is why gate drive networks often have a speed-up diode, so that turn-off can be fast, and the drain swing is capacitive mediated, and incidentally this also violates Miller's theorem so there's no plateau (but the same charge still must be put into Cdg, it just flows while Vgs = Vgs(off), so it further pays to have a low-impedance driver in the low state).A hard-switched converter, will absorb all that energy (and more) at turn-on, because, say for a buck/boost in CCM, turn-on has to drop the full supply/output voltage, plus commutate the diode (deliver all the recovery/junction charge it has),plus dissipate its stored Coss energy, and that basically makes up for all of it and more. Whereas specifically for a slow-switched resistive load, the switching loss is ~equal (rising/falling), or more specifically proportional to time taken on each edge, and for a resistive load and linear ramp waveforms (constant device capacitances) you get V*I*t/3 rather than /2 because the power pulse is a quadratic spike rather than a triangular one.Because Coss or Cj is dependent, and large at low voltage, the diode capacitance (or recovery, which can be modeled a similar way) in CCM at turn-on is a HUGE factor in overall switching loss. It's got that full supply/output voltage in series with it to the switch, so the switch has topull down from that voltage towards GNDbefore current starts flowing, then ramps up, then finally voltage ramps down. So you get the double-triangular inductive switching waveform, with an excess current peak due to Cj or recovery, and then the voltage ramp.Tim

author: iMo
author_rank: Super Contributor
timestamp: June 14, 2024, 04:35:09 pm
content: FYI - In the LTspice you may get the power plot with integrated numbers over a time period. For example below the power plot of the IRLL024Z during the 300us..ALT+click on the transistor - you will get the power plot of the transistor in the graph, CTRL+click on the formula in the graph you will get averaged/integrated numbers over the simulation duration.

author: Picuino
author_rank: Super Contributor
timestamp: June 14, 2024, 06:24:19 pm
content: It is power dissipated in the transistor by joule effect during switching.Because the current continues to flow through the transistor while the voltage is changing from Vdd to GND. Current times voltage is power.The formula has units of voltage x current x time x frequency.Time and frequency cancel each other to give a dimensionless number that represents the percentage of the time the transistor is in transition switching.The voltage across the transistor times the current in the transistor gives units of power .To this power should be added the power dissipated during the driving phase:P = D * Rdson * Idd ^ 2

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 14, 2024, 06:37:02 pm
content: Quote from: Picuino on June 14, 2024, 06:24:19 pmAre you sure of this?Consider the circuit:Does Q3 dissipate power?If so, how much?(In fact this is a trick question, as the answer turns out to be "yes"; but "how much", requires knowing more about the specified part than the datasheet provides..!)Tim

author: Lomax
author_rank: Frequent Contributor
timestamp: June 15, 2024, 07:37:47 am
content: Quote from: iMo on June 14, 2024, 04:35:09 pmThat's very convenient, thank you! I found the same functions in KiCAD's simulator by right-clicking the parameter in the parameter list on the right:Here the average for t0to the end of t3(i.e. the switch-on period) is shown as 2.435763 W over 133 ns (at 10 kHz with 10% duty).And above is the (slightly faster) switch-off period from start of t4to end of t6, showing an average of 1.875544 W over 109 ns (at 10 kHz with 10% duty).