Quick checking for VHDL syntax - Page 1
Forum section: electronics / general

author: mtwieg
author_rank: Frequent Contributor
timestamp: October 29, 2023, 04:16:39 pm
content: I'm not an FPGA expert, but I'm responsible for maintaining several FPGA designs (mainly for MAX10), using Quartus prime Lite. The number one nuisance I encounter is that when I make substantial changes to a design, finding all the stupid syntax errors takes forever because the Quartus synthesis proceeds until it finds one error, reports the file/line with the error, then stops. It generally only reports one line, even if the same type of error is made numerous times in the same file. So I have to run synthesis many times before I can even get to the more interesting issues.There's one other factor that makes this much worse. My designs on MAX10 always have a remote update (rsu) IP block, along with a flash controller, and Quartus always chooses to synthesize that part of the design first, which takes about 25 seconds. Those parts of the design never change and never have errors, but this means that synthesis always runs for 25-30 seconds before encountering an actual error.1. Put the design in a simulator (modelsim?) which could be much faster than quartus. I would have to build a testbench file containing the top level entity. Not a big deal so long as I'm not making changes to the ports of the top level entity. But what about all the IP entities in the design?2. Somehow get quartus to not build the rsu stuff first. Or not build it at all. Commenting its instances and components out of the design is an option I guess, but quite tedious. Would be great if I could switch it on/off in a more convenient way.3. Incremental compilation. Sounds ideal, but seems like a big can of worms. From what I read, it would probably require a total refactoring of the entire design.Are there any other simple things I could try to get around this issue?

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 30, 2023, 12:33:45 am
content: I use GHDL all the time - not just for simulation, but also exactly for the use case you mention - analyzing the code.With GHDL you don't need any top-level test bench file to only analyze source files. The option to use is '-a'. Pass the "package" files first in the list of files you pass to the ghdl command line (put dependencies first as files are analyzed in the order they appear).For instance, for code compliant with VHDL-2008:Code:ghdl -a --std=08 <xxx.vhd> <yyy.vhd> ...I've been using GHDL for years, it's proven reliable and is still actively maintained. Great team too.

author: betocool
author_rank: Regular Contributor
timestamp: October 30, 2023, 01:03:23 pm
content: You don't need a testbench in Modelsim, which comes with Quartus prime I believe, to run the compilation of your files. Just add the necessary files to your new Simulation Project and off you go. Modelsim even has most of the Intel primitives, so that makes it easy.Same with GHDL, but I'm not sure how to use the Intel proprietary libs.Cheers,Alberto

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 30, 2023, 07:55:28 pm
content: Quote from: betocool on October 30, 2023, 01:03:23 pmAs long as you have access to the definitions (the package files) and these are written in standard VHDL, then GHDL can handle these. You'll just have to find where they are located. It just needs the definitions, not the actual implementation.

author: mtwieg
author_rank: Frequent Contributor
timestamp: November 16, 2023, 02:54:17 pm
content: Hi all thanks for the replies so far.I wasn't aware of GHDL, looks like another good option to check out.Actually I now have a need to simulate some existing code for interfacing to an I2C master. The I2C master interface on the low level is coded in verilog (looks like it came from opencores), and its wrapped in an interface coded in VHDL, and I have to modify the interface (and that must still be VHDL).I tried to run this in EDA playground, but it seems to be ignoring the .v files entirely, and emits this warning:Warning- Unbound componentQuotei2c_inst is the name of the instance of component i2c_master_top, which is defined in verilog. If I manually add the .v files to the compile options, it does attempt to parse them but fails, apparently because it only expects VHDL syntax.From what I can tell, GHDL also doesn't handle verilog, so I guess I'll go back to trying modelsim. It's been many years though, and from what I recall setting it up is a pain...

author: nctnico
author_rank: Super Contributor
timestamp: November 16, 2023, 04:43:39 pm
content: Use a seperate IDE (like Eclipse or VS code) with a VHDL plug-in. Then you get syntax checking as you type or at least when you save the file.

author: mtwieg
author_rank: Frequent Contributor
timestamp: November 19, 2023, 08:52:30 pm
content: I actually do use VScode for editing VHDL, using the TerosHDL extension, mainly to provide basic QoL features like syntax highlighting, find references, rename symbol, etc. TerosHDL documentation suggests it can also facilitate linting and even simulation (via external tools). May be worthwhile, if it supports tools I have access to.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: November 20, 2023, 12:42:57 pm
content: I'm using TerosHDL too and I can launch VUnit directly from it to run my simulations. It works great, and most of the time I don't need the simulator GUI so I can run the simulations directly in the VSCode console and don't need to get out of the editor at all.

author: Scrts
author_rank: Frequent Contributor
timestamp: November 20, 2023, 01:27:46 pm
content: Quote from: betocool on October 30, 2023, 01:03:23 pmSecond this.You hit compile and it tells you if you have problems in your code. You don't have to run simulation at all.