Why NMOS for buck switchers? (other than generally better NMOS specs) - Page 1
Forum section: electronics / projects

author: 741
author_rank: Frequent Contributor
timestamp: August 09, 2019, 01:48:18 pm
content: Just reading up on switchers... Assuming a basic circuit, with a catch-diode and a pass transistor: The buck circuit examples I have seen all use an NMOS with drain @Vdd, and Source tied to the inductor, hence a possible difficulty driving the NMOS gate fully ON for smaller Vin-Vout.I wondered - if I invert the sense of the drive signal, can I use a PMOS, with Source at Vin+, drain tied to inductor? Ominously, I cannot find any examples, must be a catch...maybe to do with impedance of D Vs S?(In my case I'd like a high current, but pretty low voltage difference (say 3v), between Vin and Vout, hence (for the NMOS solution) I'd need to find an NMOS with low Vto)

author: Kleinstein
author_rank: Super Contributor
timestamp: August 09, 2019, 01:53:31 pm
content: One could use a P_MOSFET, but as already written, PMOS performance is not as good.One a chip it is often cheaper to use NMOS and bootstrapped gate drive. It usually requites 1-2 external caps. This also gives better performance.

author: 741
author_rank: Frequent Contributor
timestamp: August 09, 2019, 02:03:43 pm
content: Many thanks for your explanation - my mind is "easier" now.It seems to work OK in LTSpice.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 09, 2019, 02:30:07 pm
content: They're out there:https://www.ti.com/lit/ds/symlink/tps40200-q1.pdfPerformance is king. The difference is not small -- PMOS is about 2.5x worse than NMOS. More die area = bigger package and more cost (with knock-on costs from lower production quantities -- i.e., PMOS in general are less common, and cost more as a result). Poorer Qg*Rds(on) figure of merit = generally higher switching losses, and either higher conduction losses or higher drive losses (drive power is Qg * Vgs(on) * Fsw).You need a driver anyway -- the gate has generous capacitance in either type, so a mere logic-level output is unsuitable for all but the smallest transistors -- and it's not much added die area (if integrated) or cost (if discrete*) to include the bootstrap driver for NMOS. So it's very practical to use NMOS in high or low side application.* "RTL" level discrete that is, i.e., using ICs for basic functions. Low side, logic-input drivers are cheap and plentiful (TC4427, etc.), as are bootstrap drivers (IR2110, etc.). If you're doing something truly discrete (bare transistors), it's harder -- a high-voltage, noise-immune level shifter is certainly doable, but it will take more transistors than the alternative (comparethis(first page, top and left half) tothis, for example).Tim

author: 741
author_rank: Frequent Contributor
timestamp: August 11, 2019, 01:14:42 pm
content: Hi Tim"Gate_Driver.png" reminded me of something I saw in a textbook ("circuits for electronic instrumentation", T H O'Dell, p103).For added drive on fast edges, the top-left transistor had an emitter decoupling capacitor, also both bases of left-side transistors were tied via a capacitor.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 11, 2019, 01:52:19 pm
content: Yup; you would need a resistor in series with the diodes (probably replace one diode with a resistor of equivalent voltage drop) to allow some "emphasis" to be coupled through a capacitor. A downside of this connection is, significant supply ripple (more than a modest fraction of Vbe, say) is coupled from the high side to the low side, through the capacitor, potentially causing erratic operation and shoot-through. So you need to use good bypassing, and to separate or shield the supply from induced fields (fields can be quite intense in a big inverter circuit).Tim