there was DDR, now DDR3 when will we meet marketing BS limit ? - Page 1
Forum section: electronics / general

author: Simon
author_rank: Unknown
timestamp: January 27, 2012, 06:39:03 pm
content: In the good old days we had "standard" SDRAM PCwhatever, it ran at a certain speed and in theory would move data in and out at a certain speed based on it's working frequency. And guess what ? it did just that with an effective real speed at no less than 90%Then DDR came along and we thought it was great, we instantly double our data speeds admittedly with some increase in latency (amount of clock cycle that the memory spends "thinking" about accessing the data), When I tested my DDR systems I found an efficiency of 70-80%, ok not bad,Then came DDR2 technology with escalating latency timings the speed double once again taking it to 4 times the raw speed. But by now we are looking at 50-60% bandwidth efficiency.Now DDR3 has cum ! with further clock latency increases and as I've not used any DDR3 ram yet I don't know any real life bandwidth inefficiencies but I would not be surprised if it was at something like 30-40% efficient.So have we really made any progress ? or it is just marketing wankery ? Now I know that DDR3 came to us from video card memory technology but these are specialist computing systems that probably have more control over how the ram is used and use it properly. Does DDR3 really give any speed advantage ?I dread the arrival of DDR4

author: westfw
author_rank: Super Contributor
timestamp: January 27, 2012, 07:12:08 pm
content: What are you counting as "bandwidth efficiency" ?For most apps these days, you end up filling a cache line (or "something") in some sort of burst mode, so absolute bandwidth remains pretty important regardless of latency...Standards have been "weak" and short-lived since they started putting RAM on modules. I know because we always picked the wrong one. I have large numbers of standard DIMMs culled from the dumpster that aren't useful for much of anything other than the product they were pulled from :-(

author: Simon
author_rank: Unknown
timestamp: January 27, 2012, 07:17:23 pm
content: I've usually run sisoft sandra which is quite a good diagnostics program. Efficiency's (real speeds measured) have varied between brands, I've seen an SDRAM system at 30% and it showed, that was a bad system and gave me nothing but trouble (Trying to upgrade the processor would not work.... it just messed the whole system up).On the whole though the efficiency has dropped at each new DDR "level" as far as i can see. From the little I understand the data you want on a DDR system has to all be in associated addresses, so if you want data from two non associated addresses you cannot access both in the same cycle and so you have a "drop", I read this about DDR which explained the slight real bandwidth drop. If you upscale that through the newer DDR methods surely it gets worse and worse ? at some point it just won't be gaining anything surely ?

author: olsenn
author_rank: Frequent Contributor
timestamp: January 27, 2012, 07:36:45 pm
content: Nobody cares about efficiency; it's only real world speeds that affect us... if it's faster and of deeper storage at a lower size/price, then it's better.

author: Simon
author_rank: Unknown
timestamp: January 27, 2012, 07:48:44 pm
content: by efficiency i mean the REAL data transfer rate versus the so called theoretical speed.The theoretical data speed is MHz * 8, if the system (chipset + RAM) cannot achieve this amount of data transfer it will be less than 100% efficient in sandra's memory speed test

author: Simon
author_rank: Unknown
timestamp: January 27, 2012, 07:50:25 pm
content: I tested my dads PC the other day, the data transfer rate is 48% of the theoretical speed (but then it is a piece of shit of a motherboard made by asus)

author: ejeffrey
author_rank: Super Contributor
timestamp: January 27, 2012, 08:13:19 pm
content: Efficiency as you have defined it is a worthless metric for comparing different systems. What matters are latency, burst transfer rate, and sustained throughput. What fraction of bus cycles are carrying data is an implementation detail that only matters to designers trying to hit certain performance goals at a price.Now, efficiency is perhaps useful for tweakers to know how some change affects their system -- but this is simply because in that case, higher efficiency is directly related to higher bandwidth.

author: grumpydoc
author_rank: Super Contributor
timestamp: January 27, 2012, 08:13:57 pm
content: Actually if you look at the DDR history command latency has more-or-less stayed the same (for each increment the number of clocks for a command has doubled, more-or-less) but data transfer rates have increased - OK this does lower the "efficiency" but overall performance is increased.

author: Simon
author_rank: Unknown
timestamp: January 27, 2012, 08:17:59 pm
content: well my tests over the years have been to establish how fast data can be moved to/from the ram, If I have a module that runs at 800 MHz DDR2 but is 50% efficient (actually moves data at half the speed it could/should) I might as well have a 533 MHz DDR module that has say a 80% efficiency, the so called increase in speed may not exist.Yes efficiency tests are best used to compare tests on the same system, you could increase your ram clock but have to see an increase in latency which is the speed increase is modest may not gain me much

author: grumpydoc
author_rank: Super Contributor
timestamp: January 27, 2012, 08:41:47 pm
content: QuoteThe RAM is shifting data as fast as it can.There are two activities - getting the RAM into a state where you can read a sequential block of data and shifting that data onto the bus. The former isn't getting faster as fast as the latter.The latency only goes up in clock cycles - in nano-seconds it's all about the same. Admittedly as the RAM spends comparatively more time in the set-up phase then "efficiency" does drop but as I said before overall performance does increase as you go from DDR to DDR2 and then DDR3.

author: Simon
author_rank: Unknown
timestamp: January 27, 2012, 09:25:09 pm
content: I see, i remember reading something about the controller having to "predict" where to put data so that the data that you want is all in addresses that will be addressed together. My point being that you have to address a certain set of addresses at a time, so unless the data you want is all in those addresses you may find yourself addressing addresses that don't all contain the data you want, so you might end up making two transactions instead of one.I have little knowledge of how the various types of DDR's work, i guess it is time to go look at wikipedia

author: grumpydoc
author_rank: Super Contributor
timestamp: January 27, 2012, 10:05:13 pm
content: Well, you're right in that it is possible to write programs such that data access is such that the caches are used inefficiently. Such code usually has abysmal performance and finding and fixing that sort of thing can yield huge improvements.But on the whole the system works because most of the time after reading the data at address 400 the systemwillread 401, then 402 and so on.

author: Simon
author_rank: Unknown
timestamp: January 27, 2012, 10:51:09 pm
content: hm wikipedia does not explain anything about how the different rams work electrically (or the lack of diagrams makes it hard to follow), does anyone know of a good article explaining DDR ?I am still under the impression that the higher the level of DDR you achieve the more risk there is of inefficiency, wikipedia talks about cache depth, I guess this is about preloading/prefetching data that may not be needed due to a program branch requiring a reload of the line, the longer that line is made the longer it takes to reload the data, as intel found out when they artificially boosted their CPU performance with long pipelines that needed emptying and reloading every time a program branched, where as AMD came up with more "efficient" solutions.

author: Rerouter
author_rank: Super Contributor
timestamp: January 27, 2012, 10:52:03 pm
content: mate, i hope in yor comparison you accounted for timings vs. clock, being that are what directly impact upon your latency,if you have a DDR-400 chip running at 2-2-2-5, it only at a fiscal value is fair if weighed against a DDR2-800 chip at 4-4-4-10 as it cancels out the apparent latency (takes twice the cycles, but is done at twice the clock speed)also efficiency is generally a relative measure of the cpu front side bus speed to the ram speed, (i am an intel user so pardon my one sidedness) so say you have a cpu with a bus speed of 800, then ddr2-800 would deal a greater efficiency then using DDR2-533,and again, there are factors that will impact on efficiency in various northbridge revisions, and the ram controllers themselves, and i havent even spoken of the extended latencies yet, there are about 15 latency factors

author: grumpydoc
author_rank: Super Contributor
timestamp: January 27, 2012, 11:16:26 pm
content: Quotehttp://en.wikipedia.org/wiki/Dynamic_random-access_memoryhas a reasonable explanation.QuoteYes, but.....Typical set-up latencies are 10-15ns, after that you can read 8x64 bit words in 5ns (for DDR3-1600).That gives (approx) 10.6ns for one word or 15ns for 8 words - you might as well read the 8 - you win if you need just one more of those words before it gets pushed out of cache.You are right - sometimes data will be fetched that isn't needed and sometimes data will be needed that hasn't been fetched, but on average you hit much more than you miss and strategies such as branch prediction help a great deal to improve the hit rate.

author: Wartex
author_rank: Frequent Contributor
timestamp: January 27, 2012, 11:19:34 pm
content: Quote from: Simon on January 27, 2012, 07:48:44 pmTalking out your ass I see. Where did you get that bus width is 8 bit? Where did you get that you get a byte/word/dword per clock cycle? Are you aware that there is GDDR5 out and for a while now? Modern RAM uses multiple lanes and can combine interfaces.The way you calculate max theoretical output is FREQ * Channels * BusWidth * Bits/Cycle, but latencies and bufferization comes into play as well.New motherboards don't have a RAM controller any more, it's in the CPU now.http://en.wikipedia.org/wiki/Memory_bandwidthWith higher speeds we are hitting some material limitations as well as propagation delays and synchronization issues.

author: Psi
author_rank: Super Contributor
timestamp: January 28, 2012, 12:20:20 am
content: Quote from: Simon on January 27, 2012, 07:50:25 pm?asus make some of the best motherboards.And even their cheap range are good value for money.I always buy asus motherboards for myself and others and i've never had an issue.

author: joelby
author_rank: Frequent Contributor
timestamp: January 28, 2012, 06:36:18 am
content: Quote from: Simon on January 27, 2012, 07:48:44 pmAnd don't forget that you get two data bits per cycle - the clue is in the 'double' part of 'double data rate'. DDR3 DIMMs are 64-bit devices, though individual memory chips can be x4, x8 or x16.There are some other hints about the differences athttp://en.wikipedia.org/wiki/DDR2_SDRAMandhttp://en.wikipedia.org/wiki/DDR3_SDRAM.I'm not quite sure what the point of this rant about something you don't seem to know much about is. Advancing DDR standards aren't driven by marketing - they are electrically incompatible standards set by JEDEC. Newer fabrication technologies and ever higher speeds tend to mean that operating voltages are reduced - note the differences between DDR (2.5 V), DDR2 (1.8 V) and DDR3 (1.5 V).Higher latencies are compensated for by caching, though poor programming can render caches ineffective.

author: Simon
author_rank: Unknown
timestamp: January 28, 2012, 08:24:32 am
content: Quote from: Wartex on January 27, 2012, 11:19:34 pmnot really a 64 bit wide bus transfers 8 bytes at a time (64/8 ?) if you read wikipedia similar formulas are shown, I'm green on the nitty gritty of how stuff works (as I have no need to know but am now curious) but not that green thanks !As for GDDR5 that is probably for video ram where as I said before maybe things are more predictable as opposed to the general computing environment. I did say earlier that I remember DDR3 being said to come from video card technology (Infact my video card that is coming in the post has this now apparently obsolete ram)

author: Simon
author_rank: Unknown
timestamp: January 28, 2012, 08:27:39 am
content: Quote from: joelby on January 28, 2012, 06:36:18 amYes I'm no expert, but as i said as I've benchmarked my systems over the years I've seen a drop in efficiency over each new DDR technology, so are those figure meaningless ? The MHz in my formula was simplified by MHz I intended the apparent speed of the module

author: Simon
author_rank: Unknown
timestamp: January 28, 2012, 08:30:07 am
content: Quote from: Rerouter on January 27, 2012, 10:52:03 pmso in effect latency never goes down, at what point will having huge transfer speeds start to be meaningless against the "setup time" perhaps this is where i see "efficiency drops" ?. Is the latency the time it takes the memory chips to deliver the data or does it include the time to move the data through the cache ?

author: slateraptor
author_rank: Frequent Contributor
timestamp: January 28, 2012, 08:47:20 am
content: With as much variance in architecture and abstraction levels, I can't imagine any faith being placed in the absolute measurements of any benchmark software.

author: grumpydoc
author_rank: Super Contributor
timestamp: January 28, 2012, 09:27:56 am
content: QuoteYou seem to be focusing on "efficiency" - it's not really that important. Latency and throughput are important. Latency is mitigated by caching so really what matters is throughput.QuoteYes it does but more slowly than data transfer speeds go up.Very roughly** SDRAM has CAS latencies of 20-25ns, DDR around 15ns, DDR2 maybe 12ns, DDR3 mostly 10ns or under.In that time-frame the "burst" speed has gone from 100MHz with one transfer per clock to 800MHz (and up) with two transfers per clock, so in the time that latencies have halved burst data transfer rates have gone up 16-fold.In fact efficiency has gone up as DRAM set-up times have become amortised over more reads. Classic DRAM (4164 type stuff) makes you do RAS + CAS for every cycle and is very inefficient if you look at what percentage of the whole read cycle the data is present and stable on the bus (maybe 20ns out of a cycle of 250ns), FP DRAM lets you do one RAS, then read multiple columns in the same row thus spreading the cost of the CAS over multiple reads. SDRAM lets you do one CAS+RAS and then auto-increments the address letting you spread the cost of address set-up even further.DDR does then apparently does then apparently decrease bus efficiency by squeezing the time for data transfer - but the throughput goes up significantly. But this "efficiency loss" is not really all that important.**Trying not to upset proper experts- I'm just a software engineer who likes to know how the hardware ticks but the last time I had to get really down & dirty with instruction cycle times and memory access times was on an an 8-bit micro > 20 years ago.

author: ejeffrey
author_rank: Super Contributor
timestamp: January 28, 2012, 09:35:14 am
content: Quote from: Wartex on January 27, 2012, 11:19:34 pm8 bytes. Standard DDR{1,2,3} DIMM modules all use 64 bit (8 byte) data paths to the mainboard. The MHz rating of DIMMs is the transfer rate, not the clock. For a single memory controller his formula is correct, at least when talking about main memory on consumer PCs. You are correct that with a multi-channel controller (as most DDR3 systems have) that is populated properly you have to multiply by the channel count to get the total system bandwidth.