single clock radio - Page 1
Forum section: electronics / projects

author: rakeshm55
author_rank: Regular Contributor
timestamp: August 27, 2018, 04:06:39 am
content: Hi,Is there any advantage in using a single clock for entire operation of digital radio(SDR type)?? The advantage is supposed to be for RF performance.Processor clock,FPGA clock, Ethernet PHY clock, RF ADC clock ,IF transceiver clock all derived from single clock source. Does this offer improvement in RF performance ?? All clocks derived from a 10MHz low ppm stable clock.I could not understand the significance of such a design.I was under the notion of using separate crystals for digital sections. If there is any disadvantage for many crystals in a single board (5 Including RTC).... also high vibration becoz radio may be vehicle mounted ??

author: JS
author_rank: Frequent Contributor
timestamp: August 27, 2018, 04:23:11 am
content: Having an FPGA you can use the internal PLL to generate many without the need of external sources. µC also have internal PLLs so you are likely to need just one for it. Having them all in sync is a nice thing, easier to find noise sources. Interaction between different clocks that goes in and out of sync is hard to troubleshoot, if you have multiple low PPM sources you might have noises that appear every once in a while or some strange problems.RTC can run on a separate clock and probably should, as it needs a different, lower freq, lower power source to run while the system is sleeping and you don't want to generate that from a higher freq crystal not to say the FPGA. Also is less likely to have problems with other clocks as is a low power, not generating much noise and low sensitivity, not being affected much by noise, than the other electronics around, like the ADC where you want everything in sync with to reduce noise, many times even the SMPS is in sync with the ADC, and that's why some controllers have the ability to be driven by an external clock.JS

author: rakeshm55
author_rank: Regular Contributor
timestamp: August 28, 2018, 04:27:23 am
content: I have searched in web but unable to find any literature on this other thanhttp://www.newelectronics.co.uk/electronics-technology/when-it-comes-to-designing-a-clock-tree-what-do-you-need-to-take-into-account/72434/My design has a transceiver PCB, a Data converter PCB(ADC,DAC) and a baseband digital PCB(FPGA,processor).....Transceiver has a 10MHz TCXO , 10MHz comes to Data converters clock synthesizer and generates ADC clocks...Power to all boards generated from baseband board...battery power transferred via baseband board to transceiver.....Baseband has Processor , PHYs and FPGA....Having a separate clock tree for Baseband will it couple noise to radio input/output??

author: Howardlong
author_rank: Super Contributor
timestamp: August 28, 2018, 11:06:28 am
content: There is some technical benefit to deriving ADC and DAC clock sampling and the RF chain from the same clock, not least when in the R&D phase as it's much easier to create completely reproducible test scenarios as there is innate coherence.For the Ethernet phy there's no need, because everything's stuck in a buffer somewhere, although it might well save on a crystal or canned oscillator if you're already using some sort of clock distribution device which may well have spare capacity.It's also not unusual to dynamically alter the operating frequency of switch mode power supplies in SDRs to mitigate against interference.One problem in larger designs might be that distributing clocks over longer distances inevitably leads to increased interference for receivers in particular.My own preference is to start off with a single clock reference unless there's a particular reason not to.