Struggling to grasp freedback->dutycycle technique. - Page 1
Forum section: electronics / beginners

author: Unknown
author_rank: Unknown
timestamp: October 13, 2014, 12:33:58 pm
content: I've been trying to figure out and comprehend SMPS designs. I get the basic principle of the triangle wave compared to a reference to control the duty cycle of a pwm signal, but the part I'm struggling with is, that reference is not in any way related to the reference used to set the required output voltage. If the supply voltage changes for example, the duty cycle will need to increase in order to achieve the correct output, but any error amp in line will still be presented with exactly the same inputs, so I don't see how the output of the error amp could be used to get the correct duty cycle. The error amp is going to be trying to make the reference and the feedback signal equal, so when they ARE actually equal, the output of the error amp is going to be the same as the reference anyway. Most designs I've researched also seem to be flawed in that a high frequency chatter could occur on the PWM on phase if the output is fluctuating enough (maybe due to ESR degradation of the output cap). Indeed I've even modeled some SMPS ICs in spice using the macromodels for the ICs and they do indeed cause chatter on the PWM on phase.I watched one of Dave's videos on SMPS design and he started by explaining a linear regulator first. So I did that, and came up with my own basic linear regulator using an op-amp and a pnp transistor. (top circuit of image). It seems simple enough, the op-amp is configured for positive feedback so that the base current to the pnp decreases as the vout falls below the reference, turning the pnp on more and vice versa. So I tried applying that principle to a basic SMPS design (bottom circuit of image). Now that circuit is just an abstract for illustration, just to be clear there. I'm not really using an or gate and a not gate like that, those two gates represent a boosting synchronous fet driver. So, my thought was, the output feeds back to the opamp, which is configured pretty much the same way as in the linear regulator, controlling the base current to a pnp based on the difference of the vout and the reference in order to automatically home in on the correct duty cycle. But the problem is that a change in duty cycle takes much longer to be apparent on the output than on a linear regulator, as a result the opamp is just going to pretty much be working as a comparator and I'll end up turning the pnp fully on and fully off at a secondary frequency defined by the output stage's response times. I think I need to use a very very slow response opamp or somehow slow down the opamp, this is where I'm hitting a blank. I've seen illustrations for error amp applications that use a resistor and a cap in parallel feeding back from the output to the input, I assume this is done to slow it down? But I can't quite figure out how.Many thanks for any help.

author: David Hess
author_rank: Super Contributor
timestamp: October 13, 2014, 01:13:23 pm
content: The differential error amplifier's inputs in the ideal case are always equal but in reality, the gain of the error amplifier is finite so there *is* a real difference in the inputs as the output changes despite negative feedback. Usually the open loop gain is so high that the difference in the inputs is insignificant. Often it is difficult to even measure; a 4 or 5 digit voltmeter may not even show it on its most sensitive range.I think the chatter you are referring to is a large signal effect which is distinct from small signal effects where the amplifier is in balance. This is the difference between slew rate and gain-bandwidth.

author: Unknown
author_rank: Unknown
timestamp: October 13, 2014, 02:22:36 pm
content: The best I've so far been able to do is to take the junction of the fets rather than the VOUT as the source of the feedback and pass that through a small low pass filter, not enough to completely smooth it out, but to get a noisy wave around the mean output the current PWM is producing. Then I compare that wave against the reference voltage and output when the wave falls below the reference. The output then passes through another low pass filter which averages it out to the duty cycle reference. This approach seems to work. I just cannot figure out the error amp approach at all.http://i59.tinypic.com/2z69kkm.jpg

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 13, 2014, 03:21:41 pm
content: Quote from: Boltar on October 13, 2014, 12:33:58 pmNo! You are thinking like an amplifier! Do not think like an amplifier, think like an integrator!Do not let people tell you op-amps are amplifiers with "semi-infinite" gain, this is a terrible way of looking at things.A common, dominant-pole compensated op-amp is best thought of as an integrator with limited DC gain. (Isn't this the same? Yes -- but not the way of thinking, not the approach!)Then you will see, even if the inputs are exactly equal, the output can still be any value from -V to +V. The integral of an input is its antiderivative PLUS A CONSTANT, and that constant is the DC output value you're missing. In other words, even though the inputs remain very nearly equal at all times, the output is free to gradually drift around to any value. This is what makes feedback so great: you don't need to know what voltage to put into the PWM modulator, it finds out for itself.It's also important to always have, on the top of your mind, the concept that an amplifier's output does not change instantaneously (the infinite gain amplifier lie is, in fact, a terrible idea anyway, as no circuit would ever be stable!). And, in fact, this is of critical importance when controlling another circuit which has finite bandwidth or response time!QuoteWhat do you mean "chatter"? Do you mean ripple at the switching frequency, or do you mean subharmonic oscillations?If ripple is the case, then that's rarely an issue, because it's coherent with the PWM reference and only causes a distortion and offset in the transfer function (i.e., the VIN vs. PWM% out). As long as this doesn't cause spooky nonlinear (hysteresis?) or time-dependent things, it's fine.There are cases where it's a problem: the "average current mode" control loop can suffer from period doubling (1/2 subharmonic, or in chaos terms, just edging onto a limit cycle) under certain conditions, usually at the margins of pulse width (where ripple is high and phase shift is unlucky). Still, this isn't a huge problem, and can be ignored for the most part.QuoteYes, this is correct, at DC.Note that, if implemented using a general purpose op-amp, it is an oscillator.You can determine this based on a simple assumption: the op-amp is designed to be unity-gain stable with some margin, usually maybe 60 degrees or a gain factor of 2-3. However, Q1 has a gain of about 20 in this configuration, so the feedback reaching the op-amp will be 7-10 times too strong. Assuming truly static DC levels initially (such as you'd get in a simulator), the oscillation should begin around 1/10th the op-amp's GBW. As amplitude rises and the output waveform distorts into a somewhat rounded square wave, the frequency will rise somewhat. So, for an LM358, it should end up in the low 100s of kHz.The simplest way to address this is a capacitor from -in to out, across the op-amp (of course, you need some series resistance to -in for this to do anything). This effectively reduces the op-amp's integrator constant, reducing loop gain. Roughly speaking, the RC time constant corresponds to the frequency you want unity gain to occur at. In this example, probably 20 times lower than amp GBW would be safe (or again for an LM358, maybe 150kHz -- not a slouch, but a far sight slower than it was).The best simple way to compensate is with an R+C across the amp. This has the same dominant-pole action as the integrator, except it "lets up" at higher frequencies (in technical jargon, a pole-zero compensator), which gives more phase margin. You want that 'let up' to occur at pretty low gain (too much gain and it oscillates again anyway), so the R is usually a similar value to the series -in resistor. The value of C is found in much the same way as before.QuoteThat's perfectly fine, a representative schematic keeps things simple!QuoteYes, all the above analysis remains perfectly relevant, because you've just put more stuff around the same circuit -- but you've made things a thousand times worse, because now there's an LC filter in the loop. And that means all signals above 1 / (2*pi*sqrt(6.8uH * 100uF)) ~= 6.1kHz are phase shifted pretty much 180 degrees, period -- you have NO phase margin for ANY frequency above the cutoff frequency. Which means, if something bad happens at the output (a short circuit?), your error amplifier necessarily must respond several times slower than that -- fractional milliseconds! When transistors die in microseconds, this isn't looking good.In technical jargon, the LC filter is a two pole filter, which may be real or complex, depending on the value of Rload (with the values as shown, it's complex, meaning a step change in PWM (not that the error amp will ever necessarily behave that way) will take a few milliseconds to ring down). You get a pole and a zero with the "RC" compensator (also called "type 2"), so your total loop has three poles and one zero. You can strategically position the zero near one of the filter poles, but you can't, in general, cancel either one out, because it's a single (real) zero, not a complex pair (now, if you could put an LC in the feedback network, you can do that..). So you're still stuck with a two pole loop, which means 180 degrees of phase shift after that second pole, which means, you still need unity gain to fall below the higher pole. Or somewhere in the kHz range.If you have real components, the capacitor for instance having ESR, this introduces another zero into the loop, which at least helps stability; with judicious choice, it can even lend enough stability to crank the bandwidth back up. Downside? All that ESR lets a hell of a lot of ripple through, and if this is a power application, it gets hot! And still other considerations, like drift and manufacturability: if you use aluminum electrolytic capacitors, that ESR has something like a +400/-50% tolerance over the rated temperature and age of the part. It's not easy making a control loop that's both peppy AND tolerant of such sloppy loads. And obviously enough -- for a general purpose power supply, Rload is unknown, so it doesn't give you any help.So, sounds pretty shitty, right? Doing anything at all sounds like a pain (dominant pole / integrator action goes slow for any amount of feedback gain), and there's ways around that (pole-zero or other compensation), but throw in some L and C and things just get awful! But surely there must be some way around that? Naturally, there is!Tim

author: David Hess
author_rank: Super Contributor
timestamp: October 13, 2014, 03:32:24 pm
content: I should have taken a close look at your schematics instead of just reading your questions.Q1 and Q2 as shown are a problem. They add voltage gain within the feedback loop and even worse, this gain depends on operating point. This will lead to difficulty in frequency compensating operational amplifiers IC1 or IC2. Without this oscillation is likely.Typical solutions include not using the transistor for voltage gain or adding local feedback around the transistor to make it operate with a more controlled gain. Even doing this will still likely require frequency compensation as covered by T3sl4co1l above. Some designs get away without it because the operational amplifier is slow enough to start with.

author: Unknown
author_rank: Unknown
timestamp: October 13, 2014, 03:57:40 pm
content: Seeing as I understood not one word of all that, I think I'm way out of my depth.With regard to a short circuit. I didn't model the current monitoring in there, the diagram is just an abstract for trying to understand how to get this integrator to work correctly. I'm basically talking fundamental understanding I'm trying to grasp. I can of course use a dedicated SMPS controller, there are several around but they all have a drawback. All of them use a resistor divider on the VOUT to match a constant reference voltage. This means to adjust the output I have to adjust the resistance of the lower resistor in that divider. That's not what I want to do, I need to adjust the output voltage by supplying a reference voltage. Since there seems to be no SMPS chip with that capability, I'm trying to understand how to make one.I think I'll have to use an SMPS controller with a fixed divider and bias the voltage at the feedback pin with an external voltage through a resistor.Just as an example, I loaded the macromodel for some all in one step down controller in LTSpice and added another voltage source and a resistor. By varying V2 from 0 to 5V I can change the output between 1.8V and 9.3V. Is this a valid solution? Because if so it will simplify my life considerably.(Note this isn't necessarily the chip I will use, I just wanted to test the principle)

author: Unknown
author_rank: Unknown
timestamp: October 13, 2014, 10:59:15 pm
content: After a bit more reading and attempting to comprehend the error-amp stage by trying to decode what Tim told me, I still have a very limited grasp on the thing. Even trying to figure out what goddam part to use for the error amp is a nightmare. I came across a few demo circuits using a Google image search in which one guy had a single cap between the output and the -IN instead of a resistor. Well, being the "try anything" type, I tried it. And well damn, it worked!!!Still have no clue how or why it does, or if it even will IRL.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 14, 2014, 03:49:11 am
content: What level of math or school do you have, anyway?Control systems theory lies in the land of differential equations. You don't have to know how to solve DEs to use established formulas, but if you struggle with (or haven't even had) calculus and algebra, you're probably missing a lot of the timey-slopey-changey math that is a bare minimum for understanding this sort of thing.Tim

author: Unknown
author_rank: Unknown
timestamp: October 14, 2014, 11:44:56 am
content: I can cope with alegbra but not calculus. Imaginary/Complex numbers? forget it, I never understood those. Ohm's Law I can deal with, but it's when things get "yes but" and "well kind of" I have a problem. I'm a very black and white literal type of person, so when stuff borders into that area I start to get very frustrated. Being a computer programmer before this I'm used to systems that have absolute and definable outcomes. It's just that everything in this game has so so many different niggles and quirks to cope with. There's so much jargon and acronyms and stuff that as a beginner I'm not going to understand and have to try to research. I'm not being funny here, I do seriously appreciate the help you give me. Just how much of the long post above you made do you think an absolute beginner like me is going to understand? Your post equates to hours of research on my part, but then again, I have to do that in order to understand it I guess. There's no shortcuts with regard to that kind of thing.I guess my mistake was to start out by doing such a complicated project that requires that level of knowledge. I do pick things up, but I can't do it instantly at my age, it takes time to sink in. The cap in the above circuit for example. I believe its function is to slow down the opamp. I can kind of see why it does that but the mechanism is still somewhat fuzzy to me. If I put series resistance with that then it messes up the output voltage (it doesn't match what it's supposed to be with regard to Hs, Rfb and VREFIn my limited brain, I'm seeing this. Take the system from stable, VOUT is matching VREF with respect to Hs and Rfb, the cap has charged to the PD between the opamp output and -IN. IF the VOUT changes, the cap holds the voltage at -IN so it doesn't change instantly but begins to ramp slowing it down, this gives the output stage time to react? From startup however things are more sensitive, if the values of the detection network components are out, the output cannot stabalize quickly enough and you get an oscillation. For a fixed output and load this just requires tuning of the components to mid tolerance ranges, for variable output and load it gets very tricky. I need to get used to the formulas for timing and cap charge/discharge and so forth instead of just typing random values into simulators until something works.At least I think I've grasped the error-amp/integrator thing. I always looked at opamps as simple negative feedback amplifiers, their ability to automatically adjust themselves in different configurations almost seems magical. But thinking about it I guess it is just the same as an amplifier, the op amp is just trying to make the inputs equal by increasing the output if the -IN is lower than the +IN and reducing the output if the -IN is higher than the +IN. Whatever it outputs is whatever it needs to output to achieve it? Once that sinks in, the realization of the possible applications of such a device are indeed immense.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 14, 2014, 01:49:49 pm
content: If you know computers, maybe a computational analogy would help: do you know anything about DSP?Even if you don't, you can imagine some things already:Suppose you suck in all the circuit voltages with ADCs, so they show up as dimensionless, bounded numbers. Like, a 12 bit integer. Very average range ADC/DAC stuff. And whatever you've computed, goes into a DAC to make a voltage again. Same idea.Now, if you take a number and multiply it, that's gain, of course. It also needs to be clamped (saturating arithmetic) otherwise you get overflow and stuff. This is one point where natural computing (numbers wrap around) and analog (amplifiers saturate) don't connect so well. So, sometimes you end up with a little extra logic is all (if (x*3 > MAXVAL) {x = MAXVAL};).Suppose you have some stuff in the loop, which is kind of slow. If you crank up the gain, sooner or later, you'll be producing so much change at the output for so little at the input that it diverges and starts oscillating! This is equivalent to the infinite gain amplifier case: it's useless because it's never stable in a real circuit!Suppose you take a static variable and, for each sample period, you add a new sample onto it. So it accumulates. It's the sampled equivalent of an integrator. If you've got some feedbacky stuff between the DAC and ADC (the "plant" you're controlling), sooner or later that integral term is going to come back to you. So if the integral keeps on rising, and that causes the output to rise, and eventually, the feedback difference falls, and the input will trend towards zero difference and zero accumulation, and the integrator stands still at some fixed offset. Just like the amplifier: the inputs are equal (input difference is zero), and the output is... some value, you don't have to know from first principles what it was, it's just, wherever the system settled to.The basic PID (proportional - integral - derivative) controller is pretty easy to implement in software: you do the integral, and this sets the 'wandering' DC level. Then add a proportional term (the input difference times a constant), and if you like, a derivative term as well (you need to keep track of previous differences, and subtract those to get the time dependency, then multiply that by some constant), and that's your output. Repeat once every sample, and you've got a controller.Now, there is a direct transform between DSP stuff and analog stuff -- it's not always easy or exact, but it's absolutely possible, so that should be of some help too.The main downside is, to do what a simple analog loop can do, you need the DSP running at some fraction of the switching frequency, so that it's not terrifically slow (and dangerous). You can play with this using an MCU and stuff, but outside of dsPIC and the like -- with fast A/D inside, you're really just playing with toys. But if that's good enough for getting a grasp on dynamic systems, that's all that you need.Tim

author: Unknown
author_rank: Unknown
timestamp: October 14, 2014, 03:24:45 pm
content: That is kind of how I try to picture things. In a computational zero dimensional way, I just get stuck in the translation a little.Using this analogy, I'll try a simple C# application to step each value. This may be interesting.I just need to get a few basic principles sorted out. I'll use a 1:1 divider for the VOUT for simplicity.VIN = 12VREF = 0.6OUT (duty cycle) = 0-100 percent with 50% being 6V. A change in duty cycle causes a ramp in VOUT to the target which I imagine will not be a straight line but decreasing by a function of the difference each step.-IN = 1:1 divider of VOUT, a change in -IN causes a change in OUT, again as a ramp at a certain speed not sure about the shape of the ramp here.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 14, 2014, 05:02:04 pm
content: Shape of the ramp -- don't use:Code:if ((in_p - in_n) > 0)accumulator++;elseaccumulator--;(plus checks for over/underflow)which is nonlinear, and dumb to compute anyway (why use a slow conditional when better ways exist?), use:Code:accumulator += (in_p - in_n) * INTEGRAL_CONSTANT;which is linear (the change is proportional to input), and doesn't require a conditional (not counting over/underflow).In general, you will always be better off picking the linear option. Many control problems have weird dependencies (if they didn't, they wouldn't need control!), and you want to attack those as best you can to yield a smooth linear loop. Then the loop can be compensated in the conventional manner (by specifying some PID or whatever).Tim

author: FPGAcrazy
author_rank: Contributor
timestamp: October 14, 2014, 05:32:14 pm
content: I have the feeling that you miss some basic inside.I see a SMPS as a system consisting of a number of elements. For now I limit this to a step-down converter.A PWM unit of which the duty cycle can be adjusted by a voltage. In your case the ramp and the input to the comparator.An output filter consisting of a L and C part. This transforms the PWM signal into an average voltage. So for a duty cycle of 50% you will get half the value of the top value of the PWM signal.The system also has a desired voltage, the reference, and the measured output. These are subtracted in the error amplifier. When the system reaches it steady state this output always will be zero.The most important part in this system is the controller which is often implemented as a PI system. Constructed in one of the schematics as U4.The integrator is a very important unit. Its task is to generate the input for the PWM stage U2.How does this circuit work: The integrator accumulates the input signal. So when you apply a constant signal to it, it will slowly ramp up until it is clamped by the power supply of the opamp. However, this integrator sits in a loop, so its output rises when the output voltage is lower than the setpoint. This in turn increases the duty cycle of the PWM generator, which in turn results in a rise of the output voltage of filter stage. This makes the error zero and removes the input of the integrator, which will stay on the last known value. This is necessary because the PWM unit U2 needs a fixed voltage level for a certain duty cycle. The same applies in the other direction when output voltage is lower than the reference voltage.There is a lot more to it. But I tried to explain it as simple as possible.This also explains why you need the integrator. When you remove C in the feedback loop of U2 the state (voltage value) will not hold and the system will not work.Hopes this helps a little.

author: Unknown
author_rank: Unknown
timestamp: October 14, 2014, 05:38:23 pm
content: Right gotcha. The integral constant should also define the speed of the device? so I can have that as a user input for the amp. As for the output stage, that's a bit more complex as the voltage rise and fall will have a degree of inertia.EDIT: No wait, the code you posted would deal with inertia. The accumulator is used each step to adjust the output yes? If so, that's all I need. Nice one.@FPGAcrazy, yes it does thank you. I am slowly getting my head around it. I don't think I'll ever be an engineer, but I'll be happy if I can just build and comprehand the working of such a circuit. I'll get there, I'm a determined fella.

author: Unknown
author_rank: Unknown
timestamp: October 14, 2014, 10:28:04 pm
content: I thought you might be interested in the application I quickly knocked together. I may (probably in fact) have made errors in the logic code though.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 15, 2014, 03:28:01 am
content: Ah neat!Now, if you also add a proportional constant term (input difference times a constant, added to the output term -- added at the very end, not accumulated), and play with that, you should be able to get it to settle.If the ramp is doing what I think it's doing, it will never settle down (notice the numbers continue to hunt around the setpoint) because for exactly that difference of one step, it's too high or too low, and therefore the gain is very high and the loop is unstable. The instability is limited by the amplitude, because the gain becomes much more realistic for more than a few counts difference.A good (cycle-averaged) representation of a modulator and LC filter would be a two pole IIR filter; see:http://www-users.cs.york.ac.uk/~fisher/mkfilter/Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 15, 2014, 03:29:13 am
content: Ah neat!Now, if you also add a proportional constant term (input difference times a constant, added to the output term -- added at the very end, not accumulated), and play with that, you should be able to get it to settle.If the ramp is doing what I think it's doing, it will never settle down (notice the numbers continue to hunt around the setpoint) because for exactly that difference of one step, it's too high or too low, and therefore the gain is very high and the loop is unstable. The instability is limited by the amplitude, because the gain becomes much more realistic for more than a few counts difference.A good (cycle-averaged) representation of a modulator and LC filter would be a two pole IIR filter; see:http://www-users.cs.york.ac.uk/~fisher/mkfilter/Weird, I hit Post and it didn't show up... it's telling me I already posted though...?!Tim