Generation of the NMI signal for  a Z80 - Page 1
Forum section: electronics / projects

author: fabiodl
author_rank: Frequent Contributor
timestamp: July 01, 2020, 01:21:35 am
content: I was looking atthis schematic of the sg-1000and I do not understand the circuit controlling the NMI.When pin 11 of IC13 goes low (IO to the PSG), NMI is the transistor's Vbe + R4/ (R4+R5+R6) = about Vbe, which may trigger NMI. clearly this is not the intended behavior.Is the schematic wrong? or am I wrong? I do not get the intent of the circuitry either. I guess something like not allowing NMI while the psg is enabled? and what about M1?

author: duak
author_rank: Super Contributor
timestamp: July 01, 2020, 10:35:20 pm
content: It would be interesting to see what the code was at 066H, the NMI service routine.The designers may have been exploiting an undocumented feature in the processor. I see that it's an NEC 780C that may or may not be an exact functional copy of the Zliog Z80. Here's a link to some of the undocumented features:https://raine.1emulation.com/archive/dev/z80-documented.pdfbut I don't see anything obviously helpful.I sort of expect that accessing the sound generator with /CS.PSG causes /NMI to be asserted, the PC to be pushed on the stack and the NMI service routine at 066H to be executed.I also sort of expect that pressing the pause key causes the processor to repetitively execute the NMI code and not allow any other code to run. This keeps the sound generator serviced and if any DRAM in the system refreshed.I'll bet the crufty little circuit using a PNP transistor generates a new falling edge for the processor's NMI input logic.

author: fabiodl
author_rank: Frequent Contributor
timestamp: July 01, 2020, 11:27:41 pm
content: The SG-1000 is a console. The nmi is used for pausing the games. There's no BIOS, and 66H routine is different for any game cartridge (which provides the whole ROM).I can say for sure writing to the PSG (i.e. bringing down its CS signal) does not assert NMI, as can be seen by looking at any SG-1000/SC-3000 emulator source code.

author: Andy Watson
author_rank: Super Contributor
timestamp: July 02, 2020, 01:41:04 am
content: How does the pause key operate - is it open for pause, or is it closed?The NMI interupt is negative edge triggered. There must be some mechanism to allow for contact bounce and to prevent re-entry of the NMI code. The Z80 acknowledges an interupt by activating both M1 and IORQ - otherwise these signals do not normally occur together. I suggest that Q1C is somehow detecting this combination and preventing further interupts by holding the NMI line low. However, how much confidence do you have in the accuracy of the schematic? There is definitely a typo with the WAIT signal - it is drawn as being connected to the HALT pin - doesn't make sense. Also, the potential voltage levels on Q1C would give me cause to doubt the orientation of its emitter and collector.

author: duak
author_rank: Super Contributor
timestamp: July 02, 2020, 03:17:57 am
content: Looking at a copy of Zilog's data sheet UM008011-0816, figure 10, I don't see /M1 and /IORQ asserted simultaneously for an NMI response.I agree with the previous post that there are likely more errors in the schematic. If Q1C had its collector and emitter swapped it would be trying to pull /NMI high hence the inclusion of R6 to limit current and act as a load resistor. When /M1 is asserted and then negated, it might vary the voltage on /NMI enough to be detected as a transistion - but I think it would be iffy given these values. I could think of better ways to do this with more conventional designs.BTW, Q1C could be operating in reverse mode where the collector and emitter are swapped. In this mode it will have a very low hFE and Vcesat. I can't think of an advantage here so I suspect it's a typo.

author: bson
author_rank: Unknown
timestamp: July 02, 2020, 03:39:38 am
content: Quote from: fabiodl on July 01, 2020, 11:27:41 pmIt looks more like the purpose is lock out the pause keyunless/CS_PSG is low - in other words the CPU can only be NMI'd by the pause key while the PSG (whatever that is) is addressed.

author: fabiodl
author_rank: Frequent Contributor
timestamp: July 02, 2020, 10:06:43 am
content: Quote from: Andy Watson on July 02, 2020, 01:41:04 amFrom the schematic I believe normally opened, grounded when the button is pressed to pauseQuote from: Andy Watson on July 02, 2020, 01:41:04 amAs much as "I found it on the net".Quote from: Andy Watson on July 02, 2020, 01:41:04 amI completely agree, and it makes sense for it to go to wait.Quote from: Andy Watson on July 02, 2020, 01:41:04 amI completely agree with you

author: fabiodl
author_rank: Frequent Contributor
timestamp: July 02, 2020, 10:11:14 am
content: Quote from: bson on July 02, 2020, 03:39:38 amPSG stands for Programmable Sound GeneratorI agree with you, or, as reported above, E and C are swapped, so CS_PSG low shorts the transistor and disables the pause key operation...

author: bson
author_rank: Unknown
timestamp: July 02, 2020, 05:37:47 pm
content: Quote from: fabiodl on July 02, 2020, 10:11:14 amYou mean it should be a PNP BJT, not an NPN. Just reversing the BJT can't work at all.But it might make sense not to allow pausing while in the middle of writing to the sound generator if that could leave it in a half written state, like if there are multi-byte sequences. The NMI pause code might not know how to handle that, and might not be able to mute the audio.