HOW TO: Programmable Divide-by-N Counters using Standard Logic - Page 1
Forum section: electronics / general

author: Benta
author_rank: Super Contributor
timestamp: August 03, 2020, 10:53:30 pm
content: Designing programmable divide-by-N counters using "off-the-shelf" logic should be easy, right?Well, I found that data sheets don't give a lot of information, and application notes are pretty much non-existent.So I did my own universal design using 74AC161 synchronous counters (74HC, 74LS etc. will also work).The design is a 20-bit fully programmable divider, 100% synchronous, that can be shortened or extended to other lengths (12-bit, 16-bit, 32-bit...).It will run at up to 37 MHz guaranteed due to the use of "carry look ahead".You can use the schematic freely as you like, no license or anything.I attach it in .PDF and zipped .sch (KiCAD Eeschema) formats. It's a pure logic schematic, power, decoupling etc. is left to you. Design notes are in the schematic.Do nottry building the circuit on a "solderless breadboard"; use at least a matrix board, if not a real prototype PCB. The edge rates of 74AC could otherwise cause trouble.CheersEDIT:Very embarassing: A couple of the files were incorrect and the carry-look-ahead file was wrong (and actually showed the simpler ripple-carry counter).They are all correct now.I've added a .pdf schematic of the simpler divider without carry look ahead. I apologize if I've wasted time for you. Sorry

author: Circlotron
author_rank: Super Contributor
timestamp: August 03, 2020, 11:21:53 pm
content: Quote from: Benta on August 03, 2020, 10:53:30 pmJust zip it. End of story.

author: Benta
author_rank: Super Contributor
timestamp: August 03, 2020, 11:23:58 pm
content: Quote from: Circlotron on August 03, 2020, 11:21:53 pmI tried. But my zip program's gone bonkers. I'll try again when it's fixedEDIT: OK, fixed

author: free_electron
author_rank: Super Contributor
timestamp: August 03, 2020, 11:24:31 pm
content: has been around for a long time : 4059 4018 74292 74294

author: Benta
author_rank: Super Contributor
timestamp: August 03, 2020, 11:35:13 pm
content: Quote from: free_electron on August 03, 2020, 11:24:31 pmAn obsolete CMOS part, an unknown part and two Sylvania LED bulbs? What are you on about?

author: Circlotron
author_rank: Super Contributor
timestamp: August 03, 2020, 11:36:22 pm
content: I did a 16-bit programmable down counter about 20 years ago using two CD40103 8-bit counters. Was for a car ignition system. Worked well. And back in 1990 I did a 14-bit one, again for a car ignition, using a Motorola MC145151 radio PLL programmable divider. Worked great!ftp://ftp.jameco.com/Archive/Current-TechDocuments/118586.pdf

author: Benta
author_rank: Super Contributor
timestamp: August 03, 2020, 11:50:18 pm
content: I see that my point about "Standard Logic" didn't really come across. Today, almost no down counters have survived. And certainly not in today's technology (74AC etc.)Synchronous up counters are on the market, and if you want to design something that runs just a little above a couple of MHz, that's what you get. And that's what my free design offers.If you have technical issues with the design, great! I love to learn.But please don't throw 1970/80s technology at me. That's not "Standard Logic" today.

author: schmitt trigger
author_rank: Super Contributor
timestamp: August 04, 2020, 12:02:10 am
content: Benta:Thanks for sharing the circuit.I am sure you spent a significant effort to design it.

author: Circlotron
author_rank: Super Contributor
timestamp: August 04, 2020, 12:10:10 am
content: Quote from: Benta on August 03, 2020, 11:50:18 pmSorry! That was my way of saying I find your post interesting.

author: Benta
author_rank: Super Contributor
timestamp: August 04, 2020, 12:16:21 am
content: Thank You, no ill feelings from here. Rather regret that I didn't emphasize a point which I perhaps should have in the original post.

author: free_electron
author_rank: Super Contributor
timestamp: August 04, 2020, 04:25:12 am
content: Quote from: Benta on August 03, 2020, 11:35:13 pmreally ?https://www.digikey.com/products/en/integrated-circuits-ics/logic-counters-dividers/731?k=4059https://www.digikey.com/products/en?keywords=mc14018https://www.digikey.com/products/en?keywords=74ls292https://www.digikey.com/products/en?keywords=74ls294if you would have cared to search for these devices you would have found them. numbers such as 74292 are generics. they could exist as LS ALS F ACT BCL BCT or any of the hundreds of technology families.Same for the 4018. That's a motorola part so add MC1 in front and you will find itSame for the 4059. still around and in mass production.and let's not forget these :https://www.digikey.com/products/en/integrated-circuits-ics/clock-timing-clock-generators-plls-frequency-synthesizers/728?k=fractional

author: Circlotron
author_rank: Super Contributor
timestamp: August 04, 2020, 04:30:40 am
content: Looks like a 4059 is divide by BCD number, not straight binary.Probably to facilitate inputs from thumb wheel switches.

author: free_electron
author_rank: Super Contributor
timestamp: August 04, 2020, 12:36:51 pm
content: Quote from: Circlotron on August 04, 2020, 04:30:40 amyes. this part was heavily used in pll synthesizers.

author: Benta
author_rank: Super Contributor
timestamp: August 04, 2020, 10:32:51 pm
content: I've now done some timing analysis to quantify the difference between a classic ripple carry approach and the carry look ahead in my divider. The critical timing occurs when reloading the counter chain, not while counting.I've attached .PNG files for explanation, they depict the critical timing paths in the dividers.Based on 74AC161 datasheets fromwww.ti.comI'm using the delay specifications from there (5 V operation, worst case).The pertinent delay parameters are:CK -> TC: 15.2 nsENT -> TC: 9.4 nsSetup times:/Pe -> CK: 5.3 ns74AHC1G00/04 delay: 6.5 nsLooking at the ripple carry counter circuit you'll see that the delay from rising clock to load is: 15.2 + 9.4 + 9.4 + 9.4 + 9.4 + 6.5 ns = 59.3 nsPlus setup time:64.6 ns; giving fMAX= 15.48 MHzMy carry look ahead counter has a shorter path: 15.2 + 6.5 ns, plus setup time:27 ns; giving fMAX= 37 MHzAs you see, the performance difference is very significant.Here are the pictures of the critical timing paths:

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 19, 2020, 02:27:57 am
content: What is the goal of this project?Is it nostalgia, just as with the "retrocomputing" fan clubs?These days you can start with FPGA development boards for around EUR25 and open software frameworks.

author: Benta
author_rank: Super Contributor
timestamp: August 19, 2020, 06:01:49 pm
content: Quote from: Doctorandus_P on August 19, 2020, 02:27:57 amThat this question comes from a user that has contributedzilchto OSHW demonstrates a certain chutzpah combined with condescension that's decidedly unsympathetic.The circuit is a real project (can't say for what) that I wanted to share in the spirit of OSHW.A main driving factor was multiple vendors and a semiconductor BOM of ~1 Euro.

author: Circlotron
author_rank: Super Contributor
timestamp: August 19, 2020, 09:46:58 pm
content: ^^ At times it’s good to get to the fundamentals, the nitty gritty of things rather than have fifty layers of abstraction between you and the circuit. Like designing stuff using individual transistors rather than an op amp. Besides, there is a certain level of satisfaction that can’t be achieved by simply filling in a few values and selecting a few drop down menus on a screen.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 28, 2020, 10:00:20 pm
content: Jeez man, relax.There can be plenty of good reasons to do such a project.Keeping BOM costs down can be one of them.Quote from: Benta on August 19, 2020, 06:01:49 pmRemark based on what?

author: themadhippy
author_rank: Super Contributor
timestamp: August 29, 2020, 12:10:17 am
content: Quoteyea lets spend 25 quid and waste time programing instead of buying a few chips for a quid or 2 that will do the job straight out box

author: Benta
author_rank: Super Contributor
timestamp: August 29, 2020, 07:54:18 pm
content: Quote from: Doctorandus_P on August 28, 2020, 10:00:20 pmJust post a link to an OSHW design that you've submitted, then I'll retract my remark.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 30, 2020, 02:10:53 am
content: I have no interest in refuting your unfounded nonsense.