STM32F0 on 5V instead of 3.3V. I'm surprised it actually works, expected smoke. - Page 1
Forum section: electronics / general

author: Psi
author_rank: Super Contributor
timestamp: July 14, 2024, 03:43:07 am
content: So I accidently soldered the 5V and 3.3V regulators in the wrong place and my STM32F042 MCU got 5V instead of 3.3V woops, but hey mistakes happen.The incredible thing is that it's been working for weeks of development like this, at 5V.I only discovered it when I went to use some inputs and noticed the internal pullups were puling to 5V instead of 3.3VIs this something anyone else has noticed.I would have expected the thing to smoke at 5V. if not immediately after a few minutes.Is it possible I just got some silicon that can handle this?Did they perhaps have 5V in mind for stm32F042 when designing the silicon but abandoned support for it before release?The full chip name is STM32F042K6T6It's definitely running on 5V. This isn't just a case of 5V leaking into an IO from somewhere else.

author: brucehoult
author_rank: Super Contributor
timestamp: July 14, 2024, 05:57:47 am
content: Spec says 1.65V - 3.6V.They have to build in SOME margin, although 1.4V is quite a bit, and maybe 3.3-3.6 is already the intended margin.I guess if you try 100 of them don't expect them to all work at 5V -- and maybe not for 10 years, or at 85 C ambient.

author: Psi
author_rank: Super Contributor
timestamp: July 14, 2024, 06:00:13 am
content: Yeah, i fully don't expect it to be reliable and im sure some features probably wont work right, like probably the ADC. So far I've only been using GPIO and CAN. I'm just so surprised it works at all. The chip isn't even warm.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 14, 2024, 07:03:51 am
content: Hah, last time I did that (swapped regulator voltages), it was a PIC24E which handily zenered at 4.2V, sinking a good 100-200mA. When we got the boards in and USB was only partially working, a thermal check then some probing quickly found the answer.Neat to know STM doesn't  break down at the low end of that range.Were any analog peripherals in use? -- Clock oscillator / PLL, ADC, USB?Tim

author: Postal2
author_rank: Frequent Contributor
timestamp: July 14, 2024, 07:29:16 am
content: Quote from: Psi on July 14, 2024, 03:43:07 amDid you flash the firmware to him during this period? If yes I will try too. I need to connect Hitachi to STM (for test purposes).Because I experimented with a new mcu, but the mcu I needed is from an industrial device and has a crazy bootrom suddenly (can flash via CAN).

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 14, 2024, 08:18:21 am
content: I'd be curious about the current draw. Like, measuring it while using a VDD from say 3V to 5V, and see how it goes.

author: Psi
author_rank: Super Contributor
timestamp: July 14, 2024, 08:48:19 am
content: Quote from: Postal2 on July 14, 2024, 07:29:16 amYes, its always been getting 5V since i hand populated the PCB wrong.It has been flash programmed this way using the built-in UART bootloader.I've only used the GPIO and CANbus features though, not tried anything else.

author: Postal2
author_rank: Frequent Contributor
timestamp: July 14, 2024, 09:02:11 am
content: Perfectly! If the flash works, then everything is OK.About current - I'll be quite satisfied 50 ma, but chip is small and 20 ma would be visible. I guess not over 10.

author: Psi
author_rank: Super Contributor
timestamp: July 14, 2024, 09:16:59 am
content: Its a bit hard to isolate just the MCU current for measurement on this PCB.I measured the current into the linear Vreg when it's 3.3V and again when its 5V.Got 26.3mA at 5V and 26.0mA at 3.3V. This is while code sends a CAN message at 10HzMCU is using HSI48 and clocking at 48 MHzI used fluke DMM, no idea what the pulsed max current is doing.However the same VReg also powers the CAN transceiver IC which I just realized is also only a 3.3V IC.(SN65HVD232)But whatever the MCU current is at 5V, it's not crazy high compared to 3.3V.

author: Postal2
author_rank: Frequent Contributor
timestamp: July 14, 2024, 09:22:10 am
content: I will connect the STM via a diode to the Hitachi's power - and there is no need shift levels. Very well. This thought would not have occurred to me.

author: tszaboo
author_rank: Super Contributor
timestamp: July 14, 2024, 12:10:07 pm
content: Quote from: Psi on July 14, 2024, 09:16:59 amI would imagine it works fine until you turn on something.But it's definitely intersting.

author: Mahagam
author_rank: Regular Contributor
timestamp: July 15, 2024, 07:17:10 am
content: The first step is overvoltage. The second step should be overclocking

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 15, 2024, 07:39:43 am
content: Not sure what the process node they use for this series is.The absolute max voltage from the datasheet is 4V. Which is a pretty standard value for "3.3V" (which is usually 3.6V max) logic.Note that most GPIOs are 5V tolerant, if I'm not mistaken. Meaning that at least IO blocks can withstand 5V. For these small MCUs (Cortex M0, relatively small amount of memory), depending on the process node, they may be essentially pad-limited in terms of die size, and so they may have used logic cells that can operate at 5V almost in all the device, rather than just for GPIOs. Of course, that would be undocumented, some parts/peripherals may not, and that's gambling. But still, interesting to know.

author: Chalcogenide
author_rank: Regular Contributor
timestamp: July 15, 2024, 09:03:01 am
content: Most (if not all) STM32 MCUs have a lower voltage supply for the core, which is supplied by an internal voltage regulator, so the standard cells are going to be fine until something in the regulator fails.

author: tszaboo
author_rank: Super Contributor
timestamp: July 15, 2024, 05:01:52 pm
content: Quote from: SiliconWizard on July 15, 2024, 07:39:43 amI think if it would work from 5V properly, they would shout from a top of a mountain that it works from 5V.It's a feature they would place into the title of the datasheet.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 15, 2024, 07:23:21 pm
content: More likely the higher voltage accelerates damage, such as electromigration, or charge injection into gate oxide. Even if it's not zenering, there can be reasons not to operate a device on the bleeding edge (because devices really can bleed to death, so to speak).Tim

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 15, 2024, 10:30:35 pm
content: Quote from: Chalcogenide on July 15, 2024, 09:03:01 amYes, I wasn't sure for the F0 series, but checked the DS and it indeed has an internal LDO which down-converts VDD to 1.8V. The 1.8V rail should power the core and most of the peripherals, except those that are in the "analog" domain, that are powered from VDDA. And, after that, there are VDDIO1 and VDDIO2 for the IO blocks.What this means is:* While the internal LDO is rated for a 3.6V max input (4.0V absolute max), like for the rest of the supply rails, this LDO can probably withstand significantly higher. I said: probably. Meaning that you can *probably* use a higher VDD without much risk. Of course, only access to the internal design would tell that for sure. But from a design POV, it's not absurd to think that this LDO would tolerate a higher input voltage than the rest of the design.* VDDA directly powers some "analog" blocks, so for VDDA, that's a different matter. I would suspect that it would be a lot riskier to exceed the max rated voltage on VDDA.* For VDDIO1/2, can't tell. But it's also at least not unreasonable to think that the IO blocks can withstand 5V without too much trouble. Maybe there's a difference between the two, as well. Haven't looked at what exactly each of these 2 rails powers exactly - a quick look seems to indicate that VDDIO1 would power all GPIOs and VDDIO2, the USB PHY. Not 100% sure though.TLDR;* If one connects all power rails to the same supply (which is probably typical for a simple "3.3V" design, and possibly what the OP has done), then the risk, to me, looks much higher. In particular, it could cause issues with the ADC.* If one powers VDD, and possibly VDDIO1 from 5V, it may be relatively safe - can't guarantee it, but that wouldn't look totally unreasonable. I would suspect it to be much riskier with VDDA and VDDIO2. Just my thought so far.

author: coppice
author_rank: Super Contributor
timestamp: July 15, 2024, 10:45:36 pm
content: Unless you hit some complex pin protection on a split rail device, that completely fouls up, most MCUs will tolerate a lot more than their rating... at room temperature.... for a while. Its often surprising what you can get away with short term. You can't market a device on that basis, though. Specifications need to be highly predictable and sustainable. Even people who generally go for conservative specs have been known to stress their parts a little too much from time to time and have rapid failures - e.g. the first generation of Intel chip sets with 6Gbps SATA interfaces had stress failure issues when used within their specs.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 15, 2024, 11:13:13 pm
content: I recall reading about some ancient PGA chips (serdes maybe?) that, ran rather hot to begin with, but were always on the verge of failure and were clearly a wear item, to be replaced regularly. If not by design intent, but certainly on repair. Which, of course, made them rather expensive to replace, on top of being ceramic PGAs already, but particularly as they went obsolete and supplies dried up...I forget what that was in, some vintage minicomputer system I think, or perhaps video processor. Probably this is enough to jog someone's memory...Even the best get things wrong from time to time; that might've been an IDT part, plus the Intel example above. And I mean Intel is on the working group so it's not like they weren't aware of the design issues. High speed interfaces, I think, are a tight compromise between robustness (especially ESD and cable discharge), speed (maximum bandwidth for minimum current consumption) and reliability (push out aging, electromigration, etc. failure modes to some decades at operating limits). All the while, refining process control so the chips are being made the way they were designed, etc. New IO interfaces like those (i.e. back when SATA, PCIe, etc. were new) might well be tested down to physical simulations of the process node, but maybe also just from SPICE models extracted from whatever combination of physical simulation plus test fab. The challenge is, to maximize bandwidth, you maximize current density, and therefore gm/C (bandwidth, or figure-of-merit thereto), but with the IO transistors basically short-circuited (most of VDD dropping, maximum current density), and being such small and delicate features, they're only going to last so long, and failure is inevitable. It's a matter of tuning those parameters (bandwidth, geometry, etc.) to get just enough worst-case margin that yield, product quality and reliability are acceptable.And yeah I know LVDS style interfaces are a bit different than that, I don't know offhand what size (W, L) transistors they use, but obviously the low current means big savings, and they're biased a bit inbetween VDD/GND so the voltage stress isn't as crazy, besides which these IOs usually operate lower anyway (e.g. PCIe, DDR5, etc. regularly use 1.2V or lower supplies).You see a hint of this when looking at FPGA IO ratings: typically they caution against DC loads at all, or more than a couple mA say, even though you might only need them to be 74HC-equivalent (and they might be configurable to comparable ratings otherwise). It's when robustness is dictated by the finest output structures (many are configurable for LVDS etc.), that these ratings need to be posted, andhonored.As for VCOREs, it seems very popular these days: even AVRs (Dx, etc.) appear to be using that scheme, allowing them to offer even richer peripherals and memory, on smaller chips, more stable performance vs. supply (no CLK/VCC limitations as on MEGAs), and in the AVR case, 5V IOs since that's the kind of thing they're going for, but tons of 3.3V devices out there as well. It seems they've cracked a no-external-cap regulator scheme, so it works transparently, only a couple power management settings (and, I suppose, startup time limitations) even hinting at the architecture.Internal switching regulators are a relatively new thing too. Usually not so highly integrated that the inductor and capacitor are included, but nothing else than that required externally, besides the usual bypasses of course.Tim