(Review request) STM32 Breakout board - Page 1
Forum section: electronics / beginners

author: Fcolor04
author_rank: Contributor
timestamp: June 24, 2023, 02:38:22 pm
content: Hello, I've recently been listening to all the do's and dont's of pcb design and so I want to ask for a pcb review of my arduino sized STM32 bluepill redesign, I used two ldo's for higher current capability but I didnt put many power output pins just yet because I want to get signals right first, do you think its gonna have EMI issues or ground loop issues? What would you suggest I take a look at/improve/redo?

author: ArdWar
author_rank: Frequent Contributor
timestamp: June 24, 2023, 03:56:03 pm
content: Quote from: Fcolor04 on June 24, 2023, 02:38:22 pmThat's not how you parallel LDO, you can't just connect two together.Use ballast resistorIf you want to improve thermals, get LDO where the tab is GND. There are a lot of them available. I personally never a fan of Vout on tab design...Do you really plan to draw the full 3A out of it? When dissipation exceeds 3W it might be time to start considering buck regulator instead.I see there are a lot of places where your traces don't really need to switch layers, but that's not critical I guess.ED: A lot of your traces seems to be not actually connect to header pads. Don't you get DRC error? Where are the ratsnests?

author: Fcolor04
author_rank: Contributor
timestamp: June 24, 2023, 04:23:49 pm
content: I'll look for other LDO, I meant 1.6A rating when combined, headers aren't connected yet because I dont want to change schemating a dozen of times if someone tells me that I should have more ground pins in between signals for example. Regarding "signals changing layers when they don't have to", I did that to preserve wide ground plane interconnections, with signal line going almost across the board it looked like the ground plane would split across with 1-2mm connection which doesn't sound like its best practise

author: DavidAlfa
author_rank: Super Contributor
timestamp: June 24, 2023, 09:29:36 pm
content: EMI issues? That's only for commercial or extremely sensitive applications - A breadboard powered for USB is nothing special.Yeah, the inventor to the LDOs with Vin in the tab should get executed, just why!I recently tried to find a decent SOT89 LDO, high noise rejection, low drop, >500mA...90% of them had power in the tab! The rest were just to expensive so I finally gave up.Not a bad layout, but add via stitching between ground planes!Paralleling LDOs is not good, they never have 100% voltage output so one might work a lot harder than the other.If powering high current devices like leds, motors, better to use a switching converter module.But keep a LDO to power the stm32 and analog stuff, you don't want noisy rails there!

author: tooki
author_rank: Super Contributor
timestamp: June 25, 2023, 09:23:51 am
content: Quote from: Fcolor04 on June 24, 2023, 04:23:49 pmYou’ve got tons and tons of layer changes that make zero sense. Like all the top-layer connections to the left side header: why not just leave them on the bottom layer?Or the bundles of layer changes at the bottom, which exist only to get around some components that have no need to be in that exact spot (and almost certainly would benefit from being somewhere else).Or just above the MCU, where there’s a knot of vias and traces that could almost certainly be simplified.It’s not that it won’t work. It’s just needlessly complicated. And all those unnecessary via jumps take up space, taking away from the ground planes.

author: Fcolor04
author_rank: Contributor
timestamp: June 25, 2023, 07:46:57 pm
content: I've redone left connector tracks, tried to remove as many vias as I can, removed other LDO, its gonna cause more issues than necessary, I think its production ready hopefully I didn't miss anything this time

author: DavidAlfa
author_rank: Super Contributor
timestamp: June 25, 2023, 09:27:44 pm
content: Siggestion: avoid smaller parts than 0603 if soldering by hand!Also these smd electrolytics are a bit messy to get done, I'd put through holes in the said case.Still, that board can be made much smaller, specially in the LDO side

author: Doctorandus_P
author_rank: Super Contributor
timestamp: June 25, 2023, 10:00:52 pm
content: The SWD connector is in a very unfortunate location.If you move that connector, then you can route all the I/O to the first 10 pins to the left side connector on a single layer, and keep the other layer empty except for the GND plane.I also don't like running the reset track under the uC in the way you did. I prefer to at least have a local GND zone directly under the microcontroller, which connects all GND pins of the uC together.

author: Fcolor04
author_rank: Contributor
timestamp: June 27, 2023, 12:25:41 am
content: Thanks for all the suggestions, here's V3 of my design, it shrunk by 20%!!! by moving reset and analog voltage supply a bit also the 2 solid ground planes under uC should be much better than the original, any other tips?

author: DavidAlfa
author_rank: Super Contributor
timestamp: June 27, 2023, 01:28:28 am
content: You improved really fast , much better!Though you made a little ooops at pin 20, fix that track!What USB-C connector is that? Looks pretty awkard to me!Nevermind:https://jlcpcb.com/partdetail/HOOYA-USB306B/C309343

author: ArdWar
author_rank: Frequent Contributor
timestamp: June 27, 2023, 01:37:33 am
content: Beware with the two huge caps in the VBUS. I don't remember exactly but I *think* there's guideline on how much inrush current and capacitance you can put on VBUS. A maximum of 10uF can be directly connected without inrush limiter IIRC.You probably don't need (or want) to make your board USB certified, but conforming to standards and best practices as much as possible is still a good idea. You probably don't need to limit to such extent, but definitely don't put two 220uF caps on it 😅

author: Doctorandus_P
author_rank: Super Contributor
timestamp: June 28, 2023, 04:03:58 pm
content: It does indeed already look a lot better. Some more ideas:Big ceramic capacitors on the output of an LM1117 can lead to instability. (I have not checked the "LD" version datasheet).I agree with the big buffer caps. These lead to very high peak currents when the connector is inserted, and this leads to sparking and connnector wear.Make the interruptuions from tracks on the blue layer shorter to improve the GND plane. In general when you have to interrupt the GND plane with tracks, add some via stitching if there are tracks on the other side to provide a return path for the sinals through the GND plane. In this situation it does not matter much because there is only one GND pin for the connectors on the right side (hint: adding more GND pins would be an EMC improvement)Move the capacitor in the top left corner of the microcontroller a bit so the GND plane has a solid connecton.There are some quite large area's on the red layer which are only connected to GND in a single corner. Such area's can (and will) act as antennas which can both pick up and transmit noise. You can add some via stitching to prevent this.Add one (or two) stitching via's to each GND pin of each capactor, to directly connect it to the GND layer on the bottom of the PCB.KiCad has a "Symbol" library which also has kicad logo's. It's always nice to see more KiCad logo'sI count around 20 DRC violations (arrows). What are they for? Are any of them important? (You can disable them in DRC if you have verified they are not important

author: tooki
author_rank: Super Contributor
timestamp: July 01, 2023, 01:51:03 pm
content: Soooo much better in the revised version. Well done, Fcolor04.It’s good practice to not route any traces underneath your crystal. You’ve got enough space to easily make this change.Regarding LM1117 stability with ceramic caps: rather than changing the layout, I would simply find a pin-compatible alternative that is specified to be stable with ceramic input and output caps. For example, the LDL1117 from ST. Its performance (as far as noise rejection) is overkill for a microcontroller, but it’s still only about €1 and is expressly designed to work with ceramic caps. (I used it on the last MCU board I made.) Your regulator layout is physically nice and tight as it should be.I would just add more vias to ground, just like Doctorandus_P said. Put one or two next to each ground pad of components (especially ones with higher current, like power supply caps, where you may even want to add more), as close as possible. I would add a bunch of vias to the regulator ground, to ensure it’s got a nice, low-impedance path to ground. And since you’re not running out of space, just sprinkle them all over the place as via stitching. (I think kicad has a function for that, either built in or as a plug-in.) Just do that when you’re otherwise done.