Very simple FPGA for ADC 12-bit - Page 1
Forum section: electronics / general

author: Oleander
author_rank: Contributor
timestamp: August 08, 2019, 10:30:26 am
content: Hello,I am about to design a detector of some 5-10MHz, 5mV sine signals using a 12-bit ADC and FPGA.I am new in this area of electronics, so I have to choose appropriate FPGA.Will the Lattice ICE40LP384 be sufficient for that ? Or it's more feature-packed syblings ?The output of the FPGA will be further used to feed a typical microcontroller, not choosen yet.

author: aldi
author_rank: Contributor
timestamp: August 08, 2019, 04:42:24 pm
content: Hard to say. If you don't know about the number of gates/LUT's you need, you could start making and simulating the design (VHDL/Verilog), and choose the right sized FPGA after you're done.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: August 08, 2019, 05:34:02 pm
content: Quote from: Oleander on August 08, 2019, 10:30:26 amWhat operations are going to be done in the FPGA? Is this just a frequency counter or do you need to do substantial signal processing?

author: iMo
author_rank: Super Contributor
timestamp: August 08, 2019, 05:38:02 pm
content: Sure, it fits easily. The LP384 includes 384 LUTs+FFs, for reading a standard 12bit SPI ADC you may need ~50 LUTs.The question is how is the ADC sampling rate and ADC data/bit rate off the FPGA (SPI?, parallel?). In case you target an SDR-like gadget with up to 10MHz sampling/data rate you have to provide more info on that..

author: ejeffrey
author_rank: Super Contributor
timestamp: August 08, 2019, 05:54:17 pm
content: What speed is the ADC? What are you doing with the data? How are you getting it to the microcontroller?That FPGA should be large enough to clock data out of the ADC, but won't be able to do much with it. If your ADC is operating at 25 MS/s that is 300 megabit/s which you aren't going to transmit to the microcontroller via SPI... That FPGA doesn't have any SRAM to use as a buffer nor any DSP cores to use for analysis. So you are going to be limited to the signal processing you can do with just LUTs. You could do a peak detector and a rolling average or a frequency counter. If you want to do any more sophisticated signal processing (such as spectral filtering / FFT) you are going to need a bigger FPGA.The only way to know for sure is to write up some RTL and try to synthesize it with the vendor tool. See if it will fit on the target and meet timing. If not, then you decide if you think you can optimize it or need a bigger device.

author: iMo
author_rank: Super Contributor
timestamp: August 08, 2019, 06:04:21 pm
content: Any '"dsp" or "math" like operations are off the LP384 capabilities, sure. It can shift data in/out provided the clocks are less than 50MHz, imho. Maybe some simple FIFO, averaging, min-max, that is all..

author: Oleander
author_rank: Contributor
timestamp: August 08, 2019, 06:52:54 pm
content: This should be done in the FPGA:- measuring and deciding if an incoming sine signal belongs to the range between 9...10MHz,- assuring that the above singal has stable frequency for at least its 20 periods,if the result of these both conditions is OK then FPGA sends a logic 1 tocertain input of the microcontroller. This "1" is on as long as the signal is present.Data bit rate on this pin will then be 20 times slower then the rate on the outputs of the ADC.The ADC would be 12-bit, 20 MSPS. I think this will be enough to measure 10MHz sine.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 08, 2019, 06:56:15 pm
content: I guess an SPI ADC would probably be out of the question though at this sampling rate.

author: james_s
author_rank: Super Contributor
timestamp: August 08, 2019, 07:42:14 pm
content: I would first get a prototype working on a development board that has a relatively large FPGA and then figure out the most cost effective part that will meet your needs.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 08, 2019, 08:56:36 pm
content: A first step would be to get an idea on how to handle to task. Especially the reasonably stable point is not clear.One may not even have to build a board, just get the HDL code and let it compile to get get the approximate size. The size may depend on the type of FPGA, but usually no that much.I could imagine something like running an Goertzel algorithm could work, though it may be overkill, and not sure about the stability question.There could be simpler versions and not sure if it really takes 12 Bits for the job (even just 6 bit might be enough).A 20 MSPS ADC would be on the low side to get 10 MHz signal - without much analog filtering its more like 4 times the highes signal frequency.

author: BrianHG
author_rank: Super Contributor
timestamp: August 08, 2019, 09:06:47 pm
content: Quote from: Oleander on August 08, 2019, 06:52:54 pmSo what you need is a digital 9-10Mhz band pass filter with a 500Khz bandwidth AM detector/tuner which looks for a steady clean carrier.Yes, for 9-10Mhz, you will want at least 40Mhz sampling rate, maybe even 50Mhz.You actually don't need a 20Mhz ADC at all for this. Just a high speed 1 bit comparitor and in the FPGA, a counter plus a serial pipe of D-flipflops running to discriminate the precise 9-10Mhz.You don't even need a comparitor, a single or dual RLC tuned transistor amp feeding a clock input pin on the FPGA will do.(expect the tuned transistor amp to pass a signal anywhere between 5Mhz through 15Mhz, the FPGA will still be making your precision 9-10Mhz detection)(I once did this in a EPM3192 PLD to digitally decode the presence and phase of the NTSC video's color burst signal, so I know it can work, though, I was only analyzing 8 cycles with a 14.31818Mhz clock, the PLD was doing others things as well like generating a new time locked NTSC reference frame. Without any necessary additional logic, your project should also fit into a PLD of the same size using a similar 1 bit input sampling scheme.)Your other choice is an analog band pass filter with the same 1Mhz band pass, 500Khz AM detector. Readily available in a single analog tuner FM - IF ICs. (You would take the analog out of the IC and feed a slow ADC input on your certain microcontroler, no FPGA needed)

author: filssavi
author_rank: Frequent Contributor
timestamp: August 08, 2019, 10:00:18 pm
content: If you need to only evaluate frequency stability of a sinusoid you could even do with a mcu, you first square the incoming signal with a reasonably fast comparator, then you just need a MCU with a 32 bit counter, and an external clock input, you then generate a reasonably long gating pulse (let’s say 0.1 second or higher), To enable the counter and at the end you just read how many edges your signal had in the aforementioned period

author: BrianHG
author_rank: Super Contributor
timestamp: August 08, 2019, 10:25:46 pm
content: Quote from: filssavi on August 08, 2019, 10:00:18 pmHe wants a valid evaluation in 20 cycles, with an output as fast. That's a 500Khz evaluation time, meaning a 0.000002 second gating pulse.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 08, 2019, 10:28:55 pm
content: Quote from: Oleander on August 08, 2019, 06:52:54 pmOh, if you can assume that the input signal is a sine wave with reasonably low distortion, and you don't need to check that, you definitely don't need an ADC.A simple comparator to make this a square signal as suggested would do the trick. You may have to add some amplification first and possibly some level shifting too if the signal is zero-centered. Then the testing can be either done in a very small FPGA, or an MCU as also suggested above.Some small MCUs contain opamps and/or comparators, so you may even not need anything else than such an MCU (as long as it's fast enough) and a few passive components...

author: NorthGuy
author_rank: Super Contributor
timestamp: August 08, 2019, 10:52:56 pm
content: A band pass filter fill filter out everything which is not between 9 and 10 MHz.Then a comparator will digitize it into a square wave.From this point you can count pulses directly on MCU.Alternatively, you can feed the square wave to a low pass filter followed by another comparator, which will produce the desired '0' or '1' signal for the MCU.

author: iMo
author_rank: Super Contributor
timestamp: August 09, 2019, 12:28:37 pm
content: A 4046's VCO set to 9.5MHz and do use one of its phase comparators..Its input includes an amplifier such it may amplify the 5mV sine for you too (do couple the signal AC - via a 10nF capacitor)..http://www.ti.com/lit/an/scha002a/scha002a.pdf

author: Oleander
author_rank: Contributor
timestamp: August 09, 2019, 02:53:10 pm
content: Thanks for all of you - now I'll think hardly about all suggestions.Comparators that have good speed for 10MHz signal, do not have good offset input voltage - it is comparable with input signal itself.So input signal conditioning should rather be done by something else. Maybe opamp, like AD8021 or NE592 ...I forgot to add that input signal will be differential for better immunity from outer noises.It'd be good to operate in differential mode until the signal reaches Volts for further processing.

author: SiliconWizard
author_rank: Super Contributor
timestamp: August 09, 2019, 05:54:44 pm
content: Quote from: Oleander on August 09, 2019, 02:53:10 pmWell, yes, your requirements are a bit more stringent than they initially appeared.But the signal certainly doesn't need to "reach Volts" to be processed.If you really want to take full advantage of the noise rejection the differential mode offers, you should ideally use a proper instrumentation amp as the input stage. Finding one with appropriate bandwidth will have consequences on the required power supplies. Typically, most instrumentation amps powered at +3.3V/0V for instance will not have enough bandwidth for your requirements even at unity gain (if you find one, I'll take it!)If you have access to something like +/-5V, things become simpler. You could for instance (with LT parts as an example), use an AD8429 as the front-end with unity gain or (up to x2-x3), followed by a fast opamp for additional gain (may not be needed because the LT1715 has low input offset and low hysteresis voltage), then followed by a fast comparator such as the LT1715, which has a dual supply scheme: the input supplies would be +/-5V, the output supply would be +3.3V/GND for instance. Then the output can get straight to an MCU of small FPGA.Disclaimer: this suggestion is definitely not cheap. There are probably many simpler (and cheaper) approaches than this analog-wise, but I think this one is fast and good at rejecting noise, and should work reasonably well.

author: BrianHG
author_rank: Super Contributor
timestamp: August 09, 2019, 08:05:02 pm
content: I would use an FM radio IF tank/balun transformer feeding a 2 stage MPSH10/or/MMBTH10 NPN RF transistors in common emitter configuration powered at 3.3v with the final output collector driving the input of the FPGA.Only need a single 3.3v supply, fully balanced input due to the tank/balun transformer, a few 0603/0402 resistors and caps on top of the 2 x 4cent transistors and under 1$, a working solution. No positive or negative supplies. No instrumentation devices. And an above 50Mhz bandwidth if you need it by altering a few resistors.Without the tank/balun transformer, this can be done with 2 transistors in place of the tank making an equivalent opamp balanced input stage with a switch comparator like output.For near balanced or unbalanced input, you just need an inductor in the place of the tank and feed a portion of the negative source into the first stage RF transistor. This is not as high quality, but you can tune it to reject around 15 db common mode noise while the tuned input will get rid a good portion of the rest.However, without knowing all you variables, the all instrumentation devices with multiple positive and negative rail supplies may be your only hope.When I say IF transformer, I mean a Balun transformer with a tuned resistor and cap on the input and output like this guy:TDK Corporation ATB2012E-20011-T06They are around 49cents each.Not only will your input be truly balanced, but, it will also be galvanically isolated from you digital section.