(mis)using ECL for delay and pulse generation - Page 1
Forum section: electronics / projects

author: mathias
author_rank: Regular Contributor
timestamp: May 14, 2014, 06:28:59 pm
content: What I've done (successfully) in the past was to use a CMOS EXOR gate to generate a pulse from a step input. One input is coupled directly, the other through an RC-filter. Only when the cap is fully (dis)charged both input pins will be low. My question is quite simply: will the same work with MC100 ECL logic (and without too much jitter ofcourse)?

author: dannyf
author_rank: Super Contributor
timestamp: May 14, 2014, 06:42:43 pm
content: Generally not guaranteed: ECL devices have much lower input impedance vs. cmos devices and may overload the rc network. It is possible that in some cases this doesn't matter but without knowing your application, no one can assure that.

author: w2aew
author_rank: Super Contributor
timestamp: May 14, 2014, 07:01:38 pm
content: You should be able to make this work for ECL also. You just have to take special care to properly bias/terminate the emitter-follower outputs. At a minimum, they need a pulldown resistor, or your can use a thevenin equivalent to present a 50ohm to VCC-2V load (this is what they're spec'd into).

author: SeanB
author_rank: Super Contributor
timestamp: May 14, 2014, 07:05:25 pm
content: With ECL it probably is better to use a LC delay, or a short length of transmission line to do the delay. That at least will be able to be terminated correctly for ECL use. I think I have some programmable ( by using taps) delay lines on a board, they are interesting items, delay of around 10ns per tap.

author: retrolefty
author_rank: Super Contributor
timestamp: May 14, 2014, 07:11:31 pm
content: How about one of these.http://www.onsemi.com/pub_link/Collateral/MC10E195-D.PDF

author: mathias
author_rank: Regular Contributor
timestamp: May 15, 2014, 05:44:02 am
content: LC delay lines and MC100EP196 will only get me up to several ns's, but I need about 10us. Perhaps I'll make a little trip from ECL to CMOS and back. That way I can use the old trusty CMOS (little) logic for delay.@dannyf: That's not a good sign, when I need such long delays, the resistor for the RC filter will be several kOhms typically.Thanks for thinking with me!

author: jpb
author_rank: Super Contributor
timestamp: May 15, 2014, 09:51:51 am
content: Quote from: mathias on May 15, 2014, 05:44:02 amDo you have a clock in your ecl system somewhere? If so wouldn't it be easier to use something like a latch and a counter?

author: David Hess
author_rank: Super Contributor
timestamp: May 15, 2014, 02:00:15 pm
content: Short RC delays work just as well or better with ECL compared to other logic families but 10 microseconds is going to be problematical. A differential circuit using a comparator or ECL line receiver where you can control the threshold voltage and reject power supply noise would work better.

author: mathias
author_rank: Regular Contributor
timestamp: May 15, 2014, 06:49:40 pm
content: Taking everything into account, a slow ramp with comparator will probably work the best.To the breadboard!

author: David Hess
author_rank: Super Contributor
timestamp: May 15, 2014, 08:05:26 pm
content: As a practical matter I know that based on existing analog designs, with a delay of 10 microseconds I could keep the jitter within 1 nanosecond. I do not know how much better I could do but I suspect it would be a significant challenge.

author: mathias
author_rank: Regular Contributor
timestamp: May 16, 2014, 05:43:56 am
content: Jitter won't be an issue. This circuit is going to be used the trigger circuit for my sampling scope, to re-arm the trigger after a certain dead time. At this point everything is built using ECL.