"Amps per Unit Trace Width (ATW)" - Page 1
Forum section: electronics / general

author: gnuarm
author_rank: Super Contributor
timestamp: January 06, 2023, 07:24:21 pm
content: I see "Amps per Unit Trace Width (ATW)" specified in a Xilinx document. At first I thought it might be referring to something like the unit square, but that doesn't make sense in the context.It appears in table 5, page 18.In the diagram above, figure 8 on page 17, they use a similar term as the current permilof trace width and show the same current, 50 mA/mil "Amps Per Mil of Trace Width (APM)". So I guess someone writing the table got a bit lazy/sloppy? Or are these different terms?ug1099-bga-device-design-rules.pdfI'd give a link, but AMD seems to be too cautious to provide a decent one. They want you to go through their process.

author: thm_w
author_rank: Super Contributor
timestamp: January 06, 2023, 09:34:32 pm
content: A mil is a unit of trace width, so they would be the same, just the first one (ATW) is unitless.They seem to use ATW where the units are mm's.https://docs.xilinx.com/r/en-US/ug1099-bga-device-design-rules/Power-Delivery-to-the-FPGA

author: Someone
author_rank: Super Contributor
timestamp: January 06, 2023, 10:11:31 pm
content: Those figures from Xilinx are on the conservative side (as is most of their application/guide material). But calculating trace widths and power impedances are pretty much essential tasks on most FPGA designs, not something I'd be leaving to rules of thumb or pre-canned assumptions.

author: gnuarm
author_rank: Super Contributor
timestamp: January 07, 2023, 06:18:44 am
content: Quote from: thm_w on January 06, 2023, 09:34:32 pmI think you meant, "where the units aremils". No?I found this document hard to read because the writing is terse and a bit confusing. Most documents describing the land and via dimensions are confusing. This one says it is important for the board pads to be non-solder mask-defined (NSMD), meaning no solder mask on the pads. But the numbers they recommend for a 196 pin, 1.0 mm spaced BGA are 19.7 mil for the pad and 20.9 mil for the solder mask opening. That doesn't leave much for alignment tolerance!I don't understand the use of the term "via plating". How is this different from the via pad diameter? They have an illustration for via in pad, where the plating is smaller than the pad. Maybe I'm reading too much into the illustration?I find it interesting that as PCB features shrink the unit "mil" is becoming a bit coarse. They show for 1.0 mm ball spacing, a 4 mil space and 3 mil trace between pads. That leaves an extra 1.7 mils "unused". Why not spread that around a bit for 3.5 mil traces? Or, the trace to pad spacing might be more important, so 4.5 mil space and 3 mil trace? They actually have some errors in converting between inches/mils and mm. 19 mil is not 0.33 mm, not even close!If all the numbers are done in mm, 1.0 mm centers and 0.5 mm pad diameter, the trace/space can be 0.1 mm each (3.937007874016 mils). Why obsess with making things an even mil number? Is this something a PWB maker's software is going to flag as a "special" capability?

author: gnuarm
author_rank: Super Contributor
timestamp: January 07, 2023, 06:29:36 am
content: Quote from: Someone on January 06, 2023, 10:11:31 pmThis design is not going to be stressing anything power related. Max clock speed of 33 MHz and most of the design is low duty cycle being slaved to a CODEC at 48 kHz sample rate. Half of the BGA I/O won't be used, so no need for vias. Not on this board. I'll use the same FPGA on the test fixture, two actually. There I'll be using most of the I/Os, but lots more room to fan out the routing. This one will get a lot more exercise.

author: thm_w
author_rank: Super Contributor
timestamp: January 10, 2023, 01:06:47 am
content: Quote from: gnuarm on January 07, 2023, 06:18:44 amYeah you are right, its all mils used then.Mixing units in the same table is super confusing.QuoteFor via plating, I assume that illustration is just to show that the via plating might be a different diameter, if you had solder mask defined pad. In the case of NSMD plating/diameter is the same.Considering the errors, I would go based on what your fab house can reliably do for trace/space instead of what they specifically recommend in these tables.Nothing will be flagged as long as the trace width is as wide as their minimum or wider.JLC gives some specs in mm and mils for example, and the mm dimension is slightly smaller due to rounding, and is most likely the "real" spec.

author: gnuarm
author_rank: Super Contributor
timestamp: January 10, 2023, 04:15:05 am
content: Quote from: thm_w on January 10, 2023, 01:06:47 amI don't actually have the bare board made. I use a CM. In general, I get no feedback from CMs about what design rules are good for low costs, or easier assembly, other than certain things, like they don't want to use panel scoring. They said they have trouble with that. I thought that was used because it made life easier for them. They want to do the tab routing thing. That requires hand work to smooth the edges...after assembly. They say they are sanding down the edges of the scored boards too. That just seems like a way to blow out chips, but maybe they have conductive sand paper.Sometimes I think people have no clue at all about static charges. It doesn't matter if you are grounded, or if the table surface is grounded, if you rub fur on a Plexiglas rod, you are going to get a massive electrical buildup. Sandpaper and fiberglass, I'm not sure, but I think it has potential... pun intended.QuoteYeah, the problem is, I don't know who will be building the bare boards, so I don't know their design rules. I'll contact the CM and push a bit. It's pretty definite that I'm going to have to use a BGA, and they are going to want to know about that sooner or later. They've already said this will require x-raying of each board. I suppose that can be done on the panel. They aren't real big.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 10, 2023, 06:22:44 am
content: Unless you're doing high performance, I'd be surprised you need as much DC as AC (i.e. low inductance)?I suppose the other question is, is even that true? AC will simply be proportional to the maximum number of gates changing in sync and the clock rate. I don't see why that would be different if your application demands tight timing precision; it should still scale the same way, just versus a different baseline. And likewise for IO cells, how many are changing at a time, and what rate, per IO bank. (Being that there's fewer IOs/bank, you're more likely to use a large fraction of those, so, bypass accordingly.)Tim

author: gnuarm
author_rank: Super Contributor
timestamp: January 10, 2023, 02:26:22 pm
content: Quote from: T3sl4co1l on January 10, 2023, 06:22:44 amSorry, I'm lost. What are you responding to exactly? I was just asking about the use of the term "Amps per Unit Trace Width (ATW)" and various issues in routing.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 11, 2023, 04:35:04 am
content: I was commenting about the use of the term "ATW" and various issues in routing.Ampacity is a DC thing. A figure like "ATW" doesn't strike me as very useful anyway (IPC-2152 and etc. are merely idealized / suggestions), and AC tends to dominate (inductance). You're aware of routing issues/techniques with respect to that, so I needn't go into detail.Tim