Thermal relief vs direct connection for heat dissipation  - Page 1
Forum section: electronics / projects

author: ricko_uk
author_rank: Super Contributor
timestamp: May 04, 2022, 06:57:10 pm
content: Hi,normally vias and pads are connected to inner planes with thermal reliefs to relief thermal stress (expansion/contraction). Someone at a PCB fab suggested that they are not needed anymore with the materials used in PCB build nowadays. Not sure how reliable information that is...If you have a SMD package (lets say TO263) that needs to dissipate a lot of power in a cyclic manner - i.e. is turned on and off every 20-40 seconds resulting in the package heating up to 70-80 degreesC and cooling back to 25C - i.e. high cyclical thermal stress, would you need thermal reliefs? Or can you have still full/direct connection to the internal plane?I am asking because it would be safer to have them but I think that at having them they would decrease the heat dissipation/conduction into the inner planes, especially those further down the stack (i.e. layer 3 and 4 in a 4-layers PCB) which are the ones which would eventually dissipate the heat into a heat-sink in contact with the bottom side of the PCB.Thank you

author: tooki
author_rank: Super Contributor
timestamp: May 04, 2022, 11:49:45 pm
content: It’s my understanding that thermal reliefs exist to facilitate soldering, because they create choke points that prevent heat being sucked into big copper planes. High currents are exactly when youcan’tuse thermal reliefs, because you need low (electrical) resistance. Similarly, you don’t want to use them on pads that are the heatsinks for the component.

author: ricko_uk
author_rank: Super Contributor
timestamp: May 04, 2022, 11:57:59 pm
content: Thank you Tooki,what you are saying does make sense about the soldering but I always saw them in vias too where there is no soldering. And by default the CAD packages I used always put them in vias too.That's another reason for it being a bit confusing...Thank you

author: Someone
author_rank: Super Contributor
timestamp: May 05, 2022, 12:36:11 am
content: Quote from: ricko_uk on May 04, 2022, 11:57:59 pmThe default rules are usually simplified/stupid/conservative. IPC guides don't recommend thermal relief on vias so the question is solidly over to anyone suggesting them to justify it very well.

author: thm_w
author_rank: Super Contributor
timestamp: May 05, 2022, 01:45:53 am
content: No one really suggested them, its just the default rule in Altium to thermal relief every feature (holes, vias, pads).The first rule I'll add to a new design ruleset is IsVia -> Direct connect.https://resources.pcb.cadence.com/blog/2021-pcb-thermal-relief-guidelines-for-effective-layoutshttps://www.vse.com/blog/2020/02/18/pcb-thermal-relief-guidelines-for-manufacturing/

author: ricko_uk
author_rank: Super Contributor
timestamp: May 05, 2022, 01:06:21 pm
content: Thank you both

author: oz2cpu
author_rank: Frequent Contributor
timestamp: May 05, 2022, 01:50:44 pm
content: show a snip of your pcb design, where this part is, this way we can much easier explain what we would have done in this situation..every time i give advices about pcb layout, i can remember old designs where it was a super good idea, but also others where it was a super bad idea,that is why we need to see, before we can tell..

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 05, 2022, 08:00:24 pm
content: Heh, I wouldn't trust what a PCB fab says, but a PCBassembleryes. If they do both, then that's probably fine too.Note that spokes are hardly anything at all, thermally or electrically -- given judicious dimensions, and typical densities used in PCBs.So what good are they in soldering? Soldering is done at much higher heat density. If the spokes drop say 1 K/W, that's inconsequential for the say 5W you might get out of a D2PAK; but if you're putting 50W into it by soldering iron, or who knows what by hot air -- now you're talking the difference between the joint reaching MP (180 to 230°C depending on alloy) or not at all (versus a cold board / no preheater, and a hot end at 200-300°C say).And, note that hot air machines have much faster airflow than you'd normally use in a project, so of course the convective heat flux can be much higher: a D2PAK might dissipate hardly a watt over its surface in operation, at maximum temperature (minimal footprint, no heatsinking), but it can absorb enough power in this condition to make a difference (even with heatsinking pours).As for spoke size, I would suggest maybe max(pad width, pad height) / 8 or so as a starting point, also not to exceed minimum pad width/height (shouldn't be a problem, pads aren't usually so narrow as to run into this), and no smaller than minimum trace width in the design.Normally you'll just pick up two or three rules and let that be that. Like attached (download and rename to .RUL, then D, R, right-click list, Import Rules, Plane, Polygon Connect, OK, select file, OK).And you can always remove thermals by setting the pad class (D, C, Pad Classes, create new, name 'Direct', add pads in list; this list will not be updated from SCH so persistent selections can be made here, but mind to check things as you add/remove/rename components).And to be clear, for those who don't know: PCB laminatesucksthermally. It's not a terrible insulator, particularly thru-plane. Lateral is merely "not great" conductivity. Copper pours spread heat laterally (over a diffusion length on the order of 2cm/sqrt(oz of Cu thickness), something like that maybe?) so, greatly increase the dissipation of a component, going from say burning hot (150°C, no margin) for a D2PAK at 1W, to comfortably dissipating 5W (on a multilayer board). So, easily a 5x improvement. For thru-conduction, consider that, because laminate is so bad thru-plane, it pays to spread the heat out first, and then stitch it together. I mean, do both where you can, of course -- but you'll get much more heat dissipated through the laminate itself (without vias) when it's spread over a wider area. This can be good enough for a few watts on a 2-layer board without vias (topside pour only), or a 4-layer board has thin enough laminate to the nearer inner plane that the same is true for a minimal footprint. Indeed, inner planes are quite effective heatsinking, which goes for trace ampacity as well, hence why IPC-2152 asks about plane area and height.As for thermal vias, they increase the thru-conductivity massively: a modest grid of them increases thru-conductivity by, oh I forget how much anymore, 20x or something? So, with them placed near or under the component, the hottest points can be communicated to far layers, where they are able to spread out without having to be carried through any thickness of laminate. Vias can be filled with solder for a modest ~2x improvement (less if the via is small, or plated-up copper is already fairly thick, i.e. 2oz+ inside the hole), assuming no issues from solder wicking/floating. (Fairly safe to do on D(n)PAKs I would say, but maybe worth avoiding for SON/QFN/etc.)As for solder fill, you could get this say by using regular-dimensioned vias (i.e. normal pad size and soldermask opening), exposing the bottoms to wave soldering. Or using excess paste on the top, or paste-in-hole, so they wick up during reflow. Use modest or large size vias: 0.5mm i.d. seems a good combination of density and solderability. Conversely, to discourage solder wicking, use small (<= 0.3mm i.d.) vias, and choke down the soldermask to minimum clearance around the hole (typically 3 mil expansion from hole edge). Also, lead-free wicks less than leaded.Note that solder-filled vias may be bumpy on the free side, which makes heatsinking more challenging. If it's the kind of build where you have passives on the bottom anyway, you'll use a one of those squishy thermal pads to smoosh around them and it's fine either way; conversely, if you're expecting to, say, stick it down with a thermally conductive self-adhesive pad, or just a much thinner (squishy) pad, or just straight up grease -- you're going to have a bad time [if the solder's sticking out].Oh and thermals to vias: useless, turn that off (the attached rule includes this). The main exception, I would think, is if you're using them as test points, and need the thermals to facilitate soldering in debug wires -- in which case, you might consider converting them to free pads, so they dodge the rule. Or use SMT pads on whatever side is accessible, good for tacking on wires -- or probing on bed-of-nails in production.As for placement of thermal vias: near the component. Additional stitching away from the component does very little, you've already equalized the temperatures well enough, you're hardly going to net any lower thermal resistance out there. Or put another way: the vias closest to the component are the most important, and those distant are proportionally (quadratically? exponentially?) less so. Same goes for current sharing, you aren't doing anything by using huge fucking patches of vias, you're just turning your board to swiss cheese and probably reducing overall cross section in the process. (Especially so on multilayer: mind the negative space around the vias!) Just one or two rows of vias is adequate for either purpose.Speaking of which, I've done this before, on a multilayer design: I had power connections routed under a complex QFN (multi pad), I used a quincunx of vias per pad and set their inner-layer pads equal to diameter (Top-Mid-Bottom pad stack) so the inner polys can get as close as possible. This allowed the pours to weave inbetween, rather than be almost completely cut off by the pattern. (Note that unconnected pads are removed on gerber output, so normally the inner clearance is extra. Put another way: I'm doing that step manually to solve a tight routing issue.) (Note also, fab tolerances to inner layers are cumulative, so, fairly poor. Namely, layer registration adds with drilling tolerance. I set the inner clearance to account for this!) Finally, the vias were quite small (8 mil), and reduced soldermask clearance (i.e. to the hole edge, rather than pad edge) to avoid wicking.Also one final note, about soldermask: either fully tent, or keep open. Partially tented, traps gas and generates voids in the solder joint. Not good. Of course, full tenting is a PITA in most any design, and sacrifices solder joint area besides -- so the preferred choice is none. That doesn't mean you need a whole pad exposed on the backside -- reduced solder mask (using expansion rule from hole edge) is a nice compromise. It's very poorly solderable (it's not likely to pick up solder during wave), and it's very unlikely to get clogged with mask. It's still not even useless as a test point, actually: for 0.5mm+ vias, you can comfortably get a wire inside, and the wire carries heat into the hole. Also, if it fills with solder due to wicking from the top side, it's likely to stick out much less (it's not forming a meniscus across the full bottom pad), making thin thermal pad / flush mounted heatsink use easier.Tim

author: ricko_uk
author_rank: Super Contributor
timestamp: May 05, 2022, 08:31:59 pm
content: Thank you oz2cpu and also Tim for the very detailed explanation, much appreciated as always!!! As well as the RUL file.Lots of useful tips to incorporate in the design. I will post it once done.Thank you again!

author: Geoff-AU
author_rank: Frequent Contributor
timestamp: May 16, 2022, 07:01:21 am
content: Quote from: T3sl4co1l on May 05, 2022, 08:00:24 pmBrilliant post, but I am left with a philosophical dilemma. When does a via become a regular PTH?Thermals on vias seem a bit silly to me. Vias on PTH (eg for 0.1" connectors where some of the pins are connected to ground plane) are vital. I can't tell you how many times I've sworn at hardware engineers for not doing thermal reliefs on 0.1" header footprints. It's not so much soldering that's the problem, butdesoldering. Bloody impossible on 6+ layer boards where you may have multiple ground planes all providing excellent heatsinking to the inner layer.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 16, 2022, 09:14:02 am
content: Vias are plated through holes, that's how they work.If you mean as a THT pad, the only difference is whether you stick something in it before soldering. Which is going to be challenging under 0.5mm i.d., and I think the smallest you usually see is 0.8. Hm, there are 1.27 and 1mm pitch headers available in THT, I forget offhand what hole size they use -- that's probably the practical limit.And yeah, most any kind of soldering on multilayer gets difficult without extreme heat (iron >400C?) or preheating. Even if you don't have a proper hot air machine or board preheater, a hot air gun can be used to help out -- keep it at enough distance, or keep it moving, so it doesn't burn anything: typical one will be MUCH hotter than anything on a PCB should get, so don't use it up close and still. Be patient, it takes minutes of heating for the board and components to come up to temperature. In this way, you can even do SMT (reflow) soldering with a generic hot air gun, but it's a heck of a lot easier to screw up is the thing (sit still for just a little too long).Tim

author: Geoff-AU
author_rank: Frequent Contributor
timestamp: May 16, 2022, 10:21:04 am
content: Quote from: T3sl4co1l on May 16, 2022, 09:14:02 amOf course. I was tongue in cheek, you could technically call every PTH a via but I wouldn't. For me, PTH is something you plan to stick a component in and apply solder. A via's primary job is swapping layers for a trace. Mechanically, they are interchangeable... it's purely semantics. Test points are for probing or soldering things to temporarily, of course a via can be used in a pinch but test points come with silkscreen labels which makes finding it easier. Anyway, it becomes a religious argument after a while.I've had boards that resisted even preheating with hot air or a radiant PCB heater from underneath. Lead-free solder doesn't help. Some boards just want you to curse them enthusiastically before they let go. Sometimes getting the header out is OK but you'll never wick the solder out. Need to find a PCB drill and a hand chuck.... more cursing.

author: ajb
author_rank: Super Contributor
timestamp: May 16, 2022, 04:11:54 pm
content: Quote from: T3sl4co1l on May 05, 2022, 08:00:24 pmTo add to this, in terms of helping to intuitively understand the thermal dynamics, it's useful to remember that thermal behavior is analogous to electrical behavior.Heat flux ~= currentTemperature ~= voltageThermal resistance ~= electrical resistanceThermal mass ~= capacitanceAnd with those equivalencies, Ohm's law holds.So if you consider that the thermal relief spokes add a fixed amount of thermal resistance to the path between the package and the ambient via the PCB, then it's easy to see that the temperature rise across the thermal relief will be proportionally low with the relatively low heat flux induced by the package. On the other hand, the much higher heat flux available in the soldering process results in a much higher temperature difference. Of course reality is more complicated than this, because you have multiple heat paths, and there is some thermal resistance in the soldering equipment as well as time component via the thermal mass of the various components, but you can use the same basic principles to expand the model to whatever level of complexity you need.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 16, 2022, 06:30:03 pm
content: Yup. Thermal flow has the advantage that there's no wave effects*, just diffusion, so it's very easy to calculate. Even in bulk, it's just applying Ohm's law to volumes; in general you might need to integrate over many small volumes, but a lot of practical problems can easily be broken down to flat or linear geometry that can simply be added up. And I mean adding up by hand, few pieces -- like spokes and pours.So like with spokes, the pad can be considered ideal (unipotential), the spokes are just rectangular strips, and the spoke-pour transition is complex (think of it as a transition between 1-D trace and 2-D pour) but we can approximate the transition region as a circular section with some fixed resistance and skip having to compute it every time.The actual value of the transition region will go something like inverse or logarithmic with radius, in turn is given by the scale factor of the spoke width and spacing. So it only needs to be computed once, then scaled appropriately.*Not until such energies as explosive shockwaves; or in free space, relativistic energy densities. Indeed, it turns out nothing is linear, there are always limits; but obviously this particular limit is very safe to ignore for our purposes.Tim