Z80 Databus and /WR and /RD timings - Page 1
Forum section: electronics / projects

author: JonathanHerr
author_rank: Contributor
timestamp: August 03, 2018, 02:39:47 pm
content: Forgive my noobatude, but there's something I can't wrap my mind around when it comes to some Z80 computer designs of yesteryear and today.That something is the timing of the main Z80 data-bus, and the use of the /RD and /WR lines to buffer said aforementioned datalines.I'll start with the oldest, and that's the ZAP Z80 computer courtesy of Steve Ciarcia. He uses the /RD line to buffer his data input/output chips... and I'd be all well-and-good/ready to use that...Except for the more modern Z80 computer builds using the /WR line as the selector for the direction of the data line buffer.I've also looked up/at the datasheet and it too says use /WR as the direction-selector... (mind you tis a '83/'84 era z80 datasheet, but it should work for the speed and vintage of chip i'm using...)The main questions i have are why did Mr. Ciarcia design his computer seemingly backwards of everyone else, or if not backwards, what's allowing him to /use/ said seemingly-backwards buffering methods?This question is one that's been bugging me for quite a few months, so any help would be appreciated.

author: bson
author_rank: Unknown
timestamp: August 03, 2018, 03:40:45 pm
content: Do you have a schematic? Polarity depended on what buffer chip was used and what pin /RD was connected to. As you can see in the example below with 8212's, which had dual complementary data select inputs, in one direction RD was input to pin 1 (/DS1) while pin 13 (DS2) was pulled high, in the other direction it was input to pin 13 while pin 1 was pulled low. (Where RD is the inverted /RD.)

author: bson
author_rank: Unknown
timestamp: August 03, 2018, 03:48:54 pm
content: By the way, the above schematic is found on page 104 ofhttp://www.pestingers.net/pdfs/other-computers/build-your-own-z80.pdf

author: JonathanHerr
author_rank: Contributor
timestamp: August 03, 2018, 09:35:56 pm
content: Its not necessarily the polarity of the signal, (RD vs /RD) that the issue/confusion arises from. Its the usage of the RD signal in the above-mentioned diagram, yet in other datasheets and designs online, they're using the /WR line instead.In the datasheet provided by Zilog,http://bitsavers.trailing-edge.com/components/zilog/_dataBooks/1983_84_Components_Data_Book.pdfon page 31, it says:QuoteSo the questions boil down to:How does Steve's design work when using the /RD line instead of the /WR line... and why exactly is it /known/ that when its not doing a /WR cycle, its assumed to be a /RD cycle?Does it have something to do with the /MREQ line as well??Like when /WR is inactive (1) and /MREQ is active (0), that means its pretty-much-guaranteed to be a read cycle instead of a write?

author: kizmit99
author_rank: Regular Contributor
timestamp: August 03, 2018, 11:12:03 pm
content: Quote from: JonathanHerr on August 03, 2018, 09:35:56 pmYes, the "simple" Z80 bus cycles are defined by 6 signals: !M1, !MREQ, !IORQ, !RD, !WR and !RFSH.An understanding of the way these signals interact will be critical to understanding any Z80 design.I would recommend getting a pdf copy of the Z80 CPU Manual published by Zilog. It's a wealth of information on the Z80 CPU. I know it's available online, but I don't have a direct link handy.Hope that's helpful...

author: JonathanHerr
author_rank: Contributor
timestamp: August 03, 2018, 11:23:25 pm
content: I thought i linked to a Zilog Z80 pdf file a few posts back?http://bitsavers.trailing-edge.com/components/zilog/_dataBooks/1983_84_Components_Data_Book.pdf

author: kizmit99
author_rank: Regular Contributor
timestamp: August 03, 2018, 11:47:58 pm
content: That appears to be a book of datasheets on the various Zilog parts, not the book I was referring to...This link appears to be a (2004) copy of the book I'm referring to:http://www.z80.info/zip/z80cpu_um.pdfThe pdf I have is copyright 2016, but I doubt much changed after 2004

author: JonathanHerr
author_rank: Contributor
timestamp: August 04, 2018, 01:13:56 am
content: The thing that always throws me a bit about those timing-diagrams is both the multitude of interwoven dependencies and having to keep flipping between the diagram and the table to figure out how the timings go.(EDIT) Also, when i'm looking at the datasheet, I can see how the data input/output lines are sampled by the cpu at certain times (opcode fetch sampled at the beginning-rising-edge of the T3 clock-cycle.. But I'm still a bit stumped by how an inverted /WR signal can become effectively a /RD-like signal.

author: kizmit99
author_rank: Regular Contributor
timestamp: August 04, 2018, 04:00:14 am
content: Ok, I think, perhaps, you're mixing two concepts...Looking at Data Bus buffers, the Z80 basically requires that the /RD signal be used to control the direction of this/these buffers. You cannot rely on the /WR signal, because the Z80 will be driving the data bus when the /WR signal is both high or low (look at T2 of the Memory Write cycle for example). The /RD signal would be appropriate to use because the Z80 only drives the bus when /RD is high.The /WR signal is appropriate to use as a latch input to the actual memory (or I/O) chip (Data is stable before, during and after the /WR signal going active).Where are you seeing /WR being mentioned as appropriate for bus direction control?Even the doc you linked specifically states "/RD. -- The addressed I/O device or memory should use this signal to gate data onto the CPU data bus."

author: JonathanHerr
author_rank: Contributor
timestamp: August 04, 2018, 05:41:13 am
content: So you're saying that I'm conflating the idea of latching data (using /WR) and buffering the data? (using /RD)?

author: bson
author_rank: Unknown
timestamp: August 04, 2018, 04:23:50 pm
content: Quote from: JonathanHerr on August 03, 2018, 09:35:56 pmIt's implicit: when /RD is asserted the CPU isn't driving the data bus and it expects something else to provide data. When deasserted it might be driving the bus and nothing else should be./WR is a memory write strobe, not a bus direction indicator, so the CPU will be driving the bus a little bit prior to it. If you look at Fig 4.0-2on p.20 in the MOSTEK datasheet (http://datasheets.chipdb.org/Mostek/3880.pdf) you'll see there is data out on the data bus before /WR is asserted. This means you can't use it for buffer direction since this would result in an overlap where two outputs (buffer and CPU) drive the bus concurrently.Basically, Ciarcia does it right.

author: kizmit99
author_rank: Regular Contributor
timestamp: August 04, 2018, 04:34:29 pm
content: Quote from: JonathanHerr on August 04, 2018, 05:41:13 amYes, I think so...Quote from: bson on August 04, 2018, 04:23:50 pmAgreed.I am still curious though where you (OP) are seeing an example that uses /WR to control direction of the data bus buffers/transceivers? (Because unless something more subtle is going on, this would seem to be a non-starter)

author: JonathanHerr
author_rank: Contributor
timestamp: August 04, 2018, 06:40:26 pm
content: Well now i'm feeling like quite the fool... I swear i saw a hobbyist design somewheres that used /WR as a direction 'strobe'...