TZ2340 Frequency Counter - Page 1
Forum section: electronics / projects

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: June 16, 2018, 10:57:21 am
content: Just wanted to share a project I have been working on because for something so small it's been a lot of work.TZ2340 is a 100MHz reciprocal frequency counter module based on the following components.- Lattice MachXO3 1280 LUT FPGA/PLD? in a WLCSP36 package- 10 MHz Taitien 500ppb VCTCXO- MAX5482 10 bit digital potentiometer to do the frequency pulling on the clock.In the image below is the tz2340 sitting in the test jig I made with these really neat (expensive) right angle pogo pins.The module uses the 10MHz reference for counting. The gate and counting registers are all 32 bit wide giving max gate of about 429 seconds for frequencies below 10 MHz. The MachXO onboard PLL can be enabled via SPI config to multiply the reference clock by 10 giving the109 digits of precision (for shorter gates times) as seen in the image below.The next todo on the HDL front it finish the 1PPS input tracking such that the reference clock can be calibrated against GPS, that's the main purpose of the MAX5482. Although I'm already thinking to move to a DAC in the next revision for a programmable voltage reference.The module itself is a standard 2.54 pitch x 7.62 wide DIP style with castellated edges. The crazy new stuff for me here is the 0.4mm pitch BGA and the nail biting reflow of it in my toaster oven.. so far so good.[edit : Thanks mino-fm for pointing out the number of digits error]

author: mino-fm
author_rank: Regular Contributor
timestamp: June 16, 2018, 04:23:22 pm
content: I'm sorry, but I can't follow your calculation of 10 digits within 10 s. The frequency of reference clock is 100 MHz = 1e8, which will give you 8 digits within 1 second. So you have to wait 100 s to get 10 digits.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 16, 2018, 04:51:41 pm
content: For really high resolution like 10 digits it usually needs either an analog interpolator to get better time resolution or using a time stamping mode to look at more signal transitions. It depends on the signal which way (or maybe both combined) works or gives the better results. However due to the math involved time stamping mode is more suitable for use with an µC than an FPGA.

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: June 17, 2018, 12:00:58 am
content: Quote from: mino-fm on June 16, 2018, 04:23:22 pmThanks for spotting that. I've corrected my original post above.Quote from: Kleinstein on June 16, 2018, 04:51:41 pmYes I was reading about analog interpolation methods but kind of ran out of room on this designDigital interpolation on the other hand is a cleaver trick that I might be able to incorporate and is described in this paper.https://www.febo.com/pipermail/time-nuts/attachments/20071201/e7833af5/attachment.pdfBut for now I'm just looking to phase and frequency lock the VCXO to an external PPS, or at the very least provide calibration through the SPI interface.

author: mino-fm
author_rank: Regular Contributor
timestamp: June 17, 2018, 12:06:12 pm
content: A reciprocal frequency counter does not need a constant gate time of 1 or 10 s. So it doesn't need a reference frequency of exactly 10.0000000 MHz.For calculation of the result Fin it needs the number of incoming impulses (Nin), the number of reference pulses (Nref) and the exact reference frequency (Fref) which can be 10.000032, 9.9999975 or 10.000012 MHz. To get high resolution/accuracy the counter has to count these impulses for a minimum time intervall (>= 1 s for 8 digits e.g.) which is detected synchronously to input pulses. Input frequency Fin is calculated as: Fin=(Nin*Fref)/Nref.The classic way to get Fref is to stabelise it and look at it as a constant. Therefor you need a VCTCXO, a high resolution DAC und an 1 pps signal of a GPS modul and some internal/external logic/counter.A more simply way is to assume that the 1 pps signal is constant. Adding another counter (24 – 32 bit) and using the 1 pps signal as a capture signal, you can measure Fref every second and do the calculation of Fin by using this value.As known, 1 pps signal has a jitter of about 20 – 50 ns so for high accuracy you cannot use it directly. But the moving average value of pps signal (>= 100 s) will be sufficient to reduce the jitter below 1 ns. This way 9 digits resolution should be true.To proof this method for the first time I used an ATmega162 which has two independent counters und capture units:http://mino-elektronik.de/fmeter/fm_software.htm#bsp2For calculations it is important to use double values (64 bit).Today I'm using STM32F4xx controllers. They have more counters as needed and an internal PLL circuit to generate 168 – 180 MHz for Fref. CPLD, DAC or VCTCXO are not needed.For higher resoultion a TDC7200 offers an equivalent Fref of >= 10 GHz which means 10 digits/s.I hope you can extend your CPLD by another counter for 1 pps evaluation.

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: June 17, 2018, 09:50:11 pm
content: Quote from: mino-fm on June 17, 2018, 12:06:12 pmYes, moving average is the plan.Quote from: mino-fm on June 17, 2018, 12:06:12 pmYes I've read a little on the TDC7200. MAX35101 is another, resolution down to 3.8ps, but slower startup with 8us min timing. I think Intersil also make T2D's but I've not looked at them much... Really interesting chips. Might be my next project now that this one is nearing a conclusion.Anyway the CPLD is not yet half utilized so should be plenty of room to finish the PPS sync. 1200 LUTs ought to be enough for anyone