hybridfree/eevblog-posts huggingface dataset:
Using Altium designer with Actel Igloo Nano - Page 1
Forum section: electronics / general

author: djsb
author_rank: Super Contributor
timestamp: August 06, 2011, 11:03:02 am
content: The video on FPGA's has sparked my interest in using Altium Designer with Actel's Igloo Nano FPGA. I have a few questions1/ Can the chip be programmed from within AD10 using Altiums JTAG tool? or can it only be programmed using Actel's tools?2/ Can any of Altium's software platform be used with the chip and does live design work with it in a similar way to the nanoboard 3000.3/ I'm assuming that AD10 has all the required schematic symbols and footprints for this device (suppose I should just have a look).Anything else I should be aware of? These chips look very good for small designs apart from the PITA packages they come in.Thanks.David.P.S What extra tools would I have to install alongside AD10 for a start (similar to Webpack for the Xilinx FPGA's).

author: EEVblog
author_rank: Unknown
timestamp: August 06, 2011, 11:25:46 am
content: Quote from: djsb on August 06, 2011, 11:03:02 amSorry, I only know the answer to #3. Yes, it has the libraries, I used them in that video, the symbols and footprint are direct from the Actel library.I have not actually used AD with Actel Igloo's before, but I know people who have at Altium. Before I left I'm not 100% sure if all the Actel devices are supported in terms of JTAG and programming etc, but I'm sure at least some are. If they are supported, then yes, the Altium DT-01 JTAG programmer will handle them. I remember reading on the Altium forum that some people have had trouble and/or are were waiting for the latest Actel support. Worth asking Altium direct.Yes, if supported, it works exactly how the NB3000 etc works and the Software Platform etc.Dave.

author: daedalus
author_rank: Regular Contributor
timestamp: August 07, 2011, 10:34:00 pm
content: Yep, you can do actel igloo nano parts with altium, you just need to download and register the vendor tools.
Design For Manufacture - Page 1
Forum section: electronics / general

author: m4l490n
author_rank: Contributor
timestamp: July 11, 2011, 07:04:39 am
content: Hi everybodyI'd like some one to help me about what tools to use in ALTIUM designer in order to get a board in a panel, specifically, how do I put the routing slots? should I do this at the embedded board array or at the camtastic files? Thanks!

author: corona
author_rank: Newbie
timestamp: July 12, 2011, 07:02:49 am
content: You can do this a number of ways, it more comes down to asking your manufacturer what they'd prefer. Typically though you use either a mechanical layer or the keepout layer to place lines and/or arcs to define board outlines. If it's a curved line, manufacturers will usually route it without asking as there's not really any other option for them.For panelisation, I usually prefer to do this in a separate pcbdoc and use the place->embedded board array command to place panel, and you can again place extra info on a mechanical layer to show where you would like snap points etc. I only ever use camtastic as a tool to check exported gerbers look right, I don't do any panelisation myself in it. This is just my personal preference though.Just to reiterate though, no amount of documenting on mechanical layers can replace talking to the manufacturer to check they understand what you're asking for. You should also ask for how much clearance they want between two boards in a panel while you're at it.Andrew
Nanoboard NB1 availability - Page 1
Forum section: electronics / general

author: djsb
author_rank: Super Contributor
timestamp: June 04, 2011, 11:35:26 am
content: I'm on the look out for a Nanoboard NB1 that I can use at work (a UK university)for playing around with. I can't afford a newer NB2 (unfortunately) as I will be paying for this myself. Does anyone know where I can get hold of one? I've seen the occasional one on Ebay but they have been too highly priced.Thanks.P.S I have Altium Designer already so that's not a problem.

author: EEVblog
author_rank: Unknown
timestamp: June 04, 2011, 11:12:13 pm
content: Altium haven't made the NB1 for at least 4-5 years.They still have a couple lying around for support purposes, but I'm not sure they would part with them because they are now so rare.Dave.

author: TLDesign
author_rank: Newbie
timestamp: June 29, 2011, 06:16:46 pm
content: Maybe go for the NB3000 or an oldskool live design kit? The live design kit is a little outdated, but you can still play packman on it :-P. If it's just to play around, that wouldn't be a problem I guess?
Horowitz on the desk - Page 1
Forum section: electronics / general

author: s.mosfet
author_rank: Contributor
timestamp: June 20, 2011, 09:07:55 am
content: I saw "the Art of Electronics" on your desk, at altium.Is it useful for your job?and for what particularly?

author: EEVblog
author_rank: Unknown
timestamp: June 20, 2011, 09:19:02 am
content: It's a useful reference for any job in electronics.Dave.

author: Chris_Knudsen
author_rank: Newbie
timestamp: June 20, 2011, 11:39:02 am
content: I have the 2nd edition on my shelf.I loan it to all new hires, then leave it up to them to buy their own.Are there new editions / how are they?-Chris

author: Simon
author_rank: Unknown
timestamp: June 20, 2011, 11:47:20 am
content: there has been talk of a third edition to supplement the second for some years

author: shadewind
author_rank: Frequent Contributor
timestamp: June 20, 2011, 10:35:45 pm
content: Sorry to go off topic here... but this is the Altium Designer forum...

author: joelby
author_rank: Frequent Contributor
timestamp: June 21, 2011, 02:15:03 am
content: Quote from: shadewind on June 20, 2011, 10:35:45 pmAh, you see - the book was seen on a desk used by an Altium designer.

author: Mechatrommer
author_rank: Super Contributor
timestamp: June 21, 2011, 01:32:53 pm
content: i never saw anything inside aoe on how to make things like altium designer.

author: Zad
author_rank: Super Contributor
timestamp: June 29, 2011, 06:16:14 pm
content: Quote from: Mechatrommer on June 21, 2011, 01:32:53 pmSounds like someone got out of the wrong side of bed today!
Fanout anyone? - Page 1
Forum section: electronics / general

author: TLDesign
author_rank: Newbie
timestamp: June 29, 2011, 12:45:09 pm
content: Hi all.I'm currently working on a PCB project that contains an Altera Cyclone III with the 484 BGA package. Now I'm trying to figure out how the fanout option works as used on the Nanoboard 3000 (in the examples folder). Could anyone explain how the auto fanout works? I can't get it to work. On this moment only two of the four layers are fanned out when I try the auto fanout mode.Thanks in advance!
Report single pin nets on Heirarchical schematic - Page 1
Forum section: electronics / general

author: tesla500
author_rank: Regular Contributor
timestamp: June 21, 2011, 07:28:36 pm
content: When I use the report single pin nets tool on a hierarchical design, only the current schematic is reported, showing nets that go to other schematic levels as being single-pin when they're not. How do I get this tool to work?Regards,David

author: thmjpr
author_rank: Regular Contributor
timestamp: June 21, 2011, 11:34:35 pm
content: Can you explain what kind of hierarchical design (device sheets, sheet symbols)? Or maybe an example screenshot.If I create a single pin net and connect that net on another schematic page, its ok.Or if I connect to a sheet symbol, and connect the port to something, also ok.Also, not sure if it helps but you should see the same info when doing a Project > Compile Project, and looking at error messages. Assuming you've flagged it under project options > error reporting.

author: tesla500
author_rank: Regular Contributor
timestamp: June 22, 2011, 01:00:13 am
content: This is a hierarchical design using sheet symbols. Something likehttp://wiki.altium.com/download/attachments/3080261/sheet+symbols.png?version=1&modificationDate=1228187099001.Thanks for the suggestion to check the setting in project options. That works properly for identifying single pin nets, but the Reports | Report single pin nets command doesn't work right, the report it generates appears to only look at the sheet I had open when I ran the command. The compilation error checking is fine though, I think I'll just use that.Regards,David

author: maxseeley
author_rank: Newbie
timestamp: June 24, 2011, 04:08:24 am
content: No, there is some other issue in the way the project is setup, in the project options, or in the way you are labeling your nets. If you want me to take a look at it, please email your project file to me or post it if you are comfortable. The reason are there are numerous things that could be causing this.
Choosing footprint from library. - Page 1
Forum section: electronics / general

author: flodins
author_rank: Contributor
timestamp: June 11, 2011, 01:45:58 am
content: HiI have a problem with adding items from my own library for which I defined many footprints. On the schematic always lands with a default value, unless I select the Place but it is too much clicking. If you add the built-in library, this problem does not occur I can grab a footprint that interests me and this will be set on the schematic.Do you know any solution? Something had to switch in my library?I think that the movie clearly shows allhttp://flodins.info/footp.mp4

author: thmjpr
author_rank: Regular Contributor
timestamp: June 11, 2011, 05:08:54 am
content: Weird, don't see that problem in AD9.3. Is this AD10?All I can think is create a new library project, copy a part over, compile/install and see if it persists.

author: flodins
author_rank: Contributor
timestamp: June 11, 2011, 10:12:06 am
content: this is AD9

author: armandas
author_rank: Frequent Contributor
timestamp: June 11, 2011, 12:01:13 pm
content: Did you specify the correct footprint in your schematic library?

author: flodins
author_rank: Contributor
timestamp: June 11, 2011, 12:08:41 pm
content: yes, you can see that when click place it works, only grabing from my libraries does not work grabing from build in librares is ok

author: FreeThinker
author_rank: Frequent Contributor
timestamp: June 11, 2011, 05:05:18 pm
content: I've never used altium but did you save the footprint with a value attached (ie when you designed it) if so then that would most likely be the problem. If not and altium is assigning a random value (when saved ) then it is indeed strange.Edit < Just re watched the video and you have got the value item ticked in the parameter list. Does this not display the value?>
tented via cleverness, with testpoints.. thought I'd share - Page 1
Forum section: electronics / general

author: dh
author_rank: Newbie
timestamp: June 07, 2011, 01:08:39 am
content: Messing around with tented vias, I came up with a decent solution to Shift-F, Select All Vias, Force Tenting and the like:Using rules, you can make a SolderMaskExpansion rule like this:Code:SolderMaskExpansion+SolderMaskExpansion_Via+SolderMaskExpansionSolderMaskExpansion is the default (5mil expansion), and SolderMaskExpansion_Via isIsVia And (Not IsTestpoint)Expansion = -5000milThis tents all vias, but leaves testpoints clear!
Altium polygon pour weirdness - Page 1
Forum section: electronics / general

author: shadewind
author_rank: Frequent Contributor
timestamp: March 28, 2011, 04:10:19 pm
content: I'm designing a board in Altium which uses a 0.5mm QFP part. I have a ground pour on the top layer but the polygon connects for the pads on this chip end up pretty weird:I can see what's happening here. It cuts off the "horn" which is desirable but the polygon connect "track" doesn't hit the polygon the right way. Does anyone know a way around this?

author: Hypernova
author_rank: Unknown
timestamp: March 28, 2011, 05:21:11 pm
content: Easiest way is to route out a short track to meet the polygon.

author: RayJones
author_rank: Frequent Contributor
timestamp: March 28, 2011, 08:00:05 pm
content: Yes, use deliberate tracks, and ensure the polygon will seamlessly pour over these tracks.There is an option name for this but it eludes me right now.

author: EEVblog
author_rank: Unknown
timestamp: March 28, 2011, 11:33:38 pm
content: That is a known issue with the polygon pour, as yet not fixed.Yes, the workaround is to lay a track.Dave.

author: VIPR
author_rank: Contributor
timestamp: March 29, 2011, 10:49:44 pm
content: I'm really surprised they did not fix this in the new 10.0 version that just came out to the public 2 weeks ago. They certainly did improve the polygon manager in the newest version--along with many other things. I would certainly prefer proper performance of exiting functions over new functionality.

author: EEVblog
author_rank: Unknown
timestamp: March 30, 2011, 09:41:01 am
content: Unfortunately for the PCB/schematic users their focus is now more toward content and the Live site than the core tools.Dave.

author: tesla500
author_rank: Regular Contributor
timestamp: March 30, 2011, 05:05:28 pm
content: It looks like the polygon is trying to maintain clearance to the GND node. I guess it's because the RST track is so close that the thermal relief can't be put in place, and the polygon algorithm is cutting off the edge so as not to produce a sharp "point".In the polygon options, check that "pour over all same net objects" is selected. This may mess up thermal reliefs though.David

author: Hypernova
author_rank: Unknown
timestamp: March 31, 2011, 04:04:15 pm
content: Quote from: tesla500 on March 30, 2011, 05:05:28 pmIt won't, the effect you are thinking would be from "direct connect"<polygon connect style<rules.Now, there is in fact a way to fix this without drawing your own track, create a rule that apply to pads of that component+net+class combination and set it to direct connect. use "find similar" to help you build the rules for that pad. Tweak the rules carefully least you end up with a bigger cluster fuck than what you are trying to fix.
A!tium designer and thermal simulations - Page 1
Forum section: electronics / general

author: Varal
author_rank: Contributor
timestamp: February 19, 2011, 01:27:59 pm
content: Hey everyoneLong time no postI have a question to all those that work with altium designer and perform thermal simulations of their PCB's. Is it possible to do such a thing with AD (I know PADS can) or do you use externall software? And if so can you name that software?Thx for any answer

author: DaveW
author_rank: Frequent Contributor
timestamp: February 19, 2011, 10:28:27 pm
content: Don't know about AD, but with Cadstar we used to use Flomerics Flotherm which could accept quite a few formats and gave us really good results

author: EEVblog
author_rank: Unknown
timestamp: February 19, 2011, 10:35:07 pm
content: AD does not have any form of thermal capability built in.I am aware of some who export various things and use external tools, but I don't know the exact details.Dave.
PCB Artwork scaling - Page 1
Forum section: electronics / general

author: Wendy Moss
author_rank: Newbie
timestamp: September 25, 2025, 10:41:10 am
content: Hello. I have been using Diptrace V2.4.0.2 for about 5 years now. I have no issues except one. My usual operating system is Win10However when I need to print an artwork for laser / toner deposition, I Have to add +5% to the scale.. eg if the art is defaulted to 100% and I print that, the artwork is - 5%, thus IC' pins spacing is wrong by 5%. Therefor I have to add +5% to make the artwork the correct size. If I use Win 7 then NO scaling is necessary. Has anyone else had this problem... In the great scheme of things, I just need to remember to add +5% to the scaling, thus 100% becomes 105%. But it would be nice to know if there is a "Fix"Regards G8BZY

author: HwAoRrDk
author_rank: Super Contributor
timestamp: September 25, 2025, 04:53:00 pm
content: Sounds like a printer driver issue, as that is likely the only difference between the two scenarios.Might be worth making sure you have the correct paper size set - e.g. Letter vs A4. Check other settings are the same too.Have you tried looking at the printer driver settings to see if there's some system-wide scaling setting you can apply? Then you wouldn't need to remember to adjust it every time.

author: geggi1
author_rank: Frequent Contributor
timestamp: September 25, 2025, 07:15:17 pm
content: In my experience its a common problem with many printers.At work we have a expensive document center when printing from Autocad the print comes out at 95% of full scale.To remedy this I always do a test print of a known size usually a 100mm times 100mm square to calibrate in X and Y direction.

author: TimFox
author_rank: Super Contributor
timestamp: September 25, 2025, 08:58:24 pm
content: An example of a printer problem:At work, we had two printers on the network for normal text printing: an HP and a Lexmark, both worked properly with Word on Windows.Except: there was some confusion with the physical scale factor between the two units, so printing on one or the other printer actually changed the length of lines (in characters) resulting in damage to carefully-formatted prose.

author: PlainName
author_rank: Super Contributor
timestamp: September 27, 2025, 11:04:00 am
content: Could it be to do with Windows screen scaling. If one is using a high DPI screen and choosing to scale by, for instance, 5% to make the text readably large, maybe that's feeding through to the printer. Perhaps Diptrace is using a one-to-one pixel copy of the screen layout, and the scaling is messing with that.

author: Wendy Moss
author_rank: Newbie
timestamp: September 28, 2025, 04:18:39 pm
content: Hi good folk.Thanks for the replies, they all infer a printer driver error of some sort. What I cannot understand is why Win 7 is ok and Win 10 is not.As I am not a Computer "geek" by any sense of imagination, I was hoping for a "do this.. or do that" scenario,.. I will learn to live with it, as I have for the past couple of years. By the way the printer is a Samsung ML 2165. Not that it may help muchThanks again
PCB Modifications with a ground plane  - Page 1
Forum section: electronics / general

author: andybarrett1
author_rank: Regular Contributor
timestamp: June 05, 2025, 08:40:35 am
content: HiThank you for reading ....We are looking at modifying a PCB we designed about 6 years ago .... Just adding some 2 resistors and 2 LedsIt has a ground plane ..... We have placed the componants, connected with rat lines and autoroutedBut it gives more errors than we can document .....Question is do we need to remove the groundplane before autoroute or am i missing something hereThank You for any helpAndy

author: pvo317
author_rank: Newbie
timestamp: June 06, 2025, 12:15:23 am
content: Send me an e-mail to pvo317@gmail.com.Specify what you want to change.I'll try to make one.

author: HwAoRrDk
author_rank: Super Contributor
timestamp: June 06, 2025, 06:20:37 pm
content: Are the errors from the newly-routed traces clashing with the ground plane? Sounds like you might just need to re-pour the ground plane (Objectsmenu,Update All Copper Pours).The auto-router in DipTrace is not very good. I have never found it to be useful.

author: BloodyCactus
author_rank: Frequent Contributor
timestamp: August 08, 2025, 01:57:41 pm
content: Quote from: andybarrett1 on June 05, 2025, 08:40:35 amyou have to select the ground plane and have it re-pour so it floods and takes the new positions/components into account. diptrace does not automatically reflood the fills/pours.
Push and shove router is available - Page 1
Forum section: electronics / general

author: SergElectron
author_rank: Newbie
timestamp: August 20, 2024, 06:05:11 am
content: The new Beta version with push and shove router is available.https://diptrace.com/company/news/Other new features are IPC-2581 export and KiCAD netlist import/export.
DipTrace 5.0 Beta - Page 1
Forum section: electronics / general

author: SergElectron
author_rank: Newbie
timestamp: April 23, 2024, 01:05:35 pm
content: "Plugins, PCB Calculator, Planar Inductors, Digital SPICE Simulator, Via Stitching, Via Shielding, Export to PDF, Updating PCB from Netlist, etc..." are waiting for you in DipTrace 5.0 Beta.All features overview is here:DipTrace 5.0 Beta is ready for testing! Your feedback will be greatly appreciated.Download it now:https://diptrace.com/download/download-diptrace/

author: MarkF
author_rank: Super Contributor
timestamp: April 24, 2024, 02:54:42 pm
content: Are you a member of the Diptrace development team?And, can we ask you questions?

author: SergElectron
author_rank: Newbie
timestamp: April 25, 2024, 06:21:42 am
content: Quote from: MarkF on April 24, 2024, 02:54:42 pmYes, I am part of the DipTrace team. You can ask me or use thetechnical supportand theofficial forum.

author: MarkF
author_rank: Super Contributor
timestamp: April 25, 2024, 12:09:35 pm
content: It's good to have someone from the team on the forum.I do have a minor bug in version 4.3.0.5.In the 3D view, the zoom value is not always correct.If you zoom in and then 'Reset View', the zoom is not reset to 100%.Also when you zoom in, exit the 3D view and reopen the 3D view, the zoom is not reset.

author: SergElectron
author_rank: Newbie
timestamp: April 26, 2024, 02:09:37 pm
content: Quote from: MarkF on April 25, 2024, 12:09:35 pmThank you for the report. The first part of the problem is fixed for version 5.0 beta. The second part isn't fixed. I have added it to our bug tracker.
Coupled microstrip and other transmission line types in Altium - Page 1
Forum section: electronics / general

author: shadewind
author_rank: Frequent Contributor
timestamp: October 22, 2011, 01:09:41 pm
content: Hi,I'm using Altium designer for a board where some traces need controlled impedance, for example Ethernet trace. I'm not very good with this but from what I can tell, differential ethernet traces should be routed as coupled microstrip lines which has reduced impedance when compared to a normal single ended trace. The problem is that Altium does not seem to take this into account?Also, I can see no option for doing things like Co-Planar Wave Guides either. Am I missing something?

author: EEVblog
author_rank: Unknown
timestamp: October 22, 2011, 09:41:24 pm
content: I don't think you aren't missing anything, Altium Designer is quite poor in that area.It can do basic diff pair stuff (and don't marketing love to sell that as the be-all-end-all), but beyond that it's as dumb as a brick.It won't take polygons into account as ground planes for example, and it certainly is not field solver based.Dave.

author: shadewind
author_rank: Frequent Contributor
timestamp: October 23, 2011, 12:10:49 am
content: Yeah, I guess I'll just make manual rules for the traces in question instead.
Difficult times ahead for Novarm development team? - Page 1
Forum section: electronics / general

author: HwAoRrDk
author_rank: Super Contributor
timestamp: February 24, 2022, 01:01:54 pm
content: Am I correct in thinking that the company that develops DipTrace, Novarm, are a Ukranian company?If so, in light of current events, I imagine that there will be difficult times for them ahead. Hopefully any impact on their business and employees will not be severe. I give them my best wishes and hope they stay safe.

author: Zbig
author_rank: Frequent Contributor
timestamp: March 28, 2022, 02:45:50 pm
content: I think that's also true for (at least the part of) Altium's development team.

author: MadScientist
author_rank: Frequent Contributor
timestamp: March 28, 2022, 03:14:01 pm
content: They posted this on their forum“ Btw we are located in Dnipro - our primary task at the moment is to defend our cities, however we continue to work on DipTrace and plan to make a new version soon.”

author: Marathonman
author_rank: Newbie
timestamp: March 04, 2023, 02:43:20 am
content: Well it seems they are okay for the moment because I downloaded 4.3.0.4 and all is well

author: JPortici
author_rank: Super Contributor
timestamp: March 04, 2023, 05:05:06 am
content: They are planning to release 5.0.0 soonand yet they didn't increase the license price. Unlike altium (the programming team is also in ukraine)
WTF am I supposed to do here? Diff pair routing and DRC clearance problems - Page 1
Forum section: electronics / general

author: HwAoRrDk
author_rank: Super Contributor
timestamp: December 22, 2023, 04:27:42 am
content: For the first time I'm working on a PCB layout with PCIe differential pairs going to an M.2 socket. I'm pretty sure I've worked out all my trace widths and spacing correctly for 85 ohms impedance and set up the relevant net class parameters for the diff pairs.The diff pairs originate from and route to 0.5 mm pitch pads, but because my clearance rule is 0.85 mm, I get a ton of DRC errors because of unavoidable/inherent violation of clearances of traces to pads, copper pour to traces, etc, etc.I don't seem to be able to tweak any of the parameters (i.e. Clearance Details in Net Classes window) to get rid of the DRC errors. The only thing that had any effect (that of actually allowing the copper ground pour to attach to the padsat all) was setting 'SMD' to 'Copper' clearance to the pad-to-pad gap, 0.2 mm.WTF am I supposed to do here?Edit: oops, forgot to attach picture

author: HwAoRrDk
author_rank: Super Contributor
timestamp: December 22, 2023, 04:35:44 am
content: Oh, and one supplementary question: what should I be using for clearance around the diff pairs?One rule of thumb I've read in several places is 5 times the trace width from the centreline of the pair. But another rule I've read says 4 times the dielectric height (i.e. thickness of PCB pre-preg?).The former works out to be 1.04 mm (0.28*5-0.36) but the latter is 0.84 mm (0.21*4). The latter helps me more with the routing.
Pads Pattern for different PCBs - Page 1
Forum section: electronics / general

author: sairfan1
author_rank: Frequent Contributor
timestamp: September 17, 2021, 02:35:19 pm
content: I'm back to DipTrace after a long time, previously I had an issue with diptrace not sure if that is solved in newer version (or may be i did not know how to do that)For example I created a Pattern 1 x 8 Header and I set the pad properties likeShape: EllipseDiameter: 0.9mmWidth: 1.3mmHeight: 1.3mmNow I use this pattern in different PCB layouts, in PCB1 I wantdiameter: 1.1mmwidth: 1.6mmheight: 1.6mmIn PCB2 again i want different dimensions, how can i achieve that?In past I have been achieving this by selecting pads and set default pattern properties OR by setting manual dimensions but problem with this approach is that I loose manually set parameter each time I update schematic changes in PCB.
diptrace tutorial for library - Page 1
Forum section: electronics / general

author: Faringdon
author_rank: Super Contributor
timestamp: July 29, 2021, 03:36:52 pm
content: Hi,Any good tutorials/videos for diptrace?I am trying to create a library and put a Quad nand chip in it at the moment.

author: johnboxall
author_rank: Unknown
timestamp: August 03, 2021, 10:51:03 pm
content: See their mega tutorial pdf, it shows you how to create items.https://diptrace.com/support/tutorials/
Pad paste mask segmentation feature - Page 1
Forum section: electronics / general

author: HwAoRrDk
author_rank: Super Contributor
timestamp: May 14, 2021, 11:00:11 pm
content: I just upgraded to DipTrace v4.x (yeah, I know, after it's been out how long?), and one of the new features I've been trying out is the pad paste mask segmentation.Is it just me, or is it really frustrating to use? I've been attempting to make it do a 3x3 segment pattern for the large heatsinking pad of an ESP32 module (so I can have 4 vias in the pad at the junctions between the paste segments), but I can't get a satisfactory result. There's like a really narrow combination of settings (fill percent, segment size, segment gap, edge gap) thatalmostgets me to the 3x3 layout I want, but if I tweak it slightly in any way DipTrace just wants to do 2x2.It would be nicer if you could just tell it you want a fixed X-by-Y number of segments, rather than let it decide itself.
Panelization in DipTrace 4.1 (video) - Page 1
Forum section: electronics / general

author: novarm44
author_rank: Contributor
timestamp: February 12, 2021, 04:23:40 pm
content: Hi All,I have made a small presentation video how to use new panelization feature in DipTrace 4.1https://youtu.be/Atqf3S1XfmYThank You!

author: mcinque
author_rank: Unknown
timestamp: February 15, 2021, 06:03:29 pm
content: thanks!!!!
How to insert a background biptmap in Diptrace? - Page 1
Forum section: electronics / general

author: TERRA Operative
author_rank: Super Contributor
timestamp: October 02, 2020, 01:49:20 pm
content: I have a Tek PCB I'm currently replicating and I'm looking for a way to insert a background bitmap so I can use it to trace out the layout of the original PCB.Is this sort of thing possible in Diptrace?

author: mcinque
author_rank: Unknown
timestamp: October 02, 2020, 02:45:13 pm
content: adding an image it's possible without problems using the image button (attached)I neve tried to send it to a bottom layer to route over itI'm not at the pc now but I'll try asap and make you know my results

author: MarkF
author_rank: Super Contributor
timestamp: October 02, 2020, 03:13:28 pm
content: Simple.Just create a black-and-white image as a bmp or png file.Then, add the image to your top or bottom silkscreen as @mcinque pointed out.Be aware black will represent the image and white the transparent color.

author: mcinque
author_rank: Unknown
timestamp: October 02, 2020, 04:00:23 pm
content: Thanks MarkF

author: TERRA Operative
author_rank: Super Contributor
timestamp: October 04, 2020, 12:29:07 am
content: My image isn't black and white, it's a photo of a PCB so short of redrawing the PCB and component layout, to then re-redraw the layout in Diptrace, that method unfortunately won't work.

author: MarkF
author_rank: Super Contributor
timestamp: October 04, 2020, 04:41:31 am
content: Had a play around and this may give you a start (DipTrace 4.0.0.5):

author: TERRA Operative
author_rank: Super Contributor
timestamp: October 04, 2020, 04:48:01 pm
content: Oh cool, I'll give it a go.Thanks!

author: novarm44
author_rank: Contributor
timestamp: February 13, 2021, 04:54:50 pm
content: In 4.1 the raster image is available again. Place picture and choose "Keep Raster" instead of vectorizing.Raster image will be always at background layer. To temporarily hide it, you need to hide inactive assembly layer. To export it to gerber or DXF, you should vectorize it and move to necessary layer.
Moving from Protel 99SE to DipTrace - Page 1
Forum section: electronics / general

author: DTJ
author_rank: Super Contributor
timestamp: August 30, 2020, 12:12:00 pm
content: We think it may be time to update our CAD software. Our 20 year old Protel 99SE still runs well but we are starting to rely on different hacks to keep it running on later versions of Windows.DipTrace seems to be reasonably priced. We don't do anything too fancy but need a reliable & efficient commercial package.Has anyone moved from Protel 99SE to DipTrace and been satisfied?Thanks

author: Circlotron
author_rank: Super Contributor
timestamp: August 30, 2020, 12:14:45 pm
content: I am looking to buy an original copy of Protel 99SE.PM me if you are interested in selling.

author: bookaboo
author_rank: Frequent Contributor
timestamp: October 01, 2020, 02:09:41 pm
content: Quote from: DTJ on August 30, 2020, 12:12:00 pmI did many years ago and I have always been happy enough with Diptrace.

author: DTJ
author_rank: Super Contributor
timestamp: October 02, 2020, 01:40:12 am
content: Quote from: bookaboo on October 01, 2020, 02:09:41 pmThanks for the feedback. I have had a play with it and it does look good.
Autorouter too light on rules - Page 1
Forum section: electronics / general

author: Joel_l
author_rank: Frequent Contributor
timestamp: September 20, 2020, 02:00:51 am
content: I'm currently giving Diptrace ( 4.x ) another go ( have tried it in the past ). For the most part I can deal with the things it does differently from what I'm used to.I spent some time playing with the autorouter to see how good a job it does. As far as I can tell, it only applies some very simple rules from each net class, basically trace width and trace spacing. The problem is it only has one spacing for every thing. To be effective it needs, trace to trace, trace to via, trace to shape, trace to pad, and to really be good, net class to net class.If it had these things I would jump ship on the other two packages I have and go to Diptrace. Do these things exist and I just don't know where they are?

author: b_force
author_rank: Super Contributor
timestamp: September 30, 2020, 05:15:05 pm
content: Why would you want to use any autorouter anyway to begin with?
DipTrace 4.1 Beta Trial - Page 1
Forum section: electronics / general

author: johnboxall
author_rank: Unknown
timestamp: January 13, 2021, 12:54:01 am
content: "Interactive BOM, V-Scoring and Tab-Routing Panelization, Bulk Pattern Update, Expanded libraries, Automatic 3D Model Generation for All Families and a number of other improvements are waiting for you in DipTrace 4.1.DipTrace 4.1 Beta is ready for testing! Your feedback will be greatly appreciated."Download it now:https://diptrace.com/download/download-diptrace/

author: mcinque
author_rank: Unknown
timestamp: January 13, 2021, 02:25:47 pm
content: Great!
Diptrace Schematic - Page 1
Forum section: electronics / general

author: hansd
author_rank: Contributor
timestamp: April 19, 2020, 03:22:15 pm
content: Hi,I am interested in Diptrace but I have problems with the schematic side of things. How can I draw a multi page schematic file without having to use buses but only global labels etc?Please see file attached.

author: JPortici
author_rank: Super Contributor
timestamp: April 20, 2020, 10:51:01 pm
content: you don't need buses, you don't need global nets.assign the same name to a net and you are done

author: hansd
author_rank: Contributor
timestamp: April 21, 2020, 10:20:42 am
content: Tanks for the reply. How does one find components in this V4 library?
JLPCB Board Outline - Page 1
Forum section: electronics / general

author: NivagSwerdna
author_rank: Super Contributor
timestamp: September 16, 2019, 07:09:48 am
content: Hi DipTracers,I am trying to get my PCB design out of DipTrace into JLPCB Gerber Viewer and having problem getting their site to recognise the board outline (which is not rectangular so important).Normally I export the "Board Outline" Gerber as .GML and the manufacturer can then figure this out but JLPCB seems to struggle.Is there a trick to getting from DipTrace to JLPCB? Please can you tell me an extension name that would work. (I tried .GKO, .outline,... but still get errors in the JLPCB viewer although other online tools think the export if fine)ThanksNivag

author: MarkF
author_rank: Super Contributor
timestamp: September 16, 2019, 09:13:26 am
content: I just did one that was not rectangular and it came out fine.It was made of all straight lines. Nothing curved.I believe I read somewhere here that their on-line gerber viewer was not reliable.Maybe you should contact them and ask to manually check your PCB.My naming convention and the drill file had a .TXT extension

author: NivagSwerdna
author_rank: Super Contributor
timestamp: September 16, 2019, 09:19:29 am
content: That's super helpful thanks. They just cancelled my order so I will try again. I think I must have sent them board not board outline. The online viewer also displays some of my silk screen arcs incorrectly... I think that is their viewer.

author: MarkF
author_rank: Super Contributor
timestamp: September 16, 2019, 07:08:28 pm
content: That was my first PCB from JLCPCB.I normally useElecrow.About the same price WITHOUT having the order number plastered all over the board.(Just my inner OCD coming out.)

author: NivagSwerdna
author_rank: Super Contributor
timestamp: September 16, 2019, 07:12:04 pm
content: Quote from: MarkF on September 16, 2019, 07:08:28 pmMe too. Elecrow is my #1 choice but for larger boards JLPCB seems cheaper. My board is 170mm x 60mm.

author: MarkF
author_rank: Super Contributor
timestamp: September 16, 2019, 07:23:08 pm
content: Quote from: NivagSwerdna on September 16, 2019, 07:12:04 pmGood to know. Thanks.
Newbie: Text on Bottom Silk - Page 1
Forum section: electronics / general

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 06, 2019, 11:29:16 am
content: I have really confused myself.... when laying out a PCB you are essentially looking from the top down... so when you switch to the bottom layer you are seeing all the tracks etc reversed?When adding text to the bottom silk screen it appears to be the correct way around but when you fabricate it has to be reversed?I got a warning when exporting but having just got my PCB back it appears correct.... apart from.... one designator!Please can you explain how it is meant to work(When you look at the Gerber's are they meant to be forwards... Looking up at the bottom of the board?)Thanks

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 07, 2019, 11:29:08 am
content: So... my PCB arrived...The top image is 3D Preview in DipTrace... the bottom image is what arrived...Maybe the manufacturer tried to fix it silently for me and got one thing wrong?(Looks like the Rules Check didn't have Silk over Pad Checked by default either... I wonder if that check default changed in 3.3?).

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 07, 2019, 11:35:40 am
content: And here's the .GBO viewed athttp://www.gerber-viewer.com/Looks like this is a view from the top down through the board? So the text should really be reversed in this view?

author: OwO
author_rank: Super Contributor
timestamp: June 07, 2019, 11:40:52 am
content: Yes. You can see from the pictures that C3 was turned but C1 was not, so this was likely fixed manually. Gerbers are ALWAYS viewed from the top, so if it looks like that it's flipped.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: June 07, 2019, 11:52:56 am
content: Quote from: OwO on June 07, 2019, 11:40:52 amWow. They never even asked and it looks like I had some silkscreen overlaps too which they have tidied up. So... to get the right Gerbers out of DipTrace... Should... the checkbox be set or clear on export... and should... View... Flip Text Automatically... be set or clear? [It seems the defaults might be unsafe?]

author: HwAoRrDk
author_rank: Super Contributor
timestamp: June 09, 2019, 01:20:13 am
content: I haveView > Flip Text Automaticallyset, and this appears to cause theFlip Textbox in the Gerber export to actually be disabled and ticked automatically for all bottom layers.Never had any problems with silk screen text coming out wrong on boards. I don't recall ever changing that View menu setting, so I think it's the default.If you want to actually read the text on your bottom side, you can always doView > Mirrorwhich will give you the true view of looking at the bottom of a board.
Text fonts gone awry? - Page 1
Forum section: electronics / general

author: djacobow
author_rank: Super Contributor
timestamp: February 07, 2019, 04:49:35 am
content: I use Diptrace to make boards where aesthetics sometimes matter.I've been using TrueType fonts on the silkscreen and sometime on the mask layers to make "silver" text and it works great.Recently I upgraded to 3.x and also moved to a newly built PC. Now the Truetype fonts look really bad and pixelated but the built-in vector font is still fine. I'm not sure which change caused this. Has anyone else observed this?

author: djacobow
author_rank: Super Contributor
timestamp: February 07, 2019, 05:07:44 am
content: Okay, on more experimenting, it looks like the graphics mode matters. In windows GDI mode, it's fine. In OpenGL or Direct3D, they look really bad.I tried exporter gerbers and they look fine (and the same) regardless of graphics mode. So I guess this just a display issue.Still weird.
Potential Malware in DipTrace 4 MacOs - Page 1
Forum section: electronics / general

author: sleemanj
author_rank: Super Contributor
timestamp: October 06, 2020, 08:39:41 pm
content: Don't use 4, or Mac myself, but saw this mentioned on another forum I usehttps://www.geekzone.co.nz/forums.asp?forumid=73&topicid=277157Quote from: geekzone.forum.user

author: mcinque
author_rank: Unknown
timestamp: October 07, 2020, 10:43:52 am
content: Could be a false positive?

author: Electro Fan
author_rank: Super Contributor
timestamp: October 27, 2020, 08:20:25 am
content: Sort by date and look at the comment from about 2 months ago.https://youtu.be/IuG2vuwdMXc
Multiple pins joined but ALSO attached to a net? - Page 1
Forum section: electronics / general

author: NivagSwerdna
author_rank: Super Contributor
timestamp: December 28, 2018, 07:16:23 pm
content: I come across this quite a lot and it is a bit annoying... I have pins I want to join together but I also want to join them into a net.If I join all the pins together then I have nowhere to... Add to Net...Is there a trick to this.. to draw lines between the points but also join to /LD net?

author: NivagSwerdna
author_rank: Super Contributor
timestamp: December 30, 2018, 12:54:24 pm
content: OK in the absence of suggestions I will use a net port component and rename the nets and hope it all lines up

author: BloodyCactus
author_rank: Frequent Contributor
timestamp: December 30, 2018, 01:31:15 pm
content: I guess I dont understand. wire the points up, wire to the adjoined point, name the net. you dont need a net port.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: December 30, 2018, 09:35:53 pm
content: I am probably not expressing myself clearly...I would like to join some components on one part of the sheet and join another set of components on the same sheet but then join the two collections together without a wire crossing the sheet. For clarity I would like the common net to be labelled at both collections.(Between sheets I would use Net Ports)

author: sleemanj
author_rank: Super Contributor
timestamp: December 30, 2018, 10:21:43 pm
content: Be explicit, use a net port, or a wire, or a bus & port, it makes for easier schematics to read.That said, you can draw a normal schematic wire between the things you want to connect, then right click the wire and choose to hide it, it will display basically like net ports.Or right click on one set of the connected pins, choose Net Name, rename to the same net name as the other connected pins, DT will ask if you want to connect the nets (without a wire).

author: NivagSwerdna
author_rank: Super Contributor
timestamp: December 31, 2018, 02:00:38 pm
content: It would be nice if the net port displayed the name of the net to which it was connected rather than a potentially different name (and the potential to get out of sync).

author: BloodyCactus
author_rank: Frequent Contributor
timestamp: December 31, 2018, 05:12:35 pm
content: I use a bus. nets retain same name, no confusion.

author: Farley
author_rank: Regular Contributor
timestamp: December 31, 2018, 06:56:56 pm
content: To display the net name on a wire, right click on the wire and select "Display Name" from the context menu.The displayed net name can be moved around the sheet. It will update (where ever it is) if that net name is changed.
Why are there Air Wires for GND VCC showing after copper pour - Page 1
Forum section: electronics / general

author: vincei
author_rank: Contributor
timestamp: November 03, 2018, 09:19:40 pm
content: Hi EEVBlog gurus,I have a board that has large devices with many VCC and GND pins. I connected all these pins to appropriate VCC and GND in schematic and verified as much in the schematic by hovering the mouse over their nets and watching VCC and GND light up everywhere. nice.In PCB I defined VCC and GND copper pours and connected them to the VCC and GND nets, however, when I run the autorouter, no matter what I do, these pins on the devices still show as air wires, why? It looks like they are connected to the appropriate planes but I cannot get the airwires to not show. What is the program trying to tell me? What have I failed to do? I've been looking and looking but I cannot find an answer to thisI tried unrouting one of the samples in the DipTrace distribution and running the autorouter on that and it also leaves the VCC and GND showing as air wires. I'm really trying not to rant here(this could be my own stupidity and unfamiliarity) but if this is feature it is a very annoyingone because showing air wires for nets that are actually connected doesn't make sense and could result in missing real unaddressed air wires because of the extra clutter.I do see the pins of these devices connected in the connectivity checker. Verification->"Check Net Connectivity". Also the PCB and the Schematic compare without errors.Please, what am I not doing or missing? Is there an option to turn this off if it is a feature?This is the latest 3.3.0.1. Earlier versions did the same thing. I still have them installed.Thanks,Vince

author: BloodyCactus
author_rank: Frequent Contributor
timestamp: November 05, 2018, 03:25:27 pm
content: Did you tell it to fill the copper pour?

author: DerekG
author_rank: Frequent Contributor
timestamp: November 07, 2018, 02:33:10 am
content: Quote from: vincei on November 03, 2018, 09:19:40 pmAs suggested above, re-pour all your Vcc & GND polygon fills, then re-verify against the schematic. Provided the copper pours have managed to find a connection to every Vcc & GND pin, the air wires should disappear.

author: 2N3055
author_rank: Super Contributor
timestamp: November 07, 2018, 06:15:17 am
content: Right click on the edge of copper pour in question, and select properties. On "Connectivity" tab you have "Hide Net Ratlines" option. Set it to auto.
How do you connect to a Bus in heirarchical sub-sheets ?  - Page 1
Forum section: electronics / general

author: vincei
author_rank: Contributor
timestamp: July 15, 2018, 12:17:01 am
content: I have a design that has a pair of 32 bit buses. One is an input and the other is a tristate output. I need to make several instances of this sheet in my top level circuit and connect to these buses. Each bus is unique and I don't want them all tied together but I cannot for the life of me figure out how to make this sub sheet thing work. I cannot get the buses to show on the hierarchical component in top-level, I tried Bus Connectors to no avail and it appears that the bus in the subsheet is global so instances of the sub-sheet seem to have each instances buses all tied together which is absolutely not what I want. Do I have to make a hierarchical component where every single pin is called out individually and cannot use a Bus? That would suck mightily.I got DipTrace for the hierarchical feature it claims it has but I'm not getting a warm feeling. Right now I feel like I might as well have stuck with Eagle.Any help appreciated,Cheers,Vince

author: vincei
author_rank: Contributor
timestamp: July 17, 2018, 09:08:28 am
content: I got a response to this question on the Diptrace forum. This is not possibleIt seems so obvious to me I was shocked that it does not work after spending hours trying to make it work.They say this will be implemented in a future release.-Vince
altium libraries in diptrace? - Page 1
Forum section: electronics / general

author: Unknown
author_rank: Unknown
timestamp: May 29, 2018, 05:32:42 pm
content: i was looking at the libraries that comes with diptrace and it has some "altium library" extension files in it which means altium libraries are supported by diptrace but when i download some libraries from altium design site it's extension was " altium compiled library" and it was not supported by diptrace.can any one please explain me from where can i find more "altium library" that can be supported by diptrace

author: BloodyCactus
author_rank: Frequent Contributor
timestamp: May 30, 2018, 12:57:49 pm
content: file extensions are meaningless.Diptrace can import some Altium ASCII (PCAD ascii I think). Just export from altium in pcad ascii.