CS4270 ADC/DAC not working - at all.  - Page 1
Forum section: electronics / projects

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2018, 01:10:07 pm
content: Hello,trying to solve an urgent issue. CS4270 ADC/DAC is not working - at all. Datasheet here:http://www.mouser.com/ds/2/76/CS4270_F1-39353.pdfIt is wired in software mode (only 2k2 pullups on SDA/SCL pins, pin AD2 grounded). Problem is, I even don't get any voltage on the VQ and FILT+ pins. Only some strays there (few mV at VQ, few hundred mV at FILT+).I can't figure out what is wrong. I have even soldered in the other piece I had, but no change.Do you spot any obvious problem there? (I would be so glad to know there is one!) The DAC is to be used via SPI software mode. As far as I can see in the register default values table, it should by powered ON by default anyway.Circuit wired like this:Thanks for any hints!

author: Ice-Tea
author_rank: Super Contributor
timestamp: November 19, 2018, 01:32:04 pm
content: Are you driving rst high?

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2018, 01:36:32 pm
content: !RST signal is 3.3V.Y.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 19, 2018, 06:13:38 pm
content: Just a thought, but you may need to configure the DAC (writing the appropriate registers) in software mode to get it out of the power down mode, although I haven't seen that clearly stated.

author: whollender
author_rank: Regular Contributor
timestamp: November 19, 2018, 07:33:43 pm
content: I've used the CS4272 before with no problems.It looks like you need to actually set the power down bit initially in order to get the device into software mode, then clear it again to start it up.Feel free to look through my project based on the CS4272 for any ideas:https://hackaday.io/project/5912-teensy-super-audio-boardThe CS4272 has some more constraints on startup, but it should be fairly similar.

author: Jens01
author_rank: Contributor
timestamp: November 19, 2018, 08:00:16 pm
content: You should make sure MCLK is stable when the IC is coming out of reset. Mind these instructions:Quoteand also:QuoteAccording to page 19 of the datasheet the initialisation sequence must be finished within 20ms after a high-to-low transition on the reset pin.

author: Yansi
author_rank: Super Contributor
timestamp: November 21, 2018, 12:13:09 pm
content: Thank you all for the suggestions, but don't you think the VQ and FILT+ pins should have voltages present first? Doesn't matter if device powers up into software- or standalone- mode.It seems the device is not powering up at all. Irrespective whether MCLK is present, stable or not.

author: whollender
author_rank: Regular Contributor
timestamp: November 21, 2018, 02:51:13 pm
content: In ICs like this, the analog side is often controlled by the digital side.It's likely that the analog side won't even power up unless you have MCLK applied so that it can go through it's startup procedure.I normally check that the digital communication is working first, but unfortunately the CS4270 can't respond in SPI mode, only in IIC mode.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 21, 2018, 05:00:23 pm
content: Quote from: Yansi on November 21, 2018, 12:13:09 pmAlthough it doesn't seem to be very explicit in the DS (but I haven't read it extensively either), we are suspecting that the chip does shut the internal references down in power down mode to achieve low power down current draw.

author: diyaudio
author_rank: Frequent Contributor
timestamp: November 21, 2018, 05:11:23 pm
content: Your circuit is wired right, are you sure you don't have a stupid mistake.. like a bad solder joint ?You may need to double check the Power Control register, ADDRESS 0x02 Power Down ADC/DAC/DEVICE

author: Jens01
author_rank: Contributor
timestamp: November 21, 2018, 07:45:14 pm
content: Quote from: Yansi on November 21, 2018, 12:13:09 pmThe data-sheet seems clear about start-up behaviour after power-up:QuoteIf these conditions are not met one could expect unexpected start-up behaviour. There are no guarantees unless you follow the data-sheet.

author: flpvsk
author_rank: Newbie
timestamp: February 16, 2023, 09:55:20 pm
content: I was also struggling with it, but now seem to be getting closer to figuring it out. There's not much info online on that chip, so I thought I'd leave a working example with a raspberry pico (RP2040-based) board here:https://github.com/flpvsk/rp2040_i2s_example_cs4270My mistake for a while was assuming that the chip would provide the master clock when set up to be in master mode. That turned out to be false, the microcontroller has to provide that clock in all configurations.