SQRL Acorn as an interesting Artix-7 board? - Page 1
Forum section: electronics / general

author: Fred27
author_rank: Unknown
timestamp: April 14, 2020, 11:04:35 am
content: I keep seeing SQRL Acorn CLE-215 boards appearing on eBay. From what I can tell they were intended for crypto mining, but didn't go down well due to the necessary software not appearing. Cue a lot of angry people and boards being sold on eBay.Considering it's an Artix-7 and it has a M.2 interface plus a JTAG header, I was wondering if this would make an interesting board to play around with. I'm very much a beginner with FPGAs and have played with Spartan-7 and Zynq. My gut feel is that any PCIe work is probably advanced stuff and that it would end up gathering dust, especially without a schematic. Just thought I'd ask and maybe put others onto a good deal - at eBay prices that is, not the original selling price.Link to manufacturer:http://squirrelsresearch.com/acorn-cle-215/eBay example:https://www.ebay.com/itm/Used-SQRL-Acorn-CLE-215-Artix-7-FPGA-w-Powered-Carrier/184251132237Anyone have an opinion?

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 14, 2020, 05:11:12 pm
content: Quote from: Fred27 on April 14, 2020, 11:04:35 amYou're quite right about that.The board has nothing but the FPGA, power supply stuff, heatsinking and a PCIe interface. There's no access to any other IOs as far as I can see. So the only use case would be to implement some kind of accelerator for a computer. If that's of any interest to you. Then you'd need to learn about implementing a PCIe interface. And writing the appropriate driver for the OS. And... And.Yes it's going to gather dust in a drawer unless you have already done all of the above. Or you have a few years available.

author: mark03
author_rank: Frequent Contributor
timestamp: April 14, 2020, 07:57:23 pm
content: Presumably, all of those pins on the M.2 connector can be used just as well for generic I/O, and M.2 connectors are cheap, so it may not matter that it wasdesignedfor PCIe... you could always use it differently. No schematics [that I could find in two minutes] may be a more serious problem, however!

author: hamster_nz
author_rank: Super Contributor
timestamp: April 14, 2020, 09:03:53 pm
content: Quote from: mark03 on April 14, 2020, 07:57:23 pmIf they were running PCIe over those pins then they will be the high speed transceivers, and not generic low-speed fabric pins.

author: asmi
author_rank: Super Contributor
timestamp: April 15, 2020, 12:35:33 am
content: Quote from: SiliconWizard on April 14, 2020, 05:11:12 pmWell it's not that bad - Xilinx provides free PCIE IP so you can put together some working design relatively quickly, and they also provide drivers for Linux for that IP, but without available GPIO utility of such board would be severely limited.

author: asmi
author_rank: Super Contributor
timestamp: April 15, 2020, 12:36:21 am
content: Quote from: mark03 on April 14, 2020, 07:57:23 pmYou might want to read up on what exactly M.2 connector is, and what kind of signals are available there...

author: miken
author_rank: Regular Contributor
timestamp: April 15, 2020, 12:38:52 am
content: It'll probably end up in a drawer, but I bought one. I have experience with the hardware side of the PCIe, but not the drivers... Anyway we'll see in a few days how much additional I/O is available. Thanks for the tip Fred27!

author: Someone
author_rank: Super Contributor
timestamp: April 15, 2020, 07:36:17 am
content: Quote from: SiliconWizard on April 14, 2020, 05:11:12 pmThere are some acceleration/compute tasks that have a low enough data bandwidth that it can all be done over JTAG so it could be easily repurposed there, but stillveryniche.

author: Wiljan
author_rank: Regular Contributor
timestamp: April 15, 2020, 08:14:18 am
content: Do we know which Artix-7 part are on the board?The name CLE-215 could indicate 215K macrobocks = XC7A200T? (It's just a guess)After some searchQuotehttps://bitcointalk.org/index.php?topic=4391318.1100As far as I can see the Vivado WebPack should support the Artix®-7 (XC7A15T, XC7A35T, XC7A50T, XC7A75T, XC7A100T, XC7A200T)So the challenge would be to power the board correctly and to hook up the JTAG correct, I only found some high res images of the CLE-215+ and on that board you have a JTAG connector (Different shape than normal) and another connector called I/O witch might contains some I/O'sand then there are 4 leds where I would expect you could could us as I/OIt might sure be a nice board, special it you want to use it for some algo or so where you do not need high I/O as long the M2 are not documentedFor sure it sound like people want's to get rid of those boards in respect to mining

author: Fred27
author_rank: Unknown
timestamp: April 15, 2020, 08:23:19 am
content: I was thinking that the ideal use would be to use for something like an accelerator project - i.e. hand data to it over PCIe, do something and get it back. I assume that's basically what the mining was doing. I had spotted that there is some Xilinx PCIe IP and I suppose I hoped it would be reasonably easy to get something working passing data back and forth.I'm OK on the PC side of things. However, my experience working with Vivado means I suspect that SiliconWizard is right and it would require a huge amount of time and effort to get to that point. Being able to pass data from a PC to the FPGA fabric and back would be a great tool to have in the mental toolbox but it is far more likely to be a dust collector. (I suppose Zynq is a much easier way to do this sort of thing anyway.)Good luck with it, miken. Keep us posted. I don't think there will be much IO, but that's not really what it's for.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 15, 2020, 02:49:12 pm
content: Quote from: asmi on April 15, 2020, 12:36:21 amYup. And their number is pretty limited too (so that would be very limited for all-purpose IOs anyway.)You'd also have to use an M2 female connector, which implies designing a small PCB if you want to use this board outside of a computer motherboard. (Soldering tiny wires on the connector instead would be crap probably, would be problematic for high-speed stuff, and would be also problematic for the power supply lines. This thing likely draws a lot of current.)If you want a generic dev board with an Artix-7, go look elsewhere IMHO. QMTECH for instance.Now of course for those interested in exactly this - a PCIe solution - that should be fun, but without the schematic, probably close to unusable (where are the PCIe signals themselves on the FPGA? a lot of possibilities AFAIK.)And then, even though XIlinx provides IPs and driver stuff for PCIe development, if you've never done it before, I wouldn't call this easy. A reality check tells me that it WILL end up in a drawer.But if anyone manages to do anything useful with this board, please report back, that should be interesting!

author: asmi
author_rank: Super Contributor
timestamp: April 15, 2020, 04:38:02 pm
content: Quote from: SiliconWizard on April 15, 2020, 02:49:12 pmActually not a lot because in Artix PCIE hard block can only be connected to quads which are on the same side of die as the block itself. This is not the case in Kintex for example, because there MGT quads are arranged in a column - which is why it's possible to support x8 PCIE connection.This is actually interesting because you'd think you would need 2 PCIE hard blocks - one as endpoint to connect to PC, and another one as a root port to connect M.2. Which means that at least one of those connections use soft PCIE IP block. That is unless they intend to use SATA M.2 drive, in which case they will only need a single transceiver. But since MGTs come in quads, I'd connect all 4 to M.2 socket anyway even if I would only intend to use SATA protocol through a single MGT.

author: mark03
author_rank: Frequent Contributor
timestamp: April 15, 2020, 04:48:52 pm
content: Quote from: SiliconWizard on April 15, 2020, 02:49:12 pmIn my defense, this was a thought experiment, not a suggestion. The proposal was that this board (at ~ $25) could be a cheap substitute for something like the Digilent Arty series. The M.2 connector has many more pins than the PMODs provided on boards like that, and because it's designed for differential signaling, IMO it wouldn't be a bad connector choice for a cheap hobbyist dev board if you were designing one. Not my first choice, but not bad.The flaw in my reasoning was pointed out (as usual, thanks) by @hamster_nz. Never having worked with high-speed transceivers and PCIe, I didn't realize that those FPGA pins were dedicated and unavailable for other (non-transceiver) uses. All of the other objections are just... weird.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 15, 2020, 09:50:24 pm
content: Oh, and for a final nail in the coffin... how much power does an Artix 7 200T need?IIRC an M.2. slot has a 8.25 W limit.My Nexys Video (with a XC7A200T-1SBG484C) needs a 36W PSU, and has a tall heat sink.So I suspect you wouldn't be able to use most of the useful logic (eg. all the DSP blocks)

author: miken
author_rank: Regular Contributor
timestamp: April 16, 2020, 03:15:25 am
content: Yeah the hard PCIe block goes to one particular quad, and a soft IP encapsulates it. Now Xilinx does something weird inside the soft IP where the lanes are numbered backwards from what you'd expect them to be, but the lane reversal feature works as far as I know.What I didn't think about before buying: tracing the SDRAM routing. Hopefully they didn't use any fancy board technology.I doubt an Artix-200 can provide much useful co-processing for an up-to-date computer. For now it's just a cheap fun thing to play with. What's crazy is that the SQRL guys went on to make a board with a VU33P with HBM... For under $1K at eBay, that's a hell of a deal, and potentially a huge headache

author: miken
author_rank: Regular Contributor
timestamp: April 18, 2020, 11:34:06 pm
content: OK, so the bad news is that the board uses blind and possibly buried vias, since it's fairly high density. There may be enough traces on the back to guess where the memory traces are going and apply a process of elimination, but that would come later.The good news is that there's a high-density connector hidden underneath the fan. Could it possibly be I/O? I don't recognize the connector type though. I need to measure the pitch of that connector and the JTAG.EDIT: Upon further consideration the board appears to use via-in-pad, so probably no blind/buried vias.

author: Fred27
author_rank: Unknown
timestamp: April 19, 2020, 09:22:10 am
content: As far as tracing pins goes would it be possible to create some simple HDL to toggle lots of them and probe output? Our would it be easier to use JTAG for it's original purpose as a test protocol? Obviously this wouldn't work for checking connections to the RAM.That power connector may be there to supply more power than m.2 can.I decided not to go for one, partly because I realised it wouldn't physically fit in my desktop PC. I'll be interested to see how you get on though.

author: miken
author_rank: Regular Contributor
timestamp: April 19, 2020, 10:29:33 pm
content: I'm thinking something like a bunch of divide-by-2s and running them out to pins. Somehow I've gotten by without ever having to use JTAG Boundary Scan features but that would work too.The big 12V connector on the carrier board goes to a 3.3V switcher to supply the M.2. There is a footprint for a diode coming from the PCIe slot 3.3V@3A, so slot-powered is a possibility. But they probably exceeded that power envelope too. Small form factors mean a lot of tradeoffs; they fit it in a 2280 board-wise but then they slap a heatpipe cooler on it. With the carrier board it takes up two slots at least, but leaves a lot of empty space that's not doing anything useful for cooling.I think the JTAG and I/O connectors are Molex Pico-EZMate. Thankfully premade jumper cables are available, so I can initially cut them in half for pigtails.Molex 0781715006, connector, 6 circuitsMolex 0369200603, 300 mm jumper cableThe mysterious J1 connector seems to be about 0.8 mm pitch. At this point I think it's a Hirose DF52, 20 positions. Unfortunately I haven't been able to find premade cables for this one, and crimping these tiny contacts is not going to be fun, I'm sure.Hirose DF52-20P-0.8C, connector plug bodyHirose DF52-20S-0.8H(21)‎, connector socket SMTHirose ‎DF52-2832PCF‎, crimp terminalAgain, these are just guesses for now, will hopefully confirm in a few days.

author: oPossum
author_rank: Super Contributor
timestamp: April 20, 2020, 02:54:46 am
content: Have you determined what specific Artix-7 part it has?

author: miken
author_rank: Regular Contributor
timestamp: April 20, 2020, 05:50:24 am
content: I don't think I'll be able to confirm until I hook up the Xilinx pod, but I expect it to be an XC7A200T. It looks like the FBG484 package, flip-chip bare die. Unfortunately it appears to be bonded to the heatsink, so I'm not going to pull it off to see the markings at least for now. There is no way to read the speed grade from inside the FPGA as far as I know.

author: Fred27
author_rank: Unknown
timestamp: April 20, 2020, 08:12:09 am
content: I found a YouTube video where someone successfully pulls the heatsink off to add water cooling. It's possible but probably not a great idea. However, you can see it's an XC7A200T under there. Try not to shout at the screen when he describes it as "the world's most powerful FPGA".

author: richardbb
author_rank: Newbie
timestamp: April 20, 2020, 01:43:28 pm
content: The board looks very similiar tohttps://github.com/RHSResearchLLC/NiteFurymaybe the pinout is the same

author: Wiljan
author_rank: Regular Contributor
timestamp: April 20, 2020, 02:29:04 pm
content: Quote from: richardbb on April 20, 2020, 01:43:28 pmOn the phote the "VRM" (as he call it the video) with the small heatsink (1.0V 12A are on the other side than the FPGA but pretty close and a great findSold as NiteFuryhttps://www.crowdsupply.com/rhs-research/nitefury

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 20, 2020, 02:55:59 pm
content: Quote from: richardbb on April 20, 2020, 01:43:28 pmNice find. Sold for $359.A $25 "clone"? Yeah.

author: Fred27
author_rank: Unknown
timestamp: April 20, 2020, 03:33:34 pm
content: It seems quite likely that SQRL ripped off the open source NiteFury. Maybe the NiteFury schematic will help! (No surprise that I had no reply from SQRL regarding a schematic.)The original selling price for the Acorn 215 was $329. It's only selling cheap on eBay because it was a failure for cryptomining.

author: miken
author_rank: Regular Contributor
timestamp: April 20, 2020, 07:13:08 pm
content: Oh wow the Acorn does look like a NiteFury. They probably changed as little as possible.The FPGA speed/temp grade are supposed to be in the 2D barcode on the die. It looks like the guy who did the video didn't clean all the gunk off though.

author: Fred27
author_rank: Unknown
timestamp: April 20, 2020, 10:23:09 pm
content: Thanks to richardbb discovering the NiteFury, I decided that I'd take a punt. I managed to get one for £30. I expect that it will indeed be unlikely to get to a point of it being vaguely useful, but the journey to nowhere might be fun.

author: miken
author_rank: Regular Contributor
timestamp: April 21, 2020, 05:18:33 am
content: Should be funThere are four same-bank LVDS pairs on the Hirose connector, so I'm going to look at designing an HDMI dongle. And an adapter for the Xilinx pod.So I'm puzzling over the timeline of Acorn and NiteFury. The first post about the Acorn on bitcointalk was June 1, 2018. The crowdfunding campaign for NiteFury began on March 12, 2019. From what I can tell, people were receiving Acorns by the end of 2018. From these dates it would appear that NiteFury came out of the Acorn project and not the other way around. I wonder what the story is there.https://bitcointalk.org/index.php?topic=4391318.0https://www.crowdsupply.com/rhs-research/nitefury/updates/crowdfunding-has-begun

author: conmega
author_rank: Contributor
timestamp: April 24, 2020, 04:28:53 pm
content: So I just nabbed some of these and in doing my own research Nitefury says this in a lot of their materials:QuoteSo I think SQRL and RHS Research were working together on this but I guess neither publicly state it.Either way I am curious to see what the speed grade on these are... I got refused access to Xilinx's 2D barcode decoder... I did end up drawing up what the barcode was in that guy's video but the data is useless without this decoder from Xilinx... I may apply for it through my place of work and see if I can throw it through there.Nitefury apparently offered speed grade 3 parts for the first 100 parts shipped. But I have YET to see what the default speed grade they would ship after that so its a bit of a toss up...Real shame there is no way to check speed-grade over JTAG... You'd think this would be the best protection from preventing people from re-badging parts... Instead of locking an encoded barcode decoder behind a corporate wall.

author: OwO
author_rank: Super Contributor
timestamp: April 24, 2020, 05:18:47 pm
content: I think I still have access to the barcode thing; was also denied the first time but after using a friend's corporate email address they approved it. You can DM me the barcode or post it here. They used to have a web interface to look up device info using device DNA (which can be read through JTAG) but it seems to be gone and only the app remains.

author: conmega
author_rank: Contributor
timestamp: April 24, 2020, 06:07:04 pm
content: Thanks that would avoid the headache of applying with my work address and waiting the day or two! Attached should be a faithful recreation of the 2D Barcode off the chip shown in the video mentioned further back in the thread.It at-least decoded with an online 2D Barcode decoder.If Xilinx has no idea what it is let me know and I'll have to look at it more closely.I will also get a good photo of the one on one of the acorns I get when I get them but that will be a few days.

author: conmega
author_rank: Contributor
timestamp: April 25, 2020, 08:45:26 am
content: So for anyone with these to make up a JTAG cable Digikey sells pre-made cables for the Molex Pico-EZ connectors on the board.https://www.digikey.com/product-detail/en/molex/0369200601/WM26622-ND/10233018Quite reasonable considering you can cut it in half and have the connectors for both the 4 multi-purpose I/O and the JTAG header.Although TO NOTE the 4 general purpose I/O on the Pico-EZ connectors are mirrored as the "4 multi-purpose" on the 20 pin Hirose DF52 connector... So slightly less I/O available...But I was looking at the schematics:https://github.com/RHSResearchLLC/NiteFury/blob/master/Hardware/uEVB.pdfNotice the PCIE_DIO and the SMBUS both go to general I/O on the FPGA, as would make sense.So IF your not going to use these in a computer... And just on the bench... Those are also available as I/O...So that's 6 pins there. Might be-able to still use PCIe and get those pins usable with a custom board just not in a standard PC anyway where it may expect SMBUS.Though SQRL also made PCIe to M.2 boards with PLX chips on them and that has an "m.2 SMBUS enable" switch so...?Either way seems like total usable pins from the FPGA so far are:4 LVDS 2.5V pairs, 4 3.3V General purpose I/Os (also two pairs so you can do 2 more LVDS with that if you want), 6 I/O pins on the M.2, 4 PCIe RX/TX pairs and the Refclock pair.Also NiteFury mentions they would ship speed grade 2 parts on normal boards... So that MAY be what Acorn would ship. Would make sense to bulk order one part for the lower price point.Considering they sold a CLE-215 and a CLE-215+ and their cooling solution is beefier than the nitefury part though... May be that the 215 is a SG 2 and the 215+ is a SG 3. Purely speculation though.I am going to guess SG 2 worst case scenario though.

author: Fred27
author_rank: Unknown
timestamp: April 25, 2020, 09:17:40 am
content: I bought the same Pico-EZ cables (although slightly longer) and I'm hoping to see if I can get JTAG working this weekend.I don't think the strength of this board will be externally available I/O, but if between us we can get PCIe working. I'm hoping the Nitefury example will be helpful.

author: OwO
author_rank: Super Contributor
timestamp: April 25, 2020, 10:43:19 am
content: I had to add some white border to that barcode before it will scan, but here is the result:

author: conmega
author_rank: Contributor
timestamp: April 25, 2020, 11:11:41 am
content: Getting PCIe working should be little issuePretty much just dropping the IP block in and hooking to it via AXI.Now what you want to do with it after that and interfacing with AXI is the part that gets fun.Here is an example of another product and a nice little write-up on getting a basic PCIe IP block dropped in and actually seeing it on a system its plugged into.https://numato.com/kb/getting-started-with-pci-express-on-nereid/Quote from: OwO on April 25, 2020, 10:43:19 amWoot! Fantastic to see. So long as I didn't mangle that barcode when re-creating it we should hopefully have just ensured that the these CLE-215+ parts are in-fact speed grade 3.So probably a safe assumption the CLE-215 is speed grade 2 and the CLE-101 is just a XC7A100T something.Some of the best Virtex parts available! Don't know what the E means... Maybe the temp code which would be Extended in that case, 0-100C.I also just ordered up some cables, missed further back in the thread the P/N for the 300mm ones so I ordered those up, probably best to not get 100mm, probably a tad bit too shortI am also going to try my hand at hand crimping some of the itty bitty Hirose connectors... Got 5 housings and 100 pins for like... 5 bucks or whatever... Figured its worth a shot.Looks like my boards should arrive next week.

author: Fred27
author_rank: Unknown
timestamp: April 25, 2020, 01:31:49 pm
content: I also got some Hirose connectors. The look like they will be tricky to crimp. I might have to do it under a microscope!The Pico-EZ also surprised me. I thought they would slide in sideways, but you have t push them straight down to click into place.

author: Fred27
author_rank: Unknown
timestamp: April 25, 2020, 05:03:59 pm
content: Some initial success! It seems the JTAG connector matched the pinout on the uEVB schematic. That's the smaller brother of the NiteFury. (Sorry, the PicoEVB is the smaller one. The uEVB must be another name for the NiteFury.)I can detect the Artix-7 in Vivado. I'm using a Digilent HS2 and an adapter hacked together out of bits from one of those fake Xilinx programmers on eBay. The board is powered by the 12V power input on the PCIe adapter.For reference the JTAG pinout is (starting furthest from the I/O port and working towards it)1 GND2 TCK3 TDO4 TMS5 TDI6 3V3This gives me more confidence that the Nitefury and SQRL Acorn may share a lot.

author: miken
author_rank: Regular Contributor
timestamp: April 25, 2020, 11:54:27 pm
content: That's great newsYesterday I hooked up a cut-in-half Pico-EZmate cable and then realized I had no convenient way of hooking up the Xilinx dongle to it. If it cools down enough tonight perhaps I will break out the soldering iron.Also great news about the speed/temp grade. Yeah, E should be Extended. Thanks for getting that info, guys.The layout of the PCIe lanes is kind of inconvenient in this design since Xilinx has one blessed lane order. I prefer to regenerate Vivado projects from TCL scripts so I'm looking at finding a sufficiently elegant way of modifying the xdc constraints inside the IP on project creation. I think taking the IP out of managed mode and doing some hacky TCL find/replace should work.

author: Fred27
author_rank: Unknown
timestamp: April 27, 2020, 09:02:09 am
content: The NiteFury sample project does something funky with constraints regarding PCIe. The details were lost on me, but it might mean something if you're familiar with PICe stuff. See build notes here:https://github.com/RHSResearchLLC/NiteFury/tree/master/Sample-Projects/Project-0/FPGA-A200T-3. I can successfully run this project via JTAG and some different LEDs blink. Not pushed to flash, so it goes back to whatever is on flash when restarted - some mining algorithm I expect.I need to put this down and get on with some work for a bit, but good to know the Artix-7 is reachable. This is my simple setup at the moment - powering the board via a Molex MiniFit in place of a PCIe power cable and a quickly solder adapter hack for the JTAG. Next step will be verifying that the connectors are laid out as expected. No benefit in putting it inside a PCIe slot just yet.

author: conmega
author_rank: Contributor
timestamp: April 27, 2020, 02:26:06 pm
content: Quote from: Fred27 on April 27, 2020, 09:02:09 amYou will NEED at-least a 100Mhz PCIe ref-clock if your going to run the example design from Nitefury.I have been playing around with examining the Nitefury example and also setting up a project with a RiscV core generated out of their ChipYard project with the ultimate goal to have not only DDR3 but PCIe host off it.The limitation is that there is only one on-board clock on the NiteFury/Acorn, a 200Mhz DDR clock. Theoretically you can use that DDR clock for other stuff internally and even to generate the 100Mhz PCIe clock if your going to say run PCIe in host mode and want to spit out a 100Mhz ref. But its a bit of a learning curve where you can use the internal buffers and where you can't.But right now it seems easiest to just say get a cheap x1 PCIe riser and plug that into the little breakout board you have to get a 100Mhz ref clock from a system.If you get the example project open in the design view where it shows you the blocks and how they interconnect it should become clearer to you what blinking LEDs mean what and what clocks are required for what.I believe one blinks to indicate DDR train complete. The other should be PCIe Link train complete I think.Also you'll probably want some connection to a PC for the NiteFury example since its mostly a DMA engine to the DDR3 on-board, their repository also has scripts for Linux I believe to test it.All I know is I can't wait to get the Acorns I got since the XC7A200T is MUCH more roomy than the XC7A100TI was attempting to get a RiscV core on a XC7A100T and man... Just the core and DDR controller would fit but had issues reaching timing... On the 200T it JUST workedTM.Whether or not it actually works in hardware is yet to be seen but its a LOT more promising than having like a -100ns slack on a million signals...

author: Fred27
author_rank: Unknown
timestamp: April 27, 2020, 05:20:59 pm
content: Thanks. I wasn't expecting the Nitefury example to do much without being connected to PCIe - I just grabbed something to check I could push the bitstream over JTAG. I was happy to see it run and blink some LEDs connected to the expected pins. It gave me more confidence that it's the same device.Thanks for the info about clocks. I'm very much a FPGA beginner, so might just get my head round what's where and blink some LEDs using the onboard clock first before plugging it in to a PCIe slot.

author: asmi
author_rank: Super Contributor
timestamp: April 27, 2020, 06:42:59 pm
content: Quote from: conmega on April 27, 2020, 02:26:06 pmAs I understand you aren't going to be able to route clock from fabric into MGT's PLL. So your best bet would be to build a simple board with PCIE connector and place a clock generator there. This clock is probably also used for M.2 connector's PCIE (or SATA) interface.

author: miken
author_rank: Regular Contributor
timestamp: April 28, 2020, 08:32:54 am
content: Phew, this thing makes a really annoying squealI wonder if a bigger fan can be shoehorned on.So I was able to connect it up to my Xilinx dongle and dump the flash. The markings on the flash chip areS25FL256SAVH20which I believe corresponds to ordering part S25FL256SAGBHV20. It's 256 Mb, 133 MHz, 105 degC, 64 kB sectors.I also loaded in my "Hello World" image that blinks the 4 LEDs, and discovered that I'd forgotten to invert the polarity.I wasn't brave enough to try writing the flash yet.I started a repo on Github with my barebones project:https://github.com/mng2/AcornCLE215p/It's licensed under CERN Open Hardware License v2 Weakly Reciprocal, which is kind of like LGPL in spirit.

author: conmega
author_rank: Contributor
timestamp: April 29, 2020, 09:58:21 am
content: Quote from: miken on April 28, 2020, 08:32:54 amAwesome! Glad to hear your making progress hacking on it.Also interesting to know there is twice the size of flash on these compared to what NiteFury claims to put on, only 128Mb parts...I just re-watched and scrubbed through that YouTube video again, looks like the DDR3 chip is "D9SHM":https://www.micron.com/products/dram/ddr3-sdram/part-catalog/mt41k512m16ha-125Which matches the size NiteFury specs and matches the defined part in their example program.This is not a default part in Vivado, so I copied the timing information out of the defined Mig7 controller from their example project to make my life easier.You should also be-able to export the pin map file (.ucf) from that example project's controller too. Which then allows you to simply import into your own project.Also NOTE when your editing a MIG 7 controller, on the "Memory Options" panel the "Input Clock Period" ALWAYS re-calculates/resets to the memory clock (in this case their example is set to 1875ps/533Mhz) you will need to set this to 5000ps/200Mhz (if using the 200Mhz input DDR clock) EVERY TIME you go into the Mig7 config and change something and want to save it...Usually you don't have to change anything if you set it up correctly the first time, but just a "trap for young players" as they say.I got my boards in todayJust waiting on my Digikey order... Hopefully USPS gets them here by Thursday as they say they will.I did plug them in to a system and they do seem to come alive and enumerate under linux as what they are so they at-least seem to workI for now at-least have some Risc V cores Implemented with no timing issues with a PCIe root complex and Mig7 controller.Here's to hoping I can get one of those alive when I get my cables!

author: miken
author_rank: Regular Contributor
timestamp: April 30, 2020, 03:02:26 am
content: Hey conmega, sounds like you're working on something ambitious. A RISC-V computer system?Thanks for looking up the memory. That looks like the right size part, 8 Gb, but the listing says D9STQ. I wonder if they are running at DDR3 1.5V instead of DDR3L 1.35V?The MIG dialogs are indeed super annoying. We have a project at work with three memory banks... I was able to convert that project to IP generation from MIG .prj file and TCL.Good luck with your project. My PCIe extender has arrived but it's 1x. Time to see if my old computer is still functional.

author: conmega
author_rank: Contributor
timestamp: May 02, 2020, 09:03:22 pm
content: Yea, it is quite ambitious. I'll probably be lucky to get one 64-bit core going at 50~Mhz or so it looks like.But hey if I can get that up alone that would be great.Looking to heavily utilize Virtual I/O and BSCAN to JTAG adapter to allow for on chip debugging of internal signals without the need to break them out to headers. Likely going to break out only the things that make sense like say serial for a console so I can have that open live on another window.The example program has the ram set for 1.5V not DDR3L...And that chip part number I got off the youtube video of someone taking the heatsink off theirs so I believe the D9SHM is correct.I also have had the example code programmed onto a board and according to the LEDS had the memory train properly.So copy whats in the NiteFury example project and you should be OK.Digikey order JUST got in today and I was able to make up all my cables.I also ordered the parts for the little itty 20-pin connector and its not a male/female pin header like standard connectors. The cable side has two surfaces that show through the plastic housing so my idea to hack these together is by soldering.Using 28awg wire I have had some success.Basically my process is as follows (NOTE: keep pins on steel pin strip until the last step, do not break them off beforehand otherwise they will likely end up in the oblivion):Needle nose pliers to get side crimp parts bent inwards and get them parallel so they will fit width wise into connector.Take flush cutters and perpendicular to the pin cut the top most bits of the rear cable holding crimp off to allow pin to fit height-wise into the housing.Then tape the strip down, get your cut/stripped 28awg wire, lay it in the channel and with very fine solder just flow the slightest amount in.Also keep the wire just up to the tip of the front most crimp (towards the pin end) don't go further than that since this is where a plastic detent falls to hold the pin in the housing.Any extra solder on the outside of the pin or too much on top of the wire will cause the pin not to fit... Its pretty tight!But buying plenty of extra pins and a few extra housings will probably allow you to get together a complete cable with an hour or two of frustration under the microscope if you have one. If not maybe 2-3 hours and twice as many extra pinsHousing:https://www.digikey.com/product-detail/en/hirose-electric-co-ltd/DF52-20P-0.8C/H125095-ND/5721350Pins:https://www.digikey.com/product-detail/en/hirose-electric-co-ltd/DF52-2832PCF/H125109CT-ND/5721384

author: miken
author_rank: Regular Contributor
timestamp: May 03, 2020, 06:30:51 am
content: You work fastI took one look at those tiny crimp pins when they arrived, and set them aside for another day. Don't have magnification handy so I may put it off until I do.Good to hear that the memory layout seems to match the NiteFury. I am distracting myself a bit, getting better acquainted with the PCIe core than I have needed to in the past.

author: conmega
author_rank: Contributor
timestamp: May 03, 2020, 07:28:11 pm
content: That's good! I have been avoiding the PCIe core a bit after attempting to poke at it and realizing the example code in the NiteFury repository requires a certain linux kernel for the DMA example of the kernel module...I do need to poke at a more simple PCIe endpoint and see how bad it is to just poke at simple registers.I have been also working on designing a PCB to plug the little Acorn into that breaks to an x16 slot (x4 logically of-course) along with on-board 3.3V regulation and a 100Mhz HCST PCIe refclock.This is in hopes that I can run a PCIe root complex off the FPGA and be-able to attach devices to it.I have a lot of learning to do about differential signaling and AC/DC coupling some of these clocks. Luckily a lot of the clock chips and buffer chips have quite a few examples in them so we will see what comes of that.

author: conmega
author_rank: Contributor
timestamp: May 05, 2020, 11:57:15 am
content: Well I was able to get a RiscV32 core up on the FPGA and point the JTAG interface for it to the other 6-pin connector.And OpenOCD was able to see it!Code:openocd.exe -f share\openocd\scripts\interface\jlink.cfg -c "adapter speed 10000" -c "transport select jtag"Open On-Chip Debugger 0.10.0 (2020-05-03) [https://github.com/sysprogs/openocd]Licensed under GNU GPL v2libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3For bug reports, readhttp://openocd.org/doc/doxygen/bugs.htmladapter speed: 10000 kHzjtagInfo : Listening on port 6666 for tcl connectionsInfo : Listening on port 4444 for telnet connectionsInfo : J-Link ARM V8 compiled Nov 28 2014 13:44:46Info : Hardware version: 8.00Info : VTarget = 3.267 VInfo : clock speed 10000 kHzWarn : There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!Info : JTAG tap: auto0.tap tap/device found: 0x13039a73 (mfg: 0x539 (<unknown>), part: 0x3039, ver: 0x1)Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 5 -expected-id 0x13039a73"Warn : gdb services need one or more targets definedAlso I have found there is a very simple modification that can be done to make your "2.5V LVDS" pins which are just 2.5V GPIO in the current config, there is nothing in the datasheet saying they HAVE to be LVDS they are just routed for it.But there is a regulator in the schematics (U11) which is the 2.5V 500mA regulator for that rail... Its just feeling the Vref for that I/O bank and as far as I can tell that I/O bank is ONLY being used for those LVDS pins. (Might need to double check this for yourself)So if you de-solder U11 and bridge Vin and Vout... You'll have 3.3V GPIO on those other 8 pinsHere is the regulator in question:http://www.ti.com/lit/ds/symlink/tps82695.pdfCute little thing!U11 is the right one of those regulators on the back of the SQRL (M.2 connector down) towards the bottom of the board.From the pin-out of the datasheet Vin/Vout are BGA pads right in a row. So should be easy to bridge!I serve no warrenty for your SQRL if you preform this modification!I would double-triple check the schematics before. But figured some might want to know this is a possible way to get 8 more 3.3V pins to go with your 4 other pins for a total of 12 3.3V I/O pins or 6 diff pairs

author: justinjja
author_rank: Regular Contributor
timestamp: May 06, 2020, 11:39:51 pm
content: I have a few of these CLE-215 fpgas.They aren't rip offs, nitefury is SQRL's design. Dave Reynolds works for SQRL.Adding a couple pictures w/ the heatsink removed if anyone is interested.

author: conmega
author_rank: Contributor
timestamp: May 07, 2020, 11:55:02 am
content: Quote from: justinjja on May 06, 2020, 11:39:51 pmAwesome to know! I don't really know the folks at SQRL and their site is a bit lacking in information. I know from some reading that SQRL mostly deals with large bulk purchases and their dealings with private individuals online through their store is because they want to not because they have to.I think we all suspected the connection but didn't have confirmationAlso I see from the sticker you have a CLE-215+ not just a CLE-215 (There is a difference!) We suspect that the CLE-215 is a speed grade 2 part and the 215+ is a speed grade 3 part of the same XC7A200T part. The CLE-101 is a XC7A100T speed grade unknown.Which from my quick and rough searching around makes it one of the only available speed grade 3 part on a "dev board" of any kind...Now that speed grade is probably negligible to most people's use cases unless your going to really push the part and its I/Os which this has very little of so yea.

author: conmega
author_rank: Contributor
timestamp: May 07, 2020, 04:11:38 pm
content: Also I should note anyone looking to grab one of these things shouldn't pay any more than 100 bucks a pop honestly from the prices and listings I have seen sell and discussing in mining communities.Thing to note here is that they were 330 dollars a pop new but the company offered store credit to those who bought them since they failed to release a bitstream they said they would, which was for about half of what the thing cost the buyers so even the people who bought the things new only have about 160~ a pop invested in them all together. So I would say $100 a piece is a hard cap on the realistic used value of these things.Guy in france has a ton up NIB for 65 dollars a pop right now, shipping to the US isn't too crazy it looks like:https://www.ebay.com/itm/SQRL-Acorn-CLE-215-Miner-NEW-Open-box/124017503476

author: futaris
author_rank: Newbie
timestamp: May 08, 2020, 11:14:33 pm
content: https://twitter.com/enjoy_digital/status/1257985111469015040

author: Wiljan
author_rank: Regular Contributor
timestamp: May 17, 2020, 08:42:24 am
content: I just got a SQRL 215+ as well and wait for molex connector and PCI-e Riser to power the boardMeanwhile I try to make my own blinky to get familiar with the Vivado and sure a normal standalone PCI'e Rieser does not give the 100Mhz clkQuote from: conmega on April 27, 2020, 02:26:06 pmWhat about the 90Mhz clk U10 3V3 on page 6 in the schematic connected to pin V22 on the Artix-7 can that be used as a stand alone clk, or is th 200MHz DDR clk the only option?

author: conmega
author_rank: Contributor
timestamp: May 17, 2020, 10:43:13 am
content: Quote from: Wiljan on May 17, 2020, 08:42:24 amIf you notice this pin is labeled: IO_L3N_T0_DQS_EMCCLK_14_0EMCCLK is a clock pin specified for "Configuration Logic" I don't believe it is also a clock capable pin like others which will say MRCC or SRCC for example.Looking more closely at the the DDR 200Mhz clock, you can absolutely use that as a standard clock, I may just not fully understood what I was doing at the time with the MIG7 DDR3 controller IP core. It may not be possible to use the DDR3 core at the same time with the using the 200Mhz clock with other stuff but looking at it again I see that the DDR clock comes in on MRCC clock pair.Just be sure you know it comes in as a differential clock pair, you need to buffer this with the appropriate clock buffer options in either the clocking wizard if you use block view or instantiate the correct clock buffers in your HDL.Here this will be your friend and enemy:https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdfAlso one thing I did mean and I know is impossible is driving PCIe off of this as a root complex without an external clock. The PCIe connection on the M.2 goes specifically to phys designed for the PCIe or similar high speed interface. This INCLUDES the PCIe clock connection, which is ONLY an input for the clock, this pair can not be driven and as such if you want to use this as a root complex you'll need a board with an M.2 to PCIe connector with the related power supply (3.3V) and HCST clock driver for both the nite-fury/sqrl and the endpoint PCIe slot. I was working on designing a board for JUST that case, but got side-tracked by another FPGA projectAlso I noticed that post by futaris and well... My thunder was stolen heh. So I figured I'd wait to see where that goes and maybe give that litex core a try, although they have a PCIe ENDPOINT not a ROOT COMPLEX! So less fun IMOAnyway good luck and let us know how you make out!

author: Fred27
author_rank: Unknown
timestamp: May 17, 2020, 11:14:34 am
content: I tried using the 90MHz clock as a clock input and got routing errors - probably due the reasons conmega specified. (I'm new at those so it could also have been a mistake on my part.)

author: miken
author_rank: Regular Contributor
timestamp: May 18, 2020, 04:31:44 am
content: I think it's possible to use the STARTUPE2 primitive to use the config clock in a design. You'll need to select the EMCCLK as the config clock, otherwise the built-in oscillator is used for config. The documentation for the STARTUPE2 is kinda terse though (UG953). The DDR clock will presumably be of higher quality.The MIG can take a clock from "inside" the FPGA, but the default is for the clock to come from external pins.

author: Arbies
author_rank: Newbie
timestamp: May 19, 2020, 06:44:28 pm
content: Quote from: Fred27 on April 20, 2020, 03:33:34 pmHey guys, I originally got on the SQRL train for crypto and a cool FPGA board (trying to get back into FPGA programming, did a little in college). Anyhow, I am in their discord channel and mentioned this post.They had this to say"if they used the web contact, the email probably never came through. Not sure if I will be able to get it but they can try email us directly at support@squirrelsresearch.com - I always answer emails that come through to support"Not sure what they can and cannot provide but figured I would share the info.

author: Fred27
author_rank: Unknown
timestamp: May 19, 2020, 08:22:56 pm
content: Thanks for your post, Arbies. We've ascertained that the SQRL Acorn and the NiteFury are the same board, so we now have a full schematic.

author: Arbies
author_rank: Newbie
timestamp: May 19, 2020, 09:11:07 pm
content: NP, I have been lurking around here and there for while so glad to be able to contribute and connect the dots of my obscure range of knowledge. They did announce a few months ago "Official Notice: The Acorn line of hardware has officially been discontinued. We will continue to offer software / bitstream support as opportunities present." Around that time they cleaned up their website so it is hard to find things these days. If having a driver helps anyone:http://www.squirrelsresearch.com/get-started-acorn/I understand the SQRL driver works for all their products and I am not sure if there is any proprietary magic in their bit-streams to talk to their driver.There is a walk-around if you want to get the linux driver working in the latest Kernel. I can dig up the commands if someone is interested.Most of the bit-streams releases were released in the discord.

author: Fred27
author_rank: Unknown
timestamp: May 19, 2020, 09:38:06 pm
content: I took a quick look at the inf file for the Windows drivers and right at the op of SQRLDMA.inf is "Copyright (c) Xilinx All rights reserved. ... XDMA.inf".

author: fanat9
author_rank: Newbie
timestamp: May 20, 2020, 01:00:26 am
content: https://github.com/d953i/SQRL_ACORN/blob/master/constraints/sqrl_acorn_master.xdcThis may help someone. Happy hacking!

author: PharmEcis
author_rank: Newbie
timestamp: May 20, 2020, 02:24:46 pm
content: If anyone is interested in acquiring more 215+ and or some Nests I have a bunch available. I also have some m.2 to pcie 4x adapters as well. Can do package shipping. Can sell via eBay if you want or we can go direct so I can save some money on fees.As I am an unknown person here, I am linking my eBay store reputation. I am a VERY known individual in the FPGA crypto mining space.https://www.ebay.com/fdbk/feedback_profile/surplusinc

author: Wiljan
author_rank: Regular Contributor
timestamp: May 20, 2020, 05:39:30 pm
content: Ok, I have made the JTAG cable and I have soldered 3V3 + GND power wire to a external PSU and if does spin up and have LED flashing and draw around 1.3 A @ 3V3 with the shipped bitstream in flashWhen I download my own bitstream the led changes and now the current are about 300mA makes sense since the FAN also draw some current.I have a PLL in my setup and it would like to have a Reset connected ... now I do not have the SQRL connected to any PCI bus and therefore the PCI reset are not available, any suggestion for a Reset pin for a stand alone SQRL?Does the FPGA have some build-in reset function?

author: miken
author_rank: Regular Contributor
timestamp: May 21, 2020, 04:00:39 am
content: On this family of FPGAs there is a global internal reset, so you can give registers initial values for startup. For example you could make a counter for waiting for a certain amount of time before releasing the PLL. That said, I haven't seen any negative effects from hardwiring PLL or MMCM resets.If you want an external reset you'll have to add it on one of the connectors.

author: Wiljan
author_rank: Regular Contributor
timestamp: May 21, 2020, 11:38:34 am
content: Not sure if you refer to Global reset as reading the PROGRAM_B or the INIT_B pins?For now I have tired the PLL reset as .reset(1'b0), and it works fineAlso I got both the 90Mhz and the 200Mhz to workNext I have added the Config Flash s25fl256sxxxxxx0-spi-x1_x2_x4 as x4 (schematic says 25FL128 but Vivado detect it as 25FL256Created a MCS file and programmed it and now the new bitstream loads fine from 25FL256 on power cycleHad to remove the 90Mhz again since it blocked the SPI load

author: stilger
author_rank: Newbie
timestamp: June 05, 2020, 04:52:25 pm
content: If anyone is interested in acquiring more 215+ and or some Nests I have a bunch available. I also have some m.2 to pcie 4x adapters as well. Can do package shipping. Can sell via eBay if you want or we can go direct so I can save some money on fees.As I am an unknown person here, I am linking my eBay reputation and listings. I am a known individual in the FPGA crypto mining space. Maybe not as well as PharmEcis.Rep -https://www.ebay.com/fdbk/feedback_profile/stilgerI have listed the Acorns and Nest's on eBay but would be willing sell direct as needed.Acorns -https://www.ebay.com/itm/174307525400Nests x2g -https://www.ebay.com/itm/174307537397I actually have 14 Acorns. I'd make a super deal if someone wanted all 14 acorns and 4 nests.

author: FPGA_Zealot
author_rank: Newbie
timestamp: June 13, 2020, 01:12:59 pm
content: I just tested my Acorn cle-215+.The DDR is 1 GB and the flash is "Part identified : s25fl128sxxxxxx1". (Vivado)I wonder if 128 and 256 flash parts were used. The size may not be consistent across different devices.

author: stilger
author_rank: Newbie
timestamp: June 20, 2020, 02:07:59 am
content: Quote from: stilger on June 05, 2020, 04:52:25 pmThanks to everyone that has bought these. I am now down to 3 Acorns with m.2 PCIe adapters, 2 Nest x2g's and 2 Acorns that are not listed because they do not have the m.2 pcie adapter.

author: stilger
author_rank: Newbie
timestamp: June 22, 2020, 07:46:52 pm
content: Mine are all sold. Thanks to the folks here that bought. Good luck with them!

author: benh
author_rank: Newbie
timestamp: July 02, 2020, 04:07:07 am
content: So I got one of these toys to play with Microwatt on. There's one thing I'm not sure I have right: The pins on the little P2 connector (AIO1N/P, AIO2N/P), do they come from a 3.3V IO domain or a 2.5V one ?I assume I can use them as 4 generic IO pins and I don't have to use them as 2 LVDS pairs correct ? IE. I can stick a 3.3V UART there, can't I ?There's something called "TMON_CORE" but I can't completely figure out what it is, it goes to a pin of the FPGA and the TMON pin of LTC3638.Is there a way to monitor the temperature of that thing ? I want to disconnect the fan as it's high pitch noise is really annoying.

author: conmega
author_rank: Contributor
timestamp: July 02, 2020, 10:23:38 am
content: Quote from: benh on July 02, 2020, 04:07:07 amYou are correct. Those 4 pins are also duplicated on the 20 pin connector. But they are in the 3.3V domain and can be used as SE pins, so can the 2.5V pins on the 20 pin connector. Those can be used SE but they set the I/O domain to 2.5V to help allow LVDS use.I actually in an earlier post suspected that you can remove the 2.5V regulator module and short this to 3.3V and make those 2.5V domain pins 3.3V as-well. But I have yet to need to try it or try it myself.I actually used the exact same cable i made up for JTAG on the JTAG header on the other P2 header and used this for JTAG to a RISC-V core in my development and it worked great.So 3.3V RS-232 should be fine too.

author: Wiljan
author_rank: Regular Contributor
timestamp: July 02, 2020, 02:33:19 pm
content: Quote from: benh on July 02, 2020, 04:07:07 amYep very annoying (all small fans have to run fast to move little air) I have just blocked the fan mechanically, and when I see the current on my 3.3V Bench PSU goes form 250mA to 500mA every 10s for about 1s when the fan tries to start spinning again.I think it fine while not running at demanding core yet, sure a PWM controlled Fan control would be best

author: benh
author_rank: Newbie
timestamp: July 03, 2020, 05:52:29 am
content: Thanks. I snatched one of those cheap FTDI 2232H USB thingies, verified it's "SPI" port B was wired in such a way I can use it for JTAG and its port A is a UART. Seems to work with an old Spartan board I have here, i'll start messing with the pico connector this week-end.

author: Fred27
author_rank: Unknown
timestamp: July 13, 2020, 09:56:28 am
content: Whilst the Acorn CLE-215 seems to have been well and truly abandoned, it seems that the NiteFury hasn't. Whilst trying to get XDMA working with the Acorn, I noticed that the github repo for the NiteFury had been updated. The most interesting change seems to be the addition of a smaller LiteFury version with the XC7A100T. This seems to be priced at a more interesting $99, although this obvious is still higher than the Acorn (if you were lucky).Details here at the NiteFury repo:https://github.com/RHSResearchLLC/NiteFury

author: MattSR
author_rank: Regular Contributor
timestamp: July 14, 2020, 03:34:53 am
content: This has to be the cheapest way to get an Artix-7-200T FPGA dev board.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 15, 2020, 04:32:15 am
content: How easy is it to get the board communicating via PCIe to some userspace program on the PC connected to it? If I understand correctly, the differential inputs could be connected as a HDMI input using a cheap HDMI "repeater" as a buffer, even if it doesn't actually use HDMI protocol. Could be a way to get a cheap 4K HDMI capture card (not counting the cost of development time, of course) that can also work to accept all sorts of high speed data streams, with plenty of its own memory for buffering and logic for offloading some processing from the PC.Too bad there aren't any fast ADCs that I'm aware of that will be able to interface with the limited number of I/Os available, could make a really nice SDR coprocessor otherwise.

author: james_s
author_rank: Super Contributor
timestamp: July 15, 2020, 05:01:11 am
content: It would sure be nice if the designers of boards like this would bring out a bunch of the extra IO to pads on the PCB. The added cost of manufacture would be essentially zero and it would enable the board to be repurposed into something far more useful when it inevitably becomes obsolete for the original intended purpose.

author: Fred27
author_rank: Unknown
timestamp: July 15, 2020, 07:00:43 am
content: PCIe is the feature that makes this board interesting. I've been trying to get Project-0 PCIeexample from the NiteFury repo working. I'm struggling with the Xilinx xdma driver side of things. I've even gone as far as downgrading the Linux kernel on Ubuntu 18.04. Has anyone got this working or have any tips to do so?

author: miken
author_rank: Regular Contributor
timestamp: July 17, 2020, 07:18:59 am
content: Getting PCIe register peek-poke is fairly straightforward, it's DMA where you have to get into trouble with (sometimes proprietary) cores and drivers. I am more interested in the LiteX ecosystem's DMA solution rather than messing with Xilinx XDMA. Maybe in a few weeks I'll have more time to work on it.The FPGA has a temperature sensor, and the temp sensor in the power controller is connected to one of the ADC channels on the FPGA. To read the internal temp and any external analog signals, you use this block called the XADC, which I think you can either instantiate as an IP or write a sort of wrapper around (see UG480).This family of FPGA doesn't have an auto temp shutdown so I would be careful running without a fan. You can also see the temperature through the Hardware Manager if you have a dongle.

author: MattSR
author_rank: Regular Contributor
timestamp: July 21, 2020, 01:00:04 am
content: So basically, it's possible to burn one out by driving it too hard with inadequate cooling?Quote from: miken on July 17, 2020, 07:18:59 am

author: miken
author_rank: Regular Contributor
timestamp: July 21, 2020, 05:49:27 am
content: It's possible though admittedly you'd need to have a fair amount of stuff ticking away. Just do your due diligence

author: conmega
author_rank: Contributor
timestamp: July 26, 2020, 06:10:34 am
content: Ordered up boards for my SQRL root complex use case.Will let everyone know:A) How JLCs 4 layer process comes outB) If I am competent enough to have a working boardHopefully there aren't too many delays in getting all the parts and boards in.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 27, 2020, 12:03:44 am
content: Could LVDS encoders/decoders be an easy workaround to the limited I/O problem?

author: miken
author_rank: Regular Contributor
timestamp: July 27, 2020, 06:55:56 am
content: Looks neat conmega, good luck with the buildQuote from: NiHaoMike on July 27, 2020, 12:03:44 amOf course, but it all depends on your application. (Ignoring the gigabit transceivers) If you're aiming for the high end, a -3 grade LVDS pair can handle 1250 Megabits/sec, so 6x that is the hard limit as far as data transfer goes. Plus your downstream device would need to be able to handle that kind of rate. You could even slap on another FPGA, but at some point add-ons eclipse the original in terms of complexity and you might as well start over from scratch...Maybe an iCE40 breakout would be useful for people who need more I/O, but don't have large bandwidth requirements.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 27, 2020, 01:54:54 pm
content: I was thinking use a LVDS encoder to connect a fast ADC so that the board could be used as a SDR.

author: miken
author_rank: Regular Contributor
timestamp: July 29, 2020, 09:19:55 am
content: Do you have any parts in mind? I took a look around Digikey and saw mostly display link serializers.I think though that for the price of a few serializers, you could get a small Spartan-7 or similar and have that manage the interface.

author: dmendesf
author_rank: Frequent Contributor
timestamp: July 29, 2020, 12:47:41 pm
content: There are fast ADCs with LVDS outputs, for example ADS6149.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 29, 2020, 01:15:22 pm
content: Quote from: dmendesf on July 29, 2020, 12:47:41 pmExcept it has more LVDS pairs than the Acorn has available.

author: dmendesf
author_rank: Frequent Contributor
timestamp: July 29, 2020, 01:45:51 pm
content: How many LVDS pairs are available? I also bought one of these boards... Not planning to do SDR but fast data aquisition for other purposes, but I'm still searching for a suitable mini-itx board. Maybe I'll wait for Ryzen 4000 APUs broad deployment.

author: dmendesf
author_rank: Frequent Contributor
timestamp: July 29, 2020, 02:07:04 pm
content: LTC2387-18 is a 18bit, 15MSPS with single LVDS lane output. Still need to connect conv, clock, etc but maybe these can be output as single ended and then converted to differential. I Know that 18 bits is not interesting for SDR (12 bits at 30MSPS would be better) but for now that's what I found for a single lane. There's also the JESD output converters...

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 29, 2020, 10:58:01 pm
content: Quote from: dmendesf on July 29, 2020, 01:45:51 pm4 pairs specifically marked as LVDS plus another 2 that are shared with the auxiliary header. (Why they didn't dedicate another 4 pins to the header is strange, there's so many extra pins...)Then there are up to 3 more TX pairs and 3 more RX pairs (all of them really fast) if you're willing to downgrade the PCIe to a x1. Might actually do that by modifying one of my cheap PCIe extenders, x1 is the best those really cheap extenders can do anyways.Quote from: dmendesf on July 29, 2020, 02:07:04 pmNot sure about you but if I were to go through the effort to use a PCIe connected FPGA, I would like far more bandwidth than what a super cheap FX2 based solution can do.

author: NiHaoMike
author_rank: Super Contributor
timestamp: July 30, 2020, 11:31:50 pm
content: A quick search finds this LVDS serializer/deserializer:https://www.ti.com/product/DS92LV16As well as this one that has a pair of serializers, but in a not so hobbyist friendly BGA package:https://www.ti.com/product/SCAN921821Looking through the datasheets, they just seem to be super fast UARTs.

author: miken
author_rank: Regular Contributor
timestamp: August 02, 2020, 08:27:54 am
content: The SCAN921821 is interesting since you could do 18 bit I+Q at up to 62.5 MHz with just one chip. Doesn't seem available in small quantities from anywhere except direct from TI though. It's also LVCMOS/TTL in, but that's fine.The real challenge is doing the receive side. You'd have to build the "DES" part of a SERDES in the FPGA. The PLL in the Rx side needs to track the PLL in the Tx side well enough for the data to come through. I don't know if that's a realistic goal. The first trouble is getting the ADC clock into the FPGA. The bank where the 4 LVDS are doesn't have the clock-capable pins broken out. The bank with the 2 LVDS does, but those are attached to the LEDs. So you'd need to see if the clocking is feasible and/or realistic.I actually didn't know that splitting up the GTs in a quad was possible. Using the GTs might perhaps be simpler but due to shared resources there are restrictions perAR62267. The quad doesn't have the second refclk input broken out so we might be restricted to the PCIe refclk (100 MHz).

author: NiHaoMike
author_rank: Super Contributor
timestamp: August 20, 2020, 03:31:44 am
content: Just thought of this, could the PCIe interface act as a x2 device and x2 host simultaneously? Might make a cheap PCIe analyzer. I also wonder if it could be possible to implement USB 2.0 device on the aux header for connection to another PC that's hosting the UI.

author: denger
author_rank: Newbie
timestamp: September 17, 2020, 10:09:41 pm
content: I managed to build the demo FPGA-A200T-3 project included in the NiteFury git repo. Took a bit tinkering with latest vivado. Loaded it on the CLE-215+, and it's recognized by the driver. It even passes XDMA tests, sometimes. About every 6th test returns bad data. It's usually in the 18th bit, which gets flipped.I suspect the clocking of memory is at fault. Initially project sets the clock at 1850ps, which is outside the range that the IP wizard dialog wants.I have tried 3077ps (So I can get exactly 200Mhz input) and it does much better as far as error rate, but still not perfect. With that setting I get about 1 in 20 tests fail, same failure mode.Anyone managed to get the XDMA tests to reliably pass? Would you kindly share the parameters for the mig_7series core you made to run?

author: miken
author_rank: Regular Contributor
timestamp: September 20, 2020, 08:33:34 pm
content: Quote from: denger on September 17, 2020, 10:09:41 pmYou may actually be the farthest alongI haven't looked at the XDMA project. Try something slow like 2:1 mode, 2500 ps.

author: fanoush
author_rank: Contributor
timestamp: September 21, 2020, 10:58:26 am
content: Hello anyone got more of those molex Pico-EZmate jtag cables and could ship one inside EU in a letter/envelope and accept paypal? Sadly mouser/digikey/arrow has quite expensive (>$20) shipping for this ~$3 item.

author: Fred27
author_rank: Unknown
timestamp: September 22, 2020, 09:16:00 am
content: I've got a spare. PM me your address an I'll send you one.

author: fanoush
author_rank: Contributor
timestamp: September 23, 2020, 06:52:48 am
content: Great, thank you very much, so with the cable on a way to me I've ordered one from herehttps://www.ebay.com/itm/Acorn-CLE-215-Artix-7-FPGA/193672183164The prices are not that low anymore but this one still looks good to me, seen it for 70EUR few weeks ago. And it is the 215+ !Wanted to try LiteX on it but now I see someone already got it working :-)https://spoolqueue.com/new-design/fpga/migen/litex/2020/08/11/acorn-cle-215.htmlhttps://twitter.com/enjoy_digital/status/1257985111469015040

author: apshamilton
author_rank: Newbie
timestamp: November 08, 2020, 11:34:56 am
content: I am selling some Acorn 215s - new, unused but open box. Price is $70 for payment in crypto of $80 for payment via other methods.See details here:https://www.hivelist.org/fpga/@apshamilton/acorn-215-xilinx-artix-7-200t-fpga-with-1gb-dram-usdus70-with-payment-in-crypto

author: fanoush
author_rank: Contributor
timestamp: November 25, 2020, 09:28:56 am
content: Got jtag working (thanks again Fred27 for the cable!), can see fpga in xc3sprog however I did not find bitstream that would make SPI flash accessible, the bscan_spi_xc7v2000t.bit one herehttps://github.com/quartiq/bscan_spi_bitstreamsdoes not work so there is more to it - probably needs to be specific for the board.Also the fan is quite loud. Does the FPGA has some thermal protection built in? The heatsink is massive so I guess fan is not needed for moderate usage.

author: asmi
author_rank: Super Contributor
timestamp: November 25, 2020, 12:23:13 pm
content: Quote from: fanoush on November 25, 2020, 09:28:56 amNo it does not. At least I've seen several times FPGA die temperature going beyond its' grade limit and it continued working. Current consumption increases with temperature, which can cause thermal runaway (higher current -> higher heating -> higher current and the loop closes), so I recommend to be very careful with FPGA thermal management.If fan is annoying, maybe there is a way to modify the board so that it would only turn on once heatsink goes above certain temperature? Or maybe even PWM the fan speed to reduce the noise when possible.

author: miken
author_rank: Regular Contributor
timestamp: November 30, 2020, 08:52:16 am
content: Quote from: fanoush on November 25, 2020, 09:28:56 amI've not used the software in question but I think you want the xc7a200t file. For Xilinx FPGAs the SPI pins involved in configuration are fixed, so I don't think it would be board dependent.As for noise, I soldered a somewhat larger fan to the carrier board but haven't figured the rest out yet.

author: kentfielddude
author_rank: Contributor
timestamp: December 16, 2020, 06:51:18 am
content: LCSC has the artix-7 200T for $90 usdhttps://lcsc.com/product-detail/New-Arrivals_XILINX-XC7A200T-2FBG484I_C494680.html

author: -gb-
author_rank: Contributor
timestamp: January 06, 2021, 11:42:00 pm
content: Greetings,has anyone tried powering the Board through the Fan Connector?Which modelnumber is the Fan connector or are there crimped cabled to buy?And ... are there already crimped cables for the high-pincount-connector? How hard is it to do the crimping on your own?How much power will be drawn without mining, just a minimal PCIe system?What do i want to try?There are Thunderbolt3 Cases für externals SSDs which have an M.2 inside. I want to install the FPGA Card in such a case, but there is no room for Fan or passive cooling. But i do not mine, i just want to test the bandwidth i can gat over Thunderbolt3. Theoretically, Thunderbolt3 is limited at 22 GBit/s, because 18 GBit/s are fixed reserve for Displayport (will change with Thunderbolt4). But the Artix7 only supports PCIe gen2 x4, that is 4x 5 GBit/s = 20 GBit/s.(With Thunderbolt4, the limit is PCIe gen3 x4 = 32 GBit/s.)Thank you!

author: Foxxz
author_rank: Regular Contributor
timestamp: January 07, 2021, 03:25:16 pm
content: Quote from: -gb- on January 06, 2021, 11:42:00 pmI used this one with the NiteFuryhttps://www.amazon.com/gp/product/B07N74VZKZ/The FPGA lights up and I THINK an unknown device shows up on 'lspci'.You have to use the command 'boltctl' the first time you hook it up to authorize the device to connect to the system. I think its a security protection to prevent unknown devices from being plugged in since thunderbolt has DMA access.

author: -gb-
author_rank: Contributor
timestamp: January 08, 2021, 09:12:11 pm
content: Greetings!I did not jet try the Thunderbolt Case, but i received the FPGA board and indeed, the Fan is very loud. So i wrote a minimal VHDL project, just a counter for blinking LEDs and flashed it. The board consumes 60 mA @ 12 V, 12 V because i use the SQRL PCIe to M.2 adapterboard. Oh by the way, the DCDC regulator on this board is whining.But now, the FPGA stays cool, even without cooling. I removed the heatsink with hot air.Next i will read about PCIe and what to do to transmit data from FPGA to PC.

author: SMB784
author_rank: Frequent Contributor
timestamp: January 09, 2021, 06:32:36 pm
content: After reading through the thread, it is my understanding that the 6 "I/O" pins broken out through the Pico EZMate connector are also broken out through the 20-pin Hirose DF52 connector. Is this correct? Also, are the JTAG pins broken out through the Hirose DF52 connector in addition to the Pico EZMate connector?

author: -gb-
author_rank: Contributor
timestamp: January 09, 2021, 08:46:04 pm
content: QuoteYesQuoteNohttps://raw.githubusercontent.com/RHSResearchLLC/NiteFury-and-LiteFury/master/Hardware/uEVB.pdf

author: SMB784
author_rank: Frequent Contributor
timestamp: January 20, 2021, 10:40:07 pm
content: I don't know if you can safely short the VIN to the VOUT on U11 and get 3.3V out on the IO pins for the DF52 connector. From the schematic, the 2.5V output of the U11 regulator also powers VDD of the 200 MHz RAM clock in addition to the 12 digital IO pins on the DF52 connector. Maybe someone can check me on that; The datasheet for the oscillator (ASDMPLV-200MHz) says that VDD for this oscillator is between 2.25 & 3.6, so maybe 3.3V is no big deal for the RAM clock, but will the oscillator output increase as a result of the higher VDD and possibly harm the clock input pins on the FPGA? I also worry about noise on the unregulated 3.3V line affecting the oscillator that used to be powered by a 2.5V regulator. Someone else ought to weigh in on that too.

author: SMB784
author_rank: Frequent Contributor
timestamp: January 21, 2021, 02:32:44 pm
content: I looked up the recommended input voltages from the datasheet for the XC7A200T (see attached image), and it says that the max safe input for the differential IO banks is ~2.6V, meanwhile the datasheet for the oscillator says that for VDD between 2.2 & 3.6V the oscillator output swings by 0.35V and has an offset of 1.5V, which leads me to believe that the oscillator has a peak voltage of somewhere between 1.5 and 1.85V. This is within the voltage input spec of the FPGA pins, but someone with more hardware knowledge should check my reasoning here.

author: -gb-
author_rank: Contributor
timestamp: January 21, 2021, 09:44:48 pm
content: The voltage swing of the LVDS OSC is not the limit of the bank voltage. This is a HR bank, VCCO can be set up to 3.6 V, seehttps://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf. So 3.3 V is fine.BUT:With 3.3 V VCCO you cannot use this bank to output LVDS. (LVDS input works fine). If you neet to output an differential signal with 3.3 V VCCO, you may useIOSTANDARD TMDS_33as it is used for HDMI.

author: SMB784
author_rank: Frequent Contributor
timestamp: January 21, 2021, 10:21:04 pm
content: Quote from: -gb- on January 21, 2021, 09:44:48 pmI think we are talking about different things here. It has been proposed that you can change the output of the pins on the DF52 connector from 2.5V to 3.3V by removing the 2.5V regulator (U11) and shorting the U11 pads corresponding to Vin and Vout.The problem with that is that regulator is not just driving those DF52 pins, it's also serving as VDD for the 200MHz RAM clock oscillator chip (X1). My fear is that when changing VDD for that chip by swapping the 2.5V U11 regulator with a short to 3.3V, the output of the X1 oscillator will become too high voltage for differential the input pins that it is connected to on the Arty-7 FPGA.According to the datasheet, these pins can only handle at most 2.6V, which may be lower than the output voltage if the X1 oscillator at its new 3.3V VDD.However, if the output of the X1 oscillator remains below 2.6V despite the higher VDD, then this isn't a problem, and the only concern is line noise on the unregulated 3.3V rail interfering with the oscillator output. That may not be a problem either though, given that the oscillator has 50dB of rail isolation

author: -gb-
author_rank: Contributor
timestamp: January 21, 2021, 10:44:26 pm
content: Sorry!But ... look at the datasheet:https://abracon.com/Oscillators/ASDMP.pdfMinimum Supply Voltage is +2.25 V. So the LVDS OSC will work fine.

author: SMB784
author_rank: Frequent Contributor
timestamp: January 22, 2021, 12:03:58 am
content: Quote from: -gb- on January 21, 2021, 10:44:26 pmThanks, I'm pretty sure the oscillator will work fine, my concern is about the oscillator output. Does the output of the oscillator change as a function of the input voltage VDD? The Datasheet entry for the CMOS version of this oscillator says that it does, but the entry for our oscillator (LVDS variety) doesn't seem to say very much about how the output voltage is affected by VDD. If the oscillator output rises above 2.6V as a result of the higher VDD, it can damage the input pins on the FPGA.

author: -gb-
author_rank: Contributor
timestamp: January 22, 2021, 03:10:42 pm
content: Ah OK. This OSC outputs LVDS. Both pins swing 350 mV around a DC level of 1.125 V ... 1.4 V. So they are far below the 2.5 V.

author: SMB784
author_rank: Frequent Contributor
timestamp: January 22, 2021, 03:23:36 pm
content: Quote from: -gb- on January 22, 2021, 03:10:42 pmDo you think that output is unaffected by the VDD? I don't see anything in the datasheet indicating that the output changes as a function of VDD, but I don't see anything saying that it doesn't either. My guess is that if it was affected by VDD, they would probably say so like they did with the CMOS variant, but I'm not familiar enough with industry practices to know whether this omission was intentional (indicating that there is no dependence on VDD) or just the result of a poorly specified datasheet.

author: -gb-
author_rank: Contributor
timestamp: January 22, 2021, 04:53:57 pm
content: Quote from: SMB784 on January 22, 2021, 03:23:36 pmYes. It is LVDS.

author: SMB784
author_rank: Frequent Contributor
timestamp: January 22, 2021, 06:14:31 pm
content: Quote from: -gb- on January 22, 2021, 04:53:57 pmGotcha, thanks for the reassurance.For those of you who are trying to put together the DF52 cable, I recommend that you don't actually try to assemble it from the connector, crimp terminal, & wires. This is a fools errand unless you have the $6000 specialized crimping tool and the appropriate kind of wire. I recommend that you just buy the cables pre-crimped for insertion into the DF52 housing. Those cables can be found on mouser (link here). For 20 of them + the DF52 housing it will cost you about $25 without shipping. Digikey only sells them in batches of 100, which will cost you about $57 + shipping.

author: SMB784
author_rank: Frequent Contributor
timestamp: January 31, 2021, 02:32:15 am
content: Hey everyone,I wrote a minimal hardware configuration that blinks all the accessible LEDs and outputs square waves of different frequencies on all 12 of the GPIO outputs on the DF52 board. This might be useful for people to test whether or not their board works after they get it. The vivado project can be built by cloning my github repository (found herehttps://github.com/SMB784/SQRL) and using the TCL script build_SQRL.tcl. The github repository also includes instructions on how to program this board using a generic FT232H to USB adapter rather than the usual special Xilinx cable, as well as automatic scripts for uploading the post-implementation SQRL_top.bit & SQRL_top.bin files for programming the FPGA and the flash.In order to get 3.3V output on DF52 pins 15, 16, 18, and 19, you are required to remove the U11 regulator and short the input and output pins on the U11 pad together, as described earlier in this thread. I have confirmed that this works, and does not negatively affect the board in any way that I have noticed.I have attached images of the waveform output from pin 3 (3.3V GPIO pin at 12.5 MHz output) and pin 19 (2.5V LVDS pin modified to 3.3V GPIO at 6.1 kHz output ) to this post.If you need to put together a DF52 cable, I highly recommend getting the specific DF52 cables with the pre-crimped ends (found here on Mouser) that fit into the DF52 housing (found here). Cutting the cables in half will allow you to make 2 DF52-to-whatever-you-want cables (in my case, IDC20 connectors).Hopefully this helps someone else make good use of this board

author: SMB784
author_rank: Frequent Contributor
timestamp: January 31, 2021, 05:39:40 pm
content: Having tested this basic load out, the SQRL Acorn 215/215+ board appears to be a pretty good dev board for the money. You get the best available7 SeriesFPGA (Artix7 200T) that can be programmed with Xilinx's free tools, and you have the option to have it with the top speed grade (if you get the 215+). This dev board has 12 GPIOs operating at 3.3V, 4 user controllable LEDs, an M.2 adapter for a PCIe interface with even more pins, and an easy to access JTAG port for configuration/programming. Overall this is a pretty great deal for <$100.

author: teslabit77
author_rank: Newbie
timestamp: February 20, 2021, 09:04:24 pm
content: Hello folks..I'm looking for buy ONE(1) High-Power M.2 PCIe x4 adapter for acorn 215.please let me know if anyone have this PCIe board.Danny.

author: asmi
author_rank: Super Contributor
timestamp: February 21, 2021, 02:06:08 am
content: Quote from: SMB784 on January 31, 2021, 05:39:40 pmThis is not even close to being true. There are much better FPGA available in free license.

author: SMB784
author_rank: Frequent Contributor
timestamp: February 21, 2021, 05:47:19 am
content: Quote from: asmi on February 21, 2021, 02:06:08 amYou're right! The UltraScale/UltraScale+ FPGAs apparently now work with the free Vivado webpack:https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html#architectureSo, if you are ready to throw down thousands of dollars for your learner's dev board, then you will get way more power than you could muster with this ~$60 board.Of course that would be rather ridiculous to even suggest, given that the entire premise of this thread involves repurposing a bitcoin FPGA for less than a hundred dollars. Nevertheless, I have sightly modified my post to reflect this trivial fact.EDIT: For a list of dev boards for FPGA with better specs (and associated price) than the Artix7 200T which can be programmed by the free tools, see below:AVNet Ultrazed-EV (XCZU7EV for $999)Kintex UltraScale+ FPGA KCU116 Evaluation Kit (XCKU5P $2995)Trenz TE0803 (XCZU5EV $1200)Trenz TE0807 (XCZU7EV $1830)As you can see, these boards have better specs but are more than 10 times more expensive. Other boards either can only be programmed with tools that cost more than 10 times the price of this Arty7 board, or can be programmed with free tools but are themselves more than 10 times more expensive than this Arty7 board.With this SQRL Acorn board, you are getting an extremely good FPGA for rock bottom prices, and you still get 12 good GPIO ports, external JTAG access, and PCIe as well all for only $60-$80.

author: asmi
author_rank: Super Contributor
timestamp: February 21, 2021, 11:11:36 pm
content: Quote from: SMB784 on February 21, 2021, 05:47:19 amAt least they are proper devboards, not repurposed crap with no interesting peripherals.Oh, and you forgot Kintex-7 - even though K160T has slightly less LUTs than A200T, it's fabric is significantly faster, and so are it's transceivers - they can go to 10G even in speed grade 2, and 12.5G for SG3.My favorite devboard is Genesys 2 - it's got Kintex-325T device with SG2, it includes a permanent license to Vivado for that device, so programming is not a problem, and this license is only tied to device density (325T), meaning you can build your own boards with these devices in any package. And Kintex-7 can drive DDR3 memory at up to 933 MHz, so giving you all the bandwidth you will ever need. Though because of the way memory devices are wired on Genesys 2 board, you can only go up to 900 MHz, but it's still an insane 900 * 2 * 32 = 57600 Mbps.

author: SMB784
author_rank: Frequent Contributor
timestamp: March 04, 2021, 03:40:43 am
content: Quote from: SMB784 on January 31, 2021, 02:32:15 amOn a whim I bought a CLE-215+ with the best specced part with the Arty7 200T speed grade 3. I tested my basic load-out configuration, and confirmed that it works without modification, producing the correct outputs etc.So if you end up with either the CLE-215 or the CLE-215+ this should work for verification of functionality.

author: Teknoman117
author_rank: Contributor
timestamp: September 08, 2021, 05:17:01 am
content: Does anyone know what DDR3 part is on the Acorn CLE-215+? I'm a little nervous about trying to take the heatsink off at this point in time.I'd like to try and kick it up to the 1066 Mbps claimed for NiteFury, or even possibly 1333 Mbps if the part specified by LiteX (MT41K512M16) is actually what's in there. (That is, assuminghttps://www.xilinx.com/support/answers/61572.htmlis valid for -3 grade Artix-7 parts)

author: SMB784
author_rank: Frequent Contributor
timestamp: September 08, 2021, 12:50:30 pm
content: Quote from: Teknoman117 on September 08, 2021, 05:17:01 amAccording to Micron'sFBGA number decoder, the memory part for the CLE-215+ (FBGA # D9STQ) is indeed the MT41K512M16See attached photo for visual confirmation

author: Teknoman117
author_rank: Contributor
timestamp: September 08, 2021, 04:40:43 pm
content: Quote from: SMB784 on September 08, 2021, 12:50:30 pmThanks for the picture. Looks like the MT41K512M16HA-125:A is not a dual die part, and thus limited to 1066 Mbps (officially, anyhow).

author: SMB784
author_rank: Frequent Contributor
timestamp: September 08, 2021, 06:31:28 pm
content: Quote from: Teknoman117 on September 08, 2021, 04:40:43 pmThe datasheet indicates that -125:A means 1600Mbps

author: Teknoman117
author_rank: Contributor
timestamp: September 13, 2021, 05:38:11 am
content: Quote from: SMB784 on September 08, 2021, 06:31:28 pmRight, but the Artix-7 datasheet says the max frequency for DDR3 that it supports on the -3 speed grade for single die parts is 1066 Mbps / data line. Elsewhere it mentions up to 1250 Mbps / data line for LVDS, so I wonder if they are only reporting compatibility for JEDEC official speed steps.

author: BrianHG
author_rank: Super Contributor
timestamp: September 13, 2021, 05:45:12 am
content: Quote from: Teknoman117 on September 13, 2021, 05:38:11 amLVDS is differential. It tends to achieve slightly better performance using pairs of IO pins to send 1 bit.

author: Teknoman117
author_rank: Contributor
timestamp: September 29, 2021, 03:38:21 am
content: I know someone mentioned they were going to try HDMI/DVI output earlier in this thread, but I never saw a follow up. I managed to get 1080p60 out of a CLE-215+ IO connector with a little adapter board I made. It's a little beyond the official spec for differential signals (1485 MHz vs 1408 MHz), but it seems to work.It's based on a PI3HDX511D DisplayPort to TMDS level shifter / redriver and a 3.3V to 5V boost converter to supply the +5V rail to the HDMI sink. As mentioned here before, the Acorn can't output TMDS directly because most of the IO pins are hooked up to 2.5V, but I wasn't keen on modifying the board. DisplayPort uses LVDS, which is supported at 2.5V with the LVDS_25 IOSTANDARD.I threw the KiCad project up athttps://github.com/teknoman117/ACORN-CLE-DVIThe assembly is a pain though. I shake a bit, so landing the 0.4mm pitch TQFN-30 more or less perfect on the pads after applying the solder paste is quite difficult. I'm 1.9 for 3 at this point, as one board is assembled perfectly, one has a broken DDC SCL line (shorted to ground under the QFN), and the third one appears to be completely dead. I think I'll try a larger QFN next time, there seem to be a few 0.5mm pitch ones that aren't completely out of stock.

author: NiHaoMike
author_rank: Super Contributor
timestamp: September 29, 2021, 12:53:04 pm
content: What board are you using to adapt the M.2 to USB-C? Does it work for data or is it power only?

author: Teknoman117
author_rank: Contributor
timestamp: September 29, 2021, 05:03:10 pm
content: I took the board out of a Sabrent Thunderbolt 3 to M.2 enclosure (Amazon Link:https://www.amazon.com/gp/product/B08FT59SB6). It was $70 USD when I got it two months ago. Unfortunately it's only a JHL6240 controller, so there are only 2 lanes of PCIe. Since the price went up to $90 USD, it's only a short bit away from 4 lane controllers.On the host side, I did the "short pins 3 & 5" mod to a GC-Titan Ridge 2.0 thunderbolt add-in card to get it to function in an AMD system. It doesn't work under Windows, but for Linux you can pass some magic kernel arguments to reserve PCIe BDFs so you can hot-plug PCIe bridges.

author: SMB784
author_rank: Frequent Contributor
timestamp: September 29, 2021, 11:37:58 pm
content: Quote from: Teknoman117 on September 29, 2021, 05:03:10 pmDo you have a source for a 4 lane PCIe M.2 to USB C board with a similar form factor to the one you used? I was looking at this one, but I cannot seem to find a place to buy it that is reputable (amazon, newegg, etc):https://www.delock.de/produkte/G_42001/merkmale.htmlI found what I think may be areasonably priced variantof this board that supports PCIe x4 on amazon.I have ordered one, and I will try it out to see if it can at least power the unit. It comes with a nice fan and a heatsink, so I can ditch the ridiculous ACORN heatsink.

author: Teknoman117
author_rank: Contributor
timestamp: September 30, 2021, 12:52:47 am
content: I don't have a reliable source.I'm on the fence about purchasing either this one:https://www.amazon.com/dp/B085T57STTor this one:https://www.amazon.com/dp/B08P7L6SDD. The speed exceeds the maximum throughput of 2 lanes @ 8 GT/s, so it has to be a 4 lane controller. Basically, you're looking for a JHL6340 or JHL7440 controller if the enclosure uses an Intel chipset. Googling or searching Amazon for that usually just results in external PCIe cages for full size cards.In my experience, Amazon has pretty open about returns, so at worst you're left paying return shipping if one doesn't work.

author: SMB784
author_rank: Frequent Contributor
timestamp: September 30, 2021, 12:58:32 am
content: Quote from: Teknoman117 on September 30, 2021, 12:52:47 amThe one in my edited post uses an ASM2364 chipset. That seems to be an x4 controller. Does that strike you as something that would work?

author: Teknoman117
author_rank: Contributor
timestamp: September 30, 2021, 12:59:42 am
content: Yeah, it certainly sounds like it should work.However, the 20 Gbps bandwidth cap is going to limit you. 4 lanes of 8 GT/s would be ~31.8 Gbps of bandwidth.Sorry for the edit,This one won't work. It's a USB 3.2 to NVMe adapter, rather than a true thunderbolt adapter.https://www.asmedia.com.tw/products-list/d8cyq6FXzaUH8XJa/BF2yq24XzDuS5Tr4

author: Teknoman117
author_rank: Contributor
timestamp: September 30, 2021, 01:05:02 am
content: Replying again because I retracted my comment from my previous reply.

author: SMB784
author_rank: Frequent Contributor
timestamp: September 30, 2021, 01:18:34 am
content: Quote from: Teknoman117 on September 30, 2021, 12:59:42 amOk, thats interesting. Why won't it work, and what wont it work for? Why is a true thunderbolt adapter needed, and for what is it needed? Sorry I'm pretty new to the whole M.2 thing

author: Teknoman117
author_rank: Contributor
timestamp: September 30, 2021, 04:26:53 am
content: I guess "it won't work" depends on what you're using it for.A "true" thunderbolt adapter just serves as a bridge between the host system and the PCIe device. The device would show up like any other PCIe device to the host, use the same drivers, and function identically as it would if it were installed in the host machine.Problem is, the majority of computers made do not have thunderbolt controllers. So, if you want to attach one of the high speed NVMe drives to any generic computer, you need to look like something most computers do have, and this is basically always USB. The enclosure you linked has a CPU or at the very least, some complex state machine and a PCIe root complex. It makes the PCIe connection with the NVMe disk, but it presents itself to the host computer as a USB Mass Storage device. The host has no idea what kind of physical storage is on the other side, just that it complies with the USB Mass Storage specification. You can't access anything specific about the device.So, unless your goal is to turn the FPGA board into an NVMe device, you won't get much use out of a USB to PCIe enclosure. If you want to use Xilinx XDMA, LitePCIe, or something else, you'd need the thunderbolt to PCIe enclosure.

author: miken
author_rank: Regular Contributor
timestamp: September 30, 2021, 04:58:47 am
content: Nice work Teknoman117, glad to see proof of concept.I've been working on a board based on the PTN3381B. It's a bigger part but 0.5mm pitch and includes the 5V generator. I'll get around to finishing it up in the next few weeks... I got distracted by the idea of making a 3M 7700 cable for it, but attempted cable production was a disaster and now I think using the pre-crimped wires is the only realistic option.https://github.com/mng2/AcornHDMII also put together a super basic PCIe example that I need to finish writing up. I have been using the Acorn with an old computer, rather than trying to plug it into any of my modern ones. A Thunderbolt enclosure would be neat though.

author: Teknoman117
author_rank: Contributor
timestamp: September 30, 2021, 06:21:21 am
content: The integrated 5V converter is a nice feature as the boost converter and inductor are notable contributors to my BOM ($1.17 USD in unit-10 quantities). The precrimped cables are pretty hit or miss sadly. At 30cm, you have to be really careful how the cables are laid out. If the lanes get jumbled too much, the signal loses lock.I’m thinking about attempting to find a source for that self-adhesive foil wrap that goes in shielded cables or at the very least install more of the ground conductors and try to bond them into a pseudo ribbon cable where the lanes are spaced by a ground wire.As far as BOM goes, those precrimped wires hurt. Nearly $1 per wire. The cable costs more than the whole assembled adapter. $5 for the board ($50 for 10 units at JLCPCB w/ ENIG finish and the electro leveled stencil and shipping) and $7 for components. The cable is like $17 to make with all conductors populated.

author: SMB784
author_rank: Frequent Contributor
timestamp: September 30, 2021, 10:50:28 am
content: Quote from: Teknoman117 on September 30, 2021, 04:26:53 amThat is a wonderful explanation, thank you! Now I understand what I need to buy. Much appreciated!I ended up going withthis one, as it is the cheapest option. It only fits the 2280 form factor, but that's the size of the unit anyway so no biggie there. We will see how well it works!

author: miken
author_rank: Regular Contributor
timestamp: September 30, 2021, 06:28:09 pm
content: Quote from: Teknoman117 on September 30, 2021, 06:21:21 amYeah, I was thinking to put the wires on kapton to make a ribbon, cut 'em down to 10cm and solder the wires directly to the board.It's too bad RHS chose a connector system that's hard for hobbyists to work with, but understandable given the constraints of the compact form factor. I tried cutting and soldering the crimp terminals under a microscope, but in the end my results were too thick to fit in the housing. Perhaps I could get it to work if I were a bit more precise, but I'm not anxious to repeat the exercise. The pre-crimps are pricey but I'm not sure there's a great alternative unless one happens to have access to the official crimp tools.

author: Teknoman117
author_rank: Contributor
timestamp: September 30, 2021, 11:01:30 pm
content: I actually ended up solving the signal issues. I completely forgot that you're supposed to twist the pairs of wires together.No signal issues regardless of how I bend, fold, or loop the cable now. I can still get 1080p60 on the 30 cm precrimped wires with no visible artifacting as far as I can tell.

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 01, 2021, 12:22:42 am
content: Quote from: Teknoman117 on September 30, 2021, 04:26:53 amThose use UAS (USB attached SCSI) instead of the old mass storage protocol. Might it be possible to have the FPGA appear as a SCSI generic device through one of those adapters?

author: SMB784
author_rank: Frequent Contributor
timestamp: October 04, 2021, 08:42:53 pm
content: Quote from: SMB784 on September 30, 2021, 10:50:28 amMy thunderbolt enclosure came in today, and boy is it perfect for this board. It fits the board snugly, it comes with a thermal pad to turn the aluminum case into a heatsink, and it has enough space above the USB port for a small cutout so that the DF52 connector can fit inside the cutout and provide access to the 2.5V LVDS (in my case, the board has been modified to output 3.3V on those pins). The thunderbolt provides quite a lot of power for the unit, so it should be able to run complex, high resource FPGA designs without drawing too much current. The case offers an elegant heatsink alternative to the ridiculous fan and humongous heatsink attached to the original board.I haveupdated the github project for the basic loadoutto include a link & some pictures (which I have attached below) of the board in its enclosure.I will post my attempts at creating a cutout for the DF52 connector as soon as I finish that.Made a small cutout just below the USB connector to feed the GPIO wires through, and successfully tested the basic loadout from the github with the SQRL in the enclosure (see photos). To summarize, this is an excellent enclosure for this board.With a little luck, and a good PCIe architecture, this will make a very nice plug-in FPGA project for all kinds of fun stuff.

author: SMB784
author_rank: Frequent Contributor
timestamp: October 05, 2021, 03:07:56 am
content: At this point I am looking for a good terminating connector for the other side of the DF52 cable. Does anyone have any suggestions for a really ubiquitous 20-pin connector that has a lot of adapter options available to make it versatile?

author: SMB784
author_rank: Frequent Contributor
timestamp: October 05, 2021, 08:25:25 pm
content: Another question I have is related to the fact that it's possible to program the FPGA via the SQRL PCIe adapter board that comes with the unit (I'm guessing that means the JTAG interface is accessible through PCIe).Does anyone think we can access the FPGA JTAG interface via USB through the Thunderbolt board?

author: miken
author_rank: Regular Contributor
timestamp: October 07, 2021, 04:48:49 am
content: As far as I know the RHS example image just contains a SPI peripheral that can be accessed over PCIe for writing to the Flash. After all, it's not much use to reprogram it "live" since that will unload the FPGA first and then you're kind of stuckThere are more advanced things you can do with Tandem PROM or partial reconfiguration, we'll get there someday maybe.In theory the JTAG block can be accessed from inside the FPGA via the DRP interface. It might be interesting for ILA use but again reprogramming is problematic.Connectors are always kind of a pain point for hobbyist use. Anything that's not mass market is going to be expensive. There's that SYZYGY idea from Opal Kelly but Samtecs aren't cheap. If you don't need high speed then a standard 0.1" grid is probably your best bet, if boring. Modular jacks are cheap too but you'll need multiples.

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 07, 2021, 05:01:31 am
content: As for a cheap connector with multiple GHz differential pairs, HDMI and Displayport come to mind.

author: SMB784
author_rank: Frequent Contributor
timestamp: October 12, 2021, 11:10:58 pm
content: Quote from: miken on October 07, 2021, 04:48:49 amI dug around looking for what you were referring to, and I believe i have found how to program the flash as mentioned:https://github.com/RHSResearchLLC/NiteFury-and-LiteFury/tree/master/spi-loaderTherefore, it should be possible to program the FPGA flash to load a custom module using the Thunderbolt enclosure and USB cable. Now I need to figure out how to do that.

author: SMB784
author_rank: Frequent Contributor
timestamp: October 23, 2021, 06:58:26 pm
content: Alright so I have uploaded the original AXI-quad_spi project to the SQRL board via JTAG (found at this github repo:https://github.com/RHSResearchLLC/NiteFury-and-LiteFury/tree/master/Sample-Projects/Project-0/FPGA-A200T-3), and I have also successfully installed the Xilinx XDMA drivers.When I load the board onto the Thunderbolt to USB-C adapter and plug it in, my linux box (Ubuntu 20.04 HWE) recognizes the USB-C thunderbolt adapter when I use lsusb:Code:Bus 001 Device 008: ID 8087:0000 Intel Corp. TPS65983TPS65983 is the correct name for the TI thunderbolt chip in this adapter.However, when I run the spi-loader (github link on same nitefury project:https://github.com/RHSResearchLLC/NiteFury-and-LiteFury/tree/master/spi-loader) using the supplied memory configuration file, I get an error that says:Code:Device file not found:/dev/xdma/card0/user. Is the XDMA driver installed and working?modinfo tells me that XDMA is indeed installed and working correctly:Code:$ modinfo xdmafilename: /lib/modules/5.11.0-38-generic/extra/xdma.kolicense: Dual BSD/GPLversion: 2020.2.2description: Xilinx XDMA Reference Driverauthor: Xilinx, Inc.srcversion: 755B8C84314FF43EE2506DCalias: pci:v00001D0Fd0000F001sv*sd*bc*sc*i*alias: pci:v00001D0Fd0000F000sv*sd*bc*sc*i*alias: pci:v000010EEd00002808sv*sd*bc*sc*i*alias: pci:v000010EEd00004B28sv*sd*bc*sc*i*alias: pci:v000010EEd00004A28sv*sd*bc*sc*i*alias: pci:v000010EEd00004908sv*sd*bc*sc*i*alias: pci:v000010EEd00004828sv*sd*bc*sc*i*alias: pci:v000010EEd00004808sv*sd*bc*sc*i*alias: pci:v000010EEd00006D30sv*sd*bc*sc*i*alias: pci:v000010EEd00006A30sv*sd*bc*sc*i*alias: pci:v000010EEd00006A28sv*sd*bc*sc*i*alias: pci:v000010EEd00006930sv*sd*bc*sc*i*alias: pci:v000010EEd00006928sv*sd*bc*sc*i*alias: pci:v000010EEd00006830sv*sd*bc*sc*i*alias: pci:v000010EEd00006828sv*sd*bc*sc*i*alias: pci:v000010EEd00007038sv*sd*bc*sc*i*alias: pci:v000010EEd00007034sv*sd*bc*sc*i*alias: pci:v000010EEd00007032sv*sd*bc*sc*i*alias: pci:v000010EEd00007031sv*sd*bc*sc*i*alias: pci:v000010EEd00007028sv*sd*bc*sc*i*alias: pci:v000010EEd00007024sv*sd*bc*sc*i*alias: pci:v000010EEd00007022sv*sd*bc*sc*i*alias: pci:v000010EEd00007021sv*sd*bc*sc*i*alias: pci:v000010EEd00007018sv*sd*bc*sc*i*alias: pci:v000010EEd00007014sv*sd*bc*sc*i*alias: pci:v000010EEd00007012sv*sd*bc*sc*i*alias: pci:v000010EEd00007011sv*sd*bc*sc*i*alias: pci:v000010EEd00008038sv*sd*bc*sc*i*alias: pci:v000010EEd00008034sv*sd*bc*sc*i*alias: pci:v000010EEd00008032sv*sd*bc*sc*i*alias: pci:v000010EEd00008031sv*sd*bc*sc*i*alias: pci:v000010EEd00008028sv*sd*bc*sc*i*alias: pci:v000010EEd00008024sv*sd*bc*sc*i*alias: pci:v000010EEd00008022sv*sd*bc*sc*i*alias: pci:v000010EEd00008021sv*sd*bc*sc*i*alias: pci:v000010EEd00008018sv*sd*bc*sc*i*alias: pci:v000010EEd00008014sv*sd*bc*sc*i*alias: pci:v000010EEd00008012sv*sd*bc*sc*i*alias: pci:v000010EEd00008011sv*sd*bc*sc*i*alias: pci:v000010EEd00009011sv*sd*bc*sc*i*alias: pci:v000010EEd00009021sv*sd*bc*sc*i*alias: pci:v000010EEd00009031sv*sd*bc*sc*i*alias: pci:v000010EEd00009012sv*sd*bc*sc*i*alias: pci:v000010EEd00009022sv*sd*bc*sc*i*alias: pci:v000010EEd00009032sv*sd*bc*sc*i*alias: pci:v000010EEd00009014sv*sd*bc*sc*i*alias: pci:v000010EEd00009024sv*sd*bc*sc*i*alias: pci:v000010EEd00009034sv*sd*bc*sc*i*alias: pci:v000010EEd00009018sv*sd*bc*sc*i*alias: pci:v000010EEd00009028sv*sd*bc*sc*i*alias: pci:v000010EEd00009038sv*sd*bc*sc*i*alias: pci:v000010EEd0000903Fsv*sd*bc*sc*i*alias: pci:v000010EEd00009041sv*sd*bc*sc*i*alias: pci:v000010EEd00009042sv*sd*bc*sc*i*alias: pci:v000010EEd00009044sv*sd*bc*sc*i*alias: pci:v000010EEd00009048sv*sd*bc*sc*i*depends:retpoline: Yname: xdmavermagic: 5.11.0-38-generic SMP mod_unload modversionssig_id: PKCS#7signer: Modulessig_key: 26:1D:63:96:05:5C:E0:68:98:7B:AF:61:CA:40:AA:E2:37:39:26:73sig_hashalgo: sha512signature: 1F:6D:25:1C:88:6E:F1:2E:ED:2F:E1:49:64:52:7A:18:5B:BE:96:65:1A:E8:D8:8D:F3:36:B3:1E:B0:72:75:57:6C:6F:B7:8D:5F:72:DC:A7:9C:EC:91:70:64:6E:93:C9:02:59:5B:DB:B0:A4:6D:C2:46:8D:DA:1D:24:15:00:1A:DD:F1:43:A3:C3:96:5E:74:3B:5E:C5:6A:6C:C9:23:9B:43:4E:38:6C:C1:CD:BC:F3:9D:BA:C3:87:B6:33:81:14:ED:F7:33:E6:FD:69:41:FF:EA:45:71:9F:76:41:3B:A6:C0:E4:9D:65:C6:3F:10:06:3E:05:9E:B8:58:5C:CF:6C:E7:EB:18:C8:6B:90:6F:72:0C:90:8B:42:B6:F2:A6:71:46:B1:81:2E:06:1B:2F:46:C2:61:77:C4:34:AF:B3:69:7A:74:23:CA:55:F2:A6:2E:2B:7F:F0:59:9F:1C:A1:B6:53:D1:1A:01:42:1F:EA:61:0B:24:35:04:79:70:7D:4F:9C:BE:C2:97:90:40:7B:D3:EE:57:20:F9:23:38:C6:5A:4D:55:B9:07:90:22:64:3D:A6:8F:11:89:0E:1C:E2:E1:E4:39:F3:A5:A7:26:22:02:E2:2E:F0:E4:B5:46:38:79:FC:F4:50:E4:96:6A:F6:81:0E:26:00:C1:50:F7:4C:14:B4:72:CB:6A:28:0D:93:BE:EF:5C:27:95:A6:19:56:74:28:C8:D2:D9:8C:28:11:5C:6B:7C:32:57:9C:6D:AA:73:1C:5F:95:92:B2:A1:AC:73:CD:6F:D7:67:14:10:1D:4F:B7:61:00:4C:61:95:70:E0:5B:6A:53:C6:A7:85:3B:70:88:EB:1C:0C:95:3B:46:82:D0:C5:A3:AC:DA:DB:5D:E8:D3:6A:62:36:36:0C:AA:61:44:FD:4D:FB:F6:B5:86:A5:D9:DA:A3:0B:A9:63:CA:DE:C5:59:D6:77:40:9A:A3:7B:45:BD:98:61:FB:C3:05:BC:88:14:AF:7D:E8:45:E9:C6:B0:74:20:F7:54:CE:6D:9C:6F:91:A9:91:AD:86:B8:1D:28:AC:D8:D1:30:15:FD:08:F1:88:0D:DC:D5:DF:F4:98:AF:D7:E5:4D:B7:48:EC:65:4C:38:05:12:6D:D8:8D:63:D3:39:90:69:F6:81:CB:EB:38:CC:43:E6:1D:13:61:02:92:91:D8:05:B8:40:DD:33:BE:98:7E:4F:65:14:C7:CF:B7:DC:D4:E3:46:1A:F0:34:E0:87:0A:53:A6:7F:BA:8B:A8:6F:EC:CD:F7:C0:80:4A:36:F0:F1:56:EE:46:E1:40:0F:71:F9:DD:C7:F3:89:D4:2E:B9:F7:2E:BC:87:00:3Dparm: h2c_timeout:H2C sgdma timeout in seconds, default is 10 sec. (uint)parm: c2h_timeout:C2H sgdma timeout in seconds, default is 10 sec. (uint)parm: poll_mode:Set 1 for hw polling, default is 0 (interrupts) (uint)parm: interrupt_mode:0 - Auto , 1 - MSI, 2 - Legacy, 3 - MSI-x (uint)parm: enable_st_c2h_credit:Set 1 to enable ST C2H engine credit feature, default is 0 ( credit control disabled) (uint)parm: desc_blen_max:per descriptor max. buffer length, default is (1 << 28) - 1 (uint)So, my question is: why isn't this device showing up as a PCI device on my system, even though XDMA is working correctly? Am I missing some thunderbolt firmware or something? Any ideas? I have included the lspci output below for posterityCode:$ sudo lspci -v00:1c.0 PCI bridge: Intel Corporation Device 9dba (rev f0) (prog-if 00 [Normal decode])Flags: bus master, fast devsel, latency 0, IRQ 122Bus: primary=00, secondary=01, subordinate=01, sec-latency=0I/O behind bridge: Memory behind bridge: a0100000-a01fffff [size=1M]Prefetchable memory behind bridge: Capabilities:  Express Root Port (Slot+), MSI 00Capabilities:  MSI: Enable+ Count=1/1 Maskable- 64bit-Capabilities:  Subsystem: Hewlett-Packard Company Device 8514Capabilities:  Power Management version 3Capabilities:  Advanced Error ReportingCapabilities:  Access Control ServicesCapabilities:  Precision Time MeasurementCapabilities:  L1 PM SubstatesCapabilities:  Secondary PCI ExpressCapabilities:  Downstream Port ContainmentKernel driver in use: pcieport00:1c.4 PCI bridge: Intel Corporation Cannon Point-LP PCI Express Root Port #5 (rev f0) (prog-if 00 [Normal decode])Flags: bus master, fast devsel, latency 0, IRQ 123Bus: primary=00, secondary=02, subordinate=6c, sec-latency=0I/O behind bridge: 00004000-00006fff [size=12K]Memory behind bridge: 70000000-9e0fffff [size=737M]Prefetchable memory behind bridge: 0000004000000000-0000004049ffffff [size=1184M]Capabilities:  Express Root Port (Slot+), MSI 00Capabilities:  MSI: Enable+ Count=1/1 Maskable- 64bit-Capabilities:  Subsystem: Hewlett-Packard Company Cannon Point-LP PCI Express Root PortCapabilities:  Power Management version 3Capabilities:  Advanced Error ReportingCapabilities:  Access Control ServicesCapabilities:  Precision Time MeasurementCapabilities:  Secondary PCI ExpressCapabilities:  Downstream Port ContainmentKernel driver in use: pcieport00:1d.0 PCI bridge: Intel Corporation Cannon Point-LP PCI Express Root Port #13 (rev f0) (prog-if 00 [Normal decode])Flags: bus master, fast devsel, latency 0, IRQ 124Bus: primary=00, secondary=6d, subordinate=6d, sec-latency=0I/O behind bridge: Memory behind bridge: a0000000-a00fffff [size=1M]Prefetchable memory behind bridge: Capabilities:  Express Root Port (Slot+), MSI 00Capabilities:  MSI: Enable+ Count=1/1 Maskable- 64bit-Capabilities:  Subsystem: Hewlett-Packard Company Cannon Point-LP PCI Express Root PortCapabilities:  Power Management version 3Capabilities:  Advanced Error ReportingCapabilities:  Access Control ServicesCapabilities:  Precision Time MeasurementCapabilities:  L1 PM SubstatesCapabilities:  Secondary PCI ExpressCapabilities:  Downstream Port ContainmentKernel driver in use: pcieport01:00.0 Unassigned class : Realtek Semiconductor Co., Ltd. RTS525A PCI Express Card Reader (rev 01)DeviceName: Realtek PCIE CardReaderSubsystem: Hewlett-Packard Company RTS525A PCI Express Card ReaderFlags: bus master, fast devsel, latency 0, IRQ 130Memory at a0100000 (32-bit, non-prefetchable) [size=4K]Capabilities:  Power Management version 3Capabilities:  MSI: Enable+ Count=1/1 Maskable- 64bit+Capabilities:  Express Endpoint, MSI 00Capabilities:  Advanced Error ReportingCapabilities:  Device Serial Number 00-00-00-01-00-4c-e0-00Capabilities:  Latency Tolerance ReportingCapabilities:  L1 PM SubstatesKernel driver in use: rtsx_pciKernel modules: rtsx_pci02:00.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) (prog-if 00 [Normal decode])Physical Slot: 8Flags: bus master, fast devsel, latency 0, IRQ 16Bus: primary=02, secondary=03, subordinate=6c, sec-latency=0I/O behind bridge: 00004000-00005fff [size=8K]Memory behind bridge: 70000000-9e0fffff [size=737M]Prefetchable memory behind bridge: 0000004000000000-0000004049ffffff [size=1184M]Capabilities:  Power Management version 3Capabilities:  MSI: Enable- Count=1/1 Maskable- 64bit+Capabilities:  Subsystem: Hewlett-Packard Company JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016]Capabilities:  Express Upstream Port, MSI 00Capabilities:  Device Serial Number cf-dd-68-09-50-b7-d0-00Capabilities:  Advanced Error ReportingCapabilities:  Virtual ChannelCapabilities:  Power Budgeting <?>Capabilities:  Vendor Specific Information: ID=1234 Rev=1 Len=0d8 <?>Capabilities:  Latency Tolerance ReportingCapabilities:  Secondary PCI ExpressKernel driver in use: pcieport03:00.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) (prog-if 00 [Normal decode])Flags: bus master, fast devsel, latency 0, IRQ 125Bus: primary=03, secondary=04, subordinate=04, sec-latency=0I/O behind bridge: Memory behind bridge: 9e000000-9e0fffff [size=1M]Prefetchable memory behind bridge: Capabilities:  Power Management version 3Capabilities:  MSI: Enable+ Count=1/1 Maskable- 64bit+Capabilities:  Subsystem: Hewlett-Packard Company JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016]Capabilities:  Express Downstream Port (Slot+), MSI 00Capabilities:  Device Serial Number cf-dd-68-09-50-b7-d0-00Capabilities:  Advanced Error ReportingCapabilities:  Virtual ChannelCapabilities:  Power Budgeting <?>Capabilities:  Vendor Specific Information: ID=1234 Rev=1 Len=0d8 <?>Capabilities:  Secondary PCI ExpressKernel driver in use: pcieport03:01.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) (prog-if 00 [Normal decode])Flags: bus master, fast devsel, latency 0, IRQ 126Bus: primary=03, secondary=05, subordinate=37, sec-latency=0I/O behind bridge: 00004000-00004fff [size=4K]Memory behind bridge: 70000000-87efffff [size=383M]Prefetchable memory behind bridge: 0000004000000000-000000401fffffff [size=512M]Capabilities:  Power Management version 3Capabilities:  MSI: Enable+ Count=1/1 Maskable- 64bit+Capabilities:  Subsystem: Hewlett-Packard Company JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016]Capabilities:  Express Downstream Port (Slot+), MSI 00Capabilities:  Device Serial Number cf-dd-68-09-50-b7-d0-00Capabilities:  Advanced Error ReportingCapabilities:  Virtual ChannelCapabilities:  Power Budgeting <?>Capabilities:  Vendor Specific Information: ID=1234 Rev=1 Len=0d8 <?>Capabilities:  Secondary PCI ExpressKernel driver in use: pcieport03:02.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) (prog-if 00 [Normal decode])Flags: bus master, fast devsel, latency 0, IRQ 127Bus: primary=03, secondary=38, subordinate=38, sec-latency=0I/O behind bridge: Memory behind bridge: 87f00000-87ffffff [size=1M]Prefetchable memory behind bridge: Capabilities:  Power Management version 3Capabilities:  MSI: Enable+ Count=1/1 Maskable- 64bit+Capabilities:  Subsystem: Hewlett-Packard Company JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016]Capabilities:  Express Downstream Port (Slot+), MSI 00Capabilities:  Device Serial Number cf-dd-68-09-50-b7-d0-00Capabilities:  Advanced Error ReportingCapabilities:  Virtual ChannelCapabilities:  Power Budgeting <?>Capabilities:  Vendor Specific Information: ID=1234 Rev=1 Len=0d8 <?>Capabilities:  Secondary PCI ExpressKernel driver in use: pcieport03:04.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) (prog-if 00 [Normal decode])Flags: bus master, fast devsel, latency 0, IRQ 128Bus: primary=03, secondary=39, subordinate=6c, sec-latency=0I/O behind bridge: 00005000-00005fff [size=4K]Memory behind bridge: 88000000-9dffffff [size=352M]Prefetchable memory behind bridge: 0000004020000000-0000004049ffffff [size=672M]Capabilities:  Power Management version 3Capabilities:  MSI: Enable+ Count=1/1 Maskable- 64bit+Capabilities:  Subsystem: Hewlett-Packard Company JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016]Capabilities:  Express Downstream Port (Slot+), MSI 00Capabilities:  Device Serial Number cf-dd-68-09-50-b7-d0-00Capabilities:  Advanced Error ReportingCapabilities:  Virtual ChannelCapabilities:  Power Budgeting <?>Capabilities:  Vendor Specific Information: ID=1234 Rev=1 Len=0d8 <?>Capabilities:  Secondary PCI ExpressKernel driver in use: pcieport04:00.0 System peripheral: Intel Corporation JHL6540 Thunderbolt 3 NHI (C step) [Alpine Ridge 4C 2016] (rev 02)Subsystem: Hewlett-Packard Company JHL6540 Thunderbolt 3 NHI (C step) [Alpine Ridge 4C 2016]Flags: bus master, fast devsel, latency 0, IRQ 16Memory at 9e000000 (32-bit, non-prefetchable) [size=256K]Memory at 9e040000 (32-bit, non-prefetchable) [size=4K]Capabilities:  Power Management version 3Capabilities:  MSI: Enable- Count=1/1 Maskable- 64bit+Capabilities:  Express Endpoint, MSI 00Capabilities:  MSI-X: Enable+ Count=16 Masked-Capabilities:  Device Serial Number cf-dd-68-09-50-b7-d0-00Capabilities:  Advanced Error ReportingCapabilities:  Virtual ChannelCapabilities:  Power Budgeting <?>Capabilities:  Vendor Specific Information: ID=1234 Rev=1 Len=088 <?>Capabilities:  Latency Tolerance ReportingKernel driver in use: thunderboltKernel modules: thunderbolt38:00.0 USB controller: Intel Corporation JHL6540 Thunderbolt 3 USB Controller (C step) [Alpine Ridge 4C 2016] (rev 02) (prog-if 30 )Subsystem: Hewlett-Packard Company JHL6540 Thunderbolt 3 USB Controller (C step) [Alpine Ridge 4C 2016]Flags: bus master, fast devsel, latency 0, IRQ 132Memory at 87f00000 (32-bit, non-prefetchable) [size=64K]Capabilities:  Power Management version 3Capabilities:  MSI: Enable+ Count=1/8 Maskable- 64bit+Capabilities:  Express Endpoint, MSI 00Capabilities:  Device Serial Number cf-dd-68-09-50-b7-d0-00Capabilities:  Advanced Error ReportingCapabilities:  Virtual ChannelCapabilities:  Power Budgeting <?>Capabilities:  Vendor Specific Information: ID=1234 Rev=1 Len=0d8 <?>Capabilities:  Latency Tolerance ReportingCapabilities:  Secondary PCI ExpressKernel driver in use: xhci_hcdKernel modules: xhci_pci

author: abyrvalg
author_rank: Frequent Contributor
timestamp: October 24, 2021, 08:55:29 am
content: The XDMA driver has nothing with device not showing in lspci (the driver can just sit in memory waiting for any device from it’saliaseslist to appear), the problem is either in Thunderbolt or FPGA board. Try checkingdmesgandboltctloutput after plugging the device in to see is there anything other than the TB controller itself. You can try plugging an empty TB enclosure first and checking those two util’s outputs to get a reference point, then look for differences when you plug the enclosure with FPGA up and running.

author: SMB784
author_rank: Frequent Contributor
timestamp: October 24, 2021, 08:24:19 pm
content: Quote from: abyrvalg on October 24, 2021, 08:55:29 amThanks for the heads up, I read about doing that last night before bed, and woke up to your message.boltctl yields no output, regardless of whether or not the FPGA is attached.dmesg yields nearly identical outputs with or without the FPGA, only difference is the device number, and no mention of the thunderbolt enclosure, just the USB-C controller (a TPS65983) on the same board as the Thunderbolt chip in the enclosure.dmesg without the FPGA attached:Code:[ 748.079731] usb 1-3: new low-speed USB device number 6 using xhci_hcd[ 748.231809] usb 1-3: No LPM exit latency info found, disabling LPM.[ 748.238688] usb 1-3: New USB device found, idVendor=8087, idProduct=0000, bcdDevice= 4.51[ 748.238706] usb 1-3: New USB device strings: Mfr=2, Product=3, SerialNumber=1[ 748.238713] usb 1-3: Product: TPS65983[ 748.238719] usb 1-3: Manufacturer: Texas Instruments[ 748.238724] usb 1-3: SerialNumber: FD1C701466D2DCA4394575BE15664075dmesg with the FPGA attached:Code:[ 975.351287] usb 1-3: new low-speed USB device number 7 using xhci_hcd[ 975.504061] usb 1-3: No LPM exit latency info found, disabling LPM.[ 975.510403] usb 1-3: New USB device found, idVendor=8087, idProduct=0000, bcdDevice= 4.51[ 975.510421] usb 1-3: New USB device strings: Mfr=2, Product=3, SerialNumber=1[ 975.510428] usb 1-3: Product: TPS65983[ 975.510433] usb 1-3: Manufacturer: Texas Instruments[ 975.510439] usb 1-3: SerialNumber: FD1C701466D2DCA4394575BE15664075Would the absence of an output from boltctl indicate that my system isn't recognizing my thunderbolt enclosure? I have tried it on all 3 USB ports and gotten the same result (two of them are USB-C, one is regular USB). The laptop model is an HP Spectre x360 13t (model #: 13t-ap000), and its running Ubuntu 20.04 HWE (kernel 5.11.0-38-generic). BIOS tells me that the thunderbolt controller has firmware version 1F-NVM46.00 (see attached image).Apparently there's an update for it, so I'll try that. Maybe it will help.It did not help. The Thunderbolt chip in the enclosure is a JHL6340, and lspci is showing a JHL6540, so I presume the JHL6540 is the thunderbolt controller chip on the laptop. More evidence that the enclosure isn't being detected, I suppose.

author: SMB784
author_rank: Frequent Contributor
timestamp: October 28, 2021, 01:57:09 am
content: Alright so it turns out that the issue was the cable connecting the Thunderbolt enclosure + SQRL Acorn to my computer. Once I used the stock cable that came with the enclosure, it recognized it just fine. I had pre-loaded the nitefury core from the stock .mcs file found on the github (https://github.com/RHSResearchLLC/NiteFury-and-LiteFury/tree/master/Sample-Projects/Project-0/FPGA-A200T-3/mcs), and lspci gives an output that lists the device ID of the XDMA core loaded onto the FPGA, demonstrating that the FPGA is showing up as a PCI connected device.However, when I try to use spi-loader (https://github.com/RHSResearchLLC/NiteFury-and-LiteFury/tree/master/spi-loader/linux/sw/build) to upload a copy of the same out.mcs from the aforementioned github link, I get an error (see attached image).Not sure what the deal is with that yet, as the XDMA driver is indeed installed and working (and even recognizes the FPGA, and runs DMA tests on it that actually pass) but at least this is progress.

author: SMB784
author_rank: Frequent Contributor
timestamp: October 28, 2021, 11:35:42 pm
content: I fixed the error I described in my previous post. Apparently /dev/xdma0_user needed read/write permissions before it would allow me to upload a bitstream via the thunderbolt connection. However, the new problem is that uploading a bitstream appears to crash my computer. More on that as I find out.

author: SMB784
author_rank: Frequent Contributor
timestamp: October 30, 2021, 03:51:02 pm
content: Quote from: SMB784 on October 28, 2021, 11:35:42 pmNothing shows up in the logs during the lock-up/crash, and the device is being properly detected as a PCI card, so I'm not quite sure whats happening here. Checked htop, it crashes so fast that there's time for htop to update cpu/ram usage for any running processes. Log/crash behavior evidence attached. So close, if we can get this worked out I think this thunderbolt enclosure will be an excellent way to turn this into a very workable dev board.

author: SMB784
author_rank: Frequent Contributor
timestamp: November 06, 2021, 10:45:16 pm
content: Alright so after hitting a dead end trying to upload the Nitefury github repo via PCIe, I gave up and installed LiteX.That went much more successfully. I was able to communicate with the SQRL in the thunderbolt enclosure via the thunderbolt USB-C cable, and I was also able to upload new bitstreams via the PCIe connection (avoiding the need for a separate JTAG), and do a dma test (see attached photo).The SQRL Acorn is now officially a USB connected PCIe FPGA. I am currently working on integrating the LiteX PCIe core into my basic loadout bitstream so that once flashed the SQRL Acorn can be fully tested, including all GPIO outputs, PCIe connection, and DMA. I will update the github when I am finished, and merge this into a separate post.

author: Teknoman117
author_rank: Contributor
timestamp: November 13, 2021, 07:18:25 pm
content: I never actually managed to get the NiteFury (A200T) project to work on the CLE-215+. This includes even setting the LEDs. The A100T project did work on the LiteFury I bought last year.

author: SMB784
author_rank: Frequent Contributor
timestamp: November 13, 2021, 07:49:14 pm
content: Quote from: Teknoman117 on November 13, 2021, 07:18:25 pmYeah I spoke with Dave Reynolds of RHS Research (he runs the Nitefury project), and he said that he had to do some black magic with the spi-loader program to get it to properly interface with the SQRL board, and he couldn't remember how to do it anymore, so that wound up as a dead end.But, I figured a way around this issue. Litepcie provided by LiteX works just fine (in fact its a smaller core than the Xilinx PCIe via XDMA). I was able to integrate this with my thunderbolt enclosure, and now I have a USB-C programmable FPGA with full speed x4 lane PCIe connection. I described this in a separate thread on this forum:https://www.eevblog.com/forum/fpga/pcie-over-usb-interface-for-sqrl-acornnitefury-cle-215()/

author: Teknoman117
author_rank: Contributor
timestamp: November 14, 2021, 08:45:39 pm
content: From you other pictures you posted, I'm curious how you removed the thermal epoxy holding the heatsink down without ruining anything? The stock heatsink+fan is terribly annoying...

author: SMB784
author_rank: Frequent Contributor
timestamp: November 14, 2021, 10:13:34 pm
content: Its not really epoxy, its actually just very viscous thermal paste (it is soluble in isopropanol too). A slight twisting motion and some patience was enough to get it off for me. I have done it successfully twice as of today, once on a CLE-215 and once on a CLE-215+ without issue. No guarantees though.

author: randomengineer6
author_rank: Newbie
timestamp: November 20, 2021, 08:48:25 pm
content: Quote from: SMB784 on November 14, 2021, 10:13:34 pmIs the CLE-215 just a different speed grade of the XC7A200 and do you know whether its the same RAM chip as the CLE-215+?

author: SMB784
author_rank: Frequent Contributor
timestamp: November 21, 2021, 03:34:13 am
content: Quote from: randomengineer6 on November 20, 2021, 08:48:25 pmYes the 215-CLE+ is the speed grade 3 variant of the XC7A-200T, and the 215-CLE is the speed grade 2 variant.To my knowledge, the RAM chips are mt41k512m16ha-125 ait:a in both.

author: NiHaoMike
author_rank: Super Contributor
timestamp: November 21, 2021, 12:54:36 pm
content: Quote from: Teknoman117 on November 14, 2021, 08:45:39 pmThe fan is easy to remove, then 3D print an adapter to attach a larger, quieter fan. Most likely some sort of centrifugal fan would be the best fit.