DDR3 routing - lets discuss.... - Page 1
Forum section: electronics / projects

author: Northy
author_rank: Regular Contributor
timestamp: September 16, 2021, 11:29:23 am
content: Hi all,I've done a lot of reading about routing a processor to single DDR3 interface and have a pretty good handle on it, but when it has actually come to physically routing it it's not as simple.I've got all the Data and Data Mask signals routed on a single layer and all length matched nicely - all good here.I'm now trying to route the Address and Command signals. These have a resistor inline, and this is where I'm coming across an issue. I'd imagine the ideal way to length match these signals is to length match the traces either side of the inline resistor, but in reality I just don't really have the space to do that. So would it actually make any difference if I added the two trace lengths together (either side of the resistor) and matched the entire length from the processor to the DDR3?orMany thanks,G(Not George)

author: epongenoir
author_rank: Contributor
timestamp: September 16, 2021, 12:19:10 pm
content: Hi G! (Not George)It doesn't matter where you put the resistor as long as the length is matched, it's not like multi-GHz differential signals where you have to have symmetry between the + and - signals.G (I'm not George either..)

author: Scrts
author_rank: Frequent Contributor
timestamp: September 16, 2021, 01:45:56 pm
content: If you have a chance, try to length match up to resistor and then length match behind it. If you can't - it won't make much difference, since I bet the device is not far away from the processor anyway.

author: BrianHG
author_rank: Super Contributor
timestamp: September 16, 2021, 10:03:29 pm
content: Just in case some want a visualization, asmi placed a useful graphic on the topic here:https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/msg3608794/#msg3608794Note than in my example design, I only have a balanced terminator resistor on the DDR_CK lines and that resistor is close to the DDR3 ram chips. Though FPGA used in my circuit has programmable drive strength removing the need for series resistors on the control lines.

author: Northy
author_rank: Regular Contributor
timestamp: September 21, 2021, 03:59:34 pm
content: Thanks for the replies, very helpful!Regards,G(Not George)

author: Northy
author_rank: Regular Contributor
timestamp: May 31, 2022, 08:15:37 pm
content: I'd like to bring this back from the dead again if I may, as I'm back working on this and have learnt some new stuff - which has created more questions.My objective is to route one Sharc processor to a single DDR3 memory chip. Since posting last I've realised that the preferred (Jedec) way is no inline resistors, but a fly by routing and termination resistors to VTT (1/2 supply) after the DDR3 on the address and control lines.I'm using Eagle to do the design so don't have the ability to check the impedance matching, so based on that I'm routing using the following details/rules:Board Layer:DDR Signal:Signal TopGround 1Inner 1 Address, Command and ControlPower 1 Can I route DQS lines on this layer?Ground 2Inner 2 Data byte lanesPower 2Signal BottomMy aim is to keep all the same family signals on the same internal layer to simplify the impedance matching. The traces that need to be a certain impedance will be the only ones drawn a particular width and the board house 'tweaks' the gerbers to get the desired impedance required.I plan to:Have my clock lines longer than my address, command and control lines, matched to +/-10mils and 100ohm impedance.Have my address, command and control lines matched to +/-40mils and 50ohm impedance.Have my byte lanes shorter than my address, command and control lines and matched to +/-40mils and 50ohm impedance.Does that sound like a good plan?Can I route the DQS lines on the layer named Power 1? Or must they be routed with the data lines? They would be routed next to a ground layer (Ground 2) and the data lines would be routed next to Ground 1.I've read various things about how these rules are not too critical, but I'm trying to do the best job I can to give the design the most amount of margin.I've been studying evaluation board layouts and they don't seem to keep the data and address, command and control signals all routed on their own layers, but perhaps this doesn't matter if their software can check to ensure the impedance is correct?Does anyone have any thoughts or feedback on my plans? I know this isn't something that everyone has done before.Many thanks,G

author: Northy
author_rank: Regular Contributor
timestamp: June 06, 2022, 04:30:58 pm
content: Are there any people on here who have routed DDR3 who could have a look over this please?Would I be better routing the DQS lines on Signal Top rather than Power 1? I'm feeling that might be better.Thanks,G

author: nctnico
author_rank: Super Contributor
timestamp: June 06, 2022, 05:40:17 pm
content: You have to use a different approach. It is far better to keep DDR signals ground referenced.What could work is:1 top: data + clock2 ground3 inner 1: data4 ground5 power 16 power 27 ground8 bottom address + control

author: Northy
author_rank: Regular Contributor
timestamp: June 07, 2022, 10:18:02 am
content: Quote from: nctnico on June 06, 2022, 05:40:17 pmWould you mind explaining your thinking behind this? I'd like to learn.At the moment, I have this:Board Layer:DDR Signal:Signal Top. DQS impedance matched pairsGround 1Inner 1 Address, Command and ControlPower 1Ground 2Inner 2 Data byte lanesPower 2Signal BottomCan this be improved?G