Emulating HP 372x PRNG & Spectrum Display - Page 1
Forum section: electronics / projects

author: dazz1
author_rank: Frequent Contributor
timestamp: August 01, 2025, 04:09:43 am
content: This is continuation of a thread started here:https://www.eevblog.com/forum/rf-microwave/white-noise-generator-is-there-a-chip-combining-lfsrs-and-analog-output/This thread covers the design of an emulator of a HP 3720A Spectrum Display and a HP 3722A Pseudo Random Noise Generator for operation with a HP 3721A Correlator.

author: somejoe
author_rank: Contributor
timestamp: August 01, 2025, 04:31:21 am
content: Quote from: dazz1 on August 01, 2025, 04:09:43 amAs part of the effort to build an HP-3722, it would be worthwhile to examine other versions of this instrument.The "H01" version provides a Delay Code [0 0 0 +] mechanical counter on the front panel.HP application note AN98-2, "Noise at Work A point by point correlator for the H01-3722A", 1969,states that:"Selection of the shift register outputs to be added is performed by a group of decade switches on thefront panel. These switches, which are set according to a conversion table supplied with the instrument,provide a useful number of delays ranging from zero to the number of bits (N) in the sequence in use".So I am looking for a copy of the conversion table and/or the service manual for the "H01" version ofthe 3722A instrument.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 01, 2025, 07:48:12 am
content: Quote from: somejoe on August 01, 2025, 04:31:21 amI agree. I am sure I have seen a reference to a HO2 version, but can't find it again.QuoteI think all that is needed is the block diagram and the equations. All that is in software.I think the most important starting point is to define the hardware interfaces. The digital I/O and the coax connectors.Should there also be a:GPIB connector?Ethernet?USB?Wifi / Bluetooth?I would start with a Aliexpress dev board. I would choose a DSPic but that is not the only option.I would write the core software including the GUI, then breadboard the interfaces to the real world.I would do the design so an emulated instrument can be connected to a real instrument, or another emulated instrument.I am a big fan of "Fitted for, but not with" (FFBNW) pcb designs.PCB area is cheap. I would design the HP 372x pcbs so one design could be used to implement any one of the 372x instruments. This likely means not all parts fitted, depending on the instrument.Usually min pcb MOQ is 5x so one pcb design = one pcb order. That will reduce R&D, build effort, and build cost.I would implement a soft graphical user interface (mouse and screen) to headless instruments via Ethernet/USB/Wifi/Bluetooth/GPIB. This would allow multiple skins to be applied. It would allow a stack of HP372x, each in their own window, to be assembled on a single LCD monitor, as if it was the real thing.

author: radiolistener
author_rank: Super Contributor
timestamp: August 01, 2025, 07:52:48 am
content: Which specific polynomial does the HP 372x noise generator use for its LFSR? If you can provide the exact parameters, I’d be happy to help write a script to generate and analyze its spectrum.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 01, 2025, 08:04:45 am
content: Quote from: radiolistener on August 01, 2025, 07:52:48 amThat is not a trivial question to answer for the HP 3722. The exact gains applied to each stage are set with precision resistors, so exact parameters would require some work to convert resistor values to gains. Not hard, just time and effort.A better approach would be to look at the design info in HP journals and manuals and figure out the exact theoretical values. No need for resistors with dsp. Just AND the stage gains with the digital stream, and sum all of the stage outputs. That can all be done in code. No analog. No need for a bucket of precision weird value resistors.The digital stream parameters are in the manuals and (I think) journals.I think the most code will end up running the GUI as a web server on the emulator.

author: ch_scr
author_rank: Frequent Contributor
timestamp: August 01, 2025, 09:10:58 am
content: I guess you've come across this app note. Block diag and equations galorehttps://hpmemoryproject.org/an/pdf/an_98-2.pdf

author: dazz1
author_rank: Frequent Contributor
timestamp: August 02, 2025, 09:11:08 am
content: Digital I/O Pinout between the HP 372x instruments.There are also BNC connections.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 02, 2025, 09:15:03 am
content: HiHP 3720A block diagram.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 02, 2025, 09:16:30 am
content: Operator Manual for HP 3720AI can't upload the Service Manual because the file is too big.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 02, 2025, 09:21:17 am
content: Photo of the HP 3720

author: dazz1
author_rank: Frequent Contributor
timestamp: August 02, 2025, 09:28:02 am
content: Some PRNG algorithm papers.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 02, 2025, 09:30:16 am
content: App Note for HP 3722A

author: dazz1
author_rank: Frequent Contributor
timestamp: August 02, 2025, 09:32:42 am
content: HP US Patents

author: dazz1
author_rank: Frequent Contributor
timestamp: August 02, 2025, 09:56:09 am
content: HP 3721 Correlator User Manual

author: somejoe
author_rank: Contributor
timestamp: August 02, 2025, 02:20:13 pm
content: Found a good description of the instrument in question in the HP "New Electronics for Measurement Analysis Computation", Autumn 1968 publication.

author: somejoe
author_rank: Contributor
timestamp: August 02, 2025, 02:24:04 pm
content: Quote from: dazz1 on August 02, 2025, 09:28:02 amThank you - all great sources.I am going to dig a little dipper into the HP-3722A digital section to figure out the LFSR structure and polynomials used.May take some time as there are 17 front panel settings.

author: somejoe
author_rank: Contributor
timestamp: August 02, 2025, 06:55:53 pm
content: Quote from: radiolistener on August 01, 2025, 07:52:48 amThank you for your offer - the polynomials for the HP-3722A listed below and attached.Additionally, the front panel of another instrument HP-1930A which matches the polynomials of the 3722A.Software implementation:https://liquidsdr.org/doc/msequence/Hp-3722A Sequence Length-----------------------------------m n poly2 3 1,23 7 2,34 15 3,45 31 3,56 63 5,67 127 6,78 255 2,3,4,5 [8,6,5,4] [8.6.5.4]9 511 5,910 1023 7,1011 2047 9,1112 4095 2,10,11,12 [12.11,10,4] [12,6,4,1]13 8191 1,11,12,13 [13,12,11,8]14 16383 2,12,13,1415 32767 14,15 [15,4]16 65535 11,13,14,16 [16,15,13,4]17 131071 14,1718 262143 11,1819 524287 14,17,18,1920 1048575 17,2021 2,097,151 21,1922 4,194,303 22,2123 8,388,607 23,1824 16,777,215 24,23,22,1725 33,554,431 25,3 [25,22]26 67,108,863 26,6,2,127 134,217,727 27,5,2,128 268,435,455 28,329 536,870,911 29,230 1,073,741,823 30,6,4,131 2,147,483,647 31,3The polynomials in brackets are alternate set of taps that produce the same result.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 03, 2025, 01:51:15 am
content: HiAttached is a Aliexpress DSP development board. For me, this would be the fastest, easiest, cheapest development path.I think I would pair this with a ESP32 to separate DSP from UI and housekeeping.So this would require a father PCB to interface the real world signals to the processors. The father board should be low tech, low risk, low cost etc.All the complexity goes into the software.With enough spare interfaces, it should be possible to allow for the option of building a hardware emulator of the front panels of the HP 372x. Physical knobs, switches, LCD CRT, connectors etc. I wouldn't build that, but practically zero cost to FFBNW (Fit For But Not With).Aliexpress does FPGAs but they cost a lot more. DSPic33 are cheap. I don't know if DSPic33 has enough power to do the job.If someone came up with a low cost, low learning curve FPGA, I'd go along with that.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 03, 2025, 01:59:45 am
content: HiThe other parameters required are the digital finite impulse response filter.One of the things done in these instruments was to limit word lengths (bits) because every bit added required a truck load of ICs. That limitation doesn't apply to DSP devices.So I don't think it would be good to do a bit for bit emulation.Bit for bit emulation could be a software option.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 03, 2025, 03:38:04 am
content: HiAttached is the manual pages for the HP 3722A describing the digital audio output filter. The digital filter takes outputs from the same shift register as the PRNG.The filter is sinx /x.The length of the filter is truncated to 32bits keep the bit count low.The weightings (gains) are set with resistors. No need to do that in software.The output values include negatives. In the circuit, there is a negative amplifier to generate these. Then the positive and negative values are summed. Not required in software.So to implement this would require the same shift register used to generate the PRNG values to be applied to sinx/x gains along the length of the shift register (say 64bits).So even if the PRNG shift register is 15 or 31 bits, the output filter shift register remains the same bit length (eg 64 bits). When the 3722 was built, a 64bit shift register was really expensive. Not so much now.

author: somejoe
author_rank: Contributor
timestamp: August 03, 2025, 04:37:25 am
content: Quote from: dazz1 on August 03, 2025, 03:38:04 amTo add one more wrinkle, how is the value from the "Delay Code [0 0 0 +]" implemented to modify the bitstream - i.e what are the valid settings, and, how is the +/1 setting used?And lastly, how does the "Sequences Per Gate Interval [1 2 4 8]" implemented? Does it affect both the delayed as well as the binary outputs? In other words, two separate timing marks for the same signal?

author: ch_scr
author_rank: Frequent Contributor
timestamp: August 03, 2025, 06:26:53 am
content: Quote from: dazz1 on August 03, 2025, 01:51:15 amI recommend looking at the GOWIN FPGAs. There is even a open-source toolkit (with reduced functionality, and a bit of a hassle to get going),but the official IDE just works and is not overloaded with buttons. There is an "EDU" version that supports the board linked below,but they have supplied free licenses (just send a email) for the "full kit". The IDE even comes for Win and Linux.This is one of the smaller boards "Tang nano 9k"

author: dazz1
author_rank: Frequent Contributor
timestamp: August 03, 2025, 07:31:03 am
content: Quote from: somejoe on August 03, 2025, 04:37:25 amI don't know, but I would put words into a circular FIFO buffer. A pair of pointers increments with the clock rate. The delay can be as long as the FIFO is deep.The digital filter shift register stays the same length of bits.So my reading of the Gate feature is that it is single shot (push the button). It will run a bit stream for as many bits as specified [1,2,4,8 ...]If you are asking how the circuit is implemented, I wouldn't even go there. Flip-flops are implemented as canned transistors. Just stick to the maths.My thoughts are there are two levels of emulation of the HP 3720A, HP 3721A, HP 3722A, software defined.Exact emulation warts and all. Bit for bit emulation.Functional emulation where the warts are removed and the instruments achieve what the original designers would like to have achieved.Both versions of all three instruments should run on the same hardware.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 03, 2025, 08:14:19 am
content: Quote from: ch_scr on August 03, 2025, 06:26:53 amJust looking at the pin count of the Tang nano board. Based on the shallowest of analysis, there aren't many pins.Xilenx / Altera is also available on Aliexpress. Is that an option? I know what a FPGA is, but haven't used one.

author: ch_scr
author_rank: Frequent Contributor
timestamp: August 03, 2025, 08:41:58 am
content: Quote from: dazz1 on August 03, 2025, 08:14:19 amHow many fast pins do you need, really? All the "core" stuff is serial anyway, no?And the configuration pins could be shifted in/out from port-expanders if parallel pins are really needed.I started from the same point and was lured in by the price. Wasn't a bad experience, the software is approachable.Basically thought myself Verilog with that andabout 5 episodes of this Indian university course.That got my far enough to make a frequency counter, which even fit in the 1k device. The 9k is big enoughto house a C64.They have ever bigger ones, at higher prices.The 20kis a smaller of the bigger ones.Seems to be in a sweet spot for pin count, the even bigger ones then come as PCIe cards etc.That said there is only a choice of "Verilog or VHDL" as programming language anyway, and most of what you'll (need to) learn is transferable to the other platforms if need be.The "software hell" of the classical Vendors is what kept me from stepping in, supposeto the expertthe GOWIN IDE won't be as powerful, but it sure has a lot less buttons to worry about.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 03, 2025, 10:09:52 am
content: Quote from: ch_scr on August 03, 2025, 08:41:58 amAbout 38 pins for 1 to 1 to the digital ports plus BNC connectors.Yes these can definitely be expanded and serialised but this may make it more difficult to use one hardware design for all instruments. That needs more detailed analysis.Pairing a low cost ESP32 MCU with a FPGA/DSPic would immediately expand the pin I/O count. The problem with this approach is that it requires two development environments. That could be a real pain.Using an MCU and FPGA from (say) the Microchip range might make it a lot easier.It would be a lot easier to keep the signals on the FPGA/DSP, and the UI webserver on the MCU.If port expanders are required, it might be better to add a 2nd MCU to isolate the UI from the signal processing side. Using an MCU will probably be a lot easier than using individual chips for glue logic, like the old days.One of the key magnets to the DSPic33 family is the software libraries. They look like they could be Lego blocks of code. This was the primary attractor of DSPic 33.I think the project is a long way from choosing a technology solution. I am certainly not welded to the DSPic based solution.Although I am not interested in emulating a HP 3721A because I have one, I understand many don''t. Correlation and spectrum analysis are mathematically closely related, so I anticipate it should be easy to start with a HP 3720 Spectrum Display to end up with a HP 3721 Correlator.I don't see any point in limiting the emulator performance to match 1960s instrument capabilities. If modern hardware can process lots of MHz of signal, no point in hobbling itSimilarly, using a software UI means additional controls/displays can be optionally added/switched in to enhance the original instrument. There is ample opportunity for over engineering.As above, too early to be choosing solutions.

author: ch_scr
author_rank: Frequent Contributor
timestamp: August 03, 2025, 11:04:03 am
content: I certainly understood quickly that "things that are easy on a uC are hard on an FPGA" (and vice versa).So the "horses for courses" def. makes sense.Making a LFSR was easy, it was literally my "trial" project to make the on-board RGB led blink "random" colours.FPGAs in general are well suited to that part of it.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 04, 2025, 01:57:19 am
content: Attached is a proposed block diagram of an HP372x emulator. The aim is to create one hardware design for all three instruments.The block diagram is deliberately technology solution agnostic.The block diagram for the hardware will be the starting point for defining the system block diagram. (It should be the other way around.)

author: somejoe
author_rank: Contributor
timestamp: August 04, 2025, 02:59:09 am
content: Quote from: dazz1 on August 04, 2025, 01:57:19 amThank you for taking the initiative. A couple of thoughts:1. Add the capability of having an external noise source (additional connector) vs having an internal one, and, the capability to switch.2 May still want to have some external switches (need power on at least) and function buttons that can be programmed via software.3. is there an analog processing block anywhere? In parallel with the glue logic that makes use of the drivers/level shifters?4. the DSP should not be the only device that talks to the glue logic, the microcontroller needs to have the flexibility as well. For example, GPIB command execution.5. as part of the glue logic, do you want to include an FPGA block for future flexibility?6. lastly, some leds may want to be controlled directly from the glue logic.Cheers,

author: dazz1
author_rank: Frequent Contributor
timestamp: August 04, 2025, 04:13:14 am
content: Quote from: somejoe on August 04, 2025, 02:59:09 amAll good points, which is why the system signal flow diagram should be done before the hardware block diagram. It's floating around in my head.So point by point:1. What is the use case?2. There are probably going to be a few spare I/O pins, so making them available at a connector on the PCB would be an easy add. In my head, I am thinking all switches and variables are software read/controlled.3. There is going to have to be at least one DAC somewhere. Maybe inside the DSP chip, or the glue logic (also analogue processing).4. Agree. The MCU needs to control the glue logic, and the drivers.5. I think adding a 2nd FPGA would be a bridge too far. My plan is to use an Aliexpress dev board, because almost all the advanced DSP devices have BGA or really fine pin pitch that is not really practical for DIY builds. Buildability is one of the things that attracted me to the DSPic33 series. Adding a 2nd dev board would take up a lot of PCB real-estate that will probably not be populated. Probably easier to just build another emulator complete.6. Noting that the glue logic could end up being a MCU as a one chip solution, I don't think any LEDs should be controlled by the glue logic. It will make the code really messy if you have to go to different places to do similar things. Also LEDs controlled by the glue logic has the risk of locking functionality into hardware. I think leave all LED control to the main MCU. Let that do all the house keeping.Most of the BNC I/O is digital. There are analog pen plotter outputs and noise outputs, but most BNC signals are 12.5V digital. I think most will need to be connected to the DSP block because they are time critical.Writing the code, especially the GUI, will be the biggest task.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 04, 2025, 08:43:58 am
content: HiThere will be a DAC in the emulators. DACs add undesirable sinx/x roll off. The DAC output should have a dead flat noise spectrum, terminated with a roll-off that looks like a cliff.After creating the perfect white noise with an excellent implementation of a PRNG, you don't want mess up the noise spectrum with a DAC.Fixing this requires equalisation of the analogue signal, either in the analogue or digital domain. For this application, it will need to be in the digital domain because the frequency is not fixed.Analog Devices provides a really good explanation here:https://www.analog.com/en/resources/technical-articles/equalizing-techniques-flatten-dac-frequency-response.html

author: somejoe
author_rank: Contributor
timestamp: August 04, 2025, 01:18:46 pm
content: Quote from: dazz1 on August 04, 2025, 08:43:58 amAll good points. Starting to sound like there is going to be a "software simulator" needed as proof-of-concept (PoC) before the hardware design is flushed out.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 05, 2025, 01:55:33 am
content: Quote from: somejoe on August 04, 2025, 02:59:09 amAfter some more thought, choosing a DSP device with multiple cores should allow multiple emulations to run simultaneously and independently.One per core.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 05, 2025, 02:33:42 am
content: Quote from: somejoe on August 04, 2025, 01:18:46 pmIt's all a big math problem.This is the sort of problem that MatLab was created to solve, but I don't have a copy. I have created a spreadsheet to investigate the characteristics of the sinx/x filter applied to the PRNG shift register.The HP3722 implements a 32 bit (+/- 16bit) shift register but this full of compromises. If a modern dsp device can handle (say) a 256 bit shift register, why not use it? If the shift register is a circular buffer with just the pointers moving, the computational work load should be manageable.The PRNG, sinx/x filter and the DAC equalizer shift registers can be one single register.

author: somejoe
author_rank: Contributor
timestamp: August 05, 2025, 09:52:53 am
content: QuoteSee attached an HP note detailing how to extend the sequence length of the HP-3722A. In particular, see the section:"Specification 3722A-OPT.H03 is a standard -hp- Model 3722A Noise Generator which has ben modified to provide sequence lengths of n=9-20 and 24-28 inclusive....The Sequence length switch, S2, has been wired according to the diagram attached."Last four pages.

author: somejoe
author_rank: Contributor
timestamp: August 05, 2025, 08:43:15 pm
content: I had time to experiment around some of the ideas being discussed here. The data source from which the plots were created is a Raspberry Pi 4B via the I2S pins on the 40-pin connector. I'll repeat the runs later with a digital audio hat.All commands were issued in Linux using standard utils, as follows:somejoe@raspberrypi:~$ aplay -c 2 -f S16_LE -r 44100 /dev/urandomPlaying raw data '/dev/urandom' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereosomejoe@raspberrypi:~$ speaker-test -t pinkspeaker-test 1.2.8Playback device is defaultStream parameters are 48000Hz, S16_LE, 1 channelsUsing 16 octaves of pink noiseNote(s):- output using 40kHz clock. Left/right channel select waveform period and frequency look OK.- no filtering of any kind applied. Outputs taken directly from the expansion connector.- spectrum plot of random data stream derived from /dev/urandom (to simulate white noise) looks surprisingly flat.- significant overshoot of rising pulse edges on both data and clock lines.- pink noise spectrum clock shows the expected decay per octave, but with a 48kHz clock, there are two spikes at 8kHz and close to 20kHz. The extended spectrum plot shows a decaying harmonics and raised noise floor starting at 4khz. I suspect this is an artifact of the speaker-test "pink" filter.All-in-all pretty pleased with the results. Next step(s) is to implement a software LFSR using the HP polynomials to see whether or how it correlates to this set of measurements.And, needless to say, another run is warranted with an actual analog noise source.

author: somejoe
author_rank: Contributor
timestamp: August 06, 2025, 08:33:03 pm
content: The HP archive has been updated with the manual for the HP-1930A Pseudo Random Binary Sequence Generatorhttps://hparchive.com/Manuals/HP-1930A-PRBS-Generator.pdfThe last few pages have the full schematic which includes a discrete, IC-based, shift register.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 07, 2025, 09:11:30 am
content: I have figured out that in order to evaluate the HP 3722A PRNG, I need a spectrum analyzer, something like the HP 3720A I don't have.I looked at the specs for the 3720, and they are awful. Not a criticism of the engineers of the time. They could only do what they had available.The CRT is ultra delicate to the point I would be reluctant to buy a 3720 and ship it anywhere.The FFT refresh rate is about 0.8 secs per sweep.The data transfer rate from the 3721 to the 3720 is 10kHz @ 24 bits wide (about 250kbits/sec).Simulating a 3720 in a spreadsheet should be relatively not too hard. I don't want to use a commercial spec-analyzer app because the data from the 3721 is a bit stream, not a byte or word stream plus other technical reasons.So a DSP based 3722 emulator will require the following signal path.PRNGsinx/x filterDelay OptionEnergy averagingGaussian shaping or binary for digital/analog outputDAC inverse sin/x equalizer, for analog output.Where:PRNG is the noise generator shift register,Gaussian or Binary is the energy distributionDelay is the HOx delay optionEnergy averaging avoids a step output between the end of a sequence and the beginning. If listening, it avoids a click in the speaker as the sequence ends and starts again.An equalizer to compensate for the sinx/x curve in the DAC output.In addition there are line drivers, logic level shifters, and output amplifiers/buffers etc.So the next thing I am going to work on is a spreadsheet that can do FFT on a non-realtime bit stream. The aim is to get the math right. This will functionally emulate a 3720A Spectrum Display. The 3720A does not have an analog input, so a spreadsheet doesn't have to meet any speed requirements. It just has to do the calculations.

author: somejoe
author_rank: Contributor
timestamp: August 07, 2025, 12:55:26 pm
content: Quote from: dazz1 on August 07, 2025, 09:11:30 amThe plots I posted above were generated by a Digilent Analog Discovery capturing the digital output from a Raspberry Pi I2S interface (1-bit digital stream). Generating the bitstream this way has the advantage of being able to easily change the speed of both the generator (Rasp Pi) as well as the sampling rate of the capture device (Digilent scope).Because it is being transmitted over a physical 1-wire interface it's closer to simulating the final product.And, in addition to capturing a digital stream, it can capture an analog one as well - i.e. from a physical random noise generator.Quote from: dazz1 on August 07, 2025, 09:11:30 amThere is no need, unless you want to add this functionality, to perform energy averaging. At the speeds we're talking about you're likely not going to be listening to it, and, if you do, it'll likely be aliased by the reproduction chain.Also, what happens to the output of the 3722A when the sequence ends and re-starts? There is going to be a step change regardless.Quote from: dazz1 on August 07, 2025, 09:11:30 amBe careful of synchronization between the bit stream generation and it's subsequent processing - i.e. you want them to be separate processes, asynchronous, and driven by a different clock / timebase.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 08, 2025, 07:55:55 am
content: Quote from: somejoe on August 07, 2025, 12:55:26 pmThat's great. I appreciate your interest and efforts in this. I am aiming to get the maths right first. Without the constraints faced by the original HP designers, there are options and optimizations available. None of this stops a software selection of a mode that exactly emulates any version of the 3722.Quote from: dazz1 on August 07, 2025, 09:11:30 amQuote from: somejoeMy understanding of the HP documentation is this is already a feature of the HO1 version. I have read comments about a modern commercial audio PRNG that produces an audible thump when it reaches the end of a sequence.Quote from: dazz1 on August 07, 2025, 09:11:30 amQuote from: somejoeYes. I am using LibreOffice Calc which implements VBA or Python to avoid synchronization lock between the signal and the signal path.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 14, 2025, 11:59:30 pm
content: HiI'm playing around with the sinx/x filter. The sinx/x filter on the 3722A is 32 bits wide (+/- 16 bits). I am running simulations +/-512.The 3722A was severely limited by the tech of the time. The sinx/x filter is short by necessity. The angular difference between each bit is about 20 degrees, so quite coarse.With DSP there is no such limit. I have simulated 1024 bits with 2 degrees per bit and 20 degrees per bit.Attached is the plot of each. All this tells me is there is going to be an optimal setup of the sinx/x filter and it is probably not 20 degrees per bit over +/-16 bits.

author: dazz1
author_rank: Frequent Contributor
timestamp: August 15, 2025, 01:46:08 am
content: HiThe block diagram for the HP 3720A Spectrum Display is straight forward.The HP 3720A is synchronized to the HP 3721A correlator