Crosstalk/Ghosting/offset on ADC input - Page 1
Forum section: electronics / projects

author: zer0c00l
author_rank: Contributor
timestamp: June 01, 2020, 11:36:39 pm
content: I have an ADC circuit which uses all 8 channels of AD7689. The inputs of the ADC are driven by LT6010 opamp, and have a low pass filter. All 8 channels of the ADC (AD7689) have the same driving circuit. Every other input of the ADC always shows a 3.1mV signal whenever a full scale voltage is applied to the adjacent channel. For example when I apply 5v to channel 1 and short channel 2, channel 2 will read 3.1mV, and all other channels will show 0v. Similar thing happens with channel 3, and 4, and so forth. Now if I remove the capacitor (C152) which is part of the RC filter this problem goes away, and the adjacent ADC input fluctuates between 0.1mV to 0.5mV. An input on channel 1 only effects channel 2.Another thing I noticed was that if I read these channels with longer delay then I don't see this problem. Like If i wait 800 microseconds after reading channel 1, I won't see 3.1mV on channel 2. Is RC filter designed wrong

author: jbb
author_rank: Super Contributor
timestamp: June 02, 2020, 12:15:59 am
content: I haven't used that exact chip, but the AD7689 is a SAR type with an input multiplexer, i.e. one converter shared across several inputs.What I find suspicious is that the cross-talk happens in channel sequence.SAR ADCs have sample and hold capacitors, i.e. analog memory. If this capacitance isn't fully charged during the acquisition time, the sample caps will still 'remember' something from the previous channel. Suggest you read the "Analog Inputs" and "Configuration Register" sections of the data sheet and check things are OK. The acquisition time seems to be fixed at 1.8us minimum.

author: zer0c00l
author_rank: Contributor
timestamp: June 02, 2020, 01:34:58 am
content: Quote from: jbb on June 02, 2020, 12:15:59 amThanks for the response. The configuration register section doesn't really have anything useful for this situation. The only useful thing that I can find from the Analog Inputs section was the bit about settling timeWhat I understand from that is that the problem might be that the settling time for my RC circuit is higher than what is required from the ADC

author: MasterT
author_rank: Frequent Contributor
timestamp: June 02, 2020, 03:59:42 am
content: Probably, S/H capacitor of the ADC is transferring charge to 0.1 capacitor of the next channel as soon as switching to the next channel happens. Lowering RC time constant would resolve an issue, 2k R is too high value to drain excessive voltage spike in reasonable time frame - 100 nsec or less

author: zer0c00l
author_rank: Contributor
timestamp: June 02, 2020, 05:20:38 am
content: Quote from: MasterT on June 02, 2020, 03:59:42 amThe values for R and C were chosen to give a cutoff frequency of 795Hz, and filter high frequency noise. using a lower R does seem to resolve the problem, but it increases the cutoff frequency, and the adjacent channel seem to pickup fluctuations/noise

author: MasterT
author_rank: Frequent Contributor
timestamp: June 02, 2020, 12:47:13 pm
content: Data sheet page 23, Figure 28. Typical Application Diagram shows direct connection between adc inputs & buffer OPA. No RC filters. You could redesign front-end moving RC to OPA inputs, instead of post-filtering

author: ehughes
author_rank: Frequent Contributor
timestamp: June 02, 2020, 01:08:27 pm
content: QuoteYou need to drive input of a ADC MUX with a low impedance driver. Much lower than 2k. The behavior you are seeing is to be expected. Draw your circuit including the internal mux connections and it will become apparent. The switches in a mux a far from ideal and then is sample/hold circuit that expects zero(i.e. low) source impedance for accuracy.If you want some LPF, bake it into the op-amp or buffer the output of your RC.

author: zer0c00l
author_rank: Contributor
timestamp: June 04, 2020, 05:49:00 am
content: Quote from: ehughes on June 02, 2020, 01:08:27 pmThank you. Can you please provide some explanation as to why this behavior is expected if the impedance is high. I did some reading on SAR ADC after your reply and I cannot seem to figure out how/why the problem appears on the adjacent channel. The sampling capacitor for this ADC is 27pF, and the switch resistance is 2.2kohm. Shouldn't the problem only happen on the channel where the input is applied. How does this 2k resistor cause an offset on the adjacent channel, where there is no input even. I will really appreciate your response.

author: zer0c00l
author_rank: Contributor
timestamp: June 04, 2020, 10:47:43 pm
content: Quote from: MasterT on June 02, 2020, 12:47:13 pmQuote from: ehughes on June 02, 2020, 01:08:27 pmI found a schematic of an evaluation board from Analog Devices which uses an AD7689 ADC, withR = 22, andC = 2700pF. I modified my circuit to use same R as the evaluation board with C = 2200pF (didn't have 2700pF), and the problem is completely gone.Original circuitCircuit with low R and CEvaluation board schematichttps://www.analog.com/media/en/evaluation-boards-kits/evaluation-board/EVAL-AD76MUXEDZ.pdfCan anyone please shed some light on why this happens. I would love to learn more

author: Siwastaja
author_rank: Super Contributor
timestamp: June 05, 2020, 05:57:52 am
content: Every time ADC samples, it draws charge from your input capacitor. I think this is the basic thing you missed. The ADC draws a current from the input signal during sampling, and if the input cannot supply that current, the voltage sags and you get a wrong result. OTOH, if you have a ceramic capacitor here, it can easily supply the current required, but when the ADC discharges the capacitor, its voltage level changes.Sure, if the input capacitor is very large, say 10000x larger than the ADCs sampling capacitor, the change in your input capacitor voltage level is only ~0.01%.But, if you takemultiple samples, the input capacitor loses a tiny bit of chargeevery timethe ADC samples. So this capacitor needs to be topped off with the fresh input voltage. The 2.2kOhm resistor limits this current.It's likely that your 2.2kOhm was too much for the sampling rate you use. Using smaller resistor charges the input capacitor faster. Another option is to sample less frequently, so that the capacitor has time to replenish to the correct input value through that 2.2kOhm.Note there are two different time constraints here:Assuming Cin >> Csampl, the low-impedance requirement for the ADC is satisfied by the capacitor: the very shortsampling timebecomes irrelevant, the capacitor handles it. Then, the resistor must be sized so that theperiod between samples(1/samplerate) is catered by that resistor.If Cin >> Csampl isn't true - for example, no Cin at all, or Cin which is only some tens times of larger than Csampl - the input resistance must beeven smaller, because now it needs to be able to supply the charge ADC requires during thesampling time, which can be something like a microsecond.For example:If you sample every 1ms, and sampling takes 1us, and each sampling extracts 10pC of charge from the input signal:If you have no input capacitor (or small input capacitor), the input must be able to supply 10pC during 1us (during sampling)If you have a large input capacitor (say 100nF), it supplies 10pC to the ADC during that 1us. The input signal now needs to supply 10pC to that capacitor during 1ms.

author: ehughes
author_rank: Frequent Contributor
timestamp: June 05, 2020, 01:43:09 pm
content: Also, every time the mux switches changes, you have an additional dynamic load on your driving circuit. Those switches inside the ADC are not ideal and there is other "junk" in the front end. Having low impedance drive helps mitigate what Siwastaja is mentioning as you can better drive that node to the potential you eant *faster*You gave youself the clue when you said increasing the time between channel switches makes the problem better (as well a lowereing the series R) That just means there is more time for the node where the ADC is sampling to settle to the value you expect. The RC filter circuit is not decoupled from what is going on internal to the ADC / Mux) and real world effects are what you are observing.Like I said, draw a circuit including the mux/ switches and it will make better sense.*Always* drive ADC inputs with a low-z source. It even tells you in the datasheet (for other reasons but is still always good practive even with "DC" inputs).

author: Kleinstein
author_rank: Super Contributor
timestamp: June 05, 2020, 03:23:28 pm
content: With many SAR type ADCs the MUX and input sampling is done with the same FETs. So there usually is no extra charge pulse from changing the channel. It is mainly from changing the voltage. When the voltage changes there is some charge needed. If the capacitor is really large, like C_filter > 65000 * C_sample, the voltage drop is small and everything is OK. If the filter cap is smaller the drop would be noticeable. Here C_filter / C_sampe = 100 nF/25 pF is at around 4000 - so the change would be significant and the time to recharge the capacitor is quite long, way more than the sampling phase. So if a filter cap is used, make it really large (e.g. 2 µF), so the drop would be small, or don't use a filter directly at the ADC. A class 2 ceramic cap may not have full capacitance at 5 V, so one may need a relatively bulk film cap.