hybridfree/eevblog-posts huggingface dataset:
What to do with the PLL 'locked' output? - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: July 09, 2025, 05:00:34 am
content: This is for a straight forward design on a Gowin Tang Nano 20K board that uses a PLL to generate a fixed clock of 180Mhz.The PLL module has a 'locked' output. What am I supposed to do with it, should I use it to hold the design in reset state until the PLL stabilizes? Does the design even starts running before the PLL stabilizes?

author: BrianHG
author_rank: Super Contributor
timestamp: July 09, 2025, 05:13:28 am
content: You can use it as a flag to see if the CLK-INPUT is functionally there and within range.Yes, using it to keep your design in reset until your 180mhz is stable is a good idea.Remember, the PLL is an analog oscillator with a digital buffer to the core of the FPGA.It might oscillate madly before it successfully locks onto the source CLK-input reference.

author: zapta
author_rank: Super Contributor
timestamp: July 10, 2025, 01:54:01 pm
content: Quote from: BrianHG on July 09, 2025, 05:13:28 amThanks BrianHG. If I can't trust the clock when the execution starts, I guess I need to change my design from synchronous reset to asynchronous reset. I use synchronous reset everywhere.

author: asmi
author_rank: Super Contributor
timestamp: July 10, 2025, 03:48:13 pm
content: Xilinx allows specifying a bitstream parameter which would cause FPGA design to not start until all used PLLs are locked and stable. Check if your tools have similar option. This way you won't have to modify your design nor care about locked signal.

author: BrianHG
author_rank: Super Contributor
timestamp: July 10, 2025, 08:15:37 pm
content: Quote from: zapta on July 10, 2025, 01:54:01 pmThis makes no difference. So long as you hold your reset up to and including a valid clock cycle, it may still be a synchronous clock signal. (I typically have a 2-4 bit down counter tied to the clock signal with its preset on the PLL-LOCKED to create a new reset signal which has an extra few cycles after the PLL-LOCK becomes valid.)The only time you truly need an async clock is if you need to guarantee a reset condition while the clock is unstable, or if your reference clock-input unexpectedly dies.An example would be if you are using FPGA outputs to directly manually drive a mosfet driver in an H-Bridge output where you must prevent a DC or short output.The other example if if your FPGA is shading a data bus where in such an undetermined state, your data bus must be tri-stated.In these 2 cases, my choice would not be to make my design async reset, it would be just the output enable control logic for these pins requires the async reset support.
Xilinx ML506 Virtex-5 compact flash contents - Page 1
Forum section: electronics / general

author: vincei
author_rank: Contributor
timestamp: September 10, 2022, 06:55:57 pm
content: Does anyone know where to get or have the compact flash or zip files for this Xilinx board? I've tried the AMD website but all the Xilinx links are dead. Archive.org turns up a big http 503 error for all the links to xilinx resources no matter how many years I go back. The pages on the AMD website refer to all the dead Xilinx download links.https://docs.xilinx.com/v/u/en-US/ug347http://www.xilinx.com/products/boards/ml506/ml506_12.1/images.htm• ML505 -http://www.xilinx.com/ml505• ML506 -http://www.xilinx.com/ml506• ML507 -http://www.xilinx.com/ml507Thanks in advance-Vince

author: iMo
author_rank: Super Contributor
timestamp: October 26, 2022, 11:26:01 am
content: You have to register yourself at AMD/Xilinx site and you get the docs (at least I can see them there as of today)..

author: vincei
author_rank: Contributor
timestamp: November 13, 2022, 11:41:48 pm
content: Hi, it's not the documents I'm after. I have those. It's the supplemental material that is loaded into the compact flash that came with these boards that I'm after.Thanks.

author: RAQU_PL
author_rank: Contributor
timestamp: July 05, 2025, 05:40:59 pm
content: Sorry for resurrecting the topic, If anyone still needs it i do have content and mirror of CF card in Macrium of ML507 but it is to large to upload. Please PM me if You need it.Hope that helps.
Ultrazynq MIO pins  and JTAG EXTEST instruction - Page 1
Forum section: electronics / general

author: Murphy86
author_rank: Newbie
timestamp: December 05, 2024, 08:45:14 am
content: Have wierd issue where in some cases ultrazyng MIO pins are not acessible in EXTEST mode. (Not using vivado tools)Regular FPGA IO pins work well, but EXTEST write operation on MIO pins have no effect.Some boards work. When i compared jtag signal captured waveforms from working to not working, they are identical.Bootmode set to jtag has no effect.Has anyone seen this?If so what was the solution?

author: Murphy86
author_rank: Newbie
timestamp: July 04, 2025, 08:19:52 am
content: I wanna make it public knoladge incase anyone else run into same problem.in BSDL file safe_Val field is NOT only safe value you can load as placeholder. Many JTAG tools get that wrong.It is ofc safe value you can load, but in case of control bit in Boundary Scan Chain its a value you sould write to make pin input and inverted value to make pin output.As most devices 0(safe val=1) in control bit location set pin to output but in case of AMD ultrazynq MIO safeval is 0 meaning that writing 1 will make pin output. pins on FPGA fabric has safeval 1, ak output = value 0.
XC9572XL The code does not work properly. - Page 1
Forum section: electronics / general

author: YqHFXa01
author_rank: Newbie
timestamp: June 22, 2025, 05:12:14 am
content: I tried a lot and never got it working properly. The waveform after power is deformed, not square waves. The key fre cannot adjust the frequency and does not know where the problem is. How do I get through this quickly?
Altera Cyclone III Serial Flash Loader (SFL) - Page 1
Forum section: electronics / general

author: David
author_rank: Frequent Contributor
timestamp: May 31, 2010, 10:47:31 am
content: Hi all,I have quite a specific question here. I have a Cyclone III configured in JTAG mode only (MSEL pins connected to GND) and I want to use the SFL configuaration to program the EPCS4 config device through JTAG. I can succesfully program the SFL image but the programming of the config device always fails with the error message "Can't recognize silicon ID for device". After doing some quick googling it appears that the FPGA MSEL pins must be in AS mode for this part of the configuration? I am failing to see why this is the case as the whole purpose is to be able to program through the JTAG interface. Could anybody please shed some light on this?Dave

author: Maister
author_rank: Contributor
timestamp: June 14, 2025, 07:29:39 pm
content: Is this still relevant for you to solve?I have made a PCB recently with a Cyclone III, with EPCS device hooked to AS, MSEL configured in AS and I could try it out for you.Although MSEL are configured for AS, I can still use JTAG to send in the bitstream for the FPGA because JTAG has always priority. That is why the CLK pin of JTAG gets such a strong pull down (1k). You don't want the JTAG state machine to start accidentally.So, do I get it correctly: you want to flash the EPCS4 using the FPGA as a JTAG to Active Serial bridge? The SFL image is the one you need to be loaded in the FPGA for that, I assume.Where can I get hold of this image to try out?
Difference between XC9536 and XC9536B? - Page 1
Forum section: electronics / general

author: jmelson
author_rank: Super Contributor
timestamp: June 08, 2025, 02:53:49 pm
content: I have an old design from 2010 and still have a few unpopulated boards. It used an XC9536 to power-on reset some analog chips. I didn't have any 9536's so I got a couple on eBay. They were pre-programmed and the read protect and write protect fuses were programmed. So, I reset those, programmed the chips, but they seem to be dead in some way. The outputs ramp up during the power-on ramp, and then go to zero. Xilinx Impact verified the JTAG ID of the part and verified the program was loaded correctly. But, the new parts show a label of XC9536B, which I'd never heard of.I do have some old boards that I can steal some old XC9536's from, but before I attack the board with the hot air station, I'd like to see if anybody knows why these chips don't work. Yes, I am aware of counterfeits, but since Impact thought the chip programmed correctly, I kind of doubt it.Thanks,Jon
Tang 138K Console - Page 1
Forum section: electronics / general

author: Amish_Fighter_Pilot
author_rank: Regular Contributor
timestamp: July 04, 2025, 02:23:58 pm
content: There is a new FPGA hitting the market right now that CLAIMS true USB 3.0 support built right in as well as 138,000 LUTs. The BL616 MCU seems to be a bit mysterious, but they claim it supports up to 5gb/s data speeds. Is this thing for real? Why focus such a big FPGA on just retro gaming? Do other applications not need so many LUTs?I can't seem to find a lot of information about how much power and heat this thing uses and makes, but it seems like it can run off one 18650 cell potentially(no idea how long though). The FPGA and the interface seem really fascinating though. Is this thing as cool as it appears to be?
AGM's latest platform.io SDK - Page 1
Forum section: electronics / general

author: gerbay
author_rank: Regular Contributor
timestamp: April 01, 2025, 05:25:59 pm
content: March 2025 PIO SDK- some examples updated- added some new examples- added some modelsim testbenchAgRV_pio-1.7.1-win64-release.exe download link is below

author: godor2008
author_rank: Contributor
timestamp: April 02, 2025, 03:07:33 am
content: Hi there! Any chance you will be able to upload new Supra here ?I saw it Supra-2025.01.b0-90a02370-win64-all.zip on their pan.baidu but can not download it without china phone number

author: gerbay
author_rank: Regular Contributor
timestamp: April 02, 2025, 05:58:10 am
content: AgRV_pio-1.7.1-win64-release.exe include supra 2025.3logic package which is include supra is here (excluded yosys);https://drive.google.com/file/d/1HC_wAqiBla8nlYPaNGWD5HmWOam1Szpd/view?usp=drive_link

author: godor2008
author_rank: Contributor
timestamp: April 02, 2025, 04:15:33 pm
content: Thanks! It was not obvious for me that Supra is bundled inside AgRV_pio. I installed it and found in isntallation directory at: C:\Users\<your name>\AgRV_pio\packages\tool-agrv_logic\bin

author: bingo600
author_rank: Super Contributor
timestamp: April 25, 2025, 06:53:27 am
content: Would it be possible to get a link to the linux version too ??/Bingo

author: gerbay
author_rank: Regular Contributor
timestamp: April 25, 2025, 05:22:24 pm
content: April 2025 PIO SDKAgRV_pio-1.7.3 - 2025.04.b0 versionAgRV_pio-1.7.3-linux-release.tar.gzAgRV_pio-1.7.3-win64-release.exeSupra-2025.04.b0 includedDownloader-2025.04.b0 includeddownload links attached below;

author: bingo600
author_rank: Super Contributor
timestamp: April 26, 2025, 01:15:57 pm
content: Quote from: gerbay on April 25, 2025, 05:22:24 pmThank you so muchFrom all of us that can't download from Baidu

author: gerbay
author_rank: Regular Contributor
timestamp: April 26, 2025, 03:20:50 pm
content: Quote from: bingo600 on April 26, 2025, 01:15:57 pmYou're welcome..I can't download from baidu either.

author: godor2008
author_rank: Contributor
timestamp: April 28, 2025, 01:35:31 am
content: I was also suffering to download from baidu, but found that there is group in Telegram messenger where all these AGM Supra software is uploaded. And you can freely download from it!Here is the linkhttps://t.me/agmfpgadoc

author: sigint
author_rank: Contributor
timestamp: April 30, 2025, 08:12:09 pm
content: It seems that yosys is finally working. The DAC output does work now.

author: gerbay
author_rank: Regular Contributor
timestamp: June 07, 2025, 09:46:17 pm
content: May 2025 PIO SDKAgRV_pio-1.7.6 - 2025.05.b0 versionAgRV_pio-1.7.6-linux-release.tar.gzAgRV_pio-1.7.6-win64-release.exeSupra-2025.05.b0 includedDownloader-2025.05.b0 includedQuotedownload links attached below;
Can’t debug Nios II - flaky JTAG connection - Page 1
Forum section: electronics / general

author: jbb
author_rank: Super Contributor
timestamp: June 07, 2025, 04:09:29 am
content: Hi allI’m using an Altera FPGA for a work project and want to include a Nios II core (we’re using an older version of Quartus, 22.1)I can get it to boot and run a simple program, but I can’t get it into debug mode. I’m running from on-chip RAM and have included a System ID block in the Qsys / System Designer.In Eclipse, under Debug Configurations I can sometimes connect to the device and read the System ID & timestamp, and sometimes it just comes back Not Found. It’s flaky and inconsistent. Other JTAG cores like Signal Tap seem to work fine on the same FPGA.Does anyone have experience / advice on this?

author: Gleeson
author_rank: Contributor
timestamp: June 07, 2025, 06:47:06 pm
content: My experience with the Nios tools is that they are flaky and inconsistent.

author: jbb
author_rank: Super Contributor
timestamp: June 09, 2025, 07:48:02 am
content: Well, I have made some progress. I started up a new project and put in a Nios II which runs at half the clock speed and boots from pre-initialised block RAM (previously I was copying from flash to RAM in pre-boot). And it worked.But there is a minor sin in there: I changed 3 things at the same time. So now I have to determine what the critical change was.(And yes, the previous design did meet timing constraints…)

author: jbb
author_rank: Super Contributor
timestamp: June 10, 2025, 05:08:53 am
content: Returning the core clock speed to the original value has resulted in aslightlyflaky system. I sometimes need to unplug and replug it :-(Returning the code to flash storage (copied to block RAM during boot) doesn’t seem to make a big difference to the flakiness, but it does mean I can’t simply click ‘debug’ and upload a fresh ELF file.
matching rfsoc 4x2 LED/switch table to physical location on board - Page 1
Forum section: electronics / general

author: john23
author_rank: Frequent Contributor
timestamp: June 02, 2025, 11:31:39 am
content: Hello , In the table bellow each switch and LED das a name for example AR11.Given the physical photo shown in the link how can I know where is AR11?Thanks.https://technionmail-my.sharepoint.com/:i:/g/personal/yefimv_technion_ac_il/EUXqllQ04XlPn0avmoZxd8sBZj33DoGW3Pz52mIMQBGcyQ?e=aLKeD8https://www.realdigital.org/downloads/15456c97a4fe5a1ee66208c5aa3894bb.pdf
Pinout of Brooklyn 3? - Page 1
Forum section: electronics / general

author: Maister
author_rank: Contributor
timestamp: June 04, 2025, 06:13:25 pm
content: Hey folks,I scored two daughter boards equipped with a Xilinx Zynq from a dumpster.They also feature a kind of mini PCI edge connector for mounting on the eval motherboard.I would love to find out the pinout of this edge connector to use it for my own projects but I wasn't successful on the internet.Maybe someone knows that board and has a Schematic / pinout?Or has an idea how to obtain it?Board is called Brooklyn 3 from Audinate.Thanks for any advise.Patrick
Questa for Lattice - Can't make it run. - Page 1
Forum section: electronics / general

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: June 01, 2025, 09:36:28 am
content: Hi All,I'm using Lattice Diamond to develop a MachXO3 project - I've used Diamond and the MachXO3 before but never needed to simulate a design, and now that I do I'm stuck.If anyone has even a little knowledge and can help kickstart me I would be grateful.Here is what I'm doing.I've created a test-bench seems fine.Then I run the Verilog Simulation File process under Map Design.Then I run the Simulation Wizard where the only option I have is QuestaSimI've tried both RTL and Post-MapWhen Questa loads I change to Simulation Layout, andright click in the project and select Compile ALL.. and that works fine.Then under the menu Simulate | Start Simulation- In Design units I put work.testbench- In Libraries I've tried all sorts of things MachXO, MachXO3, Mach...And that's where my issues start (if they had not already), getting things like.Module 'SPR16X4C' is not definedCould not find library MachHow do I know what libraries to add? or a better question is why does the Wizard not just set everything up for me? do I need to add all the libraries to my Diamond project?Any ideas?ThanksDavid

author: David Chamberlain
author_rank: Frequent Contributor
timestamp: June 02, 2025, 07:37:59 am
content: If only I started with the first error message first.It was not able to load files because I had a space in one of my folder names. Once I fixed that it was able to locate all the libraries and runs fine now.
documentation and examples for rfsoc4x2 GPIO interrupt - Page 1
Forum section: electronics / general

author: john23
author_rank: Frequent Contributor
timestamp: May 28, 2025, 10:25:54 am
content: There is a RFsock4x2 board I need to use shown below,I need to run 4 signals from DAC depending on the gpio interrupt being raised.I am new to vivado and vitis , I am asking general strategy on how to accomplish this .We have two peripheris DAC and GPIO.1.In MCU for each periphery we have API and registers with exact manual \regarding their functionality ,where can I find them?2. How do you recommend me to implement this structure , general strategy?3. any examples will be great.Thanks.https://www.realdigital.org/hardware/rfsoc-4x2
Lattice FPGA LCMXO640C - JTAG Pins - Page 1
Forum section: electronics / general

author: 2X
author_rank: Frequent Contributor
timestamp: May 06, 2025, 08:44:32 pm
content: Hi,I want to program the Lattice FPGA “LCMXO640C-3TN144" with the below programmer (HW-USBN-2A).On the "MachXO JTAG Programming and Configuration User Guide" (page 6) I read "VCC for the internal JTAG logic is supplied by the associated bank’s VCCIO". So, for the programming the only pins where I have to connect on 3.3V are the 117(VCCIO0) & 135(VCCIO0)?The supply on VCC pins must be external or the programmer supplies these pins?The Vcc pin which powers the core of the FPGA or the VCCAUX don't required for the programming?Also, for the programming I will need and the below pins:TMS pin: 39TCK pin: 42TDO pin: 47TDI pin: 51LCMXO640C-3TN144 pinout: page 60 "MachXO Family Data Sheet"HW-USBN-2A Lattice is Download Cable USB Jtag ISP FPGA CPLD Programmer for Diamond is Lever Win7 WIN8 WIN8.1https://vi.aliexpress.com/item/4000337860205.html?spm=a2g0o.order_list.order_list_main.42.276e1802cKZKro&gatewayAdapt=glo2vnm

author: glenenglish
author_rank: Frequent Contributor
timestamp: May 10, 2025, 10:45:43 am
content: all power is required for programming and you must follow the sequence rules.Surely you are programming them on board ?

author: 2X
author_rank: Frequent Contributor
timestamp: May 11, 2025, 12:55:28 pm
content: Thanks for your reply.I will connect to +3.3V all the VCCIO (all banks power supply pins) pins, but I have also to connect and all the VCC and VCCAUX pins at the below picture (Pinout) or the VCC & VCCAUX are not necessary for the JTAG programming?On the "MachXO JTAG Programming and Configuration User Guide" (page 6 - "VCC for the internal JTAG logic is supplied by the associated bank’s VCCIO") don't refer the pins VCC & VCCAUX for the JTAG.

author: fchk
author_rank: Frequent Contributor
timestamp: May 13, 2025, 02:12:00 pm
content: Quote from: 2X on May 11, 2025, 12:55:28 pmYes, VCC and VCCAUX are always required for any operation.

author: 2X
author_rank: Frequent Contributor
timestamp: May 17, 2025, 02:38:41 pm
content: I made a schematic with jumpers in case if I want to connect a different supply on VCC/VCCAUX & VCCIO pins.I hope it is OK... if no please tell me.Programmer where I am going to use:HW-USBN-2A Lattice is Download Cable USB Jtag ISP FPGA CPLD Programmer for Diamond is Lever Win7 WIN8 WIN8.1https://vi.aliexpress.com/item/4000337860205.html?spm=a2g0o.order_list.order_list_main.42.276e1802cKZKro&gatewayAdapt=glo2vnm
Intermediate Level FPGA Books - Page 1
Forum section: electronics / general

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: April 28, 2025, 02:03:27 am
content: I have a dozen books on FPGAs, and every single one of them starts simple, like blinking an LED, and progresses through more complex projects, like driving a VGA monitor, interfacing with PS/2 keyboards, and interfacing to external memory. None of them cover topics like pipelining, crossing clock domains, or timing closure.Anyone know of any intermediate-level FPGA books that cover these subjects?

author: w42i
author_rank: Contributor
timestamp: April 29, 2025, 05:43:15 pm
content: Advanced FPGA Design: Architecture, Implementation, and Optimization by Steve Kilts does cover such topics (read it lately).But I'm interested in hearing about more advanced FPGA literature, too.

author: egonotto
author_rank: Super Contributor
timestamp: May 15, 2025, 07:53:50 pm
content: Hello,you may be interested in the following book:John Francis Wakerly, Digital Design: Principles and Practices.Best regardsegonotto

author: dferyance
author_rank: Regular Contributor
timestamp: May 16, 2025, 11:24:39 pm
content: I have two books by Jien-Chung Lo that were helpful to me.Modern Digital Designs with EDA, VHDL and FPGA which you can buy from Terasicand Rhody Computer System: an educational platform on FPGA which used to be on Amazon kindle, but I don't see it for sale anymore.They have some similarities but the Rhody book was designed for university classes and Modern Digital Designs is more generally applicable. What is nice is that they walk through specific design applications. Covering IO systems like PS2 input and video output.Edit.. after re-reading your initial posts, I think this would still be too basic for your intermediate definition.
Comments on this schematic to program an ICE40 - Page 1
Forum section: electronics / general

author: PartialDischarge
author_rank: Super Contributor
timestamp: May 14, 2025, 07:25:14 am
content: It's going to be my first time using a Lattice Ice40 so I may need some help.Want to order a small board to program the NVM of the FGPA, I have the Lattice Diamond, Icecube2 and the HW-USBN_2B programmer.My doubt is with VCC_SPI which I'm making equal to VCCIO and feeding it to the programmer, I believe this is the correct way. Also are all the signals needed for programming are at J1?
converting xilinx sdk 2017 "hello world example" into 2021 xilinx Vitis HLS tool - Page 1
Forum section: electronics / general

author: john23
author_rank: Frequent Contributor
timestamp: June 01, 2025, 03:23:19 pm
content: Hello, There is a manual which makes the rfsoc send "hello world" threw UART.They used Xilinx SDK to make this board send this massage.In my PC I have Vivado and Vitis HLS ,2021.1.I tried to create the project in Vitis as shown below ,but he sais that there is a problem because there is no test bench file.What could be done to overcome this issue?What do I need to write in the test bench file so it will work?Thanks.
CPLD Protection Diodes on JTAG Header - "R1" SMD MARKING - Page 1
Forum section: electronics / general

author: 2X
author_rank: Frequent Contributor
timestamp: January 22, 2025, 10:37:38 pm
content: Hello,I have a CPLD where on the JTAG connector is connected an SMD chip with “R1” marking. Do you know what chip is this? I couldn’t find something with “R1” marking. Do you know what kind of chip can be this… it something standard that is connected on JTAG connector? I saw in the internet a design that have protection zener diodes at pins (TDI, TDO, TCK, TMS).https://electronics.stackexchange.com/questions/546001/zener-diodes-for-jtag-interface

author: langwadt
author_rank: Super Contributor
timestamp: January 22, 2025, 11:07:45 pm
content: probably something like this:https://www.st.com/en/protections-and-emi-filters/esda5v3sc5.html

author: 2X
author_rank: Frequent Contributor
timestamp: January 22, 2025, 11:14:44 pm
content: Thanks for your reply.I can't find an SMD like this "ESDA5V3SC5" nowhere. If anyone have seen this marking "R1" and knows the part number... please tell me.

author: ataradov
author_rank: Super Contributor
timestamp: January 23, 2025, 12:42:26 am
content: What do you mean you can't find it? DigiKey alone has 128,206 of them.Why do you need that exact part? It is not really necessary in first place, but if you want it, just place any TVS you can find in a compatible package.Also, measuring TVS diodes with a multimeter is useless. They are used in reverse breakdown direction and multimeter usually don't provide enough voltage in diode mode. What you are observing is the forward voltage, which is fine. Your TVS is likely fine and does not need replacement.

author: 2X
author_rank: Frequent Contributor
timestamp: January 23, 2025, 07:38:05 am
content: I don't want the exact same component and the component isn't faulty. Just from curiosity I would like to see what are the exactly specs of these TVS diodes because with multimeter I can't check the clamping voltage of the diodes. I use the multimeter just only to confirm that all the pins have the same value in order to have clue about what this component is. Thanks for your suggestions.

author: 2X
author_rank: Frequent Contributor
timestamp: April 02, 2025, 09:33:43 pm
content: Finally I found it.Part Number: BZA868AVL,115
Is a DIY CPLD programmer possible? How would I do it? - Page 1
Forum section: electronics / general

author: MarkS
author_rank: Unknown
timestamp: March 28, 2025, 03:37:09 pm
content: Stupid question, I know, but the programmers I'm finding are around $300 USD and that's outside my budget. I know that most programmable chips are typically programmed at 12+ volts, but with proper level translation, could this be done with an Arduino Mega? How would I do this? Google isn't very helpful.

author: darkspr1te
author_rank: Frequent Contributor
timestamp: March 28, 2025, 03:44:51 pm
content: It would help if you are more specific e.g CPLD brand/type ,I dont personally know of CPLD's at 12v, PIC micro's yes but i dont get to play with all the toys.As far as a cpld programmer goes for ALL my devices i uses a busblaster jtag programmer , around $20 in all the usual places.

author: MarkS
author_rank: Unknown
timestamp: March 28, 2025, 03:52:04 pm
content: The one I'm planning on using, and the one that I've written the CUPL file for, is the Atmel ATF750LVC. I have the compiled JEDEC file for it. Atmel's datasheet is abismal! Any more sparse and it would just contain the cover sheet.

author: MarkS
author_rank: Unknown
timestamp: March 28, 2025, 07:26:12 pm
content: Nevermind. I'm making this far more difficult than I need to. I don't need the 750 chip. The 22V10 chip will work just fine and I can get a T48 programmer for $80 off of Amazon and even cheaper from AliExpress.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 29, 2025, 03:48:47 am
content: The T56 claims to support ATF750 and ATF2500 so you could consider that ? ( & likely the T76)Their PLD vector testing is still a ‘work in progress’ when I least checked.

author: MarkS
author_rank: Unknown
timestamp: March 29, 2025, 12:05:16 pm
content: Quote from: PCB.Wiz on March 29, 2025, 03:48:47 amThose are the programmers I was referring to that start at $300. Truly, there is no good reason for me to go to the 750 over a 16vxx or 22v10. The logic that I need is for a simple VGA circuit. All it will do is take the outputs from the row counters and output H_BLANK, H_SYNC and a couple of other signals. The compiled code takes up a tiny fraction of the 22V10. I wanted to use the 750 because it's newer, but that is just silly, especially when I can buy a over a hundred thousand 22v10's right now on Digikey.Anyway, I have already ordered the T48 off of AliExpress.
Problem with init Zynq Ultrascale - Page 1
Forum section: electronics / general

author: Devscale
author_rank: Newbie
timestamp: April 15, 2025, 10:46:14 am
content: Hello everybody,I have a custom board using Zynq Ultrascale+ and I encountered with a problem while booting from a QSPI flash. In the process of starting the FPGA there is a signal on the PS_ERROR_OUT pin. At the same time the FPGA is running and there is a PS_DONE signal. I have an assumption that this is due to the fact that the processor in the firmware is not connected, but unfortunately I could not find anything about this in the documentation. I would be grateful if you could tell me what could be the matter and I would be doubly grateful if you could point me to the document where it is written about it. Thanks.

author: glenenglish
author_rank: Frequent Contributor
timestamp: April 17, 2025, 07:46:44 am
content: there's only a small number of reasons the PS-ERROR will go active.There is also the PS_ERROR_STATUS signal. (Table6-16 in the PMU chapter) , what does that pin do ? Read Chapter 6.Connect a TTY to the UART port . the boot rom may tell you what is going on if theFSBL actually starts.Read the Technical reference manual Boot and Config section... then , next day, read it again....You will learn a great deal about the device solving this problem. It's the way of big chips...
Question about Zynq 7000 banks - Page 1
Forum section: electronics / general

author: HasanSyr
author_rank: Contributor
timestamp: March 22, 2025, 03:25:03 pm
content: Are banks 0-500 and 1-501 different? In the MIO Table they are the same and each pin is referenced to as "MIOx" but in the package file the pins are listed as "Bank 0" and "Bank 500" separately. In my dev board MIO[10:13] are used for 2 things if I select them in Vivado it gives me an error?In the dev board documentation, they tell me to select SDIO1 in the MIO config but they left JTAG unchecked, however in the schematic and in the documentation they show that JTAG is connected to the pins I showed in the images. If I select both SDIO1 and JTAG Vivado gives me an error!

author: RoadRunner
author_rank: Frequent Contributor
timestamp: March 22, 2025, 04:21:15 pm
content: Yes both of the banks are different banks. They are both MIO. They can be separately powered.

author: glenenglish
author_rank: Frequent Contributor
timestamp: March 24, 2025, 12:47:03 am
content: That's the PSJTAG- you want the normal chip jtag for most things. SO you wont have that conflict for JTAG.Take a look at the configuration chapter int he TRM.any reason you selecting EMIO, not MIO pins for the SD boot ??

author: asmi
author_rank: Super Contributor
timestamp: March 24, 2025, 07:08:50 pm
content: Quote from: glenenglish on March 24, 2025, 12:47:03 amThis will only work if SD card is setup as a secondary boot device, and primary will be QSPI flash. Otherwise Zynq expects SD interface to be connected to specific pins (see TPM for specifics).
CPLD - Read Bitfile With Xilinx ISE 14.7 - Page 1
Forum section: electronics / general

author: 2X
author_rank: Frequent Contributor
timestamp: March 27, 2025, 08:22:49 pm
content: Hello,I want to read a bitfile (if it is not protected) with the Xilinx ISE 14.7 from the CPLD (XC2C64A-7VQG100C) and I made a trial in a blank new CPLD (XC2C64A-7VQG100C) to read it and I get a message "Succeeded".Because I have use the Xilinx only fro programming and this before many years... please could you check the below images and tell me if I made something wrong or if I have to do something better/safer?My programmer is the DLC10:https://vi.aliexpress.com/item/32810890902.html?spm=a2g0o.productlist.main.1.534a6644xaCDQ8&algo_pvid=b59c758b-fca6-4cd0-a9fc-479d16372ecf&algo_exp_id=b59c758b-fca6-4cd0-a9fc-479d16372ecf-0&pdp_npi=4%40dis%21EUR%2143.80%2130.22%21%21%2144.07%2130.41%21%402103835e17366497292721664e5253%2164548542145%21sea%21GR%21138459962%21X&curPageLogUid=hnSK0AUntQoT&utparam-url=scene%3Asearch%7Cquery_from%3A

author: 2X
author_rank: Frequent Contributor
timestamp: March 27, 2025, 08:25:06 pm
content: the last screenshots

author: davep238
author_rank: Contributor
timestamp: March 29, 2025, 02:10:13 pm
content: It looks like you did everything correctly.
Anyone designed with Agilex5 yet, and from Xilinx world ? - Page 1
Forum section: electronics / general

author: glenenglish
author_rank: Frequent Contributor
timestamp: March 20, 2025, 07:21:02 am
content: Anyone done a design with AGilex 5 yet?I''ve been seriously evaluating a move to Altera....It's a sensational family, on paper. usual Altera problem with finding data and information. Have not looked at ALtera tools in 15 years.....Agilex 5 has almost everything you want in sillicon, although it does NOT have run time variable IODELAY capability. I think that's in Agilex 7.Price is unbeleivable , even compared to my Xilinx prices, which are OK for my volumes....Versal is a bit short on IOs if that's what you want, at least in the small gate count devices.-glen

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: March 20, 2025, 02:56:37 pm
content: Which ones catches you eyes? what about amiability and price in China?
Resources for code generation for signal processing components - Page 1
Forum section: electronics / general

author: AussieBruce
author_rank: Regular Contributor
timestamp: March 20, 2025, 10:57:37 am
content: I have a (big) stretch goal of implementing digital SSB on an FPGA, I’ve done quite a bit of Verilog, and have an extensive background in analog electronics including signal processing and RF, but this is something else. For a while I was linked in with an Italian website/project doing that very thing, but it has wound up and I have no contacts with the remnants. Some of the members were practising communication engineers, and had access to high powered and very expensive software for HDL code autogeneration, such as the Matlab toolboxes. These can cut the development time for function blocks like FIR filters from months to hours, I doubt that my planned project would be viable without them. Is anyone aware of resources on the web or elsewhere for this level of design?

author: laugensalm
author_rank: Regular Contributor
timestamp: March 20, 2025, 02:32:08 pm
content: I've done a fair bit of DSP pipeline generation using Python HDL, where things basically boil down to converting a software routine with specific data types into a pipelined block, either automatically or by using a particular pipeline notation. Then it's elaborated to plain Verilog or VHDL.Since I am not familiar with SSB, I am not sure what could help you, but you might have come across these tools already:- pyfda for graphical evaluation and design of filters- octave for more fine grained processing- numpy for detailed algorithm prototyping- MyHDL for 'translation' into proper bit-exact arithmetics for Verilog and VHDL (with bugs) targets- nmigen-style generator approachesI don't want to advertise my own HLS approach yet, but if you are looking for an efficient way to create and verify pipelined signal processing hardware against working software algorithms, there's something like this (JPEG hardware encoder co-simulation):https://gist.github.com/hackfin/0b124e280c42f5099aa7d6464cf19ee9There's a bit of documentation on the underlying kernel and HDL ecosystem, not so much on the HLS side, though.
Looking for the version 4.0 of the Atmel Prochip Designer - Page 1
Forum section: electronics / general

author: Gyorgy Albert
author_rank: Contributor
timestamp: November 22, 2024, 01:41:29 pm
content: Hi All,I am wondering if there is someone who has the version 4.0 of the Atmel Prochip Designer (which was based on the PeakFPGA/PeakVHDL) somewhere in his archives. I found a trial version of Prochip Designer 3.0 (in my CD archives), and I would like to test the 4.0 too. I know, the current 5.0.1 is available for download at Microchip, but even if you receive from them a trial license, a license for Modelsim is still needed.I really appreciate if someone can share with me the 4.0 install kit (or trial). I have not found it in all known places (including the archive.org)Thanks,Gyorgy/George

author: Gyorgy Albert
author_rank: Contributor
timestamp: March 17, 2025, 04:34:16 pm
content: Hello All,I am still looking for the Prochip Designer version 4. I found that it is included in the accompanying CD of the ATF15XX-DK3 CPLD DEVELOPMENT KIT (the old one, with the parallel port dongle, not the new USB version). See the attached picture of the kit.Maybe I am lucky this time, and some of you will recognize the image, and still have it in his archive. Particularly, I am interested in the Accolade PeakFPGA/PeakVHD which is included with the other tool chains. It should be newer than version 5.30.Thanks,George/Gyorgy
VHDL Made Easy (David Pellerin, Douglas Taylor) CD content - Page 1
Forum section: electronics / general

author: Gyorgy Albert
author_rank: Contributor
timestamp: January 07, 2025, 02:40:40 pm
content: Hello everyone and Happy New Year,I am looking for the CD content of the book VHDL Made Easy by David Pellerin and Douglas Taylor. I wasn’t lucky, since I purchased the book (two times), and received it without the CD.Is there someone who has it, and can share with me the CD content? Thanks in advance,Gyorgy

author: abeyer
author_rank: Frequent Contributor
timestamp: January 07, 2025, 10:02:35 pm
content: Ok, I'm morbidly curious what use case you have for demo versions of win95-era vhdl synthesis software that you'd buy a book twice trying to get them.There's a US amazon seller with a new copy of the book & cd listed for $50 USD.

author: Gyorgy Albert
author_rank: Contributor
timestamp: January 08, 2025, 02:38:23 pm
content: It is just another rabbit hole (or obsession of mine). I like to have the books of my personal technical library complete. That's all. Unfortunately that Amazon seller is not available for my (probably because of my location). Thanks anyway,Gyorgy

author: Gyorgy Albert
author_rank: Contributor
timestamp: March 17, 2025, 04:25:59 pm
content: Finally, I have the book with the CD. The Accolade PeakFPGA and PeakVHDL included has version 4.13. If there is anyone interested in a copy of the CD, just let me know. I will find a way to share it. I am still looking for the PeakFPGA/PeakVHDL included in the Atmel Prochip 4 (as I wrote in another post, which should be version 5.30 or above).BR,George/Gyorgy
Someone has the file modelsim-win32-6.6c-se.exe or modelsim-win32-6.6d-se.exe? - Page 1
Forum section: electronics / general

author: gfernval
author_rank: Contributor
timestamp: March 13, 2025, 01:12:58 am
content: Hello:Need ModelSim 6.6c SE edition or ModelSim 6.6d SE edition, files modelsim-win32-6.6c-se.exe or modelsim-win32-6.6d-se.exe, someone has it?

author: gfernval
author_rank: Contributor
timestamp: March 13, 2025, 02:01:25 am
content: Versions 6.6e and 6.6f are fine to me (files modelsim-win32-6.6e-se.exe and modelsim-win32-6.6f-se.exe)

author: BrianHG
author_rank: Super Contributor
timestamp: March 13, 2025, 02:16:03 am
content: Older versions of Intel/Altera Quartus' downloads on their Quartus Prime download page may have newer versions of it. Like 9.x for old Quartus 9.0 / 13.0 through 20.x for Quartus prime 20.x. I do not know about 6.x.
Programming Zynq 7000 board via FT232 breakout board - Page 1
Forum section: electronics / general

author: HasanSyr
author_rank: Contributor
timestamp: March 07, 2025, 05:50:19 pm
content: Im trying to program my board via the FT232 because I'll be using that chip in my own development board around the same SOM my dev board uses (MYD-C7Z020 V2). My board doesn't show up in HW manager. The programmer shows up but the board as a device doesn't. Im also confused with the selection, on the silkscreen it says JP3 Sel. Indep. JTAG but BOOT_MODE pins boot from JTAG when both bits are 0.The pinout on the schematic is also confusing, why is there a label called CON_JTAG_TDI while on the symbol pin it says TDO and another pin on the symbol says TDI? It has something to do with FMC I guess but I don't get it.I have programmed the FT232 chip using Xilinx's `program_ftdi` utility.
Different behaviors in clock drivers in beginner VHDL testbench - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: March 03, 2025, 08:39:40 pm
content: I am doing this tutorialhttps://vhdlwhiz.com/clocked-process/on VHDLwhiz.com to learn some beginner VHDL.I am in a VHDL class in college right now, and the professor says to drive our clocks in the testbench like this:Code:CLK_PROC : process isbeginwait for 5 ns;clk <= not clk;end process CLK_PROC;in the VHDLwhiz code, he does this:Code:clk <= not clk after clk_period / 2;with constants defined asCode:constant clk_frequency : integer := 100e6;constant clk_period : time := 1000 ms / clk_frequency;Here is my entire testbenchCode:library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity T17_flip_flop_tb isend entity;architecture sim of T17_flip_flop_tb isconstant clk_frequency : integer := 100e6;constant clk_period : time := 1000 ms / clk_frequency;signal clk : std_logic := '1';signal rst_n : std_logic := '0';signal din : std_logic := '0';signal dout : std_logic;beginuut : entity work.T17_flip_flop(rtl)port map(clk => clk,rst_n => rst_n,din => din,dout => dout);clk <= not clk after clk_period / 2;-- CLK_PROC : process is-- begin-- wait for 5 ns;-- clk <= not clk;-- end process CLK_PROC;STIM_PROC : process isbeginrst_n <= '1';wait for 20 ns;din <= '1';wait for 22 ns;din <= '0';wait for 6 ns;din <= '1';wait for 20 ns;rst_n <= '0';wait;end process STIM_PROC;end architecture;The first part of the simulation changes the input on the positive clock edge.I am using Modelsim to simulate, and when I use the first option to drive the clock (the one my professor taught us), I get the output of the flip flop to change at the same time as the input (first input changes on the clock edge).When I use the method from VHDLwhiz, I get what I think is the correct waveform, and the input changing on the clock edge doesnt change the output until the next rising edge.Please see the pictures attached.Why am I getting two different behaviors?

author: Someone
author_rank: Super Contributor
timestamp: March 03, 2025, 09:46:55 pm
content: Likely exposing the underlying sequencing of simulation:https://vhdlwhiz.com/delta-cycles-explained/

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 04, 2025, 10:03:20 am
content: Quote from: Someone on March 03, 2025, 09:46:55 pmThis.For generating clocks in testbenches, both approaches work, although I prefer the process one.Now, while the behavior of the simulation is different in your case, this mainly comes from the fact that the way you generate the 'din' signal is not synchronous to 'clk'. Just because you think they should happen at the exact same time doesn't mean that they are synchronous. That's something you really need to grasp when dealing with HDLs.So the discrepancy in simulation here is actually a good warning sign of that.For generating 'din', rather use a process with 'clk' in its sensitivity list and change 'din' in it on the rising (or falling, as you wish) edge of the clock. After that change, both ways of generating 'clk' should yield the same simulation result.
What can be applied? - Page 1
Forum section: electronics / general

author: Luosi
author_rank: Newbie
timestamp: March 03, 2025, 01:31:03 am
content: What advanced thermal management strategies can be applied when using the EPM7512AEQI208-10N in high-density PCB designs?Details of EPM7512AEQI208-10N:https://www.emsfpga.com/productdetail/epm7512aeqi208-10n
Lattice JEDEC Files Valid? - Page 1
Forum section: electronics / general

author: chick0n
author_rank: Regular Contributor
timestamp: February 27, 2025, 11:21:08 pm
content: Hi,I tried to read out some 1016E and 1032E Lattice CPLDs with isplever tool. I dont know if the security bit is set on these.Do these look like valid jedec files, or did I read out crap, because of security bit?Thanks
Signals in VHDL - Page 1
Forum section: electronics / general

author: Razvan1203
author_rank: Newbie
timestamp: February 24, 2025, 08:01:12 am
content: I need to convert a C function to a vhdl code. In the C function there is an array uint32_t a and I convert it to a signal in vhdl (type array_type is array (0 to 19) of std_logic_vector(31 downto 0); ). I made a FSM for this implementation and the problem is when I try to assign some values to the array (a(i) <= some_value;),However, when I check in simulation (waveform), all values remain 'X', even after a few clock cycles.What could be the reason for this behavior?Additional details:i is properly incremented.The value assigned (some_value) is well-defined (not 'X').The FSM transitions correctly through states.I have tried using an initialization process for a, but still get 'X'.Any ideas on what could be wrong?

author: rstofer
author_rank: Super Contributor
timestamp: February 27, 2025, 03:56:26 pm
content: Show the codeShow as little code as is necessary to demonstrate the problem. Nobody wants to pour over thousands or even hundreds of lines of code.
BrisbaneSilicon - Lumorphix Processor IP - Page 1
Forum section: electronics / general

author: BrisbaneSilicon
author_rank: Newbie
timestamp: February 27, 2025, 11:51:23 am
content: Hi all,Our company, BrisbaneSilicon, has a new IP offering - Lumorphix Processor IP. We've released a Beta Release, targeting the Tang Nano 9k FPGA development board.Additional info:https://brisbanesilicon.com.au/products/lumorphix/https://brisbanesilicon.com.au/docs/Lumorphix_ProductSummary.pdfhttps://brisbanesilicon.com.au/products/lumorphix/beta-releases/#beta-release-02.0001https://brisbanesilicon.scrollhelp.site/lumorphix/Feel free to join our mailing list - we're running a promo soon giving away a couple thousand Tang Nano 9k's, pre-loaded with our Lumorphix Processor - first couple thousand to join the mailing list will get one.Cheers!
A more precise clock PMOD - Page 1
Forum section: electronics / general

author: hamster_nz
author_rank: Super Contributor
timestamp: February 17, 2025, 02:41:19 am
content: Just finished the initial tests of a Voltage Controlled Temperature Compensated 20 MHz Oscillator that I've been wanting to build for a long while, but never had enough spare pocket money for parts.I settled on 20 MHz as it is fast enough to go into PLLs and MMCMs, but slow enough to work with PMOD headers.After tweaking the trimpot, referenced to a GPS PPS, after 5min30 it was out bu about 2 microseconds - so about 6 parts per billion. Am pretty keen to get get the DAC and control loop up and running...The SiT5155 VCTCXO seems to be much nicer than a OCXO - at 3.3V @ 50mA is ideal for a PMOD.(Yes, I will give the board a clean after I finish testing...)If anybody wants the KiCAD files just ask - only known issue is that the footprint for U1 is wrong - oh, correction it actually has the wrong part on there - I got my parts mixed up..

author: colorado.rob
author_rank: Frequent Contributor
timestamp: March 01, 2025, 04:23:27 am
content: The DCTCXO version of this TCXO has 26 bits of frequency control. Why go with a VCTCXO + 14 bit DAC?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 01, 2025, 08:30:18 am
content: Quote from: colorado.rob on March 01, 2025, 04:23:27 amInteresting point.I see digikey have stocks of SIT5501A-WU-0002 DCTCXO at $43.65, cheaper than many SiT5155 and that SIT5501A specsType DCTCXOFrequency 10 MHzOutput LVCMOSVoltage - Supply 3.3VFrequency Stability ±10ppbOperating Temperature -40°C ~ 85°C

author: colorado.rob
author_rank: Frequent Contributor
timestamp: March 01, 2025, 03:28:57 pm
content: Quote from: PCB.Wiz on March 01, 2025, 08:30:18 amOne can get the SiT5155 direct from SiTime for even less. Lead time may be longer.

author: hamster_nz
author_rank: Super Contributor
timestamp: March 04, 2025, 12:31:23 am
content: Quote from: colorado.rob on March 01, 2025, 04:23:27 am1. An Artix-7 PLL needs > 19MHz clock input, so 10MHz or 12.5MHz would add additional constraints on how the clock could be used.2. It is going through a PMOD connecter, so has dodgy SI to begin with, so I wanted to keep the frequency low, so 25MHz or 20MHz.3. I wanted to have the option to use the trim-pot for manual trimming if I decide to use it for other projects (e.g. with analog VCXO control)4. I wanted it to be a part that Element 14 had in stockFor a holiday idle-time-waster project it was totally fine, would do again.