LVDS Clock generation (x100 multiply) - Page 1
Forum section: electronics / beginners

author: vpetrog
author_rank: Contributor
timestamp: February 02, 2017, 08:15:23 am
content: Helo,I am designing a project in which i need two clock sources (LVDS) one which is around 1.677 Mhz (2^24/10 MHz) and another which is 167.7 MHz (2^24*10 Mhz), one of them will be active at one time,(so i need to select between them) Currently i have two CMOS oscilators one in each desired frequency, then i use an Analog Mux to select the frequency i want and finally i feed the CMOS signal into an LVDS driver. However, i believe, and i think you will agree, this is not the smartest way to do it.My question is, is there a better more efficient way to do it, like using a PLL (I have searched but i couldn't find any).Thanks in advance.PS. Since i'm new to this forum, i wasn't sure if i should create a topic in the Beginners or the Project Section, so if you think this is off-topic, please correct me

author: vpetrog
author_rank: Contributor
timestamp: February 03, 2017, 04:01:35 pm
content: I have finally founf the IC, that i wanted but it is a bit pricey, i have another question though, the IC outputs a PECL Clock. The receiver IC can accept a PECL signal, so my question is, do i need to use a PECL driver?

author: dmills
author_rank: Super Contributor
timestamp: February 03, 2017, 05:03:28 pm
content: If the chip outputs a PECL signal and the receiver takes a PECL signal (and there is only a single receiver) then no external driver is required.Note that you still need the usual PECL termination bias network, AC coupling for a 50% duty clock is possible if you need it for common mode fixups.Read the datasheets carefully, especially the bits dealing with PECL termination and common mode voltage.What are your jitter requirements?I might have been tempted by a single 167.7MHz osc driving a little minimal gate array of the on chip flash sort and using this to divide by 5 and then 2 (so as to get a square output). It can also do the clock mux, conversion to LVDS/PECL and any other level shifting required. Of course then you need to write the page or so of VHDL to configure the thing.This sort of use of toy programmable logic is always worth considering as it can make a lot of level translation pain go away, and some of the small parts do not need the traditional 1.0V or so painful core voltage.Regards, Dan.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 03, 2017, 05:10:47 pm
content: Divide is easier than multiply. (Indeed, almost all multipliers are actually a PLL with a divider -- using a control loop to solve for the inverse of the divider.) If you have the 167.7MHz on all the time, then this will be just fine, and saves you the 1.677 source.Tim

author: vpetrog
author_rank: Contributor
timestamp: February 03, 2017, 05:40:08 pm
content: thank you very much for your answers i have found this particular IC FS7140 which is an I2C controlled Programmable PLL, with PECL output.My jitter requirement is around 50-100ps for 167 Mhz. The FS7140 datasheet recommend a thevenin termination output,although the Datasheet is not very clear. I should also add that the IC output acts as a current sink. The receiver on the other hand requires a differential PECL/LVDS signal. I have come up with the following design, however i am a bit worried about DC bias. What's your opinion ?EvangelosPS. As far as VHDL is concerned i have no idea yet