Decoupling on microcontrollers - Page 1
Forum section: electronics / beginners

author: noname4me
author_rank: Regular Contributor
timestamp: January 21, 2018, 06:04:40 pm
content: Hi,I was reading through TI's app note: AN01283 - System DesignGuidelinesfor Stellaris Microcontrollers and was confused by the decoupling section.http://users.ece.utexas.edu/~valvano/EE345L/Labs/Fall2011/SystemDesignGuidelines.pdfOn page 4 is the attached image - I was under the impression that the cap comes closer to the IC than the vias and not the other way around.Can someone explain if I have misunderstood, or is the app note mistaken?Thanks

author: Zero999
author_rank: Super Contributor
timestamp: January 21, 2018, 06:29:03 pm
content: It appears the power is going through the vias, from another layer, in which case, it makes sense to have the vias in between the capacitor and the IC.

author: Nusa
author_rank: Super Contributor
timestamp: January 21, 2018, 07:21:56 pm
content: The chart seems to be specific to boards that have dedicated power and ground layers.Vias can be placed much closer to pins than components can.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 21, 2018, 10:01:17 pm
content: Yes, relevant to multilayer boards.For two layer boards, pour ground on both sides, add GND stitching vias around all traces (about one every few cm, prioritized around crossing traces, peninsulas and islands), and route VCC as a normal trace.VCC should be routed in such a way as to avoid resonances. The easiest way to do this is to stick to a simple network design: a single chain, routed from load to load, with minimal stub length (a short branch off the main route), and regularly spaced capacitors. Place a lossy bulk capacitor at the start and finish (usually electrolytic or tantalum), with value several times the total (small ceramic) bypass on the route.More complicated arrangements (long stubs, loops, LC filtering) can be designed as well, but as fits the arrangement -- it is less simple to explain the process.The underlying theory is that trace lengths (including via height, pin length, and component length) act as inductors, at the low frequencies where the supply can resonate. A bunch of bypass caps dotted along those trace lengths means you have alternating L and C, a lowpass filter. A filter has a characteristic impedance. It is this impedance which you are terminating, and the bulk capacitors provide ESR for this purpose.The bulk capacitors are not being used to store energy; indeed, the last thing you want is for the supply to cycle energy back and forth -- to do so would require that the voltage can change, which makes for a very poor supply indeed! The goal is actually a minimal change in energy of the supply, so that the power delivered can be as stable as needed. What the bulk caps are doing is simply dampening the network -- indeed, the energy storage is actually an inconvenience. (You can actually get high voltage capacitors, which store less energy, by way of having less capacitance at low voltages, becoming active at high voltages. They're rather niche, though, and I don't know of any that work at low voltages.)Incidentally, inductors store energy, too, so you want to minimize the stray trace and component length around the MCU supply pins. The loop distance, from power pins to the first bypass cap, is what matters.Tim

author: noname4me
author_rank: Regular Contributor
timestamp: January 22, 2018, 01:47:43 pm
content: Quote from: T3sl4co1l on January 21, 2018, 10:01:17 pmHiThanks this explains it well.Do you have any references that i can read further on this please?I was reviewing another engineer's work the other day and noticed that the analog portion of the board had more than 1 0 ohm link to the main ground plane which contained digital circuitry, without any impedance between them.Why would this be? I could understand 1 star point and an inductor bead to provide HF impedence but this wasn't there.Would the multiple connections to ground not cause some sort of ground loop?ThanksSent from my SM-G935F using Tapatalk

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 22, 2018, 05:26:05 pm
content: Quote from: noname4me on January 22, 2018, 01:47:43 pmYou're asking the wrong guy for references, unfortunately... I developed this methodology by thinking about the fields. Probably Ott (Henry Ott,Electromagnetic Compatibility Engineering, Wiley) and such contains this and more?If others could chime in, that would be great.QuoteA weak ground is almost always a bad idea, and must be used very, very carefully.It sounds like this was not done in this case...Appnotes probably suggest it, just because they need to cover a couple of possibilities, even when some of those possibilities are way out in the "you'll never need this" territory. Or, more likely, the authors themselves saw a method and thought "oh hey this looks different, let's put this in", without a care for how devastating it can be to abuse the ground like that.Multiple points makes ground loop, yes, but how much this matters depends on the voltage between those points. It's usually better to make ground so large and solid that it is solid loops -- this keeps any local current path as short as possible, and as low impedance as possible. Thus, at a distance, the ground loop current, and voltage developed, is very small. Maybe not as small as a carefully tuned split plane, but it requires far, far less experience to pull off correctly.The grossest mistake made on split planes is routing traces across the split. You put the split there, specifically toallowa voltage difference between the faces of that gap -- and now you're routing traces clear across it? Not only does this impose 100% of that split voltage upon the traces, it also puts the traces' noise into the gap, making EMC that much worse.You must route traces across a web connecting the planes. The plane necks down, but does not come to a single point. There cannot be a single point in real electronics (a zero-width trace would be all inductance and resistance, after all). The goal is never "minimize" but "optimize". We cannot get, and do not want, a pointlike plane connection: so what do we want? Well, at least enough width to support the traces crossing the gap. Or, if you've done the split-plane-under-IC thing, then at least the width/length of the IC, and anything that needs to go around it (like supplies). (What ICs usually do internally, is have two connections to the substrate. There is an ohmic connection between DGND and AGND. Imposing voltage across those, causes current to flow through the die itself! Short that out, so the IC isn't getting stressed first of all.)A necked-down plane is a perfect opportunity to place filters, as well, so that AVCC can be filtered and bypassed to AGND, at the device.But you see, it quickly gets complicated, and not only is it something no novice or rookie should attempt, but it is something that even a master uses only very rarely.Tim

author: Dubbie
author_rank: Unknown
timestamp: January 22, 2018, 05:35:05 pm
content: This was posted just in time for me to revise a 4 layer board I was about to send off. I too, didn’t realise that vias should be closer than the cap. After reading this thread it makes sense. Thanks!

author: max_torque
author_rank: Super Contributor
timestamp: January 22, 2018, 07:11:56 pm
content: RE: Via's closer to IC pins than Cap:If the Via's supply a, er, supply, that has lower impedance than the capacitor, what does the cap actually do?

author: tszaboo
author_rank: Super Contributor
timestamp: January 22, 2018, 07:35:22 pm
content: Quote from: max_torque on January 22, 2018, 07:11:56 pmThe cap filters the power supply. Right?Think about it this way:You have to filter the power in many frequency region. The 470uF elco capacitor is going to filter the 10KHz.It can be far away from the IC, because inductance for that frequency is small.The 10uF ceramic is 1cm away. It filters the 1MHz region.The 100nF capactor is very close, and it filters up to some 200MHz.And the capacitance between the ground and power plane filters higher frequencies. It is a few pF only, but it's inductance is really really small. You need to connect this as close to the pin as possible. It handles very very high frequencies.Of course, you dont have this problem with 16MHz 8 bitters or two layer boards. But you actually do, except bad engineers decided to ignore the problem (since their boards never have to go through IEC61000 or anything remotely serious), and release their IP as open source, and now everyone copies their bad practice.

author: noname4me
author_rank: Regular Contributor
timestamp: January 22, 2018, 10:25:01 pm
content: Hi,Regarding the PCB that I was looking over:It's just passed EMC, and radiated immunity (which is traditionally a difficult test for this type of device) was tested to 30V/m at certain spot frequencies, so I know it was good enough for the application that it was required for.The confusion rested on why the designer connected the grounds in multiple places - the only tracks routed over the grounds were the comms lines to the ADC? (I may be mistaken here - it is either the opamp output or the comms).Speaking with the guys that ran the site, they gave tips for grounding schemes which they consider to be the best for the application that we are using the boards in, and they spoke of having analogue ground connecting via an inductor/capacitor filter at a single point to the "dirty" ground that brought signals into/took signals off the board, at a distant end from the main ground connection. The next nearest to the main ground connection would be the digital circuitry with similar filtering applied, and lastly the high current components connect straight to the dirty ground (like pump/other high current stuff).One of the design changes made to a similar board did almost exactly this to deal with an ESD issue (it passed after the changes were made).I was curious about why the multiple ground connections to the analogue ground would not mess with the circuit in the Radiated Immunity testing; I would have expected it to. If it isn't too much trouble, could you have a go at explaining it in terms of fields? I have done the maths for understanding fields, but not in terms of EM fields - I am not averse to getting dirty with the maths if I need to.I'll check the board again in a couple of days; the designer is a good one (not my department) and it is nice to be able to see aspects of the design and understand why he did things in certain ways.Thanks