NAND outputs tied to ground - Page 1
Forum section: electronics / beginners

author: JuanGg
author_rank: Regular Contributor
timestamp: June 10, 2019, 01:05:24 pm
content: Attached is the schematic for the square wave generator from a Hameg HM604 scope. I was just taking a look when I noticed there are three NAND gates with their outputs tied to ground. Seems that their inputs are held always high, so the output should be low anyways. Is this a way to "terminate" gates, as one would do with an unused op-amp? But one would not care about the outputs then.It also seems that amplitude is controlled by changing the supply of the output gates, it seems to be a sort of voltage regulator in there, although I don't see how it regulates without feedback.Any ideas?Juan

author: Zero999
author_rank: Super Contributor
timestamp: June 10, 2019, 03:22:47 pm
content: No, the output of unused or any gates shouldn't be directly tied to either supply rail, but left unconnected. It's only the inputs which need to be connected to +V or 0V, to prevent them floating.

author: wraper
author_rank: Unknown
timestamp: June 10, 2019, 03:41:52 pm
content: Quote from: JuanGg on June 10, 2019, 01:05:24 pmNope, it's when someone designs a circuit without an idea what he/she is doing. Shouldn't cause failure but it's really dumb.

author: Andy Watson
author_rank: Super Contributor
timestamp: June 10, 2019, 03:54:39 pm
content: I would hope that Hameg do know what they are doing! The chip is question is driving the output with fast edges - my guess would be that it's an attempt to lower the ground impedance to the substrate of the chip.

author: wraper
author_rank: Unknown
timestamp: June 10, 2019, 04:27:59 pm
content: Quote from: Andy Watson on June 10, 2019, 03:54:39 pmIf they cared about impedance, they would connect multiple logic gates in parallel. Not attach 600 ohm load to the output of single gate.

author: Andy Watson
author_rank: Super Contributor
timestamp: June 10, 2019, 04:31:18 pm
content: Quote from: wraper on June 10, 2019, 04:25:44 pmBut then you would have to be sure that all the output transition at the same time, otherwise you could end up with a step in the output waveform. I don't know why Hameg have used that arrangement - I'm only guessing. I've never seen it used anywhere else.

author: Zero999
author_rank: Super Contributor
timestamp: June 10, 2019, 04:38:21 pm
content: Quote from: Andy Watson on June 10, 2019, 04:31:18 pmThe difference in transition times shouldn't be that great and will be of less importance for slower logic, with a relatively high impedance output.I haven't seen that arrangement before. It looks pretty stupid. I suppose even a good company can have engineer can go full retard on a design once in a while.

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: June 11, 2019, 04:34:55 am
content: I can't find a reference, but Xilinx recommended doing something similar with unused FPGA I/Os in an app-note. It will lower the impedance of the ground connection (more bond wires connected to ground), which decreases ground bounce inherent to single-ended logic. I can't see why this would be important in this low-frequency application, though.

author: Brumby
author_rank: Unknown
timestamp: June 11, 2019, 05:08:31 am
content: Quote from: Zero999 on June 10, 2019, 03:22:47 pmThis ^ ^ ^I would never leave unused inputs floating - and I would never tie unused outputs to anywhere.While I might not say this, it doesn't stop me from thinking it....Quote from: wraper on June 10, 2019, 03:41:52 pm

author: David Hess
author_rank: Super Contributor
timestamp: June 11, 2019, 03:33:46 pm
content: Quote from: wraper on June 10, 2019, 04:27:59 pmNo, Andy is right. They tied the inputs high and then tied the outputs to ground to lower the ESR and especially ESL of the ground connection which lowers the ground bounce.No matter how many gates are placed in parallel within a single package, the ESL of the ground and power connections limit performance. This was a big problem with Fast Advanced Schottky TTL and similar CMOS logic families; they never met their actual performance potential or sometimes specifications because of the inductance of their ground and power connections.

author: wraper
author_rank: Unknown
timestamp: June 11, 2019, 04:15:41 pm
content: Quote from: David Hess on June 11, 2019, 03:33:46 pmHow this is supposed to help when there is no such thing on positive side? Making this on GND side only does not make much sense, especially when load is pulling output to the GND anyway. Not to say output mosfets have quite large RDS(ON)to make much difference.

author: Zero999
author_rank: Super Contributor
timestamp: June 11, 2019, 04:33:18 pm
content: Yes, the 74HCxx series have an on resistance of 38Ohms, which won't make much difference. I can see it making more of a difference with something really high speed, such as an FPGA though.

author: jmelson
author_rank: Super Contributor
timestamp: June 11, 2019, 06:51:17 pm
content: Quote from: JuanGg on June 10, 2019, 01:05:24 pmActually there are THREE outputs tied to ground. I suspect this is a very inventive circuit. Pin 14 is connected to T41, They are using a feature that putting a low on the input of the gates causes it to pull current from pin 14 to the grounded outputs, and that pin 14 then feeds some circuit.Jon

author: David Hess
author_rank: Super Contributor
timestamp: June 11, 2019, 07:02:01 pm
content: Quote from: wraper on June 11, 2019, 04:15:41 pmThey could have done both power and ground but I assume they were only concerned with the ground lead inductance as the outputs were pulled low. It is common for only the performance of one edge to matter.Quote from: Zero999 on June 11, 2019, 04:33:18 pmIt is not the ESL [Update: I meant ESR] of the ground (or power) connection which matters; it is the parasitic inductance.And since the added connections to ground in this case each have the same series resistance as the output driver, they are still useful in lowering the inductance to ground.Later logic families moved the ground and power connections to the middle of the lead frame and eventually added multiple ground and power connections. But FAST and AC logic were plenty fast enough to have their performance limited and I suspect in critical applications such as this, HC logic was fast enough also or at least Hameg thought so. (1)(1) This is actually one of the disadvantages of fast CMOS logic families compared to fast bipolar logic. The constant current output characteristics of a bipolar transistor output stage yield a better ratio of rise/fall time to delay time. For equal delay time, the faster RC output characteristic of CMOS is makes it more sensitive to power supply impedance because of higher dI/dT.

author: wraper
author_rank: Unknown
timestamp: June 11, 2019, 07:02:49 pm
content: Quote from: jmelson on June 11, 2019, 06:51:17 pmDo you really understand what you wrote? T41 simply works as vreg to power 74HC00. 3 gates just stay static all of the time, all of them are simply connected in parralel. There is nothing inventive about that.

author: David Hess
author_rank: Super Contributor
timestamp: June 11, 2019, 07:04:16 pm
content: Quote from: jmelson on June 11, 2019, 06:51:17 pmThey might also have picked which three to use to help present a better transmission line environment to the fast output. Tektronix did this sort of thing with their own custom ICs to get maximum performance out of leaded packages.

author: amyk
author_rank: Super Contributor
timestamp: June 12, 2019, 01:46:02 am
content: I suspect it may have a non-functional purpose:https://en.wikipedia.org/wiki/Trap_street

author: JuanGg
author_rank: Regular Contributor
timestamp: June 14, 2019, 01:50:57 pm
content: Thanks to everyone. It makes for an intriguing topic.Juan