Track length matching between FPGA and memory - how good does it need to be? - Page 1
Forum section: electronics / projects

author: Boscoe
author_rank: Frequent Contributor
timestamp: February 21, 2016, 11:07:49 am
content: Hi there,i would say I'm very competent with PCB design but never before have I had to route BGA to BGA FPGA to memory before. In my design the memory is going to be clocked around 50MHz. My current maximum track length difference is 12mm. I wonder how I should calculate the propagation delay. I assume but assume the propagation to be near the speed of light and then divide by the frequency to find the wavelength of the signal?ThanksBoscoe

author: HAL-42b
author_rank: Frequent Contributor
timestamp: February 21, 2016, 12:55:24 pm
content: I believe this is more dependent on the rise time and not on the clock frequency. The rise time is much higher than the frequency might suggest so it is a bit more demanding.In any case you are looking at propagation times of 0.8ns/100mm (rule of thumb, substitute with actual data) so a difference of 12mm would produce 0.086ns delay. Unlikely to cause a problem as long as you have proper termination.QuoteSource PDF

author: uncle_bob
author_rank: Unknown
timestamp: February 21, 2016, 01:57:22 pm
content: HiIf you look at the "delivered wisdom" on pcb layout to a memory chip the answer seems to be "keep it under 1 mm". A typical layout has a lot of weird looking serpentine tracks going to and from the memory. That's not just on one design or one board. You see it all over the place. You also see it stated in layout rules as "matching to 10 ps" on the lengths.As you have observed, you have a clock that is running at a period of 20 ns. Three orders of magnitude seems a bit extreme. The missing element is "timing closure". The FPGA and memory have to meet certain setup and hold times on the lines. Laying out a board to the "normal guidelines" lets you drop the board out of the timing analysis up to a few hundred MHz. At 50 MHz, you probably can step back a bit on the matching. The other alternative to tight matching is to measure the lengths and punch them into the timing math. Then beat on the FPGA to make it all happen. If it does not happen ... back to board layout.This all assumes that these are not balanced lines (ECL or LVDS). If they are, then you do need to keep things pretty well matched regardless of clock frequency.Bob

author: AndyC_772
author_rank: Super Contributor
timestamp: February 21, 2016, 04:36:09 pm
content: You need to know what the setup & hold timing margins are, and that can be quite complex and involved; just knowing the clock speed alone is useless.It may, for example, be the case that the memory device requires zero (but not negative) hold time on writes, and the driver guarantees zero hold time (but no more). In that case the design can still work, but the data lines need to be longer than the clock or strobe that causes them to change state. How much longer depends on how much margin you think the design needs.Or, the FPGA design may have timing specifications which turn out to be highly tolerant of skew between data, clocks and strobes. In that case, you may not need to obey any particular rules at all provided all your trace lengths are reasonable (for some definition of "reasonable").It's no exaggeration to say that the timing and layout of a memory interface can be an horrendous problem to try and solve. To do it properly, you have to consider every relevant relationship between the different groups of signals, and compare the fastest and slowest possible specifications from the respective data sheets across all variations from device to device and over temperature.

author: marshallh
author_rank: Unknown
timestamp: February 21, 2016, 07:24:00 pm
content: at 50mhz clock, you have 100mhz data rate because of DDR. Note that since 50mhz is below the working DLL minimum for DDR2, you must be useing mobile SDRAM or DDR1.if you are using SDRAM, things are pretty simple. Just generate a phase shifted clock via PLL so that it's aligned with the middle of the valid data with respect to the ram device.DDR gets more complex. You have to consider whether you are using a prerolled ram core, writing your own, whether or not you will ignore DQS inputs or capture with them, etc. Additionally the phase relationship between data and address/cmd are different, and it changes between reads and writes.Anyway the short story is you will be fine with 12mm, but why not at least halve it. I've done worse long ago

author: John_ITIC
author_rank: Frequent Contributor
timestamp: February 22, 2016, 07:47:44 pm
content: Quote from: Boscoe on February 21, 2016, 11:07:49 amYou don't mention what memory technology you are using but at 50 MHz, I would say that you don't have to worry about length matching at all. Just make sure you properly configure your FPGA timing such that the clock edges are lined up in the middle of the data. I have done DDR2 memory interface designs clocked at 267 MHz with Altera FPGAs and at that low frequency the timing was not terribly critical. In practical terms, you would only need to worry about detailed timing if the clock frequency goes up to several hundreds of MHz. Low to mid-end FPGAs, however, typically don't support much higher frequencies than 200-300MHz.