Overvoltage protection with a twist - Page 1
Forum section: electronics / beginners

author: GarthyD
author_rank: Regular Contributor
timestamp: April 06, 2017, 10:36:16 pm
content: I am designing a test setup which is being used to test another PCB. The MCU performing the tests is a SAM4S, which is running at 3.3V, which can tolerate up to 3.6V I/O. The board being tested may have voltages up to 6V. There are a number of test pins. Each test pin is connected to a single MCU pin, and I can control the circuitry between the MCU and test pin. I need to add overvoltage protection in some form to protect the MCU pins. There are also a number of additional constraints that complicate the problem. I've included an attempted solution below, and would welcome any feedback.The constraints are as follows:- Voltages of up to 6V may be seen on the test pins.- The MCU can handle up to 3.6V (3.7V as an absolute maximum) on its I/O pins. 150mA absolute max total across all I/O. 2-4mA sink/source per pin. More info:www.atmel.com/images/Atmel-11100-32-bit%20Cortex-M4-Microcontroller-SAM4S_Datasheet.pdf- I need to use the internal pullups/pulldowns (aprx 100k, low precision) on the MCU and have their pulls respected when I read them. For example, if I enable the pullup and the test pin is floating, the pin must read logic high. Similarly for the pulldown and logic low.- The MCU pins need to be able to output something to the test pins that the other test pins will see if shorted to the pin outputting. This signal will generally be low (ie. ~0V), but I'd like to support high (3.3V) in case I need it. The output will not be on very long- generally well under 1ms.- I need to measure voltages seen through ADC on the pins, and the ADC reference is 3.3V. Measurement does not have to be precise (eg. +-0.1V isn't unreasonable), but it does have to be able to measure voltages all the way up to 6V.- The tests are run very fast repeatedly (too fast for a human to observe) and a connection may be made between the test pins and the PCB at any part of the process. For example, a MCU pin may be set to output ground, and whilst it is checking other pins, a test pin connected to this pin may end up connected to a 6V output.The solution I've come up is attached. I've included just two pins but it is easy enough to extrapolate this to an arbitrary number of pins. Some notes:- I've included a single signal coming out of the MCU that enables an N-channel MOSFET per test pin with a resistor to ground. When enabled, this forms a voltage divider, which roughly halves the voltage seen by the MCU, increasing the range I can measure. I would enable this output before doing ADC that might include voltages above 3.3V. I can then disable it when performing a test that relies on the MCU pullup/downs, as the pulldown would otherwise cause the internal pullup to not be respected.- The path from each MCU pin to test pin goes through about 11k of resistance. This is enough to change the logic level when connected to another pin, but also plenty to limit current if both the MCU and test pins are outputting together.- I'm using both a Schottky and Zener to keep the voltage at the MCU at a sane level. Every path to a potential source goes through 1k of resistance minimum. The 1k at R1 and R2 is not strictly necessary, but I found it useful when testing the setup.I have a partly-working setup, but presently lack 3.6V Zeners so can't test it fully. I have tested it without the Zener (the Schottky should protect on its own) and it appears to be working.Feedback most welcome.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 06, 2017, 11:20:49 pm
content: Where does it say 3.6V?44.1 (p.1142) says VDDIO+0.4V. And VDDIO max 4.0V, so the worst-case pin limit is 4.4V.The recommended operating conditions, and other ratings, are consistent with the pins having input protection diodes to VDDIO and GND.You can use series resistors to limit current into these pins. No need for anything fancy.Beware of gotchas when using input protection diodes, like screwing up nearby analog hardware (ADC reads offset or nonsense when analog port diodes are forward-biased).More to the point, though... what the hell is wrong with your test provider that they can't give you 3.3V logic, and ESD protection for that matter? Dump them immediately!Tim

author: Ian.M
author_rank: Super Contributor
timestamp: April 06, 2017, 11:33:32 pm
content: The Zeners don't do much if anything except protect against negative voltage as the Schottkys clamp before they conduct significantly. Replace them with Schottkys.I don't like clamping to the 3.3V rail. Each input can dump a little under 3mA into it. Is the minimum load on the 3.3V rail >3*N testpins? If not, you need a precision clamp. You can use a pair of matched PNP BJTs to provide a clamping rail that shunts to ground, referenced to the 3.3V rail, (andhereis one I designed earlier), or you can buy it all in one chip for up to six clamped circuits, theTL7726.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 06, 2017, 11:47:20 pm
content: Quote from: T3sl4co1l on April 06, 2017, 11:20:49 pmSAM4S series complete specification, p.1143, table 44-3, under VIH maximum. Value is VDDIO + 0.3V, with VDDIO 3.3V this is 3.6V. Absolute maximum listed earlier is VDDIO+0.4V, giving 3.7V. There seem to be two values of consequence here. Of course, I could be interpreting this incorrectly, bear in mind the experience difference here. :}Quote from: T3sl4co1l on April 06, 2017, 11:20:49 pmThat would simplify things somewhat.I tried, but wasn't able to find anything confirming their presence, nor their specs, which made it hard to determine what I could safely count on them to do. My level of experience isn't high enough to infer or confirm their presence unfortunately. I don't mind adding the external components for peace of mind, bearing the warning re ADC in mind of course. I don't suppose there is a safe way to test/confirm their presence?Quote from: T3sl4co1l on April 06, 2017, 11:20:49 pmCheers for the warning. I was unaware of this. This is exactly the sort of thing I was hoping people would pick up on when I posted this thread. Thanks!I'll keep an eye out for this problem.Quote from: T3sl4co1l on April 06, 2017, 11:20:49 pmI shall set about dumping myself immediately.More seriously: I am doing everything myself. The numbers are far too low at this point to start setting up a full-on exhaustive test rig, or even dedicated hardware beyond what I happen to have lying around, but I do want to set up something basic.Many thanks for sharing your thoughts on my current setup, much appreciated.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 07, 2017, 12:42:08 am
content: Quote from: Ian.M on April 06, 2017, 11:33:32 pmThanks. I was bordering on making this change and this is the push I needed to commit.Quote from: Ian.M on April 06, 2017, 11:33:32 pmDammit. I just *knew* that that clamping in this way was the wrong thing to do, but there are so many examples out there doing it in exactly this way without much in the way of warnings that I had assumed I must be mistaken. I should probably point out that this is the first time I have had to look into overvoltage protection, so I would expect some issues as I stumble around trying to figure it out.I was probably looking at about ten test pins, but it'd be nice to be able to add more. I don't think I can guarantee a minimum load on the 3.3V rail short of deliberately adding something to chew up current. Maybe I could hook up a string of LEDs to make a really bright power indicator?Quote from: Ian.M on April 06, 2017, 11:33:32 pmThis is all new to me. I'm starting to read up on it now. Thanks for the potential solution and suggested TL7726, much apprecated.Would I be correct to assume that the *right* way to solve this problem in general would be to use a precision clamp and not fuss about with ensuring that there is a certain minimum load on the 3.3V rail?One question re the TL7726 in particular: Is it a single TL7726 clamp pin for any number of test pins, or one clamp pin per test pin I am using? Basically: If I was clamping 12 inputs, is that two TL7726s or one? EDIT: I've been reading up on this and it looks like one clamp pin per signal (ie. MCU pin / test pin pair), but it replaces the Schottkys. I could be completely wrong though, I'm still reading up about it.I'm putting in an order for some parts today so can potentially order any parts that would give me a better result. I don't mind picking up anything that is either relatively cheap, or not so cheap but generally useful for other problems in the future. In any case it'll be a while before I get the parts, so if I do solve this with ordered parts I'll have to move on to other things until the parts arrive. I will probably receive the parts *just* before the real PCBs arrive.Thanks for taking a look at things and for sharing your thoughts, much appreciated.

author: Ian.M
author_rank: Super Contributor
timestamp: April 07, 2017, 01:16:28 am
content: If you've got power hungry MCUs and displays heavily loading the supply rail, clamping to it is acceptable, provided you do the math for the max current that can get dumped into the rail, and how much time you can tolerate excess current into the bulk capacitance, before the rail rises above the abs max Vcc of the weakest load. Putting an extra load on the 3.3V rail is a bodge - don't do it!The TL7726 is designed for one input per clamp pin. You are building a presumably $expen$ive$ one-off or limited qty professional test jig so the extra couple of bucks for two TL7726 and peace of mind is absolutely worth it.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 07, 2017, 01:53:17 am
content: Quote from: Ian.M on April 07, 2017, 01:16:28 amMy current setup is quite possibly the worst possible case for these conditions. The test results are offloaded from the MCU to a PC over USB where they are displayed, meaning that much of the time there is very little drawing current. The biggest current draw is probably going to be the MCU itself. At present the MCU just runs full-speed all the time, but if it actually had power-saving code written for it, then it would have failed to meet the minimum current criteria you mentioned.Quote from: Ian.M on April 07, 2017, 01:16:28 amThanks. I'd been reading up on it and that was the impression I was forming, but I'm much more comfortable hearing that from someone familiar with it. It looks like it replaces the Schottkys as well- I had assumed that you still needed them. Incidentally I have also stumbled upon SLAA004 and it is interesting reading.Quote from: Ian.M on April 07, 2017, 01:16:28 amYou're right. I can guarantee there would be tears if my current setup fried. Many thanks for the TL7726 recommendation. I'm going to add at least two of these to my order, which should be enough to get me going. I can always buy more or experiment with other solutions later. If I absolutely must experiment with the overvoltage protection part in the meantime I'll make sure I'm burning enough current elsewhere on the 3.3V rail.Thanks yet again.

author: Mr.B
author_rank: Unknown
timestamp: April 07, 2017, 02:05:26 am
content: Pardon my potential ignorance, but what is wrong with a level shifter?Same concept as 3.3v to 5v I2C.As per schematic below, except 6v instead of 5v.

author: Ian.M
author_rank: Super Contributor
timestamp: April 07, 2017, 02:12:17 am
content: AAGH!!! I've just noticed that theTL7726 has a minimum reference voltage of 4.5V(I don't do much 3.3V stuff) so that's out for your application. Either use my suggested PNP circuit + Schottkys or possibly better Schottkys into a TL43,1 or possibly a TLV431 boosted with a PNP emitter follower*, set to 3.3V, and with a pullup resistor to before your 3.3V regulator to keep it biassed.* see Fig.21 in the TI TL431 datasheet for high current shunt regulator circuit to use with the TLV431.@MrB: The O.P. wants to be able to use programmable weak pullups AND pulldowns.

author: Mr.B
author_rank: Unknown
timestamp: April 07, 2017, 02:17:31 am
content: Quote from: Ian.M on April 07, 2017, 02:12:17 amSorry. I should have read more closely.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 07, 2017, 02:18:09 am
content: Quote from: Mr.B on April 07, 2017, 02:05:26 amI believe this may fail one of the criteria listed:> - I need to use the internal pullups/pulldowns (aprx 100k, low precision) on the MCU and have their pulls respected when I read them. For example, if I enable the pullup and the test pin is floating, the pin must read logic high. Similarly for the pulldown and logic low.I believe the 100k internal pulldown may fail to generate a logic low in this case as it will be getting pulled up by R2 (10k) as well. I could be mistaken though, so please let me know if I am in error.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 07, 2017, 02:25:16 am
content: Quote from: Ian.M on April 07, 2017, 02:12:17 amThat's not good.It seemed like this would be the perfect solution.

author: Mr.B
author_rank: Unknown
timestamp: April 07, 2017, 02:26:37 am
content: Sorry, you are correct.As Ian.M pointed out also.I did not read your OP closely enough.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 07, 2017, 02:38:33 am
content: Mr.B: Not a problem. Thanks for taking a look at things and suggesting a possible solution.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 07, 2017, 05:37:30 am
content: Quote from: Ian.M on April 07, 2017, 02:12:17 amDespite considerable searching I have been unable to find a suitable example online of using something like the LM431 to provide overvoltage protection. I lack one to experiment with, and my understanding is not strong enough to piece this together by theory. This is making it difficult to determine how to use the LM431 to solve this problem.If I had to guess, I would be using a pair of resistors from REF on the TL431 to ground and the intended 3.3V-ish rail (maybe less, maybe more?). A series resistor on the 3.3V-ish rail would go *somewhere*. Then, for each test/MCU line, I'd then use a Schottky from the test/MCU line to the 3.3V-ish rail, and from ground to the test/MCU line, similarly to the original solution posted but swapping the Zener for a Schottky. As for the vaule to adjust to, I'm not sure if I should be starting at 3.3V or 3.6V, or adjusting for the Schottky or not.Or perhaps the idea is to use the TL431 as a Zener replacement, meaning I'd need one per test/MCU line, swapping the Zener out for the TL431 in each case.Am I heading in the right direction here?Quote from: Ian.M on April 07, 2017, 02:12:17 amI'm sorry. My level of electronics knowledge appears to be insufficient to be able to understand this suggestion.

author: Ian.M
author_rank: Super Contributor
timestamp: April 07, 2017, 06:54:07 am
content: For such a low voltage, you cant 'boost' a TL431 because its minimum voltage of 2.5V + 0.7V Vbe stack up to 3.2V - too close to the voltage you need, so you must substitute a TLV431, which has half the minimum voltage (and half the reference voltage) and an order of magnitude less minimum current.See theDiodes Inc. TLV431 datasheet- its more informative than the Texas Instruments one.Scroll down to 'Other Applications of the TLV431'.Bingo!Q1 is PNP, emitter up - the original datasheet is unclear.Ideally feed Vin from >3.3V but at a pinch you could clamp to 3.0V feeding it from your 3.3V rail. Choose the resistor R3 to keep a couple of mA current to keep the TLV431 *AND* the transistor biassed slightly on. Choose R4 to pass about half the R3 current when it isn't clamping so both the TLV431 and the transistor are passing some current. The transistor is non-critical but should have a HFE>80*Iclamp_max at the Abs. Max current you want to clamp, a high enough Ic_max, and a low enough thermal resistance to handle the max power, assuming it has to dissipate the whole Vout*Iclamp.If you only need to clamp a few tens of mA, 100mA short term peak, you can simply use a TL431(not TLV431) in its adjustable shunt regulator configuration without a transistor, with at least a 10uF capacitor across it, but its continuous rating will be limited by the package power handling capability, so its not a good choice for higher currents.Connect the cathodes of all your upper clamping diodes to Vout. One TLV431 + transistor, or TL431 on its own does for all the clamps.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 07, 2017, 08:06:52 am
content: Thanks for the additional detail.I'm not sure that I'm going to grasp the TLV431 plus transistor configuration at this stage, but things might fall into place once I understand the TL431 better.So, regarding the TL431. I've put together a rough guess as to how it might look when applied to the problem I am trying to solve, attached. Does it look like I am heading in roughly the right direction?

author: Ian.M
author_rank: Super Contributor
timestamp: April 07, 2017, 08:45:55 am
content: Yes, that looks OK. Personally I'd call VREGOUT VCLAMP to avoid confusion. Size the pullup resistor to pass a couple of mA - the TL431 needs at least 1mA to regulate.Unfortunately, unlike the matched pair PNP clamp I linked to on the Microchip forum, the TL431/TLV431 based circuits do not track the 3.3V rail. You should run the clamping rail no more than 5% below the 3.3V rail to avoid it compromising your logic thresholds, and as close to it as possible. Allow 2% tolerance for the TL431, and whatever percentage its divider chain stacks up to. Add the 3.3V regulator tolerance and that's the percentage that you need to shoot for above 95% of the nominal rail voltage. If the tolerance total is under 5% shoot for the nominal rail voltage. If you trim it manually you can get closer to the rail.With 12 lines to clamp and each dumping about 3mA into the clamp rail, you'll be running the TL431 at about 120mW dissipation. That should be OK unnless its got to run in a hot environment.If you need more dissipation, and want the transistor boosted circuit, drop in the TLV431 schematic I posted in place of the TL431 and every thing to the left of it, and get rid of the 100uF cap. (The TLV431 'sees' that capacitor effectively divided by the transistor HFEwhich will put it into the critical area of the datasheet STABILITY BOUNDARY CONDITION graph)

author: Zero999
author_rank: Super Contributor
timestamp: April 07, 2017, 11:38:36 am
content: Quote from: Ian.M on April 06, 2017, 11:33:32 pmGood idea!Do the transistors really need to be that closely matched?I don't see how the two transistors being matched would help because VBEfor Q1A and Q1B are very different.A bit more complex but how about using a rail-to-rail op-amp and biasing Vclamp to a diode drop below +V? The circuit can then clamp when the input voltage exceeds +V and only rise a few hundred mV above +V, depending on the current. D3 is just there in case the op-amp isn't fast enough to turn Q1 on in time. The tiny spike won't charge up the decoupling capacitors much.U1's CMR needs to include +V - 0.6V. The MCP601 could be used, if the LT1797 isn't available or is too expensive.

author: Ian.M
author_rank: Super Contributor
timestamp: April 07, 2017, 01:21:04 pm
content: They don't actually need to be matched, but it helps significantly if they are closely thermally coupled, which same-package matched pairs usually provide. As this isn't an ADC input, it doesn't require such close clamping rail control, so you can throw out the 'matched pair' requirement, (which only limited their Vbe differential so the clamping rail wasn't too many mV below the power rail), and use any same-package PNP, or even two from the same lot,, closely thermally coupled.

author: Zero999
author_rank: Super Contributor
timestamp: April 07, 2017, 01:33:48 pm
content: Another possible enhancement is another Schottky diode to lower the clamping voltage slightly, so it clips at just over V+.

author: Ian.M
author_rank: Super Contributor
timestamp: April 07, 2017, 03:14:14 pm
content: Adding a Schottky there isn't helpful unless you intend to dump a LOT of current into the clamp rail and are trying to offset it to partially compensate for Q1 Re and Rb. Even so its not much help as the base current tends to divert to Q1 as the emitter current increases, reducing the reference diode drops. Getting Vclamp under the rail is NOT actually desirable, as the original ADC application would then suffer increasing non-linearity close to FSD.Taking R4 to a higher rail to increase the pre-bias helps - if you can match the current through R3, a matched pair will have nearly identical Vbe voltages, lifting Vclamp right up to the MCU/ADC supply rail, reducing the nonlinearity.

author: Zero999
author_rank: Super Contributor
timestamp: April 07, 2017, 03:44:52 pm
content: Quote from: Ian.M on April 07, 2017, 03:14:14 pmYes, I see what you mean. The diode starts to conduct slightly and clamp, as the input voltage goes near +V. This may be fine on a digital input, not for an ADC. The same issue applies to the op-amp circuit I posted previously. Fixed circuit below.Anyway, there's no point in clamping *exactly* to +V since the MCU inputs can take it and the ESD protection diodes don't start conducting until around 600mV.

author: Ian.M
author_rank: Super Contributor
timestamp: April 07, 2017, 04:10:41 pm
content: Yes, but you want to clamp as close above the rail as you can. Most MCUs with internally diode clamped pins are only rated for I/O votages +/-0.3V outside the rails for normal operation meeting all specs. That does't give you much margin for clamping rail rise and Schottky diode Vf when clampin higher current pulses.Personally I prefer *NOT* to use the last few percent of the ADC range. 100mv to 200mv off each end makes clamping *MUCH* easier and also vastly improves signal conditioning OPAMP linearity. Alternatively, design in a 4.096V (for 5V systems) or 2.56V reference (for 3.3V systems) and get rid of all the nonlinearity problems and get better accuracy and easier maths as well;.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 07, 2017, 10:31:41 pm
content: Thankyou again Ian for your continued guidance and additional clarification, much appreciated.Quote from: Ian.M on April 07, 2017, 08:45:55 amExcellent.Let's check my understanding thus far by attempting a summary: The TL431-based solution is based around using a shunt regulator built using the TL431 to generate a stable 3.3V that will be used exclusively to sink overvoltage from the MCU pins. This protection is achieved by using a Schottky diode per MCU/test line to this rail. One advantage of using shunt regulators in this way is that they handle overvoltage conditions very well. We don't intend to actually use the 3.3V produced, except as an overvoltage sink, so 2mA is sufficient to ensure we hit the 1mA minimum required. Reasonably close?Quote from: Ian.M on April 07, 2017, 08:45:55 amI've plugged in a few values into the existing schematic and updated it, attached. Hopefully I'm approaching this the right way. I wasn't sure if I should be calculating current based on a drop from 5V to 0V, perhaps 5V to 3.3V, or something else. The resistor value I have included is for the former.Quote from: Ian.M on April 07, 2017, 08:45:55 amI've aimed straight at 3.3V for now. The Vout equation just provides a ratio for R1/R2 (.322645 for 3.3V), and I've just used a 10k for R2 for now. I'm unsure of the tradeoffs between higher and low resistor values, but if I had to guess it would be an accuracy/stability versus wasted current tradeoff.Quote from: Ian.M on April 07, 2017, 08:45:55 amI should be fine as there are so many conditions in my favour in this case. Most of the time there will only be a few lines in an overvoltage condition, and they will only remain that way for seconds at a time. The environment won't be particularly hot, at least not until next December.The MOSFET that halves the voltage will be turned on for a substantial chunk of time, and while the divider MOSFET is on, there is no overvoltage condition. I can always add code such that if an overvoltage condition was indicated in previous tests, I just reduce the sample time and leave the divider on for more of the time.Quote from: Ian.M on April 07, 2017, 08:45:55 amThanks. From the look of things I won't end up needing it, but if I do, I suspect that understanding it will be relatively easy once I've fully understood and have experimented with the TL431 setup.As a bit of a side note, I've noticed that the ON Semi TL431 datasheet has quite a few examples in it, including a shunt regulator example plus a high-current variant. Even if I don't get their specific variant, it proved quite useful for understanding.It'll be good to get a TL431 into my hands so that I can experiment with it.I'm including one in my order, and likely a few precision resistors as well.

author: Ian.M
author_rank: Super Contributor
timestamp: April 07, 2017, 10:41:43 pm
content: Sounds/looks good, except you use the drop from 5V to 3.3V (nominal Vclamp) to calculate the pullup resistor for approx 2mA quiescent current shared between the TL431 and its voltage set divider. 2.5K starves the TL431. Try 1K, as the divider only takes 1/4 mA , that gives about 1 1/2 mA for the TL431.N.B. the cap wired A-K across the TL431/TLV431 ie *IMPORTANT* for the clamping transient response as the high frequency gain of both shunt regulators sucks.

author: GarthyD
author_rank: Regular Contributor
timestamp: April 08, 2017, 12:08:53 am
content: Quote from: Ian.M on April 07, 2017, 10:41:43 pmThanks. I've adjusted the R3 value. I might use slightly less resistance in the end as I suspect that my 5V input might actually end up being a fair bit less, and power efficiency isn't much of an issue on test equipment. Still, this is something I can experiment with to determine the precise value.Many thanks for all of your input and guidance thus far. If I had continued down my original path of shunting to my 3.3V power rail, there is a good chance that, due to the fairly low current in use on that rail, that I would have eventually damaged both the test equipment and the boards I was testing.

author: GarthyD
author_rank: Regular Contributor
timestamp: July 15, 2017, 08:03:50 am
content: Just a quick update: I ended up using the overvoltage protection based on Ian.M's recommendations when testing the prototype board I have recently assembled.Here is the test setup:The left two breadboards contain the test setup. The other breadboards contain the breadboard prototype, which drives the test setup. Buried at the top left of the second-to-left board is the overvoltage protection:The breadboard prototype is being used to test a partly-assembled PCB prototype:The board has been fully assembled since:I talk about that a bit more here:https://www.eevblog.com/forum/projects/general-purpose-sam4s-mcu-and-max-v-cpld-development-board/Thanks all, especially Ian.M for setting me on the right path.