Vcd Viewer (VcdView) upgrade available (now with equations) - Page 1
Forum section: electronics / general

author: trossin
author_rank: Contributor
timestamp: September 11, 2024, 10:18:14 pm
content: I just uploaded a new version of VcdView which is a Windows tool I started about 20 years ago to view Value Change Dumps from the Icarus Verilog simulator. I’ve been using it off and on since I first wrote it but recently have used it more since getting my hands on some cheap FPGA boards (Lattice and Xilinx/AMD). You can find the latest version here:https://sites.google.com/site/tedrossin/home/tools/otherI skipped the IceCube simulator and just used Icarus but did give the Vivado simulator and waveform viewer a try but found it very slow. I made my own models of the PLL and block RAM for my Alchitry Cu board (iCE40-HX8K). I made models for the PLL and block RAM for my Digilent Cmod A7 board (Atrix XC7A35T) as well and found that the Icarus simulator dumping VCD format down 5 levels was about 100x faster than the Vivado simulator on my 10 year old laptop. I just use the Vivado simulator to check my behavioral models and do my day to day work with Icarus.I found my old waveform viewer was missing some features and had some bugs that I was ignoring so I broke down and spent some time fixing/enhancing the code. I fixed some minor bugs and annoying behavior plus added analog waves and fixed point support. The biggest change is that I added the ability to create and display equations.I often used the equation feature of Debusy when I was a working stiff to help me analyze the behavior of my designs and to help track down bugs. For example, I would AND the clock with the write enable to a FIFO then use the count transition feature to count how many writes went into a FIFO and also at various points in the pipeline to track down where some data got lost.I would also use the equations to try out theories on why some logic was failing without having to rerun the simulation. For example, does the machine fail when a new command arrives the same cycle or the cycle after a DRAM command/address parity error was detected? By making an equation, the entire simulation can be checked for a particular event without clicking through the waves looking for it. Instead, the find next edge of the equation being true feature can be used to find it. You can quickly determine if your theory is a rare event which always causes a failure or a common event which only sometimes fails and may require another arming event to fail. VcdView now supports this work flow.Equations can be created using Verilog syntax plus I’ve added some built it functions to count transitions, delay signals, find the min or max plus some others that are listed on the web page and in the tool (just select add function to get a list with a short description). For example, a bus can be created from other busses and signals with embedded equations as follows:MyData = {ThoseBits[3:1],Error,~Mess & Order,2’b01}Here are some equations using built in functions to display the PWM energy of a single active low signal:BlueOnCount = $RiseEdgeCount(Clk & ~nRgb,nRgb)BlueSample = ~nRgb & $Delay(nRgb,-500)BluePwmPercent = 7'd100*$SampleAndHold( BlueOnCount[8:0] ,BlueSample)>>3'd4The PWM period is 256 cycles so the shift right by 4 is a fast divide by 16. Normally, the divide would be by 256 but I display the result in fixed point format using 4 bits of fraction to get a fractional display of the energy (10.12% instead of just 10%). This shows that equations can be created based on other equation. Note that if the lower level equations are modified, the dependent equations are updated.

author: zapta
author_rank: Super Contributor
timestamp: September 13, 2024, 12:55:54 pm
content: Very nice tool.BTW, the current trend is to develop tools that work on windows/mac/linux. I guess that there are software frameworks that allow that.