FPGA Advice wanted. - Page 1
Forum section: electronics / general

author: Dubbie
author_rank: Unknown
timestamp: July 10, 2016, 11:12:31 pm
content: Hi,First up, I'll admit that I'm wading into water a long way over my head here!I have a project that I am working on where I need to time 16 channels simultaneously to ~ 10 nS resolution. I want to store these timings as 16bit ints somewhere, then once all a timeout is reached, set a "dataready" pin so that a microcontroller can read out the data via SPI.The readout will only happen at 60 HZ so there is plenty of time for the serial transfer.I figure that a small FPGA is perfect for this application. However I have never done anything with FPGAs before. I have a bunch of experience with microcontrollers. I also have a rough idea how the process of designing for FPGAs goes.Can anyone recommend an entry level FPGA dev board that has good intro tutorials etc? I would prefer a chip that isn't BGA so I will have a decent shot of assembling a board myself.I downloaded the free Xilinx software and had a brief poke around. It looks pretty user friendly.Thanks in advance for any suggestions.Rhys.

author: uncle_bob
author_rank: Unknown
timestamp: July 10, 2016, 11:25:42 pm
content: HiIs this a one off or a production board? If it's a one off, forget about building a board yourself. There are a lot of places that will be happy to sell you an assembled board (built in the 100's) for less than what the parts would cost you (single piece).10 ns impies a 100 MHz clock. That is not a big deal in the FPGA world these days. What *is* an issue is the design software. The manufacturers will happily give you free software to do this sort of thing on their newest parts. If you go off to eBay looking for boards or parts ... that's not what you are going to find. So:Is there a budget for this gizmo? Is $100 to much, is $10 still to much? Does it have to come in under $1? Do you already have a 100 MHz clock to time things out against or does the FPGA need to generate that clock?Lots of questions !!Bob

author: Dubbie
author_rank: Unknown
timestamp: July 10, 2016, 11:30:48 pm
content: For now it is a one off part. If I ever wanted to make more, I'd get a professional to design it properlyAt this stage it is a prototype/RnD device, so budget isn't really a concern. $100 would be completely fine.Regarding making boards I often design and build my own boards for projects even though it would be far cheaper to use dev boards because in the process I have learnt a ton.I plan for this to be a learning project as much as anything, so constraints are fairly flexible.Regarding clock, I can provide the same clock that I will clock the microcrontroller from. I presume I can PLL it up to the desired frequency inside the FPGA.

author: uncle_bob
author_rank: Unknown
timestamp: July 10, 2016, 11:40:27 pm
content: HiTo do a reasonable job, you will need at least a 4 layer board. Most of what we do is in the 8 to 12 layer range. There are non-bga parts out there. They have a bunch of restrictions on them that make them less than fun to use. The lead frame really gets in the way these days. One pretty good way to go is something like:http://www.trenz-electronic.de/products/fpga-boards/trenz-electronic/te0725-artix-7.htmlThey have all the hard to do stuff taken care of already and will drop on a carrier board that you lay out.If they ever came back into stock:https://www.arrow.com/en/products/bemicromax10/arrow-development-toolsWould also work. Getting at the clock input is only possible if you use the edge connector.This guy is a bit more fun to play with out of the box:https://products.avnet.com/shop/en/ema/kits-and-tools/development-kits/3074457345628965502Getting at all the clocks and i/o is not as easy as with the 725 boards.All of these are massive overkill for what you are trying to do. That's a good thing. Projects like this tend to grow as you get into them...Bob

author: Dubbie
author_rank: Unknown
timestamp: July 10, 2016, 11:48:40 pm
content: Thanks a lot for the useful advice Bob.That first link looks very interesting.Do you imagine that I will be able to muddle through a design from scratch on that chip? My problem is that I'm still at the "Don't even know what I don't know" stage hereThanks,Rhys.

author: uncle_bob
author_rank: Unknown
timestamp: July 10, 2016, 11:54:55 pm
content: HiThe software is not impossible to get through. You will have to come up to speed with VHDL to play in the Xylinx world. Altera will still let you do schematic entry. If this is as much a learning experience as a design ... learn VHDL. It's a couple of weeks watching videos part time. Worst case, you get the demo board from Avnet and the Trenz board.One way or another you will need to beg / borrow / steal a programming dongle to get the Trenz to do it's thing. I believe the Avnet board has some sort of programmer built in.Bob

author: Dubbie
author_rank: Unknown
timestamp: July 11, 2016, 12:18:01 am
content: Well thanks for the hints Bob, I've bought one of the trenz modules and a xilinx JTAG programmer/cable.Looking forward to getting thoroughly confused.R

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 12:21:40 am
content: Quote from: Dubbie on July 11, 2016, 12:18:01 amHiGetting confused is most of the fun !!One quick hint on the 725 module:It wants 3.3V as a supply to the module. There are switchers onboard that take care of everything else. LVDS i/o is possible (and a good idea cross talk wise). If you go that way, you will need an external (to the module) 2.5V supply to run the LVDS banks. There is a 2.5V regulator on the module. It's not easy to get at.Good liuck !Bob

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 11, 2016, 04:00:32 am
content: Quote from: uncle_bob on July 10, 2016, 11:54:55 pmWhy do you say that? Xilinx software supports VHDL, Verilog, and Systemverilog.

author: Dubbie
author_rank: Unknown
timestamp: July 11, 2016, 09:53:58 am
content: I have an ice40 dev board, but I found the software much more confusing than the XilinxSent from my phone using Tapatalk

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 12:09:12 pm
content: Quote from: Sal Ammoniac on July 11, 2016, 04:00:32 amHiIf this is a start from scratch / I know none of them sort of thing - VHDL is what I'd pick. Based on what has been posted so far, it's a pretty good bet that this is indeed a start from scratch situation.Bob

author: nctnico
author_rank: Super Contributor
timestamp: July 11, 2016, 04:11:18 pm
content: Quote from: blueskull on July 11, 2016, 06:00:24 amA large CPLD might be a better fit for a project like this.However for a one off project the last thing I'd look at is the cost of the device or the development board. Concentrate on an easy solution because getting to results quickly is very rewarding.

author: sporadic
author_rank: Regular Contributor
timestamp: July 11, 2016, 04:26:26 pm
content: Anyone have feedback on the Altera and Xilinx boards from WaveShare? Seem like they'd be ideal for something like this -http://www.waveshare.com/product/fpga-tools.htmSent from my XT1094 using Tapatalk

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 11, 2016, 04:43:49 pm
content: Quote from: sporadic on July 11, 2016, 04:26:26 pmI have no experience with the WaveShare FPGA boards, but I do have several of their ARM boards and I've found them to be well-built and very good value for the money. Documentation, however, is minimal and quirky.

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 04:56:35 pm
content: Quote from: sporadic on July 11, 2016, 04:26:26 pmHiAt least from a quick look on their web site - what they have are all older parts. Most of them have dropped off of support on the latest "free" IDE's. You can of course cobble something together downloading an older IDE. That's not what I would recommend for a first project. Many of their boards are competing directly against cheap and dirty boards from China. It becomes a "how much will I pay for quality?" question at that point.Bob

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 11, 2016, 05:23:11 pm
content: Quote from: uncle_bob on July 11, 2016, 04:56:35 pmAgree. Look at Digilent--they have boards based on more recent parts and they support their boards very well.

author: nctnico
author_rank: Super Contributor
timestamp: July 11, 2016, 06:02:08 pm
content: When it comes to Xilinx ISE 14.7 versus Vivado: AFAIK ISE14.7 is mature and Vivado is still under construction. Getting the latest&greatest may not be the best choice. Besides that Xilinx has always kept the old versions of ISE available in case you need to work on a project which has been made using a certain version.

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 06:54:25 pm
content: HiIn the context of a learning project, I find it hard to recommend people learn tools that have already been declared obsolete by the vendor. If you have projects in ISE then sure, keep trucking on those projects. If you are just starting out today .... go with a tool that has a future to it. ISE has no future.Indeed both Altera and Xilinx will let you download old tool suites. You *can* do a project on a MAX 3000. You will be learning a bunch of stuff that is now going on three generations out of date. If it is absolutely necessary, sure do it. In a "I only have $10 to spend and X months of time is free" situation, go that way. If it's a skill for the future ... not so much.Bob

author: nctnico
author_rank: Super Contributor
timestamp: July 11, 2016, 07:03:40 pm
content: As much as Xilinx would want it ISE isn't going to be obsolete for the next couple of years. There is still too much not working right in Vivado.

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 07:20:23 pm
content: Quote from: nctnico on July 11, 2016, 07:03:40 pmHiI've seen this process before. As much as the new super version has issues (they always have issues) ... they do go ahead and kill the older version. I'm not in any way saying that's right. It is what happens. If you get a couple of years of overlap that's better than the way some places do it. They *have* to get rid of the cost of support on the older version. A number of people's bonus plans depend on it. That's what makes it happen.Bob

author: rstofer
author_rank: Super Contributor
timestamp: July 11, 2016, 07:34:13 pm
content: ISE vs Vivado - where to start... I have spent 12 years working with ISE and I am still struggling to figure out Vivado. Maybe I'm a slow learner. I'm slowly starting to come around...If I were going to the Internet to find similar projects or tutorials for VHDL, I'll bet there are a thousand times more projects for ISE than there are for Vivado. I would always recommend starting with ISE even knowing that there is no future.I thought I posted last night but here's a Spartan 6 board (uses ISE) that includes a USB gadget that will handle the communications to the PC. Furthermore, it comes with a bunch of sample projects that demonstrate its use:http://shop.ztex.de/product_info.php?cPath=25&products_id=87There is a small Debug board that gets the user up to speed fairly quickly:http://shop.ztex.de/product_info.php?products_id=81A more realistic board from Digilent:http://store.digilentinc.com/cmod-s6-breadboardable-spartan-6-fpga-module/It too will require ISE 14.7Digilent has implemented the DEPP (EPP Parallel Port) on this device. So, the user code on the PC treats the device just like a bi-directional parallel port. I don't want to get too far into it but there is an address register that addresses the data registers and some data registers. Set the address and then read/write the data register. It's pretty easy on the PC end because there is an SDK provided.https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/reference-manualI'm pretty sure I would try this gadget first.

author: rstofer
author_rank: Super Contributor
timestamp: July 11, 2016, 07:44:19 pm
content: Quote from: uncle_bob on July 11, 2016, 07:20:23 pmI think Xilinx is pretty up-front about the fact they no longer support ISE but what are they going to do, leave millions of projects with no support whatsoever? That's not a winning strategy.Their view is that they will leave 14.7 out there to support the devices in the field and move on to Vivado with just the slightest overlap in devices. I don't see 14.7 going away, ever...If they did kill off 14.7, how would they redefine 'field upgradeable'? I think having a copy of the old version 10.x is pretty handy as well. I still have Spartan 2 devices to program.

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 08:15:34 pm
content: Quote from: rstofer on July 11, 2016, 07:44:19 pmHiYou probably will be able to download ISE 14.7 a century from now. It still will be available and if you have a computer that will run a 100 year old OS, you will be able to fire it up. There will not be anybody to call up when you have a question or find a bug. The latest and best timing info will be in other programs (even for the old parts). That is likely OK for a project you did 100 years ago and simply want to do a small tweak on. Available is not the same as supported ....Bob

author: rstofer
author_rank: Super Contributor
timestamp: July 11, 2016, 08:38:59 pm
content: Quote from: uncle_bob on July 11, 2016, 08:15:34 pmTrue enough. The thing is, Xilinx has no intention of supporting legacy devices with Vivado. Even chips as new as the Spartan 6 aren't supported in Vivado. Nor do I expect them to ever incorporate the legacy devices. They have a plan for moving forward and it works for me. I can use the old software to support my older projects and I can use the new software with my newer projects. But I would still recommend starting with a legacy device and the legacy softward if tutorials were of any concern.If not, the Arty Artix 7 board is pretty nice as is the Digilent Basys 3. In fact, the Artix would handle this job pretty well:http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/Mount a little mezzanine board on top for connecting the inputs and the rest is ready to go. This board works well with Vivado.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 11, 2016, 09:04:44 pm
content: I started with Vivado and find ISE strange and puzzling. It seems to me that Vivado is a big improvement in usability over the earlier tools. This is just my perspective, however, coming from someone who started with the new tool and never really put much time into learning the old tools.From a business perspective, Xilinx has to move forward with one tool and stop putting any money into the other. Since they spent $200M developing Vivado (and it's much better than ISE IMO), that's what they should concentrate on. Leave the last version of ISE available indefinitely to support those still using parts not supported by Vivado, but everyone else should move on.

author: nctnico
author_rank: Super Contributor
timestamp: July 11, 2016, 09:09:26 pm
content: Quote from: uncle_bob on July 11, 2016, 08:15:34 pmIt is the same as every new version of Windows: wait until the first service pack is released before trying and until the second service pack is released before using it for anything serious. ISE in it's current form has been around for over a decade and AFAIK the more recent versions are mostly introduced to support new devices. Sure at some point you'll want to move to Vivado but I'd rather wait for a couple of years. If I run into a problem with Xilinx ISE there are tons of answers in various fora and applications notes so no need to spend days to figure out whether you are doing something wrong or it is a missing feature/bug.

author: Dubbie
author_rank: Unknown
timestamp: July 11, 2016, 09:16:26 pm
content: Thanks for all the input. I think I will continue with vivado. In the past I've always found it worthwhile to jump on board the train of the future, even if the first couple of years have a few wobbly bits and missing features!Sent from my phone using Tapatalk

author: Kilrah
author_rank: Unknown
timestamp: July 11, 2016, 09:27:17 pm
content: Quote from: rstofer on July 11, 2016, 08:38:59 pmI'm starting right now with a Zynq on Vivado, and given the complexity of these tools I'd find it to be a waste of time to spend days/months getting used to an obsolete tool, when the new one has been around for >3 years already...If there was a huge price difference that made the old chips that are not supported in Vivado that much more attractive why not, but they understood well enough that they had to avoid that and facilitate access to newer devices if they want to sell them AND get people to move to the new tools.

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 09:42:58 pm
content: Quote from: rstofer on July 11, 2016, 08:38:59 pmHiYup, The Trenz 725 is a Artix-7 board that can easily mount on an application specific board. That's what the OP went with. It's a pretty rational little chip with enough cool features to spend lots of time playing with.Bob

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 09:59:13 pm
content: Quote from: blueskull on July 11, 2016, 09:56:09 pmHiBack up and re-read it. He wants 10 nanosecond samples. The data comes out at a 60 Hz rate. That isn't going to happen with a PSoC.Bob

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 10:17:59 pm
content: Quote from: blueskull on July 11, 2016, 10:05:31 pmHiYou need 16 counters that *async* clock at 100 MHz ... not going to happen on a PSoC. All the data and "clocks" are re-done against the CPU clock. That makes it a really rotten thing for precision timing.Bob

author: rstofer
author_rank: Super Contributor
timestamp: July 11, 2016, 10:27:44 pm
content: Quote from: uncle_bob on July 11, 2016, 09:42:58 pmAnd a JTAG programmer? I don't see an onboard USB->JTAG gadget so I suspect there needs to be something else at that JB1 header.I like the 'stamp' format for boards. Lots and lots of IO pins.

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 11:10:42 pm
content: Quote from: rstofer on July 11, 2016, 10:27:44 pmHiHe bought the programmer before we even got to talking about that part of it.Bob

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 11:23:12 pm
content: Quote from: blueskull on July 11, 2016, 10:27:28 pmHiFrom the PSoC 4200 data sheet:Maximum clock frequency anywhere: 48 MHz. That's < half of the 100 MHz he needs for 10 nsMax macrocells per channel 8: If he did have 100 MHz, he needs more like 20 to 27 per channel, more likely 2X that if he wants it buffered.It is a fun little part. It's not a universal solution to all problems ....Bob

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 11, 2016, 11:46:40 pm
content: Quote from: uncle_bob on July 11, 2016, 12:09:12 pmWhy VHDL? Any particular reason to choose it over Verilog or SystemVerilog?

author: Dubbie
author_rank: Unknown
timestamp: July 11, 2016, 11:48:40 pm
content: Evb, I have all that info clearly defined. There are a couple of other little wrinkles such as 3bits of info encoded into the start pulse that I am going to have to time as well. As I mentioned, I am very new to programmable logic, so I expect that even if I fail at this project, I will learn a lot.Sent from my phone using Tapatalk

author: uncle_bob
author_rank: Unknown
timestamp: July 11, 2016, 11:51:17 pm
content: Quote from: Sal Ammoniac on July 11, 2016, 11:46:40 pmHiPretty much everybody I know uses VHDL over the Verilog empire.Bob

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 12, 2016, 12:00:07 am
content: Quote from: uncle_bob on July 11, 2016, 11:51:17 pmThat's a quite personal (and very valid) reason to choose VHDL. Having others around you who are familiar with a language is certainly a big help, especially for beginners.Let's assume an FPGA beginner wants to learn Verilog or VHDL, but doesn't have anyone around who knows either one. Which one would you recommend he choose? Why?

author: nctnico
author_rank: Super Contributor
timestamp: July 12, 2016, 12:13:20 am
content: Quote from: Sal Ammoniac on July 12, 2016, 12:00:07 amI'd go for VHDL because it is much more a programming language and thus offers many powerful features to do a lot with only a few lines of code (creating designs which can be changed with just a few parameters is one of them). Also strong typing helps to avoid errors. Ofcourse an FPGA developer should know what HDL is going to look like in logic after the synthesizer is done with it but that doesn't mean a HDL developer should be describing the logic itself.Having other people around who know 'X' doesn't sound like a good idea because you'll also inherit their bad habbits. When I started working with FPGAs the rest of the team used schematic entry and never heard of timing constraints. Even back then I made reconfigurable designs so when a design needed to scale up from 16 to 24 and later to 96 channels all I needed to change was a number. That was just beyond imagination with schematic entry.

author: uncle_bob
author_rank: Unknown
timestamp: July 12, 2016, 12:24:25 am
content: Quote from: Sal Ammoniac on July 12, 2016, 12:00:07 amHiI would go for VHDL simply because it's what he is (in my limited sample) most likely to run into in the future. I realize this is a Ford / Chevy discussion that can go on for a few hundred years. To fully answer the question, somebody would have to be fully proficient in both and regularly use both for major projects on the same hardware. People are rarely that complex. They pick one and go with it. It becomes the default answer to the question ... In most cases that I've seen, they don't make the choice. They walk in and the place uses one or the other. They go with the "default language" or find work elsewhere. After a bit they become "centric" in one or the other and that tends to dictate where they go and what they do. Does it work that way 100% of the time? Of course not. It works that way in more cases than not. People do transition from one to the other. When they do, the "old one" does not get used. They can compare one "as it was on that project back then" with whatever they are using now. That tends to be a skewed comparison. Older normally = simpler.Bob

author: rstofer
author_rank: Super Contributor
timestamp: July 12, 2016, 01:22:16 am
content: As Bob said, it's kind of a personal decision. When I first started, the tutorials were written in VHDL and I have been using it ever since. I just don't 'get' Verilog. I have tried a couple of times to create a design with Verilog, gave up and returned to what I know. That's not a criticism of Verilog, a whole lot of people use it. Clearly, it works. And, truthfully, I didn't really give it a chance. It's not like VHDL flowed from my mind to the keyboard the first day either.There are a few 'standard' things to know: How to create a MUX, how to create a Decoder and, most important, how to create a State Machine. There are a couple of lesser used things like the Priority Encoder but, basically, there are only a handful of constructs. There are a number of tutorials on the Internet and I think "RTL Hardware Design Using VHDL" (Pong P. Chu) may turn out to be the best book I have on the subject. But it's too expensive! Maybe some of these:http://www.alibris.com/booksearch?keyword=vhdlSo, sit down and spend the time to create small sample projects creating these blocks and really understand how they work. Make sure there are default values for all the output signals in the state machines and everything will start to flow.

author: Dubbie
author_rank: Unknown
timestamp: July 12, 2016, 02:00:31 am
content: I am measuring the timing of externally generated pulses. There is a start pulse defined by its length, then a second much shorter pulse anything up to about 8ms later.It is highly likely that several channels could have identical timing, so there is no time to do things seriallySent from my phone using Tapatalk

author: Chris Mr
author_rank: Regular Contributor
timestamp: July 12, 2016, 12:01:34 pm
content: For what it's worth I have been using iCE40 for about three years now.I use ISE to synthesise and simulate and then iCECube2 to get it on the chip.I can thoroughly recommend "Advanced Digital Design with the Verilog HDL" book but it's expensive (£150). There are three words in the preface...Simplify, Clarify and VerifyThat pretty much sums it up for me - so only £50 per wordMy big lesson was to only put on the FPGA that which _has_ to be there; if a micro can do it, put it in the micro. So I simplified the FPGA, clarified that it would still do the job and then verified it.One really nice feature of the iCE40 is that there is an SPI interface which is used to write the 'image' to the device (same port is used to program the non-volatile on-board memory when you want to finalise the design), and when you are testing that can come from a local micro. Then, when the FPGA is running, those SPI pins can be used to interface to your design (pins programmed to be SPI of the FPGA design) via your local micro. For quite a lot of things it's like having an FPGA with a micro on board. One thing I really like is using the SPI as an I2C "global" interface. The LE line becomes SPI / I2C select so when low it's an SPI port, high I2C. The SPI clock becomes SCL and data send is MOSI, the data return being MISO. You can then connect a load of I2C devices to different pins on the FPGA (to save PCB layout headaches) and just AND all the SDA pins when LE is highThe other thing is, I have been clocking the iCE40 with a CDCE925 which will go up to 230MHz (the CDCE that is) and whilst I have only been running it at a tad under 200MHz it is completely solid. That's after temperature cycling and so on. That allows you to use an ARM with an SPI running at 42Mb/s which is pretty cool.Needless to say I am a fan of iCE40

author: sporadic
author_rank: Regular Contributor
timestamp: July 12, 2016, 04:15:21 pm
content: Quote from: Chris Mr on July 12, 2016, 12:01:34 pmI picked up an iCEstick two years ago learn FPGAs with and have yet to do anything with it. Are there any good guides or tutorials for working with iCECube2 you could recommend? I've found lots of good resources on VHDL and Verilog, as well as some decent tutorials for ISE and Quartus, but not so much for iCECube2.

author: sporadic
author_rank: Regular Contributor
timestamp: July 12, 2016, 04:58:30 pm
content: Quote from: blueskull on July 12, 2016, 04:48:34 pmHaha, there's a lot of truth in that! That one's going in my quote book

author: Chris Mr
author_rank: Regular Contributor
timestamp: July 12, 2016, 05:12:31 pm
content: If you think of the iCEcube as a means to get the code formatted for the chip then all you really need is to do one project and that'll be it.Essentially:Once you have your synthesised code open up iCEcube and click on "new project". It'll make a directory for it once you point it at wherever you want it to be (I usually put everything in a folder (Ver1 etc) and then the code is one folder higher up but its up to you.Pick the device, package etc in the menu for new project and do "next"Now pick your top level file (verilog in my case) and click the ">>" button so the file is added to the right hand side then click "finish"Then you set the synthesiser tool by right clicking on "Synthesis tool" and set is to LSE.Now you're good to go. Click "Run Synthesis" and given that your code has already been tested it'll synthesise ok.There is then only one more stage - you have to tell it which connection (from your design) goes to which pin which is in the "pin constraints editor".Do that and then run "Run P&R" and it'll do the rest.You get a .bin file in the directory under your original folder "\sbt\outputs\bitmap\<filename.bin>" which is just a binary so I wrote a simple "bintoarray.exe" that converts it into a 'C' array so your micro can include it in its code - and then send it to the FPGA (so you don't need any tools).I thought that was going to be a couple of lines - a true optimist!If you use ISE (xilinx tools which I am happy to do because I used lots of their parts in the past) to do the checking and synthesis - so your code has been checked first - there isn't much in the way between that and running it.You are right though, it could do with a video

author: Dubbie
author_rank: Unknown
timestamp: July 12, 2016, 05:38:41 pm
content: Yeah, that last bit is where I came unstuck with the ice40! I couldn't figure out how to get the design uploaded. I thought it was pretty bad that the dev hoard doesn't come with a single working example. Anyway, I will start again with a more "normal" chip and VHDL in Vivado, and circle back later to the ice. I still think it will be the best for the job ultimately.Sent from my phone using Tapatalk

author: Dubbie
author_rank: Unknown
timestamp: July 13, 2016, 01:46:38 am
content: Thats very generous of you Blueskull. Thanks!

author: Dubbie
author_rank: Unknown
timestamp: July 13, 2016, 03:08:23 am
content: I have the hx8k guess I'll figure out somehow what the led pins areSent from my phone using Tapatalk

author: joeqsmith
author_rank: Super Contributor
timestamp: July 13, 2016, 03:13:33 am
content: Quote from: rstofer on July 11, 2016, 08:38:59 pmI just bought this little eval board a few weeks ago and am setting up the software while I type. I wanted to play with Vivado but the tool costs for my hobby use are out. I had tried loading up the full tools when it first came out and ran various simulations. I have used Foundation, ISE, MaxPLus and Quartus. This tool set looked pretty nice the little I played with it, but no hardware to target. This board comes with a full license but as I understand targets only this device. No idea yet if there are other restrictions. Read most of what I could find on-line about the board. For $100, hard to go wrong if you just want to get your feet wet like me.For home use, the part is way more powerful than anything I have played with. Should be able to come up with something fun to do with it.

author: joeqsmith
author_rank: Super Contributor
timestamp: July 13, 2016, 04:36:21 am
content: About 48 minutes to install. Fairly painless. Was sitting at the installing drivers part for several minutes before I realized they had popped up a screen and it was behind the main install menu.

author: Chris Mr
author_rank: Regular Contributor
timestamp: July 13, 2016, 06:22:22 am
content: Nice video BlueSkullThe LSE is available by right clicking on "Synthesis Tool" in the left hand pane - you get the option to change to the lattice one which is free and not time limited.Hope that helps

author: Kilrah
author_rank: Unknown
timestamp: July 13, 2016, 06:58:36 am
content: I haz variable-speed blinkenlightsGot the board a few months ago, managed to build/load the sample design and change a few things on the software side but for whatever reason had zero success trying to do anything on the hardware side. Then got too busy with other things, seems starting fresh and from approximately 0 (make a single connection between a pushbutton and a LED...) then adding more along works much better this time.Need to try and write a few custom modules more advanced than a mux now... I've done some VHDL during my studies but that was about 12 years ago, and while I remember doing good back then it seems that now there's some kind of "mental resistance" that just doesn't want to let it sink in again, constantly have to refer to docs/searches for nearly every expression

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 13, 2016, 04:16:35 pm
content: Quote from: joeqsmith on July 13, 2016, 03:13:33 amThe Webpack version of Vivado is free.

author: mark03
author_rank: Frequent Contributor
timestamp: July 13, 2016, 07:16:49 pm
content: Quote from: Sal Ammoniac on July 13, 2016, 04:16:35 pmDoes this also include the logic analyzer now too? I noticed Xilinx are pitching "HLS Webpack" but it's hard to find concrete info on their web site.

author: whollender
author_rank: Regular Contributor
timestamp: July 13, 2016, 07:46:05 pm
content: Quote from: mark03 on July 13, 2016, 07:16:49 pmIt looks like both Vivado and ISE webpack editions should include chipscope (do they not call it that anymore in Vivado?), but I haven't tried it myself:http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.htmlhttp://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html

author: rstofer
author_rank: Super Contributor
timestamp: July 13, 2016, 11:41:57 pm
content: Quote from: mark03 on July 13, 2016, 07:16:49 pmI don't understand Vivado licensing... Apparently, if you buy a preferred board (Arty or Basys3), you get a certificate that allows you to get a fully licensed version of Vivado including all the IP. The simulator works well but I don't prefer to use it. What they do have is a logic probe arrangement whereby I can define signals I want to watch and it displays them on the screen as traces. There's more to it than that but basically, it is debugging in hardware as opposed to simulating. A built-in logic analyzer, if you will!What I don't know is what level of access you get without the certificate.VVVVVVVVVVVVVVVVVVVWhat I really wanted to mention is the new Digilent Artix 7 'stick'. This is going to be a sweet deal because it has 512 KB of SRAM along with the USB programming port. Just announced today!http://store.digilentinc.com/cmod-a7-breadboardable-artix-7-fpga-module/I want the 35 chip vs the 15 chip because more cells is better - $89. Its on order...

author: neil555
author_rank: Contributor
timestamp: July 14, 2016, 12:07:32 am
content: If your new to FPGA i'd really recommend Altera as Quartus is much easier to use than the Xilinx software (not sure what they call theirs now but it used to be called Webpack)

author: rstofer
author_rank: Super Contributor
timestamp: July 14, 2016, 12:46:48 am
content: Quote from: neil555 on July 14, 2016, 12:07:32 amI've been using Xilinx parts for about 12 years - no worries about the toolchain except the learning curve transitioning to Vivado The new constraints file is baffling beyond belief! I actually understood the .ucf file but would they leave it alone? No! They just had to tickle it (inside joke!).I have an Altera board and, at one time, I was using Quartus. Then I read the EULA! They reserved the right to cancel the license at any time in the future for any reason whatsoever. Or no reason at all! So, I have the board, I have the project and no right to use the toolchain!I had been through the license cancellation debacle with UCSD Pascal so I decided to just get away from Altera. I understand, but don't know for a fact, that they changed the terms of the EULA. But after 12 years, who cares?The tools are doing complex kinds of things. It is reasonable that they would be pretty complex themselves. None of the complexity matters as long as the user doesn't need to know about it. At least in early times.

author: hamster_nz
author_rank: Super Contributor
timestamp: July 14, 2016, 12:52:38 am
content: Quote from: rstofer on July 13, 2016, 11:41:57 pmThe licenses *used* to be useful, where without a license you didn't get the Virtual Logic Analyser, and you couldn't use the High Level Synthesis tool. It may still be useful if you are forced to run older Vivado Webpack installations for some reason, but for a new installation I wouldn't even look at it.With the Vivado HL Webpack you pretty much everything for all low end parts (e.g. Artix and Zynq 7010/7020, and a few smaller Kintex parts). The only thing you are missing out on is the DSP System Generator tools.Seehttp://www.xilinx.com/products/design-tools/vivado/vivado-webpack.htmlfor more details.It seems to me to be an attempt to allow engineers to experience and hopefully to drive the adoption of the HLS tools.

author: Dubbie
author_rank: Unknown
timestamp: July 14, 2016, 01:21:38 am
content: Blueskull, Just want to say thanks again for the great tutorial.I got the board up and running.I think between this board and the Xilinx that I've got coming, I should be covered!Thanks.R

author: Kilrah
author_rank: Unknown
timestamp: July 14, 2016, 07:20:33 am
content: Quote from: rstofer on July 13, 2016, 11:41:57 pm+1, just got the email and thought it would have been a perfect fit for this thread

author: tggzzz
author_rank: Super Contributor
timestamp: July 14, 2016, 07:32:17 am
content: Quote from: Kilrah on July 14, 2016, 07:20:33 amLook at the schematic, look at the DIP connectors and the distribution of GND pins, look at the Artix edge rates and drive capabilities, and consider whether signal integrity might be an issue in a design.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: July 15, 2016, 02:57:00 am
content: Quote from: tggzzz on July 14, 2016, 07:32:17 amAnything designed to be used on a solderless breadboard probably doesn't have signal integrity as a high priority anyway.

author: tggzzz
author_rank: Super Contributor
timestamp: July 15, 2016, 07:01:05 am
content: Quote from: Sal Ammoniac on July 15, 2016, 02:57:00 amThe thought had crossed my mind, but anybody using one of those for anything deserves whatever emerges!

author: rstofer
author_rank: Super Contributor
timestamp: July 15, 2016, 01:34:32 pm
content: OP, your project sounds a lot like a logic analyzer except you don't store the waveform, rather you just measure it. We never talked about the waveform or how to trigger the counter. Does one channel start the process for all the others or does each channel start itself? No matter, it's just a detail.Here is a site with a very nice 32 channel logic analyzer that works at 100 MHz but is also capable of recording 16 channels at 200 MHz (5 nS sample). I designed a little level shifter for the project and it runs quite well on an old Spartan 3 Starter Board.http://www.sump.org/projects/analyzer/I thought you might be able to get some hints from a project that is conceptually similar to what you are attempting.The fact that you want 10 nS resolution doesn't say much about the frequencies involved. If the signals are very high frequency, you very well could have problems with a breadboard. There's a ton of stray capacitance that will tend to smear the edges regardless of the frequency of the signal itself. You may decide at some point to build a carrier PCB. Or, maybe the manufacturer has a carrier board.Still, there's a lot of coding to do before capacitance becomes a problem.

author: Dubbie
author_rank: Unknown
timestamp: July 17, 2016, 06:50:16 am
content: Thanks for the hint rstofer. I will be sure to check it out.Sent from my phone using Tapatalk