So... I got a CLPD today... and it was Easy to use? - Page 1
Forum section: electronics / general

author: CM800
author_rank: Frequent Contributor
timestamp: January 21, 2016, 11:27:01 pm
content: I just got my CLPD (Altera MAX II) this morning, a cheap £8 china pack with a USB-Blaster.Took it home and installed the software... plugged it all in and drew up a 4 bit counter in the schematic editor.Worked first time, I'm shocked at how easy it is and I'm irritated at myself for not trying this out earlier.It seems to work practically seamless, as easy... (easier?) then an Arduino even.I've always been under the impression it must be quite hard getting started with the complex tools etc. Seems I was wrong.What are everyone else' thoughts on CLPDs. I think there needs to be a bit more promotion on the hobbiest side to show they arn't actually that complex or hard to work with at a basic level.Planning to step up to the next and try Serial comms now...(any good tutorials or guides out there?)

author: free_electron
author_rank: Super Contributor
timestamp: January 22, 2016, 12:05:40 am
content: The Altera software is just really really good. That's all. It is easy to draw a schematic , compile and download.CPLD and FPGA is nothing to be afraid of. They are just a massive drawer filled with 74xx chips ... ( actually massive drawers with LUTS (look up tables : in essence a AND/OR matrix) and flipflops )all you do is specify how to connect them , just like you would do with real chips. Altera gives you a library with almost and 74xx series imaginable as well as a massive list of other functions.If you think schematic is powerful : wait until you dig your heels into synthesis languages such as Verilog-2005. You will be writing a logic system faster than you can draw it in a schematic.Code:module counter(input clk,clear,load,direction,enable,input [3:0] data_in,output [3:0] count_out)always @posedge(clk) beginif(enable) beginif (direction) count_out <= count_out +1;else count_out <= count_out -1;end;else beginif (load) count_out <= data_in;end;if (clear) count_out <=0;endmoduleendmoduleThis is a 4 bit up/down parallel loadable ,resettable counter ( kinda like a 74193). For ease of following, all signals are active high.simplified, here is what happens :Whenever there is a rising edge on CLK ( posedge(clk) this lump of code fires.First it will check the 'enable' pin.If enable is high it will check the Direction pin and, depneding on its state , count up or down.If enable is low, it will check the load pin. if that one is high it will perform a parallel load.As a last rule it will check the CLEAR pin. if that one is high it will reset the counter to zero ( irrespective of what previous instructions decided to do. The statement closest to the 'endmodule' that evaluates is what is executed. This is inheritent in both Verilog and VHDL standards.now, want to make this a 32 bit counter ? ( with 74193 you will need 8 of them plus some glue logic ) simple change the definition of the data_in and count_outinput [31:0] data_in,output [31:0] count_out

author: trevwhite
author_rank: Frequent Contributor
timestamp: January 22, 2016, 12:11:44 am
content: Interested to hear more of your developments with this. Sounds pretty good.

author: bingo600
author_rank: Super Contributor
timestamp: January 22, 2016, 07:27:51 am
content: I followed this little course (and used a MAXII CPLD)http://www.pyroelectro.com/edu/fpga/introduction/http://www.pyroelectro.com/forums/viewforum.php?f=26Gave me a nice intro to Quartus , my uploaded assignments are for a MAXIIRemember to get Quartus 13 SP1 , not higher version (CPLD has been removed in the latest)/Bingo

author: CM800
author_rank: Frequent Contributor
timestamp: January 22, 2016, 08:10:07 am
content: Quote from: bingo600 on January 22, 2016, 07:27:51 amThat's not right. I've got Quartus 15.1 Lite, it does have CLPDs in it... hence I'm able to program themThanks for the tutorial links.Kind of annoying how little material is out there considering the price and availability of the boards.(sure it's still more then other chips... but..)Quote from: free_electron on January 22, 2016, 12:05:40 amNow that is of interest... do you know any good tutorials for this? While getting everything 'working' was fairly easy, the tutorials and guides are really lacking. Especially for UART / Serial / SPI.

author: AndyC_772
author_rank: Super Contributor
timestamp: January 22, 2016, 08:36:21 am
content: The lack of tutorials is probably because there's a lot more necessary material that's specific to CPLDs and FPGAs, and most people learning to program those devices already know everything they need to know about those things.Here's a few tips to begin:- by all means play with schematic entry to ensure your physical hardware is working OK, but then stop.- Do make the effort to learn VHDL or Verilog. It doesn't really matter which you choose, but either will very quickly allow you to generate much more complex designs than schematic entry will, with much less effort and a greatly reduced chance of bugs.- For now, if you possibly can, make sure your designs have exactly one clock, and make sure all your logic is synchronised to it. Combinatorial logic will cause you headaches, and reliably transferring signals from one clock domain to another is a whole topic in itself.

author: miguelvp
author_rank: Super Contributor
timestamp: January 22, 2016, 08:42:04 am
content: Not a lot of lack of training from Altera's site:https://www.altera.com/support/training/overview.htmlI did like their previous website better, they actually separated the courses between FPGAs and CPLDs but since they redid the website I'm a bit lost where the free courses are all at.Here is another link with tutorials.https://www.altera.com/support/training/university/materials-tutorials.html

author: tszaboo
author_rank: Super Contributor
timestamp: January 22, 2016, 11:03:58 am
content: Quote from: free_electron on January 22, 2016, 12:05:40 amI think CPLDs still fall short. You want this to be a 33 bit counter? Well sure, buy a bigger part because you run out of macrocells. I think even the manufactures know this, because the amount of CPLD advertisement and examples they give us is almost nothing.I never see the necessity to use a CPLD in any of my projects. I'm actually looking for ways to use it, but it is never justifiable cost or effort wise. Not even on a 250 EUR+ 1000 component board. It had a quad NAND gate and a single XOR on two sides, and half a dozen transistors making rudimentary RTL.

author: AndyC_772
author_rank: Super Contributor
timestamp: January 22, 2016, 11:38:06 am
content: Last time I used one it was to boot a CPU, which had a multiplexed address/data bus, from a Flash device. That, plus some voltage level shifting, clock dividing, and a few miscellaneous bits of glue logic, was a perfect fit for a CPLD - and, of course, it couldn't possibly be done by a device that needed to be configured by the main CPU first.

author: spudboy488
author_rank: Regular Contributor
timestamp: January 22, 2016, 12:37:43 pm
content: Quote from: TCWilliamson on January 22, 2016, 08:10:07 amThe MAX3000 series was dropped after Quartus 13 SP1 which is my series of choice.

author: andre_teprom
author_rank: Regular Contributor
timestamp: January 23, 2016, 12:52:01 am
content: Quote from: NANDBlog on January 22, 2016, 11:03:58 amI also never had the real need to add a CPLD in any of my projects, the nearest concept I handled it was hardware programming with the use of a uC embeeded with PSoC technology, in analog and digital blocks. In a way, as the need for performance/hardware resources grew, at that time was launched in the market a new model of uC having greater capacity, thus supplying a niche that could then be refilled by an FPGA/CPLD solution.It is undeniable that the development of a firmware programming-based solution is much more agile than based on HDL, however this is true just in projects for applications which requires general processing without higher speed requirements, on which a HDL-based solution would be mandatory.Anyway, I believe the FPGA's are still attractive with the ease of embedding soft cores.

author: CM800
author_rank: Frequent Contributor
timestamp: January 24, 2016, 01:25:24 am
content: Now I'm having trouble... just trying to get familier with VHDL and write a simple quadrature decoding program, part of that is to cascade 3 D-FlipFlops...I have found some Varilog code for this, but I'm trying to do this in VHDL.Code:module quad(clk, quadA, quadB, count);input clk, quadA, quadB;output [7:0] count;reg [2:0] quadA_delayed, quadB_delayed;always @(posedge clk) quadA_delayed <= {quadA_delayed[1:0], quadA};always @(posedge clk) quadB_delayed <= {quadB_delayed[1:0], quadB};wire count_enable = quadA_delayed ^ quadA_delayed ^ quadB_delayed ^ quadB_delayed;wire count_direction = quadA_delayed ^ quadB_delayed;reg [7:0] count;always @(posedge clk)beginif(count_enable)beginif(count_direction) count<=count+1; else count<=count-1;endendendmoduleHere is what I have done so far:Code:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;-------------- COMPONENTS --------------------------D-Type-Flip-Flop------------entity dff isport(data_in: in std_logic;clock:in std_logic;data_out: out std_logic);end dff;architecture behv of dff isbeginprocess (data_in, clock)beginif(clock='1' and clock'event) thendata_out <= datain;end if;end process;end behv;------------D-Type-Flip-Flop------------------------------MAIN------------------entity quaddecoder isport(IN_A: in std_logic;IN_B: in std_logic;OUT_Q: out std_logic);end quaddecoder;architecture struct of quaddecoder iscomponent dff isport(data_in: in std_logic;clock:in std_logic;data_out: out std_logic);end component;beginend struct;Surely there is a simpler way to do all this.Is it just me or are these Hardware Defined Languages disgustingly wordy?makes Visual Basic feel like C....

author: nctnico
author_rank: Super Contributor
timestamp: January 24, 2016, 01:33:50 am
content: A d-flipflop in vhdl (I skipped the process/end process stuff):Code:if rising_edge(clk) thensignal_out <= signal_in;for i in 1 to shift_reg'length-1 generateshift_reg[i-1]<=shift_reg;end generate;end if;In other words: you don't create flip flops but you simply tell it to do stuff when a clock edge comes along.I recommend getting a book on VHDL and try to use VHDL as a programming language to maximise productivity and minimise the amount you need to write. Let the VHDL synthesizer deal with how things look in hardware; it is very good at it!

author: andre_teprom
author_rank: Regular Contributor
timestamp: January 24, 2016, 02:57:13 am
content: In addition, you should have a look on guidelines about best practices in programming. For instance, your codding style with several instances of the "always @(posedge clk)" process blocks turns the program somewhat confusing; try bunch all them within a single group. Moreover, the syntax you´re using is outdated; As nctnico pointed with he sample routine above, it was replaced by newest compilers versions by "rising_edge(clk)".

author: chris_leyson
author_rank: Super Contributor
timestamp: January 24, 2016, 09:30:22 am
content: It's nice to program in HDL be it Verilog or VHDL. I can't do Verilog I much prefer VHDL, can't get my head around the Verilog syntax.It doesn't matter, Verilog or VHDL, Altera or Xilinx, at least you are learning logic, which is more than the clowns at Microchip can do, they are still putting buggy peripherals on their silicon. "The Designer's Guide to VHDL" by Peter J Ashenden is the definitive book for VHDL and Ken Chapman's KCPSM3 is probably the best 8-bit soft core processor, you can learn a lot from that.When describing a logic function in VHDL forget all that you learnt from microprocessor programming, HDL is not sequential logic it's parallel, it all happens on a clock edge. Syntactally it might look like a sequential programming language but it isn't. VHDL is also good for logic analysis as well as synthesis and it's a strongly typed language. You can descibe logic as a net list, KCPSM3 for example, as register transfer logic or a behavioural model and let the synthesis tools turn it into RTL.Register any incoming signals, in other words clock them into flip flops otherwise your hardware could become metastable, avoid using different clocks, metastabillity issues again and don't use variables. Think parallel not serial, state diagrams not flow charts.

author: chris_leyson
author_rank: Super Contributor
timestamp: January 24, 2016, 09:58:25 am
content: Sorry, forgot to post this link, a nice bit of code using a state table, thanks to Oleg Mazurovhttps://www.circuitsathome.com/mcu/reading-rotary-encoder-on-arduino/comment-page-1#comments

author: CM800
author_rank: Frequent Contributor
timestamp: January 24, 2016, 10:01:24 am
content: Quote from: andre_teprom on January 24, 2016, 02:57:13 amThat was not my code, I'm trying to learn VHDL not Verilog, that was some code I removed from 'fpga4fun.com' regarding Quadrature decoding.Quote from: chris_leyson on January 24, 2016, 09:30:22 amI am planning on ordering that book soon, it looks like a good one to reference.I'm already aware of the thought pattern you must put into place at how your describing hardware not writing software. It's the syntax and so on that actually gives me problems.I've got two projects I'm planning, one will be to read an encoder signal to my computer through UART or SPI, the next one will be to control a stepper motor's velocity with those same protocols, then possibly merging them together for a closed loop controller.

author: bingo600
author_rank: Super Contributor
timestamp: January 24, 2016, 12:13:46 pm
content: While waiting for the booksHere's a free one.http://freerangefactory.org/pdf/free_range_vhdl.pdfwww.gstitt.ece.ufl.edu/courses/eel4712/labs/free_range_vhdl.pdf

author: nctnico
author_rank: Super Contributor
timestamp: January 24, 2016, 12:28:29 pm
content: Quote from: TCWilliamson on January 24, 2016, 10:01:24 amThe key to writing clever VHDL is not to describe hardware. Just like in software you are describing a function. The only difference is that the execution is parallel instead of sequential. And do use variables and functions and all the other goodies VHDL offers. Variables for example are perfectly usefull as constants or to combine several signals into and then use the variable as part of other equations. They can sure help to make a long complex equation more readable. I often need only 3 or 4 lines where others need 20 to 30 lines to do the same. As a bonus my code is often more flexible as well (future extensions).

author: andre_teprom
author_rank: Regular Contributor
timestamp: January 24, 2016, 01:06:08 pm
content: Quote from: chris_leyson on January 24, 2016, 09:30:22 amI also thought exactly the same like you, but today my wish is not to return anymore to VHDL due to its more formal structure, which makes writing simple functions somewhat laborious. Today, I consider much more attractive VERILOG , due to its sympathetic(intuitive) syntax, but mainly to virtually offers same features.

author: CM800
author_rank: Frequent Contributor
timestamp: January 24, 2016, 01:27:31 pm
content: I'm surprised there aren't more people writing their own HDL languages that are less wordy (more symbols etc. such as { } andto replace some of the words you keep having to type out.then just changing it over to VHDL or whatnot once done.It seems rather inefficiently wordy.

author: andre_teprom
author_rank: Regular Contributor
timestamp: January 24, 2016, 03:41:33 pm
content: Not sure if I caught exactly your concern, but I don't see any issue in writing a code in a structured fashion ( such as a C-like syntax ) avoiding as much as possible to spread concurrent processes along different parts of the code.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 24, 2016, 03:52:51 pm
content: CPLDs are sometimes the right choice for simple applications.Cheaper, better availability of non-BGA lower pin-counts (e.g. qfp44), single supply, instant-on.

author: lem_ix
author_rank: Regular Contributor
timestamp: January 24, 2016, 04:08:34 pm
content: I'd skip Ashenden and go with Pong P. Chu RTL hardware design, a much more pleasant read.

author: nctnico
author_rank: Super Contributor
timestamp: January 24, 2016, 07:27:35 pm
content: Quote from: andre_teprom on January 24, 2016, 01:06:08 pmIt depends greatly on which Verilog you mean. VHDL has way more features like records (structs) for example and other high level language features than the regular Verilog. The strong typing in VHDL also prevents making errors. AFAIK System Verilog tries to close that gap.

author: miguelvp
author_rank: Super Contributor
timestamp: January 24, 2016, 09:12:02 pm
content: Some links, not really CPLD but HDL is HDL so they will help.1st of course Hamster_nz's pagehttp://hamsterworks.co.nz/mediawiki/index.php/Main_PageLook at his FPGA courses and VHDL links, I think all his projects are on VHDL with a few exceptions.Then there is:http://www.fpga4fun.com/index.htmlI think this is mostly Verilog but there is a VHDL tips link.And of course there is:http://opencores.org/Other links:http://www.emb4fun.de/fpga.htmlAnd if you want a beefier CPLD you could probably step up to a MAX 10 board, it's so big that it's pretty much an FPGA.http://www.alterawiki.com/wiki/BeMicro_MAX_10