Drill pairs for 4 layer PCB - Page 1
Forum section: electronics / beginners

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: July 08, 2019, 07:39:36 am
content: What is the correct / standard way to create drill pairs for a 4 layer PCB. I will have components on both top and bottom layer.Based on what I have read they say thru via's are the simplest and if we keep the board with only thru vias's it would be much easier for the board house.So I have 4 layers like Top Signal, PWR plane GND, PWR plane VCC, Bottom Signal or L1, L2, L3, L4.I was thinking of creating pairs likeL1 -> L2 Blind viaL1 -> L3 Blind viaL1 -> L4 Thru viaL4 -> L3 Blind viaL4 -> L2 Blind viaL4 -> L1 Thru viaIs this the correct way of doing it?However thinking further regarding the manufacturing process, I guess the board house might doCase1Two double sided pcb,s and some insulator in between and stick them all together.I this case they would do the double sided PCBs with thru via's so that would be L1->L2 and L3->L4 but how does a trace get connected from L1->L3 in this case?Case2One double sided pcb for the PWR planes, and 2 single sided PCBs one on top of the double sided and one on bottom.In this case all board's will be seperately drilled stuck together and again drilled to get the final thru' vias.In this case we will gett connectivity between all per what I need.But I'd like to know the standard way of doing this. I intend to get the boards done at JLPCB.

author: Psi
author_rank: Super Contributor
timestamp: July 08, 2019, 08:24:17 am
content: I had this exact question when doing my first 6 layer HDI pcb.Sadly it was a while ago and i don't recall what the answer was.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: July 08, 2019, 08:40:52 am
content: Quote from: Psi on July 08, 2019, 08:24:17 amGood to hear, In fact now that I see some info on JLPCB website on this pagehttps://jlcpcb.com/capabilities/CapabilitiesThey say1-6 copper layers PCB prototypes(Don't support Blind/Buried Vias)So if blind via's are not supported how does one connect Power traces from the top layer to the internal power plane?

author: oPossum
author_rank: Super Contributor
timestamp: July 08, 2019, 08:45:22 am
content: The vias connect to all copper layers.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: July 08, 2019, 08:51:51 am
content: Quote from: oPossum on July 08, 2019, 08:45:22 amSo, If I have a component on the top layer and I need to connect its powers pin to L3 (VCC plane) how does one do that, if as you say its a thru via and connects to all layers? how does the board house isolate this via from GND (L2).

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 08, 2019, 09:15:31 am
content: If at all possible avoid blind & buried vias.If you need them, the standard build is to make layers 2 & 3 as a double-sided board, and then sandwich a layer either side, so the cheapest ( though often least useful) is 2-3 and 1-2-3-4

author: oPossum
author_rank: Super Contributor
timestamp: July 08, 2019, 09:21:04 am
content: Quote from: ZeroResistance on July 08, 2019, 08:51:51 amYou have to have some clearance around the vias on layers they do not connect to. Your PCB CAD software will do this for you.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: July 08, 2019, 09:22:11 am
content: Quote from: mikeselectricstuff on July 08, 2019, 09:15:31 amThat's exactly what I want to know. How do I avoid blind via's if I want to connect a trace from top layer (L1) to internal PWR plane (L2).

author: martin1454
author_rank: Regular Contributor
timestamp: July 08, 2019, 09:25:44 am
content: You can connect L1 -> L3 using a through hole VIA since it goes through the whole board.a VIA is a "metal tube" though the board, and you can connect to the "tube" if you just route you trace / plane to the tube - and you isolate from it, by making a cutout around the "tube" in your plane.I have attatched a picture where you can see 2 layers of a PCB, and you can see how there is isolation by removing copper around the hole on the layer is isn't connected to, and it is connected by copper on the layer it is needed.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 08, 2019, 09:39:00 am
content: Quote from: ZeroResistance on July 08, 2019, 09:22:11 amThe PCB software should take care of that - the plane will have a net associated with it, and if a via is connected to that net, it will join it to that plane, otherwise it will create clearance around it.I'm sure different PCB software packages have slightly different ways of dealing with this.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 08, 2019, 09:42:37 am
content: A significant issue is that through vias always take up pad space on both surfaces regardless of whether you are making a connection on the layer, and this is often the first limiting factor you hit on component density.Most PCB manufacturers won't let you shrink the unused surface via rings to reduce the space used, presumably as it messes up their plating and/or test processes.You need to compare the cost of going to smaller line/hole sizes with that of using buried or blind vias

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: July 08, 2019, 10:13:16 am
content: Quote from: mikeselectricstuff on July 08, 2019, 09:39:00 amOk, I get it now, it depends on the NET then...I need to find how to assign nets to the internal planes then.

author: thinkfat
author_rank: Unknown
timestamp: July 08, 2019, 11:02:39 am
content: Quote from: ZeroResistance on July 08, 2019, 10:13:16 amIf you use copper pours for the internal planes (which is what you typically do) you won't be able to do them without a net assigned anyway.If you use an Altium PCB software, Designer or their free CircuitMaker and want to use JLCPCB as the board house, be advised to set the layer type of the internal layers to "signal". Otherwise the generated Gerbers will not be compatible with their processing.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: July 08, 2019, 11:21:18 am
content: Quote from: thinkfat on July 08, 2019, 11:02:39 amDidn't know that internal planes are generally copper pours, I guess the software does the planes for you, and you don't need to do any pours.Thanks for the info regarding JLPCB.

author: TheHolyHorse
author_rank: Regular Contributor
timestamp: July 08, 2019, 11:30:47 am
content: Quote from: ZeroResistance on July 08, 2019, 11:21:18 amIt won't just magically know that you want a copper pour, you're gonna have to specify the area, net and layer that you want the pour on.

author: thinkfat
author_rank: Unknown
timestamp: July 08, 2019, 11:39:27 am
content: Quote from: ZeroResistance on July 08, 2019, 11:21:18 amThat depends on the software you use. In Altium, if you set the layer as "power plane" you'll just specify a net for the plane and some other parameters and it will do it for you. But this is exactly what you cannot do with JLCPCB, because it will create "negative" Gerber files which they cannot process. So use a "signal" plane and put a copper pour manually.The only other software I know intimately enough to talk about is KiCAD, and there you will need to manually put a cooper "area" and assign a net to it.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 08, 2019, 12:17:59 pm
content: There are typically 2 ways - specify the layer as a plane, which produces a negative gerber, or a normal signal layer, onto which you place pours.The former can be better for single planes as it can reduce screen clutter, the latter is better if you have multiple planes and traces on that layer.

author: tszaboo
author_rank: Super Contributor
timestamp: July 08, 2019, 12:29:54 pm
content: If you dont know what a blind or a buried via is, or what is backdrilling, than dont do it, cause you dont need it. If you make a PCB with not standard via structures, your price goes up tenfold. You've been warned.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: July 08, 2019, 12:57:45 pm
content: Quote from: thinkfat on July 08, 2019, 11:39:27 amSo is this a limitation of JLCPCB processing pipeline? I guess you learnt this from experience? Or did JLPCB inform you that your gerber's were not compatible with their processes?

author: thinkfat
author_rank: Unknown
timestamp: July 08, 2019, 02:25:09 pm
content: Quote from: ZeroResistance on July 08, 2019, 12:57:45 pmYes, limitation on their side. It's in their FAQ, actually. I advise to have a look at their manufacturing FAQ and capabilities page before you start with the PCB. You'll have to set up the design rules according to their manufacturing capabilities or you might design a board that they cannot produce. Minimum drill size 0.3mm, just one example.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: July 12, 2019, 12:02:03 pm
content: Quote from: mikeselectricstuff on July 08, 2019, 12:17:59 pmI agree the former is better and I would have preferred that method.According to "thinkfat" that method is not compatible to JLCPCB. Unless ofcourse if there is a workaround to that.Otherwise signal layers as discussed above would have to be done.

author: Psi
author_rank: Super Contributor
timestamp: July 13, 2019, 05:19:37 am
content: I remember when i did a 6 layer HDI PCB with blind vias (no burred) for a 0.4mm BGA the pcb order cost ~US$1000 for around 25 pcs from PCBway.The boards arrived and a day later i was told the product was to change and the pcbs were no longer needed.