Location and value of decoupling capacitors (not BGA) - Page 1
Forum section: electronics / projects

author: c64
author_rank: Frequent Contributor
timestamp: July 01, 2020, 02:32:26 am
content: Many manufacturers recommend the following in datasheets:- have multi-layer board with ground and power planes- have trace from power pin to decoupling capacitor, then via from capacitor to power plane- use only 100nF capacitor(s), but sometimes recommend 1nF as wellMy understanding is it is better to connect power pins directly to power planes with as short traces as possible, since inductance of the power planes is almost zero, and inductance of vias (which are < 1mm long) is much smaller than inductance of trace they recommendRegarding the value of the capacitor, 100nF is good only up to 10, maybe 20 MHz, and to cover everything above you need to place more capacitors of different values, for example 47n, 10n, 3.7n, 1n - all togetherP.S. This is all about the packages with pins near the edge of the chip (i.e. not BGA)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 01, 2020, 02:44:39 am
content: Right, more or less.Regarding "goodness":A 100nF 0603 may have ESL of 3nH or so in a typical layout, which is SRF at 9.2MHz.It'sno worse thana 1nF of the same size and layout, i.e., it's still 3nH on the HF asymptote.If that's a low enough impedance for the load, that's it, you're set, it's done!If the load needs a lower impedance, it doesn't much matter what value you use, so long as it's (physically) small enough, wide enough, or quantity enough, to meet that requirement.You do of course need a large enough value to do anything; 1pF won't cut it. But 10nF and up are plenty available in small sizes, so there's not much reason to use less. And for that matter, not much reason to use more; 100nF just happens to be the de facto standard.What you definitely want to avoid, is making a resonant network between stacks of capacitors. This is the best reason to ignore advice suggesting tapered values and sizes.Tim

author: profdc9
author_rank: Frequent Contributor
timestamp: July 01, 2020, 03:21:12 pm
content: Just a quick question about this...In some cases, does it make sense to add some series resistance to the larger value capacitors to prevent parallel resonances between capacitors placed in parallel?For example, use a 100 nF 0603 with 1-10 ohms in series, and a 1 nF 0402 in parallel with that combination, with the 1 nF placed closest to the bypassed pin? Then maybe with a ferrite bead and/or a series resistor of 1-10 ohms to suppress overall resonances?Usually I try to get away with a single low inductance capacitor if the inductance is small enough, but at some point the wire bonding inductance is going to dominate and no matter what you do there's going to be a resonance.I go by what is written here as a general guide:https://www.avx.com/docs/techinfo/CeramicCapacitors/parasitc.pdfQuote from: T3sl4co1l on July 01, 2020, 02:44:39 am

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 01, 2020, 04:16:43 pm
content: Quote from: profdc9 on July 01, 2020, 03:21:12 pmYes, particularly bulk caps with large values and low ESR: ceramic and polymer especially. (Mind that, while ceramics aren't, polymers are available in many ESRs: shop accordingly. And tantalum are available in a higher but overlapping range; with ceramic and polymer being pervasive nowadays, tantalum aren't all that important anymore, and you don't have to worry about triggering thermite reactions, or buying conflict minerals.)QuoteIf the 1nF 0402 has about 2nH ESL, and the 100n + 1R has about 6nH, that's Zo = (8nH/1nF) ~= 2.8 ohms, so 2.8 ohms ESR would be the best match.The effect is this:- If the supply impedance is generally high at these frequencies, then we can ignore it for purposes of the thought experiment;- If you made the parallel combination without ESR, the peak impedance (at about 56MHz) can be many times higher than 2.8 ohms; likewise, the valley impedance nearby can be many times lower, but the peak is what we're most concerned about.- With ESR, the impedance minima is raised to 2.8 ohms, but the maxima is also lowered to that.For the stated 1 ohm, the damping will be modest, and the peak can be somewhat higher.If this is sufficient for the application, great. If it needs lower impedance, you need a different network.Note that going to 10n (0402) affords the same ESL towards the device but ~1/3 the resonant impedance and frequency, so ~1 ohm is suitable ESR.Note the first condition: this is to illustrate this network in isolation. In a practical circuit, this network will be connected to a larger PDN with trace and via inductance, and then we must consider the response of that combination in turn. Probably, the highest frequency mode won't be hugely affected (it may rise in frequency, or drop somewhat in peak impedance, but probably not go away), but everything below that (i.e., resonances concerning the 100n) will be highly dependent.QuoteWell, not necessarily a resonance, just a rising asymptotic impedance as seen by the chip inside. If the chip has onboard bypassing (there's always something, even if it's just all the gate capacitances acting together) maybe it can resonate. The chip also has some parallel resistance (digital logic consumes more current at higher voltages), and maybe series resistance too (spreading resistance).There's not much you can do about that, and presumably -- since manufacturers generally recommend wiring chips this way, with adjacent bypass -- we can assume that the chip will be well-behaved in this case, whatever the underlying explanation.Put another way, there isn't much we can do above 100MHz or so, on board -- the impedance is too low and even a tiny distance is too much stray inductance to deal with. Chips necessarily have to deal with that onboard.Tim

author: c64
author_rank: Frequent Contributor
timestamp: July 07, 2020, 04:12:17 am
content: Quote from: T3sl4co1l on July 01, 2020, 02:44:39 amSome manufacturers actually recommend placing different capacitors. Altera for example has some spreadsheet for calculating how many capacitors and which values you need. I tried to put different values and it looks like you say: 100nF is no worse than 1nF. Why do they recommend this then?Here is the link to AN and spreadsheethttps://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/signal-power-integrity/power-distribution-network.html

author: schratterulrich
author_rank: Regular Contributor
timestamp: July 07, 2020, 07:36:40 am
content: Hello,my explanation for using different capacitors:At frequencies where transmission line effects are not present, the power-GND planepair acts as an ideal capacitor.This capacitance of the planes always resonates with the combined ESL of the mounted capacitors and creates a parallel resonance. The peak impedance can be quiet high.See CASE1 in the simulation.You can reduce the peak impedance slightly by optimizing your capacitor values. X7R capacitors with lower values also show a higher ESR, which is helpful for damping the resonance.See CASE2 in the simulation. It shows that you can reduce the peak tenfold.The Excel Spreadsheet from ALTERA should show the same.Regards Ulrich

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 08, 2020, 05:23:52 am
content: Interestingly, note that the above case assumes the different sized capacitors are locatedanywhere on the plane-- they don't have to be local to anything (there's no load indicated, after all, just a plane and some caps), and indeedshouldn'tbe clustered or chained together!Also note that a 1uF + 1R, if it can be made with low enough inductance, will do a better job than either example! Wide-format (e.g. 0612) chips can be used, connected with multiple vias, and multiple such "bulk bypass" caps can be scattered around.The main difficulty with "external ESR" like this, is the ESL you get from those two chips and connecting traces and vias. This is the main advantage of tantalum, aluminum polymer and electrolytic types: the ESR is internal, so there's no ESL penalty beyond the component tech itself (which is higher for electrolytics, but can be quite competitive for the others).Note that n identical branches in parallel act as effectively one branch with C --> C*n, R --> R/n and L --> L/n. That's why the first example has just the one resonance, and effectively 300nF, 10mΩ and 1nH on the right side.If we employ an RC network with say 6n ESL due to its layout, we can use 6 in parallel to get that down to 1n total.Tim

author: exmadscientist
author_rank: Frequent Contributor
timestamp: July 08, 2020, 05:05:26 pm
content: The careful analyses discussed a bit here are correct, as far as they go, but you can get away with a lot less work. If I were to summarize the above discussion, it's "capacitance good, inductance bad, ESR useful for damping". This leads directly into my personal preferred strategy for general-purpose non-critical work:General decoupling: use only one value of physically small ceramic capacitor. Choose your package first, then buy the most C you're willing to pay for in that package.The general decoupling capacitors may be different in value for different rails (e.g., 12V vs 3.3V) but must be all identical for a single rail, to avoid resonances. Do not, in general, bother with silly manufacturers' recommendations to parallel values.(In general, take any manufacturer "standard recommendation" that looks like it's been copy-pasted a thousand times with a container of salt. Often they can be improved on.)As space permits, stitch each terminal of each decoupling cap to power or ground with three vias: one before the cap, one between cap and pin, and one after the pin. Each via lowers your L.Bulk decoupling: add on each rail one large capacitor (actual value in µF being defined by the application) with substantial ESR (>1 ohm).I usually prefer tantalum capacitors for power rails that donotrun off-board, as they are most cost- and size-efficient and their, ah, fussy tendencies are less... interesting... when they aren't connected off board.I usually prefer electrolytic capacitors for rails that do go off-board. They're larger, but more rugged. They're also usually more expensive in the grades worth buying (105°C+, 5000+ hours, or equivalent). Be careful to avoid super-low-ESR parts; they're not what you want here and it'd be a shame to add a series resistor to an electrolytic....I don't find much place in general use for polymer capacitors, either tantalum or aluminum. They're a bit more expensive and have less of the bulk ESR I'm looking for.My "standard decoupling" cap is now a 1µF 0402 ceramic. I've gotten some flak for this in design reviews, because it's not the "normal" 0.1µF. But then we build with it anyway and everything always seems to do fantastically... so this strategy does work! It's all heavily inspired by Henry Ott's writings, particularly what he and others call "Big V" decoupling. It isnotthe best you can do. But it's sure efficient in terms of performance returned per effort expended.

author: ejeffrey
author_rank: Super Contributor
timestamp: July 08, 2020, 06:32:59 pm
content: Quote from: c64 on July 07, 2020, 04:12:17 amProbably they were cutting and pasting from older recommendations that were cut and pasted from even older recommendations and never stopped to think if they still made sense. Whether those rules ever made sense or was just untested intuition is another story. There are some reasons why those recommendations might have made more sense in the past: if you go back 10 or 20 years, voltages were considerably higher. More 5V and 3.3V rails, less 1.8 V and below. Also, it used to be hard to find ceramic capacitors in small packages at higher voltages. So if you wanted an 0402 or smaller bypass capacitor on a 5V rail you might not be able to find or afford 100 nF @ 10 V. So you might end up using a combination of low value ceramic capacitors and higher value tantalums in a bigger package. The ESR of the tantalum would damp the resonance, and everything would be good. These days tantalum caps are out of fashion for good reason and high value ceramics are more available, although of course that 100 nF 10 V capacitor in an 0402 package might only be 10 nF at 5 V. But with core voltages now often around 1V, you can get a lot of capacitance in a small package.Also to reinforce what Tim said above: a lot of people overestimate how much difference proximity makes. At at 100 MHz 1/4 wavelength in FR4 is 35 cm. Capacitors significantly closer than 30 cm all basically contribute the same. Above 100 MHz, the power plane itself provides the lowest ESL capacitance depending on the laminate thickness. So it is really more correct to think of your 100 nF bypass caps (or whatever you use), a distributed *bulk* capacitance that has extremely low ESL/ESR by having so many capacitors in parallel rather than "local" decoupling. On many boards you could just stack all your 100 nf capacitors in a row along the edge of the board and it would have almost the same effect -- as long as they all had their own vias and were not crowded together so much that it created a current choke point.

author: schratterulrich
author_rank: Regular Contributor
timestamp: July 08, 2020, 06:42:52 pm
content: Quote from: T3sl4co1l on July 08, 2020, 05:23:52 amIf you analyze the real layout, each capacitor would have its ESL plus some inductance depending on its distance to the measuring point. So the impedance and resonances differ for each position on the board.I fully agree with the rest of your post.Quote from: exmadscientist on July 08, 2020, 05:05:26 pmIt's just the way I do it.It is often recommended to connect a via only before the capacitor - in order to filter interferences produced by the IC by means of the lead inductance. I believe that this is not effective. Interference on the supply pins of a digital IC can be found on all I/Os that are at high level. So you would have to filter all pins, not only the supply pins.Quote from: exmadscientist on July 08, 2020, 05:05:26 pmFor power electronics, polymer capacitors can reduce the impedance at low frequencies to very low levels. And they will keep their low ESR at low temperatures.I think these components can have great advantages.Quote from: ejeffrey on July 08, 2020, 06:32:59 pmThis is how we do it. We use a 50µm prepreg for PWR-GND plane pairs and don't need to place 100nF capacitors at each IC anymore. We only place "capacitor groups" optimized with a PI simulation tool every 1dm² of board area. And of course bulk capacitors as needed.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 08, 2020, 10:46:47 pm
content: Quote from: exmadscientist on July 08, 2020, 05:05:26 pmJust a refinement to the first quoted point -- the desired ESR is of course whatever the circuit needs. Vcore often needs much lower, for example; whereas an old school analog circuit might be most comfortable with much more (e.g. bypassing a LM317).Electrolytics have all sorts of ESRs, so you can easily toss in a small shitty one to do the latter, or a big and stout one for the former (or polymers).Regarding the other points -- hmm, shop around! I think you'll find polymers are available in a wide range of ESRs, just like tantalums are. As a group, they do cluster lower, but there is much overlap.Also, if you do "screw up" with having too little impedance, you can always add series resistance. Say you have a large common supply rail, which requires polymers or ceramics to meet its ripple spec. Then you have smaller loads starred off from this node. To keep those loads happy, you can either add series impedance at the connection, making a one-side-open, one-side-terminated filter; or parallel impedance, making a one-side-terminated, one-side-shorted filter.For the first case, use a lossy inductance (R || L). You need to know total capacitance on either side of this point, and desired impedance or cutoff frequency. Then you can solve for L and R. The load's plane can have low ESR caps all over (subject to the above limitations on split resonances, of course).For the second, use some series L (may be very little, like 10-100nH of trace inductance), and a lossy bulk cap in parallel with the plane, at the load end.Nothing wrong with doing both, of course (doubly terminated filter)!The downside to this is, an R||L element has poor attenuation at high frequencies. You can use higher order filter sections to account for this (say L + R||L, or more CLC sections, damped with R+Cs, etc.).And of course, if you can afford the DC drop, an L with sufficient DCR to do the damping, is perfectly fine!Tim