4 Layer Board for ZYNQ and DDR3 - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 12, 2019, 02:48:46 pm
content: Hi,I'm curios if someone has done a ZYNQ (XC7Z020-2CLG400I) and the DDR3 memory on a standard 4 layer PCB (maybe JLCPCB), using Altium- since I want to modify the design and just use this part to save some time! if so are you willing to share the design files?Thanks for the help.

author: OwO
author_rank: Super Contributor
timestamp: November 12, 2019, 03:25:11 pm
content: https://github.com/gabriel-tenma-white/sdr5The Zynq and DDR part are already tested; use the zynq_som_2 design.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 12, 2019, 03:31:08 pm
content: QuoteThanks, you are life saver!is it in Altium?

author: OwO
author_rank: Super Contributor
timestamp: November 12, 2019, 04:41:03 pm
content: Sorry we don't do altium here. There is absolutely no reason to use a proprietary PCB design package when we are already able to achieve better productivity than other design teams while using existing open source tools.

author: AndreZheng
author_rank: Contributor
timestamp: November 13, 2019, 07:59:32 am
content: For the same pcb size, e.g. 10cm x10cm, the 6 layer pcb costs only one more $ than 4 layer pcb. I’m curious why you want to save this 1$ when the xc7z020 board’s BoM cost more than 40$.You save 1$ here, you will lose many brnifits like: easy to route the pcb, better EMC performance, etc.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 13, 2019, 09:04:44 am
content: Quotewhich PCB service do you use? I will use 6 layer if it's 1$ higher!

author: langwadt
author_rank: Super Contributor
timestamp: November 13, 2019, 09:15:20 am
content: Quote from: AndreZheng on November 13, 2019, 07:59:32 ammore like triple the price

author: colorado.rob
author_rank: Frequent Contributor
timestamp: November 13, 2019, 01:25:10 pm
content: Depends on the quantity. At my favorite PCB house, it costs $0.40 more per board at quantity 1000, and $1.20 more at quantity 100.

author: OwO
author_rank: Super Contributor
timestamp: November 13, 2019, 02:25:28 pm
content: At 1000pcs even a 12 layer board costs only $3.8 per unit (10cm x 10cm)4 layer board for a Zynq makes it accessible for hobbyists. Cost of a 6 layer prototype (5pcs) is over $100 compared to $30 for 4 layers. BGA soldering is easy to do at home with a hot air station.

author: colorado.rob
author_rank: Frequent Contributor
timestamp: November 13, 2019, 06:52:09 pm
content: The dude's using Altium. He's not doing hobbyist work here. If you read the other thread he started where he is working on a Zynq project, he's doing commercial work. The cost of his time is going to dwarf the board cost.

author: OwO
author_rank: Super Contributor
timestamp: November 14, 2019, 04:48:42 am
content: Yes but in a medium-high volume commercial project (say 100-1000 units/month) the BOM cost will usually dwarf the development cost again; on one product line some quick math shows it's worth it to spend several engineer-months to just save $1 of BOM cost. Exact figures will depend on your volume of course but I cringe when I see people saying the extra "work" associated with using a cheaper part (usually cheaper by several dollars) will cost more than it earns.

author: Scrts
author_rank: Frequent Contributor
timestamp: November 14, 2019, 02:04:55 pm
content: Quote from: colorado.rob on November 13, 2019, 06:52:09 pmYou would think so, because you are in the US. Guess what's the illegal software population is in Iran? Even in businesses...

author: NorthGuy
author_rank: Super Contributor
timestamp: November 14, 2019, 04:24:14 pm
content: Quote from: colorado.rob on November 13, 2019, 06:52:09 pmThe cost of his time is expense for his client, but revenue for him

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 14, 2019, 04:44:59 pm
content: Quote from: NorthGuy on November 14, 2019, 04:24:14 pmAssuming he can freely bill his client according to his work time. Some contracts are based on fixed envelopes though, and once they've been dealt, the game is over. Any excess time you spend loses you money. So, that depends.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: March 01, 2020, 10:46:43 am
content: Hi,OwOWould you please add the gerbers and schematics PDF to your repo.Regards

author: OwO
author_rank: Super Contributor
timestamp: March 01, 2020, 11:02:28 am
content: You are going to want to make changes to the board because it has no peripherals, no proper way of connecting a daughterboard, and you're going to want a higher current 1.0V buck converter for Zynq-7020. The SOT23 buck converter used only goes up to 3A, which is fine for Zynq-7010 but not for 7020. The SoM design as is is only good for prototyping and one-off projects; the pads at the edge can be mated to another board of same thickness by soldering, but this is not proper mechanically and you don't want to do that for production. Just go and install gEDA and learn it, or find some way of copying it into kicad.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: March 01, 2020, 11:48:09 am
content: Thanks OwO, for the points,Actually I just want to grab the traces for the DDR3 part and paste it into the altium designer, and change the rest. I think you can help me with the gerbers at least,so I do not have to learn a new tool for just doing that.

author: tom66
author_rank: Super Contributor
timestamp: March 03, 2020, 11:02:02 am
content: I had difficulty getting a single-channel (16-bit) DDR3 layout working on a 6-layer board. Maybe if you stick to 4-bits interface you can do it on 4 layer, but you will struggle to break out any IO from within the BGA without microvias or inter-layer vias in my opinion.

author: OwO
author_rank: Super Contributor
timestamp: March 03, 2020, 11:40:01 am
content: ..and I did full 32 bits DDR3 on a 4 layer board while having >70% read/write eye at 1066MT/s. Looking on the xilinx forums most people end up with ~60% eye with 8-12 layer boards, I don't know how they achieved that, although it is a biased sample because people who get DDR3 working correctly don't tend to post on the forums.It's not that hard; here are the tips I posted on another thread a while ago:All DDR traces must form a microstrip or stripline against the closest ground plane (usually 0.1mm away) which must be solid and have no breaks under the tracesAll ground and power pins on both the SoC and DDR chip should be accounted for; either they need to go to a plane, or have a decoupling cap right under the balls that goes to a plane. Every ground ball should have its own via, but a cluster of e.g. 4 ground balls are allowed to be connected together and grounded using 3 vias spread apart.If using a power plane, it must be stitched to the ground plane using a capacitor every 1-2cm, with higher density near signal layer transitions. For example, if a few DDR signals go from top to inner layer, you need a stitching capacitor or two around the via transition.

author: OwO
author_rank: Super Contributor
timestamp: March 03, 2020, 11:49:58 am
content: Some pics:Top layer overlaid on in1:in2 overlaid on bottom:Bottom view of the board, with in2 visible and VCCDDR net highlighted:The bottom layer is a VCCDDR plane in the DDR3 area, and ground plane elsewhere. DDR3 traces are routed on 2 layers, top and in2, and all traces go over solid ground or power planes. You can see the many stitching caps that tie the VCCDDR plane to ground.In the HPS area the board also routes out USB ULPI and SD card interface, but ethernet was not possible. On the FPGA side 40 IOs are brought out in total. You can bring the GMII interface into the FPGA (can be configured in vivado) and attach the ethernet PHY to the FPGA side IOs.The board was designed for JLC specs, and uses 0.12mm minimum trace width and spacing.

author: nctnico
author_rank: Super Contributor
timestamp: March 03, 2020, 01:22:45 pm
content: What usually helps is to aggressively reduce the number of supply voltages needed. It is not the traces that eat layers but power supply layers.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: March 03, 2020, 01:25:29 pm
content: Relay Thanks OwO,Big thumbs up. does this gEDA generate Gerbers? what's the part number of the power supply parts? the excel in your repo seems broken!

author: OwO
author_rank: Super Contributor
timestamp: March 03, 2020, 02:36:57 pm
content: Actually that bom file isn't supposed to be in the repository, I'll go delete it. Don't build this without looking through the design fully and fixing things up according to your requirements. The part numbers on the schematic are indicative only; for example it specifies 2A buck converters (AP3419) but I've substituted in the pin compatible FP6373 (3A output). The mappings file (zynq_som_2.mapping.csv) contains the real part numbers; I'll go and update it with my latest parts choices.The power supply section REALLY needs to be fixed up, as it is it will only supply 2A on the 1.0V rail because that's the highest rated inductor you can get in a 1008 package. sdr5 design fixes this by using 2 inductors in parallel, but still this only gets you to 3A (limited by FP6373). In the Artix board I'm working on I'm using the JW5068 which goes to 8A but it's in a different package and uses a much bigger inductor. I'm not going to go and incorporate this into the zynq_som_2 design because I'm not doing another revision of this, it's a done project and is only meant as a reference or starting point when designing new Zynq boards. However I am designing a new Zynq baseboard for a new SDR design that I'll release soon, and that one will have these things fixed. Still it's an application-specific board and you won't be able to make use of it verbatim; you will have to make changes to suite your requirements.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: March 04, 2020, 06:43:00 am
content: Thanks for the feedback, I managed to find JW5062T in SOT23-6 pin and it can deliver up to 4A,I think it maybe used for ZYNQ 10 device.

author: asmi
author_rank: Super Contributor
timestamp: March 04, 2020, 01:52:25 pm
content: Quote from: ali_asadzadeh on March 04, 2020, 06:43:00 amI doubt SOT23 will be able to sustain that kind of load without overheating in any kind of enclosure. Even at 90% efficiency we're talking about 0.4 W of thermal power. That's quite a bit for such a small package with very high Rtja.As a rule, for currents >2 A I use DC-DC converters (and LDOs) only in packages with exposed pads, as that's the only way to ensure long term thermal performance by sinking heat into ground plane(s). This is especially so for FPGA boards which tend to have a bunch of them very close to each other.

author: OwO
author_rank: Super Contributor
timestamp: March 04, 2020, 02:44:47 pm
content: Yes, also the Zynq-7020 will need to be heatsinked too. On a Zynq-7010 with a almost fully loaded design drawing under 2A total (Vccint and Vccintp combined), it easily reaches 85C junction temperature. Zynq-7020 can draw as much power as an Artix-100T (~6A on Vccint under full load). What I did in sdr5 is put all higher profile parts on the opposite side as the Zynq, and use thin thermal pads to heatsink the Zynq to an aluminum plate/enclosure.

author: asmi
author_rank: Super Contributor
timestamp: March 04, 2020, 03:03:06 pm
content: I found an easy way to seriously heat up any 7 series FPGA - just overclock their BUFGs, load design into FPGA and watch Tj skyrocket! Even A35T will get 70°C+ without heatsink if I run my 1080p HDMI out design (which overclocks a single BUFG to 742.5 MHz that's specced to 628 MHz for -2 speed grade), and the S50 chip from the board in my signature get into 60°C+ even with a small heatsink (without it the chip went into 90°C+ before I intervened to reset the design).Part of the reason is that these boards are quite small, so FPGA can't sink a lot of heat into the board (The Rtjb of FTG-style packages is a lot smaller than Rtja), especially when it has to "compete" with DC-DC converters which also sink heat into the board.

author: aseok
author_rank: Contributor
timestamp: March 07, 2020, 06:18:01 am
content: What is the dram data and address bus termination configuration?

author: KE5FX
author_rank: Super Contributor
timestamp: March 07, 2020, 08:36:08 am
content: Quote from: asmi on March 04, 2020, 03:03:06 pmMeh, 70C is barely warmed up.You can get them rated for 100C.I don't know if you're using the internal XADC-based thermometer to check the temperature, but something I've noticed is that it overreports the temperature by anywhere from 5-10C. You can verify this simply by checking it immediately after power-on, when the die is still at room temperature. In a 25C environment it's not uncommon to see 30-32C reported, and I doubt it's any more accurate at higher temps.So you are probably fine at 70C indicated, at least IMHO.

author: OwO
author_rank: Super Contributor
timestamp: March 07, 2020, 08:37:12 am
content: Address/control are source terminated only, by FPGA driver impedance. Data lines use on-chip termination (source and load) which is standard in DDR3 and later. It's not possible to fit termination resistors on the PCB and maintain ground integrity.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: March 16, 2020, 07:44:41 am
content: what'a the part number of your DDR3 parts?

author: OwO
author_rank: Super Contributor
timestamp: March 16, 2020, 08:29:40 am
content: H5TQ4G63AFR is what I used on that board and seems to be the most common DDR3 component on the market.