synthesizable delay in VHDL?  - Page 1
Forum section: electronics / general

author: conducteur
author_rank: Regular Contributor
timestamp: April 13, 2015, 06:37:42 pm
content: I'm a student in electronics, (bachelor 2nd year) and i have to code something in VHDL, and i need a systhesizable delay in VHDL. I know there's a "Wait for" code, but you can't synthesize that?

author: Neilm
author_rank: Super Contributor
timestamp: April 13, 2015, 06:52:16 pm
content: The "wait for" command is only used for test benches. For real world delays, make a counter and reset it when appropriate. Then a bit of logic to produce the time pulse (don't do it when resetting the counter - you will get race conditions and a very small pulse.

author: Bassman59
author_rank: Super Contributor
timestamp: April 13, 2015, 08:56:38 pm
content: Quote from: conducteur on April 13, 2015, 06:37:42 pmVHDL'swait for {time};is always ignored by the synthesis tool, as is the equivalent Verilog delay mechanism.The only way to create a delay in an FPGA is to use a storage element (a flip-flop). The granularity of the delay is determined by the clock frequency.You can be clever and use a clock-management features such as a DLL or PLL to delay the clock feeding your logic, but that can get tricky. And you have to instantiate the DLL and create the phase-shift control logic.Most modern FPGA families have a mechanism to add a delay to input signals, but you have to instantiate the proper elements.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 13, 2015, 09:05:08 pm
content: It all depends on what you need the delay for!If you are interested in just delaying a data stream for a given number of cycles for smaller delays use an appropriately sized shift register. For longer delays (up to a few thousand cycles) you can use use a dual-port RAM with the read and write addresses that increment each cycle, but are offset from each other to give the delay you require. For really long delays (e.g. implementing a reverb for audio) you might need to use some external SDRAM for temporary storage.Counters are great for timing longer delays, and are very resource efficient. For really long delays you may need to cascade two counters as a single long counter can end up being too slow for your clock rate, as the logic for detecting the terminal count gets more complex. For short delays you can use a shift register with one-hot encoding. Something like:Code:...signal delay_shift_reg : std_logic_vector(4 downto 0) := "00001";...if rising_edge(clk) thenif delay_shift_reg(0) = '1' then-- do the stuff here one in 5 cycles.end if;-- Move the shift register alongdelay_shift_reg <= delay_shift_reg(3 downto 0) & delay_shift_reg(4);end if;For I/O really short (less than the clock cycle) delays you can use DDR registers to give you a half cycle delay for outputs - perfect for sending out a clock signal that is 180 degrees out of phase with data pin transitions. On some FPGAs I/O pins can delay signals with a small internal delay line that can control relative skew between signals Google "IDELAY" or "ODELAY" for Xilinx FPGAs.For more exotic needs you can use clocking resources to generate clocks with different relative phases, and use different clocks to drive different signals. I've used this once to make a write enable pulse for SRAM, which needed to be 7.5ns long while running with a 10ns clock.If you need precise short delays you can also use the SERDES blocks to make tiny adjustments in signal phase - for example, if you have a 8:1 serializer, and are running at 125MHz you have control to 1ns.

author: Harrkev
author_rank: Contributor
timestamp: April 13, 2015, 09:17:18 pm
content: Sorry, but I am coming from an ASIC background -- my FPGA experience is a bit rusty. As others have stated, for a long delay (relatively speaking), registers are the way to go.However, if what you need is a tiny delay (small fraction of a clock cycle), then it may be possible to do this. You should be able to manually instantiate FPGA gates (this makes the design much less portable to other architectures, however). Once instantiated, there should be a way to set a "dont_touch" on these gates to tell the synthesizer to keep them. A chain of inverters should work nicely.As I said, this is a great approach if you need a delay shorter than one clock cycle. The delays will also be variable, depending on the speed of your particular part, current voltage, ambient temperature, phase of the moon, etc. Still, it might be good enough.

author: conducteur
author_rank: Regular Contributor
timestamp: April 13, 2015, 09:38:45 pm
content: ... Just need to have one delay "do 10 ms nothing" (inside a process)... Clock frequency on the devboard is 50Mhz

author: Whales
author_rank: Super Contributor
timestamp: April 13, 2015, 10:58:14 pm
content: A bit of background on why it's hard to get delay elements on FPGAs: they don't actually implement your circuit in the way you expect. A lot of what you write gets turned into lookup tables (see wikip), which don't really provide a good method of intentionally delaying signals.Flip-flops and clock signals tend to be a first approach, but that may or may not suit.Where are you doing your bach?

author: conducteur
author_rank: Regular Contributor
timestamp: April 14, 2015, 09:47:45 am
content: Belgium, Vives OstendStatements inside a process are sequential?! (Or am I wrong?)

author: daqq
author_rank: Super Contributor
timestamp: April 14, 2015, 09:57:03 am
content: QuoteNope - when "compiling" into hardware everything is "executed" at once.VHDL (and other HDL languages) is for two different areas - synthesis and simulaiton/testing.Synthesis is essentially a conversion from code to hardware. A delay is NOT possible to directly synthesize. You can do it in various ways (most of which involve counters), but you cannot do:Signal <= A;WaitMs(100);Signal <= B;Simulation and testing do support a delay and a kind of sequential execution, but it's for the purposes of generating states into the tested hardware.

author: deephaven
author_rank: Frequent Contributor
timestamp: April 14, 2015, 10:17:00 am
content: Just have a counter to time 10ms worth of delay using your 50MHz clock. Things to watch out for is if your process is asynchronous with the 50MHz clock, then you would need to think about whether a 20ns jitter is a problem and also deal with meta-stable issues. If your process is synchronous with the 50MHz clock, then no problem.

author: AndyC_772
author_rank: Super Contributor
timestamp: April 14, 2015, 04:48:21 pm
content: Quote from: conducteur on April 14, 2015, 09:47:45 amNot really. At compile time, the synthesis tool parses each line in sequence, and it's certainly true that the order of the sequence can affect the meaning of your code. But when it comes to actually "executing" your code on the target device, for want of a better expression, there is no sequence unless you explicitly code for it.It's very counter-intuitive if you're used to writing code for a microprocessor. For example:a = b;b = a;... is a classic example of how not to swap the contents of two variables. But in VHDL:IF clk'event AND clk = '1' THENa <= b;b <= a;END IF;... actually does swap the contents of registers a and b on each rising edge of the clock. It doesn't matter which way round the two assignment statements are written, because they both happen simultaneously on each clock edge.Think of "a <= b" as meaning "a takes the value that b hadimmediately prior tothe clock edge".The sequence is sometimes important, though. For example:IF clk'event AND clk = '1' THENa <= '0';IF b = c THENa <= '1';END IF;END IF;... will set the value of a to 0 on each rising clock edge, unless b and c are equal, in which case a is set to 1. But:IF clk'event AND clk = '1' THENIF b = c THENa <= '1';END IF;a <= '0';END IF;... will always set a to 0. Moreover, the synthesis tool will spot that it doesn't require b or c, so if is this the only place in the code they're used, then they (and all the logic that might be required to generate them) will be optimised away. Also, since a is never assigned anything other than zero, any code which depends on the value of a will also be simplified.Be aware of this if you're ever fixing bugs in a device which is running low on spare capacity. It's quite possible to fix a bug, and find the code suddenly gets a lot bigger because half of it can no longer be thrown away!

author: hamster_nz
author_rank: Super Contributor
timestamp: April 14, 2015, 08:50:04 pm
content: Also, there may be a difference between what I think a delay is an what anybody else thinks:I want an output that delays an incoming audio bit stream by one second.vsI want a delays that turns on an on LED one second after a button is pressed.vsI need a 1s delay to debounce a switchThe solutions to all of these look very different...

author: AndyC_772
author_rank: Super Contributor
timestamp: April 14, 2015, 08:53:15 pm
content: Very much so. For the audio delay, you need a FIFO. For the other two, you just need a simple state machine and a counter.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 14, 2015, 09:48:25 pm
content: Quote from: AndyC_772 on April 14, 2015, 08:53:15 pmAnd even on the last two, it's different - for one you need a counter that just counts regardless of the state of the button till it reaches its terminal count, and for the other you need a counter that resets if the button is released.