First PSU circuit and questions - Page 1
Forum section: electronics / beginners

author: Ortzinator
author_rank: Contributor
timestamp: June 17, 2015, 12:58:37 am
content: Hello! I'm glad to finally post on this forum after watching Dave videos for a while and just recently getting into electronics.I designed this PSU after watching Dave's power supply design videos. I wanted to make essentially the same circuit but use components I have on hand. (Though, I still need a voltage reference.)Here are my requirements, which I think I have met:1.5-9VDC0-1A current limiting12VDC input (see questions below)Uses common parts, most of which I personally have.It seems to work great in simulation but it's not finished yet. I have a few questions.Would a computer PSU be alright to power this? If not, I have a few 12V/1A wall warts I could use.Can I add a current limiting LED indicator without adding another op-amp? Dave's solution used one because he was only using 3/4 he had available. But since my circuit did not require one for the LM317 adjust pin I am only using 2.Is the value of C2 correct? I just guessed at it honestly as I didn't know how to calculate the optimal value.Any other feedback is welcome. Thanks!

author: flynwill
author_rank: Regular Contributor
timestamp: June 17, 2015, 02:35:19 pm
content: The biggest problem I see with this scheme is that your current-limit circuit can not pull the output voltage all the way to zero. Once the voltage reaches the 1.25V reference of the 317 the current will rise only limited by the 317's own protection circuits.You certainly could use a computer PSU, but if you've got 12V wall wart that will fill your need I would stick with that.You will need a bypass cap on the input the LM317, the datasheets recommend 0.1 uF ceramic. It needs to be close to the 317 itself.Also the LM317 is going to potentially be dissipating 12W so it will need a decent heat sink.Since you've already got a number of parts including the dual op-amp and a voltage reference, I'd suggest skipping the LM317 and design something using a BJT pass transistor and additional opamps.

author: Ortzinator
author_rank: Contributor
timestamp: June 21, 2015, 04:10:21 pm
content: Thanks for the reply.I decided to go ahead and go with using discreet components like you suggested. However I'm having a hard time finding resources that explain how to do this in a way that I can understand. Dave's videos, by contrast, were relatively easy for me to understand. I've seen some schematics that seem simple but if I had something that outlined the different sections and and their basic functions that would be idealThanks again

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: June 21, 2015, 04:19:57 pm
content: Please put a big reversed diode across the input and output terminals of the 317.From the TI datasheet:"The diode provides a low-impedance discharge path to prevent the capacitor from discharging into the output of the regulator."The output capacitor could also be the capacitance of whatever you're powering up. If the current limit kicks in and tries to reduce the 317's output voltage, the load could start dumping current into your supply.

author: Ortzinator
author_rank: Contributor
timestamp: June 21, 2015, 07:44:23 pm
content: Is the diode always required? The majority of 317 schematics I've seen do not include one.

author: Yansi
author_rank: Super Contributor
timestamp: June 21, 2015, 07:55:48 pm
content: Yes, it is required.The output-to-input diode protects the 317 against connectin external voltage source to this supply, before switching it on (it may be a battery or so¨).The second diode, from the REG terminal to the output protects the device against breakdown of internal transistor structures, when you short the output terminals - the VREG-OUT pins would be reverse biased in that situation, due to the capacitor from REG to ground.Also third diode should be used, antiparallel with the supply's output.Use of the protection diodes depends on the application.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: June 21, 2015, 08:05:58 pm
content: Quote from: Ortzinator on June 21, 2015, 07:44:23 pmThe way to look at it is : how much does the diode cost vs. the potential failure of a power supply some time down the line. You may get a sense of false confidence with a few simple test cases then later on the supply fails when, as yansi says, you plug a powered load to your supply when it's off. etc.. etc... etc..

author: Ortzinator
author_rank: Contributor
timestamp: June 22, 2015, 01:51:36 am
content: Quote from: Alex Eisenhut on June 21, 2015, 08:05:58 pmGood point. Thanks.

author: deadlylover
author_rank: Frequent Contributor
timestamp: June 22, 2015, 02:09:27 am
content: Quote from: Ortzinator on June 21, 2015, 04:10:21 pmHi mate,check out the free chapter 9from Art of Electronics third edition, you may find it very helpful.

author: Ortzinator
author_rank: Contributor
timestamp: June 24, 2015, 09:15:10 pm
content: Quote from: deadlylover on June 22, 2015, 02:09:27 amThank you this is helping a lot!

author: Ortzinator
author_rank: Contributor
timestamp: June 25, 2015, 09:34:34 pm
content: So apparently even with discreet components you need a negative voltage to get down to 0V? And apparently the 3rd edition of AoE doesn't tell you how and just says to read the last edition.EDIT: I guess I missed the part where it says to put the adjustment at the reference to get < VrefSo here is my current circuit. Next I'll work on current limiting.

author: Ortzinator
author_rank: Contributor
timestamp: June 27, 2015, 01:10:49 am
content: New schematic! It goes down to 0V now. The big problem right now is that I had to use a large value capacitor for C1 to stop the current limiter oscillating. (I think oscillation is what was happening?) So now it takes quite a long time for the voltage to change when you adjust the setting. (Around 100ms) Is there something I'm doing wrong? This isn't normal, is it?EDIT: Attached the schematic!

author: dom0
author_rank: Super Contributor
timestamp: June 27, 2015, 07:54:58 am
content: C1...R10 smallerTry to compensate the current limiter locallyQuote from: Ortzinator on June 21, 2015, 07:44:23 pmNah, it's only an issue if the output can be powered while the input caps are discharged, which is why you never see these protection diodes in PSUs built into something. But in this case you really ought to have them...

author: flynwill
author_rank: Regular Contributor
timestamp: June 27, 2015, 02:26:18 pm
content: Quote from: dom0 on June 27, 2015, 07:54:58 amWhat he said. Try smaller R10 first, 1k. If that fails a small capacitor between the base and collector of Q2, or small capacitor between the output and - input of U2C are options.You may also want to add a small resistance (maybe 220) between the output of U2A and Q1 to stabilize the gain of that current feedback stage. Otherwise the gain depends on the effective output impedance of U2A which can vary by a factor of 10 or so.

author: Ortzinator
author_rank: Contributor
timestamp: June 28, 2015, 01:46:20 am
content: Quote from: flynwill on June 27, 2015, 02:26:18 pmIt's stable now! I needed to add both capacitors for it to work. It had a lot of overshoot but that went away when I tweaked the two capacitor's values.It seems to work as intended now. Anything else until I start ordering parts?

author: flynwill
author_rank: Regular Contributor
timestamp: June 28, 2015, 03:03:26 pm
content: There are lots of ways to stabilize a close-loop system, but adding two different poles in the forward path is not generally a good idea. To do this right requires detailed analysis of the loop gain & phase vs frequency, but I'm guessing that might be beyond your present skills. Your design may simulate ok with the "typical" values in the spice models and oscillate something awful when you build it from real parts.On thinking about your circuit further I realized that when your current limit becomes active Q2 is driving the output of the op-amp into it's current limit mode, so the small-signal gain of the Q2 stage becomes very high. I would suggest either adding a resistor between the output of U2A and the base of Q1 that is large enough that the op-amp won't current limit when Q2 saturates, yet small enough to provide the drive current for Q1 with an acceptable voltage drop (which will lower your maximum output voltage). My calculator suggests 680 ohm as a possibility, but check my math.The other option is to add a resistor between the collector of Q2 and positive supply. Perhaps 680 to 1k. This has the advantage of not further lowering your maximum voltage, but increases the power dissipation in your Op Amp.You should also look at the power dissipation of the opamp... The data sheet says these can source as much as 70 ma which if your current limit is on full force means that op-amp is dissipating 0.8 Watt. The data sheet indicates that the chip can survive this as long as it is only one amp in the package, but it might be another reason to add an resistor in series with it's output.I would also reduce the value of R10 to about 1k and/or add a capacitor in parallel with R10. This will increase the bandwidth and lower the phase delay of Q2. Then if the circuit still needs compensation add just the capacitor between the output of U2C and it's negative input. (Ie try to make the Q2 stage as wide band as practical and make the opamp the limiting factor as to bandwidth).

author: Ortzinator
author_rank: Contributor
timestamp: June 29, 2015, 02:18:20 am
content: Quote from: flynwill on June 28, 2015, 03:03:26 pmI don't know what you mean by this.

author: flynwill
author_rank: Regular Contributor
timestamp: June 29, 2015, 02:18:04 pm
content: Ah, sorry. If you don't know what is meant by "poles" and "zeros" it's not something that can be properly explained in these pages, there is quite a lot of math using complex numbers involved. I'll try to give a quick explanation but if it doesn't make any sense don't worry, the are hundreds of textbooks, manufacturer application notes, and probably web videos that cover this subject in detail and from all angles. (Dave probably even has one on this site somewhere, I haven't looked)When describing the response of a circuit vs frequency "poles" are frequencies at which the response curve takes a bend towards zero, and "zeros" are frequencies where the response takes a bend towards infinity. A simple RC filter is said to have a single pole whose frequency is 1/(2*pi*R*C). (You have probably seen that formula).In addition to the amplitude response taking the bend towards zero, the phase of the signal is effected as well. Going back to that same RC circuit, if feed it a sine wave well below the frequency of its pole and look at both the input and output on your oscilloscope you will see the output waveform pretty much lines up with the output. But as you raise the frequency starting about half of the pole frequency you will see that start to shift, and by the time you get to twice the frequency of the pole the output will be shifted nearly a 1/4 cycle (which we call 90 degrees) late compared to the input. The shift stops there, as you go to ever higher frequencies it continues to get closer to 90 degrees but no more. If you cascade two of these circuits one after the other then you have two "poles". The gain will take two bends towards zero, and the phase shift will start to approach 180 degrees (1/2 cycle) when you get about a factor of 2 higher than the higher frequency pole.Now consider a feedback loop, like the current regulator in your power supply design. Imagine a bit of noise propagating its way around the loop through each stage with it's gain & phase vs frequency characteristic. And just suppose that for some magic frequency as this bit of noise passes though all of the stages the accumulated phase shift reaches 1/2 cycle (180 degrees) but the gain greater than 1. So it arrives back where it started, louder, half a cycle late, and inverted. The net result is that it feeds on itself and the circuit oscillates. So you can see why adding two capacitors (which didn't actually create a poles but rather substantially lowered the frequency of an existing ones) is probably not helpful, because each will add it's 90 degrees of phase shift and you're already approaching 180 degrees without the contribution of all the other parts in the loop.The most straightforward way to stabilize a circuit like this is to pick a stage, typically the stage that already has the highest gain and lowest bandwidth, and add a capacitor so that the circuit has a single-pole frequency response at least until the frequency at which the gain reaches 1. That way the phase delay never gets much past 90 degrees (much less reach the 180 that will cause instability). When you see the words "unity gain stable" in an op-amp data sheet it means it has this sort of response. Gain and phase plots used to be a common feature on all opamp datasheets, but trying to find you an example just now I had to quite a bit of searching. But if you look at at the datasheet for this TI parthttp://www.ti.com/lit/ds/symlink/lmv721-n.pdfat the bottom of page 7 there is a plot of "Gain and Phase margin vs frequency". The term "phase margin" means the amount of phase shift relative to that magic 180 degrees, so the labeled "0" at the bottom of the plot represents a 180 degree phase shift, and you'll see that for that part the gain has long since fallen below unity giving a "gain margin" of almost 10 db. (Meaning you could potentially add another 9 dB of gain to your feedback loop and have it still be stable, provided that extra gain did not come with any addition phase delay.)

author: Ortzinator
author_rank: Contributor
timestamp: July 03, 2015, 12:40:57 am
content: Thank you for the detailed explanation. I understood a little but I haven't learned about RC filters yet so I'll go do that and come back. I think I need to learn more about op-amps too.

author: void_error
author_rank: Frequent Contributor
timestamp: July 03, 2015, 09:10:09 am
content: Quote from: Ortzinator on June 28, 2015, 01:46:20 amWhile it may seem stable in certain operating conditions it might be unstable/oscillate with some loads. Theoretically the topology your using should be stable with no capacitor at the output but practically it might require one along with some loop compensation network.I had this problem withmy PSU circuitwhich is a different (and inherently less stable) than yours but managed to make it stable with different loads connected to the output.Dave has a video about a circuit similar to yours.