edge-mount SMA center pin and trace width - Page 1
Forum section: electronics / rf-microwave

author: metebalci
author_rank: Frequent Contributor
timestamp: April 11, 2021, 06:48:58 pm
content: I am trying to understand how to use edge-mount SMA connectors properly.Looking at cinch's document (https://www.belfuse.com/resources/productinformations/cinchconnectivitysolutions/johnson/pi-ccs-john-142-0701-801.pdf), it is clear for 2-sided boards, 1.6mm to 0.8mm. In these cases, trace width is always larger than pad which in turn larger than center pin (I think the center pin is always 30 mil for these connectors).Moving to 4-layer boards, for example for JLCPCB stackups, trace width is either ~12mil or ~6mil, so it is smaller than the center conductor. Is there any proper way to use such connectors with narrow traces like this, or other connectors with narrow center conductor has to be used ?I saw TI's document on the same topic and they I believe recommend to use a connector with narrow center conductor, same as trace width at max or maybe it is optimal:https://www.ti.com/lit/an/snla186/snla186.pdfHappy to check reference documents or books on the topic if you have any recommendation.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 11, 2021, 09:39:43 pm
content: As always, the question is: how flat do you need?You can always relieve ground underneath the pin/pad. How much (to layer 3 or 4?), by how far (clearance), and how to taper from low to high microstrip (some kind of taper), all fine questions best answered with simulations or protos, but just a basic effort should at least extend it say an octave or two (so, many GHz).But it's... a rather irrelevant question anyway? Because, proto stackups aren't impedance controlled, and FR-4 sucks anyway; and even on good RF stock, you're only going to get so-and-so much tolerance (nominal impedance +/-10% say?).Tim

author: ejeffrey
author_rank: Super Contributor
timestamp: April 12, 2021, 05:34:56 am
content: You can fairly easily figure out how big a deal this is, the pad is just a bit of extra shunt capacitance. You can calculate how big it is and see what the effect is. If the excess capacitance is not too great you can deliberately add some series inductance to impedance match to 50 ohm. That effectively turns it into a lowpass filter with (hopefully) the cutoff frequency well above your band of interest. If you are using this in the ~1 GHz region where FR4 is normally considered suitable, chances are that the effect is small and can be corrected in this way.You can remove the middle ground planes near the connector. Effectively launch to a microstrip between the top and bottom layer, then transition to the desired waveguide with a properly engineered transition. If you have a good RF board (i.e., not a cheap JLCPCB prototype) you can do pretty well with this, especially if you are willing to characterize the process carefully and iterate the design.One cute trick is to try to keep the ground currents from having to hop planes. For instance, if you cut away the plane on layer 2 near the connector you have a microstrip between layers 1 and 3. On a normal PCB you will still be able to have a reasonable geometry in this configuration although you have to work to make sure that the connector ground properly contacts layer 3. Then you use a via from layer 1-4 to transition to a much smaller bottom layer microstrip still referenced to layer 3. Since the ground current doesn't have to hop planes (technically it moves from the top side to bottom side of the same copper) you get a compact and high performance transition.

author: metebalci
author_rank: Frequent Contributor
timestamp: April 12, 2021, 06:27:17 am
content: Many thanks for the replies. I can ask more questions nowQuote from: T3sl4co1l on April 11, 2021, 09:39:43 pmI have a toy project to study and/or practice different topics, a pulse generator. At the moment I am at 500ps rise time, I would like to push this up to 100ps at least. So if I am correct, I am looking into 1Ghz, then up to 5Ghz bandwidths.Quote from: T3sl4co1l on April 11, 2021, 09:39:43 pmLet me repeat what you say to see if I understand it correct. Because the center pin/pad is larger than the trace, and if that cannot be changed, I can change the distance to keep the impedance same. So normally I have traces on top, the reference copper plane at layer 2, and copper plane also at layer 4 just because of the connector. So, for example, if I look at the cinch's table for 1.6mm board, I can make an empty area in the copper plane at layer 2 at (or close) the connector pads, and then use the copper at layer 4 for the microstrip of the center pin/pad. Did I understand this correct ? and just by doing this if it works up to 10 Ghz or so, that is very OK.I just started looking into simulations, sonnet lite at the moment. Happy to hear if you have any recommendations on this, as I am a bit confused, I think not many software are free, and traditional FEMs seem to me a bit complicated to use only for this purpose.Quote from: ejeffrey on April 12, 2021, 05:34:56 amI have built a prototype and it is OK up to ~500ps rise time, and then I wanted to move this into PCB. My first try was >1ns, I realized I forgot something but meanwhile I realized this SMA connection issue (I had pigtail SMA not a connector on the prototype) so I want to have my second try addressing it as well, hence this question.I have an oldish TDR meter (CSA803C), I can see (I think) at the pad it decreases to ~16ohm (the blue dip in the attached photo). What do you mean exactly to add series inductance to this ?Quote from: ejeffrey on April 12, 2021, 05:34:56 amOK, I think then I understood what Tim and you said correct (which I repeated above). I am not planning to use any special material for the board, since this is just a toy project, and until I understand all the issues, but I dont know what I am saying as I dont know the limit of FR4. If 100ps/5Ghz is not doable with "normal" FR4, I would love to hear this.Quote from: ejeffrey on April 12, 2021, 05:34:56 amNormally I just keep layer 2 (for the traces) and bottom layer full copper (for the connectors, no particular reason I make it a plane). So what you (and Tim) describe:- I keep layer 2 as copper plane for traces, but make an empty region at the connector to have pad/center pin referenced to another layer (lets say to bottom layer).- I dont use layer 3, so I just keep it empty=no copper ?- I keep layer 4 as copper plane or just a copper region around the connector ? I have layer 1-4 vias at connector and other places connecting layer 2 and layer 4. Do I need more connections/more vias between layer 2 and layer 4 ?

author: metebalci
author_rank: Frequent Contributor
timestamp: April 12, 2021, 11:10:19 am
content: I think I managed to make a simple simulation. In the order of pictures attached.1) I simplified the board and kept just the connector and terminated it. Normally it is terminated by a line driver opamp.2) TDR measurement, the dip is there as before.3) s11 measurement up to 3Ghz. -6dB at 1Ghz.4) Geometry at sonnet, the one above is almost exact as my board, the one below is just the microstrip. The dielectric, metal layer and their thickness etc. I made as similar as possible to my PCB.5) Simulation result. s11 is quite similar to what I measured. Not sure still how to quantify but microstrip (port 3) looks OK.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 12, 2021, 01:50:36 pm
content: Yeah, I think you've got the idea. Also pay attention to vias, I would suggest something like this: red is top copper, blue is vias.Layers 3 and 4 can be solid over the area (with no gap for the trace that's not there), with layer 3 being optional (just, whichever layer you're using for ground here). Layer 4 should have ground regardless, to help out the bottom side pads.The pours serve double duty of making wider overlap, so that the wavefront spreads out over a wider cross section (small planes top and bottom), and covering multiple vias up close, doubly ensuring low ground impedance.For solderability, the pads can connect with spokes, maybe not the usual pattern from the pad center, but a custom pattern drawn with traces would do.I wouldn't be shy about via-in-pad for a component that is very obviously hand soldered only.Vias in general (at least in this area) are looking awfully weedy, those long and thin traces going to them -- if those are mostly/all ground or VCC, this is a well deserved improvement: bring them in closer, use fatter traces, and use multiple vias around the pads. Use smaller components as well, invest in 0402 chips and QFN/SON/DFN/CSP ICs. Hot air is cheap enough, if you're not using it already it's well worth it.Tim

author: metebalci
author_rank: Frequent Contributor
timestamp: April 12, 2021, 03:05:22 pm
content: Quote from: T3sl4co1l on April 12, 2021, 01:50:36 pmOK great, and I can make it something similar to this. It I think starts to look like coplanar waveguide, which makes me question shall I use that or microstrip. I dont think I know the difference, when/why to use which.Quote from: T3sl4co1l on April 12, 2021, 01:50:36 pmBy spokes, do you mean what is called thermal relief at least in kicad ? limiting connection to copper I believe to make it easier to solder ?Quote from: T3sl4co1l on April 12, 2021, 01:50:36 pmThis was another topic I was uncertain and particularly looked for examples when designing the PCB, I think most of the places I looked they were avoiding vias in-pad so I followed the same route but I dont know the exact reason behind.Quote from: T3sl4co1l on April 12, 2021, 01:50:36 pmJust to give you context -:)- it is the first PCB I have ever designed and I am very new to working with SMD components, so I am trying to be at the safe side still, and not using hot air yet. I will make the power traces as you said and try smaller components maybe not immediately but soon I guess. Probably I should look for hot air tools too.I like sonnet lite for simulation, I will try to simulate the microstrip-connector pad section as I understand on this thread.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 12, 2021, 04:46:42 pm
content: Quote from: metebalci on April 12, 2021, 03:05:22 pmYes, quite. Note the edge coupling is quite small, so the ground being within, even pretty close (say 1/4 the substrate height), doesn't amount to all that much (-10-15% impedance?).Also it's unavoidable at the connector itself, for obvious reasons.Doesn't matter, it's just more or less ground copper around the signal -- vary distances and widths as needed to keep the impedance where you want it.QuoteYes, exactly. What I would do [in Altium] is, I think, set a rule to no-connect those footprint pads, then draw in the traces manually. Or add the traces to the footprint. Or instead of a no-connect rule, maybe use a polygon cutout.The specific rule would be polygon pad connect, which can be set to none. I don't know what KiCAD has for that...QuoteYeah, it's not recommended for reflow soldering, particularly in blind (LGA/BGA) pads, unless absolutely required (e.g. thermal pads). Do not tent the backside, that will trap gasses, ensuring a hollow via (and probably voids in the soldering area as well). Or tent both so nothing gets in there at all, but most times that's impractical (you'd need to make an island of soldermask in the middle of a pad -- a PITA in most tools, and still questionable to fab).Gold standard is any planar technology: plugged, capped or HDI (micro lasered vias plated shut, among other things), where you get the connection without voids (or at worst, a small divot that fills with solder anyway). These are added cost though.Ordinary vias also suck up some solder, which can upset the balance in reflow... but with hand soldering you can just keep feeding it until it's got whatever fillet you desire, so that doesn't matter a lick.Oh also, the problems with via-in-pad (voids) are mitigated when there's a lot of 'em: maybe not all are voided. So, thermal vias aren't so bad. Because "vias" plural...https://imgur.com/gallery/NxgEkoQ("We're allowed to have one"... or actually it works kinda the other way around in this case.)QuoteEven just 0603s and such, will have some improvement. You're talking frequencies well beyond "first ever PCB". Fortunately PCB fab is cheap as printer ink*, you can afford rapid iteration.*Wait, significantly cheaper. What the hell...Tim

author: metebalci
author_rank: Frequent Contributor
timestamp: April 12, 2021, 05:04:04 pm
content: Quote from: T3sl4co1l on April 12, 2021, 01:50:36 pmI forgot to ask this. You mean there is a single pad, and lets say three vias each at 90deg around it. Is this only for nets related to power, decoupling cap etc. ? I read about this but not sure when to use etc.

author: metebalci
author_rank: Frequent Contributor
timestamp: April 12, 2021, 05:08:06 pm
content: Quote from: T3sl4co1l on April 12, 2021, 04:46:42 pmEnjoying the challenge

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 12, 2021, 06:09:01 pm
content: Simply, whenever you need low impedance to ground. Which if you're talking many GHz, doesn't need much.Think of the component pads and body as a microstrip of whatever width (and height, for whatever effect that has; don't worry about it, for the most part). Body, trace and via length all add up to the total stub length of that bypass. So, it's real easy to get several mm, or whatever LF-equivalent ESL that amounts to (about as many nH).Hence, smaller components, and also shorter height above ground plane, keeps the stub length down. Multiple vias in parallel act to widen the path to ground, reducing Zo, reducing LF ESL correspondingly.I keep the distinction between LF equivalent ESL, and transmission line properties, as it doesn't take many harmonics into the GHz before that stub really does look like a stub, with peaks and valleys in its impedance, not just the asymptotic impedance we use at lower frequencies. When you don't have significant harmonics or gain at those frequencies, it is okay to use the LF equivalent.Same as the 1/10 λ rule, or some related fraction, you often see quoted for consideration vs. ignorance of transmission line effects. Or in general, including mismatched impedances, it's the mismatch ratio below that. Which is why for example, a switching converter with harmonics at 100MHz, cares about mm's of loop length: its impedance might be a few ohms, so compared to the maybe 20 ohm layout, that's a factor of 10 or so working against it.Tim

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: April 13, 2021, 01:52:09 pm
content: You can sometimes improve the performance by adding a notch in your ground under the connector. This reduces the parasitic capacitance of your pin.The same can be done with SMD footprints. It does two things: the cut underneath a pad reduces the parasitic capacitance of the pad, and adds a slight bit of inductance to tune out the remaining capacitance. I've done this a lot with vias on-PCB at higher frequencies.

author: metebalci
author_rank: Frequent Contributor
timestamp: April 13, 2021, 08:17:34 pm
content: I made a simulation just with the cut under and it is much better at least until 4Ghz comparing to before, at least on paper. This I think might be my next try. (blue s11, pink Zin)I wonder why there is a big change after 4Ghz. Do you know ?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 13, 2021, 09:07:28 pm
content: How long is the wide pad, about 7.0mm?Tim

author: metebalci
author_rank: Frequent Contributor
timestamp: April 14, 2021, 04:53:01 pm
content: geometry is attached, in mils

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 14, 2021, 08:50:34 pm
content: Ah, and what's the substrate height?Wait, is that not just series resonant between the thin trace and the thick pad? The thin trace is the one thing not dimensioned but it looks suspiciously close to what I just said...Tim

author: metebalci
author_rank: Frequent Contributor
timestamp: April 17, 2021, 04:46:52 pm
content: I forgot to add the 3d view. So the 2D geometry above is the first metal. the substrate below is 7 mil and then the substrate to bottom is 55 mil. The thin trace from large pad to small pad is 10mil.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 17, 2021, 05:58:11 pm
content: Ah yeah. Keep opening it up, maybe add some vias nearby to make that more representative (the sim volume may need to grow?). Oh, is ground boundary condition all around the edges, or what..?Tim

author: metebalci
author_rank: Frequent Contributor
timestamp: April 18, 2021, 10:54:23 pm
content: I dont know too much about the software yet but all stays inside a metal box and edges are touching to metal sides, so all same potential I guess. The top layer, where the ports are, have ports between the metal/copper and the metal side. It is difficult to make sth more complicated than this with the free version I think.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 18, 2021, 11:34:23 pm
content: Makes sense. So that should be roughly equivalent to having a via fence at that distance. Keep this in mind as the simulated volume is about as wide as it is tall, those sides will have significant effect on the result.Tim