Power supply output ripple issue - Page 1
Forum section: electronics / beginners

author: tvtv
author_rank: Newbie
timestamp: February 05, 2013, 11:33:37 am
content: I built a simple power supply based on thisthisschematic. TR2 is replaced with IRF540 and TR1 is replaced with BC546. Opamp and everything else is pretty much the same as on original schematic. The regulator works, but in CV mode it has a ~10mV p-p ripple at output (100Hz base frequency). Input ripple is ~200mV p-p. I CC mode the ripple is around 10 mA p-p.I cannot track down the cause of this. Also, simulator (LTSpice) is not showing anything that even remotly resembles such output. So I am clearly missing something here. By simlation the PSRR should be 80dB and I cannot see any problems with simulated loop gain either. Any hints?

author: Kremmen
author_rank: Super Contributor
timestamp: February 05, 2013, 11:53:51 am
content: I didn't check all the amps in detail for gains and operating points, but let's assume that it is a working circuit., It does look like one at arm's length.The first suggestion is that you are picking AC or rectified AC ripple from the power input circuitry into a sensitive signal line somewhere. If the ripple shows equally under voltage and curent control, then my primary suspect would be the area aroiund TR1, or some common factor in the quad op amp. Supply voltage would be one common denominator but the ripple would have to be huge to show like this through the amp PSRR.Do you have pictures of the board layout and general constructiuon of the PSU?

author: HackedFridgeMagnet
author_rank: Super Contributor
timestamp: February 05, 2013, 12:20:53 pm
content: Some more questions:How does it behave loaded and unloaded?Is the 100hz exactly 100hz or not really a harmonic of the mains.Is the ripple also 100hz for the current mode?QuoteIs this on top of the mains??? I am not sure what you mean here.Now I see it, you mean after the full bridge rectifier. Is that correct?

author: tvtv
author_rank: Newbie
timestamp: February 05, 2013, 01:56:13 pm
content: Sorry, I cannot post the pictures until I get home. The numbers below are for 7.5V @ 100mA. At 200mA the result is more or less the same. I have not tested it on higher currents yet (need a bigger heat sink for that, but I will carry out that test).About noise pickup. I moved the PCB away from transformer, but no changes. No measurable ripple on opamp and TR2 gate drive supply.By input ripple I mean the AC component on drain of TR2. The output ripple correlates with input ripple, but the waveforms are different. Frequency of the ripple is the same for CV and CC mode. I think that loop is somehow excited by the input and thus the pumps and valleys that repeat after 10ms. I try to get pictures. Also I try to feed it from a NIMH battery back to see how it behaves when the input is smooth.

author: robrenz
author_rank: Super Contributor
timestamp: February 05, 2013, 04:07:23 pm
content: IMO if you are not using a differential amplifier to measure the ripple you are chasing your tail. There is too much common mode noise everwhere. See the HP/Agilent power supply handbooks for power supply PARD measurement techniques.

author: Kremmen
author_rank: Super Contributor
timestamp: February 05, 2013, 10:11:57 pm
content: The battery supply is a good idea. If the ripple persists you know it is a feedback loop instability issue, not an EMI issue. And vice versa of course. Let us know.

author: amspire
author_rank: Super Contributor
timestamp: February 05, 2013, 11:40:56 pm
content: It can easily be the design. When I see 0.1uF caps across opamps in a supply regulator, it usually means that the designer couldn't get it stable and so they went for the industrial-strength sedative approach. Ideally you want a fast regulator so it can quickly compensate for transient load changes which means you want as much loop gain as possible up to at least 10KHz, and that 0.1uF cap will be killing the loop gain at at anything above a few Hertz. If you reduce it to 1nF to speed up the regulator, my guess is that the supply will be badly unstable, particularly with any capacitive load.The feedback circuit time constant on the voltage regulator when the voltage pot is half way is about 10msecs, so ripple is not out of the question.Is the ripple worse when the voltage pot is at mid-way compared to 10% and 90% (with the same output current).You could also try doubling C7 to 200n. Does the ripple double?Here is the problem. The phase shift around the voltage regulator opamp will be around 90 degrees as the freq increases. The capacitance of the mosfet gate drive is driven by a high impedance source, so it will have a phase shift of around 90 degrees. The output capacitor will also be shifting phase by a few degrees making things worse. When the total phase shift hits 180 degrees, you will have instability. The theoretical conditions for instability is a phase shift of 180 degrees and a loop gain of 1, but in practice, there will always be a loop gain of 1 if the circuit has a high DC loop gain and the transient amplitude increases to a point devices can saturate. The instability may not show up in LTSpice if you do not add any transients to trigger the instability.The moral is that getting a supply to have fast regulation and unconditional stability at the same time is hard. The easy solution is to slow the regulation down to the point you have stability but very sluggish transient response.It is easy for slight differences between the simulation and the real circuit to be the difference between stability and instability. In your LTSpice, try adding transient loads on the output (say a transient voltage source connected by a resistor), and also try large capacitors of different values on the output. Look at pin1 of the opamp for any sign of instability under transient conditions (like overshoot, ringing, etc).You can also post the LTSpice files if you want us to take a look.Richard.

author: GK
author_rank: Super Contributor
timestamp: February 06, 2013, 02:04:42 am
content: A real quick analysis:Feedback factor (R23, R24) = 0.4Integrator ULGF = 1/(2pi*((VR2/4)+R21)*c7)) = ~220HzX 0.4 = 88HzAttenuator (r7,r6) = ~0.3X 88Hz = ~26HzDC Gain TR1 stage ~ R2/R4 = 100X 26Hz = 2600Hz.So, the voltage regulator has 0dB of loop gain at ~2600Hz.2600/2 = 1300Hz = 6dB = 2Av1300/2 = 650 = 12dB = 4Av650/2 = 325 = 18dB = 8Av325/2 = 163 = 24dB = 16Av163/2 = 81 = 30dB = 32AvSo, at 100Hz you have a loop gain of ~30 Av.200mV input ripple at 100Hz / 30 = 6.6mV output ripple - however high order harmonics of the 100Hz ripple also contribute so, if I haven't missed anything, your measured 10mV looks bang on target.- crap design. To fix I'd aim for a higher ULGF, Miller compensate the TR1 stage to pole-split the effect of the MOSFET's input C out to ~MHz (yes, really) and finishing off the dominant pole compwith a much smaller C7 when the TR1 stage zero kicks in due to the gm limitation imposed by R4.

author: GK
author_rank: Super Contributor
timestamp: February 06, 2013, 04:48:51 am
content: Quote from: GK on February 06, 2013, 02:04:42 amEDIT:I shouldn't post a very quick circuit analysis just before eating. While the loop gain/unity loop gain frequency calculation should be on target, the ripple rejection should be much higher than measured due to the high intrinsic ripple rejection of the source follower to begin with. I don't think there is anything wrong with the circuit (even so the frequency compensation scheme could be significantly improved as described); there must be something amiss with the implementation.Make sure zener D7 has been properly soldered into circuit/is the right type/isn't blown up; it regulates the supply voltage for the TR1 gain stage and thus the gate voltage for the MOSFET. Without this diode, the source follower would actually have a ripple rejection of about zero, and the output ripple should be pretty much in accordance to your measurements as I've described in the above post (forgetting to factor in the ripple rejection provided by D7).

author: GK
author_rank: Super Contributor
timestamp: February 06, 2013, 10:16:05 am
content: I just noticed another silly oversight in my initial analysis - the CV error amplifier has the feedback signal fed to the non-inverting input; the gain of the error amplifier itself therefore can never be less than 1. This means that the 100nF compensation capacitor can only roll off the closed loop gain a limited amount as there is a zero at ~220Hz.I've attached simplified a loop gain and phase simulation to demonstrate. As can be seen, the loop gain starts rolling off at a low frequency due to the 100nF (C7), but the zero at ~220Hz (the point at which the error amp gain approaches 1) causes the loop gain roll off to plateau "mid band", rather than continuing to a unity loop gain intercept at ~2600Hz. For stability the circuit actually relies on the secondary pole formed by the collector impedance of TR1 (~10k) in conjunction with the MOSFET input capacitance (only roughly approximated here). This pole at ~30kHz finally causes the loop gain to reduce to unity at a rather high frequency of ~200kHz. This isn't a very good design and with such a high ULGF it would be quite easily forced into global loop oscillation by only a moderate capacitive load.Also, that 1M in parallel with the 100nF doesn't do anything useful. It just limits the loop gain at DC to ~60dB, unnecessarily and pointlessly reducing the supplies DC precision. This supply clearly wasn't designed by someone with a complete idea of what he was doing - bit of a "stick a 100nF here" approach and hope for the best.

author: ptricks
author_rank: Frequent Contributor
timestamp: February 06, 2013, 01:20:36 pm
content: One of the most overlooked parts of a supply is the need for placing a large capacitor at the input stage as close as possible to the first switching device.

author: GK
author_rank: Super Contributor
timestamp: February 07, 2013, 06:14:58 am
content: Quote from: ptricks on February 06, 2013, 01:20:36 pmThis is a linear supply.

author: MikeK
author_rank: Super Contributor
timestamp: February 07, 2013, 07:21:53 pm
content: This is a neat little project with a good description. But I'm confused...Should the caps labeled with a "p" suffix actually be "u" for "micro"?

author: tvtv
author_rank: Newbie
timestamp: February 11, 2013, 10:32:45 pm
content: Thank you, everyone. The issue is now solved and ripple is 3mV ptp at 7.5V and 3A. It was a PCB layout problem after all. Capacitor C2 was routed so, that its surge currents added a huge amount of ripple to voltage/current feedback. Dremel and piece of wire fixed the problem. During testing I managed to kill TR2. It happened when the PSU switched to CC mode and my dummy CC load shorted the output to keep current at fixed level. No smoke. This issue needs still some investigation.

author: smashedProton
author_rank: Frequent Contributor
timestamp: February 12, 2013, 06:52:42 am
content: If it's just 200 millivolts that you need to knock dow. Can't you just use a lc pi filter? elegant

author: megajocke
author_rank: Regular Contributor
timestamp: February 13, 2013, 09:29:25 am
content: I see a risk of overvoltaging gate-source on the MOSFET when the output is shorted/voltage decreased rapidly before the control circuit has time to react. A zener over gate-source could solve that.But beware: I played with a circuit using a similar concept before, and found that this particular schematic has especially poor recovery when switching modes due to windup in the control circuit.