What is the actual cost for chips like these? - Page 1
Forum section: electronics / projects

author: jeremy
author_rank: Super Contributor
timestamp: October 25, 2014, 08:07:49 am
content: Hi all,I'm a bit curious about these super high speed ADCs and what makes up their cost. Does anyone have any idea of how much each chip would go for if the NRE was $0? Basically, I'm wondering what just the manufacturing cost is.I'm assuming that the yield would be poor, and the volumes low, so that would push up the manufacturing cost quite a bit. But I don't have any experience with semiconductor manufacturing so I'm not really sure how significant a problem this is.http://www.analog.com/en/analog-to-digital-converters/high-speed-ad-converters/ad9625/products/product.htmlThanks!

author: TonyStewart
author_rank: Contributor
timestamp: October 25, 2014, 08:22:40 am
content: I can't quote exact production costs but compared to high end CPU chips it would be high anytime you combine microwave speed analog with digital using different process steps, with process controls to laser trim each value.12-bit 2.5 GSPS ADC, no missing codesSFDR = 79dBc, AIN up to 1 GHz at ?1 dBFS, 2.5 GSPS

author: tszaboo
author_rank: Super Contributor
timestamp: October 25, 2014, 10:22:23 am
content: Well, this is most likely a flash ADC, which means 4096 analog comparator on the input. That takes up some space. Assuming the 8,2mm*8,2mm die the cost of silicon is not that much though. I think the testing platform costs millions, and they only sell a handful.

author: dannyf
author_rank: Super Contributor
timestamp: October 25, 2014, 12:07:37 pm
content: QuoteNot sure about NRE. I have been in cases where GWE was not terribly XMWE for us but we really wanted MOP for an application in QB89. However, the chips we used wereheavily into MPU4, as such they were not suited for BARP and we had to go with CQF in order to pass MPYR. Fortunately in the end QWER worked out for us.

author: jeremy
author_rank: Super Contributor
timestamp: October 25, 2014, 01:14:28 pm
content: Quote from: dannyf on October 25, 2014, 12:07:37 pmWell if you google NRE, the first result is the definition (on wikipedia). Non-Recurring Engineering. No need to be snarky.

author: coppice
author_rank: Super Contributor
timestamp: October 25, 2014, 02:33:55 pm
content: Quote from: NANDBlog on October 25, 2014, 10:22:23 amI think the clue that this might not be right is the datasheet saying "The AD9625 is a pipelined ADC". Does anyone make flash converters these days? I guess there should be a market for them where latency is an issue.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: October 25, 2014, 02:39:02 pm
content: Test will be a major part of the cost - imagine the gear you need to test gbps converters

author: coppice
author_rank: Super Contributor
timestamp: October 25, 2014, 02:45:46 pm
content: Quote from: mikeselectricstuff on October 25, 2014, 02:39:02 pmRight. Even slowish mixed signal chips carry a heavy test cost. Really fast ones require some seriously exotic testers. Fast DACs are especially nasty for pushing up test costs, much more so than fast ADCs.

author: zapta
author_rank: Super Contributor
timestamp: October 25, 2014, 03:53:42 pm
content: Quote from: dannyf on October 25, 2014, 12:07:37 pmWas it at Rockwell Automation?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 25, 2014, 04:39:41 pm
content: Quote from: NANDBlog on October 25, 2014, 10:22:23 amNah, definitely a pipelined SAR, or something sort-of broadly similar in function. 226 clock cycle pipeline latency wouldn't be very helpful or relevant to implement on a flash converter (certainly, 4096 high speed comparator cells wouldn't be helpful either!), and there'd be no reason to require a minimum clock rate.ENOB is rather disappointing, but these chips are only made for SDR purposes, where INL and distortion aren't exceptionally big deals. (INL and DNL don't look bad in the plots, so I guess most of the ENOB loss is due to noise and AC distortion that doesn't show up in a DC plot.) It's not like there's much absolute-voltage-accuracy DAQ to be done past the MHz, anyway; you always want to be doing analyses to find signals way out there. For example, a 3.2GHz analog bandwidth means this thing is peppy enough to acquire the full 802.11 spectrum.The filter blocks and stuff are pretty neat.As for cost, yeah, probably development and testing. Really big, low quantity chips go up exponentially, so that the biggest FPGAs are in the $10k range(!). That can come down with quantity -- it's amazing that state-of-the-art desktop/server CPUs and GPUs are available for a couple hundred bucks, older ones even less -- even for using the newest, finest and most expensive fabs. Or using the scale advantage as a cost reduction mechanism, like the Intel Atoms which are made with very small feature size, and have very little die area -- it's expensive area, but because it's so dense, it remains cheap (and power efficient besides).But out of that quantity, things go up. For ADCs and FPGAs, moderate scale products will find use -- a friend used to work for ADI as FAE, and some of their biggest accounts were medical: ultrasound and CT scanners with 256 channels per chip, 12 bit and 10MSa+. (Or maybe that was 256 channels per board, I forget.) Slap a few hundred of those in one scanner, then sell a thousand scanners to hospitals around the country, then more throughout the world -- it adds up, fast!Tim

author: jeremy
author_rank: Super Contributor
timestamp: October 25, 2014, 04:50:32 pm
content: Quote from: T3sl4co1l on October 25, 2014, 04:39:41 pmAh, well fortunately this is something I do know about, as it is the area I work in. It's not unusual to see a 16x16 array of ICs on a card. Could be ADCs, could be expensive instrumentation amps. A colleague of mine saved some of these cards from the bin once, each one had several thousands of dollars worth of parts on a board about as big as a 2.5" harddrive.

author: Marco
author_rank: Super Contributor
timestamp: October 25, 2014, 04:51:21 pm
content: Quote from: NANDBlog on October 25, 2014, 10:22:23 amThat's a lot of capacitance to drive. Pipelining, parallel ADCs, lots of design space to explore. How expensive is laser trimming? Is it cheaper to add an extra bit and some prom and calibrate it with a translation table?

author: tszaboo
author_rank: Super Contributor
timestamp: October 25, 2014, 07:05:24 pm
content: Quote from: T3sl4co1l on October 25, 2014, 04:39:41 pmWell, next time I should read the second page... And also I should update my knowledge on high speed ADCs, I was told, everything above gigasample/sec is flash, around it can be still pipelined.Thanks for the clarification.But by SAR, you mean the DAC SAR, not the charge balancer, right?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 26, 2014, 12:51:05 am
content: I don't think I've ever encountered a flash ADC in shopping before; the ones I have seen are usually really low bitcount (and these days, screaming high sample rate). The SAR kind have been climbing in sample rate for decades, and pipelining helps with that.By SAR, I mean charge balancing, yeah... since we're talking all CMOS hardware here, and you don't do the textbook compare-voltage-from-DAC thing, you do compare and dump charge between capacitors. Same thing, different method (and much easier and more precise for CMOS). Suppose I don't know how specific all those terms are.As for laser compensation and stuff... absolutely, why not? It's expensive and high-falootin' enough, probably has more than a few trim hooks inside.Tim

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: October 26, 2014, 03:39:20 am
content: Quote from: jeremy on October 25, 2014, 01:14:28 pmYou must be new to dannyf's posts... It's his schtick, and it's obvious he's NNC (nowhere near as clever) as he thinks he is..."NRE" is like a pretty basic engineering term too.