Delta-Sigma ADC Advantages/Disadvantages?  - Page 1
Forum section: electronics / projects

author: BiOzZ
author_rank: Regular Contributor
timestamp: March 09, 2014, 09:25:28 pm
content: I am looking to build a simple high accuracy low voltage voltmeter and im looking at ADC solutions and i was looking at a delta-sigma style converter, they appear to have on average around 22bits compared to an equal cost 16bit comparator ADC and still get 16+ ks/si have used Delta-sigma converters in audio applications but never in such a precision applications like thislooking at the datasheet i see nothing inherently wrong with doing so and it even looks more resistant to temperature drift (over using a resistor ladder) ... but there has to be a reason why they have not totally taken over comparator ADCsdo they have inherent advantages or disadvantages over a comparator based ADC? how are they with sticking with a precision reference voltage?im not looking for a high sampling rate ... 2 updates a second is more than enough tho i would love the 16ks/s for averagingAnd yes im aware i dont need 22bits for my project but it would be nice to go overkill for both learning and to reduce noise when rounded off

author: hamster_nz
author_rank: Super Contributor
timestamp: March 09, 2014, 09:47:40 pm
content: Not sure what price point you are trying to hit, but this might be a useful as a reference design or for prototyping.https://digilentinc.com/Products/Detail.cfm?NavPath=2,401,1159&Prod=PMOD-AD5

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 09, 2014, 10:27:50 pm
content: Hmm, good question...I think there might be two problems:1. Latency. D-S has no inherent sample-and-hold mechanism, so you can't say "I want to convert the voltage at this instant in time". You can add a S&H, but that requires at least one op-amp with Vos better than the design's accuracy requires (a few LSBs at most).2. Processing. Flash ADCs produce parallel (unary, actually, but this is usually encoded as binary for convenience; a simple exception is LM3914, which is a 10-level flash ADC -- yes, no really, think about it, it is!), and SAR ADCs produce serial (and parallel, on the last clock). It's extra work, for example, to make an SPI ADC anything other than SAR!3. Manufacturing. I don't know the actual logistics of it all, but it could very well be that SAR ADCs are much simpler to build.There are some advantages: CMOS circuitry is good at dumping charge from place to place, so an ADC can be built with a comparator, two capacitors and a handful of analog switches. The first cap is charged to the input, then the input is disconnected when the sample window closes -- you get S&H for free. Depending on whether the first cap is above or below Vref/2, you charge the second cap to 0V or VREF, then short them together -- charge is conserved but the final voltage is halfway between. Next, set the comparator reference to halfway between again (i.e., 1/4 or 3/4) and repeat. After N cycles, you have the complete conversion, and you have the input capacitor charged to the input voltage. (So when the sample window reopens, little current is drawn, and the input looks like a capacitor with switch ESR, drawing little current from the source.)Flash ADCs are relatively uncommon, for obvious reasons I think. Although flash DACs are surprisingly common these days. Evidently, 2^12 identical resistors, paired with 2^12 analog switches, don't take up much real-estate on modern processes -- they certainly don't cost much if any design time, all that layout and stuff is fully automated.Whereas a D-S ADC needs a couple key features: a very good integrator, a very good 1-bit DAC (i.e., analog switches to VREF+ or VREF-), and some digital support logic, including a high speed counter and enough interface logic (for parallel or serial; raw code output of course just needs the output buffer). Back in the day, capacitors were one of the most expensive components on an IC; the couple pF compensation cap inside a 741 took something like a quarter of the die area. And that wasn't very linear, IIRC it was MOS type.If nothing else, the converter has to have at least a low Vos op-amp, so it's going to cost at least as much as one of those (~$5). The integrator cap might be extra, how much I don't know. Suppose there might be layout area for keeping the noisy digital stuff away from the integrator and comparator too, I don't know. The interface logic needn't take much space I would think, as it can be very small stuff right up to the pin driver devices. But overall, I mean, what do these devices usually cost, the >20 bit, >10kSa/s, SPI or whatever chips -- 5-10 bucks? So, that would sound about right.Now... for a voltmeter, D-S works in your favor, because it naturally filters (rather than aliases) higher frequencies. In fact, if you can adjust the counting window to be a multiple of line frequency (like 10Hz), you can even eliminate line noise and ripple from your measurements. The only thing better is a dual (or multi) slope converter, which as far as I know is standard in pretty much all voltmeters.As far as things to know, it utterly comes down to precision components and low EMI and low offset layout. Eliminate ground loops, stuff like that.Tim

author: SArepairman
author_rank: Frequent Contributor
timestamp: March 10, 2014, 12:26:39 am
content: I read a bunch about this, but I think that this pretty much sums it up"s. On the application level, how do you differentiate between these converters? SAR converters suit applications that require fast response and low latency, such as high-speed control loops and multichannel data-acquisition systems. Delta-sigma converters target applications that require high resolution, such as scales or audio systems. However, both types of converters find use in motor control, sonar, and vibration analysis, which require precision, wide bandwidth, and high-resolution operation."This article is really good :http://www.cypress.com/?docID=22143and this article has a nice diagram that I likehttp://www.analog.com/library/analogdialogue/archives/39-06/architecture.htmlPersonally I feel more comfortable with a fast SAR ADC using over sampling to get more bits resolution if necessary, so you can always play around with your speed/resolution ratio in MCU code.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 10, 2014, 12:35:44 pm
content: Note that D-S doesn't need oversampling or AA filters*, because it does it for free. The counting window is your oversampling. Note you could use a sliding window to achieve a boxcar response (though you need 2^N bits of memory to do it for a N bit window!), or any other windowing method as desired.*At least, at the rate of the counting window. At frequencies closer to the clock rate, I'd be as concerned about RF rectification in the op-amp as aliasing to the clock rate. With orders of magnitude between window and clock, an RC filter, maybe a ferrite bead thrown in, will do the job.Note also you can do D-S with more than 1 bit DACs (and ADCs). Add the external hardware (integrator and feedback loop) and loop a DAC into the conventional ADC and you've got a N bit D-S ADC; the main difference in response here is, I think, you get dithering for free (the integrator is constantly hopping around a range of codes), as opposed to a white noise dither which gives statistical results (sidebands are scattered, but the noise floor drops slowly), or a subtractive dither, which requires an external signal (but the response, I think, will be equivalent?). Since the input is being compared to the DAC, using an ADC to approximate the signal, the resolution depends on the DAC, which better have some damn good INL to be useful. (A 1-bit DAC doesn't have INL or DNL, only absolute error. On the downside, a rapid clock rate makes the DAC's risetime an important parameter as well.)Tim