32-bit ALU getting "UUUU" as result - Page 1
Forum section: electronics / beginners

author: liulol177
author_rank: Newbie
timestamp: November 02, 2014, 03:45:21 am
content: I've been trying to make this 32-bit ALU using "generate". However in the simulation I got "U"s for both cout and ouput.ALU design and its test bench are below.-------------------ALU CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;ENTITY alu_32bit ISPORT (A : IN STD_LOGIC_VECTOR (31 downto 0);B : IN STD_LOGIC_VECTOR (31 downto 0);cin : IN STD_LOGIC;opsel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);mode : IN STD_LOGIC ;output : OUT STD_LOGIC_VECTOR (31 downto 0);cout : OUT STD_LOGIC);END alu_32bit ;architecture Behavioral of alu_32bit isSIGNAL N: STD_LOGIC_VECTOR (32 downto 0);SIGNAL C: STD_LOGIC;beginC<='1' WHEN ((mode='0') AND (opsel="001")) ELSE'1' WHEN ((mode='0') AND (opsel="110")) ELSEcin;N(0) <= '1';gen: FOR i IN 0 TO 31 GENERATEN(i+1) <= '0';--Addoutput(i) <= ((NOT A(i) AND NOT B(i) AND C) OR (NOT A(i) AND B(i) AND NOT C) OR (A(i) AND NOT B(i) AND NOT C) OR (A(i) AND B(i) AND C)) WHEN ((mode='0') AND (opsel="000"));C <= ((NOT A(i) AND B(i) AND C) OR (A(i) AND NOT B(i) AND C) OR (A(i) AND B(i))) WHEN ((mode='0') AND (opsel="000"));--Sub w/ borrowed carryoutput(i) <= ((NOT A(i) AND NOT B(i) AND C) OR (NOT A(i) AND B(i) AND NOT C) OR (A(i) AND NOT B(i) AND NOT C) OR (A(i) AND B(i) AND C)) WHEN ((mode='0') AND (opsel="001"));C <= ((NOT A(i) AND NOT B(i) AND C) OR (NOT A(i) AND B(i) AND NOT C) OR (B(i) AND C)) WHEN ((mode='0') AND (opsel="001"));--Moveoutput(i) <= A(i) WHEN ((mode='0') AND (opsel="010"));--Suboutput(i) <= ((NOT A(i) AND NOT B(i) AND C) OR (NOT A(i) AND B(i) AND NOT C) OR (A(i) AND NOT B(i) AND NOT C) OR (A(i) AND B(i) AND C)) WHEN ((mode='0') AND (opsel="011"));C <= ((NOT A(i) AND NOT B(i) AND C) OR (NOT A(i) AND B(i) AND NOT C) OR (B(i) AND C)) WHEN ((mode='0') AND (opsel="011"));--Incrementoutput(i) <= ((NOT A(i) AND NOT B(i) AND C) OR (NOT A(i) AND B(i) AND NOT C) OR (A(i) AND NOT B(i) AND NOT C) OR (A(i) AND B(i) AND C)) WHEN ((mode='0') AND (opsel="100"));C <= ((NOT A(i) AND B(i) AND C) OR (A(i) AND NOT B(i) AND C) OR (A(i) AND B(i))) WHEN ((mode='0') AND (opsel="100"));--DecrementC <= ((NOT A(i) AND NOT N(i) AND C) OR (NOT A(i) AND N(i) AND NOT C) OR (A(i) AND NOT N(i) AND NOT C) OR (A(i) AND N(i) AND C)) WHEN ((mode='0') AND (opsel="101"));--Add & Incrementoutput(i) <= ((NOT A(i) AND NOT B(i) AND C) OR (NOT A(i) AND B(i) AND NOT C) OR (A(i) AND NOT B(i) AND NOT C) OR (A(i) AND B(i) AND C)) WHEN ((mode='0') AND (opsel="110"));C <= ((NOT A(i) AND B(i) AND C) OR (A(i) AND NOT B(i) AND C) OR (A(i) AND B(i))) WHEN ((mode='0') AND (opsel="110"));--Bit-wise ANDoutput(i) <= (A(i) AND B(i)) WHEN ((mode='1') AND (opsel="000"));--Bit-wise ORoutput(i) <= (A(i) OR B(i)) WHEN ((mode='1') AND (opsel="001"));--Bit-wise XORoutput(i) <= (A(i) XOR B(i)) WHEN ((mode='1') AND (opsel="010"));--Complimentoutput(i) <= (NOT A(i)) WHEN ((mode='1') AND (opsel="011"));--32-bit shift leftoutput <= (A(30 DOWNTO 0) & '0') WHEN ((mode='1') AND (opsel="101"));end GENERATE;cout <= C;end Behavioral;-------------------ALU test bench CODE:--Modified from 1-bit ALU test benchlibrary ieee;use ieee.std_logic_1164.all;ENTITY ALU_32tb ISEND ALU_32tb;ARCHITECTURE TEST OF ALU_32tb ISCOMPONENT ALU_32bitPORT (A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);B : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;cin : IN STD_LOGIC;opsel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);mode : IN STD_LOGIC ;output : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;cout : OUT STD_LOGIC);END component ALU_32bit;SIGNAL cin_tb, mode_tb: STD_LOGIC;SIGNAL A_tb, B_tb: STD_LOGIC_VECTOR (31 DOWNTO 0);SIGNAL opsel_tb: STD_LOGIC_VECTOR (2 DOWNTO 0);SIGNAL cout_tb: STD_LOGIC;SIGNAL output_tb: STD_LOGIC_VECTOR(31 DOWNTO 0);BEGINalu_INST: ALU_32bit PORT MAP(A => A_tb, B => B_tb, cin => cin_tb, opsel => opsel_tb, mode => mode_tb, output => output_tb, cout => cout_tb);TB: PROCESSBEGINmode_tb <= '0'; --arithmetic operationA_tb <= "10100101111000001110101111001110";B_tb <= "10001101011010101110111000010100";cin_tb <= '0';opsel_tb <= "000"; --addwait for 10 ns;opsel_tb <= "001"; --sub with borrowed carrywait for 10 ns;opsel_tb <= "010"; --movewait for 10 ns;cin_tb <= '1';opsel_tb <= "011"; --subwait for 10 ns;opsel_tb <= "100"; --incrementwait for 10 ns;cin_tb <= '0';opsel_tb <= "101"; --DEcrementwait for 10 ns;cin_tb <= '1';opsel_tb <= "110"; --add & incrementwait for 10 ns;cin_tb <= '0';mode_tb <= '1'; --------Logic operations starts at 70nsopsel_tb <= "000"; --ANDwait for 10 ns;opsel_tb <= "001"; --ORwait for 10 ns;opsel_tb <= "010"; --XORwait for 10 ns;opsel_tb <= "011"; --NOTwait for 10 ns;opsel_tb <= "100"; --SHLwait for 10 ns;assert false report "finish" severity failure;END PROCESS;END TEST;I don't know how to attach the waveform picture.Please help I've been modifying my code for hours but still don't know what's wrong w/ the code.I'm really new to VHDL.Thanks.

author: Dago
author_rank: Frequent Contributor
timestamp: November 02, 2014, 06:37:11 am
content: You are not setting you variables to any defined state at any point. You need a reset condition which resets all the variables to a known state ('U' means uninitialized).