Looking for help regarding TFT timing signals - DE vs Hsyn/Vsyn - Page 1
Forum section: electronics / projects

author: rfdes
author_rank: Regular Contributor
timestamp: October 15, 2025, 05:14:23 pm
content: Hi -I would appreciate some help from someone who is an expert in TFT timing specifications. I need clarification inregards to DE (Data Enable) mode and Sync mode. It seems clear enough but I am finding conflicting information thatis confusing me. In sync mode, the TFT panel uses only the horizontal and vertical syncs to provide the required timing.The DE signal is not needed. In DE mode, the horizontal and vertical signals are not needed. This is where I am confused,some references appear to state that some TFT panels require all 3 signals. In some instances only the DE and verticalsync signals are needed. I have a Sharp TFT panel from around 1997 time frame that I am having trouble getting to work.Due to a lack of datasheet(LQ10DS05) which I cannot find anywhere, I am in the dark.I only have the interface pin out for my Sharp display (800x600 TTL). It indicated that a DE pin is present as well as the V/H syncpins. There is no pin present for selecting either DE or Sync mode. If anyone could point me in the correct direction, itwould be appreciated.ThanksJim

author: Nominal Animal
author_rank: Super Contributor
timestamp: October 15, 2025, 08:40:41 pm
content: Some displays use the full set: Dot clock (2), Data Enable (37), HSync (4), VSync (5), plus the RGB data signals; the numbers in parentheses are the ones I have for Sharp LQ10DS05, but I haven't seen an actual datasheet for it. HSync, VSync, and DE are often active-low, with DE asserted only for displayed pixels.Some displays do not need Data Enable, and use Dot Clock, HSync, VSync, and RGB only. They have internal registers to identify the number of dot clocks between HSync and horizontal active, and the number of scan lines between VSync and vertical active. This is often called "sync mode".Some displays use Dot Clock, Data Enable, and RGB only. As DE is asserted for visible pixels only, a short non-asserted DE period occurs between scan lines, and a longer period between frames. In some ways, it is more robust for digital displays, and much easier to support from devices without hardware peripheral support (in that you can use RGB555, and the MSB for DE, with a larger framebuffer with border areas corresponding to the periods, and just use DMA to a 16-bit parallel GPIO port with an associated clock signal). For a 800×600 display, something like 896×624 buffer often suffices (but would require a 1,118,208-byte buffer for RGB555 output).So, as far as I understand, as a hobbyist who plays with various smaller displays, among "parallel RGB"-type displays, there are actually three different types, with some displays capable of supporting more than one depending on strapping pins, often sampled only during startup.I'd hate to try and use LQ10DS05 without a datasheet. I always look for the datasheet first, and only buy displays that either I already have the datasheet for, or the vendor/distributor/seller promises to provide one with the purchase. I do believe many/most vendors and distributors selling these at e.g. Alibaba do have the datasheet, but will likely provide it only if you buy a display from them.I could find a datasheet forLQ104S1DG21with a pinout that matches, indicating that DE pin (37, "ENAB") is also a bootstrapping pin, and is active-high (unlike sync signals, which are active-low); and that display should be driven within 10ms after VCC has reached 2.8V. If DE is tied down, LQ104S1DG21 uses "sync mode", with horizontal active starting 88 clocks after end of HSYNC. Its vertical active starts on line 23, regardless of mode.If LQ104S1DG21 is sufficiently similar to LQ10DS05 (and it just might be), then tying DE (ENAB, pin 37) down and running the display using ~ 40 MHz dot clock, HSync, VSync, RGB Data, with 920 to 1056 dot clocks per scan line, 88 clocks before and 32 to 168 clocks after horizontal active between horizontal syncs, four-line vertical sync period, 628 to 796 lines per frame with active data starting on line 23, and thus 1 to 169 inactive lines after vertical active portion before next vsync period. All signals use 3.3V logic, HSync and VSync active-low, with the display sampling the data signals 3ns before to 5ns after a falling edge of the dot clock. Again, no guarantees, only a best guess based on extrapolation from the closest similar Sharp display model I could find the datasheet for.

author: rfdes
author_rank: Regular Contributor
timestamp: October 17, 2025 12:39:55 pm
content: Thank you for your valuable input.Yes, I agree about procuring the datasheet prior to selecting the display panel. However, in my case this was a NOS freebie from a friend. I am trying to fit it into a piece of test equipment that has a defective screen. Although this is a noncritical piece of equipment for hobby use, I am welcoming the challenge of tweaking the bios to support this panel. I've done this in the past with another TFT panel.You are likely right that the datasheet you discovered is similar to my display and that should provide me some insight.Thanks again for your thorough explanation.Take care - Jim