I dont understand type 3 compensation in error op amps - Page 1
Forum section: electronics / projects

author: MacIntoshCZ
author_rank: Regular Contributor
timestamp: February 16, 2023, 08:18:34 pm
content: Hello i just dont understand why every circuit use non inverting input of error op amp for voltage reference and inverting input is connected to voltage divider just as shown in figure 7.If i do so with tl494, it simply does not work. Well it works when when vref is 0V...I need to switch inputs to make it operate.This is my aproach. Look at block diagram of TL494When reference voltage is set at error op am inverting input by potentiometer (voltage set by user) and voltage on non inverting input is lower than Vref (V+ has voltage from voltage divider across load on output) than logic output is LOW. That means non inverting input of PWM compator has 0V which is lower than 0,7V so output voltage of PWM comparator is again ZERO and clock is not halded which result in transistors switching. But when V+ is higher than V-, than output of error op amp is in high state, which result in halding clock signal at "OR", becouse there will be always one input in logic high.Now i am really confused. Why its on every schematic i have seen inverted? M3.png is what is working for me. Op amp used is error op amp inside tl494.Can someone explain to me what is going on? Thanks very much

author: ajb
author_rank: Super Contributor
timestamp: February 16, 2023, 10:51:08 pm
content: When we talk about negative or positive feedback, it's important to consider the entire feedback loop, not just a single stage of that loop. Consider a simple linear voltage regulator made from an op-amp and a high side pass transistor. If that transistor is an N-channel FET, then the transistor is non-inverting: increasing the voltage at the output of the opamp/gate of the FET increases the output voltage. So you would take your feedback from the output from the non-inverting transistor back to the inverting input of the op-amp to provide negative feedback. Now change that transistor to a P-channel FET. As the voltage at the gate increases, output voltage *decreases*, so the transistor now inverts the op-amp output. As a result, taking feedback from the inverting output of the transistor back to the inverting input of the opamp results in *positive* feedback because the two inversions cancel out. Instead, you would need to route the feedback from the output of the transistor to the *non-inverting* input of the op-amp to keep the feedback negative. (There are other implications for the choice of P vs N channel FET here, but we don't need to worry about them for this example.) The same thing applies if you have a chain of inverting amplifiers of any sort--you always need an odd number of inversions in the feedback path because an even number would cancel out.Similar thing here. When the output of the error amp goes high it inhibits the PWM signal, so the connection between the error amp and the PWM section is inverting, which means you need to route feedback from the output of the converter to the non-inverting input of the error amp to maintain negative feedback. The tricky bit is that you have compensation elements going from the output of the error amp back to its input. These do NOT include the extra inversion of the PWM stage, so they need to stay connected to the inverting input. If they came from the output of the converter they would also need to move to the non-inverting input.

author: MacIntoshCZ
author_rank: Regular Contributor
timestamp: February 17, 2023, 10:28:35 am
content: Thanks for explanation. Can someone specify more on compensation connected from output of error op amp to inverting pin? (R+C) parralel to CLet say there will be isntead of one 5k6 potentiometer, so dv/dt will be coupled to the output of error op amp. When voltage change would be positive (increasing resistance on 5k6 resistor/ potentiometer) than it actually could skip some clock pulses becouse voltage on output will be higher than ramp voltage of oscillator, again OR in logic HIGH.I have found this schematic at danyk.cz

author: ajb
author_rank: Super Contributor
timestamp: February 18, 2023, 01:09:54 am
content: I think you'd have a hard time spinning a potentiometer fast enough to cause an appreciable dV to couple through the compensation network. The feedback node is pulled low by a 0.7mA current sink which you'd have to overcome to, it's not just the high impedance input to the comparator.