Is here any speed difference in MidRange FPGAs from different manufacturers ?  - Page 1
Forum section: electronics / general

author: Miyuki
author_rank: Frequent Contributor
timestamp: October 05, 2020, 09:14:51 am
content: Hi,just wonder if is any big difference between common MidRange FPGAsLike if I have same design in Cyclone IV/V, Artix 7 or ECP5Will there be any difference on cost and performance ?Or is it just a personal preference ?

author: asmi
author_rank: Super Contributor
timestamp: October 05, 2020, 01:51:59 pm
content: None of those FPGAs are midrange. This is the low end.As far as performance goes, Artix is the fastest of those listed, followed by CV and ECP5, which are approximately the same. Also Xilinx allows you to utilize the full potential of Artix chips for free, while others are not nearly as generous. ECP5 is on the ridiculous end of this, when you can use everything on a chip for free, except transceivers - this you will need to pay money for. Also Xilinx is the only one which offers a ton of free IPs to use with their devices, like DDR2/3 memory controllers, while other vendors want you to pay for it. It's not that big of a deal for commercial customers (as $3k/year is not a serious amount of money), this is definitely a pass for hobbyists and other cheapskates.As for the personal preference, familiarity goes a long way in this business, but they are not THAT different unless your designs ride on the bleeding edge of performance and thus will force you to optimize your designs for specific FPGA architecture. This only applies to "fabric" designs, if you want to utilize hard IP blocks or specific IO block features (like SERDES for example), then these are obviously differ quite a lot across FPGA families.

author: Miyuki
author_rank: Frequent Contributor
timestamp: October 05, 2020, 03:31:59 pm
content: Oh licencingI totally forget that they want not just to pay for devices but also to let them use itThis make big difference for hobby and low volume (10s of devices year) productionbtw low end is by me more in sub 10$ devices, I am targeting for lower mainstream when I want to use PCIe/SerDes and 64/72bit external DRAM

author: filssavi
author_rank: Frequent Contributor
timestamp: October 05, 2020, 03:58:12 pm
content: Quote from: Miyuki on October 05, 2020, 03:31:59 pmUnfortunately in the FPGA world this is not the case, when talking talking low volumes (up to at least few thousand parts per year) the families of devices that offer sub 10$ parts can be counted on the digit of a single (few lattice ice 40, the lowest end of altera/intel max line) few other CPLD here and there, but that is about it, the spartan/artix 7 cyclone etc lineup can mostly be considered low end, when compared to intel arria and xilinx kintex, that are the mid range parts (price in single quantity will probably be few k$)

author: asmi
author_rank: Super Contributor
timestamp: October 05, 2020, 04:26:20 pm
content: Quote from: Miyuki on October 05, 2020, 03:31:59 pmYea, this is why I initially selected Xilinx devices when I was doing it as hobby. And once I went on to making designs for the actual commercial customers, my familiarity with their devices made the choice of device vendor a no-brainer. One wonders why other FPGA vendors don't understand the simple concept that today's hobbyists are tomorrow's commercial customers. Xilinx certainly got this right.Quote from: Miyuki on October 05, 2020, 03:31:59 pmUnless we're talking some volumes (at least 100 boards/batch), there is not a single FPGA device in that price bracket that would offer you PCIE and 64bit DDR capability. The cheapest one would be Artix-75 in 484 package - it's got enough IO pins for 64bit DDR2/3 interface, and it's got 4 transceivers which can go up to 3 Gpbs (for speed grade 1) or 6 Gbps (for speed grades 2 and 3) each, so you can implement up to x4 PCI Express Gen 2 interface (16 Gbps of data bandwidth in each direction). This chip is listed at $116.3 for speed grade 1 and $133.77 for speed grade 2 (requirement for PCIE gen 2). That said, if you only want to use SERDES with up to 1200 Mbps per diff pair, you won't need dedicated transceivers as Xilinx devices have SERDES embedded in pretty much all IO cells (with few exceptions). This way you can implement a 720p@60Hz HDMI interface. These cells can also be a bit overclocked to implement a FullHD 1080p@60Hz HDMI interface too (wire speed of 1450 Mbps per diff pair), but this use is not officially supported (though I'm yet to see a device that can't actually do that).If you want something faster (say you want DDR3 frequency above 400 MHz, or PCIE gen 3), you will need to move up to Kintex, and Xilinx also allowing using smaller devices from that family (K70 and K160) for free. But these chips cost $200-300 per device @ Digikey.

author: Miyuki
author_rank: Frequent Contributor
timestamp: October 06, 2020, 08:43:45 am
content: Artix XC7A15T in FGG484 is reasonably cheap on what I needAnd have enough IOs and two SERDESI dont need higher than PCIe 1.0 speed or fast DDR3 interface, I need them for memory density and can run them slow (even soft memory controller is fast enough)That is also why I was interested in ECP5, they are 20-30$ devices with all HW I need, just that licence issue

author: asmi
author_rank: Super Contributor
timestamp: October 06, 2020, 12:32:39 pm
content: Quote from: Miyuki on October 06, 2020, 08:43:45 amDDR3 controller will take about 60% of that FPGA's resources. And I doubt you'll be able to implement PCIe endpoint to fit remaining resourcesYou might want to do your research and better estimate what kind of resources your design will require. Fully compliant PCIe endpoint implementation will eat a ton of resources (so 50T and smaller are out of the question unless you implement it yourself and cut all the corners you can get away with).Quote from: Miyuki on October 06, 2020, 08:43:45 amArtix only has soft memory controllers.Quote from: Miyuki on October 06, 2020, 08:43:45 amLOL. You've got to do your homework first - see above. Just because $20 devices exist, it doesn't mean you can (or should) use them in a specific design.Also - how familiar are you with PCI Express specification? If it is as I suspect ("have no clue"), you have a mountain to climb. Read the spec first to see what you're getting yourself into. Xilinx provides a ready-to-use PCI Express IP, but it consumes so many resources that it only fits into larger devices (75T and above), so you will have to implement it yourself if you still want to try fitting it into smaller device.

author: Miyuki
author_rank: Frequent Contributor
timestamp: October 06, 2020, 01:15:01 pm
content: I dont need fully general purpose PCIe endpoint, just for desired device, like USB bridge or soBut you are right I am still in age of parallel PCI and parallel connected USB 2.0 Transceiver, When everything is slow and simpleIll need to look closer to resource demand this all will haveBut I can live with simplified small and lower speed interfaces, need "just" 50-100MB/s trough PCIe and have CPU for software layer, same with RAM, just transfer fixed size blocks to cache

author: asmi
author_rank: Super Contributor
timestamp: October 06, 2020, 02:42:46 pm
content: Quote from: Miyuki on October 06, 2020, 01:15:01 pmPCI Express Gen 1 x1 link is the simplest form for this bus, it has 2.5 Gpbs / 1.25 (8b10b encoding loss) = 2 Gbps = 256 Mbytes/s of theoretical bandwidth. You might be able to fit it (along with DDR3 controller) into 50T device (thought I have my doubts), but not into 15T one for sure.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 06, 2020, 06:33:27 pm
content: I don't have a lot of experience with Cyclone FPGAs, but in terms of "max speed", I would order them like so (best to worst): Artix 7, ECP5, Cyclone 5.And if I had to choose between the 3, I would select the Artix 7, factoring in the overall cost (per unit, then tools licensing, etc.) and features.I'm not a big fan of Vivado, but it works, and has more features than the tools from the 2 other vendors, and can be used for free for the Artix 7.The ECP5 needs paid licensing. I don't know how much it is these days. It used to be "ok" at $99/year a few years ago, but I suspect the cost has raised significantly - if someone has the info? Also IPs for PCI express may incur some yet extra licensing cost.Not sure about Cyclone 5.

author: BrianHG
author_rank: Super Contributor
timestamp: October 07, 2020, 01:06:02 am
content: Quote from: SiliconWizard on October 06, 2020, 06:33:27 pmNo licensing on the lattice ECP5 unless you want to use their high speed serdes/PCIE. They are the most economical devices especially if you use the entry level non-serdes versions.Careful, the Lattice -8 is their fastest while their -6 is their slowest.For Intel, their -C8 is their slowest and their -C6 is their fastest.So, comparing Lattice -8 with Intel -C8 will show Lattice as being faster.

author: brucehoult
author_rank: Super Contributor
timestamp: October 07, 2020, 01:35:10 am
content: Quote from: Miyuki on October 06, 2020, 01:15:01 pmI just came across this permissively licenced and portable open source DDR3 controller that drives the RAM at low speeds (<125 MHz) and in Artix 7 uses about 27% as much resources as Xilinx's full-featured controller.At 50 MHz clock it gets 180 MB/s sequential read/write.Also tested on ECP5https://github.com/ultraembedded/core_ddr3_controllerAlso in the same location are a couple of RISC-V cores, a DVI framebuffer (based on NZHamster's work), motion JPEG decoder, and more.

author: asmi
author_rank: Super Contributor
timestamp: October 07, 2020, 02:57:04 am
content: Quote from: BrianHG on October 07, 2020, 01:06:02 amHe said he wants PCIE - you need a transceiver for that.

author: asmi
author_rank: Super Contributor
timestamp: October 07, 2020, 02:58:08 am
content: Quote from: brucehoult on October 07, 2020, 01:35:10 amDDR3 specifies a minimum frequency of 300 MHz, performance below that is not guaranteed. So use at your own risk.

author: brucehoult
author_rank: Super Contributor
timestamp: October 07, 2020, 03:39:19 am
content: Quote from: asmi on October 07, 2020, 02:58:08 amRead his documentation. There is a low speed mode (maximum 125 MHz) that is optional but in practice is supported by the RAM he has tried.

author: asmi
author_rank: Super Contributor
timestamp: October 07, 2020, 04:32:17 am
content: Quote from: brucehoult on October 07, 2020, 03:39:19 amQuote from memory chip datasheet:QuoteSo would you trust a random guy on the internet, or manufacturer of chips? As for "practice" - what is it exactly? Did he characterize it over all PVT range? I somehow doubt it. Hence what I said - "use at your own risk". And your own peril, I must add.Besides, one of the main advantages of DDR3 over previous memory types is bandwidth (and you pay a big price for that it terms of latency). If you don't use it - what's the point? You can use previous generations of memory which is much easier to work with. My personal favorite is LPDDR1 - it has wide range of available densities, at the same time it's quite simple to use and it's got very low latency (compared to DDR3).

author: brucehoult
author_rank: Super Contributor
timestamp: October 07, 2020, 07:40:48 am
content: If you have a board such as an Arty A7-35T or other commercially made FPGA board and it has DDR3 RAM on it then you don't have much choice to use LPDDR1. And maybe you don't need the maximum bandwidth possible from the memory.As I can see from all of your replies in this thread, you have a very strong bias towards high end parts, maximum performance, and high volume manufacture.That is not the world in which many of the other people in the thread, and on this BBS generally, operate.

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: October 07, 2020, 11:07:05 am
content: If you're looking for a mid-range FPGA, have you looked at Microchip?The PolarFire FPGA is pretty competitive with Artix-7.

author: asmi
author_rank: Super Contributor
timestamp: October 07, 2020, 01:46:05 pm
content: Quote from: brucehoult on October 07, 2020, 07:40:48 amContext is important. Here we're obviously talking about making a custom board. And so you can design in any memory.Quote from: brucehoult on October 07, 2020, 07:40:48 amThen why going into all the trouble implementing DDR3?Quote from: brucehoult on October 07, 2020, 07:40:48 amNo I don't.1. These (A75/A100) are not high-end parts, not even mid range ones.2. The reason I suggest these parts is that I do know what it takes to actually implement such a solution. Memory-mapped PCIE endpoint IP won't fit into A15 just because you really want it to, or can't afford anything larger. So I kinda expected that OP would rather get an advice on how to actually accomplish what he wants, then a pat-on-a-shoulder "Yea, buy A15, everything is gonna be fine, it's so cheap" (even through everyone who ever tried to do anything like that will tell you that it won't).

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 07, 2020, 03:59:20 pm
content: Quote from: asmi on October 07, 2020, 02:57:04 amThat's what I assumed too. I took a look at Lattice's docs for their PCIE IP, and it seems indeed only compatible with the ECP5UM/ECP5UM5G (both requiring a subscription license for Diamond.) And as I suspected, the PCIE IP ALSO requires an additional license...Note that you can get a limited license for both for free (I think for a limited time, 1 year?) if you buy one of the Lattice VERSA dev kits. Those are not overly pricy and would actually be a good start for designing a PCIE device (instead of rolling your own board first, especially if you have no experience with PCIE.)

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: October 07, 2020, 05:31:08 pm
content: Quote from: asmi on October 05, 2020, 04:26:20 pmI think OP would get better bang-for-buck with a PolarFire FPGA. The MPF100T-FCG484E is $145.73 for 1pc on Digikey. It has 100,000 LEs, 12.7Gbps SERDES, and 1.6 Gbps LVDS I/Os supporting DDR4/DDR3/LPDDR3 and 2x PCIe Gen2 Endpoints/Root Ports. It also works with the free Silver License of Libero SoC.