DIY oscilloscope (yet again) - Page 1
Forum section: electronics / projects

author: PMA
author_rank: Contributor
timestamp: November 13, 2019, 08:34:48 pm
content: I have been daydreaming about DIY oscilloscope for a while. Not for cost saving or better performance than commercial scopes, but mainly as learning experience.The end game would be 8ch scope with modest bandwidth (10-50MHZ), but I will start with something very simple.As a first step I will buy PYNQ-Z2 and design very basic 1ch front end that can be connected to the board. It will probably keep me busy for a while.I have been reading related articles and forum posts in past days, like:https://www.eevblog.com/forum/projects/diy-oscilloscope-front-end-queries/https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual-What is the best approach for the front end if I want to optimize simplicity/part count, but still keep costs in check? Should I copy the design from the discovery 2 or is there more integrated solutions available with a bit higher price?-Is there something wrong with my approach in general?

author: Yansi
author_rank: Super Contributor
timestamp: November 13, 2019, 08:40:07 pm
content: For 10-50Mhz, do the front end the good old fashioned way: JFET buffer with DC servo. Such frontend can be pushed even in the hundreds MHz region with good success rate.Then you place any ADC with integrated VGA (PGA) or an external VGA (PGA) in front of the ADC - whatever suits best.Principles briefly mentioned for example in this datasheet, starting page 34:http://www.ti.com/lit/ds/symlink/lmh6518.pdf//EDIT: Typos.

author: Boscoe
author_rank: Frequent Contributor
timestamp: November 13, 2019, 09:22:26 pm
content: If you’re happy with a reduced input range, say +/-10V then it makes your life a lot easier. Couple this with a x10 probe and you’ve got yourself some thing that will cover 95% of use cases. I don’t think I’ve ever looked at something more than 100V but I don’t design SMPSs.The difficulty in front end designs is getting the attenuation at the input with high input impedance with good bandwidth. Remove the need for the attenuator and your done.

author: PMA
author_rank: Contributor
timestamp: November 13, 2019, 09:42:01 pm
content: Quote from: Boscoe on November 13, 2019, 09:22:26 pmThat is definitely something to think about. My use case would be mostly battery operated motor controllers, so supply voltage won't be more than 48V, but it would be nice if somebody else could use my design as well.I have to take deep dive into front ends, but at the moment it sounds a good idea to keep things simple and go with +/- 10V range and old school design for the front end (+PGA which may not be so old school).

author: Yansi
author_rank: Super Contributor
timestamp: November 14, 2019, 12:10:22 pm
content: If you go down the discrete frontend route, limiting yourself to 10V is dumb limitation. You just need a simple compensated attenuator. Nothing what couldn't be done with a couple of passives and a small cheap signal relay (for example Omron G6K-2F-Y). Also briefly discussed withing the PDF I have linked.Look into how cheap DSOs (Riglents and Hanteks) have frontends made. There are numerous reverse engineered schematics floating round the web. Almost always this very same topology or thereof.Look there for a tip how for example AC coupling mode is accomplished - as this is not discussed within the PDF I have linked. Can be seen well for example from a Rigol DS1054 reverse engineered schematics. (AC coupling of the DC servo, NOT the input path)I do not see any issue why it couldn't be possible to design and tune the frontend for 20MHz operation. Couple years back I have experimented with this out of curiosity. Ugly build of that circuit on a piece of copper clad using just THT components worked well beyond 20MHz without much tuning. (I just got issues with a bit different gains of the DC and AC paths - but now I know why and could improve it).Just make a couple of prototype boards. Nothing more needed for debugging other then a decent ARB generator (sine/square) and an oscilloscope.For the VGA, you could use for example AD8330. (DC to 150 or so MHz VGA). Using a VGA instead of PGA gives a nice ability to self-calibrate gain steps. With PGA, you are stuck with the frontend (and PGA) accuraccy without much possibility to cal it out. (Multiplying the ADC output is not so great idea, but might work as well).

author: David Hess
author_rank: Super Contributor
timestamp: November 15, 2019, 03:16:20 pm
content: The simplest high performance front end uses a pair of JFETs (followed by one or two bipolar emitter followers to unload the top JFET) with the bottom one setting the current of the top one. It has one adjustment for offset and no need for a low to medium frequency compensation adjustment. Usually the JFETs are matched but this is not difficult to achieve in small production runs.In any FET based design, watch out for input voltage range. Modern designs get away with a +/-1 volt input voltage range but that is really pushing it when you consider slew rate limitations and other factors. +/-0.1 volt or less is typical for old oscilloscopes for good reasons. (1) This limitation means plan on using at least one high impedance input attenuation stage no matter what to get a useful input voltage range.There are some low input capacitance fast JFET and MOSFET input operational amplifiers now like the The LTC6268, ADA4817, and AD8065 which might be used for a lower performance design. Using shunt and differential feedback amplifiers will result in poorer transient response unless bandwidth is limited and special care is used. This applies to the following stages as well.(1) There are ways to get a +/-10 volt input voltage range without attenuators using a cascode design but the first few attempts are likely to be VHF oscillators.

author: Yansi
author_rank: Super Contributor
timestamp: November 15, 2019, 03:49:57 pm
content: Simple JFET buffer (without a DC servo) will never have good DC accuracy. Maybe good enough for analog CROs, where you tweak the offset every time. But not good enough for a DSO, where zero shall be zero all the time.

author: David Hess
author_rank: Super Contributor
timestamp: November 15, 2019, 08:13:09 pm
content: Quote from: Yansi on November 15, 2019, 03:49:57 pmJFET totem-pole buffers can have outstanding DC accuracy. With care, they can even have lower drift than the common DC servo configuration using a divider followed by a CMOS operational amplifier because the divider multiples the input offset voltage drift of the operational amplifier.In the example shown below, trim R15 to adjust offset; Q13B isolates high frequencies from R15 so a trimmer potentiometer may be used here. Q14 is a JFET being used as a low leakage diode for negative input overload protection; the forward biased gate junction of Q13A protects itself during positive overloads. C6 and R6 are also for input overload protection. As shown, Q13 is a dual JFET however matched single JFETs will work just fine but mount them in close proximity for good temperature tracking. Discrete parts would normally be thermally bonded together for best performance.Modern designs eschew this method because matching a pair of JFETs costs more than the additional circuitry for a DC servo control loop.

author: PMA
author_rank: Contributor
timestamp: November 17, 2019, 09:50:27 am
content: I probably go with DC servo. It seems to be de-facto in lower end scopes, so there is plenty of examples available and it is proven design for DSO.I have been looking different attenuator designs and found out that they are relatively complicated even in low end scopes. Not that voltage divider is complicated, but there is lots of art in compensation circuits. Is there good literature available about the subject?Higher end designs tends to use multiple selectable attenuators in parallel or in series. Is it worth of effort and pain or is it better to keep things simple and use just one?

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2019, 10:48:47 am
content: That "JFET pairing" and need for "tweak this Rx or this Ry until good" is exactly the reason, why the dc servo was invented and is widely used.I see absolutely no reason why the servo shouldn't be superior to a pair of paired JFETs. The Opamp used in the servo does not need to be that fast and can be of low Vos type. In some appnote I have seen OPA2227 suggested. But sure it will work with almost any decent opamp.

author: gf
author_rank: Super Contributor
timestamp: November 17, 2019, 01:02:46 pm
content: Quote from: PMA on November 17, 2019, 09:50:27 amBesides the compensated divider, yet another design goal for a scope's attenuator is IMO constant input capacitance - independent of the selected attenuation - otherwise you need to re-adjust a connected 10:1 probe whenever you switch to a different attenuation stop[I'd not be not sure, though, that this is really granted for all low-end scopes].gf

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2019, 01:45:45 pm
content: Constant impedance? That is not happening, even with high end scopes. Unless you use a 50ohm termination mode.You probably meant that the impedance curves shall be similar, both with and without the attenuator selected. That is probably true. But probably not that critical in a 10-50MHz setup. I'd just make sure the input capacitance stays the same.

author: PMA
author_rank: Contributor
timestamp: November 17, 2019, 03:28:12 pm
content: Why there is basically low pass filter in the Rigol? It cannot be just for bandwidth limiting for the next stage because the attenuator is selectable. Something to do with capacitive coupling of the circuits on higher frequencies?

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2019, 03:38:05 pm
content: Where exactly do you see it, or what do you mean by low pass? It is a compensated divider. Plus some resistors to get the response more right.

author: David Hess
author_rank: Super Contributor
timestamp: November 17, 2019, 05:16:06 pm
content: Quote from: Yansi on November 17, 2019, 10:48:47 amActually if you match the JFETs then the current setting resistor does not need to be adjusted however the offset of the high impedance buffer stage needs to be adjusted at some point to trim the step attenuator balance. Sometimes this is done in the high impedance buffer, either by adjusting the JFET drain current or adjusting the offset of the DC servo, and sometimes it is done in the following stage so there is always an offset adjustment somewhere.The DC servo method has its own adjustment for the low to medium frequency compensation whether they show it or not. This is why some modern implementations have a low to middle frequency step in the amplitude response that older designs did not suffer from.QuotePractically any low input bias current operational amplifier is suitable for the DC servo. Tektronix first used the TLC271 programmable operational amplifier set for high bias probably for minimum input noise.There are some disadvantages to the DC servo configuration:1. The input divider multiplies the offset drift and low frequency noise of the operational amplifier above that which would be present in the dual JFET implementation. I have seen designs which did away with this attenuation however doing so makes point 2 below worse. Low frequency noise on some modern DSOs is truly atrocious compared to past oscilloscopes despite marketting claims about "low noise". Their broadband noise is no better.2. Input overload can cause windup of the DC servo prolonging overload recovery time.However for a simple design, I would ignore all of these performance considerations and implement whatever is simplest or the designer is most comfortable with except for a shunt feedback design which just leads to troublesome transient response.Quote from: Yansi on November 17, 2019, 01:45:45 pmHe means constant input capacitance and resistance with different input attenuator settings. The former requires a trimmable shunt capacitance for each attenuator stage in addition to the timmable capacitor for frequency compensation. These adjustment have a *major* effect on the low to medium frequency compensation.Quote from: PMA on November 17, 2019, 09:50:27 amTheTektronix Circuit Concepts Bookshave a detailed discussion of high impedance input attenuators in the Vertical Amplifier Circuits book available at that link.TheTektronix 7A15(not 7A15A) service manual shows details for discrete attenuator sections from 1x to 1000x. Older designs are easier to implement with discrete parts and printed circuit board assemblies.Steve Roach who worked for Hewlet Packard designing digital storage oscilloscope front ends wrote a chapter included in Jim William's "The Art and Science of Analog Circuit Design" called "Signal Conditioning in Oscilloscopes" which covers how more modern instruments do it.QuoteYou can almost certainly get away with just a single switchable high impedance attenuator stage but better modern oscilloscopes use at least two x10 stages in series.But do not forget about the switched AC/DC coupling stage. Older oscilloscopes implemented this before the first high impedance attenuator but Steve Roach's paper mentioned above discusses how to implement this as part of the DC servo controlled high impedance buffer.

author: PMA
author_rank: Contributor
timestamp: November 17, 2019, 05:27:46 pm
content: Quote from: Yansi on November 17, 2019, 03:38:05 pmLong story short: there was series of brain farts.

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2019, 05:56:21 pm
content: Quote from: David Hess on November 17, 2019, 05:16:06 pmad 1) noise in what exact quantity? I doubt that would become anywhere close to what a shitty 8bit ADC dynamic range can offer in that application, with a standard lowest 5mV/div step.* Bad PSRR, channel crosstalk etc would be your bigger enemy. But I stay being corrected.ad 2) I think that is left as is in even many not-low-end scopes. If the AFE is overloaded, well, then you are using the scope wrong.*just guessing OP is aiming for the standard 8bit acquisition which is "good enough" for many scope applications, 10, 12 or more bits would definitely require more than just "simple & easy" AFE design.//EDIT: Not sure what "low-medium compensation" you talk about, but the DC servo's low frequency gain matching (to the JFET buffer medium-high frequency gain) is usually auto-tweaked using a couple of electronic pots within the feedback loop.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 17, 2019, 06:28:19 pm
content: Quote from: Yansi on November 17, 2019, 10:48:47 amThe OP2227 is not suitable for the DC servo, as it would add considerable current noise, that the fast part would also see. The suitable choice would be more like a good JFET based OP, like OPA141, maybe LT1012 if it really needs to be BJT based.In the discrete JFET buffer the offset adjustment with the current source also effects the temperature drift. So one could adjust for minimal temperature drift and compensate the usually small residual offset separately. The advantage of well matched JFETs is that zero offset and zero drift are close together.Even with a 8 bit ADC, input noise can still be important. It kind of limits the lowest useful sensitivity (e.g. 10 mV/div in a noisy config, and maybe 0.5 mV/div if low noise). The leveling factor here is more the noise of a typical 1:10 probe - no real need for a very low noise input with the noise of an 1 Meg resistor. It's with a 1:1 probe where the noise really counts. The ADC resolution is more like linked to screen resolution.

author: PMA
author_rank: Contributor
timestamp: November 17, 2019, 06:36:42 pm
content: Quote from: Yansi on November 17, 2019, 05:56:21 pm8bit is good enough for me. More is always better, but I think that the project is difficult enough even if I try to keep everything simple.

author: David Hess
author_rank: Super Contributor
timestamp: November 17, 2019, 06:53:49 pm
content: Quote from: Yansi on November 17, 2019, 05:56:21 pmAt high sensitivities, even 5mV/div, the dynamic range of an 8 bit ADC is plenty to pick up the noise at least in a noisy design. The servo loop is good for DC drift but low frequency noise levels can be much higher.For most applications, this is irrelevant. However if you are expecting to use an FFT to measure low frequency noise, it will limit performance.QuoteThere is a matter of degrees here. If the servo loop design is careless, then overload recovery time can be extended by orders of magnitude. Some oscilloscopes are very resistant to overload giving additional application flexibility. A few are even immune. (1)QuoteI am not sanguine that 10 and 12 bit designs are anything more than marketing at work. DSOs have enough difficulty with noise, settling time, and distortion even with 8 bit resolution. Sampling oscilloscopes are a different matter.Many low cost commercial designs use the extra resolution provided by a higher resolution converter as a free programmable gain stage.QuoteThe paper by Steve Roach that I mentioned discusses the difficulties with dual loop buffers. Automatic calibration would require additional complexity to inject the test signals. Is that desirable in a DIY design? I would settle for support for ground coupling so that the offset of the following stages can be removed.(1) Sampling oscilloscopes are immune to overload. I know how to make a low impedance signal path immune to overload but making a high impedance buffer immune is difficult to impossible and many commercial designs do not even bother to try.

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2019, 07:07:41 pm
content: Thank you for some clarifications.I am not sure of hand how the GND coupling switch is accomplished. Do you have any sources I can refer to?Not sure how difficult it'd be to inject any kind of test signal, but I guess even the low end scopes do that for self-calibration, don't they?

author: gf
author_rank: Super Contributor
timestamp: November 17, 2019, 10:25:27 pm
content: Quote from: Yansi on November 17, 2019, 07:07:41 pmWell, on my Hantek scope the "GND" position is a fake. Obviously it just sets the signal to zero in the digital domain (after ADC). Seems they did not spend money for any associated component (e.g. relay) in the analog frontend.Quote from: Yansi on November 17, 2019, 07:07:41 pmOne signal is typically injected anyway, and that's the vertical position offset. One potential injection point is at the DC servo. My understanding ist that at least some of the low-end scopes simply sweep the vertical position (and measure the resulting ADC output) in order to self-calibrate offset/gain (requiring by documentation that no signal must be connected to the inputs during self-calibration).[ This self-calibration eventually compensates the overall offset errors of all frontend stages and the ADC, so it does not matter if any of the stages has some residual offset error - what matters is rather offset drift which invalidates the self-calibration again after some time. ]gf

author: PMA
author_rank: Contributor
timestamp: November 17, 2019, 10:53:16 pm
content: I haven't found many schematics with ability to inject test signal, but there is at least one example (see attachment (don't remember original author, sorry)).If there is arb waveform gen on the board, it isn't big step to route signal to inputs.

author: David Hess
author_rank: Super Contributor
timestamp: November 18, 2019, 02:03:24 am
content: Quote from: Yansi on November 17, 2019, 07:07:41 pmIn old designs ground coupling is part of the AC and DC coupling circuit and requires another mechanical switch or relay. Functionally it connects the input through a resistor to the AC coupling capacitor while grounding the high impedance buffer. This provides two functions; it grounds signal to the high impedance buffer but it also precharges the AC coupling capacitor to the average DC input voltage which can be important in some applications to prevent damage to the input circuits. The Tektronix service manuals show various circuit configurations for achieving this but the most relevant ones are probably their early automated oscilloscopes where it was just a pair of relays.Interestingly enough, on the Tektronix 2247A analog oscilloscope which provides input calibration like gf mentioned, ground coupling does not actually connect the input to ground. Instead it connects the input to a variable calibration voltage which may be serve as "ground" by being set to zero volts when ground coupling is selected.Selecting between AC and DC coupling is possible without a relay and lots of oscilloscopes do it now (the paper by Steve Roach that I mentioned shows an example) but I am not sure how to select ground coupling without a relay which may explain why so many oscilloscopes cheat for this.

author: gf
author_rank: Super Contributor
timestamp: November 18, 2019, 11:05:53 pm
content: Quote from: David Hess on November 17, 2019, 06:53:49 pmYou mean the polular HMCAD1511? Admittedly, it makes relatively simple/cheap frontend designs possible if the demands are not too high. When I look at my Hantek 6xx4BD, there are two cascaded 10:1 attenuators at each input (-> switchable between 100:1, 10:1, 1:1), then the "classical" JFET/BJT hybrid darlington voltage follower with DC servo, and finally a fully differential amp with ~2x gain, driving diferentially into the HMCAD1511. At 100mV/div, the HMCAD1511 operates w/o digital gain, and for all smaller V/div steps, simply the digital gain is increased (up to 50x at 2mV/div). There is no dedicated VGA in the signal chain. Due to the extra internal resolution the HMCAD1511 has only a moderate ENOB loss up to a gain of 32. The noise level I see (about 350-450µV RMS) is IMO more significant than the ENOB loss due to digital gain. One drawback of this design is that enabling the the 20MHz BW limit in the frontend does not reduce the noise level at all - which makes me conclude that most of the noise is obviously introduced after the BW filter (maybe even inside the ADC chip?).gf

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2019, 09:28:40 am
content: The HMCAD1511 is a nice chip, however pretty darn expensive, for just a 10 or 20 MHz frontend. For 8 channels, you would need also 2 of them.For the simple lowMHz DSO a dedicated VGA and ADC may become cheaper. Although, with 2pcs HMCAD1511, the whole thing may look much simpler on the PCB.If it'd be me and cheaping out on some project cobbling for fun, I'd opt for external voltage controlled VGA such as AD8330 from the far east sources ($2-3 a pop) and a 100MSps ADC, such as AD9288 (also dirt cheap from far east), four times. Leaving me at about $30 for the whole VGA+ADC saga. Of course this does not likely make much if any sense for a commercial design, at least I won't be quite worried about damaging a $70 IC in the process.There may be even cheaper possibility than AD8330, as a DC to 20MHz or so VGA, this is still a bit overkill.And also, I've never worked with LVDS on an FPGA, hence a lot of parallel buses from the smaller ADCs are more familiar to me as to what I can do

author: PMA
author_rank: Contributor
timestamp: November 19, 2019, 05:50:51 pm
content: Won't you need DAC with VGA to set gain, or have I missed something? To my (quite limited) understanding, I prefer PGA. Small gain adjustments can be done on digital side if needed.

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2019, 10:51:43 pm
content: Well, at the time I was interested in building my own single channel DSO (with the sole purpose to learn VHDL), I couldn't find any cheaper gain selector other than the AD8330. Any PGA I came across was either way to slow, way to fast (hence extremely expensive) or didn't provide enough gain steps. AD8330 as a continuously variable gain stage was easy to set the gain using a DAC. I already had available two 12bit D/A channel in the MCU I wanted to control the system, so that was easy (one DAC for the VGA setting, the other for input offset setting, with a couple of offset range switches from analog MUXes). MCP4921/4922 are also very cheap external SPI DACs./EDIT: Small gain adjustments on the digital side would mean fractional multiplication of high bandwidth data, which was a nono for me. I wanted to use a cheap CPLD (Altera MAX II), where such would become impossible. I had a 480x272px display, so I didn't have to scale the 8bit data, just place directly on screen.

author: PMA
author_rank: Contributor
timestamp: November 19, 2019, 11:41:27 pm
content: Thanks for the clarification.I am much more comfortable in digital domain than in analog domain, so I probably see things in different light. That's why I prefer integrated solutions (where somebody else have solved analog issues for me), instead of more discrete solutions. I wouldn't say that money is no option, but in any case this exercise will cost more than commercial product so cost effectiveness isn't highest priority.I am planning to use HDMI output and external screen with the scope - I know, it is a bit unusual configuration. External display enables enough of real estate to display multiple signals, but in the same time it would be responsive because it is connected to the scope. PC mouse could be used to control the UI. In my case, raw data can be read to the memory and scaled when it is drawn on the display, which eliminates scaling of high bandwidth data.

author: roy5
author_rank: Newbie
timestamp: November 21, 2019, 08:24:42 am
content: I have used an Arduino as an oscilloscope and signal generator in the past. It works great as long as 5V is sufficient for you. I suppose it probably wouldn't work so well at very high frequencies either, but again, for my application it was great. It actually worked much better than a $50 oscilloscope I bought from China which connects by USB to my computer and runs via software on the computer.

author: PMA
author_rank: Contributor
timestamp: November 21, 2019, 08:40:52 am
content: Although I am a bit Arduino fan boy, it isn't right tool for this. I want to have moderate bandwidth, which means that FPGA based solution is the only option (in practice).

author: fmkit
author_rank: Contributor
timestamp: November 21, 2019, 10:14:11 am
content: if you need GHz bandwith isn't easier to shift portion of spectrum dwn tofit existing scope bandwith?just like SDR and older receivers do. 2 years back I made 0-2GHz spectrum analyzer using STM32F103(HY-Mini32v 3.2" TFT) and now thinking to add DSO function to existing setup,that is adding 2nd mixer and IF amp:

author: Yansi
author_rank: Super Contributor
timestamp: November 21, 2019, 10:31:53 am
content: Jeeeez... read at least the first post of the thread!

author: PMA
author_rank: Contributor
timestamp: November 21, 2019, 03:06:08 pm
content: Quote from: fmkit on November 21, 2019, 10:14:11 amThis is mostly learning experience for me. Scope is just good excuse to learn more about analog electronics and FPGA development.I don't think that there is any simpler way to acquire full waveform (0-50 Mhz, 500 MS/s per ch) than proper analog front end and FPGA, since there isn't too many oscilloscope specific ICs on the market.

author: David Hess
author_rank: Super Contributor
timestamp: November 23, 2019, 06:11:23 pm
content: Quote from: gf on November 18, 2019, 11:05:53 pmNo, I mean many low cost USB and "toy" DSOs use a 12 bit ADC but only return 8 bit results except in high resolution mode. The extra 4 bits are only used in place of a PGA.What the HMCAD1511 does relies on the error correction included in its pipelined subranging ADC design which is different as it is not designed to return 12 bit results.Quote from: Yansi on November 19, 2019, 10:51:43 pmHigh bandwidth integrated solutions suitable for oscilloscope gain control have been largely proprietary until relatively recently. There are ways to do it with commonly available parts, and you can learn the details by studying old oscilloscope design, but the techniques are not well known because it is a rare and difficult application.Quote from: fmkit on November 21, 2019, 10:14:11 amThat is possible and some very wide bandwidth DSOs now work that way but in general that method is not suitable for abaseband(time domain) applications because it requires a huge amount of postprocessing to merge the frequency ranges.Sampling and equivalent time sampling oscilloscopes could be considered to operate that way. Sampling and mixing are essentially the same process and may use the same parts and circuits. The same diodes used in microwave mixers are used in microwave samplers. Direct coupled mixers make fine sampling elements.

author: gf
author_rank: Super Contributor
timestamp: November 24, 2019, 12:01:02 am
content: Quote from: David Hess on November 23, 2019, 06:11:23 pmOK. At lower speeds, 12-bit ADC is certainly not so challenging as at 1GSPS.QuoteIt works differently, but eventuelly it can act as a PGA as well, up to gain of 50 (when both, coarse and fine gain are turned up to the maximum). The application notes recommend, however, not to choose a gain > 10, otherwise SNR suffers.While itreturns8 bits only, the returned value is already scaled by the selected "digital gain", having ENOB of still almost 8 bits (in the recommended gain range).Quote from: Application Notes

author: David Hess
author_rank: Super Contributor
timestamp: November 24, 2019, 02:34:16 am
content: Quote from: gf on November 24, 2019, 12:01:02 amLower is relative. 12 bit settling, noise, and linearity are very challenging at even low oscilloscope bandwidths.I have seen very old 100 MHz 8 bit DSOs which delivered better than 8 bit noise (1) but I have never seen a modern 8 bit instrument achieve the same thing. Part of it is the result of software upgradable bandwidth which means the hardware is designed for a higher than necessary bandwidth resulting in higher device noise. Another part is the use of CMOS preamplifiers that have much higher noise than the bipolar preamplifiers they replaced. The physics of today is the same as the physics of 30 years ago.Oscilloscope noise is rarely a concern however so higher noise than 30 years ago is not really a disadvantage. If you need a lower noise oscilloscope, then there is probably a better way to make your measurement. But I still chuckle that seemingly every marketing department advertises their oscilloscopes as "low noise" now.(1) It is a little weird to turn the vertical position control and be able to select a single ADC code with little or no noise producing a straight line. A noisier signal looks more natural.

author: gf
author_rank: Super Contributor
timestamp: November 24, 2019, 09:27:08 am
content: Quote from: David Hess on November 24, 2019, 02:34:16 amAt 10V/div, 1V/div and 100mV/div, the analog SNR seems indeed too exceed 8 bits on my Hantek 6074BD (only sporadic 1 LSB spikes). These are the attenuator steps where the HMCAD1511 gets driven at 2Vpp full-scale, w/o unnecessary attenuation and subsequent re-amplification in the signal chain. All other V/div steps rely on re-amplification (via digital gain) of the 10:1 or 100:1 pre-attenuated input signal and are noticeably noisier.[ Yet another candidate for unnecessary attenuation and subsequent re-amplification I'm aware of is the Hantek 2000. Every V/div step is first attenuated to a 10mV/div equivalent and then (re-)amplified to the ADC's required full-scale voltage by a (fixed) gain stage. ]Quote(Unnecessary) bandwidth is certainly a significant contributor. On my JyeTech DSO 112a toy scope (~50 bucks, ~1-2MHz bandwidth), I can clearly see ~1.2mV quantization steps in the output of a DDS generator. But on my 1GSPS Hantek 6074BD, these steps drown in noise...

author: PMA
author_rank: Contributor
timestamp: November 24, 2019, 06:21:50 pm
content: Here is my war plan for the first test. I will make 1ch on separate PCB and attach it to PYNQ-board with ribbon cable (not sure if this is good idea for high speed data).Edit:PLL chip for ADC: ADF4360-7Relays: NEC UD2I have seen two variants of ADC buffer. In some designs ADC is driven with PGA without any additional components and in some designs there is additional buffer between them. I don't fully understand why additional buffer is needed because output impedance of the PGAs are typically quite low. What are pros and cons of these design choices?

author: Yansi
author_rank: Super Contributor
timestamp: November 24, 2019, 09:04:37 pm
content: good find on that AD8370!

author: David Hess
author_rank: Super Contributor
timestamp: November 24, 2019, 10:49:22 pm
content: Quote from: gf on November 24, 2019, 09:27:08 amIf it was just caused by the greater bandwidth, then the bandwidth limiting filter would remove it.Most of the noise comes from the FET used for the impedance converter at the front end. (1) All other things being equal, higher frequency parts have higher noise and higher flicker noise so designing a wider bandwidth front end and then limiting the bandwidth results in higher noise than if the front end was lower bandwidth to start with.(1) Unless integrated CMOS preamplifiers are used. Those things have incredibly high noise; like above 1000nV/SqrtHz at low frequencies.