Required safety margin for Vds of mosfets (do I need to overprovision?) - Page 1
Forum section: electronics / beginners

author: shapirus
author_rank: Super Contributor
timestamp: June 02, 2024, 08:42:44 pm
content: I'm building a circuit which will have an N-channel MOSFET acting as a switch.Most of the time it will be turned off, and in that state drain-source voltage Vds will be about 30V.Upon turning on the transistor will pass about ~700 mA peak, which will gradually drop to zero in about 1.5 seconds, then it will be turned off again. Duty cycle is not well defined. Most of the voltage will drop on the load, so the transistor will stay well within SOA in both the turned on and turned off states.Now, how much of a headroom does the transistor need to have between the planned max Vds of ~30V (might be actually up to 32V or so) and the value specified in the absolute maximum ratings in the datasheet? Is there any rule of thumb that can be used here?Will a MOSFET with Vds(max) = 40V be fine or I should rather go for a higher voltage one?

author: CaptDon
author_rank: Super Contributor
timestamp: June 03, 2024, 01:25:56 pm
content: If the load is inductive a 2:1 increase of the VDS over the actual supply voltage would be a huge reliability enhancement along with a snubber circuit. If your load is purely resistive 40 volts VDS on a 32 volt circuit should be fine. Remember, there will always be a be of overshoot / ringing due to the inductance of the wiring itself even in a purely resistive network. The capacitance (CGS) and the way you drive the gate can help control overshoot.

author: shapirus
author_rank: Super Contributor
timestamp: June 03, 2024, 01:45:29 pm
content: Quote from: CaptDon on June 03, 2024, 01:25:56 pmYes good point about inductive overshoot.In this case, however, by the time the transistor is ready to be turned off, the voltage across the load with the transistor in series with the load will be lower than the initial voltage. The transistor is used to start or stop discharging a large capacitor into a resistor, so start voltage is always higher than end voltage.Load is resistive in this case, the only inductance present will be that of wiring. I'll have to simulate it, but I think that at this current (less than an amp) and a few tens of nH of stray inductance there's not going to be any significant amount of overshoot.What I was really not sure about is how close we are generally allowed to get to the absolute maximum rating. Semiconductors aren't supposed to be operated at the limiting values and the datasheets say that such operation can actually damage the device. But then, how many percents below the absolute maximum rating is considered to be okay?

author: Manul
author_rank: Super Contributor
timestamp: June 03, 2024, 03:24:20 pm
content: My rough rule of thumb is this: don't exceed datasheet values and don't max out everything at once. Main things are temperature, current and voltage. It's good to derate at least one of these. So for example, if junction temperature is low, barely above room temperature, I feel ok to max current and voltage.In fact, at lower temperature, Drain to Source breakdown usually has some gracefulness. Some mosfets are rated just for that - see avalanche energy. For most mosfets, small and short breakdown currents will not cause damage. That easily covers for parasitic inductance.Exeption is Gate voltage, I would always derate that, no matter other conditions. Gate breakdown is never graceful, it always causes permanent damage. It's good to avoid limits.Often mosfet damage is caused by improper driving, either too small gate voltage, too high (might be caused by ringing) gate voltage, or slow transitions, unexpectedly increasing junction dissipation. Linear region for most mosfets is a very vulnerable territory and should be avoided by driving gate hard enough.

author: shapirus
author_rank: Super Contributor
timestamp: June 03, 2024, 04:40:46 pm
content: Quote from: Manul on June 03, 2024, 03:24:20 pmTo put in some numbers, I have just tested one of IRLML0030 that I have, which are rated for max Vds = 30V, using the DY294 high-voltage tester.Result: ~36V (at 550 μA leakage current).I'm wondering whether along-termexposure to Vds at max rated value or slightly below it is going to cause any damage or degradation.Quote from: Manul on June 03, 2024, 03:24:20 pmYeah gate voltage is a whole different matter. That dielectric layer is quite fragile.

author: Manul
author_rank: Super Contributor
timestamp: June 03, 2024, 05:21:10 pm
content: Quote from: shapirus on June 03, 2024, 04:40:46 pmI think no, if other conditions are not sressed, especially temperature.It is true, that more derating statistically gives less failures. If you massively derate, you also to some extent cover manufacturing defects (parts which are partialy defective, weaker, but somehow passed the fatory tests). In the end it might not really matter if you get 5 or 3 failures out of 100,000. Important is to not screw up such that you get 10,000 failures out of 100,000.

author: amyk
author_rank: Super Contributor
timestamp: June 04, 2024, 01:50:33 am
content: I suggest looking at what other voltage ratings the family of parts is available in to determine how close to the rating you should be. If the next higher voltage than 40V is e.g. 50V, then they probably have a very tight binning and you really shouldn't get close to 40V. If the next higher voltage is something like 80V, it may be less likely to fail if you run the 40V part at nearly its rating.

author: shapirus
author_rank: Super Contributor
timestamp: June 04, 2024, 06:18:14 am
content: Quote from: amyk on June 04, 2024, 01:50:33 amTo mention specific parts, this is IRLML0<voltage> series. They come in 30V, 40V, 60V, and 100V variants. I'd pick the 60V one, but these are somewhat harder to source for me than the 40V, hence the question (but the purpose is really to understand the general case approach rather than find a one-off solution).I have a feeling that 40V may a bit too close, but maybe I have no reason to worry (provided that inductive kickback etc. is taken care of).Also, I played with a bit lower voltage, but a lot less margin with it yesterday on a breadboard: 29V with IRLML0030 (rated for 30V). No issues so far, worked fine during those couple of hours. Besides, that was the very same transistor that I tested to find its Vds breakdown voltage, meaning it was not a damaging test, or at least not obviously damaging.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 04, 2024, 07:15:33 am
content: Many (most?) MOSFETs actually have avalanche ratings available - meaning that it is "legal" toexceedthe Vds_max, and the MOSFET just acts like a "zener diode". Key is that the pulse energy needs to be limited to the datasheet value.Now of coursepracticallyproving that your circuit never exceeds these ratings is pretty difficult. You would need to find truly worst-case operating conditions, take unit-to-unit variations into account, and then measure using an oscillosscope with zero input capacitance and infinite bandwidth to catch the true peak voltage... And if you plan to utilize avalanching, how do you measure the energy? Add a zero-resistance, zero-inductance ideal current sensor in series with the MOSFET?And even if you are able to prove you are below avalanche energy rating, it still adds power dissipation, something which usually already is pretty high for the MOSFET.So in practice, given limited instruments, most of try to do their best to find the worst case peak voltage,andadd safety margin.For example:DC bus voltage is 20V nominalAdd overvoltage detection which kills the MOSFET drive, verify that it acts at e.g. 22VNow account for inaccuracies in said circuit, assume worst case actual Vbus = 23VAdd 50% margin for overshoot (could be worse if your layout sucks): choose Vds = 34.5V --> 35V rated partRun the circuit at highest input voltage, measure Vds with oscillosscope. If the layout is tight, maybe even 100MHz BW oscillosscope is marginal for the job, it could oscillate beyond 100MHz and you are missing the peak value! So use e.g. 250MHz oscillosscope if available;Run oscillosscope peak detection for some minutes/hours. If you are actually seeing 20-30% overshoot instead of your assumed 50%, be happy. If you are close to the 35V rating, itcouldstill work reliably because the avalanche rating could save your day... but I would be hesitant to trust it -> choose a different part; or use more time / effort to prove the reliability of your chosen part. Or, improve layout / add a snubber to reduce the peak voltage.Remember, excessive peaking probably also is a sign of EMI problem.

author: shapirus
author_rank: Super Contributor
timestamp: June 04, 2024, 07:30:39 am
content: Quote from: Siwastaja on June 04, 2024, 07:15:33 amI actually did. No overshoots whatsoever, in my particular case. Even though it was wired on a solderless breadboard. That's because current isn't high and the transitions are relatively slow. That's why a tighter margin is probably ok in this case.But, good info on general considerations.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 04, 2024, 07:42:56 am
content: Slow switching by adding series gate resistor is obvious when fast switching speed does not matter. If you want to go extremely slow, it might be a good idea to add extra C in parallel instead of going to tens or hundreds of kOhm.

author: shapirus
author_rank: Super Contributor
timestamp: June 04, 2024, 08:13:36 am
content: Quote from: Siwastaja on June 04, 2024, 07:42:56 amYeah, but there's a trade-off between the amount of overshoot/ringing and heat that the transistor has to dissipate during the transitions. This is, obviously, to be determined depending on application.Quote from: Siwastaja on June 04, 2024, 07:42:56 amIn this case I would rather not slow it down beyond a few hundreds of nanoseconds, maybe a few μs at most. That'll be a good balance between power dissipation of the transistor, including the instantaneous values (it's a SOT23 part, so can't go too hard on it) and ringing. This is actually already very slow switching, well sufficient to dampen any unwanted oscillations at the current in question (sub-1A).From what I've experienced so far (including simulations), ringing becomes an issue when switching times are reduced to below ~50 ns, give or take depending on many variables.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 04, 2024, 08:19:58 am
content: It's about the relation of switching time vs. natural oscillation frequency of the layout, which then again is basically defined by layout inductance and Cds of the MOSFET. Especially in small designs this easily goes beyond 100MHz, so accordingly, just slowing down by a few tens of ns already makes a difference. OTOH if you are building a switch mode converter operating at 1MHz, even 10ns slowdown already increases switching losses significantly.