Looking for a cunning way to run SPI via an SMA coax connector - Page 1
Forum section: electronics / projects

author: peter-h
author_rank: Super Contributor
timestamp: June 18, 2025, 03:25:27 pm
content: I have a requirement to bring out SPI i.e. ground, clock and data, but cannot find a multipole connector which can be PCB mounted in place of this onehttps://www.mouser.co.uk/ProductDetail/Rosenberger/32K242-40ML5?qs=ehM%252BESVsXgy4TJuLlD9mgQ%3D%3DThe nearest is something like this Lemo onehttps://www.digikey.co.uk/en/products/detail/lemo/EPG-00-304-HLN/3793469but that doesn't fit the hole in the box I haveI can decode the SPI signals using a little external PCB.One obvious way is Manchester encoding but that needs a bit of logic, which is going to be SPI speed sensitive. But there are various hacks e.g. transmit the clock edges as very short pulses within the data bits.

author: peter-h
author_rank: Super Contributor
timestamp: June 18, 2025, 03:53:35 pm
content: That's cleverI still need to generate SPI signals though. The NRZ stream will give me the data but I need to generate the clocks, and the whole thing is obviously data rate dependent.Ultimately I need to load a SIPO shift register, for which SPI is great.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 18, 2025, 03:59:16 pm
content: What's the clock frequency? And I'm assuming it's not bidirectional?

author: langwadt
author_rank: Super Contributor
timestamp: June 18, 2025, 04:08:52 pm
content: Quote from: peter-h on June 18, 2025, 03:53:35 pmhttps://www.edn.com/one-i-o-line-drives-shift-register-with-strobe/orhttps://www.ti.com/lit/ds/symlink/sn74lv8153.pdf

author: ejeffrey
author_rank: Super Contributor
timestamp: June 18, 2025, 04:33:06 pm
content: Manchester coding gets clock and data on the same signal. You just need to devise an encoding that has start of frame and end of frame delimiters to control the chip select. It could be something that looks like 10 base T Ethernet for instance.

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 18, 2025, 04:50:32 pm
content: Quote from: peter-h on June 18, 2025, 03:25:27 pmThat's also not an SMA connector... so I'm guessing you're not actually restricted to SMA connectors?QuoteIf you're using Manchester encoding, then it's by definition not SPI... again what are your actual requirements?

author: peter-h
author_rank: Super Contributor
timestamp: June 18, 2025, 05:17:57 pm
content: QuoteVariable clock speed... from 600kHz to a few MHz. Yes; output only.QuoteThe current one is SMA. The proposed 4 pole replacement is not but also it doesn't fit. So I am stuck with the SMA as the only way to get the data out of the box.QuoteWell, obviously I cannot run SPI through an SMA connector; one needs to do some encoding and then decoding.QuoteI can gate the clock+data with /CS before sending them through the connector.

author: ejeffrey
author_rank: Super Contributor
timestamp: June 18, 2025, 05:30:34 pm
content: Quote from: peter-h on June 18, 2025, 05:17:57 pmMy point was how to reconstruct the CS on the receiver side. You might need some dummy bits at the beginning to make sure you are locked on the right edge and you don't want to clock bogus zeros into your device if that's the case. 10 megabit ethernet for instance starts with a preamble which the receiver uses to lock on, then flips the last bit of the preamble to indicate the start of frame.

author: peter-h
author_rank: Super Contributor
timestamp: June 18, 2025, 05:36:22 pm
content: That's an interesting point.However, say you have a x bit long SIPO shift reg, you don't need CS (or any other kind of frame sync) because the x parallel outputs will be set according to the last x bits you shifted in.The next challenge will be to stop the x outputs jumping around while the data is being shifted in. This application doesn't want that. But one can blank the display during the (recovered) clock transitions. And if one wants a totally concurrent update of x parallel bits, one would put in x latches and update them with a timer, after the cessation of the update is detected (yes that assumes the data is not solid; if it is then you do need some sort of framing signal too).

author: bobxyz
author_rank: Contributor
timestamp: June 18, 2025, 05:51:06 pm
content: Too big?https://www.digikey.com/en/products/detail/same-sky-formerly-cui-devices/SJ1-2503A/738680

author: joeqsmith
author_rank: Super Contributor
timestamp: June 18, 2025, 05:59:03 pm
content: Quote from: peter-h on June 18, 2025, 03:25:27 pmFor a one off, just feed the wires through the hole and solder them direct? If you need a connector and like the one you found, there is always larger drill bits....

author: sslupsky
author_rank: Contributor
timestamp: June 18, 2025, 07:45:24 pm
content: Use Differential Manchester encoding and a RP Pico PIO to encode and decode it?Or use single pair ethernet such as 10Base-T1S or 10Base-T1L? I think there is a Pico with T1S available:https://docs.zephyrproject.org/latest/boards/kws/pico2_spe/doc/index.html#id1I inquired about availability but never heard back so I cannot say if you can actually buy one.What distance do you need to go? T1L can reach up to 1000m.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 18, 2025, 07:46:56 pm
content: Quote from: peter-h on June 18, 2025, 05:36:22 pmIn the simplest form, what you describe there can be done with two monostables, and PWM coded data.Very similar to serial LED, but with speed adjusted to suit your MHz.It does need continual data, then a pause for the frame / latch load.With fixed hw sample point, the clock speed needs to be fixed, but the gaps between bursts can vary.Another variant of PWM modulation is SENT, serial encoded nibble transmission.That’s usually lower baud but has a sync/cal start, then 4 bits choose 16 modulation widths.What exactly is ‘a few MHz’?

author: peter-h
author_rank: Super Contributor
timestamp: June 18, 2025, 07:51:59 pm
content: I'd say max will be 3MHz, simply because it needs to drive a few m of multicore cable.

author: Smokey
author_rank: Super Contributor
timestamp: June 18, 2025, 08:04:32 pm
content: What other connections between the boards are there? Is there some other ground reference? Other cables?If so, maybe run the clock on the "ground housing" and the signal on the pin of the SMA.

author: Benta
author_rank: Super Contributor
timestamp: June 18, 2025, 09:32:34 pm
content: An important question is: does it need to be DC-neutral? Eg, Manchester coding has zero DC content, but that's because it's normally used for magnetic recording or AC-coupled transmission.If you don't need zero-DC, a simple encoding would be pulse width. As an example: a 100 ns pulse is 0, a 200 ns pulse is 1.Easy to decode (and lock on to, you'll need to detect the period as well), and inserting pauses would indicate byte boundaries.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 18, 2025, 11:14:43 pm
content: Quote from: peter-h on June 18, 2025, 07:51:59 pmEven a UART can manage that.How much control do you have on the CLK and DAT - is this coming from some black box you have no control over?If so, how does it currently manage end of frame / CS / load ?

author: amyk
author_rank: Super Contributor
timestamp: June 19, 2025, 02:10:56 am
content: 1-wire to I2C/SPI translator:https://www.analog.com/media/en/technical-documentation/data-sheets/ds28e18.pdf

author: Smokey
author_rank: Super Contributor
timestamp: June 19, 2025, 02:45:55 am
content: Quote from: amyk on June 19, 2025, 02:10:56 amchip of the day right there!

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 19, 2025, 04:13:50 am
content: Quote from: amyk on June 19, 2025, 02:10:56 amComes up rather short on throughput for the OP's needed 3MHz clock speed:Supports Standard (11kbps) and Overdrive (90kbps) 1-Wire Communication

author: peter-h
author_rank: Super Contributor
timestamp: June 19, 2025, 05:59:32 am
content: QuoteYes I don't need zero DC, and the way it is looking, this is the best way to go.Actually I did this c. 1983 for an 8-zone heating controller (Z80 etc) which had a remote relay box, with 10 relays and just one data wire. I sent the data as-is down that wire and where the +ve clock edges were to be, I sent a brief data-inversion pulse which was detected by a one-shot. The scheme worked over a wide range of data rates from zero to quite fast, but of course "quite fast" was not needed for switching relays.It was quite primitive though.

author: Howardlong
author_rank: Super Contributor
timestamp: June 19, 2025, 06:28:17 am
content: I agree, pulse width is the obvious solution if there's no requirement for DC balance.I am immediately reminded of the Neopixel protocol, which covers for both clock and frame recovery.On modern microcontrollers, all of this is achievable on chip, offloading it to hardware with judicious configuration of peripherals including SPI, configurable logic blocks, and various timers.Furthermore, if you're using an SMA connector, this could be achieved over quite a long distance if impedance matched.

author: peter-h
author_rank: Super Contributor
timestamp: June 19, 2025, 06:53:30 am
content: I looked up Neopixel. The problem I see there is that the decoder needs to know the clock frequency fairly accurately - say within 10%.The scheme I used way back was thisThe output is same as the data input but has a brief pulse within it on +ve clock edges. So it is data rate independent, so long as that short pulse is short in relation to the rest. If say it was 100ns then data rates of 0 to about 2mbps would work.Of course, compared to e.g. Manchester it wastes the channel bandwidth (due to the short pulses) but that's OK here, and decoding Manchester also needs a speed-aware decoder.

author: JustMeHere
author_rank: Frequent Contributor
timestamp: June 19, 2025, 06:56:04 am
content: If you know the clock timing, you don't need a clock signal. Kind of like how RS 232 works.

author: 8goran8
author_rank: Contributor
timestamp: June 19, 2025, 07:22:01 am
content: I suggest you check out the Microchip solutions for single-pair Ethernet 10BASE-T1S and 10BASE-T1L.https://www.microchip.com/en-us/products/high-speed-networking-and-video/ethernet/single-pair-ethernet

author: fchk
author_rank: Frequent Contributor
timestamp: June 19, 2025, 08:51:45 am
content: Idea: use a 2.5mm or 3.5mm TRRS jack and plug - the ones used in mic+headphone combos:https://www.digikey.com/en/products/detail/same-sky-formerly-cui-devices/SP-2544/9486666https://www.digikey.com/en/products/detail/same-sky-formerly-cui-devices/SP-3540/9486672

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 19, 2025, 09:04:22 am
content: Quote from: peter-h on June 19, 2025, 06:53:30 amYou can send some known leading bits for autobaud, hence the question about how much control do you have over the CLK and DATQuote from: peter-h on June 19, 2025, 06:53:30 amThat looks doable with Monostable + Config gate for encode and Monostable + Config gate for clock extract + Monostable to stretch CLK if needed?A MCU with Config Logic cells might manage that ?

author: Howardlong
author_rank: Super Contributor
timestamp: June 19, 2025, 10:09:45 am
content: Quote from: peter-h on June 19, 2025, 06:53:30 amI wasn't suggesting using the exact same timing as NeoPixel.There is no need for the decoder to know the clock rate.Short pulse, zero.Long pulse, one.As long as both pulses fit within the bit period, all's fine and dandy.For example, you could have a bit rate from DC up to about4MHz8MHz with a short pulse being 100ns and a long pulse being 200ns.The receiver sniffs out rising edges, starting a 150ns timer/PWM for clock recovery. When the timer's complete after 150ns, the line is sampled, shifting the sampled bit into the SPI shift register. There is no requirement for the SPI slave clock duty cycle to be 50%.To detect slave select, use the rising edge to assert, and bus inactivity to de-assert.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: June 19, 2025, 10:23:07 am
content: Why not just convert to 3Mbaud UART each side?

author: peter-h
author_rank: Super Contributor
timestamp: June 19, 2025, 10:51:59 am
content: It is a bit complicated because my SPI is shared across a number of devices (with a mutex, etc): GPS, LCD, ADC, DAC, etc.The data comes out as SPI and I can't change that.I am also stuck with having to support variable data rates - this is because the kit at the other end has limitations which vary according to various factors out of my control. The most likely data rate will be about 500kHz (650 is actually one of the divider options I have).So I would have to put in an SPI UART (they do exist) and send out NRZ, and do it at the highest possible baud rate, as you say.But then to receive it I need a UART and a CPU which has SPI and which can regenerate the clock+data. I need a much simpler receiver/decoder. I don't think there is a UART which will autobaud and then output clock+data.The 3.5mm (or 2.5mm) jack is a great idea but they are too tall above the PCB and don't fit into the box. But that can be solved mechanically, but so can that Lemo connector. It is just that the SMA connector is really neat and convenient.

author: Howardlong
author_rank: Super Contributor
timestamp: June 19, 2025, 11:21:45 am
content: Quote from: peter-h on June 19, 2025, 10:51:59 amThis doesn't make any sense: you're fine with adding various adaptations to SPI, but not with just using a simple UART.QuoteAs this is a proprietary application, why are arbitrary bit rates a requirement?

author: fchk
author_rank: Frequent Contributor
timestamp: June 19, 2025, 11:25:43 am
content: Quote from: peter-h on June 19, 2025, 10:51:59 amYour SMA connector is 7mm tall. and 9mm wide according to the linked datasheet.Look here:https://www.digikey.de/de/products/detail/same-sky-formerly-cui-devices/SJ1-42534-SMT-TR/659908https://www.sameskydevices.com/product/resource/sj1-4253x-smt.pdfAccoding to the datasheet this jack is 8mm wide and 5mm tall. Should fit?

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 19, 2025, 12:36:53 pm
content: Quote from: peter-h on June 19, 2025, 10:51:59 amI'm assuming only one slave is on the other side of the cable, all the others are on the same board as the master...?QuoteDoes the clock frequency of transactions across this cable need to be variable? Or just for the local slaves?QuoteIf the serial interface must start out as SPI on the master, then I think any solution which only uses a single wire would require some sort of FPGA/CPLD or a lot of discrete circuitry.QuoteYou still haven't described your mechanical constraints in any coherent way.QuoteIs it really?? It sounds super inconvenient, given how many hoops you'd have to jump through to make it work. I'm having a hard time believing it's more convenient than changing to a different connector entirely (SATA, modular jack, stereo jack, whatever).

author: peter-h
author_rank: Super Contributor
timestamp: June 19, 2025, 12:47:21 pm
content: Yes.The solution needs to support a variety of clock speeds.One can extract clock fairly simply e.g. per the timing diagram I posted.The PCB fits into a fairly tight moulded box, and there is a UCB-C connector is close proximity to this connector. Sorry - it is too complicated to explain.The SMA is there to support some major product features, #1 being a GPS antenna and #2 being a 22 bit ADC input (obviously those two are mutually exclusive!). I am now being asked to provide an SPI output.

author: tszaboo
author_rank: Super Contributor
timestamp: June 19, 2025, 01:11:53 pm
content: Well clearly the best way is to 16QAM modulate it at around 20 GHz and send it through the connector that way. All the bits of the SPI bus can be sampled and turned into 16 states and sent that way. Tell your boss to order a spectrum analyzer and signal generator just to test it, don't ask questions, just buy me the testing equipment.

author: mtwieg
author_rank: Frequent Contributor
timestamp: June 19, 2025, 01:26:15 pm
content: Buy me one too, just to be safe.

author: peter-h
author_rank: Super Contributor
timestamp: June 19, 2025, 02:48:01 pm
content: I've just realised my sketched scheme above will recover only the +ve clock edges, not the -ve ones, so it won't recover the traditional 50/50 duty cycle SPI clock signal. Fortunately I don't need that.Years ago I did another scheme for sending NRZ data over fibre. I used one pulse for the +ve edge and two pulses for the -ve edge. Then I had a state machine, in a 22V10, which did both encoding and decoding of this scheme. It was clocked at 1MHz. The pulses were 1us wide.There's a chip you want to avoid buying today! Lots of fun with production programming from Jedec files, generated in PALASM and later in CUPLIf you remember that, you are too old... but CUPL still exists, apparently, and has a GUI version.The pulsed scheme was good for fibre work because the LED life was not great so using short pulses (the duty cycle for say a 9600 baud NRZ was tiny) made them last much longer.

author: dietert1
author_rank: Super Contributor
timestamp: June 19, 2025, 06:03:24 pm
content: One could also use a multilevel digital signal, packing clock and data into 3 analog output levels. For the transmitter one needs a resistive combiner. On the receiver side one needs some comparator to detect the third state and an RC low pass to suppress the short clock pulse at the shift register data input.Regards, Dieter

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 19, 2025, 08:48:35 pm
content: Quote from: dietert1 on June 19, 2025, 06:03:24 pmYes, fast comparators are easy to get these days, some even include a latch.If the host SPI updates data on one edge and CLK on the other edge, you can ternary modulate Data + a phase-shifted clock, to give enough front/back porch to latch the data.Addit:QuoteIf you want a many-m of tolerance, this trinary data could even send using a single RS485 transmitter, and be extracted using two receivers, with offset slicing.

author: langwadt
author_rank: Super Contributor
timestamp: June 19, 2025, 08:55:53 pm
content: Quote from: dietert1 on June 19, 2025, 06:03:24 pmhttps://en.wikipedia.org/wiki/Rube_Goldberg_machine

author: uer166
author_rank: Super Contributor
timestamp: June 19, 2025, 10:02:04 pm
content: Simple: convert to UART and use a THVD8000 transceiver to send signal if it needs to be DC balanced or just direct it not.Why would the receiver not have a <2% clock tolerance? 10% is crazy!

author: tooki
author_rank: Super Contributor
timestamp: June 19, 2025, 10:51:43 pm
content: Quote from: fchk on June 19, 2025, 08:51:45 amI highly advise against this. They’re just not reliable enough. They’re not designed for high-speed data, they tend to be scratchy (so potential data errors if movement or vibration is present), they often oxidize and need to be plugged and replugged to make good contact again, they have only poor retention, and they short out during hot-plugging.Binder makes some lovely little tiny connectors that fit in any space a panel-mount SMA jack can fit.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 19, 2025, 10:52:29 pm
content: Quote from: peter-h on June 19, 2025, 10:51:59 amThe UART does not need to Autobaud, it just needs to run faster than the fastest expected SPI speed.If going that route, I would use thesame small MCU at both ends, with a few lines of assembler.3MBd slave link is tricky but not impossible, with a good small MCU. What size packets do you need ?The SiLabs EFM8BB5x have FIFOs on UART and SPI and the UART baud is 49MHz/2/N, (2% osc) so supported are4.0833,3.500,3.0625,2.7222,2.45 MBd (etc)It has 8 & 9 bit UART modes, so 9th bit can be command/frame/CS byte or bit - packages from DFN12 upThe BB51/52 have 2 UARTS, the smaller BB50 has just the simpler 1.

author: amyk
author_rank: Super Contributor
timestamp: June 20, 2025, 03:23:43 am
content: Quote from: langwadt on June 19, 2025, 08:55:53 pmhttps://en.wikipedia.org/wiki/Pulse-amplitude_modulation#EthernetAt this point everyone is either referencing or reinventing existing high-speed serial protocols already.

author: dmendesf
author_rank: Frequent Contributor
timestamp: June 20, 2025, 05:04:43 am
content: STM32F030F4 is a tssop with 20 pins. It has an internal oscillator with PLL to run at 48Mhz. It has one SPI and one UART with 9 bit capability that can run at 6mbits/s. Use one configured as SPI slave receiving data and encoding the CS as the 9nt bit and another that receives data and outputs it with a master SPI. Problem solved.

author: Ian.M
author_rank: Super Contributor
timestamp: June 20, 2025, 06:43:56 am
content: Quote from: dietert1 on June 19, 2025, 06:03:24 pmIt actually needs four levels as for full write only SPI one needs to encode /SS as well. To get a clean(ish) MOSI at the receiver, you need to run the recovered data through a transparent latch to hold it while SCLK is active. There needs to be a small delay between the data comparator and the latch. Three fast comparators are needed + a resistor ladder to set their thresholds. I've drawn up a 2 MHz (or any slower speed down to DC) Mode 0 SPI proof of concept in LTspice using its behavioral A devices that is matched to the 50 ohm line so you don't have to worry about the length of the coax on the SMA connector. Some work will be needed to implement it with real ICs.However if you need multiple SPI slavesQuote from: dmendesf on June 20, 2025, 05:04:43 amlooks like a better approach. The first byte with the 9th bit set would select which remote /SS to assert, then after the data frame with 9th bit clear, a zero byte with the 9th bit set would deassert /SS.

author: dietert1
author_rank: Super Contributor
timestamp: June 20, 2025, 07:45:49 am
content: Yes, if you want a 50 Ohm solution it will probably work with low signal levels and require more effort on the receiver side. I thought of something similar to analog video with its embedded sync pulses. Maybe it's a case for making special receiver and transmitter integrated circuits to support a bidirectional SPI connection. Also the HP 37203A comes to mind, a coaxial transport HP once made for the GPIB bus.One can save the chip select signal for a HCT595 by gating the SPI clock on the transmitter side and routing the clock into a bipolar transistor on the receiver side. It generates the latching edge after its recovery from saturation.I used this when i needed to fit a 6 bit parallel interface to 2 pins. Now the DSub9 connection runs with- 2 pins supply- 2 pins SPI- 5 pins analogRegards, Dieter

author: peter-h
author_rank: Super Contributor
timestamp: June 20, 2025, 12:59:40 pm
content: I don't need to feed through /CS because I will be gating clock and data with /CS before outputting it. This is necessary anyway because this SPI is shared (mutexed etc) between half a dozen devices, from 650kHz to 21MHz, and I don't want all that other crap coming out.To encode data and clk, using multiple levels, I need four levels. And one of them is GND. That needs three window comparators, but no doubt can be simplified.

author: Ian.M
author_rank: Super Contributor
timestamp: June 20, 2025, 02:27:36 pm
content: Not using /SS (/CS) tends to be fragile driving most SPI compatible ICs, as unless you use a monostable (or other means) to either regenerate it from SCLK or generate a reset pulse from SCLK or MOSI, there is nothing to reset the receiver state machine, which can easily skip to persistently running 'off by 1' (or more bits) due to noise being detected as a false SCLK pulse.Take a look at my LTspice sim above - as long as you know the SPI mode in advance, one can encode SCLK, MOSI *and* /SS, with only four analog levels and three comparators in the receiver.

author: peter-h
author_rank: Super Contributor
timestamp: June 20, 2025, 03:09:54 pm
content: Excellent point, but fortunately in this case the receiving device is just a long SIPO shift reg, driving a load of LEDs. So no /CS is needed. But indeed one could be generated with a monostable, from the recovered clock, as a part of the decoder.I ran your simulation. It looks seriously impressive! I am on the edge of my LTspice expertise although I have used it for something a year or so ago. I haven't found a way to plot the waveforms one above the other - like one uses a scope. Thank you! I like the clever way to get a 50 ohm Zout for the cable driveIs the transparent latch transparent for S/H=1?

author: Ian.M
author_rank: Super Contributor
timestamp: June 20, 2025, 03:28:26 pm
content: I'm actually abusing LTspice's behavioral analog sample and hold, using it as a digital transparent latch. Seehttps://ltwiki.org/?title=Undocumented_LTspice#SampleHold_.28aka_Sample.29Yes it is transparent when S/H is high.There is no easy way to stack waveforms in LTspice short of manually adding an offset to the plot expression. Most of the time I simply use multiple plot panes. However when I'm dealing with multiple logic signals and *not* sharing the sim here, I tend to use a third party component 'dview' originally from the LTspice Yahoo group that stacks them in a single plot - seehttps://www.eevblog.com/forum/projects/simulation-model-for-parallel-in-serial-out/msg5151159/#msg5151159

author: peter-h
author_rank: Super Contributor
timestamp: June 20, 2025, 03:51:16 pm
content: OK; a 74HC75 will do the transparent latch. Why did you use A12? MCP6564 will do all 3 comparators.I might reduce the driver Vout, to reduce power into 50 ohms. With a 3.3V Vcc it would draw a fair bit. I'd like to get it down to about 5mA. SN74LVC2G125 line drivers with a 1.8V Vcc look good for this, though estimating the Icc is not trivial.

author: w42i
author_rank: Contributor
timestamp: June 20, 2025, 03:56:30 pm
content: You could also try a "more analog" way. If you have enough SNR, just feed CLK, DATA and STROBE into a DAC to generate 8 voltage levels. A simple R2R DAC and buffer may be enough, since 8 levels is still quite coarse.On the receiving end, you need a free-running ADC with correct voltage range. Use the most significant bits as recovered digital outputs.Needs a quite fast ADC, though.Question is also: What happens during the transitions? Maybe you need some deglitching logic at least for CLK and STROBE.Haven't tried this approach, but sounds plausible.

author: Ian.M
author_rank: Super Contributor
timestamp: June 20, 2025, 04:45:40 pm
content: Quote from: peter-h on June 20, 2025, 03:51:16 pmA12 provides a propagation delay so the data to the latch is still valid when the SCLK comparator triggers.The problem is decreasing the supply voltage invariably increases the output resistance of CMOS gates and line drivers which will distort the levels. However you can pad down the output, e.g. make R2 250 ohms, R3 500 ohms, add a 71.5 ohm resistor from transmitter out to ground (to keep 50 ohm output impedance). Increase R7 to 3.6K to fix the thresholds. That gets the total peak current under 20 mA but gives under 500mV pk-pk at the receiver so you'll probably need much better and more expensive comparators. TANSTAAFL applies!

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 20, 2025, 08:01:35 pm
content: Quote from: peter-h on June 20, 2025, 12:59:40 pmIf you gate the unwanted chaff, does that not mean you will know the exit clock speed reasonably well?If youknowthere are no unexpected gaps in the clock during data bursts, the CLK/DAT/CS can be decoded with two monostables and encoded with one.Quote from: peter-h on June 20, 2025, 03:09:54 pmMost led drivers have a latch strobe to avoid unwanted flickering and excess RFI during shift.Best to use that ?

author: peter-h
author_rank: Super Contributor
timestamp: June 20, 2025, 08:50:34 pm
content: QuoteThe data comes out of an SPI controller in the 32F4, so each byte will definitely be 8 tightly packed bits.Beyond that, not sure. Normally when writing SPI code where I control both ends, I use DMA. Thishttps://www.eevblog.com/forum/microcontrollers/anyone-here-using-the-ramtex-graphics-library/msg5946664/#msg5946664is done with DMA, and each horizontal line is done as one DMA transfer so tightly packed at the SPI. Not everything can be done with DMA; for a start there is a 64k block size limit. And in this case I don't know what the final requirement will be as regards block size, and/or what computation will be taking place to fill whatever buffer.This all runs under an RTOS but each DMA operation is mutexed, because the SPI is mutexed.QuoteI don't understand.QuoteYes; providing the /CS is probably a good idea, and should make this futureproof.I've done lots of 7-segment multi digit driving and normally one blanks the whole lot during the update. But that could be done entirely at the display, by detecting a gap in the clock. Whatever display it is, it won't be updated continuously; there will always be "frames", otherwise there would be no opportunity for blanking it.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 20, 2025, 10:28:19 pm
content: Quote from: peter-h on June 20, 2025, 08:50:34 pmJust how many LEDs do you expect here ? That's sounding more complex than a simple shift register ?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 21, 2025, 12:05:10 am
content: Quote from: peter-h on June 20, 2025, 08:50:34 pmEncode is a Monostable triggered by CLK and with 2 resistors - one to Vcc and one to data. Data is stable during CLK HI so it can add/subtract time to easily PWM modulate.Demodulate is the same monostable, with a mid-span time, so Shift register clocks in DATA.That leaves CS/Latch, which is done on a pause in CLK edges.If you are not certain about gaps between bytes but within large packets, you could additionally encode the CS with a long CLK = LOW time.That's another DFF which can ignore any pauses when CLK=HI = normal SPI interbyte pauses.The host here sounds quite complex, so that may help future proof things.The new TI monostables can manage pulses from ~58.1ns (1k/10pF), so they can modulate/demodulate to higher baud rates than you need.

author: peter-h
author_rank: Super Contributor
timestamp: June 21, 2025, 05:24:31 am
content: QuoteProbably a few k of them. It is just a shift register.Ian's method (multilevel analog) is the best for this job. Speed independent and encodes the whole lot. The 50 ohm transmission line is a bonus which enables long cables to be used, which could never be done if running the SPI signals.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 21, 2025, 11:41:30 pm
content: Quote from: peter-h on June 20, 2025, 03:09:54 pmA simple separation can be achieved by varying the vhigh on probed outputs slightly (eg 3.0V 3.1V ) or you can add a larger DC offset to the output, but I find the minor vhigh variance trick easier to zoom and measure.Quote from: peter-h on June 20, 2025, 03:51:16 pmAnother approach is to shuffle the 4 levels in design for lowest idle power.As drawn, clock is a top modulation level, easy to decode but more power hungry.If the clock is modulated negative, highest priority, and idles at 0 mA, that reduced the peak power.That leaves three levels of CS and DATL and DATH to encode positive going.If CS = inactive is 0mA then idle state draws zero power (or minimal power, you could add a small offset current for cable break detect )

author: eliocor
author_rank: Unknown
timestamp: June 22, 2025, 01:25:38 am
content: using a SERDES, maybe?https://eu.mouser.com/c/semiconductors/interface-ics/serializers-deserializers-serdes/

author: peter-h
author_rank: Super Contributor
timestamp: June 22, 2025, 06:50:31 pm
content: QuoteThat is fine, and the comparators are not an issue either. There are plenty of ~50ns chips, and very cheap.QuoteThat looks like quite a complex solution, and I would not touch a Maxim chip with a 20ft bargepoleNot even post ADI takeover - the same arrogant monkeys still run the company.

author: Ian.M
author_rank: Super Contributor
timestamp: June 22, 2025, 08:37:16 pm
content: A combination of your reduced supply voltage idea, my matched attenuator and possibly paralleling several buffers to reduce the output impedance is likely to give the best compromise between pk-pk amplitude and transmitter supply current.Re-ordering the levels to reduce power consumption would need much more complicated receiver circuits. As is, provided line noise is under half the interval between levels, SCLK and /SS cant glitch and the inevitable data glitch as the clock goes active is mitigated by the delay and transparent latch. There will be a glitch to '1' at the trailing clock edge but that's when MOSI transitions anyway.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 23, 2025, 02:33:07 am
content: Quote from: peter-h on June 18, 2025, 03:53:35 pmThis is new, and not much sign of real parts, but it does isolated SPI over single pulse transformer link, 2.5MBd and 100 metres.http://www.energymaths.com/en.php/index/products/id/92claims:◼ 2.5Mbps EMiso (isolated daisy chain) Data Communications◼ Simple Galvanic Isolation Using Standard Transformers◼ Bidirectional Interface Over a Single Twisted Pair◼ Supports Cable Lengths Up to 100 Meters◼ Very Low EMI Susceptibility and Emissions◼ Configurable for High Noise Immunity or Low Power

author: peter-h
author_rank: Super Contributor
timestamp: June 23, 2025, 02:17:02 pm
content: These two appear identical; both quad:74ALVC125MC74LCX125The 1st one appears to have more drive but could just be a data sheet artefact. I will buy some bits and build itLT1721 is a reassuringly expensive quad comparator

author: fchk
author_rank: Frequent Contributor
timestamp: June 24, 2025, 10:19:09 am
content: Analog/Linear has got isoSPI where they transmit SPI over a single twisted wire pair.Look here:https://www.analog.com/en/products/ltc6820.html

author: peter-h
author_rank: Super Contributor
timestamp: June 24, 2025, 10:58:42 am
content: Interesting chip!It has some odd timing issues. One would need to spend hours on the data sheet and work out the implications of their fast and slow modes...It is also not 50 ohms although it may be possible to hack it. 50 ohms was not my original requirement but it is a great feature to have it.

author: Ian.M
author_rank: Super Contributor
timestamp: June 24, 2025, 11:41:37 am
content: If fiddling with the LTC6820 IBIAS - ICMP divider doesn't let you get suitable levels and thresholds to direct drive 50 ohm terminators at each end of the line, you could simply choose an appropriate turns ratio for the coupling transformers to transform the 50 ohm line impedance up to the range the LTC6820 is designed for.

author: peter-h
author_rank: Super Contributor
timestamp: June 24, 2025, 12:49:00 pm
content: If using 120R resistors, then I would think the source impedance is 120 ohms, since the driver circuit is a current source/sink.Then with 2:1 transformers you have a 60 ohm line, no?This chip is an amazing solution - up to a 1MHz clock.

author: Ian.M
author_rank: Super Contributor
timestamp: June 24, 2025, 01:13:37 pm
content: NO! Impedance transforms by the square of the turns ratio. However see datasheet fig. 18 where they are using 2:1 transformers with 480 ohm terminating resistors to match presumably 120 ohm twisted pair, so 2:1 transformers with 200 ohm terminating resistors would match 50 ohm coax.

author: peter-h
author_rank: Super Contributor
timestamp: June 24, 2025, 01:27:38 pm
content: Well. This looks like an amazing solution, with isolation being such a great feature, BUT I want > 1MHz clock for driving LED matrix displays. So close...So back to Ian's multilevel approach.Isolation can be done easily enough at the SPI generation end, using the SI8641BB* isolator parts, and a DC-DC converter to power the floating circuit.

author: dietert1
author_rank: Super Contributor
timestamp: June 24, 2025, 03:55:58 pm
content: That LTC6820 datasheet starts with "AEC-Q100 Qualified for Automotive Applications" and the solution resembles CAN. In automotive they know how to use twisted pair and transmission rate also resembles CAN. I mean they made it because someone wanted to buy it. The speed may be enough for a LED display, unless one wants video performance,.TI offers the ISOW7841 part, an integrated SPI isolator with on-chip isolated DC-DC converter.Regards. Dieter

author: bson
author_rank: Unknown
timestamp: June 25, 2025, 07:55:23 pm
content: Quote from: JustMeHere on June 19, 2025, 06:56:04 amIn fact, why not just run 3.3V logic async serial. It can easily do 0.5-1Mbit over coax. The receiver will use the start bit to lock, and you can use a special character sequence to determine the data rate. Even better is you can use any garden variety UART (with half decent oversampling and a FIFO on the receive end). Or the tiniest of microcontrollers if you want to turn it into SPI.

author: passedpawn
author_rank: Contributor
timestamp: July 01, 2025, 12:54:27 am
content: These sorts of cunning ideas always run into issues that result in redesign and regret. It's possible you'll kludge something together that works. FSK over wire etc. I've been there lol. It'll work - kinda. And the next version, which needs more data bandwidth, etc, will break the kludge.Consider designing around a standard comm protocol instead of the kludge.

author: sslupsky
author_rank: Contributor
timestamp: July 16, 2025, 09:52:54 pm
content: How about differential Manchester and use 4b5b to frame the data?