Questions on Sub-1 Volt OTA - Page 1
Forum section: electronics / projects

author: promach
author_rank: Frequent Contributor
timestamp: June 18, 2021, 09:55:23 am
content: Could anyone explain on "Obviously, the compensation capacitance CC does not connect Drain to Gate directly around output transistor M10. It takes a path throughcascodedevice M6, in order toavoid a positive zero." ?

author: Cerebus
author_rank: Super Contributor
timestamp: June 18, 2021, 09:55:18 pm
content: You need to be a bit more explicit in what you're asking. I take it, but I'm not sure, that you're asking:What is a "cascode"?What is a "positive zero"?

author: magic
author_rank: Super Contributor
timestamp: June 19, 2021, 07:36:50 am
content: Looks like feedforward zero and Ahuja compensation.editI never really understood the problem of FF zero either. So I played with SPICE and got the result below. It appears in disturbingly idealized circuits and apparently boils down to conductance of Cc exceeding gain device transcundactance and taking over driving the output.

author: promach
author_rank: Frequent Contributor
timestamp: June 19, 2021, 09:38:12 am
content: @magic I am confused with howAhuja compensationworks ?

author: magic
author_rank: Super Contributor
timestamp: June 19, 2021, 11:04:02 pm
content: Cascode M6 ensures that the left side of Cc sees a (mostly) constant voltage. Hence Cc current is only dependent on output voltage swing and no current passes Cc due to M10 gate drive waveform.BTW, I could swear that "Analog Design Essentials" sounds like a sort of book that should explain all of that.If they say it's obvious, it's probably because the topic has already beenin earlier chapters.

author: promach
author_rank: Frequent Contributor
timestamp: June 20, 2021, 01:37:26 am
content: For those interested in Ahuja compensation, Baker's uses "indirect compensation" in his book :CMOS: Circuit Design, Layout, and Simulation, see page 813, 814 and 815

author: promach
author_rank: Frequent Contributor
timestamp: June 20, 2021, 10:23:04 am
content: I am now working on theactual mosfet circuitry implementation, the circuit is not working yet.Note: I will decrease the Vin+ and Vin- voltage amplitude afterwards.

author: magic
author_rank: Super Contributor
timestamp: June 20, 2021, 10:59:08 am
content: Your PMOS symbols are upside down, dunno if the model is symmetric.Common LTspice beginner gotcha

author: promach
author_rank: Frequent Contributor
timestamp: June 20, 2021, 12:07:39 pm
content: What do you mean by "Your PMOS symbols are upside down" ?I have updated themosfet circuitry, and the OTA circuit seems to be working fine in transient analysis.However, why does the AC analysis plot look so bad ?

author: promach
author_rank: Frequent Contributor
timestamp: June 20, 2021, 12:44:36 pm
content: Is the switch labelled as 2n related to CMFB sinceCMFB is required for all differential OTA circuit structure?

author: Cerebus
author_rank: Super Contributor
timestamp: June 20, 2021, 03:24:17 pm
content: Quote from: promach on June 20, 2021, 12:07:39 pmExactly that. You've connected them with the sources at the bottom and the drains at the top connected to the positive rail. Convention when drawing "L" shaped gates is for the gate to come out on the source side of the channel.

author: promach
author_rank: Frequent Contributor
timestamp: June 20, 2021, 04:38:01 pm
content: Do not worry about the mosfet direction or the symbol itself.I have used these PMOS and NMOS in previous projects without any issues.By the way, the following transient analysis results seems a bit strange.