complete memory map of the Cyclone 5 HPS? - Page 1
Forum section: electronics / general

author: FrankBuss
author_rank: Unknown
timestamp: December 16, 2018, 03:58:51 pm
content: I'm searching for a complete memory map of this chip. I foundthis site, which lists a few registers, but e.g. I'm missing the full description of the generic interrupt controller (GIC), which is somewhere at 0xFFDE_DD04, according tothis page. But this address is a white spot in the memory map at the other website, and it has some other white spots.

author: andersm
author_rank: Super Contributor
timestamp: December 16, 2018, 06:20:52 pm
content: I don't know if there's a single document that contains everything. Since many of the blocks are licensed, the documentation often just refers to the IP vendor's documentation. Eg. for details of the GIC, the HPS Technical Reference Manual refers to the Cortex-A9 MPCore Technical Reference Manual, available from ARM's website.

author: FrankBuss
author_rank: Unknown
timestamp: December 16, 2018, 06:36:38 pm
content: Ok, but what about at least the base addresses? Can't find them for the GIC in the Intel documents, but maybe I just didn't find the right document, there are so many. And then only the forum post lists the Cyclone 5 specific interrupt numbers.

author: andersm
author_rank: Super Contributor
timestamp: December 16, 2018, 08:30:14 pm
content: See the section titled "Cortex-A9 Microprocessor Unit Subsystem" of theHPS Technical Reference Manual.

author: FrankBuss
author_rank: Unknown
timestamp: December 16, 2018, 09:05:12 pm
content: Thanks, I found the base address of the GIC on page 737 in the PDF file, 0xfffec100. And it is actually in the first link written as well, under the mpu section:https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#topic/sfo1410068407646.html#sfo1410068407646So might be the full address range, no white spots. Looks like the Intel KBD article has the wrong addresses.

author: FrankBuss
author_rank: Unknown
timestamp: December 17, 2018, 03:13:45 am
content: PS: I need this for a quick and dirty hack for disabling the interrupts in user mode. I know you shouldn't do this, and it will mess up ethernet connections, timers etc., but it worksWell, most of the time. Sometimes I got a message "rcu_sched detected stalls on CPUs/tasks", or "NETDEV WATCHDOG: eth0 (socfpga-dwmac): transmit queue 0 timed out", so you really shouldn't do this for production software and instead write proper kernel drivers, but the system was still running, at least over the USB UART port. The source code:Code:#include <stdio.h>#include <unistd.h>#include <fcntl.h>#include <sys/mman.h>#include <stdlib.h>#include <stdint.h>// the GIC starts at 0xfffec100, mmap can map only at 0x1000 boundaries#define GIC_MAP 0xfffec000#define GIC_SPAN 0x1000int gic_fd;void *gic_map;void mmap_gic(){gic_fd = open("/dev/mem", O_RDWR | O_SYNC);if (gic_fd == -1) {printf("ERROR: could not open \"/dev/mem\"...\n");exit(1);}gic_map = mmap(NULL, GIC_SPAN, PROT_READ | PROT_WRITE, MAP_SHARED, gic_fd, GIC_MAP);if (gic_map == MAP_FAILED) {printf("ERROR: mmap() failed...\n");close( gic_fd );exit(1);}}void unmap_gic(){if (munmap( gic_map, GIC_SPAN ) != 0) {printf("ERROR: munmap() failed...\n");}close( gic_fd);}void enable_interrupts(){*((uint32_t*) (gic_map + 0x100)) = 1;}void disable_interrupts(){*((uint32_t*) (gic_map + 0x100)) = 0;}int main(int argc, char **argv){// memory map the GIC regionmmap_gic();// disable interrupts// you can't use printf etc. when interrupts are disableddisable_interrupts();// do something// enable interrupts againenable_interrupts();// unmap GIC region and close handleunmap_gic();return( 0 );}At the comment "// do something" you can write any code that don't use interrupts (so no printf and probably many other system calls), for example bit banging some GPIO pins with direct register access, without being interrupted by the task scheduler or other interrupts. Tested with the image "Linux Console (kernel 4.5)", version 1.3, 2018-03-15 fromthis page. No hwlib.h or socal.h etc. required, you can even compile it on the system itself. I could use it to access an Avalon memory mapped VHDL component I wrote with qsys, and accessing the registers with some calculations and accessing the SDRAM in a loop needed always about 15 us, without much variation. When the interrupts were running, sometimes the loop time was nearly a millisecond and it fluctuated a lot, depending on the number of loops and the rest of the system.