FPGA - Debounce with Latch - Page 1
Forum section: electronics / beginners

author: ElectricGuy
author_rank: Regular Contributor
timestamp: September 25, 2015, 03:09:40 am
content: HI;I'm very new to FPGAs, so please, go easy on me!I have a push button an FPGA and a LED.I'm trying to code in VHDL a program to on the press of the switch, debounce it and lights up the led. When i press again, it switchs off the led, and so on;At this moment i have the debounce part, but i really don't know how to get the latching part.I'm coding in VHDL.Any help?CODECode:use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity teste isGENERIC(counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)Port (SELOPE : in STD_LOGIC;OPERATION : out STD_LOGIC;CLOCK : in STD_LOGIC);end test;architecture Behavioral of test isSIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flopsSIGNAL counter_set : STD_LOGIC; --sync reset to zeroSIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter outputsignal H: STD_LOGIC;begincounter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counterprocess(CLOCK)beginIF(CLOCK'EVENT and CLOCK = '1') THENflipflops(0) <= SELOPE;flipflops(1) <= flipflops(0);If(counter_set = '1') THEN --reset counter because input is changingcounter_out <= (OTHERS => '0');ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet metcounter_out <= counter_out + 1;ELSE --stable input time is metH <= flipflops(1);END IF;END IF;end process;process(H)beginOPERATION <= H;end Behavioral;Operation is the LEDSELOPE is the Switch

author: marshallh
author_rank: Unknown
timestamp: September 25, 2015, 03:11:59 am
content: http://www.fpga4fun.com/Debouncer2.html

author: retrolefty
author_rank: Super Contributor
timestamp: September 25, 2015, 03:12:32 am
content: Quote from: ElectricGuy on September 25, 2015, 03:09:40 amNever been exposed to VHDL, but latching/toggling is usually done with some kind of flip-flop element which acts as a memory function.

author: ElectricGuy
author_rank: Regular Contributor
timestamp: September 25, 2015, 03:15:06 am
content: Quote from: marshallh on September 25, 2015, 03:11:59 amThnka for the link, but i don't even know what is a MODULE. I'm just really starting

author: ElectricGuy
author_rank: Regular Contributor
timestamp: September 25, 2015, 03:16:23 am
content: Quote from: retrolefty on September 25, 2015, 03:12:32 amYes, but i'm having dificults implementing that in VHDL

author: hamster_nz
author_rank: Super Contributor
timestamp: September 25, 2015, 03:52:48 am
content: Debounce is hard to get right. It sounds easy but it is hard,What do you really want?Do you want low latency? (e.g. change at the quickest /shortest press).Do you want press-and-hold to blink?What time windows are you thinking for filtering the bouncing?If you know what you really want it gets easier far easier to implement. If you don't know exactly what you want it will always seem wrong.It also might pay to think of it as filtering noise out of a continuous stream of 0s and 1s from the switch....0000000010101010111010010101011111111111111111111110101010101000000000000...needs to become:...0000000000000000000011111111111111111111111111111111111111111111111100000...The easy bit is toggle the LED on each 0-to-1 transition of the filtered signal.The least-effort way is usually that the output signal and input signal must differ for 'n' cycles before the output state changes - something like this hack (which has not been checked or tested at all!)Code:-- set the LED to the state of toggle.led <= toggle;process(clk)beginif rising_edge(clk) then-- Toggle when output_state has changed from 0 to 1.if filtered = '1' and filtered_last = '0' thentoggle <= not toggle;end if;-- remember the last output state so we can detect changes in output_statefiltered_last <= filtered;if filtered = input_state thencount <= count_max;else-- count down and change when count = 0if count = 0 thenoutput_state = not output_state; -- flip output to other state.count <= count_max;elsecount <= count-1;end if;end if;end if;end process;

author: TerminalJack505
author_rank: Super Contributor
timestamp: September 25, 2015, 03:56:23 am
content: My VHDL is really rusty but I think you are looking for something like this:Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity Toggle isgeneric (POR_Q : std_logic := '0' -- Reset value of Q.);port (-- Inputs...Clk : in std_logic;Rst : in std_logic; -- Asynchronous.-- Output...Q : out std_logic);end Toggle;architecture Behavioral of Toggle isQOut : std_logic;begin-- Toggle the output 'Q' each time a positive-going edge is seen on Clk.-- If Rst is asserted then 'Q' is set to POR_Q.process (Rst, Clk)beginif Rst = '1' thenQOut := POR_Q;elsif rising_edge(Clk) thenQOut := not QOut;end if;Q <= QOut;end process;end Behavioral;

author: ElectricGuy
author_rank: Regular Contributor
timestamp: September 25, 2015, 10:36:42 am
content: Hi TerminalJack505 and hamster_nz;My problem at this point its not debounce, its the latching part.My code is working good for debounce, but it does not latch. The outupt of my debounce is;Code:H <= flipflops(1);And then i you turn on the ledCode:process(H)beginOPERATION <= H;But it only turns on when i press the button, and i want to latch the led, on press turns on, on press turns off.I'm going insane, but like i said before, i'm really a beginner!

author: hamster_nz
author_rank: Super Contributor
timestamp: September 25, 2015, 10:51:20 am
content: Quote from: ElectricGuy on September 25, 2015, 10:36:42 amWith bad form:Code:led_toggle_proc: process(flipflops(1))beginif rising_edge(flipflops(1)) thenled <= not led;end if;end process;with better form:Code:led_toggle_proc: process(clk)beginif rising_edge(clk) thenif flipflops(2) /= flipflops(1) thenled <= not led;end if;flipflops(2) <= flipflops(1);end if;end process;

author: ElectricGuy
author_rank: Regular Contributor
timestamp: September 25, 2015, 11:06:09 am
content: It is working with the "Bad_Form", but still missing some press of thw button.With the "better form" is acting worst, it looses even more press fot the buttonThank you hamster_nz

author: that_guy
author_rank: Contributor
timestamp: September 25, 2015, 02:43:26 pm
content: Probably not your main bug but...Code:counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)19 bits at 50Mhz does equal 10.5ms however...Code:SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter outputThat's a 20-bit vector.

author: ElectricGuy
author_rank: Regular Contributor
timestamp: September 25, 2015, 02:48:05 pm
content: Quote from: that_guy on September 25, 2015, 02:43:26 pmThank you that_guy, but its not that. i'm changing that several times to do the experiences and didn't update the code here.

author: hamster_nz
author_rank: Super Contributor
timestamp: September 25, 2015, 07:33:18 pm
content: What's the latest code look like?

author: tggzzz
author_rank: Super Contributor
timestamp: September 25, 2015, 08:45:13 pm
content: It would help the OP if he can start thinking in a way that will enable more complex finite state machine (FSM) designs to be easily expressed, implemented, debugged and modified.This is a good short introduction to a simple flexible style:http://www.gaisler.com/doc/vhdl2proc.pdf

author: ElectricGuy
author_rank: Regular Contributor
timestamp: September 25, 2015, 10:35:32 pm
content: Quote from: hamster_nz on September 25, 2015, 07:33:18 pmHi hamster_nz;I'm not on the computer right now, but i will post the latest code here tomorrow.It is working, but not the best aproach for sure.Quote from: tggzzz on September 25, 2015, 08:45:13 pmYes, i know that, but honestly i don't know how to code an FSM in VHDL yet. Hope to get there.I'm just beginning. Thanks for the link!

author: tggzzz
author_rank: Super Contributor
timestamp: September 25, 2015, 11:28:42 pm
content: Quote from: ElectricGuy on September 25, 2015, 10:35:32 pmFirst learn how to think in terms of FSMs. From personal experience they are useful in many circumstances from hardware through to software running in distributed enterprise applications servers. Too many "softies" think FSM==compiler parsing, so you'll have an advantage over them.Secondly read and understand examples.Thirdly, don't be put off - interesting and worthwhile things always take a while to master.