Product Redesign using FPGA, project suggestions - Page 1
Forum section: electronics / projects

author: Rymanvw
author_rank: Newbie
timestamp: February 13, 2013, 08:20:31 pm
content: Hi,I am working on a complete redesign of a product because the manufacturer of a part is no longer reliable, and the entire system was based on this one part.I have a 12 to 32 channel array of the same device that I want to read from simultaneously & continuously using labview.I want to use USB to connect this device to a computer.What communication protocol would be best to capture the data from each channel, I2C, SPI, Analog?The device has either I2C, SPI, or analog interfaces.Would an FPGA be useful in this application. (I want to read samples at ~1000 Samples/Second/Channel & about 16-bit resolution)Any suggestions would be very much appreciated. Let me know if you need anymore information.-Ryman

author: fcb
author_rank: Super Contributor
timestamp: February 13, 2013, 08:40:05 pm
content: Loads of ways to do this, depending on BOM cost, development cost and required jitter etc...If development speed was an issue, then just use an FTDI FT232H and 4x 74HC373's and perhaps a couple of gates of glue logic., would work with a bunch of cheap delta-sigma ADC's. You can get the UM232H module from Farnell/Digikey to get going.If BOM is an issue, then a PIC24 as USB host & interface.Or a the new FTDI cheaper units (implement a 1Mbaud serial bus poss. via optocouplers if you want isolation) and a cheap micro-controller to mux the data.If you needed a really low BOM (and were feeling brave) then you could build a big analog mux (4x4051B's) and run a single converter at 32+KHz. I kinda like that approach..

author: Marco
author_rank: Super Contributor
timestamp: February 13, 2013, 09:38:51 pm
content: Quote from: Rymanvw on February 13, 2013, 08:20:31 pmDoes the internal ADC of the device satisfy this requirement?

author: Rymanvw
author_rank: Newbie
timestamp: February 14, 2013, 04:08:51 am
content: QuoteI have not selected the device yet but I will come as close to 1000 SpS as possible.BOM is not so much of an issue I would like to keep the number of components down and I would like to keep the price below $1000.00 (at the very max)development speed is some what a concern but not the driving factor.What is the best approach to get simultaneous sampling?

author: jeroen74
author_rank: Frequent Contributor
timestamp: February 14, 2013, 06:01:21 am
content: One ADC per channel, preferably one with a dedicated Start Of Conversion input. I probably would use an USB enabled microcontroller of your favourite flavour. I see no real use for an FPGA here other then unnecessary complexity. Sampling speed is only 1KHz.

author: mrflibble
author_rank: Super Contributor
timestamp: February 14, 2013, 05:22:10 pm
content: Quote from: Rymanvw on February 13, 2013, 08:20:31 pmAn fpga sounds like total overkill for that looooow sampling rate. A microcontroller based solution will be lots cheaper, and easier to develop.

author: fcb
author_rank: Super Contributor
timestamp: February 14, 2013, 05:51:46 pm
content: LTC2470 or LTC2472 (cheap, accurate and available:http://cds.linear.com/docs/Datasheet/24702f.pdf)Parallel up all the SDI/CS/CLK lines and have a each of the SDO's feeding a seperate pin on a leggy microcontroller)You could write the whole bitbang interface for 32 ADC's in about 100 lines of assembler.

author: Rymanvw
author_rank: Newbie
timestamp: February 14, 2013, 09:59:22 pm
content: Okay so I think the route I will take is have 24 ADC's (maybe MCP3551) in parallel with a uC (maybe ATtiny13a) attached to each one. Then all of those write to a main uC (ATmega32U4) which then writes the whole data set at once to a PC via USB. (I think this is basically what fcb and jeroen74 were talking about)#1 - What communication protocol should I use between all the components (SPI, I2C, RS485)?#2 - What is the best way to bring them all into my Main uC (32u4)?#3 - Could I achieve speeds of 100 Ks/Sec/Ch, if not around what speeds should I expect?Some reasons I chose this approach, please let me know if I am wrong on any of these.#1 - I can easily change the number of devices with out having to add many expensive components.#2 - I can get simultaneous sampling.#3 - Pretty cheap.#4 - Not too complicated (Hopefully).#5 - Similar to previous system, which worked.Okay thanks for everyone's comments more input would be greatly appreciated.

author: mrflibble
author_rank: Super Contributor
timestamp: February 14, 2013, 10:25:55 pm
content: Quote from: Rymanvw on February 14, 2013, 09:59:22 pmI vote SPI.QuoteNo, you cannot. Ever. You should expect 1.001 Ksps. There, expectations properly managed.Alternative version: so what's it going to be? 1 ksps or 100 ksps? Different rates may result in different optimal solutions.If you want to keep things simple, then use a SINGLE mcu, not a conglomerate of fail waiting to happen.Q: But but, what could possibly go wrong in a system of 25 mcu?A: Build it and find out. Optionally regret your design decisions...I would look into getting a dual or quad ADC with SPI. And then as fcb suggested, you parallel the SPI data lines. You'll have 1 SCL line and 1 SDO line feeding all the ADCs. That way all the ADCs get the same commands and will clock out data from the same registers (your samples). Then you put those data lines in parallel and pump that into your mcu.The reason I suggest getting dual or quad ADCs is that way you will have 12 or 6 data input lines, not a whopping 24. That keeps things a bit more doable. But if you feel like it, 24 will also work if you GPIO pins to burn.Assuming dual ADCs you'd need 14 pins for the paralleled SPI interface, assuming you ground CS. If you want/need CS, then it would be 15 pins.

author: fcb
author_rank: Super Contributor
timestamp: February 14, 2013, 10:27:50 pm
content: Rymanvw: I'm not sure from what you say that you have a particularly solid grasp on what your trying to do - perhaps you've bitten off too much (I'm not trying to be rude).I'd sit down and carefully sketch-out what your trying to do and look at the data-flows necessary and do the math. Your talking about the MCP3551 (13.5 samples/sec, 75x slower than you specified) and asking if you can get 100K...

author: mrflibble
author_rank: Super Contributor
timestamp: February 14, 2013, 10:42:30 pm
content: While we are at it ... maybe we should not automatically assume that the design decision to require simultaneous sampling is valid.Sooooo, why do you need simultaneous sampling? Some problems do require that, but there's plenty that can be solved perfectly well with an interleaved sampling approach. If you can get away with interleaving then that simplifies things considerably. That and lower cost too.

author: eliocor
author_rank: Unknown
timestamp: February 15, 2013, 01:35:21 am
content: Before deciding what CPU/FPGA you need, I suggest you to take a look at the following ADC selection tables:http://www.analog.com/ps/psthandler.aspx?pstid=10023&la=enhttp://www.analog.com/ps/psthandler.aspx?pstid=10022&la=enhttp://www.ti.com/lsds/ti/analog/dataconverters/adc_dac_quick_search.pageonce identified what can be the best device for your needs [e.g.: 4xAD760616-bit, 8 channel, simultaneous sampling ADC] and its interface (serial/parallel) you can choose your CPU/FPGA.

author: EEVblog
author_rank: Unknown
timestamp: February 15, 2013, 06:56:30 am
content: Quote from: Rymanvw on February 13, 2013, 08:20:31 pmThen why not just use an off-the-shelf National Instruments USB DAQ instrument?e.g.http://sine.ni.com/nips/cds/view/p/lang/en/nid/203223or 32 channel of 16bit with this:http://sine.ni.com/nips/cds/view/p/lang/en/nid/209070Dave.

author: poorchava
author_rank: Super Contributor
timestamp: February 15, 2013, 10:53:15 am
content: I would say 4xADS1178. Those are octal, simultaneous sampling, 16-bit sigma delta ADCs at budgetary price of $8@1k pcs. For higher precision you can go for ADS1278 which is very similar, but 24-bit resolution but it is also much more expensive ($25@1k pcs). It communicates via SPI. The only problem is that the digital part of these operates at 1.8V standard which means that you need to use either some 1.8V compatible MCU or use some level shifter. You can also implement the SPI interface in a CPLD, which will probably be simpler and cheaper than FPGA (plus the fact that programmable logic is much more often compatible with 1.8V standard)

author: Rymanvw
author_rank: Newbie
timestamp: February 15, 2013, 02:09:31 pm
content: QuoteSorry, I should have looked at the part more closely, a colleague of mine suggested this part and I assumed it at least met our minimum specifications. I was being hasty. Thanks for pointing that out.QuoteThey do require simultaneous sampling actually. I am trying to read the state of something (which could be moving) at any given moment. If the values are not at the same moment in time they mean very little to the customer.QuoteThis option is still being considered. (We have done many projects with NI hardware and I find that it always looks like the perfect choice on paper but when actually implementing it there are all sorts of limitations. Just in my experience)Also knowledge/experience gained from this project will be used in many other projects where those types of things would be over kill.Now I have settled on only having 12 or 24 channels with maybe expanding to 32 in the future.Thanks everyone for your comments I will update you again soon.

author: andyb
author_rank: Regular Contributor
timestamp: February 15, 2013, 03:21:48 pm
content: If I were doing this I would use a Xilinx (or Altera or Actel) CPLD and a Cypress FX2 - simply because I've got experience designing USB sampling systems using these parts. If possible, I'd try to run everything on 3.3V (or less) and make it USB powered. If I was feeling lazy about clock generation (or if I needed something wonky) I might choose a CY22150 an I2C programmed clock generator.That said... I've never designed USB hardware for National Instruments (I have designed RS-232), and I'd be tempted to use somthing like a USB-6009 (similar to what Dave suggested). Check out its teardown herehttp://bardagjy.com/?p=841

author: mamalala
author_rank: Unknown
timestamp: February 15, 2013, 04:49:01 pm
content: Also keep an eye on the actual speed that you can achieve on the USB bus. Many chips only support full speed, which is 12 MBit/second.32 ADC channels at 1 KSps with 16 bits = 512000 bit/secondAt 10 KSps you already reach around 5 Mbit/second. Also, the 12 MBit full speed is the raw signalling rate. You have to consider the protocol overhead on the bus as well, which already will consume some of that bandwidth. And you surely don't want to share that USB bus through a hub with anything else, since that would steal even more of the bandwidth.OTOH, the physical interface to the ADC's can be rather simple, if you use SPI and all ADC are the same. Just provide a common clock for all ADC, a common data-in line to the ADC, and put the data out of the ADC onto seperate port pins of the same port. You can then do the demuxing on the host computer, so you will probably get away just fine with a rather small µC, like an LPC with built-in full-speed USB. Or use a CPLD to do that, plus deserializing the incomming data and have it provide a parallel data out into the µC.Greetings,Chris

author: Rymanvw
author_rank: Newbie
timestamp: March 08, 2013, 01:10:38 am
content: Hey guys so I have been preoccupied with another project but I am back now. Thanks for every ones advice it was very helpful.I was wondering if it would be possible to use something like a shift register/Latch to store the 16-bits from the ADC so that I can take all the samples at the same time by connecting all the CS pins on the ADC's together with a digital pin on my uC, and then go back and read all the latches one at a time with my uC? I know I would be able to achieve this by having 24 ADC's and 24 uC's that then write to one main uC which then writes to the computer, but as mrflibble pointed out it would be a nightmare to have 25 uC to get to work together. Also I could use shift registers but I would need 48 8-channel (much cheaper) shift registers then I would need another 3 shift registers with a bunch of switches and the bus would be huge. I feel like there is a IC that is made for something like this. I have looked at Latches but I am not exactly sure if they are what I am looking for, I am not exactly sure what it means when Digikey askes Circuit type: 1:8, 12:24, 8:8, 4:4. I've tried to google it but I am not exactly sure what to look for.An IC that has a clocked input that will read the 16 bits then can do a simple SPI output and only needs to hold 16 bits. I guess I could use EEPROM but I haven't found them that small.The ADC I am most likely going to use is a AD7683http://www.analog.com/static/imported-files/data_sheets/AD7683.pdfThe uC I probably will use is a ATMEGA32U4. May use a faster chip is necessary.Thanks again for the help.-Ryman

author: Rymanvw
author_rank: Newbie
timestamp: March 10, 2013, 01:19:03 am
content: Is there not an IC that can do this?

author: TerminalJack505
author_rank: Super Contributor
timestamp: March 10, 2013, 02:12:03 am
content: If I understand what you're trying to do then the IC might be what's known by some vendors as a Data Acquisition System. These are multichannel ICs that will do the ADC sampling at a certain rate and pass it off to a processor.Search throughProduct Index > Integrated Circuits (ICs) > Data Acquisition - ADCs/DACs - Special Purposeon Digikey and select the "DAS" types to filter it down. Their filter leaves a little to be desired. It doesn't show the number of channels each part supports so it may be a matter of looking through a bunch of datasheets to find what you're looking for.Here's onewith 8-channels, 16-bit ADC and 200kS/s, for example. It claims to do simultaneous sampling on all the channels. So 4 of these and a MCU might do what you're needing.Edit: After posting I re-read the thread and it seems a couple of people have already mentioned using DAS ICs. eliocor even mentioned the same one (AD7606) I used as an example. Whoops.