Effect of variable size in microcontrollers. - Page 1
Forum section: electronics / beginners

author: DG41WV
author_rank: Regular Contributor
timestamp: July 09, 2018, 02:24:02 pm
content: Hi, I would like to know if there is any advantage in using variables that are smaller than the ram size. for example the STM32F103C8 seems to have a 32bit wide ram. would a 8bit variable take up the whole address or can the compiler put more variables in that memory. I'm using the GCC compiler btw.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 09, 2018, 02:35:02 pm
content: The compiler will do whatever you tell it to.What do you really want to do? Optimize for code size? RAM use? Speed?Tim

author: exit_failure
author_rank: Regular Contributor
timestamp: July 09, 2018, 02:43:08 pm
content: This is not something that can be answered universally as it depends on the interplay of the processors architecture and the exact compilation options you choose.For example there is alignment and padding. This becomes especially important if you use data types of different lengths. These describe how your data is stored in RAM. There always will be a trade-off between memory usage and access time. Usually this it not something that is determined on a hardware level but by compiler optionsThe Wikipedia article explains it quite well:https://en.wikipedia.org/wiki/Data_structure_alignmentPlease feel free to ask, if you don't understand something or have any other questions left.

author: stmdude
author_rank: Frequent Contributor
timestamp: July 09, 2018, 02:46:09 pm
content: In _this particular case_, GCC would behave like this:Code:uint8_t a,b;printf(%p,%p\n",&a,&b);0x10000000,0x10000004Because it's more efficient (faster) for it to fetch on a 4-byte boundary.However, you can tell GCC that you care more about size than speed like this:Code:#pragma pack(1) // Set packing/alignment to 1 byteuint8_t a,b;#pragma pack() // Restore default packingprintf(%p,%p\n",&a,&b);0x10000000,0x10000001(All this is typed from memory, so.. No guarantees, but this is basically how it works)

author: DG41WV
author_rank: Regular Contributor
timestamp: July 09, 2018, 03:17:09 pm
content: Thanks for the answers.I'm not particularly trying to do something specific, but was just curious of what would happen if I used a uint16_t instead of a uint8_t. So, from the answers on this thread it would be safe to assume unless you ask the compiler to optimize for space, it would use a whole address space on the ram, right?

author: exit_failure
author_rank: Regular Contributor
timestamp: July 09, 2018, 04:20:23 pm
content: Quote from: DG41WV onTodayat 01:17:09 amWith 32bit word length you can fit a two 16 bit types into one word as long as they are aligned with that word. And as far as I know, this is also what usually happens. Doing so is in most aspects advantageous. You can load two words with one memory access and you save space.Consider the following two examples:You have two structs:Code:struct {uint16_t a,uint16_t b,} sixteen_sixteen;This struct would be placed in the memory like this:|a|a|a|a|a|a|a|a|a|a|a|a|a|a|a|a|b|b|b|b|b|b|b|b|b|b|b|b|b|b|b|b|Code:struct {char c,uint16_t a,uint16_t b,} one_sixteen_sixteen;This struct would be placed in the memory like this (p=padding):|c|p|p|p|p|p|p|p|p|p|p|p|p|p|p|p|a|a|a|a|a|a|a|a|a|a|a|a|a|a|a|a||b|b|b|b|b|b|b|b|b|b|b|b|b|b|b|b|p|p|p|p|p|p|p|p|p|p|p|p|p|p|p|p|Do you understand why?

author: DG41WV
author_rank: Regular Contributor
timestamp: July 10, 2018, 12:45:32 pm
content: Quotebecause the variables will be placed at 16bit intervals. like base address +16 bits*n ?

author: exit_failure
author_rank: Regular Contributor
timestamp: July 10, 2018, 02:03:39 pm
content: Quote from: DG41WV on July 10, 2018, 12:45:32 pmExactly. I just wanted to make sure there was no misunderstanding because people in university seemed to have a lot of difficulties to get their heads around that for some reason...