Recommendations for  FPGA books - Page 1
Forum section: electronics / general

author: rhb
author_rank: Super Contributor
timestamp: February 09, 2018, 08:43:46 pm
content: I'm completely new to FPGAs. I've got a Zybo z7-20 and the Zynq Book and the other FPGA book that Digilent sells on the way. I'd like to supplement that with one or two non-vendor specific books on FPGAs. Or a Xilinx book and an Altera or Lattice book if that makes more sense.Recommendations? I'm looking for graduate level EE textbooks that provide a good overview of FPGAs and programming them.

author: jmelson
author_rank: Super Contributor
timestamp: February 09, 2018, 09:23:59 pm
content: Really, there is no Xilinx or Altera book. Most of what you need to know is more aimed at synthesis languages like VHDL or Verilog, with an emphasis on how that gets translated into just about any FPGA family. Altera or Xilinx makes almost no real impact on what you code in the HDL. There are some differences in I/O features available, and at least with Xilinx, they have a bunch of different families that have different I/O features. So, look more closely at books about designing with HDLs, and then get the specific info on internal architecture and I/O features from the respective company's datasheets.At least, Xilinx tells you a LOT about internal architecture (which really is not of much use, you just let the synthesis tools deal with that) and the I/O architecture, which you do need to understand what can be done in the I/O blocks easily.Jon

author: nctnico
author_rank: Super Contributor
timestamp: February 09, 2018, 10:43:00 pm
content: Xilinx has a synthesis manual which describes how HDL gets transformed into internal FPGA structures. Unfortunately many of the VHDL examples are translated from Verilog and not optimised for VHDL (IOW: the VHDL examples could be made much simpler).

author: NorthGuy
author_rank: Super Contributor
timestamp: February 09, 2018, 11:05:40 pm
content: Xilinx has good docs which explain what's inside. But perhaps it is more of academic interest.

author: rstofer
author_rank: Super Contributor
timestamp: February 09, 2018, 11:10:52 pm
content: Go to Amazon and search, there are many books on VHDL, Verilog and probably SystemVerilog. Any of the books by Pong P. Chu will be excellent. I have "RTL Hardware Design Using VHDL".How about a book with a project? You can build an ARM core (subset) using the code provided in "Digital Design and Computer Architecture - ARM Edition" by Harris and Harris.A project that is probably more approachable is "LC-3" (Google for LC-3 or LC-3b). Universities are using this project in upper division courses. Among other things, it comes with a C compiler and an Assembler. The book is "Introduction to Computing Systems - From Bits & Gates to C & Beyond" by Patt and Patel.You might check Alibris.com for used copies or even discounted new copies.There are MANY books on the subject. Not all are multi-hundred dollar text books.

author: Howardlong
author_rank: Super Contributor
timestamp: February 09, 2018, 11:29:17 pm
content: If you already have reasonable lower level embedded electronics experience, I found the following video unlocked my brain. I’d attempted several times in the past. This is what did it for me, it’s both clear and concise.https://youtu.be/SmdEP_ZsBgM

author: rhb
author_rank: Super Contributor
timestamp: February 10, 2018, 12:49:32 am
content: An SoC like the Zynq is a von Neumann machine with ENIAC style plug boards used to connect machine elements. This was done briefly in the early 50's by processing groups with prior experience in plug board programming. An FPGA is a purely electronic implementation of plug boards.The Zybo comes with a license to use the Vivado software design tools. About which I know little or nothing beyond it exists.The 2nd book is for VHDL. There's a version for Verilog. So I'm presuming that VHDL is the lingua franca of Vivado.I've got logic descriptions for quite a few 40's and 50's computers that should be sufficient and easy to synthesize by hand. It might be a useful learning project to create VHDL or other synthesis inputs which reproduce historic machine semantics and timing.My ultimate target is to be able to configure instruments like the Instek GDS-2000E line. The Zybo is for development work before moving the execution to my GDS-2072E. To monitor all this I have an MSO-2204E. The first project is to implement a sampling system which includes compressive sensing as an option using a COTS DSO as the development platform.

author: rstofer
author_rank: Super Contributor
timestamp: February 10, 2018, 01:18:18 am
content: Quote from: rhb on February 10, 2018, 12:49:32 amNo, Vivado supports VHDL and Verilog and a project may use both. As near as I can tell, it doesn't support SystemVerilog but I'm not sure about that.I don't want another language war (and there will be one) but if you like C, you should probably learn Verilog. If you like Pascal, you should probably go with VHDL.The ARM book I linked above uses SystemVerilog and VHDL so, with Vivado, you would have to choose VHDL if you wanted to use the provided code.

author: asmi
author_rank: Super Contributor
timestamp: February 10, 2018, 01:38:18 am
content: Quote from: rstofer on February 10, 2018, 01:18:18 amOf course Vivado supports SystemVerilog!

author: rhb
author_rank: Super Contributor
timestamp: February 10, 2018, 01:51:12 am
content: Pascal is one of the few languages I actively dislike.It seems then, that I ordered the wrong book. The Verilog version showed as out of stock. But they had other website issues. I had planned on getting both versions just to evaluate the VHDL vs Verilog question.As for the book suggestions, I plan to get them. I have 4 editions of "Computer Architecture: A Quantitative Approach" by Patterson and Hennessy and have read 3 cover to cover, So the suggestion of Harris and Harris is quite interesting.

author: NorthGuy
author_rank: Super Contributor
timestamp: February 10, 2018, 01:57:36 am
content: Quote from: rhb on February 10, 2018, 12:49:32 amIf you're going to do high speed sampling, you need to go a little-bit hardware specific. Xilinx has few docs about this:ug471: documents IO capabilities, incuding ISERDESxapp524: sort of a reference design for ADC sampling

author: rhb
author_rank: Super Contributor
timestamp: February 10, 2018, 02:07:43 am
content: Thanks. I'll read those. For my purposes, it would be a pair of external ADCs sampling at 500 MS/S . But I also want to implement a high speed, deep buffer LA.

author: helius
author_rank: Super Contributor
timestamp: February 10, 2018, 02:22:10 am
content: The difference in syntax between Verilog and VHDL is relatively unimportant, and VHDL's syntax is anyway nothing to do with Pascal. It was based on Ada.The semantic differences are the only important ones to consider: Verilog is completely untyped (unlike C) and has rather footloose and fancy free notions of structure and scope. I think the better comparison is BASIC.

author: hamster_nz
author_rank: Super Contributor
timestamp: February 10, 2018, 02:26:47 am
content: Quote from: rhb on February 10, 2018, 02:07:43 amThose ADCs will be technically challenging to implement. It is towards the high end of FPGA capabilities - not a beginner project.What interface would the have? A multi-Gb/s serial stream?

author: asmi
author_rank: Super Contributor
timestamp: February 10, 2018, 02:28:31 am
content: Quote from: rhb on February 10, 2018, 02:07:43 amIn this case you will need DDR3. So you will have to choose Xilinx because it's the only vendor that provides DDR3 memory controller IP for free.Also these ADCs probably use LVDS so you will need to learn how to use ISERDES. It's not hard at all, but it's important to understand what exactly is happening when you invoke this or that component. You never going to remember what each block does (7 series documentation is well over 10K pages!), so it's important to understand what's going on - this way you'll be able to quickly find what you need.For now, remember the number UG953 - this document contains a listing of all hard (and some soft) IP blocks provided by Xilinx, this is the document you will be referring to a lot during coding.Also if you decide to use SystemVerilog -hereis a great cheat sheet for most language constructs, again you will likely be referring to it a lot in the beginning.

author: NorthGuy
author_rank: Super Contributor
timestamp: February 10, 2018, 03:41:12 am
content: Quote from: rhb on February 10, 2018, 02:07:43 amLA is probably easier. IDDR has an oversample mode which lets you sample at 4x the clock frequency. Say, with 500MHz clock you can sample at 2Gs/s. Although RLE encoding at these speeds will be challenging.

author: amspire
author_rank: Super Contributor
timestamp: February 10, 2018, 03:55:21 am
content: Quote from: rhb on February 10, 2018, 02:07:43 amIf you can live with a smaller buffer with run time compression instead of a large buffer, there is a lot of room to improve on the Intronix Logicport LA1034 which does not use extra RAM chips. It can only buffer about 2000 transitions, but in many cases, you can do a lot with that, particularly if you have a very flexible trigger. The nice thing about run time compression is that the amount of data that can be stored is not dependant on time - only on the number of transitions. The Logicport software can do a 10 hour capture at 200MHz as long as there are under 2000 transitions.Basically the Logicport is 34 channel LA and it only stores a 34 bit vector if one of the channels changes from the previous clock cycle. At 500MHz, it doesn't compress - it just stores just over 2000 sequential clock cycles and stops.Another thing the compression gives you is you can use it with USB Full Speed mode (12MBits/sec) which means it works well with the cheap USB Full Speed isolators.https://www.eevblog.com/forum/reviews/intronix-logicport-34-channel-logic-analyzer-teardown/msg70141/#msg70141The LA1034 was based on an Altera Cyclone 1 EP1C4F324C6 with 78K bits of RAM and you can now get Cyclone V chips with 2000K bits for under $40. If your FPGA budget can go to $160, you can store 100 times the Logicport capacity.If you want to get the feel of the Logicport, you can download the software and try it in demo mode.http://www.pctestinstruments.com/downloads.htm

author: m_t
author_rank: Contributor
timestamp: February 10, 2018, 01:59:46 pm
content: Here are some resources for both VHDL and Verilog I found useful:https://github.com/m-thu/sandbox/blob/master/URLs.md#vhdl,https://github.com/m-thu/sandbox/blob/master/URLs.md#verilogSome of my notes on VHDL working through "The Designer's Guide to VHDL":http://mthu.freeshell.org/tmp/notes.pdf(LaTeX source:https://github.com/m-thu/sandbox/blob/master/notes.tex).

author: rhb
author_rank: Super Contributor
timestamp: February 10, 2018, 04:23:11 pm
content: I've started on UG471. That will probably keep me out of mischief until the Zybo arrives.Low end DSOs are sampling at 2 GS/S using the low end Zynq chips and a pair of ADCs. So it's not a matter of if, but of how.

author: NorthGuy
author_rank: Super Contributor
timestamp: February 10, 2018, 09:29:58 pm
content: Quote from: rhb on February 10, 2018, 04:23:11 pm2 Gs/s is not a limit. You can go up to 5 Gs/s (possibly more) if you have an appropriate ADC. The problem is dealing with all the data. At 5Gs/s, single channel produces 40Gb/s, 2 channels will produce 80Gb/s. If you want it somewhat deep, you need to store this somewhere. 1333 MHz DDR3 can possibly accept about 1.2Gb/s which means you need 64-bit wide memory - 80 data pins plus 30-40 control and address pins. This is 3 banks. If I remember correctly, your Zynq doesn't have so many HP pins. If you go with HR pins, you'll probably get even slower memory speeds and thus you will need even wider memory. Thus your real bottleneck is memory.

author: Mr. Scram
author_rank: Super Contributor
timestamp: February 10, 2018, 09:39:52 pm
content: I liked "Free Range VHDL" and it's totally free.http://freerangefactory.org/

author: legacy
author_rank: Super Contributor
timestamp: February 10, 2018, 09:47:31 pm
content: I can give some "sample" pdf of books by emailcontact me by PM

author: rhb
author_rank: Super Contributor
timestamp: February 11, 2018, 12:17:34 am
content: I just finished reading the Vivado High Level Synthesis manual. I'm highly impressed. It was clear and the programmer's model was very comfortable. Quite clearly I'll use those tools to program the Zybo. Most importantly, I know what sort of interface I'm dealing with to develop code.The really cool part about FPGAs is I'm not thinking about cache architectures someone else designed and I have to figure out how to live with. The last time I got this far down in the dirt was developing seismic imaging code on a DEC Alpha 164LX.I'm very curious to see how long it takes to implement a general sampling function that reads N bits at maximum clock speed. And how fast it can go.I'd been feeling a little intimidated after reading a couple thousand pages of Xilinx documentation. My comfort level has gone up tremendously. I have steered clear of FPGAs (and GPUs) for a long time because of the programming effort required. The toolset is clearly much better developed.

author: james_s
author_rank: Super Contributor
timestamp: February 11, 2018, 01:51:22 am
content: Personally I found Free Range VHDL to be very helpful when I was starting out. Of course it won't be much use if you prefer to use Verilog. The price is right though.http://www.gstitt.ece.ufl.edu/courses/eel4712/labs/free_range_vhdl.pdf

author: rhb
author_rank: Super Contributor
timestamp: February 26, 2018, 04:48:35 pm
content: I have ordered both the 'By Example" books by Blaine Readler and downloaded "Free Range VHDL". So I think I've got the basics covered for now. I also got "The Zynq Book" and "Digital Design Using Digilent FPGA Boards".I'm still looking for suggestions for a 2nd semester or graduate level book on FPGAs. Something that goes into the design and implementation of FPGAs themselves rather than their use.Now if I can just remember what all these new acronyms mean.And yes, I am acutely aware that what I want to do is hard. Normal ADC sampling is the easy case. I expect that sampling at random clock intervals will be seriously difficult to do at high speed.

author: jgalak
author_rank: Regular Contributor
timestamp: March 05, 2018, 09:49:27 pm
content: Quote from: rstofer on February 09, 2018, 11:10:52 pmI just finished reading this - teaches you two things at once - low level architecture design, and basics of ARM programming. Working my way through the labs now, quite fun. The labs are written for an Altera DE2 board. The current version, DE2-15, is like $6-700, but you can get the older DE2s on Ebay for around $100. I got one that was in great shape, even had all the CDs and accessories (neither are actually necessary).It uses an older Cyclone II chip, so you'll need to download an older version of the Altera tool chain, but it works fine on Win10.Another nice thing about this book is that it covers both SystemVerilog and VHDL, so you can choose either (or both) to learn.

author: james_s
author_rank: Super Contributor
timestamp: March 06, 2018, 04:43:59 am
content: The DE2 is a nice board, it has a spacious FPGA and comes well equipped with peripherals. I do find it annoying that there are multiple versions all called DE2 so watch for the suffix.

author: Mattjd
author_rank: Regular Contributor
timestamp: March 08, 2018, 11:00:48 pm
content: So these aren't books per say but I've found these to be incredibly useful in my journey through FPGAAdvanced Synthesis Cook Bookhttps://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/stx_cookbook.pdfRecommended Coding Styles in Quartushttps://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/HDL_style_qts_qii51007.pdfQuartus Design and Synthesishttps://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts_qii5v1.pdfAltera IP Core and Megafunction literature for your board/chiphttps://www.altera.com/support/literature/lit-ip.htmlThe last one is super useful because why not use already designed solutions (unless you're in it for learning)I once had to build a 64 bit processor on a FPGA for a course. I didn't know about these prior or during but soon found out after, wish I knew from the start!

author: rhb
author_rank: Super Contributor
timestamp: March 08, 2018, 11:44:24 pm
content: Thank you. I'll check those out. I only write code when I run out of excuses for not doing it. And as I plan to implement compressive sensing I'm sure I'll get a workout no matter what.I bought both of Blaine Readler's " VHDL/Verilog By Example" books. I clearly prefer Verilog. They are great for evaluating your language preference as they show the same tasks in both languages.At this point I'm still looking for a chip design and fabrication process level book on FPGAs if such a thing exists. The Xilinx documentation looks to be pretty thorough. The ability to prototype on a CPU and move the compute intensive parts to the FPGA is hugely appealing.I got a second hand Avnet MicroZed for my initial foray before I move over to the Zybo Z7-20. The Digilent board is nice, but they have a bit of an attitude problem about their out of box demo. Avnet keeps their demos up to date with Xilinx.At the moment my biggest problem seems to be not having things such as the right height and screw size board spacers and having to order more stuff. My other project is a precision XY stage using linear rail and ballscrews. That's a good bit more work than just mounting some dev boards in a box.

author: james_s
author_rank: Super Contributor
timestamp: March 09, 2018, 02:11:46 am
content: I wish I could say I preferred Verilog, as it's certainly far more useful in the professional world, at least in the USA. For some reason the languages I gravitate toward are amongst the least useful in the real world.