Hantek DSO3000A Series - improvements required! - Page 1
Forum section: electronics / testgear

author: Scratch.HTF
author_rank: Regular Contributor
timestamp: October 31, 2017, 02:30:37 am
content: This is a good oscilloscope, but it is let down by poor firmware and host software.From what I know, the interconnection between soft FPGA (Xilinx XC6SLX16FTG256) and SOC (Samsung S3C2416 – 400 MHz) is a HS-SPI bus operating at 1.0 MHz for control with three additional signals for FPGA code loading and has a parallel bus (most likely the OneNAND/SRAM/ROM/NOR flash interface, which could possibly have DMA) for acquisition, but the FPGA should be able to operate on a faster HS-SPI data rate (up to 50 MHz as per the SOC specification).I noted when I built a simple VGA interface (79.36 Hz - VGA inputs on most LCD controllers and VGA-HDMI converters only handle up to 75 Hz), it only displays a Hantek logo with a QR code (all static), so therefore, internal video activity is not slowing down this unit.The following enhancements (with different host software - Android host software (with USB OTG) would be good!) can be added without the need to reprogram the soft FPGA, but I am happy to provide a list of enhancements including waveform segmentation on each trigger with FPGA reprogramming (different FPGA definition files can be reloaded without power cycling):* Address a serious bug where the Sampling Rate does not increase proportionally up to a certain extent when Memory Depth is changed e.g. 1mS/Division has 100K sample rate on 1.6K Memory Depth and should increase to 1M sample rate when changed to 16K Memory Depth for the same Division time.* Increase frequency of data output to USB Device or Ethernet port e.g. command for sending data continuously until a Stop command is sent.* Send data packets to USB Device or Ethernet based on Memory Depth e.g. send 16K samples per cycle when Memory Depth is set to 16K.* Query current Sampling Rate by the connected host.* Add user programmability of the Sampling Rate.* Loading (and saving) of waveforms to a storage device on the USB Host port or the SD card.* FTP server (via USB Device or LAN)* Remote FPGA code loading (code can be reloaded without power cycling)* Remote firmware updating* Direct SPI bus control while retaining original remote control commandsI am also happy to provide detailed hardware information on request.

author: lundmar
author_rank: Frequent Contributor
timestamp: October 31, 2017, 02:45:43 am
content: If the Hantek DSO3000A features LAN/VXI and supports screenshot capturing via SCPI commands then I'll happily add screenshot support to lxi-tools (https://lxi.github.io) for this device.

author: Scratch.HTF
author_rank: Regular Contributor
timestamp: November 01, 2017, 02:46:36 am
content: I found a Linux console port inside on connector J7 (square pad denotes Pin 1):1 +3.3V2 GND3 TxD (at scope)4 RxD (at scope)CAUTION: All inputs and outputs are of the +3.3V type, any other levels will cause damage!Serial terminal settings are: 115200, 8 Bits, No Parity, 1 Stop Bit, No Flow Control, Terminal Type ANSIHardware information which I know of:S3C2416XH-40 System Controller (400 MHz ARM926EJ with 48 MHz and 12 MHz oscillators with 32.768 kHz RTC oscillator)D9SBJ System Memory (MT47H32M16NF-25E - 400 MHz 32MB x 16 DDR2-800)D9RZH Acquisition Memory (MT47H64M16NF-25E - 400 MHz 64MB x 16 DDR2-800)K9F1G08U0E 128MB x 8 NAND Flash24L64 I2C EEPROMDM9000AEP LAN ControllerUSB Wi-Fi Module (optional)USB Hub (optional)XC6SLX16FTG256 Control FPGA (under heatsink - has JTAG)1 GSPS 8-bit Quad ADC (under heatsink - Analog Devices?)ADF4905 Timebase Generator PLL (with 10 MHz reference oscillator)LTC2601 x2 (?) 12 Bit Offset DACDAC902E 165 MSPS 12 Bit Waveform Generator DAC74HC595 Channel Relay Switching (1 per channel)74HC595 Offset Voltage Switching74HC595 Trigger Source Selection74HC4051 Offset Voltage SwitchingControl FPGA has the following functions:* Quad ADC interface* Trigger threshold levels including video trigger* Timebase control* Channel relay switching* Trigger source selection* Offset voltage DAC interface* Analog mux control* Waveform generator DAC interface* Logic analysis and generation* DDR2 SDRAM controller* PLL for waveform generatorDetails for a simple VGA DAC on connector J9 is athttps://www.eevblog.com/forum/testgear/simple-vga-dac-for-hantek-hdg2000-and-certain-others/JTAG ports:JP1 (FPGA JTAG - Square pad denotes Pin 1)1 GND2 TMS3 TDO4 TDI5 TCK6 +3.3VPROGRAM_B on the FPGA is LOW during configuration with mode pins on the FPGA being used to determine configruation mode.ARM JTAG pads9 7 5 3 1. . . . . TP71. . . . . TP7010 8 6 4 21 +3.3V2 +3.3V3 /TRST4 CPU /RESET5 TDI6 TDO7 TMS8 GND9 TCK10 GNDTDI, TCK, TMS, and TRST all have 10K pullups to +3.3V.

author: Scratch.HTF
author_rank: Regular Contributor
timestamp: November 25, 2017, 03:44:07 am
content: With regard to the sampling rate not changing proportionally (up to a certain extent), here is the Linux console debug log (for the following, all four channels have been enabled):Change to 1mS/division with 1.6K memory depth:device_sync.adc_chn_mode=ADC_CHN_MODE__QUAD physical sample_rate_value=100000 cmd:0x1,0x3ddata_pack=DATA_PACKAGE__125M__1_2_3_4pll_freq =800000000,adc_clk_div = 4trig_time=0,store_depth_value=1600,sample_rate=100000store_time_pre_trig=8000000000,store_time_after_trig=8000000000,trig_time=0count_pre=1124034,count_delay=2,count_acq=807966inter=1,div=1fpga_value =0,pc_value =0read_offset=0,read_len=1600,disp_offset=0,disp_len=1600Change to 2mS/division with 1.6K memory depth:device_sync.adc_chn_mode=ADC_CHN_MODE__QUAD physical sample_rate_value=50000 cmd:0x1,0x3ddata_pack=DATA_PACKAGE__125M__1_2_3_4pll_freq =800000000,adc_clk_div = 4trig_time=0,store_depth_value=1600,sample_rate=50000store_time_pre_trig=16000000000,store_time_after_trig=16000000000,trig_time=0count_pre=2248034,count_delay=2,count_acq=1615966inter=1,div=1fpga_value =0,pc_value =0read_offset=0,read_len=1600,disp_offset=0,disp_len=1600Change to 1.6K memory depth under 1mS/division: cmd:0x2e,0x1trig_time=0,store_depth_value=1600,sample_rate=100000store_time_pre_trig=8000000000,store_time_after_trig=8000000000,trig_time=0count_pre=1124034,count_delay=2,count_acq=807966inter=1,div=1fpga_value =0,pc_value =0read_offset=0,read_len=1600,disp_offset=0,disp_len=1600_store depth__param = 0, ret = 0Change to 16K memory depth under 1mS/divison: cmd:0x2e,0x0trig_time=0,store_depth_value=16000,sample_rate=100000store_time_pre_trig=80000000000,store_time_after_trig=80000000000,trig_time=0count_pre=8324032,count_delay=2,count_acq=8007967inter=1,div=1fpga_value =0,pc_value =0read_offset=7200,read_len=1600,disp_offset=0,disp_len=1600_store depth__param = 1, ret = 0