FPGA. Possible to create arrays that are saved in external SDRAM? - Page 1
Forum section: electronics / general

author: Boscoe
author_rank: Frequent Contributor
timestamp: September 29, 2016, 08:28:14 am
content: I don't think this is possible but it would be great if so! I wonder if there's a bit of HDL that will interface my memory controller which means I'm able to write and read to variables in my code that are being held in external SDRAM and not in the memory on the FPGA or in LEs?I have some experience in FPGA/HDL but maybe only on the level of dabbling in MCUs like writing your own basic register interfaces etc. and not using libraries and such. My project usually consist of a few modules and do basic functions.So in System Verilog we could write to an element in an array like so:foo <= bar;just in my case I would like 'foo' to me located in the external memory.Is this possible?

author: ale500
author_rank: Frequent Contributor
timestamp: September 29, 2016, 09:07:04 am
content: Verilog doesn't provide a construct like "regname <= value" for a SDRAm target, you have to use a memory controller for that.

author: AndyC_772
author_rank: Super Contributor
timestamp: September 29, 2016, 10:27:01 am
content: It can't be that simple. An SDRAM controller is a complex beast, with variable latency depending on what the SDRAM happens to be doing at any given time. It might be fetching some other block of data at the time you need something, or it might be refreshing, or it might be idle awaiting a read request, or the data you want might already have been read as part of a recent burst, and doesn't need fetching from the SDRAM at all.In an FPGA, a signal assignment inside a clocked process is deterministic. Somewhat simplified, it means, 'this signal gets its value from <wherever>, right now!'.If data has to be fetched from SDRAM, it could be many clock cycles before it's available. A process that uses data from SDRAM needs to be able to issue a request, then stall until the data is available before continuing. This is done in hardware for you in a CPU, but in an FPGA it's completely up to you to implement this logic.Even if you use an off-the-shelf SDRAM controller, you'll still need to interface and handshake with it. It can't make the underlying latencies just go away.

author: hamster_nz
author_rank: Super Contributor
timestamp: September 30, 2016, 12:42:14 am
content: Like how you can make Block Ram look as though it has zero latency by using the falling edge of the clock, you can also make SDRAM look the same, but with low performance.You just have to have enough cycles for the complete transaction (times are from memory):- Close (30ns) - Optional if you have to change Rows- Refresh (70ns) - Optional if you have to refresh- Activate (30 ns) - Optional if you have to change Rows- read or write cycle (20ns)So running the SDRAM 100MHz and the rest of the design at 5 MHz it can be made to look as if the SDRAM is very slow SRAM.You can also use burst transfers to make x8 SDRAM look like x32 RAM, greatly increasing bandwidth that can be used in the design.It might not look like much, but it could be just what you need if you are processing audio samples, or anything that requires a few megabytes of memory bandwidth with known, fixed latency.