Noise in distributed bus circuit - Page 1
Forum section: electronics / projects

author: sirhaggis
author_rank: Regular Contributor
timestamp: June 17, 2016, 02:14:57 pm
content: Hi all,I am currently working on a bus circuit which runs in the vicinity of 15-24MHz with 8 lines (i.e. 15-24MB/s). The circuit allows allow for multiple plugin modules that contain RX/TX latches to participate on the bus. Modules receive a latching/output-enable clock when they have bus access (generated by a controller board they plug into), which connects directly to the OE/LE pins on their TX/RX latches. This seems to work mostly fine, however I seem to be having some (apparent) grounding/noise issues, in which noise on the latching clock (generated by the controller board) generates spurious latch activations. On the scope the clock signal is clean at its source, but at the latch entry point there are significant spikes, enough to cause occasional latching. I am able to reduce the noise significantly by adding a wire directly between the ground near the latch and a ground point close to the clock generator. This seems to indicate to me (with my limited, self taught knowledge) that the shorter ground path is reducing noise between the two points and thus I need a better grounding strategy?? Or perhaps this is a problem with signal reflection on the clock line?Admittedly I am currently using prototyping breadboards so I'm never going to get a super clean signal, but I feel that my knowledge regarding grounding strategies and noise reduction in digital bus circuits is greatly lacking. I don't feel adequately knowledgeable to diagnose and address the various potential problems beyond a trial and error approach... Can anybody point me to some resources for understanding the finer details of bus circuits? There does not seem to be a great deal of quality material on the open web that I have found so far..Any pointers would be greatly appreciated.Thanks

author: uncle_bob
author_rank: Unknown
timestamp: June 17, 2016, 04:36:31 pm
content: HiHow big a bus system is this physically? Are we talking a couple hundred feet or a few inches? Any time you send out an edge, you have a current pulse. That pulse will *always* return somehow. If it randomly gets to pick where it comes back .... you get interesting results.Bob

author: sirhaggis
author_rank: Regular Contributor
timestamp: June 17, 2016, 04:52:58 pm
content: The current prototype has about a 10inch bus, although final design could go up to 3-4 times longer than that. So you think it is likely a reflection problem? Do you know where I could get information on properly terminating a bus to prevent this?

author: uncle_bob
author_rank: Unknown
timestamp: June 17, 2016, 05:02:25 pm
content: Quote from: sirhaggis on June 17, 2016, 04:52:58 pmHiMy guess is that it's a ground plane issue.The thing you need to watch is not the clock speed, but the edge rates on your signals. A signal that switches in one nanosecond will always generate a given spike, regardless of the clock speed it switches at. In order to change the voltage on a piece of wire, current must flow. If it does not, the voltage does not change. The faster it changes, the higher the amplitude of the current spike. The more ground impedance you have (resistance / inductance / whatever) the more you will see that current spike turned into a voltage spike.Some simple answers:1) Put in a proper ground plane under all the traces (the best solution)2) Run all the signals with a ground trace next to them (poor man's twisted pair).3) Run the signals on twisted pairs where one wire is a ground wire.Could it be reflection? Sure. In order to take care of reflections you first need to know the impedance of the transmission line that the signal is running on. To *have* that information, you need to have done at least one of the things on the list above....Bob

author: sirhaggis
author_rank: Regular Contributor
timestamp: June 18, 2016, 04:09:37 am
content: Thanks Bob, that is helpful.My only additional question then would be how to deal with noise given the modular nature of the project. There will be plugin modules containing latches that will attach to the bus data and control lines. Obviously they will be separate boards that can have their own ground plane, but the connection between modules and main board will be via a ground pin. Is this going to cause me issues? This also raises the question of how to deal with reflection, as adding modules will technically add 1-2cm of additional bus wiring per module so I can never know the actual length of the bus wiring at any given time? I'm sure there are standard ways to deal with such design scenarios, but I have yet to find any detailed descriptions of such.Thanks again

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 18, 2016, 04:38:57 am
content: What bandwidth scope are you looking with?The average ~100MHz scope is not high enough to analyze signal quality issues, especially with fast logic (anything besides 74HC, TTL and CD4000). And even HC/TTL are capable of transitions at near that speed.Remember to use correct probing technique. If the problem changes (worsens, or improves for that matter!) when touching it (by hand or by probe), then be very skeptical about the exact lumpiness in your measurements. Needless to say, probe only exactly what the receiver / logic pin is seeing: from the pin to its ground reference pin, using very short ground return lead (pull off the probe tip and wrap a paperclip around the ground shank; poke the end against whatever ground pin/via is accessible).Tim

author: sirhaggis
author_rank: Regular Contributor
timestamp: June 18, 2016, 05:01:07 am
content: I'm using a Rigol DS1054 50MHz 1GSa/s - it has occurred to me that what I'm seeing is not necessarily a detailed picture of signal quality, but the spikes I'm seeing on the scope definitely explain the spurious latching events and associated data corruption. I have definitely observed that sometimes what I see on the scope is not necessarily a reflection of what is actually happening - attaching the probes does sometimes improve or worsen the problem including in this case... when I ground the latch in question using the probe the problem seems to improve (but not disappear).I have been able to apparently eliminate the problem altogether by connecting grounds between the clock source and the target latch with a short wire, which seems to indicate a grounding problem to me? There is otherwise quite a long ground path between the two components due to the current breadboard prototype.I definitely need to work on my probing technique - I have never actually read about proper techniques, do you know of any resources for this?

author: uncle_bob
author_rank: Unknown
timestamp: June 18, 2016, 12:28:53 pm
content: Quote from: sirhaggis on June 18, 2016, 04:09:37 amHiIf you wish to do a fully reflection protected design, you will need to get quite fancy in your board layout. Rather than go quite that far, let's focus first on how to get the basics covered. They *must* be taken care of before you can deal with any reflection stuff. Unless you are using very unusual logic, it will only respond just so fast. With a 20 MHz data rate, there is no need to be using GHz gates. Since they are a bit expensive, the default is not to use them. My guess is that your problem will be fixed without going to a custom board layout with all controlled impedance traces and fancy connectors.Each signal pin should have at least one ground pin adjacent to it. Two pins are better than one. Ideally the spacing on the pins should be quite close. Anything over 0.1" is too far. The goal would be something under 0.03". That's not always possible on low cost connectors.So next step: Every other pin on the connector becomes a ground. A zig zag pattern is preferred over just making all one side ground pins. Double grounds around the clock pin are a good idea. (Yes, there are more steps if this does not fix it).Bob

author: sirhaggis
author_rank: Regular Contributor
timestamp: June 18, 2016, 12:49:10 pm
content: Hmm that could get messy. In the current design I'm running an 8bit width bus, which means the connectors have 8 bus pins plus another 4 control pins for a total of 12 signal pins. Are you saying that I will need another >=12 ground pins in such a case? The current connector design uses low cost pins headers with standard 0.1" separation. I suppose I could expand it to allow that many pins... do you think that is the most viable option?Luke

author: uncle_bob
author_rank: Unknown
timestamp: June 18, 2016, 12:59:32 pm
content: Quote from: sirhaggis on June 18, 2016, 12:49:10 pmHiIf you are going to go to full reflection suppression stuff, this has to be done first. The controlled impedance lines are even more of a pain....Indeed, running half the pins as grounds is the way it's done. You can do some sneaky stuff with power pins that are highly bypassed ( = they count as grounds in this case). You can also try to play games with two signals on one ground. It may or may not work. Simple answer is to zig zag the grounds through your 0.1" header and move on. Best guess is that once you do, it will work ok.Just in case the term isn't quite clear:Zig zag =Two row header, side A and side B, each with (say) 20 pins.Every other pin on side A is a groundEvery other pin on side B is a groundGround pins on side A are across from signal pins on side BHave Fun !Bob

author: chris_leyson
author_rank: Super Contributor
timestamp: June 18, 2016, 04:23:37 pm
content: Hi LukeIdeally for good layout every digital signal line needs it's own ground return signal line and the two signal lines should have minimum separation so the "loop area" is minimized. Easiest way to fix this is to put a ground plane underneath the signal lines, that way the ground return currents flow parallel to the signal currents and still maintain a small loop area.A signal path with a large "loop area" will behave as a single turn inductor if you like, it will radiate magnetic energy efficiently but at the same time it will pick up magnetic energy from adjacent loops and that you could consider as being magnetic field cross talk. You have to consider electric field or capacitive coupling as well as that tends to dominate at higher frequencies.As regards possible reflection from a badly matched termination, that will become important at high frequencies and one way to fix the problem would be to limit the bandwidth or slew rate of the "transmitter". A resistor in series with each output driver will help reduce the bandwidth, it's acts like an RC lowpass filter where the series resistor absorbs the high frequency energy.There are lots of things to take into consideration and I would recommend reading "High speed Digital Design" by Howard Johnson as a good start.