Can someone explain this DC load circuit? - Page 1
Forum section: electronics / projects

author: microbug
author_rank: Frequent Contributor
timestamp: September 15, 2017, 08:38:30 am
content: Hi all,I've recently started thinking about my abandonedDC load projectagain, and with a bit more knowledge and fewer overambitious targets (e.g., 16-bit output precision with no prior experience in precision circuit design) I think I'm ready to have another shot.I've been looking at various drive circuitry for IXYS linear MOSFETs. I foundJay_Diddy_B's project, which was comprehensively modelled in LTSPICE and was later (scroll down) adapted for the high gate capacitance of these linear MOSFETs. I'm having a little trouble understanding the circuit (attached) though, specifically the area in red. In comparison to others I've seen (example from Kerry Wong's 1kW load), it seems a little bizarre. What is that op-amp doing? It almost looks like an integrator?! I realise that R1 is for op-amp to FET isolation and R2/21 are a 10m current shunt, but don't really understand the function of the other highlighted components.Thanks in advance for any help

author: capt bullshot
author_rank: Super Contributor
timestamp: September 15, 2017, 09:18:35 am
content: It's a bit confusing at first view, you're right.The OPAMP and the MOSFET together form an inverting transimpedace amplifier (converting a voltage input to a current output).Your usual current sink design would have the OPAMP pos. input for the control voltage and feedback from the sense resistor to the neg. input.This one is quite the same, the only difference is the control voltage is fed to the neg. input, feedback still comes from the sense resistor to the neg. input. Pos. input is at ground.So this current source is controlled by a negative control voltage opposed to the positive voltage at your text book circuit. The cap C1 is for compensation, you'd have this one in the text book variant at the very same place.The transimpedance gain of this circuit is set by R7, R4 and the sense resistor R2-> 1V over R2 etc. would produce 100A output current, so an input voltage (at the left pin of R7) of - 24k9 / 1k (-24.9V) would have to be applied to set 10A output. Or more realistiv -2.49V for 10A.The compensation capacitor C1 forms an integrator circuit over the OPAMP, this could be somewhat easier to design than the noninverting current sink, this may be the reason for this particular design choice.Edit: didn't see the paralelled sense resitors at first.

author: microbug
author_rank: Frequent Contributor
timestamp: September 15, 2017, 01:29:38 pm
content: Quote from: capt bullshot on September 15, 2017, 09:18:35 amThanks capt, that's helped a lot. A couple more questions:Is the advantage of this circuit overthis examplejust that you can change the gain without changing the value of the shunt resistor(s)? Also, I'm still not clear on exactly what C1 does. How would the circuit behave with a different value / with C1 removed?

author: TimNJ
author_rank: Super Contributor
timestamp: September 15, 2017, 01:58:08 pm
content: Quote from: microbug on September 15, 2017, 01:29:38 pmC1 is there to modify the transient response of the control circuit.The FET capacitance and parasitic inductances of the circuit (including the test leads) will cause the circuit to overshoot and produce oscillations/ringing when a load step is applied. It will react very quickly, though. By using an adequate "integrating" cap, you provide "damping" to the system which reduces overshoot and ringing. This is at the expense of a slower response time. You can experiment until you find a happy medium that optimizes response time without too much (or any) overshoot/ringing. See attaches images, with 220pF and without any cap.

author: microbug
author_rank: Frequent Contributor
timestamp: September 15, 2017, 04:04:28 pm
content: Thanks Tim, I'll leave a header socket to experiment with then (the FET that circuit was designed for is a slightly different model).If I swap the op-amp's + and – inputs on the schematic, would the transimpedace amplifier be noninverting? I'd like to avoid a negative rail below –5V, but I'd have to implement –12V with the schematic as it currently stands.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 15, 2017, 05:37:32 pm
content: Making the current output stage non inverting just needs to apply the control signal to the non inverting input. The inverting input still stay connected as is, leaving out the resistor to the inverting input.Just swapping the inputs would make the feedback loop go crazy, so this does not work with OPs.For measuring the current one might need a negative supply anyway, as the signal is very close to GND. Depending on the OP used one might need a negative supply already.I agree that a positive control might be more convenient.

author: TimNJ
author_rank: Super Contributor
timestamp: September 15, 2017, 07:06:49 pm
content: Indeed. Can't just swap the inputs.Trying to make this work with a single positive supply reliably (it can be done), might be more work than just building a negative supply. I have used the LMC7660 in an instrumentation device with good results. Literally just needs two capacitors and you have a negative supply.

author: fcb
author_rank: Super Contributor
timestamp: September 15, 2017, 08:56:27 pm
content: One word of warning (re:TL431 ref), I've recently had a production issue with NCP431A's oscillating with a 100nF bypass capacitor - only on some 5% of units.Probably better to put the 4u7 on the potential divider.Also, why the 500Hz oscillator - is this application specific?

author: microbug
author_rank: Frequent Contributor
timestamp: September 15, 2017, 09:06:04 pm
content: Quote from: fcb on September 15, 2017, 08:56:27 pmThe circuit at the top is from Jay_Diddy_B's design, I'm only interested in the drive circuitry (the red circled bit). I think he included the 500Hz oscillator for testing (it's an LTSPICE schematic). The eventual plan is to control two IXYS linear MOSFETs with a 14-bit DAC and a PSoC 5LP prototyping kit (which includes a very nice adjustable precision (up to 20 bits) delta-sigma ADC), using the drive circuitry here. I'll substitute the op-amp for something with a lower offset voltage and will probably end up using the PSoC's internal 1.024±0.1% reference.EDIT: No doubt you'll see my own circuit turn up here sooner or laterQuote from: TimNJ on September 15, 2017, 07:06:49 pmOne of my objectives here is to have the load operable from a 12V plug pack, as I've got a lot of spare ones sitting around and it would be nice not to have to worry about mains voltages when testing/debugging it. I was planning to do a Dickson voltage multiplier (EEVBlog #473) using the microcontroller and the 5V digital to get a small negative voltage (-3.5V) so the op-amps could drive the FETs properly, but that chip looks much better as I can switch higher voltages with it. I need >8V for my FETs' Vgs to be driven high enough for 20A, I'll use that chip with my +10V analog line.Quote from: Kleinstein on September 15, 2017, 05:37:32 pmOk I think I understand this. I've attached two schematics — the old inverting design and a noninverting design, will the noninverting design work? (I won't use an LM324 in the final design.)

author: MarkF
author_rank: Super Contributor
timestamp: September 16, 2017, 01:25:22 pm
content: Take a look at the DC Load that Peter Oakes built. Included are the actual values I used for a 0-1.5A load.

author: microbug
author_rank: Frequent Contributor
timestamp: September 16, 2017, 01:28:52 pm
content: Thanks, will do

author: fcb
author_rank: Super Contributor
timestamp: September 16, 2017, 07:40:38 pm
content: Quote from: microbug on September 15, 2017, 09:06:04 pmI thought that might be why - but came to the conclusion that you'd just use an AC voltage source in spice, far less hassle. Also the fact that the author had fixed the DC current of the load & had a pot to vary the AC content makes me think this was for a specific job. Which means that it might be tuned to be stable for that particular set of circumstances.

author: microbug
author_rank: Frequent Contributor
timestamp: September 16, 2017, 07:43:59 pm
content: Quote from: fcb on September 16, 2017, 07:40:38 pmReviewing Jay_Diddy_B's post on his topic, I think you're right. He'd already made a DC load, and was making a 'dynamic load' — presumably one that could test transient response?

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: September 18, 2017, 03:14:50 am
content: Hi microbug and the group,I was a little late to the party. I didn't realize that you were discussing my project till today.I can answer a few of the questions that have been raised, some of them have already been answered correctly, but you might as well hear if from me.1) Two supplies, positive and negative voltages were used to make the circuit design easier. By having two supplies I am not restricted to rail-to-rail op-amps. Strictly speaking you don't rail-to rail performance, but you need an op-amp that includes the negative rail in its common mode range. The output does not need to go the negative rail because of the gate threshold voltage in the MOSFET. The LM324 will work. The LT1014 is a better LM324.2) The inverting configuration allows me to sum two signals. There is a dc level, one potentiometer and a pulsed level the other potentiometer. This let you set a minimum level and maximum level for transient load testing.The load is connected to a power supply and the pulsating load current can be used to evaluate the transient performance of the power supply.3) 500Hz was chosen as the test frequency. Most power supplies being tested will settle (recover) within 1ms. The oscillator is part of the real circuit. If I needed a pulse generator for the modelling I would have just used a voltage source and the PULSE directive.The load was not designed for a specific job. It was designed to test generic power supplies. I have built several versions. The original was 5A dc + 5A pulsed. I then built a low current version that was 1A dc plus 1A pulsed.4) The capacitor in the op-amp circuit is to ensure control loop stability. This was discussed at length in my original thread.It is important that the load is faster than power supply being tested. This was illustrated in this message:https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg1128310/#msg11283105) The circuits presented with the IXYS MOSFET, was theoretical. I have not built and tested this version. It was done at the request of forum member BravoV. It should work because it is designed using the same principles as the loads that have been built and tested.6) Kerry Wong's designhttp://www.kerrywong.com/blog/wp-content/uploads/2017/01/eloadcircuit.pngThis circuit relies on the relative low bandwidth of the LT1636 to get loop stability. The LT1636 has a GBW product of 220kHz. The circuit also lacks an RC network across the input.The need for the RC network is discussed in my Dynamic load thread. The network can be seen in Dave's latest video of the Rigol load:7) Cload op-ampsA lot of people think that you need to use an op-amp that has been designed to drive capacitive loads. This is not the case, so long as the op-amp is separated from the capacitive load by a low value resistor. If you look at the gate currents in the model, you will find that they are quite low.The single rail load circuit:Modeling results:I have attached the LTspice model for those playing along at home.Regards,Jay_Diddy_B

author: microbug
author_rank: Frequent Contributor
timestamp: September 18, 2017, 03:09:00 pm
content: 1) Thanks JDB, the current plan is to have a ±10V analog supply (and a +5V digital), driving the –10V with an LMC7660. I'll probably go with lower offset op-amps since this design is more for testing batteries than transient response; accuracy is more important.2) Ok thanks that helps. For my load I'll mostly be testing DC sources so I won't implement the oscillator in hardware.4) That's helpful to know, thanks5,6&7) I'll stick with your theoretical design for the IXYS MOSFET then. I may need to adapt it for a lower offset op amp.I need to watch Dave's latest video as well.I have attached a some details of my current plans, but they are not set in stone. As you can see, the PSoC is quite versatile and should allow me to implement some digital logic for protection purposes and driving the fans. I will get some parts and experiment with values and set-ups soon.Edit: In the design spec it says 17 bits of the ADC are used. This is more likely to be 14 bits (10mV resolution); testing is required.Thanks allmicrobug