Modeling PCB traces at high frequencies - Page 1
Forum section: electronics / beginners

author: Charles Swain
author_rank: Newbie
timestamp: October 01, 2019, 09:51:56 pm
content: I'm in a senior design project group at my university. Our project will involve all of the following:multiple high speed FPGAs and DDR4 memory ICsDC to 20 GHz analog signals traversing some tracesoodles of DC and TTL logic tracesTherefore,we must have some kind of design verification.If we walk into the mid-year presentation to get approval to start working to build the design and we do not have some kind of demonstration that we understand high speed signals enough on PCB traces to effectively use our likely parts, then we will get chewed up. I want the ability to verify the PCB traces are sane before paying money to have a board made. We need to be able to compile a good timing budget for everything and confirm that the traces we are laying out aren't going to be total garbage for purpose. I've been working on how to represent things like jitter, crosstalk, DC noise, etc in a simulation for the purposes of confirming our timing budget and voltage margins. However, I haven't found any software (like a PCB to netlist generator) for students to do this. Therefore, all I've been doing all day is researching representing the bad contributions as pure circuit elements. I have a ton of questions, hence this post.1. am I right so far?If two traces are flat to one another and cross each other from that viewpoint, then that forms a parasitic capacitance right?Parasitic capacitance across a single stretch of parallel traces can be additionally divided up into parallel capacitance, correct?2. which circuit for traces with parasitic elements caused by parallel traces is more accurate if traces 1, 2, and 3 are all parallel?3. what is the circuit for representing both the properties of the trace by itself (lets say its resistance) and those caused by being near other traces (the parasitic capacitance)?4. which model is more correct for representing the parasitic elements of the two traces being near each other? What are the equations for calculating the part values for simulating in this PCB trace use-case scenario? The model on the right is pulled from the book "RF Circuit Design" by Chris Bowick, as a more accurate representation for capacitors.5. is this a more accurate way to represent the trace as a wire or line by itself or am I missing something? What would be the equations for the part values for our PCB use case scenarios? The model on the right is again pulled from the book by Chris Bowick and is supposed to be a more accurate representation of resistors at radio frequencies.6. how do I combine the "better" model for a trace by itself with the "better" model for parasitics caused by being in proximity to other traces? Can I use them as stand ins for what I am working with for question number 3? Do I need to have a separate simulation for everything?I have more questions, especially pertaining to trying to automate all this. If you think I'm missing anything else that I could really use, then let me know.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 01, 2019, 11:42:36 pm
content: Quote from: Charles Swain on October 01, 2019, 09:51:56 pmHeh, yeeeeah... that's kinda how it goes.It may interest you to know, there exists an equivalence, and transformation, between transmission line segments and LC sections. So, this can be done rigorously!However, this is usually more of a narrow-band approximation, allowing the design of various types of bandpass/stop filters, and the transformation into easily constructed transmission line networks.I'm not so sure, though, that this would be beneficial in a wideband (e.g. time domain) context, where the number of elements required goes, I think quadratically, with delay-bandwidth.It's not obvious if you're doing undergrad, graduate or doctorate, but it sounds like the kind of thing I would hope gets assigned to at least graduate-level students. I've met Dr.s that couldn't design a system like this. This project may be... overly ambitious. (Keep your options open, if you can.)I will note that, at least regarding digital interfaces -- many of these are very robust to begin with, for exactly these reasons. You can't ensure good matching, or low HF losses, on cheap FR-4 PCB; so they go to great lengths to deal with slow edges, "drool" (compensated by pre-shooting at the transmitter), bounce (the receiver has a brief (fractional ns) dead time following a transition), delay and skew (resynchronization or adaptive delay of the whole bus, or sections of it, or individual lines of it), all the while pushing data rates incredibly high (DDR, QDR).I forget exactly which of these is integrated with which standards, but IIRC they get more aggressive as the technology advances: DDR maybe nothing, DDR2 with say preshoot and bounce and whole-bus delay, DDR3 with segmented delay, etc.In any case, the effect is to get nominal performance from the same basic crummy medium.Obviously, you'll have a harder time doing that with a pristine 20GHz analog signal path; if you're running that into ADCs or whatever, you'll want to do that as soon as possible, and probably do it on quality laminates (usually Rogers something or other).The other big thing -- besides cramming everything about design and layout -- is testing. Obviously, you need a 20GHz+ spec or scope or VNA to measure these things. This may already be available -- if your labs are well equipped -- but use them very carefully, besides the obvious concerns like expense, but more presently, because probing needs to be done perfectly. At these frequencies, you have to consider the electrical length of the probe tip and pins, and the effect of that stub on the actual in-circuit signals. And even with a JFET probe, you still get significant loading (more through this mechanism than through overall impedance).Consider placing buffers and coax connectors on the PCB, so you can probe the signal with a cable, no need for probes with wobbly pins. Maybe make an assembly variant (optional jumpers/resistors) to divert the signals from between devices, to the test port.Tim

author: JustMeHere
author_rank: Frequent Contributor
timestamp: October 02, 2019, 12:31:27 am
content: If you're doing two layer boards, you can get 100mm x 100mm boards done for $5 USD. I won't put their name on this forum because I believe they caused an issue before. Let's just say there is a "pcb way".See if you can pull off using a ground plane and 0 ohm resistor jumpers and make a 2 layer board.You will want a ground plane. I know nothing about this subject other than I've had great luck with a ground plane getting rid of high frequency noise in buck converters. Like the 12-bit ACD in the project had no noise problem.4 layers from that company are $50.I would be tempted to make some models out of the $5 option.

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: October 02, 2019, 03:09:53 am
content: Please check with the University if you have access to Momentum software. It is best to simulate the traces before building the boards. Even with the simulations, there can be some errors due to dielectric variations. Hand calculations, only go so far when you are considering high speed traces with cross talk.

author: rfeecs
author_rank: Frequent Contributor
timestamp: October 02, 2019, 04:09:39 am
content: At 20GHz, consider everything a transmission line. Welcome to microwave.If you looking for software, Momentum and EMPro is part of Keysight ADS:https://www.keysight.com/upload/cmc_upload/All/2014_ADS_DDR4_Compliance_Test_Bench_HSD_Seminar_rev1.pdfhttps://www.keysight.com/main/editorial.jspx?ckey=2502032&id=2502032&lc=eng&cc=UShttps://www.keysight.com/en/pd-1493996-pn-W2211BP/ads-core-transient-convolution-layout-momentum-g2-bundled?nid=-34335.870787.00&cc=US&lc=engIf your school has that, it is ideal. You can co-simulate the electrical and the layout parasitics, all the way to full EM simulation of the layout.It may take a while to learn how to use it effectively.At a minimum you'll want to calculate the impedance of your traces. Look up "microstrip calculator"s to calculate impedance and electrical length given your substrate and trace geometry.