What is the importance of "Assembly? - Page 1
Forum section: electronics / general

author: Mechatrommer
author_rank: Super Contributor
timestamp: February 08, 2014, 02:25:16 pm
content: i'm confused as to what purpose it is? both Altium and Diptrace have this as in attached picture. what its purpose to a pcb project and is it really necessary? thanks.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 08, 2014, 03:18:38 pm
content: You can generate a testpoint report which shows the locations of all pads/vias tagged as testpoints.Tim

author: Mechatrommer
author_rank: Super Contributor
timestamp: February 09, 2014, 12:12:17 pm
content: thats it? its sole and only purpose?

author: free_electron
author_rank: Super Contributor
timestamp: February 09, 2014, 01:37:10 pm
content: Quote from: Mechatrommer on February 09, 2014, 12:12:17 pmVery important feature !It lets you mark a testpoint for two things: bare board testing: assembled board testing on a bed-of-nails testerHobbyists have no use for this , but any serious board work requires itYou may say bit what about jtag and boundary scan then ? Well how do you tell where the testpoints are for boundary scan ? And what about analog ?

author: Mechatrommer
author_rank: Super Contributor
timestamp: February 09, 2014, 02:03:24 pm
content: ok i get it thanks!

author: tszaboo
author_rank: Super Contributor
timestamp: February 09, 2014, 03:21:39 pm
content: I still think that vias should not be used for testpoints, in fact, via should be covered with soldermask.

author: Mechatrommer
author_rank: Super Contributor
timestamp: February 09, 2014, 06:45:53 pm
content: well maybe i'm myself got drifted, my actual question is the word "Assembly" not has something to do with "test point". even in the diptrace it has this "Assy or Assembly" word (and no test point mentioned). so i wonder where is this assembly will be used. maybe i should post this in diptrace section. but i think i get it as well, assembly probably is another extra layer added for the purpose of "we can do whatever with it" including test point for post pcb fabrication or during assembly or testing process.

author: slowaudio
author_rank: Contributor
timestamp: February 10, 2014, 09:38:42 pm
content: Quote from: NANDBlog on February 09, 2014, 03:21:39 pmqft!

author: luky315
author_rank: Regular Contributor
timestamp: February 11, 2014, 10:21:11 am
content: Don't cover your Vias with soldermask. It can cause troubles and is NOT RECOMMENDED by a lot of PCB Manufacturers.

author: Dago
author_rank: Frequent Contributor
timestamp: February 11, 2014, 12:18:33 pm
content: Quote from: luky315 on February 11, 2014, 10:21:11 amI'd say not covering them up can cause way more trouble (solder bridging etc.). Can you elaborate? I've seen quite a few PCBs and I've practically never seen a PCB with non-masked vias.

author: luky315
author_rank: Regular Contributor
timestamp: February 11, 2014, 02:37:48 pm
content: I recommend reading IPC-4761... Simple via tenting is not a good idea if you need reliable PCBs

author: free_electron
author_rank: Super Contributor
timestamp: February 11, 2014, 03:29:43 pm
content: Double sided tenting with dry film is perfectly acceptable , even according to ipc4761.Provided that-the material in the hole is not bare copper-there is no meltable material (meltable during reflow) in the holeStandard processes use tinflash (chemically grown tin) in the holes so that is not a violation of the above rule.Tenting should not be done on wide vias. 12 to 15 mil drill is perfectly tentable

author: peter.mitchell
author_rank: Super Contributor
timestamp: February 15, 2014, 05:37:56 am
content: Additionally, tenting power vias is a bad idea, not only can't you solder fill them, but they may experience thermal cycling, which may cause intermittent connections, not as much of an issue with untented vias.For signal traces, i have no issues though.

author: tszaboo
author_rank: Super Contributor
timestamp: February 15, 2014, 02:16:27 pm
content: Quote from: free_electron on February 11, 2014, 03:29:43 pmThat is stating the obvious. My standard via size is 0.35mm which is perfectly tentable. Above 0.6mm tenting is not 100% coverage, in that case it should be avoided. Also teniting must be on both sides. If a manufacturer cannot make proper tenting for small holes, that is not a design problem.

author: mrflibble
author_rank: Super Contributor
timestamp: March 12, 2014, 12:59:21 pm
content: Quote from: NANDBlog on February 15, 2014, 02:16:27 pmStupid question: why should it be avoided? Because 0.99 is a smaller number than 1.00, or because of something that impacts the reliability of your pcb. Reason I ask: for some non-crititical PCB's I did I tested a couple of larger vias. And as you say, those are not 100% covered. But inspecting them with a microscope I cannot really see anything where I'd think "gee, that might cause failure XYZ later on". So suppose you are not getting 100% coverage, and are not relying on it to be 100% covered, what is the most likely problem? Moisture? Corrosion?