NPN Not Gate Circuit Question - Page 1
Forum section: electronics / beginners

author: tzcczt
author_rank: Contributor
timestamp: August 12, 2014, 06:53:57 pm
content: I ran across a NOT gate circuit built from NPN transistors on Wikipedia, and in an effort to understand BJTs more, I built and simultated it in LTspice.The part that is confusing to me is the use of the transistors in odd ways from how I normally think of them being used (varying base current to affect current flow from collector to emitter).For example,the signal is connected to the emitter of Q1 with a constant voltage at the base. Then the base of Q2 is used as the collector voltage source on Q1, which seems very odd as well.Are there any rules or concepts to keep in mind that help in understanding circuits like this?

author: dfmischler
author_rank: Frequent Contributor
timestamp: August 12, 2014, 08:27:23 pm
content: AFAICT Q2 is the inverter (low at the base of Q2 leaves the output high). Q1 is just helping out.You might find some enlightenment here.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 12, 2014, 08:54:24 pm
content: TTL is implemented exclusively in NPN transistors, to the extent that 1. it's impossible (or at least impractical) to even try to make anything else, and 2. even if you want a diode, it's going to look more like 1/2 an NPN anyway!I don't know if they ever attempted to use PNPs in 7400 (or LS) series logic. The most likely places, I think, would be timers (like the '123) or PLLs, but I don't see a PLL in that family (whereas CD4000 series has the '4046, and the 74HC variants thereof). Likely, they could only possibly be very poor quality (lateral PNP), and very limited in how they can be connected (e.g., collector grounded by being the substrate itself). So yeah, NPN or bust, pretty much.BTW, note that, at DC, the circuit shown works just as well with a dual diode in place of Q1 -- however, Q2 will turn off extremely slowly (20us?) when that is done. The enhancement provided by Q1 is that Q2's stored base charge gets sucked out by Q1 saturating. Q2's base hovers up around ~0.6V until discharged, so when Q1's emitter is pulled below ~0.5V, it acts as a saturated switch, helping out. This, along with the output stage (which involves a few more transistors in a totem pole configuration -- the pull-up uses a resistor, hence the weak 'high' level of the family), are what defined the outside behavior of TTL.Actual TTL internals, I think, were quite a bit more diverse than you would expect, compared to the circuit you'd get from stacking discrete gates to form more complex functions. Like the D flip-flop, IIRC, was usually implemented with diff pair style schmitt trigger looking circuits, toggled by 'tugging on the tail' or something to that effect. You see a lot more of that "NPN as transmission gate" sort of use, too. 'Course, all that matters is the function is correct, meets timing requirements, and is able to interface with standard TTL pin input / output circuits.Tim

author: DJohn
author_rank: Regular Contributor
timestamp: August 13, 2014, 01:50:44 pm
content: My understanding, which could well be wrong:When the input is low, Q1's collector gets pulled low, and its base (which likes to be a diode drop above the collector) goes with it. That makes a current flow through R1, turning Q1 on. That forces Q2's base low, switching it off. R2 pulls the output high.When the input is high, Q1's collector and base are high. If Q2's base was low, then current would flow through Q1's base and emitter (which is effectively a diode), switching on Q2. That forces the output low.Without Q1, the base current to switch on Q2 would have to come through the pullup resistor of the previous stage. That's going to cause problems with power consumption: the preceeding R2 needs to be a low enough resistance to provide enough current to turn Q2 on properly, but you want a high resistance to avoid wasting power when the transistor is on. It will also reduce fan-out: if the output is driving many other gates, the current through R2 gets divided among all of them. With Q1, the current to switch on Q2 comes from R1, not whatever is driving the input.It would be worth putting monitors on the currents flowing at various parts of the circuit in your simulation, and seeing what they do as the input changes. Also try stringing two of these inverters together, and have one drive the inputs of two others. See what currents flow where, and how they change (or don't) with different configurations.

author: David Hess
author_rank: Super Contributor
timestamp: August 15, 2014, 04:49:40 pm
content: Quote from: T3sl4co1l on August 12, 2014, 08:54:24 pmLater processes included fast PNP transistors so ALS and maybe AS used them as emitter followers on the inputs which both lowered the logic low input current and compensated for one of the NPN Vbe drops. Some other functions which relied on accurate input threshold voltages used PNPs for temperature compensation.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 15, 2014, 09:42:58 pm
content: Yeah, the later series, and also the BiCMOS families e.g. 74ABT. I don't think they ever tried to get super creative in the stock 7400 or LS families though. Actually, even in the complementary or BiCMOS families, I don't think they did either; ABT is predominantly just bus drivers.Tim