Guard Ring for High Impedance Circuit - Page 1
Forum section: electronics / projects

author: ignilux
author_rank: Unknown
timestamp: September 22, 2020, 08:18:08 pm
content: Hi, all-I'm working on a design that compares the leakage current through a capacitor to a reference current in the range of 10 pA to 10 nA. At the low end of the range I'm concerned with PCB leakage currents interfering with the measurement, so I have implemented two guard rings around the two sensitive nodes. In both cases the high impedance trace runs to the inverting input of an opamp, and I've tied the guard ring to the non-inverting input at exactly one point. The guard rings themselves are 10 mil wide, and there is a 10 mil spacing between the ring and adjacent ground plane. Solder mask has been removed from the rings and enclosed areas as well. Through-hole components have a ring on the bottom side as well, and no attachment to the inner layers (it's a 4-layer board).I've attached some images of the board, schematic, and layout, and I'd like some feedback on my implementation. My primary questions are:Given that the rings are at ground and, thus, a low impedance potential, can I get away without a buffer amp driving them?Have I connected the corresponding top and bottom rings properly? I.e., multiple vias without connection to internal planes?Is 10 mil thick enough for the ring itself, given their length?If you're wondering why I'm not just air wiring everything, it's primarily due to ease of reproduction. It's not anything thatI'mplanning to reproduce, but I want it to "just work" if someone else tries to build it. That, and air wiring really starts to take up space once more than a few connections are necessary.Anyway, I'd appreciate any and all feedback you have. Thanks!

author: KT88
author_rank: Frequent Contributor
timestamp: September 22, 2020, 09:08:14 pm
content: With an inverting configuration at GND potential there is no need for a buffer.I would choose an amplifier with lower Vos though. Even a few hundred microvolts can already cause some leakage.The LT6078 would be a pin compatiblle replacement. Vos is 25uV instead of 300uV. In addition the current noise is two orders of magnitude lower - that really mattes... Ibias is 1pA instead of 45pA.The guard rings should be interupted to avoid inductive coupling of high frequency noise. The open ends should be in parallel for a few millimeters to keep leakage out.It looks like you have the layer below coupled to the guard - that helps against leakage through the bulk of the PCB material. I would reduce the width of the trace to minimize parasitic capacitance though.CheersAndreas

author: ignilux
author_rank: Unknown
timestamp: September 23, 2020, 01:26:48 am
content: Andreas-Thanks for your response, it was quite informative. Unfortunately the LT6078 takes a maximum 5.5V single supply, while I have +/-6V supplies. I agree that lower offset voltage would be desirable, and while I prefer to design based on worst-case values (as you have done with the 300 uV figure), the distribution on page 6 of the AD8667 datasheet paints a nicer picture. Current noise isn't something I'd put much thought towards, but it makes sense that it would be important. As for bias current, this is a battery powered device generating a maximum of 250 mW, 90% of which is in some front panel LEDs. Temperature inside should never get above say, 30 or 35 °C. Once again, I'd prefer to design based on worst-case values, but I'm certain I won't be getting anywhere near the 85 °C mark where 45 pA max Ibias was measured. With respect to high frequency noise, there is no such source inside the enclosure, and the chassis will be die cast aluminum. That said, I hadn't thought of opening the ring in that manner, and I may do so anyway.Thanks again for your input!

author: ignilux
author_rank: Unknown
timestamp: September 23, 2020, 01:29:54 am
content: Oh, and the money trees in my backyard are fresh out, so please nobody mention the ADA4530-1 unless you want to donate to the cause

author: LoveLaika
author_rank: Frequent Contributor
timestamp: September 23, 2020, 05:40:05 pm
content: I'm also working on a guard ring for my circuit. I'm creating a transimpedance amplifier, and I'm trying to add a guard ring to prevent leakage current. I'm assuming you're using KiCAD? It looks like you included a no-fill zone around your ring, but how did you remove the soldermask around those areas?

author: LoveLaika
author_rank: Frequent Contributor
timestamp: September 23, 2020, 05:51:27 pm
content: I'm also trying to put a guard ring for my op-amp circuit myself. However, I'm a bit confused as to how to do it. The way OP did it was that for U2, he guarded his inverting node and had the ring be tied to the non-inverting node at ground potential. Then, he used a via to connect it to his ground plane. For me, I used traces to do the same thing (in this case, Io is the lowest potential seen my my amplifier), but is this the correct way? I'm worried that I may have implemented this incorrectly. The goal of mine is to prevent leakage currents, because I am converting pico-amps to voltages with the AD795, and they highly recommend a guard ring.

author: ignilux
author_rank: Unknown
timestamp: September 23, 2020, 07:23:24 pm
content: You might get better advice by starting your own thread...That said, the way that I removed soldermask from an area in KiCad is by placing a polygon in the F.Mask / B.Mask layer. It works inversely, such that by default you get soldermask everywhere, but placing stuff on the Mask layers tells the PCB manufacturer where youdon'twant soldermask.As far as your circuit, I would really need to see your schematic to be able to comment on your implementation.

author: LoveLaika
author_rank: Frequent Contributor
timestamp: September 23, 2020, 07:46:27 pm
content: Thanks for replying so quickly. I was thinking about making a new thread, but I kind of asked this on another forum page, but I feel like if I kept on asking the same on different forums, it would make people angry. I was searching around for some ideas on the forum when I saw your post and noticed that it was pretty recent, so I thought I would try and ask here. If it helps, I was replying to @KT88's post, and I included my board layout and reference schematic there.That's an interesting little trick with the soldermask layer. I never knew that you could do that. Others mentioned that the way to do it is to use single-net component pads and so that's what I did, but I like your way better. So, your polygon removes the soldermask in your area including the traces you use for a guard ring?

author: KT88
author_rank: Frequent Contributor
timestamp: September 23, 2020, 08:09:43 pm
content: @LoveLaika: There is a KICAD section in this forum. You'll get every answer you need over there. If you like to discuss your design I would suggest you start your own thread as ignilux suggested. You find a lot of awewsome folks who have a lot of experience with low-level measurements and can support you with your design.CheersAndreas