Who screwed up the TTL Pinout - Page 1
Forum section: electronics / general

author: chris_11
author_rank: Contributor
timestamp: January 01, 2023, 11:47:46 am
content: Hello,Does anyone knows a bit of history why the VCC and GND pinout of the TTL series and with it the 4000 CMOS series ended up with the physical worst possible solution. The most critical VCC-GND decoupling loop did wind up in the longest possible pinout of 7 for GND and 14 for VCC in a typical 14 pin package. Not only the IC internal bond wires were the longest but on the PCB too it was the longest distance. That is a nightmare to decouple.Sylvania came up with its first high level logic series SM2927 in 1966 with a better approach. Pin 4 VCC and Pin 10 GND, but somehow the SN7400 series made it to 14 and 7https://archive.org/details/bitsavers_sylvaniadaiaUniversalHighLevelLogicMay66_3459527I know that on early wire wrapped boards it was somewhat easier to route 5V VCC and GND on opposite sides, but decoupling was always a challenge.Latter on fast high fan out bus drivers TI had to change to VCC and GND side by side and in the midlle of the package where the bond wires where shorter.So does anyone know why the industry came up with the physical worst solution? It took about 30 years to improve.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 01, 2023, 07:56:58 pm
content: Because it's not critical at the edge rates and frequencies typically encountered when these ICs were developed in the 1960s and '70s. By the time you need faster logic you move on to ECL or smaller packages anyway.It really doesn't matter, as you can see by the billions of electronics gizmos and computers made with TTL parts that worked quite well.And when it did matter, they changed the power pins around.https://www.ti.com/lit/ds/symlink/cd74hc93.pdf

author: PCB.Wiz
author_rank: Super Contributor
timestamp: January 01, 2023, 08:24:29 pm
content: Quote from: chris_11 on January 01, 2023, 11:47:46 amThe earliest TTL parts were power hungry, and not fast.Often physical bus bars were used for power, and PCB's were simplest, so it then made sense to have opposite corner pinsI'm not sure they ever actually improved this.History shows that the TTL corner pinout survives, simply because that is what PCBs already use, whilst the variants Philips/TI introduced with centre pinouts like 74AC11245 faded.You can still buy 74AC11245 (now from only TI), but at much higher prices than the parts it hoped to displace.New parts that are not TTL replacements, can choose any pinout the designers want, and you would never see a new part with corner pins in 2023, but you'd also never see a new part in DIP-only packaging either.Addit: Physical bus bars are still around, here is a 2020 article, where higher currents are not so much from the logic parts anymore...https://www.edn.com/3d-bus-bar-an-optimum-solution-for-managing-dc-power-rails-on-pcbs/

author: MarkS
author_rank: Unknown
timestamp: January 01, 2023, 08:32:44 pm
content: Correct me if I'm wrong, but wouldn't you just connect the decoupling cap to the VCC pin and the ground plane, while placing the cap as close to the chip as possible, like any other IC? Why decouple directly between the chip's VCC and GND pins?Forgive my ignorance. I must be missing something. 🤷‍♂️

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 01, 2023, 08:36:02 pm
content: Quote from: Alex Eisenhut on January 01, 2023, 07:56:58 pmHmm. In which way does this part exemplify the subject? Minimum max output transition time 13ns (and I suppose typical, and actual-min, are proportional fractions, typical of 74HC, so, 5ns or so). Indeed it seems to exemplify the arbitrariness of things, where they sometimes did dumbass pinouts because...who knows. (Presumably, because why pay for slightly more die area, or more than one metal layer, to solve PCB issues before they start. CD4000 I think were more notorious for weird pinouts?, but 74xx did a few too.)Tim

author: TomS_
author_rank: Frequent Contributor
timestamp: January 01, 2023, 08:40:34 pm
content: Quote from: MarkS on January 01, 2023, 08:32:44 pmMany early boards didn't have internal planes. They were two layers only.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 01, 2023, 08:42:50 pm
content: Quote from: MarkS on January 01, 2023, 08:32:44 pmYeah. It's not a big deal unless you don't use a ground plane. I don't know how common ground planes were in PCB design in the 70's. I suspect not very, due to being limited to two layers in most cases and due to layout tools which would make designing full ground planes (and not just small ground zones) unpractical. But someone having worked at the time could chime in and give us more details about all this.I don't know what the rationale was for choosing diagonally opposite corners on TTL chips and many digital chips in general. If someone does?

author: TomS_
author_rank: Frequent Contributor
timestamp: January 01, 2023, 09:23:46 pm
content: Quote from: SiliconWizard on January 01, 2023, 08:42:50 pmI think a good candidate is as mentioned above, it makes routing power supply buses easy whether you run the buses in parallel under the chips from top to bottom, or perpendicular along the top and bottom.

author: artag
author_rank: Super Contributor
timestamp: January 01, 2023, 11:18:51 pm
content: The 7475 is one that survived with centre pins for Gnd and Vcc.It has a disadvantage though : you can't put a decoupling cap close to Gnd and Vcc without using the back of the board. So corner pins with a ground plane and the capacitor placed near the Vcc pin is probably better.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: January 01, 2023, 11:25:41 pm
content: TTL was invented in 1961 by James L. Buie of TRW,https://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logichttps://en.wikipedia.org/wiki/James_L._BuieYou could try to organize a party to go stamp on his grave, but that would not be fair. As Alex Eisenhut already mentioned earlier, the pinout was perfectly adequate for the slow transistors they had back then, and Gordon Moore's prediction of exponential growth of transistor count was made in 1965, which is 4 years later.https://en.wikipedia.org/wiki/Gordon_MooreI am wondering when 4-layer PCB's were introduced, and when they became common, but it's probably years later. Although "High end" electronics (for that time) was more common compared to the mass produced cheap stuff we have today. The Cray-1from 1975 was apparently built with 5 layer PCB's. Which indicates that the even layer count process of these days was not common back then, and that is 15 years later.https://en.wikipedia.org/wiki/Cray-1

author: srb1954
author_rank: Super Contributor
timestamp: January 01, 2023, 11:31:41 pm
content: Quote from: TomS_ on January 01, 2023, 08:40:34 pmTwo layer boards were used for lower production cost in most products through until the late 80s. In the 70s we even used single sided boards wherever possible to save production cost! Assembly labour was cheap back then but PCBs were not.Multi-layer boards didn't really become widespread until EMC regulations came into force and, with the ever increasing digital circuitry clock rates, designers had trouble meeting EMC requirements using only 2-layer boards. The increased complexity and density of circuitry was also a factor forcing the move to multi-layer boards.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 01, 2023, 11:37:32 pm
content: Quote from: TomS_ on January 01, 2023, 09:23:46 pmOr both, to form a grid

author: gnuarm
author_rank: Super Contributor
timestamp: January 02, 2023, 12:15:00 am
content: Quote from: MarkS on January 01, 2023, 08:32:44 pmWire wrap boards didn't have power and ground planes as such. They were often thick boards and the power was on wide tracks, rather than being the entire plane.http://www.metricmind.com/audi/images/_0398_evision_front.jpgSo not as much capacitance as you might like.Also, many people did not really understand decoupling. If you do have ground and power planes, you don't really need to worry about the distance from power and ground pins to the capacitors. The power and ground planes act as a transmission line, providing current to the chip, while the wavefront propagates to the capacitor.I took a class with Lee Ritchey, where he showed a demo board that proved this. The cap had to be up to 6 inches away, before you could see any appreciable reduction in the decoupling. That guy was impressive. On everything he taught, he would first give the theory. Then he would show the simulation.Thenhe would show measurements made on a (usually) custom board. All three agreed, of course. No need to fudge or hand wave. Everything taught in that class was solid as a rock.I did manage to ask him a question that nearly stumped him. He was talking about ground and power bounce and had mentioned having capacitors built into the chip carriers. I asked if that wouldn't help with ground bounce and he had to really think about it before saying that it would not make an appreciable difference. It took me a bit of thinking before I realized he was mostly right. Ground/power bounce is from sinking/sourcing current through the I/O pin, with a return path through the power/ground paths. The best on chip decoupling caps will do, is to couple that current to the both the ground and power paths in parallel, so cutting bounce in half.

author: gnuarm
author_rank: Super Contributor
timestamp: January 02, 2023, 12:19:41 am
content: Quote from: SiliconWizard on January 01, 2023, 08:42:50 pmI don't recall dates of technology, but I can tell you I never saw a wirewrap board with power/ground planes, other than the traces run under the body of the chips. The columns were spaced 0.1 inches apart, so no room there. They often had a ww pin by the power and ground pins, hard wired to the appropriate trace, which means a thinning of the trace width from about 0.2 inches to 0.1 inches.http://www.metricmind.com/audi/images/_0398_evision_front.jpg

author: gnuarm
author_rank: Super Contributor
timestamp: January 02, 2023, 12:31:24 am
content: Quote from: srb1954 on January 01, 2023, 11:31:41 pmI don't know about EMC, but I recall the late 90's when DDR memory became common, and mother boards got flaky. This led to many users claiming this magic memory module was the "good" one that works, and someone else would claim it was a different brand.As it turned out, it was none of them. The problem was the motherboard makers were not using good SI design skills. So it was a crap shoot as to who's memory would work with which motherboard. Of course, some brands were designed properly, so didn't have this problem. But SI was somewhat new, or at least the knowledge of it was not widespread. So lots of crap motherboards were very marginal.This doesn't require multiple layers so much, but it requires attention to impedance and trace length. Multiple layers makes life a bit easier, but I believe Lee Ritchey was paid to lay out a two layer motherboard in that time frame, and it worked just fine. They paid Lee a boatload to design a 2 layer board, and recouped that many times over in the manufacturing costs.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 02, 2023, 05:02:22 am
content: Quote from: T3sl4co1l on January 01, 2023, 08:36:02 pmI don't know but many TTL chips were available with center power pins:https://nvhrbiblio.nl/biblio/boek/Texas%20Instruments%20-%20TTL%20DataBook%20vol2.pdfIf you scroll to page 54 of the PDF, page 3-3 of the document, you can see that apparently most standard logic TTL chips, least from TI, had this option available.I was told, a looooooooong time ago, that this reduced the inductance of the connections to the die.I suppose the only reason you'd want that, if as you point out the chips aren't any faster, is to reduce noise in systems with 100s or 1000s of LSI chips?I've seen 5V power supplies with 100s of amps for nutty systems like that.I guess that once MSI and LSI started appearing you didn't have systems with so many SSI chips, therefore they dropped the center power pin variant?Beats me, lots of guessing on my part.

author: srb1954
author_rank: Super Contributor
timestamp: January 02, 2023, 07:47:32 am
content: Quote from: Alex Eisenhut on January 02, 2023, 05:02:22 amThat option seems to only be for the W package, which is a ceramic flat pack type package, a precursor to the SOIC SMD packages of today. These were only available in the military temperature range SN54xx series and were rarely seen outside of military equipment and space applications due to their ridiculously expensive prices.

author: HwAoRrDk
author_rank: Super Contributor
timestamp: January 02, 2023, 09:31:16 am
content: Quote from: gnuarm on January 02, 2023, 12:31:24 amYeah, I remember these problems. The nVidia nForce chipset boards were notoriously flaky at 200 MHz FSB speeds. I recall going through 3 different brands/models of board before giving up and just underclocking my Athlon XP 3200+.And only a fool would ignore the three magic letters when buying DDR RAM: "QVL".

author: Siwastaja
author_rank: Super Contributor
timestamp: January 02, 2023, 11:08:55 am
content: This pinout is indeed excellent when you run power & ground tracks under the chip (in 2- or even just 1-layer design!).ASCII art:Code:(power in here)| |o| |oo| |oo| |oo| |oo| |oo| |oo| |o| ||C|| |o| |oo| |oo| |oo| |oo| |oo| |oo| |o| |This example shows two 14-pin logic ICs bypassed well enough by one bypass cap in the middle. You can route the whole thing in 1 layer. When you have to connect signals of the opposite sides, you make a longer loop, or just add jumper wires to jump over the Vcc/GND tracks. Jumpers of different lengths were really inexpensive and common back in the days.There is nothing wrong with the pinout; given the edge rates, it's good enough.

author: chris_11
author_rank: Contributor
timestamp: January 02, 2023, 12:51:42 pm
content: As soon as you have any logic with more than one I/O port the optimum decoupling loop inductance becomes zero. Any inductance to the decoupling creates ground bounce and bounce to Vcc which is added to you I/O voltage. So you add noise and decrease the margin. With the first logic generations edge rates you could live with the round trip decoupling inductance, but as faster the logic became to AS, FACT etc. as more problematic the long loop distances and with it the inductance became. Every logic output drives a TL with a certain characteristic impedance. So as soon as you have more than one output, any inductance in the decoupling does create crosstalk=noise to the other channels.TTL are usually tiny chips in the middle of the package. So you can figure that the longer bond wires have inductance of several nH.

author: David Hess
author_rank: Super Contributor
timestamp: January 02, 2023, 02:44:33 pm
content: As far as I know, corner pin power and ground made 2 layer board layout easier and the extra inductance was not a problem until advanced schottky, fast advanced schottky TTL, and AC became available at which point the corner connections limited performance.

author: Blinkenlights
author_rank: Contributor
timestamp: January 06, 2023, 12:13:56 am
content: I have designed (circuit and layout) a few hundred PCBs, including many TTL based PCBs with 20-100 chips, so I have suitable experience to answer this.I suggest that the rationale was approximately the following...<tldr> The chips will be arranged in a grid pattern, VCC and VSS are required at every chip, and what matters in EMC is loop area.</tldr>The best solution always was a power and ground plane, (which cuts loop area to just about nil) but not all of the jobs we did could afford the extra layers. Mostly power and ground were grid routed horizontally and vertically. That means multiple routes for power - a chip near the centre of a grid has power and ground routed to both chips at either side, and above and below.This was assisted greatly by most of the chips being about 14,16 or 20 pins, similar physical sizes. Once you have that grid routing in place, decouple capacitors could be placed straddling each of power and ground. Yes, it is required that the supply feed be low impedance, and that low impedance was facilitated by decoupling capacitors. But really, in the bigger scheme of things, minimizing that loop area was more important. And that loop area could not really be made a lot smaller than each of the chips - and when that becomes apparent, it really means that the position of the power supply pins is really less important - it is better to get them as far out of the way as possible, so there is more opportunity to connect signal pins directly to each other, and often those signal connections might be from one pin on a chip to another pin on the same chip - having the power connections out of the way gave more opportunity for those signal connections to be better optimised.<philosophy> I hope with this different way of analysing the problem, you can see why the choice was (and still is) the best, logical, solution.If designs were such that connections between pins on the same chip were much less likely than connections between different chips, then argument for shifting power pins out of the way holds less weight. However, the nature of logic chips is such that gate-to-gate connections are more common. Now when to reconsider this in terms of say, Microprocessors or FPGAs, then would connections would rarely be made between pins on the same chip, unless we were grounding a mode pin or something. With those devices, the loop area rationale is just as important, but there is no solid reason to "get the power pins out of the way of the signals", as the tracks are as likely to run away from the device as across the device. There is also less opportunity to grid route power to dis-similarly sized devices. There is also more opportunity for devices to be used in PCBs with just a few chips, perhaps even just one or two. With those factors in mind, it becomes more prudent to design a pinout that places power and ground close enough together so that a decoupling capacitor can easily be placed between them, which was the point-of-view of the original post. But logic chips, TTL? Yep, corner power pins were the best tradeoff, chosen by engineers with far more practical knowledge than we could ever hope for </philosophy>

author: rstofer
author_rank: Super Contributor
timestamp: January 06, 2023, 05:36:10 pm
content: Then there were sockets with a built-in decoupling capacitor. I don't know how the relatively long lead worked out.https://www.e-tec.com/v5/products/precision-ic-socket/precision-dip-ic-sockets-tht-through-hole/precision-dip-ic-sockets-wired-capacitors/index.php

author: rstofer
author_rank: Super Contributor
timestamp: January 06, 2023, 06:09:00 pm
content: Oddly enough, RTL, which came around before DTL, which came around before TTL, did have the power and ground at the midpoint of each side.https://worldradiohistory.com/Archive-Don-Lancaster/rtlcb.pdfApparently, by the time TTL came around, somebody decided that midpoint Vcc/Gnd was a mistake.Motorola used to have a nice line of RTL back in the early '70s and that's what got me started with logic design. I moved rather quickly to TTL and skipped the DTL experience but there were a lot of systems designed with DTL.

author: gnuarm
author_rank: Super Contributor
timestamp: January 06, 2023, 07:08:21 pm
content: Quote from: David Hess on January 02, 2023, 02:44:33 pmActually, it's not really important that the pins be on opposite corners. It's only needed that the pins be on opposite sides of the chip. Then power can be routed between the pin rows without interference.

author: gnuarm
author_rank: Super Contributor
timestamp: January 06, 2023, 07:11:03 pm
content: Quote from: Blinkenlights on January 06, 2023, 12:13:56 amThe idea of loop area being the significant factor only applies if you are connecting the capacitor to the pins with traces. If you have power and ground planes, with significant capacitive coupling, they form a transmission line, which supplies power to the chip as the wavefronts propagate to the capacitors.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: January 07, 2023, 10:01:58 pm
content: But still, when I first learned these IC's need decoupling capacitors over their power pins I first thought that putting those pins on opposite corners was quite strange. It would have been just as easy to define pins 1 and 14 (or 1 and 16 for the 16 pin variants) as power pins. This way the same grid layout could have been made, and by putting half the IC's upside down, power delivery would only have been needed for half the rows.I'm guessing that when the pinout was devised, the use and importance of decoupling capacitors was not very well understood.But it's far to late now to redo all those PCB's made in the '70-ies and '80-ies.

author: Siwastaja
author_rank: Super Contributor
timestamp: January 08, 2023, 10:28:32 am
content: Quote from: gnuarm on January 06, 2023, 07:11:03 pmNot true. For example, a 100 x 100 mm power/ground arrangement with typical 0.16mm prepreg separation and K=4 only has 2nF of capacitance. Same thing in other words, transmission line impedance is many ohms. This is approximately an order of magnitude too little/much for proper bypassing, which is why power plane based design needs to use (roughly) similar number of capacitors, in similar positions, as a design using wide traces. Properly done power plane does not hurt, but there is no free lunch from power planes, and people who think so usually colossally fail the PDN.Having spoken to some EM design / simulation experts, the world is pretty much moving from 0.1uF bypass caps to 1uF bypassing (because you get 'em in the same tiny packages, so high frequency performance is the same), and from power planes to tree-like wide power tracks. Which also has the benefit that you can route many supplies on a single layer pair.

author: gnuarm
author_rank: Super Contributor
timestamp: January 08, 2023, 11:16:29 am
content: Quote from: Siwastaja on January 08, 2023, 10:28:32 amI'm not sure why you think 2 nF of capacitance is not of value. Or maybe you don't understand. You have definitely miscalculated the transmission line impedance. The impedance of two planes, is very low. What is important, is that the current flows instantaneously from the power planes, as the wave propagates. On reaching the capacitor, the current is then supplied by the capacitor. The impedance you are used to calculating is of a strip line or microstrip with a limited width.Lee Ritchey taught this in a class, where he explained the equations, showed the simulation, and produced the results of the measurement on a board constructed for this purpose. I believe the voltage dip caused by a current spike was pretty much invisible until the cap was six inches from the point of injecting the current (the power pin simulation).

author: David Hess
author_rank: Super Contributor
timestamp: January 08, 2023, 04:01:03 pm
content: Quote from: Doctorandus_P on January 07, 2023, 10:01:58 pmIt would have been understood, if it was required. Saturated logic then was not fast enough to require better decoupling, and fast unsaturated logic like ECL is much more tolerant.The power and ground pin placement was changed later when faster TTL started having problems with ground bounce.

author: chris_11
author_rank: Contributor
timestamp: January 08, 2023, 04:26:37 pm
content: Sure, you get away with it until you don't. In later faster designs i.e. with GAL like 22V10 and fast logic families you have a much lower S/N than possible with a good pinout designed for decoupling. So the question remains. I assume they did not know in the 1960s what those compromise did mean. At that time they did build TV sets on single layer...Even if you make a perfect GND-Power plane design the lead inductance with the bond wires high above the closest possible plane means significant loop inductance.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 08, 2023, 05:58:34 pm
content: Quote from: Siwastaja on January 08, 2023, 10:28:32 amHm, not sure which aspect is "not true".Taking the 100 x 100mm area as a 100mm width, 100mm long parallel plate transmission line, that's Zo = 0.3 ohms and L = 0.2nH.Now, you can't connect to it with a plane wave. A via in the middle of the plane, makes effectively a coaxial stub of length h, inner radius r (half the via diameter), and outer radius R. For a step wavefront, R increases with time, so the inductance goes as mu_0 ln(R/r), where R depends on frequency. (For frequencies where the wavefront stays within the board outline, reflections from the edge will matter, and peaks and valleys will be found. For frequencies below, plane capacitance will dominate.)Note that a logarithmic impedance isn't meaningful when losses haven't been specified. Again, the case is purely for the leading edge of a transient wave. But we prefer impedance for steady-state sine. This will do for a very lossy plane where waves are absorbed over a short length (and then the impedance won't be inductive but mostly resistive), but even at 10GHz, FR-4 isn't quitethatbad, so we should expect some 2D-TL effects at the highest of frequencies.Down at frequencies like 100MHz, the plane is essentially a solid connection, with some modest capacitance, and inductance mainly centered around each via (hence the value of multiple vias in parallel, especially staggered +/- vias to cancel out nearby fields). The capacitance is handy but not really the point; the point is the nearly ideal connection to every bypass cap on the board. Indeed the plane capacitance can resonate with your bypass caps, because the ESL is low (a few nH), the capacitance is small (low nF), and ESR is very low (say <100mΩ) so compared to the Zo of ~1Ω the Q can be higher than we'd like (~10).Still, a few ohms isn't terrible for most logic devices. A step of 100mA is only a peak change of 100mV (and for periodic currents, this remains true if we keep Q <= 1), which is fairly high, certainly noticeable out of a 3.3V supply, but, still, that's only 3% ripple; most digital circuits won't notice a thing. (Precision timing applications will certainly suffer jitter, and could use better filtering -- say ferrite bead (or better) to a local plane, plus whatever considerations need to be made to reduce GND loop interference from nearby circuitry.)So:- Is it a capacitor?--> Yes, but a small one, and not very significant at most frequencies. It does have an effect on the finest edges that PCB supplies can meaningfully handle (i.e. ~100MHz, above which package strays dominate -- compare the multiple power pins of typical QFP MCUs, to the onboard bypass caps, and even on-die planes and other capacitive strategies, on big BGAs and SoCs and such)- Is it a transmission line?--> No, it is not a 1D TL, it's 2D(!).--> Yes, but not really at frequencies we're concerned with for PDN purposes.--> Yes, but the region near each via is more important, and can be approximated as LF equivalent inductance.- Does loop area matter?--> Sure, but what loop are you drawing?Note that VCC-GND loop only matters to the local device in question. Prioritizing it over everything else, likely leaves you giving up signal quality -- because of poorer signal-GND or signal-VCC loops. To wit: compare the case where an adjacent pair of power pins are tied to plane with one or two adjacent vias each, versus routed to an adjacent capacitorand only thento vias to plane. The trace length plus half pad length (and the missing parallel vias opportunity) adds between VCC and GND together (common mode) and all signals into/out of the chip.And, does this actually matter at all? Probably not very. The thing with religious arguments about how pads, traces, bypass caps and vias should be arranged are largely interminable because either no one cares to actually do the simulations let alone practical studies, or the results are ambiguous (is the right question even being asked of the setup?), or the differences are so negligible, no one could care.But you could have for example, signals coming straight off an MCU into connectors -- say if you wanted to run SPI to a display pendant that's got say a couple LEDs and pushbuttons. So you just wire them all straight up, and they're just on/off signals so why bother with a shielded cable, right? But you go to test it and find the cable's blowing out by a few dB at the CPU clock and harmonics, as if your SDRAM and stuff was leaking out, but, you used GPIOs from the complete opposite side of the chip just for this reason! Well, all those other signals (i.e. FSMC, and, I mean, anything else it's doing, Ethernet MAC, LCD, SPI, timers..) are kicking around some noise between chip (onboard GND) and PCB GND, and by extension all signals that come out of the chip, whether they're moving or not (so, including outputs set high or low almost all the time).In such a case, the noise emission will be proportional to ground/supply inductance. So improving it gives proportional reduction in emissions. I would suggest prioritizing impedance between supply pins and PCB -- reducing CM error -- for a situation like this, and then arrange bypasses how ever is suitable.Even such a case is still fairly contrived, because EMC has an absolute threshold: you don't need to be any better than the limiting level, well, a few dB to spare of course, but more doesn't do anything for you, strictly speaking. So we still don't know if we can just wing it and wire it up and go, or if we need some filtering, or a truly heroic amount of filtering plus shielding and etc. We need numbers and at least back-of-envelope calculations, or simulations or demos preferably, to get some idea where we're at, and how much of those things we'll need.The same problem shows for old school TTL boards, where the common mode (signal quality between chips in different rows) is bouncing around all over because the PDN is designed in a comb or ladder shape and the signals are pushing displacement or load currents between the tines / rungs. A grid architecture was also mentioned here, which helps -- that shorts between the rungs, reducing the loop area. Signals still end up with a high average impedance (~150Ω?), and there's still a lot of radiation to the surroundings, but still a significant improvement. You can further draw a continuum between conditions of solid plane, perforated plane (fine mesh of some density), and coarse mesh or grid (whether the grid size is one or two chip body lengths, or the whole board width as in the ladder topology).Tim

author: KE5FX
author_rank: Super Contributor
timestamp: January 08, 2023, 07:48:41 pm
content: Power planes are overrated. You might have 1 Farad of plane capacitance, with literally acres of copper separated only by prepreg, but the loop area where the fast current is flowing is still confined to the area between the chip's power pins. The chip can't draw power very quickly from portions of the planes several inches away.So you might as well use traces to distribute power, with bulk capacitors located near the parts. The values of those capacitors aren't as important as their physical size. In critical applications I like to use at least one 10 nF or 100 nF 0402 cap right at the power pin, fed through ferrite beads or low-value resistors, connected to larger bulk capacitors elsewhere.In other words, and contrary to conventional wisdom, I don'twantlow PDN impedance in areas that aren't actively involved with providing power to the ICs. It accomplishes nothing. Meanwhile, you almost certainly have better uses for an extra copper layer than devoting it to a power plane.As for vias, those are something to worry about if the books on your shelf are written by people with names like Pozar and Lee, rather than Horowitz and Hill. Otherwise, just do what it takes to minimize the loop area adjacent to the IC, and call it good.

author: gnuarm
author_rank: Super Contributor
timestamp: January 08, 2023, 10:24:08 pm
content: Quote from: KE5FX on January 08, 2023, 07:48:41 pmNot sure who you are replying to, but the power pins draw power from the plane capacitance as the wavefront propagates along the power plane. On reaching the capacitor, the current is supplied by the capacitor. If you think this is really about the total capacitance of the power plane, you don't understand transmission lines.The effects of the transmission line are like distributed capacitors along the way. Given the propagation speed of the waveform, any small section of the path only needs to draw current from that capacitance for a very short interval. If you understood transmission lines, you would know that current starts flowing into the source immediately and continues to flow as the current wave propagates along the transmission line.QuoteAnyone designing boards with high dI/dt spikes, knows this is not correct. It is very hard to accomplish PDN requirements in systems with large chips drawing large, fast spikes of current. If power planes were not useful for this, why would the extra money be spent? Once one engineer showed it would work without power planes, everyone would get the message.QuoteYou still haven't explained how youdoget low impedance PDN.QuoteThat doesn't work so well when you are routing a large BGA. It's hard to find room for the caps by the power pins, between all the vias. Putting the caps around the outside of the BGA works just fine.

author: KE5FX
author_rank: Super Contributor
timestamp: January 08, 2023, 11:45:18 pm
content: QuoteIt's funny how well my stuff works, considering how I'm doing it wrong.(channeling my inner John Larkin)QuoteYes, I did; lots of local capacitance attached to the parts of the PDN that matter. (Admittedly, around here a few 100 nF caps amounts to "a lot" of capacitance. Scale to suit.)When you think of power/ground plane pairs as transmission lines, you are really talking about a battle between distributed capacitance over distance and propagation speed over the same distance. Remarkably little energy actually comes out of that distributed capacitance, because there's not that much C to begin with.My whole point is that a plane that is significantly larger than the chip being powered is a waste of routing resources that accomplishes nothing that bulk capacitance close to the part can't accomplish.To put it another way: look at how an MLCC is constructed. Thatisa power+ground plane pair, just cut up into pieces and stacked to keep it out of the way. You can buy MLCCs with the planes stacked vertically, if that works better in your situation.

author: Stray Electron
author_rank: Super Contributor
timestamp: January 09, 2023, 12:03:42 am
content: FWIW, A lot of the early TTL stuff that I worked on used small buss bars for power and ground and there were no decoupling caps. The buss bars were two very thin metal strips about 1/4" tall with a Kaptan insulation sheet between them and the bars run down between each row of ICs and the bars had many legs on both the power and the ground strips and the legs connected to circuit board traces that were right next to every IC's power and ground pins. The strips had enough capacitance between them that they provided all of the decoupling that was needed for the ICs. Getting the power and ground off of the circuit board probably also helped with noise immunity and also allowed more room to run the traces that carried the signals and data. A 1 Mega Hertz clock rate was considered FAST in those days.

author: gnuarm
author_rank: Super Contributor
timestamp: January 09, 2023, 12:11:42 am
content: Quote from: KE5FX on January 08, 2023, 11:45:18 pmDon't know why you want to emulate him. The fact that your designs work only shows that you haven't had a problem yet, not that your ideas are sound.QuoteYou have still failed to show how you would route to a BGA where there's no space for a cap near the power pins.

author: gnuarm
author_rank: Super Contributor
timestamp: January 09, 2023, 12:13:39 am
content: Quote from: Stray Electron on January 09, 2023, 12:03:42 amIf you are talking about the rails that had pins to connect to power and ground, the ones I sawwerecapacitors. There were some that were simply solid metal and were designed as card stiffeners.

author: KE5FX
author_rank: Super Contributor
timestamp: January 09, 2023, 12:39:29 am
content: QuoteAt least some capacitors go on the back side. Usually there's not enough room for all of the ones the manufacturer specifies, so plane(s) under the BGA are used to provide low-Z paths to capacitors on the periphery.What Idon'tdo is extend the power planes all over the PCB, where they do nothing useful.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: January 09, 2023, 12:50:28 am
content: Quote from: Stray Electron on January 09, 2023, 12:03:42 amYes, those are the bus-bars I mentioned in #2 - effectively they made multilayer boards, using a 3rd dimension.They are still made for designs where currents are high enough.Some impressive examples herehttps://ep-ca.mersen.com/en/products/engineering/bus-bar-infrastructure?level1(some examples are even water cooled ! )This one has pin-pairs spread along the bus, and says :Telecommunications Board Level Power DistributionWhen board space is at a premium, laminated bus bars provide the perfect space saving solution.The bus bar is designed to be soldered into a PCB, and includes an integrated compliant pin connector, which allows for interchangeability of either the power supply or PCB.Size: 0.6” x 10” | Voltage: 60VDC | Conductors: .050” | Current: 80A

author: gnuarm
author_rank: Super Contributor
timestamp: January 09, 2023, 02:01:04 am
content: Quote from: PCB.Wiz on January 09, 2023, 12:50:28 amThat's something that might be of interest to me, but I can't find any real info on it. Do they have standard products, or are they all custom?

author: Siwastaja
author_rank: Super Contributor
timestamp: January 09, 2023, 09:37:35 am
content: Quote from: gnuarm on January 09, 2023, 12:11:42 amReal-world designs almost exclusively place the capacitors right next to the power pins, on theoppositeside; look at any motherboard/GPU/FPGA design.They do this even when two-sided assembly costs extra. There might be reasons for this...Quote from: KE5FX on January 09, 2023, 12:39:29 amBingo. Optimizing excess copper out of the power plane reduces it to "wide tracks", and allows combining multiple power nets on the same layer, with absolutely no effect on performance. The transmission line impedance of those wide tracks is, as I said, a few ohms. Because the transmission line is only coupled at the via, copper far away does not magically participate, so calculating the Z of a full 100x100mm copper clad is not useful.Transmission line theory is fine, but you have to know when it applies. It assumes perfect coupling from/to the line, which is not case when you connect with a via to a single spot of a wide transmission line. For the 100mm wide plane to couple into the device pins, the pins would need to have the same geometry; 100mm wide pins with, say, 0.16mm separation. Just like a 50-ohm coaxial cable needs a connector which also has 50-ohm geometry.So instead of transmission line model, we need even more complicated theory; basically a full blown physical EM simulation.No one is suggesting long and thin tracks (unless you want to deliberately LC filter). How wide, then? I think the width of the device(s) to be powered, plus the perimeter where the bypass caps lie, is quite understandable rule-of-thumb. Then you can couple to all the power pins and closeby capacitors from the track. Any copper outside this area has diminishing returns, regardless of whether you model it with electromagnetic wave propagation, or as a simplified model of L-C-L-C-L-C network.

author: gnuarm
author_rank: Super Contributor
timestamp: January 09, 2023, 09:56:40 am
content: Quote from: Siwastaja on January 09, 2023, 09:37:35 amBut you can't do that when the area is filled with vias for routing, as is often the case for BGAs. My point is, there's no need to putting the caps close to the power pins when you have good planes.I recall people obsessing with minute details of how the capacitors are connected to the pins, to shave off nH from the path. The reality is they were spinning their wheels by going to such picayune details that had little or no effect on the result.QuoteNot sure why you think such a complex process is required for every design. The one thing this all starts with, is knowledge of the di/dt characteristics of the chip being decoupled, yet no one has mentioned that.

author: David Hess
author_rank: Super Contributor
timestamp: January 09, 2023, 10:51:20 am
content: Quote from: KE5FX on January 08, 2023, 11:45:18 pmFor common mode signals, the power plane also minimizes the loop area and is the return current path. When I made large boards by hand, I added lines between grounds, and sometimes between power pins, just to do the same thing, but there was no power or ground plane as such.

author: EPAIII
author_rank: Super Contributor
timestamp: January 13, 2023, 09:42:00 am
content: A board layout that I have seen multiple times with the DIP chips was lining the chips in a grid, rows and columns, all oriented the same way. Ground and Vcc were routed on parallel traces between the two rows of pins with pins 1 and 14 (16, 18, 20, etc) connected with very short foil connections. And decoupling capacitors were installed on those parallel traces between every adjacent pair of chips and on the ends of the rows. A PCB with 100 chips had 110 decoupling capacitors. With 100+ decoupling caps on a PCB, a stray signal does not stand much of a chance.I have also seen top side, ground fences running across the multiple rows, connecting the ground traces in a grid. They were installed every three ICs or so in the grid layout. I don't know if they were standard components or special order for the individual PCBs.The same thing worked with power and ground on internal foil layers. Perhaps even better.Perhaps with later and faster series of logic chips this no longer works. But I can't imagine where you would go from there. Or is it an issue with chips of various different physical sizes and orientations determined by the other pin locations? But you seemed to be talking about DIP-14 and DIP-16 packages which is what I described.Quote from: MarkS on January 01, 2023, 08:32:44 pm

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 13, 2023, 10:31:44 am
content: Quote from: EPAIII on January 13, 2023, 09:42:00 amThe problem is the grid itself. The open area provides no shielding to the signals crossing it. Trace impedance goes way up in the region (150Ω+?), coupling goes way up (crosstalk between signals), so signal quality and radiation are all over the place. For edge rates much slower than the grid pitch, the magnitude of these effects is low enough that it's tolerable for TTL or CMOS thresholds, but faster logic will make a mess of it all (say, 74LVC and up; most 3.3V and below MCUs, ASICs, etc. are similarly fast).Likewise, there's voltage drop along the grid itself, due to its inductance. Consider a bus driver toggling all 8 outputs in parallel at the same time: the displacement current of driving that bus (their transmission line impedances, plus whatever loads along the way) pushes around VCC/GND in the local area, and particularly along the path of the bus (image currents). Meanwhile its inputs are coming in from distant logic and don't see the same relative bounce, so the bus driver's inputs see the opposite bounce. It can chatter or oscillate!With solid ground plane, the fields around each trace are confined locally, the image current flows directly underneath the trace; traces can be spaced pretty close together and coupling is still quite tolerable; and supply bounce is mostly confined locally (the trace + via + pad + pin inductance to the chip itself). The plane is a nearly ideal conductor joining points together: the inductance between points within the plane is almost always less than the inductance of vias joining into it in the first place.Tim