Data Bus Crosstalk Question - Page 1
Forum section: electronics / projects

author: Mr.B
author_rank: Unknown
timestamp: November 10, 2014, 08:52:22 pm
content: Hello all,I am wanting advice on potential crosstalk (interference) issues with using ribbon cable for multiple data transmission methodologies.Standard ribbon cable.Overall length: 400mmThe cable will have 4 IDC headers spaced roughly evenly along the length of the cable, connecting a controller board with 3 slave boards.I am undecided on the MCU at this stage, but is likely to be a Teensy 3.1.All data signals 5v. (level shifted if I use the Teensy)Option 1 – order of the signals across the cable:SPI-CLOCK (12 MHz – Talking to MCP4922 d2a and MCP3204 a2d)SPI-MOSISPI-MISOI2C DataI2C Clock (100KHz – Talking to AMC6821 intelligent temperature monitor)Serial Shift Register DataSerial Shift Register Clock (12 MHz – Talking to 74HC595)Serial Shift Register LatchGNDOption 2 – order of the signals across the cable:SPI-CLOCKSPI-MOSISPI-MISOGNDI2C DataI2C ClockGNDSerial Shift Register DataSerial Shift Register ClockSerial Shift Register LatchOption 3:Please advise a more appropriate solution.Many thanks.

author: free_electron
author_rank: Super Contributor
timestamp: November 10, 2014, 09:51:11 pm
content: signal ground signal ground and so on.if you can;t do that :SPIclkgndspimosi spimisogndvccgndi2cclkgndi2cdatagndssclkgndand so on

author: Neilm
author_rank: Super Contributor
timestamp: November 10, 2014, 09:54:40 pm
content: Personally I would have either0V - Signal - 0V - Signalor0V - Signal - Signal - 0V - Signal - Signal - 0VThat would ensure that each signal had a return close to it thereby minimising the EM emissions from the signal. As a minimum, I would ensure that there were 0V lines by anything that was toggling regularly like the clock. Especially at 12MHz[beaten to it]

author: marshallh
author_rank: Unknown
timestamp: November 10, 2014, 09:57:03 pm
content: Yes a ground for each signal is best practice. Make sure that physically this return path will be closest to its signal.If you have to compromise, always try to give clocks some seperation from the others. If you can, add source termination to all signals. Slew rate, not clock frequency, is your issue here.Recently I had to do this on a custom FFC. I dedicated the bottom layer to a solid ground return path for each single ended signal. This carries 50mhz data no problem over several inches.

author: Mr.B
author_rank: Unknown
timestamp: November 10, 2014, 10:27:57 pm
content: Many thanks free_electron, Neilm and marshallh.I figured that interleaving GND (0v) might be the case.I was trying to get away with a 10 way ribbon to keep the board connector to a reasonable size.I will change design and go with a 18 or 20 way ribbon.

author: free_electron
author_rank: Super Contributor
timestamp: November 10, 2014, 10:47:51 pm
content: you can play tricks :clkgndsignalsignalgndclkgndsignalsignalgndclkgndThe key is your clock.The data can suffer overshoot and 'grass'. as long as the data is STABLE , when a clean clock arrives.A clean clock = properly source terminated , target terminated and proper return path.Clock always arrives later than data. So keep that one clean and the rest can get hit by a penalty. it will still work rightfor i2c additional rules come into effect. these are open drains. NXP recommendsSDAVCCCLKGNDclock sits 'shielded' between two return paths : power and ground.

author: Mr.B
author_rank: Unknown
timestamp: November 11, 2014, 12:18:50 am
content: Many thanks free_electron.If my google fu is up to scratch:SPI Source termination...The series resistor plus the driver output resistance should equal the trace/line impedance.This may be difficult to calculate given the multi drop nature of the header placement on the ribbon and then additional short tracks on the slave boards.SPI Target termination...I should use something like a 10K pull up on SPI lines.Should the 10K pull up be at all 3 targets?For the i2c I will most likely use GND SDA GND SCK GND as the VCC (5vDC) supply to the slave boards is delivered on another cable along with 12v DC.And the usual 4K7 source end pull ups.