hybridfree/eevblog-posts huggingface dataset:
Elegant way to select output type from a register or wire ? - Page 1
Forum section: electronics / general

author: tchiwam
author_rank: Regular Contributor
timestamp: March 25, 2023, 07:05:13 pm
content: Is there a way to switch the output type from a register or wire ?In some cases I want LVCMOS33 output and in other cases it will be LVDS25Would also be nice to set other goodies like termination etc...The nicest way I have found so far is LVCMOS33 with out and !out

author: Someone
author_rank: Super Contributor
timestamp: March 25, 2023, 09:33:22 pm
content: Those are two entirely different things.Quote from: tchiwam on March 25, 2023, 07:05:13 pmSystemverilog does that.Quote from: tchiwam on March 25, 2023, 07:05:13 pmTool/vendor specific, usually you need to use device primitives and or external constraints.

author: BrianHG
author_rank: Super Contributor
timestamp: March 25, 2023, 10:20:20 pm
content: Termination can be selected via soft control on most modern FPGAs. Read up on your FPGA's advanced IO buffer primitive. Note that this is advanced and you will need to use a different custom primitive for every FPGA vendor and every different FPGA series that vendor sells.Voltage cannot be adjusted as it is a function of wiring the VCCIO pin for that IO bank.Unless you are running at the high megabit/gigabit, using one IO voltage for both 3.3v/2.5v with a software adjustable termination sequence, you can achieve functionality as long as you don't exceed the input max voltage compared to VCCIO wiring and use a true differential input instead of a emulated differential input. However, expect diminished peak performance with regard to bitrate, noise, and precision timing alignment.
Should I use one big always block or several smaller ones? - Page 1
Forum section: electronics / general

author: parkerlewis404
author_rank: Newbie
timestamp: March 25, 2023, 12:33:08 am
content: I have very little hdl experience, so wondering if anyone has any thoughts on how something like this is usually structured..I want to serially transmit a byte to an external device . The serial clock comes from that device and expects my data to change on the falling edge.Once all the bits have been shifted out, the device will shift out its data after 10-100usec.. and my fpga should latched each bit on the rising edge. Again, the device outputs the serial clock.I'm wondering if it's best to make one giant always block, that runs on an internal fast clock to keep track when to send the request, as well monitoring the clock level in order to transmits/receives the data at the right time. The slower serial clock would not be part of the sensitivity list and would just be sampled. Or should I separate the data-request time-keeping from the tx and rx process.Code:always @(negedge SCLK )begin// other always block will set register flag when time to shift out dataif ( dataOutputTime == 1'b1 )// state-mach to output data bit-by-bitendalways @(posedge SCLK )begin// other always block will set register flag when time to shift in dataif ( dataInputTime == 1'b1 )// state-mach to latch incoming data bit-by-bitendalways@(negedge PCLK or negedge PRESETN)// Check counter and if time to send , dataOutputTime <= 1// If data has been transmitted, then receive data dataInputTime <= 1VERSUS..// PCLK >> SCLKalways@(posedge PCLK or negedge PRESETN)begincase (fsm)3'b000 - 3'b111:// Check if time to send.. if so:// request data by updating output on every falling SCLK (not in sensitivity list)3'b100 : // get data// get input data by looping on every rising edge of SCLK (not in sensitivity list)Would love to hear any thoughts on this.. maybe there's other/better ways to do this. I've found plenty of syntax documentation, but not much in terms of the thinking that goes behind architecting a solution.Thanks!

author: hamster_nz
author_rank: Super Contributor
timestamp: March 25, 2023, 05:09:57 am
content: My preference is for every block to be logically complete (I.e. do the whole task). Sometimes a module might include more that one task (so an interface might have a TX and RX block).It irks me iwhen you get things that need both asynchronous and clocked logic.The traditional two process design methodology is a bit like training wheels - great to start with but soon becomes redundant.
Basys 3 Pmod Tips - Page 1
Forum section: electronics / general

author: AidanW
author_rank: Newbie
timestamp: March 22, 2023, 07:43:35 pm
content: Hello everyone!I am doing a project for my Electronics II class, and I would like to use the Pmod connectors to get a signal from a breadboard. The signal will be high (3.3V) or low, and drives some LEDs on the FPGA. Is there anything I need to be careful about when using the Pmod connectors? Do I need to connect the ground of the Pmod ports to the ground of the breadboard for reference? I looked at the master xdc file, and it looks somewhat straight forward, but if there's anything different than constraining the usual IO switches and LEDs, please let me know. I'm mostly concerned about frying the board or ruining the port.Thanks for all your help!

author: hamster_nz
author_rank: Super Contributor
timestamp: March 22, 2023, 08:12:32 pm
content: Hi! PMODs are pretty robust.Yes - you will need to connect the Ground of the PMOD to the breadboard ground (if you intend to use any GND connections on the breadboard).Some PMOD connectors are "high speed" others are "low speed" and have a 200 Ohm resistor in series - this may be an unexpected extra current limiting resistor for such things as driving LEDs.The one little annoyance is that they are unkeyed - so you can get your Power and data pins mixed up if not careful. Seems a bit odd for something aimed at the education market...Be careful when probing, as a slip of the ground probe can short the power rail. My solution to this is to use a PMOD-TPH2 (https://digilent.com/shop/pmod-tph2-12-pin-test-point-header/) that I have my logic analyzer connected to. They are cheap as so well worth getting a couple, and makes adding the analyzer into the mix pretty simple. MAKING YOUR OWN VERSION OF THESE IS AN EXCELLENT FIRST KICAD/CUSTOM PCB PROJECT - so much value for so little cost. A lifetime supply of these adapters for $2 plus shipping and a few dollars for connectors.Oh, and also be aware that the DRIVE_STRENGTH setting on a FPGA pin is not a current limiting setting - don't try to use it as one (for example to limit current to an LED). Think of it as how much current can be sourced/sunk while still maintaining a the high or low logic level. For digital high level, the 15mA setting sort of means that when loaded with a 200 Ohm resistor the pin will still be at 3V. The short-circuit current may be much higher.When connecting probes directly to a PMOD port I use a 2x5 male-male pin header block, missing out the Vcc pins. Keeps me from stuffing things up.
Anyone else misses jtag_loader? - Page 1
Forum section: electronics / general

author: glandaburu
author_rank: Newbie
timestamp: March 19, 2023, 08:29:41 am
content: Start-ups with recently designed boards are always tough, particularly when dealing with powerful FPGA or CPUs.For the former, when designing with Xilinx ICs, PicoBlaze is definitely a great handly tool: it can warn you about high-temps, and pop-out communication errors,... all with "52 to 119 million instructions per second" + "the ability to operate at the same clock frequency as the hardware" + "4.3% of the smallest XC6SLX4 and just 0.11% of the XC6SLX150T".Nevertheless, with the current so-powerful Vivado environment and 64-bit Wxx, the jtag_loader is not supported anymore. Yes, there are tricks here and there, but -as far as I know- is not the same.On the other hand, I came across an interesting xapp1191 note when I was dealing with a multi-boot issue a couple of weeks ago. The note provides a tcl script with which a hex file is loaded from the PC to the FPGA... I wonder if anyone else may also see it as a starting point for a jtag_loader.tcl script that just "makes the job". The embedded jtag_loader vhdl code seems straightforward enough for -at least- give it a try!Anyone agrees? I do think this could be the perfect scenario for such a tcl script...
TVS diodes in FPGA development boards  - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: March 16, 2023, 01:05:39 pm
content: Hi, I am wondering what are these TVS diodes and where in FPGA development boards we can use them and what is their purpose ?

author: pcprogrammer
author_rank: Super Contributor
timestamp: March 16, 2023, 01:51:12 pm
content: Maybe the full name gives a hint. Transient Voltage Suppressor.You can use them to protect inputs/outputs/supplies against high voltage surges that otherwise could brick your device. They are faster and can take more of a punch then diodes like 1n4148 or bat85.

author: dobsonr741
author_rank: Frequent Contributor
timestamp: March 16, 2023, 02:48:38 pm
content: Some good read:https://www.ti.com/lit/an/slvae53/slvae53.pdfand a video:https://www.ti.com/video/series/getting-started-with-interface-protection.htmlAt the end of the day TVSs are glorified zener diodes, with very exact specs on how to break down high energy pulses. Amazing how otherwise low dissipation/how small they are, while capable eat up >1KW in a few microsec.
DDR3 Data capture using ISERDESE2 - Page 1
Forum section: electronics / general

author: ddr_controller
author_rank: Contributor
timestamp: March 15, 2023, 11:08:01 am
content: I posted a while back that I am trying to make a custom PHY for the Arty A7 35T board. I think I got all the sending commands and writing figured however there is a bizarre thing happening to me with the capture circuit.In theory, DQS should be delayed in the PHY to center align DQS to DQ however after testing all the possible delay values for DQ and DQS I found the weird thing in the image. In short, CLK is capturing the DDLY that comes AFTER the DQS edge!!!The simulation is a Post Implementation timing simulationLink to the smaller project (only includes the ISERDES part and a TB) here:https://github.com/ESCHen99/test_iserdes
OSERDESE2 CLK and CLKDIV phase relation - Page 1
Forum section: electronics / general

author: ddr_controller
author_rank: Contributor
timestamp: March 03, 2023, 03:46:39 pm
content: Have anyone used OSERSEDESE2 with CLK and CLKDIV not phase aligned? I am confused by the UG471 documentation, page 161 says "The OSERDESE2 uses two clocks, CLK and CLKDIV, for data rate conversion. CLK is thehigh-speed serial clock, CLKDIV is the divided parallel clock. CLK and CLKDIV must bephase aligned." But in figure 3-11 at page 169 "Note: In Table 3-11, the CLK and CLKDIV clock edges are normally not phase aligned"

author: hamster_nz
author_rank: Super Contributor
timestamp: March 07, 2023, 08:03:13 pm
content: In the clocking section of that user guide it states:QuoteTable 3-11 is a table of latencies through the SERDES block.QuoteI read note at the bottom of the table as saying "in some cases, when CLK and CLKDIV are aligned to within the jitter of both clocks, the calculated latency can vary by one cycle".The alignment required to have this difference in latency occur is smaller than the phase alignment required between CLK and CLKDIV.I'm guessing somebody measured the latency in simulation and it was off by one cycle.

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 07, 2023, 08:08:01 pm
content: OSERDESE2 is for the 7 series if I'm not mistaken? Haven't used OSERDESE2 yet on Artix-7, but I've used OSERDES2 on Spartan-6, and CLKDIV for it required to be phase-aligned with the serial clock, usually generated using a PLL_ADV, dividing the serial clock by N.
Troubles while configuring Flex 10K20TC144 in PS mode from microcontroller - Page 1
Forum section: electronics / general

author: GTT95
author_rank: Contributor
timestamp: March 05, 2023, 03:24:30 pm
content: Hello,I am trying to configure Flex10K20 from a PIC MCU using 1 bit passive serial mode.The .rbf configuration file I get from quartus is exactly 28941 bytes in size. It is programmed into PIC's internal Flash and sent to FPGA upon each power on. After sending all 28941 bytes, starting each byte with LSB, I don't see CONF_DONE go high.However, while monitoring nSTATUS it goes low for 2µs, after 58ms following the start of sending data serially into the FPGA. The whole process of sending all 28941 bytes lasts arround 200ms.The fact that nSTATUS goes low for 2µs does it signify an error within the configuration process? Is nSTATUS not expected to stay low for the whole remaining configuration process?On what criteria does the device determine the configuration went wrong? Is the data checked on the fly? Shall all 28941 bytes be sent to have CONF_DONE go high?What could cause nSTATUS go low after 58ms, a wrong byte in the configuration file at this point?In the design INIT_DONE is left unconnected (as there is no need in PS mode to poll for it).Thanks a lot for helping me.
The VHDL poster you didn't know you need - Page 1
Forum section: electronics / general

author: hamster_nz
author_rank: Super Contributor
timestamp: February 23, 2023, 04:01:04 am
content: (Thanks to u/YoureHereForOthers on Reddit)

author: asmi
author_rank: Super Contributor
timestamp: February 23, 2023, 04:25:49 am
content: I know that I don't need this poster. Because I don't need VHDL

author: hamster_nz
author_rank: Super Contributor
timestamp: February 23, 2023, 04:34:56 am
content: Quote from: asmi on February 23, 2023, 04:25:49 amI prefer a language that tells me that I have typoed the signal name for a PCIe TX and RX pair, rather than one that lets you build the simulation, run the simulation for 200us and spent 10 minutes trying to find out why the PCIe link never comes up.That's how my day of mixed-language simulation has been... hope your day is going better!

author: ebastler
author_rank: Super Contributor
timestamp: February 23, 2023, 06:29:34 am
content: Boy, do I know I need that chart!I have had the page which (I think) is the original source of the chart bookmarked for years,https://www.bitweenie.com/listings/vhdl-type-conversion/.And I am using that bookmark often while writing VHDL...

author: asmi
author_rank: Super Contributor
timestamp: February 23, 2023, 02:09:52 pm
content: Quote from: hamster_nz on February 23, 2023, 04:34:56 amThat just shows that you don't really know that language. Which is typicals of VHDLers.I prefer a language which doesn't force me to write walls of stupid boilerplate code each time I need to create or instantiate the module, greatly reducing a signal-to-noise ratio of a code, and since code is read much more often than it's written, it trashes efficiency.

author: KaneTW
author_rank: Frequent Contributor
timestamp: February 23, 2023, 03:41:29 pm
content: Quote from: asmi on February 23, 2023, 02:09:52 pmI prefer knowing the type of my signal at a glance, vs having to dig through and find the documentation (often wrong) or actual usage.

author: ebastler
author_rank: Super Contributor
timestamp: February 23, 2023, 06:06:48 pm
content: Quote from: asmi on February 23, 2023, 02:09:52 pmThing is, I read pretty fluently. But I make errors when I write code. I like a compiler which catches these, and am fine with some redundancy in the written code to enable that.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 23, 2023, 08:32:28 pm
content: Quote from: hamster_nz on February 23, 2023, 04:01:04 amWhy not. Should be kinda obvious for VHDL developers, but possibly useful for beginners.
where to start? - Page 1
Forum section: electronics / general

author: professor_jonny
author_rank: Newbie
timestamp: February 21, 2023, 11:21:55 pm
content: I'm looking to make a memory like device to attach to the nand interface of a gaming console.Problem is fpga's and cpld's are not my thing and I'm intrested in advice /help designing a system.I was thinking I could add expansion pheripherials to the console by using the nand interface as a make shift expansion bus as there is really no other bus suitable for this task.What I plan to do is attach the fpga to the nand chip of a gaming console so I can read and write to it.The fpga will also connect to a second nand (256mb) on board my nand expansion device along with some ram (256mb) and possibly link to a Arm microcontroller.The plan is to have the ability to boot from the onboard nand (16mb) boot from my nand (256mb) with ram mapped from 256-512mbThis will give me an alternative signigicantly larger nand to boot from and 256 mb as ram window for Arm to device communications and offloading unused stuff from kernel and dynamic recompiling and patching of the kernel at boot.The micro/ fpga will also have a few spare I/O and buses for expansion prehiperials i2c spi usb bluetooth and that sort of thing to attatch things possibly in the future.What do you guys think?I just dont know where to look for advice, also price is of concern as I plan to make this and sell it, I was looking at an igloo m1 as a possibliity as it has an embeded arm core.

author: mon2
author_rank: Frequent Contributor
timestamp: February 22, 2023, 02:05:59 pm
content: My 2 bits (half a nibble)...1) review Gowin and the open-source tools. The Gowin devices will be a lower cost option.2) review the Tang Nano 9k by Sipeed. Well documented, low cost hardware from Aliexpress, etc. No hard CPU inside but they do offer other devices with a hard Cortex cpu. Any part with 'C' in the markings has the hardened CPU core.3) review fpag4fun on learning about verilog - there are other great sites as well.4) review lushaylabs.com to learn about the Tang Nano 9k. Gabriel's website is off the charts amazing and he is very responsive to feedback / Q&A's.
Altera standalone programmer tool, gone from the internet? - Page 1
Forum section: electronics / general

author: Berni
author_rank: Super Contributor
timestamp: February 20, 2023, 08:29:35 am
content: I want to give a costumer a quick firmware update for a Altera MAX CPLD. So i want to give them the simple standalone programmer software to get the firmware in via JTAG. However looking for it i found that there new overlords at Intel have completely replaced the download pages.As a result all the old links are now redirecting to this generic download page:https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html?s=NewestYou can get the old IDEs reasonably far back, as it should be since you often need a old IDE to compile for an old device. But they seam to have forgot any of the other extra tools (like the standalone programmer). So it seams you have to download the entire IDE of 8+ GB and then to install it it needs 25GB of space. Then you probably also need to register and get a free license from Intel to use it etc..What the hell Intel? If you are going to update the website to be in your new wanky modern style at least carry over all the downloads.Am i missing something here? Or is a whole overkill IDE+license the new workflow for simply loading a CPLDs bitstream over JTAG?

author: Daixiwen
author_rank: Frequent Contributor
timestamp: February 20, 2023, 11:55:38 am
content: I agree that the Intel web site is horrible, but when I clicked into the link forthe latest version of Quartus Lite, I could find the programmer in the "Additional Software" category.Of course whether 1.28 GB is a reasonable size for a programmer is another question...

author: Berni
author_rank: Super Contributor
timestamp: February 20, 2023, 01:37:32 pm
content: Oh thank you!Yeah i must have missed it with there crap website design. Yeah 1.2GB for a damn programmer is not great, but at least it is not the 25GB of the full IDE.

author: AK6DN
author_rank: Regular Contributor
timestamp: February 20, 2023, 11:47:57 pm
content: If all you want is the programmer tool for the Altera MAX series parts (ie, EPM7K), then the download for 13.0sp1 programmer only:https://www.intel.com/content/www/us/en/software-kit/711791/intel-quartus-ii-web-edition-design-software-version-13-0sp1-for-windows.html(go to Additional Software tab) is only 136MB.

author: tchiwam
author_rank: Regular Contributor
timestamp: February 21, 2023, 07:45:01 pm
content: https://github.com/trabucayre/openFPGALoaderWould this work ? I use it on Kintex7 stuff
TANG Nano 9K - non working external Flash memory (P25Q32SH) - Page 1
Forum section: electronics / general

author: up8051
author_rank: Frequent Contributor
timestamp: February 17, 2023, 05:11:31 pm
content: I have a problem with external FLASH memory (P25Q32SH) but only on newly purchased boards.I have two boards bought about a year ago and everything works fine on them.On the new ones bought about 2 months ago, access to the external FLASH memory does not work.I checked the physical connection between FPGA and FLASH and it is correct.Also the GOWIN programmer, when trying to program using the "exFlash Erase, Program thru GAO-Bridge" option, reports the error: spi flash not found.Have you encountered such a problem.Is it possible that there are faulty memories on the boards?Fake Tang Nano boards?

author: pcprogrammer
author_rank: Super Contributor
timestamp: February 17, 2023, 05:27:14 pm
content: You could remove them from the boards and test them with a dedicated programmer. That way you can check if they are fake, but in that case I would worry more about the Gowin chip being fake.

author: up8051
author_rank: Frequent Contributor
timestamp: February 17, 2023, 05:31:07 pm
content: Everything else (HDMI, FPGA, LEDS, oscillator) on the board works.

author: up8051
author_rank: Frequent Contributor
timestamp: February 17, 2023, 05:55:01 pm
content: Additional information, on the old board the memory is marked P25Q32H and on the new one P25Q32SH.But I couldn't find a difference in the datasheets

author: up8051
author_rank: Frequent Contributor
timestamp: February 20, 2023, 10:41:52 am
content: Looks like I found a solution, but I still don't know why it works.The new TangNano 9K modules are shipped from the manufacturer with a "PicoTiny" example (RISC-V pico SOC) pre-installed. The system sets the default SPI Flash mode to "DSPI+CRM" (I don't know what CRM means)If I switch to the "single SPI" mode (S command from the terminal) and then upload my program, it works correctly.If I delete the bistream and upload my program without changing the SPI mode first, the system does not see the P25Q32 memoryBut the P25Q32 memory should always respond to commands in Single SPI mode.
Vivado compatible FMC (HPC LA HA HB) w/ SFP+ - Page 1
Forum section: electronics / general

author: tchiwam
author_rank: Regular Contributor
timestamp: January 27, 2023, 04:00:55 am
content: Anyone having a suggestion for a dev board ?Need:1 fully populated FMC HPC with HA and HB1 SFP+ 10G1 JTAG usbIdeally Vivado Generation, I'd consider other FPGA brands too.Nice to have for config:-Gigabit ethernet-USB or USB to serialI will try to use the open source Ethernet coreI'd like to keep the pricing under the 1500$US if possible..I am IO BW hungry, won't need much space.I looked at the fpga developer site and found maybe 1 or 2 viable option, genesys2, Alinx, some really expensive stuff too...Any suggestions ?
Lattice Diamond verbose synthesis engine errors - Page 1
Forum section: electronics / general

author: lk.dgironi
author_rank: Regular Contributor
timestamp: January 20, 2023, 09:25:54 am
content: Hello,I'm working on a ECP5 project.I'm using Lattice Diamond 64bit 3.12.1.454 on Windows 10 x64.I usually write it in Verilog, using LSE as synthesizer.It happens that I mistype something. Even something simple like a wire without the ending.When it happens the only error i get on Output tab is something like:-- Verilog file '___filefullpath___.v' ignored due to errors (VERI-1483)ERROR - Failed to analyze design file '___filefullpath___.v'.Done: error code 2Error, Warning, Info tab does not help.I'm wondering if there's some setting I can use to enable a higher verbose to catch the error.Thanks!

author: ale500
author_rank: Frequent Contributor
timestamp: January 20, 2023, 10:32:09 am
content: While I normally avoid LSE and use synplify instead (produces smaller designs), its default error reporting can be sketchy too. In such cases, I run synplify manually from the tools menu, it provides more verbosity and describes those "error 9" enough that I find what I misspelled or borked.

author: lk.dgironi
author_rank: Regular Contributor
timestamp: January 20, 2023, 11:24:51 am
content: Thanks!One question about Synopsys. As far as i know Symplify is not free. Am i right?~ Previously reply with my other account, my mistake ~

author: ale500
author_rank: Frequent Contributor
timestamp: January 20, 2023, 02:48:15 pm
content: Diamond has both of them, and synplify (yeah, with 'n') is free with it.

author: lk.dgironi
author_rank: Regular Contributor
timestamp: January 20, 2023, 02:52:00 pm
content: Thank you, I thought it was an on fee component.I'll try it!... (yeah, with 'n') ... one of the typo error I was speaking aboutLOL

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 20, 2023, 08:32:33 pm
content: Yes, both are free to use in Diamond. LSE has some benefits in some specific cases, it's also usually faster. Pick what works best for you.Lattice is one of the few (if the only one?) vendors to provide both Synplify and their own synthesis engine, for free.Most others either provide one or the other.
DDR3 Strobe to data timing constrains - Page 1
Forum section: electronics / general

author: ddr_controller
author_rank: Contributor
timestamp: February 08, 2023, 07:48:05 pm
content: I don't see in the ddr3 docs from Micron where are the timing constraints between DQS and DQ. I read somewhere that DQ should center align to DQS but did not find where that is said in the Micron datasheet, nor did I find the allowed jitter. Does anyone know where this spec is?

author: BrianHG
author_rank: Super Contributor
timestamp: February 08, 2023, 10:49:34 pm
content: Read the full datasheet, it is there. And it is also within a few pages of the DDR_CK/CK# to command tolerances.

author: ddr_controller
author_rank: Contributor
timestamp: February 09, 2023, 04:45:54 pm
content: I really can´t find it, neither in the dc ac tables nor in the write section timing diagrams :/

author: asmi
author_rank: Super Contributor
timestamp: February 09, 2023, 05:34:15 pm
content: Quote from: ddr_controller on February 09, 2023, 04:45:54 pmMaybe you should read again.Read:Write:
QUARTUS-II/Verilog: Unexpected warnings implementing simple subclock - Page 1
Forum section: electronics / general

author: AussieBruce
author_rank: Regular Contributor
timestamp: January 09, 2023, 12:44:05 pm
content: Hello, I’m programming in Verilog under Quartus-II. My application needs a half-frequency clock, which I’m implementing as follows:reg wrtcyc ;always @ (clk) wrtcyc <= ~wrtcyc ; // This is line 67Synthesis brings up a the following errors:Warning (10235): Verilog HDL Always Construct warning at Datalink.v(67): variable "wrtcyc" is read insidethe Always Construct but isn't in the Always Construct's Event ControlWarning (10755): Verilog HDL warning at Datalink.v(67): assignments to wrtcyc create a combinational loopThe register and the overall build appears to be behaving correctly. Should I be concerned about the warnings? Is there a recommended way to do this simple task?

author: kmike
author_rank: Regular Contributor
timestamp: January 09, 2023, 12:52:18 pm
content: isn't it missing a posedge or negedge?I mean always @ (posedge clk)

author: AussieBruce
author_rank: Regular Contributor
timestamp: January 10, 2023, 12:44:40 am
content: Oh dear. Way too late at night.
Anyone tried Renesas ForgeFPGA ? - Page 1
Forum section: electronics / general

author: Hella_Wini22
author_rank: Contributor
timestamp: January 09, 2023, 06:02:08 am
content: I've tried Silego/DialogSemi/now Renesas GreenPaks and like them a lot.IMHO awesome idea for programmable "digital dust" at $0.5/chip, which can do many things, including voltage level conversion (1.8V-5V),I2C,SPI, analog functions, some even have MOSFET SWITCH or whole friggin MOSFET BRIDGE!Most importantly, its killer feature is reprogrammability on the fly. Chip is so simple that one can know what the each configure bit is forand flip it over I2C or SPI interface.But now they have new thing: GreenPAK on steroids - ForgeFPGA.Which is similarly small package, but has 1kLUT FPGA fabric, some SRAM blocks, IIRC FLASH block etc etc.At the same price: $0.5/chip.https://www.renesas.com/us/en/products/programmable-mixed-signal-asic-ip-products/forgefpga-low-density-fpgasFor some reason, whole "series" consists of just one model and Renesas seems coy about promoting it.​It has been some time after the announcement and one still has to jump through hoops if s/he want to play with it..

author: ataradov
author_rank: Super Contributor
timestamp: January 09, 2023, 06:07:26 am
content: There is a thread about them -https://www.eevblog.com/forum/fpga/new-fpgas-from-renesas/They initially promised Q2 2022 as a general availability date, but that obviously was a lie.There is nothing to try at the moment, since devices are not available to the general public. There are people that have samples, but you need to talk to sales people and all that nonsense.
Microchip's new family - PolarFire 2 details ? - Page 1
Forum section: electronics / general

author: Hella_Wini22
author_rank: Contributor
timestamp: January 08, 2023, 09:04:19 pm
content: After some rumors on MC forums we finally have an article on EEJournal:"Does 2+2=4? Microchip announces PolarFire 2; You Do the Math"https://www.eejournal.com/article/does-224-microchip-announces-polarfire-2-you-do-the-math/Unfortunately, all the guy has is bunch of guesstimates, based on some recent presentation.Is there a presentation date set for PolarFire 2 ?Any details that anyone would care to share early ?

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: January 08, 2023, 10:18:47 pm
content: Here is the video where Microchip gave a sneak peek at the RISC-V Summit.https://youtu.be/P5xGxedPMyMKey takeaways:• 2x Performance per Watt vs PolarFire1 (which already claimed 2x Performance per Watt vs Kintex-7 and Cyclone V)• 15x TOP/s vs PolarFire1• 2x Fabric Performance vs PolarFire1• Still SEU Immune but now supports partial reconfiguration• New Design Suite (alternative to Libero SoC)More details will be released at the Microchip Mi-V Summit in the Summer.
PS DDR Init fails: 0x00FD080030 PHY GeneralStatus Register0 stucks at Deskew ERR - Page 1
Forum section: electronics / general

author: LakshmiN
author_rank: Contributor
timestamp: January 04, 2023, 05:57:44 pm
content: Hope everyone are doing well..We have a board with RFSoC XCZU49DR with PS DDR 4GBWe are facing an issue with PS DDR Initialization, The following address returns this:Address: 0xFD080030 returns: 80C000FFWhich as per this register map: Zynq UltraScale+ Devices Register Referenceit is some Deskew done of read and write/ Eye training done error is showing.We have measured all the DDR Voltage and CLK seems to be fine. Is out of reset.Xilinx LINK:https://support.xilinx.com/s/question/0D54U000064Z0i1SAC/ps-ddr-init-fails-0x00fd080030-phy-general-status-register-0-stucks-at-deskew-done?language=en_USUpdates:We have tried reflow of DDRWe have tried reflow of FPGAWe have replaced the DDR, below are the observation after replacing the DDR, Still the same, Address 0xFD080030 returns different value of 808000FFDDR part: MT40A1G16RC-062E IT:B (Micron)Any suggestions would be appreciated. Thanks.

author: LakshmiN
author_rank: Contributor
timestamp: January 07, 2023, 04:09:48 pm
content: Any suggestions? would be helpful.

author: miken
author_rank: Regular Contributor
timestamp: January 07, 2023, 11:30:02 pm
content: Are the working boards (mentioned on the Xilinx forum) the same design, or different design?

author: LakshmiN
author_rank: Contributor
timestamp: January 08, 2023, 02:46:07 am
content: They are of same design.

author: miken
author_rank: Regular Contributor
timestamp: January 08, 2023, 08:50:27 pm
content: Googling suggests a JTAG integrity problem. Try lowering the JTAG frequency.Beyond that, I only have speculation from afar. PCB variation? PDN? It's good that you want to find the root cause but at some point you have to decide whether it's worth the time. Some problems are hard to disentangle. If you know you put in a lot of design effort in a particular area and it's thoroughly understood, then start by looking elsewhere. Or, sometimes a fresh pair of eyes will turn up something that was overlooked.
clock doesnt appear in pin planner - need advice - Page 1
Forum section: electronics / general

author: barnea10
author_rank: Newbie
timestamp: January 11, 2023, 11:21:57 am
content: hiI created the following simple design (see image)with clock_50 input doesn't show in the pin plannerafter successful analysis and elaborationplease advise how to add it to the pins listthank you!

author: BrianHG
author_rank: Super Contributor
timestamp: January 11, 2023, 11:50:41 am
content: You have selected show pins by 'Groups'.So, only grouped, multipin bus/ports will appear.Switch / enable 'View all pins' window selector which should show all IO pins, not just pin groups.

author: barnea10
author_rank: Newbie
timestamp: January 11, 2023, 12:12:58 pm
content: thank you !

author: AndyC_772
author_rank: Super Contributor
timestamp: January 11, 2023, 12:37:41 pm
content: I advise using the Assignment Editor, rather than the pin planner, unless you have a very complex pinout that you really need to visualise.AE allows pins to be allocated, but also voltage levels, drive strength, I/O voltage and so on - all of which need to be specified anyway.

author: barnea10
author_rank: Newbie
timestamp: January 11, 2023, 01:22:26 pm
content: thank you, ill try

author: barnea10
author_rank: Newbie
timestamp: January 12, 2023, 02:27:06 pm
content: I assigned the following (see image)I ran the compilation and it ended successfullyI ran the programmer successfullybut the LEDs do not count so I guessa. the clock is wrong (?)b. the chip I have is almost the same as I choose because the full chip type is not in the list of Quartos - how I can find the full chip type?thank you!

author: BrianHG
author_rank: Super Contributor
timestamp: January 12, 2023, 02:47:54 pm
content: Did you try pressing the key. In one of your modes, the LEDs would count super slow.Yes, the chip number needs to be the same. Though you can get away with a different final - speed grade suffix IE: C8/C7/C6/I7, but the real chip number should be available.Note you are using a very old Quartus, however this should not affect anything if you chose the right chip number...Are you sure you have the right pin numbers?Are you sure your clock is oscillating?

author: barnea10
author_rank: Newbie
timestamp: January 12, 2023, 02:57:10 pm
content: hithe chip I have is EP4CE6E22C8Nthe chip I choose is EP4CE6E22C8I downloaded the Quartus web edition just a week ago from intel sitehow can I check if the clock is oscillating ?

author: BrianHG
author_rank: Super Contributor
timestamp: January 12, 2023, 03:10:06 pm
content: Quote from: barnea10 on January 12, 2023, 02:57:10 pmChip selection is ok.You have a different error.You did not assign specific IO pins to your nets. You only chose which bank those IO should go to. Quartus could have placed those nets anywhere in the chosen 'IO_BANK_1'.Only the 'KEY' net has been assigned to the specific 'PIN_7'.

author: barnea10
author_rank: Newbie
timestamp: January 17, 2023, 10:33:02 am
content: fixed, its workingthanks !
Using Xilinx Platform Cable with non-Xilinx devices? - Page 1
Forum section: electronics / general

author: CaptDon
author_rank: Super Contributor
timestamp: January 04, 2023, 03:02:18 pm
content: I guess this is kind of a backwards question. Can the platform cable (I have 3 versions, the white parallel port, the black USB version and the red USB version, all genuine Xilinx) be used on things like the GAL series? Do other manufacturers (I am mostly interested in small CPLD devices) support JTAG'ing by use of the Xilinx platform device? It seems the platform device is failure prone and among the Xilinx ISE software there are problems even recognizing the platform device between old and new versions of Windows. Should I ditch the Xilinx platform devices and find something more generic/recommended? Thanks all!!! Cheers mates!!!

author: Jope
author_rank: Regular Contributor
timestamp: January 05, 2023, 12:54:31 pm
content: AFAIK, the answer is no. Xilinx platform cables are only supported by Xilinx software. Openocd, which supports more programming cables than any other software, does not support genuine Xilinx cables. And I've never seen vendor tools supporting other vendor's programming cables.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 05, 2023, 08:15:20 pm
content: Quote from: Jope on January 05, 2023, 12:54:31 pmWell, at least the Lattice ones (USB) are based on FTDI chips and should work fine with OpenOCD. (Conversely you can make your own FTDI-based JTAG adapters to work with Lattice tools.)
configuring FLEX 10K from MCU - Page 1
Forum section: electronics / general

author: GTT95
author_rank: Contributor
timestamp: November 18, 2022, 05:13:57 pm
content: Hello,I aim to use PS (Passive Serial) scheme to configure a FLEX 10K FPGA from microcontroller. Pins DCLK, DATA0 will thus be driven from MCU IOs. After configuration, same IOs will be assigned other functions, which means DCLK and DATA0 might continue pulsing after the FPGA was configured.My question: is there any issue which could lead the FPGA into troubles or is it safe (provided pin nCONFIG is maintained high to avoid reinitiating a configuration)?Thanks!

author: TomS_
author_rank: Frequent Contributor
timestamp: December 25, 2022, 08:00:23 am
content: Based on what I understand from the datasheets, once an FPGA signals that it has completed its configuration, it then cascades control to another FPGA (if it were to exist) via the nCEO pin.In such a situation, the data and clock signals (which are paralleled between all devices to be configured) would continue to pulse, but any FPGAs that have asserted their nCEO pins should no longer be observing them.So as long as you don't take nCONFIG low to initiate configuration again, it should be fine to do what ever you want with the data and clock pins after configuration is complete.Someone else could hopefully double check that this is correct.

author: GTT95
author_rank: Contributor
timestamp: January 05, 2023, 01:46:51 pm
content: Many thanks for your reply.The fact that other devices can be initialized without disturbing already configured devices most likely proves it should work.
Arduino Bootloader On Xilinx Arm Cortex Core? - Page 1
Forum section: electronics / general

author: hal9001
author_rank: Regular Contributor
timestamp: December 23, 2022, 06:40:48 pm
content: Hi all,I stumbled upon the free Arm Cortex cores for Xilinx FPGAshttps://www.arm.com/resources/free-arm-cortex-m-on-fpga.Is there a way to flash the Arduino bootloader on the cortex core such that firmware can be uploaded to the core over serial using Arduino IDE?Cheers!

author: ataradov
author_rank: Super Contributor
timestamp: December 23, 2022, 07:13:57 pm
content: This is just the core, you have to build the rest of the system to even get the serial port or any sort of memory. Once you build the system, you will have to port the bootloader, assuming that you are not going to implement the exact peripherals already supported by the bootloaders.There are no flash memories in the the FPGA, but you can use initialized BRAMs with the bootloader binary. The uploaded Arduino image would still be volatile and will disappear on power cycle. If you want it to be persistent, then you will have to use outside flash memory and connect that to the core.

author: asmi
author_rank: Super Contributor
timestamp: December 23, 2022, 08:02:26 pm
content: Quote from: ataradov on December 23, 2022, 07:13:57 pmAny FPGA board typically contains a flash memory used to store a bitstream, in most cases there is some leftover storage where you can store your custom code. If that is not enough, then yeah - you will have to connect more memory.

author: hal9001
author_rank: Regular Contributor
timestamp: December 26, 2022, 10:07:01 am
content: Quote from: ataradov on December 23, 2022, 07:13:57 pmIs there a bootloader for a existing Cortex m1 microcontroller that I can use if the Cortex core is set up identically as th microcontroller hardware?

author: ataradov
author_rank: Super Contributor
timestamp: December 26, 2022, 05:36:09 pm
content: There are no microcontrollers with Cortex-M1 core, only Cortex-M0(+).I don't really understand the question. In general, there are a lot of different bootloaders for different MCUs. But if you want it to work with Arduino, then you need to use Arduino bootloader. There is one for Atmel SAM D21, for sure.In reality, it is way easier to port the bootloader than match the hardware behaviour. Way easier.
GAL/PAL manual programming ? - Page 1
Forum section: electronics / general

author: strawberry
author_rank: Super Contributor
timestamp: December 11, 2022, 02:48:37 pm
content: is it possible to program simple IC manually? GAL22V10...cant find much info about how these IC are actually programmed nor actual internal circuits. my guess is same as parallel ROM chips

author: Beta_vulgaris
author_rank: Regular Contributor
timestamp: December 11, 2022, 04:13:40 pm
content: GAL16V8/20V8 use parallel address / serial data, and GAL22V10 both address and data are serial. You can find the diagrams on ELMchan or ATFblast etc.
FPGA MIPI CSI-2 Receiver Image ISP, making USB C Camera Lattice Crosslink NX  - Page 1
Forum section: electronics / general

author: RoadRunner
author_rank: Frequent Contributor
timestamp: November 27, 2022, 04:32:57 pm
content: Hello to all,I have recently published a MIPI CSI-2 Receiver , and Basic Image ISP with Crosslink NX FPGA from Lattice. I have published article on my blog and a basic description video as well. Its fully open source project you can find all sources of all components on my github.https://www.circuitvalley.com/2022/06/pensource-usb-c-industrial-camera-c-mount-fpga-imx-mipi-usb-3-crosslinknx.htmlhttps://github.com/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3
Alternative programmers for Microchip/Atmel ATF1500 series CPLDs? - Page 1
Forum section: electronics / general

author: JetForMe
author_rank: Contributor
timestamp: November 21, 2022, 11:00:40 pm
content: Are there alternatives to the USD230 Microchip programmer for the ATF1500 series CPLDs? I have anATMEL-ICE, and I've seen at least onepostwhere someone programs an ATF1504 using OpenOCD. The ATMEL-ICE seems to only be for Cortex-M devices, though. I also have another OpenOCD device (whose name escapes me right now!) that I've successfully programmed Feather Cortext-M devices with.Does anyone have any other experience or recommendations for this? TIA!

author: coromonadalix
author_rank: Super Contributor
timestamp: November 21, 2022, 11:10:05 pm
content: https://www.kanda.com/CPLD-Programmers.175.htmlATDH1150USB is a JTAG programming cable for Microchip ATF1502, ATF1504 and ATF1508 series CPLD devices.70$ usd, cant go wrong with this one, used it a lot for ATF1504they come with microchip software on their page

author: c64
author_rank: Frequent Contributor
timestamp: November 21, 2022, 11:15:28 pm
content: I use Altera Byte Blaster 2 (made it myself) - it's officially supported. Because I have a computer with LPT port.
VHDL  on CPLD vs. FPGA - Page 1
Forum section: electronics / general

author: CaptDon
author_rank: Super Contributor
timestamp: November 05, 2022, 08:31:46 pm
content: Greetings all. I am a newbie at this. I have a development board with the Xilinx XC2C256. I program these boards using schematic capture and have had excellent luck. During a lab clean out the boss gave me a Xilinx Spartan-3 'starter board' with all the cool features, switches, displays, VGA, Keyboard etc. and a book called FPGA Prototyping by VHDL Examples specifically for the Spartan-3 starter board. My question is as I learn VHDL can it be applied directly to CPLD's?? In the end I want to break out of Schematic Capture picking and placing logic blocks and interconnecting them with schematic representations of wires and buses and go to writing lines of logic in VHDL and applying them to these CPLD boards which our company uses for several lab projects. We use the CPLD boards because they are 'instant on' with power up so to speak and most importantly they DO NOT become un-programmed with voltage transients like the FPGA boards did. We have up to 4500 electrical horsepower near to these boards with big switching spikes. Thanks for your guidance!! Cheers!!

author: nctnico
author_rank: Super Contributor
timestamp: November 05, 2022, 09:19:53 pm
content: You can use VHDL with CPLD just fine. I have done several projects in the past. In the end it is all about getting optimised logic for the target device.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 05, 2022, 09:31:09 pm
content: Yes, besides, these days, there is a lot of offering for small, low-cost FPGAs that can replace what was earlier done with "CPLDs", but with much better performance and more features. All this using VHDL.Lattice has "instant-on" devices (MachXO2/XO3), Microsemi as well (now Microchip), using internal Flash. The MachXO3 can also come in OTP versions (actually, not one, but only just a few times programmable) in cheaper prices.

author: BrianHG
author_rank: Super Contributor
timestamp: November 05, 2022, 10:22:11 pm
content: Even Altera's Max7000 series PLDs (EPM7032 and up) are still available and compile in Quartus 13.1 with their full tool suite and simulator, meaning AHDL, VHDL, and Verilog support.Sizes range from 32mcell to 512mcell.
LVDS to USB Converter - Page 1
Forum section: electronics / general

author: themystick
author_rank: Newbie
timestamp: November 15, 2022, 09:21:00 pm
content: Hello,I want to design an LVDS to USB converter for my project. Actually, I am not experienced with FPGA design and I am trying to learn that.I have Zynq7020 board for my project. The first thing I do, I successfully setup PetaLinux and now I can see the one USB port as a device via UVC. The real question is I don't know how I can get the LVDS signal and serialize that and connect to the PetaLinux. I couldn't find any example for thatIs there anyone here who has any idea or document/example to give me some guidance?Thanks.

author: DC1MC
author_rank: Super Contributor
timestamp: November 15, 2022, 09:29:05 pm
content: That's really far from a beginner project, but start from here:https://docs.xilinx.com/v/u/en-US/xapp794-1080p60-camera

author: themystick
author_rank: Newbie
timestamp: November 15, 2022, 09:33:13 pm
content: Thank you for the documentation.Actually, I didn't realize that It's a tough job to do but I will do my best least. I think If I can handle that, I can do the same with other I/Os. I will check the document first. But at least, It seems it can be done theoretically.