decoding address lines to single Chip Select line? - Page 1
Forum section: electronics / projects

author: max_torque
author_rank: Super Contributor
timestamp: April 01, 2017, 02:47:29 pm
content: I have a 4 bit address line that will be used to select from individual 'cards' on a bus, and that bus uses SPI as it's transport protocol.Each card will be individually addressed, so when the address lines match that cards address (set by dip switches on each card) i would like to then generate the suitable chip select line to allow the SPI slave on that card to start loading the data present on the MOSI line.So, to my question, is there a single off-the-shelf address decoder IC available to do just this? I haven't been able to find such a device, but that may be due to using the wrong search terms etc! Alternatively, i could use some discrete glue logic (quad XOR gate into quad NAND gate) or program up a small micro to do this task? There is no high speed timing requirement to select each card, as they are only selected a few times a second, so latency isn't an issue for this decoder.

author: hcglitte
author_rank: Regular Contributor
timestamp: April 01, 2017, 02:54:27 pm
content: Hi,A simple search for 4000 series logic:https://en.wikipedia.org/wiki/List_of_4000_series_integrated_circuits4067 seems to do your job - single IC.https://www.digikey.com/products/en/integrated-circuits-ics/interface-analog-switches-multiplexers-demultiplexers/747?k=4067&k=&pkeyword=4067&pv7=2&FV=fff40027%2Cfff802ff%2Cffe002eb&mnonly=0&newproducts=0&ColumnSort=1000011&page=1&quantity=0&ptm=0&fid=0&pageSize=25HC

author: Kalvin
author_rank: Super Contributor
timestamp: April 01, 2017, 03:05:07 pm
content: Alternatively a quad 2-input XOR chip CD4070 or 74XX86, plus a 4-input OR chip CD4072.

author: grumpydoc
author_rank: Super Contributor
timestamp: April 01, 2017, 03:07:03 pm
content: Quote from: max_torque on April 01, 2017, 02:47:29 pmSo you are going to run the 4 address lines in parallel to all of the cards (16 addresses) and you want a 4-way DIP switch on the card which will make it respond only when the DIP switch and address lines match?But this system will only have a single SPI slave select?You want a 74xx85 magnitude comparator, or similar.

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: April 01, 2017, 03:13:26 pm
content: 74LS85, as pointed out above. You can also search on Digi-key under logic comparators.For a similar price as a 74LS85, you could also get an XC2C32A, with which you can implement a bunch of other stuff too. However, you need to be using 3.3V logic.

author: Kalvin
author_rank: Super Contributor
timestamp: April 01, 2017, 03:18:10 pm
content: 74XX85 has positive logic ie. the output will be "1" when the address matches, so basically you will still need an inverter gate.

author: FrankBuss
author_rank: Unknown
timestamp: April 01, 2017, 03:19:40 pm
content: Quote from: Kalvin on April 01, 2017, 03:18:10 pmA 74688 (e.g. this one:https://www.digikey.de/short/3wz8t0) has active low outputs.

author: hcglitte
author_rank: Regular Contributor
timestamp: April 01, 2017, 03:24:04 pm
content: OK, after reading your post more thoroughly... You say each of the 16 cards have a 4-DIP switch where you set that card's address.And you have a master MCU that will communicate with each card (in sequence or something)?How do you prevent that two or more cards have equal address (if set wrong)?One single IC of the type I mentioned will do the work if each slot has hard coded address (you don't need a dip switch on the cards in that case).In the other case, you will need 4 of the IC's I mentioned. Parallell connect the address inputs of the IC's to your MCU (SLOT_SELECT). Take the 16 inputs of the first IC to bit0 of the cards' address lines, the second IC's 16 inputs to bit1 of the cards' address lines and so on. Take each individual output of each IC to the MCU - these are now the 4 bit address for the selected slot# (selected by SLOT_SELECT). You can now read the DIP-switch-set card address at selected slot#. Then you can also make a program to detect if any of the cards have equal address - which they should not have.To select the appropriate chip select line, you will still need a another of the IC's as in my first answer.

author: grumpydoc
author_rank: Super Contributor
timestamp: April 01, 2017, 03:34:11 pm
content: Quote from: FrankBuss on April 01, 2017, 03:19:40 pmGood call, I was just thinking about what the best option was in discreet logic given that the output from the '85 is active high so not quite what you want to gate the active low SPI select.I think that you are stuck with two packages.You could use a quad XOR followed by a 5-input OR gate (the 5th beng the SPI select) - I'm not sure if there is a 5-input OR gate but there is a dual 5-input NOR gate (the 74xx260) so you could use the spare gate in that package to invert the output from the first (tying the other 4 inputs low).Or you could use the '85 to do the compare, then use a quad 2-input NOR (eg 74xx02). One gate to invert the '85 A=B output, one to combine that with the SPI select and then one as another inverter to make the result active low.Or you could use the 74688 but you still need to OR the identity output to get an active low SPI select for the cardWhich is best probably depends on what else you are doing on the card, spare gates etc.Edit: Ignore most of that.See Frank's comment below, you don't need to combine in the actual SPI select.

author: FrankBuss
author_rank: Unknown
timestamp: April 01, 2017, 04:36:29 pm
content: Quote from: grumpydoc on April 01, 2017, 03:34:11 pmWhy do you need the OR? You don't need an extra chip select line, just select another address first (the SPI slave don't care, if there is no clock), then the device you want and you have your nice falling edge CS signal. Same for the rising edge: at the end of the transfer select another address.

author: grumpydoc
author_rank: Super Contributor
timestamp: April 01, 2017, 04:41:43 pm
content: Quote from: FrankBuss on April 01, 2017, 04:36:29 pmOK, yes - if you're making it look like there is a single slave you are right.

author: Ian.M
author_rank: Super Contributor
timestamp: April 01, 2017, 04:56:03 pm
content: Lets make it a whole lot simpler - give each slot a decoded /CS line. Two 74xx138 chips can decode a four bit address for all the slots and combine it with the master /CS signal. Then on each board put an ID memory. Use aDS2406or similar with at least one I/O pin, and connect that I/O to the board's /CS line (via a 10K resistor so it cant drive /CS). The master can search the 1Wire bus to identify all the boards present and their capabilities, then poll the memory's I/O pin while selecting each slot in turn to determine each board's physical location. Once the map of slot address to board ID has been built, no further 1Wire activity is required in that session.

author: max_torque
author_rank: Super Contributor
timestamp: April 01, 2017, 06:42:04 pm
content: There is no requirement for auto addressing or clash detection or anything like that. I want to keep the device simple and accept that this brings the ability to mess things up by wrong selection of dip switches and the like!I have the SPI and address lines on the parallel 'bus'. Hardware 'cards' are not removable by the end user, but are simply there to allow me to expand the devices capabilities by adding more cards to suit the precise end use scenario. As such, i will be installing and setting the card addresses before the unit is used. I already have the ability to detect cards based on the functionality of the SPI slave that is on each card.So each card simply needs to listen to the parallel address lines, and when a matching bit map is present, pull the CS line low on the local SPI slave.

author: mikerj
author_rank: Super Contributor
timestamp: April 01, 2017, 06:50:58 pm
content: Are you saying there is no master chip select signal which is enabled by the address lines, you just want to decode the address lines and have the output of the decoder act like the chip select? If so there is a problem, any variations in latency between the individual address signals (or within the deocoder) could cause glitching, so you could get slaves briefly having CS asserted whilst the address lines change, messy and maybe problematic. Better to do as Ian suggests and have a master CS that is gated by the address decoder.

author: max_torque
author_rank: Super Contributor
timestamp: April 01, 2017, 07:10:41 pm
content: correct, currently there is no 'master' CS line, but i can easily add one!I'm not sure if address decoding glitches could cause an issue in my implementation (which is "Low speed" with individual cards only being selected once or twice a second) because even if a chips CS is asserted by accident, there will be no SPI clock pulses, and hence no data will get shifted in (or out) of the slaves?

author: Ian.M
author_rank: Super Contributor
timestamp: April 01, 2017, 07:45:58 pm
content: If you want even cheaper, but still self-configuring, put an ID resistor on each board connected to an open drain buffer. The other end of all the ID resistors connect to a single ID line, and pull it down when the corrisponding card is selected. Use a current source or a carefully chosen pullup resistor at the MCU end and feed it to an ADC input. That lets you quickly scan all the cards to identify what type they are without the protocol overhead and cost of the Dallas 1Wire ID EPROMs.An alternative not quite so cheap approach would be to have an extra pair of 74xx138 chips on the motherboard and an inverter to decode 5 to 32 lines (still with the master /CS strobing them) then give each card two /CS lines. The extra /CS line would select a SPI EEPROM for card ID.The only reasons *NOT* to design in a per-slot /CS signal are because you need compatibility with some old standard bus (e.g. IBM ISA) that doesn't support it, or you need a purely passive backplane.

author: FrankBuss
author_rank: Unknown
timestamp: April 01, 2017, 10:12:36 pm
content: Quote from: max_torque on April 01, 2017, 07:10:41 pmRight, should be no problem. But you have to read the datasheet of the chips you want to control, if you didn't program it yourself. E.g. some DACs latch the input data to the output with rising CS edge and might be a problem, if there was no new input data. If this is a problem, maybe then it is better to use a small microcontroller, which can wait some time after the address was changed and then read it again, to avoid glitches.It is crazy, they are even cheaper than the logic chips, like the PIC12LF1571 for EUR 0.53 (the 74HC688 costs EUR 0.86, both for one piece). This PIC has a special 128 bytes high-endurance flash region for writing (so like an EEPROM). You could program the type of card (or use the resistor divider), and a unique serial number, and with some simple protocol over the address lines you don't need the DIP switches anymore, but you can discover all cards at startup, and later use the same protocol for the chip select. Could be implemented in a few hours, but will save more hours in the long run when installing it at the customer site, if it is not just a one off product.If you really want the DIP switches, you need a microcontroller with more pins, like the good old PIC16F54, which costs 0.45 EUR. But it doesn't have EEPROM or flash that can be written from a program running on the PIC. The software would be trivial and Microchip even provides a programming service for it, if you want to sell lots of it.

author: rstofer
author_rank: Super Contributor
timestamp: April 01, 2017, 10:29:52 pm
content: It seems to me that you would just gate CS' with the board select signal. Set up the board select lines before starting the transaction. I have considered doing this very thing for a multi-card project.In some ways, it makes sense to use a small uC on each card because the uC can send other information like what kind of card it is. The uC would probably have two SPI ports, one to talk to the master and one to talk to the other devices on the card.

author: max_torque
author_rank: Super Contributor
timestamp: April 02, 2017, 12:13:36 pm
content: At the moment, it's definitely a "keep it simple, stupid" kinda project to avoid getting too tied down to it and investing loads of time and effort which isn't really warranted!Considering the cost, and flexibility a small micro on the cards brings that seems a good trade off. It turns it into a software optimisation task rather than a hardware one, which brings greater flexibility.It would be simple to have an "address learn" button, jumper, or similar, which when closed results in the micro taking on the value applied to the address pins at that moment etc. It also makes debouncing/deglitching, and changing CS from active High to Active Low etc trivial too.

author: ebclr
author_rank: Super Contributor
timestamp: April 02, 2017, 12:44:10 pm
content: http://www.ti.com/lit/ds/symlink/cd4063b.pdf

author: David Hess
author_rank: Super Contributor
timestamp: April 02, 2017, 06:31:16 pm
content: Quote from: Ian.M on April 01, 2017, 04:56:03 pmI was also thinking two 74138s also or a single 74154 but it seems max_torque wants to do decoding of the parallel address on each card so a 4 bit comparator is more suitable. I agree with Kalvin about a quad 2-input XOR gate plus a 4-input OR or equivalent which may be the least expensive way.

author: Ian.M
author_rank: Super Contributor
timestamp: April 02, 2017, 07:00:31 pm
content: Personally, if I HAD to decode on the card and was too cheap to use a magnitude comparator and DIP switch, I'd go for a single 74HC138 and jumpers to configure the address. A 4x3 block of jumper pins, output from the central line of 4, and each outer pin connected to a '138 output lets you select from three bits of address using a single jumper. Wire the remaining bit to the center of a three pin jumper, with its outer pins going to the EN and one of the /EN '138 inputs, with 100K pullup on EN and pulldown on /EN. Connect the incoming /CS line to the remaining /EN.