TH1520 Risc-V SoC - Page 1
Forum section: electronics / general

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 22, 2025, 04:39:15 pm
content: Has anyone tested any board with the TH1520 SoC yet?There are a few out there, such as the MilkV Meles and the BeagleV-Ahead, and the Lichee Pi 4A, probably others.The TH1520 is a quad-core C910, with an additional C906 core (that they say is dedicated to audio, haven't seen yet all that can be done with it). The C910 seems to be one of the most powerful RV cores out there, if one excepts the performance cores from SiFive (the P550?) From what I saw, it outperforms the SpacemiT X60 which can be found on the MilkV Jupiter motherboard and, I think, some laptops.Beagleboard has made the documentation available, which is quite nice:https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs?ref_type=headsThat should allow using it fully baremetal, although it certainly involves some work.

author: DiTBho
author_rank: Super Contributor
timestamp: July 22, 2025, 05:06:19 pm
content: Quote from: SiliconWizard on July 22, 2025, 04:39:15 pmThat would be interesting, for porting XINU.I don't have the time at the moment.Busy with other stuff, but I will look into this.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 22, 2025, 05:38:04 pm
content: The current SBCs around it are relatively pricey compared to the rest. Like, on Aliex, the Lichee Pi 4A with 8GB RAM AND 32GB eMMC is nearly € 200.

author: DiTBho
author_rank: Super Contributor
timestamp: July 22, 2025, 06:31:28 pm
content: Yup, just checked ...I have neither the time nor the budget.So I have to pass.Maybe in 2026.

author: brucehoult
author_rank: Super Contributor
timestamp: July 23, 2025, 12:50:49 am
content: Quote from: SiliconWizard on July 22, 2025, 04:39:15 pmSure. I ordered an 8 GB LicheePi 4A from the Sipeed store on aliexpress for $119 on May 5 2023. And a 16 GB one (and 128GB eMMC) for $179 on Jul 8 2023 after they were released.The OoO CPU is very fast when working in cache. Not quite as fast as P550, but a lot faster than the dual-issue in-order JH7110 or SpacemiT.Code:// 8.890 sec Milk-V Megrez P550 @ 1.8 GHz 210 bytes 16.0 billion clocks// 8.964 sec SiFive HiFive Premier P550 @1.8 GHz 210 bytes 16.1 billion clocks// 9.622 sec Milk-V Pioneer SG2042 C910 @2.0 GHz 192 bytes 19.3 billion clocks// 10.430 sec Sipeed LM4A TH1520 4x C910 @1.848 GHz 216 bytes 19.3 billion clocks// 11.445 sec Odroid XU4 A15 @ 2 GHz T32 204 bytes 22.9 billion clocks// 11.540 sec SiFive HiFive Premier P550 @1.4 GHz 216 bytes 16.1 billion clocks// 12.115 sec Pi4 Cortex A72 @ 1.5 GHz A64 300 bytes 18.2 billion clocks// 14.685 sec Lichee Pi 3A SpacemiT X60 @1.6 GHz 214 bytes 23.5 billion clocks// 14.885 sec VisionFive 2 U74 _zba_zbb @ 1.5 GHz 214 bytes 22.3 billion clocks// 15.298 sec HiFive Unmatched RISC-V U74 @ 1.5 GHz 250 bytes 22.9 billion clocks// 19.500 sec Odroid C2 A53 @ 1.536 GHz A64 276 bytes 30.0 billion clocks// 27.480 sec HiFive Unleashed RISCV U54 @ 1.45 GHz 228 bytes 39.8 billion clocks// 30.420 sec Pi3 Cortex A53 @ 1.2 GHz T32 204 bytes 36.5 billion clocksBeats Arm A15 and A72 on my primes benchmark also.Also has considerably better memcpy() speed than the VisionFive 2https://hoult.org/TH1520_memcpy.txthttps://hoult.org/JH7110_memcpy.txtThe vector processing is OoO with two pipelines and is to this day by far the highest performance we've seen on a RISC-V board. Just, sadly, it is RVV draft 0.7, not 1.0. But assemblers and compilers exist, so if doing actual work with code you write yourself is what you want rather than using off the shelf code then it's still the best. Not bad for a core from 2019.Weirdly, on software builds it is a little slower than the JH7110, even with the 25% higher MHz. I think it's the small caches with only 1 MB L2 shared between 4 cores, while the JH7110 has 2 MB L2 cache and the P550 EIC7700 has 256k private L2 cache per core plus 4 MB shared.So the cache is what really makes the different on the P550 machines vs the C910 machines. The OoO processing in L1 cache is not all that different.The C910 core does have a few quirks:- GhostWrite. An undefined instruction in the RVV opcode space writes physical memory instead of virtual memory, as if executed in M mode. Actual exploits have been demonstrated. Don't let untrusted users or software on your C910 machine.- unknown FENCE instructions trap (as unknown instructions usually should) but the spec says that in the FENCE encoding space unknown instructions should act as the strongest fence "FENCE RW,RW". This affects LLVM-compiled software that likes to insert FENCE.TSO even though no current RISC-V core treats FENCE.TSO any differently to FENCE RW,RW anyway. SBI emulates it, but costs a few hundred cycles.- C910 and C906 cores don't implement floating point sticky exception flags. At all. This makes glibc tests fail. I asked actual mathematicians about this and they were "meh, no one uses that stuff anyway". But they still should have implemented it.- neither the RVV 0.7 spec or the then current privileged spec said anything about vector unit OFF/INITIAL/CLEAN/DIRTY status bits, parallel to FPU ones. There were two right-sized "reserved" holes in mstatus, Thead picked one, the eventual RVV 1.0 spec picked the other one. So the kernel needs to know whether you have THead vector or RVV 1.0.- also in 2019 no spec existed for Physical Memory Attributes. Not even a working group existed. THead needed it, and picked some unused hi bits in page table entries. The eventual ratified spec used the same bits for PMA, but with different encoding.

author: brucehoult
author_rank: Super Contributor
timestamp: July 23, 2025, 12:58:06 am
content: Quote from: SiliconWizard on July 22, 2025, 05:38:04 pmThat's weird. I see $145 for the 8 GB RAM + 32 GB eMMC. It's $189 for the 16 GB RAM + 128 GB eMMC. I'm logged in and all. Official Sipeed store. As mentioned, I paid $119 for 8 GB + 8 GB in May 2023, and $179 for 16 GB + 128 GB in July 2023.Still, unless you need the (draft) RVV the Milk-V Megrez is a better deal now at $199 with 16 GB RAM, and considerably faster on most things.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 23, 2025, 01:01:25 am
content: Thanks. Yes, it's still a relatively "early" design and so does not implement RVV 1.0, different PMA, and so on.We can wish for a C920 (or whatever) with the same kind of performance (or better) and at last matching ratified specs for all defined extensions.Actually - the C910 core is open source, so if "anyone" is up to the challenge...https://github.com/XUANTIE-RV/openc910They haven't released the source code for their proprietary extensions though (AFAIK), but one could piggyback RVV 1.0 to openc910, PMA and some other niceties.Probably not for the faint of heart though.And of course, you'll have no silicon unless you have a few millions in your pocket.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 23, 2025, 01:04:28 am
content: Quote from: brucehoult on July 23, 2025, 12:58:06 amWell, not so weird. It's just the VAT + import taxes that we now have on everything on Aliex whatever the price.So - as an example - buying anyting from Arace will get you close to twice the price they show, when ordered in the EU. I think you have pretty good deals in that area in NZ compared to us...

author: brucehoult
author_rank: Super Contributor
timestamp: July 23, 2025, 01:10:24 am
content: Quote from: SiliconWizard on July 23, 2025, 01:01:25 amThat's C920 v2, and is coming soon in both the SG2044 (64 cores) which has turned up in Geekbench results a few times in the last 6 or 8 months, and also seehttps://x.com/sipeedio/status/1946122482064281829where option 1 is Zhihe A210.QuoteI recall an article or paper recently on someone doing just that, but can't immediately find it.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 23, 2025, 01:10:38 am
content: Found a better deal on Aliex for the 8GB/32GB:https://www.aliexpress.com/item/1005008588723306.htmlIt's listed at 153,99€ over here. Can you tell me what's the price for you?

author: brucehoult
author_rank: Super Contributor
timestamp: July 23, 2025, 01:49:34 am
content: Quote from: SiliconWizard on July 23, 2025, 01:04:28 amAh, ok sure, that's before tax, which Aliexpress adds on (15% for NZ) at checkout so things fly through customs. But then the shipping on that LicheePi 34A is $9.71.Arace don't and NZ tax, and if your order is under NZ$1000 (US$600) including shipping then there is no tax added when it hits NZ. But Arace add either NZ$26 (4PX) or NZ$60 (Fedex) shipping on a Mars, which usually works out a lot worse than Ali added taxes but having cheap shipping.That's not too bad on a Mars, but on a Jupiter or Megrez (Mini ITX boards) Arace wants NZ$162 for Fedex shipping with no 4PX option. Oww!! For a Pioneer (fully built in a vase) they want NZ$255 shipping. Even a Duo coss $26 for 4PX shipping.QuoteOur VAT is a bit lower than Europe, yeah. Plus we don't have tariffs on anything except I think some kinds of shoes and maybe still some clothing. Plus the $1000 minimum value before they even bother to add the VAT is better than a lot of countries. That's fairly new -- a couple of years ago it was only $400.You might think we're physically a little nearer to China but Auckland and Frankfurt airports are 9150 km and 9172 km from Hong Kong respectively. The volume of shipments probably has a much larger effect it e.g. Aliexpress could probably fill a plane to Europe every day with just their stuff, run a local warehouse in Europe etc.

author: brucehoult
author_rank: Super Contributor
timestamp: July 23, 2025, 01:51:25 am
content: Quote from: SiliconWizard on July 23, 2025, 01:10:38 amThat one is US$124.89 for me, pre tax and shipping, US$151.18 including both.

author: brucehoult
author_rank: Super Contributor
timestamp: July 23, 2025, 02:05:07 am
content: Quote from: SiliconWizard on July 23, 2025, 01:01:25 amWhat annoys me is that both THead and SiFive were in the position of needing various functionality before an official spec existed, and both just made something up.The difference is that whatever SiFive just made up for their own use either became the spec later, or else was at least grandfathered as one option in the spec.This annoyed me even when I worked at SiFive.I don't know whether THead could have communicated better with RISC-V International, put people on the working groups for the eventual specification, or what. But there is a clear difference in outcomes, and (I think unwarranted) criticism for implementing things in a non-standard way even when no standard existed at the time the design was frozen.

author: DiTBho
author_rank: Super Contributor
timestamp: July 23, 2025, 06:27:17 am
content: Quote from: brucehoult on July 23, 2025, 02:05:07 amI think this is what Linus T meant when he said "same mistake".He was annoyed because when these stuff come to the kernel, he has a lot of conflicts and confusion.

author: brucehoult
author_rank: Super Contributor
timestamp: July 23, 2025, 06:44:56 am
content: Quote from: DiTBho on July 23, 2025, 06:27:17 amIf that is what Linus meant then he is an idiot because1) there has never before been a situation where dozens (potentially, already near a dozen) of different organisations independently develop commercial CPU cores for the same ISA, with custom extensions explicitly not only allowed but encouraged, and the most successful ideas standardised for all to use in future, and2) it's not some kind of accidental mistake through ignorance of the past, but a deliberate philosophy and strategy.If it's a mistake then it's a new and unique one.

author: DiTBho
author_rank: Super Contributor
timestamp: July 23, 2025, 08:39:16 am
content: Quote from: brucehoult on July 23, 2025, 06:44:56 amI don't know why you've been getting so annoyed lately, almost always with my posts.I don't know if you have a problem with me, but I don't like the tone you're using.Git? Idiot? First of all, respect!No one's saying anything against anything! Someone interviewed Linus and he "vaguely" said that, so it's my speculation but I think he vaguely said that becuase people don't make "clear specs" and "develop haphazardly" and only then "correct stuff": this is "not optimal" because then you have to "constantly tweak the sources" and fill them with if() else if() else if()... else ... to support all the various "Quirks"."Quirks" are difficult to be maintained as maintaining them consume a lot of time, and it's high error prone.Exactly the mess that occurred with MIPS before the MIPS32 fixes, when the "cache behavior" of { MIPSIII, MIPSIV } depended on the manufacturers, that is, NEC was not the same as TOSHIBA, and among the various NECs there were even different behaviors... because there were no clear specs and it was necessary to probe the CPU, get the version, the revision, and combine these information to support different handlers ...Linus T. develops a kernel, and every time - I have seen this in person with MIPS - people sends a pull request, it gets a bunch of problems to fix, and waste a lot of his time!A few weeks earlier the interview, Linus had gotten pissed off about an HPPA pull request... he wasn't just pissed off only about RISC_V and MIPS, he was pissed off about "many things in general", including the problematic "bcache file system" (6.1*-something) ... in fact, they'd exchanged insults, like "your code sucks" (he wrote "turd") referring to something he didn't like at all, and the fact that the pull request required inclusion test-cases, a mistake people'd made in the past and which Linus had already explained was a full "no-go".And for the record, I'm not defending Linus... since he has consistently rejected all Xscale pull requests for the Zaurus kernels from the 2.6 to 4.* families.Back to the 2000s, 2.6.22, 2.6.23, 2.6.24, and 2.6.26 have a whole series of patches developed by Russian hackers—you can still find links to their Russian forum by googling them—integrated and modified by other developers in Japan, then redistributed on OE.I mean, how absurd this all is, and all because Linus never accepted them! And only in the end did he accept the request, and only after the intervention of a professional developer, in line with Linus's opinions.So, basically, the problem is being scattered during the development because no clear specs and or guide lines, and I think it's reasonable.

author: brucehoult
author_rank: Super Contributor
timestamp: July 23, 2025, 10:58:35 am
content: Quote from: DiTBho on July 23, 2025, 08:39:16 amI'm not annoyed, and not at you.I appear to have replied to your messages seven previous times in July, one was with regard to the same Linus remark, and most of the others were about ancient Macs where I would have said we were in general agreement.