Review Project Idea: Modular TTA CPU (kit) - Page 1
Forum section: electronics / projects

author: obiwanjacobi
author_rank: Super Contributor
timestamp: December 12, 2019, 10:18:34 am
content: A Transport Triggered Architecture (TTA) is an alternate CPU architecture that uses a set of internal busses to move data between functional units (potentially in parallel) and trigger output which then can be moved toward other Function Units (FU) etc. (see wikipedia)The project idea is to make these internal buses an extension point where custom function units can be added as modules. Each FU module decides how it connects to these buses and what function it performs - when it's triggered etc.HardwareA core module that will be supplied performs memory access, instruction fetching and contains one (or more) address registers - a program counter at the least.It also implements instruction decoding to direct data to the correct internal buses and enable the correct FU's. The core module will also implement a couple of FU's itself to provide a basic set of functionality.- Load and Store unit. Allows data reads and writes from/to memory.- (Conditional) Branch - manipulates the PC and possibly StackPointer as well for call-return branches.- A Constant register for constant value loads (see ISA), available as FU output.The core module also has an increment/decrement function it uses for PC and possibly SP.Additionally several (address-wide) index registers could be present to work in conjunction with the load/store unit. That would also require an address-wide adder then. The adder would be used for internal functions only and not be available as a FU.The core module would provide a CPU that does nothing but has the basic plumbing laid out.(Edit:) I could see the core module (or an addon of sorts) also providing a way to program the instruction memory from a PC. Perhaps a small MCU with USB support that DMA's into the on-board RAM (in a no ROM design). But this is still to be fleshed out further (also dependent on user requests).The user can build it's own FU to make the CPU do interesting operations.(Edit:) The core module as well as the FU modules would be build in regular hardware (not a HDL design inside an FPGA). I envisioned people might want to build their FU modules in regular 74-series TTL. The goal here is to have an educational journey when designing and building these modules. Look at the RC2014 Z80 modular design and you'll have an idea what I mean.Instruction Set ArchitectureBecause the core module does the instruction decoding the ISA is fixed independent of any FU's.This would bring building an assembler/compiler within reach.There are only two instructions:1) move data from a source FU output to a destination FU input.2) load a value into the Constant Register.Both instructions are encoded into a 16-bit value where the MSBit indicates a move or a constant-load instruction.---Do you think (some) people would be interested in this?General suggestions?

author: tggzzz
author_rank: Super Contributor
timestamp: December 12, 2019, 10:28:45 am
content: You will get extremely well-informed responses to that if you post it on the usenet group comp.arch.The denizens areextremelyexperienced in software and hardware for many kinds of architecture.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: December 12, 2019, 10:36:22 am
content: I am just a hobbyist and fear that I would not even understand their responses!But it's a good suggestion for reviewing the technical design.However this may be a better place to gauge if people are interested or not...?

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: December 12, 2019, 01:26:37 pm
content: I don't understand what you are asking us to respond to. You have fastened onto a very old idea, data flow machines. There already was a large number papers written on these before I took my computer architecture classes (1979-82). Every few years someone comes up with the same idea, gives it a new name and adds maybe a small twist then goes nowhere with it.Sorry to sound negative. I like these type of architectures which favour functional languages. We are long overdue for something better than the current Von Neuman/Harvard type machines.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: December 12, 2019, 01:47:18 pm
content: All I am asking if there are people that would like this sort of thing and build either a kit with functional units or design and build their own functional units. Then run small programs demonstrating the workings of the functional unit. It would be mostly hobby or educational.The reason why I chose TTA is that I saw an easy way to make it extensible. I envision a RC2014 type of setup with a bus plane, and a core module and slots to plugin your custom functional units.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 12, 2019, 03:10:35 pm
content: It looks interesting, although as said above, not quite new in itself.One thing I'm wondering is whether it would not add some overhead/latency compared to a traditional architecture? Also would it lend itself well to pipelines?I think (if you haven't already) you should compare this with a classic architecture point by point and see where all the drawbacks and advantages would lie. One clear advantage would be modularity, but are there many others?Prototyping this on FPGA would be a first step to really get some people interested IMO. While it may be interesting in itself, it's again not very new and cpu concepts are to be found by hundreds out there... so a pure concept is not very likely to attract a lot of interest IMO.As to comp.arch, I hadn't been there in ages. Whereas many/most usenet groups these days have little activity (or still a lot like comp.lang.c, but with a lot of trolling), this one seems still pretty active and not too polluted. I'll have a look.

author: tggzzz
author_rank: Super Contributor
timestamp: December 12, 2019, 03:39:39 pm
content: Quote from: SiliconWizard on December 12, 2019, 03:10:35 pmComp.arch is pretty high SNR.Sci.electronics.design is the wild west, but in between noise there are extremely high quality posts from, among others, Win Hill of TAoE fame.Comp.risks is extremely high SNR and low volume -everyengineer should read it.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: December 13, 2019, 12:16:11 pm
content: This is what I am planning to use to prototype it...

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 13, 2019, 04:37:26 pm
content: Quote from: obiwanjacobi on December 13, 2019, 12:16:11 pmHmm, the picture seems to be a broken link. Or maybe what you're planning is VERY minimal?

author: tggzzz
author_rank: Super Contributor
timestamp: December 13, 2019, 04:45:59 pm
content: Quote from: obiwanjacobi on December 13, 2019, 12:16:11 pmDo those boards include power and ground planes?If not then you would be wise to stick to using old logic with slow transition times (N.B. clock frequenncy is irrelevant).

author: iMo
author_rank: Super Contributor
timestamp: December 13, 2019, 05:37:58 pm
content: Interesting. Would not be this project perfectly suited for an FPGA?