weird stair-stepping on probing 68k address pins - Page 1
Forum section: electronics / projects

author: keitheevblog
author_rank: Regular Contributor
timestamp: March 18, 2025, 05:50:46 pm
content: I've used a logic analyzer for years to observe the Amiga in action, and everything has always behaved as expected. However, I'm troubleshooting signal integrity issues with an attached expansion card, so I’m using an oscilloscope to examine address pins.I've tested multiple Commodore Amiga A500 units—each boots and works fine—and they all show the same behavior. I’ve also tried different scope probes and verified them using the built-in tester. For clarity, no device was attached to the expansion port during these measurements.Attached is a scope trace of A4, but A3 are A5 are also exhibiting the same behavior. I'm using a Keysight MSOX-2024A with a 10:1 probe, DC coupling, and a 20 MHz bandwidth limit to reduce high-frequency noise (though disabling this makes no difference). I've experimented with different grounding points, including a ground pin on the 68K.The peak-to-peak voltage, including undershoot, is nearly 7V!Could this be due to multiple drivers, weak pull-ups, or bus arbitration issues?I'm inclined to think that it's either a measurement artifact (ie I'm making a mistake during probing), or it's just the way it is.... Just seems goofy to me!Please see the attached image.ThanksP.S. Also posted this to an Amiga-specific forum, so please forgive the repetition if you're a member of both

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 18, 2025, 06:55:15 pm
content: That’s pretty much as expected for TTL, with bus crosstalk.They have emitter follower drive, which can pulse higher if a crosstalk channel that was low, goes high.If you probe two bits, you should see the effect.Provided the logic is valid, it works fine.

author: pqass
author_rank: Super Contributor
timestamp: March 18, 2025, 06:55:55 pm
content: Addresses are only valid if /AS is low.On my breadboard 68K8, I get a weird non-TTL 1.5V on A2 if /AS is high which is expected as the address bus is not being driven and there aren't any weak pull-ups.In your case, it could be different loads being enabled. Anything over 2.5V is considered high and valid lows should stay below 0.8V.

author: tggzzz
author_rank: Super Contributor
timestamp: March 18, 2025, 07:19:03 pm
content: I suspect there are three effects.There is a repeatable undershoot on the negative going edges. This may be due to poor probing technique, e.g. a 6" long ground lead on the probe. Assess that by looking at the transition and undershoot, and using a spring clip on the probe.The amplitude of the signals is the kind of effect you would see with an overcompensated *10 probe. Assess that in the standard way!The "crenellations" on the +ve peaks is probably a standard TTL output, which can be anywhere from 2.4V to 5V.

author: keitheevblog
author_rank: Regular Contributor
timestamp: March 18, 2025, 07:46:53 pm
content: Quote from: pqass on March 18, 2025, 06:55:55 pmThis is a good point that Address Strobe literally tells you that the address is valid, present, stable, and ready to be read. I wonder if the "goofy" readings are in-between AS assertions. Easy enough to probe that alongside.Thanks

author: tggzzz
author_rank: Super Contributor
timestamp: March 18, 2025, 07:58:23 pm
content: Quote from: pqass on March 18, 2025, 06:55:55 pmTo be more precise: output voltage should be >2.4V or <0.4V to be valid. An input voltage >2.0V or <0.8V is interpreted as a logic high or low respectively. That gives 400mV noise immunity.

author: keitheevblog
author_rank: Regular Contributor
timestamp: March 18, 2025, 08:31:19 pm
content: Quote from: tggzzz on March 18, 2025, 07:19:03 pmI am using a 6" ground lead. HOW THE HECK does one find a ground close enough to what you're probing and physically manipulate to hold that in place, while also playing with the scope?QuoteI performed the probe compensation.... there was a very minor tweak needed, after adjusting the waveforms do look better. Also adjusted to a more typical 2v/div height.QuoteCan you please help me understand what this means? The voltage wouldn't go straight to +5v and stay there for the duration? I'm still seeing that stair-casing.... and the variation is as much as about 1v. From about 4.2v to 5v. I'm not worried about it, but still curious.See attached for a new image.Few things to note:/AS is in green on the bottom and active low. About 560ns apart which lines up with a 8-cycle (s0-s7) / two phase(??) clock memory accesstop address line in yellow.The full range between ground and the peak is about 5.2v, see delta y.The signal looks well behaved whenever /AS is asserted.Thanks!

author: tggzzz
author_rank: Super Contributor
timestamp: March 18, 2025, 09:37:27 pm
content: Quote from: keitheevblog on March 18, 2025, 08:31:19 pmhttps://entertaininghacks.wordpress.com/2015/04/23/scope-probe-accessory-improves-signal-fidelity/https://entertaininghacks.wordpress.com/2016/09/17/scope-probe-accessory-higher-frequency-results/Welcome to the late 1980sQuoteIt should go straight to a voltage level representing a valid logic signal; each logic family has different input and output voltages for valid logic levels. See, for example,https://learn.sparkfun.com/tutorials/logic-levels/allorhttps://www.ti.com/lit/SDYU001QuoteSet it up so that the /AS asserted fills most of the horizontal space. Trigger on /AS being asserted. Set infinite persistence, and let it accumulate traces.The resulting "eye diagram" will show you whether or not the logic levels are always valid when /AS is asserted.What is the Vcc PSU rail voltage? A signal going above that is probably a probing artefact.

author: keitheevblog
author_rank: Regular Contributor
timestamp: March 18, 2025, 10:21:55 pm
content: Thanks for a link to that probe accessory. I'll take a look!The Signetics variant of the 68K in use is 5v CMOS.I’m familiar with the various logic families and how they affect voltage thresholds, but I appreciate the links— that TI guide looks great!I should have been more specific—my question is why we’re seeing variations and steps in voltage, such as 4.4V for a while, then 4.6V, sometimes 5.2V, etc. What’s happening during those periods that causes the voltage to fluctuate? Could it be other devices drawing varying amounts of power, affecting the supply’s ability to maintain the load?Great idea for that eye diagram -- I have not done this before. If I'm reading this right, the highest low is +0.375v, and the lowest high is +3.75v. Looks good, right?See attached.Thanks!

author: pqass
author_rank: Super Contributor
timestamp: March 18, 2025, 10:37:36 pm
content: QuoteGiven any number of TTL (compatible) ICs of various families (F, LS, HCT, etc.) and from different manufactures, there is a variation in VOHbut should always be >2.4 <=Vcc.Depending on which address bus device has been enabled (/CS=low), they may present a different load to the bus.For example, my breadboard 68K8 has these address bus devices: CDM62256E10, AM29F010B, PC16550CN, CP82C55AAnd each /AS=low may be enabling any one of these at different times with the second and last being lower-power CMOS technology.As for the delta-Y=5.2V, have you checked Vcc? It could be a bit high (yet still under TTL max of 5.25V).Also, there could be a bit of ground resistance lifting the voltage up.Check the voltage difference between the Vcc pin of the chip driving A3 and GND pin of same chip (ie. move oscilloscope GND lead to here).

author: tggzzz
author_rank: Super Contributor
timestamp: March 18, 2025, 10:50:01 pm
content: Quote from: keitheevblog on March 18, 2025, 10:21:55 pmThat's the nominal specified voltage. What is the actual voltage?QuoteUse the scope to look at the supply voltage.It is probably due to resistances and crosstalk inside the IC. It doesn't matter so long as it is within spec.QuoteI don't know enough about your scope to understand all the features of the trace, but that sounds about right.Don't forget your probes tip impedance is <1kOhm at 100MHz, and that loading will affect the waveform, but probably not enough to be relevant in this case.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: March 18, 2025, 11:10:39 pm
content: Quote from: keitheevblog on March 18, 2025, 10:21:55 pmCheck the Vcc waveform.This is just capacitive coupling between outputs, as mentioned above, due to TTL having an emitter follower, which is not a low Z to Vcc. It allows the voltage to go above Voh.If you add a pull-up resistor to 5V those effects will reduce, but they do not affect normal digital operation.

author: tggzzz
author_rank: Super Contributor
timestamp: March 18, 2025, 11:29:44 pm
content: Quote from: PCB.Wiz on March 18, 2025, 11:10:39 pmThe crenellations can, in general, be seen in TTL outputs at any frequency. That rules out capacitive coupling.TTL inputs, including those buried in an IC, draw significantly different current in each state. Such changes in conjunction with internal resistances, is sufficient to explain the changes in output voltage.

author: keitheevblog
author_rank: Regular Contributor
timestamp: March 19, 2025, 01:25:08 pm
content: Just wanted to follow up and say thanks for everyone who replied.I learned a bunch!Keith

author: tggzzz
author_rank: Super Contributor
timestamp: March 19, 2025, 05:39:49 pm
content: Quote from: keitheevblog on March 19, 2025, 01:25:08 pmYour welcome. It is a pleasure to guide someone that thinks and listens