Mosfet driver IR2110 - undervoltage lockout  - Page 1
Forum section: electronics / projects

author: PeterFW
author_rank: Frequent Contributor
timestamp: April 13, 2016, 11:46:15 pm
content: Hello!Once more, i can not wrap my mind around something... i would be very gratefull if someone could help me out...The IR2110 Mosfet driver has an unvervoltage lockout for both channels.But... i can not figure out what that meansLets take this schematic of an h-bridge as an example:http://2.bp.blogspot.com/-dlEcbNapBZ0/UPvnk7y2MuI/AAAAAAAAAZ4/bfSogInXgj4/s1600/IR2110+-+3.pngI have +12V on VCC, +5V on VDD and +300V as the supply for the load through the mosfets.If i assume the +12V and +5V are stable, can the supply marked with +300V go below the undervoltage lockout threshold?Or, in other words, could the supply for the load through the Mosfets be just 0.5V or 1V?Greetings,Peter

author: Siwastaja
author_rank: Super Contributor
timestamp: April 14, 2016, 07:52:37 am
content: UVLO is absolutely crucial for the high side of a bootstrap controller (and very highly recommended for low side too, it's practically always there too), because the design itself can never guarantee that there is high enough supply voltage available to drive the high side FET; and there never is when the system starts. And, as you may know, switching FETs with too little voltage on gate will lead to their immediate destruction due to huge power dissipation when the FET stays in its "linear" region.Practically, this means that you just need to supply Vcc which is at least the UVLO hysteresis high level + some safety margin. Recommended Vcc seems to be 10V. When you start operating, the boost cap is empty and the high-side driver is disabled by the UVLO, but low side is working given that your Vcc is high enough. When you enable the chip and start applying pulse, the low side driver works, pulls switch node low by your switching FET, and this charges the boost capacitor; now, when the low side lets go, the high side has enough voltage to work with (in the capacitor), goes out of UVLO state and things start to work. If the low-level pulse was too short, the capacitor may not have enough voltage, but the FETs are not destroyed, it just takes another pulse to get it going.So, UVLO guarantees that the gate drive always has at least 7.0V (VBSUV-and VCCUV-on "Static Electrical Characteristics" in the datasheet) to work with. Furthermore, the datasheet specifies that the driver stage drops max 1.2V (VOH), so the design guarantees 5.8V gate drive!tldr; UVLO makes it work. You don't need to think about it too much. You need to apply pulse with duty cycle considerably less than 100% (say, <90%) so that the boost cap stays charged. Otherwise it stops working, but doesn't blow up.BTW, as a side note, this guaranteed 5.8V gate drive is not enough for most of the FETs this chip is intended to work with! As usual with too many actual, real chips, the chip is not specified to work at all in it's specified worst-case conditions, but it may self-destruct in its intended usage! But normally, it works just fine, you kind of need to trust that the actual part you use is not performing at the worst combination of minimum/maximum ranges. This is, however, something that pisses me off as a designer. You need to trust that everything goes fine, everyone else does it this way, this part isdesignedto be used like this; even though when you really read the datasheet and do the math, it says the part is non-functional and may blow up!

author: peter.mitchell
author_rank: Super Contributor
timestamp: April 14, 2016, 01:12:25 pm
content: Quote from: Siwastaja on April 14, 2016, 07:52:37 amThat depends highly on the switching frequency, the size of the bootstrap capacitor and if there is any series resistor with the bootstrap diode/switch.