PCIE layout  - Page 1
Forum section: electronics / projects

author: nihial
author_rank: Regular Contributor
timestamp: September 25, 2018, 08:47:23 pm
content: Hi,I'm reading some stuff on pcie layout and I have some points where I'm not sure what is best or what to do at all.1) First of all, the characteristic impedance, depending on the design guide, can vary between 100 and 85 ohms, I guess the important part is to chose one and stick to it?2) Also, some guides mentions the single ended impedance, let's say 50Ohms, does that mean I need to ask the manufacturer to give me a geometry where the differential impendance is for example 85 and where the single ended impedance would be 50 Ohms ?3) Does the clock impedance needs to be the same as the TX RX impedance or is the clock always at 100Ohms ?4) When changing layers do you care about the via separation ? Do you include one GND via per signal via symetrically placed ? One GND via for both ? Other ?5) The guides I read state that I need to length match segment by segment, and that the total mismatch should be below 5mils. Is this rule valid for the segment matching ? It's rather small, it means that after EACH turn I need to length match the signals this looks a bit agressive. I saw designs where they made curved turns instead of 45° bend and only bothered to match where serious mismatch were introduced (U turn for example) and to include in that the other mismatchs. Is there like some kind of rule regarding this ? I'm afraid that I'll do more harm matching the length to much because each time I need to break the impedance. This question is not only for pcie but for all high speed serial links like 10G. Any advice from more experience hardware developers would be appreciated.Best regards,nihial

author: a59d1
author_rank: Regular Contributor
timestamp: September 26, 2018, 06:56:36 am
content: https://www.ewh.ieee.org/r5/denver/rockymountainemc/archive/2000/diffimp.pdf1) The allowed variance between 100 and 85 ohms is mostly just a matter of tolerance (correct me if I'm wrong). Usually you can get away with +/-10% values for impedance since receivers and transmitters are designed to work with imperfect boards and low tolerance parts.2) Single ended 50 ohms impedance is usually equivalent to 100 ohms differential impedance. A trace of a certain thickness on a certain PCB will have Z=50 ohms, and two traces of similar size will have Z=100 ohms differential impedance. Use a PCB impedance calculator like the one bundled with KiCAD or something similar to get a feel for this, or look up the proper way to calculate transmission line impedance.3) Clock impedance should be the same as signal impedance since that's the way most chips are designed to work. If it's a differential clock, 100 ohms differential impedance; if it's single-ended, 50 ohms. Same goes for arbitrary signals. 50/100 ohms was settled on for some historic reasons and has stuck around because it isn't too hard to work with.4) This is usually up to the designer. You should use the same number of vias for different tracks so that the impedance mismatch is at least consistent between the different signals, but use as few as possible. Some people use guard tracks to separate signals, but this can be unnecessary.5) The length matching is the length of the entire signal, from output pin to input pin and vice versa. To a good approximation, the signal going down the wire is just a wave - it travels at a certain constant speed. With tools like KiCAD, you just draw all the traces at the same time, then use the length-matching tool (which preserves the trace's settings and impedance requirements fairly well) to adjust all the traces together in a semi-automated way.

author: nihial
author_rank: Regular Contributor
timestamp: September 27, 2018, 03:01:24 pm
content: Quote from: a59d1 on September 26, 2018, 06:56:36 amIt is equivalent when there is no coupling, I think the 85Ohm diff and 50Ohm single ended is a way to indicate the level of coupling between the N and P traces. But I'm not sure it's that, that's why I'm asking in case someone can confirm.Quote from: a59d1 on September 26, 2018, 06:56:36 amIt's possible but I'm not 100% sur of that, but that would be the most logical way (for me at least).Quote from: a59d1 on September 26, 2018, 06:56:36 amA lot of guides stated explicitely that length matching for pcie should be done segment by segment and not overall. The question is, how tight should it all the way down.