DSO analog frontend investigation - Building diy DSO! - Page 1
Forum section: electronics / projects

author: Yansi
author_rank: Super Contributor
timestamp: October 25, 2015, 01:10:53 am
content: Hello guys!I am just doing my research on analog frontends in DSOs. I'd like to better understand how they work. I have aleady seen some schematics, so far hand drawn only by enthusiasts who reverse engineerd some DSOs, but alwayas partialy, so some interesting parts of the circuits are missing. Take for example the Dave's Rigol DS1054 reversing. I'm quite interested in the detailed workings of the offset voltage shift circuitry. From what I have seen so far, I can only think of this scenario:The ADC is always zero-centered in the center of the screen. Any vertical shift of the trace using the "vertical knob" is done in the analog frontend. That way if you shift the trace for example -20V out of the screen and then there comes some >20V, you will be able to see a part of the waveform on the screen. That should also implicate the ADC remains in one or the other saturation, if the trace is outside of the display window.Am I right or are there some other tricks hidden? Is the ADC really saturated when the trace is out of the window? If somebody knows more precisely, how is this shifting done in the real deal?Thank you for explanation,Yan//EDIT: As I have already mentioned a few posts lower, my intention is to make a simple but usable and working diy DSO. I have almost no experience with designing DSO analog frontends, so I am trying to get down to the basics. Your help is welcome, if you like to support just anothe diy DSO.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 25, 2015, 01:33:32 am
content: That's right!

author: LaserSteve
author_rank: Super Contributor
timestamp: October 25, 2015, 01:39:25 am
content: Download or Buy Jim Williams book: The Art and Science of Analog Circuit Design (Abebooks if you want a physical copy)http://s1.downloadmienphi.net/file/downloadfile6/192/1383180.pdfSee chapter starting at page 65 authored by Steve Roach for older methods of "split" front end signal conditioning...Steve

author: Yansi
author_rank: Super Contributor
timestamp: October 25, 2015, 01:52:31 am
content: Thank you for the positives, T3sl4co1lTo be honest, I'd like to make my own simple DSO. But I am quite fed up with those "standard" diy constructions, which mostly have absolute useless garbagge frontends, based mostly on some stuff thrown together. I'd also like to publish mine after and make some competition. (I have set the goal for 100Msps 20MHz bandwidth so far).But don't take it to seriously... I have actually quite a few projects running now, so this one... well... Maybe after x-mass. Now I am only making research and gathering info, if making a diy usable DSO is even remotely possible. I have already picked some components.(namely my favourite altera MAX2 CPLD, asynchronous static RAM from ISSI, AD9283 as the ADC and AD8330 for the AFE. But those are subject to change ofcourse.) Will be built around some available ARM kit - so a standalone application, PC independent. So much for the future plan.LaserSteve, thank you for the tip. Will definitely read more in this book.Now I am going to put some thought into the offset shifting circuitry. Let's see what we will find in the book.YanEDIT: I didn't know that Jim Williams was designing DSO frontends :-O

author: LaserSteve
author_rank: Super Contributor
timestamp: October 25, 2015, 02:03:50 am
content: Read the reference papers listed in the back of the chapter, too...Steve

author: Yansi
author_rank: Super Contributor
timestamp: October 25, 2015, 03:00:36 pm
content: I couldn't resist so I tried to analyze some given schematic and I am trying to reproduce some functionality myself now, regardless that the project is planned for the next your. I am just too much curious about it.Let's take for example the circuit which Dave Jones has reverse engineered from Rigol DS1054Z. For sure it is the same "dual path" topology as described by Jim Williams in his book.I am stuck with these two things now, which I can't figure out:a) How to choose the bias current for the JFETb) What is the voltage range of the follower that it has to work atI have put the schematic part in to the attachments.Let me try to make some analysis first on both things and please tell me if I am wrong. The purpose of this analysis is to gether info how to make my own.First, I'd like to put some thought in the analysis of the Dave's schematic from the Rigol DSO. I have marked red in the image the static values in the circuit. A good guess is that the supply voltage is +-5 volts. The bias current of the JFET is therefore about 26mA and the bias of the next stage is 44mA. (Quite a lot, isn't it?) I don't know if these currents are reasonable, my experience is telling me that I'd expect both current to be half of what I see here. Maybe the negative supply voltage is not -5V but lower. What do you think?That forwards me to the question A. How to choose the bias for the JFET? I have breadboarded part of the circuit already. I have used a BF245B jfet and 2SC945 NPN for the current sink. My best uneducated thought was, that the sink current must belowerthan the minimum drain current at zero Vgs voltage. Why? Because if the sink would sink more, forward conductance in the gate junction would happen, because the maximum current at Vgs=0 is pretty defined. You cannot tell the jfet to do more, without actually pumping positive current into the gate. Am i right?So if my BF245B has the Id current in the range of 6 to 15mA, i shall design the current sink with for example 3mA, not to allow forward conductance and loss of the high-Z follower functionality.But I think I must have overlooked something, doesn't make much sense. Can you please explain me where I did wrong?The nex B question of the voltage range I will save for later, let's take only small steps.Thank you for help.Yan//EDIT: My friend has confirmed that I should be right, the bias must be sure lower than the Vgs=0V drain current of the FET. So let's make the analysis backward. From the J309 datasheet can be seen, that Id 10mA is the point of interest, most probably. That means 1.65V drop on the emitter resistor of the current sink, so about 2.25V is the negative rail? Possibly?... hmm.. that is a strange voltage level, but who knows.//EDIT2: By analyzing the more accurate schematic from Rigol DS1052 whre the same J309 fet is used, i came to the conclusion that there is 10mA drain current used. So i have to be right with this one... perhaps?In every way the breadboarded circuit with BF245B works as expected, by using assumptions stated here in this thread. The last plan for this evening is to upgrade the follower and make a prototype of the two-path follower. Just as a proof of concept. Maybe later I will try to measer the performance of the circuit, if it can fulfill my 20MHz requirement for my future planned project.

author: Yansi
author_rank: Super Contributor
timestamp: October 25, 2015, 10:25:07 pm
content: OK, so nobody wants me to build just another diy DSO?I know, my topis are always somewhat boring. So let me carry on my little dialogue with myself:Today afternoon, I have "breadboarded" the impedance converter. Based on the well known Jim's dual-path topology, I hope it will work good enough so I will be able to use it in my diy DSO. Tomorrow (I know, time is very relative here on the forum) I will take the bodgecircuit to work to measure its performance. Unfortunately, I have no such signal gen at home capable of doing up to 20MHz.So here is the hacked-together circuit. Don't laugh, it was the fastet and best way to do it. Ofcourse the final will be in SMT stuff, better parts and probably four layer pcb.The actual schematic can be seen in the photo. Nothing much to it. The input DC impedance is 1Meg, the AC impedance is who knows, but decreasing with rising input frequency. Just parasitic capacitances of the diodes, fet and so. Nothing much can be done with them.The input is clamped to the rails using 4148 diodes (were on hand), later will be used BAV99 or BAV199.The jfet is BF245B, as I couldn't find any better in my shop. Somewhere I have a few J310s, but somewhere... dunno where. The J309/310 should be better, because of higher drain current, greater transconductance so lower output impedance. The BF245 should do about 270ohm (please check me if you can) output at 5mA drain current. The J309 should do about 80 ohm if I remember the result right. I have also choosed to omit the second NPN emitter folower stage. I think this should be enough for 20MHz, but maybe I am wrong. I haven't considered the input impedance of the variable gain amplifier yet. Maybe it will turn out the output impedance needed should be much lower than that.This configuration of the jfet follower is capable of doin up to 7Vpp signal, without obvious distortion occuring on the output. So I think it is good enough for 1 or 2 Vpp signals.The OPamp used in the birdsnest circuit is TL062, resistor around standard 1% metalized. Much thought haven't been put into this part of circuit, but it seems it is working just fine. One thing I haven't figured out yet is how to calculate the crossover frequency where the operation of the JFET follower starts to dominate. Sure, the 4n7 capacitor is involved, but the combination of resistors remain mystery. I will think about that.The other half of the 062 does a follower and is sourcing the end of the 180k resistor in the schematic near the "offset" input. The shifting voltage is provided from a 22k trimpot.The 4M7 resistor for gate bias was copied from the Rigols. I dunno why 4M7, I'd use 10M more likely, just so it will affect the overall input impedance least possible. (actually, there are two 3M3 resistor in series at the moment as I couldn't find anything higher than 3M3)I hope the measurments tomorrow will convince me enough that the DSO build is possible.

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 12:58:55 am
content: Okay sorry, next part of my own boring dialogue with myself... or maybe I should stop posting? Mmmm.Made a few test a while ago. I have connected a 4,194304MHz () crystal osc on the input of my circuit. And then pure wow followed. Look at the output waveform I have captured. Yellow is input, cyan is output of the follower. I haven't expected that. Seems like the bandwidth of that must be way higher than only 20M (which was my intention, to buildat least20M capable frontend), otherwise the squarewave wouldn't look so nice.The measured tranfer ratio (at that frequency) was somewhere near 0,91-0,95. My scope is pretty shitty, no means of getting the value more accurate. The amplitude loss is shown in the scope image below.Then I have measured the output impedance of this stage (at the 4,2MHz point). I have calculated, that the BF245B at 5mA Id should have an output transconductance of about 3,75mS so that equals about 270ohm output impedance. The measurement (using the loading method up to halving the output voltage) shown that the output impedance is somwhere about 250ohm. Thats fair enough, compared to my cruel calculation. But not good enough to drive the VGA directly. So another stage will have to be added.I have checked in the datasheet, that the VGA I'd like to use has 1k input impedance. So 250ohm is no good, we need less. I will add a second follower stage with a BJT, as used commonly in other DSO frontends. But calculating output impedance of a BJT follower is nowhere near easy, the only thing I can do is estimate the Rout by 0,026/Ie+Rs/beta. But obtaining beta for AC signals can be tricky sometimes too. So the best option is just to build the circuit, select reasonable bias current and then measure the performance. Output impedance lower than 100ohm should do i think. But I am afraid that adding a next stage with BJT will for sure degrade the transfer coeficient of the follower further. Maybe I will make some form of bootstrapping to compensate. Interesting is, that the followers in the Rigol DSOs are not bootstrapped. That makes a bit of dip in transfer with rising input frequency above NF range. Strange. How do they compensate this? Or even do they at all?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 26, 2015, 01:14:52 am
content: FYI, use a 4.7M bias resistor and instead of the 1M at the input, use a R + (R || C) with the same time constant and R(hf/lf) ratio to compensate it.Kind of a crappy description, but it'll be obvious if you check out the equivalent circuit (input to 1M 'terminator' resistor, with Rbias + Ccoupling in parallel with it), and see how the resistance needs to be equal at all frequencies.Tim

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 01:20:03 am
content: Fuu. I can't get it. Can you please describe it more in detail or draw an image? It's well past midnight here, my brain is maybe not at full power now...Thanx

author: Bud
author_rank: Super Contributor
timestamp: October 26, 2015, 01:41:16 am
content: Quote from: Yansi on October 26, 2015, 12:58:55 amDo not look for ingenious solutions in rigol scopes. I have dissected a DS2072a and its frontend is simply collection of already known circuit snippets slapped together.

author: Marco
author_rank: Super Contributor
timestamp: October 26, 2015, 02:02:15 am
content: Probably better to copyOwon's front end. It lacks the old timey charm of JFET/MOSFET front ends, but a fast FET opamp makes life easier for the cost of a couple of bucks.

author: vk6zgo
author_rank: Super Contributor
timestamp: October 26, 2015, 02:08:41 am
content: Quote from: Bud on October 26, 2015, 01:41:16 amAs is most Electronic equipment!It makes me laugh when manufacturers try to claim "intellectual property" whilst using circuit configurations which have been around since the '60s in Solid State,& the '30s in vacuum tube form!

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 02:30:42 am
content: Quote from: Marco on October 26, 2015, 02:02:15 amThis is exactly what I do not want to do. Every idiot can design such frontend, using expensive ultrahyperfast OPamps and other stuff like that. Maybe at my 20MHz goal it is quite easy to make it from fast opamps, my component drawers have some pretty ones too, but their price is not so pretty and I am not trying to design an overpriced toy. The internet is flooded with diy scopes with garbagge frontends made from such "opamp stuff". Haven't seen a single praiseworthy one. (I am not trying to offend their designers, but I have a little bit different point of view than most of today's arduino hack-slappers). If there is some skill I can learn in electronics, I like to learn it. The "opamp solution" is only about selecting good enough opamp, almost none skill for that required.The "old" concept as you say is not so much complicated, consists of jellybean parts only and has similar or better performance, if done right. Try to count the components, their price and see, how many channels you can build using jellybean parts for a price of single hyperfastultrasuper opamp. Personally I don't see anything bad or disaddvantageous making frontends "the old way". Making cheap things with jellybean parts and good prformance is simply badassBut that was a little diversion from the original topic. Let's keep being nice, don't offend one topology over other and please help me to solve my frontend, if you like to do so.//EDIT: The Owon's: 16 bucks in low quantities for the first two ICs together, wondering the price of the third one in the line.

author: Marco
author_rank: Super Contributor
timestamp: October 26, 2015, 03:16:49 am
content: Well quite separate from physical opamps, multistage amplification + feedback has some inherent advantages. At high speed it gets hard to replicate that with discretes, easy to get an oscillator instead.That said, for 20 MHz what about the classic "High Impedance Low Capacitance Wideband Buffer" fromAN-32? With a cascode, since bootstrapping isn't really possible. If you want more current through the JFET you can either add a current source in parallel to the drain resistor or a zener on the PNP emitter, in theory you could decrease R1 as well but you don't really want to reduce the amplification of the JFET stage.

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 03:37:26 am
content: What's the advantage of this circuit? Some bootstrapped localfeedbackthingy. This is exactly what will likely oscillate, instead of basic follower, which as I know should be stable enough on its own.I appreciate your help, but this help is really not helping, as: The topology was already given above and no 12V supply available. Only +-5V will be. And after a more thorough look, your circuit seems quite odd. The 10mA sink in parallel with 1k doesn't make sense, so doesn't the value of R1. If you want to bias the JFET with 10mA, this won't work at all, the current will find the path through Q3 every time the Ic(Q1, Q2) will be grater than 0,6/R1.Yes, I can add another current source, another that or that and than it simply stop working. Useless circuit. I think you can't simply triumph the four-transistor dual stage follower. It is a well proven topology. Not something I am pulling out of my butt.I'd rather stick with already proven by years toplogies, try not to make up some other feedbacky unstable things. If you want to test/use your circuit, please do. But I will stick with Jim's topology. It is proven and working. Just need a little help designing the correct values around.

author: analogNewbie
author_rank: Regular Contributor
timestamp: October 26, 2015, 03:39:43 am
content: You can also get some idea from frequency counter front end.http://cp.literature.agilent.com/litweb/pdf/5989-6308EN.pdfhttp://assets.fluke.com/manuals/6690____smeng0000.pdfThe high frequency part and Low frequency/DC part go to different path.

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 03:51:05 am
content: I don't get the first link - no circuit related found.The other link is better. There is a second type of topology, also described by Jim Williams, followed by a diamond buffer or what name that circuit has.But please stop suggesting alternative topologies. I have already choosen one and trying to make it work. Only if it fails, then I will search for alternatives. So far it works well, I don't see any needs for a change.I hope T3sl4co1l will specify his modification more in detail, as I only partially understand his suggestion.

author: Marco
author_rank: Super Contributor
timestamp: October 26, 2015, 03:55:24 am
content: Quote from: Yansi on October 26, 2015, 03:37:26 amHigh open loop gain, so closed loop gain sticks closer to the 1x.QuoteIt's stable in the sense of not oscillating, but as you noted it's amplification is rather device and temperature dependent when loaded. The emitter follower is a little better in that regard, so putting that behind the JFET follower and unloading it in the process helps a lot too. Not as much though.QuoteWant to keep all the devices conducting at all time, not at too low a current either because it negatively affects their speed.QuoteI have a bad habit of editing my posts, as I edited this is actually a variation on a circuit from AN-32. Positively ancient, it just adds a cascode since you can't bootstrap it any more.

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 04:23:56 am
content: How much gain that feedbacky thing you think will have at 20MHz? It will be glad it will have any. I doubt that circuit will do anywhere near fast as the simple follower. Therefore is a step backwards even considering it.It doesn't matter gain of "my" topology isn't perfect 1.000000. I need it to be only as constant as possible in the whole frequency range.Update: I have added tho more C945s to my circuit to lower the output impedance. Some trouble is showing, the second stage not working. Works more like attenuator, than follower. Dunno why yet, maybe a defective transistor. The first stage is nicely copying the input voltage, the second stage is visibly distorting, amplitude on emitter is half of what is on the base (source of jfet). Strange, don't understand that. Will change the trannies.quick update2: F*****CK. Seems a chinese resistor at fault. Should be 130ohm, measures 98,1k. WTF!I'd rather go asleep (past 5AM here) or I will beat the shit out of the resistor.

author: AF6LJ
author_rank: Unknown
timestamp: October 26, 2015, 04:37:05 am
content: Along for the ride guys, this looks like a good thread.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 26, 2015, 04:39:22 am
content: Quote from: Yansi on October 26, 2015, 01:20:03 amSure:(The source might not be an ideal Thevenin 1M source, in fact, for scopes it basicallyneveris. That's more just for representation. You know it's matched, in terms of a Thevenin source, when the input voltage ishalfthe open-circuit source voltage.)Suppose R2 goes straight to ground, instead of with R4 and C2 in there. If it's 1Meg, everything's fine at DC, but at higher frequencies, C1 acts like a short, and R3 gets connected in parallel with the input. Therefore, R2 should be slightly larger, so that R2 || R3 = 1Meg. Then the probe compensation will stay flat. But if we make R2 larger, it won't be right at DC.At low frequencies, R2 + R4 are in series, so, er, that obviously isn't the right network, as drawn, because the R2 + R4 || C2 network can't possibly have a higher impedance at higher frequencies as needed. What we actually need is an inductor, in place of C2.Which really sucks (the value would be somewhere around 100H!), but, you could simulate it with an op-amp. Actually, Might even be able to get it for free with the bias amp.So.. I'm kind of misleading with my hastily drawn diagram here, but perhaps you get a feel for the kind of thinking around it. If you can make the impedance higher than it needs to be, you can trim it down by connecting RLC networks in parallel.If the impedance has to go higher, you don't have much choice but to add elements in series with the source, which stinks for a couple of reasons (those components have to be streamlined for RF performance; they act as dividers to the stage gain, so you need the inverse components after the buffer to correct for them in the first place!, etc.).Sometimes, though, that's better -- as an aside, you can build a high voltage probe by making a large R || C divider chain. The C's are necessary to compensate for parasitic capacitance on the resistors, so the waveform remains straight. The divider might only be 1pF at the probe end, but a 1:1000 divider ratio means you need 1000pF at the bottom of the divider. You're not going to find a trimmer capacitor that size! So it can better to leave the capacitors fixed -- which means your AC gain is some dumb random value due to poor tolerances. So you trim that out, but now your DC gain is the inverse of the AC error. Ah, but trimpots are easy to come by, so you can adjust that easily. Trimming this type of network is the inverse of adjusting a conventional probe's gain and compensation, but works out precisely as well.So if you get into a situation where you need to sacrifice one thing (like flatness of gain, in exchange for flatness of input resistance), it can still be reasonable (if annoying) to compensate it out later.Tim

author: Marco
author_rank: Super Contributor
timestamp: October 26, 2015, 04:42:26 am
content: Quote from: Yansi on October 26, 2015, 04:23:56 amMinus the cascode and with say a BF862 and a BFT92 I think it would have enough for100s of MHz. Cascode slows it down a bit, especially with the anemic biasing I gave it, although an extra current source could fix that.PS. if you don't care about the noise you can replace the JFET and cascode transistor by a single BF908 as well.

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 05:02:57 am
content: Thank you very much T3sl4co1l for the detailed explanation! I will read carefully after I get some sleep.Marco: Okay, might do then. But my experience with highspeed discrete closedloop things is unfortunately quite poor.Thats the part of a reason why I'd like to leave experimenting like this and rather stick with the more simple and proven circuits.

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 01:45:45 pm
content: So a bit of sleep taken... a little update:Replaced the f***d up resistor, now works muuuuch better. BUT... but the output is ringing, quite a lot. Interesting discovery is, when I connect the second scope probe between the two stages (base/source junction), the ringing disappears completely and the singnal is smooth as a baby's butt.I am not sure what change the scope probe did to the circuit, but most probably the circuit liked the input capacitance of the probe. (Because loading the source/base junction with a ~1M resistor does really nothing, so it have to be the capacitance).So let's try some caps: 4p7. Better. 6p8 definitely better. Let's try 10 puff and solder it with short leads directly where it needs to be. Or wait a moment. What's the input pF of the probes? Jeeeeezus christ! 18 puF on 10x setting. That would explain a lot. I have thought the capacitance to be an half an order smaller, like 5 puff, not almost 20Stop soldering caps wildly, let's put some thought into it: We know, that the first stage should have output Z of about 270ohm calculated, 250 measured. I need the circuit to pass frequencies up to 20M, so we can calculate precise capacitance. (of course we are neglecting a lot of things like input capacitance of the NPN follower stage, its input resistance,...) but at least we can make a good estimation. By using C= 1/2piRf I get about 30 puff. So now we estimated the max load value for the first stage, so let's try 22 puff, almost the same (slightly more) as my chinese probes from the Hantek beast.Now the output is clean as a whistle, as it should be. If I try loading the output with 1k (simulating the input Z of the VGA which will succeed), the circuit shows no interest that I loaded it with 1k. That's the way I like it!Do you think guys that stabilizing the circuit by placing a smal C load in between the stages is OK? Or is it pointing towards some other problem I have missed? Or do you think that on a well layed out pcb this ringing should not occur? Maybe I should try putting the circuit on a small pcb using 0603 components an try it there. (double sided home etched, bottom side solid ground)I will also visit our local component store today (as you might call them "ratshack" or whatever) and try to buy some better jfet stuff.Now I am proceeding to move myself to work, where I will be able to sweep out the whole transfer characteristic, I hope.T3sl4co1l: Sorry that I haven't answered yet, a complex post requires a complex answer. I appreciate your help here!//EDIT: The upper screenshot is the pure output, the second one shows again the output of the second stage, but also with loading the first stage with second probe. By using the 22puff cap in between the stages does produce clean output, same as on the second image.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 26, 2015, 06:53:00 pm
content: Yes, little tweaks for bandwidth are good. The output resistance of a JFET source follower should be a reasonably modest resistance, but be careful that it isn't oscillating, especially if there's a low impedance on the drain (i.e., supply bypass) and a possible resonant tank on the gate (usually a "low" impedance, like a capacitance somewhere, that actually shorts the end of a resonant tank between gate capacitance and trace or lead inductance).Speaking of resistance vs. frequency -- a scope input should exhibit three characteristics: 1M at DC to ~kHz; capacitance from ~kHz to ~100MHz; and about 50 ohms resistance for >100MHz. It should not be a perfect parallel capacitance up there, because impedances less then 50 ohms cause unavoidable reflections. Typically, the first stage has a series input resistor to dampen the JFET (or other device) input capacitance and maintain that resistive characteristic.Tim

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 09:28:41 pm
content: Hiwe have some resultsI have tried to somewhat measure the amplitude transfer function. The measurement is a kind of dirty one, but gave some interesting results.1) -3dB BW is 26MHz. With the 22puff tweak between the stages. Interesting is if you take the output impedance of the source follower (250ohm mentioned earlier) and calculate the corner frequency with about 25 puff (3 puff is an educated guess for the parasitics), you will quite interestingly get close to that 26MHz I have measured.2) trasfer is flat as ... as a flat, only little negligible peaking near the end. But the DC to lowNF part is bad. There is about 1.1dB around the crossover point - which occurs about 50Hz I think. (but rather should at 220Hz? Maybe I am calculating the integrator's RC constant wrong). The most importatnt is that the DC gain is more than 1.. but I think thats because of the not so precise resistors I have used for the two dividers near the opamp, namely those 820k and 180k ones. The gain isn't exactly one.Any suggestions how to flatten the transfer in the DC to NF range, I mean around the crossover point?Yes T3sl4co1l, I know there should be a gate stabilisation resistor. But in this prototype I haven't used one. Thanks for the comment. Still working on the complex reply, now just wanted to share some results.Here are some prints from my old LeCroy thingy (but quite a beast, color CRT, 4ch 500MHz 2GSa and haz a printer built in!). I will probably measure the DC-NF characteristic once more a bit more accurately, but all the substantials can be seen though I think.

author: dom0
author_rank: Super Contributor
timestamp: October 26, 2015, 10:23:22 pm
content: QuoteForgot a 2*Pi?

author: Yansi
author_rank: Super Contributor
timestamp: October 26, 2015, 10:45:27 pm
content: As the cap is in between two resistive dividers, I have calculated impedances on both sides, added and then calculated the RC constant.R = (820k || 180k) + (8k2 || 1k8) = 149k1, C = 4n7f = 1 / 2piRC = 227HzMaybe a measurement error (wrong settings in the swept generator - it can happen...) or possibly calculating it wrong.

author: Yansi
author_rank: Super Contributor
timestamp: October 27, 2015, 11:28:19 pm
content: To T3sl4co1l: I am sorry for my dubness, but still I can't get with what will your input modification help. For DC the impedance is now not correct, as is 1200kohm. For HF-AC the impedance will still drop and the C2 will still only help to make the drop more steep. Or am I missing something? Also, I haven't seen actualy such capacitor on that place in any scope frontend schematics I have seen so far.Can you guys please also explain me how to estimate the crossover frequency from the component values? I mean the position of the "peak-and-dip" on the amplitude transfer characteristic, example of the typical characteristic was taken from the Jim Williams' book. I have measured almost the same, the crossover point is at about 50Hz if I measured correctly. (Will check more thoroughly again on Thursday).Also what is the reasonable maximum of acceptable flatness error for a half decent scope? Now I have about a dB error in the DC-NF, haven't measured the peaking at the end of the BW. 1dB is about 12%, I think that is not good but horrible or isn't it?Thanx,Yan

author: nuno
author_rank: Frequent Contributor
timestamp: October 28, 2015, 12:32:15 am
content: Some more resources:https://docs.google.com/document/d/1xqnG20M7uSh7b6l7MWh_v6OnK6OmlYJReyGQzc51Q54/edit?pli=1

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 28, 2015, 12:40:32 am
content: You've got a pole-zero cancellation at work here. If you looked at the "high pass" part in isolation, you'd see the gain rise (starting at the frequency where the peak starts rising), then eventually level off somewhere. Likewise, the "low pass" part causes the gain to drop (at the frequency where the peak, well, peaks), eventually leveling off somewhere.Suppose these two frequencies are unequal: then the highpass starts too soon, and there's a hump in the gain. Or if lowpass starts too soon, you get a dip.You shouldn't have both (a peak AND a dip), so the network is probably more complicated than this.It probably comes down to the compensation values around the bias op-amp. Usually an R+C from output to -in is a good approach, adjusting the values (trimming, even) to get the desired response.Tim

author: Yansi
author_rank: Super Contributor
timestamp: October 28, 2015, 01:13:15 am
content: Sorry. I don't understand poles and zeros. Some stuff from/around the Laplace Transform, thats the only thing I know about that. And never found any materials suitable for such dumbass as me, to study such important stuff.But sure, I will play more with the circuit on Thursday, try to make it behave more nice. The only problem here is my very limited access to such hightech equipment as HF generators, my home lab is only "LF equipped" so to speak, so no means for me to trim stuff over about 100kHz. No sig gen available. But will try hard to get acces to some.Shame, I know, but I have to live with it...nuno: Thanks for the materials to study, I have gone through some of the few first links, the Salewski DSO card is quite impresive, huh.//EDIT: AND btw, what is the acceptable flatness error? 1dB? 0.5dB? 0.1dB? So I can have some exact amount of how far the circuit has to be tweaked.

author: nuno
author_rank: Frequent Contributor
timestamp: October 28, 2015, 01:37:05 am
content: The tek doc on the attenuator is quite enlightening.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 28, 2015, 02:44:28 am
content: Ok, a pole in a transfer function (i.e., output voltage / input voltage, gain) has a lowpass effect, and a zero has a highpass effect. This is what you get when you do the circuit analysis, which is exactly the same as with resistors at DC, but where you leave R as R, replace C with Zc = -j/(2*pi*F*C), and L with ZL = j*2*pi*F*L. (j^2 == -1, the imaginary unit.) Or to save the mess, use w (lowercase omega) == 2*pi*F, or s == j*w.When it's in terms of s, it's the Laplace domain; when it's F or w (and complex), it's Fourier domain.If you further crank the numbers, to solve for the frequency response (gain as a function of freq), and organize it as a polynomial in frequency (powers of F or w or s, times constants), then, that's not real useful, but polynomials can be factored, and those factors are the poles (denominator) or zeroes (numerator). The factoring is easy for second order (up to F^2), much harder for 3-5, and insolvable generally (can only be numerically computed) for >5 order.So it's a math thing at the base, but not terrifically advanced, just algebra level. On the Bode plot, a pole or zero is a geometric feature, where the gain changes in slope, up (zero) or down (pole) at the characteristic frequency.There are is only one property of a pole or zero: the characteristic frequency. (If it's a complex pole pair, then the Q factor (how much ringing, or peaking at that frequency) is also a property of the pair.)So if you don't know very much about circuit analysis, I'd recommend, give it a try! It's good algebra practice, and after much work, you can demonstrate exactly which ratios matter (this component versus that, etc.).Tim

author: Yansi
author_rank: Super Contributor
timestamp: October 28, 2015, 10:20:00 pm
content: I haven't said I do know nothing about circuit analysis (I have only said that not much...). I can make a transfer function in complex (j*omega) of almost any RLC circuit, maybe rewrite some easy ones to the laplace form... But nothing about poles and zeros. They didnt give a shit they even exist at the campus I have studied, I am power/energo stuff, smallsignal stuff is only my hobby and am eager to learn. Our circuit classes were really boring basic stuff, I think we have ended somwhere about harmonic analysis of basic RLC circuits (which is needed for the power industry), but no word was given about anything else.But thanks for the little insight, if you know about any good materials to study this stuff from you can recommend, please suggest one. I will try to fill my gaps in knowledge.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 29, 2015, 01:13:06 am
content: Ah, well there you go, then. Take that equation, factor the top and bottom parts, and those factors are your zeroes/poles.Tim