Looking for 74ACT family alternative - lower prop delay - Page 1
Forum section: electronics / projects

author: wb0gaz
author_rank: Frequent Contributor
timestamp: November 12, 2021, 06:12:28 pm
content: I'm looking for an alternative to 74ACT (specifically 74ACT00) that has faster (less) propagation delay.The 74ACT00 is powered with 5V supply rail and Vih min (Voltage Input High minimum) spec as 2.0V. The 74ACT00 (the device for which I seek a faster alternative) it is being driven by a CMOS clock generator operating on 3.3V rail. The voltage step-up is what drove me to 74ACT family. The 74ACT in this case is driving a modestly capacitive load (~50 pF), and has Tplh typical of 6 nS and Tphl typical of 4.5 nS. I anticipate clock speed around 150 MHz (the application currently is at 50 MHz).I've looked at 74LVC and 74ALVC families but they show Vih min of 0.7 VCC which is out of spec range for my available signal source.Am I missing something among the family of logic devices?I'm happy to answer any clarifying questions and willing to consider other approaches.Thanks!Dave

author: axemaster
author_rank: Contributor
timestamp: November 12, 2021, 06:31:51 pm
content: I imagine a comparator or LVDS-to-CMOS converter would work here.Another option is using a straight-up voltage translator IC.But in general, your high-speed options will be limited if you operate with 5V logic, since that is basically legacy technology at this point.

author: Benta
author_rank: Super Contributor
timestamp: November 12, 2021, 08:16:20 pm
content: A PNP emitter follower might be an idea. It will not introduce significant delay, but will shift your signal by ~0.65...0.7 V.

author: dmendesf
author_rank: Frequent Contributor
timestamp: November 12, 2021, 11:27:43 pm
content: Potato Semiconductors:http://potatosemi.com/(They make chips...)

author: ejeffrey
author_rank: Super Contributor
timestamp: November 13, 2021, 12:19:33 am
content: Potato semiconductor is an entire company built around providing this sort of thing although their top-line speed rating is with a 2 pF load capacitance. The PO54G00A datasheet says 350 MHz operation frequency and 1.5 ns delay driving a 15 pF load. I'm not sure what it would do with 50 pF. Ganging multiple channels together might help drive that capacitance -- it might help on your 74ACT00 as well if it is partially limited by output drive.onsemi has the NC7SZ32 which claims 2.4 ns delay into 50 pF at 5V.There are PECL, CML, and LVDS drivers that can go faster than this but they have smaller voltage swings.

author: David Hess
author_rank: Super Contributor
timestamp: November 13, 2021, 12:38:41 am
content: Quote from: wb0gaz on November 12, 2021, 06:12:28 pmLVC is the next step up in speed from AC at 5 volts, but as you noticed, there is no TTL level compatible version of LVC.

author: magic
author_rank: Super Contributor
timestamp: November 13, 2021, 06:39:09 am
content: If it's just a 50~150MHz clock you could simply AC-couple it to a 5V CMOS input biased to 2.5V.2Vpp swing would suffice for that, except for the turn-on transient when some initial cycles may get lost before the DC level settles.Use Schmitt trigger input gates to prevent spurious switching when the clock is off.

author: wb0gaz
author_rank: Frequent Contributor
timestamp: November 13, 2021, 06:49:53 am
content: Thanks for the various suggestions ---The potato semi products look interesting, however, they don't appear to have a direct sales channel (it links to ebay listings which don't exist), however, there are some reps and distributors shown, so it's worth a look.As the source can drive 50 ohm load and the sink doesn't have a specific rise/fall time specification, I may end up needing to investigate solutions that aren't based on logic gates (MMIC amplifier, impedance transformation, etc.)Thanks for taking the time to post ideas - these have been very interesting and helpful, even if not yet leading to an obvious drop-in answer!Dave

author: CaptDon
author_rank: Super Contributor
timestamp: November 13, 2021, 01:52:43 pm
content: If all of your signals are referenced to the output of the buffer then gate propagation delay becomes a bit less critical as long as it can support your 150mhz into 50pf (which begins to look like a dead short at that frequency). To keep nice clean edges on the clock signal realistically you would be looking at a circuit that could push 300mhz into 50pf and that is a lot of current!! As others have mentioned, you may need a quad or hex buffer device with all sections in parallel to get the rise and fall times you need. One circuit I have used many times was an octal buffer with all sections in parallel to drive power transistors or power mosfets. With good bypassing and circuit layout I could get nearly .5 amps of drive current from a 25 cent part that was 'in-stock'.

author: wb0gaz
author_rank: Frequent Contributor
timestamp: November 13, 2021, 03:19:34 pm
content: Thanks, Captain - your points about driving such a capacitive load are well taken.Here's one possibility (still considering some random ideas) --- 74LVC1G04 running at ~4V rail (so it's 70% point would be within the 3.3V rail of the source) in turn driving 74LVC3G04 at 5V rail (so it's 70% point would be within the 4V rail of the intermediate buffer.) Could also take advantage of fan-out so the three gates of the 74LVC3G04 could be in parallel (the 74LVC1G04 would see about 7.5 pF + parasitic capacitance from the three gates of the 74LVC3G04, which might help mitigate the endpoint load. The rise/fall time spec for the 74LVC3G04 is 10 nS/V on a 5V rail (so that would need to be investigated with respect to what the three gates encounter from the preceding 74LVC1G04.) Introducing an extra supply rail is not the most convenient outcome but would be manageable.Thanks again for the discussion - good learning experience!

author: Terry Bites
author_rank: Super Contributor
timestamp: November 13, 2021, 04:09:49 pm
content: Its not the chips that count- its the fish.As a car hire place (not plaice) told me in Cyprus, the reason the instument cluster isnt working is "because some one forgot to reset the fish" True story and they were messing with me.Which probably why I failed to laugh.Is fish reset active high or low?

author: Terry Bites
author_rank: Super Contributor
timestamp: November 13, 2021, 04:20:39 pm
content: I am an authorised dealer for Tato. We have not been affected by chipaggedon, just a shortage of mankey chickens.We have Pringle 600GHz Fish Gut Putrid Arrays (a Norwegian luxury?) in stock now- even cheaper than chips!Lays are getting far and few between.

author: Terry Bites
author_rank: Super Contributor
timestamp: November 13, 2021, 06:12:52 pm
content: A typical pnp will run out of current gain well below 100MHz. That will push the output impedance up and that will interact with Cin. You'd have to push a lot of base current into overcome it. A 3906 has delay times in the 50nS range. A MMBTH81 might work. Not many fast pnps around. On the up side, you'll get a nice VHF oscillator going. A high speed comparator will do it, but they are expensive and the can be very fussy. Very very fussy.The LMH7220 seems to have escaped chipageddon and it works down to 2.7V. Delay in the 3ns region. A MAX40025 will draw you into pS. If you the HMC974 the universe might start running backwards leading to bitchiness from your neighbours or a masive cassino win.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 13, 2021, 06:40:08 pm
content: More info about your application would be helpful.Do you just need a clock or do you have arbitrary pulse trains with a minimum pulse width of 3 ns? Do you need a square(-ish) wave or would a sine wave be OK? Do you need an accurate DC level or could you AC couple it as long as you have enough peak-to-peak swing? Is the frequency fixed or variable?If a sine wave is OK, you could potentially use an inductor to make a resonant circuit and boost the voltage up.

author: wb0gaz
author_rank: Frequent Contributor
timestamp: November 13, 2021, 06:51:42 pm
content: Thanks, ejeffrey - those are very good questions (and Terry I assume your postings were in jest?)The source is a SI5351 clock generator (3.3V Vdd, 50-ohm capable output ~2-8 dBm somewhat configurable).The sink is an RF FET (not fully specified, BS170 is an example) gate.The connection from source to sink goes through what amounts to a bias tee - the path originating from the SI5351 is AC coupled; the path from a variable DC source (generated by a microcontroller/DAC) is DC coupled and RF choked so that the AC coupled signal is not affected (that is, the AC and DC components sum going into gate of the FET.)The DC bias component of the combined signal at the gate serves to bring less (DC bias voltage lower) or more (DC bias voltage higher) of the AC signal into the active region of the FET (poor wording!). The drain circuit looks like the same AC signal but with an amplitude that is controlled by the DC bias.There is no specific rise/fall time imposed (a pure sine wave would do.)The application is wide band (the path from the SI5351 may be set anywhere in the 1-150 MHz range), but does not hop around (it's a single-tone fixed frequency at any given point in time.)This is an extension to a working design (which experiences roll-off in the AC component as frequency goes up, due I think to propagation delay limitations in the 74ACT family part currently acting as a buffer after the SI5351 and before the "bias tee" connecting point.)Thanks again for the helpful questions!Dave

author: Terry Bites
author_rank: Super Contributor
timestamp: November 13, 2021, 07:25:50 pm
content: Partly. That thing in Cyprus is stone cold fact. I lied about having the FishPGAs ready to ship and Tato's lawyers are hot on my tail.Back to reality.Has anyone looked into long forgotten common base or common gate configurations: Voltage gain with zero current gain? This is what a level translator is essentially made of. RF FETish?Hmmm.