Learn asynchronous HDL from the get go: good idea or not? - Page 1
Forum section: electronics / general

author: technix
author_rank: Super Contributor
timestamp: June 21, 2017, 08:01:38 am
content: I am trying to learn HDL and there are two major flavors I have seen: synchronous and asynchronous. In synchronous HDL every module is pumped by a clock signal, and it seemed to me the vast majority of HDL is written this way. There is also asynchronous HDL where clock signals are not spread all across the chip. I know that for things like the 7400 series most things are asynchronous.Since I am learning de novo, is it worth it to focus my energy on the asynchronous side for now? What kind of challenge will I have to face?

author: nctnico
author_rank: Super Contributor
timestamp: June 21, 2017, 09:02:55 am
content: I'd focus on synchronous logic if you are going to target FPGAs. Using asynchronous logic means you'll also need to have a thourough understanding of how the underlying logic works. For ASIC I can imagine you may need some asynchronous parts but even then you'll likely have to deal with things like preventing oscillations/prolonged metastable states.

author: technix
author_rank: Super Contributor
timestamp: June 21, 2017, 09:13:17 am
content: Quote from: nctnico on June 21, 2017, 09:02:55 amYes I am targeting FPGAs - Altera Cyclone IV for now, may step up to Xilinx Zynq in the future.I was thinking that asynchronous logic may reduce the power output as a lot less transistors are being flipped at the system clock speed.

author: legacy
author_rank: Super Contributor
timestamp: June 21, 2017, 10:43:27 am
content: Quote from: technix on June 21, 2017, 09:13:17 amwith fpga, it's more a bullshit than a truth.

author: rstofer
author_rank: Super Contributor
timestamp: June 21, 2017, 02:06:34 pm
content: First, you need to separate the idea of combinatorial logic from 'asynchronous'. Combinatorial logic usually occurs between clock cycles. There will almost always be a ton of combinatorial logic. When you build a Finite State Machine, you will use a synchronous process to clock the 'nextstate' into 'currentstate' but the other process is ALL combinatorial. The outputs may be used as inputs to other synchronous processes and they will affect what happens at the next clock.Asynchronous logic comes up when you try to latch state information without a clock. RS flops come to mind. It simply isn't done! Timing analysis will croak and most toolchains will give at least a warning, if not an error. The number of flops required to retain whatever it is that needs retaining won't change when you code it as asynchronous.I had a friend try to duplicate a CPU design which used a LOT of asynchronous flops. There are several main clock cycles but a lot of the flops are asynchronous and edge triggered between clock cycles. He almost got there before he realized that he couldn't guarantee timing like they could in the old days. If you wanted things to slow down, you just added wire length. That was easy with backplane wiring.

author: NorthGuy
author_rank: Super Contributor
timestamp: June 21, 2017, 04:26:29 pm
content: If a flip-flop is clocked at the wrong time (when the D input is changing) it may go meta-stable. You need to ensure this doesn't happen.Synchronous RTL logic is the mechanism which can ensure this. The outputs of flip-flops go to so called combinatorial logic which perform logical operations (the exact operations are usually described with VHDL's "process" statement). The outputs of the combinatorial logic return back to the inputs of flip-flops. It takes tome for the combinatorial logic to settle. Once it settles, the inputs of the flip-flops become stable. At this point in time it is safe to clock the flip-flops.The timing goes like that:- All the flip-flops are clocked with the same clock- Once they're clocked, their outputs change- The change of the outputs causes the combinatorial logic to change- The combinatorial logic changes for some time (often in unpredictable way)- The combinatorial logic settles and produces desired outputs. Flip-flop inputs are now stable. It is safe now to clock them.- Next clock edge comes. All the flip-flops are clocked at the same time. Hence the logic is called "synchronous".The design tools make sure that the time necessary to settle the combinatorial logic is shorter than the period between clock edges. This limits how fast you can clock.Now imagine a single asynchronous signal (not clocked by the same clock) comes into the system. The transition of the asynchronous signal may come at any time. If it comes exactly at the wrong time then some of the flip-flops may become metastable. The metastable flip-flops will oscillate. This will produce asynchronous changes in combinatorial logic, which may cause other flip-flops to become metastable causing system instability.Not that you cannot deal with asynchronous signals, but it's better to avoid them if you can. At least, if you're just starting, better spend time getting familiar with the synchronous RTL logic.