LTSpice Error Message Help - Page 1
Forum section: electronics / projects

author: S185149
author_rank: Contributor
timestamp: September 29, 2017, 03:30:56 am
content: I downloaded the LM5050-1 High Side Or-ing FET controller PSPICE model from the TI web site and incorporated it into LTSpice XVII. I get the following two errors when I run the simulation.Error on line 1022 : .model u1:lm5050-1_s3 vswitch roff=1e6 ron=1 vh=10m vt=27m td=25n* Unrecognized parameter "td" -- ignoredError on line 1020 : .model u1:lm5050-1_s1 vswitch roff=1e6 ron=1 vh=0.16 vt=1.47 td=250n* Unrecognized parameter "td" -- ignoredI have not used PSPICE and new to LTSpice so I don't know the difference between the two and whether error is related to the differences. Any ideas why I got the error?Thanks,S18

author: Ian.M
author_rank: Super Contributor
timestamp: September 29, 2017, 03:49:20 am
content: The LTspice SW (Voltage controlled switch) model doesn't support a parameter called td. I guess the parameter is propagation delay between the switch control input changing and the switch state changing. If you want a faithful reproduction of the PSPICE model's behaviour, you will need to add two BV (behavioural voltage) sources to it with the voltage expression of the form:V=delay(V(in,ref),delay_time)to produce delayed control signals for the switches. Unfortunately, with only a netlist format model to work from , that's going to be a PITA if you are unfamiliar with 'raw' SPICE syntax.

author: S185149
author_rank: Contributor
timestamp: September 29, 2017, 04:32:58 am
content: Thanks. I guess that will have to be on a to do much later list.

author: rstofer
author_rank: Super Contributor
timestamp: September 29, 2017, 06:39:09 pm
content: Over on Yahoo Groups, there are two LTspice groups. One is just a repository for device models and other files. The second is a forum with some very knowledgeable people. Somebody may have already created a model for your device. Search both forums in the Files folder and ask if you don't find anything.

author: S185149
author_rank: Contributor
timestamp: September 30, 2017, 01:31:59 am
content: Wow! There is a group for just about everything. I will check it out. Thanks for the tip.

author: Ian.M
author_rank: Super Contributor
timestamp: September 30, 2017, 04:42:19 am
content: I've found a PSPICE manual and confirmed that 'td' is time delay: "TD shifts the switching transition to a later time"From the model file:QuoteWithout patching it to add the delays, under LTspice, both the Reverse Current Comparator and Off Comparator will operate immediately, producing unrealistic behaviour near the switching point. However the rest of the model should run OK, so you could simply remove the offending 'td' parameters for now.If you cant find a LTspice compatible model elsewhere, come back here with your .asc sim file and i'll see if I can hack something together.Edit: see below

author: Ian.M
author_rank: Super Contributor
timestamp: October 01, 2017, 06:02:55 am
content: Well I patched it with behavioural voltage sources to implement the delays, and it ran like an arthritic snail. I tried again with terminated lossless transmission lines (1G impedance for negligible loading on the original nodes controlling the switches) and got an order of magnitude speed improvement.Its still *SLOW* compared to the original model but should be usable. In the test jig,.option trtol 7turns down the accuracy to typical SPICE levels to speed it up.N.B. its *FUSSY* about the .tran max time step - without one it stalls when 'OFF' goes high.Use at your own risk. YMMV.

author: S185149
author_rank: Contributor
timestamp: October 01, 2017, 11:23:56 pm
content: Quote from: Ian.M on October 01, 2017, 06:02:55 amThanks. I looked up the behavioral voltage source to understand it better. I can see what that would be an easier way of implementing it. I'm still trying to understand the lossless transmission line. Is the concept to adjust the length of the transmission line to generate the required delay in the signal?

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: October 02, 2017, 03:00:19 am
content: Hi,Here is a quick model that shows a couple of ways of creating a delay in LTspice.One use the behavioral voltage source BV and the other use a transmission line.Note the transmission line has to be matched, to avoid reflections. You can change the electrical length by right clicking on the Td.. parameter. The amplitude is halved, because of the matching.The results are:Both take some time to execute.I have attached the model.Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: October 02, 2017, 03:29:42 am
content: Hi,There is a third way to implement a delay using the Digital components. Search for Special Functions in the help.You can used the Td parameter to set a delay. The delay must be shorter than the pulse width of the input pulse. You can create longer delays by cascading buffers like this:The results are:This executes very fast. The help file tell you how to set the logic levels etc.I have attached the LTspice model.Regards,Jay_Diddy_B

author: Ian.M
author_rank: Super Contributor
timestamp: October 02, 2017, 03:57:49 am
content: Actually the line does *NOT* have to be matched at both ends, but it does have to be terminated by a resistor of its characteristic impedance. Therefore an ideal transmission line can be used to implement a sim delay with no loss of amplitude. However if you need to do anything with the output other than sense its voltage, you need to buffer it, e.g with an E (Voltage Dependent Voltage) Source. If you load the unbuffered line with anything other than a termination resistor of its characteristic impedance, the amplitude will not be exact and some of the signal will be reflected. If the source end isn't matched, the return signal will be re-reflected, resulting in a train of unwanted signals at 3x, 5x, 7x ... (2N+1)x the desired delay.If a transmission line is properly terminated with a matched resistance at one end, the other end 'looks' (to the rest of the circuit) like a resistance of its characteristic impedance.The digital delay by buffer cannot be used for an analog signal. However if you are able to convert the signal to a digital (boolean) one before the delay (which can be done at the buffer input if you set the threshold and hysterisis suitably) and don't mind the delay vs pulse width constraint, its the best option for a fast simulation.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: October 02, 2017, 04:01:14 am
content: Quote from: Ian.M on October 02, 2017, 03:57:49 amYou are absolutely correct, my mistake.Jay_Diddy_B

author: S185149
author_rank: Contributor
timestamp: October 02, 2017, 07:23:06 am
content: Thanks for all the ideas. A lot for me to digest.S18