FPGA beginner: I2C slave - Page 1
Forum section: electronics / general

author: greenstrike
author_rank: Contributor
timestamp: December 04, 2024, 01:59:35 pm
content: Hi guys, I would like to start creating an I2C slave.Due I would make my design indipendent from FPGA brand/model, I would avoid to use FPGA embedded I2C hardware.As starting point can I use this design for my FPGA?Thanks.

author: rstofer
author_rank: Super Contributor
timestamp: December 04, 2024, 02:58:16 pm
content: Ordinarily, I would recommend starting at OpenCores.org but I can't get the web site working today. So, off to Google searching for 'open source fpga i2c core' and there are a lot of hits with many sharing code through github, etc.

author: Mahagam
author_rank: Regular Contributor
timestamp: December 04, 2024, 04:15:04 pm
content: You can start fromhttps://www.fpga4fun.com/I2C.html

author: Murphy86
author_rank: Newbie
timestamp: December 05, 2024, 06:20:23 pm
content: You don't really need 3 separate pins and mosfet. I have yet to see modern FPGA that won't support bidirectional IO (exclude some special pins).

author: sw_guy
author_rank: Regular Contributor
timestamp: December 05, 2024, 07:25:35 pm
content: Schmitt trigger is as important in the CLK pin as it is in the SLA pin. And do yourself a favor and use a FPGA that supports 3-state pin as already mentioned by Murphy86.I have implemented i2c slave using this code:https://github.com/jiacaiyuan/i2c_slave/blob/master/FPGA_i2c_slave/i2c_slave/i2c.vWith minor changes and digital filter (=an external clock to oversample SCL and SLA lines to make it glitch-tolerant).The example provided by Mahagam also works.Neither of the codes above need external clock which is easier to start with, but they are vulnerable for glitches. Also with schmitt trigger. For learning purposes this is fine and work well enough on the workbench. In case the application is closer to a production application, I recommend digital filtering.sw guy

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 05, 2024, 10:40:02 pm
content: Quote from: Murphy86 on December 05, 2024, 06:20:23 pmYes, all FPGAs have bidir IOs.

author: pcprogrammer
author_rank: Super Contributor
timestamp: December 06, 2024, 07:44:12 am
content: Quote from: SiliconWizard on December 05, 2024, 10:40:02 pmThe only issue might be that they are not open collector or drain, like real I2C devices use. Can cause problems in multi master/slave setups and bus contention.

author: greenstrike
author_rank: Contributor
timestamp: December 06, 2024, 10:06:21 am
content: Actually I am using MachXO2, if I correctly understand almost all inputs are Schmitt trigger.I'll read more carefully datasheet to check if there are open collector outputs.I focused on external mos due I am newbie about FPGAs and this is my first FPGA application where I am using low cost device, with this solution (I mean 2 pins for SDA and external Schmitt trigger for SCL) I am planning to make chip type indipendent solution.For the while I have no restrictions in terms of space, so external components for me are "free".

author: langwadt
author_rank: Super Contributor
timestamp: December 06, 2024, 10:18:45 am
content: Quote from: pcprogrammer on December 06, 2024, 07:44:12 amnot a problem, you just three-state the output unless you want to drive a lowassign dout = data ? 1'bz : 1'b0;

author: sw_guy
author_rank: Regular Contributor
timestamp: December 06, 2024, 01:12:24 pm
content: Quote from: greenstrike on December 06, 2024, 10:06:21 amI have used both of the examples above with MACHXO2.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 06, 2024, 08:38:52 pm
content: Quote from: langwadt on December 06, 2024, 10:18:45 amWell yes, that's how a bidir IO is handled. For an open drain behavior, you assign either Z or 0. End of the story. I'll be curious to hear about how a tri-state push-pull output used only either in Hi-Z or 0 level differs concretely from an open-drain.Of course, there's always the risk of a bug in your RTL that will inadvertently set it to 1 and wreak havoc, but for such a simple thing, you would have to do it on purpose really.

author: langwadt
author_rank: Super Contributor
timestamp: December 06, 2024, 11:29:05 pm
content: Quote from: SiliconWizard on December 06, 2024, 08:38:52 pmin many cases there is no difference, but a tri-stated push-pull output is often limited by the supply voltage, a real open drain usually isn't

author: laugensalm
author_rank: Regular Contributor
timestamp: December 07, 2024, 01:29:26 pm
content: The point is indeed that a real open drain would allow a 3.3V Vcc chip to speak to a 5V slave without internal diodes or drivers being fried, for instance.This is *not* the case with an emulated open-drain behaviour of a classic push/pull tristate I/O without the push. Current will then flow, possibly through internal clamping diodes and do funny things, depending on the I/O architecture.WRT schmitt triggers: You can safely forget about these with an up to date FPGA, as their standard I/O hysteresis and slew rate configuration options are way more than sufficient, and you typically do the debouncing yourself by sampling the SCL input with an internal clock of a multiple of the max. standard SCL frequency. Most FPGA types allow you to configure a slow slew rate/glitch filtering option in their I/O constraints files and tools mostly detect if you are emulating an open drain output.For standard applications, I'm clocking in 4 SCL bits and check for "1100" for a falling edge condition - good enough to detect glitches as well. Clock streching support may require another setup, but you don't seem to require that.