if U were a RISC assembly programmer which instructions would U want to have ? - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: February 29, 2016, 06:17:25 pm
content: including the most difficult to be implementedpre increment?post increment?stack? (push/pop)?about the first two instructions, ARM seems to have them, while m88K hasn'tand currently I have no idea about how to implement them in RISC termsthanks

author: free_electron
author_rank: Super Contributor
timestamp: February 29, 2016, 07:02:57 pm
content: bit count instructions. like 'how many bits in this byte are 1'i HATE RISC processors by the way. i want processors with massive single cycle instruction sets.When i was still mucking inside silicon i built hardware instruction set expanders for an ARM7 in an FPGA.i even had vector-like capabilities

author: legacy
author_rank: Super Contributor
timestamp: February 29, 2016, 07:08:12 pm
content: Quote from: free_electron on February 29, 2016, 07:02:57 pmto be used for bitmap purpose ?I can implement an instruction like it, can you suggest me an "opcode name" ?how should it be called ?Code:bitcnt rt, rs1(how many bits in register rs1 are "1"?, put the result int rt)I can also offer bit manipulationclearsetgettoggle

author: tesla500
author_rank: Regular Contributor
timestamp: February 29, 2016, 07:10:26 pm
content: Advanced bit manipulation instructions or engine.Simple things like reverse the order of all the bits, as well as more complex things like randomly programmable remapping of input to output bits. This is very slow to do in software in pretty much any CPU I can imagine:8-bit value:Input resultbit bit0 -> 51 -> 72 -> 23 -> 04 -> 65 -> 16 -> 47 -> 3

author: legacy
author_rank: Super Contributor
timestamp: February 29, 2016, 07:17:36 pm
content: Quote from: free_electron on February 29, 2016, 07:02:57 pmlike the tensor processor unit (TPU) by SGI?(kidding)do you think I'd better implement MAC (from DSP world)?saturated operation ALU engine?something to accelerate matrix computation?(exactly what?)

author: legacy
author_rank: Super Contributor
timestamp: February 29, 2016, 07:18:40 pm
content: about pre-increment and post-descrement (and stack operations)how are they implemented within the pipeline?in which stage?here I Arise-v2 (my soft core) currently has a strict RISC pipelinefetchdecoderegister_rd (2 registers)ALU/EA (multiply and division will take more cycles)load/store (dtack will take more cycles)register_wr(1 register), branchwhich looks like MIPS-approch, and MIPS hasn't them

author: helius
author_rank: Super Contributor
timestamp: February 29, 2016, 07:33:26 pm
content: Quote from: legacy on February 29, 2016, 07:08:12 pmThe SPARC v9 architecture defines an instructionpopc rs, rdmeaning "population count". It wasn't actually implemented until the UltraSPARC IV. This is also called the "Hamming weight" sohwtwould be a suitable mnemonic. Using a combination of bitwise operations and popc, you can implement the FF1 and FF0 operations (Find First 0 or Find First 1) which are used in hash algorithms.

author: ataradov
author_rank: Super Contributor
timestamp: February 29, 2016, 07:39:19 pm
content: I want all the instruction from a modern ARM architecture (let's say ARMv8). It has all you need and some more.But good look implementing all of that, it is a nightmare.

author: ataradov
author_rank: Super Contributor
timestamp: February 29, 2016, 07:41:22 pm
content: Quote from: legacy on February 29, 2016, 07:18:40 pmDecoder issues multiple simple instructions. Push/pop typically take more cycles because of this.

author: legacy
author_rank: Super Contributor
timestamp: February 29, 2016, 07:54:49 pm
content: Quote from: ataradov on February 29, 2016, 07:39:19 pmhence we need a compromise

author: legacy
author_rank: Super Contributor
timestamp: February 29, 2016, 07:56:45 pm
content: Quote from: helius on February 29, 2016, 07:33:26 pmalready implemented

author: ataradov
author_rank: Super Contributor
timestamp: February 29, 2016, 08:01:10 pm
content: Quote from: legacy on February 29, 2016, 07:54:49 pmNo, you need a compromise, I'm perfectly happy using ARM

author: blacksheeplogic
author_rank: Frequent Contributor
timestamp: February 29, 2016, 08:35:06 pm
content: Quote from: legacy on February 29, 2016, 06:17:25 pmWhen implemented for connivence you crack them within the dispatcher. However, that will require instruction group restrictions which makes optimization more difficult.As an example,stwu sp,-stksz(sp)Would crack to an add & store, but there would be a FIG restriction. The store has a register dependency which can't be mitigated.

author: HAL-42b
author_rank: Frequent Contributor
timestamp: February 29, 2016, 08:55:51 pm
content: Quote from: free_electron on February 29, 2016, 07:02:57 pmIt is a question of transistor count I suppose."Given a million transistors, is it better to have them arranged into a single CISC or several smaller RISCs?"

author: helius
author_rank: Super Contributor
timestamp: February 29, 2016, 09:10:58 pm
content: Transistor count is never the constraint, wiring and power dissipation are.

author: legacy
author_rank: Super Contributor
timestamp: February 29, 2016, 10:34:14 pm
content: Quote from: helius on February 29, 2016, 09:10:58 pmthose are called "micro architectural constraints", right?

author: legacy
author_rank: Super Contributor
timestamp: February 29, 2016, 11:01:16 pm
content: guys, and what about addressing modes ?e.g. should I include "scaled indexed addressing mode" ?(currently it takes +1 extra cycle)

author: ataradov
author_rank: Super Contributor
timestamp: February 29, 2016, 11:31:52 pm
content: Quote from: legacy on February 29, 2016, 11:01:16 pmSure, why not?The point is, the more you include, the more people will use. But if core is FPGA-only softcore, then it must be small in a first place.

author: rs20
author_rank: Super Contributor
timestamp: February 29, 2016, 11:36:16 pm
content: Quote from: free_electron on February 29, 2016, 07:02:57 pmIf you have 256 nibbles free (which I know is a big if), this is a simple array lookup. Not sure if it deserves its own instruction?

author: ataradov
author_rank: Super Contributor
timestamp: February 29, 2016, 11:39:30 pm
content: Quote from: rs20 on February 29, 2016, 11:36:16 pmEverything deserves its own instruction. Why not? Apart from being annoying for chip designers, there is really no downside. None of those small extensions significantly affect the price of the device.Array lookups need memory access, and that's expensive. Actually more expensive than to count with a simple stupid loop.

author: legacy
author_rank: Super Contributor
timestamp: March 01, 2016, 12:42:35 am
content: Quote from: ataradov on February 29, 2016, 11:31:52 pmyep, FPGA-only soft core

author: ataradov
author_rank: Super Contributor
timestamp: March 01, 2016, 12:43:00 am
content: For soft cores look at Microblaze or NIOS-II. They have all you really need and noting extra. Plus they support extensions. I know it is much more fun to design cores, of course.

author: retrolefty
author_rank: Super Contributor
timestamp: March 01, 2016, 01:02:43 am
content: Quote from: legacy on February 29, 2016, 07:54:49 pmSuch a compromise was available starting in the 70s with several of the computer companies, mini and mainframe types, that offered WCS, writable control store, that allowed end users to define and run their own machine instructions using the same microcode method that the standard supplied instructions used.https://en.wikipedia.org/wiki/Microcode

author: helius
author_rank: Super Contributor
timestamp: March 01, 2016, 01:08:34 am
content: Quote from: retrolefty on March 01, 2016, 01:02:43 amBecause the compilers of the day were getting a little too good at actually using the available instructions!

author: westfw
author_rank: Super Contributor
timestamp: March 01, 2016, 01:58:52 am
content: QuotePresumably, since an alu operation happens in a single clock cycle, and a memory access takes more than one clock, you just do the the increment/etc while you're waiting for the memory. That's where all those weird modes of RISC operands come from, right: "We have an ALU, a barrel shifter, and ...; they should all be able to do something each clock cycle!"The less standard thing that I wish were more common is probably bitfield instructions (combining barrel shift and AND.)I wonder how the PDP11 or PDP10 instruction sets (both of which are nominally regiser/memory architectures) would work i you RISCified them and made it so only the load/store operations could access memory?QuoteThe 32-bit ARM instructions, I hope? The Cortex (thumbX only) encodings have lost any elegance, and the CM0 is almost painful in is weird limitations...

author: free_electron
author_rank: Super Contributor
timestamp: March 01, 2016, 02:08:00 am
content: I want a cpu core that does not need a compiler. the instruction set should be so simple that you can basically translate a high level language instruction directly into cpu instructions.oh, and want a machine that calculates in BCD ( even for floating point )

author: HAL-42b
author_rank: Frequent Contributor
timestamp: March 01, 2016, 02:32:17 am
content: Quote from: free_electron on March 01, 2016, 02:08:00 amSo a FORTH processor like RTX2010?How about that newfangled number format the UNUM?

author: blacksheeplogic
author_rank: Frequent Contributor
timestamp: March 01, 2016, 02:42:35 am
content: Quote from: ataradov on February 29, 2016, 11:39:30 pmIt's not that simple, for a start bits for the op code is limited with fixed length instructions, and complexity will incur latency. There is also a higher test & validation cycle. In addition, space on the die is not unlimited.One technique done is to using extended mnemonics and have the assembler do the translation, or as I mentioned above another technique is the use of cracked instructions within the dispatcher.Example of extended mnemonics: slwi --> rlwinmAlso, if you need high complexity instructions you should consider using higher level languages. in general the use of hand assembly should be limited to very small sections of heavily optimized critical code. Beyond this, hand written assembler is far less efficient (time and performance) than code generated by a good architecture optimized compiler.Quote from: ataradov on February 29, 2016, 11:39:30 pmHand written assembly is normally very inefficient compared to that of a good optimizer, and programmers ego's often conclude theroretical timing based on how they would for example in this case walk an array.Optimization is a very very complex art and there's a lot of interaction that occurs between hardware development, and the compiler teams, dependencies are often avoided by the optimizers mitigating latency, in addition it's quite typical for the optimizers to unroll loops, provide hints to the hardware, organize the code/data alignment to exploit the hardware as well as the hardwares prediction algorithms.Quote from: ataradov on February 29, 2016, 11:39:30 pmHave you ever been involved with processor development or for that matter any chip design? That small extension/change is very expensive both in cost and time. It's also never right the first time and the more complex the chip the more 'it's not right'. It's not like software where a quick code change will fix it either.The die area is always known and there always disagreement over what will or will not be included (fit). It's a difficult conversation asking a team to give up "X" space so you can have space for "Y".On several occasions those great to have instructions which took months designing, implementing, & testing, were unused because the performance suffered frequently because of dependencies. Although the use of a instruction can be deprecated, once it's released the stark reality is that you have to continue some form of support on the platform (hardware or software emulation) for the 'feature' because a platform architect will never ever let you drop it completely.At the end of the day adding instructions provided little to no value in most cases and the time, cost, and space is better spent elsewhere.

author: ataradov
author_rank: Super Contributor
timestamp: March 01, 2016, 05:30:37 am
content: Quote from: westfw on March 01, 2016, 01:58:52 amWell, I actually think otherwise. Sure, anyone can design a beautiful ISA from scratch, but getting the most of the remaining available bits scattered around is an art form. Prioritizing instructions that will be useful, but still fit into awkwardly formatted 16 bit words requires some skill.I'm not saying that it is beautiful, but it is close to the best you can do given the limitations you can't remove.

author: ataradov
author_rank: Super Contributor
timestamp: March 01, 2016, 05:37:01 am
content: Quote from: blacksheeplogic on March 01, 2016, 02:42:35 amNone of this is my problem. As a consumer I will buy from whoever offers me the best deal. It is up to manufacturers to figure out how to make things cheap, fast and capableQuote from: blacksheeplogic on March 01, 2016, 02:42:35 amI know all of this. And I want my compiler to know that my underlying processor knows how to count bits on its own and use that capability. Even with high level languages, the more capable your ISA is, the faster your resulting code will be.Quote from: blacksheeplogic on March 01, 2016, 02:42:35 amI know all of this, but no matter what you do, memory access is more expensive than operations on registers.Quote from: blacksheeplogic on March 01, 2016, 02:42:35 amOnly application-specific stuff, noting general purpose. I understand what you are saying and my point is, I don't care.

author: ataradov
author_rank: Super Contributor
timestamp: March 01, 2016, 05:38:24 am
content: Quote from: blueskull on March 01, 2016, 05:27:47 amHardcore DSP will not even consider processors without all sort of bit-permutation instructions and MAC blocks.

author: Kalvin
author_rank: Super Contributor
timestamp: March 01, 2016, 05:40:29 am
content: MOVE is sufficient for a RISC.https://en.wikipedia.org/wiki/One_instruction_set_computerAny ISA with more than one instruction should be considered as CISC:

author: legacy
author_rank: Super Contributor
timestamp: March 01, 2016, 12:53:56 pm
content: Quote from: westfw on March 01, 2016, 01:58:52 amit seems I need an extra stage in order to write back the incremented/decremented registerfetchdecodereg_rd (read two registers)alu, EA (alu, and effective address evaluation)load/storereg_wr (write one register)reg_wr2 (write one register)<-------- here I can update

author: legacy
author_rank: Super Contributor
timestamp: March 01, 2016, 01:06:21 pm
content: Quote from: ataradov on March 01, 2016, 05:38:24 amI can add MAC, multiply (32bit, saturated) and accumulate (saturated), with 1-2 cycles of penalty

author: legacy
author_rank: Super Contributor
timestamp: March 01, 2016, 01:12:10 pm
content: Quote from: blueskull on March 01, 2016, 05:27:47 amexactly where (which algorithm) are they useful?

author: Kalvin
author_rank: Super Contributor
timestamp: March 01, 2016, 02:39:31 pm
content: Quote from: legacy on March 01, 2016, 01:06:21 pmThat is pretty bad when you think of it. The pipeline stalls will turn a 100 MIPS processor to a 50 MIPS processor or worse 33 MIPS processor when performing typical DSP algorithms.The situation is not that bad if you can perform MACs in a row without any penalty (like in FIR), but the pipeline stall occurs only after the last MAC when moving the result to the memory/register.

author: legacy
author_rank: Super Contributor
timestamp: March 01, 2016, 03:04:01 pm
content: Quote from: Kalvin on March 01, 2016, 02:39:31 pmit takes 2-3clockcycles, I was not talking about cpu cycles (which are composed by 5-6 clock cycles)ALU stage:clock1: busy (while performing the first MUL)clock2: busy (while completing the first MUL) -> pipeline stallclock3: busy (while performing the last add) -> pipeline stallresult ? 3 clock cycles instead of 1 (add/sub/bitwise take 1 clock), or 2 (mul/div/mod take 2 clocks)

author: free_electron
author_rank: Super Contributor
timestamp: March 01, 2016, 03:09:20 pm
content: other useful instructionsskip next if trueskip next if falsecompare equalcompare equal/largercompare equal/smallercompare differentwhere true and false are a single bit register in the cpu.for exampleif x>=9 then {goto here } else {goto there }cmple @x,9 (compare larger/equal). the result of this manipulates a dedicated flag in the cpuskifjmp herejmp theresubroutine call with automatic state storage. no need for costly data moves.- a cpu core with a number of internal register banks. so small subroutine calls do not need push/pop all the time simply spin the register file. cpu state is preserved by switching to a different bank.let's say a cpu is built having32 general purpose registers. these do not include cptr and dptr and core state and a bank registerthere would be 4x32 registers. the bank register selects which 32 are switched in.additional bonus : having additional banks with 16 or 8 registers. so the main loop can set up data in the lower 8 or 16 then call the subroutine who can access these 16 plus its own 16.- hardware driven stream functionsno more mucking with uart routines that gobble up time. the stream functions use dual ported memory. simple spit your data to be sent into ram. last byte operation (null character detector) triggers hardware uart to transmit.stdout 'hello world \0'this sends the string to the dpram. the moment the dpram detects the null character it fires off the hardware uart to process. the string length is determined by hardware ( you always start filling from a specific address. accessing that address resets bytecounter to zero. subsequent writes increment counter. null character triggers transmit and counter value tells you how many bytes.-stringcomparesstdincmp 'hello' : scans the dpram for pattern matching. cpu is halted until hardware is done and sets true/false flag

author: legacy
author_rank: Super Contributor
timestamp: March 01, 2016, 03:12:16 pm
content: Quote from: Kalvin on March 01, 2016, 02:39:31 pmmoving a local-registers context into register-file has no stall if there is no hazards within the data path, if there are then a few bubbles are needed in order to stall the pipeline, while moving things to memory, involves the load/store stage, which might have wait-state delay, which might stall the pipeline until the memory is readycurrently my Arise-v2 soft core performs the following:withsynchronous ram, load-s take 1 extra cycles, while store-s don't take extra cycleswithasynchronous ram, both load-s and store-s take 10-20 extra cycles (yes, it's very slow)

author: nctnico
author_rank: Super Contributor
timestamp: March 01, 2016, 03:54:32 pm
content: Quote from: legacy on February 29, 2016, 06:17:25 pmI think pre/post increment make things harder without gaining much in terms of speed. A data memory access can be offloaded to a small cache which stalls execution if it is still busy. This way the time you have to wait for the memory can be used for any instruction. You could implement stack push/pop with assembler macros.What would be useful instructions are: barrel shift, bit mask based set/clearAnd how about a seperate register bank and stack area for interrupts?

author: legacy
author_rank: Super Contributor
timestamp: March 01, 2016, 03:57:36 pm
content: Quote from: nctnico on March 01, 2016, 03:54:32 pmgoodQuote from: nctnico on March 01, 2016, 03:54:32 pmbitwise already implemented (set, clear, get, toggle)I can implement more functionsQuote from: nctnico on March 01, 2016, 03:54:32 pmalready implemented

author: Philfreeze
author_rank: Regular Contributor
timestamp: March 01, 2016, 04:05:08 pm
content: I want Trigonometry!

author: ataradov
author_rank: Super Contributor
timestamp: March 01, 2016, 04:42:57 pm
content: Quote from: legacy on March 01, 2016, 01:12:10 pmFFT, for example.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: March 01, 2016, 04:50:39 pm
content: Quote from: legacy on February 29, 2016, 07:08:12 pmPOPCNTThat's a pretty standard instruction, you find it on PC CPUs and particularly you'll find it in GPUs.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: March 01, 2016, 04:56:22 pm
content: Quote from: free_electron on March 01, 2016, 02:08:00 amAP, SP, DP instructions in IBM 360 Assembler perhaps; the thing of nightmares (and a university assignment I once had!)

author: legacy
author_rank: Super Contributor
timestamp: March 01, 2016, 05:09:37 pm
content: Quote from: Philfreeze on March 01, 2016, 04:05:08 pmehehe, It "might be" planned for Arise-v6 ( currently we are with v2)

author: Cerebus
author_rank: Super Contributor
timestamp: March 01, 2016, 05:39:04 pm
content: Quote from: legacy on February 29, 2016, 07:08:12 pmWhen a bit count instruction was added to the IBM 360 architecture it was informally known as "the NSA instruction", as that is who had requested its addition. "Why?", is left as a question for the student.

author: nctnico
author_rank: Super Contributor
timestamp: March 01, 2016, 05:55:28 pm
content: Another one pops in my mind: a test instruction. Normally you would substract 2 values to set the flags but this usually also destroys the contents of the register. The test instruction does set the flags but discards the result. This way you could have:test r1, 1bra z, r1_is1test r1, 2bra z, r1_is2

author: legacy
author_rank: Super Contributor
timestamp: March 02, 2016, 07:42:52 pm
content: I am going to improve the above designthank you guys for your tipsBP stands for "break point"WP stands for "watch point"EA stands for "effective address" (physical address)

author: nctnico
author_rank: Super Contributor
timestamp: March 02, 2016, 08:03:18 pm
content: I'd put the PC, SP and flags in the register map as well. That way things will be much more integrated and you can do fun stuff like setting the flags or reading them into any register. Perhaps put the registers in two (or more) parallel memories so you can read more than one register simultaneously to save clock cycles.

author: legacy
author_rank: Super Contributor
timestamp: March 02, 2016, 08:12:06 pm
content: Quote from: nctnico on March 02, 2016, 08:03:18 pmregister-fileno, I can't because I need (1) to write 2 register in the "write back" stage, so I need to have status, PC and SP implemented out of the register file, which makes possible to write just one register per clock cycle(1) it's required by features like "private registers during exception" and "private registers during function call": I can support both of them in hw, without pipeline stall, but I need to have PC and SP implemented externally, otherwise I will need +3 clock cycles of stall.Quote from: nctnico on March 02, 2016, 08:03:18 pmCurrently I can read 2 registers simultaneously, I can't write 2 registers simultaneously, just one per clock cycle

author: nctnico
author_rank: Super Contributor
timestamp: March 02, 2016, 09:18:06 pm
content: But you don't have to write the result, PC and flags all at once. The PC can be updated at the decoding stage, flags during fetch. SP is a general purpose register anyway if you make indexed addressing flexible.

author: legacy
author_rank: Super Contributor
timestamp: March 02, 2016, 10:34:01 pm
content: Quote from: nctnico on March 02, 2016, 09:18:06 pmno, it's updated in the write back stage due to the debug constraints

author: legacy
author_rank: Super Contributor
timestamp: March 02, 2016, 11:04:35 pm
content: Quote from: nctnico on March 02, 2016, 09:18:06 pmit's a special register, the only one to be passed in function call, as I am implementing a simplified form of "registers window" and each function has its private registers, the caller's SP needs to be passed (copied) into the called's SPthings like parameters are passed over the stack instead than over registers, it's my choicealso, in this way, SP is the only one that can have pre/post increment/decrement without stall penalties

author: sarepairman2
author_rank: Frequent Contributor
timestamp: March 03, 2016, 05:01:26 am
content: goto op amp

author: ale500
author_rank: Frequent Contributor
timestamp: March 03, 2016, 05:41:57 am
content: I like the following instruction (from PowerPC): isel rdest, ra, rb, rsel : if rsel is 0 then rdest gets the value of ra, if rsel is != 0 then rdest gets rb. (or was it with 3 arguments?).Can I ask what decode do ? what do you do there ? (I like designing soft-cores too).

author: Cerebus
author_rank: Super Contributor
timestamp: March 04, 2016, 12:29:49 am
content: Quote from: legacy on March 02, 2016, 08:12:06 pmYou can. Keep the PC, SP and flags in dedicated registers and just add decoding logic that muxes them into the data path instead of the register file when they're addressed as registers. It obviously means that the physical registers in the register file that sit at the same addresses never get actually used.You can see something similar in the design below that I cooked up for fun back in 2008 while learning Verilog. Note in this case that the PC is spread out along the pipeline registers but can be read as if it was a register, or written as if it's a register in the writeback phase.

author: CXm0dk
author_rank: Newbie
timestamp: March 04, 2016, 09:33:46 am
content: Quote from: legacy on February 29, 2016, 06:17:25 pmHello legacy,an idea discussed in this forum in the past, the looping instruction for increasing code density and a mean to reduce fixed loop overhead:Code:nloop iter,#of instruction0 <= iter < 16 iterate 3 to 18 times the following number of instructions0 <= #of instruction < 16 number of instructions to iterate between 1 through 16 (only 32bit instruction size?)then, you can write this in Assembly:Code:mov Ru15,0x0Af1794d // random address of dataenter_loop: nloop 6 // for (i=9 ; i>0 ; i--) || for (i=0 ; i<9; i++){ slwi // or rlwinm, see previous post of backsheeplogicload Ru01,Ru15 // get valuemov Ru06,Ru01 // duplicatebitrev 17,Ru00,Ru01 // number of bit 1neg Ru01 // bit invert of valuebitrev 17,Ru02,Ru01 // number of bit 0 of initial valuersht Ru01,17 // right shift of complemented upper valueadd Ru01,17 // add it + 17xor Ru06,Ru01 // shuffle & shakemac Ru03,Ru06,Ru00 // famous DSP functionmac Ru06,Ru03,Ru02 // more shuffled with famous DSP functionsto Ru15,Ru06 // store #@%&~*add Ru15,4 // next value} // nloop 6,12 end of 9 loops of 13 instructionsexit_loop: // looped without using a register for i (shadow register?) Loop overhead 1 instruction!Now you have the primitive for pre/post increment or push/pop n/POPCNT!Another example:Code:nloop 1,0 imul Ru00,Ru00 //for square of square of square of Ru00!orCode:imul Ru00,Ru00imul Ru00,Ru00imul Ru00,Ru00Have fun! ;-)

author: legacy
author_rank: Super Contributor
timestamp: March 04, 2016, 12:12:00 pm
content: Quote from: Cerebus on March 04, 2016, 12:29:49 amgood trick, brilliant

author: legacy
author_rank: Super Contributor
timestamp: March 04, 2016, 12:13:28 pm
content: Quote from: CXm0dk on March 04, 2016, 09:33:46 amexcellent, thank you very much

author: legacy
author_rank: Super Contributor
timestamp: March 04, 2016, 12:20:54 pm
content: Quote from: CXm0dk on March 04, 2016, 09:33:46 amyep, I bought a Papilio/Pro board, it's Spartan6e fpga, it comes with synchronous dram (8Mbyte) already installed on the board, I added an external asynchronous static ram (2Mbyte), I am going to add an STN lcd (4bit, 320x240, 2bit of color), and a second uart console, since the first uart is used by the DebugEngineArise-v2.1 and greater will run there with a few of your tips & tricks successfully implemented (I hope)

author: legacy
author_rank: Super Contributor
timestamp: March 04, 2016, 12:22:36 pm
content: Quote from: ale500 on March 03, 2016, 05:41:57 amit prepares control signals along the data path and takes care about of magic under the hood

author: legacy
author_rank: Super Contributor
timestamp: March 04, 2016, 12:33:46 pm
content: Quote from: CXm0dk on March 04, 2016, 09:33:46 amwho is that guy called "slwi" ?

author: legacy
author_rank: Super Contributor
timestamp: March 04, 2016, 12:51:35 pm
content: Quote from: CXm0dk on March 04, 2016, 09:33:46 amyes, basically it's "decrement and loop until zero", in my head it uses a shadow registerQuote from: CXm0dk on March 04, 2016, 09:33:46 amI don't get itas I was talking about 1 instruction which is able to perform pre/post increment within the load/store class of instructionssomething like:push r1 ---> store r1, (sp)+4 ---> store r1, (sp), sp=sp+4; 1 instructionpop r1 ---> load r1, -4(sp) ---> sp=sp-4, load r1, (sp); 1 instructionsizeof(r1)=4 byte, it's 32bit register, the load/store stage is attached to 32bit bus but it's able to access the memory with a byte granularity

author: CXm0dk
author_rank: Newbie
timestamp: March 04, 2016, 02:05:30 pm
content: Quote from: legacy on March 04, 2016, 12:33:46 pmsee thisprevious post

author: legacy
author_rank: Super Contributor
timestamp: March 04, 2016, 03:04:15 pm
content: oh, PowerPC, it'sthisguy

author: legacy
author_rank: Super Contributor
timestamp: March 04, 2016, 03:16:11 pm
content: I can implement "rlwinm" with +1 penalty (it takes an extra clock cycle in the ALU stage), but …Code:dest-register, source-register, rotate-left, mask-left, mask-rightit has too many parametersdo I have to implement "variable length" opcodes in the fetch unit like in Blackfin?

author: CXm0dk
author_rank: Newbie
timestamp: March 04, 2016, 05:04:20 pm
content: Quote from: legacy on March 04, 2016, 12:51:35 pmnot in one instruction, for example, the pre-increment addressing mode:Code:xor Ru01,Ru01 // clear Ru01 (int sum = 0)mov Ru15,0x64EF01AD // tail pointer of an integer arraynloop 17 // for (i = 20 ; i > 0 ; i--) sum += *(--pointer);{sub Ru15,4 // decrement address ; pointer -= sizeof(int)load Ru00,Ru15 // value = *pointeradd Ru01,Ru00 // sum += value}I do not say that array is passed as the last parameter in the stack (or you must change 0x64EF01AD by SP) ... ;-)Quote from: legacy on March 04, 2016, 12:51:35 pmwell, neither in one instruction neither implementable with SP as special register, I just think of something like that forpush n:Code:// push in stack the int arraymov Ru15,0x64EF01AD // pointer = arraymov Ru31,SP // next store space in stack ; instack = SPnloop 17 // duplicate values of int array in stack : size(int array) - 3 = 17{load Ru00,Ru15 // value = *pointeradd Ru15,4 // next value in array ; pointer++add SP,4 // reserve space for valuesto Ru31,Ru00 // *(SP-4) = valueadd Ru31,4 // next store address in stack ; instack++} // nloop 17,4 ; 20 * 5 instructions executedoh, I forget an optimization:Code:// push in stack the int arraymov Ru15,0x64EF01AD // pointer = arraymov Ru31,SP // next store space in stack ; instack = SPadd SP,80 // reserve space in stack for the whole arraynloop 17 // duplicate values of int array in stack : size(int array) - 3 = 17{load Ru00,Ru15 // value = *pointeradd Ru15,4 // next value in array ; pointer++sto Ru31,Ru00 // *instack = valueadd Ru31,4 // next store address in stack ; instack++} // nloop 17,3 ; 20 * 4 instructions executed if instructions are not parallelized between ALU & LOAD/STORE unitthis is much simple than any complexe addressing mode, butnloopmay be reduce in early stage of your pipeline (use 0 real CPU cycle), but creating complexe addressing mode will not cover all the use case, plus the compiler will rarely use them and that's complexify code generation stage... See the reduction in the addressing mode between the68kfamily and these derivatives versions.Even better, if you have a prefetch instruction unit, it can prefetch@exit_loopthe next instructions at the end of the first loop!EDIT: correction about the 68000 addressing mode features

author: helius
author_rank: Super Contributor
timestamp: March 04, 2016, 08:52:31 pm
content: QuoteIn fact the later 680x0 processors greatly increased their addressing modes, not reduced them, adding complex modes like double-scaled double-indexed double-indirect. They had VAX envy...

author: ale500
author_rank: Frequent Contributor
timestamp: March 05, 2016, 05:44:47 am
content: The >=68020 had extra indirect addressing modes... those where the first to go for slowest implementation on the 68060... due to being hardly used.Things like :Code:lea eax,ebx+esi*4for fast add/multiply are sort of useful but indirect addressing modes ?... One should check for instance what metrowerks used to generate for the 68k and see if those modes are used...But if we see the evolution of RISC, there are not much more than base+index and sometimes post/pre increment, decrement. But that means another write port to the register file or another clock if there is only one port.

author: Muxr
author_rank: Super Contributor
timestamp: March 05, 2016, 06:00:54 am
content: Quote from: HAL-42b on March 01, 2016, 02:32:17 amOr picoJava, there was even a Verilog source for it:http://java.epicentertech.com/Archive_Embedded/Sun_Microsystems/Micro%20&%20Pico%20Java/PicoJava_Port_to_FPGA.pdfAlthough it still required compilation, it ran Java bytecode natively.

author: CXm0dk
author_rank: Newbie
timestamp: March 05, 2016, 12:21:15 pm
content: Quote from: helius on March 04, 2016, 08:52:31 pmHello helius,you are right, my statement is inaccurate, it's theColdFirewhich simplify the addressing mode, seeDifferences between ColdFire & 68KMay I should wrote "See the reduction in the addressing mode between the68kfamilies and the earlier derivatives versions."

author: legacy
author_rank: Super Contributor
timestamp: March 06, 2016, 01:35:07 pm
content: PowerPC addressing modesQuote

author: MK14
author_rank: Super Contributor
timestamp: March 06, 2016, 01:41:03 pm
content: Quote from: legacy on February 29, 2016, 06:17:25 pmDelete ALL the other instructions, and just give me my SBNZ.https://en.wikipedia.org/wiki/One_instruction_set_computer

author: legacy
author_rank: Super Contributor
timestamp: March 06, 2016, 01:58:57 pm
content: computer science humor

author: legacy
author_rank: Super Contributor
timestamp: March 06, 2016, 03:18:30 pm
content: an interesting lecture aboutPentium and PowerPC, CISC against RISC

author: MK14
author_rank: Super Contributor
timestamp: March 06, 2016, 04:14:09 pm
content: DebugInstruction Which sends all the current cpu register and status values, to the default output port, e.g. USB.ConvertIntAcsii Instruction ==>> printf("Example %d", i); // or fprintf or itoaBoundsCheckMinMax ==>> a ==>>(0,40)==>>ERROR: 41 > 40PerformFPGAleIMMEDIATE ==>> LE $00243 ==>> $00243++ = Mini VHDL/Verilog sequences, user defined, max 32 LE's per sequenceSELFTEST = Activates the built in self test. Must be first instruction after reset, if wanted. Sends result PASS/FAIL and maybe why, to default USB port. Great for easy production/product testing.FUN = Functionally UNdefined = completely undefined behavior = fun! (Joke).

author: legacy
author_rank: Super Contributor
timestamp: March 06, 2016, 05:51:11 pm
content: Quote from: MK14 on March 06, 2016, 04:14:09 pmmy debug engine tries to export and import things like the CPU's context

author: MK14
author_rank: Super Contributor
timestamp: March 06, 2016, 05:54:41 pm
content: Quote from: legacy on March 06, 2016, 05:51:11 pmThat's good, useful and thoughtful.But you have owned up to making mistakes sometimes..........

author: legacy
author_rank: Super Contributor
timestamp: March 06, 2016, 11:12:59 pm
content: Quote from: MK14 on March 06, 2016, 05:54:41 pmthose things that you are talking about are too complex to be implemented at the HDL level, and they are done by softwarethe debug engine talks with the host, where the debugger runs

author: MK14
author_rank: Super Contributor
timestamp: March 06, 2016, 11:31:46 pm
content: Quote from: legacy on March 06, 2016, 11:12:59 pmSo in a sense, your external software is talking to a jtag, or something similar, which lets you access the necessary stuff.It is rumored that later generation, high end processors, such as the Intel Xeon Server chips. Will have built in FPGA accelerators, in some/all? of them. Intel have even bought Atmel, probably to help with this.So being able to manipulate chunks of on cpu chip/package FPGA units, may become an increasingly important thing.So if you want to do extreme calculations of some types of algorithm, and stuff.Such as bit coins (before Asics took over). You could send it (presumably), to the on-die/package FPGA unit.So fully custom instruction(s), may become a thing, on an increasing large number of cpus, in the future.Details of exactly how (mainly) Intel are going to do this, don't seem to have been released, publicly. So what I am saying is SPECULATION.Massive server centres, are likely to be the first users, of this kind of stuff.

author: legacy
author_rank: Super Contributor
timestamp: March 07, 2016, 12:00:34 am
content: Quote from: MK14 on March 06, 2016, 11:31:46 pmyes, it's similar to jtag and swd, the debug engine comes with a custom protocol (HDL side on fpga, and C side on PC) that I have designed for this specific purpose in order to provide the following capabilities:code injectionstep by stepbreack-pointwatch-pointregisters read/writebus read/writeexception injectionIt's also able to upload up over the usb-serial up to 512Kbyte per session @ 2Mbps with an efficiency of 92%useful to upload code and data intoistruction-ramanddata-ram

author: MK14
author_rank: Super Contributor
timestamp: March 07, 2016, 12:23:30 am
content: Quote from: legacy on March 07, 2016, 12:00:34 amIt will be interesting to see this up and running, later. I wonder how fast it is going to be ?I guess that out and out speed, is somewhat low on your priorities list.Stead, reliable and perfectly accurate, are the vibes/impressions, I get.Are you going to start a thread, later, entitled "Criticize my new cpu instruction set" ?

author: legacy
author_rank: Super Contributor
timestamp: March 07, 2016, 01:07:20 am
content: Quote from: MK14 on March 07, 2016, 12:23:30 amit might be a good idea, as one keeps getting betterthis topic is good to understand what people needse.g. the previous tips about DSP-instructions

author: legacy
author_rank: Super Contributor
timestamp: March 07, 2016, 01:09:38 am
content: Quote from: MK14 on March 07, 2016, 12:23:30 amprecisely

author: westfw
author_rank: Super Contributor
timestamp: March 07, 2016, 09:45:04 am
content: I do miss the fancy looping instructions from the CISCO world: subtract and jump if not equal to zero, add one to both halves and jump if negative, etc.But I don't really expect them to show up on RISC machines...What MIGHT be nice is an easier way of implementing "critical sections" (which can be pretty painful), which in turn would enable easy use of macros to simulate some of the missing complex instructions. Something that disables exceptions for the next N instructions, or maybe a save-and-clear/restore pair.

author: amyk
author_rank: Super Contributor
timestamp: March 07, 2016, 10:11:46 am
content: Powerful CISC instructions are no big deal with uop translation. Loops and such just get turned into a series of uops by the decoder.

author: legacy
author_rank: Super Contributor
timestamp: March 07, 2016, 01:53:12 pm
content: decrement and branchcan be implemented with the penalty of 2 extra clock cyclesQuote from: westfw on March 07, 2016, 09:45:04 amAriseis featured by "context switch" in hardware, exceptions/interrupts are supported with their own registersthe context switch is done in hardware with no penalties, it should be fine for critical sectionsI have implemented a simple instructionCode:Eset imm16Exceptions/interrupts set enabled/disabledimm16 is a constant to used like a mask, each "1" enables, while each "0" disables, an exception/interruptEset 0xffff ; set all exceptions/interrupts enabledEset 0x0000 ; set all exceptions/interrupts disabled

author: legacy
author_rank: Super Contributor
timestamp: March 14, 2016, 12:59:52 pm
content: ProgressI have confirmed the following classes & instructions:Class.Alu.LogicandnandornorxorxnorShift.RShift.LClass.Alu.ArithmeticAdd.signedAdd.unsignedSub.signedSub.unsignedMul.signedMul.unsignedDiv.signedDiv.unsignedClass.Alu.BitfieldBit.getBit.setBit.toggleBit.get.firstBit.set.firstBit.rotateBit.sign-extendBit.swapClass.IOLoad.8Load.16Load.32Store.8Store.16Store.32

author: legacy
author_rank: Super Contributor
timestamp: March 16, 2016, 07:52:20 pm
content: I have to take a decision about the branch-instructionsthe68K way: do ALU, which modifies the condition code register, then test CCR.bit, in case it matches then branchthe88K way: compare and set a register with results (equal? greater? zero? ….), then get-bit, and if it's "1" than branchtheMIPS way: compare and branch (1 instruction)theARM60 way: similar to m68k, it adds 4 bit as "conditional execution", an instruction is executed if these 4 bits match the CCR statusIronically, I can implement all of these branch-methods

author: legacy
author_rank: Super Contributor
timestamp: March 18, 2016, 11:29:37 am
content: I confirm the following branch & trap instructions:ConditionalExecution.Branch.if.bit.setConditionalExecution.Branch.if.bit.clrConditionalExecution.Trap.if.bit.setConditionalExecution.Trap.if.bit.clras you can access r0 which always return zero (0x0000.0000)the following instructions are a subset case of the aboveConditionalExecution.BranchConditionalExecution.Trape.g.ConditionalExecution.Branch is implementedasConditionalExecution.Branch.if.bit.clrusingr0is bit.whatever clear in r0 ? yes, alwaysConditional Executionuses 16 conditions (4 bit, encoded, including overflow, carry, zero, negative, positive, etc) from the CCR (conditional code register)you can choose to "inhibit" the updating of the CCR, each instruction features the choice as there is a specific "CCR inhibit" bit in the Instruction forma (above is called "mode", I still have to rename it in the documentation)each branch can be specified asPC=rs1PC=imm32PC=rs1+signed(imm32)which permits absolutes branches, and relative branches, and register-driven branches(the program counter is now part of the registers-set, rs1 can be equal to PC)what do you think ?

author: legacy
author_rank: Super Contributor
timestamp: March 27, 2016, 04:36:36 pm
content: bought a few 80s and 90s papers, study material

author: MK14
author_rank: Super Contributor
timestamp: March 27, 2016, 05:08:52 pm
content: Quote from: legacy on March 27, 2016, 04:36:36 pmI'm jealous of you now!I use to read stuff like that. They were GREAT reading at the time, and I'd imagine that they still are.These days, a new release from Intel, is like +1% faster with such and such benchmarks, and 0.9% power consumption reduction, if the wind is blowing in the right direction, and there is a triple z letter combination in the month.Things DON'T seem to be progressing on the microprocessor front, as such. These days. Then there was HUGE changes, almost on a day to day basis. (Exaggeration).