Casting problem in VHDL - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 18, 2016, 03:11:00 pm
content: HiI'm kinda new to VHDl, I can not seems to figure out how to do this conversion, what should I do?Code:type myFRQ_BUF0 is array (0 to 7) of STD_LOGIC_VECTOR (47 DOWNTO 0);signal CapVal_00,CapVal_01 : STD_LOGIC_VECTOR (47 downto 0);signal freerun_cnt: STD_LOGIC_VECTOR (31 downto 0);signal RMS_BUF0,RMS_BUF1: myRMS_BUF0;process (clk)beginif rising_edge(clk) thenfreerun_cnt <= freerun_cnt + '1';if rising_edge(capture) thenCapVal_01 <= freerun_cnt;if(CapVal_01 > CapVal_00) thenFRQ_BUF0 <= STD_LOGIC_VECTOR (unsigned(CapVal_01) - unsigned(CapVal_00));elseFRQ_BUF0 <= STD_LOGIC_VECTOR((unsigned(CapVal_01) + X"100000000000") - unsigned(CapVal_00));end if;CapVal_00 <= CapVal_01;end if;end if;end process;ISE would trough this errorNear std_logic_vector ; type conversion does not match type myfrq_buf0

author: ale500
author_rank: Frequent Contributor
timestamp: October 18, 2016, 03:27:43 pm
content: What is the FRQ_BUF0 definition ?FRQ_BUF0 <= STD_LOGIC_VECTOR (unsigned(CapVal_01) - unsigned(CapVal_00));

author: Scrts
author_rank: Frequent Contributor
timestamp: October 18, 2016, 05:56:35 pm
content: Your myFRQ_BUF0 is array:Quote from: ali_asadzadeh on October 18, 2016, 03:11:00 pmYou are assigning std_logic_vector to an array. Assign it to one vector of that array then. For example to array element (0).

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 19, 2016, 12:28:31 pm
content: Thanks Scrts

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 19, 2016, 02:42:59 pm
content: I wanted to capture the duty cycle of a low speed input, it's called capture and it's about 500HZ my system clock is 50MHz, I have used chip scope to see the FRQ_BUF0(0) value, but it seems it does not capture the data correctly, I will get the FRQ_BUF0(0) some odd values like 0,2,3, 361 etc...what's wrong with my code, I have done it in an NXP LPC timer and the code is similar to the C implementation in there.my C code for the LPC looks like this and it works perfectly.Code:void TIMER2_IRQHandler(void){LPC_TIMER2->IR=0XF0;//Clear all sourcesCaptureValue=LPC_TIMER2->CR0;if(CaptureValue>CaptureValue){freq = CaptureValue - CaptureValue;}else{freq = ((uint64_t)CaptureValue+ 0x100000000) - (uint64_t)CaptureValue;}CaptureValue=CaptureValue;}

author: Dago
author_rank: Frequent Contributor
timestamp: October 20, 2016, 04:21:21 am
content: Are you synchronizing the input signal going to the FPGA? A 1-3 stage flip-flop chain is usually used for this.

author: hamster_nz
author_rank: Super Contributor
timestamp: October 20, 2016, 05:49:52 am
content: Code:if rising_edge(clk) thenfreerun_cnt <= freerun_cnt + '1';if rising_edge(capture) thenNested "if rising_edge(xxx)" makes no sense. It might simulate but is wrong.- no two signals can have a rising edge at the sametime.- In hardware a flipflop can only be sensitive to one edge.Also your sensitivity list is just for one signal.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 21, 2016, 08:07:09 am
content: Thanks I have syncronized the capture with the CLK but I still out of lockHere is the updated codeQuote

author: Someone
author_rank: Super Contributor
timestamp: October 21, 2016, 09:22:28 am
content: You cant simply rewrite sequential (C) code in VHDL syntax and have it work. Here is a really high level and shallow coverage of the basics:http://web.mit.edu/6.111/www/f2007/handouts/L06.pdfYou need to spend some serious time learning about how a simultaneous evaluation language (non-blocking assignments in HDL) works, and why its not directly the same as sequential language. This isnt something quick and easy but many days of slow learning to completely change your point of view about what programming is.Walk before you run.....

author: Kalvin
author_rank: Super Contributor
timestamp: October 21, 2016, 09:36:18 am
content: If your intention is to implement a shift register, the following code snippet may not do what you intend to do:Code:capture <= capture(2 downto 1) & capture_pin;See here:http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode8.html

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 23, 2016, 06:12:11 am
content: QuoteIt's for synchronising the capture_pin to the FPGA clock

author: hamster_nz
author_rank: Super Contributor
timestamp: October 23, 2016, 09:48:45 am
content: Quote from: ali_asadzadeh on October 23, 2016, 06:12:11 amOr a little less subtly, how does the value in capture(1) change when you keep on assigning it to itself?Did you mean:Code:capture <= capture(1 downto 0) & capture_pin;