SoC ADC's vs stand-alone ADC's, why such a price/performance/power difference? - Page 1
Forum section: electronics / projects

author: dmg
author_rank: Regular Contributor
timestamp: October 17, 2016, 09:51:57 pm
content: So today I got curious and started researching what kind of ADC's do 802.11ac WiFi SoC's use for their receivers. Being 160 MHz channels and usually MIMO setups I expected to find people selling IP with multiple 180+ Msps dual ADC's of relatively good performance, and sure enough that's what I found. Some IP from cadence, synopsis and some other people that also included the TX dac's and all of that to implement in <45nm silicon, some of them in <28nm. However, I expected to see modestly performing ADC's of 10 bit tops with limited dynamic range and a "reasonably high" power consumption even though I know that dealing with a wideband OFDM signal requires large dynamic range and embedding something in a smartphone requires very low power.What I found however were super tiny, very well performing 12 bit (11 bit ENOB) SAR ADC's at 200+ MSPS consuming single digit milliwats of power for the WHOLE IP including 2 or 3 dual ADC's and the same amount of DAC's, and they usually also throw in some clock distribution and syncronization stuff. See for example:https://www.synopsys.com/Company/Publications/DWTB/Pages/dwtb-data-converter-sar-2014Q2.aspxhttp://ip.cadence.com/uploads/635/IP9130C_LTE-802_11ac-AFE_ds-pdfhttp://www2.imec.be/content/user/File/NEW/Research/Wireless%20Communication/ADC/FEB%202014%20ADC.pdfSo, comparing that to the selection of stand-alone dual ADC's of typical manufacturers such as Analog Devices, Texas Instruments and such, that consume several hundred milliwats of power even taking the digital interface portion out, have comparable performance, cost 10's of dollars, are usually pipelined with huge chips in 130nm+ geometries, why is there such a difference? I'm not talking about the 300Msps+ 16 bit stuff here, I'm talking about the 12 or 14 bit ADC's that have similar dynamic range, SFDR and other figures of merit than these ADC's for wifi SOC's. Anyone can give a clue about why is there such a difference and what compromises are made? I have myself designed radio receivers with 100+ Msps ADC's in them and I'm aware that dealing with a 160 MHz noise-like OFDM signal requires good stuff so no crappy ADC would do the job...

author: moffy
author_rank: Super Contributor
timestamp: October 17, 2016, 11:44:18 pm
content: Sorry I can't help with an answer, but from reading your post it is a real head scratcher. The 28nm might be the reason for the lower power but why TI or AD haven't come out with stand alone equivalents is baffling.

author: jeremy
author_rank: Super Contributor
timestamp: October 18, 2016, 12:15:09 am
content: My guesses:- yield is low- volume is low (for standalone ADCs, most of the IPs would be integrated in a baseband modem I think)- testing is slow/expensive- can one realistically predict the noise figures for IP? Seems like you'd need to fab it on your specific process first.- (cynical version: maybe charging for old designs what the market will bear?)People who write IP only can avoid these recurring costs better than a manufacturer I would imagine.

author: Wimberleytech
author_rank: Super Contributor
timestamp: October 19, 2016, 01:00:18 pm
content: Jeremy is on target with his answer. I will expound a little.Market:There is not a huge market for these high-end ADCs, so their volume is relatively low. With low volume, TI (e.g.) is not motivated to put R&D into moving a particular design into a finer linewidth. One example I can think of: CS5016 self-calibrated 16-bit ADC started production in 1986 (Crystal Semiconductor). It was 3u CMOS single metal, single poly process. It was not EOL'ed by Cirrus until 2006. In 2006 linewidths were 60nm mainstream. Cirrus was probably selling only hundreds of these chips and was never motivated to move it to a finer geometry.Cost:A packaged chip cost = die cost + package cost + test cost with each adjusted by yield at each stage. Test cost is a biggie for a precision high-speed adc where you are guaranteeing INL, DNL, missing codes, etc. An embedded adc is not tested to these performance levels explicitly.Yield:For standard product adc's, manufacturers mitigate yield issues somewhat by binning parts and offering different grades so that they can sell most anything they can get out of the fab.There are other issues as well: validation of design for release to production (QC, burnin qualification...etc...etc). These cost money which are not part of recurring cost but part of R&D RTP. How much and what kind of capital equipment do you need in place to make/test/sell these products (and maintained!). It all adds up.IP is a different animal altogether. For the most part it is validated via simulation and a few test wafers. Cadence et al., will not guarantee yield--you are pretty much on your own. Neither do they write a test suite for the IP. All you need to punch out some IP is Cadence Virtuoso, analog artist, and a fast workstation.

author: dmg
author_rank: Regular Contributor
timestamp: October 20, 2016, 09:31:29 pm
content: All you say makes sense, however I still can't explain to myself why there is such a gap. These ADC's will be dealing with nightmarish signals that require pretty good specs to be digitized correctly, we're talking about 80-160 MHz OFDM signals crammed with densely modulated subcarriers and there are limits on what you can do on software to correct for digitalization software. I assumed those limits were higher than I though but seems like they aren't, you do need a good ADC.My main concern is why, having ADC's ready to implement in silicon and probably already tested in the real world being part of WiFi SoC's that will eventually be mainstream and be implemented on even the crappiest piece of consumer hardware, there's no one packaging these ADC's by themselves and selling them for $40 a pop, when comparable stuff today costs about the same but consumes 50 times more power. (for example:http://www.ti.com/lit/ds/sbas550c/sbas550c.pdf)

author: Ammar
author_rank: Regular Contributor
timestamp: October 20, 2016, 09:41:46 pm
content: Shahriar from the Signal Path said something that I feel is relevant here. With Moore's law, the density of transistors grows exponentially, but so does the cost involved in using the next best technology. 14nm and 22nm masks for IC productions can cost several million dollars, just for the mask. These technologies also produce transistors that are faster and consume far less power. Unless TI or Analog Devices feel that there is a massive market for packaging these ADCs on their own then it really isn't worth it for them.