Why DRAMs never binning with disabled cells? - Page 1
Forum section: electronics / general

author: Logan
author_rank: Frequent Contributor
timestamp: April 29, 2021, 11:41:02 am
content: I just realized CPUs, GPUs, and NANDs usually have lower binning with disabled parts, but DRAMs only differs by speed. How can they archive that yield with even more transistors than CPUs?

author: brabus
author_rank: Frequent Contributor
timestamp: April 29, 2021, 11:51:34 am
content: I would guess that DRAM transistors are much easier to make than floating-gate Flash.DRAM is basically a wide sea of very small capacitors.I'd like to hear the opinions of the specialists here on the Forum, I am sure there will be interesting contributions.

author: wraper
author_rank: Unknown
timestamp: April 29, 2021, 11:54:37 am
content: RAM chips use spare rows/columns. It's just that they are not available from the outside unlike on NAND where bad blocks are managed by external controller. And unlike on CPU/GPU, you don't need to disable whole cores or cluster of cores. Also I guess RAM chips with half of true capacity disabled are also possible.

author: ataradov
author_rank: Super Contributor
timestamp: April 29, 2021, 05:05:14 pm
content: There are absolutely more cells than advertised and remapping of bad cells is done at manufacturing time.This even happens in some high-performance MCUs with a lot of SRAM. That remapping capability is the key to getting good yields overall, even if memory array takes up more area. You just balance the number of spares according to your actual yield.

author: Kleinstein
author_rank: Super Contributor
timestamp: April 29, 2021, 05:17:02 pm
content: Modern DRAM chips (already for some 30 years or so) have internal error correction. So they have spare cells (e.g. some 10%) and do internal error correction, hidden from the user. So they can correct a certain fraction of bit errors - this can be be permanently broken cells or just random (e.g. from radiation) errors. It is more like normal that a RAM chip contains some bad cells, but one would not really notice it. In the groups with broken cells there may be no more error correction, but this would be more like a small fraction (e.g. a few ppm - so maybe still 100s of defects) of the cells only. At least server RAM has an addition layer of error correction also for the bus and visible to the CPU.It is just not feasible to do excessive testing to also find partially faulty cells. So the system has to be somewhat fault tolerant.There may be additional making of faulty cells, but the main part is having real time error correction with more data saved. CD ROM uses a similar system.I would not really expect that they use partially broken chips with reduced capacity. This may happen if for some reason they produce a large batch of them, but this would be rate and more likely end up in very low cost cards, maybe sold in India or China.SSD Memory / Memory sticks may use partially disabled / broken parts, as they may need the software to handle a file systen or similar anyway. So it is very little effort and even the testing can be done by the product itself. So there is very little extra effort.

author: wraper
author_rank: Unknown
timestamp: April 29, 2021, 05:29:25 pm
content: Quote from: Kleinstein on April 29, 2021, 05:17:02 pmYour claims about internal error correction are not true. AFAIK the first time it was implemented in general purpose DRAM is DDR5 which has yet to come to market. Otherwise Rowhammer attack would not be possible.https://en.wikipedia.org/wiki/Row_hammerUsage of spare rows/columns is programmed at factory and there is no further correction of faulty cells.

author: David Hess
author_rank: Super Contributor
timestamp: April 29, 2021, 11:07:06 pm
content: I agree with wraper on that one Kleinstein as I just looked into it a few weeks ago.DRAMs and CPU cache and I assume SRAM have included spare rows and/or columns for decades now to increase yields. I thought DRAM ECC would be implemented for any row access as the stage after the sense amplifiers but ECC in DRAM is limited to the burst size and is implemented at the interface. It does *not* write corrected data back during a read operation because it would take too much power and space to implement.

author: ejeffrey
author_rank: Super Contributor
timestamp: April 30, 2021, 02:03:56 am
content: Quote from: Kleinstein on April 29, 2021, 05:17:02 pmCDROM uses a very cool multilayer error correction system that is substantially different from plain ECC used in DRAM. CDROMs use two concatenated reed-solomon codes that are interleaved. If the inner code finds an error it can detect but not correct the whole block is marked as an error. The error is marked as an erasure (error at known location) to the outer code which doubles it's correction efficacy. Due to the interleaving an erased inner block is distributed over multiple outer blocks so that the outer code can still correct it. This makes it very good and handling burst errors to the point where it is almost impossible to actually get actual read errors on a CDROM. Usually long before that you screw up tracking.