Ground pour in buck regulator - Page 1
Forum section: electronics / beginners

author: VEGETA
author_rank: Super Contributor
timestamp: July 23, 2025, 06:44:01 am
content: Hello,I have a very tight space issue, 2 main buck regulators. 4 layer board with layers 2, 3, and bottom (4) all solid ground pours.My question is: is it ok for top layer ground connection from buck regulator chip (and its output filter caps) to not have a path to main source ground in top layer? while having lots of close vias to ground near chip ground pin and all the output/input caps. I want to achieve very low noise and ripple as always.I mean the path is clogged in top layer and barely any space available. the path to source ground in top layer is blocked by the power input trace of the 2nd regulator.in some measure, i can make a path on top layer but i would need to route the input power to the 2nd regulator using the bottom layer then put a small pour on top layer with vias to connect it.max output = 5v 2 amps for first regulator (less for 2nd regulator).input voltage = 15vswitch freq: 1.2 MHzcaps all ceramics and low esr polymers.what do you recommend i do?

author: MrAl
author_rank: Super Contributor
timestamp: July 23, 2025, 10:18:43 am
content: Quote from: VEGETA on July 23, 2025, 06:44:01 amHi,I recommend showing the board design here so others can see what you are talking about exactly.

author: VEGETA
author_rank: Super Contributor
timestamp: July 23, 2025, 02:46:21 pm
content: Here is the board image in attachment.the power route is in green, which is delivered normally to buck 1 on top layer.right now, buck 1 ground can reach the source ground pin (in red) on top layer, but if i routed the input to buck 2 on top layer it will block the path.should i keep buck 1 having direct path to ground on top layer (of course it will have lots of vias to the 3 full ground plains too)... and use the bottom layer to route power to buck 2? or route power to buck 2 on top layer, then rely only on ground plains and vias for buck 1 ground?for my target, buck 1 is more important and current capable than buck 2. buck 1 top output is about 2 amps while buck 2 is 1 amp at most but regularly maybe just 600mA output.

author: Kurets
author_rank: Regular Contributor
timestamp: July 24, 2025, 05:02:32 am
content: You have two main concerns when powering a DCDC circuit, voltage/power loss due to resistance and inductance of main switching loop. I see no issue in routing positive power to both converters in the top layer and just using vias for connecting to the ground plane.You should put effort into making sure that the loop formed by input capacitors (the ceramic ones, not the the bulk filter), IC input and switch pin, inductor, and the output capacitors, is as small as possible. Keeping that path in a single layer is more important in my opinion than anything related to just the input.From a glance this does not seem to be the case, and I am also doubtful about the use of a SOT23-6 buck IC. You see those appear in undersized ebay specials. Remember that ratings of chips in datasheets usually are semi-fictive when you consider non-ideal cooling of the chip etc.

author: VEGETA
author_rank: Super Contributor
timestamp: July 24, 2025, 05:19:48 am
content: Quote from: Kurets on July 24, 2025, 05:02:32 amwell, the same circuit is working fine for the current version achieving good ripple and noise results. the IC runs nicely and the entire design is very cold.The loop is very small and tight, the picture does not show the whole output caps though. the caps are very close to each other so that courtyard lines in kicad touch between them. cannot get more closer unless i modify courtyard boundaries of the caps but still very very small room there.please check the attached image and see the blue lines showing the loop from input caps to output caps and grounds. maybe you did not like that the big output cap is not facing the same direction as the other ceramics but i guess this also works. I once consulted TI with it and they approved (switcher from them). i may be able to rotate the big cap if that is the biggest issue, will take lots of tidying up tho.what do you suggest?

author: VEGETA
author_rank: Super Contributor
timestamp: July 24, 2025, 09:33:20 pm
content: i have added a new image.now i clarified the current loops + the output pins of this PSU which will be hooked to the device via a thick wiring harness.do you think the loops are good?will they be better if I oriented the big cap the same as smaller caps + make them closer to the inductor (and themselves after reducing the courtyard)?notice that routing power from last output cap to the output pin on top layer will prevent a continuous ground pour from the ground pins to the output capacitors' negative terminal. however, you seem to agree that the actual loop is more important than this.what do you think?

author: VEGETA
author_rank: Super Contributor
timestamp: July 26, 2025, 12:29:50 am
content: I tried again and made the routing with the caps all line up and close, can be closer to each other when i modify the courtyard as mentioned.i showed the power routing and ground pins location.the design is 4 layers, 3 of them are just solid ground pour and will put many vias especially near the caps.

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 26, 2025, 12:32:33 pm
content: Quote from: VEGETA on July 23, 2025, 02:46:21 pmI'm not seeing the issue here. If you have three layers with solid GND pours, then those layers will certainly become the return path for the power source. There's likely no need to have any GND pours or traces on the top layer, just vias to the other layers' GND pours.I'm assuming those groups of MLCCs (C1-C6, C9, and C10) are for bypassing Vin of the buck. It's the placement of those caps that is really important, since they will form the return path for high frequency switching currents. They look fine to me, but it would be helpful if you showed the actual copper features, not a black soldermask which hides everything. Better yet, don't bother with a 3D render at all, just show the top copper and silk layers.Quote from: VEGETA on July 24, 2025, 09:33:20 pmThe placement of the large electrolytic caps isn't critical, a few mm of spacing won't matter.QuoteAgain, I don't see the problem here. Since other layers are solid GND pours, you do not need to connect GND pins together on the top layer.

author: VEGETA
author_rank: Super Contributor
timestamp: July 26, 2025, 07:08:02 pm
content: QuoteI want to make sure that power return path current is different than ripple filtering itself. Meaning the return path is from the 6-pin output connector GND pins directly to source ground pins via the 3 layers of ground pour.while output caps with inductor forming a loop, this loop is for filtering output ripple and high freq. noise... meaning it will pass from switcher to inductor to output caps, and from output caps negative pins it will be bypassed to ground by the many vias to be there... once reaching bottom ground pours it will return directly to ground of the source... hence won't reach the output itself.is this ok?QuoteYes, C2, C4, C6, and C10 are input bypassing just before the switching IC, while the ones below are the output caps along with the big one.right now i am still haven't done the layout as I am deciding stuff, which is why i asked here to get more opinions.but as i told you, those input caps will be connected by solid pour from the 15v caps... while their negative (ground) pins to be with ground vias to internal grounds. they are facing side ways meaning their positive sides are together and their negative sides or away like in picture.Quoteit is an extremely low esr polymer cap from panasonic with 3 legs for 50% less ESL. its positive side is with the parallel ceramics but its negative on the other side... same issue as input caps which i want to verify if it is ok.i mean for ripple and noise reduction, will this negatively affect it? i mean compared to if the big cap is also in-line with the ceramics.i posted different layouts, please check if any of them is better in your opinion.Quotewon't it be a better path if the negative pin or ground pin returns directly to source ground pin without going through vias?

author: VEGETA
author_rank: Super Contributor
timestamp: July 28, 2025, 09:17:10 pm
content: Here is the layout for right side regulator:https://imgur.com/a/z8BS2z3still needs refinement of course, but overall this is it. I think loops are tight and ground is all connected firmly.you think caps being face to face like this is ok with all these grounding vias?

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 28, 2025, 10:11:07 pm
content: Quote from: VEGETA on July 26, 2025, 07:08:02 pmOkay sounds like you want to minimize the distance which ripple currents travel through the GND plane(s). This is a good way to minimize common mode emissions.Then you want to keep all the negative terminals of the input and output bypass caps as close to the switching IC as possible (especially the ones bypassing Vin). It might be possible to make the Vout caps more compact around the IC, but it looks pretty good to me already.QuoteNot sure I understand this... which caps are "the 15V caps"?QuoteI was referring to the radial through-hole caps on the Vin side of the circuit.QuoteI can't tell what pins you're referring to. Lots of things of "ground pins" or "negative pins". I guess by "source ground pin" you mean the actual power source for the whole circuit (that big black box)?

author: VEGETA
author_rank: Super Contributor
timestamp: July 28, 2025, 10:19:11 pm
content: Quoteinput caps are already the closest they can be and have short straight path to IC ground, which is surrounded by many ground vias.since i do not have direct path to source ground (big box) on top layer due to how crazily compact and tight the board space is, i opted for putting lots of ground vias near output (and input) caps' ground pins as you see. with 3 layers of solid ground it should be ok i believe.QuoteI mean the ceramic caps at the input for the switching IC not the big bulk radial ones.Quotesource is the big box which is ac-dc meanwell power module.

author: mtwieg
author_rank: Frequent Contributor
timestamp: July 29, 2025, 12:55:46 pm
content: Quote from: VEGETA on July 28, 2025, 10:19:11 pmAgain, this is totally fine. Even if you did have room for a return path on the top layer, a return path on the inner/bottom layers would probably be preferable.It would be helpful if you shared gerber files, or at least a view showing the actual copper features and vias (I don't understand why people default to showing 3D renders of the board, that is much less useful...).

author: VEGETA
author_rank: Super Contributor
timestamp: July 29, 2025, 01:55:53 pm
content: Quote from: mtwieg on July 29, 2025, 12:55:46 pmI shared the link here:https://imgur.com/a/z8BS2z3entire layout still not done but enough was made as a start.I understand what you said about return path being inner layer dependent.However, you see my output caps and what i posted about them? I mean parallel ceramics inline while the big polymer face to face (its ground on the other side but still lots of vias to ground nearly everywhere).I believe it is fine and even TI support confirms it but I would like to get more assurance from here as I want lowest ever ripple i can get.the output caps and their ground (and vias) are not so close to the GND output pins... so when the load current returns, it will return in ground plains under the caps since it is 1.2MHz and lowest inductance being mostly there... right?so the return load current path is different than filtering effect of bypassing ripple and noise done by the caps??I mean all high freq. noise and the ripple will pass through the caps directly to ground and returns while load current passes as clean as it would be then when returning it returns back from the 2 output connector GND pins using lowest inductance route (under the original current path). I need to confirm/understand this.another irrelevant thing: by using dual p-mosfets as activation + protection (ideal diode) will they provide same effect as linear regulator in eliminating low freq. ripple? i know the magnitude will be so small but still, does this effect gonna happen?

author: ArdWar
author_rank: Frequent Contributor
timestamp: July 29, 2025, 03:07:20 pm
content: Is that TPS56224? Sneaky little bugger, pain in the ass to rework.Don't worry, your layout appears to be fine. I've done worse than that lol. However I wonder why you chose to "island" the input ground. As you say you have 4 layers to work on, I'd prefer to route the EN pull-up through bottom layer. Shorter traces, more compact, and most importantly won't island/finger the top layer GND.

author: VEGETA
author_rank: Super Contributor
timestamp: July 29, 2025, 04:31:29 pm
content: Quote from: ArdWar on July 29, 2025, 03:07:20 pmit is tps564247 actually, really nice one with dcap3 control.i did not want to island it, but rather that is how it ended up with. I fixed it now as you see in attached images where EN resistors are wired through bottom layer.now there is more continuous ground to the regulator gnd from top layer.any other tip you can point out?what is your opinion about my caps and what i said about returning current vs filtered current?

author: VEGETA
author_rank: Super Contributor
timestamp: July 30, 2025, 10:03:48 pm
content: maybe i forgot to mention but i have a simple pi filter at the input of both regulators... it has 220uF -> 10uH -> (220uF || 220uF). inductor is about 10-15mohm dcr and caps are 20-30 mohm esr polymers. I usually have just the 3 polymer caps tho.I mainly added this to filter out any low frequency ripple generated by the meanwell power module (15v) to make it easier for the switchers to produce low ripple.is there any danger of doing this? like spikes, bad transient at output, etc...? the switchers are rated for maximum of 17v input and i believe the pi filter won't make any spike that would reach that from the supplied 15v.the local filtering for the switchers is 4x10uF 0805 ceramics with 100nF 0402... will produce effective capacitance of about 6uF. I want to use 22uF instead which will give effective capacitance of around 19-20uF using 6x 22uF 0805 ceramics instead.what is your opinion about all this?