VHDL help- Case statements, and declaring multi-bit signals! - Page 1
Forum section: electronics / beginners

author: McPete
author_rank: Regular Contributor
timestamp: August 14, 2011, 05:55:12 am
content: Hey all,Just putting together my first little FPGA configuration for my technical college class on VHDL- It's the first time they've taught it, so the instruction was "Go figure it out." I THINK I've got something that should work, but I'm getting a few compliation errors. If a few of our number who are experienced in the ways of VHDL could set me straight, I'd appreciate it!What I'm trying to create here is a greycode-to-bcd decoder. I think the case statement is right, I'm just not sure about my signal decs... I'm using the Quartus II IDE, for reference. Here's the code;Quote from: Pete's Decoder VHDLThanks for your help!

author: jahonen
author_rank: Super Contributor
timestamp: August 14, 2011, 07:36:54 am
content: I think you are missing several semicolons, port declaration in entity, bit vector lengths (indexes describe the number of bits the vector holds, not the value it represents) etc. Instead of describing all of them individually, I attached fixed version below (checked it with ModelSim so it should compile ok). BTW, I think it would be more appropriate to use std_logic and std_logic_vector datatypes instead of bit and bit_vector. Also, usually vectors are indexed from high down to low, so that high index is in the left. You could also put greyin and bcdout vectors directly to the entity port instead of individual temporary signals. However, don't worry, it will usually take a quite long time to master the VHDL "perfectly".Regards,JanneQuote

author: FPGAcrazy
author_rank: Contributor
timestamp: August 14, 2011, 09:01:11 am
content: Hi,The example as posted has some mistakes as already pointed out by jahonen. First of all, if you would like to assign a bit vector to the input and output signals, a vectors should be used of the type bit_vector instead of this single value bit. However, in modern VHDL coding bit and bit_vector are not used instead std_logic_vector, unsigned and signed are used for vectors and std_logic for single signalsThe use of these constructs is illustrated in the following examplelibrary ieee;use ieee.std_logic_1164.all;entity bcd_7seg isport (bcd : in std_logic_vector(3 downto 0);seg : out std_logic_vector(6 downto 0));end;architecture rtl of bcd_7seg isbeginprocess(bcd)beginseg <= (others=>'1');case bcd iswhen "0000" => -- 0seg (5 downto 0) <= (others=> '0');when "0001" => -- 1seg(2 downto 1) <= (others=>'0');when "0010" => -- 2seg(1 downto 0)<=(others=>'0');seg(6) <='0';seg(4 downto 3)<=(others=>'0');when "0011" => --3seg(3 downto 0)<=(others=>'0');seg(6) <= '0';when "0100" => --4seg(2 downto 1) <= (others=>'0');seg(6 downto 5) <= (others=>'0');when "0101" => --5seg(0) <= '0';seg(3 downto 2) <= (others=>'0');seg(6 downto 5) <= (others=>'0');when "0110" => --6seg(6 downto 2) <= (others=>'0');seg(0) <= '0';when "0111"=> --7seg(2 downto 0) <= (others=>'0');when "1000" =>seg(6 downto 0) <= (others=>'0');when "1001" =>seg(3 downto 0) <= (others=>'0');seg(6 downto 5) <= (others=>'0');when "1010" => --Aseg(2 downto 0) <= (others=>'0');seg(6 downto 4) <= (others=>'0');when "1011" => --Bseg(6 downto 2) <= (others=>'0');when "1100" => --Cseg(5 downto 3) <= (others=>'0');seg(0) <= '0';when "1101" => --Dseg(4 downto 1) <= (others=>'0');seg(6) <= '0';when "1110" => --Eseg(6 downto 3) <= (others=>'0');seg(0) <= '0';when "1111" => --Fseg(6 downto 4) <= (others=>'0');seg(0) <= '0';when others => null;end case;end process;end architecture;This is fully working example which has been tested on a FPGA.A free book is the VHDL-Cookbookhttp://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf.This is not a very good book but it contains the syntax rules and should be used as a reference only.Hope this helpsJohan

author: patb
author_rank: Regular Contributor
timestamp: August 14, 2011, 09:54:04 am
content: Quote from: FPGAcrazy on August 14, 2011, 09:01:11 amThanks for the link to the ebook. Btw, would you recommend some really good book for complete beginner?

author: FPGAcrazy
author_rank: Contributor
timestamp: August 14, 2011, 10:21:59 am
content: Hi I have to admit that I learned VHDL many years ago. But I think I especially liked this book, although I am not totally sure(long time ago)Digital System Design With VHDL, 2nd EditionMark ZwolinskiISBN 0-13-039985-XI had a quick look through the examples they use the bit and bit_vector in the begin but later on they use the std_ulogic_vector.Some remarks. Be careful VHDL support many constructs of which only a small subset is suitable for synthesis.You also need some simulation and synthesis tools which depends on your target device (silicon vs FPGA and so on). However, for most FPGA simple tools for small designs are free.Have fun hacking.

author: patb
author_rank: Regular Contributor
timestamp: August 14, 2011, 11:59:16 am
content: I've found this book also translated to Polish. It seems the author has some Polish origins (his last name is definitely Polish). Looks like it's something I was looking for. Thanks for the recommendation!

author: McPete
author_rank: Regular Contributor
timestamp: August 15, 2011, 01:11:14 am
content: Hey all,I've modified the file as suggested, but Quartus is still producing this error;Error (10500): VHDL syntax error at project1.vhdl(29) near text "PROCESS"; expecting "<="What am I missing here?Thanks for your help all- This is one heck of a learning curve, especially when teaching yourself!P.

author: jahonen
author_rank: Super Contributor
timestamp: August 15, 2011, 06:37:01 am
content: Quote from: McPete on August 15, 2011, 01:11:14 amI think it must be a typo or something like that, I tried the version I posted above and it compiled with flying colors, no problems at all with Quartus 9.0 SP2. Below is the synthesis result as viewed from Quartus RTL viewer. Looks ok'ish.So I suggest to go through it once again.Regards,Janne

author: McPete
author_rank: Regular Contributor
timestamp: August 15, 2011, 11:55:23 pm
content: Ah, found it: I hadn't changed the "&"s to "," in defining the bcdout signal.However, I'm now getting this;"Error: Top-level design entity "Project1" is undefined"What does that mean?P.

author: tinhead
author_rank: Super Contributor
timestamp: August 16, 2011, 12:33:12 am
content: Quote from: McPete on August 15, 2011, 11:55:23 pmgo to Files tab in navigator, select the file which is defining the top level (e.g. decoder.vhd),right click on that and chose "Set as top-level entity" ...

author: McPete
author_rank: Regular Contributor
timestamp: August 16, 2011, 01:07:21 am
content: That was it! Awesome! Thankyou all, I'm on my way!