Ground planes, loops and traces - Page 1
Forum section: electronics / general

author: Helix70
author_rank: Unknown
timestamp: August 15, 2024, 04:06:18 am
content: I understand that the return current on a trace wants to follow the trace when returning on the ground plane as the inductance/impedance of the loop is the smallest this way.If I have 3 copper layers, the top one with horizontal traces, the middle a ground plane, and the bottom one with vertical traces (that cross the horizontal traces), will the return paths on the middle copper layer be disrupted if all the traces have signals (digital and/or <1KHz AC) at the same time?Do the trace currents that cross act like there is a slot in the ground plane?Does the return signal tend to run on the surface closest to the trace and is thus mostly unaffected?Does something else happen entirely?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 15, 2024, 05:47:52 am
content: You seem to be asking about two different things:1. Image currents follow the trace, at frequencies where impedance dominates; the trace looks like a transmission line as such. For typical inner-layer planes, this is in the low MHz and up. The ground plane is an effective shield at these frequencies, and top and bottom currents are independent.2. Low frequencies flow through the ground, along the path of least resistance. Inductive reactance is too small to contribute to current flow, and the plane is transparent to currents, magnetic fields, etc. Mind, "transparent" in relation to its resistance, which might still be low -- but just that, whatever that voltage drop is, it's perceptible on both sides of the plane.For typical PCB materials, the crossover is in the 10 to 100kHz range. For example, copper traces are effective shunt resistors below 10kHz -- not that the tempco or manufacturing stability is really worthwhile anyway, but if nothing else, this more or less precludes its use as sense resistors for switching circuits, for example. Or for another application, PCB material is an effective susceptor for induction heating in this range; at lower frequencies, it's too transparent and not much heat is dissipated, and at higher frequencies, inductance dominates and it becomes a better shield than absorber.Or for another related circumstance: audio signals lie in the <20kHz range, where coaxial cable shielding loses effectiveness. No matter how low the resistance of the cable's connectors might be (plain, gold plated, whatever), there will still be voltage drop across the cable shield if a ground-loop current of such frequencies flows through it (say in the loop between two audio components and earth). Mains frequency and harmonics being a common issue here.The same does not occur at radio frequencies, where the cable shield is effective and, if the connectors have low resistance and the shield coverage is high, signals can flow with high immunity to outside interference. That is, the shield has effectively divided the cable into interior (signal) and exterior (common mode) currents, separate by whatever magnitude of isolation the system has (it can easily be >100dB).Tim

author: selcuk
author_rank: Frequent Contributor
timestamp: August 15, 2024, 07:10:33 am
content: Considering skin effect may be helpful here. Although 1kHz is very low for practical copper thicknesses, high frequency signals and high frequency components of digital signals will be effected differently than low frequency signals. When the skin depth is considerably thinner than the inner ground plane thickness for a given frequency, top layer return currents will flow on the top surface of the inner plane and bottom layer return currents will flow on the bottom surface of the inner plane. Thus the inner plane acts like there are two inner ground layers.https://link.springer.com/chapter/10.1007/978-3-031-14186-7_10

author: Helix70
author_rank: Unknown
timestamp: August 15, 2024, 11:14:49 pm
content: Thankyou, that is a good explanation. My takeaway is that having separate ground planes for the analog signals and digital signals will mean the voltage drops from the pulsing digital signals will appear primarily on the digital ground (the decoupling cap and supply for the digital source is connected to digital ground plane) and the analog signals (with their supplies and decoupling caps connected to the analog ground plane) will be somewhat isolated, and less affected. The analog and digital ground planes connected at a single point.My intended stackup is as follows:Top - components with ground fill (minimal traces)L2 - GroundL3 - Signals (digital and analog) (routing mostly running vertically)L4 - Analog GroundL5 - Signals (digital and ground) (routing mostly running horizontally)Bottom - Ground and test points (minimal traces)My theory is that the digital traces on L3 will return on L2, analog traces on L3 will return on L4, analog traces on L5 will also return on L4, and digital traces running on L5 will return on L6. Any thoughts?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 15, 2024, 11:54:06 pm
content: I wouldn't bother with 6 layers, unless you're doing something that needs the density -- lots of pins to route.Separate ground planes are their own issue, and likely a bigger one. Any small voltage drop between them, at that point of joinery, is beamed directly into space using the PCB as some variation of dipole or bowtie antenna. Let alone if there are wires attached to either side of that join.Worse still, this assumes there's no signals that need to cross between domains. You can't just run a digital trace up to a, say a analog mux on the far end, no, the displacement current flowing into the far section of the trace, and the pin input capacitance, has to follow the trace all the way back up to the source. Except you've run it over a slot between ground planes, and now you're coupling that energy into that slot, and the wings of the plane generally.In 99.9% of cases, split planes are a bad idea, or unnecessary given better layout options. In that small remainder, it does find use, separating analog and digital currents, or generally noisy and sensitive / low-level sections (might be digital, SMPS, high-level analog, RF, etc.).From a learning and development standpoint, split planes are ONLY something you use, once you know how to do a basic layout, you know what ground planes are, what they do, how to use them, and you've studied and exhausted all remaining possibilities that differential signaling, sectional layout, stitched planes, etc. can offer. Only then, you use split planes, and only then will you be prepared to handle all the issues surrounding them: crossing traces have to be coupled or filtered to manage signal/return currents, how to handle common mode voltages, attach connectors, etc.Tim

author: Helix70
author_rank: Unknown
timestamp: August 20, 2024, 04:30:37 am
content: Thanks.Does that mean it would be better not to have a separate analog ground, and just have top and bottom grounds that are stitched together with lots of vias and have both analog and digital signals return on the respective top or bottom layer ground? I chose the top and bottom layers to be ground to try and limit the effects of external noise.If only having one ground for the system, the 4 layer stackup could be:Top - components with ground fill (minimal traces)L2 - Signals (digital and analog) (routing mostly running vertically) - unused copper filled with 3.3V planeL3 - Signals (digital and analog) (routing mostly running horizontally) - unused copper filled with 3.3V planeBottom - Ground and test points (minimal traces)Would that be a better choice?Josh

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 20, 2024, 08:24:49 am
content: The most common stackup is the other way around.Top: Footprints and tracks. (Both signals and power)L2: GNDL3: GNDBottom: Tracks, footprints, testpoints, whatever suits the project.There are a few reasons GND is on the inner layers. The most important is that there are no pads from footprints on the inner layers, and thus the GND planes are uninterrupted, except for via's poking through the PCB. Rows of via's that generate large interruptions in the GND plane are bad, via's should be spread around a bit so GND connects in between them. Pads are also already on the top layer, so routing tracks on the top layer does not need via's. If you transfer tracks to another layer, then all tracks would have via's and this would take up a lot of board space, and lower the quality of the GND planes. Rework and repair is easier with more of the tracks visible (black solder mask is a nuisance)Quote from: T3sl4co1l on August 15, 2024, 05:47:52 amThat used to be the common assumption. Recent video's I saw (among them Robert Feranec) suggest that the effects start at much lower frequencies, and that at around 2kHz to 6kHz the impedance is already by far the dominant factor. There are several video's complete with field solver simulations on youtube.Power planes are becoming less common, power is often routed as (fat) tracks too. The goal is to maintain the GND plane, and coupling of signals with the GND plane.Rick Hartley has posted a 2 hour and 19 minute video about proper GND planes. It is worth watching at least twice (with a few months in between). That indicates how important GND planes are.I suggested two (uninterrupted) GND planes in the stackup. Reason is that prepreg is much thinner (0.1mm?) then the PCB core (1.2mm?) and the closer proximity provides for better coupling, and thus less EMI. When you use via's to get signals to the other side of the PCB, then there should also be a via connecting the two GND planes at that location, so the return path for the current can also follow the layer change. Again, there are field solver simulations on youtube (Again Feranec) to show how this works.4-layer PCB's are still a sort of compromise, and you may run out of room to run the tracks. It is usually OK if a part of the tracks are put on the internal layers, but you have to be aware to not cut your GND planes into little pieces.If power planes / zones are used, then they may also require their own decoupling capacitors, just like IC's. The goal is again to provide a smaller loop area for the return current. The high frequency content of signals goes through a decoupling capacitor just as easily as through a via. Impedance of a 100nF capacitor is less then 2 Ohms @ 1MHz.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 20, 2024, 08:57:32 am
content: Quote from: Doctorandus_P on August 20, 2024, 08:24:49 amIt's not an assumption -- it's easily calculated. To what it applies, is a matter of context though. Specifically, the higher frequencies are where skin depth is less than the thickness of the foil, thus having significant shielding effect, separating currents into top and bottom sides.You can understand a sheet conductor below skin effect (= is at least partially transparent to magnetic fields), as a reduced-dimensional skin effect system. That is, you still get the effect of skin effect, in the remaining dimension(s), at a rate determined by the effective resistance of the sheet.That's probably not very clear without a diagram, or further explanation, so let me give an example.Consider a wide symmetrical stripline (parallel plates) geometry. Let fs1 be the cutoff frequency associated with skin effect through the sheet, its thickness direction; and fs2, widthwise.For f > fs1, current flows on the facing surfaces. More current flows towards the edges, particularly the facing corners where the magnetic field between conductors is spreading out into the fringing fields beyond them. But current doesn't go deeper into the material or anything; again, depth is determined by skin effect. This is the normal and well understood case.Below fs1, current flows through the bulk of the sheet, from direct face to the far edge. The full conductor is utilized, though current is still not uniform: current flowing through the center for example, has a magnetic field around it that induces an eddy current in the nearby layer, and so on and so forth; this pushes current out towards the edges, so there is still more current flowing at the edges than in the center. As you can see, the magnitude of this effect depends on the sheet resistance of the conductor: the wider the conductor is, the better shielded the center, say, 10 or 50% or whatever, of the conductor is, from the edges, and thus the lower current density flows there.The distribution then, is to have more current flowing at the edges than in the center, and this is characteristic of the mid-frequency behavior. It's not that no current can/will flow in the center; the sheet is still transparent to magnetic field so a complete magnetic loop can be made around any given bundle of current flowing along the sheet. But current is still pushed out to the edges, and how strongly, depends on frequency and resistance.Below fs2, current flows essentially uniformly; magnetic field spreads out evenly across the sheet, and so also current density, and we have the DC case (more or less).For the ground plane case, consider an infinite sheet with a microstrip trace above and below it. Suppose we have a coupled-microstrip geometry, where they are routed apart at some distance, then come together (overlapping i.e. on top and bottom layers, but still separated by the middle ground plane), then diverge again. There is some coupling between the two traces, depending on length of overlap, frequency, and thickness of ground plane. (And, I suppose, all the other geometric factors: transmission line impedances and all that. Ultimately it's going to be something like, the ratio of transmission line impedance to plane resistance, right? We always expect reasonable separation of currents, even at DC, but only finitely so is the point, whereas as f --> infty, we expect infinite attenuation.) This geometry will depend on fs1, but not fs2. (Or, perhaps better to say: there is no fs2, or at least, an obvious datum to use for calculating it! Maybe there's a cutoff associated with the length dimension of the overlap region, I'm not sure exactly. If there is, I suspect it's a minor term, not a proportional frequency cutoff kind of behavior? Or we could use wide microstrips and use the trace width as above, but that's kind of a separate thing -- note that Zo will also be *much* lower in that case too.)Another example geometry: suppose you have two connectors (SMA or whatevr) placed in the middle of the board, separated by some distance. Suppose there is a single microstrip trace connecting between them, but not in a straight line but rather taking a square 'C' shape of equal width and height. At DC, ground-return current takes a direct line through the plane, with current density distributed according to the usual -- whatever it is, a complimentary parabolic-hyperbolic pattern I think? Anyway, mostly straight line, but fanning out a bit, particularly in the middle. At high frequencies (f > fs1), current follows the trace. At intermediate frequencies (fs2 < f < fs1), it's a mix of both -- where fs2 is given by the distance between connectors. Or perhaps more accurately, the distance between trace and DC-preferred current paths?I haven't watched the video in detail, but I expect he's used a set of illustrations showing several (or all) of the above cases.I gave the upper cutoff range, because that's the range important to what I was talking about -- crosstalk for traces above/below. Where ground-loop voltages along quasi-DC paths may be an issue, one must also take account of the lower cutoff, or more importantly, handle both cases responsibly for any f < fs1, since these cases aren't really very specific and sharply-defined, it's a slowly (~sqrt(f)) varying continuum between cases so you really just need to handle the general case properly. Or, put another way, the specific high-frequency case can be treated more simply (in terms of return current path) than the general (AC/DC) case.Tim

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 20, 2024, 10:21:53 am
content: Long story, did not read it all, but it looks like were talking about different things here. You are talking about skin depth, while I had in mind the overall route of currents though a GND plane. For DC, this is the path of least resistance, while at a few hundred Hz, to 1kHz, the loop impedance start becoming important.I searched youtube for a few minutes to try to find a video which shows how return current in the GND plane changes with frequency, but could not find a good video with field solvers in that time.I did find the video below, which is likely a good discussion about general layer stackups.