Nexys4 DDR ADC -> UART - Page 1
Forum section: electronics / general

author: SAI_Peregrinus
author_rank: Contributor
timestamp: June 12, 2017, 12:45:51 pm
content: What I'm trying to do: Use a Nexys4 DDR board (Xilinx Artix-7 FPGA XC7A100T-1CSG324C) to capture analog signals, do some processing on them, and output the resulting data over USB. The dev board has an FTDI FT2232 onboard, wired for two-wire serial communication. The FPGA has a built-in ADC module, which Xilinx calls XADC. I'm using VHDL because I have somewhat more experience with that than with Verilog. This is part of a project for school, so using a language my advisor / instructor knows well seemed like a good idea.At this stage, all I want to do is take data from the XADC and send it out the serial port.I'm not sure how to simulate this thing properly. The ADC never seems to do anything, so the UART never gets started. This has made debugging the issue difficult.The code I'm using for the UART is mostly hamster_nz's example code with comments added and style changes to make things easier for me to understand.Xilinx's XADC documentation isn't entirely clear to me. I think drdy_out indicates that data is ready, and do_out contains the data word output. Since I'm running the ADC in continuous conversion mode with the channel sequencer and 4 channels enabled, the documentation seems to indicate that it should cycle through the channels, output data when each conversion finishes, and indicate which channel it came from on channel_out. I don't think I should need to manually change channels by writing the channel address to daddr_in, but I'm not sure on this.Can anyone help? This seems like it should be simple, but Xilinx are masters at making the simple complicated, and I'm apparently amazing at overthinking things and going in circles...I've attached a file with just the sources and not the generated mess Vivado spews out.

author: hamster_nz
author_rank: Super Contributor
timestamp: June 12, 2017, 08:54:02 pm
content: Have a look here if you want:http://hamsterworks.co.nz/mediawiki/index.php/Minimal_XADC_design- it just reads one channel over and over.You most likely want to use EOC or EOS as a strobe (not to sure about this - I'ld have to check the manual)

author: hamster_nz
author_rank: Super Contributor
timestamp: June 13, 2017, 09:29:19 am
content: Had a quick sim... first issues, both in main.vhd:(Style, no real difference)Code:constant clk_rate : unsigned(31 downto 0) := to_unsigned(100000000,32); -- 100000000, for 100 MHz clock.constant baud_rate : unsigned(31 downto 0) := to_unsigned(9600,32); -- 9600 baudActual fault - not setting bit-tick or updating countCode:bit_tick_proc: process(clk)beginif rising_edge(clk) thenif count = clk_rate/baud_rate-1 thencount <= (others => '0');bit_tick <= '1'; -- << Addedelsecount <= count + 1; -- << Addedbit_tick <= '0';end if;end if;end process;

author: hamster_nz
author_rank: Super Contributor
timestamp: June 13, 2017, 10:21:32 am
content: You may also need to connect "den_in" to something that isn't always asserted (simulation fails with a DRC check):Code:adc : ....den_in => bit_tick, -- was '1', this will read the XADC register 9600 times a second.....You can then use the pulse from the XADC's data ready (drdy) to start the Serial TX transmitting:Code:uart_tx : .....data_en => drdy,....Page 74 of the XADC user guide (https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf):QuoteIs that looking any better?

author: hamster_nz
author_rank: Super Contributor
timestamp: June 14, 2017, 08:58:19 am
content: Hi,Attached are the project files...* It is for the Basys3* The main file includes a slightly different - it has the baud generator set to 115200 baud, and is set up to read the XADC temperature.* The UART converts the 16 bit values to four ASCII bytes, and appends a NL and CR character, so you can see it in the serial console session. Because it is send back-to-back you need have the console open before you program the FPGA or you might not get the framing correctly and get what looks to be garbage.Sample output (with my finger on the FPGA):Code:9C369C469C489C569C8C9C689C9A9C5A9C609C3CThe upper 12 bits are the temperature (eg 0x9c3). Transfer function (fromhttps://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf) isTemp = (value * 503.975)/4096 - 273.15= (2499* 503.975)/4096 - 273.15= 34.3 degrees CWith the finger off it read around 0x998 (29.05 degrees C) - note this is the die temp.