intel Atom, confused: wasn't RIP in 2016? - Page 1
Forum section: electronics / general

author: DiTBho
author_rank: Super Contributor
timestamp: May 05, 2025, 10:34:27 pm
content: I see there are *brand new* Google Android/x86 Zenfone2 around.Powered by intel Atom.Asus ZenFone2, Intel® Atom™ Z3580@2.3GHz, 64-bitAnd, on the intelwebsite, Atom is still listed, with new stuff.QuoteBut, didn't intel stopped developing them due to the challenges of competing with radio integration and idle power consumption?!?Quote(Wikipedia ...)Last time I read anything about it, Intel did drop Atom chips for mobile devices in 2016.But it seem they continue to produce Atom processors, primarily for embedded and edge computing applications.And, again, still phone?!? w_h_a_t?

author: abeyer
author_rank: Frequent Contributor
timestamp: May 05, 2025, 11:26:39 pm
content: Quote from: DiTBho on May 05, 2025, 10:34:27 pmThat phone is ~10 years old.

author: Whales
author_rank: Super Contributor
timestamp: May 05, 2025, 11:32:21 pm
content: QuoteZenfone 2 is from 2015and its Z3850is a 2014-era 22nm chip.Did you have a different phone/chip and copy-pasted the wrong names?"Atom" is just a name and it has been 10 years since they ditched it. The N100 and N95 from a few years ago might occupy a similar niche to the "Atom" name. I'm not sure about their idle/sleep power draw, maybe that's not good enough for phones.I want to find out more technical info about these new SoCs (I wonder if they're in-order exec like atoms were traditionally. Maybe re-using "efficiency" cores from bigger models? Or a completely different outside-house fab process?).

author: brucehoult
author_rank: Super Contributor
timestamp: May 06, 2025, 01:54:54 am
content: "Atom" is just a marketing name. Now the same series of cores is called N100, N150 etc and also "E" cores in 12th and later gen. Some chips have a mix of P and E cores (e.g. my i9-13900HX laptop has 8 P cores, 16 E cores) and some have all E cores (the aforementioned N-series)

author: DiTBho
author_rank: Super Contributor
timestamp: May 06, 2025, 01:43:47 pm
content: ok, so they sent me an ad for a 10 year old phone ...and since I don't follow intel or the world of phones, the whole thing got me totally confused-anyway it's absurd that intel still uses the "Atom" trade-name,because it only generates confusion!Atom doesn't even have a good reputation behind it!I never understood why it didn't work, I know it wasn't really a complete SOC,and the fact that you have to add other chips for the peripherals meant poor energy optimizationbesides this I don't know why a 10 years old Atom consumed more in idle than an ARM of the same era,nor why standby mode worked less efficiently than the ARM competitionI am writing just right now procedure in assembly + C/89 to manage standby on Xscale PXA270when the chip is in suspend, the clock goes down from 400Mhz to ~2.8Mhz, and it consumes 30mWattI can disable USB, CF, IRda, whatever, execpt the gpio keyboard, well ... the "key" to "resume" from "suspend"I never understood why out-of-order execution meant higher consumption, with the benefit of better performance.I never understand anything with intel....

author: Whales
author_rank: Super Contributor
timestamp: May 06, 2025, 08:42:12 pm
content: That's because "Atom" is not aimed at you, the consumer. It's aimed at OEMs who know it means "low-power low-cost SoC".FWIW Intel has mostly ditched the name and I am yet to see much or any info about this new processor. They might rename it.QuoteDid they have remotely similar runtime performance? I thought it was only in recent years they gained parity for a few models.QuoteMore features and transistors = more power loss, simple as that. Out of order exec keeps other parts of your chip busier too, so other parts work harder.

author: brucehoult
author_rank: Super Contributor
timestamp: May 07, 2025, 01:58:55 am
content: Quote from: DiTBho on May 06, 2025, 01:43:47 pmBecause a 5-stage in-order CPU is very simple. It needs to keep track of five decoded instructions, moving through pipe stages in order. (three actually, as the first two stages are fetch and decode, with three execution stages).An out-of-order CPU has to use many times more transistors/gates to keep track of far more instructions that haven't been run yet, to have an output register for each instruction, to keep track of which other instructions each instruction is waiting for. To assign instructions to execution units. Etc etc.The original Pentium Pro in 1995 kept track of 168 instructions and had 144 FP registers and 160 integer registers. Compare that to the 8 actual integer registers and 8 entry FP register stack in the x86 instruction set and that had to be implemented in the Pentium, 486, 386 etc. The OoO CPU suddenly needs 20 times more.In the Arm world A72 keeps track of 128 instructions, as does the A76. The A78 does 160, and the Cortex X1 keeps track of 224 instructions. Apple's M1 has over 600 -- the don't publish a number but 3rd party testing has come up with a number like 624.In the RISC-V world, the THead C910 keeps track of 192 in-flight instructions, while SiFive's P550 keeps track of 96.If you are keeping track of 100 to 600+ in-progress instructions then it is extremely important to have almost perfect branch prediction, because most code has on average one branch every five or six instructions, so you can be having to predict 20 or 100 branches ahead of actual execution. If one of those predictions turns out to be wrong then you have to throw everything away and start again, at huge expense in wasted work. So you need to also use a lot of transistors for branch prediction including branch history tables etc.In practice a good dual-issue in-order core such as Arm's A55 (and successors A510, A520, A530) or SiFive's U74 can come acceptably close to the performance of a small OoO such as the A72 while using a small fraction of the transistors and energy.

author: ejeffrey
author_rank: Super Contributor
timestamp: May 07, 2025, 02:44:47 pm
content: Quote from: DiTBho on May 06, 2025, 01:43:47 pmSo ad targeting works better than I thought...QuoteThe atom processors were never a good match for phones but the higher end ones were pretty successful in low end netbooks/chromebooks and embedded systems. They could never match the perf/Watt of arm processors. The higher performance chips provided significantly more performance than what Arm could offer at the time along with x86 compatibility, yet could still be passively cooled. This was their niche and continues to be the niche of the N-series branded products that replaced the atom name.As for intels brand strategy: yeah it doesn't make sense to anyone. Celeron, Atom, and Pentium(-M) were all used for various low end processors and it was often hard to tell them apart. I think now all three names have been completely discontinued.

author: DiTBho
author_rank: Super Contributor
timestamp: May 07, 2025, 04:46:32 pm
content: Quote from: brucehoult on May 07, 2025, 01:58:55 amThanks. Very thorough.Another issue, at least with MIPS-R10K, is that OoO and speculative cause serious cache coherence problems.When an instruction is speculatively considered a "good candidate for execution", if that instruction is a load/store then the operation is pushed on a IO queue, so that if branch prediction fails, the operation is removed from the queue, but this cache effect is not undone.I double checked the manual, and that's exactly what I observed on my MIPS-R10K board.The solution to this problem comes with R12K, at the cost of increased on-chip complexity: solved internally the chip.I think Alpha did the same, I think. Dunno about ARM.For R10K, there were two approaches:Workstations and servers designed for R4K (which is neither OOO nor speculative) and then updated to R10k (the CPU is on a module, you can replace it), simply introduced numerous software barriers on critical code.(linux never worked well here)All the new R10K designs (I mean motherboard) added external circuitry, just near the cpu module, to trace the pipeline and correct cache state.So .... in addition to shadow registers, and all the very complicated circuitry to manage them, you also need more intelligent IO code and circuitry to monitor the cache and pipeline, and fix speculative execution messesit gives me a headache...