World's worst QFN - Page 1
Forum section: electronics / general

author: Daixiwen
author_rank: Frequent Contributor
timestamp: July 01, 2019, 07:42:52 am
content: I remember a while ago seeing this twitter post on the world's worst QFN ever:https://twitter.com/whitequark/status/1106970233485561858I had a good laugh back then, wondering who would be masochist enough to use that....Well guess who is going to implement that component on a PCB now...

author: Ysjoelfir
author_rank: Frequent Contributor
timestamp: July 01, 2019, 09:45:10 am
content: Don't forget to add the cry for help or some kind of ragequit on the silkscreen layer. Right above the "Detail B" arrow line would be sufficient space. But remember to mirror the text - this is the bottom view.

author: coppice
author_rank: Super Contributor
timestamp: July 01, 2019, 09:47:19 am
content: I guess a BGA could be considered the world's worst QFN.

author: Ysjoelfir
author_rank: Frequent Contributor
timestamp: July 01, 2019, 09:58:20 am
content: I would prefer to create a footprint of more or less any standard bga over THAT thing. A BGA is usually at least consistent in spacing and pin numbering.

author: ataradov
author_rank: Super Contributor
timestamp: July 01, 2019, 05:40:05 pm
content: This seems like it is designed for easy fan out. It is annoying to create the footprint, of course, but you only have to do that once.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: July 02, 2019, 06:45:32 am
content: It's an application where we can't use BGA's. It's a very low volume PCB and with very expensive components so we'd better get it right on the first try!It's probably designed this way for easier fanout but there are still a few things I don't get... some differential pairs (but not all) use an oblong pad for one of the signals, and a round one for the other one. And there are 38 unconnected pads. Because of course.The pin used to hold the chip in powered down state is called COMA_MODE. Probably a good description of the layout engineer when he is finished creating the footprint!

author: Berni
author_rank: Super Contributor
timestamp: July 02, 2019, 07:33:23 am
content: Quote from: blueskull on July 01, 2019, 10:18:20 amAnd when i thought those dual row QFNs ware evil here you show me a tripple row QFN.Attached is what blueskulls evil chip looks like.

author: daqq
author_rank: Super Contributor
timestamp: February 04, 2020, 07:44:41 am
content: This is becoming silly. At some point we're gonna have to add another package name to the list, namely "Other", "Arbitrary" or "Because f*ck you, that's why!".

author: RoGeorge
author_rank: Super Contributor
timestamp: February 04, 2020, 08:13:17 am
content: Rookie complain, those chips were meant for vertical mounting.

author: babysitter
author_rank: Frequent Contributor
timestamp: February 04, 2020, 08:54:58 am
content: Pure pr0n.

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: February 04, 2020, 09:21:07 am
content: Who did that vertical mount? the technician is pure genius

author: nctnico
author_rank: Super Contributor
timestamp: February 04, 2020, 09:55:34 am
content: Quote from: RoGeorge on February 04, 2020, 08:13:17 amThat is pure art!

author: mariush
author_rank: Super Contributor
timestamp: February 04, 2020, 09:58:32 am
content: re the image in first post... it looks bad, but in reality it's not THAT bad.If you pay attention you'll notice it's mirror image (left and right sides, top and bottom), with just some pads being elongated to be 2x the size or something like that.So you only have to get a quarter of that footprint done and then mirror it twice and then extend some pads and you're done.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 04, 2020, 10:21:35 am
content: Worst one I've used, not all that bad but still worthy of an appropriate library name:3D view in situ:https://www.seventransistorlabs.com/Images/AltiumPlacement.pngTim

author: Nominal Animal
author_rank: Super Contributor
timestamp: February 04, 2020, 10:43:08 am
content: Quote from: RoGeorge on February 04, 2020, 08:13:17 amI am at loss for words.

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: February 04, 2020, 10:46:24 am
content: Quote from: T3sl4co1l on February 04, 2020, 10:21:35 amThis one is still OK. Looks symmetric and organized. Not like the random pins of various sizes placed at arbitrary locations. Someone has to be given a nobel prize for these kinds of pinout.

author: Rerouter
author_rank: Super Contributor
timestamp: February 04, 2020, 10:51:50 am
content: I can handle the really weird pinouts, I hate the stupid assignment of some chips much more,Oh, you have a 16 bit port left exposed, intended for interfacing to external memory, LCD's or similar, Why... why do they split those pins up as much as humanly possible. the I/O is sequential, so why is this function shotgunned around the pinout... or serial ports with RX half the chip away from TX....

author: exe
author_rank: Unknown
timestamp: February 04, 2020, 10:57:15 am
content: Do you guys draw these components by hands? I wish manufacturers release components as well. To me it feels quite a waste of time and effort to try to replicate what was already done.The worst part for me is to calculate sizes and distances when only a few dimensions are given. There is also a risk of doing it wrong.

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: February 04, 2020, 11:01:03 am
content: Most component manufacturers provide footprint data in multiple format these days. So that makes life easier...One thing I have learnt from QFN parts with different sized pads is that if the centre pad is very large and if the solder paste on that pad is not split into different sections, there is a finite risk of the outer pads not making contacts. This is due to the surface tension of the molten solder causing the package to lift up.The best option is to split the QFN centre pad to smaller pads so that the footprint can also be split.That makes soldering reliability much better.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: February 04, 2020, 11:03:03 am
content: I suspect the reason they don't (always, some manufacturers do release footprints) isa) everyone uses different standards and methods of drawing components. So even if they do release components a lot of people don't use them. I have this issue with schematic symbols mostly - some people like drawing schematic symbols as one big block, others like splitting them up. How do you think you should split them up? What pitch between pins? What grouping? etc etcb) You can't always support every single package out there.c) footprints tend to change based on technology too - soldermask openings, pad size, hole sizes, how you do your silk, etc.Quote from: exe on February 04, 2020, 10:57:15 amI do wish the vendors gave me a list of coordinates for each pad sometimes - would be real convenient. What is even worse is if they give all values, but in the 'wrong way' so I need to do the math to convert it to the way I need to imput the data into altium footprint generator or whatever.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: February 04, 2020, 11:18:29 am
content: I suspect another reason they don't give ready made footprints is that they don't want to be held liable in case of manufacturing problems.I wonder too how the central pad will affect soldering of the other pads, especially with so many rows all around.Worse case, we finish the soldering process with a heat gun and a hammer

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: February 04, 2020, 01:16:16 pm
content: Well mine is minor compared to some of these examples, but I was forced to re-spin a board because I used the TPS7A4700, which comes in a QFN20 - with 0.65 mm pad spacing instead of the usual 0.5 mm.Oops.

author: GeorgeOfTheJungle
author_rank: Super Contributor
timestamp: February 04, 2020, 01:22:45 pm
content: FAB: Do you want additional interconnect layer(s)?client: No, thanks.FAB: Ok, don't move the pads around then.client: fine.Routing that isn't gonna be any worse than say, any Intel bga, no?

author: ebastler
author_rank: Super Contributor
timestamp: February 04, 2020, 01:47:15 pm
content: Quote from: RoGeorge on February 04, 2020, 08:13:17 amWe had this picture before (https://www.eevblog.com/forum/chat/qfn-dead-bug/msg2338626/#msg2338626), but I have not figured out the original source yet. Google image search finds various Twitter posts and other obscure channels. "PS3 hacking" is mentioned somewhere. Does anyone know where/when/why/by whom this was done?Edit: Ah, this seems close to the source:https://www.psdevwiki.com/ps3/Syscon_Hardware

author: Berni
author_rank: Super Contributor
timestamp: February 04, 2020, 03:34:19 pm
content: Why don't chip manufacturers make CAD libraries? Cause its not so simple to do.Yes there are importers that will convert files between different CAD tools but the result is usually horrible and needs a good bit of manual fixing to make it exactly like a natively drawn symbol/footprint. There can also be some specifics about it, such as wave soldering optimized footprints. There are also sometimes certain styles of footprint design people like.. etc. When it comes to schematic symbols you might even draw them slightly differently depending on the use for it.Tho some do it. For example Wurth Elektronik has Altium libraries for everything and i love it since they are actually well made and include 3D models and everything. Pretty useful stuff since weird inductors or special connectors can be annoying to draw.For chips i don't really care anymore. Altium does a good job of making the process pretty quick. The chips are created using the built in standard IPC footprint generator where i just have to feed in some measurements and out pops a footprint complete with 3D model. When the chip is too funky to be supported i just chose the most similar chip type and then edit it manually after it auto-generates. So as long as the chip is not something like the horrendous abomination that the OP posted then i can make a footprint in a minute or two in Altium.Similar goes for creating the symbol. For 6 pin chips placing the pins manually takes almost no time at all. When the chip has 100s of pins then i copy-paste the pinout table from the datasheet to excel, clean it up there and the copy paste the excel table into Altium so that it generates the pins for me automatically, all i have to do then is arrange them in a sensible way around the symbol. What gets me furious tho is when the datasheet presents the pins in a weird messed up pin table format that explodes into a mess of ASCII characters as soon as its copy pasted out of the PDF file. Tho FPGA vendors typically give you the pinout in excel format to begin with so its super easy to copy paste into Altium.I still spend more time making my schematic look pretty than i spend making component libraries. So as long as the manufacturer gives me a easily copy pastable pinout table and a clear easy to read package drawing im happy (Tho quite a few don't).

author: thm_w
author_rank: Super Contributor
timestamp: February 04, 2020, 10:12:17 pm
content: Quote from: Berni on February 04, 2020, 03:34:19 pmSure, but you don't have to go all out. Could provide the pads drawn in DXF or equivalent common format and let people import it as needed. Have pad centers marked.Or could even make a STEP file of the package, as many connector manufacturers have now. I think I've seen a few.One issue is its no longer linked to the PDF. DXF/STEP/CSV embedded in PDF would be nice. Of course adobe has their own proprietary format, which is not relevant.

author: Berni
author_rank: Super Contributor
timestamp: February 05, 2020, 06:14:50 am
content: Quote from: thm_w on February 04, 2020, 10:12:17 pmYeah that would help with weird crazy packages.However as soon as the package is similar to anything standard i find that its faster to set up the Altium footprint generator wizard than it is to place everything by hand onto a pre-drawn guide. The generator also makes a pretty good looking 3D step model of the chip according to the given measurements so im not so concerned with actual 3D models from manufacturers, worst case you can approximate a QFN or BGA chip with just a rectangular box.But i have went this route before by importing the PDF drawing into Altium to use as a guide. This was only worth the effort when the thing i was drawing the footprint for was a huge pain in the ass to draw. (Getting a PDF into Altium is not quite so straight forward since it needs to go trough DXF as intermediate)Where i do need real 3D step models provided is connectors, buttons, enclosures... where the 3D model is actually of significant importance of figuring out if something will fit or is needed to design enclosure openings that fit. Some manufacturers STILL don't provide models for the stuff and this is what really annoys me. I have had cases where i was so desperate i started drawing my own model for a important part, but then found out i don't even have all the important dimensions from the drawing, so i had to use calipers on the physical part or scale the drawing to 1:1 and use it as a guide to guess missing dimensions.

author: exe
author_rank: Unknown
timestamp: February 05, 2020, 09:34:17 am
content: Quote from: Berni on February 05, 2020, 06:14:50 amI use different software, which doesn't have a wizard. So, I'd love to have ready components.When I looked at Altium's circuit maker, there was a large database of components linked to octopart or something. Every single thing I needed for my designs was there. I wish every EDA had such a database.

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: February 06, 2020, 12:51:51 pm
content: Quote from: exe on February 05, 2020, 09:34:17 amJust know that most of that content is community created and should not be trusted if you want a higher expectation that your design will be functional/manufacturable otherwise you may end up vertically mounting a QFN.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: March 18, 2020, 01:40:05 pm
content: And we got a prototype PCB!I still wonder how well this will solder, but unfortunately we won't be able to test this before a while.

author: thm_w
author_rank: Super Contributor
timestamp: March 18, 2020, 08:33:37 pm
content: Whats up with the no soldermask?

author: Daixiwen
author_rank: Frequent Contributor
timestamp: March 19, 2020, 08:19:46 am
content: It's a product that will go to space, so no soldermask or silkscreen allowed. This makes the soldering more challenging, especially with those vias around.

author: Fred27
author_rank: Unknown
timestamp: March 19, 2020, 08:51:20 am
content: I'd never header that soldermask and silkscreen weren't use for space work. Why is that?That also looks a bitch to debug with all the traces on inner layers.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: March 19, 2020, 09:56:01 am
content: A lot of materials are prohibited to prevent outgassing in the vacuum.My main concern with the soldering is that a good part of the solder will move to the vias and I don't know how much of it will stay on the pads.And if we get a solder bridge under there it will be fun to fix

author: asmi
author_rank: Super Contributor
timestamp: March 24, 2020, 12:42:47 pm
content: Quote from: Daixiwen on March 19, 2020, 09:56:01 amYou should've used via-in-pad to alleviate this problem - specifically copper-filled vias (as in resin-filled type a resin expands a bit more than copper and so pads can "buckle" a bit during extreme temp cycles). Since it's aerospace, a bit higher cost of that technology should not be a problem.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: March 25, 2020, 08:33:23 am
content: It's a "low cost" space project so we have to make some choicesEspecially with the cubesats now there is some demand for electronics that are resilient enough to go to space for a few years, but not as expensive as the full space grade thing.We do have vias in pads elsewhere on that PCB, but the vias for that PCB manufacturing process are bigger than the pads for that component.If it doesn't solder well we may have to do as you say and put vias in pads there too, but with vias this size it will probably be costly.I don't remember what the vias are filled with here, I'll have to check. IIRC another problem with resin filled vias for space is that if an air bubble is trapped in the resin, the via will explode when coming to the vacuum. Resins are also usually not allowed for outgasing reasons.