PCB layout - decoupling caps - Page 1
Forum section: electronics / projects

author: Grobalo
author_rank: Contributor
timestamp: November 19, 2014, 10:16:36 pm
content: Hi,This is my first board design, I'd like to build an iBeacon (a bluetooth low energy device that can be detected by smartphones). I've attached the schematic and my current PCB layout.I've programmed the bluetooth module and the circuit works fine on a breadboard but I'm not sure how to place the decoupling caps on the PCB. The moduledatasheetrecommands using 3 decoupling 1µF caps (C1, C2, C3) and a large buffer 100µF cap (C5) to compensate the internal resistance of the coin cell battery.I have 2 questions.1) I know that the C1 cap should be closer to pin 2. But is this cap really required since the battery holder pad is already next to the pin on the PCB?2) Does it make sense to have both C2 (1µF) and C5 (100µF) in parallel next to each other? Can I simply drop the C2 cap?Edit: forgot to mention that the GND net is in purple and the VCC net in orange. The bottom layer is a ground plane obviously.Thanks!

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2014, 10:35:37 pm
content: Placement looks fine for this kind off app. But make those supply (better all) routes thicker. Maybe C1 migh be placed a little closer to he BT module. (rotate 90 degrees, shift him upwards), place the VCC pad away. If it is not possible (coin battery holder footprint?) then it might be left that way. Maybe also rotate the C1 and the next one horizontaly, to shorten the Vcc track.

author: Grobalo
author_rank: Contributor
timestamp: November 19, 2014, 11:37:45 pm
content: @YansiI'll make the routes ticker.I've choosen a through hole battery holder because the SMT version doesn't fit the pcb area. And I can't rotate the BLE module because of the antena. It should be in the corner with a clearance area on the ground plane. See attached image.But what about C2 1µF and C5 100µF which are in parallel and close to each other. Does it make sense? I'm tempted to simply remove C2.Thanks

author: kxenos
author_rank: Frequent Contributor
timestamp: November 20, 2014, 12:05:44 am
content: I also agree that it's better if you have thicker tracks as stated. Also, I would try to have each GND pad with it's own via to ground. The via should be as close to the pad but not right on the pad. Also, the key about decoupling caps in each power input is to minimize the loop resistance between the cap and the pad. Therefore I would place the cap as close to the + pad as possible. Also, it's better if the +V goes first in the cap and then to the + pad. The 100uF cap should be close to the input, before the separate pads and caps. Also since you have 2 +V inputs, why don't you use 1 for the module and the other for everything else?On the other hand, I don't think this design is so critical that every single rule of correct decoupling needs to be applied, for it to work.

author: Charles Creations
author_rank: Contributor
timestamp: November 20, 2014, 02:54:03 am
content: The previous posts have offered good solutions. I just wanted to answer your question about the parallel capacitors of different sizes. For your case, its the 1uF and the 100uF capacitors in parallel. The key here is the Equivalent Series Resistance. Generally, larger capacitances have a greater Equivalent Series Resistance, so the advantage of the smaller capacitors (1uF in your case) is they can provide energy more quickly then the 100uF variety while the 100uF ones can provide energy for a greater duration. This effect is much more pronounced when you are using large electrolytic caps and small ceramics in conjunction. Like mentioned before, your application isn't super sensitive.