How to hook up 4 SDRAM chips to the SoC chip? - Page 1
Forum section: electronics / general

author: technix
author_rank: Super Contributor
timestamp: August 06, 2017, 07:01:28 pm
content: This is about my AT91SAM9260 system. I have found someone selling MT46LV64M8A2 chips, thus allowing me to deck the SAM9260 out with its maximum supported 256MB of DRAM. The memory is arranged in a 32-bit wide bus, with each memory chip providing one byte of the interface, but share the same address and chip select line. Now is there any points I should be aware of when layering out the board, regarding the four memory chips? Keep in mind that the maximum bus speed here is SDR PC133.Also there is the mixed width bus problem: the bus is shared with three devices: the 32-bit wide memory, the 8-bit wide NAND chip, and the 16-bit wide display controller (RAIO RA8875.) What should I be aware of when wiring this thing up, with the mixed width bus in place?

author: nctnico
author_rank: Super Contributor
timestamp: August 06, 2017, 07:11:54 pm
content: AFAIK: recipy for dissaster. The problem with SDRAM is that both data and address lines are synchronous with the clock. DDR memory has seperate clocks for the data lanes which makes routing them much easier. In your setup the address lines will see a load of 4 (or more) devices while the data lines will have much less load.

author: technix
author_rank: Super Contributor
timestamp: August 06, 2017, 08:15:50 pm
content: Quote from: nctnico on August 06, 2017, 07:11:54 pmUnderstandable but there is no 2Gbit SDR SDRAM chips, and the 512Mbit ones are the largest still available. The SoC only have one SDRAM chip select, so I have to pile up the fanout to get memory in there.

author: technix
author_rank: Super Contributor
timestamp: August 06, 2017, 09:51:05 pm
content: Quote from: blueskull on August 06, 2017, 08:54:14 pmI have this SAM9260 project idea for a while, and there is a package constraint that no BGA or QFN allowed. If I am okay with BGA I would go straight for MT6797 (MediaTek Helio X20) which is a PoP package and a good performer. I am aware of the RDA chip too but BGA. (I actually bought the Allwinner V3s which comes in eLQFP128 with Cortex-A7 MP1 and 64MB LPDDR2, but it is a separate project.)

author: nctnico
author_rank: Super Contributor
timestamp: August 07, 2017, 07:33:19 pm
content: How about using an SDRAM dimm module? These are dirt cheap and have termination resistors on board.

author: marshallh
author_rank: Unknown
timestamp: August 07, 2017, 10:23:55 pm
content: For vanilla sdram you'll be fine. 4 chips, just route the cmd/addr/clk in a tiered tree fashion and you'll be completely fine.

author: technix
author_rank: Super Contributor
timestamp: August 08, 2017, 05:17:41 am
content: Quote from: nctnico on August 07, 2017, 07:33:19 pmI cannot find one. And those comes in 64 bit wide bus which is not supported by my chip.

author: technix
author_rank: Super Contributor
timestamp: August 08, 2017, 07:16:20 am
content: Quote from: marshallh on August 07, 2017, 10:23:55 pmHow to do this? And what about the data lines and the termination resistors?

author: nctnico
author_rank: Super Contributor
timestamp: August 08, 2017, 08:31:41 am
content: Quote from: technix on August 08, 2017, 05:17:41 amConnect the 32 bit you don't need with resistors (47k Ohm) to ground. Problem solved.

author: legacy
author_rank: Super Contributor
timestamp: August 08, 2017, 09:22:59 am
content: Quote from: nctnico on August 08, 2017, 08:31:41 amYup, good trick, it worked for me, too.