Being lazy with decoupling capacitors? - Page 1
Forum section: electronics / projects

author: rea5245
author_rank: Frequent Contributor
timestamp: February 14, 2012, 02:17:07 pm
content: Hi,I'm wiring up an STM32 microcontroller. It's in an LQFP and each side has a Vss and Vdd. Each Vdd needs a 100nF decoupling capacitor and the docs say to put it as close as possible (one of the Vdds also needs a 4.7uF cap).And yet, if I look at the layout of the STM32-Discovery board (http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/USER_MANUAL/CD00267113.pdf), ST themselves don't seem to be obsessing over that "close as possible" stuff. It looks as if they've clustered all four decoupling capacitors next to each other on one side of the uC.My question is, once you've put four 100nF caps physically next to each other, and they all go to the same ground, and each Vdd that's wired to them is also connected to +3.3V, what's the practical difference between those four caps and a single 400nF cap? In short, I'm looking for an excuse to save real estate and be lazy with my decoupling caps. I suspect the professional EE answer is "don't do that", but I don't understand why.And while I'm on the subject, one of the Vdd pins needs both a 4.7uF cap and a 100nF cap. How is that different from a 4.8uF cap? Sure, they don't make 4.8uF caps, but that's only 2% different from 4.7uF. Given the tolerances of most caps (+/-5%, +/-10%) what's the real-world benefit of putting a 100nF cap in parallel with a 4.7uF cap?Thanks,Bob

author: JuKu
author_rank: Frequent Contributor
timestamp: February 14, 2012, 02:44:26 pm
content: High frequency impedance. The 100nF or 4.7uF are DC values, at 500MHz the impedance is what counts (and the whole purpose of the decoupling). The recommendations are like that so most people would get it about right with typical available parts. The real spec is something like <1.5 ohm complex impedance at 100-600MHz, but it is much harder to pick capacitors by that. It is hard to get wide attenuation range with one capacitor, so that is why they recommend two different types. That is also why they want to caps close to the pins; the impedance of the track from the pin to the cap is (very) significant. On a larger cap, they want attenuation in the lower frequencies, so the effect of the track smaller. Therefore, you get by with one - it is going to be ok from the farthest and nearest pin to the big cap. But not so on the high frequencies, and that is why you want to have a cap on each supply pin.

author: cybergibbons
author_rank: Frequent Contributor
timestamp: February 14, 2012, 03:02:34 pm
content: It's not strictly true, but the way I think of bypass caps is as follows:The little ones are to take high frequency noise to ground.The big ones smooth dips in voltage.So you need the combination of the two.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: February 14, 2012, 03:37:53 pm
content: If you only have one place for them there's little point putting more than one.The 'near the pin' requirement differs significantly if you have a 4-layer PCB, where the ground/power planes have low enough impedance to relax the need for caps close to every pin.As 1uf ceramics are so cheap these days, if space isn't tight I default to these everywhere, which avoids the need for larger bulk decouplers.Just need to make sure your voltage regulator is happy with the low ESR of ceramic caps.

author: rea5245
author_rank: Frequent Contributor
timestamp: February 14, 2012, 04:10:59 pm
content: Thanks to all for your replies so far.mikeselectricstuff, I don't know how many layers the STM32-Discovery has, but I'd be surprised if it were four. It's not that complex a board and they're selling it for only ~US$10.Since the LQFP is 7mm and they've put all the caps on one side of the chip, one of the Vdds has its cap about 1cm away. Is that "far"?And are you saying that in their layout, they would've been OK with one 100nF cap instead of 4?- Bob

author: Unknown
author_rank: Unknown
timestamp: February 14, 2012, 06:03:58 pm
content: High frequency performance is mostly dictated by ESL (equivalent series inductance) and dielectric. ESL is determined by package size (smaller is better) and internal construction. Of course long, thin traces will add additional inductance. ESR may actually be beneficial, because it will spoil the Q of your circuit and dampen resonances.So the smallest package your assembler accepts, with a high quality dielectric, as close as possible to the pins is best for high-frequency. Value is almost insignificant at high frequencies, since inductance tends to dominate. Just a few hundred pF should be fine if your frequency of interest is 500 MHz.You can easily find a 100pF capacitor as high quality NP0 dielectric in very small SMT packages. The 100 nF cap will probably be somewhere in between. Your 4.7 uF capacitor will probably use an inferior dielectric and be bigger, hence an inferior high-frequency performance. 100 nF is actually the old, standard value developed in the days of slow TTL logic. It's not ideal for modern high-frequency circuits, but their use is still common. One informative appnote on this topic is TI SLOA069. I believe Howard Johnson has also written about this topic.I believe Janne (jahonen) posted some measurements on this topic. I think his conclusion was that it's easier to get good results with several caps of the same value as opposed to different value caps, but I don't remember the values he used.

author: jahonen
author_rank: Super Contributor
timestamp: February 15, 2012, 10:19:23 am
content: It is important to notice that it is the supply impedance that particular IC sees that is important, not how it is achieved. One can use whatever is desired to get lowest impedance.I have seen so many "correct" mixes of bypass capacitors that I think that there is quite large solution space, otherwise there would be many more miserable failures if things were so critical. I know that many application notes and datasheets have different opinion, but I encourage everybody to make experiments and see which way works better. Reality is the ultimate judge, not appnotes or opinions.Above self-resonant frequency, all capacitors are inductive. This means that regardless of the capacitance, the inductance sets the impedance above SRF. Because inductance is determined by the magnetic field loop area, capacitance value does not matter, only physical construction. So it is pretty much the same at higher frequencies whether you use 100n, 10n or 1µ capacitors if they have same inductance (same physical size and connection geometry). But having a big capacitance means that the supply impedance stays low even at lower frequencies. So like Mike told above, using something like 1µF as local bypassing often removes the need to add bigger centralized capacitor.I don't recommend paralleling different capacitors (small ones in particular) unless one is sure that the resulting inevitable parallel resonances (high points in impedance) aren't harmful and impedance notches occur at correct frequencies. Blind application of random values can cause more bad than good. If all values are the same, then doubling the amount of capacitors will drop the impedance by half, at all frequencies. With different values, some frequencies will be worse than before.My present understanding of ideal way would be to have a capacitors with a quite high ESR (say 10 ohm or so) and then parallel a large number of those, even with different values of capacitances. Large ESR would dampen out the parallel resonances while combined impedance would drop. That way, we could indeed achieve a wideband bypassing.I believe that EMC expertBruce Archambeaultmade experiment with different capacitors and arrived to same conclusion.Regards,Janne