Lower resolution position adjustment on higher resolution display? - Page 1
Forum section: electronics / general

author: smoothVTer
author_rank: Regular Contributor
timestamp: April 29, 2017, 03:39:29 pm
content: I am working with a thermal camera which outputs a 1.8V CMOS, 640x480 16-bit YCbCr formatted bitstream. I have to display this image centered on a panel which is expecting an 800x600 16-bit YCbCr formatted bitstream. Because the panel is expecting 800x600 resolution, the image from the camera is displayed off-center and cut off.What is the easiest way to process the original data in order to add black pixels to the top/bottom/left/right of the image to achieve an 800x600 input into the panel?I know this can be done in an FPGA, but the learning curve is STEEP. Does there exist a video processor or some other IC which accepts YCbCr and outputs formatted YCbCr? Note that I am NOT looking for resolution scaling ... I am looking to simply center the 640x480 original data onto an 800x600 display, with black bars at the edges of the image. The actual area of video displayed will still be the original 640x480.

author: Bill W
author_rank: Super Contributor
timestamp: April 30, 2017, 10:00:15 am
content: Why do you say 'cut off' is this a 600x800 panel, not 800x600 ?If so that is a rotate and you are into FPGA-memory-fieldstore territory, or accept losing 20 pixels each side and black top & bottom with the display still rotated.If it is a landscape display then you need to work out the LCD timing system, and intercept this to lie to the panel so the data gets clocked in & displayed where you want it.Once you know what you are dealing with, there's two options:If it is 'line and field' trigger you are on a winner as you can simply trigger new lines when you need to with a bit of logic.If it is 'reset and clock' I'd expect you to be in a bigger mess already as the display would be displaying the start of camera line 2 at the end of display line 1.I'm assuming there is no padding options on the core output data ?Bill

author: smoothVTer
author_rank: Regular Contributor
timestamp: April 30, 2017, 05:35:39 pm
content: Thank you for respondingUnfortunately the core I am working with does not have any pixel padding settings available at this time. I might try to push the manufacturer for a firmware update to allow this, but they are typically slow to make revisions so for now I am tasked with an external solution.Here's a diagram of what I see on my display panel:I know that those pixels are "cut-off" because the display itself has the capability to shift the image +/- 12 pixels in any direction and when I shift either down or right, new valid pixels appear on the top & left. However 12 pixels just isn't enough to fully center the video data. What I can't figure out is why the display seems to start drawing a new frame outside the active pixel area ... the lower-left corner of the active video is actually outside the 800x600 active pixel area. This YCbCr bitstream is in 4:2:2 format with separate HSYNC, VSYNC, DATA_ENABLE and PIXEL_CLK signals. Signal fidelity on the PCB looks good on the scope on all lines, PIXEL_CLK is a bit rounded off but setup and hold times are within spec.