100MHz LNA - Page 1
Forum section: electronics / beginners

author: Bidski
author_rank: Newbie
timestamp: May 24, 2015, 07:39:34 am
content: Hi All,I am looking at designing a low noise amplifier for a radio receiver for a university project. The radio needs to operate at around about 100MHz.I have come across a MOSFET cascode LNA circuit that uses a MOSFET current mirror for biasing. I have attached a picture of this circuit.My issues are this, I will need to build the radio that I design and so I am trying to source some low noise MOSFETs that are readily available and I am having trouble finding any. The only ones I can find will take at least a week to ship here. However, I did manage to find some low noise JFETs.My issue now is that I am not sure how to analyse circuits with JFETs in them. Can I just take the circuit that I showed and replace the MOSFETs with JFETs? Or are the other concerns that I need to account for?I have been looking around for information on JFET current mirrors, but so far I have found nothing at all. Is this because JFETs are not well suited to this task?Best RegardsBidski

author: tggzzz
author_rank: Super Contributor
timestamp: May 24, 2015, 08:06:00 am
content: Quote from: Bidski on May 24, 2015, 07:39:34 amIn general, no you can't.Before you get to the "subtle" parameters, you will need to check the bias conditions, polarity, and enhancement/depletion characteristics.

author: VK5RC
author_rank: Unknown
timestamp: May 24, 2015, 08:22:25 am
content: This Ham has some pretty serious lna, a recent 140MHz design is on his websitehttp://www.g4ddk.com/The HP/Agilent /Keysight Application Note on noise factor measurement Y factor etc is pretty good.

author: Bidski
author_rank: Newbie
timestamp: May 24, 2015, 08:30:30 am
content: Quote from: tggzzz on May 24, 2015, 08:06:00 amHmmm ok.Does anyone know of some low noise MOSFETs that might be suitable for this circuit?Quote from: VK5RC on May 24, 2015, 08:22:25 amI will have a look. Thank you.Best RegardsBidski

author: German_EE
author_rank: Super Contributor
timestamp: May 24, 2015, 09:39:23 am
content: If you're building something that needs a really low noise figure then pay attention to your power supply. A 78xx regulator isn't good enough as it will introduce additional noise into the circuit and you will get better results using a standard 723 regulator chip. There are of course low noise regulators these days but as your time is limited the 723 is easier to obtain locally. Use lots of decoupling plus maybe a series power choke and build your circuit on a ground plane that is seam soldered to a case all the way around.

author: VK5RC
author_rank: Unknown
timestamp: May 24, 2015, 12:24:28 pm
content: I am in the process of trying to bounce a radio signal off the moon EME ( it has been done by many) it needs lots of RF grunt, a really good antenna and a really low noise pre-amp. For this ends I have built and tested one of G4DDKs LNA. I have measured sun noise using it, so it seems to be working OK.It uses the MGF4919 GaaS FET . With quite a bit of trial and error using the Y method and an old HP Noise meter 8970A (with 436A noise source) I got the Noise Factor (at 1296MHz) down to 0.27dB for a gain of about 35dB. Picture below. The FET is mounted up in the air (held up by small inductors) adjacent to the input SMA in the bottom left of the photo.

author: f1rmb
author_rank: Regular Contributor
timestamp: May 24, 2015, 12:34:21 pm
content: Use a PGA103, search Google for a publication from F1JKY, you'll find measures, PCB drawing an so on.Cheers.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 24, 2015, 03:18:59 pm
content: Quote from: Bidski on May 24, 2015, 07:39:34 amYes but:You need different biasing, which this circuit could stand a change in, anyway.The first transistor is statically biased, "diode mode", so that it develops a voltage corresponding to how much Vgs is necessary to draw the applied drain current (from the 1k resistor). This voltage is coupled to the bottom transistor, so that it gets the same Vgs, and give or take variation in Id vs. Vds (shouldn't be much), it will carry the same current (i.e., a MOS current mirror).This works great when the transistors are matched and thermally coupled (as on an IC), but may not work out so well in practice. The transistors at least need to be a matched pair. Since accuracy and power level are not big problems here, thermal matching probably isn't a big deal either (it should be good enough that they're on the same PCB). It's still not the greatest, and wastes a transistor anyway.I'd rather do it by replacing the transistor "reference" with a simple voltage divider. This is even worse (there's no reference to Vgs at all!), but we do one better by adding an R||C in the source of the bottom transistor. Vg is set such that it's a bit above Vgs(th), and so load current is drawn, causing voltage drop across the source resistor, which reduces Vgs -- negative feedback sets the bias point. The bypass cap ensures the source still "looks" AC-grounded as far as the signal is concerned.The L-C-L network is a big question, of course. If nothing else, that has to be tuned for the operating frequency. It probably also needs to be tuned for the impedance match (the gate has a fairly high impedance, even at RF). You can solve for that, but it requires having S-parameters or admittance data in the transistor's datasheet; and it'll most likely be different in practice anyway, needing adjustment. The gate L and C should be the most important there; the source L seems out of place, and might be intended to be very small (a fraction of the other L), with the purpose of adding negative feedback at AC or something like that.Converting this to JFETs means providing Vgs somewhere between negative and 0V (instead of positive), which would stink for directly grounded source -- but in practice, we simply bias the gate at GND and add enough source resistance to let it self-bias again. It's also acceptable to run a JFET at zero gate bias, at least as long as the input signal isn't too strong. The top transistor should have a voltage divider biasing its gate (with bypass to GND), so its Vg is maybe 20-50% of supply. Source voltage will rise above Vg, so that it again sets Vgs by feedback (but Id is still set by the bottom transistor; it's important that Idss of the top transistor be higher than Id of the bottom transistor).As for "low noise", a cascode might not be ideal, because it basically throws away the gain of one of the transistors -- the main advantage to the circuit is nearly eliminating reverse transfer (gain from output to input). When modest gain and absolute lowest noise is required, it might be better to use a single transistor (common-source or -gate). One advantage of a JFET is, the source input impedance (in common-gate) is fairly modest (it's roughly 1/Gm or Rds(on), which for most will be within a small factor of 50 ohms), and it doesn't need any biasing (again, it can be ran at Vgs = 0). Output impedance essentially gives the gain ratio, so a higher impedance load (100s ohms to a few k) is needed to obtain gain. Which means a matching circuit (LC or wideband transformer is fine).BJTs are good too. I forget which (BJT, JFET or MOS) is strictly best at 100MHz -- of course, if you need every last dB of noise factor, you can always go with a GaAsFET or PHEMT. Just be careful to use teensy ferrite beads to prevent it from oscillating at stupid-GHz...Tim

author: Nuno_pt
author_rank: Frequent Contributor
timestamp: May 24, 2015, 03:28:32 pm
content: Look at LNA4All from 9Q4 guy,http://lna4all.blogspot.pt/,it's cheap, or look at Sam G4DDK,http://www.g4ddk.com/for VLNA or PGA devices, or look at YU1AW,http://www.qsl.net/yu1aw/LNA/low_noise.htm.Or use some 50Ohm internal match device like PGA103, or PSA and run it on RFSim, then try it with Noise Figure meter like 8970A/B, to see the NF, or make one CANFI,http://www.canfi.eu/very cheap and results are like the best NF meters.

author: KJDS
author_rank: Super Contributor
timestamp: May 24, 2015, 05:54:14 pm
content: LNA design is an interesting area.If you design the RF match to get good S11 and S22 as you would when you weren't concerned about noise then the noise figure will be horrible. If you design the input matching circuit for optimum noise figure then the input match will be so horrible that you'll suffer nasty input match, with all the issues that that causes, and if you do either of the above with a modern high gain low noise pHEMT or FET then you'll almost certainly end up with an oscillator rather than an amplifier. Adding some resistance in the output can mean a decent compromise between a good input match for both return loss and noise performance.The reason that the G4DDK LNA has the transistor mounted in the air is to provide source inductance to give stability.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 24, 2015, 07:23:15 pm
content: Quote from: KJDS on May 24, 2015, 05:54:14 pmGot any examples? It was my understanding that the two conditions are not typically the same, but that they're close enough (+/- 50%) not to be a problem.Pathological cases like negative feedback pushing around the dynamic impedance doesn't count. (Common base BJTs might be a good example; the emitter is a low impedance to begin with, but a low base impedance combined with stray inductance typically makes it look slightly negative. Simple solution, add a damping resistor, and choose whatever match you like.)Tim

author: Electro Fan
author_rank: Super Contributor
timestamp: May 25, 2015, 09:55:48 pm
content: Quote from: VK5RC on May 24, 2015, 12:24:28 pmEME! This project idea has captured my imagination - Wow!! I'm going to start a thread (I'll put it in this "Beginners" forum since it came up here - although based on some initial reading it doesn't looks real "beginner.")Thanks for the idea! EF- After delving into it the post/thread is moved to the Projects, Designs, and Technical Stuff forum:https://www.eevblog.com/forum/projects/eme-earth-moon-earth-communications-48431/