Z80's PIO Strobe - Page 1
Forum section: electronics / projects

author: raphael3215
author_rank: Newbie
timestamp: August 19, 2024, 05:49:29 pm
content: Hello, This is my first time writing to a forum, so apologies for any mistakes. I've been designing and testing a homebrew Z80 computer, and I finally decided to attach the PIO chip for parallel input/output. I've come to a question about the design of the PIO which I have not found an answer in any of the documentation, and it is regarding the Strobe input in the ports. As far as I understood, every output in mode 0 of the PIO must have its data acknowledged by pulsing low the given port strobe when the device has finished reading the port. This is supposed to generate an interrupt, if enabled. Now, I assumed that, if the handshake is not made, the PIO would just ignore subsequent writes to it until the handshake is made, but that is not what I have observed. By setting the line low or high, the PIO latches any data that it is sent to it. Is there any documentation regarding this behavior, or am I messing something up?, is the strobe only purpose to generate an interrupt and it doesn't interfere in the data latching?

author: bson
author_rank: Unknown
timestamp: August 19, 2024, 07:19:32 pm
content: Well, the manual says "Ready stays active until the positive edge of the strobe is received, indicating that data was taken by the peripheral." It doesn't say anything about timing out, or giving up - only that it sits and holds READY until it sees a rising edge on STROBE# to acknowledge receipt. If your device never acknowledges the more reasonable assumption (which I think you checked) is that it will sit there waiting forever, or until cleared by software.Clearly this is intended for asynchronous transfer to a peripheral.

author: raphael3215
author_rank: Newbie
timestamp: August 19, 2024, 07:29:05 pm
content: Yes, I observed that, I will check the ready line with the scope later when I get home but it seems then my thoughts were incorrect in the working of the PIO strobe. Thanks for the answer.

author: Ian.M
author_rank: Super Contributor
timestamp: August 19, 2024, 07:32:55 pm
content: Possibly you've been looking at a different revision of the documentation.ZILOG Z80 PIO USER'S MANUALhas (on page 10):QuoteDisallowing further writes to the output latches till READY had been acknowledged by STROBE would have prevented Mode 0 being used for simple output without any handshaking + would have added silicon complexity and the need for extra bits in the mode word to determine whether or not handshaking was required. The designers chose not to do that, and simply settled for providing an interrupt, leaving it up to the programmer to manage the sequencing for handshaked data transfer or ignore it for simple bit-banged output.

author: bson
author_rank: Unknown
timestamp: August 19, 2024, 07:37:21 pm
content: I just looked at the datasheet athttps://www.zilog.com/docs/z80/ps0180.pdf

author: bson
author_rank: Unknown
timestamp: August 19, 2024, 07:39:48 pm
content: The data sheet says it latches to the output register on WR#. But nothing about updating it with additional writes. Isn't mode 3 for bitwise GPIO?

author: raphael3215
author_rank: Newbie
timestamp: August 19, 2024, 07:43:32 pm
content: Yes, this is definitely a different version from what I was currently using, thanks a lot for it, this answers my question perfectly. The bit banging part also makes sense, I implemented a simple driver for a 1602 LCD using the 4 bit control mode using a d-latch and I was thinking I would have to build an additional circuit just for providing the strobe for the PIO, glad for now it is not the case for now . Thanks everyone again for the help

author: raphael3215
author_rank: Newbie
timestamp: August 19, 2024, 07:44:50 pm
content: As far as I read, the strobe signal is completely ignored in mode 3

author: Ian.M
author_rank: Super Contributor
timestamp: August 19, 2024, 08:06:22 pm
content: Quote from: raphael3215 on August 19, 2024, 07:44:50 pmThat's how I read it as well.I *suppose* the designers could have made bit-banging in mode 0 impossible by gating writes to the output latch as you initially expected, leaving mode 3 as the only bit-bang capable mode, but that would have needed more silicon, in an era when designers still taped out their IC layouts by hand considering the cost of every extra gate.Seehttps://en.wikipedia.org/wiki/Rubylith

author: raphael3215
author_rank: Newbie
timestamp: August 19, 2024, 08:09:55 pm
content: My still only remaining doubt is that, if a rewrite happens without the strobe, will the ready line go low then high again during the rewrite, as in, any indication that the data is changing, I'd assume yes, since it has a delay for the write to happen where the port is not ready for reading.

author: raphael3215
author_rank: Newbie
timestamp: August 19, 2024, 08:11:26 pm
content: Also, the PIO doesn't have a WR# line, only a RD#, How does It receive then the WR# from the CPU?

author: bson
author_rank: Unknown
timestamp: August 20, 2024, 07:12:11 pm
content: Quote from: Ian.M on August 19, 2024, 08:06:22 pmSince they have to hold READY there's already a flip-flop for it presumably (or an SR latch/JK or something). And since neither READY or even WR# to the holding register are used in some modes (e.g. input), there's probably already a bit of logic around it? Who knows what that looks like... maybe it ends up masking WR# if READY is held active.