"buy cheapest fpga board you can find"  - i struggle to find tutorials (ISE) - Page 1
Forum section: electronics / general

author: GrandTheftAuto4life
author_rank: Contributor
timestamp: August 10, 2020, 10:50:51 am
content: Hello. I have a few xilinx spartan 6 boards and I haven't been able to find good tutorials for ISEMy boards has a FTDI chip, 64MB flash (W25Q64BV) and a high IO count.FPGA P/N is XC6SLX9-2TQG144C (50MHz ext. clock)Code:139 140 126 127141 142 123 124143 01 116 12102 05 114 11506 07 111 1123V3 GND VIN GND08 09 104 10510 11 101 10212 14 99 10015 16 97 9817 21 94 9522 23 92 9324 26 87 8827 29 84 85GND VIN 3V3 GND30 32 82 8333 34 80 8135 40 78 7941 43 74 7544 45 66 67Switches: 132, 131LED: 138, 137, 134, 133, 120, 119, 118, 117USB: TX:51 RX:55Extra: (unpolulated connector)47, 56, 58, 61, 62, GND46, 48, 57, 59, 144, 3V3I can generate IP cores like an I2C bus and etc but I can't find a way to access them nor a good "blink" example.Furthermore the included examples are confusing. In the "PWM led" example which fades 4 leds in/out then switches to the other set and do the same thing.There is barely any commentary and 5 of the 8 leds are being set with a ~ tilde sign. If it was four it might make sense, but it's 4+4 so that's not making things more clear.I've seen something called MicroBlaze and while it looks good at first glance it doesn't feel right jumping into that boat immediately due to various restrictions (and i'd probably get fundamentals wrong).I'd rather work closer to the metal with Verilog. But I'm sure where to begin.Eventually I would like to turn one of them into a pretty dumb i/o expander over i2c/spi with an internal row-column scanning for select pins

author: rstofer
author_rank: Super Contributor
timestamp: August 10, 2020, 01:52:52 pm
content: Do you have a .ucf User Constraints File that maps the signal names to the device pins? Such a file gets the signal to the device pin, you still need to mentally map where that pin shows up on the headers.The abbreviated file below should give you some ideas. Every signal that appears in the top level PORT statement must appear in the .ucf file. From what little I know about Verilog, these signals are in the top module definition. If it isn't there, ISE assumes the logic isn't used and removes every last shred of it from the netlist. It's pretty easy to have a lot of abandoned logic.Code:NET "CLK_PAD" LOC = "B8";#NET "Reset" LOC = "H13" | TIG;# Buttons<3>#NET "Buttons<0>" LOC = "B18" | TIG;NET "Buttons<1>" LOC = "D18" | TIG;NET "Buttons<2>" LOC = "E18" | TIG;### Printer Serial Port#NET "PrinterRTS" LOC = "A4" | TIG;NET "PrinterCTS" LOC = "B4" | TIG;NET "PrinterRx" LOC = "C3" | TIG;NET "PrinterTx" LOC = "C4" | TIG;NET "CLK_PAD" TNM_NET = "CLK_PAD";TIMESPEC "TS_CLK_PAD" = PERIOD "CLK_PAD" 20 ns HIGH 50 %;The CLK_PAD signal shows up at the top of the file and again at the bottom. It's been years since I worked it out but it works on a Spartan 3 and Spartan 3E.Here is a Spartan 6/ISE tutorial:https://bravelearn.com/blink-led-on-fpga-spartan-6-board-using-xilinx-project-navigator/The author is creating the .ucf file using the tools, I used an editor. This example uses a switch to control an LED. Next step up, bring in the 50 MHz clock, run it into a 25 bit counter and connect the LED to counter.TIG means Timing Ignore. It makes no sense to worry the synthesizer about timing external signals that are essentially asynchronous.Google for 'ISE blink LED', there are a LOT of videos.

author: prophoss
author_rank: Contributor
timestamp: August 12, 2020, 02:52:15 pm
content: I have a cyclone 4 chip attached to a board with a lot of peripherals. I use quartis prime IDE to load everything to the chip. I have not created a constraints file and I assume that I can. It is a cheap Chinese board. How does a constraints file help and what does it do exactly? Thanks Brian

author: rstofer
author_rank: Super Contributor
timestamp: August 12, 2020, 03:46:48 pm
content: The constraints file gives the tool hints about timing requirements that must be met as well as a mapping of the top level PORT signals (VHDL) to package pins. The subject is long and deep and there is a publication which is a very brief 319 pages:https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdfThe good news is that the file I posted above does most of what is required. It maps a bunch of pins to PORT signals and it defines the nature of the clock signal which, in this case, is 50 MHz and symmetric. I really don't recall the semantics of the last two lines and all I can say is that it works.I have never used the feature but apparently the constraints can also be entered using the Plan Ahead tool from within the IDE.The subject of FPGAs is so complex, at least to me, that once I have found something that works, I continue to use it. I don't look around for alternatives.The Xilinx Vivado Constraints File is a LOT more involved and far less intuitive (to me). It took a while to find something that worked. Now that I understand the syntax, things are getting a lot easier.All of the above deals with Xilinx ISE which is obsolete and no longer supported. I have no idea how things work under Quartus but, somewhere, there has to be a mapping of signals to pins and some kind of definition for the external clock.

author: mfro
author_rank: Regular Contributor
timestamp: August 12, 2020, 03:54:38 pm
content: Quote from: rstofer on August 12, 2020, 03:46:48 pmThat is correct for Xilinx, but not for the Cyclone prophoss asked about.With Quartus, the constraints (.sdc) file only contains timing constraints.With Quartus, location constraints are contained in the .qsf file and maintained from the Quartus assignment editor.

author: rstofer
author_rank: Super Contributor
timestamp: August 12, 2020, 04:03:33 pm
content: Timing constraints aren't included in my Constraints snippet above. If I had some kind of external SRAM, I might actually need to specify the access time so that the tool would know that the data wouldn't be available until some time after the address was registered. For the project that used the file, SRAM was handled by using a single wait state and timing became irrelevant, the extra 20 ns wait was more than the access time. I can imagine using DDR memory where timing would be much more critical.

author: prophoss
author_rank: Contributor
timestamp: August 12, 2020, 07:16:42 pm
content: That all makes sense, sort of anyhow. I am new to FPGAs and still learning how they work. When I use quartis I usually just set the pins in pin mapping but have never created a constraint file. That is why I asked about it. So far it has done what I asked it to do so I guess I will stick to what I know until I need more. Thanks y'all!