LTC3895 step down converter burns off - Page 1
Forum section: electronics / projects

author: Srijal97
author_rank: Contributor
timestamp: January 06, 2019, 02:52:24 pm
content: Hello all,We're a group of 3 undergraduates working on a 140V to 32V DC-DC step down converter using the LTC3895, with a current requirement of 6-7A nominal and up to 20A burst. Circuit simulations were done in LTPowerCAD and LTSpice and everything seemed alright.We went on to design the PCB following the guidelines for SMPS PCBs that we found online, mainly:https://micro.rohm.com/en/techweb/knowledge/dcdc/dcdc_pwm/dcdc_pwm03/2734The OVLO(Overvoltage Lockout) pin was used to set to 150V. EXTVCC was not used, but there is a MOSFET for NDRV. The picture of designed PCB and the Eagle files are attached below.We got all the components(major ICs from Digikey and others from local vendors) and assembled the PCB, and upon testing with 120V DC input, we had no output on the output side. After some time the LTC randomly blew up on the pin 30(Vin) pin with the magic smoke out. The 120V input DC supply was a really old one and was acting strange(voltage not changing smoothly when turning knobs) and we thought that might be the issue. So we assembled a new PCB with all new ICs. This time for the input, we used a step up module we had lying around to get 80V DC from a 48V SMPS. Even with the 80V input, the new board instantly had the same pin on the LTC blow up as soon as the input was turned on. A picture of the blown IC is attached below.At this point we think the following points might be the issue:- Both the above tests were done without any load attached on the output and we realised afterwards that this is not to be done for certain SMPSs. Is this an issue in this case?- The input ceramic capacitor C6 was not soldered because the ones we purchased had high ESRs of 1.45 to even 14.65 Ohms, and we thought that we'll wait till we find better capacitors.- The board layout. Even though we tried our best to follow the guidelines, this is a first for us and we expect some issues with it.Now, we have 2 more LTC3895 ICs left to try out and wanted to make sure that we have success with them. Any help would be greatly appreciated!Thank you for your time!

author: Miyuki
author_rank: Frequent Contributor
timestamp: January 06, 2019, 04:29:20 pm
content: And what other capacitors? C3 and output capacitors what was used during testOr was it powered without capacitors ? (then it must blow)And thenground layout > Ground bounceespecially as you take it from both sides, you need meeting ground point at switching node not far as you haveAre current sense resistors really calculated right ?

author: Srijal97
author_rank: Contributor
timestamp: January 06, 2019, 04:46:59 pm
content: Quote from: Miyuki on January 06, 2019, 04:29:20 pmThis was connected during the tests:C3 - 47uF, 250V; ElectrolyticC6 - not connectedC12, C13 - 22uF, 50V; ElectrolyticC14 - 150uF, 35V; ElectrolyticC15 - not connectedC8 - 0.47uF, 250V; CeramicThese were soldered on the bottom side of the board because we had plans for adding a heatsink later on.Quote from: Miyuki on January 06, 2019, 04:29:20 pmDo you mean that the GND trace from the IC to the GND pad is long? Can you please elaborate more on this?The current sense resistors have been calculated to accommodate for current limiting values a bit more than 20A as far as I know, though I'll get that verified. But that shouldn't have been the problem because there was no load connected right?

author: Miyuki
author_rank: Frequent Contributor
timestamp: January 06, 2019, 06:02:46 pm
content: Not sure how this control ic react to no load, but shall be okYou need to take ground from one point near switch as is in some schematics marked and look to some reference buck design for groundLike this modification or even better to have ground plane you have lot of space

author: Miyuki
author_rank: Frequent Contributor
timestamp: January 06, 2019, 06:09:33 pm
content: You have problem with this loops:

author: Srijal97
author_rank: Contributor
timestamp: January 07, 2019, 06:12:17 am
content: Okay I clearly see the problem with the GND in the blue loop, so I was thinking of this temporary modification(attached picture); removing some of the soldermask and soldering the stranded wire(about 20AWG) to that GND trace?We refrained from adding a GND plane because there are suggestions online to not to increase the copper area more than necessary to avoid picking up noise.Other than that, is the green loop looking fine?

author: Miyuki
author_rank: Frequent Contributor
timestamp: January 07, 2019, 08:23:04 am
content: Also check VCC loop a Feedback loop (feedback look like it take ground from other side)In green loop Bootstrap cap shall be some small one as close as possible (bodge some to pins)Then It may work I think

author: Srijal97
author_rank: Contributor
timestamp: January 07, 2019, 10:02:50 am
content: Quote from: Miyuki on January 07, 2019, 08:23:04 amThe feedback path wiring was done by referring to this page:https://micro.rohm.com/en/techweb/knowledge/dcdc/dcdc_pwm/dcdc_pwm03/4682, which has the following points:・The place for detecting the output voltage should be either across the terminals of the output capacitor or past the output capacitor: see (b) in the diagram・Lines from the output to a resistive voltage divider should be parallel and close to each other so as not to easily pick up noise: see (c) in the diagram・Wiring should be laid out far from the switching nodes of inductors and diodesI didn't connect the feedback path ground to the IC ground directly on purpose, thinking that it should only take the output voltages properly as feedback. But I'm not sure if that is correct...should I short the GND to a closer point now, externally?And the bootstrap cap has to handle high voltage ripples according to the simulations, that is why we decided to go with the large 250V rated ceramic capacitor.

author: capt bullshot
author_rank: Super Contributor
timestamp: January 07, 2019, 10:07:38 am
content: First of all, please provide your schematics and PCB layout in a "readable" format (e.g. pdf, or screenshot). I don't have SW to open your files, and I won't go search for it.Edit 2: found the .pdf, at least there's the layout, but the schematic would be useful also.So, that layout looks total crap (sorry, I don't intend to offend you, but it'll just won't work). Go and download all the documentation ADI provides for this chip, including the DC2117A manual and design files. They use a six-layer board to tame that beast. I don't think it's necessary to have a six-layer board, one should be able to get it working with a double sided board, but this requires a lot of experience to do it right in the first iteration. One must take care a lot of attention to the high power path, e.g. the high-side and low-side MOSFETs must be mounted close together and the switching node must have as short as possible traces between these MOSFETs, and so on ...Next, with these IC's it's very common to blow them up easily. In most cases, the reason for them to release the smoke is an overvoltage transient on one or more of their pins. And with such HV IC's, theres very little margin from working to blowing up. Such transients easily happen due to not enough input filtering or bad layout. Unwanted inductance (e.g. due to too long and narrow traces) cause "inductive kickback" by turning off the current, that may happen on the input side of the IC. The switching node might ring too much, that might cause overvoltage here.Another reason might be the inductor core saturating. This makes the current rise faster, even fast enough for the controller IC not being able to turn off the high side switch fast enough to prevent damage, or turning it off fast enough to save the MOSFET but causing a transient voltage at the input that in turn blows up the IC.In general, one wants solid ground planes, short and wide traces for the power traces and heavy decoupling at the input side. A ceramic cap alone here will ring with the inductance of the supply leads and blow up the IC at turn on, so always have a combination of ceramic (for low impedance decoupling) and electrolytics (for bulk energy storage and damping) at the input node.Edit: Anyway, where's the second MOSFET? Can't see one in the board photo.Edit 2: Now I can see it, looks way too small.

author: Srijal97
author_rank: Contributor
timestamp: January 07, 2019, 10:15:17 am
content: Quote from: capt bullshot on January 07, 2019, 10:07:38 amI do have the board file attached in pdf format in my first post, but here is the board and schematic attached as well.

author: Miyuki
author_rank: Frequent Contributor
timestamp: January 07, 2019, 10:20:49 am
content: Quote from: Srijal97 on January 07, 2019, 10:02:50 amThen is something horribly wrongBootstrap cap provide low impedance charge to gate, but have almost no loadSo where you get high voltage ripples ?It can be tricky as ringing at switching node can easy overcharge it to high voltage and then it blow driver and transistor

author: capt bullshot
author_rank: Super Contributor
timestamp: January 07, 2019, 10:46:20 am
content: OK, here we go again:The bootstrap cap is totally wrong. One would use a smallish ceramic cap here. There's typically seen 10V ... 15V across this cap, not the full input voltage.At the input node, I'd suggest a SMT ceramic cap, placed near to the MOSFETs (now I can see the real low-side FET, still looks quite small, often the low-side FET has to carry more losses than the high-side one. I didn't check your components.Your GND trace around the positive input to supply the IC is way too long and forms an nice loop that can cause all kinds of trouble, as others pointed out.I'd suggest moving the whole circuitry to the GND side of the power components (from right hand side to left hand side regarding your layout), and use a proper GND plane covering everything from input to output. Avoid vias within GND nets. It's would have been easy to rotate the HS FET within your layout by 90° to get shorter traces to the decoupling caps. For the DCR sensing traces from the inductor: keep them close together. Fill the space between + and - input (in between the pins of C3 / C6) with + input and GND planes, so you can solder SMT ceramic caps across the gap, but keep the electrolytic in place, consider adding another one or two of them.Some fine tuning (within the final circuit) can be achieved by inserting resitors into the MOSFET gate drive lines, by connecting a small value resistor (1R ... 22R range typically) in series with the gates, one can tune the switching times of the MOSFETS to reduce ringing and losses. Anyway, doing so requires a working layout first.Edit: forget about what I said regarding the small low-side MOSFET, I was reading your layout wrong due to the unusal arrangement of + input and GND in respect to the control IC. Anyway, rotating Q3 (which I now see is the low side FET) would be a good idea to shorten its power traces.So, IMO the root cause of the IC releasing the smoke is the poor GND layout, causing transient overvoltages. You might get it working by attaching a as short and wide as possible bodge from Q3 Source to the IC's center pad. But it'll still won't be a good design, better redo the layout.

author: Srijal97
author_rank: Contributor
timestamp: January 07, 2019, 11:06:13 am
content: Yes, the bootstrap was a terrible mistake on our end. Probing both ends of this capacitor shows that the voltage across it is actually just 10V and not the ripple we saw on just one side of it (attached simulation picture showing waveforms across cap).It appears that we will have to get new PCBs done now, but meanwhile, do you think we can perform one more run on the current board with the following changes made?- We'll remove the large bootstrap cap and add a 0805 ceramic close to the IC...I see vias where it can be soldered on the current board itself.- The GND trace problem should be resolved by adding the extra wire as indicated in a post above. Does the existing long trace need to be cut?@capt bullshot, how would small SMT caps be able to handle the 140V input if they're added across the + and - input gap?

author: capt bullshot
author_rank: Super Contributor
timestamp: January 07, 2019, 11:22:49 am
content: The SMT caps to handle the input voltage won't be small anymore, but still SMT. One can buy ceramic SMT caps rated for such high voltages, though they will be rather large and expensive. You've got a THT cap in your layout, a good film cap will also work here. Don't operate the board without proper input caps, or put some protection circuitry within the IC's power supply.I wouldn't replace the bootstrap cap, it's just ridiculously large but should work. Most important change would be the GND modification.If you have access to such equipment, use a variable output power supply to ramp up the input voltage slowly for the first tests, and observe critical waveforms (e.g. the switching node) with an oscilloscope. Be sure to use a very short grounding path for your scope probe, the usual ground clip supplied with the probe often is too long.

author: capt bullshot
author_rank: Super Contributor
timestamp: January 07, 2019, 11:35:13 am
content: Here's two examples of power stages / step down regulators I've done to give you some impression of how to do GND planes on a double sided circuit board:http://wunderkis.de/pvbat/converter.pdfhttp://wunderkis.de/dcdc/Test-LTC3775.brd.pdfhttp://wunderkis.de/dcdc/Test-LTC3775-2.sch.pdf

author: Srijal97
author_rank: Contributor
timestamp: January 07, 2019, 11:41:48 am
content: Quote from: capt bullshot on January 07, 2019, 11:22:49 amOkay, I will try and do that tomorrow...and let you guys know what happens.Quote from: capt bullshot on January 07, 2019, 11:22:49 amIt would be very helpful to see those...but the links don't appear to be working anymore? Also, what other resources would you suggest for these kinds of designs?

author: Miyuki
author_rank: Frequent Contributor
timestamp: January 07, 2019, 11:47:08 am
content: Srijal97: as you have your circuit in SPICE you can simple replace main traces with inductors and put in values from your layout (just convert length of traces to inductance) and you will see what is happening in "real" circuitIt might take little longer to simulate, but can provide fairly close results and show where is your main problemUse power of computer! We are not 50 years ago when you have just paper, slide rule and need to build many prototypes to do real measurement. Now you can simulate your layout within minutes (sometimes hours) and not wait days/weeks to build many versions and waste money. Even free or very cheap tools can do it today

author: Srijal97
author_rank: Contributor
timestamp: January 07, 2019, 11:50:43 am
content: Quote from: Miyuki on January 07, 2019, 11:47:08 amOh yes, that's a good idea! We'll try and do that too, thanks!

author: capt bullshot
author_rank: Super Contributor
timestamp: January 07, 2019, 12:56:09 pm
content: Quote from: Srijal97 on January 07, 2019, 11:41:48 amSorry, that was my fault. I've uploaded them here.Other resources regarding such designs would be e.g. datasheets and demo board manuals of other DC/DC controllers by LTC / Analog Devices and other manufacturers.They have better ones (datasheets and manuals) than this particular one, describing what is important in the layout. TI also has some good documentation, but it's not always easy to find. Sometimes stuff (like the noise you mentioned in your first post) is over-emphasized within some documents leading you in the wrong direction. The most important part of a good design is still experience, so it's quite normal to have your first designs fail, that's part of the experience gaining process. Second most important is to provide a massive ground plane to your circuit, usually it delivers better results than trying to divert currents to reduce noise coupling. Third is to reduce stray inductances along the traces where they really hurt in the first place. E.g. having a longer trace in series with the filter inductor isn't as bad as a longer trace from the MOSFETs to to input decoupling capacitor. The stray inductance in series with the inductor just increases its effective value a bit, but doesn't do harm in the first place. Stray inductance within the MOSFETs drain and source connections causes voltage transients that may do harm. Stray inductance within the GND connection of the controller IC causes its ground to bounce in respect to the power ground, leading to all kind of trouble. This is to get your circuit working.Then you look at the output switching noise, that's the point where you optimize your output capacitor and maybe add an LC filter.Next would be to reduce EMI, that's the point where you look at minimizing the loops and tuning the gate resistors, as seen somewhere above in this thread.Last would be to minimize output regulation induced noise, that is where you might think about splitting the ground plane. But if you've done everything right until here, this step won't be necessary anymore in many cases.

author: Srijal97
author_rank: Contributor
timestamp: January 14, 2019, 04:43:36 pm
content: Hello again,So during the testing with the modified board(extra GND wire and more capacitors), the LTC did not blow up but we had absolutely nothing on the output. We also probed Vout and the Switching node with an oscilloscope(But normal pen type probes, we did not have specialized ones) and saw nothing, a straight 0V line. The output changed from around a few mV to about 600mV upon increasing the input.We decided to completely focus on getting a new layout done, and I've tried to follow as many points given in this thread, application note 136 (June 2012) from Linear Technologies, and the DC2117A reference board layout. I've attached the new design with this post.In addition to improving layout, we worked on the selection of proper capacitors. For our last design, we simply bought local capacitors after referring to values that LTpowerCad showed. There was a lot of uncertainty in ESR values. We also had not realized the effect of high frequency that we are using(855 kHz). This time we followed this for the capacitor selection:https://www.powerelectronicsnews.com/problems-solutions/the-buck-regulator-power-supply-design-tutorial-part-2-1When calculated using formulae given in the tutorial, we found we needed a minimum input capacitance of about 0.7uF and output capacitance of 0.04uF. We also realized that using MLCCs for this purpose is useful and so made capacitor banks using MLCCs. In order to form these capacitor banks, it was suggested in the tutorial to add a bulk capacitor(electrolytic) with a bad ESR in parallel to damp oscillations and reduce ringing. It was also mentioned that a resistor can be connected in series with the bulk capacitor to increase ESR. We were having difficulty finding proper electrolytic capacitors whose values can be clearly defined(ESR value at our operating frequency of 855kHz and effective capacitance due to the DC bias effect due to the input voltage of 120V). We then simply used an MLCC capacitor and connected a series of resistance to it. Is this a good idea? As for our output capacitors, should we do the same or should we use an electrolytic capacitor as part of the capacitor bank?It would be great if I can get some improvements and comments before I place an order for manufacture, thank you very much for your time!

author: Srijal97
author_rank: Contributor
timestamp: January 14, 2019, 05:20:37 pm
content: Quote from: Srijal97 on January 14, 2019, 04:43:36 pmSo I noticed that the board pdf does not include the name of nets so I exported high-resolution images in Eagle and have them attached in this post. Sorry!

author: mvs
author_rank: Frequent Contributor
timestamp: January 14, 2019, 08:04:00 pm
content: Quote from: Srijal97 on January 14, 2019, 04:43:36 pmSense+ pin current is +/-1µA, resistance of your current sense divider 277K (280K||10Meg), this gives you current sensing error of +/-277mV.Current sense threshold is around 50mV (43-57mV), so guess why some of your ICs are blown and some do not start.Reduce resistance of your divider by factor 100 and increase capacitor C9 to 1µF.Next point are caps. You are trying to build 20A supply, there will be some ripple current, usually around 30% or 6A, perhaps even more. I have never seen a 22µF aluminum electrolytic cap that has ripple current rating of more then 0.5A. Look for low ESR caps, their typical capacitance range is 100-470µF and use more then one to split the current load. Put caps both on input and output.Ceramic output caps look also quite small. Are they in 0805 package? Why? Either they have very low capacitance, or they will loose most of their capacity with bias voltage above 15V. Go for the larger footprint (at least 1210), look for better material (X7R, X7S or at least X5R). Some caps may have "capacitance change vs DC bias voltage" diagram in datasheet, likeSamsung CL32B475KBJVPN, so you can compare their capacitance at desired 32V output voltage.And last but not least - please do not order PCBs with black soldermask for prototypes. It is very difficult to inspect and rework them.

author: capt bullshot
author_rank: Super Contributor
timestamp: January 15, 2019, 06:53:43 am
content: Some of your component values look wrong:C10 / C11 - typically one finds here a few pF or nothingR8/R7 - The datasheet states this resistor should be in the 2k ballpark. What's that R9? Looks pointless.You need an electrolytic input capacitor additionally to your ceramic ones. Placing an 100R in series with an 1u ceramic is pretty pointless, a typical value would be 0.1R to 0.5R, but this is not required if you have an electrolytic. Some 200uF are required here.Did you check INTVCC with your prototype?

author: Srijal97
author_rank: Contributor
timestamp: January 15, 2019, 05:00:48 pm
content: Quote from: mvs on January 14, 2019, 08:04:00 pmQuote from: capt bullshot on January 15, 2019, 06:53:43 amOkay yes, we messed up. We did not quite understand the current sense threshold and +/-1uA parameter and were happy to see the large values of resistors having low power dissipation allowing us to use 0805s. Now that it was pointed out(Thank you!), we spent some time figuring it out and it makes sense. Considering C9 as 1uF, R1||R2 comes out around 2.9k and so R1 is 3.9k with 0.8W max dissipation across it. I'll be adding a through hole with 1-2W rating and a vertical fold to save space. Also, R2 comes out to be 12k (which is R9 in my schematic, with earlier value 10M), so we need to put that in right? Or can you directly connect R1||R2 in place of R1, without R2? I have attached the calculations done from the datasheet, just in case.Quote from: capt bullshot on January 15, 2019, 06:53:43 amThose were the values suggested by the simulation...should I change those?Regarding the input caps, we hesitated with electrolytic ones because of the drastic loss in capacitance at frequencies of 800-900kHz...but I guess adding large values >100uF would get the effective value to the required range.And for the output, the required value came out to be very low and we did see DC bias graphs for KEMET MLCCs, so based on that we decided to go with 0805s with some of them rated up to 50VDC. But we'll change it to a larger footprint to get more options with the required voltage ratings and dielectric choices as suggested.Quote from: capt bullshot on January 15, 2019, 06:53:43 amNot yet, and it did cross out mind after the tests. We'll do it again tomorrow.Other than that, do the GND planes, switching node and overall layout look decent? Thank you very much for your support!

author: capt bullshot
author_rank: Super Contributor
timestamp: January 15, 2019, 08:10:00 pm
content: The numbers for C9 / R8 / R9 look plausible to me now.Layout looks OK now.C10/C11 - your arrangement looks unusual to me (but I didn't verify anything here), the datasheet suggests to not have C11 and treat C10 as optional. So one might first try without these.The inductor value of 4.7uH is rather low, expect large ripple and higher losses. In general your circuit looks quite tiny for your power goal (7A / 32V, up to 140V input). This is 224W output power, and optimistically assuming some 94% efficiency (may be better at low input voltage, worse at high input), your circuit will dissipate about 13W.So I'd recommend you to slowly increase input voltage / load and watch the power components temperatures.

author: Srijal97
author_rank: Contributor
timestamp: January 31, 2019, 07:11:40 pm
content: Okay so the new PCB was assembled yesterday and we did the testing today. We had a single oscilloscope of not-so-good quality and really bad probes, so we decided to connect it to just see the output voltage and not the switching node waveforms. The input voltage was given using 7*(12V, 30A) fixed output SMPS in series plus a 48V variable SMPS (set to 20V), also in series, giving a total of 104V. 3*(120Ohm, 10W) resistors were connected in parallel at the output as load, expected to draw a current of 0.8A. EXTVcc was used to power on the LTC3895 at 11.7V.The first test was done as follows, can be seen in this video here:https://goo.gl/LvMbk61- EXTVcc turned ON directly to 11.7V2- The Vin SMPSs turned on directly to 104V3- Output of 32.7V Mean was seen on the output (at least we have something now, yay!)4- Vin turned OFF5- EXTVcc turned OFF after a certain delay, at least 10-20 secsNow after this test we started everything up again with the same steps; EXTVcc first and then Vin, but we had just a tiny little bump in the output as seen in this video:https://goo.gl/RzePpP, and after that nothing, 0V. Since then, in the further tests, we have absolutely nothing on the output.What could have gone wrong? The main suspect right now are the input SMPSs. So we'll be using a 0-300V/2A supply and a thermal camera to observe the temperatures in some more tests tomorrow and try and measure voltages at specific points to know what went wrong. We'll also get a second board assembled and test that if this one does not work.Edit: I have added the latest schematic and PCB images as well. C10 and C11 were not added/soldered.