Driving the N-MOSFET Bridge in Pure Sinewave Inverter? - Page 1
Forum section: electronics / projects

author: KerimF
author_rank: Frequent Contributor
timestamp: June 18, 2023, 09:38:05 am
content: Let us assume that the MCU generates a suitable sinewave PWM to drive an N-MOSFET bridge.Let us call its four branches:‘HL’ (the High side MOSFET, at the Left side)‘LL’ (the Low side MOSFET, at the Left side)‘HR’ (the High side MOSFET, at the Right side)‘LR’ (the Low side MOSFET, at the Right side)During a half cycle, one of those 4 branches is usually turned on fully, as ‘HL’ for example. In this case, ‘LL’ should be off.My question is about driving the remaining two branches at the right side, ‘HR’ and ‘LR’.While searching on the internet, I found:Tahmid's blog: Sine Wave Generation with "Fast PWM Mode" of AVR - using ATmega16 (tahmidmc.blogspot.com)But I noticed that the way Tahmid drives the MOSFETs (fig. 5 Clear demonstration of the "deadtime") could be applied in case the bridge load is resistive only.As illustrated on fig. 5, right before the end of the half cycle the PWM which drives ‘LR’ reaches its off state. Then, ‘HL’ is turned off and ‘HR’ is turned on, simultaneously. During the following half cycle, the sinewave PWM drives ‘LL’.In case the load is inductive, at the end of the half cycle there is a lagging load current whose direction is from left to right.When: ‘HL’ only is on, the lagging current is shorted by the high loop thru the body diode of ‘HR’. ‘HR’ only is on, the lagging current has to flow from ground, thru ‘LL’ body diode, up to the supply voltage, thru Ron of ‘HR’. ‘HR’ & ‘LL’ are on, the lagging current is shorted by the low loop thru the body diode of ‘LR’.In the case , the current load is supposed to be shorted; equivalent to applying 0V on the load (the small forward diode voltage).In the case , the supply voltage should be applied on the load, not shorting the load.So, I think that, during  and , the load voltage will likely be deformed till the lagging load current is zeroed and the load current starts to flow in the right direction, from right to left. This will be repeated at every voltage zero crossing.I will try to draw an LTspice schematic to verify this.Meanwhile hearing any comment/remark will be appreciated. Thank you.Kerim

author: johansen
author_rank: Super Contributor
timestamp: June 18, 2023, 06:01:45 pm
content: Above 30 volts or so, you would not normally notice the 1volt lost across the body diode in the output voltage waveform, the non sinusoidal output at leading or lagging loads would only be slightly distorted.However, it is lost energy.Some inverters switch the lower two fets at 50 or 60hz and pwm only the upper switches.

author: KerimF
author_rank: Frequent Contributor
timestamp: June 18, 2023, 11:56:57 pm
content: Quote from: johansen on June 18, 2023, 06:01:45 pmYes, the distortion is somehow negligible when the supply voltage is relatively high as you said.Lately, I liked to build a pure sinewave inverter for 12V acid battery.For instance, I did a mistake on my previous post. The case  should be:When ‘HR’ & ‘LL’ are on, the lagging current 'also' flows from ground, thru Ron of ‘LL’, up to the supply voltage, thru Ron of ‘HR’Therefore, while the inductive lagging current is not zeroed, the reversed supply voltage (of the following half cycle) is applied on the load; no matter ‘LL’ is off or on. So, I expect to see a sort of voltage jump right after the end of a half cycle (at the voltage zero crossing).The solution is to turn on 'HL' when 'LL' is turned off (with a deadtime). By doing this, the load is shorted always by the high loop when the PWM signal is off. Naturally, this will somehow complicate the bridge driving.Quote from: johansen on June 18, 2023, 06:01:45 pmBy the way, I will likely let the load be shorted by the low loop (not the high one, as in the example I gave).Since I cannot get easily N-MOS driver ICs (as IR2110), I am designing the drivers by using discrete components, for the low side and the high side as well. And I will use the timer IC, NE555, to generate an independent supply voltage (not less than 10V above the battery voltage @20mA) for the two hi-side drivers.If you are interested, I will upload my work, as LTspice files, when it will be finished.Kerim