Datasheet Errors - Page 1
Forum section: electronics / general

author: ludzinc
author_rank: Unknown
timestamp: June 30, 2014, 11:55:58 pm
content: Time to publicly Name and Shame.Damn you Microchip!http://ludzinc.blogspot.com.au/2014/06/measure-twice-cut-once-get-new-ruler.html

author: dannyf
author_rank: Super Contributor
timestamp: July 01, 2014, 01:28:35 am
content: Mis-labeled pins are minor issues: you will quickly find it out and fix it for good.Mis-functioning peripherals are a totally different matter, particularly those without a workaround.

author: zapta
author_rank: Super Contributor
timestamp: July 01, 2014, 01:45:09 am
content: I had this problem recently, using the 1.3" OLED displays from a Chinese company. They are nice people so I will not name them here.They clearly states that it can operate at 5V. Not true. The module's 6 pins are connected directly to the internal SSD1306 controller which is not 5V compatible or tolerant. I figured this out the hard way when displays start to flicker. Now they came with a new version that has a 3.3V LDO but the SPI signals still go directly to the SSD1306 which is not 5V tolerant and the internal clamping diode raises the 3.3 VCC to 4.5V.Adafruit has similar display that works just great with 5V but is three times more expensive.

author: hans
author_rank: Super Contributor
timestamp: July 01, 2014, 07:06:01 am
content: Does this satisfy your blog title: "Still getting it wrong the first time."? There always has to be something.. always 1 some thing..I'm starting to build up the same confidence level with ST.Their STM32F4 datasheets and product info seem overrushed. Their STM32F2 is much more comprehensive, with less "TBD" and more explained errata's.Driving an ethernet Phy chip via the on-chip clock outputs? (which is all over the datasheet) Not happening - too much clock jitter. Not mentioned as an issue in the errata of F4 series.. it is in F2. As both chips look remarkably similar (basically the F4 is the M4 + FPU + extra memory bolted on the F2 peripherals). So after adding a dedicated oscillator for that Phy chip it works!I/O rise/fall times (which are configurable, so it's nice to know what you set them to) are all "TBD". Do I need to assume they are similar to the STM32F2, and use those?

author: AndyC_772
author_rank: Super Contributor
timestamp: July 01, 2014, 08:11:09 am
content: +1 for Microchip. I counted three data sheet errors in the last project I did with a PIC, two of which were new to them (I reported them to Microchip support), and one of which was listed in the errata.Yes, that's right. They got the device pin-out wrong in the data sheet, but instead of fixing the data sheet when they found out, they put the correct symbol in a completely separate document.

author: rob77
author_rank: Super Contributor
timestamp: July 01, 2014, 09:23:12 am
content: Atmel also got somethey don't know the difference between "should be" and "must be" - AT89S52 ('51 flash micro with ISP)== quote form AT89S52 data sheet - PIN description section - page 6EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetchcode from external program memory locations starting at 0000H up to FFFFH. Note, however,that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.== end quoteshould be strapped to VCC - one would think that leave it floating (it says "should", not "must") will be fine for internal program execution... but that's not true - the MCU behaves very very funny when EA is floating

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 01, 2014, 11:20:29 am
content: Well, leaving floating nodes is just bad practice in general, you can't blame them for that. The "latched on reset" part seems a bit dubious given your results, but who knows. Those sorts of pins are always weird. Which, really, is all the more reason for them to document them in particular detail, but no one ever seems to..Sure, a "pin holder" function might be nice, but most times those things simply aren't bothered with, so you're left peppering the board with pull-up/down resistors.Tim

author: rob77
author_rank: Super Contributor
timestamp: July 01, 2014, 11:38:30 am
content: Quote from: T3sl4co1l on July 01, 2014, 11:20:29 amactually i'm blaming them for not using the phrasing "MUST be strapped to VCC" in the datasheetwhen i realized they're finally making the '51 with ISP - i rushed to build a programmer (inverted reset and slightly different protocol than AVR ISP), checked the datasheet for all the "MUST" parts and then..... spent 1 hour debugging till i figured out what's the issueeven the xtal oscillator and therefore ISP is not working properly with EA floating.btw... it's pretty common nowadays to have internal pull-ups - so leaving something floating when the datasheet says "should" instead of "must" is not a crime

author: ludzinc
author_rank: Unknown
timestamp: July 01, 2014, 12:14:57 pm
content: Quote from: hans on July 01, 2014, 07:06:01 amDamn straight Skippy! Thought I'd share my pain with the world!

author: Bored@Work
author_rank: Super Contributor
timestamp: July 01, 2014, 06:20:10 pm
content: Even worse, datasheets where they deliberately try to hide some bodies by using fancy wordings or strategic omissions, downplaying important facts.E.g. the LT3080 which blows up when the difference between the set and the out pint is > +/- 0.3V.Or the Atmel xmega's, which mostly come with no or useless data in the calibration row. But Atmel keeps up the impression in the datasheets that they come with some kind of reasonable factory calibration.A bit of a gray area are measurements in datasheets which were taken outside of the intended application range. E.g. switching time or Rdson of logic-level mosfets. The figure not given for when the mosfet is driven with a typical logic-level Vgs like 3.3V, not even 5V, but 10V. Bastards. Power ratings are also in such a gray area.

author: JTR
author_rank: Regular Contributor
timestamp: July 01, 2014, 10:15:10 pm
content: Ha ha. I just knew that this thread was going to be about "microchip" () just from the subject heading...

author: mariush
author_rank: Super Contributor
timestamp: July 01, 2014, 10:53:17 pm
content: The datasheet is common for PIC16F1713ANDPIC16F1716.PIC16F1713 has 17 10bit AD channels, datasheet says PIC16F1716 has 25. That may explain the confusion, one table may refer to PIC16F1713, the other table to the other PIC. Either way, it's a bit confusing... i don't see for example how they fit 25 ad channels in a 28-soic after all there's only porta, portb, portc and one porte which can't be adc, so i guess even that 25 value is incorrect.Yeah.. new part, new datasheet (though last revised in january)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 02, 2014, 04:21:28 am
content: Quote from: Bored@Work on July 01, 2014, 06:20:10 pmMOSFETs of all types over 20Vdss always work better at higher voltage, so you should try to drive at >= 10V if at all possible. Example: you have a 5V logic circuit and a 12V supply *somewhere*, but it's not nearby, so you figured, ah hell, just use logic level. And you discover the performance sucks. Later, you add a proper gate driver supplied from 12, and it works beautifully. If it's around, it's worth using.If you must drive at 5V, do so, and use a very low impedance gate drive. The switching speed is dominated by Cgs equivalent and Miller effect, and during the switching transition (Miller step), you can't drive any more current into the internal gate node any faster than the total resistance allows. Helpfully, datasheets are providing R_g more often these days, so you can see what size gate driver is appropriate (if R_g is 5 ohms, a driver under 2 ohms or so won't help any), and better estimate switching speed.Speaking of, calculate gate transition time based on Qg(tot). Max if provided.Ignore Cgss.As for lower voltages, there is no such thing as a 3.3V logic level silicon MOSFET for high voltages (over say 40 or 60V). At best, you might find some that are specified for crappy performance there, but it's only very marginally in the saturation region, especially over Vgs(th) and T_J variation. If you absolutely must, well, whatever, but don't expect miracles. If you need actual switching performance, by all means, at the very least add a charge pump for ~6V, or a proper boost converter to get in the >= 10V range.There are only two cases currently available where lower voltage is acceptable: low Vdss MOSFETs, which are made with smaller feature sizes and thus have higher gain, and GaN FETs ($$, small selection, small stock, often hard to use -- e.g. solder-bump dies), which have all-around way better performance than Si (especially for higher voltage ratings, currently up to 200V or thereabouts). The lowest Rds(on) I've seen is something like 700uohm (that's micro) for a 7V 30A Si part, rated at Vgs = 2.0V. This would be good for single or possibly two cell lithium battery management applications, and even some DC-DC converter action (beware of R_g, I don't recall it was particularly high for this example, if it was given, but with lower voltages comes greater sensitivity and all that).FWIW, MOSFETs over about 40V all look the same, in that the gate voltage range is pretty much constant (Vgs(th) by design, as well as the amount required for saturation on top of that), and Rds(on) has a strong tempco (ranging from about +80% at 150C for the lower voltages, up to +180% for many ~1000V devices). Lower voltage devices (particularly 20V and below) exhibit higher gain (making logic level applications more practical) and lower Rds(on) tempco (more like +30 to +50% at 150C). Recognize that the only thing that really changes between "regular", "logic level" and (if you run across any,) "depletion mode", is the gate threshold voltage. The gain (change in drain current over change in gate voltage) isn't any different between any of them: the only difference is, logic level types are made with a lower Vgs(th), with a tighter tolerance. Let me put it this way: if you would never consider driving a regular FET with +2 to +7V (assuming the same Vgs(th) min-max spread), don't use a logic level FET at 0 to 5V.Tim