Why there are multiple drain pins in this MOSFET package? - Page 1
Forum section: electronics / beginners

author: Nikos A.
author_rank: Regular Contributor
timestamp: April 24, 2021, 09:28:45 pm
content: Hi everyone,Just for curiosity, why this MOSFET has 5 x drain pads?https://www.ti.com/lit/ds/symlink/csd16301q2.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1619037454183&ref_url=https%253A%252F%252Feu.mouser.com%252FThis is to improve the thermal performance? Do they act something like a heat dissipator?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 25, 2021, 01:37:52 am
content: The die is laid on top of and bonded to a metal leadframe, which is exposed on the D pins. The rest are probably wire bonded to the die (in higher current parts, the source terminal(s) may also be a leadframe that's bonded to the top of the die.) Solid metal connections have high electrical and thermal conductivity, yes indeed. Use all the D's in parallel, and attach a large copper pour to provide heat dissipation when necessary. (Likewise, when source current is high, it doesn't hurt to use wide copper connections there as well.)The best way to do this in EDA tools, varies; some you can assign multiple pin numbers to a symbol, so you can use an ordinary MOSFET symbol and footprint with normal pin numberings; others, they must match exactly, so you either need multiple identically-named pads in the footprint so they all connect to the respective pins (probably a custom variant of the footprint, since pinouts might vary between different kinds of devices in the same package -- though in this particular case, I'm not sure if anything besides MOSFETs uses that package?), or duplicated pins in a custom symbol so they can all be numbered and connected explicitly (a bit ugly, but effective).Tim

author: Jeroen3
author_rank: Super Contributor
timestamp: April 25, 2021, 02:18:41 pm
content: When you're unsure look for application notes of the package variant.I found this image in marketing material frompanasonicmosfets.So use drain to take the heat out.

author: JustMeHere
author_rank: Frequent Contributor
timestamp: April 25, 2021, 04:42:07 pm
content: "The 2-mm × 2-mm SON package offersexcellent thermal performance for the size of thepackage."You package will have a pin arrangement. It doesn't matter if you use all of them or not. If you want to get the heat out, use all of your "spare" pins to add connections to the ground. It usually has the most copper and will dissipate the most heat.

author: Nikos A.
author_rank: Regular Contributor
timestamp: April 25, 2021, 08:32:00 pm
content: Thank you for your answers guys!!Quote from: T3sl4co1l on April 25, 2021, 01:37:52 amThis is how I proceededIs there any tool to determine the necessary vias for thermal dissipation?Nick

author: exe
author_rank: Unknown
timestamp: April 25, 2021, 08:51:24 pm
content: Why the copper pour has voids around mosfet pins? Is it to provide thermal relief? I wonder if this is still needed. I guess, depends how most is going to be soldered.

author: Nikos A.
author_rank: Regular Contributor
timestamp: April 25, 2021, 08:56:51 pm
content: Hi exe,Quote from: exe on April 25, 2021, 08:51:24 pmYes this is to provide thermal relief to facillitate manufacturing (soldering)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 26, 2021, 01:23:22 am
content: You can easily calculate the thermal resistance of small parts, then add them up.For example, the spokes: take the spoke length, divide by total width, divide by copper thickness, and divide by copper conductivity (~400 W/m/K). Spoke resistance is mostly not a problem, I don't mind it.It can be easier to solder, yes. The alternative, pouring solid copper over the area, creates soldermask-defined pads, which will be oversized at default settings, and are less accurate.You may want some vias in the middle pad. I have no idea if that's what you've done in this 3D view screenshot; a transparent 2D, or top and bottom screenshots, would be more informative.Likewise for the vias: take copper thickness, via circumference and number of vias, and board thickness. If the vias fill with solder, take the volume of the cylinder of solder the same way (and look up a figure for solder thermal conductivity -- it varies with alloy).I think you will find, the thermal resistance to air is dominant. This isn't easy to calculate accurately (most dramatically, it depends on whether air is still, convecting, or forced -- as with the board flat on a table, or standing edge-vertical, or has a fan blowing over it, respectively!), but a good hand-waving estimate is taking a specific resistivity of 0.1 K m^2/W, and dividing by total area (top plus bottom). If your copper pours are 2cm square, that's a 8cm^2 area, or 0.0008 m^2, or 125 K/W.This drops off for large areas, where the resistance of the board itself becomes significant: heat only spreads out a modest distance, corresponding to the average conductivity of the board. FR-4 is a poor conductor, and copper dominates, but a few ounces isn't much, enough to carry heat a few cm (in still air). So pours more than say 5cm across give diminishing returns.If using multilayer boards, this is a very good reason to keep large (preferably solid, uninterrupted) pours on inner layers. FR-4's conductivity between layers is downright pitiful, but it adds up over wide areas; so the top copper, and vias to bottom copper (or inner, if you choose to do it that way), carry heat into a wider area, which carries heat into the planes, and together they carry it into an even wider area.And yes, I mean this works without having electrical (direct metallic thermal) connection between planes and the thermal pours. So you don't have to sacrifice good electrical performance to get good thermal performance, rather they support each other to some extent.And obviously, same is true of heavier copper in general: prefer 2oz for protos dissipating much power in SMTs. 3oz+ tends to get expensive so you might consider another method if you need more (bigger devices e.g. D(2)PAK, SMT heatsinks, heat spreaders, or going to THT).A note on via plating: PCBs are fabbed by starting with some copper foil thickness, drilling and prepping vias, then plating that. Via "barrel" copper will always be thinner than full facing copper. Check the fab specs and see if you can find this figure. Typically, 1oz boards will start with 0.5oz and plate to 1oz, so 0.5oz gets in the vias. 2oz might start with 0.5 or 1oz, plated to 2, leaving 1.5 or 1oz respectively in the vias -- a notable difference!And because via copper is relatively thin, and despite the relatively poor thermal conductivity of solder, it can be a net win to intentionally fill vias with solder. This is easier to do on big devices with outer fillets (D(2)PAK, etc.) than on buried thermal pads, but thermal vias around the part you might consider using relatively large diameter vias and exposing some copper so they can be tinned easily.Narrow vias <= 0.3mm tend to wick solder poorly, which makes them relatively safe to use via-in-pad, i.e. without thieving solder from the joint; larger ones wick easily. I would recommend around 0.5mm dia.. Larger ones, the fillet sticks out more and more, perhaps making heatsinking a challenge, if you decide to clamp the board to a heatsink with a thermal pad; and, really big holes (d ~ board thickness) just don't really stay filled at all, they're super blobby. Also, large vias have less copper in them, so you're depending more on the solder alone; a dense pattern, of modest size vias, very close to the pads (but not touching, so they don't wick solder away), is best.Oh and anyway, once you have total thermal resistance (sum package, spoke, via, pour and convection resistances), that defines the temp rise for power dissipation. So, if you're not using much power (<100mW?), it's not a big deal. I wouldn't expect much more than 1W from a device like that anyway, so don't push it. They give figures in the datasheet for typical layouts, understand which figure goes with which layout.Tim

author: dietert1
author_rank: Super Contributor
timestamp: April 26, 2021, 09:35:20 am
content: Quote from: Jeroen3 on April 25, 2021, 02:18:41 pmRead: "Read flame" = "Lead frame".Regards, Dieter