R-2R ladder DAC calibration - What do you think? - Page 1
Forum section: electronics / projects

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 10, 2016, 02:09:06 pm
content: I'm designing a digital audio synthesiser, it's just a fun project to build something and explore ideas along the way. I thought it would be interesting to implement anR-2R DACfor the output.Here's a 16-bit R-2R DAC made from 100R 0603 resistors:Here's the full-scale ramped output:I NOW know that R-2R ladder DACs are extremely sensitive to resistance errors and that high-resolution R-2R DACs are generally impracticable.Nevertheless, I would like to explore how things might be improved with some kind of on-board automated calibration. My idea is to use a comparator with two sample & holds to compare any two output values of the DAC. The host microcontroller can then use a sorting algorithm (e.g.bubble sort) to re-order the scale to achieve a monotonic output. Here's the basic schematic:What do you think?As an extra note, the calibration process could also active during run-time. For example, the DAC would be changing at 40 kHz with the application and, while this is happening, the host microcontroller could compare any two consecutive outputs and swap them if they are found to be non-monotonic.

author: bktemp
author_rank: Super Contributor
timestamp: October 10, 2016, 02:42:49 pm
content: 100ohms is much too low value, because the typical output impedance of digital I/Os is somewhere between 20-70 ohms. So you probably get 130ohms instead of 100ohms!Calibrating the DAC sounds a bit impractical to me, because it takes quite some time for 16bits, and it takes 32kByte of memory for the lookup table.It could work, but the settling time for each step is probably quite large if the voltage changes by only 1/65536.I would use one of the cheap delta-sigma audio dacs, designed for audio.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 10, 2016, 03:32:39 pm
content: Quote from: bktemp on October 10, 2016, 02:42:49 pmThanks for the tip, I had not considered this. Perhaps this explains why I observed such terrible performance even when reducing the resolution to 8-bits.Quote from: bktemp on October 10, 2016, 02:42:49 pmThis isn't a problem. The microcontroller has loads of memory (necessary for audio sampling).Quote from: bktemp on October 10, 2016, 02:42:49 pmAre you referring to the settling time of the DAC output or the sample & holds? I do not expect the final design to achieve 16-bit performance but this is a nice arbitrarily high resolution to explore ideas with.Quote from: bktemp on October 10, 2016, 02:42:49 pmI would too, if I was designing a product, but this project is for fun.

author: bktemp
author_rank: Super Contributor
timestamp: October 10, 2016, 04:02:07 pm
content: Quote from: sebmadgwick on October 10, 2016, 03:32:39 pmThe comparator:If you look into a comparator datasheet their response time is typically specified for 100mV overdrive. With only 3.3V*1/65536=50uV difference between each step, it will be very slow. For example an LM393 has a response time of 300ns for 100mV. At 5mV it is somewhere around 1.3us. At 50uV, probably much longer. The calibration will probably take several seconds if it needs to be accurate.Instead of building a 16bit DAC, I would use 2 8bit DACs and combine them using a voltage 256:1 divider. This is much easier to achieve than 16bits.You can still use the calibration for the MSB DAC (or both, but it probably doesn't care for the LSB DAC).QuoteIf you want to build an even more complex circuit, look at some ancient low cost DACs like YAC512 (DAC chip for YMF262 OPL3 FM synthesis sound chip) or TDA1543. They use some kind of floating point DAC consisting of a 10bit DAC and exponent shifter.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 10, 2016, 04:35:32 pm
content: Quote from: bktemp on October 10, 2016, 04:02:07 pmInteresting idea. Are there any obvious issues with such a design? One is that the op-amps would need to handle inputs voltages close to ground in order to deal with the LSB. A negative supply rail would therefore be essential.

author: bktemp
author_rank: Super Contributor
timestamp: October 10, 2016, 04:40:59 pm
content: Quote from: sebmadgwick on October 10, 2016, 04:35:32 pmThe MSB DAC needs to be have an error of less than 1/256 otherwise the LSB DAC is useless.This type of DAC is often used for PWM DACs:http://www.openmusiclabs.com/learning/digital/pwm-dac/dual-pwm-circuits/index.htmlQuoteAn opamp isn't needed, because a R2R DAC has a fixed output impedance of R. If you include that into the calculations you can simply use a resistive voltage divider combining both DACs.

author: w2aew
author_rank: Super Contributor
timestamp: October 10, 2016, 07:59:48 pm
content: You can save yourself some time and grief - manufacturers such as Bourns make R2R resistor arrays - everything all matched up in a single SIP or DIP package... or SMT if you prefer.http://www.digikey.com/product-search/en/resistors/resistor-networks-arrays/65543?k=r2r+array&k=&pkeyword=r2r+array&pv9=39&FV=fff40001%2Cfff80007&mnonly=0&newproducts=0&ColumnSort=0&page=1&quantity=0&ptm=0&fid=0&pageSize=25and yes, as suggested earlier - use a high enough resistance in the R2R to prevent loading issues with the digital signal inputs - these logic levels need to be consistent to get a good linear output.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 11, 2016, 12:14:20 pm
content: I've been thinking about the comparator settling time and accuracy issue. A potential improvement could be to...- AC-couple and amplify the DAC output (e.g. x100) being fed back for calibration.- The calibration process would then generate a saw tooth wave for a given fraction of the full-scale, e.g. for values between 0 and 2^n / 100.- The sort algorithm may then re-order the values in this 'magnified' fraction of the full-scale, so that the saw tooth ramp is monotonic.- The calibration process can progressively ascend the fraction under examination until the complete full-scale has been calibrated.

author: bobaruni
author_rank: Regular Contributor
timestamp: October 11, 2016, 01:09:56 pm
content: There is no way to use a lookup table to make a non monotonic DAC monotonic, if there are codes missing, you can't create them where they don't exist (unless you have a few extra bits say a 20 bit DAC to make an almost linear 16 bit DAC using lookup tables).You're better off trying to match the resistors more precisely, even resorting to buying several hundred 0.1% resistors and cherry picking a small batch of resistors that have as close to the same value as possible.There are also problems around creating glitches when the MSB gets switched.This is why Burr Brown used the dual DAC (dual segment or current segment) technique to create very high quality audio DACs, even these were laser trimmed to match the resistors....very expensive!Having said this, if you focus your design efforts on all the potential problems, a discrete DAC can be built and can outperform comercial chips.An easier way would be to use some PWM to modulate a smaller but perfectly monotonic DAC, this is exactly how the current state of art audio DACs achieve 24-32 bit resolution and low cost (no laser trimming).

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 11, 2016, 01:21:14 pm
content: Quote from: bobaruni on October 11, 2016, 01:09:56 pmI think you have misunderstood whatmonotonicmeans. It is not possible to make the DAClinearif codes are missing, but a short algorithm would achieve a monotonic output, by definition.Quote from: bobaruni on October 11, 2016, 01:09:56 pmWhat do you mean? I will use a 16-bit parallel port on the microcontroller; all of the bits would effectively change instantaneously with a single instruction.

author: rstofer
author_rank: Super Contributor
timestamp: October 11, 2016, 01:30:37 pm
content: I haven't really worked through the math but it seems to me that if 0.1% resistors are used, at best the ladder can resolve accurately is 1 part in 1000 and the 16 bits might as well be reduced to 10 bits. It's sort of stating a measurement to 0.001" when it was taken with a yardstick.I need to research just how they implement 16 bit DACs.

author: bktemp
author_rank: Super Contributor
timestamp: October 11, 2016, 01:32:23 pm
content: Quote from: sebmadgwick on October 11, 2016, 01:21:14 pmThere will be glitches because of the limited slew rate and other analogue problems, but they are most likely irrelevant here at 40kHz samplerate, because other problems are much worse (like non symmetrical high/low drive the digital outputs).

author: bobaruni
author_rank: Regular Contributor
timestamp: October 11, 2016, 01:37:39 pm
content: Quote from: rstofer on October 11, 2016, 01:30:37 pmYes, 0.1% is only good for a 10bit DAC but hand picking resistors to within 1/65536 or 0.0015% should achieve the required linearity.

author: bktemp
author_rank: Super Contributor
timestamp: October 11, 2016, 01:49:20 pm
content: Quote from: bobaruni on October 11, 2016, 01:37:39 pmBut you still have to compensate the resistance of the the digital outputs. Even if you measure and subtract the value of each output, low/high state will still have a different resistance by at least a couple of ohms, maybe even 10 or 20 ohms.

author: bobaruni
author_rank: Regular Contributor
timestamp: October 11, 2016, 01:51:03 pm
content: Quote from: sebmadgwick on October 11, 2016, 01:21:14 pmOK if you're willing to sacrifice a percentage of the DAC's ENOB's then use the lookup table but it will no longer be 16Bits but I guess that's what your aiming at.QuoteThe glitch is caused by an MSB carry, not by all the bits being driven out of sync. It's very hard to make the MSB behave properly in a 16 bit R-2R DAC without some trickery.Have a look at your oscilloscope plot of the ramp signal, the big overlap in the centre is an MSB carry glitch.In audio, the most important part of a converter is around the MSB switching point, having such a large glitch would create large amounts of noise and distortion.

author: bobaruni
author_rank: Regular Contributor
timestamp: October 11, 2016, 01:56:15 pm
content: QuoteExactly, you would have to hand measure and match everything, even then you would have complex interactions between each bit as the ladder doesn't have infinite resistance.The higher the resistance of the ladder, the less impact driver mismatch will have.But I think the OP is not so concerned with absolute accuracy but more so the concept of a self correcting DAC and having fun.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 11, 2016, 02:09:07 pm
content: Quote from: bobaruni on October 11, 2016, 01:56:15 pmCorrect!It would be interesting to simulate the full-scale output of a R-2R DAC with randomly generated resistance errors, and then sort the output to be monotonic. I wonder what the resultant shape would be.

author: rstofer
author_rank: Super Contributor
timestamp: October 11, 2016, 02:32:04 pm
content: Quote from: bobaruni on October 11, 2016, 01:37:39 pmI have no idea what it would take to measure to 0.0015% but I know I don't have it. When I used to work in the semiconductor business, I knew people who could probably do such a thing but I'm not one of them.Since the on and off resistance of the switching device is probably going to swamp the resistor tolerance, I have to wonder how real DACs are implemented. Laser trimmed internal resistors, no doubt.Temperature drift?

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 11, 2016, 02:42:11 pm
content: Quote from: rstofer on October 11, 2016, 02:32:04 pmWikipediasays...Quote from: WikipediaThat's what got me thinking about calibration.

author: tszaboo
author_rank: Super Contributor
timestamp: October 11, 2016, 02:46:49 pm
content: OK, you dont want an oversampling DAC, i can understand that. So use a TDA1543, which is designed to do this. But let's say, you dont want to use that chip, for whatever reason. So use an off the shelf industrial DAC. 16 bit, NOS is common, they have SPI interface, some can do 1MSPS. They are linear, monothonic. IND and DNL error of 1-2 LSB. Just convert the interface to SPI and have fun. Make sure to use expensive opamps for the output.But even a bunch of trimmer potentiometer is easier than what you are trying to do.And realize, that your music was recorded using an oversampling ADC, and a bunch of 5532 in the recording equipment.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 11, 2016, 02:59:35 pm
content: Not all the resistors in the R2R ladder need to be that accurate. The lower 5 bits or so might work OK with of the shelf 1% resistors. The next 3 could work with 0.1% resistors if the output drivers are low impedance and beyond that you likely need trimmed resistors or extra adjustment points, that can also take care of the driver resistance.Output glitches even happen with fest switching outputs - one of the sources is parasitic capacitance, especially if rather large resistors are chosen to reduce the influence of the driver output resistance.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 11, 2016, 03:12:44 pm
content: I'm not really interested in how to choose resistors. I'm more interested in people's thought on the calibration solution I proposed.bktempmade a good point about the comparator settling time potentially becoming an issue for low voltage differentials.What about the simple sample&hold being made of an DPST analogue switch connected directly to caps on the comparator inputs? Is that too simple?

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 11, 2016, 03:39:04 pm
content: Quote from: bobaruni on October 11, 2016, 03:23:33 pmI'm hoping this will work out. The analogue switch resistance is typically ~10 Ohm, so I need to choose the largest capacitance that is able to reach the 99.999% (or whatever) of output within the sample period. The comparator can be read immediately before flipping the analogue switch to maximum charge time.For example, the 10R switch resistance with 100n sample&hold cap would take 11 us to reach 99.999%. 99.999% corresponds to a 33 uV error when charging from 0 V to 3.3 V. These are arbitrary numbers but they give an idea about what to expect.

author: rstofer
author_rank: Super Contributor
timestamp: October 11, 2016, 04:34:04 pm
content: Your block diagram shows the DIY sample-and-hold going into a uC. Do uCs have 16 bit ADCs? Most of the chips I use are lucky to have 10 bit ADCs. And some of the uC ADCs have really low input impedance.Anyway, I would add two more switches to your sample and hold such that I could measure both voltages on both samplers. Then I might mess around with the math to work my way out of problems with the sample-and-hold capacitors. How accurate do the capacitors need to be? Anything beyond 1% is going to be difficult to find. So then you have to calibrate your way around your calibration device.Since a 16 bit DAC only costs about $3 (maybe up to $6), I would play with a discrete ladder just for the experience and then move on. Just providing a Vref suitable for 1 part in 65536 is going to be enough of a challenge.In a measurements class I took a long time ago, the rule of thumb was that you had to be able to measure 10x better than what you were trying to test. To apply this to a 16 bit DAC, you would need a 19 or 20 bit ADC.

author: Vgkid
author_rank: Super Contributor
timestamp: October 11, 2016, 04:47:42 pm
content: With the resistors you don't need 0.0015% accuracy. You need them to match with 0.0015% or better. With the 2R try to get some that match that range even better.

author: Kleinstein
author_rank: Super Contributor
timestamp: October 11, 2016, 05:07:32 pm
content: The measurement circuit proposed at the top is not practical, as comparators also have quite some offset. The more practical way would be to let the DAC switch between adjacent (or critical) values and than do AC coupled amplification, sending the result to an ADC, like the µC internal ADC (e.g. 10 Bits). The tricky part could be separating transient effects from the DAC error.One would likely need the adjustment only for the higher bits, so less entries in the table and more time to do the measurements. It might also be enough to do the adjustment for the bits, not for all the codes. So one might get away with something like only 20 adjustment points for a 16 bit DAC: likely not adjustment needed for the lower 5 bits. Just a single adjustment for bits 6 to 12 and up to 4 or 5 for the higher bits. More than just one correction value might be needed for the higher bits, as the error can slightly depend on the setting of the adjacent bits.In the simple case of using 2:1 resistor values, ignoring the driver impedance, the curve will always show overlap (to little effect for the higher bits) - so to get a more linear curve a few codes need to be dropped and no large gaps where there is not code to get close to a given voltage.Audio grade DACs are rather cheap - so it is not really worth it. It is more like an nice exercise for an application that might have had some application 20 years ago.

author: C
author_rank: Super Contributor
timestamp: October 11, 2016, 08:19:11 pm
content: sebmadgwickJust a quick read but it looks like you are thinking static.You are thinking charge times of a cap, but not using the fact that a cap has a charge curve based on time.Think of your circuit being junk, then use ohm's law and charge curves to compute the values. Have your cal use the circuit against it's self to get the calibration values.You have a ADCYou can use it as a comparator.You can change your R2R ladder so you can do dual slope ADCWhile doing this you see charge curve.Use what you have to compute everything.The cap value, the charge resistor,the charge voltage change.The ADC ratios, The DAC ratiosVerify your guess of value by what you see with ADC,time and math.Note that you have ratios. The dac and adc are ratio devices.In binary you are working bits to the right of decimal point.Left most bit of ADC or DAC is a change from 0.0 to 0.1 in binary a point 50% between the two references to ADC or DAC.Just an Idea.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: October 12, 2016, 01:41:40 pm
content: I conducted a test that confirms my proposed solution will not work in principle.Here's the test circuit using anBourns R-2R ladder ICto create an 8-bit DAC.Here's the sawtooth output for values 0 to 15.The problem is that resistance errors result many output codes creating approximately equal output voltages. Even if calibrated, the 4-bit range show above could only create 4 different output voltages instead of the 16 expected. My proposed calibration solution relied of the output codes creating different output voltages which could then be ordered for monotonicity.Oh well, it was an interesting while it lasted. Thanks for your input, everyone.

author: Kalvin
author_rank: Super Contributor
timestamp: October 12, 2016, 02:27:16 pm
content: Looks asymmetrical GPIO pull-strength tome: The GPIO may be able to pull heavily to GND, but the pull-up strength to VDD is very weak. Check the GPIO pin configurations if you can adjust the GPIO pin drive strength. You may also want to measure the voltages at the GPIO pins directly: If the GPIO pins do not go close to VDD, your pin drive strength is too low. You may also want to measure the adjacent GPIO pins in order to see whether the GPIO pins affect each others: They should not.Are you sure that you have connected the R2R-network correctly? Where is the ground connection?