YAHBPSU - Yet Another Home Brew PSU - Page 1
Forum section: electronics / projects

author: TheRevva
author_rank: Regular Contributor
timestamp: July 10, 2014, 09:10:10 am
content: I've seenlotsof PSU schematics, but none of them managed to fulfill my requirements, so I'm 'brewing my own'.Attached is a PDF (I hope?) of the regulator schematic I'm about to experiment with. Feel free to critique it to death.(I'll probably write up a detailed explanation in a subsequent posting)Rather than taking the same BJT-PNP LDO route that most others seem to choose for their regulator, I've gone with a FET based design.A downside is that this requires 2 independent AC sources, but if you use a toroidal mains transformer, you can possibly just over wind it with an additional, very low current secondary.Alternatively, an additional 'baby' transformer is unlikely to 'break the bank'.(Sure, thereareFET based supplies that operate with a single AC supply, but these can be 'risky' IMNSHO. Let's assume you've got it set for 20V output and then short the output. This can momentarily cause the absolute max Vgs of the FET to be exceeded! The Gate is still being driven with around 24V, but the Source is suddenly down to 0V)With the values specified, V-Set / V-Mon are 1/5 of the output voltage and I-Set / I-Mon (in Volts) are 1/2 of the output current (in Amps)(This means I can 'drive' V-Set and I-Set from a DAC that's referenced to a 4.096V solid reference to give a range of 0 to 20.48V and 0 to 8.192A which is all I need for now)Changing 1 resistor per signal allows different multipliers and should not require total re-compensation of the entire design.I've driven it through LTSpice a few times, and in principle, it looks reasonable (but those may well be 'famous last words').The prototype (on 65mm * 65mm veroboard / stripboard) will be built in the next week or two and I'll 'test' it with simple pots/DMMs on the V-Set, I-Set, V-Mon and I-Mon lines.The control section (which will come later) is likely to be based on the LTC2402,LTC2602/LTC6654-4.096 driven by some randomly selected micro-controller through opt0-ocouplers (for channel isolation).(I'm borrowing the concepts of the control section from Gerry Sweeney / Ian Johnston designs)Component parts (retail from Jaycar) for the first regulator channel is around NZ$100 (including a toroid with 2 * 18V 8A secondaries).A second channel would add < NZ$50 (since I'd steal back the second 18V winding on the toroid for power and 'over-wind' a couple extra low current 12V secondaries)/I expect the digital control section will approximately double the price (partially because it will include NZ$40 worth of MSOP to DIP adapters!!! Ouch!At present, I'm not intending laying out a custom PCB for it, but ya never know what the future holds - getting someone like Seeed to make PCBs would be offset by not having to buy those pricey MSOP-to-DIP adapters!

author: bktemp
author_rank: Super Contributor
timestamp: July 10, 2014, 09:25:06 am
content: It looks good, but the IRF540N is much too small. Don't get fooled by the the high dower dissipation value on the first page of the datasheet. Always look at the SOA curves. Since no curve is shown in the IRF540N datasheet for DC condition, this mosfet is not rated for linear operation at all. This does not mean it is impossible, but you have to guess how much power it can handle.If you do not switch the input voltage in some steps, go for a bigger mosfet than TO220 package (like IRFP150 in TO247) or parallel some mosfets (wich is not easy).

author: void_error
author_rank: Frequent Contributor
timestamp: July 10, 2014, 09:34:40 am
content: 20V @ 8A is a lot of power. You'll need at least half a dozen of paralleled MOSFETS to handle the maximum power dissipation in case of output short circuit. I recommend using a switchmode step-down pregulator or a huge heatsink (and maybe a fan).

author: TheRevva
author_rank: Regular Contributor
timestamp: July 10, 2014, 09:54:55 am
content: @bktemp:Oooops, I actually intended to specify the TO247 part rather than the TO220 part (IRFP540N instead of IRF540N).Also, this 'prototype' is only designed for a couple Amps max with the 540. The final version will employ a somewhat higher spec FET.Trying to find the optimum FET isn't exactly straightforward. Can someone please tell Mr Fairchild to make me a 500Amp FET with 1uOhm RDS(on) and a 1femtoCoulomb gate charge! <Grins>P.S. The Agilent E3646A uses a IRFP540N for up to 3A (0-8V) and 1.5A (0-20V), so I'd assumed it was a 'reasonable' choice for this prototype.@void_error:Please see above.I want to avoid use of an SMPS pre-regulator (for no real reasons I might add) but I accept that I need SOME degree of pre-regulation and / or transformer tap switching.The E3646A I mentioned above is intriguing. It uses a couple SCRs + opto-couplers for the tap-switching and then pushes that output through an IRFP540N as the pre-regulator before it hits the primary reservoir caps.Thanks heaps to you both for the feedback!

author: mij59
author_rank: Frequent Contributor
timestamp: July 10, 2014, 10:05:05 am
content: Referring to the provide schematic.The capacitor C11 is 4700uF , the ripple voltage at 8A will be 17V , its a bit to high.You can replace bridge B2 with 2 diodes.Protect Q1 with a zener diode of 15V between gate and source.You'll need some capacitance at the output to get the circuit stable.

author: BravoV
author_rank: Super Contributor
timestamp: July 10, 2014, 10:13:55 am
content: When using a common switching fet to work in linear region, though I'm no expert, suggesting to derate the fet by a big margin, such as using multiple fets in parallel with ballast resistors to spread the load.Launched a discussion while ago at the "potential" issues using a switching fet in linear mode ->Question on mosfet in linear mode, does "hot spotting" a serious problem ?

author: TheRevva
author_rank: Regular Contributor
timestamp: July 10, 2014, 12:57:05 pm
content: Quote from: mij59 on July 10, 2014, 10:05:05 amPlease forgive my ignorance in asking these Qs.I'm confused as to why i need to 'protect the FET with a zener? As I see it, the gate can only be 'driven' to a maximum of +12 or -12 relative to its source. (The 'common' of the 7812 / 7912 vregs is tied directly to the source)With the FET configured in basically a source-follower arrangement, I was hoping to avoid (or at least drastically minimise) any need for an output reservoir cap? I'd be happy with a few uF, but I want to avoid having 100s (I guess this will be found out in the 'prototyping')Edit:Yes, I certainly will need to bump up the main input reservoir cap. Probably a handful of 10mF caps in parallel.The reason I used a bridge instead of 2 diodes for B2 was simply because I have more of them in my 'parts bin'. It's only being used for 1/2 wave rectification. Originally, I was intending it to be full-wave rectified by using a center tapped winding.

author: TheRevva
author_rank: Regular Contributor
timestamp: July 10, 2014, 01:39:47 pm
content: Quote from: BravoV on July 10, 2014, 10:13:55 amI'm pretty confident I can get an Amp or two from the 540s (providing I start 'managing' the Vin to Vout difference. (I don't think I've mentioned above how I'll be mounting the FET directly to an old Pentium-IV heatsink (complete with fan). While the heatsink will be effectively at full drain voltage (since I'm unlikely to isolate it), the HS will be electrically isolated from everything inside the case.I've not yet found a suitable FET for the final (i.e. Non-prototytpe) version, but I've not looked too hard.As for the links you've posted... Thank you immensely!!! It'll be a while before I get through reading THAT thread.

author: mij59
author_rank: Frequent Contributor
timestamp: July 10, 2014, 01:43:49 pm
content: Quote from: TheRevva on July 10, 2014, 12:57:05 pmYour driver circuit for the fet is not very low impedance, so voltage spikes could exceed the max gate source voltage.With a zener diode positive en negative spikes are limited.Yes a low output capacitance is better, but you'll need more electronics to keep it stable.Some years ago there was a circuit in Elektor, i think they used a output capacitor of 0.47 uF .The value of the input filter cap is a trade off, higher capacity means less ripple voltage, but also higher cost and higher inrush current.The transformer and bridge rectifier must be able to withstand this inrush current.I think you'll need at least 3 capacitors of 4700 uF, giving you a ripple voltage of about 6 V

author: TheRevva
author_rank: Regular Contributor
timestamp: July 12, 2014, 09:34:50 am
content: WARNING! LONG POSTING ahead... I type too much!!!Thanks a bunch for the great feedback mij59!In my spice runs, I was very surprised howgoodthe line regulation seems to work which has made me wonder if it's worthwhile 'attempting the unthinkable'...A lot of bench supplies use transformer tap switching to limit internal heat dissipation. Also, it's quite common to see a pre-regulator inserted before the main regulator.The Agilent supplies I've looked at use both. (The transformer taps are 'switched' electronically with a couple of SCRs + opto-couplers forming the top half of a bridge rectifier – quite a clever way to avoid an unreliable mechanical relay).What I am considering attempting is either 'the ultimate in cheeky' or just 'plain elegant'? (Assuming it works at all)By installing an identical FET between the main bridge rectifier and the regulator FET and connecting the gate of this FET to the +12V 'control' supply (perhaps via a small resistor?), you're instantly feeding the main FET with a 'pre-regulated' source voltage that's Vgth less than 12V (which equates to around 9V). In other words, the main linear regulator will 'see' an input voltage that's 9V more than the desired output.So how much energy do we need to turn into heat?The output from my bridge is 100Hz with a peak at 25V.Let's assume that we have our output dialled way down to 5mV and we're (somehow) drawing 5A! Without a pre-regulator, our FET would need to dissipate 24.995V at 5A (Almost 125W!!!). It's highly unlikely we'd be able to keep the magic smoke inside the FET!By adding in the simple FET pre-regulator, the regulator FET now 'sees' (V on its drain, so it needs to dissipate 8.995V @ 5A (Still large, but a far more 'comfortable' 45W). The remainder is dissipated in the pre-regulator FET, but since the drain of this FET is fed with the rectifier output rather than DC, it is conducting 0A for about 25% of each half cycle and then dissipates energy for the top 2/3 of each ½ sine wave. At the peak of the incoming sine wave, it's still needing to dissipate 16V @ 5A (80W), but this is balanced by the fact that ZERO current flows for 25% of the time. I'm not about to do all the math, but I would bet the average dissipated power would be in the same ballpark as the main FET.Looking at the other end of the scale, let's consider what happens when we set our output to our 20V maximum. The gate of the pre-regulator FET is intrinsically driven to 12V above our desired output (20 + 12 = 32V). We then need to 'subtract' the FETs gate threshold value (let's say 3V) to determine its maximum source voltage (32 – 3 = 29V). Since our input supply to the drain only peaks at 25V, the pre-regulator FET will be switched on hard thereby achieving its minimum Rds(on) value. Consequently, our reservoir capacitor will be charged to almost the full 25V. The main regulator FET has its drain at this 25V and tries to steer its source to 20V, so it's dissipating 5V at our 5A of load current (5 * 5 = 25W).The total dissipated heat is now split across two FETs (and total FET dissipation is less too). The main reservoir capacitor is instructed to hold 9V of 'reserve power' for output voltages below 16V instead of the full 25V. The peak ripple on this cap at full output (20.48V) will be nearly identical but would be less at output voltages below 16V (since that's where the pre-regulator starts to kick in)It all sounds too simple? Either someone here will point out my 'obvious logic flaw', or I'll find out the hard way from my prototype! (Actually, I'd prefer the latter... LOL)The toroidal transformer I already have has 2 independent 18V/8.33A secondary windings, but I realistically don't expect to need more than about 4A output. Therefore, I'm scaling down the I-Set and I-Mon to suit. Instead of 1V = 2A, I'm setting it to 1V = 1A. This has the benefit of doubling the effective resolution once it's with a DAC. (While the DAC I'm looking at has 16bit resolution, I'm going to 'reserve' 4 bits of that for 'calibration' purposes. Therefore, I'd end up with 4096 'steps' of 1mA each since my DAC reference voltage is exactly 4.096V).That gives a voltage resolution of 5mV steps over a 0 to 20.48V range unless I incorporate an electronic 'range switch' (Something which I'm seriously considering! It's simply switching 2 additional 720k resistors into the V-Set / V-Mon opamp network!)Anyway, here's my list of 'proposed changes' thus far:1: Include 15V Zener, gate-to-source to 'clamp' Vgs to the range -0.6 to +15 approx. (I still don't quite understand how a spike could ever get in there, but a zener only costs $0.10). NB: Not on the schematic yet!2: Increase the main reservoir cap from 4700uF/50V to 27000uF/50V.3: Decrease R11 and R12 from 4k7 to 470R and remove R18 from main FET drive. This increases the available FET drive current tenfold (hopefully without exceeding the TL074 current sink limits which I need to confirm on some spice runs)4: Add a SMALL (10uF max?) cap directly across the output. NB: Not on the schematic yet. It'll be wired directly across the output posts which is also where the 'sense' wires will be connected. (All of the high current wiring completely bypasses the controller board)5: Include the pre-regulator FET with a 100R gate resistor to the existing +12V supply.6: Increase R15 from 180k to 360k (thereby changing the effective I-Set multiplier to 1V = 1A7: Increase R14 to 360k (to scale I-Mon the same to I-Set)8: While it's still showing IRF540Ns, I'm going with IRFP540Ns on the prototype (TO220 vs TO-247)I've attached an updated schematic along with my 'proposed' veroboard layout as PDFs since they are more usable for those few who haven't installed Eagle. (I'm more than happy to post up the Eagle sch and brd files too if anyone wants them).The big capacitor, 2 FETs, current sense shunt and the primary bridge are 'off-board' as they're mostly on heat sinks. (The FETs are going onto some old Pentium 4 HSF assemblies as I happen to have a small army of them. I'm not sure if I'll run the two fans in parallel from the 7812 or in series from the main bridge rectifier output. More likely the bridge via a 1N4001 since version 2 will have far less available current into the control section and the main toroid + bridge have 'amps to burn'.

author: mij59
author_rank: Frequent Contributor
timestamp: July 12, 2014, 11:14:06 am
content: Thanks for the warning, yes many many words.Reducing the power dissipation is always a good, everything will say much cooler and thereby increasing the lifespan of the power supply.Your pre-regulator circuit does not reduce the total power dissipation, its an attempt to divide the power between the fets.The correct way to reduce the total power dissipation you have already described.If u remove R18 the circuit will tend to oscillate, it even be necessary to a resistor in series with R22 to get the circuit stable.I think simulating the circuit can be very nice, although it is possible that reality will not be that nice to the circuit.

author: TheRevva
author_rank: Regular Contributor
timestamp: July 14, 2014, 09:38:34 pm
content: Thanks HEAPS for 'sticking with me' on this one so far.NB: This is another 'novel length' post. It appears I'm hopeless at making them short!I seem to have come up to a fundamental stumbling block that I need help from someone to understand.Quote from: mij59 on July 12, 2014, 11:14:06 amThe logic inside me totally agrees, but my math to prove this doesn't quite get there so the best way I can explain my question is with two examples.The power transformer produces around 18VAC (at a current far greater than we require). We'll assume 'perfect' (VF=0) diodes in the bridge.We set our PSU output to 5mV and connect a 1milliohm resistor across the output. We also disable our current limit by using a zero ohm current shunt. Therefore, we're delivering 5A into our resistive load.Example 1: (The original schematic with a single FET, but 'amended' to change the bulk capacitor to 27000uF/50V)The bulk capacitor is charged up to about 25VDC. (Admittedly, the capacitor voltage does 'droop' under the load during the lower portions of the transformer output by about 1V)Our FET has approx 25V on its drain and 0.005V on its source, both at 5A. Therefore, our dissipation is (25 - 0.005) * 5 = 124.975W. (Assuming it keeps the magic smoke inside)Example 2: (This time using a second FET as a 'pre-regulator' with it's gate driven enough to keep the bulk capacitor 9V above our desired output voltage (i.e. 9.005V)The dissipation in the main regulator FET is (9.005 - 0.005) * 5 = 45W. This is FAR more 'healthy' (although still a lot!)If the dissipation was truly 'shared' between the two FETs, we'd now expect the pre-regulator FET to be dissipating 124.975W - 45W = about 80W.The output (source) of this FET is fixed at 9.005VDC. (In reality, it will 'droop' a little below this value during the lower portions of the AC cycle.However, the input to the drain of this FET is not 25VDC. Instead, it's the full wave rectified output from the transformer which PEAKS around this 25V value.The pre-reg FET will conduct ZERO when the incoming AC falls below the capacitor voltage (which is approximately 23% of the time)My rudimentary math makes me think the dissipation in this FET is FAR below 80W. and is probably closer to 1/2 that value (around 40W).My only thought is that the pre-regulator is acting as a crude form of 'active rectification'. We only need to dissipate the additional power that we allow IN to the system. If we don't let it in, then we don't have to dissipate it.Therefore, I'm guessing that the aggregate internal dissipation drops from about 125W to 85W (over 30%) which is a HUGE advantage without requiring a custom (aka expensive and 'exotic') multi-tap transformer. It's also 'shared' between two active devices which should help to make them live longer. The only reason I chose 9V to begin with is that I already have a supply that's fixed to 12V above the source of the main regulator FET. After removing approximately 3V of VGS(th), this gave me values in the 9V range. My opinion is that it's best to have the two FETs dissipating similar amounts at the worst possible output settings and it appears that my arbitrary 9V was quite a lucky stab.

author: dannyf
author_rank: Super Contributor
timestamp: July 14, 2014, 09:49:23 pm
content: You probably want to figure out a way to more concisely articulate your points / questions.The power dissipation is fairly simple. Assuming constant output voltage from the rectifier / filter unit, at a given current output (load), the total power dissipation is identical between two parallel regulators / fets or two serial regulators, on a per device basis.Say in your example, the total power dissipation is 120w. If you had used two parallel regulators, and the load sharing is identical between them, the dissipation would be 60w each - think of the two devices have the same current going through them.In the case of a pre-regulator, assuming that the voltage is split equally between them, each regulator will dissipate 60w.Effectively, the parallel approach splits current load between the regulators and the serial (pre-regulator) approach splits the voltage between the two regulators.After that, it is fairly easy to see what pros / cons each approach has.A far more efficient approach is to use a switching mode pre-regulator whose "ground" is referenced to the output of the 2nd / linear regulator.

author: mij59
author_rank: Frequent Contributor
timestamp: July 15, 2014, 04:07:53 am
content: Quote from: TheRevva on July 14, 2014, 09:38:34 pmYour assuming that the current trough the fet is constant during the time it's conducting.This not the case, the bulk cap will be charged, causing a massive current surge.

author: TheRevva
author_rank: Regular Contributor
timestamp: July 15, 2014, 10:33:32 am
content: The 'lightbulb' just went on!!! (Finally!)Thanx for pointing me in the right direction!

author: mij59
author_rank: Frequent Contributor
timestamp: July 15, 2014, 10:46:56 am
content: Quote from: TheRevva on July 15, 2014, 10:33:32 amYes I can see it, it's very bright !

author: TheRevva
author_rank: Regular Contributor
timestamp: July 15, 2014, 09:23:48 pm
content: LOL!!!For quite a while, I think I had my dimmer turned down a bit too far!!!I should have realized it sooner since my "Try-Yack" was getting awfully warm!

author: TheRevva
author_rank: Regular Contributor
timestamp: July 26, 2014, 01:17:50 am
content: It's quite common to see op-amps used as the final portion of the control chain. Referring to the schematics I posted, these are IC3A (voltage) and IC3D (Current).The purpose of these opamps is simply to 'steal' drive from the series pass transistor thereby lowering the PSU output accordingly.The problem is that one of these two devices will, under normal circumstances, be saturated and thus it takes a long time to de-saturate. (i.e. When the PSU switches from CV mode to CC mode or vice versa).Their outputs are effectively tied together by diodes forming a 'wired-or' type arrangement. (i.e. IC3A _OR_ IC3D will control the series pass transistor while the other one is left to saturate).My question is...Would it be 'reasonable' to employ open collector comparators (eg: LM393 dual comparator)?This would eliminate the need for the diodes (since the two 'open collector' outputs could be directly wired together).It would also avoid them 'saturating' to the + supply rail (since there is no 'top-half' transistor in the device to saturate).Lastly, generally speaking, comparators are much 'faster' than an op-amp.The unknown (to me) is how well the open collector transistor will do in keeping linear control of the series pass transisot!(I'd probably use an LM339 so that I could use a third section as an 'output-off' / reset control)Other PSU schematics I've seen don't use comparators in these positions (which is a huge 'hint' to me), but I don't understand why not.

author: mij59
author_rank: Frequent Contributor
timestamp: July 26, 2014, 05:20:18 am
content: Quote from: TheRevva on July 26, 2014, 01:17:50 amComparators have a build in hysteresis, the circuit will oscillate.You could use transistors to drive the output transistor, a lower value of the collector resistor gives a better frequency response.

author: mikerj
author_rank: Super Contributor
timestamp: July 26, 2014, 11:06:31 am
content: Quote from: mij59 on July 26, 2014, 05:20:18 amSome comparators have built in hysteresis, but there are many that do not.

author: Kevin.D
author_rank: Frequent Contributor
timestamp: July 26, 2014, 12:15:48 pm
content: Quote from: TheRevva on July 26, 2014, 01:17:50 amHi there .You have the right ideas with your schema ,needs some changes but a good first attempt .To answer the question ,the speed of the error amp or any small transitors that are driving a larger pass bjt/fets are not going to be the limiting factors in how fast the control loop can be operated (you usually have to reduce the error amp high frequency gain to get a stable loop ,like in your schematic with the caps around the opamps ) .What usually limits the speed the loops can be operated , are other delays created by stray RC (or sometimes RL,LC) networks .Things like in your schema the fet gate to Drain capacitance (Cgd) ,which has to be charged/discharged via any gate resistor + output impedance of the opamp .Sometimes driving the gate from a lower impedance source can speed this up (thats why you sometimes see gate drive transistors instead of just direct opamp driven when you have large fets being driven),refering to your schema C7 across R12 is a speed up cap which bypasses R12 at high frequency and speeds up gate cap charging. Another source of RC loop delay would be any load capacitance(with a low esr) on the output ,this then forms a second RC pole which has to do it's charging/discharging via the output impedance of the pass transistors and any Rload (here your pass fet is (common source) which has high output impedance and so here output impedance is basically ~ Rload) ,so this means high Resitance (low current) loads with low esr caps like Ceramics result in low frequency pole (output change delays) .For a Current control loop theres a few differences to take into account compared to the Voltage cntrl loop but it's basicaly the same rules.Regards .

author: TheRevva
author_rank: Regular Contributor
timestamp: July 31, 2014, 12:54:57 am
content: Thanx a bunch Kevin,Technically, I think my series pass FET is a common drain setup rather than common source (but hey, what would I know... I'm always willing to learn).Consequently, I had expected the effective output impedance to be comparatively LOW?At very low output voltages / currents where the FET is almost switched off, I fully accept that the effective output impedance will go up a lot as the Rds of the FET increases to maintain regulation.(I expect that's another benefit of including a decent tracking pre-regulator. If we keep the Vin:Vout ratio quite close to 1 then the FET will stay at the lower end of its Rds value. I'm almost convinced to use an SMPS tracking pre-regulator... <Sigh> With the more traditional transformer tap switching, I would expect the effective output impedance to increase in proportion to the Vin:Vout ratio)As for C7 (the 'speedup' cap to assist with (dis)charging any Cgd in the FET, I doubt it will help to increase it much beyond where it is (unless I add in an additional pre-driver transistor to help with sinking more gate current). (The opamp drivers cant be expected to sink more than about 20mA or so!).What I'm REALLY interested in is your closing comment about 'differences' in the current control loop.In my naivety, I've consider both loops to be quite similar since the current sense resistor converts the load current into a voltage right from the outset!If you can elaborate any further on that point I'd be VERY grateful.

author: megajocke
author_rank: Regular Contributor
timestamp: July 31, 2014, 01:56:06 am
content: Whether it "is" a common source or common drain stage is just a matter of definitions and how you choose to analyze the circuit. Specifically, it's down to which node you define as the common node for the input signal and output signal. Circuits aren't inherently one or the other until you define exactly what the input and output signals are.As the opamp providing gate drive is referenced to the source of the MOSFET, it makes sense to analyze it as a common source stage. The input signal is then the output voltage of the last opamp referred to the control circuit power supply midpoint, and the output is the output voltage of the power supply, with the negative output being the "hot" side and positive output (=control circuit PS midpoint) ground.I took the liberty to redraw the voltage loop to make this detail stand out, as shown in the attachment. Sorry for putting the negative output on the top.However, in a small signal analysis its DC potential doesn't matter in any case.The differential amplifier measures the output voltage, and the next stage is a PI type regulator whose output voltage controls the pass transistor.Pass transistor Rds doesn't really matter for control loop behavior. (or the observable quantity which is closed-loop output impedance) What does matter is the transconductance, which depends mainly on drain current. It also decreases at low Vds.With some care it is possible to guarantee stability into any passive load at any output current, but it won't be easy without a largish output capacitor to give well-defined high frequency behavior.

author: Kevin.D
author_rank: Frequent Contributor
timestamp: August 01, 2014, 05:07:39 pm
content: Quote from: TheRevva on July 31, 2014, 12:54:57 amHeres a couple of jpgs with both configs ,hope this clears it up.Perhaps the best way to view a transistor in either Follower(C.Drain) or Common.Source configuration in order to explain the difference between them in this context , is to consider how they react to any Rload changes if their base/gate Voltages are held static ( So like In the circuits above, lets fix the Vgs and ignore any opamp loop feedback because here we are interested in the inherant a.c response of the just the two transisitor configs).So in the S.follower (load in G-S loop) if say from some steady state , Rload is suddenly reduced in value then Vsource(Vs) would also reduce .And if Vgate was constant then Vgs must now be larger and the Fet would automaticily be biased in to conducting more on ,thus increasing current through Rload and returning Vs(the voltage across Rload) to it's orignal value .So we can say a S.follower acts like a low impedance Constant Voltage Source to any Rload in it's source terminal .It has inherhant voltage regulation abilites ,and this makes it inherantly stable in C.V(constant voltage) loops. But it's not so good in CC (constant current) loops and doesnt contribute to regulating current .Conversley with the Common.Source config (load in S-D loop) circuit ,if from a steady state there a sudden change in Rload ,which then would cause Vds to change . But now Vgs will still be constant ,so now the Current through the mosfet (and our Rload) will be held constant ,since current through fet is determined by Vgs and Not Vds .So then we can say a Common .Source config looks like a high impedance Constant Current source to any Rload in it's Drain-Source circuit . (It's high impedance because a Large change in Vds will only produce a small change in Drain Current . You can get the value from the data sheet it's the slight slope in the almost flat part of a transistors transfer characterisitics, output impedance Ro =delta Vds/Delta Id ,it's usually a big number,and this value in parrallel with Rload is what gives the overall output impedance (since Ro is usually big then Ro||Rload is more or less ~ Rload ).Why is all this static gate stuff important when you have an error feedback loop which also compensates. ?Because it determines the initial ac behaviour of the two configurations until the feedback loop can take over,and tells you something about what the various pro's and cons of each is .A 'Source Follower' (which is what the poster seems to be making in this thread :-https://www.eevblog.com/forum/projects/bench-power-supply-design/wants to behave like a Constant Voltage source to the load ,so it is inherantly fast and stable in C.V loops (except at very low currents (~< 5mA) because it's output impedance (~1/gm) goes up and it starts to form poles with any caps on the output , so you would add a minimum current load on the output to help overcome this ).In C.C mode though the feedback error opamp will have to do all the work on it's own it gets no help from the S.follower and it will 'ring' like a bell with certain loads unless you put some carefull compensation around the C.C error opamp .Almost the opposite is true of the Common Source config which wants to behave like a constant current source to the load .It has inherant Current regulating abilites,and it's fairly easy to get a good performace then in C.C mode .But in C.V mode the C.V error opamp will have to do all the work on it's own to regulate V and will need extra compensation (to reduce the gain of error amp) because the fet now has high Zout in this config it forms poles with any Capacitance on the load.This aint so bad as it sounds as you also get the extra gain From the pass Fet in a CS config that you dont get from S.follower . which kinda makes up for the extra opamp compensation you need in C.V mode ,and so you may get an 'almost' equivalent C.V performance to the source follower but never as good.Thats a long enough post here I think . I didn't realize how much I had Typed till I scrolled up .Quote from: TheRevva on July 31, 2014, 12:54:57 amIt does but it's not because your Rds is changing.Remember there is a difference between R-Resistance and Z-Impedance .Rds is your fets Resistance value at DC ,not at High.Freq . Somethings can have a low output dc Resistance yet a high output Impedance (like an inductor ,or transistor acting as a Current Source .)Quote from: TheRevva on July 31, 2014, 12:54:57 amPersonally I would use the traditional tap switching method ,dont want any smps inside your precious low noise bench supply case ,the noise they generate permeates everywhere and you can't get rid of it completely, it's like getting beetroot stains out of clothes .Quote from: TheRevva on July 31, 2014, 12:54:57 amYes it really is a 'speed up cap' . you can't always use one unless your sure selected an opamp that is able to drive the resultant Capacitive gate load that you directly expose it to when you bypass the gate resistor .Quote from: TheRevva on July 31, 2014, 12:54:57 amWhat I would normally do is dissable the C.V loop so it doesnt interfere with my C.C loop testing ,I'd then get the C.C loop stable for its 'worst case loads'.Once it is you then know it will be stable for all loads .Then after you do the same thing for the C.V loop.The major difference between them is that the 'worst case loads' for a C.C loop are inductive loads,(since an inductor opposes any change in current it really affects the C.C cntrl loop ).Whilst a C.V loops 'worst case loads' are capacitors across the output(low esr) ,(since capacitors oppose any change of Voltage at the output they slow down the C.V cntrl loop .)So since this is a bench supply and you supposed to prep it to handle any type of load you might want to throw at it,you would test the C.C by sticking various size inductors (upto say 10H) on the output at high current's ,then test the C.V loop stability by sticking various size low esr caps on the output at very low output currents .Regards .

author: David Hess
author_rank: Super Contributor
timestamp: August 02, 2014, 06:37:47 am
content: When operating linearly at low Vds, vertical MOSFETs do not have problems with current sharing and their safe operating area curve is square within their rated power dissipation although Vgs matching or source degeneration is still needed to share current between parallel devices. Power dissipation still needs to be derated as junction temperature increases of course.The operational amplifiers are not going to be completely happy driving the power MOSFET input capacitance. As shown the slew response and frequency compensation will be asymmetrical. Buffering the gate drive will yield better performance.The output should have a small value of bulk capacitance to make the frequency compensation predictable. If a ceramic or film capacitor is used, then series resistance for controlled ESR may improve stability.IC3B has an uncompensated high pass response. Is that intentional? I usually make provisions for pole-zero compensation in my designs and minimize the error amplifier's feedback capacitance for high slew rate so switching between voltage and current modes occurs as fast as possible. Clamping IC3A and IC3D to prevent saturation would help with this.The integrated regulators should have output capacitors.