Help to Design/Select a PLL, to clean up a GPS signal,  for a reference standard - Page 1
Forum section: electronics / projects

author: t1d
author_rank: Super Contributor
timestamp: July 30, 2018, 11:30:57 pm
content: Re: PIC18F4550, or PIC18F45K50MPLAB X IDE, with X8 CompilerC CODEWINDOWS 8.1GPS: 9600 BaudSKILL LEVEL: Advanced Noob?Did I do my homework? Yes; Studied PLL circuits, considered LM565, 74HC4046 and many others, Google/Internet, Reference Books, Etc., 4550 and 45K50 Data Sheets, all for many hours/days.I would like to build this GPS Locked Frequency Standard project:http://www.scullcom.uk/design-build-a-gps-locked-frequency-standard-part-4/.(The complete video series is on YouTube. Video #1 is a good introduction. Video #4 includes the various revisions, made during the project's development.)It is an Arduino project, but I want to build it with a PIC18F4550, or PIC18F45K50, using C code, as those are what I am learning about. And, I want to run my entire circuit on 3.3 volts, for battery considerations.At 10MHz, the original Arduino circuit’s signal integrity is usable, but degraded, having noise and phase offset. The original design makes use of a Schmitt-Trigger, to calm the signal noise. The S-T does not do a good job, of cleaning up the signal.I would very much appreciate help selecting a PLL IC (a single IC, having a VCO and PFD, would be great) and designing this leg of the circuit. Per Louis Scully,"To remove this phase jitter altogether a Phase Locked Loop circuit could be used, but I will leave this for future project as it involves a second PCB with a Voltage Controlled Oscillator and a Programmable Frequency Divider in the feedback loop."Scully is amazingly generous, with his designs. But, he has moved on, to other projects, and various requests for the PLL have not resulted in a design being offered.I know that you need various types of information, to help me. What else do you need to know? Thank you, in advance, for your help.

author: MosherIV
author_rank: Super Contributor
timestamp: July 31, 2018, 06:48:49 am
content: HiBefore you go down the PLL route, check that you need it first!What GPS receiver do you have?Does it output a stable 10KHz signal?Most recent GPS modules/receivers do not have a stable 10KHz signal, they have a 1PPS (pulse per second) which can often be changed to another freq.However, they are not stable, they have phase jitter, skip pulses to maintain the set freq.There are a number of projects out there that use SW PLL (or what I would call averaging) on the 1PPS to dicipline a oven crystal.

author: t1d
author_rank: Super Contributor
timestamp: August 01, 2018, 04:01:41 pm
content: Quote from: MosherIV on July 31, 2018, 06:48:49 amDisplayed and fully discussed, beginning at 20:00, of video #4.Quote from: MosherIV on July 31, 2018, 06:48:49 amSimilar to video author, just one model up = NEO-M8N Chinese clone, but it keeps its restart settings . Allowed for this project, see video #1.Quote from: MosherIV on July 31, 2018, 06:48:49 amStable, but not clean.Quote from: MosherIV on July 31, 2018, 06:48:49 amThe frequency output can readily be changed, in the GPS module software, on the fly. That is an advantage, of this project.Quote from: MosherIV on July 31, 2018, 06:48:49 amYes, this unit has noise and phase shift, at higher frequencies.Quote from: MosherIV on July 31, 2018, 06:48:49 amThat may be for another project, later, but, I am just a hobbyist, trying to learn Electronics, PICs, and C Coding. This project is for combining those specific purposes. Thank you, so much, for your help.I have been looking at PLLs, with on-board integrated VCOs. I am having difficulty finding one that will run as slow as I need, say from 1MHz, bottom, to 10MHz, top. A suggestion, by someone, as to a particular make and model, to investigate, would be great. Or, some other means, to clean up the noise and phase problems... The circuit's output is terminated, with 50 ohms. I would think that using capacitors would create problems, with the square wave.

author: Bud
author_rank: Super Contributor
timestamp: August 01, 2018, 04:34:14 pm
content: There are PLLs with output dividers, such as ADF4360-9. This one can go down to 1.1MHz. but it has tiny package and you need to learn how to design the loop circuit for it and program it. Guess you could search for PLLs with output dividers.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 01, 2018, 04:42:47 pm
content: For a good GPS disciplined reference the oscillator would be something like an VCOX and the PLL loop would be rather slow, as for up to some 100-1000 seconds the oscillator can be more stable than the GPS signal. At this low frequencies one should consider a digital control instead of a classical analog PLL. There are quite a few plans online.

author: iMo
author_rank: Super Contributor
timestamp: August 01, 2018, 05:26:32 pm
content: Last few months I've been messing with the same task. Using an FPGA + NEO-7M + Trimble 10MHz DOCXO.After some experiments with PLLs in software (stm32 + PWM, or stm32 + 16bitDAC) I've currently opted for the simplest XOR based phase detector.Comparing 10kHz from NEO-7M against 10MHz divided by 1000 (within an FPGA, the XOR gate also in the FPGA, my design includes a reciprocal counter in the FPGA as well).You can do it easily with standard CMOS stuff. Basically the Miller's design, I added an opamp buffer after the PLL low pass filter (to decouple the EFC), from that buffer's output it goes to Trimble's EFC input. There is a second opamp buffer which decouples the ADC input of the stm32 (it measures the actual EFC voltage).There are advantages and disadvantages of such an HW PLL:Pros:. you must not mess with the sw/ADC/DAC/PWM etc.Cons:. it takes XX minutes to get the loop "locked" in case you have lost the already stabilized EFC voltage,. you cannot extrapolate and set the EFC voltage when the GPS is off. the XOR phase detector tracks continuously, thus it may create a modulation of the 10MHz when the loop filter is not designed properly.

author: t1d
author_rank: Super Contributor
timestamp: August 01, 2018, 08:57:39 pm
content: Quote from: Bud on August 01, 2018, 04:34:14 pmThis is an interesting IC. Affordable. Package is doable; I have a DIY reflow oven. Designing a loop circuit is outside my experience range, but there might be a suggested design, in the data sheet.

author: t1d
author_rank: Super Contributor
timestamp: August 01, 2018, 09:01:39 pm
content: Quote from: Kleinstein on August 01, 2018, 04:42:47 pmI looked at DPLLs. It is becoming clear that this area of electronics has a steep learning curve and is beyond my (present) design skills.

author: t1d
author_rank: Super Contributor
timestamp: August 01, 2018, 09:20:02 pm
content: Quote from: imo on August 01, 2018, 05:26:32 pmIt is becoming apparent that a high quality/expensive second oscillator is necessary.Quote from: imo on August 01, 2018, 05:26:32 pmI'm sorry, but I did not understand this sentence.Quote from: imo on August 01, 2018, 05:26:32 pmWould you, please, provide me with a copy of your schematic, for this portion, of your project?

author: t1d
author_rank: Super Contributor
timestamp: August 01, 2018, 09:26:37 pm
content: Well, is there another approach, to this problem? The GPS signal is quite clean, at 1MHz. Is there someway to multiply it, without introducing instability, delay, noise and phase distortion? I know that PLLs can multiply the signal, by some means. So, maybe this is exactly how they are employed. If not, how might 1MHz be multiplied, properly?

author: Bud
author_rank: Super Contributor
timestamp: August 01, 2018, 10:09:24 pm
content: Typically you would overdrive a transistor with it, followed by a tuned filter to select the needed harmonic and then amplifying to the needed level. Can also use commercial passive multipliers such as Minicircuits parts but they do not supress the fundamental much so may also need filtering, depends on what your requirements are to purity of the output signal.Can also try a fast comparator or Schmidt trigger followed by a ultrafast gate logic, again to generate harmonics, then filter select and level it. Any multiplication will also multiply the source phase noise so you need to clean the original signal as much as you can before feeding into a multiplier.

author: t1d
author_rank: Super Contributor
timestamp: August 02, 2018, 03:50:54 am
content: Quote from: Bud on August 01, 2018, 10:09:24 pmThanks for helping, Bud, but this is all beyond my skill level. That's why I originally ask for help with a specific part (that would do the complete job), or design.

author: iMo
author_rank: Super Contributor
timestamp: August 02, 2018, 06:37:48 am
content: @t1d:1. it seems you want to use the NEO's 1PPS output signal (configured to a different, higher frequency, say 10MHz or 1MHz)as the "reference source"directly.Issue N.1:There is an issue with the "quality at some NEO's specific output frequencies" (otherwise said "a crap", or full "disintegration") I addressed in a different thread here, but 12MHz, 8MHz, .., 1MHz,.. 10kHz should be ok.https://www.eevblog.com/forum/metrology/neo-7m-output-frequency-issue/2. you may use 12MHz, 8MHz, 4MHz etc. with good quality.10MHz, unfortunately,is not 48MHz/N(where N=4,5,6,7,..).Thus, if you need 10MHz you must go with disciplining of a 10MHz OCXO, or TCXO.Issue N.2:3. In order to clean-up the "GPS signal jitter" (mindthis is a different issueto the above one) people use an OCXO disciplined by that GPS'es 1PPS, or 10kHz, or 12MHz.The "long term" stability is achieved by a long loop integration constant, such the GPS jitter is averaged out.That is the process of "cleaning up the GPS reference signal".4. My recommendation to you is to configure the NEO's 1PPS output to 12MHz, or 8MHz, or 4MHz (those are clean but with the usual GPS jitter).5. Cleaning-up the 10MHz NEO-7M's output signalis not feasible, imo.You may double-check whether the NEO-8M/N is affected as well.6. To your question on the schematics - the easiest way to get a (DIY) clean disciplined 10MHz reference signal is to acquire a 10MHz OCXO (ebay $10-$30), divide its 10MHz output signal by 1000 (in order to get 10kHz out of it), and compare those 10kHz with 10kHz GPS in so called Phase comparator - for example a XOR gate. It must not be 10kHz you compare, you may try with different clean (mind the issue N.1) frequencies.The EFC is the OCXO's electronic frequency control - you control its frequency via changing the voltage, the typical voltages are 1.5-6V, the typical "EFC gains" are 100-200ppb/V with quality OCXOs.The GPS_10Khz signal, the phase detector/comparator, the RC low pas filter, and the OCXO_divided_by_1000 (where you tune the OCXO with the EFC voltage) create the phase control loop (PLL), where the OCXO locks itself to the GPS_10kHz after some time (loop settling time, typically 15-20minutes).

author: t1d
author_rank: Super Contributor
timestamp: August 04, 2018, 05:30:46 am
content: Great information! Thank you, imo.