Quartus M10K ModelSim fails - Page 1
Forum section: electronics / general

author: Wiljan
author_rank: Regular Contributor
timestamp: June 19, 2020, 09:02:05 am
content: HiI do use Altera / Intel FPGA with quite a lot of Sboxes 8x8 (256bytes) made in M9K and M10K ROM 2-port by the Mega wizard this works fine so far.Also if I implement it directly from verilog as lpm_rom or altsyncram it does work in the RTL viewer and in the FPGAWhen I try running the RTL simulation (ModelSim build in Quartus V15) the it all works fine if the ROM are implement as LUT's but when it's in the M9K / M10K it failsfault message: "Instantiation of 'altsyncram' failed. The design unit was not found"So does ModelSim work with M9K / M10K at all?Or do I miss to include something like a path ?How do you simulate M10K ?

author: Wiljan
author_rank: Regular Contributor
timestamp: June 30, 2020, 12:59:02 pm
content: I do use Quartus 15 and have attached some images showing the error I get when I try to run the build in RTL-Simullation in Q 15 after compiling the below verilog codeThis is my top entry code and I have chosen a MAX10 10M08 to get a quick compile time just for testingCode:module altram(Ain,clk,ROM_A_out);input [7:0] Ain;input clk;output [7:0] ROM_A_out;wire [7:0] rom_01;wire [7:0] rom_02;wire [7:0] rom_03;wire [7:0] rom_04;wire [7:0] rom_05;wire [7:0] rom_06;Dual_Rom inst_01(.address_a(Ain),.address_b(rom_01),.clock(clk),.q_a(rom_01),.q_b(rom_02));Dual_Rom inst_02(.address_a(rom_02),.address_b(rom_03),.clock(clk),.q_a(rom_03),.q_b(rom_04));Dual_Rom inst_03(.address_a(rom_04),.address_b(rom_05),.clock(clk),.q_a(rom_05),.q_b(rom_06));Dual_Rom inst_04(.address_a(rom_06),.address_b(rom_07),.clock(clk),.q_a(rom_07),.q_b(ROM_A_out));endmodulemodule Dual_Rom (address_a,address_b,clock,q_a,q_b);input[7:0] address_a;input[7:0] address_b;inputclock;output[7:0] q_a;output[7:0] q_b;wire [7:0] sub_wire0 = 8'h0;wire sub_wire1 = 1'h0;wire [7:0] sub_wire2;wire [7:0] sub_wire3;wire [7:0] q_a = sub_wire2[7:0];wire [7:0] q_b = sub_wire3[7:0];altsyncramaltsyncram_component (.address_a (address_a),.address_b (address_b),.clock0 (clock),.data_a (sub_wire0),.data_b (sub_wire0),.wren_a (sub_wire1),.wren_b (sub_wire1),.q_a (sub_wire2),.q_b (sub_wire3)// synopsys translate_off,.aclr0 (),.aclr1 (),.addressstall_a (),.addressstall_b (),.byteena_a (),.byteena_b (),.clock1 (),.clocken0 (),.clocken1 (),.clocken2 (),.clocken3 (),.eccstatus (),.rden_a (),.rden_b ()// synopsys translate_on);defparamaltsyncram_component.address_reg_b = "CLOCK0",altsyncram_component.clock_enable_input_a = "BYPASS",altsyncram_component.clock_enable_input_b = "BYPASS",altsyncram_component.clock_enable_output_a = "BYPASS",altsyncram_component.clock_enable_output_b = "BYPASS",altsyncram_component.indata_reg_b = "CLOCK0",altsyncram_component.init_file = "SBOX.HEX",altsyncram_component.intended_device_family = "MAX 10",altsyncram_component.lpm_type = "altsyncram",altsyncram_component.numwords_a = 256,altsyncram_component.numwords_b = 256,altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",altsyncram_component.outdata_aclr_a = "NONE",altsyncram_component.outdata_aclr_b = "NONE",altsyncram_component.outdata_reg_a = "CLOCK0",altsyncram_component.outdata_reg_b = "CLOCK0",altsyncram_component.power_up_uninitialized = "FALSE",altsyncram_component.ram_block_type = "M9K",altsyncram_component.widthad_a = 8,altsyncram_component.widthad_b = 8,altsyncram_component.width_a = 8,altsyncram_component.width_b = 8,altsyncram_component.width_byteena_a = 1,altsyncram_component.width_byteena_b = 1,altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";endmoduleCould someone please give me a hint how to use the build in RTL simulation (ModelSim) for altsyncram?If I use plain logic it all works fine but fails in respect to the altsyncram even if I add the "altera_mf" library manually in the "Start Simulation" in ModelSimIf I chose the altera_mf and the altsyncram directly and right click and press simulate it does works as expected but not when I start it from the works libraryThe altsyncram in my verilog is a rip of the megafunction output and it does compile fineI have attached some screenshoots hopefully showing the problemThank you