Via-touching-pad manufactuiring issue - Page 1
Forum section: electronics / projects

author: Rachie5272
author_rank: Regular Contributor
timestamp: November 01, 2021, 04:46:56 pm
content: I've been designing my boards with tented vias touching surface mount pads. This seems logical enough to me: the hole is far enough away from the pad, and should be fully covered by the solder mask. For some reason, JLCPCB wants to open up the solder mask over these vias. Does anyone know why this might be a manufacturing issue? I'm concerned if the holes are uncovered, solder paste might wick in, and hot gases will be trapped (the vias are tented on the other side).Their explanation was "normally we will add such obstructive point in case there is ink on the pad", but I don't fully understand what they mean.

author: langwadt
author_rank: Super Contributor
timestamp: November 01, 2021, 05:02:52 pm
content: why not just move the vias slightly and avoid the issue?

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 01, 2021, 05:46:50 pm
content: Well, just looking at your picture, it seems obvious (to me at least) the hole can't be fully covered without some soldermask spitting over the pad. Think about tolerances.I'm not sure why you did that in the first place.If you want to improve thermal conduction, the usual is to add vias inside the pad. And not just at the corners. Of course in this case, the vias will remain open. Depending on what's going on the pad itself, you may or may not need to have the pad plugged, which is something usually more expensive, or not even available with the process/manufacturer you'll be using.So maybe just tell us what's going to end up on this pad and what were the vias for.

author: ogden
author_rank: Super Contributor
timestamp: November 01, 2021, 05:59:48 pm
content: Quote from: SiliconWizard on November 01, 2021, 05:46:50 pmRight. The more you stick to "standard solutions" - the better, especially when 3rd parties involved.QuoteRight. "Thermal relief via" does not make any sense.

author: Rachie5272
author_rank: Regular Contributor
timestamp: November 01, 2021, 06:47:43 pm
content: A big capacitor sits on the pad. The vias are for low inductance stitching to a power plane on a lower layer. They were placed close because no one realized it would be a manufacturing issue.

author: ogden
author_rank: Super Contributor
timestamp: November 01, 2021, 09:08:48 pm
content: Quote from: Rachie5272 on November 01, 2021, 06:47:43 pmLet's be honest - it was you who did not realize it would be issue. If this is about low inductance then why just four vias in the corners? Even better question - why thermal reliefs for big capacitor that has no chances of tombstoning?

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: November 01, 2021, 09:15:06 pm
content: If it's a big capacitor, you don't need to worry about the picodust inductance of the pad connection.Chances are the capacitor's body size and construction totally dominates the circuit.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 02, 2021, 02:52:03 am
content: Yep.And, OTOH, if the layout can't be changed now for any reason, is this a problem if those 4 vias are not tented? Frankly? The board isn't going to fall out.