c4757p's frequency counter project - Page 1
Forum section: electronics / projects

author: c4757p
author_rank: Super Contributor
timestamp: August 02, 2014, 03:09:59 am
content: I recently sold the oscilloscope which was the host to my only decent frequency counter, so I thought I'd build myself a new one.This is just a personal project, though I do plan to share all the design files when I'm done. Here's my progress so far.Target specifications are loose, as this is my first FPGA project ever. I'll get the specs I get. It's got two channels, and I want to at least achieve a count up to 100 MHz on both (already tested to 160 MHz successfully before running out of signal sources), reciprocal counting for low frequencies, and inter-channel measurements like phase. The processor will also eventually be able to perform statistics like standard and Allan deviation natively. I've got an OCXO module as the primary reference (thanks, mamalala), as well as an external reference input.Many part selections are a bit odd, but driven by "I have this part already!", since it's just a one-off... I kind of want to do a Revision B with better part selections and design choices, but I don't think I have time.Stupid and/or questionable decisions acknowledged already:-Noinput power circuitry beyond a reverse protection diode. The input cap takes enough inrush to confuse at least one bench power supply's CC mode... Rev B would have inrush limiting and overcurrent protection. Stupid oversight.- Old FPGA. Had it on hand already...- Expensive 5V DC-DC module. Had it on hand already...- Expensive -5V DC-DC chip. Had it on hand already... A charge pump should do - I had more circuitry on that rail when I designed it.- No power switching other than the OCXO oven and front-panel display, so "standby" mode isn't quite efficient. Stupid oversight. Standby power consumption is about 1.2-1.5W.- Potentially unnecessary clock generator chip. Had it on hand already, wasn't sure if I'd want it...- Lots of signals run through the FPGA instead of to the MCU. This was planned back when I was going to use a soft processor in the FPGA.- Horrifying lack of digital test points.- Small microcontroller. IMO, a "microcontroller" is something that decides when to spin my clothes in my washing machine - I want more of a "processor", something a bit more competent to handle all that interfacing, so it can handle my quirks rather than the other way around. If there's a rev B, it will have at least an ATxmega, more likely a PIC32, or something similar, with lots of ROM, which can handle all the interface bits in a closer-to-SCPI-compliant manner (which requires floats or a close emulation thereof, some fairly large memory structures, etc).And one modification to the PCB so far:- Turns out I didn't really need that clock synthesizer (which I put on "just in case", as I already had a few); the FPGA's PLL was competent enough. Except - the 1:2 range from the 10 MHz reference clock to the 20 MHz system clock is too wide for it to use the system clock as a backup when no reference is present. I already have the MCU dividing the 20 MHz to 10 MHz, as 20 MHz is too high for it at 3.3V, so I just enabled CLKOUT and routed that up to the reference clock multiplexer with a short "bodge wire". It was easier than interfacing to the damned synthesizer, which was quite a pain the last time I played with it... and it's a step towards "rev B" compatibility, as I definitely won't be including unnecessary parts there.Schematic attached (one page got mangled, that's separate). More in a couple minutes... Currently the board is assembled and I'm in the process of writing the code.

author: c4757p
author_rank: Super Contributor
timestamp: August 02, 2014, 03:16:06 am
content: Render of outer two layers:(Yup, this cluttered board's got everythingandthe kitchen sink.)Not the best photo of the assembled board:Do I have enough capacitors?Nice and symmetric...That's all for now, I suppose. Lots of code to write...

author: Dajgoro
author_rank: Frequent Contributor
timestamp: August 02, 2014, 03:04:30 pm
content: How do you get a reading from it? I can see a usb connector. FTDI uart? Custom application? LCD panel?

author: c4757p
author_rank: Super Contributor
timestamp: August 02, 2014, 03:12:25 pm
content: Currently, I've got a SCPI-ish interface over the USB - but I've got a nice Noritake VFD waiting to be installed as the front panel, once the actual counter stuff is finished. That's what the FFC connector is for.

author: Dajgoro
author_rank: Frequent Contributor
timestamp: August 02, 2014, 03:16:14 pm
content: VFD FTW.Edit: Some people could mind about the ground plane not extending over the entire pcb area.

author: c4757p
author_rank: Super Contributor
timestamp: August 02, 2014, 03:22:39 pm
content: Quote from: Dajgoro on August 02, 2014, 03:16:14 pmThen I'll leave those people to play with the parasitic capacitance in the relatively high impedance input circuitry.Iwanted more control over that in that particular area.I've only broken the plane under the input attenuators prior to the first buffer (and also around the isolated USB section, but that's kind of obviously required...)Quote from: Dajgoro on August 02, 2014, 03:16:14 pmYeah, they're nice. One of my instructors at school was given a sample of a six-line character VFD and passed it on to me for this project, and it's a beautiful display.

author: David Hess
author_rank: Super Contributor
timestamp: August 02, 2014, 04:02:17 pm
content: One of the features I like with my older Tektronix frequency counters is that they have compensated input attenuators that work with standard passive oscilloscope probes.I would add negative overload protection to the JFET input buffer. Or is the input impedance at high frequencies enough as it is?How much drift does the buffer have without compensation? Maybe it is low enough to be insignificant but the operating point of the JFET is going to change with signal level.In the past I have considered adding universal timer/counter functionality to a GPSDO which already needs an interpolating time to digital converter.

author: c4757p
author_rank: Super Contributor
timestamp: August 02, 2014, 04:15:48 pm
content: Quote from: David Hess on August 02, 2014, 04:02:17 pmThis should too, it's relatively similar (1Meg || 15pF when set to 2X) - there's a 470 ohm resistor in series with the 15pF to tweak the response a bit, but it's close enough that it'd work fine.QuoteI'm not worried about it. The MMBF4416 can take up to -30V, which comes through a 2x attenuator, so that's -60V on the input. Add to that that the attenuator is switched to 10x mode by default, so -300V. For ESD protection, the minimum impedance from input to gate with the 10x attenuator enabled is 8.7k (unless, of course, dv/dt is such to get through the parasitic capacitance of the resistors...), so the current into the gate is at least limited a bit if this is exceeded.QuoteQuite a bit, but I'm not too worried about that. Nothing needs to stay fixed, the software can servo the threshold around to find the min/max values of the signal and center the threshold automatically. It's not really meant for vertical precision.Also - the buffer is designed for quite higher frequencies than what I think I'll actually be able to achieve - so if I everdomake a revision B, I can probably replace the discrete FET/BJT buffer with a FET op amp.(For higher frequencies, I'd consider a permanently installed RF prescaler in rev B on a third, 50 ohm input, also with an input amplifier rather than attenuator.)

author: marshallh
author_rank: Unknown
timestamp: August 04, 2014, 01:56:59 am
content: That pcb brings a tear to my eye.You dun good.

author: c4757p
author_rank: Super Contributor
timestamp: August 04, 2014, 04:04:07 am
content: He's dead, Jim!The FPGA (which has been rattling around in a bin for a couple years, god knows what's happened to it) appears to have suffered some overvoltage/ESD-related damage around the JTAG pins, which, after multiple semi-successful attempts at recovery, are now fucked.So, further development awaits the delivery of a new replacement.Now... where's my Widlarizer?

author: ThomasDK
author_rank: Regular Contributor
timestamp: August 04, 2014, 12:21:06 pm
content: Where did you get the pcb made?The silkscreen looks great!

author: c4757p
author_rank: Super Contributor
timestamp: August 04, 2014, 03:02:59 pm
content: ElecrowHere's an interesting one though - look what happened to these few NPTH. Some got plated, apparently randomly. I was under the impression that NPTH was typically done in a second pass after plating, so I'm not sure how that's possible...

author: German_EE
author_rank: Super Contributor
timestamp: August 04, 2014, 03:08:30 pm
content: It looks good, here are a couple of thoughts:1) Every man and his dog are making frequency counters with LCD and LED displays but we don't need them. A USB connection and an open window displaying a ten digit count on the PC is far better.2) Most designs that use a prescaler just divide the input by n, divide the clock by n and then leave it at that. If you use an ECL counter as the prescaler then you can load the eight bits (after level shifting) into the CPU and increase resolution. This will take you to about 1,2 GHz.

author: c4757p
author_rank: Super Contributor
timestamp: August 04, 2014, 03:10:49 pm
content: Quote from: German_EE on August 04, 2014, 03:08:30 pmBah, I do. I don't work on circuits glued to my PC. It's got the USB connection too, for when I want that. I want a front panel with full access to all (or, all-within-reason) of the features it has.QuoteYup. This also complicates the design for other measurements that I also want, like duty cycle and phase. A separate prescaled input strikes me as the simplest way to achieve what I want.

author: David Hess
author_rank: Super Contributor
timestamp: August 04, 2014, 03:36:33 pm
content: Quote from: German_EE on August 04, 2014, 03:08:30 pmAnd then one ground loop mistake propagates though the USB ground taking out the PC and maybe items connected to it. Galvanically isolated USB ports are not as rare as they used to be but they are hardly common or inexpensive.The monitor, PC, keyboard, and mouse also take up a lot of space if you have a dedicated system just to use the counter. I have the same complaint about newer oscilloscopes which use desktop operating systems requiring a keyboard and mouse.

author: c4757p
author_rank: Super Contributor
timestamp: August 12, 2014, 03:49:28 am
content: Bingo! New FPGA is installed - and also, a whole bunch of VHDL that I wasreally, reallysure should have worked, now does.Must have been something funny going on with the old one.Frequency, reciprocal frequency, period, duty cycle are all working.

author: c4757p
author_rank: Super Contributor
timestamp: August 12, 2014, 07:23:03 am
content: Project files. Presently pending some cleanup, they're the result of many coffee-fueled nights of frustrationMore than a few known bugshttps://github.com/c4757p/200a

author: bingo600
author_rank: Super Contributor
timestamp: August 12, 2014, 01:45:05 pm
content: That's a super nice project.I'm just starting with VHDL , and hope to learn some tricks from the source.What version of avr-gcc are you using ?I tried my own build of Atmels latest toolchaingcc version 4.8.1 (AVR_8_bit_GNU_Toolchain_3.4.4-Bingo-_201407191715)It warned two times , but i think it's a known error.Another really strange thing is that the resulting code were only 11k.Code:In function '__vector_18':serial.c:51:1: warning: '_vector_18' appears to be a misspelled signal handler [enabled by default]ISR(__vector_18) {^In function '__vector_19':serial.c:93:1: warning: '_vector_19' appears to be a misspelled signal handler [enabled by default]ISR(USART_UDRE_vect) {^avr-objcopy -j .text -j .data -O ihex fw.o fw.hexavr-size -C --mcu=atmega328 fw.oAVR Memory Usage----------------Device: atmega328Program: 11042 bytes (33.7% Full)(.text + .data + .bootloader)Data: 240 bytes (11.7% Full)(.data + .bss + .noinit)Then i switched to my "old trusty" avr-gcc 4.5.1 (that i , and many other on avr-freaks have used for a long time)gcc version 4.5.1 (GCC)I got no warnings , as expected.But unexpected was that the code was 2 x the size generated with the newer toolchainCode:avr-size -C --mcu=atmega328 fw.oAVR Memory Usage----------------Device: atmega328Program: 24542 bytes (74.9% Full)(.text + .data + .bootloader)Data: 496 bytes (24.2% Full)(.data + .bss + .noinit)I found a EP2C5T144 module in Aliexpress for $20http://www.aliexpress.com/item/ALTERA-FPGA-CycloneII-EP2C5T144-minimum-system-learning-board-development-board/1701452135.htmlAnd quartus seems to build fine with that board also.Code:Flow StatusSuccessful - Tue Aug 12 15:42:51 2014Quartus II 64-Bit Version13.0.1 Build 232 06/12/2013 SP 1 SJ Web EditionRevision NamefreqcountTop-level Entity NamefreqcountFamilyCyclone IIDeviceEP2C5T144C8Timing ModelsFinalTotal logic elements736 / 4,608 ( 16 % )Total combinational functions664 / 4,608 ( 14 % )Dedicated logic registers525 / 4,608 ( 11 % )Total registers525Total pins25 / 89 ( 28 % )Total virtual pins0Total memory bits0 / 119,808 ( 0 % )Embedded Multiplier 9-bit elements0 / 26 ( 0 % )Total PLLs1 / 2 ( 50 % )/Bingo

author: c4757p
author_rank: Super Contributor
timestamp: August 12, 2014, 01:51:35 pm
content: Quote from: bingo600 on August 12, 2014, 01:45:05 pmI'm just a bit less new to it than you are, so don't expect much.Though I guess one can always learnsomethingfrom a sizable collection of code that's known to work...QuoteI'm on Arch's 4.9.0 build. The "misspelled signal handler" warnings are a known avr-gcc bug. You'll note that I've taken -Werror out of the build flags at the bit that emits those.Edit: Err, no - seems those errors are gone now and I didn't even notice. Must have been fixed between 4.8 and 4.9QuoteMine compiles to 10392 bytes program code, 188 bytes data. I suspect it'll vary quite a bit from version to version, with the optimizations enabled. And I'm a bit surprised it's doubled in 4.5.1, though it's possible that some optimization feature (-flto ?) wasn't well supported.Edit: On my version, removing -flto increases size by fuck-all, to 11002/240; removing all optimizations entirely increases size to 19618/240.QuoteYup, that chip's basically identical to mine. (Though the only chip-dependent thing I have in there IIRC is the PLL configuration, so it should synthesize on damn near anything if that's changed)

author: bingo600
author_rank: Super Contributor
timestamp: August 14, 2014, 05:49:04 pm
content: avrlibc-1.8.1 has just been released.So i thought i'd give it a shot , and build avr-gcc-4.9.1 with avrlibc-1.8.1I'm using stock binutils 2.24 , so the "known" avr-size output isn't available.This is the new size (ram usage is data + bss = 188)Code:avr-objcopy -j .text -j .data -O ihex fw.o fw.hexavr-size fw.otextdatabssdechexfilename1035846142105462932fw.o/Bingo

author: c4757p
author_rank: Super Contributor
timestamp: August 23, 2014, 04:48:42 am
content: Rather small visible changes, but the fact that it's operating both channels together properly without kludges and without being held together with duct tape shows that it's actually getting somewhereI/O's nicer too, I rather like the engineering notation number formatting and parsing (supports both E+3-style exponents and metric prefixes).Clarification: the period measurement isn't broken; it's out drastically because I'm using the system clock as a reference clock (not wanting to power cycle the OCXO a million times). Its phase and frequency noise are about what you'd expect for a cheapo not-even-TCXO oscillator module... The measurement cleans up nicely when the reference clock is also somewhat clean.

author: doktor pyta
author_rank: Frequent Contributor
timestamp: August 23, 2014, 01:18:47 pm
content: My coleague designed a complete frequency counter. It was described in polish magazine Elektronika Praktyczna.Here You can find a link to his front end design.http://ep.com.pl/files/3249.pdf

author: idpromnut
author_rank: Unknown
timestamp: August 25, 2014, 05:40:11 pm
content: Quote from: c4757p on August 04, 2014, 03:02:59 pmHa! TagConnect… I was wondering if anybody used that. How do you like the TagConnect system, do you find it works well? (loose/slipping/misaligned pins, etc)

author: c4757p
author_rank: Super Contributor
timestamp: August 25, 2014, 05:51:53 pm
content: I've got no complaints about the system itself at all, it's great.I accidentally yanked the cable at one point and bent the alignment pins, but 1) I yanked itreally hard, 2) they bent back nicely, and 3) the actual contact pins were completely unharmed.However, it's fucking expensive. I got mine a while ago, I think they were on sale or something... might be worth it if you use it alot. They need to get the price down.One thing to note - the pogo pins actually press quite hard when the latching version of the cable is latched, and they were biting through the HASL a good bit. I added a thicker solder coat to the contacts so the exposed copper underneath couldn't start to corrode.

author: c4757p
author_rank: Super Contributor
timestamp: December 24, 2014, 09:08:30 pm
content: Now that school's out, I've got some more time to work on personal projects. Here's the front panel PCB, or at least a prototype of it:

author: timofonic
author_rank: Frequent Contributor
timestamp: August 20, 2015, 07:11:18 am
content: What about converting it in a module for your modular oscilloscope project?

author: c4757p
author_rank: Super Contributor
timestamp: August 20, 2015, 01:41:54 pm
content: Hah! Welcome to the project graveyardI definitely plan on the scope having a hardware frequency counter. Doesn't even need to be a 'module' per se - the AFE board will have enough on it, just needs a bit of dedicated HDL on the acquisition board.

author: TiN
author_rank: Super Contributor
timestamp: August 20, 2015, 02:25:56 pm
content: What are those J801, J901 ports receptacles? I saw these on few other PCBs for JTAG, wonder what is cable connector parts for it.It's neat to use, I'd love to know and use in my projects too.

author: c4757p
author_rank: Super Contributor
timestamp: August 20, 2015, 02:27:38 pm
content: Tag-Connect

author: TiN
author_rank: Super Contributor
timestamp: August 21, 2015, 10:32:05 am
content: Thanks!Little bit on expensive side tho. But looking neat, and no BOM for PCB

author: eneuro
author_rank: Super Contributor
timestamp: August 21, 2015, 11:01:43 am
content: Quote from: doktor pyta on August 23, 2014, 01:18:47 pmIt is up to 80 MHz "only"I'm interested in frequency counters close to 500MHz (434MHz), so this project looks intersting, but FPGA is a must in this design?There is some application notes behind those frequency counters (classic display could be fine for me)Agilent's AN200: Fundamentals of electronic frequency countershttp://cp.literature.agilent.com/litweb/pdf/5965-7660E.pdfhttp://cp.literature.agilent.com/litweb/pdf/5965-7661E.pdfAnyway, 1 wire optical interface to output measured frequency and send eg. to external display or PC to log frequency data from time to time on disk for futher analysis should be fine.I think, galvanic insulated (optical) interface could have advantage over pure USB, since it could be nice have a few kV insulation eg. between captured RF signals and PC/tablet equipment just in the case HV spikes hits RF signal via its antenas (eg.) close lighting hit during thunder storm, etc...Looking for much simplier frequency counter in the 434MHz range

author: seb785200
author_rank: Newbie
timestamp: September 30, 2016, 05:52:04 pm
content: Hello,Do you have source code for this project ?Best regards

author: tautech
author_rank: Super Contributor
timestamp: September 30, 2016, 06:12:27 pm
content: Quote from: seb785200 on September 30, 2016, 05:52:04 pmMember c4757p is no longer active here, check his profile.