How in the world do I make a split ground plane... - Page 1
Forum section: electronics / general

author: SolarSunrise
author_rank: Regular Contributor
timestamp: April 22, 2014, 05:08:56 pm
content: How do I define a split ground plane? I tried making two separate polygon planes but I can't create a star connection. Next I tried adding a keep out line but in return it generated a ton of errors. Is there a special way to do this? The Split Planes in tools menu don't do anything...Thanks in advance! Very tired here after laying out about 300 components...

author: toohec
author_rank: Contributor
timestamp: April 22, 2014, 11:12:35 pm
content: Your method depends on whether your GND layer is setup as an "Internal Plane" or "Signal" layer type. You can determine what the layer type is by opening your layer stack manager and looking at the type column for the desired layer. The split plane menu selections are only applicable to the "plane" type, and polygons are only applicable to normal "signal" layers.First off, here's Altium's documentation on Internal Plane layers:http://techdocs.altium.com/display/ADOH/Internal+Power+and+Split+PlanesIf your GND layer is setup as a Plane layer, first thing to know is that plane layer-types are negative layers where the presence of solid color indicate the absence of metal. By placing areas of color (either by fills, tracks, regions, etc.) you are removing metal from the plane area. The plane layer should start by default with a wide border around the perimeter of your board outline. If you double click in the middle of the board while on the plane layer, you can define the net used on that plane. If you completely isolate a portion of that plane by drawing a track around it, you can then double click in either of the two isolated regions to define each regions net (creating a split plane). It sound like your entire plane is the same net and you just want to limit the connection to a single location (for a star topology). In that case, you can just draw tracks to break up the area as desired, leaving the ends open where the star "net tie" will be. The split plane menu option shouldn't be needed since the planes will be rebuilt immediately as you edit that layer. Note: even though I said polygons don't apply to plane layers, polygon cutouts also work to void copper on plane layers, but I usually stick to standard fills/tracks/regions unless it's integrated into a part's footprint.If you have a standard "signal" layer, you can either 1) place multiple polygons with them overlapping where the star net-tie is, 2) draw a single polygon with the vertices defined to produce your central net-tie, or 3) place a polygon that covers the entire board area and add polygon cutouts to remove sections of the polygon and form the central net-tie. Make sure your polygon settings are made to pour over all same net objects or same net polygons, especially if using option #1. When using polygon cutouts, you will have to rebuild the surrounding polygons to see the results of the polygon cutout. Polygons depend heavily on your design rules, so it may take a while to setup your clearance/polygon connection style rules to get the results you are looking for.The plane option is the easiest but is more limited than the polygon method. The polygon method will allow you to do things that you can't accomplish on plane layers. If you have the capability, be sure to view the layer in 3D in single layer mode to make sure the layer ended up as intended. The 3D view helps a lot with the plane layers since the "negative" view can be deceiving.Good luck. Let me know if you have any questions.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 23, 2014, 12:08:32 am
content: 1. What he said,2. Don't. Just, don't. You're inviting trouble. A crappy layout on a solid ground plane will probably do much better than a crappy layout on a sawn-up plane; but a good layout, that takes thought either way.If you're already thinking well about a good layout, then nevermind.Tim

author: dfnr2
author_rank: Regular Contributor
timestamp: April 23, 2014, 01:28:09 am
content: What both of the above said. The caveat against splitting a ground plane without first thinking very, very, hard applies to the circuit grounds. However, it is very common to need a split ground plane to differentiate between chassis and circuit ground.Sometimes a portion of the periphery of the PCB is really more of an extension of the chassis than a part of the PCB circuit. For example, all your switches and connectors could be mounted at one end of the board. It is a typical practice to tie ground to the chassis (via conductive spacers, screw/washer/, fingerstock, etc.) and separate from the circuit ground. All the signals (even grounds) are brought across the gap with inductors, and any grounds are grounded on the circuit side. This is a common technique where ESD is a concern in small devices with plastic cases, and possible case gaps. It may be overkill for many applications, but this is a common reason to have split planes, both on signal and plane layers.Dave

author: SolarSunrise
author_rank: Regular Contributor
timestamp: April 23, 2014, 03:22:52 am
content: Quote from: T3sl4co1l on April 23, 2014, 12:08:32 amThe board that I am laying out is a precision ADC board. I believe it's a common practice to split analog/digital ground plane and join them in the ADC area.Quote from: dfnr2 on April 23, 2014, 01:28:09 amThat isn't the reason why I need a split ground plane but thanks for the tip! Will come really handy in the future!

author: SolarSunrise
author_rank: Regular Contributor
timestamp: April 23, 2014, 03:24:47 am
content: Quote from: toohec on April 22, 2014, 11:12:35 pmThanks for the long, detailed explanation! I already went through the techdocs but you've explained way better than those! I guess I'll have to just use polygon cut outs then for the split ground plane. Thanks again!

author: free_electron
author_rank: Super Contributor
timestamp: April 23, 2014, 04:37:16 am
content: A true plane is drawn negative. Simply select the layer and draw the cutouts with lines. Do not use tracks.Place line command. Simply draw a line with the width of the cut.No need to mess with polygons, net-ties, and other advanced stuff. You don't need it.Drawing on a plane is actually removing copper. What you draw will be removed. (As opposed to what you draw remains, on a normal layer)Now, that being said.How many layers in your board ? If you only make a double sided board with 1.6 mm thickness you aint got a plane ! The distance between dielectrics is simply too large to get any kind of plane effect unless you hit very large frequencies.The whole thing about splitting power return (ground is what is used to plant potatoes and other vegetables. There is no such thing as 'ground'. They are all power return pathways.) is to keep the digital, noisy return currents, out of the analog return currents.The problem woth an ad converter is it compares an unknown input with a ladder of references (doesnt matter what technique is used. Its all comparing to references) nkw, a reference has a top and a bottom. Inject crap at the bottom and it goes to snot just as much as it would go to snot injecting crap at the top of the ladder.There is another aspect. Shield.The difference between what is commonly called 'ground' and a shield is that no current flows through a shield, apart from the unwanted current.The drawback of a shield is that it adds stray capacitance. If that is unwanted you need to tie the shield to a low impedance version of the to-be-shielded signal. At this point we call it a guard.Its a bit long to explain in a few words. You really need to see a drawing. I'll try to make a small video explaining these concepts.

author: sacherjj
author_rank: Frequent Contributor
timestamp: April 23, 2014, 01:17:45 pm
content: After hearing talks and seeing simulations from some of the brighter minds on these subjects, I'm tending to agree with their ideas: Assume data sheet PCB layout is wrong until proven right. Energy in a PCB flows in the electric and magnetic fields, not in the conductors. This is why signal speed is dictated by dielectric constant of the material. A high speed signal appreciatively couples to the ground plane directly below it and generates an immediate opposite current. For anything but very lowspeededge rate, this is already kept right near the trace. So a split plane to isolate analog from digital does almost nothing good. But can do plenty bad.Position your chips and circuits in isolated blocks and cross as if you made a split plane. Current will flow in the closest return path to the conductor it is in. Anything over 100 kHz is running DIRECTLY under the signal. Split planes DO NOT help with this. And any place where you run a conductor across a split, you just made the problem 100x worse by not having a return path.If everyone understood that fields are what is important, they could more quickly design proper EMI layouts intuitively.

author: toohec
author_rank: Contributor
timestamp: April 23, 2014, 05:36:21 pm
content: Quote from: free_electron on April 23, 2014, 04:37:16 amWhoops, thanks for the correction. I originally meant a line. You can't even place tracks on plane layers; attempting to place a track will force you to the nearest standard signal layer.And of course I didn't discuss the design aspects or other considerations of splitting up ground planes. As suggested above, for the most part I don't split my ground planes. I find that a contiguous ground plane produces better results then adding semi-isolated regions for analog, digital, switcher ground, etc. Just pay close attention to the signal layer routing.

author: Kjelt
author_rank: Super Contributor
timestamp: April 23, 2014, 05:50:56 pm
content: Quote from: free_electron on April 23, 2014, 04:37:16 amlooking forward to it, please post the url here

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 24, 2014, 12:00:37 am
content: Quote from: sacherjj on April 23, 2014, 01:17:45 pmAlso need a "nodding" emote hereQuoteIt follows that:- If you insist on splitting the plane, keep all the traces associated with that regionwell within the bounds of the region.- If you ever, EVER run traces over splits, you're going to make an awful mess.- This applies to 2-layer boards as well: suppose you have ground pour on the top and bottom, and two long traces crossing at right angles. The image of those traces, the negative space they create in the top and bottom pours, behaves in the exact inverse way the traces do. Opening a slit creates a slot antenna (or at low frequencies / impedances, it behaves as an inductance, associated with the length and width of that slot), which couples directly to the trace crossing that slit. At least three vias are required (or four, if you are compulsively symmetric) at this intersection to short together the pours and ameliorate the effect of the slots.- This doesn't necessarily apply to multilayer boards, if multiple pours are used which overlap for a considerable area. Overlap means relatively high capacitance (or, a low impedance transmission line). You can have traces crossing from one pour to another, so long as those pours are, themselves, well supported above or below by other pours or bypass capacitors.In analogy to the two-layer ground stitch, the best place for bypass caps between pours is at the edges of the pours, where signal buses cross from one domain to the other. An example might be, a four layer board with signal traces on the top and bottom, a solid ground inner layer, and multiple pours on the second inner layer, say for different voltage domains (3.3V logic, 5V "HV logic", 12V power, etc...). The traces running over the power layer will deliver an image current into the pours on that layer; ideally, the pours should be bypassed to each other, in the places where signals cross them, for best results.Since the underlying ground is solid, bypass between regions may not be necessary. Signal quality at 3.3 or 5V isn't a big deal anyway: we're talking maybe a single volt, down to fractional volts, for any bounce resulting from these differences -- hardly a concern for "massive" 3 or 5V logic signals!Note also, differential logic signals don't produce a net image current between planes, if they are routed together and transition at the same time. The trace-to-trace distance need not be small, as long as their transitions cross the plane at about the same time and place. By the way, always treat differential signals as individual lines, first and foremost, including controlled impedance and length matching. The differential coupling between adjacent traces is relatively weak.From personal experience, I've laid out a high speed 12 bit ADC with LVDS interface, on a board including various 3.3V and 5V logic, and converters for the various supplies required. The ADC section was laid out on one side of the board, digital logic entering one side and analog (including filters and diff buffers) opposite. Solid ground and power (3.3V) planes inside the (4 layer) board, plus extra copper fill (top and bottom) around the ADC section. There was no apparent correlated noise in the system, only a few LSB white noise, attributable to the buffer amp.If, for some reason, that board had the DC-DC converters beyond the analog side, so all that power had to cross underneath the ADC to reach the rest of the digital stuff, it might've been much worse. I still wouldn't consider splitting the planes (for example, such a layout might be necessary in the case of a very narrow, long board), because noisy signals (like power and CMOS logic buses) can be routed alongside the circuit, away from direct noise. Note that, if the circuit board is laid out one block at a time (ADC here, MCU there, DC-DC over there...), there need not be any signals crossing between regions (they're all bused up and around instead), so the planes could be slotted anyway and it wouldn't make any difference. When your layout follows this approach, you are at the Zen of layout, where you could slot it, but you won't.There are still plenty of reasons to split planes -- layout should take care of AC, but DC will still follow straight-line paths. Extremely sensitive AC circuits may find residuals as well, especially on a complex board where you can't afford to arrange blocks in a simple (bus or star) arrangement. Even thermal currents can benefit from splitting -- the board itself in this case, not just the copper: very sensitive references are often routed out on three sides, to prevent mechanical stress and thermal gradients from affecting it.Galvanic isolation is a rather more dramatic example, where your planes are split on all four sides, so the isolated circuit becomes an island of course. This obviously avoids ground loop, but can create EMC issues: the island is a small capacitance (or a lot, if you have a lot of components bridging the isolation -- optos, transformers and so on), which can resonate with cables and such. Common mode ferrite beads and damping components (Y1 type capacitors spanning the barrier, perhaps with ferrite beads or resistors in series) are used to control this electromagnetic situation.Tim

author: SolarSunrise
author_rank: Regular Contributor
timestamp: April 24, 2014, 09:47:18 am
content: Quote from: free_electron on April 23, 2014, 04:37:16 amYou are absolutely right about 2 layer board not having any planes. For my board, I meant polygons.Virtually my EMC knowledge only consists of the information in this website (note I'm just a hobbyist):http://www.learnemc.com/tutorials/guidelines/Worst_Guidelines.htmlFrom that page it says that:QuoteMy board samples high precision (0.05uV bit resolution) at a low frequency (ordinarily at 500sps, max 30ksps). This paragraph says that digital circuits have to have a separate ground return to avoid contaminating precision low frequency signals. That's what I have done: I've split the ground polygon and made a star point connection at the power supply junction.I can be totally wrong here. Please correct me if I am!

author: gregariz
author_rank: Frequent Contributor
timestamp: April 24, 2014, 10:03:06 am
content: My take on this topic is when you make the splits make sure that you join the splits with a number of unpopulated footprints ie 1206's between the splits at regular intervals. You will have in mind at some point where you want the common ground return to be but in practice its somewhat of an art to get it ideal so having unpopulated footprints allows you to place inductors (low freq ground connection) or caps (high freq ground connection) and then move them around thus controlling the current flows until you can get any noise issues you may be having under control.

author: sacherjj
author_rank: Frequent Contributor
timestamp: April 24, 2014, 08:34:31 pm
content: Quote from: SolarSunrise on April 24, 2014, 09:47:18 amLayout your chips in areas of signal type. Analog on one side. Digital on the other. And only join them where you have to. Now, any digital circuit with have the ground plane current DIRECTLY under its conductor. It is going to run where the inductance is less and the capacitance is greatest. Splitting power planes can be good or bad. You want a completely flooded, low inductance power path. And you want the power and ground planes as close together as possible.

author: reagle
author_rank: Unknown
timestamp: September 26, 2014, 12:45:30 am
content: To revive this thread- how would you go about adding internal plane keepout to a footprint? Say I am making antenna footprint and need to keep a certain window through all layers. Ideally I'd like the footprint to enforce that, so I added Multilayer polygon pour keepout but my internal layers are planes so they ignore that. Is pouring planes manually the only option?

author: toohec
author_rank: Contributor
timestamp: September 26, 2014, 08:51:15 pm
content: Quote from: reagle on September 26, 2014, 12:45:30 amEven though a polygon pour cutout does work as a plane cutout when directly placed on a plane layer, it doesn't function as a plane cutout when placed on the multi-layer layer. I'm not sure if this is a bug or intentional.You will need to either 1) add the plane cutout manually to your PCB after the part is placed, or 2) add the appropriate plane layer to your layer stack manager in your PCBlib and add the cutout to the plane layer in the footprint. However adding internal layers/planes to the footprint can potentially result in extra-layers added to your PCB stackup if the PCB and PCBlib stackup don't match completely. If you do this, it's best to export your layer stack from your PCB and import it into your PCBlib to ensure they match. However, this may limit you to using the component footprint on PCBs that have a similar stackup structure. The stackup will be applied to all parts in the PCBlib, so you may want to limit this part to its own library. Because of the potential for trouble, I would probably recommend just adding the cutout to the PCB manually. You will just have to be diligent about adding the cutout to plane layers on any PCBs in the future that use this footprint. It's all part of the review process.Another option is to change your plane layers on the PCB to signal layers with polygons. That would allow the multi-layer polygon-pour-cutout in the footprint to function as desired on all the internal layers.Perhaps someone else has some further insight.