Bypassing Loads Under Constant Current Efficiently  - Page 1
Forum section: electronics / beginners

author: TheDood
author_rank: Regular Contributor
timestamp: December 05, 2019, 09:03:24 am
content: I'm playing around with LTspice and had some questions maybe someone can answer for me.I'm simulating a capacitve power supply with a few Zener's as a dummy load. I'm trying to figure how to bypass the constant current source efficiently to reduce current flow through the Zener string. When I change the filter CAP placement I get different current characteristics through the diode string.If I tie the +CAP lead into the cct before (NM2 + Schottky1), the current through the Zener string "throbs." If I tie the +CAP lead into the cct after the (NM2 + Schottky1), then the current through the Zener string is more consistent (~20-40mA ripple depending on duty cycle, no throb).I've used 120Hz as the pulse frequency and have adjusted the "time on" between the 2 layouts to measure ~108mA average current flow through the Zener string. This ended up being 0.8ms "on time" for the layout with the +CAP lead tied in before the bypass, and 5.3ms "on time" for the layout with the +CAP lead placed after the bypass.When the zener strings in both layout scenarios flow the same average current, the wattage burned across the bypass differs between the 2 layouts. When I see the "throbbing" current, or when +CAP lead is tied in after the bypass, the wattage burned across (NM2+R1) is ~0.595W, and the average wattage burned across load is ~2.83W, for ~82.5% efficiency (disregarding other components atm). When I see the more stable current, or when +CAP lead is tied in before the bypass, the wattage burned across (NM2+R1) is ~5.75W, and the average wattage burned across load is ~2.82W, for ~33% efficiency.What I'm trying to accomplish is a couple things. I'd like to utilize the layout with the greater efficiency, but then I'm stuck with the throbbing current. I'd like to learn how to, or be pointed in the direction on how to remove the "throb," reduce current ripple (without using bigger coils), and decrease the burned wattage on the bypass.(Disregard The other 3 Zener strings, they're just extra dummy loads)Thanks

author: Ian.M
author_rank: Super Contributor
timestamp: December 05, 2019, 12:12:18 pm
content: What's the end objective? i.e:What sort of load are you trying to drive and what are its voltage and current requirements?Do you have any power factor or efficiency constraints?Your schematic is a mess and makes it extrtemely hard to understand what's going on. I've de-f**ked it so its actually readable with all component designators and values visible in the standard LTspice default font size, converted decimals with excessive zeros after the d.p. to use engineering multiplier suffixes (based on S.I suffixes, see help file at 'LTspice®':'Introduction':'General Structure and Conventions') and shuffled stuff around till its in the conventional layout for a schematic: input on the left, output on the right, most positive rail at the top, most negative rail (or ground) at the bottom so I could attempt to follow the flow of your logic. I haven't sorted out your reference designators - generally its preferable to go with the default LTspice LETTERnumber style and if you edit them to be more meaningful, keep the initial capital letter, only changing it if it grossly offends (e.g. an IC that comes up as Xnmay need changing to Umfor consistency with other IC numbering on your schematic). Also, if you need multiple identical diodes in series or parallel check out instance parameters N and M in the help file at 'LTspice®':'Circuit Elements':'D. Diode' - you can model an array of diodes as a single component!Once I had it sorted enough to follow it, my opinion of it is: If I wanted it to do anything useful, I wouldn't start from here!

author: Zero999
author_rank: Super Contributor
timestamp: December 05, 2019, 12:14:13 pm
content: I couldn't understand that schematic, so I redrew it.What are you trying to achieve? You won't reduce the current consumption of this circuit like this. Yes shorting out the rectifier can take the load off the zener diodes but why?Just some hints:Avoid hiding things.Try to put the ground node at the bottom.Often it's more clear to use more than one ground connection.Use SI suffixes, rather than loads of decimal places.Also why take photographs of the screen with a camera? It results in huge files! Take screenshots with the print screen key. It's also possible to copy schematics to the clipboard, paste them into image editing software and save them in a compact file format. The image below is only 4.2kB.EDIT:Ian beat me to it, but I'll still post it anyway. He has a good idea with N=4;series, which means four in series. It does make the schematic more compact, at the expense of being slightly less self-explanatory.

author: Ian.M
author_rank: Super Contributor
timestamp: December 05, 2019, 12:45:20 pm
content: By the way, sticking comments in component parameters like I did for D5:N=4;seriesis not particularly well supported in LTspice.Its only legal if its the LAST thing on the netlist line for the component so you can only comment the last parameter.Also, you cant put a comment on a subsequent blank line in the generic component editor as without a parameter to anchor it, it will get deleted.Many of the special purpose component editors may delete comments.For schematics and waveforms, a 16 colour GIF or PNG is usually adequate, and *PLEASE* take time to crop the crap!N.B on-screen data for channel and timebase settings in DSO screenshots is *NOT* crap, please don't crop what we need to make sense of your real-life waveforms!

author: TheDood
author_rank: Regular Contributor
timestamp: December 05, 2019, 02:04:04 pm
content: Ha, well now I know. Input on left, output right, positive top, GND bottom, scientific notation, multiple GNDs and no hiding, thanks guys. I use my phone data for posting and lazied out with the screenshots (instead of transferring all the files from cpu to phone), I'll also crop the excess next time. I've picked up some helpful pointers and will implement in the future, thanks.The load will be LEDs of different layouts. I figured series Zener's having the same avalanche V compared to the actual LED string Vf, would simulate in the same way. Maybe this is naive? I didn't want to spend the time researching how to build all the LEDs I wanted to simulate, though I did see a few LEDs in the diode drop down and will implement the "instance parameters" function to create strings of more likeness to the actual on the next sim.I've not turned my attention to the PFC of the cct, but have intentions for a design with a PF >89%, and an efficiency >93% under the least favorable dimming scenario. This particular cct is attempting to simulate a string of LEDs with a Vf of ~26/27V @ 345mA.Believe it or not but the schematic I posted was actually cleaned up considerably from what I was using lol. I've run countless trials and scenarios trying to gain a fundamental understanding and it gets messy, sorry for the confusion. I used the screen shots because they had the trans patameters listed which I had changed since the first set of file transfers from cpu to phone, it was to help you guys calculate averages (if you downloaded the .asc file) easier having the waveform shown peak to peak. Everytime I tried to zoom select it would adjust itself so that it wasn't magnifyimg only the selection but a little bit more, so it seemed changing the trans start and stop time was the only way I was able to achieve peak to peak waveform ranges for more accurate average calcs. I also couldn't figure out how to unhide things after I had hid them, I then got confused on which label I was amending ect. At least you guys were finally able to make ends and pieces of what I was testing lol I appreciate the info on implied cct design.Any ideas on how to increase the efficiency? I'm thinking that feedback should be used but haven't given it much thought as to how it would be implemented..

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 05, 2019, 02:15:20 pm
content: What's the MOS for? Looks to be shorting out the supply. Not very efficient.What's the enormous inductor for? Do you actually have one sourced?You can't get high PFC from a capacitive dropper. This is due to the old fashioned kind of PFC, the phase shift. You can correct it with an inductor, forming a resonant or impedance-matching network at 50 or 60Hz, but then you need another enormous inductor.You can't avoid the "throbbing" (mains ripple) without an energy storage component. You also can't get good stability in light output by just bypassing the LEDs' supply -- LEDs are nonlinear. With bias current, the dynamic resistance is low, effectively shorting out the bypass cap for small changes in voltage; voltage drops relatively quickly. As voltage falls, current falls exponentially, and the LEDs dim significantly. The voltage ripple can be slight (say 10-20%) while the light modulation is nearly total (99%).Both of these suggest a standard approach using an active PFC front end followed by a constant current source, which can be switching, linear or passive, the first option of course having the best efficiency.Have you considered just buying the LED driver module?...Tim

author: TheDood
author_rank: Regular Contributor
timestamp: December 05, 2019, 03:14:58 pm
content: Without the MOS bypass the efficiency approaches 99%(?), and the current ripple is mitigated and precise within 10mA, and no "throbbing" (fading on & off every second). There's only minimal V drop across the bridge and other components. I like that, but I'd like to have the option of dimming too. I thought that as long as the filter CAP was not allowed to discharge through the MOS when bypass was engaged, that the efficiency would be more or less maintained during dimming (obviously drop a bit as it was dimmed). I'm trying to reduce V across MOS when bypass is engaged, because only ~0.45A RMS [120VAC/(1/377·1e-5Ω)] should be flowing through a bridge and FET, and shouldn't require much V or burn much wattage. <-- This was my assumption and the principle I'm working from??I didn't know how else to smooth the current (or if it's needed, I thought it would increase LED longevity, but if the peaks are within 80% of its max rating, would smoothing just be a fruitless endeavor) and at 120Hz it seemed that the large inductor was needed to achieve the smoothing. Yes I've a few sourced (100mH common mode choke, $4/) but I'd rather not use if there's a better more cost effective and efficient solution. I've looked into an inverted buck-boost design but not sure Ill be able to achieve any better efficiency. Ill have to look into your comments. Light bulbs are not noticeably flickering at 60Hz (120 spikes per second) so I figured even if the mA dropped to 0 through the LEDs, that at 120Hz you'd not see any flicker. The filament takes time to cool, but likewise the phosphor coating flouresces on PC LEDs for while after current has subsided. I doubt you'd notice it at the same 120Hz, but maybe this is wrong?I could buy a premade driver and not ruling it out, though I'm trying to determine if building my own can be more efficient, ect.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 05, 2019, 04:22:06 pm
content: You'd be better off dimming by using an array of current-limiting capacitors and SSRs (a power DAC, as it were).Common mode chokes saturate above some mA, beyond which their inductance quickly drops to a tiny fraction of the zero-bias rating. There are also ground-return chokes, made the same way (a single winding on a high-mu core); they are intended to saturate under fault conditions, providing a low impedance ground path, while under normal conditions choking high frequency currents (which can be sometimes beneficial, hence their existence).You need to shop from inductors -- specifically, one rated for saturation current higher than the peak current seen in circuit.You also need a proportionally larger inductor at lower dimmer settings. Size it for the lowest current you wish to maintain continuous light output on.An inductor can indeed serve as the energy storage component, but very large inductances, rated for reasonable currents (e.g., 1H and 100mA), are neither cheap nor compact. (They are at least available, amazingly enough -- Hammond Mfg. for example.)Incandescent lamps do modulate some, though you usually need an instrument to do so -- the hum is clearly audible with a photodiode for example; it's hard to observe this by eye. Other traditional sources, like fluorescent lamps and discharge tubes (sodium, mercury vapor, halide) are easier to see, tending to leave a "string of beads"-like track in your visual field when you move your eyes quickly past them.LEDs respond quite quickly, the blue source having a useful bandwidth in the 10s of MHz if driven properly, and the yellow phosphor having a decay rate in the 100s of ns. Next time you're walking past a string of LED xmas lights, see if they flicker as you move your eyes around.Tim

author: Ian.M
author_rank: Super Contributor
timestamp: December 05, 2019, 04:58:05 pm
content: Capacitive dropper PSUs just aren't cost effective if you need more than a few tens of mA, maybe 100mA on the high end. $5 just for the cheapest 10uF class X capacitor to get 400mA DC, + all the other components required means the BOM cost is unlikely to be under $10 and by the time you've designed and assembled it a $40 commercial product would be a better deal.To get back in and unhide stuff, Ctrl-RightClick a component to open the generic component editor rather than any component specific special purpose one.If you need to examine or make measurements on highly zoomed in waveforms, place the SPICE command:Code:.opt plotwinsize=0on the schematic to disable data compression. Caution. the .raw file size will bloat tremendously if the runtime is long (>3 orders of magnitude) compared to the period of the highest frequency signal in the sim.

author: TheDood
author_rank: Regular Contributor
timestamp: December 06, 2019, 11:23:13 am
content: What are some basic guidelines to inductor spacing and/or orientation? Is there some sort of linear relationship between (A/mH) & the proximity in which you can place other inductors or other magnetically influenced components? How close can capacitors be placed? What types of generic design limitations (utilizing inductors) should I keep an eye out for?If I've 2 identical inductors, both common mode choke types with the core standing/mounted perpendicular to the PCB, can I increase the total inductance over using a single standalone choke, if I placed them side by side within close proximity to each other, in such a way that that their cores' flux direction mirrors each others, to the point that if the cores were fused together that the mag flux would be doubled rather than cancelled? What effect would this orientation have?

author: Ian.M
author_rank: Super Contributor
timestamp: December 06, 2019, 11:28:53 am
content: I'd suggest you repost your inductor question as a new topic with a more appropriate title e.g. "Inductor proximity effects?"

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 06, 2019, 02:54:29 pm
content: Mutual coupling between board level components is weak at best (k < 0.05?). It's hard even to contrive custom parts that have strong coupling, without making them a single component as such. (Note that embedded inductors and etc. (planar magnetics) can do significantly better, but aren't really components either.)Capacitors simply have the capacitance between their outer foil/housing, a few pF at most.Tim

author: TheDood
author_rank: Regular Contributor
timestamp: December 07, 2019, 07:03:34 am
content: I was simulating different configurations and came across another "throbbing" waveform. I decided to try to get to the bottom of it and found that my frequency calc was not precise enough at only 0.00833s/period. I added a few more sig figs and the "throbbing" went completely away.Current sim attached if anyone is curious. I'm trying to figure how to calculate power dissipation across the capacitors? The X1 cap shows +/- power dissipation, so the average is misleading? Next step is to switch out rectifier diodes for FETs, right now the biggest power waste is at the bridge, I tried using NMOS's for my return leg of the bridge, tieing the gates to the drain but It didn't work, I think maybe Ill have to implement a few OP-Amps??

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 07, 2019, 08:54:01 am
content: FYI, gate voltage is wrong, those NMOS are in for a big surprise.Capacitors don't dissipate average power, or capacitance doesn't anyway. Any ESR you can calculate the dissipation of by taking the current through the component and P = I^2 R.A synchronous rectifier into a filter choke, isn't so bad, but you need a controller to do it into a capacitor.Tim

author: TheDood
author_rank: Regular Contributor
timestamp: December 07, 2019, 09:49:53 am
content: Quote from: T3sl4co1l on December 07, 2019, 08:54:01 amThanks Tim you're always very helpful, can you help me understand what you're saying, not enough gate V, or too much? I'm only simulating with parts that are preloaded into LTspice to get a general idea, though I just looked up the IRFP4668 and it gives a Vgs(th) of 3V - 5V, and a max of +/- 30V. If I ever were to use a component like this would I want a higher gate V, maybe 12V?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 07, 2019, 11:58:58 am
content: Measure Vgs in the simulation and you will see what is wrong.Tim

author: TheDood
author_rank: Regular Contributor
timestamp: December 07, 2019, 07:03:01 pm
content: Thanks Tim,Is 7V too low or too high? I get +7V - 0V when I've probed. Its actually the waveform I was intending if I'm looking at it correctly, I just don't know the Vgs typically required for switching 60V RMS (is that roughly accurate?, half of 120 sine wave?), 170V peak, with a 200Vds,130A, and 8mΩ Rds(on) rated FET? The FET gives a Vgs(th) of 3V-5V(max), so maybe a higher gate V, so saturation happens quicker?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 07, 2019, 07:38:11 pm
content: You probed G-S across M1 or M2 in the above diagram and measured only 7V??Tim

author: TheDood
author_rank: Regular Contributor
timestamp: December 08, 2019, 09:30:21 am
content: Quote from: T3sl4co1l on December 07, 2019, 07:38:11 pmNope haha, I realize I didn't measure the difference between the 2. I figured the difference would be equal to the size of the pulse V. I found some interesting results though.It seems that both M1 & M2 hold a negative voltage at their source of about -3.8V-ish until the pulse triggers the Gate, which at that point the NMOS Source V comes up from -3.8V-ish to +0.8V-ish. I assume 0.8V must be the diode Vf?In reality, on average, there's a 2.19V delta between NMOS Gate & Source, but it can be as large as 7.8V during Gate pulse trigger.What I'm trying to conceptualize is why the NMOS isn't always on if it has a typical Vgs(th) of 3V? Wouldn't a -3.8V at the source pin, coupled with a 0V measurement at the gate, effectively satisfy the 3V Vgs(th) needed to begin to turn on? Is it turning on? Also, the pulse generator seems to have current bounce through it? It seems when the NMOS Source side diode is blocking +V, but a pulse comes at its gate, that current travels from the NMOS Drain pin through the NMOS, to the NMOS Gate and then onto the pulse generator? It looks like there's a shove of current from drain to gate to pulse generator and then bouncing back, is this what you were talking about?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 08, 2019, 10:04:10 am
content: Well, the most important part is, the sources are alternately pulling above and below what you've declared as GND. The AC lines are only alternately connected to ground via the diode bridge. Half the time they're high up, supplying whatever Vout is, give or take. If you're supplying a 30V load, goodbye Vgs(max). Or say a line transient comes along, or someone just turns it on during a line peak.Tim

author: TheDood
author_rank: Regular Contributor
timestamp: December 08, 2019, 11:12:52 am
content: Quote from: T3sl4co1l on December 08, 2019, 10:04:10 amMan I'm sorry, I'm not trying to be dumb here, but Im still missing it.Is the simulation wrong? I just added more diodes to create a load Vf of ~62V. I still only get 7.8V max delta between NMOSsg (though a bit more -V at source pin, maybe -4.4V max)?I'm not comprehending how the load V will effect Vgs? I'm designing around single phase AC.As far as the surge from a mains spike, can't I use a TVS? And I figured the load cap would help during a turn on while mains was at peak V. But maybe Ill have to devise a way to create a small delay between mains input and load energizing, like a resistive short but only for a second till X1 cap is impeding like intended? Also, I was going to implement a type of GFCI or a re-setable trip to mitigate the need for a replaceble fuse.EDIT:If I put the coil before the load, would that help current surges more than if placed after the load?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 08, 2019, 11:51:42 am
content: Oh right, body diode holds source down, and the series diode disconnects the high side. Nevermind!You still have a number of fundamental problems, with the C dropper, and dimming, which are why this method isn't used for more than a very small amount of power (a few watts?).Tim

author: TheDood
author_rank: Regular Contributor
timestamp: December 08, 2019, 12:18:38 pm
content: You guys have been very helpful in my comprehension thus far, thanks.Feel free to point out any issues with capacitive droppers that I might not know about. I've seen lots of negative comments about them, how they are unsafe, inefficient ect, but it seems to me you can add safety regardless the type of power supply, and I'm missing where they're inefficient. The biggest thing I'm guessing is the PF, but residents in the states dont pay for PF. Even still, I'll probably look into what it will take to correct it because it will probably gnaw at me after awhile lol