PLL reference sync module? - Page 1
Forum section: electronics / projects

author: cncjerry
author_rank: Unknown
timestamp: January 02, 2022, 08:23:50 pm
content: I've been playing around with various PLL circuits to sync a 10Mhz Wenzel TC/VCXO to a Rubidium standard. I've tried several with somewhat good results.I recently built Bill Riley's:http://www.wriley.com/A%2010%20MHz%20OCVCXO%20and%20PLL%20Module.pdfand the Wenzel (mid page with 4069 and 4016):https://wenzel.com/documents/tuning.htmlI also built another using dual output DACs that was more aligned with a GPSDO as it used 1PPS.I'm wondering if there is a standard board/module that takes in two signals and produces a tuning voltage? This would be like a GPSDO without the GPS or DO, just a PLL or some other tuning circuit. I can just use the Wenzel circuit as it is cheap and works as well as Riley's, at least from initial testing but I have a couple of these and thought if there was a module I might go that route.Thanks.Jerry

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: January 03, 2022, 12:49:08 am
content: Something like this? It is more like a kit. Use only what you want:- home for 10811A, MTI-260, Morion MV-89, 100 MHz ECOC 2522, CVHD-950 and otherswith pos/neg regulation sense.- Xilinx Coolrunner CPLD ($2.50) to create local 1pps- 1pps CMOS 50 Ohms driver- Can lock to external reference frequency. 2FF phase/frequency comparator in CPLD- Not yet implemented: locking on incoming 1pps. Foil capacitor for large time constant- OPA140 FET opamps for control loop without loading the foil capacitor- 2 Linear Tech sine to square converters, for VCXO and reference- 10 turn pot to adjust nominal frequency- TL431 reference if the VCXO does not have one- output amplifier to 20 dBm. Enough signal even after power dividers.- output amplifier can be used as frequency doubler with only slightly less output power.- notch filters with crystals or toroids to remove harmonics or sub-harmonics.- power meter for level of incoming reference clock- VHDL source for 1pps and phase detector (or standard JEDEC programming file)- can be used as a test bed for a blob of logic with enough test points- Gerber files available, tested at JLCPCB and others- Minimum usage is just bare mechanical mounting. Some have done that. Low-cost enough.

author: billkatz
author_rank: Newbie
timestamp: February 15, 2024, 10:21:03 pm
content: I know this is an ancient thread, but...Gerhard - do you sell a board - either raw or assembled of your circuit? Or is there access to CAD files to modify it and get it built?cncjerry - Did you produce CAD files for the Bill Riley design?Any conclusions on a good circuit for this? In my case I'd like to lock an HP 80211 OCXO (good phase noise) to a Symmetricom X72 Rubidium standard (good long term accuracy, lousy spurs...)

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: February 16, 2024, 07:47:54 am
content: No, I don't sell them. but you can get a board or two for free.They have been manufactured at JLCCB.Sending empty boards to US in a simple letter was quite a disaster,I got most back. :-(Files are available in Altium format. The Xilinx Coolrunner CPLDis EOL but seems still to be available at DK and Mouser.

author: billkatz
author_rank: Newbie
timestamp: February 19, 2024, 10:08:51 pm
content: I'd love to get more information (design files and maybe even a board) - I sent a PM with my contact info.