selection of decoupling caps in a circuit powered by a LDO regulator - Page 1
Forum section: electronics / beginners

author: Clear as mud
author_rank: Regular Contributor
timestamp: December 05, 2014, 04:36:29 am
content: I am working on a design for a driver board for multiple strips of WS2812 LEDs. They're the Chinese RGB LED chips with data input and output so you can string them together and address each one individually to set brightness and color. I am planning to build this driver board with a low-dropout regulator for the logic, but I don't have much experience with LDO regulators. In the past, I've used standard linear regulators like the 7805, and it was not necessary to pay much attention to capacitors. Now I am trying to use theLP2951 low-dropout regulator, and it has a specified minimum and maximum ESR for the output capacitor. That didn't seem to be a problem at first. To regulate to 3.3 volts, I chose a 4.7 uF capacitor from AVX, theNOJA475M010RWJ, for the output. It is a niobium oxide capacitor rated at 4.7 uF, 10 volts, and has ESR of 3.1 ohms max. The specifications fall well within the range from the LP2951 datasheet.Where I see a potential problem is in my selection of decoupling/bypass capacitors near my digital logic chips. I have four chips on the board, only three of them powered by the LP2951. I have a PIC16 microcontroller, a single-channel schmitt-trigger buffer, and a shift register. The signal then goes to a HCT family logic chip powered from 5 volts for level conversion. The whole circuit board is only 0.7 by 3.6 inches.When initially drawing the schematic, I put in a couple of 0.1uF capacitors near the chips. I haven't built the circuit yet. I did simulate the logic to make sure it works. Although I planned to use 0805 ceramic bypass caps, I am beginning to wonder if I need to select different bypass capacitors or leave them out, because of the low ESR of surface-mount MLCCs? I have done some searching for advice on this issue, and I found a recommendation to only use ceramic bypass capacitors if they are some distance away from the regulator, to allow for parasitic inductance between the low-ESR capacitor and the LDO regulator. My two bypass capacitors are only about 1 and 2 inches away from the regulator, and I am designing this as a 4-layer board, so there will be power and ground planes.I am not sure how to address the issue of needing decoupling capacitors for the digital logic, but also needing the ESR seen by the regulator to be at least tenths of an ohm. Should I use a filter bead between the regulator output and the load, and use the MLCCs as usual? Should I use two filter beads, on Vcc and ground? Or should I leave out the filter beads and choose higher ESR capacitors for decoupling? I already am planning to use some filter beads on both power and ground on theinputside of the regulator. Do I put some on the output as well, or just move the two over to the output side? The filter beads I usually use areMurata BLM21PG600SN1- let me know if a different one would be a better choice.I should mention my reason for wanting to use a low-dropout regulator: the power source should be anything capable of supplying 5.5 to 6.5 volts at a few amps, to drive the WS2812 strips, but I am trying to make the logic voltage selectable to 5 volts or 3.3 volts, to work with an SPI data interface at either voltage. So I have a resistor feedback network with parallel resistors, and one of them can be left out to switch from 3.3 to 5 volts. In case the power supply voltage drops to around 5 volts, I didn't want the logic voltage to go much lower than that; therefore I use an LDO regulator.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 05, 2014, 08:00:53 am
content: Smaller bypass caps aren't usually a problem. If you imagine the regulator having an inductive or potentially negative-resistance characteristic (i.e., a big enough or low enough ESR cap will oscillate), then you'll see that, as long as that characteristic is well damped, it'll be okay.High ESR avoids instability, but probably doesn't offer a low enough impedance for subsequent circuits, or the output is noisy (or maybe it really is unstable with little or no load -- worse things have happened).It follows, if you have low-ESR caps, but you dampen them with a much larger, optimal ESR cap, you can insert the damping over just the range of frequencies the regulator needs, without sacrificing supply impedance for the loads, in fact making it better than otherwise.So, it's usually fine to have small caps bypassing things, as long as you have some damping in there to keep things happy.Looks like a SPICE model is available for that regulator, so if nothing else, you could simulate the power supply network and see how it goes. I would suggest this:- Instead of pure 0.1uF caps (or whatever you were intending for bypass), add maybe 0.05 ohm ESR and 2nH ESL.- Likewise for the lossy cap, find the best estimate for ESR, ESL and C you can -- tricky for electrolytics, but almost always specified for Ta/Nb types (as you've noted!).- Traces are very roughly 20nH/inch. Estimate how much length you'll need to route the supply, and make nodes at every branch or junction, separated by trace inductances.- There are also pin, pad and via inductances, which might be included for even better estimates up into the 100s of MHz range. And the ESR (bonding, spreading resistance) and capacitance of ICs themselves, which... who knows. I've never even measured, say, a 74HC00's supply capacitance before, but that would be yet another thing to consider.- If you're using ground plane or well-stitched pours, you might as well assume ground is, well, ground. If not, do the same thing for the ground return network... but note thatalltrace inductances will be significantly higher (maybe 2-5x??) in an unpoured design.- When you've got the network set up, test it by applying stimulus to a given port* (e.g., an IPULSE source, or a VPULSE + 50 ohm resistor), and observing the amplitude produced at various ports.*Port meaning, in this case, any connection point to the supply. So, IC power pins, stuff like that.If your ground network is also implemented, don't forget to measure the voltage across the respective ports, VDD to VSS. You can also inspect common mode signals (i.e., between VDDs or VSSs of different chips), but this won't be very complete without also modeling the circuit itself (the capacitance and inductance of signal traces, the capacitance of logic inputs, and so on).The neat part being, you can test what happens by placing different components, and different values, in different locations, or stringing them together with a different routing topology (chained, starred, branched..), or even adding trace inductance or explicit inductors to better isolate different sections. And adjusting capacitors, values and ESR to see what gives the best results.In general, a chained power topology is going to act like a lumped transmission line, meaning you have trace inductances between multiple caps to ground. Which will tend to have a characteristic impedance (ca. sqrt(Ltotal / Ctotal)), which is the magnitude of a disturbance (e.g., a 100mA current spike on a 5 ohm transmission line will never produce more than 0.5V peak ripple, instantaneously speaking), and the approximate "best value" for damping it (a 5 ohm transmission line, consisting of 1uF total bypass, would benefit from a 5 ohm ESR, >= 5*1uF cap somewhere). Damping is also best applied at both ends (doubly terminated, essentially), but you can get by with just one. It's not usually a good idea to go without damping, otherwise that "5 ohm" transmission line will be very different from 5 ohms at certain frequencies that are hard to predict.Accordingly, short distances between capacitors are futile: not enough inductance to matter. Typically you only need bypass caps every couple inches, but requirements become tighter with denser logic, higher speed or higher power. So, say if you have a lot of LEDs, that change intensity all at once, you can calculate how much bulk capacitance is required for some allowable voltage change, and how low the ESR must be.Tim

author: Clear as mud
author_rank: Regular Contributor
timestamp: December 07, 2014, 04:52:03 am
content: Thank you for the detailed reply. I was worried that nobody would reply because my description was too long. I always try to be succinct, and instead I end up with a wall of text that took a couple of hours to type.I'll simulate the power supply network as you suggest.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 07, 2014, 09:39:23 am
content: I have the same problem (can you tell?)Tim