How to use FIFO to process fast ADC data - Page 1
Forum section: electronics / general

author: knight
author_rank: Regular Contributor
timestamp: August 11, 2022, 08:41:35 am
content: Hello. I have to interface a fast 16-bit ADC with a slow clock FPGA. I cannot use SERDES block. So, the only option is to use FIFO. The ADC clock (lets say 2GHz) is "8x faster" than the FPGA clock (lets say 250MHz), I have only this information known to me. Can anyone point me to some sources if this has been done before or can give an idea as to how to use a FIFO in this case?Thank you.

author: nctnico
author_rank: Super Contributor
timestamp: August 11, 2022, 08:54:15 am
content: AFAIK the only option is to use some kind of SERDES IP. A FIFO won't do you any good because this doesn't change the data rate. You need to go from a narrow & fast path to a wide & slow path. Even 250MHz is quite fast for an FPGA if you need to have large amounts of logic to deal with the data.

author: ejeffrey
author_rank: Super Contributor
timestamp: August 11, 2022, 04:21:03 pm
content: You definitely need a SERDES. Keep in mind that there are two types of SERDES in most FPGA. There first are the multi gigabit transceivers used for high speed serial interfaces like PCIe, USB3, and JESD204b. These used dedicated IO pins and clocks, and are not what you want unless your ADC uses JESD204b. The other is a simple IO SERDES. These are intended for medium speed parallel interfaces on mostly regular IO pins (with some restrictions) using either LVDS or single ended signalling and often DDR. They are commonly used for DRAM and for parallel DACs and ADCs. They have a configurable serdes ratio to allow stepping down from the IO frequency to something suitable for the FPGA fabric. What exact features are supported and the way you instance this depends on your specific FPGA family.You may also need a FIFO. A FIFO can be used to handle clock domain crossing and can also have different input and output widths. However the FIFO is built into the FPGA fabric and both ends of it must operate with a clock that can be used within the FPGA fabric. Realistically that means less than 500 MHz, often a lot less depending on your FPGA and what logic you need. Again, the way you instance this depends on your FPGA toolchain. Look through their selection of IP blocks and look for a dual clock FIFO and see what the options are.

author: ejeffrey
author_rank: Super Contributor
timestamp: August 11, 2022, 04:35:10 pm
content: Also I should add: 2 Gbit/s is faster than most FPGAs can operate their LVDS IOs. AFAIK both the Xilinx Ultrascale+ and Intel 10 series FPGAs max out at 1.6 Gb/s. There may be some exceptions: I haven't looked at the highest end parts and they may be able to go faster when using hard memory controllers. >1 GS/s DACs and ADCs typically have a built in 2:1 or even 4:1 mux (or use JESD204b). So a 2 GS/s 16 bit ADC would have a 32 bit data bus and send 2 samples per transfer. These chips may have the MUX be optional. However, you will not be able to run them at the full data rate without it, at least on most FPGAs you are likely to use.

author: knight
author_rank: Regular Contributor
timestamp: August 12, 2022, 03:57:37 am
content: Quote from: ejeffrey on August 11, 2022, 04:35:10 pmThe FPGA is Zynq Ultrascale+ RFSOC ZU29DR.

author: miken
author_rank: Regular Contributor
timestamp: August 12, 2022, 04:31:07 am
content: This must be something really wild if you have an RFSoC, need more ADC, and can't use SERDES. But realistically, when using fast data converters you need to pick your FPGA to meet the interface requirements of the ADC/DAC. If you can't use JESD204x then you need a lotta pins and careful clock planning.

author: asmi
author_rank: Super Contributor
timestamp: August 12, 2022, 05:56:49 am
content: Quote from: ejeffrey on August 11, 2022, 04:35:10 pmThat's not strictly true. Ultrascale+ has MIPI which can go as fast as 2.5G, and it technically is LVDS (only with smaller Vdiff and offset).

author: dut:Mark
author_rank: Newbie
timestamp: August 12, 2022, 10:18:04 am
content: As you are on a Gen1 RFSoC, you could take a look at the resources for the ZCU111 evaluation board. UG1287 and the accompanied download (rdf0476-zcu111-rf-dc-eval-tool-XXXX-X.zip) contains reference designs which you can have a look at for inspiration. The design contains FIFO's for recording and playback, which are emptied or filled respectively by a DMA controller from/to the PS memory.Keep in mind that you end up with quite a large bandwidth for 16x16 converters at 250 MHz complex baseband (assuming 8x interpolation/decimation for the RFDC IP). Probably the reason that the later RFSoC devices have added additional interpolation and decimation options to choose form.Imho, conceptually there is no difference between interfacing over AXI-Stream with the RFDC-IP for data, or a JESD interface IP for an external data converter connected by serial transceiver(-s)? Just in case of the RFSoC, you don't have to bother with getting the JESD interface up and running.

author: tom66
author_rank: Super Contributor
timestamp: August 12, 2022, 12:48:31 pm
content: You can definitely go beyond the raw specification of the SERDES input on most FPGAs provided you're careful with your input delay training. For instance the Zynq 7010 is 950Mbit/s rated in speed grade -1 but I had it reliably up to 1.4Gbit/s for input and 1.6Gbit/s for output (in the output case you can insert an ODELAY on the clock or data to shift either into the eye.)The trick is doing this without having a 10GHz scope to test it...!

author: BrianHG
author_rank: Super Contributor
timestamp: August 12, 2022, 05:50:48 pm
content: Quote from: tom66 on August 12, 2022, 12:48:31 pmLOL, some ADC have a test pattern output for eye alignment. Using such a pattern feature built into DDR3 ram chips DQ port, my DDR3 controller aligns what supposed to have a 600mb serdes IOs limit running fine at 1ghz. Though, the code is involved and if you are lucky, the ADC may have I2C registers to set this up and tune there so you do not have to work out how to tune your FPGA's PLL like I did with my controller.Just so we are clear, it's my HDL which does this measurement at power-up and aligns for the best error free 'center tuning' of the data coming in before continuing on with the rest of my design. This tuning procedure is done every system wide power-up and reset.