Arbitrary SPI Register Length? - Page 1
Forum section: electronics / general

author: kfnight
author_rank: Regular Contributor
timestamp: January 26, 2018, 05:11:49 pm
content: I think I know the answer to this, but am looking for additional opinions. I'm designing an SPI slave device whose shift register length is 11. I'm concerned that some IO chips and their drivers won't be able to properly handle a register length that is not a multiple of 8 bits. In the spirit of engineering for the lowest-common-demoninator, am I better off making it 16 bits totals with 5 dead bits?Thanks

author: spudboy488
author_rank: Regular Contributor
timestamp: January 26, 2018, 05:17:50 pm
content: Yes. All SPI in hardware that I've worked with uses 8-bit transfers.There are many A/D (10-bit, for example) that either state the unused bits are don't care or they may have channel info, etc.

author: JPortici
author_rank: Super Contributor
timestamp: January 26, 2018, 05:40:20 pm
content: I'd make it a multiple of 8 bits (with the MSB as "don't care" or "reserved for future use"). While there are microcontrollers that support an arbitrary number of bits, the vast majority will support 8/16 bits transfers and you don't want that people have to bit-bang SPI in order to use your device..

author: andersm
author_rank: Super Contributor
timestamp: January 26, 2018, 05:58:06 pm
content: As long as the device only latches the shift register when the chip select is deasserted, it doesn't matter.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 26, 2018, 06:15:31 pm
content: You will probably not find many (if any) SPI master controllers which can handle word sizes not multiples of 8 bits.Since your device is a slave, you just need to make sure to ignore any incoming bit after the 11th. The master can then send 16-bit words.The design issue you will face is about framing (typically handled with the Chip Select signal). If you want to be able to support what is sometimes called "burst transfers" (ie. being able to transfer more than one word in a frame), the master will have to pack words in a very annoying way if you want to avoid losing 5 bits every 16 bits. On the other hand, if all you support is one word per frame, you can just ignore any clock pulse after the 11th. (Just keep in mind that if you don't support burst transfers, the average data throughput will suffer a lot. Don't know if it matters or not in your application.)

author: dgtl
author_rank: Regular Contributor
timestamp: January 26, 2018, 07:38:19 pm
content: Non-8-bit multiple size is not very portable. If you want to have 11 bits, then support 16-bit transfers in some kind of fallback mode.Either use only 11 bits and drop the rest on the device side (trigger on the 11-th clock etc) or trigger on CS rising edge (ignore the first 5 incoming bits and transmit 5 trailing garbage bits).

author: kfnight
author_rank: Regular Contributor
timestamp: January 26, 2018, 10:05:10 pm
content: I will make it 16 bits. Thanks for the insights.

author: Benta
author_rank: Super Contributor
timestamp: January 28, 2018, 06:57:23 pm
content: This can be done much simpler, while keeping your 11-bit shift register.Just send 16 bits framed as dddddddd dddxxxxx where d is data and x is don't care. The x bits will flow through your shift register and disappear, the rest will be latched correctly at the end of transmission.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 28, 2018, 07:24:12 pm
content: The only variable-length SPI port I've seen is on the earlier NXP ARM MCUs - don't know if it's also on the later Cortex parts.Definitely go 16 bit.

author: NorthGuy
author_rank: Super Contributor
timestamp: January 28, 2018, 09:02:59 pm
content: PIC32 can handle any-length transfers up to 32.However, regardless of the hardware ability, it'll be easier to deal with your device if you use 16-bit transfers.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 28, 2018, 09:10:27 pm
content: Quote from: NorthGuy on January 28, 2018, 09:02:59 pmWhich ones ? All the ones I've used only support 8,16 and 32

author: hans
author_rank: Super Contributor
timestamp: January 28, 2018, 09:33:08 pm
content: I think the widest range of data bits I've seen is on EFM32G series, which was 4-16 bits configurable.LPC1768 is 8-16bits configurable (1-bit steps).I think in general most microcontrollers allow control in steps of 8-bits, with some allowing up to 32-bits, but most 32-bit MCUs "only" going up to 16-bit transfers.

author: Benta
author_rank: Super Contributor
timestamp: January 28, 2018, 11:49:38 pm
content: Just to get back on track: the OP is not asking about the capabilities of <insert my absolute favorite MCU here>, but if an SPI transfer to an 11-bitslavedevice is feasible.Yes, it is.

author: Yansi
author_rank: Super Contributor
timestamp: January 28, 2018, 11:55:43 pm
content: Quote from: mikeselectricstuff on January 28, 2018, 07:24:12 pmSTM32 from ST can do arbitrary SPI lengths too on some MCU families.

author: NorthGuy
author_rank: Super Contributor
timestamp: January 29, 2018, 01:23:54 am
content: Quote from: mikeselectricstuff on January 28, 2018, 09:10:27 pmSorry. My mistake. Some may let you select the size to the byte - 8,16,24,32 (such as MK), but cannot do it to the bit. That was PIC18 K42 which lets you select the number of bits.

author: hans
author_rank: Super Contributor
timestamp: January 29, 2018, 08:48:05 am
content: Quote from: Benta on January 28, 2018, 11:49:38 pmI think you're missing the point. If the OP asked, can I do this on a <insert particular MCU part>, then the answer would be RTFM.It is useful to have this discussion about the applicability of variable bit length SPI communication, on both master and slave, and conclude that "it depends".E.g. extreme case: if you're setting up a communication between 2 FPGA's, you can basically do whatever you like..

author: andersm
author_rank: Super Contributor
timestamp: January 29, 2018, 10:30:23 am
content: Quote from: hans on January 29, 2018, 08:48:05 amYou can always do it, but you may have to do some extra shifting to align the data on the master side.

author: Benta
author_rank: Super Contributor
timestamp: January 29, 2018, 05:06:34 pm
content: Quote from: hans on January 29, 2018, 08:48:05 amI'm not missing anything. Read my reply #7. OP is asking about the slave. Now, if his design is daisy-chained it's a different story, but there's no mention of that.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: January 29, 2018, 06:42:51 pm
content: Quote from: mikeselectricstuff on January 28, 2018, 07:24:12 pmThe Infineon XMC-4000 series (Cortex-M4) supports SPI widths of 1-63 bits.

author: newbrain
author_rank: Super Contributor
timestamp: January 30, 2018, 08:37:27 am
content: Quote from: NorthGuy on January 29, 2018, 01:23:54 amSame thing for STM32, it depends on the family.From a quick check of the DS I have on hand:F0 and F7: from 4 to 16 bits, 1 bit granularityF1 and F4: 8 or 16 bitsI don't think designing a slave with an odd bit size is good idea.

author: jesuscf
author_rank: Frequent Contributor
timestamp: February 04, 2018, 04:46:45 pm
content: Quote from: kfnight on January 26, 2018, 05:11:49 pmWhat I have seen with other slave SPI devices with an arbitrary number of bits is that they use a start bit to begin loading the shift register. Two examples that come to my mind are: the 93C66 EEPROM (1 start bit, 2 command bits, 9 address bits, and 8 data bits for a total of 20 bits) and the MCP3008 10-bit ADC (1 start bit, 4 selection bits, 1 dummy bit, 1 null bit, and 10 data bits for a total of 17 bits).

author: Bassman59
author_rank: Super Contributor
timestamp: February 05, 2018, 05:13:20 pm
content: Quote from: kfnight on January 26, 2018, 05:11:49 pmFor shits and grins, look at the Linear TechLTC1598octal ADC. It's advertised as "I/O Compatible with QSPI, SPI, MICROWIRE ™, etc." but it's batshit daft. The channel select is shifted in with the chip selecthigh, and that select is the last four bits prior to the chip select going low. Sampling starts after the falling edge of chip select, then two clocks later it goes into hold mode, at which point you start clocking out the conversion result MSb first. Since it's a 12-bit converter, it takes 14 clocks to get that result, and after bit 0 shifts out, if you continue shifting (with the chip select asserted low), it shifts out the result in LSb-first order! The data sheet "helpfully" includes MC68HC05 assembly code to read the converter, which is amusing -- the result is shifted right by a bit.I read this thing from an FPGA, so the weird shifting means I can design the "SPI" interface to do what I need. Shit like this is why I don't use an "SPI core," and instead just design the interface to meet the needs of the particular slave device. After all, SPI is just a couple of shift registers ...