JLC2313 stackup with DDR3 fly-by - Page 1
Forum section: electronics / projects

author: grrmachine
author_rank: Contributor
timestamp: May 13, 2020, 12:14:16 pm
content: Hi everyone,I’m building a simple SBC based on Allwinner A33 for my undergraduate final project, includes two x8 DDR3 chips. I’m going with 6 layers JLC2313 Stackup 1.2mm thickness (cost reasons). It’s my first DDR3 design and I have a lot of questions.Their website/field solver suggests 14 mil track on stripline and 5.7 mils on microstrip for SE50 ohms impedance. That’s super thick.I was wondering if I can use SE60 ohms and 120 ohms for differential pairs on DDR3(That’ll be 9.4/3.8 mils).I’ve included the stack up.L1=> Signal, L2=> GND plane, L3=> Signal, L4=> Signal, L5=> Split Power, L6=> Signal. The prepreg (Dk=4.25) between L3 and L4 is just 5 mil (0.127mm) in thickness.Would that cause a lot of crosstalk? Was planning route ACC on L3 and data banks on L4. Would keeping almost minimum intersection (criss-cross) help me out here?I will reference it to the adjacent layers (GND,VDDQ) ,separated by cores with a thickness of 14.37 mil (0.365mm).Any suggestion on ddr3 layout and layer utilization, especially with JLCPCB’s 6L stack up?(Included a preliminary component placement).About DDR3 termination, BBB, most of the boards from Bpi, Olimex, OrangePi and even Rpi seems to be termination only the DRAM clock.What about ACC group? I’ve used NCT3101S VTT regulator.(Included schematics of the board, excuse the crudity, few things are yet to be added)DRAM reset signal, Is it a pull-up or down? Is it SoC specific?DRAM_RESET is active low, but I've seen a couple other designs utilizing a pull down. I’m using H5TC4G83AFR-PBA/PBC DRAM chips.I understand differential pair’s impedance can be seen as two single ended TL’s impedance coupled with a gap. I’ve tried iCD stackup planner and can’t quite get the bang-on 120 ohms differential geometry right on JLC’s stackup (aware of the 10% tolerance), same story with their website (they seem to be using Si8000).So, is it weird to maintain 60Ohm SE and 100Ohm Differential for DDR3 signals?I highly appreciate any inputs and suggestions.Thanks a lot

author: OwO
author_rank: Super Contributor
timestamp: May 16, 2020, 03:55:15 pm
content: L3 and L4 are very close to each other but very far from the ground planes, so I would absolutely not route DDR3 traces there. I would also recommend a different stackup: S-G-S-G-S-G (S for signal and G for ground). Power planes are useless here because they are too far from each other and will not give you any decoupling benefit. I would use fat traces for power, on either a signal layer or on a ground layer next to a low speed signals area.Be careful where your "breaks" in the ground plane are; the rule of thumb is that all high speed signals should go over an unbroken ground plane, and must NEVER cross a trace on the ground plane.Using the stackup suggested you can use 0.15mm traces for 50ohms. The differential signals in DDR3 should be routed with the same width as the single ended ones. 2x 50ohm traces forms a 100ohm differential trace.

author: OwO
author_rank: Super Contributor
timestamp: May 16, 2020, 04:02:42 pm
content: An example of when routing on a broken ground plane is allowed vs when it's not allowed:

author: grrmachine
author_rank: Contributor
timestamp: May 16, 2020, 05:54:30 pm
content: Thank you OwW!S-G-S-G-S-G stackup makes more sense.Should I route DQ,DQSp/n, DM on layer L4 and Address Command Control group and clock on L5?

author: OwO
author_rank: Super Contributor
timestamp: May 17, 2020, 04:58:24 am
content: L4 is ground and should not have any long traces on it. Signals must never be placed on adjacent layers, there must always be a ground plane between them. I suggest routing as much as possible on the top layer without going through vias, and use the other layers for "deep" signals in the BGA that has to go through vias.

author: grrmachine
author_rank: Contributor
timestamp: May 17, 2020, 11:23:58 am
content: Quote from: grrmachine on May 16, 2020, 05:54:30 pmI mean L3*Quote from: OwO on May 17, 2020, 04:58:24 amWill follow that wherever possible. Also, I'm getting very close trace geometry b/w 1.2mm and 1.6mm PCB (Core thickness is 0.565mm instead of 0.365mm). Should I stick with 1.2mm PCB with the least via stubs or go with 1.6mm PCB?Thanks,Nitin

author: OwO
author_rank: Super Contributor
timestamp: May 17, 2020, 03:21:43 pm
content: Depends on your mechanical requirements. The core thickness will make a small difference in your 50ohm trace widths, which will be close to 0.12mm with 0.1mm prepreg thickness.The via stub lengths only start to make a difference past 3GHz, so it's a non-concern for DDR3.Of far greater concern is the planes stitching. Every time your DDR trace changes layers, ground currents have nowhere to flow and must go to the nearest stitching via. If you used power planes, every stitching point requires a capacitor. You need a capacitor at least every 5mm or so (depending on DDR speed). For speeds >= 1866Mb/s I recommend using only ground planes, and putting a ground stitching via next to every signal via.

author: grrmachine
author_rank: Contributor
timestamp: May 19, 2020, 09:57:24 am
content: Thank you!Will stitch ground planes at signal transition!