Surge protection grounding and fail-safe biasing for isolated RS-485? - Page 1
Forum section: electronics / projects

author: kreyszig
author_rank: Regular Contributor
timestamp: March 01, 2023, 02:16:28 pm
content: Hi,I have been going through Renesas' application notes regarding RS-485 transceivers, trying to figure out the best way to protect a transceiver against over-voltage scenarios for the data lines, for a ground potential difference scenario and also using fail-safe biasing. Looking athttps://www.renesas.com/us/en/document/apn/an1979-surge-protection-simplified-renesas-overvoltage-protected-ovp-transceivers,https://www.renesas.com/us/en/document/apn/an1979-surge-protection-simplified-renesas-overvoltage-protected-ovp-transceivers,https://www.renesas.com/us/en/document/apn/an1980-ground-potential-differences-origin-and-remediesandhttps://www.renesas.com/us/en/document/apn/an1986-external-fail-safe-biasing-rs-485-networks,I find that each concept makes sense on its own. However, I am not sure how to combine them.Here are some specific questions that I have:-If I isolate the transceiver against a ground potential difference using a small DC-DC transformer and I have either a floating or a shared isolated ground between transceivers, and that I use surge protection for the data lines using TVS, OCP and OVP, these surge protection devices should be connected to the isolated ground I assume if I want to retain the support for ground potential difference? If I do that and a surge occurs, this can potentially create an over-voltage condition between the isolated and the non-isolated ground as surge clamping occurs between the data lines and the isolated ground. Should I then use surge protection between the isolated and non-isolated grounds to protect the transformer? If I do, I assume I should clamp it to a separate neutral line?-Regarding the fail-safe biasing circuit, should this be located right next to the transceiver, after then 10 Ohm pulse-protected resistors or outside the surge protection circuit? Since the resistor values for the fail-safe biasing circuit can depend heavily on the network and noise situation, I assume it would be preferable to be able to select resistors as desired, instead of using DIP switches attached to specific resistance values? How is this usually handled (separate screw terminals, etc?)Thanks!!

author: jonpaul
author_rank: Super Contributor
timestamp: March 01, 2023, 03:08:49 pm
content: environment? transients threat level? max legnth of cable? Signal rate?j

author: kreyszig
author_rank: Regular Contributor
timestamp: March 01, 2023, 03:25:11 pm
content: Quote from: jonpaul on March 01, 2023, 03:08:49 pmThanks. I am trying to keep this device as flexible as possible for other applications, but I would like to support signal rate of 1 Mbps or more, and I am using a 5 V DC-DC transformer with 1000 Vrms isolation, so it is mostly to avoid ground loop issues and not for surge protection. For surge protection I think IEC61000-4-5 Level 3 (2kV) should be sufficient.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 01, 2023, 03:33:51 pm
content: You should probably give a schematic to show exactly what all you're thinking.In the case of a pair of isolated transcievers as in AN1980 Fig.9,Notice not just DC-DC but logic-level isolation is required as well. It's a little unclear from your post if that was intended as well.In this situation, we might apply a low-voltage TVS between signal pairs (for differential lines such as RS-485), and/or between signals and local transceiver ground (triangle symbol), to protect the transceiver.If we expect transients higher in voltage than the isolation barrier's rating (when begs the question, why not increase that rating?), some manner of surge protection between earth or system ground (PE1/2) could be used. Mind that that ground may then become electrified (momentarily due to ground-return inductance, or for the duration of the surge if isolated), so this is only reasonable when an earth ground is available, or the equipment is double insulated (making it touch-safe).The local ground (triangle symbol) may be optional on the cable between transceivers. I would recommend connecting it. Without this ground, the receiver only gets a ground reference from its input divider resistors (internal to the chip), so the CMRR for high frequencies (above Fc = 1 / (2 pi R C) where R is the CM equivalent value of those resistors, and C is the isolation barrier capacitance) is reduced, i.e. you only get the CM immunity of the isolation barrier at low frequencies.If the link is point-to-point (or limited other options), input filtering or even termination can be employed at the transceiver, in which case quite a low CM impedance to ground can be had, and the ground link is more optional. These options are limited, because filtering loads the line (reducing some combination of the bitrate, length, or number of nodes sharing the bus), and only two nodes (at either end of the bus) can have the termination.When termination is onboard a transceiver, the resistor can be split into two series halves, and the midpoint bypassed to local GND, giving a CM impedance of Zo/4. This greatly enhances the value of, for example, a CMC (common-mode choke) into the transceiver.As for fail-safe resistors, the pull-up/downs can be placed anywhere; the offset distributes along the whole line. I don't know what 10 ohm resistors you're referring to; if they are series resistors, you probably want the pulls inside of the protective devices so they don't have to be pulse rated as well.Tim

author: kreyszig
author_rank: Regular Contributor
timestamp: March 01, 2023, 04:04:06 pm
content: Quote from: T3sl4co1l on March 01, 2023, 03:33:51 pmThank you Tim. Yes I will give a schematic, it will make it easier to follow what I meant. Thank you for your feedback!

author: kreyszig
author_rank: Regular Contributor
timestamp: March 01, 2023, 05:15:48 pm
content: Here is what I had in mind: I was wondering about D1 if I want to use a transformer mostly for ground loop suppression, also about GND3 (separate mains neutral to protect GND and GND2), and about the placement for R1-6. I am limited to about 600 mA of 5V supply out of my SMPS. I have selected the LPD5030V-333 DC-DC transformer for a Fly-Buck (Buck Fly-Back) design with a high efficiency.

author: coromonadalix
author_rank: Super Contributor
timestamp: March 01, 2023, 05:29:05 pm
content: this is what we use and passed safety regulationsadding tons of protection diode may not help much, you have very good transceivers with 1kv or 3kv isolation ...and the vcc iso is a fully isolated supply (ground included) absolutley no tvs dioeds between themwe did saw in the past some diode leakages who where playing tricks between ground levels ........

author: kreyszig
author_rank: Regular Contributor
timestamp: March 01, 2023, 05:37:34 pm
content: Quote from: coromonadalix on March 01, 2023, 05:29:05 pmThanks! I had made a different thread about my power supply (https://www.eevblog.com/forum/projects/efficient-regulated-5v-and-isolated-reg-5v-supply-from-unreg-2w-12-7-v/25/), but due to efficiency and part availability issues, it has been very challenging to me to me to come up with a regulated dual output 5V 600 mA total supply (non-isolated + isolated) from 12 V with ~80% efficiency, so I resorted to a Fly-Buck design with a CoilCraft transformer. I think they only had a couple of transformers that could work (one with 1kV, LPD5030V-333, and another one with 1.5kV isolation, LPD8035V-333, but note that the pads are very close to each other). I could not really find any better transformer from other manufacturers. I have found some solutions with SMPS modules if I was willing to pay $40-50 for the SMPS alone, which I found a bit too steep.The type of power supply design from Murata you are using (5V in my case though) was amongst the less expensive solutions I considered, but their availability seemed limited.Edit: When you say you had some diode leakage issues between ground levels, what kind of working voltage were you playing with for the diodes vs what you were expecting for ground levels? For what I had in mind, I would select the breakdown voltage as high as possible with only the sufficient margin required by the transformer isolation, so typically the breakdown voltage would be at least 100V above the expected difference between ground levels. Could diode leakage be an issue for this kind of application?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 01, 2023, 06:36:35 pm
content: Is this actually RS-422? It doesn't make much if any difference, but just to be specific.ABSOLUTELY NO connection to neutral. Neutral is mains. Whether it's grounded at the panel is irrelevant: surges and crossed wiring can always show up.You could use a connection to safety ground, but it's probably redundant from the GND side (is it not already grounded? would it be better fully isolated?). A GDT could be used on the GND2 side to provide lightning immunity, again assuming a safety earth is available. (The earthed GDT could also be placed in a facility entry box (SPD) so you don't have to worry about grounding the equipment.)LPD5030V isn't a "DC-DC transformer". I don't know if you intended to put a DC-DC convertermodulethere for T1, or it's just a placeholder for such a circuit..? Also not clear what you mean about "flybuck". Maybe using the input regulator (12V input, 5V output for non-isolated side)? Having an isolated output would be a nice side effect on that, yeah. Do beware that you either need a synchronous converter (forced CCM) or guaranteed higher main-output load than isolated, else the isolated channel loads down the freewheel phase and goes out of regulation. Which maybe isn't a great deal when you've got 100-200mA of potential load on that channel?Tim

author: kreyszig
author_rank: Regular Contributor
timestamp: March 01, 2023, 06:48:03 pm
content: Quote from: T3sl4co1l on March 01, 2023, 06:36:35 pmRS-485 Full duplex.About the ground issue, I feed GND from another PCB which is the circuit I am trying to protect the most, so this is why I did not want to dump a surge into it. I was going to use mains neutral as it seemed to be recommended vs safety ground to avoid frying sensitive electronic equipment that can deal better with a surge on neutral than on safety ground. I understand your point about neutral crossed wiring and surges though. I would not want an issue with neutral to back feed in my circuit that is for sure. So would you use safety ground then?

author: kreyszig
author_rank: Regular Contributor
timestamp: March 01, 2023, 06:53:24 pm
content: Quote from: T3sl4co1l on March 01, 2023, 06:36:35 pmHi Tim,Yes I wanted to use forced PWM for the buck converter. Fly-Buck is simply the trademark name from TI for Buck + Fly-Back. TI uses constant ON time converters. I was going to use PWM in forced mode (MP4576), is that an issue? Here is my SMPS circuit. If you could tell me if it makes sense or not that would be great, you seem very knowledgeable about this kind of supply, you are the first member that mentions the need for forced CCM. Many had told me to use whatever buck converter I can find.

author: jonpaul
author_rank: Super Contributor
timestamp: March 01, 2023, 07:08:05 pm
content: Tim: Application untended.....egUse in industrial plant? Touring sound stage? Cinema? medical? \Type of mains connection and feed?Lightning frequency?Inductive load transients?What's the transient risk in the equip env?PS: I Presented a detailed RS-485 REF design at AES Berlin 2017,PM me if you like to see the design was ISO LVL 3 or 4 rated...Jon

author: kreyszig
author_rank: Regular Contributor
timestamp: March 01, 2023, 07:23:26 pm
content: Quote from: jonpaul on March 01, 2023, 07:08:05 pmIndustrial would be closer to the intended use I would say. One of the applications would be to power the board of a heat pump's PCB control port. My main concern for this application would be to protect VCC, GND and the UART lines of the heat pump's PCB against transient and surge that may occur on the RS-485's side. I wanted to make the board as flexible as reasonably possible, with the possibility of using 5-12V DC power input isolated from the UART RX/TX/VCC and GND (which in this case is relatively easy using a general purpose isolator, ISO7321C, given the 5-12 DC power supply is external). Also I wanted to allow for terminating and biasing resistors for the RS-485 lines as needed. The heat pump is powered by 240 VAC.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 01, 2023, 08:57:48 pm
content: Quote from: kreyszig on March 01, 2023, 06:48:03 pmHuh. I haven't seen anyone using those split transceivers before, and, I can't really think of a use-case for one at the moment. Why would the pairs not simply be connected immediately together?Note that putting separate pulls and TVS on them increases loading (resistance and capacitance), doubling the effect if they're wired to the same bus in the end anyway. Maybe that doesn't matter here, dunno.Grounding is always a locale dependent thing, check code in your area. There is some legacy equipment I think which receives shared ground and neutral, or should be grounded with a separately wired lug (i.e. to the receptacle housing, or a water pipe, etc.). Examples that come to mind are things like stoves, welders, etc.; years ago I had an AC welder box with a NEMA 6-50P, which is H1-N-H2 here (homes are wired with 240V CT). Preferably these should just be upgraded to a safer combination, and obviously you can't design new equipment to such a standard. Maybe it still matters if you're wiring to such equipment.Quote from: kreyszig on March 01, 2023, 06:53:24 pmYeah, that'll be fine then.Regarding all the capacitors... what's 12V coming from? Do you have any particular EMI concerns about it (in or out)?Note that all those caps do nothing about the common mode, which is likely the biggest concern here, having an isolated channel.The caps don't do much because the larger (1, 10 uF) dominate the response, and the smaller values either don't have much if any less ESL, but their values are smaller so they have higher Q resonances with the larger ones, generally making response worse (peaks in the impedance / transmission at high frequencies). Like, consider this case:Note the capacitors (body, pad, trace and via) and trace lengths are represented by small inductors.There are more valleys of low impedance which is nice, but the worst-case maximum is what matters, and you've put in several new peaks in so doing.There are some old appnotes that recommend staggered or tapered values in parallel, which should be considered erroneous. That might've been appropriate back in the days of THT capacitors, but it's sadly harmful most of the time with ceramic chips.Better to use one or two large caps for low ESR/ESL at high frequency, then R plus a few in parallel for damping at middle frequency:Here, a supply is at a modest distance (several cm, say) to the load. R1 has been added (notice the value), or changed to a lossy bulk type (electrolytic, tantalum, polymer*) several times the value of the parallel low-ESR capacitor(s).*Polymer are available in a range of ESRs, tants as well; they cluster lower than tant, but shop around and choose appropriate values.You're kind of doing this already (e.g. C1-R1), but the values are inappropriate -- 0.1uF is far too little to do anything at all, and 10R is much too high compared to the surroundings. If C31/C34 are ~adjacent, their loop inductance will be say 5-10nH so sqrt(10nH/5uF) ~= 44mR is what should be targeted, and then you'd need more like 20uF with the ESR, for which a chip electrolytic would be fine I suppose. (ESR can be within say a factor of 2 of Zo = sqrt(L/C) and it's fine.)Also keep in mind, the transceivers won't care very much about supply noise; maybe just a 10uF would be enough filtering there, and no chokes. (So, you'll be fine in this regard.) If it is found problematic, maybe a couple more caps, or adding a ferrite bead or small choke (in the <200mA range, a 1206 size ferrite bead in the 30-100R range should be adequate without too much saturation).As for common mode, a 'Y' cap (in the sense of being ground-to-ground; potentially the safety rating is relevant here) might be used to return current coupled across the transformer, i.e. the switch node has some capacitance to the isolated side so the switching edge drives into the common mode. And maybe some ferrite beads or whatever on the RS-485 connectors, to dampen the resonance created between the cable and that capacitance. Which can be coupled (use a data line type CMC) if you need to keep differential bandwidth up.Tim

author: kreyszig
author_rank: Regular Contributor
timestamp: March 01, 2023, 09:48:54 pm
content: Quote from: T3sl4co1l on March 01, 2023, 08:57:48 pmFull duplex is not strictly needed, but I have a transceiver that supports it as well at the other end. I agree with you that it might increase loadingQuote from: T3sl4co1l on March 01, 2023, 08:57:48 pmI will have to check this out more. Homes are wired 240V CT here as well, but there might be slight differences for grounding.Quote from: T3sl4co1l on March 01, 2023, 08:57:48 pmFor the application I mentioned earlier, the 12V is coming from a control port from the main board of the heat pump that can supply 3-4W. I do not have particular EMI concerns. For my circuit I basically took the circuit in the MP4576 datasheethttps://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/MP4576GQBE/document_id/9740/"Figure 9: Typical Application Circuit with EMI Filters" and made the minimal changes to force PWM and to add the Fly-back. I stuck to that because honestly I have very limited experience with EMI and I was just attempting to play it safe. I was a bit surprised about the quantity of caps compared to what was suggested for other converters. Something I noticed too is that they where using much larger caps than TI in general. What is your workflow when you test this type of circuit? Do you go through multiple iterations of reflowed PCBs, or use some kind of breakout boards for these small SMD chips, or solder tiny wires to it, etc? This is a bit why I was not attempting to be adventurous at all with my design, just stick to their suggestion and then test everything. I will need to do some homework and learning to fully appreciate and follow what you suggested, I could certainly not argue against anything you mentioned vs the suggested circuit they provided.

author: coppercone2
author_rank: Super Contributor
timestamp: March 01, 2023, 10:53:47 pm
content: fail safe = pay someone to manage it

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 01, 2023, 11:27:04 pm
content: Well, having done a few dozen of these, my workflow is to place and route things the way that works.Their layout example is rather odd and I wouldn't recommend doing all that. Just place things close together, with priority to the switching loop (VCC, SW, GND; VCC-GND bypass cap, and, there's no SW diode but put that close in for non-sync types). BST can be somewhat more distant (occasionally a via or two needed). VFB even more distant (it's a low frequency control signal). Place critical components adjacent on the same side. Pour GND on the nearest layer (for top-side placement, bottom or Mid 1). What's on other layers below GND doesn't matter too much, you may just prefer to route sensitive signal traces around the general area of the converter (because a ground plane is not quite ideal). Usually for 4-layer boards you'd do signal-GND-VCC-signal, and that's fine.Also their EMI measurements are irrelevant as no layout is given. It's not clear if that was measured with the one layout, or, which schematic; and, the location of the connectors especially is critical.Tim

author: kreyszig
author_rank: Regular Contributor
timestamp: March 02, 2023, 12:43:26 am
content: Quote from: T3sl4co1l on March 01, 2023, 11:27:04 pmI had basically the same layout as them, adapted for the Fly-back with all their extra capacitors for EMI (see attachment). What is wrong with their layout, just too complicated?

author: kreyszig
author_rank: Regular Contributor
timestamp: March 02, 2023, 01:02:12 am
content: About the filters, did I get this right that you would go for something that looks more like that? You mentioned a few things about the larger capacitor and I am not sure if this is what you meant. Thanks!

author: Siwastaja
author_rank: Super Contributor
timestamp: March 02, 2023, 10:41:12 am
content: Quote from: coppercone2 on March 01, 2023, 10:53:47 pm"Fail safe biasing" is just an arbitrary name for something that has absolutely nothing to do with failing safely, or safety against failures, or anything like that, whatsoever. Misnomers in electronics are commonplace, but I think "fail-safe biasing" is my #1 favorite. Of course, by failing to have biasing, the system will fail to operate by losing noise margins almost completely (which are not that magnificent even with the biasing, RS485 is just flawed), but by the same logic, every other functional feature is "fail safe", like fail safe termination, fail safe powering, fail safe guessing A and B labeling right, and so on.RS485 is just so sad. It could have been a useful thing but resulted in colossal mess causing countless of hours lost at industrial end-users debugging trivial things like signal integrity, due to a few simple but serious design errors and weird practices (the idle state biasing farce, commonplace advice of not connectinganyground wire at all, and inability to define coherent names for the two signals so that the only way is to test, which is frustrating if there are more combinations of other parameters that require "just testing" and your only feedback is works/doesn't work).The best thing CAN did was fix all these problems. It's easy to wire up and just works.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: March 02, 2023, 10:51:27 am
content: The circuit posted by kreyszig does not look correct. You can have pulse overload protected resistors, but that does not help much if they are only connected to the RS485 IC itself. Once a significant current flows though it's pins, it's usually toast. (But there are some with built in TVS diodes).To me it makes more sense to put these resistors between the connector and the TVS diodes, This way the current though the TVS diodes is limited a bit by the resistors, and the resistors can actually have their high peak dissipation without anything getting damaged.If you do a picture search for "RS485 TVS" you find both schematic variants.If you want to protect against a hard DC overvoltage, you can also add PPTC's in series with the data lines.

author: jonpaul
author_rank: Super Contributor
timestamp: March 02, 2023, 11:06:21 am
content: Siwastajamany fine designer's have successfully used RS-485 since 1980s, it is embedded Ina vast majority of serial bal signaling systems.CAN bus is specifically for short run automotiveThe standards reveal the fan out, cable legnth, baud rates.Totally different PHYJ

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 02, 2023, 01:56:18 pm
content: Quote from: jonpaul on March 02, 2023, 11:06:21 amWell... not exactly totally. As I understand it, CAN was developed with RS-485 components in the first place. It's merely evolved, adding the input offset, extended CM range, and using unidirectional drive as part of multi-drop arbitration.CAN is alright over long distances, but because of the arbitration scheme, baud rate is limited by bus length, so it simply gets less and less useful as you go up.Tim

author: Siwastaja
author_rank: Super Contributor
timestamp: March 02, 2023, 02:08:44 pm
content: Quote from: jonpaul on March 02, 2023, 11:06:21 amAnd many fine installers have struggled getting them to work, or get them marginally work in easy lab conditions, but then signal integrity falls apart because noise immunity is nowhere near the advertising in real systems which use transition from idle to signify a start bit (i.e., almost all that use RS485 as underlying physical transport).And then the work commences, reverse-engineering products to see which transceiver ICs they use, to be able to calculate the required external bias resistors, as carefully explained in numerous appnotes. This is an interoperability issue; not a problem if the Fine Designer designs all participant devices on a bus. And of course, assuming Fine Designers have ever heard about the need of biasing.Especially if the designers themselves suffer from egoism, it's highly likely they missed something due to lack of humility.

author: kreyszig
author_rank: Regular Contributor
timestamp: March 02, 2023, 02:17:57 pm
content: Quote from: Doctorandus_P on March 02, 2023, 10:51:27 amMy understanding is that these resistors are used to avoid interference between the TVS and the transceiver built-in protection. This is what Renesas mentions in their application notes at least.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 02, 2023, 02:34:36 pm
content: Quote from: kreyszig on March 02, 2023, 12:43:26 amZoom out a little bit. Is that a slot in the ground pour around the area? Notice they left bottom layer ground poured over everything. See what I mean about odd?Better to just pour ground everywhere. Their dividing it by layers probably just makes things worse, but it makes things 1000% worse when it's misread as a gap across all layers(!).Quote from: kreyszig on March 02, 2023, 01:02:12 amErr, check the orders of magnitude there. Compare the values on the simulation to typical component parameters: the <= 50mΩ ESRs are typical of ceramic caps of respective value, by themselves. The larger ones like 200m are either tant/alum or ceramic+resistor. Nothing is over an ohm.You only need one or two large ceramics with no added ESR, and either a few more ceramics with ESR added, or tant/alum of specified ESR.So like 10uF ceramic plus 47uF electrolytic would likely be fine, and no resistors needed anywhere.Exact impedances depend on regulator rating and desired ripple; at high currents, you might need a bunch of caps in parallel, and with a dense enough array made with ceramic, their ESRs will dampen each other well enough. The same isn't true with few of them, connected with thin traces.It also depends on what the source is. If it's a 12V supply right beside, its internal ESR is probably enough (they use electrolytics often enough, but it would be good to check to make sure) that a single ceramic might do at the regulator. If it's on a cable (like an adapter, or wired to something else), the cable has inductance (~0.5 uH/m) which can resonate with your caps. In that case damping is required, and you need the C || (R+C) motif. A TVS might also be desirable, say if hot-plugging ever occurs -- the inrush current can overcharge ceramic capacitors (partly by this ringing, partly by the dropoff in capacitance as voltage goes up), blowing the regulator. (Damping helps greatly with this as well, and I would recommend an electrolytic > 10x ceramics or a TVS for this purpose.)For example how I like to lay things out, here's a small regulator in a recent project:PS1 is an on-board AC-DC converter module; its input connections aren't shown. The ceramic + electrolytic + ferrite bead filtering is almost certainly total overkill for the application, but whatever. C23 and C69 are at some distance (~cms) so C55 helps dampen their combination (as well as the FB's inductance, with C22).There are other large ceramics (with electrolytics) on the +5V, local to the loads; they're not shown here of course.Single layer views:https://www.seventransistorlabs.com/Images/ConvLayout2.jpgTophttps://www.seventransistorlabs.com/Images/ConvLayout3.jpgMid 1https://www.seventransistorlabs.com/Images/ConvLayout4.jpgMid 2https://www.seventransistorlabs.com/Images/ConvLayout5.jpgBottomC23 would be better placed below IC1 but there was a board edge, and not really enough room to move everything up to compensate. It's fine. The +V trace (C23-1 to IC1-5) should be, oh, 10mm tops, that might even be pushing it; it's around 5-7mm here. Depends on exactly how sharp (rise/fall time) the regulator is. As you can see, ground runs directly underneath (and adjacent to) all the top-side components, so the switching loop between IC1-6, D3, C23 and IC1-2 and IC1-5 is quite small. The wide body of C23, and flanking vias to GND, help reduce its inductance further. Notice the relatively circuitous route for D2 (which I think wasn't needed in the end anyway?; depends -- some regulators have the diode internal, some don't; the LMR is just one of several alternates selected for IC1), which is fine, it's just topping up a cap. C24 itself is pretty close, but if it couldn't be routed under D3 to pin IC1-1, two vias and a short bottom-side trace would still be acceptable.Inner plane is used only for 3.3V here, which comes off the regulator IC14 directly into a cap C49 and vias to the plane. 0.1uF bypasses are scattered about, keeping the plane nice and stable.Zooming out further, GND/3.3V span the bulk of the low-voltage area with no gaps larger than a couple vias. The supply section here is placed off to a corner, so any ground-loop currents in the local area are not intercepted by signal traces running across the rest of the low-voltage area. (Only WDTC, and that bus of traces on the top side, get very close. Several of which are unused test points, like TP_PB2.)Tim

author: kreyszig
author_rank: Regular Contributor
timestamp: March 03, 2023, 01:21:40 pm
content: Quote from: T3sl4co1l on March 02, 2023, 02:34:36 pmYes I had noticed that the bottom layer in their design did not have a slot, and yes I found it a bit odd since they other layers had it. I thought their intent was to separate the power ground from control ground to reduce noise outside the SMPS?Quote from: T3sl4co1l on March 02, 2023, 02:34:36 pmOk thank you. For the outputs, what do you think would be appropriate?Quote from: T3sl4co1l on March 02, 2023, 02:34:36 pmMy circuit is likely to be ~1 m away from the port of the other circuit through a cable, so damping is probably a good idea. Thank you for the layout information!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 03, 2023, 02:43:29 pm
content: Quote from: kreyszig on March 03, 2023, 01:21:40 pmIn what sense; control ground where? There's no AGND pin on this device (some regs have that though).The fact that they have input and output exiting in different directions means there is an overall path across local ground loops, i.e. the ground that VIN is bypassed to is different from the ground VOUT is bypassed to. Measuring these nodes at a distance, there will be some voltage between them, that is not due strictly to the ripple on each one by itself (i.e. V(VIN, local GND) + V(VOUT, local GND) != V(VIN, VOUT)). This is probably a small effect, because ground is overall fairly dense still, despite their odd layout. Small enough you wouldn't notice it in comparison to the ripple on each node by itself.Like, the weirdest thing about their layout is probably this:Notice the length between GND pin and vias. Switching current flows through this path, thus the chip's internal ground is offset by the voltage drop along here.Like this:Now, C1 especially C/D do bypass along this path, so I'm overstating things a bit. The switching current flows between VIN/GND and SW so the common-mode isn't dropping across the full ~5nH. But it is if there's high-frequency currents flowing out of the SW node; most inductors have a high-frequency series-resonant or capacitive mode which is relevant here, and that current will drop through this full path.So much better to use vias directly:and remove the ground slots (what were those doing anyway, more ground is better?!).Notice the path between pin 7 and C1D can be widened, reducing inductance a bit additionally.Speaking of inductors -- one wonders just what they had there. I haven't seen one with that footprint before. Does it really have a ground connection -- core connection, or shield, perhaps? That might contribute noticeably to EMI: both in reducing emissions by not having the bulk of the inductor body have switching noise on it, and by increasing its capacitance, and therefore CM switching currents as mentioned above. (Which is a local effect, manageable by layout or filtering; the inductor body acting as a tiny antenna however is not, and would require shielding if it is found to be excessive.)If you are going to use ground slots, the proper way to apply them here is to rout around the circuit, leaving it as a peninsula. VIN, VOUT, and any signals, are routed along an isthmus between the peninsula and the main board. It doesn't need to be as narrow as "isthmus" implies, indeed it should be wide to keep inductance down, but also width implies local loop currents can flow into it. More that it should be longer than it is wide, so those loop currents die out along its length. Anyway, all signals coming along this path shall be bypassed and filtered to it. This acts like a single point, and there is zero voltage across an ideal point so we've eliminated ground loop from the system. Notice also it's a three-terminal regulator: VIN, GND, VOUT (...and whatever control signals). You can't have any common mode on a common-ground system by definition, so we've again eliminated ground loop.As for the control signals, they should be filtered as well as they can be, given their bandwidth. Here, just EN and PG need to leave the site, if at all. A ferrite bead along the isthmus, with a bypass cap at either end (100s pF to 10s nF, kinda who cares?), should be adequate filtering.If you needed, like, some kind of data signal here -- I don't know, maybe an SPI controlled regulator? -- you might simply deal with EMI on a system level (because you can't compromise SPI bandwidth too much: usually SCLK has a maximum rise time for example, or maybe the bus is shared with other fast devices), or it can be communicated as a differential pair using data chokes to cross between ground domains (additionally, using RS-422 transmitters/receivers seems terribly overkill for this, but would certainly do the job..), preserving signal bandwidth without carrying as much ground loop noise into the bus.Maybe a more meaningful example would be something like, a module, or "shield" if you will, that's got onboard power, and it's dirty -- they did a shitty layout and you can't fix it, it's a 3rd party module -- and it's also got, I don't know, Ethernet coming in or something. Maybe its noise can be isolated off to one side, and the signals (RMII I suppose?) carried via CMCs to the quiet side. This wouldn't address the common mode out the connector though; you'd still need some kind of grounding solution to keep noise down at the BS terminator node, more or less....If you don't know about typical Ethernet circuits, this probably isn't very meaningful, and that's alright. These probably aren't very meaningful examples without diagrams anyway.In any case, the point is, even if you need to pass high-speed data along such a ground-isolation route, there are methods to do so. They might not be preferable (adding a bunch of CMCs and filtering, when the problem could likely be solved with better layout, or choice of less noisy parts), but it is possible.QuoteIf the loads are nearby, added ESRs might not be necessary.The isolated output might have two 10uF's, total, say, one at the rectifier, one at the chip?5V output, if routed over some length, probably should have some damping, to terminate the PDN (power distribution network). Exact values, and spacing of bypass and bulk caps along the route, depends on where and how it's routed.If inner plane, just some bypasses scattered about is probably fine.If 5V just goes to a couple loads then a 3.3V LDO, a couple 10uF (total as required by the MP4576) and maybe a bulk cap will be fine. Again, exact value and placement depends on routing.The 3.3V in turn (if applicable), depends in the same way. Choose an LDO with low GND pin current (check for a plot of I_GND vs. VIN; it can be shockingly bad on some bipolar types, or is rarely a concern on CMOS types), and check for any discussion of stability vs. ESR and C_OUT values. Modern types are designed for low ESRs so put on as much ceramic as you like. Older types require ESR within a range so you will need a bulk cap (with its ESR) to be dominant, at least near the reg's cutoff frequency (typically 10-100kHz). It's okay to have low-ESR bypasses in parallel here, as long as they don't reduce the ESR in this particular frequency range. Which means, using much less total value bypasses than bulk cap.And so on for other supplies.Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 03, 2023, 02:57:56 pm
content: I should notate that a little better actually, like this:Note that there's very little inductance between C1 A/C and B/D, and C/D are closer to the chip ground than A/B are. As for capacitance or stray modes of L1, they manifest like this, some effective series resonant circuit in parallel with it. So switching current flowing through Cp and such must also flow through the total ground-return path, it's not saved by the shorter path between pins 7/8 and C1 C/D.Tim

author: kreyszig
author_rank: Regular Contributor
timestamp: March 03, 2023, 05:14:35 pm
content: Thank you,I now understand much better the issue with the ground slot, and what you say about the isthmus makes a lot of sense. Also adding vias closer to the chip and getting rid of the local ground plane there makes sense.I really need to educate myself better about filtering though, and although I have some understanding of what you are saying, I have little to no intuition regarding this stuff, all I have is some knowledge based on an engineering course I took 20 years ago and where we were doing lots of linear algebra and played with the complex inductance. So when I look at this type of circuit all I think about are a bunch of equations, pole diagrams and equations, I lack the intuition and a higher level of understanding of this. If anyone know a great resource that could help me this would be great!Edit: I created this new thread to discuss about the filtering aspect, since it is a bit off-topic for the current thread:https://www.eevblog.com/forum/projects/approach-to-design-a-multi-stage-rlc-low-pass-filter/