Choosing a Clock Input Pin for an FPGA - Page 1
Forum section: electronics / general

author: electosleepy
author_rank: Contributor
timestamp: April 03, 2016, 02:48:32 pm
content: Hi,I am developing a prototype board for an Artix 7 FPGA (see attached picture) and have noticed that there is more than one pin for a clock input (unlike a microcontroller). Will any global clock input be acceptable or is there a preferred pin I must use?

author: langwadt
author_rank: Super Contributor
timestamp: April 03, 2016, 02:55:04 pm
content: Quote from: electosleepy on April 03, 2016, 02:48:32 pmThat can be a tricky question. for general logic any clock pin will work, but if you want to use the more advanced features of the input/output pins like deserializers etc. certain a clockpin goes with certain pinsThe definitive answer is to run the design through the tool and see if it fails

author: uncle_bob
author_rank: Unknown
timestamp: April 03, 2016, 03:29:10 pm
content: HiThere is of course the "read through several hundred pages of doc's" approach. Even then, the design wizard in Vivado is the best way to check it out. That also is becoming increasingly true for multi use pins in MCU's as well. I've seen a number of cases where the docs were wrong and the design tool had it right.The correct answer is indeed, do the design for what goes in the FPGA first and *then* layout the board. At the very least, get all of your I/O widgets into a design before you do the layout. It seems like a painful way to do things. Finding out after the board arrives that it can't be used is a lot more pain (been there / done that ...).Bob

author: electosleepy
author_rank: Contributor
timestamp: April 03, 2016, 03:45:40 pm
content: I thought that might have been the case when I started to learn about the Vivado pin planning tool. Unfortunately I don't think it will be within my power to change the direction of the project.The logic design has not been completed yet but we want to use the GTP transceivers (light blue and grey blocks within X1Y2 region). As the logic design would be presumably close to the GTP transceiver region (X1Y2) would it best to attach the clock signal to a clock pin in the X0Y2 or X1Y1 which are adjacent to the GTP transceiver region?

author: langwadt
author_rank: Super Contributor
timestamp: April 03, 2016, 05:32:30 pm
content: Quote from: electosleepy on April 03, 2016, 03:45:40 pmyou'll have to read this:http://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf

author: hamster_nz
author_rank: Super Contributor
timestamp: April 03, 2016, 10:34:20 pm
content: Quote from: electosleepy on April 03, 2016, 03:45:40 pmI've played with the transceivers a little bit on Spartan-6 and Artix-7. You can not use a regular fabric clock pin (or output from a PLL) to drive the transceivers. Apparently the PLLs are too jittery to give good results. If you use the transceivers, you must use an appropriate reference clock in the transceiver block, and then supply that clock to the fabric, where you can use it to drive the rest of your design..... however, if you don't use the IP wizards and use primitives you can supply a fabric clock to the transceiver and it does work (at least at 2.7Gb/s, with a 165MB/s clock generated by a PLL using 100MHz supplied from a global clock pin). It is however very, very troublesome, and not guaranteed by Xilinx to work. It is a "test only" feature.Also, there are lots of restrictions on which transceivers channels can be coupled to which reference clocks, with 7-series being a lot more flexible than the old Spartan 6.

author: electosleepy
author_rank: Contributor
timestamp: April 04, 2016, 02:33:51 am
content: QuoteWe do intend to use the Vivado IP wizard for what we are creating. So are you saying that the clock signal is internally generated in the transceiver block?

author: hamster_nz
author_rank: Super Contributor
timestamp: April 04, 2016, 03:35:28 am
content: Pretty much. Here is the generic structureTransceivers are usually in blocks of two, three or four (depending on FPGA family). Each block has:- Reference clock selection MUX. Options are usually limited to something like this:- a couple reference clocks- the reference clock from a neighboring transceiver block.- maybe a clock that runs the entire column of transceivers- and an 'unusable' option that comes from the fabric.- That then feeds into a high-quality PLL, usually based around an LC tank that is integrated on the die. This then generated the high speed clocks.- Signals from that PLL can then feed the individual transceiver channels, but only within that block of transceivers.- Each channel also has a not-so-smart channel PLL, that is used to perform clock data recovery on any incoming data stream, using the output of the high quality PLL as a reference clock.On 7-series this is two PLLs per block of four transceivers. On Altera Cyclone V the middle channel of a bank of three has a PLL that can act as the master for other channels in the bank (and routed to adjacent banks).Have a look athttps://github.com/hamsternz/FPGA_DisplayPort/blob/master/src/artix7/transceiver.vhdif you want to see 7-series TX implemented with primitives. The important bit for your design may be GTPE2_COMMON. It has ports that you can't make use of in the wizard:GTGREFCLK0 - Clock Reference clock generated by the internal FPGA logic. This input is reserved for internal testing purposes only (as per the User Guide).There is also GTFREFCLK1 that can be used as an input for the other PLL_1 in the same block of 4.As others mention, see the really good documentation athttp://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdffor full details and feel free to ask me questions.

author: kendalll
author_rank: Contributor
timestamp: April 04, 2016, 03:44:50 am
content: You can hedge your bets by putting the pads down for an external oscillator on the reference clock pins for the GTP transceiver. You don't have to install the oscillator in the assembly if it ends up not being needed.

author: electosleepy
author_rank: Contributor
timestamp: April 04, 2016, 05:13:02 am
content: Thanks for taking your time out to answer my questions. So looking at the attached picture is the GTGREFCLK1 also limited only for testing purposes as well?

author: hamster_nz
author_rank: Super Contributor
timestamp: April 04, 2016, 06:13:27 am
content: Yes. Officially you should not use it, and the IP wizard does not support it.However I have made it work for me

author: electosleepy
author_rank: Contributor
timestamp: April 06, 2016, 04:20:46 am
content: So for the transceivers we will use a reference clock from a HDMI input. If the general design was to use PLL to generate the clock signal from the transceivers for the logic on the fabric, am I correct in thinking that if the design did not have an external oscillator attached to a global clock pin and if the HDMI signal was not present, the logic wouldn't work? What happens if the design has no input clock, will it wait until a HDMI signal is attached and then begin functioning?

author: hamster_nz
author_rank: Super Contributor
timestamp: April 06, 2016, 05:33:23 am
content: Quote from: electosleepy on April 06, 2016, 04:20:46 amYes, you have to somehow dynamically switch to or from the HDMI clock, and maybe use the CDR features of the transceivers too.Transceivers only have a limited range of frequency where they work correctly. HDMI sources go from 0.250Gb/s (640x480) to 3Gb/s. (1080p, deep color). Doing this correctly is a hard problem to solve if you want to support a wide range of input formats.A full design is quite a bit of work, with lots of different options to chew over (e.g. oversampling the HDMI data signal at low resolution, and dynamic reconfiguration of the transceiver's PLL based the received clock rate to keep it in band. This is where the discrete HDMI receivers with wide parallel interfaces shines...

author: uncle_bob
author_rank: Unknown
timestamp: April 08, 2016, 12:27:35 am
content: Quote from: electosleepy on April 06, 2016, 04:20:46 amHiNormally, you will have a core of logic that runs off of a local clock. That clock *might* be phase locked to an external source. This part of the logic handles all of the things that must continue to happen with no data source present. Generally this is the side of things that communicates with the outside world.For multiple data rate inputs, a reconfigurable system (likely a PLL) is often used. The "core" that is independent of this input system runs the rateselection and clock detection process. Often this involves some logic to correctly guess the input clock frequency. Some FPGA's will allow reconfiguration of PLL's on the fly. Others require a reload of the image in the device. A lot depends on how far you need to stretch things. Keeping timing in line over a very wide clock range may not be practical without a re-load.A completely different approach is to run an MCU external to the FPGA. It handles the configuration stuff. It decides what image to load in the FPGA. You use two devices. The MCU may be better suited (or not) to the higher level stuff. It also may get you out of some interesting loops associated with reloading the decision making device.All of this is high level system design. Normally that is worked out first. You then pick the devices and design the stuff that goes in them. In the case of a FPGA, you compile and time the design against the candidate parts. Once you have a reasonable fit, you pick the device you will be using. After that you get down to board layout and fun stuff like picking which clock pin to use.Bob

author: electosleepy
author_rank: Contributor
timestamp: April 09, 2016, 05:09:55 am
content: In my system I want to have a HDMI input and a HDMI output. If the MGTREFCLK pins areinputs onlydoes that mean that I will have to use four of the differential MGT transmiter pairs for the HDMI output whereas the HDMI input will only need three differential MGT receiver pairs and one MGTREFCLK pair?HDMI output;TMDS DATA0MGTTXP0MGTTXN0TMDS DATA1MGTTXP1MGTTXN1TMDS DATA2MGTTXP2MGTTXN2TMDS CLKMGTTXP3MGTTXN3HDMI input;TMDS DATA0MGTRXP0MGTRXN0TMDS DATA1MGTRXP1MGTRXN1TMDS DATA2MGTRXP2MGTRXN2TMDS CLKMGTREFCLK0PMGTREFCLK0N

author: uncle_bob
author_rank: Unknown
timestamp: April 09, 2016, 01:24:52 pm
content: HiAnother thing to add to the list:What sort of glue logic are you planning on having between the FPGA and the HDMI ports?My experience with FPGA inputs and output suggests that they are best kept away from the outside world. The day to day ESD and "plug anything in anywhere / any time " issues are often not what they like putting up with. You *can* get away with some pretty terrible things (done that on a regular basis). The issue is *relying* on the ability to get away with it. I unfortunately have seen some of our customers who apparently are a lot less lucky than I am.It's worth considering because it will impact what type of ports you need to wire up on the FPGA.Bob

author: electosleepy
author_rank: Contributor
timestamp: April 09, 2016, 04:12:57 pm
content: Hi,I'm going to use a passive network for the HDMI input and a HDMI retimer/redriver for the HDMI output which is described in this document (http://www.xilinx.com/support/documentation/application_notes/xapp1077-phy-hdmi-rx-gtp.pdf). I have chosen 15kV ESD protection so it shouldn't be a problem.

author: hamster_nz
author_rank: Super Contributor
timestamp: April 09, 2016, 08:15:51 pm
content: How fast do you need to drive the HDMI port? Are you after 'just' 1080p60 8bpp?

author: electosleepy
author_rank: Contributor
timestamp: April 09, 2016, 08:39:07 pm
content: The ultimate aim is around 3.4Gb/s per TMDS pair but I am not sure if we will reach that goal with our first prototype. If only it was 1080p that we needed, it would be simpler to implement with the SERDES.