power decoupling myths - Page 1
Forum section: electronics / projects

author: electrolust
author_rank: Unknown
timestamp: July 20, 2020, 03:49:01 pm
content: https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values(2020)https://ewh.ieee.org/r3/enc/emcs/archive/2012-10-10b_DecouplingMyths.pdf(2012)

author: Bud
author_rank: Super Contributor
timestamp: July 20, 2020, 03:56:52 pm
content: QuoteThe best approach is to hook up a spectrum analyzer to the first revision board and adjust the capacitors values for best noise supression within the range of frequencies of interest. Any other aporoach you will be shooting in the dark.

author: Tomorokoshi
author_rank: Super Contributor
timestamp: July 20, 2020, 08:33:22 pm
content: That is similar to the Hoffman Effect!https://conradhoffman.com/hoffman_effect.htm

author: David Hess
author_rank: Super Contributor
timestamp: July 20, 2020, 10:33:11 pm
content: I would be more impressed if some empirical designs which failed that analysis were included, with an analysis of why they failed.I had nearly perfect application to make a test case for three different values versus three of the same value. Initially 12 surface mount capacitors of the same large value were placed in parallel *in a radially symmetrical transmission line structure*, and it completely failed up to 1.2 GHz. Replacing the capacitors with a set using three decades of values worked from 50 MHz to 1.2 GHz.The only reason I even initially tried the 12 larger value capacitors was because in theory, as given in the examples above, it should have worked, but I was skeptical enough to have also ordered additional capacitors to make a decade set which ended up saving me considerable time.

author: CatalinaWOW
author_rank: Super Contributor
timestamp: July 20, 2020, 11:10:16 pm
content: I object to this use of of the word, myths, which is found widely in Facebook clickbait.The articles are completely correct, new packaging techniques have changed the rules for design, but the old rules were not anti-factual. Just limited applicability.It is like calling turn of the twentieth century engineering handbooks myths because they have tables of strength of various wood species that cannot be duplicated today. The tables were correct for the old growth wood being used almost totally at the time. They don't apply to wood grown in rapid growth tree farms which constitute much of the wood on the market today.Engineers in all fields have to understand what they are doing. If they don't they are really technicians. Or amateurs.

author: David Hess
author_rank: Super Contributor
timestamp: July 20, 2020, 11:26:10 pm
content: Quote from: CatalinaWOW on July 20, 2020, 11:10:16 pmThat brings up something I almost included in my post. Schematics which show multiple different values of decoupling capacitor in parallel assume a context where the reader understands what the objective is, just like there is a context for how the layout should be done with separate return current paths despite how the parts are shown connected together.Quote from: CatalinaWOW on July 20, 2020, 11:10:16 pmNewton's law of gravitation is another example. It is demonstrably wrong, but completely adequate in most applications, with GPS being one of the few exceptions.If I am laying out a modern surface mount board with power and ground planes, then I would not expect to use decoupling rules intended for through hole parts on a two sided board. On the other hand, my ideal test using a radially symmetrical transmission line makes me question modern rules; something is missing.

author: vk6zgo
author_rank: Super Contributor
timestamp: July 21, 2020, 01:41:28 am
content: Quote from: CatalinaWOW on July 20, 2020, 11:10:16 pmIs that why technicians & amateurs spend a lot of their time fixing engineers' stuff ups?

author: Siwastaja
author_rank: Super Contributor
timestamp: July 21, 2020, 07:45:06 am
content: The mistake people make is they think the capacitors provide low impedance to the load by working at the operating point of minimum possible impedance, that defined by ESR only, i.e., at the SRF.Of course, loads that only require low supply impedance at one very specific frequency can theoretically exist - a sine wave oscillator could be a theoretical example, but I don't know if they can be realistically built that way -, but even then, tuning the capacitor SRF to happen exactly at that frequency despite component variations, would be next to impossible.Some resonant power converter design could utilize the low impedance point of a capacitor and auto-tune to it, but especially in this case you would want to have one strong resonant frequency, not a combination of many.Real loads, bypassing ICs for example, tend to require low supply impedanceover a broad area of frequencies. Zero impedance from DC to infinity would be nice, ourtarget.If the switching load pulls square-ish current pulses that contain significant energy from 1MHz to 100MHz, what good does it do if we have a nice capacitor that can supply current at low impedance at 40.1234MHz? No, we need it to givegood enoughimpedance over the whole frequency area. And when this is the case, having a high-Q, narrow band of being "better than good enough", can only increase the risk of unexpected oscillations.So this shows that already, the SRF dip in single capacitor solution is already an unwanted side effect.Now, adding multiple different capacitors in parallel makesmultiple dipsin the impedance plot because of their different SRF.The claim often seen is, now these different SRF dips somehow combine to give low overall impedance. This is obviously false; combining low-ESR (high-Q) ceramics cause combination of multiplenarrowdips, with massive holes in-between.So this offers no benefit because we didn't need that SRF dip to begin with;it's still just a collection of narrow frequenciesthatstillform a very small percentage of the needed bandwidth. You still need to utilize the impedancebetweenthese dips to provide the load the impedance it needs.In which case, using one large capacitor which has the lowest overall impedance is the obvious, and right solution.Multi-capacitor solution becomes interesting, even theoretically, only when the large capacitor alone has too much inductance. Paralleling 1nF, 10nF, 100nF ceramic capacitors on a 3.3V supply makes absolutely no sense since 100nF is available in the smallest packages, with the same inductance as 1nF.

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 10:28:35 am
content: Quote from: David Hess on July 20, 2020, 10:33:11 pmThat is very strange, because in my experience it's very hard to fuck up decoupling below 3GHz. Even just one or two capacitors of 470nF or 1uF gives low impedance up to 6GHz without any effort. If you are having problems at 1.2GHz the layout must be at fault.IMO the layout is as important as the capacitors themselves, especially where you put ground vias. I drew a quick illustration of the problem:The blue lines show current paths:Or even worse, using a single ground via for a decoupling cap.Btw the layout shown on the left performs better than putting vias inside the pads. You can avoid via-in-pad completely if you know what you are doing, even at many GHz.

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 10:35:37 am
content: This is how you do it for a 0402 cap:

author: Ice-Tea
author_rank: Super Contributor
timestamp: July 21, 2020, 11:03:42 am
content: What's the target application/frequency for that layout? Seems a bit overkill for a 'regular' board. Not to mention that it will be a total pain for other layers. If you do that for every cap on the board, power planes are going to look like a horror show...

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 11:12:17 am
content: Don't use power planes (unless the situation really calls for it, and never as a rule of thumb). That's another myth. This is a 4 layer board and the frequency range is 6GHz. On 4 layers with this stackup (0.2mm prepreg), power planes are completely useless for decoupling. The only potential use case for a power plane is to serve a double purpose of a ground plane that signals can travel against and at the same time deliver power. That's what I did for DDR3 + Zynq on 4 layers, but it's not going to work for RF applications because you'd need a stitching capacitor ever few mm.

author: Ice-Tea
author_rank: Super Contributor
timestamp: July 21, 2020, 01:08:49 pm
content: Interesting. I was under the impression powerplane/gndplane capacitive coupling was the highest freq/"first line responder". Granted, probably works better if the separation is less than 0.2mm but still.. Any documentation for that?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 21, 2020, 01:43:06 pm
content: Quote from: OwO on July 21, 2020, 11:12:17 amRF applications differ as greatly as any other application does. Approval or dismissal of planes is irrelevant without additional facts.You wouldn't route RF signals through planes themselves, that's ridiculous. But then, what about the very wide stripline connections to large power transistors? These have line-wave transmission line impedances of a few ohms -- they would be excellent planes for a DDR interface!Conversely, youwouldroute RF signals over power planes, even gaps between planes. The gaps can be bypassed locally as needed, or differential signals can be used. (Preferably, gaps are avoided, of course.)Quote from: Tomorokoshi on July 20, 2020, 08:33:22 pmNot a very solidly stated thesis, but the result is equivalent I think to noting that, for a C1 || (R+C2) network, R = Xc1 and C2 > 2.5 C1 should be chosen to thoroughly spoil the Q of C1 at the crossover frequency (which is also what gives Xc1).TimTim

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: July 21, 2020, 03:08:48 pm
content: Ever since I put a number of layouts into actual EM solvers I realized that everyone on the internet who says 'you have to do itthis way' is wrong.The way you have your grounds, and your substrate thickness, and whether or not you cannot have blind vias, all matter and completely change what is the 'best approach'. Not to mention that people often confuse two completely different ideas and don't get that they are two different targets with different ways to get there.If you really want to understand and know, do yourself a favor: Stop going by some online forum post telling you what to do, and go rent/buy a copy of an EM package for a few weeks, and actually play around in that. Try different substrates, different thicknesses, different types of capacitor, different styles of mounting, etc. Notice how sometimes, it's actually better to just wire to the chip than to try and drop down to a via on a plane, because that added loop area is doing more harm than good. Or that trying to get 10 mOhm supply impedance at 100 MHz is pretty much pointless, because a single bondwire will absolutely destroy your impedance at that frequency.Sometimes your traget is noise suppression/noise isolation. You want noise from device A not to get to device B. In part by making the power supply able to counter some of the noise, in part by throwing filter caps at it, and in part by reducing the noise in the first place with more capacitance. Applications? LNAs, precision analog, etc.But other times your target isn't noise suppression, but is actually supply impedance. Getting high performance, high power RF amplifiers and so on to work, often has far less to do with keeping noise in the PA at bay, and much more to do with making sure the PA can draw whatever current it damn well pleases without the supply limiting that.Some interesting things I found: When working with 2/4 layer PCBs, going to ground plane near chip was pointless, because the via inductance negated any benefit. But on some of the very high frequency boards I'm working, with 50um core's, using blind vias, going to planes actually made my 0402 caps completely unnecessary.There are also some interesting things when putting caps in parallel - Dell has a patent (US 6,337,798) that claims that putting caps in parallel will actually significantly reduce the efficacy of those caps because of skin effect and current crowding.This is also why I suspect that OwO's example is actually not useful. The current crowding will just make all but the few outer vias pointless. Might as well get rid of them, your routing, and your wallet will thank you.I have a bunch of slides that I've been meaning to release about this, but right now they still contain a bunch of unpublished PCBs as examples so I have to wait a few more months before I can.Another thing I learned: Discrete components are pointless to do any decoupling past a few hundred MHz. Even if you ignore any layout effects, the interal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range. You just can't get around that without using special bonded capacitors meant for RF/MMIC applications. And to be frank, even if you could, your bond wires will just ruin that too. Just trust that the IC guys know their stuff and take care of decap past 100 MHz.

author: ehughes
author_rank: Frequent Contributor
timestamp: July 21, 2020, 03:36:52 pm
content: QuoteWhat field solver do you use?

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 21, 2020, 03:40:09 pm
content: Quote from: CatalinaWOW on July 20, 2020, 11:10:16 pmYup. Obviously rules that made sense when using TH capacitors are not to be translated directly when using modern SMD packages.Still, they have the merit of making engineers AWARE of the question of frequency response for capacitors. May sound obvious for experienced engineers, but still not so much for beginners; and this kind of articles, along with the fact things have indeed evolved a lot with modern packaging, doesn't necessarily help: sure this is food for thought for the experienced, but may give a false impression for young engineers that capacitors' frequency response doesn't matter at all. And yes, beyond caps, PCB design can matter a lot too.You may object that you don't have inexperienced engineers design high-frequency stuff anyway, but reality is sometimes a different story. When dealing with digital circuits these days, a given design has a good chance of being in the high-frequency realm.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: July 21, 2020, 03:46:18 pm
content: Quote from: ehughes on July 21, 2020, 03:36:52 pmKeysight ADS/Momentum and EMPro/HFSS for 3D simulations. I realize that those tools are outside of the average engineers budget, but you can also get very capable simulators like Sonnet and similar for lower cost, especially if you just want to do smaller simulations (like, say, some individual decoupling capacitors).

author: David Hess
author_rank: Super Contributor
timestamp: July 21, 2020, 03:53:24 pm
content: Quote from: OwO on July 21, 2020, 10:28:35 amThe problem was that the layout was much better than anything possible on a board; the capacitors were literally and physically part of a coaxial transmission line, and everything was symmetrical. So there wasn't anything to adjust or improve except maybe fabrication accuracy.A similar coplanar waveguide would have been limited to 4 capacitors and I was up against power limits so the radial structure was used instead allowing 12, or even more had I made it larger, capacitors in parallel. And if it was a large signal effect from high power, then why would the lower value capacitors improve the situation?Lacking suitable RF test equipment, I declared victory and moved on. Had it not worked, I would have replaced the common C0G ceramic capacitors with RF capacitors and tried again.

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 04:15:04 pm
content: Quote from: TheUnnamedNewbie on July 21, 2020, 03:08:48 pmOr actually you know, make real life measurements that will tell you a typical 0402 1uF capacitor has good decoupling up to 6GHz. Or if you don't have the TE maybe manufacturer's graphs will convince you?http://weblib.samsungsem.com/mlcc/mlcc-ec-data-sheet.do?partNumber=CL05A105KA5NQNYou are already halfway to being enlightened. The first half is knowing that "best practices" are BS, the second half is knowing simulations are BS.

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 04:26:56 pm
content: I did the simple experiment of soldering various 0603 parts directly to a SMA female connector (by sawing off all legs first) and measuring with a good VNA (not a cheapo nanovna). The results agreed with what the manufacturer's graphs say. So it's impossible that you can not get good decoupling out of a common X7R cap. How you lay out the board should also not be based on rules or simulation, but rather what you have tried and verified (with measurements) in the past. I recently designed a upright SMA to microstrip transition with almost 30dB return loss to 3GHz, and found that simulations are completely inaccurate and such results can only be achieved by experiments and a good VNA/cal kit.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 21, 2020, 04:35:43 pm
content: FYI, 3GHz is DC for @TheUnnamedNewbie. Not sure how familiar you are with his work.Quote from: OwO on July 21, 2020, 04:15:04 pmAh yes, simulations can never be correct so why even bother! It's not like anyone haseverbuilt anything of significance, let alone had it work perfectly the first time, using a filthysimulator!Tim

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 04:38:10 pm
content: So how did he conclude that discrete capacitors are ineffective beyond a few hundred MHz (which is demonstrably false)? If your simulations differ that far from reality, then I'll say it's almost useless.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 21, 2020, 04:46:31 pm
content: Simulations are as good as your models are. I'm kind of questioning the models he used.

author: ejeffrey
author_rank: Super Contributor
timestamp: July 21, 2020, 04:53:05 pm
content: Quote from: OwO on July 21, 2020, 04:15:04 pmTrusting manufacturer graphs over simulations is terrible advice. Even trusting your own measurements over simulation is dubious at best, but at least you know the measurement setup. In this case, those graphs are de-embedded to the pads, and don't reflect performance in any real circuit. They show the AC voltage across the capacitor for a given excitation current. But nobody actually cares about the voltage across the capacitor. These models are in fact best suited for embedding into field simulators and in that capacity they are quite useful. For directly predicting performance they are a guide to be used cautiously at best.

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 04:54:03 pm
content: No doubt that simulations are useful for sanity checking your work, and I use them to give a rough ballpark answer to "is this design workable" and to find pitfalls of a design that I missed (e.g. potential stability issues), but my point is you should never trust it to give an authoritative answer to "how well will this perform" or "are these vias useless". Only real world experiments can say for sure. So to tell people "get a simulator, it will teach you how to do good layouts" is bad advice, and IMO that money is better spent on good TE instead, or even just experimentation and prototypes.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: July 21, 2020, 04:58:13 pm
content: Quote from: OwO on July 21, 2020, 04:15:04 pmI stated clearly that the self-resonance was at a few hunderd MHz. Your example shows that the self-resonance is at 10 MHz (and that is usually without any pad and so on included, which will only push it further down.If your simulations do not match your measurements, one of the two is done poorly. This can be misunderstanding how to do them, bad simulation setup, bad material properties, etc. We have desigend VCOs at 600 GHz that had a shift between measurement and simulation in the tens of MHz. So please go tell someone else he doesn't know what he is doing and that my simulations must be bad.Now, back to my example and clarifying why there is little use in having those tiny capacitors and going nuts about your vias:A bondwire of 1 mm is what, about 100 mOhm? Probably a good bit more at high frequencies due to skin-effect. Typical rule of thumb for bondwire inductance is 1 nH per mm. Plug that in and you find that you will have an impedance of about 600 mOhm at 100 MHz. So past 100 MHz, your chip is not gonna see a much lower supply impedance than 600 mOhm anyways. It doesn't matter if your supply impedance is 100 mOhm, 10 mOhm , or 1 nOhm at 1 GHz - your chip will just see the (at that point 6 Ohm) bondwire. Anything past a few tens to hundreds of MHz is for on-chip decoupling to solve. Sure, you can do better, and you shouldn't allow it to get horrible, but most of your decap will be done on-chip anyways.And before you say 'But RF transistors!' - Usually, you slap a big fat inductor on your supply of the transistor to tune out the internal capacitance anyways. Probably the internal parasitic capacitance of your device is going to do more 'decoupling' than any external decap you add.Quote from: SiliconWizard on July 21, 2020, 04:46:31 pmI used high-performance models from multiple manufacturers: Samsung, TDK, Taiyo Yunden, Murata, as well as from Modelithics. They pretty much all tell you the same story, and line up with what their websites tell you. And the software and methods are the same used to design high-performance filters on PCB - there might be a few percent error, but it's not going to be an order-of-magnitude difference.

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 05:05:47 pm
content: I think we went from talking about digital ICs to RF circuits many posts ago. The #1 use case for a low impedance point on the power supply network in a RF circuit is for interference rejection, and there no bond wires come into play.See for example this power supply filtering layout:This is good to 6GHz, and if your models are good enough you should be able to see for yourself. The capacitors are CL05A105KA5NQN. The distance to ground plane is 0.2mm and material is FR4. You can't make a blanket statement that discrete caps are no good beyond a few hundred MHz.

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 05:13:39 pm
content: QuoteThe problem with that is there is no "internal ESL" of a capacitor. Any inductance is due to the physical layout and the path that current has to follow. A wire by itself doesn't have defined inductance, and only the combination of a wire + ground plane does. I showed a few posts ago how to minimize the layout effects and in that example the impedance is mainly only due to the stub of transmission line between the DUT and the capacitor (which can be minimized by making it wide). I'm sure the manufacturer used a similar layout when characterizing the capacitor.The SRF of a capacitor is not important. You only care about the worst case impedance across a frequency range.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: July 21, 2020, 05:20:10 pm
content: Quote from: OwO on July 21, 2020, 05:05:47 pmI never said that discrete are no good at all. I said, and I quote:Quote from: TheUnnamedNewbie on July 21, 2020, 03:08:48 pmThe topic of this is also 'power decoupling myths'. If you read my posts, you'll notice all I talked about was power supply decoupling. You are always gonna find special cases. But this entire thread of posts before was clearly about powersupply decoupling, and your posts and images implied your way was needed.And don't try to now straw man me into being wrong by throwing the old 'but inductors need a loop' argument. You know all to well what I meant with ESL, and if you don't you aren't a very good RF engineer.And SRF is important, because it gives you a nice point to know 'It all goes down-hill from here'.Quote from: OwO on July 21, 2020, 05:13:39 pmMaking a setup to calibrate out the inductance of your test network is trivial. We do it all the time, because that is what VNA calibration is all about. That PCB inductance is thus NOT included in the models, because if it were, the models would be all but useless for design work.

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 05:28:11 pm
content: "Discrete components are pointless to do any decoupling past a few hundred MHz" is misleading, since it's implying it's the discrete components that are no good, when the real matter is the bond wires defeating any decoupling attempts."the internal ESL of a 008004 cap makes it's self-resonance frequency be around the 100 MHz range" is correct on its own, but within the context a reader will think you mean the internal ESL of a discrete cap makes it useless above a few hundred MHz, which I explained is incorrect. Again, SRF of 10MHz is irrelevant when the impedance is still < 5 ohms at 6GHz.Anyway, I don't get the appeal to authority bringing up your 600GHz design, because you are designing on a process with feature size possibly 1000x smaller than on a PCB, in other words a 6GHz design on an ordinary FR4 PCB is no easier layout-wise than a 600GHz design on a 1um process. It's like telling someone to design a 1GHz circuit using a wire-wrap process that his design is "DC" to you who designs stuff with geometries 10k times smaller.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: July 21, 2020, 05:34:14 pm
content: Quote from: OwO on July 21, 2020, 05:28:11 pmExplicitly situation the context of a statement is clearly misleading, unlike, say, showing pictures with a big red cross under a layout that is perfectly fine in 99.9% of cases, and a green check mark under a layout that has arguably way to many vias that will just make the layout a hell in any high-density situation.

author: iMo
author_rank: Super Contributor
timestamp: July 21, 2020, 05:38:51 pm
content: I've quickly looked at the pdfs in the first post. I did a recommendation on "3 capacitors in parallel" many times here. I saw that in an app note of ADI (as far as I can remember) long time back.One of the issues I see with the attempt to debunk the myth is following - the ADI recommendation (and mine here as well) said explicitly you have to use 3 capacitors in 1:100 ratio, like 100p||10n||1u, etc..Not in 1:10 as it has been elaborated above..

author: OwO
author_rank: Super Contributor
timestamp: July 21, 2020, 05:49:02 pm
content: The takeaway from the discussion above is that the capacitor values are not that important, it's the overall layout, and the fact that the bond wire in a typical IC defeats your decoupling attempts and you will do just as good with a single 1uF or 10uF cap in the common case of decoupling a digital IC. But if you are doing any other kind of design, the best layout should be decided on a case by case basis.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 21, 2020, 06:02:06 pm
content: Yes, the point is, C value isn't important as long as you have enough. After you satisfy this minimum condition, you select by L.In the past, large enough C had kind-of too much L, so you paralleled larger and smaller C to get "best of the both worlds". Said types had enough ESR to make the SFR low-impedance dips not too shallow, but combine in larger areas without so much risk of oscillation.Now, you get large enough C with small enough L, just buy a bog-standard small-case MLCC. Say 0.47uF 0402 part, for example. So there is noreasonfor the paralleling trick.Furher, the ESR of modern MLCC is so low, making Q high, that the parallel combination contains new extrariskof oscillation.

author: iMo
author_rank: Super Contributor
timestamp: July 21, 2020, 06:08:13 pm
content: When you look at the "V" shaped frequency characteristics of the capacitors - smds of any shapes and values almost all manufacturers show it in their datasheets, it is clear, at least for me, that paralleling more capacitors makes sense. Not in 1:10 ratio, as the "V" shapes are too close each other and it really makes no sense - but 1:100 makes sense.. Talking RF here, not the power supplies, however..

author: thm_w
author_rank: Super Contributor
timestamp: July 21, 2020, 09:08:21 pm
content: Quote from: imo on July 21, 2020, 06:08:13 pmDid you read all of the first link from OP?Unless you are targeting a very specific frequency, the simulation shows its no better.

author: exe
author_rank: Unknown
timestamp: July 21, 2020, 10:15:39 pm
content: I'm confused. For years I was reading that a solid ground plane is a must for a high-speed or mixed-signal design. So, it's a lie?Also, what do you guys think of capacitor bypass sequencing? (http://www.sigcon.com/Pubs/news/9_07.htm). In terms of isolating rest of the system from "noisy" components. It's very hard to find info on the topic, even harder to find a source with measurements. Most sources either provide "best practices" without going into details, or provide only theory, but not practical measurements, which makes it suspicious for me as I've seen people go very far in delusions (e.g., audiopholery).

author: David Hess
author_rank: Super Contributor
timestamp: July 21, 2020, 10:29:15 pm
content: Quote from: exe on July 21, 2020, 10:15:39 pmIt is not exactly a lie, but there are places where a ground plane is either not required or inappropriate. A ground plane provides the most direct route for return currents but if that can be provided in other ways, then it is not needed, and it is inappropriate where return currents must be directed around sensitive nodes. The alternatives require careful attention to return currents, ground loops, single point grounds, and other such things.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 22, 2020, 03:28:52 am
content: Quote from: exe on July 21, 2020, 10:15:39 pmIneffectual, for similar reasons as the, aherm, discussion, above. Which, I'm certain my explanation will get misinterpreted just as poorly...The attenuation from pin to plane, for either connection shown, is minuscule. The trace connected one will have a little more than the other. It is easy to calculate what the cutoff frequency will be (given some other assumptions), and subsequent impedance peak seen at the IC pin.The real question is, are those values -- the impedance and frequency -- meaningful? Are they desired? Do they meet a specification? If so, what?Note that there are two different goals:1. The impedance at one port of the PDN (power distribution network)2. The attenuation from that port to other ports (examples: other device power pins, conducted EMI on cables, radiated EMI to space).In general, simply having a low supply impedance at a pin will give good attenuation for a given current: V = I*Z. But it's a zeroth order relation: it doesn't have any scaling or anything, it is what it is.If you can't brute-force the impedance, and your attempts to do so are frustrated by unintended resonances (leading to peaks in pin impedance, and peaks in transmission through the network), you will have found the limit of that method.To do better, you need to design the filter. Specify port impedances, and the minimum attenuation over some frequency range. Notice zero and infinity are NOT valid inputs to this process! You are therefore forced to consider what impedances and attenuations are actually required, and have to consider what is actually possible. A meaningful process ensues, and component values and trace/plane geometry can be solved for.To put it differently:The above article is wrong, in a completely separate way. The question we must ask is, not whether one or the other is better, but what are the properties of both, and how can we design those properties?The simplest way to get high attenuation -- good filtering between ports -- is to use inductors, or CLC ladders; lowpass filters in general -- to connect between them. The impedance of these filters must be suitable for the source and load, and the cutoff and attenuation are defined by the frequencies and attenuation of interest. Additionally, we should give some thought to grounding (avoiding ground loops) and shielding, particularly when the desired attenuation is very large (say >60-80dB).With a fully specified procedure, we have no fear of encountering the situation that a naive designer might find themselves in when they, say, randomly pepper 100uH chokes throughout a design -- sure the attenuation might be great, but the impedance is massive, and must either be balanced by generous bulk filter caps (lossy ones at that), or employed only for high impedance loads. And with a "random peppering", the attenuation attained might be all over the board -- excessive (wasteful of BOM cost and board area) in some areas, yet insufficient in others.This is equally valid at 60Hz as it is at 60GHz.Tim

author: OwO
author_rank: Super Contributor
timestamp: July 22, 2020, 05:31:53 am
content: If you have the luxury of high layer count boards with very close planes, then going to the plane is usually what you want to do. But if not, then this is probably the best decoupling you can get:You can not make a blanket statement that capacitor "sequencing" is ineffective, or that you should always sequence capacitors. There is no substitute for simply having experience by doing lots of experiments, measurements, and trial and error. If you are new to high speed design, there is no better way to shoot yourself in the foot and lull yourself into a false sense of security than by playing around in a 3d EM simulator (and I learned this by experience too). Do some shitty designs, make mistakes, understand why they fail, make bodges on PCBs and do measurements to understand how the physical world really behaves.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 22, 2020, 08:40:38 am
content: Quote from: imo on July 21, 2020, 06:08:13 pmYes but your circuit likely does not draw currents at those exact frequencies defined by the "V" valleys. Your circuits want low impedancebetweenthose V dips as well. If you are able to provide low enough impedance through the whole spectrum, then adding a few additional even-lower dips is completely meaningless.

author: mawyatt
author_rank: Super Contributor
timestamp: July 22, 2020, 03:10:57 pm
content: Quote from: T3sl4co1l on July 21, 2020, 04:35:43 pmTim,Well I also got a good laughI'm sure Maxwell didn't know anything, neither did Larry Nagal (SPICE), or Ken Kundert (Cadence)Best,

author: mawyatt
author_rank: Super Contributor
timestamp: July 22, 2020, 03:36:16 pm
content: Quote from: TheUnnamedNewbie on July 21, 2020, 03:08:48 pmOn the IC side of things where I just retired from we always tried to simulate the effects of poor off-chip supply decoupling and included as much decoupling as possible on the chip. Circuits were used that were less supply sensitive like differential circuits if practical. We often used multiple regulators (Point of Load Regulation) because of decoupling, many times just getting to a chip pad wasn't practical, so a local regulator was utilized. This isn't restricted to analog/RF/MW circuits, with a massive array of digital gates all working in lock-step with the clock, very large di/dt are created and tax the decoupling schemes, both on and off chip.Best,

author: OwO
author_rank: Super Contributor
timestamp: July 22, 2020, 03:57:24 pm
content: That was in response to this:Quote from: TheUnnamedNewbie on July 21, 2020, 03:08:48 pmSimulations will not help you "understand and know". Maybe if you are already experienced and already know how to improve a layout, sure. But to suggest trying to *learn* by playing in a simulator is bad advice and will lead a beginner the wrong way. Someone experienced like you know instantly when a simulation is unphysical, either due to setting up the wrong conditions or bad models. Someone inexperienced with RF layout needs to do everything EXCEPT go buy an expensive 3d EM simulator and spend hours going down rabbit holes of unphysical and unrealizable designs, without even realizing why their design that performs perfectly in simulation is impossible to realize in real life.I also don't get the point of saying 3GHz is DC to you, because a RFIC has geometries at least 1000x smaller than a PCB, so a 600GHz RFIC circuit is like laying out a 600MHz circuit on a PCB. Not the same thing of course, the basic circuit elements you have available to work with are completely different, but layout wise your elements at 600GHz are electrically small, while at 6GHz the simple via distance or the inter-plane distance on a PCB is getting significant relative to a quarter wavelength.

author: OwO
author_rank: Super Contributor
timestamp: July 22, 2020, 04:07:18 pm
content: For a beginner wanting to start with RF design, start with pen and paper. Start with deriving the transmission line equations (telegrapher's equations) to understand 1D wave behavior, and work your way up to wave equation in 2D/3D and maxwell's equations. You need to be able to visualize how a changing electric or magnetic field give rise to each other, and how fields are related to currents and charges. None of this insight can ever be gained by playing in an expensive EM simulator. I recommend just going to your local university and auditing the high frequency electronics and electromagnetism classes up to 4th year level. None of these classes will involve a 3D EM simulator, maybe RFSim99 at most. RFSim99 is useful for checking basic circuits, but again ONLY if you already understood the underlying transmission line theory beforehand. Same story with full EM simulators, don't even touch them until you can fully visualize EM wave behavior and know maxwell's equations by heart.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: July 22, 2020, 04:48:59 pm
content: I'm a big fan of the Smith Chart. In any case you'll need to know about it to interpret VNA displays.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: July 22, 2020, 04:54:09 pm
content: Quote from: OwO on July 22, 2020, 03:57:24 pmSo, just some comments on this:- I figured that someone at this level of engineering, where they start to really ask questions of how power supply decoupling and filtering works, is no longer a beginner. Hence I stand by my statement that they could gain a lot of knowledge from simulating this kind of structure. At least a lot more than just trying to make sense of the 200 contradicting guidelines online.- Simulations with PCBs at frequencies up to a few GHz, in my experience, never show nonphysical behaviour unless you are just purposefully messing up the meshing settings. Just runing through the few tutorial examples should teach you all you need to know to simulate some decap networks. This isn't simulating some 10-pole comb-line filter or SIW or multi-band stacked patch antenna. Just a capacitor and a few pieces of copper wire.Quote from: OwO on July 22, 2020, 03:57:24 pmMy latest work involves a 100-190 GHz PCB vivaldi antenna, and a 110-170 GHz 4-layer orthomode waveguide coupler. All on PCBs. Not even that extremely fancy PCBs, regular HDI boards. Heck, I don't even have frigin blind vias! The 600 GHz transmitter was just an example.Just because I work in a team that does RFIC design does not mean that I only do RFIC design. And if you really think making 600 GHz RFICs in CMOS is that trivial, be my guest, and let me know when you pull it off.Quote from: OwO on July 22, 2020, 04:07:18 pmI fully agree that people starting with RF design should start there. That is also what we teach. But this was never fully on RF performance - this was power supply decoupling. Most cases, the caps are actually close enough to the IC's you are decoupling that you can ignore transmission line effects up to a few GHz. So all I said still stands. You are trying to make this an RF discussion, but it is not - I merely used my RF background to illustrate that I do actually have some knowledge when I talk about simulations and their merits.Also: We do actually use ADS/Momentum to teach students in I think their 4th year here. With these tools being so accessible and common-place now, and frequencies going up in the industry, more and more companies are asking for students with better understanding of the simulation workflow.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 22, 2020, 10:46:23 pm
content: I enjoyed the implication that one cannot learn anything about a system by poking at it blindly.Tim

author: exe
author_rank: Unknown
timestamp: July 24, 2020, 07:53:38 am
content: Question: are capacitors with reverse geometry any better for decoupling? I concluded that, unless it helps to minimize track lengths, it doesn't matter. So, it should help if supply pins close to each other, but it is pointless if supply pins are far. But I've never checked this. Any opinions?

author: Siwastaja
author_rank: Super Contributor
timestamp: July 24, 2020, 08:13:54 am
content: Quote from: exe on July 24, 2020, 07:53:38 amObviously, you'll be able to squeeze the loop area a bit smaller. A small optimization.The availability, cost, and uncertainty in second-sourcing weigh more, I'm afraid.For general-purpose IC decoupling, this doesn't matter; you can use a 100nF 0201 for example, reversing it makes very little difference.In power electronics with large C values this could be beneficial, though they have larger loop area caused by larger semiconductors as well so the capacitor is still a small part of that. I use quite a lot of 1206 parts when I need around 48V busses, 0805 is quite marginal, both for voltage ratings available, and amount of actual capacitance available under the DC bias. 1206 has a stupid shape, and 1210 is too big alraedy, so I'd prefer say a 0909 or 1010 instead, but the real-world availability of the parts is what drives the decision.On the other hand, with 1206, I'm able to place additional vias for both pads under the component body, while avoiding via-in-pad. For reverse geometry, I would definitely need via-in-pad in order to exceed the performance of the 1206 design.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: July 24, 2020, 08:21:22 am
content: Quote from: exe on July 24, 2020, 07:53:38 amI think one of the bigger advantages can actually be placement, instead of loop area. The impedance is lower, because not just the loop area on PCB, but also internally in the capacitor, the plates are shorter and wider, which gives you lower ESL.Murata had a document showing how a 'reverse geometry' cap can give you higher denstiy, because when you align them with pins, you have the narrow side of the cap near the chip. (image source:https://www.murata.com/en-global/products/capacitor/mlcc/smd/lll)

author: exe
author_rank: Unknown
timestamp: July 24, 2020, 09:21:09 am
content: Quote from: TheUnnamedNewbie on July 24, 2020, 08:21:22 amHuh, this rises even more questions. One is, in another thread recently people concluded that if two ICs are that close, then they can share the same decoupling cap. Sorta what murata proposes, except that there is no need to use fancy caps. What do you think?And another question that bothers me a lot. A common best practice is to put a decoupling capacitor for each power pin. I often have one LDO supplying power to multiple ICs. Question: can these caps start resonating with each other? Or should I use a separate LDO for each potentially noisy IC? To be more specific, my typical scenario: MCU, ADC (with two power rails: analog and digital), and digital isolator on the same board.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: July 24, 2020, 11:46:40 am
content: As I've stated a few times now, it's really impossible to make any hard guidelines. If you want to be really safe, it is likely easier to get good noise isolation by having separate LDOs for each. ADCs (or general mixed-signal chips) are a whole different can of worms with people giving contradicting advise on how to do things in terms of decoupling and supply noise. One of the issues there is that you have currents that might want to flow from the analog supply to the digital ground and vice-versa, so your loop area becomes massive for those currents. (incidentally, also why so much on-chip stuff goes differential for those applications - you have no high-frequency common-mode noise, so less common-mode noise issues)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 24, 2020, 05:35:08 pm
content: Quote from: exe on July 24, 2020, 09:21:09 am"that" close = ?If they are slow logic or analog ICs, locality of bypass won't matter. Example: CD4000 logic, TL072 amps. There simply isn't any energy or gain at frequencies high enough to matter; bypasses can be inches away. (If even that: historic example, the NES controller used a, CD4021 I think, and that's literally all that's soldered to the board. No bypass caps, just a long cable with +5V and GND, clock, strobe and data. The controller buttons are carbon-rubber pads touching gold plated traces, and the pull-up resistors are screen-printed ink!)74LS and HC are fast enough you'll want a cap within a few inches, but the chips being smaller than "a few inches" means a few chips can probably share.74LVC and most <= 3.3V CMOS devices (MCUs, etc.) are fast enough that you probably want the local-at-the-pins bypass caps, and not only that but if you have heavy loads on them (e.g., MCUs and bus drivers can switch a few 100 mA at a time, through whatever combination of IO and power pins). Wide-format capacitors may be advantageous.The best use-case is where a plane wave needs to be shunted to ground. The plane wave propagates along a wide transmission line or plane. It goes into the capacitors broadside (as many lined up in parallel as needed to cover the width of the plane), then into vias to ground (arrayed opposite the plane, along the C's GND pad).There probably aren't many practical cases where this exact situation arises...Most loads are through narrow pins, traces or vias, and there are simply a lot of them, and not always in regular patterns. So the best you can do is sink them all to planes, and bypass the planes at the earliest convenience. (Example: most any device that has to be a BGA, is probably also fast enough to need immediate bypassing, but also has to be connected in this way, i.e. through an array of vias.)A resonant stub, in RF circuitry, I think is a good example, and some have been pictured earlier in this thread I think. The vias, capacitor and trace are all accounted for in the total length of the stub, and the trace width is held constant thanks to the wide (appropriately chosen) capacitor. So there's no error due to lumped equivalent whatever.QuoteCan they? Perhaps. Draw the equivalent network and see if it does.See, your very next question must be: what information do I need to figure it out? Well, you don't have resonance without L and C. What are the stray L's in the circuit? What resistance dampens it? What transient loads/sources might excite it? And then you can answer these, quantitatively, by inspection of the circuit, build a model, and test it.Tim

author: David Hess
author_rank: Super Contributor
timestamp: July 24, 2020, 05:54:20 pm
content: Quote from: exe on July 24, 2020, 09:21:09 amYes, it is possible, and it can be calculated with transmission line length, loss, and impedance but this is not always easy. The impedance mismatch between the transmission line and decoupling capacitors causes reflections and if the Q is high enough, they become a problem. One solution is to properly terminate the transmission line. Lossy ferrite beads or RLC decoupling can be used to decrease Q which has saved me a few times before I understood what was happening.

author: exe
author_rank: Unknown
timestamp: July 24, 2020, 08:43:36 pm
content: I let myself ask another question or two about decoupling and noise.Is it a common practice to use, say, series resistors on digital lines? I once did an experiment: I breadboarded an spi digital isolator. When I probed the signal there was massive ringing (thanks to long jump wires). I installed 1K resistors in series and all ringing was gone. Why 1K? Values much bigger than that increased rise time too much for the data rate.Strangely enough I almost never heard of this method of reducing digital noise. Only in one datasheet for an LT ADC there was a suggestion to put up to, afaik, 150 Ohm resistor. Values bigger than that were discouraged because digital inputs had some sort of protection from slowly rising signals, or something like that. I don't remember what part was that, but, e.g., datasheet for ltc2420 also mentions serial and parallel termination of digital lines.I've also seen a small series resistor (1-2 Ohm) before ldo and its input capacitor. This, presumably, should reduce noise from fast-switching load back to the power rail. Is this a common practice? If not, why?

author: thm_w
author_rank: Super Contributor
timestamp: July 24, 2020, 10:46:28 pm
content: Quote from: exe on July 24, 2020, 08:43:36 pmIts not terribly common, because the device would work without them (unless we are talking about high speed signals 200MHz+), the benefit is for noise as you say in specific situations. eg TI suggests doing this for their 24-bit ADCs. Or if you were driving a chip thats a long distance on the board and worried about EMI, it would be worth adding. Otherwise, why add them? Build your circuit on a PCB and see if there is much ringing."TI recommends placing 47-Ω resistors in series with all digital input and output pins (CS, SCLK, DIN, DOUT/DRDY, DRDY, RESET and START). This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care must be taken to meet all SPI timing requirements because the additional resistors interact with the bus capacitances present on the digital signal lines"QuoteSometimes this resistor is for additional power dissipation reasons. Normally you'd use a ferrite bead for noise suppression.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 24, 2020, 11:05:01 pm
content: Jumper wires on breadboarding will be in the 150-300 ohm range; a comparable size resistor will control the ringing. Loose wires make poor transmission lines, expect lots of coupling between groupings.The general term is "source termination resistor", for which you should find a lot of information I would think.Ferrite beads are useful for the same purposes, for similar reasons -- at ~100MHz they offer significant resistance (per the rating).Tim

author: exe
author_rank: Unknown
timestamp: July 25, 2020, 10:37:58 am
content: Can you advice me on which ferite beads to use? From what I read, there is always a danger of resonance between ferite beads and decoupling caps. Would it help to use the beads with the biggest dc resistance? (I bought some with 2 Ohm beads, but never tried them in action). I work with low-power stuff (dac, adc, mcu) and my concern is noise injection into analog circuitry.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 25, 2020, 03:14:38 pm
content: Again, for what? This is not a cut-and-dry situation! If you need simple answers, just bypass it and be done; if you find problems, spin the board with more filtering.Tim

author: David Hess
author_rank: Super Contributor
timestamp: July 26, 2020, 02:18:41 am
content: Quote from: exe on July 25, 2020, 10:37:58 amI have never heard of that happening with ferrite beads because they are designed to be very lossy, but I have had it happen with low loss inductors which would have been more suited for a switching power supply. The solution to that is a parallel resistor across the inductor to lower the Q and this decoupling configuration is common in old test equipment between assemblies.At a low enough power, RC decoupling becomes reasonable. A ferrite bead normally only provides a couple hundred ohms so if the current draw is low enough for a couple hundred ohm or larger resistor, just use the resistor.

author: exe
author_rank: Unknown
timestamp: July 26, 2020, 08:27:37 am
content: Quote from: T3sl4co1l on July 25, 2020, 03:14:38 pmMaking new boards is what I'm trying to avoid. My current approach is to add a footprint for the bead. If it's not needed I'll just put a zero-ohm resistor.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 26, 2020, 09:09:46 am
content: Quote from: exe on July 26, 2020, 08:27:37 amNote that if you are doing one-offs, say, less than 5pcs, it's likely a more optimum configuration to skip that footprint altogether and just bodge when necessary. Optimum in terms of the big picture, that is.This is because 95% of the time, you don't find any problem and don't need to add the bead, so you end up soldering those jumper resistors by default. All of this is extra work in schematic, layout, and hand-fabrication you need to do every time, for every unit.Instead, I tend to design in what Iexpectto be the final configuration, then if I missed something or measure an unexpected problem, I bodge it to the PCB, cutting a trace and adding a ferrite bead somewhere is not too difficult if it only happens 5% of the time.Generally, I have been reducing the "trying to think about every possibility beforehand" mentality, reducing placeholders, extra prototyping features etc., because I found out I rarely have time to try and measure every possible thing I thought would be nice-to-have beforehand. And when I do have a problem, it happens to be something I didnotexpect to see... So I try to make prototypes as close as the final product as possible, then work around the limitations when necesssary.Number of cases I have needed to re-spin a prototype PCB (something serious enough that it can't be bodged): 0.But this is just my €0.02.

author: electrolust
author_rank: Unknown
timestamp: July 31, 2020, 09:46:45 pm
content: https://www.picotest.com/products_Decoupling_Test_Board_Kit.html#gsc.tab=0