FPGA - GCLK Vs LHCLK Vs RHCLK - Page 1
Forum section: electronics / general

author: 2X
author_rank: Frequent Contributor
timestamp: October 01, 2025, 08:41:55 am
content: Hello, what is the difference between the GCLK Vs LHCLK Vs RHCLK on a Spartan-3A FPGA? From the “Spartan-3A FPGA Family” datasheet I found the below description. It says that the “RHCLK” inputs optionally clock the right half of the device and the “LHCLK” inputs optionally clock the left half of the device.Also, the “GCLK” global clock inputs can optionally clock the entire device, so if the global clock inputs can clock the entire FPGA why the “LHCLK” & “RHCLK” are existing?Excerpt from Spartan-3A FPGA Family pdf:Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 global clock inputs that optionally clock the entire device. The exceptions are the TQ144 and the XC3S50A in the FT256 package). The RHCLK inputs optionally clock the right half of the device. The LHCLK inputs optionally clock the left half of the device. See the Using Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for additional information on these signals.

author: Someone
author_rank: Super Contributor
timestamp: October 01, 2025, 09:13:18 am
content: Quote from: 2X on October 01, 2025, 08:41:55 amSo did you read UG331? what is the confusion?

author: 2X
author_rank: Frequent Contributor
timestamp: October 01, 2025, 09:33:08 am
content: Quote from: Someone on October 01, 2025, 09:13:18 amOn the UG331 (Spartan-3 Generation FPGA User Guide) I read the below but din't help me.The primary clock path is shown with bold lines, with a dedicated clock pad (GCLK) driving a global clock buffer (BUFGMUX) that connects through global routing resources to clock inputs on flip-flops and other clocked elements. The GCLK pads can be used as general-purpose I/O, and include the LHCLK and RHCLK inputs described later. A DCM can be inserted into the path between the clock pad and clock buffer to manipulate the clock, or the DCM can acquire the clock signal from general-purpose resources. The BUFGMUX can multiplex between two clock sources or be used as a simple BUFG clock buffer. The clock buffer can only drive the clock routing resources, which in turn can only drive clock inputs. However, clock inputs on flip-flops can also come from generalpurpose routing, although their use is not recommended due to higher skew.P.S. My knowledge about the FPGAs are very limited.

author: whollender
author_rank: Regular Contributor
timestamp: October 01, 2025, 06:28:10 pm
content: I'm sure they just didn't have enough clock routing resources to get all the global clock inputs to all parts of the chip, so they partitioned it such that some of the 'global' clock inputs could only be routed to one side of the chip.So, if you clock some logic based on one of the LHCLK clock inputs, that logic must be placed in the 'left' side of the chip, but logic clocked from a GCLK input can be placed anywhere.

author: bbreuer
author_rank: Newbie
timestamp: October 04, 2025, 01:30:00 pm
content: Take a look at figure 2-2 in UG331.This was an earlier version of clock regions where each quadrant of the chip is a region. With careful planning, you can have up to 24 clocks throughout the chip with a limit of 8 per quadrant.