Simple C code builds but doesnt work...PIC18F26K20 (XC8 compiler) - Page 1
Forum section: electronics / general

author: ocset
author_rank: Super Contributor
timestamp: June 08, 2017, 08:30:17 pm
content: Hello,The following XC8 C code for PIC18F26K20 Builds successfully but doesn’t work.Please help make it work?All it is supposed to do is output on RC2 what it reads as an input on RB0. (They are both Digital I/O ports)I cannot see why it wont work.The following is the crux of the entire code………..while(1) {if (PORTBbits.RB0 == 0) {PORTCbits.RC2 = 0;}__delay_ms(1);if (PORTBbits.RB0 == 1) {PORTCbits.RC2 = 1;}__delay_ms(1);}…..surely there is nothing wrong with this?Here is the complete code listing……Code:/** File: main.c*///This file is very simple code.//It simply puts out on RC2 what it reads on RB0. (HIGH or LOW)/*Generated Main Source FileFile Name:main.cDescription:* Generation Information :Device : PIC18F26K20The generated drivers are tested against the following:Compiler : XC8 v1.38MPLAB : MPLAB X IDE v3.61*/#include <xc.h>#include <stdint.h>#include <stdlib.h>#define _XTAL_FREQ 16000000// CONFIG1H#pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)// CONFIG2L#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)#pragma config BOREN = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)#pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)// CONFIG2H#pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)// CONFIG3H#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)#pragma config HFOFST = OFF // HFINTOSC Fast Start-up (The system clock is held off until the HFINTOSC is stable.)#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)// CONFIG4L#pragma config STVREN = OFF // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))// CONFIG5L#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)// CONFIG5H#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)// CONFIG6L#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000h-00FFFFh) not write-protected)// CONFIG6H#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)// CONFIG7L#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)// CONFIG7H#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)void main(void){OSCCON = 0x72; // 16MHzOSCTUNE = 0x00;//Set up Special Function RegistersANSEL = 0x00; //Enable all input buffers (not using analog functions)ANSELH = 0x00; //Enable all input buffers (not using analog functions)ADCON0 = 0x00; //ADC disabledCM2CON0 = 0x00; //Comparator 2 disabledCM1CON0 = 0x00; //Comparator 1 disabledCCP2CON = 0x00; //Disable PWM and capture compare modules.CVRCON = 0x00; //Disable internal voltage reference (of comparator))TRISA = 0b00000110; //AJM checkedTRISB = 0b00001111; //AJM checked //RB0 is input.TRISC = 0b00000000; //AJM checked. //RC2 = Output.INTCON = 0x00; //Disable all interruptsINTCON2 = 0x80; //Disable PORTB pullupsSLRCON = 0x00; //All PORTB outputs slow at standard rate.PORTCbits.RC2 = 0; //LEDs OFFwhile(1) {if (PORTBbits.RB0 == 0) {PORTCbits.RC2 = 0;}__delay_ms(1);if (PORTBbits.RB0 == 1) {PORTCbits.RC2 = 1;}__delay_ms(1);}return;}

author: aiq25
author_rank: Regular Contributor
timestamp: June 08, 2017, 09:12:24 pm
content: I'm not that advanced in programming but something that needs adjusting is:"PORTCbits.RC2 = " --> Use LATx instead (this is better practice in general).

author: aiq25
author_rank: Regular Contributor
timestamp: June 08, 2017, 09:15:47 pm
content: Typically I use something like this:Code:// Setup outputs --> RA0TRISAbits.TRISA0 = 0; // RA0 is outputANSELAbits.ANSA0 = 0; // set for digitalLATAbits.LATA0 = 0; // initialize RA0

author: ocset
author_rank: Super Contributor
timestamp: June 09, 2017, 05:26:09 am
content: Thanks, so we should always write to the 'LATCH', and read to the 'PORT'?

author: jaromir
author_rank: Unknown
timestamp: June 09, 2017, 05:35:23 am
content: Quote from: treez on June 09, 2017, 05:26:09 amYes.Your example should look likeCode:while(1) {if (PORTBbits.RB0 == 0) {LATCbits.LATC2 = 0;}__delay_ms(1);if (PORTBbits.RB0 == 1) {LATCbits.LATC2 = 1;}__delay_ms(1);}

author: JPortici
author_rank: Super Contributor
timestamp: June 09, 2017, 06:05:34 am
content: Quote from: treez on June 09, 2017, 05:26:09 amyes. even written in the datasheet.well actually bit manipulation are converted to BCF and BSF instructions so there is no real harm in this case, but it's still bad practice.does it work now?if it doesn't try sampling porta first, i tend to have a lot of problems reading pin states this way, i prefer to sample to ports first (also help with debugging)Code:uint8_t portb_state...portb_state = PORTBif (portb_state & 1) { pressed } else { not pressed }if you single stepped you would see if the pic is getting the correct data from the port.Also, the 26k20 like all modern pics has the ANSELx register to make an input pin digital/analog. so you should also add ANSELBbits.ANSB0 = 0

author: BrianHG
author_rank: Super Contributor
timestamp: June 09, 2017, 06:32:01 am
content: If you are keeping the programmer plugged in, did you release the PIC from reset state?Are running in debug mode?Is the PIC cpu clock truly oscillating?EG, get rid of the IF part & delay and just set and clear PortRC, see if it is going high and low all on it's own.

author: ocset
author_rank: Super Contributor
timestamp: June 11, 2017, 12:44:10 pm
content: Hello,I have now enabled the portb pullup on RB3 too, though please could you check the order in which i setup the special function registers?..I mean i know that ANSEL must be set before TRIS, but what about INTCON etc, should you set that before or after setting TRIS?Code:/** File: main.c*///This file is very simple code.//All it does is mimick the input on pin 18 (RB0) and put it out on pin 10 (RC2))/*Generated Main Source FileFile Name:main.cDescription:* Generation Information :Device : PIC18F26K20The generated drivers are tested against the following:Compiler : XC8 v1.38MPLAB : MPLAB X IDE v3.61*/#include <xc.h>#include <stdint.h>#include <stdlib.h>#define _XTAL_FREQ 16000000// CONFIG1H#pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)// CONFIG2L#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)#pragma config BOREN = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)#pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)// CONFIG2H#pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)// CONFIG3H#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)#pragma config HFOFST = OFF // HFINTOSC Fast Start-up (The system clock is held off until the HFINTOSC is stable.)#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)// CONFIG4L#pragma config STVREN = OFF // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)#pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))// CONFIG5L#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)// CONFIG5H#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)// CONFIG6L#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000h-00FFFFh) not write-protected)// CONFIG6H#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)// CONFIG7L#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)// CONFIG7H#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)void main(void){OSCCON = 0x72; // 16MHzOSCTUNE = 0x00;//Set up Special Function RegistersANSEL = 0x00; //Enable all input buffers (not using analog functions)ANSELH = 0x00; //Enable all input buffers (not using analog functions)ADCON0 = 0x00; //ADC disabledCM2CON0 = 0x00; //Comparator 2 disabledCM1CON0 = 0x00; //Comparator 1 disabledCCP2CON = 0x00; //Disable PWM and capture compare modules.CVRCON = 0x00; //Disable internal voltage reference (of comparator))TRISA = 0b00000110; //AJM checkedTRISB = 0b00001111; //AJM checked //RB0 is input.TRISC = 0b00000000; //AJM checked. //RC2 = Output.WPUB = 0x08;INTCON = 0x00; //Disable all interruptsINTCON2 = 0x00; //Enable PORTB pullups (depends now on WPUB)INTCON3 = 0x00;SLRCON = 0x00; //All PORTB outputs slow at standard rate.LATCbits.LATC2 = 0; //LEDs OFFwhile(1) {if (PORTBbits.RB0 == 0) {LATCbits.LATC2 = 0;}__delay_ms(1);if (PORTBbits.RB0 == 1) {LATCbits.LATC2 = 1;}__delay_ms(1);}return;}

author: StillTrying
author_rank: Super Contributor
timestamp: June 11, 2017, 04:36:57 pm
content: LATCbits.LATC2 = 0; //LEDs OFF...while(1) {I'd put a 200ms LED flash between those two lines. If you don't see the LED flash you know the problem is in the setting up, if you do see the LED flash you'll know the problem is in the while loop's sensing/setting.Don't forget to add a 200ms delay after the flash, in case the while loop immediately turns the LED off!

author: StillTrying
author_rank: Super Contributor
timestamp: June 14, 2017, 09:16:20 pm
content: Well what was it that stopped the LED going on and off.

author: ocset
author_rank: Super Contributor
timestamp: June 24, 2017, 08:19:58 am
content: Thanks, dont know but this did itCode:/** File: main.c*///This file is very simple code.//All it does is mimick the input on pin 18 (RB0) and put it out on pin 10 (RC2))/*Generated Main Source FileFile Name:main.cDescription:* Generation Information :Device : PIC18F26K20The generated drivers are tested against the following:Compiler : XC8 v1.38MPLAB : MPLAB X IDE v3.61*/#include <xc.h>#include <stdint.h>#include <stdlib.h>#define _XTAL_FREQ 16000000// CONFIG1H#pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)// CONFIG2L#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)#pragma config BOREN = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)#pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)// CONFIG2H#pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)// CONFIG3H#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)#pragma config HFOFST = OFF // HFINTOSC Fast Start-up (The system clock is held off until the HFINTOSC is stable.)#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)// CONFIG4L#pragma config STVREN = OFF // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)#pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))// CONFIG5L#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)// CONFIG5H#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)// CONFIG6L#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000h-00FFFFh) not write-protected)// CONFIG6H#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)// CONFIG7L#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)// CONFIG7H#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)void main(void){OSCCON = 0x72; // 16MHzOSCTUNE = 0x00;//Set up Special Function RegistersANSEL = 0x00; //Enable all input buffers (not using analog functions)ANSELH = 0x00; //Enable all input buffers (not using analog functions)ADCON0 = 0x00; //ADC disabledCM2CON0 = 0x00; //Comparator 2 disabledCM1CON0 = 0x00; //Comparator 1 disabledCCP2CON = 0x00; //Disable PWM and capture compare modules.CVRCON = 0x00; //Disable internal voltage reference (of comparator))TRISA = 0b00000110; //AJM checkedTRISB = 0b00001111; //AJM checked //RB0 is input.TRISC = 0b00000000; //AJM checked. //RC2 = Output.WPUB = 0x08;INTCON = 0x00; //Disable all interruptsINTCON2 = 0x00; //Enable PORTB pullups (depends now on WPUB)INTCON3 = 0x00;SLRCON = 0x00; //All PORTB outputs slow at standard rate.LATCbits.LATC2 = 0; //LEDs OFFwhile(1) {if (PORTBbits.RB0 == 0) {LATCbits.LATC2 = 0;}__delay_ms(1);if (PORTBbits.RB0 == 1) {LATCbits.LATC2 = 1;}__delay_ms(1);}return;}

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: June 24, 2017, 08:50:43 pm
content: Quote from: treez on June 24, 2017, 08:19:58 amThat's the identical code to your previous post. Compared to the original code, you:-- Turned LVP OFF- Explicitly cleared INT3- Enabled pullup on RB3- changed PORTC to LATCThough youshouldset PORTC bits using LATC to avoid disturbing other output bits, this should not have affected the bit you were setting. Perhaps having LVP on was preventing the code from running.

author: NorthGuy
author_rank: Super Contributor
timestamp: June 24, 2017, 09:05:23 pm
content: Quote from: Bruce Abbott on June 24, 2017, 08:50:43 pmLVP enables the PGM pin. If the PGM pin is left unconnected, the PIC will reset from time to time randomly. Disabling LVP alleviates this problem.

author: StillTrying
author_rank: Super Contributor
timestamp: June 25, 2017, 02:25:22 pm
content: Quote from: Bruce Abbott on June 24, 2017, 08:50:43 pmBut as you noted that was already done by Reply#7, and still no worky, so it must have beensomething else.

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: June 25, 2017, 05:54:38 pm
content: Quote from: StillTrying on June 25, 2017, 02:25:22 pmI don't see where in reply#7treezsays it is still no worky, and since the 'this did it' code in reply#10 is identical I can only presume that it was already working in reply#7.If it was me, I would have undone the changes one at a time until the fault reappeared, then I would know what caused it. But apparentlytreezdoesn't care...