32 Channel Analog IC Switch Control with STM32F7 SPI - Page 1
Forum section: electronics / general

author: A.Ersoz
author_rank: Regular Contributor
timestamp: September 21, 2018, 03:37:44 pm
content: Hello Guys,On my custom design board, there are a STM32F767ZI microprocessor and a HV2901 Analog Switch IC. My plan is that with controlling HV2901, already generated signal should flow the other components on my board. I have two questions. One of them is defining variables, so how can I fix the errors in this part. The other one is that I define SPI as full duplex master. How can I write codes for receiving data?Here is my code;const uint8_t testdata_out; // Main signal which will flow through ON-switch to other part of the circuitconst uint32_t switch_output={1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; // I try to define which switch should ON. Based on data // sheet, for first switch, DO should 1.uint16_t SW_Out_1; // In CubeMX, there is only option for setting 16-bit data as maximumuint16_t SW_Out_2; // In CubeMX, there is only option for setting 16-bit data as maximumuint32_t SW_Out = (SW_Out_1>>16) | (SW_Out_2<<16); // HV2901 needs 32 bit data length for controlling switch positions, so I merged previous //variables as 32-bit.// Latch or SYNC Pin needs to LOWHAL_GPIO_WritePin(LE_Pin_GPIO_Port, LE_Pin_Pin, GPIO_PIN_RESET);// Write data with SPISW_Out = switch_output<<1 | testdata_out<<31;HAL_SPI_Transmit(&hspi4,(uint8_t *)&SW_Out,32,100);// When data is ready, LATCH will highHAL_GPIO_WritePin(LE_Pin_GPIO_Port, LE_Pin_Pin, GPIO_PIN_SET);

author: A.Ersoz
author_rank: Regular Contributor
timestamp: September 25, 2018, 03:53:58 pm
content: I modified a little bit of my code. But still the first switch is not ON.Variables:uint16_t Switch_Select1st = 0x8000;// I try to define that the first switch should ON. Based on datasheet, for first switch, DO should 1.uint16_t Switch_Select2nd = 0x0000; // Rest of the 16 bit// SPI4 Communication between microprocessor (master) to DAC (slave)HAL_GPIO_WritePin(AnalogSWIC_LE_GPIO_Port, AnalogSWIC_LE_Pin, GPIO_PIN_RESET); // LE Pin set as lowHAL_GPIO_WritePin(AnalogSWIC_CLR_GPIO_Port, AnalogSWIC_CLR_Pin, GPIO_PIN_RESET); // CLR pin set as lowHAL_SPI_Transmit(&hspi6,(uint8_t*)&Switch_Select1st,2,100);HAL_SPI_Transmit(&hspi6,(uint8_t*)&Switch_Select2nd,2,100);HAL_GPIO_WritePin(AnalogSWIC_LE_GPIO_Port, AnalogSWIC_LE_Pin, GPIO_PIN_SET); // LE pins set as highHAL_GPIO_WritePin(AnalogSWIC_CLR_GPIO_Port, AnalogSWIC_CLR_Pin, GPIO_PIN_SET); // CLR pin set as high

author: newbrain
author_rank: Super Contributor
timestamp: September 25, 2018, 09:24:14 pm
content: Quote from: A.Ersoz on September 25, 2018, 03:53:58 pmUse the code quote (the # button) tags, please.In any case, this looks much better than the first attempt!But we still have some problems.The major one is that you are using SPI6, and I assume the configuration is the same as inyour other question.If that's the case, you must have it configured for low polarity and clocking on the second (so, falling) edge in order to use that DAC:Code:hspi6.Init.CLKPolarity = SPI_POLARITY_LOW;hspi6.Init.CLKPhase = SPI_PHASE_2EDGE;This switch, as described in and just above the picture at page 7 in theDS, clocks data into the shift register at the raising edge of the clock.So there's the need to reconfigure the SPI when switching peripherals (or simply use another SPI!).I would advise against doing that through the HAL_SPI_Init(), as that's really shooting a mosquito with a nuclear warhead.You can directly manipulate the registers or use a function provided by the LL library, taking care that all trasmissions have finished; this is not a problem if you are using the blocking functions.According the DS, it would seem that it's not even needed to disable the peripheral.With that out of the way, a couple of other points:Have you studied the DS? On page 7 it is also shown clearly that when you have CLR high, all the switches will be off.You are setting CLR high after every write in your code...The interface is very SPI like, but the shifting happens even with LE high! This will disrupt any data in the switch if you use the same SPI for other tasks and result in many glitches when updating it unless you:1. always keep LE high so as to maintain the latched output configuration, independently from the shift register data.2. onlybriefly pulseit (H->L, L->H)aftershifting in the whole 32 bits needed.This also is hinted in the DS, in the first page:"..., the latch enable bar should be left high until all bits are clocked in."though they suggest this in order to reduce clock feed through noise.

author: A.Ersoz
author_rank: Regular Contributor
timestamp: September 26, 2018, 04:50:32 pm
content: QuoteI reserved in to SPI4 for communication, and I selected transmit only master.Code:// SPI4 Communication between microprocessor (master) to DAC (slave)HAL_GPIO_WritePin(AnalogSWIC_LE_GPIO_Port, AnalogSWIC_LE_Pin, GPIO_PIN_RESET); // LE Pin set as lowHAL_GPIO_WritePin(AnalogSWIC_CLR_GPIO_Port, AnalogSWIC_CLR_Pin, GPIO_PIN_RESET); // CLR pin set as lowHAL_SPI_Transmit(&hspi4,(uint8_t*)&Switch_Select1st,2,100);HAL_Delay(1);HAL_SPI_Transmit(&hspi4,(uint8_t*)&Switch_Select2nd,2,100);I keep LE and CLR pins as low, so I deactivated about shifting high level of the signals.Actually, I didn't understand briefly pulse.Hence, I didn't switch the the first latch yet.

author: newbrain
author_rank: Super Contributor
timestamp: September 26, 2018, 07:38:47 pm
content: Quote from: A.Ersoz on September 26, 2018, 04:50:32 pmGood, so you are now on a separate SPI, I would imagine you've set it up as shown in the datasheet: clock polarity high and second edge matches the picture, but from the description also clock polarity low and first edge should work (only the L to H transitions are important).CLR is fine, it can stay low as you've set it. No need to change it.As for the /LE: the shift register and the output latch are independent.The SR is always active, and will shift its content at every clock tick.The output latch is transparent if /LE is low, so the switches will directly follow the values in the SR.When /LE goes high, the last configuration is frozen in the output latch.My advice, since you were using SPI6 in the code (same as for the DAC), was to do something like:Code:HAL_GPIO_WritePin(AnalogSWIC_LE_GPIO_Port, AnalogSWIC_LE_Pin, GPIO_PIN_SET); // LE Pin set as high (normal condition)HAL_GPIO_WritePin(AnalogSWIC_CLR_GPIO_Port, AnalogSWIC_CLR_Pin, GPIO_PIN_RESET); // CLR pin set as lowHAL_SPI_Transmit(&hspi4,(uint8_t*)&Switch_Select1st,2,100);HAL_SPI_Transmit(&hspi4,(uint8_t*)&Switch_Select2nd,2,100);HAL_GPIO_WritePin(AnalogSWIC_LE_GPIO_Port, AnalogSWIC_LE_Pin, GPIO_PIN_RESET); // Give a brief pulse ( \_/ )HAL_GPIO_WritePin(AnalogSWIC_LE_GPIO_Port, AnalogSWIC_LE_Pin, GPIO_PIN_SET); // to LE in order to latch the SR contentAs suggested in the datasheet. This is OK in any case, and avoid the switch configuration changing while shifting.If the switch is correctly powered (at least +/-40V for the HV side and 3-5.5V for the LV side), connections are correct and signal integrity is decent, I see no reason why it should not work.

author: A.Ersoz
author_rank: Regular Contributor
timestamp: September 26, 2018, 07:55:25 pm
content: QuoteActually, I connected VNN as -5V; VPP as 5V; VDD as 5V.I got around 1V constant signal from DOUT, but I couldn't see clock signal. Maybe, I make a mistake setting parameters of SPI4?I set in CubeMX SPI4 Configuration;Transmit Only MasterNSS is disableMotorola16 bitsMSB8 (Prescaler)13.5 Mbit/sLow2 Edge

author: newbrain
author_rank: Super Contributor
timestamp: September 27, 2018, 07:17:12 am
content: Quote from: A.Ersoz on September 26, 2018, 07:55:25 pmFirst of all a disclaimer: my advice is worth exactly what you pay for, I try to be correct and check my posts, but I might be and have been wrong.The datasheet for that part provides quite scant information.But from my reading, the operating conditions for that chip call for at least VPP= +40V and VNN= -40V.There is no characterization for values outside that range.Will it work with +/-5V?I can't say, as the DS does not say, but it's definitely out of the recommended operating conditions.My default answer would then be "no".DOUT at 1V is not good. It should be much closer to either GND or VDD, unless it's heavily loaded (it should not be).Why second edge? With low clock polarity it should be first edge:(Or dually, why low clock polarity? With second edge it should be high.)Code:2. Serial data is clocked in on the L to H transition of the CLK.Pardon my bluntness, but I start to have the feeling that you're trying to run a marathon with a 2000m trainingIs this a hobby project, a study assignment, a task for your job?