4-layer stackup "controversy" - Page 1
Forum section: electronics / projects

author: jrs45
author_rank: Regular Contributor
timestamp: February 01, 2022, 03:41:11 pm
content: I've been digging through his videos, and Hartley generally recommends GND/Signal/Signal/GND, which I can understand, because each signal layer has a GND adjacent to it, and the outer layers act as a sort of shield. But I see a few issues that I haven't seen addressed satisfactorily:1. The top GND plane is interrupted by the component pads, to a pretty substantial degree. With fine pitch components, it's difficult to ensure the plane's integrity, and many slots and such will result. This is avoided when using an inner plane for GND.2. The top GND plane is also interrupted by vias, which are all over the place, since every signal now needs its own via. Though it's easier to space these out a bit to preserve a mostly solid ground plane. Still, it's a ton of vias, all making stubs to the bottom layer.3. For any designs with high current, using inner layers will create more heat, though I suppose this only means we need to expand the trace width sufficiently to compensate (is there a % guideline? I guess there are just tables for inside vs. outside traces)For the above reasons, I'm still thinking that signal/gnd/gnd (maybe a few signals)/signal is the best approach, while ensuring the 3rd layer gnd is unbroken under any (high speed) bottom layer traces. It's also a little easier during development to bodge, but then again hollowing out a via to disconnect a trace is pretty easy.But I could be convinced otherwise! Please do so! (I'm working on a new board that should only need ~25MHz clocks, but maybe with sharp edges, and I want to do it right!)

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: February 01, 2022, 04:19:58 pm
content: The frequency at which these things are a concern is in the dozens of GHz. I've seen people lose their minds over a few mils of gap around pins of a DC-DC switcher... Um, if that had any impact, no switching power supply would ever have worked. People get concerned over things that are real, but insignificant or even unmeasurable.The idea of putting the ground planes on the outside is a part of HDI, but HDI also includes more than 4 layers and uses via-in-pad and blind vias.Also, whenever there is a "controversy" like this, where two people are arguing that two different approaches are "correct", usually that's because both approaches work. Because few circuits really run at those high GHz frequencies where you'd actually see a difference.High current is a concern, but what current?I always look at things in historic perspective. People read things about shielding and ground returns and trace inductance and seem to think these are vital problems. If they were, no Amiga or Atari ST would have worked back in the day. Big sloppy boards, power routed as traces, no terminations, swiss cheese power and ground planes. So what?At 25MHz you really REALLY need to be extra sloppy and careless for things to fail.I feel you are trying to apply exotic approaches to a simple problem.How will you mod-wire a PCB with all traces inside?

author: nctnico
author_rank: Super Contributor
timestamp: February 01, 2022, 04:22:25 pm
content: But it doesn't hurt to put a 33 Ohm resistor in series with the output that produces 25MHz (if it is a square wave) to soften the edges. Put that resistor close to the source.

author: vad
author_rank: Frequent Contributor
timestamp: February 01, 2022, 04:43:50 pm
content: GND-SIG-SIG-GND stack up does not make sense to me either for the same reason that you have mentioned - component pads and signal and power routing on the top layer will interrupt ground plane. So the top layer must be SIG, and the layer below it must be GND. If your application requires shielding (e.g. sensitive RF circuit), you would be using external shielding anyway. For non-sensitive circuits you do not need shielding. Coupling to a solid GND inner plane is sufficient for controlling EMI and signal integrity.If I had to stick to 4 layer stackup for medium speed digital designs, I would go for SIG-GND-PWR-GND. If keeping all signal traces on top layer is infeasible and 6 layer is out of budget, then I would go for SIG-GND-PWR-SIG/GND (filling bottom signal layer with Gnd copper pour).PS. Clock speed does not matter for EMI and signal integrity. What matters is signal rise time. If the clock is 25MHz, but signal rise time is 1 nanosecond, then you would be in GHz territory, despite of relatively slow clock.

author: Siwastaja
author_rank: Super Contributor
timestamp: February 01, 2022, 04:45:22 pm
content: Quote from: jrs45 on February 01, 2022, 03:41:11 pmThis is a pretty obvious solution which applies to:* through hole components because the cost of going to any layer is the same,* long traces which may benefit from shielding.But your observations are spot on. If you have two SMD components on top, and are going to make a 1mm long track between them, by moving into mid layers through vias is only going to make things worse, there are no benefits. This was also discussed in the thread discussing confusing space technology regulations.This is the danger in rules of thumbs: they always have some scope in which they apply, and this scope needs to be well defined.If you have long traces which are either high-speed, or sensitive analog measurements, then burying them in mid layers obviously offers some shielding: stripline being better than microstrip. This being said, if you look at actual high-speed or precision devices, they are full of microstrips anyway.Finally, GND - signal - signal - GND isn't very good because the two signal layers are not shielded from each other. If you really go that way, why not make it GND - SIG - GND - GND - SIG - GND. Or one of the GNDs can be well bypassed power plane, too.IMHO, #1 step is always removing excess. Miniaturization plays in your favor. Think about component placement to minimize routing. Very short tracks are the best tracks. You can't bury components anyway, so if the tracks are of the same order of magnitude of length than the components, the design is already pretty much optimum. If this isn't enough, external shielding becomes a thing; a PCB reference plane can't shield the components and their legs, anyway.

author: free_electron
author_rank: Super Contributor
timestamp: February 01, 2022, 04:51:07 pm
content: there is only one one true statement when it comes to all these things : "it depends"a given layer stack may work in one case and be total shit in another case. That's why there is no 'universal layer stack' that works in all cases.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 01, 2022, 05:36:35 pm
content: Quote from: vad on February 01, 2022, 04:43:50 pmYep. Sure the "right" answer would be "it depends", but the point above is major. If you stack up like this, your top (and bottom if it also has components) layers will be planes cut by footprints, tracks and clearances. Often not worth much.Except in very specific cases, the most usual is SIG-POWER-GND-SIG (the POWER and GND layers can of course be swapped, again it depends).The only real question IMO is whether it's worth it to add ground planes on the top and bottom layers (which are usually signal layers). Some people do, some don't. But no dedicated ground and power planes? That sounds crazy. (If someone comes up with a good example of when it's useful, please consider I said "very specific cases".)And I didn't think there was any real controversy here. But in the age of clickbaity videos, what do we know... =)

author: harerod
author_rank: Frequent Contributor
timestamp: February 01, 2022, 05:53:59 pm
content: Quote from: free_electron on February 01, 2022, 04:51:07 pmAnd thus comes a point where one has to start understanding EMC. I have quite a few books on that topic in my shelf. For starters I would recommend working through Howard Johnson's "Handbook of Black Magic" ISBN-13 ‏ 978-0133957242. A really nice read. My copy is full of notes, where I calculated intermediate steps for his examples. The only drawback is the usage of statute units. If required, you can always move on to Henry Ott.As far as actual implementation goes: I haven't had any problems passing EMC testing with four layers SIG-GND-POW-SIG in a long time. It is the overall design that counts. On the other hand, I only do simple industrial or medical stuff. Have a look at my website, if you like.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: February 01, 2022, 05:57:21 pm
content: Sure, it does depend on the frequencies of interest. I've used lots of ADCMP572 comparators only with HDI-type layouts because that's the only way they'll work at rated frequency. And also usually with *local* structures with external ground planes because with blind vias the signals go right into the PCB at the pin.The whole philosophy of HDI is to minimize inductance and intrusions, because many parts have large ground pads and ground pins, so by putting the ground planes on the outside you maximize plane area. But you also use via-in-pad and blind vias to minimize intrusions elsewhere.in other words the GND-layer-layer-GND thing is just one aspect of the whole HDI approach, and it isn't useful if you don't go all the way with the rest of HDI.I think in the context of OP's 25MHz question, it is over-engineering IMO."(I'm working on a new board that should only need ~25MHz clocks, but maybe with sharp edges, and I want to do it right!)"Fine, then put damping resistors. Solved! The Commodore 64 used 33R resistors on the data lines for its RAM expansion. It's not a big problem.Now OTOH if you *want* to make a cool board where you just see components and no traces... well that *is* cool but it's not necessary for things to work.Anyhow, if you want good info on HDI, go herehttps://resources.altium.com/experts/happy-holdencheck this outhttps://www.eknet.no/wp-content/uploads/2019/05/HDI-Presentation.pdfBut if all you're concerned about is the ringing after rising and falling edges, well, put damping resistors.

author: jrs45
author_rank: Regular Contributor
timestamp: February 01, 2022, 06:03:56 pm
content: Thanks everyone for the thoughtful advice and discussion.One followup, inspired by one of the responses: Is it notably better for the power plane to be ground + power traces, or better to just have a vcc plane? Is a vcc plane, say on the 3rd layer, as effective as a return reference as gnd would be for traces on the bottom?So: sig-gnd-pow-sig vs sig-gnd-gnd(+some traces)-sigI understand it's all a fine point and probably doesn't matter much at these frequencies, but I'd like to grok all this for future designs.

author: Siwastaja
author_rank: Super Contributor
timestamp: February 01, 2022, 06:11:47 pm
content: If you think about the symmetry that goes into CMOS logic, and you have a bypass cap at every IC, coupling the planes at every source and destination, then there should be absolutely no difference which one is the reference plane.If you have cuts in the Vcc plane because of it consisting of multiple different voltage regions, then bypassing the voltage planes to the ground planes is important at every crossing, I think.

author: free_electron
author_rank: Super Contributor
timestamp: February 01, 2022, 07:10:18 pm
content: Quote from: Siwastaja on February 01, 2022, 06:11:47 pmcorrect. hence the usage of a ground via adjacent to a signal via when layer hopping.there is other things to consider as wellpeople often confuse signal integrity and emc. they are related but different.example : a large board with an active portion of electronics in one corner. the rest of the board is bare. ( 19 inch rack board . needs to be specific size ). to save etching they flooded the empty space with power and ground planes.During emc testing they find out this thing radiates like crazy. the planes act as a dipole antenna !The stackup was a 6 layer . The flooded portion was ground (top), power, ground, power, ground, power.solution attempt 1 : stitch vias around the edge of the board to short the ground planes and short the power planesIt still radiated ! topside of the board was flooded with ground, bottom side with power. it is still a dipole !So they altered the flooding so both top and bottom were ground.This was a lot better, but directional measuring still showed a spike in the spectrum when pointing side-on. DC does not radiate. AC does.So they shunted the AC by putting small 10nf caps close to the edge of the board space 5cm apart. that shunted any RF between power and ground.problem solved. (the actual root cause was found later ... the master clock generator was in resonance with the size of the copper pours. the whole thing resonated. Be wary of large copper pours that go nowhere.. replace with checkerboard pattern that is unconnected.

author: free_electron
author_rank: Super Contributor
timestamp: February 01, 2022, 07:24:59 pm
content: Quote from: harerod on February 01, 2022, 05:53:59 pmHoward Johnson : Handbook of Black magicLee Ritchey : Right the first timehttps://speedingedge.com/product/volume-1-right-the-first-time-a-practical-handbook-for-high-speed-pcb-and-system-design/<-highly recommended to get the books and digital library ! for 100$ you get more than any other book set will ever give you.Eric BogatinMark Montrose highly recommend his class at UCSC.https://www.ucsc-extension.edu/courses/printed-circuit-board-design-for-signal-integrity-and-emc-compliance/learnemc.com