Soft switch latch help - Page 1
Forum section: electronics / projects

author: Evilmachinist
author_rank: Newbie
timestamp: December 12, 2019, 04:39:03 am
content: I need the soft switch latch circuit for a machine I’m building.The circuit diagram on Dave’s video has one of the 3904’s is upside down.I realize that this might not be a big deal, but to someone who’s struggling to begin with it is devastating!Could someone clarify this circuit for me?It needs to run on 12v dc and switch a simple relay on an off using a normally open momentary switch.Also, what would be the proper P channel MOSFET part number to use?

author: Peabody
author_rank: Super Contributor
timestamp: December 12, 2019, 04:49:17 pm
content: I don't know what you mean by upside down. Both transistors look correct to me. What looks wrong to you?

author: Peabody
author_rank: Super Contributor
timestamp: December 13, 2019, 03:53:26 pm
content: Here's a circuit that's even simpler than Dave's, but works essentially the same way. And there's an explanation of how it works.https://www.edn.com/design/power-management/4427218/Latching-power-switch-uses-momentary-pushbuttonThe choice of mosfet depends on how much current your relay coil draws. Perhaps you can provide information on your relay.[In this edn circuit, I don't understand why R3 is needed. Can anyone explain?]

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 13, 2019, 04:15:55 pm
content: Quote from: Peabody on December 12, 2019, 04:49:17 pmSame here.Quote from: Peabody on December 13, 2019, 03:53:26 pmWhat I can think of: when the circuit is in the "latched" state, Q1 conducts, and C1 charges. The moment you will push the button to turn it off, if R3 were just a short, C1 would immediately (ie. very quickly) discharge through the pushbutton and Q1, and Q2 may never get a chance to turn off.

author: Peabody
author_rank: Super Contributor
timestamp: December 13, 2019, 06:21:15 pm
content: Quote from: SiliconWizard on December 13, 2019, 04:15:55 pmYes, I see that now. I think that's the explanation.In the comments over at edn, there are several reports that when power is applied, the latch's initial state is unpredictable. Specifically, it may come up with the power turned On, which might not be a good thing. The only explanation I can come up with is that starting with everything discharged, when power comes up, the mosfet gate voltage lags a little because of gate capacitance, and the mosfet may turn on enough to turn on the NPN. Does that make any sense? Is there another explanation? Well, if I'm right about that, it might be prevented by adding a very small capacitor between the source and the gate to bring the gate up to +Vs more quickly than R1+R3 can. Another way I think of it is the little cap acts like a charge pump cap acts - whatever its charge state, if you change the voltage at its bottom, the voltage at its top instantly changes by the same amount. Depending on the mosfet, I suspect the cap could be very small, not big enough to materially interfere with the 330nF cap. What do you think?

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 13, 2019, 07:46:54 pm
content: The added cap will help counter-act the gate charge, but "very small" will largely depend on the gate charge of the PMOS AND on the output load. You may need pretty "large" values (significantly greater than the rated input capacitance). You have to consider the transient state at power-on... (The PS voltage rising from 0V to its end value at a certain rate; you can't just consider the circuit as though +Vs was a constant and all you had to worry about was all the capacitors charging - including parasitic ones.)Without this cap, this circuit has every chance to start with the "on" state at power-on (except with a PMOS with a VERY low gate charge - which will basically mean usually a pretty low-power one), especially at very light loads.Attached is an LTSpice sim that you can play with. The default rise time for voltage sources in LTSpice when using the "startup" option is 20µs. See how that goes...

author: Peabody
author_rank: Super Contributor
timestamp: December 13, 2019, 10:10:34 pm
content: I just meant that I suspect the capacitance will be small in comparison to the 330nF. If that's the case, then the original circuit would still work normally, but would just always power up in the Off state. The added capacitance does increase the effective gate capacitance as seen by the 330 when you press the button, so if you need to add a large capacitance at the gate to make sure it powers up Off, then the values of some of the other parts might need to be changed. I just thought that if the power-on state is unpredicatable, then it's probably not all that far away from working as it should. But as you say, that depends on the mosfet, etc.

author: hugo
author_rank: Regular Contributor
timestamp: December 14, 2019, 01:13:18 am
content: Here's another circuit that's even simpler than Dave's:http://danyk.cz/zap-vyp_en.html

author: Peabody
author_rank: Super Contributor
timestamp: December 14, 2019, 03:25:54 pm
content: Quote from: hugo on December 14, 2019, 01:13:18 amThat appears to be the low-side version of the edn circuit. However, if the edn circuit needs R1 and R3, then this circuit would have a problem when trying to switch off since there's a low impedance path to V+ through the PNP which would immediately charge the capacitor without necessarily shutting down the mosfet. That would mean it needs another resistor which is the equivalent of R3 in the edn circuit.But he obviously tested this and it works, so maybe the 1M base resistor limits current through the PNP enough that it still works. If that's the case, then the same change could be made to the edn circuit, eliminating R3 there. But if the PNP functions enough as a resistor to make the power-off function work, then the gate voltage when power is On would not be V+. You would have a divider situation with the pull-down resistor, which might leave the mosfet not fully turned on. I guess I kinda like having the extra resistor and a lower value base resistor as shown in Figure 2 of the edn page.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 14, 2019, 04:18:05 pm
content: Note that Dave's version potentially suffers from the same problem: being ON after power-on.In some cases, that may actually be the required behavior! But if you want it to be OFF right after power-on, that would require some tweaking as well.

author: Zero999
author_rank: Super Contributor
timestamp: December 15, 2019, 12:11:05 am
content: Here's my version:It's also possible to add a time delay and bootstrap the whole circuit so it can be connected in series with the load. Checkout the thread linked below:https://www.eevblog.com/forum/projects/onoff-switch-with-timer/

author: Peabody
author_rank: Super Contributor
timestamp: December 15, 2019, 04:38:38 am
content: That's pretty slick, Zero999. In your circuit the cap operates through the NPN base instead of the mosfet gate. And you've reduced the resistor count down to three. Maybe Dave should do a followup video showing the later further simplifications of his "world's simplest" toggle switch design.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 15, 2019, 06:54:23 pm
content: Quote from: Zero999 on December 15, 2019, 12:11:05 amIt's elegant, but I can see a small issue with this design for the ON to OFF transition.When the circuit is on the ON state, we can consider the capacitor discharged. The moment the button is pressed, the NPN transistor will thus switch off, which will in turn make the PMOS switch off. So far so good. The less good part is that while the button is still pressed, the capacitor is still connected to the NPN's base and will start charging through the two resistors in series on the left, up to the threshold voltage of the NPN, which will then switch on again, making the PMOS in turn switch on again!The whole thing to consider here is the circuit formed by all 3 resistors, the capacitor AND the load! The higher the input voltage, the faster the cap will get to the threshold. Conversely, the higher the load (in terms of current), the slower. There's a whole range of conditions that can make this circuit thus turn ON again by itself while the user presses the button. With light loads, it won't take a very long press either, but a pretty typical one.Of course one solution would be to increase the capacitance, but it may make it in turn pretty hard to get it to switch ON if you don't wait long enough before cycles.So yes, anyway, unless I missed something (which can always happen), this circuit can't handle "long" button presses in general, and the fact that the max press time depends on the input voltage and the load can be a bit annoying.What do you think?

author: Zero999
author_rank: Super Contributor
timestamp: December 15, 2019, 09:10:31 pm
content: Quote from: Peabody on December 15, 2019, 04:38:38 amQuote from: SiliconWizard on December 15, 2019, 06:54:23 pmI agree. It's not a good circuit. It's very sensitive to changes in supply voltage and the base current is too high, when the switched is pushed to turn it on.I think the low side circuitposted by hugois better and could easily be converted to high side, by swapping the PNP for NPN and N-channel for P-channel.

author: Zero999
author_rank: Super Contributor
timestamp: December 15, 2019, 11:06:52 pm
content: Here's the circuit posted by hugo, changed to high side. One thing to note about this and the circuit I posted is it won't work without a decent minimum load, since the load has to have a low enough impedance to charge C1, without turning on Q1.

author: Peabody
author_rank: Super Contributor
timestamp: December 16, 2019, 04:03:26 am
content: Quote from: Zero999 on December 15, 2019, 11:06:52 pmAs I commented about the hugo circuit when he posted it, I'm still puzzled by how the On to Off transition works. If the bipolar transistor is fully saturated, then pressing the button will simply dump the capacitor without turning off the mosfet. So the 1M base resistor must limit the collector current enough that the transistor acts like a significant resistor, and the capacitor can then switch the gate off when the button is pressed. But if that's the case, then when the mosfet is On, the gate is in the middle of a divider when it's supposed to be at the rail. The link hugo posted has a video showing that circuit working, so I guess it does, but I wonder how well it supplies power to the load with the gate being at a middling voltage. Of course I may be misinterpreting how the hugo circuit works.That video also shows the power oscillating if the button is held down.I guess I still like the edn circuit even though it has one more resistor.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 16, 2019, 02:40:07 pm
content: True challenge now: designing the simplest possible circuit that: (I think none of the above completely fullfills all of these - I'd say most actually fail most of these)1. Works properly regardless of the output load;2. Toggles the switch state when pressing the button, with the following requirements: minimal button press time a few ms (say 10 ms, no need to be accurate, just to avoid spurious toggling), no maximal press time (should not oscillate or toggle back if we keep pressing the button indefinitely);3. Leaks only minimal current in the OFF state in *any* condition;4. Works for supply voltages as low as 1V;5. Has a definite power-on state (either ON or OFF).

author: Zero999
author_rank: Super Contributor
timestamp: December 16, 2019, 07:14:33 pm
content: That's a pretty strict list of requirements there. I don't see why it needs to work down to 1V and if it's part of another circuit, then I don't see why designing it to accommodate a known load current is an issue.I'd probably not bother with these simple circuits and go with a flip-flop IC such as the 74HC74 or similar.

author: Peabody
author_rank: Super Contributor
timestamp: December 17, 2019, 07:41:04 pm
content: Here's the answer. Only 19 cents each:https://www.ebay.com/itm/352483795711

author: not1xor1
author_rank: Frequent Contributor
timestamp: December 19, 2019, 05:21:19 pm
content: Here are a couple of other circuits (tested just in LTSPICE)The CMOS version require less components, probably is more reliable (tested within 1-500 ms range of button on-time) and might drive directly small loads. The simulation requires the CD4000_v.lib.Here is an NMOS + PMOS version. The component values depend on the PMOS gate charge and probably require various adjustments in the real world.Anybody willing to experiment?