:: JFET gain?? - Page 1
Forum section: electronics / beginners

author: 3roomlab
author_rank: Frequent Contributor
timestamp: March 05, 2017, 10:10:33 am
content: i just stumbled on this videoas it states, JFET gain = Gm x Rdif i use BF862, with a gain intention of x31 (and gm = 45mS), that would mean i must have Rd = 31/0.045 = 702R.then by substituting in this 702R into LTspice,i would then discover that, there is a sweet spot Rs (about 7.5R) and a sweet spot voltage supply (between 17.5-18v) i must have to get a x31 gain. and then the damping capacitor for Rs helps improve gain over bandwidth (esp LF).i am curious to know, is my thought process going about this done correctly? esp getting Rd first due to the intended gain?(again this video reminds me about GK's marvelous LNAhttps://www.eevblog.com/forum/projects/low-noise-amplifier/?all)so onward to next part, by stitching 2 (x31) together, i get roughtly a x1000 gain LNA, can i suppose this way derived from the Rd/mS is a "sane" design method for a beginner?

author: Kleinstein
author_rank: Super Contributor
timestamp: March 05, 2017, 10:34:11 am
content: Using just a JFET amplifier without a feedback to stabilize the gain is not very common any more. One reason it that the trans conductance of JFETs depends on the current. Also the JFET parameters have quite a scattering - so you might need individual adjustments. With feedback, like in amplifier of GK, the gain is usually set by the ratio of resistors instead - much like in OP circuits.For the BF862 the typical gm is 45 mS at 0 gate voltage and a correspondingly high current in the 10-25 mA range. However this is not a very practical operating point and it would scatter quite a lot between samples. A more practical condition would be something like a 2 mA current and thus a lower gm of maybe 10-20 mS. To get such a more predictable working condition is purpose the the source resistor. The source resistor also sets the DC amplification to a more predictable value, as this includes a kind of DC feedback. AC gain is still high (and less predictable) due to the parallel cap.

author: Zero999
author_rank: Super Contributor
timestamp: March 05, 2017, 11:18:25 am
content: What are your over all requirements? Power supply voltage? Bandwidth? Output voltage swing? Input/output impedance?Why can't you use a JFET op-amp such as the TL072?How about a BJT amplifier? If the input impedance needs to be high then there are tricks such as bootstrapping to increase the input impedance, or you could use a low gain JFET amplifier for the input, followed by a higher gain BJT amplifier.JFETs have poor transconductance compared to BJTs, so are normally used for low gain stages, with a high input impedance. You could use a JFET amplifier with a gain of 3.1. At low gains, say <5, and no RSbypass capacitor, the gain can be approximated: AV= RD/RS. The same formula is true for a BJT amplifier: AV= RC/RE

author: 3roomlab
author_rank: Frequent Contributor
timestamp: March 05, 2017, 01:40:13 pm
content: Quote from: Hero999 on March 05, 2017, 11:18:25 amyes i did just picked up some understanding of Rd x gm from youtube.im trying to understand if it is possible to just use purely "x" stages of JFET (x31.6 x31.6 gain = x1000) to create an op-amp-less ULNA, which may work like GK's version. but in my case, i have terrible understanding of JFET design, so picking up bits n pieces from youtube and looking at hints of how others build theirs and hopefully gain some tips from JFET experts here.i have watched another of youtuber OFFSETVOLT's vids. much juicy bits in this 1. especially the part about "normalizing" the "gm" spread at the expense of gain.so by fiddling with R2 / R13 (see pic), i managed to get x1000 gain. playing with supply voltage seems to show that i can use the supply voltage like a gain adjustment.what im not sure is1) will the x31.6 gain completely transfer this 5.7nV self noise into (5.7 x 31.6)nV at the input of 2nd stage? which means if the JFET noise is 10nV, the final output will have 10uV noise no matter what?2) will the thermal noise of R1 be also amplified, if so, should i assume using all low value resistors = lower noise advantage?

author: Kleinstein
author_rank: Super Contributor
timestamp: March 05, 2017, 02:05:30 pm
content: The noise voltage of R1 will only be effective at low frequencies, mainly below the cross over frequency for the input RC coupling. Of cause it will be amplified. A smaller value for R1 does not really help - by it's own it will even increase the noise. Only the than larger needed coupling capacitor is really helping to reduce the noise. For the lowest noise one should have a large resistor to ground and a low lower frequency limit in the initial AC coupling and use later stages to set the low frequency limit of the amplifier.R13 and R2 also add to the noise and these should be small in a design with super low noise.There is not much sense to have two high pass filter stages in between the amplifiers - especially not with a frequency limit lower than the input RC. For lowest noise it should be the opposite way around: R1*C1 should be larger by something like a factor of 3 to 10 than the next AC coupling stage. In addition to less noise from R1, one also filters the low frequency noise of the input stage.The main noise contribution will be the first input stage, noise of later stage is usually less important as is is compared to the already amplified noise from the input stage. No matter what you add after it one can not reduce the noise density of the input stage. Later stages can only add to that, though usually not much if the design is good. Only a reduction of the bandwidth is possible to reduce the overall noise.

author: 3roomlab
author_rank: Frequent Contributor
timestamp: March 05, 2017, 11:25:00 pm
content: in this next simulation, i increase the Id of the JFET. smaller R2/R13, higher Id = lower noise i assumethis seem to suggest lower Vds = promote higher mS per mA current, because the simulation is able to produce similar gain with much lower Rd. did i deduce/understand this correctly?for some strange reason, without the double highpass, the signal from stage 1 doesnt get into the gate of the 2nd JFET, so im not sure what is wrongif assuming 1nV creates exactly 31.6nV in stage 1 (Vds = approx 1v), with a Id of 9mA (Rd = 450R), the mS = 31.6/450 ~ 70mS (see pic Vdc 1v) ? does this seem legit? it is so much more than the typical suggested in the pdf. or otherwise, the simulation is increasingly incorrect as Vds approaches zero?for those interested in simulatingBF862 to be inserted into "standard.jft" inside "C:\Program Files\LTC\LTspiceIV\lib\cmp" (option : abs V/A tol = 1e-13)* .model BF862-L1 NJF(Beta=.0478 Betatce=-.5Rd=.8 Rs=7.5 Lambda=.0373 Vto=-.57093 Vtotc=-.002Is=424.60E-12 Isr=2.995p N=1 Nr=2 Xti=3 Alpha=-.001Vk=59.97 Cgd=7.4002E-12 M=.6015 Pb=.5 Fc=.5Cgs=8.2890E-12 Kf=87.5E-18 Af=1.2)