Logic level translation with resistor network? - Page 1
Forum section: electronics / projects

author: thinkfat
author_rank: Unknown
timestamp: January 03, 2021, 11:15:38 am
content: Hi,I'm working on a small breakout board for U-Blox LEA-M8 GNSS receivers, you can find the current state on github:https://github.com/thinkfat/ublox-breakout.The module is powered from 5V, with an on-board LDO to have a 3.3V power supply for the LEA-M8.One of its features is a buffered 1PPS output that can drive a 50 Ohm load with sufficient power to bridge a meter or so with coax cable.I'm using a 74HCT2G125 buffer, reason being that I want to maximize the output level of the 1PPS signal, so I'm powering the buffer from the 5V supply.While this works, the rise time of the 1PPS signal is not great. The buffer has an output rise time of typically 6ns, while I'd be comfortable with maybe 2-3ns max. A suitable replacement would be a 74AHCT2G125, however I want all essential parts be available in the JLCPCB SMT catalog.A replacement suggested to me is the NC7SZ125, from the ONsemi TinyLogic family. These gates are really fast and if I use them in SC-70 footprint, I have enough space for two buffers in parallel. However, if I supply the buffer with 5V, the input levels are not compatible with the 3.3V logic level of the LEA timepulse output. Someone suggested the attached circuit as a means to lift the logic levels a bit. But I'm not really happy with it. For one, while R1/R2 lift the signal level sufficiently, they also reduce the voltage swing and so the signal only marginally passes the required low and high levels (1.5V and 3.5V). Second, the input capacitance of the gate (modeled with C1) forms a low-pass filter with R1 and R2 and causes not only an additional propagation delay in the 10ns range, the signal will pass the input threshold levels much more slowly and likely cause jitter.So, I'm a bit stuck here. If anyone has a suggestion, I'll gladly consider it, provided it doesn't introduce additional BOM items outside of the JLCPCB SMT catalog.

author: Peabody
author_rank: Super Contributor
timestamp: January 03, 2021, 04:31:16 pm
content: If V2 could bring the line low, with no series resistor, would R1 on its own pull it back up fast enough? I'm thinking of replacing R2 with an NPN transistor. The base would be connected to the 3.3V rail through a resistor, the collector would be connected to the A1 input, and the emitter connected directly to V2. That would be non-inverting, and would convert V2 to an open collector output, but with no gain. When V2 goes high, the transistor shuts off, and R1 pulls the A1 input back high. I don't know what this would look like in simulation.If V2 is 5V tolerant, you could just replace R2 with a diode. But that won't work if it has the typical protection diode to its Vcc.

author: thinkfat
author_rank: Unknown
timestamp: January 03, 2021, 06:04:38 pm
content: The time pulse output is not 5V tolerant, also open collector would be rather slow. I rather have fast rise time at the buffer input...

author: Peabody
author_rank: Super Contributor
timestamp: January 03, 2021, 07:15:33 pm
content: Well then if you can't find a part in the JLC catalog to serve as a pre-buffer, maybe you could construct a totem-pole output with two transistors - an NPN on the high side and a PNP on the low side, both driven by the time pulse output. That would get you to within one diode drop of the rails. Or if the NC7SZ125 comes in an inverting version, you could switch the transistors and get full rail-to-rail swing.But what about just powering the NC7SZ125 through a Schottky diode, bringing its Vcc down to 4.7V? Then 3.3V would be high enough to drive its input.

author: thinkfat
author_rank: Unknown
timestamp: January 16, 2021, 10:37:54 am
content: Quick update - I decided to go with the resistor network method and got a few boards made. The output rise time is really pretty fast, I get a 10-90 time for a 0-5V swing of < 800ps, into a 50 Ohm terminated coax. That's not bad!I also found that adding a small capacitor (1nF) in parallel to R2 effectively eliminates the slow rise time at the gate input.