Modelling Inrush Limiting Power Switch - Page 1
Forum section: electronics / projects

author: dazz1
author_rank: Frequent Contributor
timestamp: July 03, 2019, 10:11:35 am
content: HiI have a battery application driving a DC-DC SMPS. 13VDC in, 5VDC out. Output current = 10A.The battery has current protection that causes the battery to trip with 75Amps >1msec.The aim is to reduce the in-rush current to <30A and also act as a power switch.I need a highly efficient current limiter and power switch. Relays, PTCs, in-line resistors are all unsuitable. I have looked for integrated device solutions but none found are suitable. I need a discrete PMOS based solution.I have read and applied designs from the often referenced Application notes AND9093 and AN1542.I have used LTSpice to model the circuit. Both the battery and the SMPS are modeled with parameters that are close to actual.The Attached is the distilled circuit diagram. It is intentionally missing power switch controls and other components in the application notes.The exception is R5 and R6 which have no effect. I don't have a good model of the MOSFET. I intend using a SQD40031EL device.The three traces on the simulation are:Vn001 = battery voltage. The battery model includes internal resistance.Vn002 = output voltage across the SMPSId(M1) = load current.The problem is that the simulation shows a massive current spike at power on. I don't know if the spike is real or a side effect of the simulation.The spike is still there if I include a cap between the S and G.I have a feeling that it is a combination of real and modelling error.I don't really want to build and test this circuit. If the model is half right, the battery will trip and the MOSFET will not survive.Any suggestions on how to improve the confidence/quality of the model?Dazz

author: dazz1
author_rank: Frequent Contributor
timestamp: July 03, 2019, 07:03:20 pm
content: HiThere is one option I haven't looked at before.A latching relay in parallel with a low value resistor could suppress the in-rush current.I would need a 2nd latching relay in series to provide a power switch function.Dazz

author: capt bullshot
author_rank: Super Contributor
timestamp: July 03, 2019, 07:12:34 pm
content: That circuit won't work, don't need a simulation to see ...You've got C2 connected from drain to gate, at the moment you apply V1 and C3 is discharged, C2 will fully turn on the MOSFET - that's where the inrush current results from.Try connecting C2 from gate to source, that should get you further, but take precautions to quick discharge C2 when V1 is disconnected (a reverse diode across R1 might do).

author: capt bullshot
author_rank: Super Contributor
timestamp: July 03, 2019, 07:20:39 pm
content: Took a quick peek into AND9093 - the circuits from fig. 5 and fig. 7 work if you have the proper starting conditions, and then turn on the EN signal. They won't work if you turn them on by connecting the source (VIN) to the circuit, regardless of EN state. Otherwise, connecting C2 from drain to gate works as a miller integrator - quite a simple and effective way indeed.For this kind of circuit (limiting the inrush current when the battery is connected by other means), you should look up some hot-plug controllers (e.g. by LT / now ADI) and adapt their working principles.

author: capt bullshot
author_rank: Super Contributor
timestamp: July 03, 2019, 07:26:32 pm
content: Have a look at fig. 6, AN1542, there's a way to provide a proper start condition to the miller-integrator - take care to get C2 (refering to your circuit) charged before the MOSFET starts to turn on - that tricky part around Cch and Dg (refering to sad fig. 6) shorts the gate to source to pre-charge Cgd', then the limiting turn-on starts.

author: dazz1
author_rank: Frequent Contributor
timestamp: July 04, 2019, 09:51:36 am
content: HiI have done some more testing and come up with some promising results.The simplified design rules I have figured out are:R1 defines the duration of current limiting, and therefore the peak in rush current. If you want to reduce the peak current, increase R1.The ratio of C1 to C2 is important. C1 ~ 10 x C2 The ratio defines the shape of the response curve. I suspect this ratio will be dependent on the PMOS devices transconductance. I don't have a model for the specific device I want to use (SQD40031EL).When C2 >> Ciss changing device parameters doesn't have too much effect on operation. This is demonstrated by placing two mosfets in parallel. Something I intend to do because it will increase efficiency (half Rds) and keep the MOSFETs within their SOA. Note that the peak current in the plot is per device. To keep the battery current within limits will require an increase in the value of R1.R2 is there as a snubber to soak up any oscillation / RF interference at the gate. Its value doesn't have much effect on the inrush response.Attached are the:circuits for a single and double MOSFET inrush current limiters andplots of their transient responses.These models do not include a low power switching MOSFET in series with R1. That will be necessary to switch the power.I need to do some more modelling to look at different starting conditions before building a hardware prototype. Even with fused protection, the potential current available from a large Li battery is a lot more than I want to draw.I really need a current probe and storage scope but both are lots of $cash. For this one project, I might look at hiring.Dazz

author: capt bullshot
author_rank: Super Contributor
timestamp: July 04, 2019, 11:06:04 am
content: A very simple way to see your basic circuit working (the one from your first post) would be to provide C2 with a proper start value for the simulation (charged to supply voltage level).Then you'd see the miller integrator working. Next step would be to provide some kind of circuitry to provide this start condition in real life (one cannot simply define this capacitor properly charged at time of battery connection in real life, but one can do so in simulation).The new circuits you came up with don't provide this start condition in a proper way, they're just a capacitive divider that reduces the G-S voltage at turn on, with some (calculatable) luck below the gate treshold voltage so the circuit kind of works.You'd want to completely short gate to source at turn on, so C2 can fully charge (add some resistance to C2 to limit the charging current), then open the G-S short and the circuit will behave as expected.

author: dazz1
author_rank: Frequent Contributor
timestamp: July 05, 2019, 09:28:24 am
content: Quote from: capt bullshot on July 04, 2019, 11:06:04 amBut it:workshas near zero quiescent current (only leakage)is simpleeasy to tuneis OK with wide component toleranceshas low parts countQuote from: capt bullshot on July 04, 2019, 11:06:04 amSounds great. Do you have a circuit diagram and Spice plots?Dazz

author: dazz1
author_rank: Frequent Contributor
timestamp: July 06, 2019, 10:56:59 am
content: HiI have done some sensitivity analysis to figure out the optimal behaviour of the inrush limiter circuit.I ran stepped simulations to see how the value of C2 affected operation.In simple terms, if C2 is a too high value, the MOSFET will emit the magic smoke.If C2 value is too small, the peak inrush current will be unnecessarily large.If C2 is just right, current will ramp up from zero at the moment power is applied.Danger lurks if there is a step jump in current when power is applied.The ratio of C1 to C2 is affected by the PMOS threshold voltage.Around 10 to 1 is about right.Try 20 to 1 initially to be on the safe side.The next step is to build a prototype and validate the model.Dazz

author: dazz1
author_rank: Frequent Contributor
timestamp: January 05, 2020, 10:44:21 am
content: Hi(note I am having problems attaching images. Will fix this in the next day or so.)I have modeled an in-rush test circuit and validated the model. I found a lot of bad information and circuits that could not work. This information is backed up with actual circuit testing and scope screen shots.The model circuit is shown in the next post:It works as follows:When power is first applied, the FET gate voltage VGS is kept low. C1 acts to pull up the voltage with R1 and keep the FETS switched off.As the impedance of C1 increases, VGS also increases. The gates are pulled toward ground which starts to turn on the FETS.As the FETS turn-on, C2 applies voltage to the gates, reducing VGS and providing some negative feedback.C2 voltage applied to the gates is proportional to the rate of voltage increase across the load. A high rate indicates high current, so C2 attenuates in-rush current.R1 sets the RC time constant for the circuit. A long time constant reduces the peak inrush current.R5 is a DC pull up resistor.The simulations and measured circuit results show there is a optimum ratio between C1 and C2. The optimum ratio is achieved when there is a small delay between when power is applied, and when the FETs begin to turn on. When this condition is met, the current curve is wide and shallow. The peak in-rush current is minimised.If C2 value is too high, or if C1 is not included, there is a massive current spike. When power is first applied and the source voltage increases, C2 provides a low impedance path to the load capacitors. C1 pulls down the gate voltage turning on the FETS until the drain voltage starts to increase. This effect causes a large but short inrush current spike. This can be seen on both the simulation and the circuit.The ratio of C1 and C2 set the shape of the current curve. R1 sets the duration and the peak current.When the ratio is right, the gate voltage that controls the current is smooth and consistent. The inrush current curve minimises the peak current.The circuit showed a very short current spike when power was first applied. My requirement was to keep the inrush current to less than 75A for less than 1ms. This short spike is well that specification. The test circuit is a rats nest so the spike is likely to be an artifact of poor circuit layout.Note that the stepped cap values in the simulation are not the same as the actual circuit values.Both the simulation and the circuit show that the ratio of C1:C2 has a wide tolerance.Images of the circuit response are shown in the next post (I hit file size limits). These plot the load current and the gate control voltage for different ratios of C1: C2.Dazz

author: Yansi
author_rank: Super Contributor
timestamp: January 05, 2020, 11:36:31 am
content: http://www.ti.com/lit/an/snva717/snva717.pdf

author: dazz1
author_rank: Frequent Contributor
timestamp: January 05, 2020, 06:00:28 pm
content: Quote from: Yansi on January 05, 2020, 11:36:31 amI haven't seen this before and I have only had a quick flick through but it looks like the best reference I have seen to date. I wish I had seen it sooner.The circuits include features that I don't want or need, and it is not efficient enough for my application but the core of circuit at Figure 5 is the same as I describe here.My contribution here is defining the importance of the relationship between C1 and C2 (my circuit).Dazz

author: dazz1
author_rank: Frequent Contributor
timestamp: January 05, 2020, 06:02:42 pm
content: HiMore screen shots here.

author: dazz1
author_rank: Frequent Contributor
timestamp: January 05, 2020, 06:04:28 pm
content: And some more circuit responses.The modelling and measured results show that inrush current form is shaped and minimised with the correct ratio of C1 to C2.The RC value between C1,C2 and R5 define the duration of the inrush control, and can therefore be used to set a peak inrush current value.The ratio C1 to C2 will be affected by the characteristics of the FET(s) so some experimentation will be needed to optimise a design.Dazz

author: Yansi
author_rank: Super Contributor
timestamp: January 05, 2020, 08:33:45 pm
content: Quote from: dazz1 on January 05, 2020, 06:00:28 pmBy adding one more lil transistor, you can make the inrush current well better controlled and even make the whole short circuit or overload proof.

author: dazz1
author_rank: Frequent Contributor
timestamp: January 06, 2020, 04:21:32 am
content: Quote from: Yansi on January 05, 2020, 08:33:45 pmHiFor this application, the main reason for the in-rush current limiter is because of the battery protection incorporated inside the battery. It trips out if 75A load is drawn for >1ms. The battery is the only source of power, so no need for input protection. A fuse is included just in case the electronics protection fails.The output of the current limiter is only connected to a SMPS which has its own input protection.Given this is a battery-only application, energy efficiency is paramount. I am fretting about adding connectors with 15mV loss so adding a diode in the power path is a non-starter.The only reason for using 2x FETS is to reduce Rds and therefore improve energy efficiency.The reason for keeping the inrush current down to the relatively low 30A or so is to keep the FETS within their SOA.FYI attached is the layout of the test setup. Very old school but effective.Dazz

author: Doctorandus_P
author_rank: Super Contributor
timestamp: January 08, 2020, 12:03:15 am
content: Why would you say that SNVA717 is "Not efficient enough for my application"The reverse polarity diode in "Figure 5" is probably one of the features you do not need and can be easily omitted.The only other component in your current path is some big power MOSfet, and dowaday's RdsOn of those things is lower than from a piece of wire.It seems to be turned on slowly from some RC constant, which certainly limits inrush current, while turning the MOSfet fully on after a while.What sort of efficiency are you looking for? Less power loss, component count, / cost, other ?The Only way I can see an improvement is if you modifiy your load in such a way that it inherently does not draw a big inrush current.

author: dazz1
author_rank: Frequent Contributor
timestamp: January 08, 2020, 03:40:29 am
content: Quote from: Doctorandus_P on January 08, 2020, 12:03:15 amI don't know anything about the SNVA717 device. My comment relates to net circuit efficiency.Quote from: Doctorandus_P on January 08, 2020, 12:03:15 amAs I recall, the power efficiency of the circuit is specified in the App note.Quote from: Doctorandus_P on January 08, 2020, 12:03:15 amThe response of this circuit is a result of the combination of C1 and C2 caps. I tried putting diodes in series with the caps to create an analog OR gate driving the FET gate pin. The circuit response was terrible. The complexity of the circuit operation is hidden in the simplicity of the topology. It took me quite a while to figure out how the circuit actually works.Quote from: Doctorandus_P on January 08, 2020, 12:03:15 amMostly power efficiency, secondly parts count and assembly cost.Quote from: Doctorandus_P on January 08, 2020, 12:03:15 amMy load is an off-the-shelf SMPS with a design I have no influence over. Modifying the SMPS would void all of the certifications. It would be the most expensive solution. I have modified the load seen by the battery with the circuit shown here.The circuit I have applied is commonly seen in the literature. The thing that I have not seen documented is how to optimise the performance of the circuit. That is, how to minimise the in-rush current while producing a stable and well behaved circuit with wide component tolerances. If that information is published anywhere, I haven't found it.Nor have I found a description of how the circuit actually works. That specifically includes App Note AND9093. I could not get the circuit shown in Fig 7 to work. It is notable that the plots of the circuit output are not shown.If anyone wants to design a simple in-rush current limiter, then the information I have provided will help with that.The TI App Note provides extra functionality that is not required or desired in my particular application.Dazz

author: Yansi
author_rank: Super Contributor
timestamp: January 08, 2020, 08:10:51 am
content: You should probably stop that your "know it all" attitude, if you are asking for help.If you are that smart, it shall be probably obvious, what part of the linked AN is relevant to your problem and what is not.

author: dazz1
author_rank: Frequent Contributor
timestamp: January 08, 2020, 08:32:26 am
content: HiThose that think they know it all only annoy those of us that do.No "know it all attitude" intended.Others must have done the same analysis but chosen not to share or were unable to share the results. I can and have put this onto the forum as a positive contribution. I started by asking for help, but I did the analysis and now I am providing answers backed up with evidence.If you apply the linked AN you will end up with a circuit that does not work.Dazz

author: LoveLaika
author_rank: Frequent Contributor
timestamp: September 13, 2023, 02:10:20 pm
content: Quote from: capt bullshot on July 03, 2019, 07:26:32 pmI know it's been a while since this post, but what are the proper starting conditions for the AND9093 inrush current limiting? You said that C2 was the one causing the inrush current. In simulation, I see that, so why do they have their C2 like that if that's causing the inrush current? Looking at Figure 7 of AND9093, I still get an inrush current when I run everything in startup conditions (all voltages are 0 volts initially). What conditions are they assuming so as to not have inrush current?

author: dazz1
author_rank: Frequent Contributor
timestamp: September 14, 2023, 01:29:41 am
content: Quote from: LoveLaika on September 13, 2023, 02:10:20 pmHiI can't answer for them but I think it shows the importance of doing your own modelling/testing/development rather than applying a follow the cookbook approach.