Making a PWM based voltage standard. - Page 1
Forum section: electronics / projects

author: Doctorandus_P
author_rank: Super Contributor
timestamp: September 02, 2021, 10:05:58 pm
content: Some time ago I got a bit interested in generating variable reference voltages. I first had a bit of thought about Kelvin-Varley, but it seems a bit obsolete, bulky & expensive.So I did a bit more research and everybody seems to use PWM these day's.PWM is inherently linear, and does not need precision parts (or just a few of them).So I did a few simple calculations, based on the attached schematic.If you take a 16-bit PWM output of a 100MHz microcontroller, then you've got a PWM frequency of around 1.5kHz.A 3rd order low-pass filter of around 15Hz or = 94 rad/s seems appropriate. With a 6 time constants settling time it's stable after around 63ms which is good enough to 10+ measurements per second in some automated setup.A single filter stage does 20dB /decade, so 2 decades * 3 orders * 20dB = 120dB dampening of the PWM ripple. (Back of envelope calculations, but accurate enough).Maybe throw in some resistor sized inductors to get a passive 6-stage filter. The beauty here is that the whole filter is non-critical No precision parts needed. The only critical parts of the filter are probably the leakage through the PCB and the capacitors, and the buffer opamp bias current. so good quality capacitors are needed, but only a few of them.But a 16 bit PWM is not very impressive. It will have very noticeable steps in it's output voltage. So then you add another identical stage, and connect them with a high ohmic resistor (Oops I goofed up: 1uF * 100M Ohm = 100s time constant). But the overall Idea is clear. The second stage adds a bunch of small steps in between the main PWM generator, and exactly how many of those steps and their size is a software calibration.For the switches I think that a simple 74HCT541 is a reasonable choice. By using all 8 outputs parallel the differences between the N- and P- channel mosfets become less important. The 74HCT541 itself is powered from the (constant) voltage reference. Asymmetry between rise and fall times is probably fairly easy to calibrate out. It's got a 100MHz or so microcontroller on board (I'm thinking of 168MHz STM32F411 from the WeAct Black Pill)I think this is a recipe for a quite good but still low cost variable voltage generator. Most of the parts are cheap and easily available. I have not thought much about what voltage reference and opamp to use. (Opamp has to be a precision type with FET inputs and low bias current).Overall this may be a better option compared to the Kelvin-Varley variant with steppermotors I also posted here:https://www.eevblog.com/forum/projects/making-switch-contacts-for-kelvin-varley-project/1. Did I make some gross errors here, or does the idea look quite sound?2. How good could such a thing be? Would a very good voltage reference be a waste for this application?3. Alternatives for the PWM buffer? Maybe a MOSFET gate driver or analog switch (but these get more expensive quickly, and are more difficult to obtain)

author: moffy
author_rank: Super Contributor
timestamp: September 03, 2021, 01:21:37 am
content: PWM is not perfectly linear because leading and falling edges have finite times. Clocks also have jitter etc., plus PWM is inherently noisy. You would get better performance using an FPGA than a micro, faster I/O. But along with precision of voltage, a voltage reference needs to be low noise, PWM just isn't going to compete with inherently linear voltage sources. Also for PWM based Vref the supply to the logic needs to be a Vref, which needs to supply the load current for the logic including the switching glitches, not a good formula.

author: Nominal Animal
author_rank: Super Contributor
timestamp: September 03, 2021, 12:46:36 pm
content: Quote from: Doctorandus_P on September 02, 2021, 10:05:58 pmDo consider pulse density modulation instead. (Say, anN-bit counter incremented by the duty at each cycle, with the most significant bit determining the output signal state.)Except for duty very close to 0% or 100%, the resulting spectrum is much easier to filter out.If you limit the duty range to say 6.25% to 93.75% (1/16 to 15/16), the maximum interval between transitions is 16 cycles. Most of the noise to be filtered out in PDM is therefore very high frequency (compared to PWM), and easier to filter out. (In general, restricting the duty range to 1/Nto (N-1)/N, inclusive, ensures the maximum interval between transitions isNcycles.)There are obvious downsides, of course. One is the much greater number of transitions (and therefore the switching transistors are in their linear region a larger fraction of time, yielding a higher power consumption; and possibly nonlinearity etc. due to asymmetric rising/falling transition rates).

author: Kleinstein
author_rank: Super Contributor
timestamp: September 03, 2021, 02:11:09 pm
content: The filtering is not working that well with 3 stages just passively connected. It is a lreatively low load to the switches (P to N symmetery gets important) and the output is still quite high in impedance. The roll of is still relatively soft. There are better suited filters, that also avoid an extra OP in the signal path.The Logic chip for switching is kind of OK, though not ideal. The voltage is relatively low and thus errors at the output buffer get relatively important.CMOS switches look like a reasonable compromise. something like DG419L, maybe DG403 could be a possible alternative. They have the advantage that the gate drivers use a separate supply and thus less spike to the reference.I would not go all the way to pulse density modulation, as this would give a variable switch frequency. More like a littel modulation on top of a PWM for the last 1-3 bits.I know that some classic solutions use 2 x similar PWM, but I would avoid it. For the lower bits I would just use an of the shelf DAC. At some 8-12 bit this is not a big deal and avoids possible interaction between the 2 channels when the transistions happen at the same time.The simple solution as shown may not be very linear due to the switch resistance. For the residual ripple it depends a lot on the layout and how sensitive the reference is to pulsed load. Some refrence chips have quite a good output driver, some would need an extra buffer. A µC inernal PLL to generatore the higher clock speed can have quite some jitter - it depends on the details. Especially non integer PLL ratios can be bad.

author: moffy
author_rank: Super Contributor
timestamp: September 03, 2021, 03:22:43 pm
content: Sigma-Delta DACs do use switched pulses fed into an analogue filter, simplest is just an integrator, but they involve a lot of design. I have previously built a Sigma-Delta ADC on a breadboard but the best I got was about 14 bits with some drift. It gets a lot harder to get better results.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 03, 2021, 04:55:50 pm
content: The simple sigma delta ADC/DAC don't get a constant numbers of switchings and this is a big problem for linearity. A simple PWM or slightly modulated PWM is better for linearity. For the start, just simple 16 bit PWM is OK. A little slower and as compensation a better (less rounded transition) is probably easier, as the switching adds to the errors.Different rates for falling an rising are not such a problem. The probelm there is more if the rates drift. Chances are one would need to trim / measure the zero anyway because of different delays and even AZ OPs still having some offset. Nonlinearity comes in when the reference buffer is not yet settled before the switch is operated again. More switching also sums upt the error from more such events.

author: iMo
author_rank: Super Contributor
timestamp: September 03, 2021, 07:05:04 pm
content: In Metrology section - thread "LM399 based 10 V reference" there is a long series of posts related to making a pwm based voltage standard, aprox from replay 850 to 950 (+/-50)..

author: macaba
author_rank: Regular Contributor
timestamp: September 03, 2021, 09:05:54 pm
content: I've built a precision PWM DAC so the following is based on that experience:- There will be a non-linearity, the midpoint will be the worse error, additional circuitry is normally needed to reduce the current going though the main switch.- There will be a long settling time for the filter due to dielectric absorption. As a rough rule-of-thumb, I discovered WIMA polypropylene 2.2uF takes around 60-90 seconds to settle to <0.1PPM. That's a very good capacitor.

author: Badwolf
author_rank: Contributor
timestamp: September 04, 2021, 10:06:28 pm
content: The PWM reference is used in many calibrators considered to be rather efficient, e.g.: Adret 103 and 104, Valhalla 2701C. The latter is quite interesting and simple to study if one makes abastraction of the FET cascade for the generation of the 1000v.For the filter, I recommend the one used especially in the 2701C which is of the type zero-offset active lowpass (a description is available on EDNhttps://www.edn.com/zero-offset-active-lowpass-filter-part-1). It makes it possible to have good filtering without the usual inconvenience of conventional active filters (offset drift, ...)

author: iMo
author_rank: Super Contributor
timestamp: September 05, 2021, 10:54:45 am
content: Some sims with above zero offset low pass

author: Doctorandus_P
author_rank: Super Contributor
timestamp: September 09, 2021, 12:06:22 pm
content: It's been a week now since my first post.It took me some time to digest it all. especially the LM399-10V-standard thread.It's become abundantly clear that when you go over 3 digits or so of precision / accuracy / repeatability / etc, then all sorts of small details become important.My main goal is not to build a perfect voltage standard, but to design and build some measurement equipment for a low budget, but still very usable and affordable. Similar to the Scullcom series, which I quite like.I think I first start with some simple power supplies. Maybe just a symmetrical power supply from 2x 18650 with built in protection circuits. Then expand with some ADS1118 ADC on a uC for logging data for a few days. For example, build two uC's with PWM based Reference voltage generators, set them to the same voltage output, and then log drift between them. I also still have to do linearity, noise and drift characterization of the HX711 I've got lying around.I do have the reference manual with full schematic of an old Kelvin-Varley Fluke reference thingie with oil baths, but I do not have a full schematic of any of the more modern PWM based equipment. some block schematics, those do not have enough details for filtering and such. Can't find a (free) schematic of the Valhalla 2701C. Adret 103 was mostly French (Yuck) only block schematic and no full schematic.The EDN article for zero-offset active lowpass filtering is also interesting, but putting 200k in series is not good for wanting to measure 5+ digits accurate DC. At the moment I'm leaning much more towards a passive (dampened) LC filter approach. Low DC resistance, High dampening for higher frequencies, and maybe add a double pi for sucking out the PWM base frequency. Passive filter is relatively easy to design, because I do not need a sharp corner frequency nor a very linear response just below the corner. I just want high suppression for frequencies of two orders of magnitude above DCThere is lots of room for experimentation. I've got an old Rigol DS1052E but such scopes (and scopes in general) lack accuracy. The old trick for using an audio card for measuring audio-frequency stuff may still be the best option for a low-budget approach.I also value the remarks of the 74HCT versus analog switches and the DC reference loading. AD411 are above my budget for a thing like this though. but the remark is important enough to also build some 4053 based variant, put some of the switches parallel and compare differences in DC, charge injection, leakage, asymmetric switching and other things that can introduce non-lineairity. One of the experiments is probably to build both 74HCT and 4053 variants, and compare linearity.I've thought about pulse density modulation.It's probably not a good idea for this. DC voltage can be extracted sufficiently with a better passive filter (8 stage LC?) while more flanks introduce more non-linearity.Static 5V voltage standard IC's are another issue. These things become expensive quickly when you want more stability. My goal would be to have around 10ppm resolution / accuracy and drift per year for an EUR10 total BOM cost (exclusive power supply, PCB), and preferably also with readily available (no vintage) parts.

author: mawyatt
author_rank: Super Contributor
timestamp: September 09, 2021, 01:35:06 pm
content: A technique we utilized decades ago in our precision FOG work was to employ an Elliptic (Cauer) or Inverse Chebyshev low pass filter for analog waveform smoothing. The filter transmission zeros were located to suppress the fixed frequency components in the input, this is similar to what DMMs do digitally for AC mains line frequency suppression. You can also utilize a twin "T" notch filter at the interfering frequency along with a regular Low Pass for smoothing.Best,

author: Badwolf
author_rank: Contributor
timestamp: September 13, 2021, 07:06:16 pm
content: In case you want some info on the Adret and the Valhalla. Here are the documents of these 2 devices.The Valhalla diagram is slightly easier to understand.

author: Echo88
author_rank: Frequent Contributor
timestamp: September 13, 2021, 07:59:11 pm
content: Throwing in the Fluke 5700A PWM DAC:https://xdevs.com/doc/Fluke/5700a/Fluke_5700A_5720A_Multi-Function_Calibrator_Service_Manual.June_1996.pdfPage 514With a good explanation of the DAC on page 123.

author: MIS42N
author_rank: Frequent Contributor
timestamp: September 14, 2021, 05:36:44 am
content: Although it isn't a voltage reference, I am using a PWM to source the control voltage for an OCXO. It is a 10 bit PWM driven at 40kHz from a PIC16F1455. In software, the width of every pulse is varied (if necessary) to generate voltages between what would be obtained using fixed pulse width. The base number used is 24-bit and the voltage is from 0 to 5V resulting in steps less than a microvolt. At 40kHz the bit stream repeats more than twice a second, and the application only needs to change the voltage once a minute or more. The filtering I use is adequate for the application. The output probably has all the non linear behaviour others have pointed out, but this could be compensated in software by comparing a few points against a better reference.Just throwing the idea into the mix. No messy combining two sources into one.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 14, 2021, 08:18:42 am
content: Combining 2 parts is not that complicated. The main difficulty is getting the scale factor right for the small part. So it needs a way for the adjustment. However in many versions one would need a way to check / set the zero point anyway and using this also for the fine scale is not that much extra effort (mainly software).For the fine part I would prefere a ready made DAC - some 8-10 bit accuracy could be sufficient with enough resolution from the main PWM.The Fluke5700 circuit is quite a bit confusing. The 57LFC has a somewhat simpler version, using CMOS DG411 switches instead of discrete fets. The linearity compensation is also easier to understand in that form.Using HC4053 type switches would limit to reference level to some 7 V (e.g. as +-3.5 V). Lower voltage makes amplifier offsets more important. At the very low cost end a 5 V ref. may still be OK, but it limits the performance a little.

author: iMo
author_rank: Super Contributor
timestamp: September 14, 2021, 08:48:09 am
content: Quote from: MIS42N on September 14, 2021, 05:36:44 amHow do you do that in sw?

author: MIS42N
author_rank: Frequent Contributor
timestamp: September 14, 2021, 09:39:49 am
content: Quote from: imo on September 14, 2021, 08:48:09 amTimer 2 is the counter for driving the PWM, and for other reasons it is set to loop at 250 (25ms). On the timer interrupt, enter the interrupt routine:Code:; Timer 2 determines the length of each PWM output. The duty cycle of; each pulse is dithered each interrupt. In software, the PWM value is; held as 24 bits. The most significant 10 bits are loaded into the PWM; duty cycle register. The least significant 14 bits of the 3 byte PWM; value are repeatedly added to the value Dithr. If Dithr overflows to; the 15th bit then the duty cycle is increased by 1 bit for the next; PWM pulse.BANKSEL PWMMOVF PWM,W ; Add the least significantADDWF Dithr,F ; 14 bits of PWM to DithrMOVF PWM+1,WANDLW 0x3F ; truncate to top 6 of 14 bitsBTFSC STATUS,CADDLW 0x01 ; add in carryADDWF Dithr+1,W ; add to the current DithrBTFSC WREG,6 ; was there 14 bit overflowBSFSTATUS,CANDLW 0x3F ; truncate to top 6 of 14 bitsMOVWFDithr+1MOVF PWM+1,W ; now work out the top 10 bitsANDLW 0xC0 ; get least significant two bits of 10BTFSC STATUS,CADDLW 0x40 ; yes, increase duty cycle 1 bitMOVWF PWM2DCL ; save 2 bits for inserting in CCP1CONMOVF PWM+2,W ; top 8 bits of duty cycleBTFSC STATUS,CINCF PWM+2,W ; add 1 if there was a carry from bottom 2 bitsMOVWF PWM2DCH ; and store it as top 8 bits of next pulse widthAlthough it is called 40,000 times a second it only takes about 15% of the available cycles with a 10MHz instruction rate. The PIC PWM is double buffered so there's no problem writing the next value asynchronously. Hope it makes sense. If all the PIC was required to do is generate the bit stream the Timer could be set to 64, so only 8 bits are loaded into the PWM (effectively an 8 bit PWM) which would make the bit fiddling much easier. The output pulse rate would be 4 times higher making filtering easier.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 14, 2021, 09:52:56 am
content: For the modulation of the PWM ratio there is a rather simple way like 1st order sigma delta. The set values is with a higher resolution and the difference between the set value and the values actually send out as PWM is summed up. The summed up part from the past is included in calculating the next pwm setting. With this simple method the PWM setting switches between 2 adjacent values. The natural implementation has the adjustment in the PWM timer ISR to calculate the next setting. Often the timer HW support suitable buffering / shadow registers.There are also ways to do higher order SD modulation, e.g. like the MASH converters used for audio. It is a little more math, but still not that much. The PWM setting may change even by 2. I would still not go so high in the PWM frequency, as the switching part adds errors. Somthing like 1 kHz should be enough to get easy filtering and reasonable fast settling on a step. The modulated part has lower frequencies, but these are with a significant lower amplitude. So the normall fitler would still be good for the much smaller residual part at 500 Hz to 100 Hz. The subharmonics start out much lower (e.g. 1/10000).Ideally the digital moulation should be of a similar order as the analog filter.

author: MIS42N
author_rank: Frequent Contributor
timestamp: September 14, 2021, 12:26:20 pm
content: Quote from: Kleinstein on September 14, 2021, 09:52:56 amExactly what the bit of code I posted does (but not particularly elegantly). The set value is named PWM (3 bytes), the summed up part is Dithr (2 bytes, 14 bits used). And yes, the PWM hardware does the buffering. I noticed after posting that the code was cut and paste from a PIC16F628A to a PIC16F1455. The latter has an expanded instruction set and some of the cumbersome carry code could be cut out by using ADDWFC (add with carry) which wasn't in the original instruction set. But if it ain't broke ....

author: iMo
author_rank: Super Contributor
timestamp: September 14, 2021, 05:13:58 pm
content: While g..ling on the dithering I foundthispdf doc (ST) on PWM dithering (for stm32 mcus).They use a table in sram with dithering patterns which create the lowest ripple, reading them via the dma into the pwm registers.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 14, 2021, 05:48:22 pm
content: The table and DMA solution is convenient if only a slightly higher resolution is aimed for and the hardware provides this feature. Not all µCs offer this option.Some of the STM32 µCs (and also some other comparable µCs) provide very high resolution PWM with added interpolatoin for the timing. So they get PWM resolution as if the base clock would be in the GHz range. So they may provide 20 or even 24 bit PWM resolution at a reasonable frequency without a fine part.edit: However there may be a timing problem: delivery in may 2022 with some luck.

author: iMo
author_rank: Super Contributor
timestamp: September 14, 2021, 05:52:17 pm
content: Here is the sourcehttps://www.st.com/en/embedded-software/x-cube-pwm-dithr.htmlAnd yes - the stm32f334 - has a 217ps resolution timer, for example ..

author: iMo
author_rank: Super Contributor
timestamp: September 14, 2021, 05:54:43 pm
content: Quote from: Kleinstein on September 14, 2021, 05:48:22 pmNo problem, till may 2022 your ADR1000 will just pass the initial burn-in

author: MIS42N
author_rank: Frequent Contributor
timestamp: September 14, 2021, 10:29:45 pm
content: Quote from: imo on September 14, 2021, 05:13:58 pmI had a look at the application note. The pattern table they show for adding 3 bits is exactly what would be produced by the method suggested by Kleinstein, and implemented by myself to add 14 bits. Except for the line 3/8 which I suggest is an error.It should be 0 0 1 0 0 1 0 1 which does not have 3 zeros in a row. The error is not repeated in 5/8.In case anyone should stumble on this looking for actual code, I revised my crude example for the PIC and updated it for the enhanced 8 bit instruction set. In my defense, the original was written over 10 years ago as part of the first program I wrote for PIC. I hadn't looked at it since, except to modify the PWM register writes.It may seem ludicrous to extend 10 bits to 24 bits, it is only useful when the output doesn't change frequently. At 40MHz the full pattern repeats in less than half a second, so if changes are made less frequently then the technique becomes applicable. In the particular application it is changed every few minutes. There is a project called picDIV which implies the PIC outputs have very little jitter, so it may be quite linear and accurate. I'll leave that to the metrologists.Code:BANKSEL PWMMOVF PWM,W ; Add the least significantADDWF Dithr,F ; 14 bits of PWM to DithrMOVF PWM+1,WANDLW 0x3F ; truncate to top 6 of 14 bitsADDWFCDithr+1,WMOVWFDithr+1ANDLW0x40 ; isolate possible carry outXORWFDithr+1,F ; remove it from DithrADDWFPWM+1 ; now the most significant 10 bitsMOVWF PWM2DCL ; bits 0-5 ignoredCLRWADDWFCPWM+2,WMOVWF PWM2DCH ; and store it as top 8 bits of next pulse width

author: MegaVolt
author_rank: Frequent Contributor
timestamp: September 15, 2021, 09:50:47 am
content: Dithering is not a magic solution. If you get a normal PWM at 1 kHz and use 4 cycles to add 2 more bits, your frequency becomes 250 Hz. And accordingly the filter should get better. Otherwise you will see a wave with a dithering frequency on the output.

author: MegaVolt
author_rank: Frequent Contributor
timestamp: September 15, 2021, 09:52:35 am
content: The best magic is to stack two PWM channels with different gain. Or a combination of PWM+DAC.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: September 15, 2021, 01:00:18 pm
content: I thank you very much for the documentation of the Valhalla, Adret & Fluke.I've got some more reading to doAnd I also thank you in the name of the 20 or so other who had enough interest to download it.@MIS42NMy main reason for adding two separate stages is to use higher PWM frequencies. I want to do automated measurements, and for this my goal is 4 or 5 digit settling times in 100ms. Not "just" DC. (I need to do some calculations to get this right)But a bit stream repeating "twice a second" is not going to do it for me, and your filter is not going to attenuate the 2Hz ripple.@kleinstein.Calibrating the small part is not difficult (in theory). It just needs a "zero comparator" just like other standards comparisons. Then you use two resistors, and set the coarse PWM to one step below the resistor divider, and start adjusting with the small stepsto find zero. Then you set the coarse PWM one bit higher, and start adjusting with small steps in the other direction.The only pre-condition ( <- My spelling correction wants to make a pee-condition out of this ) is that all the small steps combined must be bigger then a single big step.You can repeat this at different voltages to measure differential non-linearity of the "big" steps. It's just software, so I may give this a try.I intend to have a configurable overlap between the two (Jumpers or a single resistor replacement), so I can experiment with 12 to 16 bit PWM for the fist stage, which allows for higher base frequency and easier filtering or quicker settling times.Using a ready made DAC, is extra hardware and you also have to combine it with the voltage reference. With PWM, you can combine them before (or halfway) the filter. And with 74HCT you can easily use 2 times 4 outputs (maybe 6 + 2 is better?) which again reduces costs.Using a 10V reference does halve offset problems compared to 5V. But I'm not aiming for lab grade prescision here. 4 digits of real precision and 5 digits resolution is my minimum goal, while 5 digits of real precision with 6 digits resolution would be a plus, but that would be my upper limit.My best meter is currently an 4000 count old Wavetek Meterman 35XP, and this PWM thing can easily outperform it in resolution.It also has no serial output (it can be modified, it's on the chip)The best meter I'm willing to put my money in would be a Brymen BM867sIt would be hard to beat for EUR150.https://www.welectron.com/Brymen-BM867s-Multimeter_3I just have to compare it with some other Brymens before I make a final decision.It does need data logging though, so I can write a script and let it gather linearity data for a few hours.I don't trust UNI-T because there is too much quality variance in their products.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 15, 2021, 01:38:05 pm
content: Using PWM also for the fine part is OK at the lower grade level. However it may introduce some INL if the PWM steps of the fine an coarse part coincide. So for a higher level (6 digits and more) it may be easier to use a DAC for the fine part instead of extra effort to really isolate the 2 PWM parts and do the tests to be sure.One can use the extra modulation of the PWM setting also with a higher PWM frequency. It is a way to reduce the ripple amplitude for the lowest frequency part. With the same overall resolution and the last 2 bits from modulation of the PMW setting the PWM frequencies goes up 4 times and only relatively low amplitide (e.g. 1/1000) is at the the original ripple frequency. Keeping the PWM frequency the same and adding a little modulation for more resolution is usually also OK. There are lowere frequency components, but these come at a much lower amplitude. So the filter made for the main PWM frequency can usually also suppress these frequencies, at least to maybe 1/4 or 1/8 the main frequency.For the measurement of the fine part it helps if the fine part covers 2 steps of the coarse part. For the simple test with a comparator one needs some of the fine part range ( nearly 1 step worst case) to get the first zero crossing and than an additional 1 step to get to the next.With an auxiliary ADC to cover 1 coarse step one can get away with less range for the fine part.A point easy overlooked is the buffer to drive the reference side of the switches. More switches in parallel add to the load to the buffer.The fine part is way less critical and would not need much effort, but it may be a bad idea to use the same chip to switch both the coarse and fine part, as the fine part this way can effect the coase part quite a bit.

author: iMo
author_rank: Super Contributor
timestamp: September 15, 2021, 02:06:54 pm
content: Quote from: MIS42N on September 14, 2021, 10:29:45 pmThe low output jitter (for example as it is stated on the picdiv page - 2ps) applies only when the pic is driven from an outside source. I doubt one can get such a jitter while using a crystal, PLL, or RC with the onchip oscillator.

author: MIS42N
author_rank: Frequent Contributor
timestamp: September 16, 2021, 12:56:20 am
content: Quote from: Doctorandus_P on September 15, 2021, 01:00:18 pmI agree if you want 100ms settling times a 24 bit dither isn't going to do it for you. I could argue the case for a 16 bit output (10bits + 6 bit dither), that pattern repeats in just over a ms. But whatever floats your boat. I only mentioned the technique because I have used it extensively and it works for me. But that is application specific.I must say, however, there is no 2Hz ripple as such. The output is a string of pulses that vary in width by 25ns (e.g. 500ns 500ns 525ns 500ns 500ns 525ns etc) and that is measurable at the first capacitor as a fluctuation of a couple of µV in a 300µV sawtooth. By the time it gets to the second cap, the sawtooth is in the µV region with the fluctuation down to nV. By the time the signal gets to the third cap the variation is lower than the step size (about 300nV) so of no consequence.Quote from: imo on September 15, 2021, 02:06:54 pmI use an OCXO as an external clock source.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 16, 2021, 07:54:47 am
content: From my experience with the µC based ADC I can say that the µC can introduce some jitter and not so random phase variations. e.g. the clock to the UART or µC internal ADC can have a small, but still visible effect on the output timing.This is likely not yet a problem at 20 bit resolution, but it can become an issue at 24 bit.Similar a second PWM signal can interfere with the main signal, especially if with the same frequency. This would be in the µC, but also externally with the buffering of the reference and supply to the switches. If not careful this may even be a problem at the 16 boit level.The bare crystal at the µC is more suceptable to interference (I saw up to some 10 ppm with the ADC) than an external oscillator. There is no need for an OCXO - a simple crystal should be good enough. However a mems or PLL based clock chip may show some jitter - likely still OK for some 20 Bits, but not ideal. Clock jitter and phase modulation gets more important with a higher PWM frequency, so there is also some advantage in a not so high clock frequency. Than even the cystal at the µC can be OK, with some care. With a lack of capability to measure the linearity one may still want to start on the safe side.For good settling it helps to have a good filter - just 3 stages of RC is not very effective and gets a relatively slow settling with a given suppression of the ripple. With the relatively low frequencies an LC filter is no really practical - LC is practical for more than 1 MHz maybe 100 kHz. An inductor may still help with the very high frequency content, that an active filter may not like very much.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: September 16, 2021, 11:35:18 am
content: A quick look showed that small sized inductors are readily available upto about 100mH.https://www.bourns.com/docs/Product-Datasheets/rlb.pdfhttps://www.bourns.com/docs/Product-Datasheets/8250_series.pdfWhich translates to 628 Ohms @1kHz2*pi*1000*100e-3 = 628.3185307179587Which is indeed not much, but not negligible either, and indeed it probably helps with filtering out high frequency switching artifacts, but won't help with reducing ripple at low frequencies.Maybe an inductor can reduce the effect of charge injection?Non linearity is supposedly worst near the middle of the range.I just had the idea of using two PWM outputs of the uC for the first stage. (They're cheap, most uC's have 10 or so of them)Then output them at the same PWM frequency, but with 180 degree phase shift.This adds symmetry in the buffer stage and also greatly reduces output ripple in the filter if the PWM outputs are joined after the first resistor.Which means that for example if the outputs of the 74HCT541 have a 10k and 10k1 resistor, then directly after the resistors and 50% duty cycle it switches between approx 2.45V and 2.55V,For duty cycles between 0% and 50% both the effective output frequency is doubled (easier filtering) and the output of the sum point switches between 0V and either 2.45V or 2.55V, depending which of the two phases is high. For duty cycles >50% the switching will be between both outputs high, or one of them low.So the total effect is that the PWM ripple is reduced with 75% by just adding one resistor (and a extra PWM channel and a few lines of firmware in the uC)I'm not sure yet what sort of changes get introduced by switching currents in the power supply of the 74HCT. I guess that also would be difficult to simulate (I do not have much trust in simulation anyway) I was sort of hoping that constant PWM frequencies would result in a static error which is easy to calibrate out, but that may be wishful thinking.Gosh, just realized:When adding the signals with two resistors, and without any further filtering, the output will switch between 2.45V or 2.55V, and on top of that almost DC you see all introduced switching artifacts on your scope so that is a good way to compare performance of 74HCT540 versus 4053, and what some added inductors do.

author: MegaVolt
author_rank: Frequent Contributor
timestamp: September 16, 2021, 11:41:00 am
content: Quote from: Doctorandus_P on September 16, 2021, 11:35:18 amIt is worth considering the series resistance of this coil of 484 ohms. This can introduce a DC error by forming a divider or a voltage drop at a small current.

author: ezalys
author_rank: Frequent Contributor
timestamp: September 16, 2021, 12:33:08 pm
content: What exactly does an ADI 20-bit DAC buy you over one of these PWM based DACs, besides: INL, offsets due to say, charge injection, resolution, bandwidth/settling time, bipolarity, and reduced nonlinearity around 0 volts and the reference voltage?If I wanted a dead-stable voltage at coarse resolution with ok settling time, is this a reasonable route?

author: iMo
author_rank: Super Contributor
timestamp: September 16, 2021, 01:16:50 pm
content: Quote from: MegaVolt on September 16, 2021, 11:41:00 am.. and TC=3930ppm/K for copper...

author: Kleinstein
author_rank: Super Contributor
timestamp: September 16, 2021, 01:36:10 pm
content: Quote from: ezalys on September 16, 2021, 12:33:08 pmCompared to the ready made DACs the PWM solution can be quite stable in time and if made right very linear.The down sides of the PWM solution is that it is slow and needs quite some effort for the circuit with a few point's that can get wrong.Ready made DACs get quite expensive once you want INL in the single digit ppm range. However they get afforable in the 16 bit range and below. So for the lower resolution a PWM DAC is not really attractive anymore. It becomes attractive at more than 20 bits, if speed is not really needed.