Lattice MachXO2-7000 DDR SDRAM - Page 1
Forum section: electronics / general

author: petrmate
author_rank: Newbie
timestamp: February 01, 2022, 01:36:04 pm
content: Hy.I have a MachXO2 based FPGA image processing project. I have to add a single DDR DRAM to the system to store the previous frame of the image. I have to achieve at least 120MHz memory speed at 16bit wide memory bus.At this point the project is relatively small, so we avoid BGA components, so DDR1 is the only chioce.I found this memory IC: IS43R16160D-6TL-TRhttps://www.issi.com/WW/pdf/43-46R16160D-32800D.pdf. The memory supports the "SSTL_2 Class II" signaling. I'm a bit confused about the SSTL_2 class types, what is the differencie between the two classes.The FPGA support class2 for output only and support bidirectional in class1, according to the XO2 family datasheet. So this memory is incompatible with this FPGA? I can't find DDR1 memory IC that supports class1. Have I misunderstood something?And the last question is termination. I've read a dozen of application notes about the topic, but I'm not sure what termination should I use. Serial termination is enough or I need to add pull-up resistors to the source or to the sink or to both?Thank,Petró

author: voltsandjolts
author_rank: Unknown
timestamp: February 01, 2022, 04:36:26 pm
content: Quote from: petrmate on February 01, 2022, 01:36:04 pmYourmaking a rod for your own backand your better off going 1mm pitch FBGA. It'll be fine.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 01, 2022, 05:42:03 pm
content: Note that - I don't know much about your project - but you could probably get that kind of data throughput (which doesn't sound all that impressive) using simple SDRAM with a 32-bit data bus, if you can afford the extra 16 IOs. Much easier to deal with.

author: asmi
author_rank: Super Contributor
timestamp: February 01, 2022, 08:30:51 pm
content: Quote from: SiliconWizard on February 01, 2022, 05:42:03 pmThat's gonna require like 80 IO pins. Not many non-BGA packages have that many. And it makes no sense as DDRx is better in just about every way.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 01, 2022, 11:11:42 pm
content: Quote from: asmi on February 01, 2022, 08:30:51 pmSure DDR is "better", but that's not a contest. That's about selecting an appropriate solution for the requirements.No, that's not gonna require 80 IOs, but 50-odd IOs, actually.DDR controllers are definitely harder to design, the MachXO2 is a very humble FPGA, and Lattice does not offer memory controllers for free. Were we talking about say a Xilinx Spartan/Artix 7 here, I wouldn't even have mentioned that option.So there are the pros and cons. Now it's up to the OP to select whatever suggestion they find most appropriate, but at least considering all constraints.

author: asmi
author_rank: Super Contributor
timestamp: February 02, 2022, 01:57:27 am
content: Quote from: SiliconWizard on February 01, 2022, 11:11:42 pmOf course it is - it's about finding the best solution to a problem. I'm yet to see a hardware platform which would suffer from having too much memory capacity or speed, so the more the merrier.Quote from: SiliconWizard on February 01, 2022, 11:11:42 pmIt's more like 60, but also remember that unlike in DDRx, the entire bus has to be length-matched - all signals (!!!). In DDR address/control works independently of data lanes, and each data byte lane can be length matched independendly of others, so it's actually easier to route (even if we ignore the fact that DDRx requires only half as much data width to achieve the same bandwidth).Quote from: SiliconWizard on February 01, 2022, 11:11:42 pmExcept for DDR3 with it's peculiarities like link training, I would say the rest are more-or-less the same, provided that FPGA comes with the hardware to make PHY possible, and as far as my (admittedly very rudimentary) research has shown, Lattice does provide PHY module generators for free, so it's only the controller part which needs to be designed. Not easy for sure, but not that hard either. In my experience designing a LPDDR1 memory controller, the hardest part (after PHY that is) was higher level functions like request reordering, command scheduling and other functions one would need for a full-featured AXI slave port with bursts support. Video applications typically have a very straightforward access pattern, and so they usually don't need sophisticated bus interface adapters.