(List of SDI video ICs) Please help me find an SDI interface IC - Page 1
Forum section: electronics / projects

author: Yansi
author_rank: Super Contributor
timestamp: December 18, 2019, 12:04:22 am
content: Hello,just got the idea to start this thread. Some of you may be familiar with SDI video interfaces already, for those who are not, pleasesee here (wiki), or search for the most used standards: SMPTE259, SMPTE292 and SMPTE424.I know this is a very niche topic, but lately I decided to finally start my battle through FPGAs and my main motivation behind that is to have some fun with video (and their professional interfaces). What would likely help me a bit to get started, is to make a list of what is available, what can it do and for how much. As all this will at the moment sure be only hobby level, price will also be a constraint. It is not a problem to find an interface IC within a minute, but sure it won't likely be the best suited one, certainly not cheapest option for the task.If you happen to know of any interesting diy projects that would include the above mentioned interfaces, please let me know too.I know that there are way to many possibilities to skin a cat, so making a comprehensive list of solution is impossible, but any tips and pieces of information may be beneficial for me or others, that may be also interested in the same hobby.I will divide the ICs of interest into three main groups, based on the standard they can deliver. I will stop at 3G, because I think that is the most that can be done on a hobby level without using rocket science and probably the most used standard these days.I will try to update the list below based on your suggestions. Please post tips for any SDI related ICs you know are somehow interesting, either with their capabilities or for example price-wise. (if you think this whole idea is nonsense, you can tell me that too).SD-SDI (SMPTE259)CLC001 - Cable Driver, 622mbps, SOIC8, cheapCLC006 - Cable Driver, 400mbps, SOIC8, cheapLMH0070 - Serializer, 5xLVDS in, $20+LMH0071 - Deserializer, 5xLVDS out, loop out, $25++HD-SDI (SMPTE292)LMH0034 - Adaptive Cable Equalizer, $20+LMH0040 - Serializer, 5xLVDS in, $25++LMH0041 - Deserializer, 5xLVDS out, loop out, $25++3G-SDI (SMPTE424)LMH0302 - Cable Driver, $10+LMH0356 - Reclocker, FR4 EQ, 4:1 input mux, $25++GV7600 - Serializer, parallel 20bit input, 1mm pitch BGA, $15+ (obsolete)GV7700 - Serializer, parallel 20bit input, awful dual row QFN, used in cheap Chinese products, $15+ (but not for this price likely)LMH0340 - Serializer, 5xLVDS in, $25++GV7601 - Deserializer, parallel 20bit out, 1mm pitch BGA, $15+ (obsolete)LMH0341 - Deserializer, 5xLVDS out, loop out, $25++

author: dmills
author_rank: Super Contributor
timestamp: December 18, 2019, 10:29:17 pm
content: Does your FPGA of choice have a handful of high speed serdes available on its IO?For a play toy I might be looking at a Microchip EQCO30R5, costs bugger all and will get it done within its limits. You mistake is that you have been looking at external Serdes, nobody does it that way these days.The usual way to do SDI is just to use a line receiver (Typically TI, Semtec or MaCom, but Microchip have something available that could be worth a look) and then go into the FPGA as 3Gb/s over one of the high speed interfaces.Do look to your clocking, you need something suitable wired to the Serdes PLL input 148.5/148.35MHz is the usual choice.

author: Yansi
author_rank: Super Contributor
timestamp: December 19, 2019, 07:38:31 pm
content: Could you please post some other part numbers to look for? That microchip bugger looks promising (there is even a complementary transmitter). But I have a bad feeling that an FPGA equipped with integrated 3Gbps serdes begins to be rocket science and quite expensive.I'd like to start with cheap Cyclone IV FPGAs, which are available at sensible prices. Well... at least the smaller ones.Now looking into the Cyclone IV handbook, the smallest 3Gbps capable is EP4CGX30, which is a hell of a beast, in a very unfriendly packages, not to mention the crazy cost factor. And even trying to attack a smaller BGA of probably still acceptable "diy size and complexity", like EP4CGX30BF14xxx (FBGA169, 1mm pitch) means you get only two 3gig serdes IOs. Maybe good enough for simple format converter... but not for anything past that.2.5gig serdes is available even on the smaller ones, good enough for SMPTE292 (HD-SDI). But having an external serdes leaves the option to use even small cheap FPGA, as LVDS is abundant even there. The smallest EP4CE device still has about 20 LVDS pairs available (including those emulated).Maybe I see it all just too simple to do. I know it is not and certainly will not start playing with a 3G-SDI first, but with a plain ol' SD-SDI at couple hundred mbps. For example making a simple CVBS to SDI converter would be that much fun to begin with!Maybe I should just forget all this and play with something more useful...

author: dmills
author_rank: Super Contributor
timestamp: December 20, 2019, 03:07:13 pm
content: Key phrase is "SDI Equaliser" not "SDI Serdes" because all the non integrated serdes stuff is old technology and expensive.TI LMH0324 and LMH0397 is what we tend to go to at work, but Semtec and MaCom both have allegedly pin compatible parts.Broadcast tends to be a Xilinx shop these days for the most part due to better IP being available, and in the office for small video things we generally go Artix 7 series.

author: Yansi
author_rank: Super Contributor
timestamp: December 20, 2019, 09:02:48 pm
content: Well, I haven't looked specifically for "serdes" as a keyword, but just to know what options are out there. External serdes is certainly a way to go with a cheap and simple FPGA.I have zero experience working with Xilinx devices, but I may as well switch in the future. As far as I can see, Artix 7 devices can be found for third of the price of what a decent Cyclone IV costs. Doh!The main limiting factor for a hobby use is the price and and also package. High pin count BGA are rocket science (and PCBs for them are rocket price).But to be more specific: Say I would like to start with something simple (I haven't done much VHDL past the simple stuff), so as a first trial, I'd like to just build a CVBS to SD-SDI converter. Cyclone IV FPGA should be more then enough to shovel the 27MHz sampled 4:2:2 video data, question is, how am I supposed to do the data serialization?For example, is a cheap Cyclone IV ( for ex. EP4CE6E22C8N) able to do the serialization by itself? "Just" SD-SDI, 270mbps. I have the feeling the integrated LVDS output might be used for just that, but how about deserialization of the SD-SDI data?Thank you for any insight into this.

author: dmills
author_rank: Super Contributor
timestamp: December 21, 2019, 05:53:24 pm
content: Does the Cyclone IV have per pin serdes (slow ones, not proper transceivers)?I know this is a standard thing on the Xilinx parts and you can run any LVDS pair at up to nearly a Gig even on the lower speed parts, but I have not touched Altera in years.

author: Yansi
author_rank: Super Contributor
timestamp: December 21, 2019, 06:16:07 pm
content: I am no FPGA expert, but trying to understand theCyclone IV handbook (click to open), the smallest Cyclone IV devices (I currently have some at home, the EP4CE6E22C8N) do have 8 proper HW LVDS channels, and up to 21 with the "emulated ones" (see Table 5-6 page 133), which I am not sure how to understand.Proper serdes transceivers are available only on a huge ass size BGAs, but as I understood even them, they can't work below 600mbps anyway, so probably unusable for just the 270mbps SDI.These LVDS channels if I am read the handbook correctly, can work up to 640mbps (for my EP4CE6E22C8N), see table 1-34 page 477 in the device handbook linked atop.How does one use these channels to serialize (or deserialize) the data? As I understand the typical LVDS application requires both data lanes and the clock lane to be also present for it to function.

author: dmills
author_rank: Super Contributor
timestamp: December 21, 2019, 10:16:39 pm
content: The high speed trancver serdes lower speed limit you work around by oversampling, just run the thing at a multiple of the expected data rate and decimate in the fabric.As for clock recovery, if you look at the clock generation options for the low speed pin serdes you generally find that there is some way to slip the phase by dynamically tweaking some divider phase bits or something to that effect, you can build a loop around that.Tricky but it works reasonably well, and while you still want the XO to be basically right it gives you a little wriggle room, details tend to be device family dependent as is usually the case with FPGA clocking.

author: Yansi
author_rank: Super Contributor
timestamp: December 21, 2019, 11:13:45 pm
content: Hmm... interesting. One could also use a VCTCXO or just pull a regular crystal with a varactor, using some simple external analog loop filter (would be at least way easier for me, rather than trying to do it all digital in the FPGA).While thinking about this... I remember seeing this exact solution (with VCTCXO) on a MADI audio card, where they probably have used this technique to sync the system clock onto the incoming MADI data. I think it is blatantly obvious from the pcb layout, there is some sort of analog loop filter with 272 opamp:So for SD-SDI TX, if I understand right, I could likely use the simple LVDS transmitter, likely in x10 mode and feed in the 27MHz system clock. Sounds reasonable. The LVDS_CLK out will just output the 27MHz clock anyway (but data at the x10 rate), LVDS_CLK won't be used in this case.Leaving me to "just" make the scrambler and 8b10b encoder to feed the x10 LVDS output. Is that right or have I misunderstood?Thanks, Y.

author: dmills
author_rank: Super Contributor
timestamp: December 22, 2019, 12:29:50 am
content: MADI is fun because the audio rate and the MADI datastream rate are decoupled.You can actually vary the audio sample rate over quite a wide range while keeping the MADI clock constant.External analog loops work just fine, but you will need to decide how to produce the loop control signal, and I dont know enough about the Cyclone IV to tell you how to skin that.Regards, Dan.

author: Yansi
author_rank: Super Contributor
timestamp: December 22, 2019, 12:43:25 am
content: For starters, I'd stick with just the single CVBS to ST259 conversion. For that I'd probably not need any PLL loop*, just leave the free running clock from the CVBS digitizing circuitry.Do all digital video switchers have a full frame buffers for every input, to be able to sync all (actively processed) SDI inputs? Obviously, SDI cameras are not frame aligned in any way against each other, are they?I will need to look into how the LVDS is implemented in the Cyclone IV.//EDIT: *Of course, still a x10 PLL is needed for the shift register, but that is only fed with the constant 27MHz input clock, no need to sync to any input data.

author: dmills
author_rank: Super Contributor
timestamp: December 23, 2019, 02:22:58 am
content: Nope, SDI routers and switchers generally only have a few lines or so of buffering, certainly not anything like a full frame store on every input (Gets a bit impractical at facility router scale). What they have is basically to deal with lightspeed delays on the cabling, not randomly drifting sources.The CCU (Camera control unit) generally takes a sync input (Often old school trilevel sync of all things), so yes cameras are generally locked to house sync, at least in the grown up world, difficult to do a clean wipe otherwise, even if there was a fame store on each input.Now the low end stuff may ironically actually have more going on here (BMD) simply because their users are not expecting to have house sync and are probably not so worried about small amounts of delay.

author: Yansi
author_rank: Super Contributor
timestamp: December 23, 2019, 09:57:15 am
content: Studio environment is probably genlocked, sure, but a small video production will not likely have genlocked cameras (neither will have I, hihi)I then expect to need a full frame buffer memory to be able to compensate for unknown sync relations and clock drift :-/(Black Magic Design stuff does not impress me that much, due to their stupid decision to use ST-424 level B signalling, so their equipment can't be interfaced with shit all. But that is just an offtopic rant...)