Lead length to bypass cap "must exceed 20mm" ?? - Page 1
Forum section: electronics / projects

author: adamcord
author_rank: Contributor
timestamp: May 27, 2019, 03:07:52 pm
content: Hi all, I'm thinking of using the ADuM4120-1 isolated gate driver for a project, and I came across a curious line in thedatasheet, on page 13, in the "PCB Layout" section. At the end of that section appears the following (talking about bypass capacitor placement):"The total lead length between both ends of the smaller capacitor and the input or output power supply pinmust exceed 20 mm."I'm hung up on the "must exceed 20mm" bit. My usual thinking is the closer the better with bypass caps. Is this a typo, or is there something I'm missing? Perhaps the designers found that there needs to be some tiny extra inductance between the bypass cap and the pin for high-frequency response? If anyone has some insight on this, I'd love to hear it!

author: MagicSmoker
author_rank: Super Contributor
timestamp: May 27, 2019, 03:26:16 pm
content: 99.9% chance that is a typo. No gate driver benefits from extra inductance in the loop between it and its bypass capacitors.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 27, 2019, 06:00:54 pm
content: It could almost make sense actually, in that those things use quite high frequencies internally (100s MHz) and maybe they want you to stay away from it a little bit.... but much more likely yeah it's a typo, and that's precisely why it needs to be close up.On that note, keep that in mind -- they can generate significant emissions, so a little filtering outside of that bypass cap (a ferrite bead and another cap, with everything laid out on ground plane) may be desirable.Tim

author: David Hess
author_rank: Super Contributor
timestamp: May 27, 2019, 06:46:31 pm
content: High frequency analog ICs sometimes have requirements like that but in this case I suspect it is a typo and they meant maximum instead of minimum lead length.

author: coppercone2
author_rank: Super Contributor
timestamp: May 28, 2019, 03:19:56 am
content: why does the power supply pin for the IC require a minimum 'choke' inductance ? That would be approximately 20nH I think.

author: coppercone2
author_rank: Super Contributor
timestamp: May 28, 2019, 03:30:17 am
content: Quote from: David Hess on May 27, 2019, 06:46:31 pmexample? I.e. even high power MMIC amplifiers have no such restriction. They want maximum decoupling. What is worse then a 45dB power saturation microwave power amplifier on a tiny chip??Actually I found one, which is biased at the output with VDD so it has 900nH on the Vdd rail AFTER the decoupling capshttps://www.analog.com/media/en/technical-documentation/data-sheets/HMC1099.pdffigure 38

author: JackJones
author_rank: Regular Contributor
timestamp: May 28, 2019, 03:32:26 am
content: Definitely a typo. The previous sentence talks about avoiding vias to reduce inductance, it would make no sense to then talk about adding it."Avoid the use of vias on the output supply pin and the bypass capacitor, or employ multiple vias to reduce the inductance in the bypassing."

author: coppercone2
author_rank: Super Contributor
timestamp: May 28, 2019, 03:36:40 am
content: You would think though, that if they had a amplifier on that, biased like those MMIC, it would have a separate power supply pin with forced impedance rather then sharing the RF power amplifier supply with the schmitt trigger internally... the block diagram is lackingthat would seem a little bootleg but I don't know.... is that a good design decision to share a schmitt trigger supply with a noisy RF rail thats not internally isolated? won't that risk decreasing the noise margin on the digital logic if something starts to go wrong in the chip (like the amplifier impedance decreasing, which would normally just increase dissipation and current consumption but still work without faults relating to the encoder non power section and power amplifier)?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 28, 2019, 04:03:19 am
content: They're CMOS with a somewhat hefty stage driving the monolithic air core transformer. No different from, say, 74LVC logic driving runt pulses.Tim

author: coppercone2
author_rank: Super Contributor
timestamp: May 28, 2019, 04:52:14 am
content: Quote from: T3sl4co1l on May 28, 2019, 04:03:19 amAre you sure? I thought I saw the waveforms on one of those devices in the datasheet (may have been silicon laboratories) where they show a nice sine wave based on/off modulation, like they are connecting and disconnecting a power amplifier from a oscillator, not digital logic driving magnetics??figure 20 of the datasheet link shows a sinewave/evelope detector deal

author: Arjunan M R
author_rank: Regular Contributor
timestamp: May 28, 2019, 05:51:22 am
content: It's a mistake.Look at their evaluation board.The caps are not that far away from the ic.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 28, 2019, 06:10:46 am
content: Quote from: coppercone2 on May 28, 2019, 04:52:14 am1. They're just showing the concept, not the particulars.2. The drivers may well be slow enough that it looks pretty rounded! RF amps in CMOS are the same basic thing, from 125kHz RFID tag readers to Wifi radios (the latter being rather more careful in design, however).Tim

author: capt bullshot
author_rank: Super Contributor
timestamp: May 28, 2019, 06:27:53 am
content: Quote from: T3sl4co1l on May 28, 2019, 06:10:46 amYes, we've experienced some real electromagnetic emission issues with these ADUM parts. Not the gate drivers in particular, but the Delta/Sigma frontends. You'll have to place the decoupling caps as close as possible and you need some GND and VCC planes to cope with them. Their internal CMOS drivers emit quite fast transients through the supply pins, causing trouble at several 100MHz when doing EMI compliance testing. So Tim is right about the internal structures, this was confirmed by ADI also. In more recent parts, they've changed the modulation scheme, maybe this reduces EMI also.Otherwise, for the 20mm minimum length requirement (this cleary doesn't apply here), I've done such specs before. In this particular case to add some ESR to a ceramic cap to keep the LDO from ringing / oscillation. Beware, you'll also have to specify trace width and thickness too.