Help with getting started on Lattice Brevia XP2 FPGA - Page 1
Forum section: electronics / general

author: RickCHodgin
author_rank: Contributor
timestamp: April 25, 2017, 05:04:42 pm
content: Greetings. I have a solid background in logic and low-level programming, but am fairly new to FPGAs and Verilog. I have gone through some tutorials that came with the board, and I can get the various projects to synthesize, and I have been able to program the JEDEC files and use the four on-boards switches and eight red LEDs to do some cool things (binary counter, K.I.T.T. red light back and forth, etc.) ... but there are aspects of the machine's design I don't understand and I would like to ask for help.I searched today for Lattice's own forum, but it is closed apparently:http://www.latticesemi.com/support/forumsDoes anybody have experience with these Brevia XP2 boards? I would be willing to buy another Lattice breakout board (MachOS2 orMachOS3, for example) if that would be more helpful.Basically I'm looking for information on the bigger picture of why it's doing some of the things it's doing, how I can gain more control over the clock, how the clock is distributed, what the various banks mean, etc.It may seem very obvious, but without a background in this type of thing I just don't have the basis to know what it is I don't know.Thank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: April 25, 2017, 05:22:34 pm
content: Another question: I had planned to use some of the GPIO pins to communicate with an external piece of hardware which would allow me to send data to and receive data from the host computer. But, it occurred to me that maybe there's already a way to do that using the existing USB cable for programming / power.If I had a software program and wanted to communicate data to/from the board, how would I do it? Separate hardware? An existing API of some kind through a Lattice DLL? Use a parallel or serial port (with the card's on-board UART support)? Or ... ?Thank you,Rick C. Hodgin

author: ebclr
author_rank: Super Contributor
timestamp: April 25, 2017, 05:48:32 pm
content: Did you try this link already?https://globalengineer.wordpress.com/category/lattice-xp2/

author: helius
author_rank: Super Contributor
timestamp: April 25, 2017, 05:59:02 pm
content: Typically the USB cable doesn't go directly into the FPGA, but into a support chip like a FT*232* or FX2. This chip is programmed (from the USB side) as a JTAG host to load the configuration into the FPGA. It can be re-programmed into an async or SPI port to communicate with the FPGA after configuration.

author: RickCHodgin
author_rank: Contributor
timestamp: April 25, 2017, 06:08:37 pm
content: Quote from: ebclr on April 25, 2017, 05:48:32 pmYes. It came up Googling. The board revision and software that version uses are out of date with the equipment I was able to purchase, and I was confused by his reference to equipment other than the Brevia XP2, such as the 50 MHz oscillators which can be purchased separately. I was thinking he might be referring more to the underlying FPGA and not the development kit board? I'm not sure.Thank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: April 25, 2017, 06:11:04 pm
content: Quote from: helius on April 25, 2017, 05:59:02 pmI read about that, but I didn't understand what it meant. What is an SPI port (spy port for real-time debugging)? Is there an example where it can be done through the USB? How would I open up a two-way communication over that feature in Windows or Linux?I'm needing to setup a system to transmit only about 12 KB of data per second (6 KB/s bi-directional). And, I have excellent C/C++ developer skills. I would be willing to trade some software development or maintenance for this information.Thank you,Rick C. Hodgin

author: ebclr
author_rank: Super Contributor
timestamp: April 25, 2017, 06:36:50 pm
content: Fpga have a set of internal PLL, the external clock is handled internally by the PLL and can be multiplied and divided, and can do a lot of things, generating several different clocks, your VHDL will define what is going on, an FPGA is no more than a lot of logics blocks and bunch of "electronically defined jumpers"This is the point to starthttp://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf?document_id=24635FPGA isn't a processor, is pure bare metal logic, if you want a rs232 port you need to create one, using a IP, or making your own, everthings need to created on hardware, not software, VHDL isn't software is hardware definition

author: ebclr
author_rank: Super Contributor
timestamp: April 25, 2017, 06:41:39 pm
content: SPI Serial Peripheral Interface (SPI)https://embeddedmicro.com/tutorials/mojo/serial-peripheral-interface-spi

author: RickCHodgin
author_rank: Contributor
timestamp: April 26, 2017, 12:20:15 pm
content: Quote from: ebclr on April 25, 2017, 06:36:50 pmI understand that. And I understand the philosophy of how it should work. I'm getting bogged down in the syntax, and in the various protocols specific to the boards.Another issue I have is that I have dyslexia. It's very difficult for me to read large quantities of text. I actually have my wife read stuff to me so I can hear it rather than read it. My retention is 10x what it is when I read it. :-)Thank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: April 26, 2017, 12:21:48 pm
content: Quote from: ebclr on April 25, 2017, 06:41:39 pmThank you, thank you!Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: April 26, 2017, 04:09:58 pm
content: Quote from: ebclr on April 25, 2017, 06:41:39 pmOkay, this makes perfect sense to me. I can see how two devices would communicate with each other using that protocol.I'll look in to the Lattice SPI documents.Does anybody have experience on the Lattice toolchain / system, to show me how I can communicate with the FPGA from the host computer after it's programmed using SPI over USB? I would like to be able to send and receive data generically from a high level software interface, and have the thing I communicate with be a "black box" which handles the nitty gritty details for me.Thank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: April 26, 2017, 04:26:41 pm
content: Quote from: helius on April 25, 2017, 05:59:02 pmHow do you do this? In looking at the Lattice documentation I could not see how to use it for general purpose data after programming:http://www.latticesemi.com/view_document?document_id=39454Would it be better / easier to write some custom ECP/EPP parallel port driver code in software (in DOS, for example, where I have complete control over the machine), which communicate over multiple pins a byte at a time with a simple protocol?And if so, perhaps it would be even better to use multiple ECP/EPP ports to drive the signals I'm looking for? Does anybody have experience with this?Thank you,Rick C. Hodgin

author: ebclr
author_rank: Super Contributor
timestamp: April 26, 2017, 10:38:14 pm
content: this may help you improve, You mean you wan't to comunicate with the XP2 board, what is your definition of communication?The board has a usb to serial converter, a realterm on windows side can send and receive bytes using this converter, But you need to have something inside your VHDL to do the other side of the comunication, and this must be done in veriloghttp://esd.cs.ucr.edu/labs/tutorial/https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.htmlhttps://sourceforge.net/projects/realterm/

author: RickCHodgin
author_rank: Contributor
timestamp: April 26, 2017, 11:34:34 pm
content: Quote from: ebclr on April 26, 2017, 10:38:14 pmI need to be able to send about 6KB of data per second to the board, and receive back between 0KB and 6KB of data per second.QuoteI think what you've indicated here will work for my needs. I read today at lunch about the Lattice FTDI to UART interface, and how there's a virtual serial port driver you can install on the host computer. It's exactly what I'm looking for (a "black box" from the host software side to communicate with the board).I'm working on reading/writing from SRAM tonight, and creating a little CPU that can read byte opcodes stored in SRAM at synthesis time, and handle a little programmable workload whenever data's received.I'll work on the FPGA / UART tomorrow. My 132 x 22 pixel display should arrive in time for the weekend and it would be nice to get it working this weekend with some test data I can create at synthesis time, and then get the serial communication working and displaying its data on that little screen next week.Ultimately, I plan to use the screen to display graphics data which will emulate on the display what's happening on equipment controlled by the FPGA.Thank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: April 27, 2017, 03:26:56 am
content: I couldn't get it to work. The synthesis step is saying the two nets associated with two push-buttons I created (for navigating to higher or lower addresses to display the data there on the on-board 8-LEDs) have no load. No idea where that comes from. I'm still trying to learn Verilog and express my ideas in its syntax, and it keeps knocking me down.Thank you,Rick C. Hodgin

author: helius
author_rank: Super Contributor
timestamp: April 27, 2017, 03:32:40 am
content: The verilog code is only programming the logical operations that happen inside the chip. I/O options are set in a different file called the constraint file (.LPF for Lattice). You put the pad options there, like whether each pin should have a strong or weak pullup, etc.I bet "net has no load" means that it can't set the pin for output without knowing how it should drive it.

author: RickCHodgin
author_rank: Contributor
timestamp: April 27, 2017, 03:36:52 am
content: Quote from: helius on April 27, 2017, 03:32:40 amIt's possible. I used defaults in setting the pins for each input and didn't change the UP/DOWN/whatever option each one was set for. I have my prior project that uses the board switches and it works properly, with each LED activity being tied to whatever switch is pressed down, so I'll take a look at how they are set and do the same here.Thank you for the advice,Rick C. Hodgin

author: ebclr
author_rank: Super Contributor
timestamp: April 27, 2017, 03:46:40 am
content: Here some extra resourceshttp://fpgacenter.com/examples/If you need a processor on this FPGAhttp://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspxBut the magic of FPGA is to have everything running in parallel not in sequence as a microprocessor, For the slow and sequential you can create a mico32 processor , But FPGA are more much more expensive and powerful than microprocessor, and have no sense to use FPGA only as a microprocessor, You need to take advantage of the high throughput and parallelism FPGA can give to youVHDL sintax is quite related to ADA / Pascalhttp://www.fpga4fun.com/

author: RickCHodgin
author_rank: Contributor
timestamp: April 27, 2017, 01:23:29 pm
content: Quote from: helius on April 27, 2017, 03:32:40 amIt took me some time last night to figure out how aninoutworked. I think I have a handle on it. A register is used to determine if the input should be used as input or output, and for that you use an assign like "my_inout = x ? y : 8'bZ;" so that if x is high, it routes y data on the wire, otherwise it is not routed, and is then used instead to sample the input values.Is that correct?It also took me some time to realize that input wires that aren't identified by their subsequent use in source code are considered the pin in/out contacts to the outside world. I couldn't figure out why the top module had input wires which were then routed to other modules which received them as input registers, but now I see that the registers become the source for those wires, whereas the input wires that are not identified as being sourced to a register by any module must then be routed to an external pin through explicit assignment.Is that correct?Thank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: April 29, 2017, 04:45:19 pm
content: Quote from: helius on April 27, 2017, 03:32:40 amI'm not sure what to do. I'm sure there are bugs here, but I don't know enough about Verilog to know where they are. Can you look at this code and give me guidance?My goals are two-fold using a 40 MHz clock:#1 -- With a 10 clock cycle, use the first 255 cycles to write 255..0 to addresses 0..255,#2 -- Afterward, respond to two input buttons displaying the address go up by 1 on up, down by 1 on down) and display the data there on the LEDs.https://pastebin.com/peMX8avpWhen I synthesize I get:Code:35935014 WARNING - c:/lattice/sram/top.v(126): Register \sramscope/operation_49 is stuck at One. VDB-501435935013 WARNING - c:/lattice/sram/top.v(93): Register \sramscope/ldata_65__i0 is stuck at Zero. VDB-501335935013 WARNING - c:/lattice/sram/top.v(126): Register \sramscope/leds_i1 is stuck at Zero. VDB-50131166052 WARNING - logical net 'up_c' has no load.1166052 WARNING - logical net 'dn_c' has no load.I haveupanddnset to UP, and everything else set to UP except l[7:0] (LEDs) which are set to DOWN.My working K.I.T.T. project is here. I use the same settings for the buttons and LEDs on that one as I do in this project:https://pastebin.com/U107VJJbAny help would be appreciated. I'm kind of stuck until I learn what I don't currently know.Thank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: April 30, 2017, 12:25:30 am
content: I have purchased two books which teach Verilog to help me.Thank you,Rick C. Hodgin

author: ale500
author_rank: Frequent Contributor
timestamp: May 03, 2017, 04:45:43 am
content: Just some comments:writeis not being restored to 0, so it will be stuck at 1. The leds are assigned with a blocking assignment inside a clocked always block, I find it hard to justify not using a non-blocking assignment (<=).I'd just simulate with icarus verilog or similar before I go to synthesis, it helps you along the development path. The Lattice Diamond software comes with another simulator Active HDL, not very difficult to use either.The examples at fpga4fun are a nice starting point, I'd suggest you go through them, they teach you with working examples many basics and how to build up with them, in verilog.

author: RickCHodgin
author_rank: Contributor
timestamp: May 06, 2017, 07:34:08 pm
content: I'm having trouble figuring out in Verilog syntax on how to read and write data to the SRAM data ports, and how to design the inputs and outputs.To help me understand, could somebody post an example which writes data to SRAM from addresses 0x00 to 0xff using values 0xff to 0x00, and then reading the data back from it starting at 0x80, using two buttons, one to increase address, one to decrease address, with the value read from memory having its bits displays on the on-board LED?I've been trying to write this, but I can't figure out how to do it in Verilog. Here's my current attempt. It won't compile, and it contains notes about my thinking here and there:https://pastebin.com/CVr0ed8EI appreciate any help.Thank you,Rick C. Hodgin

author: Buriedcode
author_rank: Super Contributor
timestamp: May 06, 2017, 09:28:04 pm
content: It appears you are writing verilog as you would 'code' for a micro. That isn't what verilog is, although it is designed to be a bit more "C-like" than VHDL. Even so,that belies the fact it is still a hardware description language.'Code' for the most part, is sequential instructions for specific hardware that is somewhat abstracted from that hardware. Eg: Variable = 0xFF; That places 255 in variable, but it doesn't say *how* to do that.HDL's require you to assign registers, IO's, and 'wires' and specify the behavior of these based either on a clock, or combinatorial - such asCode:assign y = (sel) ? b : a;Are you trying to read/write to/from embedded block ram (EBR) inside the device? or an SRAM chip connected externally? Internal SRAM blocks tend will have their specific 'ports' for which I'm sure there are verilog examples. (they will be the obvious, address, data, read enable, write enable, chip select etc..). External SRAM is only slightly trickier. Both would most likely require a state machine.I'll admit, for something seen as 'basic' by many, I too had trouble finding verilog examples for SRAM. I ended up having to start completely from scratch, which forced me to think about it, and helped me learn. If you are still struggling, and its for external SRAM, I'll post a verilog snippet I made years ago. It won't have the functionality you want, as in incrementing and decrementing address based on buttons, its just a module for hooked up external SRAM to internal busses.

author: RickCHodgin
author_rank: Contributor
timestamp: May 06, 2017, 09:36:37 pm
content: Quote from: Buriedcode on May 06, 2017, 09:28:04 pmI am using the Lattice XP2 Brevia2 dev kit:http://www.latticesemi.com/latticexp2-breviaI was under the impression that the SRAM ports defined on the board (data0..7 = 1,2,5,6,7,8,9,10, address0..16 = 119, 120, 121, 122, 123, 124, 125, 127, 129, 130, 131, 132, 133, 134, 137, 138, 141, chip select = 142, output enable = 143, and write enable = 144) was the same as the EBR, but that it was a real SRAM chip.QuoteI believe that's what I'm trying to use, but I can't figure out how to "multiplex" the data pins. I presume I need an inout, but how does that work? I will assign at some point when I'm writing, and otherwise use 8'bZ or 8'bX so it's not connected when not writing?QuoteIt would be great to see the example. I believe I understand everything in concept, but I am having difficulty translating thought into the mechanics of Verilog syntax.UPDATE:I have just found this link which demonstrates the use of an inout. It has a flag indicating when data is put onto the wire, and when not use N'bZ for the value:inout example on altera.comThank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: May 06, 2017, 09:54:33 pm
content: Let me ask another question.I've seen something today called a Dragon Board (http://www.knjn.com/ShopBoards_PCI.html) which uses an FPGA attached to a PCI bus, and another model which connects to a PCI-Express bus. I am wondering if it would be possible to create a board like that which responds to address and data on the PCI bus to receive commands, and then simply respond to those to carry out functions? It would also be able to read data and allow it to be queried by software running on a standard PC.The PCI bus runs at 33 MHz, PCI-X at 133 MHz or faster. Would my Lattice FPGA run decently at that speed? It has a 400 MHz max clock (that I've been able to try out on the Diamond software thus far). If I could get an interface card which plugged into a PCI bus slot, and communicate there it would greatly simplify what I'm trying to do by having a piece of hardware I could send commands to, write memory ranges to, handling specialized operations which then translate into data reads/writes for my software.It would seem to greatly simplify a great many things in communication between a host computer and custom hardware.If not, I also have an Altera Cyclone V dev board with a 160-pin breakout daughter-board which could be used to communicate with the PCI or PCI-E bus.Thank you,Rick C. Hodgin

author: ebclr
author_rank: Super Contributor
timestamp: May 15, 2017, 12:20:17 pm
content: In Lattice word the board to play with for pciexp is this onehttp://www.mouser.com/ProductDetail/Lattice/LFE5UM5G-45F-VERSAPROMO/?qs=sGAEpiMZZMurtJ7VwBTl0T0d2L4lJyrxBmx7pcOirvJOI7ilfBIH3g%3d%3d

author: RickCHodgin
author_rank: Contributor
timestamp: May 15, 2017, 12:51:17 pm
content: Quote from: ebclr on May 15, 2017, 12:20:17 pmThank you! Exactly what I'm looking for.- Rick C. HodginUPDATE:Ordered. Thank you again.

author: ebclr
author_rank: Super Contributor
timestamp: May 15, 2017, 06:56:33 pm
content: Take special attention to the SERDES Test SMA Connectors, those will bring you to very big data transfers

author: RickCHodgin
author_rank: Contributor
timestamp: May 18, 2017, 12:43:24 am
content: It arrived today. I won't be able to begin coding for it until Saturday.Do you have any examples of code which allow me to send / receive data to / from the card? I presume I would code the FPGA to monitor data addresses and mirror those writes to on-board DDR3, and reads from on-board DDR3.Thank you,Rick C. Hodgin

author: ebclr
author_rank: Super Contributor
timestamp: May 18, 2017, 01:19:42 am
content: Read the docs, several samples are available, and also pc host software.This board need a lot of time and effort, But is well documented and a lot of samples is available, go step by step

author: RickCHodgin
author_rank: Contributor
timestamp: May 18, 2017, 01:26:02 am
content: Quote from: ebclr on May 18, 2017, 01:19:42 amI have been reading through them. It's hard for me because I have dyslexia. It makes the translation from printed text to thought very difficult. I do better hearing and seeing example tutorials given by people.Thank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: May 18, 2017, 02:26:30 am
content: In looking for video tutorials tonight, I came across this gem. It certainly does "It's All About The Pentiums" one better.LOLing. :-)Thank you,Rick C. Hodgin

author: ebclr
author_rank: Super Contributor
timestamp: May 18, 2017, 11:55:36 am
content: Without reading capability will be a tough challenge due to the complexity of this board, Did you try to use a narrator ?

author: RickCHodgin
author_rank: Contributor
timestamp: May 18, 2017, 12:21:25 pm
content: Quote from: ebclr on May 18, 2017, 11:55:36 amI have used several. :-) I also sometimes record me reading text into an app, and then play it back. I get 10x the comprehension when I am able to hear it over reading it.But, I'm finding several videos on ECP2, and ECP3 which show installation of the software. I think I have a handle on where to start.Does the software come with PC source code for the scatter/gather app? And other apps? In addition to the Verilog / FPGA source code?Thank you,Rick C. Hodgin

author: ebclr
author_rank: Super Contributor
timestamp: May 18, 2017, 10:59:10 pm
content: Kit content downloadhttp://www.latticesemi.com/Products/DevelopmentBoardsAndKits/ECP55GVersaDevKit.aspxIf you wanna take full access you need to buy some extra thingsIntellectual Property Connectivity IP Suite Connectivity IP suite includes commonly used interface IP cores such as PCI Express, CPRI, JESD204B, DDR3 controller, Gigabit Ethernet MAC etc. $995 $99 Buy NowLattice Diamond Design Software Lattice Diamond Software Leading edge design software for Lattice FPGA families with an easy-to-use interface, superior design exploration, optimized design flow and more. $895 $99 Buy Now

author: RickCHodgin
author_rank: Contributor
timestamp: May 18, 2017, 11:12:03 pm
content: Quote from: ebclr on May 18, 2017, 10:59:10 pmHow long is the promo? Through May 31?UPDATE:"To help you accelerate your designs, we are extending the pricing promotion to the Connectivity IP Suite and the latest Lattice Diamond Software. Take advantage of this great offer before it expires on June 30, 2017 or while supplies last. "The documentation stated demo licenses come with the kit, allowing for four hours of use before bricking the IP portions ... if I read it correctly.Also, a full use Diamond software comes with the kit ... again, unless I am mistaken. Am I mistaken [crosses fingers] ?Thank you,Rick C. Hodgin

author: ale500
author_rank: Frequent Contributor
timestamp: May 19, 2017, 04:29:57 am
content: I thought the board (ECP5-5G) was 99 and the Diamond for that board for 1 year was 99.

author: RickCHodgin
author_rank: Contributor
timestamp: May 19, 2017, 08:48:47 am
content: Quote from: ale500 on May 19, 2017, 04:29:57 amYou may be right. I see here where it's only a limited time offer:"Diamond Free License - for the ECP5-5G Versa Development Kit Only"If you currently do not have access to the award-winning Lattice Diamond design software (version 3.8 or later), Lattice would like to offer you a special 1-year license, that enables design for the ECP5UM5G-45F FPGA used on the ECP5-5G Versa Board. To request this license, please follow instructions included with your ECP5-5G Versa Development Kit. Please note that this license is valid for Diamond design software (version 3.8 or later) and can be used only with the ECP5-5G Versa Development Kit. This is a limited-time offer."Thank you,Rick C. Hodgin

author: RickCHodgin
author_rank: Contributor
timestamp: May 19, 2017, 08:59:44 am
content: Continued on thread:https://www.eevblog.com/forum/microcontrollers/help-with-getting-started-on-ecp5-5g-versa-development-kit/Thank you,Rick C. Hodgin