Microchip EERAM - Page 1
Forum section: electronics / general

author: Jeroen3
author_rank: Super Contributor
timestamp: December 06, 2016, 10:16:24 am
content: So, today I found out that Microchip has made EERAM. Which is a combination of I2C SRAM and EEPROM with wear leveling and automatic write/read.I can only find these from Microchip, which is a significant risk. Has anyone used them before?Something also tells me these are just mask-rom PIC's.http://ww1.microchip.com/downloads/en/DeviceDoc/20005371C.pdf

author: wraper
author_rank: Unknown
timestamp: December 06, 2016, 10:27:23 am
content: Quote from: Jeroen3 on December 06, 2016, 10:16:24 amNo chance for that. Doing so would be impossible at given specs, and just plain stupid and expensive. Moreover there is a backup power pin.EDIT, not a single word about wear leveling in that datasheet.

author: bktemp
author_rank: Super Contributor
timestamp: December 06, 2016, 10:27:49 am
content: Similar devices have been around for a long time. Xicor has some non volatile static ram devices.

author: Jeroen3
author_rank: Super Contributor
timestamp: December 06, 2016, 10:42:30 am
content: Xicor seems to have found the markets of eternity though.The backup pin would be a challenge on a PIC indeed.

author: Wilksey
author_rank: Super Contributor
timestamp: December 06, 2016, 10:45:35 am
content: Looking at their history of "EOL" products, I should imagine that Microchip was one of the least risky companies surely?

author: ebclr
author_rank: Super Contributor
timestamp: December 06, 2016, 11:43:02 am
content: Let's educate user wrapper" just plain stupid and expensive. "Be polite, try to be courteous you are always so aggressive, the owner of the truth, do not compensate your small toy on the forum, all other readers will say thank you

author: AndyC_772
author_rank: Super Contributor
timestamp: December 06, 2016, 11:48:06 am
content: Wear levelling is hardly required if the EEPROM is only written when the chip powers down.

author: timb
author_rank: Super Contributor
timestamp: December 06, 2016, 12:25:20 pm
content: Cypress has a similar technology they call nvSRAM. It's basically a sort of SRAM/Flash hybrid. When power is removed, the contents of SRAM will instantly be shadowed to the SONOS array. It is then read back out to SRAM on power up.These type of parts are designed to replace Battery Backed SRAM. Though, be aware that when replacing traditional SRAM with one of these types of devices, the SRAM isn't ready immediately on power up. There's generally a small delay (a few ms, maybe more, maybe less, depending on the part).Anyway, the Cypress nvSRAM works very nicely. I've used one of their first generation parts to replace the BBSRAM that held calibration data in an quantity of legacy equipment for a company, and it's worked flawlessly.FRAM is another alternative that doesn't involve any "Copy on Power Loss" operations like the nvSRAM and EERAM parts do. FRAM is basically just as fast as SRAM and can inherently retain data without power. It has a write endurance approaching trillions of cycles. I've used some of Cypress' FRAM parts as well (once for BBSRAM replacement in an old scope and a couple of times in new projects) and it's *very* nice.Personally, I trust FRAM more than nvSRAM/EERAM, because it's been around for awhile and thus has a decent track record.

author: coppice
author_rank: Super Contributor
timestamp: December 06, 2016, 12:25:39 pm
content: Why would anyone choose a device like this over the FRAM I2C EEPROM lookalikes from RAMTRON? They've been around for years, and are used in high volume. Used at 3.3V you couldn't write enough times to wear one out in any realistic product life.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: December 06, 2016, 01:06:46 pm
content: Quote from: coppice on December 06, 2016, 12:25:39 pmMore package options ?Quick DK search shows no TSSOP options among alternate FRAM parts.

author: daveshah
author_rank: Unknown
timestamp: December 06, 2016, 01:14:39 pm
content: Quote from: coppice on December 06, 2016, 12:25:39 pmI suppose FRAM ICs have the downside of destructive reads (wasn't there a thread about brownouts causing data loss a while ago); OTOH it's foreseeable a power glitch could cause these devices to fail to store and lose SRAM content, losing any changes made since the last store.

author: coppice
author_rank: Super Contributor
timestamp: December 06, 2016, 01:15:10 pm
content: Quote from: coppice on December 06, 2016, 12:25:39 pmIt looks like Cypress now own RAMTRON, so the Cypress FRAM parts are actually the RAMTRON ones.

author: coppice
author_rank: Super Contributor
timestamp: December 06, 2016, 01:20:42 pm
content: Quote from: daveshah on December 06, 2016, 01:14:39 pmNobody can really build any kind of FRAM device without allowing for this issue. There is a chunk of circuitry on every FRAM device I know of, called the anti-tearing module. This stores enough energy on the chip to complete a read and rewrite cycle before any cycle is allowed to be initiated. Have you ever seen one of the EEPROM look-alikes corrupt its data, even under severe attack by EMI destabilising the supply rails?

author: Jeroen3
author_rank: Super Contributor
timestamp: December 06, 2016, 02:10:30 pm
content: I have indeed designed in an FRAM from Cypress already. Unfortunately EERAM is not spi yet. If it was, it could have been a candidate.This topic is pure from interest. So far no users though?

author: David Hess
author_rank: Super Contributor
timestamp: December 06, 2016, 06:54:43 pm
content: FRAM is not a direct replacement for parallel EEPROM or SRAM in some applications because it requires a precharge cycle for every read access.

author: Jeroen3
author_rank: Super Contributor
timestamp: December 06, 2016, 07:06:38 pm
content: The FRAM does not show any of it's limitation to the user. It's command-address-write, done. No latency or wait states. I like it.We'll see how it performs in the field in a year.

author: AndyC_772
author_rank: Super Contributor
timestamp: December 06, 2016, 07:30:38 pm
content: Could it have an equivalent block of SRAM that holds a shadow copy of the FRAM data? That would allow reads to happen non-destructively and writes to happen in the background.

author: coppice
author_rank: Super Contributor
timestamp: December 06, 2016, 07:32:44 pm
content: Quote from: AndyC_772 on December 06, 2016, 07:30:38 pmYou would need to load the RAM from the FRAM at startup, and you would need to protect against corruption then. What would be the benefit? If you don't have absolutely rock solid anti-tearing logic, you really don't have a viable product with FRAM.

author: Benta
author_rank: Super Contributor
timestamp: December 06, 2016, 08:50:01 pm
content: NVSRAM has been around for ages, originally from Simtek and ZMD (20 years or more ago).Basically, each bit is an SRAM/EEPROM combo. When powering up, the EEPROM content is transferred to the SRAM cells, when powering down the opposite happens. This all happens in one go as parallel bit-to-bit copy.It's a perfect replacement for the (now mostly obsolete) NVRAMs, you know, the SRAMs with a piggy-back battery.Only downside is, the device needs an external capacitor to provide programming energy when powering down (might be that never devices have the cap internally).Cypress is the main supplier today, but the Microchip parts seem to be the same.FRAM is newer, and is a non-volatile drop-in replacement for SRAM. Suppliers are Cypress and Fujitsu. There is no "mirror SRAM" or something like that, the bits are like normal SRAM cells, but with FRAM storage capacitors that keep their state after power-down.These are true NVRAM/SRAM drop-in replacements.Both NVSRAM and FRAM have access times like normal 32K x 8 or whichever size SRAMs.

author: David Hess
author_rank: Super Contributor
timestamp: December 07, 2016, 04:07:20 pm
content: Quote from: Benta on December 06, 2016, 08:50:01 pmThe ones I bought from Cypress a couple years ago were still marked with the Simtek logo despite having a 2013 date code. Cypress stopped producing DIP parts a couple years ago and I am surprised nobody makes a SOIC to DIP adapter with any needed support circuits; demand must be low.I do not think the issue with requiring an external capacitor was ever a big deal because they were available with internal capacitors early on; the annoying thing about the ones which require an external capacitor is a slightly different pinout to accommodate the extra pin. The ones with internal capacitors have some limitations however on how quickly the supply voltage drops but I doubt many systems would have a problem with this.These parts really are amazing and I am surprised they were not more popular than the various embedded lithium backed up SRAMs.QuoteFRAM is not a drop-in replacement for parallel SRAM in all cases. It has special access requirements to handle precharge for read operations which lead to it not operating asynchronously:After the address has been latched, the address value may bechanged upon satisfying the hold time parameter. Unlike anSRAM, changing address values will have no effect on thememory operation after the address is latched.andThe pre-charge operation is an internal condition in which thememory state is prepared for a new access. All memory cyclesconsist of a memory access and a pre-charge. Pre-charge isuser-initiated by driving the CE signal HIGH. It must remainHIGH for at least the minimum pre-charge time, tPC.The user determines the beginning of this operation since apre-charge will not begin until CE rises. However, the device hasa maximum CE LOW time specification that must be satisfied.So unlike a parallel asynchronous SRAM, a FRAM must have its CE line toggled for every access. The floating gate based nvSRAMs have no such requirement and operate just like SRAMs.

author: tszaboo
author_rank: Super Contributor
timestamp: December 07, 2016, 04:38:30 pm
content: Quote from: Jeroen3 on December 06, 2016, 02:10:30 pmIt came out, like few weeks ago.Probably it is going to be a lot cheaper than FRAM though.

author: coppice
author_rank: Super Contributor
timestamp: December 07, 2016, 05:24:56 pm
content: Quote from: NANDBlog on December 07, 2016, 04:38:30 pmThat would depend on the size. Small FRAM parts are very cheap. They require no bulky charge pump on the chip, as a flash part does. As the memory size increases the charge pump overhead decreases, and the smaller cell of the flash wins out. When you add RAM alongside the flash I doubt it would ever compete with FRAM.

author: Benta
author_rank: Super Contributor
timestamp: December 07, 2016, 08:22:24 pm
content: David, I understand what you are saying here:QuoteThis is true. FRAM does not support the "Address Controlled Read Cycle" that older SRAMs accept, but only the CE/OE cycle.That's not a bad thing in my opinion, and a problem that is virtually nonexistent. Which design would keep CE active and address a device willy-nilly?The only one that comes to mind is a PROM-lookup type of circuit.Everywhere else, I'd expect an address decode per cycle with subsequent CE/OE generation. Anything else would be bad design.Cheers.

author: bktemp
author_rank: Super Contributor
timestamp: December 07, 2016, 08:40:48 pm
content: Quote from: Benta on December 07, 2016, 08:22:24 pmKeeping CE\ low while accessing multiple addresses is fairly common.Most devices toggle RD\ (OE\) each cycle, but some of them do not, especially when doing burst reads:Because OE\ has to go high-low-high, it has the highest frequency and lowest pulse duration. So keeping OE\ low allows a higher data rate.Therefore you occasionally see designs keeping CE\ + OE\ low while cycling through the adresses. But you probably wouldn't do it for something you would use FRAMs for. This will be used most likely on highspeed SRAMs.

author: AndyC_772
author_rank: Super Contributor
timestamp: December 07, 2016, 08:41:31 pm
content: Back in the day, I built a device from a kit which allowed the range of colours displayed by a BBC Micro to be expanded.The 'beeb' had a digital TTL video output, ie. one bit each for red, green and blue, giving a palette of 8 colours.To allow different colours to be shown on a compatible monitor, the device used the digital RGB signal to drive the address bits of a small capacity SRAM chip. The data outputs from the SRAM fed DACs for each channel, giving an analogue RGB signal that could show a much wider range of colours.I no longer have a schematic, but I can easily imagine that the SRAM's CE was permanently enabled, and the data outputs simply changed in time with the video signal.

author: Benta
author_rank: Super Contributor
timestamp: December 07, 2016, 08:54:56 pm
content: QuoteYes. But you are talking high-speed synchronous RAMs here.This is about old-fashioned parallel asynchronuos SRAMs.QuoteThat's exactly what I meant when I referred to a "PROM-lookup type of circuit". And in your "beeb" extension it was probably a PROM, not an SRAM.All that aside, the normal application for an asynchronous-interface parallel FRAM would not differ from an SRAM. That was my point.Cheers.

author: bktemp
author_rank: Super Contributor
timestamp: December 07, 2016, 09:12:25 pm
content: Quote from: Benta on December 07, 2016, 08:54:56 pmNo, I am talking about high-speed asynchronous SRAMs.One example of a microcontroller using this type of bus cycle I know offhand is PIC24FJ256DA210 when external SRAM is being used for its build in display controller.http://ww1.microchip.com/downloads/en/DeviceDoc/39730B.pdfpage 46It keeps RD active (shown as active high in the example waveform) while reading a burst of 3 bytes, transferring 1 byte per clock cycle.It also supports the conventional bus cycle with RD\ being pulsed once per access, but it is much slower.

author: Benta
author_rank: Super Contributor
timestamp: December 07, 2016, 09:42:50 pm
content: Yes. Well. Right. That's of course a typical application for a 100 ns SRAM or FRAM.'Nuff said.