Mojo V3 FPGA Blinker not working - Page 1
Forum section: electronics / general

author: CM800
author_rank: Frequent Contributor
timestamp: May 29, 2016, 08:06:14 pm
content: I brought a Mojo V2 a while back and I've only just got around to playing with it, now I've been following through the tutorial on theMojo websiteNow, I managed to get the input / Reset button working just fine in terms of turning a switch on and off, along with some other small things (turning on a number of the LEDs using a constant value)However I can't get their blinker demo working at all, I have copied the code in exact, put it in the correct folders and compiled and uploaded without problem, all that happens is there are no LEDs on (except the ready LED as to be expected with an uploaded program.)I have no clue at all why it is not working... and it is really starting to put me off.Does anyone have any suggestions and thoughts, really appreciate it. Thanks!

author: hamster_nz
author_rank: Super Contributor
timestamp: May 29, 2016, 09:26:29 pm
content: As well as you LEDs, do you have your clock pin defined in your UCF file? (I've forgotten to do this a few times....)Also double-check your Pinout report and verify that the correct signals have been connected to the correct pin.

author: CM800
author_rank: Frequent Contributor
timestamp: May 29, 2016, 09:43:57 pm
content: Quote from: hamster_nz on May 29, 2016, 09:26:29 pmI'm using the UCF file provided by the Mojo board team. I have a suspicion that the clock isn't working as I tried measuring it with my scope with no success... but I could be wrong.This is a devboard with minimal / no use.

author: hamster_nz
author_rank: Super Contributor
timestamp: May 29, 2016, 10:20:01 pm
content: Can you post the lines with the clock signal constraints? It might just be that they are commented out..

author: CM800
author_rank: Frequent Contributor
timestamp: May 29, 2016, 11:29:00 pm
content: Quote from: hamster_nz on May 29, 2016, 10:20:01 pmIs this what you want?UCF:Code:#Created by Constraints Editor (xc6slx9-tqg144-3) - 2012/11/05NET "clk" TNM_NET = clk;TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;# PlanAhead Generated physical constraintsNET "clk" LOC = P56 | IOSTANDARD = LVTTL;NET "rst_n" LOC = P38 | IOSTANDARD = LVTTL;NET "cclk" LOC = P70 | IOSTANDARD = LVTTL;NET "tout" LOC = P1 | IOSTANDARD = LVTTL;NET "led<0>" LOC = P134 | IOSTANDARD = LVTTL;NET "led<1>" LOC = P133 | IOSTANDARD = LVTTL;NET "led<2>" LOC = P132 | IOSTANDARD = LVTTL;NET "led<3>" LOC = P131 | IOSTANDARD = LVTTL;NET "led<4>" LOC = P127 | IOSTANDARD = LVTTL;NET "led<5>" LOC = P126 | IOSTANDARD = LVTTL;NET "led<6>" LOC = P124 | IOSTANDARD = LVTTL;NET "led<7>" LOC = P123 | IOSTANDARD = LVTTL;NET "spi_mosi" LOC = P44 | IOSTANDARD = LVTTL;NET "spi_miso" LOC = P45 | IOSTANDARD = LVTTL;NET "spi_ss" LOC = P48 | IOSTANDARD = LVTTL;NET "spi_sck" LOC = P43 | IOSTANDARD = LVTTL;NET "spi_channel<0>" LOC = P46 | IOSTANDARD = LVTTL;NET "spi_channel<1>" LOC = P61 | IOSTANDARD = LVTTL;NET "spi_channel<2>" LOC = P62 | IOSTANDARD = LVTTL;NET "spi_channel<3>" LOC = P65 | IOSTANDARD = LVTTL;NET "avr_tx" LOC = P55 | IOSTANDARD = LVTTL;NET "avr_rx" LOC = P59 | IOSTANDARD = LVTTL;NET "avr_rx_busy" LOC = P39 | IOSTANDARD = LVTTL;

author: hamster_nz
author_rank: Super Contributor
timestamp: May 30, 2016, 12:01:19 am
content: The reset button is an active low (at least onhttps://cdn.sparkfun.com/datasheets/Dev/FPGA/mojov3-sch.pdf)Hold the reset button down - does it work?(also, the whole resetting scheme is a minefield - just get rid of it :-) )

author: CM800
author_rank: Frequent Contributor
timestamp: May 30, 2016, 12:07:50 am
content: Quote from: hamster_nz on May 30, 2016, 12:01:19 amI have had the reset button work for turning on and off an LED, now. I re-routed the clock to output on pin one, I haven't had any output on it, equally I tried scoping the clock with no success, I have a feeling the clock might be dead, plus the chip is not the same one shown in the official pictures. I will order a new chip from Digikey when I next have a load of components I need and replace it. I think that is the best course of action.

author: hamster_nz
author_rank: Super Contributor
timestamp: May 30, 2016, 12:17:53 am
content: The Spartan 6 have an on-chip clock that you can press into service in times like this. It can be accessed via the 'STARTUP_SPARTAN6' primative. Here's how you do it in VHDL:Code:STARTUP_SPARTAN6_inst : STARTUP_SPARTAN6port map (CFGCLK => open, -- 1-bit output: Configuration logic main clock output.CFGMCLK => config_clock, -- 1-bit output: Configuration internal oscillator clock output.EOS => open, -- 1-bit output: Active high output signal indicates the End Of Configuration.CLK => '0', -- 1-bit input: User startup-clock inputGSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)KEYCLEARB => '0' -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM));I don't know Verilog, but I assume it is much the same, but with difference syntax.