EEVBlog #543 - PCB VIA Current Investigation - Page 1
Forum section: electronics / general

author: EEVblog
author_rank: Unknown
timestamp: November 03, 2013, 08:40:52 pm
content: Dave tests the myth that plugging a PCB VIA with solder does nothing (or not much) to improve the current handling capability. Is manual wire feed-through any better?Does the industry rule of thumb of 0.5A per VIA have any basis?What is the typical plated VIA/hole thickness?Previous videos on PCB solder coating:Does a PCB VIA halve in resistance like a PCB trace does when coated with solder?

author: walshms
author_rank: Regular Contributor
timestamp: November 03, 2013, 10:05:30 pm
content: You're absolutely right about the plating in the holes and the corners where the hole plating meets the copper on each side of the board; that's a point of increased resistance. And that definitely confirms why the US Air Force insisted on using Z-wires in its wiring specification.They took it a step further, though; the mask around pads was expanded enough to leave a bit of trace exposed, and the wire was bent over against the trace and soldered to it. Resistance drops even more as a result in most cases.

author: sarm
author_rank: Contributor
timestamp: November 03, 2013, 11:06:16 pm
content: Great video Dave thank you.Would it be fun to see what happens when the via or traces are designed under specs for theintended handling current.I really would like to see the avalanche effect, the rise in temp that rises the resistance that willrise the temp of the via and so on, until self destruct.

author: SAI_Peregrinus
author_rank: Contributor
timestamp: November 03, 2013, 11:19:08 pm
content: This is about what I'd expect.Resistance is proportional to cross sectional area. The ring of a via has a much lower cross sectional area than the filled via.Solder isn't as conductive as copper, so putting copper in the middle decreases the resistance. The same goes for steel.

author: free_electron
author_rank: Super Contributor
timestamp: November 04, 2013, 12:10:30 am
content: The solder does make a difference as it fills the tunnel. But... that is not the issue. You have indeed made the tunnel more conductive. You have NOT altered the connection area between trace and the tunnel , and that is where the board will fail at overcurrent !Code:trace trace-tunnel - tunnel - tunnel-trace - trace-------- --------------- --------|____________| |________________|(1) ____________ (3) ________________ (1)| (2) |_______________| (2) |________--------Current handling is determined by CROSS SECTION of a wire.Resistance is LENGTH AND CROSS SECTION dependent.(1) = Base equation : trace width * trace thickness. But !! plated copper is LESS conductive than rolled copper (the base foil)! There is about 8% difference.so the real equation =(Trace width * foil thickness) + (0.92 *(trace width * plating thickness))1 ounce copper PCB starts as 1/2 foil and is grown 1/2 ounce. 1/2 ounce is 17 microns(3) = base equation : circumference of the hole (diameter * PI ) * plating thickness- plating is 1/2 of the trace thickness !- plated copper is 8% less conductive(diameter*pi) * (1/2 * trace thickness * 0.92)So yes, filling this with solder will have a massive impact. The resistance will go down and current handling capability will go up.now comes the hard bitequation (2)you need to compensate for:- the loss due to 1/2 thickness loss when going from trace to via- the increase in resistivity of the plated copperAssuming a 1mm wide trace. To get a 1mm circumference (maintain width) in the hole we need 1mm/pi diameter.So rougly 0.3mm diameter hole.But since our plating is 1/2 thickness and 0.98 we need to double the 0.3mm hole in diameter to offset for 1/2 thickness plating.Then compensate the 8% loss of conductivity and you end up with a required diamter of roughlySo you end up with a 0.7 mm diameter drill hole.This will compensate the half plating and maintain the current handlaing capacility in the handoff from trace to the tunnel.Filling with solder cannot alter the handoff point ! it can only alter the actual tunnel.Now, Here is the real 'GOTCHA' situation.There is a massive difference between current handling capability of a VIA and a COMPONENT PIN !The plated pad having a component pin installed and soldered will solve the tunnel resistance.The fillets formed due to correct soldering both at top and bottom will eliminiate the handoff resistance.Code:--------------| |-==============| |=| || || |=| |==========-| |----------= : foil- or | : plated copperyou can fill the tunnel but you cant alter the contact SURFACE between trace and tunnel (equation 2)if you stick a wire in the hole and flood it with solder you get this :Code:""""/""""\/ """" \ < solder fillet top/ """" \--------------|""""|--==============|""""|==|""""||""""||""""|==|""""|==========--|""""|----------\ """" /\ """" / < solder fillet bottom\""""/""""""""So those are NOT a problem. The solder fillet increases the HANDOFF point ( equation 2) and the component pin and flooded tunnel solve the current problem.Now, we go look at a real VIA.- there is no component pin !- typical VIA's can't be flooded ! They are capped with solder resist ! there is also no tin plating in them left by the process.so equation (2) is very much in effect !How do we solve this ? Here is the rule in effect :ANY current handlingvia should be leftuncovered(not tented) so that during wave soldering the via WILL be filled with solder. An ample opening around the hole in the soldermask needs to be maintained so that the capillary effect can properly form a fillet both top and bottomThen, and only then can you apply the 2/pi * trace width formula to make a proper via in relation the trace width.Now, there are other factors.The area from foil to plated copper is a mechanical stress point. For boards under lots of warp or flex or vibration it is recommended not to trust the plating to hold out. Micro cracks may form over time. that is why , for mission critical stuff like avionics they recommend z-wires or copper turrets(pres-fit) to be inserted and soldered both sides.If you take a look at a modern PC motherboard you will find examples of power via's that have been filled during wave soldering in the power convertor around the processor. other (signal via's) are simply tented with soldermask and left alone.for hobby stuff you don't really care .. if you are messing around with high reliability stuff like automotive it DOES matter.

author: NiHaoMike
author_rank: Super Contributor
timestamp: November 04, 2013, 12:16:30 am
content: Quote from: sarm on November 03, 2013, 11:06:16 pmI had some high power vias blow like fuses and start arcing on a grid tie inverter board (senior design project). The resulting bang (just one high voltage capacitor discharging into another, nothing actually damaged) scared away a team member, at which point I had to convince her that everything was alright.The funny part was that ordinarily, the vias would be more than capable of carrying the current. It was just that Texas A&M's bad PCB service plated a really thin layer that happened to test fine with a multimeter, but couldn't handle much current.

author: robrenz
author_rank: Super Contributor
timestamp: November 04, 2013, 12:32:49 am
content: Excellent video Dave!Excellent additional comments Vincent!

author: timb
author_rank: Super Contributor
timestamp: November 04, 2013, 12:56:12 am
content: Very informative and about the results I'd have expected.What are some other tools similar to Saturn PCB?

author: kevinpt
author_rank: Contributor
timestamp: November 04, 2013, 01:54:17 am
content: I believe the common "wisdom" that wires are needed is aimed at unplated holes typically used by hobbyists making their own boards. In that case there is a risk of not making a connection due to voids or contaminants if you use solder alone to try and plug the hole.

author: Synergy Hub
author_rank: Newbie
timestamp: November 04, 2013, 03:23:44 am
content: Thanks Dave for a great presentation. Right on the mark with some current questions we were posing here ourselves for a project. Between your video and the( golden )mention of the Saturn PCB, we have answers and another tool ( software ) to use.

author: carlpj
author_rank: Newbie
timestamp: November 04, 2013, 04:56:17 am
content: I assume the resistor lead you used in the via was copper. Many leads are tinned steel, which would show little difference from solder filling since the conductivity of steel and 60/40 solder are about the same, and about 12% of copper’s conductivity. That is a good reason to use only copper wire for links and filling vias.

author: EEVblog
author_rank: Unknown
timestamp: November 04, 2013, 05:36:28 am
content: Quote from: free_electron on November 04, 2013, 12:10:30 amHow can it have no effect on that?The solder doesn't magically just go inside the tunnel and nowhere else, it's on the top of the untented via/pad/trace too, and going over the edges.So you will always have some solder plating thickness over the edge of the hole, and usually the solder will bulge out a bit too. This all improves the current handling of the trace/pad to turret current handling capability.

author: Mafketel
author_rank: Newbie
timestamp: November 04, 2013, 07:47:59 am
content: the steel and the solder have about the same order of magnitude resistance, the only reason why you see a decrease in the resistance in this experiment is because of lowering the resistance at the thinnest point (the pad to solder area there are some nice ASCII drawings above here)If you would use a copper wire it should improve more.Also remember that normally vias do not have nice wide solder pads on top to make a good connection so it might limit the success you can obtain. And of course there is the trace to and from the via

author: EEVblog
author_rank: Unknown
timestamp: November 04, 2013, 11:53:06 am
content: Quote from: Mafketel on November 04, 2013, 07:47:59 amVias that carry any significant current are usually on large traces or fills or some sort, so this generally is not an issue.If your via pad diameter is bigger than your trace to it, and it's being used for power where you have to worry about this stuff, then you aren't doing it right!

author: kayvee
author_rank: Regular Contributor
timestamp: November 04, 2013, 12:29:38 pm
content: Thanks Dave, very interesting video indeed.Pretty much in line with what I had expected, of course much nicer to see it somewhat validated in your tests.Oh and of course to add a little credibility to the advice I offered up to Simon in his thread

author: free_electron
author_rank: Super Contributor
timestamp: November 04, 2013, 12:44:09 pm
content: Quote from: EEVblog on November 04, 2013, 05:36:28 amIf your soldering process is under perfect control it will i deed bulge both top and bottom, but it is not a guarantee.IPC recommends not to rely on that alone. Oversize the hole.There was an article in PCB magazine a while ago on this. I'm trying to find it.On large current traces it is actually recommended to drop down multiple vias, creating more handoff area that what would be required. But this is purely because of mechanical concerns. Under mechanical stress the via plating may shear off. Empirical data has shown that the cracks typically happen on the rolled copper to plated copper barrier.Rolled copper lays horizontally. You grow plating on top and sideways. So the shear point is if you go down in the tunnel at the point where the vertical plating transits from rolled copper to the dielectric material. That is a fragile point.Again, if you flood it with solder : problem solved. Solder is a soft material and will withstand vibration better than the hard copper plating in the tunnel.Most microcracks happen during reflow. Improperly conditioned boards, poor temperature control and the via's will popcorn or microcrack.It is all about long term reliability.A real pad is self solving due to the component pin and solder fillets.A signal via (tented) is not a problemA power via should NEVER be tented so solder can enter and solve the mechanical problem , but do not rely on the solder to solve the handoff problem. You have no control over the end process. As a PCB designer it is your task to make the layout post process independent. So oversize power via's , plonk multiple down , remove tenting. Even if back end screws up , it will still meet requirements. It can only be better than minimum required.Never rely on back end processing to solve a design problem.

author: EEVblog
author_rank: Unknown
timestamp: November 04, 2013, 01:04:18 pm
content: Quote from: free_electron on November 04, 2013, 12:44:09 pmOf course. But it's not going to be zero as you implied. You are at least going to get one side, and in most cases the other side. In fact I don't recall ever not seeing a via that didn't have solder come up over the top side by wicking action. But yes, it could happen of course. But to all of them?QuoteOf course, that is standard practice. If you are just relying on one via for power stuff, you are doing it wrong.So multiple via automatically give you redundancy on any feed-through issues with one getting missed for example.If you are so on the margin that you can't tolerate say 1 of 5 vias not being filled with solder on one side, then you've got your calculations and design margins wrong.QuoteOf course, that's another given. If you are tenting your vias that you intend to be solder filled, then you are doing it wrong.QuoteYes, these are all basic practice for power stuff.QuoteSure, but that's not what solder filling is for (or shouldn't be for).It's primarily a manufacturing tolerance and reliability problem. i.e. via plating thickness & connection to layer has tolerance and is not 100% tested. Going for soldering filling is an often used insurance against any plating manufacturing issues. Not to mention the extra reliability of course.

author: ConKbot
author_rank: Super Contributor
timestamp: November 04, 2013, 02:19:13 pm
content: Quote from: carlpj on November 04, 2013, 04:56:17 amThat resistor looked rather beefy, so the lead was most likely copper. 1/8 and 1/4 W resistors are generally steel leads, but once you get into chunky resistors like that ,the leads are then copper for current handling capability.

author: u271D
author_rank: Contributor
timestamp: November 04, 2013, 04:01:02 pm
content: In the video you talked about the Saturn toolkit using IPC-2221, from there site they say "...IPC-2221 formula are now obsolete!!!" and they now use IPC-2152 "conservative" chart since version 4 of the tool kit.Any significant difference between the two?

author: Carrington
author_rank: Super Contributor
timestamp: November 04, 2013, 04:03:11 pm
content: Anyone know why this happens?Link:https://www.eevblog.com/forum/projects/polar-si9000e-and-sarturn-pcb/msg318336/#msg318336

author: LaurenceW
author_rank: Frequent Contributor
timestamp: November 04, 2013, 04:17:20 pm
content: Interesting. I guess that, for production purposes, you'd be stuck with Lead Free Solder (taste-free beer?), but I would be interested to see if there is any significant different between lead free, lead, or even silver solder (although the last one is getting a bit esoteric, admitedly).

author: Monkeh
author_rank: Super Contributor
timestamp: November 04, 2013, 04:33:29 pm
content: Quote from: LaurenceW on November 04, 2013, 04:17:20 pmTin is a better conductor than lead.

author: free_electron
author_rank: Super Contributor
timestamp: November 04, 2013, 04:46:57 pm
content: Quote from: u271D on November 04, 2013, 04:01:02 pmIPC2221 is the general standard on printed board design Dated 1998 ...IPC2152 is the Standard for determining current carrying capacity in PCB design Dated August 2009Key differences : the cross sectional graph has changed a lot. in some instances the current has been HALVED !in IPC2221 there is only one tableIPC2152 has at least 50 tables. tepending on altitiude, number of layers , small trace adjacent to wide trace , adjacent traces carrying high currents and much more.IPC2221 is based on a single trace with nothing left and right of it running a current.IPC2521 does a whole bunch of scenario's. It has actual thermal plots obatined using IR camera's of what happens in the trce as well as in the via. The handoff area i described in earlier postings here is a clear hotspot.IPC2521 also has guidelines for etched coils ( like for planar transformers etc ).It is much more extensive than a single graph.

author: Mindaugas
author_rank: Newbie
timestamp: November 04, 2013, 06:30:40 pm
content: How about old punch vias. how effect soldier.http://sparks.gogo.co.nz/.tmp/photoserver/full/270x250/exact-size/short-side-scaled/padded/270x250/fff/274392944.jpg

author: walshms
author_rank: Regular Contributor
timestamp: November 04, 2013, 08:01:15 pm
content: Quote from: Monkeh on November 04, 2013, 04:33:29 pmSilver is one of the best conductors.

author: Monkeh
author_rank: Super Contributor
timestamp: November 04, 2013, 08:02:02 pm
content: Quote from: walshms on November 04, 2013, 08:01:15 pmIndeed. It's a tiny percentage of solder, though.

author: ali80
author_rank: Contributor
timestamp: November 04, 2013, 08:25:22 pm
content: Interesting video, thanks DaveHow the temperature rise of the via is calculated? filling out the via may have some effect on heat transfer coefficient of the via. so the temperature rise may be different.and since the via's mass is pretty small probing it with a thermocouple may change the via's temperature.and how much temperature rise would you recommend for a Power supply board without reducing the board life significantly?

author: walshms
author_rank: Regular Contributor
timestamp: November 04, 2013, 08:28:36 pm
content: Quote from: free_electron on November 04, 2013, 12:44:09 pmWell... maybe. If we're going to talk about the mechanical interface, let's don't forget about the ductility of the metal. Even thin layers of copper have ductility, and can withstand some expansion, contraction and flexion. In fact, copper is one of the more ductile metals, and that's one of the reasons (along with its conductivity) that it's the preferred material for wires.Basically, the interface between the "rolled" layer of copper and the plated layer isn't as fragile as I think you believe it to be; the process of plating includes a cleaning step where nearly all of the oxidation is removed from the "rolled" layer before it's plated. The result is a nearly continuous interface. Provided enough copper is plated, there's enough ductility to handle the mechanical interface as long as you're not beating the board to death or trying to fold it, which would indeed place large shear forces across the interface.The only way this would actually become a problem is if the plating was too thin. Most quality manufacturers will plate enough material to obviate that in all but extreme cases. I think the only real problem is that the plating in the via is thinner, and has increased resistivity; the way to obviate that is either to fill the via with solder or use a Z-wire.QuoteIf you're seeing this, your boards weren't sufficiently plated. It simply shouldn't happen if the board is up to snuff. However -- I'll give you this: larger boardswouldbe more susceptible to it, and smaller boards would belesssusceptible to it. A lot depends on the substrate. FR-4 will behave differently than polyimide or PTFE. What we're talking about here is obviously FR-4, but I think you'd be far more likely to see issues with PTFE, and far less likely to see them with polyimide, because of the differences in the thermal expansion coefficient for those materials.My bottom line on it is the same, though -- if you're seeing the sorts of problems you're describing here, you've made an engineering error (not specifying sufficient plating) or your PCB manufacturer has made a production error (not plating sufficient material or not seeding the vias properly for plating.)

author: walshms
author_rank: Regular Contributor
timestamp: November 04, 2013, 08:29:36 pm
content: Quote from: Monkeh on November 04, 2013, 08:02:02 pmNo doubt, but even adding a small amount significantly increases electron mobility.

author: open loop
author_rank: Regular Contributor
timestamp: November 04, 2013, 08:55:57 pm
content: I wonder when putting a leaded component like a resistor in it would act like a heat sink and then would improve the current handling capability of the via. Would it be worth repeating some measurements with the component wires trimmed off.Btw very interesting video as I was not expecting the solder filling to have such an effect..

author: walshms
author_rank: Regular Contributor
timestamp: November 04, 2013, 09:05:51 pm
content: Quote from: open loop on November 04, 2013, 08:55:57 pmThe resistivity of most materials increases with temperature. If it heats up, it will become more resistive, and current will drop. Adding metal would allow you to sink more heat, up to a point, and keep resistivity lower. A trimmed component lead, for example, will reach its thermal capacity sooner than it would if it weren't because there's less surface area to reject the heat to the atmosphere.If you want to seriously start slicing and dicing, however, you have to include the effects of the thermal conductivity of the substrate, the copper traces and other components, convection currents and airflow, yada yada...For the kinds of things we do on a day-to-day basis (i.e., we're not designing high-precision measurement and test equipment) the effects are negligible if you use reasonably good engineering practice and always design in enough margin to absolutely kill dead any of these effects. If you are designing high-precision equipment, you need to consider all of these factors sufficiently to ensure that you're not getting unintended effects.

author: EEVblog
author_rank: Unknown
timestamp: November 04, 2013, 10:12:04 pm
content: Quote from: open loop on November 04, 2013, 08:55:57 pmIt's only 800uW we are talking about here.And given that we had a 2.2C rise without the wire, and resistance has now dropped by maybe 60-70% with the wire, I don't expect the heat sinking to have any major effect on the results. Plus I took the readings pretty quick, not really giving the "heatsink" much time to heat up.

author: lilshawn
author_rank: Regular Contributor
timestamp: November 05, 2013, 04:28:23 am
content: Quote from: EEVblog on November 04, 2013, 10:12:04 pmbut every little bit may have a huge repercussion.then let's blast the bare via with freeze spray and see if that is indeed true. it stands to reason that the voltage across the via increases when the via was heated (before soldering) that the voltage would also reduce if it was simply cooled.you could also test that theory by performing the experiment with a same sized via that also had a large thermal mass like an etched copper "heatsink" on the board that would sink away some of that 2.2 degree delta and change the characteristics of the via current handling.

author: walshms
author_rank: Regular Contributor
timestamp: November 05, 2013, 07:54:28 am
content: Quote from: lilshawn on November 05, 2013, 04:28:23 amThe resistance change should be relatively small, though; at the power Dave is talking about, the heating isn't significant enough to seriously affect the resistivity. A meter with good resolution would probably be able to pick it up. If the delta T were closer to 100C, that would make a big difference, and would be easily measurable.QuoteThat would be a good little experiment; it's something you can do yourself very easily. It would certainly show the opposite effect, but again, it would likely be small. In metals, the resistivity changes are smaller than they would be in, say, a carbon composition resistor.

author: nitro2k01
author_rank: Frequent Contributor
timestamp: November 05, 2013, 11:49:27 am
content: Quote from: lilshawn on November 05, 2013, 04:28:23 amOf course it would, but this experiment is less relevant. The relevance of the increased resistance when the via is being heated, is that it's a positive feedback loop. If you are grossly overloading a via, the increased resistance might cause it to break faster than you would expect without taking this effect into consideration. Exactly how much faster? I don't know.

author: EEVblog
author_rank: Unknown
timestamp: November 05, 2013, 11:55:18 am
content: Quote from: lilshawn on November 05, 2013, 04:28:23 amI doesn't work like that.The changes in resistance from the temperature change was minimal to begin with (you saw it in the video, a few voltage LSD's per second or something). Putting the wire through reduced the resistance heating by maybe 60-70% again.So it's not going to make any difference to the final result.

author: nathanpc
author_rank: Unknown
timestamp: November 05, 2013, 01:39:30 pm
content: Dave, could you share the link to the Google Drive spreadsheet you've created?

author: chat1410
author_rank: Newbie
timestamp: November 05, 2013, 03:04:48 pm
content: This video was posted two weeks after I've completed my first PCB layout for senior design. Due to my inexperience laying out boards, my entire 12 V rail comes from the regulator and through a single via to the rest of the board.I'm anticipating a peak current of 1.5 A for ~20 seconds every now and then (water pump will occasionally spray water). The only negative is that the via will heat up, right? I suppose if it heats up too much, I can scrape away the soldermask, jam a lead down it, and fill it with solder.

author: SeanB
author_rank: Super Contributor
timestamp: November 05, 2013, 07:18:40 pm
content: Correct, just scrape top and bottom and place a small copper wire lead and bend over top and bottom and solder.

author: Neilm
author_rank: Super Contributor
timestamp: November 05, 2013, 09:04:26 pm
content: Quote from: chat1410 on November 05, 2013, 03:04:48 pmI did that with a 5V rail once. Every so often the micro reset (assuming it actually booted correctly) for no apparent reason.Chalk it up to a learning experience and remember not to do it in the future.

author: u271D
author_rank: Contributor
timestamp: November 07, 2013, 10:21:42 am
content: just learning about electronics; what good information. I'm putting together a chipino and it has a via for the 5v; after this you best be sure I'm going to be plugin that hole with a bit of copper and solder.

author: lilshawn
author_rank: Regular Contributor
timestamp: November 08, 2013, 01:17:24 am
content: After all this talk about vias I ran across this in a schematic for an amplifier...nice...

author: zapta
author_rank: Super Contributor
timestamp: November 08, 2013, 04:30:47 pm
content: Dave, is it a Digispark left to the scope here?

author: ee851
author_rank: Regular Contributor
timestamp: November 08, 2013, 05:03:46 pm
content: Awesome discovery! Sometimes the smallest detail can make a big difference. Thanks for sharing, Dave. Naturally, I'd love to see the reading with Cu-to-Cu, but Cu is quite soft, so you'd have to use sandpaper to scratch down the surfaces until they just barely fit without lubricant. (Lubricant would probably have a significant resistance. I'm talking about the anti-corrosion black conductive paste used in mains wiring for connecting Cu to Al) It would be a lot more work. But I'd love to know how much lower the Cu-to-Cu would lower the overall DC resistance.Another thought is there must be some combination of heat, vibration, and perhaps even current that would make the Cu wire bond at the atomic level with the Cu clad on the circuit board, if both were scratched down to bare metal. But I don't know what that process would be. It would certainly be a whole new area of research. And whether or not it would work without causing the PCB to delaminate and self-destruct is another question altogether.

author: AndersAnd
author_rank: Frequent Contributor
timestamp: November 09, 2013, 02:16:25 am
content: Haven't heard about the myth that solder doesn't decrease via resistance.But I guess it could come from high frequency signals, where it might not be a myth, because of the skin effect.I would expect the impedance drop by filling a via to become smaller and smaller as frequency rises because of the skin effect.Could you try a similar experiment at high frequencies?Skin depth in copper @ 1 MHz is just 0.065 mm:Source:https://en.wikipedia.org/wiki/Skin_effectQuote

author: moemoe
author_rank: Regular Contributor
timestamp: November 10, 2013, 08:50:05 pm
content: This might be slightly Off-Topic, but as dave recommended the tool in this episode, I hope it's not totally misplaced:I tried to reproduce the values printed on the µruler withhttp://saturnpcb.com/pcb_toolkit.htmMax A SMBOC @1oz: 5mil, 10K => 0.45ABut I only get 0.2A as result, see attachement.Can anybody give me a hint what I'm doing wrong? The via values exactly match the ones on the µruler.EDIT: Just found it, it's the IPC-2152 with(out) modifiere mode that changes a lot here.

author: Jerry1111
author_rank: Newbie
timestamp: November 10, 2013, 10:09:39 pm
content: Very interesting video, thanks Dave.I've had in my head (for quite a long time now) that solder-filling vias drops their resistance by 10%-20%. I have to admit that I've never actually measured it. I'm a little bit surprised that the resistance is 40% lower than that of the unfilled via. Excellent!I'm tempted to test if a similar result can be achieved by making holes in the paste mask and using SMD paste instead of solder. The problem of having enough paste to fill the via might be fixed by an over-sized paste-pad. We end up with paste on soldermask, but it should flow into the via (standard technique on various SMD 'modules' with half-cut holes for mounting).I've just realized that this is quite a good example for a video about test automation in the lab. There are 3 instruments and a time delay involved, which is not uncommon when characterizing something. Writing a simple script which shows how to solve such a task might benefit people (I still remember when I wrote my first ever python script to check a DC/DC using a programmable PSU and a DVM).

author: twistedresistor
author_rank: Contributor
timestamp: November 11, 2013, 04:13:39 pm
content: Might be a bit off topic, but does anyone know why the copper thickness of the Saturn PCB toolkit defaults to18um base copper + 35um plating, which leads to a "total copper thickness" of 53 um (as stated in the "Information" Box of the toolkit).Reading through a few technolgy guidlines of some pcb-houses for a final copper thickness of 35um they generally start with a copper foil which is about 18um thick and the rest to meet the final copper thickness of 35um is added via electrolysis.So wouldn't the right choice in the Saturn toolkit be 18um base copper and 18um plating?