Oscilloscope ASIC Kickstarter instead of Open scope. - Page 1
Forum section: electronics / projects

author: excitedbox
author_rank: Regular Contributor
timestamp: January 09, 2020, 05:59:28 am
content: We keep seeing open source oscilloscope projects for several reasons. One reason is features that the big players are not providing such as good firmware. Lets face it though these open source projects are no better.The big reason in my opinion is price though. Scopes and test equipment cost insane amounts of money. Which is why these open source scopes will never compete with the main players. In the last few years Rigol, Tektronix, Keysight, and Agilent have all spun their own Asics. In an article last year Keysight claimed that it brings the cost down to a point where they use the same chip in a $450 scope as their $45k scope.Why is there no purpose built Oscilloscope SOC on the market? It seems like such a no brainer that since we all need scopes that that is one of the chips that is desperately needed. Over the last few years the cost of producing a custom chip design have come down dramatically. I have done some looking and it is much cheaper than what is wasted on these multi million dollar kickstarters that produce the Solar dehumidifier or graphene super heater that breaks physics. The NRE for a custom ASIC would be about 500k-1 million (I have seen much cheaper but lets be realistic) but that is quickly recovered because the production cost would go down so dramatically after. If everyone that has bought one of the $700 Open Scopes or $650 RedPapaya etc. put even 1/3 of that money into kickstarter they could have a scope that performs on the level of a multi thousand dollar scope for the same price.I propose a 2 prong solution. A fabless company/foundation to produce the chip and sell it in addition to offering the design at a very low licensing fee and a base design for free such as what arm does with their IP. The collected licensing fees can then be used to fund development of firmware development. The free design would allow anyone to benefit from it not just big companies with huge wallets.The chip should be modular in design so it can be cut down for entry level, mid level designs. It should be adaptable for use in multiple test instruments to allow MSO, MDO, DSO all to use the same SOC. This way instruments no longer need to use expensive fpga chips which are only suited to the task because of their adaptability. It will cut down a lot of the development cost for the firmware as well, while also allowing anyone to modify or extend the firmware.The dominant players in the industry have been selling us hardware and then charging us again to use it, with crazy expensive license fees for faster bandwidth or a signal generator, etc. that is already in the scope. Why should a $1k scope cost over $4k if you want all the features unlocked. They have been nickle and dimeing us worse than Apple.They are holding back innovation by keeping the test equipment out of the reach of students, researchers, small companies, and individuals. We need to put a stop to it.I think the first step would be to Form and Register a foundation or company to make something official. Then look for people with experience who would be willing to donate some time or work with the promise of getting paid at a later date. Then a more solid plan than my ramblings needs to be formulated which can be presented to companies who may invest into this endeavor so they can use the chip once complete. Once we generate some interest we can hammer down the specs for the design. During that time the rest of the team can develop a web presence and generate more interest around the project. When we get to a place where we are confident we can raise the money and have a design that fits enough peoples needs we can move to the funding stage. During that stage the design should be finished so that once the goal is reached we can do a first tape out.Obviously this plan needs work and I have nowhere near the experience to lead a project like this but I would be happy to donate my time and skills in any way possible. At the very least I can make a website and make marketing materials in German and English. If it gets to a point where we meet with manufacturers I would also be able to meet with German manufacturers to push the project.I have made a discord server for anyone interested in helping move this along. OScopeAsic is the server name.https://discord.gg/DVmNC3

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: January 09, 2020, 06:16:06 am
content: That's a good plan, If you manage to find some donation that could cover 50% of my prices, I have expertise in the VHDL and PCB design,and I can help and can donate the other 50% myself.

author: ataradov
author_rank: Super Contributor
timestamp: January 09, 2020, 06:35:41 am
content: "500k-1 million" is not realistic, it is way-way optimistic. It would be somewhat realistic for a run of the mill digital IC, like a very simple MCU. It is nowhere close to analog ASIC.And if you are starting from a complete scratch, then this sum will just cover tools and libraries.

author: daqq
author_rank: Super Contributor
timestamp: January 09, 2020, 07:06:52 am
content: While a noble cause, I'm thinking that you are severely underestimating the cost of developing a usable IC (according to your specification it is a one-size-fits-all-and-everything) and overestimating the demand for a product with such an IC.To the best of my knowledge, the whole semiconductor industry is a patent minefield, everyone suing everyone enthusiastically.QuoteA third of 700 USD is 230 USD. That's not a lot of money to build anything for that's not built in REALLY massive volumes.

author: aheid
author_rank: Regular Contributor
timestamp: January 09, 2020, 07:55:35 am
content: "Why is there no purpose built Oscilloscope SOC on the market? "Maybe that's a hint. More often than not there's a reason for a gap in the market, and it ain't a missed opportunity.

author: OwO
author_rank: Super Contributor
timestamp: January 09, 2020, 08:16:59 am
content: Don't jump to conclusions that just because it doesn't exist, that it doesn't make sense economically.VNAs are a good example of untapped market potential existing for years, and it was a low hanging fruit; it didn't take much effort to beat existing players on price/performance. It still baffles me how no one saw the opportunity for all these years and only now was something like the NanoVNA introduced. Maybe it's due to the high barrier of entry to electronics entrepreneurship in most countries, and it had to take chinese cloners taking it on.However, I agree that developing an ASIC as described will take far more than just the mask costs, and to do it in plain daylight means patent lawsuits. I think there is still room to beat existing players WITHOUT a custom ASIC, and this path is more worthwhile of investigation. You will not get anywhere near a good idea of parts costs from looking at digikey, so the starting point must be a market survey of the key components (ADC & FPGA) and "inside knowledge" of the pricing of these things in volume from the manufacturers, as well as discovering all such manufacturers. High speed ADCs for cheap probably do exist, see this thread:https://www.eevblog.com/forum/projects/reverse-engineering-fnirsi-5012h/FPGAs also can be very cheap in volume.

author: DaJMasta
author_rank: Super Contributor
timestamp: January 09, 2020, 08:25:38 am
content: There are also virtually no scopes that use a single SoC solution for the whole thing. You get the ADC, the memory controller/triggering, the sample memory, and then the SoC running the display and stuff. We've got good availability on SoCs for the application software, ADCs (to some degree), and memory.... so it's the triggering/channel timing/memory controller ASIC that's the real missing link in my mind.But the problem is cost. As others have mentioned, just fabbing the chip is a gigantic cost... but finding those with enough expertise to design it with a relatively high success rate (and not many very costly respins) is going to be expensive in itself. You can't expect that caliber of design team to be donating their time... and most of the people with the experience needed to put something like that together in somewhat short order already work for the major players making their own proprietary ASICs for doing just that.If you're talking about <1GS/s sample rates, maybe you can get some basic SoC for the ADC, basic triggering, and memory management.... but if you're expecting versions of the chip to be able to handle 1GHz+ front end bandwidths or high resolution (10b or 12b conversion).... I think it's a lot more difficult of a challenge than you give it credit for.As a point of order, I'd also disagree with the assertion that the big test equipment managers can't provide good firmware. Yeah, a lot of it can stand to have some more polishing... but I think it's come a long way in usability and gets a lot more issues addressed in the last 10-15 years. Most of the major manufacturers don't offer entirely bug free firmware, but offer scopes that are very usable and very powerful that have a couple orders of magnitude more complexity than early digital scopes and their firmware.Now if someone wrote the software for an FPGA that connected a standard ADC interface, a standardized trigger system (or just implemented basic entirely digital triggering), and regular DDR memory of some flavor - that could be a core element that could be used in a lot of designs and be iterated on meaningfully in an open source environment.... but it's not going to be nearly as flexible or modular as what you're thinking, I think, and then there's still the matter of building up the whole UI and application software to interface with it.

author: filssavi
author_rank: Frequent Contributor
timestamp: January 09, 2020, 09:07:43 am
content: The main misconception here is about why big players put ASICs in theirs scopes. At the top end (think keysight UXR or lecroy labmaster with 100 GHz of BW) it is ceratinly because no off the shelf solution does exist with the required level of performance, however if we look at the mid/low end (where a kickstarter effort mightjust manage to be competitive) with up to maybe 2/4 GHz BW and 10/12 bits ADC's this is most definitly not the reason.In that space you can build a solution entirely out of standard components from regular manufacturers (AD, TI, etc). The ASICs are only used because they are cheaper in large volumes (tens to hundreds of thousands of units), and keep also in mind that by going down this route you commit to a single architecture until you have recouped the costs and made enough profits for the next generation, and you risk ending up with something like the megazoom 4 and the low end keysights, that while they were once competitive and all, now are hopelessly outdated (in the low end maket anyway).Now even if you manage to raise the capital on kickstarter (let's say 5-15 milions might be just enough) and assemble a team (which will be if we are generous 1/2 senior engineers with 5-10 years of experience poached from industry and the rest newly graduated students) you still face a 2-5 years development cycle (2 for a half backed product and 5 for a fully polished one) which is way too long for kickstarter, and the uncertainty of how much it will sell later (you still have to convice engineers to back you) if you want this to become something long term viableEven if you manage to execute all the above perfectly and all the stars align, what will really kill you is that you will not have any serious probes to use your product with, as all the interesting stuff (active differential, current, high voltage differential, etc) with decent performance is only available by scope manufacturers and compatible with their scopes only

author: OwO
author_rank: Super Contributor
timestamp: January 09, 2020, 09:23:38 am
content: Above 2Gsps forget it. One channel of desktop DDR3 connected to a Kintex 7 can probably manage 2GB/s reliably (and 4GB/s peak), but any more and you won't be able to do it within reasonable cost with off the shelf parts. Triggering is not very hard and doesn't take much FPGA resources to implement.

author: Someone
author_rank: Super Contributor
timestamp: January 09, 2020, 09:47:40 am
content: Quote from: OwO on January 09, 2020, 09:23:38 amBut thats the inherent beauty of an FPGA, need more throughput to memory? Use a wider bus. Also using the characteristics of the incoming stream allows you to simplify and/or produce hard realtime performance in the controller rather than relying on a general purpose random access policy.

author: filssavi
author_rank: Frequent Contributor
timestamp: January 09, 2020, 09:59:59 am
content: Quote from: OwO on January 09, 2020, 09:23:38 amThe Zynq Ultrascale (MPSoCs) the PS alone (hardware memory controller) support up to DDR4-2400 for a theoretical maximum bandwidth of ~20GB/s, you could also implement an additional DDR controller in the PL and get even higher bandwidth,From trenz you can even get an off the shelf module with 4GB of DDR4 and a almost 300k LUTs for considerably under 1000 € in 1k quantity, and I'm shure that with higher volumes and dealing directly with Xilinx would get you a good deal on the IC's themselves

author: OwO
author_rank: Super Contributor
timestamp: January 09, 2020, 10:05:12 am
content: So the OP is targeting a retail price around $200 which means a total BOM cost under $80. Zynq-7010 is probably the best you are going to get if you want to leave enough room for the ADCs and front end. At this price I say 1Gsps is realistic and you may undercut Rigol, just maybe with no display.

author: filssavi
author_rank: Frequent Contributor
timestamp: January 09, 2020, 10:56:22 am
content: I had completely missed the targeted price-pointIn that case I completely agree with you, and also the use of an ASIC is even more unlikely, unless he intends to ship milions of the thing

author: ogden
author_rank: Super Contributor
timestamp: January 09, 2020, 01:12:24 pm
content: Quote from: OwO on January 09, 2020, 10:05:12 amRight. Result will be "scope" in form of bare PCB with no enclosure, no screen, and .... no firmware/software. This is just one of those daydreaming projects "let's make XYZ because BOM of PCB cost virtually nothing"

author: OwO
author_rank: Super Contributor
timestamp: January 09, 2020, 04:02:45 pm
content: You know, if someone manages to put out a 1Gsps scope for less than $50 it'll probably sell pretty well even with very rudimentary software. A waveform display, maybe a bit of zooming, some basic triggers, etc. I could write the software and firmware in two weeks. But getting the ADCs and Zynq for that cheap is a bit of a stretch. Might be possible with chinese ADCs, I'll look into it.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 09, 2020, 04:11:12 pm
content: Quote from: excitedbox on January 09, 2020, 05:59:28 amI don't think you've got this right. Today's low-end scopes can be found in the $200-$300 range and still have pretty "impressive" specs (I consider designing a 1Gsps scope impressive even to this day).There's very little way you can do better than this price-wise especially if you don't have the "weight" of a big player (to get ultra good deals on all critical components, to be able to pull off selling with very low margins, etc.)I think that's the recurring DIY syndrome issue. You always start thinking how much cheaper you can do it than COTS, and it rarely ends up that way.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 09, 2020, 04:36:48 pm
content: I will start believe in Kickstart projects for ASIC if there was a prior history of successful lesser projects. Say some FPGA based Kickstarter, then rerun, then it became more and more established and popular.May be there is an example of small groups rolling their asics. Look at the Parallax Propeller 2, some analog chip "THAT 2151" rolled for music synthesizers community, so there is a hope.I think ASIC on Kickstarter is possible, but only after some meaningful transparent history of lesser successes.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 09, 2020, 05:09:26 pm
content: Regarding just the ASIC thing. If it's a purely digital design, and can be prototyped (even if at lower clock frequencies) on FPGAs, this could stand a small chance. There's a number of companies that offer services to get an ASIC from your HDL, so if the project gets enough traction and funding, that could be doable. (Whether/when it would become cost-effective is another story.)Now if it contains anything analog, that's a completely different league and story. You'd need to pre-select a given node process, get enough guarantees you could prototype this through the corresponding manufacturer, get access to the PDK AND the design tools... and of course get microelectronics engineers onboard, that know what they're doing... that's almost impossible IMO. You could first start through MPW, and try to get access to the tools for "cheap" through some kind of education/small company deal, but then getting up to scale later would probably be out of the question entirely. And even if you get to the point of a few ASIC prototypes (that's what you'd get through MPW, something in the 15-20 usually), you'll need a lot of resource to properly test them...Microelectronics is a f*cking expensive activity. The only remotely realistic endeavor would be my first point IMO (purely digital stuff through a fabless company getting your design to silicon).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 09, 2020, 06:26:14 pm
content: There's no market for oscilloscope ASICs.You could gather a bigger market by making a more general device.But general purpose devices already exist: analog front ends, fast ADCs, SoCs and FPGAs for continuous, burst, SDR and ET sampling, and waveform analysis. Which are indeed what a lot of scopes already use, and for good reason.Or -- how about a campaign to write an OS for Rigol or other cheap scopes? The ones with ASICs (Rigol) may not be very practical to rewrite (a proper careful reverse-engineering of the software or hardware may be necessary to understand their interfaces), but the more general ones using off-the-shelf parts should be relatively straightforward to trace and build from the bottom up.Tim

author: Lukas
author_rank: Frequent Contributor
timestamp: January 09, 2020, 07:34:15 pm
content: Wondering why nobody mentioned the RFSoCs yet. Kinda on the pricy side, but you'd get 8(!) 4GSa/s ADCs and a CPU beefy enough to run the user interface.

author: KE5FX
author_rank: Super Contributor
timestamp: January 09, 2020, 07:49:46 pm
content: Yep, the RFSoC really does sound like the right way to go. Analog Devices seems prettyupsetabout them, for some reason.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 09, 2020, 08:06:28 pm
content: Please read thoroughly before posting it seems a lot of replies are based on misconceptions of what these asics do and what it is I am suggesting.In Short. ASIC IS THE FRONT END. ADC, DSP, Memory Controller, Clock, Triggering, All those things. Then whoever wants to use it buys an ARM soc with Arm cores, LCD driver, Uart, IO, all those things you need for the displaying of the signals etc. for a few $ from ST and connects it to the memory.Also keep in mind that I am not proposing designing or producing a single scope. I want to produce a cheaper solution to making scopes and it is a FACT that these asics do just that. If you are a manufacturer buying FPGAs and ADCs right now, you can just as well purchase an ASIC to combine those things. With free access to the basic framework for the software your development costs drop even more.How much they sell the product for in the end is still up to them in the end. Any speculation of what is achievable price wise is just speculation and WAY to early to say what is or isn`t feasible beyond Keysight using the same chip in a $450 and using 4 of them in their $45k scope. If each company right now can afford to make their own ASIC and hoard it for themselves the economies are there even for low production. Then multiple companies using the same chip must be worth it even if it just gives them cheap access to the IP to produce the chips they need.A 300mm wafer produces hundreds of CPUs and even 7nm costs 8k per wafer. Yes they make higher numbers but 7nm is also WAY more expensive than 130nm or 350nm.This is not a problem of can it bring results it is a problem of can we get it financed. This levels the playing field because it removes the large upfront nonrecoverable expense and spreads it across multiple companies over time.I think people misunderstood me on the price example. I meant if they all pooled that 1/3 of the cost of those projects and put it towards investing in the development of an asic you would have raised enough money for the development of the chip. Then the other 400-500 would have paid for a much better scope using that chip.Nobody is gonna use our chip for a 100GHz scope. Be realistic. This doesn´t have to be an all or nothing thing. Just as there are budget CPUs and Server chips.If we make a chip for up to 1Ghz and 4-5Gsps using interleaving on 1 channel that would bring the cost of the scopes used by over 50% of the market down to something affordable. These scopes right now are in the 40-50k range because of software licenses. If you use 4 chips you can have 4 channels with 4Gsps or you can use 1 chip and have 1Gsps.A chip like that would bring a 1GHz 2 ch scope down a ton in price.You would not want to put the processor in the asic. The asic would contain the analog front end and signal processing and memory interface. Everything beyond that can be handled by off the shelf ARM SOCs for pennies. Most of the features that make a scope desirable such as UI, LCD, USB interface, Ethernet, Wifi, Displaying a waveform or inputting values for a waveform to output, that can be done using a few ARM cores. The only part that needs to be on the asic is the Front-end because of the speed at which signals need to be captured, processed and stored.What makes it expensive right now is that there are only few analog FPGAs and those that do have some analog functions only have slow ADCs because they are not specialized for the test equipment market. That means you need a fast ADC and an FPGA to process the signalAlso keep in mind the concept of SOCs has only really taken off in the last few years. Before that parts count in electronics was much higher because the development cost was higher. The technology, ecosystems and way of doing things just hasn´t been around that long to say this is a missed opportunity because as we see the companies that are at the tip of the spear are now starting to implement this. I am sure that in a few years some company with more of a application focused product portfolio will make such a thing.Piecing together IP from many companies has become much simpler and there are now basic building blocks that are combined just like we build a circuit on a PCB but smaller. Combining a DSP core, DDR3 controller, ADC, DAC and attenuation. etc. onto a single chip is much easier and the Open Core Project, and a few others make it possible for anyone to build a chip.Keep in mind that Keysight and the crew design the chip from the ground up because they want to go for huge bandwidth and maximum savings an so on. We can use IP cores because we wouldn't need 100GHz signal capture. Nobody is gonna use our chip for a million dollar Oscilloscope.If Feelelec can make a signal generator and sell it for under $100 why is it a $1200 upgrade for a 25Mhz gen on a Rigol scope? Obviously the cost is just an arbitrary number and if you can bring the parts cost down and provide an open source framework of tools each company can customize their UI and features to their hearts content and drop prices to a reasonable level.There are millions of scopes sold world wide and it would be more if they were more affordable. Don´t kid yourself and believe that because of small production runs they can´t afford to make them cheaper. If this was the case they wouldn`t give you the Hardware for a $4000 scope for $999 and charge the rest in upgrade fees.If the chip has a modular design meaning you can slice off a channel on the ADC etc. it should be possible to make a scope for 250 or 300 or 500 or 1000 by putting in a whole chip or half chip or multiple chips. Just like AMD has done with their chiplet architecture. The 3970x sits on the same module as the 3990x they just solder on 4 chiplets less.Anyone that is interested in working on this send me a PM and lets see if we can at least do a market analysis to see if it is possible. I assume everyone has discord maybe we can move the discussion there. I made a discord server. OScopeAsic is the server name.https://discord.gg/DVmNC3My dad is a retired chip engineer (Zeng Labs, Original AMD Radeon GPU, Iphone 3 to 4 A processors at Apple, and SOCs at LG) and although he wont want to work on this full time he would be a valuable asset for any questions that might arise.Silicon Wizard, I know there are budget scopes in that price range. I have a Hantek 5000 series myself. Those scopes could be even better if they used a custom asic. Right now they are buying ADCs that cost about as much as an ASIC would. The budget scopes are great and I would never have been able to afford a scope if it wasn`t for them but as soon as you go past what they offer you are stuck buying a scope that costs as much as a car.My post has gotten long enough. I ask people to please read thoroughly before posting and informing themselves of what these chips do. Half my post is just correcting misconceptions. It doesn´t help you or the project to get off topic discussing things that are irrelevant.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 09, 2020, 08:17:01 pm
content: By the way the Oscilloscope market is about to reach $1.7 Billion in the next few years. So don`t tell me that the market size is to small and the numbers are not there. That is probably close to 1 million scopes per year being shipped by about 70 companies.https://www.marketwatch.com/press-release/oscilloscope-market-size-to-cross-1720-million-by-2024-2019-11-01

author: daqq
author_rank: Super Contributor
timestamp: January 09, 2020, 08:53:30 pm
content: QuoteMy guess: there's no way you'd fill the budget for a competitive IC that could handle all of that, that includes:- paying a team that is able to pull it off for a reasonable time frame- NRE for prototypes and initial batch- development and validation- IP (you either license a load of IP or develop everything from scratch, ADC included in such a way that it does not step on any patents)- toolsfrom kickstarter, given that the repayment is pretty much a thank you and the possibility of cheaper scopes in the distant future. The kinds of cash you'd need is in the serious venture capitalist area. Good luck and all, but I'm skeptical.QuoteWhy? Aside from the fact that not everyone has discord, the forum is a much better platform for this sort of discussion.

author: tautech
author_rank: Super Contributor
timestamp: January 09, 2020, 09:13:05 pm
content: Quote from: excitedbox on January 09, 2020, 08:06:28 pmHappening already:https://siglentna.com/product/sds5104x-1-ghz-4-ch/QuoteRubbish, may a few are but the marketplace is rapidly changing.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 09, 2020, 09:29:00 pm
content: I really should not have to explain why you do not develop a semiconductor in 1 thread on a message board but ok.To eliminate 70% of the posts repeating "you will never fit the budget" from the nay sayers with 1 zero experience, 2 not the slightest knowledge of what is and is not possible, 3 don´t understand the project. Out of 17 Replies since yesterday only about 3-4 were in any way shape or form productive. You can´t develope a product on an open forum with 1000s of people who are not involved throwing their opinions into the mix. I know I am no expert and I don´t pretend to be but I have done some research and don´t need to reply to 20 people that misunderstood the original intent and have done no research but are making claims as facts.Also can´t work a project with only one communication thread and maintain any organization.There will have to be Non disclosures signed etc. for Design Kits so certain things can´t be public.Sharing confidential info and files.I think those are enough valid reasons that your question has been answered. This thread can still be used for outsiders to throw their 2 cents in but this is not a place to get work done.This is not directed at you so don`t feel attacked this is just a general notice to downers.If you don´t think it is possible keep it to yourself, it is not helpful. If you have a suggestion how to improve it or a valid concern that is great I would love to hear it. If you say I would rather have this feature instead of that feature Super. Just saying it wont work or it is not what anybody wants doesn't help because apparently at least someone wants it since several people have expressed interest including me.As stated before the economies do work because these companies can even afford to keep the manufacturing quantities even lower by not selling the chips publicly. The most expensive part is the NRE after that they can enjoy huge margins.A few years ago people would have said you could never afford a 3d printer. they cost 10s of thousands. the Makerbot drove the price down and now they cost a couple $. Same with Arduino, Arm SOCs and everything else. People need to get out of this boxed in mind set that these things can only be done by big companies. Especially on this forum people should understand that.

author: magic
author_rank: Super Contributor
timestamp: January 09, 2020, 09:36:36 pm
content: Quote from: excitedbox on January 09, 2020, 08:06:28 pmThere is a certain counterbalancing factor, which is that not everybody wants to be a manufacturer of glorified reference boardsChances are that established players would rather collectively boycott you and shut you down with patents. They have their own special snowflake SOCs, IPs and "differentiating" features which they aren't sharing with anyone. But you could target the sort of vendors who make all those PCB modules sold on AliBay, if you get it to the level of "route BNC jack to pin 1 and read capture data over SPI from pin 2, pin 3 is ground and 4 is VCC, please bypass with 100nF".

author: excitedbox
author_rank: Regular Contributor
timestamp: January 09, 2020, 10:04:10 pm
content: Quote from: tautech on January 09, 2020, 09:13:05 pm

author: excitedbox
author_rank: Regular Contributor
timestamp: January 09, 2020, 10:09:49 pm
content: Quote from: magic on January 09, 2020, 09:36:36 pmThat is like saying that Apple will boycott me if I try to design an OS. There is nothing that Apple needs from me but other companies who sell computers might want a good free OS that gives them the same stuff as the big players.Also your counterbalancing factor is what all these companies like Hantek etc. are doing.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: January 09, 2020, 10:16:27 pm
content: Quote from: OwO on January 09, 2020, 09:23:38 amHow many people1) need >2Gsps2) would be interested in a hugely risky Kickstarter3) can't afford one of the many tried and tested off-the-shelf scopes?

author: excitedbox
author_rank: Regular Contributor
timestamp: January 09, 2020, 10:31:31 pm
content: That is why we need industry support. Hantek, MCH, Siglent, Picoscope, Voltcraft. Developing their own Asic might be out of the range of each of them individually but if they each only have to put up 5-10% they might be willing to invest. They would be the ones benefiting the most from it in the end and in the grand scheme of things is 50k no that much to invest in the future of their business. You have to remember that all their competitors now have their own chips so they are falling behind.As technology gets better signals have gotten faster and there are more of them. People used to be excited about 20MHZ analog scopes but now that is considered a useless toy scope.The reason they can each use the same chip is the same reason they can use the same FPGA or ADCs etc now. One company might use 1 asic for 4 "slow" channels while picoscope uses 4 asics to give you the maximum bandwidth and sampling speed on each channel. One company might decide to use a USB2.0 while another uses USB 3.0 or USB C or Ethernet, or Wireless, One uses a touch screen while the other uses knobs and buttons. All those feature differences will be controlled through the ARM processor though which is separate from the ASIC.When you look at the Asic as a complex signal capturing chip just as you would use a ADC to get your signals in another project you see that they really are not all developing the same products in the end. It is just 1 small piece of the product that will be the same. Just as in the computer industry there are only a couple CPU architectures but OEMs don´t all have the same laptops.

author: thm_w
author_rank: Super Contributor
timestamp: January 09, 2020, 11:21:44 pm
content: Quote from: excitedbox on January 09, 2020, 10:04:10 pmMSO5072 costs $909, has 8GS/s stock and likely 10Gs/s capability built in. You'd be better off buying that and hacking the front end to 1GHz.The cheapest siglent is $2,900 and has 5Gs/s, so there is no comparison here in terms of raw performance.The thing is though, with that ASIC, they are using the same chip in their $10,000+ oscilloscopes. So you get payback from those sales which recovers the initial NRE of designing the original ASIC. Its the same with keysight, except they kept the ASIC in their high-end scopes for years then eventually trickled down to the low end. Rigol would probably sell you the ASIC,ifyou weren't building a competing product, and they'd probably charge you $500+ per piece.When you just build the low end model, and sell it for $900, you have no ability to recover those NRE costs.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 10, 2020, 12:20:10 am
content: that 8gsps is on 4 channels which you cant use all of at 70mhz. to use the full bandwidth and sampling you need all the upgrades which brings the price to over 4k. That scope is an outlier and when it came out I was surprised. Rigol was celebrated for releasing that scope for such an affordable price. Rigol is not as bad as the other companies when it comes to their base models because they are hackable. But the upgrades are still over priced.You could also say Hantek makes affordable scopes so this isn`t needed. These are all excuses. Companies like Hantek have given us a good product at an affordable price which is why they don´t have the budget to develop their own chips. I for one would have no problem investing a couple hundred knowing that it will allow them to continue doing so at an even better price to performance. Think of it this way If 2000 people each paid $250, (Before people misinterpret that again. NO I don´t expect 2k people to do that) any budget manufacturer could give you 8gsps scopes for $900 like Rigol can but with all features unlocked from the start. Not having to pay another $3500 for all the upgrades. Last year that $900 MSO cost $4500 fully unlocked. That is the price difference that is possible. Also keep in mind that hacking the scope is piracy and is illegal because that is a software license they are selling you.1. Multiple companies using the same chip spreads costs. (This seems to be the hardest for people to understand. People keep acting like this is going in only 1 product)2. Manufacturing costs are tiny in comparison. (AMD pays less than $13 for a CPU made on the MOST expensive node while this will be one of the cheapest. A qty discount can only go so far since there are still set costs such as materials and EUV is very slow)3. Companies offer shit software and locked down systems.4. This chip has other uses other than Scopes.5. These features are not set in stone. (I said in my 1st, 2nd, 3rd, 4th, 6th, and 8th post that we would need to see what makes sense.)6. Scopes are multi year products. Meaning 1 chip will be sold over several years. (if 1% of scopes use this chip that means over 1 million units in 5-7 years.)7. We don´t have any of the facts yet and nothing is set in stone there is no way to determine if it REALLY makes sense until you look at the math.8. This is not going to happen through a kickstarter. The title was hyperbolic to say that these OS scope kickstarters are misplaced because they can`t compete with an ASIC. (should have been clear from my first post. Where I outlined in detail forming a foundation and going to companies for support).I know this comes off as harsh but I feel like I am talking to a wall. People keep repeating the same arguments that don´t hold up if you look at the numbers that we do have. Not one of the people posting these arguments seem to have read even the last 3 comments. They skim the first paragraph and post the first thought in their mind. I am going to have to start a new thread and maybe move to a different forum with a less shoot from the hip impulsive response. This thread has gone completely off the rails and there is nothing productive happening here.

author: thm_w
author_rank: Super Contributor
timestamp: January 10, 2020, 12:50:10 am
content: Quote from: excitedbox on January 10, 2020, 12:20:10 amSorry but I don't care what the upgrade costs, its not relevant to me.Publishing a binary patch is not piracy and has not been shown to be illegal, as far as I know.I disagree that any budget manufacturer can give you a 4-ch 450MHz 8GSPS scope for $900 without losing their shirts.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 10, 2020, 01:34:41 am
content: Quote from: T3sl4co1l on January 09, 2020, 06:26:14 pmFrom years ago what I remember about advertised breakthroughs in oscilloscope ASICs is two things: One brand advertised 50000/sec screen updates, may be meaning the good coverage of triggered sweeps ratio to missed events. Another manufacturer claimed trade mark of "Digital phosphor". That made me think that actual challenge in scope ASIC is dual-or-multiport memory with digital adders and faders per "pixel" (bin of Y magnitude). Say for Megasample wide X window you actually need full vertical Y column of "pixels" with all accumulated counts and fading. Perhaps 500x16 bit values. Before any optimization and compression that means 1GByte of multiport SRAM. That is core of ASIC. The rest are small things like interpolators, non-linearity correction by lookup, addressing routes/pipes to feed the SRAM, adders, faders, output interface to present SRAM to external CPU bus.The multiport SRAM can be turned into external normal DRAM may be, say put large amount of DRAM chips on individual buses for parallelism, as much as pincount allows.Then ASIC becomes a deserialising data sorter, updater to external DRAM, plus some DMA from the point of view of CPU.I am just theoritizing about what "universal" can there in such pure ASIC for reusability as pure digital chip. May be such chip or major part of such chip already exists in form of say obscure telecom "Bla ATM arbiter, backbone router, massive crossinterconnect Cisco Bla thing"Edit:@excitedbox. I think there is nothing negative in this thread. The idea alone is very novel and disruptive. Speaking of shooting from hip. Which is also good. Internet is fast place.Edit2: By "novel and disruptive" I mean idea of creating ASIC market for scopes. Not other related ideas of conquering existing established markets. Entering the established market is bad idea. Creating your own new market is good idea. That was some advise I heard from one successful tech in business.

author: ebclr
author_rank: Super Contributor
timestamp: January 10, 2020, 02:30:05 am
content: "(AMD pays less than $13 for a CPU made on the MOST expensive node while this will be one of the cheapest. A qty discount can only go so far since there are still set costs such as materials and EUV is very slow)"Once upon a time, somebody charges a customer 250 USD dollars to fix a device with only a 0.01C broke resistor, The customer complains, the resistor is only 0.01 C and you are charging me 250 USD? The technician said, no resistor is only 0.01C I'm charging you 249,99USD, for my years of study and experience to know with one is the resistor who is brokenRegarding the dream to make the SOC, will not happen with 1 Million dollars you can buy 1111 Rigols, I doubt you will find 2000 interested in pay this amount for a chip, It's a dream, Will be easier to bring this million-dollar to Rigol and make a proposal for a open-source firmware version of the product, where all the hardware is open-sourced, at a 30% discount for the ones on kickstart, with the soc they already paid, Still a dream but a more viable one

author: wraper
author_rank: Unknown
timestamp: January 10, 2020, 02:37:41 am
content: Quote from: excitedbox on January 10, 2020, 12:20:10 amDo you really believe that? If that was true, they would sit on piles of money instead of going towards bankrupt before releasing Ryzen. Such price is valid only for their outdated low end CPUs on old node.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 10, 2020, 03:29:04 am
content: Quote from: unitedatoms on January 10, 2020, 01:34:41 amThanks for the reply you brought up some good points. The hard part with an Oscilloscope is getting the data into memory after that it becomes a lot easier. All these open source scopes would be a lot better if they had access to an asic like this. The Analog Discovery 2 for instance is a cool device but sadly they are limited in speed by their capture speed. A project like that with a faster signal capture would be very disruptive to the market.The negativity I refer to is the stuff below that I am answering for the 8th time now. The one guy brings up a $900 and in his next post claims no manufacturer could afford to sell a scope for that price.Quote from: thm_w on January 10, 2020, 12:50:10 amIt is illegal because that binary patch is circumventing the DRM to enable software that you do not have a license to use. This is what the whole right to repair fight in the US is about. There is a guy sitting in jail right now for giving away free copies of windows that could be downloaded from the microsoft website WITHOUT a license key for people to use with their OWN license. If you download a free trial of photoshop and crack the license key it is clearly illegal. That is exactly what you are doing when you hack your scope. I don´t care about that though.Rigol already sells the MSO5000 for that price, YOU brought that up. The hardware cost to them is no different whether you upgrade it or not. The parts are in the device when you buy it for 900 and then you buy an upgrade code for each feature that you want on top of that. They have reduced the price slightly recently for some of the upgrades but this scope is very attractive to the hobby market who is unlikely to upgrade and will sooner hack the license. And again the price will come down using an ASIC.Quote from: ebclr on January 10, 2020, 02:30:05 amAgain I already said that getting 2000 people to donate $200 is not the plan (I even clarified that in a note just for you) it was a hypothetical. Please read the thread before posting irrelevant stuff that everyone that does read has to waste their time on. The big cost for designing a Keysight ASIC compared to this is also that they build from the ground up instead of using IP blocks. Using IP blocks is like using chips but smaller. You don´t design every op amp circuit either you buy an op amp and call it a day. There are IP blocks for fast ADCs and everything else needed available. There is a software suit called Magick that is open source for designing chips.Quote from: wraper on January 10, 2020, 02:37:41 amNo, those prices are for their 12nm node which are much more expensive and these asics would be made on much older nodes anyway due to the higher voltages and cost savings. At the smallest 45nm but I am assuming either 65nm or even larger. That would have to be determined.Again though please don´t make statements without informing yourself first. A quick google would have saved me that answer. AMD was no going bankrupt because of the costs of manufacturing chips. Up until 2012 Intel was paying Dell up to $1.2 billion a year not to use AMD chips. Along with every other OEM. AMD tried gifting HP 1 million CPUs FOR FREE and they refused to take them because Intel would punish them by cutting off their bribes. In addition Intel who is a major supplier of compilers kneecaped AMD CPUs by having their compilers use slower instruction sets if you had an AMD CPU this made peple think AMD CPUs were worse than Intel.Here is a video that will explain the anti consumer BS Intel has done since 1982.

author: tautech
author_rank: Super Contributor
timestamp: January 10, 2020, 03:34:33 am
content: Quote from: excitedbox on January 09, 2020, 10:04:10 pmAs others have attempted to point out, this 1 GHz 5 GSa/s HW is the same as used in 350 MHz models for some $ 3570 and the same promo including all 7 options for free is effectively a $2k further saving.Do the sums, 1 GHz, 5 GSa's HW and options for what amounts to $ 1570QuoteDo you imply other brands don't/won't do promotions ?QuoteJust one word; support !QuoteAll brands are guilty of this. Period.If the true cost of options was factored into pricing all equipment would be somewhat dearer and we wouldn't have the pricing structures we have today. For some time manufacturers have been cramming additional capability into equipment that few of us will ever use let alone want however such is the capability of modern gear now this results in less equipment on the bench albeit also for less cost.

author: tautech
author_rank: Super Contributor
timestamp: January 10, 2020, 03:41:50 am
content: Quote from: excitedbox on January 09, 2020, 10:31:31 pmCan you really see marketplace competitors in some alliance developing an ASIC that they each will use ?I have my doubts but good luck.

author: ogden
author_rank: Super Contributor
timestamp: January 10, 2020, 04:44:29 am
content: Quote from: excitedbox on January 10, 2020, 03:29:04 amThey can't sell "fully unlocked" scope for price of BW-limited one! With same success you can ask all software companies to sell their full products for price of "lite" version. Your argument is not even naiive. It is absurd.

author: David Hess
author_rank: Super Contributor
timestamp: January 10, 2020, 05:26:00 am
content: You can accomplish everything you suggest with a reference design using existing parts including a bit of programmable logic and no custom ASICs. Nobody has even done that so I doubt the economics make either viable and an ASIC based solution even less so. Full documentation to an existing DSO with the proper hardware would allow it but that is sure never going to happen.Quote from: unitedatoms on January 10, 2020, 01:34:41 amThe ASIC or programmable logic generates a 2D histogram in real or decimated time. Performance is limited by memory bandwidth so embedded memory which can be wide and shallow has an advantage over external memory. High performance desktop CPUs have enough cache bandwidth and instruction parallelism to take advantage of it to perform this operation.Some compromises in performance would allow a commonly available CPU for embedded use to produce a reasonable display assuming that the digitized data could be delivered to it.

author: wraper
author_rank: Unknown
timestamp: January 10, 2020, 07:38:56 am
content: Quote from: excitedbox on January 10, 2020, 03:29:04 amPlease don't make such bolt statements without providing anything supporting it, showing source of this data. Googling does not show up anything supporting this claim.QuoteAs if it was enough to cause this. And I knew about it even without you. Also I knew that Intel paid compensation to AMD.QuoteNow it's simply BS.EDIT: BTW HP made AMD based desktop PCs and laptops before 2012 when judgement was made and before 2009 as well. have seen plenty of them.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 11, 2020, 12:07:26 am
content: You can not say what can or can not be afforded without knowing how much this chip costs. We know right now the ADCs etc are expensive. We know FPGA development takes a lot of time, making it expensive. We know Open Source projects reduce costs in 95% of cases. Paying 5-10 engineers 50-60k a year to develop memory controllers on an FPGA is money you can save if you have a chip that has a memory controller on it.David Hess- Keysight, Tektronix, Rigol, all have their own ASICs. Did you even read the first post? You picked single pieces of information to base your argument on and didn´t look at the whole picture.You say there wouldn`t be competition but when anyone can buy the same chip, if you don´t compete someone else makes the same product and your share is reduced. Also there are many ways to skin a cat. I might want to save a few bucks and buy a scope with USB 3.0 while someone else wants a larger LCD and another person wants even faster data transfer to chain instruments. Most of the things that add value to a scope are beyond the signal capture. Signal capture is only the first step. Even in the UI there are enough differences that 10 people want 10 different devices. Some people love USB scopes while others would never buy one.Someone mentioned a ~$1300 scope with 350MHz. Hantek has a $600-700 scope with 300MHz. The thing is anything beyond that you are spending as much as a car. You are basing your arguments on hypothetical specs for a chip that has not a single feature locked in. No one including myself knows yet what this would look like.Arguing that it is pointless is ridiculous since 6 companies each spending 1 mill plus and hoarding a chip for themselves is done for a reason. BECAUSE IT IS WORTH IT. They make so much money they don´t need to sell it to split the costs.The argument of not being able to recover the costs is missing the point. They are buying several chips right now which cost enough to cover development of those chips, company profits for those chips, marketing costs for those chips. These costs are still there. When McDonalds sells you a Happy Meal that Toy is not free. YOu pay for the toy in the price of the happy meal. Same with buying 1 chip instead of 5-6-7-8. Buying 1 chip is cheaper because of efficiencies or NO COMPANY WOULD EVER make their own chip. It would never be worth it to combine chips into one custom chip.Yes Intel paid less than 3 Billion compensation for 20 years of pushing them out of the market. They didn´t just pay Dell they paid ALL OEMs Toshiba, Lenovo, Samsung, HP, All of them took bribes. These companies sell/sold around 80% of the worlds PCs. AMD was forced to settle in 2007 or 08 when the recession started and they would have gone bankrupt if they hadn´t. Fact is AMD was almost locked out of the market from 1984-2012 while producing a very expensive product and that is where the money problems came from and not because the profit margins were not there. Someone did the math recently and their entire Server chip production comes from a few like 2k wafers a year. Now look at how much profit the server market brings them. That profit is coming from around 100k CPUs.Quick googleSearch: "AMD 7nm wafer cost"AMD cost per wafer, yields, and cost per good die for 7nm, 12nm, 14nmhttps://adoredtv.com/zen2-chiplet-quality-examined-by-cost/Here are similar prices for Apples wafer and die costs.https://wccftech.com/apple-5nm-3nm-cost-transistors/Search: "300mm wafer cost"Wafer Profits for Pure Play $7.41 per sq inch at .5 micron on a 200mm wafer $53.86 per sq in at <20nm on 300mm. So same square inch produces 8x the profit because of higher costs.https://www.elektroniknet.de/markt-technik/halbleiter/wafer-preise-unter-druck-158732.html

author: tautech
author_rank: Super Contributor
timestamp: January 11, 2020, 12:37:56 am
content: Quote from: excitedbox on January 11, 2020, 12:07:26 amNope, you missed the point.So does Siglent in the 2ch SDS2000X-E series, for $ 620 you can have the 200 MHz version that can be hacked to 350 MHz....done it so proven.SDS5000X 4 channel models of 350 MHz are the same HW as 1 GHz @ 5 GSa/s and using two 5 GSa/s ADC's.The point being SDS5034X @ ~$3.5k with current promo of $2k of free options is effectively just $1500 if you wanted all of them.Current marketingandtechnology is giving us deals like never seen before which leaves little fat on the boneordesire to push to higher levels of performance such is the small amount of sales in that sector.

author: nctnico
author_rank: Super Contributor
timestamp: January 11, 2020, 12:39:37 am
content: Quote from: excitedbox on January 11, 2020, 12:07:26 amASICs are even more expensive to design compared to FPGA. Actually many digital ASIC designs are prototyped/debugged using FPGAs.Either way the hardware cost of an open source oscilloscope is largely irrelevant. There is lots of existing hardware for sale anyway. When push comes to shove it is perfectly feasible to take an existing piece of hardware (for example a low cost Hantek) and create new firmware for it. However even when including the FPGA development the balance between hardware & software effort to create a digital oscilloscope is 1 to 50. Writing good oscilloscope firmware is a massive task which is where open source oscilloscope projects fail. It takes probably 3 complete rewrites before getting the fundamental structure right. If there is any chance on a succesful project then start with the software while using an existing platform (red pitaya, analog discovery, etc). Once the software is done the hardware is peanuts.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 11, 2020, 03:12:03 am
content: That is a good point about the software that is why I want to include a "scope OS" with this project or at least a framework. Just like there is Openwrt, RouterOS, Asterix etc. We do have the sigrok firmware but right now no manufacturer wants to use that. The reason development is so expensive is because the signaling hardware is so different in each scope. You can´t just attach a SOC and send some triggering commands to a chip or set the attenuation or gain.There is also the problem of light speed. Hantek CAN'T give us more without ASICs the distance that the electrons travel in that time becomes to short. So even if someone wanted to capture signals faster it just isn´t possible. This applies to other products besides scopes as well. If there is a simple to use signal capturing chip, a ton of other opportunities open up.In addition a FPGA is really complex internally which makes them expensive. A chip has tons of transistors and resistors but a FPGA needs all the same stuff PLUS the routing and switching transistors. There is a ton of complexity that can get removed.If you look at the links I posted below a custom ASIC starts to look very attractive with a development savings of 40-60% and a BOM savings of 50%. Their calculation is if you spend 250k a year on parts you can recover the investment in 1 year using multi Layer Reticals.We all know that when working with Arduino, using a motor library etc speeds things up tremendously. So if we can offer a library to interface with this chip it will drive costs down much more.I have already gotten interest from 3 other projects that say yes, it would make things easier and I am looking to contact more in the coming week to see what would be interesting for them.Claims a 40-60% development cost savings in addition to noise reduction and other benefits.https://www.sigenics.com/blog/7-asic-integration-benefitsCustom Silicon Solutions claims 125-250k NRE expenses for a custom mixed signal asic and 50% savings on components.http://blog.customsiliconsolutions.com/uncategorized/custom-asic-development-cost-considerationsTantech-Again the argument that because there are $2000 350mhz options we don´t need $1000 options for 1GHz is stupid. Also you are assuming that companies don´t want to save money. And you are making that assumption before even knowing what savings are possible. The hypothetical specs I mentioned ARE NOT SET IN STONE as I have mentioned before but you keep ignoring. You would rather push breaking the law. If you don´t like it don´t participate, If one of these chips gets developed you don´t have to use it or buy a product using it.It is stupid not to innovate just because YOU are happy hacking your oscilloscope. There are plenty of arguments to make against this but none of yours are valid.If someone had asked does anyone need a DDS chip like the AD9850 you would have said no way, you can already build that yourself. But a ton of signal generators use it. Or even better the BA5937AFP which is a 4 Channel driver chip used in DVD drives. It is just a couple OpAmps but for some reason every DVD and CD drive uses those chips instead of putting 7 OpAmps in their drive.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 11, 2020, 03:22:18 am
content: I'd hate to work in R&D with bosses who think that R&D has a predictable cost. Say someone walks into the room and says, $250k to start and finish this design. Go!Idiocy! That is the breed of MBAs we (technocrates) allowed to grow and start speaking and even have an attitude. They have a language with words like "SME" Subject Matter Expert, because they themselves have no clue about a subject, only about accounting. This SME word must freaking die in history. "SME"s should ever work for bosses who are technical or scientific themselves. Not for those who have no back history of doing the homework and sweating on the Subject Matter.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 11, 2020, 04:06:35 am
content: Did you read the last post and that is it or did you need me to explain it more clearly? Nobody assumed any cost was set in stone in addition to most talk having been of costs 4 times as high. I was stating that with their reported costs for the development coming to $250k dollars and that 250k being a 50% savings would conclude that if you spend $500k in parts you would recover your money in 1 year. It was an attempt to make it easy for people to understand since. People essentially keep saying you can´t make money by paying less for parts.Id hate to work with people who every time you say "We could do this, or we could do that", that it is an absolute. I say we need to see what is needed but a chip with 4gsps would offer these possibilities and their answer is 4gs exists, 4 gs is not possible, Rigol does 4gs, nobody can do 4gs and not go broke. Nobody needs 4 gs.Do you see how that is not productive? Maybe that is the difference between management and a worker. The worker has been told what to do so long he can only think in terms of definites and not maybes.You have to explore and discuss what is possible, what makes sense, what are the trade offs, what are the numbers.People keep making assumptions and when I show examples of their assumptions being wrong they again assume that those examples now apply to this.I just wish that the idiots would learn to keep it to themselves. If they disagree good. Don´t waste my time with it though.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 11, 2020, 04:16:02 am
content: When last time Europeans (nations occupying Europe geographically) made an Asic with more than 100 transistors ? Simple question.Edit: I mean NEW asic design

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: January 11, 2020, 04:38:18 am
content: So THIS is how those clueless KickStarter projects get born. I often wondered.Obviously, the first thing you need to get people on board is some people skills. Find the right people, and listen to what they saying. Telling the engineers how to do their job never works out.Maybe the OP needs to post to thatotherwidely respected electronics forum were the real experts are, instead of nay saying fools

author: daqq
author_rank: Super Contributor
timestamp: January 11, 2020, 07:47:38 am
content: Quote from: unitedatoms on January 11, 2020, 04:16:02 amIgnoring the fact that there are several major semiconductor manufacturers based in Europe (ST, AMS...), have foundries (Global foundries, ST, AMS, On Semiconductor, Ti...), have R&D offices here (even more), then that only leaves the little players. Given that that sort of thing happens pretty often, I'm guessing last Tuesday.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 11, 2020, 07:58:43 am
content: @daqq. Thank you. I did not know. And I am exaggerating. BTW, I checked and found that Global foundries is US company. Never heard about them. Anyway. I do not see Europe as a place where any new semiconductor development is happening. It is just a perception of random internet person. Not a true fact. You presented facts, I looked and saw.Well. In my world, there is no NEW semiconductor development happening in anywhere except USA or perhaps South Korea. Nothing. May be all those silicon developers in Europe are attending their jobs, work, come back home. And no effect is felt anywhere. The progress of things in 21st century is pathetic. The guys in Europe are faking each to other, because they have learned how to fake the things recently. In USA the fakery was popular and was quickly unlearned long before.

author: daqq
author_rank: Super Contributor
timestamp: January 11, 2020, 08:11:38 am
content: Quote from: unitedatoms on January 11, 2020, 07:58:43 amYup, with foundries and R&D offices all over the world. They Like most notable semiconductors.https://en.wikipedia.org/wiki/GlobalFoundries#Fabrication_facilitiesQuote from: unitedatoms on January 11, 2020, 07:58:43 amMust be an interesting world where China, Israel and a host of other places do not exist.Quote from: unitedatoms on January 11, 2020, 07:58:43 amYeah, I mean, we just have the equivalent of a supercomputer of the year 1995 in our pocket, there are 10+ GSPS COTS ADCs out there, and 16GB of RAM is common. Where's my damn' flying, semi-sentient AI controlled, brain connected car!?

author: Kilrah
author_rank: Unknown
timestamp: January 11, 2020, 09:12:09 am
content: Quote from: excitedbox on January 09, 2020, 10:09:49 pmThey would not boycott/sue you for designing an OS, but put anything they have a patent on in either intentionally or by mistake and they'll jump on you right away.Point is, it's likely you can only make a relatively simple IC that might not be stellar, becasue all the little tricks that can make it better are patented.

author: iMo
author_rank: Super Contributor
timestamp: January 11, 2020, 09:25:06 am
content: Back to the topic before Dave closes this thread13y back you would hardly expect you may get 16ch logic analyzer with 200MHz sampling rate for $50 incl shipping. I was the early adopter of theOLS- one of my best investments - after the hw was created (and still sold afaik) it took the community 1-2y to fine tune and enhance the fw in the fpga and mcu, and another ~5y of rather slowish development of the client app. Now you have a capable LA handy.If somebody produced an open sourced hw on say 10x5cm 4 layer pcb with 2ch 1-2Gs/s, 8bit res, FPGA+256MB ram and an usb connectivity for say $50 incl shipping, I would bet the community will do a steep learning curve and in 1-2y you would have an useful instrument handy. GUI in the PC/tablet.

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: January 11, 2020, 11:41:09 am
content: Quote from: imo on January 11, 2020, 09:25:06 amThe "Open Bench Logic Sniffer" is not actually Open Source, despite the description. It has max sampling rate of 200MHz. There is not going to be a $50 incl shipping board meeting the specs you describe, that's just a dream.Talking of Dave, the OP should ask him to run through the proposal and give his opinion.

author: ogden
author_rank: Super Contributor
timestamp: January 11, 2020, 12:28:10 pm
content: Quote from: unitedatoms on January 11, 2020, 07:58:43 amEver heard of ARM?

author: aheid
author_rank: Regular Contributor
timestamp: January 11, 2020, 12:32:02 pm
content: Quote from: imo on January 11, 2020, 09:25:06 amWhat kind of ADC would you put in that thing? Cheapest name-brands I can find blows the $50 budget for just the ADC alone, for example the HMCAD1511 used in the Siglent SDS-1104x scope is $49 per 100 qty and that cuts down to 500 Msps when running two channels. Then again, I'm just a n00b so curious what else is out there.edit: Just for fun I checked the FPGA used in that scope, it's about $120 in low quantities. So just between the ADCs and FPGA the BOM cost is half the price of the scope. Though if post-processing and display etc is handled elsewhere, I assume a much cheaper FPGA can be used.:https://youtu.be/Kay4Jk2DHuE?t=532:https://github.com/360nosc0pe/fpga/blob/master/projects/sds1104xe/create_project.tcl#L20:https://www.digikey.com/product-detail/en/xilinx-inc/XC7Z020-1CLG484C/122-1850-ND/3925759

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 11, 2020, 01:19:33 pm
content: Quote from: ogden on January 11, 2020, 12:28:10 pmARM is not a semiconductor company, also its Japanese.My point is that for certain industries there is certain geographies. I see someone (lets make it exact, some German person) out of place, then it causes a dissonance. I start to re-evaluate what do I know about this kind of relevance. Say if someone in 1960s in Liverpool UK nonchalantly suggests to roll a music band, I do not see a dissonance, because it is their local culture, the industry, that's what they do. When I see a German pushing for IP project I can not connect few dots, there is some dissonance. It is not how such person is supposed to look like. There is some underlying lie there. And I can not put a finger on it and start throwing random pokes. Was is that fact that credentials are based on fact that his father is Queen of England who bakes semiconductors every Friday, or some arithmetical quantities of dollars in high thousands or millions even. Something does not look natural. And I have to wake up and try to fugure out what place or time or person I did expect to be in such position.

author: ogden
author_rank: Super Contributor
timestamp: January 11, 2020, 01:41:27 pm
content: Quote from: unitedatoms on January 11, 2020, 01:19:33 pmARM is UK company based in Cambridge,developingsemiconductors in Europe.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 11, 2020, 01:42:20 pm
content: Quote from: ogden on January 11, 2020, 01:41:27 pmThey develop papers. And owned by Japanese. And I am exagerrating

author: ogden
author_rank: Super Contributor
timestamp: January 11, 2020, 01:52:40 pm
content: Quote from: unitedatoms on January 11, 2020, 01:42:20 pmJapan owns biggest part of US public debt as well. So what?

author: Marco
author_rank: Super Contributor
timestamp: January 11, 2020, 02:01:16 pm
content: ADCs really show the death of discretes. The integrated ADCs in my cable modem would probably cost 10x the modem to buy discrete.Anyone with volume does it themselves, what's left is just too small not to get ravaged by boutique prices. Ah well, can't always be lucky when hitchhiking ...

author: wraper
author_rank: Unknown
timestamp: January 11, 2020, 04:29:56 pm
content: Quote from: unitedatoms on January 11, 2020, 01:42:20 pmThey develop silicon design for particular manufacturing processes which can be integrated into chips. And then it likely will be produced at TSMC in Taiwan. Where BTW basically all discrete GPUs are made (Nvidia and AMD).

author: daqq
author_rank: Super Contributor
timestamp: January 11, 2020, 04:42:15 pm
content: Quote from: unitedatoms on January 11, 2020, 01:42:20 pmI'm not sure if it's best to scoff at fabless semiconductor companies, Xilinx, AMD, Nvidia, Quallcom, and many other are fabless, yet their influence is massive and their product lines are REALLY important. Developing IP is a MAJOR factor in the semiconductor industry. The majority of large companies are owned by other faceless international investment companies and funds (who in turn also have interesting ownership). ARM was sold to a similar company, SoftBank Group, it started in UK.QuoteYes, a proper German person will not be dabbling in semiconductors, he will be eating schnitzels by the dozen whilst brewing craft beer and sneakily preparing to attack Russia.

author: nctnico
author_rank: Super Contributor
timestamp: January 11, 2020, 05:48:33 pm
content: Quote from: unitedatoms on January 11, 2020, 07:58:43 amAs stated before: there are many European chip developers. Not just big ones but also many smaller ones. Take FTDI for example. Many (like NXP for example) also have offices in China where they do development. And last but not least: the majority of the lithography equipment used for chip production comes from Europe.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 11, 2020, 09:43:45 pm
content: This guy doesn`t know that ARM is in the UKThere are more semiconductor companies outside the US. Even the ones who are now in the US are in large part not US companies. LG, SAMSUNG, Toshiba, Western Digital etc are all Japanese, Korean, Chinese, German, English, Israeli, and so on. Most of the Engineering Labs that design 99% of the chips around the world are outside the US.The US has maybe 10-12 Big companies that got big by buying up a bunch of companies to make 1. The rest of the industry is International.And then people wonder why I don´t think this is the place for a project like this. Because these are the type of people that get to fill a thread with nonsense. Ignoring the fact that you can barely have a conversation on a forum let alone organize an ENTIRE COMPANY.I think it is time to abandon this thread. I am gonna edit the first post with just contact info on how to get involved in this project and then the idiots can do what they want on the rest of the thread.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 11, 2020, 09:57:02 pm
content: Quote from: donotdespisethesnake on January 11, 2020, 11:41:09 amThat is a good idea. I agree $50 including shipping is way too low for anything containing a chip that is also useful for much higher end stuff.I am still working on writing up a proper description of what the goal even is. The original post was just me asking peoples opinions which attracted all the 5 year olds, who can´t think anything besides the USA #1 propaganda they have been fed all their lives. I wish one of these days they will spend a few weeks outside the country and just realize how wrong they have been.

author: ogden
author_rank: Super Contributor
timestamp: January 11, 2020, 10:18:50 pm
content: Quote from: excitedbox on January 11, 2020, 09:43:45 pmDon't. By doing so you essentially will destroy this thread and show disrespect to those who spared their time to comment.  Thou damage is already done. You already insulted many much more experienced forum members than you are. I will ignore you from now so you can live with your Dunning Kruger syndrome and dream your impossible dreams happily without my distraction

author: nctnico
author_rank: Super Contributor
timestamp: January 11, 2020, 10:20:17 pm
content: Quote from: ogden on January 11, 2020, 10:18:50 pmI agree. This forum is a very good place to discuss and several good designs for test instruments have been born on this forum already.

author: ebclr
author_rank: Super Contributor
timestamp: January 11, 2020, 10:23:12 pm
content: " then the idiots can do what they want "If you leave the thread, the thread will be cleanup up of Idiots. Please do that

author: ogden
author_rank: Super Contributor
timestamp: January 11, 2020, 10:45:53 pm
content: Whole post for archival purposes:Quote from: excitedbox on January 09, 2020, 05:59:28 am

author: excitedbox
author_rank: Regular Contributor
timestamp: January 11, 2020, 10:51:37 pm
content: You mean I would be disrespecting the disrespectful idiots that keep wasting space by not reading and making the same baseless assertions repeatedly. Then disregarding any evidence disproving their assertions and nit picking hypotheticals as facts. Now they want to complain when I don´t want it to continue. Wasting my time. Anyone seeing this project for the first time would have to read through 3 pages of BS just to see where things stand. That will just drive people away.As you can see any valid criticism has been treated with respect and considered. I appreciate those that do want to contribute. I invite anyone to join on discord in an effort to make this a reality. Even there I will have to set up multiple chats for public suggestions and discussions and true insiders and partners who will have access to confidential information. This thread holds no importance to this project and letting it die is the smart thing to do.The main work for those designs did not happen on the forum. The forum is used for posting updates and discussion but not for doing the actual work. There is a big difference. If you can´t accept that Im sorry. Maybe you can convince Dave to conduct all discussions and work between him and colleagues/employees/partners on the forum. Even asking that is absurd. I am also not gonna spend hours each day arguing with people over which country has the bigger chip industry or the legality of exploiting DRM restrictions on software licenses.If they don´t think an ASIC is needed, lets end the RISCV project too. we don´t need another processor we have Intel and AMD and they have been dropping prices recently anyway. Lets end all Linux development we have Windows and Win10 is free now. Wordpress (Runs 95% of all websites) is no longer needed, everyone can just code their entire site from scratch.PS. Germany is the 4th largest electronics manufacturer.https://www.trade.gov/topmarkets/pdf/Semiconductors_Germany.pdfGood idea on archiving the original post. I would have forgotten to do that. Like I said anyone is welcome to join the discord as long as it remains productive.

author: nctnico
author_rank: Super Contributor
timestamp: January 11, 2020, 11:32:40 pm
content: Quote from: excitedbox on January 11, 2020, 10:51:37 pmOff-topic rants by the OP also do that. If you want a thread to to stay on-topic then stay on-topic yourself. Lead by example.

author: David Hess
author_rank: Super Contributor
timestamp: January 12, 2020, 02:03:04 am
content: Quote from: excitedbox on January 11, 2020, 12:07:26 amYou not only have to compete with existing designs which have the advantage of economy of scale allowing a fully custom ASIC but existing programmable logic based designs which did *not* justify an ASIC. Based on HP and Tektronix using the same fully custom ICs for such long periods of time that it held back features and performance, I think ASICs were marginal even for them except at the high end.Is there something that you cannot accomplish economically with an FPGA now? I have looked into this problem in detail before and with a small or perhaps no loss of performance, I am sure that an economical FPGA based design is feasible now if the hardware and software is partitioned correctly. Most of the flaws in commercial designs seem to be on the software side.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 12, 2020, 06:35:46 am
content: Xfab has open source ip on this site and also includes a handy little cost calculator that shows just how cheap it is for raw dies. Obviously you gotta package them too but it is pretty cool looking at all the microscope pictures of the transistor stacks.https://www.xfab.comYou are right that software is a major expense because salaries stack up quickly. That is why the 2 prong approach with a open source scope framework. The only reason those Chinese Logic Analyzers are so cheap is because they stole the software fro that other project.Right now a lot of projects are not viable because of the high cost for fast ADCs and DSPs etc. Each chip is not just associated with a manufacturing cost right now but also with a profit margin, marketing budget, and operating expenses for the manufacturer and that reduces the profit you can make on your product.You do bring up some valid points. Rigols 7 in 1 scope would probably not have been possible without a custom asic so it allows them to add features that wouldn´t exist otherwise. But that is also a plus for competition. As an opensource project we don´t have to compete with anything since it is not about making money. Part of the "profit" is helping people access equipment they couldn´t otherwise. Right now a 2ch1Gsps ADC costs over $400 that is not a cost many consumer products can carry. If that chip comes down in price we might see a whole host of new products on the market.An FPGA is just not an efficient way of doing things. Yes it is great when you need to customize a circuit but a chip is already 70% interconnects. When you add all that switching it becomes even more.even Intel eAsics which have a bunch of blocks and only the top layer is customize robs you of one out of 6 layers. With each layer you build the yield drops substantially too driving costs up more.We need to focus on finding out what is on one of these custom Asics besides a DSP and ADC and what modules manufacturers are currently implementing on the FPGA. Only then can we see if it is worth it and what it would take to make it reality. Everything else is useless right now. None of these arguments are real without having real world facts.

author: tautech
author_rank: Super Contributor
timestamp: January 12, 2020, 07:52:27 am
content: Quote from: excitedbox on January 12, 2020, 06:35:46 amHow can that be when something just like that is the basis for a SDS2000X-E series DSO retailing @ $620 ?

author: EEVblog
author_rank: Unknown
timestamp: January 13, 2020, 08:13:04 am
content: Quote from: excitedbox on January 09, 2020, 05:59:28 amWow, are you serious?Do you have any clue how much scope you can buy for under $400 these days?

author: EEVblog
author_rank: Unknown
timestamp: January 13, 2020, 10:22:36 am
content: Quote from: DaJMasta on January 09, 2020, 08:25:38 amThis is why many scopes use a the Xilinx Zynq as it combines an ARM applications processor and an FPGA. More than powerful enough for decent performance entry level scopes.

author: EEVblog
author_rank: Unknown
timestamp: January 13, 2020, 10:28:28 am
content: Quote from: unitedatoms on January 09, 2020, 04:36:48 pmAnd only if you show a working prototype first, like the whole working scope built from an FPGA and ADC's etc. Then you can say "We need $X million to make this cheaper with an ASIC. You can't just say "Give us money to make a scope ASIC and we'll work out the details later".

author: EEVblog
author_rank: Unknown
timestamp: January 13, 2020, 10:33:19 am
content: Quote from: excitedbox on January 09, 2020, 10:31:31 pmYes, but now you can get hacked 200MHz 4 channel scopes for under $400.Anything much higher bandwidth and you reach the usable limit of passive probing technology.

author: EEVblog
author_rank: Unknown
timestamp: January 13, 2020, 10:34:13 am
content: I've unlocked this thread because I think it's hugely interesting, please play nice.

author: EEVblog
author_rank: Unknown
timestamp: January 13, 2020, 10:38:01 am
content: The first thing you need to do before even considering such an ASIC is tofully itemise the BOM costfor current designs and find out how much you can actually save with this magical custom ASIC. You might very well find it's simply not worth it and doesn't offer enough advantage.And I'm talking BOM cost down to every last screw and knob.If you haven't done that then the whole thing is a folly.

author: EEVblog
author_rank: Unknown
timestamp: January 13, 2020, 10:41:27 am
content: Quote from: excitedbox on January 11, 2020, 10:51:37 pmThat right there is your problem. You can simply chose to ignore such comments and not respond to them. This is how to forum works, you can direct the discussion by only talking about what you want to talk about and ignoring everything else.

author: iMo
author_rank: Super Contributor
timestamp: January 13, 2020, 11:05:48 am
content: So what would be a BOM cost estimation for the first version:1. 2 channels (ie. parts similar to the Rigol 1054) - simple AFE and the 1x 8bit ADC (500M/1G samples/s)2. an FPGA capable enough to process the data and push the data into say 4x64MB sdrams (thus 64bit data access, max 128MB/sec write speed)3. 4x 64MB sdrams4. a high speed USB interface (an MCU or embedded into the above FPGA)5. 1GHz clock generator6. voltage regulators7. R,C,L passives8. 10x10cm 4 layer pcb9. 2x input BNC, 1x usb and 1x power connector (5V/0.5A).

author: EEVblog
author_rank: Unknown
timestamp: January 13, 2020, 11:09:14 am
content: Quote from: imo on January 13, 2020, 11:05:48 amThat's not a bench oscilloscope. If oyu want to revolutise the bench scope market and get the likes of the big payers to buy in then there has to be substantial cost savingon a proper conventional bench oscilloscope product.Not a bare bones hobby PCB only scope.

author: iMo
author_rank: Super Contributor
timestamp: January 13, 2020, 11:17:36 am
content: Quote from: EEVblog on January 13, 2020, 11:09:14 amI don't want. I want to know what would be a BOM cost "estimation" for the above hobby PCBPS: 1k quantity for example.

author: aheid
author_rank: Regular Contributor
timestamp: January 13, 2020, 12:18:33 pm
content: Quote from: imo on January 13, 2020, 11:17:36 amFor reference, the ADC used in the Siglent SDS-1104x (it uses one per pair of channels) is, AFAIK, theHMCAD1511. The per-channel VGA isAD8370and per-channel ADC driver isADA4932-1. For two channels, you're looking at about $70 just between those parts.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 13, 2020, 12:21:08 pm
content: Quote from: EEVblog on January 13, 2020, 10:34:13 amand i think you are wise in doing soits not nice when mod can reply without letting the defendent draw their opinion. as someone said everybody has a right to their own opinion... i dont care if this thread is locked or not (i have no slight knowledge in ASIC) but it keeps popping out with admin's replies made me WTH. btw i think one of OP's main point is this...Quote from: excitedbox on January 09, 2020, 05:59:28 ambut imho, it will take someone with more knowledge in this area to make a start. simply saying "hey come on lets make this!" thread will not go anywhere. when someone starts with something usefull, the rest will join in. maybe for the start, doing in FPGA maybe? ASIC is too much of a take, as many others mentioned about the cost etc etc.. but as i said, i dont really care much its not my league, i already got a decent high end scope from used market. so if anything i have to say... lets scour the feabay for this kind of gems... ymmv. peace no war carry on gais.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 13, 2020, 12:45:59 pm
content: Yup yup yup. Wise thing obviously would be to start with a prototype design with off-the-shelf parts (ADCs, FPGA, etc.) Once there's something working, there can be a subsequent phase of trying to simplify it as much as possible. Then once it's there, going to an ASIC (with all the pitfalls we talked about) could be considered. But going for it right from the start would be a mistake, and as Dave mentioned, would make the crowdfunding campaign hard anyway, as such an ambitious goal without any prototype to show? Not gonna work.

author: ogden
author_rank: Super Contributor
timestamp: January 13, 2020, 12:49:04 pm
content: Quote from: aheid on January 13, 2020, 12:18:33 pmRight. Obviously much better idea than scope ASIC is ADC Kickstarter project

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 13, 2020, 02:25:15 pm
content: Quote from: aheid on January 13, 2020, 12:18:33 pmone maybe can get cheaper 50% discount at best by buying in say 1000pcs qty, but $35K? only for that? maybe we are looking at $100K (if using FPGA uneducated guess) excluding headache to find and deal with assembler and mold maker (enclosure) its time for a new brand name company, maybe Riglent? or Siglol? or more precisely... SickLoL.. jk..Quote from: blueskull on January 13, 2020, 12:58:23 pmlets forget sampling scope which can be done with KSps or MSps ADC at tens of GHz BW, its different beast people have done it at cheap. but when you said mainstream players are using massive array of ADCs? i dont think so. i believe its another custom ASIC in one package, maybe massive array they are, but they are in one package, and in one IC... (pictured below, unluckily blocked by a heatsink)Quote from: blueskull on January 13, 2020, 12:58:23 pmif you refer to this thread,Lecroy DDA-5005 DSO TeardownAFE for high end (50 ohm) scope is quite simple, i guess anyone can do with a free EM simulator and proper PCB materials... but once the signal goes into the ADC/DSP/ASIC/whatever it is, thats where the massive array of money is... there are few of them, from ADC/AFE to DSP/ASIC to RAM down the line, those the unobtaniums...ps: i once tried to figure out the possibility of diy high sampling rate DSO, 10x whats the venerable DS1054Z can, using their brilliant idea of interleaving slower ADCs. the first study is to look at ADC cost in digikey, luckily that alone made me teared the idea into pieces without further wasting my time.... yeah agreed, let the man do their job.. let me tinker with arduino...

author: OwO
author_rank: Super Contributor
timestamp: January 13, 2020, 02:38:02 pm
content: Quote from: Mechatrommer on January 13, 2020, 02:25:15 pmThat's where the mistake is. I know for a fact from working with a startup that FPGA prices at distributors are typically over 10x what you get direct from Xilinx at even small batch quantities, and ADCs may be similar.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 13, 2020, 02:57:04 pm
content: Quote from: OwO on January 13, 2020, 02:38:02 pmYes... but can you deal with Xilinx or AD directly if you're a small fish (regardless of batch quantities)?

author: OwO
author_rank: Super Contributor
timestamp: January 13, 2020, 03:02:55 pm
content: ADI probably not, but in my experience Chinese chip vendors are more open to talking to random small businesses, so I'm going to investigate that direction first.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 13, 2020, 03:04:58 pm
content: Quote from: OwO on January 13, 2020, 02:38:02 pmi'm glad if you can share where we can get GSps ADC and parts etc at 1/10X of digikey, it will surely make diy/os designs bloom.

author: ogden
author_rank: Super Contributor
timestamp: January 13, 2020, 03:20:01 pm
content: Quote from: SiliconWizard on January 13, 2020, 02:57:04 pmDefine small fishAFAIK no matter you are small or big fish - quarterly volume and ability to commit to your agreements matters. If interested - ask:https://www.xilinx.com/about/contact/contact-sales.html

author: aheid
author_rank: Regular Contributor
timestamp: January 13, 2020, 03:21:00 pm
content: Quote from: Mechatrommer on January 13, 2020, 03:04:58 pmSarcasm aside, I'd be interested in any such results. I tried searching on LSCS and such but couldn't find any.

author: iMo
author_rank: Super Contributor
timestamp: January 13, 2020, 03:31:56 pm
content: Digikey's or Mouser's $30 boutique price for an FPGA or an ADC (in US or EU) means in practice they buy for $5 in rather small quantities (like 1k). China is a different market - they mess with parts in millions quantities and they buy directly from manufacturers. It also could be the local distributors there are much less greedy than the other boutique shops.

author: ogden
author_rank: Super Contributor
timestamp: January 13, 2020, 04:02:23 pm
content: Quote from: imo on January 13, 2020, 03:31:56 pmDigikey/Mouser buy 1K for 5$/piece and sell for 30$ @1qty? I say BS unless you provide proof that I am wrong. Distributors do not work with such insane margins. HMCAD1511 mentioned here: AD list price 46$ @100, Digikey 55$ @100. You may get discount from AD sales, deal depends on you quarterly/yearly volume and your commitment. Shipments most likely will arrive from Digikey or Mouser anyway.

author: iMo
author_rank: Super Contributor
timestamp: January 13, 2020, 04:17:54 pm
content: "List price" means nothing. Everything else is subject to Contracts agreed between the parties and such agreements are usually Confidential

author: ogden
author_rank: Super Contributor
timestamp: January 13, 2020, 04:22:01 pm
content: Quote from: imo on January 13, 2020, 04:17:54 pmSo what you said about pricing means the same: nothing.

author: nctnico
author_rank: Super Contributor
timestamp: January 13, 2020, 04:29:38 pm
content: Quote from: ogden on January 13, 2020, 04:02:23 pmI fully agree. My experience: Once you get into quantities (say >100 pieces) the prices from Digikey, Farnell, Mouser, etc are pretty much the same compared to buying parts from a distributor. The added value of Digikey, Farnell, Mouser, etc is that you can buy small quantities c.q. are not bound to MOQs. Ofcourse you pay a premium for that but who cares for just a few pieces. In some cases that does result in weird pricing. Last time I bought ty-raps from Farnell I ended up buying 1000 pieces because that was cheaper compared to buying 300.When it comes to FPGAs pricing is even more muddy. You have to go to Xilinx with a project and they will give you a price. Recently I have been looking at Zync development boards and some boards are sold at prices below the single quantity prices on Digikey. Not sure what is going on here; maybe chips are sold at a loss to keep the competition away or they may be untested / rejects.

author: ogden
author_rank: Super Contributor
timestamp: January 13, 2020, 04:36:48 pm
content: Quote from: blueskull on January 13, 2020, 04:24:45 pmNo. You guys are inventing reality on the goDistributors do not buy for lowest possible price OEM can agree upon.https://www.ebnonline.com/shedding-light-on-electronic-component-pricing/#

author: magic
author_rank: Super Contributor
timestamp: January 13, 2020, 04:44:03 pm
content: Rumor has it that some manufacturers will ask different prices depending on the market you are from. They may sell cheaper in China to compete with Chinese alternatives and recoup it by asking more from those not willing to try Chinese alternatives.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 13, 2020, 05:17:06 pm
content: sorry gais your mass order hunt is moot from my eyes from wherever you can get them. lets say you can find a $1 1GSps ADC in 10K qty later on... who want to play R&D with 10x $100+ ADC?ADC081000CIYB (assuming its in stock)10x128-LQFP in interleaved trick? thats just the ADC. and what DSO/RF TEA are you going to verify them with? i know some may have a brilliant idea of using the venerable ADC used in DS1054Z to get 10GSps from 40x overclocked 200MSps to 250MSps system...ADC08200CIMTit doesnt look too much saving by any stretch there, for the sole R&D purpose. and aligning 40 x 24-TSSOP is going to be more fun, esp the 40x interleaved signals. i'm sorry if it looks like an insult but i'm just giving my (bad) idea here, i'm trying to help with the least appearance damage to the end product, and the least moral and brain damage to the interested party. but luckily, i'm very bad at giving advice in this kind of field. maybe another (worst) advice is... ASIC ADCs? with biasing and adjustable attenuation built-in?...

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: January 13, 2020, 05:23:14 pm
content: These proposals always end up discussing logistics of how to source cheap parts, and how to get a decent plastic case that doesn't look horrible and doesn't cost $10k for tooling.As a Open Source type hobbyist, I wouldn't mind paying for a "some assembly required" kit, but quite obviously I would expect to save some money vs say a Rigol DS1054.If you are talking about a commercial quality scope in a nice box that engineers at SMEs would buy, you are talking about a startup company attempting to compete with low cost Chinese suppliers, which has no hope in hell. Also, the idea that an Open Source ASIC would enable companies to create low cost scopes, that is rather fanciful.Anyway the two questions I would try to answer:1) Can I make anything for $200, that would be better/cheaper than a commercial scope? (Ready to use in a box, excluding markup and shipping).2) How much would it cost to make a decent entry level scope electronics that anyone would buy, even if just to say they have an Open Source scope?There was a reference earlier to Open Logic Sniffer, that project is dead/closed, probably killed by the $5 Saleae logic clones.

author: nctnico
author_rank: Super Contributor
timestamp: January 13, 2020, 05:38:45 pm
content: Quote from: donotdespisethesnake on January 13, 2020, 05:23:14 pmTrue. Part costs are completely irrelevant at this point as the engineering effort in the software dwarfs any effort needed for the hardware. A project starting with looking for the cheapest parts never ends well (or never ends at all).QuoteI don't think an open source project should aim to compete with low cost equipment. The advantage should be in having an open software platform which people (companies) can extend and build upon. FPGAs fit much better in such an approach than a fixed function ASIC.One of the big features missing from oscilloscopes is the ability to extend the features by writing plug-in modules. Nowadays every manufacturer is implementing the same feature from scratch. That is just idiotic and a complete waste of time.

author: ogden
author_rank: Super Contributor
timestamp: January 13, 2020, 06:06:29 pm
content: Quote from: nctnico on January 13, 2020, 04:29:38 pmRight. FPGA (and fast ADC's) of your choice may fall under export control restrictions as well. That's why they want to know more about your product and to whom /where you will be selling it.QuoteManufacturers often sell devboards (including their BOM) at zero profit or even below that. Prices for older chips tend to increase rapidly. Hobbyist looking for LQFP FPGA that were introduced 5 years ago, may get wrong impression about FPGA pricing. (example that may not be your case)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 13, 2020, 07:09:55 pm
content: Don't forget that DK/Mouser/etc. have a default catalog price, which is basically your optimistic "thanks for looking!" price. As mentioned, they participate in sales and supply contracts just as much as anyone, and that is where you can negotiate better prices.My one example: a modest (80MSps 12b 2ch) ADC by National, we were considering improving. Via FAE, we picked an ADI part with twice as many channels and a fraction of the total operating power (1.8 vs. 3.3V, among other improvements), and they offered it for a lower per-part cost at the quantities we proposed. So, they improved on BOM cost alone, but also offered considerable economy with the bigger and better-performing part. The manufacturer in turn negotiated with Digikey, who quoted the price to us.It's also my understanding that DK is very competitive in passives, when you're buying them in boxesor palletsat a time (i.e., millions of units). Not much of an economy the home gamer can take advantage of, but it shows they're not all about your top dollar.Tim

author: tautech
author_rank: Super Contributor
timestamp: January 13, 2020, 07:41:49 pm
content: Quote from: EEVblog on January 13, 2020, 10:34:13 amThanks Dave, yes it is interesting yet it might seem the OP has yet to get a full perspective on what's already in the marketplace.Any new ASIC will need to be positioned for the upper end of mid-range products such is the capability of existing off the shelf solutions currently available. Only then the economies are likely to offer a ROI.

author: ogden
author_rank: Super Contributor
timestamp: January 13, 2020, 08:15:18 pm
content: Quote from: nctnico on January 13, 2020, 05:38:45 pmLow end market is only chance for hobby/startup/Kickstarter projects because buyers of hi-end/expensive stuff would not risk to source their equipment from nonreliable sources, not to mention KickstarterThey would pay 2x price or more just to be assured that product or it's support will not suddenly disappear one day. After years when you are big fat and famous - then you can look for hi-end market. Hoping to be successful in hi-end from day one - forget it.QuoteCould not agree more. You pretty much nailed it.

author: iMo
author_rank: Super Contributor
timestamp: January 13, 2020, 09:02:41 pm
content: If I were for example Rigol I would offer to the EEVBLOG community an "empty" 1054Z, or 2072A for the production costs + shipping. No fw, no warranties, no support, just naked (hw without fw) box with a schematics. And you may play with it as you wish.1054ZN $100 + shipping2072AN $200 + shippingWhat would be the response of the community? Will you buy it?

author: nctnico
author_rank: Super Contributor
timestamp: January 13, 2020, 09:40:54 pm
content: Quote from: ogden on January 13, 2020, 08:15:18 pmI wouldn't say that too quickly. It just takes offering something which isn't in the market. Extendability is one example.Another example: CERN has developed a time synchronisation protocol + open source hardware. This is pretty much a niche application but it is gaining traction in the market and nowadays there are several commercial companies offering solutions around it. Actually, having an oscilloscope platform which could support this timing protocol would be very interesting. Think about being able to do fully synchronous measurements with a long distance in between.

author: thm_w
author_rank: Super Contributor
timestamp: January 13, 2020, 11:36:48 pm
content: Quote from: imo on January 13, 2020, 09:02:41 pmDoesn't make sense because:- The firmware cost to them is essentially $0 at this point. Maybe some cents of production time to load it.- Support is minimal, probably under 5% of the cost ($20 off retail price). Its also a legal requirement in a number of countries.- Market is too small.- People might hack it and figure out how to load the existing FW, meaning you are competing with your own products.

author: ogden
author_rank: Super Contributor
timestamp: January 13, 2020, 11:44:09 pm
content: Quote from: nctnico on January 13, 2020, 09:40:54 pmWithout demand it does matter - there is something in the market or not. I think basics including serial decode are pretty much covered in the modern lo-end scopes (Rigol 1000z series and alike), business buyers usually are looking for one-stop shopping of everything - hardware and addons (like signal/jitter/eye analysis and so on). As it was said in another already dried outopen source scope thread- I want to debug just my circuit using scope that do not need debugging itself.QuoteBad example. CERN is THE biggest science projects on Earth, far beyond "fat and famous" (2500 staff, ~12000 contributing scientists).

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 12:11:44 am
content: Quote from: ogden on January 13, 2020, 11:44:09 pmNobody said you need to do any debugging before you can use the oscilloscope. The base functionality should all be there in order to create momentum. However, if you need extra functionality you can create it. It is more or less the same with any piece of open-source software. 99.9% of the people will use it as-is and the remaining 0.1% will add extra functionality to it. Nothing wrong with that.IMHO it would be interesting to start a Kickstarter to raise money to get basic oscilloscope firmware (software + FPGA) development going by hiring a bunch of software engineers and getting a few Zync FPGA development boards.

author: OwO
author_rank: Super Contributor
timestamp: January 14, 2020, 03:16:24 am
content: Quote from: nctnico on January 13, 2020, 05:38:45 pmI don't know why you keep saying parts cost aren't important, but in projects like these with one of the most cost sensitive market you can imagine (hobbyists), parts costs literally make or break a product. Look at an example, the NanoVNA. Basic math shows it's worth spending ONE ENGINEER YEAR to save $1 USD of BOM cost, with payback being just over one year. Yes, every dollar you save on the BOM pays for one full time engineer who can then bring far more value to the product.

author: OwO
author_rank: Super Contributor
timestamp: January 14, 2020, 03:24:47 am
content: As someone who's worked closely with small corporations that are actually selling to hobbyists, I can say from observation that there is a single absolutely most important thing that the market cares about, which is bang for buck. An example to look at is the FNIRSI-5012H. Even with absolutely shit software people still keep buying it, and someone on this forum is even working on replacement firmware for it, completely on his own dime! Now imagine if it came with primitive but open source software, people would be on it even faster. In the end value/price is what matters.

author: ogden
author_rank: Super Contributor
timestamp: January 14, 2020, 03:50:50 am
content: Quote from: OwO on January 14, 2020, 03:24:47 amSure. How do you define value of the scope? Just number of oscilloscopes per buck or what? If we take in account: scope bandwidth, number of channels, ease of use, physical controls, software, gui, screen size, safety and so on, most likely winner will be some low-end Owon, Rigol or alike. As we already (hopefully) agreed, open source/crowdfunding approach can't compete in this league.

author: OwO
author_rank: Super Contributor
timestamp: January 14, 2020, 04:04:58 am
content: The OP's intent is offering more raw performance per buck, so mainly bandwidth, analog performance, sample memory, trigger POI, etc. That or offer DS1054Z level data acquisition functionality for less than $100. I think these are all doable. I have some basic idea of what kind of ADC prices you can get in volume and am already starting negotiations. But it's still up to our parent company whether they want to take the risk on a new product like this.

author: ogden
author_rank: Super Contributor
timestamp: January 14, 2020, 04:38:24 am
content: Quote from: OwO on January 14, 2020, 04:04:58 am100$? Are you sure?If result is Zynq FPGA + >=500Msps ADC + >=2 100MHz channels + I/O similar to rPI (Ethernet, USB, HDMI, parallel LCD) with basic scope software that supports variable screen resolutions, I'm in with my 100$ even if LCD is not supplied. Price point ofScopeFunIMHO is fail for hobby market, yet they somehow got enough backers. You never know For extra 50$ "advanced version" with buffered 16x logic input and 1x 50 Ohm + PGA/Attenuator for "mixed signal" and direct RF sampling SDR and Spectrum Analyzer functionality. - It may go like hot cakes then. Forgot to mention that it must run Linux - for better acceptance from open source community. With Linux you may get some "other customers" - because it can be used as low cost sampler as well.

author: David Hess
author_rank: Super Contributor
timestamp: January 14, 2020, 06:04:32 am
content: Quote from: DaJMasta on January 09, 2020, 08:25:38 amMost modern DSOs implement triggering digitally after the digitizer in parallel with the memory controller essentially making it free. The only reason to include a dedicated trigger circuit is to support equivalent time sampling.Quote from: blueskull on January 13, 2020, 12:58:23 pmDo you mean Picotech? If so that is funny coming from them when they use integrated CMOS broadband preamplifiers from TI with 1000 nV/SqrtHz noise.Quote from: blueskull on January 13, 2020, 12:58:23 pmQuote from: Mechatrommer on January 13, 2020, 02:25:15 pmI disagree. It will be very difficult to compete on performance but modern DSOs are missing a lot of useful features which would be cheap to add besides a sane user interface which does not make me want to puke.1. Real time network analysis, not just sweeping a sine wave while you get coffee, should be included if a waveform generator is included. Check out Cleverscope and the market they cater to. Is a magnitude/phase FFT and noise marker too much to ask? Apparently it is.2. If separate trigger hardware is included for equivalent time sampling, then it is a small addition to add true sampling capability with a separate auxiliary 50 ohm input. Or if digital triggering is used, the digitizer can be used as part of a centroid timing or transition midpoint timing time delay counter for picosecond resolution. A 100 or 200 MHz DSO would be greatly enhanced with low performance 4 to 8 GHz *random* sampling capability.Quote from: blueskull on January 13, 2020, 12:58:23 pmThe low impedance part of the signal path is much easier than the high impedance part because the later requires a good substrate which does not suffer from excessive hook. This is why you find high quality oscilloscopes with plastic substrates for the high impedance attenuators and modern DSOs and high voltage differential probes with bad transient response after a couple years because the FR4 substrate they used absorbed water.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 14, 2020, 07:14:06 am
content: Quote from: David Hess on January 14, 2020, 06:04:32 amlecroy 50 ohm scope has add-on adapter called AP-1M, to provide high impedance measurement, you can search eevblog i posted the internal of it, but only to few hundreds MHz BW. for GHz BW high impedance?i never seen one and not have a plan to even think about it. otherwise, i will have a very serious time (and probably financial) damage into it. but i think whats the point of trying hard to design HBW HiZ circuit when we can have or design active probe or such an AP-1M adapter in the next project phase?the AP-1M doesnt have special ASIC nor fancy ICs, only BJT/FET discreetes, but LeCroy charge them like K$, its like nuts when thinking about it. but when think further, they probably need to gather $ from surrounding ecosystem that they have introduced, to cope with ASIC damaged they experienced on the DSO side. this is i guess how they keep going..

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: January 14, 2020, 08:17:08 am
content: Quote from: unitedatoms on January 11, 2020, 07:58:43 amYes, it is not like imec, arguable the most high-ranking and advanced semiconductor research center in the world, is not european. Or, when you look at research output, that some of the most skilled analog/RF semiconductor research groups are in europe (don't know bout digital - not my field). Or that the 256 GS/s ADC that is the hart of that 110 GHz scope is in part developed in Europe. Or, ever heard of these rohde&Schwarz guys? I can go on...But I feel like there will be little point to go on here, since you made up your mind already

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 08:27:57 am
content: Quote from: OwO on January 14, 2020, 03:16:24 amIt really doesn't matter at this stage. First get software going and then look at which platforms it can actually run on. There has to be some traction from companies to contribute at some point. Starting oscilloscope development at the hardware end is absolutely the wrong way to take such a project on. Been there, done that.

author: iMo
author_rank: Super Contributor
timestamp: January 14, 2020, 09:28:52 am
content: QuoteHmm, I doubt so. Nobody will start to mess with fw/sw development unless he/she/it sees the hw first. Unless you are getting $$ for such an effort you will not do..The community willing to develop open fw/sw usually have to see tangible "something" they are attracted to, what they can buy cheap, and what is readily available such there will be a critical mass of people around it soon.An recent example: user atadarov and his effort with the cheapo stm32 scope..

author: ogden
author_rank: Super Contributor
timestamp: January 14, 2020, 10:04:21 am
content: Quote from: imo on January 14, 2020, 09:28:52 amThis is typical chicken & egg paradox of hardware+software development. I doubt community will be attracted to bare PCB. Someone have to design & code "version zero" software for community to take over.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 14, 2020, 10:11:21 am
content: there are top down type design, and there are called bottom up design. what i think nctnico trying to say is we start with FPGA design, let it receive some input, store it somewhere, do the triggering and output some data, and see how fast can it go... but then (to my knowledge) we also will need either to simulate the IO, or provide the suitable device to send and receive the data from the "FW". assuming the FPGA now can get 20Gbps throughput, then what? sooner or later the HW will expand to the real thing. ok maybe the GSps ADC can be replaced with Gbps FPGA to output some simulated or random data to the main FW/FPGA, and then stored in array of RAM etc, and output the 500KWfm/s data to the display. this we can call a demo platform to show that it can be done, that is phase one. costing of the complete system BOM can comes later in phase two, but it should be realistic depending on how cheap they can be mass ordered. now we can share knowledges if someone have a chap or factory next door that can source the parts at lowest price, and the logistics and all. then goes to the Kickstarter.. but i bet, the high end GHz GSps spec is not going to be cheap, maybe say 1-5K$, depending on how you see it, some people may say its better than 45K$ of mainstream brands... without the base (demo) platform to show, we can talk empty wind forever.

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 10:21:07 am
content: Quote from: imo on January 14, 2020, 09:28:52 amThat is why a Kickstarter campaign to pay for software and FPGA engineers makes so much sense. There is no use to develop hardware without software. There are plenty of FPGA development kits out there to do the software development on.Quote from: Mechatrommer on January 14, 2020, 10:11:21 amNo. Do not start with the FPGA design. Start with the software. Design the user interface framework and determine requirements for software signal processing. From there you get to the stage where you can see what makes sense to put inside the FPGA and what to keep in software (likely this leads to a more or less modular approach where you can implement features in software first and then move to the FPGA for better performance).In an oscilloscope everything hinges on how to present a signal to the user and what kind of operations may take place on the signal. The actual acquisition part is 1% of the work. Remember that most DSO manufacturers went through a complete rewrite of their software at some point.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 14, 2020, 11:03:38 am
content: Quote from: nctnico on January 14, 2020, 10:21:07 ama person with good enough knowledge of overall system (or several people expert on each area) can do this on drawing table at $0 cost. SW guy with his part and FPGA guy with his part. its when they start the work is where the $ (workhour) is.Quote from: nctnico on January 14, 2020, 10:21:07 amyou said that maybe because you are the HW guy. maybe its 1% the work, but 99% the cost. some hobbiests can treat their free part time as $0 developing SW, but not with buying parts for R&D. let alone tools to verify them.

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 12:07:50 pm
content: Quote from: Mechatrommer on January 14, 2020, 11:03:38 amIt is not about cost. Developing oscilloscope software is far beyond hobbyist level. I estimate it will take a few experienced software engineers 3000 to 5000 hours to get a reasonable basic oscilloscope firmware done. So basically it will take a US $500k Kickstarter campaign to get somewhere. IMHO the idea that the software development for such a huge project like oscilloscope firmware can be done for free is wrong. If you look at open source projects then you'll see most of the contributions are made by companies.

author: OwO
author_rank: Super Contributor
timestamp: January 14, 2020, 12:15:13 pm
content: The hardware, FPGA firmware, and software must all be designed together because they are tightly inter-related. If this is to be a USB based scope the device must do most of the work compressing the waveform into a bar graph for display. No, the FPGA is NOT an accelerator. The FPGA handles data too fast to be ever presented to the system bus. It hosts a pipeline that must be designed a certain way for data to not be lost and for triggers to work reliably. You can not design it from a software perspective and then "accelerate" the slow parts later.I can tackle most of the software + firmware work myself (my current roles are firstly RF and FPGA engineer, followed by software engineer). If the ADCs were available for cheap, I see no problem designing the product end-to-end with a UI that has the basic functionality. People (including on this forum) already go great lengths to develop improved software when they see attractive hardware, so it would work even better if there was officially supported open source software to begin with. The precondition of course is that the hardware is of sufficiently good bang for buck for it to be considered worth it.

author: OwO
author_rank: Super Contributor
timestamp: January 14, 2020, 12:22:14 pm
content: Quote from: nctnico on January 14, 2020, 12:07:50 pmDon't know where you pulled those numbers from. I'm sure I can get it done in 3 months, let's say 5 months conservative estimate. 5 months * 20 workdays per month * 8 hours per day = 800 hours. 800*$40 = $32000. That's not a very big investment for something that could potentially pay back tens of times, even if it's considered a high risk investment. I would not even go to crowdfunding.EDIT: that's if you pay someone to work on it (with the high overhead of officially employing someone). If it was one person doing it it would be more reasonable to account salary as $3000/month or similar, since that's closer to take-home pay at work. $3000 * 5 = $15000, which is a tiny investment.

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 12:24:54 pm
content: Quote from: OwO on January 14, 2020, 12:22:14 pmUtter nonsense. I'm sorry but you are severely under estimating the amount of work it takes. I have already worked on a USB oscilloscope (FPGA + host software) well over a decade ago and it really takes a lot more effort then you'd think at first sight.Getting a signal on a screen is not difficult. But making it tie-in with math, reference traces, digital traces, having multiple acquisition methods, rendering traces (persistance, color grading), etc, etc, is what makes things very complicated. And all traces need to be time aligned as well. The oscilloscope manufacturers usually don't get it right the first time.Quote from: OwO on January 14, 2020, 12:15:13 pmNo. Look at all the oscilloscope manufacturers. They have a universal software stack which they can tailor to specific hardware. If you are going to develop the software for a very specific target it will become obsolete very quick.QuoteThat is not what I wrote. I wrote 'develop the software + FPGA first by using FPGA development boards and then start to think about specific hardware'. In the end the hardware is the AFE, ADC, FPGA (and SoC) and some memory. You can make the hardware as cheap or expensive as you want if the software side (including FPGA firmware) is flexible enough.

author: OwO
author_rank: Super Contributor
timestamp: January 14, 2020, 12:35:23 pm
content: I took on the entirety of the NanoVNA V2 contract and did the hardware design, PCB layout, firmware, custom PC software (not based on anything existing) in 3 months from scratch. Everything was already ready in December and now the wait is on the customer to manufacture and sell itFor the oscope I already have the base designs for Zynq + DDR3, adding a ADC is not hard and I also have a big library of VHDL modules (USB interfacing etc is already worked out). Cross platform PC software with custom plotting widgets is also something I already have experience in, and lots of code can be reused. 5 months is a highly inflated estimate. 3 months is the center estimate.EDIT: getting traces aligned, already done that. A while ago for fun I wrote a web SDR interface with an oscilloscope plot, which is completely rendered in the FPGA. There was nothing especially hard about keeping several traces in sync.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 14, 2020, 12:53:32 pm
content: Quote from: nctnico on January 14, 2020, 12:07:50 pmyou definitely a HW guy

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 01:07:34 pm
content: Quote from: Mechatrommer on January 14, 2020, 12:53:32 pmNo. I have a lot of experience with software projects; I'm one of the very few who can give realistic estimations of how much effort goes into a software project and how long it will take to finish. Perhaps some people have different views on the target but when I think about a minimal oscilloscope then it should be at the functional level of the Rigol DS1000Z / Siglent SDS1000X / GW Instek GDS1000B/2000E or MicSig TO1000 series.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 14, 2020, 01:24:06 pm
content: Quote from: nctnico on January 14, 2020, 12:24:54 pmor maybe you were doing it wrong?sorry but just curious.. care to tell what DSO project you are talking about, so maybe we can have a look. multiple acq is like multiple lanes? multiple entry points to a mcu? is color grading and signal alignment are done in mcu too? how can a mcu possibly overlay 500KWfm/s realtime? cant FPGA be made to do such heavy task (color grade and alignment) and output its data to mcu using serial protocol i2c or some sort? parallel if necessary? or fashion it so it will make SW guy's job much easier?Quote from: nctnico on January 14, 2020, 12:24:54 pmshould we call them inexperienced?Quote from: nctnico on January 14, 2020, 12:24:54 pmi'm imagining any HW using the SW stack must be compliant to the stack as well. there must be communication protocol that must be adhered to, no? who made the SW stack? i'm guessing they must be really experienced. we once read about "reusability" in SW. but thats just for a brief moment in time.

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 02:40:11 pm
content: Quote from: Mechatrommer on January 14, 2020, 01:24:06 pmI never published anything (except for my current avatar picture on the left). Remember that my project is very old. I used two spartan3 FPGAs and a standard PC style DDR memory module to get a total memory bandwidth of 1GB/s. Nowadays you just get a DDR memory interface from a hard-IP block but back then I had to develop my own from scratch. In my design the FPGA is modular and allowed to pipe the acquired (10 bit) data to memory and to post-processing modules. This -for example- allows to look at the same signal using different timebase / trigger settings and/or extremely high update rates in parallel. Scrolling through memory (playback) works in a similar way. Instead of realtime data the data is streamed from memory into the post processing modules. The memory also stores the data in formatted frames (IIRC with a timestamp) which allows -for example- to mix signal data, digital input data and decoded data in the same stream. Not saying I would use this method in a new design again but it is very flexible. The high memory bandwidth makes fetching data very quick.The computer receives data frames which can then be converted into visible data. The whole idea hinges on the fact that having 1000 to 2000 screen pixels of width doesn't need to transfer a whole lot of data and thus keeps a reasonable update speed (5 times per second IIRC) over a low bandwidth link (like the 12Mbit/s USB 1.0 offers).Nowadays it would be interesting to dump the acquired data into a GPU (from a SoC) and have the GPU do most of the formatting work.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 14, 2020, 06:51:09 pm
content: I have done a lot of research in the last 2 days into how much it costs to have a ASIC manufactured and designed. I like Dave´s suggestion of doing a cost analysis of the parts but I think on any scope, salaries are going to play a much larger role than parts. I will try to price out the parts needed for a scope though.Anyone else interested in participating and dedicating some hours to this project? Please contact me with some details so we can get something official started.As Dave has said; if this is going to work it needs to offer something that is not available now. Xilinx and Intel own all the Patents on FPGAs so we would only be able to buy an FPGA from them and design another open source oscilloscope. If you want to make yet another open source oscilloscope, I think you should start a separate project because this is about designing an ASIC.Our job is to organize Companies, Sponsorships, Partner agreements to come up with the funds to do this and to develop an SDK. After the design and tape out is done and we have working samples we can organize a Kickstarter for a production run. So people who want to buy their own chip to use in a project can do that.The ONLY way this can succeed though is if we can become a serious project though and this back and forth on an open forum has done nothing but put this project to negative respectability. So again, anyone that wants to actually make this happen contact me or join the discord.PS: Manufacturer rebates is how contract discounts and free samples are handeled. Linus from LTT explained it in a video about Intel dropping prices. Basically the manufacturer gives back the cost of the parts.

author: Marco
author_rank: Super Contributor
timestamp: January 14, 2020, 06:56:12 pm
content: I don't see why you need field programmable logic, they are just a convenient way of connecting ADCs to memory when you use COTS ICs. For a digitizer ASIC just connect the ADC to the memory with fixed function logic, no FPGA needed ... just a license for a DDR3/4 macro or a couple thousand more expert man hours.

author: ogden
author_rank: Super Contributor
timestamp: January 14, 2020, 07:11:07 pm
content: Quote from: Marco on January 14, 2020, 06:56:12 pmFPGA fabric does *everything* with waveform from ADC till LCD display (persistence, triggering and so on). How else modern FPGA-based scopes achieve >=30000 waveform updates per second? Using ARM CPU? In case you think someone offered to use ASIC *and* FPGA - you are mistaken. I think this is where OP is completely missing actual complexity of scope ASIC because it must do virtually *everything* that defines scope. If you find that you did not include something important into your design which in result means Owon and Rigol will not be your customers soon - blame yourself when investors will be coming to kill you.

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 07:32:48 pm
content: Quote from: Marco on January 14, 2020, 06:56:12 pmAnd then you find out that much of the functions you like to perform needs lots of processing grunt (*) which is typically where you need more dedicated logic (and development and testing) OR where a GPU comes in very handy. The GPU on an NXP iMX8M SoC for example provides 64Gflops of processing power. This likely allows to take over lots of jobs which are typically done in an FPGA / ASIC.* This is a problem Rigol seems to be facing currently. Appearantly they left a few things out of their new ASIC which are now slowly done in software.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 14, 2020, 07:38:15 pm
content: You seem to be missing the point. You realize a scope doesn´t DISPLAY 300,000 waveforms a second. You have a 60hz LCD tops.The ADC captures the signal and sends it to a DSP which processes the signal and puts it into memory. Where is there an ARM CPU in there?The arm CPU just updates an LCD at 30FPS and renders some pretty touch screen controls. Arm SOCS can render millions of pixels a second so yes it will keep p with drawing a waveformThat is how it is done right now only that the display processing is on the FPGAhttps://www.embedded.com/wp-content/uploads/media-1113967-2011-02-15-crh-agilent-infini-2000-3000-2.jpgOr maybe you like how keysight does it better? ADC ASIC-> Memory Controller and another line form ADC ASIC -> TRIGGER ASIC which is NEXT TO an FPGA (Now another ASIC).https://keysightoscilloscopes.wordpress.com/author/colinfmattson/

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 07:42:49 pm
content: It is funny that you bring up Agilent/Keysight. It is the prime example of why you shouldn't go the ASIC route for a modern day oscilloscope unless you can't move the amount of data around using an FPGA. Keysight's Megazoom ASIC is what is holding them back for half a decade already. There isn't enough memory in the bloody thing and math functions are performed on sub-sampled data.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 14, 2020, 07:45:19 pm
content: They are using ASIC in ALL their scopes now and currently produce the worlds fasted scope at 110GHz and have a ADC ASIC with 80GSPS. light moves 14mm in that time giving you 7 linear mm on a chip to do your sampling.An ASIC is the same as an FPGA only without the switching. If their megazoom wasnt fast enough either tech wasn't fast enough or they tried to save too much money. memory interfaces like ddr4 move 2 times the data half way across a motherboard.Also you missed the difference in that picture to my plan. I want to put the DSP on the same chip you say the Megazoom is bad. Now look at that picture again. The DSP is so far away it isn´t on the picture.Literally anything you can do on an FPGA can be done on an ASIC only faster because no switching. You have high up front costs but after the chip is done. EVERYTHING becomes cheaper, faster, easier, more efficient. That is the point of an ASIC it is a F1 car compared to a Porsche. Yes an FPGA has advantages but those are exactly the problems this project would be solving; the high up front investment cost.FPGA VS ASIChttps://www.google.com/url?sa=i&url=http%3A%2F%2Fhardwarebee.com%2Ffpga-vs-asic-difference%2F&psig=AOvVaw2kEKdoYB5jPPmiDwweGmXi&ust=1579118057093000&source=images&cd=vfe&ved=0CAIQjRxqFwoTCKjBtanvg-cCFQAAAAAdAAAAABAShttps://www.google.com/search?q=difference+between+asic+and+fpga&client=firefox-b-d&sxsrf=ACYBGNQgmUKzHKCMb3Pw5XFuZh8ZiVgiqg:1579031653426&source=lnms&tbm=isch&sa=X&ved=2ahUKEwjdlaqm74PnAhWSZVAKHay0BcsQ_AUoAXoECAwQAw&biw=1920&bih=1005#imgrc=3ALqRl9BVok-jM

author: ogden
author_rank: Super Contributor
timestamp: January 14, 2020, 08:09:34 pm
content: Quote from: excitedbox on January 14, 2020, 07:38:15 pmI did say "30000 waveformupdatesper second". It means 30000 waveform trigger/processing events. The faster update speed - the more chances you will not missthat glitch. It has nothing to do with LCD update speed which OBVIOUSLY is slower.Kids... Dave measure Rigol DS2202 waveform update rate (46KHz) here:https://youtu.be/_TSr9nFN1GU?t=563

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2020, 08:19:12 pm
content: Quote from: excitedbox on January 14, 2020, 07:45:19 pmYour analogy is quite good. With a Porsche you can go everywhere and take people and/or luggage with you. An F1 car in contrast does 1 thing great but sucks at everything else. Probably 90% of the oscilloscopes sold nowadays are FPGA based and for a good reason.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 14, 2020, 09:54:26 pm
content: A DSO has different parts that are hard to integrate into a single ASIC as they need different processes: Input amplifier, ADC, Memory and control / logic. The Rigol MSO5000 has thus 2 types of custom chips.For the ASIC to FPGA comparison one has to keep in mind that FPGA tend to use state of the art processes very early, as the structure is simple and just repeats a lot of times. An ASIC for the logic part of a scope on the other side is more complicated and usually would be used over a long time. So it would be more like a well matured process (e.g. some 5 years behind in development) and thus lower performance transistors. So the advantage is not that clear and may only be for a short time. Modern FPGAs may also have optimized memory interfaces and may be ahead of an ASIC there, unless you could compete with the big guys.There is quite some competition in the scope market. So it would be hard to do a new start here.

author: ogden
author_rank: Super Contributor
timestamp: January 14, 2020, 10:07:48 pm
content: Quote from: Kleinstein on January 14, 2020, 09:54:26 pmRight. Manufacturing scope ASICs w/o any demand from market is risky business. Better drop idea of scope ASIC. If it is so easy to make scope ASIC then OP can make "just ADC" part of it, something like 1/2 cost HMCAD1520 and put Analog Devices out of business.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 14, 2020, 10:17:51 pm
content: If you read, triggering would also be on the ASIC so you wouldn´t miss anything. EVERYTHING to do with the signal is done on the ASIC. The only thing done on the CPU is display the data and interface same as every Oscilloscope. Why did I bother writing it and including pictures. If you can´t understand a basic sketch I really can´t help youWhy do the 2 of you insist on arguing about something you seem to not understand and have no interest in learning. This does EVERYTHING EXACTLY the same as an FPGA does concerning the signal. The ONLY thing changed is how you display the signal. Once the signal is captured to memory it doesn´t matter how slow you are in retrieving the data. I don´t know how many times I can explain the same thing to someone that doesn´t want to understand. The reason Oscilloscopes are made on FPGAs today is because of the cost of developing the chip. You have to invest money in developing a chip which is expensive and that is the only reason anyone uses them. It makes sense for small volume or if you don´t have the resources to finance developing a chip.Imagine if in the early days of transistors people said everything is made with vacuum tubes today how can it be better to use a transistor. It is like the People don´t want broadband internet argument.What kind of reality do you live in? Earlier you claimed digikey doesn´t have big margins on single quantities when you can see the price difference for 1 and 10,000 on many items and on something like a capacitor or usb connector you can see that buying 10k saves you 99% on some items. A resistor costs like 10 cents and 10k resistors it costs 1/10th of a cent. That is a 1000% difference. Of course they make huge margins on the parts because packaging on 1 or 100 costs the same and literally cost 10 times as much as the item.Kleinstein You are right that some parts are hard to put on the same chip due to interference but that can and has been designed around and they can be moved off chip if need be. Those things that need to be close together for the benefit of saving money can mostly go on 1 chip.The 130nm process is being used by CERN to make 20GSPS ADCs and is used on particle accelerators. an ASIC is not nearly as complex as an FPGA. An FPGA has to maintain signal quality and low noise while going all kinds of detours due to switching and cope with noise due to all those transistors. keep in mind silicon is not copper and every transistor is a jump from copper to silicon back to copper. Yes it conducts under the right conditions, but not nearly as well. Those FPGAs are not on the newest processes and in most cases an older process doesn´t make a difference like you think it does. It offers lower power consumption which you get much more of a boost from ASIC.Just go read about this stuff you don´t need me to explain it to you. If you look at the link of the comparison I posted above you would see that your argument is not the case.

author: ogden
author_rank: Super Contributor
timestamp: January 14, 2020, 10:40:21 pm
content: Quote from: excitedbox on January 14, 2020, 10:17:51 pmLOLYear ago you werejust PHP developer, now you **ck off professionals who have decade(s) of experience in electronics. You have much to learn kid.* howz your PCB printer project going? No posts about it for some time.

author: David Hess
author_rank: Super Contributor
timestamp: January 14, 2020, 11:16:21 pm
content: Quote from: Mechatrommer on January 14, 2020, 07:14:06 amLeCroy is not the only one to make something like that for converting a 50 ohm input to a high impedance input suitable for high impedance passive probes. They are also built for RF test gear like spectrum analyzers and network analyzers. Internally an oscilloscope with high impedance inputs has the buffer like you describe built in.High impedance active probes perform the same function as the high impedance buffer at the input of an oscilloscope with 1 megohm inputs. Both buffer a high input impedance to drive a low impedance which is typically 50 ohms. The difference is that the input fixture of the oscilloscope limits how low the input capacitance can be which limits bandwidth so typically 500 MHz is about the maximum while an active probe with much lower input capacitance can provide several GHz of bandwidth. I think HP/Agilent/Keysight made some oscilloscopes with extra low input capacitance which were 700 MHz or 1 GHz?There is also another trade-off with bandwidth. Higher frequency JFETs and MOSFETs which have lower input capacitance have both higher flicker noise and higher broadband noise. So achieving a low noise high impedance front end conflicts with high bandwidth. This can be seen in older specialized oscilloscopes which had like 1 or 5 MHz of bandwidth and higher input capacitance, like 47 picofarads, but usable sensitivity down to 10s or 100s of microvolts per division. Even lower noise high impedance front ends found in lower frequency instruments can have 100s of picofarads of input capacitance.Quote from: Marco on January 14, 2020, 06:56:12 pmAn FPGA is actually a pretty convenient way to interface a fast digitizer to bulk memory but there are other needed functions between the digitizer and memory like:1. Decimation to adjust the sample rate. The sampling clock is almost always fixed for performance reasons so decimation is used instead.2. Digital triggering if used.3. Acquisition modes like peak detection and high resolution.

author: ogden
author_rank: Super Contributor
timestamp: January 14, 2020, 11:34:41 pm
content: Quote from: David Hess on January 14, 2020, 11:16:21 pmYes indeed. FPGA givesflexibility. It is said million times here already - that hobbyists, "tinkerers" and open source community do not need fixed solutions like ASICs, they need something THEY can change & improve. This is what rephrasing OP's words, he seem to not understand and have no interest in learning.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 14, 2020, 11:59:07 pm
content: Quote from: excitedbox on January 14, 2020, 07:45:19 pmmost members here knows this basic fact, even i who have zero FPGA/ASIC experience. some of them cook FPGA for their life. so are you basically asking backers to pay for F1 cost? or how much fraction from it? good luck asking for Porche cost. once your "module" is completed and shipped to backers, then what? what they have to add to the module to make it a usefull scope? 10GSps ADC as we've worked out the cost and source for you earlier? or the ADC is implemented in your project too, as odgen hinted, you have a bright future to take down some of the big names if so. we have a hope and you are our hope, good luck!Quote from: ogden on January 14, 2020, 10:40:21 pmcomparing between PHP and VHDL which one is the F1 and which one is the Porche? just a side joke to release some tension.i was just as enthusiastic, built my own FG because i dont like the taste and price of existing FG/AWG. built a crap grade Arduino Logic Analyzer, and it just went poof when i got a $10 knock off salaea LA, now with a $100 Uni-T AWG bought, i can put my diy FG at rest. i asked in forum how to deal with GSps memory pipelining, and thats it, i never continue further when thinking i maybe just wasting time and money buying wrong (expensive) parts by mistake that i have no clue about. thankfully my day and part time job have struggled enough to reward me with some old high end gears, one member are also nice enough to donate me one of them as well, so the crave for enthusiasm settled down a little bit. i still have this funny idea for GHz SA and VNA manthere are more to tell about the dream but i dont feel like typing it all, i may just wasting my time here, simply short... it was the time.. i should concentrate on building my dream printer or CNC machine, because they are 5 digit price (with proper spec) and there is very slim hope that someone will come up with cheap knocked down alternative. or maybe i just keep working hard and just buy them off the shelf when i have enough moneywe always trade time with money but if i have money i will save time. yeah, sometime its chicken and egg problem. <end of useless mumbling>

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: January 14, 2020, 11:59:38 pm
content: Might be worth mentioninghttps://chips4makers.io/at this point.Quote

author: ogden
author_rank: Super Contributor
timestamp: January 15, 2020, 12:43:11 am
content: Quote from: donotdespisethesnake on January 14, 2020, 11:59:38 pmVery good resource to learn from. They started project with good intentions in 31jan 2018 or even before that. Where are they now? - Nowhere. Still nothing, no ASIC. That is about digital ASIC which could be copy-pasted from VHDL/Verilog of FPGA if properly designed from beginning.

author: excitedbox
author_rank: Regular Contributor
timestamp: January 15, 2020, 01:01:21 am
content: You can still use an FPGA instead of a SOC for post processing if that fits better. Keysight did that in the megazoom. Although I think these days there are so many SOCs out there for media centers and such from manufacturers like Media Tek that it should be possible to find something with enough processing power for cheaper.It really depends if you need hardware decimation though. You could really do that in DSP too. The point of the DSP is really to do any processing to the signal and save it to memory. Including deciding what needs to be saved. I listed hardware triggering and the trade offs between purely digital and a mix of hardware and digital will need to be discussed more when there is more solid information.I am almost done a write up of the whole project along with about 20 questions for manufacturers to get a better idea of what they would like to see. They are after all the experts.The "backers" shouldn´t have to carry a big burden. I am hoping that we can get the manufacturers, sponsors (like the EU and corporations), partners to split the costs for development. There are over 40 of them right now that have nothing over 500MHz. I am thinking the kickstarter will mainly be to make a small percentage profit on the chips in order to produce enough extras to pay for a couple wafers to sell after and sustain future production. Once the masks are made future costs will be quite low in comparison. I am would hope to raise 50-75k. If there even is a kickstarter the risk would be low with the design done and tested. And wait around 4 months.PHP is just hell15 years as PHP dev will make you hate what it has become.I just silenced Ogden I am done letting some little kid bother me.

author: ogden
author_rank: Super Contributor
timestamp: January 15, 2020, 01:14:59 am
content: Quote from: excitedbox on January 15, 2020, 01:01:21 amThank you for notice. It means I can stop wasting my time here and talk to people who actually listen.No comments, just hints for potential investors:https://www.eevblog.com/forum/projects/multi-layer-dual-sided-pcb-printer/https://www.eevblog.com/forum/projects/ai-circuit-design-experiment-programing-the-meat-of-a-component-sandwich/

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: January 15, 2020, 01:42:56 am
content: Quote from: ogden on January 15, 2020, 01:14:59 amWell that is good news; when he settles on a design he'll get the best price for the parts before 3D printing the PCB.Boy am I glad I live in the future.

author: BravoV
author_rank: Super Contributor
timestamp: January 15, 2020, 04:00:39 am
content: Just show or even brag what is the current progress, even its still really crude at early stage, instead of just ... talk.The proof of the pudding is in the eating.

author: Someone
author_rank: Super Contributor
timestamp: January 15, 2020, 05:58:14 am
content: Since the OP appears completely out of their depth and unfamiliar with the processing integrated in mid range scopes, attached is the system diagram from Rigol showing their UltraVision II platform:

author: nctnico
author_rank: Super Contributor
timestamp: January 15, 2020, 08:54:40 am
content: Quote from: Alex Eisenhut on January 15, 2020, 01:42:56 amMaybe he can 3D print the ASICs too!

author: magic
author_rank: Super Contributor
timestamp: January 15, 2020, 09:06:25 am
content: Quote from: excitedbox on January 14, 2020, 10:17:51 pmPro tip 1: you don't even understand what those people are talking to you aboutPro tip 2: and it isnotbecause they are babbling nonsensePro tip 3: watch some reviews of scopes or read the T&M subforum to first understand what people expect from the final productPro tip 4: even if you think opinions of reviewers and other Internet oracles are wrong, their opinions still affect your marketability

author: nctnico
author_rank: Super Contributor
timestamp: January 15, 2020, 10:57:51 am
content: I'm still wondering if it would make sense to start a Kickstarter for an open source oscilloscope software framework (without going into a detailed discussion on what kind of acquisition hardware should or shouldn't be used).

author: ogden
author_rank: Super Contributor
timestamp: January 15, 2020, 11:20:09 am
content: Quote from: nctnico on January 15, 2020, 10:57:51 am"Oscilloscope software framework" is way too vague goal. Definition of target hardware list/options will greatly help to get support from backers. BTWSigrokis halfway there. Would be shame to not use at least partial code of it. For instance Sigrok community implemented quite enough protocol decoders... For me open questions are: 1) Linux or lightweight RTOS 2) broad connectivity (Ethernet, USB, HDMI, parallel LCD) or not. Clear benefit of Linux: hardware & I/O support.

author: nctnico
author_rank: Super Contributor
timestamp: January 15, 2020, 11:38:40 am
content: Linux platform for sure. Ethernet, USB and parallel / LVDS TFT interface for sure. Beyond that it starts to become hardware specific.There are basically two ways to go: use a Xilinx Zync to have an all-in-one solution or use an FPGA + SoC. What I like about a SoC solution is -that if it has a GPU- it will be much easier to extend the functionality using OpenCL rather then needing FPGA development work for decoders & math. I have not looked deeply into OpenCL yet but it at least has a C-ish syntax. In theory you could implement a form of OpenCL scripting for signal post-processing at very high speeds.

author: ogden
author_rank: Super Contributor
timestamp: January 15, 2020, 12:09:14 pm
content: Quote from: nctnico on January 15, 2020, 11:38:40 amGood.QuoteI'm afraid that strict "Zynq only" platform limit will be discouraging. Would be nice to cover everything - from rPI-connected USB scopes (or even SPI ADC), cheap Spartan3+40Msps_ADC+some_ARM till hi-performance Zynq with all the bells and whistles. I think with careful system & HAL design/layering it could be achievable.

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 15, 2020, 01:14:27 pm
content: Quote from: nctnico on January 15, 2020, 10:57:51 amI think Kickstarter the company has rules against any software projects.

author: EEVblog
author_rank: Unknown
timestamp: January 15, 2020, 01:42:38 pm
content: Quote from: excitedbox on January 14, 2020, 10:17:51 pmThen you are already a step behind Keysight's almost 10 year old ASIC used in their entry level scopes, the ASIC does the screen plotting:

author: nctnico
author_rank: Super Contributor
timestamp: January 15, 2020, 02:17:56 pm
content: Quote from: unitedatoms on January 15, 2020, 01:14:27 pmThanks for noting that. There is always the option for a reference hardware platform or use a different crowd funding platform. The plan -if there is any- hasn't gotten to that point yet but it is something to keep in mind.

author: wraper
author_rank: Unknown
timestamp: January 16, 2020, 12:58:48 am
content: Quote from: unitedatoms on January 15, 2020, 01:14:27 pmReally?https://www.kickstarter.com/discover/advanced?category_id=51&sort=popularity&seed=2631893&page=1

author: unitedatoms
author_rank: Frequent Contributor
timestamp: January 16, 2020, 03:14:40 am
content: May be rules did not change, it is just my memory failing. I think the rule is something like "Kickstarter cannot be used to fund software projects not run by the developers themselves." I'd broaden this to all projects, not just software. Why the hell someone will start a campaign to just pay to someone else to do the work.

author: ogden
author_rank: Super Contributor
timestamp: January 16, 2020, 11:23:15 am
content: Quote from: blueskull on January 16, 2020, 07:13:10 amIn case of scope drawing does not mean "plotting" as you say. Think of signal pass/fail (mask) processing - it does not happen at screen refresh rate, signal is "drawn" against mask at waveform update rate. Fixed screen size of MegaZoom was not limitation of ASIC as such, it was just poor design decision. Computer GPU's are ASICs as well, yet they support multiple resolutions . "MegaZoom case" actually shows limitations of ASIC - that you can't fix your errors easily and they cost alot.

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: January 16, 2020, 01:15:22 pm
content: Quote from: unitedatoms on January 16, 2020, 03:14:40 amPossibly this ruleQuoteThere is nothing wrong with raising money for third party to do the work, quite sensible in fact, but it's not something Kickstarter generally support.Other than that, there is no restriction on software projects.

author: edigi
author_rank: Regular Contributor
timestamp: January 16, 2020, 02:08:00 pm
content: Just one minor note on this oscilloscope ASIC/SoC project. You/the people involved in this better to be darn good in this kind of design as in case of FPGA if you made a mistake you fix the HDL and recompile/reload (often the design mistake is some kind of missing requirement). In case of ASIC you need re-run the design for another half a million or so.When off-the-shelf components are used and you create only the glue logic with FPGA it's a huge help that you can trust the components to work as per their specifications saving a lot of guesswork where to look for a faulty part in a system working with very fast signals (that necessitate that people working on improving the design have very capable test equipments at their disposal).For simple products the BOM is considerable price factor, for complex products like DSO it's not the BOM that is biggest factor but the several engineering learning cycles that go in it. Do you want to start a project where each learning cycle costs half a million or so or one where at worst case just a redesign of PCB but more often just a rebuild of the glue logic in FPGA is needed?

author: OwO
author_rank: Super Contributor
timestamp: January 16, 2020, 02:13:58 pm
content: The FPGA/ASIC doesn't/shouldn't draw the actual image displayed on the screen. It "plots" traces by taking group min/max, for example min/max for samples 0-1023, 1024-2047, 2048-3071, etc. In my implementation I had the FPGA generate a series of these mipmaps, for example a /16 mipmap, /64 mipmap, /256, etc. The software does the drawing (which in my case was javascript in a browser) by requesting the lowest detailed mipmap that is equal or more detailed than the viewing zoom level. In my case the server side software does the downsampling from the selected mipmap level to the actual screen width in order to conserve network bandwidth. In a proper implementation for an oscope the mipmap generation adds very little memory bandwidth requirement because it is done directly on incoming data, NOT on data read from DRAM like an accelerator would do (that is why I dismissed the accelerator approach). However the implementation should still allow the possibility of reading data from DRAM, for example in FFT mode (assuming you have large >=1M FFT support at all which most scopes on the market don't).

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 16, 2020, 02:17:26 pm
content: Quote from: blueskull on January 16, 2020, 07:13:10 amstill a good idea or at least it should not hurt with modern FPGA. mcu not just to draw 60fps. it has to do math, USB to PC or pendrive capture, GUI, simple FFT etc. etc user interaction. look what happened to Rigol DS1000Z series. crawling slow GUI, only to stop acquisition just to get the responsiveness a bit better.

author: edigi
author_rank: Regular Contributor
timestamp: January 16, 2020, 02:35:14 pm
content: Quote from: Mechatrommer on January 16, 2020, 02:17:26 pmInteresting but not very competitive idea, when nowadays even entry level DSOs can do 1M point FFT. No FFT in MCU.While the MCU may only refresh the LCD with 60Hz only, the intensity graded waveform can contain the accumulation of several thousands of waveforms that can be done only in FPGA/ASIC.Only one such glitch (missing requirement) in the ASIC design and either the project has to live with the gap or create a redesign for huge pile of money.

author: Mechatrommer
author_rank: Super Contributor
timestamp: January 16, 2020, 02:49:52 pm
content: Quote from: edigi on January 16, 2020, 02:35:14 pmwell you know, when everybody only care about $5 cheaper DSO... (less one chip) but if FFT can be fitted in the FPGA at $0 cost, why not? (but istr dso with dedicated 1Mpts FFT IC is not $5 cheaper)

author: ogden
author_rank: Super Contributor
timestamp: January 16, 2020, 02:56:59 pm
content: Quote from: OwO on January 16, 2020, 02:13:58 pmYes, software/CPU itself may take raster image prepared by FPGA, put it on the screen @60fps together with other stuff like grid, axis and additional info. What I am telling that CPU can't handle each of "0-1023, 1024-2047, 2048-3071" traces because they can come at 60000 times per second even on lo-end scopes such as Rigol DS1xxx series. Better scopes have even faster waveform processing & update speed.

author: ogden
author_rank: Super Contributor
timestamp: February 25, 2020, 03:39:46 pm
content: Long time no see. Any progress? Where do we line-up for scope ASICs?