Measuring FULL 20V on Arduino without Voltage Dividers - Page 1
Forum section: electronics / projects

author: techoyaki
author_rank: Newbie
timestamp: August 30, 2021, 08:36:31 pm
content: Hi everyone,I recently worked on a video on how to use a circuit named Quantizer to measure up to 20V on the Arduino. Note that there are no voltage dividers used (i.e., no resolution lost on the ADC). Here is the video if you're interested in checking out the circuit and learning the concept behind the Quantizer:Sources on where I got the idea from are also provided in the description.

author: Bassman59
author_rank: Super Contributor
timestamp: August 30, 2021, 08:38:47 pm
content: Quote from: techoyaki on August 30, 2021, 08:36:31 pmWhy would a voltage divider (or a buffer amplifier with gain less than unity) "lose resolution" on the ADC?

author: techoyaki
author_rank: Newbie
timestamp: August 30, 2021, 08:45:59 pm
content: Sorry, I should've been more descriptive.The most common method to measure any signal that is above operating voltage of an Arduino (i.e., above 5V) is to use a voltage divider for the signal before going into the ADC. However, you would inherently lose resolution of the original signal assuming you wanted to measure the full-scale voltage of the original signal before going into the voltage divider. The video provides explanation on how much ADC points you would lose if you were to reduce an 18V signal by a factor of 4 to make it 4.5V.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 30, 2021, 09:25:43 pm
content: The circuit is a try to extend the resolution of the ADC by adding 2 extra higher bits. It can work, but it is quite some effort to make it only reasonable accurate and it usually still need 4 conversions. With just 4 conversions and averaging one could have got 1 extra bit without much extra effort. Joining the 4 parts accurate is tricky. It tends to loose some of the accuracy for errors in the way the parts are joined.If speed is not that critical, just 16 fold oversampling would be likely the easier way to get a crappy 12 bit ADC.

author: iMo
author_rank: Super Contributor
timestamp: August 30, 2021, 09:59:38 pm
content: Instead of 1 voltage divider there are 8 voltage dividers used..

author: techoyaki
author_rank: Newbie
timestamp: August 30, 2021, 10:09:14 pm
content: This is true! However, in my defense, the video does mention the  signal isn't 'reduced' using a voltage divider... You get the full-scale same as the input signal at the end!I'll provide another circuit implementation for the Quantizer that doesn't use any voltage dividers later on to stay true to no voltage dividers statement.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 30, 2021, 10:26:19 pm
content: 7:40 timestamp would be appreciated.Some other descriptions of your system might be:Fuzzy logicUnary ADC extensionMulti-[voltage-]windowed ADCFloating point precision ADCetc. As an array of variables, which take values of "true" and "false", but also varying levels of "truthiness" between those bounds; often as a probability, but in the case as a proportion. Perhaps not as appreciated as it should be: the classic LM3914 LED bargraph display driver, is a 10-bit unary flash ADC.- It has a voltage divider chain, setting a series of reference/threshold voltages.- It has exactly as many comparators, and the output is instantaneous (i.e., propagation delay of the comparators -- typical for its time, fractional microsecond).- The output of the comparators has not been encoded in any way, and the reference series is a linear progression.- Therefore, the output is a sorted count-the-ones (thermometer code) value. In other words, every digit has a significance of 1, no matter its position; it's a non-positional number system; unary.It also has a dot-graph mode, in which case it is a... kind of oddly positional system, but that's less helpful here.(Real flash ADCs, use an encoder to produce binary output, or whatever they happen to; weird things like gray code have been popular IIRC. They're not at all common for board-level integration purposes these days, AFAIK.) We can generalize further from the above, and consider the unary result (as whichever inputs are fully "true", in the "fuzzy" sense) as the exponent offsetting a proportional mantissa (which takes some logic to select it from whichever element is not saturated). This is kind of an abuse, because, floating point has a multiplicative exponent, whereas this system is additive only -- but I think the analogy is arguably apt, as we see the same relationship between the unary number and a conventional (positional) number.And a point for sake of discussion: it's not sacrificing ADC resolution in any way whatsoever. It'sextendingit (hence the second term at the top). In this case, 4 unary digits (uh, they're not bits... uits?... oh right,units) adds two bits, effectively extending the 10-bit ADC (this was a regular ATMEGA Arduino right? I didn't check for that detail) to 12, more or less.Downsides to the system:- Saturation is not perfect. RRIO opamps only saturate within some margin of their supplies, sometimes a fixed offset (particularly bipolar types), others proportional to load current (which is positive (output-sinking) for all amps for Vin > Vcc).- The supply isn't perfect either. Vcc is being used as a reference, so it's "dirtied" in a sense, from all the op-amps running off it. Their supply currents cause voltage drops, and change in the input signal causes partial response on other channels, and corresponding disturbance at the supply. (This probably explains, in part, the lumpy saturation waveforms seen on the scope, and the dips seen on the readout.)- Alsoooooo... you're using, not just resistors, but a shitton of resistor dividers. So, the headline claim is...a bit disingenuous....which I can  excuse for sake of memes, of course it's gonna clickbait, right?So, we could improve it by:- Add an analog switch to change the input scaleThis multiplies the input by some gain factor (<> 1 as needed, and if you want to use op-amps vs. those vile-nasty resistor dividers!), thus implementing floating point as such. Negative ranges would have to be extended with bipolar (+/-) supplies to get the voltage range (including down to / a teensy bit below zero, to avoid amp saturation issues), including an inverter to restore the positive (unsigned) ADC range. You never get any more bits in the mantissa, but you get true floating point with a binary (or other base, however you dimension the dividers) exponent.This is actually of some commercial importance: some audio systems (sound cards etc.) use this mechanism (both ADC and DAC, though probably more at DACs, I'm not sure exactly?). If some fractional bits are added to the exponent, it can be used for volume control without loss of dynamic range -- simply add/subtract a volume gain (in dB or whatever) to the exponent, and the signal is still there, in all its 16 bits or whatever of glory (at least until it disappears beneath the input/output buffer's noise floor). Or, really, if you don't mind cranking the multiplication, you can have whatever accuracy of exponent, and rescale the mantissa (by a factor [0.5 ... 2) say, for a binary exponent) at the cost of minimal rounding error.Another benefit is, with audio signals often being very peaky, a lot of information is recorded both in the mantissa and exponent; sometimes this is used directly at the ADC, with an exponential sequence of thresholds: "mu law" encoding. This was used back in the day to improve the bandwidth efficiency of digital trunk (telephone) lines; and, I suppose it's still relevant today, albeit in less direct ways (like, today we have whole-ass lossy codecs that discard tons more information, without losing vocal fidelity).Alternately (and more directly equivalent):- Add a selectable offsetTreat the input node as a summing junction. But, unlike a linear op-amp, our amp has a chunky (heavily quantized) output, and we measure the remainder. The summing node ranges 0..5V; when it's below this range, we decrement the output, or above, increment. Thus leaving some hysteresis where the input can hover inbetween thresholds, but also giving a potentially unlimited range, at least if we don't mind that the input has a current-mode characteristic or whatever. (That is, if we have an input voltage, through a series resistor, now we get a current; or vice-versa if current into a shunt resistor.)And we supply this offset from a DAC, so that there's no messy op-amp saturation, the level is precise (reference-derived) and etc.This in turn, is equivalent to a counting-type ADC, i.e.: simply hook a free-running digital counter (0...MAX) to a DAC and let it spin; when its output meets the above criteria (input within range), copy the result. More exactly, as described, it's an up-down relative count, but a counter nonetheless. Either way will work, of course you'd probably just do it this  way in software, it's easier, faster and smoother.The DAC can have a binary input, so that we aren't wasting GPIO pins, and it only requires a single ADC input, no sampling skew incurred (which is probably the other part of the dropouts in your plotting output?) (and, only requiring N samples required to slew over an input step change of N * Vref).And it only needs the one op-amp to sum the input with the DAC output.oof.wavairhorns.wavBut seriously -- it's a good demonstration of how to invent something, and which, with a little refinement, leads into perfectly practical methods such as above. Thanks for showing it off. I probably take issue with exact things in the video (which, again admittedly, I skipped through, and anyway, some of that is just stylistic choice for the video), but it's far from useless as you can see.There are still some sticky points, with matching up the ADC/DAC range -- if a given DAC bit is too wide, there will be missing bits (the (xx)FF or (xx+1)00 step is anomalously wide), or if too narrow, there will be missing bits ((xx)FE jumps straight to (xx+1)00 or whatever), or the measurement is unstable (dithering between the two codes because the range is never met on either side of the exact input). And the DAC must be extremely precise, so as to preserve the LSBs' accuracy -- i.e. the VREF steps need to be accurately "full scale" to within an LSB of the ADC's range. Which is kinda another way to say the same thing.So hey, there you go.On a related note, if you cascade the amps rather than stack them, you get a log amp instead. Which is another way to implement a (true) floating point measurement. Every amp that is railed, is another decimal place (read in unary, expressing whatever number base the stages are wired in, i.e. each stage's gain, ideally 2.000... for binary, etc.), and the first proportional one gives the mantissa. (All lower-gain stages give the respective fraction of the same mantissa, so aren't interesting.)This is used -- with somewhat less precision as it doesn't matter -- in IF (intermediate frequency) amp "strips" in some radio receivers. By taking the (arithmetic) sum of all amp outputs, the output magnitude is more-or-less log(input), and so changes in amplitude are passed with modest fidelity (i.e., it's an amplitude detector), and the mean level simply gives signal strength in dB (times a constant).Or wired another way: say we use a sample-and-hold, and instead of cascading amps, we use a single amp and loop it onto itself -- with the S&H as an analog "D flip-flop" (i.e., output takes value of input only on rising edge). And suppose we simply take a 1-bit ADC (a comparator at VREF/2) each step, because it's cheap. Finally, we subtract 0 or VREF/2 from the signal each time, corresponding to the result of the comparator. Now we have a SAR (successive approximation register) ADC, although not quite a SAR as that properly uses a full-width DAC I think; but it produces one bit per cycle all the same. This is most likely what's used in most CMOS ADCs (using charges coupled between capacitors, to save on op-amps), and in particular, can be pipelined trivially: make a matrix of such stages, sequencing the input between the first amp in each chain, all the rest being cycled to their own outputs; and latching the comparator outputs into shift registers to record the bit results as a continuous bit-stream. Add some compensation and encoding (typically packing bits into LVDS pairs or buses), and you have a typical modern high-speed ADC.(I don't know the exact details of those faster ADCs (pipelining is typically used >20Msps or something like that), and they're notoriously secretive with their tricks of course. The ATXMEGA series (and maybe MEGA0 by extension, I don't know?) does seem to have the (single amp loop, non-pipelined) version, with control features including adding additional sample or multiplication cycles -- without shifting out the result, delaying and gaining it instead. The hardware is probably not much more advanced than that of the ATMEGA (it's 3.3 instead of 5V, and 30 instead of 20MHz F_CPU), but the sample rate is ~30x higher; a substantial improvement. It's also 12 bit, and has much improved INL/DNL.)Tim

author: techoyaki
author_rank: Newbie
timestamp: August 30, 2021, 11:25:47 pm
content: Hey Tim,First off, thank you for your reply! I really appreciate it.All the other potential names you've mentioned are valid and it looks like well-thought-out (I might steal one later on if that's okay).It's true what you said regarding not really sacrificing ADC resolution if you consider the signal from the ADC input. However, what I wanted to achieve was keeping the same full-scale at input-referred (i.e., not losing resolution in terms of the step size of each ADC value). It's mentioned in 3:50 of the video but it could have been more explicit and descriptive so that was my fault.Haha, yes. You got me regarding the voltage divider... It was mainly for clickbait to generalize the idea and encapsulate the benefits that the Quantizer circuit brings.The improvements regarding small offsets is something I'm currently exploring for the Quantizer 2.0 but a 'selectable' offset sounds like an interesting idea!Thanks again Tim for your well-thought-out reply and your compliments!P.S. someone on Reddit mentioned I should do analysis on SFDR and SNR on the circuit which was a good point. The non-linearity and intermodulation components would highly be dependent on the components chosen but it'd be interesting to see if ther overall DR can actually be increased using this concept and if so, by how much.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 31, 2021, 08:36:11 am
content: The circuit is effectively adding 2 more bits on the high side (extend the range to higher voltages) of the ADC. It can be done, but it needs the full 12 bit precision for this part. Internally a piplined ADC is not made that much different: see of the voltage is on the upper or lower half, and if in the upper half subtract a well tuned voltage from the input and than send the rest to the next stage.The tricky part is to get the inital shift to be really accurate the right amount to avoid an DNL error at the transition.There is actually a way to measure a higher voltage without a divider and even without the internal ADC. Use a large resistor to charge a capacitor and measure the time it take to charge up to a level (e.g. 1/2 supply) set by the comparator. For the low range one would start at full supply (5V) and discarge. The downside is that the result is nonlinear, but in a known way. It only need a resistor (e.g. 100 K or 1 M) and a capacitor (e.g. 1 nF of reasonable quality, which means not X7R or similar) and maybe a 2nd small resistor for the piece of mind to limit the discharge current. The 1/2 voltage level would need 2 more resistors.

author: RoGeorge
author_rank: Super Contributor
timestamp: August 31, 2021, 09:02:08 am
content: This seems to be the initial paper from 2018:J. Musayev and A. Liscidini, “Quantised inverter amplifier,” Electronics Letters, vol.54, issue. 7, pp.416-418DOI: 10.1049/el.2018.0056https://ur.booksc.eu/book/68988989/f870c9More details in Musayev's PhD thesis:Quote from: Abstract at hdl.handle.net/1807/97909Thesis:https://tspace.library.utoronto.ca/bitstream/1807/97909/1/Musayev_Javid_201811_PhD_thesis.pdf

author: techoyaki
author_rank: Newbie
timestamp: August 31, 2021, 03:06:58 pm
content: Quote from: Kleinstein on August 31, 2021, 08:36:11 amThis sounds like a very interesting idea! Has anyone implemented this (specifically in IC design)? If so, could you please provide a reference? I'd love to read more about this.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 31, 2021, 03:11:31 pm
content: The RC and comparator way is a known way to implement a simple DIY ADC for µCs that don't have a build in ADC. AFAIK there was a application note from Atmel on this, though the idea / principle is older. The analog joystick inputs of the C64 work in a similar manner.

author: mawyatt
author_rank: Super Contributor
timestamp: August 31, 2021, 04:42:58 pm
content: Somewhat along these lines of ADC type discussions, over a decade ago development of a completely new type ADC was underway. This new ADC utilized amplitude and time quantization simultaneously, and had the unique property of not requiring an ADC anti-aliasing filter preceeding the signal digitation by the ADC. Anti-aliasing was preformed post ADC conversion in the digital domain!!This technique was called Non-Uniform Sampling ADC, and spearheading by Dr Mike Chen at USC.Here's and early rendition of this NUSADC chip development.Best,

author: Renate
author_rank: Super Contributor
timestamp: August 31, 2021, 06:20:52 pm
content: I dunno, I'm boring, I reach for the same things.A TI INA226 high side current monitor with I²C gives you 15 bits voltage (15 bit + sign current) off the bat.It goes to 36 V. There are other models that go higher.126 dB CMRR is good enough for me.https://www.ti.com/product/INA226

author: techoyaki
author_rank: Newbie
timestamp: September 01, 2021, 07:10:53 am
content: Quote from: mawyatt on August 31, 2021, 04:42:58 pmThat was an interesting read! Just as a side note, the concept of performing anti-aliasing in digital domain kind of reminded me of the concept of IQ signal summation in RF signals to remove the image component which is also usually done in digital domain.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: September 01, 2021, 04:12:58 pm
content: How would a voltage divider loose any resolution?The AVR still has an 10 bit ADC, regardless whether you use it to measure 1V or 20V.Its just some silly video based on misnomers that it's not worth watching.If you want more resolution, just get an ADC with more resolution or an uC with a better built in ADC. Simple as that.Funniest datasheet I once read was about a 20bit ADC with on-chip 5051 compatible processor.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 01, 2021, 06:25:13 pm
content: Quote from: Doctorandus_P on September 01, 2021, 04:12:58 pmYou mean 8051?Be thankful they gave you the courtesy to say so; many high-bit serial ADCs have one internally and they don't tell you at all. Some of which, their internal state cannot be reset any other way than cycling power.Tim

author: techoyaki
author_rank: Newbie
timestamp: September 02, 2021, 03:33:52 pm
content: Quote from: Doctorandus_P on September 01, 2021, 04:12:58 pmI believe there's two ways of looking at it. First is what you've mentioned where you only look at the input node just before the ADC (i.e., full-scale value of 5V for the Arduino) which is how you would normally look at the resolution. Second way is to keep the same full-scale as the very first input which would be 20V but with the same voltage resolution steps as you would have with the 5V which is approximately 5mV step size. I do specifically mention this in 3:50 but should have been explained more clearer/explicit. The main point was that if you use a voltage divider to reduce the final signal going into the ADC from 20V to 5V, you essentially lose information (and also increase the quantization noise) after converting the signal to digital and the only way to keep the same resolution steps would be to somehow, as you've pointed it out, use an ADC better than 10-bit.

author: mawyatt
author_rank: Super Contributor
timestamp: September 02, 2021, 04:46:53 pm
content: An easy way to deal with situations like this is to use Input Referred Resolution, where the effective resolution at the input source is utilized. So in a case with a 10bit ADC with 5V full-scale, the ADC resolution is ~5mv/bit, with a 4X input attenuator for 20V full scale input, this becomes 4*5mv/bit or 20mv/bit at the input source.Best,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 02, 2021, 06:34:47 pm
content: Still another way to look at it, the preferred way IMHO: the ADC is just a ratio sensor. You're not sensing 5mV/LSB at the input, you're sensing 1/1024ths of Vin/VREF.As a ratio, it makes no difference what the input scale is, in absolute units; it's always and necessarily relative. You can do calculations on it as any other ratio, and simply add calibration offset and gain (and unit) at the very end (e.g. when printing to the screen). This often greatly simplifies internal logic: you don't need to mind what the scale of any variable is, it's simply some numerical range corresponding to that ratio. Often that ratio can be packed conveniently within a 16-bit 2's-complement variable (which serves nicely as a ratio itself: or more technically, a finite ring modulo 2^N), so that you have no unused values, exactly every value the variable can possibly take is fully represented in its range. No edge cases!(The downside is, you'll typically be overflowing that range with calculations -- it's rather hard to offset or scale-up a modular variable; you have to implement saturating arithmetic, or catch errors. Or you'll be casting to a larger datatype to get extended fractional bits, at some expense to performance, depending on the platform. But these are normal numerical concerns, DSP stuff, not specific to ADC interfacing.)(Oh, and to make that clear: a ratiometric ADC is simply reading its result as a fixed-point fraction. So fixed point arithmetic is perfectly natural to follow it up.)Tim