Learner project? - Page 1
Forum section: electronics / general

author: paulca
author_rank: Super Contributor
timestamp: June 06, 2025, 02:51:37 pm
content: As soon as tutorials set you on your way to "mount stupid", I start challenging myself for "real world applications".I can think of a dozen mini-projects to learn this or that in FPGA land, but I probably would reject 11 out of the the dozen for being "Just use an MCU!"That path just tells me I don't need an FPGA.However I have an idea. I am already abusing verilog as a digital circuit simulator, without synthesis, the boring single component address logic for my Z80 computer was born there.It got me to thinking though. There is a lot of modernisation that can happen to a Z80 CPU if you plonk an FPGA in front of it and call it "Chipset and MMU". Things like multi-processing w/ virtual memory. Just extend "bank switching" to happen via a TLB (table lookup buffer, or a but LUT). The "OS" pre-loads those tables into the FPGA. The FPGA then manipulates and maps virtual addresses to real addresses. As long as you map enough of your "kernel" address space into each processes address space to "get yourself back out".Does this sound like a project for a beginner to slow chip away at in verilog simulation land? Then later try and physical-ize it on a real FGPA?In parallel the 74HC logic gates will used. Later I could replace them and everything else that clutters the bus, like buffers / transceivers by that stage into one little LatticeICE package.

author: asmi
author_rank: Super Contributor
timestamp: June 06, 2025, 03:29:14 pm
content: The question is - how many hobbyists/FPGA beginners have enough knowledge of inner workings of CPUs/MMU to even contemplate such project? And using Z80 core will inevitably be way too limited for any more-or-less modern application due to small address space - just fitting even old-school dumb display buffer at useable resolution (like 720p or 1080p) is going to be a serious challenge. Which is why I would use 32 bit core at the very minimum for such purpose, and since you use FPGA and not physical CPU silicon, you are free to use whatever core you want.

author: paulca
author_rank: Super Contributor
timestamp: June 06, 2025, 04:08:55 pm
content: Quote from: asmi on June 06, 2025, 03:29:14 pmThe thing about 32bit cores or even better 64bit address bus... they don't come in easy to understand form like a Z80. It gets right out of hobby scope fast.Which relates to your "how many people understand the inner workings" point. I know enough to get my self into trouble and hopefully learn my way back out of it again.Just another idea...Spectrum Analyser display with large RGB LED matrix as an FPGA project?The challenge there would be finding an open source "FFT" or fake FFT component as I am not going down that rabbit hole. The digital audio feed and LED waveform sequencing I think I could manage with a bit of time.Data flow... pipelines... FIFOs. But how does one do something like FFT? Do you just convert the equation into a state machine and clock each "element" through it? Out pops the result in a reg? Duplicate it a dozen times, so a bunch in parallel?

author: asmi
author_rank: Super Contributor
timestamp: June 06, 2025, 04:46:05 pm
content: Quote from: paulca on June 06, 2025, 04:08:55 pmI disagree. For example, basic RV32I command set is only like 40 something commands, and I will argue that this command set is much more straightforward and is easier to understand than Z80 command set (which is full of weird submodes and half-documented "bug-o-features"). Anyone can memorize all these commands in a matter of days of actual use, but even that can be avoided if you use C instead and a C compiler which can generate RV32I code.Or you can roll out your very own command set if you so desire - I wouldn't recommend that approach as it's got too many pitfalls, but it is absolutely possible and within reach if desire is there.Quote from: paulca on June 06, 2025, 04:08:55 pmBut before you roll your own, you learn this stuff by looking at how existing architectures approach this task first, right?Quote from: paulca on June 06, 2025, 04:08:55 pmFFT is a pretty straightforward algorithm, and there are plenty of existing implementations - both open source and vendor-provided. You do need to understand pipelining to implement it - or at least to follow existing implementations, but that's kind of the point - this kind of project is basically "FPGA designs 102", as opposed to typical simple examples you find online which can be collectively summed up as "FPGA designs 101".

author: nctnico
author_rank: Super Contributor
timestamp: June 06, 2025, 06:14:21 pm
content: I agree with Asmi. Go for something like Risc-V or the Lattice LM32 as a CPU core. And keep in mind that most, if not all, of the stuff from Opencores is useless junk.

author: BrianHG
author_rank: Super Contributor
timestamp: June 07, 2025, 01:24:12 am
content: We haven't a good scope of what a 'learner' project would count as viable lesson for Paulca?If you want to flex you Verilog abilities, maybe design your own 8bit mcu.See how fast and useful you can make it.maybe look at the really old entry level PIC MCU series and see if you can code your own equivalent which will successfully run code from their compiler.I've done multiple simple codes here and my github, like floating point clock dividers, an enhanced stereo version of a YM2149 6 channel programmable sound chip with a 6 channel audio mixer that has bass and treble controls, an I2C initializer for those pesky I2C devices which need to be set on powerup, a real-time RS232 <-> PC memory viewer / debugger and a few others.Most of these were well documented and have full Modelsim setups where you may poke and prod at the logic and stimulus anyway you like.

author: asmi
author_rank: Super Contributor
timestamp: June 07, 2025, 02:17:10 am
content: Quote from: BrianHG on June 07, 2025, 01:24:12 amI wouldn't recommend that unless one is into retro stuff, because these things are full of clever engineering tricks and compromises which were neccessary back in the day, but are completely obsolete now as silicon tech has advanced to the point that straightforward implementations are often the best because the simpler they are, the less chance of them having some bugs. There is a reason nobody uses wave generators for music in the last 2 decades (at least). Now I would rather recommend one to study I2S bus and create a module which outputs some kind of waveform to an external DAC - which is how sound works nowadays.

author: paulca
author_rank: Super Contributor
timestamp: June 07, 2025, 08:44:14 am
content: Quote from: BrianHG on June 07, 2025, 01:24:12 am40 years a software person. Sums it up really.So far in FPGA land I have got someone elses soft-core Z80 running in testbench, I added my own RAM and ROM to it. They are pretty simple. I just implemented them to work like the datahseet said they did.... sans the timing requirements of course.... except where it need to pay attention - causality.I took the LED Chaser example and made it ping pong back and forth and I took the PWM example and made it too go up and down.One avenue is to carry on like I did with the RAM and make simple IC components and just carry on using Verilog as a "digital circuit simulator".On another path I created myself a "basic_counter" module with parameterized modula and automatic bitwidth.I did start into a button debouncer, but I wrote it into scrap land by breaking the rules. I didn't decide "What a button debounce was" before I started, so I ran around in circles with competing requirements and ruined it. (Notable later when I did a button debounce in an MCU I knew exactly how I wanted it debounced (single pulse, no return 100ms) so it took 2 minutes.

author: paulca
author_rank: Super Contributor
timestamp: June 07, 2025, 09:02:53 am
content: Quote from: asmi on June 06, 2025, 04:46:05 pmWhat I have is the academic textbook models. I no longer have the book (Jean Bacon's - Distributed systems, operating system and databases). It form a full year of uni for me. We weren't asked to read it all, but I did.The relevant chapters where looking at the hardware and up to answer the question of the "Two ATM machines" classic race condition.... more formally described as "non-interoperatable-sequence" occurring and corrupting state.That started with the CPU architecture and it's MMU focusing on the "Test and write" instruction, how it works and what happens in architectures that don't have such an atomic instruction... how does it interact with the cache? etc.On that ride we explored the TLBs and how the MMU works to enforce memory protection. On that, I don't think the Z80 has got the right stuff for proper "secure" virtual memory and full protected mode, I believe in modern architectures the CPU is aware enough of the virtual memory model to make handling interrupt in kernel memory space easier etc. Without necessarily givng the running "process" access to that memory.My idea was to just scrap the surface of it and take the bits I need, leave the bits I don't.I don't need to care about all the rigorous transactionality and I don't really care for the security either. So I was just going to give each process it's own 16K block of RAM. A map something like:16K - OS Vectors16K - Common Rom Lib16K - Shared RAM16K - Dynamic virtual addressed RAM - per processThen give it access to maybe 256kbyte of RAM. I don't even need to write malloc routines, just "fork(), probably join()" and a scheduler interrupt.EDIT:The practicalist in me would like to say something...Given the scope of the Z80 project being - an Arduino like MCU the size of biscuit tin - It would probably be far more appropriate if you virtually paged the Flash ROM to run multiple "sketches" like an RTOS, rather than piss about with RAM block multi-tasking.

author: zapta
author_rank: Super Contributor
timestamp: June 07, 2025, 07:32:44 pm
content: Here is an FPGA project idea for you, an acoustic camera. Having an array of I2S SMD microphones on a grid, all going to the FPGA, and the FPGA outputs a two dimensional matrix with the sound level in each direction. The I2S microphones are small and cheap, a few bucks each, and the FGPA needs to read their I2S stream, forms the beams (involved delays and sums) and compute the sound level of each beam.https://hackaday.io/project/192750-sesenta-open-source-tileable-acoustic-camerahttps://hackaday.com/2024/10/10/building-a-sound-camera-for-under-400/

author: zapta
author_rank: Super Contributor
timestamp: June 08, 2025, 02:48:37 am
content: Here is another interesting learner project, an FPGA soft core. That is, a Verilog module reads its configuration from RAM at runtime and implements arbitrary combinatorial and sequential logic.

author: rstofer
author_rank: Super Contributor
timestamp: June 10, 2025, 02:17:58 pm
content: Quote from: paulca on June 07, 2025, 08:44:14 amGiven the Opencores T80 core (Z80), grab the prom data from the MAME project and voila' PacMan! How cool is that?It is KNOWN to sork...Or, tie a Compact Flash to the bus as a disk drive (actually several logical drives) and implement CP/M. Then find the Microsoft Fortran compiler or the Digital Research PL/I compiler. Also KNOWN to work.I used a Digilent Spartan 3 Starter Boards for both of these projects a long time back.