Power supply topology - will it work? (Control theory, stability) - Page 1
Forum section: electronics / projects

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2016, 08:05:46 pm
content: Hello!Just an interesting topology useful for high voltage power supplies, requiring only asymmetrical aux supply and opamp capable of working with (near) zero voltages (like 324 or 358 or any RRIO one). The question however is - will this one work?A little description: Referencing the aux supply to the positive output terminal has a big advantage of driving the mosfet gate, no high voltage amplifying stages are needed.As the feedback voltage is negative related to the aux supply reference point an inverting amplifier is used to both scale the voltage down and change polarity to positive.Then a regulator is used to control the mosfet, based on the positive feedback voltage, comparing with positive reference voltage, related to aux supply gnd.R1 is used as a current shunt.The regulator is the most difficult part: How should I determine, what type of regulator (R and C configuration) and compensating circuits shall I use so I can make the thing stable, even with added capacitive loads on the output?Note: The integrating regulator might not be what the circuit really requires!Schematic is attached.Thank you for helping meYan

author: Kleinstein
author_rank: Super Contributor
timestamp: November 17, 2016, 08:26:40 pm
content: In principle this type of regulator works. Many of the HP lab supplies use this type. The nice thing is that you can use essentially the same regulator part for different voltage levels - from low voltage like 3 V up to 100s of volts with suitable power transistor.The regulator might need a resistor in series with the integrating cap and an output cap with sufficient ESR or series resistor. One can even simplify the circuit by using the non inverting input for the feedback (and add a positive reference current).Today one would use a simulation (e.g. LTspice) to check.

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2016, 08:55:08 pm
content: Yes, I have also found later the non-inverting input can be used, by supplying a positive reference current. One opamp less, however this has the advantage of an high impedance reference input. (One would have to use an extra follower to supply the reference current, if high impedance control voltage input is needed).What do you mean by "sufficient ESR"? User of the PSU can always connect a big low ESR cap directly on the output terminals.How would you estimate the compensation values in a specific circuit design? (or to make a simulation? First estimate will still be needed)Do you know any schematic I could reference to?Thanks,Yan

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 17, 2016, 09:19:28 pm
content: Note that, since MOSFET source, and error amp, are referenced to +out, this is a negative voltage LDO (open drain output). Which means, a better way to draw it would be... *waves hands around erratically*. Well, you know.You don't need ESR for stability of this type of regulator, but you do need a loop with enough means of control to realize that -- usually using the transistor as a controlled current source (which it is anyway, regardless of how you treat it -- the drain output in the linear range (FET current saturation) is CCS), with feedback to control that current precisely (rather than the quadratic to exponential dependancy on Vgs that a naked transistor has), and feedback around /that/ to set the actual output voltage.ESR helps because of adding a zero in the loop response; ideally, ESR * C is selected so that the zero falls near fT (i.e., loop gain ~= 1), so as to improve phase margin.Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: November 17, 2016, 09:35:59 pm
content: For this type of regulator the ESR of the output cap helps to get stability. Often something like an 0.1 - 1 Ohms ESR can work to provide enough damping in the 100 kHz range. Even with an external low ESR cap this damping will persist. With enough low ESR capacitance the ESR might not be needed anymore. However a capacitance without ESR can worst case loose its effect with an inductive load. The ESR has a similar function for stability as the relatively low output impedance of the classical emitter follower stage.For the fist estimate of the tuning loop one can start very slow and than adjust in the simulations.A good point to look at is the output impedance in the 10-100 kHz range. Something like 1-10 Ohms is realistic unless you have a very slow of fast output stage.In the simulations looking at the output impedance (use AC source as a load and look at output voltage) is a good way to check for stability with different load conditions. If the output impedance has less than 90 degree phase shift everything is stable, no matter what (passive, up to +- 90 deg phase shift) load is used. One still needs to check transient response for unpleasant surprise of nonlinear effects from saturation or similar. Linear stability is required but not sufficient for good regulation.

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2016, 10:05:24 pm
content: OK, thank you both for some hints. But may we try with some specific design situation, so I can better understand the processes involved?Let's say I want to build a regulated DC supply, 0 to 400V using the topology in the first post (here attached again). The max output current will be 150mA.The ref voltage has been chosen to be 5V full scale, so the inverting opamp shall have a transfer of -1/80. So set R5=800k and R4=10k.The current shunt has been selected R1=22ohm (3.3V drop per 150mA) and gate resistance of whatever some hundred ohms, say 270.I want the output capacitance of the PSU to be as small as possible, yet it has to be stable with all kinds of additional loads. How should I estimate the required output cap Cout?How will I estimate then the loop bandwidth and compensation values? (R3, Cfb or other ones if needed).What shall be the first step in this situation?Thanks,Yan

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: November 17, 2016, 11:08:52 pm
content: Yansi,You can start the control loop modelling with the attached LTspice model.Here is the modelThis the resultsI haven't made any attempt to optimize the loop.Note:I have essentially designed this as a negative output unit. This is because the positive terminal is the small signal ground.Regards,Jay_Diddy_B

author: Yansi
author_rank: Super Contributor
timestamp: November 18, 2016, 11:50:55 am
content: Thank you for the sim! I'd now better install LTSpice and learn the damned thing(Sorry, my best sim yet is the soldering iron, heap of components and a bunch of meters)How did you estimated the compensation values? (C1, R3) and how can one figure out C3 R7 were also needed?What are those arrows marking in the bodeplot? Is that the "crossover frequency" and how did you use that to derive the component values?Thank you,Yan

author: Kleinstein
author_rank: Super Contributor
timestamp: November 18, 2016, 01:10:42 pm
content: The part with C3, R7 is known from lab supply circuits. They usually need it to get stable with large capacitive loads, but it also changes the rest of the adjustment. So better include them from the beginning. The rule of thumb I know is having R7 about 1/10 of R5. The exact value is usually not that critical.For R3 and C1 values could be just ballpark figures, e.g. from an other supply circuit or a little higher. If one really wants one could calculate it up front to get the desired cross over frequency ( 0 dB Gain for the loop gain, marked with arrow). But with a simulation if could be just a crude guess and one correction step.The circuit likely will need protection diodes to GND where R4,R5 and C3 come together.With a MOSFET power stage one might have to watch the performance at low currents, as the MOSFET is rather nonlinear and much slower at low currents. So some minimum load (or even 2 quadrant operation) might be a good idea if one cares about minimal output capacitance.

author: Yansi
author_rank: Super Contributor
timestamp: November 18, 2016, 01:19:35 pm
content: I think guessing / trying component values won't work here at all. You have at least six components you might change: double RC compensation and the output C+ESR. The probability of guessing these correct (enough) by trial and error is almost zero.I have already built the circuit (few days ago), but had serious troubles making it to behave nice. It does not oscillate, but that is the only thing it does right. The load change step responses were ugly as hell. My friend even had told me, that the circuit topology is incorrect and will be always unstable - hence why I have asked in the first post about it, because I was almost sure, this has to work.I have tested only so far the step responses of "no load at all" versus "some load". Circa 250V input, about 30-50V output, up to 30mA load. (Cannot test higher voltages or currents, as I don't have suitable equipment and mosfet in the circuit: STP6N80K5 being used currently)The step response at the time of connecting some load is I think good enough, however disconnecting the load (to no load) produces ugly ringing. The bigger the output capacitance, the longer it rings with a lower frequency. And it is not any kind of high frequency oscillation, it rings at kilohertz to Hz range for a 100ms or more sometimes.But before posting further, I need to make a better measurements of the step responses and use a better measurement technique.Maybe I want something that is simply not possible with what components/circuit I have.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 18, 2016, 04:33:03 pm
content: There are not that many degrees of freedom in adjusting the compensation. The R5/R7 ration is relatively fixed. So there are essentially only the 3 caps c1,c2,c3 and the series resistance. The caps also are responsible for different frequency ranges: the highest frequencies are mainly influenced by C2,R6 and only a little by C1. The intermediate frequency range is influenced mainly be C1 (or more accurately by C1*R3/R1/R4*R5) and a possible resistor in series to C1. C3 is usually important for the lower frequency range - though the 100 pF value shown is rather small, but R5 is also large.So once you have a reasonable start, one can optimize the three caps relatively independent So it's not one system with 6 interacting degrees of freedom - which would really be hard, but more like 3 systems with 1 or 2 parameters with relatively little interaction. Optimization is still not easy and will take some time and simulation runs. One may not find the absolute best - but defining what is best is already difficult. It will be a compromise on performance at different loads and tolerance to parasitic effects and not so perfect models. It does not make sense to optimize to far in the simulation, as really life will be a little different - so it also has to work with slightly values.The more annoying part is that the "best" parameters also depend on the DC current. So one has to find a solution that works at high and low currents. Here it can really help to have the output stage in a way that it depends less on the current: this could be an extra local loop or maybe using feedback from the source resistor instead of the gate driving part. If performance of low currents is important, I would consider using a output stage that can work 2 quadrants.The next possibly tricky part could be nonlinear effects do to a kind of windup of the regulation loop - so sometimes even if everything is fine for small signal tests, the a regulator circuit can still oscillate after large steps with certain loads. However this also applies to other topology.It can be still a little tricky when doing it with hardware, unless you have good instrumentation (response analyzer). However in the simulation no limitations from instrumentation: for example one can still get the loop gain for an unstable system. So one can directly read loop gain or output impedance or step response.Having a regulator of emitter follower / source follower type can be a little easier to tune - at least if you don't need a lab supply that includes current regulation too.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: November 18, 2016, 06:04:52 pm
content: Hi,Let me see if I can explain how to do analyze this.Modified ModelI have rearranged the model, without changing the circuit or the component values. I have added labels OP_U1 and OP_U2. I have divided the circuit into three blocks, the power stage, error amplifier and the divider stage. The loop gain is the product of the gain of all three stages.ResultsThe results show that the error amplifier has a single pole slope, 20 dB/decade and 90 degrees of phase shift. The result deviates from this at high frequency because of limitations in the op-amp.The divider stage has a pole zero pair. This is often used in power supplies to generate phase advance or phase boost. Again the result is textbook, until the op-amp characteristics creep in at the higher frequencies.The output stage is the most interesting. The other blocks, nothing changes with load current, output capacitance etc. but in the power stage everything matters. The Power stage is a single pole from the output capacitance and the transconductance of the MOSFET. There is also a zero formed by Cout and the ESR of the output capacitor.Changing CoutI have introduced the .step directive to change the value of the output capacitor through a list of values.Results from Changing Cout.I hope this give a little insight in to how to model this circuit.Regards,Jay_Diddy_B

author: Yansi
author_rank: Super Contributor
timestamp: November 18, 2016, 09:39:11 pm
content: Thank you for detailed explanation how to simulate the loop stability. Will install the spice soon and try to bite it. Currently the soledering iron is still the easiest for me.I have finished building the load step test jig, so I can finally measure the response.The setup was as follows: Schematic with values attached. Input is around 260V, output set to 70V. Load switched on-off is 1k65 resistor (so 42mA or nothing).Step responses shown below. Tested first with 1uF 1ohm only, then added 10uF ellytic cap directly on the output (no "additional ESR").Could you please evaluate the results, somehow? I am not sure how that should look like when correct, but I am concerned the ringing when load is switched OFF is really not good. I have tried fiddling with C3 and C1, increasing their values slightly (up to 0,5nF or so), but not much effect on the step responses. Increasing C3 too much (0,6n) makes it oscillate.Note the very long ringing time (and period) at load off, especially with the additional 10uF cap.I will also try stepping the load between 20 and 40mA, what will be the difference.Thanks,YanEDIT: Schematic added. Note V2=875mV.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: November 18, 2016, 10:23:06 pm
content: Yansi and the group,I ran the transient test with this model, 10uF capacitor:Here are the results:Fairly similar to what you have on the hardware.Modified ModelI have modified the model to improve the response:Here are results from the modified model:Try modifying the hardware and see if you get a similar result.You may need to add load resistor, around 1mA to set a minimum output current.Regards,Jay_Diddy_B

author: Kleinstein
author_rank: Super Contributor
timestamp: November 18, 2016, 10:34:59 pm
content: Doing the step response all the way to zero current is difficult for the regulator. Some of the ringing when switching the load off can be from nonlinear effects (having the MOSFET turned off for some time). This might need additional measures. Also the MOSFET gets quite slow with only the 800 K from the divider as a load.The LM324 is a quite slow OP and thus one can not expect a very fast response. To avoid the dead band from the output stages one could try an additional 1-2 K to GND at the OPs, especially OP1. A faster OP (like TLC272) could help. The response is relatively slow, but much of this can be attributed to the slow OPs. One could ease a little on the OPs by reducing R1 to maybe 5 Ohms.Some ringing like with the 10 µF capacitive load is normal and cannot be avoided. However the slow ringing indicates a still slow regulator and normally such heavy ringing should only happen with much larger caps (like 1000 µF).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 18, 2016, 11:00:32 pm
content: Note that ringing is a symptom of control loop stability, phase margin and all that.The total (peak) magnitude of over/undershoot is determined by the capacitor, at the very least.Simply, the control cannot respond instantly, so until it does, the output has the relationship:I = C * dV/dtFor a delay of, say, 1us, and a specified stability of 1% or better (i.e., +/-1V transient out of a 100V supply), and say 100mA load step, the capacitor must be V = I * dt / dV = (0.1A) * (1us) / (1V) = 0.1uF. Or more for longer time scales, or tighter regulation, and so on.For the ESR to matter, it has to have a comparable voltage drop, i.e., on the order of (1V) / (0.1A) = 10 ohms.There can exist no such arbitrary rule as "1 to 10 ohms ESR". A very low current, very high voltage regulator will see even 100 ohms as a short circuit. Whereas a very low voltage, high current regulator will need as manymilliohmsto have acceptable output impedance. Only the time constant ESR * C matters, and it will be proportional to the loop time constant.This way, you can figure out the ballpark C and ESR that is desirable for any power supply.Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 18, 2016, 11:06:59 pm
content: Note that the overshoot is excessive in the above simulation, because the op-amp has to slew a huge voltage range (from cutoff to normal operating voltage), and is limited by its own speed, and the compensation network across it (where the capacitor is dominant -- note that the resistors are both 10k, so an input step into that amplifier will only make an equal amplitude output step, with slew rate limiting added, and rising slowly over time as the capacitor charges).If a quiescent load is introduced (say, changing the ISTEP from 0 to 42mA, to 10 to 52mA), then it will behave much nicer.It will behave nicer still, in the current range where the 22 ohm source resistor is dominant (i.e., gm > 1/(22 ohm)). This is where the MOSFET becomes a nearly linear transconductance amplifier (voltage in, current out). In this region, the control loop response no longer varies with average current level.Tim

author: Yansi
author_rank: Super Contributor
timestamp: November 18, 2016, 11:21:27 pm
content: Thank you for responses guys!I have made another set of step measurements. This time at 40V output (I had to lower the output, otherwise the mosfet would get some hot soup!) as my set of resistors for high voltage loads is not variable enough. When stepping from 27mA to 51mA, the responses are much nicer. With the 10uF added load, the ringing is quite damped now. Without the 10uF load, the step from 27 to 51mA yields only about 1.2V overshoot and undershoot. With the 10uF cap connected, both under half a volt. I should also test with larger capacitive load like 100+ uF, but am afraid the mosfet might get killed, as no current limiting is being implemented now. (But sure will be soon)Please note the 10uF cap should be external load to this PSU, the internal cap should be only the 1uF foil plus the 1ohm ESR. By the way, isn't this similar function to the "zobel network" used in many audio amps (to present a load at higher freq)?Yes, the LM324 is slow. But was the first opamp in reach with "input commonmode include gnd" and also being a quad OPAmp. The other two will be later used one for current limiting and one for pre-regulator control. (a stepdown converter will be used - prototype is mostly finished and seems working and happy).TLC272 you say? I have a feeling I should have few TS274 opamps somewhere. Should be even faster and the quad I need. But let me tell ya, I made a mistake soldering the 324 directly to the veroboard. Doh! Thanks for the tip, I'll try to find them.The 22ohm current shunt has been chosen due to two things: I wanted larger sense voltage, so that the opamp's offset voltage will have less influence on stability. 22ohms will result about 3V at 150mA. (however the target is 300mA using two IPW90R1K0C3 in parallel - but that might be in a future). The second reason I have chosen higher source resistance was me thinking I will linearize the mosfet output characteristic - but I might be wrong ??I will try to desolder the 324 and put there aTS274socket and TS274 in it and try again.T3sl4co1l: Interesting to know, I had thought there would be a more complicated relationship. Will try to take that into account. What would you suggest to be the spec for a decent amateur built 400V 300mA general purpose PSU?

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2016, 12:23:28 am
content: TS274 has been successfully found and socketed on board. It works. Without touching the compensation networks, the overshoot/undershoot are slightly better, say by a tenth of a volt. (1V instead of 1,1V). It also seems there might be less damping when the 10uF load is used.After having modified the compensation according to your latest sim, the results are way better. 480mV no cap, 280mV with 10uF load.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: November 19, 2016, 02:21:41 am
content: Hi,I am not a big fan of this topology from a control theory point of view.You start with a pole in the error amplifier, this is because there is a capacitor in the feedback loop to ensure that there is no d.c. error.The power stage is a transconductance stage with a load capacitor. This is another pole.So we have a double at the origin (or low frequencies) The combined double pole has 180 degrees of phase shift.The power stage pole moves with the addition of output capacitance as we have seen.To stabilize the loop I added a pole zero pair in the divider get phase advance at the frequency were the gain = 0dB. I also added a zero, by placing a resistor in the feedback path of the error amplifier to remove the error amplifier pole.There are other contribution to consider.The zero formed by the ESR in the output capacitor is included, in the model, to show its effect. With the values shown it is too high frequency to be useful, it is higher frequency than the loop bandwidth.With the values that I have chosen there is little benefit to using faster op-amps. The gain of the op-amp sections is determined by the passive components around the op-amps, as it should be in a good design.Regards,Jay_Diddy_B

author: Kleinstein
author_rank: Super Contributor
timestamp: November 19, 2016, 08:46:55 am
content: It is a good idea to do the testing with a lower voltage, alone for safety reasons. With a sufficiently fast OP, the higher source resistor is not such a big problem unless it gets too hot.The LM324 might be still acceptable for it's bandwidth, but the slew rate can be rather poor and the output stage shows quite some cross over distortion when going from current sinking to current sourcing.I would at least add minimal current limiting with a transistor driven by the voltage at the source resistor and turning down the gate.There is not that much difference in the control loop when you go to the alternative emitter follower topology. In a unified picture one can also consider other output stages as controlled current sources, just with an addition impedance to ground, to take into account the usually lower output impedance of an emitter follower. However at low currents even the emitter follower will not be that low in impedance to be useful. So one generally still needs the output capacitor of similar size. Some of the capacitance might be moved to the base side of the transistor and thus will not be directly at the output - but the effect is essentially the same in the good and bad.It's only on transients of increasing load, that the than low output impedance can really help to limit drops in output voltage, so that an slower control loop can be acceptable.On the downside one also has to make sure the output impedance of the power stage is well behaved and does not tend to oscillate by itself.Things get better with a push pull output stage, that has a low output impedance even at low currents.@blueskull:I think it should be *k4 not +k4 in the transfer function. So no such easy way to prove stability.The tricky part is to make it stable even with variable load.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: November 19, 2016, 10:18:49 am
content: Quote from: blueskull on November 19, 2016, 08:56:16 amI don't understand, intuitively, why the gain (or attenuation) of the divider is treated any differently than any other gain block in the control loop.If I increase the gain of the feedback and reduce the gain of the plant by the same amount, the loop gain is unchanged.The loop gain is theproductof all the gains in the loop.Regards,Jay_Diddy_B

author: Kleinstein
author_rank: Super Contributor
timestamp: November 19, 2016, 10:49:24 am
content: Calculating the forward gain and treating the regulator as an amplifier from reference to output may not be enough to check for stability. We actually do not care very much about that gain, as the reference is not really changing fast. The important part is the loop gain, this G*H and the output impedance, thus the response to an current acting on the output.

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 19, 2016, 10:53:38 am
content: The output transistor M1 can be augmented by making it run in cascode mode, this way you opamp isn't sinking all that miller capacitance.Simply break the connection between M1_Source and R1, put a NPN here , a simple NPN bipolar will work 30v 1A or a small NMOS.So the opamp now drives the base (gate) of the lower transistor, and the gate of M1 goes to +12 via say 20R (to stop VHF oscillation).The cascode configuration can also be used with depletion mode FETs (Like the 1600v SiC devices).You will need zeners/diodes to 12v and/or "gnd" to stop the source node flogging around if the output arcs.(You need something from gate to source anyway with your existing circuit, otherwise arcs will cause punctures through the oxide).Note this idea is tossed in as a discussion point only, if your circuit works fine then don't mess it up.Note you can use a depletion mode MOSFET to make a simple bias supply, as per figure below, this is a 11v output LDO, with input voltage range 11.1v to 250v , Iq is ~ 100uA.(Output current is limited by heat dissipation, so maybe 2mA at 100v).This is thrown in for interest only, as it won't work in your circuit as it will drag the unloaded output up.(Your circuit could probably do with adding a PMOS to drag the output down anyway)

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: November 19, 2016, 02:45:20 pm
content: Quote from: blueskull on November 19, 2016, 08:32:32 amHi group,I don't agree with the analysis that k3 = R1 x Cout.ModelsI have generated 3 models on the same schematic to make it easier to compare the results.Vout_1 is a simple model a single pole with a frequency of 1/(2pi x (R1 || Rout) x Cout) but, if Rout >> R1, then Fo = 1/(2pi x R1 x Cout).Vout is considering the MOSFET and R1 to form a transconductance amplifier. This would be a pure integrator, except for a zero at 1/(2pi x Cout x Rload)Vout_3 is essentially an op-amp circuit with the same characteristics of Vout, but with a 180 degrees of additional phase shift introduced by the inverting amplifier. The voltage controlled voltage source E1 can be considered to a power op-amp with an open loop gain of 100K. This circuit is recognizable as an integrator with a zero formed by Cout and Rout.ResultsThe results suggest that circuit formed by the MOSFET, R1 and Cout is not the same as an R1 x Cout network, because it has a gain greater than 1 at low frequencies.Regards,Jay_Diddy_B

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2016, 05:09:13 pm
content: Again at the bench! Thank you guys for discussing the problematic in such detail. Although I do not understand everything now, I might in the future, when I will grow up and be like you guysI might have not specified in the beginning, that the whole "supply madness" is a part of my project designing a usable "high voltage" regulated supply 0-400V 0-300mA. There aren't many of those real usable designs on the web, so I accepted the challenge to make one. Sorry for not being clear from the beginning, but originally I have asked due to my colleagues concerns about the topology might be inherently unstable - which I am glad is not.I do understand, that there are many ways to design such supply, but please respect this is my first (or not exactly first, but first which might work) trial to make such PSU, so some compromises have to be donesalbayeng: Thank you for the tip to use cascode! I might try that one in the next better prototype. Gate-Source zener diode will also be added, together with other at least two protection diodes in the circuit (the schematics posted here are nowhere near complete, more like describing the principles of the regulation loop)Kleinstein: Yes, current limiting is what I need to do next. Or before I do, I need to think out how to merge the voltage and current control loops.Could you please help me evaluate my ideas for merging the control loops?One of the usual ideas behind current limiting seen in many other circuits is that the current regulator opamp drags the voltage regulator reference input down, through a diode. However I can't use that, as I would need the opamps output to go negative (one diode drop) to be able to drag the ref voltage down to zero.The idea behind using the inverting amp as a voltage divider was that only unipolar supply voltage is required. Therefore I cannot use the "ref voltage clamp" technique, as I can't go negative, as described above.What I thought was I could sum the opamp outputs through diodes and "hang" the gate with a resistor (or possibly current source) up to the positive supply. The schematic is below, image A. This circuit has a dangerous flaw: To be able to control the mosfet fast enough, the source current through Rg might be high (some tens mA). That means the diode voltage drop will be quite high and also the opamp output saturation voltage adds up. This means the gate voltage cannot be brought directly to zero, but only about a volt or so. (one diode drop + opamp sat.)I think better solution might be to use the B variant on the schematic below. The diode drop is compensated by the Vbe of the transistor. So when the cathode of D1 or D2 is at GND level, the emitter will be very near GND too. Also the current through the diode and opamps output will be low, resulting in low saturation voltage and the widest range of gate control voltage down to almost zero. The emitter resistor Re might be also replaced by a current sink: A simple two transistor one (adding few hundred mV of drop) or likely just JFET as a current sink?What do you think about this idea? Is it a good enough solution or are there similarly simple but better ones? How will this influence the control loops?Thank you!Yan//EDIT: Just a thought: A diode accross E-B of the emitter follower might speed up gate discharge, as the opamp sink current ant I(Re) current will sum.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 19, 2016, 06:08:47 pm
content: Both ways for combining voltage an current regulation can work. For most MOSFETs a gat voltage in the 0.7 V range will not turn on the MOSFET. This is especially true for older types suitable for linear operation. The version with extra emitter follower also work an has the advantage of slightly more driving power for the gate capacitance. So it can slightly speed up the output stage, which usually is good for the control loop (usually no changes needed, but might be possible for faster regulation). Likely the voltage range for the gate voltage is quite limited - so the resistor can be good enough.If needed one could add an additional drop, so that the OPs need a higher voltage to turn on the output stage.For the control loops one might consider moving the capacitor from the OP output to the source resistor - this somewhat limits wind up if current control is active and thus speeds up the switch over from CC to CV mode.The extra cascode stage is not that important unless one wants a really fast regulator. One can als o use a similar configuration to combine two transformer taps, to reduce heat production: use the one FET or BJT as a cascode for the higher voltage tap and use a diode to provide power between the two power transistors.

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2016, 07:09:36 pm
content: Thank you for confirming. I will modify my circuit on veroboard and test.Sure 1V should not open it, but still I don't quite like it, so I came with a better solution.I think I will not be bothered with extreme switch over speeds from CC to CV in this case. I think the best solution would be to use similar circuit like in the LM12 datasheet, where transistors are used to switch in or out the oapmps local feedback RC cell. But it might be an interesting thing to test or compare, if there will be any improvement (remember we might have some or more capacity on the PSU output, so extreme switch over speeds aren't possible either)I might use the cascode configuration in another project. If I am not mistaken - Keithley 2600 series SMU use similar cascode arrangement, aren't they?This time I have designed a stepdown preregulator, no transformer taps switching. The project goal was to use cheaply available transformers 400/230V (connected in reverse) we use here often in industrial control systems to obtain 230V control voltages from 3ph power systems where connecting a load between phase and earth is not possible (like 4 wire only 3ph supply after an RCB). These transformers can be bought like really cheap and are safe, usually double insulation rated.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 19, 2016, 07:45:51 pm
content: The circuit in the LM12 data sheet looks strange / interesting, somehow using the transistors in revers too. I am not that sure if this way can easily be used for this topology. Usually current regulation is relatively easy in this topology. Somewhat opposite to the emitter-follower form, where voltage control is a little easier, but current control can be hard.The output capacitance is not that large yet so one might still want a reasonable fast transition to keep overshoot within bounds. If you look at regulators using the emitter-follower topology for comparison, the visible output capacitance might be smaller, but quite often there is some more hidden in the circuit. A slow responding current limit might have a similar effect as some 1000 µF of output capacitance.There is also an easy option to add just 1 or 2 diodes as a kind of shunt regulator to provide something like a -.6 or -1.2 V negative supply for the OPs and regulator circuit, as long as there is only little current drawn from it. So keeping it single supply might not be the highest priority.The Keithley SMUs use some kind of cascode type circuit to use more than one raw voltage / transformer tap, but also some parts to divide a high voltage over several devices to get better SOA. But things get more complicated as the SMUs have a 4 quadrant output stage. This type of regulator is more like 1 Quadrant, maybe extended to 2 Quadrants if one wants to.

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2016, 08:12:46 pm
content: I have actually tried the transistor-switched comp. cells in one of my projects few months ago - it also was 4 quadrant +-3V +-5A supply I tried to design for local university, but before I finished a PCB, they changed their minds and didn't need anything. It worked quite well.The design goal is really not to use *any* negative supply at all. I don't like this in PSUs - one have to careuly look for unwanted glitches in the circuits, where one rail ramps up or dies sooner or later than the other. Sometimes even extra protection circuits are required to get rid of such glitches. So this time I'd try without any negative rails if possible.I will try the "B" variant of the merging circuit. The gate-ground voltage measures about 5.4V at 27mA load (just took random measurement what to expect there). Interestingly - I consider the 4.8V gate-source voltage rather on the high side while the mosfet being just barely opened. But who knows, maybe a higher threshold voltage.I will use the B variant for now, without the CCS, just gate-ground resistor. I will try with 30mA drive current (will be sufficient?), meaning I need about 150ohm resistor down there.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 19, 2016, 08:41:56 pm
content: 30 mA of current is already quite a lot, already more than an typical OP deliver. So at least with such a high threshold the resistor should be ok. One could even use an emitter-follower NPN+PNP push - pull stage, driving the PNP from the diodes.

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2016, 09:13:55 pm
content: Yes I have also thought about that. I think the PP stage should be with at least some base-to-base voltage or ideally some bias current, otherwise I am afraid the "hysteresis" or "crossover distortion" or how to name that might be a trouble for the control loop. But this complicated current boost stage might be more complicated than what is really needed, so I'll try the simple first.If I weren't so tired today... yaay. Still just writing here and doing nothing, the soldering iron is cold.

author: Yansi
author_rank: Super Contributor
timestamp: November 19, 2016, 10:47:30 pm
content: With a little help of coffee, the circuit mod is finally done. Rb=2K2 (round about 2.5mA to the opamps), Re=150 (did want to try 180, but couldn't find any)Circuit still stable, step responses hasn't changed much, if at all.Now I should cobble together the current regulator on the veroboard, so we can have some other thing to play with.

author: Yansi
author_rank: Super Contributor
timestamp: November 20, 2016, 01:03:27 am
content: What an epic win!I have put there another opamp as the current regulator. Did not bother to connect any feedback cap across the opamp, turned it on to see if it at least works, while expecting it to oscillate wildly when the current limiter kick in. And guess what: Nothing! And then I noticed it does limit current and is stable without any additional R/C. (Only 22k resistor in the inverting input)So the high voltage PSU prototype finally works! Tomorrow I will test step responses of the current regulator and the CC/CV switch over. Thanks so far very much for help, now some bed time is needed!Here is the photo of the little bastard.

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 20, 2016, 01:11:30 am
content: Step response testing:I just connect a small relay coil to a signal generator set at ~ 1Hz (10v output into 600ohm drives a 12v 1000ohm coil nicely)use this to switch your dummy load, really only good for 100vDc per contact, 2 in series will get you 200VDc, more than that and you will need MOSFET.Note that 0-10% transient responses are different to 10% TO 100% transients.Note re current limiting: if you have integrators in your voltage loop, then applying current limiting after the integrator will cause the capacitors to charge up fully, at that point the inputs of the opamp will float away from each other, and it will take a loooong time to recover.

author: Yansi
author_rank: Super Contributor
timestamp: November 20, 2016, 01:42:35 am
content: I have made this for step testing this supply. NE555 + suitable mosfet and bunch of resistors (value selected through the switches), trigger out to the scope.

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 20, 2016, 03:02:38 am
content: Nicely made dummy load!I used to make them neat when I was younger, but after you've killed 4 or 5 of them, you get a bit sloppy!.See attached for a dummy load and 20v 40A supply for testing a 24VDC distribution systemand a nice looking one (on the outside!) I made maybe 20years back (the DPM and fan is dead and some switches too)I use these cheap 100W rheostats a lot too, only broken one so far!

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: November 20, 2016, 05:02:12 am
content: Blueskull and the group,The difference is more than taking the Thevenin equivalent circuit and paralleling R1 and Rload. This is only a very small change. Typically R1 would be 100 times smaller the Rload, just for efficiency reasons.This is the point that I am trying to make. This circuit:Which represent the MOSFET stage and R1 as a transconductance amplifier, does not have the same transfer function as this circuit:In the second circuit, the maximum size of the output signal, is the always less than the input signal. At low frequencies this circuit has very small phase shift.In the first circuit, which represents Yansi's circuit, the amplitude of the output can be greater the input voltage. At low frequencies, and high value of load resistor, the gain is high and the phase shift is -90 degrees. The circuit is an integrator.Regards,Jay_Diddy_B

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 20, 2016, 06:38:10 am
content: Yea, you're right, of course. (an improvement on "right off course")I first looked at the output stage and thought to myself , "the output impedance is just R1 (as the MOSFET that shunts it in current mode is effectively infinite impedance)"It's obvious if you consider the output swings 100's of volts but only a few volts across R1.The maximum gain (at DC obviously) is simply 100k/R1.The simple circuit you have is sufficient to explain what is going on.I would add the embellishment of(a) the gate resistor and miller capacitance but guessing 300R and 1nF puts a pole in at 500kHz, of no concern(b) and also add the zero due to ESR 100uF + 1R is only 1.6kHz (I should probably find some real capacitor data and not guess!)

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 20, 2016, 08:34:49 am
content: Tried to check on ESR for typical capacitors.Most datasheets stop listing ESR above 100v rating, If I do some extrapolating based on tan\$\delta\$ and rated current, the quality 105C electros have ESR's from 3 to 10for 10uF/450v. (say 3kHz for 5ohm + 20uF)A datasheet for 85C rated capacitors is here:http://www.mouser.com/ds/2/88/SK-32353.pdfthis shows 26for 10uF/450V , this gives a zero at ~ 600HzIf Yansi were to use a 1uF 450v polypropylenehttp://au.mouser.com/search/ProductDetail.aspx?R=0virtualkey0virtualkeyECW-FE2J105J, reasonable size (28x17x10) and 66cThis has tan\$\delta\$ < 0.1% , which is <120millias an ESR at 1kHz, This would push the zero out to ~ 200kHz.

author: Yansi
author_rank: Super Contributor
timestamp: November 20, 2016, 10:16:29 am
content: Hi!I am using X2 rated caps in the circuit, as I have many of those available and they are sufficient with voltage rating.Currently the output cap is an 1uF MKT from Vishay, so not polypropylene but polyester:http://www.vishay.com/docs/28161/f1772x2.pdfIt has a an added series resistor of 1ohm, as you did recommend in the beginning.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: November 20, 2016, 12:51:17 pm
content: Quote from: salbayeng on November 20, 2016, 06:38:10 amJust to clarify this further.You may not have seen this circuit before:But if you rearrange the parts:It begins to look familiar.You have probably seen this before:It is a textbook common emitter amplifier.If you ignore Cout, the simplified voltage gain of this stage is Rcollector / Remitter.The challenge with designing a (bench) power supply, is that you don't know what value of Cout or Rload somebody will attach. The load may not be a resistor. If the load is a constant current load the gain can be very high.If you designing a power supply where the load and capacitance is know, it is a little easier.Regards,Jay_Diddy_B

author: Yansi
author_rank: Super Contributor
timestamp: November 20, 2016, 09:35:42 pm
content: Hi! A little update: As the current limiter is working just fine, I left it alone and have begun working on the preregulator control loop.Before I started with the preregulator, I have noticed an unseen problem in the circuit (you can skip if you want, really nothing serious or much interesting, easy solution):Way back when we discussed how to merge the two regulator outputs, we had the choice between resistor or CC load for the emitter follower. The resistor works fine, sure, but there is a problem! If the regulator output goes into positive saturation (like "not enough input voltage"), the resistor in the emitter of the follower will get blown after a while: It was calculated for 30mA at round about 6V gate voltage, which is fine. However when the saturation occurs full voltage (like almost 11V) appears on it and high current is gonna destroy it. So the CC load might be a better solution, than an over engineered (1 or even 2W) resistor, that won't see more than 0.2W very often. The overload is somewhere about 0.8W so 1W resistor is not such a big deal. But just wanted to point that out.Preregulator: Is a textbook standard inverted buck (switch and choke in the negative rail, positive common) controlled by an UC3843. I have successfully tuned the opamp that controls the preregulator. Partial schematic attached. Vds is a voltage sensed from a mosfet drain, ground is still the positive output terminal. Works quite good.Step response of the preregulator output is also attached. Supply set to 75V, then shorted for a moment. Preregulator holds constant 50V over the mosfet. The undershoot is about 6V, no big deal - caused very probably by a windup of the integrator - as the ramp down speed is limited by the discharge rate of the prereg output cap (depends on supply output current).The LED on the schematic is an optocoupler to the COMP pin of UC3843. There is a mistake in the drawing, the LED should be connected of course against +12V, not ground (otherwise the polarity of the feedback is wrong).Slight problem 1: At some level of PWM, the current mode control of the buck convertor is still very slightly unstable (at the currentmode side of thing - subharmonic oscillation, even though I tried to apply a slope compensation. (Maybe doing it wrong or completely another problem). I will draw the complete schematic so we can look more in detail, where the problem might be.Another slight problem 2: After adding the drain voltage sense divider, you know, across the mosfet... guess what, current flows to the PSU output even when the mosfet is fully closed. Meaning, when the PSU is unloaded, quite some volts are present - 180V or so to be exact. (voltage divider is formed from the two voltage sense dividers 800k / (800k+330k+22k) * LinregInputVoltage).Now what to do with it? Low value resistor accross PSU output terminals is not a solution, due to very wide voltage range (the parasitic current flowing from up top is constant (as the Vds voltage is also constant), about 0.15mA. A small CC load on the PSU output would do. What do you think?Thanks,Yan

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 21, 2016, 01:45:33 am
content: re problem 2:If your switching regulator is connected to the real negative ground, then use two matched voltage dividers, one for the prereg voltage, other for the drain voltage, and use the difference of these. With a bit of cunning you can bleed your setpoint voltage into one of these legs. So it's just one opamp needed.The problem of the output floating up is to be expected, (and you will get leakage current in mosfet and on PCB's particularly with heat, moisture, aging, lint buildup) I looked at this and didn't have an elegant solution (else I would have posted it) , you need a Ptype device, but there is no footroom to drive it. possibly lifting the bottom leg of R1 by a few volts would allow a PMOS to be activatedAlso note for the dropper resistor in the divider, use 3 or 4 in series , allow for no more than 200v per resistor, and ensure you use metal oxide resistors, rated at 300v.re the first problem:Cheapest is sometimes the best; use a 2w resistor is a viable option, there are some axial types in 1W package sizes, they get stinking hot, they have really thin steel wires so the body can be 250C, but not conduct enough heat to melt the solder.You could use back to back diodes across the integrator cap, but difficult to decide which voltage to use, and you would need the low If, low leakage variety. Note this saturation problem is vaguely related to your problem 2 , like many elegant designs, things get real ugly when you have to contend with all the exception handling.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 21, 2016, 05:30:13 pm
content: To compensate the leakage current or current through the drain-source sensing circuit, one could add a constant current load to the output. One can use the (supposedly 12 V) supply for the OPs for this to provide headroom to make it work down to zero:Have a PNP transistor with base connected to GND, a resistor (e.g. 10 K) from the +12 V (preferably regulated) to the emitter and the collector to the negative output. This would provide something like a 1.1 mA constant load, working down to about - 600 mV. So to avoid the possibility to get a slightly negative output one could lift the base to that about 600 mV (e.g. one diode drop - saturation voltage of the PNP). As the current from sensing the DS voltage is pretty constant one can compensate this also.Unless for very high voltages the pre-regualtor should be set for much lower DS voltage. Usually something like 3-10 V should be enough. It is just to have some reserve in case the preregualtor can not follow fast enough. There should also be an filter between the two stage, to keep RF noise out.For the gate drive, it might be a good idea to have a fixed maximum voltage limit for the gate - this would also act as an independent fast acting instant current limit, though not accurate.

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 22, 2016, 03:43:21 am
content: I've combined , (and hopefully improved upon) Kleinstein's ideas.(a) Inherent current limit of the main MOSFET (Q1) in my schematic , by voltage limiting the gate (to 12v in my schematic) , and setting the emitter resistors R4+R5 to produce the appropriate current limit. I've added C1 so there is a fast current limit of ~ 20mA to charge up the output cap , and a slow limit of 5mA, obviously you can adjust these values as required.(b) constant current pull down this is Q3 in my schematic (could be a PNP , I didn't have any HV PNP in my model library, and too lazy to import a model) , for a fixed current , connect gate to gnd, and omit D1, set R2 to 10k, and that's the 1.1mA source Kleinstein refers to.I've embellished it so it only comes on when the capacitor needs discharging. The big problem with my approach is the crossover, and discharge current is achieved by subtracting 2 x Vth and a zener drop from 12v, so if any of these move around much it won't be accurate.You could also split R2, and add a speed up cap just like C1 if you were that way inclined.I've also set resistor values so the error voltage can swing through the entire 12v available , and now the upper 4-12v region controls the charging current, and the range below 4v controls discharge , given the mosfets have ~ 4v this went together better than I expected, so we have basically a class AB amplifier stage.The simulation produced excellent response with no feedback around X1, although Verror was oscillating ~ 1MHz!I took a wild stab at some compensation values, and it's pretty good now as shown with 100k & 1n , the opamp gain is 100 above 1.6kHz . and an integrator below thatThe step response overshoot is about 1v at 300v ,slightly underdamped ,ringing at ~1kHz ( I repeated sim with smaller timestep and relative accuracy and its still similar looking, so the sim might be believable!)The closed loop responses attached (blue = 3meg, red=30k load) shouldn't be trusted, I'm not sure where the bias point is . The blue one corresponds to the observed step response.The sim just applies a step change in the setpoint to and from 70v to 320v, I've stepped the load from 30k to 3meg, with 30k you can see the current limiting taking place, and you can only sustain ~ 140v across the 30k while in current limit mode.There are figures attached for the output voltage, current, error voltage, and drain voltages.

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 22, 2016, 08:11:28 am
content: Ok , I've managed loop gain plot (Using Jay_Diddy method), see pdf.I've done this with 3 load resistors, 30k, 300k,3meg red green blue for loop gain , and light shades of same for phase.The 30k & 300k are pretty much under each other , the 3meg is different , presumably the mosfets are biased into a cross-over dead spot?The phase at 0.01Hz starts at 180deg , and the gains level off (as the op-amp maxes out its gain)According to the plot, loop gain is 0dB ~ 2.5kHz, with phase ~ 55deg.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 22, 2016, 10:55:12 am
content: Adding a P-MOSFET in the way salbayeng did, is adding limited 2 quadrant operation. This can be an big advantage when is comes to recovery from large disturbance. This version needs an stable 12 V (preferably a little lower) supply and might be a little sensitive to thermal drift. The zener diode would need an individual adjustment, depending on the FETs to keep the dead zone small or even ensure class AB operation.Adding the phase boost with splitting the source resistor is less practical. One thing is that it need a quite sizable capacitor, if R5 is in a much smaller more realistic range (e.g. 1-10 Ohms). The advantage of having the phase boost in the feedback divider is that it also reduced the bandwidth requirement for the OP and together with protection diodes it helps with the CC to CV transition without much overshoot (tends to be a little slow instead).

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 22, 2016, 12:03:21 pm
content: Yep I acknowledge it's not perfect, I just scribbled it on bit of paper to see if I could avoid having a current source on all the time, by simply moving Q3 gate drive across,I tried it on a sim and it worked better than I expected so I printed some epictures off and pushed it here for comment.The "emitter bypass" cap wasn't primarily for phase boost, I would expect to use a shunt cap on the feedback for phase boost to improve HF regulation.I had it working open loop just driving a trapezoid pulse into the gates, and it worked well, so just closed the loop as simply as possibly, R11 and C3 are the default values Simetrix drops in, and 100k gives a gain of 100 which seemed appropriate, I wasn't trying to get an optimal controller, just wanted to see how well the crossover worked with a closed loop, heck even the 4.7v zener is the default zener, and I fluked about 100mV crossover overlap. Q3 is only a 50v MOSFET, but a quick edit of the spice file fixed that!.The 1k / 500uF is intended to provide a time constant of 500ms, to approximate the thermal time constant of Q1, so it can draw more current for short periods of time.While pea-size 560uf/6.3v caps are available as polymer dielectrics, this brute force approach is unweildy with say 100R as the source resistor.And you could do the "anti-surge" feature using smaller capacitors, a handful of resistors and a zener in the gate drive but it's less elegant.I've used the PMOS threshold before (as a 3.8v reference voltage) to set pullup current in some active terminators in another project, and over ~ 60 units there was a 5% spread in actual currents, better than I expected , and those current sources also used an elegant method to reduce power consumption when not actively switching.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 22, 2016, 12:17:00 pm
content: The source resistor should be much smaller - even the 22 Ohms that the OP used are relatively large. Otherwise too much voltage (and power) is lost there. For the P-MOS the source resistor might be relatively large and the capacitor to boost the current for short times might be viable.For a short time current limit a zener right at the output of the OP (or where the CC and CV signals are combined with diodes) is more effective. There just is no need for a very high gate voltage. This would also save the small resistor at the emitter follower.

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 22, 2016, 01:35:42 pm
content: Ah found it, the OP says 150mA, (for some reason I was thinking it was in 5-15mA range???) OK an upper bound might be 1W or 3v at 150mA = 20ohms.Probably don't need the "surge" feature as 150mA will charge the cap fast enough.??One could probably achieve rough local current limiting by using a small NMOS (2n7002) to drag the big MOS gate down. It's threshold is ~ 1.8v , so with a 10ohm source resistor, current limiting would occur around 180mA, (and you could put in a high impedance RC network if desired for "surge" protection),For more accuracy, substitute a TL431, it will pull down the big MOS gate at 2.499v across the source resistor. Although if one were using an opamp for CC mode, the local current limit would be superflous, design effort might be better spent on thermal protection.I can see how the boost cap for the PMOS would be useful now, with 150mA load current, a capacitance of 10uF might be required for adequate filtering so the PMOS may need to handle 10-20mA during reference changes to constrain the slew rate.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 22, 2016, 05:47:19 pm
content: Note that the source resistor contributes to loop stability, because it sets the maximum transconductance of the pass transistor.Tim

author: Yansi
author_rank: Super Contributor
timestamp: November 22, 2016, 09:46:39 pm
content: Thank you guys for more detailed analysis of the circuit. I have been few days quite overcome by my other work, so sorry for a small drop in communication. Hopefully I will draw the full schematic soon, so we can discuss a bit more in detail about the whole circuit.Yes, the preregulator will have a filter attached on the output, you will see from the full schematic. (however there are still some unknown, what capacitances will be used there).You think those 50V reserve accross D-S is too much? Well, cannot say much about that. Just wanted to be sure there is enough headroom for the voltage reg and also that the negative undershoot of the preregulator can not cause problems (currently 6V undershoot - but I think no easy solution for it, as the negative slope of voltage is given by the discharge rate of prereg output cap and windup occurs in the integrator in the control loop - please see my last post)The overall goall is to make a decent (but not overcomplicated!) regulated PSU of 0-400V 0-300mA. As the current circuit seem very much viable, should not be much problem to scale it up for that goal. Bigger mosfets are on the way, so I might have them on friday.I have chosen easily available and quite cheapIPW90R1K0C3from Infineon, will be two of those devices in paralell (to increase SOA withstand capability of the linear stage against direct shorts or any wild overloads, where the mosfet will see full voltage accross D-S and full current for a moment). The source resistors should be left the same value, 22ohm per mosfet (11ohms together, so same drop at full 300mA output as we had so far with 150mA). But I might drop the value down if necessary.By the way, what is better for the control loop? To have bigger or smaller source resistance? With higher resistance the mosfet should behave more like a current source device, more linear than with very small source resistance. Also should be better for a "SNR" side of thing (offset voltages will hide better if the signal value is higher, do not want to sense milivolts there). There is only half a watt being lost (0.15 squared times 22), 1W together both shunts at full output current. I don't thing it is a big deal, for a 120W output supply, do you?I will use some constant current load on the output, to (maybe? over-)compensate the current leaking through the D-S resistor divider (feedback for the prereg).Note that the 800K feedback resistor is actualy 330+470 K in series. Shall withstand 400 volts together easily.Yansi

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 23, 2016, 04:29:23 am
content: More source resistance is better. The maximum value is [V(opamp-supply) - Vgs(th)] / Iout(max), so in principle you could use a high voltage amp (Vsupply as high as Vds(dropout), say?) and make it stupidly linear.But really, more than 10V gate to common isn't important.Source resistor also affords you short-circuit, reverse and surge protection. Put a zener from common to gate, and the transistor will limit current on its own, no matter how suddenly the output gets pulled around (say from connecting up a fully-charged electrolytic backwards, or several accidentally stacked somehow).Putting active current and voltage limits on top of that makes things all the sweeter.(You actually want the protection network a bit more complicated than a single zener, since reverse surge would do nasty things to the simple connection above. A diode or zener at G-S, and a series resistor, in the common/ground return path I'm thinking, would be best.)Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: November 23, 2016, 05:14:58 pm
content: A relatively large source resistor is needed to make the current sharing work well. The 22 Ohms are well large enough. The gate (especially gate to drain) capacitance might be a considerable limit to common mode rejection, e.g. ripple of the switched mode stage. So one might consider the earlier mentioned cascode circuit might be worth a thought with higher power (two quite large MOSFETs) - to a certain degree this an alternative to a more power full gate drive.The drop on the linear output stage does not need to be much larger than the undershoot / drop of the pre-regulator. So something like 10 V should be enough. Overshoot of the pre-regulator might be relevant for worst case power loss for the FETs.I am not that convinced the choice of MOSFET is good - this are modern fast switching types, that tend to have a not so well suited SAO. Though the high voltage helps. The more natural choice would be old types.

author: Yansi
author_rank: Super Contributor
timestamp: November 23, 2016, 06:59:52 pm
content: Look carefuly: The mosfet that I have chosen is DC rated. I don't know a single one "older" type of high voltage mosfet that has a DC SOA. Ant the SOA limit is only power limit in reality (no second breakdown as BJT ones have) - which is what one would expect from a mosfet that is rated for DC linear operation.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 23, 2016, 07:47:08 pm
content: The problem with modern MOSFETs is that they do have an effect similar to second brake-down, it just got a different name. So if the curve only shows the a simple power limit, there is a good reason not to fully trust that curve. The old first generation MOSFETs usually did not have this extra limit, but modern types usually have. However I also do not know a suitable type.It is well possible that FET could work. Under normal conditions it will not see more than 50 V for more than about a few ms (if at all). Also many of the MOSFETs can survive quite some power, but one never knows. Especially many modern FETs are not made and tested for linear operation, but for fast switching and low R_on from a small die.

author: Yansi
author_rank: Super Contributor
timestamp: November 23, 2016, 09:11:12 pm
content: If the SOA states only the power limitation, there should not be any other limitation. If there is, the manufacturer is lying and it would be a big trouble for them then.Also not much mosfets are with DC SOA today, so if you find one that is, I think one could rely on that.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 23, 2016, 09:22:36 pm
content: SuperJunction FETs apparently are "free of" 2nd breakdown. Which is remarkable, as they have the highest current density among MOSFETs, too. I haven't seen any articles discussing this aspect of the technology.As far as I can tell, there was only ever one reason why MOSFETs claimed to avoid 2nd breakdown:they sucked. Until recent advances (Trench, VDMOS), the current density was always significantly lower than that of BJTs. The gain is lower, too. The power levels required to cause 2nd breakdown would've been perhaps 10 times that for a contemporary BJT, or even more -- nothing that could ever possibly be achieved, given the limitations of the package.There's no such thing as "free from 2nd breakdown", only that it be inaccessible within package dissipation limits.Which, by the way: I don't think I've ever seen a SOT-23 MOSFET with 2nd breakdown limits. There's just not enough heat flow through the package to cause a gradient in the die!IGBTs have even higher power densities, with the sensitivity (gain and tempco) of BJTs. Though, remarkably, I have seen a few datasheets (not many) which show power-limited DC SOA. I find this suspicious, and wouldn't recommend using them that way without extensive qualification testing.I have no problem with using MOSFETs where the SOA says they're okay. Qualification is always good, of course.Related: I tested an IRF740 to have RthJC something like 60% of the datasheet (maximum) rating! Those old chips have one thing in common: huge dies. In comparison, a brand new Fairchild FDPF6N60 (I think) expired damned close to its ratings, like 5% over. Tiny die!Tim

author: Yansi
author_rank: Super Contributor
timestamp: November 23, 2016, 10:11:29 pm
content: Oh yea, that's why I fuckin hate those new "150A" mosfets in DFN (and similar) SMD packages, where the claimed cannot be ever reached in real applications.IRF3205 and IRFP4110 is still the top of quality products I have ever used. (And those old IRF540 and similar are still the good ones). Huge dies!BTW, the courier was almost unimaginably fast, they delivered me the parts today (although I expected tomorrow at best). So now I have the 90R1K0 Infineon mosfets prepared for some more weekend toying. Also bought some STF3NK80Z for the prereg, as those STP6N80K5 I have used so far in the prototype (both in the prereg and linreg part :-) ) to be too good for the prereg, will try the cheaper ones. Should do good enough too. (Also I like the fully plastic body more for this application)As far as the prereg voltage setpoint over the drain-source of the linreg: Yes, I might lower the voltage, I admit those 50V might be more than what is really needed. (it is an easy mod, also I plan to leave a trimpot for this in the final design).Y.

author: salbayeng
author_rank: Frequent Contributor
timestamp: November 25, 2016, 09:00:05 am
content: For the pre-regulator, I would suggest a slightly different approach(a) make a fast, low gain inner loop that controls the voltage output of the pre-regulator so it tracks a reference voltage, the pre-reg output would then havesmallish capacitors, and probably a fairly high ripple. Theloop gain would be fairly low, e.g. the pre-reg output might droop 10v under full load, (so GH~40) , and there would be no integrators to wind up.(b) form a reference voltage that is equal to output voltage + desired_MOSFET_drop , so you are making an outer loop that controls the MOSFET_dropWhile it might be argued that (a) and (b) together are algebraically the same as what you already have, but in practice you can employ different filtering to the signal path in (b)(This approach also avoids the voltage divider leaking current across the MOSFET)Because your buck stage is back to front, in practice the feedback for (a) is a difference of Bus_plus - Vout_minus, and the reference voltage in (b) is generated from another difference amp Vout_plus - Vout_minus. You won't need an opto-coupler either, and you can feed in your desired_MOSFET_drop using the 5vref on the UC3842. The downside is you may now be leaking current across the pre-reg MOSFET.An alternative is to use a current mirror as a level shifter to replace the Diff amp---------An alternative control for the pre-reg might be hysteretic control , this is always stable (or always unstable, depending on your viewpoint!)-----Something else to possibly throw in series with one of the supply lines is a largish bobbin type inductor with a diode across it, but depending on where you hook your power supply caps, you probably wont need this (and your supply is current source essentially). This helps avoid extreme levels of short circuit current when discharging capacitors. Basically the inductor sucks up the capacitor voltage for the first millisecond or so, and discharges the capacitor at hundreds of amps instead of thousands, the internal resistance of the inductor also limits the short circuit current, and the large slug of copper sucks up a lot of joules. The diode is there to recirculate the stored current when the short circuit is removed. If there is a semiconductor involved , having the inductor there pushes the locus down in the SOA curves to a safe region, and gives control loops time to respond.

author: Yansi
author_rank: Super Contributor
timestamp: June 12, 2017, 05:04:30 pm
content: Hello guys!After some long time, I have finaly found some time for more hobby electronics toying. This is the result:A fully working CV/CC programmable power supplies 0-300V 0-100mA.A dual channel 12bit DAC with a 12bit ADC (for output current measurement) have been added together with an isolated DC/DC and digital SPI isolation. The module requires just the unregulated input of 300+ V and 5V for the controls. The floating section is powered from the 5V through the isolated DC/DC.These are based exactly on what you have helped me a lot with in the above comments. These two will be used in a later project. The larger power supply with the switchmode pre-regulator we have discussed (400V 300mA) is still under development (waiting till I have more time to design some custom PCBs for it).Many thanks! Will post more when I get more time to finish this supply.Y.

author: marcopolo
author_rank: Regular Contributor
timestamp: February 11, 2019, 12:32:23 pm
content: Any news?

author: Yansi
author_rank: Super Contributor
timestamp: February 11, 2019, 03:08:19 pm
content: Hello, unfortunately not many news - what exactly do you have on mind?The programmable modules are still sitting on the shelf, waiting for the control board to be assembled. (I have some troubles on the control board to be solved there too - I need a DAC output within the range of +5 to -55V).The original idea of 400V 300mA power supply with switchmode pre-regulator is currently at rest, due to other high priority work and access to a proper 3kW 500V PSU from ElektroAutomatik. I could make some pretty interesting series of episodes of the design failures in those two EA power supplies I have repaired.Also, I have helped my friend to design a linear power supply using this topology, I will post an image when it'll be finished.

author: marcopolo
author_rank: Regular Contributor
timestamp: February 11, 2019, 04:13:34 pm
content: Hello,Something like the final schematic

author: Neomys Sapiens
author_rank: Super Contributor
timestamp: February 11, 2019, 09:21:16 pm
content: Quote from: Yansi on February 11, 2019, 03:08:19 pmOOOh, yes please! Black cloud of shame over Viersen!

author: Yansi
author_rank: Super Contributor
timestamp: February 11, 2019, 11:14:21 pm
content: Well... just as a sneak-peek: Our team bought a 10kW up to 1000V 30A power supply from Electro Automatik Gmbh (EA-PS 81000), to charge our prototype EV traction accumulators with it. The damn thing exploded like at least! four times (and at least three times was sent for warranty repair), and under the most bizarre circumstances.It has even exploded once, sitting turned on on a table, with no load. BANG! Something blew inside. Most of the time, the power supply had like 10-20 hours of run time before the big bang happened.You know, these blow ups were one hell scary, if it did that, while the traction accumulator was connected to it. Fortunately, we have had it always connected through fuses and safety disconnect relays and the damage never occurred on the secondary side of the PSU.One time we desperately needed to power supply (but it was again kaputt gemacht), so we have requested a temporary replacement. We were given a different type (1U rack-mount 3kW 500V one, don't know the type off-hand). And guess what! Once upon a time at the place wee needed it the most, it blew like hell too, just after I have plugged it in the wall and flipped the switch. It has just shown the obligatory "Device is starting up" and then all hell broke loose inside.So, ended up with two exploded very expensive power supplies which one of them was not even ours, the company finally stopped communicating with us (as far as I was told so - I was not the one in charge of "communication").We ended up voiding the warranty on both PSUs deciding to see where the issue was (the manufacturer never told us, they have just swapped the modules inside and sent it back with a paper attached to it how within specification the unit was after repair).Later we have learned, that the temporary 3kW power supply exploded due to short circuit on the DCbus after the PFC circuit - due to them (Elektro Automatik) using a fucking damn stupid thin kapton foil as an insulation for the components on heatsinks, and that further due to cheaping out on a €3000 or €4000 power supply, to omit the obligatory Y2 caps to couple the heatsink to ground (to reduce RFI, it was rather directly sitting on the hard DCbus+ potential, increasing the potential (no pun intended) of the big bang.The kapton foil failed, due to probably a burr being present on a TO247 shunt resistor (stamped aluminium back side of it) in the PFC circuit that have over time pierced the kapton, or the resistor failed itself, resulting in the damage of the insulative kapton tape. Not really sure which one first, that would require further writing, which I currently do not have time to do.The other PSU, the big 10kW guy is a completely different matter. Although still kapton tape insulation on the heatsinks, the failure mode was completely different - probably arc-over on badly designed PCB. Combined with the fact, we used the PSUs on mobile basis in all kinds of different environments (but never damp, mind you!) coupled with absolutely NO particle or dust filters on the fans and lack of conformal coating, was a disaster waiting to happen.The 665V DCbus jumped across to the control circuitry and blew the shit out of it. I have once tried repairing it with my friend (after spending numerous tens of hours reverse engineering the schematics of that over-complicated thing), but it blew again in the same spot just as we were slowly bringing the PFC section back to life, which was just pita and a show stopper.The smaller 3kW PSU was successfully repaired. Fortunately just the DCbus was shorted, no damage in any of the electronics occurred. I have replaced the fucking kapton with kerafol. It is working flawlessly ever since (and hopefully will still be). We still posses the 3kW PSU, they never wanted it back. If they will, we will likely charge them the repair costs.So the lesson learnt here:1) Elektro Automatik PSUs are not really worth the money they are sold for. Although nice and shiny on the outside, the PCB designs inside are just pure hell. It is I'd say obvious, the designer haven't had much of a clue* how to do layout of switchmode power stuff, the power components are all over the place with in my opinion just extreme lengths of parasitics within the current loops and the control circuitry aint any better: Looks like someone dropped a bucket of SMDs on a PCB and let the auto-router software loose. (It was absolutely evil to trace the control circuitry). Also some shape features on the PCB were found very funny looking.*or he wasn't let to do it better in the first place.2) do not use kapton tape/foil as (the only) thermally conductive insulation material, between heatsink and components. Can be easily nicked and punched through. (And also I think it even doesn't have that good thermal properties, does it?)As I have said, this would make a few very interesting episodes by itself, now I will just end with a couple of photos of the aftermath.Inside of the 10kW PSUWhere the arcover occured (There is straight DCbus right on the pinheader)Mess after the PSU was raided by us reverse engineering almost every single PCB of it.Inside of the 3kW PSUYou could probably tell where the sharp burr was

author: Yansi
author_rank: Super Contributor
timestamp: February 11, 2019, 11:29:33 pm
content: Quote from: marcopolo on February 11, 2019, 04:13:34 pmThe original idea of building the 400V 300mA PSU is not completed yet, see above. The circuit is a huge spaghetti ball across a couple of veroboards, including the tracking pre-regulator (nothing special there either, just an inverted buck topology with 500V at the input side with an UC3843 in control of it).The schematic partials I think are still available in this thread. I do not see much value of posting a schematic of an unfinished circuit/product, I see more value in the thread being as a guide how to design such PSU and verify its performance.Also, currently I am toying with a completely switchmode based 200W regulated PSU of 0-350V - so I have something to employ my brain cell with, as a medicament for my otherwise very bad mood (due to other things in my life) :-/

author: 001
author_rank: Super Contributor
timestamp: February 12, 2019, 10:32:55 pm
content: Quote from: Yansi on February 11, 2019, 11:29:33 pmThank You for Your work! It is amasing projectBut can You help me with schematic of analog variant since I`m no need any microcontrollers?

author: Yansi
author_rank: Super Contributor
timestamp: February 12, 2019, 10:40:27 pm
content: Switchmode power supplies do not typically require any microcontrollers in them. (By analog I meant linear, sorry for the possible confusion).Also attaching photo of the switchmode supply I am working on to have some stress relieved.PS: Please fix the quotes in your answer