declaration of wire[0:0] producing undefined behavior. - Page 1
Forum section: electronics / general

author: Rainwater
author_rank: Regular Contributor
timestamp: July 02, 2024, 03:43:28 am
content: Im trying to create a module that will scale to a latency parameter. For all but .LATENCY('d0),the vectors will have a width greater than 1. So I declare the vectors with [MSB:LSB]. Latency zero isa valid option, so the vector declaration becomes [0:0]. This is causing some very strange issues whensimulating with IVerilog.Using the module `math_combinational` directly. "wire result" returns the correct value.but when I pass a wire vector to `math_combinational` through module math_lfmr, strange things happen.If the == operation results in FALSE0 then the `results_two` is set to false, but if the operationresults in TRUE1, then 'results_two' is set to unknown `1'bx`.the following test bench is stripped down code that will reproduce the behavior so it looks a littleweird. I think its call `indexed part select`, that I am using to select the piece of the vector I wantto operate on. But it is being defined as a scaler(size of 1) not a vector, which should generate anerror message.Its the strangest thing. I get the `1'bx' result, but why isn't it always 1'bx, and the part about pipingit through another module, to me shouldn't have an effect. anyone see what Im doing wrong?terminal outputCode:I1:01 result 0 results_two 0I1:10 result 0 results_two 0I1:11 result 0 results_two 0I1:00 result 1 results_two xI1:01 result 0 results_two 0I1:10 result 0 results_two 0I1:11 result 0 results_two 0I1:00 result 1 results_two xI1:01 result 0 results_two 0I1:10 result 0 results_two 0Code:`default_nettype none//`define CAUSE_ERROR//`define FIX_UNDEFINED_BEHAVIOR`ifndef CAUSE_ERROR`define VECTOR_DECLARATION [0:0] // creates undefined behavior`else`define VECTOR_DECLARATION`endif`ifndef FIX_UNDEFINED_BEHAVIOR`define DEFINE_PORT w_CMP_EQ_CHAIN`else`define DEFINE_PORT`endifmodule math_combinational( clk, I1, I3,cmp_eq, cmp_eq_carry_out,);input wire clk;input wire [1:0] I1;input wire [1:0] I3;genvar idx;//cmp_eqoutput wire cmp_eq;output wire `VECTOR_DECLARATION cmp_eq_carry_out;assign cmp_eq = cmp_eq_carry_out`VECTOR_DECLARATION;for( idx = 0; idx <= (1 - 1); idx = idx + 1 ) begin : CMP_EQ_base_loopassign cmp_eq_carry_out = I1[idx*2+:2] == I3[idx*2+:2];endendmodulemodule math_lfmr(input wire clk,input wire rst,input wire [1:0] I1,input wire [1:0] I3,output wire cmp_eq);wire `VECTOR_DECLARATION w_CMP_EQ_CHAIN;assign w_CMP_EQ_CHAIN`VECTOR_DECLARATION = 0; //This line is causing the undefined behavior.math_combinational ALU_LOGIC(.clk(clk),.I1(I1),.I3(I3),.cmp_eq(cmp_eq),.cmp_eq_carry_out(`DEFINE_PORT));endmodulemodule bug_report();reg clk = 0;always #1 clk <= ~clk;initial #20 $finish;reg [1:0]I1 = 1;reg [1:0]I3 = 0;wire result;wire results_two;always @(posedge clk) beginI1 <= I1 + 1'b1;$display("I1:%b result %b results_two %b", I1, result, results_two);endmath_combinational uut(.clk(clk),.I1(I1),.I3(I3),.cmp_eq(result),.cmp_eq_carry_out());math_lfmr uut_two(.clk(clk),.I1(I1),.I3(I3),.cmp_eq(results_two));endmoduleEdit: found it.Line 49ishassign w_CMP_EQ_CHAIN`VECTOR_DECLARATION = 0;im making an assignment, then passing it as an output port to another module, so its getting assigned twice.