Reading DEC Schematics circa 1970-1990 -- Bubbles - Page 1
Forum section: electronics / general

author: radiogeek381
author_rank: Regular Contributor
timestamp: April 26, 2020, 02:17:44 am
content: WARNINGThis is areallylong post. If you're interested in reading schematics from DEC, read on. Otherwise, you may find this tedious.Folks restoring minicomputers or other vintage digital systems may be lucky enough to find schematics. For systems built from SSI and MSI digital parts, this can provide an opportunity for repair, and insight that may well have become impossible with the rise of VLSI and later technologies. (It is very hard to put a scope probe down onto even the most crude VLSI designs of the 80's.)The following notes are an effort to explain how and why certain logic drawing standards came to be. I'm not saying that *YOU* should use this style. I'm not saying that anyone was a bad designer for not using this style. This is just about how schematics (particularly at Digital Equipment Corporation) were created, and how they were intended to be read.Those of us who learned logic design from the "popular" logic textbooks may find some drawing styles rather off-putting. I've heard from time to time people complain about "bubbles" and drawings that show a NOR gate as some kind of twisted AND gate, and NANDs as oddball ORs.There is a method to the apparent madness. It is rooted in a design method that was extremely successful and provided substantial improvements in productivity, debug-ability, review-ability, and general quality over the design techniques from textbooks by M. Mano and others.The technique goes by a bunch of names. Mixed-mode, mixed-level, mixed whatever logic. The central idea is this:There is a choice in how we map TRUE and FALSE to "HIGH" and "LOW" voltage, or "GOZINTA" and "GOZOUTA" current. That is, in this system, it is not correct to assume that "TRUE" is "HIGH" or that "FALSE" is "LOW."This is where at least one student in the class would give me a look that says "get outta here. Everybody knows that HIGH is TRUE and LOW is FALSE." But decoupling the values TRUE and FALSE from their representation provides a very powerful mechanism for mapping logic designs into physical devices.---------------For this discussion, I'll refer to two kinds graphical representations of a logic function. "Pointy Boats" represent OR functions, and "Dull Boats" represent AND functions.So, let's start with an example. Imagine that we want to implement a logic function that looks like this:Code:Z = S A + ~S BMany will recognize this as a two input mux.If the design is to be implemented in TTL, there is an advantage to using a 7400 -- referred to in the catalog as a "Two Input NAND" gate.The way logic design was taught in most places, we'd look at the equation for Z and notice the problematic OR in the middle. No problem, we were taught to "deMorganize" the equation on the way to mapping it into the gate types we had to work with. In this case:Code:Z = ~(~(S A) ~(~S B))And so we'd go from the function that we *wanted* (see the top of the figure called "nMUX.png" or something like that) to the network of dull boats labeled "Single Level Logic." Anybody of a certain age who looks at that drawing will know that it is a set of 74x00 gates and an inverter.But, on the way to designing that mux, the designer went through the step of deMorganizing his original expression. The intent started off simply enough with ANDs and ORs that pretty much said what we wanted to do. (The top drawing.) But the mapping to a NAND based technology forced the error prone step of pounding the bejeebers out of the original expression to get it into something else.Worse, readers of the schematic must tease out the meaning of the logic network, perhaps by un-deMorganizing the network to get back to the original intent. Yes, a trainee in his second week of work would be able to recognize a mux, but most computers were built of logic networks that were a little more complex.But, if we consciously choose the mapping of TRUE/FALSE to HIGH/LOW, we can avoid all that deMorgan work, both in synthesis and in analysis. We need, however, to be able to tell the reader what choice of mapping we've made.And now the bubbles:A wire that starts with a bubble will represent "TRUE" with a low voltage, and "FALSE" with a high voltage. If the wire starts with no bubble, TRUE is HIGH and FALSE is LOW. We call the (TRUE = low) type signal "active LOW" and the (TRUE = high) signal "active HIGH." We also indicate the mapping in the name of the signal. A signal name ending in "_L" is an active low signal. A signal name ending in "_H" is an active high signal.With that convention, we can develop a new interpretation of the "dull boat with a bubble" symbol: it is an AND function that takes active HIGH inputs and produces an active LOW output. So, a 7400 is an AND function.But, and this is the *only* role deMorgan plays here, we can also use a 7400 as an OR gate that takes two active low inputs and produces an active high output. (!) So the "Active High Inputs" representation of a mux in nMUX.png is exactly the same circuit as in the drawing above. But for many (and for those trained in the technique) it is instantly readable.Oh, but what about inverters?And this is an interesting point. If a wire is driven as "active low" and ends up at an active high input, we've got a disagreement in the representation of TRUE/FALSE. One side represents it as LOW/HIGH and the other represents it as HIGH/LOW. We've *inverted* the value of the signal. TRUE becomes FALSE and vice-versa.A wire that starts in a bubble and ends in no-bubble or vice versa, inverts the logical value on the wire.But what about the triangular boat?That is a buffer. It takes an active high input and converts it to active low. (or vice-versa). This usually bends a bit of mental metal for students. I've found it helpful to mark "inversion" wires with a little slash mark, as shown in the drawings. The slash has a bubble on it so as to distinguish it from another oft-used mark in schematics.Not all logic designs were done in TTL. Some of the other families favored "NOR" gates as the fundamental block. The last drawing in nMUX.png shows the same multiplexer implemented with 2 input NORs.-----------OK, around this point people start to say "what a waste of time, any idiot can do deMorgan conversions."Yes, but engineers tasked with producing 2, 5, 20 sheets per week found it very convenient to be free of all that scribbling and doodling on the note pad next to them. It just took too much time when time was money. And technicians and the folks in the proto lab really appreciated being able to discern the *intent* of a circuit from the drawing. And even an idiot's time costs money.As for "good engineers would recognize that mux:" yes. But what about a simple two-bit carry-lookahead "G" circuit. The equation tells us whether a two bit adder will generate a carry output, independent of its carry input. The expression is pretty simple:Code:G = A0 A1 B0 + A0 B0 B1 + A1 B1But the way most designers were taught takes them directly to deMorgan's fifth ring of hell, and produces the drawing at the top of "nCGEN.png". Hard to read, and it took a bit of scratching on the doodle pad.The drawing at the bottom of the figure, however, uses *exactly* the same parts, but is instantly readable. (Or as instantly readable as you're going to get with a four input function.)It may be easy to dismiss this as so much "a matter of taste." But it was a drawing *standard* in many computer companies beginning perhaps in the 1970's if not earlier. Further, they found that it improved productivity and product quality.----------The last figure (nMAP.png) shows the representation of AND, OR, NOT, BUFFER, and XOR logic functions and their mapping to standard 74xx series part numbers.Again, this isn't a sales pitch -- it is meant to provide a key for folks who may not understand why or how certain schematic practices came to be.