discussion on routing 4 layers - Page 1
Forum section: electronics / beginners

author: hsn93
author_rank: Regular Contributor
timestamp: December 24, 2018, 06:11:15 am
content: hello,its common that to use 2 inner layers for power planes, (top and bottom) for signal.will I'm opening this thread because (most my search results show the above sentence "or equivalent") as advice.in fact, here is one of the nice topics:https://www.eevblog.com/forum/altium/4-layer-pcb-power-plane-help/now keep in mind I'm totally not expert in RF but i always "imaging" the following points:1- signals shouldn't cross on top of each directly as they might have cross talking.so using this configuration :top = signals2nd = power3rd = powerbottom = signalsNote: i will call this (1001 config) in the post.is actually good in that matter.but, (most of PCB have less copper oz in inner layers + it need heat dissipation more as its not open to the air like out layers)so what is the draw back if someone used the following as default in his designs:top = signals2nd = power3rd = signalsbottom = powerNote: i will call this (1010 config) in the post.and that brings a question "do weJUSTwant to increase the distance between signal layers as much as we want" or just separating it by power plane will take most of emission power by that fast edge.2- in (1010) we have bottom as power which means it can have more current flow right? (+ maybe less resistance?).3- in (1010) do we have top and 3rd layer acting as shield to the signal layer between them? (good for analog sensitive signals?)4- we still have top as (signal) in (1010) so we will not a lot of vias ("vias are little inductors?"). via to 3rd is same as via to bottom (if all components are one side assembled) right? and top as power means less vias for power right? so better?5- less distance between power planes = more capicitance = good? (doesnt worth talk about it,, but is it true)?so these questions or notes are always in my mind and i always think that could it be better configuration to use (1010) as de facto rule? what are pros and cons of using either of both configurations?what do you think guys.is it good topic or so stupid by the way?

author: hsn93
author_rank: Regular Contributor
timestamp: December 24, 2018, 07:14:11 am
content: Quote from: blueskull on December 24, 2018, 06:31:36 amhello, what is Z0?Quotehmm, didn't understand how its better? does signal being sandwiched between two power planes is not good andthese two power planes will miss with that signal plane?Quotewhen you talk about sharp edges, do you mean vias? but in (1001) we have via from top to bottom so it will be same as (1010) "im considering all components in top side mounted"so jumping between layers "vias" is not good for reflection.reduce crosstalk = not having signal traces running on top of each other. (1001 or 1010) same?emi = ? which is better in your opinion? why?Quotehmm, could it be two planes that are just copper not connected to GND? acting as shield? or maybe earth ground "chassis" ?

author: Psi
author_rank: Super Contributor
timestamp: December 24, 2018, 10:50:57 am
content: I never use a dedicated power layer, always signal layers with copper pour. This way i have the option to put signals on the inner layer as needed.I start by trying to route all signals on the top and bottom layers only. Trying to keep long runs going vertical on Top layer and horizontal on Bottom layer. (This helps to prevent boxing yourself in)When doing top/bot layers i don't route VCC, i just add a VCC via when needed.I only route GND around the board edge and to components if easy to do so. Anywhere else i put a GND via.If i need to use an inner layer for a short signal run i do so. Being careful to keep the runs small.Towards the end of the design i assign one inner layer to a VCC copper pour and the other a GND copper pour.Of course, if i'm doing a BGA this gets fanned out first before starting the rest of the steps.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 24, 2018, 11:51:09 am
content: A couple things:1. Boards are manufactured in pairs of layers at a time. You want to have balanced copper areas on both sides, otherwise the laminate may warp, causing distortion of the layers, and out-of-flatness of the finished product.This also limits where you can have different thicknesses of copper -- it's very rare (most likely a custom order substrate!) to have unequal copper thicknesses on such layer pairs.You do have the freedom to choose which layers are paired together: for a 4-layer board, these are:Layer Pairs: (1 + 2) + (3 + 4)Two cores are made (1 and 2, 3 and 4). These are laminated together. The cores can be different thickness, but again should be equal. The cores must be made with equal thickness copper foil. Drilling and plating can be done at this stage to make buried vias. Then the cores are laminated together with prepreg. Finally, the board is drilled and plated. The outer layer copper thickness is usually more than inside, because of the final plating step (which also deposits copper in thru-holes).Oh, some terminology:Core: blank "copper clad" stock from the vendor. Comes in standard thicknesses (foil and laminate) and materials (FR-4, Rogers, etc..). Core down to 5 mil is pretty standard as far as I know, so don't worry about being able to make very thin, or very thick, boards.Prepreg: fiberglass that's been pre-coated (impregnated, treated) with resin. The resins, by the way, are room-temperature-stable, solid, epoxy resins (for FR-4 at least, of course). They melt and set when heated in a press.Prepreg usually has more resin than core material does, giving a higher dielectric constant, poorer dimensional tolerances, and better fill-in around etched traces. Usually used in thin layers, but can be stacked up to make thick layers, too.Foil: copper as it comes laminated on the core. Typically 0.5, 1 or 2oz, but other sizes are used.Plating: electroplated copper, added on top of existing foil or (activated) holes. (Holes that are to be plated, are drilled, then coated with an activation agent, so they will become plated as well.) Can be plated quite heavily, plugging small holes ("copper filled vias") and making some very beefy boards indeed ("heavy copper" of 20oz or more).And yeah, ounces are standard over here... meaning ounces weight per square foot, IIRC. Just substitute "1oz" with 35um (and so on) for the actual metric measurement.Anyway:With a layer-pairs build, layers 2 and 3 can be quite close together, using a thin prepreg to glue the two cores together, which is nice for power planes. Buried vias connecting between layers 2 and 3 cannot be made in this process.Internal layer pairs: 1 + (2 + 3) + 4A core is etched (and drilled and plated, if buried vias are used), then prepreg and additional foil is glued on top and bottom. The outer layers are etched, drilled and plated. This is the most common process.A typical 4-layer proto build is 1mm core, 0.25mm prepreg and a few 0.1mm's worth of copper foil totaling 1.6mm final thickness. This makes the inner layers quite close to the surface, which isn't so great for plane-to-plane coupling, but is great for signal-to-plane coupling. The best advantage is making 50 to 100 ohm traces feasible with default width/space rules (usually 7 mils), which is very suitable for the most common CMOS and LVDS type signals.More terminology: Z0 is the characteristic impedance of a trace. A trace over ground has equivalent (series) inductance and (parallel) capacitance. The ratio of these corresponds to the impedance: Z0 = sqrt(L/C).Transmission line theory is very useful. You don't have to decompose a circuit board into L and C components; instead, you design it in such a way (namely, using solid ground planes, so the outer signal layers are microstrip transmission lines) that it can be analyzed as simple transmission lines, and then you only need to know Z0, length and velocity factor to solve for interfaces at the transmitter and receiver. Z0 can be calculated from the trace width and dielectric thickness, velocity from the laminate material, and length computed from the CAD files.This applies to circuit design in, broadly speaking, oh, the 50MHz to 20GHz+ range. Note that that includes harmonics; a signal can be switching at 1Hz but still have signal quality problems when its edge rate is fractional nanoseconds! Typical transmitters and receivers respond in a few nanoseconds, making signal quality a concern even for some Arduino projects, for example.So, having considered manufacturing -- if we're making that "1010" board, maybe we hatch the planes to balance their copper densities against the signal layers (they are only paired with signal layers -- in either type of 4-layer build). And we flood the signal layers with ground fill.Now we have some other considerations. Suppose the board is relatively large, and we have some high speed signals that need to be matched impedance, high speed USB say. We could route them on the top layer, but we gain no advantage from our build -- we have two options, microstrip (top layer) and stripline (a trace surrounded by dielectric and then ground, mid-bottom layer). If we route it on the inner signal layer, we need to make sure the dielectric thicknesses are at least enough that a minimum width trace meets the required impedance.Impedance calculators are easy to find -- there's a number of good ones here:https://chemandy.com/calculators/microstrip-transmission-line-calculator-hartley27.htmNote that, unless we do blind vias (a hole is drilled partially into the board, but not all the way through, and then plated), every via we make will be from top to bottom, leaving a hole in the bottom ground plane and leaving a stub (if a short one, ~0.5mm) on our signal line. This won't matter until very fast signals indeed (10s of ps), but is a bit of a bother, and the exposed signals on the bottom side can lead to more RF leakage (emission or susceptibility) than desired.By the way, putting signals on inner layers is tempting from a signal quality standpoint (lots of shielding!), but rather inconvenient to realize, due to the fact that components still have to be mounted on the surface, sooner or later.This may've been obvious enough that you didn't list it. So, here it is for completeness.Obvious though it may be, it is sometimes done. Tektronix did this fairly often in the 80s, it seems; it makes their boards very difficult to repair, unfortunately (you can't follow a signal around its trace, it disappears into the board right away..). Where components don't need to be crammed together at maximum density, it does indeed provide shielding for the signals; it also keeps traces away from environmental contamination, except for that little bit connecting to a component. A layer of conformal coating helps more though.Tim

author: mvs
author_rank: Frequent Contributor
timestamp: December 24, 2018, 07:40:56 pm
content: Quote from: T3sl4co1l on December 24, 2018, 11:51:09 amMost pcb fabs will laminate just one core for 4 layer board...

author: hsn93
author_rank: Regular Contributor
timestamp: December 26, 2018, 10:21:16 am
content: Quotehello Tim, @t3sl4coi1, thanks very for your very helpful reply it scared me on my designs i've to care about copper distribution.this raise a question for me. but hiding 90% of the trace is good right? yes you will expose very little of the trace?just to confirm what I've understood 4 layer PCB:sometimes:core [top - dielectric - 2nd]prepreg core [3rd - dielectric - bottom]in the above case you will have 2nd and 3rd coppers close to each other. [more capacitance on internal planes]and some other manufacturer could use:foil prepregcore [2nd - dielectric - 3rd]prepregfoil in this case we will have top close to 2nd, 3rd close to bottom.. [2nd and 3rd are far].. [more capacitance on 1&2 and 3&4 than internal planes]although core has less dielectric constant but the distance is much larger right?=============================================what happen when you make (1010) and then after routing all traces you just put a solid Gnd polygon on all layers? that will make the copper distribution?here is a design im working on (1001):top2nd3rdbottom- so, what if i make (rest of 3rd layer = gnd) ..- what if i make bottom and top gnd also.. its better for routing gnd on top... (+ better for bottom as there is few traces and need to be copper equal to top?)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 26, 2018, 01:10:00 pm
content: The main reason I don't like polygons on signal layers, is it's a right pain to stitch around two layers of routing plus components. Polygons can do more harm than good if not stitched: the random resonant stubs can radiate EMI or affect signal quality (for precision applications).This low density board looks like it would be fine in 2 layers, In that case, you must pour both sides for ground, and route VCC. With single side component placement, stitching is pretty easy.Tim

author: EEVblog
author_rank: Unknown
timestamp: December 26, 2018, 02:47:49 pm
content: Quote from: blueskull on December 24, 2018, 06:31:36 amI've done that with 8GbpsQuoteDepends on what your needs are, it's possible to do the ballpark calcs and get near enough for many requirements. Risk of re-spin is always higher though.

author: EEVblog
author_rank: Unknown
timestamp: December 26, 2018, 02:52:03 pm
content: That board you showed looks nothing special signal integrity wise (nice tidy layout BTW), so any configuration will work. Just go for the normal sig/power/gnd/sig stackup.

author: xyrtek
author_rank: Regular Contributor
timestamp: December 29, 2018, 09:29:39 pm
content: Quote from: EEVblog on December 26, 2018, 02:52:03 pmBasically what Dave said, the "sig/power/gnd/sig stackup" that Dave calls normal seems to be the de facto standard.

author: hsn93
author_rank: Regular Contributor
timestamp: December 30, 2018, 07:52:34 am
content: hello, i found this useful and wanted to share few links to the post in case anyone in the future read it:Tip #10:http://www.hottconsultants.com/tips.htmlQuoteQuotei've also find these very useful:http://www.icd.com.au/articles/Copper_Ground_Pours_AN2010_4.pdfhttps://www.edaboard.com/showthread.php?194624-copper-pour-on-signal-layers(so when use ground in all layers = must stitch planes = for this design it doesnt matter anyway.)thank you all, i know its not high speed design circuit and it doesn't matter a lot for this circuit I've shown, but i know sooner or later i will have to understand all of this because i need to design in noisy environment and i feel its good to investigate this area from now.Quotethank you dave