Interleaved ADC randomization without one extra ADC? - Page 1
Forum section: electronics / projects

author: fonograph
author_rank: Frequent Contributor
timestamp: August 05, 2018, 07:39:46 pm
content: I read this paper by Analog Devices about interleaving ADCs and it mentions technique that turns the spurious tones resulting from imperfect time and gain matching of individual ADCs into noise by using one more ADC than necessary and then randomizing the order they are switched between.What is very interesting and almost unbelievable,and also point of this question is that later in the paper they briefly mention some uber patented invention that allows for the randomization without using one extra ADC.Is that for real? I am no Einstein but that seems to me to be impossible.I mean if you have two interleaved ADCs,you cant just randomly every once in while use one ADC two times in row,that would break the entire point of interleaving,or not?My common sense tell me you must have atleast 3 ADCs if you want to do interleaving and randomization at same time. Does anybody know how that technique works?

author: JS
author_rank: Frequent Contributor
timestamp: August 05, 2018, 11:00:54 pm
content: Could be random sampling times, it does help to avoid some effects seen in with a fixed frequency, it all depends on what you are trying to archive.If it's patented you could look for it...JS

author: fonograph
author_rank: Frequent Contributor
timestamp: August 06, 2018, 06:19:24 am
content: JS I think you misunderstood me,ofcourse its random sampling,but how can they do it without extra ADC?

author: Siwastaja
author_rank: Super Contributor
timestamp: August 06, 2018, 07:41:33 am
content: Adding random jitter to the timing? The downside would be that you can't get the full sample rate out of the devices. But if they are only compensating for small timing errors, the adjustments to the timing would be small. You'd need to control this jitter in very small steps, something a standard synchronously clocked digital logic IO cell possibly couldn't do directly.Just guessing.

author: iMo
author_rank: Super Contributor
timestamp: August 06, 2018, 10:05:10 am
content: I think HP did this in their counters (at least in 70ties). They phase-wobbled the signal from the local OCXO with a random signal (ref clock passed via an LC with a varicap and modulation noise came from a zener diode). They did it in order to suppress various beats and other effects while measuring frequency. I forgot the exact counter type, google.PS: the dithering above in HP5345A - 10MHz_OCXO-->white_noise_dithering-->x50 to 500MHz ref clk

author: David Hess
author_rank: Super Contributor
timestamp: August 06, 2018, 02:29:24 pm
content: HP was not the only one to do that in frequency counters; Tektronix and others did it also. Adding random jitter to the frequency counter timebase prevents the errors associated with phase locking to the measured signal.What HP did however is make some digital storage oscilloscopes which randomized the sample clock on their interleaved analog to digital converters. They published some application notes about it if you can find them.

author: Hydron
author_rank: Super Contributor
timestamp: August 07, 2018, 06:55:56 am
content: If it is a patented technique, then look up the patent! That's what the patent system is in _theory_ for, sharing knowledge rather than locking it up in exchange for a period of exclusivity (shame about the crazy language they use in them, bad patents, insane levels of abuse, lawyers making billions while innovation is stifled rather than encouraged etc etc).