Buck converter MOSFET design guide - Page 1
Forum section: electronics / projects

author: tatus1969
author_rank: Super Contributor
timestamp: September 11, 2017, 09:40:55 am
content: This is by far the best article on this subject that I have come across. I have ready it completely, and I could not find a single error nor that they would have left out something important.As I am currently developing a 8V / 70A buck converter, some of the details given there have been very helpful for me.http://www.eetimes.com/document.asp?doc_id=1225701

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 11, 2017, 10:07:55 am
content: At a glance, I don't see anything outrageous.Hey, the e-mags are likely to have a good article, once in a while.Tim

author: b_force
author_rank: Super Contributor
timestamp: September 11, 2017, 02:36:27 pm
content: They missed something very important!Practical component choice and PCB design.You can have a great theoretical circuit, but in the end it all comes down in proper board design, decoupling, placement. component choices and other stuff to prevent noise, ringing or even just a circuit that's not gonna work.

author: tatus1969
author_rank: Super Contributor
timestamp: September 13, 2017, 09:48:21 am
content: Quote from: T3sl4co1l on September 11, 2017, 10:07:55 amagreeQuote from: b_force on September 11, 2017, 02:36:27 pmit's not the More Than Complete (&Unabridged) Hitchhiker's Guide to the Buck Converter. It's only about a practical approach to estimate MOSFET power dissipation sources.By the way, has anyone experience with Infineon's OptiMOS5 devices? The spice simulation shows some weird arftifacts that worry me:

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 13, 2017, 10:57:55 am
content: Are you unaccustomed to using loop inductance in your sims?That looks reasonable as a start, but overly simple.Here's a simulation and a real measurement, of an H bridge:These are gate voltages, measured against ground (5V/div top, 2V/div bottom). The squigglies are surprisingly similar. I don't remember if I had added package parasitics to the FET model, or if it's stock (with them).Tim

author: tatus1969
author_rank: Super Contributor
timestamp: September 15, 2017, 10:21:47 am
content: Quote from: T3sl4co1l on September 13, 2017, 10:57:55 amIt's like that when you don't have a layout yet. But in the meantime that has condensed, and I added the most important inducances (MOSFET package parasitics are included in the model). (HS MOSFET is changed in this simulation because Rdson losses are still low enough with these and it simplifies the gate drive circuit). The result does not differ significantly, the large negative spike at the switch node is still there. This exceeds the LTC3870 ratings for this node, and this is why I am worried.The question is specifically related to the OptiMOS5 devices, and simulating them. Infineon chose a completely different approach to create the model, there is not a single NMOS instance in the library. I have never seen undershoot at this magnitude in any of my low voltage designs, and I wonder how far I should trust the simulation results (if at all).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 15, 2017, 12:20:23 pm
content: Oh yeah, that's right, they built it from scratch with parametrics. I remember that kind of model going very very slowly in most environments...Tim