Mixed signal PCB layout help - Page 1
Forum section: electronics / projects

author: calvingloster
author_rank: Regular Contributor
timestamp: July 02, 2023, 02:01:39 am
content: Hi AllI am busy laying out a mixed signal PCB and i am stuck at deciding where to place my power rails. I am also not sure where to make the single connection between digital and analog ground because i have more than 1 analog IC's and the data sheets recommend making this connection under the thermal sink/ground of the IC. If I do that then I think the digital ground return path of the one IC (ADC) will couple with the analog signals of the DAC.Would you guys go to town on this PCB layout and possibly give me advice on what I need to change etc. to get it as best I can.

author: Marsupilami
author_rank: Frequent Contributor
timestamp: July 02, 2023, 07:23:19 pm
content: I haven't done any precision analog design ever, so take this with some reservation, but until someone smarter chimes in here's this.Is this something needing peculiar precision or do you just want to get it reasonably good?If latter, just do one or more solid ground plane, and try to make everything wide and thick to present the absolute lowest possible impedance, so the return current doesn't cause a noticeable voltage drop.The power rails can be kept reasonable separate, with any extra filtering and decoupling as close as possible to the sinks. Carefully decoupling the digital power rails is important too.Split grounds can be very tricky and you can very easily do more damage than good.

author: Benta
author_rank: Super Contributor
timestamp: July 02, 2023, 10:29:54 pm
content: I can't see anything. The "Dark Theme" fetish has gone too far.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 03, 2023, 01:14:32 am
content: Quote from: Benta on July 02, 2023, 10:29:54 pm

author: calvingloster
author_rank: Regular Contributor
timestamp: July 03, 2023, 01:19:29 am
content: Quote from: Marsupilami on July 02, 2023, 07:23:19 pmThis is for a scanning tunneling microscope. This board senses the tunneling current that has been amplified on another board and then generates precise voltages to control the tip of the microscope. The more precise I can get it the better the resolution will be so I would like to get it as best i can.Here is an attempt at separating ground planes. It hurts my eyes to look at it, its not very pretty but as far as i can tell the return currents don't interfere with each other. Maybe the guru's can see something that I cant though.

author: Marsupilami
author_rank: Frequent Contributor
timestamp: July 03, 2023, 04:33:08 am
content: Oh wow. Well, you're not lazy, that's for sure.Is this 2 layer only? Is that due to economic consideration?For example what's the return path for the ADC digital signals?

author: Hammbone
author_rank: Newbie
timestamp: July 03, 2023, 09:32:19 am
content: I think you are going to have ground bounce issues with your current layout. Ground bounce is the worst form of cross talk. Much larger than the noise you get from having digital and analog circuits share a ground plane. Ground bounce occurs whenever a trace is routed over a gap between planes. This causes the return path of the signal to be extra long increasing mutual inductance between signals. Mutual inductance is your enemy and will cause large crosstalk. If this is a two layer board I suggest making the bottom layer a solid ground plane. Do all your routing on the top layer. If you have to route a trace on the bottom layer make it as short as possible before returning to the top layer. Additionally if you are going to have ground pour on the top layer use lots of vias to stitch it to the bottom layer. Maybe one every 500 mils. Datasheet recommendations are not always best when they are taken out of context. Good luck with your pcb!

author: Doctorandus_P
author_rank: Super Contributor
timestamp: July 03, 2023, 10:24:37 am
content: To me it looks like you have not got any GND plane at all.It's just a mess of patchy floating copper area's and antenna's.You have got 5 tracks between the TC2326 and the 4809QFN. I assume this is some serial channel (SPI?) Routing for this is extemely bad. Remember that current always flows in loops, and with your layout you are forcing the return current though the GND plane to make a detour through whatever location you choose to connect those GND plane pieces.Separating analog and digital GND planes is also deprecated, for 20 to 30 years or so. In most situations a single continuous GND plane works better, especially when combined with a bit of physical separation between the analog and digital parts of the circuit. To do it properly, also consider how currents flow though the GND plane. Worst case would be putting the uC on the left, an SMPS circuit on the right and then your analog stuff in the middle. In that case the power for the uC would go right underneath the analog stuff.From your design, it's clear you do not have much PCB design experience, (and that is a place where everyone starts). I don't like altium much, but if you want to know how to handle GND planes then watch this 2 hour video from Rick Hartley:2 hours may seem excessive for "GND on a PCB", but it's not. You may even want to watch this video twice or thrice, and do some PCB design in between. Robert Feranec has also made some nice video's about GND and signal integrity in PCB design.If you find signal integrity very important, then go for a 4 layer PCB, use a single continuous GND plane, and put it on an inner layer close to the signal layer. It is even advantageous to use both inner layers as GND, and then use the outer layers for signal and power only. For the background, go watch the video's linked to above.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 03, 2023, 01:50:18 pm
content: Quote from: Marsupilami on July 03, 2023, 04:33:08 amYes this is two layer only, my Diptrace layout program is limited to two layers but I am trying to get a license for more layers as we speak.The return path of the ADC is as shown below. The ground of the input opamp runs to the second layer via vias and then underneath the ADC IC.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 03, 2023, 02:11:49 pm
content: Quote from: Doctorandus_P on July 03, 2023, 10:24:37 amThe 5 tracks between the TC2326 and the 4809QFN are SPI lines you are correct. Thanks for pointing this out, could you be as kind to elaborate a bit more? I'm looking at the loop of the SPI current and all I see is that the loop doesn't interfere with the analog side. This is what I see:Thanks for the video link I am going to watch it now.

author: Marsupilami
author_rank: Frequent Contributor
timestamp: July 03, 2023, 02:48:26 pm
content: Quote from: calvingloster on July 03, 2023, 01:50:18 pmThis is what I see for the ADC SPI shortest path. It's very hard to tell where is that loop going to couple, especially if you have similar ones that might not even be obvious.I forgot to say it in my previous post, that really cool application tho.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 03, 2023, 04:01:10 pm
content: Quote from: Marsupilami on July 03, 2023, 02:48:26 pmHaha funny picture. So how would a continues ground plane make that loop any different? If the ground plain was continues, i.e. I didn't have those ground splits in there, that loop would still exist. I am also confused as to why the digital ground would take that route because the digital ground is not connected to that ground pour? This raises another question. What difference does splitting ground planes make if analog and digital ground pins of the IC are connected internally?I have attached a closer picture of the ADC, The red line shows the digital ground pin is not connected to the analog ground pins at all. However I do realize that this doesn't matter if they are internally connectedif they are connected internally how is it possible to prevent the SPI return current from coupling with the ADC analog current then?

author: ajb
author_rank: Super Contributor
timestamp: July 03, 2023, 06:42:13 pm
content: Quote from: calvingloster on July 03, 2023, 04:01:10 pmThe answer is that you separate out the return current paths. A split/single-point-connected ground plane is kind of a shortcut way of enforcing this, but only really works on eval boards with one mixed signal IC, limited supporting circuitry, and limited external connections. In the context of a more complex design, it falls onto the designer to ensure that return currents are properly directed, regardless of how the ground plane is laid out. A big part of this is placement (in fact, good layout in general is 90% about good placement), so making sure you have a good idea of what kinds of currents will flow in/out/between each block of circuitry and place them accordingly is a good start. From there, consider the loop paths between blocks, and make sure you route accordingly, including maintaining a solid ground plane as much as possible.There are multiple loops to be concerned with here. This starts with the power supply input, which is a loop unto itself between your input capacitors (I don't see any on your board, btw) and the external power source. From there you have a loop between the bulk capacitors on the board to the local decoupling caps. Then you have the loops formed by decoupling caps with the ICs they serve, these want to be as tight as possible to provide maximum stability of the local power supply, and they are the foundation of the next set of loops, which include the signal tracks between ICs. Consider that when your MCU is clocking the SPI line to the ADC, on every clock transition the MCU delivers a pulse of current into the clock line. The energy for that pulse comes from a local decoupling cap at the MCU, delivered through the MCU's output stage into the clock line, into the ADC, and is returned through the ADC's ground pins, through the ground plane, back to the MCU decoupling capacitor. High frequency return currents will be concentrated in the path of lowest inductance. When a signal track is routed over a continuous, unbroken ground plane, the lowest inductance return path is through the ground plane directly underneath of the track. This is why a continuous ground plane is generally ideal, because return path inductance is minimized (as is the DC path resistance by virtue of there being as much copper as possible). In terms of 'high frequency', remember that with digital signals it's not the transition frequency but the transition rate (slew rate, dV/dt) that determines the highest frequency of concern. This is why you don't want to route tracks across a break in the ground plane, because it forces those return currents to detour through a higher inductance path around the break to get where they need to go. This is also what makes the old advice to only have one point of connection between analog and digital grounds tricky--in order for that to work properly, any signal that crosses the digital/analog boundary has to do so at that single point. Having a single contiguous plane is often a more realistic path to acceptable results.Even if your design would benefit from a split ground plane strategy, that would likely only come into play after you've dealt with other things that will have a much more significant effect on your precision: power supplies, input filtering (power and signal), DAC/ADC reference quality, error terms in your analog components, etc. No amount of fancy ground plane shenanigans will make up for deficiencies in those areas, but they will all benefit from a good ground plane.In any case, aside from the fundamental question of whether or not you should split your ground planes, your ground planes are far too fractured by signal tracks to really be of any benefit here. You have a number of islands, and near-islands in the ground pours as things stand now. You could probably get a reasonably contiguous plane with two layers on this design, but it will take much more careful routing and you'll still likely need to stitch top and bottom pours together with vias. In general, I suggest moving a lot of your longer tracks to the top layer, and rather than moving whole tracks to the bottom layer, use short bottom-side tracks to allow signals on the top layer to cross. The small hole created in the ground plane by a short jumper track is far less harmful than a big slot created by a longer track. Where you must have longer tracks on the bottom, avoid having top side tracks cross over them. If that can't be avoided, use a top side pour and stitch it to the bottom pour, such that the top and bottom pours add up to a more-or-less uninterrupted plane.

author: Marsupilami
author_rank: Frequent Contributor
timestamp: July 03, 2023, 09:16:55 pm
content: Quote from: calvingloster on July 03, 2023, 04:01:10 pmMY bad, I missed the separate ground pin of the ADC. I didn't mean to confuse you, but it still doesn't help the loop.ajb's comment is great.

author: nctnico
author_rank: Super Contributor
timestamp: July 03, 2023, 11:55:39 pm
content: First of all use a 4 layer board. This design ain't gonna work with only 2 layers.Make sure to have a single, solid ground plane. That has the lower impedance and thus the least cross talk.Remember current flows in a circle. So use local filtering for high-speed parts using ferrite beads + capacitors to create locate power planes. HF current can not travel beyond the ferrite bead. When interfacing ADCs / DACs to something like an FPGA or microcontroller, you can add series resistors in the signal lines. These will reduce the (HF) peak currents flowing between the devices and also through the ground plane.If the ADC has multiple inputs and a single reference input you could opt for a seperate 0V 'reference plane' the is connected to the ground plane through a 10 Ohm resistor or so. This way you get a semi differential input but using ADCs with fully differential inputs is better ofcourse.

author: ArdWar
author_rank: Frequent Contributor
timestamp: July 04, 2023, 12:37:29 am
content: Can you at least rotate your OpAmp or flip your supply traces so they aren't interdigitized like that? Those ground islands makes me anxious.

author: gnuarm
author_rank: Super Contributor
timestamp: July 04, 2023, 12:41:21 am
content: Quote from: Benta on July 02, 2023, 10:29:54 pm

author: calvingloster
author_rank: Regular Contributor
timestamp: July 04, 2023, 02:01:43 am
content: Quote from: Doctorandus_P on July 03, 2023, 10:24:37 amThis video was really eye opening. Firstly it had made me realize that the power in traces are actually carried around the trace in the dielectric of the PCB and or air. This helps me in understanding how fast signals will couple to the closest return path irrespective if they are connected or not. Proximity is king.Another thing I understand is that high frequency is not necessarily the clock speed but rather the rise time. In my mind I thought ahh i'll just drive the SPI lines in the khz range to get rid of too much digital noise but the rise time is the real killer.Then the two layer board. I now see how limiting this is in terms of allowing low inductance return path for signals. From the video I rate I will go atleast 4 layers with layers 1,2,3,4 being 1. ground, 2.signal/power, 3.signal/power, 4.ground. And wherever I need to route a signal line from 2 to 3 I will use ground VIA's as close as possible to these signals to offer the lowest inductance return path to ground. And yes I get that these principles apply to really high frequency signals but there is an alement of it in the ADC's rise times so it's worth learning these good practices now rather than later. I will also be stitching ground planes as much as I can.So time to upgrade diptrace license to get access to use more layers then back to the drawing board.

author: ArdWar
author_rank: Frequent Contributor
timestamp: July 04, 2023, 02:48:42 am
content: Quote from: calvingloster on July 04, 2023, 02:01:43 amWith 4 layer it's usually Signal-GND-GND-Signal. The idea is to have closely coupled return path available everywhere no matterwhat you're doing with the signal trace on the outer layers.For practical reason it's also usually preferrable to route signal only on the outer layer. It might sounds nice to have signals "protected" in the middle between GND, but in reality they'll crisscross with other signal instead making it barely better than 2 layer. Component pads also break ground plane continuity. Also imagine debugging or repairing boards where signal traces are internal...Note:  within reasons

author: calvingloster
author_rank: Regular Contributor
timestamp: July 04, 2023, 02:55:19 am
content: Quote from: ArdWar on July 04, 2023, 02:48:42 amThe video above suggests that it becomes really difficult to have components, signals and power on the outer layer and recommends using ground signal signal ground instead. However the video also mentions its mainly for high density boards and this is by no means a high density board so i think i may just use signal ground ground signal.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 10, 2023, 12:15:56 pm
content: OK so I got the license for more layers. I went 4 layers with Signal/Power,Ground,Ground,Signal/Power. Each ground point gets stitched to the inner ground layers with a Via. I am thinking I must do a regular grid of vias stitching the top and bottom pour to the inner ground layer? Would be great if you guys could go to town on the PCB again thanks.

author: gnuarm
author_rank: Super Contributor
timestamp: July 11, 2023, 12:17:01 am
content: Quote from: calvingloster on July 10, 2023, 12:15:56 pmI haven't reviewed all the posts, but I can't think why anyone would suggest that you use two ground layers. A solid power layer will have similar signal integrity characteristics. If you have more than one power rail, you can divide the power layer into "zones" for each power rail. In some designs, you also need separate ground areas for analog and digital grounds (joined at one point, at an edge of the ground area). So, one ground layer and one power layer.With adequate bypassing, the power planes will act the same as the ground plane, establishing the impedance of your signal traces.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 11, 2023, 10:25:10 am
content: QuoteOk well maybe you should read the whole post because what you saying about splitting ground planes causes more harm than good if not done exactly correctly and its a really outdated way of doing it. Watch that video that was recommended its really good.

author: gnuarm
author_rank: Super Contributor
timestamp: July 11, 2023, 05:27:24 pm
content: Quote from: calvingloster on July 11, 2023, 10:25:10 am"if not done exactly correctly"You seem to be making a statement, but then you completely undercut yourself by saying it will work, but only if the designer is not crap.The idea of isolating analog and digital ground planes is sound. Digital electronics can produce huge ground currents, such as the impulses from a switching power converter. No matter how well you design that circuit, it will have very large ground currents that will create ground noise, disrupting sensitive analog circuits. So, the two need separate ground areas, connected at a single point. Any digital signals that cross between the two areas, should do so as close to the point of connection as possible.I've used this approach in any number of designs, and it works.

author: ajb
author_rank: Super Contributor
timestamp: July 11, 2023, 10:50:22 pm
content: Quote from: gnuarm on July 11, 2023, 05:27:24 pmAs previously mentioned in the thread you admitted you didn't read, and covered extensively in the very good video Doctorandus_P shared.... High frequency return currents (above audio frequencies) are concentrated in the path of least inductance. With a track over a solid ground plane, the return currents take the same path as the track except through the ground plane, because that's the path that encloses the smallest loop area. At best, splitting the ground plane is not effective for controlling high frequency return currents, because with a solid plane they already take the optimal (least impedance) path available. At worst, splitting the ground plane can cause serious problem with EMI, SI, and basic function by forcing HF return currents to flow around--or even couple across--the gap in the plane, increasing inductance, and spreading fields out further across the board and beyond where they can impact more signals. As you note, signals should be routed across the junction point to avoid this, but that also forces the signal and its return current closer to the sensitive ADC/DAC--or you have to make that junction area larger, stretching the definition of "single point", to preserve signal separation without tracks spanning the split. So, bottom line, split planes can work, but they're not going to be better than a single solid plane for high frequencies, and will cause more harm than good if not done exactly correctly.Splits/Slots can be effective at controlling lower frequency return currents (in the audio range down to DC), but that's only relevant if you have enough current in those lower frequency ranges to cause meaningful voltages across the DCR of the return path. "Meaningful" of course depends on the sensitivity of the circuitry involved as well as the magnitude of the currents concerned.

author: gnuarm
author_rank: Super Contributor
timestamp: July 11, 2023, 11:12:22 pm
content: Quote from: ajb on July 11, 2023, 10:50:22 pmI don't know why you have ignored what I wrote. Ground planes must be connected. The signals can be routed over the point of connection between the two areas, to allow the return currents to follow the same path as the traces. This is easy to do properly. Just route the "high speed signals" along the path the return currents will follow. It is seldom required to minimize the length of traces crossing from one area to another. The signals just have to cross between the planes at the point of connection.What the split plane is better at, is limiting the impact of high current, RF spikes, that are created by one circuit, from crossing the split, and impacting another circuit. A perfect example are the large transients generated by a switching power supply. By giving this section of the design a separate area of ground plane, the current spikes are limited to that area, preventing the currents from flowing over the other parts of the ground plane, where the IR drops can cause excessive noise.If there is a section of analog circuitry that can be disrupted by digital noise, the semi-isolated area prevents noise from entering. Think of it as an iso-potential ground area.If you don't believe this, consult any good reference on designing such switching power circuits, such as an LT (now Analog Devices) data sheet. They offer very useful design guidance and theory of operation information.You are only talking about the propagation of high speed signalsacrossa split in the power plane. This is not what I am proposing.If you don't understand what I am describing, say so, and we can stop discussing it now.

author: ajb
author_rank: Super Contributor
timestamp: July 12, 2023, 04:47:57 am
content: Quote from: gnuarm on July 11, 2023, 11:12:22 pmBut split planesaren'tgood at that. Say you've got a board with a single point connection between analog and digital sections. We both agree you wouldn't route any high edge rate signals across the split (and if you DON'T have any signals that need to cross that boundary, then you don't have any intrusive return currents to worry about anyway, thus no need to discuss a split), so all of those signals that cross the boundary now have to bunch up into that one crossing point. That means all of the return currents also cross at that point instead of crashing into the split, great. Except if all the signals are routed across that one point we don't NEED the split, because the high frequency return currents are simply following the least inductance path through the ground plane directly under their corresponding signal tracks. So just get rid of the split, and now you can spread those tracks out and away from the sensitive stuff, and their high frequency return currents go away with them. Splits or slots may be useful in managing the paths of lower frequency return currents down to DC, but in either case lateral separation of potential interferers from their potential interferees--and good placement to keep those signals and power paths in separate areas in the first place--is more effective. When sufficiently good placement isn't an option is when splits and slots are useful.

author: nigelwright7557
author_rank: Frequent Contributor
timestamp: July 12, 2023, 08:04:17 am
content: My star ground is usually at the power connector to the pcb.Or the main smoothing negative terminal.Mixed signal is fun, I once designed a USB scope and when I tested it it had 10KHz square all over the signal !I had run analogue signal beneath a TC7660 inverter IC which runs at 10KHz.I had also run analogue signal through crystal oscillator and got 8MHz all over the signal.I designed a USB audio mixer.With inputs shorted I got 1VAC on output !I hadn't star grounded it and charging impulses into smoothing cap was modulating the ground line.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 12, 2023, 08:16:47 am
content: Quote from: gnuarm on July 11, 2023, 11:12:22 pmYou got this exactly the wrong way. HF return currents closely follow the trace anyway, so splitplacement(of components and traces) is enough; adding a ground split does not add anything. On the other hand, DC and low frequency currents spread in ratios of resistivity so quite far away from the trace. Ground splits are useful and used whenever low-frequency analog accuracy is important, because DC/LF ground shifts in tens-hundreds of uV are hard to avoid by placement alone. For digital signal integrity, such small shifts do not affect the slightest, and they also are not relevant for EMI because not only the amplitude is small, frequency is too.Switching power supplies are a perfect example ofnotusing ground splits; you never see them, because adding one is likely to cause a fail in EMC qualification, prompting for a redesign.

author: gnuarm
author_rank: Super Contributor
timestamp: July 12, 2023, 08:43:39 am
content: Quote from: ajb on July 12, 2023, 04:47:57 amI reject your premise that the split is required by the presence of high speed signals crossing the split. The split serves to prevent the current from various sources, crossing the ground plane around the sensitive circuitry and creating voltage gradients within. This can be digital circuits disrupting analog circuits, or as I've said, switching power supplies creating ground currents. Try as you might, you will never restrict the impact of switching power supply noise by good layout of the power supply. That certainly helps, but only reduces, not eliminates.QuoteBut you insist on limiting your thinking to high speed signals running between the two areas. That's not the entire design.QuoteWhen you accept that there is more on a board than the high speed signals running from the aggressor to the sensitive circuits, maybe we will understand one another.

author: gnuarm
author_rank: Super Contributor
timestamp: July 12, 2023, 08:50:08 am
content: Quote from: Siwastaja on July 12, 2023, 08:16:47 amYou can't seem to understand the difference between signal integrity of high speed signals, and the prevention of noise in a sensitive circuit. Not the same thing at all. There doesn't need to be any high speed signals running into the sensitive circuit to introduce noise.QuoteIf you design a switching power supply circuit next to a sensitive circuit, itwillinject significant noise into the sensitive circuit. Isolating the ground plane of the sensitive circuit, with a single connection at a point away from the noise source, will minimize the impact of the noise.Please explain the EMC failure. I expect you are picturing something different from what I am.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 17, 2023, 11:05:22 am
content: Ok so I've decided on the 4 layer board. Would anyone please be so kind to explain why I should not shouldn't pour ground on the empty space on the top and bottom signal layer?

author: Siwastaja
author_rank: Super Contributor
timestamp: July 17, 2023, 11:21:37 am
content: Quote from: calvingloster on July 17, 2023, 11:05:22 amLaziness is a good enough reason. If you do pour, you have to carefully via stitch to avoid leaving long unconnected antennas, which is quite some work and in worst case you need to move stuff around in other layers to accommodate space for these vias. Then there will be those narrow spikes between traces where you can't fit vias, so better remove them. Adjusting pour settings carefully, the PCB software does most of this job but you usually need some manual fine tuning (e.g., adding some pour cutout areas here and there).When done properly, these fills of course do no harm, but improvements are not that big so I understand the reasoning not to do it. I tend to fill.

author: gnuarm
author_rank: Super Contributor
timestamp: July 17, 2023, 09:34:01 pm
content: Quote from: calvingloster on July 17, 2023, 11:05:22 amAdding ground plane on the signal layers will only be useful in creating capacitance to power layers. Do you have power layer(s)? What is on the two layers in the middle?

author: calvingloster
author_rank: Regular Contributor
timestamp: July 18, 2023, 02:46:41 am
content: Adding ground plane on the signal layers will only be useful in creating capacitance to power layers. Do you have power layer(s)? What is on the two layers in the middle?I used the bottom layer as a power layer however the power is routed with traces because there is so many different voltages, -3v, +3v, -15v, +15v, +5v. The two layers in the middle is ground

author: calvingloster
author_rank: Regular Contributor
timestamp: July 18, 2023, 02:47:29 am
content: I used the bottom layer as a power layer however the power is routed with traces because there is so many different voltages, -3v, +3v, -15v, +15v, +5v. The two layers in the middle is ground

author: gnuarm
author_rank: Super Contributor
timestamp: July 18, 2023, 04:44:15 am
content: Quote from: calvingloster on July 18, 2023, 02:46:41 amYeah, I already explained to you this is not good. There's virtually no reason to have two ground planes. One should be ground and the other should be power. The power plane(s) should have significant overlap with the ground plane so as to create capacitance with very low inductance and resistance. This is the most important part of your Power Delivery System (PDS). Adding capacitors is useful at a range of frequencies, but poops out at the high end as the series inductance of the capacitor itself dominates. Add the power plane and you have added a very high frequency cap that covers the entire high end.A board I designed 14 years ago, and redesigning now, has +3.3V digital, +3.3V analog, +5V, +12V, -12V. Each of them have an area of the power plane. This board is less than 1 inch wide and 4.5 inches long. Yet I found placements to make this work. Running traces for power is a terrible way to distribute power with adequate decoupling. Using two planes for ground is simply wasteful unless absolutely essential for impedance control. Do you have impedance controlled traces?

author: calvingloster
author_rank: Regular Contributor
timestamp: July 18, 2023, 11:00:46 pm
content: No I don't have any traces that need impedence controlled. So if I use 4 layers what stackup do you recommend? Signal, ground, power, signal? If I use this then the signal layer at the bottom is not close to a ground plain. Doesn't matter what I do there will always be a compromise in the layout. I can't have everything.

author: gnuarm
author_rank: Super Contributor
timestamp: July 18, 2023, 11:42:11 pm
content: Quote from: calvingloster on July 18, 2023, 11:00:46 pmAs I've said before, the power planes are closely coupled to the ground plane... at least they should be if you want a low noise PDS. So the signals couple to the power planes just like they do to the ground plane. You don't need to worry about the breaks between the power planes, because of the close coupling to the ground plane, they act as one plane at high frequencies.Yes, S1, P, G, S2 is what I recommend.What edge rates do your signals have? What is in your design that might generate high frequency noise?

author: calvingloster
author_rank: Regular Contributor
timestamp: July 19, 2023, 12:56:54 am
content: The ADC I am using (LTC2326) has a fast edge rate, looking through the datasheet I don't see any specs for the rise time but it capable of up to 100mhz SPI speeds. Other than that I have a microcontroller which is the atmega4809 and a DAC driven by the microcontroller. So fast signals might be SDO lines coming from the ADC and the clock lines for the ADC and DAC.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 19, 2023, 12:59:18 am
content: I've attached a picture showing the clock and ado lines from the micro to the ADC. And the micro to the DAC which is routed on the bottom layer.

author: gnuarm
author_rank: Super Contributor
timestamp: July 19, 2023, 04:04:26 am
content: Quote from: calvingloster on July 19, 2023, 12:56:54 amIf you are running a 100 MHz clock (I'm not sure what mhz means), you will probably want to control the impedance and add termination. In SPI, each signal is one way, which means you can use the simplistic termination at the source. A series resistor to match the output impedance to the line impedance will provide an initial pulse edge of 1/2 the full scale amplitude. On reaching the high impedance input, the reflection will be positive, bringing the amplitude to full scale and that wave will bounce back to the transmitter.Why do you have parts so spread out? The closer together they are, the less impact any reflections will have. I get the impression you have little experience in high speed logic board design. Do you know how to control the impedance of the traces?

author: Siwastaja
author_rank: Super Contributor
timestamp: July 19, 2023, 06:17:02 am
content: 100MHz SPI is indeed quite tricky. Make sure your master/slave chips can handle it, then route the traces somewhat impedance controlled (no need to pay PCB manufacturer premium for this, but use an online calculator for rough approximation, important parameters are trace width and distance to the ground plane (prepreg thickness)). Then approximate the driving CMOS Rds_on, something like 20-30 ohms, and add explicit series R right at the output pin (MOSI, SCK, nCS at master, MISO at slave) to match the transmission line impedance, e.g. for a 70-ohm line a 33-47R would be right. You might need to test on prototypes because the driver R is an unknown parameter (and it will vary with temperature, sadly).Another option to avoid having to terminate would be minimization of distance, place the SPI devices very close together, like an inch or so.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 19, 2023, 09:37:18 am
content: I don't intend to run the clock at that speed I'll most likely do 1 to 2 MHZ. Yes I don't have any high speed design experience at all hence why I'm asking you guys for your input.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 19, 2023, 12:04:55 pm
content: I spaced everything out so much because I initially used a 2 layer board. Now it's 4 layer, so do you recommend I move everything closer even though I'm not running the SPI at 100MHz? I figured the spacing would keep the analog side well away from the digital side.

author: gnuarm
author_rank: Super Contributor
timestamp: July 19, 2023, 03:33:30 pm
content: Quote from: calvingloster on July 19, 2023, 12:04:55 pmWhat's important in signal integrity is edge rate, not the clock rate. By edge rate, I mean the rising/falling time of the clock edge. The other signals are not so important, since they will have setup and hold times that allow them to settle.So, series terminate your clock lines or just keep your clock line path length short and you should be ok. The clock itself must be clean, to prevent multiple edges being generated from the reflections. If the rising/falling edge of other signals is even as short as 1 ns, but the path length is only a few inches, it will have settled out by the time the clock edge comes along. It doesn't matter if the other signals have multiple edges, since they are not edge sensitive.SPI is programmable as to which edge the clock is active on. Make sure the data is changing on the other edge.

author: calvingloster
author_rank: Regular Contributor
timestamp: July 20, 2023, 03:04:03 am
content: Quote from: gnuarm on July 19, 2023, 03:33:30 pmOk cool thanks. How will these edge rates affect the analog signals?The ADC will sample a voltage of around 100mV without any SPI comms taking place, and once it has sampled the voltage, the micro can get the info so I am not too concerned with the digital interference here however the DAC will need to maintain a very stable output voltage constantly during this process happening multiple times, so I guess I am concerned with how the Digital side will affect the DACs output voltage?

author: gnuarm
author_rank: Super Contributor
timestamp: July 20, 2023, 03:14:29 am
content: Quote from: calvingloster on July 20, 2023, 03:04:03 amIt should be no problem because you are going to keep them miles apart.I have learned to use a separate ground plane area for analog from the digital, with the tie point under the ADC. This will prevent the digital noise from affecting the analog signals.QuoteI don't remember much about your design, largely because I don't see where you have shared any useful images. A schematic is essential.I assume you have connectors that go off the board for the analog?

author: calvingloster
author_rank: Regular Contributor
timestamp: July 20, 2023, 05:11:31 am
content: Ya sorry I don't have the schematics on me at the moment. The DAC's output voltages are buffered by summing and subtracting OPAMPS at unity gain to output connectors. Wires that control a piezo actuator then get connected to this output with wires. The input signal is also connected to the PCB via wires. I have drawn a diagram to helpfully explain.

author: gnuarm
author_rank: Super Contributor
timestamp: July 20, 2023, 05:23:45 am
content: Differential input for the ADC is good. That helps a lot with ground noise, what is called common mode. You still need a good ground between the board and the amp. I assume the piezo outputs have good grounds as well. I assume the frequency to the piezo is not so high? Is this audio?

author: calvingloster
author_rank: Regular Contributor
timestamp: July 20, 2023, 05:34:01 am
content: Yes one of the output (red wires) to the piezo actuator is ground and I have not shown the power and ground connection to the amplifier PCB but those are connected with wires as well. This is for a scanning tunneling microscope. Very similar to the design herehttps://dberard.com/home-built-stm/. The frequency the piezo actuator is low, a few hundreds of Hz if I'm lucky enough to get that.

author: temperance
author_rank: Super Contributor
timestamp: July 20, 2023, 02:54:49 pm
content: QuoteOr just use series termination with resistors at the driver side of things. Anything between 22...56R will do.

author: jkostb
author_rank: Regular Contributor
timestamp: July 20, 2023, 07:33:03 pm
content: Be very careful with split analog and digital ground planes. Usually it creates more issues (EMC emission violation). Usually you can solve this also by proper component placement and using 1 ground plane and careful trace routing. You should be very suspicious if datasheet or application notes recommends split ground planes. I made several designs where I ignored the recommendation of the datasheet/application note to use split planes. Never had noise issues or EMI issues. I have however seen designs failing EMI testing because they used split planes.

author: uer166
author_rank: Super Contributor
timestamp: July 20, 2023, 07:36:37 pm
content: Just say no to split GND planes. Separate the analog/digital stuff (but keep it on the same plane). The advice for plane separation has been propagated from old and outdated mis-understandings of how noise actually couples between circuits.There are a few applications where split GND planes do help as was mentioned (low frequency, high current next to low-level measurements), but in 99% of cases you're simply creating an EMC issue out of nothing via dipole radiation, and not actually improving noise coupling whatsoever.

author: gnuarm
author_rank: Super Contributor
timestamp: July 20, 2023, 08:57:36 pm
content: Quote from: jkostb on July 20, 2023, 07:33:03 pmSure, you can screw up any design. Your anecdotal accounts are not evidence of the appropriateness of splitting ground planes.I don't know the current level of the piezo drives, but that is the sort of thing that using a split ground plane will work to reduce if not eliminate.

author: uer166
author_rank: Super Contributor
timestamp: July 21, 2023, 10:25:18 am
content: gnuarm, you've been given many references (see above linked data by Rick Hartley and others). Other people have also explained the exact reasons and background regarding plane splitting that you seem to ignore.The concepts are far from anecdotal, and can be simulated, measured, and tested..

author: Siwastaja
author_rank: Super Contributor
timestamp: July 21, 2023, 10:37:07 am
content: Quote from: uer166 on July 21, 2023, 10:25:18 amgnuarm is seemingly stuck with some concepts popular in appnotes and even among many EMC gurus in 1990's/early 2000's.In reality, GND plane splits are really only useful for high accuracy DC-to-low-frequency circuits, and power planes do not magically offer zero inductance and full plane capacitance at device pin. All modern day EMC experts I have talked with recommend avoiding split planes (and instead think about splitplacement), and also emphasize the importance of local bypass capacitors at device pins, in which case a power plane offers nothing more compared to a wide power track. You still have to come from the plane through via, through thermal relief, to the pin, which adds almost as much inductance as a 0402 capacitor footprint.

author: gnuarm
author_rank: Super Contributor
timestamp: July 21, 2023, 04:57:47 pm
content: Quote from: uer166 on July 21, 2023, 10:25:18 amAnd I have given details of why these approaches work. I can't give you a reference, unless you want to buy one of his books or take the course like I did.https://www.google.com/search?client=firefox-b-1-d&q=lee+ritchey+booksEverything Lee Ritchey taught, was analyzed in theory, simulation and tested on a physical circuit. One of the more surprising results was the debunking of the idea that the "loop impedance" of a capacitor between the ground/power planes makes a difference to the effect on the chips. This is a myth that persists because, "it sounds right". However, the power/ground planes form a transmission line, supplying current until the wave reaches the capacitor. The "loop impedance" is meaningless in this context, because of the distributed capacitance.People often apply the wrong theory.

author: jkostb
author_rank: Regular Contributor
timestamp: July 21, 2023, 04:58:52 pm
content: I have done my home work and studied books, notes, application notes from authors like Henry Ott, Kenneth Wyatt, Eric bogatin an many more authors. They all say the same: don't use split reference planes. This matches with my experience. My anecdotec stories are based on experience in past and based on literature from welknown experts in the field.

author: gnuarm
author_rank: Super Contributor
timestamp: July 21, 2023, 05:05:09 pm
content: Quote from: Siwastaja on July 21, 2023, 10:37:07 amYes, many people continue to teach the "local" bypass capacitor theory, which has been solidly debunked. Well, unless by "local" you mean within an inch or two.The idea that the high frequency capacitance of power/ground planes is of no value compared to traces for power is only valid when your circuit is not sensitive to high frequencies. It is very common for circuits to be over designed in this regard. The idea of "one capacitor for each power pin" was from the days when power/ground planes were not used and persisted in designs where power/ground planes are used. Now we know better. Well, some of us.I assume you've looked at the impedance curve for caps, no? At higher frequencies the inductance takes over and the impedance rises, making the cap pointless for decoupling. This is where you need ground/power planes. If your chips do not have high current spikes on the power rails, this will not be important. But most people have no idea how to even verify this.

author: gnuarm
author_rank: Super Contributor
timestamp: July 21, 2023, 05:06:39 pm
content: Quote from: Siwastaja on July 21, 2023, 10:37:07 amI like that you continue to talk about split planes only being useful in the exact situation the OP is seeing.

author: gnuarm
author_rank: Super Contributor
timestamp: July 21, 2023, 05:07:23 pm
content: Quote from: jkostb on July 21, 2023, 04:58:52 pmWhat are your anecdotes on when split planes did not work?

author: jkostb
author_rank: Regular Contributor
timestamp: July 21, 2023, 05:20:33 pm
content: Hello Gnuarm,Regarding your statement:>I don't know the current level of the piezo drives, but that is the sort of thing that using a split ground plane will work to reduce if >not eliminateIt is not OK to give such advice to other engineers without having seen schematics, PCB layout or having detailed knowledge of the project. The big problem with split ground planes is that there is no return path for signals if they cross the split ground plane. Preferred return path is always the reference plane (e.g. ground plane), because this is the path of minimum inductance. If you split the ground plane, then return current must find other path. The result is a large loop antenna which radiates. This is the reason why I have seen so many projects fail radiated emission tests during EMC tests. If you use split planes, it is very difficult to prevent routing signals over split planes. So be very careful with giving other engineers wrong advice

author: gnuarm
author_rank: Super Contributor
timestamp: July 21, 2023, 05:49:50 pm
content: Quote from: jkostb on July 21, 2023, 05:20:33 pmIf you split off the ground plane of a sensitive analog circuit, with a connection to the digital ground plane at a specific point that will minimize the impact of digital ground noise to the sensitive analog circuit, where would the digital traces be running that they cross this split, other than at the point of connection???You are making your own demons to fight off.Doctor, doctor, it hurts when I do that! Then don't do that!

author: jkostb
author_rank: Regular Contributor
timestamp: July 21, 2023, 06:24:36 pm
content: > If you split off the ground plane of a sensitive analog circuit, with a connection to the digital ground plane at a specific point that willSo you agree that you need some connection? But this is not a split ground plane right? A split ground plane has no interconnection right?It is good to see that you start making progress learning this topic. Now you need to learn that in many designs where you have multiple analog to digital converters it is usually not practical during PCB layout to make 1 small connection between analog and digital plan and route all signals over this small connection. So you start increasing the small interconnection, but then what is the difference with using continuous plane? Your theory is outdated, and it looks like you have done a lot of "theoretical" studies without any practical experience regarding this topic.

author: gnuarm
author_rank: Super Contributor
timestamp: July 21, 2023, 06:32:17 pm
content: Quote from: jkostb on July 21, 2023, 06:24:36 pmI'm not going to banter back and forth forever. Please read my posts. I have always been talking about ground planes, split everywhere but for one point, where they are connected in a way, that prevents digital ground currents from entering the analog circuitry and disrupting sensitive circuitry.What high speed digital signals will you be routing to the analog circuit??? You seem to want to create problems, rather than designing a simple circuit.Read my posts.It's all there. If you contort what I write, you will never understand.

author: Siwastaja
author_rank: Super Contributor
timestamp: July 21, 2023, 06:46:59 pm
content: Quote from: gnuarm on July 21, 2023, 05:05:09 pmCloser than that - millimeters, really, if at all possible. That's how I can see basically all existing circuit boards designed, local bypassing of all power pins that matter.QuoteInductance is no magic, power planes are no magic, and capacitors are no magic. Parasitic inductance is simply caused by distance. Capacitors are just "power planes" tightly coupled in a small package with very high dielectric constant and minimized distance between the planes for maximum capacitance - and minimum inductance. If a capacitor is placed 2mm away from the device pin it is bypassing, it does no worse than power plane 2mm away from the device pin. You can build a small-value but physically large distributed capacitor from power/gnd planes, but the capacitance will be small, whereas local bypassing with largest value of C in smallest possible package - something like 1uF in 0402 - does the same, plus the impedance curve extends to LF way better.You can calculate low Z for a power/gnd plane pair modelled as a transmission line until cows come home, but you can't connect that inches wide transmission line into a device pin, so it does not matter. The connection to device pin (plus the via to the plane) is the bottleneck, and as a result, power plane gives very little of that low-ESL capacitance, just some picofarads. More capacitance is further away, after more inductance.Power planes do no harm in itself, but if they give you false sense of security of not requiring proper bypass caps, then theydohurt. Also if they increase your layer count, then they hurt in your pockets.

author: gnuarm
author_rank: Super Contributor
timestamp: July 21, 2023, 08:14:05 pm
content: Quote from: Siwastaja on July 21, 2023, 06:46:59 pmOh, yes! This is a superstition that is very hard to break. I do it myself! It doesn't prove anything. I carry an amulet to prevent attacks by rampaging elephants. Works a charm!QuoteClearly, you don't understand anything I've said. The problem is that at frequencies above the SRF, the impedance across a capacitor rises until it is no longer useful for bypassing... at all! The capacitance of the power/ground planes is small, but is effective all the way into the GHz region. So when your bypass caps poop out, the power planes still do the job.Why does the small capacitance value of the planes not matter? Because you need much less capacitance at high frequencies. You should understand this. I don't know why you continue to argue the point. But maybe you don't understand. You say, "local bypassing with largest value of C in smallest possible package - something like 1uF in 0402 - does the same". But this is not true, which you would know if you ever looked that the impedance vs. frequency curve of the caps you use for bypassing. Have you?QuoteYou wag your tongue fiercely, but you have never actually tested your ideas. Your hand waving of connecting the power plane to the pin being a bottle neck is not based on any technical analysis. You clearly fail to understand the nature of a transmission line. You are doing the same faulty sort of thinking that makes people talk about the loop impedance of a cap connected to a chip via the ground/power planes.As I've said, these are not my ideas. This is from Lee Ritchey, who analyzed this in theory (correct theory), simulated it in a 3d field solver and tested it by building a board. He connected the cap next to the pin, and at several distances from the pin. There was virtually no difference in the voltage waveform at the pin, until the cap was something like 4 or 6 inches from the pin. A very clear and simple demonstration.If you want to argue about this, perhaps you should take it up with Lee Ritchey. He is one of the very few "experts" who actually build circuits to verify his thinking. It took me a while to get my head wrapped around what he was saying in his class. Once I did, it all made sense. People tend to get some wrong perspective on problems like this, and let it take them in all directions.

author: uer166
author_rank: Super Contributor
timestamp: July 21, 2023, 08:40:50 pm
content: Quote from: gnuarm on July 21, 2023, 04:57:47 pmHere is what Lee Ritchey has to say about splitting ground planes:"Sometimes there is confusion as to the need for a separate analog ground and digital ground when a mixed technologypart, such as an A/D converter or read channel, is being used. This is not necessary, nor is it advisable. Once the reasonfor having two different terminals is understood, it can be seen that two different grounds are not needed."Not only are you using appeal to authority to push a mis-understood concept, but the authority itself disagrees with you.

author: gnuarm
author_rank: Super Contributor
timestamp: July 21, 2023, 10:48:38 pm
content: Quote from: uer166 on July 21, 2023, 08:40:50 pmAgain, you misunderstand what is being said. Lee is clearly talking about having distinct ground planes. I've never said that was a good idea.By explaining this again, I'm just repeating myself. If you want clarification, please read my prior posts, with an open mind, but most important, paying attention to what I say, not what you think I'm saying. There is a big difference, which your post makes clear, you don't understand.OK? Can you do that?Read what I wrote, not what you read!

author: jkostb
author_rank: Regular Contributor
timestamp: July 22, 2023, 11:13:39 am
content: You keep referencing Lee Ritchie. I have read literature from Lee Ritchie and also seen lectures given by him. What you are posting on this forum, is NOT what he is teaching. Your theory about decoupling and bypass capacitors is ridiculous. Yes, the interplane capacitance is important for power integrity for modern high speed processors. But that does not mean you can get rid of the bypass capacitors. There is nothing magical regarding interplane or by pass capacitors and by simple physics laws you can prove that bypass capacitors are required.It seems that you can not be convinced. That is OK. But what is not OK, is that you are teaching other engineers the wrong things. If you are so convinced about your theories, can you share some designs of high speed circuit boards which went into production ncluding layout? Can you also share EMI test results of these boards?

author: Siwastaja
author_rank: Super Contributor
timestamp: July 22, 2023, 12:14:25 pm
content: Quote from: jkostb on July 22, 2023, 11:13:39 amThe complexity of subject and pass/fail nature of qualifications make this futile. Obviously disastrously bad practices (for example: wiring GND with 10mil traces without bypass caps) get wed out, but stuff like believing in magic of power planes usually isn't bad enough to cause design to get rejected. One similar thing is paralleling of multiple different values of MLCCs. It's a really bad idea and thank god pretty much abandoned as the word gets out, but still some believe in itbecause they think they have evidenced it being helpful(while it truly isn't). Longer explanation here:https://www.eevblog.com/forum/projects/decoupling-caps-value/msg4891286/#msg4891286Similarly, if GND plane splits are made with care and correctly,addingto placement separation and notsubstitutingit, and avoiding crossing signals over the split, it might well pass the EMI, being only slightly worse, or in some specific case, actually better. But for a good rule of thumb, avoiding splits for HF and EMI, and using splits for low-frequency high-accuracy single-ended analog signals, is a good idea.

author: gnuarm
author_rank: Super Contributor
timestamp: July 22, 2023, 07:41:27 pm
content: Quote from: jkostb on July 22, 2023, 11:13:39 amWhat I am saying here, is directly from his class and book (he only had one at the time). I was very surprised by this, having heard the same religious garbage as everyone else. Lee directly attacked the idea of considering the "loop inductance" because it means nothing. The power/ground planes are not an inductive loop. They are a transmission line with distributed inductance and capacitance.Consider a 50 ohm transmission line, with a 50 ohm resistive load and a very low impedance driver. The initial wave will be at the driver voltage, with the corresponding current,at the very instant the driver output rises!There's no delay, because thetransmission linedelivers the current to/from the driver the entire time the wave is propagating.In our case, the impedance is much lower, and the load is a capacitor, which continues to supply current when the wave reaches it. So while the wave is propagating the transmission line distributed capacitance supplies the current. When the wave reaches the capacitor, that supplies the current. Notice there's no mention of distance. Current flows from the instant the driver changes voltage all through the spike.QuoteWhy do people continue to misstate what I write??? I'm tired of the BS, I'm calling you on this! Please find where I said bypass capacitors are not needed.QuoteYou know I can't share boards I have designed in my work. They are property of my customers. But I can say, not one has ever had a problem with EMI. NEVER!Before you challenge someone, perhaps you should actually read what they write?

author: lucy.sierra
author_rank: Newbie
timestamp: January 05, 2024, 05:24:23 pm
content: Just want to mention thatKen Wyattwill do an AMA so you can actually ask him his opinion.