AGM CPLDs & FPGAs? - Page 1
Forum section: electronics / general

author: ResistorsAreFutile
author_rank: Newbie
timestamp: November 25, 2024, 12:50:59 pm
content: I'm having to transition many of my designs away from Xilinx XC9500XL CPLDs as those parts are EOL, and also settle on an FPGA family for more ambitious future projects. Ideally I'd like to use the same tools for both, so Altera's Max V and Max 10 parts have been the front runners despite the cost of the Max 10 and larger Max V parts being quite a lot higher than I would like.Then I found the AGM parts, which seem to be clones of the Max II, Max V and Cyclone IV. Their prices are impressive, less than $3 for a 10K LE FPGA in a QFP-144 package and their 2K CPLDs are an order of magnitude cheaper than the Altera parts.Does anyone have any real world experience with these things?

author: up8051
author_rank: Frequent Contributor
timestamp: November 30, 2024, 10:12:37 pm
content: Did you somehow manage to download the "Supra" program?

author: JimboJack
author_rank: Regular Contributor
timestamp: November 30, 2024, 11:58:46 pm
content: I found it from different sources and not using that chinese backdoor malware app.they seem to have two websitehttp://www.agmsemi.com/has all the informationhttp://www.agm-micro.com/do a web search on these file namesSupra-2023.11.b0-84524805-win32-allSupra-2023.11.b0-84524805-win64-allagRV_Pio-1.6.6-win64agRV is their latest release superseds supra-2023 i installed both to see any difference could not find any however the supra zips contains the license file.1. from my take it can only do verilog, no VHDL support, uses YOLO I think with their GUI and scripts on top.2. agRV release complains on the install , you need to manual install platform.io with the correct paths you see it in the install windowslook for AGMPILL on search engine it point to a github with example files, which has the designs they sell on aliexpress, it does something no way to test the output it created yet.hope it helps, as always be safe use VM's

author: ResistorsAreFutile
author_rank: Newbie
timestamp: December 05, 2024, 03:57:21 pm
content: Thanks for the advice.I've got Supra installed in a VM and it recognises the attached Altera USB blaster and can read the chip ID from a Cyclone IV, so the programming part at least seems to be working. No idea what I'm doing with the Quartus project migration part of Supra yet, the 'manual' is not informative even when translated from ChineseLooks like I will be working up a break-out PCB for the AGM16K and possibly the AGRV2K as well.

author: JimboJack
author_rank: Regular Contributor
timestamp: December 06, 2024, 01:02:27 am
content: can you tell me please how it goesI want to try the AGRV2K CPLD replacement.From the datasheet pretty weak, could not see what the max clk rate or the max Mhz on the I/O pins it can do.

author: monk88
author_rank: Newbie
timestamp: December 10, 2024, 11:21:58 pm
content: Alright, Greetings everyone!I've made this account to comment on the AGM FPGAs and my experience with them so far. I am trying to find cheaper "alternatives" to Altera's devices, and AGM came right in time.I've bought two boards from Aliexpress:- AGM TCX (black) board with AG10KL144H FPGA- Etree F01 again featuring the AG10KL144H FPGA" alt="" class="bbc_img" />The Supra SW you can download from here:https://t.me/agmfpgadoc/142Anyway, I will be short as it is very late here. I managed to run several examples on the AGM TCX board, specifically targetting the NIOSII Soft CPU with some periphery. I was able to create and run an SOPC system, toggling some leds (PIO) and trying to print some text message (via JTAG-UART).Now, the NIOS CPU and its application ran fine, except that the printed message over JTAG was not visible. The problem is that JUART-Terminal application, running on the PC, would not attach/find the JTAG periphery of the FPGA. Also, because of that I guess, it is not possible to use the debug (to downlaod and debug from the NIOSII SBT Eclipse IDE) your firmware on the SOPC HW (.sof) that you may have already programmed to the FPGA. So the JTAG-UART and JTAG debugging are broken with AGM FPGAs , and not usable.I am attaching pics and an example project I had used if anyone wants to check for themsevles.https://drive.google.com/file/d/1Qft_PTqO6CI-o_n6OHdiBJCy_upovUHZ/view?usp=sharing

author: JimboJack
author_rank: Regular Contributor
timestamp: December 12, 2024, 01:08:26 am
content: ooo thkstheir domestic information and storehttp://www.tcx-micro.com/doc_26934765_5589870_0_1.htmlonline storehttps://agm-micro.taobao.com/other newshttps://blog.csdn.net/HIZYUAN/article/details/134865902

author: sigint
author_rank: Contributor
timestamp: March 23, 2025, 11:00:43 am
content: Hi everyone,i've just ordered some AGRV2K. Did someone make progress in using the AGM FPGAs? The AG32VF403 looks interesting... an RISC-V combined with an AGRV2K :-D

author: sigint
author_rank: Contributor
timestamp: March 28, 2025, 07:29:56 am
content: Hi everyone,i found this:https://archive.org/download/agm-microJust forget the native Framework, it doesn't work for me. This combination worked: Quartus 13.1 and Supra-2023.02.b0-7773ca8a-win64-allNow everything is working fine. I just have to find out, how to use the ADC/DAC from the FPGA part of this device.Greeting,SIGINT

author: gerbay
author_rank: Regular Contributor
timestamp: March 28, 2025, 08:39:32 am
content: there is an example in the sdk directory; AgRV_pio/platforms/AgRV/examples/analogincludes ADC, DAC and comparator

author: sigint
author_rank: Contributor
timestamp: March 28, 2025, 09:00:14 am
content: Yes, but it's for the native framework. It's missing the Quartus-Project file. I don't know which file i have to add to the project. When i add the alta_sim.v then my DAC gets optimized away and SUPRA won't see it. The native framework don't work for me... it always throws errors when PNR.

author: gerbay
author_rank: Regular Contributor
timestamp: March 28, 2025, 10:29:47 am
content: open project via using platformioselect in left side project tree: project task > release > custom > "prepare LOGIC"pio creates some files (also include supra project file and quartus project file)and than open quartus project file "my_board.qpf"inside the quartus, select : tools > Tcl Scripts menu,and than select af_quartus.tcl and click run button..if quartus design compiles finished than run supra and open my_board.proj file,inside the supra, select Tools > Migrate, click next button 3 times.. supra starts place and route process..and than switch vscode - pio screen,select in left side project tree: project task > release > custom > "Create Batch"it creates agm_analog_release_batch.bin file which is combined mcu binary and fpga bit stream..

author: gerbay
author_rank: Regular Contributor
timestamp: March 28, 2025, 09:37:51 pm
content: The windows batch file script I use with Quartus 24.1 is as follows. I run it in the "logic" directory.verilog, vhdl, systemverilog can be synthesizedCode:@echo offC:\altera\24.1std\quartus\bin64\quartus_sh.exe -t af_quartus.tclcd simulationren questa modelsimcd ..PATH="%~dp0";%PATH%set ALTA_HOME=af.exe -B --batch --mode QUARTUS -X "set QUARTUS_SDC true" -X "set FITTING Auto" -X "set FITTER full" -X "set EFFORT high" -X "set HOLDX default" -X "set SKEW basic"set status=%errorlevel%timeout 4exit %status%

author: sigint
author_rank: Contributor
timestamp: March 29, 2025, 08:04:26 am
content: I can't get platformio to work. :-( I'll just forget using the ADC and DAC. It's too much stress getting it working. It's not woth the efford.

author: gerbay
author_rank: Regular Contributor
timestamp: March 29, 2025, 10:17:13 am
content: Preparing the development environment is very easy. First you need to install vscode. Then you select platformio from vscode extensions and it will be installed as an extension to vscode. Then you install AgRV_pio-1.6.9-win64-release.exe. That's all. It only requires an internet connection. Then you open the "analog" folder under the "AgRV_pio\platforms\AgRV\examples" directory with "windows explorer" with the "open with vscode" command. You can also open it with "open folder" under the file menu from vscode. vscode can also be opened in restricted mode. You say trust. You select the platformio icon from the left menu, all the operations are there.

author: sigint
author_rank: Contributor
timestamp: March 29, 2025, 07:32:47 pm
content: Just got it to work... but it doesn't work anyhow. The AGM PNR Tool won't find the DAC or PLL instance, because Quartus optimizes it away. Wenn i try to implement the PLL by Megawizard Plugin the PNR won't find the PLL too. I give up...

author: gerbay
author_rank: Regular Contributor
timestamp: March 30, 2025, 02:51:39 pm
content: I wrote a small utility that decodes AGM's encoded files

author: sigint
author_rank: Contributor
timestamp: April 06, 2025, 08:08:11 am
content: Ok... im pretty sure right now, that the WebEdition from Quartus doesn't work. It cannot produce design partitions, so it will optimize away any IP from AGM.So you are stuck to the bare FPGA part without any IP like PLL,ADC,DAC,RISC-V. I don't know why the native workflow won't work.

author: gerbay
author_rank: Regular Contributor
timestamp: April 06, 2025, 08:30:14 am
content: You must use quartus standard edition. lite edition will not work either

author: godor2008
author_rank: Contributor
timestamp: April 14, 2025, 04:14:25 pm
content: I use Quartus Standard 24.1 and Supra 2025.03.b0Created simple blink project fro AGRV2KQ32, compiled in Quartus, executed "af_quartus.tcl"Then open Supra and choose Compile and Run. But it fails with error:Error: Can not find design verilog file blinker_design_name.vqm.Anybody faced it?I also tried to run "af_run.tcl" as said in Supra, but it fails in Quartus with such error:Code:source "L:/.../AGM_projects/Project_3/af_run.tcl"Error:invalid command name "alta::begin_log_cmd"Error: while executingError:"unknown_original alta::begin_log_cmd ./alta_logs/run.log ./alta_logs/run.err"Error: ("eval" body line 1)Error: invoked from withinError:"eval unknown_original $cmd $args"Error: invoked from withinError:"if {[regexp {^[0-9*?]+$} $cmd] || [regexp {^[0-9]+\.\.[0-9]+$} $cmd]} {Error:return "\[$cmd\]"Error:} elseif {[string compare "" [info command help]] !..."Error: (procedure "::unknown" line 2)Error: invoked from withinError:"alta::begin_log_cmd [file join $alta_logs ${RUN}.log] [file join $alta_logs ${RUN}.err]"Error: (file "L:/.../AGM_projects/Project_3/af_run.tcl" line 91)Error: invoked from withinError:"_source L:/..../AGM_projects/Project_3/af_run.tcl"Error: ("uplevel" body line 1)Error: invoked from withinError:"uplevel 1 $cmd "Error: (procedure "source" line 5)Error: invoked from withinError:"source "L:/.../AGM_projects/Project_3/af_run.tcl""

author: gerbay
author_rank: Regular Contributor
timestamp: April 14, 2025, 05:59:39 pm
content: old quartus comes with modelsim and after compilation it produce "simulation/modelsim/sample.vo" netlist filesupra tool look ./simlation/modelsim/ directory for place and route process input netlist file (sample.vo)..quartus 24.1 comes with questa (not modelsim) and after compilation it produce "simulation/questa/sample.voyou should change eda netlist writer output directoryright click top design hieararchy > Settings > Eda Tool Settings > Simulationon the right side there is "eda netlist writer settings" panel.. output directory sholud be changed to "simulation/modelsim"and than you can run af_quartus.tcl and than supra..

author: godor2008
author_rank: Contributor
timestamp: April 14, 2025, 06:30:31 pm
content: I changed it accordingly to your advice, but still getting error.In Quartus it compiles ok.Runningaf_quartus.tclis okRunningaf_run.tclfails with errorIf then open Supra -> Open Project_1 -> Tools -> Compile -> Run still complains on this file:Code:Error: Can not find design verilog file blinker_design_name.vqm.I suppose this file should be generated after runningaf_run.tclwhich fails?

author: godor2008
author_rank: Contributor
timestamp: April 14, 2025, 06:59:36 pm
content: I also just installed old Quartus II 13.1 and getting same error of not found file:"Error: Can not find design verilog file top.vqm."

author: gerbay
author_rank: Regular Contributor
timestamp: April 14, 2025, 07:21:13 pm
content: you should apply below procedure:Quote

author: gerbay
author_rank: Regular Contributor
timestamp: April 14, 2025, 07:29:57 pm
content: You are using "native" mode.In this case, the supra tool uses yosys for synthesis. It does not use the quartus output. Open the supra project file (.proj) with an editor and try it by changing it to the following form or follow the procedure in my previous message.Code:design=...device=...flowInline=forcemodeGroup=falsemodeQuartus=truemodeSynplicity=falsemodeNative=falseand than open project file by using supra, select Tool > Migrate menu and click next, next, next

author: godor2008
author_rank: Contributor
timestamp: April 14, 2025, 09:37:44 pm
content: Holy transistors, it's blinking! Great THANK you for helping me with all these hacks in Supra. Seems you know a lot about it. Maybe there is also way to have top module be written in VHDL? Since my project that I want to migrate is on VHDL, and learning Verilog and converting to it would be pain.Another thing that I noticed, blinking worked after I chaned ve file fromCode:LED_0 PIN_2:OUTPUTBT656_LLC_IN PIN_1:INPUTTX PIN_12:OUTPUTDEBUG_0 PIN_9:OUTPUTtoCode:LED_0 PIN_2BT656_LLC_IN PIN_1TX PIN_12DEBUG_0 PIN_9Supra Compiler was complaining like this, however I was doing all according to their manualsCode:Warn: Unrecognized pin BT656_LLC_IN or location PIN_1:INPUT.I will leave here my steps, so it can be searched for future, just in case someone faces same errors.So what I did:Supra - File - New Project - Project_2.Design name: topDevice: AGRV2KQ32ve file: blink_test.ve:Code:LED_0 PIN_2BT656_LLC_IN PIN_1TX PIN_12DEBUG_0 PIN_9Click NextOpen Project_2 in Quartus.Settings - EDA Tool Settings - SimulationChagesimulation/questatosimulation/modelsimEdittop.vfile and add statements to set high output on few pins and blinking led output:Code:module top(BT656_LLC_IN,LED_0,TX,DEBUG_0);input BT656_LLC_IN;output reg LED_0;output TX;output DEBUG_0;reg [31:0] counter;always @(posedge BT656_LLC_IN)beginif (counter == 27000000)begincounter <= 0;LED_0 <= ~LED_0;endelsebegincounter <= counter + 1;endendassign TX = 1;assign DEBUG_0 = 1;endmoduleCompile in Quartus. Then run Tools - Tcl Scripts - af_quartus.tclOpen with notepadProject_2\Project_2.projand set it to use Quartus instead of Native mode:fromDir=design=topdevice=AGRV2KQ32veFile=../blink_test.veipFiles=@Invalid()backwardCompatible=falsemodeGroup=falsemodeQuartus=truemodeSynplicity=falsemodeNative=falseflowInline=falseNow open Supra - Tools - Complie.Then Supra - Tools - Program. I use Jlink.In program from file selectProject_2\top.bin

author: gerbay
author_rank: Regular Contributor
timestamp: April 14, 2025, 09:45:03 pm
content: @godor2008,your example project is attached below; (quartus 24.1)led_top.zip(37.44 kB - downloaded 72 times.)

author: godor2008
author_rank: Contributor
timestamp: April 14, 2025, 09:50:38 pm
content: Thanks also, seems you uploaded it just right I was able to make it blink with your advices.I am curious, why there is no more need in ":INPUT" or ":OUTPUT" mapping in ve files for pure CPLD usage.And if there is any hack to have top level entity on VHDL and use only it without Verilog

author: gerbay
author_rank: Regular Contributor
timestamp: April 14, 2025, 09:56:50 pm
content: quartus uses ".qsf" file, I created project and manually add source file lines inte qsf file.my led project with systemVerilog looks like;Code:...set_global_assignment -name VERILOG_FILE pll1.vset_global_assignment -name SYSTEMVERILOG_FILE led.sv...also my canbus project with VHDL looks like;Code:...set_global_assignment -name VHDL_FILE transmitter.vhdset_global_assignment -name VHDL_FILE receiver.vhdset_global_assignment -name VHDL_FILE fifoctrl.vhdset_global_assignment -name VHDL_FILE decoder.vhdset_global_assignment -name VHDL_FILE can.vhd...also mix of them are possible..What I wrote is valid for quartus mode, not for yosys used in native mode.also you can search TOP_LEVEL_ENTITY text in qsf file and change name with your vhdl top module name.. ( !! it is case sensitive !!)..Code:...set_global_assignment -name TOP_LEVEL_ENTITY "can"...

author: godor2008
author_rank: Contributor
timestamp: April 14, 2025, 10:16:36 pm
content: Holy diodes, it worked! I deleted created by Supratop.v, addedtop.vhd, made it top and it all worked! Man, you are my hero!

author: sigint
author_rank: Contributor
timestamp: April 30, 2025, 08:14:53 pm
content: It seems that the native yosys based framewort works now. I can synthesize a DAC example and it's outputting an analog waveform.

author: godor2008
author_rank: Contributor
timestamp: June 04, 2025, 04:47:47 pm
content: Anyone knows if it's possible to use on-board Flash as EEPROM from CPLD? Right now I have separate EEPROM chip on PCB, and it would nice to be able to use intead fuilt-in flash

author: bonnom
author_rank: Newbie
timestamp: June 10, 2025, 11:47:10 pm
content: Quote from: godor2008 on June 04, 2025, 04:47:47 pmI just got an AGM and haven't tested it out yet, but you could try to access to write to the flash in the exact same you would with STM32 using the APB and AHB buses?

author: godor2008
author_rank: Contributor
timestamp: June 22, 2025, 01:41:50 pm
content: Found article and example for MCUhttps://mp.weixin.qq.com/s?__biz=Mzk0MjY2MDIwNA==&mid=2247484275&idx=1&sn=97e9f18e8693e60efef18ecc922af566&chksm=c33e8c70f4490566388d51ed69674072407f12370f542cdecad72ff17fccefb8117af0d4b3d0&scene=178&cur_album_id=3518899612192980993&search_click_id=#rdSo for usage in CPLD it will require a bit complex code to pass data trhough bus. But seems possible

author: geegor
author_rank: Newbie
timestamp: August 02, 2025, 02:16:37 am
content: Reply to SIGINT:What steps did you take to get YOSYS working, and did you manage to do it with the AG32 MCU/FPGA ones? I have been trying on 1.7.3 (and now 1.7.6) and haven't had any luck getting it working with supra and a LED example.When running the PIO build command on ubuntu I get errors about missing libmpfr4 for the RISCV64 bit toolchain which doesn't make sense to me either. <- Fixed by following this (https://msyksphinz.hatenablog.com/entry/2021/09/08/040000) guide, TLDR: you need to link the so.6 to the so.4 ($ cd /lib/x86_64-linux-gnu $ sudo ln -s libmpfr.so.6 libmpfr.so.4) at least this fixed it for me.Oh what on earth, running the setup.py script in the download deletes the platformio penv file. (Causes errors when running setup.py) <- you can fix this by modifying the setup.py file to remove where it does the remove dir command, its in a try catch block that can be fully commented out.Sorry for the rapid edits, but I'm making progress. I was able to successfully generate a .bit file from the analog example. The key is using command line yosys and af_run to run af_map and af_run respectively. af_map can be run in the yosys command line, It may have issues with duplicate modules that can be fixed by adding -overwrite to the read_verilog commands. af_run doesnt respect mode, and needs to have the conditional "QUARTUS" block removed, along with the while(1) statement above it for it to run correctly.Good luck to anyone else who wants to try this!