Mixed 100kHz/400kHz I²C slaves on one bus - Page 1
Forum section: electronics / general

author: leonerd
author_rank: Regular Contributor
timestamp: October 31, 2016, 09:58:27 pm
content: I have several devices sharing an I²C bus, including an OLED display that is 400kHz-capable, and GPIO expander (a PCF8574 connected to my button panel) that isn't, only supporting 100kHz. Will "bad things" happen if I try to send data to the display at 400kHz?For example, I could send the initial addressing byte at 100kHz so that the PCF knows to ignore it, and now presumably it will just ignore everything on the I²C line until the STOP condition anyway.

author: wraper
author_rank: Unknown
timestamp: October 31, 2016, 10:04:02 pm
content: PCF8574 supports 400 kHz, check the datasheet again.

author: newbrain
author_rank: Super Contributor
timestamp: November 01, 2016, 01:00:31 am
content: Quote from: wraper on October 31, 2016, 10:04:02 pmThe newer ones, yes, both from TI and NXP.If they are older chips (Philips, maybe others?), not so much.When they started supporting 400kHz, I frankly don't know.As for mixing I2C speeds on the same bus, I would not advise it. The slower device might get confused by the faster speed.

author: wraper
author_rank: Unknown
timestamp: November 01, 2016, 01:14:38 am
content: Quote from: newbrain on November 01, 2016, 01:00:31 amChecked datasheets, Phillips/NXP must be PCA8574 to support 400 kHz. Although newer PCF8574 from NXP might have the very same die inside and just have a different marking. There seems to be no 100 kHz only from TI.

author: leonerd
author_rank: Regular Contributor
timestamp: November 01, 2016, 11:05:20 am
content: Yeah; the difference between the NXP and the TI datasheets got me first time. Another difference between those two is that the TI sheet says their A0/A1/A2 lines have pullup resistors, whereas the NXP doesn't, and my chip seems to agree. If I don't tie high -or- low then they float randomly. So I definitely have the NXP version.

author: leonerd
author_rank: Regular Contributor
timestamp: November 01, 2016, 11:22:41 am
content: Well this is odd.A close look at my chip does reveal the TI logo, not the NXP one. It doesn't have what I can recognise as a date code, but it says in total:(TI logo) 46AN27ME4PCF8574ANI've tried talking 400kHz to it and it appears to work absolutely fine. But yet, those address lines just float without being tied in either direction.Either way - I do have everything working reliably at 400kHz as it turns out.

author: Nick Novak
author_rank: Contributor
timestamp: November 04, 2016, 06:29:35 pm
content: It's my understanding that slower devices will hold the clock low for as long as they need. So you may end up with a 100KHz bus as a result of the slower chip or that slower chip may just decide it can go 400K but I don't think you're going to break the bus.Nick

author: leonerd
author_rank: Regular Contributor
timestamp: November 04, 2016, 06:42:09 pm
content: Quote from: Nick Novak on November 04, 2016, 06:29:35 pmSometimes. Rarely. Some particularly new fancy modern chips that might be on mixed-bus systems do that. But doing that requires adding a pulldown transistor on the SCL line of the chip, whereas most cheaper chips (such as these simple GPIO expanders I'm using) won't have that. They're really readonly on SCL.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: November 04, 2016, 07:09:23 pm
content: You could always use a 4:2 rail-to-rail analog mux to split your I2C bus up into slow and fast sides. Just make sure to choose a mux with reasonable on-state resistance, there are lots of options.

author: leonerd
author_rank: Regular Contributor
timestamp: May 05, 2017, 12:06:51 pm
content: Quote from: suicidaleggroll on November 04, 2016, 07:09:23 pmWell to be honest, unless there are addressing conflicts, there's no need to isolate the 400kHz-capable slaves from the master when it's talking to the slow ones. So a simpler setup involving a couple of analog switches (e.g. the 74HCT1G66) between the master/fast bus and the slow bus should suffice.

author: AndyC_772
author_rank: Super Contributor
timestamp: May 05, 2017, 12:33:47 pm
content: If nothign else, the slower slaves will need to decode the address phase correctly in order to know they're NOT being accessed. If they see a blur, you can't be sure they won't think they recognise their own address every so often, and start ACKing when you don't want them to.So, it's another vote here for separating the buses. I suggest an analogue switch IC, or perhaps more easily, just use a couple of GPIO pins on your processor to drive the slower devices on one bus, and keep the display on its own on a second bus.