no-schematic PCB workflow? - Page 1
Forum section: electronics / general

author: djacobow
author_rank: Super Contributor
timestamp: September 18, 2018, 04:43:29 pm
content: I don't like schematics. They get messy easily, and the solutions like using lots pf ports/connectors and constantly rearranging pins and the locations of objects are a lot of work and mostly useless. I also find the structure of a multi-page schematic often at odds with how I think about the circuit. And finally, I'd just prefer to work in a text editor without a mouse as much as I can.I used to develop EDA tools for the semiconductor industry and there almost everything has moved to HDLs and netlists.For PCB work, I'm not really interested in HDL+synthesis, but working directly in a netlist format or using an HDL as if it were a netlist format (all you can do is instantiate and connect stuff) is very appealing to me.One of the nice things I can do with simple netlists is write tools to process them, elaborate them, flatten hierarchy, check for my own personal favorite ERCs, etc.So ... my questions are:- what common PCB tools can support a netlist to PCB flow?- are any of you working this way?I'm not designing huge circuits, but if I were I'd be even more strongly biased against schematics. I currently use Diptrace, which I mostly continue to like. The PCB tool does have a netlist import capability, but it's a bit clunky. If I change the netlist and reload, it zaps the layout. This is in contrast with the normal schematic-to-pcb flow where you can make a change to the schematic and only the changed bits change in the PCB tool.

author: langwadt
author_rank: Super Contributor
timestamp: September 18, 2018, 05:30:00 pm
content: I write plenty of HDL, but except for maybe the case of huge schematics with large busses it sounds like insanityKicad could do it

author: djacobow
author_rank: Super Contributor
timestamp: September 18, 2018, 05:48:27 pm
content: Quote from: langwadt on September 18, 2018, 05:30:00 pmThanks for the Kicad steer. I'll look at it.I know, this is something a lot of people would hate. But I guess to each his own. I think I'd stick with schematics for analogy things, but for digital stuff I just don't wanna. Classic example, is following a line from one block to another as it snakes around the page to see where it connects. In a netlist, you'd have a named "wire" that you can grep for. To me, that's very fast and less error prone.

author: ataradov
author_rank: Super Contributor
timestamp: September 18, 2018, 06:01:01 pm
content: I agree that for mostly digital circuits a simple net list may be better. The problem is that this breaks up fast with analog circuits. Try to describe uCurrent using a net list and see what happens.There may be a hybrid approach, but someone has to think it though.

author: langwadt
author_rank: Super Contributor
timestamp: September 18, 2018, 06:16:46 pm
content: Quote from: ataradov on September 18, 2018, 06:01:01 pmyeh I remember doing spice netlist by hand, bascailly only one way; draw on paper, name all nodes and hope youget it right

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 18, 2018, 06:33:35 pm
content: The HDL approach is interesting and there have been some initiatives. Of course there is the VHDL-AMS and Verilog-AMS, Spice for a simpler approach and a few independent projects.It's very hard to design a proper HDL that could replace a schematic editor for mixed-signal designs though.Most projects I've seen are not "proper" IMO. The first reason being that you usually need to (declare in VHDL/Verilog-AMS) and *name* ALL your nets, something that's handled automatically when using a schematic editor. Beyond a few nets, this becomes atrocious to handle. Much more so than in digital-only designs. So all in all, describing connections is what seems the hardest to design properly.OTOH, big plusses of this approach would be: 1. to be independent of any vendor and encourage sharing/interoperability, 2. to use modularity much more easily than the usually clunky hierarchical modules in most editors, 3. to allow parametric designs, including parameters that are results of computations.For readability, you could still have some kind of HDL to schematic converter (in the spirit of LaTeX for instance).

author: donotdespisethesnake
author_rank: Super Contributor
timestamp: September 18, 2018, 06:53:14 pm
content: You might be interested in Skidlhttps://forum.kicad.info/t/skidl-a-python-based-schematic-design-language/3743There's a handful of people interested in "no schematic" work flows. Unfortunately this became slightly inconvenient in kiCad because of the integration of footprint assignment with the schematic editor, it's no longer possible to run "cvpcb" standalone to allocate footprints, it must be done via the schematic. You need some other method to insert footprint assignments into the net list.

author: djacobow
author_rank: Super Contributor
timestamp: September 18, 2018, 08:39:19 pm
content: Quote from: langwadt on September 18, 2018, 06:16:46 pmActually, I still do it that way. Usually when I'm doing something in SPICE I am only managing part of a larger circuit, and so the complexity isn't too bad. And I'd rather just type a few lines than deal with the GUI in ltspice or whatever.A small advantage of doing the netlist + command line approach is that it becomes easier to script to run a shmoo of multiple operating conditions, or minor circuit variations, etc. Of course, dealing with the output can become challenging.

author: djacobow
author_rank: Super Contributor
timestamp: September 18, 2018, 08:46:39 pm
content: Quote from: SiliconWizard on September 18, 2018, 06:33:35 pmThat's an interesting point. There the old joke: There are 2 hard problems in computer science: cache invalidation, naming things, and off-by-1 errors.Naming things is a pain. In digital designs it is easier because most signals mean something and so the name follows naturally. But in analog circuits, it's not like every node in the circuit has a useful "meaning" so I see the difficulty there.I agree, there is a need for a hybrid approach of some kind. Perhaps ideally you could draw a schematic for an analog portion and then instantiate it in a netlist as a hierarchal block. If the analog stuff is off in its own world (like everything before an ADC) then maybe that would work fine, whereas if the design is largely analog in nature, that still probably would not be acceptable.

author: langwadt
author_rank: Super Contributor
timestamp: September 18, 2018, 09:08:45 pm
content: Quote from: djacobow on September 18, 2018, 08:46:39 pmor turn it around, draw a schematic with the analog parts and add the "netlist parts" as hierarchal blocks

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 18, 2018, 10:33:30 pm
content: Why not, but it kind of defeats the original point of using no schematic.I'm sure we can define proper constructs for an HDL which would be at least more usable. I'm actually interested in that and am currently thinking about that on and off.For nets, one construct that would be much easier to handle IMO would be to be able to define connections between signals/component pins without having to name the nets (except those we actually want to name), in the least verbose way possible. The classic component instantiation approach (which resembles a function call) doesn't cut it - way too verbose and clunky.As I suggested, some kind of "automatic" layout converter a bit like LaTeX would be a nice addition for getting a schematic view, possibly with some kind of styling templates. So that you would actually concentrate on the design itself rather than its graphic appearance.Also, schematic importers/exporters could still allow to use hybrid approaches if one so desires, or for interoperating with other teams/existing designs.

author: Rerouter
author_rank: Super Contributor
timestamp: September 19, 2018, 12:11:13 am
content: Kicads approach to un-named nets is a fairly decent one if you wanted to try synthesizing it, the first component it finds with a new net becomes the name, e.g. C2-pad1 That way it still means something even if you have not named it,but in reality you can type whatever you feel like as net names and it will run with it, and all in plain text format.If you figure out how to synthesis digital schematics from something approaching HDL, I think there would be many devs curious.

author: Bassman59
author_rank: Super Contributor
timestamp: September 19, 2018, 12:41:27 am
content: Quote from: djacobow on September 18, 2018, 04:43:29 pmMy previous employer (which goes back 14 years now) used a home-grown text-based design entry instead of schematics. It was really quite a slick system, and scaled quite well to the quad-CPU VME boards that were the company's main products.The system ran on a big SPARC (see recent thread about them!) server, so it ran on Solaris, and we used Emacs as the front end for design entry. A whole bunch of Emacs LISP code implemented the necessary features. It depended on things being in specific locations in the file system, because the Emacs modes "knew" what was what based on that.For example, all PCBs were in the pcb directory, with each design's four-letter-plus-revision name (like VCMD-A) as the root for the design. Library parts were in another directory, etc.The syntax was not unlike an HDL. You instantiated parts from the library (using an Emacs command), and the instantiated parts each had ports (pins) with electrical types defined. Each port had an actual, just like an HDL. This meant that every signal in the design got a useful name.The library system was very simple. Again, there was a library directory on the server, and each and every part had an entry. (So, yes, each and every resistor had a library part.) Part names followed a mandatory scheme, so it was all company part numbers. A part was a file with its pins all defined, for electrical type, loading, all of that. Each part also had a callout for a footprint, so when you instantiated the part in your design, it knew about the footprint. Creating a part was a simple as cloning something similar (which made the thousand-or-so resistors in the library tenable) and changing it to meet needs and giving it the correct part number.It even had the concept of modules, so for instance you could create a module for a CPU, its cache memory, all of the decoupling caps, everything it needed, and then you simply instantiate the whole module in the board design. For a quad-CPU board, just instantiate four CPU modules. Everything for a VME or cPCI interface was a module. PMC slots were a module. So there was a lot of reuse. Modules could be hierarchical -- a module could include other submodules.Since it was Unix, you could always tell who changed a file last, and it enforced a change log in the header of designs. That said, no version control system was used, mainly because it wasn't designed with that in mind, as everyone worked on the designs on the server. There was never more than one copy of a design.The system had commands for rules checking, connectivity checking, BOM generation and of course PCB netlist generation. It even had a crude ASCII-schematic generator. It handled design variants without fuss, as we sometimes had a ridiculous number of configuration options. As parts got more complex, features were added. It exported PCB netlists in both Accel and Mentor formats (the big boards were done in Board Station, I think).Once you got the hang of how it all worked, it was really quite slick and easy to understand, and you could zip through the design quickly.All that said, it was a system built up over many years and maintained by one person. And it didn't have a lot of the features we take for granted in a graphical-schematic system, such as the linking between schematic and layout (click a part on schematic, it zooms to the part on the board) and the like.Would I go back to it? Hmm... it is quite compelling. Back when I worked for that company, one of the other guys and I thought that a "better" system for the text-based design entry would be to use VHDL, as the language structure has everything you might need. All that is required is for someone to write a netlister that elaborated the design and generated a netlist in whichever PCB format you liked. Oh, and a BOM generator is needed, etc etc. But it's elegant.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 19, 2018, 01:10:46 am
content: Quote from: donotdespisethesnake on September 18, 2018, 06:53:14 pmI had seen this project. I'm not very fond of python, but it seems to have most of the basic ideas I was mentioning.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 19, 2018, 11:17:30 pm
content: @Bassman59: interesting real-life experience with this approach.As I said above, although a true language is a great addition (such as VHDL), its inherent way of describing connections is very clunky to use for a general-purpose, non-digital design entry tool. Just look at VHDL-AMS (which is now I think a part of the VHDL standard), which is the closest that has actually been standardized. Powerful but with the problems I mentioned above.Of course one could use VHDL a bit like Skidl uses Python, and not use the standard component declaration/instantiation, signals, etc, but by defining specific constructs through operator overloading and such.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 19, 2018, 11:24:41 pm
content: Quote from: djacobow on September 18, 2018, 08:46:39 pmAbsolutely.Thinking about it, naming nets is not the only pain here: having to name all the components/parts is as painful if not worse, and this is how automatic annotation in schematic entry tools is invaluable. Can you imagine having to manually define and set ALL the component references? That's just unbearable for circuits containing more than a few parts.And this annotation problem is actually much more difficult to handle than the net naming, which is rather simple to solve (as others have mentioned here and as we can see in the Skidl project).Granted that modularization can alleviate this somewhat, if you partition your design enough so that you only have to deal with a few parts in each module, but that could still be painful.It's actually a matter of being able to reference a nameless object. Easy to do graphically, tough to do textually.

author: djacobow
author_rank: Super Contributor
timestamp: September 19, 2018, 11:30:21 pm
content: Quote from: SiliconWizard on September 19, 2018, 11:24:41 pmI'm not so sure it's that awful. With judicious use of hierarchy and arrays (like VHDL generate statements) can do a lot of the work for you, certainly if you have regular structures, or near-regular structures with minor variations.I guess there is the example of the singular enormous analog rats nest that, yes, would suck to do in a text editor, but is that the exception that proves the rule?

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 20, 2018, 12:06:49 am
content: Maybe so. It's really hard to tell without actually trying on a lot of different designs to get a good grasp of the problem. Looks interesting. As I mentioned, being able to naturally design parametric circuits some parts of which could even be built algorithmically sounds quite appealing.

author: Bassman59
author_rank: Super Contributor
timestamp: September 20, 2018, 08:19:48 pm
content: Quote from: SiliconWizard on September 19, 2018, 11:24:41 pmThe system I described automatically gave each part a proper reference designator upon instantiation. And, even better, it included a geographical ref-des renumbering system. After layout is completed, you'd run another Emacs command ("georef," I think) which sucked in the layout, analyzed the position of each part on the board, re-assigned reference designators in the order you see the parts on the board, and also updated the text-based design.As for naming nets, the boards were for the most part overwhelmingly digital, so names were fairly easy to work out. For analog stuff you had to be somewhat clever, but I suppose we wereTo this day I give every single net in my board designs a proper name instead of relying on the system to name them for me.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: September 22, 2018, 10:06:54 pm
content: Quote from: djacobow on September 18, 2018, 05:48:27 pmAlso look at the WireIT plug-inhttps://forum.kicad.info/t/wireit-pcbnew-plugin-for-adding-cutting-swapping-wires-in-the-physical-layout/11212That allows direct connection entry, by select of pad(s) and then enter net names.It also allows pin swapsYou can also easily export a netlist from kiCad, via a Python script, that can be used as a snap-shot / version control check, or if mixing the external NET and join-the-dots approach inside KiCad Pcb.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 24, 2018, 05:46:53 pm
content: Quote from: Bassman59 on September 20, 2018, 08:19:48 pmI'm curious how you were textually refering to a part without having to name it? (This is the tricky part.)(Unless you were actually naming the parts but those names were not the final reference designators. Which is somewhat what we were talking about when emphasizing the modularity/hierarchy to keep each block simple enough so that naming would be doable.)

author: Bassman59
author_rank: Super Contributor
timestamp: September 25, 2018, 10:27:16 pm
content: Quote from: SiliconWizard on September 24, 2018, 05:46:53 pmI'm sorry, but I don't really understand your question.Just like in VHDL, where when you instantiate an entity, you must give that entity a unique instance name. It's not optional.The system would create a unique instance name (reference designator) if you used the correct magic Emacs command to do the instantiation. Otherwise you'd have to give the part a refdes when you typed it in.It handled hierarchical designs, with instantiated modules (each of which looks like a part, and gets a reference designator), which themselves contained parts with reference designators, in a rational way. I think there was a command that basically flattened the netlist, that is, expanded all hierarchical modules and then ensured that each part in the module had a design-wide unique reference designator. It must have, otherwise the layout wouldn't have worked (duplicate reference designators). I honestly don't remember, as it was quite awhile ago.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 26, 2018, 05:22:51 pm
content: OK, so you had to name every instance. That answers my question and concern. Apparently you had some kind of emacs extension to choose the names automatically, but otherwise, you had to manually name (and anyway reference) each instance.Yes this is like in VHDL - as we discussed earlier, I just think that it can be a huge pain especially for mixed-signal designs. Obviously this is usable, but I'm trying to see if other approaches are possible.As I said, in a schematic editor you don't have to name parts. That's one thing that makes them very productive and intuitive to use. And as we discussed, I was looking for a clever way of being able to kind of use the same paradigm in an HDL. There may not be any.

author: Bassman59
author_rank: Super Contributor
timestamp: September 26, 2018, 06:19:57 pm
content: Quote from: SiliconWizard on September 26, 2018, 05:22:51 pmWhen we draw a schematic, we don't name parts -- but we (or the system) gives them a reference designator. That's the same as the text-based system I described.You need a reference designator to ensure uniqueness, right? And it's how you know which symbol on the schematic goes with which footprint on the board. Or am I missing something?VHDL's instance names perform the same function as the reference designator on a PCB.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 27, 2018, 06:14:47 pm
content: Not sure you got my point.I'm using "naming" in the very general sense: using a word to reference some object. That can be anything including an intermediate identifier or a reference designator or just any identifier.Quote from: Bassman59 on September 26, 2018, 06:19:57 pmWell, we don't need to. That's the whole point. And we usually don't until we need to. You can draw an entire design without ever giving any part an identifier (nor the system, at least not one you have to care about or that even appears), nor having to use any to connect objects together.This is only needed when you want to generate a netlist, or obviously to ease documentation/communication. That's called "annotation" in most EDA tools and the process doesn't need any of your attention most of the time. This step is not required to draw a whole schematic and still be able to understand it.That's actually one of the main differences between drawing and writing. You don't need any kind of textual identifier (which I call "naming") on a drawing to understand the whole thing. Other (visual) cues serve the same purpose: shapes, location, and links between the various graphical objects. That's why most people still use graphical editors.One simple example of that is Spice circuits. Anyone that has written Spice circuits knows how annoying it can get when you're dealing with more than a dozen components. So most people either use schematic editors that can export to Spice, and those writing them by hand (I do occasionally for various reasons) often find themselves drawing the schematic first and then translating it to Spice by hand. Not that efficient.So again, I'm wondering/looking for maybe new syntactic/language constructs that could ease the process. Again that may not really be possible since it would somehow mean designing a language that doesn't need names to reference objects. Maybe there are some concepts to grab in hieroglyphic languages?