Injection locked VCO - Page 1
Forum section: electronics / rf-microwave

author: Sun_
author_rank: Newbie
timestamp: March 13, 2025, 06:27:52 pm
content: Hello everyone,I am trying to design an injection-locked VCO for the 2.45GHz band.During my research on the internet, I did find only one design which is at the same time VCO and with an injection port (not in IC design) but I was not able to reproduce it in simulation (picture attached to this post)... I am wondering if anyone have an idea on how to do so or had materials to share.I was able to do a different injection-locked oscillator using Ansys circuit but the output voltage was very low and I could not replicate this result using LTspice or Qucs with the same schematic..Thank you,

author: A.Z.
author_rank: Super Contributor
timestamp: March 13, 2025, 08:17:37 pm
content: what about a small amplification stage at the output offering voltage gain ?

author: A.Z.
author_rank: Super Contributor
timestamp: March 13, 2025, 08:19:19 pm
content: strange that LTSpice can't simulate that circuit

author: EggertEnjoyer123
author_rank: Frequent Contributor
timestamp: March 14, 2025, 05:36:17 am
content: What are your component values?

author: Sun_
author_rank: Newbie
timestamp: March 14, 2025, 04:54:09 pm
content: Thank you for the replies.I am not willing to add an amplification stage for two reasons :1/ it will decrease the performance in terms of SNR and phase noise and I really need to keep it high2/ Authors of this design were able to achieve output power of 5dBm and 0.3GHz VCO range so the problem is my designUsing an other design I found in a book, I was able to achieve 10dBm output power using a single transistor and very low phase noise. So the problem is clearly that my design here is not good. I was not able to transform this book's oscillator to a VCO, this is why I am staying at the moment on the design presented in the picture which is known to work.I don't know how to choose a suitable transistor/diode for this application. I looked on internet for FET used in oscillator until I found one which was already integrated in Qucs (BSP317). Its transconductance seems low for me which might be the reason I only get -10dBm but I am not sure of me since I have struggle to estimate some components values too..For component values, this is what I did: I said that Ci, Co are decoupling capacitors and set them to 1uF.Ls, Lct,Lc1 and Lc2 are for DC bias and set them to 1uH.Cd, LD,Cs1/2 are Clapp resonance elements and I used the formula f=/1sqrt(L*C_effective)I set Rs to 10ohm (i tried differents values here but have no explanation) and R1,R2 to 50ohm with Vdd to 3.3. I wanted to set a bias point to around 1.5V as 1.5V is often refered in the datasheet.If you have informations on the choice of transistor/diode or if my logic to compute component values is wrong, please tell meThank you in advance

author: EggertEnjoyer123
author_rank: Frequent Contributor
timestamp: April 01, 2025, 06:59:28 am
content: I haven't built any injection locked VCOs specifically (just normal VCOs)Try using more physical components. 1uF and 1uH are very big values at 2.4 GHz, try something like 22nH and 10pF instead. Using big values sometimes confuses the simulator, just because of the amount of time it would take for a 1uF capacitor to settle to steady state. You can also sometimes get more power by messing with the output capacitor.Increasing R1+R2 and putting a capacitor to ground for the divided voltage also might help.Rs just controls the biasing point of the FET. Increasing it will limit the current through the FET.

author: Sun_
author_rank: Newbie
timestamp: April 17, 2025, 04:32:35 pm
content: Thank you for the replies.I tried your answer by changing the bias but also using ideal DC block or AC block giving the same results as before. Is it possible to tell me if my approach towards the problem is correct or not ?What I did for this oscillator is first simulate the FET alone it to determine if its IV curves match its datasheet. I also simulated a complete EVB using this JFET for LNA application and got the same results from the datasheet EVB.So for me the FET model is validated.I then began designing the oscillator. I set a bias for the FET. I only considered L_choke and resistors and removed all Ci, Cs, Cd, Ld. I set a bias to 35mA which is twice the wanted current on the 50ohm load output for the wanted power. This x2 factor was found in a book for optimal phase noise in BJT but I can change it later if the power is not enough. I also verified that the maximum current allowed for the FET which is 60mA.After that, my prodecure to design the oscillator was :1/ Add C0 and Cd as decoupling capacitors and add S_port behind them. I expected to see |S21|>0dB with port 1 on Cd side and port 2 on output.2/ Then I add the Cs1, Cs2. I expected to see Z11 on the capacitive side of the smith chart and |S11|>0dB for oscillation.3/ Lastly, I had the LC tank Ct and Ld. I vary Ld to have a phase of 0° on S11 at 2.45GHz as well as |S11|>0dB creating the oscillator behaviorBy doing so, I never get |S21|>0dB from step 1 nor others steps. I also tried to add the 50ohm load on injection port. Without it, I see a floating gate for the JFET in small signals and was not sure about this.Is my procedure to design the oscillation wrong ? Can JFET stability impact the oscillation ?

author: EggertEnjoyer123
author_rank: Frequent Contributor
timestamp: April 18, 2025, 07:43:54 am
content: Does bypassing Rs with a decoupling capacitor do anything?Also the transistor acts as a common collector, not a common emitter. So it makes sense that S21 is under 0 dB (since the output voltage should be lower than the input)

author: Sun_
author_rank: Newbie
timestamp: April 21, 2025, 07:26:21 pm
content: Hello EggertEnjoyer123,Isn't Cs2 already bypassing the Rs from step 2 ? I added a decoupling capacitor on step 1 and both S12=S21=0dB on all frequenciesCommon collector is a good remark and I did not saw this. I tried to calculate the the gain of my circuit but as the gate is left floating without injection port I find it weird.The transistor is not really in a common collector or emitter also since the input is place on the drain not gate. What I can see in simulation is that the S12 (port 1 LC tank and port 2 output) is from -20dB to -8dB depending on the bias value. But the S21 is from 1dB to 10dB.I tried to procedure what I wrote on previous post changing port 1 and port 2 locations but at step 2 since S21>0dB but the impedance is not anymore negative from step 2.I think that port 2 with output is the correct location since I found several scientifical articles with this architecture. However, I don't know how they achieve it