Logic Analyzer / MSO Digital input max signal frequency per Nyquist criteria  - Page 1
Forum section: electronics / testgear

author: TK
author_rank: Super Contributor
timestamp: May 12, 2020, 03:31:18 pm
content: What is the maximum signal frequency that a Logic Analyzer / MSO Digital input can capture based on Nyquist criteria?I tested with a 500MSa/s Agilent Logic Analyzer and an MSO with the same 500MSa/s on digital inputs. I generated a 112MHz clock signal using the Si5351 clock generator and the MSO analog input measures correctly 112MHz, while the digital input measures 100MHz. The Agilent Logic Analyzer shows the same waveform distortion (not equally spaced high/low square wave).Is it reasonable to say that it requires 5 times the signal frequency to sample the correctly even when the waveform is distorted? In this case, 500MSa/s / 5 = 100MHz.MSO: 112MHzAgilent 1671G: 112MHzMSO: 13.51MHz

author: Tomorokoshi
author_rank: Super Contributor
timestamp: May 12, 2020, 04:19:48 pm
content: Disclaimer: I haven't used an HP Logic Analyzer for a long time.1. Are you in State or Timing acquisition mode? There are limitations around 150 MHz for State mode. Timing mode has limitations of 250 MHz or 500 MHz depending on the channel configuration of the pods.2. With TTL thresholds the sine wave might not be achieving setup and hold requirements, so it could be missing cycles. Is it possible to drive a square wave of your frequencies into it?

author: TK
author_rank: Super Contributor
timestamp: May 12, 2020, 04:26:12 pm
content: Quote from: Tomorokoshi on May 12, 2020, 04:19:48 pm1. I am using timing acquisition mode @ 500MHz2. It is a square wave. Both the logic analyzer and the MSO are using TTL threshold. With CMOS or LVCMOS the waveform changes, but still not regular high / low transitions.

author: Tomorokoshi
author_rank: Super Contributor
timestamp: May 12, 2020, 04:43:24 pm
content: Ok. On the MSO, the analog waveform seems to be slew-rate limited / filtered to be something between a sine wave (which I had originally assumed) and a triangle wave.Could there be excess parasitics with the cabling setup? It sounds like from the original posting that both instruments were on the signal generator at the same time. That is, the yellow trace on the MSO may be showing the actual waveform going into the logic analyzers.1. Can you try one instrument at a time?2. It looks like the source impedance should be 50 ohms. What are the cable and input impedances of the instruments? How long are the cables, what type, etc.

author: TK
author_rank: Super Contributor
timestamp: May 13, 2020, 12:05:56 am
content: Analog channel has 200MHz 10X probe.1. I had 1 instrument at a time (digital channels on the MSO)... I then connected the analog channel to verify.2. The SI5351 board is connected to a breadboard, but I am using male pin headers to connect the analog probe and the digital POD cables.With the same setup, it can show a nice square wave on 45MHz SPI SCK signal. I need to test increasing the clock to see when I start seeing irregular (not perfect 50% High-Low) signal on the digital inputs. The MSO has 2GSa/s for 4 channels, I was using 2 channels at the time of the measurement, so it was sampling @ 1GSa/s. Digital inputs are sampled at 500MSa/s.

author: tautech
author_rank: Super Contributor
timestamp: May 13, 2020, 02:20:47 am
content: IMO the impedance of the MSO is impacting on the result whereas a 10x probe will have less effect.While 10x probe vs MSO capacitance loadings are similar the R of the MSO probe is a magnitude less.I might be wrong but I see the MSO insertion having a greater impact on a result which of course has little to do with Nyquist.And of course each bus will be impacted differently depending on how low its impedance is.

author: nctnico
author_rank: Super Contributor
timestamp: May 13, 2020, 06:45:13 am
content: Quote from: TK on May 12, 2020, 03:31:18 pmYou have to look at this from the time domain: The digital sampling interval needs to be smaller than the narrowest pulse you try to capture. Digital probes usually have enough bandwidth; even with attenuated signals there is more than enough swing to meet the minimum hysteresis requirements. Worst case you'd have to adjust the thresholds a little bit.

author: rcjoy
author_rank: Regular Contributor
timestamp: March 27, 2023, 06:40:01 am
content: I know this is an old thread, but I had to chime in.Your 1671G logic analyzer waveform display shows it is sampling at 4 ns, which means it is in the 250 MHz timing mode.It will show a sample period of 2 ns when in the 500 MHz timing mode. See the attached picture for what you will get whenlooking at a 112 MHz waveform in the 500 MHz / 2 ns mode. Given the sampling rate, it is as expected.