Decoupling capacitor trace length for low-frequency applications. - Page 1
Forum section: electronics / beginners

author: GymBoss
author_rank: Newbie
timestamp: August 27, 2023, 12:54:24 pm
content: Hello.TLDR question: what is the rule of thumb for decoupling capacitor trace length\inductance for not high-frequency (<= 100Mhz\250MHz default MCU frequency nowdays) applications?I know the long answer - ".... it depends on calculations, on characteristics, etc."Also i know the short "fast" answer - "as close as possible"And thats the problem - technically, i can place place caps just near pin, idk, in 0.1mm from it. But this makes real pain in ass at signals tracing time.So generally im make 1mm traces. But 1mm for 32MHz STM32L0 and same for, idk... ESP32 240MHz? Sounds weird. Its looks like 1mm traces have huge reserve for 32MHz application or invalid long traces for 240MHz... Looks at real applications by big vendors, i suppose, what the first assumption is true one.It means, what i can make more long decoupling caps traces for "low frequency" applications and make signal tracing more easy == more well designed PCB (grounds, lengths, etc).But in home, you really have no tools to make such exepriments. Im guess, you need:1) Really good theoretical base and experiense for all of this spike\harmonic shit calculations and assumptions.2) Some experience and knowledges in "good" simulators.3) 200MHz+ oscilloscope to see what is really going on.I haven't, like most of generic amateur PCB designers, i suppose.But, i know the rule of thumb about 15nH for 1inch\1nH for 1mm of trace.And this is looks like not so huge for this frequences, it is like near 1.5Omhs for 200MHz and 1Omh for 100MHz. And... it is very near of impendance of 1206 ceramic capacitor...If my assumption is right, we need to know the amount of current, draining during the IC transient, if we can assume it somehow base on Freq\average consumption, we can assume the voltage drop.Is my thoughts right? Can you help me?

author: SuzyC
author_rank: Frequent Contributor
timestamp: August 27, 2023, 02:35:00 pm
content: You're overthinking the problem. The problem has been long solved. For ideas, Look at the layout and placement of bypass caps on salvaged boards for a hint on bypass cap placement.Just use a .1uF ceramic cap bypass and you'll be fine. Locate cap as close to and between the IC's Vdd and Vss pins as possible without interfering with probing or making pcb trace layout looking abnormal. If you have a two-sided pcb, then use vias to connect with shortest lead length.Then test your device for proper stable operation.

author: GymBoss
author_rank: Newbie
timestamp: August 27, 2023, 06:54:04 pm
content: All this i know. But this is not solve the question:1) "As close as possible" - it is possible to place it in 0.1mm, no really, but more convenient is place it in few cm (near power supply lol). This "as possible" is really pain, when you trying to make a compact design.2) "Look at big guys" - sure, but there is significant amount of contradictory data. I have saw 100MHz+ applications with 3mm+ trace length, but in reference board (idk discovery\nucleo) there is only 1mm for L0 cores, what works only on few dozen MHz, same 1mm for H7.This topic is not about "oh guys i dont know where to place my decoupling cap", it is about "ok, i know how to place it safely, but now i want to know rude borders".If this small clarification drag an avalanche of heavy-math, so ok... but looks like, what in this "rude" way, it is do not take that much.

author: BillyO
author_rank: Super Contributor
timestamp: August 29, 2023, 09:27:09 pm
content: Your question can't really be answered as you've made many assumptions that show a cognitive bias.Even "slow" digital circuits, running at 10MHz can produce switching frequency components in excess of 1GHz. Even simple old 74ACxxx logic is capable of that. More modern logic will easily produce switching frequency components into the 10s of GHz.1) Use at least a 4-layer board and reserve the inner layers for ground voltage and supply voltage planes.2) Put at least one 0.1uf bypass cap at EVERY power/ground pin and connect it to hat pin with as short a trace as possible then connect it to the other power plane through a via and a trace as short as possible. IF you are using SMT look into via in pad.3) The traces to and from the caps should be as short and as wide as possible.4) for devices that are particularly sensitive to supply noise or are particularly power hungry consider putting a 2nd capacitor at each pin. If the chip is power hungry the 2nd cap might be a 1.0uf. If it is particularly sensitive the 2nd cap might be a 0.01uF.5) Stagger holes (vias and/or component lead holes) such that there are no contiguous breaks in the power planes.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 30, 2023, 09:14:03 pm
content: A few extra millimeters is probably all right. Do note that it is not the distance from the capacitor to the pad of IC that counts, but it is the distance from the capacitor to the silicon inside the IC. And the frame for the pins and the bondwires to the actual silicon are already several millimeters. And compared to that, a few millimeter extra does not change much, but do not go adding whole centimeters.