Method for testing 64MHz USB DAC for missing samples  - Page 1
Forum section: electronics / beginners

author: 240RS
author_rank: Regular Contributor
timestamp: July 24, 2023, 04:55:39 pm
content: I am in this project to record the complete 2-30MHz radio spectrum for many seconds and have received good pointers from this forum on how to do that: Cypress USB3.0, i7 or single board computer specs, commercially available RX888 SDR. And it seems to work. I recorded GB’s of HF noise to SSD with seemingly correct 256MB/s data rate (32bits per sample, 64M samples per s).Next up is that I want to verify I didn’t miss a single sample. For that I want to generate a known digital signal, D/A convert that with a vector signal generator (512MSamples, 160MSPS max), A/D convert it with the RX888 over USB, store it and compare it with the original.I was wondering if there is commonly used method for this with focus on missing samples. I have thought about chirps, high frequency signals and sync pulses. But it felt as reinventing the wheel. Since I do not expect to receive accurate samples every single time (noise), I also do not expect the transmitted and received digital signal to be 100% identical.I want to test conditions under which the PC might have overrun conditions. I am concerned about the effect of missing samples since I want to use the recoded data to decode OFDM signals. And orthogonality (the “O” of OFDM) is completely lost if you lose a sample randomly every 1000 or so. In real time this issue doesn’t manifest itself. A wrong sample is less impactful than shifting part of your samples.

author: 240RS
author_rank: Regular Contributor
timestamp: July 25, 2023, 01:01:59 pm
content: Well, making that test wasn’t too hard. Made a 1M sample long 6.4MHz tone followed by 1M zeros and let the signal generator repeat that at 64MHz sampling rate. Recorded two seconds with the ADC and SDR Console, sampling at 32Mhz and loaded the result in Python. All the bursts are 500kSamples (plus or minus 1) long. And the 60th burst started 60MSamples later than the first (clock of ADC is 0.5ppm per the spec).CPU load was 50% (8 core) without peaks. Disk was up and down with peaks at 1GB/s. I had not expected this to work that easily. Laptop I used is a 6 year old gaming laptop!Still interested to know whether there are standard testing methods to asses ADC performance at high sampling rates.

author: __greg__
author_rank: Newbie
timestamp: July 25, 2023, 01:47:42 pm
content: I did the following:feed ADC with some fast sine signal (f/4 > f > fs/10).Sample it as long as needed. The longer the better.Multiply resulting samples by the same sine signal in digital domain.Do some simple low pass filtering. No need to be agressive, 4/8/16 sample's averaging will be fine.If all is OK, You'll see only smooth - sailing DC value.It will change in time showing the slow ADC sampling clock drift from your perfect digital sine frequency.If clock differs by 0.01Hz expect sth similiar to sine of 100s period.if You've lost single sample, or got some sample repeated twice (like it may happen in bad async FIFOs for example)You'll see a sudden change in filtered signal.This change can be easily detected visually if You plot it,but in case of lots of samples let for example matlab or python or whatever find it...

author: 240RS
author_rank: Regular Contributor
timestamp: July 25, 2023, 07:03:43 pm
content: Perfect and understood. Exactly what I was looking for.

author: 240RS
author_rank: Regular Contributor
timestamp: July 26, 2023, 08:56:11 am
content: Quote from: __greg__ on July 25, 2023, 01:47:42 pm__greg__, you intrigued me with your method. I know that if you multiply two sinusoids with the same fundamental frequency and integrate that, that you end up with DC. Which is a constant based on the magnitudes of the two and the phase shift. Basis for Fourier’s math. So in a way simple (if you know it), but also very clever. Can I ask you if you have more background on this? Would be great if there were some articles on how to use this principle.While writing this I realized that with the proposed method the DC value is constant, and dependent on cos(phi). If you would multiply by double (or any other integer) frequency, the integral should always be zero. Is that helpful in a way? Or not to increase sample rate, you could also multiply with half the frequency I guess. It makes me curious!

author: 240RS
author_rank: Regular Contributor
timestamp: August 08, 2023, 08:31:34 pm
content: Solved it I think. Basic decimation by a harmonically couple frequency did the job I think. Python notebook with test attached. I took a 10MHz signal, sampled it with 32Msps for 9 seconds and just decimated it by 3200. Too simple (if correct, please let me know if wrong).

author: radiolistener
author_rank: Super Contributor
timestamp: August 09, 2023, 09:41:08 am
content: You can put clean sine or saw tooth waveform on the DAC and then analyze it's output in frequency domain. If it has missing samples, it will lead to distortions. But any DAC has it's own distortions, so you're needs to know the distortion level of your DAC for comparison

author: gf
author_rank: Super Contributor
timestamp: August 11, 2023, 02:20:20 pm
content: Quote from: 240RS on July 26, 2023, 08:56:11 amI suggest the following modification to __greg__'s procedure:Use signal frequency f = fs / N where N is aninteger> 2After sampling, multiply with acomplexsine wave exp(-j*2*pi*f*t)For the moving average filter use a length ofexactly Nsamples, since this leads to zeros at frequency f and integral multiples of fBoth, magnitude and phase of the filtered product are supposed to be constant if the sampled signal happens to be an (undistorted) sine wave with frequency f.[ Btw, note that this calculation is basically equivalent to a STFT with a length of N samples and an overlap of N-1 samples, but calculated only for the single frequency bin with frequency f. ]