Cascode MOSFETs for high voltage - Page 1
Forum section: electronics / projects

author: Red_Micro
author_rank: Regular Contributor
timestamp: February 28, 2020, 11:29:21 pm
content: In this circuit attached, the HV+ point ranges from 100 to 1200 VDC. The two MOSFETs are rated at 800V, which makes 1.6kV breakdown. D7/D8 are 300V each, so they have a clamping voltage of 600V. My question is:If R7 is "large" there is no low impedance path to turn on or off Q1 so that turn off would happen very slowly which might be an issue for Q2, as I could get larger voltages on it.If R7 is small (near zero), when Q2 turns off it would turn off Q1 quickly but the voltage at the Q1/Q2 connection is somewhat unpredictable. I want to get C5/C6 from almost zero volts when the FETs are on back up to half of HV+. The only path to charge C5/C6 is through R4/R5/R6. That will take a long time so Q1 might see most of the voltage for a while.So is there actually a moment when a FET could see a voltage bigger than it can handle? At the end, the purpose of the cascode is to increase breakdown voltage of the main switch.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 29, 2020, 12:05:43 am
content: Referring to your previous thread (because you've hidden or omitted component values, erasing information in this new version of schematic), the R and C values are such that the middle-side gate node follows the bottom side switch reasonably quickly.In the instant of turn-on, if nothing else the zener shunts the capacitor charge through the switch, and drain voltage follows source voltage (because Vgs is high, saturating the middle-side transistor). It is probably intentional that the low-side switch absorbs somewhat more turn-on energy than usual, due to this; it should be heatsinked accordingly.In the instant of turn-off, the middle-side transistor turns off gradually. Whereas in a regular common-source gate drive situation, the gate can be driven quite hard; in this case the middle-side transistor is driven off by drain current, so, probably not very fast/hard (depends on turn-off current; 100s mA minimum?). Its gate voltage also rises gradually over time, due to the RC circuit connected.Preferably, the RC circuit matches the time constant of the drain voltage rise, and low-side turn-off, so that Vds's are reasonably closely tracked; there is some room for adjustment here, and again, rate will depend on Id(pk).Worst case, the rates don't track, and one or the other ends up avalanching briefly; this isn't really a killer, it just increases switching losses a bit. Enough that you need to design for it. A worst case design with generous heatsinking isn't a bad idea, but it can be improved through these adjustments, and range testing.Tim

author: Red_Micro
author_rank: Regular Contributor
timestamp: February 29, 2020, 12:17:45 am
content: Quote from: T3sl4co1l on February 29, 2020, 12:05:43 amThanks. This is the original design application note:http://www.ti.com/tool/PMP10195and full schematic:http://www.ti.com/lit/df/tidrlf7/tidrlf7.pdf.I'm just trying to use this approach for my wide input voltage, and thinking what could be wrong in this design with the cascode configuration. One of the things I'd like to change is the circuit around Q3, since Q3 part no. STP3N150 is a really pricey transistor. And the other challenge is find a right VOR for the flyback transformer redesign.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 29, 2020, 12:33:01 am
content: I mean you can get 2.5kV, even 4kV transistors, whole single parts, but it's your own fault I guess for needing such a high voltage range. This is legitmedium voltageand it's not going to be cheap to work with.A two-transistor forward or flyback converter may actually be desirable, if the isolation / bootstrap drive isn't too annoying to deal with.Tim

author: Red_Micro
author_rank: Regular Contributor
timestamp: March 01, 2020, 01:54:58 am
content: Quote from: T3sl4co1l on February 29, 2020, 12:33:01 amA question.. looking into the original schematic (http://www.ti.com/lit/df/tidrlf7/tidrlf7.pdf.) What could be the reflected voltage? I see D1 is 110V, so it leads me to think they chose a low reflected voltage for this wide input range (64-1260VDC). This is what I think:With two 800 V mosfets, we should leave at least 100V safety margin when at max voltage. So, we don’t want to exceed 700V on each drain, i.e., in total 1.4kV.Vinmax + Vz = 1400 + Vz <=1200Vz <=1400 – 1200 = 200VLet’s pick Vz = 110VVz/VOR = 1.4 optimum ratioVOR =0.7*110 = 77 Is this Okay?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 01, 2020, 11:46:42 am
content: Yes, which also implies a low duty cycle, which seems fine considering how little current it takes to draw a lot of power at these voltages, well, the higher voltages anyway; lower voltages will pretty quickly run into CCM and current limiting.VOR?Given that the primary peak is maximum 110V and the secondary is nominal 24V, the turns ratio must be more than 110:24. The secondary uses a 600V diode, suggesting the maximum primary supply of 1260 must be divided to less than that, or a maximum ratio of 1260:600. If we take the (geometric) mean of these, we get 3.1:1. Aux would be about half that, since the controller needs 10-20V.Ah, LM5020 has an internal regulator, up to 100V supply, so aux can actually be pretty aggressive. Could be same ratio as main secondary. And it's... basically a UC3842 after that, it even has the same COMP pullup, offset and divider, heh... So I don't know what the RCD network in the other thread was, it's not an AC sense pin like for quasi-resonant operation.Tim