53131A counts Frequency but not Time - Page 1
Forum section: electronics / repair

author: Tony_G
author_rank: Super Contributor
timestamp: December 30, 2016, 01:37:16 am
content: Hey All,I asked this over on the HP Yahoo Group but I thought I'd post here as well as I'm out of options (and running out of vacation to work on it).My 53131A (HS Oven & Ch 3 to 3GHz) seems to not want to measure when I try to use the Time options, T1 to T2, Rise Time, Fall Time, +/- Width. It does however measure Period correctly and all the Frequency options. It passes both the start-up and detailed self-tests and the high stability time base is bang on 10MHz.The service manual is only to the assembly level so it doesn't provide any guidance on what could be wrong except to use the self-tests, which pass so they aren't much help (The FPGA, FR END & MEAS tests pass). In trying to track down the issue I removed the 3GHz pre-scalar, the high stability time base and then then the cans from the front end.While doing that, I did notice that the unit would occasionally fail the startup self-tests when cold but rapidly warm up to the point where it would work. So, I thought it might be cold related and I can get it to fail the FR END test if I use some cold spray on U64. I'm not sure if this is telling me anything though as I can also get it to fail if freeze the corresponding CH2 Op Amp (it's an LM308AM) U57.Nothing else on the motherboard is temperature sensitive though which I would have expected if there was another thing causing the cold start fails.With that as the only pointer, I ordered replacements for the LM308s w3hich arrived this morning. I removed the old LM308s and installed the new LT1008s (a drop-in upgrade per the datasheet) and this had no impact on the actual issue.I'm now not sure whether the temperature is an issue because the cold is causing something or if it is simply the ice/condensation on the caps causing the apparent capacitance to change in the front end.Using the schematic for 53131-68004, which isn't my board - I have 53131-68001 but this is the closest revision board number that I can find - I traced the signal through to where it goes to the FPGA and it does indeed disappear when you go to "T1 To T2".My problem is that as far as I can tell all the components that control the signal path are working. They react to changing from frequency to time but when they're in frequency you can see pulses occurring and the gate indicator flashing but in Time mode you see one pulse and the gate indicator is solid.For example, if I feed 10MHz into CH1 I see 2.5MHz signal on pins 18 & 19 with Vpp of ~1.3V and a Vmid of 3.6V - I also see a 5MHz signal on pins 3 & 4 with similar voltages. As soon as I switch over to Time they all go their 1 & 0 logic levels (MECL I believe because there are MECL to TTL converters on the schematic).I'm really at a bit of a loss as what to do next.I can only think of two reasons this would be happening. The first is that the firmware has become corrupted - If the microprocessor was failing I'd expect it to fail across the board and not just in one specific area, similarly I'd expect that the FPGA wouldn't work for frequency either as the same IO pins are used in both cases. Both the micro and FPGA pass all the self-tests.The second is that there is something in the signal path between the input and the FPGA that changes when you swap from frequency to time measurements. However, I simply can’t find anything that doesn’t appear to be working, so if it is there then I’ve missed it.Any suggestions?Thanks,TonyG

author: dhillman
author_rank: Contributor
timestamp: December 30, 2016, 07:19:36 am
content: Regarding the firmware, there is a checksum at the last two bytes. If the CRC does not match during the self test, the unit will declare ROM FAIL.This was my case on a 53132a. Good luck.

author: Tony_G
author_rank: Super Contributor
timestamp: December 30, 2016, 07:55:38 am
content: Thanks - The firmware passes both the start-up self test and the more detailed one so if it's doing a complete checksum review of it then I can probably rule that out.TonyG

author: HighVoltage
author_rank: Super Contributor
timestamp: December 30, 2016, 10:09:44 am
content: I have repaired several of these counters but you have an odd problem.Are you sure your trigger levels are correct?Have you tried to set it up remotely over GPIB and get the same or different results?

author: Tony_G
author_rank: Super Contributor
timestamp: December 30, 2016, 07:06:23 pm
content: Thanks HighVoltage - I hadn't tried that before but I tested this by following the procedure detailed in the manual for the 53131A Performance Test 1: Time Interval (Page 1-17 of the Service Guide) - I set it up exactly as described except I used a Rigol DG1032Z instead of a HP 8130A.In any case I didn't try using GPIB so trying that I get the following using a 3 MHz square wave setup for a 50 ohm load, high of 1V, low of -1V. Here are the GPIB commands I issued:[Device Clear]*RST;:CONF:FREQ (@1);:EVENT1:LEVEL 0;:INP1:COUP DC;:INP1:IMP 50;:INIT;:FETCH:FREQ?The result of that is +3.000E+006[Device Clear]*RST;:CONF:PER;:EVENT1:LEVEL 0;:INP1:COUP DC;:INP1:IMP 50;:INIT;:FETCH:PER?Result - +3.333E-007To measure T1 to T2 I need to set the common and slopes as well:[Device Clear]*RST;:CONF:TINT ;:INP1:COUP DC;:INP1:IMP 50;:INP2:COUP DC;:INP2:IMP 50;:EVENT1:LEVEL 0;:EVENT1:SLOP POS:EVENT2:LEVEL 0;:EVENT2:SLOP NEG:EVENT2:FEED "INP1";:INIT;:FETCH:TINT?This generates a VI_ERROR_TMO which is a timeout and is indicative of what I see when I do this manuallyYou can see the C# code in the attached file

author: Tony_G
author_rank: Super Contributor
timestamp: December 30, 2016, 11:04:26 pm
content: It may be normal but I do notice that the Motorola 10H series ICs run very hot:In the range of 145 to 150F(63 to 66C) - Seems a bit hot but not unprecedented I think.U52 is where the signal goes into the FPGA and where I can see it disappearing on pins 3,4,18 & 19TonyG

author: TheSteve
author_rank: Unknown
timestamp: December 30, 2016, 11:14:51 pm
content: I can confirm those IC's do run hot - it is normal.

author: harrimansat
author_rank: Regular Contributor
timestamp: May 02, 2018, 09:04:52 pm
content: is ECL logic