Design review needed: TPS65131 buck and inverter (single supply to dual) - Page 1
Forum section: electronics / projects

author: anotherlin
author_rank: Frequent Contributor
timestamp: December 22, 2022, 03:27:34 pm
content: Hi everyone,I'm designing a small board for the TPS65130/65131 which is a buck and inverter DC/DC converter. So single supply (2.7-5.5V) to dual supply (maximum -15V/+15V). So pretty useful for USB (5V) or from a single 3.3V supply.So I'd be glad if you guys can do a design review about the layout. I've attached the schematics and the annoted layout.I've not specified the values of the components yet. In fact, they're dependent about the outputs you want, and the way you want to optimize for your application.It's actually a "reboot" of a previous project (https://github.com/anotherlin/olympic-white) that I started and then left because the first try was unsuccessful.It is an "open source" project made with Kicad and everything will be on github when the first prototype will be made.The schematics is basically following the "typical application" of section 8 of the datasheet. I've added extra input and output capacitors, it may be cheaper to put 2 instead of 1 big capacitor.I've written a lot of comments have been written on the attached layout. I need to make the copper pour cleaner (corners in particular).For the inverter part (lower part of the board), I think it is about as close/tight as it can get regarding the loops.For the buck part (upper right of the board), the closed switch loop (input caps C1, C11, inductor L1, U1 (TPS65131 switch) to ground is about as tight as possible. The "open switch" loop to output capacitors C4 and C13 is a bit bigger, but current from V_in (input supply) is flowing, so my guess is that it's ok.So did I do anything wrong?Things to improve?Suggestions for this project?Also, if it's more convenient to have a look using Kicad directly, I can provide the project files.Thank you.Best regards,

author: Thunderer
author_rank: Regular Contributor
timestamp: December 23, 2022, 02:06:27 am
content: Hello,I would stick to the datasheet example on the PCB layout.I tried to be creative on my version and ended up with an unstable negative voltage rail. I have to redo the layout and manufacture a new PCB.The EVM gives you too some more details on the best PCB layout, and also about the proper type of capacitors. I'd stick to X7R allover, expect the specified COGs. Otherwise, you'd be surprised about the behavior of the circuit if you use a Y5R where you should not use.At the same time, I'd look also into getting rid of the quasi-useless PMOS transistor (switch).

author: anotherlin
author_rank: Frequent Contributor
timestamp: December 24, 2022, 10:57:45 am
content: Copying the layout of the "typical application" of the datasheet, or the one used by the evaluation board, is the low risk solution.However, nothing is learned in the process.For the Q1 switch, this board can be enabled/disabled, I've not yet routed ENP.

author: Thunderer
author_rank: Regular Contributor
timestamp: December 24, 2022, 10:45:14 pm
content: Well, what did you learned from the failed layout? The question is valid, not an argument.For me, I learned that I placed an inductor too far from the chip.The new layout to send manufacturing next week:A+ et Joyeux Noël!

author: anotherlin
author_rank: Frequent Contributor
timestamp: December 26, 2022, 10:47:09 pm
content: The first try was actually my second design using Kicad and that was just too ambitious for a second project.I never managed to solder U1 properly and the 0402 resistors are just too small.Most importantly, I didn't do my homework and I didn't understand how boost and inverting converters work.In particular, if you look at the example layout from the datasheet, I just don't get why D2 diode (for negative output from the inverting converter) is the closest component to U1, instead of the inductor L2. In the (internal switch) closed state, it won't conduct and L2 will charge through U1. And in the opened state, no current will flow from OUTN of U1, and L2 will "discharge" through D2 to the output capacitor.BTW, I've completed my layout, please see attached. Hopefully, I'll send to fabrication (JLCPCB or PCBWAY) the first week of januaryBonne année

author: Thunderer
author_rank: Regular Contributor
timestamp: December 27, 2022, 06:22:19 pm
content: 2 comments:1. I see the first design had some pins floating, the Enable pins. The datasheet does not say if they are good to float. Sorry, I did not looked into this first time.2. The output caps for the positive rail are too far from the chip GND. I'd put them where the text Olympic is or put some vias on the GND trace between the C1 and C4 - that's a "nice" ground loop.NB: I will do the same for my design too, though I use overall ground planes on both sides.Regarding the 0402, I use this package only for decoupling caps that need to be very close to chip's pins. Otherwise, I build with 0603.For soldering the TPS, put not too much solder, and much more flux. The central pad will align the chip and the liquid solder will do its job. Bonne chance!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 27, 2022, 08:00:11 pm
content: More vias. Way more vias! Is the bottom side even GND? It looks like there's thermal relief to VIN; and the two bottom traces cut straight across the pour, so that any current path on the pour would have to wrap all the way around the chip!Just because nothing else connects to VIN, doesn't mean currents won't flow (or try to) in that pour. Every current on top, will induce a ("image") current underneath the trace, and those currents together will follow the path of least impedance -- which for switching frequencies is very close to the route. But anything crossing that gap, that current will have to go all the way around, and drop a huge voltage (10s, maybe 100s of mV peak?).Well, "huge" is relative -- but keep in mind, EMI limits are in the fractional mV, roughly speaking. 10s of mV you will easily see while probing the circuit, and when it manifests in the common mode, you will find it quite pervasive and confusing (including when probing between GND and GND!).What is "Earth"? Shouldn't that be tied with GND?!...I think a lot of appnotes overemphasize ground separation. Really, all they want, is to have the signal-level stuff, returned to ground near where it says -- usually an AGND pin or whatever. They don't mean to imply cutting the whole damn board in half and putting things over here and over there, neer the tween shall meet -- but clearly they often do a poor job communicating that, and people are misled into being overly paranoid.In almost every single case, you will have better results just pouring whatever counts as "ground" -- what is usually the most numerous (in terms of pads) net, against which everything reads its inputs and outputs -- all over the board, letting that fill top and bottom, stitching them liberally with vias (they don't cost you anything, go nuts with them!), and routing the rest. You want to pack input/output/bypass capacitors close to supply pins, and also the catch/boost diodes as in SMPS like this (the switching loop comprises diode, switch and cap). Inductors can be further out (don't worry much about inductors --they already have inductance,you can't make anything worse by putting a long inductive connection to them!*)*And by "much", I mean, in exactly the scope of that: a long inductive path won't affect theinductanceof an inductor to any meaningful way. The path does not need to be short to keep inductance low (which is the purpose of the switching loop minimization).There is still good reason to keep it small,but this is due to where the currents are flowing (don't shove it off somewhere by a bunch of signal traces or connectors where noise will be induced!), and simply the voltage on the switch node itself, which capacitively couples to everything near it. So, keep the inductor nearby, but don't pull your hair out if it has to be a couple mm away, no one will notice....Oh, is the top side actually poured too? I think I see a few wispy outlines of pads on there.Always show everything in your design!It doesn't look like it'll fill very well, among the traces and chip R/Cs. Always check pour/fill, and add stitching vias to connect peninsulas or islands that are cut off from the bulk, or set island removal rules so it doesn't try to fill every minuscule gap that won't matter.Anyway, back to grounding: the thermal pad on that style package is used for heatsinking. It must be connected to a wide pour of copper, to spread that heat out. Leaving it floating in space is a bad idea. The datasheet may or may not actually say what the hell it's connected to (if anything at all), unfortunately many aren't at all specific -- in that case, it's probably safe to assume it can be grounded anyway, but if in doubt, check (search TI's e2e forum, or sign up and ask yourself!).Disclaimer: this is just stuff I see off-hand in the screenshot provided -- I haven't looked at the datasheet yet. Take it as a primary resource, until found otherwise. (And yes, it does happen from time to time; they aren't as well written as you would hope.)Tim

author: anotherlin
author_rank: Frequent Contributor
timestamp: December 29, 2022, 03:18:48 pm
content: Thanks for your feedbacks, I've followed your recommendationsI've also been looking at quite a few documents and youtube videos regarding layout.One particular document is interesting:https://www.ti.com/lit/slva773So indeed for a boost converter, the most important thing seems to be the output capacitor.And it does make sense as the inductor charging (switch closed) duty cycle is long (especially if the output voltage is much higher than input), the output capacitors must provide the necessary voltage during that time, and the discharge duty cycle is short, they (capacitors) must be charged as fast as possible.At first I thought that because the L1 inductor is in series with the output, that didn't matter.Also, I've poured everything with GND ground whenever possible. The back side is basically all ground, with vias routing for the feedback of the positive voltage, and the controls ENN, ENP, PSN, and PSP. In particular, I've routed the positive feedback bottom side so as not to "break" the path of ground to the output, I've even added some vias. The GND "input" to the boost converter is through vias from back layer.I still have separated analog ground (AGND) "earth" in schematic and GND. They are separated but connects through pin AGND and pad 25 behind U1, as recommended by datasheet. If that's no good, I can still "bodge" wire the prototype PCB board.Also, ENP and ENN must be connected to VIN by end-user, this is output enable/disable. The pins (2.54mm separated) are breadboard compatible.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 29, 2022, 04:14:55 pm
content: Much better! But it can be improved still:- L1 and D1/C4/C11 can be swapped. This keeps the high frequency C1-U1-D1-C4/C11 loop minimal.- Ditto D2/C5/C12 and L2.- The block of passives where it says '"Earth"' can be moved up and over a bit, with no impact on themselves, making room for the above move.- Matter of fact, the IC and related stuff can all expand into that otherwise unoccupied area "GND", this will greatly relieve congestion in the bottom-left corner of the board(!).- This should also be good enough to get the switching loop away from the bus crossing (the EN and jumper signals) -- better yet, move the EN/jumper to the bottom edge so they aren't involved in the switching or output loop at all.You may still want an LC on the input or outputs; something small like 0.2-1uH and another 4.7uF is probably fine. Maybe a 22uF+ electrolytic in parallel for damping (select ESR ~ sqrt(L/C) or ~300mΩ).I don't see that you'd ever want/need a linear postreg for this but you can if you want, I guess. LDOs only work over the frequency range they do -- usually low (<= 10kHz ballpark); this is good for dealing with ripple at light load (burst mode operation), useless for switching noise. You will be limited by common mode noise anyway, due to the congestion of the layout and the connectors being spread out around it -- ground plane is good but it's not ideal and some mV will be dropped across the board at RF. This can be avoided by grouping connectors together, preferably extending the board length a bit, pushing the SMPS section away from the connectors, and placing the filtering inbetween.Tim

author: anotherlin
author_rank: Frequent Contributor
timestamp: December 30, 2022, 05:15:18 pm
content: The main thing I really have trouble to understand is the placement of the diodes.All layouts I've came across have them close to the switching pin of the IC. And that's also your recommandation.In particular, page 4, figure 3-e and figure 3-f, and explanations page 3:https://fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/converter_pcb_layout_appli-e.pdfI've attached a screenshot.It seems it's to reduce the spike noise due to switching, or so. But there's probably a good reason for thatAt university there was a mandatory course about electromagnetism, boring and full of tedious mathematics, which I skimmed to have passing grades. I wished I'd worked that more seriously. I'll dig that in my free timeSo I'm up for another iteration of the board layout! Because JLCPCB is so cheap (less than 4 euros for 5 pieces), I'll probably send that (bad) iteration anyway, just to see how bad it is.For the second iteration:* I'll add some EMI filtering (need to dig that subject) on the input. And add 0805 footprints parallel to input and output capacitors so a 100nF can be added.* The current board is 25.4x25.4mm (10 inches square), the original project was smaller (PDIP), I can move the feedback circuitry around and less packed. And indeed, the left bottom corner is really packed!* If there's space, maybe optional LC on outputs.Regarding the post regulation, the idea of the board is really to provide the +/- voltage. Maybe for some applications, that's just good enough. Or a LDO post-regulation is needed, I haven't think that far. Maybe first make that board work first, otherwise there's nothing to post-regulateBut that's a problem that has been addressed by manufacturers, after all DC/DC converters are the norm now. I would be considering LT3045 (positive) and LT3094 (negative), claimed to have a PSRR of 76dB at 1MHz (TPS65130 is 1.25MHz).https://www.analog.com/en/products/lt3045.htmlhttps://www.analog.com/en/products/lt3094.htmlBut again, I've a DC/DC switcher to make work first

author: Thunderer
author_rank: Regular Contributor
timestamp: December 30, 2022, 05:30:24 pm
content: Great doc the Rohm App Note. Thanks!I would not bother to add parallel footprints for bypass caps, I'd solder one on top of the other. Stack the caps, as long as they are close to the TPS pins, otherwise you need new footprints.I placed yesterday my order for the PCB @ JLC, and still had the unnecessary GND traces (as per Rohm AN) under the L1 inductor. Well, we'll give it a try.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 30, 2022, 06:06:10 pm
content: Quote from: Thunderer on December 30, 2022, 05:30:24 pmThat matters even less: ceramic cap ESL is exactly body geometry (length and aspect ratio). A cap on top is actually pretty much invisible to the circuit!Caps side by side, can resonate with each other, and their ESL and the stray inductance in the trace length between them (which is to say: it's all trace/body length, eh). The impedance of the combination has two valleys (series resonance) corresponding to each part's ESR, ESL and C, but between the valleys is a peak (parallel resonance) corresponding to the sum ESR+ESL+C* between them. If the Q factor of that resonance is high, the peak impedance can also be high -- to be exact, Q times the total ESR. So this can make the worst-case impedance (i.e. the highest impedance at any frequency within a given range) actually worse.*C in series that is (Ceq = C1 C2 / (C1 + C2)), because capacitance goes as reciprocal impedance.Better to have one cap with nominal ESR = sqrt(L/C) to dampen this. For example, tantalum, polymer*, electrolytic, or ceramic with external resistor.*Tant and poly are both available in a wide range of ESRs; shop around. Tant tend to cluster higher, and poly lower, but they have a lot of overlap. Mind the downside of electrolytic: they eventually dry up (C down, ESR up), ESR depends on temperature (it "freezes out" i.e. goes way up at low temp), and has awful tolerances to begin with. Fortunately, these kinds of damped filters are quite loose so that's not usually a problem, but it is something to be aware of.And you can always make a "lossy" high-frequency cap by using a small, low-ESR cap in parallel with a large, medium-ESR cap (or R+C). Make Cbulk >= 3C and R = ESR, with the RC time constants such that R dominates at the filter cutoff frequency, or control loop cutoff (for use with regulators). That is, Fh = 1 / (2 pi R C) should be above cutoff, and Fl = 1 / (2 pi R Cbulk) should be below.So, don't worry too much about caps in parallel, especially different values and sizes. Just make up whatever total value needed to meet low-frequency requirements, using closely spaced parts of same/similar value. If you need HF filtering, add a small inductor and filter against that.Speaking of inductors, it might be tempting to use PCB traces, at least if you happen to have some free space to do it in, but it actually really stinks. Copper is a terrible resistor so it's not even really possible to make current shunts this way, and the inductivity isn't very high without multiple turns spiraled or stacked up, and preferably using magnetic cores. Probably not a temptation on a small board like this, but just FYI.Tim

author: anotherlin
author_rank: Frequent Contributor
timestamp: January 01, 2023, 04:50:09 pm
content: Ok, I've found what I was looking for:https://youtu.be/HTywk_tlcAkSo far, this is the best explanation I've found: Give the basics/fundamentals and then everything makes sense.I mean, the tips and guidelines of appnotes sometimes sound like "black art" or experience gained after long trial and error.But that video makes them very logical.Regarding ground pour and return currents:* DC returns using the shortest geometric path;* AC returns using the least inductance path (with a GND pour on bottom layer, that's just under the trace).So it's really a good thing to have a ground pour beneath high current traces.Traces have inductance, what various documents refer to parasitic inductance. But well, they're nothing parasitic and why not just treat some traces as inductors.With high di (on-off current on some nets) and short dt (high frequency of the switcher), that's a recipe for disaster (voltage spiking).For example, taking 0.8nH/mm^2, on my 1st iteration layout, the trace between the IC pins and D2 (inverting converter's free wheeling diode) is about 12mm^2. With di = 0.5A, dt = 0.4e10-6 (supposing half duty at 1.25MHz), L = 12 *0.8 ~10nH, I should obtain a v = L * (di/dt) ~ 12.5mV. Not great, not terribleBut yes, for noise limitation, there's definitely good reason to put the diodes close to the switching pins.And as already mentioned by T3sl4co1l, inductance of traces to inductors just give them extra inductance, hence we have some more freedom in their placements.In a buck converter, the on-off current is on the input capacitors, hence most important loop, must be close to switch (IC pin). The inductor is directly connected to output capacitor and inductor has DC current + ripple on it, less important so.On a boost converter, the on-off current is on the output capacitors, so most important loop, must be close to diode. The inductor connected to input capacitors directly.Inverting converter is the worst, the inductor is never directly connected to either input or output capacitors. So both experience high di/dt (on-off) current hence both loops are critical and must be minimized.

author: anotherlin
author_rank: Frequent Contributor
timestamp: January 01, 2023, 04:53:36 pm
content: Quote from: Thunderer on December 30, 2022, 05:30:24 pmI guess the application note is rather suggesting to avoid routing beneath inductors, but GND is actually perfect because it helps the return current (according to the physical explanation).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 01, 2023, 08:04:13 pm
content: Quote from: anotherlin on January 01, 2023, 04:50:09 pmI just flipped through a couple early slides, but it looks like he's on the right track; seems alright.QuoteIt's worse than that -- at the moment of commutation (switch goes from on to off or vice versa), inductor current is flowing from VCC to inductor, then that current flow is interrupted (VCC to SW inductance is excited), and simultaneously that current begins new in the GND to SW path. The dI/dt is the same in either case, and the dI/dt at the filter-inductor side of SW is irrelevant (that current is set by the (much larger value) inductor -- its dI/dt is very slow compared to the nanosecond-scale commutation event), so we are only concerned about the dI/dt within the switching loop: VCC to GND, through the switch, diode, and bypass capacitor.Current transfers "simultaneously" because of capacitance: real switches/diodes have some capacitance, which limits dV/dt, and the instant the voltage starts moving away from one side, the displacement current (I = C dV/dt) becomes a superposition of the two capacitances sharing SW (i.e. the total from VCC to SW, plus the total from SW to GND).At the finest level of detail, note that the switch does not turn on/off instantly, but is itself a continuous process; as it begins to turn off, voltage begins to shift, and current flow begins to shift from channel current (in the case of a MOSFET switch), to charging its capacitance, to charging both capacitances, to charging mostly the opposite-side capacitance (recall that junction capacitance depends on voltage, being highest near 0V, so the current sharing shifts while the voltage swings between VCC/GND), to opposite-side conduction (catch diode, or synchronous MOSFET turning on).With typical ~1MHz regulators, this all happens in 5ns or so. So a 10nH loop might see 2A switching in 5ns or V = L dI/dt = (10n)(2) / (10n) = 2V -- which may be at the limit of the regulator itself, note the absolute maximum plus transient voltage rating of the SW pin is usually around this amount. So coming in less than this is paramount, and having the cap and diode adjacent to the chip is the best way to achieve this.Meanwhile, in 5ns, the load current has changed imperceptibly: say we have a 12V supply into a buck with 2uH filter inductance. At 1MHz, that's ballpark 6V for 500ns or delta (6)(0.5u) / (2u) = 1.5A (peak to peak ripple -- maybe this is a couple-amps DC output; or the actual peak current and pulse width are lower, operating in DCM). In 5ns, it's changed, well, 1/100th of that or 15mA -- who cares. Hence, switch loop is priority.There are, by the way, situations where this inductance is, in fact, desirable -- in that case, probably its flyback voltage (when current rises, and inevitably overshoots (due to capacitance) at turn-on, or load current is released at turn-off) needs to be absorbed with a snubber, and so the limiting condition becomes the loop between switch and snubber. Sometimes the  loop inductance can't be made as small as the snubber, so you are forced into this (example: bus bar wiring of industrial IGBT modules); other times, the inductance might be used to shift where/when switching losses occur, and to deal with high capacitance switches (especially the pseudo-capacitive effect of diode reverse recovery).There are also cases where trace impedance manifests as a mix of both L and C, or dominant C. The deciding factor is roughly the system impedance in comparison to the characteristic impedance of the trace as a transmission line. For SMPS, very nearly 100% of the time, Zsys << Zo and inductance manifests, but it can still happen that Zsys > Zo and then we might want to keep traces narrower rather than wider (to keep Zo higher). This will be on the order of 100 ohms (because it's hard to make PCB traces much higher than 150 ohms, even entirely without ground plane).A good counter-example is [well... "good" may be debatable,but...] vacuum tube circuits -- from the days of yore, these have the limitation that they're really only effective at rather high voltages (100s V up) and low currents (10s to 100s mA for common "receiving" types). So the load impedances are in the low kohms, maybe high 100s at best, and best-practices wiring is to route relatively thin wires through space, within a chassis (which ultimately serves as ground plane). Output capacitances range from single to 10s of pF, and input capacitances, 10s of pF; for bandwidth in the 10s of MHz (as you'd want for anything from a wideband or RF amplifier, to a switching circuit), the capacitance is absolutely the limiting factor. The most topical commercial application was television horizontal deflection, using a beam tetrode capable of saturating down to 50-80V, at a peak current of 1A or so; these came with a breakdown voltage around 6.6kV, so they still perform surprisingly well in general terms (if we ignore the other electrode requirements -- screen current and heater power!). They've been  eclipsed only surprisingly recently (last decade or two) by high voltage MOSFETs (something like 30 ohms Rds(on) and 4kV Vds are available as a single part).SMPS also tend to have very short length traces, so that they don't really look much like transmission lines (read: having a consistent cross-section along the length), and pins, pads and vias tend to contribute significantly to the total (i.e. a few nH here and there).Which are all points in favor of using wide traces, pours, components, and multiple vias/components in parallel, for SMPS. Vias and chip capacitors, a few in parallel can be good; switches and diodes, low-profile chip and DFN styles are good. So, as here, a chip cap, chip diode, and QFN switch work nicely together. It's probably not worth paralleling cap or diode here, but a couple vias near each ground pad can help (which is close to what the last layout was showing -- like I said, it's on the right track)....Oh hm, just to make that perfectly clear if you haven't played with transmission line impedance much as yet -- wide traces and short substrate spacings (i.e. trace to inner copper plane is preferred over trace to opposite layer) contribute roughly inversely, and proportionally, respectively.To be exact, in the case of a microstrip (flat surface trace) over ground plane, when the trace width is much much greater than the substrate spacing, and at high frequencies / assuming ideal conductors, then the specific inductance is Lo = mu_0 h / w (for height-above-substrate h, trace width w, and Lo == inductance/length, i.e. multiply by length to get total L). In general, there's a geometry factor when using formulas like these (what's basically nothing more than dimensional analysis!), but for this case that factor happens to be 1.When width is comparable, we can't ignore fringing fields, and a more complicated formula applies (geometry factor differs from 1). Here, just use the traditional microstrip formulas, then get inductance from Lo = Zo / c, where c is the speed of light*.*Actually the speed of magnetism in the medium, so to speak; we don't want to use c_0 (velocity of propagation) because that's usually reduced bu dielectric loading, but that has no impact on magnetism. Conversely if we did have a magnetically loaded medium, we'd want to divide c by sqrt(mu_r) first. (c_0 = c / sqrt(mu_r * epsilon_r) in general. Or, the uh, c/c_0 is the index of refraction in optics...exactly, isn't it?)And a similar relationship holds for capacitance, for when that's important. Note that Zo = sqrt(Lo/Co) relates the two.This is the low-frequency approximation, valid as long as the waves we're applying to the transmission line don't go through much phase angle along it (i.e., << 1/4 wave). So, for an SMPS layout some 10s of mm across, this is valid into the 100s of MHz, no problem.Oh actually, this ties in with another thread, let me backlink that then:https://www.eevblog.com/forum/beginners/high-frequency-passive-low-pass-filter-with-cheap-components/The discussion of layout is exactly the same: to construct a lumped-element (read: zero-length or infinite-speed-of-light) circuit, we must have the dimension of the circuit/elements small enough to validate that assumption.QuoteYup; by the way, note that buck and boost are identical, down to swapping the diode and switch, and load current direction. All the dynamics are identical. Or in general, we can use both switches (active rectification), and also get operation either way i.e. bidirectional source/load current -- there's no distinction between buck or boost and operation goes seamlessly between cases.For inverting: merely relabel the supplies. Instead of VCC/GND you have VIN/VOUT, and instead of VOUT off the inductor, you have GND. (Does this make it obvious why a buck converter can be used to "bootstrap" itself, making a negative supply?)So the general case is a half-bridge arrangement (two switches, from VCC-SW and SW-GND), with the critical capacitor spanning both switches (VCC-GND). The generalization also applies to explicit "bridge" types: half-bridge identically, and full-bridge is just two side-by-side. So, bypass those accordingly.Tim