Full Bridge Phase Shift on ATSAME70Q21A - Page 1
Forum section: electronics / general

author: analityk
author_rank: Regular Contributor
timestamp: December 02, 2024, 10:08:08 am
content: Hi,like in title, i have some throuble with configuration of PWM0 in SAME70Q21A uC. I asked chat gpt for help but it is not an optimal solution. He help me something but oscillograms tell me this is still far from desired shapes. Especially dead times not work and i can not change frequency or phase shift. My patience for GPT is gone, so i decide ask here.What i have on this moment:Code:pmc_enable_periph_clk(ID_PIOD);pmc_enable_periph_clk(ID_PIOC);pmc_enable_periph_clk(ID_PIOB);pmc_enable_periph_clk(ID_PIOA);pio_configure(PIOB, PIO_PERIPH_A, PIO_PB0, 0);// PWM0Hpio_configure(PIOA, PIO_PERIPH_A, PIO_PA1, 0);// PWM0Lpio_configure(PIOD, PIO_PERIPH_A, PIO_PD25, 0);// PWM1Lpio_configure(PIOD, PIO_PERIPH_A, PIO_PD21, 0);// PWM1Hpmc_enable_periph_clk(ID_PWM0);REG_PWM0_CLK = PWM_CLK_PREA(0) | PWM_CLK_DIVA(1); // CLKA = MCK / 1REG_PWM0_SCM = PWM_SCM_SYNC0 | PWM_SCM_SYNC1; // channel 0 (PWMH0/PWML0)REG_PWM0_CMR0 = PWM_CMR_CPRE_CLKA | PWM_CMR_CALG | PWM_CMR_CPOL;REG_PWM0_CPRD0 = 1000; // Period PWM (1000 cykli)REG_PWM0_CDTY0 = 500; // duty 50%REG_PWM0_DT0 = PWM_DT_DTH(100) | PWM_DT_DTL(100); // dead time// channel 1 (PWMH1/PWML1)REG_PWM0_CMR1 = PWM_CMR_CPRE_CLKA | PWM_CMR_CALG | PWM_CMR_CPOL;REG_PWM0_CPRD1 = 1000; // period PWM (1000 cycles)REG_PWM0_CDTY1 = 500; // duty 50%REG_PWM0_DT1 = PWM_DT_DTH(90) | PWM_DT_DTL(90); // dead timeREG_PWM0_ENA = 3;Pic rel for PWM's.If someone have idea how to do it in this uC please help.Second picture present project i'm working on.SincerelyEDIT:i place PWM in some shape but can't controll them:

author: analityk
author_rank: Regular Contributor
timestamp: December 02, 2024, 10:08:48 pm
content: Very funny uC...There are some library, ofc from Microchip and you can find code:Code:#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */[...]#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */#define ID_AES (56) /**< \brief AES (AES) */[...]#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */[...]#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */[...]#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */So how much TC channels do you expect? from 0 to 11? I do. Even in 144 Lead package pinout you can find for example PD21 and PD22 which one can work as TIOA11 and TIOB11. Easy ye?But i have some code:Code:pmc_enable_periph_clk(ID_PIOA);pmc_enable_periph_clk(ID_PIOD);pio_configure(PIOA, PIO_PERIPH_B, PIO_PA1, 0);// PWM0L TIOB0per bpio_configure(PIOA, PIO_PERIPH_B, PIO_PA0, 0);// PWM0LTIOA0per bpio_configure(PIOD, PIO_PERIPH_C, PIO_PD21, 0);// PWM1H (!)TIOA11 per cpio_configure(PIOD, PIO_PERIPH_C, PIO_PD22, 0);// PWM1H (!)TIOB11per cpmc_enable_periph_clk(ID_TC0);pmc_enable_periph_clk(ID_TC1);pmc_enable_periph_clk(ID_TC2);pmc_enable_periph_clk(ID_TC3); // (?)// Configure TC0 Channel 0 in waveform modeREG_TC0_CMR0 = TC_CMR_TCCLKS_TIMER_CLOCK2 | (1<<10) |// Timer clock = MCK/2TC_CMR_WAVE | // Enable waveform modeTC_CMR_WAVSEL_UP_RC | // Up mode with automatic reset on RC compareTC_CMR_ACPA_SET | // Set TIOA on RA compareTC_CMR_ACPC_CLEAR | // Clear TIOA on RC compareTC_CMR_BCPB_SET | // Set TIOB on RB compareTC_CMR_BCPC_CLEAR; // Clear TIOB on RC compare// Set RA, RB, and RC values for PWM signalREG_TC0_RA0 = 80; // TIOA high for 30% of the periodREG_TC0_RB0 = 80; // TIOB high for 70% of the periodREG_TC0_RC0 = 164; // Period of the waveform// Enable and start the TC channelREG_TC0_CCR0 = TC_CCR_CLKEN | TC_CCR_SWTRG;// Configure TC3 Channel 2 in waveform modeREG_TC3_CMR2 =TC_CMR_TCCLKS_TIMER_CLOCK2 | (2<<10) |// Timer clock = MCK/2TC_CMR_WAVE | // Enable waveform modeTC_CMR_WAVSEL_UP_RC | // Up mode with automatic reset on RC compareTC_CMR_ACPA_SET | // Set TIOA on RA compareTC_CMR_ACPC_CLEAR | // Clear TIOA on RC compareTC_CMR_BCPB_SET | // Set TIOB on RB compareTC_CMR_BCPC_CLEAR; // Clear TIOB on RC compare// Set RA, RB, and RC values for PWM signalREG_TC3_RA2 = 80; // TIOA high for 30% of the periodREG_TC3_RB2 = 80; // TIOB high for 70% of the periodREG_TC3_RC2 = 164; // Period of the waveform// Enable and start the TC channelREG_TC3_CCR2 = TC_CCR_CLKEN | TC_CCR_SWTRG;And on o-scope i see PWM for channel 0, but for 11 don't. Where is the secret?I study carefully registers summary for timer counter and what i find:There is TC_CCR0, TC_CCR1, TC_CCR2 ... but TC_CCR3 is gone.In the errata there are nothing about any problems with timer counter module.In this moment i decide to use PSoC4 for my purpose, i can obtain this PWM signals with 4 line of code.Another iritating moment is on my Xplained Board there is only TIOA0/B0 and TIOA11/B11 signals connetced to GPIO expansions. I have lost too much time.