Duty cycle limiter - Page 1
Forum section: electronics / projects

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: January 31, 2025, 06:11:34 am
content: I had a need for a duty cycle and pulse width limiting circuit. Given a PWM signal with an arbitrary pulse width and repetition time (in the kHz range), it should detect pulse widths in excess of some maximum, and also if the duty cycle exceeds a maximum. My first implementation used the timer blocks in an STM32 but I was looking for something simpler. A bit of searching led me to US patentUS4305010A, which I thought was a really neat way of doing this and thought I should share it here.A switchable constant current source and switchable constant current sink are driven by the input signal. These source or sink current into an integrator capacitor. The output of the capacitor is compared against a reference, indicating an error condition if the pulse width or duty cycle are exceeded. The source and sink currents are adjustable (R1/R2 in the attached circuit). Adjusting R1 sets the maximum pulse width at which the capacitor charges up enough to trigger the comparator. R2 sets the discharge rate, and controls the maximum duty cycle at which the comparator is triggered. The comparator output can be used to gate the PWM signal to keep it within a known pulse width and duty cycle. This is useful in various applications, such as pulsed high-power transmitters, Tesla coil drivers etc.I don't fully understand how the switched current source and sink work. Q2 and Q3 appear to act as switches, but that would add their Vce to the Vb of Q4 and Q5, on top of what D2/D5 add. Anyway, the values in my schematic are configured for a duty cycle limit of 10% and a pulse width limit of 120 us. I tested this on a breadboard, and it worked well.

author: Zero999
author_rank: Super Contributor
timestamp: January 31, 2025, 11:49:15 am
content: It doesn't look right to me. I don't have time to analyse it in great detail but shouldn't Q3 and Q4 be configured symmetrically?

author: mtwieg
author_rank: Frequent Contributor
timestamp: January 31, 2025, 02:13:39 pm
content: Neat, this circuit is basically the analog equivalent of something I've implemented in an FPGA to limit duty cycle.Basically you define an up slope and a down slope (su and sd). When input is high, a counter counts at the up slope su, and when the input is low it counts down at the down slope sd (or until it hits zero). If the duty cycle is below some threshold dthresh = sd/(su+sd), then the counter always rests to zero every period. If the duty cycle exceeds dthresh, then the counter value will count towards infinity. You set some threshold on the counter to detect when the duty cycle has gotten "too high". In your circuit, the current source values are the equivalent of the two slopes.But keep in mind this is an extremely crude method if the period of the signal is not fixed. If the period is very short, then this circuit will not allow duty cycle to briefly exceed dthresh. And for very long periods, it will act like a maximum pulse width limit (meaning the effective duty cycle limit will become smaller).In general, limiting duty cycle for a PWM with varying frequency is an ill-defined problem. So you have to make some sort of compromise based on your specific application.

author: youngda9
author_rank: Regular Contributor
timestamp: January 31, 2025, 02:50:49 pm
content: I whipped up a simple circuit using a comparator. Shown switching at 100KHz, 50% duty-cycle into the circuit.Use the V(Compout) net connected to a transistor to pull up on the current sense feedback net of the PWM to terminate the duty-cycle for each pulse.I would suggest tighter tolerance parts throughout this circuitry to reduce threshold variation.

author: youngda9
author_rank: Regular Contributor
timestamp: January 31, 2025, 04:32:10 pm
content: Here is a better solution. Front-end changed to a constant current source that resets to 0V when the duty-cycle V(Vpulse) goes low. This will have much less variation.Connect CompOut to a transistor pulling up on the current sense feedback to initiate cycle-by-cycle current limiting....to terminate the pulse input (which represents the PWM output signal). Circuit at the bottom RH corner of the schematic mimics what this would do to the duty-cycle.

author: Zero999
author_rank: Super Contributor
timestamp: February 02, 2025, 12:43:16 pm
content: Are we talking about maximum pulse length or duty cycle?The circuit attached to the original post behaves the same over a range of frequencies, whist subsequent circuits just look at the pulse duration.

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: February 02, 2025, 06:47:45 pm
content: Quote from: Zero999 on January 31, 2025, 11:49:15 amWhy Q3/Q4? Q4/Q5 form the current sink/source respectively, and R1/R2 set the charge and discharge rates. These are asymmetric because the duty cycle/pulse width I wish to limit to is 10%. They would be symmetric if the duty cycle limit was closer to 50%.Quote from: mtwieg on January 31, 2025, 02:13:39 pmTrue, it is crude, but it is meant to complement a digital implementation. The digital implementation is not available when the micro (in my case) or FPGA is being reflashed, for example. During this time, it may be possible to drive a trigger with too high a duty cycle into a sensitive device. It had happened to me, hence my interest in a method to mitigate it. The analog implementation is a last ditch method to catch such a condition and clamp it, so the duty cycle limits would be set to be a bit higher than the digital implementation.Also, I understood your first statement about the behavior for short periods, but not the one about the duty cycle limit getting smaller for larger periods - could you elaborate?Quote from: mtwieg on January 31, 2025, 02:13:39 pmHmm - this is what my application looks like under some operating modes. One mode that a radar transmitter could be in is called 'staggered PRF' where the radar transmits blocks of pulses at different PRFs. I suppose I should simulate this or test it out on my breadboard.Quote from: Zero999 on February 02, 2025, 12:43:16 pmLooks like what@youngda9posted only responds to the pulse width, it's the same as the top half of the design I posted. The first one charges the cap with a constant voltage, and it shows up in the trace for Vcap - it charges exponentially. The second one charges linearly due to the constant current supply. It does remind me that I should add hysteresis to the comparator.An interesting behavior I observed from the breadboard is that the circuit responds differently to over-duty vs over-pulse width. The over-duty case causes the capacitor voltage to rise up till it hits the compliance limit of the constant current source. It then takes a short while to drop back down once the over-duty condition is removed. The excess pulse width condition does not cause this 'latching' behavior, the comparator output goes high for the width of the input pulse, then drops back down a short while after. If the input pulse is gated with the inverse of the comparator, it can be used as a 'protected' trigger whose pulse width cannot exceed some maximum.

author: mtwieg
author_rank: Frequent Contributor
timestamp: February 02, 2025, 11:36:31 pm
content: Quote from: radar_macgyver on February 02, 2025, 06:47:45 pmFor your circuit, the value of C1 is 0.5uF, the threshold of the comparator is ~2.4V, and the charging current is ~1.15mA. That means any single pulse longer than 1ms will trip the threshold. So for a period of T=10ms the max duty cycle is 10%, for T=100ms the limit is 1%, for T=1s the limit is 0.1%, etc.Actually for this circuit Q4 will only discharge down to around 2V, so the limits are actually much lower, but you get the point.Quote from: radar_macgyver on February 02, 2025, 06:47:45 pmNot sure what difference you're referring to. In both cases the comparator output will stay high for some time after the input pulse has gone low. The duration it stays high just depends on how high the voltage on C1 reached during the previous pulse.

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: February 03, 2025, 04:06:32 am
content: Quote from: mtwieg on February 02, 2025, 11:36:31 pmThat's the expected behavior - it's supposed to limit both the max pulse width as well as duty cycle. The purpose is to protect a pulsed RF amplifier from being triggered on for too long, or to exceed its rated duty cycle. In an application to limit just the duty cycle, yes, that would be a limitation.