Low jitter 100kHz oscillator for A/D - Page 1
Forum section: electronics / projects

author: floobydust
author_rank: Super Contributor
timestamp: September 17, 2017, 08:27:14 pm
content: I have this 100kHz crystal oscillator clocking a dual-slope A/DICL7135.Low jitter and phase noise are important, but exact frequency is not.I'm wondering why no Schmitt trigger (gate) is used.Other oscillators typically used are RC (Schmitt) types, or LM311 comparator.What is oscillator design is better for low jitter?

author: Benta
author_rank: Super Contributor
timestamp: September 17, 2017, 08:45:48 pm
content: Your 4011 oscillator is biased to run as a semi-linear inverter, which works well for XCOs. Crystals don't like Schmitt-triggers at all.In this case it depends on the rest of the circuit, which can not be seen. It might be followed by a Schmitt trigger somewhere.

author: danadak
author_rank: Super Contributor
timestamp: September 17, 2017, 10:41:15 pm
content: You might want to look at phase noise with a spectrum analyzer.I find it hard to believe a CMOS gate on a digital supply rail would yield a lowphase noise design. Of course you have not disclosed what you mean, a spec,for phase noise goal. The gate has no appreciable rejection to rail noise, theinput to gate HiZ, thereby susceptible to external noise coupling.....Regards, Dana.

author: David Hess
author_rank: Super Contributor
timestamp: September 17, 2017, 11:51:50 pm
content: A dual slope ADC like the ICL7135 does not require a clock source with particularly good phase noise. Even an LC oscillator may be adequate.High gain digital gates and especially schmitt triggers are pretty poor as far as noise. Comparators and unbuffered gates do better. Single transistors followed by a gate or comparator do better yet.

author: floobydust
author_rank: Super Contributor
timestamp: September 18, 2017, 03:07:05 am
content: The 7135 datasheets (Intersil, TI, Maxim, Microchip, Teledyne) have no clock requirement spec:"The clock source should be free of short-term phase and frequency jitter during the conversion period, but long term stability is not critical.""The clock used should be free from significant phase or frequency jitter."There's four different oscillator types in the datasheets- comparator or logic gate and xtal or RC.I see Pierce oscillators with Schmitt triggers or buffered or unbuffered CMOS logic gates.I couldn't anything on oscillator design wrt jitter and phase noise, well it's an issue in the RF domain.You have a sine-wave and at some point need to convert to digital.For low jitter, I imagine you want consistent switching thresholds- so a clean power supply, low noise stable threshold detection and some hysteresis?Schmitt triggers give a fast-edge but threshold voltages are imprecise, and David you say noise is poor.Just trying to understand the oscillator side before looking at what the A/D needs.

author: David Hess
author_rank: Super Contributor
timestamp: September 18, 2017, 10:41:22 am
content: Quote from: floobydust on September 18, 2017, 03:07:05 amThey do not specify it but you could calculate the requirements based on how the dual slope conversion works.QuoteI happen to know first hand that RC oscillators are not good enough for 20,000 count dual slope conversion and will result in errors in the least significant digit which look like flicker noise. The higher Q of an LC oscillator prevents this problem.QuoteThere are some other considerations as well having to do more with reliability than noise. Buffered logic has excessive gain making it more prone to spurious oscillation. For this reason crystal oscillators made using TTL gates often used the slower and lower power TTL families. Unbuffered CMOS tends to have more problems operating at the lower end of its temperature range and this crops up sometimes with CMOS logic which has a built in oscillator section.QuoteThis is a problem with digital logic in general. Input threshold voltages and the output voltages follow the ground and power levels. A comparator with its differential input at least may have a stable threshold voltage.QuoteDual slope conversion really is not that picky so unless the crystal oscillator is malfunctioning, any of the various crystal oscillator designs will work and it becomes more of a matter of reliability. If you are designing for production, then the design should be tested for operating margin and this is where the single transistor oscillator has a real advantage.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 18, 2017, 04:01:49 pm
content: A dual slope ADC is not that demanding on the oscillator. Even a good RC oscillator can work - it would some kind of shielding and the simple 74HC14 based RC might not be good enough, a cmos 555 timer should be sufficient. A LC or crystal version might still be the easier option - though 100 kHz crystals tend to be expensive due to low demand. So I would prefer a higher frequency (e.g. 3.2 or 6.4 MHz) crystal / ceramic resonator and a divider like the 74HC4060 if exactly 100 kHz are needed (to get good 50/60 Hz suppression).

author: floobydust
author_rank: Super Contributor
timestamp: September 18, 2017, 04:23:02 pm
content: I'll stay with the crystal for high-Q and CD4011B. This is for mods to an existing product to increase from 100kHz to 120-200kHz;Epson149kHz and 192kHz crystals exist.With a scope (persistence) I can see about 30nsec wander, which seems insignificant at 100kHz and the 10,000 clock cycles integration time/20,001 count de-integration time.Not sure if clock noise would cancel in the dual-slope ; the two periods are not equal.TheLM311comparator osc. (crystal) version references VDD, has hysteresis so I don't see it being much better than a Schmitt trigger gate- but the comparator is relatively slow 165nsec and this is desirable for stability, if I understand David correctly.Added attachments missed from my previous post.

author: Benta
author_rank: Super Contributor
timestamp: September 18, 2017, 05:28:16 pm
content: QuoteThat's fine, but I'd go for a 4011UB for the oscillator.