2.7pF feedback capacitor -- sign of overly sensitive design, or perfectly fine? - Page 1
Forum section: electronics / projects

author: rs20
author_rank: Super Contributor
timestamp: July 26, 2015, 06:59:01 am
content: I'm just designing this dummy load in simulation, and I've arrived at this solution which looks alright:However, the design is not stable with the feedback/integration capacitor (C1) absent -- but a value of just 2.7pF gives it the ~60 degrees phase margin that we all know and love. This concerns me because 2.7pF is a kinda tiny value, getting close to the parasitic capacitances on FR4 board. I know I should "just try it", but am I begging for trouble with this design? If you arrived at this design yourself, would you just run with it, or use some technique to make those nodes less susceptible to parasitic capacitance? Placing capacitors in parallel to R3-R6, and increasing C1 seems like a vaguely reasonable idea, but is that a waste of 4 components?Preempting some questions:"Why not just reduce R3 thru R6, and increase C1?" There will be circumstances where U2 is not powered, but voltage will be applied to the DUT connection. So I don't want so much current flowing through R5, R6 and through U2's ESD protection diodes that U2 (and the rest of the circuit) starts getting sort-of powered-on. Also, current flowing through R5 detracts from the accuracy of the current measurement by R1."Why use a BJT? Why use PNP rather than NPN? Why is the sense resistor not connected to ground?" I've heard that BJTs are better at being linear, I don't need to go down below 1V (this is a very special purpose dummy load), and I want the tab of my power device to be connected to ground for easy heatsinking.EDIT: Fixed broken image link.

author: German_EE
author_rank: Super Contributor
timestamp: July 26, 2015, 08:49:07 am
content: This is a situation which I have come across before but in another piece of equipment, an amateur radio receiver. This design used a large number of op amps and each of them had a 10K resistor with a 100pF capacitor in parallel as the feedback element. All of the amplifiers were used at audio frequencies but if the 100pF capacitors were removed there were various stability problems including oscillation. 2,7pF is probably a minimum value and unless you want to work at RF I would put in something larger, say 10pF, and see if everything is stable.I leave the answers to your other questions to those who are better skilled in circuit design.

author: rs20
author_rank: Super Contributor
timestamp: July 26, 2015, 09:11:06 am
content: Quote from: German_EE on July 26, 2015, 08:49:07 amThanks for your response! I'm certainly not working with RF, but a value of 10pF brings the phase margin to 92 degrees. Very stable indeed, but with the predictably lazy transient response that goes with that. So yeah, what I'm trying to get a sense of is whether such sensitivity is frowned upon in knowledgeable circles. It's interesting you mention RF, I imagine a 2.7pF shunt will quite effectively ruin many RF circuits, so maybe it's not so crazy.

author: nctnico
author_rank: Super Contributor
timestamp: July 26, 2015, 09:38:02 am
content: I think you better put a series resistor between the opamp and the gate of the mosfet. 2.7pf tells you this circuit won't work in the real world.

author: rs20
author_rank: Super Contributor
timestamp: July 26, 2015, 10:00:30 am
content: I added a 1 kiloohm resistor between the opamp output and the gate; and consequently I needed to increase the feedback capacitor from 2.7pF to 6pF to get my 60 degree phase margin back. I'm assuming this isn't a particularly significant change? Or does this bring it into "working in the real world" range?When you say "2.7pf tells you this circuit won't work in the real world", how specifically would it fail in the real world? Self-oscillation?

author: Zero999
author_rank: Super Contributor
timestamp: July 26, 2015, 10:09:24 am
content: Adding a series resistor between the op-amp's output and MOSFET gate is a good idea because the op-amp will probably oscillate when driving a very capacitive load, such as a MOSFET gate. Unfortunately the resistor will slow things down and add more lag which is why the compensation capacitor needed to be increased, in order to keep it stable. You could probably reduce the gate resistor to something like 100R if you want better transient response.How many units do you tend to build? Playing around in LTSPICE is good but it's a good idea to build a prototype, especially if you want to make a large quantity.

author: dom0
author_rank: Super Contributor
timestamp: July 26, 2015, 10:10:30 am
content: Marginal phase margin (no pun intended) usually gives oscillations without completely breaking the loop, i.e. the loop amplifier oscillates around the operating point, often with decaying oscillations after input steps.The 1k between the opamp output and the gate give you a (non-linear) RC circuit, adds the associated pole to the overall transfer function and gives the associated phase shift. With small FETs and their small capacitances it usually doesn't matter, but can improve step response a bit if a local feedback cap is used.AC simulations are fair enough, but they are based on the assumption that the circuit operates linear with the given input signals to the DC operating point, which is almost always the case for amplifiers, and only true, say, half of the time for regulators. YMMV.

author: nctnico
author_rank: Super Contributor
timestamp: July 26, 2015, 10:12:40 am
content: Parasitic capacitances are in the pf range so there are likely more capacitances in this range connected to the opamp in a real world circuit.

author: tggzzz
author_rank: Super Contributor
timestamp: July 26, 2015, 10:23:58 am
content: Your circuit diagram is drawn in a way that suggests you are using the op-amp as a comparator. If that isn't the case, then it would help if you would draw it in a more standard way so that theintendedmode of operation is apparent.If you are using an opamp as a comparator: don't!The capacitor can only prevent oscillation in conjunction with other components, e.g. passives, parasitics or the opamp itself. Some of those componets have poorly-defined characteristics, so the damping factor would be poorly-defined and widely variable in practice.

author: rs20
author_rank: Super Contributor
timestamp: July 26, 2015, 10:25:48 am
content: Thanks all!Quote from: dom0 on July 26, 2015, 10:10:30 amWhat do you mean by local feedback cap? My C1, the 2.7pF under discussion? Or a feedback cap from the drain or source of the FET?Quote from: dom0 on July 26, 2015, 10:10:30 amYeah, good tip. I have been cross-referencing AC analysis with DC transients; and it seems like AC analysis is work well for my circuit -- the overshoot of the transient matches the phase margin of the AC analysis as expected.Quote from: Hero999 on July 26, 2015, 10:09:24 amI'm just building one or two units, this is just messing around. I will do a prototype (a version 1, basically), but I want to maximise my chances of getting v1 right! Although it's slower than it can be, my circuit behaves perfectly acceptably at 22pF and more, so perhaps I should just build the circuit in real life, and reduce the value until it starts misbehaving.

author: rs20
author_rank: Super Contributor
timestamp: July 26, 2015, 10:28:47 am
content: Quote from: tggzzz on July 26, 2015, 10:23:58 amIt's not a comparator, it's an opamp that's holding the voltage across the sense resistor (R1) equal to Vctrl. I will try to find some similar circuits on the intertubes so that I can draw it in a more standard way.

author: rs20
author_rank: Super Contributor
timestamp: July 26, 2015, 11:28:07 am
content: Updated schematic, now with a 8.2pF and still with a approx. 60 degree phase margin below. Other changes from my original post include the addition of R7, the gate resistor for the mosfet; and I've decreased the source resistor (R2) to increase the open loop gain and allow further increase of C1 to 8.2pF.Quote from: tggzzz on July 26, 2015, 10:23:58 amSo, I had a look around and couldn't find any similar topologies, so I don't know what a more standard way of drawing it would be. I've slightly rearranged things below, on the off chance that it helps. If it helps, the feedback is inverted bythe PNP[EDIT: the common source amplifier], so the loop feedback goes to the non-inverting input of the opamp, which I suppose is unusual. As the control input (Vctrl) increases, the opamp increases the current through Rsense to keep the non-inverting input at 2.5V via R6. Also, the capacitor (whichisworking in conjunction with the 50 kiloohm impedance of the R3/R5 node) forms your classic integrator arrangement, which is pretty op-ampy.EDIT: Fixed broken image link.

author: dom0
author_rank: Super Contributor
timestamp: July 26, 2015, 11:30:12 am
content: The comment is wrong. The common-collector amplifier is not inverting, the common-source amplifier, however, inverts the loop.I'd recommend giving Q1 some BE resistance.What's the drain current of M1? As it only sees Iload / beta I suspect it's low, so R2 probably doesn't do much in terms of source degeneration. Maybe try a higher value bypassed by some nF.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 26, 2015, 11:44:53 am
content: The small capacitor is not that unusual. It's just unusual to have it with 100 K resistors. It's OK it the other parts are simulated correct, thus inclusing parasitic capacitance for the resistors and input capacitance of the OP-amp.In this circuit also take care of the parasitic inductance of the shunt - try a few 100 nH. This may reduce the phase marging somewhat. Wireing to the power transistor can do the same. So carefull with lose wires to a transistor on an external heat sink.

author: rs20
author_rank: Super Contributor
timestamp: July 26, 2015, 12:52:26 pm
content: Quote from: dom0 on July 26, 2015, 11:30:12 amThanks, fixed.Quote from: dom0 on July 26, 2015, 11:30:12 amWhat does adding BE resistance achieve? In my simplistic mind, it just moves heat from Q1 to M1?Quote from: dom0 on July 26, 2015, 11:30:12 amDrain current is at most 45mA. R2 must therefore be less than approximately 50 ohms or else Iload can't reach the target of 3A. I tried some other resistor values, 22, 33 ohms etc, with and without some nF in parallel -- I liked the idea of adding some nF in parallel to sharpen up the AC loop response, but it actually made the transient performance (settling time, etc) more sluggish in practice. I'm not really qualified to say this, but I think it just spoils the "dominant pole compensation" I've got going with my 8.2pF capacitor.Quote from: Kleinstein on July 26, 2015, 11:44:53 amThanks, I threw in a few hundred nH, and it made the response more sluggish, but still perfectly stable. In the process of messing around, I've added all sorts of parasitic capacitances around the place and I can always bring it to stability by changing C1. My design has the transistor mounted directly to the PCB, so loose wires won't be a concernI think I will go ahead with prototyping this. It may turn out that a 2.7 or 8.2pF capacitor is not stable in real life, but it very much looks like I'll be able to make it stable in real life with at most 22pF or so. Thanks everyone for your input!

author: German_EE
author_rank: Super Contributor
timestamp: July 26, 2015, 01:44:51 pm
content: We're now seeing the difference between modern electronics and the methods I used at university. If rs20 wants to try a circuit he fires up the PC and loads a simulator, if I wanted to try something out I grab a handful of components and the breadboard (or a scrap sheet of PCB if it's at RF) then fire up the scope. It's fun seeing if a circuit works by actually building it because once in a while they bite back and you suddenly find that your dream audio project is actually a 3 MHz oscillator. I know that Dave prefers to build a circuit using real hardware but how about Dave 2 and the rest of you?

author: rs20
author_rank: Super Contributor
timestamp: July 26, 2015, 01:51:51 pm
content: Quote from: German_EE on July 26, 2015, 01:44:51 pmI have neither a 8.2pF capacitor, nor a 330mR resistor, nor a signal generator in real life -- but I do in the simulator!

author: Kleinstein
author_rank: Super Contributor
timestamp: July 26, 2015, 01:56:11 pm
content: I also like to build circuits in real life. You don't forget the smell of a burned transistor as fast as a curve from Spice.But I also like trying a curcuit in the virtuel word first - the scope is much better there. Also one can do analysis like loop gain or in/out impedance much better than in real like.With the simulation you have to be carefull if the models are realistc and parasitic effects are to large. So this exactly the initial question - the simulation looks very good, but will the real circuit be the same ?So finally you have to do the real thing.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: July 26, 2015, 02:15:23 pm
content: Hi group,I see a couple of potential problems with this approach:1) The 100K resistors need to very well matched. You need very good common mode rejection to level shift the small voltage across the current sense resistor. Try making one of the resistors 99K and see what happens.2) If the input voltage is greater than 10V, the op-amps common mode voltage range will be exceeded.Have a look at this thread, I presented a detailed analysis of a dynamic load:https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/Regards,Jay_Diddy_B

author: rs20
author_rank: Super Contributor
timestamp: July 26, 2015, 02:25:34 pm
content: Quote from: Jay_Diddy_B on July 26, 2015, 02:15:23 pm1) Yes, I was playing around with 0.05% ratio tolerance matched arrays in the simulation. A bit over the top, I know, but hey, I like playing with shiny things. I also have an ADC recording the load voltage, so as long as thing aren't too far out of kilter I can calibrate in software. The software can't calibrate for the load consuming some current even when the control voltage to the opamp is 0.000V, but I've checked that worst case minimum load current and I'm OK with that too.2) My particular special use-case uses a load voltage of 6V max, so I'm OK with this as well.Quote from: Jay_Diddy_B on July 26, 2015, 02:15:23 pmI will certainly do so (but tomorrow, it's past midnight), thank you!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 26, 2015, 03:57:53 pm
content: The amp's fT is in the 20MHz range, so this should not be surprising.You should probably use a much slower amp (3MHz or less?), and some gate resistance (like the 1k suggested above), and a larger feedback cap (10s to 100pF?), to improve stability for arbitrary loads. Assuming your load characteristic does not need to be a fantastically fast current sink.Note that, for a differential amplifier configuration, a feedback cap acts in parallel with the feedback resistor; one should also be used in parallel with the "+in to GND" resistor for symmetry. Lack of symmetry means poor CMRR. In this case, just because you don't have the feedback resistor (because you want high open-loop gain), doesn't mean the capacitor goes away; you still need the balanced capacitor action.Note that, with equal divider resistors, the output compliance won't be above 10V (for supplies as shown). Unpredictable things may happen when Vcm is exceeded (like the op-amp saturates and your current draw goes cuckoo, which is a bit of a problem, when your load transistors arecompletely unlimited in current draw capability).BJTs are undesirable as load dump components because they exhibit 2nd breakdown much earlier than other types. Preferably, "linear" MOSFETs, or just dumb old resistors, should be used. This doesn't matter much at 5V, where the power density is still low, but will matter in the 50V+ range, and is critical in the 100s of V range.Linearity matters zero, because the op-amp has orders of magnitude higher than the pass transistor(s).Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: July 26, 2015, 04:22:15 pm
content: Having a relatively fast OP-amp and sufficient lokal HF feedback is not that bad. This somewhat behaves like a slower Op-amp, but with better phase reserve than many slow op amps. In addition one can have better CMR.Still it's better to have the shunt on the GND side.Using MOSFETs instead of BJT does not really help again 2nd breakdown. In MOSFETs there is also a similar limitation - it just has a different name. Its rather difficult to find MOSFETs specified for linear operation - most types are not specified. There are many BJTs specified for high power even at 100 V. One real advantiage of MOSFETs is that they often can survive spikes of high voltage.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 26, 2015, 04:52:31 pm
content: Quote from: Kleinstein on July 26, 2015, 04:22:15 pmWe went through this in the other thread;MOSFETs do still suffer from 2nd breakdown.The power density is lower, so the effect is less of a problem than for BJTs.They can be made with a low enough power density, or such a construction so that they don't suffer from 2nd breakdown within their rated SOA.Which is why I emphasized "linear" rated MOSFETs for the task.Tim

author: rs20
author_rank: Super Contributor
timestamp: July 27, 2015, 12:59:45 am
content: Quote from: T3sl4co1l on July 26, 2015, 03:57:53 pmI tried out the LT1001, which has a GBW of 0.8MHz, and got the following results:Part + feedback cap P.M. Response time (5%-to-95% output in response to ctrl input step)LT1001 + 4pF 60° 3.9µsLTC6240 + 5.3pF 60°1.1µsLTC6240 + 11pF87°3.9µsNow the conclusion I draw from this is not "I should avoid a faster opamp like the LTC6240"; instead I think "Ishoulduse the LTC6240; and not be so obsessed with getting the phase margin to beexactly60 degrees, but instead get it to beat least60 degrees and work based on transient response times beyond that point." Because the tradeoff curve between phase margin and response time is better for the LTC6240. But maybe the LT1001 is a bad choice? Please to tell me if I'm making some bad leap of logic here.Edit: as I mention below, the analysis above is completely ignorant w.r.t. response time to DUT voltage steps, as opposed to control input steps. This is something I should fix.Quote from: T3sl4co1l on July 26, 2015, 03:57:53 pmGood point, thanks, I hadn't considered this. I think adding a capacitor in parallel to R4 ("+in to control input") has the desired effect of restoring CMRR, and has the interesting additional effect of giving some HF emphasis to the control input, which (excessively) sharpens up the response of the loop to changes in control input. I evidently need to try stepping my DUT voltage (which would undoubtedly have exposed my poor CMRR), and not just focus on stepping the control input.Regarding the use of a BJT, and the inability to handle load voltages above 10V, these are both fine for me because my DUTs won't put out more than 6 volts. I'm inside the SOA of the transistor, so I think I'll be OK, although I fully concede that the versatility of my particular design is massively impacted by these design choices. This is a single-purpose load though, so it's OK. In a more general context, I echo Kleinstein's point that "linear-rated"/lateral MOSFETs are hard to find, unless I'm just missing some good keywords or popular part numbers.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: July 27, 2015, 02:47:03 am
content: Hi,I have done a little modelling to explore the effect of lead inductance in your load. The first model generates Bode plots of the control loop, while stepping the value of the lead inductance:These are the results:The AC analysis predicts instability.Transient modelThe model was modified to perform transient analysis:This is the step for the lead inductance = 0.5uH, this is unstable:I have attached a zip file with my models.Hardware test - another design.I while ago I made a fast, lower current version of my Dynamic Load. These are measurements from the hardware. In both these waveforms the red trace is the current measured with a Tektronix TCP202 50 MHz DC current probe. The Blue trace is measured across the current sense resistor. The current is being stepped from 1A to 2A and 2A to 1A.I have lost the schematic for this load. But I will recreate it in the next few days.Regards,Jay_Diddy_B

author: BravoV
author_rank: Super Contributor
timestamp: July 27, 2015, 03:02:58 am
content: Quote from: Jay_Diddy_B on July 27, 2015, 02:47:03 am

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: July 27, 2015, 03:19:08 am
content: Hi,I have done a little more modelling with a modified version of the load proposed by RS20. I have re-arranged the circuit. The re-arrangement helps a lot. It removes the need for matched resistors. It also has better stability with lead inductance.Here is the modified schematic:And the Bode plots with different values of lead inductance:This is the transient response with 1uH of lead inductance:I can go one step further an add an RC network, I did not calculate the RC network, so there may be better values.This is the transient response while stepping the lead inductance:I have attached the zip file with the modified models.Regards,Jay_Diddy_B

author: rs20
author_rank: Super Contributor
timestamp: July 27, 2015, 03:56:17 am
content: Hi Jay_Diddy_B,Thanks for your considerable efforts in helping me out with this, I've been at work/sleeping so I have a lot of catching up to do! However, I'll note that due to space constraints, I'd like the tab (collector) of the power element to be connected directly to ground, as I'm working under very tight space constraints (6.2mm total end product thickness). Obviously this is a costly restriction, as it does indeed introduce the need for those matched resistors (or other additional complication/circuitry), and quite possibly makes getting a stable loop more difficult.Also, at this stage, I'd like to stubbornly forge ahead with the high side sense resistor, if only as an educational experience.I'll also note that your first Bode plot for the high sense resistor case ("Effect of lead inductance") looks wacky, only 13 dB open loop gain at 10 Hz? That's nowhere near right; I suspect your DC conditions are off there. Nevertheless, I have no doubt that the circuit is indeed unstable with the addition of that inductance; but I'd like to experiment with increasing C1, adding capacitance across the DUT terminals, etc etc before compromising on the placement of the sense resistor. But as I said, hold tight, you're way ahead of me at the moment!

author: TheMG
author_rank: Frequent Contributor
timestamp: July 27, 2015, 04:59:41 am
content: Quote from: German_EE on July 26, 2015, 01:44:51 pmI usually start with a pen and paper, drawing up a rough schematic. Then out comes the breadboard and I start whacking in some components and fire it up. Once it's working on the breadboard and all the bugs are sorted out, on to the PCB stage.I actually designed my first programmable load (just a small 50W unit) that way. I found it was oscillating a bit at certain load currents. No problem, chuck in a small value resistor on the MOSFET gate - no more oscillations. Actually given the information I've learned recently on using switching FETs at high DC power dissipation levels, that's one heck of a tough little IRFZ44N in that load! I've loaded that thing up to full 50W for prolonged amounts of time on many occasions. Tc= about 80C. Yikes! Tough little transistor that one!

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: July 27, 2015, 09:11:08 am
content: Hi,Quote from: rs20 on July 27, 2015, 03:56:17 amI moved the disturbance source to this location:I get this result which makes a lot of sense:Jay_Diddy_B

author: rs20
author_rank: Super Contributor
timestamp: July 27, 2015, 09:34:10 am
content: Hi Jay_Diddy_B,A couple of observation about your reconstruction of my circuit:A) Following T3sl4co1l's advice of adding a matching (2.7pF) capacitor in parallel with R7 makes the transient response stable, albeit a bit overshooty. Raising the value of the caps to 6.8pF makes it nearly ideal, and it functions perfectly stably (but obviously increasingly slowly) up to 1000pF and beyond. So the topology seems fine, apart from the resistor matching issue.B) [I forgot to hit send earlier, you've figured this out in parallel] Once you decouple FB+ from being mathematically equal to 5V, an AC signal can travel through FB+. This renders the open loop bode plot analysis invalid, because we haven't cut the loop properly.Illustration of point (A), with both control and load steps in quadrature (note the timescale, risetimes of under 10us -- I look forward to seeing how true this turns out to be in real life! Not betting any money on it...)Thanks for the link to your thread, I'll look into those MEAS statements one day!EDIT: Fixed broken image link.

author: MagicSmoker
author_rank: Super Contributor
timestamp: July 27, 2015, 11:43:40 am
content: Quote from: rs20 on July 27, 2015, 03:56:17 amYou might want to consider using a dedicated "high side current sense" IC (e.g. - ZXCT1009 in a SOT23 package for ~0.90USD) to translate the sense resistor voltage down to ground-referred. Then you won't have to task the op-amp with being a difference amplifier and a gain stage at the same time (with all the woes that result from real-world mismatch in resistances leading to terrible CMRR).

author: rs20
author_rank: Super Contributor
timestamp: July 27, 2015, 12:11:33 pm
content: Quote from: MagicSmoker on July 27, 2015, 11:43:40 amThanks, that's a cool little part, I wasn't aware of that as an analog device. I'll be sure to make use of it in the future. As for this project I've figured that by usingthis resistor array(which yes, is more expensive than the part you just cited), and factoring in the 325uV max offset voltage, and the bias current (negligible, even at 50 kiloohm impedance seen from the amp inputs) of the LTC6240 I'll get +/- 9mA error on my 3A full scale, which is +/- 0.3% FS. Not brilliant, but easily within my requirements (and software calibration can take me even further). For comparison, the current sense part you referenced is 1% on its own -- as I say, still a cool part, I'm definitely noting it down and thank you for showing me; but there are resistor arrays out there that can reign in the CMRR of this circuit very well.EDIT: It's also interesting to note that while many people (not you, MagicSmoker) are suggesting to "flip the load side", i.e., bring the current sense resistor down to ground; no-one is suggesting to "flip the control side". If I was super-keen to get rid of the resistor array, I'd be considering making my control input positive-rail-referenced -- basically, make the top rail ground and the bottom rail V-. It doesn't work for my particular use case (the DUT isn't isolated), but in general, there's nothing magical about positive voltages... you can flip theentirecircuit upside down and keep the topology identical.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: July 27, 2015, 12:35:10 pm
content: Quote from: MagicSmoker on July 27, 2015, 11:43:40 amThe challenge with parts like the ZXCT1009, is that they need a minimum voltage to work. In the case of the ZXCT1009 the minimum voltage is 2.5V. Below to 2.5V you don't get any feedback signal.Jay_Diddy_B

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 27, 2015, 01:16:11 pm
content: Most current sense amps aren't terrifically accurate, either; likewise, the resistor divider depends on accurate resistors, but as long as you don't mind the (actually pretty small) cost premium for 0.1% resistors (or better), that's fine.How fast does this thing need to go? I assumed DC load, so that it could be dreadfully slow and still meet spec. Do you have some idea in mind for how fast it should be? Or a target output impedance at some frequency?e.g., if you're CC-loading an SMPS with noticeable ripple, it might be desirable to have a high impedance at f_ripple, or at least a reactive (preferably inductive) impedance, so it loads it the least, and/or has the least interaction with respect to additional lead inductance and etc.Note that your choice of an emitter follower will tend towards a low impedance, even with the MOSFET driver in there.Another question: are the supply and load isolated, or must they share a common ground?Tim

author: MagicSmoker
author_rank: Super Contributor
timestamp: July 27, 2015, 09:33:29 pm
content: Quote from: Jay_Diddy_B on July 27, 2015, 12:35:10 pmYep, a fair point, and that also means the maximum source voltage to the current sink is limited, too (but that may not be the ultimate limiting factor here).Quote from: T3sl4co1l on July 27, 2015, 01:16:11 pmRight, but degraded CMRR from even a 0.1% mismatch in the ratio of the dividers feeding a single op-amp diff-amp could result in a much worse error, especially if the diff amp is run at unity gain and/or the burden voltage across the current sink (ie - the voltage of the source-under-test, which is effectively the common mode voltage as the drop across the sense resistor will  be very small) is greater than 10V or so.See, for example, the handy calculator here:http://masteringelectronicsdesign.com/differential-amplifier-output-common-mode-voltage-calculator/Quote from: T3sl4co1l on July 27, 2015, 01:16:11 pmYes, good advice! You'd be surprised how many practicing EE's forget that you need to decouple a constant current source/sink with inductance just as you decouple a constant voltage source/sink with capacitance.

author: MagicSmoker
author_rank: Super Contributor
timestamp: July 27, 2015, 09:39:44 pm
content: Quote from: rs20 on July 27, 2015, 12:11:33 pmYep, while the absolute accuracy of the resistors in an array might be terrible, the relative accuracy as well as tempco will be excellent - unmatched by anything else, really. And as you correctly noted, that will do wonders for the CMRR.Quote from: rs20 on July 27, 2015, 12:11:33 pmNo, you can lump me in with the rest: ever since ECL (and Germanium!) went out of fashion the modern EE rarely comes across positive ground circuits!

author: dom0
author_rank: Super Contributor
timestamp: July 27, 2015, 09:51:11 pm
content: Most people also seem to have great trouble understanding current-mode circuits... (just while we're at it)

author: rs20
author_rank: Super Contributor
timestamp: July 28, 2015, 06:54:28 am
content: I'm afraid to reveal what the actual "purpose" of this circuit is, given the remarkable amount of vitriol and snarkiness delivered to a recent thread about USB chargers. Nevertheless, the purpose of this project is 40% having fun building control loops, 40% having fun constructing physically small devices (6mm total thickness) with good heatsinking and unusual/interesting construction techniques, and (takes a big breath) 20% developing V/I curves for USB chargers as and other USB ports.So the idea is that the dummy load will step through a ramp (/staircase) of different current values, and an ADC will track the DUT's voltage and thereby develop the V/I curve. So, I don't require infinite impedance or extraordinary dynamic performance, since for every current setting I'll have to make it sit back and allow the USB charger to equilibriate. Obviously the < 10us response times I'm getting in simulation are completely pointless in this application, but it'll be fun to play with such a touchy circuit for edumacational purposes -- I can just chuck in a 1nF feedback capacitor instead of a 6.8pF if I find that it just goes crazy in real life.I'm also not particularly trying to strain the control loop of the USB charger, I assume most phones are capacitative in nature so my load needn't look inductive. It's the load regulation of the charger I'm interested in, not its phase margin or ripple (although now that you mention it, ripple could be of interest…).Quote from: T3sl4co1l on July 27, 2015, 01:16:11 pmYour assumption is right, to meet the spec we're talking about a DC load that settles within 10ms or something embarrassingly slow like that. There is no target impedance per se, "looks like a phone" seems like a reasonable goal.Quote from: T3sl4co1l on July 27, 2015, 01:16:11 pmDo you mean that the impedance of my load will tend to get smaller as frequency increases? This is a very interesting observation and I'd like to understand this more deeply, although from what I've said above you can probably tell that I'm not actually concerned about this.Quote from: T3sl4co1l on July 27, 2015, 01:16:11 pmSince the supply and load are both USB connections, they will tend to be sharing a common earth. I'm vaguely concerned that I'll be creating a ground loop; but if that impacts accuracy I can just use a floating battery-powered laptop on the supply side. Would be half-arsed and unacceptable for a commercial product, sure; but I'm just having fun here!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 28, 2015, 03:25:50 pm
content: Ok, coolQuote from: rs20 on July 28, 2015, 06:54:28 amYes.What we can do is: consider a short instant, so that the op-amp's output voltage doesn't change*. Which means the MOSFET will look like a constant current, and so will the BJT's collector. Ah, but we're hanging off the emitter, so a change here acts to push around the base, incrementally; and any capacitance on the base (like Ccb and MOS's Coss) will be multiplied by hfe. Hence, the emitter looks like a low impedance.*Op-amps have identical considerations, of course; their outputs tend to be modestly low impedances at higher frequencies (~50 ohms, give or take some reactance -- and sensitivity to capacitance!), meaning the voltage doesn't change much under outside influence, or you can drive it and it will kind of go "meh" before the feedback kicks in. Conversely, rail-to-rail types tend to be high impedance, so you can push them around quite a lot, before feedback takes hold.)We can estimate where these break frequencies should occur, and make a cartoon of the Bode plot (which might even turn out correct!). We plot Zout vs. F. The first obvious curve is Ccb, which at the very least adds to the conductance. But we know this is in parallel with Coss, and gets multiplied by hfe, so we plot that (which is therefors a much higher conductance = lower impedance, and so drawn as a negative slope (capacitive) with a lower intercept than Ccb alone).By the way, what's hfe vs. F? It's not constant. In fact, it also decreases with frequency, generally assumed to be a first-order effect. So that if you plot the Bode of *that*, you get a flat region from DC to some break frequency, then dropping at -20dB/dec to unity gain at fT. As with all Bode plots, there are no actual sharp corners; the break frequency comes and goes gradually, as an RC lowpass would.Ideally, you'd use this curve to weigh the Cb multiplication. In practice, it's probably okay to assume hfe is constant up into the MHz range, and just say "well, our output impedance will be *about* so-and-so". The effect is that impedance levels off, rather than being a hard and fast capacitance, dropping to zero Z at infinite F. The dropoff will be gradual, which means the phase shift will change gradually, and the real component of the impedance will be significant -- what's happening is, the transistor is acting as a lossy resistor at these frequencies.At lower frequencies, Cb has less effect (|Z| is high enough to be useful), and the feedback does its work, too. How much? We can find the break frequency based on the op-amp's cutoff. Now, what the op-amp is able to do, I'm not entirely sure of. It will at least have the effect that -- if we fixed its output voltage down to DC (assuming the MOS and BJT behave, without drifting..), the output impedance will plateau at low frequencies, where Early effect and such become dominant over capacitance (probably in the 10kohm and 100pF range?). Assuming the feedback loop is sensitive enough, it can push that plateau up to higher resistances, and the break frequency down to a lower cutoff (approximately the f-3dB of the op-amp, usually in the 10s of Hz range). It shouldn't be able to push the impedance up any faster than the same capacitance line we started with, because that would require the loop to have much more than 90 degrees of phase shift! At least, I think.It is possible for the curve to have local bumps, where impedance changes at a rate faster than 20dB/dec, but these can't be very wide (i.e., LC resonances), and they are usually very sensitive -- a sign of instability, which we are intentionally avoiding by compensating the amplifier properly.Tim

author: rs20
author_rank: Super Contributor
timestamp: January 30, 2016, 04:19:56 am
content: OK, this thread is a bit old, but I thought I should close the loop! Behold, real life:I know there's a lot of solder blobs around, not sure why that happened. Maybe my solder paste was bad. I cleaned it up after taking this photo.Anyway-- interestingly, real life followed simulation with remarkable precision. with no feedback capacitor fitted, we see instability in the loop: (embarrassingly, I've actually forgotten* what I'm probing here. Ithinkit's the gate voltage on the FET; the offset/CMRR for my particular resistor array/opamp leant slightly on the dummy-load-always-draws-a-tiny-current side of things, so the gate voltage never goes far below the FET threshold voltage.)And with a mere 2.2pF capacitor fitted, it's a totally different story:Now I'm not saying that this one case vindicates simulation once and for all, and I do know that many errors can occasionally combine to give the correct answer. But you gotta admit, the simulation worked well on this occasion.For the record, even though it seemed to work well with 2.2pF, I ended up using larger caps (10pF I think*) just to stay well away from the bleeding edge.Many thanks everyone for your advice, I learned a lot and the design was improved as a direct result of everyone's advice. Oh yeah, and the dummy load works great!* I did all this months ago, just forgot to tell anyone. Also, note to self: keep better notes in futureEDIT: Fixed broken image link.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 30, 2016, 08:04:25 am
content: Always nice to see observation agree with theoryTim