Trouble with Transmission Gates.... - Page 1
Forum section: electronics / projects

author: BurnedResistor
author_rank: Regular Contributor
timestamp: February 23, 2020, 01:43:54 pm
content: Hey All!After taking a class in Digital Electronics I wanted to construct a D-FlipFlop with CMOS tranmission gates.I had seen basic CMOS logic gates in the past but had never worked with tranmission gates.I constructed the following Transmission Gate for testing:Using BSS84 2n7002 Fets.I am not able to get the gate to work. As far as I understand, if I Enable the Control signal (Ctrl = 5V, !Ctrl = 0V)the gate should be able to conduct in both directions between A and B.If I apply 5V to the B terminal, and connect A through a resistor to GND I am able to pull current from B to A only whenthe gate is enabled - as expected.However, if I connect 5V to A, I can draw current from B no matter what the CTRL signal is at.I have also attempted to construct the gate by having the drains and sources of the fets connected to each other instead ofthe Source-Drain Connections I have drawn above, but then the gate conducts in both directions no matter what the control signal is.Hey, at least it is parallel?Anybody got any idea what is going on here? I am at a loss.Wrong Transistors? Am I misunderstanding something?(Could cheap transistors from LCSC.com be the cause?)Thank you!

author: BurnedResistor
author_rank: Regular Contributor
timestamp: February 23, 2020, 02:44:12 pm
content: Quote from: blueskull on February 23, 2020, 02:05:37 pmThat makes a whole ton of sense, and explains all the behaviour I was seeing.(Who would have thought that the diodes included in the Mosfet-Schematic symbol are not just there to look fancy)Thank you for the fast response.

author: BurnedResistor
author_rank: Regular Contributor
timestamp: February 23, 2020, 04:14:54 pm
content: Thank you for the detailed explaination!

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 23, 2020, 04:21:20 pm
content: Yep, body diodes!Don't feel bad, this is a common trap. Unfortunately, if you're using discrete transistors, you will have a hard time doing what you want to do here.If you'd really like to prototype something with discrete parts, you may be able to devise something using a back-to-back configuration, using 4 transistors instead of 2.If you don't know what I'm talking about, see the idea here for instance:http://www.ti.com/lit/an/slva948/slva948.pdf

author: BurnedResistor
author_rank: Regular Contributor
timestamp: February 23, 2020, 04:52:01 pm
content: Quote from: SiliconWizard on February 23, 2020, 04:21:20 pmI wanted to try and build a Discrete D-FF:Another option would be to build an SR-Latch from 2 Nand Gates (8 transistors)I could then turn that into a D-Latch using 2 Nand gates and an inverterTwo of those + inverter(s) puts me at a D-FF and about 70 transistors.That seems a bit exessive. Especially because I was toying around with the idea of building some simple logic circuit/state machine from transistors for the fun of it.70 Transistors per D-FF would be an issueactual symmetrical two-way transmission isn't really necessary: The transmission gates are only used to either close the memory loop, or break the loop and connect it to the input.I guess I could look at Tristate buffer designs?https://electronics.stackexchange.com/questions/273933/3-state-buffer-mechanism?rq=1Then I would only need two extra transistors per transmission gate, so I could probably do a D-FF with:4 Not Gates (Memory Loops) = 82 Not Gates (Control Signal) = 44 Tristate-Buffers = 1628 Transistors. Still much but plausible.(Plus if I was latching multiple D-FF in parallel as in a basic state machine I would not need individual control-signal inverters for each gate)Or is that also not plausible?

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 23, 2020, 04:55:44 pm
content: You should consider implementing your FF without pass gates.Something like:https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#/media/File:True_single-phase_edge-triggered_flip-flop_with_reset.svg?Note that this is a dynamic FF here, so this is a bit of cheating. Dynamic logic is an interesting tool to know, but it has drawbacks. It requires constant clocking.A typical static D flip-flop will look like this:https://en.wikipedia.org/wiki/Flip-flop_(electronics)#/media/File:Edge_triggered_D_flip_flop.svg(That's 6 NAND gates with one with 3 inputs, so that would be 25 transistors.)The master-slave configuration:https://en.wikipedia.org/wiki/Flip-flop_(electronics)#/media/File:D-Type_Flip-flop_Diagram.svg(8 NAND gates, two inverters: that's typically 36 transistors.)So unless you're going for a dynamic version, not quite "cheap"!

author: BurnedResistor
author_rank: Regular Contributor
timestamp: February 23, 2020, 05:04:12 pm
content: I did see that image floating around but I have no idea how that is supposed to workI kinda don't want to blindly implement it without understanding it - the whole point of doing this from the transistor level up was to try and understand as much of it as possibleIll try and see if I can learn anything more about it (Some basic googling seems to refer to it as C2mos?)

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 23, 2020, 05:26:48 pm
content: Quote from: BurnedResistor on February 23, 2020, 05:04:12 pmYes, this is dynamic logic, also sometimes called "Clocked CMOS logic" when it's implemented with CMOS.You can find lectures about that out there.As I said, one drawback is that it can't operate statically.Benefits are several including lower transistor count, and in many designs in which the clock "never stops", they are a good fit. They'll be of course a problem if you need static operation (such as retaining state when the clock stops.)

author: BurnedResistor
author_rank: Regular Contributor
timestamp: February 23, 2020, 05:28:52 pm
content: Quote from: SiliconWizard on February 23, 2020, 05:26:48 pmI will get to work!Thank you

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 23, 2020, 05:40:15 pm
content: If you don't know her already, Jeri shows the concept in a simple way with some experiments: