Cause for the Vs waveform in Trans Impedance Amplifier circuit? - Page 1
Forum section: electronics / beginners

author: kankanas
author_rank: Contributor
timestamp: July 10, 2020, 05:27:47 pm
content: Hi,I am trying to figure out the cause for the Voltage waveform(attached image) being produced at Vs node in the below(attached image) Trans impedance amplifier.what I can understand is, due to some capacitance involved at that node may be the vs waveform is generated with the positive and negative spikes.Ideally speaking due to negative feedback of the OPAMP, the Opamp should provide virtual ground at that node Vs, at must remain at zero, but from which capacitance effect and how by analysis the spikes are being produced by giving the input current source is not clear to me.I would be thankful if anyone can help in the analysis.

author: kankanas
author_rank: Contributor
timestamp: July 10, 2020, 05:30:16 pm
content: Below attached schematic and waveform

author: magic
author_rank: Super Contributor
timestamp: July 10, 2020, 10:50:14 pm
content: Plot I(I1), I(R1), I(C1), I(R1)+I(C1), I(I1)-(I(R1)+I(C1)) and think what it all means

author: mikerj
author_rank: Super Contributor
timestamp: July 10, 2020, 11:33:34 pm
content: Notice thattia_opdoes not look like the input square wave, do you understand why? If so the reason for the waveform atvsshould become obvious.

author: kankanas
author_rank: Contributor
timestamp: July 11, 2020, 07:29:56 am
content: Hi,After plotting all the graphs What I understood is, Ideally I1=IR1+IC1. But it is not happening so. Points are----Initially, the capacitor C1 is shorted and tries to take the full current 420nA through it, when it charges to maximum it opens and current flows through resistor R1.1. As the pulse width of the input current source is very small(2us, Tperiod=5us), The R1C1 product i.e the time constant of the circuit is not able to take the full420nA current through the resistor R1 during this 2us duration. So due to this TIA_OP is not following a proper square wave2. The rest of the current I1-(IR1+IC1), the only path to flow this current is through the OPAMP inverting terminal. This current actually generates the voltage waveform at Vs. Now to have voltage at VS there should be some impedance of the opamp as the extra current flows through the opamp.Here Can I assume Vs= (I1-(IR1+IC1))*INTERNAL IMPEDANCE OF OPAMP?from the datasheet, internal resistance mentioned as 10^12ohm, but it is not following through after multiplying with the current as of the generated voltage

author: kankanas
author_rank: Contributor
timestamp: July 11, 2020, 07:33:26 am
content: As the pulse width of the input current source is very small(2us, Tperiod=5us), The R1C1 product i.e the time constant of the circuit is not able to take the full420nA current through the resistor R1 during this 2us duration. So due to this TIA_OP is not following a proper square wave as the charging time is more.if I increase the pulse width of current or make changes in the R1 C1 value then it approaches more like a square wave.

author: kankanas
author_rank: Contributor
timestamp: July 11, 2020, 08:25:57 am
content: I think there was a mistake in the previous simulation. IR1+IC1 is actually I1 only, reviewed the simulation.Attached the corrected waveform.So, it seems that the vs waveform is due the capacitor C1, a capacitor does not allow a sudden change in voltage. So, as the TIA_OP starts increasing after the 1st pulse of current input arrives, to remain the VC(Voltage difference across cap) to zero Vs drops to negative spike instantaneously

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 11, 2020, 08:31:49 am
content: What else could it be / what were you expecting it to be?A dominant pole compensated op-amp is an integrator, therefore it has less gain at high frequencies, and its input (in the inverting configuration) has a rising impedance (as opposed to the "virtual ground" of the infinite-gain case).To increase bandwidth as shown, reduce the feedback capacitance.Tim

author: magic
author_rank: Super Contributor
timestamp: July 11, 2020, 08:33:38 am
content: The opamp has internal input capacitance (a few pF) which is being discharged by I1. I think TL071 datasheet fails to specify itbut it's something you expect to exist in every chip.The reason the opamp fails to prevent it is because it has limited bandwidth and limited gain at high speeds. It takes a significant input error (a voltage spike at Vs) to cause the opamp to start moving the output, which increases current flow through R1||C1, compensates the increased I1 current and slowly discharges Vs. You can see that the output isn't exactly equal to the input current, it's delayed and distorted.A faster opamp will do it faster. If you are using LTspice, try the built-in LT1022 model. Or heck, even LT1468 which is a significantly faster bipolar opamp. Bipolar might still be good enough with only 50kΩ feedback resistance. Maybe.You will never eliminate it completely, unless you replace the opamp with something much more ideal, that has zero phase delay and constant open loop gain at all frequencies. Try the 'e' component (voltage-controlled voltage source). Connect its inputs as an opamp, connect the negative output to ground, set its E value to 1Meg (open loop gain).editT3sl4co1l is right that some of the output distortion is due to C1. However, the distortion of combined C1||R1 current is due to limited opamp speed, otherwise this current would exactly follow I1 current. And the fact that there are spikes on Vs is a clear proof that the old '071 needs a serious kick on its butt to get it going

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 11, 2020, 11:19:48 am
content: To be clear -- are you using "distortion" in the "it's not identical" sense, or the technical sense?Tim

author: magic
author_rank: Super Contributor
timestamp: July 11, 2020, 11:47:02 am
content: Not sure what kind of "technical sense" would apply here, just that it's different than expected.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 11, 2020, 12:10:46 pm
content: The waveforms appear to be linear, i.e., the relationship between input and output, is an LTI transfer function, i.e. it obeys f(a+b) = f(a) + f(b) among other things. It doesn't have the frequency response of the input signal, but that doesn't mean it creates distortion (nonlinearity).But if you're referring to pulse shape, in that sense it can be said to be "distorted". This would be a less technical meaning.Tim

author: kankanas
author_rank: Contributor
timestamp: July 11, 2020, 04:30:57 pm
content: The waveform should be linear, i.e while giving input current as square wave produced TIA OP must also be square.But, here the distortion in the output waveform is happening as the capacitor and resistor value are not able to charge that fast as the input. within 2us the resistor should finally take whole I1(420nA) but due to insufficient values of the system parameter R1C1 it cant follow. So it is showing the distorted output.Now, I cant reduce the cap value very small(min 5pF tested correct result) as it will give me oscillation at the output and increasing resistor-capacitor product too high will give me distortion i.e slow responseI tested with LTSPICE inbuilt OPAMP LT1022, and the responses are showing the same only.To understand this point ---"The reason the opamp fails to prevent it is because it has limited bandwidth and limited gain at high speeds. It takes a significant input error (a voltage spike at Vs) to cause the opamp to start moving the output, which increases current flow through R1||C1, compensates the increased I1 current and slowly discharges Vs. You can see that the output isn't exactly equal to the input current, it's delayed and distorted."------- I configured a simple inverting amplifier model with that OPAMP and tried with two types of inputs: 1. Square 2. sine1. For a square wave, I observed the same type of spike at inverting terminal node--- so got a point that whenever a comparative sharp change input is given to the OPAMP, it produces spikes at that node to reflect the change in output, to make it able to flow the current through the feedback resistorBut with increasing rise and fall time(much high), the node of inverting terminal showing more pulse kind a waveform with some +mv to -mv range2. For applied sine wave this node is showing sine wave pulse with uV rangeso still the cause of the waveform at the node(which is assumed to be at virtual ground) is in little doubt.

author: magic
author_rank: Super Contributor
timestamp: July 11, 2020, 06:11:23 pm
content: Below is a simple, "highly ideal", "opamp" circuit with 16MHz gain bandwidth product, 120dB open loop gain, 90° phase margin and zero input capacitance. This enables it to work in TIA configuration without feedback capacitor.You can copy this simulation and run AC analysis if you don't believe that it works like an opamp.As you see, it exhibits exactly the same peaks on Vs. And they are absolutely necessary if you consider how this opamp works, and real opamps work in a similar manner. That is, charging/discharging an internal capacitor with current proportional to the input error voltage and outputting the capacitor's current state by means of a unity gain voltage follower. An input error is strictly necessary for anything to happen and the faster you want it to happen, the larger the error needs to be.The peaks are caused by the current source forcing current through the feedback resistor despite the other end of the feedback resistor (the output node) not having changed yet. Vs is exactly V(out) - I(I1)*R2, as it needs to be because all capacitances have been eliminated from this (fictional) circuit.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 12, 2020, 12:43:50 am
content: You must understand what is called thebandwidthof a signal, or system.You specify a square wave with 0.1ns edges. This requires a bandwidth on the order of 5GHz.To faithfully reproduce a signal with 5GHz of bandwidth, you must have an amplifier capable of the same or greater bandwidth.The TL071 rolls off at some 10MHz, a factor of at least 500 lower than what you are apparently demanding of it!Tim

author: kankanas
author_rank: Contributor
timestamp: July 12, 2020, 07:55:26 am
content: Thanks for giving more insights about the OPAMP macro model and explaining vs.So, the conclusion is, due to the internal capacitor of OPAMP, whenever an input change will come in the inverting or noninverting terminal internal capacitor will charge/discharge with the internal VCCS and the voltage responsible for creating a flow of current through cap is the vs, i.e the input error voltage between the two terminal.From different test input, I observed that if I reduce cap value so vs change will be less. The reason is as cap value reduces the VCCS will take less time to charge the cap and very fast it will approach output and vice versa for increasing. Similarly it depends upon the gain of VCCS. but with the input rise time increase or decrease i.e for slow change input or fast change the vs graph is not changing. Isn't this case also output response and Vs should change?

author: kankanas
author_rank: Contributor
timestamp: July 12, 2020, 08:14:40 am
content: Yes, That was my mistake understanding the bandwidth of square pulse.For a square wave, bandwidth is 0.35/tr where tr is rise time. So, as I took rise time in such small bandwidth of the signal is very high but the opamp cant process such high bandwidth(as unity gain frequency limited to 5MHZ).regarding the system bandwidth, I observed that with suitable RC it is following the input graph though the OPAMP is not capable. How this can be justified I mean, I am designing a TIA, where the I am giving input bandwith more than OPAMP Bandwidth, and adjusting system parameter (RC) it is approaching the input current waveform?