Gate Driver Suggestion - Page 1
Forum section: electronics / projects

author: blueskull
author_rank: Unknown
timestamp: December 10, 2015, 11:21:07 pm
content: Hi,Anyone have any suggestions on ahalf bridgedual gate driver that can operate at10MHz?The load voltage swing requirement is fairly low, just 0 to 5V will be okay. The total gate charge will be around 20nC.Preferably rise/fall time below 2ns, which translates to 20A peak current, but anywhere below 5ns is fine.Minimum on time requirement is not too strict, 20ns will be fine, which represents 10% duty cycle at 5MHz.This will be used in a voltage regulation module generates 0.8~2.5V from 12V, operates at 2MHz~10MHz.Thanks,Bo

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 11, 2015, 01:59:31 am
content: As in, bootstrap monolithic thinger?I don't think they're usually that fast...Can't find a controller chip with all that stuff integrated too? That's usually the way to go, it seems... assuming you can find the right functionality of course.Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 11, 2015, 03:16:03 am
content: And just to reality check:You realize what you're asking, right..?20A in 2ns, at 5V, is 0.5nH, so it's not even within the domain of PCB fabrication -- if you're lucky, it could be done on a hybrid module (even bondwires are problematic, there), but most likely has to be done entirely on die.If this has to be realized on a PCB (where lead, pad and trace inductances are >1nH), consider doing it at lower efficiency (i.e., more slowly, maybe 5 or 10ns edges?), or at lower power (smaller transistors per half-bridge, with multiple phases wired in parallel?). If the ultimate goal is size savings, you're probably going to waste more space organizing the parallel units, than you'll save at the high frequency. Which would basically illustrate all the design issues for why you don't see much in power switching over 2MHz or thereabouts...Tim

author: Marco
author_rank: Super Contributor
timestamp: December 11, 2015, 03:34:34 pm
content: A dozen ZXGD3003E6 in parallel?Or a couple EL7158.I don't really see how you could avoid going bare die here, everything gets too large otherwise.

author: Marco
author_rank: Super Contributor
timestamp: December 11, 2015, 04:46:38 pm
content: How much pulse current can LDMOS transistors take? (It's not what they are designed for, so datasheets are a bit useless here.)

author: Marco
author_rank: Super Contributor
timestamp: December 11, 2015, 05:15:25 pm
content: No, I mean you could use RF LDMOS transistors (like PD85004) to drive the gate if they can take the pulse current.

author: langwadt
author_rank: Super Contributor
timestamp: December 11, 2015, 05:36:39 pm
content: Quote from: blueskull on December 11, 2015, 03:24:55 ama trick to bypass the source inductance is to use a current sensing mosfet and use the kelvin connection for the gate drive ground

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 11, 2015, 06:01:52 pm
content: Quote from: langwadt on December 11, 2015, 05:36:39 pmThat avoids the bootstrap effect of load current flowing through the signal path and making things >10 times worse, yes. But the Kelvin loop itself isn't going to have magically zero inductance. The speed of light is finite, and requires that his connections be <1 mm long, from chip to chip, basically.It might not be impossible, but I can guarantee it won't be cheap. Direct die mounting is required, very fine pitch is required (not impossible for a PCB, but more like a BGA interposer than a standard PCB fab), and even then, arranging all the required components around will be a challenge.Tim

author: Marco
author_rank: Super Contributor
timestamp: December 11, 2015, 08:09:05 pm
content: Quote from: T3sl4co1l on December 11, 2015, 06:01:52 pmIf you ram it with enough voltage it's doable with normal components, it's the 5v swing which makes it almost impossible.Seethis paper. They switched a TO247 in 3.25 ns with SO-8 MOSFET gate drivers. With a SON2x2 main MOSFET and RF LDMOS gate drivers you could shave off a lot off inductance relative to that.With +/- 12V drive it could be possible.

author: diyaudio
author_rank: Frequent Contributor
timestamp: December 11, 2015, 09:27:31 pm
content: Quote from: blueskull on December 10, 2015, 11:21:07 pmuse a driver chip with weak current output, but capable of high frequency.. then use local buffering to handle the current output levels.

author: MagicSmoker
author_rank: Super Contributor
timestamp: December 11, 2015, 10:23:59 pm
content: Personally, I would be looking at a resonant gate driver. Run the numbers, and you'll see this is an almost impossible task for a conventional gate driver. You need to pump the gate with 10A peak to slew 20nC of charge in 2ns, but just 1nH of stray inductance will result in 5v of overshoot during turn on, and that is more than enough to punch through the gate of a GaN MOSFET.

author: Marco
author_rank: Super Contributor
timestamp: December 12, 2015, 12:18:33 pm
content: When I think about the term resonant gate drive I think about circuits which recirculate energy in the gate between switching cycles, it's good to save energy but it doesn't fix the fundamental problem. Such a circuit can swing up to destructive voltages as easily as a hard driving design.It's all about limiting the energy you're driving into the gate each cycle, whether the energy is recirculated isn't really important for limiting the gate voltage. That paper I linked earlier for instance does not, it just limits the turn on time of the gate drive transistors.

author: MagicSmoker
author_rank: Super Contributor
timestamp: December 12, 2015, 02:17:28 pm
content: @marco - yes, poor layout with a resonant gate driver - and/or insufficient damping of the tank network - can result in destructive overvoltage, too, but let's not dance around the essential problem here that 10MHz is an extremely high switching frequency for an SMPS. In fact, the power conversion topology itself should also employ resonant or quasi-resonant switching, and not just the gate driver. The OP is attempting cutting edge stuff here.Attached is a paper discussing various resonant gate drive techniques which I have found useful.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 12, 2015, 07:08:09 pm
content: I don't see how that gets you any speed advantage. Or in reference to peaking circuits, more than a factor of 2 advantage. Yes, every little bit helps, but it's not like it's an order of magnitude.Peaking circuits depend upon the conditions being consistent; Cgs is neither constant with input voltage, nor independent of load conditions, so choosing the right inductance and resistance values is nebulous. You also depend upon the internal Rg, which is poorly specified and may be too large to allow this method (i.e., to achieve the required risetime, you'd have to drive it with a negative resistance gate driver -- or an overshoot method, but that requires even more risetime, and at a low impedance). Given the gate drive doesn't need to be precise, it's probably workable anyway, but do expect more sensitivity to surrounding conditions (like supply and load V/I).Tim