OK to have zero size via pads on outer layter of 4L PCBs? - Page 1
Forum section: electronics / general

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 25, 2014, 05:32:26 pm
content: Just looking at the feasibility of a potential stupidly dense design on a 4 layer PCBIdeally it would use a lot of blind vias between layers 1-2 and 3-4, but it seems this is an expensive process (compared to buried vias between 2-3).I may be able to live with all the vias going all the way though if I could avoid having via pads on the layers that the don't connect to, particularly the outer layers.so for example I'd have a 0.15mm hole with 0.4mm pads on layers 1&2 only, or 3 & 4 only.This is low-volume so needs to be compatible with a normal processI don't think I've seen a board like this, but can't immediately think why it shouldn't be possible - Anyone done this?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 25, 2014, 05:46:25 pm
content: Hmm, I should think it has to connect to at least one layer, else how are they going to plate the barrel?That said, once upon a time I ordered boards with NPTH holes through standard proto -- the NPTHs came back dutifully plated, despite having no annular ring and no connecting copper. (They were then reamed out to clear the plating.)Do you know anything about standard micro vias or laser drilled?Tim

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 25, 2014, 06:02:19 pm
content: Quote from: T3sl4co1l on November 25, 2014, 05:46:25 pmyes they do - 1&2 or 3&4

author: free_electron
author_rank: Super Contributor
timestamp: November 25, 2014, 06:32:04 pm
content: neat idea but not manufacturable.here's why :the core is etched first. two outer layers with solid copper are added.now you need to drill.perform platingnow photoresist is added. this resist is open over the barrel ( negative process )they apply tinflash in the barrel and on the annular ring.then resist is stripped and the resist removed.the tinflash protects the copper against etching ( sodium persulfate only eats copper , not tin )if you do not have an annuylar ring the edge of the plated copper would be exposed leading etchand to seep in between the wall of the barrel and the pcb material.you need a minimum annular ring to prevent this.due to registration errors in drilling ( typical 2 to 3 mil) they want to see a 6 mil annular ring of 6mm. so, even if you are off 3 mil there is still 3mm material covering the edge of the barrelwhy don't you use via in pad ? that way they simply plug the via's in one shot and plate em shut.no need for stacked via's. and this process is much cheaperafter plating they screen print conductive expoy in the holes , cure it , sand it down ( planarisation) and then plate the entire board again .. expse , tinflash, strip and etch.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 25, 2014, 06:45:36 pm
content: Quote from: free_electron on November 25, 2014, 06:32:04 pmThanks - that was the info I was looking for!Fortunately it shouldn't be too much harder to do as two 2-layer boards that can be stacked.

author: IconicPCB
author_rank: Super Contributor
timestamp: November 26, 2014, 08:02:10 am
content: Mikeselectric,I make PCBs commercially using mechanical milling process.It is not a problem for me to etch away any copper anywhere on the surface of the multilayer board.

author: WarSim
author_rank: Frequent Contributor
timestamp: November 27, 2014, 03:41:08 pm
content: Quote from: free_electron on November 25, 2014, 06:32:04 pmBy your answer it suggests alternate buildups so are no longer possible.Every layout software title I have ever used starts with a buildup definition.Most will warn on buildup definition violations.Is this all ignored now?I know the board was shopped out to specific manufactures depending on the design, of which buildup was a factor.I have never shopped out my own boards. Most likely the main reason your answer confuses me. Especially because I have never seen any board maker state their buildup process was fixed to only one buildup.The reason I am so interested is I am semi-retired now so I will be shopping out my own boards now.Sent from my iPad using Tapatalk

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: November 27, 2014, 05:44:02 pm
content: Quote from: WarSim on November 27, 2014, 03:41:08 pmThat doesn't mean that buildup is manufacturable (at a sensible cost).Like I said, I need to keep to standard processes.It was only when I re-watched the Eurocircuits video that I realised that 4L is built from the core outwards, not as two 2Ls that get stuck together.

author: WarSim
author_rank: Frequent Contributor
timestamp: November 27, 2014, 09:32:27 pm
content: Yes each board house has a Standard process, and deviating cost extra. Depending on board house how much more varies. This is one reason why we contracted out to different board houses.What I previously though you said was. Some how all the various board houses decided on one specific standard. Also that the other buildups have been all but abandoned.If there is one "standard" buildup, this makes little sense to me. Then again there is no law about making sense.Sent from my iPad using Tapatalk

author: Rufus
author_rank: Super Contributor
timestamp: November 28, 2014, 01:49:49 am
content: Quote from: WarSim on November 27, 2014, 09:32:27 pmPlating holes (normally #1) requires solid copper at both ends so must be done before etching. You can only etch the outside of a board or stack component. You can bond boards together, you can bond copper on the outside, you can probably sandwich copper planes between boards.Those requirements lead to not many ways to make build up.#1 you can do pick drilling where you only drill deep enough to hit copper on an inner layer and plate the hole with solid copper only at one end to create a blind via.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: December 01, 2014, 10:02:05 pm
content: So Ijustmanaged to do it with 0.15mm via holes and 0.125mm track/space...

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 01, 2014, 10:55:45 pm
content: LED matrix?Tim

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: December 01, 2014, 11:13:48 pm
content: Quote from: T3sl4co1l on December 01, 2014, 10:55:45 pmYes - 1.5mm pitch, 0402 LEDs 32x32 matrix driven as 16x64

author: AlfBaz
author_rank: Super Contributor
timestamp: December 02, 2014, 03:56:37 am
content: Quote from: mikeselectricstuff on December 01, 2014, 10:02:05 pmHi Mike.I looked into this some time ago and I asked PCBCART if they could do it. The response was "yes, no problems, no extra cost".Still I decided against it as I couldn't ascertain how it was manufactured and had concerns about manufacturabilityGood to see that it is indeed possibleJust to clarify, are the following two pictures something along the lines of what you have done? The first pic is with a pad on every layer the second with pads on 2 and 4 only. The main feature being no pad on the outer layer

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: December 02, 2014, 10:32:02 am
content: Quote from: AlfBaz on December 02, 2014, 03:56:37 amThe second pic is what I was interested in doing, to make space on outer layers where the via doesn't need to connect to that layer.

author: Scrts
author_rank: Frequent Contributor
timestamp: December 16, 2014, 09:32:19 am
content: I use such thing all the time without any issues. When you have to route two tracks between BGA pads and there's also a VIA for one of the pads, then it's the only way to go.

author: Korken
author_rank: Regular Contributor
timestamp: January 18, 2015, 08:17:00 pm
content: I have been trying to do this in Altium (removing the via pad on some layers).How do you do this? I've tried using drill pairs, but didn't get it to work.

author: free_electron
author_rank: Super Contributor
timestamp: January 18, 2015, 10:00:06 pm
content: Place via. Double Click Via.Set 'diameters' to 'FULL STACK'edit the annular ring for every layer.

author: Korken
author_rank: Regular Contributor
timestamp: January 18, 2015, 10:01:50 pm
content: Thank you! Of course I didn't look in the obvious place...

author: AlfBaz
author_rank: Super Contributor
timestamp: January 19, 2015, 01:19:08 am
content: Quote from: free_electron on January 18, 2015, 10:00:06 pmIn multilayer designs, pads on unused layers can be considered "mini-stubs" in high speed designs. I could of sworn somewhere in the past there was an option to prevent pads on unused layers. Am I misremembering or have they gotten rid of it/buried it somewhere?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 19, 2015, 07:32:19 am
content: Rings on non-connecting layers is an export setting. In Outjob / Gerber output.Tim

author: AlfBaz
author_rank: Super Contributor
timestamp: January 19, 2015, 07:51:16 am
content: Quote from: T3sl4co1l on January 19, 2015, 07:32:19 amAh ok, that rings a bell.There may also have been an option like that in a script I was using to export to hyperlinx before they included it