Ground splitting - clearance = min. trace width? - Page 1
Forum section: electronics / projects

author: ninux
author_rank: Contributor
timestamp: July 27, 2020, 12:02:10 pm
content: Dear colleagues,I'm working on a resonant capacitor charger PCB (see attachment) and I have a power ground zone (resonant currents present) and a "clean" ground zone (digital and analog). I have separated them using common mode chokes both for the signals and the LV supply (e.g. 12 V for the gate drivers), so that there is a defined return path while having a suppression of common mode disturbances (see attachment).For the spacing and trace widths I oriented my design towards the smallest structures given by the parts used (QFN32), thus, I have >= 0.3 mm trace widths and >= 0.2 mm clearances. For the ground splitting I have chosen a clearance of 0.4 mm which is 2 x the min. clearance.Now I'm wondering, how to determin a "good" clearance for different ground zones? Do you just use the min. trace width or do you have some other rule of thumb? Additionally, would you suggest different clearances for inner layers?Thank you all in advance for your replies, any suggestion will be thoroughly appreciated.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 27, 2020, 05:23:58 pm
content: Ah, one of the O.G. KiCAD users? Welcome!The clearance there doesn't depend on voltage, obviously it's zero (DC; and probably...hopefully? not much AC). It does set the capacitance (or at very high frequencies, slotline impedance) between sides.For a 1.6mm thick board I usually go for 1mm slots, if I don't have any particular reason to do otherwise. Closer approach is okay in places, if traces need more space nearby (DO NOT CROSS TRACES OVER SLOTS), or even overlap between top and bottom (as long as there's clearance within each layer, and the overlap is small).Tim

author: ninux
author_rank: Contributor
timestamp: July 28, 2020, 07:37:23 am
content: First, I had to check the urban dictionary about the O.G. ... Thanks for the warm welcomingThank you very much for your reply. I have changed my clearance for the slots to 0.8 mm as this fits everywhere in my design.I usually keep everything together on a single ground plane for the non-power part of my designs. However, when power is involved, it makes sense to separate things. Here, it's an interleaved PFC stage switching at 100 kHz and next to it is a series-resonant full bridge converter at 100 kHz (current is at ~ 220 kHz). "hopefully not much AC" depends on who you ask I guess. My RF colleagues would say it's still DCI placed a slot to guide the current away from the feedback processing. Regarding the slot-crossing, I have to do it for the PWM signals but there I used the common mode chokes, which should be fine I guess. However, the control chip is also processing feedbacks referenced to power-ground and thus, I have some feedback signals crossing the slot. But these signals are filtered and the chip is directly next to the slot having the "star" connection next to the chip (see attachment).I know, ground splitting is a delicate thing and I avoid it wherever possible. Wish me luck to get it working with this one

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 28, 2020, 02:50:34 pm
content: I don't know what exactly your application is, but split grounds... it's rarely recommended these days. I'm surprised nobody commented on this yet.Of course you may have very good reasons for doing so, but as you yourself noted, they are often best avoided. So I'm curious what your rationale is here for choosing this approach.As a general thought, split grounds typically between "digital" and "analog" sections is *usually* NOT a good idea, and further putting inductors between them makes things worse.Your design looks a bit different, as if I understand correctly, you essentially have a very noisy, power section, and a cleaner section. Rather than split grounds, if you really do not manage to keep noise under control for the "clean" section using a common ground, something that may be more sensible could be to galvanically isolate the two sides completely. Just a thought.

author: ninux
author_rank: Contributor
timestamp: July 28, 2020, 07:25:28 pm
content: Quote from: SiliconWizard on July 28, 2020, 02:50:34 pmI totally agree with you and I also try to avoid ground splitting wherever possible. However, every rule has it's exceptions ... otherwise we would not need so many creative engineers, right?About the isolation: Yes, I agree! However, this particular design is a bit odd in some ways. Indeed, it has already three isolated regions. One is the input (I/O and LV supply) section, another one is the HV output. The input is ground referenced. In between is the two-stage converter (PFC + SRC), which is implemented with reinforced isolation and powered by the mains input. The "ground" for this region is the negative potential of the mains full-bridge rectifier. Now, the PFC controller is referenced to this "power ground" and so is the SRC controller. With this, the controllers are on the "hot" side of the design (I know, not easy to debug with HV on).My rationale to not implement another isolation barrier for both the PFC controller and the SRC controller was that the chips are made for direct feedbacks and that the whole power region is already reinforced isolated for both the input and the output. With this, I decided to make a power-ground for the HV and high-current region of the design and I wanted to separate the LV parts (controllers, signal processing, and internal communication) on a "clean" ground.I know, it's hard to follow a written explanaition of a quirky design. See the attached diagram for the different regions.