Need Help on DAC Layout verification - Page 1
Forum section: electronics / general

author: Monsun
author_rank: Newbie
timestamp: June 11, 2025, 03:21:33 pm
content: Hey there, I just recently joined this Forum in hopes to find some help for my University Project. We designed a PCB to apply a IIR Filter onto an Audio Signal via an FPGA. We use a PCM1808 ADC in combination with a PCM5102A as an DAC. The whole configuration is set so the ADC is in master mode. Right now it appears so, that the ADC is working correctly, producing all the correct Signals. (We use I2S)The BCK, LCK seem to be correct and data is also being transmitted. However, we don't seem to get any audio out of the DAC, and now I am unsure if it's a lack of my FPGA programming skills(Which are not good) or I made an error in the PCB Design somewhere. We have 2 weeks to somehow figure this out until our final Presentation, and I can't seem to find what's wrong. I have already replaced the DAC and probed every connection to make sure nothing was soldered wrong to my knowledge. I strictly followed the Application example in the Datasheet of the DAC, but it somehow doesn't match with the PCB Layout example. Since all the Ratings in the rest of the datasheet state that CPVDD has to be indeed 3.3V I assume the Layout Example is just misleading or wrong.If anyone has an Idea or could help me find the error, I would be extremely grateful. If any further Information is needed like the VHDL code I can also provide it, but I assume that would be better suited in another Subforum.(Since this isn't fully ruled out that this is the source of my error)

author: betocool
author_rank: Regular Contributor
timestamp: June 13, 2025, 02:51:28 pm
content: I will assume that your schematic and layout is correct, I haven't double checked it.Have you probed the output of the DAC? Have you checked the I2S signals from the bus? Do you have access to a Logic Analyzer where you can see the I2S signals?Common issues could be your bit output not be synchronised with your bit clock. Also, some PCM DACs require a MCLK additional to the bit-clk signal. Is the configuration on the DAC correct (i2S left, I2S right, PCM?).If your schematic is correct and you vaguely follow the layout recommendations you will be ok. Are your FPGA outputs ok? Mapping OK?Try to generate a Sine signal from -2^22 to +2^22 (24 bit) on your FPGA and see at the DAC's output what it spits out. I've had issues in the past where serial bit 0 is sampled as bit 1 and so forth, creating a spike at the peak of the sine.Cheers,Alberto

author: Monsun
author_rank: Newbie
timestamp: June 13, 2025, 05:09:02 pm
content: First of all, thanks for the reply. To give a quick overview of what ive done.First i have probed, if the DAC receives Data, Clks etc at all, and that seems to be the case. Although, what i found out today, i seem to shift the data bits a little bit wrong. They are not beeing shifted by 1 exact LCLK cycle.(Picoscope pics) This altough to my understanding should still lead to some Output.( Garbage obviously but in some cases the MSB is 1 so i should see garbage from 0.8xVDD to -0.8xVDD) which isnt the case. I just see some noise. In the "better" Osciloscope pics, you can see the ADC input to the FPGA and the input to the DAC and also the BCLK to the DAC. This also seems to be correct in my eyes. In the last Picoscope pic you can see Green ADC in. Blue LCKLK. Red DAC in. The noise level was from just 200mv to -200mv.I will try to fix the shifting issue, but as far as i know it should still do SOMETHING since it still aligns with changing the bit state on a Falling edge of BCLK.(Last two images).Note: I have also quadruple checked if I am sending all these signals to the right pin of the DAC.Also i will try as soon as possible to try your suggested Idea.

author: Monsun
author_rank: Newbie
timestamp: June 13, 2025, 07:19:16 pm
content: Quick update. I have fixed the misalignment and the signal is now shifted by one full 64BCLK cycle as intended. Silence. I have also instead of trying your sine approach, Invert each bit to see if that makes a difference. Silence. New screenshots attached. I am running out of Ideas and feel kind of helpless.In my eyes it can only be:DAC Dead(swapped once already verified voltages),Wrong Layout,XSMT(Soft mute not working correctly)Dont know why it should just needs to be high to not be muted. I also added some pictures of where iam probing the output Signal. And yes the Flux is a mess and dont judge the Trace Via Incident on the Right)

author: pcprogrammer
author_rank: Super Contributor
timestamp: June 13, 2025, 07:55:08 pm
content: Did you check that the XSMT pin on the DAC is actually high and not floating or low?I use the PCM5102A based modules found on for instance Aliexpress, and when I got a slightly different module when I ordered new ones, during the first test I did not had the XSMT pin connected and got no audio out. Only after connecting it to the 3V3 supply sound started to come out.

author: Monsun
author_rank: Newbie
timestamp: June 13, 2025, 08:43:18 pm
content: Yes that was my immediate concern aswell, but i checked on the FPGA pin and on the pin of the Chip and indeed 3.3V. Note i set it high via an GPIO from ther FPGA, but that shouldnt cause any issue right? I could in theory solder a jumper to it to hard set it on 3.3V instead, but to me there shouldnt be any issue right? To further add to your response i actually also orderd one to test it with a module rather than my PCB:https://www.amazon.de/dp/B07PMGGMJF.It arrives tomorrow, so I will check with that one as well to rule out any layout issues.

author: dietert1
author_rank: Super Contributor
timestamp: June 14, 2025, 05:42:30 am
content: About 12 years ago i used the PCM5102 audio DAC without any problems.As you mentioned some doubts about the charge pump: You can check the voltages on the LDO out pin and the negative supply. You wired SCK to the FPGA. It needs to be low for using the PLL driven by BCLK or the proper clock depending on I2S audio rate. Which mode of operation is intended? Did you check the implementation?Regards, Dieter

author: pcprogrammer
author_rank: Super Contributor
timestamp: June 14, 2025, 06:28:40 am
content: Quote from: Monsun on June 13, 2025, 08:43:18 pmIf all the other signals are correct it should work as long as XSMT is high, either driven by the FPGA or directly connected to 3V3.The module you ordered is the same as a couple that I have. The other ones I have are these:https://www.aliexpress.com/item/1005006104038963.htmlFor reference this is the same one as you ordered:https://www.aliexpress.com/item/32828177686.htmlI use them as I2S slave device with SCK supplied by the MCU. For this the FLT, DEMP and FMT signals are driven low. (Connected to ground, just as in your schematic.)A difference between your schematic and the module are 22 Ohm series resistors in the clock and data lines, but if this causes a problem like you are seeing is doubtful. On the other hand SCK probably has quite high frequency and it could have an impact on the edges.The test point you made for this signal can act as an antenna. It would have been better to just add a round pad without hole directly on the trace to keep it as short as possible. With SCK up to max 50MHz it is in radio frequency range.

author: pcprogrammer
author_rank: Super Contributor
timestamp: June 14, 2025, 06:34:50 am
content: I checked your posts again, and noticed that you did not measure BCK in relation to SCK. Maybe there is a phase problem between these two.You can try to just make SCK low in the FPGA programming and let the PCM5102 make it's own master clock based on BCK, just like what dietert1 suggested.

author: dietert1
author_rank: Super Contributor
timestamp: June 14, 2025, 08:11:17 am
content: For your entertainment: This is an audio DAC i made in 2018. The Toslink input drives a CS8416 SPDIF receiver and two ES9023 DAC modules that yield two channels of symmetric audio. The ES9023 is somewhat similar to the PCM5102A. It provides a 6 Vpp audio output, that becomes 12 Vpp in this symmetrical configuration.There is a digital inverter for the I2S audio signal and a supply voltage regulator with a common mode choke. Mains transformer and rectifier are external.Regards, DieterEdit: I thought about making a similar device with 6 audio DAC modules, implementing the 168 dB S/N DAC that we recently learned about. The inverter would become a little FPGA and then there would be four 3 to 1 analog MUXes to connect the audio outputs from the DAC that performs best. The FPGA would implement the level meter and the level calibration necessary to join the reference voltages of the DAC chips. So many ideas..

author: Monsun
author_rank: Newbie
timestamp: June 14, 2025, 07:22:03 pm
content: First and foremost again, thank you so much for the replies. This way i at least don't feel alone losing my mind.To furthermore answer all sugestions step by step.I inted to use the FPGA as the Master Clock.ADC as Slave: "Slave mode (256 fS, 384 fS, 512 fS autodetection)"SCLK: 12.228Mhz (Created via Clocking Wizard on the FPGA)BCLK: 3.072MhzLCLK: 48kHz->given to DAC/ADCI am aware that the DAC also has a PLL to create an internal SCLK from the BCLK but to my understanding it is also viable to give the SCLK non the less to the DAC. It will just starting to use the PLL if the no SCLK is present.(See pics) I also tried to just give BCLK for testing to the DAC, still didnt seem to produce any Output.Data is buffered and given 1 LCLK Cycle shifted and given to the DAC.XSMT: HighFMT: LowFLT: LowDEMP: LowAbout the 22 Ohm series resistors, i also just found out when I ordered the Modules, but those weren't mentioned in the Datasheet, so I was not aware it's better practice to have them.As far as I know, since my traces are extremely short, this still shouldn't propose the issue of the DAC being completely silent.And well, to come back to the Entertainment part: At least yours looks like a finished working well integrated solution, while my signal integrity is on a path of steadily declining, just like my sanity.Furthermore, the full VHDL code is attached in the txt file, maybe it's been the issue all along, and I am stupid!It has been heavily inspired by this:https://forum.digikey.com/t/i2s-transceiver-vhdl/12845Note: The module arrived today as well and still: Silence. But unfortunately i can only solder tomorrow, so it could very well be the case now that because of all the nonsense that you see in the picture of my current test setup its not working because of that.Anyway, onto another 12-hour shift of trying to make this work.

author: EggertEnjoyer123
author_rank: Frequent Contributor
timestamp: June 14, 2025, 07:40:31 pm
content: Have you tried using a logic analyzer instead of an oscilloscope?Your BCLK is only 3 MHz. A cheapo USB logic analyzer should work and you should be able to decode the I2S data.Can you try sending all zeros followed by all ones to the DAC? That would rule out any issues with bit ordering.

author: dietert1
author_rank: Super Contributor
timestamp: June 14, 2025, 08:38:01 pm
content: The LDO output pin and the negative supply have been checked?

author: pcprogrammer
author_rank: Super Contributor
timestamp: June 15, 2025, 07:52:39 am
content: I'm not very good with VHDL, but what I noticed is that you have the ADC configured for left justified, (FMT is high) and the DAC is set for I2S (FMT is low).Not sure if this will lead to no audio output, but it is something to think about.To test if the DAC is working it is advisable to do what betocool advised, and write a FPGA configuration that sends samples, that alternate at some rate, to the DAC. So maybe 10 samples 0x00000000 and then 10 samples 0xFFFFFFFF. This should lead to a square wave output of 2400Hz at a sample rate of 48kHz.Follow the I2S signal specifications as stated in the datasheet of the PCM5102.If this works, you can try to forward the ADC data, but to make sure it will work, buffer the data from the ADC and setup two separate I2S interfaces for handling the data. You will need this anyway to be able to process the data in the FPGA.So de-serialize the ADC data into a double buffered register and serialize the data again to send to the DAC. The double buffering is needed to allow for receiving and sending at the same time.

author: dietert1
author_rank: Super Contributor
timestamp: June 15, 2025, 09:52:00 am
content: The FPGA code includes separate input and output shift registers and the data transfer is intended to happen here:Code:elsews_cnt := 0;ws_int <= not ws_int;r_tx_int <= r_rx_int;l_tx_int <= l_rx_int;But like this the data transfer happens twice in each left-right cycle and it should happen once. ws_int is the same as LRCK.One can debug such problems by simulation and probably that's the intended curriculum. Learning by doing! There is no debugging with the real FPGA, except you instrument your model to output more of the internal state. It depends on your "unused" FPGA io pins.Regards, Dieter

author: betocool
author_rank: Regular Contributor
timestamp: June 15, 2025, 11:54:19 am
content: Do you have access to simulation tools? I forget if you mention you're using Vivado or Quartus, both have integrated simulation tools.Best way to check the output is to have a 16 point array with a sinewave (that will be 3 KHz at 48 KHz sampling frequency) that you iterate over and over again and send to the DAC output. You can then check that the output values are correct, and that your settings are correct. It means a bit more tinkering with VHDL and learning about test benches, but it will help your development in the long run by avoiding lengthy compile and test times. Once you're satisfied your outputs are as expected, then program the FPGA and see what happens.The 22 Ohm resistor in series won't affect the output.Cheers,Alberto

author: Monsun
author_rank: Newbie
timestamp: June 15, 2025, 08:47:13 pm
content: "Some" Progress has been made and as always, thank you all so much for the help!What dieter suggested, was in fact true. I set up a Test bench for the Old code and realized that some stuff was messed up. I played around a bit with itand got it semi working. I decided to re-aproach it a bit. Instead of making one transceiver myself out of the digikey source, i used it as intended with a Top module and not changing anything in it.And we got SOMETHING at least. Although I am not sure what exactly, but I got some form of inaudible sound, which i could actually controle with Audio from my phone. So it would only appear when i actuallyplay a song.Note: for this i used the ordered Module and a monstrosity of a Setup with an Arduino as my 3.3V supply for the DAC and a Ton of Jumper wires and potential ground loops.The Signals were obviously not clean at all, but it did lead to some form of Output.I checked again the LDO voltage and Verified these:ADC:FMT LOWMDO,MD1 LOWDAC:XSMT HIGHFLT LOWFMT LOWDEMP LOW.Then I hoped, after getting some feel of progress, it would magically work on my PCB, and it was just because of the garage Jumper wire setup.But then again, silence. To me, since It did produce some form of Audio which some might even could argue as an Inaudible version of the bass of the song I played itnow must be the PCB??? I am in the lab tomorrow, swapping the DAC for my last replacement and triple quadruple check all connections another time.Also worth mentioning:After remounting the FPGA to the PCBi verified all the voltages from before and the CLK signals to be present at the right frequencies.Also, the FMT to high was another thing that was wrong, as pcprogrammer mentioned.Another thing I will try is as suggested again, send only all high all low, but this (At least with the PCB)It didn't work Yesterday, but that was with the old code. I will also try to get a working simulation in Vivado up and running for this code aswell.Also when using a Logic Analyzer I can see senseable data being transferred. I attached a screenshot of it as well.But again the DAC on the PCB quiet as one can be.I really don't know where this will lead, but one week left to find out!Thank you so much for all the help so far! At least I made a partially working grrr noise generator so far!

author: radiolistener
author_rank: Super Contributor
timestamp: June 16, 2025, 02:13:43 am
content: You could consider writing a simple test firmware for your FPGA that allows you to manually control all I2S signals going into the DAC from a script running on your PC (via UART or USB). This approach can help you verify whether the DAC is functioning correctly and rule out any PCB-level or power issues. Once you confirm that the DAC produces sound when driven manually, you can compare the waveform and timing of your full FPGA implementation against this known-good case to identify where things diverge. This method is often more efficient than debugging a full audio pipeline all at once, especially with limited time.

author: dietert1
author_rank: Super Contributor
timestamp: June 16, 2025, 06:21:28 am
content: The scope dumps above show a strange habit of keeping all traces merged into one. This is a pretty destructive way to use a multichannel scope. In order to compare the measurements you need to adjust the vertical position of each trace to keep them somewhat separate.

author: pcprogrammer
author_rank: Super Contributor
timestamp: June 16, 2025, 06:49:39 am
content: The DAC module works of 5V and has it's own 3.3V regulator on board. Feeding it with 3.3V could lead to problems, depending on which pin it is supplied to. This might explain the crappy sound, but to make sure test with only the DAC and a know signal generated by the FPGA.Attached is the schematic of what I made years ago to test the modules I bought on Aliexpress. Not my best schematic work but is shows how the modules are wired up to the STM32F303 module. The prototype board can be seen in the picture.

author: Monsun
author_rank: Newbie
timestamp: June 16, 2025, 02:49:18 pm
content: Big news!We got AUDIO. The suggestion on the Module from pcprogrammer was correct. I somehow didn't pay attention that these regulators werepresent on the board. It finally produced audio. Still shitty Audio, but Audio.Now, before trying to check more of the code if it is proposing any Issue, id like to get it running on the PCB.It of course didn't work again. But i kept measuring everything again.When measuring CAPP Charge pump flying capacitor terminal for positive rail:I see an Squarewave clock like signal at 1.5Mhz from 0-3.3V. (I think is expected?)VNEG: -1V (rather unclean)LDO pin: 1.8V stableAVDD, DVDD: 3.3VSCK: 12.228MhzBCK: 3.072MhzLRCK: 48khzDIN: Flowing as on the working module.XSMT: 3.3VNow to how i might still damaged it.I bypassed the low pass on the OUTL, OUTR pins. I used a jumper to connect it to my Analog Equalizer.Today i noticed, when its not connected, there is somehow 2V DC on it. It is most likely from a faulty connection on some resistorsi added to the Filter stages in a DIY fassion. If this damaged the DAC the old and the new might have been affected.I will resolder my last swap DAC and fix the faulty 2V from where every they might come.DC blocking caps wouldve probably been a good idea.Again, when comparing to the example schematic i found of the module(Not the exact same but i assume it's similar)I see no significant differences between the schematic and my layout. Only the resistors on the CLK input lines.I still plan on doing a proper Test bench setup as many suggested, but since time is spare i at least want to get the same form of Audio going on the Outputas I did with the Module. And also giving each channel a offset is definitely a good idea, but I didn't figure out how I can save My Picoscope settings correctlyso it doesn't forget it on each software startup.And yes it definitely needs a proper cleaning from all the flux and dust that has accumulated on it.And once again. Thank you all so much, without all these Ideas and approaches you suggested i probably would've given up.I also added some more closeups of the PCB + the Kicad files if anyone wants to take a look at the project itself.Also a cleaner Scope picture with the data correct alignment and transfer.I appriciate any further input and will give an update if stuff works as always!

author: pcprogrammer
author_rank: Super Contributor
timestamp: June 16, 2025, 06:22:44 pm
content: The problem is with you VNEG. I measure ~3V with my scope on pin 5 and it looks clean. On pin 2 I also see a 1.5MHz square wave ~3.3V. On pin 4 the same 1.5MHz square wave can be seen but now ~-3.3V.The output of LDO, pin 18, is ~2V.You can verify these voltages on your module of course.Edit: I don't have Kicad so can't look at your schematic or pcb layout. In your original schematic in the first post I see CPGND connected to ground, as it should be, but the close up of the board shows it might not be properly soldered or damaged at the pin 3 side.

author: Monsun
author_rank: Newbie
timestamp: June 18, 2025, 04:53:49 pm
content: Final UpdateI know I already said it a lot, but thank you all so much for the support.It now works flawlessly! The issue aspcprogrammerpointed out, was indeed a faulty cap on the DAC side.Further more i made another fatal error on the ADC side. I forgot to also AC couple it with a capacitor.The PCM1808 expects 2.5V centered Audio(Which it does via an internal 2.5V voltage reference) and therefor only few snippets which were pulled down to 0V centeredfrom the Phone made it even to the output. Furthermore, some audio parts were clipping over the negative maximum ratingfor the Audio input, and therefor produce garbage or all 0.Anyway, all has been fixxed, just some small adjustment stuff on the Equalizer, and we did it and still half a week until the Deadline!Here is a video of the Final result:Have a nice day y'all and cheers

author: pcprogrammer
author_rank: Super Contributor
timestamp: June 18, 2025, 06:54:53 pm
content: Well congrats on finally having a working setup.A valuable lesson in how to debug hardware.