Indexed pins in constraints file? - Page 1
Forum section: electronics / general

author: Shimonu
author_rank: Regular Contributor
timestamp: February 11, 2024, 12:33:35 am
content: Just started using an FPGA recently and got the master file for my development board. Something I noticed was how the pins were declared there using brackets, like thisCode:set_property -dict { PACKAGE_PIN "K12" IOSTANDARD LVCMOS33} SLEW FAST} [get_ports { LED }];set_property -dict { PACKAGE_PIN "K13" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED }];set_property -dict { PACKAGE_PIN "R10" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED }];set_property -dict { PACKAGE_PIN "R13" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED }];set_property -dict { PACKAGE_PIN "T13" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED }];set_property -dict { PACKAGE_PIN "R12" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED }];set_property -dict { PACKAGE_PIN "T12" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED }];set_property -dict { PACKAGE_PIN "R11" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED }];But how am I supposed to use them? I can't just declare LED as an output, I get an error that I can't declare LED as an array. I'm assuming this is to easily use the LEDs as a group but can I still just bring one LED into a top file? So are my options to rename them or use LED as a bus?

author: langwadt
author_rank: Super Contributor
timestamp: February 11, 2024, 12:43:38 am
content: you declare LED as an 8bit output port

author: glenenglish
author_rank: Frequent Contributor
timestamp: February 11, 2024, 01:45:50 am
content: yeplike this. now the tool will be able to connect the dots.(VHDL)GENERIC (NLEDS : integer :=8);Port (LEDS : out STD_LOGIC_VECTOR(NLEDS-1 downto 0)

author: hamster_nz
author_rank: Super Contributor
timestamp: February 11, 2024, 05:58:46 am
content: Quote from: glenenglish on February 11, 2024, 01:45:50 amNote that the signal name must match in upper/lower case, as well as in singular vs plural (note how the constrains used "LED", but this code snippet uses "LEDS".

author: ejeffrey
author_rank: Super Contributor
timestamp: February 11, 2024, 05:53:54 pm
content: Quote from: Shimonu on February 11, 2024, 12:33:35 amI don't quite get what you are wanting to do. You declare LED as a bus in the top level module but you can access them individually which the module body.

author: pcprogrammer
author_rank: Super Contributor
timestamp: February 11, 2024, 07:29:28 pm
content: In verilog you also list them as a bus like below.Code:module MyModule(output wire [7:0] LED);Within the code you can use either the whole bus or parts of it or just a single one.Code:assign LED = 0;assign LED[7:4] = 1;More on this can be foundhereorhere.

author: glenenglish
author_rank: Frequent Contributor
timestamp: February 15, 2024, 11:29:54 pm
content: verilog : "assign LED[7:4] = 1"VHDL would never allow such a thing ! More reasons VHDL is the real mans HDL.

author: langwadt
author_rank: Super Contributor
timestamp: February 15, 2024, 11:42:56 pm
content: Quote from: glenenglish on February 15, 2024, 11:29:54 pmyou like fishing?

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 16, 2024, 12:36:43 am
content: Quote from: hamster_nz on February 11, 2024, 05:58:46 amThe plural thing was fun.Regarding case, VHDL is actually case-insensitive so it doesn't matter. Still, for style and consistency reasons, I strongly suggest always writing a given identifier in exactly the same way case-wise. But it's not required.

author: AK6DN
author_rank: Regular Contributor
timestamp: February 17, 2024, 08:09:59 pm
content: Quote from: pcprogrammer on February 11, 2024, 07:29:28 pmBetter to write:Code:assign LED[7:4] = {4{1'b1}};orassign LED[7:4] = 4'b1111;as what you have written is really:assign LED[7:4] = 4'b0001;