HDMI TMDS CLK issue - Page 1
Forum section: electronics / general

author: maszoka
author_rank: Newbie
timestamp: August 14, 2015, 02:24:56 am
content: I am working on bringing video from a HDMI connector into an FPGA via an ADV7611.When in freerun mode, I receive correct 1080p30 video from the ADV7611.However, I can not get the ADV7611 to lock to my HDMI source (embedded PC).When scoping the TMDS CLK pins, I see a 68.6 MHz clock, instead of the 74.25 MHz clock that I expect.The rest of the TMDS data pins look healthy otherwise (substantial voltage swing, seemingly differential signals).When I connect the HDMI output to a HDMI splitter that I took apart so I can monitor signals, and connect one splitter output to a monitor, the monitor displays the 1080p30, and I can see a 74.25 MHz clock on the TMDS CLK signal.If I connect my board under test to the other end of the splitter, it does not drive my HDMI input.Any ideas what this may be, or how to debug further?Thanks, Gabor

author: dgtl
author_rank: Regular Contributor
timestamp: August 14, 2015, 08:44:32 am
content: On some of the AD HDMI parts, they had some magic values, that had to be written to some registers to tune the PLL. Iehttps://ez.analog.com/message/29105#29105. Read the information about their other HDMI chips as well, some of them are quite similar and some tips about other chips have helped me a lot on my projects.

author: wraper
author_rank: Unknown
timestamp: August 14, 2015, 09:02:53 am
content: Obviously wrong EDID data is provided to the PC or wrong or resolution / refresh rate selected on the embedded PC. Check the EDID data PC gets, with a program like Extron EDID manager.

author: maszoka
author_rank: Newbie
timestamp: August 14, 2015, 05:09:59 pm
content: Thanks for the quick responses!@wraper: EDID is the most likely culprit. I am using the advantiv EDID editor, and created an EDID set from scratch. When connected to the embedded PC directly, the PC displays the vendor / product ID as specified in the EDID file, and selects the only mode supported (1080p30) by the sink. This makes me believe the EDID is correct, or at least the IIC connection is healthy. Could the EDID specify the TMDS CLK rate to be used by the HDMI source?@dgtl: could these settings affect the HDMI source TMDS CLK rate? I thought the magic register setting influence how the AD7611 processes the stream, but not affect the negotiated standard between the sink and source. I can be wrong - in fact if this issue can be fixed just by programming registers, that would be awesome!

author: wraper
author_rank: Unknown
timestamp: August 14, 2015, 05:43:39 pm
content: Quote from: maszoka on August 14, 2015, 05:09:59 pmI don't know anything about AD7611, but if you provide EDID, PC won't care about anything else. There is no refresh rate in detailed timing descriptors of EDID at all (and 30Hz cannot be standard timing anyway). Only resolution, some other stuff andpixel clock(refresh rate appears naturally out of them). If pixel clock is wrong, either you created EDID with timing containing wrong pixel clock or there are multiple timings in the EDID and the wrong one is selected by the PC. Anyway, check your EDID with Extron EDID manager and see what it says in the report.

author: maszoka
author_rank: Newbie
timestamp: August 15, 2015, 12:23:40 am
content: @wraper: Thanks a bunch! I installed the Extron EDID manager, and it revealed an incorrect pixel clock settings (specific timing definition in the VESA block)! Now the TMDS CLK freq is ~74.25 MHz as expected. Thanks again!