PCB Design Review: USBC, 4 Layer PCB, Decoupling caps, Vias to power plane - Page 1
Forum section: electronics / projects

author: makestuff4fun
author_rank: Newbie
timestamp: March 06, 2022, 02:32:11 am
content: Hi All,I've been working on a PCB design and have run into some problem. The problem is I don't know the best way to layout certain things and could really benefit from some help.4 Layer PCB, with 0.1mm pre-preg height between top layer and GND plane, same between bottom and power plane. PCB thickness 1.6mm1oz outer layers, 0.5oz internal layers. JLC2313 Stackup. However I don't think the stackup is critical to these question.L1 SignalsL2 GNDL3 PowerL4 SignalsL1/L4 do not have any ground poor.1. When is it better to route with vias to bottom layer vs. staying all on top layer? For example look at the routing for W25Q80BV. I could have had "prettier" traces using vias, but this avoids layer changes and there is then a solid ground plane underneath.Servor S wire, labelled PB31 at the bottom of the PCB could be routed on the top layer but the trace would be 3 times as long as it would need to go all the way around the outside of the board.These signals are not high enough speed to need length matching, pretty sure, but how to decide when to use vias vs not?2. USB C differential pair needs to be shared between 2 sets of pins so there must be vias with this socket. I matched the length to the first pair of pins, then matched length to the second pair, so both are matched, but the "stubs", if that's the right term, are now 3mm or so which seems very long.Alternatively, I could route to B6 A7 as a pair, then have stubs on the top layer only, connecting to the other set of pins but them I'm not sure how to length match both sets as the connection are in pairs A6/A7 or B6/B7. Please see "altusb.png". The pair actualy needs to be swapped for this but by coming out the back side of the uC pins, the traces are still on the top layer with no vias needed.3. ESD diodes for USB (or network). Is it better to connect as a "V" in/out of the pad, or is it equivalent to just use a branch? You can see what I mean by "branch" in altusb.png. usb_layout.png shows the "V" style I'm talking about.4. With a power plane, what's the best way to connect decoupling caps and ports? If you look at the USB port again, I've connected VUSB to the power plane, but I could have simply used traces. The split in the power plane should have no effect as all the traces are referenced to the solid ground plane, but how to decide which way to do it? Similarly C16, decoupling cap for W25Q80BV, I have it connected with a trace to the power pin and a via to GND plane. Is this the best way? I'm limited as I cant connect to the GND pin directly as I chose to route all my signals with no vias on the top layer.If you see any other issues or places that could be improved, I'd love to hear about. I just want to make better layouts.Thanks a lot.

author: makestuff4fun
author_rank: Newbie
timestamp: March 06, 2022, 02:37:57 am
content: I just realized the images don't show the pin labelling for the USB connector to show which are A and B sides of the connector. I've added 2 images for clarification.Thanks

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 06, 2022, 11:13:42 am
content: 1. Doesn't matter, electrical length is far shorter than the signals care about (that's going to be at most, what, 50MHz Q/SPI, with few-ns edges?).You also have enough width/space to get traces between SOIC pads.BTW, keep enough clearance between vias and pads, so they don't suck up solder. Alternately, fully tent them (top and bottom).- Also note, anywhere you have vias, you have negative space (clearance) in the opposite plane(s). A close row of vias can break quite a slot in the plane(s). Around the MCU? it doesn't look dense enough to be a problem so that's good, but there is the column of vias on the LCD? connector that might be tight enough to do this. These could alternate sides to double the spacing in each column.Generally speaking, I don't like more than three or four vias in a tight group; if working with higher speed / low noise signals, try for fewer around the respective traces. Further: where e.g. a high speed signal or diff pair crosses layers, a bypass cap or two can be added adjacent to the via(s), so that the image currents can transfer from top to bottom, through the cap and plane impedances together.- Speaking of caps: anywhere you have bypass caps, you can basically double their effect by flanking both sides with vias. The via and trace inductance act in parallel this way. Whereas the lengthwise arrangement has maximum component body, trace and via inductances. The trace can also be wider, or obviously shorter, up to whatever limit the via (tented/not) dictates.2. If I should assume this is USB Full Speed, it's just another CMOS logic signal. Differential routing doesn't matter, length matching doesn't matter, trace impedance hardly matters. Not at least to any kind of scale that would matter on-board. If it's High Speed, these lengths are still within tolerance (check the spec, it's free), and indeed you can still do...- ...Why not route USB through the other pair of ESD diodes? Can bulge out around the power pins, so the connector-facing pair picks up the inside corners (diagonal connect) of pins e.g. 1 and 6, traces loop around 1-3 and 6-4, and diagonal connects to 3 and 4.Probably not even a big improvement, as clamping performance is limited by power pin inductance (again, can use wider traces/vias -- treat these pads as if a bypass cap), but it'll still account for the ESL of the clamp pins themselves, and internal resistance, acting in parallel so dropping the peak clamp voltage.And I'm guessing it's a one of those diode-clamp-into-TVS types, so you're not at risk of blowing out line capacitance limits in this way.In any case, get rid of that extra trombone length under the connector, that's not doing anything for 'ya. Also regarding the alt: avoid acute angles, mainly just 'cuz they look bad. The tee joint can be a tee, angling it towards the connector pad doesn't do anything.Also the, what's the short other connector, oh maybe it's a really stubby uSD slot? ESD diodes might be desirable there, though if it is indeed SD, yeah doesn't really matter.Or the big pins on the right edge, no idea if those see any kind of current, or what the series chip components are (current limiting? filtering?), but the size of the connector suggests some amperes of capacity so the traces look rather thin in comparison. Also if those are resistors, wider traces can be used to improve heat dissipation from them. And the transistors? driving them, either should be digital/prebiased BJTs (if low current outputs), or should have series resistors at the MCU, whether for  BJT (current limiting is mandatory!) or MOSFET (series gate impedance reduces EMI and risk of oscillation).3. V is better. The difference in stub length is only a few nH, but strictly speaking, that's a few nH saved.4. Doesn't matter, it's just a dumb connector. Like you say, signals are on Top / ref GND so this layer is irrelevant. You might still route it on Mid2 or Bottom for convenience (also, is there a keepout area under the connector body?).- Also note that the big slot in the middle (LCD cable passthru?) won't have square corners. If you need square corners, relieve them with an extra cutout with a specified radius. Or specify what radius you actually need. Typically board rout is done with 1mm, and finer will cost extra for tool change/wear. It looks more than wide enough so that a little rounding won't matter here, but FYI -- avoid ambiguity, and extra-tight corners, when it does matter.Y'know, this is pretty low density overall anyway, it could be just two layers. The planes aren't doing anything that a well-stitched top/bottom pour can't do, and with direct routes for most signals, there aren't even a lot of crossings. (Crossings are critical in 2-layer builds: you always want a trace over an opposite pour, so crossing traces create a negative space on both layers. Keep these areas small -- bunching traces into buses say -- and stitch around the crossing with 3+ vias to minimize the loop area for currents flowing around the edge of that negative space.)And, that's about everything I see. Maybe you'd like a TVS on VBUS, looks like it's supplied from/to several connectors? Can mitigate problems with hot-plugging. Likewise some supply impedance to the uSD can avoid brown-out on hot-plugging (cards are allowed up to like 8.2uF onboard, compare that to your board's total 3V3 capacitance! -- and likewise, they're allowed onboard bypass, don't worry about trying to bypass the pins at the connector, some impedance here is fine, say a couple ohms as current limiting). Don't know what your regulator is like, if it needs ESR or other compensation. Do see a lack of thermal vias on it, but maybe the load and drop are small enough not to matter. RS-485?, maybe some ferrite beads or additional filtering, but it's somewhat uncommon for it to be an EMI problem, it's a well behaved standard.Tim

author: makestuff4fun
author_rank: Newbie
timestamp: March 07, 2022, 01:15:35 am
content: Tim,Thank you so much for taking the time to review my layout. I very much appreciate it. I'll implement your suggestions.I chose a 4 layer board only to reduce the risk of issues. 2 Layer board would be basically free, and 4 layer $20. However this particular MCU is out of stock and I had to pay about $30 each for those (instead of say $6). I just didn't want to risk the 2 layer because of the cost of the MCU.I'll add the TVS diode, maybe ESD on the SD card, remove the trombone on the USB C (only used for loading firmware). Outputs are Mosfets that drive SSRs, can add a resistor footprint on the gate and use 0R resistors if they end up not needed. The output current is 25mA or there abouts. very low current. I'll split up the lines of ground vias for better ground plane. I'll also add some more vias to the voltage regulator.It's interesting you mention vias sucking up solder, as some QFN put vias under the chip. I guess those should all be marked as fully tented? I will give them some more space on this board for sure.Good point about the cutout. I think I have clearance enough (it is for the cable for a small LCD). I have had issues in the past because cutouts didn't have rounded corners.This is just a control board for my reflow oven. My current control board has lasted 5 years or so but is starting to act up. Just upgrading to something with color screen.I can't thank you enough for taking the time to give such comprehensive reply.I've added the, messy, schematic in case it can be useful to someone else.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 07, 2022, 11:45:36 am
content: Via-in-pad is a compromise; for interior pads, you have no choice (QFN, LGA, fine pitch BGA). In that case, either:- If you have enough space available (pad area >> via area): the vias can be tented. Note this leaves a void of plastic (soldermask) between the pads, which will accumulate some flux and gas during soldering. That is, it's a void in any case, and the outgassing can leave even bigger voids. You can't tell, externally, short of x-raying the whole thing.- Order plugged or capped vias. The vias can be filled with copper plating (if thin enough), or conductive (or non-) epoxy, leveled, and plated over. Looks sexy, but costs several extra steps, in a custom fab run.- Use untented vias, and accept the solder wicking in. This is the usual case, and works out because there's usually enough paste on the thermal pad that the component tends to float up anyway. Also, using fine vias (<= 0.3mm), solder tends to wick slowly into them, and using less-"wet" solder (lead-free), even more slowly still. Often you don't see any solder on the backside of a grid of vias sinking a modest-size QFN pad.Note that you don't want one-side-tented vias; the back side is likely to get plugged, and now the barrel fills with bubbling flux, leaving even bigger voids.Note also that, if you want to make tented vias in a pad, usually the pad soldermask opening takes precedence, and the top side won't get tented at all. You need to tent both and craft a custom soldermask opening.By the same logic, via-in-pad might be justified for other components, but anything with a lead, or metallized body, can form a toe, heel or side fillet which both increases strength of the joint, and is visually inspectable (no x-ray required). So you don't want to steal (or risk) much solder going away, particularly on small pads. And most components will be small, so won't have much if any solder to spare. I'd probably consider a 12 mil i.d. via in a 1206 or larger chip component, if I had to?There's also the "tenting not tenting" method: shrink the soldermask expansion so that it comes right up to the hole, plus fab clearance (typically +3 mils). This looks tidy, but avoids the risk of blocking off holes, and you can get it a bit closer to a pad than a fully untented via. I typically do this when I have no reasonable expectation of needing a connection to the via in question: if the net already has a test point, I don't need an untented via to serve the same purpose. And you can still solder to them, albeit with difficulty.I do tend to fully tent general GND, power and stitching vias. Leaving a few untented, and perhaps extra-large (20-40 mils i.d.?), in power/GND, scattered around the board, is a good idea to get easy access to them (without having to excavate down to the power plane -- which is doable!).FWIW, a friend has documented a similar project here:https://www.moltensolderlabs.com/projects/reflow-ovenTim

author: makestuff4fun
author_rank: Newbie
timestamp: March 07, 2022, 01:28:17 pm
content: Thanks for the detailed explanation of tenting vias and vias in pads. I do usually tent all my vias for ground pours. I actually haven't given it much thought. I setup the rule to be that way and then make test pads scattered around like you say. I think I've been unintentionally having 1 sided tented vias on my QFN footprints. I will make sure to change that right away. I haven't had to dig down to a power plane yet, but I can see how that would need some skill!I was re-reading your initial reply and never answered if I had a keep-out under the USB connector. I don't have one. When would I want a keep-out under parts and connectors?It's interesting you link to that post. My adventure in reflow ovens started by also making a controleo2 compatible PCB back in 2015. You can see my post here :https://makestuff4.fun/2015/08/29/controleo2-compatible-reflow-oven-controller/I added an LCD to graph the temperature and it's been used a lot.It actually used to be quite a popular post on my old site, but got moved to a new domain after the server got hacked and never regained it's former popularity.This PCB is a controloe3 compatible board, if it worksI really appreciate the work Peter Easton did on the original design and his open source software.Thanks again for the help and I'm sure you've saved me trouble with QFN parts on my future boards!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 07, 2022, 03:04:54 pm
content: Hah, nice!I realize that was kind of oddly ascribed -- I mean if the USB connector itself wants a keep-out. SD sockets and other things sometimes call these out, too. The purpose might be to ensure flat seating, in case something might bump out that side of the connector, or just to avoid sliding wear (like an SD card sliding completely against the board, if applicable?). Or just to avoid concerns of poor insulation, because soldermask really isn't much of an insulator (it's prone to pinholes) and putting a solid piece of metal on top (e.g. connector body) could short out anything under it.That connector looks like the kind with thru-pin mounts and SMT pins, probably clears its underside okay so doesn't need it? Some do, some don't. And not that it matters here either -- you've routed nothing under it, besides that trombone trace in the first example. Put another way: just a heads-up to check the datasheet/drawing, maybe it was already checked when the library part was made (by yourself or someone else), maybe worth double checking, etc. A few minutes getting it right, right now, is well worth the couple weeks delay to order a replacement.Tim

author: TimCambridge
author_rank: Regular Contributor
timestamp: March 07, 2022, 04:37:32 pm
content: Small points:- Put some pads under the USB-C connector, vias to ground. To give a bit more adhesion.- If there's a chance that this could be driven from a USB-C host, you need pulldowns on CC1 and CC2. There's a Microchip app note for this called somthing like "simple USB-C". Don't be tempted to save a resistor by sharing it between CC1 and CC2.- That ESD part looks tough to source, but maybe you have a supply.Cheers

author: makestuff4fun
author_rank: Newbie
timestamp: March 08, 2022, 01:22:19 pm
content: Thanks again. That's a good idea. It such an awful feeling when you bend the USB port off a PCB. I've had that happen a few times for sure.Microchip app notehttps://ww1.microchip.com/downloads/en/AppNotes/00001914B.pdfAdding the 5.1k CC resistors is a good idea. In theory, the device could even be powered by USB.Thanks again. I'll try and post the final version and assembled PCB.

author: crgarcia
author_rank: Regular Contributor
timestamp: April 04, 2022, 02:40:29 pm
content: Quote from: T3sl4co1l on March 06, 2022, 11:13:42 amWhy is that?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 04, 2022, 05:41:45 pm
content: Quote from: crgarcia on April 04, 2022, 02:40:29 pmThe proceeding paragraph:Quote from: T3sl4co1l on March 06, 2022, 11:13:42 amHm, opposite? Any planes they go through, anyway.Tim

author: DavidAlfa
author_rank: Super Contributor
timestamp: April 05, 2022, 12:46:36 am
content: USB spec says the differential skew is limited to 5ns in FS(v1.0) and 100ps in HS (v2.0).Light travels 300mm in 1ns. The speed in the pcb depends how it's constructed, but I've found the slowest to be ~140mm/ns (Velocity factor of 0.47).That USB-C conector has 0.5mm spacing, which is length error you're making by routing that way.0.5mm would cause a worst-case skew of 3.6ps. So you're completely fine doing this!

author: makestuff4fun
author_rank: Newbie
timestamp: April 05, 2022, 01:02:21 am
content: I've made progress on the project. I made a rookie mistake on the first revision of the PCB. Since it's reverse engineered, I'll give myself a pass. I forgot the 8 data lines for the LCD. I wired them up manually on the first PCB and verified they were correct and then made second version of the PCB. The attached pics are the second revision of the PCB and I've installed it on my reflow oven. It works great.I have a custom bezel being printed that should arrive this week. I'll update the final build pic when that arrives.

author: makestuff4fun
author_rank: Newbie
timestamp: April 05, 2022, 01:05:46 am
content: Thanks. I can also confirm is works with that basic layout. Here is what I ended up going with. I played around with a USB switch but dropped the idea as controlling the switch from the CC lines on the USB C port involved an IC I didn't have and didn't seem worth the effort.You might notice the width of the traces changed from the previous pics. I changed the stack-up so I could get the PCB In black. The distance between layer 1 and 2 went from 0.1mm to 0.2mm.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 05, 2022, 10:11:47 am
content: Oh sheesh... yeah, data lines might matter.Good work wiring them up!Tim