Odd instabilities with level shifter 5V <-> 3.3V for SPI - Page 1
Forum section: electronics / projects

author: kalj
author_rank: Contributor
timestamp: March 21, 2021, 09:34:30 pm
content: I am building am combining a Raspberry Pi Zero with an LCD display based on NT7108 (right lcd/wrong lcd) through an SPI IO expander (MCP23S17). Since the Raspberry Pi has 3.3V IO whereas the LCD uses 5V, I use an Adafruit TXB0104 level converter breakout board (https://www.adafruit.com/product/1875). See the attachments for how it is connected (excuse my crappy sketch and messy breadboard hookup).As the LCD indicates, writing to the display seems to work okay, at SPI speeds up at least several MHz, so that is all fine and dandy. However, I am seeing some quite weird instabilities on the MISO line making read backs unreliable.I initially saw the problem when using twice as long wires between the Pi and the breadboard, but after switching to the shorter wires shown above, I could confirm that the problem is still there in the current setup.Oddly enough, the problem goes away if I do any of the following:a) Connect an extra 100nF capacitor between 3.3V and GND on the breadboard (note that the TXB0104 BoB already has one).b) Connect an oscilloscope probe (!) to the MISO line on the 3.3V side.So, the question is: What could be the cause of this weird behavior, and what could be done to treat it? Eventually, I want to make an adapter PCB for the display with the level converter and IO expander, so I want to make sure I don't design something which doesn't work reliably.Also, I have not settled on the TXB0104 for the level conversion, so if someone has any other suggestion, that is welcome too.

author: dmendesf
author_rank: Frequent Contributor
timestamp: March 21, 2021, 11:03:46 pm
content: I once lost a lot of sleep with one of those bidirecional level converters. I think I solved it with pull up/ pull down resistors. The problem was as soon as CS was reasserted the MISO floated and the level converted started oscillating. I never trusted these again and only use directional converters.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 22, 2021, 12:02:36 am
content: Yeah, those things are a scam. Sorta. They work when the transmission line lengths are short, and the impedances reasonably stable. Probably, your jumpers are enough already to make it chatter, with a combination of high impedance (to a poorly coupled ground?), and length.You indicate directions on the drawing -- just use a fixed or selectable (wired to VCC/GND) translator. Twas a cheap lesson.Tim

author: mvs
author_rank: Frequent Contributor
timestamp: March 22, 2021, 12:05:52 am
content: Quote from: kalj on March 21, 2021, 09:34:30 pmYou can try to power LCD from 3.3V. 5V are usually needed to generate LCD bias voltage (V0 pin) only.

author: WattsThat
author_rank: Frequent Contributor
timestamp: March 22, 2021, 12:19:57 am
content: You’ve posted a link to an LCD datasheet that that is an I2C part, not standard parallel. I found that confusing until I studied your photograph.You should place the 100nf capacitor directly on the connection points of pins 9 & 10 of the MCP23S017, not off on the power rails of the breadboard.There is a lot of resistance in all those breadboard connections. In other words, don’t count on the capacitor of the TXB0104 breakout board to be effective. It’s too far away through all those crappy (high resistance) connections of a breadboard and it is there for the chip on the breakout board, not for the rest of the circuitry that is off of the board itself. Breadboards introduce their own instabilities, especially at bus speeds which you control with Rpi. Where do you have the SPI speed set?Also, how long of a run are your SPI wires? That too is a big factor in success.

author: Ian.M
author_rank: Super Contributor
timestamp: March 22, 2021, 01:00:47 am
content: For 5V SPI slaves on a 3.3V master:Use any 74HCT non-inverting logic gate, powered at 5V for 3.3V to 5V translation of MOSI SCLK and /SS, as HCT logic's TTL input thresholds are 3.3V CMOS compatible. e.g. 74HCT32 Quad OR with one input of each gate strapped to Gnd or 74HCT08 Quad AND with one input of each gate strapped high, will translate 4 signals, so ideal for the Pi, which has two /SS pins (/CS0, /CS1).For downwards translation from 5V to 3.3V of MISO, use74LVC1G125single tristate buffer, powered at 3.3V, which has 5V tolerent inputs with its /OE input driven by /SS so its output is disabled when the specific /SS is deasserted. There's also the74LVC2G125, which is the two channel version, a good choice if you have two 5V SPI slave devices. Wire the 5V side MISO signals separately to its inputs, the separate /SS signals to its /CS pins and parallel its outputs to Pi MISO.However, if your display really has an I2C interface, then why the <expletive> <expletive2> don't you hook it up to the Pi's I2C bus via a suitable I2C level translator? e.g. for each line a low Vgs threshold small signal N-MOSFET, gate tied to 3.3V supply, source to the 3.3V logic signal, drain to the 5V logic signal, with pullups to the respective supply rails either side of it.

author: gnuarm
author_rank: Super Contributor
timestamp: March 22, 2021, 02:14:55 am
content: Quote from: mvs on March 22, 2021, 12:05:52 amI researched this for a project using a 2x16 display parallel port and you are right. The LCD controller chip works fine from 3.3 volts and probably works down to much lower voltages as well.The LCD multiplex drive voltages are from a resistor divider chain tied to Vdd on one end and V0 on the other. Typically it needs V0 to be about 4 volts below Vdd. On LCD modules which are intended for 3.3V operation they include a 7660 chip to generate a negative voltage which the external pot is connected to for setting this V0 voltage.I would not use a voltage translator for the comms signals. I would use a 7660 to generate a negative voltage for the LCD V0 bias. If a spare pin is available on the MCU a pin can be used with two caps and two diodes to generate the negative voltage with no chip. I added the resistor R1 to limit the initial surge current from the MCU pin, you might want to make that 220 ohms if your MCU can't drive 20 mA.I would also point out that the OP is talking about using an SPI interface but the LCD has an I2C interface according to the data sheet. I'm not sure if he is mistaken or can't drive the I2C directly from his MCU.

author: kalj
author_rank: Contributor
timestamp: March 22, 2021, 03:28:43 am
content: Hey, sorry for the confusion regarding the lcd, the original link was wrong. Here is the correct part:lcd. I've also clarified the original post.

author: gnuarm
author_rank: Super Contributor
timestamp: March 22, 2021, 04:35:18 am
content: That is a horse of a different color. But in some ways it is worse. They don't specify the input or output logic levels of the signal pins. So you are going to need to assume the worst.I guess you need an I/O expander as you have in your original drawing. If that is 5V then you just need a level shifter for the few pins going to that part.You can use a switch type part that doesn't drive to 5 volts, but will allow pullup resistors to pull up to 5 volts without the other side seeing that voltage. So the 3.3 volt side only sees 3 volts while the pullup resistors provide 5 volts on the other side. The switching is still fast since the I/Os are driven to 3 volts hard, then the resistors pull up the rest of the way.A part I've used is the SN74CBTD3384CPW. But that is 10 signals in a 24 pin package. You only need a handful, so an 8 bit version will work fine for you. No need to worry with signal directions or switching the direction.

author: ConKbot
author_rank: Super Contributor
timestamp: March 22, 2021, 06:04:06 am
content: I'm also in the camp of disliking the TXB series shifters, unless true bidirectional is needed, I.e. I2C busses. They caused me their fair share of pain. Cursed serial ports on nvidia TX2 modules with bootstraps, that can't tolerate their pull ups (the TXB's got used everywhere on the factory carrier except those ports, didn't pick up on that), or them managing to pick up stray noise on relatively well isolated traces and feed garbage into a console serial port causing grief there, even with additional pull up resistors etc.Since adding more capacitance helps, obviously it's a power distribution network problem, which makes sense, as the shifters put out pretty sharp edges (they are "good" for quite a few Mbps for pushpull signals), so adding more high frequency decoupling helps the voltage rails stay stable. The probe capacitance helped slowit down and ignore the power glitch for that case, but it isn't ideal.Either way, with the TXB, or using a single direction solution, modern logic ICs can be damn fast, extra attention to decoupling is always good. When you're in the 1-2 ns range for rise and fall times, you're looking at hundreds of MHz of bandwidth in a signal or the current impulse into the IC. And when the IC is the TXB series having to play logic threshold games to figure out which end is being driven, a messy power rail makes for even messier thresholds.

author: Berni
author_rank: Super Contributor
timestamp: March 22, 2021, 06:38:44 am
content: Yep avoid these automagical bidirectional level shifters like the plague!They do work surprisingly well in a lot of cases and they are convenient to use since you don't have to worry about what way around it goes. But there is always a few situations where they mistake what direction the signals are supposed to be going and cause all sorts of weird problems, they also tend to get confused by pullups in some cases. Said problems may even be intermittent and very difficult to debug, along with something inconspicuous as a level shifter typically being one of the last things to suspect and check. Just use regular unidirectional level shifters and take the extra 10 seconds to check what direction they are supposed to be pointing, it saves a lot of cursing later.Oh and running SPI over too long of a ribbon cable can also cause issues. The crosstalk of the tracks can inject bumps into the clock line and make it stop working even at low clock speeds, similar can happen with the CS line but not as easily. You want to run the clock on the edge of the flat cable with the wire next to it being ground. But optimally its best to have a ground wire between all of the signal wires, so half the wires are ground half are signal. This solves the crosstalk issue completely and lets it work with surprisingly long ribbon cables and high clock speeds.(Until the roundtrip delay on MISO gets too long)

author: gnuarm
author_rank: Super Contributor
timestamp: March 22, 2021, 07:07:27 am
content: Yeah, the SN74CBTD3384CPW is not a level shifter, it's a level limiter. It is pass transistors that essentially connect one side to the other without going through drivers. The 5 volt rail is dropped by an internal diode so combined with the gate threshold voltage the pass transistors turn off above about 3 volts. So the 5 volt side can't cause harm to the 3.3 volt side and the 3.3 volt side drives at full strength on the 5 volt side up to about 3 volts with pullups taking care of the rest.I guess I'm a bit surprised there isn't an I/O port expander that can be driven by 3.3 volt devices but drives 5 volts on the outputs. I see TI has one with an I2C interface, TCA6416A

author: kalj
author_rank: Contributor
timestamp: March 24, 2021, 07:43:19 pm
content: Thanks all for the answers. So what I have gathered:1. I will stop using the haunted bidirectional converter (since I don't need it anyways). Instead of that, I need one 5V -> 3.3V converter for MISO, and four 3.3V -> 5V converters for MOSI, SCLK, CS, and RST. I looked at the SN74LVC1G125, but also found the even simpler SN74LVC1G34 (always on non-inverting buffer). I guess I can use these in both ways, however, it would be cool if there were a single 4-line chip so I can save some space. There doesn't seem to exist a four-channel version of the SN74LVC1G34. Any tips for suitable parts? Preferably no smaller than SO/SOIC or SOT-23 since I am scared of hand soldering SSOP. I guess the SN74LVC125 is one option although it has tri-state which is useless for me.2. I will try to minimize signal problems by interleaving some ground lines in the cable to the Pi. I am including images of the LCD PCB that I am working on (with the level converters missing). I guess lots of 100nF decoupling capacitors would help too. I'm thinking one per chip, even for the one-signal SN74LVC1G34?

author: Ian.M
author_rank: Super Contributor
timestamp: March 24, 2021, 09:36:51 pm
content: Always on ('1G34) is only OK if you have a *SINGLE* SPI slave or all your slaves are 5V so you can combine their MISO signals before the translating buffer. If you have more than one at different voltage levels, you *NEED* individually tristatable buffers.With only one slave, you could use the previously mentioned 74HCT32, with a 1K8:3K3 potential divider to drop its fourth gate output to 3.3V levels.If you are desperate to save space on the LCD board, you could swap to the I2C version of the port expander, MCP23017 with two BSS138 N-MOSFETs to level shift the I2C SDA and SCL in the classic Philips level shifter circuit.Ignore the 'TX' in the net lables, its equally applicable to I2C SDA and SCL.You can omit R2 on the 3.3V level side as the Pi has built in I2C pullups. Put the MOSFETs and 10K resistors on the 5V side as close as reasonably possible to the 5V I2C port expanded, and use narrow tracks, to minimize the track capacitance and get good risetimes on the 5V side in spite of the high 10K pullup value.It is unfortunately significantly slower than the SPI version, due to the 400KHz max I2C bus speed on the Pi, whereas the SPI version can be run with an 8MHz SPI clock (if you are feeling brave, have grounds in between the signal lines, and maybe even RC (AC) load termination to match the cable impedance and damp ringing).

author: kalj
author_rank: Contributor
timestamp: March 25, 2021, 05:47:09 am
content: The LCD is the only SPIslave there will be, so it can hold the MISO line indefinitely. Regarding priorities, speed is still too important to use I2C. Besides, as you see I think I have plenty of space left on the board. I think I was mostly thinking about component count. But even that is not a big deal.Performance, correctness, and simplicity is what matters the most.

author: Berni
author_rank: Super Contributor
timestamp: March 25, 2021, 06:19:46 am
content: Yep the mosfet level shifter from Ians post is the one bidirectional shifter that actually works.Only issue with it is that it only drives the signal high using a pullup. This is fine for something like I2C where you need pullups anyway, so its the perfect solution for shifting I2C. But when it comes to SPI stuff tends to run in multi MHz clock speeds and those might need a bit more than just a pullup to drive properly.And yes the unidirectional level shifter can be a problem in cases where you have a mix of 5V and 3.3V devices on the same SPI bus. This tends to be fairly rare since SPI is generally used for only a few devices per bus, but if you had to do it then you can still use a level shifter that feature a OE pin and tie that to the chip select.

author: Ian.M
author_rank: Super Contributor
timestamp: March 25, 2021, 06:34:48 am
content: So why not future-proof your LCD board by designing it using the 74HCT32 quad OR for MOSI SCLK and /SS upwards level shifting, with two options for downwards level shifting of MISO:1K8:3K3 divider on output of fourth gate of the quad OR74LVC1G125, gated by /SSIn both cases 5vMISO goes to the OR gate input. You select which to use by populating either the resistors for (1) or the '1G125 for (2).As the cheap board houses typically send you five to ten boards for cheap one-off designs, I'd also put in a footprint for a header on the 5V side of the level shifter so you can omit the level shifter components and reuse it in a pure 5V application, and if I was feeling particularly pissy and scrooge-like I might even look at providing the option to drop in a MCP23017 for an I2C version, with footprints for optional MOSFET level shifters, pullups, and for jumpers (zero ohm or solder) to set the I2C address.

author: mrburnzie
author_rank: Regular Contributor
timestamp: March 25, 2021, 08:48:05 am
content: I would recommend using digital isolators that are bidirectional.This is what I used in my latest design:http://www.ti.com/lit/ds/symlink/iso1541.pdfOf course you don't have to use it for i2c...

author: gnuarm
author_rank: Super Contributor
timestamp: March 25, 2021, 05:08:21 pm
content: Quote from: Berni on March 25, 2021, 06:19:46 amIt does not work as well as it could if the gate voltage were higher. Parts like the SN74CBTD3384CPW are designed with a diode in the power path. This puts the upper limit of the drive through voltage right around 3.2 volts. So the 5 volt signals safely drive the 3.3 volt interface and pull ups are needed only on the 5 volt side.Even on the 5 volt side the active drive is to 3.2 volts while the 5 volt CMOS upper threshold is 3.5 volts, so only 0.3 volts to go using the pull up before being completely compliant. In reality the threshold is much closer to 1/2 Vcc or 2.5 volts. So in any but the most extreme cases of temperature, voltage and process the threshold is met by the rapid, active drive.If you can't find a part to suit you in the 74CBTD family, you can use a regular CMOS switch and add the diode from the 5 volt power rail yourself. Just don't use a Schottky.

author: Ian.M
author_rank: Super Contributor
timestamp: March 25, 2021, 09:00:46 pm
content: Biassing the MOSFET level shifter off a supply rail that's higher than the target voltage is dodgy as heck if you are using discretes. An IC designer has much better control of the MOSFETs Vgs_threshold matching and can arrange to generate a bias supply very close to one Vgs_threshold above the target rail.The best you can easily do with discretes (without select on test or hand trimming horrors) is to select a *VERY* low Vgs_threshold MOSFET, typically with a Vgs_abs.max of no more than 5V (just enough to reliably survive 1V of undershoot on the signal with the gate at 3.3V+10%). If the threshold is under 0.8V, the translated logic '1' will be over 75% of the 3.3V side Vcc (good enough) so you only have to worry about the pullup and RC time constant with the stray capacitance on the 5V side, from a starting point of Vcc/2, which is where the MOSFET stops letting through the rising edge from the 3.3V side.

author: gnuarm
author_rank: Super Contributor
timestamp: March 25, 2021, 11:03:23 pm
content: The issue of discretes varying from unit to unit is why I would use a chip like the SN74CBTD3384CPW. But the discrete design presented will barely drive either side to more than 2V with any certainty according to the BSS138 data sheet. Drive it from the 5 volt rail through a diode and you won't see more than 3.5 volts on the 3.3 volt side. The diode needs some current so a 1k resistor to ground. This bias point can be shared among all the signals.I've seen circuits that use FET array chips where one is used to set the operating point of the others, works a charm if you want to go to that much trouble.The real issue with level converters is there are so many to choose from. The logic market used to be 74LS or if you really needed speed, 74S or if you wanted low power, 4000 series. Then they started with the F, HC stuff, AC, AHC, LVC,... and all the xxT variants. I literally can't keep track and there's no score card! The level shifters are the same way with a bazillion different families all just a tweak different. This is why I have no hair.

author: Ian.M
author_rank: Super Contributor
timestamp: March 25, 2021, 11:44:34 pm
content: Yes, but I'm not the one that wants to use bidirectional single MOSFET level shifters for fast unidirectional push-pull signals. The discrete design I presented is well suited to slower open drain I2C signaling, though I do admit the value of the R3 pullup on the 5V side is rather suspect if its the *ONLY* pullup on the 5V side of the bus.

author: gnuarm
author_rank: Super Contributor
timestamp: March 26, 2021, 03:48:44 am
content: I've used switch isolation for 5 to 3.3 level shifting primarily because it requires nothing special for either direction. No need to turn direction around, no need to even bother with the concept of direction. It just connects the two voltage levels correctly minimizing the waste of left over buffers in one direction.The only other devices that do this use drivers in each direction through a resistance which can be over driven by the device on that side on bidir buses. To deal with the slow risetime that would result they detect the leading edge on one side and drive the other bus hard for a short time, enough to raise a hi-z signal, then turning off letting the resistor driver hold the bus state. This also acts as a state keeper for tristate buses since the two sides are coupled.Hmmm... I wonder if they have these in singles. They could be useful as latches in some applications.

author: kalj
author_rank: Contributor
timestamp: March 26, 2021, 07:02:12 am
content: Finished up adding the level converters to the board design. I figured I might as well go with the *125 chips and get proper tristating of the MISO line (as people have suggested!). Also, I believe this should work for VCC = 5V (i.e. 5V -> 5V conversion), so it is quite flexible in case I want to connect to a 5V MCU.Feedback and suggestions are welcome!

author: gnuarm
author_rank: Super Contributor
timestamp: March 26, 2021, 07:39:54 am
content: I've missed something here. How can a 3.3 volt LVC chip drive a 5 volt CMOS input without pullups or something??? The LVC part can only drive to 3.3 volts which does not meet the spec for the MCP chip inputs.If you are going to use that, why bother with an interface chip at all? The signals driving the LVC chip already reach 3.3 volts. So this chip accomplishes nothing that I can see. What am I missing?On top of that, why do you tristate the SCK_HI and SI_HI signals using the CS? Shouldn't they be driven all the time? Is something else driving the MCP chip? If so, doesn't that also need to drive the CS signal to the chip?

author: Ian.M
author_rank: Super Contributor
timestamp: March 26, 2021, 09:58:33 am
content: I don't know what intoxicant our O.P's on, but if its legal save some for us - we need it to cope with this thread!Answer: You aren't missing anything - It cant, nor can it run (reliably) at 5V Vcc.*ONLY* MISO should have a 5V tolerant input, 3.3V supply tristatable buffer (e.g 74LVC1G125). The others require upwards translation to 5V and to be continuously driven, so as I recommended earlier the easiest option for the three master output signals is a 5V Vcc 74HCT32 quad two input OR gate. Why OR gates? Simple non-inverting HCT buffers are not so common. The quad OR is dirt cheap, and eases layout vs the alternative of a quad AND as the spare inputs can tie to the ground plane.

author: kalj
author_rank: Contributor
timestamp: March 26, 2021, 11:32:39 am
content: Ah, damn it. I don't know how I missed that these LVC chips are all 3.3V max. But yeah, the 74HCT125 is the one that I should have used. What is the advantage of using the OR gate instead of the tristate buffer? It seems equally suitable - both have an unused feature I guess.Regarding tristating the SCK and SI, I guess I thought their values don't matter when the device is not selected, but I guess any valid driven value makes more sense than tristating. Simply tying all enable lines to Gnd should solve make it work I guess?@ Ian.M If you can't cope with people that are still learning you can read other threads.

author: Ian.M
author_rank: Super Contributor
timestamp: March 26, 2021, 11:53:55 am
content: Yes you can use 74HCT125 with all its enables tied low for the upwards translation. Whether you use the '125 or the '32 depends on what you can get the most easily, what you've already got in your parts bin, and of course cost. I just checked Digikey, and the '125 is a whopping 1.2 cents cheaper each in x10 qty, so lets go with that.A trap for the unwary is that 74LVC isn't *always* 3.6V max (operating). e.g. 74LVC1T45, '2T45 and '8T245 are rated for operation at up to 5.5V VccA and VccB.@kalj,Sorry, I should have used a smiley to indicate my intoxicants comment was intended as humor. However if you feel I'm taking a dig at you for failing to read the datasheet's limiting ratings, you might not be entirely mistaken.

author: kalj
author_rank: Contributor
timestamp: March 26, 2021, 12:13:21 pm
content: @Ian.M: No worries, in retrospect I realize it must have looked kind of silly missing something that fundamental.But I am happy I learned something new.Then I will go with any of '125 or '32.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 26, 2021, 04:24:39 pm
content: Uh..? Thehttps://www.ti.com/lit/ds/symlink/sn74lvc1g125.pdfliterally headlines 6.5V max in the limits section.I don't recommend using it at 5V, but it can be done. I'm not aware of any specific parts in the family that are specified for lower.Tim

author: Ian.M
author_rank: Super Contributor
timestamp: March 26, 2021, 06:41:15 pm
content: Back in the 2000's T.I for one certainly had a 3.6V upper limit foroperatingVcc, for much of their 74LVC range as can be seen fromhttps://www.ti.com/lit/pdf/scbd152I suspect the introduction of single/dual gate small package devices which are 5.5V Vcc capable in normal operation has grossly muddied the waters.Nexperia still claim 1.65 V to 3.6 V (standard) for their 74LVC range except 'PicoGate' which is 1.65 V to 5.5 V.https://www.nexperia.com/products/analog-logic-ics/family/LVC/Therefore my statement "A trap for the unwary is that 74LVC isn't *always* 3.6V max (operating)." still stands - if you need higher Vcc, check the specific datasheet!

author: T3sl4co1l
author_rank: Super Contributor
timestamp: March 26, 2021, 07:23:01 pm
content: Recommended max, yes -- but not absolute max. You're taking some risk running it at 5V, mainly that you have no headroom for transients, and maybe there's some degradation mechanism as well. I wouldn't use it lightly in this way -- but I wouldn't say "always". As "a trap for the unwary", I agree it's a good rule; newbies are very unlikely to encounter (let alone recognize) the situations where the above would apply.Good catch that it's varied over time, or between families -- I hadn't noticed that.Tim

author: gnuarm
author_rank: Super Contributor
timestamp: March 26, 2021, 07:35:10 pm
content: Quote from: kalj on March 26, 2021, 11:32:39 amYes, as a matter of fact, all CMOS inputs (and many TTL inputs for that matter) need to be tied high or low to avoid a floating input that can park at the transition point turning on both the pull up and pull down FETs drawing a large slug of current, possibly damaging.QuoteHis response may have been a bit much, but if you are going to ask for help in a public forum, you need to grow a bit more skin over your nerves.As to the Vcc issue, the data sheet says:VCC Supply voltage Operating 1.65 5.5 (volt min / max)So the LVC part can work just fine at 5V Vcc. The problem is the MISO signal will be driven to 5V. However, it is not needed. A resistor divider can drop the 5V output of the MCP device to a safe 3 volts and meet the input requirements on the MCU, no buffer needed... unless it needs to be tristated. Even then, use resistors that are light enough and the other devices driving this net easily over ride it.

author: gnuarm
author_rank: Super Contributor
timestamp: March 26, 2021, 07:51:28 pm
content: Quote from: Ian.M on March 26, 2021, 06:41:15 pmI find the plethora of logic families with little to distinguish them to be very confusing. If they will do the trick I typically reach for an HC/HCT part before anything else. In this case the HCT has low voltage compatible inputs and with a 5 volt supply spec will drive 5 volt devices. So great for 3.3V or even 2.5V CMOS to 5V anything. The output drive is not so hard, but it is enough to even drive TTL inputs.

author: jziegler
author_rank: Newbie
timestamp: March 26, 2021, 09:15:20 pm
content: Quote from: gnuarm on March 25, 2021, 11:03:23 pmHere's your score card, at least for TI families:https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf?ts=1616793015113&ref_url=https%253A%252F%252Fwww.ti.com%252Flogic-circuit%252Fsupport-training.htmlNot too easy to find on their website, but useful.There's also a separate guide for the "Little Logic" (single/double gate packages)I've used a bunch of SN74LVC2T45 chips where I need 3.3 to 5V level shifting. 2 bits per package, bi-directional with a single direction control. Not quite what OP needs here, but similar parts with different numbers of channels are available.

author: ejd.pol
author_rank: Contributor
timestamp: January 17, 2024, 06:10:19 pm
content: Just for completeness sake: TI also has a doc devoted to level translation:www.ti.com/lit/scyb018Cheers!