Failsafe P-FET gate drive? - Page 1
Forum section: electronics / projects

author: LogicalDave
author_rank: Regular Contributor
timestamp: May 14, 2021, 04:46:53 am
content: I'm designing a circuit that uses low Rdson P-FETs to switch 24V power at moderate current levels (5-25A). The FETs have 3-5mOhm Rds when Vgs is between -5V and -12V so thermal dissipation is minimal. Vgs max is -12V. Switching is infrequent (this is a relay replacement application not an SMPS) so I don't need a high current (fast) gate drive.I can easily achieve this with a resistor pulling the gate to the source voltage (24V) and a 15V zener diode from the gate to ground. This keeps Vgs at (15-24= -9V) and the FET saturated. This works well, but a problem arises if the power supply sags under load: because the zener voltage is constant, Vgs will drop linearly with the supply voltage and if it drops below -5V, the FET will fall out of saturation causing Rds to rise and the FET to overheat and fail.So the question: other than a brute force solution using several op-amps, has anyone seen or designed a clever, simple, failsafe, P-FET gate drive circuit (or reasonably priced integrated driver) that maintains good Vgs (e.g. -10V) even if the source voltage drops, and shuts off the gate drive if Vgs becomes too low to maintain saturation? Thanks!

author: AndersJ
author_rank: Frequent Contributor
timestamp: May 14, 2021, 06:36:06 am
content: Perhaps a voltage supervisor such as a MCP120 can be used to detect low Vgs and turn off gate drive.A zener would be needed to protect it from overvoltage.

author: Ian.M
author_rank: Super Contributor
timestamp: May 14, 2021, 06:56:50 am
content: If you drive the gate from a switched current sink, the drive voltage is set by the product of the current and the gate pullup resistor, provided the sink has enough headroom, so you can limit the maximum gate drive. The problem then reduces to disabling the current sink when there's insufficient headroom, for which, AndersJ's suggestion of a voltage supervisor will do nicely.However, assuming there's a regulated logic supply rail available, and the control signal is a rail-to-rail logic signal, a fully discrete solution is reasonably practical. See attached LTspice sim.N.B. you only need ONE lockout circuit for a number of switched current sinks and associated P-MOSFETs.

author: LogicalDave
author_rank: Regular Contributor
timestamp: May 15, 2021, 12:22:24 pm
content: WOW. Thank you soooo much Ian.M; I can see why you are named a Super Contributor; I think Dave needs a new category for folks like you (Super-Duper?)That was not just a concept, but a clever circuit and complete SPICE simulation; simply amazing!!!If I understand correctly, I'd only need to duplicate the PFET (M1,R6) and control current-sink (Q2,R7) to fail-safe drive additional loads (my circuit actually has 3 such loads).Many thanks Ian!

author: Ian.M
author_rank: Super Contributor
timestamp: May 15, 2021, 01:46:23 pm
content: Yes. However theMCP120voltage supervisor AndersJ suggested vastly simplifies the circuit and also removes the dependency on the logic supply voltage for UVLO (but not for the sink current that sets the drive). Replace R3-R5, Q1, Q3 with the MCP120, fed from the R1:R2 potential divider. Reduce R1,R2 for a greater divider current as the MCP120 needs up to 60uA supply current. You'll also need to pick a divider ratio and MCP120 trip-point variant to get your desired UVLO threshold while ensuring that MCP120 Vdd doesn't exceed 5.5V in normal operation and 7.0V abs. max.There are plenty of alternatives to the MCP120 - all you need is a comparator with integrated reference, that will either run from your logic supply (open drain or push-pull), or an open drain one that will run from your max. main supply or draw a low enough supply current that you can power it from a potential divider.If you stick with my BJT idea you'll need to do some worst case analysis to confirm that the UVLO trip point is acceptable and that R5 provides enough hysteresis over your full working temperature range and no matter how component tolerances stack up. hFEvariation from part to part and Q1 VBEvariation with temperature are likely to be the main issues.

author: LogicalDave
author_rank: Regular Contributor
timestamp: May 17, 2021, 03:12:10 am
content: The 3v3 logic supply already exists (the power switches are controlled by an STM32 uC) so the logic supply comes for free. Additionally, it's an indoor device so the operating temperature range is small (0-50C). These days I only use 1% resistors because there is virtually no cost difference. There is also a lot of error tolerance because the range of acceptable Vgs is -5 to -20v (nominally -10v).However, you're right that I need to do worst-case analysis considering stacked tolerances and transistor variations; I'll look at that below. WRT Anders comment (and thank you for that Anders!), a voltage supervisor and op-amp comparator was my original thought, but I'm quite space constrained for layout and was looking for a simpler and more elegant solution....and yours really seems to fit the bill Ian!First, let me make sure I understand your circuit properly. It's probably worth covering here since this post has received a lot of views already. My understanding is as follows; please correct any errors or expound on the function:* Regardless of Vcc, when Ctrl is off (0v), Q2 is off and R6 keeps Vgs=0V so no current flows through M1 to the load.* The BJT circuit serves two key purposes:1. Undervoltage lockout (UVLO) prevents turning on M1 if Vcc is too low.2. Keeps M1 Vgs at roughly -10V when Ctrl signal is On and Vcc > UVLO.* It does this by:* R1, R2 form a voltage divider for Vcc which is compared with a regulated 3V3 supply to implement the UVLO* The 3V3 rail and R4 keep Q1 Vbe reverse biased until Vcc >= ~11v94 (the UVLO threshold)* When Q1 Vbe forward biases, current flows through R3 and Q3 Vbe rises.* When Q3 Vbe exceeds ~600mV, current flows through Q3 causing Vc3 to drop to 0v.* This lowers the voltage at Q1 base (b1) due to the R4,R5 divider providing UVLO hysteresis* This also allows current to flow through Q2 and R7 when Q2 is turned on by the control signal.* Q2 is an emitter follower: when Ctrl is driven active (3v3), and Q3 is conducting (c3=0V),Q2 will allow current to flow through it and R7 until e2 equals the control voltage (3v3) less ~600mV = 2v7.Since R7 is 2k7, 1mA will flow through Q2. That current is sourced by Vcc through R6.Since R6 is 10K, 1mA of current flowing it results in a 10V drop so Vgs=-10V...elegant.As you noted, there are quite a few tolerances involved, but mainly manufacturing tolerances and temperature coefficients of the resistors and the transistors. I use 1% resistors with 50ppm or 100ppm temperature coefficients so they will have a +/-1.25% or +/-1.5% tolerance over the 0-50C operating range (plus the tolerance of the 3v3 LDO regulator). So:* Resistor divider R1, R2 determines UVLO with a 3% max error from a nominal 11v94 = 11v58 - 12v3* 2N3904 saturation voltage can be as high as 0v85, so the emitter follower might be as low as 3v3-0.85 = 2v45 instead of 2v7.* Resistor R7 determines the current through Q2 and has a worst-case 1.5% tolerance+temperature = 2.659K - 2740.5K* Resistor R6 determines Vgs based on the current through it and Q2 and also has a 1.5% tolerance = 9.85K - 10.15K* The emitter follower seeking 2v45 through 2740.5K = 0.894mA through 9.85K yields a minimum Vgs=-8v94* The emitter follower seeking 2v70 through 2659K = 1.015mA through 10.15K yields a maximum Vgs=-10v30There are other tolerances, but even stacked, they seem too small to matter given the acceptable Vgs range of -5 to -20v.I haven't looked closely at the hysteresis, but I need to examine that too.

author: Ian.M
author_rank: Super Contributor
timestamp: May 17, 2021, 04:16:00 am
content: You are well on your way towards grokking the circuit.2N3904 max. VBE(sat)of 0.85V is specced at 10mA ICand 1mA IB(forced beta of 10). The worst case VBEfor an emitter follower with 1mA IC, will be considerably smaller.Datasheetfig. 17 has a VBEvs ICcurve that will let you estimate it if you assume that max. VBE@ 1mA ICis the same distance above the VBEcurve as max. VBE(sat)@ 10mA ICis above the VBE(sat).There was nothing special about the choice of 2N3904 transistors. Any jellybean NPN with hFE>=100 and adequate VCEOshould be suitable. The chosen MOSFET is of course purely as an example.I thought you might be using a +/-12V max. VGSMOSFET. For a +/-20V one you can afford to drive the gate a little harder, You probably want >10V drive to guarantee it meets its RDS(on)specs. I'd go with R7 of 2K2 for approx 12V VGS.Schematic attached for convenience of discussion.

author: BradC
author_rank: Super Contributor
timestamp: May 17, 2021, 04:27:26 am
content: Quote from: LogicalDave on May 14, 2021, 04:46:53 amWhy not put a 9V zener between gate and source, then the resistor from gate to ground? This will keep Vgs at -9V until the supply drops ~> 10V.

author: Ian.M
author_rank: Super Contributor
timestamp: May 17, 2021, 04:49:05 am
content: Quote from: BradC on May 17, 2021, 04:27:26 amThat requires a rail-to-rail drive signal to the bottom end of the gate resistor, so at the very least a N-MOSFET and a pullup to the source. Its probably more robust if you are pushing the max. VGSlimit, but if you've got enough margin, and a stable logic supply, the switched BJT current sink saves a Zener, and uses a probably cheaper transistor (jellybean BJT vs MOSFET).Also, do you have any alternative ideas for the UVLO requirement?

author: BradC
author_rank: Super Contributor
timestamp: May 17, 2021, 05:34:29 am
content: Quote from: Ian.M on May 17, 2021, 04:49:05 amI can see the pullup, but I figured a simple NPN open collector would do the job at bottom of the gate resistor.Quote from: Ian.M on May 17, 2021, 04:49:05 amNot really. My interpretation of the first post was the voltage sag was due to load, and the existing drive example was pretty susceptible to this. The one I outlined would require the input voltage to sag 50% before it even got close to becoming an issue, so didn't really look at it much harder. Frankly if your load is such that the power supply collapses to half it's desired output I'd have though there are bigger issues to deal with.Anyway, I'm not here to argue or even suggest I have the solution. It just seemed that putting the zener G-S made more sense than G-Gnd.I've been using this configuration to buffer the trailer lamp socket on my car for the last 10 years. Needed to add the zeners after popping a regulator in the alternator and 19V frying the MOSFETs on the first implementation.

author: LogicalDave
author_rank: Regular Contributor
timestamp: May 17, 2021, 01:40:19 pm
content: @Ian.M, I had been considering a MOSFET with +/-12Vgsmax, but settled on one with +/-20V (Vishay SQD40031EL), so the tolerance range is quite large and I might indeed drive it harder (-12Vgs) and understand how to do so. I grabbed the 0.85 Vbesat spec from the first datasheet I looked at (https://media.digikey.com/pdf/Data%20Sheets/NXP%20PDFs/2N3904.pdf) which did not include a curve; I realized it was worse at Ice=10mA than it would be at 1mA, but it was also spec'd at 25C (not over temperature) and since I was looking for worst-case, I figured it would be better to use a higher number. Your solution appears to have loads of margin for my application; there was just enough space in the existing design for it so I've already added it to the layout and will spin a board later this week to test it (and will report results back here). Again, thank you so much!@BradC thanks to you as well; a zener across GS is indeed better than in series with the gate. As Ian mentioned, it doesn't solve my UVLO problem but it does keep Vgs at a suitable voltage until Vcc drops too low. The reason UVLO is important is that I have little control over the load in this application. I had specified a 20A max load, but discovered that customers don't respect specifications and were placing loads on it that would briefly far exceed 20A. The few seconds of voltage drop (and resulting drop in Vgs/increase in Rds) was sufficient to destroy the MOSFETs. Because I can't control the customer, I can't control how much the supply voltage will drop without a UVLO capability...hence this re-design. However, in the future, if UVLO is not required, I will certainly use a zener across G-S rather than in series with the gate...lesson learned!

author: Ian.M
author_rank: Super Contributor
timestamp: May 17, 2021, 01:57:32 pm
content: That complicates things. The UVLO circuit I proposed will oscillate if the load is dragging down the supply voltage to below its threshold. Depending on the resulting oscillation frequency, the MOSFET may well spend too long in its linear region, dissipate excessive power and be destroyed.You should probably consider switching to using a latching voltage supervisor IC so that the pulse repitition rate can be brought under MCU control to better manage MOSFET dissipation and reduce stress on your PSU.It may be preferable to add current sensing to enable the protection circuit to trip more quickly, before the supply drops significantly, to reduce the energy dissipated as heat in the MOSFET, and to transfer UVLO detection and management to the MCU, as with current sensing protecting the PSU and MOSFET from overloads, its only really needed during system powerup and powerdown, or supply brownout.

author: LogicalDave
author_rank: Regular Contributor
timestamp: May 18, 2021, 12:41:17 am
content: In my application, supply voltage seems like a reasonable proxy for supply over-current (i.e. I don't think monitoring current directly would buy any advantage). The only condition of interest is over-current sufficient to cause the supply voltage to drop so low that the FETs fall out of saturation and self destruct. If the supply current-limits but the voltage stays above the threshold for FET damage, it's fine. The uC already monitors the supply voltage and can use the Ctrl line to turn off the FET if Vcc gets too low which would (in software) serve the same purpose as a voltage supervisor with delayed reset (essentially implementing the "hiccup" mode used in many SMPS to handle over-current conditions).You're certainly correct that a fast oscillation would likely destroy the FETs, especially given the slow turn-on caused by weak gate drive (10K pull-up). I need to make sure I can detect the low voltage or UVLO condition in software and then implement a timed UVLO latch...I might be able to make use of the fact that Q3 collector is actually a logic-level UVLO indicator). Otherwise, a hardware solution like a voltage supervisor might indeed be required. I'll give it some thought; thank you again!

author: Terry Bites
author_rank: Super Contributor
timestamp: May 18, 2021, 02:02:40 pm
content: The single fault condition is the FET failing short and becomming completely unrespovive to the gate grive.So you need down stream sensing. Compare the gate drive and test if it is generating the expected output current or voltage.Use this to trip a load disconnect device like a latching relay. A power supply supervisor ic will help you out here.

author: LogicalDave
author_rank: Regular Contributor
timestamp: May 19, 2021, 04:34:37 am
content: Thanks @Terry Bites. Yes, the failure mode is caused by overload/over-current -> PS Vcc droops -> insufficient Vgs -> excessive Rds -> excessive Pd -> FET fails. As you note, the FET failure mode is short circuit between source and drain (the FET can't be turned off). Presently, I detect (and mostly mitigate) such failures using an additional closed-loop communication path that already exists for other reasons between the main control processor that drives the FET switches and slave processors downstream of the switches. The main processor signals the switch states and the downstream processors report switched voltage. If a mismatch occurs, the downstream processors take corrective action (act as though the switches were open which mitigates the failure) and the main processor alarms the fault. If the communication path is interrupted, the system alarms as well...so single faults do not cause systemic failure; at least not those single faults :-)It would be lovely if I had the PCB real-estate and component budget to add a dedicated supervisor and 20-30A relay to each FET for hardware fail-safe, but for now, I must use the software methods described above. This thread has focused on how to prevent the FET failures and has been very helpful! However your point about the importance of detecting and mitigating such failures is certainly a good one too; thanks!

author: boB
author_rank: Frequent Contributor
timestamp: May 19, 2021, 05:24:31 am
content: UVLO plus Desaturation protection would be my failsafe wish for this...You could make one of those too but looks like you've got your answers here.boB

author: Zero999
author_rank: Super Contributor
timestamp: May 19, 2021, 10:04:54 am
content: How about the TL431? That will give an accurate threshold, insensitive to temperature fluctuation.Presumably the logic signal is stable? If not, another circuit will need to be added to ensure it triggers at a precise threshold.

author: LogicalDave
author_rank: Regular Contributor
timestamp: May 19, 2021, 02:01:43 pm
content: Hi @Zero999, thanks; that works too and is also clever!For anyone following this thread, in this circuit, R1,R2 set the UVLO cut-off voltage; for my scenario, the value of R1 should be lower (e.g. 15K) to allow operation with Vcc down to ~10V. R4 sets Vgs and (again for my scenario), should be higher (e.g. 5k6) for higher gate drive (e.g. Vgs=-12v down to -7v7 at UVLO). The use of a precision reference adds a little bit of cost but, as Zero999 notes, improves tolerances (not important in my scenario, but good generally). The TL431 is a nice reference that operates to 36V and costs about $0.08 to $0.11 in qty 1K.

author: AndersJ
author_rank: Frequent Contributor
timestamp: May 19, 2021, 03:10:04 pm
content: You may need some hysteresis, or a latch,depending on how you want to handle possible oscillation at cut-off.

author: Zero999
author_rank: Super Contributor
timestamp: May 19, 2021, 04:01:28 pm
content: Quote from: AndersJ on May 19, 2021, 03:10:04 pmThe circuit I posted has hysteresis. R3 provides positive feedback. When U1 & Q2 are off, R3 is in parallel with R2, pulling U2's input closer to 0V, which lowers the threshold. When Q2 is on, R3 is connected to the control voltage, thus increasing the threshold. R8 ensures Q1 doesn't start to turn on when the control voltage is low, by shunting the tiny current through R1 and R3.If anyone is interested, please download the .asc file attached and LTSpice, if you don't already have it: it's free. The TL431 model and symbol aren't included in he default LTSpice install, so download the ZIP, if you don't already have them. You can extract them to the same directory as the .asc file, or put TL431.mod in LTSpice directory\lib and TL431.sym in LTSpice directory\sym.

author: AndersJ
author_rank: Frequent Contributor
timestamp: May 19, 2021, 05:28:30 pm
content: Beautiful solution!

author: LogicalDave
author_rank: Regular Contributor
timestamp: May 20, 2021, 01:47:06 pm
content: Several elegant solutions have been posted that keep Vgson optimal as supply voltage droops; two solutions include UVLO with voltage hysteresis. The remaining issue is UVLO delayed reset. The scenario I am trying to protect against is a temporary overload (over-current) condition. The UVLO circuits presented will disconnect the load, but then the supply voltage will rise quickly and potentially cause the circuit to oscillate which might still destroy the FET (particularly with a slow gate drive). SMPS protect against this by implementing a "hiccup" mode where UVLO reset is delayed. I could do this using a voltage supervisor with internal delayed reset such as APX810S or possibly use software to achieve this if the oscillation is slow, but are there better approaches? A judiciously placed R-C?

author: Zero999
author_rank: Super Contributor
timestamp: May 20, 2021, 09:57:54 pm
content: Of course it's possible, but why not increase the hysteresis? It also sounds like the power supply is under-rated, has too thinner cable, or poor decoupling. The voltage shouldn't be sagging so much under load.

author: LogicalDave
author_rank: Regular Contributor
timestamp: May 21, 2021, 12:07:54 am
content: Thanks @Zero999!The system powers 1-4 motor controllers. The supply can source more than 20A and in normal operation, each motor draws roughly 1A...so plenty of power. The problem occurs when multiple motors stall simultaneously. Although the motor controllers will reduce power to the stalled motors within a few seconds, each stalled motor can draw more than 13A! This massive overload causes the supply voltage to drop precipitously (for a few seconds) and that drop causes the MOSFET switches to fail. I can't size the supply to handle 50+A of stall current because it would be too expensive.The solutions shown in this thread may help since they will:keep the FETs in saturation as Vgs dropsturn off the FETs if adequate Vgs can't be maintainedkeep the FETs off for some time (hiccup mode) after Vgs recovers to avoid oscillation.My last challenge is to determine whether the FETs I'm using can handle the short-term overload even while fully saturated.The sharp increase in I will still cause a great deal of Pd; even with 4-mOhm Rdson: 50A * 50A * 0.004R = 10W!Thanks again to everyone in this thread for their ideas and feedback; eevbloggers are amazing!