Solid state current limit for my active load... maybe a simple question - Page 1
Forum section: electronics / projects

author: Davidwasalreadytaken
author_rank: Contributor
timestamp: January 29, 2025, 10:27:21 pm
content: I have made my high powered active load and enjoyed it for ages testing power supplies...and then I blew the mosfets. And again. And again. They are individually fused, which prevents things melting, but the fuses are not preventing fets from going "click" and dying the death...then all the neighbors are overloaded suddenly and they go to the restroom together like a bunch of girls, and never come back, like my ex. This is now officially old and I am tired of blowing FETs.The goal for this thread is to design a hopefully-very-simple circuit I can apply to each input section on my load, to prevent any one from going over-current. My bright idea is the bits with red lines: give an opamp a small reference voltage that corresponds to some set current through/voltage across the 0.05R resistor. Then the opamp is a comparator and turns on the input FET until the current is reached, when the input FET has its gate signal shut off instead of going kablooey.Am I on the right track here? I take it for granted I have something wrong-way round and even basic circuitry 101 kind of advice would be helpful, as this is the first time I ever tried to implement an idea I thunk up in my own thinker. Links to implementations of similar things would be welcome.The original threadhttps://www.eevblog.com/forum/projects/please-let-me-know-if-my-very-high-power-load-has-a-fatal-flaw/

author: PCB.Wiz
author_rank: Super Contributor
timestamp: January 29, 2025, 11:23:56 pm
content: Quote from: Davidwasalreadytaken on January 29, 2025, 10:27:21 pmYou already have an opamp that senses current and drives the gate, so unless the requesting level goes wildly wrong, you are not protecting much.You can add a simple input scaler so that it cannot grossly exceed the current ceiling.If you have many FETs failing, that may need spike protection on the drains and gates.Keep track of exactly when the FETs fail? Is it during current ramp, after time, or during a hotplug ?

author: mtwieg
author_rank: Frequent Contributor
timestamp: January 30, 2025, 12:54:11 am
content: Agree with PCB.Wiz above. Your circuit already has current regulators. Adding an additional current regulator/limit probably won't help. If the existing ones aren't working well enough, should fix them.Can you describe the conditions under which the FETs are dying, and the part numbers of the FETs?

author: moffy
author_rank: Super Contributor
timestamp: January 30, 2025, 01:32:41 am
content: It would be better to use the extra FET to clamp the gate to ground, if the extra protection is needed. Noise across the shunt will be an issue, and you would probably want the fault to latch and turn the FET off permanently until a reset.

author: JohanH
author_rank: Frequent Contributor
timestamp: January 30, 2025, 07:34:51 am
content: Maybe there are issues with thermal imbalance. PaulV did some attempts with thermal balancing, see his blog athttps://www.paulvdiyblogs.net/2015/08/dynamic-dc-power-load.html(the 4.1 revision schematic).

author: Davidwasalreadytaken
author_rank: Contributor
timestamp: January 30, 2025, 05:19:15 pm
content: PCB.Wiz, it's a good point. I forgot to look at what I have, and started thinking of a way to fix it!The input currently has a resistor dropping most of the voltage, then smaller potentiometers to provide the setting voltage for the op-amps driving the gates of my FETs. Were you thinking of something other than that, for a scaler? I revisited the maths, and it is possible to provide more current than I wanted, so I'll have to increase that resistor to decrease the amount of current I can command per FET. In retrospect, this could have been half of my problem! (the other half being over-powering the FETs)For spike protection, do you mean like MOV across the FET?I don't have any instrumentation on this, just a voltage and current meter for the whole thing, there's no data collection at all. It would be interesting to have a few dozen sensors and voltage/current monitors but ...mtwieg, the problem seems to be the monkey turning the knob. I need to idiot (me) proof this system and I think that means more FETs with less current through each.moffy can you please explain what you mean about "noise across the shunt"? I like the idea of clamping the gates to ground in the event of a fault. That seems cleverer than just opening the gate! Now that I think of it, just opening the line form an already-charged gate would be kinda pointless.JohanH I think giving everybody his own opamp for gate drive should keep the currents close, which will hopefully keep temperatures close. The rebuilt version of this will have much better access to the FETs so I will be able to see if there is a problem with thermal imbalance. I hope I won't have to go as far as active temperature controls.I think I have arrived at a point that I am so frustrated trying to troubleshoot this in its current condition, I'm going to rebuild it. Thanks all for your suggestions, and I'll probably be back after a while with a revised schematic.

author: Ian.M
author_rank: Super Contributor
timestamp: January 30, 2025, 06:01:11 pm
content: The biggest problem with simple OPAMP + MOSFET current sinks is when there isn't enough voltage at the MOSFET drain to maintain the target current through the sense resistor in series with the MOSFET source. This results in the OPAMP railing, driving the MOSFET gate high, so its hard ON. Suddenly apply voltage to the drain, the MOSFET will pass far far too much current and die before the OPAMP can get its output off the positive rail, slew the MOSFET gate voltage down to its Miller plateau linear region and control the current. If you ramp up the drain voltage slowly from 0 to 1V or there abouts, each individual current sink's feedback loop has time to stabilise, and everything then works OK. As all the sinks are in parallel, whichever OPAMP + MOSFET is slowest to recover from being railed is the one most likely to pop, and that depends on part to part differences in the characteristics of the OPAMP and MOSFET gate charge.What you need to do to fix this is make sure the OPAMP outputs hit the negative rail when there is insufficient voltage across the load, so they ramp up the current from zero when load voltage is suddenly applied. If you've got a negative supply, a fast comparator sensing the drain voltage and pulling the control voltage negative if the drain voltage is too low will do the job.If there is no negative supply for the OPAMPs, you cant simply force the control voltage negative. Zero control voltage is not good enough - some of the OPAMPs input offset will cause them to rail positive with both inputs at zero. Either add a negative supply (which could be as simple as a silicon diode in series with the control PSU 0V to get a voltage one diode drop below ground) or use a comparator with a push-pull output feeding a potential divider to individual diodes to pull all the OPAMP +In pins up enough to exceed the max. possible control voltage at the -In pins.

author: Davidwasalreadytaken
author_rank: Contributor
timestamp: January 30, 2025, 06:08:42 pm
content: Ian.M that explanation made a lot of sense, re: which FET pops first.I am thinking about this at the moment, and reading other threads. MarkF suggested to take a resistor from a +v supply to the 'top' of a sense resistor, so the sense resistor always has some minimal current flowing, so the opamps are not trying to jam the FETS hard on all the time with no input. What do you think of that idea?https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg2486418/#msg2486418

author: Martinn
author_rank: Frequent Contributor
timestamp: January 30, 2025, 06:49:37 pm
content: What FETs are you using exactly?Do they have a DC SOA?Are they genuine or fake?

author: Davidwasalreadytaken
author_rank: Contributor
timestamp: January 30, 2025, 07:06:10 pm
content: For this round I am looking at IXFK55N50 and IXFK73N30, sourced from scrapped equipment and likely genuine. The datasheets for these are lacking, among other things, SOA charts! They are extremly unlikely to be rated for DC or designed for linear opration. I am thinking of using them for 5A maximum, each, and keeping them under 100W each, so I think they will be alright.https://www.kynix.com/pdfview?pdffile=r%2Fdatasheets%2Fixys-ixfk73n30-datasheets-0777.pdf&partinfo=ixfn73n30-ixys-10050428https://www.alldatasheet.com/datasheet-pdf/pdf/114953/IXYS/IXFN55N50.html

author: Slh
author_rank: Regular Contributor
timestamp: January 30, 2025, 08:40:13 pm
content: No SOA graphs but figure 6 admittance is very interesting. There's usually a much bigger difference between 125C and 25C. I can see why they were doing well in the linear region.I'd keep it below 50W. I think you'll struggle to get 100W out of them reliably.

author: moffy
author_rank: Super Contributor
timestamp: January 30, 2025, 09:30:12 pm
content: Quote from: Davidwasalreadytaken on January 30, 2025, 05:19:15 pmI was really thinking about switching noise of switching FETS, but this is a linear application so less likely. However if there is any HF noise in the load, capacitances around the FET will make it appear across the shunt.