EEVblog #1228 - Do Digital Scopes Have REAL Verniers? - Page 1
Forum section: electronics / general

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 03:17:30 am
content: Do digital oscilloscopes have REAL vertical vernier controls?Let's probe a scope up the clacker to find out!

author: BravoV
author_rank: Super Contributor
timestamp: July 10, 2019, 03:27:01 am
content: Imo, this video shows a huge advantages having a 4 inputs scope, compared to 2 when probing digital lines like the example at the Siglent scope's front end VGA.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 05:50:38 am
content: Dave,when you do this kind of investigation and then claim some things like example difference between 500uV and 1mV/div. (position around 12:00/18:55 in video) Now you claim it is not true 500uV/div just because you do not see control data change in ONE place. Are you seriously making this claim based only to this ONE single fact without anything else. Is it now better to take spoon in to hand and start first thinking and and after thinking and study is ready, then talk and publish claims and conclusions based to all facts.Look what happen AND where happen when you change example from 500uV/div to 510uV/div and so on, every fine step to 1mV/div. Also investigate real ADC data. If 500uV is just digital magnification like example 1mV/div in Keysight derived from (I do not remember if from 2mV/div or something like it) lover sensitivity you can also see it in data, you can see it even on the screen if you know how to look it with some signal+noise. If I remember right some model do 1mV/div as digital "image" magnification from 4mV/div. Whole full scale is now 6 bit data (64 steps). Have you seen this kind of digital magnification in Siglent (this model). Yes there is this method in older SDS2000(X) But how about SDS1000X-E. ( it is very different). If we use word digital magnification... well, I think it need go bit more deep to think what are these.Why do you make such simple and hasty conclusions and arguments? Before submitting the conclusions, the matter should really be examined more closely. If your claim is right or wrong it is not now case. But now your claim is not based to nearly anything. (exept that VGA control byte do not change between 500uV and 1mV/div. Are you seriusly as real engineer need be with this claim. Now you have no ground under your feet here. First you need investigate, collect data and many kind of evidences. After then come out again and tell with data that there is no real full ADC scale 500uV/div (or 530uV/div or what ever).If go just roughly: 13*50 fine steps = 650 steps. (but yes, part of thing is also 3 different relay selected V bands. Example in Voltage band I, 500uV/div - 118mV/div, there is 358 steps if I count right. Band II and III naturally have less steps due to more narrow Voltage ranges)5 points tip:VGA gain control range max is 8 bit. Think!!! Think again!example from 500uV/div to 1mV/div there is 50 step. From 1mV/div to 2mV/div again 50 steps.from 2mV/div to 5mV/div again 50 steps and so on.... ( I have also told it already in this other thread)Now think again. Whole range from 500uV/div up to 10V/div and how many steps there is total (do not care if 1-2-5 major steps or fine steps. Just count total. Think again this 8bit cotrol byte. No any bell ringing your head?Then think one other data sheet where are these:Quote from: data sheet xAnd, using this together with... and so on.Media business and Engineer work are some times different or is it better say, it need be differerent.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 06:39:25 am
content: Quote from: rf-loop on July 10, 2019, 05:50:38 amThe ADC is 8 bit.The chip gain does not change from 500uV to 1mV.How on earth do you expect it not to have have digital gain at 500uV?A true 500uV/DIV front end amplifier would amplify the signal to the full scale ADC input. When the gain instruction to the chipclearlyshows there is no change in amplifier gain, it's by definition not a true 500uV analog range.But you are correct that the Siglent does not just "pixel double", it's doing some form of digital gain.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 06:47:50 am
content: Quote from: EEVblog on July 10, 2019, 06:39:25 amADC chipOUTPUTis 8bit. Yes. It is other thing.PLease, kindly, do your home works and some real investigation before start bullshit generator.Make tests and look raw ADC data. Do you find 128 steps or 256 steps (7 or 8 bit data) when you look example 500uV/div raw data.In Siglent SDS1000X-E It is NOT at all like example Keysight digital "image" magnification from ADC output data when they magnify from 4mV/div first to 2mV/div and even then to 1mV/div what have only 64 level steps (6bit).

author: tautech
author_rank: Super Contributor
timestamp: July 10, 2019, 06:48:08 am
content: Quote from: EEVblog on July 10, 2019, 06:39:25 amFFS Dave think !Can you vernier lower than 500uV/div ?NOOnly below 1mV/div !

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 06:52:03 am
content: WTF is your problem guys.The ANALOG GAIN IS THE SAME for both 1mV and 500uV ranges, do you deny this?Unless there another x2 amp somewhere else in the analog chain that's being switched in then the 500uV must be doing digital gain somewhere else in the system, surely?In fact the analog gain is the same for the 2mV, 1mV and 500uV ranges.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 06:56:56 am
content: Quote from: rf-loop on July 10, 2019, 06:47:50 amI'm not saying it is.I'm just saying the the FRONT END ANALOG GAIN is the SAME for the 2mV, 1mV, and 500uV ranges.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 06:59:38 am
content: Quote from: EEVblog on July 10, 2019, 06:52:03 amYes, but also then no. Please do you home works.VGA is before ADC yes and it is only place where is doing analog gain adjustment.But after then you forget some important thing. ADC have 8 bit output. Yes it is.But with Analog HMCAD1511 we can do things different. We do not need magnify (reduce resolution) after its output.Think now carefully. How example Keysight do magnification from 2mV/div to 1mV/div. It magnify this ADC output. Siglent do not. After magnification, ADC output is still 8 bit and it use still this full resolution. You need only take out 500uV/div raw data out and look. I ask, is it 7bit or 8 bit data. Please, read HMCAD1511 data sheet and pleease read it as long so that you also understand what you read there.In previous I have emphasised this important thing... due to higher than 8 bit resolution internally.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:00:11 am
content: It uses the HAD1511 ADChttps://www.analog.com/media/en/technical-documentation/data-sheets/hmcad1511.pdfIt has internal digital gain after the ADC, it must be using that.If you have evidence that the gain changes IN THE ANALOG FRONT END then present your evidence.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:01:28 am
content: Quote from: rf-loop on July 10, 2019, 06:59:38 amI am not going to go and analyse the ADC output data to satisfy your little bug-bear. You go do it if it's so important to you.My investigation and comments stop at the analog front end.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 07:03:15 am
content: Quote from: EEVblog on July 10, 2019, 07:01:28 am500uV/div is still full 8 bit ADC resolution because magnification is done there using it internal higher resolution. Period.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:03:42 am
content: If you really have a problem with this then I can include a screen shot of the HAD1511 datasheet and a comment that the digital gain is being done in there. Will that shut you up?

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:06:32 am
content: Quote from: rf-loop on July 10, 2019, 07:03:15 amThe ADC has a voltage reference. That voltage reference and the analog gain will be scaled for 1mV( or maybe 2mV?)/dev, so let's say 16mV total signal input.On the 500uV range the analog gain is the SAME a the other ranges, so there is now only a 4mV FS signal on the ADC input that has a 16mV reference.Look at the datasheet, the gain is done "digitally" after the ADC.I don't care about the performance, the fact is the gain is done digitally after the ADC output wiht the same voltage reference as the higher ranges.

author: JxR
author_rank: Unknown
timestamp: July 10, 2019, 07:09:35 am
content: I have no desire to get in the middle of this current discussion, but I watched and enjoyed the video after I got the email notification. Just wanted to point out that you still have the video as unlisted on YouTube, in case you meant to update that.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:10:07 am
content: Quote from: JxR on July 10, 2019, 07:09:35 amFull release is tomorrow.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 07:13:15 am
content: Quote from: EEVblog on July 10, 2019, 07:03:42 amYes, exactly. It is there. And now we need bit think when we talk digital magnification. When we talk just "digital magnification" because inside group "digital magnification" can be very different things. . And just because this ADC have more internal resolution than just 8bit what is its final output resolution (some reason I believe Analog Devices claims about 1511 ADC).It is very different if we just magnify 8bit ADC raw output data (like example some Keysight models do) or magnify internally using ADC extra internal resolution and then still get out and use full 8bit output. Result is different. (oh yes, noise figure etc not so nice if compare to system where is very good low noise analog front end with amplifier before ADC and then get 5mV full scale 0-255. but still this system what Siglent use can claim it is full 8bitresolution500uV/div.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:15:33 am
content: New version rendering now to shut everyone up. Well, shut up the rabid Siglent fanboys

author: tautech
author_rank: Super Contributor
timestamp: July 10, 2019, 07:17:29 am
content: Quote from: EEVblog on July 10, 2019, 07:06:32 amYet you said "software" magnified in the video @ ~12.10

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:19:02 am
content: Quote from: tautech on July 10, 2019, 07:17:29 amOh FFS, are you going to nit pick every word in my videos?I'm not going to go back and dub over that.I have included an overlay correction, and if you don't like it, tough titties.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 07:22:59 am
content: Journalists and Engineers...

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:23:33 am
content: Quote from: rf-loop on July 10, 2019, 07:22:59 amWhat are you insinuating?If you aren't careful I'll leave the video as-is and not correct it, just to piss someone off...

author: Barny
author_rank: Frequent Contributor
timestamp: July 10, 2019, 07:31:24 am
content: A educational video on the main channel below 45 minutes?Who are you and what have you done to Dave Jones our Mr. EEVblog the waffle master?(Mhmmmm waffles)Are you a repiloid from the big anti free energy organisation?Funn asside:Thanks for the educational video.Now I know another thing I miss on my old, big Rigol scope.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:40:28 am
content: Quote from: Barny on July 10, 2019, 07:31:24 amI was disappointed by the 19min length, I thought it'd be about 12-13min.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:42:52 am
content: Video uploaded, processing now.

author: Circlotron
author_rank: Super Contributor
timestamp: July 10, 2019, 07:51:46 am
content: When you use the vernier volts/div I'd like if there was the option instead of all these fractional volts/div figures, you could shrink the waveform back inside the bounds of the screen and also shrink the spacing between the vertical amplitude lines (horizontally drawn lines). That way the volts/div figure could remain constant but the size of the divisions would change instead.

author: Rerouter
author_rank: Super Contributor
timestamp: July 10, 2019, 07:53:24 am
content: At least for the siglent, I can provide some evidence to the fact they are using the VGA for all vernier steps down to 500uV (cant see video because youtube is processing), (technically the front end can measure to about 313uV / div if you manually set it)for a given channel you can use the CX:VGAC? command to read the current setting of the VGA, equally you can manaually set it with CX:VGAC = 255So to read the VGA for channel 1, you would send C1:VGAC?If you have the 4 channel model you can do this through the Web UI.Attached is the calibration file of gain and offset it runs for "Most" VGA steps for each attenuator range, I would recommend opening it in notepad++ so it can present it in a nice formatted way.To best explain it, you have the channel, the attenuation range, and then the VGA code, next up is the channel offset DAC code it needed to use to make the ADC read 0 during calibration, the other 2 codes I am less sure on at this time,

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 07:57:55 am
content: Quote from: Rerouter on July 10, 2019, 07:53:24 amNot on the scope you can't it stops at 500uV/div in vernier mode.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 08:01:17 am
content: Here is small help to uderstand this case.There is VGA before ADC. But its gain steps resolution is not enough. (only one 8bit control byte)Programmer can even select what is best combination how to use ADC digital cain combined with VGA gain. (optimize for noise etc... )For get full control over whole voltage range including "vernier" aka fine steps in this case.Most wide voltage band is band I from 500uV to 118mV/div. It include over 350pcs V/div steps. Where some steps are these major steps 500uV, 1mV, 2, 5,...etc up to 100mV/div and fine steps between these and then still some fine steps from 100mV/div to 118mV/div. After then, (120mV/div) it change to voltage band II.ADC output is 8 bit. Simple solution is magnify this digitally. Just drop resolution. Like example in some Keysight and also some others. Also Siglent do this kind of magnification in SDS2000 series from 2mV/div to 1mV/div.But in series SDS1000X-E there is Analog Devices HMCAD1511 ADC. Also this ADC output is 8bit.Secret is inside this ADC. Internally it is 13 bit. 5 bits more than output resolution 8 bit.Analog Devices tell that it can use even 32X magnification without missing codes. Just this 5^2=32.And Siglent use this, together co working with front end Variable Gain Amplifier for get full resolution including all major and fine steps starting from 500uV/div, then 510uV/div and so on... until 118V/div. Then change front circuit and go to 120mV/div to 1.18V/div with all fine and major steps and then change again front circuit and start from 1.2V/div to 10V/div with all fine and major steps.So we do not need digitally magnify ADC 8 bit output at all. We must not mess and mix this system with systems what use 8bit ADC output magnification method at all. It leads to missing codes, (reduced resolution)In Siglent vernier and major steps mode (they are not different except relay selected three Voltage bands) We can use VGA + ADC internal 13bit resolution for do all this without missing codes full 8bit ADC output.Note "digital gain", not "digital magnification" done for ADC output as some Siglent and other brands some models.

author: Rerouter
author_rank: Super Contributor
timestamp: July 10, 2019, 08:06:05 am
content: The command I detailed lets a user manually over-ride the VGA, if you max out the VGA with code 255, that is what I measured its equivilence to be, its noisy as all heck down at that level, but it does measure it (the scope in this situation does not correct its VDIV values, becuase you have essentially over-ridden the UI,With this method, you could set 1 channel to say 5mV, another to 500uV, and manually override the first channel to 500uV's VGA code to compare if they are doing any other trickery. as this bypasses the entire scope UI

author: The Soulman
author_rank: Super Contributor
timestamp: July 10, 2019, 08:11:32 am
content: The VGA makes 1 dB steps?That doesn't sound like fine adjustment to me.And also from the ADC datasheet:QuoteDo they use a combination of VGA and ADC analog domain adjustment for the vernier control?I also don't see how they would keep real 8 bit resolution at 500uV range if 1mV is also 8 bit,the datasheet doesn't mention adjusting the v-ref. (although the analog 10% adjustment may be doing just that).Could they run the ADC at a higher sample rates at lower analog level input (lower settling times) and oversample??(they=siglent)edit: rf loop beat me.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 08:13:56 am
content: Quote from: The Soulman on July 10, 2019, 08:11:32 amRead my previous msg.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 08:20:42 am
content: Quote from: The Soulman on July 10, 2019, 08:11:32 amDon't know, interesting question.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 08:23:51 am
content: Quote from: EEVblog on July 10, 2019, 08:20:42 amOf course.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 08:31:52 am
content: Quote from: rf-loop on July 10, 2019, 08:23:51 amAnd once again, what are you insinuating?

author: The Soulman
author_rank: Super Contributor
timestamp: July 10, 2019, 08:32:39 am
content: Quote from: rf-loop on July 10, 2019, 08:13:56 amYes, thanks.Could you post a link to the datasheet that shows that graph and mentions 13 bit?Silly little ADC that is, 13 bit resolution on a 8 bit output..Glad this isn't the metrology forum, also from datasheet:QuoteAnd linearity is actually not to bad for a 8 bit high speed ADC,but if you translate that to 12 or 13 bit, it is pretty horrible.Quote

author: The Soulman
author_rank: Super Contributor
timestamp: July 10, 2019, 08:40:23 am
content: Quote from: EEVblog on July 10, 2019, 08:31:52 amI can't speak for rf loop, but I think he is implying that 1 dB aren't really fine adjustment and so they must use a other way on top of that and only other way is the analog adjustment inside the ADC.

author: rf-loop
author_rank: Super Contributor
timestamp: July 10, 2019, 09:31:22 am
content: Quote from: The Soulman on July 10, 2019, 08:40:23 amNo. It is not analog adjustment inside ADC. It is digital adjustment. From internal 13 bit we scale out 8bit depending amount of digital gain. No missing codes up to 32x. If go over 32x then of course missing codes because there is not anymore enough resolution. It can also see in this ADC bloc diagram where it happen. After ADC. So agter signal is digitized. But ADC resolution is more than 8bit (of course 13 bit resolution is what it is... if look it with metrologist eyes... terrible.). But also it is not digital magnification if we talk about this kind of digital magnification what magnify displayed waveform on the screen like example what Keysight do. 4x magnification there mean that they take half of ADC data and magnify it so that it is now full screen so they can write 1mV/div (display scale) and resolution is 64 bits, or 2mV/div with 7 bit resolution.But there is 1511 ADC we can select and scale 13bits to 8bit (up to 32x magnification) (also there can use FS fine adjustment but I believe this is used only for cal) and output is 8 bit resolution (but with reduced some guality things) I do not "believe" that Siglent use this max 32x digital gain at all. But some amount what need together in VGA what give acceptable compromise. (result we can see also in BodePlot II and FFT what can not do what these can if there is just simple digital magnification after ADC 8 bit output)

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 11:18:05 am
content: Quote from: rf-loop on July 10, 2019, 09:31:22 amHow do you know it doesn't include the ADC reference DAC adjustment as well?

author: nctnico
author_rank: Super Contributor
timestamp: July 10, 2019, 11:49:26 am
content: I like to point out that a variable gain amplifier isn't the only way to do vernier control. Another way is to use a DAC to drive the ADC reference voltage. So even if an osciloscope doesn't have a VGA it may do vernier control in the analog domain.

author: EEVblog
author_rank: Unknown
timestamp: July 10, 2019, 01:10:43 pm
content: Quote from: nctnico on July 10, 2019, 11:49:26 amAll things considered though I think it's always the most desirable to do it in the front end amplification though.But chips like the HAD1511 are purpose designed to do some or all of it more cost effectively inside the ADC.

author: goaty
author_rank: Regular Contributor
timestamp: July 10, 2019, 02:38:53 pm
content: Very interresting Video.I read the HMCAD1520 datasheet (its from Hittite/AD) and it can do 8, 12 and even 14bits and mentions:"For the high speed interleaved modes, there will be no missing codes when using digital fine gain, due to higher resolution internally (1 bit)."So could this be a 1bit ADC ? Because it nowhere mentions internal '13bit' or alike. Only on some public announcement there is mentioned 13bits.Thank you

author: ogden
author_rank: Super Contributor
timestamp: July 10, 2019, 04:38:19 pm
content: Quote from: EEVblog on July 10, 2019, 01:10:43 pmUnless 40dB range of VGA is insufficient, "digital" gain of ADC does not help because it's gain granularity is6dB1dB compared to 1dB VGA steps. I think ADC reference adjustment is plausible. Isn't that (ADC VREF) good idea to check in follow-up video? After (more) careful reading of datasheet I did find out that ADC gain step is 1dB. Anyway it does not change my statement that ADC gain does not improve anything for vernier.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 10, 2019, 07:29:06 pm
content: The SNR vs "digital" gain curve does not look like just digital domain scaling. It looks more like scaling down the reference, maybe add analog gain before the actual ADC. So I would consider the 13 Bit number more like marketing talk combining 8 Bit real ADC and a gain of up to 32 (2^5) gain adjust, even though SNR drops at a "gain" of more than about 6. So the actual useful gain adds more like 2-3 bits and not 5 bit to the resolution at the fine end.This still may be enough to get the extra boost from 2 mV/div to 500 µV /div..

author: ogden
author_rank: Super Contributor
timestamp: July 10, 2019, 07:58:06 pm
content: Quote from: Kleinstein on July 10, 2019, 07:29:06 pmThey would not lie about internal 13-bit architecture. Accusing (ex)Hittite of something like that is EE blasphemy.

author: tautech
author_rank: Super Contributor
timestamp: July 10, 2019, 09:43:52 pm
content: Video link on YouTube:https://youtu.be/7v-P75MOZ5oWhere Dave adds this note:NOTE: The Rigol DS1054Z does have the ability to do vernier control. It uses the same HAD1511 ADC as the Siglent, and that ADC has two methods of vernier control. One is the digital gain after the ADC (available because the ADC is actually up to 13 bits internally). And second, the ADC reference voltage has an internal DAC that can be changed.So either or both of those techniques can be used, technically no need for a Variable Gain Amplifier on the front end.So why then is it used ?

author: ogden
author_rank: Super Contributor
timestamp: July 10, 2019, 10:26:46 pm
content: Quote from: tautech on July 10, 2019, 09:43:52 pmBecause VGA provides 40dB (100x) dynamic range. 13bits of ADC reach around 20dB (10x) with good SNR, ADC reference does not count because it is for small (<1dB) adjustments.

author: Mr. Scram
author_rank: Super Contributor
timestamp: July 10, 2019, 11:05:57 pm
content: Looks like we don't want Siglents on the channel in the future. The hardware isn't terrible but the crowd is a nuisance.

author: ogden
author_rank: Super Contributor
timestamp: July 10, 2019, 11:09:32 pm
content: Quote from: Mr. Scram on July 10, 2019, 11:05:57 pmWhat are you talking about? Mind to quote?

author: StillTrying
author_rank: Super Contributor
timestamp: July 10, 2019, 11:39:12 pm
content: After reading the HMCAD1511 data sheet I'm quite sure it doesn't have 13 ADC bits internally, although it does have 8 ADCs.If the fine gain could be adjusted by 2^9 the gain could only be adjusted to X 2 or X 0.5The 2^13 means amplitude wise 1LSB can be adjusted in steps of +/- 1LSB/(13-8) = +/- 1LSB/32, but there's still only 8 bits.I think.

author: ogden
author_rank: Super Contributor
timestamp: July 10, 2019, 11:58:03 pm
content: Quote from: StillTrying on July 10, 2019, 11:39:12 pmIt does not have 8 ADCs but 4. Datasheet states it clearly that it is not just 8 bit ADC internally, on DS page 23: "There will be no missing codes for gain settings lower than 32x (30dB), due to higherthan 8 bit resolution internally. ". BTW I was wrong about ADC gain step, it is actually 1dB. Will fix original post.

author: alpher
author_rank: Frequent Contributor
timestamp: July 11, 2019, 12:11:36 am
content: Quote from: Mr. Scram on July 10, 2019, 11:05:57 pmThey certainly are, rabid fanboyism is what swayed me finally toward buying a Keysight instead they beloved Siglent. So it worked against their (at least some of them) interests.They're like that ubiquitous used car salesman, when he start pushing that certain car on the lot , you know you have to run.

author: ogden
author_rank: Super Contributor
timestamp: July 11, 2019, 12:22:38 am
content: Quote from: alpher on July 11, 2019, 12:11:36 amThat's problem of salesmen, not car. In case of your example probably both are inferior. What I am trying to say - don't spoil your buyers decisions by analyzing salesman "performance" instead of product. Disclaimer: I am far from "fanboy" of Siglent.

author: StillTrying
author_rank: Super Contributor
timestamp: July 11, 2019, 12:33:54 am
content: Quote from: ogden on July 10, 2019, 11:58:03 pmPerhaps it's the way they're describing the differential inputs.P26:HMCAD1511 is a multi Mode high-speed, CMOS ADC, consisting of 8 ADC branches, configured in different channel modes, using interleaving to achieve high speed sampling. For all practical purposes, the device can be considered to contain 4 ADCs.P13:Quad channel mode interleaves 2 ADC branches, dual channel mode interleaves 4 ADC branches, while single channel mode interleave all 8 ADC branches.Edit:By my calculationyou need 8 ADCs to do 1Gsa/s from a 1GHz clock, although I'm confused by the timing diagrams.QuoteAnalog resolution might be 13 bit but the ADCs are 8.

author: Mr. Scram
author_rank: Super Contributor
timestamp: July 11, 2019, 12:46:51 am
content: Quote from: alpher on July 11, 2019, 12:11:36 amIt's the same here. Initially I thought Siglent was doing okay but considering anything that could look like criticism causes the Church of Siglentology to jump down your throat, it seems impossible to get a good idea of the drawbacks and issues with the products. The useful information is drowned out. If you can't inform yourself you can't make a good assessment and a sale is lost. The forum unfortunately also loses some of its value. I started looking elsewhere and it looks like it might be a Keysight too.

author: ogden
author_rank: Super Contributor
timestamp: July 11, 2019, 01:19:11 am
content: Quote from: StillTrying on July 11, 2019, 12:33:54 amThank you for pointing out about 8 ADC branches, yet it still does not add-up. To get 8x gain at ENOB of 8-bit ADC (7.6 bits), one need much more than eight 8-bit ADC's. Conclusion still is - internal resolution of ADC's is more than 8 bits. After all manufacturer states that and as already mentioned - I am sure they do not lie. Thou, it's interesting that in the datasheet ADC SNR/ENOB figures for 10x gain are specified for single channel only.QuoteNo you don't. I do not know internals of particular chip, but for example flash ADC will give one output per each clock pulse.

author: StillTrying
author_rank: Super Contributor
timestamp: July 11, 2019, 02:44:19 am
content: Quote from: ogden on July 11, 2019, 01:19:11 amYes, I can't find a description of the 1511 or similar internal workings.I still think the ADCs are 8 bit, and the part that is adjustable at the fine 2^13 resolution is each ADC's Ref. voltage or something, and all the other larger gain changes are done in analogue rather than ignoring the top or bottom 5 bits of a 13 bit conversion.QuoteI forgot they could be flash, but I doubt there's 4(or8) 13 bit flash converters in there.

author: David Hess
author_rank: Super Contributor
timestamp: July 11, 2019, 02:44:52 am
content: Thanks for the video Dave. The demonstrated non-decimal vernier step size gives some idea of what is going on. My cursory examination of the VGA datasheet seems consistent with the displayed vernier step sizes.My guess is that the fine gain control of the HMCAD1511 and similar ADCs is only being used for gain calibration between the ADCs when operating in interleaved mode as the datasheet discusses. Their range is just too small because they are meant for only this purpose. This explains why the external VGA is necessary for vernier operation. If there is another vernier adjustment, then I suspect it is being done by trimming the ADC's reference voltage but that does not appear to be happening here.Modern pipelined ADCs produce more bits per stage than strictly needed and then these bits are combined through digital error correction to produce the final monotonic output.The VGA here only has 7 bits of "vernier" gain control. The 8th bit selects between low and high gain mode.The Siglent's calibrated vernier settings seem to follow the vernier gain settings that are actually available in hardware rather than an arbitrary scale like decimal.

author: rf-loop
author_rank: Super Contributor
timestamp: July 11, 2019, 05:07:05 am
content: Quote from: EEVblog on July 10, 2019, 03:17:30 amThank you about this video update/edit. Now it looks much better if the viewer also carefully takes note of all the added texts.(there is some hidden details still what it do not explain but it can not do without hard work for fully "reverse engineer" also ADC control bus data and imho it is not needed in this context )

author: EEVblog
author_rank: Unknown
timestamp: July 11, 2019, 07:58:40 am
content: Quote from: tautech on July 10, 2019, 09:43:52 pmIt's NOT used on the Rigol. The Rigol does not have a VGA.As for Siglent, maybe they wanted different performance, or couldn't do it with the ADC alone. No idea, how about you ask them?

author: rf-loop
author_rank: Super Contributor
timestamp: July 11, 2019, 08:22:55 am
content: Quote from: tautech on July 10, 2019, 09:43:52 pmIt is not only vernier between main steps what need handle. Vernier steps and main steps are not different Exept in software)Example whole voltage band I from 500uV/div to 118mv/div there is over 350 steps in Siglent SDS1000X-E and all these need solve using VGA and HMCAD1511 internals together.Voltage bands II and III are bit more easy due to less steps.Just alone from main step 500uV to 1mV/div it use 10uV increments.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 11, 2019, 08:49:10 am
content: From die DS the ADCs inside are pipelined type ADCs with digital error correction. So the internal resolution needs to be higher, though possibly with missing codes that are only corrected later. So it is hard to even give a number for the resolution and it may very well be be not an integer number of bits. If the first pipeline stages are always one way with a small signal, the later stages may well give good resolution, like a 13 Bit ADC - though chances are it would not work that well (more DNL and possibly missing codes) if the initial stages are changing. With some 49.x dB SNR the ADC is pretty close to an ideal 8 Bit ADC at low gain.The gain adjust in the ADC is only really coarse steps (x2 , x 1.25 etc.) or very fine for a very small range. So it is not sufficient for a true vernier mode. It is still a little better than the normal 1:2:5 steps used on a scope.

author: tautech
author_rank: Super Contributor
timestamp: July 11, 2019, 10:27:24 am
content: Quote from: EEVblog on July 11, 2019, 07:58:40 amDon't need to.The answer to why Siglent used VGAandADC variable gain control is already in this thread:https://www.eevblog.com/forum/blog/eevblog-1226-how-to-get-better-accuracy-on-your-oscilloscope/And yes, the reasons have been further expanded on here.Sometimes things are not as straightforward as they first appear and require deeper investigation for full understanding as rf-loop has shown. Neither VGA or ADC on their own are sufficient to get the full range of Fine adjustment so both must be used in tandem so a HW and SW solution is the solution.

author: SilverSolder
author_rank: Super Contributor
timestamp: July 11, 2019, 10:57:32 am
content: Very interesting video and forum thread. To me, it made it clear that there are many ways to skin this particular cat - and clearly, there will be good and less good ways of implementing vernier gain, even with the same chips!Hard to think of a way to test oscilloscope vernier performance consistently, so different manufacturers/models can be compared...

author: thm_w
author_rank: Super Contributor
timestamp: July 11, 2019, 09:01:10 pm
content: So makes me think, if all these gain ranges are available in a $7 chip (AD8370), why do we still have the poor software multiplied ranges in the keysight/rigol.Even if the front end noise is too high, I think you'd still get a bit of benefit by having the extra gain ranges. Especially in the case of Rigol, adding an extra gain range to the ASIC should be minimal in terms of cost no? Maybe AD can get those performance levels but others can't.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 12, 2019, 07:26:34 am
content: How difficult it is to add an VGA to the ASIC depends on the process used for the chip. It may not be that simple, especially hat high speed. Anyway it will add power dissipation, making the chip run even hotter. An extra chip between the input stage and ADC is not such a bad solution.Besides the VGA chip, it also needs calibration for the gain stages if it is supposed to be accurate.For some cases (especially lowest gain) the VGA chip may also add some errors, linearity is limited and there can be a gain dependent delay. With a good (e.g. 10 Bit) ADC using just digital multiplication may not be such a bad decision.

author: Mr. Scram
author_rank: Super Contributor
timestamp: July 12, 2019, 02:57:13 pm
content: Quote from: thm_w on July 11, 2019, 09:01:10 pmPossibly because people don't know and care. A video like this may create more awareness. Of course most customers may simply not care if it gets the job done.

author: SilverSolder
author_rank: Super Contributor
timestamp: July 12, 2019, 05:16:15 pm
content: Maybe it's just me, but I would expect any scope to be implemented in a way that makes the best use of its hardware capabilities. If the vertical amp vernier control doesn't actually control amplification, it should be relabeled "vertical zoom" or something like that?

author: StillTrying
author_rank: Super Contributor
timestamp: July 14, 2019, 03:58:23 pm
content: I beginning to think the HMCAD1511 might not have anycoarseanaloguegainstages afterall.Instead, 8 X 13 bit 125MHz ADCs. 2V input from the top 8 bits gives the X1 gain, 62.5mV input from the bottom 8 bits gives the X32 gain.If the X50 gain is a digital multiplication of the X32 gain the top 92 values from the ADCs can't be used, because their values would be covered by the digital multiplication.