opamp simulation - Page 1
Forum section: electronics / beginners

author: promach
author_rank: Frequent Contributor
timestamp: April 13, 2019, 12:39:57 am
content: Is the following open loop transient simulation ofopampcorrect ?

author: promach
author_rank: Frequent Contributor
timestamp: April 13, 2019, 07:14:19 am
content: Ok, I understood why the output is pulled to the high voltage side.The culprit is M11. Vgd of M11 is 1.2V-0.25V ~= 1V. How to make M11 to be in saturation region ?

author: promach
author_rank: Frequent Contributor
timestamp: April 13, 2019, 07:26:36 am
content: Here you go :Code:* modified for use with LTSpice; DM 8/19/2008** 0.18u CMOS process** NMOS transistor model name: NM* PMOS transistor model name: PM*-----------------------------------------------------------------------.subckt NM D G S B+params: W=10u L=1uM1 D G S B NM L={L} W={W} AS={1.1u*W} PS={2.2u+W} AD={1.1u*W} PD={2.2u+W}.ends* ----------------------------------------------------------------------* NMOS transistor model* ----------------------------------------------------------------------.MODEL NM NMOS LEVEL=49* ----------------------------------------------------------------------************************* SIMULATION PARAMETERS ************************* ----------------------------------------------------------------------* format : LTspice* model : MOS BSIM3v3* ----------------------------------------------------------------------* TYPICAL MEAN CONDITION* ----------------------------------------------------------------------+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.354505+K1 = 0.5733393 K2 = 3.177172E-3 K3 = 27.3563303+K3B = -10 W0 = 2.341477E-5 NLX = 1.906617E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 1.6751718 DVT1 = 0.4282625 DVT2 = 0.036004+U0 = 327.3736992 UA = -4.52726E-11 UB = 4.46532E-19+UC = -4.74051E-11 VSAT = 8.785346E4 A0 = 1.6897405+AGS = 0.2908676 B0 = -8.224961E-9 B1 = -1E-7+KETA = 0.021238 A1 = 8.00349E-4 A2 = 1+RDSW = 105 PRWG = 0.5 PRWB = -0.2+WR = 1 WINT = 5e-9 LINT = 2.351737E-8+DWG = 1.610448E-9+DWB = -5.108595E-9 VOFF = -0.0652968 NFACTOR = 2.4901845+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 0.0231564 ETAB = -0.058499+DSUB = 0.9467118 PCLM = 0.8512348 PDIBLC1 = 0.0929526+PDIBLC2 = 0.01 PDIBLCB = -0.1 DROUT = 0.5224026+PSCBE1 = 7.979323E10 PSCBE2 = 1.522921E-9 PVAG = 0.01+DELTA = 0.01 RSH = 6.8 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 7.7E-10 CGSO = 7.7E-10 CGBO = 1E-12+CJ = 1.010083E-3 PB = 0.7344298 MJ = 0.3565066+CJSW = 2.441707E-10 PBSW = 0.8005503 MJSW = 0.1327842+CJSWG = 3.3E-10 PBSWG = 0.8005503 MJSWG = 0.1327842+CF = 0 PVTH0 = 1.307195E-3 PRDSW = -5+PK2 = -1.022757E-3 WKETA = -4.466285E-4 LKETA = -9.715157E-3+PU0 = 12.2704847 PUA = 4.421816E-11 PUB = 0+PVSAT = 1.707461E3 PETA0 = 1E-4 PKETA = 2.348777E-3*-----------------------------------------------------------------------.subckt PM D G S B+params: W=10u L=1uM1 D G S B PM L={L} W={W} AS={1.1u*W} PS={2.2u+W} AD={1.1u*W} PD={2.2u+W}.ends* ----------------------------------------------------------------------* PMOS transistor model* ----------------------------------------------------------------------.MODEL PM PMOS LEVEL=49* ----------------------------------------------------------------------************************* SIMULATION PARAMETERS ************************* ----------------------------------------------------------------------* format : LTSPICE* model : MOS BSIM3v3* ----------------------------------------------------------------------* TYPICAL MEAN CONDITION* ----------------------------------------------------------------------+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.4120614+K1 = 0.5590154 K2 = 0.0353896 K3 = 0+K3B = 7.3774572 W0 = 1E-6 NLX = 1.103367E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 0.4301522 DVT1 = 0.2156888 DVT2 = 0.1+U0 = 128.7704538 UA = 1.908676E-9 UB = 1.686179E-21+UC = -9.31329E-11 VSAT = 1.658944E5 A0 = 1.6076505+AGS = 0.3740519 B0 = 1.711294E-6 B1 = 4.946873E-6+KETA = 0.0210951 A1 = 0.0244939 A2 = 1+RDSW = 127.0442882 PRWG = 0.5 PRWB = -0.5+WR = 1 WINT = 5.928484E-10 LINT = 3.468805E-8+DWG = -2.453074E-8+DWB = 6.408778E-9 VOFF = -0.0974174 NFACTOR = 1.9740447+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 0.1847491 ETAB = -0.2531172+DSUB = 1.5 PCLM = 4.8842961 PDIBLC1 = 0.0156227+PDIBLC2 = 0.1 PDIBLCB = -1E-3 DROUT = 0+PSCBE1 = 1.733878E9 PSCBE2 = 5.002842E-10 PVAG = 15+DELTA = 0.01 RSH = 7.7 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 7.11E-10 CGSO = 7.11E-10 CGBO = 1E-12+CJ = 1.179334E-3 PB = 0.8545261 MJ = 0.4117753+CJSW = 2.215877E-10 PBSW = 0.6162997 MJSW = 0.2678074+CJSWG = 4.22E-10 PBSWG = 0.6162997 MJSWG = 0.2678074+CF = 0 PVTH0 = 2.283319E-3 PRDSW = 5.6431992+PK2 = 2.813503E-3 WKETA = 2.438158E-3 LKETA = -0.0116078+PU0 = -2.2514581 PUA = -7.62392E-11 PUB = 4.502298E-24+PVSAT = -50 PETA0 = 1E-4 PKETA = -1.047892E-4* ----------------------------------------------------------------------

author: iMo
author_rank: Super Contributor
timestamp: April 13, 2019, 07:45:18 am
content: It looks like it works, provided you will create a feedback loop with defined closed loop gain, DC offset etc.

author: promach
author_rank: Frequent Contributor
timestamp: April 13, 2019, 07:47:40 am
content: Could you explain more on your feedback circuit ?

author: iMo
author_rank: Super Contributor
timestamp: April 13, 2019, 07:54:39 am
content: https://en.wikipedia.org/wiki/Operational_amplifier

author: promach
author_rank: Frequent Contributor
timestamp: April 13, 2019, 08:13:58 am
content: I have updated my opamp circuit with negative feedback and the output voltage is now less than 2.5VAnd all mosfets are in saturation.Please correct me if wrongNote: I have attached the updated opamp.asc

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 13, 2019, 11:55:48 pm
content: OK, lets peal the onion.Start with bias. I do not think this is what you intended with M10. Eliminate Vb1 and short gate and drain of M10. That will bias it and mirror Ib1 to the other current sources.Next, you common mode input is almost at ground. You can often get away with this when driving a pch diff pair. But in the feedback configuration, you might have a problem.

author: promach
author_rank: Frequent Contributor
timestamp: April 13, 2019, 11:58:56 pm
content: The mosfet_018.lib is posted in this forum thread. I think third post. Look carefully.QuoteI do not understand this. Could you explain using pictures ? Why almost at ground ?QuoteOk

author: promach
author_rank: Frequent Contributor
timestamp: April 14, 2019, 12:14:44 am
content: Oh, the circuit has so little gain-bandwidth product. Why ?

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 14, 2019, 12:22:45 am
content: See attached model.You need to take the inputs off ground. You can't amplify a negative signal.Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 14, 2019, 12:30:30 am
content: For the loop response. Use this model.You will get:Regards,Jay_Diddy_B

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 14, 2019, 12:31:04 am
content: Quote from: promach on April 13, 2019, 11:58:56 pmI deleted that comment right after posting it. You saw it before I deleted.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 14, 2019, 12:40:12 am
content: Here is an interesting thing to try.Step the bias current:You will see you get higher GBW for higher Ibias.Regards,Jay_Diddy_B

author: promach
author_rank: Frequent Contributor
timestamp: April 14, 2019, 01:25:12 am
content: In your opamp_JDB_bode_plt.asc , why DC 0.6V input stimulus for Vin+ ?And why are you not using large LC for DC feedback ?

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 14, 2019, 02:01:54 am
content: Quote from: promach on April 14, 2019, 01:25:12 amThe op-amp will only work properly if both inputs are within the common mode range and the output is between the supply rails.If I step the input voltage and measure the Bode plot:I have changed the feedback to be a voltage follower, that is a gain of +1. A negative input would require the output to be negative. It can't go negative because we only have a positive supply. So the output would be near zero and there would be no gain.If the input is 0V, the circuit will work for positive half-cycles, but not negative half-cycles. If the input is positive, the circuit works properly.I get these results:If I look in the time domain, transient analysis, and I step the voltage and apply a 100mV peak 1kHz sinewave, is see this. You can see that this op-amp doesn't work if the output is required to go negative.You can also see that this op-amp has a 'defect' called phase reversal when the inputs are near or just below zero.The choice of using an LC or positioning the voltage source like I did is preference.Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: April 14, 2019, 02:27:31 am
content: Hi further to my last post, consider these circuits:In one I am just using the voltage source and in the other I am using the large inductor and capacitor to close the FB loop.If I look at the results:In both cases I get 80dB which is 10000, the gain of the amplifier being tested. The phase is different. In one case I am measuring the inverting input, so I get -180 in the other the non-inverting input so I get 0 degrees.Regards,Jay_Diddy_B

author: promach
author_rank: Frequent Contributor
timestamp: April 14, 2019, 12:20:23 pm
content: QuoteWhyis that so for the "near zero" case ?See this updated schematics.

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 14, 2019, 03:22:05 pm
content: I tweaked your design a little bit. Improved the cascode stack.

author: promach
author_rank: Frequent Contributor
timestamp: April 15, 2019, 12:55:16 am
content: here is your opamp3.ascWhy are you using small LC (L1, C3) ?Could you also explain analytically on cascn, cascp and biascn ?I have done some modification to your opamp3.asc and put it side-by-side to my latest opamp.ascI am bit curious on how to improve the phase margin of your opamp3.asc (left)

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 15, 2019, 01:00:04 am
content: L and C in that schematic have no impact during transient...they are there for the ac simulation, but for transient unity gain, I kinda make them invisible. Easier than deleting components and then adding them in later.I did not investigate phase margin.What phase margin are you wanting to achieve?

author: promach
author_rank: Frequent Contributor
timestamp: April 15, 2019, 01:32:41 pm
content: Is it possible to achieve phase margin of 70 degrees with opamp3.asc ?Could you also explain analytically on cascn, cascp and biascn ?

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 15, 2019, 02:00:18 pm
content: Quote from: promach on April 15, 2019, 01:32:41 pmYou can increase the two compensation capacitors, or you can reduce the gain (load it with a 10k resistor).I created the bias string before making any other tweaks...thinking I might need several bias references. In the end I only needed but two of them (the two cascodes) but left the string intact.

author: promach
author_rank: Frequent Contributor
timestamp: April 15, 2019, 02:26:57 pm
content: For improving phase margin of opamp3.asc , I use an extra series resistor to put a zero near the unity gain frequency.but then, good accurate resistor is hard to fabricate.So, let me ask: anyone have any idea on how to replace both the ideal current source and the extra resistor with a mosfet in ohmic regionwithout using any extra bias voltage source?In other words, is it possible to useconstant gm bias circuitin your opamp3.asc or my opamp.asc circuit ?

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 15, 2019, 03:35:50 pm
content: Quote from: promach on April 15, 2019, 02:26:57 pmYes. Both of your references are sound.

author: promach
author_rank: Frequent Contributor
timestamp: April 16, 2019, 10:32:15 am
content: For theImprovements_in_biasing_and_compensation_of_CMOS_opamp(second reference link), why the author break open the connection between gates of M3A and M3B ?And how to derive the inequality expression (14) in the document ?

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 16, 2019, 01:11:52 pm
content: Quote from: promach on April 16, 2019, 10:32:15 amSet P3 < P1 and simply do the algebra.Eq 14 appears to have an error...should be gm2b in numerator, not gm2a

author: promach
author_rank: Frequent Contributor
timestamp: April 17, 2019, 03:00:49 am
content: QuoteI will check your advice regarding the inequality expression, but why set P3 < P1 ? Is it dominant pole compensation or something else ?I try to incorporate the author schematics (Figure 6 in the second reference link) into the opamp, but it resulted in erroneous bode plotWhich part is wrong in the schematics ?

author: Wimberleytech
author_rank: Super Contributor
timestamp: April 18, 2019, 11:45:07 am
content: Quote from: promach on April 17, 2019, 03:00:49 amyes, essentiallyQuoteALWAYS check bias points before even looking at your ac response. In this case, your biasing is broken.

author: promach
author_rank: Frequent Contributor
timestamp: April 19, 2019, 01:25:38 am
content: See the following circuit :I am having problem using the miller lead compensation (M24 mosfet in triode region)Any help ?When I sawthis 90MHz bandwidth opamp OPA838, I am inspired to do the same, but my current circuit bandwidth is only 10MHz.

author: promach
author_rank: Frequent Contributor
timestamp: April 19, 2019, 05:46:59 am
content: I managed to obtain unity-gain bandwidth = 275MHz , phase margin = 76 degrees , Gain = 93 dB , Power dissipation = 366 uW

author: promach
author_rank: Frequent Contributor
timestamp: April 20, 2019, 09:53:58 am
content: QuoteWait, I tried setting P3 < P1 , but I am getting totally different result from expression 14.I think you have wrong interpretation of expression 14 ?