How do I program WDC W65C816? - Page 1
Forum section: electronics / general

author: technix
author_rank: Super Contributor
timestamp: October 05, 2018, 02:47:10 am
content: I ran across that chip one day. How do you program it? Also is there a common memory map for that chip?p.s. I found an Intel application note on implementing a LPSDRAM controller in EPM570. How far from a regular voltage SDRAM controller is that? For W65C816 and 68SEC000 projects that CPLD DRAM controller means a cheap implementation for 8-64MB system memory.

author: ale500
author_rank: Frequent Contributor
timestamp: October 05, 2018, 04:15:16 am
content: The 65C816 is a microprocessor, no flash, eprom, eeprom or similar inside. So you store the program in some kind of non-volatile memory and let it run!. There are many projects around using the chip, you may want to search the likes ofhttps://www.retrobrewcomputers.org/forum/index.php?t=thread&frm_id=1&.I think that there is a 3.3 V version, if not it is a 5 V part, so you need level-shifting. Last I checked, the EPM parts (MAXII) go upt to 3.3 V only. The 68K is another story, because a 3.3 V version exists, the 68SEC000. Look at the retrobrew website where I show one way of doing it (Not new as the Minimig project used to do the same but to a Spartan3).Do you have a link to the app note ?

author: technix
author_rank: Super Contributor
timestamp: October 05, 2018, 04:37:08 am
content: Quote from: ale500 on October 05, 2018, 04:15:16 amHere it goes:https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an499.pdfQuote from: ale500 on October 05, 2018, 04:15:16 amI actually have a few MC68SEC000 samples. If that app note code can be modified into a 3.3V SDRAM controller it would be fairly simple to build the bus controller and SDRAM controller into one EPM240/EPM570 chip. It would result in a cheap MC68SEC000 system combined with 8MB SDRAM and 2MB NOR Flash. Also the SDRAM runs at a few times the speed of CPU, maybe the CPLD or FPGA should also contain a L1 cache controller using its internal block SRAM?

author: ale500
author_rank: Frequent Contributor
timestamp: October 05, 2018, 04:50:57 am
content: SDRAMs are 3.3 V parts, and the EPM570 too. No level shifting needed. Only to connect to a 5 V part.

author: technix
author_rank: Super Contributor
timestamp: October 05, 2018, 11:54:14 am
content: Quote from: ale500 on October 05, 2018, 04:50:57 amThe problem is the command structure. Does 3.3V regular SDR SDRAM and 1.8V Mobile SDR SDRAM use the same instruction set and command structure? If so, lose the level translation and there goes the memory controller on a 100-pin part or a complete bus controller with the 144-pin part.The memory would be running at 100MHz though, several times faster than the processor (4x for a 25MHz 68SEC000, 8x for a 12.5MHz W65C816.) Do I need to perform some optimization like adding a write-through cache in there and add a second cached port for the graphics? (The similar question exists for another crazy idea too: coupling Am80486DX4 with XC6SLX16-2CSG256C with a 33MHz bus and DDR3-1600 memory, a 48x slower bus for the DRAM.)

author: ale500
author_rank: Frequent Contributor
timestamp: October 05, 2018, 04:00:01 pm
content: Look at the access times for random read or write... and yeah a read cache would be something useful.MAX II CPLDs suppor between 1.5 and 3.3 V for the IO, so you use a couple of banks to interface the SDRAM and another one for the processor. You have to look for the info at intel's website, they seem to have hid most MAX II referencies

author: Rasz
author_rank: Super Contributor
timestamp: October 05, 2018, 07:03:30 pm
content: Quote from: technix on October 05, 2018, 11:54:14 amlike ale500 said, SDRAM marketing timing parameters are about bus clock (or best case scenario transfer speed), not access time. There was no major ram break-thru between EDO and SDRAM technologies, just packaging slightly inteligent controller into ram chip to simplify/unify interfacing.That 100MHz ram is ~just as slow as fastest FPM DRAMs from 1995 when accessing one byte at a time, and thats what W65C816 will want to do.

author: technix
author_rank: Super Contributor
timestamp: October 06, 2018, 12:38:53 am
content: Quote from: Rasz on October 05, 2018, 07:03:30 pmThat is the whole point of adding a read cache. When the CPU request one byte the cache controller turns it into an aligned burst read of 8 to 16 bytes. There is a good chance that the CPU will be requesting the next byte very soon after, which allows me to immediately return from cache without the request going to the DRAM controller.

author: Rasz
author_rank: Super Contributor
timestamp: October 06, 2018, 06:55:15 am
content: Yes, so now you have even more complicated design, or you could just throw in 2MB (way too much for W65C816, good amount for 68000) of SRAM (4xAS6C4008) and be done with it

author: technix
author_rank: Super Contributor
timestamp: October 06, 2018, 02:45:16 pm
content: Quote from: Rasz on October 06, 2018, 06:55:15 amFor my design there need to be a CPLD as bus decoder anyway. The SDRAM controller is almost free for me since it just occupies otherwise unused logic, and I just decreased the chip count by three.I have been searching for CPLD devices suitable for retrocomputing projects. It can be more expensive for me to go with a bigger board with discrete logic (even the cheaper SMT 74HC series) than condensing all logic into a few CPLDs simply due to the PCB cost.

author: technix
author_rank: Super Contributor
timestamp: October 08, 2018, 02:04:05 pm
content: Quote from: Rasz on October 06, 2018, 06:55:15 amThis just occurred to me: I have a stack of IS62WV51216BLL-55 chips - 18MHz 3.3V SRAM chips at 1MB each (512k x16.) For chips running at 10MHz (e.g. MC68SEC000-10) are those better choice than SDRAM? Also since 68SEC000 is fully static can I just cut clock to the core when I need to lower the system power?

author: iMo
author_rank: Super Contributor
timestamp: October 09, 2018, 03:25:53 pm
content: With 68k (3.3V) there is a nice option to go with something like IS66WVE4M16ECLL-70BLI-TR - that is the PSRAM (pseudosram) 4Mx16 70ns. SRAM interface, SDRAM internally.I worked with it, it is a 48BGA, easy to solder. Quite cheap years back.

author: technix
author_rank: Super Contributor
timestamp: October 09, 2018, 06:01:36 pm
content: Quote from: imo on October 09, 2018, 03:25:53 pmThat thing is a bit hard to find here sadly.

author: iMo
author_rank: Super Contributor
timestamp: October 11, 2018, 09:00:24 am
content: http://www.mouser.cn/ProductDetail/ISSI/IS66WVE4M16EBLL-70BLI?qs=sGAEpiMZZMt9mBA6nIyysLlQZMenxQHXPDoA5%2f6vM5s%3d$5 single quantity..