FPGA drive multiple DDR SDRAM chips - any experience ? - Page 1
Forum section: electronics / general

author: Miyuki
author_rank: Frequent Contributor
timestamp: April 29, 2016, 08:37:40 am
content: HiI want to ask if anybody have experience with interfacing FPGA with SDRAMI'm planing to build small scope/data logger, have two 100MS 10bit ADC some cheap FPGA (like Lattice XP2) and some SDRAM chipsI want as big memory as possible, with lowest possible cost. 1Gbit DDR2 chips cost almost nothing.Question is how many chips I can have in single data bus. I cant find much data about it, just some like dual rank DIMM. But I want something like four or five 16x memories on one bus/channel and have two this channelsWhen I keep clock as low as possible (need write just that 250MB/s so clock can be less than 100MHz) can I drive five memory chips ?

author: jahonen
author_rank: Super Contributor
timestamp: April 29, 2016, 09:25:41 am
content: I have done one design with Altera cyclone III with 8 DDR2 chips running at 166 MHz clock (DDR 333), two 32 bit banks.It is doable if you take care to do the balanced tree layout (split by two successively until you have enough branches) for address/control lines, to cancel out the reflections. I would strongly recommend that you do some preliminary feasibility study with some kind of SI simulator (HyperLynx or something) to check if it is going to work and to determine the termination scheme.Regards,Janne

author: Miyuki
author_rank: Frequent Contributor
timestamp: April 29, 2016, 09:54:32 am
content: I was thinking about simple bus topology:FPGA === RAM == RAM == RAM == RAM = terminationAs I need just simple circular buffer, only one at time need to be active and others can be in self refresh "sleep"Or is it bad way to do ?

author: Scrts
author_rank: Frequent Contributor
timestamp: April 29, 2016, 04:14:54 pm
content: Quote from: Miyuki on April 29, 2016, 09:54:32 amCheck if your FPGA is capable of that first of all. Also check their reference designs. 2 memory chips is relatively common design and beyond that it becomes complex.

author: nctnico
author_rank: Super Contributor
timestamp: April 29, 2016, 05:47:17 pm
content: Actually when clocked at 166MHz and when using a hardware DDR controller in the FPGA the design should be doable with multiple chips but proper termination, drive strength control and proper routing (no stubs in the data lines!). Nowadays 166MHz isn't that crazy high.

author: Scrts
author_rank: Frequent Contributor
timestamp: April 29, 2016, 06:14:47 pm
content: It all goes to impedance matching, signal strength and setup/hold margins eventually.

author: jahonen
author_rank: Super Contributor
timestamp: June 16, 2016, 10:53:44 am
content: I just wanted to update that we got 8 chips of 8x DDR3 (8 GiB of memory!) running at 300 MHz on Cyclone V with software memory controller.Design contains two banks of x16 RAM, 64 bit total data width. Seems to work fine. We just did careful balancing of address/command-line branch (3 splits into two) lengths, and signal termination with termination regulator. Cyclone V does not support DDR3 fly-by so DDR2 style balanced tree topology is the only possible option. It seems that careful design of the bus topology and termination scheme with Hyperlynx LineSim was time well spent.Regards,Janne