High Resolution, Discrete Delta-Sigma ADCs - Page 1
Forum section: electronics / general

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: September 11, 2025, 05:07:33 pm
content: I have seen designs related to making high resolution multislope converters (Kleinstein's for example, which uses the residue ADC strategy to get high resolution with a reasonably simple design), but I have not seen as much discussion around making discrete, high resolution sigma delta ADCs. I believe the tightest linearity spec for an ADC on the market is 30 ppb full range for the Isotech Micro-K gold, which is used in a high performance thermometry bridge. This ADC uses a fourth order sigma delta modulator with a 5-bit PWM DAC in the loop. The DAC linearity spec required a lot of design effort to achieve the requisite timing accuracy from what I have read in a monograph by forum member Christopher Dakin. I have wondered if it would be possible to build up a reasonably high performance SD converter using some of the principles in that design with a one-bit DAC instead.To suppress quantization noise and idle tones, the modulator should be high order, really as high as can be made stable. The linearity requirement also dictates that some topologies are not usable (see:https://backend.orbit.dtu.dk/ws/portalfiles/portal/4364572/Steensgaard.pdf). For example, the frequently used cascaded integrators with feedback (CIFB) places the linearity requirements entirely upon the first integrator. Multistage Noise Shaping (MASH) topologies are also not suitable for the application because of the gain matching requirements between stages at high orders to obtain good noise shaping performance. A reasonable topology would be cascaded integrators with feedforward (CIFF). I modeled a 5th order modulator using this topology that appears to be stable in simulations with a 1 MHz clock frequency. The quantization noise would be well below the integrator + input + DAC noise below frequencies of a couple hundred Hz. I tested this by modeling quantization noise as an AC source and also by taking the FFT of the bitstream in a transient simulation.Another part is the feedback DAC. I think that it is somewhat glib to say that a 1-bit DAC is inherently linear due to the possibility of intersymbol interference (ISI). For example, with a current steering DAC, the total charge delivered from two successive 1s may be more or less than twice the charge delivered from a 01 or 10 combination. I have not fully looked into ways of combating this problem, and I am open to ideas. I expect that ISI could be the limiting factor for accuracy.Using correlated double sampling to null offset and gain errors is another feature of the Micro K. I have attached a schematic that incorporates this strategy with a 5th order modulator. Referring to that schematic, there are eight possible input switch combinations. Running these in sequence for each conversion would null the gain error, offset error, 1/f noise of the integrator, and excess noise of the resistor network used in the current steering DAC, at the cost of a sqrt(2) noise penalty. If the input switching is faster than the thermal time constant of the resistor network, the power coefficient of resistance (ratio), which would give nonlinearity errors, is also nulled. This allows the use of somewhat smaller resistors and also ensures that the gain of the ADC is drift-free (excluding reference contributions). It would not cancel linearity errors due to channel length modulation or other V_in impacts of switch Rds_on, so there is an additional circuit to attenuate this effect. The noise floor for the ADC should end up around 30 nV/sqrt Hz with autozeroing.I also included a way of resetting the modulator in case of saturation because it is possible that this could happen on startup. My plan for receiving the bitstream is to use the MDF peripheral on an STM32U5 MCU to do initial decimation down to 24-bit words and do further processing on a host PC to try different filter designs.I am aware that there are many forum members who are more knowledgeable in Delta-Sigma modulator design than I am, so I am including this design more as a starting point of a discussion on the topic than anything.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 12, 2025, 08:37:31 am
content: There is quite some information about a higher resolution discrete build (and contineous time as opposed to the switched capacitor type usually found if chips) SD ADC from CERN.One problem that I see with a pure 1 bit DAC is the rather high switching rate. Because of the extra charge pumping and settling effects during transitions one kind of needs a constant switching rate and thus an additional in between phase. One can still have some issues with not yet fully complete settling as a way of ISI to cause nonlinearity.I don't see a PWM DAC that much more complicated, just more resolution with fewer switch transitions. The switch operations can cause noise from jitter and linearity issues from not ideal settling or charge injection. So less frequent switching is preferred. With a PWM DAC and thus a bit slower switching the first integrator would see a slightly larger voltage swing. The modulation frequency is still high enough to not expect noise issues and if there is an linearity problem with this, it would be more a local repeating DNL issue not so much the difficult to deal with long range INL.The PWM from the PWM DAC would not use the full 0 -100% range, but more like 10% to 90% to avoid very short pulses. This comes with a small SNR penalty, but helps with linearity. Also the 1 bit case would be more 20% or 80% and not 0%/100% that has issues with the number of switching events.IFAIK there is also some stability issues (likely beyond the simple linear picture) with more than 2nd order integrators, that kind of require more than an 1 bit DAC. For a discrete build I don't think the parallel thermometer style DACs used with some ADC chips are practical, as these need quite some extra effort / parts. This is less an issue on a chip as it would come with smaller capacitors and switches.For the proposed circuit I don't seen a need for the integrator reset switches. Especially the switch at the first integrator would be an issue as switch leakage would cause issues.For the choice of parts I would consider starting with more moderate speed OP-amps for the initial tests. This makes it easier to measure settling effects and similar to get an idea how much is there. One can than in a 2nd step change to faster parts where needed.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: September 12, 2025, 11:52:29 pm
content: Quote from: Kleinstein on September 12, 2025, 08:37:31 amDo you have a link for that?I do think that implementing a guard period between each clock cycle where the DAC input is high impedance is a good idea, but it would require complicating the relatively tidy scheme I have here. Bringing both LO (gate) inputs of the quad MOSFET high would mean it is sourcing no current, but that would essentially ground the input to the first integrator, which would be bad. Bringing both LO inputs low would cause the drains to slew until they had forward biased the protection diodes, but then the Rds_on compensation op amps would be slewing back and forth every cycle. I suppose an alternative would be to put another switch (which, for level and timing reasons would have to be a PE4140) between the RF inputs (sources) and turn it on when turning the second gate on. That would be more complex, but it would do the job. Moreover, you could use the same scheme to use PWM to do multibit feedback.I do think it would be worthwhile to add the option of implementing a PWM DAC, but I have seen up to fifth order modulators with single bit feedback in the literature. Making the feedback decisions quickly enough in an MCU would be difficult for more than a couple bits because a global interrupt would be required. But the stability would be better, and the speed requirements for the first integrator would be much lower. Two bits would be doable with a three-section comparator and an OR gate, beyond that an ADC would probably be best, and it would have to be very low latency.Either way, the DAC does carry the full linearity burden of the converter, and the INL would be kind of a smoothed out version of the DAC INL. The reason for this is that the vast majority of the time, the DAC will alternating between two levels.You may be right about the first stage reset switch. I can change this to a low leakage JFET switch instead. If there are potential stability issues, however, it will pay to be able to reset the integrators because they will just end up saturating. I can use the lower bandwidth ADA4805 in place of the ADA4807 during testing. In place of the OPA818, I could do something unity gain stable like the ADA4817-1, which can use the same footprint. It is not exactly a slow op amp, but it will be less of a nuisance to stabilize than the OPA818. I would like to keep that footprint because it will ultimately need to be a wide BW amp, and a lot of them have that pinout.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 13, 2025, 07:43:59 am
content: If the reset switch is needed one can improve on the leakage with 2 switches in series and a ground link in between. This would be easy with still one switch unit unused.To get a zero inbetween switching would not need extra switches, but a different control logic (not shown in the schematics). The switching is already between on and off (send the current to ground). The extra phase will however reduce the usible range. So the 13 V ref. may be just barely enough to reach a 10 V range. Similar getting PWM feedback could use the same switch control. The point with a PWM type feedback is more on how to make the decision - maybe too much for µC control and only the comparator signal.The linearity with a PWM DAC and the simple 1 bit modulation should not be that much different: the burden is mainly on the integrator. The PWM case kind of corresponds to a idle tone case. The advantage with PWM is in a fixed number of switch operations to start with or fewer switch operations when the additional switching is added to 1 bit modulation.I don't think the simple 1 bit modulation without the extra fixed 01 phases would work, as there is some net charge injection from switching cycles. As a complication the extra fixed phases would add some minimim time the reference is active. As shown the ADC would no longer work all the way to 0 V anymore. Even without the extra switching a small offset or leakage current could shift the range away from 0.So one may want a 3rd pair of switches and thus both a positive and negative reference available via the fast switches and not just the slow MUX for +-ref and the input. The question is than still if one handles the 4 possible setting of +ref, -ref, zero, +ref and-ref as just 2 states + and - or as +,- and 0 as a 3 state FB signal. The 3 state case would need a very accurate +-ref ratio.The need for more than 1 bit for more than 2nd oder integrator was for a SD DAC. With an ADC it may still work, but may need an accurately designed integrator with the right amount of feed forward parts and in the contineous time the right modulation frequency.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: September 13, 2025, 06:33:34 pm
content: I think I understand the scheme you are thinking of - the DAC control signal always starts at 0 and ends at 1, so a 1-bit DAC would have 0 and 1 be 10% and 90% duty respectively (or something like that). I believe including the gates as shown below with DUTY_CTL being a signal that goes high straddling the clock transition would do the trick (with a complementary output flip flop clocked at maybe 50-100 MHz to clean up jitter). It would be nice to be able to vary whether each period starts with a 0 or a 1 to be able to cancel any errors arising from that out, which I guess would take another XOR gate. I will revise the schematic to include this, but it is getting to a lot of discrete glue logic. My only hesitation with this is that the added delay will reduce the stability of the modulator.With two more comparators in there, I can at least test out 1-bit vs. 2-bit feedback, but I think that going beyond that will be out of MCU territory.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 13, 2025, 07:27:28 pm
content: I initially though about start at 0 and end with 1, but for the simple 1 bit modulation one could also get away with just a short phase with alwas zero between the symbols. This way the 2 switching events from 0 to 1 and back, with there possible added net charge injection would be part of the reference strength. Different from the multi-slope ADC one does not need the run-up steps to be related to the fast run-down part, as there is no run-down. There could still be an advantage of an added mandatory 1 phase, though it adds an offset and would definite need changes with the references.I am not so sure that one would need a super fast clock for the sync FF's. The time window is anyway limited by the settling speed of the integrator. So I would consider some 50 ns as a lower limit for short phases.