Reactive Clock Driver Circuit - Page 1
Forum section: electronics / projects

author: mawyatt
author_rank: Super Contributor
timestamp: November 19, 2022, 08:38:03 pm
content: This is about a means to save much of the power dissipated when driving a highly capacitive load with a repetitive clock pulse waveform.A little history about this concept. We were awarded a contract to develop a battery power Handheld Real Time Spectrum Analyzer (RTSA) back in 1980~81. The RTSA concept was based upon a tiered Chirp Z Transform (CZT) and the lower tier CZT had very long Real and Imaginary CCD convolvers which had 4 clock inputs, 2 of which were very large clock capacitances.Prior efforts to develop this RTSA by two large West Coast Technology Firms (CA) with in-house custom CMOS capability had failed. One of these firms had recognized the power consumption of the large CCD capacitances and developed a multi-tapped transformer approach (we were told they were patenting the concept) to reduce power consumption, so we needed to avoid this approach and started looking for another means to drive the CCD clock large capacitances.After much research, and not finding any prior work, we ended up with a technique where the clock energy required to charge the CCD capacitances was exchanged from another source/de-coupling capacitance with an inductor and transferred to the CCD capacitance for the high voltage state (+15), then recovered with the same inductor to the source/capacitance for the low 0 volt state. A low-loss series LCR circuit allows the peak to peak voltage across C to be ~ doubled from the peak voltage across L at resonance. The idea is to "Open" a series switch when the inductor current is 0, then the C voltage is maximum peak and then the switch is closed and the L current swings to maximum magnitude and again back to zero when the switch is again opened. At this time the C voltage swings down and is ~ 0. The peak to peak voltage across C is ~ 2X the peak magnitude voltage across L which alternates polarity. The circuit shown also has the feature to self regulate and optimize power loss without any additional effort or circuitry (a concept that the late Bob Pease disputed and later conceded when a wager was proposed, but that's another story).The voltage across the mid-level bypass filter capacitor will self adjust to minimize the overall clock driver power consumption. To be honest this was discovered by accident, during a early testing setup to evaluate the new CCD chips. A number of DMMs were connected to the various PS inputs of +15V, +-15, +5 +-7.5, and a couple reference voltages and a number of analog scopes connected to various test points and clocks. While reaching across the setup we knocked off the clip lead that supplied the +7.5VDC for the Reactive Clock Driver and while attempting to reconnect we noticed the clock waveforms on the scopes didn't change. Upon further investigation we noticed the supply current from the +15VDC clock supply actually dropped without the clip attached, and none of the other supply currents changed. So without the 7.5VDC bias supply connected the overall power consumption was lower for the CCD and without any detrimental effects to the waveforms and performance!!What was happening, the circuit would self-servo to a condition where the average current thru the inductor would be ~ 0 and thus not "wasted". We monitored this bias voltage while changing the +15VDC main clock voltage, and later changed component values and temperature, and the voltage would self-regulate to optimum low power condition!! We should have patented the idea but didn't and about 7 years later NASA patented a similar CMOS driver for driving large Gate capacitances in Power MOS devices. Eventually we were allowed to publish and did so in 1989 EDN.Back in ~2007 we were developing a custom CMOS Digital System on Chip that needed to be very low power and resurrected this old Reactive Clock concept. We prepared a brief booklet for the Digital chip design folks to use, since we weren't part of this chip development, and this booklet is where these pages originate.Anyway, some folks may find this Reactive Clock circuit concept interesting and useful, so here it is. Note the EDN article included an HP41C program as shown, the various formula derivations are left to the reader.BTW: The RTSA worked very well indeed and put "us" on the mapBest,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 19, 2022, 11:25:27 pm
content: Pretty simple. The thought has occurred to me, say for gate driving, but power MOSFETs don't have low enough gate losses, and most applications benefit more from a higher Fsw, than this would be helpful for. You'd also be stacking up quite a lot of MOSFETs to get conduction losses down enough that drive losses matter.If you don't have a mid rail (I hadn't thought of the bypass cap, that's nice), can also just switch a half-bridge at both ends of the inductor; the inductor ends up overcharged (it doesn't make a sigmoid wave but just slams into one side) and clamp diodes (body diodes, or do it synchronously) return that charge into the supply.Also reminds me of "lossless logic" which had some articles a number of years ago, but I don't know that anything's come of it since... Seems nice, but I'm guessing the very low density isn't worthwhile yet, and will need the development of multilayer chips to make its low power density worthwhile. Also probably slow clock rates which will necessitate even wider buses (but that's also very amenable to current neural net tech with high speed not being so important, and what with the added dimension being available to better optimize layout). Anyway, such a driver would be a key component.Tim

author: mawyatt
author_rank: Super Contributor
timestamp: November 20, 2022, 01:01:39 am
content: Yep, simple is what we wanted, the tapped transformer used by the other firm was quite complex. We required 4 of these Reactive Clocks per chip, and forgot how many convolver chips were employed, probably 16 or more just in the second tier. Recall we saved something like ~96% of the power wasted with a conventional CMOS driver.In fact this concept worked so well with self-correcting for optimal power consumption we used the Reactive Clock created mid-level voltage (~7.5V) as an efficient low power source for some other analog type functions!!The CCDs even liked the truncated smooth sine-wave rise and fall waveforms, the Charge Transfer Efficiency (CTE) or charge out/charge in per tap transfer became almost perfect at something like six 9s at 0.999999!! Since the CCDs had over 10,000 taps, the charge was transferred over 10,000 times from the convolver input to output, and you could count the electrons left behind after a transfer, they were that good!! The Charge Transfer Function (CTF) outputs of each of the Real and Imaginary Convolvers is modulated by the CTE as CTF = CTE^(N), where N is the number of tap transfers. So at 10,000 transfers the Charge Transfer Function was 0.999999^10,000 or > 99% efficient, or ~0.087dB loss!!Interesting you mention "lossless logic". Dr David Lamb was researcher from London and a leading expert on CCD devices (way back he co-authored a book on Charge Coupled Devices and Their Applications). He joined us (Honeywell) later and helped with the final developments of the CCD convolvers, and much later got involved with Null Convention Logic, or NCL. Much much later he left and founded a company in Orlando, Florida called Invigicom, and recall they were involved with NCL.Edit: Here's some info for a Reactive Clock Driver test chip back in 2007 for use by the Digital folks, think this was in 130 or 90nm CMOS. The inductor was realized by just a wire bond across a couple pads. The digital folks were working on some low power but high computing power logic that didn't require really fast clocks, it was massively parallel.Best,

author: KE5FX
author_rank: Super Contributor
timestamp: November 20, 2022, 02:33:31 am
content: Cool stuff. I'd never heard of performing convolution with a CCD by itself before, but it'sobvious enough in retrospect. Bragg-cell analyzers that are read out by a CCD are old hat, but I guess this idea has the advantage of dispensing with the Bragg cell, given a fast-enough CCD.As usual, in the long run nothing ends up beating CMOS.

author: mawyatt
author_rank: Super Contributor
timestamp: November 20, 2022, 02:47:38 am
content: This was for use in the MW frequency range and the CCD Convolvers were operated with Discrete Time Continuous Amplitude (DTCA) domain, sorta like one foot in analog and the other in digital domains.Best,

author: Terry Bites
author_rank: Super Contributor
timestamp: November 21, 2022, 10:22:49 pm
content: What ever happened to adiabatic logic?

author: Circlotron
author_rank: Super Contributor
timestamp: November 21, 2022, 11:17:00 pm
content: Quote from: mawyatt on November 19, 2022, 08:38:03 pmTwenty years ago I did a whole lot of work on lossless resonant snubbers for PFC boost converters up to 3kW size. Then along came SiC schottky diodes that put all that hard work and fun in the dustbin of history.The subject is practically an entire discipline in itself. What you are describing is so reminiscent of the work I was doing at the time.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 22, 2022, 02:28:45 am
content: Quote from: Circlotron on November 21, 2022, 11:17:00 pmHah, not to mention quasi-resonant. Assuming you can get a good enough inductor (for any kind of power and speed, gapped ferrite + litz is mandatory!), that shit runs pretty damn smooth. Tried it with a PN diode, waveforms were fine, but the poor diode ran very toasty; SiC, hardly noticeable. Big cut to the harmonics too, smoother waveforms.Schottky have basically taken over all switching rectifier applications, and I must say I like it. PN diodes are mainly for, I guess extreme cost reduction where size and efficiency aren't required, and for pulsed applications where schottky ESR and capacitance dominate. (Schottky can indeed be worse for specific applications; have seem some snubbers that turned out that way.)Tim

author: mawyatt
author_rank: Super Contributor
timestamp: January 16, 2025, 04:27:09 pm
content: Former colleague sent me this about an IEEE Spectrum Article, he recalled what we did back in 80s to drive CCDs Clocks in our project called DDU.This was part of our Chirp Z Transform based handheld battery powered microwave Real Time Spectrum Analyzer. Interestingly this project had been attempted by Rockwell and Huges (both had in-house CCD capability, as did Honeywell) and failed, but we pulled it off and this put us on-the-map for future research projects!!The article references an on-chip “resonator” to recover the clock energy used by CMOS and references the “sinusoidal waveform”, same as we were doing back on DDU in early 80.https://spectrum.ieee.org/reversible-computingBest