Which JTAG inteface? (JLINK EDU, ARM-USB-OCD-H, other?) - Page 1
Forum section: electronics / general

author: hansan
author_rank: Newbie
timestamp: August 28, 2014, 08:40:25 pm
content: Dear all,I am looking for an cost effective and reasonable quality JTAG inteface for a debug project. I would like to debug a i.MX6 ARM Cortex-A9 (wandboard to be specific) with means of JTAG. My main operating system is linux, but that would be with OpenOCD and GDB not be a limitation for my purpose. Fancy windows software (IDE) are not needed / I can probably not use.But which Jtag hardware is recommendable for hobby work on a linux platform?I am mainly targeting ARM but other architectures should be nice to have as well. Voltage rage of the cores are 1.8V -- 5V. Price range <100 Euro.I am looking into the Segger J-Link EDU or the Olimex ARM-USB-OCD-H. Both are supposed to be well supported by openOCD. The non-commercial usages of the Segger is for now not a problem. I see on EBAY also a lot of U-link 2, which is as far as I know not so well supported by OpenOCD.My feeling/impression is that the Segger one is the better one because to the internal processor / hardware jtag support compared with the Olimex FT2232H based one. I am only afraid that this hardware jtag is not working with other architectures than with ARM. (with MIPS for instance) But I hope someone can comment on that.Has someone a recommendation for a JTAG specific hardware interface that is fairly good supported under Linux and works well?Greetings.

author: nctnico
author_rank: Super Contributor
timestamp: August 28, 2014, 10:53:21 pm
content: An LPT port based JTAG interface?

author: legacy
author_rank: Super Contributor
timestamp: August 28, 2014, 11:39:42 pm
content: Quote from: hansan on August 28, 2014, 08:40:25 pmwhy ?

author: tiltit
author_rank: Regular Contributor
timestamp: August 29, 2014, 11:39:05 am
content: I'm not sure if this helps but here is a picture from the guts of the Olimex ARM-USB-OCD-H.You may also want to consider the Bus Blaster from Dangerous prototypes.

author: legacy
author_rank: Super Contributor
timestamp: August 29, 2014, 03:07:36 pm
content: Quote from: tiltit on August 29, 2014, 11:39:05 amdoes anyone used this jtag ? it's in my wish list but i have no feedbacks about it

author: hansan
author_rank: Newbie
timestamp: August 31, 2014, 08:02:30 pm
content: Quote from: legacy on August 28, 2014, 11:39:42 pmAs far as I understand is basic JTAG (the standard) is just a bunch of shift registers and a state machine. However the usage of JTAG to do something with a processor is not that well standardized; I am afraid that a solution that works very well on one platform (ARM in this case) is not working that well on a different platform (MIPS) due to the additional logic in the JTAG interface probe. A parallel port interface or something based on a FTDI 2232 chip is more basic/low level, the higher level functionality (like setting breakpoints) is all done by the software on the host; which can work for any device.But maybe is my concern wrong. It would be nice to hear of someone that has experience with a Segger J-link on a not ARM platform. Is there someone?

author: hansan
author_rank: Newbie
timestamp: August 31, 2014, 08:06:19 pm
content: Quote from: nctnico on August 28, 2014, 10:53:21 pmI use the LPT port already for other interfaces. And I have read that the bit-banging on the LPT port is rather slow; good enough the flash firmware to save a bricked router, but not nice as debug tool. That is why I am primary looking for USB based solutions. However if you know or have good experience with a different tool then I am very much interested!

author: hansan
author_rank: Newbie
timestamp: August 31, 2014, 08:17:49 pm
content: Quote from: tiltit on August 29, 2014, 11:39:05 amThe inside of the ARM-USB-OCD-H looks rather good.The bus blaster is indeed a good suggestion; nice hardware concept, only a bit basic so without housing. I only have to look for a shop here in Europe.

author: legacy
author_rank: Super Contributor
timestamp: August 31, 2014, 08:27:42 pm
content: Quote from: hansan on August 31, 2014, 08:02:30 pmWhat you can do is specified with the BSDL file, i mean which registers and resources you can access inside the CPUQuote from: hansan on August 31, 2014, 08:02:30 pmWhile most of modern SOCs support JTAG (IEEE 1149.1), MIPS goes for "ejtag" which is aproprietary extensionwhich utilizes widely used IEEE JTAG pins for debug functions in order to provide a standard debug I/O interface, enabling the use of traditional MIPS debug facilities on system-on-a-chip components with new capabilities for software and system debug.EJTAG provides:- run control- single-step execution- breakpoints on both data and instructions- real-time trace (optional)- direct memory access- Debug Exception & Debug Mode (EJTAG-SPC-03-10)- Memory-Mapped EJTAG Registers (EJTAG-SPC-03-10)- Off-board EJTAG Memory (EJTAG-SPC-03-10)- Debug Breakpoint Instruction (EJTAG-SPC-03-10/SDBBP)- EJTAG Processor Core Extensions (EJTAG-SPC-03-10)- Hardware Breakpoint Unit (EJTAG-SPC-03-10)EJTAG utilizes a 5-pin interface defined in IEEE 1149.1. The basic Test Access Port (TAP) is composed by {TDI, TDO, TMS, TCK, nTRST}This is the common EJTAG pinoutCode:nTRST 1 2 GNDTDI 3 4 GNDTDO 5 6 GNDTMS 7 8 GNDTCK 9 10 GNDnSRST 11 12 -keyDINT 13 14 VCCYou can see additional pins:* DINT pin is used to raise Debug Interrupt. Many chips has no this pin.* nSRST pin is a "system reset" signal and acts like conventional "Reset' button (1)(1) While nTRST is the "TAP Reset" signal, the nSRST signal does not reset TAP controller, often it resets the SoC peripheralsDebug Exception and Debug ModeTo allow inspection of the CPU state at any time in the execution flow, a debug exception with priority over all other exceptions is introduced. When a debug exception occurs, the CPU goes intoDebug Mode, a special mode with no restrictions on access to coprocessors, memory areas, etc., and where usual exceptions like address error and interrupt are masked. Thedebug exception handleris executed inDebug Modeand provided by the debug system. It can be executed from the probe through a processor access, or may also reside in the application code if the developer chooses to use a debug task in the application. An overall requirement is that debugging be non-intrusive to the application so execution of the application can be continued after the needed debug operations. However, loss of real-time operation is inevitable when the debug exception handler is executed. The system designer may chose to indicate debug mode by a signal to certain hardware modules to freeze them when executing the debug exception handler.Memory-Mapped EJTAG RegistersEJTAG provide memory-mapped registers, located in the debug register segment (drseg), which is a sub-segment of the debug segment (dseg). They are accessible by the debug software when the processor is executing in Debug Mode. These registers provide both miscellaneous debug control and control of hardware breakpointsOff-board EJTAG MemoryEJTAG allows a MIPS processor in Debug Mode to reference instructions or data that are not resident on the system under test. This EJTAG memory is mapped to the processor as if it were virtual memory in the kseg3 segment, and references to it are converted into transactions on the TAP interface. Both instructions and data can be accessed in EJTAG memory, which allows debugging of systems without requiring the presence of a ROM monitor or debugger scratchpad RAM. It also provides a communications channel between debug software executing on the processor and an external debugging agent.HW specific: the EJTAG probe polls the EJTAG Control Register through the TAP, and a bit in this register indicates when a processor access is pending. The physical address of the transaction is then available in the EJTAG Address Register, and the transaction size and read/write indication are available in the EJTAG Control Register. The EJTAG Data Register is then accessed either to get data from a write or to provide data for a read. Finally the EJTAG Control Register is updated to indicate that the processor access is done.Debug Breakpoint InstructionCPU-Specific: EJTAG introduces a new breakpoint instruction,SDBBP, which differs from the MIPS32 and MIPS64 BREAKHardware BreakpointsEJTAG defines various types of hardware breakpoints for interrupting the CPU at certain transactions on the CPU buses. The debug exception happens before the bus transaction causing the exception alters any memory or CPU state. Hardware breaks on instructions have the advantage over software debug breaks in that it is possible to set them in any address area. Furthermore, if memory cannot be altered by inserting SDBBP codes, the hardware breaks can still be used. Hardware data breakpoints allow breaks on load/store operations.EJTAG implements two kinds of breaks:-Instruction breaks, in which a break may be set on an instruction fetch from a specific virtual address-Data breaks, inwhichabreakmaybesetonaload/storereferencefromaspecificvirtualaddress,whichadditionally can be qualified by a data value.There may be up to 15 break channels of each type implemented, and each break channel may be programmed with address, address mask, ASID, and reference type.EJTAG Processor Core ExtensionsA MIPS processor or core supporting EJTAG must support EJTAG-specific instructions, additional system coprocessor (CP0) registers and vectoring to Debug Exceptions, which puts the processor in a special Debug Mode of execution.

author: legacy
author_rank: Super Contributor
timestamp: August 31, 2014, 08:38:17 pm
content: In short, you could use awiggle clone(parallel port jtag cable) for MIPS, too!You have to use a software which is aligned with the EJTAG capabilities, more specifically you need- the correct BSDL file- Debug Exception & Debug Mode support

author: janoc
author_rank: Super Contributor
timestamp: August 31, 2014, 09:08:20 pm
content: Please, guys, everyone suggesting parallel port interfaces, let them die in peace! Those things are simple and cheap, but a royal PITA to use, especially in Windows, not to mention the chances of frying your motherboard should something go haywire. Moreover, dongles that bitbang JTAG are extremely slow for debugging (be it USB or parallel port based). You really really want something that has the JTAG implemented either in a microcontroller or at least a FT2232H.There are plenty of good USB JTAG dongles - I have the Chinese OpenJTAG and the Dangerous Prototypes BusBlaster, the latter can be even re-programmed to emulate various other dongles (uses CPLD for the frontend). Both work fine.

author: legacy
author_rank: Super Contributor
timestamp: August 31, 2014, 09:23:03 pm
content: Quote from: janoc on August 31, 2014, 09:08:20 pmThe problem with MIPS is related to the software side, i mean commercial debuggers are targeting for expensive EJTAG unit, for example the cheapest cable supported by OCD is thewiggle, which is parallel port.We can go for OpenOCD but i do not know how good is the support for EJTAG: never tried.Quote from: janoc on August 31, 2014, 09:08:20 pmDangerous Prototypes also sells FT2232H-breakout, BusBlaster adds a little CPLD, the breakout is missing. I have used their FT2232H-breakout in order to interface my blackfin BF537-stamp board with open sources tools (openOCD and gdb), unfortunately AnalogDevices VisualDSP++ is not supporting FT2232H, so to use such a software i have bought a dedicated (and expensive, $200) usb-cable (called "adzs-ice-100b") targeted for blackfin BF5xx.An example that can clarify the "software traps" is this:AnalogDevices is also not supporting gnICE by their VisualDSP++. gnICE is a low cost usb-jtag cable with low performance ADI compatible designed according to Analog Devices' application note EE-68; i have writtenheresomething about it, and may be interesting to know that it is based on FT2232 so you can save you money (gnICE is sold at 150USD or more) building it by yourself with a FT2232 breakout.

author: nctnico
author_rank: Super Contributor
timestamp: September 01, 2014, 10:59:35 am
content: Quote from: legacy on August 31, 2014, 09:23:03 pmOpenOCD works well with EJTAG. I revised most parts of it years ago.

author: andersm
author_rank: Super Contributor
timestamp: September 01, 2014, 11:44:32 am
content: Quote from: hansan on August 28, 2014, 08:40:25 pmOne thing to keep in mind is that AFAIK the J-Link EDU is still on hardware revision 8, which will limit its lifespan if you want to use Segger's tools. PIC32 support for instance is only available on r9 and newer hardware.QuoteThose are almost all clones, which means they'll have compatibility problems with Keil's tools.

author: ElektroQuark
author_rank: Unknown
timestamp: September 01, 2014, 12:43:51 pm
content: Quote from: andersm onTodayat 10:44:32 PM

author: JDubU
author_rank: Frequent Contributor
timestamp: September 01, 2014, 05:57:15 pm
content: Quote from: andersm on September 01, 2014, 11:44:32 amWhere did you see that limitation?From what I can see from the Segger web site, J-Link EDU version 8 hardware should work with the latest firmware update.

author: andersm
author_rank: Super Contributor
timestamp: September 01, 2014, 06:02:10 pm
content: Quote from: JDubU on September 01, 2014, 05:57:15 pmAthread on their forum.

author: JDubU
author_rank: Frequent Contributor
timestamp: September 01, 2014, 06:12:15 pm
content: Quote from: andersm on September 01, 2014, 06:02:10 pmThanks!

author: andersm
author_rank: Super Contributor
timestamp: September 01, 2014, 06:39:08 pm
content: Speaking of Microchip and J-Link, they're currently having a$75 off sale. You can also save $100 on a RealICE.

author: abyrvalg
author_rank: Frequent Contributor
timestamp: September 02, 2014, 08:22:02 pm
content: AFAIK OpenOCD doesn't use J-Link's builtin high level functionality like "set breakpoint" etc, it uses lower level scan chain access APIs, so there will be no advantage over FT2232H-based interfaces in this mode, no reason to pay more.