JLCPCB smallest possible label and text font size - Page 1
Forum section: electronics / general

author: Krotow
author_rank: Regular Contributor
timestamp: November 03, 2024, 11:57:25 pm
content: Did somebody recently tried to order PCBs with label and text size below 1mm in JLCPCB? Which text size is smallest that they reluctantly accept and which is still distinguishable? I'm asking because minimum text size/height in JLCPCB is 1mm, but I would like to make label text 0.75mm high due to space constraints.

author: tooki
author_rank: Super Contributor
timestamp: November 04, 2024, 12:42:56 am
content: Even 1mm text often comes out illegible, depending on the font. The silkscreen on low-volume [edit:2-layer] PCBs at JLCPCB is often done with UV inkjet*, and the resolution isn’t that high, I suspect under 300dpi. I don’t think 0.75mm text height stands a snowball’s chance in hell of being legible. Even on a high-res true silkscreen that would be asking a lot.If you can, make your label on the copper layer. The resolution of the copper layers is far higher than of the silkscreen layer. If you can’t do that, can you do it on the solder mask layer? That’s still better resolution than the silkscreen layer.*inkjet printer using UV-cured lacquer/resin inks

author: scottapotamas
author_rank: Regular Contributor
timestamp: November 04, 2024, 01:17:33 am
content: I've been reliably using 0.8mm high, 0.8mm wide characters with JLC >=4 layer processes without legibility issues. The rare time I've used 2L processes has shown lower fidelity.I typically aim for 0.15mm linewidth for non-text geometry (markings or other callouts) and it's generally fine but can sometimes show minor inconsistencies for short lengths.

author: Krotow
author_rank: Regular Contributor
timestamp: November 04, 2024, 09:43:53 am
content: Seems I should put some smaller text somewhere on PCB and see what will happen

author: Kean
author_rank: Unknown
timestamp: November 04, 2024, 09:48:30 am
content: I regularly use 0.8mm high silkscreen designator, and using 8% ratio (height to line thickness), but that is really a bit low. Like scottapotamas these are mostly 4 layer designs which generally JLC build with better quality silkscreening. So I maybe would not recommend going to 0.8mm on their low cost 2 layer process if the text must be legible. I've probably done it, so I could dig around to see if I have any samples to check for quality.Because the 8% ratio that I've been using is so low, I strongly suspect that the PCB houses increase the line thickness to meet their requirements. It hasn't occurred to me how thin that actually is, and the end result has generally been quite readable to me. On reviewing some of the production PCBs from our CM (who isn't using JLC), I can see the silkscreen text is a slightly lighter weight but still readable. Again, I suspect they have standard automated process with rules to adjust these. They've never highlighted it to me.If I want the text to stand out but still be small (e.g. a connector or button label), I've increased the ratio from 8% to 15% - but unlike the CAD view on the PC screen, I cannot actually see much difference between them on the actual PCBs when using 0.8mm high text. It is noticeable with larger text.

author: tooki
author_rank: Super Contributor
timestamp: November 04, 2024, 10:44:38 am
content: Quote from: scottapotamas on November 04, 2024, 01:17:33 amGood point: all the PCBs I’ve had made at JLC were 2-layer.We know the 4+ layer process is more precise, so it doesn’t surprise me whatsoever that it has better silkscreen, too!

author: Kean
author_rank: Unknown
timestamp: November 04, 2024, 10:57:17 am
content: I thought of a proto PCB I threw together with JLC 2 layer proto service, and checked and it does have 0.8mm high text.The text "SJ1" and "Q1=SOT23", and "Q2=SC70/SOT323" is 0.8mmOther text like the part designators, "NTC", "FET/BJT", etc is 1.0mm, and "SOURCE" at the top is 1.27mm.

author: Ice-Tea
author_rank: Super Contributor
timestamp: November 04, 2024, 11:11:33 am
content: The opinion no-one asked for: create an additional layer in your design for ref des (except for connectors). Put the ref des in the centre of the component. Include a pdf with this layer in the documentation and/or schematic.Much cleaner board, room to put actually important stuff and text on the board, uniquivocal component indicators.

author: Uky
author_rank: Regular Contributor
timestamp: November 04, 2024, 03:22:45 pm
content: Another opinion no-one asked for from a Cadence user.Maybe this method can be applied in other systems as well.(OrCAD features a separate REF layer "ASSY" intended for documentation whichdoes not get included in the silk screen but is used in Assembly drawings togetherwith cross section and dimension information.)There is a a separate board geometry layerwhere arbitrary silk texts can be created like board name, revision, connectordescriptions etc.OrCAD does also offer the possibilityto create new sub-classes. Eg. "SILK_HIDDEN" or any arbitrary chosensub class on the REF class layer.Then simply select those reference designators that does not need to be seenon the silk screen (like small SMD components in cramped areas)and move the REF designator to the hidden layer, which can beomitted during gerber generation. Thus it is possible to retainimportant reference designators visible and leave out others.

author: DavidAlfa
author_rank: Super Contributor
timestamp: November 04, 2024, 04:16:21 pm
content: Silkscreen quality varies vastly depending on the fab.The white pcb is using 0402 resistors, so the text is really small, yet it looks great, while it's blurry in the blue pcb.

author: Smokey
author_rank: Super Contributor
timestamp: November 04, 2024, 06:11:30 pm
content: I use 40mil height, 4mil line refdes for 0402 parts and it always comes out fine now. Haven't had problems with that silk size in years.Standard White silk on green mask.

author: Krotow
author_rank: Regular Contributor
timestamp: November 04, 2024, 11:19:35 pm
content: Seems it is at least worth to try small print in not critical areas while board is still in prototype stage. I will try 0.8 mm then.

author: scottapotamas
author_rank: Regular Contributor
timestamp: November 05, 2024, 01:14:46 am
content: Quote from: Uky on November 04, 2024, 03:22:45 pmI can't remember how much of this is the EDA tools or my IPC adherence for parts libraries, but that's pretty typical?Altium has a specific layer pair for the designator to provide more control for draftsman/other exports.KiCAD has it's front and rear Fab layers which serve this purpose.It's possibly slightly off-topic, but for people using KiCAD theinteractive bom pluginis highly recommended even if you're not hiding designators.

author: Krotow
author_rank: Regular Contributor
timestamp: November 14, 2024, 04:38:17 pm
content: For KiCad users Interactive BOM plugin is God's gift. Proven as helper for a person who assemble the PCB and for repairs later. I use it quite often.

author: Kasper
author_rank: Frequent Contributor
timestamp: November 15, 2024, 01:24:32 am
content: Earlier this year, 0.6mm high, 0.15mm thick on 4 layer from JLC. Looks good to me.

author: westfw
author_rank: Super Contributor
timestamp: November 22, 2024, 09:39:18 am
content: What about other vendors?FWIW, a recent board I had made at OSHPark has VERY clear 1mm text (using EAGLEv7's vector fonts.)

author: Infraviolet
author_rank: Super Contributor
timestamp: November 25, 2024, 10:14:12 pm
content: The important thing is to make sure the thinnest line in your text is thick enough (if I remember rightly with JLC that is 0.1mm). Beyond that, however small your text it will be somewhat printed, though the spaces between the lines of the text (like the gaps inside a B) would eventually shrink to nothing. I regularly do 0.9mm height text with a vector font and "20%" thickness ratio, this prints nicely with JLC's 2 layer process (atleast for white text on green/red/blue boards, might be different for black text on white boards). I find it readable enough for the purpose I use it for (text beside components as a quick way to know when soldering the parts on what goes where, easier than checking against a magnified picture of the board's design files on a PC screen every time).

author: phil from seattle
author_rank: Super Contributor
timestamp: November 27, 2024, 12:51:22 am
content: Given how cheap it is to make bare boards at JLC, I usually spin off a quick test board when I have questions like that. Often, I keep an open test board project and add things I want to test. Eventually I push a test run. $20 and a few days later, I know the answer(s). Cheap piece of mind.That said, with JLCPCB, 1mm is about as low as I typically go on 2L boards. Their quality is variable - sometimes great, sometimes barely legible.

author: Krotow
author_rank: Regular Contributor
timestamp: November 30, 2024, 01:40:25 pm
content: Quote from: Kasper on November 15, 2024, 01:24:32 amLooks good for me too. I now have four 4-layer boards in progress. Order I mentioned earlier got cancelled due to last minute changes by a customer, causing complete board redesign. Though while he pay for that, I'm not complaining.Quote from: phil from seattle on November 27, 2024, 12:51:22 amYep, I'm in process to f--k around and find out are component labels still readable at so small sizes.Another problem - due to mentioned space constraints I now want to change a third of resistors and capacitors to 0402 size and move them closer. That will not left the space for labels at some board areas. How you guys are managing this? Do you make illustrative "label blocks" in free board areas like some motherboard makers do? Or simply omit labels at all?

author: Kean
author_rank: Unknown
timestamp: November 30, 2024, 02:07:38 pm
content: Quote from: Krotow on November 30, 2024, 01:40:25 pmYes, omit them altogether but have a usable assembly drawing. See replies 7 & 8 above.

author: Krotow
author_rank: Regular Contributor
timestamp: February 09, 2025, 01:40:09 am
content: To conclude the topic. Due to other tasks returned to mentioned project at mid-January. Decided to put 0.6mm text on 4 and 6 layer boards. As turned out, JLCPCB deal with this text size just fine - see attached pictures. I can clearly see label text without glasses and zoomed text is not badly jagged. So it seems that 0.6mm in small space constrained boards is a way to go.Nevertheless it seems that future versions of these boards may have even more components so most labels will disappear completely. Luckily KiCad Interactive HTML BOM plugin already matured enough to turn into practical cross-platform HTML boardview generator with real trace and rat nest displaying by selecting them with mouse cursor and pretty good net/component searching.

author: Kasper
author_rank: Frequent Contributor
timestamp: February 12, 2025, 03:27:04 am
content: Good to hear it turned out!Here is one of my assembly drawings for when silkscreen just won't fit. In circuit studio (altium), I export assembly drawings which makes a pdf. In it I put 3 layers for each side: assembly top, assembly text top, PCB outline.

author: Krotow
author_rank: Regular Contributor
timestamp: February 14, 2025, 01:14:12 am
content: Yes, I'm also moving to that kind of layout due to necessity

author: asmi
author_rank: Super Contributor
timestamp: February 14, 2025, 04:41:10 pm
content: This is what 0.7 mm/0.15 mm stroke width labels look like on a 10 layer PCB made by JLCPCB - attached are bare PCB of the first revision and assembled version of the second one just to see if soldermask color affects readability. To me they both are perfectly readable.