Data Traces Between Plane and Split Plane - Page 1
Forum section: electronics / general

author: Kasper
author_rank: Frequent Contributor
timestamp: June 03, 2021, 06:05:33 pm
content: A question about routing data traces for example SPI or I2C over splits in planes.For example:Layer 2 = solid GNDLayer 3 = SPI and I2CLayer 4 = split planes for multiple power suppliesNormally I avoid routing data over splits in its reference plane but I wonder if it matters in this example. There is a solid GND on 1 side of the data traces, can I ignore the splits in the plane on the other side of the data traces? I am guessing it somewhat depends on which plane is closer, worst case being the GND plane is further than the split power plane but even in that case, I'm guessing it is fine. What do you think? Is this something I should worry about?

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: June 07, 2021, 03:35:14 pm
content: For I2C or SPI it probably won't matter. Depending on the speed of your clock you should look at the 5th harmonic's 1/10 wavelength and see if your routing is on the same order of magnitude. If you wanted to be safe though you should route those signals on layer 1, that would ensure a good return path and impedance reference.As a general rule using your power planes as an impedance reference / return path is ok as long as they are properly bypassed with caps.You may be able to adjust your stack up to better arrange your signals and return paths.Is your board 4 layers, 6 layers, or even 8 layers? Perhaps more?6 layer boards are usually pretty non-ideal if you are using 4 layers for routing. You'll find that higher layer count designs are usually the result of trying to isolate high speed signals with many ground planes.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 07, 2021, 05:31:15 pm
content: I take it this is a 6-layer board with signals on layers 1 and 6, and another plane on 5..?Or if 4 then why signals on 3, you seem to have them swapped around?Tim

author: Feynman
author_rank: Regular Contributor
timestamp: June 07, 2021, 05:44:13 pm
content: Impossible to tell, with that amount of information. Does the circuit "just" have work or do you need to pass EMC tests?Just a few ideas:- I wouldn't be too concerned about the split, since the signals have a solid GND plane as reference (assuming the signals are launched between the signal line and GND with no return path discontinuities somewhere else). It's always better to have the signals closer to GND than to the power planes, of course.- It's almost always a good idea too slow down the digital edges as much as possible. Just don't forget about the I2C falling edges.- What's on layer 5? If layer 5 isn't a ground plane, a significant amount of the circuit's power supply energy is stored between Layer 2 and 4. Just where the digital signals happen to be. So you might see power supply noise on your signals, or signal noise on your power supply.As I said, it's hard to tell. The circuit could work perfectly well, even in a EMC test or exactly the oppositeBut I would be more concerned about the signals being in the space where the power comes from than about the split in the plane.

author: David Hess
author_rank: Super Contributor
timestamp: June 08, 2021, 01:24:33 am
content: Track the return currents for each driver state. When the driver pulls down, the return current is through the ground plane which is ideal. When the driver pulls up, the return current cannot cross the split power planes, so it travels though the nearest decoupling capacitor and then through the ground plane. I2C has no driven pull-up which helps but the passive pull-up should be decoupled to ground, just like any of the drivers.