Open source FPGA + DDR Memory 50mmx50mm PCB - Page 1
Forum section: electronics / general

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 19, 2022, 12:00:54 pm
content: Hi,As you may have seen JLCPCB has a limited 2$ 50mmx50mm 8 layer PCB offer, and I have designed several PCB's for Xilinx parts, But unfortunately all of them are way bigger than 50mmx50mm, So I wonder if members in here have an open source smaller designs with Just the FPGA and DDR memory on a 50mmx50mm,so we can take advantage of this great offer.

author: asmi
author_rank: Super Contributor
timestamp: December 19, 2022, 05:58:51 pm
content: Considering that even relatively small 484 ball package will take up a quarter of such board, I don't think you can really design a useful devboard that small. You can design a module with such dimensions, but it will likely require 10 or even 12 layers because otherwise the layout will be super tight and you will quickly run out of routing layers. That said, you are free to try

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 19, 2022, 07:20:46 pm
content: Yeah. Xilinx parts are not really small enough for this.You could probably design a board with a Lattice ECP5 and a DDR3 chip on that area, it's available in a 285 csfBGA (10 x 10 mm). One forum user designed an open-source DDR3 controller and some of us were willing to port it/test it on the ECP5, that could be an occasion.

author: DavidAlfa
author_rank: Super Contributor
timestamp: December 19, 2022, 08:26:14 pm
content: Yay! lets make some crazy 8-layer sh*It would be tight but you probably could compress a whole SBC in 50x50mm!

author: Someone
author_rank: Super Contributor
timestamp: December 19, 2022, 09:06:51 pm
content: It can be done:http://www.sioi.com.au/download/FS60X-DataSheet.pdfBut the motivation here is stupid, why save a few dollars on the PCB manufacture (adding time and size pressure) when the time spent to design/assemble/document the items (before parts costs) are going to be orders of magnitude higher?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 19, 2022, 09:29:40 pm
content: Thanks for the feedbacks, But any FPGA or advance Board with DDR, like ARM SOC's also would do the job, since 2$ is so compeling! it's cheaper than a sandwich

author: asmi
author_rank: Super Contributor
timestamp: December 19, 2022, 10:00:13 pm
content: Quote from: ali_asadzadeh on December 19, 2022, 09:29:40 pmIt's compelling only to those who don't value their time. Designing such board is going to take at least a few weeks, and chances are your first revision is going to be a bust unless you have extensive prior experience with these devices. So you're saving maybe like $100 from the total of $10k+ which is what it would cost to design such a board and make a couple of prototypes to confirm that it actually works.Not to mention with parts becoming unobtanium without any notice whatever design you come up with will be very short-lived unless you do a lifetime-buy of entire BOM for however many boards you plan to make right from the get-go, which is going to be a lot of money tied up in the inventory. Making open hardware designs nowadays is rather pointless for this reason, because chances that someone else will be able to source those exact parts in a year from now are quite slim, and redesinging such tight boards for new parts which one could manage to source is going to be a big headache. So the only value of such designs right now is purely academic - so that others can see how you did this and that aspect of design, and learn from that.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 19, 2022, 10:46:36 pm
content: Agreed.

author: BrianHG
author_rank: Super Contributor
timestamp: December 19, 2022, 10:51:03 pm
content: A 4 layer with the Lattice ECP5 is possible, but I recommend at least 6 layers.Remember, the Lattice max is a 400MHz, 800MTPS DDR3 controller. Except for the differential clock and DQS, trace length matching for such a DDR3 controller isn't too critical compared to a 1.8GTPS DDR3 controller especially when using multiple DDR3 ram chips. IE: when I say multiple, I mean 2-4 chips making a 64bit DQ buss.The truth is if you are wiring a single DDR3 ram chip or wisely laying out 2 of them, at 800 MTPS, you can easily get away with +/- ~2mm trace lengths on the DQ bus and +/-4mm on the CMD lines except for the length between the differential clock pairs.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 19, 2022, 10:53:46 pm
content: Yes and the OP said the offer was for 8-layer PCBs. So that's largely doable.

author: BrianHG
author_rank: Super Contributor
timestamp: December 19, 2022, 11:03:44 pm
content: Quote from: asmi on December 19, 2022, 10:00:13 pmYes, you should only be doing this as a personal learning experience and remember, an error free first run PCB is an exceptional case. Expect to through out your first PCB.Also, for my first FPGA DDR2 design, I used laptop SODIMM modules instead of mounting the ram directly on the PCB. This way, I can probe and correct code and trace errors. You will have no such luck if you mount your DDR3 directly on the PCB.50x50mm isn't going to cut it unless you exactly know what you are doing...(Yes it is doable, but you better have experience with such compressed and dense circuits)100mmx50mm would have been perfect...

author: strahd_von_zarovich
author_rank: Contributor
timestamp: December 20, 2022, 06:50:53 am
content: If you use 2 DDR RAM IC's on top and bottom, there is enough space to fit them all.Here is a picture of my design with 4 DDR3L ICs with FFG676 Kintex-7 FPGA. I used 16 layers, but I think you can make it on 8 layers If you use less ram ICs since they are the real reason why I use more layers. I am pretty sure I can fit Gbit ethernet, USB, couple of connectors and power section on that space but it is easier said than doneBy the way I paid 23 USD per PCB for 16 layers which has gold plating, via-in-pad, impedance matching, special dielectric material. So, cost of the PCB is not most important thing in designing FPGA boards

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 20, 2022, 09:08:22 am
content: QuoteWe can do it! This mindest is like saying no one can send a rocket to sapce and thenland it safly to earth to save costs , till some one do it.QuoteWow, that's super cheap, in what QTY and where? it's very interesting.

author: asmi
author_rank: Super Contributor
timestamp: December 20, 2022, 03:23:56 pm
content: Quote from: ali_asadzadeh on December 20, 2022, 09:08:22 amReally? Rockets are launched when there is a sale on a chewing gum?Like I said, you are free to prove us all wrong and design and make such a board. We're merely pointing out that the effort to actually design such a board is so significant that PCB manufacturing cost is almost irrelevant. When I spend 3 weeks designing a PCB, I don't really care if it's going to cost $2, $20 or $200 to manufacture, because to me it's already worth more that any of these numbers.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 20, 2022, 09:05:50 pm
content: Quote from: asmi on December 20, 2022, 03:23:56 pmCertainly, that's something, although obvious, that seems often overlooked. I guess it is mostly overlooked by people who are employees, or at least have an "employee" mindset, and don't count their time as an expense (but their boss does!) Weirdly enough, I think the OP is a freelancer or has a small business, so he should know.But still interesting to see how so many people value their time less than they value money.The same thing happens about those few-cents MCUs, for which people may waste hours, days or weeks, sometimes for a whole team, compared to using a slightly more expensive and better supported chip. Factor in the extra time and see how many products you'd need to sell to barely make it even.Anyway. Not only people's time has value, but contrary to money, any spent time will never be regained. Oh well.

author: asmi
author_rank: Super Contributor
timestamp: December 20, 2022, 10:11:38 pm
content: Quote from: SiliconWizard on December 20, 2022, 09:05:50 pmThere is nothing wrong in messing around with parts for fun, but it's important to be under no illusions that all of that work is free.

author: DavidAlfa
author_rank: Super Contributor
timestamp: December 20, 2022, 10:34:20 pm
content: Sure, stm32, pics, these never have weird sometimes erratas requiring weeks of debugging.I still remember a buggy spi interface in a PIC24 10 years ago, no errata for it but under certain circumstances very weird things happened.Of could it could have been my fault, I'll never know, in the end we just disabled and enabled the module after each frame.

author: strahd_von_zarovich
author_rank: Contributor
timestamp: December 21, 2022, 08:33:05 am
content: Well, I got 4 PCBs produced. Of course I didn't mention about the tooling cost which is 612 USD. However, every PCB cost 23USD.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 21, 2022, 03:42:33 pm
content: I agree with you that the design cost is much more than 2$, But at first post I said Open source project and we have a limited time offer, so that means an already done project which happen to be open source.I have a 50mm X 50mm 4 layer design with MIMXRT1052DVL6A part, It has a SDRAM, Ethernet PHY, Audio Codec,SD Card etc… if more than 5 people are interested I make it open (It’s in Altium), so you can take this offer, test and debug the board at your own risk!Just post I’m interested in your design, so I can count the number of people.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 21, 2022, 07:33:02 pm
content: Well as I said, designing a 50x50mm board (or even smaller) with a Lattice ECP5 and DDR3 RAM is definitely possible. There are some such boards that have been designed in feather form factor (so smaller than this) and fewer than 8 layers for sure. For Xilinx parts I don't see it as practical though, although maybe not impossible.https://github.com/orangecrab-fpga/orangecrab-hardware22.86mm x 50.8mm

author: asmi
author_rank: Super Contributor
timestamp: December 21, 2022, 07:59:24 pm
content: Quote from: SiliconWizard on December 21, 2022, 07:33:02 pm0.15 mm drills, 0.89 mm traces and 0.5 mm pitch package. Good luck getting it manufactured at JLCPCB for any price, let alone for $2

author: asmi
author_rank: Super Contributor
timestamp: December 21, 2022, 08:07:06 pm
content: Quote from: ali_asadzadeh on December 21, 2022, 03:42:33 pmWhat's the point in manufacturing something you don't actually need? You don't have enough junk PCBs collecting dust? I certainly have plenty of that.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 21, 2022, 08:19:47 pm
content: Quote from: asmi on December 21, 2022, 07:59:24 pmhttps://jlcpcb.com/capabilities/CapabilitiesFor >= 4 layers, min via hole is 0.2mm and min trace width is 0.09mm. (I guess you meant 0.089mm traces? 0.89mm is huge.) So that's not all that far away.But it was just as an example, this board is half the area. I posted it as an example, I didn't say that the OP should just send it as is to fabrication. He wants to design something.With 50mmx50mm, 8 layers and if necessary, a slightly larger package for the ECP5, going with JLCPCB should be no problem.

author: asmi
author_rank: Super Contributor
timestamp: December 21, 2022, 08:41:05 pm
content: Quote from: SiliconWizard on December 21, 2022, 08:19:47 pmWhat about 0.15 mm drills?Quote from: SiliconWizard on December 21, 2022, 08:19:47 pm0.8 mm pitch packages are much larger. And I still don't see utility of such board - it's got literally nothing, and you can't connect anything useful to it because it lacks high-speed connectors.Look, I designed a fair share of "compute modules" which are about the size we're discussing here, so I have a fairly good idea of what you can and can not fit on such area, doing a layout of such boards is an extremely hard and tedious job even if you aren't limited to 8 layers (most of such modules' PCBs are 10 or 12 layers anyway) - there is simply not enough space, and you often route yourself into a corner and have to tear down routing to try again. For modules this is typically not a problem because you normally only place a limited set of most critical components on the module itself - flash memory for bitstream, DDR, power delivery components and a heatsink/cooling fan with associated control circuitry, everything else goes out through the high-speed connectors on the bottom of the board and then is routed on a typically much larger, but cheaper due to lower layers count, base board. For full-up devboard though - heck, just look at how much PCB space is occupied by a simple Ethernet connector!