How does this shift register work? - Page 1
Forum section: electronics / projects

author: robertbaruch
author_rank: Regular Contributor
timestamp: July 18, 2016, 03:15:55 am
content: I have an old calculator from the 60s made of DTL NAND gates along with DTL gates made of components. I've been reverse-engineering it, but I found thatsomeone's already done a similar, later calculatorand it shares many circuits with mine.The thing that I can't wrap my head around is this shift register.I understand that each of the NAND pairs forms an SR flip-flop, and that the inputs are -S and -R, and the outputs are Q and -Q. This explains the crossover between each stage. What I can't understand is how the capacitors work with the n0SO signal to act as a clock. Note that this is just the name in this schematic. The circuit board trace says "CP" next to that signal, so I'm assuming that's "Clock Pulse".Consider that last pair, IC108. Assume that the top output is Q, and it's at logic 1. Let's also assume that the inputs, -S at pin 2 and -R at pin 4 are at 0 and 1 so that the flip-flop is forced to be set. Now, suppose the Q output of the previous stage (IC107 pin 3) goes to 0 (and -Q goes to 1). It looks to me as though the n0SO signal does absolutely nothing. -Q from the previous stage goes to 1, which charges the capacitor until pin 2 of IC108 reaches its threshold, and Q from the previous stage goes to 0, discharging the other capacitor until pin 4 reaches its threshold. Now the last stage's -S and -R inputs are at 1 and 0, which resets the flip flop.How does n0SO have any affect on the circuit?For extra info, here's the circuitry inside the NAND gates:

author: David Hess
author_rank: Super Contributor
timestamp: July 18, 2016, 04:41:32 am
content: The outputs of the previous stage precharge the 47 and 68 picofarad input capacitors so when shift (n0SO) is strobed, the data is transferred to the following stage. nLDSDK functions as a parallel load function but it can only set or reset each stage.

author: helius
author_rank: Super Contributor
timestamp: July 18, 2016, 05:20:26 am
content: In schematics "Ø" usually means "clock phase" (from the Greek letter ? or phi) and not zero.

author: robertbaruch
author_rank: Regular Contributor
timestamp: July 19, 2016, 02:15:32 am
content: Ah, I wasn't taking the input resistance of the gate into account. That's the key. Even if the output of the previous stage were 0V, the input on the next stage couldn't get below about 3.6v because the 22k resistor is large compared to the input resistance. That's not enough to register as a 0 to the gate.Assume the clock remains high, then the capacitor is charged to 3.6 - 5 = -1.6v (with respect to the clock line). As soon as the clock goes low, -1.6v appears on the input to the gate, which triggers it. Then when the clock goes high, the input again goes to 1.A 1 output from the previous stage appears as 5v on the input, so the capacitor is charged to 0v. Again, when the clock goes low, 0v appears on the input to the gate, which triggers it also. That's not good.BUT! Since it appears they were playing threshold level games, I figured that the clock pulse couldn't be a 0-5v signal. And sure enough, looking at the diagram, I found that the clock pulse is the output of a gate, with a 560 ohm resistor to ground. With the output resistance, paralleled with the input resistance because the clock pulse comes from a flip-flop, a logic 1 appears as 0.9v or so.Now if the clock remains high, a 1 output results in the capacitor charged to 3.6 - 0.9 = 2.7v. As soon as the clock goes low, 2.7v appears on the input to the gate, which does not trigger it.I feel sure that this is the right mechanism, I just have to find the voltages that make the thresholds work out. I think I'll power up mine and just measure the voltages.

author: robertbaruch
author_rank: Regular Contributor
timestamp: July 19, 2016, 02:42:14 am
content: Yes, measurement showed that in fact the gate output is 1.8 when low, which is above the threshold. The clock gives a 1v transient, so that's enough to knock the signal below the threshold, but not enough to knock a 5v high signal below the threshold. Now I understand how this thing works. Threshold games!