SoftCore debug - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: July 29, 2014, 09:19:51 pm
content: hi guysi have seen that the ZPU has a jtag tap machine in its RTL level (1), so guys are trying to attach a second jtag in order to debug the firmware (the primary jtag is used to download the fpga bitstream), that's cool !i guess, what about putting a tiny debug-processor inside the SoC, instead ?Assuming you have enough resources to put two soft core inside your fpga(2)the debug processor should be so cool because it can- stop the Main Softcore's clock, at a particular PC, or at breakpoints- access (reading/writing) the Main Softcore's registers (also to PC, EPC, cause, cop0 and whatever …)- access (reading/writing) the Main Softcore's local bus (so r/w its iram/dram)the idea is to put gdb-stub inside the tiny Debug Processor (which is validated, so you can trust it), and let it to (uart-serially-)-talk gdb-uart-protocol with the host in order to control the target !in this ways you put much more intelligence in the debug module, which could simplify things like … attaching the host in order to control thingswith a gdb-debug-processor the host could simply send commands (high level commands, also in pretty ASCII form) and gets replies instead ofhardly handling all the signals of a jtag tap machines (which also requires … a special file, BSDL file, that describe the target from the point ofview of the TAP machine)what do you think ?anything around ?(2) for example, a smaller debug-processor-Softcore made with the Xilinx PicoBlaze, which is very essential and tinyedit: repo's link added(1) from theZPU repo, seezpu.hdl.tap(vhdl source), it looks very interesting!

author: mrflibble
author_rank: Super Contributor
timestamp: July 29, 2014, 11:08:48 pm
content: Personally I'm more partial to using chipscope, and sometimes a small FSM to keep track of things and generate triggers for the chipscope ILA.But maybe your picoblaze-as-debugger has some use too, when a simple ILA or ILA+FSM doesn't cut it. One thing to beware though, is that before you know it you are debugging the debugger.

author: legacy
author_rank: Super Contributor
timestamp: July 30, 2014, 10:52:06 am
content: Quote from: mrflibble on July 29, 2014, 11:08:48 pmit the only one dogma: do not debug the debugger

author: legacy
author_rank: Super Contributor
timestamp: August 03, 2014, 11:33:29 am
content: Quote from: mrflibble on July 29, 2014, 11:08:48 pmi have bought an Avnet FPGA board equipped with Spartan6, it also comes with a "locked license" version of Xilinx ISE v14.7 (2 DVD provided, one of these is for ISE, which is … 15Gbyte once installed) that has the chipscope enabled. The price is cheap and it is very useful, thank you for your advice !

author: mrflibble
author_rank: Super Contributor
timestamp: August 03, 2014, 03:24:43 pm
content: Yup, that board is nice price/performance. Especially considering the included chipscope license.About chipscope, you might want to get into the habit of manually instantiating the ICON and ILA and such. The *pointy* *clickey* workflow where this gets automagically included does work, except when it mysteriously fails for bullshit reasons unknown. Maybe the underlying issue has been fixed by now (as per ISE 14.7), but I'm not waiting to find out.

author: Bassman59
author_rank: Super Contributor
timestamp: August 04, 2014, 04:09:00 am
content: Quote from: mrflibble on August 03, 2014, 03:24:43 pmI haven't instantiated a ChipScope core in my code in ages; I always use the core inserter. And this is going back to something like ISE 10.It tends to fail if you change the source code and forget to open up the design in the core inserter after synthesis and before place and route. Once I got into the habit of doing that it is fine.Plus the ability to import the .cdc file into the ChipScope Analyzer window is genius. Start the ChipScope analyzer, connect to the chip over the JTAG, and when it finds the core, do the import. Then all of the signal names in the design are matched with what's in the analyzer. Saves a lot of work renaming all of the signals.

author: legacy
author_rank: Super Contributor
timestamp: August 04, 2014, 12:00:38 pm
content: also, the chipscope "locked license" will expire in 1 year since when you activate it, the license manager is telling me this

author: miguelvp
author_rank: Super Contributor
timestamp: August 05, 2014, 03:10:43 am
content: Quote from: legacy on August 04, 2014, 12:00:38 pmI don't know how is it for Xilinx toolchain, but on Altera's they have a talkback option that lets you use their signaltap features. Cypress toolchain has something similar, so maybe the Xilinx one offers it or will offer it in the future?I like the model of free as long as you provide silent feedback, and no, they don't send your code to them

author: legacy
author_rank: Super Contributor
timestamp: August 05, 2014, 05:10:56 pm
content: Quote from: miguelvp on August 05, 2014, 03:10:43 amit seems the same with Xilinx web pack license: the ISE WebPack edition's license will never expire if you enable the talkback, unfortunately the ChipScope seems to have a different license that looks like "locked" to a workstation (you have to provide your hard disk serial number, or your built-in LAN's MAC) and time-limited

author: Bassman59
author_rank: Super Contributor
timestamp: August 05, 2014, 07:40:11 pm
content: Quote from: legacy on August 04, 2014, 12:00:38 pmThe license should be perpetual, meaning that when it "expires," you won't be able to run any version of the software newer than the license expiration date. And since ISE 14.7 (and thus ChipScope 14.7) is the end of the line, there won't be any more ChipScope updates so you're good.

author: Bassman59
author_rank: Super Contributor
timestamp: August 05, 2014, 07:41:55 pm
content: Quote from: legacy on August 05, 2014, 05:10:56 pmYou cannot disable the talkback with WebPack. Well, not without either disconnecting the network from the Internet, or doing things in your router to block whatever the talkback feature tries to access.

author: legacy
author_rank: Super Contributor
timestamp: August 05, 2014, 11:02:27 pm
content: Quote from: Bassman59 on August 05, 2014, 07:40:11 pmif i invoke ISE the license manager is reporting me that i have activated a locked-license on august 4, 2014 and that it will expire on august 4, 2015, this makes me thinking that when it will expire i will simply have to buy and other license that will expire in 2016, and so on (1). The license is physically a file in where there are a lot of characters probably encoded with an hash algorithm, something that probably has been made with- an activation date, when it has been activated- an expiration date, when it will expire- an host ID, made with lan mac address or hard disk serial number- a licence ID (which should implicitly contains a "license kind", a magic code that could make it permanent or not)this is my speculation about how it could work, but i can imagine that all of these informations have been encrypted with an hash algorithm (i do not know which one) in order to make the physical license file.btw, when i bought the AVnet board i got a piece of paper inside the box with a long string made of alphanumerical characters and i was asked to fill all of these chars into a web form, also providing my hard disk serial number, and implicitly providing the activation date, in order to get the license-file by email(1) at work a friend of mine has exactly this working scheme withWindriver's things, he has volatile licenses that expire in X-days, when a license expires he simply buys an otherp.s. you are right, you can not disable the talkback in the WebPack, you can disable it only if you install the FULL suite.

author: legacy
author_rank: Super Contributor
timestamp: August 05, 2014, 11:10:34 pm
content: from the email i got from Xilinx, i know there are 4 possibilities about licensesQuote

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 06, 2014, 01:05:14 am
content: Clicked on thread, did not see partially open hardware with skimpy dongles attached. Disappointed, 1/10.Tim

author: legacy
author_rank: Super Contributor
timestamp: August 06, 2014, 02:30:31 am
content: Quote from: T3sl4co1l on August 06, 2014, 01:05:14 amhave you checked this ?Quoteif so, any comment about ?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 06, 2014, 02:37:37 am
content: Quote from: legacy on August 06, 2014, 02:30:31 amDon't mind me, I'm just joking... it's a Reddit style comment..Tim

author: legacy
author_rank: Super Contributor
timestamp: August 06, 2014, 02:48:19 am
content: that's ok, like the reddit style comment i wrote to express my disappoint with this (1) guy(1)QuoteQuote