Internal planes to improve thermal dissipation through thermal vias - Page 1
Forum section: electronics / projects

author: ricko_uk
author_rank: Super Contributor
timestamp: June 11, 2023, 10:38:54 pm
content: Hi,I have a simple power PCB (mostly power transistors) where most of the power MOSFETS are SMD. To ensure that is runs at as low temperature as possible I am thinking of using the internal planes to help a little bit further wit thermal dissipation.So I created a solid copper region under the TO263 on the top layer (much larger than the TO263 footprint) and then the same large copper area also on the bottom layer AND on the two internal power planes. Then filled the area with thermal vias. That way the heat is transferred to the internal planes through the via copper as well as through the FR4.Apart from being a bit more difficult to solder because of more heat being absorbed by the copper (instead of all going to the solder), are there any other potential issues?Thank you

author: Benta
author_rank: Super Contributor
timestamp: June 11, 2023, 11:07:19 pm
content: I think you need to do a basic think about this.The element cooling your circuit is the surrounding air (unless it's submerged).So burying copper inside your PCB will effectively insulate it from the surrounding air, right? Not a good idea.Letting your copper dissipate freely would be a better option, I think.

author: artag
author_rank: Super Contributor
timestamp: June 11, 2023, 11:43:06 pm
content: They have copper on the bottom layer too, though. What is needed is to ensure a good thermal path through the board to that surface. Adding a surface on the intermediate planes will increase the thermal capacity of the whole block, so ts temperature will rise - and fall - more slowly. However I don't see that it would increase the thermal resistance from top to bottom, which is the critical parameter.

author: trobbins
author_rank: Frequent Contributor
timestamp: June 12, 2023, 12:23:36 am
content: I can't see why that technique wouldn't help to lower thermal resistance. Are the vias being filled with solder? Are you soldering the thermal tab of the Fet to the top copper land?Of course this may be all somewhat mute if the pcb is not able convect, or better still conduct, that local heat source relatively easily to an external ambient.

author: uer166
author_rank: Super Contributor
timestamp: June 12, 2023, 12:25:14 am
content: I'll counter the above 2 replies and mention that inner planes do help the overall situation by improving heat spread laterally, so more of the outer layer is effective. It's more than a measureable difference, and the inner planes help quite a bit. Maybe 2 extras won't be huge, but I've designed boards with 44kW passing through, and a couple 2Oz internal layers can make or break it.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 12, 2023, 01:13:18 am
content: Quote from: ricko_uk on June 11, 2023, 10:38:54 pmMultiple layers certainly help, as it spreads the heat around the board, lowering the hot-spot temperature. Have max-pour on all layers, and make the via-array-connected areas as large as practical.Sometimes you can get thicker copper too, for a few cents more.This from Nexperia data for a SOT223 package BCP56T shows that effect in numbers :0.6 W Device mounted on an FR4 Printed-Circuit-Board (PCB); single-sided copper; tin-plated and standard footprint.1 W Device mounted on an FR4 Printed-Circuit-Board (PCB); single-sided copper; tin-plated; mounting pad for collector 1 cm21.3 W Device mounted on an FR4 Printed-Circuit-Board (PCB); single-sided copper; tin-plated; mounting pad for collector 6 cm21.3 W Device mounted on an FR4 Printed-Circuit-Board (PCB); 4-layer copper; tin-plated and standard footprint.1.8 W Device mounted on an FR4 Printed-Circuit-Board (PCB); 4-layer copper; tin-plated; mounting pad for collector 1 cm.2These days you also use lower RDS mosfets, to manage power / temperature rise.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 12, 2023, 01:58:21 am
content: Is this DC or switching? Inner planes tied to drain is a red flag for stray inductance -- you normally want that as GND or whatever.Thermal resistance can be estimated within planes, between layers, and to space. The bastard-units figure I remember is 150 C in^2/W for surface convection, so, divide by board surface area to get Rth(PCB-A) as a rough estimate.Heat spreading is dominated by copper, as it's much more conductive than FR-4 in-plane, and muchmuchmore conductive thru-plane hence the value of either vias, or wide overlapping pour areas, to sink heat and spread it out. Units for all these materials can be looked up, and, just do some basic sums on cuboidal segments to get a feel for what's good and bad, and what ballpark total Rth's are.Don't worry about nonuniform (non-parallel-to-cuboid-faces) heat flow; you'd need a sim to figure those out for sure, but, a sim likely won't improve accuracy a whole lot over a reasonable estimate, unless your thermal system is very complicated and simulation is the only feasible estimation method. (But then, one might accuse you of making things needlessly complicated: stick to simpler, easier-to-estimate geometry where possible. There are still some cases where that complication is deserved -- but be prepared to pay, whether empirically (build and test) or by simulator.) And, if you need Rth that accurate (say <10%) -- you're probably doing something else wrong (running devices at the bleeding edge of ratings!).Multilayer boards often have thin outer laminates, so that the Rth from top/bottom to inner is fairly modest. Indeed this greatly increases the ampacity and fusing current of outer traces, where they run over planes (and doesn't where they don't, so beware if otherwise narrow and high-current traces have to cross wide gaps between planes!).Because D2PAK is a nice wide package, and can be widened further with same-side thermal pour, it often suffices to have *an* internal plane -- doesn't have to be connected to drain. Vias also help (the via barrel has some resistance to the inner plane too!), just mind not to choke off the inner plane by making a solid fence. And vias carrying heat to the opposite side are not only convenient for direct sinking (say by squishy thermal pad), but to more heat-spreading pours (further improving the transfer of heat to inner planes).Alternately, you may find it advantageous to use a 5x6mm PDFN-8 ("PowerSOIC" or whatever; there's literally a thousand names for compatible packages..), which being thinner is not only better able to sink some heat from its top side (some variants even include top side heatsinking metal), but allows a thermal pad to get closer to the board and nearby components. Available ratings aren't much less than D2PAK (the biggest difference being thermal mass, if you happen to be doing a pulsed application), and the power density can be higher.Tim

author: f4eru
author_rank: Super Contributor
timestamp: June 12, 2023, 07:24:00 pm
content: A heat spreader in inner layers is a good thing.Beware of EMC, especially if your drain is switching.You can increase the thickness of the inner layers from typical 17um to 35um.filling the vias with solder also helps.

author: ArdWar
author_rank: Frequent Contributor
timestamp: June 15, 2023, 05:08:16 am
content: Keep switch node as small as reasonable. If you really want to dissipate heat and don't mind using rather nonstandard packages, there are evenreversed MOSFET packageso you can pour on the VCC plane instead.

author: ricko_uk
author_rank: Super Contributor
timestamp: June 15, 2023, 06:54:00 am
content: Thank you all, lots of useful info and feedback.@Tim,some are switching and some linear. Yes I did changed one of them to a SOIC powerpack as you suggested.And as some of you suggested I will get the vias filled.Thank you

author: Siwastaja
author_rank: Super Contributor
timestamp: June 15, 2023, 12:31:11 pm
content: Which net? If GND, then obviously you use continuous planes everywhere and get best possible EMC and thermals.Non-GND? Internal polygon on non-GND net might be worse than contiguous GND plane, and I don't only mean EMC, but thermal too. Heat can't go sideways because the polygon ends somewhere. Instead, if you have the non-polygon/large pad just on top layer, and right underneath it (with usual prepreg thickness say 0.2mm) a GND plane, heat does flow through FR4 to that GND plane because the FR4 prepreg between top/mid1 is so thin. And because it's an uninterrupted GND plane, heat can also go sideways to some extent - not very far because copper is thin, but still better than with smaller, isolated polygon. The GND plane tends to have vias already, heat couples everywhere on the board.If this is not enough, then you can use thermal vias to move heat on bottom layer polygon, so that you can add a thin sheet of thermal interface material and mount the whole PCB on a aluminum heatsink. Single-sided SMT-only component load makes this easier.Thermal vias should be as small as possible because holes are just air and you want to minimize that; ratio of copper-plated holewell cross-sectional area vs. board area wasted gets better with smaller holes, and you also get rid of excessive solder wicking into holes which could become a production yield / reliability issue. 0.3mm is quite optimal IMHO.

author: ArdWar
author_rank: Frequent Contributor
timestamp: June 15, 2023, 05:14:43 pm
content: Quote from: Siwastaja on June 15, 2023, 12:31:11 pmIf you have to use via in pad it's worth to pay for plugged vias to minimize manual inspection and rework due to wicking, especially if the other end is not tented (or even worse, also a pad). I still got considerable amount of wicking even with 0.3mm via!

author: DavidAlfa
author_rank: Super Contributor
timestamp: June 15, 2023, 05:19:57 pm
content: Quote from: Benta on June 11, 2023, 11:07:19 pmWhat? You aren't insulating anything, but spreading the heat, thus increasing the power dissipation factor.You can't insulate anything by adding thermally-conductive layersFR4 is a much worse heat conductor than cooper, adding a ton of vias and tinning/filling them will be a much better option.The thermal performance improvement will be small or large, but will be better for sure.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 15, 2023, 05:30:09 pm
content: Quote from: ArdWar on June 15, 2023, 05:14:43 pmNote that one-side-tented via-in-pad is worse, because it will likely fill with flux, bubbling away incessantly during reflow, thus leaving a void -- and maybe putting voids into the wider pad area too. Most preferable is filled/capped vias (no impact on assembly, more expensive fab), then untented (solder thieving, no cost), then half-tented (causes voiding). Fully tented is kind of an option but kind of not: the added thickness of soldermask means the device can't sit as flat on the board, but also you need to go through extra effort to make such a shape (normally soldermask is logical-OR of any overlapping objects, thus you need to construct a custom soldermask shape for any tented via-in-pads). And the masked area is obviously not soldered, so you're intentionally putting in a void (maybe it's not a gas void, but solder and mask don't bond well is the point), and just hoping it doesn't cause enough area reduction that problems occur.Small untented vias (under 0.3mm ID) are generally not too bad, as they don't wick very quickly. Lead-free also spreads out slower than leaded. Via size may be a restriction on power boards (thicker board, heavier copper --> larger minimum drill/via size required) so you can't always use this, but it is at least relevant to, like, SON/QFN packages where via-in-pad is the only reasonable way to handle the center pad.Tim

author: Siwastaja
author_rank: Super Contributor
timestamp: June 15, 2023, 06:37:18 pm
content: Quote from: ArdWar on June 15, 2023, 05:14:43 pmThere is no need to pay for plugging, it's just an extra expense for no reason. Gazillions of products are being made with normal vias no problem whatsoever. This is also what all datasheets and appnotes of SMD power packages show. I have never had any issues either. Remember, we are not discussing a 0.3mm hole in a 0402 SMD resistor pad which would wick too much of the small solder volume; we are talking about components that require cooling and have large thermal pads with shitloads of solder paste. Plugged vias are for increasing component density by allowing vias in any pads, including small chip capacitors / resistors.

author: ArdWar
author_rank: Frequent Contributor
timestamp: June 15, 2023, 07:05:29 pm
content: My case is that much of an outlier I guess. Rarely manufacturers app notes /recommended layouts include cases where there are components on the other side. Much less cases where the other side is also a huge pad /bare copper, making vias wicking nightmare both ways.

author: tszaboo
author_rank: Super Contributor
timestamp: June 15, 2023, 08:35:28 pm
content: Quote from: T3sl4co1l on June 15, 2023, 05:30:09 pmYou know, I used to think this way. Then I realized, that if something works with QFN packages, why wouldn't it work for transistors?

author: thm_w
author_rank: Super Contributor
timestamp: June 15, 2023, 10:37:12 pm
content: Quote from: DavidAlfa on June 15, 2023, 05:19:57 pmAnd air (~0.01W/mk) is a much worse heat conductor than FR4 (0.25 with no copper present).Common PCB design myth, that internal layers are somehow "super insulated" from the outside environment. When it is not the case.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 16, 2023, 01:54:31 am
content: Quote from: tszaboo on June 15, 2023, 08:35:28 pmNot sure what your "realization" is implying? If you mean like power/DFN transistors, yeah, that's no problem either. Leaded types however have the requirement of additional solder to form a fillet, so thieving is a bit more critical there.Tim

author: T3sl4co1l
author_rank: Super Contributor
timestamp: June 16, 2023, 02:16:39 am
content: Quote from: thm_w on June 15, 2023, 10:37:12 pmDistributing heat, from where it's generated, to where it needs to go, is probably a somewhat underappreciated problem.A basic calculation of, say, a transistor bolted in the middle of a wide sheet -- well, I wish it were "basic", the solution (for fairly basic/standard assumptions, that is) actually involves a Bessel function -- but the result is that heat spreads out in some radius (to within some margin of total dissipation e.g. 90% of power dissipated within some radius R), determined by sheet conductivity and dissipation rate (assuming linear convection, no chimney effect etc.), with the total temperature rise depending on these constants, and the source radius (that is, assuming heat is deposited within an isothermal patch of radius r).The temp rise depends critically on r, because as r --> 0, the thermal resistance of the sheet diverges, as the circumference of layers carrying heat away from the point are approaching zero. This shouldn't be a controversial point; it's also why e.g. arcwelding, or laser cutting (or e-beam welding for that matter, for a somewhat exotic example), require relatively low power levels (from kW, down to 10s of W) to fully melt or even vaporize the base metal in a small spot, whereas doing that over a large area would take orders of magnitude more power.You want a large starting radius, to keep device temperature low. Transistors use small dies on large copper tabs to facilitate this. But you don't want to put too much power through a tab of some size; hence why we might recommend TO-220 stay under 50W, TO-247 under 100W or so, etc. (particularly with thermal interface material in play; with greased joints and large or liquid-cooled heatsinks, double or triple these figures can be feasible).There is value in heat spreaders. Instead of bolting a device to a heatsink, bolt it to another, heavier tab, to a heatsink. Or bolt it to multiple heatsinks.Or, those CPU heatsinks with a copper slug pressed in place. Gimmicky? Maybe. Effective? Yes!A similar case is that pyrolytic graphite sheet stuff -- terrible, awful thru-plane conductivity, it's basically plain graphite; but mind-boggling in-plane conductivity,better than copper,approaching diamond even! Now, if you have a few 0.1mm's to spare, you get the same effect from a somewhat heavier sheet of copper -- but in the rare case you don't, this stuff can do wonders. You still need to spread out heat wide enough in the local area to ensure it's flowed through the sheet, but once there, it's spreading as far as it can. A lining of that might make a plastic enclosure thermally feasible, for example, whereas you might have to go with painstakingly machined aluminum otherwise.It's a situation very similar to multilayer PCB: you need to spread the heat out a little ways first (expand the device footprint with pours; start getting heat into the board with vias), to get it into all layers; from there, it continues to spread out along inner planes, and since convection rate is lower than PCB thru-conductivity, the outgoing thru-FR4 conductivity is negligible, it only counts against you significantly near the source.Tim

author: tszaboo
author_rank: Super Contributor
timestamp: June 16, 2023, 09:08:47 am
content: Quote from: T3sl4co1l on June 16, 2023, 01:54:31 amNo what I mean is like putting vias under a DPAK package. I have old designs where vias are carefully placed outside the footprint, with soldermask between. Placing a 0.3mm via under a DPAK works just as well, in fact better because it's thermal resistance is lower.The basic rule for heat distribution is the same as current. Metals have a very similar electrical resistance and heat conductivity properties. So a ground plane is good at carrying currents and it's just as good reducing temperature. And it doesn't magically trap the heat inside, even if FR4 is a bad conductor. Even if you have a 0402 resistor on a minimal footprint, flooding it with ground with 0.15 or 0.2mm separation will reduce the temperature it significantly.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 16, 2023, 10:01:08 am
content: Quote from: tszaboo on June 16, 2023, 09:08:47 amIn fact significantly better: lateral heat transfer within component pad area is good because the component substrate/carrier/leadframe itself (which can be order of magnitude thicker than PCB foil) participates. As soon as the component pad ends, all you have is PCB foil. If you place all the vias very close to the component area, not too bad but then you have only one row of vias you can use. Any added rows contribute less and less.Also, some amount of solder wicking into holes increases thermal conductivity even further, although the exact amount is hard to guarantee so you can't count on it.QuoteFR4 is not thermal "insulator" at all, yes. At 1.6mm thickness, it's not that great for thermal transfer, but coupling from top to mid1 (or from bot to mid2, in 4-layer design) is surprisingly good because the prepreg is so thin (due to the usual impedance control requirements for microstrips). I remember once testing a 0603 resistor with standard size pads but full ground plane right underneath, and even dissipating ten times the rated power did not cause destruction or resistance shifts within hours of testing. The extra cooling effect compared to the 2-layer design without ground plane, assumed in datasheet ratings, is just so great. Basically the whole board (maybe 10x10cm) heated up in that simple test. It helps when you also pour top and bottom and stitch the GND planes together over the whole board area: even if the heat initially couples to MID1 only, if you have GND vias close by, it's soon coupled to all four layers.