Copper covered thermal vias? - Page 1
Forum section: electronics / general

author: ocset
author_rank: Super Contributor
timestamp: August 19, 2018, 11:54:44 am
content: Hello,We want to put thermal vias in the pad of our DPAK FET. Is it possible to get thermal vias which can be covered over with copper, so that there are no holes through which solder can wick away during reflow?(I am not talking about copper filled vias…rather, I am speaking of “copper covered vias”….copper filled vias are too expensive)

author: TJ232
author_rank: Frequent Contributor
timestamp: August 19, 2018, 12:34:21 pm
content: No.

author: Nusa
author_rank: Super Contributor
timestamp: August 19, 2018, 01:03:41 pm
content: To prevent solder wicking, you don't need a cap. You just need to specify the holes be filled. The usual non-conductive fill material is fine. It doesn't have to be copper.But what you describe does exist. The hole has to be filled first. This explains is as well as I can:https://www.pcbuniverse.com/pcbu-tech-tips.php?a=5It may not exist at your favorite low-cost shop, however.

author: TJ232
author_rank: Frequent Contributor
timestamp: August 19, 2018, 02:50:00 pm
content: I think you want to reinvent the entire Via Tenting, Plugging, and Filling process fabrication?As I said before, what's hard on your posts is not to give an answer but to guess the intended question.With all the problems that you have out there with your products, how and IF it makes any sense for you to cover or not your vias is your last problem to think about right now.

author: chris_leyson
author_rank: Super Contributor
timestamp: August 19, 2018, 03:14:55 pm
content: BetaLayout and Eurocircuits will do via in pad with filled vias and plate over the top/bottom.

author: ocset
author_rank: Super Contributor
timestamp: August 19, 2018, 04:41:15 pm
content: Thanks very much Chris, may i ask if you know if its massively expensive or not?Im amazed that it can be done and leave a flat copper surface...and not a little bump over the filled via bit.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 19, 2018, 07:06:00 pm
content: Yes. And there's also plated-shut vias when small diameters are used (I think 5 mil typically?). Probably more relevant to a HDI build, which is probably not what you want here.Tim

author: D3f1ant
author_rank: Frequent Contributor
timestamp: August 19, 2018, 07:26:15 pm
content: Using 0.3mm hole vias on the thermal pad (inc dpak) devices geberally fine. It's common practice, look at the recommendation of the pad design by the device manufacturer or other similar devices. They typically have many vias under there and make no mention of having to use 'special' vias.

author: ocset
author_rank: Super Contributor
timestamp: August 19, 2018, 07:40:52 pm
content: Thanks, i dont know if it was our board stuffer, but we had 0.3mm thermal vias in our dpak pads...but we got wicking through them and solder bumps on the bottom side of the PCB...which meant it wouldnt sit flat on the heatsink pad.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 19, 2018, 08:29:53 pm
content: Shrink back side solder mask expansion. It'll only wick down to the surface.0.3mm vias, in ENIG, lead free, with a properly tuned reflow profile, often doesn't wick all the way through. 0.2mm rarely wicks all the way through.Tim