Audio ADC/DAC interfacing (CS4272, balanced in/out) - Page 1
Forum section: electronics / projects

author: Yansi
author_rank: Super Contributor
timestamp: January 20, 2024, 06:43:49 pm
content: Hello,just got decided to try building a small simple audio DSP module, to get some more hands on and put some theory to the test.What I have is aCirruc Logic CS4272 audio coded IC (datasheet), which i intend to put on a PCB together with a couple of balanced interfaces, a microprocessor and some other stuff. However, during the design, I have come to some level of difficulty making some design decisions or getting enough understanding of stuff to do or not to do.So first, the CS4272 codec has balanced inputs and outputs. My module is supposed to also provide balanced input/outputs (possibly, XLR), so I was thinking about how to interface in between those and the codec itself. Due to both the input and output being balanced, I came to the idea of usingOPA1632 (datasheet)FDA (fully differential opamp), as I also have a couple of those available.Lets first discuss the input section, from the XLR to the ADC. After studying theCS4272 evaluation kit (manual here), it seems it can be somewhat helpful, but not fully. One would need at least three normal opamps to interface from the XLR to the ADC: One to make a difference amplifier for the XLR input, and again two making a differential driver. Thats at least two SOIC packages. The OPA1632 seems suitable for an ADC driver, as the datasheet suggests, and could be done in a single package. Or, so I hope.However, I find there a couple of problems: Input impedance is just 2 kohm differential, 1k single-ended. Standard line level audio interfaces use something like 10 k afaik. The gain of the circuit is less than unity, -11.4 dB to be exact.Now lets have a look at the CS4272 spec.: Input full scale voltage is specified as 1.15xVA = 1.13 * 5V = 5.65 Vpp of input voltage. That is almost exactly 2 Vrms, or +8 dBu in audio engineer units. As I want the module to operate with a nominal level of 0 dBu (775 mVrms), I already have a headroom of 8 dB, as 2 Vrms is about +8 dBu. Now the question is: Is this considered a good enough headroom for practical use? Increasing the headroom excessively will decrease my SNR, as the signal will get closer to the noise floor. So I think I should leave the amplifier between the XLR input and the ADC with a unity gain.Now back to the OPA1632: Does something like this make any sense? I have increased the input resistors to 10 kohm, to obtain 10k unbalanced and 20k balanced input impedance. I have also added an input RFI protection (according to Douglas Self's book, it should be good enough and according to my experience it should be sufficient too) and AC coupling, as the FDAmp will operate with an offset of 2.5 V to match the ADC input requirement.The feedback circuit got a bit more tricky to modify. I have used this articleOp Amps Driving Capacitive Loadsto calculate the values again and ended up with something like this:I am not sure, if this is usable or not. It happily runs in LTSpice, but is it practical, to do an interface like this? I know, that the noise will increase, when using 10k resistors instead of keeping the ~1k impedance there, but I have no other choice, 1-2k is too low input impedance for a generic line input.I would like to ask now: Is this kind of interface good enough, or are there any significant flaws I missed? The only thing coming to mind now is that some for of amplitude limiting/protection should be good to add, both maybe for the ADC and the input of the OPAMP. Thinking of just clamping the inputs to supply rails with 4148 or similar diodes? Is there anything else I should consider?Many thanks,Y

author: Yansi
author_rank: Super Contributor
timestamp: January 20, 2024, 06:55:47 pm
content: This is what I was thinking about the input amplitude protection: Either place diodes directly after the coupling capacitors C29 C30, or maybe would it be even more clever to split the input resistors of the FDamp, and place them after about 1k of impedance, to provide some current limiting for the diodes?Again, looking at the Douglas Self's book (Small Signal Audio Design), he claims the distortion added by such a diode clamp (by junction capacitance voltage variation) shall be negligible, when the impedance before the diode clamp is kept at about 1k or less.//EDIT: Now thinking about it, shouldn't the ADC also have a lowpass filter in front? Looking at the CDB4272 eval board, they have a 48kHz -3dB lowpass only after the DAC. No lowpass before ADC. Why?

author: moffy
author_rank: Super Contributor
timestamp: January 20, 2024, 11:23:53 pm
content: The OPA1632 has around 10uA input bias current, one reason for low input resistor values, also it's 180MHz GBW, the low values and driving a capacitor probably help with stability. If you already have a differential input why not use two unity gain buffers? If you need to convert from single ended to differential as well it would need a little more thought.e.g.https://statics.cirrus.com/pubs/proDatasheet/CS4272_F2.pdfand page 32

author: Yansi
author_rank: Super Contributor
timestamp: January 20, 2024, 11:39:52 pm
content: I have a balanced input, sure, but with XLR universal input, you have no guarantee the input signal will be always balanced. It very well can be unbalanced. The CS4272 evaluation board does exactly as you have said - uses just two unity gain buffers. Probably expecting always properly balanced signal to be available.I was thinking about using the FDA because it will significantly decrease the component count.Is the input bias current really an issue? For possible offset voltages, sure, but that won't matter much. I see that the input current noise density is comparable to for example NE5532 opamp (around 2pA/sqrtHz), and the voltage noise density even much better, than NE5532. So in the end, the noise will by dominated by the Johnson noise from the higher value resistors. Am I right? GBW is of no concern here, fortunately.Not much I can do about, as there are requirements for an input impedance to be reasonable. I would need to buffer the inputs, so I could use low value resistors around the FDA. That would mean an extra SOIC package and the advantage of doing everything with a single FDA package would be gone. (am kind of fighting space on the PCB)But am kind of finding other issues with the FDA, like that the transfer function of a filter is not the same for unbalanced input. And a transfer function for common mode is another weird animal. Am not liking it much, so I am kind of undecided, whether I should go back to NE5532, where I am confident I can make it work. I admit I have never designed with an FDA, hence asking and confirming, if what I am doing makes any sense.

author: moffy
author_rank: Super Contributor
timestamp: January 20, 2024, 11:59:45 pm
content: Personally if I was using the OPA1632 I would keep the resistor values low, I mentioned the GBW because high BW opamps like low value feedback resistors for stability reasons, but I have no personal experience with the OPA1632, and you do have the feedback capacitors.

author: Yansi
author_rank: Super Contributor
timestamp: January 21, 2024, 12:23:09 am
content: The output circuits should be easy to implement with a single NE5532 (single SOIC package), as one half I would use to implement the recommended output filter from the CDB4272 and the other half would be used to just create the inverted copy of the signal, to preserve balanced output, easy:But the input circuit is killing me (and my ideas). My original idea of "simply using" an FDA is starting to seem not so simple. If we could invent a way, how to utilize a single NE5532 to do the job, I would happily get rid of the FDA.For sure with the 5532 input section, I could use one to make the input differential amplifier and he other half as a inverted buffer to create again the differential output for the ADC. However am not sure how would one add the input lowpass filter there. (Is one needed at all for the ADC?)Searching theCS4272 datasheetin section5.4.1 Input Connections, they mention this:If I understand well, there is no need for any special LPF filter, if one can keep RF junk out of the input far enough. Hence probably why the eval board does not contain any LPF circuit before the ADC.In such case, it could be doable with just a dual opamp such as 5532. Need to think more about it.//EDIT: Something like this? It would be nice to have the resistors around that inverting buffer small, but achieving symmetric transfer of both halves would not be easy. This way with same resistors and capacitors, result is guaranteed, although with a bit higher noise. :-/ I have calculated the f3 to be again around 500 kHz as with the original buffer, but attenuation would need to be verified, as the circuit is slightly different from the recommended one.But hold my beer, I have some more ideas, maybe.

author: moffy
author_rank: Super Contributor
timestamp: January 21, 2024, 01:14:31 am
content: That looks quite reasonable as long as the 5532s can drive the needed input storage capacitor for the ADC, but I assume they can because of the 100R resistors and the positioning of the 33p feedback caps. If you want to improve CMRR then you could replace R18 with a resistor and low value trimmer and R18 should probably be bypassed by something like the 33p feedback cap.

author: jonpaul
author_rank: Super Contributor
timestamp: January 21, 2024, 11:56:09 am
content: To commen a few question:Application eg home studio? Broadcast? High end HiFi?Expected signal sources, V range, Zo?Expected dynamic range and SNR?Jon

author: Yansi
author_rank: Super Contributor
timestamp: January 21, 2024, 05:26:49 pm
content: Jonpaul:Application eg home studio? Broadcast? High end HiFi?PA speaker hobby project.Expected signal sources, V range, Zo?Whatever the previous signal source will provide. Could be straight from a mixing desk, DSP rack or what not. Signal level for nominal operation is expected of course to be 0 dBu (775 mVrms) for full blast, with some headroom for peaks. As discussed above, I think that 8 dB of headroom above full power is enough, isn't it? (to process signall peaks above nominal level without clipping). Zo of the signal sources is depending on the device, usually could be around 100 ohm or so. Balanced, or unbalanced.Expected dynamic range and SNR?Hard to answer these. The best I will be able to do within the constraints I have. Which in this case is mostly driven by the size of a PCB, so the design must be a KISS type (Keep It Simple Stupid). I don't need anything fancy, but hate doing half assed job. I don't even have much practical experience with these designs yet, so don't know what is achievable easily and what is not.After some more plying around with the OPA1632 in LTSpice, I come to the conclusion, that it is not really that of a great choice as I thought. So back to square one, with NE5532s. Nothing wrong with these opamps, only likely need one SOIC package more. And to conserve some space, I was thinking the FDAmp could help.See below, what am I fighting with. The PCB width is 115 mm and I can not have any more, limited by the space I need to get it into. Depth of the PCB behind the panel is currently 50 mm, but I could probably add a bit more.It is just a first idea slapped-together, so please ignore the cruelty on the PCB. Am just considering things to know, whether it'll fit, or I need to rethink the whole design. Need to improve there a lot of things and think about the separation of digital stuff from the analog. Not sure, if with such limited space I could get any acceptable results.And finally, I have an access to a proper audio analyzer (Audio Precision), so I could validate the design by measurement, not just ears.

author: jonpaul
author_rank: Super Contributor
timestamp: January 21, 2024, 08:02:19 pm
content: Rebonjour, suggst to reexamine your goal, as it is unclear:Powered speaker?Include DSP for EQ, anti X talk, etc?Watts/power amp type?Most powered PA speakers now are digital input bluetooth, WiFi or if wired,Digital: I2S, AES/EBU, SP/DIF, AES3id.The use of a balanced XLR line level inout on a speaker is unusual and seldom used.The need for a balanced audio in/out is questionable in you use.Finally examinethe chipsets sopecifically designed for DSP/EQ use with onboard ADC/DAC/DSP from ADI, TI, AKM.No need for any outboard diff amps. or diff ADC/DAC.Bon ChanceJon

author: Yansi
author_rank: Super Contributor
timestamp: January 21, 2024, 09:15:19 pm
content: Yes, powered active speaker, with a DSP module included to provide a pre-set EQ, crossover, limiter and dynamic protection.Have currently two projects I could use this in: 600-700W class D powered subwoofer and a 200W class D LF and 60W HF biamp. Does not matter, does not change anything what we are supposed to discuss here.Most powered PA speakers now are digital input bluetooth, WiFi or if wired,If talking about those commercial cheap plastic ghettoblasters, then probably yes. Not interested in those. One better buys one off the shelf.Digital: I2S, AES/EBU, SP/DIF, AES3id.I2S is the local serial bus between the CS4272 and the microcontroller/DSP. AES/EBU is the Audio Engineering Society / European Broadcast Union, did you mean the AES3 standard (the "professional S/PDIF") instead? S/PDIF for home use, sure. AES3 and AES3id for professionals, sure. Neither of which I have ever seen used to run signal into an active reinforcement speaker cabinet.The use of a balanced XLR line level inout on a speaker is unusual and seldom used.On cheap junk, maybe not used. It is the number one analog interface on anything more serious than a cheap ghettoblaster.The need for a balanced audio in/out is questionable in you use.No comment. Quite often we use cable runs of more than 50 meters from the source to the active speakers. Not sure if I would ever want to try that with unbalanced.Finally examinethe chipsets sopecifically designed for DSP/EQ use with onboard ADC/DAC/DSP from ADI, TI, AKM.Not interested. I can and want to make my own DSP processing, and the codec was already given (CS4272). My favorite CS4270 is no longer made, hence CS4272 as a replacement.No need for any outboard diff amps. or diff ADC/DAC.Not sure what do you mean by this. All interfaces I need the codec to connect to, are differential and the codec itself has differential io also.We are not here to question how an active PA is built, but to solve an interfacing problem with a differential in/out of the CS4272, as I have never used this chip and see no issue with learning how to do so.To make things possibly more clear, if somebody wants to dig what is this for, then see following diagram please:This is an absolute typical signal flow as used in a woofer or two-way active reinforcement speaker. In an subwoofer configuration, you use one output channel for the obvious, the woofer, and you loop out the second channel back out, to be used by the speaker cabinet on top. This way, you can make a matching crossover for a matched pair of subwoofer + mid/HF speaker cabinet.Option 2 is to connect XLR physically in an IN -> LOOP OUT configuration (as usual with full-range speakers), both DAC channels are then used to feed a biamp powered two-way speaker cabinet (active crossover in the DSP).Look for example at this picture of ours of a rather typical active two-way speaker.I hope it is now much more clear of what is going on. Now please back to the circuit design

author: jonpaul
author_rank: Super Contributor
timestamp: January 21, 2024, 10:42:42 pm
content: SuggestBAL>SE line rec 600 OhmInput of CODEC ADC ><CPU/DSP/MCU via I2SCODEC DAC SE >< BAL LINE DRVj

author: Yansi
author_rank: Super Contributor
timestamp: January 22, 2024, 12:45:21 pm
content: Awesome, but that is what I already have(Except that 600 ohm is not used for audio connections. Analog audio is usually run as a low impedance source and high impedance receiver end.)

author: Yansi
author_rank: Super Contributor
timestamp: January 28, 2024, 11:55:43 am
content: While trying to design a power supply for the codec, I ran into a bunch of troubles, as the datasheet contains a lot of almost contradictory stuff and the evaluation board is even violating datasheet values.The CS4272 has three supply pins:VDDigital Power (Input) - Positive power for the internal digital section.VLLogic Power (Input) - Positive power for the digital input/output interface.VAAnalog Power (Input) - Positive power for the internal analog section.TheCS4272 datasheetthen in section 5.7 states:Figure 8 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply (VL) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be powered from VD.If VL is the digital IO, why does it have to be connected to a clean source?As VL dictates voltage levels on the IO interface, does it mean I need et another clean 3V3 regulator?If VD is the digital section, why is it allowed to be powered from the clean analog?See above picture from datasheet. I would guess VA andVDneed a clean supply, since they can be powered together from a clean 5V supply. But the text in the datasheet suggests VA andVLshall be the clean supply.And I have found more discrepancies: See the note in the image above, on VCOM pin you are not supposed to exceed 1uF. So what capacitors are on the CDB4272 eval board? 10uF.I smell mistakes in the datasheet.What do you think? I think I should maybe ask the support from Cirrus.

author: jonpaul
author_rank: Super Contributor
timestamp: January 28, 2024, 01:18:36 pm
content: data sheet is fine on power/ground, std practice.See similar parts from TI, ADI, AKM, ST, etc.Pay attention to the PCB layout, pours, spacing, star ground.See Henry OTT Noise Reduction Techniquesj

author: Yansi
author_rank: Super Contributor
timestamp: January 28, 2024, 02:19:46 pm
content: Datasheet provides contradictory or wrong information. Please read above, carefully.I am not sure, if it is a standard practice to require designer to limit a capacitance to a specific value of 1 uF and then provide customers with an evaluation board, that has 10 uF capacitor instead.CS4272 Datasheet is extremely vague explaining what each supply pin powers. Other Cirrus converters from the same series use VD to define logic levels on some digital IO pins (SPI/I2C control interface), and VL on other digital IO pins (serial audio). I find it then strange this part is documented in a way this is not fully clear what can be powered from where.

author: Someone
author_rank: Super Contributor
timestamp: January 28, 2024, 07:58:39 pm
content: Quote from: Yansi on January 28, 2024, 02:19:46 pmThe data sheet is typical, and correct. Immediately blaming it when you are inexperienced and do not understand is not going to make friends.

author: Yansi
author_rank: Super Contributor
timestamp: January 29, 2024, 11:13:25 am
content: The only not making friend is you making your useless comments to just bump up your post counter. Finally decided to report you.

author: Halcyon
author_rank: Unknown
timestamp: January 29, 2024, 11:17:36 am
content: Quote from: Yansi on January 29, 2024, 11:13:25 amFree speech applies on this forum, just as it applies in Australia. We're not here to remove comments just because someone disagrees or have their feelings hurt by them. Only in extreme cases do we start getting involved.

author: Yansi
author_rank: Super Contributor
timestamp: January 31, 2024, 08:16:07 pm
content: Nobody said comments shall be removed. Certainly not me. So who did?

author: jonpaul
author_rank: Super Contributor
timestamp: February 01, 2024, 11:20:51 am
content: Halcyon, many thanks for the intervention!Besides free and open discussion, It is professional courtesy and mutual respect of the other's notes and feeling.More and more lack of respect.Jon

author: dmills
author_rank: Super Contributor
timestamp: February 01, 2024, 01:50:00 pm
content: Going back to your input level calculations and circuit, if you are going for 0dBu nominal, I would like to see clipping at about +18 to +20dBu (7.75V RMS 11V peak), so your input stage gain would want to be about -12 to -14.8dB. And yes, audio is that dynamic, good gear leaves at lest 18dB between nominal and peak, and 20 or even 24dB is not unheard of.In reality the noise floor of a modern ADC is so far below that of even a decent room that leaving headroom to avoid any real chance of clipping is not going to compromise performance in a meaningful way, clipping however sucks.The 10k resistors will add potentially significant Johnson noise so I would be staying with the low input Z and adding a pair of unity gain buffers if required to raise the input impedance and massively raise the common mode impedance, any decent dual opamp (LM4562, 5534 whatever) will have much lower noise then a 10k resistor in the audio band, so adding the chip and using low value resistors will significantly lower the noise.

author: Yansi
author_rank: Super Contributor
timestamp: February 03, 2024, 07:14:55 pm
content: Thank youdmillsfor your insight, the signal level info was exactly what I wanted to know. Unfortunately I do not have much practical experience building any professional audio gear that would include any digital processing, so this is a first.I have just finished assembling and making first tests on my own "CS4272 eval board". Simply, because the original one costs nonsense and includes functionality one is not interested in (and archaic PC interfaces like LPT port... come on, Cirrus guys, update yo stuff!)The frontend was calculated to accept +12 dBu at full scale (so 12 dB of headroom against nominal). If you say it is more practical and useful to increase headroom to 18 dB, I can easily change the values there. But still afraid of getting extra 6 dB closer to noisefloorYou are right about the noise, however I do not think this will be a real trouble or a bottleneck, as it will be a part of active PA speaker (so right at the end of signal chain), so the noise contribution compared to the class D amp will likely be negligible. I have a Douglas Self's book, there's a lot to learn on low noise input design.And the analog mixing desk, that will be feeding it, will likely itself have a noisefloor way above the simple frontend beginning with 10k resistors. But I agree, it is a kind of excuseSee photos below what I did. Everything seems working about fine now, only minor issues found (like that I forgot to buy a crystal with correct Cload spec and the one I tried did not want to oscillate)

author: MathWizard
author_rank: Super Contributor
timestamp: February 04, 2024, 09:10:45 am
content: I have an old soundcard to play with, I'm sure it also has some CirrusLogic IC. And I have receiver with lots of DSP chips too. So far I haven't tried the digital stuff on it.I don't know near enough programming to do anything cool, but I know some I2C. My AVR only had a pre-amp for a subwoofer. So right now I have basically have 2 stereo's hooked up with some added circuits, to run 5.1CH's.So besides the SW and it's transformer, I need to get all the rest inside the AVR, which really means I should remake just the sub-driver circuits.

author: adasoj
author_rank: Newbie
timestamp: December 28, 2024, 03:39:48 pm
content: Hey Yansi,That's a really cool proect. I am about to undertake a journey similar to yours, also tinkering with the IC's input and output stages.Would you be willing to share your findings, measurements, etc..?Have a good one,Adam

author: Yansi
author_rank: Super Contributor
timestamp: January 02, 2025, 01:40:18 pm
content: Hello,The board I have designed above, uses only single ended outputs and balanced inputs: First, a differential amplifier is used to get the difference, then a balanced driver/buffer is used. All done using NE5532 opamps.I do not anything past that was reasonable for my application, of just wanting to play with the codec IC for a bit.So far, no measurements on it have been done, only tested for basic functionality, that it works in loopback mode (I2S bus directly looped back from ADC do DAC and via external microcontroller (STM32 NUCLEO) connected to the audio codec board. No issues were found afaik, do not remember fixing anything in the design later.Unfortunately not much time was spend pursuing this project further, as I got other higher priority work to do. I plan to return to this in spring this year. If you have any further questions re the design, pls send me a PM, I could even possibly share the PCB with you.