Is it safe to connect inputs to VCC directly - Page 1
Forum section: electronics / projects

author: ataradov
author_rank: Super Contributor
timestamp: February 04, 2020, 03:56:01 am
content: Ok, I did some searching and I can't find a good definitive answer.Is it safe to connect to inputs of the 74-series CMOS logic directly to VCC instead of using pull-ups? What are realistic pros and cons?I'm not interested in what may happen if device fails catastrophically and the input becomes an output and stuff like that. I'm only interested in normal operation.I'm also not interested in TTL logic. The devices will never be substituted on accident. Seriously, some people still make this argument.I guess the question may be rephrased as: are there realistic use cases where it is not safe to connect inputs directly to VCC?

author: EEEnthusiast
author_rank: Frequent Contributor
timestamp: February 04, 2020, 04:08:58 am
content: Direct shorting of inputs to Vcc or Ground can lead to latchup in some CMOS families. It is always safe to use some pull-up to limit this current.

author: ataradov
author_rank: Super Contributor
timestamp: February 04, 2020, 04:14:00 am
content: What are "some". I see things like this said a lot, but no concrete evidence or an actual description of the process of that latch up.Plus I have never seen anyone use pull-down resistors, except for some flight-critical avionics, but they do this stuff there because of very-very old standards.

author: digsys
author_rank: Unknown
timestamp: February 04, 2020, 04:18:17 am
content: I've probably done it several 100+ times, over ~35yrs, and I've seen it done in 100s devices. In my cases, I've never seen latch-ups. As long as the Vcc lines are clean (nicely decoupled), I doubt you'll ever see a problem

author: james_s
author_rank: Super Contributor
timestamp: February 04, 2020, 05:53:51 am
content: I've seen it lots of times too and done it in some of my own projects, never saw a problem anywhere.

author: obiwanjacobi
author_rank: Super Contributor
timestamp: February 04, 2020, 06:27:59 am
content: The only reason I always use pullups is because I can remove them if I need the gate to botch a problem."Know your limitations"

author: TimFox
author_rank: Super Contributor
timestamp: February 04, 2020, 08:56:45 pm
content: Connecting inactive inputs to ground or Vcc through appropriate resistors allows testing the IC in-circuit by driving the input from a “stiff” test voltage on a test jig. This is part of design-for-test process.

author: ataradov
author_rank: Super Contributor
timestamp: February 04, 2020, 09:00:40 pm
content: Quote from: TimFox on February 04, 2020, 08:56:45 pmThis argument is just strange. Why would you ever want to override an input, which value is fixed at the design stage? What are you testing here exactly?Why don't you decouple the inputs that are driven by other outputs? So you could override those as well for testing?What is so special about pins that must have fixed value?

author: ejeffrey
author_rank: Super Contributor
timestamp: February 04, 2020, 09:15:58 pm
content: On a straight 74 series CMOS logic? No, just connect to Vcc. On a more complicated IC like an MCU There are lots of reasons you might not want to: ease of rework / modification, that the pins might have some use during function test, or to prevent excess current if the pin is accidentally switched to an output. But these are all unlikely to apply on a simple logic chip, and only really apply for R&D prototypes anyway. On anything you make a second time, those resistors are just a waste of space and another thing to go wrong.

author: wraper
author_rank: Unknown
timestamp: February 04, 2020, 09:35:29 pm
content: Quote from: EEEnthusiast on February 04, 2020, 04:08:58 amHow resistor is supposed to limit current through MOSFET gates when latch-up does not even cause current flowing through them?

author: TomS_
author_rank: Frequent Contributor
timestamp: February 04, 2020, 10:07:12 pm
content: I asked about this some time ago and got some reasonably good answers:https://www.eevblog.com/forum/projects/pull-up-resistors-technically-necessary-vs-preference/msg1699586/Short answer: I dont bother with pull up/down resistors any more except when I might need to override a signal.

author: tggzzz
author_rank: Super Contributor
timestamp: February 04, 2020, 10:08:51 pm
content: Quote from: ataradov on February 04, 2020, 09:00:40 pmNot testing the design; that was done earlier.Testing thatthis instanceof the design has been manufactured correctly, e.g. components inserted correctly, no short circuits etc. That requires a completely different set of tests.

author: tkamiya
author_rank: Super Contributor
timestamp: February 04, 2020, 10:32:47 pm
content: The idea is, you don't want input of a CMOS gate floating around. You can tie it to ground, VCC, via or without registers. Just make sure the voltage you tie to is equal to or less than power to the chip. I usually tie to VCC or ground, whichever is closer.

author: David Hess
author_rank: Super Contributor
timestamp: February 04, 2020, 11:12:36 pm
content: If multiple Vcc supplies are used then that would be a good reason to use series input resistors to limit the current but in the common case, I do not know of any reason the input cannot be directly connected to either power rail.Early TTL is a special case because of its common base multiple emitter input structure which required series resistors if an input was pulled up to Vcc.Quote from: wraper on February 04, 2020, 09:35:29 pmIt does not have anything to do with the gate; it is insulating after all. Latchup occurs when carriers are injected into the substrate and they activate the parasitic SCR structure present in a junction isolated CMOS process. This can happen if the input or output ESD protection diodes are forward biased with enough current.I have personally witnessed it a few times when static jumped between a finger and a CMOS logic board and one CMOS IC became an SCR crowbar across the power supply.

author: MarkF
author_rank: Super Contributor
timestamp: February 04, 2020, 11:28:30 pm
content: Very very old...

author: ataradov
author_rank: Super Contributor
timestamp: February 04, 2020, 11:29:24 pm
content: But what does SCR latch-up has to do with connecting inputs to the VCC directly?

author: wraper
author_rank: Unknown
timestamp: February 04, 2020, 11:40:36 pm
content: Quote from: David Hess on February 04, 2020, 11:12:36 pmExactly, you need to bring terminals above Vdd or below GND. Direct input connection to the power rail actually prevents it. So I don't get what current is supposed to be limited by using resistor instead of direct connection. Certainly not current which flows through IC when latch-up already happened.

author: tkamiya
author_rank: Super Contributor
timestamp: February 04, 2020, 11:45:59 pm
content: And..... Why do input of TTL logic gate have to be pulled up or down? It is completely safe to just leave it unconnected. At least I've never done it and never seen any one else do it that way. I thought the practice was for ?mos type devices only.

author: james_s
author_rank: Super Contributor
timestamp: February 05, 2020, 12:05:04 am
content: It's just good practice to do so, it can prevent strange problems. A lot of modern "TTL" stuff is actually CMOS.

author: wraper
author_rank: Unknown
timestamp: February 05, 2020, 12:13:40 am
content: Quote from: james_s on February 05, 2020, 12:05:04 amMore like stupid practice how to increase manufacturing costs and problems due to higher component count. Also you reduce noise immunity or robustness against board contamination or tin whiskers. Say CMOS output (connected to input) has much lower impedance than a few k resistor you would use as pull-up.EDIT: It was about adding resistors. Apparently james_s meant connecting to power rail.QuoteHaven't seen anything claiming to be TTL. There might be written something like TTL voltage level.

author: MasterT
author_rank: Frequent Contributor
timestamp: February 05, 2020, 12:30:02 am
content: Quote from: ataradov on February 04, 2020, 11:29:24 pmIn normal condition doesn't matter if there is a resistor installed or not. But a good designer have to predict all abnormal situation as well, like:1. over-voltage to the IC2. ESD discharge3. current injection to/from neighboring inputs/ outputs that may get signal from other modules/ boards etc.4. power pin connection loss5. strong RF pulse - EMP warfare.Inputs are not designed to pass much current, so there is "probability" latching-up, and it's easier to install a resistor than estimate 12-20 inputs/outputs interference to each other .

author: iMo
author_rank: Super Contributor
timestamp: February 05, 2020, 12:31:11 am
content: It is a good practice, originated in times where a 2 layer pcb board was 40x80cm large with 500 DIL14/16 chips on it. On such a board with a dozen of XXcm long parallel straight Vcc and Gnd rails, following the never ending rows of DIL sockets, the term "connected directly to Vcc or Gnd" may not always mean "connected directly to Vcc or Gnd"..

author: ataradov
author_rank: Super Contributor
timestamp: February 05, 2020, 12:34:37 am
content: As I said, I'm not interested in catastrophic failures. If there is over-voltage or power pin connection loss, then device is broken. It does not really matter what happens after that.I don't buy this "good designer" stuff.I see this matter for aerospace or military applications, but there you have to think about much more than just a simple pull-up.

author: wraper
author_rank: Unknown
timestamp: February 05, 2020, 12:38:50 am
content: Quote from: MasterT on February 05, 2020, 12:30:02 amAgain, please explain how MOSFET gates tied to Vdd/Vss are supposed to pass any current. Latch-up does not result in current passing through the gates.

author: iMo
author_rank: Super Contributor
timestamp: February 05, 2020, 12:45:20 am
content: Quote from: wraper on February 05, 2020, 12:38:50 amHave you ever seen how a CMOS input looks like?

author: wraper
author_rank: Unknown
timestamp: February 05, 2020, 12:58:41 am
content: Quote from: imo on February 05, 2020, 12:45:20 amYes I did and it's a non answer.

author: MasterT
author_rank: Frequent Contributor
timestamp: February 05, 2020, 01:08:56 am
content: Quote from: ataradov on February 05, 2020, 12:34:37 amFailures happen all the time. It's saving on resistors what makes them catastrophic. Cellular towers and mobile phones all around us, no need to be in aerospace.

author: wraper
author_rank: Unknown
timestamp: February 05, 2020, 01:13:55 am
content: Quote from: MasterT on February 05, 2020, 01:08:56 amIt's like saying saving on fur coat could make your life catastrophic. But I doubt it will make your life safer if you live in tropical forest. What I mean is that you should use stuff for a reason and I don't see how dumbly sprinkling resistors over unused inputs is supposed to make anything better.QuoteAnd in that case you better tie things hard with low impedance paths instead of using resistors which cannot quench RF interference.

author: MasterT
author_rank: Frequent Contributor
timestamp: February 05, 2020, 01:21:26 am
content: Quote from: wraper on February 05, 2020, 12:38:50 amI 'd refer to TI - White PaperSCAA124 – April 2015Latch-UpMarty Johnson, Roger Cline, Scott Ward, Joe SchichlQuoteIn short, there is certain "design rules".

author: wraper
author_rank: Unknown
timestamp: February 05, 2020, 01:32:40 am
content: Quote from: MasterT on February 05, 2020, 01:21:26 amYou forgot to mention that in only happens when there is intentionally made SCR structure on inputs for ESD protection.

author: MasterT
author_rank: Frequent Contributor
timestamp: February 05, 2020, 01:51:27 am
content: Quote from: wraper on February 05, 2020, 01:13:55 amI'd not be so sure about 5 GHz, that connecting pin - essentially small piece of antenna, to ground is more safe. Another end may have 1/4 length to be hardly energized.I can't comment what kind of SCR is in use nowadays, last time I seen CMOS in X-ray in 90-th. But my understanding, since human body doesn't change much since than, has same charge capacity and lethal for CMOS energy, the same time size of components (MOSFET, shottky diodes ) shrink substantially, means that simple diode-R-diode chain may not be enough to satisfy same ESD standard. So, manufacturers have to incorporate much more sophisticate protection, SCR or whatever.

author: james_s
author_rank: Super Contributor
timestamp: February 05, 2020, 02:25:25 am
content: Quote from: wraper on February 05, 2020, 12:13:40 amHow does tying unused inputs to Vcc or ground increase manufacturing cost and increase component count?

author: Miti
author_rank: Super Contributor
timestamp: February 05, 2020, 02:33:21 am
content: Quote from: ataradov on February 04, 2020, 09:00:40 pmTo kill a clock so the MCU doesn't start running the code. To keep an MCU in reset or otherwise it would interfere with your ICT or boundary scan. To pull up a "test enable" pin to put a JTAG compatible device in... well... test mode.This is a strong requirement in our DFT guidelines.

author: ataradov
author_rank: Super Contributor
timestamp: February 05, 2020, 02:37:45 am
content: Quote from: Miti on February 05, 2020, 02:33:21 amThose are provisions for dedicated pins. I'm not arguing with that.I'm asking specifically about single 74-series gates. Let's say I use 4-NAND and I only need 3 inputs. All I need is to force one other input to be always high. Any testing like that should happen through other 3 pins. This extra pin carries no function in the design. Unless you assign it a function to be a test input.

author: wraper
author_rank: Unknown
timestamp: February 05, 2020, 02:40:03 am
content: Quote from: james_s on February 05, 2020, 02:25:25 amI thought you meant adding resistors as good practice.

author: tkamiya
author_rank: Super Contributor
timestamp: February 05, 2020, 02:55:19 am
content: QuoteNow I am genuinely interested in finding more. Taken literally, you are saying 74LSxxxx are actually CMOS with TTL interface. I am not finding anything on this. Will you please give me an example device so I can further research this? I have not seen anything like this.

author: oPossum
author_rank: Super Contributor
timestamp: February 05, 2020, 03:04:12 am
content: 74HCT and 74AHCT are CMOS with TTL thresholds

author: tkamiya
author_rank: Super Contributor
timestamp: February 05, 2020, 03:10:04 am
content: Oh, OK. That I knew. I thought you guys were talking about 74LSxxxx series being redesigned as quasi TTL.

author: Miti
author_rank: Super Contributor
timestamp: February 05, 2020, 03:19:41 am
content: Quote from: ataradov on February 05, 2020, 02:37:45 amYes, our customers with good design experience do this all the time, pulling input pins directly to GND or Vcc, even dedicated pins. Many that didn't design-for-test before, have an eureka moment when we ask them to add pullup/dn resistors in our DFT reports.

author: tkamiya
author_rank: Super Contributor
timestamp: February 05, 2020, 03:40:18 am
content: We've been talking about resisters. Like what values? Normal pull up like 470 ohm to 10K ohm range? And the "test" that has been referred to, they are extreme tests like overlaying KV pulse on power line, etc, or zap the input with huge noise. Right? We are not talking about normal usage in office.

author: David Hess
author_rank: Super Contributor
timestamp: February 05, 2020, 03:49:26 am
content: Quote from: ataradov on February 04, 2020, 11:29:24 pmIf you had more than one Vcc supply, which used to be more common, and the input was connected to the other one, then power supply sequencing could cause SCR latch-up. Now this would be more likely to happen at the interface between different voltage domains.Quote from: tkamiya on February 04, 2020, 11:45:59 pmSome parts in the later bipolar TTL families, I think the ones built on complementary bipolar processes so some AS and FAST parts at least, had buffered inputs and present a much higher impedance to the input making them susceptible to capacitive coupling into an unconnected input. I would not put it past having the same problem with advanced low-power schottky or even low-power schottky parts.

author: tkamiya
author_rank: Super Contributor
timestamp: February 05, 2020, 03:57:40 am
content: Thank you. Learned something new today. It was a simpler time when chip was made by Texas Instruments and started with 74, it was always TTL, and if the chip was made by Motorola and started with 4, it was always CMOS. Yes, I'm that old....

author: aix
author_rank: Regular Contributor
timestamp: February 05, 2020, 06:25:54 am
content: Quote from: ataradov on February 05, 2020, 02:37:45 amI do realise that your question is broader than this. However, this particular example got me wondering: to get 3-NAND from 4-NAND, what are the pros and cons of tying one input high vs tying two of the four inputs together.

author: ataradov
author_rank: Super Contributor
timestamp: February 05, 2020, 06:56:57 am
content: Quote from: aix on February 05, 2020, 06:25:54 amI have no idea. I don't think there is a significant difference. Intuition tells me that having one input fixed is better, it avoids one more thing changing, but I don't know for sure.In this case question came up for XOR gates, so no way to tie things together.

author: tggzzz
author_rank: Super Contributor
timestamp: February 05, 2020, 08:23:56 am
content: Quote from: ataradov on February 05, 2020, 02:37:45 amAnd that's an example of the problems caused by omitting context. You did write. (with myemphasis)...Quote from: ataradov on February 04, 2020, 09:00:40 pm

author: ataradov
author_rank: Super Contributor
timestamp: February 05, 2020, 08:28:18 am
content: Quote from: tggzzz on February 05, 2020, 08:23:56 amThere is a difference between the pin that must normally be held high when not in use, like programming and test pins, and a pin that is absolutely never needs to be overridden, like that 4th unused input on a 4-NAND gate.Nobody tries to override random parts of the circuit "for testing". That's just nonsense.

author: tggzzz
author_rank: Super Contributor
timestamp: February 05, 2020, 08:30:31 am
content: Quote from: ataradov on February 05, 2020, 06:56:57 amIn some cases the extra load capacitance might be an issue.

author: David Hess
author_rank: Super Contributor
timestamp: February 05, 2020, 10:42:40 am
content: Quote from: aix on February 05, 2020, 06:25:54 amExcept for edge cases where doubling the capacitance and leakage matter, you can always do that and it is even the recommended method for TTL where it does not even increase the fan-in of a single gate.

author: iMo
author_rank: Super Contributor
timestamp: February 05, 2020, 11:29:02 am
content: As indicated by above posters - connecting a CMOS input "directly to Vcc or Gnd" of the SAME chip is safe.What could be an issue - and that is what the people try to indicate above - is when somebody "thinks the CMOS input is connected directly to the Vcc or Gnd" (mind the word "directly"), but in reality:a) the wire is rather long - it pickups transients from its surroundingb) the Vcc or Gnd potential (at the point of connection) is DC biased (ie a voltage drop on Vcc or Gnd rails) against the Vcc or Gnd at the CMOS chipc) the Vcc voltage at the CMOS chip vs. the voltage at the point of connection differ during powerupd) the Vcc voltage at the CMOS chip vs. the voltage at the point of connection is noisy..etc.In those cases there could be a peak current flowing through the first two (upper or lower) clamping diodes (the input of a CMOS logic gate consists typically of 2 diodes - 1 resistor - 2 diodes) and the excessive current may cause some issues in the silicon of that CMOS chip. As I wrote above in past the "connection points" where the unused inputs were connected to were sometimes "far away" of the actual CMOS chip, and/or were connected to different Vcc and Gnd power rails. Thus adding a resistor close to the CMOS input pin helped to limit those spurious current peaks.

author: Siwastaja
author_rank: Super Contributor
timestamp: February 05, 2020, 12:02:07 pm
content: Quote from: wraper on February 05, 2020, 12:38:50 amIt's the case of the inputs being connected to adifferentVdd, with wrong power-up sequencing.Some logic IC families specify in the datasheet that they are safe against inputting voltages on unpowered chip. That's an actual marketing argument.Needless to say, this does not apply to most use cases, including the OP's.

author: wraper
author_rank: Unknown
timestamp: February 05, 2020, 12:57:47 pm
content: Quote from: Siwastaja on February 05, 2020, 12:02:07 pmIt's a completely different case from what was asked, doing so is simply stupid and those who do this should be burned on stake.

author: Siwastaja
author_rank: Super Contributor
timestamp: February 05, 2020, 01:47:55 pm
content: Most of the "best practice" bullshit is based on mental copy-paste of something that usually is not related to the actual problem, often not even close, and given some engineering discipline, the disconnection is trivial to see.It's a colossally bad idea to add random components because someone somewhere thinks that they are necessary in a completely different circuit, and to call that "good practice" is disgrace. Engineering just isn't that simple. Understanding the circuit is paramount.

author: tkamiya
author_rank: Super Contributor
timestamp: February 05, 2020, 01:50:45 pm
content: imo,That's a bunch of obvious but good points. I think most folks (me too) do this without thinking. Pick the closest low impedance (ie. power) point. But taken literally, nothing stops folks from just daisy chaining empty input pins and just ground or pull up at one point. That would be problematic.

author: MasterT
author_rank: Frequent Contributor
timestamp: February 05, 2020, 01:51:48 pm
content: If I asked, is it safe to apply 5.5V? Everyone would say, yes, DS specifies acceptable voltage level. But reliability numbers would fall from 10^-7 to 10^-6 or like that. So, from reliability point of view, increasing voltage (or using safety resistors) should be considered based on Acceptable failure rates. And this strongly depends on a market, cost of device, and things that difficult to estimate - brand name ratings. Nobody would care if led-blinking toy breaks down, OTOH, if a scope failed because someone save on single resistor - would you buy another one from this maker?

author: Siwastaja
author_rank: Super Contributor
timestamp: February 05, 2020, 01:56:46 pm
content: Quote from: MasterT on February 05, 2020, 01:51:48 pmWhat does this comment has to do with this topic, though?And what the heck is a "safety resistor"?Do note that sprinkling resistors randomly without a reason won't increase reliability, and if they are in series with actual nets (instead of, say, on the side of the board unconnected), each resistor slightly decreases the reliability (not by much, of course). I would expect the scope manufacturer to only design in resistors that are needed or do good for the circuit, and don't put in any excess.

author: TimFox
author_rank: Super Contributor
timestamp: February 05, 2020, 02:06:46 pm
content: The specific reason to add (small) resistors at inactive input pins is to allow testing the device after it is soldered in the circuit. It is a reasonable design rule. By inactive, I mean inputs (e.g., enables) that are not exercised in operation.

author: Wimberleytech
author_rank: Super Contributor
timestamp: February 05, 2020, 02:44:07 pm
content: Quote from: ataradov on February 04, 2020, 03:56:01 amMy answer is: Other than for reasons of testing, there is norealisticuse case for using a resistor pullup (versus a direct connection) to VCC.I read this thread before answering. The testing idea was not something I thought of, but it is an interesting idea. For production, you would not want to waste lots of resistors for testing features used only during qualification and/or debug.

author: thinkfat
author_rank: Unknown
timestamp: February 05, 2020, 03:03:57 pm
content: Quote from: Wimberleytech on February 05, 2020, 02:44:07 pmUnless you're really space-constrained, is it really an issue to have a couple of additional resistors sprinkled onto the board? Especially if they're not introducing another unique BOM item.

author: 741
author_rank: Frequent Contributor
timestamp: February 05, 2020, 03:08:55 pm
content: Here is a similar threadhttps://www.eevblog.com/forum/projects/is-it-ok-to-directly-tie-logic-inputs-to-vdd/

author: MasterT
author_rank: Frequent Contributor
timestamp: February 05, 2020, 03:20:13 pm
content: Quote from: Siwastaja on February 05, 2020, 01:56:46 pmMay be won't. Since you don't provide specific numbers to estimate reliability, and me nether, what I'm trying to say is that question has no sense w/o strictly confidential manufacturer's reliability report for specific part number. How much failure rate goes up if not follow to recommended design rules.OP says, that doesn't need a highest military/ aerospace reliability marks. But consumer product is also demands reliability numbers not equal to zero.

author: TimFox
author_rank: Super Contributor
timestamp: February 05, 2020, 06:26:03 pm
content: This question probably arises because of a real feature of original 7400-series TTL, which wasactualTTL, using a multiple emitter input transistor instead of DTL diodes to do logic. The breakdown voltage of the input structure was less than the smoke level of the rest of the circuit. Therefore, with a direct pull-up to Vic, there was an unnecessary risk of damage if Vcc overshot on power-on. The situation is different with later bipolar and CMOS families.

author: Wimberleytech
author_rank: Super Contributor
timestamp: February 05, 2020, 07:03:36 pm
content: Quote from: thinkfat on February 05, 2020, 03:03:57 pmA couple? No big deal. Ten? Dunno. This boils down to designer's choices really. There is no "correct" answer I suppose.

author: wraper
author_rank: Unknown
timestamp: February 05, 2020, 07:12:58 pm
content: Quote from: thinkfat on February 05, 2020, 03:03:57 pmAdding parts "just because" without any understanding or measurable evidence of any benefits is not a good design practice IMHO. Over-engineer here and there and result is simply worse, as minimum because of larger size and manufacturing price.

author: wraper
author_rank: Unknown
timestamp: February 05, 2020, 07:15:51 pm
content: Quote from: Wimberleytech on February 05, 2020, 07:03:36 pmIMHO the correct answer is what isn't needed shouldn't be there. You'd better add some real ESD protection where it might help instead of sprinkling useless resistors.

author: Siwastaja
author_rank: Super Contributor
timestamp: February 12, 2020, 09:39:21 am
content: Oh, there certainly is a correct answer. Except for some very specific cases for testing (then the designed would know what they need!), no one has provided any pointer for what the resistors are supposed to do in the circuit. If no such mechanism cannot be shown at all; even speculated; the correct answer is clear as day.

author: graybeard
author_rank: Frequent Contributor
timestamp: February 12, 2020, 11:43:23 am
content: Quote from: ataradov on February 04, 2020, 11:29:24 pmnothing

author: graybeard
author_rank: Frequent Contributor
timestamp: February 12, 2020, 11:46:45 am
content: It is fine for CMOS to connect logic inputs to the chip power supply VCC.