Schmitt trigger or pull-up/pull-down? - Page 1
Forum section: electronics / beginners

author: nForce
author_rank: Frequent Contributor
timestamp: November 03, 2018, 07:14:06 pm
content: I don't understand for debouncing the pin on the MCU is it used Schmitt trigger or pull up/pull down resistors?Or is it both, and something is not used for debouncing, rather it has other functionality?Thanks.

author: rstofer
author_rank: Super Contributor
timestamp: November 03, 2018, 08:30:47 pm
content: The pull-up and pull-down resistors provide a current path such that there is some current passing through closed switch contacts. This has nothing to do with the Schmitt Trigger that may also be present.There is a potential problem with internal pull-up resistors in that they may not pass enough current to get a good connection with some types of toggle switches. It is not unusual to add external resistors down around 1k or so. Sometimes it is helpful to use the internal pull-up or pull-down resistors to establish a voltage on an unused inputs. CMOS doesn't really like floating inputs. In the old days this was a clear way to smoke chips - leave an unused input just floating.The Schmitt Trigger has asymmetric switching thresholds spread much wider than normal logic inputs. It doesn't really help with contact bounce but it does help clean up input signals in terms of their switching levels. The ST doesn't fix everything but it is definitely better than a standard CMOS input design.

author: nForce
author_rank: Frequent Contributor
timestamp: November 04, 2018, 11:12:24 am
content: So floating means that the pin on the MCU is not zero nor one?You said we can destroy a chip if the input is floating. Why so? A lot of schematics using MCU does not connect external circuitry to all of the pins of the MCU.What are we then using for debouncing?

author: Zero999
author_rank: Super Contributor
timestamp: November 04, 2018, 07:56:59 pm
content: Leaving a pin floating can cause it to pick up stray fields and make it much more vulnerable to ESD. Another issue is, if the pin's voltage sits at half the supply voltage, both the transistors inside the CMOS gate will turn on simultaneously, causing excessive current draw. Modern MCUs are generally well protected against ESD and are much less vulnerable to this sort of abuse, but it's still a good idea to avoid it. Unused pins can also be configured as outputs or inputs with internal pull-ups, to avoid adding lots of external resistors.

author: Bassman59
author_rank: Super Contributor
timestamp: November 05, 2018, 04:18:30 am
content: Quote from: nForce on November 04, 2018, 11:12:24 amIt means that the input is "undefined." Read the data sheets, they will tell you the logic thresholds for your chip. You must ensure that your input voltage is above the logic-hi threshold to be recognized properly as a high, and below the logic-low threshold to be recognized as a low.QuoteWhen a CMOS logic input is left open and the input floats, that input may be in the "undefined" range between valid logic levels. A logic gate is really a high-gain saturating amplifier (meaning its output "saturates" to one of the rails), and when the input is in that undefined range, the amplifier may toggle very rapidly between the two rails, likely exceeding the gate's actual maximum switching frequency, and the amplifier gets hot and dies.QuoteSpecifically to prevent that death described above, MCUs (and FPGAs, too) have internal "weak" pull-ups (and/or pull-downs) to ensure a valid logic level when the input is not connected (and the chip's I/O pins are set up as inputs). A weak pull-up is easily overdriven by valid logic levels.But the thing is with a weak pull-up is that when an open-collector driver connected to that input turns off its driver, so the logic level can pull up to high, that turn-off time, and thus the time for the signal to go high, can be very slow. So it's always recommended to use a properly-sized pull-up resistor for these applications. Lower-value pull-up resistor means faster time to pull high, while minding that you must ensure that the driver can pull down to a valid low logic level. For 5V logic it was common to see 4.7k or 5.1k resistors; for 3.3 V logic often a 2.2k resistor is used. The exact value isn't that important.QuoteWhen we use push-button or other SPST switches in logic circuits, usually we tie one leg of the switch to ground, and the other leg is tied to our logic circuit (MCU, perhaps) and also pulled up to the logic supply rail. In the normally-open position, the switch is open so the pull-up resistor establishes a logic high at the micro. When you push the button, the switch closes, and connects the MCU pin to ground. Release the switch and the pull-up resistor again establishes logic high, and just like the open-collector circuit I mention above, the time to go to that high level depends on the resistor value.------As for using a Schmitt trigger input: standard logic inputs have symmetric logic thresholds. For example, common CMOS logic inputs are high when the voltage is at or above ⅔ the supply rail, and they are low when they are at or below ⅓ the supply rail. It is assumed that a logic input will be driven from a logic output -- one that switches "Fast" and spends very little time in the undefined middle region.But what happens if the logic input is not driven by a logic output, and instead does weird things like bounce around a logic threshold voltage before settling? The output of the standard logic gate will chatter and do weird things. This is where the Schmitt trigger's asymmetric logic thresholds come in. There is hysteresis on the logic input, and the gate is guaranteed to not switch between the thresholds. That is, once the input signal is recognized as logic high (going above the high threshold), the output signal will not go low or undefined if it goes below the high threshold. The signal must go all the way down to below the low threshold before the output switches.