Sequences in an FPGA - Page 1
Forum section: electronics / beginners

author: jnz
author_rank: Frequent Contributor
timestamp: October 25, 2017, 11:12:38 pm
content: Ok, so FPGAs don't run on software, they unroll their loops, you're describing hardware, all your block code is executed at once...So what is the right way tothink aboutimplementing a wave sequence like UART or SPI or CAN or whatever.If I have a FSM, and I want to output a sequence of high and low at for a duration x clock edges, what does that look like? But more importantly, how do you think about that when designing your block?Or does the question not make sense?

author: tggzzz
author_rank: Super Contributor
timestamp: October 25, 2017, 11:21:18 pm
content: Quote from: jnz on October 25, 2017, 11:12:38 pmAs a beginner, you should draw the FSM first, using circles to represent states (i.e. the contents of a register) and directed lines showing the events (i.e inputs or conditions) that lead to transitions between states.Google for Harel Statecharts.

author: ataradov
author_rank: Super Contributor
timestamp: October 25, 2017, 11:39:18 pm
content: Just draw an actual schematic with registers and combinatorial logic between them. You don't need to draw all the details, of course, but you need to get all major things drafted.Also, get a good (whatever it means for you) simulation software and check the results often. I personally use iverilog + GTKWave, but FPGA vendor tools may work as well, they are just painfully slow.And for complex stuff, drawing actual state machines is very helpful.

author: rstofer
author_rank: Super Contributor
timestamp: October 26, 2017, 01:16:20 pm
content: Let's assume you have a clock that is properly related to the output waveform frequency - one tick of the clock, one transition on the output.You enter a state and set a signal output. Then you enter another state and, perhaps, reset the signal output. If you need a wider pulse, you might have two or more states where the output doesn't change.Sometimes you want to hang in a state for a relatively long period of time. Just use one state to start a counter and branch to another state where you hang until the count reaches some value. Then branch to a 3rd state.There are two ways that FSMs can be written. I use two processes: The first is a clocked process that does nothing more than set 'currentstate <= nextstate' (at reset it does 'currentstate <= firststate'). The second is a combinatorial process that has all the logic and generates the outputs for each state. Among other things, it sets the value of 'nextstate' for the state transition at the next clock.The other way to code them is to have just one clocked process. I have only used this approach once so I don't know if there are any advantages. There is certainly a difference in timing but I haven't thought through whether it matters.In the combinatorial process, right after 'begin' and before the 'case' statement, you need to define the default value for every output of the process. If you don't, you will infer latches and I can just about guarantee the logic won't work. The alternative, too ugly to contemplate, is to define the value of every output in every state. Somehow, that doesn't seem reasonable if you have dozens of outputs.Here is an overview of the LC3 RISC CPU project which seems popular at a number of universities:https://classes.soe.ucsc.edu/cmpe012/Winter09/lectures/03_LC3_Architecture.pdfHere is the state machine diagramhttp://highered.mheducation.com/sites/dl/free/0072467509/104691/pat67509_appc.pdfA page with all the appendices:http://highered.mheducation.com/sites/0072467509/student_view0/appendices_a__b__c__d____e.htmlYou can find other resources for LC3 on the Internet. The nice thing about the project is that it comes with a simulator (I have never used it), an assembler and a C compiler. The C compiler is a port of LCC, a reconfigurable C compiler you can use with most any processor by just changing some tables in the code generation section. I haven't done this nor do I believe it to be trivial."Introduction To Computing Systems" Patt and Patel - if I could have just one book on computer science, programming, architecture and everything else related to CS, this would be it. It is the source of the LC3 project.https://www.amazon.com/Introduction-Computing-Systems-Gates-Beyond/dp/0072467509/ref=sr_1_1OTOH, if I wanted to see a MIPS processor and all the SystemVerilog and VHDL code, "Digital Design and Computer Architecture" by Harris and Harris would be the one.https://www.amazon.com/Digital-Design-Computer-Architecture-Second/dp/0123944244/ref=sr_1_1This book looks interesting:https://www.amazon.com/Digital-Design-Computer-Architecture-ARM/dp/0128000562/ref=sr_1_2

author: rstofer
author_rank: Super Contributor
timestamp: October 26, 2017, 03:33:02 pm
content: If you look at State 21 (lower right) in the state diagram I linked above (PDF page 4), you will see, all in one place, the essence of HDLs.PC <= PC+off11;R7 <= PC;Both of these statements execute in parallel at the next clock. The EXISTING value of PC goes into R7 on the very same clock edge as the PC is updated by the offset field in the instruction. At a lower level of detail, it must be true that the data at the output of the PC register doesn't change so fast after the clock edge that it influences the setup time for R7.It is considered poor practice to gate a clock signal. As a result, EVERY clocked element (register or flip flop) sees every clock pulse - all at essentially the same time. There is some clock skew across the device but the tool takes care of that (if possible). In effect, we control the enable signal, not the clock itself.How does State 21 really work? See the block diagram on Page 6. We gate PC onto the bus, we select DR = 7 and we enable LD.Reg. The clock was already going to the register stack anyway. So, when the clock comes along, R7 <= PC.Simultaneously, we set up Addr1Mux to select the PC input and the Addr2Mux to select SEXT(10:0). The Adder combines the terms to form PC + off11 (the sign extended offset field in the instruction register). We then select the adder output on PCMux and set LD.PC. The clock will cause the PC to update.Here's what the state code looks like:Code:when 21 => -- JSR InstructionAddr1Select <= Addr1PC;Addr2Select <= Addr2Sext11;PCselect <= PCadder;LD_PC <= '1';GateBusSelect <= GatePC; -- put current PC on busDRaddrSelect <= DRusesR7; -- and save it in R7LD_REG <= '1';NextState <= 18;

author: rstofer
author_rank: Super Contributor
timestamp: October 26, 2017, 04:52:14 pm
content: As long as I'm on a roll, I'll show you the clock portion of the FSM and the part where I define all the default values in the combinatorial process just before the 'case' statement:Code:-- FSM Next Stateprocess(reset,Pulse,NextState)beginif rising_edge(Pulse) thenif reset = '1' thenState <= 18;elseState <= NextState;end if;end if;end process;-- FSMprocess(State, BEN, IR,MemReady, Immediate, PSR, Interrupt)begin-- set default values for all signalsGateBusSelect <= GatePC;MIOenable <= '0';LD_MAR <= '0';LD_MDR <= '0';LD_IR <= '0';LD_BEN <= '0';LD_PC <= '0';LD_Reg <= '0';LD_CC <= '0';LD_Privilege <= '0';LD_Priority <= '0';LD_PSR <= '0';LD_SavedUSP <= '0';LD_SavedSSP <= '0';LD_VectorAddr <= '0';PCselect <= PCplus1;MARSelect <= MARzext;Addr1Select <= Addr1PC;Addr2Select <= Addr2Zero;SR2select <= SR2OutSel;SR1addrSelect <= SR1usesSR1;ALUop <= ALUpassA;DRaddrSelect <= DRusesDR;MemWr <= '0';SPselect <= SPminusOnesel;VectorMux <= "00";Privilege <= '0';case State iswhen 0 => -- Branch Instruction...The reason the clocked process uses 'Pulse' instead of 'ClkIn' is that I have arranged for a single step clock as well as a 100 MHz clock. Buried in the combinatorial code is 'Pulse <= ClkIn' which is used when I am NOT debugging. Otherwise the single shot component provides the pulse. Gotta be able to single step...In any event there are over 25 signals that need a default value.

author: dmills
author_rank: Super Contributor
timestamp: October 26, 2017, 05:19:47 pm
content: State machines are useful and very commonplace, but do not forget the possibilities of a counter and some decode logic, sometimes particularly for things like UART transmitters this is actually simpler, and sometimes just walking a '1' down a SRL16 (Xilinx specific) is the small way to do this.Lots of ways to skin the cat, but particularly for small sequence detectors, a shift register and some combinatorial stuff is often no bigger then the state machine equivalent while being a ton easier to debug.Special purpose small processors are another fun trick, sometimes something having a small handful of instructions running out of a block ROM can save a lot of low speed logic, stack machines are easy for this (Think Forth).

author: dnwheeler
author_rank: Regular Contributor
timestamp: October 26, 2017, 06:32:16 pm
content: You can always use combinations of these, too. For example, you might have Start, Data, and Stop states, then within the Data state, use a counter to clock out the bits and switch to the Stop state when the counter reaches its limit.

author: tggzzz
author_rank: Super Contributor
timestamp: October 26, 2017, 09:54:04 pm
content: Quote from: dmills on October 26, 2017, 05:19:47 pmThose are state machines. There are many ways to implement state machines.

author: dmills
author_rank: Super Contributor
timestamp: October 26, 2017, 10:32:49 pm
content: Indeed, **ALL** sequential logic is at base a state machine, but usually the academic definition involves rather more explicit feedback then hiding it in a counter.Regards, Dan.

author: tggzzz
author_rank: Super Contributor
timestamp: October 27, 2017, 09:22:45 am
content: Quote from: dmills on October 26, 2017, 10:32:49 pmEr no. "Academic" definitions are usually more abstract than "practical" definitions, and include a wider range of special techniques (e.g using a counter).But that isn't important. What is important isthinking in terms of states and transitionsunderstanding many techniques for implementing states and transitionschoosing whichever implementation technique has the best set of characteristics for your specific set of states and transitions

author: dmills
author_rank: Super Contributor
timestamp: October 27, 2017, 11:36:27 am
content: True when you hit the good literature, but most of the undergrad level books just cover Mealey and Moore machines in any depth and sometimes even fail to consider that a register or a counter are state machines.But yea, you just to got have a toolbox of techniques to choose from and then write whatever makes the most sense.Regards, Dan.

author: jnz
author_rank: Frequent Contributor
timestamp: October 27, 2017, 04:44:34 pm
content: Quote from: dmills on October 27, 2017, 11:36:27 amSuch as?

author: tggzzz
author_rank: Super Contributor
timestamp: October 27, 2017, 04:50:41 pm
content: Quote from: dmills on October 27, 2017, 11:36:27 amEven an isolated simple synchronous counter with carry lookahead, e.g. a 74*163, is a Mealy machine!