JTAG only works when scope is attached - Page 1
Forum section: electronics / projects

author: twam
author_rank: Unknown
timestamp: February 01, 2020, 10:26:05 am
content: Hi everybody,I've got a strange problem (at least for me) and no idea what could be the issue. I'm trying to talk to an ECP5 FPGA via JTAG using an FT232H. Between the FT232H GND, TDO, TDI, TMS and TCK are connected. The problem is, that I only read out the correct chip ID if I listen on the TCK channel with the scope and a passive (!) probe. The problem is independent of frequency (10 kHZ to 25 MHz).In the working case the signals look like this (TCLK_A = Active probe on TCK, TCLK_P = Passive prob on TCK):And when I disconnect the passive probe on TCK it looks like this (different signal on TDO)Any hints want could be causing this issue?

author: cowana
author_rank: Frequent Contributor
timestamp: February 01, 2020, 10:35:16 am
content: I suspect that without the scope connected, you're seeing ringing on the TCK line, causing the FPGA to incorrectly register two bits.With a small amount of capacitance connected (the passive scope probe), the rise time is slugged, stopping the ringing and making the FPGA correctly see a single edge.Can you try connecting a small resistor in the TCK line between the FT232H (22R?) to slow the rise time? Alternatively adding a capacitor to the board (10pf) should have the same effect as the scope probe.Note that edge rise-times are separate to frequency - it's not surprising you see the same issue at 10kHz or 25MHz.

author: rs20
author_rank: Super Contributor
timestamp: February 01, 2020, 10:36:47 am
content: Strange issue. Assuming it's not caused by something you're not mentioning, and assuming that attaching the group clip of the oscilloscope alone doesn't have any effect, all I can think is to suggest that maybe there's an interfering noise source, and the capacitance of the probe is shunting some of the noise away. Make sure you're using 1:10 mode on your probe, and if that still causes it, try replacing the probe connection with a 10-100pF cap to ground, as a way to validate my hypothesis.

author: magic
author_rank: Super Contributor
timestamp: February 01, 2020, 10:39:50 am
content: It's a phenomenon known to programmers as a "Heisenbug", after the Heisenberg quantum uncertainty principle, which states that it is impossible to measure/observe a system without affecting its behavior.Attach a scope probe permanently to the circuit and forget about itSeriously, I suspect that probe capacitance provides some noise reduction which eleminates earlier problems with TDI that you didn't even notice. If the probe is removed, this problem causes the JTAG probe to identify the chip incorrectly and send different commands.QuoteIt's probably capacitive crosstalk between CLK and TDI. The JTAG sends a clock edge which causes a spike on TDI and then immediately reads TDI state, regardless of clock rate, before the spike has enough time to dissipate. Or perhaps the DUT samples TDO immediately after a clock edge, interprets a command wrong, sends wrong response, the JTAG outputs a wrong next command.

author: tggzzz
author_rank: Super Contributor
timestamp: February 01, 2020, 11:49:25 am
content: Insufficient information to be able to diagnose a signal integrity problem.Specify the probes used.Show the schematic, and preferably the PCB layout.Show a photo of your probing technique.That's all necessary when dealing with analogue signals - and your signalsareanalogue.

author: twam
author_rank: Unknown
timestamp: February 01, 2020, 12:30:14 pm
content: This is my current probing setup:I don't have schematics or a PCB layout as this is an off-the-shelf board, which was reverse-engineered by some awesome people athttps://github.com/q3k/chubby75/blob/master/5a-75b/hardware_V7.0.mdThe FT232H sits in a cable from FTDI (https://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_C232HM_MPSSE_CABLE.PDF).I already tried to put a 22 pF between TCK and GND as I was also thinking of the capacitance of the probe, but didn't see any difference. However now I tried to put a 22 R in series as suggested by cowana and this seems to fix the problem.

author: tggzzz
author_rank: Super Contributor
timestamp: February 01, 2020, 12:47:42 pm
content: You should also look at the edges of the pulses; don't be mislead into thinking that a 1kb/s logic waveform is low frequency.The setup and hold times are also relevant.In addition, what's the waveform seen by the receiving ic, without all the extra lead parasitics.

author: bson
author_rank: Unknown
timestamp: February 01, 2020, 05:34:55 pm
content: Grab your DMM and check that you have a clean ground between the power supply, FT232H ground pin, and your microcontroller. Is the power supply floating? Remember that the ground clip on the scope probe is an alternate return path for current, and can make ground loops go away.

author: ebastler
author_rank: Super Contributor
timestamp: February 01, 2020, 07:58:06 pm
content: Quote from: cowana on February 01, 2020, 10:35:16 amQuote from: bson on February 01, 2020, 05:34:55 pmYes, those would be my two bets as well:- Either the scope probe adds some capacitance to dampen ringing on the signal line(s),- or the scope GND connection adds a previously missing ground.You should be able to quickly distinguish which effect is in play by connectingonlya ground clip from the scope, leaving the actual probes disconnected. If that makes things work, it's due to a grounding issue which the scope works around.

author: twam
author_rank: Unknown
timestamp: February 01, 2020, 08:34:04 pm
content: Quote from: ebastler on February 01, 2020, 07:58:06 pmGround of scope is/was connected all the time.

author: ebastler
author_rank: Super Contributor
timestamp: February 01, 2020, 08:55:24 pm
content: Quote from: twam on February 01, 2020, 08:34:04 pmYou mean the scope ground was also connected when you had actual the scopeprobesdisconnected? And under that condition the JTAG transmission didnotwork?(I am not quite sure whether you got my point from the previous post. My proposal was to connectonlythe scope ground clip, and not the probes, for a test. This can be used to diagnose whether it is the added ground connection via the scope that makes JTAG work, or the capacitive loading of the signal lines.)

author: iMo
author_rank: Super Contributor
timestamp: February 01, 2020, 09:15:14 pm
content: Jtag likes pullups resistors on all signals (ie 4k7-10k) except TCLK which should be a pulldown.

author: Niklas
author_rank: Frequent Contributor
timestamp: February 02, 2020, 08:01:47 am
content: Looking at the scope pictures without the probe attached to TCK shows an increase of noise on the other signals. Zooming in would probably reveal that the noise is synchronized with the edges of TCK.The issue with both the JTAG connector and the probing setup is the return current path for the signals. There is no 0V/GND on the vertical breakout board and both the oscilloscope and the FTDI are referenced to other points on the PCBA. You would not probe on a switchmode power supply with the ground clip lead attached to your probe, but this is exactly what you have here. Essentially, the probing setup has created an invisible transformer between TCK and the other JTAG signals and the edges are coupled. By attaching the probe, the coupled signal is changed by the impedance in the probe.There are pulldown resistors at the bottom of the PCBA next to the JTAG connector, but the values are unknown. The FTDI harness also only has one wire for the return current, so that will also make the setup more sensitive for fast edges by adding another transformer coupling between the signals.

author: twam
author_rank: Unknown
timestamp: February 02, 2020, 10:56:36 am
content: Quote from: ebastler on February 01, 2020, 08:55:24 pmI had the ground connect while the passive probe was not connected to TCK. I didn't do a test without any probes and only a GND connected.Quote from: Niklas on February 02, 2020, 08:01:47 amDo you have the same board? Did you notice any issues?Also tried replacing the FT232H with a J-Link and this also works.

author: Niklas
author_rank: Frequent Contributor
timestamp: February 02, 2020, 03:43:02 pm
content: No, I don't have the same board but have seen similar symptoms in the EMC lab. In that case we saw a coupling of transients on the power supply over to a CAN bus. The fix was to twist the wires together in a 5 cm section where they were arranged similarly to your setup. The twisting reduced the loop area, hence less coupling.The 20 pin JTAG on the JLink has 0V wires spread out between the signals in the flat cable. It also seems to have 22R series termination resistors.