Automatic trace length matching - Page 1
Forum section: electronics / general

author: nickb
author_rank: Newbie
timestamp: October 02, 2019, 01:59:32 pm
content: Hi All, first post on this forum.I recently worked on a DDR4 design an spent days manually length matching traces using the Interactive Length Tuning tool.Pushing adjacent traces using the tool does not seem to work so you really have to think ahead in terms of spacing.Is there a way to automatically trace length match a group of signals in a net class?There is an Equalize net lengths command but it just tries to match all traces which is not ideal.Seeing as competing tools can do this in a few clicks I pitched it as an idea on Altiums bug crunch:https://bugcrunch.live.altium.com/#Idea/11995Any help voting would be greatly appreciated!

author: cgroen
author_rank: Unknown
timestamp: October 02, 2019, 02:39:24 pm
content: I used one of Robert Feranec ecxellent videos:

author: SerieZ
author_rank: Regular Contributor
timestamp: October 02, 2019, 02:42:49 pm
content: I have only ever applied this to Differential Pairs and not anything more complicated than that so take it with a grain of Salt...Have you tried to make a rule specific to the net class?Maybe take a thorough read of this:https://www.altium.com/documentation/16.0/display/ADES/((Length+Tuning))_ADI am asking because I might get stumped by the same Issue if in the Future I am required to do more complicated Designs.Anyhow I am voting for your Idea just in case.

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: October 02, 2019, 03:09:09 pm
content: Quote from: nickb on October 02, 2019, 01:59:32 pmSounds like your rules were not properly scoped/defined. Or you routing settings were incorrect.This has been talked about many times before on the forum.https://www.eevblog.com/forum/altium/altium-differential-pair-length-match-problems/

author: nickb
author_rank: Newbie
timestamp: October 02, 2019, 03:17:57 pm
content: Thanks for the answers.The Robert Feranec video shows the approuch I took.I used the xSignals DDR4 wizard to create the xSignals between al the devices together with the Matched Length rules.He also has a video about xSignals:Then you have to start routing the traces in the best way possible (keeping byte lane signals from the same byte on the same layer, etc..).And then you can start length matching using the interactive tool.But this is an iterative and tedious process that takes a long time.Competing tools can do these two steps automatically within a few clicks, hence my bugcrunch idea

author: nickb
author_rank: Newbie
timestamp: October 02, 2019, 03:22:41 pm
content: Quote from: Pseudobyte on October 02, 2019, 03:09:09 pmI did not have any problems getting everything routed and length matched.It was just a very time consuming process.

author: Pseudobyte
author_rank: Frequent Contributor
timestamp: October 02, 2019, 03:48:11 pm
content: Quote from: nickb on October 02, 2019, 01:59:32 pmSorry that sounded like problems to me.

author: lilstevie
author_rank: Contributor
timestamp: October 03, 2019, 03:40:01 am
content: Quote from: nickb on October 02, 2019, 03:17:57 pmBefore AD I was using CircuitMaker then CircuitStudio. I don't know if its just coming from doing it all manually but I found it to be an extremely pain free process that was super quick

author: nickb
author_rank: Newbie
timestamp: October 03, 2019, 07:03:25 am
content: Quote from: lilstevie on October 03, 2019, 03:40:01 amYeah it's the first time I did a design this complex, the next time it would probably go faster.But still, in this time and age, I think trace length matching a bunch of traces is something that could be automated.

author: nickb
author_rank: Newbie
timestamp: October 03, 2019, 07:08:25 am
content: https://www.pads.com/multimedia/player/stay-ahead-of-the-curve-with-full-range-ddr-design-capabilities-9b987cb8-e2d4-484c-a448-1a5d6242c353At 17:30 you can see what I mean with a few clicks.