Op amp noise question - Page 1
Forum section: electronics / beginners

author: DuncanSteel
author_rank: Contributor
timestamp: January 28, 2017, 12:15:08 am
content: HiI hooked up my load cell to an op amp & made 220 measurements on the output (see the schematics below). As it turned out the output is jumping for about 8 units after I ADC read & then convert it to decimal.Is it normal for it to be this jumpy or its the noise?

author: BrianHG
author_rank: Super Contributor
timestamp: January 28, 2017, 12:30:27 am
content: Try a 100 ohm series resistor between the op-amp output and adc. Then put a 100uf cap between the GND and ADC input. Any remaining noise you see is the ADC converter's noise + you +5v rail noise.Load cells connected to op-amps do have quite a bit of noise due to the high gain usually involved when amplifying load-cells.

author: David Hess
author_rank: Super Contributor
timestamp: January 28, 2017, 01:38:15 am
content: Quote from: BrianHG on January 28, 2017, 12:30:27 amI disagree with both of your points. Operational amplifier noise has nothing to do with the poor results here although it would be nice to know what operational amplifier was used.If a ratiometric differential measurement is made, then the effects of noise are minimal even without low pass filtering because most of the noise is rejected. Noise from the operational amplifier is not an issue but drift is. A good design will yield 40,000 counts with less than 1 count of noise and that is better than the accuracy of practically all load cells.So how to fix the circuit? Start by making a differential measurement which includes the other leg of the bridge which in this case is the non-inverting input to the operational amplifier and make sure the excitation level for the load cell is tied to the ADC reference or the reverse. The first removes common mode noise and the second removes reference drift.Ideally the measurement is made using an integrating ADC like an integrating dual-slope converter or a delta-sigma converter but fixing the above two things is a good place to start. Sampling ADCs are poor performers in these applications.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 28, 2017, 10:54:10 am
content: The shown amplifier the 1 M and the usual 150-200 Ohms output impedance of an DMS bridge is a lot of amplification. So an 8 LSB noise corresponds to something like 8 µV at the OPs input. Given the likely relative high bandwidth (could be in the kHz range) this might be normal for the OP. It also depends on the choice of OP.To improve on it one could use a little of filtering. The more obvious point for filtering is a capacitor in parallel to the 1 M resistor. Depending on the speed of the ADC, something like 100 pF or 1 nF could be about right. The main part is filter enough to avoid aliasing for the ADC, so to remove noise faster than the ADC reading can correctly handle. The ADC should than be ran relatively fast (e.g. continuous mode at maybe 10 kHz). It is Ok and even good if the ADC still sees some noise - this makes oversampling and averaging values more efficient.

author: DuncanSteel
author_rank: Contributor
timestamp: January 28, 2017, 11:01:43 am
content: Quote from: David Hess on January 28, 2017, 01:38:15 amFollowing Op amp is used, 6 pin. It should be a good op amp, (I think..), this is why I was wondering about so horrible readings.MAX4239AUT+TA sample was taken every 100ms. 220 times. That is pretty slow.I tried a cap parallel to 1Mohm resistor. No difference in readings at all.EDIT: well this is embarrassing, since I did try several caps parallel to 1Mohm resistor & there were no difference at all, maybe I was too tired then. Tried again just now with a ceramic 0,1uF cap & accuracy went from peak to peak 8 digits to peak to peak 2 digits.So yes, thank you.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 28, 2017, 12:06:46 pm
content: The max4239 is a reasonable good choice, though not the lowest noise.The high gain and GBW of the OP sets a BW limit of about 1-2 kHz for the OP. Above that the OP is more or less open loop and might show even higher noise. So it would be a good idea to have the parallel cap in feedback.The relatively fast sampling ADC has a high bandwidth and thus can get noise up to the 100 kHz range. So a 8 µV_pp noise at the input of the amplifier makes absolute sense. A second filter behind the OP might have it's value - though not with a 100 µF cap, more like 10-100 nF.Than taking many samples an averaging can help to reduce the noise even further. A sampling ADC just needs the anti-aliasing filter to get the lowest noise. Averaging over a window of 100 ms also helps to reduce noise from 50/60 Hz or 100/120 Hz mains related disturbance.For oversampling one needs some noise in the raw data - so a better OP might not even help. It looks like the ADC could get the limiting factor first.

author: danadak
author_rank: Super Contributor
timestamp: January 28, 2017, 12:11:09 pm
content: Also consider signal averaging on code.https://www.dropbox.com/s/2h96beh1fbvz4e2/noise_notes.zip?dl=0Regards, Dana.

author: David Hess
author_rank: Super Contributor
timestamp: January 28, 2017, 01:05:30 pm
content: I wish we had had operational amplifiers like that in the past but somehow we managed to get noise free 16 bit and better results anyway. Once we had results which were off by 1 count (!) and found a bug in TI's integrating ADC chipset which nobody else had noticed for years. Or maybe somebody did notice but TI was not sharing.I agree with Kleinstein about sampling over a window to create a sin(x)/x response to null out 50/60 Hz noise and that is the first thing I would do. Integrating converters do this naturally. Since you are in Estonia, a multiple of 20ms worth of conversions will be sufficient to notch out 50 Hz and its harmonics. 100ms has the virtue of notching both 50 and 60 Hz.Studying ADC sections of the Atmega32u4 datasheet reminds me of why I never used Atmel's microcontrollers. Differential mode is lower resolution? Why? (1) The maximum reference voltage is lower in differential mode? What does this even mean?Given the ADC's nebulous limitations, I would alternate two separate channels during the integration time to sample both sides of the bridge to make a (poor) differential measurement. This will allow the reference to be Vcc if you are not going to use the internal reference and apparently not throw away INL. What I absolutely would not do is use Vcc for the load cell excitation while using the internal reference for the ADC. If you want to use the internal reference, then add a circuit to provide the load cell excitation from it.This is an awful lot of work for a result which might be no more accurate than 8.5 bits or about 1 part in 400.(1) My guess is that their differential amplifier is atrocious.

author: Brutte
author_rank: Frequent Contributor
timestamp: January 28, 2017, 01:42:33 pm
content: Quote from: DuncanSteel on January 28, 2017, 12:15:08 amThat is a differential amplifier arrangement. I am not sure what bridge you use but assuming it is a popular 350ohm one, you get the equation:Uout-U3_4 = X*(U1_3 - U2_4)U1_3 is the voltage on connection of (Rb1 Rb3), U2_4 is on (Rb2 Rb4) and U3_4 is on (Rb3 Rb4) which you have grounded.The X is called differential gain and in your case that is over 5714You should not reference the output to U3_4 because this signal eventually is fed to ADC so it should be referenced to GND of ADC and uC. And GND on uC is not the same as U3_4.If by some chance U1_3 is lower/higher than U2_4 by some 5V/5714=875uV initially then the output hits the top/bottom rail. So you have to null the output somehow (tare).As for peak to peak and noise - calculate mean and variance of the signal fed to ADC. If the variance is around 0.027 of an ADC bit then that is ok.