Xilinx Ise 14.7  create an ucf  file pinout - Page 1
Forum section: electronics / general

author: coromonadalix
author_rank: Super Contributor
timestamp: August 29, 2019, 02:26:19 am
content: Hi i have some 20x Xilinx xc9572 plcc 84 cplds laying around, i know i know they are oldies ... and i must admit its been a while since i've played with Xilinx Ise .... had the v9 before ...I have this idea to synthetise an Intel 8243 vhd file i saw herehttps://github.com/freecores/t48/tree/master/rtl/vhdl/t8243and create a pld file and later if it goes well, maybe convert it to an Atmel Atf1504 or 1508, my ultimate goal is to keep/have it working at 5v i/o'sCreated a new project with xc9572 plcc84, added all the source files from the link, made the simulation (attached file)My problem is to create the cuf file, i cant figure out how im adding or determining the pinoutsThe 8243 has 5 ports of 4 bits bidirectional = 20 pins used + one active low CS and a prog pin = total of 22 pinsTried to read as many help files on the web, but no availNeed some help and pointers, i'm lost for the bidirectional ports and the internal structure when i try to read the vhd files.

author: coromonadalix
author_rank: Super Contributor
timestamp: August 29, 2019, 04:08:14 am
content: It give me this attached image and files and we see 2 errors on the bottom ?But the p2 thru p7 port have separated pinsand a enable pin ??Ex:NET "p2_i<0>" LOC = "S:PIN44";NET "p2_en_o" LOC = "S:PIN23";NET "p2_o<0>" LOC = "S:PIN62";I need to use the chip in asynch and use the tri state in out

author: davep238
author_rank: Contributor
timestamp: August 29, 2019, 07:07:26 pm
content: This VHDL code is for something like what you were trying to do. It fits into a XC9536, so it will also fit into your XC9572.

author: coromonadalix
author_rank: Super Contributor
timestamp: August 29, 2019, 10:39:20 pm
content: okay ill try this, i never worked with tri state logic, so i dont catch why i dont have a bidirectional pinout, they are separated ... i may have loaded the non tri state vhd ...

author: davep238
author_rank: Contributor
timestamp: August 30, 2019, 01:53:39 am
content: Imagine that you have a register in your 9572 that the CPU can both write into and read from over a single data bus. The output of the register must be isolated from the data bus when the CPU is NOT reading the register. This is done using tristate buffers. When a tristate buffer is disabled, its output is disconnected from its input. The output then "floats". An output buffer is tristated when a 'Z' is written to the output buffer in VHDL. See my code for reading the registers as an example. And because the data bus is bidirectional, it must be declared "inout".

author: davep238
author_rank: Contributor
timestamp: August 30, 2019, 01:58:39 am
content: If you have a separate input data bus and a separate output data bus, then yes you won't need bidirectional ports or tristate buffers. You will, however, use a lot of pins. You will need to check that your design fits into your 9572.

author: coromonadalix
author_rank: Super Contributor
timestamp: August 30, 2019, 04:07:21 am
content: okay it gave me this files (attached), i think i wasn't working with the right top moduleCan't go down to an 9536, doesn't fit and need pins renaming/remapping

author: davep238
author_rank: Contributor
timestamp: August 30, 2019, 09:16:29 am
content: "top_in_out.vhd" (modification of my code) should be the top module in your project. However, your UCF has 2 pins that aren't in my design: "prog_n_i" and "cs_n_i". The UCF must match the pins in the VHDL entity. My code assumed a generic CPU interface, so I used "cs", "rd", "wr", and "clk". You can use "cs_n_i" or "cs_n" if you need an active low chip select. In that case change the "cs" check from (cs= '1') to (cs_n='0'). If you really need to duplicate the 8243 chip's strange interface, then you will need to use the CPU interface portion of the 8243 code from the github. That code generates read and write strobes based on the rising or falling edge of "prog_n_i". You will use the write strobe in place of "clk".BTW, what will your 9572 be connected to?

author: coromonadalix
author_rank: Super Contributor
timestamp: August 30, 2019, 10:45:54 am
content: This is the Intel 8243 datasheethttps://www.datasheets360.com/pdf/-967702548426954361I cant figure how the chip is used ? it's connected to an 80c31 port 1 as a i/o port expanderThe files i have from, mention an async and sync mode with no tri-statehttps://github.com/freecores/t48/tree/master/rtl/vhdl/t8243On the page 5-60 i see the pins conditions, and i have a tri-state at power onThe attached file seem the right one to work with but i see many sections, do i have to add all sections of this file in the behaviorial file ?

author: davep238
author_rank: Contributor
timestamp: August 30, 2019, 05:09:10 pm
content: Do you have a schematic diagram of your 8031 system, that wold show at least the external ROM? And just out of curiosity, why a chip from the 8051 family? WHat are you trying to accomplish? Remind me again why you need a 4-port expander. Atmel/Microchip has 8051 core MCUs with lots of I/O ports, and internal flash program memory (EPROM).If you need the VHDL 8243, then use the async version. But I'm not sure how to connect it to the 8031. Perhaps someone in the "microcontollers" forum could help you with the 8031 and memory, etc.

author: coromonadalix
author_rank: Super Contributor
timestamp: August 30, 2019, 06:16:45 pm
content: Its my personal take on a old sencore interface, its build around an 8243 i/o expander a c31 mcu an 32k eeprom and an 8250 uart ic and a max232, I have begun a reverse schematic for it.My ultimate goal while refreshing my xilinx stuff is to modernize the interface while keeping 5volts in / out chips inside. It connect to the main sencore unit thru a 4 bit port to an c39 mcu ... im not very good a coding and or sniffing out protocols. I have the other parts but in plcc44 pinouts ...The xc9572 i have (around 20) are never used leftovers from previous boards at my company, they have been replaced with atf1504 cpld on a small made plcc84 board mimicking the 9572.But this 8243 port is not easy since i'm taking a huge leap from v9 to a v14.7 ise.

author: davep238
author_rank: Contributor
timestamp: August 30, 2019, 09:37:13 pm
content: I have ISE 14.7 that I used for XC9500/XL CPLDs and Spartan3 series FPGAs. I don't recall what ISE 9 was like. That was probably back when ISE used Modelsim as a simulator. Now it uses ISim which is a part of ISE.BTW, when you use someone else's code the polite thing to do is put their name as an author in the header comments along with your own. You are required to do this when you use code from OpenCores (GPL). My code comes with the unstated BS that it's not perfect, but you can do anything you want with it. My code was written to show the basics of a 4-bit 4-port bidirectional device. It does not mimic an 8243. That guy's code on OpenCores does mimic an 8243, but oddly it uses separate inputs and outputs rather than bidirectional buses.This is the first time I've done a VHDL project in quite a while. I had forgotten a lot, but I had fun re-learning VHDL.

author: coromonadalix
author_rank: Super Contributor
timestamp: August 30, 2019, 10:29:04 pm
content: sorry will correct my mistakesEverything i compile give me the no tri state async or sync chip ... only once i had the correct pinouts assignment quantity ??

author: coromonadalix
author_rank: Super Contributor
timestamp: August 31, 2019, 04:34:21 pm
content: @davep238 thks for the helpI'm banging my head over this one loll can't toss it aside lollSlightly reworked your code description to help me understand.I was not understanding the entity section, should the port give : (size 3 downto 0) ?? there is 4 ports pins (p0 p1 p2 p3) ??You define the ports, cs, addr, wr, clk, rst separately because they are the chip functions, correct ?Maybe thats why i get pinouts differently in the simulation, in and out are separated with an added control pin, thats why i get around 45-46 pins instead of 20 bidirectionals pins ?I have some misunderstanding of the power on state, rise and falland the simulation give me the attached pdf, 26 pins instead of 20 ??GCK is the clock, my renamed (progclk ??) of your file. Rename the *.htm.txt into htm

author: davep238
author_rank: Contributor
timestamp: September 01, 2019, 02:55:27 am
content: Quote from: coromonadalix on August 31, 2019, 04:34:21 pmThat's why I wrote the code.QuoteJust use "(3 downto 0)" and then delete the "generic" line. I used "generic ( size : integer := 4);" just to show that the port widths could be easily changed. I'm sorry that I confused you. Yes there are 4 port pins: p3, p2p, p1, p0.QuoteBecause "cs", "wr", "clk" and "rst" are all std_logic, they could have been on the same line as long as they are separated by commas.for example:cs, wr, clk, rst : in std_logic;QuoteYour PDF file actually shows the Fitter Report, and not a simulation report. You got the same results as me. There are 5 4-bit ports, plus 6 control signals plus the clock. That adds up to 27 pins.QuoteI looked at the Xilinx DS063 XC9500 family data sheet and didn't see anything about power-on states for flip-flops However, outputs will be disabled until the 5v line reaches 3.8 volts. To ensure that outputs are the correct value at power-on, you must write some code. For example:write_ports: process (clk, cs, rst, addr, wr, data) isbeginif rising_edge (clk) thenif (cs = '1') thenif rst = '1' thenreg_port40 <= (others => '0');:note that <= (others => '0'); --sets all bits to '0'. Alternatively I could have written:<= "0000";using "others" means that if the port's width changes, say from 4 bits to 8 bits, that the code doesn't have to change. For 4-bits typing each bit is no big deal, but it gets awkward when there are 32 bits.QuoteThere are 26 pins + the clock pin (GCK/IO). BTW, I didn't see anything useful in the htm files. Change anything you want in the code. Again my code was for a generic 4-bit, 4 port device with a generic CPU interface. It was not intended to directly interface with your 80c31 CPU. I didn't know what your CPU was at the time I wrote the code. Thank you for putting my name as an author. However, since you are making changes, your name should also be an author. To interface with your 80c31 CPU you will need to use that code that you found on Open Cores plus my code for the bidirectional ports. His code internally generates the Read and Write signals so you won't need "rd" and "wr" or "clk" (the 80c31 doesn't output a clock). Be sure to add his name as an author.I'm not sure what hard-copy books I can suggest that you read. I have some and most are out of print. However, I highly recommend "Free Range VHDL" which is an on-line book. It should help you with your beginner questions. I will still continue to help if you need it.

author: coromonadalix
author_rank: Super Contributor
timestamp: September 07, 2019, 02:15:16 pm
content: Failed miserably to merge and or do a full code implementation

author: davep238
author_rank: Contributor
timestamp: September 13, 2019, 01:43:42 am
content: The attached VHDL code should describe a 8243 I/O expandor chip. It uses bidirectional ports. It does reads, and writes + ORLD and ANLD. It has not been fully tested because I need to see some 80c31 code that communicates with the 8243. I need both read and write CPU code, but especially, I need to see CPU code that reads from a 8243 port. It fits into a XC7536.I will be gone for several days. Let me know if this works. I just got some 8243 chips (eBay), that I can test with once I get the CPU code. I plan on using an Arduino for testing.

author: coromonadalix
author_rank: Super Contributor
timestamp: September 13, 2019, 03:07:29 am
content: Hi thks for the helpa small errorERROR:HDLParsers:3313 - Line 83. Undefined symbol 'rising_dege'. Should it be: rising_edge?ERROR:HDLParsers:1209 - Line 83. rising_dege: Undefined symbol (last report in this block)corrected to 'rising_edge'Gave this errorline 80: Signal port_2 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.??Im running on the 14.7 version, do i need another one to match yours ? or the license i have doesn't fit the needs ... i do have a few exired features ..

author: coromonadalix
author_rank: Super Contributor
timestamp: September 13, 2019, 03:26:04 am
content: Oh the cpu code ?? its coupled on an 80c31 cpu port 1 with an 27c256 eeprom ... the eeprom content has been dumped

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 14, 2019, 05:13:32 pm
content: Quote from: coromonadalix on September 13, 2019, 03:07:29 amIndeed. Just a typo, but that may indicate the author didn't actually compile their code, or at least the version they posted.Quote from: coromonadalix on September 13, 2019, 03:07:29 amThis one may not be immediately obvious. It's not a VHDL error per se, it's indeed an implementation problem.A typical case of this error would be if you were writing a process sensitive to more than one clock edge, such as:Code:process (Clk1, Clk2)beginif rising_edge(Clk1) thenA <= ...;elsif rising_edge(Clk2) thenA <= ...;endif;end process;This won't work because it would require a dual-clock flip-flop to register 'A', which is not something that exists in an FPGA. Thus the synthesis would fail.In the posted entity ('v4'), I think the problem comes from the 'capture' process. It registers port_2 (slices of it) on the falling edge of 'prog', whereas in the 'read_ports' process, 'port_2' is a register clocked on the rising edge of 'prog'. Conversely, the 's_instr_cd' signal, which is compared on the rising edge of 'prog' in 'read_ports', is registered on the falling edge of 'prog' in 'capture'. This sorts of create a circular registering scheme that would, I assume, require dual-edge flip-flops. Something those FPGAs don't have.This piece of code would have to be rewritten. That may simulate properly, but this is where simulation and synthesis diverge. Writing RTL to be sensitive to both edges of a clock signal for FPGAs can be tricky. Now some FPGAs may have dual-edge flip-flops (I don't think I've ever used any, but they may exist). Or that could also be synthesized directly on an ASIC given you have dual-edge flip-flops in the libraries you're using....

author: davep238
author_rank: Contributor
timestamp: September 15, 2019, 11:23:02 pm
content: Thanks SiliconWizard. I made last minute changes to v4.vhd before going on my weekend trip and didn't think things through. It appears that I also didn't compile it, because if I had I would have seen the errors. That's what I get for rushing. I'll have to rethink the "read" process.

author: coromonadalix
author_rank: Super Contributor
timestamp: September 16, 2019, 03:11:29 am
content: ok thksfound this :https://www.xilinx.com/products/silicon-devices/cpld/coolrunner-ii.htmland maybe some explanation:https://electronics.stackexchange.com/questions/39709/using-both-edges-of-a-clocksome pseudo code:http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdfsome vhdl ??:https://forums.intel.com/s/question/0D50P00003yyKW0SAM/low-power-vs-dualedge-triggered-flipflops?language=en_USdualEdgeTriggered: process(reset,clk) isvariable q1,q2:std_ulogic_vector(q'length-1 downto 0);beginif reset='1' then q1:=(others=>'0'); q2:=(others=>'0');elsif rising_edge(clk) then q1:=d xor q2;elsif falling_edge(clk) then q2:=d xor q1;end if;q<=q1 xor q2;end process;

author: davep238
author_rank: Contributor
timestamp: September 16, 2019, 11:08:33 pm
content: Before the disastrous version 4, I had created version 3. I've created a test bench that shows that writing to a port works. I'm weak writing test benches so I'm having problems testing the input feature. However, the code does follow the 8243 datasheet. So I think that this code will work in real life. Please *ignore* version 4!

author: davep238
author_rank: Contributor
timestamp: September 16, 2019, 11:11:38 pm
content: Quote from: coromonadalix on September 13, 2019, 03:26:04 amWhat port is the 8243 connected to?

author: coromonadalix
author_rank: Super Contributor
timestamp: September 17, 2019, 09:11:22 am
content: ok hope you follow me here loll80c31 to 8243 portsp1.0 p4.0p1.1 p4.1p1.2 p4.2p1.3 p4.3p1.4 p5.0p1.5 p5.1p1.6 p5.2p1.7 p5.3the 8243 port who goes to the lc102 main cpuprog pinp2.3p2.2p2.1p2.0Pigrew did a port of this chip in the lc102 interface into a machx02,https://www.eevblog.com/forum/projects/sencore-usb-interface-project/his github repohttps://github.com/pigrew/SencoreLC102/tree/master/sencore_IBBut i must admit, i dont understand the github structures, i wanted to play with 5v i/o tolerant cplds ... reducing the parts count, we use atf1504 and atf1508 at my job, their software are linked to the network mac adress of the computer you use, in the license ??But my knowledge is limitted to the old xilinx stuffIts more complex than i tought.