I'm looking for some pointers/criticisms on my first 2-layer board layout. - Page 1
Forum section: electronics / projects

author: roymoran
author_rank: Contributor
timestamp: July 20, 2022, 02:33:44 pm
content: I am close to completing the layout for a project I've been working on for some time. I've done my best to do a lot of reading and video watching to make sure I've covered some of the more obvious things in a 2-layer board. Although as a beginner I am certain I am making some blunder that I am not aware of. For that reason - I'd appreciate some general or specific thoughts about this layout. I am including a few screenshots of the front and back copper layers. I've also included an annotated screenshot of the front copper layer with annotations/general guidance breaking down the board into certain sections/components and their purpose.To summarize the goal of the board. It is meant to power/control a 4.3 inch TFT-LCD with STM32 as the MCU.The top copper layer routes a majority of the power and signal traces. The bottom layer is a ground layer with the occasional power/signal routed through there too.The parts I use include- STM32 MCU- Micro SD Card Connector- Switch mode power supplies including boost and buck converters- USB-C Connector operating at USB 2.0 full-speed- LiPo battery charging IC- 40 pin FFC Connector for LCD

author: ebastler
author_rank: Super Contributor
timestamp: July 20, 2022, 04:10:20 pm
content: You have clearly put a lot of thought into this, and for a first layout it looks impressive! I am an amateur myself, so have just a few superficial comments -- I am sure others will have further remarks:The GND plane on the bottom layer is just barely connected from left to right. You will probably get away with it since the design is not overly critical (high speed or sensitive analog). But I would at least try to shift the traces on the bottom layer around a bit to make the connecting "pathways" between the left, center and right GND areas wider.What's up with the two signals between the µC and the SD card which briefly dip to the bottom layer and then come back up? Maybe a leftover from an earlier stage of the layout where you needed them to cross, or had something else crossing on the top layer?The length-balanced wiggly traces to the SD card are probably unnecessary at the data rates used?On the right-hand side, I am not sure where the physical board edge is located. The USB jack wants to stick out slightly over the board edge, but hole H2 should probably be well within the board?The position of the mounting holes is unusual. Are they where you wanted them to be, or where you could find room for them in the end? If it is the latter: No need to change them now if you have control over the mounting arrangement, but in future designs you may want to place them early on.You have plenty of test points (I assume), which is great. If you want to use them for manual testing, rather than a pogo pin adapter for automated testing of a whole batch, I personally prefer through-hole pads over SMD pads. Easier to position a probe tip without slipping, and you can solder a vertical wire to them to attach a probe's GND clip or such. For GND, I like to have two through-hole pads next to each other in one or two locations, so I can solder in a U-shaped jumper wire for solid attachment of GND clips.None of the above are "must-do" changes, I think. Again, great job with your first layout!

author: georges80
author_rank: Frequent Contributor
timestamp: July 20, 2022, 04:31:31 pm
content: Great for a first attempt. Your power and ground connections are very problematic and power (especially the VCC) looks poor with minimal bypass caps sprinkled around near VCC pins and ground. As above, the ground 'plane' is VERY cut up.For very little $ for a few protos, I would seriously look at moving to a 4 layer PCB and dedicate the inner 2 layers to power and ground distribution. And sprinkle more bypass caps near VCC and GND pins (especially the CPU). Consider where power currents have to flow. Also consider switching noise of your various DC:DC switchers and not running data/signal/sense traces under/alongside those areas.cheers,george.

author: roymoran
author_rank: Contributor
timestamp: July 21, 2022, 12:42:00 pm
content: Thanks ebastler, I appreciate the notes. I'm reviewing them now, and making changes to the board.To respond to a few of your comments -Quote from: ebastler on July 20, 2022, 04:10:20 pmThe bottom layer is being used predominately to route the LCD lines so those ended up taking a lot of space. I think that's mainly what's causing the separation between GND regions. I will be shifting these lines around to accomplish a wider connection between these areas.Quote from: ebastler on July 20, 2022, 04:10:20 pmThis part of the board layout is heavily guided by an STM32 application note (AN4661 page 44-45). It outlined some high level points for laying out the data lines in order to accomplish a "high speed" mode for the SDMMC peripheral on the STM32. The SDMCC peripheral defines this as a maximum clock rate of 50MHz. I think you're right about the length-matched data traces - they are likely to be unnecessary. I was going back and forth on whether to length-match these traces since I am not operating near 50 MHz (my testing operated the clock at about ~12MHz). In the end I decided to go with the STM32 recommendation in order to have some hope of "future-proofing" the layout in the event that I do want to operate at higher clock rates.The two signals which get routed to the bottom layer and back were based on a point from the application note. It states - "Keep the same number of vias between the data signals." And since I was not able to get away with routing the 2 left-most data lines on micro sd card connector without using 2 vias that led me to adding those vias to keep in line with the recommendation. Admittedly I don't know what the impact of the vias are the on the traces and why that was the recommendation. But after reading around I learned that vias introduce inductance/capacitance so I suspect the recommendation is driven by this since it also includes a couple points around trace inductance/capacitance.Quote from: ebastler on July 20, 2022, 04:10:20 pmThe position of the mounting holes is still kinda up in the air but they will roughly stay in the same position just off by a few millimeters right now. Although you're right the mounting hole by the USB is misaligned and not within the board. I adjusted this.Quote from: ebastler on July 20, 2022, 04:10:20 pmVery good points - I will be hand assembling and manually testing the board so it will be nice to have an easier probing experience for when I need to debug. I'll make these changes.Quote from: ebastler on July 20, 2022, 04:10:20 pmThank you - I appreciate it.

author: mariush
author_rank: Super Contributor
timestamp: July 21, 2022, 01:03:51 pm
content: May be a controversial opinion BUT the first thought that came to mind was why isn't the chip at 45 degree angle?The traces to the lcd connector (from the left side in current layout) would be MUCH shorter, closer to the connector)The corner of the chip could sit between the SD card and the USB connector where there's not much nowThe traces to the SD connector could be shorter, closer to the SD card slot.The programming header and whatever's above the chip could be shifted in the space freed between the chip and the SD cardI don't understand from the pictures why the LCD backlight circuit has to be so far away from the actual lcd connector, when the thick traces with higher voltage (3VIN I assume is 3 x input voltage) have to travel across the board to the right side of the connector.With the chip at 45 degree angle, the connector could be moved a bit to the left to make space for the backlight circuit right there to the right of the connector... but I don't get why that 3VIN thick trace goes over the top width of the pcb.All the stuff around the USB connector could be moved around to make room for the backlight driver or whatever, the test points for example TP103 and TP203 both ground test pads, TP206 can be moved, U201 could be closer to the usb port ..edit: is H101 a mounting/screw hole? if so, would it affect the flat flex cable going into the connector there? Looks kinda close to it, as is that trace going to the 4th pin on the right on the connector.edit2 : also look at that ground fill under the chip and where it's connected to all the other ground fill ... there's basically only two connections ... a thin ground path where the SD card traces are and another thin channel in the middle bottom area of the chip, between the traces to the ffc connector.The ground fill on the left side is connected to the right side only by a very thin channel / path under that H101 screw hole or whatever that is.Doesn't seem right to me...Consider using a smaller font / different font for the text, looks to me like you chose to layout some components depending on how the printed text fit, not how to have traces better placed, and have space for things. Text also doesn't have to be all the time close to the component ... for example you could place those test points near the usb connector in a vertical line, and have a legend with the test points numbers somewhere in a corner (ex above the usb connector where that space isn't used.

author: roymoran
author_rank: Contributor
timestamp: July 21, 2022, 01:29:52 pm
content: Quote from: georges80 on July 20, 2022, 04:31:31 pmThanks for the thoughts. I'll be reviewing the board to add additional bypass capacitors throughout. I am seriously considering moving to a 4 layer board for this project - learning about how difficult it is to accomplish a target trace impedance on 2 layers and also learning about how much easier it is to access/distribute ground/power on a multi-layer board is compelling. I haven't migrated a 2 layer project to 4 layers but I'm sure it's manageable. I just need to read up on how to do it in KiCad. Thank you again for the input.

author: pcprogrammer
author_rank: Super Contributor
timestamp: July 21, 2022, 01:41:46 pm
content: Also an amateur on PCB design, but the "problem" with the ground plane can be easily fixed by using the copper fill option on the top layer and add vias to connect top and bottom ground layer.The input poster mariush gave about putting the MCU at an angle and rearrange the different parts on the board might be good to consider.Also the SD card signals, I don't think you have to be worried about signal integrity to much. I made an experimental system with a FPGA module and a double DAC module connected with fairly long wires (5 ~ 10cm) of different lengths and have it running on 125MHz. Had to tweak the FPGA design to have a clock and a strobe signal set with a proper phase between them to avoid some glitches in the analog output, but it works.So with 50MHz on these short lines you have and synchronous to a clock you will be fine without the length matched lines. I think the high speed they refer to in the application note is for the ~200MHz some of the devices are capable of.But it is probably a good idea to move the pull up resistors closer to the pads of the SD card bay. Because the way you placed them the data lines become longer and in that area you did not use length matching. Think about transmission lines and reflections. I'm no expert, and maybe completely wrong, but I would try to fit them in close to the pads.Edit: With a fairly simple system like this you can do fine with just the two layers. Just try moving the bits around to get a more optimal placing. With the ground plane set on both layers it will be fine. If possible you can also increase the size of the board a bit to make routing a bit easier. Is still cheaper then a 4 layer board.

author: woody
author_rank: Frequent Contributor
timestamp: July 21, 2022, 02:06:15 pm
content: I am nowhere near a specialist and a little prone to OCD so take that into account while reading my comments- Prevent sharp corners and strange PCB tracks like around Q201/TP218- Let tracks always end in the middle of vias and pads- Let tracks that run 'together' have the same distance from each other in all their segments- No vias on the edge of a copper pour / ground plane- I see some tracks between vias in the ground plane. Maybe from earlier or because of errors- Align vias that are close together as much as possible- Prevent loose 'fingers' and small connections in the ground plane. Remove or reroute so that it is more 'connected', more a solid plane. Use a smaller clearances for the copper pour- Make much more use of vias to make connections from the chip to the ground plane. Now there are long, thin tracks that connect multiple pins that could get an immediate via to ground.- Some adjacent pins that need to be connected have a track 'between' the pads while others are connected 'behind' the pads. I would use one or the other.

author: roymoran
author_rank: Contributor
timestamp: July 22, 2022, 01:03:23 pm
content: Several good points mariush - I'm going to experiment with the suggested changes and see where this takes me. Right now there are 2 constraints on the placement of a couple components including the 40 pin FFC and USB-C connector. USB-C is positioned according to cut-out on enclosure. And the FFC is placed according to how the LCD mounts onto the enclosure and its ribbon cable must be able to reach the connector.Quote from: mariush on July 21, 2022, 01:03:51 pmKiCad defaults to rotating the components by 90 degrees so I didn't register this as a possibility while laying out the board. After a small search I was able to find out how to change this default - I'll mess around with it.Quote from: mariush on July 21, 2022, 01:03:51 pmThis 3VIN is actually not 3*VIN but it is the 3.3V VIN for a few components in the circuit including the MicroSD, MCU, and LCD logic pin. That's why right now it goes across the top width - to reach the MicroSD card connectors power pin.Quote from: mariush on July 21, 2022, 01:03:51 pmH101 is a mounting hole. The LCD flex cable will be inserted from the opposite side. Not over the top of H101, but over the top of TP110 so I don't think this hole/screw will be in conflict with the flex cable from the LCD. The trace coming into the 4 pin does look a bit close to the screw. I'll see if making previous adjustments (45 degree chip and moving backlight IC closer can help with this)Quote from: mariush on July 21, 2022, 01:03:51 pmI have started widening these thin ground paths and moving around traces on the bottom layer so that ground fills on bottom layer are more connected.Quote from: mariush on July 21, 2022, 01:03:51 pmYou're right, I kept the default size on all text and at times was prioritizing how well the text fit into the layout without going over traces. I wasn't really sure if it was okay for the silkscreen to be laid over the traces so I kinda avoided it at times, but slowly started just placing text over traces as I saw other boards doing this. I haven't gotten the hang of adding extra text-boxes/legends but this is good knowledge nonetheless.Lots of good thoughts here. Thanks for your input mariush.

author: roymoran
author_rank: Contributor
timestamp: July 22, 2022, 01:37:24 pm
content: Thanks pcprogrammer. The microsd card connector and its communication to the MCU is probably the component I am most worried about screwing up in this design. But it's reassuring to hear that you had little trouble with longer lines and higher clock speeds. Good to hear.Quote from: pcprogrammer on July 21, 2022, 01:41:46 pmI'll take a look at this option too for resolving the lack of connectedness between the bottom ground plane.Quote from: pcprogrammer on July 21, 2022, 01:41:46 pmHaving these a bit closer I'm sure won't hurt. I'll see about moving them up a bit.Thanks again for the feedback.

author: roymoran
author_rank: Contributor
timestamp: July 22, 2022, 01:55:11 pm
content: Quote from: woody on July 21, 2022, 02:06:15 pmThanks woody for all the points. I'm taking closer look at the board with these in mind.

author: pcprogrammer
author_rank: Super Contributor
timestamp: July 22, 2022, 03:26:57 pm
content: @roymoran, take a look at the PCB of the FNIRSI-1013D scope.https://www.eevblog.com/forum/testgear/fnirsi-1013d-100mhz-tablet-oscilloscope/msg3118672/#msg3118672You can see that the traces for the SD card are quite long and at least the visible bit is not length matched and I doubt it is done underneath the card holder. The resistors are close to the pads though. This runs at almost 50MHz without problems.

author: roymoran
author_rank: Contributor
timestamp: July 22, 2022, 10:43:02 pm
content: Quote from: pcprogrammer on July 22, 2022, 03:26:57 pmVery nice. I'm definitely more at ease about the sd card layout than I was prior to this post. Thanks.