Super duper ultra low frequency noise measurment.  - Page 1
Forum section: electronics / projects

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 04:20:55 am
content: I'm designing an analogue-input data acquisition/memory card with programmable Nyquist sampling rates ranging 200uS to 10s.The low-pass bandwidth will be 0.1*fs to keep the programmable anti-alias filtering practical.The unit will have a serial interface to upload the acquired raw data to a PC for FFT/DFT in MATLAB, etc.I've done little FFT/DFT from a coding perspective, so here is my question. Would there be much point in going beyond 10-bits of ADC resolution?The number of bits significantly effects the complexity of my anti-alias filter.Memory depth will be 100k-words, returning a frequency range of 4 decades given the 0.1*fs upper cut-off frequency.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 30, 2015, 04:54:27 am
content: Oversample, filter (digitally) and decimate; added bonus, tons more bits.Tim

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 05:10:24 am
content: fh @ 0.1*fs is 5x oversampling.........

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 30, 2015, 05:14:46 am
content: No, I mean, oversample the **** out of it, don't even begin to worry about analog filtering. Unless there's a compelling reason to do so (dynamic range, in the presence of very large signals at to-be-filtered frequencies?).Tim*Sorry, wouldn't want to offend anyone's dainty sensibilities...

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 05:20:23 am
content: QuoteUltimately the data (FFT) will need to be processed in a uC.This is a noise-measurement application (as suggested by the title) Analogue filtering is mandatory.

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 05:40:20 am
content: Quote from: evb149 on October 30, 2015, 05:30:42 amNoise measurement over the stated 4 decades. 1/f noise (3db/octave) over that range nor the occasional burst of popcorn noise DC-offset will yield a particularly large signal dynamic range, as far as I can figure.ADC linearity should be largely irrelevant.Wanna keep my computation to a minimum due to the need to ultimately perform all processing in a uC.Mainly concerned with if there is any true advantage for the implementation/execution of FFT routines to having a bit-depth significantly beyond the signal dynamic range requirements.

author: awallin
author_rank: Frequent Contributor
timestamp: October 30, 2015, 05:47:01 am
content: If your input is DC-coupled and you want to measure low-frequency noise I'd imagine you get issues with:- 1/f noise or random walk of the voltage reference for the ADC- 1/f noise of any op-amps for signal conditioning in front of the ADCThe common trick (I think) to get around this is to reverse the polarity of the signal voltage periodically. This is doable if you have e.g. resistive sensors.You mentioned a serial link. For low-noise you want isolation between the measurement setup and computers.A battery-powered box that has Ethernet, which has built-in isolation?If you are only interested in the FFT of the signal then you can look at the cross-spectral methods. This uses two ADCs to digitize the same signal and figures out the signal FFT while uncorrelated ADC noise is supressed.

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 05:55:31 am
content: Quote from: awallin on October 30, 2015, 05:47:01 amSignal pre-amplification and signal conditioning (where required) is completely independent of the ADC/acquisition card.The ADC will be receiving high-level signals to the extent that the noise contribution of the anti-aliasing filter is wholly irrelevant.

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 06:00:16 am
content: Quote from: blueskull on October 30, 2015, 05:42:14 amThen my 100k-word memory becomes 5G-word at my lowest equivalent sampling rate. That is a lot of data to crunch with uC.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 30, 2015, 06:14:20 am
content: Nah -- that's the beauty part. Filterand decimate, so you only take, say, the average of 16 samples, which becomes one sample at 1/16th the sample rate. And so on until you're at the desired level. Probably you'll want a better filter profile (a proper FIR or IIR) on the bottom stage, to get whatever final filter response you were looking for.Tim

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 06:24:43 am
content: Sure, if processing is done on the fly.But none of this answers my original inquiry:"Mainly concerned with if there is any true advantage for the implementation/execution of FFT routines to having a bit-depth significantly beyond the signal dynamic range requirements."Exactly how that bit depth is achieved (higher resolution ADC or oversampling) can now be considered irrelevant.

author: Kalvin
author_rank: Super Contributor
timestamp: October 30, 2015, 06:29:04 am
content: Oversampling by a factor of 4**N will give you N extra bits of resolution. For example, oversampling by 1024 will give you 5 extra bits, in theory.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 30, 2015, 06:43:01 am
content: Quote from: GK on October 30, 2015, 06:24:43 amSo now that we have the easy questions out of the wayI wouldn't think it would matter. That is, as long as the numerical step has a few extra bits, it's okay. Do be careful with carries from fractional parts; I expect you'll find there's a lot of residue drooling off the low order terms (namely, the samples that coincide with the zero crossings of sin/cos terms). In that regard, it might be worth keeping 50-100% more bits. 16 or 24 bit fixed point would seem reasonable enough to me?Tim

author: Kalvin
author_rank: Super Contributor
timestamp: October 30, 2015, 06:54:32 am
content: That's quite easy to test on PC without actual hardware. Just generate some noise and add two sine signals with amplitude difference, say 40dB. Compute the FFT. Truncate the bit width one bit at a time. Recompute the FFT and see what happens. Or you can start from 10 bits and increase the FFT bit depth one bit at a time and see what happens.

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 07:35:39 am
content: Quote from: T3sl4co1l on October 30, 2015, 06:43:01 amNot really. My range of frequency acquisition is 50,000:1. A fixed-frequency, low-order low-pass filter that simply fulfills the anti aliasing requirement of a significantly oversampled, fixed-frequency rate for the uppermost range will not by any means provide adequate protection against well out of band (by decades) spurious signals from potentially saturating the filter or both the filter and the ADC when effectively acquiring frequency data for the lowest (lower) range(s). My input filter is performing two important roles here.So in that regard my requirements for range-switching the anti-alias filter aren't removed, and that is where the principal complication lays (aside from the number of poles required as governed by both the ADC resolution and oversampling rate, which is what actually pertains to the question I asked at the beginning of this thread ).

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 07:46:38 am
content: Quote from: Kalvin on October 30, 2015, 06:54:32 amThat sounds like a plan but I have neither the software nor the time to get up to speed on doing that that right now and probably won't for a little while. If anyone else is eager, even if for just their own edification, then feel free to post the results up here

author: Kalvin
author_rank: Super Contributor
timestamp: October 30, 2015, 07:56:02 am
content: Quote from: GK on October 30, 2015, 07:35:39 amYou can make a passive, higher order filter quite easily which will attenuate the out-of-band signals as much as you wish. Still, you can take advantage of the oversampling as it will make the filter design easier and you can benefit from the extra bits from oversampling. If you really need to create steep low-pass-filter, and should the filter affect the passband signals near the cut-off frequency, the attenuation is very easy to compensate after FFT if you have bits to spare.

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 08:34:25 am
content: Quote from: Kalvin on October 30, 2015, 07:56:02 amHmm, not really. A high-order passive filter requires LC components and getting down to a cut-off frequency of 0.01 Hz with practically realizable inductors ain't going to happen!My preliminary filter design is active, with reed-relay-switched capacitors for the decade ranges and analog MUX-switched resistors for the 1/2/5 steps. Reed relays are used for the capacitors as analog switches put too much resistance in series that limits the ultimate stop-band attenuation (in a low-pass configuration).My only concern is to have the attenuation reducing a full-scale input to the LSB-level at the sampling frequency. I think I'm still pretty much going with the x5 oversampling that I specified in my opening post and 10-ADC-bits is likely enough even without decimation. More ADC-bits just means more reed relays and big bulky polypropylene capacitors.

author: Kalvin
author_rank: Super Contributor
timestamp: October 30, 2015, 08:53:30 am
content: Quote from: GK on October 30, 2015, 08:34:25 amWell, building a Nth order sallen-key active low-pass filter isn't too hard. Have you checked Maxim or Linear Technology? They have 8th order, clock-tunable switched capacitor low-pass filters. LT has also single resistor settable low-pass filter available. Using a simple active low-pass filter driving the switched capacitor filter would save you from lot of trouble. If you have high amplitude noise at higher frequencies you can use passive filter to get rid of those signal components before you feed the signal into active filter in order to avoid filter saturation. Also, there are op amps that can be operated at +/- 30V supply rail.

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 08:59:58 am
content: Problem with switched-capacitor filters is the clock-feed through on the output, which invariably requires filtering - and that filtering will need to be ranged switched........

author: Kalvin
author_rank: Super Contributor
timestamp: October 30, 2015, 09:03:55 am
content: I would consider attenuating the signal suitable for the 16bit ... 24-bit ADC, use a sampling frequency at least 1kHz, perform digital filtering to get rid of the unwanted frequency components. Using the attenuator with the high bit resolution ADC makes it possible to perform the actual signal processing in digital domain and you can keep your analog path very simple and you wouldn't have to use any analog filters with selectable cut-off frequency.

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 09:21:52 am
content: That would exacerbate the problem of making the ADCs filters noise contribution negligible in the same proportion that freedom from input overload is improved.

author: Kalvin
author_rank: Super Contributor
timestamp: October 30, 2015, 10:31:15 am
content: Well, it might help if you could provide more information about the following:- Signal frequency range of interest- Signal amplitude- Disturbance signal frequency range- Disturbance signal amplitude- Overall signal frequency range- Overall signal amplitude range- Accuracy requirements- Dynamic range requirements- How fast you can sample the signal- What kind of ADC you have available (Seems to me that you are trying to use Arduino and its on-chip 10-bit ADC here.)

author: Kleinstein
author_rank: Super Contributor
timestamp: October 30, 2015, 11:17:04 am
content: Especially for the low frequencies, I would avoid using analog filters. Digital filtering is usually easier at low frequrequenies. Because of spurious signals (e.g. 50/100 Hz) a silightly higher resolution ADC may be helpfull, bit today even 16 Bit ADCs are cheap and many µC have 12 Bit ADCs inside. So there is no need to use only 10 Bit resolution, except at very high speed. For the µC it does not make a difference if calculation is done with 10 or 12 bit - usually the µC will use 16 or 32 Bits anyway.With just noise there is no real need for a variable anti aliasing filtering. If at all this would be more like choosing one of 3 or 4 complete filter circuits - ranges can be decades and more apart. It's likely easier to even use a 24 Bit ADC (e.g. MCP3911) instead of switchable filters. Sigma delta converters also don't need much antialiasing filtering, even if the sampling rate is reduced at the converter.

author: GK
author_rank: Super Contributor
timestamp: October 30, 2015, 12:17:52 pm
content: Quote from: Kalvin on October 30, 2015, 10:31:15 amI actually provided much of that information and I don't really need help with anything that you've listed; reiterating once more the only real question I needed (past tense; no longer) answering was whether or not it is worthwhile (for FFT computations) to have significantly more bits of ADC resolution than that necessary for the dynamic range of the signal sampled.There isn't an Arduino in sight.

author: Marco
author_rank: Super Contributor
timestamp: October 30, 2015, 03:04:30 pm
content: Quote from: GK on October 30, 2015, 12:17:52 pmAFAIK generally only INL will matter, because generally you will do the FFT over a number of samples significantly larger than the period of the frequency of interest, which will increase your SNR (even without sufficient dither or noise assuming the frequency is not a trivial fraction of the sampling frequency).You'll not a lot of generally's, that's because it depends on a lot of factors.PS.thishas some formulas (see the bit on spectral averaging on page 7 and 8).

author: mark03
author_rank: Frequent Contributor
timestamp: October 30, 2015, 03:29:26 pm
content: Quote from: blueskull on October 30, 2015, 06:31:23 amDither is not required as long as your input signal traverses enough LSBs that the quantization noise can be modeled as white.