Verilog - Inout port giving weird errors - Page 1
Forum section: electronics / general

author: pigtwo
author_rank: Regular Contributor
timestamp: May 08, 2016, 07:07:19 pm
content: Hello all,I'm working on a very basic(and probably poorly coded) SRAM memory controller. I'm running into some difficulty with the inout port that goes to the SRAM chip. The code for the controller and a basic test setup is posted below for reference.Here is the memory controller:http://pastebin.com/CmrnYcHwand here is the basic test module:http://pastebin.com/HEVxYmQJThe parts the are of interest I believe are things to do with the inout port.So the way it is posted in paste bin I don't get an error(in Quartus) but I get a warning that says "Warning (13047): Converted the fan-out from the tri-state buffer "SRAM_Memory_Controller:tb1|DATA" to the node "SRAM_Memory_Controller:tb1|Selector53" into an OR gate" This error comes from the SRAM Controller.And if I simulate this it doesn't work. It will make the inout port act like an input port(as far as I can tell).I was able to get the program to simulate correctly by changing line 24 in the SRAM_TEST module from "DATA = data;" to "data = DATA". Now I'll admit this doesn't make sense to me because if it's an inout port I don't see why the order this is assigned in would make a difference but I don't have a very good understanding so I just went with it. But when I take this to Quartus it gives me this error: "Error (13066): Illegal directional connection from the pin "DATA" to the node "SRAM_Memory_Controller:tb1|Selector53" " This error also comes from the SRAM Controller.I looked these errors up but it didn't look like I was doing what google says would cause these errors.Does anyone know what I'm doing wrong? I feel like there might be a problem somewhere else that is manifesting itself here and I'm not noticing it.Also as a side question, I remembered that hampster_nz had a SDRAM memory controller and so I took a look at how he did the tristate and the like to see if that would give me a clue but he did something very different. He does this for the tristate:Code:genvar i;for (i= 0; i < 16; i = i + 1) begin : xxIOBUF #(.DRIVE(12),.IOSTANDARD("LVTTL"),.SLEW("FAST")) IOBUF_inst (.O(sdram_din),.IO(sdram_data_wire),.I(iob_data),.T(iob_dq_hiz));Which I'm not familiar with but I assume he's using some dedicated IO port to tristate. What would be the advantage of this over something like "assign out = (en) ? 16'bz : data;"?Thank you for the help!

author: Scrts
author_rank: Frequent Contributor
timestamp: May 10, 2016, 03:59:22 pm
content: I am not a Verilog guy, however the error of port being input only usually is thrown when OE signal is not controlled or not connected properly. Check that first of all. If it's stuck at particular state or not connected - the synthesizer optimize out the logic.

author: hamster_nz
author_rank: Super Contributor
timestamp: May 10, 2016, 07:21:58 pm
content: Quote from: pigtwo on May 08, 2016, 07:07:19 pmIf I have a design with a bidirectional signal, after lots of frustration I now always connect it only to a tristate buffer primitive, and then use the data_in, data_out and highZ control signals within the control logic. I've found that if I don't do this my designs are hit-and-miss, and difficult to debug.For example, if the bidir signal is passed from a top level module to an inner module, and I monitor the signal at the top level it seems to break the design.

author: Scrts
author_rank: Frequent Contributor
timestamp: May 10, 2016, 09:00:11 pm
content: Never instantiate a tristate anywhere else than a top level! The inner modules have to have data_i, data_o and data_oe.

author: pigtwo
author_rank: Regular Contributor
timestamp: May 13, 2016, 03:10:17 pm
content: Ok that makes sense. I removed the conditional method of tristating and used a primitive like hampster_nz did and it at least doesn't cause errors. Now I need to figure out how to simulate with Quartus. Unless ModelSim can do it, which I haven't tried yet.Thanks for the help!

author: Scrts
author_rank: Frequent Contributor
timestamp: May 13, 2016, 03:39:55 pm
content: Quote from: pigtwo on May 13, 2016, 03:10:17 pmI usually simulated in, out and oe signals, then left everything rest for the tristate buffer. You can't even use internal logic analyzer to check tristate pin (at least SignalTap doesn't allow this).