Multi-stage BJT amplifier design - Page 1
Forum section: electronics / projects

author: Randall W. Lott
author_rank: Regular Contributor
timestamp: October 28, 2012, 08:57:50 am
content: Here, I have a circuit that has been assigned. There's an input stage biased by a current mirror, whose current is set by R3. The output is fed differentially to Q10 and Q11. The voltages at the collectors of Q1 and Q2 determine the base bias for Q10 and Q11.R1=R2, R10=R11, R13=HighDesired gain is 75-200.2IC12=IC9+IC13What is a good way to pick values that ensures the optimum response?Is there a specific methodology that needs to be used?Should I design the first stage or second stage first?How should the gains be distributed? Setting both stages to a gain of 10 would yield a total gain of 100, but is this smart?I'm not looking for someone to do the work for me. I'm trying to learn, but some guidance would be nice.Thank you!

author: penfold
author_rank: Frequent Contributor
timestamp: October 28, 2012, 10:03:08 am
content: It is usually a good idea to start from the output. That way you can define the bias currents for the previous stages based on the current demand from the stages drawing on them.When you have decided which transistors you will be using in each stage based on current and gain etc. you can tweak the gain of the individual stages based on the gain-bandwidth product (to maximise frequency response) or input bias and offset requirements.

author: Randall W. Lott
author_rank: Regular Contributor
timestamp: October 28, 2012, 10:06:03 pm
content: Thank youpenfold. I assumed that forcing conditions to get what you "desire" would be the smartest way to handle things.All transistors are CA-3046 NPN transistor arrays. I'll be sticking within the audio frequency range, so attenuation past 20kHz is not an issue.My laboratory section is completely out of sync with my lectures and it's creating a lot of problems. We haven't even covered a single BJT amplifier yet. Most of our time has been spent on CMOS logic, manufacturing/device physics, and timing. I honestly don't care about the NMOS channel geometry and its' respective capacitance. I'll look on a data sheet if I want to know that.I understand that the current mirror is simply to ensure proper DC biasing and that the first stages' collector resistors aid in setting the base voltages for the second stage. I do not understand how to calculate the values. I want to engineer this, not stumble upon values that seem to "work".I can't seem to find a way to logically break it down into manageable parts.I've read that VTotal/3=VCE1=VRC=VCE12, but I don't know why. I understand that I would like to get the maximum symmetrical swing, keeping the Qpointequidistant from the Cutoff and Saturation regions.

author: Performa01
author_rank: Super Contributor
timestamp: October 28, 2012, 10:08:03 pm
content: Well, where do we start?This is a tricky project as we have to design it for a given gain, without any negative feedback neither locally nor globally.Generally, it would be wise to put as much gain into the first stage as possible, since this will prevent the 2nd stage from contributing to the total noise. But here we don't have much of a choice in that regard as will become clear rather soon.Due to the lack of local feedback, the gain of the amplifier stages will be just Gm * Rc, where Gm stands for the forward transconductance of the transistor and Rc for the associated collector resistor. Since the quiescent current of the 2nd stage is just twice that of the first one, loading effect will be negligible and we only need to consider the resistors.Gm depends on the collector current and will roughly be 40 * Ic. But now comes the big surprise: since the voltage gain is Gm * Rc it also is 40 * Ic * Rc. Now Ic * Rc happens to be the voltage across the collector resistor, so we can simply state that the voltage gain will be 40 * Urc with Urc being the voltage drop across the collector resistor.That's why we cannot decide on the gain distribution as we like. We rather need to determine a suitable biasing scheme.If we want to put the major part of the total gain into the first stage, this will leave very little voltage drop for the collector resistor of the 2nd stage, hence the base of the output transistor will be close to the positive rail and output voltage swing will be limited to very low amplitudes. From that point of view, we would like to put all the gain into that 2nd stage – but what's the point in having the first one then? Really there is none. But assuming that's just an exercise, so we'll have to make do with that somewhat weird design.Well, what biasing (= voltage levels) will we use? Since the output stage is a single ended design with just a resistor to ground, it is usual practice to set the emitter to approximately 1/2 of the positive supply voltage. With this the voltage drop across the collector resistor of the driver would be some 1.9V which means the majority of the gain (~76) is accomplished here. And only about 1.3 is left for the first stage. This is not what we want.We'll have to put the voltage level of the output stage a bit higher, which helps reducing the gain of the 2nd stage and also has the benefit of a higher voltage drop across R12.This way the resistor can provide the required current to drive the load at the negative peak amplitude more easily. The output transistor on the other hand has a similar issue with the collector resistor of the driver stage, just the current level is much lower so it's easier to deal with.So let's assume we set the base of the output transistor to 4V, resulting in about 3.4V for the emitter. This still means a voltage gain of 40, leaving just 2.5 for the first stage. Not only is this undesirable in terms of noise performance, but also does it leave very little voltage drop for the collector resistors of the first stage, so the bases of the 2nd stage will be far too close to the positive rail and the required output swing cannot be obtained.That's the quirk with this design. It only allows very limited output swing, as it's always limiting at one point or another. If we put a lot of gain in the first stage, the 2nd stage will have the collectors close to the rails due to its low gain, leaving not much room for output swing. If we shift gain to the 2nd stage, the first stage suffers the same phenomenon, and even though it does not matter there as the signal level is still low, the base voltage for the 2nd stage will be close to the positive rail as well, and the collector cannot go down much more than maybe 0.5V below the base potential at best (with a good deal of added nonlinearity that is).The best we can do is an even distribution of gain, that is, 10 for each stage.Since only one output of the 2nd differential pair is used, we are wasting one half of the signal, hence need a gain of 20 there.That means we need a whooping 0.5V across our collector resistors of the 2nd stage, resulting in a collector voltage of 4.5V. The emitter of Q14 is then at some 3.9V.Now we should know what load we intend to drive. Let's assume 10kWith the values determined so far we can already calculate the maximum output swing as well as the maximum value for R12 now. If we have the quiescent current for the 2nd stage at least five times higher than the driving requirements for Q14, the positive limit will be at about 100mV voltage drop across R11, hence the maximum positive swing is 5V - 0.1V – 4.5V = 0.4V. Since waveforms are symmetrical in amplitude, this is also the maximum practicable negative output (even though it could actually go much lower) as we'd otherwise get a heavily distorted waveform. With the bias level of 3.9V at the output (Q14 emitter), the negative peak deviation would be 3.9V – 0.4V = 3.5V.Maximum output is 0.8Vpp or 280mV rms for sine waves. At a gain of 100, maximum input will be 2.8mV rms.At this point it should have become clear that this design has a very limited dynamic range and is just for very small signal levels (and the linearity will nothing to write home about either).The peak load current would be 0.4V/10k = 40µA. In a single ended class A design without current source like this we want the quiescent current at least ten times higher than the peak load current in order to avoid major variations of the base-emitter voltage drop in Q14, hence nonlinearity. So what about 400µA? R12 would then be 3.9V/400µA = 9k75. Well, let's be generous and say we use 4k7 instead, which also means our load resistor can go down to at least 5k if so required.BTW, normally it would be far better to connect R12 to the -5V supply line instead of ground (and make it higher in value accordingly). This would make it look much more like a current source because of the increased resistance at the same current. It could also help increasing the output swing – all these advantages don't come into play with this particular design thoughThe emitter current of Q14 at maximum positive output (3.9V + 0.4V = 4.3V) would be the maximum load current plus the current through R12, that is 40µA + 4.3V/4k7 = ~955µA. Assuming a beta of >100 for the transistor (which is pretty much standard assumption), the base current would be less than 10µA.R11 has to deliver that current at a voltage drop of 100mV, so its maximum value will be 0.1V/10µA = 10k. The base voltage at the negative peak would be 4.5V - 0.4V = 4.1V with no current drawn by Q14, so the current through R11 which is then also the collector current for Q11 would be (5V – 4.1V)/10k = 90µA. Hence with a resistor value like that, the collector current of Q11 would go from zero to 90µA and we do not want a current variation that high as this massively changes Gm and introduces gross nonlinearity.R11 should be made considerably smaller than the maximum value, and according to our previous assumption it has to be at least 5 times smaller. So we choose 2k. With no signal, Q11 collector will be at +4.5V as defined before, so the quiescent current will be (5V – 4.5V)/2k = 250µA. This is also what the current mirror has to be fed with, as we will get twice its value (500µA) as the quiescent current for the entire 2nd differential amplifier due to the paralleled transistors Q9, Q13.So we can already calculate R3 at this stage: 4.4V/250µA = 17k6. Odd value – you would normally choose 18k, but as the real gain tends to be a bit lower than calculated, we should use the next smaller value for initial test, that is 15k.As a side note, R10 is completely useless and should be omitted. It might make the circuit look nice and symmetric, but in fact doesn't have any real impact at low frequencies, and makes things worse at higher frequencies – a discussion that I won't get into here right now as I think it's irrelevant for this project.Since the current of the first stage is already determined to be half that of the 2nd stage by design (of the current mirror), there is not much left to calculate. To get a gain of 10, the voltage drop across the collector resistors of the first stage is half that what we had before (0.25V). Since the current is also just half of what we had in the 2nd stage, the same resistor values apply, i.e. 2k for R1 and R2.There is one major feature - you can use R3 to adjust the gain of the whole thing to exactly what you want it to be, within limits that is. So if you have to build it up to demonstrate its functionality, you can tweak it a bit with next to no effort (just put a 10k trimpot in series with 4k7 in there). Take care to use signals low enough not to drive it into saturation, as stated earlier in this essayOkay, so much about solving this puzzle – and a puzzle it is rather than a particularly useful circuit…Good luck!HerbieEDIT: Initially I didn't take into account that half the signal of the 2nd differential pair is wasted. The article has been adapted and corrected accordingly.

author: Randall W. Lott
author_rank: Regular Contributor
timestamp: October 28, 2012, 10:26:14 pm
content: Quote from: Performa01 on October 28, 2012, 10:08:03 pmHerbie, I'm very impressed! Thank you so much. I've read it once, but I'll come back and read it a few more times. I had a suspicion that this design was rather strange.You've been a great help. I truly appreciate it.

author: Performa01
author_rank: Super Contributor
timestamp: October 30, 2012, 08:12:42 pm
content: Well, it was late here on the opposite side of the pond when I wrote that reply, and of course it had a little flaw. I have edited and corrected the original post, so you might want to have a look one more timeRegardsHerbie