Using UART TX line to supply power when idle - Page 1
Forum section: electronics / projects

author: sebmadgwick
author_rank: Regular Contributor
timestamp: March 07, 2020, 02:42:28 am
content: I am designing a device with a connector for UART TX and RX lines. The device will offer an alternative mode of operation where the UART TX line is not used for data and is instead used to supply power, e.g. 50-100 mA at 3.3 V. A connecting peripheral would be powered by the TX line and send one-directional data on the RX line, similar to how old serial mice would operate.My first idea was to buffer the TX signal through a line driver IC. The TX line could then be held high to supply power. Unfortunately line drivers seem to be limited to supplying no more than ~20 mA.Load switches or similar ICs are not viable because they add output capacitance that would destroy the UART signal.I tested the attached circuit but found this destroyed the UART signal. I would like to support up to 3 Mbaud.I'm now considering using a multi-channel tri-state line driver with all channels in parallel. For example, the 74LVC125ABQ can supply up to 24 mA per channel. The quality of the UART signal would not be compromised by the presence of the high-impedance outputs. However, I'm not keen on this idea because any imbalance between the channels risks a runaway failure.Any suggestions?

author: NiHaoMike
author_rank: Super Contributor
timestamp: March 07, 2020, 02:59:12 am
content: Replace Q8 with a short from drain to source (less capacitance for the microcontroller to drive), then add a small N channel MOSFET to connect the output to ground if the input is high. You might have to add a resistor in series with that MOSFET to limit the cross conduction current. If you want the output to be noninverted, add an inverter gate in front of the input.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: March 07, 2020, 03:27:53 am
content: I should clarify that the schematic in my previous post is intended to supply power or be high impedance. It is connected in parallel with the UART TX signal, it does not drive the UART TX signal.

author: NiHaoMike
author_rank: Super Contributor
timestamp: March 07, 2020, 03:49:27 am
content: Try a smaller MOSFET with less capacitance. Or a PNP transistor.

author: TomS_
author_rank: Frequent Contributor
timestamp: March 08, 2020, 10:43:55 am
content: Check the maximum current that the VCC pin of the 74LVC125ABQ can handle. It may be less than the sum of all outputs.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: March 19, 2020, 09:58:25 pm
content: Thanks for the hint about capacitance. I've been playing with low output capacitance MOSFETS and I am considering the attached circuit.The goal is forOutputsupport up to 3 Mbaud UART or to supply up to 100 mA when UART functionality is not required.The BOM already includes inverters so their use would be preferable over N-channel parts. The UART signal source (shown in schematic) only has weak driving capability and so requires some kind of buffering to overcome the MOSFET output capacitance.Is this circuit poor practise? I am concerned that the propagation delay in G2 will causes a momentary clamp of 3.3V to ground. I believe this is the explanation for the messy falling edge shown in the attached screenshot. Thanks in advance.

author: NiHaoMike
author_rank: Super Contributor
timestamp: March 19, 2020, 11:39:42 pm
content: Add a resistor in series with the second inverter output to limit the current, try 47-100 ohms for a start. You'll probably also want another resistor of 33 ohms or so in series with the gate to prevent ringing.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: March 20, 2020, 12:42:47 am
content: Adding a resistor to the MOSFET gate has no effect. The attached screenshot shows 3 different resistances between G2 output andOutput.The negative spike ~20ns before the falling edge is a separate phenomenon from the ringing. 20ns is much larger than the typical 1 ns propagation delay of the inverter so my previous interpretation was incorrect.I'm not so much asking for assistance tuning this circuit, I'm asking if the arrangement is poor practise. I'm essentially using a logic gate output to drive a floating MOSFET drain low... it feels a bit hacky.

author: NiHaoMike
author_rank: Super Contributor
timestamp: March 20, 2020, 01:25:57 am
content: It looks like the optimum resistor value is just above 100 ohms, since the ringing is reduced a lot with 100 ohms but not completely and 470 ohms noticeably degrades the fall time.The gate resistor might need to be quite big for a small MOSFET - try 470 ohms or so. (I'm used to big MOSFETs where 4.7 ohms is a good starting point...)

author: David Hess
author_rank: Super Contributor
timestamp: March 20, 2020, 10:39:51 am
content: Quote from: sebmadgwick on March 07, 2020, 02:42:28 amOr implement a discrete driver. Maybe use a strong pull-up and weak pull-down. Or I might try using a paralleled strong pull-up transistor which activates after a long high time.QuoteWhat imbalance are you referring to? Is that imbalance between paralleled drivers?I like the idea of using paralleled 74LVC125s but I would use all 8 drivers in parallel from two separate quad chips, and might use the 74AC125 or 74HC125 instead. Extra bulk power supply decoupling should be close by.Quote from: sebmadgwick on March 20, 2020, 12:42:47 amNo, there is nothing wrong with driving a MOSFET gate with logic gate unless the gate capacitance is so large that it causes problems or the limited drive is not fast enough. It used to be commonly done in lower frequency switching regulators and inverters.

author: sebmadgwick
author_rank: Regular Contributor
timestamp: March 20, 2020, 11:46:26 am
content: The attached schematic and screenshot is about as good as the 2 inverter + MOSFET solution will get. The falling edge is delayed by 90 ns. Not ideal for 3 Mbaud.My original post and suggestion of using paralleled 74LVC125 drivers would use a GPIO to enable/disable power. If was to go down this route then the solution is a low output capacitance MOSFET (e.g. DMG1013UW-7). I'm now interested in a solution that is able to source current whenever UART is left idle (high) and so not require GPIO control. Perhaps paralleled 74-series drivers could be used.Quote from: David Hess on March 20, 2020, 10:39:51 amIf current is not split evenly between all drivers then the driver under the greatest load may fail, this would then increase the load on the remaining drivers so that the next driver under the greatest load would fail and so on. This is what I mean by an imbalance causing a runaway failure.

author: David Hess
author_rank: Super Contributor
timestamp: March 20, 2020, 07:07:41 pm
content: Quote from: sebmadgwick on March 20, 2020, 11:46:26 amThat is very unlikely to ever be a problem with CMOS gate outputs because their channel resistance is relatively high. For instance HCMOS is about 25 ohms at 5 volts.The output voltage requirements are usually what dictate how many outputs are needed in parallel to reduce voltage drop to an acceptable level rather than the output current requirements.