3 Phase FET Heat Dissipation Calculations (Someone to confirm Methodology)  - Page 1
Forum section: electronics / projects

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 12, 2018, 06:11:44 pm
content: Hi,As part of my degree thesis I am building a BLDC motor controller, on which I have a main thread which can be found at the end of this post.I have made some calculations to determine what Hear losses I will have on the FETs. I found 2 application notes from infineon on which I calculated the heat losses based on my parameters.Attached I have included a PDF which shows off step by step the calculations I made. I have also included an Excel file which shows the heat losses as a function of the Duty Cycle Used. The links to the application notes can be found in the PDF. Please note I am using the !20 degree switching strategy.If anyone has the time, can you guys give a quick look to see if I made any mistakes in my methodology/calculations. Marked in red in the PDF is a parameter which I am not really sure about.Here are the results I gathered:Here are the losses at 30kHz switching frequency:Here are the lossses at 10kHz switching frequency:As can be seen with the reduced switching frequency, the high side mosfet losses improved significantly, however the low side mosfet losses were largely unchanged since the diode losses were dominant.Hope some can confirm my work!Feel free to use the excel files and date I have postedCheers!Link to my Project:https://www.eevblog.com/forum/projects/bldc-motor-controller-rc-snubber-design-waveforms/

author: fourtytwo42
author_rank: Super Contributor
timestamp: February 12, 2018, 08:56:20 pm
content: Just a gut feeling something is drastically wrong as I see no reason for the large imbalance between low & high side!

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 12, 2018, 09:10:57 pm
content: Quote from: fourtytwo42 on February 12, 2018, 08:56:20 pmIf I understood the referenced AN correctly there will be an imbalance between the high and low side fets. If you refer to the images below, you'll se that during the off time high side mosfet the low side body diode will be conducting as stated in the AN. This means that the high side will have only the mosfet losses (i.e. conduction + switching), whereas the low side mosfet will have mosfet losses (conduction+ switching) and diode losses hence the big increase in dissipation.NAturally this is from what I read up on and understood. I am not a 100% sure and thats' why I'm Asking for helpWhat do you think?Cheers

author: fourtytwo42
author_rank: Super Contributor
timestamp: February 13, 2018, 08:01:00 am
content: I think I would verify the equations by simulating the circuit in LTspice or MathCad to ensure your understanding of what conducts when is correctI never rely on one means only to get results, crosschecking is vital.

author: Siwastaja
author_rank: Super Contributor
timestamp: February 13, 2018, 09:00:30 am
content: Something is horribly wrong if you are having freewheeling diode losses in a 3-phase motor control bridge. The controller needs to turn the FET on to reduce the losses. Fix this first. (Never heard the term "120 degree switching" but if this means giving up synchronous rectification, I think it's fundamentally broken. Diode losses are huge in a low-voltage BLDC application and why would you want them, you have the mosfets there!)You are still going to have body diode reverse recovery losses + diode conduction losses during the FET drive deadtime, but these should be almost insignificant, especially at lower f(sw). (Use minimum deadtime possible - driver ICs often give you more deadtime than you'd want even with the lowest deadtime setting (if adjustable)).

author: max_torque
author_rank: Super Contributor
timestamp: February 13, 2018, 12:52:34 pm
content: You really need to run with "centre aligned" pwm as your effective switching frequency is double your fundamental pwm frequency, so you get half the ripple current for no extra switching losses!

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 13, 2018, 02:11:57 pm
content: Quote from: fourtytwo42 on February 13, 2018, 08:01:00 amI have all parts and the PCB ready to go. I plan on soldering the circuit in the next few days so rather than simulating it I will test it on the real thing. I have acquired a thermal camera so I can check weather there is such a large disparity between the High and low side FETS.Quote from: Siwastaja on February 13, 2018, 09:00:30 am120 degree switching is one of the most basic trapezoidal switching scheme. It is described in the AN I linked in the document I attached. I am using the UCC20520 where by I am adjusting the deadtime with a resistor, IIRC I set it to around 300ns. My software is quite minimalist and I know has a lot of room for improvement, however that is not my main goal currently. I am aiming at just minimizing my hardware as much as possible, determining the effect of non essential components of on performance (waveform) and trying to find the most effective good performance hardware along with collecting general data.I have already implemented pure 3 phase control before but for this project I am using a limited uC, the (LPC2119) which limits what I can do. After I finish this phase I plan to switch to the STM32F4.For now I just want to confirm whether the calculations are within reason.Quote from: max_torque on February 13, 2018, 12:52:34 pmAs stated above I will improve my software in the future when I switch to the STM32F4. I agree center aligned is the way to go as it also improves your THD. However I will implemented this in the future for now I am sticking to consolidating my hardwate

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 17, 2018, 07:52:41 pm
content: Quote from: Siwastaja on February 13, 2018, 09:00:30 amI have done some more reading on your suggestion and have implemented synchronous rectification as you suggested. No I am looking a t how to calculate my new heat losses. So thanks for that!However if I am understanding correctly, the low side mosfets should still face larger losses than the high side mosfets since, you have the synchronous losses through the fets and body diode losses during deatime along with the conduction losses. Whereas with the high side fets, you only have conduction losses along with some switching losses

author: Benta
author_rank: Super Contributor
timestamp: February 17, 2018, 09:55:16 pm
content: The power loss calculations in your original post are completely off somehow.First, the lower FETs are switched statically for 120 degrees commutation, and the upper FETs are also switched for 120 degrees commutation and PWMed at the same time (this is from your timing diagram in post#2).Is that right?So, the losses in the lower switches increase with increasing PWM (due to increased motor current), which is reasonable (although the very low losses are strange. Is there a scaling error here?)But the upper FET losses are abnormal. Normally, their losses would mirror the lower FETs, plus a linearly increasing loss from PWM switching. Switching frequency is constant, so you have the same number of transitions at any time, but increasing current (like the low sides).A better way of estimating power loss is driving both upper and lower side FETs statically for 120 degrees commutation. Then you can add the high frequency switching losses on top afterwards.The free wheeling diodes should not contribute significantly to power loss in this setup, they only deal with stray inductance.

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 17, 2018, 10:59:52 pm
content: Quote from: Benta on February 17, 2018, 09:55:16 pmYes that is 100% correct. IQuote from: Benta on February 17, 2018, 09:55:16 pmI think in this sentence you have switched the high side and low side Mosfets.Having said that I have calculated the heat dissipation as you suggested. Were I calculated the conduction losses fore both low side and high side mosfets. Then I also added the switching losses only for the high side losses, since the low side mosfets are constantly on/off.Here are my calculations for this and it makes a lot more sense, having said that I did not include the diode losses or synchronous fet losses. What do you think?

author: Benta
author_rank: Super Contributor
timestamp: February 18, 2018, 09:47:30 am
content: QuoteWithout going into the calculations, it looks a lot more like I'd expect.

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 22, 2018, 05:30:19 pm
content: So I have taken your guy's advice and simulated the circuit in LTspice. I tried making the circuit as accurate to real life as possible. I have a rise time of around 1us which I measured from the hardware and the rest (parasitic inductances etc I guesstimated)The load across the bridge are the phases of my motor.Naturaly this would only be showing switching for part of the commutations steps. So to summarize, I switch on M3 and M1 to roate the motor. I keep M1 always on while I switch off M3, and switch on M2 which acts as the synchronous FET.Below is my calculated power dissipation across M3, it has the switching losses along with the conduction losses (2W when the FET is on). The average can be seen there (In practice this value can be dived by 3 since for the rest (2/3) of the commutation sequence this FET would be off)Please bear in mind this was my first time using LTspice. Are there any glaring errors which I made, maybe in my parasitics or anything?Power DissaptionVoltage/Current

author: ransonjd
author_rank: Contributor
timestamp: February 22, 2018, 06:23:29 pm
content: Assuming you're using some sort of high-side gate driver, you should model your high side gate drive as a voltage between the gate and the source.

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 22, 2018, 07:12:26 pm
content: Quote from: ransonjd on February 22, 2018, 06:23:29 pmI am using a high side driver, however I think the way I implemented it in the simulation, for the purposes of the simulation should be fine as I did it that way to keep things simple. I don't think it should effect the simulation correct?Naturally in the actual hardware I implemented it between gate and source.

author: ransonjd
author_rank: Contributor
timestamp: February 22, 2018, 07:36:10 pm
content: Hard to say. With a fixed ramp time, the gate drive slew rate will be faster for the top fet. This could affect the speed of turn-on and turn-off, and consequently the switching losses. You're also driving more energy through the gate capacitances, but I'm not sure if that's going to show up the way you're measuring it. That said, unless your gate drive model actually approximates your driver, your switching losses are really an educated guess.

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 22, 2018, 07:48:35 pm
content: Quote from: ransonjd on February 22, 2018, 07:36:10 pmI have measured the actual rise times and fall times, in the actual hardware and they come a almost 1us for all fets hence why I modeled it like thatEdit: Grammar

author: Siwastaja
author_rank: Super Contributor
timestamp: February 22, 2018, 08:29:41 pm
content: I can't understand what "simplicity" it brings you to connect the top fet gate drive that weird way. Just connect your "gate drive" voltage source like the actual circuit (hopefully) does - simply and normally between G and S. Now it's between the top fet's gate andbottomfet's source.Or maybe there is a misunderstanding? Nothing wrong how you model things - you just connected the top side FET driver voltage source incorrectly, maybe by accident? Fix that.

author: nuno
author_rank: Frequent Contributor
timestamp: February 22, 2018, 09:56:09 pm
content: A short article:https://www.eetimes.com/document.asp?doc_id=1225701

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 23, 2018, 07:19:42 pm
content: Right, So I took your advice and molded the whole thing even using a gate driver and the correct resistance. Granted the gate driver I chose is not the one I am using in practice however I think it should be close enough. I am using the UCC20520, I went on the TI website downloaded the spice file, however when I imported it in, it did not work properly.I am new to LT Spice so I probably did something wrong when I imported the file.Anyways I did the simulation and here are my results.I have a coupple of questions:1, Is the body diode of the mosfet in real life modeled within the transistor model? Since I am not sure I added one myself2. Are the parasitic inductance I added in the bridge realistic at all ?3. Should I take the absolute value of the power dissipation since I have negative values of power?Thanks for your constructive criticism learning a lot!!Edit: Updated image

author: nuno
author_rank: Frequent Contributor
timestamp: February 23, 2018, 08:25:03 pm
content: Caps have ESR and ESL, and there's some inductance on the connection driver - FET too. There's also an important inductance from the power supply to the bridge that you're not modeling.

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 24, 2018, 09:47:15 am
content: Woops my mistake, I moved the supply around to the other side and it messed up my circuit haha. All fixed now the caps also have the relevant ESR and ESL.Here are my results. For the high side fet I added the switching losses and the conduction losses, took the absolute and divided it by 3 since it would only be used for a third of each electrical cycle.For the low side fet, I took the conduction losses of the fet that is always on and added the switching losses and conduction losses of a synchronous fet, since each fet would do both these tasks in a single electrical cycle. As per above I took the absolute and divided it by 3 for the same reasonsThanks!

author: Glenn0010
author_rank: Regular Contributor
timestamp: February 24, 2018, 10:59:15 am
content: So I ran the simulation at different Duty Cycles and frequencies. Here Are my result.Do these results make sense?

author: nuno
author_rank: Frequent Contributor
timestamp: February 24, 2018, 07:02:51 pm
content: There should be an inductance between the power source and the capacitor (battery wiring).It's easier to compare graphs if they use the same scales, just a suggestion.I can't say much more about the results, they seem linear with frequency, as I would expect. At 100% duty cycle you don't have switching losses anymore, so the total dissipation drops, also makes sense to me.

author: SparkyFX
author_rank: Frequent Contributor
timestamp: March 09, 2018, 01:07:51 am
content: Quote from: Glenn0010 on February 24, 2018, 10:59:15 amFor the first graphs... i could not make a sense out of them and assumed a resistive load. But the duty cycle itself would not really make a difference the amount of switching processes per time remains the same, so the same amount of energy is heating up the switching element. It is distributed a little bit different over time, allowing to transfer heat at a different time, but probably evens out for 10kHz or more.But when switching inductive loads your new graphs do match what would be my expectations, as the current in this electromechanical system rises throughout the duty cycle and the later the switch occurs, the higher the switched current and its share in the form of power dissipation. So the loss in the switch kind of reflects the properties of the coil that is to be switched and therefore the rotor and mechanical load as well. So it might be necessary to include that throughout all calculations.

author: Glenn0010
author_rank: Regular Contributor
timestamp: May 08, 2018, 03:27:17 pm
content: So I forgot about this,But as you guys suggested here are all the plots on the same scale. Not 100% sure about the "magnitude" of the rusults as they seem a bit too high but at this point I am going with them.