Ethernet and FPGAs? - Page 1
Forum section: electronics / general

author: Thane of Cawdor
author_rank: Regular Contributor
timestamp: September 05, 2021, 09:32:26 am
content: I am working on an FPGA design and I'm on a journey to connect an ethernet port (10Mbps) to the FPGA by using the least amount of FPGA IO. From reading, there are a two main options:1. RJ45 -> magnetics -> ethernet controller (MAC -> PHY) -> FPGA2. RJ45 -> magnetics -> PHY -> FPGA (using RGMII, RMII, MII) and ethernet IP coreHas anyone here had experience with a similar design and recommend any method?

author: rstofer
author_rank: Super Contributor
timestamp: September 05, 2021, 02:53:52 pm
content: That ENC28J60 has been around for a long time and is available on a small PCB for about $9https://www.amazon.com/HiLetgo-ENC28J60-Ethernet-Network-Arduino/dp/B00WX1NRO0This approach still leaves the daunting task of implementing the TCP/IP (or UDP/IP) stack in FPGA fabric unless you are using a programmable CPU core but there is a project at Opencores.org that implements the stack and it uses the ENC28J60You may have to register to get to the file but it does exist.https://opencores.org/projects/tcp_ip_core_w_dhcpI used the ENC28J60 with the uIP stack (predecessor to the lwIP stack) a long while back with a LPC2106 ARM board. It made a connection with a Linux server and grabbed music files to play. Just a demonstration, really but it all worked well.

author: Thane of Cawdor
author_rank: Regular Contributor
timestamp: September 05, 2021, 03:38:41 pm
content: ThanksI have been reading into that chip and it looks quite good, I shall continue the research. Do you by chance know the logic/memory resources (approximately) required to implement the required cores? Out of interest, have you had any experience working with 1000BASE-T ethernet? If so, do you need a high-end FPGA to get 1Gbps to work with available MAC IP?

author: rstofer
author_rank: Super Contributor
timestamp: September 05, 2021, 04:12:36 pm
content: The Artix A7 has onboard PHY and MAC and can do 10/100 Mbps. The Opencores project I linked above struggles to make 10 Mbps and that is primarily a limitation of the ENC28J60 (10 Mbps). The problem with the project may be that it will only handle one connection at a time. I don't know what to think about the limitation. Both of my projects only required one connection.https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/The Opencores project doesn't talk about resources, AFAICT.The high dollar Nexys Video Artix-7 will do 10/100/1000 Mbpshttps://digilent.com/shop/nexys-video-artix-7-fpga-trainer-board-for-multimedia-applications/Here's a white paper regarding Xilinx's IP core for lwIPhttps://www.xilinx.com/support/documentation/application_notes/xapp1026.pdf

author: Thane of Cawdor
author_rank: Regular Contributor
timestamp: September 05, 2021, 04:31:02 pm
content: Thanks for the informationI am interested in using a lower cost Actel part like the IGLOO series, hence the interest in the resources. I imagine it would be difficult to achieve greater than 10Mbps due to the reason you mentioned and unlike the higher end IGLOO2 series, there is no ethernet MAC IP for the device. Thanks for the links, I'll have a look through them now.

author: rstofer
author_rank: Super Contributor
timestamp: September 05, 2021, 04:52:27 pm
content: That's why I went with the mbed LPC1768. It had a 100 Mbps MAC built on the card and the lwIP stack supported Berkeley Sockets - all I needed for my simple project.https://www.digikey.com/en/product-highlight/n/nxp-semi/mbed-lpc1768-development-boardI still had to write the state machine to make the connection, transfer the data and terminate the connection. Not a big deal...There are 126 in stock at DigiKey...I use the online mbed development tools:https://os.mbed.com/ETA:This project was created in June 2012 so it's been a while. It still compiles so I assume the libraries are still available.

author: james_s
author_rank: Super Contributor
timestamp: September 05, 2021, 06:03:43 pm
content: I played around with the ENC28J60 chips several years ago, IIRC they're pretty much crap. They run hot, consume a lot of power, and are very buggy. I didn't think people were using them much these days, all of the consumer stuff has switched to wifi.

author: nctnico
author_rank: Super Contributor
timestamp: September 05, 2021, 06:38:07 pm
content: For an external ethernet chip the Wiznet chips are a much better choice nowadays but it is still good to have some kind of processor inside the FPGA to deal with handling connections.

author: Bassman59
author_rank: Super Contributor
timestamp: September 06, 2021, 02:16:08 am
content: Quote from: Thane of Cawdor on September 05, 2021, 04:31:02 pmI'm with nctnico on this -- if you need to put Ethernet into an Igloo FPGA, use the WizNet WZ5500. It interfaces to the FPGA over SPI. But as he notes you still need something smart inside the FPGA.Perhaps you can use the Igloo M1 variant, which lets you embed an ARM Cortex-M1 in the FPGA? Then you can use some standard driver software (WizNet has code!) to handle your data.

author: rstofer
author_rank: Super Contributor
timestamp: September 06, 2021, 03:12:02 pm
content: Quote from: nctnico on September 05, 2021, 06:38:07 pmThe Wiznet 6100 seems like a good place to start. It handles all of the protocol details and the SPI interface is easy to implement on the FPGA. Packet buffering is provided on the 6100 and it supports 8 sockets.https://www.mouser.com/ProductDetail/WIZnet/W6100-MKR-Ethernet-Shield?qs=PzGy0jfpSMsWeVRjaTiNjQ%3D%3DSo, I ordered one! There should be 3 left in stock...

author: james_s
author_rank: Super Contributor
timestamp: September 08, 2021, 03:30:43 am
content: A friend of mine used a Wiznet ethernet part in a project a while back, must have been around 15 years ago. I remember him saying it worked really well, though at the time at least it was an expensive part.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 08, 2021, 04:59:02 pm
content: The Wiznet chips seem to be pretty good indeed. Now, don't expect very high data throughput with them, of course. If you need the throughput you can get with 1Gbps Ethernet, look elsewhere.

author: ejeffrey
author_rank: Super Contributor
timestamp: September 08, 2021, 07:50:18 pm
content: I've used the wiznet 5500 with a cortex M0+ using their provided "almost BSD socket" library and DHCP client. They work pretty well for what they are. You won't get high performance of course, but good enough for the intended applications.The fixed socket table is kind of annoying for TCP server applications, but I wouldn't recommend that on a microcontroller anyway. A TCP client would be fine, or UDP applications if you can tolerate its limitations. It doesn't support HTTPS/TLS or any sort of serious authentication and you probably aren't going to implement that on a simple microcontroller either, so it is best used on a private network in most cases.

author: AaronLee
author_rank: Regular Contributor
timestamp: September 09, 2021, 12:10:55 am
content: Another vote for Wiznet. That solution has worked well for me, as well as Zynq FPGAs with the PS side controlling the Ethernet and using LWIP.

author: laugensalm
author_rank: Regular Contributor
timestamp: September 10, 2021, 05:31:06 pm
content: Wiznet W5500 is fine for only up to 4 concurrent TCP streams (aka sockets). However, malicious users on the network can cause those chips to stall (requiring reboot), so for more robustness I went for a Ethernet core, see alsohttps://www.eevblog.com/forum/fpga/1gb-ethernet-core/.Logic consumption isn't that bad, porting a proper stack is most of the work though (which means, you'll need to have the resources for a compact CPU core).

author: Scrts
author_rank: Frequent Contributor
timestamp: September 10, 2021, 07:22:23 pm
content: Quote from: evb149 on September 05, 2021, 04:44:35 pmYes, I've done this with Cyclone III utilizing Altera Tri-Speed MAC, Nios II without RTOS & LwIP 1.4.0. This was about 10 years ago...

author: zkf0100007
author_rank: Contributor
timestamp: October 13, 2021, 05:21:57 am
content: https://www.fpga4fun.com/10BASE-T0.html

author: radiolistener
author_rank: Super Contributor
timestamp: October 14, 2021, 02:20:07 am
content: Some time ago I was used cheap Chinese LAN8720 Ethernet PHY 10/100 module.https://www.aliexpress.com/item/33037526970.htmlIt is cheap, very simple and provides 10/100 RMII interface. Works very good and stable, almost no heating. The advantage of this module is that it doesn't requires a lot of signal wires. You're needs just 7 wires to use PHY (+2 for GND and VCC) and 2 additional wires for MDIO bus to configure it's registers. It works from 3.3V power supply.The only con is that it doesn't supports 1 gigabit speed, the max ethernet speed for LAN8720 is just 100 megabit.Since I need high speed transfer, later I switched to QMTECH board with RTL8211EG, it needs much more signals than LAN8720, but allows to use 10/100/1000 M speed.So, if 10/100 M ethernet speed is good enough for your needs, then that LAN8720 module will be the best choice. But try to find some FPGA starter kit board which already has ethernet PHY on the board, it will be much more convenient when you don't have extra wires and modules

author: asmi
author_rank: Super Contributor
timestamp: October 14, 2021, 04:06:05 am
content: Actually the most pin-efficient solution is SGMII. But it requires FPGA which can do 1.25Gbps over differential pair. Something like 7 series speed grade 2 or higher. Or slower one, but with gigabit transceiver.

author: radiolistener
author_rank: Super Contributor
timestamp: October 14, 2021, 05:14:39 am
content: Quote from: asmi on October 14, 2021, 04:06:05 amfor GMII PHY you're needs to be very careful with transmission lines layout and length. For SGMII it will be even more important.

author: jeremy
author_rank: Super Contributor
timestamp: October 14, 2021, 08:18:29 am
content: Quote from: radiolistener on October 14, 2021, 05:14:39 amSGMII is actually easier than GMII; your only problem is really just routing a single diff pair. And it is only 1.25Gbps, so as long as you use a calculator for the impedance matching, you should be able to make some fairly long traces without much effort.As for the original post, you don't need to use a full MAC if you just want to get data from FPGA to PC as a starter project and can plug the device straight into the PC, you can just write the raw ethernet frame for a UDP packet straight to the PHY and it will work (though the OS may force you to assign a static IP to the PC).

author: ejeffrey
author_rank: Super Contributor
timestamp: October 14, 2021, 08:44:42 am
content: Quote from: radiolistener on October 14, 2021, 05:14:39 amSgmii is actually pretty easy. There is a single differential pair in each direction and length matching between tx and rx is not critical. Length matching withing the diff pairs is important but not hard to accomplish as they will be routed together from adjacent pins. You can invert the polarity in the fpga if you need to.

author: jeremy
author_rank: Super Contributor
timestamp: October 14, 2021, 09:49:42 am
content: If I recall the tx and rx pair don’t have any length matching requirements at all (between tx and rx, you still need to length match the pairs + and -). More of the issue is ensuring that clocks are stable on both ends with low jitter.

author: marcov
author_rank: Newbie
timestamp: July 16, 2024, 01:17:36 pm
content: Quote from: laugensalm on September 10, 2021, 05:31:06 pmThe W5500 has 8, the older W5100 only has 4.QuoteDo you have more information about that? Is it a silicon issue or in the software libraries?

author: laugensalm
author_rank: Regular Contributor
timestamp: July 16, 2024, 09:27:29 pm
content: Quote from: marcov on July 16, 2024, 01:17:36 pmIt's been a while ago (like 8 years), but if I recall right there were several issues with SYN packets, some of those could be solved. But we found one scenario where the chip would totally stall and only recover by a hard reset, losing all TCP connections, obviously. It seemed past this point no more possible to force closing the connection by the CPU. So, I'd assume a firmware/silicon issue.Eventually, it was cheaper to integrate a bare bone ethernet core plus stack that could be verified to withstand bad packets by simulation.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 16, 2024, 09:44:05 pm
content: There are a few SPI interface + IRQ line 10/100 PHYs from AsixI used them successfully in moderate quantity (1000 pcs) with STM32 and small fpgas. they work.they are about $1 eachhttps://www.asix.com.tw/en/product/EmbeddedEthernet/1-Port_Ethernet/AX88796Cincludes buffer sram, mac , phy, just add magnetics. happy to provide the code of the micro that talked to it from FreeRTOS+TCP

author: asmi
author_rank: Super Contributor
timestamp: July 17, 2024, 01:45:16 pm
content: I seriously doubt these things can get anywhere close to 100 Mbps in real world, so if you need that bandwidth, MII/RMII PHY is the only way to go. But PHY chips are not that much more expensive.

author: slburris
author_rank: Frequent Contributor
timestamp: July 17, 2024, 06:19:02 pm
content: If you want to go out of box a bit, and leave the network heavy lifting elsewhere, how about an ESP32 with ethernet, such as WT32-ETH01?About $15https://www.amazon.com/EC-Buying-WT32-ETH01-Development-Bluetooth/dp/B09Z298QJQ/andhttps://github.com/egnor/wt32-eth01You should be able to set it up as an SPI slave, or have the FPGA be an SPI slave and let the ESP32 be the master, depending on your needs.

author: asmi
author_rank: Super Contributor
timestamp: July 17, 2024, 08:35:07 pm
content: Quote from: slburris on July 17, 2024, 06:19:02 pmWhat's the point of that, if OP offers essentially the same thing, but with less code, and for only $1?

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 17, 2024, 09:03:16 pm
content: Quote from: asmi on July 17, 2024, 01:45:16 pmYeah but for some basic IP interaction and say 2-5 Mbps of throughput , the ASIX chip is hard to beat.A good , industrial PHY on RMII is about $2-$3 (in 250 pcs) . not much.I'd avoid ESP32, seems like putting something else annoying in the way.Either let the ASIX chip do the lot for you on SPI, you throw down a soft core MAC on the fpga, or use a low end ZYNQ or Polarfire SoC ($30) with hard MAC. .

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 17, 2024, 09:12:26 pm
content: Quote from: radiolistener on October 14, 2021, 05:14:39 amNo, that is not the case. Not at all.All the parallel PHY interfaces are really easy to lay out if they're < 6 inches long.Just make sure the TX and RX clock are ( a few mm) longer than any data or control line - and use a PHY chip that supports extra delay to be inserted internally in the clock outputs. WHich is pretty much all of them. and you can't go wrong.And ensure your tx and rx clock traces are free from crosstalk- give them a wide birth on the PCB at least a gap of 3 or 4 layer heights. the data lines you can jam them up next to each other if short. keep them away from the clock trace.SGMII is something different and not applicable for this op- it requires transceivers (clock recovery) - UNLESS the op needs optical isolation for the job. Then, SGMII + SFP transceiver is a good option (but it is NOT low power LOL) ... EThernet provides enough galvanic isolation for most jobs.anothe roption is SPE, uses a single pair at 1km (10 Mbps) or 100m (100 Mbps) , and supports transformers, isolation, and there are SPI interface chips with onboard MAC and PHY - nice eh? ADIN1100 , ADIN1110. SPE is my go-to for industrial, now.glen

author: asmi
author_rank: Super Contributor
timestamp: July 18, 2024, 03:13:22 am
content: Quote from: glenenglish on July 17, 2024, 09:12:26 pmSGMII is simply a serialized version of GMII, it's been designed by Cisco to make connecting a lot of PHY chips easier. There are a number of PHY chips on a market which support SGMII natively (for example Marvell 88E1512 or 88E1514). 7 series FPGA with speed grade of 2 and higher support 1.25 Gpbs over any differential IO pair (no need for dedicated transceivers) as almost all IO cells (48 out of 50 in any IO bank to be exact) contain SERDES module, which has a specific architecture to do a 4x oversampling to aid in extracting data from the incoming stream without clock recovery module. You can take a look at XAPP523 appnote for detailed explanation of how to implement that. Also a version of SGMII overclocked to 3.125 Gbps is often used to connect 2.5G PHY to MAC.Then there is also a QSGMII standard which is essentially 4 SGMII streams time-multiplexed into a single 5 Gbps stream, it further reduces the number of connecting traces, and allows implementing multi-port PHYs without obscene number of pins on a package. Example - Marvell 88E1548, which is a quad channel 10/100/1000 PHY, which can connect to MAC either via 4 SGMII channels, or a single QSGMII channel.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 18, 2024, 09:05:08 am
content: Yes, that is true, but I would put that in the 'expert' class.

author: Mahagam
author_rank: Regular Contributor
timestamp: July 18, 2024, 10:29:32 am
content: And for 'novice' class you can usehttps://www.fpga4fun.com/10BASE-T.html

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 19, 2024, 02:00:24 am
content: Quote from: Thane of Cawdor on September 05, 2021, 09:32:26 amIf you are after a truly slow and minimal implementation, I assume that you are going to have fixed frames- IE no dynamic ability, except for the data, and the packet it will send will be (almost) the same every time... (Otherwise, you'd need a soft microcontroller , RAM etc etc ) In that case, you dont need at all- you'd be generating the frame for the PHY side directly if its 10 Mbps. - you might get away without a PHY if you have a good differential receiver IO for the FPGA. You dont need much for 10 Mbps over 100m of UTP .?

author: DiTBho
author_rank: Super Contributor
timestamp: July 20, 2024, 04:21:45 am
content: MPU + Net + PHYinterfaced via SPI to the FPGA

author: nctnico
author_rank: Super Contributor
timestamp: July 20, 2024, 02:47:56 pm
content: Quote from: DiTBho on July 20, 2024, 04:21:45 am= Wiznet or the Asix chip.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 20, 2024, 10:37:04 pm
content: The OP was only asking for a 10Mb Ethernet link. The cheapest Wiznet chip of the bunch would do. No need to bother with anything more elaborate and more expensive IMHO.A MCU-based solution is not going to be cheaper - say, a CH32V307 will not be cheaper and will require firmware, which is a PITA unless you really have some use for an additional MCU for other purposes.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 20, 2024, 10:46:14 pm
content: nothing back from the original poster. probably has posted the question in half a dozen forums simultaneously... and forgotten about this one.