LTspice gate parameters - Page 1
Forum section: electronics / projects

author: Wimberleytech
author_rank: Super Contributor
timestamp: May 01, 2020, 08:04:15 pm
content: What gives? I seldom use logic gates in LTSpice. If I need one, I generally just make it out of MOSFETs.Today I thought I would build a logic circuit using the digitallib.LTSpice seems to ignore the dynamic parameters (e.g., td).What am I doing wrong.* F:\Documents\LTspiceXVII\nonOverlap.ascXU1 N001 N005 N002 NAND_2 Trise=50n Tfall=50n td=50nXU2 N004 N008 N006 NAND_2 Trise=50n Tfall=50n td=50nXU3 N001 N001 N008 NAND_2 Trise=50n Tfall=50n td=50nV1 N001 0 PULSE(0 5 0 .1u .1u 50u 100u 100)XU4 N002 N002 N003 NAND_2 Trise=50n Tfall=50n td=50nXU5 N006 N006 N007 NAND_2 Trise=50n Tfall=50n td=50nXU6 N003 N003 N004 NAND_2 Trise=50n Tfall=50n td=50nXU7 N007 N007 N005 NAND_2 Trise=50n Tfall=50n td=50n.tran 200u.lib DigitalLogic.lib.backanno.end

author: Ian.M
author_rank: Super Contributor
timestamp: May 01, 2020, 08:21:03 pm
content: Quote from: LTspice manual: A. Special FunctionsYou *MUST* force a timestep an order of magnitude smaller than the rise/fall times or propagation delay during transitions by settingtripdtaccordingly for each gate instance, otherwise LTspice simply interpolates between the digital output levels at the nearest timesteps caused by other parts of the sim, loosing propagation delays and rise/fall times that lie in between them.

author: Wimberleytech
author_rank: Super Contributor
timestamp: May 01, 2020, 09:45:48 pm
content: Quote from: Ian.M on May 01, 2020, 08:21:03 pmLike this?:XU7 N001 N001 N008 NAND_2 td=100n tripdt=10n

author: Ian.M
author_rank: Super Contributor
timestamp: May 01, 2020, 09:52:15 pm
content: Yes that should work, provided the time between consecutive input transitions is greater thantdas the min. input hold time is also set bytd.N.B you may observe an A type gate working correctly without thetripdtparameter if some other part of the sim forces small enough time steps, either explicitly in the .tran command or by a high enough frequency signal. However that typically results in a very slow sim as unlike per-instancetripdtit cant skip over periods where the gate inputs are steady state.Edit: thanks eblc1388 for pointing out a bad typo - see spelling of 'tripdt' in the quote below!

author: Wimberleytech
author_rank: Super Contributor
timestamp: May 02, 2020, 02:35:59 am
content: Quote from: Ian.M on May 01, 2020, 09:52:15 pmOK, I think I get it. Thanks.In the future, if it is important, I will just build my own logic subcircuits and pay the penalty in time. This was not really important...was just thinking about an easy way to construct a non-overlapping clock generator rather than constructing it with pulse or pwl. Here is the transistor-level version...but it is overkill.* F:\Documents\LTspiceXVII\nonOverlap.ascV1 N001 0 PULSE(0 5 0 .1u .1u 50u 100u 100)M1 N003 N001 N006 N006 CMOSN w=10u l=.5uM2 N003 N002 VDD VDD CMOSP w=20u l=.5uM3 N003 N001 VDD VDD CMOSP w=20u l=.5uM4 N006 N002 0 0 CMOSN w=10u l=.5uV3 VDD 0 5M5 N008 N007 N010 N010 CMOSN w=10u l=.5uM6 N008 N005 VDD VDD CMOSP w=20u l=.5uM7 N008 N007 VDD VDD CMOSP w=20u l=.5uM8 N010 N005 0 0 CMOSN w=10u l=.5uM10 N004 N003 VDD VDD CMOSP w=20u l=.5uM12 N004 N003 0 0 CMOSN w=10u l=.5uM9 N005 N004 VDD VDD CMOSP w=20u l=.5uM11 N005 N004 0 0 CMOSN w=10u l=.5uM13 N009 N008 VDD VDD CMOSP w=20u l=.5uM14 N009 N008 0 0 CMOSN w=10u l=.5uM15 N002 N009 VDD VDD CMOSP w=20u l=.5uM16 N002 N009 0 0 CMOSN w=10u l=.5uM17 N007 N001 VDD VDD CMOSP w=20u l=.5uM18 N007 N001 0 0 CMOSN w=10u l=.5u.model NMOS NMOS.model PMOS PMOS.lib F:\Documents\LTspiceXVII\lib\cmp\standard.mos.tran 0 200u.include model.txt.backanno.endThanks again...

author: SiliconWizard
author_rank: Super Contributor
timestamp: May 03, 2020, 02:40:17 pm
content: Of course, using LTSPice's logic gates will get you much faster simulation times than using hand-crafted, analog versions of them. LTSpice basically does mixed-signal simulation when using its embedded logic gates.The latter approach will give you something more realistic.I suggest building your own library of gates with subcircuits. Once you've done that, you can reuse them just as easily as using the provided logic gates. But yes, simulation times will be much longer.Note that for using custom voltage sources like this, LTSpice allows you to use PWL data from a file instead of typing in the values (which is error prone and very tedious.) You can then generate this file either by hand or automatically from some script with your favorite language. A time saver.