Is there any two-channel or four-channel version of SN74ALVC164245? - Page 1
Forum section: electronics / projects

author: technix
author_rank: Super Contributor
timestamp: October 20, 2018, 08:24:17 pm
content: This is about using 68010 in an otherwise 3.3V LVCMOS board without breaking compatibility with 68HC000. 68010 is a 5V NMOS chip that has LSTTL logic levels, and 68HC000 has 5V CMOS logic levels. Also I want to retain the signal I/O type while level translating from 5V LSTTL to 3.3V LVCMOS - when the CPU tristated the 3.3V dude get tristated for example.SN74ALVC164245 is so far the only logic level shifter that, on the B side, has 5V LSTTL-compatible input logic levels and outputs 5V CMOS levels. (A side is 3.3V LVCMOS.) For most of the outputs (everything that would be tristated on either HOLD or bus yield) and the bidirectional data bus I have implemented the logic level shifting using three SN74ALVC164245. The input signals of the CPU can use 5V CMOS levels so I used a SN74LVC8T245 for that. Now I have four remaining signals: nRESET, nHOLD, nBG and E. nRESET and nHOLD are both open drain signals, while nBG and E are both outputs from the CPU not subjected to bus release control.The original plan was to use TXB0104, two channels for the open drain since that chip is automatic bidirectional, and two channels just to bring out the two outputs. However there is a problem for that: TXB0104 has a 3.5V VIH while 68010 has a VOH capped at 2.4V. I can use 74HCT2G04 in the 5V zone to level shift the two output-only LSTTL signals to 5V CMOS, bring it into the 3.3V zone and invert it back using 74HC00 (two gates, the other gates are used to recreate the tristate control for the level translators) but that is hardly an elegant solution, and it does not handle the logic level problem with the two remaining lines at all.Do you have any suggestions? Is there a two-channel or four-channel version of that LSTTL-compatible CMOS level shifter?

author: spec
author_rank: Frequent Contributor
timestamp: October 20, 2018, 10:30:08 pm
content: +technixThe attached list shows some logic level translators for you to have a look at. The number in brackets indicates the number of channels (x2) = two channels and (x4) = four channels.

author: technix
author_rank: Super Contributor
timestamp: October 21, 2018, 04:41:32 am
content: Quote from: spec on October 20, 2018, 10:30:08 pmNeither would work: the 5V side has a VIH of 3.5V, which won't recognize the 2.4V VOH of 68010 properly.

author: spec
author_rank: Frequent Contributor
timestamp: October 21, 2018, 05:53:02 am
content: Quote from: technix on October 21, 2018, 04:41:32 amJust a thought. If you made the supply voltage of the 68010 side of the translator around 3V, won't that fix the problem?

author: Ian.M
author_rank: Super Contributor
timestamp: October 21, 2018, 07:09:48 am
content: For the bidirectional open drain signals, use a low Vgs threshold N-MOSFET with its gate tied to +3.3V, and a pullup either side of it, as commonly used for level shifting I2C signals.For the output only signals, any 3.3V non-inverting gate or buffer with 5V tolerant inputs would be suitable.

author: technix
author_rank: Super Contributor
timestamp: October 21, 2018, 08:44:39 am
content: Quote from: spec on October 21, 2018, 05:53:02 amI need to support both 68010 and 68HC000, the former has 5V LSTTL levels and the latter uses 5V CMOS levels. If I swapped out the 68010 with 68HC000 the translator would fry.

author: technix
author_rank: Super Contributor
timestamp: October 21, 2018, 08:48:31 am
content: Quote from: Ian.M on October 21, 2018, 07:09:48 amIt is exactly the latter I am struggling. Any ideas?

author: Ian.M
author_rank: Super Contributor
timestamp: October 21, 2018, 09:00:35 am
content: Quote from: Nexperia websitePower it at 3.3V and strap each gate's inputs together so they act as plain buffers. The inputs will be happy with 5V levels and will have TTL-like thresholds (2.0V Vih_min, 0.8V Vil_max)

author: technix
author_rank: Super Contributor
timestamp: October 21, 2018, 09:43:51 am
content: Quote from: Ian.M on October 21, 2018, 09:00:35 amHmm it appeared to me that 74LVC2G17 can do that too. Smaller chip. Although it is a bit difficult to find.As of the I2C level shifter, is there any concrete chips?

author: Ian.M
author_rank: Super Contributor
timestamp: October 21, 2018, 10:07:02 am
content: Yes, the 74LVC family gates typically have 5V tolerant inputs. Its usually only the bidirectional buffers that don't.For the I2C-like level shifting its just two MOSFETs (or one dual one if you can find a suitable one). Seehttps://cdn-shop.adafruit.com/datasheets/an97055.pdf

author: technix
author_rank: Super Contributor
timestamp: October 21, 2018, 11:12:52 am
content: Quote from: Ian.M on October 21, 2018, 10:07:02 amThis solution is cheap though, 74LVC2G17 + 2x 2N7002.I wonder if I can get those to fit in the drawings though as there are close to 30 bus pull-up and pull-down resistor packs. Close to 120 10k resistors total to keep the bus in a known state even in the case that the processor socket is unpopulated and the FPGA is unprogrammed.

author: Ian.M
author_rank: Super Contributor
timestamp: October 21, 2018, 11:31:47 am
content: Although a 2N7002 will probably work, ideally you want a MOSFET with a lower max Vgs threshold voltage, to be certain it can turn hard on when the line is low with only 3.3V - Vol for Vgs. I'd look for ones with a max Vgs threshold under 1.6V. Low gate charge is also advantageous - so don't go for Id_max or Vds_max much higher than you need as that increases the typical gate area.