High Speed USB issues - Page 1
Forum section: electronics / projects

author: mribble
author_rank: Regular Contributor
timestamp: December 08, 2014, 01:05:56 pm
content: This is the second version of my pcb for this project. The first one worked at USB1 (full speed), but wouldn't connect at USB2 speeds. I did a ton of research and redesigned the board in a way that I thought was ideal for USB2. I went to a 4 layer board and isolated the heck of of the USB differential pair. The v2 board comes back and still it only connects at USB 1 speeds. I've never done high speed USB design before so maybe there is something obvious to you experts.Also worth noting is I'm using the ATSAM3x chip. The Arduino Due uses this chip and it supports USB2 high speed. I took a look at it's layout after I was done with my design and while mine is very different I actually think my is better, but clearly it isn't since it works at high speed and my design does not.Schematic just shows how things are connected (remember the obvious stuff has to be right since the design works on USB 1 speeds). The important pins are DHSDP, DHSDM, DFSDM, DFSDP, and the 39 ohm resistors. This is all standard USB design so I'm pretty sure the schematic is correct.PCB1 and PCB2 just show my layout. The usb differential pair is on the front copper layer. Then there is a ground plane on inner2 copper and I isolated the plane under the USB differential pair to remove currents on the ground plane.The only components on the usb differential lines are:1) These resistors (0.5%):http://www.mouser.com/ProductDetail/Susumu/RR0816Q-390-D/?qs=sGAEpiMZZMu61qfTUdNhG%2fDhcyQpRg8MX%2fgzrG1iZcA%3dThese2) These varistors:http://www.mouser.com/ProductDetail/Bourns/CG0603MLA-55ME/?qs=sGAEpiMZZMvxHShE6Whpu%252bS9l6TTnhSSJE8CrQaGb2s%3dIdeas or questions?

author: Wilksey
author_rank: Super Contributor
timestamp: December 08, 2014, 01:39:29 pm
content: Hi,I am not 100% familiar with that chip, but a quick look and a few questions:1. ATMEL suggests you use a 12MHz external clock for USB, do you have this?2. ATMEL suggests you set the USB PLL correctly, has this been done?3. ATMEL DS 43.6 suggests pull up resistors of 1.5k and 15k, have you checked this?4. ATMEL provide a typical connection diagram on page 954, have you checked this?Also, a schematic checklist document is here:http://www.atmel.com/Images/Atmel-42187-ATSAM3X-and-ATSAM3A-Series-Checklist_AP-Note_AT03462.pdf

author: madires
author_rank: Super Contributor
timestamp: December 08, 2014, 01:40:36 pm
content: What impact does the varistor's capacitance of 270 pF have on a 480MHz signal?

author: mribble
author_rank: Regular Contributor
timestamp: December 08, 2014, 02:36:17 pm
content: Wilksey1) Yes2) Yes. I'm using the build in ROM bootloader which does appear to set this. This is also what the Due uses.3) I don't know what you are referring to here. Can you explain this one more?4) Yes. Checked that and other atmel documentation many times to design this optimally.MadiresThat is a good point. Not having worked with high speed before I haven't considered this. I can certainly try removing these (they are just a safety feature) and see if that fixes it. I will try that later today. I did quickly look up captive resistance. Calculated it for 480MHZ/270 pF and got 1.2 ohms. This seems low and like it could be a problem, but I've never had to worry about this sort of thing before so I'm interested what others think and if there is a rule of thumb about what a good target captive resistance is for this sort of application.

author: wraper
author_rank: Unknown
timestamp: December 08, 2014, 02:41:17 pm
content: Quote from: madires on December 08, 2014, 01:40:36 pmThis, ESD protection on USB must be ultra low capacitance, ESD protection ICs for high speed USB usually have around 1pf capacitance. Moreover that groundplane under differential pair which looks like dick will compromise signal integrity even more.

author: mribble
author_rank: Regular Contributor
timestamp: December 08, 2014, 02:55:41 pm
content: Thanks wrapper. That 1 pF suggestion really helps! I will look into this.Could you explain why the "anatomically shaped"ground plane might be an issue? The reason I put that there was to eliminate any ground currents from happening under the usb differential pair, which I read for high speed signals can be a problem. If you could explain what sort of problems it might cause that would be helpful. Would you suggestion be to completely remove the ground plane cutout I did and just have it be a solid plane?

author: tggzzz
author_rank: Super Contributor
timestamp: December 08, 2014, 03:12:01 pm
content: Quote from: mribble on December 08, 2014, 02:55:41 pmA gap in a ground plane won't stop currents; it will make them go elsewhere.A high speed signal crossing a gap in a ground plane is a bad idea since the gap will cause an impedance discontinuty. Such discontinuities cause reflections, therefore pattern-sensitive signal distortions.You need to do everything possible to ensure the signals see the correct constant impedance, which means getting the right trace width, no stubs, no vias, no gaps, no spurious capacitance or inductance, and the correct termination.This can be a complex subject. Search for application notes that include board layouts, or for general high speed pcb layout principles using "signal integrity" as a keyword.

author: mribble
author_rank: Regular Contributor
timestamp: December 08, 2014, 04:15:19 pm
content: Sorry, I meant the gap would redirect currents. The high speed differential pair never crosses a gap in the ground plane. The gap circles the high speed differential pair so I believe it should be good. The traces you see crossing these gaps (green) are on the bottom of the board and are low speed signals.

author: wraper
author_rank: Unknown
timestamp: December 08, 2014, 07:24:23 pm
content: As I understand from the last picture, that reproductive organ split plane is not connected to anything under the IC and is connected only at USB connector side. That makes it freaking bouncing antenna.QuoteYes it does, as all GND pins of ATSAM3x are connected to another part of split ground, that will make current return path to be around in loop everywhere except directly where it actually should. Moreover I see there more than a dozen of another tracks going over split grounds.

author: wraper
author_rank: Unknown
timestamp: December 08, 2014, 07:44:52 pm
content: Counted most (but not all) of the tracks going over split GND planes.

author: marshallh
author_rank: Unknown
timestamp: December 09, 2014, 12:45:48 am
content: Your data lines ar routed correctly. USB2.0 is pretty forgiving.However there is no reason to put the data lines on an island. Just give it a solid ground. Also like hte others mentioned you are creating lots of EMI hazards with the slotting on other signals.It's very unlikely that the ESD protection would affect it at all. This is piddly 480mbps. I've done worse things to 5gbps links.So it would seem it's a configuration problem with the MCU.

author: mribble
author_rank: Regular Contributor
timestamp: December 09, 2014, 12:51:16 am
content: Thanks Marshallh! That is language I can understandI will consider removing that slotting in the next version of the board to reduce emi.I tried removing the varistors. That got the USB2 high speed working. The issue was the high capacitance of those EMI filters. I will switch to some different varistors rated for USB3 (0.5 pF capacitance).http://www.mouser.com/ProductDetail/Bourns/CG0603MLC-05E/?qs=sGAEpiMZZMuQmL5N8IqpXymci2sG3PgGo%2fJNc4rDxtM%3dYou were all very helpful. Thanks for all your help folks!

author: techydude
author_rank: Unknown
timestamp: December 09, 2014, 01:42:35 am
content: others have correctly identified most of your issues, but those varistors will kill it, & sounds like you've just proved it. go for "Transient Voltage Suppressors" (e.g. Transorbs), no more than a handful of pF for USB High Speed. no need to go overboard with USB3 spec'd transient suppressors tho, unless there's no financial penalty in doing so. & get rid of that penis isolated ground section, it's not helping, and could severely dick around with emissions for everything else that's crossing it (pardon pun). just keep the D+ & D- tracks tight together, over the shortest possible path, & as equal length as you can make them. if you want to use length-matching &/or impedance-control features of your CAD, go for it, purely for the learning, but unlikely to be required here over that distance. the aim of the game is to minimise the loop area: of the D+/D- relative to each other, and also compared to the ground return path through the ground plane. I can see why you make the dick, but you've got too much else crossing its path. FTDI datasheets & app-notes have some helpful examples of this overall situation too.