Decoupling caps value - Page 1
Forum section: electronics / projects

author: VEGETA
author_rank: Super Contributor
timestamp: June 01, 2023, 10:30:40 pm
content: Hello,I've been reading about this and watching videos to conclude what is the best answer to which values to use.here are my current findings:Facts:1- decoupling caps most important thing is their location to be very near to IC power pins and short path to ground.2- their value is not so important. 100nF is enough but 1uF is better and won't hurt.3- their physical size is very important... as small as possible is always best. 0402 1uF seems the best choice overall.4- adding parallel caps won't do any enhancements to decoupling, but may help reduce ripple if needed.5- having elec. cap to dampen the rail is always recommended. having a relatively big elec. cap (10~22uF) as a local area storage is good too...won't enhance decoupling much but will help in ripple and stuff like that.what is your take on this? can we consider 0402 1uF X7R 10V to be the best choice overall assuming the price is suitable (which is is)?best regards

author: ataradov
author_rank: Super Contributor
timestamp: June 01, 2023, 10:42:04 pm
content: I'd say all this is fair.The physical size is only important in a sense that bigger capacitors will interfere with close positioning. But if the layout allows to place bigger capacitors, there is no harm in that.At the same time, I would not focus too much on placement near the IC on the same side of the board. Often this interferes with routing and creates a big mess of vias. In that case there is nothing wrong with placing the capacitors on the other side with a via close to the pin. Consider BGA packages, for them this is the only way to do it anyway.

author: VEGETA
author_rank: Super Contributor
timestamp: June 01, 2023, 10:59:32 pm
content: Quote from: ataradov on June 01, 2023, 10:42:04 pmI thought small size such as 0402 is better than 0603 not just because of room but rather package inductance is low. most of the time I have enough space.I am speaking mainly about 2 layer board where component placement is only on top. of course 4 layer board with internal ground and power planes will be much better.what about ceramic dc bias effect in this regard? 100nF in 5v could be mere 10-20nF.

author: ataradov
author_rank: Super Contributor
timestamp: June 01, 2023, 11:12:37 pm
content: Quote from: VEGETA on June 01, 2023, 10:59:32 pmYes, sure, but the difference is minuscule and in many cases theoretical for most cases. Especially if your capacitor is connected to the TQFP package with long leads and then connection goes though the bonding wire to the die. Inductance of that combo will be way greater than the difference due to the capacitor size.Quote from: VEGETA on June 01, 2023, 10:59:32 pmYou can do double sided placement on two layer board too.Quote from: VEGETA on June 01, 2023, 10:59:32 pm100 nF was always "I don't know, lets put something" value anyway. In most cases, it is fine, especially on devices with a lot of VDD pins. If you find out that in some design it is not enough, you can fine tune it.

author: VEGETA
author_rank: Super Contributor
timestamp: June 01, 2023, 11:17:05 pm
content: QuoteI know but my point was that 2 layer top placement is my only choice due to price and so on...etc. but I know 4 layer is best in this regard. the question was about how to do it properly in 2 layer top placement only.Quotemy opinion was that 100nF 0402 or 0603 is the default choice for normal stuff like MCUs and regular other low power chips, assuming power supply is finely designed and doesn't ring or have such problems.However, you mentioned 100nF might not be enough, how can I know or estimate that before doing the board? and if so, isn't it better to just use 220nF-1uF 0402 0603 and never worry?

author: ataradov
author_rank: Super Contributor
timestamp: June 01, 2023, 11:22:35 pm
content: The only way to know for sure is to build a prototype and measure it.Bigger does not mean better. If design has a lot of power pins (like FPGAs and high-performance MCUs often do), with 1 uF per pin and weaker power supply, you may end up with a very slow rise time. And many devices don't like that.But if the design is simple, then sure, just place 1 uF.In most cases the way you know there is a problem is by observing that device does not work as expected. This is where you would do investigation and know what to change.

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 01, 2023, 11:27:34 pm
content: Quote from: ataradov on June 01, 2023, 11:12:37 pmAbsolutely.OTOH, I still see some engineers who put smaller value ceramic caps (like 1nF or even 100pF) in parallel with larger ceramic caps (like 1µF, 10µF) *for decoupling purposes*. In most cases, it doesn't bring anything as ceramic caps in small SMD packages, even at 10µF, have negligible parasitic inductance and very low ESR.We might start discussing the finer details when dealing with high-frequency RF stuff, but for bypassing some logic IC, really?

author: VEGETA
author_rank: Super Contributor
timestamp: June 01, 2023, 11:36:41 pm
content: Quoteafter my latest readings and watching, I got convinced that multiple value parallel ceramics are not really beneficial.the ones who aid this used to claim stuff about different value for different frequencies, and they post that drawing diagram..etc but the others like Eric from Robert Feranic videos says it is all about cap's inductance and placement not its own valve..etc.Quoteso 0402 10uF cap can work as good as 100nF 0402 (nearly) due to the package size. I just wanted to know the go-to value in normal situations.

author: chilternview
author_rank: Frequent Contributor
timestamp: June 02, 2023, 12:07:47 am
content: Quote from: VEGETA on June 01, 2023, 10:30:40 pmNot necessarily true, at 10MHz a 1uF may be good but at 100MHz 100nF may be better. See for example:https://article.murata.com/en-eu/article/impedance-esr-frequency-characteristics-in-capacitorsIf the self resonant frequency is lower than the primary noise frequency you are trying to decouple, a smaller value may be better.

author: Someone
author_rank: Super Contributor
timestamp: June 02, 2023, 02:04:24 am
content: Quote from: chilternview on June 02, 2023, 12:07:47 amYou'll have to pull out exactly where in the article you think it says a smaller value can be better, because I read it as exactly the opposite. That article reinforces the generally true concept that smaller case size is better (assuming nothing else changes).

author: Someone
author_rank: Super Contributor
timestamp: June 02, 2023, 02:12:18 am
content: Quote from: VEGETA on June 01, 2023, 11:36:41 pmThere is no single go-to value, these existing "nice" values never made sense. Two things:what is the (distributed) capacitance actually trying to achieve? for bypass, specify as a target impedance insteadthen find whatever combination of capacitances meets that at the lowest cost, which results in things like this:https://www.eevblog.com/forum/microcontrollers/bypass-caps/msg930381/#msg930381

author: PCB.Wiz
author_rank: Super Contributor
timestamp: June 02, 2023, 03:34:21 am
content: Quote from: Someone on June 02, 2023, 02:04:24 amIt does say thisFigure 7 shows an LW reverse capacitor with a short length l and large width w. From the frequency characteristics shown in Figure 8, you can see that LW reverse capacitors have lower impedance and better characteristics than a conventional capacitor of the same capacity. By using LW reverse capacitors, the same performance can be achieved as that of conventional capacitors with a fewer number of units. The reduction of unit number enables reduced costs and a reduction of mounting space.

author: Someone
author_rank: Super Contributor
timestamp: June 02, 2023, 04:21:36 am
content: Quote from: PCB.Wiz on June 02, 2023, 03:34:21 amWhich is another point further again: "normal" vs wide electrodes and their reduction of the loop area + reduction in ESR (again generally).

author: Siwastaja
author_rank: Super Contributor
timestamp: June 02, 2023, 06:37:33 am
content: Quote from: chilternview on June 02, 2023, 12:07:47 amYou are looking at wrong metric. Physics and your circuit does not understand what SRF is. It only cares about impedance being low. Plot the impedances of 1uF and 100nF caps in the same packageusing the same Y axisand you will immediately understand that 1uF is superior and there is no compromise. Low-frequency impedance is better and high-frequency impedance is roughly the same.Your misconception is very very classic so I don't blame you. But really it's true only whenever larger C also implies larger package and bigger ESL (including placement further away).

author: chilternview
author_rank: Frequent Contributor
timestamp: June 02, 2023, 06:40:52 am
content: Quote from: Someone on June 02, 2023, 02:04:24 amAs per Fig 4 the resonant frequency of the cap, the point at which it changes from being capacitive to inductive, depends on the capacitance (and of course the parasitic inductance). So it's entirely possible that you might have noise at a high frequency that is not efectively decoupled because the capacitance is too large, and the capacitor is operating past its resonant frequency. It's not black and white, the best value depends on the application.This is why people sometimes use both a high capacitance e.g. electrolytic or tantalum and a low capacitance e.g. ceramic in parallel.And as you mention, size matters - the smaller the cap, the less its parasitic inductance.

author: chilternview
author_rank: Frequent Contributor
timestamp: June 02, 2023, 06:45:36 am
content: Quote from: Siwastaja on June 02, 2023, 06:37:33 amYou missed the words 'may be better'. Of course if the package (and hence the parasitic inductance) is the same, then a larger capacitance will have a lower impedance. But if it's just using a bigger capacitor both physically and in terms of value, it may not.I'm just poitning out that the OP's statement that bigger is *always* better is not true.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 02, 2023, 06:46:26 am
content: No, the OP was crystal clear constraining the package size to be the same in this comparison, the whole point was that package size thus ESL defines high-frequency impedance, not having smaller capacitance value. Always look at the context, removing sentences from the context is dangerously misleading.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 02, 2023, 06:53:55 am
content: Quote from: VEGETA on June 01, 2023, 11:36:41 pmYes, but note that in $current_year, 0402 10uF is not realistic; if some manufacturer sells such a thing you should expect a significant drop in capacitance (maybe even -90% down to 1uF) under any DC bias, even at just 3.3V. If your task is to filter at 3.3V, then excess capacitance at 0V does nothing useful but increase the initial inrush energy or make hotplug ringing transients more difficult to deal with. So don't go overboard. 1µF in 0402 is a good go-to MLCC instead of the classic 100nF. If you don't work in a field where certification ofeverycomponent is required, like most of us don't, being able to substitute different values helps tremendously given the dire situation with availability. Maybe 0.56uF is suddenly available for cheaper? Good for you!

author: Siwastaja
author_rank: Super Contributor
timestamp: June 02, 2023, 07:17:31 am
content: Regarding 100nF, it's really the "bare minimum" value. Given DC bias, temperature, tolerance and aging, let's say it goes down to 50nF. Then, at 10MHz, which is a relevant figure because it's tested for EMC and it's well within the edge rate capability of microcontroller / logic IC IO, impedance is1/(2*pi*10e6*50e-9) = 0.32 ohms,which means a switching current peak of 1A would cause 0.3V voltage drop due to used charge from that capacitor, which then the upstream power trace would then try to supply, limited by its inductance, causing a dip in the supply voltage and then opposite overvoltage peak (ringing). Now this doesn't seem too bad but redo the calculation with 10nF and you start seeing why I suggest the classic 100nF is the "bare minimum" which works in most cases fine but does not have much margin. Therefore, I second the recommendation you often hear from EMC experts, use 1uF as your default bypass cap if you can get it in the same package size you would use with 100nF.

author: AndyC_772
author_rank: Super Contributor
timestamp: June 02, 2023, 07:36:12 am
content: https://www.cawteengineering.com/design-focus-parasitic-inductance/

author: Someone
author_rank: Super Contributor
timestamp: June 02, 2023, 08:18:03 am
content: Quote from: chilternview on June 02, 2023, 06:40:52 amYour reasoning is completely faulty, and misses what that article says. Fig 4 does not show any comparison between different capacitors, only a single representative impedance plot.... which you are asking us to imagine could look different for different values, without any examples or data to back that up (trivial to pull from the manufacturers public databases).Further, Fig 5 says the exact opposite of what you are asking us to imagine. Siwastaja is on the money here, it would be extremely unusual for a 1uF cap in the same package as a 100nF cap to be "worse".

author: Avelino Sampaio
author_rank: Frequent Contributor
timestamp: June 02, 2023, 08:50:47 am
content: W2aewvideo lesson is very enlightening.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 02, 2023, 09:15:09 am
content: Also the idea that capacitor stops being a capacitor and changes into inductor at SRF is totally wrong. It's only after this point the impedancestarts to risebecause of inductance, so inductance isstartingto "win" over the capacitance. All that matters is the value of impedance (absolute; not relative to something else), so filtering properties are still acceptable quite far ahead from SRF; quite logically, since the impedance was higher before the SRF, too.It's the sweet spot fallacy. One could say a capacitor is at its best at SRF, but the real question is how wide is the range it isgood enoughat? And that is the area below some "required maximum Z" curve. By choosing smaller C value in the same package, the range on the left side (low frequencies) shrinks, but does not (significantly) widen at right (high frequencies), even if SRF shifts to right, because SRF was wellinsidethe range to begin with, not at the edge of the range as some mistakenly think.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 02, 2023, 09:33:20 am
content: Random image from Google image search:https://www.doeeet.com/content/wp-content/uploads/2019/10/Impedance-of-usual-MLCCs-16V-rated-vs-DC-voltage-bias.pngChoose some Z value you deem sufficient, let's say 1E-1 ohms and say do you see any advantage in using the smaller capacitance part?Another:https://res.utmel.com/Images/UEditor/c8cd4daa-b2ee-42e6-80ba-59384db825b8.png

author: iMo
author_rank: Super Contributor
timestamp: June 02, 2023, 10:04:25 am
content: FYIhttps://ksim3.kemet.com/capacitor-simulation

author: VEGETA
author_rank: Super Contributor
timestamp: June 02, 2023, 11:14:23 am
content: Quote from: Siwastaja on June 02, 2023, 06:53:55 amsorry for my mistake but i meant 1uF 0402 not 10uF.thus we can safely say that anything between 100nF to 1uF 0402 X7R is a good value and case size to pick in general. Plus adding some bigger elec. cap to filter ripple and dampen the rail.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 02, 2023, 02:12:15 pm
content: Yes, I can totally agree with your conclusion and this is what I do.Also remember that while the tabulated package inductance difference is small between 0402 and 0603, 0402 allows you to do much better layout when you have a package with 0.5mm pitch so that you need to place dozens of parts (power bypass caps, ADC RC input filter caps, output pin series termination resistors) around it. 0201 would be optimal but is a tad difficult to work in manual prototyping and some not-up-to-date fabs might have problems with it. But 0402 works with manageable amount of breaking-out in layout while 0603 requires spanning the parts significantly further away.

author: MisterHeadache
author_rank: Regular Contributor
timestamp: June 02, 2023, 02:38:21 pm
content: Wes Hayward provides an explanation of the interactions between multiple filter cap values on his web site. Scroll down about half-way where he shows how the self-resonances of multiple caps can interact and create essentially nulls in the filtering frequency response.http://w7zoi.net/bypass/decouple.html

author: Siwastaja
author_rank: Super Contributor
timestamp: June 02, 2023, 02:47:57 pm
content: Quote from: MisterHeadache on June 02, 2023, 02:38:21 pmGreat resource, one point I want to bring out to add to my earlier posts, this guy says it better:Quote(emphasis mine)

author: David Hess
author_rank: Super Contributor
timestamp: June 02, 2023, 05:07:41 pm
content: Quote from: VEGETA on June 01, 2023, 10:30:40 pmThe electrolytic bulk decoupling capacitor is often located at the power input and perhaps at the end of the distribution network on the board. The best model I have found for it is that its ESR terminates the impedance of the power distribution network absorbing any reflections, which agrees closely with the rule of thumb of 50 microfarads per amp. Another way to think of it is that the bulk decoupling capacitor quashes the Q of the transmission line forming the power distribution network.Quote from: ataradov on June 01, 2023, 11:12:37 pmIgnoring EMC, see below, one way to calculate the minimum decoupling value is by how much charge the IC is switching. The ratio of charge stored in the coupling capacitor and the load determines how much voltage ripple will be produced. I found that this gives very accurate agreement with measurements.Quote from: Siwastaja on June 02, 2023, 07:17:31 amI remember one design where decreasing the decoupling values reduced EMC because the series inductance combined with the lower capacitance produced a null at the frequency of operation.

author: Siwastaja
author_rank: Super Contributor
timestamp: June 02, 2023, 05:54:15 pm
content: Quote from: David Hess on June 02, 2023, 05:07:41 pmThe fact people sometimes see mild successes by decreasing C also keeps feeding the myth of smaller C having any advantage. You can see this in my above post where I posted two links; both show a very narrow region right at SRF where the impedance is lower than that of the largest capacitor. So yes, the smaller cap gives better HF performance but only at that very narrow frequency band.The problem is the narrowness of this dip, and it being dependent on unit-to-unit variation, DC bias, temperature and ageing of the capacitor. Therefore, if such change to smaller capacitance value makes the EMC pass, the result is not valid as it depends on that exact part found at the lab. Lab of course writes the report for you, and for self-certified stuff, if you don't understand what happened, then no one cares even if your product is in reality non-compliant, until someone does independent testing.If you look my second link, you can kinda see that if you wanted a modest say 3-5dB improvement over wide band, you would need to parallel not 3 but 10-15. maybe 20 different capacitor values! This is obviously impossible because you could not physically fit them close enough. So aiming for SRF dip is not going to make it; instead the correct way for the improved high-frequency attenuation is lower the ESL i.e., use a smaller part and/or better layout, or paralleling multiple caps (the same part number!) if layout enables this.Quote from: David Hess on June 02, 2023, 05:07:41 pmExcellent and simple way of thinking, I like it. I regularly use this approach when choosing power bypass cap or bootstrap cap for gate driver ICs, knowing the Qg_tot of the MOSFET. Make the capacitor 100x or so. Same thing when using simple RC filter to provide low impedance for SAR ADCs for those slowly moving inputs you won't want to spend an opamp for; use 1000x the internal sample&hold capacitor (again a simple datasheet value) for roughly 10-bit performance.

author: David Hess
author_rank: Super Contributor
timestamp: June 03, 2023, 01:14:40 am
content: Quote from: Siwastaja on June 02, 2023, 05:54:15 pmIt was a while ago so the design was through hole and they were using stacked metal film capacitors with 5% tolerance and no adverse characteristics. For a while back then stacked metal film capacitors were as inexpensive as ceramic capacitors. I recognized them because I was also using them for decoupling applications. They had a specific EMC problem and changing the capacitors values fixed it without a redesign.

author: The Electrician
author_rank: Frequent Contributor
timestamp: June 03, 2023, 01:43:51 am
content: Quote from: Siwastaja on June 02, 2023, 09:33:20 amThis would be worth reading:https://web.archive.org/web/20200518044500/https://www.ultracad.com/mentor/esr%20and%20bypass%20caps.pdf

author: Smokey
author_rank: Super Contributor
timestamp: December 03, 2023, 05:24:53 am
content: I thought this was interesting. At least from a historical perspective of how we got the 0.1uF, 1uF, 10uF set.https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values