Excessive IO ripple on microcontroller output pins - Page 1
Forum section: electronics / projects

author: Sac
author_rank: Contributor
timestamp: July 20, 2025, 09:31:18 am
content: HiI am currently testing a new designed PCB running a ATMega234pb. I have found that multiple IO pins seem to have a high ripple voltage when switched on and even when switched off.When pin are high the ripple is 70mv and low 20mv. Has a frequency of around 4mhz.Design notes are as follows1. 5v Rail plane 8mv pk-pk2. Has 100n and 2.2uf caps on Vcc for decoupling3. Micro running a external 8mhz crystal4. Pin currently testing PB.4 , PA.3 PD.4, PD.5QueriesThese pins are part on the Peripheral Touch Controller (PTC), but I'm just using them as a enable pin for a Op-amp and switch a transistor for an LCD backlight.I don't have any success with setting the PTC off with PRR2.3 = 1 to stop the ripple.The only way to stop the ripple is to put the micro into power save mode ( CONFIG POWERMODE = ADCNOISE) or by adding a 100nf cap to that io lineAttached are the scope readingsSDS001 = Pin HighSDS002=Pin LowI would have thought the ripple would have been say 8-15mvPk-Pk???Whats people thoughts??I'm using Bascom as my compiler

author: bson
author_rank: Unknown
timestamp: July 20, 2025, 07:48:54 pm
content: What's the bandwidth of the scope? Looks like pulses low-passed to 50MHz (10ns per div).This looks neither capacitive or inductive. I would strongly suspect it's a scope or probe artifact, and what you're looking at is a very brief capacitive spike that can probably be knocked out with a small series resistor, maybe 100 ohm.

author: neillnz
author_rank: Contributor
timestamp: July 21, 2025, 08:36:55 am
content: I wonder about the test setup, in particular the placement of the probe ground lead.When measuring the ripple on the port pins is the probe ground lead in the same place as when you observed 8 mv pk-pk on the +5 V rail?Are you able to upload images of your PCB layers?Also, go the BASCOM, it's rather awesome.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 21, 2025, 08:46:25 am
content: Quote from: neillnz on July 21, 2025, 08:36:55 amOr even the use of a ground lead, as opposed to a very short wire from the nearest ground on the PCB to the ring of the probe.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: July 21, 2025, 09:41:02 am
content: Assuming that both the GND connection of the uC board (Do you have a proper GND plane?) and the probing (where is your scope probe connected) are OK, an uC output is just a switch, either to GND, or to the uC supply voltage. So if you see ripple on an output pin, that same ripple is very likely to be on the power supply pin as well.Also, any output current to an output pin is coming from the uC's Vcc rails, and also going though the bondwires which have a bit of resistance. So if one output pin is switching a "heavy" load such as a LED, then all the other output pins are likely to some voltage ripple in the same rithm as the switching of the LED.

author: Sac
author_rank: Contributor
timestamp: July 21, 2025, 10:03:02 am
content: Hi Team,Thanks again for the input so far.Just to clarify — I’m using the grounding spring on the probe tip and referencing the same ground point when measuring both the Vcc ripple and the IO pin ripple. They're physically close, more by luck than design.PCB Stackup:L1: Signal + GND pourL2: Full ground planeL3: 5 V power planeL4: Signal + GND pourThere are no fast-switching signals on the board — just the 8 MHz external crystal.Would you consider 70 mV peak-to-peak ripple excessive? My scope samples at 1 GHz, so there could be more happening that I'm not seeing.Today I removed the external 8 MHz crystal and switched over to the internal oscillator — unfortunately, no change.I first noticed the issue after enabling an op-amp, which drives a 12-bit ADC. The ADC readings showed ringing, which led me to start probing and eventually discover the ripple on the port pins.I'm using Bascom, and pretty happy with it — cut my teeth on C64 BASIC and 6502 assembly back in the day.That said, I’m not entirely confident the port is fully configured. It’s declared as an output, but I’m unsure if the Peripheral Touch Controller (PTC) might still be active and unintentionally clocking the pins.PTC Control:According to the datasheet:Page 39, Section 10.1.3Page 62, Section 12.11.5Both mention PRR2 bit 3 (PTC disable). I’ve tried clearing this bit (PRR2.3 = 0), but I’m not sure how to verify whether the PTC module is actually disabled.I would’ve expected the IO pin ripple to closely match or slightly exceed the Vcc ripple — which is only around 8 mV peak-to-peak. I’ve got 100 nF + 2.2 µF decoupling caps on the AVcc pin. Adding a 100 nF cap directly to the affected IO pin brings the ripple down to 20–30 mV, but that’s not really a recommended fix from what I’ve read.Any tips or insights would be much appreciated.Cheers,Snow

author: Siwastaja
author_rank: Super Contributor
timestamp: July 21, 2025, 05:54:37 pm
content: Quote from: ScroatyBallSac on July 21, 2025, 10:03:02 amThis expectation is incorrect. Your Vcc pin is bypassed by the closeby capacitor, whereas the IO pins are powered by the internal copy of the Vcc - and it will share paths with current-consuming, switching parts of the circuit, and on the other hand, bypassed by the capacitance of the non-switching CMOS structures.Without having deep knowledge in chip design and knowing the exact layout of the chip, it is impossible to say if this amount of ripple is normal. Datasheets never specify such parameter (digital output ripple voltage) at all; there is guaranteed minimum output "high" and maximum output "low" voltage and your ripple is clearly within these limits with great margin.Maybe AVR is just that way. We all know it isn't an excellent design in this regard; for example its ADC is known to have quite a lot of noise from the digital domain to the point they suggest powering down the CPU during conversion.Adding external RC filters to the pins would be a simple solution.

author: thm_w
author_rank: Super Contributor
timestamp: July 21, 2025, 09:32:59 pm
content: If this is happening every clock edge, then that adds up, since its 8MHz clock. Its ~60ns spacing between the peaks. Not sure where you are getting 4MHz from.You can try measuring the clock with one channel and this ripple with another and see that they are in sync or not.Is there only 2.2uF on the entire 5V rail? That doesn't seem like much, also 8mV on 5V seems a little high unless its got a decent load. Try adding some more bulk capacitance to the 5V rail if all you have is 2uF.Post some photos of the layout and schematic.

author: neillnz
author_rank: Contributor
timestamp: July 21, 2025, 10:54:36 pm
content: May not be the issue but note that to disable the PTC the data sheets says you need to set the PRPTC bit, not clear it:Bit 3 – PRPTC: Power Reduction PTCWriting a logic one to this bit shuts down the PTC module. When the PTC is enabled, operation willcontinue like before the shutdown.Rather than trying to directly access that bit from BASCOM, write to the entire register like this: PRR2 = PRR2 and &h08

author: PCB.Wiz
author_rank: Super Contributor
timestamp: July 22, 2025, 02:42:35 am
content: Quote from: ScroatyBallSac on July 20, 2025, 09:31:18 amAny noise like this is a result of parasitic inductances and current spikes,The GND plot reports 16MHz so is giving one spike per 8Mhz edge, and is not hugely different from your VCC measurement, so it is pretty much as expected.The VCC plot reports 4.73kHz but also say 10ns so not sure what to make of that?MCU Vcc/Pin=high noise is commonly rather worse than GND noise, as the internal paths and metal is less allocated to Vcc than ground.Pullups are not as strong, meaning more crosstalk.Pins further from VCC pin can be expected to be worse than pins nearer.You have about 3x worse, that maybe normal, perhaps check how it varies with pin placement?

author: Psi
author_rank: Super Contributor
timestamp: July 22, 2025, 03:14:48 am
content: Assuming this is not just a probing issue.I've seen voltage spikes on MCU pins caused by someone (me haha) accidently putting the capacitor on the wrong side of the inductor for the LC filter on AVCC. (power rail for adc/analog side)eg. You're supposed to have a cap from AVCC to GND and an inductor from AVCC to VCC but I had the inductor in series with AVCC and then a cap to gnd after that. It makes a nice little voltage boost circuit any time you draw pulses of current through AVCC.Since some of the GPIO is powered by AVCC any current you draw on those outputs goes through AVCC, so 30mA PWM into leds etc..

author: Doctorandus_P
author_rank: Super Contributor
timestamp: July 22, 2025, 03:04:14 pm
content: A pulse every 60ns. That's at 16MHz, so twice your clock frequency (I.e. every flank). Maybe your decoupling capacitors are missing, defective, loose connection, too long wires.How many decoupling capacitors do you have and what is their location?Do you see any difference if you replace them, or add more decoupling capacitors close to the IC?

author: MariuszD
author_rank: Regular Contributor
timestamp: July 22, 2025, 04:33:57 pm
content: Use the probe with the spring to make the GND connection as short as possible.You wrote that you have decoupling capacitors, but are they close to the integrated circuit? Decoupling capacitors should be as close as possible to the IC. Ground circuit on PCB should be wide ground plane. That's all you can do to minimize the inductance of the power supply circuit. Inside the integrated circuit, there are wires that have inductance whose effect cannot be avoided. One can only choose an IC with a greater number of GND and VCC pins, which are connected in parallel, thereby reducing inductance.Read about ground bounce:https://resources.altium.com/p/ground-bounce-reduction-techniques-minimize-signal-integrity-issueshttps://www.protoexpress.com/blog/how-to-reduce-ground-bounce-pcba/https://www.edn.com/how-to-estimate-ground-bounce-in-a-connector-rule-of-thumb-8/

author: thm_w
author_rank: Super Contributor
timestamp: July 22, 2025, 10:39:14 pm
content: They already said they are using spring probe:https://www.eevblog.com/forum/projects/excessive-io-ripple-on-microcontroller-output-pins/msg5985127/#msg5985127

author: Sac
author_rank: Contributor
timestamp: July 23, 2025, 08:35:29 am
content: Hi Team, thanks for your feedback!Probing the IO pin and the clock signal was a great suggestion — turns out they're definitely coupled. I've attached the scope results showing the behavior. Just a heads-up: check the mV scale between the two traces — it’s a bit misleading at first glance.I tried fiddling with register 63 as [@neillnz] suggested — turning it on and off via different methods — but either it made no difference to the output or the code wouldn't compile. I reckon the register isn't actually updating. I’ll ask on the Bascom forum about this one and see what they say.For now, I’ve gone with a hardware fix: added a 100 nF cap on the IO pin that drives the op-amp’s enable line, and an RC filter (10 kΩ / 200 nF) on the op-amp output to smooth things out before hitting the ADC. With a bit of tweaking, I’m now getting pretty decent data from the ADC chipset.Cheers Snow

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: July 25, 2025, 03:18:05 pm
content: Quote from: Sac on July 23, 2025, 08:35:29 amYou should ideally add some series R, maybe 100-1K to avoid a current spike when switching