Multi-tap delay line impedance - Page 1
Forum section: electronics / beginners

author: hermitengineer
author_rank: Regular Contributor
timestamp: November 02, 2020, 07:37:28 pm
content: When designing a multi-tap LC delay line, is there a recommendation on impedance? The input would be a clock signal operating at about 1.76MHz, and each output will have delay times in nanoseconds. Is there a frequency vs impedance recommendation? Or would it have more to do with the input device?

author: hermitengineer
author_rank: Regular Contributor
timestamp: November 05, 2020, 07:47:29 am
content: After some reading and experimentation, I've realized that the impedance will be for a matched load and not for a half-wave reflection (the wavelength is way too long for a half-wave). This means that the input impedance matches the load impedance. So if it's too low, the first inverter will just curl up and die. So I think I'll use a 1K impedance instead. This has the benefit of simplifying time delay calculations since inductance in uH will match capacitance in pF for each node.Now to test if this actually works.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 05, 2020, 09:40:52 am
content: Hm, why LC over other methods? A CCS + C works very nicely at these frequencies. Maybe it has too much adjustable range? But if you're doing like, single digit nanoseconds, that's not at all reliable with the 74LS shown. Are those gates just an example then, or..?As for DL impedance, you want something comparable to or greater than the driver impedance, depending on exactly what signal level and step response you need. Higher is fine, and saves some supply consumption (not that that's significant given the 74LS already?), but cannot be too high or else the C will be too small. Beware also stray C between taps -- you can't buy pure inductances.For 74LS, the terminator should probably be a divider biased near GND. This keeps the output stage evenly loaded, and balances the wave around the input threshold.Tim

author: hermitengineer
author_rank: Regular Contributor
timestamp: November 05, 2020, 06:10:30 pm
content: The intent is to replace an EP82xx-series active delay line.https://www.datasheets360.com/pdf/298123435008976227This one was a one-off with varying delays between taps. So I'm attempting to re-engineer the original. The pinout of the EP82xx is compatible with the 74LS14, and in appearance, they took a standard LS14, attached the delay line components, and potted it over.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 05, 2020, 08:37:45 pm
content: Eww, time delay logic!Yeah, lowpass chain, or preferably all-pass with coupled inductors (CT inductors with k ~ 0.4, depending on passband shape), but I guess you don't need much bandwidth in this particular instance so that will be fine. An end or double terminated network is needed, as you'd get indeterminate levels from a source-terminated network.For a cutoff of Fo = 1 / (2 pi sqrt(L C)) and impedance Zo = sqrt(L/C), the elements are L and C per stage, but don't forget the extra L/2 or C/2 at each end. (A "stage" is actually better seen as the midpoint between rungs -- a constant-LC ladder like this, is composed of L/2, C, L/2 stages. Or C/2, L, C/2. Either way, they add up in the middle, so you only need halves at the ends.) Which in this case, you'll want an L at the source end, since the source impedance would otherwise dominate over the C. Terminator end can be either. I suppose you should also account for the capacitance and loss of the gate inputs, maybe just trim the C's and terminator to clean up the step response, then assume that the pin equivalent load is the amount trimmed by. Loading will be heavier than if the gate were CMOS, and also worse at higher impedances, so you won't be able to go too high.Also, they show a terminator to ground, but I wouldn't be surprised if that's an equivalent circuit; a biased divider still seems likely. The bandwidth looks to be pretty poor (notice the test frequency versus delay) so it's probably not using tapped coils, and I guess you're working with one of the shorter delays to get 1.76MHz through it so that will be fine.Tim

author: hermitengineer
author_rank: Regular Contributor
timestamp: November 06, 2020, 08:13:54 am
content: By "biased divider", do you mean using a parallel resistance that matches the transmission line Z, but connects one to VCC and the other to GND, biasing it to VCC/2? In other words, if you want 1K impedance, use a VCC->2K->last node->2K->GND circuit?Also, I've seen delays calculated as SQRT(lc), but then I've also seen them as 2piSQRT(lc). The second equation agrees with frequency calculation, but in the experimental circuit I made with all delays the same (don't have enough inductors yet to experiment with different delays), the calculation better matched T(seconds)=SQRT(lc) for each node.I also didn't have a lot of capacitors to try yet, so just used 560pF for the entire chain (though 5pF seemed to work better for the very first one, signal-wise). Each inductor was 4.7uH and the terminator was 100-ohm. Each inner node measured around 55ns, which seems to be close to the SQRT(lc) calculation as mentioned. And I guess if I had some 280pF caps for the ends, then all delays would be equal? It's a bit non-intuitive, because that would mean that each inner node is calculated as half the previous capacitor in parallel with half the following one. And apparently the capacitors on each end are used as their full values. Weird.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 06, 2020, 10:04:09 am
content: Yes, but the midpoint will be closer to GND because TTL's I/O levels are off-center. Like, back in the day, you'd often see 390+150R dividers in resistor packs -- for terminating ribbon cable driven by TTL. (Ribbon cable having Zo ~ 100 ohms, when every other wire is grounded.) For example, a vintage hard drive interface (ST506) used this for its control signals; the interface supports up to two drives, with the control signals chained between them and the final drive having the terminator inserted in a socket.Yeah, sqrt(LC) is effectively the time constant; whether that's exactly the delay in an ideal ladder of this type, I'd have to do some math. If nothing else, it's proportional to it.You do have 280pF caps, just wire two 560s in series.Tim

author: hermitengineer
author_rank: Regular Contributor
timestamp: November 07, 2020, 01:59:20 am
content: Quote from: T3sl4co1l on November 06, 2020, 10:04:09 amYou're right.