FPGA to switch output ports - Page 1
Forum section: electronics / general

author: stan001
author_rank: Contributor
timestamp: January 03, 2021, 01:50:24 pm
content: I'm a complete noob in FPGA, did a lot of readings recently and was wondering if this is possible for a FPGA, to use as a wire selector for different protocol on a fix 4 pins output port on RJ45 pins.The output have 4 pins each x 8 = 32 pins on the 4x2 RJ45 connectors.What I wanted to achieve is based on the ADDR1-4 pins from the MCU, it will connect the A1-4 or B1-4 ( up to 8 output ) to different protocol like I2C1, IC2C, SPI or UART ..Is this something possible to be done using a FPGA ??Output ports, 4x2 RJ45 :-[url=https://www.rj45-modularjack.com/sale-11206289-rjsne-5381-08-stacked-rj45-4x2-port-ethernet-shield-right-angle-lpje108xagnl.html]https://www.rj45-modularjack.com/sale-11206289-rjsne-5381-08-stacked-rj45-4x2-port-ethernet-shield-right-angle-lpje108xagnl.html4 of the 8 pins are used as data pins, the balance 4 pins are used as power pins.

author: rstofer
author_rank: Super Contributor
timestamp: January 03, 2021, 09:11:55 pm
content: Sure, it seems simple enough but it's not clear to me which direction the device is controlling. I guess the question is: Who is the master and who is the slave?Have you considered a need for control signals on the A1..4 ports? Data Available, Transaction Complete, that kind of thing. Are these ports used for different protocols simultaneously?A sort of Truth Table describing what the Addr1..4 signals are supposed to do would help. Remember, I2C, in particular, is a master/slave arrangement that allows for multiple masters. If something comes in on I2C how is the address field and R/W' signal going to be handled.I think it's going to be messy because you don't have control signals. Maybe there is some room in the Addr1..4 signals to select between data from/to the port and control to/from the port.Electrically, this is no big deal but you need to spend a lot more time detailing what you expect to happen.

author: rstofer
author_rank: Super Contributor
timestamp: January 03, 2021, 09:21:59 pm
content: If you want to forward a protocol, say I2C to the A1..A4 port (using just two pins) and decode the I2C somewhere else then this project got a whole lot easier. In fact, it is just some glorified multiplexor. It doesn't need to understand any of the protocols, just switch some connections around.

author: asmi
author_rank: Super Contributor
timestamp: January 03, 2021, 10:39:22 pm
content: Why use FPGA in the first place? There are plenty of analog switch ICs which will do what you want.

author: NorthGuy
author_rank: Super Contributor
timestamp: January 03, 2021, 10:48:30 pm
content: UART no problem.SPI is fine, except if the output is on the master side there will be some delays through FPGA which will limit slave transmission speed somehow.I2C, you can re-transmit, but you cannot connect. This is because I2C devices have open drain outputs pulled up by a common resistor.Of course, you don't need FPGA to mux the lines. You can use an analog mux, such as CD4053B, to mux just about anything.

author: stan001
author_rank: Contributor
timestamp: January 04, 2021, 03:41:43 am
content: Quote from: NorthGuy on January 03, 2021, 10:48:30 pmThanks for pointing out that the I2C with a common pull-up resistors cannot go thought the FPGA ...

author: stan001
author_rank: Contributor
timestamp: January 04, 2021, 03:43:35 am
content: Quote from: asmi on January 03, 2021, 10:39:22 pmYes, initially I wanted to do auto-detect of comms protocol, but for a first FPGA project, it is too complicated for me... hahaI will look into analog switch IC for this too, thanks

author: NiHaoMike
author_rank: Super Contributor
timestamp: January 04, 2021, 04:25:14 am
content: Quote from: stan001 on January 04, 2021, 03:41:43 amActually, they can, but you have to implement a state machine so it would be able to switch the direction of the forwarding as needed. It's surprisingly complex to get it right.Apart from the suggestion of using an analog switch, some microcontrollers (most notably some newer PICs and the Cypress PSOC) have very flexible pin muxing built in. A few PICs even have some programmable logic blocks, basically the start of the convergence of FPGA and microcontroller. I predict that we'll eventually see the line between high end microcontrollers and low end FPGAs blur as multiple devices that combine a few microcontroller cores with a little programmable logic become common on the market.

author: NorthGuy
author_rank: Super Contributor
timestamp: January 04, 2021, 03:29:25 pm
content: Quote from: NiHaoMike on January 04, 2021, 04:25:14 amThe situation where both sides pull low cannot be modelled with directional forwarding. For example, master pulls SCL low - you see this and pull the slave's SCL low. Slave decides to stretch the clock and pulls SCL low too. But you don't see this because slave's SCL is already low. Thus you cannot pass this to the master's side. When master releases the SCL, it will see its SCL go up.

author: BrianHG
author_rank: Super Contributor
timestamp: January 04, 2021, 03:33:58 pm
content: A few dual 4x analog mux/switch like 74HC4052 or 8x1 74HC4051 would be my pick.Yes I have done this before in FPGA, however, the FPGA was also the master I2C/MSOI and it knew when to switch the direction of the I2C data line when I2C was in use.

author: Foxxz
author_rank: Regular Contributor
timestamp: January 04, 2021, 07:57:30 pm
content: Today on Foxxz's "how to solve a problem badly"...Could you do something like this to deal with I2C without much logic in the way of the FPGA? Assign the pins to be pullups or just use a pullup on the lines?

author: FenTiger
author_rank: Regular Contributor
timestamp: January 04, 2021, 08:01:07 pm
content: Use tristate IOs. Tie the data pin low and drive the tristate enable.

author: NiHaoMike
author_rank: Super Contributor
timestamp: January 05, 2021, 01:22:20 pm
content: Quote from: NorthGuy on January 04, 2021, 03:29:25 pmThere are ASICs doing just that, I forgot exactly how they dealt with that problem.Probably easier to just implement a master I2C controller in the FPGA and control that over SPI.