ethrent connection to hp 1670e logic analyzer - Page 1
Forum section: electronics / testgear

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 02, 2019, 09:54:30 pm
content: I want to load an inverse assembler on my hp 1670e. Don't currently have a GPIB connection. Also, I don't have an external floppy for my laptop. That leaves the Ethernet connection.I'm on windowss 10. Googling has been unhelpful. I don't even know where to start! I have the analyzer, my pc, and an ethernet cable.I figure I need to open a tc/ip connection of some sort.Help!!!

author: cruff
author_rank: Regular Contributor
timestamp: March 02, 2019, 10:10:09 pm
content: Possibly acquire an Ethernet to GPIB or USB to GPIB adapter?

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 02, 2019, 10:19:26 pm
content: I have a UGSimple gpib to USB. Turns out it doesn't support file transfers. I did order a USB floppy drive, but for the moment, I want to attempt Ethernet. Won't have the drive 'till Monday.

author: TK
author_rank: Super Contributor
timestamp: March 02, 2019, 10:24:16 pm
content: You can setup TCP/IP address on the analyzer and use FTP to transfer the files to the analyzer hard disk.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 02, 2019, 10:42:34 pm
content: I'm clueless on network stuff. I'll google what you just suggested, but any help is appreciated. I've found googling anything network related is the road to being overwhelmed if you don't know exactly what to ask.I'm currently trying to set up X window, but maybe that's a bad way?

author: TK
author_rank: Super Contributor
timestamp: March 02, 2019, 11:07:08 pm
content: If you can setup a network with only the logic analyzer and your laptop or PC is better. You will need an Ethernet Hub and 2 Ethernet cables.I like to set 128.0.0.1 as my PC / laptop IP V4 address on the ethernet port, mask 255.255.0.0You can set the logic analyzer IP address to 128.0.0.2, same mask 255.255.0.0Then you can ping from the PC/laptop to test if the logic analyzer responds: ping 128.0.0.2If ping works, then you can proceed to ftp files to 128.0.0.2Here are the instructions:https://www.keysight.com/main/editorial.jspx?cc=US&lc=eng&ckey=1687067&nid=-11143.0.00&id=1687067

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 02, 2019, 11:21:46 pm
content: can this not be done without the hub? I.E., direct connection from analyzer to pc?I don't have a hub (unless an old wireless router can act as one)

author: TK
author_rank: Super Contributor
timestamp: March 02, 2019, 11:34:15 pm
content: You can do it without a HUB, but you need a cross-over ethernet cable. Or you can use an old wireless router with ethernet ports and use 2 standard ethernet cables. You can just assign static IP addresses on the logic analyzer and PC/laptop or let the router assign dynamic addresses in the 128.0.x.x range with 255.255.0.0 netmask.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 03, 2019, 01:04:37 am
content: OK, makes sense.I have a usb floppy drive coming, and some disks. I think I'm gonna try that route first, since digging out the old router I THINK I have could take longer.What format is the analyzers drivedrive? I know its an MS-DOS compatible format from other threads on this forum. Do I format for NTFS? Is it as simple as just putting the compiled inverse assembler file on the disk, and loading it in the analyzer?

author: DaJMasta
author_rank: Super Contributor
timestamp: March 03, 2019, 01:12:12 am
content: MSDOS is FAT, and generally not FAT32. NTFS is a couple of filesystems too newI don't know the format myself, but I would start with regular FAT (FAT16) and give it a try first.

author: gslick
author_rank: Frequent Contributor
timestamp: March 03, 2019, 02:27:23 am
content: It should be trivial to connect the 1670E analyzer to your network. How is your PC connected to the net? I assume it is connected to a broadband router of some sort. Are all of the LAN ports on the router already in use? If so and you don't have a spare Ethernet switch, go buy a used 10/100 or gigabit switch for $10-15 on Craigslist and have the seller throw in a few Ethernet cables too so you can connect the PC and the analyzer together though the switch to your router.To configure the 1670E, on the main System screen set the Controller / Connected To: Ethernet (instead of HPIB or RS-232C). That is not necessary for FTP data transfers, but is for FTP control transfers.Then go the the System / Lan Settings screen. Set the Lan Port: to LAN TP (instead of LAN BNC). Then set the Analyzer IP Address: to a free address on your local network, and the Gateway IP Address: to the appropriate address for your network. Then go to the System / Lan Settings / Subnet Mask screen. You can either set the Subnet Mask: to the appropriate value for your local network, or if you set it to 0.0.0.0 it should automatically be configured to the correct value.On a Windows PC you can use the ipconfig command to get the local network parameters for your PC to find the Subnet Mask and Default Gateway, and from its IPv4 Address make a good guess about an appropriate free address you can use for the analyzer. For example on my PC at the moment the router / default gateway is at 192.168.1.1, the subnet mask is 255.255.255.0, and the router has assigned the address 192.168.1.103 to the PC. In this case the router has started assigning DHCP addresses at 192.168.1.100, and I picked 192.168.1.200 as a fixed free address for the analyzer. If you log in to the admin page of your broadband router you should be able to find a DHCP page which shows the dynamic range it is configured to use. Pick something outside of the dynamic range within the same subnet.Code:C:\>ipconfigWindows IP ConfigurationEthernet adapter Ethernet:Connection-specific DNS Suffix . : blah blah blahLink-local IPv6 Address . . . . . : blah blah blahIPv4 Address. . . . . . . . . . . : 192.168.1.103Subnet Mask . . . . . . . . . . . : 255.255.255.0Default Gateway . . . . . . . . . : 192.168.1.1System screen, set the Controller / Connected To: EthernetSystem / Lan Settings screen. Set the Lan Port: to LAN TP. Set the Analyzer IP Address: and the Gateway IP Address: to values appropriate for your local networkSystem / Lan Settings / Subnet Mask screen. Set the Subnet Mask: to the appropriate value for your local network, or if you set it to 0.0.0.0 it should automatically be configured to the correct valueUsing FTP from the PC to capture a screen image:Code:C:\HP-1670E>ftp 192.168.1.200Connected to 192.168.1.200.220 HP167XE V02.02 FUSION FTP server (Version 3.3) ready.500 Command not understood.User (192.168.1.200:(none)): data230 User DATA logged in.ftp> dir200 PORT command ok.150 Opening data connection for (192.168.1.103,55607).dr-xr-xr-x 2 1 1 766 statusdr-xr-xr-x 4 1 1 894 systemdr-xr-xr-x 3 1 1 766 slot_a226 Transfer complete.ftp: 138 bytes received in 0.01Seconds 9.20Kbytes/sec.ftp> cd system200 Remote Directory changed to "/system".ftp> dir200 PORT command ok.150 Opening data connection for (192.168.1.103,55608).dr-xr-xr-x 4 1 1 638 diskdr-xr-xr-x 2 1 1 894 graphics-rw-rw-rw- 1 1 1 0 program-rw-rw-rw- 1 1 1 1 setup.raw226 Transfer complete.ftp: 187 bytes received in 0.03Seconds 6.03Kbytes/sec.ftp> cd graphics200 Remote Directory changed to "/system/graphics".ftp> dir200 PORT command ok.150 Opening data connection for (192.168.1.103,55609).-r--r--r-- 1 1 1 1 screen.pcx-r--r--r-- 1 1 1 1 screenbw.tif-r--r--r-- 1 1 1 1 screen.tif-r--r--r-- 1 1 1 1 screenbw.epi226 Transfer complete.ftp: 203 bytes received in 0.03Seconds 6.34Kbytes/sec.ftp> bin200 Type set to Image.ftp> get screen.tif screen1.tif200 PORT command ok.150 Opening data connection for screen.tif (192.168.1.103,55611) (308934 bytes).226 Transfer complete.ftp: 308934 bytes received in 1.34Seconds 229.86Kbytes/sec.ftp> bye221 Goodbye.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 03, 2019, 02:59:02 am
content: right on. I think my failure has been thinking I could just attach a normal cable from the computer to the analyzer.

author: gslick
author_rank: Frequent Contributor
timestamp: March 03, 2019, 03:40:01 am
content: Quote from: Dan Moos on March 03, 2019, 02:59:02 amWell that could work too, with a crossover patch cable instead of a straight through patch cable, as was already mentioned by others. If you don't have a crossover patch cable a decent computer store in your area should have some, or some place like Fry's if you have one of those near you.I just tried this with my PC and 1670E. I had the network settings of both the PC and the 1670E exactly as before when they were both connected to a switch. I unplugged both from the switch and connected a crossover patch cable between the PC and the 1670E and the network connection between the two worked as it did when they were both connected to the switch. If you don't mind temporarily disconnecting your PC from the Internet, then using a crossover patch cable between the PC and 1670E might be your easiest solution.

author: TK
author_rank: Super Contributor
timestamp: March 03, 2019, 04:57:27 am
content: Quote from: Dan Moos on March 03, 2019, 01:04:37 amExternal USB floppy will be MS-DOS format, 1.44MB. You need to use a High Density (HD) disk. Open a command or cmd window and format the floppy (format a:). Copy the files to the A: drive. Once on your logic analyzer, you need to copy them one by one (I did not find another way) by using the COPY command from the System -> Floppy menu. You can first create a new directory on the Hard Drive of the logic analyzer, then CD to the directory (all by using the system menus) and then copy the files from the floppy to the new directory. This way, you will have the IA files better organized.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 03, 2019, 05:16:46 am
content: I think I'm gonna go that route. Have a floppy drive and disks on the way. Strange how little removable storage we use these days! Wev'e come a long way from my days of loading software onto my TI 994/a via cassette tape!This analyzer is great so far. I knew it was more advanced than the 1631d I was using before, but didn't realize how much. The triggering options alone are gonna be a godsend.

author: gslick
author_rank: Frequent Contributor
timestamp: March 03, 2019, 07:34:35 am
content: It is still very much worth the effort of getting a network connection set up to the analyzer for copying data off of the analyzer.One thing I have typically done when analyzing the operation of a microprocessor system is to capture a state listing, then "print" the listing to a disk file on the hard disk. With a 1M deep sample capability of the 1670E it is easy to generate a listing file that is several MB in size on the hard disk. I often find it much easier to move a large listing file from the analyzer to a PC for further analysis instead of trying to view and scroll through the file on the analyzer. If the state depth of a listing file is more than around 16K to 32K states it can easily exceed the size of a 1.44MB floppy, in which case a floppy could not be used to transfer the listing file between the analyzer and a PC.

author: gslick
author_rank: Frequent Contributor
timestamp: March 03, 2019, 09:15:10 pm
content: Quote from: TK on March 03, 2019, 04:57:27 amYou can also format the floppies on the 1670E to make sure they are in a compatible format. Make sure you use the default DOS Format option instead of the LIF Format option.You can copy all of the files from the floppy to the 1670E hard disk in one operation instead of one by one. Move to the File: field, then press the Clear Entry button and then press the Don't Care button. That enters a * wildcard character in the File: field.

author: TK
author_rank: Super Contributor
timestamp: March 03, 2019, 10:36:12 pm
content: Thanks for the wildcard tip... I was copying files one by one...

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 05, 2019, 03:06:38 am
content: Ok, I have my analyzer hooked up via ethernet cable to my router.An IP scan utility does indeed find it.other than that, I have no idea what to do. Googling has been useless

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 05, 2019, 03:32:21 am
content: Ok. Progress. I am at an FTP prompt in the command window. Found that Keysight link.What I'm not clear on, is whether I need PUT or GET to grab a file from my PC.

author: gslick
author_rank: Frequent Contributor
timestamp: March 05, 2019, 04:17:22 am
content: Quote from: Dan Moos on March 05, 2019, 03:32:21 amGET is from the FTP server on the 1670E to the FTP client on the PCPUT is to the FTP server on the 1670E from the FTP client on the PCYou can use MGET and MPUT to transfer multiple files with a wildcard file specification. You will be prompted to confirm each file before it is transferred (which can be annoying).You can log in as user DATA to transfer files. You need to log in as user CONTROL if you want to remotely control the 1670E by using PUT to transfer a PROGRAM file to the 1670E.In almost all cases you want to use the BIN command before transferring any files. Otherwise the default is text mode where CR/LF <-> LF (carriage return, line feed) translation occurs, which will corrupt binary files.You can use either the DIR or LS commands to list the files in current directory, CD to change the current directory, and PWD to print the current directory path. You can use the LCD command to change the current directory on the local FTP client running on the PC.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 05, 2019, 04:25:23 am
content: Ok, just before you posted, I realized there was a whole lot more to your previous posts. I'm IN!!! File transfer success!My biggest hang up was not realizing that the hard disk is several directories deep. Once that hurdle made sense, I was good.Thanks for the huge help. Seriously had no chance otherwise. After 3 days of bumping my head against the wall, it sure felt good to see my file successfully moved!

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 05, 2019, 05:12:00 am
content: Ok, New hurdle.I have all the files for a 6502 inverse assembler both on the analyzers hard disk, and on a floppy.How do you load them?

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 05, 2019, 06:12:30 am
content: Sorry for the shot gun of posts. I seem to have the inverse assembler running.The only human readable files that came with the IA was a text file he said which bits certain status pins should be on, and the .S file. In another thread, it was implied that I needed to get my label names exactly correct. I can find no documentation telling what I should do. Is there some way to glean this from the .S file?To be clear, it seems to be working, as I named my DATA bus DATA, figuring what else would you call it. Just wondering if naming the other busses correctly would add some functionality.

author: gslick
author_rank: Frequent Contributor
timestamp: March 05, 2019, 06:43:51 am
content: Do you have a link for the set of 6502 IA files you are trying to use? That is one set I am missing.An IA will always need at least three labels: ADDR, DATA, and STAT.ADDR is the address bus and DATA is the data bus. Those two should be obvious.STAT is a set of status signals from the microprocessor. The particular status signals needed and their order in the STAT label is defined by the IA. Hopefully the descriptive text file and/or the IA .S source code file would make it clear what status signals are needed and what their order needs to be in the STAT label. Without having those files to look at myself I couldn't guess the correct configuration.In addition to setting up the labels, you need the correct clock signals and clock specification for state analysis.

author: TK
author_rank: Super Contributor
timestamp: March 05, 2019, 01:05:37 pm
content: STAT information for 6502 (From 6502.S source file)* Inverse assembler for the Western Design Center W65C02S** INPUT_STATUS bits:* _* 7 R/W* ___* 6 RST* ___* 5 NMI* ___* 4 INT** 3 SYNC** Logic states must be clocked in on the falling edge of the 6502's* PHI2o (phase-2-out) clock.

author: gslick
author_rank: Frequent Contributor
timestamp: March 05, 2019, 05:23:37 pm
content: Quote from: TK on March 05, 2019, 01:05:37 pmOK, I finally found a link to a ia6502.zip file which appears to contain the same 6502.S IA source file. Looking at the source code it is clear that the SYNC signal is the LSB of the STAT label, and R/W is the MSB of the STAT label.What I am missing is what does the 3 - 7 mean for the STAT signals in that above comment? The bit positions in the STAT label would be 0 - 4?Code:NOT_TAGGED* what state is the CPU in?LOAD INPUT_STATUSIF 0,0 = 1 THEN GOTO DECODE_OPCODE ; opcode fetchCASE_OF 4,1OUTPUT RESET ; 0000 RESETOUTPUT RESET ; 0001 RESETOUTPUT RESET ; 0010 RESETOUTPUT RESET ; 0011 RESETOUTPUT UNKNOWN ; 0100 NMI AND INT (ILLEGAL)OUTPUT NONMASKABLE ; 0101 NMIOUTPUT INTERRUPT ; 0110 INTOUTPUT MEM_WRITE ; 0111 MEM WRITEOUTPUT RESET ; 1000 RESETOUTPUT RESET ; 1001 RESETOUTPUT RESET ; 1010 RESETOUTPUT RESET ; 1011 RESETOUTPUT UNKNOWN ; 1100 NMI AND INT (ILLEGAL)OUTPUT NONMASKABLE ; 1101 NMIOUTPUT INTERRUPT ; 1110 INTOUTPUT MEM_READ ; 1111 MEM READCASE_ENDRETURN ; not an op fetch so exit

author: TK
author_rank: Super Contributor
timestamp: March 05, 2019, 08:38:20 pm
content: I agree STAT signals should be 0-4, 0 being SYNC. Probably 3-7 was left in the source file as a comment and never updated.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 06, 2019, 03:05:23 am
content: What about the clock?It says (as I would expect) that I should clock on the falling edge of ph2o. But when I load the IA, it sets itself up to clock on the falling edges of the J+K clock. Is "+" an OR symbol, or and and? Also, what would I hook up to the second clock?It seems like things aren't exactly synced as they should be for me. I have it set to trigger on an address where a bit of code starts. It interprets that first opcode correctly. It seems to interpret most things correctly, but sometimes, it seems like it isn't taking the number of cycles an instruction takes into account properly.i initially had the STAT label bits set as the .txt file instructed (3-7). I now have it 0-4, in the order the file suggested, with SYNC being the LSB. I don't think it really made a difference. It definitely seems to be getting the R/W line right. I haven't tried to throw it an interrupt yet, but I'll try that next.Here is a perfect example of what is happening:My code says:STZ $05that opcode should take two bytes, and three cycles.The interpretation by the IE is: (status bits from left to right are R/W, RST, NMI, IRQ, SYNC)3 80F7 64 STZ $81 111114 80F7 64 STZ $80 111115 80F9 05 memory read 111106 0005 00 01110to me, line 4 is shouldn't exist, which could be why line 3 is wrong (should be STZ $05)if you took away line 4, it wouldn't be off the rails to me. It feels like a clocking problem.This result is completely repeatable, so its not noise on the clock line.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 06, 2019, 03:16:39 am
content: I'm also not clear on how to properly load the IE.I seem to be able to load either the I6502 or the C6502 files as analyzers. They seem to do he same thing, although C6502 is a way bigger file. Also, I'm not sure what happens when I load them one after the other as an analyzer. I know the .S file is the source. Not sure what to do with the .R file. I had thought before now that it was what I was supposed to load.I guess my questions are, what files do I load, and what do I load them as?

author: gslick
author_rank: Frequent Contributor
timestamp: March 06, 2019, 03:59:05 am
content: Where did you get the files you are using? I found a link to an ia6502.zip file here:https://stardot.org.uk/forums/viewtopic.php?t=11043That ia6502.zip file contains:2,690 6502.A14 6502.BAT9,452 6502.R27,480 6502.SThe 6502.S file is the IA source file. The 6502.R file is the relocatable output binary file that is produced by the 10391B assembler when it processes the 6502.S the IA source file. The 6502.R relocatable file is processed by the logic analyzer when the file is downloaded to the analyzer and transformed slightly into the IA file as it is stored on the analyzer disk. The 6502.R relocatable file cannot be loaded directly on the analyzer without going through the download transformation.(I forget exactly what the 6502.A file is, possibly a temporary symbol file used by the 10391B assembler when it processes the 6502.S the IA source file, which has no real use when the processing is complete).The ia6502.zip file I found does not contain a C6502 configuration file, or a downloaded version of the 6502.R relocatable file.An IA file contains instructions (and any necessary constants, variables, and strings) that are interpreted by the analyzer to decode each state in a state listing. It doesn't contain any information on how to set up the analyzer.A configuration file contains all of the information necessary to set up the analyzer. Timing mode vs. state mode, what pods are assigned to each analyzer, what channels are assigned to each label, channel polarity, pod mode (master, slave, demultiplex) clock configuration (which clock(s), polarity, qualifiers), trigger configuration, symbol definitions, etc. It can all add up to a large amount of data. A configuration file can also specify an IA file to be loaded, so if you load a configuration file which specifies an IA file, they both get loaded together.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 06, 2019, 04:29:05 am
content: Do I load these files as analyzers? You have to choose between All, system, analyzer, and symbol table. Analyzer seems to work.I guess, with the files I have, what specificly should I do to load things properly?

author: gslick
author_rank: Frequent Contributor
timestamp: March 06, 2019, 06:10:42 am
content: Where did you get the files you are using? It would make it easier to understand what you are seeing if I could start with the same files.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 07, 2019, 02:08:00 am
content: Here is the link to the ie.:https://www.eevblog.com/forum/testgear/hp-1631d-logic-analyzer/?action=dlattach;attach=317125

author: gslick
author_rank: Frequent Contributor
timestamp: March 07, 2019, 02:46:47 am
content: Quote from: Dan Moos on March 07, 2019, 02:08:00 amThanks. My searching wasn't working earlier when I only found ia6502.zip somewhere else online and didn't find the 6502_ia.zip file in the thread below.https://www.eevblog.com/forum/testgear/hp-1631d-logic-analyzer/#msg1213513That's embarrassing because not only did I post messages in that thread, I also downloaded the 6502_ia.zip file in that thread back in May 2017 when it was posted and I forgot about it and just found on my hard drive the copy I already downloaded.I'll try loading the 6502 IA file on my 1670E and attach it to a target system and see how it goes for me.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 07, 2019, 02:52:59 am
content: Thanks for your help! I did have dinner better results by grounding my clock probe. I mostly just want to stop guessing on how to make this thing work, and be confident knowing I'm doing it right. I don't really know what things should look like exactly when all is correct. My hope is that every instruction is decoded properly, and that every cycle in between at least make sense.

author: gslick
author_rank: Frequent Contributor
timestamp: March 07, 2019, 09:19:40 pm
content: I finally got around to setting up my 1670E connected to a target 6502 system.Instead of loading the configuration file from the 6502_ia.zip file I just created a configuration program file from scratch and used FTP to put that program file to the analyzer. This program file assumes that the IA file named I6502 is stored in the directory named \6502 on the analyzer hard disk. If you try using this program file yourself, edit the IA file name and directory name as appropriate for your analyzer.The inverse assembled states in the list display I captured look reasonable to me. In the capture below the first line in the list begins with the fetch of the reset vector.Code:C:\IA6502>ftp 192.168.1.200Connected to 192.168.1.200.220 HP167XE V02.02 FUSION FTP server (Version 3.3) ready.500 Command not understood.User (192.168.1.200:(none)): control230 User CONTROL logged in.ftp> dir200 PORT command ok.150 Opening data connection for (192.168.1.103,51980).dr-xr-xr-x 2 1 1 766 statusdr-xr-xr-x 4 1 1 894 systemdr-xr-xr-x 3 1 1 766 slot_a226 Transfer complete.ftp: 138 bytes received in 0.02Seconds 7.67Kbytes/sec.ftp> cd system200 Remote Directory changed to "/system".ftp> dir200 PORT command ok.150 Opening data connection for (192.168.1.103,51981).dr-xr-xr-x 4 1 1 638 diskdr-xr-xr-x 2 1 1 894 graphics-rw-rw-rw- 1 1 1 1592 program-rw-rw-rw- 1 1 1 1 setup.raw226 Transfer complete.ftp: 187 bytes received in 0.02Seconds 7.79Kbytes/sec.ftp> put program200 PORT command ok.150 Opening data connection for program (192.168.1.103,51982).226 Transfer complete.ftp: 1629 bytes sent in 0.01Seconds 108.60Kbytes/sec.ftp> bye221 Goodbye.Code::SELECT 1:MACHINE1:NAME '6502':MACHINE1:ASSIGN 1,2:MACHINE1:TYPE STATE:MACHINE2:ASSIGN NONE:MACHINE2:TYPE OFF:MACHINE1:SFORMAT:MASTER J, FALLING:MACHINE1:SFORMAT:REMOVE ALL:MACHINE1:SFORMAT:LABEL 'ADDR', POSITIVE, #H0, #H0000, #HFFFF:MACHINE1:SFORMAT:LABEL 'DATA', POSITIVE, #H0, #H00FF, #H0000:MACHINE1:SFORMAT:LABEL 'STAT', POSITIVE, #H0, #H1F00, #H0000:MACHINE1:SFORMAT:LABEL 'SYNC', POSITIVE, #H0, #H0100, #H0000:MACHINE1:SFORMAT:LABEL '-IRQ', POSITIVE, #H0, #H0200, #H0000:MACHINE1:SFORMAT:LABEL '-NMI', POSITIVE, #H0, #H0400, #H0000:MACHINE1:SFORMAT:LABEL '-RST', POSITIVE, #H0, #H0800, #H0000:MACHINE1:SFORMAT:LABEL 'R/-W', POSITIVE, #H0, #H1000, #H0000:MMEMORY:CD '\6502', INTERNAL0:MMEMORY:LOAD:IASSEMBLER 'I6502', INTERNAL0, 1, 1:MMEMORY:CD '\', INTERNAL0:MACHINE1:SYMBOL:REMOVE:MACHINE1:SYMBOL:WIDTH 'STAT', 12:MACHINE1:SYMBOL:BASE 'STAT', BINARY:MACHINE1:SYMBOL:PATTERN 'STAT', 'RESET', '#BX0XXX':MACHINE1:SYMBOL:PATTERN 'STAT', 'NON-MASK INT', '#BX101X':MACHINE1:SYMBOL:PATTERN 'STAT', 'INTERRUPT', '#BX110X':MACHINE1:SYMBOL:PATTERN 'STAT', 'MEM WRITE', '#B01110':MACHINE1:SYMBOL:PATTERN 'STAT', 'MEM READ', '#B11110':MACHINE1:SYMBOL:PATTERN 'STAT', 'OPCODE FETCH', '#B11111':MACHINE1:STRIGGER:CLEAR ALL:MACHINE1:SLIST:REMOVE:MACHINE1:SLIST:COLUMN 1, 'ADDR', HEXADECIMAL:MACHINE1:SLIST:COLUMN 2, 'DATA', IASSEMBLER:MACHINE1:SLIST:COLUMN 3, 'STAT', SYMBOL:MACHINE1:SWAVEFORM:REMOVE:MACHINE1:SWAVEFORM:INSERT 'ADDR', OVERLAY:MACHINE1:SWAVEFORM:INSERT 'DATA', OVERLAY:MACHINE1:SWAVEFORM:INSERT 'STAT', OVERLAY

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 08, 2019, 01:40:05 am
content: First of, that KIM is awesome!Questions:I've never read a configuration file, but it seems pretty obvious what it's doing.I'm curious. You made individual labels for STAT lines, along with single lable that has them all. I presume the individual labels are a convenience, and that the group label is what the IA is looking at?Next: Your list view on the analyzer is doing something mine isn't. As it happens, your opening assembly code is identical to mine. Not surprising, since setting the stack pointer to FF is the usual first task.Anyway, when the LDX opcode appears on the data bus, with all ones on the STAT lines, your STAT symbol says OPCODE FETCH. Makes sense. On the next cycle though, your sync line must go low, because you now show a read, whereas on mine, sync is still high. I assume that KIM has an original NMOS 6502, whereas my homebrew has a modern CMOS 6502. Perhaps it handles sync differently?Finally, is it standard that the configuration file should load the IA?

author: TK
author_rank: Super Contributor
timestamp: March 08, 2019, 01:56:04 am
content: That is a very impressive 8-bit vintage setup!!

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 08, 2019, 05:21:15 am
content: UPDATE:Things seem to be working as they should now. I noticed that when I probed SYNC with my oscilloscope, SYNC started appearing correctly on th analyzer. I put some capacitance from that pin to ground (figuring that's what my scope probe did), and voila!The whole shebang is currently bread boarded, so signal integrity is not great. Just trying to get a few things sorted out before I commit to having a PCB made. It's a 6502 computer, with a 7400 logic only implementation of VGA. Compared to your typical blinks light project, its gonna be a largish, 4 layer, expensive (to me anyway) board, so I'm trying to breadboard as much as I can before I spend the dough. Its pretty much ready to go, so I'll be off the janky bread board setup soon!

author: gslick
author_rank: Frequent Contributor
timestamp: March 08, 2019, 06:47:24 am
content: Good to hear that you got things working.If in doubt when things don't look right in state mode, switching to timing mode instead of state mode to see what the signals are doing all of the time and not just when they are sampled at a clock edge can give you a better picture of what is going on, and if things are really behaving as expected. Then if things don't look right in timing mode, pull out the scope to take an even better look, as you did.Before I saw your last reply I captured some notes about using timing mode. I added a Phase 1 label in addition to the Phase 2 label that was being used as the state clock so that the relationship of the two clock phases could be observed along with the rest of the signals.The timing mode waveforms captured below start at the rising edge of the /RESET signal and should match the states listings I posted previously. The first waveform display starts right at the rising edge of the /RESET signal, the second waveform display is scrolled slightly later in time to the right when the first few instructions start executing.Take a look at the Programmer’s Guide. It's fairly straight forward to figure out the configuration commands. Once you get the hang of it it can be easier to set things up exactly the way you want with a configuration command script instead of trying to use the analyzer front panel keys.HP 1670E-Series Logic Analyzers Programmer’s GuidePublication number 01670-97008First edition, August 1998https://literature.cdn.keysight.com/litweb/pdf/01670-97008.pdfExample timing mode configuration command script used for the screen captures below:Code::SELECT 1:MACHINE1:NAME '6502':MACHINE1:ASSIGN 1,2:MACHINE1:TYPE TIMING:MACHINE2:ASSIGN NONE:MACHINE2:TYPE OFF:MACHINE1:TFORMAT:REMOVE ALL:MACHINE1:TFORMAT:LABEL 'PH2', POSITIVE, #H1, #H0000, #H0000:MACHINE1:TFORMAT:LABEL 'PH1', POSITIVE, #H2, #H0000, #H0000:MACHINE1:TFORMAT:LABEL 'ADDR', POSITIVE, #H0, #H0000, #HFFFF:MACHINE1:TFORMAT:LABEL 'DATA', POSITIVE, #H0, #H00FF, #H0000:MACHINE1:TFORMAT:LABEL 'STAT', POSITIVE, #H0, #H1F00, #H0000:MACHINE1:TFORMAT:LABEL 'SYNC', POSITIVE, #H0, #H0100, #H0000:MACHINE1:TFORMAT:LABEL '-IRQ', POSITIVE, #H0, #H0200, #H0000:MACHINE1:TFORMAT:LABEL '-NMI', POSITIVE, #H0, #H0400, #H0000:MACHINE1:TFORMAT:LABEL '-RST', POSITIVE, #H0, #H0800, #H0000:MACHINE1:TFORMAT:LABEL 'R/-W', POSITIVE, #H0, #H1000, #H0000:MACHINE1:TWAVEFORM:REMOVE:MACHINE1:TWAVEFORM:RANGE 10E-6:MACHINE1:TWAVEFORM:DELAY 4600E-9:MACHINE1:TWAVEFORM:INSERT '-RST':MACHINE1:TWAVEFORM:INSERT 'PH1':MACHINE1:TWAVEFORM:INSERT 'PH2':MACHINE1:TWAVEFORM:INSERT 'SYNC':MACHINE1:TWAVEFORM:INSERT 'R/-W':MACHINE1:TWAVEFORM:INSERT 'ADDR', OVERLAY:MACHINE1:TWAVEFORM:INSERT 'DATA', OVERLAY:MACHINE1:TTRIGGER:CLEAR ALL:MACHINE1:TTRIGGER:ACQUISITION MANUAL:MACHINE1:TTRIGGER:TPOSITION POSTSTORE, 90:MACHINE1:TTRIGGER:SPERIOD 8E-9:MACHINE1:TTRIGGER:EDGE1 '-RST', 'R':MACHINE1:TTRIGGER:FIND1 'EDGE1', OCCURRENCE, 1

author: gslick
author_rank: Frequent Contributor
timestamp: March 08, 2019, 07:04:18 am
content: Quote from: Dan Moos on March 08, 2019, 01:40:05 amYes, the IA only uses the ADDR, DATA, and STAT labels.Breaking out each signal in the STAT label into individual labels is just for convenience. It might be helpful to make some things more clear in the list display to have separate columns for the signals, and in the waveform display to have separate waveforms for the individual signals.Also, in the trigger configuration it can be easier to specify levels or edges of individual signal labels, instead of specifying them as bits inside the STAT label. For example in the timing trigger specification screen capture in my previous reply I specified the rising edge of the -RST label as the Edge1 term, instead of specifying it in the STAT label.

author: Dan Moos
author_rank: Frequent Contributor
timestamp: March 09, 2019, 06:00:48 pm
content: couple bits of curious behavior.I have it set up to trigger on the first address where my code is run. My first opcode is LDX #$FF (the usual deal for setting up the stack pointer)The analyzer triggers as expected, shows the proper HEX for the opcode (A2), but doesn't show the mnemonic (LDX #$FF). The symbol in the STAT line says OPCODE FETCH (I just copied your settings for the STAT symbol table)From that point on, the mnemonics are always displayed as expected. Just that one first opcode does this. Other calls to LDX immediate mode display properly, and in fact, if I trigger earlier (on the cycles where the reset and IRQ vectors are set up), when it get to that line, it works correctly.Another curiosity, that I suspect might be a signal integrity issue again, but thought I'd throw by you.I call PHX to save the X reg on the stack. Th analyzer output is as expected. One cycle to fetch the opcode. On cycle that is the opcode both running, and the next opcode being put on the data bus (neat to actually watch the pipelining happen!), and one cycle that is a write to the stack.PHY is exactly the same. PHA is the same, except instead of a write to the stack, I get a read from ROM. What makes me think its a signal integrity thing, is that the low byte of the ROM address being read is the expected low byte of the stack address I wanted to write! The high byte is the high byte of the part of ROM where the program counter should be. Seems like the anaylizer is working fine, and that this must be a problem with my sketchy bread board set up. Concur?Also, how are you getting screen shots? Does the analyzer have a way to do this, and you are grabbing them via the ethernet connection?

author: gslick
author_rank: Frequent Contributor
timestamp: March 09, 2019, 07:56:15 pm
content: Quote from: Dan Moos on March 09, 2019, 06:00:48 pmI'll reply to the easy part first.You can use FTP from the PC to capture a screen image. Make sure you use the FTP BIN command to set the transfer mode to binary before using GET to transfer the file from the analyzer to the PC. (I also used an image editor on the PC to convert the TIF format image files to PNG format image files before posting them here).The /system/graphics/screen.tif file is a dynamic file on the logic analyzer. It doesn't exist on the disk. It captures whatever is on the analyzer screen at the time the file transfer occurs.Code:C:\HP-1670E>ftp 192.168.1.200Connected to 192.168.1.200.220 HP167XE V02.02 FUSION FTP server (Version 3.3) ready.500 Command not understood.User (192.168.1.200:(none)): data230 User DATA logged in.ftp> dir200 PORT command ok.150 Opening data connection for (192.168.1.103,55607).dr-xr-xr-x 2 1 1 766 statusdr-xr-xr-x 4 1 1 894 systemdr-xr-xr-x 3 1 1 766 slot_a226 Transfer complete.ftp: 138 bytes received in 0.01Seconds 9.20Kbytes/sec.ftp> cd system200 Remote Directory changed to "/system".ftp> dir200 PORT command ok.150 Opening data connection for (192.168.1.103,55608).dr-xr-xr-x 4 1 1 638 diskdr-xr-xr-x 2 1 1 894 graphics-rw-rw-rw- 1 1 1 0 program-rw-rw-rw- 1 1 1 1 setup.raw226 Transfer complete.ftp: 187 bytes received in 0.03Seconds 6.03Kbytes/sec.ftp> cd graphics200 Remote Directory changed to "/system/graphics".ftp> dir200 PORT command ok.150 Opening data connection for (192.168.1.103,55609).-r--r--r-- 1 1 1 1 screen.pcx-r--r--r-- 1 1 1 1 screenbw.tif-r--r--r-- 1 1 1 1 screen.tif-r--r--r-- 1 1 1 1 screenbw.epi226 Transfer complete.ftp: 203 bytes received in 0.03Seconds 6.34Kbytes/sec.ftp> bin200 Type set to Image.ftp> get screen.tif pcfilename.tif200 PORT command ok.150 Opening data connection for screen.tif (192.168.1.103,55611) (308934 bytes).226 Transfer complete.ftp: 308934 bytes received in 1.34Seconds 229.86Kbytes/sec.ftp> bye221 Goodbye.

author: Bassman59
author_rank: Super Contributor
timestamp: March 10, 2019, 05:11:44 pm
content: Quote from: Dan Moos on March 03, 2019, 02:59:02 amAny reasonably-modern computer’s Ethernet port is auto-MDX, which means that a crossover cable shouldn’t be necessary, nor should a hub or switch between the analyzer and the computer.I have an HP1661 and I used to connect it to a PC directly all the time (two Ethernet cards in the computer). I say “used to” because I can’t remember the last time I turned it on.

author: kb5mu
author_rank: Newbie
timestamp: June 26, 2019, 11:14:33 pm
content: I am trying to load an inverse assembler on a 1670G, but I get errors like this one:Insufficient memory to load IAL - load abortedI've tried the Z80 inverse assembler (the one I want to use) and the 6502 inverse assembler (the one you're talking about in this thread).What kind of memory is it talking about? Is there anything I can do to free some up? These should work on a 1670G, right?Thanks for any help!-Paul KB5MU

author: gslick
author_rank: Frequent Contributor
timestamp: June 27, 2019, 12:49:44 am
content: Quote from: kb5mu on June 26, 2019, 11:14:33 pmMaybe the IA files you are trying to load are corrupted. How did you copy the IA files to the 1670G?

author: kb5mu
author_rank: Newbie
timestamp: June 27, 2019, 03:26:12 am
content: Thanks for helping!I used the Python script that purports to be equivalent to IALDOWN.EXE but over Ethernet. This one:https://bits.sigpipe.me/Software/HP/Tools/IALDOWN.pyiz80_i.r is 10616 bytes on the computer and the resulting file is 11264 bytes long on the 1670G and is recognized as type inverse_assem.New info: the 6502 inverse assembler DOES work on my 1670G, loaded the same way. It's only 9452 bytes on the computer and 10240 bytes on the 1670G. Operator error earlier.If I read back the two files from the analyzer via FTP, I see the same file sizes as on the analyzer, and here are MD5 hashes of them:MD5 (i6502) = 180cb26f40a39faa8b12254f212f1bf1MD5 (iz80_i) = 56b97d8b67cdcc668a269ec94df1d6c7-Paul KB5MU

author: gslick
author_rank: Frequent Contributor
timestamp: June 27, 2019, 04:25:48 am
content: You shouldn't need to use an IALDOWN transfer for the iz80_i.r inverse assembler. The downloaded version of the file iz80_i is already available. You can just do an FTP copy of the iz80_i file to the analyzer (make sure the FTP transfer mode is set to binary). The iz80_i file is what was available to customers, the iz80_i.r relocatable file version was recreated from the iz80_i file.The iz80_i inverse assembler is set up for use with the 64683A / 10300B Z80 preprocessor. It might require a slight modification to work correctly with the analyzer connected directly to a Z80 instead of through the preprocessor. I'd have to look at some notes about that. One of the CPU status signals is inverted by the preprocessor if I remember correctly, maybe the R/W signal.Edit:According to my notes in this thread the 10300B Z80 preprocessor does invert the /WR signal from the Z80 pin 22.https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485

author: kb5mu
author_rank: Newbie
timestamp: June 27, 2019, 07:03:11 am
content: Cool, thanks! I thought I had tried the original iz80_i file, but maybe something else was wrong at the time. Now I've loaded it successfully from the distributed iz80_i file. I do wonder what went wrong with the .r file, though.Thanks for pointing out the need for special signals to trace. I was aware of that from other postings of yours on this forum. I'm already making my own adapter PCB to plug into the Z80's system bus and hook up via HP 01650-63203 Termination Adapters, so it's easy to add the needed circuitry. At the moment I'm thinking I'll add the six inverters but skip the two buffers, but I need to think a little harder about the timing requirements before I finalize that decision. And do a breadboard test.My prototype board is out for fab right now, but it was based on my unfounded assumption that the inverse assemblers and details on how to hook them up would be impossible to locate after all these years. I had chosen a slightly different set of signals for my equivalent of STAT, but already had to add some delays to make it work. I'm going to assume the HP engineers spent more time figuring out the best way to deal with Z80 bus timing and switch to their definition of STAT. This forum has been incredibly helpful in that regard.Because I wasn't expecting to be able to use the analyzer's inverse assembler, I was planning to write my own post-processing program to convert a hex dump from the analyzer to a disassembly. I may still do that, because once the data is in the computer I can also combine it with actual source code, when I have it, which is far better than a primitive single-instruction disassembly.Again, thanks!-Paul