Internal power plane connection not detected by DRC in Altium - Page 1
Forum section: electronics / general

author: Alinik
author_rank: Contributor
timestamp: July 14, 2025, 07:40:52 am
content: Hi everyone,I’m having an issue in Altium Designer with a via that’s supposed to connect to an internal power plane. Here are the details:There is a via on the Bottom layer that ties to the 5 V power pin of a PSoC5 microcontroller.This via should make direct contact with the internal 5 V plane.However, nearby there are other vias that do not connect to the 5 V plane and actually drill through it, leaving an annular ring of isolation around them.As a result, this isolation ring prevents the 5 V via on the Bottom from properly contacting the internal plane.I understand that increasing the spacing between vias would fix the issue, but I’m puzzled why Altium’s Design Rule Check doesn’t flag it as an error.Are there specific clearance or via-to-plane rules I need to enable so that the DRC detects this situation?Note: when I select the 5 V plane in PCB view, the via shows the little “cross” symbol indicating a connection, yet in 3D view it clearly isn’t making contact.In the pictures, you can see the vias I refer to selected and circled in red.Thanks in advance for any suggestions!

author: bookaboo
author_rank: Frequent Contributor
timestamp: July 14, 2025, 11:13:58 am
content: Does it not give you an "unrouted connection" violation?If not, and assuming you have not made the connection elsewhere, then it might be a bug.I'm not 100% sure , but that pin not connecting to the polygon might not in itself be a violation, since there's no rule that the via needs to connect to that polygon, only to that net.

author: Alinik
author_rank: Contributor
timestamp: July 14, 2025, 12:04:10 pm
content: Thank you very much for your response.Currently, the Un-Routed Net Rules setting is already enabled, as you can see in the attached image.The pin is not connected to a polygon but to a power plane. As you can see in the picture, for example the blue circled vias is also connected to 5V and in the inner layer does not have an arc around it as it directly touches and contacts the plane of the inner layer.

author: ajb
author_rank: Super Contributor
timestamp: July 14, 2025, 02:25:56 pm
content: Is "Un-Routed Net" also enabled for Batch DRC in the DRC options? And you're running a batch design rule check, not just relying on online DRC to find this, right?I think the general advice these days is to avoid using plane layers where possible. They should make complex boards easier to work on since they're less computationally intensive than polygon pours, but they have some limitations and I've seen a number of people report connectivity errors with them. For most modest-size boards, using polygons on signal layers may be a better way to go -- you can always shelve polygons while doing other routing if performance is an issue.

author: thm_w
author_rank: Super Contributor
timestamp: July 14, 2025, 08:40:30 pm
content: In the second image it does look like it could be connected, just not very well, with a tiny sliver.The 3D view is not showing it correctly for whatever reason, there should be a copper pad surrounding the via. It should always have that pad unless you've messed with the via settings. Can you check those via properties?

author: Alinik
author_rank: Contributor
timestamp: July 15, 2025, 03:33:56 pm
content: I found that it is a known problem.https://bugcrunch.live.altium.com/#/bug/22977

author: thm_w
author_rank: Super Contributor
timestamp: July 15, 2025, 09:40:56 pm
content: That discussion is hilarious, links back to a bug report from 2013 which has the same issue, and the conclusion was:Quote