Renesas RX Architecture - Page 1
Forum section: electronics / general

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 09, 2022, 12:26:24 am
content: Anyone have anything to say, good or bad, about the Renesas RX MCU family? Specifically the CPU architecture? (I'm not interested in the development tools--they're just bog standard Eclipse--or the software libraries--I wouldn't use them).

author: brucehoult
author_rank: Super Contributor
timestamp: February 09, 2022, 08:32:06 am
content: I've never used it, but I want to know something about every ISA so I took a look.It's very CISCy. The register set is pretty good with 16 GPRs and only r0=SP is dedicated. The choice of instructions, naming of 16 and 32 bit values (Word, Long), instruction mnemonics and addressing modes are very reminiscent of M68k (but with a unified register file, obviously). Arithmetic is all 32 bit, but the MOV instruction allows you to specify a size. Single precision floating point operations use the same registers as integer. There are also a couple of larger "DSP" registers and operations on them, but I didn't look closely at those.The instruction encoding is *highly* variable, in 1 byte increments vs the 2 byte of M68K. For example theADD src,dstinstruction with an immediate value for thesrccan be 2,3,4,5, or 6 bytes long depending on whether the constant will fit into 4,8,16,24, or 32 bits. v2 addedADD src,src2,dstwith fewer addressing modes (only register to register, or with a literal) and other instructions such as SUB, AND, OR, XOR got three address register-to-register only.Relative branches have a similar set of lengths, but with the smallest offset field being 3 bits giving a displacement of +3 to +10 bytes. BRA, BEQ and BNE with a 3 bit displacement are single-byte instructions.Absolute JMP and JSR exist only in the form of jumping to the address held in a register -- presumably intended to be used only for pointers to functions, or calculated addresses such as switch/case statements. Return address is pushed on to the stack. There is also relative BSR with 16 or 24 bit or register offset from the current PC. RTS pops the stack and returns.There are MOVLI (Linked) and MOVCO (conditional) instructions for atomic operations (MOVCO fails is there was an interrupt).There is single register PUSH and POP and multiple PUSHM, POPM. Unlike the M68K's bitmap, RX uses a contiguous range of register numbers. RTSD discards a given number of bytes from the stack, pops a register range, then returns.Rotate through carry is by a single position, other rotates and shifts are variable.There are some byte-string oriented instructions, with both counted and until a 0 byte possible.I believe v3 only adds bitfield move, register bank switching, and an optional double precision FPU with its own register set.In summary:- very M68k-ish, but optimised differently- code should be more compact- no indirect addressing and at most one memory operand, so pipelined implementation is much easier.

author: mino-fm
author_rank: Regular Contributor
timestamp: February 09, 2022, 09:20:25 am
content: More then 10 years ago I played arround with RX210, RX610 and RX62 in comparison with STM32F407. Before that I've been familiar with Hitachi/Renesas H8/3000, H8S and H8SX replacing my M68K designs.I liked many details like discrete interrupt vectors, DMAC running forward/backward with offset, very fast Flash-ROM and many fine things I don't remember today. For my applications HEW IDE was a good solution.But at the end Cortex-M4 (STM32F407) has been much faster, allowed more compact code, much cheaper and you could buy it anywhere as single parts. No need to buy trays and waiting weeks or months for delivery.I have compared RX and STM32 controllers doing TFT-direct-drive QVGA displays. It ended up in a small STM32F407 solution:http://mino-elektronik.de/TFT-direct-drive/TFT-direct-drive.htmI don't know what Renesas is doing today. My favorites are STM32H7xx controllers.

author: brucehoult
author_rank: Super Contributor
timestamp: February 09, 2022, 10:52:52 am
content: Thumb2 has very good code density, but after looking into it, I can't see how it would beat RX on general-purpose code given the same quality of compilers.There are a lot of *other* advantages to a RISC design.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 09, 2022, 05:09:04 pm
content: Thanks for the replies, guys.M68K has always been one of my favorite architectures, but its current incarnation, ColdFire, appears to be moribund.

author: Harjit
author_rank: Regular Contributor
timestamp: February 13, 2022, 07:44:06 pm
content: I've seen the RX series used very successfully in robotics applications where others were using the STM32F4 and Microchip series parts.I think it was the RX6xx and RX7xx but I'm not sure.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 17, 2022, 04:00:17 am
content: I decided to give the RX a try and ordered an RX71M Revelation board. Surprisingly, the board was in stock at Mouser and I received it last Friday.The board is kind of sparse with only two user LEDs, a push button, a bunch of 0.1" pins breaking out most of the MCU's pins, a small color touchscreen display, and two USB ports, one of which is for the debugger connection, which emulates a Renesas E2 Lite. The board is little bigger than a credit card. The CPU runs at 240 MHz and has 4MB of FLASH and 552K of RAM.The documentation for the board is poorly written and I needed to really hunt for a lot of basic information, which wasn't easy to find. The MCU's documentation is much better. It's split into a datasheet and a 3000 page user's manual, which is typical for a lot of MCUs these days.I downloaded the Renesas IDE, E2 Studio, which is based on Eclipse, and adds a graphical configuration and pin mapping utility, and GCC for the RX. Installation went well, and everything started up fine. It took me about half an hour to get an LED blinky application running on the board. Over the weekend I ported my RTOS, which I originally wrote for the 68000 35 years ago, to the RX. It went quicker than I expected, as the CPU architecture is mostly clean without too many gotchas. As you would expect, porting an OS to a new CPU architecture is fairly straightforward as 95% of it is written in C and porting the assembly code didn't take long. Now I'm concentrating on writing drivers for the peripherals. Since I've already written drivers for many of the peripherals on the Renesas Synergy Cortex-M chips, I'm hoping the RX peripherals are either identical or close enough so I can minimize the effort here. The RX comes with a HAL that supports all this stuff, as you'd expect, but I prefer to write my own.The assembly language reminds me of the 68000. It's got enough stuff, like string manipulation instructions, to put it squarely in the CISC camp. Some instructions are oddly implemented, however. For example, the interrupt priority level is encoded as bits 24-27 in the processor status word. Changing them normally requires masking and shifting, but there's an instruction called MVTIPL which can set these bits directly--the only issue is that the only addressing mode it supports is immediate, so you can do something like MVTIPL #4 to set the IPL to 4, but there's no much more useful register direct mode, so you can't do something like MVTIPL R1. There's no matching MVFIPL instruction to read the IPL. Several other instructions have similar quirks. Perhaps this is fixed in the RXv3 ISA (the RX71M is RXv2).Overall I'm pretty impressed with the RX so far. I still need to read several thousand pages of documentation and get the peripherals working before I pass final judgement on it.EDIT: I've done a little more work with this board, and have encountered more of its limitations. Unlike many dev boards that have built-in debuggers, this board doesn't have a virtual serial port via the debugger USB port. Serial out to a PC requires connecting a serial-USB adapter to pins on the board. Inconvenient. ST Nucleo boards at 1/3 the price of this board have that. I've found that the register defines in the provided iodefine.h are very awkwardly structured, making it difficult to write drivers that support more than one port.I've ordered a board based on the RX72N. The RX72N is based on the newer RXv3 ISA, which has several additional instructions and features, including bit indexing instructions, and 15 register banks. The CPU can switch register banks in one clock cycle, so that should speed up interrupt handling as there's no need to save registers on the stack when entering an interrupt handler. I'm hoping this board isn't as limited as the current board.

author: brucehoult
author_rank: Super Contributor
timestamp: February 17, 2022, 05:37:25 am
content: Care to submit an entry forhttps://hoult.org/primes.txt?I think it should fare very well on the code size.Edit: I grabbed the gcc 8.3.0 (GCC_Build_20211125) and measured the size of the countPrimes() function, as usual.RX gcc 8.3.0 gets 184 bytes with -O and 125 bytes for -Os, which is pretty stunning.RV32IMC gcc 10.2.0 gets 216 bytes with -O and 160 bytes with -Os.Thumb2 gcc 9.3.0 gets 236 bytes with -O and 172 with -Os.m68k gcc 9.3.0 with -mcpu=68000 gets 210 bytes with -O and 172 with -Osm68k gcc 9.3.0 with -mcpu=5475 (Coldfire V4) gets 196 bytes with -O and 160 bytes with -Ossh4 gcc 9.3.0 gets 208 bytes with -O and 172 bytes with -Osmips32 r2 (i.e. pic32) gcc 9.3.0 gets 292 bytes with -O and 256 bytes with -Os (owwww!)I'm still interested in knowing the execution speed with -O

author: peter-h
author_rank: Super Contributor
timestamp: February 17, 2022, 06:37:07 am
content: Hitachi (Renesas) are good at running chips for many years.I have a product using the H8/323, going since 1994, and the last time buy was around 10 years ago, so it ran for 25-30 years. I worked on a project in 1991 when the H8/300 and H8/500 already existed. Then on the LTB you can order enough for a few years.Compare that with most uC makersST should be pretty good too.This will be project dependent but I don't think code size matters much these days. What generally bites you first is not enough RAM. Raw speed likewise... in most cases you have plenty, and bottlenecks are best addressed by addressing them specifically (e.g. using DMA).

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 17, 2022, 07:13:50 pm
content: Quote from: brucehoult on February 17, 2022, 05:37:25 amI took your code and ran it on my RX board. Here are my results for various optimization levels. Note: I commented out the calls to printf since I don't have that working yet, but the relative sizes should still be meaningful.GCC 8.3.0.202102:Optimization Level Time (Sec) Code Size (countPrimes)-O0 497.5 321-O1 176.2 184-O3 199.8 160-Os 219.2 125CCRX 2.08.01Optimization Level Time (Sec) Code Size (main+countPrimes)Level 0 450.5 251Level 1 233.1 162Level 2 187.7 121Level Max 202.0 123

author: brucehoult
author_rank: Super Contributor
timestamp: February 17, 2022, 08:50:55 pm
content: OK, I've added it, thanks, using my gcc -O1 code size (like everything else) and your CCRX level 1 execution time since you didn't do gcc -O1.Interesting that the number of clock cycles is right in line with Cortex M3 and M4 and xtensa in ESP32, but 50% to 55% more than simple pipeline RISC-V such as SiFive E31 and Alibaba C906. So it doesn't suffer from being CISC with highly variable instruction lengths, but it does suffer from using condition codes on this very branchy code where it (and ARM) often need "CMP;Bcc" while RISC-V does compare and branch in one instruction.

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 17, 2022, 10:01:16 pm
content: I just ran GCC -O1 and added it to my previous post. To my surprise, -O1 ran 23 seconds faster than -O3.

author: brucehoult
author_rank: Super Contributor
timestamp: February 18, 2022, 12:00:31 am
content: Quote from: Sal Ammoniac on February 17, 2022, 10:01:16 pmI'm confused why your -O1 code size is so different from what I got with the same source code and same compiler version!

author: Sal Ammoniac
author_rank: Super Contributor
timestamp: February 18, 2022, 12:21:48 am
content: I corrected the entry for -O1. What I had there previously was countPrimes+main. Now it's just countPrimes.

author: brucehoult
author_rank: Super Contributor
timestamp: February 18, 2022, 01:32:13 am
content: Quote from: Sal Ammoniac on February 18, 2022, 12:21:48 amOK, now we're in agreement :-)-O1 is a good everyday optimisation level. It compiles fast and does the most important optimisations, but without trying to be too clever and getting itself into trouble. If you write good C code you'll get good asm code...