Selecting an op-amp for integrator - Page 1
Forum section: electronics / general

author: macaba
author_rank: Regular Contributor
timestamp: May 04, 2020, 10:55:07 am
content: I've got a good idea of how to select op amps for general applications but I've hit the limits of my knowledge for this application:What are the important specifications for an op-amp used as an integrator in an integrating ADC? (for a 7.5/8.5 digit meter)Edit: I intend to use correlated double sampling, so zero-drift isn't necessarily required which is useful for avoiding any charge injection effects of AZ topologies.Thanks.

author: David Hess
author_rank: Super Contributor
timestamp: May 05, 2020, 04:02:03 am
content: The operational amplifier *must* be unity gain stable.Since the configuration is inverting, common mode effects can largely be ignored.High open loop gain will reduce the change in offset voltage as the output voltage changes. I often see cascaded designs and I suspect this is one reason but adding gain inside the feedback loop is tricky when unity gain stability must be maintained.. A cascaded design also allows a separate part to drive the load reducing thermal feedback to the input stage which limits performance, which usually means two operational amplifiers.Broadband noise is irrelevant but flicker noise will limit low frequency performance.

author: macaba
author_rank: Regular Contributor
timestamp: May 05, 2020, 09:29:18 am
content: Thank you, that is helpful.I do wonder about the cascaded designs and what performance gains they're trying to achieve in the specific case of integrating ADCs. I have been looking at reference sources for an answer but haven't found it yet.Requirements so far:- Unity gain stable- The highest GBW, whilst still satisfying 'precision/low-noise' requirements yet to be determined.

author: David Hess
author_rank: Super Contributor
timestamp: May 05, 2020, 06:56:12 pm
content: Quote from: macaba on May 05, 2020, 09:29:18 amI think there are two reasons:1. Higher open loop gain prevents offset voltage shift which would have been a larger consideration in the past when using lower performance operational amplifiers.2. Thermal feedback from the output to the input compromises precision and *also* limits open loop gain, so a cascaded design should be used anyway to limit thermal feedback but this applies to any precision circuit. If the open loop gain is already sufficient, then this takes the form of just adding a buffer to drive the integration capacitor and following stage.There are of course other considerations like minimizing the change in input bias current and offset voltage but you mentioned calibrating these out.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 05, 2020, 07:07:00 pm
content: Both low frequency and higher frequency noise can be relevant. For the lower frequency the relevant frequency is 1 / (2*T_int) if a simple +- / signal - zero chopping is used. So this is usually something like 25 Hz (50 Hz grid) maybe lower if longer integration at a piece is used.Higher frequency noise (e.g. 1 MHz range) can effect the final charge reading. This can be important for shorter conversions, like < 1 ms. Here the size of the capacitor is an important factor - the larger the cap, the more important the higher frequency noise.Current noise is also a factor in BJT based OPs especially the low frequency end.With modern JFET OPs one may not need a BJT based OP.A BJT based OP can also have a problem with lower slew rate / getting nonlinear when the input voltage reaches some 50 mV.Unity gain stability is not an absolute must, but it helps with the loop stability. The compromise needed for a non unity gain stable OP amplifies the (higher frequency) noise.For the very fast initial spike a low open loop Z_out can also be an advantage.The 2 OP (or more) compound integrator has some advantage in getting a lower voltage at the integrator input. The 1 OP integrator has an effective input resistance of some 1/ (2pi f C). So with a modulated input current there would be a square wave - with a variable input resistance this can lead to INL errors. With the 2 OP integrator the input voltage will show only short peaks and thus more like an offset, but hardly an INL effect. Often the "slower" OP in the compound integrator is the more critical, while most of the work is done by the other OP. This helps with thermal effects and supply ripple.The slower OP in the compound integrator can be slower by something like a factor 5 than the fast one. It does not need a high supply.The faster OP should have at least a little higher supply - like at least some 16-24 V.It helps to check the circuit in a simulation, including the output impedance (often missing in the models).An odd effect I found with the OPA172 (other OPs are likely also effected) is that the frequency response / phase reserve seems to change with the output current. This is usually not desirable, though in my case I did not find an effect on the ADC performance. The effect is quite visible on the scope however. So the type of output stage can have an effect and lower power OPs may have some disadvantage here.Similar cross over distortion at the output could be a factor, as this can effect the settling after a jump in the current.

author: macaba
author_rank: Regular Contributor
timestamp: May 05, 2020, 09:49:03 pm
content: 2 OP design is making more sense to me from the thermal feedback perspective. I'm still absorbing what Kleinstein said, that's one to sleep on.I did a simulation of the style of converter I want to attempt:The output waveform (yellow, 5v/div) and the Pin 2 waveform (green, 2mV/div):The frequency is 1.2kHz.As I want to do CDS (or as Kleinstein put it: signal/zero chopping) I would estimate that my focus should be minimizing these Pin 2 spikes.(I'm not so concerned about input drift as long as the drift is small within my chop period)Kleinstein: Would the OPA1641 & TLE2071 combination as used in your multi-slope converter be appropriate here?

author: Kleinstein
author_rank: Super Contributor
timestamp: May 06, 2020, 10:00:53 am
content: For the 2 OP compound integrator there are many option, and 2 OPs to select. The fast one for the output mainly needs to be fast, noise is determined by the other OP. The "slow" OP should be at least 1/10 the speed to make full use of the fast OP, faster is no problem. The critical parameter is more the noise at low frequency. One still has the resistors as a competing noise source, so there is limited gain once the noise is lower than some 20 nV/sqrt(Hz) at the low frequency end.The OPA1641 is rather similar to the OPA141, OPA140 , just slightly cheaper. These 3 should be good choices, at least the OPA1641 work well for me. It should also be Ok up to some 100 ms of integration time, with more the 1/f noise gets increasingly tricky and other OPs may be a better choice: either an AZ OP or a modern BJT based OP like OPA202 or ADA4077. Here the 1/f part of the current noise is an additional point to watch for.For the fast OP the TLE2071 worked but is has a nasty point: when saturated to the negative side (this can happen on start up) the supply current goes up quite a bit. So I replaced it with an OPA172. The OPA1641 should work there too. If really fast modulation is planed one could consider an even faster OP.For dampening the short spikes one can us an RC combination (e.g. 500 pF+50Ohms) towards ground from the integrator input. Just a capacitor also helps against the spikes, but can have a negative effect on the settling. Especially the 2 OP integrator may like that extra RC. Some switching spikes are kind of normal and not such a problem.The circuit shown is the Solatron type ADC with a forcing waveform. This type kind of needs long integration time to get high resolution, as there is no slow slop involved and the whole resolution comes from the "run-up". Even with modern parts it gets tricky to get a timing resolution high than some 10 ns. So this would be some 21 Bits after 20 ms. So higher resolution would need more like 200ms or even 1 s at a time and thus likely an AZ OP in the integrator. The forcing part also makes switching between inputs a little slower. One kind of needs to wait one cycle and it also adds to the higher frequency noise. There is another reason to prefer a higher frequency also for the forcing part, this is dielectric absorption. This can carry over some charge and causes some settling to the new reading. In the Solatron 7081 this is part of the trouble with the drift correction. A higher forcing frequency would help. So today I would consider more like 10-50 kHz for the forcing waveform and smaller capacitors. A smaller capacitor also gets a steeper slope and this easier to get low timing noise.It however needs a faster settling integrator.The resistor values look relatively low - with more current the switches get more tricky. I did some test with 10 K, but this is more to see the limits, and they do show up. Less current also reduces the spikes. Of cause it is not so much the resistor values but the current that matters.

author: branadic
author_rank: Super Contributor
timestamp: May 06, 2020, 12:32:14 pm
content: QuoteWell, the drift correction is a timing bug in IC803, that was already fixed by MickleT. I'm expecting results on that soon, once the EPROMs have arrived.-branadic-

author: Kleinstein
author_rank: Super Contributor
timestamp: May 06, 2020, 01:30:35 pm
content: I don't think the trouble is a strict timing bug, but more like some kind of settling effect after switching between different voltages. Likely DA is causing the delayed reaction and thus the need to wait longer, so that at least the faster part can decay.

author: macaba
author_rank: Regular Contributor
timestamp: May 06, 2020, 05:51:10 pm
content: Quote from: Kleinstein on May 06, 2020, 10:00:53 amMy aim is to bring the solartron design into the 21st century so I would be happy to investigate a higher forcing frequency especially if modern OPs & parts facilitate this. I've already got a 100MHz counter in the design so that 10ns resolution is there. I do not mind the long integration times - my aim is to get the most performance from the least parts, and the attribute that suffers will be the necessity for a long integration. (it's the "3 things, pick 2" principle at play)Interesting thing about doing a much higher forcing frequency to get a smaller capacitor; opens up the possibility of using the AVX MLO series with its extremely low DA.I will increase those resistor values, and try OPA1641 + OPA172.In the hypothetical case of a 10kHz forcing frequency, the mode of operation I was considering is:- Switch input to Vin- Discard 10 cycles for settling- Capture 1000 cycles- Switch input to 0V- Discard 10 cycles for settling- Capture 1000 cycles& repeat. Repeat as many times to get the desired integration time/digits.I suspect 1000 cycles will end up being some other value - perhaps related to the 'frequency knee' of the noise density where it transitions from flat into the 1/f region.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 06, 2020, 06:43:20 pm
content: The concept looks reasonable. The choice of modulation frequency and the actual OPs can be adjusted later if needed.The ADC with forcing signal is relatively simple, so it may still make sense, though not the lowest noise. It may have quite good linearity however. This is usually the more difficult part.A higher frequency for the forcing signal has 3 positive effects:1) The actual integration time gets closer to the nominal one.2) There is less effect of DA (about ~ 1/f)3) The slope is steeper and thus better timing resolution with the same voltage noise level.There are mainly 2 down-sides:1) The settling of the integrator is more critical, one may need faster OPs2) Errors related to the switching (e.g. charge injection, jitter) get more important.A higher speed may also be needed for driving the reference signals.A point to decide is still if one wants one or 2 comparators. As far as I understand it, the 2 comparator version can use a lower amplitude of the forcing signal and this way get less complications there. It also gives a little extra resolution. It however needs more hardware: 2 comparators and dual reference switching.From my understanding one could get away with a different time resolution / clock for reading the comparators and the control of the feedback signal. So one could use a lower frequency clock for the synchronization (external flipflops) and the full clock only for measuring the comparator timing (e.g. inside an FPGA or µC).

author: macaba
author_rank: Regular Contributor
timestamp: May 06, 2020, 07:29:55 pm
content: Simplified schematic of high speed (10kHz+) design.Hasn't got 2 OP because I copied this simplified schematic from my simulation schematic and spice gives me a time-step too small error if I simulate 2 OP.Some points:- Forcing waveform, input mux (which also has +10V and -10V inputs for self cal), and control waveform are all using ADG1223/ADG1221 due to low charge injection that is consistent over the full voltage range.- To avoid running clock signals near sensitive circuitry, the flip flop is asynchronous (to the 100MHz clock domain) by using set/reset inputs. The counter inputs on the uC have synchronization circuitry to synchronize to the 100MHz clock domain inside uC.- 100k resistors are LT5400 based (hence why R7 and R9 are in parallel rather than being 50k). Precision/stability of the 150k resistor isn't that important (afaik).Given that the forcing waveform is using the same highly stable +/-10V source as the control waveform, self-cal inputs & comparator thresholds, do I need C2?

author: Kleinstein
author_rank: Super Contributor
timestamp: May 06, 2020, 08:18:30 pm
content: C2 is definitely needed. It is not only there to isolate the integrator from DC current, but also part of generating a good forcing waveform. C2 does not need to be super high quality though - DA is not important here.The control signal has to be synchronized before effecting the reference switches(s). The comparator signal going to the µC for reading the exact timing does not need an extra sync if the reference control signal is also sampled (possibly slower). Depending on the µC, one could get away without external counters and use the µC internal timer capture unit(s). So the external logic could be limited to 2 or 3 flip flops to synchronize the ref. control signal(s) and the forcing signal (not sure if really needed, but it would help). The µC would read the ref. control and the comparator signal(s).The ADG122x are really good switches, but not sure they are the right choice here. Low charge injection helps a little to simplify buffering the reference, however it is note really needed with the switch at the reference side. One may more prefer faster switching and lower on resistance. Especially for the input side the variation of the resistance with voltage would be a problem. So the better choice there would be more like an DG411 or similar very low resistance switch, possibly discrete MOSFETs like 2N7000 or even lower R_on.For the reference I would more like think about DG419 or similar.

author: macaba
author_rank: Regular Contributor
timestamp: May 06, 2020, 09:30:30 pm
content: I'm still not clear on why the reference switching needs to be syncronized, I will try probably try both. The forcing waveform will be synchronized as the forcing waveform control signal is generated by the uC that has the onboard 100MHz counters (timer peripheral).Input mux - DG411 looks good. I'm not sure the resistance variability matters so much if the input path is [Input/0V/10V/-10V -> Mux -> JFET amp -> Integrator] due to the JFET amp buffer. JFET amp will be unity gain to start with, switchable gains later.Reference/forcing switching - DG419 looks good, especially with regards to variation over temperature and lower resistance. I wonder if there is justifiable benefit to using a unity gain AZ OP after the switching to eliminate the switch resistance variability influence?(21st century has given us cheap & good AZ OPs, so no problem to add if there's a small benefit)

author: jbb
author_rank: Super Contributor
timestamp: May 06, 2020, 09:42:11 pm
content: I’m by no means an expert, but I understand that zero drift opamps should be treated with some caution.I think they may experience a sort of extended settling time following a large input change - probably not relevant here because input common mode is zero. Also, there are multiple internal types (full chopper, chopper stabilised, some hybrids?) which may exhibit different behaviour to source and load steps and leak differing amounts of energy at the chopper frequency.As I recall, Kleinstein’s excellent multislope ADC thread mentions biasing opamp outputs to get the output stages into class A. If you have an op amp with enough gain and slew rate, how about a simple BJT output buffer loaded with a BJT current sink? Provides current gain, hopefully lowers output impedance and gets the heat out of the opamp. The BJT base current may be enough to get the opamp into Class A, or a modest base to emitter resistor could be added.On simulation: I often find that adding something like a 1Meg to ground at the troublesome node can help with numerical issues. Also don’t try to include power supply impedances and decoupling caps until you really need to.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 07, 2020, 07:45:07 am
content: If switching at the input is with an extra buffer after the switching, the switch resistance does not matter any more. This is very viable for the signal input and does not even need an AZ OP if a regular zero reading or similar is done.For the reference side buffering after the switches is tricky and probably not viable as the settling would have a large effect so temperature effects on the slew rate would cause trouble. For the dual slope ADCs one kind of accepts the reference through the amplifier, but these are usually lower resolution and the reference is only switched a few times. If at all such an amplifier would not be an AZ type, but more like a super high speed (e.g. 100 MHz GBW, high slew rate one) - an offset would be corrected with the general offset.The easier way is likely with direct switches with good speed and low resistance. As the switch resistance would add to the overall gain drift, even the DG419 is on the high side with the resistance. There is some reason the Solartron 7071, HP34410, Keithley 2001 use discrete FETs.The FET switches have a TC for the ON resistance of some 6000 ppm/K. So even if the switch resistance is 1/1000 of the series resistor, this would leave 6 ppm/K for the overall resistance and ADC gain, in there is no compensation. So the target for the switches would be more like some 10 Ohms. In theory one could use dual switches, a little like in the Fluke 5700 series to eliminate much of the resistance - with a fixed reference this is not even so bad: one DG419 for +-10 V and one for some +-14 V for the correction.The reference switching definitely need to by synchronized - even to a good level (e.g. ns range). It sets the main resolution and thus has to be accurate. It can however use a slower clock (e.g. 10 MHz range). The forcing signal might get away without an extra external sync as it is generated by the µC and thus at least in sync with it's clock and on the long run would not contribute due to the capacitor C2. So a few ns error would not sum up.

author: macaba
author_rank: Regular Contributor
timestamp: May 07, 2020, 08:34:10 am
content: jbb - good suggestions with the BJT buffer and the 1M workaround, I’ll try those.kleinstein - thank you for your prolific input so far, it’s appreciated. I’m new to metrology, with some experience in analog electronics & much experience in digital electronics. Your input should help the first iteration of this design achieve better results than I dare hope for, which will keep me enthusiastic in my new voltnut hobby!My plan with the original asynchronous design was to only have the ‘PWM’ reference control signal entering the uC, the comparator signals were not going to be read by the uC. Just a single line to read. Following your input, I think I will adjust in the following way:The comparators outputs will be carefully routed over to uC section of the board (which has its own EMI shield) to enter sync flip flops which are clocked at 100MHz. The flip flop clock pins will be right next to the uC 100MHz output pin to absolutely minimise the trace length. The synchronised reference control signal will renter the analog section and switch the references. I still intend on using the reference control signal only for measurement as it should now be a faithful & synced representation of the the comparator output (just with 10-100ns of flip flop delay).I will look into the discrete FET scheme (rather than investigating the AZ buffer suggestion I had). I can obviously look at service manuals of old instruments for inspiration but I have to wonder if there is a modern solution (maybe MOSFET gate driver ICs intended for motor control).

author: jbb
author_rank: Super Contributor
timestamp: May 07, 2020, 08:59:48 am
content: On the BJTs: I have no idea how well it might work. Good luck.On switches: are you planning to switch a voltage signal into the circuit, or something more complex?It might not be worth the trouble, but you could try using 2 high resistance (and hopefully low leakage and charge injection) switches. One on the output of an opamp and one on the feedback line. In principle the opamp loop will compensate out the voltage drop...But there’s no such thing as a free lunch. More switches means more leakage and charge injection. But the switches are smaller. But the voltage drop across the higher resistance switches will eat up headroom eat up some of the opamp open loop gain.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 07, 2020, 09:57:09 am
content: I have though about those gate drivers too. However they are usually only for relatively low voltage like 15 V max. There may be gate drivers intended for GaN / SiC Fets that can work with some 20 V, that may be an option for the reference switching. One still has the compromise on resistance and charge injection towards the reference driving circuit.I see 4 options here:1) low R switching with CMOS switches / discrete FETs / gate driversthis would also need more effort buffering the reference.2) not so low R switching and some compensation with a suitable FET also in the input path3) 2 stage switching with one for the voltage and a 2 nd to deliver an approximate current from a higher auxiliary reference (5700 like)4) use switching at the integrator side (e.g. more like the HP34401). This is easy, but has a few of its own problems with very long integration at a time.Which µC is planed ?Many of the newer fast µCs have an internal PLL and this may contribute to jitter. So the µC generated 100 MHz clock would not be absolute pure. So the more logical way would be to use a slow, e.g. 10 MHz clock to synchronize the reference control signal directly to a crystal clock and read the comparator timing relative to the µC clock derived from that 10 MHz clock. So no 100 MHz clock outside the µC and the µC would read two signals: the reference control and the comparator signal.For the forcing signal, there could be an option to go a little beyond the original solartron design: use a separate "integrator" (low pass filter) for the forcing signal and this way reduce the noise and avoid some complications for the DNL. It keeps the principle idea of the forcing signal to produce a relatively good feedback at a forced frequency, just from the other input of the comparator. Chances are this could give better performance with moderate extra effort.

author: macaba
author_rank: Regular Contributor
timestamp: May 07, 2020, 10:22:50 am
content: How about 2 or 3 DG419 in parallel?uC = STM32F411CEU6, driven from 25MHz crystal, through 4x PLL.The uC clock routing does allow bypass of the PLL (if the PLL jitter is too much) for a system clock of 25MHz, thus making only the crystal specification important in that case. Given that longer measurement time is the compromise I consider to be acceptable, this could well be the end result. It's easily tested with both frequencies with no board level changes. The testing methodology comes at a later time (one step at a time) but I would guess the jitter will show up in the noise spectrum during testing.Interesting idea regarding the forcing signal - I think this sounds like a good 2nd iteration idea. I'm not even sure how I'm going to test INL/DNL yet with limited equipment...(charge a very large capacitor from stable voltage & resistor over 24 hours, do e^(-t/RC) curve of best fit to data and observe the deviation from this curve?)

author: macaba
author_rank: Regular Contributor
timestamp: May 07, 2020, 10:54:41 am
content: I'm thinking something like this, where U11 is the only IC located near uC.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 07, 2020, 02:45:30 pm
content: With the forcing signal the comparator levels would be much closer to zero, more like +-1 V, maybe even less, more like a comparator with a little hysteresis.Using 2 or 3 DG419 in parallel may work, though it also adds to the spikes seen at the reference. I would prefer 1 x DG419 with a higher voltage to provide the approximate current and the 2nd to get the final voltage only. Something like the 1 st from +-15 V than 25 K to the 2nd DG419 with the +-10 V reference and 50 K to the integrator (virtual ground). So ideally there would be no current flowing through the 2nd DG419 and thus no effect of the switch resistance. With real world tolerances there may be still some 1% of the switch resistance effective.

author: macaba
author_rank: Regular Contributor
timestamp: May 07, 2020, 05:13:38 pm
content: Quote from: Kleinstein on May 07, 2020, 02:45:30 pmI'm finding it difficult to visualise this so I started drawing it; what am I missing?

author: Kleinstein
author_rank: Super Contributor
timestamp: May 07, 2020, 05:34:24 pm
content: The missing like is from the right side of R1 to the left side of R2. One would either have 25 K for R1 and +-15 V at U1 or 20 K and +-14 V.U1 is providing the current for R2 to a first approximation and U2 is only doing a correction to the final value with a low current.

author: bsw_m
author_rank: Frequent Contributor
timestamp: May 07, 2020, 05:48:09 pm
content: Quote from: macaba on May 05, 2020, 09:49:03 pmYou have inverted driving signal for reference switches.P.S.1. IMHO increase integrator frequency is not a good idea. I think good frequency for integrator is 200...500Hz, maximum 1kHz.2. IMHO integrating capacitor DA not most important for this type converter and most affect for settling time for conversion result. Good for this propylene type or NP0 ceramic.With best regards, Alexey/P.P.S. DG419 is good switches but, I think, very slow if You want 10ns time resolution.

author: macaba
author_rank: Regular Contributor
timestamp: May 07, 2020, 07:04:46 pm
content: Interesting trick Kleinstein!0.2mA going to integrator virtual earth. Of that, 0.186mA is being sourced by U1, and more importantly, the effect of any U2 switch resistance changes significantly reduced. I also assume that R1 doesn't need to have a very low TC like R2 does.Quote from: bsw_m on May 07, 2020, 05:48:09 pmI welcome your input, do you have reasons why?

author: macaba
author_rank: Regular Contributor
timestamp: May 07, 2020, 08:19:42 pm
content: Also interesting; I was curious to see what a sine forcing waveform would do.Square forcing waveform:(Top = forcing waveform, Middle = Integrator output, Bottom = reference waveform)Can see spikes on integrator virtual earth for reference switching, and spikes for forcing waveform, approx. 33% of the magnitude of the reference switching spikes.Sine forcing waveform:(Top = forcing waveform, Middle = Integrator output, Bottom = reference waveform)33% magnitude spikes gone. I don't think this will be worth the effort to implement in reality.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 07, 2020, 09:03:35 pm
content: With this type of converter the DA causes a kind of settling when switching between different inputs. The effect may be relatively linear as the average voltage is relatively linear depended on the input. It can still be a hassle with frequent input switching like some auto zero mode. The DA settling can be really slow (e.g seconds to minutes). There is a chance the linear DA problem could be largely suppressed with the forcing signal to the other side, away from the main integrator.The other reason for faster modulation is getting more slope and thus an improved time resolution. One can also see the smaller capacitor as a way to reduce the effect of higher frequency noise. Here it is not so much the actual modulation frequency that matters but the size of the capacitor. A large capacitor this way limits the resolution possible at a given integration time. With too large a cap the noise would limit the useful timing resolution. So one kind of has to modulate faster for more time resolution.A faster modulation has some downsides: the errors from the switching process get more important. This would be things like settling of the integrator, jitter (should not be so bad) and also settling of the drivers for the reference. With a higher frequency they have less time. One may loose more of the theoretical range and getter higher INL near the ends, when the pulses get short.The ADCs with more fixed pattern feedback can tolerate less perfect settling, as there the imperfect settling causes more like a changed gain but only little INL error. They also need a faster modulation because of the DA causing more nonlinear effects.Anyway the modulation frequency would be a parameter to optimize later. 10 KHz may be a little on the high side, but I would expect more than 2 kHz to get a useful timing resolution in the 10 ns range.The extra Resistor R1 does not have to be as stable as the main integrator resistor. With a better trimmed values (e.g. reduce by the resistance of U1), the attenuation for the U2 resistance could get even better. So a relatively normal (e.g. 1 % tolerance) resistor would be OK. The DG419 would need a higher VCC and would thus have lower resistance.More speed could in deed help (e.g. with jitter), though it is not directly related to the time resolution.For the forcing waveform, there are options in between - already a slightly rounded square (some extra RC) can reduce the spikes.

author: bsw_m
author_rank: Frequent Contributor
timestamp: May 07, 2020, 09:36:51 pm
content: Quote from: macaba on May 07, 2020, 07:04:46 pmThe capacitor in this type ADC doesn't charge/discharge with input signal, like in dual-slope or multislope A-D converter/Capacitor used for forming linear ramp, but it's worked with virtualy zero charge.If you have increased frequency in integrator opamp have more distortion and less gain in result - less accurate ramp.

author: bsw_m
author_rank: Frequent Contributor
timestamp: May 07, 2020, 10:03:19 pm
content: About switches for reference currents.I'm propose this concept (in schematic I'm draw diodes, but in real switch better use p-n of high freq BJT).Negative ref connected constantly to integrator input. Positive ref used constant current generator with I=2*Iref-.Advantage for this switch:B-E junction of BJT have very low capacitance (less 1pf) and have maximum voltage amplitude about 1.5V, charge less than 1.5pC. And have very fast switching: less than 5ns.Due Iref- connected constantly and Iref+ have constant current generator we avoid problems with switch resistance drift and switch synchronization.With best regards, Alexey.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 08, 2020, 07:01:41 am
content: Switching only one side also adds to the noise, as the current sources also have current noise. It is attractive to use this with diode current steering, but it still is a disadvantage.The reference switching with diodes as current steering is possible, but this would be switching at the integrator side. It is possible (e.g. the old 3455 used this), but it also has it's problems. Fast diodes / transistors usually have higher leakage currents. So one has to choose careful there. With slower diodes / transistors there can be quite some reverse recovery / charge storage, well beyond the 5 ns.Switching at the integrator side needs separate resistors for the positive and negative reference current. This adds another source for zero point drift. It is thus less attractive with the long integration times and an AZ OP in the integrator.The charge in injection of CMOS / JFET switches is not such a large problem: it mainly adds a constant offset to the current. Only indirectly, with variations in the charge injection (e.g. due to supply variations) this can cause problems. There also is some statistical variations. So a small total gate / switch charge can be an advantage, when it comes to ultimate performance - not yet important for 7 digits.There still is some average charge dependent on the input voltage in the integrator. With a input near the positive maximum the integrator will swing mainly to the negative side, with only minimal positive values. The positive thing here is that the average voltage is quite well proportional to the input voltage. So there is same effect of the DA, but the effect is linear, carrying over a small fraction to the next conversion. In a simple signal - zero chopping mode this would give a slightly reduced gain, not not yet an INL. In addition one could correct such a linear effect numerically. One could compensate for the linear part, a little like HP does is many of there older meters (34401, 3456, 3457), if a separate comparator is used for the feedback and the final reading. AFAIK this is not normally done with this type of ADC.

author: macaba
author_rank: Regular Contributor
timestamp: May 08, 2020, 09:00:20 am
content: Quote from: Kleinstein on May 08, 2020, 07:01:41 amFor the benefit of those following along, this is the integrating waveform for inputs of 0V, +10V, -10V, showing a change in the average.0V:+10V:-10V:Alexey - thanks for showing the current switching concept, it's useful to know. With regards to DA - the average of the integrating waveform does change as Kleinstein says, but perhaps not enough to be concerned with. I am considering reducing the frequency to 2.4kHz (common multiple of 50/60/400) for the first version. This does mean switching to normal PP film capacitor (with 0.05% DA) as the AVX MLO with its 0.0015% DA becomes impractical/costly with the increased number of caps required in parallel at this lower frequency.Quote from: Kleinstein on May 08, 2020, 07:01:41 amIndeed - my aim is to reduce part count with the tradeoff of increased computational complexity in the uC. The input mux has +10V and -10V on it for a self-cal operation, that would presumably solve any slight change in gain (assuming it's linear and stable).Kleinstein: the dual DG419 scheme might also be used for the forcing waveform? Only to reduce burden on the voltage reference, I don't think the resistance variability matters? As far as I know; the 150k resistor specification doesn't need to be as good as the 100k/50k resistors?Edit: just calculated the current from the reference, where the dual DG419 used for reference waveform, but not used for forcing waveform; 0.014mA for reference, 0.066mA for forcing. Probably not worth the extra part count to have dual DG419 for forcing waveform.

author: bsw_m
author_rank: Frequent Contributor
timestamp: May 08, 2020, 09:54:14 am
content: Quote from: Kleinstein on May 08, 2020, 07:01:41 amIn real world we can't search any reference with zero noise. In reality constant current generator noise little more than noise from reference.In this concept I spent some time for dynamic correction for current generator. Output voltage variance is little (about 1V), but need little dynamic correction for current generator.Quote from: Kleinstein on May 08, 2020, 07:01:41 amYep, but with this schematic we have low level reverse voltage, not more than 0.6V. And in real schematic I have the leakage about 100-200fA with B-E junction of high freq BJT.And, leakage in switch is not big problem, this only add zero offset to integrator.Quote from: Kleinstein on May 08, 2020, 07:01:41 amWith good matched TC resistors its more like zero offset, but not zero drift.Quote from: macaba on May 08, 2020, 09:00:20 amAcceptably, attention to Gain and distortions on this freq.Quote from: macaba on May 08, 2020, 09:00:20 amYou can use any good metal film resistor with TC 25ppm or less. Select this resistor with good power margin.

author: macaba
author_rank: Regular Contributor
timestamp: May 08, 2020, 11:24:56 am
content: Pending feedback on any errors I may have made, attached is what I intend to build as version 1.

author: bsw_m
author_rank: Frequent Contributor
timestamp: May 08, 2020, 11:54:27 am
content: I'm not recalculate values of passives. But one problem is immediately visible: comparators in integrator referenced to +-10V. Connect this to ground.

author: bsw_m
author_rank: Frequent Contributor
timestamp: May 08, 2020, 12:43:35 pm
content: I quickly sketched a simplified diagram in the LTSpice. Only for reference.

author: macaba
author_rank: Regular Contributor
timestamp: May 08, 2020, 01:05:31 pm
content: I understand what you're thinking now. I'm thinking of a 2 comparator design, you're thinking of a 1 comparator with slope amp design.

author: bsw_m
author_rank: Frequent Contributor
timestamp: May 08, 2020, 01:30:42 pm
content: Not important one or two comparators use in design. Comparators must compare integrator output with "0". If You referenced comparators to +-10V, design cannot work.P.S.In simplified diagram, that I'm post, I'm not use the slope amplifier, but yes, I'm use one comparator. Trigger connected other than real design, due I'm not want to simulate clock signal.

author: macaba
author_rank: Regular Contributor
timestamp: May 08, 2020, 01:40:59 pm
content: Every simulation screenshot in this thread from me was using 2 comparator design on +/-10V levels. I'm unsure as to what 'design cannot work' really means.

author: Kleinstein
author_rank: Super Contributor
timestamp: May 08, 2020, 02:22:17 pm
content: It is OK to have 2 comparators for 2 slightly separate values. This can be either one comparator with quite some hysteresis or 2 comparators with some spacing. Using 2 comparators could be a little more accurate than the shift from the hysteresis. I would consider +-10 V levels as too much as the integrator would swing quite high. The forcing waveform together with the spacing set the feedback quality. The amplitude of the forcing signal should not be excessively large.The Spice file from BSW_m is using a 2 OP integrator, and no slope amplifier. An extra slope amplifier gets a little tricky for 2 comparator levels. It may still make sense if a second comparator for exactly zero is used for the final timing.

author: macaba
author_rank: Regular Contributor
timestamp: June 21, 2020, 03:44:10 pm
content: Thanks to everyone who contributed & gave me recommendations, I managed to get a working prototype together that works far better than I'd hoped.In attached image: ADC input = 0V, top trace = forcing waveform, middle trace = integrator waveform, bottom trace = 3.3V output waveform read by counters.Now begins the long task of characterising it. Any recommendations?

author: Kleinstein
author_rank: Super Contributor
timestamp: June 21, 2020, 05:31:34 pm
content: Congratulations to the working ADC.There are a few things one can do for characterization, even without special equipment. One of the first would be using a zero input and just record data to measure the noise. A longer set could also show if there is drift and if there is not much drift one could use an FFT for a noise spectrum to see if there is 1/f noise.For the noise one can look at short and longer integration times. Rather short integration (e.g. 20 ms, possibly less) would be effected by quantization and more higher frequency noise for the comparator. The long integration would be more a thing of low frequency noise. So one could see the ranges were higher / lower frequency noise dominates. The noise and stability would give a hint which other tests are possible / feasible in a reasonable time frame.From the data with a short one could also calculate an histogram. This could give first indications about possible DNL errors (however just at a single point).Another way to look for gross DNL problems would be recording a slow discharge of an RC combination (e.g. some 1000 µF and 10 M or the like). This should give a rather smooth, slowly changing voltage. This may tyke quite some time to record data sets (e.g. hours, maybe more if the ADC is relatively slow). The difference of consecutive readings should thus give relatively constant only slowly changing values. If there are larger DNL error these would show up as extra noise or outliers.A first step to INL testing is using an external reference and do the turn over test: so measure the same source with both polarities.

author: jaromir
author_rank: Unknown
timestamp: June 21, 2020, 06:25:26 pm
content: Quote from: macaba on June 21, 2020, 03:44:10 pmOh, this is great news.Is it the same circuit as per your post #33? What is your choice of forcing and reference waveform switches?

author: macaba
author_rank: Regular Contributor
timestamp: June 21, 2020, 08:23:55 pm
content: Quote from: Kleinstein on June 21, 2020, 05:31:34 pmThat's a great listing, I'll aim to do most/all of those and report back with the interesting points.Quote from: jaromir on June 21, 2020, 06:25:26 pmIt's mostly the same.The sections labeled "Input mux & amp" and "Overrange comparator" aren't built yet, I'll do that after the initial characterisation as it'll allow me to do an A/B comparison to see the effect of the input amp & mux.Using OPA140 for the integrator amps.The LM319's had to be replaced with different comparators as the Differential Input Voltage specification of the LM319 is vastly exceeded in my design (it just got warm and eventually failed).I replaced them with EL2018CN which works extremely well but presents me with a future problem - finding a suitable part that isn't obsolete. (I wonder what they now use in the modernised 3458A...)Also had to switch to the inverted Q output of U6 for the correct polarity (as reported by bsw_m in post #24).Using the DG419 for switches.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 21, 2020, 08:30:03 pm
content: For the comparators one could get away with the LM311 at slightly lower speed. Chances are the noise level would be more critical than pure speed. So far I have not seen noise specs with many comparators, so it is up to guesswork. A limited speed / bandwidth can actually be good as it reduces the noise.

author: macaba
author_rank: Regular Contributor
timestamp: June 22, 2020, 05:25:21 pm
content: I captured some initial data today to look at the 'least significant bit' noise.I programmed two profiles into the uC: 5SPS (samples per second) and 0.5SPS.5SPS corresponds to a little above 7.5 digit resolution.0.5SPS a little above 8.5 digit resolution.For each profile, the input is alternated between -10V/0V/+10V, where the +/-10V comes from the onboard reference (so the reference noise may be partially/completely reduced).60 seconds of data is captured.'Filter uVrms' and 'Filter uVpp' refer to the 10 second moving average trace.Ignore the absolute value error, it is an approximate calibration sufficient to get reasonable accuracy on the RMS and peak-peak values.5SPS:0.5SPS:Observations:- Going from 5SPS to 0.5SPS reduced the raw RMS noise to 35% but the 10 second moving average RMS & PP values stayed about the same. (To me that suggests a source of low frequency noise that I should attempt to reduce.)- The board is not inside an enclosure so there is airflow/magnetic field/electric field interference. I certainly can observe the effect of airflow. I'll need to resolve this before longer duration tests.- When switching from -10V to +10V, there is a settling period over about 20 seconds where it slowly drifts over 8uV to a final value. The main integrator caps are Wima PP film caps, but the forcing waveform coupling cap is a X7R 50V 0.1uF ceramic that may have DA? so I should swap that for a better cap to eliminate it as a cause. It's not clear to me yet what the selection criteria for the capacitance value of this cap is.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 22, 2020, 06:58:23 pm
content: Getting very similar noise for the 10 s average suggest that the 5SPS conversions does not have significant higher frequency or quantization noise. Without AZ mode both modes would see the full low frequency noise.The ratio of the noise at 5SPS and 0.5 SPS is relatively close to the square root of 10 value expected for white noise. So not yet much 1/f noise even for 0.5 SPS. Averaging from 5 SPS down to 10 seconds does not give a corresponding reduction (e.g. factor 7), but only a factor of 4. So there is some low frequency noise, but still not that dominant.To check for higher frequency noise, e.g. from the comparator, one may have to to a test with even shorter conversions. It is possible that a limited resolution (as quantization steps) can be the limiting factor here.If there is no amplifier / switching at the input, I would guess these are direct raw readings from the input, with no extra zero phase in between. So this would correspond to the non AZ case with a DMM. In this case one would also get the very low frequency noise from the integrator, like all the way down to 0.1 Hz. The integrator has some gain for the noise. Without the forcing signal, there would be a gain of 3 (if the reference resistor is 1/2 the input path resistor). The forcing signal may increase the noise gain, so a higher resistance, smaller cap is desirable. However one still needs enough strength to get stability.With the given values I would not expect that much extra noise gain from the forcing part. Chances are that the extra observed low frequency noise is 1/f noise of the OPA140 and from thermal fluctuations - like from the 0.01 to 0.1 Hz range amplified by a factor of some 3.3.The forcing cap would not see much effect from DA, but the X7R cap may also show some leakage, and other additional noise. Depending on the frequency used for the feedback, the forcing cap could be a little smaller. The integrator waveform still looks piecewise linear, thus not much effect from the capacitor. A smaller capacitor could probably also work, possibly better. I would consider at least a polyester film. If the final value is known and not too large (e.g. 10 nF) maybe an C0G MLCC.Overall the noise is reasonably low for a start. It is still quite a bit more than the limiting contributions from the resistors and OPs in the integrator. So there seem to be some other significant noise sources, like mains hum, the reference amplification to +-10 V, clock jitter, low frequency noise of the comparators or others. One can kind of exclude resistor excess noise (not much 1/f noise) and the higher frequency noise of the comparators (noise with 5 SPS is not much higher).The new 3458 use TL3016 comparators (+-5 V supply) and additional clamping of the signal with a JFET current limit and diodes.So quite some parts, but not very expensive.

author: macaba
author_rank: Regular Contributor
timestamp: June 23, 2020, 09:02:24 am
content: 50SPS plot:It would appear that the noise is mostly contained within 2LSB (~40uV) at this sample rate. Those occasional spikes above the main body of pulses - I wonder if that's clock jitter. I may be able to artificially increase this by using the uC PLL to generate the 25MHz frequency (multiply it up, and divide it back down again!) instead of using the crystal directly and having the PLL disabled as currently configured. EDIT: This worked *too* well. Huge noise added (760uVpp).The next thing on the todo list is to kludge in another DG419 to do AZ switching on the input and program this mode into the uC.

author: macaba
author_rank: Regular Contributor
timestamp: June 23, 2020, 09:25:11 am
content: It occurred to me that 0V isn't the whole story. Here is the 50SPS noise at Vmax.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 23, 2020, 11:40:14 am
content: Are the conversions using the same comparator reading for the stop of one conversion and the start of the next conversion ?In this case the averaging / filtering of consecutive readings would be exactly the same as a single longer conversion.So if would make no difference averaging 500x20ms or 50x200ms or another combination.So one has cases with 20 ms , 200 ms , 2 s and 10 seconds. Here it looks like the 20 ms case has extra quantization noise or higher frequency noise (e.g. from the comparator) and thus the noise higher than sqrt(10)*4 µV = 12.6 µV. The quantization noise could be a large part of the extra noise, especially as each conversion has quantization at the start and stop.The 10 second case already sees the 1/f noise. The 200 ms and 2 s cases seem to be about the cross over, though not clear if there is a region dominated from white noise in between.One can kind of simulate the AZ mode even without extra HW by looking at the difference of consecutive (or with one in between) conversions. Like the AZ mode this would suppress much of the very low frequency noise.

author: macaba
author_rank: Regular Contributor
timestamp: June 23, 2020, 03:59:46 pm
content: Quote from: Kleinstein on June 23, 2020, 11:40:14 amYep, so the 10 second filter is a sanity check to ensure results from test runs are comparable, itshouldbe the same.Quote from: Kleinstein on June 22, 2020, 06:58:23 pmGood point - that's an easy metric to look at for every decade change in SPS.Quote from: Kleinstein on June 22, 2020, 06:58:23 pmAgreed.Quote from: Kleinstein on June 22, 2020, 06:58:23 pmThe +/-10V reference (VRE102CA) has good tempco specs. The 0.1 - 10Hz noise over 30 captures looks like:I intend to create a board with 8 of these references summed together (through 1k resistors then >10uF capacitor ) into a zero-drift OA buffer so the reference noise can then be eliminated from the equation (aside from low temperature fluctuations).Quote from: Kleinstein on June 22, 2020, 06:58:23 pmInteresting. Would have to have a think about how to do this in my design. Potentially with 4 resistors as dividers with suitable specification so that drift between self-calibrations is minimal. The integrator waveform would be between -1V to 1V, and the forcing/reference input waveforms stay as -10V/+10V.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 23, 2020, 05:19:49 pm
content: The reference VRE102CA is a rather expensive one with high precision. The circuit here does not really need this. Chance are one get similar performance from an LM399 with external amplification. The ADC circuit does not need the -10 V to exactly opposite the +10 V. The relevant reference voltage is the difference between the positive and negative level. The symmetry has very little effect, mainly on the offset.The type of ADC shown is anyway not super low noise. It may be good linearity, if the modulation frequency is not too high and integration over long times (e.g. > 2 seconds), even though this may be higher noise.I don't think it would be a good idea to limit the integrator waveform to +-1 V. With the relatively large integrator cap the higher frequency noise can be important. Even just dividing down the signal would amplify the noise of the comparators. Changes are an LM311 with the full signal would be better than the TL3016 with 1/3 the signal.I don't think one would really need a super fast comparator. Even if there is some delay with a slower comparator, a constant delay would not really matter. Because the forcing waveform also effects the slope, the accuracy from the exact timing is not that high anyway. For good linearity it is thus important that the signal is stable and the integrator waveform settled and stable.I see one possible mistake in the circuit: the +- ref. for the forcing signal should be isolated from the main reference. Otherwise the switching of the forcing signal can effect the reference signal used for the main ADC.Ideally one would have extra, good speed (e.g. OP27, maybe even OPA209) buffers for the +-10 V reference going to the switches. The CMOS switches have quite some current spikes. The reference to the forcing waveform would ideally have separate buffers, though less critical.

author: macaba
author_rank: Regular Contributor
timestamp: June 25, 2020, 09:23:23 am
content: Quote from: Kleinstein on June 23, 2020, 05:19:49 pmTrue, I have 8 of them at no cost and want to add a '10V reference' card to my metrology eurorack. Yesterday was spent measuring the noise levels. Turns out that one of them has such good performance, it makes sense just to use the best (#6) for now:The quality of noise was quite different too - #3 has small magnitude popcorn noise, and #8 has a lot of higher magnitude popcorn noise (exceeding datasheet specification slightly). #7 has a lot of short impulse noise, the others are well behaved.Wondering about putting some together in parallel with different weightings of resistors corresponding to their measured noise level but not sure if it'll be effective.As a side experiment, I used the ADC as a current input ADC (by feeding the current to be measured into the summing node) at 5SPS. I used a 1000uF electrolytic from the batch that I measured for my LNA input capacitor and measured it's leakage current after 2 hours of settling at 7V (PP3 battery).First half is the leakage measurement, 2nd half is removing the cap from the input just to be sure I wasn't seeing ADC noise! Where is that noise coming from? (about 100uVpp, 36uVrms) I did a couple of basic calculations to try explaining it:A. sqrt(kB*T/C) = 2nVrmsB. sqrt(4*kB*T*R*(F2-F1)) where R: 7V/5nA & F2-F1: 2.5Hz =7.6uVrmsI'm probably missing something obvious. Why don't I see this noise in my LNA?

author: Kleinstein
author_rank: Super Contributor
timestamp: June 25, 2020, 10:17:10 am
content: Having the ADC input open (as opposed to tied to ground) can reduce the ADC noise a little. With the relatively large 100 K resistor to the input this would not be that much though.It is hard to see from the picture, but it slightly looks like the noise without the capacitor looks smaller than the noise if the ADC in normal voltage mode.The noise level currently seen for the is still quite a bit higher than the simple noise sources I have in my calculations.So there seem to be additional noise source like EMI, supply ripply, mains hum, ... . Some of these may change with the capacitor.With the cap there may be an effect of ripple on the voltage.For the leakage current through the capacitor one may have to assume shot noise and not leakage through just a low noise resistor. The leakage "resistor" can also show some excess noise - I would not expect the leakage path to be a good resistor, more like a really poor one.The noise level of the capacitor may depend on the time it was charges before. Mechanical stress could requite a new settling cycle.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 25, 2020, 07:07:22 pm
content: I had another look at the known noise sources. It looks like the measured noise is still a bit higher than the expected (at least the noise sources I have on my list). This type of ADC would never be very low noise, but could probably be able to perform still a bit betters (e.g. 1/2 the noise).One quite significant noise source could be noise in the 2.4 kHz band of the reference. The modulation / forcing waveform would do a +-1 demodulation from this frequency down to near zero. Because of the 50 K / 100 K resistors for reference and input this noise would be amplified 2 times. So if the reference would be at some 100 nV/sqrt(Hz) (about the level of the LM399), this would contribute some 200 nV/sqrt(Hz) for an input voltage near zero. To avoid this noise the reference buffers may want to include some low pass filtering.One more relatively simple looking, but actually not so simple question: how is the final result calculated from the measured times ?With the forcing signal it may not be so easy to decide which reference level is active at the end. I think one should include the forcing signal as part of the reference.On average the error may be zero, but a wrong scaling could increase the noise.

author: macaba
author_rank: Regular Contributor
timestamp: June 26, 2020, 08:58:00 am
content: Quote from: Kleinstein on June 25, 2020, 07:07:22 pmI'll add this to the list.Quote from: Kleinstein on June 25, 2020, 07:07:22 pmProbably incorrectly, I'm learning as I go along here.- Integrate for N cycles (where a cycle is 1/2400), and N usually selected for 50hz rejection (N=480 for 5SPS, N=4800 for 0.5SPS).- At the end of integration time, there are 2 counter values:Total time (which is usually around N * 5208, where 5208 represents 25000000/2400. I've tried both A. using the counted total time & A. calculating 5208 * N. No large difference).High time (the time spent in the 3.3V level of the 'PWM' waveform).- Compute the ratio: High time/Total time (approx. 0.5 for a 0V input, 0.25 for a -10V input, 0.75 for a +10V input)- Compute the calibrated reading: readingCal = (ratio * scale) + offset [where scale & offset were previously determined during calibration]Yesterday I added the input mux and started coding the AZ functionality. I first wanted to see if I *could* see a correlation so I set up a state machine that would switch between 0V and 'Input' (really just the 10V reference), allowing 8 cycles (3.33ms) of settling time between integration times. Running at 0.5SPS. I then sent the 'input' and 0V values to my computer, manually subtracted offsets to align the 2 waveforms to each other, and summed them.Blue is 10V waveform (subtracted with constant offset down to 0 region), Green is 0V waveform (added a small constant 300uV to get it up in the 0 region), Black is the summed waveform of the other two.[All the adding and subtracting of offsets is to get all the traces to display in the same area; around the black trace. I might just add 2 more Y axis in the next attempt.]EDIT: Forgot to mention traces are after filtering.It certainly looks encouraging.Today I will probe around the board to see if I can see any obvious sources of noise.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 26, 2020, 09:48:20 am
content: The correlation for the AZ like measurements looks encouraging. The difference still looks correlated to the single readings. For the AZ case one gets a sequence of zero and signal readings and there is still the question of which zero reading to use: zero before signal or the zero after the signal or maybe the average of before and after. The last choice would reduce the noise a little and compensate for a rate effect.The noise now is closer to the final limits, now more like 1.5 µv_peak to peak , maybe some 0.3 µV_rms.From the noise sources I know I would expect some 120-200 nV_RMS (quite a bit depending on the reference).I don't think one would see noise source by probing around with the scope. The way to pinpoint noise is more like measure the noise for some variations and look at the differences. E.g. try a larger capacitor (not that easy here as this would also need different comparator levels) as this would increase the effect of higher frequency noise. So the difference would be attributed to higher frequency noise (from the comparator and integrator). The comparison of different speeds is also such a case.For the way to calculate the result, there likely is some additional effect of the change in total time. During this time the forcing signal has a defined setting and would add to reference. So chances are the change is total time will be correlated with the result, not only from the total integration time, but also from the extra current. This type of error would mainly effect the faster readings. A can imagine it could be an important part for the 50 SPS noise.

author: macaba
author_rank: Regular Contributor
timestamp: June 26, 2020, 12:56:12 pm
content: Quote from: Kleinstein on June 26, 2020, 09:48:20 amAs a quick check for large issues... I did find something interesting.Top trace is the 10V reference, probed near the DG419 switches.Bottom trace is the forcing waveform (mainly to use as a trigger).The larger spikes are from the forcing waveform, the smaller spikes are from the reference switching waveform (which uses the 20k resistor current sharing scheme).Zooming in...Difficult for me to know what effect this is going to have, it might be worth some time to try reducing/eliminating these?

author: macaba
author_rank: Regular Contributor
timestamp: June 26, 2020, 01:04:26 pm
content: As another point of interest - the smaller spike on the +10 reference from the reference waveform switching. Persistence is infinite and spike position is variable because of the 25MHz synchronous switching jitter.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 26, 2020, 01:31:38 pm
content: It is not surprising to find some spikes on the reference from the DG419 switching. It may be a little surprising the spikes are so short - so really fast settling of the reference. I had expected slower settling on the reference.As the settling is so fast, I would not expect much effect on the ADC. The forcing waveform and reference switching should be well separated (e.g. at least 2 µs or so). So the main effect would be a little bit of offset. So if it is not getting worse, I would no worry so much about it.

author: macaba
author_rank: Regular Contributor
timestamp: June 27, 2020, 12:49:08 pm
content: Ignoring the small reference spikes for now, agreed they probably don't introduce enough error to be concerned.I did some longer term AZ tests (1SPS over 20 minutes, with 30 second smoothing filter) at 0V input, and -10V input.At 0V input (therefore the same as the 'zero' input) the correlation is good (might be scope to improve it over the basic 'zero before input' algorithm).At -10V input, there is correlation but not as good. Almost as if there is long term popcorn noise (-500 to -300 seconds).I'm now considering replacing the first amplifier in the integrator (U2) with an AZ amp; LTC2057 (input current noise specification of LTC2057 is much better than something like ADA4523-1). Eventually when there is a JFET front end amplifier with selectable gain, the AZ switch can go before that to remove the JFET noise, still with AZ amp in the integrator so any extra noise after the input amp is added can be directly attributed to the input amp.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 27, 2020, 03:11:12 pm
content: In the Az mode the noise of the integrator is relevant only down to the sampling rate, so in this case 1 Hz. Lower frequency noise would be suppressed by the chopping action. This works for the input amplifier and integrator (though with the noise gain of some 3-3.5 for the integrator in the current circuit).With 1 SPS or faster I don't see an advantage for the LTC2057 over the OPA140. One could consider running the AZ cycle even a little faster (e.g. 2SPS). It is a compromise between the low frequency noise of the OP and the higher frequency noise and quantization noise on the other side.An AZ OP is kind of needed in the very slow running ADC like in the Solartron 7071 with up to 50 seconds for a single conversion. Than one also needs an AZ type amplifier at the input. Besides the input amplifier also the reference part generating the -10 V ref. would also enter and can add 1/f noise.The zero signal before AZ looks a little like there is some periodic ( some 100 seconds) part. This may be something like a beat frequency with mains hum.The residual signal also looks a little like correlated with the deviation of the zero signal, so it may be worth considering the zero before and after.When reading a non zero voltage, there can be additional noise, e.g. excess noise from the resistors.In a real world application, reading an external signal there would be additional reference noise.The curve sows some drift, and not only noise. Without the drift part the noise is about comparable to the reference noise, even though the reference is not the main source.A possible source if the drift could be the switch used for the AZ switching, if directly at the resistor. The R_on has a rather high TC and could lead to gain drift. It does not take much to get some 0.5 ppm of change in the gain.So it absolutely makes sense to have the switching before the input amplifier(e.g. like the HP meters).

author: macaba
author_rank: Regular Contributor
timestamp: June 27, 2020, 04:02:26 pm
content: Quote from: Kleinstein on June 27, 2020, 03:11:12 pmAfter reading your reasoning, one agrees. I'll keep OPA140 for now.Quote from: Kleinstein on June 27, 2020, 03:11:12 pmA very interesting point. At this precise moment, the mains frequency is 50.049 Hz.The forcing waveform is running at (assuming a perfect crystal) 2400.1536 Hz, whereas, to compensate for 50.049 Hz, it needs to be 2402.3520 Hz.At the moment it's too difficult to adjust this - mains frequency doesn't remind stable for long and I have no digitally controllable crystal capacitor loading register on this uC (I've seen other uC where you can clock steer the crystal).PLL, as per Solartron, could be a future experiment.Another interesting experiment: I changed the AZ settling period (the time after switching) from 0 to 6 cycles (where a cycle is 0.416ms).Overall view:Zoomed in to the interesting region:So that resolves the question of what settling time to use; about 5 cycles.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 27, 2020, 06:13:11 pm
content: For the settling in the AZ cycle it could be interesting to look at the resulting actual integration time. Chances are, that after switching it would take some time for the feedback and integrator to settle. So the starting time for the conversion after switching can be off quite a bit. The forcing signal acts a little like an extra reference signal and if this is not included correctly, the settling in the start position can lead to an error in the voltage.The other effect that can change with the waiting time is the faster part of the DA. However I would not expect so much effect from there. Another possible point could be some thermal effect, though I would not expect much.For the mains hum it should need quite some amplitude to get a visible effect. Even if the frequency is off a little, there is still some suppression of mains hum. The PLL for the mains frequency is also quite tricky. It is not so easy to get a good mains synchronous clock. The variations of the mains frequency are a little high to work with an VCXO and would more like need a high quality factor LC based VCO. A time constant in the 10s to 100s of seconds is in the range that is tricky to do analog. So the PLL would be a topic of it's own.With the more continuous running ADC one could do some numeric fine adjustment of the integration time, by looking at 2 overlapping conversion, one a little shorter than the nominal multiple of 20 ms and one a little longer. So one could look at 2 stop timings, 1 period of the forcing signal apart. Instead of adjusting the time one could use a weighted average of the 2 cases to approximate a fine adjustable integration time. This way one should get very good suppression of the mains frequency. Only higher harmonics of the mains frequency may be tricky. The exact main frequency could be measured independently.As a first or additional step one could synchronize the start of the conversions with the mains phase. However this would add some extra delay (e.g. around 20ms -> so plenty of time for the settling).

author: macaba
author_rank: Regular Contributor
timestamp: June 29, 2020, 10:52:46 am
content: This latest round of testing took much longer as it involved thermal tests.1st - approximately how long does it take for the ADC to warm up and settle to a 'flat' line with 10V input?- ADC is in open air in a room that isn't temperature regulated so results are to give an approximate idea for how long to wait before conducting other tests that rely on a settled ADC rather than being an absolute benchmark.- It took 7 seconds for forcing waveform to settle to the beginning of the slow thermal curve.- It took 90 minutes for components to reach thermal equilibrium.- Over the 90 minute period, the non-AZ input voltage drops 132uV, the AZ-calculated voltage drops 273uV.Subsequent tests after this had a 90 minute settling period before commencing.2nd - the input mux is non-buffered, what happens if the mux IC is touched with a fingertip on top of the package for 30 seconds?(Grey region is the 30 second fingertip touch)3rd - adding a buffer (OPA140) after the mux and before the 100k resistor (as per U1 in post #33). What happens if the mux IC is touched with a fingertip on top of the package for 30 seconds?(Grey region is the 30 second fingertip touch)That was a worthwhile improvement. Note that there is approximately a 2.1mV difference in the resulting AZ value after the buffer was added, I would guess the 25-35 ohm mux resistance had an effect.

author: Kleinstein
author_rank: Super Contributor
timestamp: June 29, 2020, 02:46:11 pm
content: The switch resistance can have some effect, including a thermal effect due to the rather large temperature-dependence (e.g. some 6000 ppm/K). So even with the switch some 3000 times smaller in resistance, this can still give some -2 ppm/K for the scale factor. So only a little more than 1 K temperature rise needed to cause the 25 µV drop in the test with the finger.Beside the thermal effect for the input path, there is however also some thermal effect for the references, here even with only 50 K resistor. So this can also become a weak point.

author: macaba
author_rank: Regular Contributor
timestamp: July 03, 2020, 11:17:55 am
content: A continuous self-cal scheme is now implemented in the firmware where the input mux cycles in 4 phases: input/0V/10V/-10V so now the readings have the correct value when compared to my U1252B (but with 2 extra digits!).The noise over various integration times look as expected:There doesn't seem to be any more easy upgrades to reduce noise, the integration times to achieve a certain level of noise were always going to be long.Onwards to the next interesting design; a multi-slope converter with relatively simple design (I don't think I'm interested in using a residual ADC at this time). The aim is still not to get the fastest ADC, just the easiest to construct well.I'm considering something like this with a single NOMCA on the input:Followed by slope amplifier and comparator, as usual. What is not yet clear to me is how a multi-up-slope converter achieves mains rejection (whereas it's quite obvious in a dual slope - the ramp up is N PLC in duration).

author: jaromir
author_rank: Unknown
timestamp: July 03, 2020, 12:23:31 pm
content: Quote from: macaba on July 03, 2020, 11:17:55 amThe multislope runup has to be N PLC in legth. Multislope runup is basically the same thing as dual slope runup, with occasional controlled kickdown of integrator charge, in order to avoid integrator output saturation.Also, consider moving switches to opposite side of resistors; changing common mode voltage on switch element changes its on resistance, possibly causing INL, especially on input switch (SW2 in your schematics). Keeping switches at ground potential greatly decreases this problem.In configuration without measuring residual voltage, it's probably vital to have way to discharge integrator to known state before every runup (by adding another switch).You may find some inspiration in my voltmeter projects documented here on forum.

author: MegaVolt
author_rank: Frequent Contributor
timestamp: July 03, 2020, 12:40:13 pm
content: Quote from: jaromir on July 03, 2020, 12:23:31 pmAny link?

author: Kleinstein
author_rank: Super Contributor
timestamp: July 03, 2020, 12:45:50 pm
content: Using a cycle with signal , 0, +10 and -10 V spends quite some time for the reference. One should get away spending less time there like doing signal, 0 , 10 V , signal, 0, ... or signal , 0, signal , 10 , ...With good, stable resistors, one could even skip the reference reading in ever cycle and do this only occasionally during some extra ACAL run, e.g. every hour or days. With not so good resistors reading the reference can help. AFAIK some meter do the ref reading in their AZ cycle (e.g. HP3455, Keithley 19x, K2001?), while others don't (e.g. HP3456, 3457, 3458, 34401). The resistors seem to acceptable - at least no very large excess noise visible, so a scale factor calibration only once in a while may be OK.For the new proposed configuration the matching of R1 to R4+R5,R8+R9 is important for the scale factor. So one would normally try to use resistors from the same array. So it is kind of odd needing 9 resistors.Switching the references only on / off at the reference side can be tricky, as there is capacitance at the switch side and it takes some time for the residual charge from there flow through the resistor. This can limit the speed for short phases to several µs. The more usual way would be to switch between +ref and +ref with the same resistor.For a simple multi-slope ADC one only needs 1 slow slope. If high speed is not important this can be a rather small ref. current: e.g. the Keithley2000 uses 1/128 the full reference. The fine slope(s) is far less critical and can use lower grade resistors.A point likely still missing is the integrator reset, though not absolutely needed if the rundown is very exact and high resolution.For low noise it helps if the resistors for the reference current are not much smaller than for the input current. Smaller resistors for the reference would increase the noise from the resistors and the OP. So it would be better to use a 14 V reference and 50 K instead of 7 V and 25 K.Using same value resistors for the input and main references helps matching the relative switch resistance. This is especially true with HC4053 switches at the integrator input, where same resistor values are needed for the relative switch resistance matching.There are pros and cons of switching at the reference side versus switching at the integrator input.Switching at the reference side is much less sensitive the charge injection and switch leakage (especially if switching between two voltage levels). As a downside one is limited in the voltage and matching of the switch resistance is more difficult, as this is at different voltage levels.

author: jaromir
author_rank: Unknown
timestamp: July 03, 2020, 01:45:36 pm
content: Quote from: MegaVolt on July 03, 2020, 12:40:13 pmhttps://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/https://www.eevblog.com/forum/metrology/diy-6-digit-handheld-volohmmeter/

author: macaba
author_rank: Regular Contributor
timestamp: July 03, 2020, 10:16:39 pm
content: Hmm, the multi-slope converter seems like a rabbit hole that I'm not sure I want to go down at this point...Tangentially related: anyone know if the G3VM-21MT has charge injection? I know the price is a bitter pill to swallow but the other specifications seem good.I'm wondering if I can adapt my current ADC to some new approach to see if I can reduce the integration time required on the same/similar principle.Maybe a silly idea but see attached image.Theory of operation:- Do 'fast' (1 PLC) conversion as normal with U12 and U14 set to 0V. EDIT: I now realise I probably want to isolate completely... maybe reed relays on the U13/U16 outputs instead and remove U12/U14.- In this example, fast conversion gives a result somewhere within +9V to +10V.- Set the PWM DAC output to -9.5V and enable U12 and U14 to pass through voltages.- ADC will now read input voltages from +9V to +10V as 0-100%, so do 10-1000 PLC conversion scaled to 0V - 1V and add 9V to the reading.Apologies for the R100-R104 mess, it was the quickest way I could think of to get an equivalent of 5k (when R2 included).

author: Kleinstein
author_rank: Super Contributor
timestamp: July 04, 2020, 07:55:43 am
content: The Photo-fet switches will also have some kind of charge injection, though obviously to to the gate, but between both sides of the switch. So when having a circuit like a small capacitor on both sides and than turn off the switch, there can be a small charge transfer and thus differential voltage. The charge injection can be relatively small, as the symmetry can be quite good.I am a little suspicious about the leakage specs: it looks like they kind of cheat and measure leakage at zero voltage over the switch with the extra guard and 2 step switching. This may work in some applications, but not always. Such a photomos switch (especially a higher voltage version) may help for the input section of a voltmeter, but I see limited use in the ADC itself.The crazy idea circuit is a little like a differential voltmeter. So the reaction to steps would be slow. This could be a problem with offset / LF noise compensation with an AZ mode. So one would likely need to use an AZ OP at the integrator and input amplifier and do the offset compensation only very rarely, a little like the Solartron meters.With the low 5 K resistors one would have effectively a small input range to the ADC and the rest is done through the PWM DAC. The ADC is not working that good with the small range. There may be a more effective way to implement this, than directly at the ADC input. The more obvious choice for a differential meter would be using (differential) amplification before the ADC and than an ADC chip, as the ADC itself would not need high resolution anymore.I see still some potential to improve on the initial mark /space type ADC with the forcing signal: One possible path could be using a 3 rd comparator at the output: the 2 original comparators only for the feedback part could be lower grade (e.g. LM311). The final resolution, start/stop could use a 3 rd comparator for zero crossing with some slope amplifier for lower noise and a defined bandwidth and possibly higher timing resolution than the others. The 3rd comparator result would not need synchronization to the stable external clock. One could use a little more (e.g. 4) than just 1 transition for the start and stop and this way reduce the noise at the cost of a little more switching time.This type of ADC would not be extremely low noise (competing with the 3458 or modern meters like DMM7510, 34465), but it could be relatively low effort and good linearity, if a larger error from DA can be avoided. I see no principle reason why the noise should not go down quite a bit over the current state. I would expect something like 1 µV RMS for some 2 SPS a realistic target.

author: macaba
author_rank: Regular Contributor
timestamp: July 04, 2020, 11:31:51 am
content: Quote from: Kleinstein on July 04, 2020, 07:55:43 amInteresting... I was curious to see if I could improve upon the DG switches I've got. I suspect discrete JFET would realistically be the ultimate answer, not something I've tried before so I'll have to read up on that.Quote from: Kleinstein on July 04, 2020, 07:55:43 amThat does sound sensible, I'll draw up a draft schematic of such a amplification scheme.Quote from: Kleinstein on July 04, 2020, 07:55:43 amThank you, that's a good idea. I intend to change the EL2018 ICs to LM311 for future-proofing (and characterise any change in noise) so that frees up a EL2018 for prototyping the 3rd comparator idea. Being able to feed that 3rd comparator signal directly into the uC 100MHz clock domain (after it's been through the sync registers), not having to expose that 100MHz clock on a pin, should have some advantage (in addition to what you suggest). I did not see any noise benefit when I changed the reference switching sync clock from 25MHz to 5MHz so I'm not focusing on that at the moment.Quote from: Kleinstein on July 04, 2020, 07:55:43 amFor differential idea, or after further improvements to the original principle?

author: macaba
author_rank: Regular Contributor
timestamp: July 04, 2020, 11:41:14 am
content: Simulating the 3rd comparator idea, it seems to reduce the mark-space dynamic range a little. Instead of 25-75% duty cycle (for -10 to +10), it's approx. 38% to 62%.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 04, 2020, 12:24:01 pm
content: The noise estimate would be for the mark space ADC.Using a 3rd comparator should not effect the possible duty cycle range, as the reference control would be the same. There could however be a some complication if the forcing signal switching moves so far as switching close to the zero-crossing. Getting to close there could be a problem for the linearity.The useful duty cycle (for the reference control) range should depend on the ratio of the resistors for the reference and forcing signal, the integration cap (in relation to the forcing frequency) and the capacitor at the forcing signal (well possible that it just has to be large enough and no real optimization here).If a slope amplifier is used for the 3rd comparator, the actual comparator would be less critical and even the µC internal comparator can be good enough. So no real need for the obsolete EL2018.With the switches at the reference side (voltage switching) the charge injection is not that important. The relatively slow modulation also makes charge injection less critical. The more important factors are the switch resistance (could be compensated with the extra path for the main current - with 50 K for the reference and 20 K for the current it should be some +-14 V for the auxiliary references for the current). The photomos switches are really slow and thus of limited use for the ADC. JFET switches are not that easy either. Nice point is that the on resistance does not depend on the voltage level. However it takes quite some effort for the gate signal to get a constant shift with a fixed delay.The CMOS switch ICs are really convenient with the gate drivers inside the IC and often good matching and already some compensation of the charge injection.

author: macaba
author_rank: Regular Contributor
timestamp: July 04, 2020, 02:09:34 pm
content: See simulation attached for +10V input.Yellow is integrator output, red is forcing waveform, blue is the mark-space signal that is currently being read by uC, green is the proposed new signal from the zero crossing comparator (connected to the same point as the other 2 comparators; the output of the integrator).

author: Kleinstein
author_rank: Super Contributor
timestamp: July 04, 2020, 05:08:36 pm
content: Ok, the 38/62 % ratio is for the comparator signal, not the reference.So the reduce ratio is not limiting the input voltage range, but the timing signal, making the comparator for zero crossing possibly a little less sensitive, as the slope is steeper. This would reduce the resolution a little, but not that much. However comparing to the transition following the zero crossing it would be the same slope and thus the same charge resolution. Anyway there are 2 slopes, and depending on the input signal one can be better than the other.One may not actually need the 3 rd comparator. It has pros and cons : on the downside there is mainly the possible trouble when switching of the forcing signal is just before the zero crossing. This would causing a troublesome range. Not sure at which voltage this happens and if it could be avoided by simply using the other slope.Reasons in favor of a 3rd comparator would be that it is a little easier to have a slope amplifier near zero than relative to a 10 V trigger point. Also the noise (mainly the higher frequency part) of the trigger level would enter when using the trigger at some 10 V.So it is not so clear if it is really worth using a 3rd comparator, even if the effort is minimal when the µC internal comparator is used behind a slope amplifier. Filtering the 10 V trigger level with an inverting slope amplifier is also possible. With 2 comparators one could also use both to control the reference and additionally read the 1st flip-flop before the external synchronization with higher time resolution.As far as I know the current circuit I see 4 weak points:The compensation of the switch resistance should use +-14 V and 20 K, with the +-14 V derived from the reference and not just the supply.When calculating the result, for the initial and final timing there is the forcing and reference signal active and this should be included. So the scale factor for those times would be higher.The initial and final timing use the synchronized signal and thus give away some possible resolution.The length for the individual readings is a compromise between 1/f noise and quantization noise - so more time resolution could be used for shorter conversions at a piece and less 1/f noise.

author: macaba
author_rank: Regular Contributor
timestamp: July 04, 2020, 08:00:47 pm
content: Quote from: Kleinstein on July 04, 2020, 05:08:36 pmAlready in there, 14V from stable LDOs.Quote from: Kleinstein on July 04, 2020, 05:08:36 pmPlease could you explain this? I think you referred to this in post #54, I am curious to hear more.

author: Kleinstein
author_rank: Super Contributor
timestamp: July 04, 2020, 08:45:17 pm
content: In the time before the comparator switching the input current to the integrator is from the input, one reference and the forcing signal. So for calculating the charge one has to include the current from the forcing signal. This is only needed for the small part of the time when the total time is different from a full period of the forcing signal. For full periods of the forcing signal the overall charge from the forcing signal is zero, but for the small different there is some extra current.For the size of the extra current it helps that the capacitor in the forcing signal in rather large, so that the voltage lost in very small.So in the simulated curve just shown there is the reference current + the forcing current. So approximately 4/3 of the normal reference current. When the waveform is well settled the difference in the total time should be small. So the 4/3 approximation should be usually good enough.

author: macaba
author_rank: Regular Contributor
timestamp: December 31, 2020, 06:04:44 pm
content: As a point of interest; I recently gained the ability to measure the linearity of this design (implemented on a protoboard so plenty of sources of error).See attached... better than I expected!I think this will be slightly improved with a PCB implementation and a better integrator capacitor (perhaps C2012C0G1H332J060AA).

author: Kleinstein
author_rank: Super Contributor
timestamp: December 31, 2020, 07:18:12 pm
content: For a proto-board setup, the INL curve looks really good, but also a little odd in places. At least the curve looks quite repeatable, so the noise must be at an acceptable level and the stability also looks good, with not much drift.I don't recall which circuit is actually used. The mark space type ADC with continuous PWM feedback is usually not very sensitive to DA of the capacitor. This is because the average capacitor voltage stays close to zero or at least constant. The shape of the curve looks quite complicated. This makes simple effects like self heating of the input resistor (usually give an U³ part) and non-linear switch resistance (more like U²) as the main error mechanism unlikely. It is also no so much things getting worse close to the extremes, which is one kind of problem possible with the PWM type feedback.There are a few points that may get better with a PCB, but it is not so clear. My initial result from the PCB was even worse than from the breadboard + µC board setup.The prototypes tend to be good with a star ground. With a PCB one tends to go for short cuts and has the dilemma of ground plane versus star ground. There are usually more caps on a PCB, though this is not always good.One way to search for INL mechanisms is to measure with slightly changed circuits / program. Some of this may be easier with the protoboard than with a PCB.

author: macaba
author_rank: Regular Contributor
timestamp: January 04, 2021, 04:46:37 pm
content: Another point of interest...I've been trying various changes to get the linearity curve to do something interesting.Things like:- Switching between C0G and PP integrator cap- Switching between 1.6nF and 3.3nF integrator cap (with 2400Hz and 1200Hz forcing waveforms respectively)- Changing the reference switching current sharing resistor value by up to 10%- Switching between LM311 and EL2018CN comparators- Switching between 10nF and 100nF for forcing waveform coupling capacitorVarious combinations of those gave a very mild improvement (3.3nF C0G with EL2018CN in particular)I then did a larger change; a 15nF Russian PTFE integration capacitor (order of magnitude larger than before) with ~280Hz forcing waveform.Attached is the chart. All the background traces are my various experiments, the black trace is the 15nF PTFE capacitor along with the purple trace which is the polynomial best fit subtracted from the black trace.What I'm tentatively concluding, for now, is that this is a balance between the integrator/comparators not being fast enough (or low noise enough) at the high forcing frequency, vs. the dielectric absorption becoming the bigger factor at lower speeds due to larger capacitor.I probably want to be somewhere in the middle (600Hz?), with a decent C0G cap, and a small polynomial firmware correction (I don't want a massive correction as this could be temperature dependent... to be confirmed).

author: Kleinstein
author_rank: Super Contributor
timestamp: January 04, 2021, 06:20:24 pm
content: The forcing frequency is a balance:A faster frequency allows a smaller capacitor and this may makes the noise of the comparator and higher frequency noise of the integrator less importance. However there are more switching related errors and this may need a faster OP at the integrator. Clock jitter also gets more important.l, the speed of the comparator may become an issue. however compared to other ADCs the capacitors are still relatively large.It is kind of a balance between different errors - some get better ad some get worse.There should be a best frequency - but no idea where is lies - the possible range can be quite large - from a few 100 Hz to maybe some 10 kHz. Especially the switching related errors can be complicated - like supply spikes and capacitive coupling and clock jitter.I would expect a tendency that a higher forcing frequency will result in slightly lower noise, but higher INL (except for the DA part).With a smaller cap and high forcing frequency it may become more attractive to look at more than just the first and final slope. The slopes more at the inside would also give a result for a slightly shorter integration times that can be useful to reduce the noise. So one could average over a few points for less noise with relatively little extra time to get an average the same integration time. looking at 4 slopes each may give a near 2 fold reduction in the noise for the final decision part - the low frequency noise of the integrator is little effected.Looking at slopes of both directions may help with the INL as the errors may be different there and average out to some part.The best size of the capacitor for the forcing waveform depends on the frequency. Having the right size can help - for a test I would look at jumps in the input voltage and see how fast the feedback pattern stabilizes after the jump. This should be a much faster test than looking at the INL curve and should still show which value should be suitable. Fast settling may be needed to measure fast after switching the input. Chances are also that fast settling would also be good for the INL and noise.Chances are the cap for the forcing waveform and integration would scale in parallel and one could than adjust the frequency accordingly. It should be a 3 dimensional parameter space (2 caps and the frequency) - so it is more than just the frequency to look at.For this type of ADC it is not so easy to calculate how DA effects the linearity - on average the voltage is low, so DA should not have such a large effect despite the relatively low frequency. So maybe do a test with a known poor cap, like MKS. It is much easier to see the error there - a good C0G maybe something like 50 times lower DA.

author: Terry Bites
author_rank: Super Contributor
timestamp: January 16, 2021, 06:54:57 pm
content: IVC102 from TI a ready made integrator.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 17, 2021, 05:25:03 pm
content: The IVC102 is a integrator chips for very low currents. It is not suitebale for a high resolution ADC, but more like good for a low current input - so if you want to measure currents in the pA range.I would not even consider the amplifier part special - the good parts is more the integrated switch.A high resolution ADC is using a current more in the 10-300 µA range to get lowest noise.

author: macaba
author_rank: Regular Contributor
timestamp: January 25, 2021, 09:56:47 am
content: Quick update. New INL plot attached.- I experimented with integrator and forcing capacitor values/types.- I increased the post-mux-switch settling time. I would say this represents the majority of the improvement.Interesting correlation around 0V.

author: Kleinstein
author_rank: Super Contributor
timestamp: January 25, 2021, 10:26:36 am
content: The curves looks quite good. A reason for the scattering can be noise from the references. So less noise near zero is kind of the expected picture. If the reference for the DAC and ADC are not very good (e.g LM399 or similar) it may just need several runs and averaging.There seems to be common curve, like a small hook up at -9 V and the bend at around zero.The relatively slow modulation and thus still relatively slow settling for the integrator waveform may require a little more time after mux switching. For optimizing the forcing capacitor and maybe series resistor, it may still be good to do this with a relatively short waiting time (still at least 1 period of the forcing signal). The final step would than be a little longer waiting.One may be able to look at the first view comparator signals after mux switching and thus get data for different waiting times in parallel. Especially with relatively slow forcing frequency there could be enough time. One than would also have data for the settling phase alone that would make the settling effect more visible.In the long run one could use a kind of averaging over a few (like 2-4) start times and this way reduce the error and also the noise a little. Similar averaging may work for the stop part for the noise.

author: macaba
author_rank: Regular Contributor
timestamp: January 25, 2021, 11:04:44 am
content: I also suspect reference noise - a better reference is on my todo list.The curve (shown by the dotted line) I suspect is due to the stimulus DAC - the shape and magnitude matches my prior observations and expectations. At some point in the distant future, the DAC will be sent out for 3458A or fluke calibrator verification but first I want to subject it to a temperature chamber to ensure the linearity is stable between 10 - 40 degC (with remote voltage reference outside chamber).As a point of interest, I attach a picture of my DAC prototype.It's a 6-phase PWM DAC with counter clock of 6GHz, using switch resistance compensation (with the parallel switch arrangement sourcing the majority of current, similar to what the ADC design in this thread uses).v2 will likely be 12-phase PWM DAC (switch charge injection doesn't seem to be as big a problem as I anticipated) which allows me to adjust resistor values to further reduce the effect of switch resistance mismatch. I've also got ideas in mind for significantly reducing settling time (due to DA). The design in the picture takes about 80 seconds to settle to final value, I intend to get this down to 500ms.(I don't think the odds are good that I'll be able to achieve this but I'll make the attempt anyway.)

author: Kleinstein
author_rank: Super Contributor
timestamp: January 25, 2021, 12:06:32 pm
content: If DA is a problem with the DAC, I would also keep an eye on the DA in the board material. The parasitic capacitance of the board is still relatively low, but the DA of the board material can be some 100 x higher than the DA in PP capacitors. Relatively thin traces and guard traces can reduce the parasitic capacitance quite a bit.Multiple phases sounds interesting, but I would be afraid of interactions: if the switching of one phase is in near coincidence with another phase (other direction) there can be coupling via the reference or ground back to the µC.Another option could be using some SD like modulation. So have the PWM frequency higher (e.g. 2 kHz range), but with low level modultion (+-1-2 LSB). The full resolution is than on average, e.g. over some 5 ms. This can reduce the need for the filter, as most of amplitude would be at the higher frequency - a little like with multiple phase PWM, but with less HW.If the settling part is predictable, one could compensate by an intentional overshoot: so when going from 0 V to 2 V, one would first go to some 2.1 V for a short time and than to the final target of 2 V.

author: macaba
author_rank: Regular Contributor
timestamp: February 02, 2021, 10:26:25 am
content: Quote from: Kleinstein on January 25, 2021, 12:06:32 pmI was curious about this, so it was time for more experiments.In a 6-phase PWM DAC, there are 5 notable duty cycles where PWM edges of multiple channels will align: 16.6%, 33.3%, 50%, 66.6%, 83.33%, so I plotted these alongside a 60% duty cycle to provide a control basis for comparison.Chart is attached.I have complete control over the PWM rise/fall edge positions so I'll write an algorithm to detect if PWM edges overlap within a certain window and offset the edges slightly if so (at the downside of a tiny amount more output ripple).

author: Kleinstein
author_rank: Super Contributor
timestamp: February 02, 2021, 05:47:55 pm
content: The curves around the different critical points look remarkable similar. The control curve looks also good confirming good DNL for the ADC used for the measurement.Only 1 ppm error is less than I had expected, so the reference buffer seems to be working well.Shifting the switching times a little should not add that much extra ripple. The critical point are likely those where the rupple was near ideal to start with.

author: NWerner
author_rank: Contributor
timestamp: February 03, 2021, 09:45:01 am
content: Hello,could you elaborate how you did switch resistance compensation for your DACdesign?