Quartus II default pin assignments - Page 1
Forum section: electronics / general

author: gregallenwarner
author_rank: Regular Contributor
timestamp: December 16, 2014, 10:16:35 pm
content: I have a two-fold question regarding pin assignments in Quartus II.I'm writing up a quick little logic circuit that I need for a project, targeted for a MAX3000 CPLD (44-pin TQFP). The design uses up all 34 IO pins. I noticed when I let Quartus II do the pin assignments, there seemed to be absolutely no logic behind its placement decisions. Inputs were thoroughly mixed in with outputs, and vectors were nowhere near in order. It literally looked like someone had taken all my pin names, written them down on playing cards, and then shuffled the deck multitudes of time before assigning them in their resulting order. Why does it do this?Secondly, I attempted to place half of the pins myself, and let the software auto-place the other half. I grouped all my inputs on two sides of the chip, and made sure my vector bits were in order from least significant bit to greatest. When I went to synthesize my design, the fitter failed, saying that I had "assigned too many input pins". I only assigned the input pins that were a part of my design. What in the world does this mean?All I want to do is assign my pins in some sane, rational ordering!

author: marshallh
author_rank: Unknown
timestamp: December 17, 2014, 01:06:08 am
content: Always do the pin assignments in tandem with the pcb layout. I never let the fitter decide any pins, because it's constrained by my pcb breakout.Your input problem may be to a limit of several i/o along each bank. Check out the datasheet. I never ran into taht with EPM3064

author: Rigby
author_rank: Super Contributor
timestamp: December 17, 2014, 03:30:32 pm
content: Yeah, it'll put the pins closer to the logic in the chip itself when it can, so I always build the project, set or import pin assignments, then build again.Never let QII work out its own pin assignments unless you REALLY don't care or you're looking for an adventure. Like how sometimes I'll just go wherever the GPS tells me when I'm bored. I never get where I'm going because the damn GPS puts me on a road that hasn't existed or hasn't been maintained for 15 years.So, yeah, if you're looking to kill an afternoon let Quartus II assign pins for you.

author: Scrts
author_rank: Frequent Contributor
timestamp: December 17, 2014, 04:56:57 pm
content: The logic behind pin placement is just random. Since there are no pins assigned, it will do the routing in this way, that the design would take the smallest area and would work on the fastest clock rate that is possible for that design. In other words: it will decide the pins to have a balanced result area-wise and speed-wise.And the bottom line is: NEVER allow the software to assign the pins. Do that by yourself and set unused pins to be input with weak-pull-up.

author: Rasz
author_rank: Super Contributor
timestamp: December 18, 2014, 02:42:11 am
content: you simply ran out of silicon to route your IO from logic to assigned pins, shuffle stuff around

author: gregallenwarner
author_rank: Regular Contributor
timestamp: December 27, 2014, 04:50:54 pm
content: Thanks. I'm starting to get the hang of things.I did eventually find a pin configuration that synthesized successfully, however, I noticed that when I let the fitter do all the assignments for me, my logic consumed 47 macrocells, yet when I assigned the pins myself, with no change to the VHDL at all, all of a sudden it consumed 50 macrocells after building. Is this normal? Should I try going back and optimizing my design?

author: dgtl
author_rank: Regular Contributor
timestamp: December 27, 2014, 05:13:14 pm
content: You can't use the whole CPLD/FPGA. As you are starting to reach the limits(interconnects, registers, macrocells, dsp blocks, memory blocks etc), you'll start getting problems. Just one of the resources run out or is in the opposite end of the chip and the fitter fails or you'll get timing failures. Usually below 2/3 of capacity you are safe. It is normal that routing some signal to a specific pin takes some space in the internal fabric. It is quite similar to PCB design. Bringing out all the signals at the nearest pins after the logic has been placed, makes things much more easier. (as it is in pcb design - if the connector locations are not determined). The fitter has to layout the whole circuit and optimize all of the interconnects (both internal and external); the more connections there are, the more difficult the task is. If quartus needs to bring out some signals to specific pins, it may optimize some internal logic that way that is not best.You can also configure the fitter effort and other parameters in the q2 settings. Maybe it just needs to try a little harder and then everything starts to fit.The normal approach would be taking a larger part. If you must use that CPLD and can not use a larger part or reduce your design functionality, you may try to understand what signals should be grouped to nearby pins and then place them that way. You may try to let quartus place the pins a couple of times and then use one of those placements. Then try to swap the pins due to the pcb layout issues where it is needed. You'll probably get a working design, but it might get insanely difficult to make some changes in the future in case bugs need to be fixed or functionality needs to be changed.

author: Scrts
author_rank: Frequent Contributor
timestamp: January 15, 2015, 11:10:02 am
content: My last project had 99% usage of Cyclone III EP3C55 device. The fitter showed 103% usage before and ended up at 99% percent after optimization. The main clock there is 81MHz and there are no timing issues. The device runs Nios II and has 5 separate memory controllers plus Ethernet.You must do FPGA design rock-solid in case you're going for a full FPGA, but that's a good example that you can achieve this much utilization and meet all the timing requirements.

author: AndyC_772
author_rank: Super Contributor
timestamp: January 15, 2015, 02:31:50 pm
content: That's impressive. What constraints did you have to set? Did you have to specifically assign the location of any of the logic within the FPGA fabric, or did the Fitter manage that level of utilisation based on an SDC file alone?

author: Scrts
author_rank: Frequent Contributor
timestamp: January 16, 2015, 02:51:12 pm
content: Quote from: AndyC_772 on January 15, 2015, 02:31:50 pmQuartus did manage to do it itself. This would be a challenge for Xilinx, but not for Altera. I had to describe every IO pin in SDC file and some IO paths, but apart from that - nothing fancy. Be sure to run clocks on clock domains and use clock enables where needed.Anyway, the SDC constrains consisted of 5 separate files to maintain normal readability by blocks. E.g. top constrains, Ethernet constrains, memory controllers IO constrains, output constrains (especially output clocks) and misc stuff like jtags and false paths.