USB 3.0 Stackup wizdom for 4 layer board - Page 1
Forum section: electronics / projects

author: brentsinger
author_rank: Newbie
timestamp: January 07, 2016, 07:38:09 am
content: Hi.Has anyone got a stackup they like on FR4 for routing USB3? Pref one that has been tested and known to be ok. I can work it out myself, but would prefer to start with some sage advice and wizdom if you've got a good usb3 board.Boards being made cheap in China with 5/5mil rule but I try to stick to 7/7mil. I'm not keen on paying for impedance control and prefer to micromanage the stack and copper thickness/separation to do the impedance. Impedance control test strips are dodgy anyhow because they only tell you impedance AT the edge of the panel, not in the middle and platerns in China can be ***uncalibrated***.Thanks a ton.

author: marshallh
author_rank: Unknown
timestamp: January 07, 2016, 06:12:01 pm
content: Match lengths on the pairs and you're good to go. Also, you can swap the polarity of any pair if it makes routing easier - part of the phy spec is sensing RX POLARITY and adjusting accordingly. Usually outer prepregs on chinese 4layer are very thin, so it makes getting the track width easier. Just plug the numbers into Saturn PCB calc.In all honesty, it's not terribly critical, I have seen multiple usb3 hubs done on 2layer with pairs running across ground slots. USB3 phy layer has quite a large budget for channel loss, but no reason to spend that budget if you can avoid it.

author: brentsinger
author_rank: Newbie
timestamp: January 07, 2016, 10:55:04 pm
content: Thanks Marshall.So you are saying that I can connet RX- to RX+ @ the connector? That's OK with hubs, and device IC's? It sounds a little like one of those quirky things that the isn't 'always' supported. And does USB3 have a way of checking the link and then limiting data rate if there is an imperfect link? Or does it just NOT work if it doesn't have a good eye?USB3 is 100R differential right?Brent.

author: Monkeh
author_rank: Super Contributor
timestamp: January 07, 2016, 11:14:21 pm
content: Quote from: brentsinger on January 07, 2016, 10:55:04 pmIf it's not supported, it's not USB3. If it's not USB3, who cares, dispose of it.

author: marshallh
author_rank: Unknown
timestamp: January 07, 2016, 11:55:51 pm
content: Quote from: brentsinger on January 07, 2016, 10:55:04 pmRight, this behavior is clearly defined in the spec and mandatory for all PHYs. Technically, it's done at the MAC layer during link training.BER increases asymptotically with channel degradation and eventually the link fails. The link is designed to compensate for channel loss by deepmhasis, link training (equalization etc).

author: John_ITIC
author_rank: Frequent Contributor
timestamp: January 08, 2016, 12:42:43 am
content: Quote from: marshallh on January 07, 2016, 11:55:51 pmFor USB 3..0, it is actually 90 ohm, a left-over from USB 2.0. I don't know why they did not choose 100 ohm diff impedance in USB 3.0 since standard for all other forms of SERDES links and otherwise very similar to PCIe 2.0, which uses 100 ohm diff impedance:https://www.google.com/?gws_rd=ssl#q=USB+3.0+differential+impedanceOne trick for a 4-layer board is to route on the outer layers. If you transition from the top to the bottom then you will get no via stubs, which cause some reflections due to impedance discontinuities. Also, make sure to use a couple of GND vias next to the layer transition vias. Google for the background of this...Finally, it you have very short runs (an inch or two) in FR4 then the impedance matching of the actual 90 ohm traces are not too critical. This is because the USB connectors themselves cause a tremendous impedance mismatch and, in relation, the lesser trace impedance mismatch would cause less of an impact.

author: Monkeh
author_rank: Super Contributor
timestamp: January 08, 2016, 12:56:04 am
content: Quote from: John_ITIC on January 08, 2016, 12:42:43 amI was under the impression they made the (unpopular) choice to switch to 85 ohm with 2.0.

author: John_ITIC
author_rank: Frequent Contributor
timestamp: January 08, 2016, 01:56:00 am
content: Quote from: Monkeh on January 08, 2016, 12:56:04 amI believe you are correct:https://www.google.com/?gws_rd=ssl#q=pcie+2.0+differential+impedanceWhy was this unpopular?

author: Monkeh
author_rank: Super Contributor
timestamp: January 08, 2016, 02:02:24 am
content: Quote from: John_ITIC on January 08, 2016, 01:56:00 amBecause, as you pointed out, 100 ohms is more or less the standard everyone else uses.DVI/HDMI, DP, FPD-Link (typically), SATA/SAS, Ethernet (we'll gloss over the isolation requirements here), etc etc.We are very close to being able to use a common connector and cable to carry every relevant interface, varying impedance requirements simply get in the way.

author: TiN
author_rank: Super Contributor
timestamp: January 08, 2016, 03:34:07 am
content: Also make sure you have uniform solid GND reference plane under your USB3 routing on your 4 layer. Avoid plane splits and crosses under diff-pairs.

author: brentsinger
author_rank: Newbie
timestamp: January 11, 2016, 03:59:25 am
content: Thanks to all! I've got about 4" of trace, which I'll do outer layer with a mind to the stub issue and consistent gnd on next inner layer. I can go the whole way with only one layer change which is handy, there won't be slot antennas.I'll run with Saturn.Turns out I have access to a nice, recently calibrated Agilent TDR that was sitting in the corner of a lab holding some boxes. :-) I'll run that on the bare board to see just how close I got... as soon as I can find someone who knows how to work it.

author: wraper
author_rank: Unknown
timestamp: January 11, 2016, 04:48:09 am
content: Quote from: marshallh on January 07, 2016, 06:12:01 pmSeen that, 2.4 GHz mouses/keyboards and wifi stop working normally at the close distance when you try to read/write some data from from USB flash. Effectively this produces a good radio transmitter.