What am I doing wrong? - Page 1
Forum section: electronics / general

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 15, 2019, 10:27:01 pm
content: So I am looking at this garbage video and trying to do the same as him.@ 27:30, he starts dabbling in a input .txt file, wich is ridiculous path the way he writes it down its so painful and time consuming, I was under the assumption that I could just name this file only with .txt and have it in the same folder and I would be good? Seems like he has valid data in his sim and not me.Here is my setup, what am I missing?

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 16, 2019, 01:59:35 am
content: Is my pathing wrong?

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 16, 2019, 04:43:56 am
content: Ok never mind this garbage tutorial.But I have tried other things and cant make it work,Can anybody show me how in Quartus Prime free edition they implement $readmemb and their file pathing?

author: rstofer
author_rank: Super Contributor
timestamp: November 16, 2019, 03:16:24 pm
content: Tried Google?https://stackoverflow.com/questions/37135859/in-verilog-im-trying-to-use-readmemb-to-read-txt-file-but-it-only-loads-xxxxThis may help. You can specify the complete path to the file if you wish.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 16, 2019, 04:44:25 pm
content: QuoteMaybe relying on "garbage videos" (as you qualified it yourself) without bothering to look up for further information elsewhere?

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 16, 2019, 05:20:44 pm
content: Well I saw that page and still it didnt work and I tried some more and got mad then came here.I gave up on that garbage example. Getting the hang of it from other videos, I watched a 10 hours tutorial that took me a month to watch before dont worry, I just find these IDE's extremely complicated now that I'm actually about to code my app... Just look at all these options OMG.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 16, 2019, 05:41:21 pm
content: Many IDEs from FPGA vendors are clunky, but I think here it's more a matter of pure Verilog and not the IDE itself? Besides, knowing that Verilog source files are compiled with often third-party tools such as Synplify, which are pretty standard.I'd suggest, if you haven't already, looking up just the following keyword: "$readmemb"Example of what I've found (there are many others, so you should end up finding how to use it properly?)https://timetoexplore.net/blog/initialize-memory-in-verilog

author: asmi
author_rank: Super Contributor
timestamp: November 17, 2019, 01:16:08 am
content: Quote from: lawrence11 on November 16, 2019, 01:59:35 amI think what you're doing wrong is using arrogant and offensive language for no good reason, which doesn't make anybody want to help you out.So next time try using polite language - maybe this will make people more willing to spend their time trying to help you.

author: jhpadjustable
author_rank: Frequent Contributor
timestamp: November 17, 2019, 01:31:33 am
content: Quote from: asmi on November 17, 2019, 01:16:08 amAs would including the important parts in a readily machine-readable form, rather than a video and a screencapof everythingbutthe important part.

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 17, 2019, 02:19:14 am
content: Everything is the video's fault, this is his style of writing.I just wanted to follow a video and see the end result, wich was a failure.BTW, I saw somebody from a turotial write reg [31:0] xxx , isnt that integer?I think people now make garbage tutorials after first semester @ school they are the teachers now.

author: lawrence11
author_rank: Frequent Contributor
timestamp: November 18, 2019, 03:06:51 am
content: Mods, please delete this useless topic