Synchronization of Opal Kelly FPGA board with an external clock - Page 1
Forum section: electronics / general

author: Tueftler
author_rank: Contributor
timestamp: April 13, 2018, 06:39:06 am
content: Hi,I want to synchronize the FPGA board "Opal Kelly XEM7310" / "Opal Kelly XEM6310" with an external clock.An external clock coming from a sine wave generator has programable frequency f < 50 Mhz. Now, the Opal Kelly (with a master clock of 200 MHz) should read data from several ADCs with a transfer rate that is ideally a multiple of f.This transfer rate OR the master clock of the Opal Kelly needs to be synchronized with the clock from the sine wave generator, so that I can digitally reproduce the sine wave with the correct phase for a digital I/Q demodulation (lock-in amplification) of the data coming from the ADCs. For f = 50Mhz, the phase error for unsynchronized clocks would be 50MHz/200MHz=25 %, which is far too much for high-precision I/Q demodulation. A constant phase shift does not matter, but a time-variant phase drift matters a lot.Is it possible to synchronize the Open Kelly clock with the external clock of the wave generator?Or is it possible to, at least, read the flags of the external clock independently from the master clock, so that one can calculate the time-difference between the clock flags with an accuracy of 1 ns or better?A related question would be: Is it possible to run the I/Os at individual clock rates that are NOT a divider of 200 MHz, let's say, at 190 MHz?Of course, one could add another ADC for reading the reference sine wave at the rate of the master clock, or one could add a DAC for on-board sine wave generation. But I think, there must be a more elegant and recourse-friendly solution...I am happy with any advice. Thanks!

author: NorthGuy
author_rank: Super Contributor
timestamp: April 13, 2018, 01:55:02 pm
content: Looks like these boards are made of Artix-7.You can run any part of FPGA on any clock which you can bring in. Thus clock doesn't need to be synchronous with other clocks which may be used in other parts of the FPGA. You can easily have FPGA design where many different parts are run from many different clocks. For example, DDR3 controller working with a DIMM module uses more than 20 different clocks.The FPGA also has very advanced clock generating capabilities if you need to produce different clocks you can use MMCM can PLL. You can multiply or divide the incoming clock. They also can generate practically any frequencies, and any phase shifts.Finally, FPGA has delay elements on every pin which can delay the incoming signal to align it with the clock.You can transfer data between clock domains and the simplest way to do it is using FIFOs. You write to one end with one clock (for example ADC clock) and read from the other end with a different asynchronous clock without any restrictions on the clock relationship (besides obvious fact that if you continuously write with faster clock and read with a slower clock the FIFO will overflow).

author: Tueftler
author_rank: Contributor
timestamp: April 14, 2018, 08:03:01 am
content: Hi,Thanks for you answer. I was reading now the Artix-7 datasheet. I think the points "Mixed-Mode Clock Manager and Phase-Locked Loop" and "MMCM Additional Programmable Features" on page 8 are important for the synchronization. But, it's not getting very clear to me. Is the phase-shift timing increment the value I am looking for to calculate the accuracy of the clock synchronization? At 1600 MHz, the phase-shift timing increment is 11.2 ps. How much is it at 200 MHz?Well, I don't really want to run everything with the external sync-out clock of the sine wave generator, because it is quite slow and probably not very accurate. I would like to use the 200 MHz master clock of the FPGA for all possible on-board elements (ADCs, multiplexer...). Additionally, I want to synchronize the sync-out of the sine wave generator and maybe another trigger-out from annother FPGA board.Can we do the calculations for a simple example? Let's assume we have the FPGA master clock of 200 MHz controlling all the board elements. Then, we have the sync-out clock of the sine wave generator running at about 60 MHz, connected with one I/O of the FPGA. Can I switch the MMCM/PLL to this I/O and lock to the 60 MHz with an accuracy of 11.2 ps? This would give me a phase accuracy of only 60 MHz * 11.2 ps = 0.07 % right? That's probably not as accurate as running an on-board DAC (connect to the 200 MHz master clock) for sine wave generation?

author: NorthGuy
author_rank: Super Contributor
timestamp: April 16, 2018, 11:42:15 pm
content: Once again, FPGA doesn't run on a single clock. You can run parts of it using one clock, and you can run other part on the other clock. They don't need to be synchronized. If you get an external reference clock from DAC or another FPGA, you can simply use this clock to generate your output, there's no need for any synchronization with the other clocks in your FPGA to accomplish this.If you want to synchronize DAC output with something inside FPGA, there will be some delay from the input you generate to the output the DAC produces (delay inside FPGA, PCB traces, delay inside DAC), which will be at least several ns. Therefore, aligning your clock's phase with high precision doesn't really accomplish anything useful. You cannot really align the DAC output unless you have some sort of means to measure the entire delay.