Adc input filter - Page 1
Forum section: electronics / projects

author: nihial
author_rank: Regular Contributor
timestamp: May 02, 2023, 03:02:08 pm
content: Hi,By curiosity I'm looking at how to filter an ADC input and the requirements for the filter using an RC filter as example,From what I understand, the capacitor in front of an ADC should have enough charge so that when the sample and hold circuit is charged, the voltage change induced from the charge moving from one cap to another should be lower than a certain value (let's say 1/2 LSB)Then there's the resistor, I'm not sure what requirements are applicable to it. My intuition tells me that the current should be enough to recharge the storage cap enough and that the higher the sampling frequency the lower the resistor should be.Is there a paper on that somewhere using as a hypothesis that the sample and hold circuit capacitor and series resistor are known ?Best regards

author: wasedadoc
author_rank: Super Contributor
timestamp: May 02, 2023, 03:08:33 pm
content: Are you asking about a low pass anti-alias filter or the sample and hold components? Quite different things.

author: nihial
author_rank: Regular Contributor
timestamp: May 02, 2023, 04:10:32 pm
content: Anti aliasing and what to pay attention to when chosing their values other than the cutoff frequency

author: David Hess
author_rank: Super Contributor
timestamp: May 02, 2023, 09:53:40 pm
content: Quote from: wasedadoc on May 02, 2023, 03:08:33 pmNeither, this is about providing a low enough AC impedance to drive the sample and hold. Many feedback amplifiers have problems with this so capacitance is added at the input to the sample and hold to provide the needed charge. A series resistor may need to be added to allow the amplifier to drive the capacitor.

author: moffy
author_rank: Super Contributor
timestamp: May 02, 2023, 11:21:46 pm
content: Quote from: David Hess on May 02, 2023, 09:53:40 pmDavid Hess is correct it is about providing a suitably low input impedance into the ADC to drive the sample and hold without degrading the ADC's performance. However if you have a lower bandwidth input signal you might be able to adjust the values slightly e.g.https://www.analog.com/media/en/technical-documentation/data-sheets/ad4000-4004-4008.pdfpage 23 gives a table of input RC values based upon input bandwidth, it's not much of a variation but there is some. I think the best advice is to follow the manufacturers recommendations as no doubt they have done significant testing.

author: Berni
author_rank: Super Contributor
timestamp: May 03, 2023, 06:52:46 am
content: Quote from: David Hess on May 02, 2023, 09:53:40 pmIn some cases you can use a RC circuit to do the job of both.For fairly low bandwidth scenarios where you just want to measure some voltage you can tune the RC filter for a pretty low frequency (helps with noise too) and this results in a pretty high value capacitor down there (like 100nF 1uF..etc) and so the capacitor itself has enough charge in it to quickly fill up the ADCs internal sample and hold capacitor. As long as the sample rate is low, then the filter capacitor has plenty of time to come back up to charge by the time the next sample gets taken.This is especially useful when you have a large number of analog input channels, say 16. Having that many buffer amplifiers would be expensive and take up a lot of space. caps and resistors are cheaper and easier to layout, while with so many channels most of the time the ADC will be sampling other channels, so leaves plenty of time for the capacitors to charge up.But all depends on the exact case, what sample rate, what accuracy, what kind of ADC..etc

author: tinfever
author_rank: Regular Contributor
timestamp: May 03, 2023, 08:56:11 pm
content: This is how I think of it, although it could be wrong:On a very short time scale, when the sample and hold cap is connected to the input RC filter of the ADC, the voltage on the caps now in parallel will drop. You either need this initial drop to be less than 1/2 LSB, *or* your acquisition time needs to be long enough that the two parallel caps can recharge through the resistor to less than 1/2 LSB of error. Example: 10nF input cap at 3.3V + 8pf sample and hold cap at assumed 0V = 2.637mV dip (Analog Devices calls this Vkick I think) on start of acquisition.If you can have your acquisition time long enough for the caps to recharge, no problem in the short time. How long is long enough? Well assuming an input RC filter of 10nF + 400R, a 12-bit ADC with a Vref of 3.3V, it would take 7.5us for that 2.637mV kick to recover to 1/2 LSB error of 402uV. This assumes an ideal voltage source for your input signal though. Also, note that acquisition time is different from time between each sample. The sample and hold cap has to be connected for it to count towards acquisition time.You can either make sure you have sufficient acquisition time or you can reduce the cap size in your RC filter. I guess at the extreme you could reduce the RC cap size down to zero, then your Vkick is enormous but your recovery time is almost instant, however now you don't have a filter at all.On the other extreme, you could have a very large cap size in your RC, then your Vkick on acquisition stays below 1/2 LSB so no recovery needed. However, now your RC filter either has a very low cut off frequency, or if you reduce the resistor to compensate, now you are trying to drive a large capacitor with your input buffer (if applicable), which is problematic too.There are other challenges on a longer time scale. If you assume each sample requires filling an 8pf sample and hold cap from 0V to 3.3Vref worst case, and you sample at 80kHz, you're now pulling a sort of constant 2.1uA through your 400R resistor in the RC filter, which means you have an additional error component of 2.1uA x 400R = 844uV = 1.05 LSB ...oops. (Edit: I think this error part might actually be a mistake by me. In theory I think the current through the resistor will have decayed enough as the capacitor recharges that at the time of acquisition, this might not actually be introducing much error. I need to think about this some more...)Also on the longer time scale, if you rely on having a big cap in your RC and not worrying about recovery at all, that might be fine the first sample, but in theory each sample is going to pull a little more charge out of your input cap, if you didn't have any recovery at all, and your error keeps climbing. This is mitigated by the fact that you do have some recovery or nothing would work in the first pace, and the larger your error on the input cap, the more recovery current you'll pull through the input R. So it actually balances out at some level of error.This is when I usually start simulating the circuit in LTSpice because there are just too many interacting parameters. For example, an input buffer could actually cause overshoot during acquisition and recovery in some scenarios. Then you have to start looking at the bandwidth of the input buffer and ...Real example:STM32F103 MCU with 12-bit ADC and 3.3 VrefOne input sampling at 80 kHzSample and hold cap: 8 pFTarget RC cut off would be 40 kHz (half sample rate) and that is probably still not great because the cut off of a single RC filter isn't that sharp.1 LSB = 804 uV1/2 LSB = 402 uVSelect components:68R + 68 nF for RC filter = 34.4 kHz cut offUsing Gainsil GS8594 opamp for input bufferCalculation results:Vkick = 388 uV = 0.48 LSB (no recovery time needed for 1/2 LSB error target)DC error due to sampling frequency * sample and hold cap current = 143 uV or 0.18 LSBSimulation results:~32.7 uV = 0.04 LSB error from C in RC filter never full recovering to ideal value before next sampleTotal error = 0.48 LSB + 0.18 LSB + 0.04 LSB = 0.7 LSB error? (Simulation shows closer to 0.51 LSB total error so there is a difference created somewhere, could be 100% my error.)I haven't built this board yet so I can't say for sure yet that it works though.

author: nihial
author_rank: Regular Contributor
timestamp: May 04, 2023, 10:21:29 pm
content: Your explanation feels correct, I found the missing piece of the puzzle in my head and the math associated with it. I like to have the math to confirm intuition and not to trials and errors sessions blindlyThe minimum acquisition time is not only dependant on the RC product (constrained by the desired BW) but it's a product of R*C * ln(Vkick/Vsettle) which confirms the intuition at the extremesThe larger the R for a given RC the larger the min acquistion but less problems with driver stability.Minimum R can be found using simulation but this formula quickly gives a rough estimation of the minimum acquisition time and what parameters influences itNice videos about it short and clear :

author: gf
author_rank: Super Contributor
timestamp: May 04, 2023, 11:23:16 pm
content: See alsohttps://e2e.ti.com/cfs-file.ashx/__key/telligent-evolution-components-attachments/00-232-01-00-00-12-39-75/PA_2D00_001--Optimize_5F00_SAR_5F00_converter_5F00_design-REV-b.pdf

author: David Hess
author_rank: Super Contributor
timestamp: May 05, 2023, 11:44:47 am
content: Quote from: nihial on May 04, 2023, 10:21:29 pmIt does not cover what happens at the extreme of no RC filter. Unfortunately she does not cover that in the video. She mentions using the RC filter to control bandwidth and therefor noise, but it also isolates the driver from the ADC's charge injection, which may be the only reason to have it. If I did not care about limiting noise, then why wouldn't I connect the driver directly?Some of the more recent ADC drivers do not require the resistive element at all, and will drive the capacitor filtering the ADC input directly.At a further extreme, sampling is possible where the sampling time is shorter, even much shorter, than the acquisition time, in which case the input RC element is irrelevant because it is literally too far away. All that the sampling element sees then is the resistive impedance of the transmission line.