KM44C256BP-8 : 256K x 4bits DRAM --- How to refresh ? - Page 1
Forum section: electronics / beginners

author: PinheadBE
author_rank: Regular Contributor
timestamp: October 25, 2022, 11:42:15 am
content: Hi,I found back a small lot of those DRAM chips in DIP-20 package in my parts binI suspect they are outdated and with no commercial value left.So, I would like to experiment with them, and why not, use some of them in a hobby project, "just because".I have never handled the problematic of refreshing a DRAM.Nowadays, as I understood, the refresh controller is embedded in the chip, which was not the case of the ones I own.Does anyone have a readable documentation or example of how I could achieve that with a microcontroller ?All ideas are welcome.Thanks

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 25, 2022, 11:56:16 am
content: Did you read thedatasheet? There's no autorefresh.As stated in the datasheet, you must access all the 512 rows every 8ms, that's a 15.6us refresh cycle.The only way I can think on is to set a timer interrupt every 15.6us doing the refreshing.For example:Code:volatile uint16_t refresh_row;void read/write_ram(etc, address, count){while(count --){disable_interrupts(); // avoid refreshing while accessing addressset_address(address);load/save data();enable_interrupts(); // Allow refreshing again}}void timer_interrupt(){ // Every 15.6usload_ras(refresh_row++);toggle_dram_signals();if(refresh_row>513)refresh _row=0;}

author: PinheadBE
author_rank: Regular Contributor
timestamp: October 25, 2022, 12:35:04 pm
content: Thanks for that answer.Yes I read the datasheet, but I wondered because that seems to be very time consuming for a mid-range micro .Example: if I use a PIC controller running at 32 MHz, this gives an instruction cycle duration of 1 / (32M / 4) = 0.125 µsDuring an elapsed time of 15 µs, the PIC could only execute, give or take, 120 single assembly instructions.....The refresh process, if completely handled by firmware would take a significant part of the process power of the microcontroller.....

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 25, 2022, 12:48:11 pm
content: That's why you only see them in systems with dedicated hardware dram support doing all that stuff automatically.I might be wrong, but drams with self-refresh still need this type of manual refresh when running in normal operation, the autorefresh command is a low-power mode doing the refresh to keep the data.Edit: I might be mixing self-refresh with auto-refresh:https://www.edaboard.com/threads/dram-question-auto-refresh-vs-self-refresh.133575/Anyways, not automatic.What you're searching for is a pseudo-sram, it's a dram interfaced like a normal sram.However they still have limitations, for example you can't perform long operations, refreshing is inhibited while Chip Enable is selected, so any operation must last at most about 64us.Again, modern hardware can automatically handle this.

author: macboy
author_rank: Super Contributor
timestamp: October 26, 2022, 03:33:28 am
content: The requirement is to access each row at least once every 8ms. You don't need to spread these access out evenly so that you literally do one each 15.6 us. You could fire an interrupt each 8 ms and do all 512 refreshes all at once. Or do 64 refreshes each 1 ms. Or 8 each 125 us. You dramatically reduce the overhead of the refresh interrupt by doing it less often and doing a little more work inside each time. This RAM has a convenient CAS before RAS refresh which uses an internal row counter so you don't even need to provide a row address, just toggle the CAS and RAS with appropriate timing.

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 26, 2022, 04:34:32 am
content: Datasheet clearly says all 512 rows every 8ms, not each row every 8ms.Rest is doable!

author: David Hess
author_rank: Super Contributor
timestamp: October 26, 2022, 03:28:00 pm
content: Computers of the past sometimes used the timer interrupt method to implement software controlled DRAM refresh. The original IBM PC used the output from one of the 8254 timer channels to trigger a DMA channel to issue a read for DRAM refresh.Either system was sometimes useful in real time systems because refresh could be temporarily disabled during a critical operation and then resumed.

author: PinheadBE
author_rank: Regular Contributor
timestamp: December 13, 2022, 01:38:07 pm
content: Quote from: macboy on October 26, 2022, 03:33:28 amThat's it !It works without a treat and do not eat up the controller time.Thanks MacBoy !

author: BigJoeScientist
author_rank: Newbie
timestamp: June 12, 2024, 04:06:44 am
content: @PinheadBE, I'm interested in acquiring some KM44C256BP-8. Don't suppose you have any you'd be willing to part with? I need them for a digital sampler repair.

author: PinheadBE
author_rank: Regular Contributor
timestamp: June 12, 2024, 11:23:00 am
content: Quote from: BigJoeScientist on June 12, 2024, 04:06:44 amHi, I still have 8 pieces, NOS, butNOT TESTEDThe problem is the cost to send it from Europe to the USA.....