Getting started with FPGAs: choices on HDL and devboards - Page 1
Forum section: electronics / general

author: ivan747
author_rank: Super Contributor
timestamp: May 06, 2013, 10:20:13 pm
content: I want to spend my last school summer break wisely by learning how to program FPGAs. Now, I have a couple of questions. As anyone getting started I am overwhelmed by terms I don't know so I can't do an informed choice. These questions have been asked hundreds of times when it comes to MCUs, but what about FPGAs:Which hardware description language is best to get started? (notice I don't ask which one's the best because that's very subjective and probably dependent on the application)Which method is best to learn? By this I mean, should I go for something analogous to an Arduino/Launchpad, simulators, actual hardware on a SMD breaktout or expensive development boards with integrated peripherals?I can order online and I prefer a budget of $30 but I can extend it up to $100. I would also like to have a varied stock of chips in the future, as I currently do with microcontrollers, but that comes later.For $30 I can't really get much, but you know, since we have RasPi for $40 and MSP430 for $4.30 I thought it is possible. After this a fake programmer will probably cost me $50, but that is easy to justify after I learn on something like the board I hope to get.I learned MCUs by purchasing a simple 8 pin PICAXE. It's essentially a PIC with a bootloader that allows you to download BASIC code to it. It has a built-in interpreter. Then I moved to PIC by buying a JDM programmer and programming in C. So I didn't start out with anything fancy, but FPGAs are not that simple either.Thanks for all.-Ivan

author: free_electron
author_rank: Super Contributor
timestamp: May 06, 2013, 11:25:05 pm
content: get a terasic board. for 50$ you have the device + the programmer.as for the easiest language to start ... systemverilog or verilog 2005.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 06, 2013, 11:46:27 pm
content: The Lattice LCMXO2-7000HE-B-EVN board is in your budget and has onboard programmer. No peripherals though.I would very strongly recommend you define a specific thing to develop an work towards that, instead of random tinkering. This forces you to work through issues instead of wandering away onto something elseI only know VHDL , but from what I hear, VHDL is less likely to land a beginner in trouble as it has more thorough type checking

author: MacAttak
author_rank: Unknown
timestamp: May 07, 2013, 12:03:34 am
content: I am just getting started in it, I always assumed that it would be just a bit too difficult of a learning curve for me at this point. I ended up getting a Mojo board (decent Spartan-6 chip) from Embedded Micro, and have been very happy with it. Cost is $75 and no external programmer is needed. It is a very minimal board - just the FPGA, power jack, micro USB port for programming (using an AVR chip on-board), reset button and 7 LED's. All of the signals (including almost 200 IO pins) are broken out into 1mm headers.I don't get the impression that language choice really matters all that much for most things. I went through the Xilinx ISE tutorial material and everything was shown in both Verilog and VHDL and it really wasn't very different.

author: nctnico
author_rank: Super Contributor
timestamp: May 07, 2013, 12:09:44 am
content: I don't know if a larger project is a good idea. The first thing I ever made on a CPLD was a counter.

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: May 07, 2013, 12:12:05 am
content: I am in a similar situation to Ivan and was about to buy a Papilo pro from Gadget Factoryhttp://papilio.cc/index.php?n=Papilio.PapilioProSpartan LX6 with 64 Mb SDRAM. What do the experienced folks think?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 07, 2013, 12:20:22 am
content: Quote from: nctnico on May 07, 2013, 12:09:44 amStart small, and build gradually into something more substantial, but it really helps to have an end goal.

author: marshallh
author_rank: Unknown
timestamp: May 07, 2013, 12:53:00 am
content: Quote from: chickenHeadKnob on May 07, 2013, 12:12:05 amGet the DE0-Nano instead. It has an Altera Cyclone IV.Avoid the Xilinx tools like the plague (yes even they know ISE is crap).Don't be another one that ignores my advice then bawws at how hard fpgas are unnecessarily

author: ivan747
author_rank: Super Contributor
timestamp: May 07, 2013, 01:24:20 am
content: Quote from: free_electron on May 06, 2013, 11:25:05 pmThis DE0-nano is actually $80 but the built-in peripherals aren't too bad. It's got RAM, EEPROM, basic LEDs and switches, ADCs and even an accelerometer.Now, LCMXO2-7000HE-B-EVN (what's going on with these model numbers?).The price seems very atractive, built-in RAM too. Seems like this is more what I need. On the DE0-nano I have things I probably won't use, like the accelerometer or the 32MB of RAM. I am not a crazy programmer, at least in programming languages. Who knows, maybe I will become a HDL freak.The DE0-nano features a much more powerful chip but I can't find a use for it right now. Also, the Lattice chip has hardwired peripherals I can use, like I2C. The DE0-nano's series of chips can even support PCI Express! I like it, but I will keep it for when I can take advantage of the student discount.So far the LCMXO2-7000HE-B-EVN is the chosen one.Quote from: mikeselectricstuff on May 06, 2013, 11:46:27 pmAs a project, I want to do a "lab-grade" chronometer/timer with external triggering and such. It could accept 10MHz input, provide a 10MHz and 1pps outputs. It can also have a real-time clock and store datestamps and what not. But it will start as a chronometer with external trigger. I know there must be some variation of the frequency counter that does this but whatever, I need an excuse to work on FPGAs. You can do this all with discrete components, of course, but again, I need an excuse to work with FPGAs. And I suspect the board will be smaller if I use an FPGA instead of discrete logic. I want to make it small.Quote from: MacAttak on May 07, 2013, 12:03:34 amMojo is still on pre-ordersI am getting the same impression on the language as well. Are they interchangeable? i.e. do manufacturers support both languages extensively?

author: free_electron
author_rank: Super Contributor
timestamp: May 07, 2013, 03:25:15 am
content: The language is irrelevant. the tools handle both equally fine.Verilog is easier to 'step-in'- there is less keyboard pounding involved- it's more productive ( not my words. year after year it is proven again in 'coding contests' between vhdl and verilog guru's . they get 30 minutes to desing something. the veriloggers are alway fully ready, fully debugged and the vhdl'ers are still fixing punctuation and lexical errors in their source )Now, irrepective of the language used, the mindset is TOTALLY different from working on a CPU. A CPU works sequential. in FPG aeverything happens simultaneously under control of a clock. the 'program' in the fpga determines what is ALLOWED to happen. ( on a cpu it's more 'what must happen')an important stepstone in beginning work with synthesis languages ( whetehr in cpld /fpga or ASIC work ) is UNDERSTANDING the synthesis process.This is where 99% of the people beginning this stuff go catastrophically wrong. there are very few books that explain this process and the basic concept is lost. this leads to ugly ,kludged code, that often has uncovered scenarios and doesn't exactly do what you expect it would do. you then need to patch in more 'conditions' to cover these holes. if you understand the synthesizer you won't run into these problems.The languages have evolved use the latest versions as they solve annoyances that often get frustrating very quickly.Verilog2005 (sometimes called SystemVerilog although they are not 100% the same) is now the de-facto verilog standard. VHDL sits at release 204 i believe and 2010 is almost (very lately) finished but only some hi end tools support that one .How does a logic synthesizer work ?it essentially needs to translate a list of instructions and conditions ( if/then/else , mthematical and boolean operations etc ) into a block of logic. the way we describe theis block is essentially 'sequential'. it is a bunch of lines of code , each line containing some instructions. so the synthesizer reads these line by line and builds code.. but this s contradictory to the concept of digital logic ! everything has to happen at once. so how do we translate this 'list' into parallel form ?the solution is simple :we begin at the INPUTS, read the first line and build a little cloud that connects inputs to what is required by the line of code.the next line of code as 'glued on' at the end of the previous build step.once we hit the last line of code we have reached the OUTPUTS of the block. at every step the synthesizer can cut wires going to outputs and 'inject' a new block. it can also splice existing signals.so we grow our logic from INPUT to OUTPUT.an example ( in pseudo laguage so it is easy to read)if x = 1 thenz = a and belsez = a or bend ifso this describes a block that can switch between an and and an or operation under control of a signal.so the synthesizer will begin building :if x=1 then : take input pin'X' and drive a mulitplexer 'select' signal ( if/then/else constructs are built using multiplexers).z = a and b : output of the multiplexer goes to 'Z' . Apply signals A and B to an AND gate. Ouput of the ANd gate goes to the multiplexer input for'X=1'else : this is the other multiplex casez = a or b : take a and b and attach to an or gate. output of the or gate goes to mulitplexer input for 'x=0'A mulitplexer is a simple boolean equation. a mulitplexer has a control line (S) , two inputs (x and y) and an ouput (z). the equation is Z = (X.Sn) + (Y.S)since our code generates more boolean stuff we can now substitute terms into a massive equation, squash it, reduce it and done. we have logic.when code becomes more complex you will need more constructsif (enable=1) thenif updown =1 thencount = count +1elsecount = count -1end ifelseif reset = 1 thencount = 0elseif preset = 1 thencount = inputvalueend ifend ifthere. the bove code is a simple counter that can count up and down, has a reset and a perest input. reset makes count zero , preset loads an input value. but.. can you figure out what will happen in the following cases :i make reset high and i make preset high ... (this one is fairly obvious)i make reset low and preset low ... (this one is bit harder.. it is actually undefined as there is no full definition for this pathway...this can lead to very strange situations and logic not doing what you expect it to do . and this is a common pitfall. your block of logic does not work right under all possible conditions because you forgot a pathway ... you need to go over the entire tree and figure out hat happens when... reading a large block becomes tedious to understand.if you use the scheduling technique this problem will not occur.Scheduled code is code written in such a way that there are no ambiguous or forgotten conditions possible by using the synthesis mechanism.both VHDL and Verilog have a clause in the language definition that states the following : Logic shall be implemented in the ORDER it was WRITTEN.what does this mean ? this goes back to the way the synthesizer builds logic. it read a line , builds a little cloud of logic , splices input sgnals and cuts the prior generated output to inject the new block inbetween.so, the LAST line of code in a block sits CLOSER to the output than the first line of code.using this mechnism we can rewrite our counter as follows :if updown =1 thencount = count +1elsecount = count -1end ifif enable =0 then count = countif reset =1 then count = 0if preset =1 then count = input valuethe lowest line in this list has the HIGHEST priority. we don't care what has happened earlier. as the lowest line sits closest to the output it takes controlso , depending on 'updown' we count up or down.if enable is zero then count remains count. this line sits closer to the output. so it doesntmatter what updown just wanted to do. if this line is active then count will not move !if reset =1 thencount = 0. i dont care that enable wanted me to stay where i was.. theis line says : if reset is low : counter becomes zero. screw what happened before !and lastly if preset is 1 then i load the input value.there are no hidden pathways. something will happen , no matter what. the priorirty of 'what' happens is purely defined by the order of the instructions.if someone tells you reset needs priority over preset you simply swap those two lines.for simple things this may not be that obvious but if you start writing large complex blocks this way of coding saves a lot of time and it eliminates problemsfor example an i/o block that talks to a bidirectional bus that needs tri-stating.output = Z ( high impedant)if (write) thencase (address)0: output = somevalue1: output = someothervalue9 : output = anothervaluedefault : output = 0xdeadbeefend ifthere we go. by default the 'output' pin is high impedant. only if 'write' is logic high will i apply some code that looks at an address and switches through some data.if they now tell me i need a few additional modes : in reset all outpus need to be low ,and in writetest mode a special pattern (010101010) needs to be therei simply add two lines at the endoutput = Z ( high impedant)if (write) thencase (address)0: output = somevalue1: output = someothervalue9 : output = anothervaluedefault : output = 0xdeadbeefend ifif testmode then output = &b01010101if reset then output = 0done. this reads very easily . there is no mishmas of if then else elseif and other curly wurly bits.output is high impedant, except if write is active then we look at address and throw some stuff on there, except if testmode is active then we throw 1010101 on there ,except if reset is active then we throw all zeros on there.no hidden pathways, no surprizes. very aesy to read and understand , very easy to modify ( priority changes is a matter of moving some lines up or down ) and there is a very good chance it will work first time as you intended it to work.

author: marshallh
author_rank: Unknown
timestamp: May 07, 2013, 03:32:04 am
content: Have a look at my verilog tipshttp://retroactive.be/verilog_tips.pdfState machines, counters, muxes are the bread and butter of synchronous logic. It took me over a year of head banging (not the good kind) to figure out how to start thinking in the right mindsetI use/abuse the priority ordering that free_electron was talking about all the time. But you need to be very careful as in larger modules you can forget about it and chase bugs for days. I usually put some sort of cycle counter increment at the top and handle resetting inside the FSM cases below, and synch reset FSM resets go at the very bottom

author: TerminalJack505
author_rank: Super Contributor
timestamp: May 07, 2013, 08:28:57 am
content: I'd recommend getting a bare-bones FPGA board. If you get a board with a bunch of stuff on it then you'll likely find that all that stuff just gets in the way and wastes I/O pins and power when you want to put your own code on the FPGA.I would get an all-in-one type of board only if you have lessons or a book that walk through projects using that particular board.If you're just starting then, like others have said, you might consider starting with a CPLD. You can't fit a lot of code on them but you'll want to start small anyway. If you make your own boards at home then you can buy just the CPLD and make your own development board since a lot of the CPLDs come in hobbyist-friendly packages.Finally, if you haven't taken formal lessons on digital systems design then I recommend you grab a cheap used textbook on the subject and watchthese video lectures.To effectively define hardware with an HDL you need to have an understanding of discrete digital electronics and these lectures will give you a good foundation on the subject. This is very important if you are coming from a programming background! Verilog and VHDL are not programming languages. They are hardware definition languages. You are building a digital system with a textual representation. You arenotprogramming a CPU.Random Rant:If you come from a programming background, you will absolutely hate Verilog and VHDL. You can tell they were developed by EEs and not software developers. For example, neither language uses curly braces to denote blocks of code. Because of this you get code that becomes unreadable when you mix poor indentation habits with just a few levels of nesting.

author: chickenHeadKnob
author_rank: Super Contributor
timestamp: May 07, 2013, 10:05:03 am
content: Thanks to free_electron, Marshallh for pointers, Respect!I just did the findchips thing for the altera thats on the DE0 nano: $66.00 for a 256 pin BGA package. The Xilinx on the Papilo pro: $15.50 for a 144 pin lqfp. I can't tell how much this is apples to oranges as I don't have a good feel as to how to compare them. Superficially the xilinx looks friendlier If I was to develop my own homebuilt boards so the waters just got muddier.

author: nctnico
author_rank: Super Contributor
timestamp: May 07, 2013, 01:18:38 pm
content: Quote from: free_electron on May 07, 2013, 03:25:15 amIMHO this code should work fine. An uncovered path (enable, reset and preset low) causes no change. Exactly as the code describes. You showed the scheduling before but I really don't like it because the code doesn't describe what has priority. You have to assume people know about some obscure rule if you allow them to maintain the code. All in all I'm not convinced the problem you outline actually exists. Maybe at some point you made an error in your code which could have been fixed by using a different construct but instead someone showed you an obscure quick fix. At some point if-then-else constructs based on several signals become messy. A better solution is to concatenate the control signals in a new signal (vector) which resembles states and use a switch statement. If you want to play nice you can create a named type with names like LOAD, COUNT_UP, COUNT_DOWN, RESET, etc. Not necessary for this example but for more complex situations definitely something to consider.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 07, 2013, 01:29:39 pm
content: Quote from: TerminalJack505 on May 07, 2013, 08:28:57 am..and with cheap, simple boards, it's much less of a deal if the smoke comes out, or if you want to do some solder kludgingQuoteMy pet hate is the lack of #define, #include and block comments, and enforced seperation of things like device type and constrints from the HDL source.These things don't matter much if you're designing an ASIC, but for FPGA development it is highly likely you will have a differnt device on a protoype than a production unit, and there is much more need to deal nicely with product variants, and teh inability to specify these options elegantly with a few #defines is a major PITA..and why do we need yet another symbol for comments - I'm frequently flipping between VHDL, C and VB on one project - all with their own different comment characters

author: free_electron
author_rank: Super Contributor
timestamp: May 07, 2013, 02:47:25 pm
content: @nctnoco: scheduling is not 'obscure'. It is the basic fundament of how synthesizers work ! Both the vhdl and verilog definitions (the ieee specs) have a whole chapter on it. In fact, you cannot pas the 'compiler test' if you do it differently. It is MANDATED by the spec to work that way. So any synthesizer has it.Scheduling makes the construction of very complex thing very simple with minimal keyboard pounding. Maintenance is also simple. You never need to wonder in which branch if the ifthenelse soup things go wrong. Just move the line up or down to change priority. Lowest prioirity is at the top. Highest at the bottom.@mikes electricalstuff : whaddayamean no define ?'Define something 16'd123'Define nextstate state<=state+1'Define resetmachine state<=0'Define return state <= savedstate'Define gosub savedstate <= state + 1; state <=If x =='something ....Select case state0: if start then 'nextstate1: beginx <= somethingNextstateIf abort then resetmachineEnd2: begin'Gosub 1000;End;3: blabla ...1000: beginIf |x thenx<= x-1;Else'Return;My statemachines have gosub-return and goto's !I can even build stacks and make nested constructs.I use this all the time for serial prototcols. For example a 32 bit packet contains 7 leading zeroes , a sync bit and then, dpeneding on the sync bit either an 8 bit or a 16 bit right aligned payload.Imstead of mucking about building counters at every phase i have a generic 'downcounter' state. I load the downcounter and 'gosub'. At this point the returnstate is stored , the count begins and the machine returns all by itself. The define construct allows you to define anything. Numbers , code, even multiple lines of code. Note that you need to use the 'backtick , not the regular tick . Its the tick on the topleft keyboard button, paired with the tilde.Includes exist as wellSame for comment and block comment// is comment/* blabl */ is blcok comment.No different than c.Oh . I now only noticed you are talking about that 'Very Hard Design Language' do yourself a favor and switch. There are good verilog code editors with auto indentation, code collapsing and more. ( they exist for vhdl also)My main gripe with vhdl is that there is too much typing involved ( keyboard pounding) and duplication of work. You need to define all signals twice.If x is an output you cannot write x=x+1 as you cannot read back... You need to define an intermediate signal to bring the output back in. Then there is the muckery with all the libraries. Std-blabla ieee-blabla. There is maths , boolean and you need to provide the marshalling between them. Synopsis has its ow libraries that are not compatible with ieee and it all becomes soup...And in every block of code you need to reload the libraries. How stupid is that ?This misery stems from the original project. HDL was a darpa project to make a uniform language to describe hardware. This can be anything. From a nut or bolt , a wing of an aircraft , a chair .. Anything. See it as a kind of xml precursor. The HDL in itself has no concept of anything. It is just a storage and retrieval format for information. You can extend the language using libraries. You can define what is a zero and a one and a tristate and a dont care. You can define what the + operator does for numbers, for strings, or for wakalixes (wakalixes being something you invented. If you need to add two wakalixes togethere here is how you do it. Basically operator overloading.So, some other darpa project Vhsic : very high speed integrated circuit. Was looking for a way to describe circuitry in textual form and do away with schematics. Vhsic and hdl met each other , the libraries were written and off we go. Vhdl was born.But it fits like pliers on a pig ! It is a constraintfile, and a set of libraries bolted on to a generic language processor.Verilog was written fro. The beginning to describe logic. So it doesn't need all the curly-wurly bits.Both languages produce exactly the same output and are equals.Vhdl is just the grumpy sauerkraut snorting german while verilog is a friendly british grandma 'care for a crumpet and some tea ? 'You pick what you want to deal with every day .. The saur kraut , or tea and crumpets.

author: krivx
author_rank: Frequent Contributor
timestamp: May 07, 2013, 03:35:49 pm
content: Quote from: mikeselectricstuff on May 06, 2013, 11:46:27 pmIs there a source for these apart from Digikey? Rs and Farnell both stock similar looking boards but I'm not sure if they're comparable.LCMXO2-1200ZEhttp://ie.farnell.com/lattice-semiconductor/lcmxo2-1200ze-b-evn/board-breakout-machxo2-1200ze/dp/2253066LCMXO2280http://radionics.rs-online.com/web/p/programmable-logic-development-kits/7434788/

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 07, 2013, 03:43:27 pm
content: Quote from: free_electron on May 07, 2013, 02:47:25 pm..in VHDL - I gather Verilog is better in this respectMy main gripe with vhdl is that there is too much typing involved ( keyboard pounding) and duplication of work.Yes, it is a bit typing-heavy - if only you could do #define sl std_logic and #define slv std_logic_vector....Quotehuh?QuoteYou can do x=x+1 to a signal in VHDL - are you maybe talking about ports?QuoteAnother comparison I got the feeling of was that VHDL is like Pascal and Verilog is like C, in terms of type-checking and being able to get into trouble very easily.Quotemaybe I should look at Verilog next time I have a more serious project - I typically only do FPGA stuff every couple of years so tend to stick with what I know - projects are often on silly timescales (like 2 weeks for PCB, FPGA, firmware and build of boards) & fighting with general devtool and programmer issues tend to leave no time to learn a new language.The only reason I went for VHDL originally a few years ago was I found a good book.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 07, 2013, 03:50:19 pm
content: Quote from: krivx on May 07, 2013, 03:35:49 pmSomething to be aware of is they changed the FPGA, and hence the board part no from the 1200 to the 7000, so some websites have some confused part numbers - Farnell show the 1200 one as awaiting delivery.mouser definitely have it.http://uk.mouser.com/ProductDetail/Lattice/LCMXO2-7000HE-B-EVN/?qs=sGAEpiMZZMurtJ7VwBTl0fuXvMOPgNe8hSHI90CFJ0k%3dThe 2280 is the old XO family (unfortunate that the part no starts with 2 - this confused me for a while as the PCBs loko similar).BTW once you get started, I suggest avoiding using the programmer tool in Lattice Diamond - it's slow and can be flaky in SRAM mode- ISPVM (from Lattice website) is much faster (2 secs vs. 6 secs SRAM program time).

author: free_electron
author_rank: Super Contributor
timestamp: May 07, 2013, 04:28:12 pm
content: Quote from: mikeselectricstuff on May 07, 2013, 03:43:27 pmonce in the entity once in architecture.. it's all duplication of work.Quoteyep. if x is a registered output port you need intermediate hoop-jumping to get it back in. that's stupid.there is a t less keyboard pounding in verilog. you also don't have these annoying problems with the library incompatibilites. some people use the std_logic some use the std_maths and then you try to synthsize and you get barfed on by the compiler ...for a bit of fun : take a look at this topic :http://www.alteraforum.com/forum/showthread.php?t=23803imodule countr(input clk,enable,reset,ouput reg [15:0] count)reg [15:0] internalcntr;always_ff @(posedge clk)beginif (!&internalcounter) internalcounter <=internalcounter +1;if(!enable) beginif (|internalcounter) count <=internalcounter;internalcounter <=0;end ifif(reset) begincount <=0;internalcounter <=0;endendendmodulethe !& basically logically ANDS together all bits ( so it creates a 16 input AND gate , combining all bits in the counter) as long as the output of that ANd is LOW ( ! operator) we count up. when we hit all '1' the count will seize..as this is scheduled code the counter can be running always. since the 'enable' is tested later it has overriding power. that clause actually keeps the counter at zero unless we release it. i test if there is something in 'internalcounter'. if there is i copy it over to output. if there is nothing i don;t copy it over. this has the effect of 'holding' the last non-zero number.and finally the reset has the largest hammer. if that one kicks in i don;t care what any other rules said : wipe it all.Here is one of the disaster contests i talked about. this was organized by SNUg ( Synopsys Users group )http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.htmlthere are several others. one they had to make an alarm clock including mulitplexd 4x7 segment . they had 30 minutes. the veriloggers were all done. vhdl ? nil ... as their code wouldn't synthesize..

author: krivx
author_rank: Frequent Contributor
timestamp: May 07, 2013, 04:43:26 pm
content: Quote from: mikeselectricstuff on May 07, 2013, 03:50:19 pmThanks. Unfortunately shipping from Mouser is almost as much as the board. I might have to wait and combine a few orders.

author: TerminalJack505
author_rank: Super Contributor
timestamp: May 07, 2013, 04:46:10 pm
content: Most of my experience is with VHDL. I remember reading somewhere that Verilog was C-like. I thought, "Awesome! I'll have to check it out." It seems to me they forgot the important parts of C language.Who in their right mind would throw away the bracketing notation and use Pascal/SQL/Ada-style block notation?Oh well. At least it isn't Shell script notation:Code:if [ blah ] ; thencase $whatever...esac # Huh?fi # Wha... ?I'll have to do like Mike's thinking about doing and do a project or two in Verilog. See if I can stomach it a little better than VHDL.

author: nctnico
author_rank: Super Contributor
timestamp: May 07, 2013, 05:47:33 pm
content: The biggest advantage of VHDL is that it is a lot like a programming language. Like Pascal its roots lie in Ada. The thing is that a lot of designers use VHDL to describe logic equations. That takes a lot of typing indeed.In my experience one should approach an FPGA design as writing a piece of software and just don't care about how it is translated into hardware. VHDL offers a lot of powerful tools like functions and records (the C equivalent of a structs) which make life so much easier. A clever function can replace dozens of lines of code. A record can be used to easely convey a whole bunch of signals throughout a design like passing a pointer to a struct in C. It really pays off to study VHDL's advanced features.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 07, 2013, 06:00:37 pm
content: Quote from: krivx on May 07, 2013, 04:43:26 pmLattice do have their own store, but I suspect shipping may also be an issue. May also be worth prodding farnell - it could be that the part number change has confused their system

author: jahonen
author_rank: Super Contributor
timestamp: May 07, 2013, 06:12:38 pm
content: Quote from: free_electron on May 07, 2013, 02:47:25 pmBut if you make the port type buffer instead of out, it works just fine. No need to use an extra signal.Regards,Janne

author: MacAttak
author_rank: Unknown
timestamp: May 07, 2013, 06:19:43 pm
content: Quote from: ivan747 on May 07, 2013, 01:24:20 amThey are very new (just launched about 2 weeks ago), and now that the initial pre-orders will have all been shipped this week I think they are opening up web orders again. This was launched through Kickstarter, so those boards had higher shipping priority than any web-based orders.This board won't have all of the bells and whistles that a typical dev board might, but it is quite approachable and the vendor has been producing decent tutorials for the board (in Verilog) which are beginner-focused... starting with simple stuff like blinking an LED up to PWM and I/O.

author: marshallh
author_rank: Unknown
timestamp: May 07, 2013, 07:14:18 pm
content: Quote from: nctnico on May 07, 2013, 05:47:33 pm

author: nctnico
author_rank: Super Contributor
timestamp: May 07, 2013, 07:22:31 pm
content: So I guess you still program everything in assembly language

author: free_electron
author_rank: Super Contributor
timestamp: May 07, 2013, 07:51:11 pm
content: Quote from: nctnico on May 07, 2013, 07:22:31 pmcome talk to the people that are trying to minimize the die-size.... or are trying to do the timing closure on your convoluted design...designing hardware is not designing software ...

author: nctnico
author_rank: Super Contributor
timestamp: May 07, 2013, 08:36:34 pm
content: If silicon is expensive... most people work on low / medium volume products where time to market is far more important than saving a dollar on component costs. I've seen many projects where a lot of time and money got wasted because people tried to save pennies on components. Penny wise pound foolishBesides that developing code for an FPGA is exactly the same as writing software. There is a function Y which needs to be implemented with resources X in development time T. If you make X large then T gets small and vice versa. Unfortunately this relationship is exponential. If you make X smaller then T increases exponentially.

author: ivan747
author_rank: Super Contributor
timestamp: May 07, 2013, 08:40:09 pm
content: Quote from: MacAttak on May 07, 2013, 06:19:43 pmSounds good, if the price is right. I still prefer the Lattice board so far.

author: free_electron
author_rank: Super Contributor
timestamp: May 07, 2013, 09:24:27 pm
content: whoa. stay away from lattice ! talk about sucking development tools !stick to Altera or xilinx.best devtool is still altera quartus.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 07, 2013, 09:46:04 pm
content: Quote from: free_electron on May 07, 2013, 09:24:27 pmMaybe (never used it but hear good things) but Altera have nothing at the low end of the market that competes with Lattice or Xilinx, and Lattice go a lot lower than Xilinx at the lowest "only just need an FPGA" end. Probably less difference as you go up in size.Lattice software seems to be pretty much the same as Xilinx ISE in many respects and I'd be highly surprised if most of the code wasn't the same, less umpteen gigbytes of useless bloat of device files for devices you can't even use with the free version.Unlike Xilinx and Altera who have a PITA distribution system where you need to ask for quotes on production qtys, you can get quantity pricing easily from Digikey etc. on Lattice parts.

author: ivan747
author_rank: Super Contributor
timestamp: May 08, 2013, 07:04:31 pm
content: I don't think I will ever start a project complex enough to fully use the potential of a $60 FPGA. I found a handful of cheap boards searching around. I'll take a look in detail. I like Lattice's concept of having low end CPLDs for when you just need simple things. That's probably going to be my main use for programmable logic anyway.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 08, 2013, 11:56:03 pm
content: Here's a very cheap FPGA board option, albeit with minimal IO accessiblehttp://hackaday.com/2013/05/08/hdmi-color-processing-board-used-as-an-fpga-dev-board-to-mine-bitcoins/

author: ivan747
author_rank: Super Contributor
timestamp: May 09, 2013, 12:19:09 am
content: Quote from: mikeselectricstuff on May 08, 2013, 11:56:03 pmJust saw that. The time spent getting the thing to work properly for the first time isn't worth it, but hey, nice hack.The second last thing I want is to try to debug a learning tool. The last thing is debugging a debugger...I'm going for the Lattice devboad. It's readily available and I like it. Some say the software is bad but I've tolerated MPLAB X 1.0 so their software cannot bethatbad.

author: gocemk
author_rank: Regular Contributor
timestamp: May 09, 2013, 03:21:28 pm
content: Hi everyone,This is my first post on this forum, but i've been visiting here for a while now.I wanted to learn how to work with FPGA's, so i ordered this Open3S250E (actually mine is 3S500E):http://www.ebay.com/itm/XILINX-XC3S250E-Spartan-3E-FPGA-Development-Board-LCD12864-LCD1602-12-Kits-/261135683246?pt=LH_DefaultDomain_0&hash=item3ccce64eaefrom ebay along with the appropriate usb jtag programmer and a few other items (sd card board, GLCD, and keypad). It says that it comes with Xilinx ISE 12, and with examples with both Verilog and VHDL. So, i was wondering if any of you had any experience with this dev board and maybe can share something?I am still waiting for it to arrive, so maybe i'll post some pictures of it later.Thanks!

author: joelby
author_rank: Frequent Contributor
timestamp: May 10, 2013, 12:22:45 am
content: I maintain a list ofcheap FPGA development boards, which you might find interesting.Personally, I would recommend spending a bit more to get a development board that includes some of the more interesting peripherals that an FPGA can talk to.With a microcontroller, you can connect many of the external things you'd use with a few loose wires. An FPGA can talk to gigabit Ethernet PHYs, DDR memory, HDMI transceivers, PCIe buses, and so on. These high speed interfaces require attention to signal integrity and trace length matching during design and thus are much harder (or impossible) to breadboard on to a generic development board. I think that learning about these more complicated interfaces is good for developing more advanced FPGA experience.

author: ivan747
author_rank: Super Contributor
timestamp: May 11, 2013, 08:42:55 pm
content: Quote from: joelby on May 10, 2013, 12:22:45 amI have read this list as well as this website:http://www.fpga4fun.com/Thanks for the list. I am still considering my choices, but the site I mentioned has a great introduction I can use to guide myself and your list is a great place to get started.Update: Dave should do an FPGA introduction/tutorial series. If he splits the tutorial into several videos he will get hundreds of thousands of views combined.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 11, 2013, 10:47:36 pm
content: Quote from: joelby on May 10, 2013, 12:22:45 amLattice XO2 board I linked to earlier in the thread isn't there

author: ivan747
author_rank: Super Contributor
timestamp: May 12, 2013, 12:44:25 pm
content: Quote from: mikeselectricstuff on May 11, 2013, 10:47:36 pmMike, I have a question. On your iPod screen hacking video, part 2, is the CPLD operating at full capacity? And by that I mean, how many blocks were taken and if that is the maximum framerate you could get from it.I'm asking because that board is the Lattice XO2.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 12, 2013, 03:29:39 pm
content: Quote from: ivan747 on May 12, 2013, 12:44:25 pmNot much (see image) but the logic isn't very complicated. On my PCB I used the 1200, of which it used maybe 50%, but there is significant unnecessary logic for test & debug (e.g. serial commands to send DSI packets from the PC). I'm sure it would fit a 640 part without much effortIt currently takes 35mS to display a frame from flash, but this is just limited by me not having yet implemented wide flash transfers as I had to get something built & working quickly. Bandwidth to the display is not an issue - I had it running at 99MHz, but slowed it down to make it easier to debug on the cope. - It could easily do 60FPS.

author: ivan747
author_rank: Super Contributor
timestamp: May 12, 2013, 03:44:55 pm
content: More than capable for my needs, thanks!

author: glatocha
author_rank: Regular Contributor
timestamp: May 26, 2013, 02:41:24 pm
content: I would like to go back to the HDL question. From the future employment point of view, which Verilog or VHDL is better?More widely used and so on?

author: nctnico
author_rank: Super Contributor
timestamp: May 26, 2013, 08:56:34 pm
content: If you are in Europe: VHDL, if you are in de US: Verilog. I don't know about the rest of the world.

author: joelby
author_rank: Frequent Contributor
timestamp: May 27, 2013, 01:02:26 am
content: I don't think it's too hard to move from one to the other. The syntax is a bit different and VHDL is strongly typed, but the concepts as they apply to FPGAs are the same. Perhaps concentrate on whichever one is dominant in your geographic area, but make sure you're familiar with the other too.

author: ivan747
author_rank: Super Contributor
timestamp: May 27, 2013, 01:43:40 am
content: Would this be a good Verilog tutorial? I feel the author treats it more like a programming language than an HDL, but I'm not sure if this is the way it should be typed.Here's a page from it talking about thealwaysblocks:http://www.asic-world.com/verilog/verilog_one_day3.html

author: joelby
author_rank: Frequent Contributor
timestamp: May 27, 2013, 01:50:33 am
content: It's probably a little brief, but it might be okay as a basic introduction to the syntax. It doesn't make it very clear which parts of the language are synthesisable and which aren't (and what this actually means to you).. but to be fair it's a Verilog tutorial and not an FPGA synthesis tutorial.I'd probably recommend Pong Chu's books (there are identical Verilog and VHDL versions) though they're expensive and I don't love absolutely everything about them.

author: glatocha
author_rank: Regular Contributor
timestamp: May 27, 2013, 01:57:44 am
content: I found yesterday this course recorded. I didn't watch it yet, but maybe worth to give it a try

author: nctnico
author_rank: Super Contributor
timestamp: May 27, 2013, 09:32:39 am
content: Quote from: joelby on May 27, 2013, 01:02:26 amBad mistake. VHDL is a full blown programming language where Verilog is a netlist format. If you are used to using the full potential of VHDL then switching to Verilog will be a cold shower.

author: vvanders
author_rank: Regular Contributor
timestamp: May 27, 2013, 04:47:42 pm
content: Bring on the holy wars!As far as a decent Verilog reference I foundthisPDF via fpga4fun to be pretty good with a nice heavy emphasis on synthesis.

author: fpga
author_rank: Regular Contributor
timestamp: May 29, 2013, 03:01:12 am
content: Quote from: nctnico on May 27, 2013, 09:32:39 amThis reminds me of the days that people were comparing Pascal with C, then shortly later Modula with C++. Since C and C++ permit accessing memory contents directly via pointers, they were declared as very low level languages, not suitable for high level software development. I wonder how many Modula programmers are gainfully employed today? If it weren't for Borland Delphi, Pascal would be history too.Modern versions of both VHDL and Verilog / SystemVerilog, can each do everything that the other can do. Just a quick search of who uses what -- ARM, Infineon, and NXP use VHDL, Intel, AMD, Broadcom, Qualcom, and Cisco use Verilog or SystemVerilog. So clearly either language can be used to get the job done.The major difference that others in this blog have so very well pointed out is that VHDL is a very strict language that forces you to code in a certain way. Verilog, on the other hand, offers freedom of expression -- it doesn't care how you code, kind of like C and C++ for programming.One fallacy is to rely on the language semantics as a guarantee of good code. Simply choosing to use VHDL will not assure that your design is correctly implemented. The very strict type enforcement and the duplication via declaration and definition may help catch novice bugs, but in practice such bugs are easy to spot by an experienced engineer, but the extra code overhead will bury and obscure the complex bugs.In my opinion, the language that permits expressing one's intent in the most elegant, readable and concise form is the clear winner.From what I've seen SystemVerilog is the language that has everything worth keeping and has the highest level of adoption today. This is not to say that VHDL is going away any time soon, but more and more complex designs using VHDL will be mixed language with some IP in Verilog or SystemVerilog. A decade ago, Xilinx IP was mostly all VHDL, but today much of the newer IP is in Verilog while the older IP is in VHDL. As a result, complex Xilinx designs today are mixed language, granted that you only need to know one of the languages to implement your designs.So finding fault in one language over the other is purely religious. If you have a choice, then the best one is always the one that most closely aligns with you philosophy, otherwise, it's the language that your employer has chosen for you.

author: glatocha
author_rank: Regular Contributor
timestamp: May 29, 2013, 07:19:20 am
content: Yeah I think generally it will go down to what book I will get and in which language is the demo software for my board written, so you can take a look and copy some parts.Another thing, I checked out the Xilinx ISE and there is a function that you can simply draw the schematic. Use standard gates or the 74 chips series.Is this used at all in the industry? I think for some simple decoding or some registers it is fast and convenient.

author: joelby
author_rank: Frequent Contributor
timestamp: May 29, 2013, 07:27:32 am
content: Basically, no. Schematic capture is not very well supported in the latest releases of ISE, and as far as I can tell nobody uses it seriously except for supporting legacy designs.Well-structured HDL is much quicker to write and easier to comprehend and test.

author: MacAttak
author_rank: Unknown
timestamp: May 30, 2013, 12:44:42 am
content: Even just going through the basic stopwatch tutorial for ISE that covers schematic capture alongside VHDL and Verilog, I walked away thinking "who in their right mind wouldchooseto use schematic capture for this?". As a tool, it just didn't really seem to fit the purpose.Both VHDL and Verilog are significantly easier to understand than schematic (once you start digging below the very topmost layers of a design). At least for me (and take that with a grain of salt, because I'm far from a professional with these tools). That may be because I come from a programming background - text is often easier to grok than drawings for complex systems.And I think the modern toolchains don't really care - they will let you use whichever you prefer. At least ISE does... I don't have experience with the others but presume they all do.

author: c4757p
author_rank: Super Contributor
timestamp: May 30, 2013, 12:52:01 am
content: Quote from: joelby on May 29, 2013, 07:27:32 amI implemented an entire CPU in the ISE 14 schematic capture last semester for my intro Digital Logic Design course term project. (We were required to use schematic capture, god knows why, and I wanted to do a CPU.) Not very well supported how?

author: joelby
author_rank: Frequent Contributor
timestamp: May 30, 2013, 01:22:09 am
content: Quote from: c4757p on May 30, 2013, 12:52:01 amFrom memory, some of the primitives supported by newer FPGA families are missing, the tool hasn't been updated in years, and I don't think traditional schematic capture is supported in Vivado at all (but don't quote me on that).

author: c4757p
author_rank: Super Contributor
timestamp: May 30, 2013, 01:24:22 am
content: Ah. I wasn't doing anything on a newer FPGA, so I didn't know that. The only bad impression I got from it is that the capture system itself was shitty, but by the end of fourteen pages or so of schematics I was even getting used to that steaming turd.

author: nctnico
author_rank: Super Contributor
timestamp: May 30, 2013, 01:01:48 pm
content: Quote from: fpga on May 29, 2013, 03:01:12 amThe catch is that the old school Verilog is no match for VHDL if you know how to use VHDL to its maximum potential. I'm not saying VHDL is the best language there will ever be for FPGA or logic design in general. If you have tomake dowith what you have available (Verilog or VHDL) I'd recommend VHDL.Now SystemVerilog is a whole different beast. I must admit I've never looked into it but from what I've read so far it has all the advanced features of VHDL without the obfustigated syntax. So it makes sense to try SystemVerilog first if the tools support it.

author: fpga
author_rank: Regular Contributor
timestamp: June 01, 2013, 04:54:58 am
content: Quote from: nctnico on May 30, 2013, 01:01:48 pmFirst of all, if you are going to draw a comparison, make sure you are comparing the items from the same time era; don't compare modern VHDL with Verilog from the early 90's. There's nothing old school with today's Verilog. In fact, VHDL is older than Verilog. Second, make sure you have knowledge of what you are comparing. Both languages are used very successfully today by very successful companies. Neither is deficient in implementing complex circuits such the microprocessors in your PC, Mac, or iPhone. The differences lie elsewhere. For a quick feel of what the languages are like, look them up on Wikipedia.If you are just starting out learning digital design, my suggestion is to do all three -- implement in VHDL, Verilog, and in schematics. Then build the design on your chosen FPGA and test it out. Also learn how to write a testbench and use a simulator. If this becomes your career, you will be far better off if you are well versed in both VHDL and Verilog. You will quickly see that doing anything of any complexity becomes very tedious in schematics. Schematics are best for board design. But make sure that you are able to represent simple clocked circuits and boolean expressions in schematics since this is what will be asked during interviews.If you are choosing a language as a career choice, search through the job listings of companies you are interested in working for. Often they specify or strongly hint which language they are using.Finally, SystemVerilog is a superset of Verilog much like C++ is a superset of C. Most of the object oriented stuff in SystemVerilog applies only to simulation testbenches and the synthesizeable subset is basically Verilog.

author: marshallh
author_rank: Unknown
timestamp: June 01, 2013, 07:19:52 am
content: Just keep in mind that for all his fpga advice, he has only written a counter...And I hope he doesn't stop posting, because that would deprive another fpga discussion channel some much needed comedy

author: glatocha
author_rank: Regular Contributor
timestamp: June 01, 2013, 10:10:51 am
content: thank you guys for contributing in this topic. Interesting opinions.New question:What is the smallest pin count FPGA on the market. I only find TQFP144. A little unfriendly startup.And can anyone list known FPGAs with internal configuration memory:- Xilinx Spartan - 3AN- Latice XP2- Actel Fusion, ProASCI3, IglooIs any of new Xilinx non volatile?Is any Altera option or other producers?

author: nctnico
author_rank: Super Contributor
timestamp: June 01, 2013, 12:22:22 pm
content: Quote from: fpga on June 01, 2013, 04:54:58 amThis is turning into a semantic discussion. What I'm saying is that if the tools support SystemVerilog then use that. If not then use VHDL. I have no idea which tools the OP may end up with. Maybe its some old commercial software package bought 10 years ago.@marshallh: I typed that the first thing I ever made on a CPLD was a counter. In the 20 years after that I have developed lots of complicated CPLD and FPGA designs.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: June 01, 2013, 01:25:20 pm
content: Quote from: glatocha on June 01, 2013, 10:10:51 amThere is a huge unexplained gap in FPGA pin counts. There are some 32 pin QFNs (Lattice XO2, and I think Ice40) , and also 25 ball WLCSP and 64BGA in teh XO2 range, but pretty much nothing from the major players until you get to 100 pin. I suspect it may have originated from die sizes on early devices, but seems pretty ridiculous nowadays.I thing Microsemi have some smaller packages.Lattice XO2 has internal config (and core regulator if you want) - although the XO series started off as basically CPLD, the upper end XO2's are much more like FPGAs than CPLDs

author: mrflibble
author_rank: Super Contributor
timestamp: June 01, 2013, 01:42:24 pm
content: Quote from: glatocha on June 01, 2013, 10:10:51 amThat was what I was thinking.QuoteIf you don't mind QFN's there's the AGL030 in a QFN-48 package. The ICE40 also has some low pincount devices, although if you want lower than 48 ... then it's a 36 ball bga device. Which is probably more unfriendly than the TQFP144.The TQFP144 might actually end up being easier than the QFN though. As in easier to route out all the connections, assuming you don't need all the IO's. That, and you actually see the pins so reworking a little mistake is going to be easier than QFN. There's also some VQPF100's in the Igloo & ICE40 series.Is suspect that if you want smallest number of "pins" then you'll end up with bga. If you want something where you can still see the pins for easy mucking about then it's going to be TQFP/VQFN 100 pins or more.Quote from: mikeselectricstuff on June 01, 2013, 01:25:20 pmWhich ICE40 is in QFN-32? I vaguely recall the smallest being one of those double row bigger QFN's (80-ish pins) when I went over the list, but I could very well be wrong.*checks datasheet* Ah, you're right. The LP384 is indeed in QFN-32. I guess I immediately forgot about that one again because it doesn't have a PLL.So if glatocha doesn't mind QFN and doesn't require a PLL then that might be a nice option.

author: gregariz
author_rank: Frequent Contributor
timestamp: June 04, 2013, 07:47:52 pm
content: Quote from: chickenHeadKnob on May 07, 2013, 12:12:05 amI have the Papilio board.. yes its Xilinx but the parts are easy to get if you are doing your own thing. The upside with the Papilio board is the free tutorial book (VHDL) by Mike Field that seems pretty good if you are starting out. You'd probably want the logic start board as well though. Its an alternative to the Digilent Basys board although its a bit cheaper. I ended up getting the arcade board and turning it into a Galaga game console when I finished with it.Depending on what you want to do it may be easier and cheaper to work with a small CPLD if you don't need the logic space but still want to learn VHDL.

author: mrflibble
author_rank: Super Contributor
timestamp: June 04, 2013, 08:18:53 pm
content: Quote from: gregariz on June 04, 2013, 07:47:52 pmIt indeed depends on what you want. If you are really new to this and don't know what you don't know, and also don't know precisely what you're going to do as a first project ... best get an fpga board instead of cpld. With a CPLD you run out of flip-flops real quick. For some things that's no biggie, but if the moment you want to do something that requires a reasonable amount of memory ... *poof* ran out of FFs.Case in point, I started out on a cpld board (Altera MAX 3000A). And while it was perfectly good to learn all sorts of thing regarding programmable logic, some things I would have liked to do just weren't going to fit.So I'd suggest that if you don't know exactly what type of design you're going to try out first, get a fpga board since it's a bit more versatile in the type of design you can try. Besides, with modern fpga's you also get all sorts of extra goodies like PLL/DCM to generate clocks, which also can be quite handy.

author: nctnico
author_rank: Super Contributor
timestamp: June 04, 2013, 11:25:24 pm
content: Quote from: mrflibble on June 04, 2013, 08:18:53 pmYou can always use an external SRAM. I did several CRT/DSTN to TFT conversion designs using a Xilinx XC9500XL CPLD. The image is kept in the SRAM and displayed onto the TFT screen.

author: legacy
author_rank: Super Contributor
timestamp: June 04, 2013, 11:34:27 pm
content: Quote from: marshallh on May 07, 2013, 12:53:00 amWhy Xilinx is so bad ?

author: mrflibble
author_rank: Super Contributor
timestamp: June 05, 2013, 01:08:05 am
content: Quote from: nctnico on June 04, 2013, 11:25:24 pmAnd I did several <fill_in_stuff_here> on a coolrunner II. That doesn't change the fact that cpld's typically have a low storage element to combinational logic ratio. Which is fine for some things, but not for others. The display controller scenario is where you can stream in your data, and then only need a limited amount of internal (cpld/fpga) to do the actual processing. My point is that as soon as you need more than a few FFs to simultaneously hold data so you can actually do processing on it, with the cpld you are boned.

author: Hardcorefs
author_rank: Regular Contributor
timestamp: June 05, 2013, 01:13:28 am
content: Quote from: legacy on June 04, 2013, 11:34:27 pmIf I was being vindictive I would say the tools are programmed by morons.....All the underlying tools are actually command line programs that have seen better days, that in itself should be a warning for ANY shell based GUI.After all how can the GUI get to the fundamental data needed to correctly control the process, without having to parse a shit load of CR/LF terminated crap.To round out these overly expensive tools they have built the GUI out of java, don't get me wrong... java is excellent I use it myself in a BIG way....However in the hands of a 'mad-man- C++ programmer it is a disaster, specifically , creating and removing 'objects' in java is VERY expensive.So you have a GUI that calls "Subroutines" (subroutines are good.... they allow code reuse), unfortunately the idiots over at xilinx, decide to 'create' a lot of NEW object inside these subroutines, then don't properly release them... and so memory leaks and GC events breed faster than roaches... (just fire up the java debugger when their front end is running.....and watch the upward sawtooth GC)That is just on the technical side.....On the VHDL side, WHY O WHY in this day and age to I have to repeatedly COMPILE from scratch, even if I add a blank line?Because the idiots take the timestamp as being the deciding factor if the VHDL has changed, and when you are on a 16 HR compile time it is no joke....WHY can I not have VHDL that compiles into small modules (like it does NATURALLY), then be able to DRAG & DROP PRE compiled logic sections to be linked together.If I have a UART that communicates at 19200 with the outside world but stores the shit in memory.. do I really give a rats ass if the link between the UART and the memory cannot function at the "global" clock timing of 5-10ns.. no... but WTF do i then have to get my "magic" book out and start typing Martian.. so as to enter a timing constraint to tell the compiler I don't give a rats ass....WHY can I not use D&D then have a parameter between the logic links doing this....." Hay pls link my 500MHZ memory module with my 100Mhz Uart ... using this netlist with the timing link at ~10MHZ""I would prefer if the memory module sit in subsection A and the UART sits in subsection B" using these external pins...."Next up......Plan Ahead........(for your early stressed out retirement)This allows you to set "different" compiler options to fine the BEST route/ timing, but..... lets say you find a design that compiles at 120MHZ, but the timing says "shit, i can get this upto 150MHZ"So you reset your DCM inputs to use the new clock speed and run plan ahead.........BAM YOU ARE DEAD,Plan ahead has NO source control......., so unless you are a genius that can remember EVERY change you made.... you cannot quickly roll back to a previous design... even if it is a single line change such as:CLKFX_MULTIPLY => 12, -- Can be any integer from 2 to 32toCLKFX_MULTIPLY => 15, -- Can be any integer from 2 to 32AND just to make your life REAL difficult... because you changed a SINGLE VHDL statement , EVERYTHING has to be re-compiled... even un-associated modules. (yep i know I can drop down to the command line with my martian incantations and patch bits of files together using TCL, but WhereTF is the source control and a record of what I did to achieve the design)WTF can they not integrate GIT into the JAVA GUI?All this and more can be yours for $5,000 per seat....Final handy tip....Reboot your computer BEFORE running a long compile... it can fails silently halfway through...I.ENo reboot>20hours no result... java crashes silently with out of memory... only Java debugger can spotreboot4hours fully compiled....

author: glatocha
author_rank: Regular Contributor
timestamp: June 05, 2013, 02:58:39 am
content: hmm,you wrote this about ISE or Vivado.How does the Altera and Lattice in comparison?

author: legacy
author_rank: Super Contributor
timestamp: June 05, 2013, 08:12:35 am
content: @Hardcorefsabout this issueQuotewhat about Altera ?

author: nuhamind2
author_rank: Regular Contributor
timestamp: June 05, 2013, 11:10:10 am
content: I choose Altera just because the avalaibility of cheap board and programmer from ebay.

author: nctnico
author_rank: Super Contributor
timestamp: June 05, 2013, 12:36:00 pm
content: Quote from: legacy on June 04, 2013, 11:34:27 pmJust ignore. Every tool has a learning curve and it takes time to understand the principles that are behind it. I get along with ISE just fine but I have been using it for almost a decade. If you are new to it then it is wise to follow some tutorials and watch some videos.

author: legacy
author_rank: Super Contributor
timestamp: June 05, 2013, 02:02:55 pm
content: I am toying with Linux & ISE v10, original Xilinx Usb-Jtag-v1my target fpga is Xilinx-Spartan3E-100 and S3E-500so a very little fpga devices, the S3E-500 is ~ 2K LE!I am coding around a m6809 softcore with just few devices:- 2 uart, fix baud rate @9600bps (the first is for the Noice-6809's talker)- 2Kbyte prom (with Noice's Talker inside)- 30Kbyte of ram- CGA video array, 1bit color, to drive an old fashion CGA tube at 320x200x1- HD40780,4bit databus,3.3VNo great issues with Linux/Ise v10

author: Hardcorefs
author_rank: Regular Contributor
timestamp: June 07, 2013, 10:12:18 am
content: Quote from: legacy on June 05, 2013, 08:12:35 amAltera Is better in some respects....

author: fpga
author_rank: Regular Contributor
timestamp: June 12, 2013, 03:43:55 am
content: Xilinx is the biggest of all of the FPGA vendors in terms of market share, numbers of devices, numbers of cores, etc. However, their GUI tools are basically java IDE that create TCL scripts (make files) to run the command line tools in the background. If your design builds cleanly without issues, then no problem. But if for some reason it doesn't build, or you are doing something that exposes one of their bugs, then you need to waste a lot of time digging through the various log files with misleading messages and 1000's of pages of PDF documentation to find out what's going on. The devices and IP are very capable, but it can sometimes be very frustrating for no good reason.Altera, the second largest FPGA vendor, is significantly smaller in terms of market share. Their tools are far better designed and a pleasure to use. Altera's approach to IP is different from Xilinx where Altera integrates a lot of externally source IP along with their own. I'd say that their IP is often more refined, but the selection is smaller. Also in terms of devices, their focus is more on the mid-range. Xilinx has much broader choice of FPGAs in terms of price and capacity than Altera.Lattice is third. They have a good selection of non-volatile FPGAs and a lot of low end FPGAs, but in the mid to high end, they just can't compete with Xilinx and Altera. Also their IP tends to be much simpler, but on the plus side, they have made a lot of their IP open source. Their tools are mostly a collection of licensed 3rd party tools some of which are better than Xilinx and Altera, but they are not as well integrated. Also, since the 3rd party tools are limited versions, some capabilities are purposely limited unless you directly license those tools from the individual vendors.Lattice also has the iCE40 family of tiny non-volatile, super low power FPGAs from their acquisition of SiliconBlue. This is probably the interesting offer they have since no-one else has anything like it. However, the devices, IP, tools are totally different from Lattice's other devices.MicroSemi (Actel) is the fourth vendor. All of their devices are non-volatile flash based. They have some interesting SoC devices with ARM Cortex-M3 cores as well as small low power devices. They claim their flash based devices are less prone to single event upsets and so more suitable for aircraft, nuclear, and satellite use. However, their devices tend to be significantly more expensive then the other vendors.The rest 1% of the FPGA market are either up for acquisition by the larger players or fill very niche markets.Given a choice, I'd favor Altera due to far less senseless frustration, but Xilinx is what 8 out of 10 clients ask for. I'd consider Lattice and Actel only if their devices offer a better match for a particular application than Altera or Xilinx.If you are starting out, don't get too particular about the sizes, packaging, and cost of the actual devices. Find a good, well supported, development board with a good size device and all of the interfaces you care for. Once you have done several working designs on that development board, then you'd have a much clearer picture of how to select a device for your own board.

author: TerminalJack505
author_rank: Super Contributor
timestamp: June 12, 2013, 04:09:35 am
content: My pet peeve about the Xilinx development tools is all thecrapthey stick in your project folder. For the love of Pete! Put all that stuff in a subdirectory or something! All I really want to see in a project folder is the source files. Yes, I know that other stuff is needed but I don't want it to pollute the project folder.

author: fpga
author_rank: Regular Contributor
timestamp: June 12, 2013, 05:23:11 am
content: Quote from: TerminalJack505 on June 12, 2013, 04:09:35 amActually its not too difficult to have the Xilinx tools put all their stuff in a build directory separate from the source. Having a separate source, along with separate coregen, constraints, and sim directories makes version control much easier and cleaner. The more recent version permits referencing source files rather than copying them into the "project" aka build directory. I also do this to target different FPGA sizes or packages with one common source.