uc3842 power supply - Page 1
Forum section: electronics / beginners

author: epaelectronic
author_rank: Contributor
timestamp: February 21, 2021, 04:47:52 pm
content: Hello.I want to design a smps with uc3842 switching controller.It's supposed to have 24v input and 70v 1.2A output and a working frequency of 100khz.I built up a circuit in LTspice using the LT1242 which I believe is similar to the uc3842.I have achieved around 70v output in the simulation but there are some weird things going on.First, when I begin the simulation, the switching mosfet pulses 100 amp currents trough it for about 1ms.And after kind of stabilizing it has these very short peaks which are odd. (Attachment Blue is current at switching mosfet and green is output voltage)I tried all sorts of soft start circuits shown in the datasheets on the COMP pin.The circuits worked somewhat at reducing the startup current spikes, but all of the circuits causedlarge output voltage swings and even weirder mosfet switching behavior.Also the current going trough the power mosfet is saw tooth shaped. Does it mean the mosfet istaking too long to fully conduct?I calculated that the output capacitor should be 11.2 microfarads. With just one output capacitor the voltagehas around 800mv ripple. If I place for example one 120uf cap at the output in addition, the ripple is just 60mv.Yet I have read that parallel capacitors with differing values etc shouldn't be used directly on the output as the output capacitor is for some feedback purpose.Should I have a bulk cap directly on the output after the calculated capacitor?And in general are there any improvements I could make? Am I missing something crucial? How can I reduce the voltage ripple happening at the output?Am I using wrong component values somewhere like the current sensing?

author: epaelectronic
author_rank: Contributor
timestamp: February 21, 2021, 06:59:39 pm
content: Update:I got rid of the spikes in the stable mode and with a different value inductor and a larger 250uf cap, the output ripple is now 30mv.I wonder if it is going to cause problems not using the calculated feedback cap.Still have the high startup current spikes though.

author: epaelectronic
author_rank: Contributor
timestamp: February 21, 2021, 08:04:48 pm
content: Update:I got the startup spikes almost resolved by using a different kind of soft start circuit.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 21, 2021, 11:30:30 pm
content: Three things:1. Notice the voltage swing during the first 100us. Notice the circuit layout besides the transistor and controller. This is the startup transient, completely apart from anything under your control. Inductor current is very high (a peak of approx. +V / sqrt(L1 / (C4 + C5))), and any attempt to switch during this transient will result in those currents being shunted through the transistor. The controller will detect this and generate runt pulses (contingent on internal delay time, and R2*C1), but the switching loss may still be very high.If inductor saturation were modeled, this would be even more exaggerated: inductance drops at high current, accelerating the rising slope and increasing peak current even more. On the upside, the transistor would be "testing" that current for only a few cycles, rather than a dozen.2. Do any components have a default parasitic parameter entered -- inductors with capacitance or resistance, capacitors with resistance or inductance? This will affect efficiency and output ripple.Also, you may find it's more beneficial to use film capacitors than electrolytics. These have different parameters, you may be able to find representative SPICE models for them -- the downside is, film capacitors are larger and more expensive.Also, larger C4+C5 worsens the startup transient, so there's that, too.3. Don't use the gain-limiting feedback network, R6 || C3. Connect them in series, instead (and adjust values until the output step response is as desired). The difference is, the output voltage will vary some with load (poor output regulation) as shown. Because V(COMP) is, essentially, how hard it's working, the throttle. If some of that voltage is put into the feedback node, well, the feedback voltage depends on throttle, so the output voltage depends on output current. Simple as that. With them in series, the capacitor means they can only have this effect momentarily -- i.e. at AC, as is needed for control stability.You may find it's helpful to set initial voltages, so the entire startup sequence doesn't have to be simulated every time. This is either a node property, or set inside C4 and C5.Tim

author: epaelectronic
author_rank: Contributor
timestamp: February 22, 2021, 12:25:16 pm
content: The comp network is in series now. I also added all the parameters to every component.Now the output voltage is going crazy. I tried adjusting the comp values but nothing seemed to help.Any ideas?

author: xavier60
author_rank: Super Contributor
timestamp: February 22, 2021, 02:18:26 pm
content: C3 is too small. Experiment with larger values.

author: epaelectronic
author_rank: Contributor
timestamp: February 22, 2021, 03:23:43 pm
content: I tried many capacitance's up to 1uf. The output voltage seemed similar with most values, but with a few values for example 0.009uf it began doing some sort of swinging.

author: epaelectronic
author_rank: Contributor
timestamp: February 22, 2021, 03:37:32 pm
content: All of the voltage spikes have a frequency of around 140Mhz if that's any help.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 22, 2021, 04:45:24 pm
content: Is that coincident with turn-on? If so, that is most likely D1 capacitance resonating with M1+D1+C5 loop inductance, which if D1 is around 50pF, evidently that loop is around 26nH.Again, did you enter parasitics, or what? LTSpice hides them by default, so I have to ask...Tim

author: epaelectronic
author_rank: Contributor
timestamp: February 22, 2021, 05:05:23 pm
content: What I did was just adding series resistances and the other values on all the components. If parasitic values are hidden then I don't know.

author: epaelectronic
author_rank: Contributor
timestamp: February 22, 2021, 05:15:05 pm
content: Also yes, the spike is coincidental with turn on.

author: epaelectronic
author_rank: Contributor
timestamp: February 22, 2021, 07:12:21 pm
content: I added a low esr cap on the output. Now the worst spikes are gone but it still has 800mv ripple.What next? Do I fiddle around with the feedback?

author: nicknails
author_rank: Regular Contributor
timestamp: February 23, 2021, 02:43:38 pm
content: I'm not super familiar with flybacks, but R9 seems large to me. What does the switch waveform look like? I don't see a snubber, that could help if you have spikes during switching. I would also add a couple more ceramics on the output.

author: epaelectronic
author_rank: Contributor
timestamp: February 23, 2021, 03:55:30 pm
content: I've tried many different values on R9 to no avail.I added a slope compensation circuit from the datasheet that uses a npn. It seemed to remove weird switching behavior, wherethe lt1242 output slows down to 50khz and after going low immediately jumps back because of a current spike trough the sense resistor.I also tried snubbers at different positions but they sometimes made the problem worse. How do I know what values to use for snubbers?Currently the output voltage has a 1.6v peak to peak ringing.Are most of my problems caused by the ringing that's happening?pic 1 has output voltage pic 2 has output voltage (green) lt1242 output (blue) and current trough switching mosfet (red) and pic 3 shows howsometimes the lt1242 mosfet switching (blue) immediately jumps back up compared to the RT/CT clock (green) as the behavior seems to have a connection?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 23, 2021, 04:05:39 pm
content: Yeah, need slope comp to run in CCM.For some reason, almost every appnote claims the requirement is operation over 50% duty cycle -- but this is wrong, coincidental at best, as we generally design for nominal operation around 50% -- but we don't have to.Slope comp works down to a modest ripple fraction (i.e., inductor current pk-pk / inductor average current; not that DCM is >= 100% ripple), below which you really should reconsider choice of controller (average current mode) or inductor value (reduce to get closer to DCM).DCM isn't great at high power levels, as the inductor core loss is higher, and the bypass capacitors have to handle more ripple as well.Tim

author: epaelectronic
author_rank: Contributor
timestamp: February 23, 2021, 04:11:17 pm
content: Just noticed that inductor current goes to zero every cycle. Does this mean the converter is currently running DCM?If so how do I get it to run in CCM? CCM is preferable in my case right?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 23, 2021, 04:19:45 pm
content: Oh, remove C8 by the way, need bias current for that transistor to do anything.The last waveform looks to be CCM. That chaotic pattern of alternate, or seemingly random, pulse widths is characteristic of peak current mode control in CCM. Like I said, slope comp helps to a point, but you can't run very deep into CCM without severely compromising performance (like current limit accuracy).Preferable? I suppose. What are your motivations? Size, cost? Simplicity? Efficiency?Tim

author: epaelectronic
author_rank: Contributor
timestamp: February 23, 2021, 04:25:54 pm
content: I really don't have any motivations concerning this circuit. I would just like it to give out a nice stable 70v with max 100mv ripple.I'm pretty much lost on what I have to do next as by changing a value I always seem to make matters worse.

author: epaelectronic
author_rank: Contributor
timestamp: February 23, 2021, 04:33:37 pm
content: Maybe I should now concentrate on getting rid of the ringing?

author: epaelectronic
author_rank: Contributor
timestamp: February 23, 2021, 06:54:57 pm
content: It seems like it's running on CCM as the current trough the inductor never goes to zero.Also added a snubber after the inductor.I think the 4.5 Mhz ringing on the output is now gone (almost?).Still the spikes on the output voltage are 2v peak to peak. Is this now a question of adjusting the slope compensation, VFB compensation and current sense?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 24, 2021, 06:16:20 am
content: That's just switching ripple. Not control related.Again, high frequency ringing is caused by M1+D1+(C5+..) loop inductance resonating with diode or MOSFET capacitance. Check component models or strays.To test controls, set up a step load and observe the settling behavior. Time constants are usually in the ms range. The same response will also be relevant during startup, but that only illustrates a full throttle-to-quiescent step change, and in general you want to test rising and falling between several load values.Tim

author: epaelectronic
author_rank: Contributor
timestamp: February 24, 2021, 03:11:03 pm
content: Ok, high frequency ringing is caused by loop inductance resonating with diode or mosfet capacitance.But what can I do about it? Change the output capacitors? Change diode and mosfet to ones with less capacitance?How about reducing the 2v output ripple? Does reduction of switching ripple come with reduction of the resonations?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 24, 2021, 03:52:50 pm
content: Anywhere you have an RLC network, immediately think of the quantities:Fo = 1 / (2 pi sqrt(L C ))Zo = sqrt(L / C)Q = Zo / R (series resonant) or R / Zo (parallel resonant)If you want to dampen ringing, get Q down to or below 1.If you want to minimize peak voltages, reduce Zo.If you want to minimize peak currents, increase Zo.If you want to shorten the pulse, increase Fo. (Including making it shorter than any relevant harmonics generated by the circuit, in which case Zo and Q matter less and less, in proportion to the range Fo is above those harmonics.)Relevant harmonics correspond to the switching edge rate, whatever that is. You haven't posted a zoomed drain voltage or source current waveform, I don't know, you'll have to measure that.I don't see explicit parasitics on your schematic; apparently, some of your models have them built in. You'll have to check which, and by how much. Look up how to view model source or whatever, it should be a dialog somewhere, or in a library file (unless it's encrypted, in which case you can thank LT). Or at worst, set up a test jig and measure it.Conversely, anything you have, that isn't modeling parasitics, is probably erroneous. A rough estimate for stray inductance is 1nH per mm of trace or wire length. You'll need a rough or estimated layout to add these in.Applies to component body length just as well. So a long film capacitor does worse than a short ceramic chip capacitor; though the film cap probably has a larger value, so there's that, too.You can always increase capacitance or inductance, by placing components in parallel or series; you can never reduce them below the limits of the physical components, their dimensions and geometry. So, if thermal dissipation isn't a problem, PDSO-8 is better than DPAK is better than TO-220, for example.Output ripple is the rectified inductor current, dropped across the capacitors. Just use better ones -- lower ESR and ESL. Electrolytics tend to need to be rather large (100s uF?) to get low values; they're cheap enough that it's not a bad deal.If a single block of capacitors still isn't good enough (less than a volt pk-pk should be reasonable to achieve), just add an LC.And, what values? -- well what did we just learn about RLC circuits? In this case, the output filter values depend on how much load transient response you can tolerate. Roughly speaking, Zo equals Vpk / Ipk in the transient response. You need Fo somewhat lower than Fsw, by how much depends on requirements. You may find ESR is actually desirable here, because if the load is not a resistor (or not equal to Zo, in any case), it'll keep on ringing. ESR provides damping for the filter (keeps Q low), independent of load (well, for RL > Zo; for RL << Zo (a shorted load) it's a different case, but maybe not an important one, either).Tim