PWR up sequence for new design using ICE5LP4K  - Page 1
Forum section: electronics / general

author: hostile
author_rank: Contributor
timestamp: April 21, 2021, 06:06:19 pm
content: First time using the ICE5LP4K and trying to verify that my power on sequence is sufficient. I attached the sequence stated in data sheet, and my design snippets for retaliative sections. I see a lot of public design references do not have much in controlling this power up voltage levels, is it not really important or is there something I am missing ? I did use a voltage supervisor ( MIC803-26D4VC3 ) to make the 1V2 come up before the 3V3 by 1ms, but there isn't really anything controlling SPI_VCCIO, VPP_2V5, in that order, after VCC and before VCCIO0. This is a small board, and if it is needed can it be done with just RC circuit or can I just ignore it ? Small board and I am running out of room.

author: Evan.Cornell
author_rank: Regular Contributor
timestamp: April 22, 2021, 12:09:12 pm
content: I typically do this sort of thing by choosing DC-DC converters that have both EN and PGOOD pin. Sequence #1 PGOOD goes to EN of Sequence #2 converter. PGOOD usually goes high when VOUT >= 90-95% of set-point (check datasheet on this), which fulfills the sequence requirements you posted.

author: hostile
author_rank: Contributor
timestamp: April 22, 2021, 04:58:05 pm
content: Quote from: Evan.Cornell on April 22, 2021, 12:09:12 pmThe attached schematic has the use of EN from a dual DC to DC converter. I can not simply drive the one into the other because the lower 1V2 has to come up first and is not enough to drive the enable for the 3V3 side. So the added voltage monitor. What I need to know is that the datasheet specifies 4 different pins for the ordering up powering up, when I look at other designs I do not see anyone obeying this order. It is a real pain if I really have to add more timing for this powering on sequence

author: Evan.Cornell
author_rank: Regular Contributor
timestamp: April 22, 2021, 05:05:29 pm
content: Quote from: hostile on April 22, 2021, 04:58:05 pmAnd I'm saying you should choose a different DC-DC (either a single Dual DC-DC or two single DC-DC) that has ENand PGOOD(usually an open-drain signal pulled up to VIN, which takes care of the EN threshold), if you want to adhere strictly to the power up sequence in the spec sheet. You'd need confirmation from the vendor if you can violate the power-up sequence without issue... although that seems unlikely, since they wouldn't have listed a power-up sequence if it didn't matter.

author: hostile
author_rank: Contributor
timestamp: April 22, 2021, 07:43:29 pm
content: I am using the Dual, to follow the spec I need two duals or 4 singles, seems overkill to me. Using the dual channel regulator gets me the 1.2 for VCC before 3.3V SPI_VCCIO. I am using a diode in the attached schematic to get the 2.5V for VPP_SV5, so that comes up third as stated. Now just need to delay the 3.3V foVCCIO0/1. Thinking of using a FPF2000 type device. Going to play around a little in a simulator and see what it looks like. What a pain and it appears no one else is doing anything on public designs for this timing. I have seen a RC on one to that it delays the 3.3V, but I the datasheets also recommend against having ferrite beads or series resistance because of the fast changing currents on the deviceThat design also didn't meet the specification because all 3.3V are tied together.

author: hostile
author_rank: Contributor
timestamp: April 22, 2021, 09:11:16 pm
content: [ Specified attachment is not available ] [ Specified attachment is not available ]Quote from: hostile on April 22, 2021, 07:43:29 pmAfter paying attention I caught the wording on the 4 rule of power sequence. I apparently already doing all that is necessary. Messed me up because it was number 1, 2, 3, 4.