Quick question on level conversion and power sequence. - Page 1
Forum section: electronics / projects

author: Buriedcode
author_rank: Super Contributor
timestamp: July 05, 2016, 05:38:06 pm
content: I have far too many old ('95-'99) graphic LCD's without controllers so I'm using an FPGA to make a generic LCD controller with the final goal being a 'testbed' for, well testing them, as well as a large multi-panel display that more art (isn't it pretty) than useful. All controlld by one FPGA and perhaps a raspberry PI. Just so they get used.Whilst I've asked questions about FPGA's in the other part of the forum, I realised today that they are almost all 5V systems, with CMOS inputs, and my FPGA IO is 3.3V. No trouble there, I have some HCT series logic (573's, 245's, 541's etc..) being HCT they have true TTL inputs so will do the job. However, some of the panels have specific power up sequences - often 5V power for logic, then the drive voltage (~-23V) then the applied data/timing signals.So, given that most of the logic chips I'm using have output enables, would it be prudent to have the output's high Z until a signal from the controller? Or perhaps high-Z (from chip) with pulldown resistors, effectively making all logic outputs low until either a power-on delay, or a 'display on' signal? I'm thinking if I have to have a small level translator board for each display, might as well provide some form of global output enable so its not down to the FPGA do the work.My main worry is that, whilst testing the FPGA could be powered and putting out signals when no power is applied to the LCD displays, or the translator boards, so current could flow from the input protection diodes and possibly get to the outputs. I am probably worrying about nothing but if I'm going to make >10 of these, I guess it pays to make sure I have some extra protection there.Thoughts?

author: danadak
author_rank: Super Contributor
timestamp: July 05, 2016, 09:10:43 pm
content: The main issues in CMOS is not triggering the intrinsic parasitic SCRthat exists that can short the internal supply rails and in some casesblow out the die power bond wires. Or generate hot spots capableof melting the internal silicon at high current density spots.So observing power sequencing important.That being said some die now have specs on triggering current, so if youuse series R to limit it (not concerned about RC speed loss) thats oneway of partially getting around sequencing issues. But not ideal.Additionally not powering up parts properly can wind up drawing largecurrent when inputs linger in active region for an excessive amount of time.In critical battery operated stuff this can seriously degrade battery life.Or overload of regulators.....Also on this topic is ramp rates for power up. Some parts need minimumramp rate to wind up initializing properly, often in the tiny font notesburied at some point in specs.Regards, Dana.

author: Buriedcode
author_rank: Super Contributor
timestamp: July 05, 2016, 11:40:15 pm
content: Hmm so series resistors (fastest any line will go is about 4MHz) but should the inputs be held or, or High-Z ? With digital of course I always pull up/down, in this case pull down, but it seems the only way to do that with 'unknown' inputs, using one chip is to use output enable, and put pull-down resistors on the outputs. I have a terrible habit of over-complicating matters but as I said, if its a test-board the last thing it should do is risk damaging the displays