Routing 4 layer boards - Page 1
Forum section: electronics / general

author: Simon
author_rank: Unknown
timestamp: May 07, 2017, 08:06:05 am
content: I am trying to do my first 4 layer board in Proteus. This is proving to be a bit of a nightmare. Okay I’ll admit I have tried to make the auto router work and it does not seem to get it even though I have tried to specify routing pairs et cetera. The idea is to have the bottom layer as a ground plane and the top layer has mostly a ground plane carrying only power stuff that I manually route. Obviously the components all sit on the top layer as surface mount parts so they are going to need a via nearby and a short trace in order to get the connection into the middle pair of layers. I have also tried creating 2 types of via. One that goes through all 4 layers and one that goes from the top layer and only through the 2 internal layers. This via is not being used only the complete through-hole via is used. It also routes all over the top layer before trying to use the inner layers. Am I missing something significant or is the auto route the not really capable of doing for layers like this?I’m also at a loss as to how I would choose to use a specific via while I am manually routing. Or indeed how do I choose which layer I am going to switch to.

author: Simon
author_rank: Unknown
timestamp: May 07, 2017, 08:24:15 am
content: I am using PCB cart. As far as I am aware they do do blind and buried via types.I don't have any special requirements of the routing, there is nothing high-speed et cetera I'm simply trying to avoid EMC problems so am trying to keep anything that might be emitting inside the board.

author: Simon
author_rank: Unknown
timestamp: May 07, 2017, 08:36:04 am
content: Yes their prototyping does not do blind/buried, as it also has limitations on number of layers and copper weights. I suspect that prototype boards are made on standard setups so that they can get lots of peoples boards on one tool, if they offered all options it would become impossible to group anyones design or they would end up with an expensive process to cover a few designs but that also applies to designs that should be cheaper breaking the "prototype" model. On production orders you are payinf for the tool and are keeping ownership of it so I guess they do as you want and charge you for it. Adding one blind via put the price up by about 15%

author: mc172
author_rank: Frequent Contributor
timestamp: May 07, 2017, 09:31:20 am
content: Unless you're working up at around 6 GHz and beyond, fully stacked vias aren't going to radiate anything or be particularly susceptible to RF. Blind vias are incredibly expensive and completely unnecessary for 99% of the time that people use them. I routinely use fully stacked vias up to 3 GHz. I don't work above 3 GHz much but doubt it would start to become a problem until at least double that.If you are working up there in microwave voodoo land, you've got more to worry about than vias, such as the slot antenna formed by the thickness of the substrate material.

author: Simon
author_rank: Unknown
timestamp: May 07, 2017, 09:43:39 am
content: Well I'm not too fussed about blind via's its more about trying to understand how to use proteus, it supposedly chooses the shortest via but then is clearly not doing so. Going for faraday cage style routing cannot be done with the autorouter. I guess if I manually put a via next to each component and force all routing to be on the inner 2 layers this would work.

author: Simon
author_rank: Unknown
timestamp: May 07, 2017, 09:49:47 am
content: Quote from: mc172 on May 07, 2017, 09:31:20 amThis also depends on the class you are trying to pass. I have been told of an AVR held in reset failing EMC and all that would have been running would have been the clock inside the chip awaiting programming commands.

author: Rerouter
author_rank: Super Contributor
timestamp: May 07, 2017, 10:29:50 am
content: From what i can see by searching for it, the EMC issues with AVR's where primarily due to using a piezo susceptible ceramic capacitor on the reset line, and leaving inputs floating, failing around 1.3KV, while needing to pass 2KVOddly enough my searches turned up that the mega 128's SRAM does not clear on reset, atleast until VCC is below 0.3V, meaning part of the EMC susceptibility can be software related by not zeroing values after reset. I would assume this quirk would exist in similar models.

author: mc172
author_rank: Frequent Contributor
timestamp: May 07, 2017, 10:31:35 am
content: I appreciate that it doesn't help you use Proteus. Is the answer don't use the autorouter?

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 07, 2017, 12:45:20 pm
content: Do not even think of using an autorouter.More so if you are not experienced as you won't know how to set it up correctly. It will be a waste of time.Do not use blind or bured vias unless you absolutely need to - it adds cost and is not supported by most cheap services. Even where supported they tend to be only between the 2 inner layers due to the way the boards are made, which in practice isn't as useful as 1-2 and 3-4, which is a more expensive process.Chances are 6 layers with through vias will be a similar cost to 4L with blind/buried vias.On a 4L, one inner layer is usually dedicated to ground - either as a plane layer or a fill with a few tracks if necessary. In some cases you can get ground and post of power on one layer.If you have to get power to lots of places, or have high power or low inductance requirements, the second inner layer is typically used for power. Again either as a complete plane or most of it filled with odd tracks you can't fit on other layers.if you're very pushed for density (especially on through-hole PCBs) or need to maximise EMC performace, putting planes on the outer layers is sometimes done, but less so nowadays as you need the space for SMDs. It also makes PCBs basically impossible to track-hack.For a SMD layout you need the outer layer ( both if double sided) for parts so you shouldn't be relying on putting planes there.The "default" starting position would be inner layers for ground and power, and see how you get on from there. By all means add surface fills in unused areas when you're done, but to start with, work on the assumption that you won't be able to do that.And never forget the three most important things to get a good layout:PlacementPlacementPlacement

author: Simon
author_rank: Unknown
timestamp: May 07, 2017, 02:55:48 pm
content: Quote from: Rerouter on May 07, 2017, 10:29:50 amit all amounts to the same thing EMC wise, the processor would stop working when pulled into reset but even then what is going on, on the chip can cause it to fail an EMC

author: Simon
author_rank: Unknown
timestamp: May 07, 2017, 03:02:51 pm
content: Quote from: mikeselectricstuff on May 07, 2017, 12:45:20 pmA common practice these days for EMC is to use the outer layers as ground (I'm sure one could be power with no adverse effects) and run everything inside thus shielding it. Obviously you need a small trace on the part itself to go to a via very close by but after that it's all inside minimizing any length of trace that could act as a transmitter.For real sensitive stuff I'd be tempted to run a row of vias around the edges of the board whilst using both outer layers as ground. in my case I plan to be caging the whole board anyway so traces on the top layer are not a problem but I am also just messing with settings trying to learn how to use Proteus.Placement is indeed important and i spend a lot of time on it often using the auto router just to see how well I have done by eyeing up the complexity of the board layout. I generally undo it again and move stuff around and once happy I route power and sensitive stuff first then let the auto-router take care of what little is left.

author: hammy
author_rank: Unknown
timestamp: May 07, 2017, 03:58:26 pm
content: Quote from: Simon on May 07, 2017, 03:02:51 pmThere are four requirements:1. Decoupling2. EMC-Immission/-emission3. Signal-Integrity4. Self-InterferenceA layer-stackup like this:GND/SIGNAL/SIGNAL/GNDor:GND/SIGNAL/SIGNAL/VCCisn't effective for at least three of these four requirements.Decoupling: If VCC and GND are not on adjacent layers the capacetive effect is impossible by means.EMC: The VCC layer isn't next to a GND layer. One signal layer in this stack-up is not next to GND. VCC will radiate.Signal-Integrity: Bad if another Signal layer is between Signal and Gnd-Layer.Only boards with 6 or more layer can fulfill all requirements. 4 or less layer are always a compromise. A stack-up described above is the worst possibility.Consider something like SIGNAL/GND/VCC/SIGNAL or SIGNAL/GND/SIGNAL/VCC but - maybe it sounds strange - PCBs with GND and/or VCC on outer layers are never good regarding EMC. It is better to shield the board by edge plating.Cheershammy

author: Simon
author_rank: Unknown
timestamp: May 07, 2017, 04:09:16 pm
content: coming from a 2 layer board where you still would not have protection from self interference or signal integrity. All I am doing is putting a screen around an existing 2 layer PCB. EMC failures happen when traces that have no shielding carry varying currents/voltages usually with high speed swings. I'm not sure how GND-Signal-GND-Signal shields that outer signal layer and how having a ground plane under it stops it emitting other than the fact that the signal may go to ground rather than emit into free space. Obviously at the end of the day component leads are still exposed but I plan on shieldng the overall board anyway.

author: hammy
author_rank: Unknown
timestamp: May 07, 2017, 07:17:23 pm
content: Quote from: Simon on May 07, 2017, 04:09:16 pmBut what about board-thickness, prepreg, epsilon-r, return path and core? Have a look into thisdocumentor thisdocument.(There are more documents from EMC labs out there, a lot of research about this topic.)Don't think about GND-layers, think more about reference planes. Not only GND-planes offer a return path. You want to keep your signal close to their reference plane with a constant impedance. Also proper decoupling is needed.Something to think about: The idea about GND-layer on the outer layers of a PCB is nothing new. But in all these years, with all these smart guys out there, no one is doing this (*). Also in HS-design classes something like this is not taught.A PCB with SMT and GND-layer on the outside needs way more vias. This is not the best practice regarding density and signal integrity. If a signal changes reference plane it needs a path for it's return current nearby. With two GND-planes you can us a via connecting these two planes. With a GND-plane and a VCC-plane you need a capacitor and two via nearby. All not good regarding signal integrity and more board space.Anyway, theoretically two GND-planes on the outside could reduce EMC. But in reality it is not worth the effort because components on this GND-layer consume all space. If your layout and design is so bad regarding EMC-emission that you need the GND-layers on the outside, you made something wrong.What do books like "HS Design Black Magic" from Johnson and "Signal and Power Integrity" from Bogatin say about this? I'm not sure, but I don't remember they recommend this.Simon, give it a try. Why not? Nothing bad about trying new stuff. But be aware it is not best practice. And always ask yourself "What would Johnson or Bogatin do?" or "What was taught in this design-class?" or "Am I really smarter than all these guys out there?"No pun intended!*) Anyone?Edit: "OpAmps for everyone" chapter 17.2.3Quote

author: rob77
author_rank: Super Contributor
timestamp: May 07, 2017, 08:48:50 pm
content: Quote from: Simon on May 07, 2017, 03:02:51 pmand where you place you parts ?on a densely populated board you don't have too much (actually none at all ) surface for the shield... if you just want to have some shielded traces inside a PCB without any components , then a bunch of coaxes would do a better jobi would definitely listen to Mike and go for inner ground + power without blind vias

author: timb
author_rank: Super Contributor
timestamp: May 07, 2017, 11:10:07 pm
content: Yes, Signal + Ground + VCC + Signal is the way to go. I've done this on 4 layer boards running high speed clocks (1GHz) and and 1Gsps DACs without issue. You want a complete, unbroken ground plane and you can't get that with it on the top or bottom, because parts and traces break it up.Sometimes, if the board isn't too crowded, I'll do a copper pour on the top and bottom layers and then via stitch them into the inner ground plane. If done right and in the proper circumstances it can help EMC issues. (Note: That's not true in all cases, sometimes it can make things worse.)

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 08, 2017, 08:34:26 am
content: A solid ground plane in the middle is likely to do you more good overall than a broken one on the surface.

author: Kjelt
author_rank: Super Contributor
timestamp: May 08, 2017, 12:10:14 pm
content: Quote from: mikeselectricstuff on May 08, 2017, 08:34:26 am+1

author: Simon
author_rank: Unknown
timestamp: May 08, 2017, 03:32:06 pm
content: hm interesting, not sure which way to go, I and working at low frequencies in the few KHz range, my main reasoning was RFI shielding for some of the more stringent EMC standards.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 08, 2017, 03:38:32 pm
content: Quote from: Simon on May 08, 2017, 03:32:06 pmKeep it simple - start with power/gnd planes in the middle. This works just fine for the vast majority of cases. If that's not good enough, chances are you'll need external shielding anyway

author: Simon
author_rank: Unknown
timestamp: May 08, 2017, 03:40:36 pm
content: Well I have other plans for external shielding also.Sent from my Moto G (4) using Tapatalk

author: bktemp
author_rank: Super Contributor
timestamp: May 08, 2017, 04:40:40 pm
content: Quote from: Simon on May 07, 2017, 03:02:51 pmHere is a nice presentation on multilayer pcbs:http://www.kbl-circuits.com/Layer%20stack%20up.pdfPutting all traces in the inner layers does not make sense for a 4 layer pcb, but can be useful if you have 6 or more layers.Also putting most traces on the inner layers makes troubleshooting very difficult, because you can't probe the traces.

author: Neilm
author_rank: Super Contributor
timestamp: May 08, 2017, 06:11:17 pm
content: I have worked passing IEC61326 for years and have always gone signal-0V-Vcc-signal for a 4 layer board.There are a very good series of articals on PCB layout by Keith Armstrong look athttps://www.emcstandards.co.uk/You will have to log in, but I found his articles easy to understand and without all the transmisstion theory maths that some people insist on putting in articles on EMC.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: May 08, 2017, 07:40:15 pm
content: The only time I've seen a production 4L PCB with planes on the outside was on an extremely dense design on a large PCB, where it was done to prevent having to go to 6 layers - I think it was a predominantly through-hole design, so theer is more clearance between TH pins on inner layers than on the surface, as pads weren't needed on the inner layers..

author: Simon
author_rank: Unknown
timestamp: May 09, 2017, 09:23:24 am
content: Well I'm going with GND-signal-GND-signal + SMD, my board is layed out in functional blocks anywhere and many traces would take as much length if not more to bury than route directly.

author: tszaboo
author_rank: Super Contributor
timestamp: May 09, 2017, 10:14:48 am
content: Quote from: Simon on May 09, 2017, 09:23:24 amSo, you are not listening to us.

author: timb
author_rank: Super Contributor
timestamp: May 09, 2017, 10:50:39 am
content: Quote from: Simon on May 09, 2017, 09:23:24 amOP: "Hey guys, how should I blah blah blah?"Everyone: "X is the correct way to do it in your case, not Y."OP: Thanks guys, I'll go with Y!Everyone:

author: Simon
author_rank: Unknown
timestamp: May 09, 2017, 11:36:22 am
content: Quote from: NANDBlog on May 09, 2017, 10:14:48 amerr i am

author: Simon
author_rank: Unknown
timestamp: May 09, 2017, 12:07:07 pm
content: Quote from: timb on May 09, 2017, 10:50:39 am

author: timb
author_rank: Super Contributor
timestamp: May 09, 2017, 12:15:13 pm
content: Quote from: Simon on May 09, 2017, 12:07:07 pmYou said you're going with GND-Signal-GND-Signal (which wasn't even one of the recommended methods). Recommended was Signal-GND-Power-Signal (with short runs of signal being OK on the power plane if required).Anyway, I was just messing with you; your method will work, but is still non-ideal. You need to make sure you have *plenty* of via stitching between GND planes otherwise you'll end up with your two GND planes at different potentials, which wouldn't be good.

author: Simon
author_rank: Unknown
timestamp: May 09, 2017, 12:23:26 pm
content: I see the suggestion was power be a plane instead of two grounds, in that case it makes lots of sense to have a top plane for power There is only 5A in the board and with 2 TO220 packages with a ton of vias full of solder under their heatsinks that will be plenty.

author: noname4me
author_rank: Regular Contributor
timestamp: May 22, 2017, 05:45:17 pm
content: Please let us know how you get on at EMC testing.Sent from my SM-G935F using Tapatalk

author: Simon
author_rank: Unknown
timestamp: May 29, 2017, 08:49:25 pm
content: Well I spoke to the guy that suggested the idea to me and it's ground - signal - signal - power.

author: dmills
author_rank: Super Contributor
timestamp: June 07, 2017, 03:30:11 pm
content: So coupling between the two signal planes, and big loops for the current in the lower signal plane trying to return on the nearest plane which is power and needing to find a decoupling cap and making the thing a right `mare to debug then, also long vias adding inductance to your power connections?The thing to remember is that the significant fields in modern electronics are usually magnetic, not electric. This did not used to be the case back in the valve era when everything was high voltage and high impedance, but is very much the case these days.Both radiation efficiency and susceptibility to magnetic fields is largely driven by loop area, so having a reference plane that is both unbroken and **close** to your signal layer serves very much to minimise radiation, there is a reason almost everyone uses S-P-P-S for 4 layer.73 Dan.

author: Simon
author_rank: Unknown
timestamp: June 07, 2017, 05:10:43 pm
content: But if you have power traces that are negative and positive shifting the same current you can put then on top of each other, much as we use twisted wires in cable bundles to keep opposing conductors close.I'm in the middle of getting into ARM and learning circuit studio as I have given up on proteus.

author: Rerouter
author_rank: Super Contributor
timestamp: June 07, 2017, 11:38:05 pm
content: By having signals on the outside, all vias can be impedance compensated without stubs for high speed signals that traverse the outer layers.With signals in the middle any high speed nets need to be back drilled, which ends up expensive. Or your left with many stubs radiating noise

author: Simon
author_rank: Unknown
timestamp: June 09, 2017, 06:13:05 am
content: So your referring to tiny un-terminated spurs in the form of a via extension that does not make up part of the main path ? I expect at high frequencies that would be a problem. Well I am a long way off a redesign as I'm back to the drawing board anyway.

author: electrolust
author_rank: Unknown
timestamp: July 11, 2017, 06:53:57 pm
content: Quote from: Simon on May 07, 2017, 08:06:05 amThis is pretty simple. The configuration you are looking for is "drill spans", part of the layer stackup definition for your board.Quote from: Simon on June 07, 2017, 05:10:43 pmThat's unfortunate, as you've barely learnt how to use Proteus. I also gave up due to library frustrations, and took the plunge @ $500 for CS, but now I'm back to Proteus ...

author: Simon
author_rank: Unknown
timestamp: July 11, 2017, 07:06:32 pm
content: both programs have pros and cons, proteus is more stable and mature, but CS is actually intuitive enough to use without trying to use hopeless documentation.

author: electrolust
author_rank: Unknown
timestamp: July 11, 2017, 07:30:46 pm
content: I agree CS is more intuitive so to do simpler things you can get there quicker from ground zero. But you still have to learn it to do anything beyond "my first circuit". It's not fair to compare the first-pcb experience, you have to compare the 2 as if you are reasonably experienced with both packages. I hit 2 fatal bugs within my first hour of using CS. I've yet to find a fatal bug in Proteus. But what really kills CS for me is 1, the lack of win 10 high res (retina) display support. It makes many essential dialogs unusable -- either too small to read or too big to fit the screen. And 2, the complete lack of support.You aren't reviewing Proteus fairly if you're not willing to even read the documentation.

author: Simon
author_rank: Unknown
timestamp: July 11, 2017, 07:35:29 pm
content: I have used proteus for 1 year, more infact now and done a few designs in it two of which were manufactured. I don't find it easy to use and the documentation is not comprehensive and considering they seem to have gone to extreme lengths to complicate everything or find the weirdest way of doing it I have given up. Support is a big issue with CS and with proteus for £210 less you do get instant phone support and if they can reproduce a bug they will take it seriously I think.