FR4 high speed limitations  - Page 1
Forum section: electronics / general

author: joniengr081
author_rank: Regular Contributor
timestamp: April 17, 2023, 12:28:44 pm
content: Hi,We need to design a board having maximum frequency of digital signals around 2 GHz. It will be multilayer board using Zynq Ultrascale device and other components. Can we still use FR4 in the PCBs ? Up to which frequency and bandwidth (a function of rise time) can we use FR4 ?

author: dmills
author_rank: Super Contributor
timestamp: April 17, 2023, 12:57:05 pm
content: 2GHz? Is that a clock frequency or the highest harmonic?In the clock frequency case, it should be ok, but the eye will be getting a little fuzzy if you don't do everything to keep lengths down, in the harmonic case, meh, it will be fine.I have a design doing 12Gb/s serial on FR4, and it does just fine, granted we had an SI analysis done on it, and had I had to specify the orientation of the glass mat.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: April 17, 2023, 01:08:24 pm
content: There are some guidelines for stretching the capabilities of FR4. One of them is to not route copper tracks parallel to the weave of the glass. The glass fibers have a different dielectric constant then the epoxy, and when for example one wire of a differential pair is on top of a glass fiber, and the other is not, this will create an impedance mismatch. By routing the tracks a bit slanted, you avoid this situation. There may be more tricks for extending the reach for FR4, but I'm not really into high-speed design myself, and thus do not know much details.

author: joniengr081
author_rank: Regular Contributor
timestamp: April 17, 2023, 05:17:00 pm
content: Let me first get the concept of rise time, bandwidth, and firth harmonics in digital signal.If the signal frequency is 2 GHz then the rise time according to 10%-90% approximation is calculated below.Time period of 2 GHz signal is 0.5 nsecRise time = 0.5/10 nsec = 0.05 nsecThe Bandwidth = 0.35/Rise Time = 0.35/ 0.05 nsec = 7 GhzIs the Bandwidth calculated above is 5th harmonics ?

author: tggzzz
author_rank: Super Contributor
timestamp: April 17, 2023, 11:36:05 pm
content: Quote from: joniengr081 on April 17, 2023, 05:17:00 pmThere are some bits of that which are correct, but overall it is incorrect.For an intuitive overview and some measurements, seehttps://entertaininghacks.wordpress.com/2018/05/08/digital-signal-integrity-and-bandwidth-signals-risetime-is-important-period-is-irrelevant/

author: joniengr081
author_rank: Regular Contributor
timestamp: April 18, 2023, 06:58:46 am
content: I would actually like to know the minimum rise time and max clock frequency of the digital signal for which we can design the PCB layout using FR4.Regarding the signal bandwidth, the text book says that rise/fall time is more important then frequency/time period to calculate the bandwidth.If the rise time of a signal is 0.05 nsec then what is the bandwidth approximation, or the significant bandwidth that need to be consider.and is fifth harmonic is just clock frequency x 5 ?

author: joniengr081
author_rank: Regular Contributor
timestamp: April 18, 2023, 07:17:22 am
content: I think I get the relationship between rise time and the bandwidth.It's true that in practice, we cannot have zero rise time in digital signals. The digital waveforms in practice can be modeled as trapezoidal waveform corresponds to an approximation that relates the rise time of a signal to its bandwidth as:BW = 0.35/Rise TimeBy this definition if the rise time is 0.05 nsec than then the approximated bandwidth is 7 GHz.If the stack up in the PCB layout is correctly defined and it is impedance control then can we still use FR4 as dielectric ?

author: tggzzz
author_rank: Super Contributor
timestamp: April 18, 2023, 07:39:14 am
content: Quote from: joniengr081 on April 18, 2023, 07:17:22 amThat is the rule of thumb for oscilloscope front ends, but in some cases 0.45 is more appropriate.What you can get away with in your circuit will depend on how the receiverinterpretsan incoming waveform, the length of the tracks, crosstalk etc. There is no simple yes/no answer, unfortunately.For general information, google for EDN's "Bogotin rules of thumb", and there is a book "Right the First Time, A Practical Handbook on High Speed PCB and System Design" by Lee W. Ritchey.

author: nctnico
author_rank: Super Contributor
timestamp: April 18, 2023, 11:57:15 am
content: I'd check the application notes. A lot of modern day high speed signaling interfaces are optimized to stretch the limits of FR4.

author: joniengr081
author_rank: Regular Contributor
timestamp: April 18, 2023, 01:55:34 pm
content: The purpose of posting the question was to know the minimum rise time and max clock frequency of the digital signal for which we can design the PCB layout using FR4. In other words what are the limitations on PCB having FR4 as dielectric

author: Doctorandus_P
author_rank: Super Contributor
timestamp: April 18, 2023, 02:37:54 pm
content: As nctnico and I already wrote: There are no hard limits. It just gets progressively harder to maintain signal integrity. A "single frequency" is also a far too limited way to specify "FR4 capability". What sort of signals do you have? (LVDS, ECL like, analog ?) and over what distances do you need to run your signals? What other stuff is there around to eat into your noise margins? Bad PCB design can also wreck signal integrity at much lower frequencies.

author: asmi
author_rank: Super Contributor
timestamp: April 18, 2023, 05:23:52 pm
content: Yeah, it's not like there is a brick wall when it comes to the frequency. A lot depends on the nature of a signal, and also - how long the line is, if there are any layer changes, connectors, and other things which degrade signal integrity. For a practical example, as far as I know, PC motherboards with PCIE 4 are still using FR4 (16 Gbps), so you can go at least that high.