Very high slew rate logic gates - Page 1
Forum section: electronics / projects

author: Revky27
author_rank: Contributor
timestamp: July 05, 2023, 09:26:07 am
content: Hi,I am looking for a logic gate (prefferably AND) that has very fast slew rate and short propagation delay with CMOS architecture.Currently I was using ALVC and LVT families from TI but I was wondering if anyone knows any families that are faster.This is in order to avoid using any ECL/CML gates or having to use a very fast slew rate op-amp.

author: moffy
author_rank: Super Contributor
timestamp: July 05, 2023, 09:50:46 am
content: TI has a guide to all of its logic families speed and voltage:https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf?ts=1688545860499&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FSN74LVC1G97

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 05, 2023, 10:53:23 am
content: Have you tried wired-AND with diodes?Probably not applicable, but the falling-edge rate is as fast as either input can move. (Therisingedge, however, is not so much..!) Worth mentioning for completeness.Tim

author: dobsonr741
author_rank: Frequent Contributor
timestamp: July 05, 2023, 01:54:43 pm
content: Are you creating an “analog” square wave output to drive something? Asking as you speak from that perspective when mentioning slew rate. If so paralleled buffers are usual, from whichever logic family you choose from the TI selection guide. Alternatively, you can choose to build a push-pull driver with fast analog switches. If interested I’ll find the applicable Maxim app note.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: July 05, 2023, 07:04:32 pm
content: Maybe using a small FPGA or CPLD is an option.

author: madmac
author_rank: Contributor
timestamp: July 05, 2023, 07:21:06 pm
content: https://www.ibselectronics.biz/datasheet/potato/PO74G08A.pdf

author: PCB.Wiz
author_rank: Super Contributor
timestamp: July 05, 2023, 07:56:55 pm
content: Quote from: madmac on July 05, 2023, 07:21:06 pmInteresting parts, does the company still have a pulse ? Website fails to render ?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: July 05, 2023, 07:59:48 pm
content: Quote from: Revky27 on July 05, 2023, 09:26:07 amExactly how fast does thisneedto be ?As you will already see in the CMOS data, speed is very much a factor of loading, so smallest loads can give faster operation.

author: Marco
author_rank: Super Contributor
timestamp: July 05, 2023, 08:03:21 pm
content: UHS is the fastest common stuff.https://www.onsemi.com/pdf/datasheet/nc7sz08-d.pdf

author: PCB.Wiz
author_rank: Super Contributor
timestamp: July 05, 2023, 09:09:45 pm
content: Quote from: Marco on July 05, 2023, 08:03:21 pmThat's similar ballparks to Nexperia 74LVC1G08 : ~2.1ns < 4.5ns 50pF to 85'C, vs nc7sz08 < 5.5ns over temp and ~3.3ns < 5.2ns at 25'C 50pFNote the 50pF test case would be considered large for local load PCB designs.

author: coppice
author_rank: Super Contributor
timestamp: July 05, 2023, 09:39:45 pm
content: Quote from: PCB.Wiz on July 05, 2023, 07:56:55 pmhttp://www.potatosemi.com/takes me to their site. Its very basic. It always has been, but it still seems to be there.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: July 05, 2023, 10:05:32 pm
content: Quote from: coppice on July 05, 2023, 09:39:45 pmHmm, strange, a simple potatosemi.com seems to fail.

author: coppice
author_rank: Super Contributor
timestamp: July 05, 2023, 10:08:48 pm
content: Quote from: PCB.Wiz on July 05, 2023, 10:05:32 pmhttp://potatosemi.comworks for me.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 05, 2023, 10:09:29 pm
content: Ultra fast gates do not grow on trees.

author: coppice
author_rank: Super Contributor
timestamp: July 05, 2023, 10:10:47 pm
content: Quote from: SiliconWizard on July 05, 2023, 10:09:29 pmYou find the fastest gates in trees.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: July 05, 2023, 10:15:25 pm
content: Quote from: coppice on July 05, 2023, 10:08:48 pmMy browser did this for mehttps://potatosemi.comwhich fails here - simply blank.Their shop page also seems to no longer exist ?

author: dobsonr741
author_rank: Frequent Contributor
timestamp: July 06, 2023, 12:18:17 am
content: They don't do TLS - not cool. Tryhttp://potatosemi.comOr perhapshttps://potatochips.com

author: ArdWar
author_rank: Frequent Contributor
timestamp: July 06, 2023, 12:59:39 am
content: Quote from: madmac on July 05, 2023, 07:21:06 pmThey still exists?

author: David Hess
author_rank: Super Contributor
timestamp: July 06, 2023, 01:23:54 am
content: LVC running at 5 volts instead of 3.3 volts should be the fastest CMOS available. If you want something faster, then either use ECL/CML, or use the LVC output to drive the emitter of an NPN RF transistor to make your own discrete ECL output stage.That means that the simple method is to use a fast comparator. So what is wrong with that?

author: schmitt trigger
author_rank: Super Contributor
timestamp: July 06, 2023, 03:27:38 am
content: Quote from: SiliconWizard on July 05, 2023, 10:09:29 pmIndeed! Potatoes are actually a root.

author: ArdWar
author_rank: Frequent Contributor
timestamp: July 06, 2023, 03:30:04 am
content: Potatoes are actually stem tubers, not root.But yeah...Anyway, what's the actual use case here? It's rare that someone asks for slew rate in a logic gate. The dream logic gate is probably one with zero propagation delay but slowest slew rate possible within rate or input limit.

author: Revky27
author_rank: Contributor
timestamp: July 06, 2023, 08:09:23 am
content: Quote from: PCB.Wiz on July 05, 2023, 07:59:48 pmYes, I am using high impedance (maybe 1kOhm loading with a few tens of pF). This is more to see if there are any families that I missed.

author: Revky27
author_rank: Contributor
timestamp: July 06, 2023, 08:15:14 am
content: Quote from: dobsonr741 on July 05, 2023, 01:54:43 pmYes, I am basically using it as a very fast analog pulse generator as I can achieve faster transitions than with typical fast op-amps and comparators.If you're referring to APPLICATION NOTE 1866, I am familiar with this solution however it is too slow compared to a few paralleled gates digital gates.

author: rhb
author_rank: Super Contributor
timestamp: July 06, 2023, 12:55:01 pm
content: I attempted a similar project to generate a sub-nanosecond step to calibrate my Tek 465. I actually thought I had failed, but a few years ago I realized that the EE at work and I had not used a thru termination which lead to a lot of ringing and not the rise time I needed.After I got a 1.5 GHz LeCroy DDA-125 I came across it. When I tested it correctly I had about 1.5 ns rise and fall.If you want seriously high slew rates, check out the laser diode driver Leo Bodnar uses in his superb pulsers. 21 ps. That's about 1.5x slower than the internal calibrator in a Tek 11801.Have Fun!Reg

author: Revky27
author_rank: Contributor
timestamp: July 06, 2023, 01:51:47 pm
content: Quote from: rhb on July 06, 2023, 12:55:01 pmWhich leo bodnar pulser is this?

author: DavidAlfa
author_rank: Super Contributor
timestamp: July 06, 2023, 02:27:53 pm
content: http://www.leobodnar.com/shop/index.php?main_page=index&cPath=124https://physik.co-i60.com/2022/02/leo-bodnar-fast-risetime-pulse-generator/https://www.eevblog.com/forum/metrology/generating-a-lt3-ps-rise-time-step/50/

author: dobsonr741
author_rank: Frequent Contributor
timestamp: July 06, 2023, 03:05:03 pm
content: QuoteYes, that app note. It claimed 4nsec. How about 400ps by this TI part:https://www.ti.com/lit/ds/symlink/lmg1020.pdfor perhaps this for 25psec:http://ww1.microchip.com/downloads/en/DeviceDoc/SY88022AL.pdf

author: langwadt
author_rank: Super Contributor
timestamp: July 06, 2023, 03:14:13 pm
content: here's a plot of the falling and rising edge ibis data for a NC7SV74

author: David Hess
author_rank: Super Contributor
timestamp: July 07, 2023, 12:32:17 am
content: Quote from: ArdWar on July 06, 2023, 03:30:04 amThat is exactly the problem. For logic, slew rates are made as slow as possible to limit ground and power bounce.One reason the faster TTL logic families remained competitive with CMOS is that they have better controlled transition times. The performance of CMOS AC and later families, which should have been faster, was limited by package parasitics and corner ground and Vcc lead placement. FAST and AS had the same problem.Surface mount helps a lot here, as well as SOT-23 and smaller packages with individual gates. I would look for something like a 74LVC125 in a SOT-23 package and use that to drive the emitter of an NPN RF transistor. This allows for very clean switching at the collector which is isolated from the output of the logic gate by the common-base configuration. Old Tektronix reference level pulse generators use this method for very clean edges at 600 picoseconds and faster, but use a microwave schottky diode for isolation.

author: Revky27
author_rank: Contributor
timestamp: July 07, 2023, 06:35:33 am
content: Quote from: David Hess on July 07, 2023, 12:32:17 amI don't think that's right. Logic gates typically aim for fastest slew rate to allow for high speed and clean transitions because in logic you're not as much worried about ground bounce as you are about your logic output for example oscillating between 0/1 when its around its threshold voltage. Also faster slew rates give you more open eye diagrams. The comparators and amplififers are typically slew rate limited for stability hence why they have slower transition.

author: Revky27
author_rank: Contributor
timestamp: July 07, 2023, 06:49:56 am
content: Quote from: dobsonr741 on July 06, 2023, 03:05:03 pmThank you I am familiar with those parts. But they are not suitable I need specifically logic gates (XOR,NAND).

author: tggzzz
author_rank: Super Contributor
timestamp: July 07, 2023, 09:09:42 am
content: Quote from: Revky27 on July 07, 2023, 06:35:33 amIf the slew rate too fast and the current is too high, then ground bounce most definitely is a problem. Ground bounce will shift the on-chip voltages sufficiently that the gate inputs are no longer operating within the defined thresholds - and that cancauseoscillations.This kind of thing definitely caused problems in the mid-80s, especially with 8-bit bus buffers which had power pins in the worst possible place: opposite corners.You might like to do some simple Spice simulations: estimate the ground lead inductance (1nH/mm), crudely estimate the device output impedance (e.g. 10ohms), pick a load capacitance (e.g. 10pF), then have eight RC circuits plus the ground inductance driven by a voltage pulse with varying transition time. Obviously you won't see any oscillation, but you will be able to see how the chip's ground is lifted.

author: Revky27
author_rank: Contributor
timestamp: July 07, 2023, 09:26:44 am
content: Quote from: tggzzz on July 07, 2023, 09:09:42 amOkay but we are no longer in mid-80s. Nowadays a CMOS/TTL logic would not give you ground bounce provided you design your board correctly so that issue no longer applies. I understand you can get some if you drive very high currents very fast but I dont expect any 3.3/5V logic nowadays to have this issue with modern layout techniques.

author: tggzzz
author_rank: Super Contributor
timestamp: July 07, 2023, 10:37:01 am
content: Quote from: Revky27 on July 07, 2023, 09:26:44 amGiven that the problem arises inside the device where even a "perfect board" cannot affect effects, can you give some justification for your assertion? Simulations would be a good place to start.Don't forget that:in many cases gates are used to drive 50-80ohm transmission linesIBIS spice models are there for a reason: to help designers understand the consequences of chip packagesmany CMOS devices have programmable strengths, partly to reduce EMI, but also to contain ground bounce and crosstalk and similar effectsYou are of course right to note that things have changed in 40 years: they have gotfaster, which tends to make the problemsworse.