Running DDR2 below rated speed? - Page 1
Forum section: electronics / projects

author: petersanch
author_rank: Regular Contributor
timestamp: March 18, 2021, 11:32:42 am
content: Is it possible to run a SDRAM rated for DDR2-800 at lower speed than 400MHz reliably, for example 333MHz or 200MHz?Looking at part IS43DR16640C-25 as an example. Data sheet writesQuote.Does that mean that by adjusting CL in the FPGA memory controller that as low as DDR2-400 is supported?Cheers

author: Berni
author_rank: Super Contributor
timestamp: March 18, 2021, 11:43:34 am
content: You can run SDRAM slower no problem.This is just the best clock speeds you can get with the given timing settings. The RAM array inside has a certain latency to it, so once you start going at high clock speeds this latency becomes a problem, so more clock cycles need to be inserted to satisfy it the required delay before accessing data.If you are going to go even slower just pick the lowest available CL setting so that you don't have unnecessary latency and clock it as slow as you want.Tho the clock still has to be within reason since the chips probably use a lot of dynamic digital circuitry, so going below 1MHz would likely break something, while because its DDR means you still have very strict nanosecond level timing requirements on the pins, so you still need to use the proper DDR pins on a FPGA even if you are running it at a snails pace clock speed. But for non hardIP DDR RAM controllers the 400MHz indeed sounds like a pretty fast speed on a cheep pedestrian chip.

author: amyk
author_rank: Super Contributor
timestamp: March 18, 2021, 01:22:31 pm
content: Slower but within the same order of magnitude is no problem at all. On the other hand, if you want to goreallyslow, the refresh interval is likely to be the lower limit.

author: jziegler
author_rank: Newbie
timestamp: March 18, 2021, 04:43:15 pm
content: Yes, all DDR2 chips are backward compatible to the lowest DDR2 data rates. Adjust CAS latency as in the data sheet.When designing DDR2 / DDR3 into FPGA and embedded microcontroller systems, the controllers frequently will only handle around the minimum speeds for the standard. And as time moves on, only faster and faster memory parts are available.DDR2 can probably handle lower rates to a point. DDR3 specifically calls out 300MHz as the minimum allowed. I've never tried to go slower than that.

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 18, 2021, 06:22:44 pm
content: Yeah, the limiting point will be the refresh cycles. As long as your controller can ensure that the right number of refresh cycles are executed within the specified time interval, there should be no problem.Of course, since the required number of refresh cycles will be the same, the slower the clock, the more refresh cycles will affect overall data throughput. At some point, there won't be enough cycles left to issue any other command than auto refresh.

author: David Hess
author_rank: Super Contributor
timestamp: March 21, 2021, 04:54:34 am
content: Quote from: petersanch on March 18, 2021, 11:32:42 amIn addition to the above, there is nothing which prevents using a higher CL at lower frequencies; it will just mean higher access times. The CL specifications are the minimum at a given frequency.