Vds overshoot issue in half-bridge high speed topology - Page 1
Forum section: electronics / general

author: Xenom
author_rank: Newbie
timestamp: July 27, 2019, 04:24:53 pm
content: Hi guys, i'm new. I hope this is the right section for this topic.I'm building for learning purpose an high frequency general purpose inverter. I want that it can be suitable up to 230 Vac input voltage. The circuit is basically an half bridge with two high speed power mosfet driven by two isolated drivers, driven as well by a microcontroller.The only problem i'm experiencing is that this mosfet (SIHG22N60) has a very low rise/fall times. It is a very explosive device.Now i'm driving the circuit with about 500 kHz with an input DC voltage of 5-20 Vdc. With 20 Vdc i get a 100 Vpk overshoot with 20 ns rise time on the Vds of the mosfets when the mosfet opens. The irradiated EMI is too high, i'm experiencing problems with the nearby devices, and i fear that this overshoot can lead to a driver / mosfet faliure if i try to increase the input voltage.note:- no load- I'm working on a pcb i realized, i tried to be compact and close as possible with power and signal layout.- I'm using film capacitors as close as possible to the mosfets.- I placed a snubber RC network in parallel with the drain-source of every mosfet, but it is light, i cannot increase the snubber because of the high frequency and voltage.- I tried to modify the gate resistance but with no results.- in attachment the waveform. Yellow the Vds, violet the VgeDo you have any suggestion?if you need more details tell me pls.Thanks in advance

author: filssavi
author_rank: Frequent Contributor
timestamp: July 27, 2019, 05:05:42 pm
content: There could be a lot of problems, but let’s try to narrow it down1- if you could post a schematic and layout examples it would be very helpfullHowever assuming the purple one is a gate source voltage for the transistor, that is for sure a problem such a bad gate voltage Is asking for troubleAlso note that at 20V a 20 ns raise time is not too bad from an EMI standpoint, it is only when you have a high VDS voltage that that should become a problem

author: Xenom
author_rank: Newbie
timestamp: July 27, 2019, 05:22:01 pm
content: Quote from: filssavi on July 27, 2019, 05:05:42 pmYes, tomorrow i'll post scheme and pcb layout.Note that the purple (gate waveform) is dirtied by the Vds transient, and it is smoothed due to the high Rg i mounted in order to slow down the transient.about the rise time, indeed the 20 ns is the rise time of the Vds at 150 V and more, so with a transient of about 5 V/ns.

author: Xenom
author_rank: Newbie
timestamp: July 28, 2019, 11:23:33 am
content: Here is the power section of che circuit.Note: i showed only the high voltage section and driving.The half bridge power capacitors mounted are 1000 uF low ESR electrolitic, 3.3 uF film polypropilene capacitors and 680 nF smd capacitor on the bottom of the film capacitors.Driving circuits are as close as possible to the respective mosfet.I mounted only a single gate resistance, without the diode. I tried from 10 to 56 ohm.

author: filssavi
author_rank: Frequent Contributor
timestamp: July 28, 2019, 05:08:33 pm
content: I'm sorry but you have to try and draw a cleared schematic. because this one is extremely hard to follow,- The component values are not always present- Try avoid crossing unconnected wires as much as possible- Name important nets (HV+, HV-, signal grounds, inputs, etc)- show in some way what is mounted or not (that could just mean crossing out stuff that is not soldered)- Space things out, no designator should be covered by another component- The bridge legs MUST be drawn according to the usual convention with the positive terminal at the top and the negative at the bottom, and the output in the middle- Everything must flow from left to right, that means not only the gate signals but also the power, so on the far right there should be the Half bridge output, not the inputAlso most importantly, the circuit is not complete, you should show everything related to the power, as I don't know what all the unmarked lines going out of the shown section do.Now, with all of that out of the way there are few things that I can't understand, how is the high side gate driver powered or is it bootstrap?what are those 50 ohm resistor, RZH and RZLanyway the purple trace on the scope is very wrong, the gate should raise to the gate drive voltage, with a speed set by the gate resistor, and then it should stay there until the other transistor is turned on, apart from a small dead time (1-2% of the period or less) just enough to be sure to avoid cross conduction, in your case the gate rises to ~15V and then the gate driver suddenly switches offalso a 500 kHz switching frequency for that mosfet is way too high (that means by at least a factor 20) as the transistors will cook to death in a matter of milliseconds. To switch 600V at 10A at those frequency you need to look at wide bangap devices, which are way more expensive, fragile (especially GaN HEMT that die for just about anything, including looking at them wrong)Also keep in mind that even if you manage to switch those at such a frequency (at no more than 10 or 20 V of course), how will you control the resulting converter, a microcontroller is out of question as you will be hard pressed to close even a trivial current loop at 80-100 kHz (and that is with the hand optimized code ecc), that leaves you with FPGA, and frankly that is a big step up in complexity

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 28, 2019, 11:46:52 pm
content: Adjust the value of the snubbers, and try at higher supply voltage -- you're testing at quite low voltages where the Coss(Vds) curve is incredibly steep.This is why your Vds ringing is so spiky.At higher voltages, Coss will be more stable, and very very much lower. This raises the Fo of the switching loop, though it may not raise it far enough to exceed the switching rate of the transistor itself (which is the preferred design state, you can't excite an LC circuit that you aren't generating harmonics for).You may need to consider a 4-layer board with SMT devices, so that +V, OUT and -V can be stacked with minimal stray inductance.As little as 5nH is achievable in this way; with leaded components, you're limited to an absolute minimum of about 20nH loop inductance, due to the lead length of the transistors.Also consider using ceramic caps (up to 1812 size, preferably C0G) for snubbing, and maybe bypassing as well.Tim

author: Xenom
author_rank: Newbie
timestamp: July 29, 2019, 07:23:23 pm
content: Quote from: filssavi on July 28, 2019, 05:08:33 pmYes you are right. Here the new schematics i hope it is better understandable.RZH and RZL as well of the zeners were removed because unecessary (isolated supply regulation).NOTE: DH1, DH2, RBL1, RBH1 are not mounted. i'm using only a single gate drive resistance.The drivers are isolated throught the input signal e throught the power. I used a transformer in order to generate the power supply for both drivers. Transformer driving circuitry is not shown.the purple trace is maybe too filtered because of the high value gate resistor i tried in order to slow down the dV/dt Vds transitory.This is an experiment, i want to try to increase the power and the frequency as much as possible; there devices are very fast and they can reach 600 Vds with about 20 A rms, according to the datasheet.

author: Xenom
author_rank: Newbie
timestamp: July 29, 2019, 07:27:23 pm
content: anyway, with a good inductive load (about 50 uH), the overshoot will almost disappear.I reached about 40 Vdc input voltage @500 kHz without problems, but i'm scared to increase the voltage

author: daveatol
author_rank: Regular Contributor
timestamp: July 30, 2019, 06:53:41 am
content: Your snubbers don't look correct, as the capacitors don't have a discharge path. If using a diode, the capacitor should have a parallel discharge resistor; without a diode, the series R-C is OK.The snubber design will affect the ringing you see.

author: f4eru
author_rank: Super Contributor
timestamp: July 30, 2019, 05:02:43 pm
content: where is the low part of the driver connected ?is that path minimized on the layout ?

author: Xenom
author_rank: Newbie
timestamp: July 30, 2019, 05:11:12 pm
content: Quote from: daveatol on July 30, 2019, 06:53:41 amyou are right, i dind't realized it because diode is not mounted (i shorted the gap). But the snubber is useless in this case because i cannot increase it too much to avoid the excessive dissipation on the snubber resistance. At this frequency you cannot exceed 100-200 pF or the resistors will take fireQuote from: f4eru on July 30, 2019, 05:02:43 pmi think that the driving signals don't require the path minimization, at least if the inductive and capacitive couplings are minimized. Am i right?the signal path are about 7-8 cm long but they are as close as possible with each return line to minimize the inductive loop.The ground of the driver is separeted, so no current flows throught the signals paths.