Pls suggest small cheap FPGA with 3Gbps tranceivers - Page 1
Forum section: electronics / general

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 11:21:09 am
content: Hello,for a potential future project, where I would utilize 3Gbps capable transceiver/s, I am looking for a cheap lowend FPGA, that can be diy soldered, so probably nothing bigger than FBGA256 is possible.As this is clearly for a hobby use, I am willing to take risk and buy stuff from the dark corners of far east.I am used to the Altera world (Quartus workflow and the documentation hiearchy), so I'd preffer an Altera FPGA, unfortunately it seems there is exactly none cheap FPGA in diy-solderable BGA with 3Gbps trx. The only one close I could find is Cyclone IV EP4CGX15, that comes in a nice BGA169, but has only 2.5Gbs transceivers and some smart ass thought be great idea to make an FPGA without multipliers.Then the obvious choice from Lattice seem to be LFE3-17A, which is BGA256 and has whoknows how many transceivers in that package - the Lattice documentation is a mess. But I guess at least one Rx and one Tx is there. But it is an extremely cheap FPGA, from $6 up from china.Then I have discovered, I could buy Artix 7 XC7A35T cheap in FBGA256 too, unfortunately, in this package, there is exactly zero GTPs. WTF is wrong with you, Xilinx? Would have been a damn good deal, for those $15-$18.Are there any options left? Have I missed any cheap FPGA with 3Gbps IO capability? Have not researched in those pure Chinese FPGA like Gowin, as I am afraid of the toolchain and documentation. As a beginner I'd rather stick to something from Altera/Latttice/Xilinx.To recap, only two cheap FPGA options with fast transceivers, out of only one is really fulfilling the requirement of 3Gbps.Altera Cyclone IV: EP4CGX15BF14C8N, about $8, BGA169 1mm pitch, 4x SERDES but only 2.5 Gbps and stupidly no multipliers.Lattice ECP3: LFE3-17EA 6FTN256, about $6, BGA256 1mm pitch, notsurehowmany SERDESes 3.2GbpsThank you for any suggestions.

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 12:39:29 pm
content: Take a look at Artix in CPG236/CPG238 packages. They have 2 MGTs which go up 6.25 Gbps for speed grade 2 and above, speed grade 1 is up to 3.75 Gbps. Now, this is a 0.5 mm pitch part, which sounds terrible until you see the actual pinout diagramOnce you do you will realize that you can route it out even on 2 layer board as long as you can do 3 mil traces. WellPCB can do that for any boards, JLCPCB can do 3.5 mil for 4 layers, which is probably good enough (you can make pads an oval shape to let traces through, or make them a bit smaller than they suggest and it should be still good enough). And you will need 4 layers for MGTs for SI reasons. On the upside it is literally very small package (9x9 mm), so you can fit it everywhere.

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 01:47:30 pm
content: I can accept the challenge of 0.8mm pitch BGA, but 0.5, oh shit never. That is bordering with HDI PCBs and laser drilled vias. Of course that can be manufactured, it is not a question of "if", but money. If I could afford such, I wouldn't be asking for suggestions and just pick the first suitable FPGA from Mouser and be done with it.Considering I have zero experience handsoldering BGAs (not counting the bunch soldered on an ERSA machine at my former employers site), I'll definitely have a pile of damaged junk - that could get very expensive easily. Hence looking for the cheapest FPGA options available, that can be at least partially routed on cheap 4 layer boards.However thanks for the suggestion, I'll try looking what you consider a not terrible 0.5mm pitch BGA pinout.

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 01:53:10 pm
content: Is there any easy way to display the pinout graphically, so at least one can see where the supply, IO and config pins are located? Those CSV or similar files are great, but not really making things much easier.//EDIT: Seems also Spartan 6 may be a candidate: XC6SLX25T-2CSG324C is in the $15 to $18 range from china, is unfortunately a BGA 324 with 0.8mm pitch - which is still doable on 4 layer board, but unlikely to achieve full fanout. Has two 3.2 Gbps GTPs.

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 02:32:17 pm
content: Quote from: Yansi on November 16, 2020, 01:53:10 pmTake a look at UG475 - it has pinout diagrams for all 7 series devices. Attached are two screenshots from it for CP236.As you can see, IO are only 3 rows deep, and there is a ton of space between outer ring and the middle section for vias and whatnot. This is why I said it will be very easy to route out if you can fit a trace between two pads - you route out two outer rows directly, and drop vias for third row in the space between outer ring and middle section. Also middle section pinout is such that you don't need any vias inside that field as all internal balls connect to the same net as one of the balls on the outer row of that middle section. See power diagram for details. Hopefully you will see what I mean.

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 03:02:09 pm
content: That are some nice images, exactly as I wanted them to be. Yes, the pinout seems very logical and manageable even on 4 layers. However I have kind of large disgust for these fine pitch BGAs, as long as I can't even solder the larger pitch ones.Designing a PCB for these small ones would certainly require some experience I don't have. Lastly, the cheapest Artix 7 in this package I can find is $30+, which unfortunately is twice as the Spartan 6 mentioned above.I have created the color pinout image for the Cyclone IV GX myself, as far as I know, Altera does not have such beautiful colored images in their documentation.So, there are three options now:Altera Cyclone IV: EP4CGX15BF14C8N, about $8, BGA169 1mm pitch, 14k LE, 4x SERDES but only 2.5 Gbps and stupidly no multipliers.Lattice ECP3: LFE3-17EA 6FTN256, about $6, BGA256 1mm pitch, 17k LE, 4x SERDESes 3.2 GbpsXilinx Spartan 6: XC6SLX25T-3CSG324C, about $15, BGA324, 0.8 pitch, 24k LE, 2x SERDES, 3.2 GbpsClearly, Lattice for the win.

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 03:08:30 pm
content: Quote from: Yansi on November 16, 2020, 03:02:09 pmYou PCB is going to cost you more than thatIf you want to be a real cheapskate, you can try your luck in gambling on Aliexpress. There are some super cheap options to get your hands on these parts, but of course the quality is unknown.Quote from: Yansi on November 16, 2020, 03:02:09 pmYou can cross out Lattice from this list unless you don't mind paying 1k$ for the license:http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/FPGAandLDS/LatticeDiamond#_FD13D8A25CBB47BD83F143E5B55DBC75Which doesn't exactly fit for being a cheapskate

author: BrianHG
author_rank: Super Contributor
timestamp: November 16, 2020, 03:39:52 pm
content: Quote from: Yansi on November 16, 2020, 03:02:09 pmYou got unlucky with Altera, EP4CGX22BF14C8N & EP4CGX30BF14C8N are the same die and interchangeable, however the EP4CGX15BF14C8N happens to be a different die unlike the CycloneIV E series where the first 2, EP4CE6 and EP4CE10 are the same. You could have gotten away with murder. (IE place a EP4CGX22BF14C8N, compile for a EP4CGX30BF14C8N & program your JTAG/BOOTPROM with that file and it will run with everything in tact as if it were the larger FPGA.)Double check the Cyclone10, they might have a better solution with their bottom end GX equivalents.Also check for the Lattice ECP5-5G LFE5UM-25/45/85 family. The eval PCB:https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/LFE5UM-45F-VERSA-EVNG/5222128Comes with the LVDS version of the chip and it would be stupid is once you buy Lattice's own eval board, a compiler license wouldn't come with it which wouldn't allow you to use the IC itself or LVDS.

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 03:58:13 pm
content: Quote from: BrianHG on November 16, 2020, 03:39:52 pmThey require Quartus Pro license ($4k). Cheap 10LP options are total garbage - they don't even support DDR memory, let along have any transceivers. I'm not sure what's the purpose of such devices.

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 04:40:43 pm
content: Quote from: Yansi on November 16, 2020, 03:02:09 pmJust noticed that you apparently consider 0.8 mm 324 ball package to be "small". In this case you can look at Artix in CSG325 package, they are a bit more expensive than CPG236/238, but they have 4 transceivers (instead of just 2) up to 6 Gbps, 0.8 mm ball pitch, and have more IO balls available. You didn't specify anything about connectivity requirements other than transceivers, but depending on how much stuff you will have to connect beyond MGTs you might need a 6 layer board for those devices.

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 05:02:12 pm
content: Interesting, I have no experience with Lattice, but anyway am quite surprised by that. Thought maybe you need a licensed tools for some of the IP cores, but that you can't even use iCE40 FPGAs with the free license? (see them not checked there). Thanks for pointing out. Thought those iCE40 sticks had free support, as they were all the rage couple years ago.That unfortunately changes the game plan a bit. That is rude from you Lattice, you hear me, RUDE!So, either Altera, or Xilinx. I'd better check the licensing with both then. But as far as I know, no limitations of using Cyclone IV devices.Problem is, that I can't get Artix 7 in CSG325 (XC7A12T-1CSG325C) anywhere below $30. XC7A15T is $35+.Same goes with Cyclone 10. Prohibitively expensive and with no interesting features.I can have two Spartan 6 devices (XC6SLX25T-3CSG324C) for the price of a single Artix 7 (with half the LE for example). Does not make sense to push an Artix 7 then.PS: Not that 324 ball package would be small, but is the smallest of them, that has any GTP and does not require HDI PCB.(Note: To describe what I need it for is say a 3Gbps data stream I need to decode, exctract some data out of and encode back into another stream. So I don't really need much IOs for this. Not even any external RAM. Project should be dead stupid simple, but it seems almost impossible, due to lack of sensible FPGA options on the market).

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 05:32:34 pm
content: Quote from: Yansi on November 16, 2020, 05:02:12 pmFor me it absolutely does, as I don't want to touch ISE with a long pole unless Xilinx will pay me for doing that. Also 7 series is significantly faster. Unless you really need to race to the bottom with price, extra few bucks is a fair price for much better device and move convenient (in my opinion anyway) IDE and workflow.Quote from: Yansi on November 16, 2020, 05:02:12 pmI thought I already demonstrated that you don't need HDI to break out CP236 package...Well, that's all I have to offer at this point, the decision is obviously yours to make.

author: BrianHG
author_rank: Super Contributor
timestamp: November 16, 2020, 05:49:22 pm
content: Quote from: Yansi on November 16, 2020, 05:02:12 pmThe Lattice ECP3 eval board is ~120$. You seem to get a license with the eval board, it isn't too bad a deal.You get a full device with LVDS ports to play with for testing with DDR3 & PCIE already there as well.However, can you compile designs with your own FPGA? Or, do they stiff you there for the 1k$?https://www.latticesemi.com/ecp3versa

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 06:24:31 pm
content: Have visited GowinSemi website. GW2A seem their "flagship" FPGAs, up to some pretty large BGAs. But not a single mention of any SERDES capability. Documentation under registerwall.Xilinx ISE - worked in it one semester at college. I can't remember that well, but it wasn't as bad. Is Vivado that much better?You know what... forget all the above, I'll take some BGA practice elsewhere, then buy (whatever it takes) suitable BGA. As thinking 3Gbps SERDES in a lowcost FPGA in a sensible size of package seem to be a wet dream.Damn, what's so difficult integrating a 3Gbps SERDES these days? It's nothing new, the technology is here like what, 15+ years?I come quite disappointed and frustrated out of this fight.

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 06:38:37 pm
content: Quote from: Yansi on November 16, 2020, 06:24:31 pmIt's not, it's just your definition of what is low cost does not align with what is considered low cost in this market segment. Remember that three big markets for FPGAs are military, communications and aerospace, and it's just so happened that none of them particularly care about cost of components, because their markups are so insanely high. All others just get spoils from that table. This is why both Xilinx and Altera/Intel can come out on stage and say with straight face that US$500 devices are "low cost"Quote from: Yansi on November 16, 2020, 06:24:31 pmIt's not difficult. It's just nobody wants 3G SERDES in 2020, everyone wants 25G+ ones. So the only options are back from those old days.Quote from: Yansi on November 16, 2020, 06:24:31 pmYup, this was expected as you set unrealistic expectations.

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 06:52:53 pm
content: 3Gbps serdes in a FBGA256 is an unrealistic requirement? WhatMaybe, I am trying to push the price way too low, I am fine with that (I like to push prices down), but even if I wouldn't, I have found so far exactly 0 parts smaller than BGA324 with any 3Gb serdes. (not counting the paywalled Lattice part)(yes, your CPG236 has indeed less that 324 balls, but is so small, I wouldn't touch it with a stick. Not before I get enough BGA practice beforehand)

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 06:59:41 pm
content: Quote from: Yansi on November 16, 2020, 06:52:53 pmI thought I explained the situation on a market we're in. You and I are simply not the target audience for FPGA vendors. So they don't give a crap about what we need or want.Quote from: Yansi on November 16, 2020, 06:52:53 pmThis package was obviously designed exactly for cases like yours (needs MGTs but not many IOs), and the pinout was designed specifically to allow using low cost PCB manufacturing while keeping the device itself very compact as they probably envisioned it's use in some kind of converters or adapters, where space is usually at premium.

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 07:34:48 pm
content: I get your explanation and understand nobody gives a crap about anything but big buck. That's unfortunately the world we live in now.I think we've done this topic to death. To sum up: There are no ((lowcost) && (small package)) solutions with 3Gbps serdes.... apart from that one fine pitch bastard I'd rather avoid using.//Sadly seems ECP3 has not been reverse engineered like ECP5 was, no open source tools available there to solve the problem.

author: BrianHG
author_rank: Super Contributor
timestamp: November 16, 2020, 08:37:31 pm
content: Have you considered an external 4:1/5:1 serializer. All you need are 5-6 DDR LVTTL outputs (4-5data + clock) at 750mb / 600mb and it will serialize that data externally to 3GB/sec.

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 08:48:50 pm
content: Quote from: BrianHG on November 16, 2020, 08:37:31 pmLOL that will probably end up costing more than slightly more expensive FPGA which has all he asks forLife lesson here - know when to stop when racing to the bottom. Because at some point you are going to be giving up too much in order to pay just a little less.

author: Scrts
author_rank: Frequent Contributor
timestamp: November 16, 2020, 09:30:03 pm
content: SerDes FPGAs are usually used for communications and serialization/deserialization of data (e.g. video data like SDI links or 2.5/10Gb Ethernet). There are no needs of hardware multipliers and if you really need a couple - these can be implemented in the logic itself.When I was looking for the cheapest SerDes FPGA 5 years ago - it was ECP3, but I've ended up with Altera, since I knew the tools and brought up fiber Ethernet in a day.

author: Someone
author_rank: Super Contributor
timestamp: November 16, 2020, 09:40:22 pm
content: Quote from: Yansi on November 16, 2020, 06:52:53 pmQuote from: Yansi on November 16, 2020, 01:47:30 pmQuote from: Yansi on November 16, 2020, 01:53:10 pmQuote from: Yansi on November 16, 2020, 05:02:12 pmSelf inconsistent, and drip feeding unquantified/vague requirements.The obvious question is why are you even looking at soldering a BGA package in low volume. Buy a module/carrier/evaluation/embedded board and be done with it.

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 09:54:52 pm
content: Picking random statements without context does not make consistency any better.So hobbyist shall only use an off-the shelf module according to your consistent logic?

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 10:02:21 pm
content: Quote from: Yansi on November 16, 2020, 09:54:52 pmHe does have a point though. You're saying that it's unlikely you are going to achieve a full fanout of 324 ball package, but then proceed to say that you don't really need much IOs. These two directly contradict each other.Quote from: Yansi on November 16, 2020, 09:54:52 pmIf he/she refuses to use parts which *are* available - yes, what other option is out there? Well, aside from *not* doing anything at all.

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 10:40:02 pm
content: Yes, there is point, that I haven't specified exactly what I want. Indeed, I have a specific project in mind, that would need about 30 IO pins and one MGT Rx/Tx. But I wanted to make myself a little comparison of whats available, and what is not, which I think, was done to death and your insight was very helpful, even though you may not think so.The important result I bring out of the discussion is that: MGTs are a rare periphery on small FPGAs (in terms of ball count) and the minimum required ball count to get at least 3Gb seems to be above 324 balls, which is a lot.This time I may need just 30 IOs, but next time I may need 100 and I'll be back here again, with the same problem. At the same time I do not want to invent all the SCH + PCB again, hence looking for a compromise, which a 256 ball chip could offer, unfortunately there are really no such options, as you've correctly pointed me at the licensing scheme.And note I am refusing to use a $70 Artix in fine pitch BGA, as I have already enough bad experience soldering this sh!t at my former work and that wasn't on cheap Chinese PCBs. Yes, I may have done something incorrectly, hence I try to avoid these and use something more tolerant for process error, as I do not have any king of specialized equipment for BGA work, yet. Hence my preference for 1mm pitch and smallest ball count possible, which I am confident I can design a PCB for, without pushing the cheap technology to the limits.Ruining a $70 Artix hurts, looking for cheaper alternatives makes sense, as I am not confident with my non-existent BGA skills. As I'll get confidence in soldering these bad boys, I may as well opt for a $70 chip, because its price gets dissolved in the rest quite easily, but not if you kill two of these in a row (reading everywhere now and then how the BGA is sensitive to this or that...).You may (or not) understand, that after learning some basics in vendor's A toolbox I don't want to start over again with vendor B or even D.And yes, not doing anything is also a valid option here. Clearly, I do not have to budget for this, so scrapping the project may be a good option after all.I hope this explained at least a bit why I proceeded like I did.PS: I thought there will be much more options, than those three I've found myself.

author: asmi
author_rank: Super Contributor
timestamp: November 16, 2020, 11:00:50 pm
content: Quote from: Yansi on November 16, 2020, 10:40:02 pmI said here like a million times already - if you want to get BGA soldering practice on cheap, buy some super cheap QSPI flash in BGA24 package, design a small breakout and go crazy! It's easy to break out on just 2 layers, it's trivial to connect it to any MCU you've got around with SPI bus to verify if soldering went well, and it's the cheapest part I know of which is 1)BGA, and 2)you can easily verify soldering.Quote from: Yansi on November 16, 2020, 10:40:02 pmNo, not only I don't understand, but I actively disagree with this approach because knowing multiple vendors' tools not only gives you more options, but it also broadens your perspective as something different vendors solve the same problem differently, and it's helpful to know ups and downs of each one.I may sound at times as if I actively hate Altera/Intel (I like to call them Antel for short), but I actually don't. Their FPGA board and toolchain have been my very first ticket into the world of FPGAs, and I'm thankful to them for what I've learnt, how to do some things, and how NOT to do themSo by the time I moved to using Xilinx devices, I already had some knowledge and experience, and that might explain in part why working with their devices seems much easier to me. I also used some Lattice devices - mostly to just get to know them a bit better than one can do by just reading a datasheet.So having more-or-less working experience with multiple vendors' tools is a big asset, and never a liability.

author: Yansi
author_rank: Super Contributor
timestamp: November 16, 2020, 11:21:56 pm
content: I have some NOR FLASH memories in BGA64x1mm packages ready, that may serve the purpose, but soldering a miniature BGA does not equal soldering a BGA256/324/484. Applying even heat will be more difficult. That's why I'm afraid of higher failure rate, than with soldering the small one. But I may be successful, who knows... time will tell.I kind of understand why knowing more vendor toolboxes is beneficial - unfortunately in my case, it would mean I would have two (even three), but neither one nor the other would I know enough to be able to do anything properly. Look, I haven't still even figure out how to write a freaking testbench in the Quartus, let alone constraint the design properly (declaring clock period doesn't cut the mustard I guess..)In the end I would really love to know all three major ones, but now I'm glad I can do at least something basic in one of them.And yes, I am very pesimistic, paranoid or whatever. I know myself long enough to know I always screw up badly.

author: Someone
author_rank: Super Contributor
timestamp: November 16, 2020, 11:28:19 pm
content: Quote from: Yansi on November 16, 2020, 09:54:52 pmIts the cheapest way to achieve what you want, unless you value our time and yours as $0. Fine pitch BGA is not something that is cheap in low quantity, but you want to try it anyway for some (unspecified) reason.There is no defeat in using modules, they take all the "hard" bits out of the design as someone has already done the work/manufacturing.If you roll your own board from scratch I'd be predicting a few threads about how to design the power systems, and route the high speed traces. If you want to learn that stuff go ahead, but stop complaining that its expensive as the parts are a tiny cost compared to the engineering effort.

author: BrianHG
author_rank: Super Contributor
timestamp: November 17, 2020, 12:18:55 am
content: This is the cheapest 484pin 1mm bga with transceivers:https://lcsc.com/product-detail/CPLD-FPGA_Altera-EP4CGX50CF23C8N_C568986.htmlThough, it is way too large for your app if the EP4CGX15 was on your hit-list.

author: asmi
author_rank: Super Contributor
timestamp: November 17, 2020, 01:20:59 am
content: Quote from: Yansi on November 16, 2020, 11:21:56 pmThis specific function is implemented way better in Vivado, because it's got a fully featured integrated simulator, as opposed to a bolted-on external one crippled to death in order to entice you to buy a license for a less-crippled version. So adding a testbench in Vivado is just a matter of adding a simulation-only module without ports, IDE will automatically recognize it, and all that will be left to do is to click "Run Simulation" button.

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2020, 02:02:55 am
content: Quote from: BrianHG on November 17, 2020, 12:18:55 amGreat find! However currently zero stock. Hopefully one day I'd be able to use all the balls.EP4CGX15 fulfills all needs, apart that the transceivers are 2.5Gb. But I can live with that, at least for now - as a training to layout the BGA. Then will need to find a faster device anyway.Quote from: asmi on November 17, 2020, 01:20:59 amI remember even in ISE there was just a switch either simulation or synthesis+P&R.I have installed some Modelsim something in Quartus, but never got it to fully work as I expected it to.

author: BrianHG
author_rank: Super Contributor
timestamp: November 17, 2020, 02:29:46 am
content: > 3gb for $15.77 :https://lcsc.com/product-detail/CPLD-FPGA_XILINX_XC7A35T-2FTG256C_XC7A35T-2FTG256C_C181716.htmlI think this one is 6gb/sec...And there is stock.You no longer have any complaints.Also, JLPCB will mount the FPGA since their SMD assembly service for their PCBs get their components from LCSC.Ooops, Xilinx did a dirty move...

author: asmi
author_rank: Super Contributor
timestamp: November 17, 2020, 03:14:23 am
content: Quote from: BrianHG on November 17, 2020, 02:29:46 amUnfortunately this package does not bond out any transceivers.

author: BrianHG
author_rank: Super Contributor
timestamp: November 17, 2020, 03:19:10 am
content: Quote from: asmi on November 17, 2020, 03:14:23 amOdd, I thought that the big red 'XC7A35T' meant it has the transceivers bonded out.What would be the purpose of paying extra for that 'T' when the cheaper ones without are available for 7$.However, you appear to be right...I guess you are stuck with this 35$ monster:https://lcsc.com/product-detail/CPLD-FPGA_XILINX-XC6SLX45T-3FGG484C_C569030.html

author: asmi
author_rank: Super Contributor
timestamp: November 17, 2020, 03:39:23 am
content: Quote from: BrianHG on November 17, 2020, 03:19:10 amNope, actual silicon always contains transceivers, but in some packages they are not bonded out and lasered out on the die to make sure they don't waste power.You just need to know which packages have them bonded out, and which ones don't. At least Xilinx provides excellent guide UG475, which includes graphic diagrams so you can easily see what is available in specific package. No other vendor to my knowledge does that, which is super weird. This of course is listed in the datasheet, but I prefer those diagrams because they contain a lot of information if you know how to read it.Quote from: BrianHG on November 17, 2020, 03:19:10 amThere is smaller 0.8 mm pitch package CSG325, which also bonds out a full transceiver quad (4 transceivers).

author: miken
author_rank: Regular Contributor
timestamp: November 17, 2020, 04:33:03 am
content: Lattice has a new Crosslink-NX family that would seem to be a good fit for this use case. But the usual new product caveats apply as regards sourcing and support...

author: Yansi
author_rank: Super Contributor
timestamp: November 17, 2020, 09:03:35 pm
content: Someone mentioned silicon dies are shared between some of the devices, so similar question comes into mind: What is limiting the smaller density Cyclone IV GX FPGAs at the specified 2.5Gbps transceiver rate?Thinking about all of them being in the same family, probably exact same silicon technology and very similar if not exact same transceiver design, why the smaller ones are specified only for 2.5Gbps?2.5 and 3 Gbps is not as much of difference, so what makes it?Not that I plan to try abusing them to 3Gbps, but I mean, seriously, why the smaller package is limited to work at 2.5G, while the huge BGAs are cpable of doing 3G? Isn't this just marketing by any chance?

author: asmi
author_rank: Super Contributor
timestamp: November 17, 2020, 09:18:00 pm
content: Quote from: Yansi on November 17, 2020, 09:03:35 pmIt might be that their characterization results showed that some packages can not be guaranteed to work in entire PVT range. Remember that when FPGA vendor says "it can do X" what they really mean is "it can ALWAYS do X, no matter if it's -40°C cold or +105°C hot, if it's powered by 0.95 V or 1.05 V, in any combination of those parameters as long as each of them is within supported range".For example, that is the reason Spartan-7 in BGA196 package can only drive DDR3 at 333 MHz and not 400 MHz like all other packages can. That gets even worse as your bitrate goes into Gbps range. For example, the very same Kintex-7 silicon can go as low as 6.6 Gbps or as high as 12.5 Gbps depending on a package it's in! And before you begin inventing conspiracies, the cheapest package is not the slowest one, in fact it's closer to the fastest (see attachment for the speed grade -3).

author: BrianHG
author_rank: Super Contributor
timestamp: November 17, 2020, 11:01:10 pm
content: Quote from: Yansi on November 17, 2020, 09:03:35 pmJust the quality of the silicon and routing to the BGA's package pad.In the -GX, the -8 and some -7 are 2.5-2.7gbps while the -6 are 3gbps. Raise the v-core by 50-100mv and you will get full -6 performance on a -8 part with a little more power consumption. Just tell Quartus your pcb has a -6. If you cannot get the 3gbps because of your package selection, even with a -6, do the same with the core supply and when configuring the PLL, underrate the CLK input setting by 17% compared to your true crystal value only if you need to to actually achieve a compile. Usually Quartus will still compile for the 3gsps, but just give you a timing violation warning.It also helps if you have a good cable driver amp at the output of the LVDS IO transmitter pins, especially if that driver has some signal gain in the 3GHz frequency range.The LVDS receivers seem to tolerate much better when being overclocked, however this is usually because you are feeding the input pins a really fast and clean signal which gets terminated on the die.