Latency for ethernet to ethernet - Page 1
Forum section: electronics / projects

author: rakeshm55
author_rank: Regular Contributor
timestamp: December 07, 2018, 08:41:28 am
content: Hi,For a point to point 10/100 Ethernet connection what is the typical latency i can expect.I am sending data between emac to emacMy scheme will beDataA ---->EMAC_1---->PHY_1---->PHY_2---->EMAC_2 ----DataBWhat can be the typical latency?? there is no network ... its a pint to point connectionThe scheme is used for on board communication between two modules....I would like to quantify the processing delay that would be incurred while assing feom ethernet to ethernet

author: Yansi
author_rank: Super Contributor
timestamp: December 07, 2018, 08:43:03 am
content: Propagation delay in the cable.Plus the few clocks on top of that to process data through the PHY and MAC.

author: Rerouter
author_rank: Super Contributor
timestamp: December 07, 2018, 01:43:59 pm
content: If its for onboard communication. If you dont need isolation you could drop the phys and possibly the macs.

author: ejeffrey
author_rank: Super Contributor
timestamp: December 07, 2018, 10:40:20 pm
content: Propagation delay will always be less than the transmit time 100base/T. Minimum frame size is 64 bytes plus 8 bytes for the preamble, which takes 5.76 microseconds to transmit. Signal propogation for maximum size network link of 100 meters is only about 500 nanoseconds. So unless you are chaining many switches together with maximum length cables you will never get close to 5 microseconds.So delay to the MAC layer is probably dominated by receiving the full packet to evaluate the FCS. There may be further delays depending on how you are getting the data: for instance, a USB to ethernet adapter would need to wait until the the next time the host requests data, while other buses support interrupts.

author: jbb
author_rank: Super Contributor
timestamp: December 08, 2018, 01:43:08 am
content: There’s also approx 400ns delay for collision sense before transmit (yes even with full duplex :-( )

author: ogden
author_rank: Super Contributor
timestamp: December 08, 2018, 01:57:51 am
content: Quote from: jbb on December 08, 2018, 01:43:08 amCould you provide some links to manufacturer's documentation PHY confirming what you say? Those PHY's I know, clearly does not do anything about collisions while in full duplex.

author: jbb
author_rank: Super Contributor
timestamp: December 08, 2018, 06:16:19 am
content: Ah, not in the PHY but the MAC, I think.

author: ogden
author_rank: Super Contributor
timestamp: December 08, 2018, 10:14:33 am
content: Quote from: jbb on December 08, 2018, 06:16:19 amNot sure anymore?I did not ask what you think, I asked pointer to document that confirms what you said. Collision Detection is function of PHY. MAC adds just serialization/deserialization of frame, delay.

author: Berni
author_rank: Super Contributor
timestamp: December 08, 2018, 12:06:21 pm
content: PHYs are mostly just glorified shift registers with level shifting. Whatever you stick in passes straight trough to the other side with possibly a few fixed clock cycles of latency to clock data trough the internal logic. About as instant as you could reasonably have for what they do.Its the MAC that introduces delays. It needs to see the whole packet before it can process it. This already introduces a large delay that is dependan't on packet size and not fixed. This MAC also has to signal onwards that it has a packet and this could also be very jitter prone as it might have to compete on a internal bus inside a MCU with a built in MAC. Then whatever is using the MAC might introduce even more jitter as it likely has other things to do than to just wait for the MAC to give it data.If this is a network card in a PC then things get even worse. The information has to propagate trough the busses of a PC to get to the CPU, this could be pretty fast in the case of a PCIe card having to do only one hop. Worse in the case of a regular PCI card as it has to pass trough the chipset and possible a PCI bridge, or WAY worse if it is a USB network card and needs to go trough all the USB shenanigans. When you are running a common PC OS like windows on top this adds an even larger amount of latency because the OS has to get around to servicing the network card. Putting it all together this can result in miliseconds of time passing before a packet is received and processed.But if you are to simply directly connect a FPGA to a PHY you can indeed get very impressive timing performance.