KICAD-ATMEGA328P Layout Review - Page 1
Forum section: electronics / projects

author: Arsh ahmad
author_rank: Regular Contributor
timestamp: August 27, 2024, 06:51:40 pm
content: Hi All,Below are the images for a Simple Barebone Atmega328P based MCU Board Layout. I have also attached my board constraints, signals are routed with 10milsI want some feedbacks on the design, like what things I can improve in my layout.Any feedback is appreciated.

author: xvr
author_rank: Frequent Contributor
timestamp: August 27, 2024, 10:16:00 pm
content: Looks good, but still can be improved a little:Shift traces (TX/RX/PA_4) to move them out of back of quartz.Make thermal reliefs for ground plane. You will get a serious problems in soldering SMD components to GND plane without it.BTW - why quartz have C5 refdes? It's name for capacitor.

author: Arsh ahmad
author_rank: Regular Contributor
timestamp: August 28, 2024, 05:12:50 am
content: Hi, Thanks for the Feedback, I have still not done silk cleanup it is ref des for the CAP only.

author: zapta
author_rank: Super Contributor
timestamp: August 28, 2024, 04:48:24 pm
content: The ground plans are barely connected. I would try routing as much as possible on the top layer with only short 'jumpers' on the bottom layer which acts mainly as a ground plane.BTW, why 10 mils? PCB houses such as JLCPCB can easily handle 6 mils tracks and clearance. It may give you more flexibility with the routing.

author: tooki
author_rank: Super Contributor
timestamp: August 28, 2024, 11:17:02 pm
content: Quote from: Arsh ahmad on August 27, 2024, 06:51:40 pmA few things I noticed:- if I’m guessing correctly, the 2-pin header on the right is the power input, and the headers on the left and bottom have 5V pins to power peripherals or whatever. But the input and outputs connect only through a quite thin trace running under the MCU. I’d try to come up with a route that gives them a fatter trace.- C2, 3, 5, and 6 seem to be a smaller package than all the resistors and a few other caps. There don’t appear to be any particular space constraints on those capacitors, so why use smaller ones? Remember that multilayer ceramic caps suffer from DC bias effects (reduction in effective capacitance as DC voltage increases), and that the smaller the capacitor’s physical size, the stronger the effect (so physically smaller cap = lower effective capacitance). So it’s better to use physically larger multilayer ceramic caps whenever you can. For example,on this page, they compare three 6.3V-rated 22uF caps from the same series, just in three different sizes. At 5V DC, the 1206 cap loses over 50% of its capacitance, the 0805 loses nearly 70%, and the 0603 loses over 80%! The effect is very, very significant, as you can see.- to the extent that is practical for whatever assembly method you’ll be using, move the crystal as close to the MCU as possible. Make sure you don’t route any other traces underneath it.- by moving PA2 and PA3’s top-layer traces to just above the RESET pad of the button, you could route RESET all the way to the MCU on the top layer, giving your bottom ground pour and traces more room. This in turn would let you route ADC3/4/5/6 more directly, and with a bit of luck and/or tweaking, that in turn would let you move PA4’s via to the right, no longer under the chip, and route its trace away from the crystal. This also frees up ground pour under the chip, where you could stitch the layers together better.- as zapta said, your ground is quite weak (classic beginner “gotcha” that everyone messes up at first :p ) Their routing suggestion is exactly right. A trick I sometimes use to make sure I have nice fat ground connections between key areas of a board is to first draw fat ground traces connecting them (in addition to the pour) so that I can’t break up the pour with signal traces. Use lots of vias to stitch your ground pours — they don’t cost extra.- a power LED is always welcome, as a reminder to be careful when working on a powered-on circuit.- since there’s plenty of room for one, add a proper test point for your oscilloscope ground clip. It can also be a larger (plated) hole or slot close to the edge of the board

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 29, 2024, 10:07:09 am
content: As others have written before, improve the GND plane. Thinner tracks are good, because they allow you to move more tracks to the top of the PCB and leave the bottom more intact. I do see some GND stitching via's. That is often a necessary compromise when a full GND plane is not possible on a 2 layer PCB. However those 18 via's in the lower right corner do nothing.For a bunch of years it's also becoming more common to use 4 layer PCB's. This makes it easy to use at least one full GND plane, and using the other internal layer as a GND plane is a further improvements (i.e. lowers EMC emissions) It is more expensive, but with many PCB manufacturers the difference is not very big anymore, and what you get back for it is both the improved / lower EMC, and a significant reduction in design time.

author: Arsh ahmad
author_rank: Regular Contributor
timestamp: August 29, 2024, 02:24:20 pm
content: Hi all,Thank you, for all the feedbacks I have incorporated a few Changes:1. Added Power LED2. Reduced Trace width to 6 mils.3. Made Bottom layer Ground pour more consistent4. Increase the width of the trace connecting power pins under the IC.5. Adder more stitching vias through out the board.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 30, 2024, 10:29:45 pm
content: This already looks a lot better, but you're only about halfway.Would you care to zip up and upload this design or make it available via some repository site?I could tinker with it for 15 minutes or so...

author: ArdWar
author_rank: Frequent Contributor
timestamp: August 30, 2024, 10:54:58 pm
content: It's okay I guess. Ground plane continuity could be better but that's not critical as the current design is sufficient already.Maybe one glaring weakness is relying on a single via to tie the 5V traces.

author: Arsh ahmad
author_rank: Regular Contributor
timestamp: August 31, 2024, 07:25:58 am
content: Quote from: Doctorandus_P on August 30, 2024, 10:29:45 pmHi I have attached the zip file for reference

author: zapta
author_rank: Super Contributor
timestamp: August 31, 2024, 02:48:45 pm
content: Quote from: ArdWar on August 30, 2024, 10:54:58 pmIs it a matter of via hole size (e.g. make it bigger) or that a single via, of any size, is not reliable for higher current?Also, what are the rules of thumb for power trace width and via holes for low power applications like this one?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 31, 2024, 03:00:35 pm
content: Me and my big mouth (itchy fingers?)I really did not want to spend more then 15 minutes on this, but that turned into nearly two hours.The main reason is that I really did not like the 0.15mm (6mil) thin tracks.Tracks that thin are perfectly all right for 4 layers, but quite a lot of PCB manufacturers have wider track width rules for double sided PCB's. If you do not go narrower then about 0.25mm then it makes you compatible with nearly any PCB manufacturer, and you still have some room for tolerances left (Many PCB manufacturers advise to go a bit courser then their minimum rules.After "fixing" the narrow tracks I got the GND plane to look like:Maybe I should have listened to ArdWar. The IC's on the arduino are relative old technology and don't have very steep flanks, and as a result the GND plane is not terribly important.Some other notes:* Don't use Earth. Use GND instead. ("Earth" is to much like PE ( Protective Earth) and this is just for very different purposes.* Added C7 for Vref.* I would use another connector for J1. Maybe a barrel jack, maybe a screw connector.* Maybe add a voltage regulator and mounting holes?When zipping up or archiving a project, you do not need to include the whole backup directory (with 20 copies of your project) and you can also remove the fp-info-cache file. (Silly KiCad quirk, this file should not even be in the project directory).With those changes, your zipped archive shrinks from 2.2 MiB to 87KiB.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 31, 2024, 03:16:36 pm
content: Quote from: zapta on August 31, 2024, 02:48:45 pmIt's partially a habit from 30 year old, and partly a current handling issue. In most cases a single via will also be just fine for "higher current", but it is possible the via gets damages if for some reason a short circuit happens. If a via gets blown because of this, I'm not sure whether it will always be visible on the outside.Quote from: zapta on August 31, 2024, 02:48:45 pmEven narrow tracks (such as 0.2mm) can also easily conduct more then 500mA without getting very hot. KiCad has a built in calculator for calculating track with, length, thickness, current handling and temperature rise.But for power tracks, there are some other reasons.* A lower voltage drop over the track is preferable.* Wider track have lower inductance.* When Power tracks are wider on the PCB. You can easily recognize them during PCB design, and PCB repair etc.

author: Arsh ahmad
author_rank: Regular Contributor
timestamp: August 31, 2024, 04:03:55 pm
content: Hi, Thanks for the files, It is helpful for me for understanding the placement of components on small boards.Although there is one query, about the stitching vias, Adding more vias if we have space will have any effect on designs like these or is there any other way to decide?Generally whenever I route any RF Board I use Shielding Vias near the RF Trace, and equally spaced stitching vias through out the ground. What should be the general strategy to decide.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: August 31, 2024, 04:28:27 pm
content: Quote from: Arsh ahmad on August 31, 2024, 04:03:55 pmNo, filling your whole PCB with via's is useless, and it adds to the production costs. Those holes take time to drill, and the drills have a limited lifetime too.The goal is to place vias to provide the shortest path to GND. Shorter tracks is less inductance, and thus a better high frequency performance. For decoupling capacitors, you try to minimize the he loop from: uC pin to capacitor, from capacitor back to the GND pin. Often this can be done on the same layer, so no via's needed (Except for the "DC path") But when you need to use vias then put them close to both the GND pin of your uC, and close to the GND pad of your capacitor, and also place them to minimize the total length of the loop mentioned earlier.For tracks. Realize that electrons flow in loops. For every electron flowing out of an IC, there is another electron going into the IC. the electrons going into the IC are either coming from GND or from the Power supply, depending on the direction of the current in the track. In PCB design, usually it is assumed that all return currents flow though the GND plane. This is not exactly true, but when decoupling capacitors are placed well, this is good enough.Quote from: Arsh ahmad on August 31, 2024, 04:03:55 pmI've seen that used too. It's easy to copy, but hard to apply in a meaningful way. Best advice I can give is read some thick books about it. I don't have enough experience here.

author: tooki
author_rank: Super Contributor
timestamp: August 31, 2024, 04:38:09 pm
content: Quote from: Doctorandus_P on August 31, 2024, 04:28:27 pmWell, it's not entirely useless (in that it is very unlikely to cause harm, and potentially might improve performance in some situations, as unlikely as that is to be the case here). And as far as I know, none of the PCB prototyping manufacturers actually charge more for vias. So while you definitely wouldn't want to add gratuitous vias to a mass-produced board, on a low-volume hobbyist board, it won't cost anything extra.

author: tooki
author_rank: Super Contributor
timestamp: August 31, 2024, 04:40:48 pm
content: Quote from: Arsh ahmad on August 31, 2024, 04:03:55 pmWith a solid ground plane like that, they aren't likely to do much on this design. It's not an RF board."General strategy"? It really depends on the circuit.

author: zapta
author_rank: Super Contributor
timestamp: August 31, 2024, 04:46:56 pm
content: Quote from: Doctorandus_P on August 31, 2024, 03:00:35 pmRegarding the mounting holes, for hobby project I have had very good success mounting PCBs with 3M VHB Double Sided Heavy Duty Mounting Tape (the clear kind is slightly easier to remove than the gray kind). I am using 3D printed cases.