What is meant by 28nm process? - Page 1
Forum section: electronics / general

author: jp1390
author_rank: Contributor
timestamp: May 08, 2012, 01:44:43 am
content: Just wondering if this is referring to a chips gate length or channel length. I'm also not really sure of what the difference between the two terms are also.Thanks!

author: IanB
author_rank: Super Contributor
timestamp: May 08, 2012, 02:01:43 am
content: I read it to be the radius of a circle enclosing a memory cell in the technology. Typically called the half-pitch, i.e. half the distance between identical memory cells. Other features on a chip will have all sorts of different dimensions. The distance quoted is just a scale indicator for comparing similar devices.

author: free_electron
author_rank: Super Contributor
timestamp: May 08, 2012, 05:43:18 am
content: Nope.28nm is the width of the smallest 'feature' on the chip. For a mos transistor this is the width of the gate. Since layers are ' stacked ' each layer up needs wider features. So , the metal interconnects can be 35 nanometer or larger.It is really the width of the smallest element. This is limited by the imaging and etching technology.I just posted a very long text in the thread on how transistors are made. Go read it.

author: IanB
author_rank: Super Contributor
timestamp: May 08, 2012, 06:41:29 am
content: That isn't what it says here:http://en.wikipedia.org/wiki/22_nanometerBut I don't imagine there is a universally agreed standard for this, is there?

author: free_electron
author_rank: Super Contributor
timestamp: May 08, 2012, 06:48:45 am
content: That is exactly what it says there.. The features themselves are 22nm, the half pitch between them is also 22nm.So you have a 22nm line , a 44 nm gap, and another 22nm line...They give a particular case for a memory cell. That's all.The universal denotation is ' the width of the smallest feature on the chip' and for cmos devices this is the width of the gate.

author: Time
author_rank: Frequent Contributor
timestamp: May 08, 2012, 04:28:49 pm
content: I always thought that the "x nm process" referred to the smallest capable feature size in a particular process, like free_electron said.

author: vxp036000
author_rank: Regular Contributor
timestamp: May 08, 2012, 04:53:14 pm
content: A 45 nm process does not necessarily mean minimum feature size. It refers to the mimimum gate length on a FET. So the minimum gate length is 45 nm. This is the commonly accepted definition in IC design, despite what you'll hear from laymen. Minimum feature size means something entirely different.

author: free_electron
author_rank: Super Contributor
timestamp: May 08, 2012, 06:07:14 pm
content: well duh ... the gate IS the smallest feature on the chip ...name me something that is smaller ...QuoteAnd stop your incessant belitteling.

author: Time
author_rank: Frequent Contributor
timestamp: May 08, 2012, 06:24:11 pm
content: I didn't hear from laymen. I absorbed it from my advanced VLSI design courses from way back when. I don't work in the semiconductor fab/design industry though.

author: FenderBender
author_rank: Super Contributor
timestamp: May 08, 2012, 09:38:50 pm
content: I was touring Rutgers University a couple weeks ago, of course in the EE building. One professor was giving a presentation on manufacturing processes.He said that the numbers refer to the LxW dimensions of a single transistor (so 28nm by 28nm)....I'm not sure sure if that's correct or if he was simplifying it for us stupid high school kids, but that is what he said.

author: ejeffrey
author_rank: Super Contributor
timestamp: May 08, 2012, 09:58:01 pm
content: Since the size is a feature of the process, not the actual device you make the most correct definition is similar to how you define lines/mm for an optical scanner or camera -- the closest you can space lines and have them resolvable. For CMOS logic/memory this is the same as the gate size, but feature size applies even if you don't make transistors. Feature size is an important criteria for MEMS devices, on-chip optical waveguides, and superconducting circuits as well as the on-chip passive elements like interconnects and spiral inductors.

author: A-sic Enginerd
author_rank: Regular Contributor
timestamp: May 08, 2012, 11:40:17 pm
content: I've been doing IC design for quite a few years, and I used to think I understood what it meant to define a given process node. Now days I'm not so sure. I'm just a digital designer that doesn't get involved with the backend of things (have always had a vendor that handles that) so I haven't really had a need to be intimately familiar with how a given process node was actually defined. But as of the last few years in working on projects that were done in 65nm, 45nm, and 28nm processes.......it seems the lowest level of technical definition hasn't remained consistent over the years. And yes, I said "28nm".....that's NOT a typo. I see on sites like wiki and such they go from 45 to 22. Well, guess what? Try finding a 22nm process with the likes of TSMC or other fab.So in general, I don't think you can necessarily take a lowest level, hard and fast technical definition of a given process technology to be accurate. There is likely to be some fudging in there. I used to think that free_electron's description is / was the most accurate. Now....I don't friggin know. I mean shoot, go look at the wiki page for the definition of a 65nm process. Even right there it's claimed that the actual smallest 'feature' could be as small as 25nm.So once you get a 'feel' for the scale of what you're dealing with, don't sweat the real nature of the precise size of things. Use it as a gauge of what to expect in terms of power, performance, and cost. Ie: you're going to see an XX improvement in power consumption and speed when moving from a "45nm" process to the "28nm" process.

author: free_electron
author_rank: Super Contributor
timestamp: May 09, 2012, 12:00:50 am
content: Quote from: FenderBender on May 08, 2012, 09:38:50 pmand he was abolutely correct !28nm means the gate can be 28nm wide. the actual 'transistor' is only the part right underneath the gate the rest is just the channel. ( there are some fringe effects ) .

author: vxp036000
author_rank: Regular Contributor
timestamp: May 09, 2012, 12:49:43 am
content: In IC design, I've seen design rules with feature size smaller than the gate. And the process was still categorized by the gate length.Quote from: free_electron on May 08, 2012, 06:07:14 pm

author: vxp036000
author_rank: Regular Contributor
timestamp: May 09, 2012, 12:57:01 am
content: In IC design, I've seen design rules with feature size smaller than the gate. And the process was still categorized by the gate length. Here is an example.Quote from: free_electron on May 08, 2012, 06:07:14 pm

author: FenderBender
author_rank: Super Contributor
timestamp: May 09, 2012, 01:13:06 am
content: Quote from: free_electron on May 09, 2012, 12:00:50 amOhhh I see what the question is now.

author: vxp036000
author_rank: Regular Contributor
timestamp: May 09, 2012, 01:16:06 am
content: Notice that the minimum feature size in my example was 0.1. Minimum gate length is considerably larger.

author: vxp036000
author_rank: Regular Contributor
timestamp: May 09, 2012, 01:41:09 am
content: I realize my example was a little confusing. This example should make it more obvious. 20.5 - 20.4 = 0.1 lambda.

author: NiHaoMike
author_rank: Super Contributor
timestamp: May 09, 2012, 02:07:14 am
content: Quote from: A-sic Enginerd on May 08, 2012, 11:40:17 pmIntel's "Ivy Bridge" is built with their 22nm process.

author: A-sic Enginerd
author_rank: Regular Contributor
timestamp: May 09, 2012, 04:59:54 am
content: Quote from: NiHaoMike on May 09, 2012, 02:07:14 amFine, but my point still stands. Call it whatever label you want to, but there doesn't seem to be consistency in what that label may be attempting to strictly define.

author: Spiro
author_rank: Contributor
timestamp: May 18, 2012, 01:11:36 pm
content: To cut it short, it is basic unit of measurement for given technology.

author: free_electron
author_rank: Super Contributor
timestamp: May 18, 2012, 01:27:22 pm
content: In your first example the minimum feature size is 3.1.You are confusing distances and features. A distance between two elements is NOT a feature ! Especially not if they are on different layers !You can make an make an nwell of 30 nm wide , deposit poly on top of it and etch it so that there is at the end a 22nm strip that overhangs the side 1nm. That does NOT make it a 1nm process....1nm. 22nm<-----><------------------------------->PpppppppppppppppppppppppppppNnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnIt would still be a 22nm process