Specs of transistors used in CMOS ICs - Page 1
Forum section: electronics / projects

author: Manul
author_rank: Super Contributor
timestamp: January 21, 2023, 09:45:44 pm
content: I wondered if someone knows where I could find specs (or at least ballpark specs) of single transistors at various CMOS process sizes. Like the usual stuff found in datasheets including threshold voltage, maximum ratings, capacitances and so on. The reason is mostly curiosity.Thanks

author: mawyatt
author_rank: Super Contributor
timestamp: January 21, 2023, 10:22:30 pm
content: For the more modern CMOS processes these specs will likely be considered propriety, even the various simulation model parameters are protected (BSIM, PSP). Lots of time, effort and $ go into creating these models, so the foundries usually don't make them available, unless you are a IC design partner.Best,

author: Benta
author_rank: Super Contributor
timestamp: January 21, 2023, 10:41:29 pm
content: Only place I can think of is theunbufferedinverters in the standard logic families:MC14069UB74HCU0474LVCU0474LVC1GU04etc.

author: berke
author_rank: Frequent Contributor
timestamp: January 22, 2023, 03:50:45 pm
content: Quote from: Manul on January 21, 2023, 09:45:44 pmI was looking for the same kind of info to model logic input/output stages when interfacing to various devices. Apparently the proper way is to use IBIS models, but you need something that can use them.I found these MOSFET parameters for some process (T58F ??). At least it provides an example.https://github.com/khandelwalkshitij/microelectronic-circuits-17-18/blob/master/tsmc018.lib

author: Weston
author_rank: Regular Contributor
timestamp: January 22, 2023, 07:43:07 pm
content: You could try to directly compute some values based on the published GPIO specifications of parts, possibly aided by die photos of some parts you could find online.The answer to your question would also directly be addressed by the process development kits (PDKs) used for IC design.However, most of the process development kits used in IC design are covered by NDA agreements, so its hard to find transistor parameters.Luckily, Google has been sponsoring a lot of work on open source IC design which has led to the SKY130 PDK (130/180nm CMOS, developed by Cypress Semiconductor) and the GF180 PDK (180nm, developed by GlobalFoundries) being open sourced. Parsing the spice models and documentation is a bit hard, but looking through the PDKs would be a direct answer to your question. The SKY130 PDK has more documentation.Here are the pages for the transistor models. You could also download the models and simulate them in SPICE.https://skywater-pdk.readthedocs.io/en/main/rules/device-details.htmlhttps://gf180mcu-pdk.readthedocs.io/en/latest/analog/model_parameters/LV/LV.html

author: rdl
author_rank: Super Contributor
timestamp: January 22, 2023, 09:21:05 pm
content: There is the CD4007 which is nothing but some transistors.https://www.ti.com/lit/ds/symlink/cd4007ub.pdf

author: tggzzz
author_rank: Super Contributor
timestamp: January 22, 2023, 11:23:43 pm
content: Quote from: Manul on January 21, 2023, 09:45:44 pmWhy? Or rather how would you use the information?If you plan on using "naked" transistores, then the packaging will have a significant effect and may be dominant.

author: David Hess
author_rank: Super Contributor
timestamp: January 23, 2023, 12:53:35 am
content: Find an old Signetics databook with their SD series of MOSFETs. Those are the single transistors from an HCMOS process.http://archive.retro.co.za/archive/datasheets/SD200.pdf

author: harerod
author_rank: Frequent Contributor
timestamp: January 23, 2023, 06:12:47 pm
content: Quote from: David Hess on January 23, 2023, 12:53:35 amSignetics 25120, maybe?

author: edavid
author_rank: Super Contributor
timestamp: January 23, 2023, 07:01:35 pm
content: Quote from: rdl on January 22, 2023, 09:21:05 pmIf you look at the CA3600 datasheet, it has a bit more info on the same IC:https://shop.griederbauteile.ch/info/c/CA3600E.pdfHowever, that is an ancient (20 micron?) metal gate process.

author: edavid
author_rank: Super Contributor
timestamp: January 23, 2023, 07:05:45 pm
content: Quote from: David Hess on January 23, 2023, 12:53:35 amSD stands for Signetics DMOS.I don't think there's any connection with a CMOS process.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 23, 2023, 07:55:00 pm
content: This may be of interest:Code:* HCMOS Subcircuit and Primitive Elements Library* HC_TNOMI.CIR* Nominal Process Corner* Standard Logic Product Group* NXP Semiconductors** Version Date By Remarks* ---------------------------------------------------------------------* 1.2 30/03/2011 RRV Rewritten netlists to add package options.* 1.12 27/10/2010 RRV Added HC(T)240/253* 1.11 06/07/2010 RRV Added HC(T)02/08/86* 1.10 10/12/2009 RRV Removed HCT05* 1.09 09/22/2009 RRV Corrected typo in SWITCH3N* 1.08 09/08/2009 RRV Added HC(T)4020/4060* 1.07 03/27/2009 RRV Added HC(T)05* 1.06 02/20/2006 RRV Added HC(T)366/368* 1.05 10/27/2005 RRV Updated HC/T04 and HCU04 models* 1.04 09/22/2003 RM Active High Enable for SWI2 and SWI2T************************************************** NOMINAL N-Channel Transistor ** UCB-3 Parameter Set ** HIGH-SPEED CMOS Logic Family ** 10-Jan.-1995 *************************************************.Model MHCNEN NMOS+LEVEL = 3+KP = 45.3E-6+VTO = 0.72+TOX = 51.5E-9+NSUB = 2.8E15+GAMMA = 0.94+PHI = 0.65+VMAX = 150E3+RS = 40+RD = 40+XJ = 0.11E-6+LD = 0.52E-6+DELTA = 0.315+THETA = 0.054+ETA = 0.025+KAPPA = 0.0+WD = 0.0************************************************ NOMINAL P-Channel transistor ** UCB-3 Parameter Set ** HIGH-SPEED CMOS Logic Family ** 10-Jan.-1995 ************************************************.Model MHCPEN PMOS+LEVEL = 3+KP = 22.1E-6+VTO = -0.71+TOX = 51.5E-9+NSUB = 3.3E16+GAMMA = 0.92+PHI = 0.65+VMAX = 970E3+RS = 80+RD = 80+XJ = 0.63E-6+LD = 0.23E-6+DELTA = 2.24+THETA = 0.108+ETA = 0.322+KAPPA = 0.0+WD = 0.0.MODEL INT D***************************************** START OF SUB-CIRCUIT DESCRIPTION ** MARCH 30, 2011 **********************************************NOMIN.CIR*********Version 1.04 Added Inverter****.SUBCKT INV4N 2 3 50 60*IN=2, OUT=3, VCC=50, GND=60MP1 3 2 50 50 MHCPEN W= 88U L=2.4U AD= 350P AS= 350P PD=100U PS= 88UMN1 3 2 60 60 MHCNEN W= 56U L=2.4U AD= 225P AS= 225P PD= 70U PS= 56U.ENDSINV4Nwould be a 74HCU04 I believe? Uhh...yep, they use that lower down, good.Come to think of it, 2.4µm sounds long for what process node 'HC is supposed to be (isn't it..?). But go figure, it's only a level 3 model, it's probably an approximation at best.Obviously this doesn't show breakdown voltage, but that's typically ~10V, can add a zener if need be.This file BTW has, at least what looks like reasonable models for the simpler types like HC(U)04, but HC00 is completely wrong (it appears to be NOR), and none of the functions more complex than single gates exist at all, they're dummy/stub versions (e.g. HC138 contains a single NOR)....Ah here it is, the file is on Nexperia now, of course. Can be found on:https://www.nexperia.com/documentation-center.htmlselecting for Analog & Logic ICs, Automotive logic, Gates, filter by Models:https://assets.nexperia.com/documents/spice-model/hc.zipTim

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 23, 2023, 08:04:44 pm
content: This may be useful too:https://www.eevblog.com/forum/eda/free-circuit-simlator-for-logic-gates/msg4015123/#msg4015123

author: mawyatt
author_rank: Super Contributor
timestamp: January 23, 2023, 09:13:52 pm
content: Quote from: T3sl4co1l on January 23, 2023, 07:55:00 pmThis looks like the basic core MOS model that was "patched" to allow use for somewhat analog use. The model uses an absolute value to the the Gate to Source & Gate to Drain Voltages in the correct sense of the model. When these get reversed, where the source and drain interchange by the channel current changing direction, the model yields an incorrect derivative of the transconductance.This was found even in later models, we experienced such when developing the original work for the PolyPhase Mixer (AKA N-Path Mixer) and even earlier back in ~2000 time frame. This causes the channel linearity to be incorrectly modeled with bidirectional currents, even when relatively small levels are concerned. We were developing large dynamic range front-ends based upon large passive NMOS "switches" that could see revered currents at Microwave and MMW frequencies, NMOS was selected because it exhibits the best overall 3rd Order IMD performance for a given size and speed. Our test chips were showing better than predicted IMD performance, and eventually was traced to this issue.We started using another model called PSP (Penn State Philips) developed by Dr Gildenblat, this was a purely physics based model and required significantly more computing power, and often did not converge to a workable solution. Later we met with the BSIM Berkeley folks and Dr Gildenblat (had moved to ASU) about these issues and the 3rd Order non-linearity.Berkeley came up with a clever solution for the BSIM 6 model, in that they referenced the Drain, Gate and Source voltages to another voltage related substrate voltage. This didn't increase the computation time & difficulties as with the PSP model, and gave a much better representation of the device with the source and drain interchanged.Best,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 23, 2023, 09:50:57 pm
content: Speaking of -- you can find, what I assume are detailed, proper -- internal perhaps even -- models of some logic families, with sufficiently advanced BSIM models included. But you need fully licensed and equipped HSPICE or whatever to use them. They're encrypted, of course. (Supposedly HSPICE uses/used some variant of Enigma cipher? I don't know that there's enough known plaintext to decrypt it though. Probably newer versions use common modern block ciphers like AES, more or less hopeless to attack; maybe you get lucky finding a bug or misconfiguration, that'd be about it.)Tim

author: berke
author_rank: Frequent Contributor
timestamp: January 24, 2023, 06:01:34 pm
content: Quote from: T3sl4co1l on January 23, 2023, 09:50:57 pmTypically you don't attack the AES steel door, you just enter through the window.Even if it's AES the key has to be produced somehow on the PC running the software.The memory structure of the AES keyschedule has peculiar properties that make it trivial to detect from a live memory image, unless it is implemented differently or uses hardware instructions. Even then, if the cipher key is stored anywhere in RAM, it is trivial to try all 128/192/256-bit RAM strings provided you can recognize valid plaintext.In other words, if someone can run that model with a licensed copy of the software on a PC, it is quite possible that the key might be extracted quite easily, from the process memory dump, unless they've been quite careful and used countermeasures (or enclaves or whatever.)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 24, 2023, 06:20:29 pm
content: I wouldn't be surprised either, if most of them just decode to a plaintext SPICE deck in memory and run from there; or perhaps a mildly parsed bytecode representation which would be a bit harder to locate. But in any case, that assumes you have the keys already...Tim