Looking for a high resolution, ns step programmable delay line. - Page 1
Forum section: electronics / projects

author: Bendba
author_rank: Regular Contributor
timestamp: January 25, 2018, 11:20:29 pm
content: Hi,I'm working on a telescope high resolution motorized tracking.One of the design I am considering is phase shift control with a 400Hz resolver.The idea is to delay the reference 400Hz signal and feed it back to a phase to voltage or phase to current converter.The section that I'm stuck on, the delay line. I want to achieve a delay of 0 to 2.5ms (I know there will be a fixed delay but that is not a problem, I can calibrate the offset)What is the best programmable delay line commercially available?The dream would be 24bit, 0.2ns incrementAll that I can find only offers delays of up to about 50nsEdit: I'm also investigating microcontrollers and FPGA options but a programmable delay line would keep the software development to a minimum.

author: Someone
author_rank: Super Contributor
timestamp: January 25, 2018, 11:52:04 pm
content: If the waveform is steady/consistent then a delay line is an expensive way to solve the problem. It would be much cheaper to have a PLL lock onto the reference and then produce an output of the same waveform. If you don't need absolute frequency/waveform reference then generating all your own waveforms in arbitrary phases is trivial.

author: Bendba
author_rank: Regular Contributor
timestamp: January 26, 2018, 12:05:05 am
content: Hi,PLL is the first thing that came to mind. But I can't wrap my head around how to precisely generate the phase shift.Frequency and waveform wouldn't be critical, precisely controlled phase shift is what I'm after.I want to generate a phase shift of 0° to 360° with a 0.1" resolution as I want to avoid manically gearing it down.

author: RandallMcRee
author_rank: Frequent Contributor
timestamp: January 26, 2018, 12:28:08 am
content: How about using DDS? It can generate two identical waveforms that differ in phase as you wish...See:http://www.analog.com/en/analog-dialogue/articles/all-about-direct-digital-synthesis.html

author: Someone
author_rank: Super Contributor
timestamp: January 26, 2018, 12:32:19 am
content: If this is for a synchro (400Hz usually gives that away) then you can produce all the signals from a microcontroller and not worry about trying to lock to a reference, even if you want an external reference a micro is still easy enough to design a PLL on for these sorts of low frequencies. Modern micro controllers with high speed timers/waveform generators can get to your requirements if you dither the output phase and follow it with a bandpass filter to average it out.A masochist could do it all in assembly and bit banging but the concepts are the same whether you use hardware or software timers to do it. Or jump straight to an FPGA if you are planning to do many many channels in parallel.

author: Marco
author_rank: Super Contributor
timestamp: January 26, 2018, 12:54:56 am
content: Only a couple of microcontrollers could get close to his desired resolution, only by using high resolution timers at that. The STM32F3 gets close, the C2000 gets a little below.

author: BrianHG
author_rank: Super Contributor
timestamp: January 26, 2018, 01:04:18 am
content: Quote from: Bendba on January 25, 2018, 11:20:29 pm0.2ns steps on a 400hz signal. I cannot dream of anything so tightly insane unless you are talking about something for NASA or space...Say in a world where your source is a 400Hz digital square wave.Lets say we make a 400 Mhz counter and divide it by 1000000 (one million), you will output 400hz. You have 1 million steps, each 2.5ns apart, or, 20 bits of definition. Finding a 400MHz capable fpga, making a 20 bit counter, dividing by 1 million & have a second delayed programmable phased output feeding your PLL feedback oscillator takes a small fast PLD to achieve, yet, a small simple program using only around 80 logic cells + PLL, both external for the low frequency 400Hz, then multiplied internally for the much higher 400MHz.Now, you are asking for 0.25ns, or a 4GHz 24 bit feedback counter. Say you can find such an affordably fast PLD to run 2 x 4GHz 24 bit counters. Just the temperature and age drift of your primary fundamental 400Hz frequency comparator for the external PLL will never sit within 0.25ns. It will drift unless you completely temp compensate all your circuitry and the source sensor as well. You can do a simple count and reset on your first 4Ghz counter and start the second 24 bit output counter at you desired delay. This would also work fine, but, you would have a random glitch noise at +/- 0.25ns. Can you even tolerate that error?The above examples are basically 1 counter as a timer and a second as a delayed start/offset timer generating your 400hz output.Now, to delay a 400Hz analog sine wave with 0.2ns steps. Though there may be some tricks you can use to achieve an average over time where your can create a programmed delayed output which appears to step by 0.2ns in steps even though you may be using as an example a fixed 20Mhz sampling clock & 20 MHz dac, you better know what you are doing with your math to achieve anything even remotely close to pure true steps as the above 2GHz digital method, let alone anything even close to the programmable 2.5ns steps in the much more reasonable 400MHz source clock method. The analog sine wave delayer method will obviously use tons more gates, include trigonometry mathematics & require ADCs, DACs, clocks, analog filters, buffer amps, and still might need a PLL clock circuitry, or, a fast enough MCU with well though out programming to achieve all this. Do not expect 0.2ns steps with any definitive-ness with a MCU sampling your 400Hz sine wave only at 100Khz. Remember, you are asking for 0.2ns steps, not 100ns steps. Think of an MCU ADC sampling and DAC operating at least at 20Mhz and at 12 bits.

author: Someone
author_rank: Super Contributor
timestamp: January 26, 2018, 01:16:24 am
content: Quote from: Marco on January 26, 2018, 12:54:56 amEveryone keeps jumping to brute force solutions (same as in a previous thread on a very similar idea).Quote from: Someone on January 26, 2018, 12:32:19 amIf the output doesn't need high phase agility then its very easy to average out the dither, you could use an intelligent modulation control loop and get faster transitions while keeping the phase noise low. Maintaining a relative phase of 0.1 degrees between two output sine waves is trivial, getting lower to 10s or single digit nanoseconds is not difficult.

author: BrianHG
author_rank: Super Contributor
timestamp: January 26, 2018, 01:30:24 am
content: Quote from: Someone on January 26, 2018, 01:16:24 amOk, 0.1 degrees on a 400Hz sine wave with an MCU is trivial and is nowhere near to the 0.2ns the OP asked for.0.1 degree steps on a 400Hz sine wave will only still require 3600 steps, or, a 12 bit delay control, not 24 bit. We are also talking about 694ns per step, not 0.2ns. (I hope I got my decimal place correct in the math)This is well do-able with many different MCUs. Whether it is an analog 400Hz sine wave in to sine wave out using a sampling ADC & DAC synth delay, or, a more precision digital square wave In and Out using precision PWM timer modules, just selecting the right MCU with appropriate peripherals will do a 12 bit delay, or even 16 bit delay, which will work perfectly fine. Striving to achieve 24 bits might be a practice in futility, but not impossible if you expect the output to be averaged over the long run, but, proving your software design is actually achieving this 0.2ns at true fidelity might be more difficult than actually writing the code itself.

author: jbb
author_rank: Super Contributor
timestamp: January 26, 2018, 01:35:02 am
content: I think Analog Devices make chips for this.It’s definitely possible to do DDS carrier gen (add external DAC) and digital demodulation (add external ADC(s)).But FPGAs are pricey so you would want to cram lots of functions in there (e.g. do multiple resolvers, maybe parts of motor driver, maybe use soft-core processor to run control software) to get your money’s worth.Also, your resolver might (i’m no expert!) be a multiplie type which goes through several electrical resolutions per mechanical resolution (ie 1 mechanical degree might equal 2 or 3 electrical degrees) which can help improve performance.Note: 400 Hz frequency leads to a slightly slow update rate, so don’t shoot for super-fast performance. (I imagine this isn’t a problem for telescope control provided your controller uses acceleration control.)

author: BrianHG
author_rank: Super Contributor
timestamp: January 26, 2018, 01:50:21 am
content: What kind of resolver are you using? Are you providing the extrication signal, or just probing into an existing circuit? Are you controlling the positioning motors? Note that some resolvers don't operate on phase or delay, but use amplitude. Are you making the control system?We may be giving you the wrong advice or options which may be completely mute say if you are exciting the resolver and just listening to the result and adjusting motor position. You do not need to delays here, just analysis of the return signal's delay and how to move the motor. This is something completely different than just making some delay circuit, and it actually may even be easier to do...

author: David Hess
author_rank: Super Contributor
timestamp: January 26, 2018, 04:30:49 am
content: I would use a comparator fed with logic triggered ramp and a DAC controlled voltage. But 0.2ns resolution with a 2.5ms range is 12 million counts which while possible is well into the realm of requiring differential signaling, careful decoupling, and precision analog design.The limited common mode rejection of the comparator can be solved by feeding both the ramp and DAC signal into the same pin with the other pin grounded. Careful attention to noise will be required but noise will still be the limiting factor.