Low Leakage LLC Converter for Instrumentation - Page 1
Forum section: electronics / general

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: July 30, 2025, 11:51:22 pm
content: As part of a project I am working on I needed a low leakage isolated converter. The primary side will have battery backup with a 4S/2P Li-Ion battery, so the converter needs to maintain reasonable efficiency to maximize battery life and minimize heat dissipation. The load is 100 mA minimum, 150 mA nominal, 250 mA max at 16.5 V. The primary will be powered with a 30W/18V AC/DC converter. To make use of the full battery life, I would like to ideally have it be able to power a 150 mA load at 12 V on the primary. The leakage goal was NMT 1 nA RMS (or more accurately 10 mVRMS over 10 M), but I was also interested to see how far I could push it down.I have experimented with low leakage converters using the LT3439 and LT1533 in the past, but I wanted to see if I could do better, so I looked at some resonant topologies. I quickly designed a board and built up an LLC and LLC converter for the purpose (and switched radius and diameter for the transformer, so there's a lot of empty space). A primary consideration was that it is not practical to reduce interwinding capacitance enough to get good leakage out of a single ended design. Even a couple turns around a small nanocrystalline core is a couple pF, and a 10V/us drive with 100 fF leakage will still give 1 uA p-p. Of course, with a balanced drive, the amount of common mode current that is conducted through the stage can be much greater than what is created by it (for instance, if using a noisy switcher as an AC/DC converter). The risetime of the drive signal should be at least 1 us because the admittance of the interwinding capacitance increases at the same rate as the envelope of a trapezoidal waveform until you hit about f = 0.35/t_r.The LCC converter gave pretty nice sine waves, but the efficiency was low, and the amount of resonant current caused VDD to bounce around leading to more leakage. The design I ended up favoring is an LLC converter with RC snubbers across the primary and secondary to slow down the edges. There is a simplified schematic attached. To achieve balanced drive of the primary, I used a full H-bridge drive (with a quad MOSFET) and a coupled inductor for the series resonant L on each leg of the drive because matching separate inductors and expecting them to stay matched did not seem reasonable. Both the primary and secondary are shielded from the core by copper foil connected to the respective grounds (though the choice of the point you consider ground is important). This gave me about 12 pF from primary to secondary. I have recorded the efficiency at about 78% at 150 mA going up to 85% at 500 mA. It would probably be feasible to operate open loop over a limited load range as the output impedance is about 4 Ohms. I will probably regulate the output voltage ultimately, but I have been testing it open loop.To test the leakage, I have used an OPA810 in unity gain over a 10 MOhm resistor to reduce noise and keep added capacitance low. I used a gimmick to trim the capacitance to the core between the two drive legs, as they were bit unbalanced. Doing this, I saw 0.95 mVRMS (10.5 mV p-p) with my OPA810 probe. I averaged 500 captures using the drive as the trigger because there is too much noise at this level to see what is happening, and I only care about leakage that is synchronized with the drive at the moment anyways. I tested a common mode choke wound some number of times around a nanocrystalline core (the parallel inductance was 150 mH at 10 kHz, and it was a 60 uH/turn^2 or so core. Leakage inductance was about 1.2 uH (!). I added 120 pF shunt capacitance between the grounds as well, otherwise the CM choke is just an LR divider with 10MOhms. This significantly reduced the harmonic content of the leakage. With no gimmick, I got 0.97 mVRMS (3.7 mV p-p) with 25 kHz drive. From previous tests, I know that the drive frequency does not significantly affect leakage, so this is a CM choke effect.It's not clear what the best way is to convert voltage to leakage in this case. For the first example, I could say that the impedance at the fundamental is about 620k, so 0.95 mVRMS would be about 1.5 nARMS. However, the apparent leakage current when connecting an instrument with a 10 MOhm input impedance would be <100 pARMS. Using three op amp instrumentation amplifier made from AD8099s with a gain of 40 dB and a bandwidth of >200 MHz, I saw about 40 uVRMS across the input impedance of 50 Ohms (one input was shorted), so that would be 8 nARMS. Interestingly, there was less high frequency content with the 50 Ohm probe, even though the RC bandwidth is much higher (this is without the CM choke).I am waiting on some bobbins to arrive to try another core with lower A_L, which will let me use L_m as the parallel inductance of the LLC. With nanocrystalline cores, the A_L high enough that I would need something like 3 or 4 windings, which would end up saturating the core with the drive frequencies and voltage I am using. I would like to get the efficiency up to 85% for a 150 mA load and see if further leakage current reduction is possible.

author: julian1
author_rank: Frequent Contributor
timestamp: July 31, 2025, 11:04:32 pm
content: That is a neat trick to put the CM choke after the h-bridge and directly before the transformer.I did a test board with a CM choke on the supply of an H-bridge, and placed optocouplers to communicate drive signals to the half-bridge/leg drivers - but it was so convoluted it felt silly, and I didn't build it.Although it sounds like the CM choke only reduced the harmonic content/rate of CM current, and not the amount (RMS is about the same)- maybe due to parasitic capacitance of the choke.Not that it matters, when the leakage result is already so good, and hard to measure.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: August 01, 2025, 01:27:21 pm
content: Thanks! It is probably best to think of it as a coupled inductor, since the phasing is the opposite of a CM choke. The purpose of using that is really just to ensure that the inductors are matched well to keep the transformer primary drive 180 degrees out of phase with respect to ground. I checked a handful of coupled inductors and found the matching was well within 1%. The (maybe) issue with this is that there is very little series common mode impedance at high frequency, but I don't know whether this is actually a problem.It is tough to say whether the CM choke + shunt capacitor was responsible for the increased leakage current at the fundamental frequency. At this level, small shifts in the transformer windings from soldering things on and washing the board can do that. I also changed the actual points on the ground net on both sides of the transformer where the shields were attached because they are ideally at the points where you are actually measuring the leakage (or where there is little AC current flowing between those two points). That the increase was at the fundamental suggests that the change in shield grounding on the secondary side was not a factor (that would have increased the second harmonic because of the bridge rectifier). It is also possible that there is resonant gain from the parallel capacitance after the CM choke (e.g., from the wires connecting the output to the load and ground). I could add a snubber to check whether that is the case.I built up an error amplifier with a CPC1001N optocoupler to regulate voltage on the secondary attached to the ADC of the MCU driving the bridge, and I was able to get that to be stable. I will need to incorporate reading VDD (with just a D term) into the control scheme because there is too much phase shift to get fast line regulation and have the thing remain stable. It remains in regulation between about 20 and 700 mA load at 16.3V on the output.I attached a scope trace of the converter in open loop operation. Yellow is one side of the primary, magenta is the other H-bridge output, green is VDD (AC coupled), and cyan is leakage across 10M with the OPA810 probe. You can see from the yellow trace that there is some overshoot on the transformer drive. This is related to resonance between the primary leakage inductance and the snubber. It is possible to further damp this with a larger resistor in the RC snubber at the cost of increasing power dissipation. It's not related to the diode conduction you can see in the magenta trace despite the similarity in waveforms. When I adjust the deadtime down far enough to turn on the FET just before the H-bridge diode begins conducting, there is no effect on the overshoot. The bigger issue from a leakage standpoint is the asymmetry between the rising and falling edges around the point where the phase of the bridge changes. This leads to the common mode voltage of the primary drive dropping nearly 1V during the beginning of the switching transitions. Unfortunately I forgot to save the scope traces before adding the CM choke, but I did save the spectrum. The trace colors are the same (but with no magenta trace).

author: julian1
author_rank: Frequent Contributor
timestamp: August 02, 2025, 10:09:49 pm
content: I think I see the overshoot/ asymmetry issue - the magenta side of the primary has squarer turn on/off transitions.Is the slew behavior mostly derived from the lower fet 2.2n DS caps (c17,c11) or RC snubber (r5,c13) ?I tried slowing down switching using the gate/drain inverting Miller capacitance (10k gate resistor, on a ID=7A size nmos/pmos fet) but I dont remember what the transitions around turn-on/off looked like.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: August 03, 2025, 01:25:08 am
content: The magenta trace is actually straight out of the H-bridge, before the series LC network. The yellow trace is one of the primary leads. The primary thing controlling the slew of the transformer drive is the snubber. The DS 2.2 nF caps are there to limit the slew rate of the square wave driving the resonant network because the SRF of the series coupled inductor is 13 MHz. That edge takes about 200 ns, although it is dependent upon the frequency of operation since the energy stored in the resonant tank is what pushes that node up and down (there is ZVS on turn on and turn off in the frequency range this is operating in). The overshoot on the primary drive is from a damped resonance between the leakage inductance of the transformer and the snubber. It seems that low leakage is a nice to have here more than a need to have, within reason.I did try the C-core with the primary and secondary on other sides, and the leakage inductance was pretty bad - about 30 uH for 600 uH primary inductance. The overall leakage performance was about 10x worse. I wound the primary and secondary on the same bobbin with shields in between just to get a comparison, but I haven't run that experiment yet.My current thinking is that nanocrystalline cores are the way to go for this because you can separate primary and secondary without suffering too much leakage inductance. You still need to be in the neighborhood of 10-16 turns on the primary to keep the flux density in the 200-400 mT range (another benefit is the higher saturation flux density). For example, with a 0.85 cm^2 area core with A_L of 90 uH/turn^2, a B_max of 400 mT requires 7 turns (actually about 380 mT) and will still only get you down to 4.4 mH. Getting lower magnetizing inductance means higher peak flux densities and more core losses. For this application, I think the best solution is to have your parallel inductor as a separate component rather than using the transformer magnetizing inductance. Lowering the voltage is no help because the characteristic impedance of the resonant network will need to go down proportionally, as will the inductance of your parallel inductor (for constant m).

author: d-smes
author_rank: Regular Contributor
timestamp: August 03, 2025, 12:22:09 pm
content: Usually when people refer to low-leakage isolated converters for voltage reference use, they strive to minimize the capacitance from input to isolated output. Galvanic isolation is assumed. The 120 pF from primary-side to secondary-side goes against this goal. I understand it's there for EMI reasons but consider that if the transformer had zero in/out capacitance, this 120 pF capacitor would not be needed.I'd suggest having a look at the LLC converter topology discussed inhttps://www.ti.com/lit/an/sluaab9a/sluaab9a.pdf. By placing the resonant capacitor on the secondary side and operating at resonance, they achieve zero-voltage switching AND secondary voltage regulation. Moreover, the transformer design outlined in the link has fairly low primary-to-secondary capacitance. If you look at the whole family of Wurth transformers for this application, they have one that has coupling capacitance less than 1 pF. You read that right- Less than one pico-farad!

author: Kleinstein
author_rank: Super Contributor
timestamp: August 03, 2025, 03:02:42 pm
content: There will be some capacitance in parallel to the transformer from the normal shielding around the isolated part and ground or the environment.So there is no absolute need to keep the capacitance at the transformer super small. The shield to shield capacitance gives a return path for injected current, so limiting the injected voltage.The relevant part is the capacitance times the average voltage at the turns or shield. Ideally one would have near zero voltage with having the right position to connect the shield or have the banance between positive and negative voltage part.So low capacitance helps, but to get really close to zero it is more about good balance and compensation in the voltage.

author: CurtisSeizert
author_rank: Regular Contributor
timestamp: August 03, 2025, 08:48:51 pm
content: I agree with Kleinstein. The gate drive transformer needs to tolerate large dV/dt during switching transients. That is not really the point here, and in any event, reducing absolute capacitance between primary and secondary beyond a certain point will not end up accomplishing anything. If I put a 70 x 100 mm piece of copper clad in a somewhat larger aluminum box that surrounds it on four sides with at least 10 mm clearance, that gives me 15 pF. The mainboard for my application is 180 x 200 mm, and there will be additional shielding that adds capacitance, so I will probably be looking at least 100 pF between PE and isolated ground. The main issue I see for large primary to secondary capacitance is the possibility of conducting common mode currents through this capacitance, and I think the best defense for this is a CM choke with more shunt capacitance on the primary side.If you want C*dV/dt to integrate to near zero over the primary winding, you need a balanced drive and a single layer of turns. Most of the primary to secondary capacitance when the windings are split is series capacitance of each winding to the core. With multiple layers, one leg will couple (capacitively) to the core more than the other, so that transformer may leak like a single ended drive across 1 pF even with a balanced drive.It may be worth trying to put the resonant network on the secondary side, as long as there is some shunt capacitance on the outputs of the H-bridge to slow the edges it may be possible to get better balance on the primary side that way, provided all the propagation delays are reasonably well matched. The converter in this design does also have both ZVS and voltage regulation.I began characterizing the common mode admittance of some transformers to get a better feel for what helps and what seems like it should help but really does not. I used the network analyzer function on an ADP3450, which is pretty good for making bode plots in the frequency range of interest here. I drove the primary with the leads shorted and measured current on the secondary (both leads) using a purpose-built TIA with a gain of 10V/uA and a bandwidth of 160 kHz. I am making a faster one with lower gain but I am waiting on some parts, which will be interesting to see if shielding loses some effectiveness at higher frequencies. The reason for using this over measuring voltage over a shunt resistor is that it is not possible to differentiate between shields just adding more shunt capacitance (so more attenuation due to C-C divider ratio) and them actually shielding above the bandwidth of a shunt resistor probe, which is quite low for a dozen or so pF and 10M.The blue trace shows the admittance of the transformer to common mode leakage in dB(mhos) + 140 (due to the transimpedance gain of the amp). I checked the gain with a GenRad 10 pF standard capacitor and measured -3.87 dB vs the theoretical value of -4.04 dB at 1 kHz. The best performer was the 30 mm nanocrystalline core with split windings and copper tape shielding each winding from the core. I put a piece of copper foil wrapped in kapton tape in the middle to shield direct capacitive coupling in that case as well. The gave -34 dB at 1 kHz for an effective capacitance of 300 fF between primary and secondary windings. When the shield was floating, I measured 12 pF with an LCR meter, and the results here were in line with that. I tried the single bobbin with shield between primary and secondary, but the shunt capacitance was too high and the amp was not stable. That gave the best results with a 10x probe, but it's unclear if that effect was just due to the 100 pF of capacitance between primary and secondary in that case. I tried some SMD flyback transformers I had lying around (with a 10x probe), and they were off the charts as expected.