Cleaning up a square wave?  + DDS help - Page 1
Forum section: electronics / projects

author: BiOzZ
author_rank: Regular Contributor
timestamp: August 15, 2013, 04:01:28 pm
content: Ok first (because it both may be relevant and people always ask) im working on a DDS function generator/clock generatorfor personal use and wont be put in production.... it only has an adjustable duty cycle square wave (invertible) output from 3.3-16vparts are on order and won't come for 5 days (20th)im making this on 2 pieces of per strips in a metal enclosure and it will have (being a DDS) digital signals going on in it and even tho i will do some shielding internally i know i will get some ringing/overshoot and some noise on the signali dont think a low pass filter will work here because its a fast rising (as fast as 10ns) and i want to keep it that way ... it has 50 ohm series impedance but even when matched i think it would cause some issues ...any ideas to clean this up? if not it wont be a major problem as i will use this for applications where i have a basic idea of the frequency needed and i can put some filtering on the side that im using------------------Now for help with the DDS while im here ...it will run from 1hz - 40mhz with 1hz steps BUT i will include 2 x/10 counter/dividers to be able to switch it for more fine adjustments at lower frequencies (i design powersupplies so bringing this past 4mhz i would find a very very rare thing on my side)BUT for the output i need a fast rising output that can handle some current (driving gate transformers and stuff like that) and it only needs to be binary (square wave) in DCSO i chose a MAX4428MOSFET driverto do this ... i am a 2nd year EE student but for a living i design switchmode power supplies so in my mind this would work in theoryYES worse case scenario it has a rise time of 60ns on the inverted output at max temperature and voltage limiting me to (WARNING head math) 16mhz or so in that condition, 30mhz on channel 2 (inverting) best case and 10ns is more than enough for channel 1 (non-inverting) but as i said if i push this over 4mhz than its a strange experiment ...)is there anything inherently wrong with this? i would like it fairly stable but delays from the DDS chip to the output is 100% fine as long as its a linear delay or something i can compensate forand i will probably be driving a mosfet with it anyway XPThank you!------------TL;DRCan i clean up a square wave without harming its rise time?Can i use a MAX4428 MOSFET driver for the output?------------Full disclosureim a 2nd year EE student and work making switch-mode and linear power suppliesexcuse my english ... was NEVER good at this language and i dont need feedback for that ... thank youEDIT: OH i will be posting the schematic for this after i get a little help for you guys to check on another post and give feedback ... open hardware of course ... not much money to be made from a home made DDS square wave generator anyway XP

author: cosmos
author_rank: Regular Contributor
timestamp: August 15, 2013, 04:14:05 pm
content: QuoteI don't see how putting dividers will give you any better fine adjustment, If you want better resolution increase the system clock of the DDS.If you want fine tuning why restrict yourself to 1hz steps?What technology are you designing it in? (mostly see DDS implemented in FPGA or dedicated ASICs)

author: BiOzZ
author_rank: Regular Contributor
timestamp: August 15, 2013, 04:29:04 pm
content: Quote from: cosmos on August 15, 2013, 04:14:05 pmwell my train of thought is 1hz resolution with a max of 40mhz if i divide the output by 10 (dividers placed before the mosfet driver and after the comparator (more info on why i used a comparator coming in the schematic post)) than the 40mhz is brought down to 4mhz and the resolution is also divided giving me 0.1hz resolution at 4mhz maximum ... 100 division would give me 400khz at 0.01hz resolutionfor the DDS chip im using a AD9850 dev board (built in clock, filtering exc with only a few personal modifications i will touch on later) that has a limitation of 1hz at a clock of 125mhz ... i could probably also use a DS1077 as a replacement of the clock on the DDS chip but i find a divider on the output and a software adjustment would work and work simply for what i needam i missing something or did i have a total logical brain fart?

author: cosmos
author_rank: Regular Contributor
timestamp: August 15, 2013, 06:11:07 pm
content: Where did the 1Hz limit come from?Datasheet of the AD9850 says 0.0291Hz resolution with 125MHz sysclk, (this is normally more than enough).Dropping sysclk to 20MHz gives you 0.005Hz resolution.Dividing the output after the comparator might be good to reduce jitter caused by slow transition + noise trough the comparator switch point.I agree the divider gives you even better frequency resolution, it is just normally not needed.

author: BiOzZ
author_rank: Regular Contributor
timestamp: August 15, 2013, 06:26:35 pm
content: Quote from: cosmos on August 15, 2013, 06:11:07 pm... im seriously scratching my head here because im reading that also ... i honestly have no idea where i got 1hzsorry about that i need to update a few things but i think i will keep at least one of the dividersthanks allot for pointing that out for me ... proofreading ... thats why i love you guys XD

author: SArepairman
author_rank: Frequent Contributor
timestamp: August 15, 2013, 06:39:25 pm
content: Out of curiosity what other methods are there for cleaning up square waves? I guess low pass filters are out of the question if there are fast rise times.I am interested in filtering the output of a DDS generator that I bought on ebay for 5$.

author: BiOzZ
author_rank: Regular Contributor
timestamp: August 15, 2013, 06:41:57 pm
content: Quote from: SArepairman on August 15, 2013, 06:39:25 pmone question im trying to get ... might need to make a separate topic for it thoanyone have any good ideas?

author: BiOzZ
author_rank: Regular Contributor
timestamp: August 15, 2013, 06:54:58 pm
content: Quote from: SArepairman on August 15, 2013, 06:39:25 pmincase no one responds my only theroy is using some fast logic like the 74HC line of inverters or buffers ... maybe a very small low pass LC filter (below the rise time), DC coupling and such ... just making sure you only use the one signal on the inverter (not use a leftover inverter for something else) to prevent crosstalk ... or whatever the equivalent of crosstalk is on a non-data signal ...

author: Skimask
author_rank: Super Contributor
timestamp: August 16, 2013, 04:25:22 am
content: Maybe use the sine wave output, thru a high speed comparator, and a divide-by-2 FF?