Loading FPGA configuaration from SPI flash - Page 1
Forum section: electronics / general

author: VSV_electron
author_rank: Regular Contributor
timestamp: April 01, 2023, 09:55:21 pm
content: I need your help on this apparently very simple for you and quite mysterious at the moment for me question. I want to save some time on this, while normally I would try my best to investigate the subject myself.In very simple terms - how does FPGA know if it can be loaded from the onboard flash on power-on? Also at what stage of the programming the configuration one uses the method of storing it to the onboard flash memory if it is available?I'm only scratching the FPGA surface as yet (as a former SW programmer)...I got couple Asian FPGA boards: one with Altera CycloneIV and another with Xilinx Spartan-6. Like many boards, these come with the preloaded configuration that is in my understanding stored on the SPI flash installed on the boards.My question is: Is there a standard method that is used for 'storing to/retrieving from' a given FPGA configuration to/from the SPI flash?Let me elaborate on my question a bit. So far, I've only followed some basic book instructions on creating a simple 'blink' configuration. The basic exercise assumes a clean basic board that has an FPGA that is loaded with a configuration over the standard cable after power-on and discards it on power-off.These Asian boards somehow store the configuration to the SPI flash present on the boards.Could you please point me in the right direction to familiarize myself with apparently not so complicated method of storing the configuration to the flash and loading it to the FPGA on next power-on? Is that a function of what?A board can have an SPI flash on it (obviously connected to the FPGA) and can be designed flash-less as well. So when the flash is present on the board what is the hopefully standardized method to access if from the FPGA?I guess it first should be confirmed that the flash is available for storage and once it's done then there is a mechanism for storing the configuration to it and loading the configuration from the flash on the subsequent power-on(s).

author: langwadt
author_rank: Super Contributor
timestamp: April 01, 2023, 10:25:37 pm
content: there is usually some mode pins that configure where to load the configuration from, e.g. from spi flash and then the fpga loads it automatically on powerupthe tools usually have a way of programming the flash using the standard cable (JTAG)

author: asmi
author_rank: Super Contributor
timestamp: April 01, 2023, 10:26:05 pm
content: It's kind of hard to follow this stream of conscious, but here a few facts which hopefully can answer some questions:1. FPGA can be configured in many different ways, they typically have strap options to specify which configuration method to use. These straps are typically read during FPGA initialization, in some cases for a change in this strap config to take effect, one would require a power cycle FPGA.2. SPI/QSPI is the popular one because QSPI flash chips are readily available, cheap, doesn't not require many pins and is very easy to implement. Some FPGA vendors implemented a way to program such memory devices in-system through JTAG, which is very handy for quick iterations.3. Some FPGAs allow reusing remaining space in a QSPI memory device for application use, this allows consolidating both FPGA bitstream and firmware for a softcore inside a single memory device.4. As (1) notes there are many ways to configure FPGA, QSPI flash is by far the most popular, but there are more, including using BPI (parallel flash), JTAG, some custom serial or parallel protocols which can be used by a dedicated CPU/MCU to configure FPGA from software, some FPGAs can even re-configure themselves dynamically.

author: betocool
author_rank: Regular Contributor
timestamp: April 02, 2023, 12:50:27 pm
content: Like others answered before, check on your board's schematic the position of the "Bootselect" or "boot" pins (I forget the exact name, but something along those lines). Usually they'd have a switch or a pull-up which tells the default configuration at boot time.There's a few options, active or passive. Active mode is normally used to boot and get data from an SPI memory chip. Be aware that you have to flash that memory chip with your FPGA binary, otherwise it loads nothing. Passive mode lets the FPGA be programmed either by a microcontroller or the JTAG interface after reset. There are a few extra options like parallel or serial, compression on or off, etc.Look online for your brand and how to flash the bitstream in nonvolatile memory, there's tons of info. Your board's manufacturer would have some instructions for that perhaps.Hope it helps.Cheers,Alberto

author: iMo
author_rank: Super Contributor
timestamp: April 03, 2023, 10:47:49 am
content: The spi flash is usually loaded with your fpga bitstream (your "fw") via a programmer - there is usually an option to select - either to load the bitstream directly into the fpga, or, into the spi flash. Also you may simply upload the bitstream directly into the spi flash with a spi flash programmer (there is usually a pin on the fpga which tristates the spi flash bus pins such it disconnects from the spi flash).Out of "your user land" (your app in the fpga) the spi flash is accessible via a spi module you have to design in verilog/vhdl, and use it for the data transfer to/from the spi flash (after the fpga loads its bitstream it disconnects itself from the spi flash bus and the pins are free usable out of user land, typically). You would need to design some mechanism to play with the data via your spi module, of course (a sequencer or a small mcu).

author: VSV_electron
author_rank: Regular Contributor
timestamp: April 03, 2023, 06:17:16 pm
content: Thanks much to all the responders!I now know what to look for when exploring this subject. I guess most of the info is in the corresponding FPGA devices' datasheets and probably in the accompanying app notes. Anyway it's useful to know what to look for beforehand.

author: rstofer
author_rank: Super Contributor
timestamp: April 04, 2023, 08:54:03 pm
content: During development (typically Xilinx), I create the image for and program directly to the FPGA, leaving a known good image in the flash. This means I lose the development image on every power cycle but that's not a big deal. Once it seems like my project is working, I beginning programming to the flash.