Tapping into microsecond pulses from a 7400 - Page 1
Forum section: electronics / projects

author: hydrogen maser
author_rank: Regular Contributor
timestamp: October 16, 2016, 12:00:01 pm
content: I'm trying to tap into some pulses passing through a 7400 quad nand gate. The pulses go through 3 of the gates - being inverted - inverted again - and inverted again and finally exiting. Why it was done this way, I don't know, but in any case this looks like a good spot to grab two versions of the pulses - normal and inverted. I tried using a opamp buffer (inverting input shorted to the output), but the "best" opamp I have does not have the slew rate to do it. The pulses are between 500ns and 3 microseconds wide and have a rise/fall time of 10 nano seconds. ultimately I would like to be able to count the pulses, but first I need to tap into them w/o disturbing them too much. Any ideas what method to use?

author: tggzzz
author_rank: Super Contributor
timestamp: October 16, 2016, 12:26:29 pm
content: More information is needed.Is itreallya 7400 - wheredidyou get that? "Count the pulses" with what? "What does "disturb them too much" mean?The key distinction will be the distance involved, the interconnecting media, and the sensitivity of the counter. Once we know that,relevantsolutions can be proposed.

author: hydrogen maser
author_rank: Regular Contributor
timestamp: October 16, 2016, 12:48:40 pm
content: Quote from: tggzzz on October 16, 2016, 12:26:29 pmYes, it is a 7400 quad nand gate made by Fairchild in Singapore in the 49th week of 1985. I could post a pic if you want, but trust me, that is what it is. Counter is later, I will figure that one out, tap in is first. Disturb them too much, I don't know what that means. I don't know how tolerant the rest of the circuitry is to disturbances of the pulses so I was leaning towards opamp buffer, but ran into the slew rate issue. I have access to the pins and plenty of space above the 7400 so, the tap circuity could be as close as a centimeter away. Sorry if there are a lot of unknowns here, just getting started on this one and ran into trouble at the first step.

author: Ian.M
author_rank: Super Contributor
timestamp: October 16, 2016, 01:16:01 pm
content: Run them through a 74HCT00 quad NAND gate. 74HCT inputs are level compatible with original TTL and its bipolar successors but the loading they present is usually negligible (approx 1uA and a few pF). Their outputs are standard 5V CMOS levels. Do *NOT* substitute other CMOS logic families.The 74HCT00 will directly drive short runs of ribbon cable. For longer runs you'll probably need 100R source termination, and to interleave signals and ground wires so no two signals are directly adjacent. Other types of long cables may well need line drivers.Probably the easiest would be to piggy-back the 74HCT00 directly on top of the 7400, with *ALL* its output pins bent out for tapping and all its inputs + power and ground pins soldered to the chip underneath it. If the 7400 is socketed, remove it for soldering and do it with the legs in the air so no solder runs down its pins.As its a 30 year old chip its legs are probably rather oxidised. Clean the outside of the wide part of the 7400 pins with a fiberglass abrasive pencil brush, and use liquid Rosin R or RMA flux applied carefully to ONLY the wide part of its pins with a Q-tip or small artist's brush or similar. If the chip's socketed, don't use synthetic or gel fluxes unless you've got the manufacturer's recommended cleaning solvent for them. Methylated spirits on a Q tip will do a good job of removing Rosin flux residue.

author: hydrogen maser
author_rank: Regular Contributor
timestamp: October 16, 2016, 01:33:11 pm
content: Thanks Ian.M! Just ordered that.

author: tggzzz
author_rank: Super Contributor
timestamp: October 16, 2016, 03:18:31 pm
content: As Ian said, use an HCT device to get TTL compatible input threshold voltages.There are then two potential issues, which may or may not affect your existing circuit, depending on how "close to the edge" it is.If the timings on your existing circuits are critical, then extra capacitance might just be an issue: the extra loading will slow down the edges. Whether or not that affects the existing circuit depends entirely on what the gates are doing, of course.If you are driving a long line and/or a 50ohm load, then there will be current transients. They are dealt with by decoupling capacitors directly across the powers supply pins. Keep ground leads and connections very short.

author: chris_leyson
author_rank: Super Contributor
timestamp: October 16, 2016, 04:02:27 pm
content: Not quite sure why you need 3 TTL gates to buffer a signal, maybe for phase noise performance or the designer just needed to use up spare gates, putting your question into some sort of "application context" might help. But like Ian.M and tggzzz said use a CMOS buffer gate with TTL thresholds HCT or AHCT family and you even piggy back a DIL chip onto the existing part.

author: hydrogen maser
author_rank: Regular Contributor
timestamp: October 16, 2016, 04:24:15 pm
content: Thanks to everyone for the suggestions and info, I do appreciate your time, consideration, and ideas. As to the device - it is a HV (0 to 2000vdc) power supply and pulse counter used for GM or scintillation detectors. I already modified it to have a preamp out (just AC couple the first stage output of the preamp through a capacitor), but I also want the detected pulses out. It has a counter already in it, but I don't think it works very well and I want a pulses out so I can detect them with external circuitry. That will be the next issue, how to count the pulses. At first I thought I would use a monostable multivibrator "one shot" to stretch the pulses, but then I realized that I would likely lose pulses by doing that so now I'm thinking fast enough ADC (500ns = 2mhz - nyquist = 4mhz? not sure it works out that way....) I don't need very many bits - just enough to tell if it is logic high or low (1 bit adc?). I don't care about the dead time so really it is not much data at all if you throw away all the zero samples. Still thinking about how to do it. Suggestions are welcome, perhaps there is an IC out there that does something like this - basically count the number of pulses over a period and report that number. Just realized why there are 3 nands strung together - there is an optional gate input that is not present on my device - that input goes to the middle of the 3 nands, makes sense now.Schematic is here:The 7400 I want to tap into is the three nand gates marked "1" in the upper left section of the schematic.

author: tggzzz
author_rank: Super Contributor
timestamp: October 16, 2016, 04:55:36 pm
content: And at last we get the useful information...Quote from: hydrogen maser on October 16, 2016, 04:24:15 pmExactlywhat are they symptoms that lead you to believe it isn't working very well? Unless you can characterise your problem, it feels like "my experiment isn't doing what I expect, therefore the equipment is faulty".QuoteYou have a habit of complicating things beyond belief. Just what do you think is the difference between a 1-bit ADC and a logic gate? (Optional: with a schmitt trigger input). You have bits: count them.QuoteAnd from that we can see that the extra input capacitance might well affect the operation of that horrible subcircuit. It is horrible because of the 5k1 resistor, the 2nF capacitor and becuse its operation relies on unspecified behaviour.The first thing I would do with equipment of this age is use a scope to look at the Vcc supply to see what ripple/noise is present. Replace electrolytics, e.g. that 4mF 15V and 10uF 16V, and ensure there are ceramic decoupling capacitor across the Vcc/Gnd of each digital IC.If it still doesn't work, then consider connecting Q2 collector to a comparator, and just counting the output from the comparator with external equipment.

author: hydrogen maser
author_rank: Regular Contributor
timestamp: October 16, 2016, 05:12:21 pm
content: Quote from: tggzzz on October 16, 2016, 04:55:36 pmI don't trust it, I have no idea if the number of pulses it reports bears any resemblance to reality or if it is off by a factor of 10, I have no way of knowing because I have nothing to compare it to. So - count em myself and see if they are reasonably close or not. As you say below, the circuitry looks a little hokey to my limited understanding of how circuits might be reasonably be built, but what do I know? Not much, I would never claim to be an expert on any of this stuff, that is why I ask others that know more than me their opinion rather than spend months spinning my wheels on dead ends.QuoteYep, I do tend to do that, guilty as charged.QuoteI replaced all the electrolytic caps before the first time I turned it on. I do that with something of this age as a matter of course. I will take a look at the PS ripple. Of course there are no decoupling caps on any of the IC's. Thanks for all the suggestions, I do appreciate it.

author: SeanB
author_rank: Super Contributor
timestamp: October 16, 2016, 05:34:26 pm
content: Those 3 gates make up a monostable, so the input pulses are a very narrow pulse on the rising and falling edge of the input signal. The input there from the circuit is a simple enable input, so that the counter section does not increment when you have a high on the gate input but holds the last value.To get a pulse from this use another 74 series gate and feed it the output of pin 11 of IC1, which will give you a narrow pulse per edge of the count.Also note there seems to be an error in this schematic, there should be no connection between pins 12 and 13 of IC1, and the same for pins 8 and 9 of IC2. This would otherwise short 2 gate outputs together

author: MK14
author_rank: Super Contributor
timestamp: October 16, 2016, 06:06:03 pm
content: Quote from: SeanB on October 16, 2016, 05:34:26 pmAre you sure ?

author: SeanB
author_rank: Super Contributor
timestamp: October 16, 2016, 06:35:15 pm
content: The output connected back to the input in phase could be to add hysteresis and make a fast pulse time, but Schmitt trigger TTL was around almost from the beginning, and most MSI counters had one on the input, and using one would have saved a gate package there as there would have been 2 spare inverters available to use there in the rest of the design. Would have been done as a single TTL package was expensive, even for SSI parts.Love the total lack of decoupling caps there, which would work with low speed TTL as they are pretty much a constant current part at low frequency, with no real increase in supply current with frequency below 2Mhz or so, when long trace capacitance can cause some, along with the output stage charge storage.

author: Tom45
author_rank: Frequent Contributor
timestamp: October 16, 2016, 06:50:43 pm
content: And what is the deal with Q2?Is it an incorrectly drawn 2N3904 or an incorrectly labeled 2N3906?

author: hydrogen maser
author_rank: Regular Contributor
timestamp: October 16, 2016, 07:12:32 pm
content: Quote from: Tom45 on October 16, 2016, 06:50:43 pmIt is an incorrectly drawn 2N3904 - wrong symbol - 2N3904 on the board and the emitter goes to ground.There is about 100mv peak to peak PS noise on 5v supply - problem?Quote from: SeanB on October 16, 2016, 05:34:26 pmNot sure where you are seeing that, in the nand gates marked "1" on the schematic - first gate - inputs 1 and 2 are shorted, 2nd gate input pins are not shorted and for gate 3 input pins 12 and 13 are shorted - seems like that should be ok. What I don't understand it why there is a .002 cap and 5.1K resistor between the shorted input gates of nand 1 and nand 3 - point of this?

author: edavid
author_rank: Super Contributor
timestamp: October 16, 2016, 08:25:37 pm
content: Quote from: hydrogen maser on October 16, 2016, 07:12:32 pmIt's a Schmitt trigger circuit.https://en.wikipedia.org/wiki/Schmitt_trigger

author: hydrogen maser
author_rank: Regular Contributor
timestamp: October 16, 2016, 08:45:03 pm
content: But why is it needed? The analog signals entering the first nand gate already have very short rise times similar to the nands output - the falling edge is smeared out a little but is still pretty steep and the same width as the the nand square pulse is. If you look at those signals on an oscilloscope it appears as though just the signal hitting the gate should produce the output that it has without any other circuitry or feedback. I am trying to learn why things happen and why circuits are they way they are and this part seems unnecessary and there is a problem with the external gate input - if you have a pulse entering the external gate input (not present on my unit) at the 2nd nand in the chain then that circuitry is not active(?), yet it still works (presumably). Signals entering the first nand gate:

author: tggzzz
author_rank: Super Contributor
timestamp: October 16, 2016, 09:11:45 pm
content: Quote from: hydrogen maser on October 16, 2016, 08:45:03 pmHave you read the wackypedia reference? The key concept is "hysteresis".

author: hydrogen maser
author_rank: Regular Contributor
timestamp: October 16, 2016, 09:35:28 pm
content: Yeah, I read that, but that can't be what is going on and here is the proof:Cap and resistor lifted (angle is bad - believe me - that cap is lifted):Output from pin 11 - final nand gate:Final count (same as others (+/- 10% nature):

author: Ian.M
author_rank: Super Contributor
timestamp: October 16, 2016, 10:10:36 pm
content: I'd tap in at IC9 - it gets you well away from the analog mess around IC1. At that point in the circuit short flyleads to a small protoboard to carry the 74HCT00 shouldn't be a problem. Use one gate with one input tied high to buffer it and the other three paralleled to drive your output, which will give the same pulse polarity as the IC1 output signal.As to what to count it on. Either use an off-the-shelf fast counter/timer (some frequency counters can do this) or if you want to roll your own, Microchip PIC18 family MCUs' Timer 0 can be externally clocked at up to 50MHz with a minimum pulse width of 10ns. Add a fast Schmitt AND gate between the signal and T0CKI with its other input driven by an output compare pin to provide a precision gate, and use a TCXO oscillator to clock the PIC and you should be able to manage 2ppm accuracy. Seehttp://www.microchip.com/forums/m932543.aspxfor discussion of how to design a 100MHz frequency counter based on the same concept. You'd replace the flipflop mentioned by a network of logic gates to permit gating the input from a CCP output + pulsing the T0CKI pin under program control to clock the residual count out of the prescaler, which lets you run Timer 1 as a 24 bit hardware counter.

author: David Hess
author_rank: Super Contributor
timestamp: October 17, 2016, 02:35:17 am
content: Quote from: hydrogen maser on October 16, 2016, 07:12:32 pmThis all makes sense now but the original design was screwed up; it looks like it worked but only by accident. Pins 1 and 2 were not suppose to be shorted and the 5.1K resistor was suppose to pull pin 1 up to +5 volts creating a time constant of 10us.So at idle, pins 1 and 2 are high and pin 6 is high. On the falling edge at pin 2, pin 3 goes high, pin 6 goes low, and pin 6 drives pin 1 low latching the output low for the RC time constant.

author: MK14
author_rank: Super Contributor
timestamp: October 17, 2016, 02:58:43 am
content: I found this.A complete makeover of the entire thing, apparently. Lots of details and new circuits.http://web.csulb.edu/~mmclaugh/GeigerCounter/geigerCounterWriteUp2p0.pdf

author: hydrogen maser
author_rank: Regular Contributor
timestamp: July 31, 2017, 09:40:29 pm
content: I finally had some time to work on this. Per Ian.M suggestion I used a 74HCT00 - input signal to pins 1 and 2 - output pin 3 tied to input pins 4,5,9,10,12,13 of the other 3 NAND gates - output pins 6,8,11 ganged up for the output. Works fine other than some ringing on the rising edge of the output pulses - not a major issue and I think it might be because the coax output is not properly terminated the way I have it hooked to my scope. While I was at it I added the components needed for a gate input (option on the 550 only) - two 2n4401 transistors and a half dozen resistors. The board in my 500 is the M500C and it looks like this board was used for the 550 also with some components not populated for the 500. Interestingly the gate input is split and sent into both the "live" input and the test input, kinda handy (circled in red). I ordered a ALTERA FPGA EP2C5T144 and plan on using it as a pulse counter - not because this is the best solution, but because I want to learn about FPGA's and use them for other things. Thanks to all who helped!PS: the tap board is right over the top of IC9 - Ian.M called it

author: Ian.M
author_rank: Super Contributor
timestamp: July 31, 2017, 10:55:08 pm
content: To drive 50R coax, try a 43R resistor in series with the combined 74HC00 outputs for source termination and terminate the scope end with 50R. However proper termination will halve the amplitude, and the 74HC00 output voltage will drop considerably with each gate sourcing 16.7mA, so the amplitude at the far end may be inadequate*. You'll definitely need a carefully biassed fast comparator to restore it to valid logic levels. Unterminated you can get ringing of double the source amplitude, so unless the termination is hard-wired your input corcuit needs to either clamp or be able to tolerate 10V levels.* You may need to add an octal bus driver with all sections paralleled after the 74HCT00. That would reduce the output impedance so the source termination resistor should be 47R

author: tggzzz
author_rank: Super Contributor
timestamp: August 01, 2017, 07:42:13 am
content: Quote from: Ian.M on July 31, 2017, 10:55:08 pmTo get full amplitude without ringing, you need either source termination (~40ohms series) or receiver termination (50ohms parallel), but not both. There are advantages and disadvantages to each.Alternatively, if a half-amplitude signal is acceptable, you can have both source and receiver termination.When I need urgency, I'll use (74lvc1g* + 143ohm serial)*3 in parallel. The output is so clean and fast I can't measure it accurately; the transition time is in the range 300-1000ps.

author: hydrogen maser
author_rank: Regular Contributor
timestamp: August 04, 2017, 06:24:30 pm
content: I used 50 ohm parallel receiver termination and it fixed the ringing (voltage slightly lower but I think I will need it even lower to go into the FPGA - need to read up on that), however a new(?) problem has appeared. I don't remember seeing this before on the output and I don't see it when I scope the input to the tap. The noise is intermittent - most of the time the output is clean but occasionally this will happen.Update: not seeing the noise now, perhaps my scope probe was not making good contact with the coax output, will keep an eye on it.

author: hydrogen maser
author_rank: Regular Contributor
timestamp: February 10, 2018, 08:07:57 pm
content: So the goal of this project was to see if the Nucleus was accurate or not and now I think we have an answer.Take two of mods to the 500 was to add an enable output that goes high while the 500 is counting. Used the same method as the pulse output - nands connected to U10 at pin 6. External counter is a Saleae clone logic analyzer with Sigrok/Pulseview - trigger on the enable line and a counter on the rising edges of the pulses - 24mhz sample rate. A test count shows 1800 on the Nucleus (60hz X 30 seconds) and 1798 on Pulseview, perhaps the first and last edges are lost due to the way the counter works/how I have it setup, but close enough. So what does a real sample show? Sample is a Uranium doped glaze ceramic plate being looked at by a scintillation detector. 30 second count - Nucleus: 16,414 - pulseview counter: 18,300 so not too much of a discrepancy. I wonder what the Nucleus is missing, pluses too short or too close together or both or something else? Thanks to all who had suggestions on how to do this, I appreciate it.