Why is my FPGA blinky not blinking (iCE40HX8K) - Page 1
Forum section: electronics / general

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 22, 2018, 07:42:27 pm
content: I have just got some FPGA boards back from the fab and am just trying to bring them up by controlling the LED. But for some reason it's not doing what I want.I am using an iCE40HX8K in the 121 bga package and lattice Diamond programmer and iCECube2. Schematic attached. It programs fine via a FT2232H mini module and the done pin asserts after I program it. I can read back the program and verify that it is programmed correctly.(Of the components shown in the schematic, everything is stuffed except C502, C505, C504, C506 which should be fine as I'm not using a PLL yet).My Verilog code:Code:module main(output LED, output DEBUG7);assign LED = 1;assign DEBUG7 = 1;endmoduleMy constraints file:Code:set_io DEBUG7 E2 -pullup noset_io LED J8 -pullup noThe LED D102 should turn on after programming but it doesn't. I've measured the voltage across D102 and it's around 900mV, regardless of whether I set LED = 0 or LED = 1.D102 does turn on if I turn on the internal pull-up however I then cannot turn it off! D102 is also on pre-configuration because the pull-ups are engaged, but turns off once I program the FPGA.(Everything I've said here is also true for pin DEBUG7). 3V3 and 1V2 rails are fine.I'm hoping I'm doing something stupid...Here is the log from iCECube2:Code:"C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\synpwrap\synpwrap.exe" -prj "TestHP2VGA_syn.prj" -log "TestHP2VGA_Implmnt/TestHP2VGA.srr"Copyright (C) 1992-2014 Lattice Semiconductor Corporation. All rights reserved.==contents of TestHP2VGA_Implmnt/TestHP2VGA.srr#Build: Synplify Pro L-2016.09L+ice40, Build 077R, Dec 2 2016#install: C:\lscc\iCEcube2.2017.08\synpbase#OS: Windows 8 6.2#Hostname: DESKTOP-6I79T4A# Wed Aug 22 20:30:08 2018#Implementation: TestHP2VGA_ImplmntSynopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec 5 2016@N|Running in 64-bit modeCopyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.Synopsys Verilog Compiler, version comp2016q3p1, Build 141R, built Dec 5 2016@N|Running in 64-bit modeCopyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\generic\sb_ice40.v" (library work)@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\vlog\umr_capim.v" (library snps_haps)@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)@I::"C:\Users\Matt\Downloads\main.v" (library work)Verilog syntax check successful!File C:\Users\Matt\Downloads\main.v changed - recompilingSelecting top level module main@N: CG364 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Synthesizing module main in library work.At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputimeProcess completed successfully.# Wed Aug 22 20:30:09 2018###########################################################]Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec 5 2016@N|Running in 64-bit mode@N: NF107 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Selected library: work cell: main view verilog as top level@N: NF107 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Selected library: work cell: main view verilog as top levelAt syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputimeProcess completed successfully.# Wed Aug 22 20:30:09 2018###########################################################]@ENDAt c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputimeProcess completed successfully.# Wed Aug 22 20:30:09 2018###########################################################]Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec 5 2016@N|Running in 64-bit modeFile C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\synwork\TestHP2VGA_comp.srs changed - recompiling@N: NF107 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Selected library: work cell: main view verilog as top level@N: NF107 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Selected library: work cell: main view verilog as top levelAt syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputimeProcess completed successfully.# Wed Aug 22 20:30:10 2018###########################################################]Pre-mapping Report# Wed Aug 22 20:30:11 2018Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1612R, Built Dec 5 2016 10:31:39Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.Product Version L-2016.09L+ice40Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)@A: MF827 |No constraint file specified.@L: C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\TestHP2VGA_scck.rptPrinting clock summary report in "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\TestHP2VGA_scck.rpt" file@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)ICG Latch Removal Summary:Number of ICG latches removed:0Number of ICG latches not removed:0syn_allowed_resources : blockrams=32 set on top level netlist mainFinished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)Clock Summary*****************Start Requested Requested Clock Clock ClockClock Frequency Period Type Group Load---------------------------------------------------------------===============================================================Finished Pre Mapping Phase.@N: BN225 |Writing default property annotation file C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\TestHP2VGA.sap.Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)NoneNoneFinished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)Pre-mapping successful!At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 46MB peak: 133MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Wed Aug 22 20:30:12 2018###########################################################]Map & Optimize Report# Wed Aug 22 20:30:12 2018Synopsys Lattice Technology Mapper, Version maplat, Build 1612R, Built Dec 5 2016 10:31:39Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.Product Version L-2016.09L+ice40Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)Available hyper_sources - for debug and ip modelsNone Found@N: MT206 |Auto Constrain mode is enabledFinished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)PassCPU timeWorst SlackLuts / Registers------------------------------------------------------------Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 130MB peak: 133MB)Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 130MB peak: 133MB)@S |Clock Optimization Summary#### START OF CLOCK OPTIMIZATION REPORT #####[0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)0 instances converted, 0 sequential instances remain driven by gated/generated clocks##### END OF CLOCK OPTIMIZATION REPORT ######]Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 133MB)Writing Analyst data base C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\synwork\TestHP2VGA_m.srmFinished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 129MB peak: 133MB)Writing EDIF Netlist and constraint files@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF@N: FX1056 |Writing EDF file: C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\TestHP2VGA.edfL-2016.09L+ice40Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 130MB peak: 133MB)Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)##### START OF TIMING REPORT #####[# Timing Report written on Wed Aug 22 20:30:14 2018#Top view: mainRequested Frequency: 1.0 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.Performance Summary*******************Worst slack in design: NAClock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise--------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack--------------------------------------------------------------------------------------------------------========================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found##### END OF TIMING REPORT #####]Timing exceptions that could not be appliedNoneFinished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)---------------------------------------Resource Usage Report for mainMapping to part: ice40hx8kct256Cell usage:SB_LUT4 0 usesI/O ports: 2I/O primitives: 2SB_IO 2 usesI/O Register bits: 0Register bits not including I/Os: 0 (0%)Total load per clock:@S |Mapping Summary:Total LUTs: 0 (0%)Mapper successful!At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 25MB peak: 133MB)Process took 0h:00m:02s realtime, 0h:00m:02s cputime# Wed Aug 22 20:30:15 2018###########################################################]Synthesis exit by 0.Current Implementation TestHP2VGA_Implmnt its sbt path: C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbtSynthesis succeeded.Synthesis runtime 9 seconds"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\edifparser.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/TestHP2VGA.edf " "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist" "-pBG121" "-yC:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/sbt/constraint/main_pcf_sbt.pcf " -c --devicename iCE40HX8KLattice Semiconductor Corporation Edif ParserRelease: 2017.08.27940Build Date: Sep 11 2017 16:51:25Parsing edif file: C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/TestHP2VGA.edf...Parsing constraint file: C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/sbt/constraint/main_pcf_sbt.pcf ...start to read sdc/scf file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/TestHP2VGA.scfsdc_reader OK C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/TestHP2VGA.scfStored edif netlist at C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main...write Timing Constraint to C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt/Temp/sbt_temp.sdcEDIF Parser succeededTop module is: mainEDF Parser run-time: 1 (sec)"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\sbtplacer.exe" --des-lib "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --outdir "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer" --device-file "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" --package BG121 --deviceMarketName iCE40HX8K --sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\Temp/sbt_temp.sdc" --lib-file "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib" --effort_level std --out-sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdc"Executing : C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\sbtplacer.exe --des-lib C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main --outdir C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer --device-file C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev --package BG121 --deviceMarketName iCE40HX8K --sdc-file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\Temp/sbt_temp.sdc --lib-file C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib --effort_level std --out-sdc-file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdcLattice Semiconductor Corporation PlacerRelease: 2017.08.27940Build Date: Sep 11 2017 17:12:23I2004: Option and Settings Summary=============================================================Device file - C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.devPackage - BG121Design database - C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-mainSDC file - C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\Temp/sbt_temp.sdcOutput directory - C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placerTiming library - C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.libEffort level - stdI2050: Starting reading inputs for placer=============================================================I2100: Reading design library: C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main/BFPGA_DESIGN_epI2065: Reading device file : C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.devI2051: Reading of inputs for placer completed successfullyI2053: Starting placement of the design=============================================================Input Design StatisticsNumber of LUTs:0Number of DFFs:0Number of DFFs packed to IO:0Number of Carrys:0Number of RAMs:0Number of ROMs:0Number of IOs:2Number of GBIOs:0Number of GBs:0Number of WarmBoot:0Number of PLLs:0Phase 1I2077: Start design legalizationDesign Legalization StatisticsNumber of feedthru LUTs inserted to legalize input of DFFs:0Number of feedthru LUTs inserted for LUTs driving multiple DFFs:0Number of LUTs replicated for LUTs driving multiple DFFs:0Number of feedthru LUTs inserted to legalize output of CARRYs:0Number of feedthru LUTs inserted to legalize global signals:0Number of feedthru CARRYs inserted to legalize input of CARRYs:0Number of inserted LUTs to Legalize IOs with PIN_TYPE= 01xxxx:0Number of inserted LUTs to Legalize IOs with PIN_TYPE= 10xxxx:0Number of inserted LUTs to Legalize IOs with PIN_TYPE= 11xxxx:0Total LUTs inserted:0Total CARRYs inserted:0I2078: Design legalization is completed successfullyI2088: Phase 1, elapsed time : 0.0 (sec)Phase 2I2088: Phase 2, elapsed time : 0.1 (sec)Phase 3Design Statistics after PackingNumber of LUTs:1Number of DFFs:0Number of DFFs packed to IO:0Number of Carrys:0Device Utilization Summary after PackingSequential LogicCellsLUT and DFF:0LUT, DFF and CARRY:0Combinational LogicCellsOnly LUT:1CARRY Only:0LUT with CARRY:0LogicCells :1/7680PLBs :1/960BRAMs :0/32IOs and GBIOs :2/93PLLs :0/2I2088: Phase 3, elapsed time : 0.4 (sec)Phase 4W2659: No Constrained paths were found. The placer will run in non-timing driven mode.I2088: Phase 4, elapsed time : 0.4 (sec)Phase 5I2088: Phase 5, elapsed time : 0.0 (sec)Phase 6I2088: Phase 6, elapsed time : 0.0 (sec)Final Design StatisticsNumber of LUTs:1Number of DFFs:0Number of DFFs packed to IO:0Number of Carrys:0Number of RAMs:0Number of ROMs:0Number of IOs:2Number of GBIOs:0Number of GBs:0Number of WarmBoot:0Number of PLLs:0Device Utilization SummaryLogicCells :1/7680PLBs :1/960BRAMs :0/32IOs and GBIOs :2/93PLLs :0/2I2054: Placement of design completed successfullyI2076: Placer run-time: 2.2 sec."C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\packer.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --package BG121 --outdir "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer" --DRC_only --translator "C:\lscc\iCEcube2.2017.08\sbt_backend\bin\sdc_translator.tcl" --src_sdc_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdc" --dst_sdc_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc" --devicename iCE40HX8KLattice Semiconductor Corporation PackerRelease: 2017.08.27940Build Date: Sep 11 2017 16:52:47Begin Packing...initializing finishTotal HPWL cost is 42used logic cells: 1Design Rule Checking SucceededDRC Checker run-time: 1 (sec)"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\packer.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --package BG121 --outdir "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer" --translator "C:\lscc\iCEcube2.2017.08\sbt_backend\bin\sdc_translator.tcl" --src_sdc_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdc" --dst_sdc_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc" --devicename iCE40HX8KLattice Semiconductor Corporation PackerRelease: 2017.08.27940Build Date: Sep 11 2017 16:52:47Begin Packing...initializing finishTotal HPWL cost is 42used logic cells: 1Translating sdc file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdc...Translated sdc file is C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdcPacker succeededPacker run-time: 1 (sec)"C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\sbrouter.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\netlist\oadb-main" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib" "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc" --outdir "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\router" --sdf_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.sdf" --pin_permutationSJRouter....Executing : C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\sbrouter.exe C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\netlist\oadb-main C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc --outdir C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\router --sdf_file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.sdf --pin_permutationLattice Semiconductor Corporation RouterRelease: 2017.08.27940Build Date: Sep 11 2017 17:02:50I1203: Reading Design mainRead design time: 0I1202: Reading Architecture of device iCE40HX8KRead device time: 16I1209: Started routingI1223: Total Nets : 1I1212: Iteration 1 : 0 unrouted : 0 secondsI1215: Routing is successfulRouting time: 1I1206: Completed routingI1204: Writing Design mainLib ClosedI1210: Writing routesI1218: Exiting the routerI1224: Router run-time : 17 seconds"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\netlister.exe" --verilog "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.v" --vhdl "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/sbt/outputs/simulation_netlist\main_sbt.vhd" --lib "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --view rt --device "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" --splitio --in-sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc" --out-sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\netlister\main_sbt.sdc"Lattice Semiconductor Corporation Verilog & VHDL NetlisterRelease: 2017.08.27940Build Date: Sep 11 2017 17:30:26Generating Verilog & VHDL netlist files ...Writing C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.vWriting C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/sbt/outputs/simulation_netlist\main_sbt.vhdNetlister succeeded.Netlister run-time: 1 (sec)"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\sbtimer.exe" --des-lib "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --lib-file "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib" --sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\netlister\main_sbt.sdc" --sdf-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.sdf" --report-file "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\timer\main_timing.rpt" --device-file "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" --timing-summaryExecuting : C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\sbtimer.exe --des-lib C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main --lib-file C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib --sdc-file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\netlister\main_sbt.sdc --sdf-file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.sdf --report-file C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\timer\main_timing.rpt --device-file C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev --timing-summaryLattice Semiconductor Corporation TimerRelease: 2017.08.27940Build Date: Sep 11 2017 17:01:05Timer run-time: 1 secondstimer succeeded."C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\bitmap.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" --design "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --device_name iCE40HX8K --package BG121 --outdir "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\bitmap" --low_power on --init_ram on --init_ram_bank 1111 --frequency low --warm_boot onLattice Semiconductor Corporation Bit Stream GeneratorRelease: 2017.08.27940Build Date: Sep 11 2017 17:29:39Bit Stream File Size: 1080760 (1M 31K 440 Bits)Bit Stream Generator succeededBitmap run-time: 1 (sec)Please spot my mistake!

author: asmi
author_rank: Super Contributor
timestamp: August 22, 2018, 09:10:45 pm
content: I don't have IceCube handy, but I would check if you set up correct Vccio voltages for all banks. Wrong settings can lead to FPGA IO buffers doing funny things...

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 22, 2018, 09:30:21 pm
content: Quote from: asmi on August 22, 2018, 09:10:45 pmVerifiednot solved

author: jmelson
author_rank: Super Contributor
timestamp: August 22, 2018, 10:08:07 pm
content: I don't see a clock anywhere on your schematics.Jon

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 22, 2018, 10:10:13 pm
content: Quote from: jmelson on August 22, 2018, 10:08:07 pmWhy do I need a clock? There will be a clock later on, but do I need one if I'm just using combinational logic?

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 12:14:50 am
content: Ok some new evidence has come to light but I don't know how to explain it.If I tap the board repeatedly with a metal implement (e.g. my tweezers, or a single (floating) multimeter lead), eventually the board comes to life and the led turns on and DEBUG7 goes high etc... It seems like the small amount of voltage on my body from being in an electrically noisey environment can suddenly trigger the FPGA to start responding if I touch it at the right time and right place. You can also see that before the FPGA starts, the LED is lighting up from this voltage.This is very repeatable and seems to happen only with metal objects (makes sense) but I can be touching lots of different places on the board (e.g. ground, random input pins, the LED).I really can't explain what is happening! My power supply is floating (I realise it won't be perfectly floating and there will be some capacitance to earth).Please give me your suggestions?https://youtu.be/RATjZ0fGiv4The red LEDs are power and DONE from the fpga. The geen LED is D102 which should turn on as soon as I program the FPGA.

author: BrianHG
author_rank: Super Contributor
timestamp: August 23, 2018, 12:32:44 am
content: Floating input, like a dedicated chip wide reset, or, global output enable pin. Even if these pins are wired, there may be a cold joint under the BGA...This includes the programming port, including auxiliary JTAG which overrides all the FPGA's functions instantly.Some of these unused pins might be configurable as outputs or a generic data input, which programming them as so would stop this from happening...If these pins are dedicated inputs, well, then you need to tie them to a pullup or pull down, otherwise, you see your problem.Also, don't forget, even if you aren't using them, the PLL VCCs nee to be powered.All unused IO and inputs must be pulled up or down, for the outputs, you can drive them high or low.Scope all your power supply VCCs while programming, you might see the funny thing that happens when floating input pins become active after programming. Hint: Good proper powersupply decoupling caps helps alleviates this...

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 12:58:32 am
content: Hi Brian,The chip's global reset pin must be soldered ok because the programmer uses it during programming... Also if the chip was resetting, the DONE pin would de-assert, which it doesn't.The FPGA doesn't have JTAG, only SPI interface for programming.The problem of the LED not turning on happened even when all unused IOs were pulled up (which is the default setting in iCECube2).The PLLs are powered, R501 and R502 are stuffed, just not the capacitors.Will scope my VCCs tomorrow.Can you explain how a cold joint would cause this to occur? Would you suggest a reflow?

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 01:08:20 am
content: Update: the weird bug with the tweezers works even when there are no floating IOs

author: BrianHG
author_rank: Super Contributor
timestamp: August 23, 2018, 02:10:32 am
content: Your tweezers are acting as a capacitor on that IO line. You need to scope the power supply as close to the IC's programming IO supply as possible.Open contact on slow BGA input pins, like reset, can still work based on just being so close. If the IO pin for the led is so close to the reset which is truly open, the high speed of that IO pin can capacitively bridge to the adjacent open reset input pin with something like a 1-2pf, causing a fluttering loop reset until adding the capaccitive load of the tweezer on that IO slows down the IO to a point where that 1-2pf series bridge to the reset pin wont spike the reset input. Once the led is on, removing the tweezer allows the device to continue to function since the IO stays at one level.No decoupling on the power supply, or, improperly uncleaned flux residue under the BGA can also cause the same problem. Adding a stronger pullup on the reset input will also help prevent the problem.

author: iMo
author_rank: Super Contributor
timestamp: August 23, 2018, 07:38:32 pm
content: If I were you I would1. modify the verilog -> add an input pin,2. connect the input pin with the output to the LED (you may invert if you wish),3. compile and flash into the fpga.While changing the input level observe the LED.2 minutes of work..

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 08:08:30 pm
content: Quote from: BrianHG on August 23, 2018, 02:10:32 amI have scoped directly across the decoupling caps on the underside of the FPGA. I see a massive Vpp pre-configuration when the programmer is connected... like 500mVpp. But after programming this drops to 60mVpp on 3V3 and 120mVpp on 1V2. Regardless of whether all pins are floating or pulled up it is the same.I tried putting a 1,5nF and a 100nF cap across the LED to add capacitance and this did not make a difference.I cleaned the flux off the board with IPA. No difference. Although obviously I cannot clean under the FPGA.I can measure the reverse voltage protection diode on the reset pin a 550mV which is the same as on any of the input pins. This, to me, suggests that it is connected just fine.Quote from: imo on August 23, 2018, 07:38:32 pmGiven what we already know, the LED will stay off until I poke it with my tweezers and the FPGA springs to life at which point the FPGA does exactly what you expect and the LED turns on and off with the input. Nonetheless, I tried it and it does exactly that.Going to try adding 0.01uF decoupling caps in parallel with my 0.1uF caps. But otherwise I am somewhat at a loss other than trying to reflow the board, but that's annoying because I'll have to remove a bunch of components first.

author: jmelson
author_rank: Super Contributor
timestamp: August 23, 2018, 08:35:58 pm
content: Quote from: MattHollands on August 22, 2018, 10:10:13 pmHow's an LED going to blink without a clock? Are you going to command it from something external?Anyway, might check your FPGA synthesis reports to make sure it didn't throw in any FFs that you are not aware of.Very easy for that to happen, as the tools do NOT LIKE totally unclocked designs.Jon

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 08:37:34 pm
content: If you look at my verilog code it's pretty obvious I'm not trying to flash it. The LED just won't turn on. Except when I touch it with tweezers as discussed in the rest of the thrad...

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 08:38:18 pm
content: Adding 0.01uF caps in parallel with the 0.1uF ones did not help.

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 08:49:44 pm
content: If I ground myself the tweezer trick doesn't work.

author: iMo
author_rank: Super Contributor
timestamp: August 23, 2018, 08:58:40 pm
content: Is the R603 populated?

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 09:08:11 pm
content: Quote from: imo on August 23, 2018, 08:58:40 pmYep

author: BrianHG
author_rank: Super Contributor
timestamp: August 23, 2018, 09:17:14 pm
content: DO not add a 100nf cap to the LED. If you want to mimic the tweezers, add a 10pf to 100pf cap across the LED and VCC or GND. Try probing the LED, the scope probe tip may also have the same effect as the tweezers. 100nf will make thing royally worse...When probing the power and probing the reset, is your probe GND connected to near the same cap where you are measuring the VCC. Is your scope set to trigger and capture the slightest voltage spike down at the +/-50mv from target VCC voltage & 10ns/division or less, sampling at full speed? You should be capturing a spike after the PLD boots up, not that large programmer source signal? Is the input channel bandwidth at full using 10x probes?

author: iMo
author_rank: Super Contributor
timestamp: August 23, 2018, 09:20:19 pm
content: It is my understanding you do not use an external flash for the bitstream.Am I right?

author: NorthGuy
author_rank: Super Contributor
timestamp: August 23, 2018, 09:30:03 pm
content: I would suspect the LED is not soldered well. Instead of looking at the LED, probe the voltage on the resistor.

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 09:44:04 pm
content: Quote from: BrianHG on August 23, 2018, 09:17:14 pmWhy will 100nF make it worse? It's after a 2k2 resistor anyway.Probing scheme attached. On the 3v3 rail it is set to about 50mV above and does not trigger at all during programming. 1v2 there is about 100mVpp noise anyway when the programmer is connected. There is an increase in noise measured during programming but no spike stands out. Scope is set to full bandwidth using 10x probes.I don't understand how your theory explains the fact that I can touch ANY FPGA GPIO (even unused ones) and it will start working. These unused GPIOs are not trying to go high, they should just have an internal pull-up resistor. Why would adding capacitance to these pins suddenly make the FPGA work? Will post a video in a minute.Quote from: imo on August 23, 2018, 09:20:19 pmYes programming directly over SPI interface using FT2232HQuote from: NorthGuy on August 23, 2018, 09:30:03 pmIt is soldered fine. Read the rest of the post. A) if the led was not connected then we would still see 3V3 on one of the pins. B) This happens on NC outputs C) it wouldn't start working when I touch other pins.

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 09:46:48 pm
content: @BrianThe pin I touch with my multimeter is completely unconnected in the design. It's pin K1 and yet it still makes the FPGA start working? Can't remember what mode the multimeter is in but the other probe is just floating on the desk.https://youtu.be/iCUSLkI50NA

author: iMo
author_rank: Super Contributor
timestamp: August 23, 2018, 10:01:55 pm
content: Quote from: MattHollands on August 23, 2018, 09:44:04 pmDouble check the programming manual - the R603 should be wired to GND when SPI in slave mode, afaik.SPI_SS_B:Quote

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 10:12:52 pm
content: Quote from: imo on August 23, 2018, 10:01:55 pmFair observation, however the pull-up needs to be there because later I will add an external flash. The programmer pulls the SS_Prog line low during programming to force it into slave spi mode and then brings it high again. Nonetheless, it was worth a try and I connected SS_PROG to ground instead of to the programmer - it still programmed and the same end result.From the Programming and Configuration guide:"The optional 10 KOhm pull-down resistor on the SPI_SS_B signal ensures that the iCE40 FPGA powers up in theSPI peripheral mode. Optionally, the application processor drives the SPI_SS_B pin Low when CRESET_B isreleased, forcing the iCE40 FPGA into SPI peripheral mode."In this case, the application processor is the FT2232H

author: BrianHG
author_rank: Super Contributor
timestamp: August 23, 2018, 10:16:01 pm
content: Quote from: MattHollands on August 23, 2018, 09:44:04 pmI did not know this.QuoteThe spike I want you to check is when the LED tries to turn on. Maybe hook 1 probe to the LED and use that as your trigger, and see what happens on the other signal lines, VCCs, GNDs, Resets, programming CLK & Data linesQuoteOk, this is new info. Begin with my above test.Note that 100mv noise on the 1.2v is close, but should be ok, however, you are measuring at the caps shows less than at the BGA pin which you cannot do. You hope all your power planes vias on your PCB are good, because if you didn't do impedance control during PCB fab, they can be as high as 10ohm from some manufacturers and that would still be considered a pass.It would almost seem that you are missing a VCCIO on a bank somewhere and the touching of a wired floating probe has just enough current and capacitance that the ports internal clamping diodes forces the bank's VCCIO high enough for the IC to operate. Try this, tie that unused IO pin to VCC or GND with a small 100 ohm resistor and see if the IC powers up. If so, you have an open VCCIO or GND somewhere on the BGA.

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 11:01:46 pm
content: The 100Ohm resistor trick didn't work.Attached is the LED, 3v3 and 1v2 during programming. You can see the LED turn on after the chip has been reset. Then there is a bunch of noise that I think is EMI noise from the fact that it's passive probes and long programming leads. After that I can't see a point where the LED tries to go high - I zoomed in,

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 23, 2018, 11:52:53 pm
content: OK, new clues!If I drop my 3V3 rail to 3.22V or lower it works just fine. If I raise the voltage above 3.23V then it doesn't work! What?! It's rated for 3.3V

author: asmi
author_rank: Super Contributor
timestamp: August 24, 2018, 12:30:36 am
content: Quote from: MattHollands on August 23, 2018, 11:52:53 pmThat might mean that overvoltage protection kicks in.

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 24, 2018, 12:31:44 am
content: My best guess is that it is upset because VPP_2V5 is too high if D502 is not dropping enough voltage? It is around 3V

author: asmi
author_rank: Super Contributor
timestamp: August 24, 2018, 12:41:17 am
content: Quote from: MattHollands on August 24, 2018, 12:31:44 amDiode's voltage drop is smaller at low currents. According to datasheet, max current through 2V5 rail is 4.1 mA, which may not be enough depending on the actual diode part you've soldered in. I would remove the diode and botch together a voltage divider to confirm if that's the case. Also try to probe this rail with the scope to see if voltage goes outside the range.

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 24, 2018, 12:55:00 am
content: Quote from: asmi on August 24, 2018, 12:41:17 amI put a 47R resistor from the cathode of D502 to ground to increase the current through it and thus decrease the voltage. This dropped VPP_2V5 to about 2.9V but still the device would not program at 3.3V - therefore I think we can rule out VPP_2V5 as OK.Flush out of ideas though.

author: MattHollands
author_rank: Frequent Contributor
timestamp: August 24, 2018, 01:07:53 am
content: I THINK I CRACKED IT.R503 is too large! I originally designed it to have 649R but replaced it with a 2kR to make the LED dimmer. BUT in the Programming and Configuration guide it says:"However, for iCE40LX/HX devices depending on the system capacitance and configuration frequency,the CDONE pin must be tied to an external pullup resistor connected to the VCCIO_2 supply. The maximumresistor size can be calculated knowing the configuration clock frequency (SCLK or MCLK) and the CDONEtrace capacitance with the following formula:Rpullup=1/(2*ConfigFrequency*CDONETraceCap)"I remember reading this and thinking, "The LED I bought doesn't come with a capacitance spec so I'll base my design on other boards I've seen and if it doesn't work I'll come back to this."

author: asmi
author_rank: Super Contributor
timestamp: August 27, 2018, 04:20:20 am
content: Glad you solved the puzzle!I would still recommend you to work on improving your PDS. FPGAs are infamously picky about good power supplies, and require 5% or better tolerance, which can be a challenge to implement across the entire spectrum of currents. For my projects I had to do few iterations over PDS until I managed to get about 20 mVpp (AC-coupled with 20 MHz BW limit) for Vccint rail (1.0 V) at currents from essentially zero to 2 Amps (didn't test it at higher currents yet). To make things easier for me, I've made a PDS on a separate cheap 2-layer board, so that I didn't risk over $100 worth of ICs on an actual project board, or even more if a respin would be necessary (my main board has 6 layers).