PIC18F SPI SMP = 1 use case? - Page 1
Forum section: electronics / general

author: TrickyNekro
author_rank: Frequent Contributor
timestamp: February 22, 2017, 12:04:39 am
content: Hi,I was playing around with a PIC18F project of mine and SPI and something really sparked my curiosity!From those who don´t know the PIC18F SPI peripheral uses two MISO / SIMO sampling configurations.One is at the middle of the clock period SMP = 0, and the other is at the end of the clock period SMP = 1.When looking at the SPI modes, one would assume that the sampling is done at the middle of the clock period, although modes 0 & 2 might seemnot so well behaved cause the lack of make before break, the modes 1 & 3 offer, that´s for the MSB at least, but I guess they might be "arming" with the state change of the CS pin.So in other words SMP = 1 for the PICs seems like a good solution for buses plagued by relative heavy capacitive loads and / or long cables. Generally the data in is retarded relative to the clock.Other wise the normal use case would be sampling at the middle of the clock cycle, right were the clock is changing state. Or am I missing something?Thanks in advance,Lefteris, Greece

author: David Hess
author_rank: Super Contributor
timestamp: February 23, 2017, 04:20:30 am
content: No, you are not missing anything; sampling can occur after either a 1/2 or 1 clock cycle delay.In an application where the data line needs a maximum amount of time to settle, a delay of 1 clock cycle is used. In an application where the clock might arrive early, a delay of 1/2 clock cycle is used. In most cases, either delay produces the same result.Asynchronous serial receivers usually do something very different by sampling each data bit multiple times, 8 is common, during the duration of the bit and then accepting the majority as the result.

author: bktemp
author_rank: Super Contributor
timestamp: February 23, 2017, 07:22:59 am
content: Microchip itself probably doesn't know exactly what this bit does (or at least does not want to share this information), because there is no datasheet showing the timing specification for SMP=0 mode!And it gets even worse: All timings are shown for SMP=1, but even that timing is shown incorrectly in all datasheets I have seen (all PIC24/dsPIC datasheets and many PIC18F using a similar SPI module): According to the description of the SPI module, it samples the input at the same clock edge as it outputs the data when SMP=1. But when looking at the timing characteristics, it is the other way: For SMP=1 it samples the input at the first edge, and outputs data on the second edge.Just look at this two diagrams taken from a random dsPIC datasheet: The SMP setting works exactly the inverted way for both timing diagrams!SMP=1 when in master mode and SMP=0 in slave mode seems to be the default setting and it seems to be working fine for most cases.

author: bktemp
author_rank: Super Contributor
timestamp: February 25, 2017, 12:16:08 pm
content: I did some measurements trying to find the SPI input sampling timing:Because it is impossible to measure the sampling point directly, I connected SCK through a variable delay line to the SDI pin.I used the most common SPI mode 0 (CKE=1, CKP=0) on a PIC24FJ16GA002 running at 14.9MHz.Here you can see the data I got back when reading from SPI:For SMP=0 it is always missing the first SCK high period, so the sampling point is before the first SCK rising edge.It sees the end of the first SCK high period when delayed by 58ns (for divider=2) and 125ns (for divider=4). That is around 10ns before the next SCK rising edge in both cases.So with SMP=0 it is probably sampling at the same time it outputs the SCK rising edge internally.But what looks strange is the odd duty cycle of the sampled data. The signal going into SDI pin has almost 50% duty cycle like the SCK pin, but the sampled data seems to prefer 0s instead of 1s, especially at higher clock rates.SMP=1 looks a bit more difficult at first glance:For SPI clock divider 2 =(7.46MHz = 134ns) the sampling point seems to be 40ns after SCK rising edge (or 27ns before the falling edge).For SPI clock divider 4 =(3.73MHz = 268ns) the sampling point seems to be 107ns after SCK rising edge (or 27ns before the falling edge).But when looking at the other end of the data (where 1s turn into 0s), we also get a sampling point of 10ns before falling edge.So, to get correct data in all cases, it must be stable at least in the 30ns-5ns window before the sampling SCK edge (the necessary setup/hold time probably gets larger when changing to a different operating voltage or temperature).So the timing diagram shown in the SPI section is correct, but the timing shown in the electrical characteristics section of many (or all?) PIC24/dsPIC33 is wrong, because they show the timing for SMP=0 but say it is for SMP=1.That means I have some controllers with probably marginal SPI timing in the field, because I have trusted the electrical characteristics section, but they screwed up the specs in every datasheet. Well done Microchip.There is probably some difference in timing between different microcontrollers because of the peripheral pin select feature used for routing the SPI peripheral to the IO pins, but the basic behaviour is probably identical for most other PIC families using a similar SPI peripheral.I also tried measuring using SPI clock divider = 1 (14.9MHz is out of specs, only 10MHz are allowed). Here it gets more interesting:For SMP=0 it confirms the 10ns before rising edge.For SMP=1 it now also misses the first SCK high period, because the minimum delay of 7.5ns my delay line generates leaves less than 27ns before the falling edge. If I skip the delay line completely, it is just enough so it can sample the high level. That also confirms the previous measurement.So when using 16MHz SPI clock frequency and SMP=1 the input signal must be stable almost during the full SCK high period. I haven't done any measurements over the full voltage and temperature range, but according to this measurement using 16MHz SPI clock with SMP=1 should be fine. That matches my previous experience with overclocking SPI.

author: David Hess
author_rank: Super Contributor
timestamp: February 25, 2017, 06:58:10 pm
content: The 1/2 cycle difference controlled by SMPI is generated by internally inverting the clock to the shift register so sampling is 180 degrees out of phase with changes in the data output. At least I assume that is what Microchip is doing and the MSSP schematic shows that albeit poorly.At high frequencies, the setup and hold times associated with the data input become a significant fraction fraction of the clock cycle so sampling never really occurs at 0 or 180 degrees and I think that is what you are seeing. The difference is insignificant at low clock frequencies. Some D flip-flops are better than others for this and whatever Microchip used is pretty atrocious with a specified 100ns setup and 100ns hold time; I wonder why it is so bad. The poor setup and hold times explain why SMPI is so important.I have to agree with bktemp about the Microchip schematic shown in their datasheets. It does not show how sampling can occur on the opposite edge from the output clock; there must be more to the shift register than shown. I wonder if their old datasheets had a more accurate schematic.

author: TrickyNekro
author_rank: Frequent Contributor
timestamp: February 27, 2017, 09:08:10 pm
content: Hey! Nice set of data there!Quote from: bktemp on February 25, 2017, 12:16:08 pmSupposedly in mode 0 and mode 2, data (the MSB) is already available at the the DataOut pin of the Slave device.This pin stops being tri-state when the CS line is driven to active level. Either that or it is set at the beginning of the clock period.For SMP = 0, the sampling is happening at the 1/2 of the period but the data line is set at least at the beginning of the clock period.For SMP = 1, the sampling occurs at the end of the clock period.Are you sure about your timing? Cause it seems that, you only send an 0xFF (keep the data line high presumably).It is actually pretty accurately depicted in the datasheet of PIC18F46K80 (micro I am working with right now). I have not checked with the others.Quote from: David Hess on February 25, 2017, 06:58:10 pmIt is not even 0 or 180! It´s either 180° when SMP = 0, or 360° when SMP = 1 (meaning a full clock period has already occurred).And the difference is made clear when you compare slave devices with different SPI modes. I will be comparing two below, the ADT7311 (Mode 3) and the AD7766 (Mode 0).For the AD7766. The Data is available to the SDO pin when the CS pin is turning to active state. So SMP = 0 and SMP = 1 should both work according to the diagram, no problem.For the ADT7311, it might be a bit more difficult to opt out for SMP = 1, as it seems like the timing is more based on the falling edge for setting the output and on the rising to sample.That being said, after the clock line returns to the high state, the SDO pin of the ADT7311 will remain for some nsecs to the previous bit state, but I wouldn´t risk it.So in the end it seems that it all really depends on the slave device also.For what it seems, for Mode 0 and mode 2 sampling time can be more lose. But for Mode 1 and Mode 3 SMP = 0 seems like the way to go.That´s a generalization thou based on 2 devices, the sample is extremely small so I would not consider this a rule of thumb by this point.Cheers,Lefteris

author: bktemp
author_rank: Super Contributor
timestamp: February 27, 2017, 10:00:38 pm
content: Quote from: TrickyNekro on February 27, 2017, 09:08:10 pmThe transmitted data don't care in my test, because I'm using the SCK signal as data by feeding it back into the SDI pin after a variable delay. That allows me to measure SDI sampling time relative to the generated SPI clock.I probably repeat the test sometime, because I want to figure out why the duty cycle of the sampled signal changes.QuoteYes, there is this nice drawing in the SPI section, but there is absolutely no specification in any PIC/dsPIC/PIC24/PIC32 datasheet showing the exact timing specifications/requirements for SMP=1 mode. You can only guess it is the same as SMP=0 mode delayed by 1/2 clock. The diagram helps understanding what the SMP bit does, but if you design a circuit you want hard numbers for verifying your timing.QuoteYes, that is the problem, because we don't have any timing specifications for SMP=1 mode. Assuming it is identical to the SMP=0 mode specifications + 1/2 clock cycle the hold time after falling edge is 40ns for PIC18F and 30ns for most dsPICs.That makes SMP=1 almost useless for most SPI slaves with fast hardware shift registers and only useful for slow SPI slaves with a large delay (>30/40ns SCK to output data change).The AD7766 you have shown has a data access time after SCLK falling edge at 3.0V of 24ns max and no spec for a hold time. So it will be violating the 30/40ns hold time requirement when using SMP=1.ADT7311 is similar: It has 5ns hold time and 80ns data access time, so it will probably violate the requirement, because 5ns < 30/40ns.

author: TrickyNekro
author_rank: Frequent Contributor
timestamp: February 27, 2017, 10:59:30 pm
content: Quote from: bktemp on February 27, 2017, 10:00:38 pmHey, that´s the thing though, the clock has to be retarded relative to the data. You were testing in Mode 0 right?First the data line has to settle, then comes the rising edge of the clock to essentially swift in the data to the micro.Quote from: bktemp on February 27, 2017, 10:00:38 pmThat´s true indeed, that´s why I also started the post. I have been working with the PIC18F46K80, so I can only talk for that right now. There is a lot that is "hidden" and not explained in the datasheet.But, I could perhaps try to draw some conclusions from some "generic" hardware specifications. For example the prescaler.The SPI Module can be sourced clock signal from either the main Fosc or Timer2. When using the main clock, the minimum prescaler is div. 4 and when sourcing from the timer, it is div. 2.Without knowing the innerworkings, we can assume that the action in the SPI module is divided in at least two actions (if not 4, but with Timer2 div. 2 we can rather lean to the 2 factor).So the circuit used and timing as in settling times etc. are the same. Just in one chase the sampling is done after 1/2 clock period, the other case after 1 clock period.So the SMP = 1 timing specs are provided, they just happen exactly 1 / 2 clock periods later than when SMP = 0.Cheers,Lefteris