HDL code for positive edge triggered J-K flip-flop with preset and clear  - Page 1
Forum section: electronics / general

author: caius
author_rank: Regular Contributor
timestamp: June 06, 2021, 11:23:56 am
content: Hi all,I' new to HDL and I'm not yet able to write my own code so I'm using block diagram/schematics under Quartus II.I'm looking for Verilog code (I prefer this over VHDL) to implement TTL gates .I need code for a positive edge triggered J-K flip-flop with preset, clear and complementary outputs (like the 74LS109 for example).Can some one help me?Thanks in advance!

author: cruff
author_rank: Regular Contributor
timestamp: June 06, 2021, 12:13:00 pm
content: Try searching for "verilog jk flip flop" and I expect you will have your pick of examples.

author: caius
author_rank: Regular Contributor
timestamp: June 06, 2021, 01:49:46 pm
content: I did many searches but found only example of JK flip flop with no preset.As aid, I need something like the 74LS019.

author: AndyC_772
author_rank: Super Contributor
timestamp: June 06, 2021, 03:08:55 pm
content: I speak VHDL, not Verilog, so I'm afraid I can't help with your example - but...All too often I see people trying to learn a hardware description language by coding individual logic functions, then trying to build those up into a model of the circuit they actually want - like you'd have to do if you were restricted to building your circuit using off-the-shelf components.I've seen examples that show ridiculously simple logic - like, say, a single OR gate - and wrap it up in a process or even a whole component, then instantiate it at a higher level in order to actually use it. This is kind of OK as a way to demonstrate the syntax of the language, but as a way to learn how to really use HDL, it's terribly misleading.The beauty of an FPGA is that you can describe the behaviour you want without having to worry about how that behaviour might, possibly, be realised using off-the-shelf logic gates. If you're following a tutorial or worked example which does spend more than a trivial amount of time creating complex circuits this way, I'd advise you to look elsewhere. Don't ever get into the mind set of building real circuits directly from these traditional building blocks; that's the job of the synthesis tool, not you.

author: rstofer
author_rank: Super Contributor
timestamp: June 06, 2021, 03:38:44 pm
content: First you need the Truth Table for a JK flop with Presethttps://electronicsarea.com/jk-flip-flop-preset-clear-inputs-truth-table/Pay very close attention to the effect of the asynchronous Preset and Clear inputs.At page 6, there is a VHDL description for a JK flop with Presethttps://web.nmsu.edu/~tturner5/courses/et398/files/reports/TurnerET398Lab6.pdfOn page 7 there is code for the flop. Note how the asynchronous Preset and Clear inputs are handled in the process before the clocking is even considered. These asynchronous inputs mask out any transition change that might occur from the J and K inputs and the clock.I don't use Verilog so transmorgifying from VHDL to Verilog is on you.

author: rstofer
author_rank: Super Contributor
timestamp: June 06, 2021, 05:26:03 pm
content: Here's a video of a Xilinx ISE Verilog project including simulation for a J-K flop with asynchronous Clear. Adding asynchronous Preset is trivial.

author: caius
author_rank: Regular Contributor
timestamp: June 08, 2021, 03:41:44 pm
content: Thank for replies, guys.I wonder if there is some kind of library for 74 TTLs in Verilog (or VHDL, I don't dislike it).

author: emece67
author_rank: Frequent Contributor
timestamp: June 08, 2021, 07:07:08 pm
content: .

author: SiliconWizard
author_rank: Super Contributor
timestamp: June 09, 2021, 12:12:38 am
content: Question of course is: why would you implement basic logic gates and flip-flops in HDL? Other than as an exercise? (Which I suppose it is...)Except for very particular cases, implementing such low-level logic in HDL is a pretty inefficient way of using a HDL. Just saying.

author: BrianHG
author_rank: Super Contributor
timestamp: June 09, 2021, 01:16:35 am
content: The OP never specified that the preset and clear need to be asynchronous.Keeping things synchronous in the FPGA keep the design timing very predictable unless you specifically know your fitter will be using hardware async preset and clear within the logic cells.

author: langwadt
author_rank: Super Contributor
timestamp: June 09, 2021, 01:23:08 am
content: Quote from: SiliconWizard on June 09, 2021, 12:12:38 amnot only inefficient, that kind of async logic is also a bad match for an FPGA

author: NorthGuy
author_rank: Super Contributor
timestamp: June 09, 2021, 04:54:00 am
content: You can build something from logic ICs and there are many of them that you can use.FPGA is built the same way, it has blocks and interconnect. You connect the blocks pretty much the same way as you would connect logic ICs, except blocks are different - you won't fond JK flip-flops in FPGA, but you will find LUTs for example. There's some overlap - for example, D flip flops are present both in FPGA and logic IC series.If you use logic ICs, it will never occur to you to build a LUT because you can use various ready-made gates instead.Similarly, if you use FPGA, there's no point in building JK flip flops, because it's better to use resources which are already present in FPGA.FPGA is actually much easier than logic ICs - the variety of blocks is not anywhere close to the variety of logic ICs and the blocks are more configurable. Not to mention the tools will build circuits for you.