GPIO organization in RT1064 - Page 1
Forum section: electronics / general

author: luiHS
author_rank: Frequent Contributor
timestamp: February 22, 2023, 09:53:29 pm
content: I am using the RT1064 for a project where I need to read, among other things, three data buses of 8 bits each. I have already done something similar with a Kinetis MK66, and I take into account that the ports to be used for each bus must be contiguous GPIO to read them in blocks of 8.In the MK66 the organization of the ports is clearly seen, PTA, PTB, PTC, PTD, and within each port its GPIO pins are numerically PTA1, PTA2, PTA3, etc...In the RT1064 I don't see it clearly, consulting the GPIO table I find, for example,GPIO_AD_B1_00that is increasing up toGPIO_AD_B1_15. I understand that this could be a 16-bit port. However, in the same table they assign another nomenclature to those same pins, which starts withGPIO1.IO, but does not end inGPIO1.IObut extends toGPIO1.IO, how much goes to GPIO1.IO this corresponds to GPIO_AD_B1_00 and continues to GPIO_AD_B1_15.I don't understand how the GPIOs are grouped to consider whether or not they are part of the same port. With other ports I see the same, for example with GPIO_B0 and GPIO_B1, which start with GPIO2.IO and end with GPIO2.IO.GPIO_AD_B0_00 --> GPIO1.IOGPIO_AD_B0_01 --> GPIO1.IOGPIO_AD_B0_02 --> GPIO1.IOGPIO_AD_B0_03 --> GPIO1.IOGPIO_AD_B0_04 --> GPIO1.IOGPIO_AD_B0_05 --> GPIO1.IOGPIO_AD_B0_06 --> GPIO1.IOGPIO_AD_B0_07 --> GPIO1.IOGPIO_AD_B0_08 --> GPIO1.IOGPIO_AD_B0_09 --> GPIO1.IOGPIO_AD_B0_10 --> GPIO1.IOGPIO_AD_B0_11 --> GPIO1.IOGPIO_AD_B0_12 --> GPIO1.IOGPIO_AD_B0_13 --> GPIO1.IOGPIO_AD_B0_14 --> GPIO1.IOGPIO_AD_B0_15 --> GPIO1.IOGPIO_AD_B1_00 --> GPIO1.IOGPIO_AD_B1_01 --> GPIO1.IOGPIO_AD_B1_02 --> GPIO1.IOGPIO_AD_B1_03 --> GPIO1.IOGPIO_AD_B1_04 --> GPIO1.IOGPIO_AD_B1_05 --> GPIO1.IOGPIO_AD_B1_06 --> GPIO1.IOGPIO_AD_B1_07 --> GPIO1.IOGPIO_AD_B1_08 --> GPIO1.IOGPIO_AD_B1_09 --> GPIO1.IOGPIO_AD_B1_10 --> GPIO1.IOGPIO_AD_B1_11 --> GPIO1.IOGPIO_AD_B1_12 --> GPIO1.IOGPIO_AD_B1_13 --> GPIO1.IOGPIO_AD_B1_14 --> GPIO1.IOGPIO_AD_B1_15 --> GPIO1.IO

author: josip
author_rank: Regular Contributor
timestamp: February 23, 2023, 07:42:06 am
content: You can find ports related video and device datasheet pin multiplexing exported to readable excel tables ini.MX RT GPIO/Pin Muxing Spread Sheetssection here ...https://www.utasker.com/iMX/developers.html

author: newbrain
author_rank: Super Contributor
timestamp: February 23, 2023, 09:19:16 am
content: QuoteIt's not you.Itisquite confusing!The idea is thatpads, which are the actual I/O pins, and carry names like "GPIO_AD_B1_06", but also stuff like "PMIC_STBY_REQ", are separated from GPIOs.This is not really that different from having GPIOs "alternate" configurations (such as in STM32s), but means that the pads' names, though not totally arbitrary, do not match the GPIO port at all, albeit most are still called GPIO_something...To add to the confusion, there's also some degree of flexibility in remapping different GPIO ports to the same pad through the use of GPRs (general purpose registers).E.g., GPIO_AD_B1_02 can be either GPIO1.18 or GPIO6.18.I think the RM and DS are quite cryptic, as this info is a bit spread all over, search for the IOMUX description.Note that the different GPIO ports might have different timing and capabilities, notably speed (at least in a 1062, GPIO1 and GPIO6 run from different clocks) and possibly DMA access, so it might matter which one is used!

author: Nominal Animal
author_rank: Super Contributor
timestamp: February 23, 2023, 02:02:25 pm
content: Let's say you use FlexIO 1 and 2 for the 8-bit buses, with DMA. FlexIO 3 does not really support DMA, so I'll assume that's immediately out.Looking at the manual, you find out you need to select contiguous FlexIO pins in each bus (because that's how FlexIO works).Table 10.1 in the manual describes the muxing options.For FlexIO 1, i.e. FLEXIO1_D00 .. FLEXIO2_D15, the pins are GPIO_EMC_00 ... GPIO_EMC_11, GPIO_EMC_26 ... GPIO_EMC_29 (ALT4 set).For FlexIO 2, i.e. FLEXIO2_D00 .. FLEXIO2_D31, the pins are GPIO_B0_00 ... GPIO_B0_15, GPIO_B1_00 ... GPIO_B1_15 (also ALT4 set).Let's say you don't need FlexIO, and can instead do GPIO. Note:only 32-bit access is supported to GPIO registers. DR, DR_SET, DR_CLEAR, and DR_TOGGLE registers can only be accessed in full 32-bit reads and writes! Youcannotdo e.g. a 8-bit DMA writes to one of the four bytes in those registers!(For a GPIO-based bus, on Teensy 4.x MIMXRT1062, I use the DR_TOGGLE register and lookup tables for output parallel buses, sincemsg[curr-1] ^ msgis the set of bus bits to be toggled, and a 2bus_bitslook-up table of 32-bit entries (if the pins are in the same GPIO bank) allows me to quickly update only that specific output bus without affecting the other pins in the same bank, and pick an arbitrary order of the bus pins. Input buses are more annoying.)GPIO1 and GPIO6 are the same bank, with GPIO1 using IPG_CLK_ROOT clock (standard speed) and GPIO6 using AHB_CLK_ROOT clock (high speed).Similarly for GPIO2/7, GPIO3/8, GPIO4/9. You use IOMUXC_GPR_GPR26-29 registers to pick which one each uses.Again, Table 10-1 in the manual is the key.Bank 1/6: GPIO1_IO00-15 are pads GPIO_AD_B0_00-15, and GPIO1_IO16-31 are pads GPIO_AD_B1_00-15Bank 2/7: GPIO2_IO00-15 are pads GPIO_B0_00-15, and GPIO2_IO16-31 are pads GPIO_B1_00-15Bank 3/8: GPIO3_IO00-11 are pads GPIO_SD_B1_00-11, GPIO3_IO12-17 are pads GPIO_SD_B0_00-05, and GPIO3_IO18-27 are pads GPIO_EMC_32-41Bank 4/9: GPIO4_IO00-31 are pads GPIO_EMC_00-31Bank 5: GPIO5_IO00 is pad WAKEUP; GPIO5_IO01 is pad PMIC_ON_REQ; and GPIO5_IO02 is pad PMIC_STBY_REQ.Because of this, most RT106x users resort to creating their own spreadsheets, with physical pads in one column, and various buses and peripherals each in their own column. I know of one for RT1062 as used in Teensy 4/4.1/MicroMod, but not for all RT1062 or RT1064 pads. I myself have made (but not completed; filling in all the data is really drudge work) a static HTML+JS page with the BGA pinout and markable and annotatable alternate functions. I've never soldered BGA, and making anything more complicated than 2-layer boards scares me, I'm that inexperienced on the electronics design side.Exposing one or more parallel buses of the RT1062-based Teensies is a topic that pops up regularly at PJRC forums; even I have considered making my own, for controlling various BuyDisplay/EastRising display modules, as the high-speed USB 2.0 interface (max. 480 Mbit/s) is excellent for various appliances' small external displays, without having to mess with HDMI etc.