Books for learning Verilog as a beginner - Page 1
Forum section: electronics / general

author: hatsune_miku
author_rank: Newbie
timestamp: March 12, 2025, 08:57:48 am
content: Hello i recently got into FPGAs and got myself a Sipeed Tang nano 9k FPGA dev board as it was te cheapestbut i really don know anything about Verilogi do know logics and i have programmed STM32s beforebut Verilog is a whole new thingso any books which would teach me Verilog syntax and programming with optional some projects as examples?thanks!

author: pcprogrammer
author_rank: Super Contributor
timestamp: March 12, 2025, 10:06:06 am
content: There are plenty of resources on the net to learn from.https://www.asic-world.com/verilog/veritut.htmlhttps://www.chipverify.com/tutorials/veriloghttps://nandland.com/learn-verilog/https://www.fpga4student.com/https://www.fpga4fun.com/Keep in mind that writing "code" for FPGA is very different than writing code for a processor. In a FPGA operations are done in parallel, which might not be so clear when writing in a HDL.Within a statement like:Code:always @(posedge clk)beginif(a == b)begin...endif(c == d)begin...endendBoth "if" statements are processed at the same time.To verify logic that you write I can recommend modelsim. There is a free version available from Intel that goes with the Quartus suite.

author: mon2
author_rank: Frequent Contributor
timestamp: March 12, 2025, 07:45:00 pm
content: Adding one of the best sites for Gowin (opensource tool) & verilog tutorial:https://learn.lushaylabs.com/The author uses the 9k Gowin based devkit for most projects.Keep in mind that with open source tools, the toolchain will not be able to support encrypted factory supplied IP. Otherwise, opensource tools are great to use and to learn from.

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: March 14, 2025, 04:57:27 am
content: To be honest, it’s not generally the concepts of verilog being a hardware description, rather than a programming language that I feel is the sticking point; modern software design is so parallel in nature, and the mental model of the “virtual machine” you’re programming to is so inherently parallel (got to use those cores) that it’s not the stumbling block any more. I expect everything to be happening at once these days, I expect data-hazards, and I expect synchronization to be a part of the design, and yes I’m talking about software.I think what is harder is the practicum, the knowledge you learn along the way, things like “how the  am I supposed to understand all those clauses in my clock specification when the ‘F’ine manual ain’t so Fine”, or “great, it works, but too slowly. How do I make it faster”, etc.

author: Mahagam
author_rank: Regular Contributor
timestamp: March 14, 2025, 08:37:15 am
content: I strongly recommend that you read "Digital Design and Computer Architecture" by Harris and Harris. This book doesn't look like a Verilog tutorial, but it describes what can be written on Verilog and how it can be done.This book has 3 versions: MIPS/ARM/RISC-V. From the point of view of Verilog knowledge, they are the same.

author: AussieBruce
author_rank: Regular Contributor
timestamp: March 20, 2025, 10:40:19 am
content: One more point to add to the excellent comments so far. One technique that is fundamental to FPGA coding is the finite state machine. You can get in a terrible mess if you code without having that aspect thoroughly under control. Once you do, HDL coding is way more straightforward.

author: zapta
author_rank: Super Contributor
timestamp: March 23, 2025, 05:31:53 pm
content: Quote from: mon2 on March 12, 2025, 07:45:00 pmApio is an easy to use opensource suite that supports also the Tank 9k. It was inspired by platformio and provides simple commands such as 'apio build' 'apio upload' 'apio test' and 'apio sim', 'apio lint'. It also provides a few sample Tang 9K verilog projects such as this onehttps://github.com/zapta/apio-examples/tree/master/examples/sipeed-tang-nano-9k/blinkyhttps://github.com/FPGAwars/apio/blob/develop/COMMANDS.md(I am a user but also contributed some code).