Simple single-supply, negative ramp/sawtooth generator idea? - Page 1
Forum section: electronics / projects

author: ebastler
author_rank: Super Contributor
timestamp: November 09, 2019, 09:47:17 pm
content: Well, lets face it -- my analog design skills are marginal.So I could use some help...From an FPGA, I would like to drive a simple negative sawtooth output: With approx. 3 kHz repetition rate, set the output "high" (rise time up to 1µs), then let it fall reasonably linearly to the "low" level (for approx. 300µs). "Resonably linear" means within a couple %, so no high precision requirements, but exponential capacitor charge/discharge curves won't be good enough.I have a 3.3V supply available. To drive/trigger the ramps, I can provide one or two (complementary?) digital signals with whatever duty cycles makes sense, toggling them between 3.3V and 0V, or high-Z if that helps. The output does not have to operate rail-to-rail (0V to 3.3V), but at least 1Vp-poutput amplitude would be desirable.There must be a simple solution to this, using an op-amp or two, or an NE555 -- but I have not found any "cookbook" solutions, and can't figure out anything simple myself. Any ideas or pointers are much appreciated!

author: temperance
author_rank: Super Contributor
timestamp: November 09, 2019, 10:57:35 pm
content: I see several options:-A SPI DA converter if you have four pins available-A resistor network DA converter if you have 6 or more pins available.-A resistor network DA converter connected to the outputs of a 74xx595 like shift register if you three pins available.-A PWM output with a low pass filter. (one op-amp, two or four resistors and two capacitors)-An integrator with the non inverting input biased around 1V. (the integrator input is pulled up to the op-amp VCC. To reset the integrator, the input is pulled low with an open collector output with 100R in series connected to the inverting input. Make the integrating capacitor just a few nF)

author: MT
author_rank: Super Contributor
timestamp: November 09, 2019, 11:06:08 pm
content: Dont really understand what you want but you can rearrange a 7555 (dont use 555) to generate up or down ramps or drive it from negative voltage and do the same but then ramps are -V going. Some 7555 can be driven from +2V.

author: temperance
author_rank: Super Contributor
timestamp: November 09, 2019, 11:08:20 pm
content: Attached you will find the integrator based version.For the op amp you will need to select a rail to rail op amp like the OPA350 or something alike.

author: magic
author_rank: Super Contributor
timestamp: November 09, 2019, 11:28:21 pm
content: ICs are boring

author: temperance
author_rank: Super Contributor
timestamp: November 09, 2019, 11:52:24 pm
content: You've beaten me. I forgot about miller integrators although I use those all the time in power rail switches with MOSFET's.

author: Cerebus
author_rank: Super Contributor
timestamp: November 10, 2019, 03:11:31 am
content: Have a look at this posthttps://www.eevblog.com/forum/testgear/test-equipment-anonymous-(tea)-group-therapy-thread/msg1541450/#msg1541450inspired by figuring out how a Tektronix sig gen did separately controllable rise and fall times for triangle/square waves. Obviously for your sawtooth you can swap the controlled fall time half of the circuitry for a simple transistor switch that just dumps all the current in one fell swoop. Biasing's going to be slightly tricky with only 3V3 to play with but that's going to be true of the analogue side of this for any design. Obviously the output is going to call for a buffer if you've got to drive anything other than a high impedance.The current sources that are just shown as ideal ones could be as simple as a JFET with a resistor or even a constant current diode if you can actually find one that isn't grossly overpriced, or you can go with any of the classic current mirror sources.

author: ebastler
author_rank: Super Contributor
timestamp: November 10, 2019, 08:58:27 am
content: You guys are amazing -- thank you! Temperance's "one transistor, one op-amp" solution is what I was hoping for; magic's "just one transistor" is totally baffling to me, as I hadn't expected such a minimal solution!@magic -- I love that minimal solution, and would like to use it. But I struggle with the "floating" reset signal, referenced to the transistor's base. How would I provide that in practice? There must be a way to reset the output to "high" voltage with a ground-referenced signal, but I can't figure it out... Thanks for another bit of help for the analog-challenged!

author: magic
author_rank: Super Contributor
timestamp: November 10, 2019, 09:07:01 am
content: I envisioned a complementary 0/3.3 GPIO drive (hence rser=100) and Hi-Z to replace the diode, but frankly, it isn't that great actually.Trying it out in SPICE shows an output spike on the rising edge, probably because the base of the integrator jumps from 0 to 0.7V when the I/Os go Hi-Z and the capacitor bootstraps the output above the rail.I don't know, a common mode choke could make a 1:1 transformerOr just go with MT's solution, a constant current sink draining the capacitor and a refill by whatever means to trigger another pulse.editOr, you know, you have an FPGA there, right? So hook up a DDS chip to SPI and call it a dayOr digital countdown driving PWM or a 1-bit 1st order delta-sigma modulator to be fancy. Possibilities are endless.

author: ebastler
author_rank: Super Contributor
timestamp: November 10, 2019, 10:46:05 am
content: Quote from: magic on November 10, 2019, 09:07:01 amHey, that actually works quite well! I can live with some overshoot in my application. (By way of background: I want to drive a scope output from my functional replica of a 1950's computer, a bit-serial design. The original computer used a built-in oscilloscope to display register contents. The replica mainly uses a little TFT screen instead, but I want to optionally connect a CRT scope for the vintage look. I have done this with a scope in X(t) mode -- but since the bits are processed low-bit-first and the low bit needs to be shown on the right, that means turning the scope on its head. A tad inconvenient... Hence the need for a falling ramp output, to use the scope in X/Y mode.)QuoteI like the PWM idea, because of its "brutal" simplicity.Just an RC is even better than "just a transistor"... I will give that a try too, thank you for the idea!

author: soldar
author_rank: Super Contributor
timestamp: November 10, 2019, 10:24:16 pm
content: Quote from: ebastler on November 09, 2019, 09:47:17 pmA (constant) current source will charge a capacitor linearly. If you add a diac orUJTor similar circuit it will discharge the capacitor suddenly when the threshold voltage is reached.As has already been said, you can modify a 555 astable oscillator so that the capacitor charges through a constant current source.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 10, 2019, 11:17:52 pm
content: A simple and low-power variant can be built around a JFET (see attached).V1, V2 and S1 are a simple model of a digital I/O driven as '1' (for 1µs) or as Hi-Z (for the rest of the period) alternately, so it's just a small capacitor, a resistor and a common JFET.You will probably need to buffer the output though (with an opamp for instance) depending on what it's going to drive, since loading the output can distort the signal significantly. You can also play with the capacitor value vs. the resistor value (which defines the constant current for the discharge).

author: ebastler
author_rank: Super Contributor
timestamp: November 11, 2019, 07:08:57 am
content: Quote from: SiliconWizard on November 10, 2019, 11:17:52 pmThank you -- that's a nice one! Who would have thought that there is so much to be learned (for me) from that simple application!Thanks for pointing out the potential need for an output buffer. I would like to drive a 50 Ohm cable; some loss of signal level would be OK, but no major distortion of the output. Of course, the need to buffer the output applies to the "single NPN transistor" or PWM solutions too. So now all that remains to be done is to select the solution I actually want to put on my PCB...

author: magic
author_rank: Super Contributor
timestamp: November 11, 2019, 07:15:47 am
content: At this point I might as well shill for my favorite obscure component: the depletion mode MOSFETBut there is a problem with all kinds of FETs and not without reason did SiliconWizard cleverly conceal what happens when the output gets close to groundA bipolar sink could go almost all the way down. Not that you care, so whatever.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 11, 2019, 03:45:12 pm
content: If you really want to do without an opamp for buffering the output for some reason, you can buffer it with just an appropriate MOSFET as a follower (appropriate meaning: must have a low enough VGS(th).)Attached an example - the BSS123 works as an example here, but you can find many other N-ch MOSFETs with a low(er) VGS(th). The output signal will be shifted down.And of course, as magic hinted above, the key here is to choose the discharge current so that the output voltage always stays well above ground (all the more if you're buffering the output!), which is no problem here, since you mentioned that your requirement was a 1Vpp signal, so this circuit is designed assuming you don't care about the exact min and max values as long as the p-p amplitude is sufficient.Design with a comfortable margin, because there's a relatively wide dispersion in the constant current you'll get depending on the JFET.

author: ogden
author_rank: Super Contributor
timestamp: November 11, 2019, 05:25:45 pm
content: You can get reasonably linear capacitor charging curve using simple current mirror.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 11, 2019, 10:41:22 pm
content: I would probably go for a diode from the FPGA output pin, to a cap, with a CCS to discharge it. The Miller integrator is a close 2nd. Add buffers as needed, say to improve ratings, or rise time (FPGA pins tend to be weak, or may be adequate electrical strength but not rated for the kind of repetitive current or C-load this application would have), and to buffer the output (so you don't have to worry about load resistance on the output changing the time constant).Tim