Generating CMOS output levels from differential signals? - Page 1
Forum section: electronics / projects

author: smoothVTer
author_rank: Regular Contributor
timestamp: June 29, 2017, 03:37:20 pm
content: I'm using a nifty little transimpedance amplifier ( MAX3658 ) which takes care of low frequency DC offset and outputs a differential signal from its OUT+ and OUT- pins in response to changing photodiode current. The goal is to use this differential output to generate 3.3V CMOS levels for driving GPIO.Signal characteristics are: 1MHz square wave as an input, 50% duty cycle, 25ns rise/fall times.Since I don't have a SPICE model of the MAX3658, I'm using LTSpice to experiment with this type of conversion in a more general sense. So as an example & starting point:Let's say the detection threshold is Vdth ( Vdth could be 25mV, could be 200mV ... should be able to be tuned by me ) I want a logic low (~0V) when( outP - outN ) < VdthI want a logic high ( ~3.3V ) when(out_P - outN ) > Vdth(1) Is there a single chip solution to accomplish the above task?(2) Can differential line receiver IC's work here? Remember, I am not trying to adhere to a predefined standard like RS-485. I cannot find a monolithic solution which has an adjustable threshold detect, and wondering if such an IC exists.(3) How would the solution change if there was a significant DC offset in the differential signal output? In the illustration above, outP and outN are both referred to the common mode voltage of 1.65V without offset, so the "zero" level is easy to discern since outP and outN are both close to 1.65V. In some cases, the differential output could look like:where there is a large offset between the outP and outN portions of the differential output. Now simply sensing(outP - outN) <> Vdthdoesn't work because they would always be < Vdth.Thanks for reading everybody!

author: Benta
author_rank: Super Contributor
timestamp: June 29, 2017, 04:29:09 pm
content: A comparator with differential inputs should do the trick. Your Vdth can be adjusted by changing the hysteresis.

author: smoothVTer
author_rank: Regular Contributor
timestamp: June 29, 2017, 06:25:02 pm
content: Aren't all comparators differential by nature of their design?

author: Benta
author_rank: Super Contributor
timestamp: June 29, 2017, 07:28:23 pm
content: Yes, but not always used in a differential way. Apologies for poor wording.

author: smoothVTer
author_rank: Regular Contributor
timestamp: June 29, 2017, 09:05:24 pm
content: So how does one use a comparator in a differential way? I have used various families of comparators in single-ended designs and there is no shortage of literature about this. But I cannot find a single reference schematic that shows a comparator interfacing with a differential signal source. Of course there are the classes of "differential line receivers" from TI, Analog Devices etc. but these all seem to adhere to a pre-defined switching thresholds for LVDS, RS-485, RS-422. I wish to define my own switching threshold.

author: Benta
author_rank: Super Contributor
timestamp: June 29, 2017, 10:37:42 pm
content: Quote from: smoothVTer on June 29, 2017, 09:05:24 pmLet me first see if I've understood you circuit correctly.Vcc is 3.3 VVee is 0 VThe outputs from your amp are differential, centered at Vcc/2 = 1.65 VIf this is right, a comparator connected to the two outputs would do the job.outP through a resistor to the NINV input of the comparator.outN through a resistor to the INV input of the comparator (for bias current compensation only, could perhaps be unnecessary).A resistor from the comparator output to the NINV input to set the hysteresis.By varying either the positive/hysteresis feedback resistor, or the NINV input resistor, you can set the trigger levels.Be aware that most comparators have open-collector outputs, so a pullup resistor is needed.

author: edavid
author_rank: Super Contributor
timestamp: June 30, 2017, 12:26:15 am
content: 1. Have you considered AC coupling?2. Why do you need a variable threshold?3. Why would the differential amp have a DC offset?

author: smoothVTer
author_rank: Regular Contributor
timestamp: June 30, 2017, 08:26:44 pm
content: Thanks friends. I am posting results here for posterity in case anyone else wants to use this as a reference for similar designs.(1) From your help above, I've been able to successfully implement my circuit block. It all boiled down to AC coupling the differential outputs, as edavid pointed out, and then waiting for the coupling capacitors to charge to Vcm. Here's the functional circuit and simulation waveforms:Zoomed out, you can see it takes ~75us for outP_acc & outN_acc to settle to the Vcm level:It was indeed necessary to AC couple outN & outP in order to have these signals cross each other symmetrically about Vcm.(2) Originally I thought I wanted a variable threshold in order to tune the comparator to my amplifier's output levels, but this issue becomes moot once you AC couple.(3) I am not sure why this DC offset occurs with the LT1994, perhaps it is specific to this amplifier or otherwise I am not understanding something about the general circuit operation. In any case, here's an illustration. For a gain of 3 as in the circuits above, outP & outN share a common de-asserted level of 1.65V; this 1.65V level is set by the "Vocm" pin on the LT1994 diff amp.If I up the gain to 5, outN is shifted up by 5mV and outP is shifted down by 5mV:Unclear as to why this extra DC offset occurs. My first guess is the LT1994's input offset ( ~2mV ) is getting amplified. In any case, AC coupling solves the comparator problem.