Sinewave Dimming (AC Buck Converter) - Page 1
Forum section: electronics / projects

author: sean6541
author_rank: Contributor
timestamp: December 18, 2020, 02:42:36 am
content: Hi,I am in the process of creating a sinewave dimmer (AC buck converter). It will operate by using high frequency PWM to "chop" the AC waveform, thus reducing the amplitude. Switching will be done by the ESP8266 at 100kHz.For correct operation the dead-time between the switching FET and freewheeling FET needs to be as short as possible. A quick LTspice simulation reveals that a dead-time of just 100ns and load current of 10A will result in capacitor C5 being charged to well over 600v. My current solution is to prototype with different dead-times until I find the optimal.I am wondering if someone with more experience could look over my design and give me some advice. (Schematic and PCB are attached.)

author: NiHaoMike
author_rank: Super Contributor
timestamp: December 18, 2020, 03:52:00 am
content: You figured out why a "solid state variac" is hard to get right. One way to make it easier is to split each of the switches into a pair of switches with diodes across each one, then one switch can be left on each half cycle so that a diode will always be ready to catch the current. But then you end up with similar parts count as a more conventional VFD, so only useful for specialty applications.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: December 18, 2020, 02:18:43 pm
content: Hi sean6541 and the group,I have taken the topology that was proposed by NiHaoMike and made an LTspice model. This has many advantages over the schematic that was proposed by in the first post. It is much more efficient. When the circuit is working there are no diodes in the path. All the switches are synchronous.I am showing the output waveforms for 10, 30, 50 and 90% pwm duty cycle.I have made a reasonable attempt to design input and output filters.I have attached the LTspice model.Regards,Jay_Diddy_Bac_buck.asc(4.09 kB - downloaded 93 times.)

author: mag_therm
author_rank: Frequent Contributor
timestamp: December 18, 2020, 02:32:14 pm
content: Very Good.Can you put a switch in series with the 50 Ohm load ?Increase the run time to about 50 cycles and switch the load on and off during the run time.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: December 18, 2020, 03:25:50 pm
content: Quote from: mag_therm on December 18, 2020, 02:32:14 pmHi,I have placed a switch in series with the 50load. I have timed the switch to turn on and off at various points in the line cycle:Here are pictures of the glitches:and here is the big picture:I have attached the LTspice model.Regards,Jay_Diddy_Bac_buck switched load.asc(4.59 kB - downloaded 57 times.)

author: sean6541
author_rank: Contributor
timestamp: December 18, 2020, 03:46:56 pm
content: Thanks for the quick replies. I hadn't thought of that. Makes much more sense than my current solution.To detect the polarity of the AC cycle I would need to use a comparator, an optoisolator, and a 3rd isolated supply. Rather than using supply modules, I will just use a flyback power supply. Anyone know of an off-the-shelf flyback transformer with 3 isolated secondaries? I've searched but can't seem to find anything. Will probably have to wind my own.

author: sean6541
author_rank: Contributor
timestamp: December 19, 2020, 02:50:39 am
content: I've made the changes suggested by NiHaoMike and I have to say the design seems much better.BTW: Does the comparator-based polarity detector section of the schematic seem okay? I am a bit worried about possible shoot-through occurring around the zero-crossing. The inductor L1 should help to limit any shoot-through current... right?

author: sean6541
author_rank: Contributor
timestamp: December 19, 2020, 10:31:51 pm
content: For those who are interested, I've made some changes to the schematic. It is attached.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 20, 2020, 03:15:41 am
content: Hmm, is that a fully isolated gate driver, not a bootstrap one? Hot damn it is, and boasting quite some speed at that, nice!Yeah, back-to-back switches. Easy. Got fully isolated drivers, need 'em anyway, no reason not to!So dead time: set it as close to zero as you can, or even negative (overlapping). I suppose the driver isn't going to allow that exactly. You can set it to minimum, then skew the gate timing a bit, by using R || (R+D) instead of just R for the series gate elements. In this case, turn-on should be fast (diode pointing towards gate) and turn-off should be slowed down slightly.This is also useful when applied to ordinary synchronous DC-DC converters, where dead-time causes the synchronous diode's body diode to briefly forward-bias, causing reverse recovery losses that act like t_rr of shoot-through. Indeed I've done this many times, to deal with controllers that have fixed internally generated dead time.To ease shoot-through, add some L in series to the half-bridge. This will absorb some flux (volts * time) during turn-on, limiting shoot-through dI/dt equal to that (V = L dI/dt). It does overshoot after commutation, and during turn-off, which needs to be absorbed either with a TVS (e.g. from neutral to Q1 drain), or snubber resistor (you can use an R||L but it's rather wasteful, the R needs to be rather small), or clamp snubber (diode into R||C, in this case a FWB diode -- use high speed diodes BTW).Note that surge protection is a good idea here anyway. Mains is a nasty place, and you don't have any substantial capacitance to deal with it (whereas a typical SMPS has a big fat electrolytic capacitor that can absorb smaller surges). Best results would probably be SiC MOSFETs, 900 to 1200V, for 120 or 240V mains, and a 250VAC MOV at the inlet, and maybe the outlet too. With properly scaled surge protection on the outside, you don't have to worry about exploding a small TVS hanging off the bridge -- a SMDJ size TVS is probably enough (or rather, a few stacked in series to get the required total voltage rating), whereas without surge protection, you need a much bigger one (they do make TVS diodes for mains application -- they're $100s!), and probably suffer from its high capacitance anyway.Or another MOV can be used, but mind their clamping voltages are quite high, typically 2-3x nominal. Hence the 900V+ transistors.Also, note that this (switching loop inductance) is in series with the stray inductance of the switching loop. Keep that to an absolute minimum (with TO-247s and a 2-layer layout, it'll be at least 30nH, and if it's more than 60nH rip it up and redo it!), so that the added inductor, and associated snubber, can dominate. Which means its value should be in the 100-300nH range; which in turn sets a limit on switching frequency vs. power dissipation at given load current (it stores a peak energy at least E = 0.5 L Iout^2, dissipated in full every cycle).Tim

author: sean6541
author_rank: Contributor
timestamp: December 20, 2020, 04:40:35 am
content: Capacitor C2 will have an ESR of about 0.1 ohms. Would that be enough to limit the di/dt of L1?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 20, 2020, 06:36:41 am
content: No, that would be limited by loop inductance and/or gate drive. Consider the typical schematic,Place parasitic elements for every component:When Q turns on, while D (or in this case a synchronous switch) is still on, then the loop Cin-Ls-Ld is short-circuited, and therefore we have the initial voltage Vin and the series RLC tank Cin, Ls+Ld+ESLin, ESRin+Rds(on)+Rds(on). The switching transient (commutation, the ~100ns duration it takes for load current to redirect from one switch to the other, and for switch node voltage to swing between rails) is much shorter than any time constant with Cin (i.e., it's a bypass cap), so we only need be concerned about the ESR, loop inductance, and switch capacitance.When both switches are momentarily on, current ramps up through those total inductances, up to a limit defined by the resistances (or whatever peak current the transistor(s) can carry).Then, when one switch turns off, it transforms from a ~short circuit, into a capacitance. Its current continues to flow, now charging its voltage -- quite rapidly. Now we consider the RLC tank Cin||Cd*, Ls+Ld+ESLin, ESRin+Rds(on). The peak current coming into this phase may be enough to transform to a substantial voltage, 1/4 wave later (sqrt(L*C)*pi/2). If we can apply enough resistance to dampen that peak, we'll keep the transistors happy. We can connect an R+Csnub across each switch, where R = sqrt(L/C) and Csnub >= 2.5 C; if we can get a lumped equivalent inductance, we can put R (R_Ls is shown) or RC there; or we can use an RCD snubber, or other things, to absorb the energy at somewhat lower expense to overall power loss.*Just to be clear, I'm using "||" to mean, apply the parallel formula. Capacitors in series have the equivalent Ceq = C1*C2 / (C1 + C2).These inductances are unavoidable -- they are a manifestation of the physical circuit, proportional to the length of the physical switching loop. A wide aspect ratio (planes in a multilayer board) can reduce this, but you're still limited by the transistors themselves (which have narrow leads and no overlap -- they contribute about 10nH per package). Traces on a 2-layer board are difficult to route well.Improved packages can do better -- the new GaN power transistors, in DFN packages, have a very low profile with wide connections, and amount to just a few nH (a necessity with their extremely low capacitances and rapid switching!). Another option: using multiple transistors wired in parallel with a multilayer bus.Tim