Electricity Energy/Power measure with Different power factor - Page 1
Forum section: electronics / projects

author: Ashraf Almubarak
author_rank: Contributor
timestamp: September 21, 2017, 11:24:26 am
content: I am designing a circuit that measures theenergy consumed(error must be < 1%), by measuring the voltage through potential divider; and current from shunt resistor. Then these two signals go to ADC inputs of microcontroller PIC18F46K80 to be multiplied and get the power.The voltage signal enters a potential divider and an amplifier with DC offset and goes to the ADC input. In current measurement circuit the difference between shunt terminals is amplified and then an amplifier with two feedback resistors (NMOS used to select between them to modify the gain) amplify it again. Then go to a DC offset stage after that to the ADC input.The problem is when the phase change between current and voltage, the energy measurement error changed by0.8%if thepower factor of measured energy changed from 1 to 0.8L.During my work in this circuit I had come with these notes:1- Capacitive coupled noise (in the OPAMP negative input) could affect the measurement if the power factor is changed. But in this case, I am sure it is not because I measure the RMS value in the ADC to check if there is a capacitively coupled noise or not.2- The OPAMP is not 100% inverting, it has some parasitic effects on the phase of the signal that comes to it. It depends on the gain and other stuff.3- I had some DC blocking capacitor that will make a phase shift (time delay), between voltage and current signal, this phase is very small but it affects the measurement accuracy.The points 2&3, I have solved it by making small software delay between acquiring the signal of the voltage and the current to compensate for that phase shift/delay.I have two circuits: Theold oneworks perfectly when the power factor change from 1 to 0.5L. But it suffered from aging of a capacitor as describedhttps://electronics.stackexchange.com/questions/309114/ceramic-capacitance-aging(Ceramic Capacitor Aging Stack Exchange). The accuracy had dropped after 2 months of operation.So I have modified the circuit (NEW ONE) by increasing the capacitors and some resistors to minimize the effect of the capacitor aging. But Now I couldn’t even have an acceptable result, though I have tried adding variable delays between reading the voltage and current from the ADC.New Measurement Circuit Old Measurement CircuitThe Code:Code://================== voltage measurement ==================== //set_adc_channel(VOLT_CHANNEL); //voltage reading channeldelay_us(3); //wait for ADC channel capacitor to chargevoltage_binary = read_adc();delay_us(10);//================== current measurement =====================//set_adc_channel(Current_Channel); //current reading channeldelay_us(3); //wait for ADC channel capacitor to chargecurrent_binary = read_adc();Code:Differences between two designs:Item New Design/Old DesignC16 10uF/4.7uFC7 100uF/47uFOPAMP TL064ID/TL064INSRD9 BAS70/BAV99SResistor Case Code 1608/2012R38 100K/18.2KR35 470K/82KSampling rate (Sample/Second) 3400/2700The Question is: What else could affect the operation of the measurement when the power factor change?

author: MasterT
author_rank: Frequent Contributor
timestamp: September 21, 2017, 02:01:47 pm
content: I'd measure magnitude-phase vs frequency for both, voltage and current channel. Basically, power factor is the ratio of the harmonics content, and any mismatch would reflect itself as error in calculation of the power. Also, it wouldn't hurt to check THD level of your amplifiers, if they introduce some measurable level of harmonics on its own.Do you sample two channels simultaneously?Is there a HPF in software? If so, how linear is it in term phase-frequency?

author: Ashraf Almubarak
author_rank: Contributor
timestamp: September 21, 2017, 02:19:34 pm
content: I will Check the THD of amplifierQ: Do you sample two channels simultaneously?Ans: No, I sample one channel, wait for acquisition time, then the other channel.Q: is there a HPF in Software?Ans: No, no HPF filter, I am using the sampled values directly in the calculations.

author: MasterT
author_rank: Frequent Contributor
timestamp: September 21, 2017, 06:34:08 pm
content: If you can't sample two channels (voltage-current) simultaneously, than make phase shift by linear interpolation on voltage channel, something like N->m = (N->m-1 + N->m) / 2.Here is my code for arduino AtMega328 with linear interpolation and interleaved samplingCode:ISR(TIMER1_COMPB_vect){int16_t adc_value = ADC - adc_Offst;static int16_t last_smpl = 0;if ( smpl_Nmbr < SAMPL_P ){if( smpl_Nmbr & 0x01 ){ADMUX = 0xC5; // Voltage, pin AN5v_s[smpl_Nmbr >>1] = (last_smpl + adc_value) / 2; //Linear Interpolationlast_smpl = adc_value;}else{ADMUX = 0xC4; // Current 3, pin AN4c_s[smpl_Nmbr >>1] = adc_value;}}smpl_Nmbr++;}Precise sampling in time is necessary for accurate results, I see delay() in your pseudo-code, it'd be better to drive ADC by one of the timer, and even synchronize timer to AC frequency, running software PLL with x40-50 multiplier.

author: Kleinstein
author_rank: Super Contributor
timestamp: September 21, 2017, 08:07:45 pm
content: Many µCs have a free running mode for the ADC. So the ADC speed will set the speed. One than has to use a suitable large number of sampled to get enough averaging and preferable an integer number of periods. If the interval is rather long (e.g. 2 seconds) the exact length is not that important any more.Even with capacitive coupling it might be a good idea to still consider a possible DC offset to be corrected in software. Ideally it would also warn about too much DC current.To get close to a kind of simultaneous sampling one could use the average voltage reading from before and after the current reading. Usually the voltage has less higher frequency parts and thus is less effected from averaging. I would guess the µC should be fast enough to do the calculations in real time. So there is no need to store all the data.The circuit might need shields against capacitive coupling. It is quite high impedance in some areas. To reduce capacitive effects the voltage divider might want a capacitor in parallel to the 470 Ohms resistor. With a divider ration of a little over 1000 and a parasitic capacitance of maybe 1 pF, this would be something around 1 nF in parallel to the 470 Ohms. As the speed of the ADC is limited anyway better a little more.

author: Ashraf Almubarak
author_rank: Contributor
timestamp: September 24, 2017, 07:22:52 am
content: I have never thought about interpolation/averaging.I have tried right now and it worked perfectly.The next challenge is to ensure that the phase between the voltage and current signal will remain constant and not affected by the aging of capacitors.Thank you a lot