PLL multiplier or divider have less phase noise? - Page 1
Forum section: electronics / rf-microwave

author: profdc9
author_rank: Frequent Contributor
timestamp: October 07, 2023, 03:44:33 am
content: If I take an oscillator and use a fractional divider in a PLL to multiply the frequency of the oscillator, does it have more or less phase noise or spurs than a fractional divider used to divide a high frequency clock signal down to a lower frequency signal?For example, would the phase noise be less for multiplying a 27 MHz oscillator up to a fractional multiple such as 913 MHz (approx multiply by 33., or dividing from 913 MHz to 27 MHz (divide by 33.? What if the two multiplier and divider have the same loop bandwidth?

author: fourfathom
author_rank: Super Contributor
timestamp: October 07, 2023, 03:58:13 am
content: How does a divider, fractional or otherwise, have a loop bandwidth?Generally, multiplying up with a frac divider in the feedback loop will give you a cleaner signal. But of course this depends on the intrinsic PLL oscillator phase noise, especially beyond the PLL loop corner frequency.A frac divider in the output will have an output jitter if +/- a half-cycle of the PLL clock. Some output divider designs include a tapped delay-line or similar circuit to smooth out that skipped-clock jitter.So the answer is "it depends"

author: profdc9
author_rank: Frequent Contributor
timestamp: October 07, 2023, 04:24:16 am
content: I was thinking of the case where a divider also has a PLL with VCO that is compared to the divided signal with the error signal used to adjust the VCO.I wrote code for the SI5351A that fixes the PLL multiplier as a integer value and uses the divider to adjust the frequency. I did this because I want more than one output to be divided from the same PLL source so that they have a fixed harmonic relationship between the outputs (this is to make orthogonal tones). The details of how this is performed inside the chip are not clear but I thought it might be done with some kind of VCO on the divider multisynth to smooth out the jitter of the fractional divider.

author: ejeffrey
author_rank: Super Contributor
timestamp: October 07, 2023, 04:31:26 am
content: For close-in phase noise, a PLL (ideally) multiplies or divides the noise the same as the signal. So going 27 -> 913 will increase the phase noise, dividing back to 27 will decrease the phase noise.For large offset you just get the free running phase noise of the VCO, divided down by any output dividers.These are the ideal situations, it's possible to do worse by having e.g., analog noise in your loop filter.large and small offset frequency are the same fraction as the ratio of the loop bandwidth to the phase detector frequency.

author: fourfathom
author_rank: Super Contributor
timestamp: October 07, 2023, 05:52:05 am
content: Quote from: profdc9 on October 07, 2023, 04:24:16 amI am using the Si5351 in a similar manner (https://turnislandsystems.com/wp-content/uploads/2023/09/BB-6-Manual-v1.1.pdf), and I'm virtually certain that the output dividers use delay-line tap adjustment for fractional dropped-clock jitter smoothing. These output frac-dividers are much cleaner than a generic frac-divider, but not as clean as the PLL with a frac-divider in the feedback loop. I am seeing output spurs as high as -42 dBc (which is acceptable in my application.)

author: profdc9
author_rank: Frequent Contributor
timestamp: October 07, 2023, 11:07:31 am
content: Is there any information about the difference in spur performance with the divider in the PLL as opposed to the divider in the output? I have looked at a few spur measurements of the SI5351A and they seem to be on the order of the amount you measured, so I wonder if there is a significant difference between the two configurations?

author: fourfathom
author_rank: Super Contributor
timestamp: October 07, 2023, 03:26:44 pm
content: Quote from: profdc9 on October 07, 2023, 11:07:31 amI am sure the measurements are out there somewhere, but I haven't seen a good A/B comparison. There are so many potential combinations of [PLL divider, Reference Clock Frequency, Output divider] in the '5351 that it's going to be hard to draw definitive conclusions. But the general consensus is that setting the output divider to an even integer and modifying the PLL frequency with the frac-div yields a cleaner output.I am starting a new design that uses four Si5351s to get eight outputs, and will be using PLL modulation (via divider changes). One goal is to reduce the output spur level so I will be making some comparison tests before getting too far down that path. I will share the results.

author: szoftveres
author_rank: Regular Contributor
timestamp: October 07, 2023, 03:47:03 pm
content: When dividing down by edge-triggered flip-flops (a simple example is 74HC74, with /Q output connected back to D input), the flip-flop divider circuit discards every second edge of the original incoming signal.After let's say 4 stages, only every 16th edge of the original signal has an effect on the jitter of the output.This makes me think that the divided signal should carry less energy outside the fundamental (and harmonics) than the original signal.

author: 3apw
author_rank: Contributor
timestamp: October 08, 2023, 09:07:43 am
content: May be this note will helphttp://www.ra3apw.ru/proekty/si5351-spectrum/

author: profdc9
author_rank: Frequent Contributor
timestamp: October 09, 2023, 03:30:05 pm
content: So I did try changing over so that the PLL does the fractional multiplication and the multisynth does even integer division, and I compared it to PLL does even integer multiplication and the multisynth does fractional division, and the former (PLL does fractional multiplication) had significantly fewer spurs, usually -60 dBc or even lower, as compared to about -45 dBc for the PLL does even integer multiplication.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: October 10, 2023, 07:23:18 am
content: Isn't it widely known that a multiplication of N gives 20log(N) (dB) more phase noise? As far as I'm aware this is why mixing is sometimes preferred for higher frequency generation as the phase noise doesn't increase as significantly.

author: fourfathom
author_rank: Super Contributor
timestamp: October 10, 2023, 03:39:40 pm
content: Quote from: TheUnnamedNewbie on October 10, 2023, 07:23:18 amThis is true for classic frequency multiplication done by picking off a harmonic of the fundamental. But multiplication by PLL will attenuate any phase noise on the input reference that is above the loop filter corner frequency. Above that corner frequency we are left with the intrinsic PLL oscillator phase noise (which may also be a problem.)And remember that with the Si5351 clock generator there is a digital smoothing filter after the output fractional divider. The spurs from a "normal" frac-div would be much worse (and easier to calculate.) In case anyone doesn't already know this, the Si5351 has two frac-divs in the synthesis chain: one in the PLL feedback loop, and another that divides the PLL output down to the desired output frequency. The '5351 has two PLLs and three outputs. Each output can select either PLL as a source.