Daisy chain shift registers (74HC595) - Page 1
Forum section: electronics / beginners

author: mblyman89
author_rank: Contributor
timestamp: February 02, 2023, 06:53:32 pm
content: Hello. I am curious to know if it is possible to daisy chain multiple shift registers together with all ICs sharing the same clock, latch, OE, and Clear pins. And instead of cascading the data from one to the next, use a separate gpio pin to control the data input of each register? Maybe I am over thinking this, what i am trying to achieve is to activate one of the pins, have it stay on for 1.5s, then turn off. But while that is happening, I would like to be able to activate a second pin that too will stay on for 1.5s then turn off. so far, the only way i know of how to do this is to turn the first one on, then turn the second on, and then turn them both off at the same time. But this scenario leaves the first pin on for too long, longer than the 1.5s i need.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: February 02, 2023, 07:03:34 pm
content: I believe 74HC595 can run at 20MHz or more (apparently upto 100MHz), so you can cascade several million of them to get to a delay of 1.5s.(except when using "arduino", then you're probably limited to 5 or so).But the internals of a 595 only show on its output when you latch the data. So it is the latch you have to control separately and not the data pin. You can shift bogus data through all the others (no matter whether in series or parallel) and as long as you don't latch the data it does not matter (it's only shifted out after 8 clocks).You can also use a combination of series and parallel if you want to have a lot of outputs but still want to keep latency relatively small.you can also use a 74HC138 or similar to reduce the number of uC pins needed for the latches. ... Or other logic, you can even use an extra 74hc595 for this. I'd say order a bunch of them stick them on a breadboard, read the datasheet and start programming and experimenting.

author: langwadt
author_rank: Super Contributor
timestamp: February 02, 2023, 07:14:29 pm
content: the data in the shift register doesn't go to the output until you assert the latch input and you are not limit to one bitclock out 10000000clock the latch -> output is now 10000000wait 0.5secclock out 11000000clock the latch -> output is now 11000000wait 1secclock out 01000000clock the latch -> output is now 01000000wait 1secclock out 00000000clock the latch -> output is now 00000000if you have more shiftregisters you clock out more bits

author: mblyman89
author_rank: Contributor
timestamp: February 02, 2023, 08:08:32 pm
content: Thank you! This explanation is exactly what I needed. I was thinking my design was limited by the hardware, but it is my lack of knowledge of the software and how to write proper code for the registers. But this makes a lot of sense now what you described! I will give that a try.

author: brucehoult
author_rank: Super Contributor
timestamp: February 02, 2023, 09:44:07 pm
content: Quote from: mblyman89 on February 02, 2023, 08:08:32 pmIt is very simple.However many 595s you have daisy chained together, have an array of that number of bytes (char) in your program. Set and clear bits in the bytes in the array however you wish.When you are ready, send all the bits of all the bytes out, using the clock pin and data pin, either completely manually or maybe using SPI hardware if you have it.Then finally use the latch pin to instantly load all new data from the shift part to the output latches in all the 595s at the same time.

author: Benta
author_rank: Super Contributor
timestamp: February 02, 2023, 10:45:58 pm
content: ^ +1That's the way to do it.

author: spostma
author_rank: Regular Contributor
timestamp: February 03, 2023, 07:33:24 pm
content: A point that is often overlooked with daisy chaining 74HC494 devices is that there is acritical timing of the SER input when cascading,for the 'tsu' parameter, SER serial input setup time before the rising SRCLK edge,is less than the 'tpd' parameter, SRCLK to QH' output propagation time.Check the datasheet if you don't believe me ;-)It helps a little if you route your PCB such that the last 74HC494 in the chain is the first one in line from the driving CLK output,so the direction of propagation of the CLK signal is opposite to the propagation of the data signal.Another thing that helps to delay the QH' output a little is to add a resistor like 330R directly to each QH' output of the 74HC595,so there will be about 4 signal bounces between the subsequent chips before a logic level transition arrives at the next input.I would also suggest to use74HCS595devices with schmitt trigger inputs especially if you use longer distances.Of course you could clock every other chip with an inverted clock, but that will take 17 clocks for 16 bits to be transferred.Just my 2 cents...PS. signal propagtion on PCBs is about 15cm/ns, so using long PCB traces to correct timing is not practical...

author: langwadt
author_rank: Super Contributor
timestamp: February 03, 2023, 09:01:15 pm
content: Quote from: spostma on February 03, 2023, 07:33:24 pmthe important timing is that Tpd is larger than ThTsu + Tpd just determines the maximum frequencyQuote from: spostma on February 03, 2023, 07:33:24 pmyes, then it is pretty much guaranteed to work because Th is typically negative

author: Benta
author_rank: Super Contributor
timestamp: February 03, 2023, 09:52:03 pm
content: @spostma, I've no idea what you're describing here.Cascaded 74HC595s are clocked in parallel, and the data clocked into the next stage is the current QH' state. There's lots of time, it's totally uncritical. And the couple of nanoseconds lost in long PCB traces are totally negligible.The only relevant parameter is the QH' hold time, and that's just fine.