Spartan6 + SRAM and NVRAM, looking for a board, before being tempted to develop - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: December 21, 2016, 03:21:45 pm
content: So, I am really tempted to to design a *new* fpga board with 64 Mbyte of sdram and a DIP socket for a NVram (static asynchronous, 3.3V). All of this with a Spartan6 LX9 fpga and an uart-to-usb (dual channels, FTD2232?) adapter, one port for the console, and one for the debugger.Before reinventing the wheel: is already there something similar ? and if not, is someone interested in the new clone ?I am tempted to reload the Papilio/pro project

author: ebclr
author_rank: Super Contributor
timestamp: December 23, 2016, 07:44:49 pm
content: Some reference for youhttp://numato.com/products/fpga-boards/xilinx-spartan6/This 13 USD onehttps://world.taobao.com/item/533900936696.htm?spm=a312a.7700714.0.0.d4ZaMi#detail

author: legacy
author_rank: Super Contributor
timestamp: December 23, 2016, 08:13:02 pm
content: but, none of them comes with NVRAM

author: Someone
author_rank: Super Contributor
timestamp: December 23, 2016, 09:58:07 pm
content: Quote from: legacy on December 23, 2016, 08:13:02 pmThese all come with a large number of uncommitted IO which is fine for sram, they've taken care of the hard work getting the power supplies/bypassing/config all working. Or are you just wanting a layout project to fill your time?

author: legacy
author_rank: Super Contributor
timestamp: December 24, 2016, 12:16:58 pm
content: well, the Papilio/Pro project is also fine, it's an Eagle-CAD project;I can re-design the whole PCB in order to fit my needs.

author: ebclr
author_rank: Super Contributor
timestamp: December 24, 2016, 04:15:03 pm
content: Numato is much more bang for the buck than papiloXC6SLX9 34,95 USDXC6SLX45 140 USDPapilo pro same Spartan 6 LX9 74.99

author: KE5FX
author_rank: Super Contributor
timestamp: December 26, 2016, 03:48:44 am
content: Don't start with Spartan6, go with Artix. Vivado is infinitely nicer than ISE, and has the advantage of not being a dead product.

author: legacy
author_rank: Super Contributor
timestamp: December 26, 2016, 10:38:58 am
content: um,thisboard by Numato looks fine, but it comes with DDR, which is more difficult on the VHDL side.FPGA Device: { XC6SLX16, XC6SLX45 }Memory: LPDDR, 512MBits ~64MbyteNumber Of GPIOs: { 150 }Configuration Options: { JTAG, USB }Primary Clock Frequency: 100MHzso, you are suggesting a development board will suffice for quite some time, and my needs of NVRAM can be achieved piggyback as daughter cards.My own made board just needs to care about the NVRAM chip, so it means less complexity ( power supplies/bypassing/config all working ) by different order of magnitude than developping the whole fpga board.Right?

author: legacy
author_rank: Super Contributor
timestamp: December 26, 2016, 12:09:06 pm
content: Xilinx Spartan 6 FPGAs come with DDR memory controller built-in which makes working with DDR easier

author: ebclr
author_rank: Super Contributor
timestamp: December 26, 2016, 01:46:37 pm
content: WIth few wires you can connect a nvsramhttp://www.cypress.com/file/45831/download

author: legacy
author_rank: Super Contributor
timestamp: December 26, 2016, 07:29:57 pm
content: In my case the NVRAM is a parallel bus device.It needs* 8 lines for the data* 20 lines for the address* 3 lines for the control==================it takes 31 linesI have already written and tested the fsm (vhdl).Now I have to take a decision for the implementation.Currently I am working with a prototype fpga board, wired to a 1000holes board.BTW, I am worried about the DDR. It's not a piece of cake.

author: KE5FX
author_rank: Super Contributor
timestamp: December 26, 2016, 09:13:30 pm
content: Quote from: legacy on December 26, 2016, 07:29:57 pmAs with Spartan6, all mainstream FPGAs will have IP core support for DRAM controller generation. You won't need to write one from scratch. The logic on your side will amount to a reasonably simple state machine to get data in and and out of the controller, maybe 100-200 lines of code at most.If your FPGA board vendor doesn't have documentation and examples showing how to instantiate a DRAM controller, it will not be hard to find one that does. It's not a problem.