PSFB PCMC Low Load - Page 1
Forum section: electronics / general

author: multipla
author_rank: Contributor
timestamp: December 19, 2024, 11:00:31 am
content: Hi all,I am designing a PSFB converter (100 kHz switching frequency, peak current mode control, center tapped transformer (12:1+1), synchronous rectification) with nominal output values of 20 V and 200 A, it's operating from recfitied three phase mains.Mid and full load is working fine, no-load above a certain voltage is also working fine (when using synchronous rectification all the time), short-circuit at the output above a certain current is fine (I have implemented a CC mode).However, when both output voltage and output current go below roughly 10% of the nominal values, I'm having difficulties with the output regulation.The reason (I think) is the primary current sensing circuit. I'm using a 1:200 CT in the DC bus, a 2,7 Ohm sense resistor, then I amplify it and add a slope compensation and give it to a comparator, which compares it to a DAC signal which is generated through the control circuit on a microcontroller. Operating points with small DAC output signal is where I'm having problems.There are some oscillations on the primary current signal which become pretty dominant with low peak current set points. They impair the sensing signal because only the positive part of it goes through the rectification diode which adds to the signal and is difficult to filter out.I have installed a snubber on the CT secondary (in parallel to a 1k reset resistor) and used some (more) analog filtering, which both helped already. I also implemented a blanking period, but because of the oscillations it needs to be approx. 600 ns long. Together with lowering the switching frequency dynamically to 50 kHz and also skipping every second pulse I can get down to 1,7 V at the output, with a 100 mOhm resistor, or to 1,9 V with a 600 mOhm resistor, both at high line (710 V).This is still not enough as I have to get it down to 2% of the nominal value (0,4 V).So, to ask my question: To improve my output range to lower values while using peak current mode control, what options do I have other than skipping more pulses, because it gets into audible range already, which sounds bad?Or is a PCMC PSFB not suited for this kind of range?

author: mtwieg
author_rank: Frequent Contributor
timestamp: December 19, 2024, 07:26:37 pm
content: Quote from: multipla on December 19, 2024, 11:00:31 amHaving trouble parsing this... could you show an example waveform of the CT output signal? What sort of pulse width/duty cycle does this issue occur at?QuoteIs your objective to have an adjustable output voltage with a wide range? Is your voltage feedback able to work with such low voltages (a typical TL431+opto circuit wouldn't work).QuoteI don't think PSFB is particularly unsuitable for wide line/load ranges (as compared to LLC which is pretty bad). For light load conditions, are you emulating diodes with the synchronous rectifier FETs, or are you operating in "forced ccm" mode?

author: jbb
author_rank: Super Contributor
timestamp: December 20, 2024, 06:25:07 am
content: 20V and 2000A is pretty high power. Nice!It sounds like this might be a job for pulse skipping mode. The basic idea behind the approach is to replace a continuous series of tiny-and-don’t-work-right pulses with a few sparse large-enough-to-work-right pulses (hence the name).

author: multipla
author_rank: Contributor
timestamp: December 20, 2024, 08:07:22 am
content: Quote from: mtwieg on December 19, 2024, 07:26:37 pmOkay, I'll explain it in a bit more detail. It's easier to see in the simulation, so I'll refer to these waveforms, but I'll also attach two measurements showing it in the prototype. It starts getting problematic at peak current levels that would demand an on-time of below 600 ns (which is a duty cycle of 600 ns / 5 μs = 12 % before duty cycle loss through the resonant inductor).First, an example how it looks good and works well, input voltage at maximum and output power at maximum. Green (I(L6)) is CT primary current, blue (I(L14)) is CT secondary current, V(Iprim) is the voltage across the CT sense resistor and V(Iprim_F) is the same signal after a filter.Note the CT currents at the marker position (passive-to-active transition, dashed line), it goes negative (normal with PSFB*) with some ringing. I think this is what causes the problems at lighter load, at the next picture:The negative peaks are of course still there, together with the ringing the signal also goes positive though. The rectification on the CT secondary is the usual single diode. Through this rectification only the positive part of the ringing comes through, which then, after filtering, causes a bump in the measurement signal at the beginning of the active phase. I have to use leading edge blanking to ignore that part currently.Here are comparable measurements in my prototype. Yellow / CH1 is equal to V(Iprim) in the simulation, the voltage across the CT sense resistor. Green / CH2 is after the filter, Blue / CH3 is the voltage between the switching nodes and red / CH4 is the transformer primary current.Output at 8,38 V, 90 A:Output at 1,68 V, 18 A. This still works stable, but when I go lower than this, the controller outputs 0 peak current set point but it can't go lower because of the leading edge blanking:QuoteYes. CC and CV mode down to 2% of the nominal values.QuoteI measure output voltage and output current with a 2 channel ADC over SPI. I tested that circuit and it works well too. It's also not what is causing my problems at the moment, the digital controller's output is stable and all.To have it working stable, I have a leading edge blanking of ca. 600 ns at the moment. When I reduce it down to below 350 ns or so, the CMC-Comparator starts triggering on the first "bump" in the primary current signal too, which leads to erroneous jumps in the duty cycle.I don't really know how to fix this now, I only see the options of getting rid of the leading edge oscillations (but how?) or reducing the effective duty cycle by skipping pulses/lowering switching frequeny/using burst mode.Am I missing some option?QuoteI made the above measurements with forced CCM. I also tried turning off the synchronous rectifiers together with pulse skipping at low loads, but that doesn't improve the situation, it even makes it worse, because in DCM the output voltage is even higher at the minimum duty cycle.* This is a point I don't understand fully yet. PSFB have a small, negative input current spike after the passive-to-active transition (see first simulation picture). This has to go through the CT, but, as it is in reverse direction than the normal sense signal, the impedance during that time is very high as the CT secondary diode blocks, so the impedance is mostly that of the CT primary inductance, which is quite high (2 μH in my case).Is this correct?Does this cause problems, maybe even my problem here (the ringing)?Why do all the application notes from TI, Microchip, ST, etc. do it like this then?Is there a "better" way?Thanks for the input so far.Quote from: jbb on December 20, 2024, 06:25:07 amOnly 200 A, but yes, thanksQuoteI already have pulse skipping and it works, but at the moment not enough. I can make it skip even more pulses, but it already gets into the audible range rather loudly and I have to increase the output capacitance probably, so I am looking for other options as well.Thanks.

author: mtwieg
author_rank: Frequent Contributor
timestamp: December 20, 2024, 12:38:43 pm
content: Quote from: multipla on December 20, 2024, 08:07:22 amThanks, you've explained the problem clearly. Filtering after rectification leads to the "bump" being large.QuoteMakes sense. Usually forced CCM makes control easier (more consistent transfer function over line/load variation)...QuoteRight, I believe the negative spike is the result of the converter's ZVS operation (the transformer and leakage inductance must source energy back towards the bridge in order to get soft switching).QuoteAll of my experience with PSFB is with lower bus voltages, where I use a shunt resistor+current sense amplifier, so admittedly I've never had to deal with this... but 2uH sounds very large for the CT primary. My gut tells me it should be far less than L5 (L9 and L5 will effectively form a voltage divider when D9 is reversed biased).QuoteNot sure. Perhaps it contributes to the high frequency ringing. But even without that, you would still see some negative spike in CT current (so long as the bridge is still operating in ZVS).It might be worthwhile to replace the CT in LTspice with a more ideal (bidirectional) current sensor, just to see if that helps.

author: jbb
author_rank: Super Contributor
timestamp: December 21, 2024, 12:32:13 am
content: On the burst mode: have you identified which components are the source of the noise? If it’s the magnetics, could you perhaps pot them with an appropriate compound?For noise finding, I have heard that you can glue a thin plastic or wooden stick to the bottom of paper cup. When you press the stick against a noisy component, vibrations will travel up the stick, into the paper cup and then into the air.