Suggested low pass filter for a DAC - Page 1
Forum section: electronics / projects

author: peter-h
author_rank: Super Contributor
timestamp: November 30, 2021, 07:53:33 am
content: What would be the best approach for filtering this stepped sinewavehttps://www.eevblog.com/forum/microcontrollers/32f417-a-cunning-way-to-reset-two-dma-pointers-from-an-edge-on-a-pin-etc/msg3841010/#msg3841010I reckon Sallen-Key is probably the most effective, using just one op-amp.I also need a gain of 2x (Ra=Rb) so C1 is likely 0.5xC2, but beyond that I am not sure, apart from trying out different values.It is 400-500Hz and 64 steps per cycle. I can go to more steps and obviously that makes it easier but there are issues which drive 64.I would like the phase lag variation between 300 and 600Hz to be less than 1 degree - because I am compensating for it by shifting the sin(x) table. I think this can be achieved but mainly by having the -3db rolloff well into the kHz range.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 30, 2021, 08:39:56 am
content: Phase or gain flatness: pick one. Flatter phase in the passband leads to peaked gain at the transition frequency. For a minimum-phase (standard all-pole) filter, anyway.Flatter phase through the transition band, leads to soft gain rolloff. Bessel is defined as minimumgroup delay, which in turn is defined as dPh/dF, so the phase changes more gradually for that type. Note that phase still has to go through whatever range corresponds to the filter order (through transition to stop band), so you can't have flat (as in constant for all frequencies) phase, and filtering at the same time.Or, you delay the passband to slow it to match the stopband delay, which obviously doesn't work all the way down to DC, but is technically applicable for bandpass filters. You can have basically any phase shift at any frequency, using all-pass filters (while keeping flat gain), but not minimum phase: you can't speed anything up, of course, you have to slow everything else down.The whole question seems academic since, as you say, you'll use a compensation table. Maybe you just want the sharp corners to propagate correctly (when settings are changed suddenly)?BTW you can get a 3rd order for free, put an RC out in front. This changes the input impedance to the rest, so all the values have to change of course.Also, MFB has better high frequency attenuation than SK (N-1 poles direct to GND, whereas SK has the feedforward path R1-C1), but is inverting. (Since you're generating a sine, I don't see why it can't be complemented automatically, but whatever.) MFB is also less sensitive to component values/tolerances than SK; but the difference isn't enough to matter for such a low order filter. I have no problem using either, here -- this is just informational, really. If you have further requirements, maybe it would motivate one over the other.64x sounds like a rather low sample rate, especially for such a capable MCU. But I haven't been following that thread, I don't know. To get rid of the steps, you need a cutoff somewhere between [intended signal] and Fs/2, and enough attenuation by >Fs/2 to get the steps smoothed out (time-quantization noise down to noise floor, say). This defines the filter order and sample rate. Oversampling is great value to reduce analog requirements, allowing a lower order filter.Tim

author: peter-h
author_rank: Super Contributor
timestamp: November 30, 2021, 08:54:26 am
content: I am trying toremovethe steps.The variation in the frequency will be very slow - over minutes or hours.I can generate >1000 samples with the hardware, before running out of the DAC feed rate limit (DAC settling time). The reason for just 64 samples is because I am doing some amplitude variation and this needs recomputing the whole table. I won't be computing sin(x) of course; I will use a lookup table with 64 values and just doing a multiply; the 32F4 is 1 clock cycle for an int32 or single float multiply.If something turns out to be really hard I can go to 100+ samples but would prefer not to.What corner frequency would you suggest I start with?Indeed I can get a 3rd pole wth just an RC, and the DAC is buffered in this case (with some sort of primitive x1 op-amp) which helps.Also I wonder about which op-amp. Some reading suggests it needs to work at 100x the corner frequency, and the old LM358 is probably too slow. OP27 is better, OP37 better still but not stable below a 5x gain, but I want a single supply device. Obviously there are loads... The DAC output swings from +0.25V to +2.25V so the op-amp output will go from +0.5 to +4.5V. I have a 4.7V supply availableor could use a DC-DC converter to get -15V and +15V.

author: srb1954
author_rank: Super Contributor
timestamp: November 30, 2021, 09:10:38 am
content: Quote from: peter-h on November 30, 2021, 08:54:26 amIf you using 64 steps per cycle theoretically there will be practically no harmonics until the 63rd and 65th providing the step sizes are exactly right and the step timing is exactly right. However, if there is any variation in the step timing (due to jitter) or inaccuracy in the step sizes (due to DAC quantiation error etc) then the lower harmonics will reappear in varying amounts.Your best option would be to do an FFT on the unfiltered output to determine its harmonic content and determine how much that harmonic content has to be reduced by filtering. Knowing those parameters and your phase distortion requirements you could then pick a filter characteristic to suit.

author: peter-h
author_rank: Super Contributor
timestamp: November 30, 2021, 09:55:00 am
content: I can't get the LeCroy 3034 to do a meaningful FFT (the values I enter just keep resetting themselves) but my old Tek 2004B produces thiswhich shows the first harmonic at 500Hz x 64 as expected. It is almost 40db below the fundamental which I think is 10000x(?) below.With 128 samples it is 2x further out as expected and is slightly smaller.

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: November 30, 2021, 02:04:58 pm
content: You can even do a 4th order filter with one opamp. Not sure about the numbers but would a higher order filter with the cutoff pushed out a bit further do less damage to the signal?https://www.eevblog.com/forum/projects/third-order-filters-with-a-single-opamp-are-possible-after-all/

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 30, 2021, 02:20:06 pm
content: Quote from: peter-h on November 30, 2021, 08:54:26 amGreat! That's a good start.How small must they be, before theyappearto be "removed"?Note: the answer cannot be zero, you must pick something nonzero.QuoteAh, so AM and FM then. What update rate for each? How fast (and smooth, or not) should they change? What delay (between programmatic change, and output update) is allowable?What's wrong with simply changing the DAC scale? (I forget what exactly that MCU is capable of; this might be inapplicable given available features and requirements.)How about dumping into a circular buffer every so often, and DMA --> DAC from there? (I assume that's what the other thread is about, figuring out that sort of thing?) The update simply occurs somewhere midstream, which could be per update of the buffer (polled or timed), or down to the sample (when the update event is known to a similar resolution)? No need to rewrite the sine table, just get the change propagated into the buffer. Nor any need to rewrite the buffer itself, unless you need instantaneous amplitude response somehow.And there are still other methods, perhaps hardware involved, to provide very fast amplitude updates. For example, run DAC into a digital pot, and update the pot (via SPI or parallel) with a fast interrupt (or even DMA) path, while the buffered sine wave stuff just goes on in the background as usual.QuoteWhat phase flatness do you need? Check the gain and phase curves of typical prototypes (Butterworth should be a fine starting point) and see how far down the curve (in the passband) you need to be. Then go up the curve (into the stopband) and find where sufficient attenuation is reached to "eliminate" the steps. That will be your sample rate.If the ratio between the two is too large, try a higher order, or a flatter-phase prototype, and repeat. (Chebyshev is peakier than Butterworth, but I don't think it's particularly flat in phase? You may want to hand-tune things in SPICE or whatever and see what you can get.)QuoteOnly needs to be GBW ~ Fc * Q. For low order filters, Q is low, so GBW doesn't need to be much.Another bonus of MFB is, the amp's own integrator characteristic acts in parallel with the feedback cap, so this can be factored out. SK needs a bit extra, to deal with the gain dropoff of the amp stage (and consequent phase shift).I would be surprised if LM358, or TLV2372, or OPA171 or friends, doesn't do the job.Tim

author: Kleinstein
author_rank: Super Contributor
timestamp: November 30, 2021, 02:54:47 pm
content: The demand on the OP should not be so bad. The SK low pass filter is a bit worse, as the output gets hit by a current spikes through the FB capacitors. This gets less of a problem in the 3 rd oder configuration. The MFB form is supposed to be a bit less sensitive in this respect.A flat phase in the passband is not very common requirement and 1 degree limit for the phase shift is already relatively tight. On the other side the corss over can be relatively high (e.g. 10 x the signal) with some 64 samples per second and thus theoretical the 1 st harmonics to worry about at 32 times the frequency. So testing in a simulation is a good idea. Some gain peaking like in the Chebychef version may help. One is not limited in Q to the standard types - values in between are OK too. There may be a lesser known one for flat phase.

author: peter-h
author_rank: Super Contributor
timestamp: November 30, 2021, 03:26:34 pm
content: "How small must they be, before they appear to be "removed"?"I don't knowThe signal needs to look clean on an analog scope, so perhaps 30x attenuation."so AM and FM then. What update rate for each? How fast (and smooth, or not) should they change? What delay (between programmatic change, and output update) is allowable?"FM, very slow. It is only to take out drift in the (crappy) oscillator feeding this thing (not my project).AM, zero to max amplitude could happen in 1 second. It needs to appear smooth; I would estimate that during that one second I would need to generate the table 10-20 times. If I generate it at the maximum speed mentioned (1/400 sec) that will easily meet the requirement."What's wrong with simply changing the DAC scale?"This is not a multiplying DAC. For those who know, this is essentially a form of LVDT emulation, and traditionally this is done with a four quadrant multiplying DAC. I am doing it wholly in this chip... The two DACs are just cheap on-chip 12-bit ones. Yes I could do an "instant" amplitude modulator post-DAC but it would need a digital (SPI in this case) control input, and I don't think it is needed."How about dumping into a circular buffer every so often, and DMA --> DAC from there? "I am basically doing that. The DMA is double-buffered i.e. each time the transfer count gets to zero, it toggles the address pointer, and sets a "you can now fill the other buffer" bit. But I still need to be able to process the incoming signal (the one which requests the new amplitude) and fill that buffer with new sin(x) values, before the buffer is flipped back, which needs to be done in ~1ms to have a decent margin. And I have two channels of this to do. The two are always in phase, and always in phase with the input signal, but their amplitudes vary, from -sin(x) to +sin(x).The whole thing runs in hardware. There is a counter which measures the input signal period, and which leaves that value (resolution ~1/5000) in a register, and there is a timer which triggers the DACs (whose period is periodically adjusted to match any frequency drift) and the DACs trigger a DMA. The only "software" in this whole "tracking wave generator" is an ISR which runs in 3us, on every zero crossing, and which resets the DMA pointers, to maintain sync. It's actually quite impressive to see it all running, and using up < 0.1% of CPU time"What phase flatness do you need?"I did some digging around - there is a Japanese site for filter simulation - and it looks like < 1deg delay is easy to achieve if the rolloff is say 10x the base i.e. ~4kHz. I will just need to birdsnest this and see... In fact, with 64 samples, if I go for a delay of 360/64 = 5.6 degrees then I can compensate for that with a 1 sample shift, which is easy (I am already doing a 2 sample shift due to the obscure reason mentioned in the other thread). And to get a 5+ deg delay you will be running the rolloff frequency pretty close to the base frequency."I would be surprised if LM358, or TLV2372, or OPA171 or friends, doesn't do the job."The 358 won't quite do it because the +2.25V input is a bit tight with a +4.7V rail, and it won't do x2 gain (+4.5V max output) with a 4.7V rail. What the 358 does do is Vcm down to GND, and the output also swings all the way down (but below about +1V Vout is has almost no drive capability). I need a reasonably decent output drive because it may be driving a few m of cable.As suggested earlier, an RC "pre-filter" before this filterwill give me a "free pole" but importantly should much reduce the op-amp BW requirement because one is taking out the really high harmonics. It will also take out the MHz-level crap which anything coming out of a "CPU board" is full of. I actually have a 16-bit ADC subsystem on this board and getting the noise down on that was a real challenge; the inputs had to be heavily filtered passively, and the whole circuit is galvanically isolated.I have picked the TSV912AIDR - for rail to rail input and output, good BW, and an SO-8 package which is easy to birdsnest.I don't have a simulator setup, unfortunately (used to have an analog sim many years ago).What I don't understand is the need for precise component values. I mean, if one stage rolls off at say 4kHz and the one after it rolls off at 5kHz, does it matter? The S-K 2-pole config, with a gain of 1, "can't possibly be critical", but maybe at higher gains it is.My plan was to make the 1st (passive) stage with a much lower Zout so the loading on it is not big (R3 in above diagram being maybe 1k only).Playing around herehttp://sim.okawa-denshi.jp/en/OPstool.phpwith these valuesI get 5.3deg phase delay at 400Hz and 6.5deg at 500Hz which is not far off the 5.62deg achievable with a 1 sample DAC table shift, and these are the two frequency limits of main interest.What I don't have a sim for is a) the extra RC lowpass stage before this and b) a gain of 2x (but AIUI the 2x gain is simply taken care of by making C1 half the value and that keeps the curves the same).

author: mawyatt
author_rank: Super Contributor
timestamp: November 30, 2021, 04:25:18 pm
content: Quote from: Kleinstein on November 30, 2021, 02:54:47 pmObviously you haven't worked around digital communications where linear phase and flat group delay are as important as passband ripple and stop band rejection, where both Amplitude and Phase/Group Delay adversely impact Bit Error Rates (BER). Massive efforts are put forth to achieve acceptable phase, group delay and amplitude responses and often are achieved with complex "equalizers". Since all analog filters are by definition IIR, digital FIR filters/equalizers are often employed to create an overall system level transfer function which has an acceptable BER performance. Many designers will focus on the analog amplitude characteristics, especially stop band where aliasing is handled since these are pre-digitization, then utilize a digital FIR filter to correct the usual unpleasant passband phase-group delay responses that result from being neglected in the analog domain. As we try and cram more digital bits into a given limited BW, the effects of Phase and Group Delay responses become even more critical in the never ended battle to get more reliable information thru a limited bandwidth channel!!QuoteThe prior mentioned Bessel is a maximally flat group delay filter function, like the Butterworth is in amplitude. There are also analog filters that go between these two maximally flat limits, think the Gaussian and equiripple Chebyshev fall into this category. We often selected inverse Chebyshev in the advanced digital comm systems we developed, but that discussion is for another topic.BTW the stop band "shoot thru problem" with Sallen-Key filters can be improved by loading the output Op-Amp with a resistor to Vee, this causes the output NPN or NMOS device to be biased more "On" and thus exhibits a lower open and closed loop output impedance.Best,

author: peter-h
author_rank: Super Contributor
timestamp: November 30, 2021, 04:31:36 pm
content: I very easily got a very flat enoughgroup delaywith the above mentioned sim site, but I actually need a fairly flatphase lag- because I am trying to cancel out the phase lag by shifting the DAC feeding table, and with 64 samples I am stuck with 360/64 of a degree resolution there.Best I can do, around the 5.6deg figure, are the above values and the 5.9kHz cutoff.It will be good enough for this application, but if there is an easy improvement it would be niceThe "shoot thru problem" is what I think drives the need for a good fast op-amp. No good doing an active filter with an op-amp which can't work at the frequencies you are trying to get rid ofBut hopefully choosing an op-amp which has a decent output stage helps. TSV911:Maybe Class A would be better - which is what a pullup does, basically.I am beginning to see that going for 128 samples per cycle would helpBTW it doesn't need to be a power of 2.

author: mawyatt
author_rank: Super Contributor
timestamp: November 30, 2021, 04:44:44 pm
content: @ Peter,If I understand above, a constant phase delay implies a time delay that varies inversely with frequency of generation? IS this correct?Best,

author: peter-h
author_rank: Super Contributor
timestamp: November 30, 2021, 04:48:20 pm
content: Yes; that would be ideal.I can do 360/64 or at a push 360/128, degrees.The S-K filter appears to do something like that - presumably because one is approaching the corner so there must be a slope of some sort.

author: mawyatt
author_rank: Super Contributor
timestamp: November 30, 2021, 04:51:48 pm
content: Also the shoot thru problem with SK is due the the fact that the closed loop output impedance "looks" inductive due to the roll off of the open loop gain. Bias loading the output causes the open loop impedance to start lower.Here's a 3rd order Butterworth we published eons ago that uses Equal Value Components, which makes realizing easier. It does use multiple Op-Amps tho, but these may be available in a quad package. You can get by with 2 Op-Amps by moving the first order to the output of the last Op-Amp, but you lose the advantage of the passive first order at the input , and no Op-Amp output at the filter output.Best,Edit: You might look to a 2nd, 3rd or 4th order Gaussian (approximation) filter for the 1/f group delay effect. See image below from Zverev.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 30, 2021, 05:56:26 pm
content: Quote from: peter-h on November 30, 2021, 04:31:36 pmI'm not quite sure what you mean here. A flat group delay is just a constant time delay, equivalent to a fixed # of samples delay. Low phase delay can matter in high bandwidth feedback loops since it affects stability but in a normal waveform generation applications it doesn't matter at all since the start time is effectively arbitrary. Are you sure that is what you need?

author: peter-h
author_rank: Super Contributor
timestamp: November 30, 2021, 09:04:30 pm
content: Yes - because I am compensating for the filter delay by shifting the DAC table along by 1 sample (actually, potentially a multiple of samples) and the width of a sample is some fixed proportion of a cycle period.If I am running with 64 samples per cycle then each sample is 5.625 degrees long - regardless of the frequency being generated.I guess this is a bit weird since probably most people building filters want a constant group delay, not a constant phase shift.BTW I have done more of the code and using a precomputed sin(x) table I am able to compute a 128-sample DMA-> DAC table in just 15us which is negligible, so there is no performance issue at 128 samples, and the waveform looks pretty clean:Using a S-K filter with a 43.kHz corner, I am getting about 5.5 deg of phase shift which is close to 2 DAC samples.

author: ejeffrey
author_rank: Super Contributor
timestamp: November 30, 2021, 09:53:05 pm
content: I see, so you are doing frequency modulation by changing the sample rate?

author: peter-h
author_rank: Super Contributor
timestamp: November 30, 2021, 10:09:19 pm
content: Yes. The sample width is determined by a timer running at 84MHz, so it has a reasonably large time constant (about 1300). Constant number of DAC samples per cycle, regardless of the frequency.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 30, 2021, 11:31:20 pm
content: Why shift something so gross as the whole DAC table? Why not change the phase accumulator by small offset (DDS)?Tim

author: ejeffrey
author_rank: Super Contributor
timestamp: December 01, 2021, 12:24:18 am
content: I see. That isn't ideal for filtering because the nyquist frequency changes when you change operating frequency. Your filter has to pass the highest frequency you generate while blocking the alias from the lowest sample rate you will use. Since you have a relatively large oversampling ratio and a small frequency range you can probably make it work, but you are making it harder on yourself than if you used a fixed sample frequency and a constant group delay filter. The downside is that it is potentially more resources than using a fixed buffer of samples and just varying the sample timer. A standard NCO implementation is to have a phase accumulator that increments a set amount every cycle, then take the most significant N bits of the accumulator as an index for a pre-computed table. You only need to store the table for the range 0..pi/2, so a 10 bit table only has 256 entries which is not usually prohibitive. At your ~ 10 kHz sample rate most microcontrollers should be able to do the phase accumulation, lookup, and amplitude scaling in real time. This also makes it trivially easy to implement a phase shift with a single addition.But it sounds as if you have found an acceptable solution for your needs, if it works then I guess that's good enough.

author: peter-h
author_rank: Super Contributor
timestamp: December 01, 2021, 02:41:57 am
content: I am not doing this with DDS. I have a timer triggering a DAC which in turn triggers DMA to fetch the value from RAM and that loads up the DAC.It is no doubt true that my reference frequency tracking mechanism could be much smarter. I could make tiny adjustments to the counter in the timer, for example. Currently I just load the freshly calculated auto-reload value into the timer.I really don't think this is an issue however. I do need to track the inputphase(align the zero crossings) but the only reason for tracking the inputfrequencyis because the source is usually fairly primitive and drifts around a bit, over minutes or hours. And obviously if one doesn't track the input frequency then eventually you will end up with a big notch at the trailing end of the cycleYes indeed what I have works as far as the sinewave generation goes. I've spent a number of days chasing various subtle issues, to do with e.g. some registers not being writable while say a timer is running, and disabling the timer causes one artefact while doing something else causes another... I have now settled on a generator design which is running totally in hardware, with the only CPU load being a very short (about 3us) ISR at every +ve edge of the 400-500Hz input waveform. I still have an artefact where the first two DAC samples output after the zero crossing are equal (!); this is due to double buffering somewhere which is losing one DAC update (a hypothesis was by someone in the other thread) but while this is visible on a scope, with 128/256 samples per cycle you struggle to see it, and it leaves absolutely no trace whatsoever on a spectrum analysis of the DAC output so it will be completely immaterial after any filtering.The simplest way to compensate for a filter delay is to rig up the filter so the delay is roughly one sample period, and shift the table by that much. I am already having to shift the table by 2 places due to double buffering on the DAC (no evident way to disable that, and you would never design such a stupid circuit if you were designing a wave generator yourself, with a DAC chip, because it is completely pointless).The spec on what I am trying to emulate (something out of the 1970s) calls up a phase shift better than 10 degrees, which is atrocious, and I suspect some kit which is decoding this (probably in software) is actually a lot more fussy, so I am trying to do a lot better. I am readily achieving sync of 1 degree now.I've done tons of analog since the 1970s (top grade audio, ppm-stability PSUs, etc) but never looked at filters properly, so this has been an interesting experience. It looks like there isn't a filter which does a constantphasedelay - other than by selecting the rolloff so the phase delay is constant because it is negligible

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 01, 2021, 11:39:21 am
content: Right, in general, phase goes up with frequency; how much, is given by the group delay (give or take some funny business dis/ambiguating phase and group delays I think), and in a continuous system (transmission lines or free waves, as opposed to this lumped-element RLC system) the delay is a true causal delay, at whatever the speed of light is. Delay meaning, phase shift exactly proportional to distance and frequency. We can only have constant phase either with additional delay added for low frequencies to compensate (in which case, in finitely many bands, depending on how fancy we want to build the all-pass filter), or sufficiently near DC that we don't care about the real delays (which is the case here, up to the filter of course).I don't get the reluctance for a DDS, you can run one into a buffer just fine. It's preferable on a platform like that anyway, queue up a bunch of outputs, sit back and relax a while, repeat. It doesn't have to run perfectly in real time, it just does whatever it does from sample to sample, and the DMA+DAC syncs it to real time. Also solves your timer-shittiness problems, that timer issue doesn't sound like something that should happen in the first place, but eh when you need workarounds, you'll take options, right?Tim

author: mawyatt
author_rank: Super Contributor
timestamp: December 01, 2021, 02:36:39 pm
content: Since this is a created file for a sine wave from a DAC and then analog filtered if I understand correctly. If correct, one could implement a FIR filter before the DAC that compensates for the analog filter and creates the desired overall constant phase response at the output. Kind of like what I mentioned above about the phase and group delay response being very important in digital comm systems.So in effect, equalizing the analog filter & desired phase response before the digital to analog conversion, and doing so in the digital domain where FIR filters/equalizers are possible!Best,

author: gf
author_rank: Super Contributor
timestamp: December 01, 2021, 03:23:44 pm
content: Or even simpler, just fill the buffer with phase-adjusted samples (compensating the filter's phase response at the current frequency), given that the frequency changes so slowly that assuming a constant frequency and phase for the duration of one buffer is a sufficient approximation. A pre-calculated sine table with 512 entries is sufficient for 0.7° resolution, and 4k entries enable a resolution of < 0.1°.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 01, 2021, 04:00:10 pm
content: Quote from: gf on December 01, 2021, 03:23:44 pmWell yeah that's what he said, as I understand it -- albeit on the granularity of single samples, which is pretty coarse at the proposed sample rate.Tim

author: Conrad Hoffman
author_rank: Super Contributor
timestamp: December 02, 2021, 12:22:38 am
content: Have to mention that the Don Lancaster Active Filter Cookbook is now a free pdf on his site-https://www.tinaja.com/ebooks/afcb.pdfIt's an oldie but goodie.

author: David Hess
author_rank: Super Contributor
timestamp: December 02, 2021, 08:22:17 pm
content: My default for simplicity is the 3-pole Sallen-Key with a Butterworth response for fastest settling because it takes on a single operational amplifier, the 3rd pole is free, and component values are not critical. If linear phase is important, than I use the Bessel response. If a more complex filter with more poles is used, then component tolerances become critical.If DC accuracy is important, then there are filter topologies which AC couple the output of the filter into the signal to subtract the undesired components. For instance multimeters use these.

author: peter-h
author_rank: Super Contributor
timestamp: December 02, 2021, 09:24:55 pm
content: I am still hereI am just waiting for some parts to arrive from Mouser and then I will birdsnest the circuit (2 pole S-K with a 3rd passive lowpass in front of it) and will post the waveforms, the delays, and the spectra.One thing I was wondering was whether the 1st (passive) stage should roll off at the same frequency as the active filter after it, or whether I should set it for a 10x higher corner frequency, and just use it to suppress the high frequency components (and general logic noise) so the active filter op-amp doesn't need to work well at high frequencies.Another thing I found was that reasonable tolerance caps are hard to get in SMT, and if you are happy with 5% then ceramic SMT ones are easy. Whereas for through-hole mounting there are loads of 2.5% caps; polypropylene foil etc but they are tall, and need to be hand-mounted because almost no contractor today has a flow soldering machine. But a filter like is needed here can't possibly need 2.5% caps, can it?In the meantime I fixed the waveform artefacts mentioned earlier (the consecutive DAC samples being the same value). They really showed up on the fourier analysis, and at a frequency right next to the fundamental, too (as expected - they are periodic with the fundamental!).Then I spent a bit of time looking for a sin(x) code (x= 0 to PI) because even though I am precomputing the table, math.h (needed for sin(x)) takes up 5k of FLASH... most C code for Taylor series that I found uses pow(x,y) which is daft since it needs math.h tooI need accuracy of about 0.1%, only. I did all this in Z80 asm in the 1980s, computing just one octant and then transposing. If I was willing to fix the samples per cycle, a LUT would be perfect.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 03, 2021, 12:57:48 am
content: Quote from: peter-h on December 02, 2021, 09:24:55 pmWell, don't fiddle around, just calculate. You showed the calculator tool earlier, they have the 3rd order form already solved too.In the limiting case (passive RC resistance << filter resistance), the added pole will be placed on a geometric shape, regularly spaced with the other poles (circle, ellipse, or off-centered ellipse, as in the three standard types), with the RC values as eyeballed.If not much-lesser-than, then the filter will significantly load the RC, and adjustment is required. This is also easy to see in the calculator: for too-small ratios of R or C, a solution cannot be produced -- namely, that it would require one or more negative capacitors or resistors, to still produce a filter of given type. Which the programmer's smart enough to notice don't exist, so it errors out instead. Alternately, if you play around with component values (viewing the response), you'll see that trying to push the poles together (making it sharper or peakier), instead causes them to repel away along other trajectories (you get a peak plus, say, a lump in the stopband). You need a high enough ratio between sections, so that the poles can be placed close enough together to get the optimal response.This is easiest to see for the simple passive RCRC filter. Easy enough to evaluate by hand -- I invite you to do so if you're feeling adventurous. You will find that, for equal R and C, a transfer function of the form:\[ \frac{1}{\omega^2 + 7 \omega / \omega_0 + 1/{\omega_0}^2} \]appears (or something like that, I forget exactly -- I first solved this alongtime ago and could use a refresher myself!). The 7 being the damping factor (less a factor of 2), meaning it's very overdamped -- as you'd expect from a dumb RC filter. Well, using R-C-10R-0.1C instead, obviously the second stage has less loading effect on the first -- and this is reflected by the middle term dropping to, 2.41 I believe it was? -- much closer to a repeated real pole. That is to say, in the limit as the ratio goes to infinity, that term approaches 2.The limiting case is called a repeated real pole, because x^2 +2x + 1 has the factorization (x+1)(x+1). But those are roots, and they're on the bottom, so they're poles of the whole thing, hence the name. And if the middle term is any smaller (less than 2), the factorization becomes complex valued; this is only possible with gain and feedback, or inductors.Note that real poles are separated horizontally on the complex plane (they're on the real axis, obviously enough), and complex poles are separated vertically (always in conjugate pairs). We can adjust the feedback factor of the 2nd order Sallen-Key filter, for example, and tune the position of the poles -- we can plot the trajectory of their positions as a function of gain. For the zero-feedback (fully passive RCRC) case, they will be horizontally opposed; as gain rises, they draw closer together (as the cutoff becomes sharper, but still very gentle), until they're on top of each other (repeated pole), at which point they split apart vertically (complex conjugate pair). They may drift to the right (real component decreasing), eventually crossing over to the right half-plane, where you get an oscillator instead. The exact trajectory depends on the circuit; the pole-splitting may happen straight vertically, or along diagonals or other curves (particularly when more poles are involved).This is all to say, in the 3rd order case: if the passive RC (real pole) is too close to the complex pair (or the Q is so low that they are real poles as well!), they start to repel, and the minimum possible distance is determined by the ratio of passive to filter impedances.As for the standard, named prototypes: these happen to work with poles spaced evenly along some shape, namely a semicircle for Butterworth, ellipse for Bessel, or, I think a translated circle (or is it elliptical as well?) for Chebyshev. So, simply put: you need the impedance ratio sufficient to place the poles close enough to meet the spec. That's all you're doing with that ratio.Note that evenly-spaced poles, is NOT the same as adding a real pole to a 2nd order standard type. Those two complex poles will be evenly spaced (e.g. +/-45° along the semicircle for Butterworth -- which is to say, that stage has a Q of tan(45°) = 1, more on this in a moment). Bringing in a real pole, will no longer be evenly spaced: you'd have poles at -45, 0 and +45, for a spacing of 45 between each but 45 also to the axis, when it should be 60 between poles and 30 to the axis. The whole filter must be adjusted to give the correct 3rd order response (so for Butterworth, raising the Q to sqrt(3), while keeping the poles at the same frequencies).So, on top of existing poles shifting around as you bring in new ones, they need to go to different positions besides. None of this is very well conditioned, in general (finding roots of polynomials!), so while it's helpful to understand things like the above -- the practical consequence is, go to the calculator!Now, all that said -- how important is all of this,really?It is largely an academic matter -- as long as you aren't scattering the poles just completely bonkers, I mean heck, it might even be preferable for a given application, to take the somewhat flatter response of the, shall we say, somewhat more naive design (but that's a rather strong way to put it, see). That is, of taking a 2nd order filter and adding a real pole to it without tweaking anything (assuming the poles don't move around -- again, this is the case only for a very large impedance ratio Zfilt / Zpassive, or with buffering). Maybe the lower overshoot, or flatter group delay, is preferable. The only real difference is completely technical: you won't have something as closely approximating a named type. As long as it has the characteristics you need, that's it!It's not at all that these types have been passed down from on high, it.....well, to be sure, theyhavebeen, it was surely no small feat solving for them -- and we record their results in celebrated tomes like Zverev. But they are still only guides, starting points for practical designs to work from, not strictures we must obeyor else!So between that, and between the circuit sensitivity and Q factor -- it need not be such a picky thing.You should, perhaps, at this point, have some appreciation for what tolerances are actually relevant now. And, you can test this yourself in the simulator (whether a webpage calculator, or a full SPICE engine -- of which, you posted a screenshot from LTSpice so I'm not sure where you missed that you have a simulator too) and see what variation in component values does to the response.QuoteGenerally speaking, frequency is proportional to R and C (so, Fc the geometric average of everything, more or less), and Q proportional to the components responsible for it. Sensitivity is a concern whenever a component has a rate faster than this -- I forget what the figure is for S-K, somewhere around double I think (worst case, for applicable components), or maybe it's on the order of 2Q or Q^2 or something. (MFB I think is flat, no anomalous sensitivity?)In any case, that's hardly a problem. Q is about 1. The poles are fairly far apart. Frequency isn't going anywhere fast, and you've got a huge transition band to work with (i.e. Fclk / Fsignal). It seems doubtful that even 10% components will be an issue.Note that higher order and sharper filters have higher Q stages, so need proportionally tighter tolerances.This is one of the advantages of low-order filters, when you can afford them -- you might not go to, like, X7R caps, because of distortion and microphonics -- but basically anything else is game. C0G and PP are basically complete overkill here, but they're so readily available, it's not at all a guilty pleasure to use them.QuoteA polynomial will reduce that easily, yes. Rearrange to use Horner's rule, it'll go fast even on AVR, heck.pow() may optimize down when given integral values, but it depends. The arguments are both floating so the compiler might rightly preserve them as such (i.e. because of rounding error); or it might spot that an integer value is within rounding distance and thus produce a simpler form, or even notice the argument is integer cast to float.It might even notice that the repeated, and sequential at that, multiplications can be chained, thus deriving Horner's rule for you. But for all of this, you'd have to see what the compiler does, and it will vary by platform. (If I had to guess, GCC ARM and x86 probably fare quite well, but I don't know if they cover this particular situation.)In any case, ALL of this, should easily fit in just a few kB -- table included! If you're compiling without optimization (-flto in particular..?), there might be a lot of library cruft included, I don't know. Again, something you'll have to look at. (Checking the output listings from time to time, is a good idea. Likewise, being at least vaguely familiar with the platform's instruction set.)Offhand, I'm playing with a thing that uses this,Code:#define SIN_DATA\0,\6,\13,\19,\25,\31,\38,\44,\50,\56,\62,\68,\74,\80,\86,\92,\98,\104,\109,\115,\121,\126,\132,\137,\142,\147,\152,\157,\162,\167,\172,\177,\181,\185,\190,\194,\198,\202,\206,\209,\213,\216,\220,\223,\226,\229,\231,\234,\237,\239,\241,\243,\245,\247,\248,\250,\251,\252,\253,\254,\255,\255,\256,\256const int16_t sin_table[] = {SIN_DATA};/***Calculates the fixed point sine of the specified*angle via table lookup.*/int16_t fixsin(uint8_t a) {int16_t r;if (a & 0x40) {//Second or fourth quadrant, mirrorr = sin_table[0x3f - (a & 0x3f)];} else {//First or third quadrant, no mirrorr = sin_table[a & 0x3f];}if (a & 0x80) {//Third or fourth quadrant, negativer = -r;}return r;}/***Calculates the fixed point cosine of the specified*angle via table lookup.*/int16_t fixcos(uint8_t a) {return fixsin(a + 0x40);}which obviously doesn't have the greatest accuracy (veeery slightly more than 8 bits output), but it does its job. Easy enough to adapt the same method for other purposes, just run off a more accurate table as needed.Note that the argument is a full int8, no degrees/radians in sight. This is a very natural change, as C int types (on common platforms) are cyclic groups, and simple bitwise logical operators provide access to whatever 1/2^Nth of the circle you want. Hence the 6th and 7th bit operations above, determining which quadrant to return.I don't know how much of this you've done already, so maybe it bears saying, maybe it's redundant.As for DDS, it's just so trivial:Code:uint16_t ddsFreq, ddsPhase;int16_t getDdsSample(void) {ddsPhase += ddsFreq;phaseShifted = ddsPhase >> 8;return fixsin(phaseShifted);}In this case, the phase accumulator has 16 bits but only the top 8 are read (by the sin table). The extra bits are kept from sample to sample, as they will roll over from time to time, thus allowing an effectively fractional sample rate. If you call this every 100kHz say, then the frequency step is 1/65536th or 1.525... Hz per count. You can use as many bits as you like in the phase accumulator, and truncate it by as many, too. If you like, rewrite the sin function to interpolate, taking advantage of a few extra bits; or make it fully continuous* with interpolation (linear, Bezier or otherwise), polynomials, or whole-ass floating point libraries for all that matters.*In the sense that you're using all the bits, as high a resolution as you can; obviously this is nowhere near continuous in the mathematical sense.O'course using int32's will be a natural fit on your platform, good luck noticing a four-billionth step size in frequency, it's no effort, high reward.Tim

author: peter-h
author_rank: Super Contributor
timestamp: December 03, 2021, 10:04:12 am
content: Thank you T3sl4co1l for the great detailed post.I didn't know that .jp site has a 3 pole S-K but I found it. It gives "interesting" results. If you get the first (passive) stage wrong, the attenuation at say the first harmonic (400Hz x 128 = 51kHz) can be actually worse! Maybe you were trying to say this but maths was never my strong point, especially complex numbers (I failed all maths exams at univ but got 100% for electronics so they couldn't chuck me off the course). Predictably, if you make the 1st stage same RC as the next i.e. a similar rolloff, you get a better result, but only if you go for a decent impedance ratio (say 10x smaller R) so the loading of the active filter on the passive 1st stage is not too significant.I am also finding, again predictably, that the attenuation at 51kHz is much better if I rig things so the phase lag istwoDAC samples, not one, i.e. 5.6 degrees. I can get better than -40db, and better still if I increase the Q (increase the beedback cap) but then there is some ringing in the transient response, which might not matter since I am dealing with such tiny steps. What I can't tell is what the result will look like without building it.This looks goodwith 2-sample-period phase lag around 450Hz and -52db at 51kHz. The gain will be 2x (they don't have a model for that) but with C2=2.2nF that should produce the same result.I did think about the LUT approach, or even linear-interpolating a table. If the design was always 128 samples per cycle then a direct LUT would be perfect: 256 bytes of FLASH. One could even get clever and generate the table at build-time, with a little .exe utility, into a text file, according to the # of samples which is defined in a .h file.

author: Kleinstein
author_rank: Super Contributor
timestamp: December 03, 2021, 10:24:56 am
content: The SK version with gain changes more than just a factor to the feedback capacitor. It is only a first crude approximation. If the filter design program does not support this configuration, one could still use a general simulation with a SPICE variant. With only 3rd order ony may be able to fine tune the resistors by hand to get an acceptable response.For the phase shift one may be able to adjust the time when the DAC is updated or the other part is using the signal. This may just need an extra timer compare unit for the trigger.

author: peter-h
author_rank: Super Contributor
timestamp: December 03, 2021, 10:42:14 am
content: Yes - the intention is to arrange for the phase shift to be a multiple of DAC samples, and then shift the table. This is all working already.Also been playing with this one. I am finding this config very difficult to select values for. They all interact stronglyI am trying for whatever rolloff achieves a 5.6deg phase lag at 450Hz. It will probably be around 5kHz. There must be some iterative means. Many years ago I wrote a prog in Fortran which calculated the RC stuff for a passive RIAA attenuator. But that involved IIRC 3 stages and each was sufficiently independent to do it iteratively.Obviously, R4=2*(R1+R2) for 2x gain.But it is no better than the non-inverting version. This achieves the desired result with phase lag:" It is only a first crude approximation"Why is that? For the non-inverting version, that's completely counter-intuitive. Assuming a perfect op-amp, all that cap sees is the op-amp output swing, and 2x the swing with 0.5x the cap should produce the same result.

author: Kleinstein
author_rank: Super Contributor
timestamp: December 03, 2021, 11:58:24 am
content: In the SK form the input side of C2 is not a virtual ground. The voltage on the input side is significant. For the pass band there is very little voltage with a gain of 1, but there would be quite some difference with a gain of 2.To get back to the form with gain 1 one would need an additional capacitor to ground. So not 1/2 the capacitor, but 1/4 the capacitoance in Fb and 1/4 the capacitance to ground. However this may well be more than the capacitove drive capability of the OP, and may thus not work.With gain the inverting multiple feedback version may be more suitable. Chances are that with gain the SK filter would also show more interaction between the parts.For the practical build one often sets the capacitors to fixed values, as the available values are often more limited. With reasonable values for the capacitors (like all the same or may be one at twice the value) it is enough to adjust only the resistors. To get the odd resistor values 2 in parallel or series is more practical than with the capacitors.

author: mawyatt
author_rank: Super Contributor
timestamp: December 03, 2021, 02:24:58 pm
content: The Equal Valued Component 3rd Order Butterworth filter shown before and repeated here has the advantage of using equal value capacitors and resistors, and less sensitivity to component variations than regular SK 3rd Order. Very easy to use and build. We published this in EDN decades ago, and Walt Jung (Analog Devices) copied this in one of his analog books.Best,

author: peter-h
author_rank: Super Contributor
timestamp: December 03, 2021, 03:05:39 pm
content: @MawyattThank you. This looks like a S-K but with a x1 buffer after each stage. It needs 3x more op-amps@KleinsteinInteresting! I also just realised that the sitehttp://sim.okawa-denshi.jp/en/Multiple3tool.phphas acalculator. I've been playing with it and no wonder I could not get anything sensible by setting the values manually. It produces quite weird values. The performance is not obviously better than the noninverting version though... if set up for the same phase lag at 450Hz of 5.6deg. The Butterworth option also produces similar results.In the end, the noninverting is more convenient because my DAC swings +0.25 to +2.5V (actual since wave is +0.25V to +2V) and with a R-R op-amp and a 5V supply I can do it without AC coupling or needing a negative rail.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 03, 2021, 03:23:12 pm
content: Why would you not take Vref/2 for virtual ground, in the inverting case..? Or do you mean that the noninverting case simply doesn't need that divider?Tim

author: peter-h
author_rank: Super Contributor
timestamp: December 03, 2021, 03:37:45 pm
content: Annoyingly I don't have access to Vref on the connector which is used for this filter. It could still be done, of course.However, is the inverting version somehow better as a filter? The only advantage I see is that we have an online calculator for the 3 poleinvertingversion with gain, but don't have a calculator for the 3 polenoninvertingversion with gain. And I can't find one online.I wonder if anyone here has a sim and could take a quick look. I am looking for a delay of 5.6 deg at 450Hz, which will probably be achieved with a cutoff freq around 8kHz, and a gain of +2, and that's about it. The attenuation at 450x128Hz (57kHz) will probably be about -60db. I have a +1 gain design already (above) but with 4.4nF in the feedback which I was planning to replace with an actually available 2.2nF with a gain of +2, but from what's been said this may not work so well.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 03, 2021, 07:01:45 pm
content: Oh weird, behind a connector. Okay, a bit annoying yeah.Like I said, it's not a big deal either way, it's a low order filter and the tolerances aren't particularly important compared to what's available.I still don't... what's wrong with the bloody DDS? You can get any minuscule phase you like, man. You can put the filter phase in a lookup table and cancel it out perfectly within as many arcseconds as you want. The filter is not the problem, you're making an X-Y problem for yourself.Tim

author: peter-h
author_rank: Super Contributor
timestamp: December 03, 2021, 10:44:13 pm
content: It's not an issue. I can go for 2.8 degrees instead.But from playing around with those filter tools, it is obvious that a shift of just 2.8deg will be from a filter whose rolloff is much less at the relevant harmonics, than with a phase shift of 5.6deg. I know nothing about filters and the maths but it is obvious that the phase shift starts at zero and then builds very slowly and then builds fast as you approach the corner frequency.So that's the tradeoff. If you want a simple filter, the phase lag at say 1/20 of the corner will be closely related to the attenuation at say 10 x the corner. It doesn't matter how one shakes the numbers on those simulators, one always gets the same curves. I am sure there are better (more complex?) filters, and there are digital filters, but here I am doing 128x oversampling... it can't be that hard, and rigging the phase lag to match the DAC sample period, by shifting the table along, is a trivial solution.

author: mawyatt
author_rank: Super Contributor
timestamp: December 03, 2021, 11:45:28 pm
content: Quote from: peter-h on December 03, 2021, 03:05:39 pmYes does take 3 amps, or 2 if you move the first order section to the backend with output now from RC junction. As mentioned sometimes quad amps are available and useful, the advantage of course is you can use same C value for all Cs and same for Rs.Best,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 04, 2021, 01:23:04 am
content: Quote from: mawyatt on December 03, 2021, 11:45:28 pmMight be tempting with emitter followers. Meh, about the same space taken up as a quad. But I'd much rather use a quad for more interesting things; op-amps are far higher BOM cost than a unique R or C. (The relevance to your IC experience is obvious, however: where another amp, even a good and proper one, is likely cheaper than the capacitors are. Not that IC caps need to be matched values, but as long as you're making them as small as possible, your ratios will be rather limited.)Tim

author: David Hess
author_rank: Super Contributor
timestamp: December 04, 2021, 04:01:39 pm
content: Quote from: peter-h on December 02, 2021, 09:24:55 pmThe passive RC stage followed by a 2-pole stage makes a 3-pole filter so the cutoff frequency of the RC stage is critical to the desired filter shape. The only time the input passive RC stage is made to be a much higher cutoff lowpass section is to keep only RF or high frequencies out of the following active stages which may have problems handling them.Quote from: mawyatt on December 03, 2021, 02:24:58 pmDon Lancaster's book covers the equal valued component filters in detail as well.

author: peter-h
author_rank: Super Contributor
timestamp: December 04, 2021, 09:16:31 pm
content: I came across this Analog Devices filter calculatorhttps://tools.analog.com/en/filterwizard/You can select a gain there. It does pick some weird component values e.g. the 20.4k + 20.5k here is clearly dumb. They are trying to sell expensive micropower op-amps which have a poor GBW for the purpose, but that's irrelevantAFAICT it won't simulate the config with the 1st stage being a passive RC but fairly obviously the one below could have the op-amp replaced with say 6.8k / 10nF. But they are clearly avoiding simulating the noninverting configwithgainby putting any gain in the first stageThis shows a S-L lowpass wth a gain of 2x and the calculation seems totally straightforward. Is it actually right?https://www.electronics-tutorials.ws/filter/second-order-filters.htmlThey have the same value resistors, same value caps, and a Q of 1.

author: peter-h
author_rank: Super Contributor
timestamp: December 05, 2021, 10:52:00 am
content: Well, I installed LTSPICE. It took me only minutes to get it running. Clunky program - just like the ones I used 20 years ago. But seems to run perfectly.The slight issue is that the modelling is nothing like the results from that .jp site aboveEven at frequencies which are a tiny fraction of the opamp GBW.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 05, 2021, 04:22:44 pm
content: Did you bias the op-amp, and choose a representative model? Note there are 3 and 5 terminal models, the former are a linear idealization (which should actually work fine here), the latter needs the input and supplies at realistic values.Tim

author: peter-h
author_rank: Super Contributor
timestamp: December 05, 2021, 06:04:38 pm
content: Yes; there is a variety of gotchas.After much mucking about, and finding weird stuff like the 1st stage can easily make the result go the opposite way to what one expected (as if partly cancelling one of the stages of the active filter), and finding that some of the component values are quite sensitive, I have ended up with thisIt uses the real op-amp I will be using, which is very similar to some of the AD/LT models (LTspice doesn't come with other brands- you have to import them).Interesting to discover that COG 1% is easy to get, 0805, if not totally cheap.The desired phase shift is achieved at 450Hz too. Attenuation is 56db at the 1st harmonic - the basic DAC step frequency. This should do the job very well.The 2x gain modifies absolutely everything, quite dramatically. Halving the feedback cap is pretty well meaningless; one has to start again.Also interesting that the attenuation levels off after about 200kHz - I would not have expected that, given the passive 1st stage. I don't have any ESR selected. But if I simulate to 100MHz then sure enough it works as expected (meaningless in reality due to stray capacitances etc). A few years ago I worked a bit on a programmable attenuator for a signal generator (using those expensive chips which switch resistors using MOSFETs, and work into the microwave region) which was supposed to go to 80+ db and that had to use a metal box with partitions.The sim I last used, about 20 years ago, was Simetrix. Interesting to see it is still out there. I bought it - not cheap, about £300 - when it was a spinoff from some UK university. Probably still have it, though it would need to run in a winXP VM. The way it worked was almost identical to LTspice - horrible editing, horrible everything

author: mawyatt
author_rank: Super Contributor
timestamp: December 05, 2021, 06:57:18 pm
content: Quote from: peter-h on December 05, 2021, 06:04:38 pmYou shouldn't complain much, the early renditions of SPICE in the 70s and 80s were text based nodal entry, and had no graphing capabilityWe had to make graphs by using a line print outputs with ASCI characters using wide carriage line paper printers.Then had to create our IBM "punch cards" that were mailed to our IBM 360 computer in Minneapolis, then get the printouts in a couple days mailed back.Even the early versions of the popular PSpice were text based, and all were based on the Berkeley Fortran code that Larry Nagel developed. Later Ken Kundert from Cadence contributed significant improvements to the core SPICE computing engine, mostly the Transient Analysis engine.So in retrospect LTspice isn't that bad, the MAC version seems to be inferior to the PC version in terms of UI tho.Best,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 06, 2021, 06:26:47 am
content: Check the default ESR, ESL etc. on the reactives, LTSpice likes to hide things from the schematic like that.Tim

author: peter-h
author_rank: Super Contributor
timestamp: December 07, 2021, 03:11:08 pm
content: I built this filter and it doesn't work at all. With C2 anywhere near the 5nF, it oscillates wildly.With C2=1nF it is ok but obviously a very different response. It is also stable with 2nF.Weird!

author: peter-h
author_rank: Super Contributor
timestamp: December 09, 2021, 12:23:47 pm
content: Interesting that nobody has spotted why it oscillates1nF is fine. 2nF produces a filter with a pretty high Q. Beyond that the phase shift goes all funny at higher frequencies - as the last graphic above shows (with 5nF). The simulator this supports what is really happening, including the big gain increase with ~2nF, but doesn't show the oscillation - presumably because - like all real oscillators - that needs some initial conditions set up.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 09, 2021, 05:18:55 pm
content: A check with transient simulation is always worthwhile.(Making sure there's a noise source somewhere, so that it starts up if it does oscillate.)A pole-zero analysis should show poles in the RHP, although for any nontrivial circuit, there always seems to be a mess of poles and zeroes, or I'm just using the analysis wrong, dunno.Tim

author: peter-h
author_rank: Super Contributor
timestamp: December 10, 2021, 02:40:31 am
content: Despite me being clueless on filters, I am amazed nobody spotted that this circuitislikely to oscillate, by looking at what the phase is doing in the plot I posted above.There is only one way this circuit can oscillate and that is the feedback cap. There is no other feedback. And if one starts at say 500pF and plots the amplitude and phase every 500pF, one finds the gain peaks sharply around 2000pFand after that the phase remains oscillation-favourable on the right hand side, eventually. There is a dramatic change either side of 2000pF.This is with 1000pF

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 10, 2021, 04:53:02 am
content: Positive phase shift, as in, predicting the future? A hallmark of RHP poles, yes.Tim