Die size and IC Package - Page 1
Forum section: electronics / beginners

author: Freshman
author_rank: Regular Contributor
timestamp: February 26, 2025, 10:09:57 am
content: I would like to gain a better understanding of IC package lead inductance and on-die capacitance.For a physically larger IC chip, would the on-die capacitance generally be higher due to the reduced distance between the pad on the die and the corresponding pad on the IC pin lead? Additionally, would the package lead inductance be lower because of the shorter connection length between the same pad on the die and the IC pin lead?Conversely, for a physically smaller IC chip, would the on-die capacitance be lower, while the package lead inductance is higher?Could you confirm if this understanding is correct? Any visual representations or diagrams would also be helpful for clarification.

author: AnalogTodd
author_rank: Regular Contributor
timestamp: February 26, 2025, 02:22:39 pm
content: The capacitance you would be talking about from package pins to the die is down in the femtofarad range, you won't get a big change as a function of die size. Honestly, there are larger amounts of capacitance on the die from the metal bond pad to the substrate of the silicon underneath (usually less than 2pF). You will find this hard to measure, with the on-die capacitance often being much more variable than you could measure as a function of die size.With regards to length of bond wires, a good rule of thumb is ~30nH/inch of wire. Most manufacturers use the smallest package possible (smaller for customer boards, less cost for the leadframe/package, etc.) so you might see a maximum difference of ~0.05in between a large die and a small die, so you would be talking about 0.15nH difference for the bond wire (the inductance for the lead would stay the same).

author: Freshman
author_rank: Regular Contributor
timestamp: February 26, 2025, 04:03:43 pm
content: Thanks for the answer. Any visual representation of the package lead inductance and on die capacitance?

author: AnalogTodd
author_rank: Regular Contributor
timestamp: February 27, 2025, 03:11:32 pm
content: Here's one I found just by searching for 'chip bond diagram':This is a large chip overall, and to really get at the idea of capacitance, you would have to look at the relative areas of the metallization on the die to where the corresponding pad on the IC is. Here's an example of wire bonded chip:You'll find that the areas facing each other are VERY small as the metallization on the die is maybe a few microns thick and the lead of the package is maybe a few hundred microns thick and the two are usually spaced with a fairly good distance between them. Heck, my estimation of femtofarads may have been generous.As for bond wire length, when you look at the die and the packages, you need to realize that there are reasons that large packages typically do not have small die in them. First is the cost of the package--for a commercial or industrial product that is on the same order as the cost of the silicon going into it. Second is to look at the image above--there are rules that must be met for spacing between bond pads/wires (and if they're going to the same pin or not), angles from the die going out, etc., that must be met. A big one for products that are in molded packages is wire wash; you can't have two long wires close to each other because the mold has the epoxy come in from certain points and it can cause the wires to move in the middle and potentially short.There's a lot going into decisions made for packaging of chips beyond just making the different connections from the die to the outside world.

author: jwet
author_rank: Frequent Contributor
timestamp: February 27, 2025, 03:49:51 pm
content: Just for completeness, the trend in IC packages over the last 20+ years has been away from die on lead frame with bond wires towards chip scale packages (CSP)- like flip chips where a die is mounted to a substrate somewhat like a tiny PCB with connections made without bond wires using conductive adhesives, etc and then molded over. This is how QFN's etc are made. Parasitics is one of the drivers as well as size, cost and reliability. Importantly, as IC processes shrunk, IC functionality grew and pin counts grew. Die on lead frame really starts to fall apart at about 200 pins. As Analog Todd said, IC packaging is a complex field unto itself. Though its not well known, most IC companies will provide bare die if requested subject to rather high minimum order quantities. (~5000 pcs). QFN's and other CSP's make this much less necessary than in the past.