Making opamps stable - Page 1
Forum section: electronics / beginners

author: AQUAMAN
author_rank: Regular Contributor
timestamp: June 30, 2014, 07:32:48 pm
content: Can anyone tell me why when I edit the capacitance C2 in this circuit, it completely ruins the output?Its a peak detector that removes the diode voltage drop but doesnt put the opamps into saturation as it needs to detect very fast peaks.You can see that when C2 is 2pF the circuit output seems fine, when it is changed to say 10pF it goes AWOLWhy is this? I'm obviously editing the time constant because the same things happen with the 10k resistor, but I need to undestand what Im doing if im ever to debug this in real lifeI attach images of 2pF; 10pF, and no capacitor at all

author: Andy Watson
author_rank: Super Contributor
timestamp: June 30, 2014, 08:11:03 pm
content: Complex, but here's a couple of suggestions: When U4 output is positive, it has a capacitive loading C1, and your are increasing the overall loop gain through U2 and U4. When U4 output is negative (with respect to U2's output), D1 conducts and you are joining the outputs of the two op-amps together via C2.

author: XFDDesign
author_rank: Frequent Contributor
timestamp: July 01, 2014, 04:12:44 am
content: There are a few things which look problematic, so I would ask what your end design goal is to see if we could come up with a better outcome. You mentioned that the block itself is to rectify without the drop (super-diode topology), but there circuit itself is highly non-linear which when put into a negative feedback loop ( as configured currently) it's easy to get sucked out to the sea of unstable loops.All of that being said, consider that your amplifier (LT1363) has remarkably low open-loop gain (at best 79dB, 71.6dB at worst). If you look at other parts (assuming you like the Linear family of products) such as the LT1013 (137dB) [precision, slow amp], LT1126 (128dB) [High speed amp] they have at least 56dB more gain - which will go further for reducing error in the loop.I think the first real step would be to break the loop and run the non-linear circuit and run it open loop.Hope this help some.Cheers!

author: Kevin.D
author_rank: Frequent Contributor
timestamp: July 01, 2014, 09:39:09 pm
content: Hi there . What is happening here is the opamp is ringing (overshooting) this happens because of low phase margin ,and since this is a Peak detector circuit it will capture the highest overshoot value .The opamp your using has built in compensation to enable it to drive any size output load and will not oscillate claims the data sheet ,but these "any load type" do still ring and overshoot when phase margin drops below about 35 deg .You can not see the ringing in your circuit due to the diode capturing the peak ,but you can see it if you remove the diode , Heres the ouput response to a fast pulse input .Also the xtra few pF of capacitance on your opamp input (diode in reverse bias has capacitance about 4pF for a 4148 )which also reduces your phase margin by another 5-10 or so deg .When you add cap across feedback you can get a modicom of compensation here but not a great deal (about +15 deg of xtra phase margin which may be enough) .If you add too much though the opamp output will rise to slow to capture high frequency events . (increasing this cap reduces the high frequency gain to less than -1) .Another way to increase your phase margin and your aquisition speed is to reduce your capture capacitor ,but this will also reduce your hold time though because of any charge leakage from the cap.( p.s the lt1363 has a huge 2uA input bias current so connecting the input of one of them to your storage cap will really reduce your hold time.)

author: Andy Watson
author_rank: Super Contributor
timestamp: July 01, 2014, 10:29:23 pm
content: Quote from: Kevin.D on July 01, 2014, 09:39:09 pmI suspect that the claim "to drive any size load and will not oscillate" does not take into account having two op-amps in the loop. Given that one of the op-amps is operating as a unity gain follower it is probably already maxed-out on available phase margin! Wouldn't take much to push it over the edgeI've not read the whole of the other thread, so this may already have been suggested: I would look at the possibility of using a sample and hold type circuit, either synchronously triggered, or possibly gated with a simple comparator.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: July 01, 2014, 11:51:20 pm
content: Hi,Here is some analysis on the original circuit.Simplified AC modelI am only considering the stages with U2 and U4. If we consider the circuit during the peak detection process, D1 will be blocking and can be removed from the circuit. D2 will be conducting and I have replaced D2 with a low value resistor. I have included the AC voltage source V1 to inject a disturbance into the loop. We can plot the closed loop gain of the circuit by plotting V(Va)/V(Vb).I can examine the loop gain with various values of capacitor using a .step statement:This is the results:The results show that the circuit is marginally stable with the capacitor value of 2pF and the conditions for oscillation are met if the capacitor is increased to 10pF.Time domain (Transient) ModelThe model was modified to the time domain:The result for 2pF shows stability but some ringing:With 10pF the circuit oscillates as predicted by the AC analysis:I haven't given any ideas on how to modify the circuit, but I have explained the behaviour.I have attached a zip file with my LTspice models.Regards,Jay_Diddy_B

author: AQUAMAN
author_rank: Regular Contributor
timestamp: July 02, 2014, 02:07:06 pm
content: Quote from: Kevin.D on July 01, 2014, 09:39:09 pmSome really great replies which I will respond toI'm not sure my hold time matters that much, as long as my ADC is able to sample at the same point each time and the droop is always constant. Its likely that the storage cap will be reset in under 100uS anyway so any reading by the ADC will probably be done 1-10uS after the 'peak' is detected.Yes when I decrease the storage capacitor the circuit seems to improve. However even with a 10p storage cap, if I only include 1k resistors for R6 and R2, it still wont track the change in the peak properly, and it is the change in the peak that I want to seeIn fact it is the same with the differential amplifier U3, even if all the resistor ratios are the same 10k vs 2k or 1k produces a dramatic change in the output of that U3 (mainly a lot more oscillations at 10k).I wonder when I build it whether I should include these parallel capacitances in my PCB, I wonder if the tracks and the resistors I use wont have 2pF capacitance built in them anyway.I have used these opamps before in a high speed circuit (an integrator) and actually the result on PCB was a lot cleaner than in simulation.

author: Kevin.D
author_rank: Frequent Contributor
timestamp: July 02, 2014, 05:16:49 pm
content: Yes the prob before was where you where putting the feedback cap across R6 ,Its not a very good place to put it (becuase your taking it from the output of the second opamp in the loop and it's output is also phase lagged,so then the cap wont be very effective). I didnt take the second opamp into account in my previous reply .Heres how I would get it stable ,You put the compenasation cap from the outputof U4 (not the output of U2 as before) to the - input of U4 .So it's in parallel with your D1. (D1 also has some capacitance of it's own about max 4 pF but this will reduce with it's reverse voltage), .This cap (Cf) combined with R2 and R6 rolls off your U4 bandwidth ,the larger Cf is the slower your opamp output rises but the greater your phase margin (upto a point) so increased stability ,you optimise your speed vs phase margin . Your crossover (loop gain =1 ) frequency for this opamp with a gain of -1 will be approx 1/2 pi Cf (R2*2) , so reducing R2 and R6 from your original 10k to 1k allows you to use a larger Cf for a given bandwidth ,(Requiring a larger Cf of ~20pF rather than a couple of pF means is good since your final circuit wont be effected as much by small pF size parasisitc capacitances like that from the diode and pcb tracks).Heres the response using the values I have used to a fast input pules ,notice no overshoot and quite a good rise time on the ouput of ~ 150 nS .Heres the bode plot (plot of gain and phase shift around the feedback loop) of this circuit ,if phase shift reaches 180 and Gain is > 1 that would be oscillation point .Just slightly Less than 180 and it will still ring .you can see a phase shift of 151 so we have about about 30 deg phase margin, which looks to be ok going from the earlier input pulse transient response test.Heres another bode plot of what happens when we put Cf directly across R6 like on your first post . You see phase margin is only 2 deg here .

author: AQUAMAN
author_rank: Regular Contributor
timestamp: July 02, 2014, 05:44:07 pm
content: THank you for your helpIm going to build a PCB and leave in spaces for these feedback capacitancesFirst Ill try to build it without them in and see if the parasitic capacitances from the tracks and connections solve the issues anyway, then Ill start adding in the capacitances.The new position for the feedback capacitor seems much better.