Threshold frequency for NO Signal Integrity issue for PCB - Page 1
Forum section: electronics / projects

author: Wilson__
author_rank: Frequent Contributor
timestamp: September 20, 2024, 05:35:11 pm
content: Is it correct that there will be NO signal integrity issue (no special layout technique) for MCU PCB:SPI clock 10MHzRise/fall time programmable 3 to 9nsOne MCU branching out to two chips, signal path length less than 10 inches (250mm)Some PCB factory says no issue for 50MHz and 10 inches.Wikipedia sayas, "On printed circuit boards, signal integrity became a serious concern when the transition (rise and fall) times of signals started to become comparable to the propagation time across the board. Very roughly speaking, this typically happens when system speeds exceed a few tens of MHz."Many thanks

author: tggzzz
author_rank: Super Contributor
timestamp: September 20, 2024, 05:55:01 pm
content: Signals can be compromised by many different mechanisms. Hence there can be no single magic number between good and bad.Asone simpleexample, consider a low frequency high current flowing through a ground lead. That could provide sufficient voltage difference to impair signal integrity.A useful starting point is Bogotin's rules of thumb on EDN.https://www.edn.com/category/blog/bogatins-rules-of-thumb/page/4/But any single.source is insufficient

author: Wilson__
author_rank: Frequent Contributor
timestamp: September 20, 2024, 06:27:07 pm
content: Quote from: tggzzz on September 20, 2024, 05:55:01 pmMany thanks. In this case, no large V nor A involved.

author: tggzzz
author_rank: Super Contributor
timestamp: September 20, 2024, 07:06:19 pm
content: Quote from: Wilson__ on September 20, 2024, 06:27:07 pmNow move on to consider all theothermechanismsFundamental insight: digital waveforms areanaloguevoltages (or rarely currents), which areinterpretedby the receiving chip's inputs as digital signals. Signal integrity is about anything andeverythingthat could compromise that interpretation.Signal integrity is a whole discipline; people make their living from teaching it in lectures and via books.

author: TimFox
author_rank: Super Contributor
timestamp: September 20, 2024, 08:08:55 pm
content: Be careful about stipulating "NO" in all-capitals (or "every" and other absolute adjectives).You need to specify an allowable or maximum acceptable level of contamination for such questions.

author: ArdWar
author_rank: Frequent Contributor
timestamp: September 20, 2024, 11:43:27 pm
content: There's no such thing as guaranteed problem-free limit for PCB layout. Unrelated to signal integrity itself, but one of the most common PCB design fail around MCUis to route fast GPIO next to its xtal, killing it or at least destabilize it upon toggle. 10MHz SPI certainly fits there, especially since SPI is hard push-pull drive.As for the signal integrity, 10MHz SPI usually isn't problematic. Unless you do ridiculously bad layout like cutting off it's return path. : Well, the oscillator driver where it tend to happen (early(?) STM32s) are so weak that you may conclude that no practical xtal are compatible with the requirement if you were to follow their design appnote for it.

author: Wilson__
author_rank: Frequent Contributor
timestamp: September 21, 2024, 12:04:59 am
content: Quote from: ArdWar on September 20, 2024, 11:43:27 pmGood point on Xtal. I would not think about that point. Input pin of Xtal osc is analogue signal, high impedence and weak. I guess it is to post and see what people say. This forum has impressive knowledgable people. Then do the layout and measure it.

author: Wilson__
author_rank: Frequent Contributor
timestamp: September 21, 2024, 12:06:10 am
content: Quote from: TimFox on September 20, 2024, 08:08:55 pmSorry not clear in wording. I am reading to determine whether 10MHz SPI over 10 inches PCB requires high-speed PCB layout techniques. One pcb factory ebook starts by saying, generally circuits lower than 50MHz, 10 inches do not require high speed techniques and reader can stop reading the next 100 pages.Yes, very good question on acceptable level of contamination. Thinking about it, may be counting at at voltage level crossed valid high/low threshold, it should meet setup time, hold time, rise/fall, minimum high/low pulse width, etc, right? Measured at receiver chip pin, ringing should be smaller than valid high/low voltage, right? For a rising edge signal, the lowest point of ringing should still be higher than valid-high voltage stated in datasheet.

author: tggzzz
author_rank: Super Contributor
timestamp: September 21, 2024, 08:58:34 am
content: Quote from: Wilson__ on September 21, 2024, 12:04:59 amAllof the inputs are analogue inputs, and have about thesameimpedance - a few pF for CMOS inputs.The difference is that the other inputsinterpretthe analogue waveform as a digital signal, and that implies they "ignore" most small voltage variations. In contrast, the XTAL input "notices" small input variations.Be aware that from the SI point of view, the signal period is completelyirrelevant. Theonlyparameter that matters is the transition time. To use anthropomorphic terms, the digital circuits neither "know" nor "care" when the next transition will occur. You can get ringing, non-monotonic transitions, setup and timing violations (especially thold) just as easily with a 10kHz waveform as with a 10Mhz waveform.For a little more theory and a practical demonstration and measurements, seehttps://entertaininghacks.wordpress.com/2018/05/08/digital-signal-integrity-and-bandwidth-signals-risetime-is-important-period-is-irrelevant/That discusses scope sampling rates, but for SI purposes the energy is the important point.As for PCB layout, look at the datasheets and/or application notes.

author: Wilson__
author_rank: Frequent Contributor
timestamp: September 21, 2024, 12:02:26 pm
content: Quote from: tggzzz on September 21, 2024, 08:58:34 amMany thanks. True, it is different interpretion. I looked up some doc.Pin is digital mode has 200mV hysteresisWould it is ok if ringing is, says, 150 to 200mV?TI Application Report SZZA043 - January 2004, CMOS inverted configurated as Xtal OSC with R placed between input and output, biasing it at middle of high/low, it has analogue gain of 25dB. Small noise pickup at OSC in pin will be amplified.When a pin is configurated as digital input, the Schmitt trigger circuit is enabled by default, with voltage hysteresis of 200mV.If I interpret correctly, says, input a sawtooth signal sweeping from 0 to 3V3 at 1Hz and mixed with square wave of 10MHz at 100mV peak to peak. With Schmitt trigger on as default, output likely be a clean transition at around mid voltage of 1.65V.Consider Schmitt trigger off. When the CMOS circuit is biased at mid point by the input sawtooth signal (instead of R in Osc), it should have same 25dB gain, right? There will be multiple transistion at 10MHz around 1.65V. Since the transistion is 10MHz and within the freq response of the SPI receiver circuit, it will response to it.

author: tggzzz
author_rank: Super Contributor
timestamp: September 21, 2024, 12:38:27 pm
content: Quote from: Wilson__ on September 21, 2024, 12:02:26 pmSimple answer: obey the listed specifications for the input voltages and input timings.More complex answer: noise on the power/ground lines can cause additional problems, as can outputs causing "large" currentchanges. The latter can cause voltages induced across the wires, wires on the PCB or inside the ICs, Vinduced=Ldi/dt. Such "noise" voltages on the PSU lines are equivalent to input voltage changes.QuoteAny such gain is highly dependent on many factors. The concept of gain in a schmitt trigger is meaningless except when switching is occurring.QuoteMore or less. See the datasheet for the upper and lower transition voltages.QuoteI don't know; I'm not familiar with the chip.

author: 2N3055
author_rank: Super Contributor
timestamp: September 21, 2024, 01:03:26 pm
content: A musician asks:"I plan to play an concert to a crowd that does not seem to have much musical education. How much out of tune I can play to consider it acceptable?.That is how OP question looks to me.Answer: instead to spend time figuring out how to cheat, just practice and tune your instruments perfectly. Slow designs or not, learning good practice is a long term goal. Slow designs will give you "forgiveness" that even if you don't do perfect work it will still work.And 10 MHz clock SPI and 3ns edges are more than 100Mhz BW. 250mm (a quarter of meter) is long for SPI..It is going to be nice antena..

author: Wilson__
author_rank: Frequent Contributor
timestamp: September 21, 2024, 03:43:41 pm
content: Quote from: Wilson__ on September 21, 2024, 12:02:26 pmSorry. Here are the missed diagram in my previous post

author: Wilson__
author_rank: Frequent Contributor
timestamp: September 21, 2024, 04:02:07 pm
content: Quote from: 2N3055 on September 21, 2024, 01:03:26 pmThat sounds fair enough. Thanks

author: 2N3055
author_rank: Super Contributor
timestamp: September 21, 2024, 04:26:40 pm
content: Quote from: Wilson__ on September 21, 2024, 04:02:07 pmNo offense was meant, just best intentions without beating around the bush..We are all tempted to do it the quick way. But with years you realize all those were just lost opportunities to learn. So when you need to do "same kind of project" but "with just 40 MHz SPI clock" and you can't make it work for the life of you.. Then you get it...But you ask questions and listen to answers. That is more than most.Best,