SRAM ce line - Page 1
Forum section: electronics / general

author: hedley
author_rank: Contributor
timestamp: July 20, 2021, 08:07:22 pm
content: I have some old boards using intel 80188uC with 2 x sram chips . I want to retain data in the sram when VCC fails. I connected a wired or diode pair - one to vcc and 1 to a nimh battery pack . When battery pack is powering the system the other side of the diode goes only to the power pin of the SRAMs and a pull-up resistor to both CE lines.The battery runs down rapidly - it appears as if when the CPU has no power the output CE lines ( lcs & ucs) are draining the battery , I suspect through protection diodes internal to the chip . I cut the traces on the PCB to verify this , which does seem to be the case .Request for help - please can someone send a diagram of how I could perhaps insert a mosfet “ in line “ on the two CE lines so that they effectively go “ open circuit “ when battery is powering the memory and then close when VCC is restored.Any help much appreciated .hedley.davidson@gmail.com

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 20, 2021, 08:33:38 pm
content: can you show us a small schematic of your mod?

author: Benta
author_rank: Super Contributor
timestamp: July 20, 2021, 11:33:20 pm
content: A possibility could be a 74HCT1G66 in series with the CE line powered from the OR'ed battery/VCC line. Connect the control input to VCC.A better idea would be using FRAM or NVRAM instead of SRAM. Would also eliminate the battery.

author: David Hess
author_rank: Super Contributor
timestamp: July 21, 2021, 01:36:01 am
content: The way battery backup is normally done is to include some extra discrete logic between the processor bus and memory to control -CE which itself is powered by the same backup supply so when power to the processor is removed, no extra load is presented to the battery.

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 09:07:50 am
content: Firstly excuse poor drawing - its an age thing. I was needing advice on how to insert the 2N7000 in the circled areas. The thinking is that when there is VCC the FET will be on thereby providing a low impedance patch for the 2 * CE lines.Then when VCC is removed the fet will turn off thereby preventing the battery VBAT draining through the CE line on the CPU , as it seems to be sinking current through the esd protection diodes internal to the chip as the pin is pulled high by the 10K resistorstherefore forward biasing the high side esd diode . FRAM is not an option as we have over 1000 of these boards in the field for the last 25 years and they use a K6XX4008CIF-GB70 OR BS 62LV4006SIP55 OR BS 62LV4007SC-70 all of which are 32 pin form factor so I have been unable to find the same foorprint FRAM or NVram + they are very expensive so I was hoping to Frankenstein a solution

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 10:52:03 am
content: I TRIED TO ADD A MORE READABLE DIAGRAM - see attached .The yellow circles are where the switching FET's would be needed . I guess as the 2n7000 is enhancement mode , it would also need a pull down resistor on the gate ? . The gate would be connected to the VCC line so that when there is vcc the fet would be on with a Rdson on 5 ohms and an ID of 200ma continuous so may do the job . Th Vgs is 800mv so dont see a problem turning it on . The key questions are :1. Would this work2. Has anyone else seen an unpowered processor drain batteries through the I/O pin esd diodes.3. Which way around must the fet be installed - I think with Drain facing the pull-up resistor and the Source connected to processor pin ?

author: oPossum
author_rank: Super Contributor
timestamp: July 21, 2021, 02:28:32 pm
content: This is the easy way:https://datasheets.maximintegrated.com/en/ds/DS1312.pdfUnfortunately a rather expensive chip.A CD4066B (to switch CE, WE, RD) and a power good circuit may be a workable solution.

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 02:44:41 pm
content: Thanks for response but as mentioned before the pin out and footprint are different which would require a new layout and production run plus field replacement and as it is a 25 year old system the client wants a cost effective “ band aid fix “ . Some years ago I saw a circuit using a fet to do exactly this , but can’t remember - duh . If I measure between processor CE pin and VSS with a meter on un unpowered board it is 6k4 and almost the same between the CE pin and VCC.The requirement appears simple - supply battery power and hold CE/ high to retain data . This works fine BUT due to the CE/ line on the processor chip the battery drains in about 20 hours . The battery is a nimh 4.8V , 2400mAh pack .

author: edavid
author_rank: Super Contributor
timestamp: July 21, 2021, 02:56:31 pm
content: 2N7000s are not suitable for 5V logic since the VGSis too high. You would need logic level FETs.I don't think a 4066or even an HC4066is a good idea because of RC delays. HC4066 should be OK.However, these are logic signals, so there's no need for analog switches. A 74HC32 + inverter (or TL7705/some other supervisor IC) would probably work well.How are you going to prevent the CPU from scribbling on the SRAM during power down? Do you have control of the firmware?

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 03:04:02 pm
content: I did order some analogue switches as per a pervious post . I thought the Vgs was 800mV ? . I will look at your suggestions and yes we wrote all the firmware back in the day . The EPROMs we used were end of life many years ago so overall a bit of a challenge which I’m sure all on the forums are used to . I aged a lot due to two words in our industry ( EOL and MOQ ) , especially being in low volume industrial electronics where systems have to last 10 years at quotation time.

author: CJay
author_rank: Super Contributor
timestamp: July 21, 2021, 03:17:38 pm
content: How is it drawing enough current through a 10K resistor to deplete a 2.4AH battery in 20 hours?My head and my calculator say that's less than half a mA so I don't think it can be draining it through the /CE line, could it be as simple as an incorrect resistor?have you measures the current drawn through the cut track?What am I missing?

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 03:33:05 pm
content: Yes I use a Rigol DP832 bench supply to provide the - VBAT and therefore can monitor and plot the current drawn . I was also confused so cut the tracks at the two CE outputs of the processor LCS and UCS on pin 100 and pin 92. As soon as the tracks are cut then current to power the ram goes down to uAmps .Regarding the other question of scribbling the ram contents I am proceeding based on pulling CE line high soonest , which then ignores the read and write lines .

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 21, 2021, 03:41:12 pm
content: Can you not just "isolate" the CE lines with diodes? So adding a diode between the processor's signal and the CE line of the RAM chip? This way you have a OR function between the microprocessor and your backup battery.

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 03:42:08 pm
content: I agree that something odd is going on . Ohms law would suggest that a 4.8 volt battery through a 10k would take a long time to discharge. If I measure with a scope the one side of the 10K is at 4.8v as expected and the other side which is the CE line pull-up is at 1.02v . Which would suggest 378uA is being drawn . I’m based in SAafrica so have left office and will start afresh in the morning . Thanks again for sanity check , it normally ends up being a simple error as outlined in the book “ the dog barks when the phone rings “

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 03:47:36 pm
content: I did try that as a first step but the vf of the diode .6 volts caused issues under normal operation . That then led me to look for mosfets with a low rds in the region of max 5 ohms . And then I fell down the rabbit hole and was hoping someone had had issues with a non powered processor chip providing paths to voltage rails where I suspect the current is flowing , do to cutting the tracks at the processor , resulting in significant reduction in current drawn .

author: CJay
author_rank: Super Contributor
timestamp: July 21, 2021, 03:48:53 pm
content: Ahh, so it must be enabling something else which is drawing all the current through the diode on the VCC line.Is VCC to the SRAM chips isolated from the rest of the board or is it perhaps somehow still connected to some other components too?

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 04:02:32 pm
content: We use Cadence Allegro for PCB design . On PCB Editor , When I select the net eg LCS the only devices connected are the SRAM pin 20 the processor pin 92 and the pull-up resistor . As far as power is concerned the VBAT net is connected to the pull-up resistor and the 2 x SRAM chips and 1 x RTC . This makes me think that under battery power all other chips on the board and discretes have no power . I will confirm with measurements as there are things like an old ALTERA flex chip with custom VHDL code and these gobble power .

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 21, 2021, 04:13:04 pm
content: Quote from: hedley on July 21, 2021, 03:47:36 pmAh, I see. You could have tried a Schottky diode, but unfortunately, those tend to leak (in reverse) a lot more. So in the end, you probably wouldn't gain anything much.

author: Benta
author_rank: Super Contributor
timestamp: July 21, 2021, 06:25:36 pm
content: Quote from: edavid on July 21, 2021, 02:56:31 pmWhat RC delays? passing CE through an analog switch is significantly faster than through a logic gate.Please explain your thinking.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 21, 2021, 06:49:54 pm
content: Yes, when /CE and /OE are pulled low by the unpowered circuit, the RAM's outputs assert. Probably at address 0 for the same reason. /WR should be pulled low too but check the datasheet for precedence (I think it's still read?). If you'd stored nonzero data at that location, the active pins will be backfeeding the bus, probably putting a few volts into the circuit via ESD diodes.MOSFETs won't do here as they have massive capacitance (~30pF), and as mentioned the threshold voltage should be lower to deal with TTL level logic.An analog switch is okay, given that its resistance is low enough -- with only the RAM's control pins after it, a CD4066 is probably enough, but I'd be more comfortable with a 74HC4066 or better.Any logic gate that disconnects its output when unpowered, will also work. A plain buffer function will do, and then it can be powered by VCC, and the pullup resistors to VBAT take over when off. 74LVC family is a good example, though it's not really suitable for 5V (it can be used there, but it's tight, and better suited to 3.3V operation). I'm not sure if there's a 5V family that does that?Transmission gates can also be used. 74HC125 and the like, with /OE's driven from inverted VCC (note the inverter needs to be powered by VBAT), will deassert the signal and the pullups to VBAT take over.The HC4066 is probably the simplest, not needing an inverter; complete logic solutions I think require two chips (e.g., 3 NAND + 3 NOT), or some manner of discrete glue logic, which tends to cost speed or current draw. The pullups are kind of a compromise, that fortunately don't cost VBAT current because of when they're used.Tim

author: edavid
author_rank: Super Contributor
timestamp: July 21, 2021, 06:52:25 pm
content: Quote from: Benta on July 21, 2021, 06:25:36 pmWhoops, you're right, at least for an HC4066 or better.

author: edavid
author_rank: Super Contributor
timestamp: July 21, 2021, 07:02:36 pm
content: Quote from: T3sl4co1l on July 21, 2021, 06:49:54 pmThis is confusing. If /CE, /OE, and /WR are all low, the databus will be Hi-Z, and data will be overwritten.Conversely, when /CE is high, /OE and /WR are don't cares.QuoteIf you use 74HC32 as I mentioned, you don't need pullups.

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 07:05:02 pm
content: Thanks for reply and a lot of food for thought . I will go through each suggestion and ensure I understand in depth and then build up on veroboard and test . Expected delivery of some of the components is in 8 days .

author: hedley
author_rank: Contributor
timestamp: July 21, 2021, 07:17:32 pm
content: section of sram datasheet showing why my prime objective if to hold CE high.

author: Benta
author_rank: Super Contributor
timestamp: July 21, 2021, 07:52:20 pm
content: Here's a suggestion.If you have more than one CE, you only need to duplicate U2 and R1.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 21, 2021, 08:38:29 pm
content: Quote from: edavid on July 21, 2021, 07:02:36 pmAh, write-dominant after all, got it. Which will hold the chip active of course, but won't do more than that. Doesn't seem to be any reason then that it would "drain rapidly"...Or, HC32 needs an inverter still, but since it's just CE needing the treatment, a 74HC2G02 will do it all in one chip.The Schmitt trigger is a nice touch; I don't know that it's really necessary, so what if it chatters a bit? -- Well, depends if /WR is read as asserted during that time, doesn't it. Which is a concern for whatever type of gate here, so, that probably helps but isn't a guarantee, hm.Really what should be used, is something to detect failing power, before it crosses any logic threshold -- then you can guarantee no data loss during power cycles. An active-high reset generator / voltage detector IC would be perfect here.Tim

author: Benta
author_rank: Super Contributor
timestamp: July 21, 2021, 09:04:29 pm
content: Quote from: T3sl4co1l on July 21, 2021, 08:38:29 pmI'm totally with you here, the main power supervisor should ideally be tied in to this. But as we have no idea what it looks like, it's pure guesswork.All the rest is a workaround, and my suggested circuit was meant as such (read: quick fix).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 21, 2021, 10:36:27 pm
content: No I mean that as a quick fix too -- supervisors are as jellybean as transistors, handy for many things besides reset generation as such! Although that's pretty much the application here, so it's a natural fit.Tim

author: hedley
author_rank: Contributor
timestamp: July 22, 2021, 09:03:21 am
content: Many thanks to all for response . See summary attached and we have ordered the parts and will try out Benta suggested " quick fix .

author: hedley
author_rank: Contributor
timestamp: July 22, 2021, 03:47:19 pm
content: The joys of pandemic - just have been advised that earliest shipping date for 74LVC1G17QW5 is 23 June 2022 . GRRRRRRR

author: edavid
author_rank: Super Contributor
timestamp: July 22, 2021, 04:03:07 pm
content: Quote from: hedley on July 22, 2021, 03:47:19 pmThousands in stock at DigiKey, Mouser, Newarkhttps://www.findchips.com/search/74LVC1G17QW5

author: hedley
author_rank: Contributor
timestamp: July 22, 2021, 04:06:48 pm
content: Tks will look - I noticed that I started the exercise on 2017 and gave up - see forums topic “ Battery power “ . I know remember that this is where the 2N7000 was suggest as well as the DS1250 NV ram which now runs at $ 94 per chip on mouser and is a dip so would need a converter PCB and rework of all boards installed in the field .

author: oPossum
author_rank: Super Contributor
timestamp: July 22, 2021, 04:16:13 pm
content: DS1312 is a NVRAMcontrolleravailable in SOIC for about $9.https://www.digikey.com/en/products/detail/maxim-integrated/DS1312S-2-/956884https://datasheets.maximintegrated.com/en/ds/DS1312.pdf

author: hedley
author_rank: Contributor
timestamp: July 22, 2021, 04:45:01 pm
content: After a day of measurements key major issue is the voltage drop across the 10k pull-up resistors on the CE lines . If I lift the processor pins then there is only .46 volt drop so CE line high value is within spec . With processor pins connected then volt drop is 4.16Volts resulting in the CE lines being under 1Volt. To make things more difficult the processor datasheet does not have output and input pin impedance values . If I measure between lifted processor pin and ground on a non powered board the resistance is 330k ohms .m

author: Benta
author_rank: Super Contributor
timestamp: July 22, 2021, 05:03:48 pm
content: Quote from: hedley on July 22, 2021, 03:47:19 pmYou may not need it, I put it in there as a safety measure (important with 5k units in the field). You should be able to test the circuit using only the 1G66 parts. The VDD/Battery diodes should be Schottky types of course.An alternative solution is using two 74LVC1G14 in series, they may be easier to source.

author: hedley
author_rank: Contributor
timestamp: July 22, 2021, 05:10:29 pm
content: Thanks , we’re in the jungle here in South Africa , and normally purchase through RS - Components . I’ll give mouser a try as if this works we have to mod about 1000 boards , so will buy a reel and make a small add on , board that we can do on our in house prototyping p & p machine .

author: hedley
author_rank: Contributor
timestamp: July 23, 2021, 05:55:41 pm
content: Where I started in 2017 which worked on sim . I’ll wait for parts and build as per benta suggestion

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 23, 2021, 06:17:25 pm
content: Quote from: hedley on July 22, 2021, 03:47:19 pmYeah. OTOH, it's never been easier to get junk food delivered at your door within 30 minutes. Maybe that says something about our priorities?

author: hedley
author_rank: Contributor
timestamp: July 24, 2021, 08:47:30 am
content: lT spice sim which also works , so ill give the fet based solution one more try . The 4k7 in place of 10k pullup will help meet SRAM VCC to CE/ line criteria for data retention , and importantly I did not have the n channel fet drain resistor to ground in original circuit so it basically never turned off to isolate the processor .

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 24, 2021, 09:50:57 am
content: It's a fine solution at DC. But try it with a 100 ohm, 5ns rise PULSE at nCE.Tim