74xx181 help needed - Page 1
Forum section: electronics / beginners

author: bitman
author_rank: Unknown
timestamp: July 12, 2017, 08:22:21 pm
content: I know the 74181 is ancient - I'm attempting to build a very basic CPU using old TTL chips. But I've run into a problem with the 181 - I simply am not able to grasp how the function table is to be used - I don't get the idea of being able to use "active high" and "active low" at the same time.Datasheet:http://www.ti.com/lit/ds/symlink/sn54s181.pdfI'm looking for a "dummies guide" or something, because I cannot find the "AND", "OR", "XOR" features. I wanted a simple way to create most common ALU features including Increment - but all I can find is "decrease by 1".Note, I have foundhttp://www.righto.com/2017/03/inside-vintage-74181-alu-chip-how-it.htmlbut it focuses mostly on the cascading aspect of the chip, which right now isn't important to me. I like the tester this site has, if I could just figure out how the function selector relates to the data sheet.

author: chris_leyson
author_rank: Super Contributor
timestamp: July 12, 2017, 08:38:52 pm
content: Found some VHDL from when I was simulating the Cinematronics CPU, the formating didn't come out to well.Code:------------------------------------------------------------------------------------ Company:-- Engineer:---- Create Date: 12:56:53 03/31/2009-- Design Name:-- Module Name: S181 - Behavioral-- Project Name:-- Target Devices:-- Tool versions:-- Description:---- Dependencies:---- Revision:-- Revision 0.01 - File Created-- Additional Comments:------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity S181 isport (cn : in std_logic;m : in std_logic;s : in std_logic_vector (3 downto 0);a : in std_logic_vector (3 downto 0);b : in std_logic_vector (3 downto 0);fout : out std_logic_vector (3 downto 0);c4 : out std_logic;Xout : out std_logic;Yout : out std_logic;eq : out std_logic);end S181;architecture Structural of S181 issignal f3,f2,f1,f0: std_logic;signal h3,h2,h1,h0: std_logic;signal i3,i2,i1,i0: std_logic;signal nm,x,y: std_logic;signal x3,x2,x1,x0: std_logic;signal z3,z2,z1,z0: std_logic;signal nb3,nb2,nb1,nb0: std_logic;signal alu_13: std_logic;signal alu_45: std_logic;signal alu_55: std_logic;signal alu_58: std_logic;signal alu_61: std_logic;signal alu_64: std_logic;signal alu_66: std_logic;signal alu_68: std_logic;signal alu_70: std_logic;signal alu_72: std_logic;beginh3 <= not(((s(2) and nb3) or (s(3) and b(3))) and a(3));h2 <= not(((s(2) and nb2) or (s(3) and b(2))) and a(2));h1 <= not(((s(2) and nb1) or (s(3) and b(1))) and a(1));h0 <= not(((s(2) and nb0) or (s(3) and b(0))) and a(0));x <= not(h3 and h2 and h1 and h0);y <= not((((((i0 and h1) or i1) and h2) or i2) and h3) or i3);alu_13 <= not(cn and h3 and h2 and h1 and h0);i3 <= not((s(1) and nb3) or (s(0) and b(3)) or a(3));i2 <= not((s(1) and nb2) or (s(0) and b(2)) or a(2));i1 <= not((s(1) and nb1) or (s(0) and b(1)) or a(1));i0 <= not((s(1) and nb0) or (s(0) and b(0)) or a(0));nm <= not m;z0 <= not(cn and nm);z1 <= not(((cn and h0) or i0) and nm);z2 <= not(((cn and h0 and h1) or (i0 and h1) or i1) and nm);z3 <= not(((((cn and h0) or i0) and (h1 and h2)) or ((i1 and h2) or i2)) and nm);alu_45 <= not(f3 and f2 and f1 and f0);f3 <= not((z3 and x3) or alu_55);f2 <= not((z2 and x2) or alu_58);f1 <= not((z1 and x1) or alu_61);f0 <= not((z0 and x0) or alu_64);x3 <= not((i3 and h3) or alu_66);x2 <= not((i2 and h2) or alu_68);x1 <= not((i1 and h1) or alu_70);x0 <= not((i0 and h0) or alu_72);alu_55 <= not(z3 or x3);alu_58 <= not(z2 or x2);alu_61 <= not(z1 or x1);alu_64 <= not(z0 or x0);alu_66 <= not(i3 or h3);alu_68 <= not(i2 or h2);alu_70 <= not(i1 or h1);alu_72 <= not(i0 or h0);nb3 <= not b(3);nb2 <= not b(2);nb1 <= not b(1);nb0 <= not b(0);--fout <= f3 & f2 & f1 & f0;--c4 <= not(y and alu_13);--Xout <= x;--Yout <= y;--eq <= not alu_45;fout<= transport f3 & f2 & f1 & f0 after 20ns;c4<= transport not(y and alu_13) after 30ns;Xout<= transport x after 20ns;Yout<= transport y after 20ns;eq<= transport not alu_45 after 40ns;end Structural;

author: jmelson
author_rank: Super Contributor
timestamp: July 12, 2017, 08:44:21 pm
content: There is no active low function, although the logic functions all have fairly reasonable results if the A, B and F pins are considered to be inverted data.For logic functions, hole M high. And is written as AB, so the select pins would be HLHH. OR is A+B, so that is HHHL. XOR is A "xor" B, where the XOR symbol is a + in a circle, so LHHL.Some of these functions are available with M=L also. With 4 select pins plus M (mode) you have 32 possible logic combinations, not all of them really useful.Jon

author: bitman
author_rank: Unknown
timestamp: July 12, 2017, 09:07:01 pm
content: Quote from: jmelson on July 12, 2017, 08:44:21 pmHmmm the datasheet says it can be used both ways ... well, all I need is active high, so I'm fine by just using that. Thanks for explaining the symbology. How do you tell the difference between + for OR and + for ADD?

author: uwezi
author_rank: Unknown
timestamp: July 12, 2017, 09:55:05 pm
content: Quote from: bitman on July 12, 2017, 09:07:01 pmIn the table from the datasheet ADD is written as PLUS to avoid this conflict...

author: rstofer
author_rank: Super Contributor
timestamp: July 12, 2017, 10:18:39 pm
content: Look at your table again and consider what the M signal is doing. If M is HIGH the chip does the logic functions in the left column. If M is LOW, the chip does the arithmetic functions in the right two columns depending on the value of Cn'. Be careful with the definition of Carry In - it's LOW to indicate a CARRY IN.

author: amyk
author_rank: Super Contributor
timestamp: July 13, 2017, 01:53:59 am
content: Look here:

author: bitman
author_rank: Unknown
timestamp: July 14, 2017, 08:23:06 pm
content: Thanks everyone. I now get what I missed before and things make a lot more sense now.

author: Zero999
author_rank: Super Contributor
timestamp: July 14, 2017, 08:40:47 pm
content: Do they still make it today?I notices there's an HC variant and found a datasheet last updated in 1998 which still seems very recent for what it is.http://pdf.datasheetcatalog.com/datasheet/philips/74HC181N3.pdf

author: bitman
author_rank: Unknown
timestamp: July 14, 2017, 09:49:37 pm
content: Quote from: Hero999 on July 14, 2017, 08:40:47 pmI found some on Ebay - from their condition I would definitely not say they are new.

author: Sweeney
author_rank: Newbie
timestamp: July 14, 2017, 10:28:11 pm
content: Quote from: bitman on July 12, 2017, 08:22:21 pmI can see the potential confusion if you are referring to the following part:I highly doubt you will find the need to design active low inputs and active low outputs. If you are familiar with DeMorgan's Theorems, you can recognise that all they've done for the active low side is inverted the input variables, then inverted the whole term at the output and simplified it for convenience.Maybe the following image is going to help:Having said that, it can be a bit confusing to describe an AND-gate as an OR-gate in an active low input/output configuration.

author: bitman
author_rank: Unknown
timestamp: July 16, 2017, 03:58:42 pm
content: Quote from: Sweeney on July 14, 2017, 10:28:11 pmSo first of, I got my 181 ALU working thanks to the feedback here. That said, this particular area is still confusing to me. I get that using the selector I can have some inputs/outputs inversed. I wonder if the claim that you can use active high and active low inputs is simply tied to different selectors are applicable only if you're using active high and others when you're active low. If that's the answer, then I follow but man was that described in a twisted way in the datasheet. To me, it means I have a lot less features albeit from this list I realized there were 32 total potential combinations - not 16 as I thought. So win some lose someQuoteI don't see that setup in the logic gate setup at all. I see a few inverters here and there, and I see why this is a great circuit learning from - I'm still studying it and now that I understand how to use the chip, it's helping a lot to dissect the different areas of the chip. But understand when I initially read the data sheet I thought the statement was about the chip "auto sensing" the "active" setup I was using - and that simply didn't make sense.

author: rstofer
author_rank: Super Contributor
timestamp: July 17, 2017, 03:00:53 pm
content: The chip uses combinatorial logic to form some output based on various control bits (5) and operands. It simply doesn't care if you are using active high or active low logic levels, the result is interpreted by the surrounding logic.Look at the LOGIC output for the control pattern LLHH - it is logic 0 for active high logic. In other words it is 0V. When considered as active low logic, the output is logic '1' which is, again, 0V because we're thinking active low. The chip put out exactly the same thing in both cases. It is all in how the user thinks about logic levels. The chip doesn't care.It is difficult to wrap your head around active low but we do use it all the time. Look at the Carry In and Carry Out signals. They are active low (assuming active high logic). Asynchronous set and reset signals for D flops are typically active low.

author: retrolefty
author_rank: Super Contributor
timestamp: July 18, 2017, 12:38:28 am
content: The '181 was the goto ALU chip in the very competitive mini-computer era of the 70s, most all used them in their 16 bit processors. Never found one failed in 10 years of field service on such systems.

author: bitman
author_rank: Unknown
timestamp: July 18, 2017, 03:35:09 am
content: Quote from: retrolefty on July 18, 2017, 12:38:28 amI believe you. I tried my best to fry it by switching S(elector) and F(unction) inputs around - not sure how I made that setup error, but the consequence was a very warm chip. Once fixed, it still hummed along just nicely. Very robust.