TPS552882 Buck-Boost circuit (reference PCB/SCH used). - Page 1
Forum section: electronics / projects

author: Psi
author_rank: Super Contributor
timestamp: August 17, 2025, 01:01:09 am
content: I'm having an issue with the TPS552882-Q1 36-V, 16-A buck-boost converter and i would appreciate any suggestions where the issue might be.It's probably something simple/stupid but I've not been able to track it down.Design specs are 10-30V input and 13.5V output at hopefully 5A.Frequency is set to 400khzILIM (avg/peak current limit set to 10A)Output current limit set to 5AI'm using component values from the WEBENCH® Designer as my starting point and the PCB layout is a direct copy from the datasheet.Note that 2 H-Bridge fets are built into the TPS552882RPMR and 2 are external (buck-boost with synchronous rectification).The issue is that it only ever outputs around 3V (no load) it never gets into voltage regulation.Parts used are- Controller TPS552882RPMR -https://www.ti.com/lit/ds/symlink/tps552882.pdf?ts=1633815350361- Inductor - 10UH 12.2A 16.1MOHM MPXV1D1264L100https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/209/MPXV_Series_DS.pdf- NFETs - 60V 60A -https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcsd18543q3aMeasurementsWhen it's powered, and has 3V at the output, I took these measurements (11V in and <10mA draw)FB pin = 0.24V (should be 1.2V Vref when regulating)UVLO = 1.43V = ok, shutdown at < 1.23VPG currently pulled low (makes sense, output is low and not regulating)CC currently high, (not in current limit)VCC = 5.13V (correct)Here's the schematic / PCB / PCB Layers and all the images and scope traces I could think of that might help.The traces 'startup' & 'startup initial' were taken from inductor to GND (SW2 side) triggered at first power on.All the other traces are taken once it's producing 3V.

author: Psi
author_rank: Super Contributor
timestamp: August 17, 2025, 01:03:51 am
content: More imagesThanks in advance for any help.Also, side note, if you have been using your Siglent scope with USB sticks to grab images try the LAN port instead, web browser control and screenshots are awesome!

author: Psi
author_rank: Super Contributor
timestamp: August 17, 2025, 03:58:57 am
content: I've figured out the startup issue.There was a bad solder join on one of the IC pads.I had removed and reinstalled the IC twice previously without any improvement, so I had assumed the issue was elsewhere. But I just did it again a 3rd time and it' now working.

author: Psi
author_rank: Super Contributor
timestamp: August 17, 2025, 04:18:03 am
content: The new thing I'm looking at is some instability around the transition point between boost and buck. (coil screams and current is 150mA instead of 40mA)I can completely fix it by adding 1000uF of output capacitance but that seems a bit ridiculous. Shouldn't need that much.In the reference design they have some ceramic and some electrolytic but for my design I want only ceramic.Is there a reason why I might need some high ESR bulk capacitance ? eg, do i need to have some ceramics with 1R in series to simulate some bulk high-esr capacitance to make it stable?(The ref design has 10UF ceramic + 56uF electrolytic. I currently just have 70uf of ceramic (10uf x 7))

author: Someone
author_rank: Super Contributor
timestamp: August 17, 2025, 05:32:29 am
content: Quote from: Psi on August 17, 2025, 04:18:03 amDo you need the $$$ of time in measurement, modelling, and simulation to answer that?If the 1000uF is too much for you then back off the capacitance in ceramics, ballpark is 10:1 alu:ceramic for benign designs. Or stick with the eval boards choices.

author: Psi
author_rank: Super Contributor
timestamp: August 17, 2025, 08:48:31 am
content: Any tips for stable operating when the Vin is right on the edge of UVLO shutdown.It seems to kill the chip sometimes. Current should be fine, UVLO is 9.5V so nothing that should have crazy high currents.Maybe my 3.3nF across the shutdown divider lower resistor is a bit small and causing it to go in and out of shutdown too quickly. That's the next thing to test after i change the chip for the 4th time., hahaAlso regarding the cap situation, I seem to have the output ripple under control now with 70uF ceramic and 100uF electro. But I found that webdesigner has an option to generate with only ceramic caps.Looks like I was correct, the designer wants to add 110uF at 1uOhm and 5.8uF at 1mOhm. So definitely wants a combination of ESR's.

author: Psi
author_rank: Super Contributor
timestamp: August 17, 2025, 10:01:36 am
content: OK, It wasn't that cap on the ULVO line. as it blew up again.It seems that if you have it running at high load and you drop the input voltage down to under the 9V cutoff you get an inductor scream and the chip is dead.Actually I now wonder if i don't have enough input capacitance and the current needed at 9V is just too high for the caps I do have.I will have to park this until more chips arrive. I only bought 5, should have got 10 or 20.

author: scottapotamas
author_rank: Regular Contributor
timestamp: August 17, 2025, 11:14:57 am
content: I've just finished integrating/validating this exact regulator for 8.5-24VIN 12VOUT 10A and generally been pretty happy with the results. Can't really dump it all here but if there's specific areas of the design I'm happy to help compare. I didn't use Webench for the design at all, so maybe run your parts through the excel spreadsheet from TI's website and see if anything comes out differently?Input capacitance is a bit tricky because fed by a BMS on the same board, but I've got a 68uF hybrid on the input with about 40uF of ceramics after derating, 100uF hybrid on the output with similar to the input side. No issues around the mode transition point.I can see you're closer to their recommended layout, mine looks more like the one proposed in their EMI testing app-note for this reg, with the symmetrical input caps around the buck fets.I've got a handful of boards with plenty of spares so happy to do a deeper schematic comparison, maybe load one to try and reproduce your failures?

author: Psi
author_rank: Super Contributor
timestamp: August 17, 2025, 12:31:05 pm
content: Thanks!The instability between boost->buck transition was just output capacitance, that is all fixed now.Yeah, I'm 99% sure my current issue is just a lack of enough 'true' input capacitance. It's almost definitely causing loop instability at high current and responsible for the coil wine and failure.The combination of loop instability with the stop/start/stop/start from being right on UVLO seems to be a bad combination.Did you have any hand soldering issues with this IC, I'm pretty good at soldering QFN/DFN and even some large BGAs. I don't normally have any issues but this IC seems to be giving me some problems. I think it's just the combination of easy to solder outer pads and big center pads with so much thermal mass. I plan to drag out the pre-heater when my new chips arrive.

author: scottapotamas
author_rank: Regular Contributor
timestamp: August 17, 2025, 02:27:03 pm
content: I've probably done a dozen or so by now? I've got them on a 2/1/1/2oz board and don't have issues hand soldering them.Across the batches of prototyping I've done hot-plate with hot-air assist (bizmuth), air pre-heater with hot-air (SAC305), and vapour phase (SAC305). Only assembly issues on these boards have been some high density board-to-board connectors and minimal excess ball formation.Attached L1 of an older layout, should look fairly recognisable.

author: Psi
author_rank: Super Contributor
timestamp: August 18, 2025, 09:26:34 am
content: What ceramic capacitor brands do you recommend that provide full data like ESR and DC bias graphs for their parts.I know TDK is really good, they're also expensive, but what others are good?

author: scottapotamas
author_rank: Regular Contributor
timestamp: August 18, 2025, 10:37:25 am
content: Depends on what you consider expensive, volumes etc. I'm mostly low-volume, high-margin so not too constrained.TDK and Murata have good parametric search with the curves on their websites. I use mostly TDK, Murata, Panasonic, Würth, Kemet parts. The data is usually available for the other brands with a little more digging.I think the larger ceramics around this reg were about $0.20ea so not a huge concern for me, but I'm not too deep into optimising the BOM at this stage.Don't just look for the largest capacitance available in a given package, the DC bias derating curves often get steeper near the extremes than a more reasonably rated part.

author: mtwieg
author_rank: Frequent Contributor
timestamp: August 18, 2025, 11:34:01 am
content: Quote from: Psi on August 17, 2025, 10:01:36 amAccording to the datasheet, an UVLO should trigger a new soft start. The soft start time is internally fixed at 4ms (unfortunate). I'm guessing the "scream" you hear is due to the thing repeatedly tripping the UVLO.To avoid the UVLO/SS loop, you want to add more hysteresis on the EN/UVLO pin. Do this by increasing R10 and R12 (keeping the same ratio). As for C17, it's not clear why they add this capacitor, or what value it should be. I would keep the time constant of that filter much less than the soft start time (under 1ms).The amount of hysteresis necessary is a bit complicated to predict. Basically you should ensure that the maximum input current at the minimum Vin does not cause enough change in Vin to drop below the UVLO threshold. In your schematic you have those two schottky diodes on the input, so that change in Vin is at least 0.5V. So R10 should be at least 100K (0.5V/5uA). I would just double R10 and R12 to 150K and 22K, respectively.Oh, and another thing to consider is that if your power source has its own current limit, that must be higher than the peak input current drawn by the TPS552882. If it does hit its current limit, then the UVLO/SS loop will be very difficult to avoid.Even if that does avoid the UVLO/SS loop, I still think something is amiss. Even if the controller is being repeatedly disabled, this should not put extra stress on anything, if the controller is properly designed and implemented. If I were you I would investigate this failure mode more. I would manually force EN/UVLO low and carefully observe behavior during and after the soft start. Watch for excessive input current or ringing in the output voltage. Then drive EN/UVLO repeatedly with a function generator, starting at a low frequency (like 10Hz), and slowly increase that frequency while watching for temperature rise.

author: Psi
author_rank: Super Contributor
timestamp: August 18, 2025, 11:47:23 am
content: Quote from: mtwieg on August 18, 2025, 11:34:01 amThanks,yeah i'm suspecting the issue may be more related to lack of enough input capacitance than the UVLO in itself.My guess is when i fix that issue the UVLO transition will be fine, but i cant test it until new chips arrive.I have also properly tuned the comp using the provided excel file for the chip, since i had nothing else to do. The original comp values were from the webbench designer tool and where more intended for rapid response to drive digital logic which i don't need for a battery charger. So I have re-tuned comp for 2khz loop instead of 10khz which should make it more stable and less twitchy

author: Psi
author_rank: Super Contributor
timestamp: August 20, 2025, 06:22:45 am
content: Quote from: scottapotamas on August 17, 2025, 11:14:57 amI see with the symmetrical layout in EMI app note they have a physically smaller cap right on the output close to the IC at pins 9 & 11.I'm guessing based on size that it's not a 10uF cap, definitely not true 10uF. The app note isn't so clear as the designators don't match the photo. (C5 isn't output cap in photo but is on sch)From the schematic I think it's a small 1uF right next to IC and then all the 10uF's after that.I can only assume using a physically smaller cap close/first reduces the size of the loop which helps EMI.It seems to be a tradeoff between having as much capacity as possible right near the IC vs having a smaller physical cap to reduce the loop size between chip and first cap.What cap physical size/capacity did you pick for the first output cap next to pins 11,9 in your design?

author: scottapotamas
author_rank: Regular Contributor
timestamp: August 20, 2025, 06:53:27 am
content: Quote from: Psi on August 20, 2025, 06:22:45 amIt's a 1uF 50V X7R in 1608M (0603). At this package size and ~12V bias you'll end up around ~700nF regardless of value.Pulling some suggestions from my library,C1608X7R1H105K080AB,GRT188R61H225KE13.Remember the layouts in datasheets are only an example and rarely a gold-standard. Sufficient de-rating and margins, good cooling, small loop areas, and minimal trace lengths where possible to reduce stray/parasitic inductance and capacitance.I'll be assembling a new revision of the board that includes this regulator late next week, so when I'm validating it I'll run some quick EMC scans with and without that cap (I wouldn't expect much difference from just that change).Shoot me an email at my username@gmail and I'll send some extra info over that you can compare against.

author: mtwieg
author_rank: Frequent Contributor
timestamp: August 20, 2025, 12:23:48 pm
content: Quote from: Psi on August 18, 2025, 11:47:23 amSimply adding more Cin/Cout isn't always the best fix.Keep in mind that increasing Cout means that the inrush current drawn during soft start will be larger. This will make the UVLO instability more of a problem.In theory, a large enough Cin can prevent the UVLO from tripping during startup. But some back of the envelope math will show that if the UVLO hysteresis is small, then Cin will have to be enormous.For example, right now your UVLO has 0.375V of hysteresis. Let's say your Cout is 70uF. In order to guarantee that the UVLO doesn't trip, Cin needs to provide all the energy to charge Cout to 13.5V (6.4 mJ), while dropping its voltage less than 0.375V. This requires that Cin be at least 1830uF. Seems impractically large. And increasing Cout means Cin would have to increase as well.

author: scottapotamas
author_rank: Regular Contributor
timestamp: August 20, 2025, 02:43:22 pm
content: While I'm somewhat interested in trying to reproduce a failure in the ULVO to harden my own design, I don't believe it's the biggest issue at play given the odd inductor and gate waveforms.@Psi thinking on this a bit, a scope-trace of the 5.2V LDO output might be sensible. If it looks reasonably stable in DC then set your scope to AC coupling and increase vertical scale for more detail.Attached some extracts from my design notes for comparison, compare these relatively clean squarewaves on SW1/SW2 compared to the scope traces in the OP.

author: Psi
author_rank: Super Contributor
timestamp: August 20, 2025, 11:49:49 pm
content: Thanks.Yeah, I will know more once my new chips arrive and I can do more tests with enough input/output capacitance given DC bias losses. Will recheck SW1/2 and see what it looks like after that.I'm not convinced there is any ULVO issue. Input current is max at lowest Vin which is just before ULVO, so that maybe the cause not the ULVO itself. Will know more once i test it again.

author: Psi
author_rank: Super Contributor
timestamp: August 21, 2025, 04:44:45 am
content: For ceramic input/output caps on a DCDC, has anyone heard of any issues when you split the caps between top and bottom layers?Obviously there needs to be a cap on the same layer as the IC right at the pins, but can other caps be split between top & bottom layer?I've not heard of this being an issue in general but just thought I'd ask. No odd current loops between layers that causes any issues?

author: Psi
author_rank: Super Contributor
timestamp: August 24, 2025, 11:43:10 pm
content: So the issue was a combination of- Lack of input capacitance- The ULVO triggering (oscillating)- And most critically, the lab psu (that was powering the circuit) was starting to go into its own current limit while the ULVO LVO was cycling.What techniques are used to prevent damage to a DCDC when the input supply goes into current limit and both the DCDC and the input DCDC start oscillating from each other?Is it something that usually never needs to be addressed as the input supply is always designed to handle the current required without going into current limit?Adding more input capacitance that can smooth out the current limit loop of the input supply sounds like one way.In my application the input supply will be a battery so this isn't actually going to happen, but I'm just interested to know how you protect a DCDC from a current limited input.

author: mtwieg
author_rank: Frequent Contributor
timestamp: August 25, 2025, 12:16:12 pm
content: Quote from: Psi on August 24, 2025, 11:43:10 pmLike I mentioned above, such an issue should not lead to damage in the DCDC:Quote from: mtwieg on August 18, 2025, 11:34:01 amQuoteIt's an issue that comes up fairly often, usually because the designer only thinks about current draw at steady state, not during startup.In an ideal world, all DCDC would use peak current mode control, and the peak current limit on each DCDC stage would be greater than the combined peak current limit of all downstream DCDC stages that it supplies. And all downstream DCDC stages should wait until the upstream DCDC has reached steady state before being enabled. In theory this should always prevent such oscillations from happening, but in the real world doing things this way isn't always feasible/practical.Usually one can find a solution by adjusting soft start times and UVLO thresholds/hysteresis, but there's no general approach to doing so. Depends on the specifics of the pwm controllers being used.

author: Psi
author_rank: Super Contributor
timestamp: August 27, 2025, 12:51:26 am
content: Quote from: mtwieg on August 25, 2025, 12:16:12 pmI did some tweaks to the UVLO and a current-limited input no longer causes squeal and a dead chip.The output just cycles on/off as you would except.Using 220k, 33k with 750pF.So thanks for your recommendation to change UVLO resistors to add more hysteresis to keep it more than the diode Vdrop and under well 1ms soft start time constant.It seems that was the issue.