MCUs with different IO voltages - Page 1
Forum section: electronics / general

author: axemaster
author_rank: Contributor
timestamp: September 25, 2021, 04:08:54 pm
content: Hi all! As I'm sure you all know, it is very common for FPGAs to have IO banks with multiple IO voltages. This makes it easy to interface with 3.3V and 1.8V logics for example.Are there any popular/common MCU families with this feature? It's such a nice thing to have...

author: igendel
author_rank: Frequent Contributor
timestamp: September 25, 2021, 04:36:17 pm
content: The 8-bit AVR DB family has one "Multi Voltage IO" port (the entire port will work with a separate voltage from the rest of the MCU)https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/8-bit-mcus/avr-mcus/avr-db

author: harerod
author_rank: Frequent Contributor
timestamp: September 25, 2021, 06:28:25 pm
content: Igendel, thanks, I wasn't aware of that device family. Interfacing between 3V3 and 5V is usually not a problem, but this device could work as a glue logic for anything between 1V8..5V. If I read the datasheet correctly, there is only up to one 8bit-port with separate VDDIO, though.And the best part: digikey.com actually has those AVR*DB in stock. Under normal circumstances I wouldn't look at any AVR, but the ATtiny0 series, but as long as STM32 are close to unobtanium...

author: JPortici
author_rank: Super Contributor
timestamp: September 25, 2021, 06:41:40 pm
content: Quote from: igendel on September 25, 2021, 04:36:17 pmfinally.

author: errorprone
author_rank: Contributor
timestamp: September 25, 2021, 06:47:44 pm
content: The LPC804M111JDH24 also has this feature. It’s not in every part of the family though.https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc800-cortex-m0-plus-/low-cost-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:LPC80X

author: Doctorandus_P
author_rank: Super Contributor
timestamp: September 26, 2021, 11:43:24 am
content: There have been some microcontrollers that can run from a supply voltage of up to 12V.Atmel once had such a thing in its assortment for the car industry.I once had interest in it because it promised to open power MOSfets better then possible with 5V, but it was such a niche market that quickly decided on a more conventional approach.In the mean time some microcontrollers with significant changes in the I/O pins are coming to the market.A year or so ago I was surprised by the "STSPIN" microcontrollers. These are alsmost a complete motor drive solution on a single chip. Just add power MOSfet's.These chips have:* SMPS built in. Can run form 40V or so, just add an inductor.* MOS-fet Drivers for a 3-phase bridge built into the chip.* Free Opamps, which are meant for shunt resistor voltage amplification.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 26, 2021, 05:37:21 pm
content: It's still relatively uncommon, whereas it could indeed be useful in some cases.A couple notes about that:* Many modern MCUs do have a relatively wide operating range for Vdd - often between 1.8V and 3.6V. That doesn't give you multiple IO banks, but you can certainly use 1.8V logic without any external level shifter. In that case, you still can't mix with 3.3V logic directly, but can still be useful. Just mentioning that because a lot of people don't think about running their MCUs at lower voltages than 3.3V, even when that would make sense! (And the additional benefit is a lower power consumption.)* Also on a growing number of them, you have a separate voltage rail for the core, thus powering IOs at 1.8V doesn't hinder the max frequency at which you can run the core, which OTOH can be the case on some MCUs.* Same for FPGAs, but worth noting: a typical voltage range for IOs of 1.8V to 3.6V is no big problem, but if you wanted anything above the (typical) 4V absolute maximum, that will usually require using different CMOS processes, and be (much) more expensive. So don't expect such devices with a range up to 5V or higher, except niche, expensive ones. "5V-tolerance" is easier - but that just means inputs can take up to 5V, while the IOs are still powered at lower voltages. That's not quite the same, there's no level shifting in this case. Now there's still some MCUs available with a 1.8V to 5.5V voltage range - often 8-bitters or a few entry-level Cortex-M0 ones - but those are usually on "older" CMOS processes that have lower density, so not adapted to more complex and higher speed devices.But apart from the two examples mentioned by some above, I don't have others in mind.You can also typically find this on processors taking DDR/2/3 RAM, which have a separate voltage rail for the RAM interface - but then those are IOs that are reserved for DDR RAM, and not GPIOs. And those aren't MCUs per se - at least I don't know of any "MCU" taking DDR RAM as of yet. Maybe there is? But the families that are often called "crossover" these days still support only SDRAM. AFAIK.

author: axemaster
author_rank: Contributor
timestamp: September 26, 2021, 06:00:16 pm
content: Thanks for all the replies! I'm surprised that this feature isn't more common, especially after looking at the simple implementation on the AVR-DB (thanks harerod!). The MCU market is so competitive, you'd think this would be a good way to differentiate products.HINT HINT - Microchip, if you're reading this thread, can you add this feature to a bunch of your PICs? Please?

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 26, 2021, 06:18:35 pm
content: What would be your typical use?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: September 26, 2021, 06:37:42 pm
content: Quote from: axemaster on September 26, 2021, 06:00:16 pmThis competitive microcontroller market has been inflated to a point that manufacturers make a few controllers, stamp on 100 different part numbers and then sell them at different prices to queeze a few more dimes out of all those "different" variants, and with those dubious methods increase the costs parts management, distribution, and engineers who have to wade through artificially inflated differentiation of parts.I would also not be surprised if the "differentiation" is inflated by making the "big" chips, and then blowing fuses to disable perfectly working peripherals and sell them as "smaller" chips.A big part of this "differentiation" is just a ploy devised by the marketing department. "look, we have 3000 different models, and our competitor only has 200". Yuch!

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 26, 2021, 07:01:58 pm
content: Quote from: Doctorandus_P on September 26, 2021, 06:37:42 pmThat happens when it's cost-effective for the manufacturer, yes.One recent example I ran into was with some FPGA, the Lattice ECP5. Turns out their smallest variant, the -12F, is exactly the same as the -25F. Only the IDCODE is different. The additional slices are not even disabled internally. While they are not accessible if you're using Lattice tools, this is just an artificial limit - the -12F has 25 kLUTS, and all are usable if you're using the Yosys/nextpnr toolchain.For the bigger variants, -45F and -85F, I'm sure those are different, much bigger dies and doing the same with those wouldn't have been cost-effective.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: September 27, 2021, 02:25:14 am
content: Quote from: axemaster on September 25, 2021, 04:08:54 pmNuvoton have what they call Voltage Adjustable Interface (VAI), on a number of their MCUs, on some it specs (1.8V-5.5V)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 27, 2021, 03:25:11 am
content: Microchip MCUs in general (including AVR, ATSAM, PIC..) haven't been too badly hit by stocking issues, mind, not that the quantities have been all that high when they are in -- a couple reels here or there kinda thing.Tim

author: josip
author_rank: Regular Contributor
timestamp: September 27, 2021, 05:33:19 am
content: There also some from TI MSP430 family, for example MSP430F5172.

author: true
author_rank: Frequent Contributor
timestamp: September 30, 2021, 06:15:25 am
content: Also some from Cypress - PSoC5 LP for sure and I think PSoC6 have various VDDIO on banks or sides of the chip, and they can work at voltages different from core input voltage.Some STM8 MCUs have a VDDIO pin, which the datasheet says to tie to VCC, but may allow for different IO voltage from supply voltage. This is likely the entire chip though - no multiple banks. I also haven't tried this yet.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: September 30, 2021, 09:43:47 am
content: On a related, but not useful note: likely many MCUs are built as if to have IO banks; the rub is, if the VCC pins are not all joined internally by direct wiring (by moderate resistance -- hence why they want you to use all of them!) then perhaps there's internal circuitry that would be just totally screwed up if you wired them separately (ala old school power sequencing requirements*). So, you could probably get away with wiring them tovery slightly differentvoltages, including at AC (local bypass for slightly lower noise?). But you won't be going far before the datasheet starts looking at you funny...As far as I can tell, most AGND/PGND arrangements are of this form (connected via die, but enough resistance to be... kinda useful? or else as a Kelvin connection, at least), and probably a lot of AVCC/VREF sorts of pins.*Very specialized things can still require strict sequencing, I think, but most commercial stuff has been greatly simplified in use. So, most MCUs, FPGAs, ASICs. This seems a historical improvement to me, at least; comparing to, say the 8080, which had three supplies that had to be in the right order or something, right? Or, probably some really strict RF or mixed signal parts, or with combination TTL/CMOS/ECL/etc. ports...Tim

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 30, 2021, 05:51:29 pm
content: Some MCUs that have a separate "analog" power rail can use a different voltage than Vdd (on some others, the voltages must be equal within a limited span). But doing this for digital IOs in several banks would require the use of many internal level shifters, which is costly. It also makes it a bit more difficult for the IC layout.Now on MCUs that already have a separate rail for the core, some level shifting must be done already, but having more than one IO bank just adds cost. I guess that except for a few MCUs out there, there just isn't enough demand to warrant the added cost.

author: Siwastaja
author_rank: Super Contributor
timestamp: September 30, 2021, 06:48:37 pm
content: I think it's a chicken-egg problem. This feature would be handy much more often than the MCU marketing/designers think, but because traditionally this has not been offered, end-product designers also have found ways to cope without. And as nobody offers this, there is no competition driving the inclusion of the feature; so we designers end up wasting area and money in numerous level shifters and whatnot, all the freaking time.I mean, maybe excluding simplest and smallest designs using those less than 20 pin controllers, I think some 10-20% of designs would find real beneficial use for this feature. Many many MCU features see much less use than that, yet they are included. Think about a JPEG codec. Who uses that? It's maybe used in 0.01% of the designs done using that chip, yet they decided it's good to have because when it's needed, it's very good to have. Following the same thinking, adding the level shifters to most large pin count devices which have multiple Vdd pins and separate Vcore and some level shifters anyway - would be a great idea, but won't be seen because nobody does that so nobody expects that.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 01, 2021, 12:59:35 am
content: I wouldn't say it's all that common. There are lots of products to support e.g. an entirely 1.8V design, or 2.5, or 3.3.3.3 (or less) to 5V (or more, especially things like 12V+ gate drive or load switches) are the more common cases IMHO. Many of which just aren't reasonable to offer on a single chip (hm, are 5V IOs even compatible with 1.2V core logic? Eh, probably). And anything high current, pretty obviously deserves another chip, due to power dissipation.I haven't seen any MCUs that support JPEG or MPEG, though, I've not seen all that many in general, anyway (~hundreds?). I would assume such features are just outrightcommonin application processors (where graphical accelerators, and multiple CPU cores, are common). The obvious niche that comes to mind is picture frames: a little JPEG decoding, an LCD controller, and not much actual CPU power.Tim

author: Siwastaja
author_rank: Super Contributor
timestamp: October 02, 2021, 02:19:32 pm
content: Most if not all in STM32F7 and H7 series. Which are general purpose microcontrollers and notthatfancy. Large pin counts, separate Vcore, a lot of Vddio pins, and GAZILLION of peripherals never used in 99.9% designs like the JPEG codec mentioned. I'm thinking about such devices, those could very well include the few extra level shifters (or whatever needed - their IO already is completely level shifted from Vcore so I don't know what's the problem) which would increase production cost by $0.001 each yet allow them to brag with yet another nice-to-have feature, much more useful than the broken crypto accelerator no one can use or dare to use.Quarter of their peripherals are untested and broken anyway. Too many features for time-to-market. Different voltage levels would be an "analogue" silicon design thing, very easy to verify it works. It would end up useful, unlike many other features.

author: asmi
author_rank: Super Contributor
timestamp: October 05, 2021, 03:21:34 pm
content: I think it comes down to a silicon-level design. Theoretically all they need to do is to split their internal Vccio power plane into several sections which would be powered by separate pins/balls, but in practice this requires that die contacts are arranged in such a way to make this possible, which might not be the case right now. For example, ST MCUs are famous for their erratic pinouts of peripherals which seemingly defy all common sense, and I suspect this is caused by equally erratic layout of contact spots on a die, as bonding methods also have limitations as to how to bond these to the package balls/pins.

author: Siwastaja
author_rank: Super Contributor
timestamp: October 05, 2021, 04:43:52 pm
content: That's a good point; knowing the ST's pinout apparently designed by hallucinating madmen who broke out of mental institution, if they had separate Vddio domains, likely the domains would be completely mixed up, like Vddio1 on the opposite side to the related IO pins, or ten IO1 domain pins next to each other with one IO2 domain pin in the middle.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 05, 2021, 06:01:57 pm
content: It's not just them though; even ATSAMs are scattered like that. Not quite as bad, but bits and pieces of each port, not like your homely little ATMEGA, but that's only bytes at a time so...Tim

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 05, 2021, 06:26:20 pm
content: There's a small difference between how the pads are laid out on the die and how the pins are laid out on a given package. Particularly when the number of pads becomes pretty large.

author: harerod
author_rank: Frequent Contributor
timestamp: October 05, 2021, 06:31:19 pm
content: What SiliconWizard is saying. Check the same device with different footprints. The IO-arrangement might look way more sensible on a the largest BGA, than on the smallest QFP.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: October 05, 2021, 06:46:48 pm
content: As well as power layout on-chip, I wonder if there may also be issues with power management/powerdown/sleep modes, something that's not so much of an issue with FPGAs and CPLDs.Many non-trivial peripherals have seperate VddIO pins, so in some cases it can be addressed from that end.