10 GHz NCO using Cyclone V - Page 1
Forum section: electronics / general

author: Bigethan
author_rank: Newbie
timestamp: July 01, 2025, 02:18:01 pm
content: Complete novice when it comes to FPGAs so I appreciate any help and I apologize for what I am guessing is going to be a poorly written question!I am trying to implement a IQ demodulator on the Cyclone V (Starting with simulating in Model Sim). I am expecting the carrier frequency of the received signal to be 1GHz, as such I need a 1GHz NCO. The clock frequency on the Cyclone V is 250 MHz which means the max NCO frequency I can generate is 125 MHz. After surfing the web 3 potential solutions for increasing NCO frequency stand out to me.- Parallel NCO- Polyphase filter- External DAC (FPGA board has an ARM chip)I do not known which option is most realistic or if I am missing a more elegant solution. If someone could point me in the right direction I would greatly appreciate it.Last note, I know that the easiest solution is to not use an FPGA but I am doing this as a exercise/learning experience. I want to learn Verilog and thought this would be a fun project! Thanks again!

author: KE5FX
author_rank: Super Contributor
timestamp: July 01, 2025, 07:09:30 pm
content: You may need to subsample. What is the bandwidth of the signal you're trying to recover? That's what actually matters, not the carrier frequency.

author: hamster_nz
author_rank: Super Contributor
timestamp: July 02, 2025, 12:15:58 am
content: Quote from: Bigethan on July 01, 2025, 02:18:01 pmNeither of those three sound feasible to me, based on the limited requirements to generate a "1GHz NCO" (e.g. an NCO that can generate useful I+Q values for 0Hz to 1GHz range).Parallel NCO - Sure, you can generate 4GS/s in parallel with a (say) 200MHz clock - so 20 samples values per cycle, with the required phase offset between each sample value. But I don't think you can leverage it to do anything useful without matching data convertors.Polyphase filter - Often used to change between sample rates, where the natural intermediate sample rate is too high to be realistic. E.g. audio going form 44.1kHz to 48.0kHz. Doesn't seem applicable to what you have described.External DAC -I am not sure what you would do without a ADC or DAC that can handle your desired spectrum.

author: KE5FX
author_rank: Super Contributor
timestamp: July 02, 2025, 03:15:23 am
content: Therearevarious tricks and hacks that can make something like this feasible -- for instance, mixing the incoming signal with a 4-phase NCO at Fs/4, which is just the sequence +1, 0, –1, 0, +1… for the cosine branch and 0, +1, 0, –1, 0… for the sine branch, then passing each mixed stream through a halfband LPF to kick off the downsampling chain.But without more detail we'd have to assume that the OP has an X/Y problem, rather than an I/Q problem.

author: BrianHG
author_rank: Super Contributor
timestamp: July 02, 2025, 01:56:42 pm
content: Without knowing the OP's bandwidth and modulation type, we cannot offer any sound advice.For example, if his source is nothing more than a received FM encoded signal with only a ~25MHz bandwidth, passing a cleaned up 1bit sampled version of the signal directly into a CycloneV's LVDS serial input clocked at 3GSPS, with your core logic running at a fixed 1/16 frequency, 187.5MHz core clock, you can create a reasonably functional receiver. Though with today's digital RF front-end ICs, it is not the current go-to strategy. I'm just saying you can get something like this to work with grit and effort.The same can be done in reverse, however, you would need a quality 1GHz 25MHz bandpass filter on LVDS TX output pin to generate a sine wave output ready to be amplified for over the air broadcast.

author: ejeffrey
author_rank: Super Contributor
timestamp: July 02, 2025, 06:53:15 pm
content: Parallel NCOs is a totally reasonable approach. I've done exactly this to make a ~350 MHz NCO of IQ demodulation with an Arria V. We used a 1 GSPS sample rate and a 250 MHz core frequency, so 4 interleaved samples per clock cycle.The problem will be getting the data into the FPGA. In my case the Arria V has 1 GB/s capable LVDS pins with built in serdes, and uses a parallel LVDS ADC. In your case you will run into the problem that few if any ADCs can support the sampling rate you want with a parallel interface and the cyclone V doesn't have the high speed transceivers you would need for jesd204b.