How to implement bus transceivers on 486 bus (SIS85C471)  - Page 1
Forum section: electronics / general

author: Haz
author_rank: Newbie
timestamp: November 04, 2021, 09:43:40 pm
content: Hello,I wonder if anyone can help me? I'm trying to essentially build an 486 SBC computer using the SIS85C471 chipset. The computer will interface through a 16 bit ISA interface and will have the bare minimum of components for it to work. The video, sound, serial and IDE drive connections will be from pre-existing ISA cards.I think I'm off to a good start, however I'm having some confusion on how to implement the bus transceivers (74245) I think I've correctly connected the ones for the SD0 bus and XD0 bus from the datasheet and block diagram. It doesn't give much information or an application note on how they should be connected.There is also some transceivers for the address bus but I can find no mention in the datasheet on how these should be connected, no enable and dir pins for the 74245 like there is for the data bus. My best guess that these signals must connect to the processor.This is the part of the datasheet that mentions the control and enable signals for the 74245 transceiver and block diagram.https://drive.google.com/file/d/1wSpw27KvH5ryM-jGVGrVCXmC1PwGFVRY/view?usp=sharingThis is my quite crude eagle schematic:ttps://drive.google.com/file/d/1wZNo4Xg030tFSLRfSUH1UflCNyjBYJ-U/view?usp=sharingLink to the full SIS85C471 datasheet.https://www.datasheets360.com/pdf/805338928285727440Many thanks for any help

author: Benta
author_rank: Super Contributor
timestamp: November 04, 2021, 11:02:03 pm
content: Using Google Drive for your schematics is not very smart.

author: RomDump
author_rank: Regular Contributor
timestamp: November 05, 2021, 03:24:16 am
content: Quote from: Haz on November 04, 2021, 09:43:40 pmI did a quick google search and similar question was already asked on reddit.The following link has a schematic of Motherboard on the last few pages using the SIS85C471.https://docs.rs-online.com/1d5c/0900766b80028943.pdf

author: x86guru
author_rank: Regular Contributor
timestamp: December 09, 2021, 05:41:46 pm
content: I'm unable to view your schematics but one of the great features of the 486's external bus is the addition of the bs8# pin. If you assert the bs8# pin on the 486, the external data bus becomes only 8-bits wide and the 486 internally converts all I/O to 8-bits and internally steers the byte enables. When bs8# is asserted, you can mux the 32-bit wide data bus using four 74245's that are selected based on the byte-enable lines. I built a wire-wrapped 486dx2 SBC (DX2 because it allows for a lower external frequency) back in the 90's for fun when I found out about the bs8# pin. It reduces the amount of glue logic to the bare minimum.

author: TomS_
author_rank: Frequent Contributor
timestamp: December 09, 2021, 06:22:47 pm
content: For the address buffers, could it be the AEN signal (page 55)?It seems the chipset includes a DMA controller, and the AEN signal goes high when the DMA controller is the master and low otherwise (if I am interpreting the datasheet correctly). If that is the case, the AEN signal could be connected to the OE/ pin of the address buffers to put them into high impedance mode when the DMA controller will be driving the address bus.It could be worth getting a motherboard with the same chipset on it, then you can buzz out the signals and see what a manufacturer has done. Theyve likely had a lot of behind the scenes support directly from the chipset manufacturer for queries just like this one, so it would be a good reference platform.For the SD and XD busses, my interpretation of the BDIR and SDIR signals also mentioned on page 55 is as follows:BDIR when high connects D15..8 on pins 2-9 to SD on pins 11-18 and D7..0 on pins 2-9 to XD on pins 11-18BDIR when low connects SD on pins 11-18 to D15..8 on pins 2-9 and XD on pins 11-18 to D7..0 on pins 2-9SDIR when high connects XD on pins 2-9 to SD on pins 11-18SDIR when low connects SD on pins 11-18 to XD on pins 2-9The way I remember how 74x245's work is that when the DIR signal is low, the signals travel from the higher pins to the lower pins, and vice versa.The datasheet is a bit terse, so it is leaving a lot of room for interpretation and guesstimating what exactly to do.