Simplest / Cheapest FPGA for bulk SPI to USB - Page 1
Forum section: electronics / general

author: Rerouter
author_rank: Super Contributor
timestamp: August 17, 2020, 08:29:31 am
content: Hello, a project I am working on needs to shunt 4x 20MHz SPI buses from ADC's in, and 1x 20MHz DAC SPI bus out via USB, I really do not need any fancy processing in the FPGA, just a nice way to interface it, Any recommendations?Sadly the end point devices cannot operate faster than 20MHz, the ADC data would be a block of 64x24 bit readings, and the DAC data would be 24x16 bit outputs, all SPI interfaces would be about 70% utilization.

author: Ice-Tea
author_rank: Super Contributor
timestamp: August 17, 2020, 08:54:51 am
content: What's your target? One-off proof of concept? Production run? Of how many pieces? Something off the shelf? Will you design your own board?

author: Rerouter
author_rank: Super Contributor
timestamp: August 17, 2020, 08:56:21 am
content: one off / less than 15 units, hand assembled (am quite good at SMD, prefer not to play with BGA), and yes I am designing the PCB

author: Berni
author_rank: Super Contributor
timestamp: August 17, 2020, 09:14:46 am
content: Just pick the biggest FPGA that you can get for a low price from whatever vendors tools you know the most(Altera Xilinx Lattice..) and use a FTDI parallel to USB chip to get the data out. Plenty are available in soldering friendly TQFP or QFN packages.When you don't need any special features like high speed DDR IO or serdes or need some special IP then pretty much any FPGA will work. Tho you may want to go for the more integrated kinds that only need 1 or 2 supply rails and have internal flash.

author: BrianHG
author_rank: Super Contributor
timestamp: August 18, 2020, 02:46:53 am
content: If you do not want to deal with multiple supply voltages or a bootprom, take a look at Intel's Max10 series, basically an all in 1 chip solution, single 3.3v supply with a programming port, (it has a built in PLL and you still want an FTDI 480mb USB-parallel interface for development simplicity sake):https://www.digikey.com/products/en/integrated-circuits-ics/embedded-fpgas-field-programmable-gate-array/696?FV=-8%7C696&quantity=0&ColumnSort=1000011&page=1&stock=1&nstock=1&k=max10&pageSize=100&pkeyword=max10(Careful, some are low voltage variants.)Also, you will need to look at FTDI's throughput latency handshaking response to see how much on-chip cache you might need to keep a perfectly smooth stream running if it is one of your requirements.

author: NiHaoMike
author_rank: Super Contributor
timestamp: August 22, 2020, 06:51:22 pm
content: ICE40 + Cypress FX2.

author: NorthGuy
author_rank: Super Contributor
timestamp: August 22, 2020, 07:44:07 pm
content: It's only 100 Mb/s traffic. You should be able to do this with an MCU with HS USB module. You only need to find one with 5 SPI modules. You might be able to find one in $3-5 range. This is certainly cheaper than FPGA. Otherwise, practically any FPGA will do.

author: Rerouter
author_rank: Super Contributor
timestamp: August 22, 2020, 10:35:01 pm
content: Currently leaning towards a FT600q and a lattice Machx02, but if you can recommend such a micro I'm all ears, STM32 my first though seems to have so many subtle hardware bugs that the SPI cannot be relied onThe FT600q is overkill, but it also does not have as long FIFO timeouts as the USB2.0 tranceivers, e.g. the HS modules tend to need a full 4K transfer to send to the host, while this one will send immediatly,

author: EverydayMuffin
author_rank: Regular Contributor
timestamp: August 22, 2020, 11:07:09 pm
content: The cheapest FPGA would probably be GOWIN's GW1NS-2. This FPGA has an internal ADC and USB 2.0 PHY, it also has the option of an Arm Cortex-M3 (similar architecture to Microchip SmartFusion2).

author: BrianHG
author_rank: Super Contributor
timestamp: August 23, 2020, 01:07:15 am
content: Quote from: Rerouter on August 22, 2020, 10:35:01 pmNot true. At least with the work my app developer has done with FTDI. You can set a 'Latency' timeout timer in FTDI's drivers when opening the port and withing that refresh cycle, even if the buffer is partially full, you will receive the current size contents of that buffer.This may be different in newer drivers, however, the feature has been there since the mid 2000's.Even in their USB-RS232 modules, they have the feature in 2 places. Either in the control panel, see here:https://www.eevblog.com/forum/fpga/verilog-rs232-uart-and-rs232-debugger-source-code-and-educational-tutorial/msg2801424/#msg2801424With the default setting of 16, you either need to fill FTDI's 4K receive buffer before your app even knows that a single character was sent, or, once sending a few characters, you need to wait that 16ms before your app would know only a few characters were sent.The other way is a parameter built into FTDI's drivers when you directly interface with their hardware.

author: brucehoult
author_rank: Super Contributor
timestamp: August 23, 2020, 02:05:27 am
content: 5 SPI and one USB seems well within what many Cortex M4 microcontrollers can handle.

author: Bassman59
author_rank: Super Contributor
timestamp: August 23, 2020, 05:15:04 am
content: Quote from: NorthGuy on August 22, 2020, 07:44:07 pmNXP LPC55S28 should be able to do this.

author: Rerouter
author_rank: Super Contributor
timestamp: August 23, 2020, 10:14:20 am
content: I think the micros get ruled out by generally only having 2 DMA channels, I cannot run the SPI buses any faster, which leaves me feeling I would be left juggling grabbing bytes,E.g. the NXP chip has a 16 bit x 8 entry fifo that I would need to keep cleared, when I have 24x10 bits coming in, and 24x8 going out.

author: up8051
author_rank: Frequent Contributor
timestamp: August 23, 2020, 10:10:52 pm
content: LPC55S28 have to DMA blocks: DMA0 with 23 channels and DMA1 with 10 channels.Each SPI (Flexcomm) have own DMA channel.