PCB Manufacturing Control of Differential Pair - No Shield - Page 1
Forum section: electronics / general

author: tarun172
author_rank: Regular Contributor
timestamp: February 05, 2024, 07:24:55 pm
content: Hi everyone,I am collaborating with a PCB fabricator on a project involving a differential pair design using an unshielded RJ45 connector. The PCB fabricator has expressed uncertainty about controlling impedance without a shield ground.The key question is: How can the PCB fabricator effectively control the impedance of the differential pair during the PCB fabrication process?Thanks,Tarun S

author: ajb
author_rank: Super Contributor
timestamp: February 06, 2024, 06:09:01 pm
content: I don't know why the fabricator would be concerned about an unshielded connector since that's not part of what they're fabricating. Are they perhaps referring totracksthat lead to the connector not having a ground plane below? That would make more sense, as differential impedance is related to single-ended impedance.

author: tarun172
author_rank: Regular Contributor
timestamp: February 06, 2024, 09:22:20 pm
content: Thank @ajb. I agree. I will ask them for clarification.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 06, 2024, 10:06:16 pm
content: If I may read into this connector... it's just Ethernet, right? If it's 100/1G, the baud rate is a bit over a hundred MHz, permissible mismatch length is HUGE, 10s of cm -- just don't worry about it.Or, to put it another way: you think that poor connector is any kind of impedance controlled? Or the plug or sockets along the way? Have you looked at those junction boxes before?Not that existing errors are excuse to introduce more, of course -- but it really is a very tolerant standard and not one you need to worry about. Keeping mismatch lengths short is more than good enough.Anything you would need controlled impedance for, will also have a ground plane, and shielded impedance-controlled connectors, as they will be high bitrate (Gbps) and low level (e.g. PCIe interfaces typically running from 1.2V supplies). You can't meaningfully run such a standard over UTP because ambient noise knocks it out, let alone ESD frying the interface; mechanical solutions to both (pins surrounded by shield, hid away from errant zappy fingers) are the way to go.Tim

author: tooki
author_rank: Super Contributor
timestamp: February 09, 2024, 05:51:13 pm
content: Let me answer your questions in reverse, since I suspect the second question may not actually be what you want to know.Quote from: tarun172 on February 05, 2024, 07:24:55 pmFor impedance-critical boards, the fabricator will:a) calculate and provide you with the trace geometry to useb) use superior PCB material with more accurately controlled dielectricsc) control the etching process extra-carefully (since etch time will affect the final trace and gap widths, as well as the actual shape of the trace’s cross-section)d) add test swatches to each panel, containing controlled-impedance test traces, and will then measure their impedance and provide a test certificate. If your contract with them contains contractually binding impedance targets, these swatches serve as the control that it actually meets them.With that said, I concur that gigabit Ethernet doesn’t have requirements anywhere near stringent enough to require those services. (I’ve never ordered such a board myself, but my old boss did, so I got to see the process.)Quote from: tarun172 on February 05, 2024, 07:24:55 pmJust to rule out the most obvious:1. did you calculate your controlled-impedance trace geometry using the actual specs of the board the PCB fabricator will use? The default layer stacks in many EDA packages don’t correspond to anything in particular. This is especially critical for boards with 4 or more layers, because there are huge differences in layer stackups, thanks to the huge variation in core thicknesses to choose from, which in turn means huge variation in the thickness of the prepreg between your signal layer and ground plane, which fundamentally defines your controlled-impedance trace geometry.2. What kind of controlled-impedance traces are you using? Ground plane below? Ground fill on the signal layer?