A fairly simple 8051-based SBC project. - Page 1
Forum section: electronics / general

author: technix
author_rank: Super Contributor
timestamp: December 03, 2016, 10:47:03 pm
content: Here is the features I shot for on this project:* 8051-compatible processor: AT89C51RC @ 24MHz* Von Neumann connected system bus* 32kB EEPROM, 32kB SRAM (0x0000 - 0x7fff = AT28C256, 0x8000 - 0xffff = IS61C256)* PIC16F1455 for USB virtual serial port and system control (including reset)* Serial 128x64 graphic display (ST7920 controller, contains built-in character generator)* PS/2 interface for keyboard* DS1307 RTC* Buzzer* Fully through hole construction* Board size identical to the LCD display moduleHow do you guys think?I found PIC16F1455. Here is the (almost) complete BOM:* 1x AT89C51RC-24PU* 1x SN74HC00N* 1x SN74HC573N* 1x IS61C256AH-15N* 1x AT28C256-15PC* 1x PIC16F1455-I/P* 1x DS1307N* 1x ST7920-based LCD module* 1x USB Mini-B connector* 1x PS/2 connector* 2x 22resistors* 2x 4.7kresistors* 7x 220nF MLCC* 2x 22nF ceramic disk capacitor* 1x 16MHz HC-49/S crystal (12MHz will work too, with different fuse settings in the PIC though)* 1x 32768Hz warch crystal* 1x buzzer* 1x SS9015 PNP BJT* 1x 2N7000 NMOSFETThe PIC16F1455 generates the 24MHz clock for 8051 from its internal 48MHz clock, provides USB CDC, and handles switching the 8051 between internal ROM and external ROM booting.

author: ChristofferB
author_rank: Frequent Contributor
timestamp: December 03, 2016, 11:48:23 pm
content: Sounds interesting! What code is it going to run? Something BASIC-y?

author: technix
author_rank: Super Contributor
timestamp: December 04, 2016, 08:30:35 am
content: Quote from: ChristofferB on December 03, 2016, 11:48:23 pmI have not figured out what code I should make it run yet. The wiring along with the 32kB internal ROM in the chip allows me to go both ways. My original plan was to run native code only, using the internal ROM as a bootloader, and store actual application code in the external EEPROM. If I ended up running BASIC, the interpreter and OS will have to sit in the internal ROM while the external ROM is used as a filesystem of sorts.

author: JPortici
author_rank: Super Contributor
timestamp: December 04, 2016, 10:26:03 am
content: Quotewhy? are you planning to do tens of thousands of units? still, usually microchip's lead time is less than 10 weeks

author: technix
author_rank: Super Contributor
timestamp: December 04, 2016, 11:22:56 am
content: Quote from: JPortici on December 04, 2016, 10:26:03 amI can't find them in local electronic component stores.

author: JPortici
author_rank: Super Contributor
timestamp: December 04, 2016, 12:18:22 pm
content: fair enough, though i bet ebay or microchip sample program can be of helpstill, microchip direct has ton of them and (at least here) 10€ shipping

author: stfsux
author_rank: Contributor
timestamp: December 04, 2016, 12:43:34 pm
content: Quote from: technix on December 03, 2016, 10:47:03 pmI'm not sure to understand.i8051 is normally a modified harvard architecture, or are you talking about something else?

author: Kalvin
author_rank: Super Contributor
timestamp: December 04, 2016, 03:51:09 pm
content: Quote from: technix on December 03, 2016, 10:47:03 pmIf you just want a USB serial port, why don't you use those cheap FTDI or similar USB-to-serial modules available on eBay for $1.30? Typically those modules have DTR-signal which can be used for the reset purposes.

author: technix
author_rank: Super Contributor
timestamp: December 04, 2016, 04:40:56 pm
content: Quote from: Kalvin on December 04, 2016, 03:51:09 pm8051 needs external active-high POR which should be present regardless of the prescence of a USB host, and this chip generates that signal. It also generates the signal intended for the EA pin if I decided to store native code on the EEPROM and use the onboard ROM as a bootloader. I don't think that a simple USB to serial chip can do all those. In fact the USB interface will have to be a bit more complicated for that.

author: jesuscf
author_rank: Frequent Contributor
timestamp: December 04, 2016, 05:38:37 pm
content: Either the AT89LP51RD2 or the AT89LP51ED2 are a much better option than the AT89C51RC. They both come with 64k of ISP Flash and 2k of RAM. The ED2 comes with 4k of EEPROM as well. On top of that you'll get a built-in serial boot loader, a one clock per cycle CPU, and a sometimes usable 10-bit ADC.

author: technix
author_rank: Super Contributor
timestamp: December 04, 2016, 09:30:04 pm
content: Quote from: jesuscf on December 04, 2016, 05:38:37 pmI cannot source them (similar situation as PIC16F1455 - in fact AT89LP series faces extremely harsh competition from STC equivalents that is much cheaper, so they are even more expensive to find and nigh impossible to find.)And this design being a dual purpose (running BASIC using interpreter in internal Flash, or running native code directly off the external EEPROM) means the processor must be able to be forced external code and data memory in Von Neumann bus.

author: westfw
author_rank: Super Contributor
timestamp: December 05, 2016, 03:40:33 am
content: QuotePresumably he means that he's setting up the bus so that external RAM and external Program space share the same bus. (that probably means that a chip with 64k internal memory is "undesirable", because you'd want to have the flexibility of putting some code in the external memory. Or do the 64k versions have a provision for turning off internal flash in pieces?)

author: ebclr
author_rank: Super Contributor
timestamp: December 05, 2016, 06:36:30 am
content: I don't know why you want to do this board, it's hard to understandI would suggest buy this one and you your time for some other stuff like firmwarehttps://world.taobao.com/item/37792947308.htm?spm=a312a.7700714.0.0.fRMBBX#detail

author: technix
author_rank: Super Contributor
timestamp: December 05, 2016, 11:24:55 am
content: Quote from: ebclr on December 05, 2016, 06:36:30 amDo that thing get any chance to run BASIC? Does that board also serve as a teaching tool for students learning computer consistency?

author: stfsux
author_rank: Contributor
timestamp: December 05, 2016, 12:02:10 pm
content: @westfw oh yeah ok. nvm

author: ebclr
author_rank: Super Contributor
timestamp: December 06, 2016, 06:30:44 am
content: For sure, and better than 89C51, that board is only a cheaper, smaller and faster 89C51 also less power from supply

author: technix
author_rank: Super Contributor
timestamp: December 06, 2016, 06:34:27 am
content: Quote from: ebclr on December 06, 2016, 06:30:44 amIhavethat exact chip. And no it does not work in this design. STC chips does not have the required EA pin.

author: ebclr
author_rank: Super Contributor
timestamp: December 06, 2016, 11:39:24 am
content: Chip is not STCIs silabsWhy external memory, if all memory address are filled up internally

author: technix
author_rank: Super Contributor
timestamp: December 06, 2016, 01:23:23 pm
content: Quote from: ebclr on December 06, 2016, 11:39:24 amCan I fill the data into the external memory, and immediately jump into it? I am using a Von Neumann external bus.

author: ebclr
author_rank: Super Contributor
timestamp: December 06, 2016, 01:34:45 pm
content: I put the wrong linkthe correct ishttps://world.tmall.com/item/12500559730.htm?spm=a312a.7700714.0.0.D7Zo2CYes you can access external memory (http://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F32x.pdf)12.1. Accessing User XRAMXRAM can be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or usingMOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as@R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register(EMI0CN as shown in Figure 12.1). Note: the MOVX instruction is also used for writes to the Flashmemory. See Section “11. Flash Memory” on page 106 for details. The MOVX instruction accesses XRAMby default.For any of the addressing modes the upper 5 bits of the 16-bit external data memory address word are"don't cares". As a result, the 2048-byte RAM is mapped modulo style over the entire 64k external datamemory address range. For example, the XRAM byte at address 0x0000 is also at address 0x0800,0x1000, 0x1800, 0x2000, etc.Important Note: The upper 1k of the 2k XRAM functions as USB FIFO space. See Section 12.2 fordetails on accessing this memory space.

author: ebclr
author_rank: Super Contributor
timestamp: December 06, 2016, 01:37:51 pm
content: If this will be used for educational purposes , i would sugest take a look herehttp://www.edsim51.com/

author: technix
author_rank: Super Contributor
timestamp: December 06, 2016, 03:47:19 pm
content: Quote from: ebclr on December 06, 2016, 01:34:45 pmWhat I mean is 1) reading and writing code memory on the fly and 2) execute code that is just written.

author: Bruce Abbott
author_rank: Frequent Contributor
timestamp: December 06, 2016, 05:51:59 pm
content: Quote from: technix on December 06, 2016, 03:47:19 pmYou can do this if you make the external RAM respond to both program and data memory requests. /PSEN goes low to indicate reading external program memory, while /RD or /WR goes low when accessing external data memory. RAM /CE (and /OE) could be generated by combining /PSEN, /RD, and /WR with a 3 input AND gate.On the AT89C51RC, connecting /AE to +5V maps the lower 32k of program memory to internal Flash and the upper 32k to external ROM. So you could have 32k of operating system in internal Flash, and 32k of external RAM for user programs and data.

author: technix
author_rank: Super Contributor
timestamp: December 06, 2016, 07:38:37 pm
content: Quote from: Bruce Abbott on December 06, 2016, 05:51:59 pmI have 32k SRAM (0x8000 - 0xffff) and 32k EEPROM (0x0000 - 0x7fff,) making full 64k external memory, so slightly different wiring:/OE = /PSEN * /RD/WE = /WR/CS(EEPROM) = A15/CS(RAM) = /A15So, all those is going through one 74HC00.

author: technix
author_rank: Super Contributor
timestamp: December 08, 2016, 09:13:14 am
content: Now I got a breadboard prototype up, how do I implement a boot loader and a BASIC interpreter then?Do you guys consider this a good idea, instead of implementing the interpreter in 8051 directly, implement a byte code virtual machine in the onboard ROM, and create a BASIC compiler (or LLVM backend if I want C and C++) targeting this byte code for PC.

author: westfw
author_rank: Super Contributor
timestamp: December 08, 2016, 10:33:27 am
content: QuoteReally? Usually one gets the Intel BASIC52 firmware and adapts that. It's all over the net, in various forms. Here's one:http://home.arcor.de/h.boehling/80c32.htm#MCS-BASIC-52It's a real (from text) interpreter, complete with floating point, and I assume that it's REALLY slow on stock 8051, but it's essentially THE defacto standard for the 8051 world. Or was, back when there weren't very many other choices.http://www.nomad.ee/nomad/micros/bas52man/index.shtmlPJRC (now of "Arduino Teensy" fame) used to do 8051 stuff:http://pjrc.com/tech/8051/I've never gotten close enough to implementing anything that I've looked into finding an updated version for the newer chips, or into how much effort might be required to get the source code working on a non-Intel 8052-like chip. IIRC, the big claim to fame was that once you had an 8052 with BASIC-52 in it's on-chip program memory (either by programming it yourself, or by buying an 8052BASIC chip), you could write BASIC into RAM and/or save the text in an external EPROM and run your home automation software on it (that was the killer-app. Steven Ciarcia (more recently of Circuit Cellar Magazine) was a big proponent, and sold 8052BASIC chips via his MicroMint company.AFAIK, hobbyist use of 8051 systems dropped off rather rapidly after PCs capable of running a cross-compiler became common, and relatively-easily programmed flash/eeprom microcontrollers (PIC, AVR, 68HC11) show up.(It's hard to recall that PCs used to be so expensive that buying an 8051 SBC for $300 and using an old ASR33 or "dumb CRT terminal" to program it was the preferred "embedded solution"...)

author: legacy
author_rank: Super Contributor
timestamp: December 08, 2016, 09:26:39 pm
content: yes, I got a few '51 assembly example of the basic interpreter from Dr.Dobb'sand it was super fast

author: technix
author_rank: Super Contributor
timestamp: December 09, 2016, 03:43:11 am
content: Quote from: westfw on December 08, 2016, 10:33:27 amThat is a full featured product, but it won't work very well for me, as I need to squeeze in native code boot and EEPROM in system programming support.I will probably use a byte code VM as it can be a full C implementation with all those features and Von Neumann bus in mind.

author: westfw
author_rank: Super Contributor
timestamp: December 09, 2016, 03:58:33 am
content: BTW. Quick and approximatecheat sheet, especially for people who might be reading this thread that are less familiar with the history:8051: Usually the label for the Architecture. Aka "MCS-51"Also, an Intel chip with 4k internal ROM and 128 bytes RAM.8052: Chip with 8k internal ROM and 256 bytes RAM.8031, 8032: like 51/52, only no internal ROM. Could only be used in "external program memory" configurations. pre-programmed 8052/etc would appear on the surplus markets as "8032", since the same wiring for external program memory would simply bypass any internal program memory that happened to exist.80C52/etc: Like 8051, only CMOS instead of NMOS - lower power!87C52/etc: Like 8052/etc, only with internal EPROM (UV-erasable) rather than ROM. Usually ceramic package with quartz window for UV-erasure. (Later, plastic with no window for One-time programming (OTP))89C52: like 87C52, but with FLASH internal program memory. (Atmel part number)89C2051: low pin count (20pin) variant with 2k Flash and 128bytes RAM (Atmel.)89S52: like 89C52, but with In-circuit Serial Programming. Devices earlier than this required complex HV parallel programming. (Atmel part number)Sometime around then everyone started shipping 8051 clones (when Intel lost interest? When they opened up the IP? I dunno.) Different vendors used different part number schemes to indicate different features/memorysize/memory technology. On some, the numbers tell the story. Others, alphabetic suffixes are more relevant...The original architecture uses as least 12 clock cycles for each instruction. Intel implemented a faster version (MCS-151) that did 2 clocks, and I think since then many vendors have done single-clock versions without being explicit via part numbering. (This is "clock cycles per machine cycle", some instructions require more than one machine cycle.) (This has some substantial impact on external program memory and such...) (There's some microcontroller history in here somewhere. 8bit PICs are widely sneered at these days for using 4 clocks/machine cycle. But when they were first introduced, that was pretty uncommon...)There was a follow-on MCS-251 architecture introduced by Intel, but it didn't go very far. (IIRC, Intel exited the microcontroller business shortly after introducing the architecture, and may have been fussier about licensing. And by then, there were a lot more competing microcontroller architectures.)

author: westfw
author_rank: Super Contributor
timestamp: December 09, 2016, 04:01:45 am
content: QuoteThe full basic interpreter fit in 8k. There should be plenty of room in a modern implementation for that PLUS any additional code you need, PLUS the code to have them interoperate.I think paul's page also had pointers to a "tiny basic" for 8051.

author: legacy
author_rank: Super Contributor
timestamp: December 09, 2016, 01:05:10 pm
content: (if anyone needs the original intel 51-basic,PM me for the binary, 8Kbyte size)

author: technix
author_rank: Super Contributor
timestamp: December 09, 2016, 03:19:10 pm
content: Quote from: westfw on December 09, 2016, 04:01:45 amWill they play nice with my Von Neumann bus unmodified? XDATA and CODE memory goes to the same place, 0x0000 - 0x7fff is non volatile while 0x8000 - 0xffff is volatile, and I also have to allow for dual booting so BASIC program does not start at EEPROM address 0x0000.My byte code virtual machine is a Von Neumann RISC instruction set with always-aligned 16-bit instructions and botf 0x0000 and 0xffff being nop. This mean using this byte code I can easily tell if it is byte code or 8051 native code in the ROM, since the first four bytes of a 8051 program will almost never be all 0x00 or 0xff. The byte code interpreter will always refuse to boot any ROM content not starting with two nops in its own instruction set, allowing the system controller (PIC16F1455) to detect this scenario and reboot the 8051 from external bus.

author: legacy
author_rank: Super Contributor
timestamp: December 09, 2016, 03:51:30 pm
content: dealing with NV-RAM(1) is not a good ideamy 68hc11 board bootstraps from the NVRAMwhich is also used for the stack and data sessionssometimes gets corruptedalso, the battery doesn't last 10 years.I am using fe-RAM instead of NV-RAM.(1) static ram + battery, Dalsemi/Maxim technology

author: technix
author_rank: Super Contributor
timestamp: December 09, 2016, 05:01:52 pm
content: Quote from: legacy on December 09, 2016, 03:51:30 pmI am using EEPROM and FRAM as the nonvolatile RAM technology. (FM18W08 on SOP-28 adapter board is a drop-in replacement for AT28C256 anyway)