Flip flop clocking issue - Page 1
Forum section: electronics / projects

author: Digibin
author_rank: Regular Contributor
timestamp: July 14, 2016, 07:45:36 am
content: I designed a board recently with an array of LEDs that switch between two display states, and I had an issue that I have worked around but don't really understand. A momentary action pushbutton clocks (pulses high) a D type flip flop with the inverted output tied back to the data input, so it just toggles the output on each clock rising edge. The pushbutton input is debounced with 10k series resistance and 10nF capacitance to ground. The problem was that the flip flop was clocking on both edges, i.e. when pushing in the button (rising edge) and also when releasing (falling edge). It's only supposed to clock on the rising edge. I removed the debouncing cap and it stopped clocking on the falling edge, so clearly it doesn't like the slow RC discharge 'edge' of the clock input. Fortunately the switch didn't need much debouncing so I just left the cap off, leaving only the 10k series resistance. But I don't know what was causing the problem. There's no mention of a maximum clock edge duration in the datasheet or a minimum clocking frequency. The input voltage thresholds suggest there is some hysteresis which should prevent noise or interference on the clock line from triggering the clock input as the RC discharges past the voltage threshold. If this was the case I'd also expect the output to toggle a number of times before settling down as the clock voltage passed over the threshold - this wasn't the case as it was reliably toggling only once on each edge. In hindsight a Schmitt trigger on the clock line would have been a good idea, but I didn't think I'd need it.So, what's the problem?Schematic attached, flip flop datasheethere.

author: Kjelt
author_rank: Super Contributor
timestamp: July 14, 2016, 07:59:01 am
content: Should work, only thing messing it up is the pushbutton IMO, so you do need to debounce it.Datasheet specs around max 10MHz so 100ns minimum clockpulse on the clock so make sure you debounce it appropriately, 10nF is a bit small.Test it with a frequency generator at 1kHz, that is a clean stable pulse and you can check if you didn't make a wiring error. BTW did you safely terminate the other flipflop in the package (all its inputs should be tied to gnd or vcc).

author: Kjelt
author_rank: Super Contributor
timestamp: July 14, 2016, 08:06:48 am
content: BTW: place the debounce C as close as possible near the flipflop clock input, you don't want long traces or wires to pick up noise.

author: Alex Nikitin
author_rank: Super Contributor
timestamp: July 14, 2016, 08:20:46 am
content: Quote from: Digibin on July 14, 2016, 07:45:36 amActually, there is - 15us for 5V supply, 5us for 10V supply.CheersAlexP.S. - if the second flip-flop in the package is free, I would build a monostable on it for debouncing the switch.

author: Digibin
author_rank: Regular Contributor
timestamp: July 14, 2016, 08:44:26 am
content: Quote from: Kjelt on July 14, 2016, 07:59:01 amI've already built the board. Initially I had designed for 10uF debounce cap, which didn't work correctly, so I reduced it to 10nF and it continued to behave in the same way. It only behaved correctly when I removed the cap altogether. I did check it with a pulse train and it worked correctly and that's when I tried removing the cap to get sharper edges. The inputs of the other flip flop are grounded and the outputs are left open.Quote from: Alex Nikitin on July 14, 2016, 08:20:46 amYou're right! Somehow I didn't see that. So out of interest why would a device like this have a maximum clock edge duration, i.e. what part of the internal circuitry requires a minimum edge speed?

author: Someone
author_rank: Super Contributor
timestamp: July 14, 2016, 09:16:02 am
content: Quote from: Digibin on July 14, 2016, 08:44:26 amMetastability of the gates.

author: tggzzz
author_rank: Super Contributor
timestamp: July 14, 2016, 11:00:52 am
content: Quote from: Someone on July 14, 2016, 09:16:02 amNot metastability; that's an entirely different phenomenon.The problem is noise, either thermal, EMI/EMC, or digital, or any combination thereof.Make sure you understand why schmitt trigger inputs exist.

author: Digibin
author_rank: Regular Contributor
timestamp: July 14, 2016, 04:05:10 pm
content: Quote from: tggzzz on July 14, 2016, 11:00:52 amIf it were noise causing false triggering then you'd expect to see the output toggling a number of times before settling down, but it doesn't. The flip flop doesn't have a single voltage threshold - it has a positive going threshold and a negative going threshold. So a Schmitt trigger isn't needed and noise shouldn't be causing false clocking.

author: tggzzz
author_rank: Super Contributor
timestamp: July 14, 2016, 05:14:11 pm
content: Quote from: Digibin on July 14, 2016, 04:05:10 pmSigh. I suspect you don't know the characteristics of a schmitt trigger input. I suspect you don't even realise that, unless you are dealing with photon counting or femtoamp applications, all circuits are actually analogue.With noise the transitions are not monotonic, and that can lead to a positive transition on a negative-going edge. Consider a transition voltage of 0.5V, and a negative transition of 1, 1.1, 0.9, 1, 0.8, 0.9, 0.7, 0.8, 0.7, 0.6,0.4, 0.5, 0.6, 0.4, 0.3, 0.4, 0.2, 0.0, 0.1.Ensure you have also calculated the effect of the inductance in the two power leads, and crosstalk between adjacent wires.

author: basinstreetdesign
author_rank: Frequent Contributor
timestamp: July 14, 2016, 08:25:20 pm
content: Yep, noise is the culprit. Even the humble 4013 CMOS flop will trigger many times on the tiny noise content of a slowly rising edge as tggzzz infers. Fiddling with a cap on the clock input rarely helps. You really need to debounce it one of a several ways and they all involve adding more silicon.1 - Follow the switch with a schmitt trigger gate such as a couple of 4106's in cascade, or2 - a non retriggerable one-shot such as the 4538 set for about 30 ms and with false output tied back to inverting input, or3 - a dedicated, clocked debounce circuit, or4- if your switch is SPDT then following both poles of that with an S-R latch (possibly made with two cross-coupled NAND gates or two cross-coupled NOR gates) will do it.Cheers

author: Someone
author_rank: Super Contributor
timestamp: July 14, 2016, 10:32:06 pm
content: Quote from: tggzzz on July 14, 2016, 11:00:52 amI've seen my explanation in data sheets and app notes. To be sure I confirmed with the fab engineers here, minimum slew rates/maximum rise times on inputs are for preventing metastability and shoot through. Noise margins and multiple triggering of clocks are specified with other parameters. Whats your source?

author: tggzzz
author_rank: Super Contributor
timestamp: July 14, 2016, 10:47:01 pm
content: Quote from: Someone on July 14, 2016, 10:32:06 pmPhysics, and the maths of metastability. Google for it.Metastable behaviour occurs in an extremely tiny time window, and is therefore rare and difficult to stimulate even when you try. I remember it taking about a decade (~ the 70s) before there was a widespread acceptance that it ever occurred! With low frequency clocks, the chance of seeing metastable behaviour is effectively zero.If you persist in believing it is metastable behaviour, please post a picture of the oscillograms showing the flip-flop output waveforms. Also post pictures of the circuit implementation, so that other effects can be discounted.Remember Occam's Razor: choose the simplest explanation.

author: Someone
author_rank: Super Contributor
timestamp: July 15, 2016, 03:08:44 am
content: Quote from: tggzzz on July 14, 2016, 10:47:01 pmThe data sheet specifies:QuoteAnd this reduces with higher operating voltages. From the idealised and rarefied world of specifications it is quite unusual to see a requirement for a maximum transition time on a logic input, and annoying because the designer might want to trade off EMI by intentionally slowing the edge rates while not caring about multiple triggers from noise but the data sheet prohibits it from this constraint. I've seen minimum slew rates specified on non clock inputs, and seen maximum slew rates specified. Given the logic diagram shown in the data sheet it would appear that a metastate on the clock input gate would cause shoot through, exactly the explanation I propose and checked against multiple sources.Quote from: Digibin on July 14, 2016, 04:05:10 pmI don't see a schmitt trigger input (hysteresis) stated in the data sheet, just the normal margins for inputs.

author: tggzzz
author_rank: Super Contributor
timestamp: July 15, 2016, 07:07:09 am
content: Quote from: Someone on July 15, 2016, 03:08:44 amShrug. None of that changes the physics and maths.You don't think that the logic diagram is exactly mirrored in the internal structure, do you?Measuring delays in units of conductance (15nS) doesn't inspire confidence in a solid understanding of electronics.Your understanding of input structures and the reasons for them is faulty; see any decent application note describing schmitt triggers.

author: Someone
author_rank: Super Contributor
timestamp: July 15, 2016, 07:32:01 am
content: Quote from: tggzzz on July 15, 2016, 07:07:09 amYou've not explained how they arrive at your conclusions, and now wander off into nit picking and dancing around the issue. There is a data sheet limit for the maximum transition time (minimum slew rate) and it is to avoid leaving the input logic and the logic downstream of that in indeterminate logic levels for too long, which may damage the device. Here is actel talking about it:http://www.microsemi.com/document-portal/doc_view/130021-ac161-using-schmitt-triggers-for-low-slew-rate-input-app-noteAnd some other random reference:http://www.interfacebus.com/IC_Output_Slew_Rate.htmlThere are many more, and they all mention a schmitt trigger gate to be placed before the sensitive input to provide a sharp transition and eliminate the problems. But the problem is excess dissipation or metastability in the logic being driven with a slow input.

author: Someone
author_rank: Super Contributor
timestamp: July 15, 2016, 07:51:16 am
content: Quote from: tggzzz on July 15, 2016, 07:07:09 amWhen they go to the effort of including a functional layout or overview and it doesn't follow the "normal" methods you might want to pay attention to it. They are explicitly calling out transmission gates as the switching elements.

author: tggzzz
author_rank: Super Contributor
timestamp: July 15, 2016, 08:26:55 am
content: Quote from: Someone on July 15, 2016, 07:32:01 amA quick skim of those references indicates sound engineering and causes/consequences that arecompletely sufficientto explain the double clocking mentioned by the OP. They even have very relevant diagrams.Neither reference contains any reference to metastability.If you still think metastability is an explanation, please indicatethe probability of entering a metastable state, preferably for the OP's clock rate but failing that for any specified clock ratethe expected duration of a metastable stateThe numbers will indicate that metastability is highly improbable.Then use Occam's Razor to choose between alternative explanations.

author: manganin
author_rank: Regular Contributor
timestamp: July 15, 2016, 08:49:01 am
content: Quote from: Digibin on July 14, 2016, 08:44:26 amQuote from: Someone on July 15, 2016, 03:08:44 amThe NXP (Philips) 4013 has a built-in Schmitt trigger while many other manufacturers don't have.

author: MK14
author_rank: Super Contributor
timestamp: July 15, 2016, 08:57:11 am
content: Quote from: manganin on July 15, 2016, 08:49:01 amThat is very interesting, it even says:QuoteIn the datasheet:https://www.nxp.com/documents/data_sheet/HEF4013B.pdfSo maybe the metastability currently occurring in this thread, can settle down and stabilize.But on the other hand, it does recommend:QuoteSo I'm a bit confused here (since I would have thought the Schmitt-trigger, if suitably designed by the IC designers, would allow as slow (clock input transition time) as you like, down to DC). But there must be an explanation, I would think.On reflection, maybe a more powerful Schmitt-trigger (i.e. larger hysteresis voltage) would be needed, but has not been done, because it impairs other parameter(s), such as maximum clock speed, yield, min/max logic level V, etc (I'm guessing here).

author: tggzzz
author_rank: Super Contributor
timestamp: July 15, 2016, 10:22:03 am
content: Quote from: MK14 on July 15, 2016, 08:57:11 amDon't guess, look at the specifications of several devices. If you use any device outside its specified envelope, the specifications do not apply. Full stop. End of story.Limitations aren't put there for fun, they are there to help designers get designs that workreliablyandrepeatably. That's true inallengineering disciplines.

author: MK14
author_rank: Super Contributor
timestamp: July 15, 2016, 05:21:55 pm
content: Quote from: tggzzz on July 15, 2016, 10:22:03 amI did not explain what I meant well enough. Yes, the datasheet specification(s) should/must be used for the design.But what I meant, as regards guessing, was why some of the specifications, applied. (Was put in the datasheet).

author: MK14
author_rank: Super Contributor
timestamp: July 15, 2016, 05:30:56 pm
content: To the OP, I'm wondering if your "double edge triggering", is because of the way you have wired up the switch ?Usually people seem to wire up only one side, of the switch, and a resistor/capacitor handles the other edge.Hence in one direction, you will tend to get very rapid voltage transitions, which should hopefully not trigger multiple times.In the other direction, the resistor/capacitor, would gently (but it needs to be fast enough to meet the datasheet specs) bring the voltage in the other direction, when the switch is released/open.Like this: (the component values are not necessarily the right ones for your circuit)If you want to add a low value resistor, in series with the switch, to limit possible arcing on switch contacts, then fair enough.The way you have it, would seem to increase the risk of the circuit "lingering" at around the flip flop clocks switching voltage, in both directions. Maybe that has got something to do with it toggling on both edges.

author: Kjelt
author_rank: Super Contributor
timestamp: July 15, 2016, 05:35:07 pm
content: Quote from: manganin on July 15, 2016, 08:49:01 amI can't find that specification in the june 1977 SC6 Philips databook under HEF4013B, but it is mentioned in the january 1995 Philips databook, so I am not sure if or when this changed or they just never mentioned it.The logic diagram does differ however, on the 1977 there are two normal inverters used after the CP signal, in the 1995 the first inverter is a Schmitt triggered inverter.

author: Audioguru
author_rank: Super Contributor
timestamp: July 15, 2016, 05:42:01 pm
content: The Cmos Cookbook by Don Lancaster says the clock rise and fall times must be 5ms or faster and yours are 10 times too slow with 10k and 10nF.

author: Kjelt
author_rank: Super Contributor
timestamp: July 15, 2016, 05:45:15 pm
content: Quote from: Audioguru on July 15, 2016, 05:42:01 pmOh really, then what is your formula for the RC delay time when using a 10k and 10nF ?

author: Audioguru
author_rank: Super Contributor
timestamp: July 15, 2016, 05:55:51 pm
content: 10k x 10nF= 100ms. I was wrong, yours are 20 times too slow. I haven't debounced a switch for 30 years so I cannot remember if it gets longer or shorter as the switch wears out.

author: Kjelt
author_rank: Super Contributor
timestamp: July 15, 2016, 06:06:06 pm
content: NANOFarads not MICROFarads a 1000 times difference.You get 10000*0.00000001 = 0.0001s = 100us = 0.1msAnd that is not the correct answer either but a close aproximation.The correct answer is that a 12V CMOS will see a '1' at around 8,8V input voltage.A transient from 0->12V to reach 8,8V on an RC of 10k and 10nF will take aprox. 0.1322 ms or 132us.

author: Someone
author_rank: Super Contributor
timestamp: July 15, 2016, 10:35:10 pm
content: Quote from: MK14 on July 15, 2016, 08:57:11 amThe slow edge through a schmitt trigger is unlikely to oscillate and cause multiple pulses but can still go through a linear region of drive to the complementary fets (C.MOS), yielding an undefined state for an undefined period of time. This can damage some chips and/or cause undefined behaviour. I think tggzzz is stuck on their definition of metastability and doesnt consider these undefined periods as metastability, but they still wont explain anything.

author: MK14
author_rank: Super Contributor
timestamp: July 15, 2016, 11:07:50 pm
content: Quote from: Someone on July 15, 2016, 10:35:10 pmThat is exactly one of the things which came to mind, when I wrote that post.The problem with many logic circuit designs (at the IC level), if I understand things correctly. Is that there is a danger that the top and bottom transistors, will conduct at the same time (shoot through). Some of this, is (apparently) allowed for, in their circuits, e.g. TTL, which I think is known to do this while switching, and is why such extensive decoupling capacitors are required for it.So (as you say), at some voltage point(s) going to the input pin, it may linger at a voltage (e.g. approx half supply), which causes the top and bottom transistors, to "fight each other" (shoot through). I am happy to believe that, that can/may be another cause of metastabilty. Does it matter what we call it, anyway ?Metastability, race hazard, instability etc etc.We are just trying to better understand how logic integrated circuits work here,notdiagnose/fix a faulty production IC design or write a Digital Logic Handbook.When (in real life), one is presented with such technical challenges (professionally). It can take a lot of work, to properly pin down the exact nature of the fault. Calling it metastabilty or race hazard or whatever, too early. Can be a mistake.Although commonly metastabilty is usually caused when the data and clock pin signals are too close together (and probably breaking the datasheet), you can get metastabilty. Potentially any breach of the datasheet, could (in theory) cause it. (But I accept, I may be going too far, maybe some datasheet violations, can't cause metastability issues).Metastabilty is what the engineer(s) might initially call some problems (with flip flop circuits). But when it has been extensively investigated, the actual cause can be something completely different, e.g. a race hazard because the timing was not thought out well enough, by the chip designers.

author: tggzzz
author_rank: Super Contributor
timestamp: July 16, 2016, 04:50:19 pm
content: Quote from: Someone on July 15, 2016, 10:35:10 pmIt isn't me that is stuck, unless everyone else is stuck as well! Metastability has supervise definition and meaning, and some people in this thread are confusing the issue not understanding the topic.For reference, the seminal paper ishttp://ibm-1401.info/AnomalousSynchronizer_ChaneyMolnar_IEEE1973.pdfEven after that, it took a decade before everybody accepted the phenomenon existed. For fun, seehttp://blendics.com/wp-content/uploads/2014/09/My-Work-on-All-Things-Metastable-OR-Me-and-My-Glitch.pdf

author: tggzzz
author_rank: Super Contributor
timestamp: July 16, 2016, 05:01:36 pm
content: Quote from: MK14 on July 15, 2016, 11:07:50 pmIf it doesn't matter what we call it, let's call it the steeplejack phenomenon, or how about clock-slow propagation, or bridging term omission. Or squirdlefloop, for that matter!QuoteSigh. Metastability is a well defined phenomenon. If you want to use a non-standard meaning, then it is up to you to explain your definition every time you use it. If you don't people wont understand you and will ignore you.If you read and understand the seminal paperhttp://ibm-1401.info/AnomalousSynchronizer_ChaneyMolnar_IEEE1973.pdfwhich is the first reference on the wackypedia page, then you will see how wrong your statements are.

author: MK14
author_rank: Super Contributor
timestamp: July 16, 2016, 06:58:25 pm
content: Quote from: tggzzz on July 16, 2016, 05:01:36 pmAre you under the impression, that the "too slow" clock rise and/or fall time,can't bemetastabilty ?Let's look it up and see:QuoteAs apparently requested in another thread. It has been bolded and coloured green for you.Source:http://www.asic-world.com/tidbits/metastablity.html

author: tggzzz
author_rank: Super Contributor
timestamp: July 16, 2016, 08:17:47 pm
content: Quote from: MK14 on July 16, 2016, 06:58:25 pmThe article is bollocks, pure and simple. The author is clueless.. "Whenever the input signal D does not meet the Tsu and Th of the given D flip-flop, metastability occurs" is simply false. Do not confuse not being able to predict whether the output is high or low with metastability.Please please read the reference provided before attempting to sow confusion by unhelpfully changing a definition.Please show you have done that by calculating the probability of a flip-flop entering the metastable state. (Hint, with the clock frequencies in question, the mean time is longer than the age of the universe.

author: MK14
author_rank: Super Contributor
timestamp: July 16, 2016, 09:49:24 pm
content: Quote from: tggzzz on July 16, 2016, 08:17:47 pmIf you are going to attack the source(s) I supply like that. Even though that source has its own list of references, within the article. One of which is apparently by the same author(s) {Thomas J. Chaney, "Measured Flip-Flop Responses to Marginal Triggering", IEEE Transactions on Computers, Vol. C-32. No. 12, December 1983, pp.1207-1209.} that you seem to be going on and on about.Also since there are other sources apparently saying the same or similar thing, I am still happy with my source(s).I am going to have to call it a day, as we are already beginning to be partly off-topic, by discussing metastabilty anyway.As regards myself, your latest argument hasnotswayed my opinion on metastabilty, sorry!

author: tggzzz
author_rank: Super Contributor
timestamp: July 17, 2016, 05:50:03 am
content: Quote from: MK14 on July 16, 2016, 09:49:24 pmIt is revealing that, while I look at your random (and incorrect) source, you cannot be bothered to look at the seminal source I provided, nor to answer the basic question reveals whether or not you have even a basic clue about metastability.I am content for others to judge which of us know what they are talking about in this instance.

author: Simon
author_rank: Unknown
timestamp: July 17, 2016, 08:00:40 am
content: Sorry people but this is getting more unruly than brexit and I' locking it as it's clearly helping no one