Interfacing FT232H to FPGA in FIFO Synchronous mode; 1 clock wide TXE# pulses - Page 1
Forum section: electronics / general

author: bsccara
author_rank: Contributor
timestamp: October 17, 2024, 11:46:36 pm
content: I need to get a FT232H working with an ECP5 FPGA in Synchronous mode as a loopback device. My design has all inputs and outputs to/from the FT232H registered to improve timing, as all other designs I've found online. I'm using Manta to capture the FPGA's internal signals and on the PC side I have code that sets up eight 4KB buffers full of 33 byte long records that run from 0x00 to 0x21. To receive I use eight 512 bytes long buffers and I pass them all to libusb's asynchronous functions, running on Kubuntu 24.04.1.My problem is that after some packets I start getting errors in the data, like shown below:As shown, instead of getting ...0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D... I'm getting ...0x06, 0x07, 0x09, 0x0A, 0x08, 0x0C, 0x0D... I know that the problem is due to my design not being able to handle something that I was not expecting; the TXE# goes high for a single clock cycle, as shown below:(signals starting with 'r' are registered inputs and with 'u' are copies of the registered outputs)But if indeed the TXE# can go high for a single clock cycle that makes it impossible to register the inputs and outputs of the FT232H, as by the time the internal logic reads the TXE# (one cycle after it happened) its already too late for pull WR# high to stop the transmission into the FIFO, since it would take another cycle for the output to switch, by which time the FT232H would have already captured another byte, as seen in the image above.Is this one-cycle-high normal behaviour or is this a clone that does not implement the FIFO Sync mode properly ?

author: bsccara
author_rank: Contributor
timestamp: October 18, 2024, 09:16:19 am
content: I've looked into FTDI's App Note 165, which focus on interfacing a FT2232H with an Altera Cyclone II FPGA. In their accompaning VHDL code the #TXE signal is fed directly into the state machine, without any registering. If that implies that the #TXE line can switch at any time, including on consecutive clock cycles, is what I'd like to know.

author: glenenglish
author_rank: Frequent Contributor
timestamp: October 18, 2024, 09:53:21 am
content: another way to look at it , from the other direction, is that if TXE was high on the previous cycle, then that word was transferred, and has not yet otherwise . A little like an AXI4 stream transfer. If you accept data every clock cycle and then check the TXE state for that cycle, that shoul dtell you if the data was valid to transfer.

author: tom66
author_rank: Super Contributor
timestamp: October 18, 2024, 10:12:10 am
content: How fast can the output data toggle? I would consider approaching this like sampling UART. Sample the input against a fast clock (4-8x the input but it does not have to be synchronous) and vote majority for each bit. If it is 60MHz you could probably get up to 240MHz on a modern-ish FPGA, if you keep the fast clock close to the input.You can also turn the input for TXE# into DDR logic, feed the clock and data into DDR logic and if Q0==1, Q1==0 then you have TXE# event.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 18, 2024, 02:35:05 pm
content: You don't need (and shouldn't) "register" any of the input control signals from the FT232H. This is a synchronous interface. The FTDI chip provides the clock. You can directly read these signals in your state machine.Make sure your state machine IS clocked by the FTDI clock and not by your own clock in another clock domain.If you need to cross clock domains, use FIFOs for instance.