Fast trigger latch - Page 1
Forum section: electronics / beginners

author: AlexRG
author_rank: Regular Contributor
timestamp: September 11, 2025, 04:51:47 pm
content: Hello everyone. For fast, emergency shutdown of the driver, I need to develop a fast trigger latch. It should work according to the following algorithm:1. Supply voltage 5V.2. When the power is turned on, the latch output should be +5V (logical 1)3. If a constant voltage or pulses with an amplitude of +5V (logical 1) are supplied to the latch input, the latch output should be 0V (logical 0). After this, the latch should self-lock.I developed such a trigger latch on the SN74HC00 logic, using three elements. The response time (from input to output, through 3 consecutive elements) is about 80ns. In the future, I will try to install the SN74AHC00 logic, it should be 3-4 times faster.However, maybe there are already specialized trigger latches that are suitable for my simple task? Let me remind:- 5V power supply- state response time from input to output 6-15ns. Faster than 6ns is not necessary, because there is a risk of self-excitation and false alarms.If you have encountered such a chip, please write about it. What kind of chip is it and how to connect it.

author: AlexRG
author_rank: Regular Contributor
timestamp: September 11, 2025, 04:55:03 pm
content: p.s.In the diagram, resistors R4, R5 and power supply V2 simulate the driver control circuit. If the driver control is +5V, the driver works. If 0V, the driver turns off.

author: jwet
author_rank: Frequent Contributor
timestamp: September 11, 2025, 09:09:39 pm
content: You could use a fast comparator with a lot of positive feedback so it essentially becomes a latch. The LT1016 is extremely fast- 10 nS, as are the LT1116. The retail pricing for these things is ridiculous. Perhaps you can find one one ebay for a few bucks.On your present circuit, it should work much better than your results. The prop delay of HCMOS is about 10 nS. Loading the output with big caps will slow things down a lot. However, the output Z is about 10 ohm and with a 1 uF cap hanging there, you'll be getting into uS times for latching. No reason to use a big cap or any for that matter. Use a set reset type circuit with the same HC00. The circuit uses cross couped ANDS- a google circuit will show the way.

author: AlexRG
author_rank: Regular Contributor
timestamp: September 11, 2025, 09:36:44 pm
content: C1 in the diagram is only needed for reliable triggering of the latch. If it is not installed, then when power is supplied, the latch output will be logical 0. I have already checked this experimentally on a breadboard. This capacitor is connected only to one input of one of the elements and does not affect the working delay of the output state transition from 1 to 0.On the other hand, could you draw the same diagram on the comparator, so that the latch blocks itself after triggering?

author: jwet
author_rank: Frequent Contributor
timestamp: September 11, 2025, 10:37:48 pm
content: Here you go- you have to find the LT1016 at a decent price, its an old classic and never cost more than a buck. I guess you could find an equivalent with digikey's search engine. Its an alternative to be aware of.(also you're right about the power up reset, my mistake, but make the c much smaller and the R larger, CMOS is high impedance, the problem is having a bunch of charge in this thing with no where for it to go. On power down, it going to go into that gate's protection diode and a decent ceramic cap could provide several amp- degrading and eventually trashing that gate)Your existing circuit should have a delay of 32 nS nominal, I don't know why you're seeing 80 ns. Is the part bypassed close to the Vcc and Gnd pins- this can make a big difference and will be more important with AC MOS. CMOS is limited by its ability to charge nodes and you need a bypass resevoir to do that.Is your test setup and scope fast enough to catch all this action? You need a pretty decent scope- the old rule is BW = .35/tr, so to capture pulse with rise times on this order- say 5 ns, you need a 70 Mhz scope "minimum". Somewhere around 200 Mhz would be comfortable and you wouldn't have to back your scope rise time out the equations.Good luck.

author: AlexRG
author_rank: Regular Contributor
timestamp: September 11, 2025, 11:00:37 pm
content: Quote from: jwet on September 11, 2025, 10:37:48 pmOne SN74HC00 element has a delay between input and output of about 22ns at 5V supply. I have 3 series elements in the circuit, so the total delay time is 22x3 = 66ns. Having measured with an oscilloscope, it turned out to be about 80ns. You can take into account the error, the capacitance of the mounting, the capacitance of the oscilloscope probes, etc.I simulated your circuit and it did not work. When power is applied, the output is not 5V, but 2.524V. When S1 is closed (simulation of applying logical 1 to the latch input), the output is not 0V, but 2.499V. Let me remind you that R1, R2 and the 12V power supply are an imitation of the driver input control circuit, these elements cannot be removed. When power is applied, the latch output should be logical 1. When logical 1 is applied to the latch input, logical 0 should appear at the output and the latch should self-lock until the 5V power is restarted.

author: jwet
author_rank: Frequent Contributor
timestamp: September 11, 2025, 11:06:34 pm
content: R3 and R4 are borked.When experts are giving you free advice, you should take it easy and look over what you've got before you fire back.Good luck with your projects.

author: AlexRG
author_rank: Regular Contributor
timestamp: September 11, 2025, 11:48:02 pm
content: Quote from: jwet on September 11, 2025, 11:06:34 pmIt seems to me that an expert is a person who does not make mistakes when giving free advice to someone.I changed the circuit exactly as you suggested. It works exactly the opposite, not as I need.1. When we apply power, the output is 800 mV (should be 5 V)2. When we apply a logical 1 to the input (we close S1), the output is 5 V (should be 0 V) ​​However, the latch already blocks itself. If you open S1, the output remains 5 V. Dear expert, please correct your circuit.

author: jwet
author_rank: Frequent Contributor
timestamp: September 11, 2025, 11:57:15 pm
content: You're a piece of work buddy. Good luck.

author: ledtester
author_rank: Super Contributor
timestamp: September 12, 2025, 01:03:56 am
content: Attached is my effort to simulate it using LTspice.In the graph, Vout is the green trace and the inverting input of the LT1016 is the blue trace.A cursor measurement yields a response time of about 12ns.

author: PGPG
author_rank: Frequent Contributor
timestamp: September 12, 2025, 07:58:56 am
content: There should exists D-Latch having also Set/Reset inputs.Using one of Set/Reset you should be able to ensure initial state you need.Pulse at Clock input could latch the state from D input permanently.I believe time delay will be shorter than in your circuit.

author: AlexRG
author_rank: Regular Contributor
timestamp: September 12, 2025, 11:49:46 am
content: Quote from: PGPG on September 12, 2025, 07:58:56 amPlease draw a diagram of your implementation and write an approximate name of such a chip.

author: Zero999
author_rank: Super Contributor
timestamp: September 14, 2025, 11:12:18 am
content: The 74HC00 is perfectly suited to this application. There's no need for special comparators.R3 and C1 just ensure the circuit always starts with the output high, when the power is first applied. I recommend increasing R3 to 430k and reducing the capacitor to 10nF. That will keep the time constant the same and reduce the amount of energy stored in the circuit, which is good, as it reduces the risk of damaging the CMOS inputs and reduce the time required for the circuit to reset, when the power is removed.R2 isn't required, because the 74HC00 has a push-pull output.R4 & R5 aren't needed either.EDIT:Simulation attached.

author: MathWizard
author_rank: Super Contributor
timestamp: September 17, 2025, 02:05:46 am
content: So how fast are the fastest latches? How fast would some latch in a new AMD or Intel CPU, or GPU, all at a few GHz be ??

author: Zero999
author_rank: Super Contributor
timestamp: September 17, 2025, 07:21:30 am
content: Quote from: MathWizard on September 17, 2025, 02:05:46 amThe latch inside an IC will be faster than discrete components because it's a fraction of a wavelength of the switching frequency. Building a latch from discrete components which will work at several GHz is more challanging because the waveform contains components of tens of GHz and a quarter of a wavelength of those frequencies is several mm.

author: PGPG
author_rank: Frequent Contributor
timestamp: September 17, 2025, 10:42:24 am
content: Quote from: MathWizard on September 17, 2025, 02:05:46 amFastest all over the world - I don't know.What is easily available - I use LVC1G79:https://www.ti.com/lit/ds/symlink/sn74lvc1g79.pdf?ts=1758091712984&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FSN74LVC1G79that 3V3 supplied has setup time = 1.3ns and hold time 1ns.In my application one slope is 2ns before the clock slope and it is latched.What I detect is when first slope shifts 4ns to be 2ns after the clock slope. I think true detection is made even for smaller shift, but it is just a certain reserve over the design assumptions.