Confusing MOSFET transition times - Page 1
Forum section: electronics / projects

author: mbless
author_rank: Regular Contributor
timestamp: July 13, 2020, 04:48:19 pm
content: I’m evaluating negative high-voltage pulser designs (see this thread), part of which I’m testing different mosfets. For the current topology I tested 4 mosfets, but I ended up with confusing results regarding the turn on/off times.Here are the mosfets and a summary of what I believe are their relevant numbers. Data sheets are linked.PartInput capacitance @ 150VTotal gate chargeEnd of Miller plateau @ 400VST STF12N50M2560pF15nC @ 400V12nCInfineon IPA60R280P7S760pF18nC @ 400V10nCON Semi FQPF8N80C1580pF35nC @ 640V22nCON Semi FQA19N602800pF70nC @ 480V49nCBased on the parameters, I would expect the rise/fall times to increase as you move down the list. I tested the parts by pulsing -150V into a 50ohm non-inductive resistor for a commanded 100ns. I used the same PCB for all parts so everything would be the same except for the mosfet. All mosfets are also TO-220 package. What I found, though, is that the 3rd part (FQPF8N80C) was the fastest and closest to the commanded on time. Here is a table of rise, fall and on times extracted from the attached plot of output voltage. Note that I didn't measure current, so I'm treating the on time as conduction time.PartRise time -10V to -140VFall time -140V to -10VOn time -10V to -10VST STF12N50M27.6ns20.4ns130.8nsInfineon IPA60R280P7S5.6ns22.0ns132.0nsON Semi FQPF8N80C5.6ns12.8ns109.6nsON Semi FQA19N608.8ns26.8ns130.8nsI'm trying to figure out why the FQPF8N80C performed so well when its parameters are 2-3x worse than the STF12N50M2. Normally I wouldn't even have selected FQPF8N80C for testing based on its parameters; I only chose it because it was in an Art of Electronics example circuit for nanosecond pulsers. So far the only two distinguishing characteristics I can find aredifferent MOSFET technology from different manufacturersSTF12N50M2 and IPA60R280P7S have built-in gate zener diodes where as the FQPF8N80C and FQA19N60 do not. Not sure why the fall time would be so adversely affected unlike the rise time.What am I missing?EDIT: Imgur albumhttps://imgur.com/a/AYe0QeD

author: TimNJ
author_rank: Super Contributor
timestamp: July 13, 2020, 05:17:24 pm
content: I don't have enough experience to give a good answer, but what does your test PCB look like? Sometimes a poor gate drive layout with high inductance can cause a "high performance MOSFET" to underperform, maybe even worse than a MOSFET that's worse on paper. Reasons may be include parasitic oscillation during switching transitions.

author: jmelson
author_rank: Super Contributor
timestamp: July 13, 2020, 06:10:25 pm
content: Input capacitance is not the whole story. A major component is the "Miller" capacitance, ie. the capacitance from the drain to the gate. While much less than the gate-source capacitance, the drain swings, perhaps, 50 X the g-s voltage swing.During turn-on, the gate is brought up to, perhaps 12 V, with respect the the source. As the transistor turns on, the drain voltage falls toward the source voltage. But, the falling drain voltage pulls charge away from the gate, causing the gate voltage to plateau until the drain has come most of the way down to the source voltage.To turn it off, the reverse happens. You want to bring the gate down to zero, with respect to the source. But, then the rising drain voltage puts charge back into the gate.Jon

author: temperance
author_rank: Super Contributor
timestamp: July 13, 2020, 08:16:02 pm
content: Rising edge: You can actually see what's happening from the measurements you've made. With a 50R load, the FQPF8N80C will be the fasted MOSFET because it has the smallest output capacitance.Falling edge: artefacts in timing are caused by differences in the miller plateau voltage and the output resistance of the driver circuit.

author: magic
author_rank: Super Contributor
timestamp: July 13, 2020, 08:20:06 pm
content: Quote from: temperance on July 13, 2020, 08:16:02 pmAlso my thought. The FQPF8N80C has higher threshold voltage, therefore more volts is applied across internal and external gate resistance during turn-off. Internal gate resistance is unspecified, perhaps it's smaller than the 7Ω specified for the other two parts. At an amp or two of drive current it may make a difference.

author: trobbins
author_rank: Frequent Contributor
timestamp: July 14, 2020, 12:24:03 am
content: Datasheet parameters for each fet use different test levels. Eg for Qg: 400V 10A; 400V 3.8A; 640V 8A; 480V 18.5A.Apart from testing in a jig like you have done, I'd anticipate you would need to do a sim with each FET - benchmarked for the datasheet parameters - to get a view as to relative switching performance. However, the sim has to include the non-linearity of Cdg rather than just use a linear cap model.

author: mbless
author_rank: Regular Contributor
timestamp: July 14, 2020, 12:40:53 am
content: Quote from: TimNJ on July 13, 2020, 05:17:24 pmThis is theschematic based on the Brown 2002 paperwhich is a two-stage totem pole driver. I attached a screenshot of the 3D view, and the bottom is a solid ground plane. It's definitely not the best layout since the components are large and hard to minimize the loop area.I also added the gate drive voltage traces. All except the STF12N50M2 initially reach the peak drive voltage before dropping. Is that the oscillations you speak of?

author: mbless
author_rank: Regular Contributor
timestamp: July 14, 2020, 01:17:34 am
content: Quote from: jmelson on July 13, 2020, 06:10:25 pmI added roughly similar gate charge at the end of the Miller plateau to my table in the first post to consider this. My understanding (I'm a ME not EE so please forgive my ignorance) is that full conduction is reached at the end of the plateau. Given that, FQPF8N80C has ~twice the capacitance of the first two but similar turn on and faster turn off.Quote from: temperance on July 13, 2020, 08:16:02 pmAre you sure you looked at the correct datasheets? At 150V I'm seeing 30pF for STF12N50M2, 18pF for IPA60R280P7S, ~100pF for FQPF8N80C, and ~250pF for FQA19N60.Quote from: magic on July 13, 2020, 08:20:06 pmSo if its gate resistance is smaller then it would go back down the gate charge curve faster. Makes sense then that it would start the falling edge sooner. So is the slow transition to the high dV/dt portion of the falling edge the Miller plateau?

author: mbless
author_rank: Regular Contributor
timestamp: July 14, 2020, 01:30:36 am
content: Quote from: trobbins on July 14, 2020, 12:24:03 amI think testing is going to have to be the way since I've simulated some and the real world performance is better than simulation suggested. My issue is being able to narrow done parts to test since I would have excluded FQPF8N80C with my standard approach.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 14, 2020, 02:52:59 am
content: Ugh... I was interested in this thread, but I see the forum attachment bug has rendered it useless.Can you please host images externally for now? (I recommend Imgur.) Thanks.Tim

author: trobbins
author_rank: Frequent Contributor
timestamp: July 14, 2020, 04:21:12 am
content: Quote from: mbless on July 14, 2020, 12:40:53 amI quickly checked your other thread, and same issue cropped up - why aren't you just using a purpose made gate driver IC - many varieties have been around for decades ?If you are using that design because you read it in a book, then I think that is your problem. Perhaps if you read up on the app notes for dedicated driver IC's, that may help you get a better awareness.

author: mbless
author_rank: Regular Contributor
timestamp: July 14, 2020, 04:45:46 am
content: Quote from: T3sl4co1l on July 14, 2020, 02:52:59 amDoes this work?https://imgur.com/a/AYe0QeD. Imgur has changed a lot since the last time I used it.Quote from: trobbins on July 14, 2020, 04:21:12 amAs addressed in that thread, it's a requirement to reproduce that topology as a baseline and then I can improve upon it. It's from a journal article with images of the PCB and output voltage. The PCB was etched and the components are fairly spaced out, so I'm not worried about my PCB layout. I'd wager I almost have the same dV/dt as them, so I'm trying to understand the mosfet difference here.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 14, 2020, 06:21:05 am
content: That works!So, it looks that gate drive goes through quite a loop: C7, Q7, C9. Probably 20nH total? And if C9 is bypassing the supply with respect to the load side as well, then more than half of that loop is carrying load current as well as gate drive -- that is, you have source inductance through the whole path.This is one of several reasons why the circuit shown is just not a good idea.FYI, the gate capacitance doesn't make much difference; it's a small-signal off-state parameter (Vgs = 0) and ignores not just Miller effect, but much of the nonlinearity (Vds = 150V is well above the interesting 10-50V range for most of these). Fortunately they're in order of Qg(tot) as well, so this should be okay.What I think is interesting is:- The times listed are in no proportion to the gate capacitance or charge- The gate drive is pretty slow anyway; I've built a similar circuit (MOS inverter driver, though also buffered with a BJT follower) which seems to be much faster, even at high loads (10n + 2.2R):https://www.seventransistorlabs.com/Images/GD8.jpghttps://www.seventransistorlabs.com/Images/GD9.jpg- The FQP and FQA parts have serious ringing, at turn-on at least. Their capacitance is high enough that there's a modest Q to the inductive loop. Which if that's ballpark 4nF and 20nH would be 18MHz, or a 28ns half-period. Which... is eerily close to the lumps seen on the FQA gate waveform, despite my just ramming together two one-would-hope unrelated parameters.- In here,I think your Miller plateau is actually very near the top, and doesn't start until about the 25ns mark. Where the crazy stuff (over/undershoot) begins. That this is at a high voltage, implies one or both of: drain current is very high, or source inductance * dI/dt is very high.- Likewise, everything starts unloading by the ~113ns mark, and you get similar ringing, but at somewhat higher frequencies because the gate capacitance is now higher (because Vds is high).So we might express this as so:Hypothesis: gate charge dominates switching time.Evidence: test a series of transistors with a 5:1 spread of gate charge; examine switching time.Result: switching time has a 2:1 spread, and is poorly if at all correlated with gate charge.Conclusion: the hypothesis is very unlikely to be true.Indeed, we might suspect that, because the switching time has barely changed over this spread, we should consider other invariants in the circuit.The drivers are one. You can test them independently, with a low inductance RC network, say, 1-4.7nF + 1R. You should find they perform well, and that the variance is smaller than seen here -- it might span say 10 to 20ns, or be even faster like 5-10ns. If it's 10-20ns, it may be a strong contributor to overall performance; if it's much shorter, you'll be looking elsewhere.I think you will find the elephant on this PCB (so to speak) is the switching loop. Make gate drive through a short Kelvin connection, and you will get much closer to the capability of the driver. This isn't easy to deliver via coupling capacitors. I suggest building an isolated gate driver, so you can continue experimenting with greater flexibility.I think it's telling, that the gate waveforms are already at full, in the first 15ns or so rising, and 10ns falling; the transistors are literally catching up afterwards. And a slower rise is typical of "complementary" PMOS, so I suspect the driver is doing alright for what it is.Also, if possible, change the package:- D2PAK parts have shorter lead length- Or especially D2PAK-multilead types, with intended Kelvin connections- DFNs, if possible. Not really an option, I think, as PDSO-8 style parts don't come in quite high enough ratings. Also, the real good ones are GaN, which might be... a bit too hot to work with, without more experience. (Something to look forward to? Just blast out 1ns edges in the first place?)SMTs are harder to heatsink than THT; and DFNs are harder than D2PAKs. If your PRF is high enough to require substantial heatsinking, this might not be an option. In that case, you can consider using more THTs in parallel (with individual drivers, to avoid strays causing skew), which reduces lead inductance proportionally, but increases heatsinking capacitance proportionally as well.Which, if you get to the point where heatsink capacitance is a barrier, they actually make HIP extruded alumina heatsinks -- sounds insane but they're not even aerospace priced, very much affordable in one-offs. Thermal conductivity is a lot poorer than aluminum of course, but still more than good enough for natural convection, or modest forced convection. As an excellent insulator, they add almost no capacitance to the drain tab!And if you do need a lot of power, look at AlN insulators -- fantastic stuff, conductivity about halfway between aluminum and copper metal! A bit hard to source.Tim

author: magic
author_rank: Super Contributor
timestamp: July 14, 2020, 06:35:39 am
content: Quote from: mbless on July 14, 2020, 12:40:53 amNitpick: totem pole is a pair of emitter/source followers, like your first two FETs driven by the opamp. The other "stacks" are basically discrete CMOS inverters.But why? That thing looks complex for what it does. Why drop money on a high speed opamp if there are much simpler gate drivers which, I think, should be able to do the job better and probably even cost less?From my time playing with high speed switching, I remember TC4551 being the beefiest driver I found (chances are a weaker/cheaper one would suffice for you). I ended up not using this part, but anyway, look at the datasheet - it laughs at load capacitances below 1000pF. It should get to the Miller plateau in less than 10ns and then plow through it at up to a few amps of current, limited by the FET's gate resistance and your board's inductance, which you minimize by placing things close together and using a single-chip driver kinda makes that easier.I think even replacing the opamp with a gate driver and then using the discrete output stage would still be an improvement, in terms of cost if nothing else.Quote from: mbless on July 14, 2020, 12:40:53 amThe peaks and valleys are probably a slight ringing due to all inductance between the driver and the FET.You really need to minimize these loops:gate - gate driver output - gate driver guts - gate driver ground - sourcegate - gate driver output - gate driver guts - gate driver VCC - gate driver bypass capacitor - gate driver ground - sourceThis also implies that you need a nearby bypass capacitor between the driver's ground and the FET's source, if you really insist on AC coupling between the driver and the FET. I would investigate the feasibility of putting the driver at -350V and somehow isolating its input signal, perhaps?If you want to AC couple the driver's output, put it as close to the FET as HV clearences permit. And I think a smaller, ceramic coupling capacitor would have less ESL, not sure if there are some safety concerns preventing that.Quote from: mbless on July 14, 2020, 01:17:34 amThere is actually one place where output capacitance matters: the end of the falling/(rising?)AKA the turn-off edge. Since the output is pulled up to 0V by a resistor, it's subject to the standard exponential decay curve. The knee near 0V is probably due to differences in output capacitance and nothing more. 250pF times 25Ω is 6ns time constant - even if the FET conducts exactly nothing, it takes 6ns for the output voltage to get some 60% closer to 0V than it currently is, again and again. Use the FET with the lowest output capacitance if this is important to you, simple as that.editMiller plateau is when the drain voltage rises/falls and your switching speed is limited by your ability to source/sink current into the parasitic gate-drain capacitance which is being (dis)charged in the process.BTW, look up maximum dV/dt that your FETs are capable of surviving and (ideally) don't exceed this limit. There is such a limit, if you go faster, the FET may spuriously turn-on when it's supposed to be off and blow up. I have never seen it happen (because I didn't try), but all FET manufacturers swear that it can happen.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 14, 2020, 06:57:39 am
content: Oh, I was also thinking but forgot to add: tabulate Vgs(th), and maybe transconductance at a given (equal for all parts if possible) drain current.The Miller step is relative to Vgs(th), so a higher threshold gives slower rise and faster fall; or vice versa. (A good reason to avoid logic-level parts, when full drive voltage is available -- the Miller step is at so low a voltage, you literally can't draw any more than whatever the short-circuit current is from the gate. Only fix then is to use negative turn-off. Which is definitely an option here, given the cap coupling, heh...)Tim

author: magic
author_rank: Super Contributor
timestamp: July 14, 2020, 07:14:39 am
content: OP actually AC couples the drive signal so I think the drive waveform will be centered around ground or something like that?In such case, a low threshold / logic lever FET could even offer better on/off matching, I think.That being, the gate waveforms that have been posted show a 0V-15V swing. What's going on in here?editNevermind, the output is at zero almost all the time and only turns on for 100ns. So it will be 0-15V swing and 7V threshold FET would be ideal. Note that it may be easier to change driver supply voltage than use an otherwise bad FET just for its threshold voltage.And that's provided that the output impedance / current capability of your driver is fully symmetric

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: July 14, 2020, 08:12:36 am
content: Not an expert when it comes to discretes, but on chip at RF we can tune out the all the capacitance with inductance. The thing that limits our ability to do so up to arbitrary frequencies is the resistance of the terminals (mostly gate resistance) since it exists between the capacitor we want to tune out, and the inductor/transmission line we use to do the tuning. I wonder if this is related to what is going on here?Also, what about mobility and so on? different doping amounts or such influencing the carrier recombination time of the channel? I would imagine all that happens order of magnitude faster than the rates at which you can switch these things but I'm not sure.

author: magic
author_rank: Super Contributor
timestamp: July 14, 2020, 08:59:58 am
content: It works for RF because the inductance is already "precharged" to some desired state by the previous cycle of the wave when the next one begins, so its current aids with discharging the capacitance right when you need it.You can't "tune" an LC tank to do a single edge on commandThere is little philosophy here, you just have a capacitor which you need to rapidly short out and discharge.Quote from: TheUnnamedNewbie on July 14, 2020, 08:12:36 amI wondered about it too, but it seems that FETs are pretty darn fast and shoving charge in/out of the gate against all inductance and resistance usually is the limiting factor.I had little trouble devising a circuit which turned off a FET fast enough that it took maybe 10~20ns to go from 0Vds to avalanche at 250Vds, with a 10A inductive load (inductive load actually helps with fast drain slew rates, if you know what I mean).I was a total noob playing with a flyback transformer and thought that the faster I switch it, the better. It probably didn't matter that much, but whatever

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 14, 2020, 11:37:42 am
content: Quote from: TheUnnamedNewbie on July 14, 2020, 08:12:36 amRight, in fact we can methodolize that --1. Understand the network the transistor is embedded within.2. Determine the intrinsic properties of the transistor, in some reference arrangement. (Remember, surroundings matter, too: whether it's bolted to a heatsink, etc.)Once we know R, L and C, we can tune out L and C for narrowband purposes, or do our best to peak them for baseband purposes.Note, switching is a baseband application. It's also large-signal, so we need a model that accommodates that as well, not just a small-signal s-matrix or the like.3. Device properties. If we have insight into their fabrication*, we can begin to understand physical properties and fundamental limitations.*Heh, well, you do, in your field of work; the rest of us, down here at DC, well...Now, I've had accidental oscillation up at several hundred MHz before. Not a very strong signal (the amplitude being a fraction of total supply -- mind, still way more than I'd want during an EMI scan), but these things are definitely getting squirrely. That's kind of around the fT of the device. Which doesn't mean it's incapable of power gain up there -- it's just not nearly as much as at lower frequencies, and the impedances are all flippy-floppy, making it impossible to amplify a pulse that square. An analogy might be blowing a whistle with molasses: maybe it oscillates, but it takes a lot of effort, so it's not very useful, just annoying when it happens...Since switching is baseband, we're limited to some fraction of fT, and to obtain reasonable squareness or efficiency, it's a tiny fraction at that -- maybe 1/100th.Which means, a PRF of some MHz, or pulse widths of 100ns give or take, are reasonable. Which, well, that's what we're seeing here.So that's device limits. Once we have a model of pin strays and device R and C, we can optimize the driver and load coupling networks.I do think device physics, mobility and such, have some effectnearby, but for the most part are well outside the range of interest. If resistances were lower, fT would be higher, and we could push narrowband operation up there, maybe at useful power levels. Baseband operation still wouldn't be up there, but given lower inductance connections, we could at least push it a little higher.So, I think we're currently at step 0 -- my vote is on uncontrolled mutual source inductance. We have much to cover, before we can even begin to observe device limits, say. Not that a full understanding is very applicable here, or even very possible with these devices; but the first two steps will be great value.The big differences between switching and RF types, are: impedance range, lead inductances, and power dissipation. Capacitance nonlinearity also tends to be a bit better with RF types.Impedance, because switching devices use big junctions (lots of width or perimeter), prioritizing low Rds(on) at the expense of capacitance.Inductance, because leads are easier to work with than pads (e.g. DFNs) or tabs (e.g., RF microstrip packages).Power, because to get the output moving at the desired rate (against all that capacitance), much load current must flow.For example, the PD57006-E is basically a power 2N7002. It has very wide gate and drain terminals, the package can dissipate 10W, and it has similar Rds(on) (ca. 1 ohm) and capacitances (ca. 30pF). Probably the die area is substantially larger, and the layout is optimized for isolation (low Crss) rather than, well, I don't know what a 2N7002 is really optimized for, if anything at all, to be honest... And of course, lower intrinsic resistances. The 2N7002 is dropping off heavily by 50MHz (where its gain is dropping approximately as sqrt(1/f), so that it still has some gain left even at 200 or 400MHz, actually), but this thing is useful beyond 1GHz due to all these differences.Also interesting that old transistors, like 2N7002, typically have a diffusion characteristic -- resistance and gain going as sqrt(1/f). Newer transistors have solutions for this -- presumably, they have moved from uniform planar interconnects (the gate is a sea of metallization applied over the source metallization and channel oxide), to fractal interconnects (routing in stages, from wide traces off the bond pad, to smaller secondary traces, and so on, finally connecting tiny traces up to individual MOS cells; the resistance from bondwire to any transistor cell is approximately equal). This gives good agreement when modeling a transistor as a lumped equivalent gate resistance and capacitance.Tim

author: David Hess
author_rank: Super Contributor
timestamp: July 14, 2020, 01:05:34 pm
content: Are you separating delay time and transition time? During turn-on, until the gate voltage reaches the gate threshold voltage, nothing happens so there is a delay before the MOSFET begins to turn-on. Transition time is only controlled by the charge transferred during the Miller plateau. The same thing applies during turn-off with the delay being proportional to the gate voltage above the Miller plateau.Some designs minimize the turn-on and turn-off delay by precharging the gate or limiting how much extra charge is applied. But when PWM is used, then the extra delay times get removed by the PWM control circuits so they do not matter.

author: mbless
author_rank: Regular Contributor
timestamp: July 14, 2020, 01:09:07 pm
content: Quote from: T3sl4co1l on July 14, 2020, 06:21:05 amNow that's some interesting guess work! I calculated 48MHz for FQP and 30MHz for FQA.What makes you think the Miller plateau is at 10-12V instead of ~6V from the datasheets?Comparing the gate voltage and Vds waveforms shows it is around 10-12V.Quote from: T3sl4co1l on July 14, 2020, 06:21:05 amI do have an isolated gate driver PCB with the desired small loop area to test out. It appears the general consensus is to use the ideal PCB to test the mosfetsQuote from: T3sl4co1l on July 14, 2020, 06:21:05 amI actually have DPAK versions of a couple of the mosfets in the same PCB design to see if I measure the effect of lead inductance/package size. The PRF is very low, so I'm not expecting to need heatsinking.Quote from: T3sl4co1l on July 14, 2020, 06:57:39 amThat's a good tip since I need to improve on the falling edge.

author: temperance
author_rank: Super Contributor
timestamp: July 14, 2020, 01:22:59 pm
content: Drain source capacitance for your MOSFET'sSTF12N50: 4nF @ 100mV and 1nF @ 10VVIPA60R280: 10nF @ ~0V and 200pF @ 25VFQPF8N80: 2nF @ 100mV and 250pF @ 10VFQA19N60: 5nF @ 100mV and 500pF @ 10VThe drain to source waveform shows how the voltage dependent drain source capacitance is being charged by a 50R source. That's why the IPA60R280 is "slowest" is your setup.And other thing I forgot to mention about the falling edge (drain to source) but it has been mentioned by others is the intrinsic gate resistance which is very often not included in the data-sheet.You might want to read this book. Especially chapter 3.2:https://archive.org/details/bitsavers_siliconixdixMOSPOWERApplications_38092918

author: mbless
author_rank: Regular Contributor
timestamp: July 14, 2020, 01:32:05 pm
content: Quote from: magic on July 14, 2020, 06:35:39 amI also have an isolated gate driver PCB using recent tech to test. The attempt at AC coupling was quite simple but appears to be hard to implement in terms of loop current. I think I would have clearance issues for 500V, of course that all depends on which standard you follow for clearance and creepage. I'm also not sure of typical ceramic caps' quality at 500V.Quote from: magic on July 14, 2020, 06:35:39 amI would expect to see a more pronounced knee for FQP than STF since it has higher output capacitance, so there must be more going on. Or my eyes are deceiving me.Quote from: magic on July 14, 2020, 06:35:39 amGood point. I'm seeing 50-80 V/ns, so I'm getting close to that at peak dV/dt during turn on. I can foresee surpassing that when I go to higher voltages.Quote from: magic on July 14, 2020, 07:14:39 amCorrect, the mosfet gate is actually swings from -150V (off) to -138V (on). I didn't include the plot since I stupidly recorded data with it in dc-coupled mode, so the bit digitization resulted in poor resolution. It looks the same, though, with ringing in FQP and FQA parts. There's also ~3V peak loss.

author: mbless
author_rank: Regular Contributor
timestamp: July 14, 2020, 01:43:19 pm
content: Quote from: David Hess on July 14, 2020, 01:05:34 pmYes, that is visible in the plots as the x-axis is relative to the input signal. The gate voltage starts to rise around 10ns, but the output voltage doesn't change until 20-30ns when the gate voltage is 5-11V. I'm not concerned with delay time since I'll be running low PRF, and it is low enough for my application.

author: mbless
author_rank: Regular Contributor
timestamp: July 14, 2020, 01:59:30 pm
content: Quote from: temperance on July 14, 2020, 01:22:59 pmI see it now! I needed to look at the output capacitance when it's on (Vds=0). Those numbers fit the turn-off trend well. And thanks for the reference material.

author: magic
author_rank: Super Contributor
timestamp: July 14, 2020, 02:23:21 pm
content: Quote from: mbless on July 14, 2020, 01:09:07 pmRemember that the voltage you see is not the "true" gate voltage but the voltage you applied to the outside end of a 7Ω parasitic resistor.If you add another 70Ω externally, you will probably be able to see something resembling the datasheet waveform on the transistor's pin.Quote from: mbless on July 14, 2020, 01:32:05 pmFact. But as I said, time constant is only some 6ns so perhaps it fits. You can see more of this effect on the high capacitance FQA, and I would say that the low capacitance Infineon part actually shows the most promising performance on average, except for the problematic bottom knee (top is actually quite nice).It also occurred to me that there is another issue: capacitance increases dramatically at low Vds, which causes a soft knee at the bottom end on both turn-on and turn-off edges. That being said, this effect alone would make the two edges mirror images of each other but the turn-off edge is much worse. It might be due to gate ringing aligning differently with each edge.In the future, it would be helpful if you posted the plots differently: Vgs and Vds of each FET overlaid on one image. That makes them easier to correlate and see what's going on.Perhaps the sharper top knee of FQP has something to do with the gate dipping down to -1V at about the same time?You should do the math and see if those curves fit the RC curve expected, or are worse, or (if such a thing is even possible) better.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 14, 2020, 03:17:07 pm
content: Note that I already cheated in just such an overestimate -- on the FQA, I went with 4nF because Ciss is about 2nF at high voltage and typically about doubles at low voltage (i.e., in saturation, when turned on). This forms a resonant tank between supply bypass cap, gate driver (which is a bit of resistance, and not much else), coupling cap and transistor, and the strays of all of these, and the PCB.It sounds accidental, but this is part of the actual circuit, and so it's not as much of an accident as it seems, that I put those two numbers together and got such good agreement.It's pretty scary actually, to have a loop like that, as part of the load supply. What happens if there's a load or source transient of more than a few volts? Pfsst...BANG!With a direct driver, the drive loop inductance can be much smaller, and most importantly, the mutual (shared) inductance between driver and load goes to single digits -- dI/dt will bemuchhigher, and Miller plateau will look as expected.And yes, that's the real Miller plateau I think -- you can also confirm it in a simulation with source degeneration inductance.Relevant story: I've made a converter that runs at 12V 20A, and used a current shunt resistor that added about 10nH to the ground return path -- even with beefy driver ICs and confirmed 20ns edges at the gatepins, the switching was still some slow 50ns or thereabouts, because it was entirely dI/dt limited. In the same way that you make a current source by putting resistance in the source return path, you make a ramp source by putting inductance in the source return path. Inductance kills, when it comes to switching!Tim

author: temperance
author_rank: Super Contributor
timestamp: July 14, 2020, 06:15:02 pm
content: Note that the miller plateau might not be visible or very hard to see at turn off because the drain voltage starts to rise much later because of the RC time constant. (50R with Coss) At turn, it should be very easy to see.Ringing in the gate driver can be solved by placing a ferrite bead + a small resistor in series with the gate. Something like this will work:https://www.we-online.com/catalog/datasheet/742792620.pdf

author: temperance
author_rank: Super Contributor
timestamp: July 14, 2020, 06:21:13 pm
content: Quote from: T3sl4co1l on July 14, 2020, 03:17:07 pmThat's not the miller plateau. The miller plateau can only be observed at the gate. But at turn off, you want see to much because Coss is being charged trough a 50R resistor.