USB power supply selector - Page 1
Forum section: electronics / projects

author: Starlord
author_rank: Frequent Contributor
timestamp: March 22, 2015, 09:50:40 am
content: Hey guys,I'm making some modifications to a schematic for a microcontroller that can be powered via USB or an external 5V supply (actually, it's the VIN pin and can be anywhere form 3.5-6V) and which can act as a host, and will need to supply 5V to devices (under these circumstances it will be assumed the user is actually supplying 5V to VIN).The microcontroller itself is powered via a 3V3 linear regulator supplied from the 5V rail, and its pins are not 5V tolerant. For this reason, you see there is a buffer in the schematic above.My question is... is that buffer necessary?If you remove the buffer, and you remove R34, then R10 should pull the gate of the PFET high by default, just as it is now. And if a USB B devices is connected, ID will be connected to ground, which will turn the PFET on and allow power to flow from the 5V rail to the USB device. And HOST_EN will be able to detect the state of ID without any need for level translation, since it is open drain.The only potential complication I can see here is that the PFET's gate will be floating until the 3V supply ramps up. And if VIN is higher than 5V, that could potentially allow the USB to be powered with more than 5V for for a few nanoseconds. But my gut says that 3V linear regulator is going to be so fast this isn't anything to worry about. Also, there's those varistors there which are supposed to protect against static shock and lightning strikes so I can't imagine 6V for a nanosecond is going to harm anything.

author: Starlord
author_rank: Frequent Contributor
timestamp: March 23, 2015, 01:37:19 am
content: Anyone?I just want to know why they used a buffer here when it seems like they shouldn't need one to turn the transistor off if 5V/Vin is powered, because there's a 3V linear regulator powered by the same rail, and 3V should be able to pull the transistor down just as easily and won't overwhelm the uC pins.

author: Starlord
author_rank: Frequent Contributor
timestamp: March 23, 2015, 02:51:32 am
content: > You can not use you MCU pin, unless it supports open drain output, because 5V-3.3V=1.7V, many fets will conduct at Vgs=-1.7V.This is the datasheet for that particular FET:http://www.nxp.com/documents/data_sheet/PMV48XP.pdfVGSth gate-source threshold voltage: -0.75V MIN -1V TYP -1.25V MAXIs that the relevant parameter? And does this mean that if Vgs < 0.75V that the FET will conduct?Also, that's only where it begins to conduct, right? It looks from the datasheet like it needs to reach around -4.5V when 2.4A of current is flowing for Rds to drop to the lowest point, and at -2.5V it's 0.75 ohms.This is an alternative I was looking at:http://www.onsemi.com/pub_link/Collateral/NTJS3151P-D.PDFBut it seems to be even more touchy, with a Vgs of ?0.40V.And it looks like it's happiest around Vgs -2.5V, going by the graph showing that the Rds doesn't go up as the amps increase.I just want to make sure I understand the parameters right.

author: Starlord
author_rank: Frequent Contributor
timestamp: March 23, 2015, 03:14:53 am
content: > According to your schematic, when its input is low, it pulls down. When its input is high, it goes high-z.> Which is to say, it is used as a npn transistor.Don't you mean PNP?When you pull the gate of an NPN down, it turns off. That would be high-z. Pull the gate high it turns on, connecting the drain to the source and therefore ground.http://www.electronics-tutorials.ws/transistor/tran_7.htmlIf I can use a PFET, then I think I can get two in a single package and then if I wire up the second one like how you said it would avoid the need for the buffer.

author: Starlord
author_rank: Frequent Contributor
timestamp: May 13, 2015, 03:42:21 am
content: I was just having another look on Digikey to see if I could swap that buffer for something cheaper, and I think I've got a problem.Almost all the buffers I looked at, whether they be open drain or the usual kind, appear to have outputs that aren't tolerant of voltages higher than Vcc when the output is LOW. In addition, input HIGH is usually Vcc * 0.7, which means I cannot power the buffer with 5V, while using 3.3V logic with it.So what gives?This is the datasheet for that buffer:http://www.ti.com/lit/ds/symlink/sn74lvc1g125.pdfIs the 52K pullup supposed to protect the output in some way? As far as I can tell it won't reduce the voltage the pin sees.How do I resolve this?

author: Starlord
author_rank: Frequent Contributor
timestamp: May 13, 2015, 03:59:32 am
content: Hm... I was looking at buffers before because they're cheaper than translators and they've always worked well for me, but I was always translating from 5V to 3.3V before. Now that I'm going in the other direction I took a look at some translators, and I found this part which is oddly similar to the buffer, but it has two power supply pins and looks like it would work in place of that other part:http://www.ti.com/lit/ds/symlink/sn74lvc1t45.pdf

author: Starlord
author_rank: Frequent Contributor
timestamp: May 13, 2015, 04:34:35 pm
content: I think I've found an even better an significantly cheaper solution.I didn't want to chain two NFETs together because it would require a less available more expensive (than a single transistor) dual transistor part, and more importantly it would require another pull up resistor which would add another part to my BOM and take up space.The dual NFET however was cheaper than the translator, so I looked to see if there was a way to use it without that extra resistor, and in the process I happened across this:http://electronics.stackexchange.com/questions/107382/use-bjt-transistor-as-a-switch-without-inverting-the-signalhttp://www.hobbytronics.co.uk/mosfet-voltage-level-converterAnd that looks perfect for my needs. In the current design when the uC pin goes high, the buffer goes open drain which allows the pullup on the 5V line to turn off the PFET. With this setup, when the UC pin goes high, the NFET turns off, and again, the 5V pullup is free to turn on the PFET.And when it goes low, it pulls the PFET's gate low and... wait. Isn't 5V still connected to my 3V uC pin through that resistor? I guess the 3.3V pullup (which I've changes to the same value) would reduce the voltage it sees to 4.15V but that's still too much for the uC pin.Is this circuit actually safe for 3->5V translation?