Sequential logic problem - Page 1
Forum section: electronics / projects

author: leonababy
author_rank: Regular Contributor
timestamp: April 02, 2022, 06:24:41 am
content: I haven't designed sequential logic in over 30 years, and I am having trouble seeing if what appears to be an easy problem has a solution.I have a circuit that has a zero crossing detector of the 60 Hz power line, and creates a 1ms pulse at each crossing. There is 60 Hz signal created from the 120 Hz signal on the rising edge of each pulse. I would like to create the signal named "Gate" in the diagram, which essentially is the inverse of the 120 Hz signal with every other pulse removed.If Gate has glitches from switching noise, it may be acceptable and a logic gate solution could possibly work. I would prefer a solution with flip flops but I am not seeing a solution. I always had a faster in-phase clock available when I did the designs I did, but in this case I don't have anything faster than the zero crossing output. I considered making an glitch edge detector for the rising and falling edges of 120 Hz but this would not be an elegant solution. Any advice would be greatly appreciated...Don

author: Ian.M
author_rank: Super Contributor
timestamp: April 02, 2022, 07:09:12 am
content: The problem is that your proposal has the 60Hz signal togging within the pulse you are trying to gate which inevitably leads to glitches.However if you clock the 60hz signal on the falling edge of the ZC pulse, it then toggles between pulses so can be used to gate the ZC signal without glitches. Additional gate delay from inverting ZC can only help the timing margins.A minimal implementation in CMOS logic might be a74LVC2G132dual Schmidt NAND to invert the ZC signal and gate the output, and a74LVC1G74single D flipflop, wired to toggle. The Schmidt inputs will help clean up the ZC pulse if it has slow edges but cant cope with a noisy falling edge that could cause the flipflop to double-clock. If that's a problem, a RC low-pass filter feeding the NAND wired as an inverter would help.See attachedLTspicesim for concept. Note: LTspice digital primitives disable unused input pins - this is *NOT true for real CMOS logic, so always tie to an appropriate level.

author: leonababy
author_rank: Regular Contributor
timestamp: April 02, 2022, 04:16:39 pm
content: Hi Ian. Thank you so much for your reply. As I was making breakfast this morning, my first thought was "I just need to delete every other 120 Hz pulse." As I went back, I realized the same thing you pointed out - the problem was these are both switching on the same edge. I then thought - what if I create a second 60 Hz wave, on the falling edge. After doing this, I came up with Gate = ~120 Hz + 60 Hz delay (see diagram). My original thought had Gate = ~120 Hz + ~ 60 Hz, which I believe would have glitches at the pulse to be removed. But with the 60 Hz wave created on the falling edge, I don't believe there will be any glitches - my Gate signal will just be affected by a few gate delays - which is not critical at all.So, I believe I identified the root of the problem the same as you have, but you gave additional tips for practical implementation. I very much appreciate your advice!Don

author: jmelson
author_rank: Super Contributor
timestamp: April 02, 2022, 04:41:53 pm
content: Feed 120 Hz into a NAND gate and 60 Hz into the other input of the NAND gate. If there are glitches, they will be VERY narrow, just a couple ns wide, the time it takes the FF to change state. If that is a problem, add an RC delay of a few ns to the 120 Hz before the NAND input. If the NAND is a CMOS gate, just put a 1 - 5 K resistor in series, the gate's input capacitance will be enough to create your RC time constant.Jon

author: RoGeorge
author_rank: Super Contributor
timestamp: April 02, 2022, 05:13:09 pm
content: I think this should do it. Please ignore the Vhigh level of 1V. It can be set to 5V as well.

author: Ian.M
author_rank: Super Contributor
timestamp: April 02, 2022, 05:28:51 pm
content: Yes, that's another variant of the circuit I and leonababy came up with. However needing three different ICs is somewhat sub-optimal,.Also you are fortunate that the LTspice A device flipflop is behaving itself without a propagation delay having been set. One usually has to settdappropriately in any logic using feedback, and once the propagation delay shifts the output transition away from a clock edge,tripdtis usually needed to persuade the simulator to use appropriate timesteps to resolve the transition.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 02, 2022, 06:07:39 pm
content: Yeah a flip-flop would do it. Do not forget to use either one with schmitt trigger clock input, or add a gate with a schmitt trigger input before it, because your zero-crossing detector likely has relatively slow transitions (and possibly noisy), and a typical flip-flop will require a certain max rise and fall time for its inputs, otherwise it may get into a metastable state.

author: Ian.M
author_rank: Super Contributor
timestamp: April 02, 2022, 06:12:39 pm
content: Yep. Schmidt trigger inputs are pretty much essential if the ZC signal comes from an optocoupler, due to its typically slow turnoff, as any significant noise while its in the transition region will cause multiple clocking. Here's a sim with filtering for a noisy falling edge. Remove the C and watch the flipflop double-clock.

author: inse
author_rank: Super Contributor
timestamp: April 03, 2022, 05:05:00 am
content: Just as a side note: can't you have a single rectified 60Hz signal and thus spare the flip flop?So you would only need a schmitt trigger and a monoflop, which all could be realised with a 74HC14.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 03, 2022, 05:23:53 am
content: The signal shown does not require any additional state, and can be derived using combinational logic only from the other signals shown (as jmelson first noted: X = A NAND B).Whether glitches might occur, is not indicated from the diagram (timing constraints are not provided, only lines implying synchronicity of edges). The original post suggests that glitches are tolerable, so the problem is solved.Glitches can be resolved with a more in-depth explanation of the signal sources, or if nothing else a bit of filtering.Also, if this is going into an MCU, the signals will be clocked sooner or later anyway -- even pin-change interrupts ultimately get read by the fixed-clock CPU. Some chatter might be desirable to avoid there (spurious interrupts can be quite troublesome), but some combination of these methods would seem to be adequate.If it's for an analog circuit (e.g. starting a variable monostable for thyristor phase control), the signal level may be adequate, or it will be latched anyway by the timer so does not need additional clean-up.I will note that, mains is often quite dirty, and so filtering should be done there, first and foremost, if at all possible. (This may introduce some phase error, though it may also be calibrated out in the digital signal path.)If other uses are envisioned, perhaps they can be explained, and a better-suited solution can be offered.Tim

author: leonababy
author_rank: Regular Contributor
timestamp: April 03, 2022, 07:12:36 pm
content: I appreciate the additional responses. Regarding glitches and a zero cross detector, yes, I discovered previously the importance of a Schmitt trigger buffer. I have two different zero cross methods I have found stable and acceptable - one with an HCPL3700 chip (1.3ms pulses), and the other a common opto-isolator solution (440us pulses). I found it was required for the first one and automatically used one in the second solution. Thanks again for the suggestions.Don

author: RoGeorge
author_rank: Super Contributor
timestamp: April 03, 2022, 08:09:47 pm
content: For zero cross detection, I made once this schematic. Worked very well, don't recall seeing any glitches.(By the way, the flip-flop schematic I attached assumes the 120Hz signal was already debounced and glitch free.)More details on the source website of the above pics:https://dextrel.net/dextrel-start-page/design-ideas-2/mains-zero-crossing-detector

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 03, 2022, 08:29:08 pm
content: Keep in mind your mains signal may be pretty noisy depending on what kind of loads are on the same line. And whatever filtering you add will have a time response. So you may get a clean zero-crossing detection, but lagging from mains.