AoE bad way to switch MOSFET from logic gate - Page 1
Forum section: electronics / projects

author: todorp
author_rank: Regular Contributor
timestamp: July 29, 2020, 03:24:06 pm
content: Hi, I have been plowing through the FET chapter in AoE 3e. When talking about MOSFET switching the following is given as a bad example:The text says that if the MOSFET were IRF740 for example, with feedback capacitance of around 200pF the output would be approximately switched on in 50us.There is a very similar example in AoE 2e:In this case they take as an example an 2N6763 with avergare feedback capacitance of 350pF. The approximate switching time in this case is given as 20us.How are these approximate switching times calculated?Thanks a lot,Tod

author: temperance
author_rank: Super Contributor
timestamp: July 29, 2020, 04:39:11 pm
content: An out of print but excellent book:https://archive.org/details/bitsavers_siliconixdixMOSPOWERApplications_38092918Chapter 3.9 (page 112 in your PDF reader)

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 29, 2020, 07:46:33 pm
content: No idea where they get 1mA from, CD4000 gates at 10V are about 600 ohms output, or about 15mA short circuit and decreasing towards the rails.IRF740 is about 15nC over the Miller step, for a typical load and voltage swing; from 10V that's 1.5nF equivalent capacitance. (The instantaneous capacitance is much higher, because of how Miller effect works.) 600 ohms * 1.5nF = 900ns, about a microsecond.Probably similar for the 2N6763 and a bit slower(?), but it's so old they didn't even rate it in terms of Qg so it's hard to say. They do give switching times at R_G = 4.7 ohm; at 600 ohms it would probably be closer to 12.7us (using the same method for IRF740, gives 1.8us).Note this is just for the largest part of drain voltage swing, but also weighted towards the bottom (low Vds), where Cgd is largest. The capacitances are varying all throughout this process, so you can't draw a straight line through anything and say that's the answer.Because Vgs isn't varying exponentially like it would for a constant capacitance, the gate voltage timing differs for rising and falling edges, and for reactive loads (capacitive loads draw lots of drain current when the drain voltage is changing rapidly; inductive loads drop lots of drain voltage when drain current is changing rapidly). And in turn, drain voltage.A precise answer is basically up to measurement, or simulation, given a sufficiently accurate model (which isn't always the case from the manufacturer).Because of this, the design process for MOSFETs uses a guard-band approach: if we need a certain rise/fall time, then use Qg(tot) / Vgs(on) = Ceff, and the driver resistance (or current), to determine gate rise/fall time. Drain rise/fall will be about half that figure.Tim

author: todorp
author_rank: Regular Contributor
timestamp: July 30, 2020, 09:08:11 am
content: @temperance - thanks for the link. That is indeed a very detailed explanation. I was hoping for something more "back of the envelope" but I will try to do the calculations following the Siliconix doc and see if I get more or less the same results as AoE.@T3sl4co1l - I think they used 1mA only as an example for a low output current capability source. In AoE3 there is a footnote that uses Qg = 40nC producing a switching time of 40us (vs 50us using the "other unknown to me method").Here is what the text in AoE3 says about this (my apologies for the blurry image):Hope it is not a problem posting small extracts from copyrigh protected books on the forum ...Thanks again,Tod