looking for a VHDL code driver for RGB-S/PAL timings - Page 1
Forum section: electronics / general

author: legacy
author_rank: Super Contributor
timestamp: December 13, 2014, 01:52:19 pm
content: hii ve got an LCD which is RGB-S/PAL timings, i'd like to interface with an fpga in order to realize a very easy VDU (video display unit), limited to "text" console.i have realized something like but for VGA, never player with PAL timing before, so i am looking for documentation and a piece of example of VHDL code.the LCD has the following signalsLCD_enable, digital inRed, analog inGreen, analog inBlue, analog inS, synchronism, digital in (not clear how sync_H and sync_Y are mixed together (1))thank you in advanceedit:Separate sync: Uses separate wires for horizontal and vertical synchronization. When used in RGB (i.e. VGA) connections, five separate signals are sent (Red, Green, Blue, Horz. Sync, Vert. Sync)Composite sync: Combines horizontal and vertical synchronization onto one pair of wires. When used in RGB connections, four separate signals are sent (Red, Green, Blue, Sync) <---- this is my caseSyncliterally means the "synchronization" of lines on the screen. Basic composite video (that yellow cable you used to plug into your TV) carries all of the video information (all of the colors combined), as well as thesyncinformation to your TV. RGB signals separate the colors into their own channels (Red, Green and Blue) and carry both the horizontal and vertical sync information in it’s own separate channel called "composite sync" (totaling 4 channels). This is called "RGB-s" (1)

author: marshallh
author_rank: Unknown
timestamp: December 13, 2014, 08:27:15 pm
content: Get a copy of the ITU specs.Best reference book ishttp://www.amazon.com/Video-Demystified-Handbook-Digital-Engineer/dp/0750683953

author: Scrts
author_rank: Frequent Contributor
timestamp: December 13, 2014, 09:34:04 pm
content: Do you have a specification? At least a resolution? Many LCDs these days doesn't use VSYNC and HSYNC. There's DE (Data Enable) used instead of that, which is a combination of VSYNC and HSYNC. When DE is asserted, the incoming data is treated as active data, when DE is deasserted, then it means that it's the blanking area going.

author: miguelvp
author_rank: Super Contributor
timestamp: December 13, 2014, 09:54:06 pm
content: His sync is a composite sync should be easy to do that in VHDL/Verilog.Timings are a bit different than NTSC but not by much, there are plenty of examples for PAL drivers for FPGAs out there. It's just 625 lines instead of 525 and 50 Hz instead of 60 Hz.As for the synch, drive it low for each of the horizontal syncs and also during vertical sync.Since you don't have to deal with the full composite signal the hue differences between NTSC composite and PAL composite won't affect you at all because you are using analog RGB signals.Analog impedance is 75 Ohms the same as in NTSC.Edit:A random example link:http://papilio.cc/index.php?n=Playground.TVOutputWingTo look at the timings, not the generation since that one does the full composite.

author: legacy
author_rank: Super Contributor
timestamp: December 13, 2014, 10:50:15 pm
content: SONY PSone LCDQuote from: Scrts on December 13, 2014, 09:34:04 pmThe LCD Screen is 5" diagonally, PAL timing.herea guy has written something about timing specifications, but he wanted to interface the LCD to a VGA driver, and he is using an XOR+RC circuit.vga2rgb-s

author: legacy
author_rank: Super Contributor
timestamp: December 13, 2014, 10:53:11 pm
content: Quote from: miguelvp on December 13, 2014, 09:54:06 pmyes, it isQuote from: miguelvp on December 13, 2014, 09:54:06 pmgoodQuote from: miguelvp on December 13, 2014, 09:54:06 pmok

author: legacy
author_rank: Super Contributor
timestamp: December 13, 2014, 11:18:35 pm
content: thepapilioPlayground.TVOutputWingseems to have a lot of good documentation, exactly what i needthank you guys

author: Stonent
author_rank: Super Contributor
timestamp: December 15, 2014, 09:16:55 am
content: You just need an LM1881 chip to separate the sync for you.http://www.ti.com/lit/ds/symlink/lm1881.pdfI built this circuit about 15 years ago when I wired my playstation1 into an RGB arcade monitor. No FPGA needed.http://www.gamesx.com/misctech/lm1881.htm

author: legacy
author_rank: Super Contributor
timestamp: December 15, 2014, 11:38:56 am
content: Quote from: Stonent on December 15, 2014, 09:16:55 amthe problem goes into the opposite direction: i already have a working and tested vhdl code for VGA (it's a VDU driver, text console), which has Vsync and Hsync, and i have an LCD which is RGB-S, so it needs Vsync and Hsync mixed together as "composite synchronism", and that is the problem: how to make it in fpga ?the schematic above uses XOR and RC, and i am not sure about this solution, also i have not understood it

author: Scrts
author_rank: Frequent Contributor
timestamp: December 15, 2014, 02:13:17 pm
content: Maybe try to simulate with some kind of Spice?Anyway, do you have to provide analog signals to the LCD module?

author: legacy
author_rank: Super Contributor
timestamp: December 15, 2014, 03:14:07 pm
content: Quote from: Scrts on December 15, 2014, 02:13:17 pmmay be someone knows the rgb-s or has any good documentationQuote from: Scrts on December 15, 2014, 02:13:17 pmoff course, and it is not a problem, i have 3 DAC attached to my fpga.

author: Scrts
author_rank: Frequent Contributor
timestamp: December 16, 2014, 09:30:27 am
content: Go with the provided schematic then. It's a single chip with 4 XOR gates, two transistors and some passives - nothing really fancy and won't take a huge area on a small PCB. Try to do it on the breadboard first, but it could introduce additional capacitance, which you may not want.