Example circuit seeked - Power On initial value - Page 1
Forum section: electronics / beginners

author: bitman
author_rank: Unknown
timestamp: July 18, 2017, 03:37:56 am
content: Very short - I'm looking for example diagrams that shows how a counter would be loaded with a value other than 0 on "reset". I'm looking at a delayed pulse on power on to hit reset, and then a second pulse to load a value. I'm looking for example diagrams that would do that with simple latch circuits. Another key feature is that manual reset should trigger the same form.

author: SL4P
author_rank: Super Contributor
timestamp: July 18, 2017, 05:13:11 am
content: Much more info needed.Hardware reset, and parallel loading of a counter chip is easy enough, but if the counter is any more complex, you're probably going to better off with a single-chip uC solution.What does the counter have to do after it has. even pre-loaded?

author: bitman
author_rank: Unknown
timestamp: July 18, 2017, 05:37:40 am
content: Quote from: SL4P on July 18, 2017, 05:13:11 amIt probably will change, but right now several 74161 - probably will end up with some 74594 if I can find some (I need 16 bits). Is a simple 555 or slightly similar circuit that produces a delayed single tick the way to do it? I'll probably need a tri-state buffer too since the input is shared with a bus. I actually realize I have a few areas that would need a controlled setup on power-on so I'll probably have to really think this through. Hence, looking for circuits to illustrate how this has been done before.

author: Benta
author_rank: Super Contributor
timestamp: July 18, 2017, 07:48:02 am
content: 74161 won't work for this, you need a counter with asynchronous load.

author: SL4P
author_rank: Super Contributor
timestamp: July 18, 2017, 08:14:42 am
content: Are all the units going to have the same preset value?I'm still thinking a uC may be. a cheaper, simpler solution.what sort of initial value are you using?I'm assuming the counter counts down on some clock input signal - to trigger an output when it reaches zero?

author: Benta
author_rank: Super Contributor
timestamp: July 18, 2017, 09:01:22 am
content: The CD4526/MC14526 will do this for you with no trouble. It's a "down" counter, though.

author: danadak
author_rank: Super Contributor
timestamp: July 18, 2017, 10:36:51 am
content: Some questions -1) Max clock rate for counter2) Counter width3) 3.3V or 5V system4) Preset value a constant or a variable, if latter source of value5) Do you need to know when counter reaches a certain value6) What do you want to do with counter value, read it periodically,send it serially to another device, display it.....Regards, Dana.

author: rstofer
author_rank: Super Contributor
timestamp: July 18, 2017, 02:19:09 pm
content: What's the big picture?Is there any sequential component to what you are building? If so, dedicate the first or second state to setting counters and such.

author: bitman
author_rank: Unknown
timestamp: July 19, 2017, 01:30:53 am
content: Here’s what I’m aiming at: a 16bit Program Counter using TTL. Since the counter is connected to an 8 bit bus I need to be able to address HI/LO sperately which isn’t an issue.I need the PC to reset at a high address (MSB set – all others reset). This is required due to the memory I’m using. Right now I have 4 – 4bit counters, so I’m just looking at doing this load on one of the chips, but as I mentioned earlier I’m looking at 8 bit counters to see if they’ll do better.Because the input is connected to the bus, I’m trying to come up with a design that allows me to load values outside the bus. Just pulling the line to 0 will cause issues with other chips/data-bits on the line. So I think I need a tri-state buffer – still testing.I need to be able to load addresses from the bus (jump). To each counter must be able to take a value from input. I also don’t need to count down, just up.1) Max clock rate for counterThis is meant to be shown so the clock rate can be quite low. However I currently use a 200ns pulse to coordinate with. I don’t expect to ever run this at higher rates that 4MHz – probably closer to 1MHz but technically I can run it at 4Mhz given my current setup.2) Counter widthNot sure I get exactly what you mean. I would like the reset/change to happen as soon as possible, so I’ll take the “ready” parameters from the chip into account. Right now I was thinking of using 200ms of a delay on power-on – it may even get to 500ms – not sure yet. There’s no real rush. But the pulse is just 200ns wide.3) 3.3V or 5V system5V – some of the chips I have can only do 5V so I’ve kept that constant through the whole setup.4) Preset value a constant or a variable, if latter source of valueJust need MSB set post-reset/PO. Everything else should remain at 0.5) Do you need to know when counter reaches a certain valueNot in this circuit – and not directly. When the value gets to the max (if that happens) I would simply have it swap to 0. It’s unsigned and pretty straight forward.6) What do you want to do with counter value, read it periodically,send it serially to another device, display it..…Yes. This value is definitely read often using a bus to read values from memory into an instruction register. The clock to this chip is controlled by the instruction set so not every clock pulse will result in a count.Question: What's the big picture?See above. A basic Program Counter (PC).Question: Is there any sequential component to what you are building? If so, dedicate the first or second state to setting counters and such.The PC is sequential? Other than the cases where a value is directly loaded into the register it just counts up.I wanted 16 bit because I wanted to struggle with some of the 8/16 bit conversions that comes out of that.Note – the memory has a EPROM on the high addresses – by setting the address to the initial address of the EPROM I can boot the system on power-on. Hence the need to set a value on power-on.

author: rstofer
author_rank: Super Contributor
timestamp: July 19, 2017, 02:20:30 am
content: Suppose you exclusive-or the high bit with a D-flop that resets (use capacitor on reset input). Use the Q' output. So, if the counter resets to 0 and the D-flop is reset, the XOR will be '1'. Somewhere in the code, you clear the D-flop. Or, maybe you clear it on some address condition. This isn't a very satisfactory solution.The way this is usually done (according to me and my projects) is to have a shadow memory at 0x0000 that is in the memory map and copies the monitor code (also in the shadow memory) to high memory. The addresses within the monitor code are those of the destination address while the copy code is ORG'd at 0x0000. The very first thing the monitor code does when entered is change the memory map to get rid of the startup code and map in RAMl.A variation has the monitor code in PROM at the proper high address and only a JMP MONITOR instruction is mapped in at startup. This is probably easier but you wind up stuck with the monitor code unless you can map it out. I have done this when I know the system will run CP/M because I know where the entry point will be and I simply need to branch there. I think the JMP MONITOR instruction could be set with dip switches (flexible) and gated onto the bus instead of RAM by some kind of D-flop or whatever.

author: bitman
author_rank: Unknown
timestamp: July 19, 2017, 11:42:45 am
content: Quote from: rstofer on July 19, 2017, 02:20:30 amThanks - this has me thinking. I wonder if a simple XOR will work for me - I have to think that through. As to the rest, I'm not sure we're seeing the same problem - the Power On starts with no data what so ever, fake/simulated or otherwise. I have a ROM (created with EPROM) that I need to be addressed when the code starts, and in there I'll be doing some of the "tricks" you're talking about. But I need to get the reset to start at the right address first.Thanks again. It surely has given me plenty to think about.

author: rstofer
author_rank: Super Contributor
timestamp: July 19, 2017, 01:51:31 pm
content: No, you don't need to start at a non-zero address, you just need to JMP to the address. But you do have to be able to cleanly start from 0x0000.Suppose, by default, all RAM is mapped out of the memory space (it's CE' is held high somehow) and the PROM is mapped into the memory space at a high address, where it belongs. Further, assume that a buffer for a 16 bit dipswitch is mapped into memory space at every address except the PROM area. In other words, use very little address decoding, just enough to keep the dipswitch from colliding with the PROM. That dipswitch contains the full instruction to JMP PROM. The first thing the PROM code does is switch the memory map to get rid of the dipswitch and enable the real RAM.You could also change the memory map automatically after the jump by noting that a MemRd' occurs with a high address bit set.Here's another way: Map the PROM into memory at both the high and 0x0000 address. The first instruction in the PROM jumps to the next instruction but in the high memory location. Either this second instruction or the MemRd' at a high address maps the PROM out of the low address space.You will probably want to be able to map the PROM out of the address space as well. But that's a side issue.

author: bitman
author_rank: Unknown
timestamp: July 19, 2017, 05:00:40 pm
content: Quote from: rstofer on July 19, 2017, 01:51:31 pmI'll admit resetting on restart to 0x0000 is by far the easiest but I'm not sure why I HAVE to start there? It's a lot easier to map modules of code by using high bits to differentiate the different segments (that could be display etc).QuoteThis section really has me confused. If I use CE and have overlapping chip addresses, how do I copy/initialize RAM values from the PROM addresses? I would have to have special OP codes that toggles the CE moving a single byte at a time? All the PROM is going to do is load data from an "external" source into RAM and execute it.QuoteIf I understand the process you're laying out, here's what you're doing:1) PO - delayed RESET, PC=0x00002) PO -> CE => CMOS3) CMOS 0x000: JMP 0x80034) Clear CE for CMOS, Enable CE for memory module(s)?Not sure how I can make the CMOS addressable at both addresses?QuoteSeems to be a lot of work instead of just "hardcoding" the RESET to address a different value?QuoteThe PROM is much smaller memory space wise than the RAM. What I want to do is to load code faster than toggling switches from now to kingdom come on every PO.

author: rstofer
author_rank: Super Contributor
timestamp: July 19, 2017, 06:37:14 pm
content: Since I like the last approach the best, I'll try to expand upon the idea:Suppose you have a PROM and the first couple of instructions look like this:Code:ORG 0x0000 ; this is what the CPU thinks it seesJMP Start ; at address 0x0000 a 3 byte jump to 0x8003 in 8080 talk this is C3 03 80; note that this instruction also exists at 0x8000ORG 0x8000JMP Start ; this is the exact same instruction that is ORG'd at 0x0000 C3 03 80Start: ; at address 0x8003 is the first instruction of the monitor... < this is the starting point for the monitor.When you create the PROM, ignore the stuff at 0x0000 and just assemble and burn the code that starts at 0x8000. That JMP instruction works from either address since it is a direct jump to an address.Now, the address decoding for the PROM is to normally involve the high address bit (or some combination of bits) so you need to include the output of a D-flop that is automatically reset at startup (or by a reset signal/switch). Simultaneously, you need to include the output of the flop into the CE' logic for the RAM. Bottom line, when the D-flop is cleared at reset, the RAM disappears and the PROM shows up at both 0x0000 and 0x8000. When the flop is set, RAM shows up at low addresses and the PROM still shows up at 0x8000.Now, after the JMP Start instruction following reset, your CPU will be headed off to 0x8003 (assuming 3 byte JMP instruction like the 8080). The PROM is ALWAYS mapped into 0x8000 so the state of the D-flop is irrelevant.Finally, now that we have actually entered the PROM at 0x8003, we need some way to set the D-flop to enable RAM and disable the mapping of the PROM at 0x0000. One way to do this is to notice MEMRD' with the high bit of the address = '1'. We always SET the flop so the D input should be a solid '1'. The only thing that resets the flop is the reset signal. This will come from the RESET toggle switch and/or a capacitor on the R input. Whatever it takes to guarantee the flop is reset at startup.Short answer, the PROM shows up at 0x0000 long enough to JMP to 0x8003 and gets mapped out of low memory as soon as the first byte is read at 0x8xxx.ETA: This approach assumes that the CPU will cleanly start at 0x0000 (pretty easy to force a reset on the PC) and that MEMRD' is clean at startup so the D flop doesn't get set prematurely. The advantage to this approach is that it doesn't play convoluted tricks with the address signals (inverting and such) that ultimately need to be unwound.ETA: That JMP Start instruction will only be executed at 0x0000, never at 0x8000 because we have already jumped over it and are working at 0x8003. Looks strange but it works. Make sure to comment it because it looks like a stupid instruction. Why JMP to the next sequential address? Yup! I can simplify that code right out of here! Something like that...

author: rstofer
author_rank: Super Contributor
timestamp: July 19, 2017, 08:56:32 pm
content: So, I messed around with a truth table and here's what I get when using A15 to select the PROM (that is, the PROM occupies ALL of high memory.A15 Q CE' -- assume Q is the D-flop output which starts reset0 0 0 -- here we are noting that the D-flop is reset and we should map the PROM0 1 1 -- here we have the D-flop set but PROM CE' doesn't go active because A15 is 01 0 0 -- A15 is a 1, select the PROM regardless of what the D-flop is doing.1 1 0 -- dittoThis comes down to AND(A15',Q) which is easy to create with a NOR gate NOR(A15, Q'). That's neat because the D flop will have a Q' output. One NOR gate ought to cover it.The CE' for RAM is simply the inverse of the CE' for the PROM so use another NOR gate (or just an inverter if you have one) and just invert the PROM CE'. This makes sense because we only have a choice of PROM or RAM when we access memory and if the address/D-flop aren't selecting the PROM, they should be selecting the RAM.Then we have to come up with a way to set the D-flop. One way might be to clock it with some combination of MEMRD' and A15 (see below), hold the D input to '1', pull the Set input high and tie the Reset signal (capacitor,switch,reset signal) to the Clr input. Then clock the flop to 1 when the first MEMRD' comes along addressing A15 = 1.A15 MEMRD' Clk'0 0 10 1 11 0 0 -- Clk goes low when MEMRD' goes low and A15 is high.-- Q changes on rising edge of MEMRD'1 1 1Let's redraw it with MEMRD' inverted, call the signal MEMRDA15 MEMRD Clk'0 0 10 1 11 0 11 1 0 -- Clk goes low when MEMRD goes high and A15 is high.'-- Just a NAND gate (plus inverter)So, Clk = NAND(A15,NOT(MEMRD') and a NAND gate plus an inverter (or spare NAND or NOR gate) will get it done.I guess it would be fair to mess around with the equations to see if they could all be generated with either a quad NAND or quad NOR. I didn't do that...