What does the circles in the logic circuits mean? - Page 1
Forum section: electronics / beginners

author: MrOmnos
author_rank: Frequent Contributor
timestamp: July 24, 2016, 08:47:28 am
content: I know those circles in the circuits mean 'Not' but when they are used everywhere like in the above circuit, it gets really confusing for me. Can anyone explain it to me, how to properly decipher those circles? Does the circle in the input mean it takes 0 as a value or does it mean the value is being flipped? Every time I see a circle do I need to flip the values?How does it work?Edit: For some reason, Image is not being displayed, so have added an attachment.

author: German_EE
author_rank: Super Contributor
timestamp: July 24, 2016, 08:53:22 am
content: A circle on an input means that it is active low, you may also see the pin name with a line drawn above itA circle on an output means that either the output is active low or that the logic gate is inverting. So, if you see the circle on an AND gate then it becomes a NAND and with both inputs high the output will go low.

author: MrOmnos
author_rank: Frequent Contributor
timestamp: July 24, 2016, 09:26:17 am
content: Quote from: German_EE on July 24, 2016, 08:53:22 amSo for an active low input, if the the input is high, does that mean I need perform the inverting operation?

author: Kilrah
author_rank: Unknown
timestamp: July 24, 2016, 09:29:55 am
content: If an input is active low it means the gate will consider it active when it's low instead of high - What do you think you "need to perform"? That would depend on your circuit and what you want to do...

author: ebclr
author_rank: Super Contributor
timestamp: July 24, 2016, 10:05:13 am
content: In simple way a circle is a inverter including on the output0 = 1 if pass on a circle0 = 0 without circle

author: tatus1969
author_rank: Super Contributor
timestamp: July 24, 2016, 11:47:38 am
content: all you need to do is count the circles in a signal path. If the result is an even number, then you can cross out all the circles/inversions. Keep in mind that every two inversions cancel themselves. If the result is odd, then the signal is inverted on its way.Applying this to your picture means that IOADR, IOW, IOSEL go through directly without being inverted, and the gate just before the latch is actually a regular AND.

author: ebclr
author_rank: Super Contributor
timestamp: July 24, 2016, 11:55:17 am
content: the afirmation 2 circles cancels itself is only 90% true, because this will add a delay, and in some circumstances will give you unexpected results

author: tautech
author_rank: Super Contributor
timestamp: July 24, 2016, 12:22:38 pm
content: Have a play around here:https://tams.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/chapter.html

author: tatus1969
author_rank: Super Contributor
timestamp: July 24, 2016, 12:33:20 pm
content: Quote from: ebclr on July 24, 2016, 11:55:17 amsure, and the circuit above does not use any clock synchronization although the decoder inputs have different delays. Consider a write to address 00, followed by a read from address 01. A0 is faster than /WR, which could already trigger that latch. But the question was basic logic diagram understanding, so I didnt want to go into all this.

author: tggzzz
author_rank: Super Contributor
timestamp: July 24, 2016, 12:38:07 pm
content: Quote from: MrOmnos on July 24, 2016, 08:47:28 amThe technique is used to simplifyunderstandingof andreasoningabout a circuit by showing itslogicalfunction. Do not confuse thelogic valuewith thevoltage.If thereisn'tcircle on a pin then it means that the logical value "1" is with a high voltage (often, but not always, near the power supply rail).If thereisa circle on a pin then it means that the logical value "1" is with a low voltage (often, but not always, near zero volts).Thuswhere there is a circle on an output connected to a circle on an input, the two "cancel out", e.g. the active-low IOSEL, IOADR and IWR signals in your example.It is fast and easy to see that the latch is IOSELected when there is an IOWrite AND the IOADDress is correct.

author: helius
author_rank: Super Contributor
timestamp: July 24, 2016, 01:02:18 pm
content: Unless I'm missing something, you can trace a signal through the circuit and each circle will invert it once. The basic gate symbols are AND and OR: circles around them modify their meaning. If you think of each gate as a sentence of first-order logic (Boole's calculus), the basic gates are Output = (AND w x y z...) respectively Output = (OR w x y z...)Gates can have arbitrary numbers of inputs but just one output. The AND/OR gates correspond to saturating arithmetic, too: OR is like the + operator, its output is positive (1) when any of its inputs are 1; AND is like the * operator, its output is positive (1) only when all of its inputs are 1. A circle on the gate's output makes an AND into a NAND gate and an OR into a NOR gate. Their Boole sentences would become Output = !(AND w x y z...) respectively Output = !(OR w x y z...)NAND means NOT AND, but also means NOT EVERY input is true. NOR means NOT OR, but also means NOT ANY input is true.Circles on all of a gate's inputs turn an AND into a NOR, turn an OR into a NAND: this is called De Morgan's Law in logic. The sentences are (AND !w !x !y !z...) = !(OR w x y z...), respectively (OR !w !x !y !z...) = !(AND w x y z...)So armed with the above knowledge, we can tell that the gate in the middle, that has /IOADR and /IOW as inputs and /IOSEL as output, is actually an OR gate. Its output will be 1 (high) if either /IOADR OR /IOW is high, and 0 (low) only if /IOADR and /IOW are both low. These signals are active low, which simply means that the condition we are interested in is in effect when the signal is 0, and not active when the signal is 1.The whole graph is telling us that the latch will be enabled if and only if the Address bus is 10000000, (A0 is 1 and [A1:A7] is 0), IO/M is 1 (meaning IO is active and not M), and /WR is 0 (meaning WRite is active, a write cycle is taking place).QuoteThis is an incorrect application of De Morgan's Law. The gate is an OR, not an AND.

author: tatus1969
author_rank: Super Contributor
timestamp: July 24, 2016, 01:40:41 pm
content: Quote from: helius on July 24, 2016, 01:02:18 pmWith "applying this" I meant to remove the inversions before and after, not applying DeMorgans Law. As you said yourself in your post:Quote

author: Brumby
author_rank: Unknown
timestamp: July 24, 2016, 01:55:26 pm
content: Quote from: MrOmnos on July 24, 2016, 08:47:28 amIn simple terms - YES. Every time you see a circle, think of it as an inverter.If there is a circle on theinputof a gate, invert the signal andthenperform the gate operation.If there is a circle on theoutputof a gate, find the result of the gate operation and then invert the signal.Some of the comments given above relate to advanced handling, but this is the basic concept.There is a whole subject on how to wrangle this stuff on paper. It's called Boolean Algebra. With it, you can take a complex set of logic gates and simplify it - sometimes to a ridiculously simple set of gates that is completely unintuitive. Sometimes not. Be aware that Boolean algebra does not take into consideration any physical characteristics of logic gates such as propagation delay.

author: tggzzz
author_rank: Super Contributor
timestamp: July 24, 2016, 03:29:40 pm
content: Quote from: Brumby on July 24, 2016, 01:55:26 pmThat reasoning is unnecessarily confusing when you have an active low signals, as in the OP's example.

author: Brumby
author_rank: Unknown
timestamp: July 24, 2016, 03:46:33 pm
content: It's not reasoning. It's definition.I make NO inference on a signal being "active" or otherwise. That comes down to function - which is the next step AFTER the signal level is determined.The OP asked about the function of the circle ... NOT the operation of gates, active states or other "hints and tips" - just the circle. That's what I answered.Once they are comfortable with that, THEN they can move on to the functional aspects - which is what everyone else seems to be talking about.

author: zapta
author_rank: Super Contributor
timestamp: July 24, 2016, 03:54:32 pm
content: The diagram in the original post is misleading. Here is a more intuitive one with the latch enable text inside the box, before the negation.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 24, 2016, 04:18:00 pm
content: Read it exactly as it says:"When all these inputs are low, AND this one is high, \IOADR becomes active. When IO/\M is IO, AND \WR is active, set \IOW active. When \IOADR AND \IOW are active, set \IOSEL."If you like, use De Morgan's theorem -- an active-low AND is an active-high OR, and vice versa. But this won't clarify the circuit, because ORing active-low signals doesn't follow from the statement being made: when the address is correct AND IO is being written, enable the latch.The circle simply tells you that the output from a function (such as AND) is active-low. That is, only when the function becomes true, the output becomes low.All the "inside" signals (IOADR, IOW, IOSEL) could be created as active-high (in which case the latch would need an active-high type enable, or an inverter to convert it to active-low), and the circuit would read the same -- however, these type of signals are active-low for traditional reasons, so that's why it's been written this way.Tim

author: klunkerbus
author_rank: Unknown
timestamp: July 24, 2016, 04:25:55 pm
content: If we start nitpicking the schematic, I would have shown the inversion circles on the left side of the A1 to A7 inverters, since the IOADR gate is looking for the case where A1 to A7 are all low. I would locate the latch enable input on the left side of the latch, not at the bottom where I'd normally expect to see a reset pin. I *might* show circles on the outputs of the latch, since that is the active state that turns on the LED, but then adding the inversion circles on the latch inputs for consistency starts distracting the design. And oh, I wouldn't show VCC shorted to ground over by the LEDs.But on a more serious note, back in the day where combinatorial logic was a necessary part of almost every circuit design, I used to prefer this functional representation of logic, and encouraged new engineers on my design projects to do the same. It helped with understanding what the logic was supposed to do - especially helpful in the case of an independent design review or when bringing in a tiger team to troubleshoot a design. EDIT: This is going back in time as well, but IIRC having the functional representation of the logic also helped minimize errors in transferring the design into PAL/PLD software like ABEL.

author: tggzzz
author_rank: Super Contributor
timestamp: July 24, 2016, 04:30:05 pm
content: Quote from: klunkerbus on July 24, 2016, 04:25:55 pmPrecisely.

author: zapta
author_rank: Super Contributor
timestamp: July 24, 2016, 05:25:45 pm
content: Quote from: klunkerbus on July 24, 2016, 04:25:55 pmInverters of a 6-pack IC will have different symbols based on the context of their usage? How does this work with standard libraries?

author: ebclr
author_rank: Super Contributor
timestamp: July 24, 2016, 07:00:01 pm
content: Inverter have exactly the same simbolA triangle that is a buffer and the circle that is the inverter

author: klunkerbus
author_rank: Unknown
timestamp: July 25, 2016, 01:54:00 am
content: Quote from: zapta on July 24, 2016, 05:25:45 pmMy insight is dated, but it all depends on the schematic capture software and whether alternative views were defined for the part when it was added to the library. Inverters and combinatorial gates that have no shared pins like a clock, reset or enable would typically be used in the schematic individually, not as a block. On more complex logic like octal registers and buffers with shared pins, yeah, you may not have much flexibility in how that device is shown on the schematic.

author: ebclr
author_rank: Super Contributor
timestamp: July 25, 2016, 04:24:37 am
content: This have nothing to do with software this is a ieee standardhttp://www.ddpp.com/DDPP3_pdf/IEEEsyms.pdf

author: bitslice
author_rank: Frequent Contributor
timestamp: July 25, 2016, 01:11:40 pm
content: I find input bubbles a bit confusing and the IEEE way of doing it a complete 'mare.

author: tggzzz
author_rank: Super Contributor
timestamp: July 25, 2016, 02:21:44 pm
content: Quote from: bitslice on July 25, 2016, 01:11:40 pmIt is easy and easier if you think of twocompletely independentconcepts:thelogic operation, i.e. and, or, exor. Just draw the symbol indicating yourdesign intention, not yourimplementationthelogic true voltageof the input/output signals. Just add circles if the signal is logically true with a low voltage. If logically true with a high voltage, omit the circlesHence if your design intention Z is "signal X AND signal Y", where Y is true with a low voltage, then draw an AND gate with a circle on the input driven by the Y signal. Similarly, if X is true with a low voltage, draw a circle on the input connected to the X signal.

author: bitslice
author_rank: Frequent Contributor
timestamp: July 26, 2016, 11:26:16 am
content: ^ yep I can see that there will be different ways of approaching a problem and bubbles probably suits a larger scale design, and probably more like how chip designers think.I've always looked if any complex TTL IC will do the job more efficiently, then looked at what logical operations to do on the incoming signals, then inverted the logic to suit an implementation.Certainly from a testing viewpoint I reckon it's easier to not care what the design is supposed to do, but simply to see if what goes in relates to what is actually coming out.

author: Galenbo
author_rank: Super Contributor
timestamp: July 29, 2016, 09:43:56 am
content: Quote from: MrOmnos on July 24, 2016, 08:47:28 amLike said before, yes, and be aware of timing too.You can see those circles in places where you think they arenot necessary, and that can have multiple reasons.For example: Sometimes a signal has to amplified/buffered/limited/filtered, and an easy way is/canbe to use an unused NAND port that is present anyway.But now the signal is inverted? No worry, that's easily solved in software or port settings.