Hey guys, I just finished designing my first board. Could I get a once over? - Page 1
Forum section: electronics / general

author: thomasb9511
author_rank: Contributor
timestamp: March 12, 2016, 06:00:29 am
content: Don't be too harsh esp. if I broke some design rules.

author: Rerouter
author_rank: Super Contributor
timestamp: March 12, 2016, 06:05:41 am
content: how about post some images, for those of us not using eagle, e.g. top and bottom layer,

author: thomasb9511
author_rank: Contributor
timestamp: March 12, 2016, 06:22:16 am
content: Top copper layerBottom layerSchematic

author: Skimask
author_rank: Super Contributor
timestamp: March 12, 2016, 06:25:50 am
content: You could place a few more ground plane stitching vias to extend the ground plane to those blank areas and make more filled ground.And you've got plenty of room to fatten up every one of those traces rather than using the minimum trace widths. Same with the clearances.And better add a few more decoupling caps across Vcc and GND.

author: thomasb9511
author_rank: Contributor
timestamp: March 12, 2016, 06:41:26 am
content: Quote from: Skimask on March 12, 2016, 06:25:50 amSo via stitching is what I did and it ok to do?I'm rerouting with 10-15 mil traces. And widen or lessen the clearance?And I can't believe I forgot the decoupling caps. 10uf eletro and 10uf ceramic caps be ok?

author: daqq
author_rank: Super Contributor
timestamp: March 12, 2016, 06:43:02 am
content: You are using the minimal widths for traces available on most signals as well as the minimal clearance available in copper pour - while this will work there is no reason not to wider traces - this will remove any risks of using limit values of clearences/widths.As was advised previously - more local decoupling would be great - both at the input and output of U2 and on the processor.Also, your SCK trace running under U2 splits two power rail signals - it would be more proper to split the SCK signal and run the two power rails without interruption.

author: Rerouter
author_rank: Super Contributor
timestamp: March 12, 2016, 06:44:40 am
content: Signal lines under the crystal,Decoupling cap is quite far away from the micro power pin,Crystal layout is sub optimal, could be much tighter,On your 3 pin regulator, you could move your ground via much closer to the pad,Moving C3 closer to the regulator pin means you could move your 5V and ground jumper points closer to J5, reducing the length, and a trace running half way across the board,Moving your ICSP header between the micro and PORTB means you could reduce your connection length,

author: Rerouter
author_rank: Super Contributor
timestamp: March 12, 2016, 06:47:13 am
content: the first 3 i suggested are things that should be fixed to improve the devices immunity to less than desirable conditions,The rest are just suggestions

author: Skimask
author_rank: Super Contributor
timestamp: March 12, 2016, 06:52:36 am
content: QuoteDecent start, but you can add more to fill in those open spaces on the top layer. But I'd save that for somewhere around last. You got other stuff to fix.QuoteFatter traces, fatter clearances. In the future, when you decide you want to change something, you've got a bit more room to play with.QuoteWatch Dave's last video.

author: thomasb9511
author_rank: Contributor
timestamp: March 12, 2016, 08:58:51 am
content: Any better guys?Top copper layerBottom layerSchematicAdded bypass capsfatten up traces and clearancemoved everything closer together

author: radar_macgyver
author_rank: Frequent Contributor
timestamp: March 12, 2016, 02:30:28 pm
content: Looks a lot better. I suggest adding a copper fill (polygon) under the heat sink tab of the 3.3V regulator. This acts as a heatsink. Consider routing the crystal nets around the crystal rather than underneath. You may also want to increase the clearance between the fill poly and the traces. Finally, this may just be a personal preference - I don't like using long diagonal traces, when all the parts on the board are oriented vertically or horizontally (ie, none are rotated 45 degrees). This lets me route using fewer vias.

author: Skimask
author_rank: Super Contributor
timestamp: March 12, 2016, 04:13:13 pm
content: I'd also move the outer dimension (the bounding dimension, the edge of the board) out a bit so the ground plane has a continuous path on both top and bottom around all four sides.And echo the previous comment about the clearances on the fills and traces (I think it's the 'isolate' parameter). Tight clearances on the fills make for easy chances to short some oddball trace directly to ground.

author: thomasb9511
author_rank: Contributor
timestamp: March 12, 2016, 06:16:34 pm
content: Increased the polygon isolationAdded a heatsink pour for the regulatorEnlarged the board slightlyTopBottom

author: Skimask
author_rank: Super Contributor
timestamp: March 13, 2016, 06:29:57 am
content: Now you can still add more stitching vias to increase the ground plane area on the bottom layer.Other than that, looks pretty good to me.

author: thomasb9511
author_rank: Contributor
timestamp: March 13, 2016, 08:06:23 am
content: Redid the board layout entirelyLarger board sizeAdded a lot more via stitchesTopBottom

author: ptodorov
author_rank: Contributor
timestamp: March 20, 2016, 07:52:28 am
content: thomasb9511 Can you please post the final brd file as well? I'm working on a 3D visualization tool for Eagle board files and would like to test with your designthanks

author: elgonzo
author_rank: Unknown
timestamp: March 20, 2016, 10:50:50 am
content: Holy moly... Did a hedgehog sleep on your PCB, or where are all those vias coming from?Note that specifically with regard to your board, the via stitching has no negative side effect but it also has no purpose either. Your board is neither dealing with (somewhat) higher currents, nor is it dealing with high(er) signal speeds/frequencies. It's just a simple 328P board. So, why the obsession with all those vias?There are only two things on your board that could possibly (i am stretching the meaning of "possibly" here) benefit from via stitching (if at all).One would be a seam of vias around your board edges which would counter possible EMI radiated from your board. The other would be the copper pour functioning as a heat sink for your VREG (using vias as "thermal vias" to connect the heat sink copper pour on the top with a copper pour on the bottom, thus increasing the thermal capacity of the heat sink). Side note: I do not expect EMI or the size of the current heat-sink copper pour to be really a problem for your board design...With regard to when and why via stitching is recommended/necessary, read the following thread:via stitching in PCB's(random pick, there are probably more threads here which say something similar along those lines).Remember that i said that the via stitching on your board has no negative side effect. So, if you like 'em, keep 'em. Don't worry. Just try to understand what the reasons requiring via stitching are and whether they apply to your board...

author: TheDirty
author_rank: Frequent Contributor
timestamp: March 24, 2016, 09:02:55 pm
content: A little late, but are those slots specified on the USB connector? If this is a cheap chinese PCB batch vendor, like elecrow, seeed, ... they may not support those slots. I've had to change some slots to larger holes in order to get these through.

author: Karel
author_rank: Super Contributor
timestamp: April 17, 2016, 06:59:18 am
content: Quote from: thomasb9511 on March 13, 2016, 08:06:23 amCheck ratsnest. You forgot at least one connection.

author: AndyC_772
author_rank: Super Contributor
timestamp: April 17, 2016, 01:23:39 pm
content: Personally I never put an RoHS logo on the board, because the PCB artwork isn't what determines whether or not the finished product is RoHS compliant. You can, for example, assemble a compliant bare board using tin-lead solder, and then the assembly is non-compliant but the logo is still there.

author: gauravmp
author_rank: Regular Contributor
timestamp: May 24, 2016, 03:47:51 am
content: I haven't readrough all the comments and someone might have already pointed this out. I notice that your name is not written in silk screen. It is instead a copper GND surface. Change that in the top/bottom layer setting and you should be fine. Else, you won't be able to see your name. It'll just appear as a trace.

author: vzoole
author_rank: Regular Contributor
timestamp: May 24, 2016, 09:39:51 am
content: I prefer solid ground as possible like this:(I used Eurocircuits basic rules so easy to make it)