Crosstalk and the large parallel bus - Page 1
Forum section: electronics / projects

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: April 15, 2022, 08:00:54 pm
content: So I'm in the design stage of an FPGA<-->FT601<-->Mac/Pc add-on, and I just wanted to poll opinions on requirements of the FT601/FPGA interface...The FT601 is a USB3:FIFO chip, which runs the FIFO at 100MHz/32-bit. You can run it at 66MHz/32-bit but that reduces your data bandwidth to the FPGA, obviously enough. I'm planning on putting 33R resistors close to the FT601, which is what FT do in their demo board, but I'm concerned about the potential for cross-talk as the connection are made to the FPGA.[ Specified attachment is not available ]In the screenshot, you can see I have the option of running 3.5 mil trace/space out between the BGA pads either with 1 or 2 traces between the two pads - due to complications with other design constraints, if I use the 1-trace-between-pads, I'll have to go to an 8-layer board to route all the signals. If I can route 2 traces between consecutive pads, a 6-layer board will be fine. The cost different is about a factor of 2...The rule-of-thumb I've used before for cross-talk avoidance is to have center-to-center of parallel traces be 3x the width of the trace itself, (or: separation between must be 2x the trace width). That doesn't seem achievable with 2 traces between the pads as the signals go past those pads [of course, sigh]. The same for deeper-in traces that go by vias.So, to those who know, or who maybe have done something like this before, is this a strict constraint for a realistic chance of it all working ? Or could I get by with relaxing it and reducing my layer-count ? This is for prototyping, not for production - when the run is scaled up, the difference between 8 and 6 layers doesn't really matter to me.(Ignore the signal names, btw, I just chose random signals that were close by to illustrate what I was talking about).[aside: and some day I will understand how to put an image into the middle of a post - the 'inline expandable thumbnail' option continues to elude me...]

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 15, 2022, 09:36:38 pm
content: Outer FR4 thickness is the critical dimension here.Separation doesn't matter in relation to trace width -- well, almost. Edge coupling is very minor, essentially because the facing edges are very thin, also half the space inbetween is through air. The shielding effect of the ground plane gives the important dimensional reference here: traces closer to each other than to the ground plane, have notably higher coupling (though still maybe not very much; again, the ratio is fairly unfavorable due to the conductor ratio). Highest pairwise coupling comes with much higher distances over ground, that are hard to achieve on PCB; think twisted pair (round conductors) in a wiring harness (spaced some distance above a metallic enclosure). Or if you can afford flat-facing traces (routed in same location, on adjacent layers), that would be one way to achieve higher pair coupling on PCB.For reference, edge coupling of traces on outer layers of typical multilayer boards, is something like 10 or 15%. So, not a big deal for digital purposes, where you'd need 30% or more to violate logic thresholds. Probably more still if this is a clocked bus, as long as the propagation delays aren't too weirded by the crosstalk and the clock itself is clean.And that's all just if it's the geometry over the full trace length. A local neck-down like this, hardly matters: only wavefronts comparable to the dimensional scale (a couple mm, so, 10s of ps?) will see much coupling, and at lower frequencies it's just a tiny bit more (mutual) inductance or capacitance, hardly anything to matter. So, don't worry about it too much.Source termination resistors are a good idea, yeah, though not too important if the bus is short -- 100MHz is 10ns period or 5ns bit times, you'd want a modest fraction of that as the maximum propagation delay. Which is really quite a bit of bus, like, almost a meter. Now, you might still have signal bounce in that case, so, if it settles down before the clock arrives, that's fine. Otherwise,the edge rate is key, so, say the drivers are 100ps risetime, then for electrical length less than that, it's fine without terminators; which might be a couple cm, basically two chips butted together; and then for greater distances, termination is required.Note that pin driver impedance adds with the external resistor; generic CMOS drivers are usually in the 30-70 ohm range, though you might have something different/special here, I don't know. (Your average say 60MHz MCU has risetimes in the 1-3ns range; a 100MHz bus probably has somewhat higher performance.) Which is why you only need say 33 ohms to match a pin driver to a ballpark 50-100 ohm trace and get good signal quality. And again, if the bounce is much less than 20 or 30%, which is to say, the impedances match within the same margin -- it's fine for digital logic purposes. So the pin drivers tend not to be very tightly controlled in the first place (Rds(on) depends on manufacture, supply voltage and temperature), but it's okay because thresholds cover that.Mind, to say nothing of EMI; a 1m ribbon cable carrying that kind of signal, even without a lot of bounce, would be quite nasty indeed. These are logic level signals, so, shielding is mandatory. Which in the context of a PCB, means ground plane construction, so that's alright.Tim

author: SpacedCowboy
author_rank: Frequent Contributor
timestamp: April 15, 2022, 09:49:00 pm
content: Awesome, thank you very much!The chips aren'tquiteabutted, but they're close - say within 5cm for the longest trace FPGA<->resistor then another 0.4cm for resistor<->FT601. The FTDI data sheet is a little vague on rise-time, it's more focussed on the protocol timing (setup, hold,..) but their example board has them on so seems like the termination might help...And thanks for the clear explanation - very helpful to file away for the future