Problems with SPI master code on ARM - Page 1
Forum section: electronics / general

author: perdrix
author_rank: Frequent Contributor
timestamp: February 09, 2022, 10:49:04 am
content: I'm looking at some SPI master code that runs on an LPC2388FBD144 (NXP ARM processor) for a colleague. I'm doing the slave SPI code that runs fine on a PIC.Somehow his code "misses" reading messages that I know were sent because I can see them in a hardware LA trace of the exchange. We're both quite puzzled how SPI master code can appear to "drop" messages. He's been adding delay loops to the code in an attempt to make it work which I don't think can be the right way to solve this problemHere's a small snip of the code:Code:// Lag = Signed position error (int, transmitted as two values)while (SSP0SR & BSY);while (!(SSP0SR & TFE));/* Wait if TNF cleared, Tx FIFO may still be full. */for (rb=1;rb<10;rb++);// allow for a gapSSP0DR = 0xEBEB;// send 7. pollwhile (!(SSP0SR & RNE));val = SSP0DR << 16;// read back 6th value: Lead/Lag, High int partwhile (SSP0SR & BSY);while (!(SSP0SR & TFE));/* Wait if TNF cleared, Tx FIFO may still be full. */for (rb=1;rb<10;rb++);// allow for a gapSSP0DR = 0xEBEB;// send 8. pollwhile (!(SSP0SR & RNE));ram_var.Lag_X = val | SSP0DR;// read back 7. value: Lead/Lag, Low int part// Statewhile (SSP0SR & BSY);while (!(SSP0SR & TFE));/* Wait if TNF cleared, Tx FIFO may still be full. */for (rb=1;rb<10;rb++);// allow for a gapSSP0DR = 0xFFFF;// send dummy byte for reading back the last valuewhile (!(SSP0SR & RNE));ram_var.State_X = i = SSP0DR;// read back 8. value: Flags// wait for end of transmission before deactivating SSEL/while (SSP0SR & BSY);while (!(SSP0SR & TFE));/* Wait if TNF cleared, Tx FIFO may still be full. */for (rb=1;rb<20;rb++);// allow for a gap// condition handlingif (i & 0x4000){// was a stall indicated?for (rb=1;rb<200;rb++);// allow for a longer gapSSP0DR = 0x8001;// Send STALL_ACKwhile (SSP0SR & BSY);while (!(SSP0SR & TFE));/* Wait if TNF cleared, Tx FIFO may still be full. */for (rb=1;rb<20;rb++);// allow for a gap}I believe that there must be a problem with how he is testing that it's:OK to transmit the next 16 bits, andthe data xfer has completed.I'm a complete beginner with ARM SPI - I only saw this code yesterday for the first time.The LA trace is quite clear (image attached) that 0x4000 was received by the master when it sent the 0xFFFF message. And yet the code that's supposed to send the ACK never triggered (otherwise you'd see the master sending 0x8001 before *SSEL was raised - orange trace).Any guidance on what's wrong will be gratefully received.ThanksDavid

author: bson
author_rank: Unknown
timestamp: February 09, 2022, 05:55:48 pm
content: You only read one byte of the last 16-bit word, right? If so you would get the high byte, and you should check for bit 7 (0x40) rather than bit 15 (0x4000).

author: perdrix
author_rank: Frequent Contributor
timestamp: February 09, 2022, 06:13:37 pm
content: No the SPI is configured for 16 bit xfer

author: perdrix
author_rank: Frequent Contributor
timestamp: February 09, 2022, 06:15:21 pm
content: However I did notice that he's not pulsing *SSEL between sending each buffer ... that's naughty!So I've asked him to change his code ...D.