SPARC is it dead? - Page 1
Forum section: electronics / general

author: mipl
author_rank: Newbie
timestamp: September 16, 2018, 10:16:15 pm
content: Is the SPARC architecture still alive? As fa as I know ORACLE laid off most of the US design team... I know that the SPARC was a server CPU, but it had a niche in the rad hard / space application ([ESA/LEON][http://en.wikipedia.org/wiki/LEON])Regards, Mipl

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 16, 2018, 10:21:15 pm
content: AFAIK the latest SPARC core that was openly released was:http://www.oracle.com/technetwork/systems/opensparc/opensparc-t2-page-1446157.htmlHaven't heard of any further updates on the SPARC architecture in ten years.

author: mmagin
author_rank: Frequent Contributor
timestamp: September 16, 2018, 10:28:30 pm
content: Sure sounds like it's entirely Fujitsu now:https://en.wikipedia.org/wiki/SPARC

author: TheBay
author_rank: Unknown
timestamp: September 16, 2018, 10:44:54 pm
content: Quote from: mipl on September 16, 2018, 10:16:15 pmThere were SPARC workstations, a few different things have been SPARC based.Sad really that it declined.

author: glarsson
author_rank: Frequent Contributor
timestamp: September 16, 2018, 10:54:46 pm
content: SPARC was also used in embedded systems, e.g. in digital cameras.

author: Cerebus
author_rank: Super Contributor
timestamp: September 16, 2018, 11:10:14 pm
content: Quote from: SiliconWizard on September 16, 2018, 10:21:15 pmThen you can't have been listening very hard. There have been the SPARC T3, T4, T5, M5, M6, M7, S7 and M8, and that's just the SPARC chips released by Oracle in that time period. Fujitsu, Atmel, Cobham, MCST, and NUDT have all released SPARC chips in the same 11 year period since the release of the T2. Twenty three implementations in total since the original T2. There have been two further revisions of the core SPARC architecture since the 2007 revision that the T2 is based on.

author: boffin
author_rank: Unknown
timestamp: September 16, 2018, 11:16:43 pm
content: There's a SPARC emulator out there for AMD/Intel now from Stomasys called Charon-SSP. That's what my old employer were moving their stuff to (that had to run on SPARC)

author: PhilipPeake
author_rank: Regular Contributor
timestamp: September 17, 2018, 01:11:38 am
content: Its dead. It was mostly used in Solaris servers and workstations.Every company that I know of that uses (used) Solaris is working hard to move to something else (mostly Linux).They see no future, and really don't want to deal with Oracle.

author: drussell
author_rank: Super Contributor
timestamp: September 17, 2018, 01:23:59 am
content: Quote from: mmagin on September 16, 2018, 10:28:30 pmIndeed:Quote

author: helius
author_rank: Super Contributor
timestamp: September 17, 2018, 04:08:28 am
content: It is available as an open hardware VHDL core (LEON), which is used in NavSpark GPS modules among other things.

author: andersm
author_rank: Super Contributor
timestamp: September 17, 2018, 05:46:10 am
content: Fujitsu have switched to AArch64 for their future supercomputers.

author: richardman
author_rank: Frequent Contributor
timestamp: September 17, 2018, 07:14:05 pm
content: Just a couple years prior to the Oracle acquisition, SUN released some roadmaps of new Sparc microarchitectures. It was clear to most people that they basically ran out of ideas and people were skeptical, so the Oracle sales were inevitable.I think the Sun servers had made some money for Oracle, but clearly they weren't going to continue with the architecture. Now that companies can leverage someone else's hardware investment in cloud servers, I don't think people care that much anymore.And of course on the embedded side, there is few opportunities to compete against ARM, so we are definitely seeing a consolidation, or in a negative way: the absence of choice, in the marketplace.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 17, 2018, 09:21:29 pm
content: Quote from: Cerebus on September 16, 2018, 11:10:14 pmProbably.I also noticed the whole line of more recent Sparc processors following the discussion in this thread - but admittedly not before that.As PhilipPeake said (maybe a bit too pessimistically), Sparc-based servers seem to have disappeared in a lot of areas (obviously there must still be some as there is active development), and I honestly haven't run into one in over ten years. That's just my experience of course. I'd be interested in knowing where they are still used.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 17, 2018, 09:26:17 pm
content: Quote from: richardman on September 17, 2018, 07:14:05 pmYes. There is some competition though. MIPS for instance. They have nice stuff. Microchip chose MIPS over ARM for their PIC32 MCUs, but with the acquisition of Atmel, I wonder how long they will maintain their MIPS-based line of products.

author: andersm
author_rank: Super Contributor
timestamp: September 17, 2018, 09:48:01 pm
content: Quote from: SiliconWizard on September 17, 2018, 09:26:17 pmMIPS has been passed around so many times in recent years it's hard to see a future there. A lot of their traditional customers have switched to ARM, like everyone else.QuoteThat decision seems to have been more marketing-driven than anything, but the devices seem to be gaining in popularity despite Microchip's best attempts at sabotaging their own products. Allegedly the Atmel acquisition did result in Microchip killing their high-end MIPS SoC projects.

author: technix
author_rank: Super Contributor
timestamp: September 18, 2018, 03:41:45 am
content: Quote from: andersm on September 17, 2018, 09:48:01 pmThose chips overlapped with ATSAMA5 line, and that line already has an established community and open tool set carried over from the AT91SAM9 days. I can see Microchip killing their overlapping MIPS products so they don't have to maintain two overlapping and competing communities.As of SPARC, I think it is still the best performing open source CPU cores out there. Although chips like Zynq and Cyclone V SoC - FPGA with a high performance hard CPU core, often ARM - are encroaching the market of soft cores in general, especially the high performance ones carved out by OpenSPARC. And there is this crouching tiger that is Xeon Arria (yes Intel confirmed it, although it is currently a build-to-order product) that has a huge Arria 10 FPGA coupled to a 8-core Skylake Xeon Scalable.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 18, 2018, 05:58:03 pm
content: Quote from: andersm on September 17, 2018, 09:48:01 pmFuture is always hard to predict and most people have failed spectacularly when they tried.That said, yes ARM is a pervasive monster, but any decent competition is as interesting as it is sane.AFAIK, big companies such as Broadcom and Mediatek use MIPS cores in their network processors/modem ICs. There is also the chinese Loongson initiative. They have a harder time competing with ARM for MCUs and general-purpose processors for a number of reasons, but I wouldn't call MIPS dead by any means.For Microchip, I think this choice was threefold: first for technical reasons (MIPS microAptiv had distinct advantages at the time), then marketing reasons of course (a way of setting itself apart) and finally they most likely got a way better financial deal with MIPS. ARM sales can be obnoxious.

author: technix
author_rank: Super Contributor
timestamp: September 18, 2018, 08:07:57 pm
content: Quote from: SiliconWizard on September 18, 2018, 05:58:03 pmLoongson is, curiously, trying to run on the higher end chipset market. They don't put much effort in embedded markets, instead they focus on laptops and larger computers. They even has dual processor capable chips,. Since their chips uses HyperTransport, I have seen some rumors floating around that new chips would be built with a 486-compatible Zet core built in to properly execute the x86-based BIOS, so those newer Loongson can operate in straight COTS AMD AM3+ and G34 motherboards. (A special bootloader would be used to start the MIPS cores from the Zet core.)AFAIK Richard M. Stallman is a Loongson user. This alone makes me believe that at least for general computing purposes MIPS is not going away anytime soon.

author: andersm
author_rank: Super Contributor
timestamp: September 18, 2018, 08:44:45 pm
content: Quote from: SiliconWizard on September 18, 2018, 05:58:03 pmBoth Broadcom and Mediatek also make ARM-based products in other segments. It'll be interesting to see which way they'll go once they decide it's time for a new device generation. Qualcomm (Atheros) and Cavium have already switched to ARM. China had that whole "national computer architecture" political thing which begat the Loongson, but after ARM started granting licenses to Chinese companies I can't think of a single new manufacturer that selected MIPS (that of course doesn't mean they don't exist, just that none of them have made the news in the west. Meanwhile eg. Allwinner has taken off in a big way.)QuoteWhat advantages did the microAptiv offer? From a user's perspective it's somewhere around the Cortex-M3/M4, with slightly higher performance but a much more clumsy architecture.

author: andersm
author_rank: Super Contributor
timestamp: September 18, 2018, 08:55:32 pm
content: Quote from: technix on September 18, 2018, 08:07:57 pmThat was a purely political decision based on the claim that the machine was more "free" because it didn't use closed firmware (dunno if anyone audited the chips for backdoors). Even at the time, the machines (sold under the "Lemote" brand) were pretty miserable underpowered netbooks. I don't know if they've released new models since then, though.

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 18, 2018, 11:25:45 pm
content: Quote from: andersm on September 18, 2018, 08:44:45 pmAs I remember, at least the following: more performance per clock cycle, the ability to reach higher clock frequencies for a given process node (partly due to a deeper pipeline) and a reduced interrupt latency. The second point allowed Microchip to use a 250 nm process for the PIC32MX while keeping a reasonable power consumption. The LPC1700 line, for instance, cortex-M3 based and released in 2008 with approx the same max clock freq was using a 130 nm process which obviously was much more expensive. Microchip probably wanted to keep initial costs down as they were entering the 32-bit market with uncertainties.The PIC32MX was released in 2007 as I reckon, the project itself probably started at least 2 years before that; the Cortex M3 had barely been released by then and there were not many MCUs using it at the time. The context also has to be taken into account.Maybe it's a much more clumsy architecture but I'd be interested in getting facts and details on that.

author: technix
author_rank: Super Contributor
timestamp: September 19, 2018, 02:46:39 am
content: Quote from: andersm on September 18, 2018, 08:55:32 pmThose Lemote machines boots from u-boot with properly released source code, and it goes straight to Linux-libre.Quote from: andersm on September 18, 2018, 08:55:32 pmLemote and Loongson are two separate companies. I am not sure if Lemote has progressed beyond netbooks, but Loongson certainly has those more powerful chips including some quad-core dual-processor behemoths.

author: andersm
author_rank: Super Contributor
timestamp: September 19, 2018, 06:19:16 am
content: Quote from: SiliconWizard on September 18, 2018, 11:25:45 pmNitpick, but the PIC32MX MCUs use the M4K core. The first microAptiv MCU was the trash fire that was the PIC32MZ EC, released in 2013. I don't remember what the first Luminary devices looked like, but I do remember the STM32F101 topping out at 36MHz. By 2009 there were definitely Cortex-M3 devices going up to 100MHz on the market.QuoteYou can write quite complex firmwares for Cortex-M devices without requiring any assembly or compiler intrinsics. The PIC32Ms require quite a lot of compiler support to hide the ugliness. The whole KSEG/USEG split, and especially the KSEG0/KSEG1 aliasing, adds a lot of complexity if you want to customize the memory layout. The MIPS architecture also carries a lot of baggage, eg. every PIC32M starting up in single-vector interrupt mode because that's how ancient MIPS processors worked, and it's somehow important to be compatible with that.

author: technix
author_rank: Super Contributor
timestamp: September 19, 2018, 10:24:40 am
content: Quote from: andersm on September 19, 2018, 06:19:16 amI have some LM3S317 if you want to test on. Are those “early Luminary” parts?Quote from: andersm on September 19, 2018, 06:19:16 amARM made a point that the NVIC uses the exact same vector format as void(*[])(void) in ARM EABI, and made interrupt behaves exactly as an EABI function call. This allowed Cortex-M processors be programmed with literally zero line of assembler if combined with an EABI compiler like GCC and pure memcpy/memset in C library.Although I have multiple samples of PIC32 chips I have not actually programmed any of them yet. AFAIK the PUC32MZ DA (and the MZ EF series) with MPU cores the TLB MMU appeared to be simpler to use than the FMT one on the MCU cores as the entire KSEG thing can be bypassed and redefined into a single flat address space (or if you have the spare RAM just use Linux)

author: SiliconWizard
author_rank: Super Contributor
timestamp: September 19, 2018, 07:36:43 pm
content: Quote from: andersm on September 19, 2018, 06:19:16 amAlright. I assumed the M4K was considered a part of the microAptiv line, apparently not. It doesn't change the reasoning though, and I believe the architectures are close enough.Quote from: andersm on September 19, 2018, 06:19:16 amYes, but not in 2007 when the PIC32MX was released. I mentioned the NXP LPC1700 line which was released in 2008, Cortex-M3 and going up to 100 MHz. Still one year later and as I mentioned, on a much costlier process node.Quote from: andersm on September 19, 2018, 06:19:16 amI get the point, but whether those are issues is up for debate.I'm certainly no specialist of the MIPS architectures, but the split between a "kernel space" and "user space" bears some security advantages despite being somewhat more difficult to handle. Granted, it looks like a somewhat "ancient" way of segmenting memory but it's not necessarily bad per se.The Cortex-M3 and M4 have optional MPUs and a lot of MCUs have been released without one AFAIK.

author: mipl
author_rank: Newbie
timestamp: September 19, 2018, 08:55:55 pm
content: The "user space" and "kernel space" wrapped in the TrustZone name is now promote by ARM as feature of the Cortex M-23 / M-33. In that case of the MIPS, PowerPC and others, they had this feature since long time.... how it was implemented is the other story.Regarding the SPARC and the niche of rad hard CPUs, it was also taken over by ARM... Atmel was manufacturing rad hard SPARCs for ESA (European Space Agency) and after Mirochip took over the company they are moving to ARM here as well.http://www.microchip.com/design-centers/aerospace-and-defense/radiation-hardenedQuoteIn general I would say that the PIC32Mx (MIPS) days at Microchip are counted and it will follow the path of the AVR32 as soon as PIC32Cx (ARM) become reality (if ever).

author: westfw
author_rank: Super Contributor
timestamp: September 19, 2018, 10:25:23 pm
content: Quotethat doesn't seem to be stopping the ARM CM0, which I'd also rate as "much more clumsy" than CM3.(although the number of vendors offering tiny and cheap CM4 chips is encouraging.)

author: technix
author_rank: Super Contributor
timestamp: September 20, 2018, 04:22:26 pm
content: Quote from: mipl on September 19, 2018, 08:55:55 pmI don't find it likely that Microchip would have two distinctly-named product lines using the same core. What was PIC32C is mostly now folded into the ATSAM series.

author: andersm
author_rank: Super Contributor
timestamp: September 20, 2018, 06:13:11 pm
content: Quote from: SiliconWizard on September 19, 2018, 07:36:43 pmIt's a newer release of the architecture (MIPS32r3 vs MIPS32r2) which adds the microMIPS instruction set. So fairly similar, but also significant additions.QuoteNot directly, as you still need some mechanism to actually map the address space into USEG. On PIC32s with fixed mapping translations you have Microchip's bus matrix controller, which isn't the greatest mechanism, and on others you have a TLB. In any case, adding virtual addresses to the mix certainly doesn't make things simpler.On "grown-up" hardware, the fixed address space split also adds its own complications. Eg. OpenBSD dropped support for 32-bit MIPS not too long ago, because the limited address space didn't allow for effective address layout randomization.QuoteYes, and the specification of the MPU makes it almost unusuable, since the section size and alignment restrictions are far too coarse for practical use. I think this may have been improved in the ARMv8-M specification, but don't know offhand for sure.

author: james_s
author_rank: Super Contributor
timestamp: October 17, 2018, 04:44:13 pm
content: I still have several Sparc based workstations and a small Netra server but I don't often fire them up. They were really impressive stuff in their day, but now a Raspberry Pi is considerably more powerful.

author: brucehoult
author_rank: Super Contributor
timestamp: October 18, 2018, 02:50:06 am
content: Quote from: andersm on September 20, 2018, 06:13:11 pmMicroMIPS is a bit ugly. The entirely new NanoMIPS encoding looks pretty nice though.