Help me debug issues with FSK demodulation (PLL NJM2211) [SOLVED] - Page 1
Forum section: electronics / projects

author: PeterF
author_rank: Contributor
timestamp: April 12, 2018, 03:36:46 pm
content: Hi,I'm continuing on my power line communication project that I got a lot of great input on previously.It is a 132kHz~/184kHz~ PLC device that communicates to a specific type of device that I have not designed myself.See attached schematic.I have now had a board for a while, and am using it to communicate with devices.I have found a scenario where my setup for the first time cannot decode a received message anymore.It seems that it does not lock on the high frequency signal.I am not sure how to start debuging what my problem is, and how to improve and solve it.I have attached waveforms of both waveforms which are divided by a resistive divider to half the amplitude, and then fed to the demodulator as seen in the schematic.https://www.njr.com/semicon/PDF/NJM2211_E.pdfAny tgoughts?

author: ehughes
author_rank: Frequent Contributor
timestamp: April 12, 2018, 06:19:49 pm
content: Hello!QuoteWhat device are you trying to communicate with?

author: PeterF
author_rank: Contributor
timestamp: April 12, 2018, 06:26:32 pm
content: Hi,I am sorry but at this time I cannot talk too much about the devices.

author: nightmechanic
author_rank: Contributor
timestamp: April 12, 2018, 07:59:46 pm
content: Hi,I am a bit puzzled since I don’t understand how there are cases where this works...Can you share the calculations you made for selecting the demodulator components?And, why you have chosen to deviate from the manufacturer’s recommendations, specifically for c202 which seems a very low value?

author: PeterF
author_rank: Contributor
timestamp: April 13, 2018, 05:40:40 am
content: Hi,I am so sorry, I realized that I was looking at the wrong version of the schematicHere is the one I've had built up and tested attached.Also, see my calculations attached here.I found during some initial range testing with a test setup that I got some improved locking range by lowering C205 ("C1") to 47 pF, hence that diviation from the calculations.

author: PeterF
author_rank: Contributor
timestamp: April 13, 2018, 06:15:50 am
content: Perhaps I can attempt to clarify a bit.The above curveforms are at the edge where my decoding stops. I have many devices connected, with long cables.Some of the cables are still rolled up which could perhaps cause some capacitive and inductive loading as well?But one of them is decoded perfectly, without any glitches in the lock signal (and ofc. all data is correct) while the other is not.(see the names of the files)I have (different measurement setup unfortunately) here attached a received signal from just one unit hooked up, with much shorter cables.There are no issues in decoding this message.I can see that the signals that are troublesome don't look too good, but I cannot figure out exactly what is happening when the PLL fails to lock into one of them but not the other.From my point, the following things are NOT the issue here:Amplitude of the signal. (I could have increased my amplification, but it seems to be sufficient and not so much damped compared to working signals.Lock range of the demodulator. (It seems that the frequency I am getting is still within the lock range, but I am getting other components in the signal that are interfering?)Is it possible to filter out the "bad components" of these signals to leave only the main 184/132 kHz signal in a non-to-complicated fashion?I have attached an image of a rough idea of a strange idea of what I am assuming I would want to filter out.

author: nightmechanic
author_rank: Contributor
timestamp: April 13, 2018, 08:14:37 am
content: Thanks for the clarification,Can you share the spectrum (e.g. FFT ) if the 4 good/bad signals?

author: PeterF
author_rank: Contributor
timestamp: April 14, 2018, 07:04:48 pm
content: I don't think I have any equipment to produce a decent FFT at this point.Or maybe the Rigol scope I'm using can do something.. I have to check when I'm back in the lab.

author: PeterF
author_rank: Contributor
timestamp: April 16, 2018, 04:48:23 am
content: I found the problem. And the solution.Measured the data with my Salae logic pro () and did some FFT analysis in python. (see attached images)Then tried a butterworth filter with a Fc of 180 kHz and it cleaned everything up real good.Hacked together a similar filter with the stuff I could find around the lab, and the signal was very cleaned up in real life too(see image. yellow is before filter, blue after)I am still having a few minor issues with locking now after this, which I will look more into.But that might just have to do with the amplitude of the signal being too low.Anyway, a much minor issue in comparison to the bad signal I had earlier.The system has now worked practically in every case I could find to put it into, so was a great find.