VHDL - Link pins from different entities - Page 1
Forum section: electronics / beginners

author: soFPG
author_rank: Frequent Contributor
timestamp: May 06, 2018, 12:41:21 pm
content: I am trying to copy a simple existing CPU inside a microcontroller.For initial testing purposes I tried to set the program counter to start value 0x000 and hoping for a change at the "instruction-bus", these are my two VHDL-entities involved:Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity MDT90P01 isport (pc: out std_logic_vector(8 downto 0);c0: in std_logic;w_reg_top: in std_logic_vector(3 downto 0);instruction: in std_logic_vector(10 downto 0));end MDT90P01;architecture Behavioral of MDT90P01 isbeginprocess(c0)beginif(falling_edge(c0)) thenpc <= "000000000";end if;end process;end Behavioral;Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;USE IEEE.numeric_std.all;entity Instruction_Memory isport (pc: in std_logic_vector(8 downto 0);instruction: out std_logic_vector(10 downto 0);c0: in std_logic);end Instruction_Memory;architecture Behavioral of Instruction_Memory istype ROM_type is array (0 to 511) of std_logic_vector(10 downto 0);constant rom_data: ROM_type:= ("10010000110","10010000110",(others=>'0'));beginprocess(c0)beginif(rising_edge(c0)) theninstruction <= rom_data(to_integer(unsigned(pc)));end if;end process;end Behavioral;But ModelSim-Altera only shows me this, I expected "instruction" to be "10010000110" but it isn't - why?

author: rstofer
author_rank: Super Contributor
timestamp: May 06, 2018, 02:01:59 pm
content: I don't see a 'top' module where you tie the signals together. Usually this module will just define the various signals and connect them between lower level entities. You may have such a module and didn't post it.'pc'' is declared as an output in MDT90P01 and as an input in InstructionMemory but there doesn't seem to be anything tying the ports together.

author: soFPG
author_rank: Frequent Contributor
timestamp: May 06, 2018, 02:10:51 pm
content: QuoteMDT90P01 is the Top-Level Entity. I am new to VHDL and unaware of that different entities need to be tied together besides equal port names.I added this:Code:architecture Behavioral of MDT90P01 issignal pc_int : unsigned(8 downto 0);begininstr_inst: entity MDT90P01.Instruction_Memoryport map(pc => pc, instruction <= instruction);process(c0)beginif(falling_edge(c0)) thenpc <= pc_int;pc_int <= pc_int + 1;end if;end process;end Behavioral;but I get:Quote

author: rstofer
author_rank: Super Contributor
timestamp: May 06, 2018, 05:41:57 pm
content: I know I'm going to screw this up...Assuming your entities are in separate files in your workspace:Code:library stuff...entity myproject isPort (clk : in std_logic;);end myproject;architecture Behavioral of my project issignal pc : std_logic_vector(8 downto 0);signal c0 : std_logic;signal instruction: std_logic_vector(10 downto 0);signal w_reg_top: std_logic_vector(3 downto 0) := (others => '0');beginc0 <= clk; -- for exampleinst_PC: entity work.MDT90P01 Port Map (pc => pc, -- hook up the wiresc0 => c0,w_reg_top => w_reg_top,instruction => instruction);inst_InstMemory : entity work.Instruction_Memory Port Map (pc => pc, -- hook up the wiresinstruction => instruction);end Behavioral;Something like that...ETA: I had left out a couple of details...