basic Verilog question - Page 1
Forum section: electronics / general

author: danmcb
author_rank: Regular Contributor
timestamp: February 05, 2017, 10:52:42 pm
content: I am teaching myself some Verilog with the help of icarus and the great course materials available online at MIT.I set myself a little task to model a D flip-flop with NAND gates, and a test bench, this is what I came up with.===(file d_flip.v)Code:module d_flip(input clk,input d,output q,output q_bar);wire a, b;assign a = !(clk && d);assign b = !(clk && a);assign q = !(a && q_bar);assign q_bar = !(b && q );endmodule===(file d_flip_tb.v)Code:module d_flip_tb;reg d, clk;wire q, q_bar;d_flip uut(.d(d),.clk(clk),.q(q),.q_bar(q_bar));initial beginassign d = 1'b0;assign clk = 1'b0;$display("time = %t: q=%b, q_bar=%b",$time, q, q_bar);#100;assign clk = 1'b1;//#10;$display("time = %t: q=%b, q_bar = %b",$time, q, q_bar);#10;assign d = 1'b1;assign clk = 1'b0;//#10;$display("time = %t: q=%b, q_bar = %b",$time, q, q_bar);#10;assign clk = 1'b1;//#10;$display("time = %t: q=%b, q_bar = %b",$time, q, q_bar);endNow when I run, i get this:time = 0: q=x, q_bar=xtime = 100: q=x, q_bar = xtime = 110: q=0, q_bar = 1time = 120: q=0, q_bar = 1If I uncomment the extra time steps before each $display, I get this (which is what I expected):time = 0: q=x, q_bar=xtime = 110: q=0, q_bar = 1time = 130: q=0, q_bar = 1time = 150: q=1, q_bar = 0Why do I need to have an extra time step? it's as if the simulator assumes some delay or something ... ?thanks dudes! fun stuff.

author: helius
author_rank: Super Contributor
timestamp: February 06, 2017, 12:01:02 am
content: You are supposed to use non-blocking assignments in a clocked process for sequential logic elements like D flip-flops.

author: BrianHG
author_rank: Super Contributor
timestamp: February 06, 2017, 02:34:38 am
content: Question for clarification: Are you trying to synthesize a d flipflop deliberately manually using instant gates & time the results as an exercise?

author: danmcb
author_rank: Regular Contributor
timestamp: February 06, 2017, 05:33:26 am
content: Quote from: BrianHG on February 06, 2017, 02:34:38 amyes, exactly.

author: danmcb
author_rank: Regular Contributor
timestamp: February 06, 2017, 05:35:50 am
content: Quote from: helius on February 06, 2017, 12:01:02 amwell, as Brian says, this is a flip-flop synthesised only from NAND gates. I am not explicitly declaring a clocked process.

author: danmcb
author_rank: Regular Contributor
timestamp: February 06, 2017, 04:41:21 pm
content: I get the same result if I implement the D differently:(file d_flip2.v)Code:module d_flip(input clk,input d,output q,output q_bar);reg q;always @(posedge clk) beginq = d;endassign q_bar = !q;endmoduleand all that is need to make it work is a #1 right after the first clock leading edge:(dflip_tb.v)Code:module d_flip_tb;reg d, clk;wire q, q_bar;d_flip uut(.d(d),.clk(clk),.q(q),.q_bar(q_bar));initial begind = 1'b0;clk = 1'b0;$display("time = %t: q=%b, q_bar=%b",$time, q, q_bar);#100;clk = 1'b1;#1; //<=== comment this out to break things!$display("time = %t: q=%b, q_bar = %b",$time, q, q_bar);#10;d = 1'b1;clk = 1'b0;$display("time = %t: q=%b, q_bar = %b",$time, q, q_bar);#10;clk = 1'b1;$display("time = %t: q=%b, q_bar = %b",$time, q, q_bar);endendmoduleI must be missing something simple. but what?

author: helius
author_rank: Super Contributor
timestamp: February 06, 2017, 05:12:44 pm
content: In simulation, there are multiple modules running at once. The simulator runs one timestep after another, and within a timestep, it does updates in every possible module. But it isn't smart enough to know that you wanted to use the resultqorq_barin your$display()function. It just picks an active event at random, and maybeqgets to update first, or maybe$display()gets run first.If you use$monitorinstead of$display(), it is forced to monitor the value at the end of the timestep, so you wouldn't see this problem.Seehttps://pdfs.semanticscholar.org/8cc7/6b884e551065b8822f590eabf131051882b6.pdf

author: danmcb
author_rank: Regular Contributor
timestamp: February 06, 2017, 06:32:52 pm
content: Thank you Helius! that was it!

author: danmcb
author_rank: Regular Contributor
timestamp: February 07, 2017, 07:27:30 am
content: Quote from: helius on February 06, 2017, 05:12:44 pmSo in fact, what you are saying is that the order in which things get executed within a timestep is pretty much random?

author: helius
author_rank: Super Contributor
timestamp: February 07, 2017, 03:17:28 pm
content: Not really random, but nondeterministic. It depends on the order of statements and how the compiler processes them.