Capacitor decoupling plane PCB - Page 1
Forum section: electronics / general

author: Blueled
author_rank: Newbie
timestamp: March 16, 2016, 06:01:03 pm
content: Hello!I'm new here, sorry for my not perfect english..I make a new project with a 6-layer PCB:Layer1 : Signal1Layer2 : GNDLayer3 : Signal2Layer4 : Signal3Layer5 : +3V3Layer6 : SignalI use a microcontroller in BGA256, I'll put all the components on one side (top).My question concerns the routing of decoupling capacitors, what is the right way to proceed?Like this with via and planeOr like this with routing?Thanks you

author: Neilm
author_rank: Super Contributor
timestamp: March 16, 2016, 07:28:21 pm
content: Read the datasheet for the device. There will almost certainly be a something on recommended layouts. It may be in a separate document so have a good look around.The trouble with the way you are showing it is that there will be a long track from the pins in the middle to the capacitor. Usually, the decoupling caps are on the other side of the PCB directly under the chip. Often, the internal core voltage has its own separate plane under the chip.

author: AndyC_772
author_rank: Super Contributor
timestamp: March 16, 2016, 07:32:32 pm
content: The lowest inductance path between any two points is usually through a solid plane, not a trace.So, wherever you place the decouplers, connect them into the planes using vias as close to the cap as possible. Keep the routed trace length to an absolute minimum.For a large BGA, it's normal to route each pad to a via, in such a way that there's a '+' shaped gap under the device which can be used for decouplers. Doing it this way allows the caps to be much closer to the IC than they could be otherwise.

author: nctnico
author_rank: Super Contributor
timestamp: March 16, 2016, 09:12:16 pm
content: The routing doesn't do anything else than waste space on the top layer. So decouple the planes like you did in the first picture. Even better: use 4 vias per capacitor if you have room.

author: AndyC_772
author_rank: Super Contributor
timestamp: March 18, 2016, 09:56:24 am
content: ps. I just noticed you're using red for the top layer and blue for the bottom, which is exactly what I've always done too.I can't remember why, though!Are they the default colours on some CAD package that I've long since forgotten?

author: sca
author_rank: Regular Contributor
timestamp: March 18, 2016, 11:43:24 am
content: Quote from: AndyC_772 on March 18, 2016, 09:56:24 amAlso my default colours.Possibly EasyPC? The earliest board software I remember using was a shareware program on 3.5" floppy - boardmaker perhaps?sca

author: AndyC_772
author_rank: Super Contributor
timestamp: March 18, 2016, 11:48:27 am
content: Doesn't ring any bells with me; I think the first CAD package I used was a Racal (Zuken?) product. After that I used PADS for several years.

author: ruffy91
author_rank: Regular Contributor
timestamp: March 18, 2016, 04:38:50 pm
content: When possible use multiple vias for the cap. The plane has low enough inductance so the distance between pin and capacitor doesn't really matter, but the inductance on the vias does, 2 vias gives half the inductance.

author: Feynman
author_rank: Regular Contributor
timestamp: March 19, 2016, 01:52:58 am
content: Use the method that causes the smallest loop area between 3V3 and GND. Most likely this will be the first method. You might also consider to place the two power planes closer together, since power plane distance also contributes to the loop area.Maybe the best solution is placing the decoupling capacitors under the BGA on the opposite side of the PCB.

author: Michaelbradford
author_rank: Contributor
timestamp: April 18, 2016, 12:14:20 am
content: Use viers as close to your caps as possible and all should be ok

author: tggzzz
author_rank: Super Contributor
timestamp: April 18, 2016, 07:16:20 am
content: Quote from: AndyC_772 on March 18, 2016, 09:56:24 amGo back earlier, before CAD was iused for PCB layout... "Rubylith" tape was red for top and blue for bottom.

author: Jeroen3
author_rank: Super Contributor
timestamp: April 18, 2016, 07:31:37 am
content: Whenever in doubt. Go hunting for application notes from respectable sources.Such as:http://www.analog.com/media/en/technical-documentation/application-notes/EE-253.pdfAnd remember that you'd basically want the capacitors on-die. Try to get as close to that as possible.Best you can get it inside the pcb (faradflex?) or on theopposite sideof thebga.

author: electosleepy
author_rank: Contributor
timestamp: April 25, 2016, 02:34:17 pm
content: Hi there,I can see that you have length matched signals in blue. If the signals are high speed they will also need to be impedance matched. I would recommend using layer 1 and layer 6 (microstrip) as you have done, do not use layers 3 and 4. This is because you do not have a solid copper planes either side of the signal layers to control the impedance.Also with decoupling, place as close as possible to the IC, this is because parasitic inductance in the traces is reduced.Ideally the purpose of these caps is to instantaneously supply current to the IC. If you place decoupling caps further away parasitic inductance is increased which increases the time for current to overcome the inductance and supply current to the IC.I would also use polygon pour tool to create power planes between multiple capacitors to reduce impedance. Also one capacitor is probably not going to be sufficient to reduce noise (multiple caps of varying values are best). Usually the number and value of decoupling capacitors are supplied in the datasheet.