best fpga - Page 1
Forum section: electronics / projects

author: electros6
author_rank: Regular Contributor
timestamp: February 06, 2017, 10:53:54 am
content: hi guys ,I am newbee to FPGA, which of the fpga altera , xilinx, lattice is best in terms of cost programming and developing software.

author: NivagSwerdna
author_rank: Super Contributor
timestamp: February 06, 2017, 11:16:27 am
content: I'm also interested in this question. For me I would add that I would need a device that is small cheap and probably 64-pin TQFP or similar.I was considering Lattice XO2 since mikeselectricstuff has an interesting example of using one.

author: CM800
author_rank: Frequent Contributor
timestamp: February 06, 2017, 12:30:59 pm
content: Hey,I'd dare say there are a good place to start:http://www.ebay.co.uk/itm/Altera-FPGA-CPLD-Program-USB-Blaster-Compatible-LC-MAXII-EPM240-Dev-Board-M-/152389158511?var=&hash=item237b1a066f:m:mrsZZ06TUWFngNsw1EgV1RQThat's where I began, with a CPLD, they are cheap Programmer included!Once you are familier with writing HDL on them and playing around, I'd recommend moving on to an FPGA (the step I'm moving on to)CPLDs are really basic FPGAs without all the fancy DSP blocks and all that around. You can still do a lot with them.I'm looking to move onto getting one of these:http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1021http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=998http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=836http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=941

author: alexanderbrevig
author_rank: Frequent Contributor
timestamp: February 06, 2017, 12:40:11 pm
content: I'm a beginner with FPGAs but I've had one of those cheap ebay deals laying around. My tip would be to get a board that already has some peripherals on so you can pick it up and just start doing something.It quickly becomes a bore having to make a breakout board every time you want to try something.Beware that some of them are not supported by the newest tools, so you'll have to hunt for the version that can deal with that part.Furthermore, none of the FPGA toolchains are what I'd callvery good. I've been playing a bit with all of them and have settled on the Altera as my favorite, without any better argument for it rather than I can easier relate to the thinking behind it. Highly personal opinion, so don't assume it is valid for you.If you're going for the Xilinx, I'd recommend this resource:https://github.com/hamsternz/IntroToSpartanFPGABookThe tools are free, and you can download them and have a look.I've recently ordered a board from waveshare.com;http://www.waveshare.com/product/fpga-tools/altera/openep4ce10-c-package-b.htmAlthough it does not have much peripherals on the board, I got some wings for the same effect. Their documentation seems nice, and the package is supported by the newest tools

author: Howardlong
author_rank: Super Contributor
timestamp: February 06, 2017, 01:23:33 pm
content: It took me a very long time to be in a position to actually write my own HDL, over ten years. The problem with many tutorials I've been through is that they take you just so far and then leave you hanging, so in the end all you've accomplished is the art of being a script monkey. I understood the basic concepts, but what wasn't clear was how to stand on your own two feet.The Machxo2 was the first time I made any progress, but regrettably even my first attempt at that was a fail when it turned out the 64 bit drivers for their board released at the time I tried didn't work, but to get to the stage where I realised that this was the problem I'd already given up. Fighting with the tools is never a good start.Much more recently I came across a Youtube video on Machxo2 which pretty much took me from frustrated noob to writing my own Verilog in about half an hour. Highly recommended, but take care to download the right version of tools: just finding the right version on Lattice's website is a bit of a fight as I remember.

author: hlavac
author_rank: Frequent Contributor
timestamp: February 06, 2017, 08:05:29 pm
content: Yep recommend Lattice MachXO / MachXO2 for the beginning,then maybe DE0 Nano to look at Cyclone IV and QuartusII toolchain from Altera.Maybe Zybo board if you wat to look at Zynq and Artix from Xilinx.Wouldn't bother with anything older than Artix from Xylinx, they obsoleted all the toolchains for the older likes of Spartan etc, you cant get the third party simulators for them anymore

author: rstofer
author_rank: Super Contributor
timestamp: February 06, 2017, 09:41:48 pm
content: Quote from: hlavac on February 06, 2017, 08:05:29 pmThe Xilinx Artix is the new general purpose FPGA. The Digilent Artix board is not cheap but it has some features that make it worthwhile. It uses the latest Xilinx Vivado toolchain.I prefer the Spartan 3 boards (of one kind or another) and I have Xilinx WebPack ISE 14.7 installed simply because I have so many of these boards. It seems that the simulator is now open but I haven't used it. Vivado has a simulator and, even better, it has in in-circuit logic analyzer.I haven't found simulation to be very useful. It is easier for me to simply download the code to a chip and see what REALLY happens. The simulation isn't hardware and only hardware counts. Waiting for 100k cycles to pass just to see how a state machine transitions seems, to me, to be a waste of time. There are better ways. Like blink an LED when the FSA gets to the state. This simulation idea reminds me of single step debugging of 8080 code I did some 40 years ago - a complete waste of time. Other opinions will vary...The Vivado toolchain is the only Xilinx tool with a future. ISE 14.7 is the last iteration so what it is is what it will always be. Truth be known, I like it better than Vivado just because I have been using it for the last dozen years. I'll eventually get comfortable with Vivado.http://store.digilentinc.com/arty-artix-7-fpga-development-board-for-makers-and-hobbyists/There are a lot of boards out there that are much cheaper.ETA:If you think you will build a CPU, make sure the chip you select has about 15,000 logic cells. My IBM1130 emulation takes about about 30% of the XC3S1200E chip which has 19,512 cells. That doesn't mean I would want to try to stuff it into an XC3S500E - for one thing, I want as much BlockRAM as I can get.https://www.xilinx.com/support/documentation/data_sheets/ds312.pdfBy contrast, the Artix35T chip has over 33,000 logic cells and a LOT of BlockRAM:https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdfThe point is, many of the cheap FPGA boards use very small devices. Enough to learn but not enough to do anything major.

author: hlavac
author_rank: Frequent Contributor
timestamp: February 07, 2017, 09:44:00 am
content: Quote from: rstofer on February 06, 2017, 09:41:48 pmWhaaaat... how the hell do you validate your designs without simulation & testbenches?You don't I guess...

author: rstofer
author_rank: Super Contributor
timestamp: February 07, 2017, 04:31:09 pm
content: Quote from: hlavac on February 07, 2017, 09:44:00 amLogic analyzer and "Does it work?".In the first place, the simulator was never free for ISE (AFAIK). Didn't have it, came up with alternatives. Second, I can't come to grips with writing a test bench for a CPU that might become a problem after a 100k cycles. This is far past simple logic blocks and registers/counters. I didn't have problems with trivial logic, I had issues with communications between modules (Request/Grant,DMA) and there could be a very large number of cycles before such a thing would occur.For example, the 16 bit signed non-restoring division was just a few more states in an otherwise huge state machine. But to get the CPU to execute a divide might take a bit of manipulating. Load the accumulator, load the extension, execute an instruction that pointed to the divisor (directly or indirectly), do the division, store the result and, somehow, make the result visible to the world.It seemed to me that it was faster to just download the configuration to the FPGA and let it rip so I carried a 32 bit 'debug' bus down into the modules so I could send signals up to the top module and out to a logic analyzer.I built up the CPU by adding one instruction at a time. The main FSM kept growing as I added more and more instructions. No attempt was made to minimize states or even encode the state.The biggest problem I had was not having a default state defined for the various outputs of the state machine and thus generating latches by mistake. This creates some nasty problems. Newcomers: Pay attention to this! Have a default value for every output from a FSM! Every signal must be defined in every state so learn how to define default states.One advantage I had was a decent assembler for the instruction set. I knew it worked so the input part was guaranteed. I wasn't smart enough to use 'data2mem' so I spent more time compiling VHDL than I needed to. Lesson learned.I actually had the ultimate test bench: The entire operating system including an assembler and Fortran compiler. I figured that if I could execute the factory code (boot) and compile/run Fortran programs for which results were known, I was heading in the right direction.Vivado includes a simulator.

author: Neilm
author_rank: Super Contributor
timestamp: February 07, 2017, 07:22:33 pm
content: Quote from: rstofer on February 07, 2017, 04:31:09 pmI have been using ISE webpack and it came with a built in test bench called Isim. In older versions (about version 5 IIRC) it came with a limited version of modelsim (one reason I am still on their mailing list)

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: February 07, 2017, 07:51:45 pm
content: Quote from: hlavac on February 07, 2017, 09:44:00 amNever used either myself. I just do the same as I do when writing software - build things up a step or two at a time, testing & debugging as I go.Works for me as I don't do anything especially complex, so testing and verifying on the hardware is easy, and place & route time isn't a major issue (< 30 secs). I also don't often use FPGAs, so I'd have to refresh myself on the sim tools as well as VHDL.For the stuff I do, I can't imagine that writing simulation files etc. would be quicker than just throwing real data at it. And I also wouldn't be wasting time finding errors in the simulation stimulus data.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: February 07, 2017, 07:57:37 pm
content: Quote from: Howardlong on February 06, 2017, 01:23:33 pmI'd agree with the basic nature of most tutorials. I don't recall ever seeing anything on things like setting up timing constraints, other than basic clock frequencies. Fortunately the stuff I do is typically so far inside the device specs that it's not an issue - high-speed stuff scares the crap out of me as regards producing something with enough margins for long-term reliability.The key thing to keep reminding yourself is that you are designing hardware, not writing code. If you get stuck as to how to do something, think about how you'd do it in hardware.

author: nctnico
author_rank: Super Contributor
timestamp: February 07, 2017, 08:06:42 pm
content: IMHO learning about timing constraints is essential if you go over a few MHz when using Xilinx devices. The routing software won't do anything about the delay between the input pins towards the flipflops and from the flipflops to the outputs. This can give nasty surprises. Also timing constraints can guide the place&route software so runtime is shorted. Whether to use a simulator or not depends on how quick a cycle is. On some of my FPGA projects a synthesis + P&R cycle takes close to an hour to complete so simulating a piece of VHDL before giving it a spin on the FPGA can save a lot of time.

author: mikeselectricstuff
author_rank: Super Contributor
timestamp: February 07, 2017, 08:29:12 pm
content: Quote from: nctnico on February 07, 2017, 08:06:42 pmYeah I think I'd find doing a complex FPGA project really,really annoying...One thing that can help is developing on a much part than you're intending using in production, so it takes less P&R effort, though that may be less of a benefit if routing is more constrained by timing than space

author: james_s
author_rank: Super Contributor
timestamp: February 07, 2017, 08:34:36 pm
content: I use both Xilinx and Altera FPGAs and CPLDs. The hardware choice is largely irrelevant, though it's hard to beat the $13 EP2C5T144 Cyclone II FPGA boards that are all over ebay. What it really comes down to is software used to develop them and even then there is no clear winners. There are things I like better about Xilinx ISE but overall I tend to prefer Altera Quartus II. ISE has a superior simulator, Quartus is overall easier to use and has a handy feature that lets you fill block RAM using standard hex files.

author: rstofer
author_rank: Super Contributor
timestamp: February 07, 2017, 09:01:27 pm
content: Quote from: james_s on February 07, 2017, 08:34:36 pmThe Xilinx data2mem tool jams hex code into the initialization of RAMS. In this way, the .bit configuration file is changed but a complete compilation isn't required.I quit on Quartus when I read the license. This was a long time back but the gist was that they could yank my free license at any time, for any reason, or no reason at all.I went through this nonsense with UCSD Pascal and I wan't going to do it again. FWIW, I think the license has been rewritten but I have pretty much settled on Xilinx.For Xilinx components, there are manuals describing everything you could possibly want to know (including timing). The thing is, these are in separate volumes and they are MASSIVE. Here are a couple of the Series 7 volumes:https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdfhttps://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

author: james_s
author_rank: Super Contributor
timestamp: February 07, 2017, 09:25:28 pm
content: I may have to revisit the Xilinx block ram thing at some point, I remember I tried many different things and was never able to make it work. I ended up using a tool called romgen written by the fpgaarcade guy, it works well enough but it annoys me to rely on an external tool when I can simply use the wizard in Quartus.Either way, having used both for several years now I still can't pick a clear winner, bottom line is either one will do the job, and like EDA packages, they all leave something to be desired and often have what I consider to be unreasonable licensing clauses, but they both work. If Altera (Intel) ever decides to pull my free Quartus license then they'll lose me as a customer of their chips and I'll just use Xilinx instead. I don't see them doing that.

author: MagicSmoker
author_rank: Super Contributor
timestamp: February 07, 2017, 09:36:35 pm
content: It might be somewhat heretical to say this - and for sure I am almost as much a noob as the OP when it comes to FPGAs - but I've installed Quartus II and Vivado and both are just extremely foreboding programs. I would say they are not at all appropriate for the total beginner. There may be an argument that it is better to learn one of these two behemoths to future-proof your skillset, but if you aren't planning on using FPGAs to process 4K HDMI video or other horrendously complex tasks then you might be better served starting with a more modest development suite like, e.g., Lattice's IceCube2 (see the video posted by blueskull above - it convinced me to give IceCube2 a try).

author: Dubbie
author_rank: Unknown
timestamp: February 07, 2017, 09:57:35 pm
content: Once you have got the hang of iceCube, you'll find that Vivado actually isn't that bad.I managed to figure it out well enough to complete a project I was trying to do on an Artix-7

author: rstofer
author_rank: Super Contributor
timestamp: February 07, 2017, 11:31:46 pm
content: Quote from: james_s on February 07, 2017, 09:25:28 pmI have used an approach to memory contents jamming that basically just modifies the .ucf file (ISE filetype for IO configuration and timing constraints). This is ok, and I used it for years, but it requires Place and Route to run all over again. I even wrote BASIC programs to generate the .ucf file using contents from a .hex file generated elsewhere. I guess these days it would be Python...data2mem doesn't require any kind of compilation, it jams the contents into the .bit file. But here's the glitch: You have to know where, in the fabric, the BlockRams are located and there's a bit of a learning curve to getting the configuration right. And if the place/route moves the BlockRAM or otherwise reconfigures the layout, you get to start all over again figuring out how to configure data2mem. But, if all goes well, this is a very fast way to get test code/data into a CPU project.

author: james_s
author_rank: Super Contributor
timestamp: February 07, 2017, 11:50:01 pm
content: Quote from: rstofer on February 07, 2017, 11:31:46 pmYeah that's just a pain in the ass though for what I'm doing, compared to just create a new ROM instantiation, select the parameters, choose the .hex file I want to load it with and presto, it's created and ready to go.As far as the software, I found Quartus and ISE both to be reasonably easy to learn how to use, at least to the extent that I need to use them. That pales in comparison to the learning curve involved in actually developing something worthwhile in HDL. I think it took me about 2 years of banging my head against a wall before something finally clicked and it was just like one day I suddenly could do it. I'm still far from an expert, but I can put together and modify blocks of code written by others, write my own glue logic and simpler subsystems but there's no limit to what remains to learn.

author: brucehoult
author_rank: Super Contributor
timestamp: February 08, 2017, 10:08:29 am
content: Quote from: rstofer on February 06, 2017, 09:41:48 pmAnd a lot that are much more expensive!I'm tempted to get one of these "Arty" boards because that's what SiFive supports downloading the design for the HiFive1 into. It only runs at 65 Mhz vs 320 MHz for the production board with the SoC, but that's still not horrible. $99 seems relatively reasonable.The FPGA board they use for simulating their upcoming Linux-capable SoC (Xilinx Virtex-7 FPGA VC707) is $3500!!!!! And it still only runs at 65 MHz.Quote from: rstofer on February 06, 2017, 09:41:48 pmWhen a chip spec says it has "15000 LUTs" or whatever, how do you know how many bits of input those LUTs have? Does it implicitly mean 2-input, or what?

author: hans
author_rank: Super Contributor
timestamp: February 08, 2017, 11:47:16 am
content: Simulation test benches is like test driven development. You develop some feature in a module of your project, write a testbench for it that stimulates a situation, and then asserts the result. In particular edge cases are interesting to test, which I don't think you will be doing every iteration if you deploy it on real hardware.The latter is often key in creating useful testbenches and often not taught unfortunately. Most testbenches I had to write at college were visual based.. you stimulate inputs and then look at the waveforms to verify if it is correct. That is great.. but VHDL is more powerful. You can check your expected behaviour in code, run your library of tests, and see where things start to break once you tweak a process in a module.This however does require effort to set up and for some projects it does not pay off.Oh and yes.. the small boards that are cheap are often the low end devices of the series. Sometimes you will see "Cyclone IV" or "Spartan 6" chip, but it's the smallest in the series with only 20kB of Block RAM when utilized in 8-bit wide mode. If you're doing a CPU project or something similar, then that's maybe OK to simulate a small PIC16 or AVR alike core, but not great if you want to write your own 32-bit processor with 64kB of RAM.

author: nctnico
author_rank: Super Contributor
timestamp: February 08, 2017, 11:54:24 am
content: Quote from: rstofer on February 07, 2017, 11:31:46 pmIn my projects I usually integrate some way to load blockrams from a processor/microcontroller.

author: rstofer
author_rank: Super Contributor
timestamp: February 08, 2017, 03:15:48 pm
content: Quote from: brucehoult on February 08, 2017, 10:08:29 amThe number of bits of input (width) of a LUT (Look Up Table) is usually a parameter of a particular chip family. Usually (and I'm hesitant to use that word), the LUTs are 4 bits wide so, by itself, the LUT can implement any of 16 functions of 4 bits. It's a Look Up Table - put in a 4 bit 'address' and get back a 1 bit result. Xilinx has newer families with 6 input bits so 64 functions can be implemented.Here is a much better explanation:https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdfFor reference, the Artix board uses the 7A35T chip Table 1-2Slices are the fundamental unit and they are quite complex. See pages 19 and 20 for the 2 different types of slices and a block diagram of their function. It would be very interesting to design at the slice level. The sythesizer does a good job as does place/route but it would just be fun to get down to the nitty gritty.

author: brucehoult
author_rank: Super Contributor
timestamp: February 08, 2017, 08:19:36 pm
content: Quote from: rstofer on February 08, 2017, 03:15:48 pmThanks! I've downloaded that manual and starting to have a look.However: "Usually the LUTs are 4 bits wide so, by itself, the LUT can implement any of 16 functions of 4 bits. It's a Look Up Table - put in a 4 bit 'address' and get back a 1 bit result. Xilinx has newer families with 6 input bits so 64 functions can be implemented."That can't be right :-)There are 16 functions of two input bits. Two input bits can each be 0 or 1, so there are four combinations: 00, 01, 10, 11. Each of those combinations needs one bit of storage to specify the output for that input combination i.e. 4 bits of config. Those 4 bits of config can take on 2^4 = 16 values, hence there are 16 possible functions.Here are the 16 possible functions of two bits, x, and y:01x~xy~yx&yx&~y~x&y~x&~y = ~(x|y)x|yx|~y~x|y~x|~y = ~(x&y)x^y~(x^y) = ~x^y = x^~y = x==yA LUT with 4 inputs needs 2^4 = 16 bits of config, and can encode any one of 2^16 = 65536 functions.A LUT with 6 inputs (as in that 7A35T) etc needs 2^6 = 64 bits of config. Those 64 bits of config can implement any of 2^64 = 18,446,744,073,709,551,616 different functions.

author: rstofer
author_rank: Super Contributor
timestamp: February 09, 2017, 12:00:08 am
content: Yup! 22nI knew that! I just had my head up and locked...