The small open source IC allows us to use RS485 like full-duplex (up to 50Mbps) - Page 1
Forum section: electronics / general

author: dukelec
author_rank: Contributor
timestamp: December 25, 2023, 09:22:03 am
content: As we know, RS485 physical layer is half-duplex, even if there are only two nodes on the bus, such as a PC and a device, the device can not take the initiative to send data to the PC, because it may conflict with the data sent by the PC.This is the main reason why RS232 can never be replaced by RS485. In addition to not being able to full-duplex, other aspects of RS485 are much better than RS232, such as longer distances, higher speeds, can be connected to more nodes, more anti-interference.However, it is now possible to virtualize a full-duplex line between any two nodes on a half-duplex RS485 bus with this small chip.For example, if there are four nodes A, B, C and D on the bus, A and B can send data to each other at will, and C and D (or A and C) can do the same, and there will be no data conflict.It also supports multicast communication: A sends data to C and D at the same time, and supports broadcasting: for example, A sends data to B C D at the same time, and then B C D can reply to A at the same time.The principle of the chip is actually very simple, it is a SPI to UART controller, the UART side has a fixed packet format (original address, destination address, data length of a total of 3 bytes frame header + user data + 2 bytes CRC tail), the chip's UART port can be connected to the RS485 interface chip to control the RS485 send and receive, SPI port is connected to the user MCU.This UART controller introduces the arbitration function of the CAN bus, except that the sending and receiving follows the standard serial 8N1 format (one start bit, eight data bits, one stop bit, no parity bit).When transmitting on RS485, arbitration is performed by the first byte of the packet header (the first byte is the sender's address), and non-destructive arbitration is performed by bitwise readback, so that the node with the highest priority has first priority to use the bus, and the node with a low priority, the data will be retransmitted later automatically.When sending the first byte, RS485 is half-drive output, because there is a delay in readback, the rate is recommended not to exceed 1Mbps.Since RS485 supports full-drive output (push-pull), so from the second byte, you can use a higher transmission rate, the rate of this chip can reach 50Mbps (similar to the CAN FD dual-rate, but due to the high speed part of CAN FD is still half-drive output, so the rate is restricted).When using the arbitration mode, you need to keep the rate of the high speed part and the low speed part the same when you need to be compatible with the traditional serial port.The chip also supports another mode, which can use high speed baud rate throughout the whole process, and can also use RS485 as full duplex - Break Sync mode.The principle is not complicated, after the bus has been idle for some time, if a node wants to send data, it needs to send a break character (a special serial character with 10 consecutive bit 0's) first.The function of the break character is to bring the bus out of the idle state, and if more than one node sends a break character at the same time, there will be no harmful impact.After waiting for the bus to become idle again, each node waits a different amount of time to send data, with higher priority nodes waiting a shorter amount of time. Since each node waits for a different time, no data conflict occurs.This mode is suitable for buses with a relatively small number of nodes; with a larger number of nodes, the maximum waiting time becomes longer, reducing efficiency.In addition to the above two peer-to-peer communication modes, it also supports traditional full-duplex and traditional half-duplex modes, and can be used as an ordinary serial expansion chip.Chip source code and details:https://cdbus.orgThe CDBUS IP core is free for FPGA users.Datasheet: attached below.Related open source projects:Semi-automatic desktop SMT machine CDPNP:https://github.com/dukelec/cdpnphttps://www.eevblog.com/forum/manufacture/(cdpnp)-tiny-open-source-pnp-machine-upgrade-nozzle-and-chip-auto-calibration/CDFOC brushless motor FOC controller :https://github.com/dukelec/cdfocCDSTEP stepper motor controller :https://github.com/dukelec/cdstepCDCAM Serial Camera:https://github.com/dukelec/cdcamCDBUS-BRIDGE (USB to high speed RS485 converter):https://github.com/dukelec/cdbus_bridgeCDBUS-GUI open source serial software, supports parameter configuration, waveform display, IAP upgrade:https://github.com/dukelec/cdbus_gui

author: peter-h
author_rank: Super Contributor
timestamp: December 25, 2023, 12:12:43 pm
content: It's a nice idea but about 20-30 years too late.Industrial building-wide comms has mostly moved to ethernet, 232/485 is still widely used for instrument interfaces (because it is cheap, simple, and "just works") and those who want to run 232 over a long like use a serial-ETH box which the chinese make for two a penny.Nowadays, with the painful lessons learnt during the covid-manic shortages, nobody should buy a single sourced chip like this. The open source IP, usable in an FPGA, is very admirable, but FPGAs are awfully expensive.

author: dukelec
author_rank: Contributor
timestamp: December 26, 2023, 08:57:57 am
content: Thank you for your reply.I don't think it's too late, serial communication has always been the simplest and most basic form of communication, and we don't have to worry about it becoming obsolete in our lifetimes.In addition to this chip, you can also use the following small module with Lattice's iCE40UL FPGA, which is completely open source, and the price of this FPGA is about 1.5 USD.You can also use Chinese FPGA, such as Gowin's FPGA with the same capacity, the price is around 0.6 ~ 0.7 USD.And there are already some soc companies using CDBUS, for example, Ingenic's X1600(E) CPU has a built-in CDBUS controller:More MCU / CPU with built-in CDBUS controller will be released in the future.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 26, 2023, 09:16:48 am
content: I tend to implement this kind of stuff in-house, so personally not really interested - nonetheless, this looks like a good idea and I'm sure many could definitely make good use of that.Bonus point for releasing it open source, allowing implementation on very modest FPGAs.

author: voltsandjolts
author_rank: Unknown
timestamp: December 26, 2023, 02:55:38 pm
content: @dukelecInteresting.How much does it cost to get a small asic like this CDCTL01A produced in China?Can you point to some providers?

author: dukelec
author_rank: Contributor
timestamp: December 27, 2023, 03:51:32 am
content: This chip is SMIC 180nm process, I can't tell you the exact cost due to NDA limitations, this is the company I chose:https://www.britesemi.com/en/There are many other cheaper services and fab plants, but I didn't choose them to ensure the quality of the chip.The approximate cost (without design service fee) can be found athttps://www.reddit.com/r/chipdesign/comments/14pea2o/mask_and_wafer_cost_at_smic_180nm_or_350nm/If you need further information, please email me.