Vias as belt and braces? - Page 1
Forum section: electronics / general

author: paolo
author_rank: Contributor
timestamp: November 28, 2012, 01:30:49 am
content: I've been laying out my first board. It's fairly simple, a driver chip and a bit of decoupling. Because it's based around the TI TLC5947, I've been taking some inspiration from the TI demo board.One thing that's puzzling me... there's lots of vias all over the place, not just the minimum needed to bridge between layers.Is there some kind of design principle of adding them beyond just making basic connectivity? e.g. minimising signal paths between areas of pours, or adding robustness by making the connections diverse? I'm guessing at the moment.The board I've been using as inspiration:http://e2e.ti.com/cfs-file.ashx/__key/CommunityServer-Discussions-Components-Files/192/3872.TLC5947_5F00_Layout_5F00_PCB.pdf

author: poptones
author_rank: Frequent Contributor
timestamp: November 28, 2012, 02:29:38 am
content: Think of every connection on the board as having two wires - the wire from the driver to the load, and the wire returning the ground.Now, imagine the ground wire runs all over the place, in this spaghetti path, back to the driver. What happens to the inductance of that connection? What does the ground look like? Remember, electricity follows the path of least resistance. So is the ground return path at high frequencies going to be distributed evenly across all the copper and vias?The vias minimize inductance of the return path.

author: paolo
author_rank: Contributor
timestamp: November 28, 2012, 03:24:35 am
content: OK - that makes sense, and will I'm sure help me place extra vias sensibly. Thanks.But here's another question, specifically about the board design I linked to.See the top edge of the board? There's a line of vias up there, and I can't figure out how those would help shorten the return path. To my eyes they're bridging the top and bottom and ground pours, and yet the nearest ground components seem to be miles away. Maybe there's something else I'm not understanding.

author: SeanB
author_rank: Super Contributor
timestamp: November 28, 2012, 04:39:31 am
content: They join the 2 planes so that they do not act as antennas.

author: paolo
author_rank: Contributor
timestamp: November 28, 2012, 04:46:17 am
content: Quote from: SeanB on November 28, 2012, 04:39:31 amMore enlightenment.Good practice to scatter some round the edges of the planes then, fixup the outer reaches?(You may be realising my analogue is massively beginner level.)

author: SeanB
author_rank: Super Contributor
timestamp: November 28, 2012, 04:11:58 pm
content: They join the copper on the bottom to the large copper plane on top ( via all those thin traces between the pins) so that they reduce radiated noise from the board. You should ideally have the planes joined on all sides with vias and a scattering of then on the board as well, especially around decoupling capacitors where multiple vias reduce the inductance of the connection as well as the resistance. On some boards you will find a copper strip soldered all around the board edges as extra screening.

author: paolo
author_rank: Contributor
timestamp: November 28, 2012, 05:27:54 pm
content: Ah - interesting point about the decoupling capacitors.I've just now posted my board design up - at the moment without the benefit of that advice. I will make note.

author: Neilm
author_rank: Super Contributor
timestamp: November 28, 2012, 07:59:42 pm
content: The vias should be spaced at 1/10 the wavelength of the highest frequency of interest.Neil

author: paolo
author_rank: Contributor
timestamp: November 28, 2012, 09:18:03 pm
content: Quote from: Neilm on November 28, 2012, 07:59:42 pmUmm. Now I'm lost. At, say, 1MHz, what does that mean? Is there a formula I can use?

author: jeroen74
author_rank: Frequent Contributor
timestamp: November 28, 2012, 11:23:11 pm
content: It's not the frequency per se that's important, but the rise and fall times of signals. A 1KHz square wave with 1ns edges likely gives more problems then a 100MHz sinewave.

author: paolo
author_rank: Contributor
timestamp: November 28, 2012, 11:42:00 pm
content: OK, will scope the edges and report back.

author: Mechatrommer
author_rank: Super Contributor
timestamp: November 29, 2012, 12:01:40 am
content: Quote from: jeroen74 on November 28, 2012, 11:23:11 pmyes risetime is more important as it translates the highest harmonics content. my ROT to get a rough figure is Fcontent = 1 / (2 x risetime). so 1ns risetime has 500MHz harmonics. this way easier for me to think frequency'wise. as placing via, if you can afford or the pcb house allows, place the via anywhere you can and like to, even at 1/100 or 1/1000x wavelength