Microsemi/Microchip Polarfire tools . what are they like ? - Page 1
Forum section: electronics / general

author: glenenglish
author_rank: Frequent Contributor
timestamp: June 05, 2024, 05:24:31 am
content: Has anyone got any Microsemi/Microchip Polarfire tool experience (and also has other tool experience)what's it like ?I'm considering Polarfire for something.I've used Lattice, was a bit "meh". XIlinx is good. Efinix is ... getting better.-glen

author: Daixiwen
author_rank: Frequent Contributor
timestamp: June 06, 2024, 09:37:25 am
content: I'm using Libero SoC with Polarfire FPGAs and it's... a huge step back from Vivado, but it's usable. It crashes from time to time but it is usually solved by clearing the project and opening it again. It does have sometimes the huge kind of crash with no information about the error and where you can spend days headscratching trying to find the cause.The FPGA itself is great. The documentation for the hardware part is okay, but the documentation for the embedded software... well if you try to do anything that is a bit different than their examples, you will struggle a bit. Also their examples look like they have been written by trainees straight out of university. They work, but there is a lot of inconsistencies and code quality vary a lot from module to module. I have nothing against using trainees, but maybe not for code examples that are supposed to show their customers how to properly do thingsFPGA debugging is the least practical offer of the 3 tools I tried. It's even less usable than the one from Vivado, and I really miss the ease of use of SignalTap (Altera).Integration between the hardware (Libero) and software (SoftConsole) design tools is... meh. On par with Altera, and also a step back if you are used to the Vivado integration with Vitis.if you have any specific question I can try and answer.

author: glenenglish
author_rank: Frequent Contributor
timestamp: June 06, 2024, 09:53:17 am
content: Hi Daixiwenthanks for the comments. Yeah, FPGA reads as a good feature set.Since that post, I've read a bunch of reviews and options and forum discussion I have read lead me to think I should avoid it ....My stuff is low volume , time expensive so I dont want the tools crashing. I'm used to the best tools , though they all suck to some degree.I'll stick with the Ultrascale+ MPSoC / Spartan 7 / AU7PYou know what it's like- there is alot invested in knowing the device..... The MPSoC is a beast to know. There didnt seem to be as much doco on the Polarfire SoC as I would expected there needed to be.There is a big step up in XIlinx device cost when going to any sort of SoC with 10 Gbit transceivers, mainly because their mid tier stuff has all 6 Gb transceivers.I use mostly ZU2CG, has 4 x 6Gb transceivers. But I've been sniffing around for devices that handle 10 Gb ethernet easily.I've also been evaluating and done a couple of designs with Efinix Titanium. and we're still waiting for the Ti375, at least the pinout of the 1152 BGA device with 16 x 12 Gbit transceivers is out..... That's a killer if the place and route tools can improve.Local support here in Australia is good for Microchip, Like you say, the Polarfire FPGA devices are good.regards,

author: Daixiwen
author_rank: Frequent Contributor
timestamp: June 06, 2024, 10:36:15 am
content: My personal list by order of suckiness (from least to most) is Vivado, Quartus, Libero. So yes if it's a low volume and you can absorb the higher cost of the FPGA, just use a Xilinx. It may not be worth the time to get used to Libero

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: July 10, 2024, 11:36:39 pm
content: I have used Libero and Vivado and Quartus for many years.5+ Quartus.3+ Libero.1+ Vivado.I would recommend to anyone, if you love your life, if you love sanity, if you don't want to commit suicide then don't use Libero.The silicon from Microsemi is quite nice. The documentation is ok, could be better. But the tools are hopeless. The debug features look good on paper but often crash or show "Error detected" or "Uknown error occured" and crash and there is no way to really find out what was the actual problem.I would say from personel experience that if you want people to hate being an engineer and just resign and leave, put them on project that uses Libero and don't let them change. In best case scenario they will resign and worst case scenario they will commit suicide after shooting everyone in the office.I am not joking. If you have choice then NEVER go for Libero. You want their silicon? OK. Prototype design and test it with Intel or Xilinx tools and then put it on Microsemi FPGA.Intel/Altera tools are best when compared with the rest, their silicon lags behind Xilinx. Microsemi is mainly niche with their ProASIC and Flash based FPGAs.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 10, 2024, 11:44:06 pm
content: Hi. thanks for the commentsSeems to be a common theme with microchip/microsemi - . love the silicon. tools suck++.Altera is on a leapfrog with XIlinx right now with the Agilex 5 I think, at least in midrange . looking good. same tools and datasheets for 30k-3M gates . just speed diff. which is interesting that they have a seemingly 2:1 speed binning on the same mask set (10nm) .I really wanted to use Polarfire SoC/ Polarfire 2 SoC . but, back to ZYNQ for the moment.. groan.... (for designs where the MPSoC is too much chip) .I dont mind Efinix tools, they dont do much, so I guess cant get into real trouble and lately dont crash.

author: tom66
author_rank: Super Contributor
timestamp: July 11, 2024, 09:53:59 am
content: We use Libero for some of our products and it is bloody terrible. The implementation and synthesis is single threaded and very slow. The timer/retimer is highly sensitive to minute variations in logic design which can create non-working products very easily. The tool crashes easily and has other random bugs and errors (not that Vivado is immune to this but it occurs less often!)

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 11, 2024, 11:08:23 pm
content: Quote from: tom66 on July 11, 2024, 09:53:59 amYes, I have also had to work with Libero at some point, and it was very painful. It was a few years ago though, but I'm guessing that it hasn't much improved.

author: Daixiwen
author_rank: Frequent Contributor
timestamp: July 12, 2024, 08:23:45 am
content: The only thing changing in new versions of FPGA tools over time is the installation space taken on the hard drive

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 23, 2024, 01:11:41 am
content: I am told - new "Polarfire Studio" is coming next year....

author: tom66
author_rank: Super Contributor
timestamp: July 23, 2024, 09:28:07 pm
content: If that is true, very good news, but let's hope that it includes a ground-up rewrite of the FPGA tool. No point at all just putting new clothes on Libero.

author: glenenglish
author_rank: Frequent Contributor
timestamp: July 24, 2024, 10:25:53 am
content: Hi TomI'll buy an eval kit (polarfire or pic64) which will probably give me some lead in my pocket to get some early access..IE pay to play....Polarfire2 public release is 2 months.Price wise, Zynq still beats Polarfire hands down -- if you dont need the transceivers and the low power consumption , and all those RISC-Vs. These days I like SoC devices because they simplify splitting the hardware and software once I hand over a project to "sustaining engineering and further feature development"....

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: August 01, 2024, 01:23:04 pm
content: Microsemi Libero as one of the most abhorrent and soul sucking abominations ever created. If you don't want to end up on medication for depression and anxiety, never use it as your primary tool. If you need their silicon, use some other Altera or Xilinx to prototype the design.Those that love life and want to stay away from mental health disaster will avoid Libero like a plague of biblical proportions.

author: iMo
author_rank: Super Contributor
timestamp: August 06, 2024, 10:40:01 am
content: I've got to try a 20y old proasic3e kit and tried with the Libero 11.9SP6 (the latest downloaded from Microchip site, free silver license). I do it not because I do not love my life (or because I want to deepen my mental health disaster), but from the nostalgia as the Actel was the first fpga/cpld I ever worked with (2000 gates antifuse OTP one, in 1991 with ViewLogic). So I could not resist the temptation to try with the 1.500.000 gates oneAfter several days and nights coping with IDE, programmer and the board jumpers/switches, it works now, and I can build and blink the leds..The Libero is quite sensitive on the sequence of operations you do, I often get the ".lok" file where I have to delete it in order to proceed at certain step further on. Also FlashPro programmer works here in stand alone mode only.The issue I had was with the fpga's pins assignment, as sometimes it somehow changes the assignment to a random one and the fpga did not work as expected of course (there is none "Save" in pin planner window). So it seems to me the order of saving the data in various opened windows of the IDE sometimes creates a mess, but when you get the feeling how to do it it works reliably.Otherwise I cannot say it is not useful or a crap, of course it has its quirks. The smartdesigner gui works as well, and it is comparable with quartus or ise14.7 I've been using from time to time.The major disappointment here is with my fpga chip - it has an onchip flash for the setup, but the internal sram (or at least a part of it) cannot be init off the internal flash, as there is none internal flash for the sram init at all (there is a 1024bit user flash only)..This problem might not exist with the polarfire/smartfusion/igloo2 devices, however.Now, I've been trying with its CoreABC ucontroller (luckily it uses the versatiles for its rom emulation) and CoreSPI IP blocks to learn how to read an external spi flash and feed the data into the internal sram such I can use the sram somehow.If any experience with it I would be happy if you may share (a different thread perhaps)..

author: iMo
author_rank: Super Contributor
timestamp: August 07, 2024, 08:06:29 am
content: Quote from: iMo on August 06, 2024, 10:40:01 amFYI - the 11.9SP6 is the "latest version supporting ProAsic3E chips", not the latest Libero version generally.The higher Libero versions do not support those older chips anymore..

author: glenenglish
author_rank: Frequent Contributor
timestamp: August 07, 2024, 08:26:38 am
content: well 20 years is enough I think

author: iMo
author_rank: Super Contributor
timestamp: August 07, 2024, 09:03:15 am
content: Yep, but the proasic3 chips are not a crap, actually, pretty good ones for education, experiments and small retro projects, etc.What was a lovely Actel's marketing trick is the designation of the chips like ProAsic3e1500 with 1.500.000 "gates" used to used as the first info on the page 1 of their datasheets, I like it.. I have to doublecheck, but the meaning of "sea of gates" in 1991 meant something different..Those ProAsic's "gates" are not accessible, of course, the smallest entity you work with are the VersaTiles, so it is a sea of Versatiles..Each VT consists of aprox 40 "gates", thus you get those 38k "equivalent VTs or DFFs" (page 2 of the DS).And you would need perhaps 5-6 VTs in order to get a single logic cell somehow compatible with for example Spartan6.Yes, 20 years is a long time in this biz..

author: iMo
author_rank: Super Contributor
timestamp: August 07, 2024, 10:37:21 am
content: This is a small example I've found on the web, added comments to the CoreABC ucontroller program, and enhanced its functionality significantly with a cryptographic strong encryptionThe entire stuff to create, build and test fits into 40minutes with the students, for example.. (provided the lecturer is prepared enough)..It receives data via UART (115k2 8N1) and mirrors it back, with an opened Teraterm you may encrypt/decrypt the stream while passing it twice, and it works..The stuff takes 477 VersaTiles (out of 38400 available).

author: matrixofdynamism
author_rank: Regular Contributor
timestamp: August 12, 2024, 09:51:38 am
content: Older devices will have better support.My experience with Libero has been incomplete support of silicon. It is where a feature is supposed to be in the program but Microsemi says it is on our backlog. Then there is the weird split between Libero and its 3rd party synthesis tool "Synplify" and debug tool "Identify". They both have an ancient feel to them.Libero gives obscure errors but the project compiles. How come? That is because Synplify does not actually think those errors exist so Libero is wrong.Now Libero's own SmartDebug can't be used at the same time as the Identity program. Why such a limitation? Anyway, looking at SmartDebug,Reading IGLOO2 Flash causes it to crash straight away, although it worked fine for the first few months. No one knows what has changed in the FPGA flash to cause the whole program to crash now.When I use the Probe Insertion, more than 50% of the time it says "Error occured" or "Unknown error occured". So I can't get an probe insertion. Also, sometimes it says that the operation was completed, but there is no active probe actually formed since no signal is coming out.When I use the active probe, it works often but sometimes it again fails to get the internal signal to the outside.When I use the live probe, I can't find the signals I am looking for but it does work often for read. When I want to write, it does not work most of the time and I get error message that is again without any description of what the actual problem is, so it can't be investigated.Libero has no TCL console like Quartus and Vivado. Another serious problem. In my case when I was using IGLOO2, there was no TCL command to generate the SystemBuilder component. I could not automate the project creation. When I asked them if there is a workaround they said that they don't know of any, but if I find one, I should tell them about it.Libero generates a whole plethora of files, its impossible to know what exactly to put into version control for a project that contains more than just few HDL files. Even Microsemi don't know. I am saying this since I asked them about it.Biggest problem I had. Project compiles fine and after few few it compiles but does not work anymore. How come? Well the netlist generated by Libero is suddenly no longer consistent. Delete project and create Libero project from scratch again, now it will correctly work, for few weeks atleast. No one knows what is getting corrupted inside Libero suddenly that my project netlist starts to mutate on its own. I enter a line break into a HDL file and just like that I get a new broken netlist. I put a comment into a file and just like that I get another broken netlist. I can't automate the whole thing since Microsemi still has not put in TCL command for some of the features and IP that I was using in the project. SO I create a new project, a tedious task since I am using so many IPs.Moving to latest version of Libero does not help at all to fix these issues.Microsemi FAE was totally useless since he was basically a sales guy. Microsemi customer support tried their best to help but with a tool so broken there was not a lot that they could do. They just said ok, we will note this as a bug to fix or a feature to introduce or our software team will investigate and this and that. They were able to help me on several occasions but the big problems could not be resolved since they are fundamental to the program.This all happened only few years ago. There is a lot that happened but I have put the main recurring issues in this post. It has cause permanent damage to my brain.