RDS ON Sanity Check - Page 1
Forum section: electronics / projects

author: Wilksey
author_rank: Super Contributor
timestamp: October 05, 2021, 03:22:00 pm
content: Hi,It has been a while since I specc'd a MOSFET and I think I remember my equations but would like someone to double check for me if possible!I have a P Channel FET (NVD5117PL), and it states that at VGS -10V the RDS-ON value is 12mR (Typically). There is a graph in the datasheet that shows resistance vs temp and I read somewhere that this shows 0.5% each degree above TA (25degC), so if I am aiming for theoretical TJmax of 60, then that works out to 0.5% * 35 degrees, so for my calculation I did 12mR * 1.175 which gives me around 14.1mR, does this seem right?Next I wanted to look at power dissipation and maximum power dissipation.For max power I used the TJ-MAX of the FET as listed at 175degC, minus my theoretical TJMax of 60degC and divided it by RthetaJA of 37degC/W which gave me 3.1W (115/37), am I right in thinking that this is the maximum PD before requiring a heatsink, the FET will be on a big plane with quite a few VIAs.I calculated that my max PD at a max of 3.2A (more than likely be 1-2A), would be my 14.1mR from above * sqr(3.2) = (10.24) which works out to around 0.144W.Do my calculations seem correct or have I cocked something up?Cheers all.

author: Wolfram
author_rank: Frequent Contributor
timestamp: October 05, 2021, 04:48:33 pm
content: From the Rdson vs. temperature plot on page 3 (fig. 5), it looks like it's more like 20 % up at 60 C. Note that 12 mohm is the typical Rdson, worst case is 16 mohm.Your calculation of maximum dissipation is correct, with some assumptions. Their figure of 37 k/w assumes that the drain tab is solidly bonded to a 650 mm^2 copper pad of 70 um thickness. Note that most common PCB processes are 18 - 35 um thickness. 70 um is commonly available, but at a higher cost and with larger minimum trace width and clearance. It also assumes that ambient is 25 C, which is often not the case. Other components dissipating power in the vicinity can raise the ambient temperature significantly, and placing a board inside a box can also do the same. Due to these uncertain factors, you can either design conservatively with plenty of margin, or do calculations, simulations and measurements to find the real values for Rth_ja and Ta in your design, under real world conditions. It sounds like a lot of work, but it can be both interesting and educational, especially if you have access to a thermal camera.Calculating PD is complicated by the fact that the rise in temperature comes from on power dissipation, but power dissipation also depends on temperature due to the change in Rdson. You might have to iterate on the calculations back and forth to get a final value. Your estimate looks to be in the right ballpark here.

author: Siwastaja
author_rank: Super Contributor
timestamp: October 05, 2021, 04:52:29 pm
content: You did something weird with the temperatures. 175degC shouldn't be part of equation (after you chose Tj lower than that, although you went quite low!)You need to decide some maximum ambient temperature for your device, and if enclosed, understand the thermal behavior of the whole system so you know the "local" ambient at the PCB. Then, maximum power dissipation is defined by RthJ-A and the difference between Ta and Tj.Choosing Tj=60 is ridiculously low though because ambient practically is often something like 40 degC, or if the device is used in sunny car, then easily Ta=50degC or more. This leaves very little over the thermal gradient J-A, and limits power more than it needs to be. In other words, it'stooconservative to be practical.These parts that are rated to Tj=175degC max survive happily for a long time at Tj=125degC, though I tend to limit myself to Tj=100..110degC if at all possible. At such high temperatures though you should multiply Rds_on by 1.5.And use MAX value for Rds_on, not the TYP value.

author: Wilksey
author_rank: Super Contributor
timestamp: October 05, 2021, 07:13:39 pm
content: thank you both for your replies,@Wolfram, I was going to spec 2oz copper, which I believe is 70um?I was going to stick with 25deg ambient as it will sit in a shed in the UK (bare board, screwed to a bit of wood) and apart from the height of summer when it might reach that at ambient it'll always be below that in the shed (I have a temp sensor in there already and it is now reading 11deg), I thought 60 sounded like a decent max temperature to aim for, though it might be a bit low, I looked at the chart and as 25 is essentially 1 on the chart I looked at the difference between 60 and 25 which is 35 and estimated the value, I might be way off however, and i may be working it out incorrectly.I was going to recalc with max RDS On but wanted to double check everything first to see if I was doing it correctly.I always use "ambient" for whatever it is inside the place it is going, if it is inside a case i'll stick a probe in the case, but for bare board in the shed I presumed the ambient temp of the shed would suffice and I don't think i've seen it go over 25deg maybe once or twice?So do you think it would be worth adjusting the ambient temp and my theoretical TJ Max from 60?I have a IR Thermal gun, so I can see what it does on the bench but I was hoping with a nice slab of copper it would not need a heatsink and that seemed quite low when I calculated it but I did it 3 times and it came out the same each time so I wanted to check my calcs.

author: Siwastaja
author_rank: Super Contributor
timestamp: October 05, 2021, 07:16:15 pm
content: If the bare PCB sits on your max 25 degC shed uncovered in free air, and you follow the layout for which the RtjJ-A was given, then the calculation is OK with Ta=25 degC. This is just quite a special case IMHO.With such exceptionally low Ta, you can of course practically aim for such low Tj. Usually you aim a bit higher because you can, these components are really fine at Tj=100degC or even more.

author: Wilksey
author_rank: Super Contributor
timestamp: October 05, 2021, 07:48:11 pm
content: To be fair this is for a personal project, but most of the designs at work often revolve around 25degC ambient, this is just a follow on from the old EE's that are probably now dead who retired about 10 years ago.In this case though the shed has never got above 25degC apart from a few times where it might have reached a few deg above, but I figured there was enough overhead to cope for those rare occasions.Thanks for confirming the calcs are correct, I shall have a play with the values and see what they look like with higher temp ratings, I think it'll be within the no heatsink usage zone, I'll be using the IR thermal gun and put it in rooms at a higher ambient temp to see how it behaves.So if you were designing something similar, you would use TA = 50deg and TJ =100?

author: Siwastaja
author_rank: Super Contributor
timestamp: October 06, 2021, 07:04:25 am
content: Yes, usually Ta=50 and Tj=100 for projects that sit in "normal" indoor environments with casing that allows cooling.In a tight, closed case, the casing itself needs to be thermally modelled - or simply tested, there is no way around that.

author: Wilksey
author_rank: Super Contributor
timestamp: October 06, 2021, 09:35:19 am
content: Thanks for the advice, I changed TA to 60 and used the max RDSon of 16mR and the calcs came out to about 0.24W from 0.14 so I *think* that will still be OK, I shall see what the actual temperatures are vs calculated if I build it up.

author: Psi
author_rank: Super Contributor
timestamp: October 06, 2021, 10:27:23 am
content: Don't underestimate the thermal benefit of going from say 2 layer 2 oz to 4 layer 2oz.I went from 2 layer 2 oz to 6 layer 3oz and the fet temps went from 100C to 40C

author: Wilksey
author_rank: Super Contributor
timestamp: October 06, 2021, 04:49:40 pm
content: Interesting, seeing as 4L isn't much more than 2L these days I might just do a 4L.With 2L would stitching top + bottom with the drain signal help temps at all?

author: Siwastaja
author_rank: Super Contributor
timestamp: October 06, 2021, 05:52:25 pm
content: Stitching works, even when the copper wall in the via is thin, it's still better than FR4. Vias are usually free of cost so why not add 50 of them. Thermal resistance of a 0.4mm via is some 120K/W IIRC. This number is of course useful only for vias close (under, or right next) to the MOSFET; if you add too many, some of them are far away and heat needs to travel through the copper layer sideways first.Filling the via with solder increases thermal conductivity by some 30-50% maybe - solder is much worse at conducting heat but the layer inside via will be thicker than the copper. This is trivial to do when hand soldering. For manufacturing, you can add small circular paste openings over the vias (only to see that your contractor removes them as they think you made an error).With 4-layer, the key is that the added internal layers areveryclose to the external layers, like just 0.2mm apart; compare this to the typical 1.6mm between external layers in 2-layer design. FR4 is quite acceptable thermal conductor when this thin, meaning, you can transfer a lot of heat to your ground planes without the vias, keeping functional electrical isolation, simplifying everything; just pour the mid layers full of copper and ground it regularly for good EMI performance, and thermals improvea lotas a side effect basically for no extra effort.

author: uer166
author_rank: Super Contributor
timestamp: October 06, 2021, 07:50:50 pm
content: Quote from: Siwastaja on October 06, 2021, 05:52:25 pmNot just functional, but in most cases that would count as a "cemented joint" and counts as both basic and reinforced isolation if the thickness of the prepreg works out.

author: Wilksey
author_rank: Super Contributor
timestamp: October 06, 2021, 08:03:40 pm
content: I'll see how many are VIAbleonce i've put the component footprint down onto the big copper slab.Not much other that the FET, a Zener, tvs, fuse and a connector to go on the board anyway so plenty of room for stitching.

author: Wolfram
author_rank: Frequent Contributor
timestamp: October 07, 2021, 09:20:33 am
content: Quote from: uer166 on October 06, 2021, 07:50:50 pmThis is very interesting, do you have any more info or links to references? I have been looking for information on this without too much success.

author: uer166
author_rank: Super Contributor
timestamp: October 07, 2021, 06:01:46 pm
content: Quote from: Wolfram on October 07, 2021, 09:20:33 amYou're going to have to buy some standards, I can't tell which one(s) specifically but IEC 60950-1, IEC 62368-1, IEC 60664 and some UL standard I'm forgetting probably have the info. I recommend getting official paper copies fromhttps://www.evs.eefor maybe 5% of the normal cost. Sorry for hijacking the thread..

author: uer166
author_rank: Super Contributor
timestamp: October 07, 2021, 06:07:20 pm
content: Here's a good UL presentation on the cemented joint topic.