First PCB board, 4 layers - Page 1
Forum section: electronics / beginners

author: MichaelW
author_rank: Contributor
timestamp: January 15, 2015, 05:28:59 pm
content: I'm a EE student and I'm working on an independent study project for a professor designing a board using Eagle. It's not a terribly complex board, it's a microcontroller (PIC18LF14k50) controlled power controller board. The switching is done by 3 high-side load switches with are designed to handle up to 10 amps. We are going to be using Seeedstudio to produce the prototype boards. I have downloaded their DRU file and loaded that so I can do the DRC check. We will be using 2oz copper, which from their fusion pcb specs indicate are only for the top and bottom layer, the inner layers will be 0.017mm (.5oz). So, given this, we decided on a VCC top layer, GND bottom layer, and signals in the two middle layers. I saw a post from Dave indicating the opposite, signals on the top and bottom, etc, but because we need really beefy 10A traces, we need it to be on the 2oz copper (still, it needs to be 3.6mm wide).Given all of that, in the DRC layer setup, I'm trying to set up the vias and it's quite confusing. I'm probably very wrong here, but I think I need blind via's from both top and bottom layers to both signal layers, and a through via from top to bottom. I also need a buried via between the middle two layers. I'll have some through hole components as well as a bunch of SMD parts (like the micro, for instance).Attached is a screenshot of my layer set up currently, but I can't figure out how to structure the setup so that I can get the connections I think I need. Any advice or corrections will be gratefully accepted! :-)

author: gxti
author_rank: Frequent Contributor
timestamp: January 15, 2015, 05:55:48 pm
content: Blind and buried vias are very expensive to get manufactured, and you don't need them unless you have a high-density design with BGAs. Which you don't.Normal vias that go all the way through the board work just fine -- your PCB software will only electrically connect them to layers they should connect to, even though the hole and plating goes from top to bottom.It is true that 4 layer PCBs typically put power and ground on the inside and signals on the outside, but mainly because it is easier to route. Signals can stay on the top without going through vias. But if you only have a few signals and need the thick copper for power, that's fine too. It's likely the case that you could do as well with a 2 layer board, but 4 layers is not too expensive these days so do whatever gets you to the finish line quicker.

author: Jeroen3
author_rank: Super Contributor
timestamp: January 15, 2015, 05:58:41 pm
content: Keeping the power planes inside and the signals outside makes reworking with wiresa loteasier.

author: tggzzz
author_rank: Super Contributor
timestamp: January 15, 2015, 06:01:39 pm
content: Quote from: gxti on January 15, 2015, 05:55:48 pmI don't see why it would be easier to route. Easier to debug/modify, but that's a different topic.Another reason for having the power planes on the outside and signals in the middle is to reduce EMI and improve EMC.

author: langwadt
author_rank: Super Contributor
timestamp: January 15, 2015, 06:09:29 pm
content: Quote from: tggzzz on January 15, 2015, 06:01:39 pm

author: rx8pilot
author_rank: Super Contributor
timestamp: January 15, 2015, 06:47:05 pm
content: I do 10A with 1oz copper all the time. Just keep the traces very short. Think of the various SMD FETs out there that can do huge amperage with only 3 tiny connections on the source. Keep the layout tight in terms of power devices and you will be rewarded with a much easier to manufacture PCB. Using a mixed 2oz/1oz with blind/buried vias in a first PCB is a lot to take on for the first time.In the real world of EE, you will almost always be rewarded for taking the simplest path possible to solve your problem. I keep a list of "Special" features during a design and force myself to justify their existence. After some critical thought, almost all the specials get replaced with a more typical and easier to implement solution.As a side note: One of my EE friends always secretly poked fun at people that say "PCB Board" = "Printed Circuit Board Board"

author: max_torque
author_rank: Super Contributor
timestamp: January 15, 2015, 09:40:41 pm
content: If the layout isn't very dense, and you are ending up with your high current traces connecting to through hole connectors (which, generally you are if you want high current interconnects) then simply copy/double the high current traces onto an 2nd layer in parallel. Use a multiple "via field" near the output pin on the power switch to connect that second trace (it gets connected "automatically" by the through hole pin at the output end. This way you can easily lower your trace resistance etc

author: MichaelW
author_rank: Contributor
timestamp: January 15, 2015, 10:04:32 pm
content: Quote from: rx8pilot on January 15, 2015, 06:47:05 pmLol, yea normally I am more careful than that. I was dashing that question off before I ran to class and wasn't paying as much attention to that as I would normally. I only committed that crime in the title though! :-)Thanks for all the suggestions guys, I'll try some of it tomorrow when I work on it some more. I have exceeded my time quota on it today. I have a microelectronics quiz tomorrow that I desperately need to prepare for a little. haha

author: mazurov
author_rank: Frequent Contributor
timestamp: January 15, 2015, 10:06:11 pm
content: Quote from: tggzzz on January 15, 2015, 06:01:39 pmIt would be easier to route because as a general rule components are mounted on outer layers. Consequently, a trace on outer layer doesn't need a via to connect to a component pin.

author: rx8pilot
author_rank: Super Contributor
timestamp: January 15, 2015, 11:32:24 pm
content: Quote from: MichaelW on January 15, 2015, 10:04:32 pmI now assign you this homework - due first thing in the AM.http://youtu.be/8Gv0H-vPoDc

author: rx8pilot
author_rank: Super Contributor
timestamp: January 15, 2015, 11:57:45 pm
content: Quote from: Jeroen3 on January 15, 2015, 05:58:41 pm+1Quote from: tggzzz on January 15, 2015, 06:01:39 pm

author: jahonen
author_rank: Super Contributor
timestamp: January 16, 2015, 07:38:37 am
content: Quote from: tggzzz on January 15, 2015, 06:01:39 pmTheoretically yes but in practice the situation is that the cables are usually the greatest EMC offender in form of common mode radiation, not the PCB itself. In almost every case, the PCB itself passes the radiated emission test if there are no cables connected. Common mode radiation is dictated by how stiff the reference plane is electrically compared to the other reference points. One can think that the reference plane is flexible and all the active components cause it to wiggle around. Stiffer the ground/reference plane, less movement of the attached cable and less radiation from them.Placing all the signal traces inside would require extensive number of vias which themselves are a discontinuity on the PCB in addition that they make holes to the planes and disrupt the return current paths, so definitely would prefer a top/bottom trace without any vias if at all possible. And for RF, any vias are usually too much of a disruption.Regards,Janne

author: tggzzz
author_rank: Super Contributor
timestamp: January 16, 2015, 09:11:14 am
content: Jahonen notes that cables are much more of an EMI/EMC problem than on-board tracks. I completely agree.Nonetheless, once everything else has been dealt with, high speed clocks can emit significantly at single frequencies (plus harmonics). One mitigation is to have a "spread spectrum" clock, another is to bury the clocks.

author: Scrts
author_rank: Frequent Contributor
timestamp: January 16, 2015, 09:15:15 am
content: On 4 layers, if the clock paths are really long, you can route clock signals in GND polygon. This will for polygon cut-out, but it should still be fine. It must be stitched to top and bottom GND polygons when the PCB is routed.

author: coppice
author_rank: Super Contributor
timestamp: January 16, 2015, 09:22:07 am
content: Buried signal, surface power layouts made quite a lot of sense for screening the traces in the good old days, when everything was through hole. These days you just end up with a mass of vias trying to bring all the signals to the surface to connect to the components. The mess that creates tends to defeat the objective.