Pulse height measurement - Page 1
Forum section: electronics / projects

author: Resurge
author_rank: Newbie
timestamp: April 17, 2018, 03:21:53 am
content: I am starting a pulse amplitude measurement design. Square Pulses, 30nS wide, arrive at 60Hz. Their amplitude can vary from 50mV to 2.5V. I have to measure the amplitude. I am thinking along the lines of a peak hold circuit - which can hold the amplitude value for about 1 mS, so that a very busy A/D converter following this stage can measure the held value. After that I can either let the hold capacitor decay or reset it using an analog switch. I have enough digital bandwidth available to activate a switch post the A/D conversion.I am looking for the experience in this community to guide me to right approach on designing the above measurement circuit.If there are better or entirely different ideas/approaches to this problem - Please advise.Thanks in advance to all.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 17, 2018, 09:20:32 am
content: (FYI, "ns" = nanoseconds, "nS" = nanosiemens.)Without any other background, constraints or specs, I would guess a moderately fast, voltage type (conventional) op-amp, over 100MHz GBW, in a peak-detect circuit, would do fine. Use an analog switch to reset the hold capacitor between pulses (you have pleeeeeeeenty of time to do that).The op-amp will never track the input perfectly, it will always be a little behind the real value. The overall gain will be slightly less than 1, and/or there will be an offset. Do a 2-point (or more) calibration to account for response time.Possible gotchas include: unspecified input bandwidth, noise level; available supply voltages, and their noise/ripple level; source impedance; consistency of peak duration and shape; min and max time between pulses, and between pulse and sampling; etc.Tim

author: Resurge
author_rank: Newbie
timestamp: April 17, 2018, 02:00:40 pm
content: Thanks Tim,To answer some of the points you have raised. The Design is still on paper, so there is flexibility. I have a low noise, low ripple +/- 5V available, but can generate others if necessary. The signal is the output of a low noise amplifier, so low impedance - the signal is specified having a noise floor of 20mV . The pulses arrive at a fixed 60Hz and the pulse width is also fixed at 30ns.like your suggestion, I am considering using a fast op-amp, the LTC6268 is my choice. for the peak detection circuit I am considering a BAT68 diode. Alternatively, a fast transistor, like the 2N2369 to add some charging current to charge the hold capacitor, followed by a voltage follower. I am still not sure whether to provide Feedback to the op-amp from the final output or add another diode/transistor as a feedback element to compensate for the drop in the p-n junction.Are there any fast dual npn transistors available, that will work for this application? what are your thoughts on using the BAT68 and the LTC6268? any experience using these? any pitfalls to be careful of ?Your time to reply is really appreciated - thanks for the pointing out the ns typo.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 17, 2018, 02:05:15 pm
content: So, timing-wise, the pulses are guaranteed to always be 30 ns wide, one every 1/60 s?Do you have to be able to detect the absence of pulses?

author: Resurge
author_rank: Newbie
timestamp: April 17, 2018, 04:36:21 pm
content: @SiliconWizard : No - I dont have to detect the absence of pulses.

author: iMo
author_rank: Super Contributor
timestamp: April 17, 2018, 05:52:55 pm
content: QuoteSchottky has got a higher reverse leakage current than a planar epi one (ie 1n4148). Thus it may discharge the hold cap faster.

author: Resurge
author_rank: Newbie
timestamp: April 17, 2018, 06:18:43 pm
content: Thanks @imo - That is a good input. Can you recommend some alternatives to 1N4148, perhaps faster or lower capacitance or even lower reverse leakage.

author: iMo
author_rank: Super Contributor
timestamp: April 17, 2018, 06:23:44 pm
content: Do not underestimate the 1n4148 - it is fast enough for your application..PS: I messed in past with a similar peak detector - first_opamp with the diode, the hold capacitor, reset switch, second_opamp-buffer, a slow 16bit adc. The hold cap was rather small value (around an nF, a foil one) and output was quite noisy - you may consider a "guard ring" around the point where diode_cathode-capacitor-resetswitch-second_opmap_input are connected together.

author: SiliconWizard
author_rank: Super Contributor
timestamp: April 17, 2018, 06:50:07 pm
content: You could take a look at this:https://patents.google.com/patent/US20070030033(Ok it's patented but it's nothing that fancy.)Achieving good precision with 30 ns pulses will probably be challenging.Of course, the peak detection approach will just track the maximum of the signal until the next detector reset, so you'll have to be very confident about what gets out of your LNA to be certain it's actually the last pulse's amplitude.

author: iMo
author_rank: Super Contributor
timestamp: April 17, 2018, 07:38:42 pm
content: QuoteThe above opamp can source 135mA (max value). Consider the diode's dynamic resistance ~few ohms, you may calculate the hold capacitor's value when to be charged say in 20ns to 2.5V..

author: Resurge
author_rank: Newbie
timestamp: April 17, 2018, 08:52:03 pm
content: @imo - thanks for your suggestion about the guard ring. I will implement that.Indeed a 1N4148 is a good part, a colleague suggested 1SS427 diode, I am looking into its specs as well.

author: Resurge
author_rank: Newbie
timestamp: April 17, 2018, 08:55:59 pm
content: @SiliconWizard - Thanks for pointing out to the Patent, it has useful information. However, I am using a single supply op-amp, so I am not sure if the feedback diode described in the patent will help me.Regarding the LNA, since pulses are not random and can only arrive at 60Hz, i have plenty of time to implement a detector reset.

author: Resurge
author_rank: Newbie
timestamp: April 17, 2018, 09:03:56 pm
content: "The above opamp can source 135mA (max value). Consider the diode's dynamic resistance ~few ohms, you may calculate the hold capacitor's value when to be charged say in 20ns to 2.5V.."@imo - A 1000pF capacitor will charge to 2.5V in 25ns at 100mA. I am planning to use this value as an initial value and go from there.

author: Marco
author_rank: Super Contributor
timestamp: April 17, 2018, 09:45:17 pm
content: While your 1nf capacitor is short circuiting the opamp output, the input stage will be driven into saturation ... hard to predict what will happen at that point. If you include resistance to limit the current enough so the opamp doesn't saturate you'll need about 33 Ohm, which would limit your sampling capacitor to around 330 pf (to allow for 3 time constants to charge the capacitor).But then leakage currents really start kicking your ass. I wonder, would a series combination of a Schottky and a 1n4148 get you fast recovery and low leakage?PS.the open loop opamp based peak detectorseems more appropriate at these speeds.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: April 17, 2018, 10:37:59 pm
content: There are lower leakage diodes, like BAS70, and RF types. There may be faster switching diodes too (although, good luck finding any forward recovery specs -- 1N4148s vary between manufacturers).If leakage is a serious limitation, you might put a second peak detector, or S&H, after the first. This can be made with slower time constants and much longer retention time, until your ADC can get around to it.Or you can just get a better ADC. Anything sampling in the ms sounds really awful to me. Is it 24+ bits or something? How much accuracy are you actually expecting here? 10 to 16 bit converters are cheap and readily available in the low MSps, even integrated in MCUs and such. Maybe you should consider adding a peripheral, or using a new platform?Even sampling the pulse directly is feasible, though probably not with an integrated MCU -- you might need a faster MCU or FPGA to handle the raw data rate, and a ~100 MSps ADC to get a good reading on the pulse. This is under $100 parts cost, which may easily be outweighed by the cost in development time (assuming a commercial development environment).Or, again, if the pulse width and shape is consistent -- just filter it down to a lower bandwidth, so that the peak becomes a hump of lesser amplitude, and sample that with a slower ADC.Or, if the pulse timing is consistent (actually truly 60.000000pps, or even better, if a pretrigger is possible), a fast (high analog bandwidth) ADC and MCU could do the job quite cheaply.Or if you don't need to measure every pulse exactly, but can use their statistics over a longer period of time, an equivalent-time sampling method could be used, even if no pretrigger is available and the timing isn't coherent (i.e., a period of 16.6ms +/- much more than 30ns).These options are getting down in the noise floor of possible methods, but without any tolerances on the parameters given -- who knows?Tim

author: Resurge
author_rank: Newbie
timestamp: April 18, 2018, 02:50:55 am
content: Quote from: T3sl4co1l on April 17, 2018, 10:37:59 pmThanks much Tim,Statistics over a long period will not work for me. I need amplitude in real time.Pulse timing is consistent but I cannot get a pre-trigger clock. I will have to generate one myself, maybe using an ultra fast comparator. That will further shorten my sampling window.Filtering it down to lower bandwidth has been considered but with the lower measurement limit of 50mV with a noise floor at 20mV, that idea was abandoned.I am looking at 16 bit accuracy. But I was trying to save an ADC by using an existing channel in an A/D converter so that is why i am trying to hold the value for 1 ms.I like your idea of a dedicated A/D and maybe direct conversion without the peak hold. Can you suggest a part or a platform that will be suitable for my project. I can look further into it then.