Extra pins? Why isn't my design fitting? - Page 1
Forum section: electronics / general

author: gregallenwarner
author_rank: Regular Contributor
timestamp: April 09, 2015, 06:08:35 pm
content: I'm writing some VHDL for an Altera EPM3064ATC44-10 (MAX3000A CPLD) using Quartus II 13.0. It's basically a shift register, with both parallel in/parallel out, serial in/serial out. I'm going to use it to interface a small microcontroller to a parallel SRAM chip via the uC's SPI bus.The chip I'm using has 34 IO pins. By my count, I have 32 pins declared in the VHDL entity. However, when I try and compile the design, Quartus II fails, reporting 36 pins used out of an available 34. Where are these extra four pins coming from? I don't know the Quartus software well enough to know where to go to have it generate a report of all the pins it's trying to assign.All I've done so far for manual fitting is placed my two clock signals and the OE (output enable) signal on the chip's global clock and OE pins. I've left everything else unassigned for the fitter to automatically place.Here is my code:Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity shift_bus isport (addr: outstd_logic_vector(17 downto 0);data: inoutstd_logic_vector(7 downto 0);ser_in: instd_logic;ser_out: outstd_logic;oe: instd_logic;sh_clk: instd_logic;st_clk: instd_logic;load: instd_logic);end shift_bus;architecture arch_shift_bus of shift_bus issignal addr_reg: std_logic_vector(17 downto 0);signal data_out_reg: std_logic_vector(7 downto 0);signal data_in_reg: std_logic_vector(7 downto 0);signal set_signals: std_logic_vector(7 downto 0);signal clr_signals: std_logic_vector(7 downto 0);begin-- Data lines output enable processprocess (oe, data_in_reg)beginif (oe = '0') thendata <= data_in_reg;elsedata <= "ZZZZZZZZ";end if;end process;-- Serial in shift processprocess (sh_clk, ser_in)beginif (rising_edge(sh_clk)) thenaddr_reg(17 downto 1) <= addr_reg(16 downto 0);addr_reg(0) <= data_in_reg(7);data_in_reg(7 downto 1) <= data_in_reg(6 downto 0);data_in_reg(0) <= ser_in;end if;end process;-- Address lines latch processprocess (st_clk, addr_reg, data_in_reg)beginif (rising_edge(st_clk)) thenaddr <= addr_reg;end if;end process;-- Asynchronous parallel data load process (Generate SET signals)process (load, data)beginfor i in 0 to 7 loopset_signals(i) <= data(i) and not load;end loop;end process;-- Asynchronous parallel data load (Generate RESET signals)process(load, set_signals)beginfor i in 0 to 7 loopclr_signals(i) <= not set_signals(i) and not load;end loop;end process;-- Serial shift out process (and SET/RESET for asynchronous load)process (sh_clk, set_signals, clr_signals)beginfor i in 0 to 7 loopif (set_signals(i) = '1') thendata_out_reg(i) <= '1';elsif (clr_signals(i) = '1') thendata_out_reg(i) <= '0';elseif (rising_edge(sh_clk)) thenif (i /= 0) thendata_out_reg(i) <= data_out_reg(i-1);elsedata_out_reg(i) <= '0';end if;end if;end if;end loop;end process;ser_out <= data_out_reg(7);end arch_shift_bus;EDIT: Nevermind, I see. I have to repurpose the JTAG pins if I want to fit this design to this chip. There are only 30 non-JTAG pins available. My bad.