How exactly does an 8 bit CPU pull a 16 bit opcode from 8 bit RAM in 1 cycle - Page 1
Forum section: electronics / projects

author: MatCat
author_rank: Frequent Contributor
timestamp: December 14, 2014, 09:19:51 am
content: Ok, I have been working on a personal project to build a fully functional 8 bit computer from scratch in Minecraft, which I will when done port to an FPGA for further experimenting, now one of the kickers on this is that I am doing it from scratch and not looking up hardly ANY existing design concepts, and something has been bugging me extremely as I consider my control unit and opcode design, how the heck does something like an AVR with 8 bit CPU, 8 bit data bus, pull a 16 bit opcode from RAM every cycle? I have googled for 2 weeks and cannot find bupkiss on this subject.

author: SeanB
author_rank: Super Contributor
timestamp: December 14, 2014, 09:27:56 am
content: They normally use a clock that is faster than the CPU clock, so that typically the CPU clock is 4 times the main clock. That way you can do the required 2 opcode fetches required and the data fetch in the 4 clock cycles of the CPU cycle, then it can be executed in the next CPU cycle.Another method is to have a 16 bit internal data bus and then simply pull from it. 8 bit external data will be done with either 2 bus cycles with the CPU in a halt state during the second one, or by a fetch when the bus inot bust during internal decoding.the method varies from CPU to CPU.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: December 14, 2014, 09:29:40 am
content: 2 seconds:https://en.wikipedia.org/wiki/Atmel_AVRmodified Harvard architecturehttps://en.wikipedia.org/wiki/Modified_Harvard_architecture" entirely separate memory systems to store instructions and data."

author: MatCat
author_rank: Frequent Contributor
timestamp: December 14, 2014, 09:31:51 am
content: Quote from: SeanB on December 14, 2014, 09:27:56 amLooking over the block diagrams in the datasheets of 8 bit AVRs it seems they do the latter, stating an internal data bus for fetching from RAM to the instruction register, so my guess is that it's internal bus is indeed probably 16 bits then, thanks for the quick response.

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: December 14, 2014, 09:32:35 am
content: I guess another way would be to have the instruction fetch on the same clock as the main CPU, but on both rising and falling edge? That way you don't need extra clock hardware to implement it.

author: MatCat
author_rank: Frequent Contributor
timestamp: December 14, 2014, 09:32:48 am
content: Quote from: Alex Eisenhut on December 14, 2014, 09:29:40 am2 seconds of googling, but the key is WHAT did you google to come to the information?

author: DJohn
author_rank: Regular Contributor
timestamp: December 14, 2014, 09:33:07 am
content: The words you're looking for are "Harvard architecture". The short answer is that it doesn't. That 8 bit data bus that you're seeing is just for data access. There'll be another bus just for fetching instructions, and that's likely to be the width of the instructions.This way, it can fetch an instruction on every cycle, and also do a data access in parallel. The trade-off is that program and data memories will be separate (unless the two busses go to two different caches, which are being fed from one common memory, but that's unlikely in a small microcontroller). That's why the AVR has special instructions for fetching data from program memory: it isn't accessed in the same way as data memory, because it's attached to a different bus.

author: Retep
author_rank: Regular Contributor
timestamp: December 14, 2014, 09:34:53 am
content: The 8-bit AVR is a Harvard architecture processor; it has separate memories for instructions (16-bit) and data (8-bit) on separate busses allowing both instructions and data to be fetched at the same time. Also the AVR is pipelined; when executing an instruction (which may involve a read or write of data memory) it fetches the next instruction.

author: Howardlong
author_rank: Super Contributor
timestamp: December 14, 2014, 09:37:42 am
content: In addition, with von Neumann architecture you could do it using double data rate.So, assuming for the moment for the sake of simplicity, that the 16 bit instruction is aligned on an even address boundary, you can simply use the clock for the LSB of the address, using an 8 bit edge triggered latch to save the first byte while the second is fetched.Cheers, Howard.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: December 14, 2014, 09:38:48 am
content: Quote from: MatCat on December 14, 2014, 09:32:48 amLook up the AVR article on wiki and read it?I mean where else to start than at the beginning?

author: MatCat
author_rank: Frequent Contributor
timestamp: December 14, 2014, 09:43:44 am
content: Quote from: Alex Eisenhut on December 14, 2014, 09:38:48 amYeah, I hadn't actually used AVR as a search term, I only really thought of it when I posted here as an example... most of my searches where consisting of things like "how does 8 bit processor read 16 bit opcode in 1 cycle" and various renditions of similarity, so yeah I wasn't getting much back helpful to what I was actually looking for.