newbie question about library management - Page 1
Forum section: electronics / general

author: PythonGuython
author_rank: Contributor
timestamp: May 08, 2024, 01:45:26 pm
content: I am using altium DBlibs and for each part I add to my design, I typically create a new footprint or symbol. I am reluctant to reuse footprints even for common packages (say tssop or QFN) because different manufacturers specify slightly different pad layouts. Library management ends up taking a long time as a result of this. If I start reusing footprints for common packages, do you think I will run into assembly issues?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: May 08, 2024, 05:45:03 pm
content: Some packages are problematic. They can have a pitch of for example either 0.6mm, 0.65mm, or maybe even 0.635mm (referenced to some banana unit). Such differences are too small to see, but when you have a 16 pin IC package, the difference is just big enough to cause a problem.Similar with the Green / industrial terminal blocks. They are sold both in 5mm pitch and in 5.08mm pitch. For two or 3 pole blocks they are exchangeable, but for a 16 pole connector, the differences accumulate and it won't fit anymore.But when the package pitch is the same. It really does not matter much. An old (Dos age) program I had long ago had different libraries for "technology class". Some libraries had big pads and are easy to solder. Other library sets had smaller pads for the same IC's. Those need more accurate SMT placement, but the PCB can be made denser.When Solder melts, it flows around any area it can wet, and it will it's shape according to surface tension, so a lot of variability can be tolerated. But there are a bunch of factors that are critical to keep within range. For example either too much or too little solder paste will result in unreliable PCB's. And guess what. Some PCB / Stencil manufacturers make the stencil apertures as you created them, other stencil manufacturers shrink all apertures by some (arbitrary?) amount. This inserts a lot of uncertainty in what should be simple. Solder stencils also come in different thicknesses, and this also changes the amount of paste for each pad.So as long as the pitch is right, and pad size and location sort of looks OK, it is very likely good enough, but there are more factors that can dominate.

author: PythonGuython
author_rank: Contributor
timestamp: May 08, 2024, 08:56:33 pm
content: I found two 8-SOIC parts as a random example. They have the same pitch, but one manufacturer recommends pad lengths of 1.55mm, the other 1.3mm. Would you reuse the same footprint in this case?https://www.digikey.com/en/products/detail/microchip-technology/MCP6002-I-SN/500876https://www.digikey.com/en/products/detail/littelfuse-inc/SRDA3-3-4BTG/4490758

author: Doctorandus_P
author_rank: Super Contributor
timestamp: May 09, 2024, 12:18:37 am
content: That microchip datasheet has 23 pages with mechanical drawings.I wanted to compare the width of the actual IC instead of the footprint recommendations (I guess they are the same), but I got lost in all those pages.I work on a hobby level, but usually I print the PCB on paper, and use the physical parts to see if they fit nicely on the paper. A difference of 0.25mm is not going to be noticeable. The check on paper is mostly to verify pin pitch and total width of the IC, or even a mistake in a completely wrong footprint assignment.I consider my check on paper more valuable then some random recommendation from a manufacturer (They often do not put much thought in such recommendations, and often just copy those pages from some other datasheet). And because I don't trust such recommendations much, I hardly even look at them in the first place.But also, do not take it too lightly. Some kind of verification is important. There are too many silly mistakes that can be made, and if the IC does not fit on the footprint, then you may have to re design the PCB, order new ones, and wait for them to arrive. So it both costs money and time.

author: PythonGuython
author_rank: Contributor
timestamp: May 09, 2024, 02:58:43 am
content: I used ctrl+f and "soic" to find the layout, but I'm not paying you by the hour, so I won't ask you to dig further. Thanks for your thoughts

author: thm_w
author_rank: Super Contributor
timestamp: May 09, 2024, 09:08:06 pm
content: Quote from: PythonGuython on May 08, 2024, 01:45:26 pmFor common packages, no I don't think so.The microchip ones list the dimension as "max" so seem to be what you'd use for "low density" type design, eg the most forgiving. So if you have space might go with that.https://electronics.stackexchange.com/questions/216032/altium-database-and-footprint-density

author: murisio
author_rank: Newbie
timestamp: May 12, 2024, 12:18:18 pm
content: What i did for my workplace's repository is to use generics for passive components and then for SOT-25 i've seen that they all use the same footprints or that's what the EuroCircuits' assembly check tells me. The only ones that I would definitely don't trust are Infineon and some Linear Technology packages, picrel.TLDR: use generics for passive components and for ICs break your back a little bitEdit: if you want i can forward you some sections of the repository with scripts already implemented and all that