Programming Flash on Spartan 3E Starter Kit - Page 1
Forum section: electronics / general

author: TeddyPython
author_rank: Contributor
timestamp: October 14, 2020, 12:59:58 pm
content: I'm trying to do some experiments with Xilinx FPGAs, after getting some limited experience with Altera. I've managed to write .bit files to the FPGA successfully, but am stuck when it comes to writing to the xcf04s flash memory onboard so I can cycle power. I am using a different version of impact and the ISE project navigator (P.68d) to what all the instruction manuals online have, which makes things a little more tricky but it is not too difficult to follow along.Indeed, I am able to get a "Program Succeeded" message when I try to write my .mcs file to the flash memory, but nothing happens. I cycle the power, and the starter kit's demo file still plays. I can get a device ID, etc for the flash so I think I can connect fine to it, but maybe I am missing something else.I am trying to use the USB cable to program, and have tried a variety of combinations of the programming headers (currently on SPI mode), but to no avail.I've tried using the following resources, but they only help so far.https://www.xilinx.com/support/documentation/user_guides/ug332.pdf(page 126 onwards)https://my.eng.utah.edu/~cs3710/xilinx-docs/examples/s3esk_picoblaze_nor_flash_programmer.pdfAny ideas as to what I am doing wrong?

author: 0db
author_rank: Frequent Contributor
timestamp: October 14, 2020, 03:00:08 pm
content: Um, it smells the FPGA is not configured to bootstrap from the FLASH.Probably some jumper needs to be checked and changed.

author: asmi
author_rank: Super Contributor
timestamp: October 14, 2020, 03:07:56 pm
content: Quote from: 0db on October 14, 2020, 03:00:08 pmBut where would the demo bitstream come from in this case?I bet on flashing part being broken for some reason. I know in Vivado you can do "write & verify" to ensure that programming was actually successful, do you have the same function in ISE (or whatever the programming SW is called in that package)?

author: TeddyPython
author_rank: Contributor
timestamp: October 14, 2020, 03:20:49 pm
content: Thanks asmi and 0db,I couldn't find write and verify, but verify comes back as in the attached picture.

author: 0db
author_rank: Frequent Contributor
timestamp: October 14, 2020, 03:22:26 pm
content: Quote from: asmi on October 14, 2020, 03:07:56 pmGood question. I had a board with multiple choices for the bootstapping chip, and I finally found that I was programming the wrong one with the result that the bitstream was actually correctly written on a chip, but not to the one selected for the boostrapping. I spent two days thinking the chip was not properly programmed.

author: TeddyPython
author_rank: Contributor
timestamp: October 14, 2020, 03:35:14 pm
content: Quote from: 0db on October 14, 2020, 03:22:26 pmThis is what I suspect I am doing, but I can't identify how I'm doing it. Attached is a photo of all the jumpers I think are related to programming - anything jump out?

author: vstrakh
author_rank: Contributor
timestamp: October 14, 2020, 04:11:34 pm
content: It looks like the configuration mode is not Master Serial, so FPGA will boot not from the xcf04s platform flash, but from M25P16 flash chip.Table 4-1 in the user guide explains it.

author: TeddyPython
author_rank: Contributor
timestamp: October 14, 2020, 04:46:20 pm
content: Thanks vstrakh, unfortunately that hasn't fixed the problem. I switched all jumpers to connect all pins for MS. I then went through the following steps:Choosing memory device:Having chosen my .bit file it says it generates the mcs file ok.I then setup the devices as shown:And program the flash:Alas, the XC-DONE LED doesn't light, even when I press the PROG button. Cycling the power doesn't help either.

author: TeddyPython
author_rank: Contributor
timestamp: October 15, 2020, 01:39:45 pm
content: I've made some progress, sifting through old forum posts and broken links.The flash memory (IC 11) has its enable pin controlled by a CPLD (IC 16), which I've read has sometimes needed a reprogram with the s3esk_cpld_design.zip - originally from Xilinx. However, this is no longer available on Xilinx's website - though through the magic of the WayBackMachine, I've managed to download this zip (and others) for safekeeping. I will try to upload the cpld example and report back with my results.If it is ok, I have attached the zip here as it should be better indexed for future users to find, rather than on wayback machine. If this is not allowed let me know and I will remove it.EDIT: Yes - it works! I used impact to program the .jed file in that cpld example zip to the cpld (xc2c64a). Before I did this, I asked for checksum from the cpld and it came back different. After uploading the example the fpga works from the flash without problem.