How to determine if PLL 4046 is locked? - Page 1
Forum section: electronics / beginners

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 11, 2018, 12:47:29 pm
content: I am trying a Class E amplier with a PLL 4046. I see certain a half sine wave across the resonant capacitor, but I have no idea if the PLL is working as intended, bascally I plan to make a small dielectric heater, and I want to keep the gate pulses in phase with the sine wave output, that is always switch on the mosfet at zero voltage / zero current even if the load capacitor varies.I have attached my circuit and some oscilloscope waveforms.

author: Lee Leduc
author_rank: Regular Contributor
timestamp: August 11, 2018, 01:28:02 pm
content: Application note for 4046.http://www.ti.com/lit/an/scha003b/scha003b.pdf

author: iMo
author_rank: Super Contributor
timestamp: August 11, 2018, 01:35:30 pm
content: Pin 1 High when locked??

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 11, 2018, 01:39:07 pm
content: Quote from: Lee Leduc on August 11, 2018, 01:28:02 pmThanks for the reference, additionally whats bugging me is the feedack that I derive from the tank capacitor then give it via current limiting resistor to the diodes (1N4148). I was expecting a square wave here between 0 to 15V but I get quite low level over there.

author: Lee Leduc
author_rank: Regular Contributor
timestamp: August 11, 2018, 01:51:25 pm
content: Here's another TI appnote. See Figure 15.http://www.ti.com/lit/an/scha002a/scha002a.pdf

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 11, 2018, 02:04:17 pm
content: Quote from: imo on August 11, 2018, 01:35:30 pmI am using the HEF4046 and its Pin 1 is given as "Phase Pulses". I'm getting a square wave on that pin.

author: Benta
author_rank: Super Contributor
timestamp: August 11, 2018, 02:08:49 pm
content: You are using PFD I. This one locks at appr. 90 degrees offset between VCO and input.If you want 0 degrees lock, you need to use PFD II.CAUTION: the PFD II needs an active loop filter to lock, it will NOT lock with the simple RC filter (Even though data sheet and TI app notes suggest it).

author: iMo
author_rank: Super Contributor
timestamp: August 11, 2018, 03:39:24 pm
content: Quote from: ZeroResistance on August 11, 2018, 02:04:17 pmAccording to the HEF4046 datasheet the PIN1 (PCP_OUT) indicates "locked" with High when Phase comparator 2 is in use (High at PIN1 means the both high- and low-side charge pump transistors are OFF, and when the both are OFF it means no charge is needed to be pushed into the filter because there is zero phase difference = "locked").PS: With the XOR phase detector you have been using the "locked" state to indicate isn't easy. I do it in my GPSDO by measuring the voltage at the output of the XOR's low pass filter (opamp buffer and stm32's ADC). When the voltage is between, for example, 1.855-1.865V the PLL is considered "locked".

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 11, 2018, 05:37:40 pm
content: Quote from: Benta on August 11, 2018, 02:08:49 pmI am using a capacitor to couple the waveform to the input (Signal in), won't the capacitor introduce a phase shift of the said 90deg. Now I am thinking of using a optocoupler instead of the capacitor / diode circuit that was used? The opto might introduce is 180 deg out of phase.Also I don't understand the part why the Phase Comparator locks only at 90 degre offset between VCO and input. I didn't find any such info in the data sheet

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 11, 2018, 05:53:45 pm
content: Quote from: imo on August 11, 2018, 03:39:24 pmSorry My bad its actually an HCF4046 from ST, it does have a "Phase Pulses" at pin 1 though and the datasheet indicates that a locked condition exists when the level of this pin goes high. Although the waveforms for this pin are only shown for phase comparator 2.The real question I should be asking is based on the waveforms I have posted is the PLL in locked mode. And yes I checked the "Phase Pulses" pin and it shows a square wave and not a high signal which might indicate that it is not in lock right?Whats the reason for the "1.855-1.865V the PLL is considered "locked""? Do you use 15V supply voltage?

author: Benta
author_rank: Super Contributor
timestamp: August 11, 2018, 06:01:39 pm
content: It might be in lock. Reread my reply #6. The PFD I will only provide a frequency lock, not a phase lock. If the signal at pin 1 is a stable square wave, your loop is frequency locked as expected.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 11, 2018, 06:28:46 pm
content: Quote from: Benta on August 11, 2018, 06:01:39 pmIn the datasheet "Pin 1" is only referred to during Phase Comparator II operation, does it apply to Phase Comparator 1 also?

author: Benta
author_rank: Super Contributor
timestamp: August 11, 2018, 06:53:17 pm
content: Quote from: ZeroResistance on August 11, 2018, 06:28:46 pmYes, insofar as the two PFDs are in parallel, and PFD II is forced to run out of lock when using PFD I, the pin 1 output indirectly also applies to PFD I.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 11, 2018, 06:57:00 pm
content: Okay so I'm adding some more waveforms here.First waveform shows relation between VCO out and Signal In.Second waveform shows the original resonant capacitor waveform that i wan to lock onto and Signal In (Derived from the resonant capacitor)My question is Signal In required to be a square wave of CMOS levels. Or is the signal shown in the waveform a valid signal for the PLL to operate?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 11, 2018, 07:22:44 pm
content: You claimed "sine wave", but the output will never be a sine wave. What are you really trying to do here?If you have an output coupling network (seems likely, for dielectric heating?), put that in the loop!FYI, because this circuit is self driven, it's never "out of lock", though you might be unhappy with how it is locked (i.e., out of phase, or unstable control loop).It should be pretty easy to get it to behave. Mind that you will need the two phase signals of interest: presumably, output voltage and resonant current. You can't use the oscillator output directly due to phase shift through the driver and output chain.Mind also that the kind of 4046 matters. The original CD4046 is apparently the best, albeit probably too slow for this. The 74HC4046 was a chintzy hackjob of a clone, with deadband in its type II detector, and a much worse (nonlinear, drifty) oscillator. There are also "improved" versions (HC7046 and I think 9046?) that still aren't as good as the original (in all aspects but speed), and have another PFD type available. (Disclaimer: this is what I've heard; I have had few PLL applications myself, so this is not first hand experience, let alone with data to back it up.)You may well be better served with a semi-discrete solution: a VCO, driver, PFD and error amp, all separate components (probably still ICs, or gates or whatever, just not a single-chip solution). That's how I design induction heaters (same thing, inductive rather than capacitive load). Could also potentially use a frequency multiplier to get higher frequencies from a lower frequency osc/PLL, if that's a problem.Tim

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 11, 2018, 07:48:07 pm
content: Quote from: T3sl4co1l on August 11, 2018, 07:22:44 pmI do see a half rectified kind of sine wave across the resonant capacitor.Quotei don't have any coupling network yet, i was planning to connect 2 parallel plates across the resonant capacitor and then put some material between the parallel plates to be heated.QuoteI'm sorry I didn't get this. When I load the material into the output plates the resonant capacitor would change and so would the frequency. The would change the switching of the mosfets out of their zero voltage / zero voltage switching. I want to achieve zvs / zcs even though the capacitor and frequency changes.It should be pretty easy to get it to behave. Mind that you will need the two phase signals of interest: presumably, output voltage and resonant current. You can't use the oscillator output directly due to phase shift through the driver and output chain.QuoteI am currently using an HCF4046 from ST, altough it is not suitable for this application because I need a higher frequency preferably 3 to 5Mhz.QuoteGood Idea regarding the frequency multiplier..So If I still want to continue using this chip for say 5Mhz would I need both a multiplier (for feeding to the mosfet driver) and divider for feed back into the signal input?

author: iMo
author_rank: Super Contributor
timestamp: August 11, 2018, 07:48:57 pm
content: Quote from: Benta on August 11, 2018, 06:53:17 pmThe PIN1 "lock" indication will not work with PFD1 (the simple XOR). The XOR "continuosly wobbles" around the "lock" position, thus the PIN1 shows a square wave.The PFDII when "locked" stops pumping the current into/from the filter, thus you get PIN1 high when the phase is zero (plus minus dead time for some 4046 variants).QuoteIt was a "for example". The voltage at which the XOR PD is considered to be "locked" depends on many factors. It could be any voltage from almost 0V to almost 15V in your case.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 11, 2018, 08:03:04 pm
content: Quote from: ZeroResistance on August 11, 2018, 07:48:07 pmYeah, you might not like what lock condition it's in, but it's never not in a lock condition. In Diff Eq, this is a non-homogeneous system. When the system is linear (as an RLC network is), the steady-state solutions are always at the driven frequency (assuming the "driver" is a periodic signal, of course).In simpler terms: no matter what frequency you're driving at, the network is always doing whatever it's doing, at that same frequency. There is no locking to be done*, because it's always locked on frequency.*In the sense that the phase might go outside of (-pi, pi] (in terms of total phase, not modulo phase).This makes PLLing a resonant network much easier than the general case (typically, a PLL locking to a completely arbitrary and separate signal, like for radio). So that helps!PLLing a class E stage (with no output network) is even easier still, because it's not resonant at all, as such. It's quasi-resonant. There's a half-sine* hump, then the voltage goes back to its initial state, and current goes back to ramping up. The ramp duration is variable. To a certain extent, you can drive over a wide frequency range, and get output power proportional to frequency (though this is probably prohibitive because of peak current and voltage demands on the switch).*It's still not actually a sine part, but a segment of a decaying sinusoid. And if we include real components, not even that, because MOSFET Coss is nonlinear, so the zero crossings are rather slower (more Coss at lower Vds) than expected.Be very careful talking about precise things like waveforms! If you say "sine wave", I fully expect something very tightly defined in the frequency domain: one spectral line, no distortion, no sidebands (maybe a DC offset, but strictly speaking, no). As soon as you have "sine wave BUT", the spectrum goes out the window, and it simply doesn't have the properties of a sine wave, and should not be called that.Tim

author: iMo
author_rank: Super Contributor
timestamp: August 11, 2018, 08:16:27 pm
content: While trying to understand your schematics (I have to rotate my notebook upside down) - what the 10k pot-trimer actually does?I think it cannot be wired that way..Could you describe what the system shall actually do?

author: Benta
author_rank: Super Contributor
timestamp: August 11, 2018, 08:22:16 pm
content: Quote from: ZeroResistance on August 11, 2018, 06:57:00 pmYour first plot shows exactly what is to be expected from using PD I. A locked signal with appr. 90 degrees shift. The 4046 has an input amplifier, your input signal is perfectly OK. It works as it should.And No, the XOR does not "continually wobble", no idea where that came from.

author: iMo
author_rank: Super Contributor
timestamp: August 11, 2018, 08:40:49 pm
content: Quote from: Benta on August 11, 2018, 08:22:16 pm

author: Benta
author_rank: Super Contributor
timestamp: August 11, 2018, 08:53:10 pm
content: Quote from: imo on August 11, 2018, 08:40:49 pmYour picture does not represent "wobble" in any way, the triangular waveform is synchronous to the PD and VCO and will not result in frequency or phase "wobble".That aside, the scha002 and scha003 are the dodgiest application notes from TI ever, and were probably written by an intern during the summer vacation. I've ranted about those in other threads.

author: Zero999
author_rank: Super Contributor
timestamp: August 11, 2018, 09:47:43 pm
content: Here's a schematic of a tone decoder I found in a Forrest Mims book (I can't remember which one) I found awhile ago. It uses the '4001, D1, C4 and R5 as atone decoderlock detector.

author: Benta
author_rank: Super Contributor
timestamp: August 11, 2018, 10:33:15 pm
content: Quote from: Hero999 on August 11, 2018, 09:47:43 pm

author: Zero999
author_rank: Super Contributor
timestamp: August 11, 2018, 10:42:15 pm
content: Quote from: Benta on August 11, 2018, 10:33:15 pmYes, my fingers were faster than my brain. Fixed.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 12, 2018, 05:41:28 am
content: Quote from: Benta on August 11, 2018, 08:53:10 pmI was under the impression that when both VCO and Signal In are in phase the phase comparator should have output 0 volt's.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 12, 2018, 05:44:11 am
content: Quote from: imo on August 11, 2018, 08:16:27 pmI was followinghttp://uzzors2k.4hv.org/index.php?page=pllsstc1

author: iMo
author_rank: Super Contributor
timestamp: August 12, 2018, 06:30:53 am
content: Quote from: ZeroResistance on August 12, 2018, 05:44:11 amThen you miss the 120k resistor at the 10k pot's wiper (from the pot's wiper to the LP filter)..

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 12, 2018, 09:18:54 am
content: Quote from: imo on August 12, 2018, 06:30:53 amI have it soldered on my board, I missed it while drawing the schematic.

author: Benta
author_rank: Super Contributor
timestamp: August 12, 2018, 10:16:36 am
content: Quote from: ZeroResistance on August 12, 2018, 05:41:28 amNo. From your link:"The phase locking itself works by using an XOR gate to detect the phase angle between the two inputs, pin 3 and 14. The output from the XOR (pin 2) is a PWM signal, and the duty cycle will vary from 0 to 100% as the phase difference between two 50% duty square waves moves from 0 to 180 degrees."

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 12, 2018, 12:39:13 pm
content: Quote from: Benta on August 12, 2018, 10:16:36 amOK, so lets see if the VCO out is the same frequency as "Signal IN" but 180 deg out of phase, at this point PFD1 out will be high continuous right? and this will cause VCO frequency to increase this the Both VCO and Singal In are locked in phase but different frequencies right?So does this PLL have 2 modes of operation Locked Phase and Locked Frequency?

author: Benta
author_rank: Super Contributor
timestamp: August 12, 2018, 03:31:14 pm
content: Quote from: ZeroResistance on August 12, 2018, 12:39:13 pmNo, not quite. First, it does not make sense to analyze an out-of-lock situation, because that is chaotic.When in lock, input and VCO frequency are the same, and the phase difference between them is constant.The difference between PD I and PD II is, that for PD I, the phase difference is constant, but varies with frequency, as it needs to provide a PWM signal that can be filtered to a DC voltage for the VCO.For PD II, the phase difference is always zero, and the output is three-stated most of the time. This is also one of the reasons why you need an active loop filter.Please note, that for PD I to function correctly, the input must either be a sine wave or a 50% duty cycle square wave.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 14, 2018, 07:34:12 pm
content: So for a high frequency verson (5Mhz to 15Mhz) of the CD4046 what would be better?74HC404674HCT904674HC7046AD9901Or are there any other better alternatives? Even a purely digital version would do I can add it to the listEDIT: The AD9901 seems to be PFD and not a full fledged PLL

author: Kleinstein
author_rank: Super Contributor
timestamp: August 14, 2018, 08:05:49 pm
content: Speed wise there is not much difference between HC4046 / HC7046 und 74 HCT ...Choosing the manufacturer could have a larger effect.There are quite a few modern PLL Chips, many of them much faster, like in the GHz range. ADF4351 is one such example.PLLs are also integrated into quite a few µCs.

author: Benta
author_rank: Super Contributor
timestamp: August 14, 2018, 08:30:29 pm
content: Quote from: ZeroResistance on August 14, 2018, 07:34:12 pmNeither the CD4046 nor the 74HC types will work well at those frequencies. I think you need to take a step back and rethink this project.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 15, 2018, 06:08:04 am
content: Quote from: Benta on August 14, 2018, 08:30:29 pm74HC4046 datasheet says that VCO center frequency @ Vcc 6.0V is min 13Mhz typ 21Mhz ? Am I missing something here?

author: Benta
author_rank: Super Contributor
timestamp: August 15, 2018, 06:14:05 am
content: Didn't say it wouldn't work, just that it won't work well. At those frequencies, the VCO output will not look like a square wave. And the PD will have issues.

author: ZeroResistance
author_rank: Frequent Contributor
timestamp: August 15, 2018, 06:23:32 am
content: Quote from: Benta on August 15, 2018, 06:14:05 amOk, then what do you suggest, is there a chip that will work well at those frequencies?

author: iMo
author_rank: Super Contributor
timestamp: August 15, 2018, 06:58:18 am
content: The most recent variant is the 74HC9046 with improved params.The only way how to verify it works fine at 5-15MHz is to wire it and measure..

author: Zero999
author_rank: Super Contributor
timestamp: August 17, 2018, 01:47:23 pm
content: Quote from: ZeroResistance on August 15, 2018, 06:23:32 amAn LC oscillator with a varactor?

author: Benta
author_rank: Super Contributor
timestamp: August 17, 2018, 04:56:31 pm
content: This might seem like a total overkill, but there aren't that many PFDs and VCOs out there. These ON Semi parts will do the job:MCK12140MC100EL1648They're not cheap (appr. 5 € each). Upside is, they're relatively easy to design with, as ECL technology does not send major switching spikes onto the supply lines.Finding PLL/VCO parts in the 1<100 MHz range is hard. BTW, ON Semi specifies max. operating frequency as 1.9 MHz for 4046, 3 MHz for 74HC4046.

author: Zero999
author_rank: Super Contributor
timestamp: August 18, 2018, 12:31:06 pm
content: I was thinking of something like this. It may need buffering to give a nice square wave, which could be done with the spare gates in the quad NOR gate IC, used for the lock detector.https://www.electronics-notes.com/articles/radio/pll-phase-locked-loop/voltage-controlled-oscillator-vco-design-for-plls.php

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 18, 2018, 07:25:55 pm
content: Not really necessary to go to an LC oscillator. RC is perfectly reasonable at this range, you just need something that's not HC slow.Might look for V-to-F converters, or anything using a comparator for the same purpose. MCP6562 and the like should be fast enough, or there's always faster types out there. (Or LM319 if you're feeling... rustic?)Tim