Weird output stage in a function generator - Page 1
Forum section: electronics / testgear

author: reagle
author_rank: Unknown
timestamp: March 10, 2013, 08:02:38 pm
content: While working on repairing TTL/CMOS output on my signal gen, I've stumbled on something I hope the collective hive mind can help me with. I've already fixed the more obvious things like a dead logic power supply and shorted driver chips. (Sockets were added to ease the pain next time)See attached pictures for before/after and a schematic diagram.It appears the design takes the signal from the analog section and feeds it into U6 (dual 4 input NAND gate 74LS20N). Several inputs are either shorted together and left floating or are floating on their own. The board is essentially single sided with a few planes on top, so the pins are clearly not connected. The outputs are paralleled, despite not being open drain type. The output is then fed into an open collector HV gate to drive the higher voltage setting. I can get working output simply by bypassing U6 with a jumper (and probably loosing output buffering etc)So my question is- what are they doing with the two gates and their inputs? Is that something relying on internal properties of the LS series gates?

author: SeanB
author_rank: Super Contributor
timestamp: March 10, 2013, 08:25:44 pm
content: Genuine TTL logic has the property that a floating input is treated as a logic 1 inside the chip. Thus for standard 54/74xx, 74ls, 74ls, 74f and 74als if you leave a gate open it will be seen as high. It is better to pull up to a defined level noise wise, but it will work. This is because the inputs are the emitters of a multi emitter transistor, and the inputs that are pulled down are active in determining logic state.Parallel connection of the outputs of gates in the same package if they have the same inputs is doable, it just increases the current sink capacity and slightly increases source capacity, and makes the edges faster into high capacitance loads. Not a good design recommendation but it works.Replace the IC with a plain 74xx device, or a 74ls or 74s one. This is one of the edge cases where the cmos parts will not work at all. The dual gates in this case are to drive the long cabling of a test lead with fast edges. If you can put pull ups to all those unconnected pins, or tie them together to the input ( in this case it will not increase the fan in loading at all) to improve things. Then you can use the 74 HC or HCT parts as well.

author: reagle
author_rank: Unknown
timestamp: March 10, 2013, 08:34:57 pm
content: That's what I figured- looking at the output stage schematic for LS series, they have a series element , that will probably prevent magic smoke from escaping if one gate drives low and one decides to go high. What's the logic behind tying two unconnected inputs together but leaving the third one floating mewonders though

author: KJDS
author_rank: Super Contributor
timestamp: March 10, 2013, 09:02:37 pm
content: Quote from: reagle on March 10, 2013, 08:34:57 pmSometimes, designers make mistakes. I suspect that can fall into that category. It might just be possible that the board was laid out for another device and ended up using the quad input gates because they could be made to work.

author: SeanB
author_rank: Super Contributor
timestamp: March 11, 2013, 09:06:39 pm
content: I made a buffer using a 54S14 buffer driving the one gate and using it to drive the other 5, with all outputs connected together. Stacked a second one on top to double the power capacity and tacked a 10uF wet tantalum on top of the pile as well for decoupling. That could drive a 1R load without getting hot enough to unsolder the cerdip packages it was in, though it was hot enough doing that with 14MHz drive that it was not touchable. connect a long wire and it made a pretty good jammer for a short radius into the VHF radio range.