Anything wrong with this PMOS gate driver? - Page 1
Forum section: electronics / beginners

author: shapirus
author_rank: Super Contributor
timestamp: December 13, 2023, 11:15:35 pm
content: So I've been trying out some topologies to drive a PMOS with a signal that's not suitable for direct drive in kicad + ngspice.Application:- 0V / 5V controlling signal- PMOS is used as a power switch for a circuit powered by 12V- short (tens of microseconds) turn-on pulses with low frequency (tens of Hz max)- ...which means that the driver's power consumption in the "on" state isn't important, but in the "off" state it (more or less) is- let's say Cgs is around 3nF- turn-on time can be a few microseconds- turn-off time must be as short as possible, sub-100ns would be fineI came up with the following:D2 provides path for the gate discharge at turn-on.Q2 is to speed up the turn-off transition in comparison with a single pull-up resistor.D3 is also to speed up the turn-off transition in case R5 is non-zero. I am not sure if it actually has to be non-zero -- is it only necessary to suppress ringing on the gate?It simulates just fine:I haven't tried to build a real circuit yet.Is it bad? Can it be improved? One obvious downside is that it's not rail-to-rail, gate voltage will be one p-n junction away from either rail. I guess it's not a problem if the specific MOSFET used is fully on and fully off in those two states.What are other gate driver topologies to drive a PMOS gate that are fast and simple? I'd prefer to avoid using dedicated driver ICs unless their advantage becomes overwhelming. I know that they exist, and some suitable ones can be obtained here, but I just have more fun building things, as long as they don't get too complicated, with discrete parts.

author: Benta
author_rank: Super Contributor
timestamp: December 13, 2023, 11:18:27 pm
content: I think you need to edit your post. There's no schematic.

author: shapirus
author_rank: Super Contributor
timestamp: December 13, 2023, 11:26:37 pm
content: Quote from: Benta on December 13, 2023, 11:18:27 pmYou were apparently too quick to open it :).The attachments were messed up originally, so, as usual, I had to edit and re-edit the post to make them appear. Please try Ctrl-F5/Ctrl-R, does it work? It works for me, including in private mode.

author: Whales
author_rank: Super Contributor
timestamp: December 14, 2023, 01:05:44 am
content: Very notable delay for Vgate rise when simulated in QUCS, albeit I'm simulating the mosfet gate as a 3nF capacitor.The voltage at the collector of the first transistor follows the same shape, so presumably it's at fault. EDIT: Adding 50R emitter degeneration helps reduce the problem but then makes the Vgate fall very gradual.

author: shapirus
author_rank: Super Contributor
timestamp: December 14, 2023, 09:33:12 am
content: Quote from: Whales on December 14, 2023, 01:05:44 amSimilar thing in ngspice, however by the time it reaches the point where the delay is most significant, the mosfet must be either turned off already, or in the process of turning off. Which means a higher-Vth transistor is to be preferred here.Quote from: Whales on December 14, 2023, 01:05:44 amGood catch. While this won't be acceptable in the real circuit because of slowing down the turn-on time too much, it gave me an idea.I tried to add a resistor between the base of the first (left) transistor to ground, effectively creating a divider of the input signal.And guess what, the lower the voltage that's applied to its base, the faster it turns off when the input pulse goes down, and the sharper the mosfet's gate voltage rising edge becomes. Of course, it can't go below the minimum Vbe voltage (~700mV or so), and in practice there will be additional limitations related to the source impedance of the signal. This is interesting: at this point it calls for breadboarding.Aside from this, any other ideas? :)

author: shapirus
author_rank: Super Contributor
timestamp: December 14, 2023, 09:54:02 am
content: Quote from: shapirus on December 14, 2023, 09:33:12 amMore ideas follow. A capacitor, known as "speed-up capacitor", in parallel to R4 (between the first transistor's base and the input signal source), makes that rising edge quite nice and tight. And it's better than the pull-down resistor at base, because it won't need (as much) manual tuning to find the best value.

author: ArdWar
author_rank: Frequent Contributor
timestamp: December 14, 2023, 09:57:53 am
content: Quote from: Whales on December 14, 2023, 01:05:44 amDid everyone suddenly forgot about Miller effect?

author: shapirus
author_rank: Super Contributor
timestamp: December 14, 2023, 10:29:59 am
content: Quote from: ArdWar on December 14, 2023, 09:57:53 amOf course no, it's actually seen in the simulation plot in the first post.However, what do we make of it in this case, I mean, what does it change? Regardless of it, we still want to pull Vgate down or up, and, in the latter case, as fast as we can.

author: ArdWar
author_rank: Frequent Contributor
timestamp: December 14, 2023, 10:57:23 am
content: I was referring to Whales wondering why the lower drive transistor is so slow to turn off.Now thinking about it, it's probably just simply BJT storage time in action.

author: MrAl
author_rank: Super Contributor
timestamp: December 14, 2023, 10:58:26 am
content: Quote from: shapirus on December 13, 2023, 11:15:35 pmHi,What's wrong with a dedicated MOSFET driver IC ? That would provide the fastest switching as most of them can do at least 1 amp at high speed while these transistor solutions are probably around 500ma.The more usual case for using small transistors to drive a MOSFET is to use two transistors, one PNP and one NPN. Tie the emitters together and use that as the drive. Because your input voltage may be limited, you would use a third transistor to drive those two, along with a pullup resistor. This would take three small transistors and one pullup resistor, unless you wanted to keep that asymmetrical drive, and then you would have to add one more resistor in series with one of the emitters or maybe in series with one of the collectors.Storage time can be a problem sometimes. To reduce that as much as possible it is necessary to apply a reverse bias to turn off.In a book I read from the Rutgers library a long time ago, it was referred to as, "sweeping the charge out of the base region".That's another problem that a dedicated MOSFET driver IC would mitigate.

author: shapirus
author_rank: Super Contributor
timestamp: December 14, 2023, 11:16:48 am
content: Quote from: MrAl on December 14, 2023, 10:58:26 amNothing, really. If I were creating a commercial product, that would probably be the choice. In this case, however, it's driven by a hobbyist's desire to achieve more with less, as well as to learn something. Besides, a driver IC will have to be ordered additionally. Not that I wouldn't order them anyway, though... But they'll rather go into other projects.Quote from: MrAl on December 14, 2023, 10:58:26 amYes, that works fine to drive an NMOS regardless of the voltage difference between input and power rail (of course as long as Vin > Vth).For PMOS, however:Quote from: MrAl on December 14, 2023, 10:58:26 amI think I did try to simulate this or something similar. For some reason I did not keep it, maybe because I didn't like the turn-off time, or because the lower, PNP, transistor could be replaced by a diode without affecting the result. I will do it again and see how it simulates, then will post an update.Quote from: MrAl on December 14, 2023, 10:58:26 amYes this is what the "speed-up capacitor" also helps to achieve.I do realize that dedicated drivers will be better at it and their creators have done the R&D to solve all these problems, but the goal in my case is not so much to "drive the PMOS with a high impedance signal", but rather to "build a driver" that can do it. In other words, yes, I know I'm reinventing the wheel, but that's the point.

author: PSR B1257
author_rank: Frequent Contributor
timestamp: December 14, 2023, 11:36:07 am
content: What is the application?Why use P-channel MOSFETs (with generally worse properties compared to N-channel types)?Driving a high-side N-channel MOSFET is no option?

author: shapirus
author_rank: Super Contributor
timestamp: December 14, 2023, 11:50:44 am
content: Quote from: PSR B1257 on December 14, 2023, 11:36:07 amhttps://www.eevblog.com/forum/beginners/understanding-an-inductor-turn-off-transient/(basically measuring current flowing through an inductor)Quote from: PSR B1257 on December 14, 2023, 11:36:07 amBecause with a sufficiently high value of R1 (current sense resistor) and sufficiently high current it may be impossible to achieve Vgs high enough for the transistor to turn on: too much will drop on the sense resistor. PMOS will not depend on what happens between its gate and ground.Quote from: PSR B1257 on December 14, 2023, 11:36:07 amI can't see how. Well, I can, if there's a dedicated subcircuit referenced to the NMOS's source instead of common GND and with its own power supply referenced to source, and that will at the same time be controlled by a GND-referenced input pulse... By this time using a PMOS already sounds more attractive.

author: PSR B1257
author_rank: Frequent Contributor
timestamp: December 14, 2023, 12:33:25 pm
content: QuoteThat would be a realy high value.AgoodN-channel MOSFET has a only a view mOhm RDSon. A current sense resistor at it's drain may be in this case operational insignificant.

author: magic
author_rank: Super Contributor
timestamp: December 14, 2023, 02:03:51 pm
content: Simplification: remove D3, put R5 in series with Q4 collector if you need it.If Q4 is slow to turn off, try Baker clamping it or replace with N-MOSFET.Maybe it would work to use a -5V regulator to generate a virtual ground for an ordinary gate driver with logic input and control it by means of a voltage divider from 12V to the GPIO.Or use a 6.8V zener and resistor to the 12V rail to drive complementary emitter followers directly from the GPIO.

author: shapirus
author_rank: Super Contributor
timestamp: December 14, 2023, 05:54:02 pm
content: Quote from: MrAl on December 14, 2023, 10:58:26 amYou meant something like this?This is what I tried initially and then discovered that Q3 could be replaced with a diode (in place of the E->B pins) without any change in the result (and that's actually not too unexpected). The transistor seems to improve the switch-on time (pulling Vgate low) by a very tiny bit compared to the diode, but the turn-off time remains the same, and it's the turn-off time improvement that I'm after. It's actually already pretty good, at least, in simulation, when C2 is added.

author: PSR B1257
author_rank: Frequent Contributor
timestamp: December 14, 2023, 06:31:06 pm
content: QuoteThat's quite often the caseIf you build this thing for real, you have to deal with all sorts of parasitic elements, especially inductance, since you have a short pulse and (relatively) high current.

author: shapirus
author_rank: Super Contributor
timestamp: December 14, 2023, 07:57:54 pm
content: Quote from: PSR B1257 on December 14, 2023, 06:31:06 pmThat's actually easy to see:1. Input pulse (falling edge) vs gate voltage:2. Input pulse vs voltage at VSENS (1 Ohm for the shunt resistor for now):I'd say it doesn't look too bad for a solderless breadboard with through hole components with uncut leads.This is with C2 (=1nF) installed, ~125 nsec turn-off time. Without it, the turn-off time increases to about 1 microsecond. Generic Chinese TO-92 NPNs, TO-220 IRF5305 (original) for the PMOS. I have yet to try it with an inductor instead of R2, but it looks good enough to me for now.p.s. actual switching time, as can be seen by the sense resistor voltage trace, is much shorter than 125ns, which is, rather, the propagation delay.

author: Zero999
author_rank: Super Contributor
timestamp: December 14, 2023, 08:33:54 pm
content: I don't understand why you're using a P-channel device. The duty cycle is very low, which is even more reason to use an N-channel and a bootstrapping circuit. It's not that much more complicated, just an additional diode and capacitor. P-channel devices only make sense when the output needs to be continuously on, so a bootstrap won't work, as it needs to be off to recharge.Here's an example of a bootstrap MOSFET driverr. Q3 could be changed to a small MOSFET, such as the BSS123, then R2 and C2 aren't needed, but I used a BJT because it's easier to get hold of. The input waveform looks a little funky because I set the output resistance of V3 to 50R, to model an MCU output so the loading affects the voltage.EDIT:Did you know the forum software can scale images? This can save you the trouble of using imaging software to resize small oscilloscope screenshots.Here's your oscilloscope screenshot shrunk back down to 320x240, using image tags.

author: shapirus
author_rank: Super Contributor
timestamp: December 14, 2023, 09:24:24 pm
content: Quote from: Zero999 on December 14, 2023, 08:33:54 pmI'll have to redo my calculations once again, but the options considering the device that this will be used in (to recap, it'll be an Isattester for inductors that sends short pulses of current via the DUT) are as follows:- 5V control signal in all cases- potentially up to tens of amps flowing through the current sense resistor by end of the input pulse1) 12V power rail + NMOS -- will work, but needs calculations w/r/t the max possible current before the drop on the shunt becomes so high that it'll prevent reaching the necessary gate-source voltage2) 5V power rail + NMOS -- will work only for low currents, unless the current sense resistor is small, which will require to (pre)amplify its signal to get useful readings, and that will require a fast op amp3) 12V power rail + PMOS -- will work, but likely no advantage over NMOS4) 5V power rail + PMOS -- will work, including high enough currents (needs verifying again), plus no trouble with level conversion.Using a 12V rail has the disadvantage that it'll require a boost converter, as I plan on using USB power for the device.Using a PMOS has its own obvious disadvantages.Using 5V to power both the logic and the discharge circuit has the disadvantage that this voltage will potentially sag considerably during the discharge pulse, which will create side effects for the logic.So I'm basically exploring various options before settling on one of them. In this thread I've been looking specifically for PMOS driver pecularities and possible topologies.Quote from: Zero999 on December 14, 2023, 08:33:54 pmYes, this is pretty much the same thing that I used in my NMOS variant too, only without what is Q3 and its pull-up resistor in your circuit. This provided only up to ~4.5-5V at the gate of the NMOS, but the transistor I used turns on at a bit above 3V, so it was fine in that case.There's been a discussion here about it:https://www.eevblog.com/forum/beginners/understanding-an-inductor-turn-off-transient/I made an actual PCB with it, it works, but that's only a part of the future circuit, for which I may decide to use a different approach. Again, I'm currently exploring.Quote from: Zero999 on December 14, 2023, 08:33:54 pmWow. Nope I didn't!Thanks, this can reduce the hassle of dealing with images that this forum's engine is well known for. OTOH, I'm converting them from BMPs before uploading, anyway. However I guess the forum can handle this step as well.

author: PSR B1257
author_rank: Frequent Contributor
timestamp: December 15, 2023, 06:26:19 am
content: QuoteWheres the problem? You need some sort of storage anyway when:QuoteWith a bulk capacitor possible. The converter itself can be low power, depending on the pulse repetition (average energy demand).A second boost converter for the high-side N-channel MOSFET is then also no problem.

author: shapirus
author_rank: Super Contributor
timestamp: December 15, 2023, 09:32:51 am
content: Quote from: PSR B1257 on December 15, 2023, 06:26:19 amWell, in the boost converter itself. It'll need to be added. Not that it's too big of a problem, anyway. Easily done.Quote from: PSR B1257 on December 15, 2023, 06:26:19 amYes, that's the idea. Pulses will be very low duty cycle (maybe even a single pulse), so I'm thinking of a big electrolytic (or rather a couple aluminium polymers) plus a few MLCCs placed close to the DUT.Quote from: PSR B1257 on December 15, 2023, 06:26:19 amI haven't thought of it. Good idea. Quite feasible, too. I have quite a few of those small isolated DC-DC converters, so finally I may have found an application for them. Will only need to find a way to properly send the 5V logic signal coming from the main 5V circuit to this isolated one. Optocouplers would be an obvious choice, but most likely they'll be too slow. Magnetic-coupled isolators like ADuM1210 are faster, but expensive and really wasteful for this purpose. Maybe a resistor divider will do the job, will see.

author: PSR B1257
author_rank: Frequent Contributor
timestamp: December 15, 2023, 09:41:18 am
content: QuotePerfect.QuoteThere are also fast types out there for example 6N137. But if you have to buy this one you can also buy a proper MOSFET-driver

author: shapirus
author_rank: Super Contributor
timestamp: December 15, 2023, 10:23:58 am
content: Quote from: PSR B1257 on December 15, 2023, 09:41:18 amI already have a bunch of (however in a THT package -- so slightly higher parasitics I suppose) 6N137 and HCPL<something>. As far as I remember, they did not work very well for me when I played with something in the ~16MHz range, so they aren't super fast, but I guess they well deserve another try this time.But let's have a step back and reconsider PMOS.What are their, so to speak, absolute disadvantages, as opposed to ones relative to NMOS? The relative ones are clear: generally worse specs for the same price, lower availability etc. But, provided that I can find one that is cheap, available and whose specs are quite good (for example,AOD403), what else is to be considered that can still make an NMOS more attractive?

author: PSR B1257
author_rank: Frequent Contributor
timestamp: December 15, 2023, 10:41:48 am
content: QuoteMaybebecause there are not designed to operate at such high frequencies

author: shapirus
author_rank: Super Contributor
timestamp: December 15, 2023, 11:00:33 am
content: Quote from: PSR B1257 on December 15, 2023, 10:41:48 amwell yeah, that's true, but 10MHz is also at the edge of their capabilities, and it's about there (100ns-ish), that I'll need, or I think I'll need. So I'll have to test again and see experimentally what they're capable of. Either way, that sounds like an option.

author: Zero999
author_rank: Super Contributor
timestamp: December 15, 2023, 10:23:57 pm
content: Why use N-channel not P?You want it to turn off fast, which means the gate needs to be discharged as quickly as possible. The smaller the MOSFET, the lower the gate charge, which means fewer electrons are required to move through the gate terminal in order to switch it off. As already mentioned, N-channel devices have a lower on resistance, than P-channel, everything else being equal. This means a P-channel MOSFET, with the same on resistance of the equivalent N-channel device, will need to be much larger and have a much higher gate charge, making it more difficult to switch off quickly.Why use a separate boost converter for the gate drive?That will work, but isn't it much easier to use a bootstrap circuit, which just requires an additional capacitor and diode? A separate power supply is only necessary if you want the MOSFET to be kept on continuously. A small capacitor will easily store enough charge to keep the MOSFET on for short pulses.There were a couple of reasons why I connected Q3 as common base, rather than common emitter:1) It's faster. The base has a low AC impedance path for the Miller capacitance (base to collector).2) I thought you wanted the circuit non-inverting, so the input is high, the MOSFET will be on. If common emitter were used for Q3, it would invert.Another way to drive a MOSFET with short pulses is to use a small transformer. Here's a circuit I designed awhile ago to drive LEDs with short, high current pulses. It uses an off the shelf MOSFET driver IC, with a pulse transformer.Here's an oscillograph of the 60A current pulse through the LED, measured using a current transformer.It's probably not worth it in your case, just use a bootstrap circuit. There are off the shelf ICs, which have additional circuitry to regulate the gate voltage and protect the MOSFET from burning out, due to insufficient voltage on the capacitor, to switch it on properly.

author: shapirus
author_rank: Super Contributor
timestamp: December 16, 2023, 12:27:41 am
content: Quote from: Zero999 on December 15, 2023, 10:23:57 pmI'm gonna research this (bootstrap circuit for high-side NMOS switching). This is new stuff to me.One of potential problems here is that the pulse duration is not fixed. There will be an event that initiates it, and there will be several conditions, which, when any of them are met, will result in a turn-off signal being produced. Uusing the signal generator with fixed length pulses was just to verify the concept. I do not know yet if it's going to be an issue or not.Even if it won't be applicable in this specific case, it may be elsewhere, eventually, so I'll read, try and simulate. Thanks for the hint.Quote from: Zero999 on December 15, 2023, 10:23:57 pmIn this case I'll actually have both inverted and non-inverted outputs coming from a logic IC, so I have the luxury of being able to use either of them, whichever will be required by the specific gate drive circuit used.Quote from: Zero999 on December 15, 2023, 10:23:57 pmYes, interesting method, might very well use it somewhere too.

author: MrAl
author_rank: Super Contributor
timestamp: December 17, 2023, 01:40:00 pm
content: Quote from: shapirus on December 14, 2023, 11:16:48 amYou can also use a Baker clamp if needed. That reduces the storage time by preventing the bipolar transistor from going into full saturation.

author: shapirus
author_rank: Super Contributor
timestamp: December 17, 2023, 02:00:24 pm
content: Quote from: MrAl on December 17, 2023, 01:40:00 pmI tried to simulate it, and it failed. Now that I think of it, it was likely because KiCad insists that 1=K 2=A, whereas the external spice models usually assume the pin orientation the other way round (I used an external Schottky diode model). I'll need to try it again and make sure that the pins are (re)assigned correctly for the simulation.