How to reduce current-backlash when turning system off? - Page 1
Forum section: electronics / projects

author: LoveLaika
author_rank: Frequent Contributor
timestamp: March 01, 2022, 08:06:31 pm
content: As part of a set of improvements to my old DC-DC power supply, I'm working on what will be the portion between the DC-DC supply and the input voltage. This part consists of a PMOS for reverse-voltage-protection and an elaborate PMOS-circuit to suppress in-rush current. I'm facing an issue where there's a large "reverse-current" coming from the load when the power supply turns off, and I was wondering what can I do about it?Roughly speaking, the input voltage is 14-volts, and the DC-DC power supply load is modeled as a resistor and a 1-mF capacitor in parallel. I want to limit the in-rush current to ~3 amps in order to work with my bench power supply; I've also set my load resistance so it will draw 3 amps. The PMOS that I've chosen is the RSJ250P10 (with a threshold of -2.5 volts, RDS-ONof 48-mOhms, a max VDSof -100 V, a max current of 25 amps, and a power rating of 50-watts). The in-rush current portion of this circuit really troubled me. Several documents and sources didn't really give me the results I needed. However, I found onesolutionthat seemed to accomplish the goal where others didn't. Thus, I modeled my in-rush current limiter based on that.With that description, I've attached pictures of the power supply turning on and off (after a 100ms delay). Looking at the image when the voltage source turns on, the first PMOS works as expected. Moving on to the current limiter, the bottom-left of the in-rush limiter (R4, R6, R7, C2) acts as a voltage divider to bias the NPN (Q1). At the top, the components (R2, C5, and D2) bias the gate of the PMOS. Initially, the PMOS is closed, and the NPN is closed. When the voltage source is turned on, the NPN is forward bias, causing a charge to build up at C3. At the same time, the PMOS's gate is slowly changing, which causes the voltage at the collector to drop. As VSGbecomes larger, the PMOS is turned on, causing current to flow through the opposite side of C3. Collector voltage drops and the emitter voltage rises slowly, causing the NPN to go into saturation, which causes the PMOS to stay open. With the current going into C3 instead of the load, the in-rush current is suppressed, and the load voltage/current reaches its correct values of ~13.7 V and ~3 amps. (There's a little voltage drop which I suspect to be caused by the "large" PMOS resistances; it isn't ideal, but this is what I have so far)Looking at the other photo of when the voltage source turns off, you can see a really high "reverse-current" at the ammeter. When the source turns off, C1 discharges in the reverse direction, reaching up to 180 amps in simulation. Now, before the voltage source turns off, the PMOS is turned on, and the NPN is in saturation. VBEand VBCare both positive, under one volt. When the voltage source turns off, C1 and C3 discharge. The emitter, base, and collector voltage drop suddenly as well as the gate voltage, but the PMOS and NPN are still turned on/in saturation. Eventually, they turn off, but the large current backlash is concerning, even if it is instantaneous. As the opening question states, what can I do about it? Could I add some sort of current suppressor before my ammeter to prevent this backlash, like an inductor-based filter of sorts (or simply an inductor)? Do you have any recommendations or suggestions as to how I can improve my circuit? (While I'm at it, would an NTC thermistor help? If so, where would be the best place to put it?)

author: moffy
author_rank: Super Contributor
timestamp: March 02, 2022, 07:42:49 am
content: One of the troubles with simulations can be assigning 0R output impedance to voltage sources. Switching off a power supply can be done by disconnecting it via a switch from the load or turning off the mains supply. In neither case will it appear as a 13v to 0v step with 0R impedance. The real world is going to be a bit more complicated than your model.

author: jonpaul
author_rank: Super Contributor
timestamp: March 02, 2022, 10:59:35 am
content: Power engineering needs many consideration in valid simulation, as the transformers and inductors may be non-linear.Energy is stored in inductor and transformer cores and turn off will cause a high reverse voltage.Thus all depends on the load.Most lab/bench PSU have reverse current and voltage protection diodes.Protection includes thermistors, relays and SCR crowbars. See the App Note 90B from Hewlett-Packard, power supply design.https://xdevs.com/doc/HP_Agilent_Keysight/HP%2090B%20Application%20Note.pdfEnjoy,Jon

author: LoveLaika
author_rank: Frequent Contributor
timestamp: March 02, 2022, 03:56:25 pm
content: Thanks for replying. Yes, I see now that I neglected very important parameters. Altering my bench source to account for more realistic rise/fall times when turning on/off, the issue goes away (or at least becomes negligible).

author: moffy
author_rank: Super Contributor
timestamp: March 02, 2022, 09:57:46 pm
content: Glad to hear that, nothing worse than chasing ghosts.