Best way to fanout a big BGA (1760 pads) - Page 1
Forum section: electronics / general

author: fjnieto15
author_rank: Newbie
timestamp: May 26, 2018, 02:17:10 pm
content: Hi!I need to fanout a big FPGA with a 1760 ball pads. I was wondering if there is a better way of doing this rather than adding 200000 layers.Many of the signals are LVDS and they need to be shielded with ground planes above and below, which at the end it means that every signal layer I need for the fanout, I have to add two layers, one for signals and a ground plane. My layer count is up to 16 layers right now and I can't get to the inside of the FPGA yet.Am I missing anything? I'd like to keep the cost relatively low.Also, Xilinx provide some design rules in which there are some alternatives to escape two traces between two pads, is it possible to do this in Altium automatically?Thanks for your help.

author: tszaboo
author_rank: Super Contributor
timestamp: May 26, 2018, 04:48:11 pm
content: Probably with blind and buried vias you can reduce the layer count.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 26, 2018, 07:14:01 pm
content: Low cost? Use two 900-pin BGAs.If you can find one with blank spaces in the footprint (e.g., four rings of pads, then some open space, then some more pads in the center), you'll have better luck. I don't think these are very common with FPGAs, probably because you're paying so much for this chip already that a 16+ layer board isn't a big deal. They seem somewhat common in computer parts, usually system chips. Though I guess they don't have much choice with CPUs, which have been full pin/pad grids for a long time. Dunno.Have you considered optimizing the layers for breakout? You only need so many power layers, and signal layers can be paired when their timing is not extreme (i.e. super low jitter).Tim

author: Ice-Tea
author_rank: Super Contributor
timestamp: May 26, 2018, 07:18:32 pm
content: As an FYI: a reference plane does not have to be GND. AC doesn't care. A related power plane is just as well.

author: voltsandjolts
author_rank: Unknown
timestamp: May 26, 2018, 07:30:36 pm
content: Very best of luck with that. Stay sane and keep smiling

author: Doctorandus_P
author_rank: Super Contributor
timestamp: May 26, 2018, 07:45:47 pm
content: Very recently there was this exact same question on the KiCad forum:forum.kicad.infoThe answers there had a few good hints, including a link to a PDF with a lot of examples.You can also have a look at the Olimexino A64.It is a complete project with BGA's done in KiCad, and is on Github, including schematic / PCB layout.

author: fjnieto15
author_rank: Newbie
timestamp: May 26, 2018, 09:17:47 pm
content: Quote from: NANDBlog on May 26, 2018, 04:48:11 pmI've thought about it, but the prices of blind/buried vias are much higher than adding 2 more layers. I can't see the real advantageQuote from: T3sl4co1l on May 26, 2018, 07:14:01 pmI didn't mean low cost, but reducing the costs that can be reduced. It is a 40x25 cm board, nearly 3k$ so I would like to avoid it going over 5k$.What do you mean by optimizing the layers for breakout?Quote from: Ice-Tea on May 26, 2018, 07:18:32 pmSo, do you mean that shielding the LVDS signals with power planes is as good as doing it with GND? Even with different voltages?Quote from: Doctorandus_P on May 26, 2018, 07:45:47 pmI'll take a look, thanks!Thanks for all of your answers and help

author: Daixiwen
author_rank: Frequent Contributor
timestamp: May 28, 2018, 10:19:34 am
content: Quote from: fjnieto15 on May 26, 2018, 09:17:47 pmYes. Just make sure that the power plane you choose is properly decoupled to ground with capacitors near both ends of your LVDS signals, and that the power plane doesn't have any cuts that the signals would cross (just like a ground plane). The return currents will happily go through the power plane, even if that power isn't actually used by the LVDS component.

author: Doctorandus_P
author_rank: Super Contributor
timestamp: May 28, 2018, 10:20:33 am
content: Did a bit of digging:One of the fun things about KiCad is because of it's open-ness all kind of side projects pop up.I have not used BGA's myself, but this semst o be a project to partly automate the fan-out of Big ball BGA's.https://forum.kicad.info/t/bga-vias-as-part-of-footprint/10083/10Bit it is of course limited to KiCad.The thread I thought of was:https://forum.kicad.info/t/0-4mm-bga-via-in-pad/5240/3]https://forum.kicad.info/t/0-4mm-bga-via-in-pad/5240/3] https://forum.kicad.info/t/0-4mm-bga-via-in-pad/5240/3and the document with examples is from lattice:https://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/PT/PCBLayoutRecommendationsforBGAPackages.pdf?document_id=671

author: ehughes
author_rank: Frequent Contributor
timestamp: May 30, 2018, 12:45:21 pm
content: QuoteIt think that ship has sailed! :-).I did a Xilinx device with 1738 balls. It took 20 layers are 10 reference planes to get it done. @13k USD for 10 boards (that were 6U card size) from Streamline. I used a fairly exotic dielectric (which allowed me to get 20 layers @ 0.0625" thickness).If you haven't already, call the board house *now* to work out your stackup.

author: EEVblog
author_rank: Unknown
timestamp: May 30, 2018, 12:52:33 pm
content: Quote from: fjnieto15 on May 26, 2018, 02:17:10 pmWhat frequency?How many pairs?On which rows are the pins located?Can the critical pairs be moved to outer row pins?

author: Doctorandus_P
author_rank: Super Contributor
timestamp: May 30, 2018, 01:04:06 pm
content: Quote from: ehughes on May 30, 2018, 12:45:21 pmSome time ago I heard / saw a story / interview ( Davey Jones / youtube?) about a guy who did PCB layout for a living. One of the projects he did was from a client who could not get a board layout in 12 layers, and came to him.He said something like.Well, I can do that for USD *** in a day or so, or I can redo the whole board for USD **** (4 digits) and then do it in 8 layers.His client did some calculations, and he got the job to redo the board in 8 layers.Anybody can draw a few traces on a PCB with a CAD package, but a good PCB layout is artwork.

author: mengfei
author_rank: Regular Contributor
timestamp: June 21, 2018, 06:10:06 am
content: Quote from: Doctorandus_P on May 30, 2018, 01:04:06 pmawesome mind & skill that guy have, do you still have the link to that video?

author: Paulvanavesaath
author_rank: Newbie
timestamp: July 16, 2018, 09:17:30 am
content: Hi Just did a XCVU13P with 2104 balls on 16 layers (8 singal layers 8 internal planes) .. with blind and micro via's (via pairs 1-2l, 1-3, 1-16, 14-16, 15-16)is definitly doable..with regards to the signaling, you need solid planes, but they do not need to GND.. the reference is not to ground, but to copper.. so you can reference the impedance from any potential.good luckl

author: EE-digger
author_rank: Frequent Contributor
timestamp: July 31, 2018, 12:16:56 am
content: Dave beat me to it. Have you fully excersized your pin swapping to bring the signals to the perimeter? LVDS is differential and while you still need a return path, it is only for a small percentage of the signal. You may want to run, or have someone run, SI simulations to see if the plane above and below are necessary. For adjacent LVDS layers, route orthogonally as you would for single ended signals.Also, while a return path does not need to be GND, be sure to pepper the planes with high frequency caps. You want the impedance of that power plane to be as low (almost) as the GND plane at the frequencies of interest.