Help Understanding my JFET amplifier - Page 1
Forum section: electronics / beginners

author: tron9000
author_rank: Frequent Contributor
timestamp: January 13, 2017, 10:18:37 am
content: Morning all.I've been playing around with JFETs in TINA TI in order to refresh my memory and managed to build this amplifier circuit (file see attached-schematic below):and obtain the bode plot as shown below:As you can see (ignoring the hump in the roll off at about 1kHz)) I get about 19dB gain between 10kHz and 1MHz, which is what I was aiming for (some gain between 10kHz & 1MHz)The problem I have is that Id = 6.68mA, Vgs = -1V & Vds = 5.52V and From looking at figure 3 on the datasheet(http://www.farnell.com/datasheets/2172091.pdf?_ga=1.96281884.1080831287.1470060388), that these values do not appear to match any of the curves on that table?I'm quite confused as I was hoping to prove this correct. Have I done something daft? or even misunderstood something?The method I used to calculate these values was to set the Vgs Bias to half the pinchoff voltage and set R1 using the approximation that Vgs=Id*Rs and equating Id=Ids=Idss(1-(Vgs/Vp))2- Schokly's EquationThen, with a supply voltage of 12V I ideally wanted Vd = 6V and calculated R2 using ohms law.C3 was adjusted till the desired roll off was acquired.Another question: I realise the method I've described above doesn't really allow you to design the amp to a specific gain. Is there a correct way to design with a specific gain? Also id the maximum gain dictated by the JFET's maximum transconductance?cheers for any advice and help

author: eblc1388
author_rank: Frequent Contributor
timestamp: January 13, 2017, 11:59:56 am
content: My suggestion is to measure the physical characteristic of the JFET in your hand first before designing any circuit, rather than base solely on the data given in the datasheet. JFET characteristic has a very large spread.I am surprised to find out the IDss characteristic of my batch of J112 from RS-Online UK. I even wonder if there was something wrong with my test. However, after testing fifteen samples, I started to believe that was typical what I have on hand.I attach test result of three random samples I have tested. They all have IDss > 40mA.

author: tron9000
author_rank: Frequent Contributor
timestamp: January 13, 2017, 12:25:02 pm
content: whats the test setup for obtaining those curves?

author: danadak
author_rank: Super Contributor
timestamp: January 13, 2017, 01:00:55 pm
content: The datasheet graphs typically come from the Production Engineer/Designer characterizingsome samples. Specs vary a lot, some instances 100's of percent, one device to another.Although a specific lot of devices may have close agreement as they come from the samewafer run.To design for G start here (google "jfet amplifier gain analysis") :https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-101-introductory-analog-electronics-laboratory-spring-2007/study-materials/jfet.pdfBasically choose G, then backtrack to establish needed Gm which will then establishId then leads to Rl, Rs, Bias. Its an iterative process to some extent. Note if you lookat the Gm equation it has a stong dependence on Idss, Vgssoff, which you cannotcontrol unless you stipulate in procurement an Idss and Vgs range. This is impracticalthese days unless you are talking about zillions of parts and/or large price adders.Just one of the reason using an OpAmp circuit where very high available Aol allows,with fdbk, accurate G setting.Regards, Dana.

author: tron9000
author_rank: Frequent Contributor
timestamp: January 13, 2017, 01:20:37 pm
content: just so I don't confuse terminology.Is Vgssoff = Vp (pinchoff voltage?)

author: danadak
author_rank: Super Contributor
timestamp: January 13, 2017, 01:25:42 pm
content: Note one way of handling fixed G problem for a signal path is AGC solution,but that has its own benefits/burdens.Regards, Dana.

author: eblc1388
author_rank: Frequent Contributor
timestamp: January 13, 2017, 02:26:18 pm
content: Quote from: tron9000 on January 13, 2017, 12:25:02 pmThe setup operates under Agilent VISA COM library control vs USB and GPIB connected instrument.USB connected Rigol Signal Generator DG1022 providing DC gate drive and GPIB connected HP6632B power supply for VDS. JFET Id Current value is read back from HP6632B. All instrument control, measurement and curve plotting happens inside Excel. It took about five minutes to obtain a characteristic plot of 384 data points.

author: tron9000
author_rank: Frequent Contributor
timestamp: January 13, 2017, 02:38:38 pm
content: say I don't have access to that kind of kit at home. can I just set a negative supply across Vgs and turn up Vds and observe and record current on DMM?

author: eblc1388
author_rank: Frequent Contributor
timestamp: January 13, 2017, 03:00:02 pm
content: Quote from: tron9000 on January 13, 2017, 02:38:38 pmSure you can. It is exactly how I did to test my JFETs.

author: tron9000
author_rank: Frequent Contributor
timestamp: January 13, 2017, 03:22:01 pm
content: just making sure the method I had in my head was correct.