High Speed ADC Board Schematic/Layout Review - Page 1
Forum section: electronics / projects

author: rheb1026
author_rank: Regular Contributor
timestamp: June 14, 2017, 05:23:33 pm
content: I hope this is the right section to post this...I've been sitting on this board for a while doing lots of reading/tweaking and I'm finally tired of waiting around for it to be "perfect" and just want to get it sent out and get moving on my project. So I'm looking for a second set of eyes to review this and give me any suggestions. This board is going to be for a direct sampling receiver (0-30 MHz). I have almost no experience with high speed digital design besides what I've read in books, so take this into account. I understand that it's probably cheaper/easier in the short term to buy the demo board, but I'm doing this for fun/learning.Some notes before viewing the schematic:* This will be connected through an adaptor board (Hirose FX to VHDCI) and attached to a Digilent Nexys 3 board.* +3V3B is the 3.3V supplied by the Digilent board.* The ADC will run at 3.4V max, so I put a LDO in just in case I decide to run it at 2.5V or 3V. Anywhere in the schematic labelled +3V3 would be this voltageSome questions I have:* What is the best method for routing the oscillator clock signal? Should I lengthen the clock signal going to the ADC so it more closely matches the length of the trace going back to the FPGA? I haven't measured the trace length, but off hand I'd guesstimate 5" between the oscillator and FPGA.* Should I fill copper on the top and bottom layers of the board? This is a four layer board with a solid ground and power plane internally.* The Linear demo board shows a buffer between the ADC digital outputs and their other acquisition board. Is this necessary?

author: Howardlong
author_rank: Super Contributor
timestamp: June 14, 2017, 05:48:15 pm
content: I always flood fill on all layers.It looks like some of this is a bit over-engineered, for the speed you're sampling at there's really no need for serpentine traces.You may wish to consider damping resistors on the digital lines though.Make sure any LDOs in the analogue domain are super low noise.Make sure the TCXO isn't digitally compensated (that leads to discontinuities in digital modes) and that it's a "proper" oscillator, not a factory programmed one for minimum phase noise.What antialiasing techniques are you using in the analogue domain?Edit: don't be shy with ground stitching vias.

author: DaJMasta
author_rank: Super Contributor
timestamp: June 14, 2017, 06:24:57 pm
content: Maybe an LC low pass filter right on the input power? You're going to have a very low resistance path to the supply with so many conductors, but they're going to be sharing a cable with a bunch of digital lines, so there will be noise, and since it's coming into the same connector, you probably can't just slap on a ferrite on the input power line.I don't think there's any issue with the clock trace length as is... though is it that important to clock the FPGA on a separate board from the same source? The only thing lengthening of the trace is going to get you is a different relative phase of your clock signal, and I don't think that is a problem in this case (though if your ADC has a synchronous output that has to be matched in the FPGA... maybe? Though in that case wouldn't you clock the FPGA directly and then pipe over the ADC clock with the data lines?)I honestly don't know how beneficial this would be, but you could make a separate ground plane for the analog input which meets the main board ground at the ADC. This would be somewhat analogous to star grounding with the reference at the ADC's ground, but since there's so much ground plane around I wouldn't expect it to make a big difference, if it makes one. I can't say I've done enough testing or have enough understanding to make a compelling point for it, but it could be a consideration.

author: suicidaleggroll
author_rank: Super Contributor
timestamp: June 14, 2017, 06:41:13 pm
content: You're going to get a lot of power supply noise in there, I hope that's ok. I'm not sure what the ripple coming out of the LTC3633 on the Nexys 3 is, but if it's like most other switchers it's probably in the tens of mV at a frequency of 2 MHz. With a full 1V drop on the LT1763 you're looking at less than 20dB of PSRR at 2 MHz (with less drop you'll get less rejection), so single digit mV ripple on your analog power supply line. I'll leave it to you to look up the PSRR on your analog components (pre-amp, adc, internal reference, etc), but it's not going to be great at those frequencies. You'll likely see a lot of energy at 2 MHz in your samples.If that's not acceptable, you'll want to switch to an LDO that's better equipped to handle ripple at these frequencies, such as the LT3042 (90dB PSRR at 2 MHz). But like any linear reg, you need a healthy voltage drop across it to get that kind of rejection, 3.3V in and 3.0V out won't cut it, 2.5V out probably still isn't enough. If you want to run at 3 or 3.3V then you may want to consider adding a boost converter to get the input voltage up higher, giving your LDO more room to clean it up.As Howardlong mentioned, you should also seriously consider an antialiasing filter as well. Perhaps switch to the filtered output of the LTC6401 and/or add an external cap to create a lowpass filter at an appropriate frequency. It's not going to do a lot, but it'll help.Also it's been mentioned before, but it's worth repeating. The wavelength at 60 MHz is 5 meters. You'll want to length-match your lines to better than 1/10 (maybe even 1/100) of that, but that's still several inches. There's no need to length match down to the mm like you've done, that's for signals running into the GHz. You will probably want to add series resistors on the data lines leaving the ADC though.

author: Flanbix
author_rank: Contributor
timestamp: June 14, 2017, 06:49:00 pm
content: It is always better to fill layer with copper, on large board it can avoid warping.For high speed design, you will probably adapt your track thickness for impedance and use an SMD connector (or use your through hole one on the other side) to avoid "stub". But as the frequency are low and you probably don't control the stack up, this is not important.I always find easier to read schematics when all the ground are pointing down and all the rail voltage pointing up. Some symbol (U101, U103) lack clarity.

author: dmills
author_rank: Super Contributor
timestamp: June 14, 2017, 08:10:25 pm
content: The LTC6401 is a 200 ohm input impedance device, so there is an opportunity for 6dB of noiseless gain there by placing a 4:1 (impedance) balun at the input.I would be thinking about a separate regulator for the clock and its buffer, else you will likely see switcher spurs from your power supply in the output spectrum (Phase noise from the clock module), and you will want to have a careful think about PSRR at speed anyway, LC filters often trump LDOs above a few MHz.ADC outputs are best if driving low capacitance loads, not long traces, buffer then or at least place source terminating resistors.The Vref decoupling, might be better to use an interdigiated cap here for the low value bit, less stray inductance that way.C155 and friends probably wants to be right up against the side of the converter.The clock should probably do flow thru routing past the clock buffer as otherwise you will get reflections from the buffer connection stub.The digital connector has a weirdly sub optimal pinout for single ended high speed cmos, is this fixed or can you do something more reasonable (Mix the ground and power in among the signal pins to shorten the loop areas, if you do this scatter some caps between 3V3B and ground in that area so the 3V3B pins have a low inductance path to ground)?I second the note to be careful of TCXOs of the sort that do digital temperature compensation, stupid things.Some ESD protection is also not a bad plan, back to back low C diodes are a reasonable approach for the RF port).

author: rheb1026
author_rank: Regular Contributor
timestamp: June 15, 2017, 03:25:29 am
content: Quote from: Howardlong on June 14, 2017, 05:48:15 pmThanks for all the information, I wasn't really sure whether or not the trace length matching would be needed, but I figured it was better to have and not need.Should I still add the damping resistors even though the ADC presents a 50 ohm impedance and the trace impedance will be close to 50 ohms? What kind of ballpark value should I add?Thanks for the tip about the TCXO, I will look into it.I didn't add any front end filtering between the RF connector and the op amp because I was going to make and test out a few filters and eventually put that in line between my signal generator (and eventually an antenna) and the input to this board.The only filtering between the op amp and ADC is just a simple RC LPF. Should I use a multi pole LC filter?Quote from: DaJMasta on June 14, 2017, 06:24:57 pmI'll have to look into the pinout of the connector and see if I can spread the digital lines between some of the ground and power pins.The synchronous output was my concern about the clock signal and the FPGA. I'm wondering if it would be better to just route a clock signal from the FPGA to the ADC?I've read both when it comes to the grounding. The LTC demo board does have a star ground right under the ADCQuote from: suicidaleggroll on June 14, 2017, 06:41:13 pmThanks for pointing out the PSRR issue. I did overlook this and will replace the LT1763 with the LT3045 which should help a lot.Quote from: Flanbix on June 14, 2017, 06:49:00 pmThank you for the feedback on the schematic. I don't usually get any feedback on this outside of work, and if you saw the schematics the other engineers I work with drew you'd have a hard time taking their feedback seriously!Quote from: dmills on June 14, 2017, 08:10:25 pmThanks for all the information. I didn't think of that with the balun, I'll definitely look into it.Can you explain flow through routing? I'm not familiar with the term and a quick search didn't bring up anything usefulI've never heard of an interdigiated cap before, I'll have to look into this, too.The connector is not fixed and I'll take a look at the connector pinout and see if I can spread around the signal pins with the ground/power pins.Good catch on the ESD diodes, this was another thing I forgot!

author: suicidaleggroll
author_rank: Super Contributor
timestamp: June 15, 2017, 05:08:36 am
content: Quote from: rheb1026 on June 15, 2017, 03:25:29 amAt high frequencies you have to start watching out for stubs. Those are short traces that branch off of a longer trace and "dead end" so-to-speak. Signals will travel down the trace, branch off down the stub, hit the end, reflect back, and re-join the original signal at some phase offset based on frequency and stub length. These stubs and resulting phase shifts can cause problems like double clocking (FPGA picks up two rising edges per clock pulse) or similar. In short, at high frequencies stubs are problematic. It's better to route your signal "through" the pad, instead of routing it near it and using a stub to connect to it. In other words, use the pad as part of your trace.

author: Howardlong
author_rank: Super Contributor
timestamp: June 15, 2017, 10:14:59 am
content: Quote from: rheb1026 on June 15, 2017, 03:25:29 amYou're right, that device has internal damping resistors, nice! Depending on your trace lengths, board stackup and materials, you may want to consider trace width but I suspect the signal distances are going to be short enough for it to not matter.QuoteYes, the full power bandwidth of that ADC is 575MHz, you'll definitely need some reasonable form of band limiting, RC alone certainly won't be enough. As the maximum sample rate is 65MHz, and you're looking for an input frequency range of 0 to 30MHz, a target transition region of 30 to 35MHz will be just about doable with a lumped LC filter of sufficient order using fixed of the shelf components.

author: dmills
author_rank: Super Contributor
timestamp: June 15, 2017, 11:57:33 am
content: Quote from: rheb1026 on June 15, 2017, 03:25:29 amThat is horrible from a phase noise perspective, the FPGA only needs the clock to be good enough to reliably meet setup and hold on the data and for its internal PLLs to lock, in the ADC clock phase noise directly impacts system noise, you REALLY CARE about the ADC clock, and routing it via the FPGA fabric is not going to reduce the phase noise.Regards, Dan.

author: rheb1026
author_rank: Regular Contributor
timestamp: July 07, 2017, 02:29:23 am
content: I apologize for taking so long to get back, life has been very busy lately. I just wanted to thank all of you for your input, I'll be sure to post any further questions I have once I have the time to get back to this and finish it up

author: bson
author_rank: Unknown
timestamp: July 08, 2017, 09:50:00 pm
content: Why an XO on the ADC board - why not obtain a sample clock from the FPGA? This way you don't end up with multiple clock domains and can adjust skew and/or the sampling rate from where the data is used. If you update the processing you can update the acquisition rate accordingly.