SMPS Input Filter Design - How is it done in this article? - Page 1
Forum section: electronics / projects

author: arildj78
author_rank: Regular Contributor
timestamp: July 31, 2019, 06:57:20 am
content: In the articleSMPS Input Filter Design: Negative Resistance Approachthe author shows some circuits that looks very much like an LTspice simulation. I tried to recreate them in LTspice with no luck, so I concluded that I had not understood how to find the Z_FilterOut. For the 33µH circuit I get 0.6Ω for low frequencies, 5mΩ for high frequencies and 1.52Ω at 4.0kHz. In the article the filter output impedance is found to be Z_FilterOut=11.5Ω at 4.1kHz.Also, I do not understand the model of the inductor. From searching online I find inductor models like this:https://wiki.analog.com/university/courses/electronics/comms-lab-isrI guess that L1, R1, C1 and R2 is modeling the inductor in the LC filter, but I don't recognize the model. For instance, where do the R1=10k come from?Any help would be appreciated

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 31, 2019, 09:09:29 am
content: The inductor and capacitor models are a typical 2nd order form.For the series equivalent (capacitor), measure C at low frequency, L at high frequency, and measure the peak inbetween to find R.For the parallel equivalent (inductor), measure L at low frequency, C at high frequency, and measure the peak inbetween to find R.The inductor you usually add DCR in series, so the model is again correct at DC, not just a low frequency. This gives a 4 point fit. Capacitors you'd add a resistor in parallel to get leakage, but this is usually large enough to ignore.For fitting more points, a still higher order model is desirable; this for example:https://www.seventransistorlabs.com/Calc/Coilcraft1.htmluses a diffusion function to represent both copper and core losses, and has a more nuanced high frequency cutoff (R+C) model.This page allows you to play around with the parameters and see the impedance curve, and also generate a model from it if you like (follow the LTSpice instructions for installing and using a model).Most of this is irrelevant to the present example, because the frequency and Q are both low. A DCR + L model will suffice.What are you missing in your model? Note the current source is an AC source, and its frequency is varied according to the directive. Its magnitude is 1A, so the voltage measured across it corresponds to V = I*Z = (1A)*Z, or ohms impedance at a 1:1 scale.The article makes a fatal error about the negative resistance characteristic: it is also a bandlimited characteristic. It is true at DC, but somewhere between DC and the loop cutoff frequency or Fsw (depending on architecture), it becomes positive, and probably inductive. This probably contributes to the 3.3uH case being much more stable than the DC negative resistance alone would suggest.That said, the DUT appears to be running around 400kHz, so the filter cutoff (4 and 14kHz in the two respective cases) should be well below the loop cutoff frequency, and so there should be some negative resistance in play here, if still not necessarily the full DC value.The other solution is to introduce additional damping, by taking the total value of C2+C3, about tripling it, and connecting that in parallel, with ESR = sqrt(L1 / (C2+C3)). Put another way: introduce a third parallel branch, like C3+R4, but with Cnew = 3*(C2+C3) and Rnew = sqrt(L/C).Typically, an electrolytic or tantalum capacitor is chosen to meet this, or ceramic or polymer with added series resistor. This allows significantly more freedom in choice of L, including if the source is particularly inductive by itself (say by being at the end of a long cable).Tim

author: arildj78
author_rank: Regular Contributor
timestamp: July 31, 2019, 09:27:37 am
content: My problem is a simple one. I've designing my first SMPS and are trying to minimize EMI. The circuit is powered from 3xAA batteries and to minimze loop area for high switching currents, I figured that it would be smart to add a LC-filter in front of the SMPS (also as a learning experience before designing something powered off the grid).The design input voltage is from 3 to 5 volts (to give a steady 9V out). Output power from 1 to 20W, with a nominal 7.86W. The efficiency of the SMPS is estimated to 95% at nominal power and 90% at min and max power.From these numbers and the article referenced above I figured that the input impedance of the SMPS is from -0.45Ω to -25Ω. Now I tried to use these numbers to design the input filter, but got stuck when I couldn't replicate the graph from the simulation in the article.You say that the article have a fatal error, so now I'm bewildered. How should I go about to make sure that switching noise does not propagate upstream toward the battery or other loads connected to the same source?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 31, 2019, 10:01:43 am
content: For the battery, actually -- doesn't matter, it's a big electrochemical capacitor. Indeed it has very much the Z ~ sqrt(1/F) diffusion response means that, attaching an LC resonator to one, tends to dampen the Q quite well.You'll have some stray inductance due to the batteries, pack and connecting cable (under 1uH I would guess), and this has a lowpass against the SMPS input caps. Batteries don't radiate (any more than their physical size allows), so this will most likely suffice.For testing from a bench supply, you may find it beneficial to add a CLC filter, so that you aren't measuring the ripple that would otherwise be reaching the battery. And this will manifest as common mode noise.Common mode noise: effectively, both wires to the power supply have inductance, so half the ripple reaching the supply appears as ground loop voltage. Half of it dropped across the +, half across the -. If the power supply is earthed, and the scope is earthed, the minus voltage drop appears between these however, and you'll get a ground loop error, anywhere you probe in the circuit -- even if probing from ground to ground (clip the probe tip to the ground clip, and poke that at circuit ground)!And if you're using a corded power supply, or making an offline supply, same thing applies of course, noise going up the power cable can manifest as errors when connected through to other things. So while you probably don't need to go for it in the battery case, this will be what you're shooting for, and what you'll see if it's bad, and also how to fix it (common mode chokes to break that ground loop!).So for the filter, the negative resistance is still there, it's fine; I'm just saying it has less significance at higher frequencies (closer to Fsw). Though it's not entirely clear how much less. It would be best to determine by measurement -- set up an impedance measurement fixture (also known as a bias tee), and actually measure the input impedance of the SMPS itself.For filter design, the lowest magnitude is the most significant; -25Ω in parallel with modest value resistances is still positive, but -0.45Ω dominates much more strongly.Again, use a parallel damping R+C (somewhat oversized C*, matched R), you can dominate even that, and dampen the LC at the same time.*Oh, also, C can be much bigger, no problem there. Electrolytics often need to be huge to get the ESR down where you need it, and as long as the extra capacitance doesn't cause other problems (like uh, inrush current I suppose, or of course bigger physical size, or higher cost), that's fine.Personally, I never worry about negative input resistance, because it's mostly a low frequency parameter, and because my filters are designed for low impedances (the characteristic impedance of an LC is sqrt(L/C)) in the first place, and well damped on their own.By the way, the meaning of impedance of a filter, is this: if you have a step change in current at the load, then expect its voltage to fluctuate by ΔV = ΔI*Z. This of course matters when a substantial negative resistance is in parallel (ΔV/ΔI is dominant and negative), but it's also important to operation of the SMPS itself (you don't want load changes to cause wide swings in supply voltage), and designing to the latter (for a moderate sized fluctuation, ΔV/V < 10%, say) covers the former.Tim