Building my own scope - Page 1
Forum section: electronics / testgear

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 11:14:36 am
content: Ok, that could be way-over-my-head kind of project, but gathering some information won't hurt.Here is what I'd like to do, in general terms:1. Buy a Xilinx Zynq board (or something similar).2. Buy some decent ADCs and attach them to the board.3. Use something like Scopy as scope software.Do you think it's doable?Alternatively, one could just buy a PCIe ADC board with 4 channels and snap it into a common PC.Again, it this doable in a reasonably non-nightmarish way?

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 20, 2022, 11:21:19 am
content: Depends on your skills of coarse, but it is doable.Making something really high end and fast is more difficult and expensive though.It is also the question why. If you need a scope for your hobby it is easier and probably cheaper to just buy one. If it is a hobby to build one then nothing is stopping you to just try. It can be a lot of fun.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 11:34:09 am
content: Quote from: pcprogrammer on October 20, 2022, 11:21:19 amI'm motivated by two reasons, essentially:1. I'm dissatisfied by commercial scopes within my financial reach (say 1 grand).2. I think I'll learn a lot of things by building my own scope.That said, I'm having difficulties finding the ADCs, primarily because I don't know exactly where to search, and apart from the main specs (e.g. resolution in bits, etc..), I don't know what to look for... Here is where I need advice.

author: 2N3055
author_rank: Super Contributor
timestamp: October 20, 2022, 11:41:40 am
content: Quote from: balnazzar on October 20, 2022, 11:34:09 amOnly do this if you want to learn. Prices for parts scope manufacturers get are very different from prices you will get for same parts at low quantity. FPGA + 2 ADC might cost you more than twice your budget for scope... Not to mention that it is not a beginners quest. There are dozens of open scope projects on net, and dozens topics here on the forum. Some attempted by pro FPGA designers and whatnot. None of them went to working product. Making a scope is a large, very hard project.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 11:57:16 am
content: Quote from: 2N3055 on October 20, 2022, 11:41:40 amI was thinking.. Let's not consider a FPGA-based project for now. It could be very, very interesting from a learning point of view, but I think it's too hard given my current level of competence. So, let's talk about ADCs on a regular desktop PC.Consider Digilent Waveforms, a fine piece of software. It does all the things I need, essentially.It works OOB with any soundcard. A soundcard is essentially a low frequency ADC.It's not unreasonable to assume it'll work with a PCIe ADC.The problem is that I'm having a hard time finding pci-express ADCs.Maybe you can point me towards some manufacturers?The only one I was able to find is this:https://dev.alazartech.com/en/Prices are nowhere to be found though.

author: nctnico
author_rank: Super Contributor
timestamp: October 20, 2022, 12:05:23 pm
content: You might want to start with something that already works and go from there. Maybe the AD2 is suitable. An alternative is to use your existing oscilloscope as an acquisition device and do data processing on a PC.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 20, 2022, 12:09:52 pm
content: Quote from: balnazzar on October 20, 2022, 11:34:09 amFor that kind of money there are acceptable scopes to be bought, but it depends on your demands on it if you can like it.Quote from: balnazzar on October 20, 2022, 11:34:09 amYes, you can learn a lot by doing it but like 2N3055 wrote it is a large project when you want it to be up to all your demands, which seem to be high going on not being satisfied with what is available on the market.On the other hand, sticking modules together and throwing some open source software in it, will not be much of a learning experience in my eyes. Writing your own FPGA code for the acquisition bit and the software to process the samples will, but it involves a lot of knowledge.Quote from: balnazzar on October 20, 2022, 11:34:09 amThis also depends on what you need. If 1 GSa/s and 8 bit is enough then there are more then enough ADC's out there, but getting a module to stick it to a zynq board becomes much harder.A four channel ADC board for in the PC with high speed will be expensive too.I dabble with this kind of things for fun, but on much lower frequencies. Made new software for the FNIRSI-1013D, which was fun and a good learning experience, but it took time.

author: 2N3055
author_rank: Super Contributor
timestamp: October 20, 2022, 12:13:38 pm
content: Quote from: balnazzar on October 20, 2022, 11:57:16 amYou're not listening. As I said, first go and do a search on previous art. What you think, you are the first one that had this idea?Humanity has been building scopes for 80 something years, and digital scopes for 30 something.If it were easy and cheaper than buying ready made device, we all would have home made scopes.Of course you need FPGA. It's hosting triggering, data transfers from ADCs, memory transfers etc. It guarantees scope will sample at regular intervals and will have enough data BW to do so. ADC is only a dummy device doing conversions. Scope is in a FPGA...And then there is a matter of scope front end before ADC.Scope is much different than sound card..Read on the subject first.And soon enough you will start to realize that even cheapest scopes are marvel of engineering and very sophisticated devices..

author: rob77
author_rank: Super Contributor
timestamp: October 20, 2022, 12:19:10 pm
content: Quote from: balnazzar on October 20, 2022, 11:34:09 amyou will not build a better scope with the same money... it doesn't work that way.. people tend to underestimate the effort and overestimate their capabilitiesi have a few "long running" projects myself.if your motivation is to learn, then go ahead full steam ! but expect much higher cost than buying the scope and what's more important, expect a giant investment of your time.and just a small piece of advice ... always quadruple your time estimate to get closer to reality

author: Fungus
author_rank: Super Contributor
timestamp: October 20, 2022, 12:35:32 pm
content: Quote from: balnazzar on October 20, 2022, 11:34:09 amWhat don't you like?Building something better is going to cost much more than $1000 of your time.(unless you're in prison or something...)

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 20, 2022, 01:17:39 pm
content: Here are some threads on this forumhttps://www.eevblog.com/forum/testgear/a-high-performance-open-source-oscilloscope-development-log-future-ideas/https://www.eevblog.com/forum/chat/500-mhz-8b-2gss-oscilloscope/The first one shows what it takes and it was never finished due to not having the time to work on it anymore.This kind of development takes a lot of time and money for something better than store bought.As a learning project I would suggest cheaper modules that do at max 100MSa/s and a simple FPGA connected to a simple MCU.I started a project to make both a scope and a function generator. Due to shifting interests I left it as is, after finishing the FPGA part for the function generator. Might continue with it someday.https://github.com/pecostm32/Lichee_Nano

author: ledtester
author_rank: Super Contributor
timestamp: October 20, 2022, 01:49:16 pm
content: Saw this listing on ebay:https://www.ebay.com/itm/114051630870Probably doesn't have the specs you want but still could be interesting because there seems to be rather extensive documentation about how it works here:https://earthpeopletechnology.com/digital_storage_oscilloscope_dso_100m

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 05:42:35 pm
content: Quote from: nctnico on October 20, 2022, 12:05:23 pmYou mean for building the custom scope?

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 05:53:52 pm
content: Yours was quite an informative reply, thanks.Quote from: pcprogrammer on October 20, 2022, 12:09:52 pmUh, I wrote extensively about that in other threads, for example the one baout bode plotting on a MSO5K. Essentially, I'm bothered by acoustical noise (1104x-e) and front end noise (MSO5000). USB scopes starting with 100 MHz and 1 GSa/s are expensive (the pico is near 1500 eur).Quote from: pcprogrammer on October 20, 2022, 12:09:52 pmThat's the problem. I don't even know where to start. I don't have any experience with the FPGAs, and the discussions here are generally between people who already have a lot of expertise about them.Quote from: pcprogrammer on October 20, 2022, 12:09:52 pmMh, can you give me some links to shops where I can buy the ADCs? TBH, I was hoping to get something a bit better than 8 bit.Also, what do you mean by saying that it will be hard to stick them to the FPGA board? Aren't there some standards for connection? Pardon my ignorance!Quote from: pcprogrammer on October 20, 2022, 12:09:52 pmI see. But expensive like how much? Consider that in going along that way I'll spare the money for the FPGA board...Quote from: pcprogrammer on October 20, 2022, 12:09:52 pmMaybe you can point me towards some learning resources. It's true that there are plenty of threads about such stuff here, but they are a bit over my current level of competence...Thanks!

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 05:59:30 pm
content: Quote from: 2N3055 on October 20, 2022, 12:13:38 pmAs a matter of fact, I'd like to build one precisely because they are fascinating pieces of engineering.Anyway.. It's a bit difficult to find the information I need. I'm delving into the forum, but like I said to the other user above, the discussions are a bit over my current level of knowledge.You said that the heavy lifting is done by the FPGA. Ok, I have two questions then:1. If I stick a PCIe frontend/ADC card into a desktop computer, can the computer do what the FPGA does in commercial scopes?2. Do USB scopes have a FPGA board inside??Thanks.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 06:04:14 pm
content: Quote from: Fungus on October 20, 2022, 12:35:32 pmNo I'm not in prison, but building the scope would be a wonderful way to waste my timeAnyway, about what I don't like, see that long thread of us about bode plotting on the MSO5K..By having used the AD2 and various bench scopes, I decided I definitely like the usb scopes much more. It's one of those I want to build. A whole lot of hassle removed (screen, knobs, etc...).

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 06:05:59 pm
content: Quote from: pcprogrammer on October 20, 2022, 01:17:39 pmThanks! I'll start from there!

author: alm
author_rank: Super Contributor
timestamp: October 20, 2022, 06:07:23 pm
content: Don't forget the analog front-end. You'll want a 1 MOhm in parallel with 10-25 pF or so input impedance to work with standard 10x probes, and some amplification and/or attenuation to extend the range beyond the native range of the ADC. Especially since you value low noise, which presumably means you want to look at low-level signals.You also may want some input protection so you don't blow up your expensive ADCs.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 06:09:39 pm
content: Quote from: rob77 on October 20, 2022, 12:19:10 pmThe idea started from just wanting to have a scope without the issues which bother me. But then I indeed thought that it would be interesting and fun per se. Even if it'll take years. Or a decade. I mean, I can think of worse ways to employ one's time.Have you talked about your projects here? If yes, could you point me towards the relevant threads? Thanks!

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 06:11:56 pm
content: Quote from: alm on October 20, 2022, 06:07:23 pmWell said. In the end, low noise amounts to a well-thought front end. I don't have the faintest about how to learn concocting good front ends..

author: Bud
author_rank: Super Contributor
timestamp: October 20, 2022, 06:22:20 pm
content: TI application note on a high speed front endhttps://www.ti.com/tool/TIDA-00826

author: tggzzz
author_rank: Super Contributor
timestamp: October 20, 2022, 06:50:15 pm
content: There is a fine line between tackling a project that stretches you and one which can't be completed within reasonable time and effort. Engineers ought to be able to distinguish. N.B. it is not for me to define "stretches you", "completed", "reasonable time", "reasonable effort". That's your decisionHowever, there isalsonothing wrong with trying something, finding where the pain points are, finding workarounds -and knowing what you would do better next time. Indeed, in some circumstances that can be positively beneficial, e.g. during job interviews being able todemonstratethat you are interested in the subject and in continuously improving your knowledge and judgement. Back in the 70s I built a 6800 computer (similar to an Altair 8080) from scratch. In many ways it was appalling, but I learned a hell of a lot and could discuss things with other people.I would suggest that learning when and how to use (or to avoid using) FPGAs is a useful skill, just as learning how to programme microcontrollers is useful. I would also suggest that if you are starting from scratch, then the magnitude of learning FPGAs is similar to that of learning MCUs.Have fun! Eric Laithwaite at Imperial College used to set exams where one question was easy and sufficient get you a pass mark, one was more challenging and couuld get you a good degree, and one could not be answered adequately in the time available.He expected his undergraduate engineers to be able to determine which questions to avoid. If they couldn't, they wouldn't make good engineers anyway.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 07:04:33 pm
content: Quote from: tggzzz on October 20, 2022, 06:50:15 pmI have to say I'm studying physics, not engineering. We are somewhat supposed to venture even in stuff that cannot be explored in any reasonable stretch of timeBut yours are good advices nonetheless!One step forward would be establishing if it's absolutely necessary to use a FPGA.I'm sure it'd be interesting to learn FPGAs per se, but nevertheless I need to know if one can make a functional scope with just a computer, a front end, and an ADC.

author: tautech
author_rank: Super Contributor
timestamp: October 20, 2022, 07:20:30 pm
content: Where did balnazzar go ?I think he fell in here:

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 20, 2022, 07:44:54 pm
content: A scope without a FPGA is certainly possible, but would not have a high sampling rate. Take a look at these little scopes made with a STM32103 MCU. Just 1MSa/s, but good as a basis to learn about how a scope works.Schematics of the Wave2 of jyetech can be found here.https://jyetech.com/wp-content/uploads/105-15800-00M.pdfFor higher sample rates without a FPGA you would need a more powerful processor and an external ADC. Don't have examples on this.With a FPGA there are many options like for example a zynq board you mentioned but high speed ADC modules need fancy FPGA boards with FMC connectors. It would then be easier to buy for example a Hantek DSO2C10 and make your own FPGA design and software for that. The schematics are reverse engineered by me and can be found here:https://github.com/pecostm32/Hantek_DSO2000/tree/main/SchematicsFor a system with less bandwidth and easier to build with modules I already pointed you to my Lichee Nano repository. I refer to a 2 channel 65MSa/s 12 bit ADC module there. For a scope it would need more work on a front end, which is not in my skill set, but for a starting point it is good enough.As a learning tool the FNIRSI-1013D is also fun. It has all the hardware needed to make a scope, and there is plenty of info about it in my repositories and the thread here on the forum. I'm currently trying to reverse engineer the FPGA design of it. Also as a learning projecthttps://www.eevblog.com/forum/testgear/fnirsi-1013d-100mhz-tablet-oscilloscope/https://github.com/pecostm32/FNIRSI-1013D-1014D-HackA PCIe card that is not even very fast but 16bits can be found here:https://buy.advantech.eu/Boards-Cards/Data-Acquisition-I-O-Data-Acquisition-I-O-Cards-PCI-Express-Cards/model-PCIE-1840-AE.htm?country=France&token=638018915275564395&f=AUSIt is very expensive.Hope this helps you make up your mind. Have fun with what ever you choose.

author: tggzzz
author_rank: Super Contributor
timestamp: October 20, 2022, 07:55:22 pm
content: Quote from: balnazzar on October 20, 2022, 07:04:33 pm"The art of research  the art of making difficult problems soluble by devising means of getting at them."https://www.azquotes.com/quote/777283"No scientist is admired for failing in the attempt to solve problems that lie beyond his competence. ... Good scientists study the most important problems they think they can solve. It is, after all, their professional business to solve problems, not merely to grapple with them."https://www.azquotes.com/quote/905059QuoteYou need to capture samples at a regular defined rate without missing samples. Ideally you also do a little real-time processing to identify when to start/stop capturing them, i.e. a trigger.Whether or not you need an FPGA depends on the sample rate and sample depth, and the degree to which you can/cannot rely on a computer to keep up. The latter depends on what other things the computer is doing and the guarantees about the computer instruction timing. I know of only one computer that guarantees instruction timing: the XMOS xCORE family. With all others you have to guess and test and hope that you have spotted the worst case. The guesswork and testing can be minimised by careful use of peripherals and by having the computer sitting around doing "nothing important". That is sufficient for many purposes.Where a computer cannot guarantee to keep up with the input samples all the time, you have two choices: reduce the sample rate until it can keep up, or have buffers to match the peak/mean processing rates to the fixed input rate.An FPGA has two things a computer (xCORE excepted) cannot have: guaranteed timing/latency and many independent operations occurring in parallel. The penalty is that the conceptual design and implementation technologies are completely different.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 08:05:27 pm
content: Quote from: tautech on October 20, 2022, 07:20:30 pmIt's the story of my life. I always endupdown in there.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 08:14:04 pm
content: Quote from: tggzzz on October 20, 2022, 07:55:22 pmGood information. Mhhh, so I guess the answer is "yes, USB scopes do have a FPGA inside them".Suppose we allocate a PC to do only oscilloscope related things. There will still be plenty of OS processes competing for CPU cycles. I wonder if something like this:https://en.wikipedia.org/wiki/RTLinuxcould be helpful in attaining a decent sampling rate (e.g. 1 GSa/s with sufficient depth) without missing important signal's details....

author: rob77
author_rank: Super Contributor
timestamp: October 20, 2022, 08:15:15 pm
content: Quote from: balnazzar on October 20, 2022, 07:04:33 pmit's absolutely crucial to use an FPGA. without FPGA your options are pretty limited.if you really want to go down the rabbit hole then Cyclone IV + FT602Q usb3 superspeed fifo will get you to the 100+ Msamples/s relatively cheap if you want to run the software on a computer. it's a fifo for 400Mbytes/s - that can yield 400Ms/s at 8bit. but definitely need an FPGA to run the ADC and feed the fifo, there is no microcontroller capable of such IO speeds.developing a usb connected "scope" would be the preferred way because it's much easier to write a software for a full fledged linux OS than it's for a small embeded system.and a hint for "cheap" first experiments... there is a product which exactly has the Cyclone IV + FT602Q combo inside.. it even has a unpopulated jtag header for connecting USB blaster and it costs 120 EuroOrico HVC-1080 video capture device - solder a 10pin IDC header for JTAG and you can immediately start playing with the FPGA + USB fifo and start writing software for data capture. later on you can desolder the video procesor chip from the device and use the freed up I/O pins on FPGA to interface the ADC and start capturing real data...then you can go even deeper into the rabbit hole and dive into the analog magic for the frontend...if you bailout at any point, you still can solder the image processor back, flash the original bitstream back to the cyclone and you have very low losses because you still have your hdmi capture card back

author: tautech
author_rank: Super Contributor
timestamp: October 20, 2022, 08:16:52 pm
content: Quote from: balnazzar on October 20, 2022, 08:05:27 pmThe task you plan to undertake will consume you entirely.To have a glimpse of what's in front of you study this thread by tom66 that pcprorammer linked earlier:https://www.eevblog.com/forum/testgear/a-high-performance-open-source-oscilloscope-development-log-future-ideas/Tom got a fair way through with HW but then the fun begins to get anything like replicating or bettering the feature set in a $500 DSO.Good luck.....maybe you haven't realized how complex the little SDS1104X-E you have actually is ?

author: alm
author_rank: Super Contributor
timestamp: October 20, 2022, 08:23:55 pm
content: Quote from: balnazzar on October 20, 2022, 08:14:04 pmBack in the days of DOS this was feasible using twiddling bits on the parallel port. There were a number of parallel port oscilloscopes back then, with an okay sample rate for that time. The parallel port was a very simple protocol that could easily interface with discrete logic or small micro-controllers. These days IO has gotten a lot faster, but fast IO in PCs is usually serial bulk transfers, like USB, PCI Express or SATA. To connect ADCs to it you'd need something that regularly samples the ADCs, buffers it and sends it in chunks using your desired protocol. If you want high bandwidth, then an FPGA might be a good way to accomplish that.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 08:24:55 pm
content: Quote from: tautech on October 20, 2022, 08:16:52 pmNo, indeed. But I'm starting getting an vague idea. There is a video of Eric Quinn being interviewed by Dave. He talks about how insanely difficult was to put together their first scope..

author: tggzzz
author_rank: Super Contributor
timestamp: October 20, 2022, 08:26:40 pm
content: Quote from: balnazzar on October 20, 2022, 08:14:04 pmCheap "toys" won't have an FPGA inside them; a 100kHz (say) scope could be based on an MCU alone.More complex ones, almost certainly but not necessarily: it depends on what performance you require. I suggest you have a look at the Digilent Analog Discovery and/or the Red Pitaya.QuoteI wouldn't want to use a PC for anything more than the GUI, both because of the lax RT guarantees and because the x86-64 processors have caches and TLBs and lots of other features that increase themeanprocessing performance without changing the worst case performance. And for hard real time systems the mean performance is irrelevant.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 08:27:49 pm
content: Quote from: alm on October 20, 2022, 08:23:55 pmMh, I see. I wonder how those Alazartech cards do actually work. Maybe they have a large memory buffer directly on the card, and then they send what they buffered in chunks exactly as you described...

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 08:33:21 pm
content: Quote from: tggzzz on October 20, 2022, 08:26:40 pm"The Analog Discovery 2 is built on a Spartan 6 FPGA".Ok, if even a device with 100 MSa/s and shallow memory needs an FPGA, I think the matter is solved.Thanks. If I venture into it, that will be a very-very-long-term learning project, without expecting to get my actual working scope from it.

author: rob77
author_rank: Super Contributor
timestamp: October 20, 2022, 08:33:32 pm
content: Quote from: alm on October 20, 2022, 08:23:55 pmFPGA is the only waythere is no RT OS capable of sampling with low jitter at any reasonable sample rates...If you do the sampling on the FPGA (low jitter), serialize the data, send it to the computer, then processing on the computer is absolutely not critical.. the only concern would be to have enough processing power to get reasonable waveform update rates on the screen.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 08:50:37 pm
content: Quote from: rob77 on October 20, 2022, 08:33:32 pmUnderstood. This thread aready served a useful purpose. Previously, I was convinced that a computer could virtually tackle any possible task (up to its sheer computational power).

author: alm
author_rank: Super Contributor
timestamp: October 20, 2022, 08:57:20 pm
content: Quote from: rob77 on October 20, 2022, 08:33:32 pmI was thinking you might be able to hook up an USB SuperSpeed interface IC from the likes ofFTDIto an ADC via some very simple glue logic. Especially if you could find an ADC with a parallel output.

author: rob77
author_rank: Super Contributor
timestamp: October 20, 2022, 08:58:43 pm
content: Quote from: balnazzar on October 20, 2022, 08:50:37 pmalso have a look at my suggestion with the video capture deviceusing a video usb fifo saves you a lot of time.. because the OS already has the driversusing that video fifo makes your life easy - you feed any data to the USB fifo with FPGA and on the computer side you simply just a open the corresponding "/dev/video" device and read it like a fileand you have a 400Mbyte/s data stream available to you with almost zero development

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 09:02:57 pm
content: Quote from: tggzzz on October 20, 2022, 07:55:22 pmMhh, here they are described as some sort of MCUs:https://www.xmos.ai/download/xCORE-Multicore-Microcontrollers-Overview(1.2).pdf

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 09:04:37 pm
content: Quote from: alm on October 20, 2022, 08:57:20 pmInteresting! Would you kindly provide some starting point (links, etc..)?Thanks!

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 09:08:05 pm
content: Quote from: rob77 on October 20, 2022, 08:58:43 pmFor unknown reasons, I missed your previous message, thanks for having pointed that out!You mean this device?https://www.startech.com.bd/orico-hvc-1080-hdmi-to-usb3-0-video-capture-card

author: rob77
author_rank: Super Contributor
timestamp: October 20, 2022, 09:26:52 pm
content: Quote from: balnazzar on October 20, 2022, 09:08:05 pmyes and this is what's inside

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 09:44:19 pm
content: Now that could actually be a very effective starting point...

author: tggzzz
author_rank: Super Contributor
timestamp: October 20, 2022, 09:51:18 pm
content: Quote from: rob77 on October 20, 2022, 08:33:32 pmThere is a halfway house.Sample using a low jitter clock. Put samples in a FIFO/queue. At the computers convenience, take samples from FIFO at computer's convenience. Provided the computer can take the samples at a mean rate that is higher than the sampling rate, all is well.The averaging interval for calculating the mean rate is closely tied to the depth of the FIFO.

author: rob77
author_rank: Super Contributor
timestamp: October 20, 2022, 10:12:32 pm
content: Quote from: balnazzar on October 20, 2022, 09:44:19 pmyes, good starting point to get onboard with FPGA and writing software for linux.if you will go for that capture board then obviously you have to desolder the FPGA to figure out what is connected to which io and create a io pin map (ring the traces through with continuity tester) and then reball the fpga and solder it back.i'm planing to do that once i'll have some time, but it's like that for few months alreadyi'm planing to rip out the hdmi sink and the video-processor , make a small daughter board with bus drivers(level shifting) and use it for high speed data capturing (even using the HDMI connectors).as you see on the picture i have the pin header populated on one of the boards, and can confirm it works with USB blaster and Quartus no problem, i can read and write the configuration memory through the FPGA.

author: rob77
author_rank: Super Contributor
timestamp: October 20, 2022, 10:17:18 pm
content: Quote from: tggzzz on October 20, 2022, 09:51:18 pmisn't that exactly what the FPGA + USB fifo + OS device driver combo does ?

author: tggzzz
author_rank: Super Contributor
timestamp: October 20, 2022, 11:19:49 pm
content: Quote from: rob77 on October 20, 2022, 10:17:18 pmProbably, but omit the FPGA and have a FIFO that isn't tied to a communication deviceCats? I know lots of ways to skin them

author: BillyO
author_rank: Super Contributor
timestamp: October 20, 2022, 11:52:30 pm
content: I built a scope once. Back in 1978. It was a Heathkit.The only way I'd build a 2nd one is if I found an un-built Heathkit kit. Of course that would probably cost me as much as a decent new car, but a whole lot less than a Keysight 8ch 32GHz jobbie.I wish you success. This is a bigger project than I would ever take on as a hobby.

author: rob77
author_rank: Super Contributor
timestamp: October 20, 2022, 11:58:07 pm
content: Quote from: tggzzz on October 20, 2022, 11:19:49 pmand how exactly would you connect it to the computer ?

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 20, 2022, 11:59:10 pm
content: Quote from: tggzzz on October 20, 2022, 09:51:18 pmMh. Not promising.

author: jasonRF
author_rank: Regular Contributor
timestamp: October 21, 2022, 12:36:27 am
content: Quote from: balnazzar on October 20, 2022, 08:33:21 pmYup. And as others have said, if/when it is finally working, it will almost certainly not compete with a new scope that you could buy with the money you spend on it.Going back to the beginning of the thread, I think it really is remarkable what $1000 can buy these days. Exactly what you want might not be available, but that goes along with engineering in general. Similarly, the exact parts you want for your scope project might not exist, or they may be unavailable (pretty likely these days) or too expensive for your project. You find creative ways to overcome challenges using the parts and test gear that you have access to.jason

author: gf
author_rank: Super Contributor
timestamp: October 21, 2022, 05:17:07 am
content: Quote from: pcprogrammer on October 20, 2022, 07:44:54 pmThe low-cost Hantek 6022BE uses an EZ-USB microcontroller to stream the ADC samples via USB2 to the PC. No FPGA involved. Sample rate is 48MSa/s, IIRC. Processing (incl. trigger) is done on the PC.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 21, 2022, 05:29:31 am
content: There is one thing that is overlooked in this talk about a scope without a FPGA, and that is DMA. (direct memory access) It is possible to do sustained capture with it, but to do triggering on the signal will still require the processor to do a lot of work. With microcontrollers it still would not bring the high sample rates. No idea about the speeds that can be obtained with a modern PC.The cards of the company found by you, balnazzar (https://dev.alazartech.com/en/) also uses a FPGA and has lots of memory on the card to do the data capture.As a starting point for learning take a look here:https://www.fpga4fun.com/digitalscope.htmlIt starts with the basics.Since you, balnazzar, did not comment on my last post it might be that you missed it. It provides lots of information you asked for.https://www.eevblog.com/forum/testgear/building-my-own-scope/msg4474414/#msg4474414

author: alm
author_rank: Super Contributor
timestamp: October 21, 2022, 08:58:46 am
content: There's always the possibility to do triggering in the analog domain using a fast comparator and timer. That would remove the need to do any real time calculations on the data.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 21, 2022, 09:21:57 am
content: True, but this means adding a DAC, and other logic to make it somewhat flexible to mimic like what can be done in software or a FPGA.

author: alm
author_rank: Super Contributor
timestamp: October 21, 2022, 09:31:24 am
content: Yes, absolutely. I'm not saying it's an elegant solution, but it could help towards making a somewhat usable scope while avoiding using an fpga.

author: 2N3055
author_rank: Super Contributor
timestamp: October 21, 2022, 09:46:00 am
content: Quote from: alm on October 21, 2022, 09:31:24 amBut you're missing the point.A home made scope cannot be made to be better and cheaper than many ready made scopes on market.So only reason why OP would choose to make a scope is a learning experience.And if so, why he would learn how modern digital scope is NOT made..A modern digital scope (all of them) have ADC /FPGA combination, minimum. Sometimes special ASICs to accelerate thing or provide some kind of real time capability that is too complicated or too fast for FPGA They also have digital triggers implemented inside FPGA code as a part of acquisition engine. If they are USB scopes, then they have some sort of solution (also inside of FPGA or a separate CPU) to pump data to PC. Standalone scopes in addition to ADC/FPGA have their own CPU that runs GUI/analysis. Sometimes that CPU is inside FPGA (Zynq for instance). There are few nice scopes on market based on ADC(1 or 2) and Zync.If he wants to learn sampling theory and DSP math, a sound card built in a PC and Octave (and hundreds of books) will provide lifelong fun and games..

author: tggzzz
author_rank: Super Contributor
timestamp: October 21, 2022, 09:51:22 am
content: Quote from: rob77 on October 20, 2022, 11:58:07 pmSigh. Why do people choose to omit context relevant to their point? Here's what I was replying to...Quote from: rob77 on October 20, 2022, 10:17:18 pmDon't use the "USB fifo" as part of thescope'sfunctionality.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 21, 2022, 10:01:01 am
content: Quote from: gf on October 21, 2022, 05:17:07 amIf 48 MSa/s is the best one can do without FPGA, then FPGA is necessary.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 21, 2022, 10:08:10 am
content: Quote from: pcprogrammer on October 21, 2022, 05:29:31 amThanks, quite informative. I indeed missed it, or I owuld have at least thanked you for it!Also I didn't catch that alazartech cards had a FPGA.. BAsically then, they are quasi-whole oscilloscopes, except they are directly inserted into the pcie slot rather than using usb or thunderbolt..I thought they were just analog front end plus ADCs..Once more, thanks.

author: tggzzz
author_rank: Super Contributor
timestamp: October 21, 2022, 10:11:34 am
content: Quote from: balnazzar on October 21, 2022, 10:01:01 amNot if you are only interested in audio signals(But for audio you might to be very interested in the dynamic range and linearity, for which a decent sound card could be a good "front end + ADC".)

author: gf
author_rank: Super Contributor
timestamp: October 21, 2022, 10:27:47 am
content: Quote from: balnazzar on October 21, 2022, 10:01:01 amI think 48 MSa/s was chosen due to USB2 speed limit, and due to the EZ-USB FX2 clock frequency, from which the ADC clock is directly derived as well. In the mean time there also exist EZ-USB FX3 controllers for USB3. I guess they would enable a higher rate. Yet another limit is of course the processing speed of a PC.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 21, 2022, 10:46:37 am
content: High speed with 8 or more bits per sample results in high bit rates. 1 channel at 1 GSa/s for 8 bits per sample means 8Gbps, which is more then USB3 can handle.Even for a FPGA it is fast unless paralleling is used. The ADC used in the Hantek DSO2000 series uses a multi phase clock to bring the speed down and spread it over 4 separate bytes into the FPGA. To write it into memory this is also needed. Clocks and data signals at higher rates bring a bucket load of problems that yo need to be aware of.High speed FPGA design is also tricky. I'm learning about this at the moment and it is not like just slapping some gates together and you got something running. It requires timing constraints and tweaking to get a proper design.For learning my advice is to stick to sample rates below 100Msa/s.

author: Fungus
author_rank: Super Contributor
timestamp: October 21, 2022, 11:20:42 am
content: Quote from: alm on October 21, 2022, 08:58:46 amA simple rising/falling edge trigger can probably be done on a PC in software.Modern DSOs can do far more than that though. Take a look at the trigger menu of the average 'scope these days, there's runt pulses, zones, serial data... all stuff that needs an FPGA.

author: rob77
author_rank: Super Contributor
timestamp: October 21, 2022, 09:51:06 pm
content: Quote from: tggzzz on October 21, 2022, 09:51:22 amit's pretty relevant i think.. if you propose a solution it must be something that can be implemented in real life..if your proposed solution mentions "computer will read the fifo" then please share your idea how...probably you didn't noticed that nowadays computers have only PCIe , USB, LPC , SPI, SMBUS I2C.... nothing else , have a look at the datasheets of the CPUs used in computers, for high speed it's PCIe and USB , for generic peripherals it's a superio chip connected through LPC , bios and sensors is SPI, i2c, smbus..... and it's like that for at least a decade...there is no other way to interface a computer, and only the first 2 in the list are fast enough for data capture at reasonable rates for a scope.

author: 2N3055
author_rank: Super Contributor
timestamp: October 21, 2022, 10:01:23 pm
content: Quote from: Fungus on October 21, 2022, 11:20:42 amAt what sample rate you think that can be made? How much data can be synchronously transfered to PC per second without loosing a single bit....?

author: tggzzz
author_rank: Super Contributor
timestamp: October 21, 2022, 10:24:56 pm
content: Quote from: rob77 on October 21, 2022, 09:51:06 pmI think there is a language problem here; I'm not sure what you are arguing against and for. I am guessing English isn't your first language.You wrote "the FPGA + USB fifo + OS device driver combo" which could be parsed as "the (FPGA + USB) (fifo + OS device driver) combo" or "the FPGA + (USB fifo) + (OS device driver) combo". Only the latter makes some sort of sense, so that is how I interpreted it.Now a scope (of the type being discussed) will have a signal chain consisting ofanalogue front endADCdata capture FIFO controlled by an FPGA or by other meansfirst level processing and controlcommunications mechanism to and from...control and display GUI in a computerThe communications mechanism (5) could be over USB, Ethernet, SPI, UART, or even RFC1149 (or revision RFC2549). If you are using USB or Ethernet there will be one or more FIFOs in the comms mechanisms - as you noted.But, unless you wish to grossly simplify the hardware and limit performance, the FIFO in (5) is separate to the FIFO in (2).

author: Fungus
author_rank: Super Contributor
timestamp: October 21, 2022, 10:25:06 pm
content: Quote from: 2N3055 on October 21, 2022, 10:01:23 pmIfI'mprogramming it on a multi-core 3GHz CPU with SSE instructions? Quite high...

author: rob77
author_rank: Super Contributor
timestamp: October 21, 2022, 10:39:56 pm
content: Quote from: tggzzz on October 21, 2022, 10:24:56 pmthe whole point was to grossly simply the hardware and do all processing in software on the computer... i think it was pretty obvious from my posts.... same approach as you do with SDR - "simple" HW sending IQ data to the computer and gnuradio (or whatever else) doing the heavy lifting.and regarding the interfaces, everything you listed boils down to the very interfaces the CPU has (serial through superio on LPC, MAC controller connected to PCIe for ethernet...etc...) , so to get lowest latency and highest throughput you need to use one of those interfaces the CPU has implemented directly... and that's PCIe or USB.

author: David Hess
author_rank: Super Contributor
timestamp: October 21, 2022, 11:14:55 pm
content: Quote from: balnazzar on October 20, 2022, 05:59:30 pmA PC processor has the performance to implement the decimation and triggering which the FPGA handles, but many high speed PCIe and USB digitizers cannot stream continuously at high sample rates.QuoteYes, USB scopes have an FPGA or equivalent for handling decimation and triggering.Quote from: alm on October 20, 2022, 06:07:23 pmDo not underestimate the finesse that goes into a high impedance input. For high impedance attenuators, I would consider picking up a couple of the 4-pin hybrid attenuators Tektronix used in the 1970s. Add a DPDT telecom relay and you have a switchable high impedance attenuator good to 100 or maybe 200 MHz.Input noise is dominated by the high impedance buffer, typically an FET being used as a source follower, which is the noisiest part.Quote from: balnazzar on October 20, 2022, 06:11:56 pmThe Tektronix Circuit Concepts books "Vertical Amplifier Circuits" and "Oscilloscope Probe Circuits" availablehereare a good place to start."Signal Conditioning in Oscilloscopes and the Spirit of Invention" by Steve Roach included in "The Art and Science of Analog Circuit Design" edited by Jim Williams discusses modern front end designs."Good Engineering and Fast Vertical Amplifiers" by John Addis in "Analog Circuit Design - Art, Science, Personalities" edited by Jim Williams would be useful for a discrete amplifier design.Studying various Tektronix service manuals for their solid state oscilloscopes from the 1970s to 1980s will be helpful. They include detailed theory sections describing every circuit. The Tektronix 2230 and 2232 DSOs will be particularly helpful. The 2230 implemented a sampling rate of 20 MHz with a TTL design.Quote from: pcprogrammer on October 20, 2022, 07:44:54 pmA low sampling rate sampling oscilloscope could be made for bandwidths above 1 GHz but that entails several other design disciplines and is less generally useful.QuoteLast year I figured there should be standard interface ADCs and processors to allow for a high sample rate design without an FPGA or custom logic, and there are, but they are incredibly expensive.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 22, 2022, 12:29:11 am
content: Quote from: tggzzz on October 21, 2022, 10:24:56 pm

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 22, 2022, 12:36:14 am
content: Quote from: David Hess on October 21, 2022, 11:14:55 pmThanks. You seem to be remarkably knowledgeable. Do you work in the field of oscilloscope manufacturing?(P.S. the link to Tek literature contains a typo, but removing the trailing 'url' makes it work)

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 03:03:02 am
content: Quote from: balnazzar on October 20, 2022, 11:34:09 amAnalogue ones are much much easier.With digital ones the problem is that you need to have 1 amplifier (at least for each channel) and one thing sampling it (the ADC). This is because if you had 2 and switched between them (say taking it in turns) they'd be slightly different in gain and sampling. We often don't expect channels to be exactly the same so you can get away with it but still.Say you want 1ghz bandwidth, you'd need to sample at at least 2ghz, this is where you run into problems, you can't just dump that into DRAM (you can get about ~100m/sec (100mhz) requests from DRAM, they're faster than this at sequential transfers once you've opened the page) - so you'll need to buffer there.What you need are say ~20 things able to latch the digital reading in a round-robin fashion (this might be doable on the FPGA, but getting it onto it could be tough) - then you can read each at ~100mhz which is bordering on practical.This is a demultiplexor and something the FPGA can be good at. Then you need to get this to a circular buffer in RAM. I'd also make it so you knew via software if say a "latch" hadn't been read and had to latch a new value (meaning you missed a sample)That'll be the hard bit, the rest is software or the same as analogue scopes.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 22, 2022, 05:57:32 am
content: Quote from: David Hess on October 21, 2022, 11:14:55 pmCorrect. Take equivalent time sampling, but for that to work you need a reliable fine scaled delay, or more useful for spectrum analysis a heterodyne mixer to bring your signal down in frequency. But these require a lot of additional electronics to make it work.https://en.wikipedia.org/wiki/HeterodyneQuote from: David Hess on October 21, 2022, 11:14:55 pmYou mean the FMC based systems?

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 22, 2022, 06:13:25 am
content: Quote from: py-bb on October 22, 2022, 03:03:02 amWith a cathode ray tube sure, but try making something for a LCD.Quote from: py-bb on October 22, 2022, 03:03:02 amAnd yet many scope use this to get higher sampling rates. Mostly with the ADC's integrated into a single chip. Good ones will be matched by laser trimming in the factory.Quote from: py-bb on October 22, 2022, 03:03:02 amThere are some threads on this forum with discussions about the needed sample rate. For a scope the opinions differ from 2.5 to 10 or more times for proper signal representation. Times 2 is the nyquist theorem for the ability to reconstruct a sine wave. How often is it that you are just interested in a pure sine wave when using a scope? Maybe you want to see some distortion on your signal. You need a much higher ratio to be able to see it. Or use a spectrum analyzer of course.

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 07:49:00 am
content: Quote from: pcprogrammer on October 22, 2022, 06:13:25 amWith the first thing... OK good point.As for the 2nd one, why? I am sure at some point separate ADCs becomes sensible, but when and for what? I imagine really really high frequencies because multiplexing the sample values (rather than ADCs) is easier and gives good results.But either way you've gotta demux the samples.As for 3, yes you're right that's the nyquist limit. I think we can all agree you need to go at least that high because otherwise it's not possible to recover a signal.That's the definition of it, whilst good you know that, you should have a look on wikipedia I think about the significance of it. If anyone tells you they need < 2x the bandwidth for a signal they want, they are simply wrong.Putting it at 2.5, 10, sqrt(5), pi, whatever are all above 2 - and we venture into practical constraints.In the ideal world, 2 is fine, but practice varies based on everything and you cannot give it a number of the same "mathematical rigor" as the Nyquist Limit.Finally, I picked 1 ghz because it's 1e12 hz and this would have been nice for back of the envelope calculations, it's not special.Hope this helps.Addendum: You may have heard of the Nyquist Bound- this term is used when we mean that anything with a sampling rate >= 2 x frequency we care about will do. The Nyquist Limit is the lowest sampling rate you can have and have an (idealised) chance of catching the frequency you care about.They're the same thing.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 22, 2022, 08:21:47 am
content: Not going to start a discussion about nyquist. There are plenty around here on the forum.Quote from: py-bb on October 22, 2022, 07:49:00 amWell most likely money. High speed ADC's are expensive and using two that are capable of half the speed might cost way less than the single high speed one.Take the FNIRSI-1013D and 1014D, these use two AD9288 chips. One for each channel, and this chip has 2 ADC's in it. This way they have 200MSa/s, but do need calibration to equalize the readings between the two.The Hantek DSO2000 series use a ADC08D500 chip. This is a 2 channel 500MSa/s ADC where the two ADC can be connected to the same signal inside the chip. So a single channel can do 1GSa/s. Have not looked into the software of this one, but assume it also needs some calibration.These are the ones I know of, but there will be others.Using a single ADC to sample multiple channels can of course also be done, but it lowers the sample rate instead of increasing it.For really high frequencies (> GHz) it requires a lot more knowledge to get it right with multiple ADC's, and this is not within the realm of what I know.

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 08:36:03 am
content: Quote from: pcprogrammer on October 22, 2022, 08:21:47 amIf you're going that high you need knowledge of microwave propagation... which also doesn't help OP.

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 10:06:49 am
content: Quote from: py-bb on October 22, 2022, 03:03:02 amNot true. The bandwidth and sampling rate are independent.Examples:SDR. Even the cheap dongles capture 1.5GHz waveforms, and their sampling rate is several orders of magnitude lowerTDR. My 1970s Tek 1502 displays <140ps risetimes and its sampling rate is <100kS/sScopes. One I used many decades ago is the HP54100A: 1GHz/350ps, 40MS/sX-Y plotters. In the mid 70s I saw an experimental sampling scope with >1MHz bandwidth that used an XY pen-plotter as an output device.There are many many other examples.

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 10:10:40 am
content: Quote from: pcprogrammer on October 22, 2022, 05:57:32 amDelay isn't too much of a problem: see the very simple circuits in the Tektronix 1502 TDR.Triggering from the signal is more challenging. The Tek 1502 avoids that by having an, ahem, external trigger that is generated internally

author: Fungus
author_rank: Super Contributor
timestamp: October 22, 2022, 10:12:24 am
content: Quote from: pcprogrammer on October 22, 2022, 06:13:25 amTimes 2 can reconstructanybandwidth limited signal, not just sine waves.The main problems are:a) Finding a bandwidth limited signal in real lifeandb) Using an infinitely wide filter to reconstruct it

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 10:18:27 am
content: Quote from: py-bb on October 22, 2022, 08:36:03 amNot true.Here's an example that doesn't - and can use a pen plotter as an output devicehttp://www.redrok.com/Circuits_1GHz-samplig-Oscilloscope-Front-End.pdfhttp://www.redrok.com/sampscope.htmShame that author measures time intervals in mohs (e.g. 50nS)

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 11:15:00 am
content: Quote from: tggzzz on October 22, 2022, 10:18:27 amI'm not convinced it'll be any good, trust me at ~ghz speeds things are a lot less nice.At ~4ghz digital stuff you need to zig-zag traces to avoid problems from the fibres in the circuit board. Width and bends in "traces" matter - it's really non-trivial.Also that link is analogue.If you don't believe me BTW, I encourage you to try it (seriously, love to know how you get on) PROVIDED you have some equipment to know if it's working well or not. I'm sure it'll do something! The question is it it accurately reflecting that something.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 22, 2022, 11:20:13 am
content: I'm following (or trying to follow) your discussion with the utmost interest.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 22, 2022, 11:28:20 am
content: Maybe you will find this video interesting then

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 11:40:02 am
content: Quote from: py-bb on October 22, 2022, 11:15:00 amIf you had bothered to understand the techniques in that circuit, you would see that the high frequencies are limited to averysmall part of the board. They are entirely tractable; see the old scopes I referred to earlier.Besides, zig zag traces aren't principally used to avoid "fibres in the circuit board", and there are standard ways of reducing how the weave affects the spatial variation of impedance.QuoteHere's an example of a 4GHz sampling circuit where the weave in the PCB is clearly visible (Tek 1502, from half a century ago).The only interesting point is the notch next to the CR1732 sampling diodes, used to counteract the effect of the diode's capacitance.QuoteIrrelevant.All circuits are analogue- except arguably for photon counting and femto-amp circuits (and Josephson Junction, but I don't know enough about those).You could easily add a very slow ADC and it would work unchanged. For example, you could use an Arduino's ADC if you wanted to show the result on a computer screen. Alternatively ( if you used skill and imagination to circumvent a lack of DC response) you could use a PC Sound card as an ADCQuoteThat's valid for each and every approach, therefore doesn't distinguish between techniques.

author: rob77
author_rank: Super Contributor
timestamp: October 22, 2022, 11:47:59 am
content: Quote from: tggzzz on October 22, 2022, 10:06:49 amare you trolling or are you just simply dumb ? that's a question not a statement.Quotediscuss this please wit mister Nyquist and mister Shannon , the best place for the discussion would be a class in a school.Quotewtf ? do you even know how it works ? how the heck would you sample a waveform with a sample rate several orders of magnitude lower that the sampled frequency ?the SDR fronted downmixes the signal to lower freqeucy and that low frequency is sampled. e.g. you're interested in a 10Mhz wide band @ 1Gz, then you downmix it and sample the resulting low frequency.probably you're getting seriously confused by the fact there are sampling scopes which in fact can sample higher frequency than the sampling rate, but the signal must be repeating and it works by sampling different part of the waveform each cycle.

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 12:01:31 pm
content: Quote from: rob77 on October 22, 2022, 11:47:59 amNo, it is an accurate statement, as demonstrated in the commercial examples.QuoteI don't need to.I, and others, have used it as a question for job interviewees in the form of "you have an audio signal superimposed on a 10MHz carrier. What is the minimum sampling rate you can use to recover the audio signal?" Anybody answering >10MS/s doesn't understand the fundamentals.QuoteI was using such analogue sampling techniques in 1979, based on an 1957 Bell Labs Technical Journal paper. As I've noted elsewhere, when I had time to return to the topic, I was irked that Tayloe had "got there first".I will admit to phrasing the point somewhat ambiguously, in order to make the point about the independence of sampling rate and bandwidth.QuoteAnd there you have the answer.Yourconfusion is that you haven't understood the inter-relationships between Nyquyist, signal bandwidth, bandwidth and aliasing. Or maybe you do understand them, but haven't articulated the relevance to this problem.

author: balnazzar
author_rank: Frequent Contributor
timestamp: October 22, 2022, 12:20:28 pm
content: Quote from: pcprogrammer on October 22, 2022, 11:28:20 amYou did actually read my mind. That's the scope I finally decided to buy.

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 22, 2022, 12:39:03 pm
content: Quote from: tggzzz on October 22, 2022, 10:06:49 amits funny you have a habit to get into disagreement with people and giving lecture philosophically about "in context" discussion, strawman fallacy etc (in other thread) without realizing you are the one you are lecturing about. i browse this thread quickly and nothing talk about sampling scope (which is a specialized scope), you cant bode plot with sampling scope. people talked about nyquist criteria (2.5X BW to be exact, not 2X) which is what we understand normally as what a normal scope do, and then you wandered off to suggest 1GHz BW with KSps scope, and how unimportant is trace length and propagation delay is in GHz domain. its just out of context, and even incorrect in some context... no need to further mess the already complicated subject (now i quote you fully so you have less chance to invent strawman argument on me)btw, i agree with tautech, OP is going into rabbit hole, or worse a worm or black hole. if you really want to waste your time you can dig i also created a thread like this to ask many years ago (while the spirit is high) and then i never made the first step, knowing more (or just a little bit) of what i actually dealing with... if you think you can beat the already cheap Rigol or Siglent and their in-house engineers, then imho you are delusional. lest if you want to talk about saving your pocket money. and later after that, i was thinking about the 10GSps or greater DSO segment where we dont have cheap option yet, maybe i can implement Rigol brilliant idea of interleaving 10x 1GSps ADC? but when i browsed digikey for the price, i closed the browser and never went back to the idea again. going fishing is much much better things to do for the sake of your brain and health.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 22, 2022, 12:40:40 pm
content: Quote from: Fungus on October 22, 2022, 10:12:24 amYou are correct, and I should have be more specific. When you only have two samples for a period of the signal you can only reconstruct it to a sine wave, as long as the samples are not taken on the zero crossing of course. And it is missing information about the max amplitude unless the samples are taken on the top and bottom of the wave.To reconstruct a square wave you need much more samples to be able to do it to some extend. Fourier comes into play here. But as I wrote in another post, there are enough threads discussing this.

author: Messtechniker
author_rank: Frequent Contributor
timestamp: October 22, 2022, 12:56:24 pm
content: To start with, I'd keep it simple. Like an USB controlledrelay attenuator/amplifier box ahead of a standard sound card.Once you have programmed time domain, XY, FFT, Bode and all the rest,you might go for an extended frequency response by writing your own driverhaving a 1 MHz+ sample rate for a specifically modded sound card.In an even further step you might want a sound card generator with a similar USB controlled relay/amplifier output box.So this would mostly be a software project.Feeling up to it? Even this will not be a one-man-show. Or it will take a very long time(10 yrs + ?) to implement.Just an idea.

author: Fungus
author_rank: Super Contributor
timestamp: October 22, 2022, 01:22:13 pm
content: Quote from: pcprogrammer on October 22, 2022, 12:40:40 pmReconstruction only works atlessthan Nyquist.If it's 99.99999% of Nyquist the sampler will go in and out of phase with the signal and still reconstruct correctly if the signal+filter are infinitely wide.(which they won't ever be in real life, obviously)

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 01:37:50 pm
content: Quote from: tggzzz on October 22, 2022, 11:40:02 amIn the picture you linked to a scope you see those fat copper traces - waveguides, because it had to be designed with great care to be useful.That they succeeded doesn't mean it's trivial or easy.

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 01:40:50 pm
content: Quote from: Mechatrommer on October 22, 2022, 12:39:03 pmYou think a Rigol DS1054 or the many equivalent low end scopes are "a specialised scope"? I don't think many people would agree.QuoteYes you can. It is standard on the entry-level Digilent Analog Discovery, and I believe it is an option on many other low-end scopes.With skill and imagination you can do it onanyscope, snalogue or digital, with or without digital post-processing. You might find it convenient to have a numerically controlled oscillator or voltage controlled oscillator (with log scaling), plus an Arduino's ADC, but you can do it.QuoteSo you discount commercial scopes such as the HP54110A 1GHz bandwidth, 40MS/s? That was a "normal" scope in its day, albeit top of the range.Or the Tektronix 11801 with SD-22 plugin: 12.5GHz, 200kS/s. I know people actively creating advanced electronic products using those.Your definition of "normal scope" appears to be "scopes that I think of using", which is rather limiting if you are trying to understand the minimum necessary to make a useful and usable scope.QuoteI've made no such statements, of course.I have stated that you can make the traces so short that their length is unimportant - and proved that with a photo of a commercial product.QuoteI'll leave the OP to decide what is relevant for him. It would be arrogant for me to speak for him.I too think the OP is biting off more than they can chew. I suspect he does realise that, but he is enjoying the conversation, vizQuote from: balnazzar on October 22, 2022, 11:20:13 amFrom what little I can infer about the OP, he is having fun understanding what's in a scope and the many imaginative ways you can build them. Whether he builds one is a separate issue.Having fun while pushing the boundaries of his understanding and capabilities?I like that attitude

author: 2N3055
author_rank: Super Contributor
timestamp: October 22, 2022, 01:59:27 pm
content: Quote from: tggzzz on October 22, 2022, 10:06:49 amAnd all of these are wrong statements.SDR is digital downconversion device that deliberately breaks Nyquist to make downconversion. Those are narrowband receiver devices and do not belong into discussion about scopes.Speed with which sampling scopes assemble screen representation is NOT their SAMPLE rate.Theirsample rate in relation to input signalis their equivalent sample rate (ETS, RIS or whatever), basically 1/sampling aperture of S/H circuit + a bit more. And since they are not realtime but a repetitive process, it takes a lot of time to, dot by dot, reassemble whole screen worth of waveform. And stable repetitive signal, because what you see on the screen is reassembled from thousands of separate different trigger events.And since their apparent (equivalent) sample rate is not breaking Nyquist it is possible to reconstruct signal.Most of the modern scopes designed in last 10 years don't have ETS mode at all (some do but most don't) because of very limited usability on modern signals.Could you please accept the fact that when people speak aboutsample ratethey meanrealtime sample ratenowadays..?

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 22, 2022, 02:14:55 pm
content: Quote from: tggzzz on October 22, 2022, 01:40:50 pmi'm not sure whats your problem is... Rigol DS1054 is one of the among "normal" (and cheapest) scope today. we are talking about whats "normal" today, not what is "normal" 80 years ago. or maybe you need to update your terminology...https://blogs.keysight.com/blogs/tech/bench.entry.html/2022/05/09/what_s_the_differencebetweenareal-timeandsamp-WuT8.htmli mean "normal" is the abundant of cheap "real-time" dso you can find today.Quote from: tggzzz on October 22, 2022, 01:40:50 pmyes we can with some not so straight forward tricks. please do a bit of homework first before posting, Analog Discovery (100MSps) is not a "sampling" scope.https://www.jensign.com/Discovery/bode/index.htmli know sometime during the time, "sampling" used to means generally anything that sample digitally at interval of time (including Rigol DS1054Z), when analog scope dominating the world, and ADC was the kind of luxury.. but not today. maybe this explained your confusion. if "sampling" that you understand is the better way, think why they dont do it today? opps yeah i know, some minority of people did it, reinventing the wheel minus the boat anchor weight...https://hackaday.io/project/167292-8-ghz-sampling-oscilloscopei know one guy did it enclosed nicely and sell it, but i cant find it right now. yes it has some specialized use today, we can invent some new devices out of it, but only within its limitation and context (repeatetive signals) when you need it cheap, affordable and if thats the only option available during the time, like when your stated "sampling" scopes was manufactured. today real-time 8GHz scope costs your soul, you tell me why companies still buy it? instead of cheaper sampling scope? are they fool or some other reason?Quote from: tggzzz on October 22, 2022, 01:40:50 pmso you discountShannon-Nyquist Theorem? circa 1915

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 02:15:16 pm
content: Quote from: py-bb on October 22, 2022, 01:37:50 pmNot quite. Perhaps I should have been more explicit.The scope part of the TDR is measuring the voltage as it whizzes past CR1732 sampling diode. The strip is part of the internal signal generator creating a step with a <50ps risetime.In the (expandable) picture below the signal source CR1703 (a tunnel diode) is on the bottom right. The signal travels along the strip to the BNC socket on the bottom left, and hence into the UUT (a cable). Impedance variations in the UUT cause reflections which return to the BNC socket and then whizz back past the sampling diode.The BNC socket contains a special internal shorting strap, so that if no cable is connected, the "scope" captures the signal rising as it goes past the sampling diode and falling as the reflection returns.In the picture below, the 1-div wide pulse shows the signal travelling the (72mm??) from the sampling diode to the BNC short, and back again. (It looks like the pulse could be expanded by a factor of 4 horizontally, to give better time/distance resolution).Note the 140ps risetime can also be captured on the chart recorder. No ADC, no microprocessors (1972!), and the most complex ICs are 741 class op amps, CMOS quad gates and dual flip-flops, and a CMOS 7-stage ripple counter acting as a DAC.

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 02:30:43 pm
content: Quote from: Mechatrommer on October 22, 2022, 02:14:55 pmRead more carefully. I think the DS1054 scope is a normal scope. The context you chose to omit indicates you think it isn't normal.QuoteWe clearly have different concepts of "normal" and "tricks". In addition, in what way is the AD's bode plottingnot"normal"?QuoteYes, the AD is a sampling scope. The samples are clearly visible in the displayed waveform!What exactly do you think an ADC is doing when it captures a sample?QuoteI can't be bothered to parse and attempt and understand that rant.The key point is that "sampling" is capturing and measuring something at an instant in time. The capture is always analogue, but the measurement and subsequent processing can be either digital or analogue. Sampling scopes, both digitising sampling scopes and analogue sampling scopes repeatedly sample the input voltage. Some have, but not all, have anti-aliasing filters in front of the sampler or in the digital processing subsystem.

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 02:34:17 pm
content: Quote from: tggzzz on October 22, 2022, 02:15:16 pmThis is going to come across a bit snippy but I mean it pragmatically.You're causing serious thread clutter with this.I think you think you're informing me of stuff, I think you're ... spouting stuff you've heard without really understanding (again for the spirit of brevity) and you think you're doing something.Spouting these facts does not help OP.You had a good point with the "analogue is easy" without a CRT not being easy, but the rest isn't going to help.

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 22, 2022, 02:36:45 pm
content: Quote from: tggzzz on October 22, 2022, 02:30:43 pmthere you go strawman fallacy again. i never mentioned anything about DS1054. i bet you havent read this carefully...https://blogs.keysight.com/blogs/tech/bench.entry.html/2022/05/09/what_s_the_differencebetweenareal-timeandsamp-WuT8.html

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 02:49:11 pm
content: Quote from: Mechatrommer on October 22, 2022, 02:14:55 pmThe two options are that:you don't understand those theorems as well as you think you do, orHP manufactured and sold equipment that violated those theorems. Bear in mind that I used that scope and knew the engineer that designed the digitiser.Which is more likely?BTW, here's the manual from which I took the numbers:https://www.keysight.com/us/en/assets/9018-05874/user-manuals/9018-05874.pdfTo save you the irritation of giving a false email address, here are the two key specs from p3-1 and 3-2...

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 03:03:35 pm
content: Quote from: py-bb on October 22, 2022, 02:34:17 pmThat's oneopinion. In any case, it takes two to make clutter.QuoteYou do not understand that you do not understand!I wish I could repeat a PM I received about you a couple of hours ago. I can't since it is obviously private, and therefore I cannot unfortunately justify that statement. Sorry about that. The key observation was your first post was a simple question about scope input protection, followed by your being a microwave expert. I prefer not to jump to conclusions as fast as wryly and tentatively suggested in that PM.QuoteThat's not for you to say. Or do you know what he thinks and speak for him?QuoteI have never said "analogue is easy" or anything remotely similar. Analogue is subtle and complex; that's why there aren't so many analogue engineers and products nowadays.

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 22, 2022, 03:05:20 pm
content: the problem with my wife is.. apart from wandering off topic to defend her point, is she thinks i'm a fool, even if when talking about technical topic (she's a kindergarden teacher).

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 03:13:43 pm
content: Quote from: Mechatrommer on October 22, 2022, 02:36:45 pmSigh.Go and re-read the context you snipped in order to make that (invalid) point. I never intimated you did initially mention the DS1054; I used it as an example to demonstrate the fallacy in one of your statements.No, I didn't read that blog entry in detail. I stopped at "Rick ClarkProduct Marketing Manager".

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 22, 2022, 03:36:44 pm
content: your prejudice and lack of insight caused your ignorance. what you dont realize is how many Keysight engineers and technical netizens are next to him to bash him if he write bullshit in Keysight blog. cheers.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 22, 2022, 03:44:17 pm
content: Quote from: tggzzz on October 22, 2022, 03:03:35 pmLet me do that for you@py-bb32 posts in a single day. The very first indeed being, an in my eyes, simple question about the protection of a scopes front end being the same for all the sensitivity settings.https://www.eevblog.com/forum/beginners/oscilloscope-safe-to-use-any-scale-as-long-as-not-over-max-ratings/msg4475026/#msg4475026And then you show up here as if you know all about how a scope works and that it is way easier to do in the analog domain, and then suddenly you know all about microwave technology for high frequency signals.Further more you use Afghanistan as you country flag whilst you write here that you are proud of your British power plugs:https://www.eevblog.com/forum/chat/(youtube)-american-is-impressed-by-sensible-british-mains-plug-design/msg4477015/#msg4477015.In your profile you write "Ashamed to say my real country ATM".https://www.eevblog.com/forum/profile/?area=summary;u=902560So I assume that you are either treez or Faringdon or some other troll.

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 04:41:26 pm
content: Quote from: pcprogrammer on October 22, 2022, 03:44:17 pmI asked a practical question about a very old scope that doesn't list the protections we'd expect of a modern scope & most PCB design is simulated these days and how they test/fix manufacturing duds is not something I deal with.I work very hard to know where I'm fit to comment and I do not like your tone.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 22, 2022, 04:48:01 pm
content: Quote from: py-bb on October 22, 2022, 04:41:26 pmWell that is your prerogative. As it is mine to make observations, and what I wrote is what my opinion is, based on what I have seen today.

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 04:51:02 pm
content: Quote from: pcprogrammer on October 22, 2022, 04:48:01 pmWell in my opinion you're a git,you should never mock someone for asking a question about how to operate equipment safely.That's a very bad habit to have indeed.

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 06:36:54 pm
content: Quote from: py-bb on October 22, 2022, 04:51:02 pmIf pcprogrammerhaddone that, I would agree with you.

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 06:43:44 pm
content: Quote from: tggzzz on October 22, 2022, 06:36:54 pmThanks for sharing your unique view of the world..... I guess.Hopefully now you've got that out of the way we can get back on topic.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 22, 2022, 06:57:22 pm
content: Quote from: py-bb on October 22, 2022, 04:51:02 pmAgain your prerogative, but I did not mock you. I just questioned if you are a troll.And I did this on making an observation on what you have posted here and in other threads. It is quite uncommon for a new member to go from a simple question to being a world class expert handing out advice in a single day. Most just ask a question and get their answers and ask maybe another question and that is it. Post count does not go up as fast as yours.

author: tggzzz
author_rank: Super Contributor
timestamp: October 22, 2022, 07:06:36 pm
content: Quote from: py-bb on October 22, 2022, 06:43:44 pmThere are solid grounds for stating it is not a unique view of the world.I agree that your becoming the subject of a subthread is indeed distracting.

author: py-bb
author_rank: Regular Contributor
timestamp: October 22, 2022, 07:09:33 pm
content: Quote from: tggzzz on October 22, 2022, 07:06:36 pmHey I've been trying to drop hints I'm not interested for a while.For some reason you seem to think you're worth listening to.The post I am replying to, why did you feel the need for that?All you're doing is making yourself look bad, the regulars might know you but I'm new! To me you look like this weird contrary loon arrogant enough to to think crap like that is worth posting.Take 10 minutes, think before you press enter. Otherwise I don't see what good can come of interacting with you.

author: David Hess
author_rank: Super Contributor
timestamp: October 23, 2022, 12:40:13 am
content: Quote from: balnazzar on October 22, 2022, 12:36:14 amI never have, but I have studied oscilloscope design for years, and am considering doing a similar project based on the Tektronix 2232.Quote from: py-bb on October 22, 2022, 03:03:02 amThe Tektronix 2230 and its predecessor, the 468, use a single digitizer for two channels with analog channel switching without any problems. The 2230 even weirdly supports chop or alternate mode when operating as a digital storage oscilloscope. Of course it would be silly to design a DSO this way today, and the 2232 which replaced the 2230 uses one digitizer per channel.Most DSOs even now use analog channel switching to support more than one channel per digitizer, or more than one digitizer per channel, but it is done internally as part of the ADC. This has been done for a long time to support higher sampling rates when fewer channels are in use. It is not difficult to do, but is an unneeded complication.Quote from: pcprogrammer on October 22, 2022, 05:57:32 amI was thinking in terms of a sampler and the timing circuits. Neither are a trivial exercise at GHz bandwidths and picosecond resolution.I have been looking into the requirements to design a modern "sampling DSO" based on the random sampling capability of the Tektronix 7T11. This would combine 4+ GHz sampling bandwidth with conventional operation from the user's perspective without a delay line.QuoteI do not remember if that was it, but there is a standard for high speed ADC interfacing and I did a search for ARM microcontrollers which support it. The cost of the ADC and microcontroller were much higher than the cost of a more conventional ADC and microcontroller and an FPGA to interface them.Quote from: pcprogrammer on October 22, 2022, 08:21:47 amThere are plenty of reasonably priced sampling ADCs now that are fast enough to make a useful DSO.Quote from: tggzzz on October 22, 2022, 10:10:40 amA TDR has the advantage of operating synchronously and generating its own trigger. A sequential sampling oscilloscope has two triggers, one for the external signal and one for the sampling strobe. A random sampling oscilloscope in addition has to measure positive and negative delay, and includes a rate generator.QuoteIn most cases the triggering does not need to have as high a bandwidth as the input signal. What does matter however is trigger noise which requires careful design to minimize. The required performance was easier when tunnel diodes were available, but there are some modern comparators which are good enough. What is missing now however are fast PNP transistors.

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 23, 2022, 01:17:18 pm
content: now i found the guy (apart from the Ted Yapo OSHW thread). 12GHz $300 Kickstarter was no go... official website out of stock. the BOM should be lesser than $300 in case somebody want to follow the trail, or implement the concept into slower MHz much cheaper, much fewer like maybe 200 Sa/s? i think we can push arduino to 2KSa/s so GHz frontend with arduino sampler should not be improbablejk..https://www.kickstarter.com/projects/1855991221/10-ghz-usb-oscilloscopehttp://www.fastsampling.com/https://www.eevblog.com/forum/crowd-funded-projects/10-ghz-usb-oscilloscope/if you want to get fancy $35K sequential ETS PicoTech:https://www.picotech.com/oscilloscope/9300/picoscope-9300-sampling-oscilloscopesand here recap from not a marketing manager, the Tek.. to whoever missed the bus... befriending Al Zimmerman alone will not make you right..https://w140.com/tekwiki/wiki/Sampling_oscilloscopehere quoted to get into context:Quotethats the Tek's saying, not me.not the best guy i can find explaining to prejudice, but best demonstration i can see in my top google list for those who are lazy to read texts...talk aboutCompressive (Random Time) Sensingbut link is broken..Shannon also mentioned theory of lossless reconstruction through subsampling...https://en.wikipedia.org/wiki/Nyquist%E2%80%93Shannon_sampling_theorem#Sampling_of_non-baseband_signalshttps://en.wikipedia.org/wiki/Compressed_sensingfor those who want to dig into the math and hence to the possibility of application... i can barely understand, but my ignorance doesnt make me right when bragging fallaciesfwiw..

author: David Hess
author_rank: Super Contributor
timestamp: October 23, 2022, 01:59:28 pm
content: Quote from: Mechatrommer on October 23, 2022, 01:17:18 pmAn Arduino easily has the processing power, but significant external hardware is required for the sampler, triggers, and time-to-digital conversion.QuoteAll modern sampling oscilloscopes use sequential sampling which further limits their general applicability. Past instruments which were more general purpose include the Tektronix 7T11, 7S14, and 3T2 which provided either random sampling, or in the case of the 7S14, a delay line, allowing them to sample the leading part of a signal like a conventional oscilloscope.QuoteSampling oscilloscopes require a repetitive signal, but it is possible to sample a repetitive but irregular signal.

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 23, 2022, 03:15:05 pm
content: Quote from: David Hess on October 23, 2022, 01:59:28 pmbut random sampling still needs repetitive (any shape) signal to show meaningful display. glitches, close loop control system, noises and many other areas (non-repetitive) cannot be shown correctly.

author: tautech
author_rank: Super Contributor
timestamp: October 23, 2022, 07:37:07 pm
content: OP, balnazzar, you have mail.

author: David Hess
author_rank: Super Contributor
timestamp: October 24, 2022, 03:01:46 pm
content: Quote from: Mechatrommer on October 23, 2022, 03:15:05 pmSure, and the same applies to equivalent time sampling when used by a digital storage oscilloscope. Sampling oscilloscopes can capture the same thing, but it takes longer because of their lower sample rates. I once measured the rise time of a coaxial relay type of pulse generator operating at 120 Hz. With a general purpose digital storage oscilloscope using 500 MS/s equivalent time sampling, this takes only a fraction of a second. With a random sampling oscilloscope, it took half an hour. The advantage of the sampling oscilloscope was 10+ GHz bandwidth and predictable transient response versus 100s of MHz.Glitches and the transient response of closed loop control systems can be repetitive. In many applications, including eye diagrams, a histogram is desired anyway, but histogram will not distinguish between noise and non-repetition.

author: rob77
author_rank: Super Contributor
timestamp: October 24, 2022, 03:16:51 pm
content: Quote from: David Hess on October 24, 2022, 03:01:46 pm"can be" doesn't mean that all glitches are repetitive, in wast majority of cases glitches are non repetitive.each tech has it's own use case... but if you're hunting a bug on a 40MHz SPI bus then all your sampling scopes and the 1GHz bandwith scope with 40MS/s are useless....

author: tggzzz
author_rank: Super Contributor
timestamp: October 24, 2022, 05:10:26 pm
content: Quote from: rob77 on October 24, 2022, 03:16:51 pm40MHz? Do you mean 40Mb/s? A 100MHz scope (say) with 1GS/s (or 10GS/s for that matter!) would be hard put to spot signal integrity issues or create a useful eye diagram.As you say, each tool has its own use cases. That means it is unwise to make global statements without reference to use cases or preconditions for the statement's validity.

author: rob77
author_rank: Super Contributor
timestamp: October 24, 2022, 05:47:36 pm
content: Quote from: tggzzz on October 24, 2022, 05:10:26 pmi meant 40MHz because it's 40MHz... it's pretty common to specify the SPI speed by it's clock frequency.Quoteyour sampling scope would not even catch the runt pulse, and your 1GHz bandwidth 40MS/s scope you love so much would not even notice half of the data... so what to use ? Mr. Tggzzz with a sharp pencil and a paper roll will do the trick i guess... while everyone else is happily using the 1GS/s scopes which are in fact not usable because the almighty omnipresent and omnipotent Mr. Tggzzz said soQuotethat's exactly what You were doing in this threadpeace for everyone ! i'm signing off

author: David Hess
author_rank: Super Contributor
timestamp: October 24, 2022, 06:19:17 pm
content: Quote from: rob77 on October 24, 2022, 05:47:36 pmBoth a sampling oscilloscope and a 40 MS/s digital storage oscilloscope would capture a runt pulse eventually, but neither could decode the data. Actually that is not quite accurate; some older DSOs supported synchronous sampling so a 40 MS/s DSO could decode 40 MHz SPI if provided with the clock.But it does come down to using the right tool for the job. The subject of sampling oscilloscopes came up in connection with what could be done with Arduino class hardware. Such would be useful to very accurately characterize the communications channel of an SPI interface, but not for decoding it. Most often I use my sampling oscilloscope to verify the transient response of other oscilloscopes.

author: rob77
author_rank: Super Contributor
timestamp: October 24, 2022, 06:35:04 pm
content: Quote from: David Hess on October 24, 2022, 06:19:17 pmsynchronous sampling ... isn't that called logic analyzer ?but anyways... sampling scope or a 40MS/s scope (be it whatever GHz bandwidth) is not the right tool in that case, we can agree on that.and if we steer back to the topic of the thread , then neither of those is a good candidate for a DIY build as as learning experience.

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 24, 2022, 08:55:03 pm
content: Quote from: David Hess on October 24, 2022, 06:19:17 pmno, it came up much earlier when someone broke the box proposing that we dont need nyquist minimum sampling criterion (for real-time sampling) to build an dso. since there is no objection from OP so far, so lets discuss and expand it with current reinvention into tiny and cheaper unit linked earlier. known guy using sampling (equivalent) scope here is Leo Bodnar to verify his 40ps rise time pulser device which i bought one.

author: tggzzz
author_rank: Super Contributor
timestamp: October 24, 2022, 09:06:53 pm
content: Quote from: Mechatrommer on October 24, 2022, 08:55:03 pmI haven't seen any claim to the effect that Nyquist can be circumvented.I have seen some people fail to understand the definition of bandwidth of a signal in the context of the Nyquist criterion. And then either go on to either deny certain types of equipment work successfully, or change their statement without acknowledging the change.

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 24, 2022, 09:13:42 pm
content: because generally when a person want to build a diy dso implicitly means the real-time one. a person will come with building a "sampling" scope in the topic when he knows what he is talking about. and nobody will recommend newbies asking about buying a new scope to buy a "sampling" scope.

author: tggzzz
author_rank: Super Contributor
timestamp: October 24, 2022, 10:53:46 pm
content: Quote from: Mechatrommer on October 24, 2022, 09:13:42 pmEr, newbies areroutinelyrecommended to buy a sampling scope.You, at least I think it was you, previously ignored the point that all modern scopes (e.g. the Rigol DS1054) tale samples of the input signal. You can even look and see the individual samples on the display, presuming you can navigate the menu system to find the right config parameter.

author: rob77
author_rank: Super Contributor
timestamp: October 24, 2022, 11:32:58 pm
content: Quote from: tggzzz on October 24, 2022, 10:53:46 pmjust stop it , seriously... twisting everyone's words and spreading bullcrap....now you suggest that every DSO is a sampling scope because they take samples ?it's you who spreads half truth statements and derails the discussion in this thread.it was you who stated sample rate and bandwidth are independent without context , which is half trueit was you who stated that cheap sdr dongles are sampling 2GHz... that's a misinformation... those have have a tuner outputting a much lower IF and that IF is sampled...it was you who suggested to delete a FPGA and do discrete control for ADC and let the computer take data on it's convenience...when i asked you how exactly you would implement your "idea".. you just mumbled some generic stuff and steered away...you might be a knowledgeable expert but that doesn't mean you can't be an trolling a-hole at the same time

author: tggzzz
author_rank: Super Contributor
timestamp: October 25, 2022, 12:38:43 am
content: Quote from: rob77 on October 24, 2022, 11:32:58 pmYou do realise how stupid that sentence is, don't you?Could you please point us towards a DSO thatdoesn'tsample the inputs?QuoteThey are independent, in theory and in practical instruments and products that you can go out and buy. I've given examples.QuoteThe "tuner" (as you call it) is a mixer andthatis doing the sampling.That'spreciselyhow the Tayloe/PolyPhase mixer in SDR dongles work!.The output of the Tayloe/PolyPhase mixer is then sampled (and digitised) at a much lower rate, usually a few MHz.You appear to be confusing the sampling in the mixer with the digitisation sampling rate.FFI you can enlighten yourself with the info in this thread:https://eevblog.com/forum/rf-microwave/polyphase-or-n-path-mixer/Be warned that it isn't easy reading, and many people find it is counter-intuitive. Alternatively the "ARRL Handbook for radio communications 2014" has a brief description and a practical circuit in section 10. I imagine it is also in other ARRL Handbooks.QuoteWell, I certainly haven't got time to (poorly) explain the basic theory here; a textbook will do a much better job.As for designing an implementation, I doubt the OP wants that. If he did then I would discuss the commercial terms.QuoteCan I suggest your being a little less sure that you know and understand the theory and practice.

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 25, 2022, 01:19:23 am
content: Quote from: rob77 on October 24, 2022, 11:32:58 pmi know the problem now. he is a literalist and want to stick with terminology when it was first appeared some 80 years ago. let the old man give his point of view, we only need to know his dictionary to come to an agreement.

author: David Hess
author_rank: Super Contributor
timestamp: October 25, 2022, 07:20:09 am
content: Quote from: rob77 on October 24, 2022, 06:35:04 pmLogic analyzers can operate synchronously or asynchronously.Quote from: tggzzz on October 24, 2022, 10:53:46 pmDSO stands for digital storage oscilloscope distinguishing it from digital sampling oscilloscope. The later term was almost never used, but does refer to a specific type of instrument which is not a DSO.Nothing requires a digital storage oscilloscope, or any ADC or digitizer, to use sampling, and when they do use sampling, it is *not* the same type of sampling that a sampling oscilloscope uses. Datasheets tend to no longer distinguish them, but ADCs are available in sampling and non-sampling varieties. Going back to the beginning of DSO evolution, the Tektronix 468, 2230, and 2232 all use non-sampling ADCs, however the 2230 included a discrete sampling unit before its 20 MHz flash ADC, and the 2232 included integrated samplers before each of its 100 MS/s flash ADCs. None of these worked the same way as the sampler does inside of a sampling oscilloscope. These were digital storage oscilloscopes.The sampler in a sampling oscilloscope operates with a strobe which is *shorter*, often a lot shorter, than the acquisition time needed to charge the storage element. This means that either the storage element must be reset between samples or the output is based on both the old and new value, which is where sampling gain come into play. By requiring only a fraction of the charge to be transferred, the "sampler" has gain which can be applied to increase its bandwidth. (1) (2)The distinguishing feature of a sampling oscilloscope is that sampling occurs first in the signal chain. Gain is applied after sampling in the analog domain. This means that bandwidth is determined entirely by the the sampling strobe width, which also produces a non-linear frequency response, so the 0.35 rule does not apply. One advantage of this besides predictable frequency response, is instant overload recovery. Overload never gets past the sampler so nothing needs to recover.(1) Nobody is saying how modern integrated ADCs do their sampling for high bandwidth. An internal 50 ohm termination results in a 25 ohm source impedance to charge the sampling storage element which sure doesn't seem like enough for the bandwidth they achieve.(2) I am describing the sampler needed for random sampling which is the more general case. The sampler in a sequential sampling oscilloscope can operate with a gain of 1 by repetitively sampling the same point of a waveform.

author: David Hess
author_rank: Super Contributor
timestamp: October 25, 2022, 07:24:39 am
content: Quote from: tggzzz on October 25, 2022, 12:38:43 amThe Tektronix 468 does not use sampling. Not all high speed ADCs use sampling.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 25, 2022, 08:08:57 am
content: So the distinction basically is that sampling means charging a capacitor to the analog voltage at the input and not the conversion to digital to make a digital sample.So some of the scopes discussed here do not turn it into a digital value, and just use the analog voltage stored in capacitors to show things on the display. Where as modern digital scopes hold the analog sample while the analog to digital converter turns it into a digital value which is referred to as a sample.Hence the assumption that a DSO uses sampling.Very confusing unless you know the history of the technology.And now the question is how this is done in very high speed ADC's because the charging of such a capacitor for taking the sample is possibly to slow to do this. For this I don't know the answer.Is this a correct recap?

author: tautech
author_rank: Super Contributor
timestamp: October 25, 2022, 08:12:12 am
content: Quote from: pcprogrammer on October 25, 2022, 08:08:57 amOf course they do. Why else would their sampling capability be listed in every datasheet in GSa/s ?

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 25, 2022, 08:19:14 am
content: Quote from: tautech on October 25, 2022, 08:12:12 amRead David his post.The way I read it, is that according to him sampling is charging a capacitor with an analog value, not the turning it into a digital value. It is semantics.

author: tautech
author_rank: Super Contributor
timestamp: October 25, 2022, 08:34:53 am
content: Quote from: pcprogrammer on October 25, 2022, 08:19:14 amI did also Mech's, rob77's and tggzzz's earlier all with some amusement.But you just can't get away from facts, a DSO samples.....fast !

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 25, 2022, 08:42:32 am
content: But how? Like David wrote the charging of the capacitor might be to slow when it comes to GHz signals.Looking at analog to digital conversion it depends on the used technology if there needs to be a sample and hold circuit before the analog to digital converter. With successive-approximation the input needs to be stable during the conversion. There are several types and the question is which does not need a sample and hold circuit.https://dewesoft.com/daq/types-of-adc-converters

author: tautech
author_rank: Super Contributor
timestamp: October 25, 2022, 08:48:53 am
content: Quote from: pcprogrammer on October 25, 2022, 08:42:32 amDo you think the sampling dots in a DSO in Dot mode are just invented ?

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 25, 2022, 08:56:27 am
content: Quote from: tautech on October 25, 2022, 08:48:53 amThat is not the point. Yes a DSO uses digital values that represent the signal. And we call these samples. But what part ofsemanticsdon't you get?David states that sampling is the act of capturing an analog value in a capacitor and not the converting it into a digital value.And what he, and me too, wonders about how this works for a high speed ADC. Does it use asampleand hold circuit or not.

author: gf
author_rank: Super Contributor
timestamp: October 25, 2022, 09:00:03 am
content: Quote from: pcprogrammer on October 25, 2022, 08:56:27 amVirtualy any ADC does. Continuous-time sigma-delta ADCs are the only exception i'm aware of.

author: tggzzz
author_rank: Super Contributor
timestamp: October 25, 2022, 09:14:03 am
content: Quote from: David Hess on October 25, 2022, 07:20:09 amThe key phrase there is "it is *not* the same type of sampling".I entirely agree that - to put it overly simply - one type of sampling captures the average voltageduringa period, and another captures the average voltage atan instant ina period. The two types' very different aperture times lead to differing characteristics, advantages and disadvantages.Nonetheless they do both providerepresentations of the input voltage at discrete time intervals- and that is the key distinguishing feature of sampling vs analogue processing.Classic examples of radically different aperture times found in sampling scopes are a diode ring (aperture time << sampling interval) and capacitor in a CCD (aperture time = sampling interval).

author: tggzzz
author_rank: Super Contributor
timestamp: October 25, 2022, 09:19:50 am
content: Quote from: tautech on October 25, 2022, 08:34:53 amNot the old CCD-based Tek scopes! If you had a 1s sweep and 1000 capacitors in the CCD, then each capacitor contained the average voltage in a 1ms interval. A 1MHz oscillation would be invisible - and that was a problem.More modern ADCs have a constant sampling rate even at slow sweep speeds, and that is the reason they can have "peak detect" modes which can show the presence of a 1MHz oscillation as a "noise" band.

author: tggzzz
author_rank: Super Contributor
timestamp: October 25, 2022, 09:25:06 am
content: Quote from: pcprogrammer on October 25, 2022, 08:08:57 amSampling means representing a signal at discrete intervals of time.Some scopes simply display those discrete representations.Some scopes digitise the representations, then store and digitally process them before displaying them.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 25, 2022, 09:25:53 am
content: Quote from: tautech on October 25, 2022, 08:48:53 amActually the original FNIRSI-1013D does invent (calculates) them when the input is above 44MHz

author: tggzzz
author_rank: Super Contributor
timestamp: October 25, 2022, 09:28:46 am
content: Quote from: gf on October 25, 2022, 09:00:03 amAnd they also produce samples, of course.I have an ADC that produces one sample every 50 seconds (a Solartron 7081). If the signal isn't constant within a sampling period then the output is the average of the input over that period.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 25, 2022, 09:35:20 am
content: Quote from: tggzzz on October 25, 2022, 09:25:06 amIn this context yes. Sampling has many meanings. You can sample food or drinks, or take a sample of something you send to the printers to see if it matches the quality you require.

author: Mechatrommer
author_rank: Super Contributor
timestamp: October 25, 2022, 09:35:55 am
content: Quote from: tautech on October 25, 2022, 08:34:53 amto be pedantic, my tongue can sample every food in restaurant and later pick which one i like, so i have a "sampling" tongue. a doctor will sample blood from various people to know where covid originated, so we have sampling doctor etc etc... albeit links are provided earlier from Tektronix and Keysight, some people still failed to read they generalized the term "sampling oscilloscope" as either 2 classes of equivalent or random sampling (or mix) where BW>>sampling rate.. and the other larger class is what we know "digital storage scope" (heck who are so pedantic to type all those?) or DSO as general purpose scope where sampling rate > 2 x BW. even analog scope will sample something into the CRT, so will it make it a "sampling scope"? its semantic of the same thing but different term or vice versa, some want to narrow them into classes and some still want to generalized for all classes as one. so looking at the topic... lets be more pedantic...

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 25, 2022, 09:41:25 am
content: Quote from: gf on October 25, 2022, 09:00:03 amA sigma delta converter is in itself a kind of sample and hold device. It keeps track of the input signal and checks if it goes up or down on the next clock.A flash ADC might not need a sample and hold because it uses many comparetors to make up the output bits, so clocking just the outputs might do well.

author: tggzzz
author_rank: Super Contributor
timestamp: October 25, 2022, 09:42:08 am
content: Quote from: pcprogrammer on October 25, 2022, 08:56:27 amThere are many many types of ADC.One type is a flash converter. An 8 bit flash converter contains 256 analogue comparators, each of which compares the input voltage with one voltage somewhere "along2 a 256 resistor potential divider. The output of the 256 "one-bit ADCs" is converted to an 8-bit number by combinatorial logic. That combinatorial output will continue to change while the input is changing. A separate 8-bit latch is then used to capture the output at a suitable instant, the sampling instant.A variant of that is to have 256 latches, one for each of the 265 1-bit ADCs. Subsequent processing reduces the 256 digtial signals to an 8-bit number.EDIT: I see our replies crossed in the æther!

author: tggzzz
author_rank: Super Contributor
timestamp: October 25, 2022, 09:43:22 am
content: Quote from: pcprogrammer on October 25, 2022, 09:41:25 amIt can be analysed as a dithered 1-bit ADC with subsequent digital signal processing.

author: tautech
author_rank: Super Contributor
timestamp: October 25, 2022, 10:07:52 am
content: Quote from: pcprogrammer on October 25, 2022, 09:25:53 amThey haven't got that to themselves. Back in 2010 a member reported the early Rigol's doing similar things.

author: gf
author_rank: Super Contributor
timestamp: October 25, 2022, 10:21:21 am
content: Quote from: pcprogrammer on October 25, 2022, 09:41:25 amIdeally yes, but In practice a proper sample-and-hold usually enhances the dynamic performance because of the inevitable timing mismatches between comparators (-> close the S&H aperture, let the comparators and priority encoder settle, and then latch the digital output).

author: David Hess
author_rank: Super Contributor
timestamp: October 25, 2022, 04:24:09 pm
content: Quote from: pcprogrammer on October 25, 2022, 08:08:57 amIt does not have to be a capacitor. Fast samplers can use a transmission line in place of a capacitor, and atraveling wave gate samplerhas no extra storage element. There are some old designs which use an inductor as the storage element but I do not think these were ever used for digitizers.QuoteI think of it as three difference classes of oscilloscope:1. Some very old DSOs (digital storage oscilloscopes) used non-sampling ADCs. This has performance disadvantages but can work at lower bandwidth. High speed track-and-holds and samplers are not trivial to design or implement, and for a long time they remained separate from ADCs.2. DSOs (digital storage oscilloscopes) generally use sampling ADCs of one variety or another. In the past the sampler was a separate stage preceding a non-sampling ADC. The frequency response of the sampler has the standard single pole -6dB per octave roll-off based on its time constant. Most or all of these are really using a track-and-hold and not a sampler, which adds to the confusion.3. Analog and digital sampling oscilloscopes place the sampler at the first stage of the input signal chain and use a sampling strobe width much shorter than the time constant of the sampler. This produces a non-linear frequency response based only on the sampling strobe width as shown below. RF sampling voltmeters also work this way.QuoteI do not know how they do this, especially since these are pipelined subranging ADCs which use charge redistribution. Maybe the sampling capacitance really is that small?Quote from: tggzzz on October 25, 2022, 09:14:03 amWhen the sampling gate width is much smaller than the time constant, like in a sampling oscilloscope, then the average voltage is captured. The sampler in a digital storage oscilloscope does *not* capture the average and operates as a track-and-hold with the bandwidth determined by its time constant.QuoteIt is a distinguishing feature between sampled data systems and continuous time systems. Sampling works just fine with analog processing and analog sampling oscilloscopes exist. The discussion here is about two different types of sampling which produce very different results and the two different types of oscilloscopes which make use of them.Quote from: gf on October 25, 2022, 10:21:21 amSome flash converters were better than others at handling dynamic inputs, and adding a sampler could improve the bandwidth tremendously of any ADC.The Tektronix 468 used the TRW TDC1007 20 MS/s flash converter which was advertised to *not* require a sample and hold amplifier up to 7 MHz, at least according to the datasheet. The Tektronix specifications say 10 MHz of useful storage bandwidth, but that seems to be based on the Nyquist criteria. The 468 implements jitter correction but not equivalent time sampling.The Tektronix 2230 which followed the 468 used a Sony CX20052A 20 MS/s sub-ranging converter which *must* be used with external sampling in a dynamic application. Sony had a companion track-and-hold but Tektronix implemented their own higher bandwidth discrete solution. The Sony datasheet does not say what the input bandwidth of their ADC was, which might be considered a comment saying that it was abysmal.

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 26, 2022, 08:48:16 am
content: The talk about ADC's made me look at the datasheets again, of some that are used in scopes I have here and now I get why they show a delay in time on samples taken and output on the digital bus.They use pipe lined architectures to make the high speed and in the mean time reduce on power used. The AD9288 shows a track and hold part on the input, so it does sample the input before doing a conversion. This one is not that high a speed. 100MSa/s at max.The ADC08D500 is much faster and mentions a pipeline delay of 13 clocks. The block diagram shows a sample and hold part on the input, which is more or less the same as the track and hold.Interesting stuff