FPGA recommendation for 80 MHz feedforward control in quantum optics - Page 1
Forum section: electronics / general

author: Moritz
author_rank: Newbie
timestamp: May 26, 2025, 01:20:09 pm
content: Hello everyone,I am currently working on a quantum optics experiment and need to build a feedforward system using an FPGA. Since I have no prior experience with FPGAs, I would really appreciate your help with choosing suitable hardware and understanding the basic setup.Experiment:- I am using a pulsed laser with a repetition rate of 80 MHz, meaning a pulse every 12.5 ns. Through parametric down-conversion, each pulse has a certain probability of producing a photon pair. While the physical process is not central here, the important part is that each pulse can result in either a photon pair or nothing.- After generation, the photon pair is split. One of the photons is sent to a single-photon detector with a dead time of around 10 ns, which allows me to detect individual photons at the used repetition rate. The other photon is delayed so it can be manipulated later based on the detection result.What the feedforward system should do:- I want to observe a fixed time window of 100 laser pulses (i.e. 1250 ns).- During this time, I want to record which of the 100 pulses resulted in a detection event – essentially building a 100-bit binary pattern (1 = photon detected, 0 = no detection).- This pattern should then be compared against predefined patterns.- If a matching pattern is found, the FPGA should output a control signal to an electro-optic modulator (EOM) to switch its state.- The switching must happen between pulses, so I assume I will need to double the clock frequency to 160 MHz (or more), enabling decisions to be made within the 12.5 ns window.Technical requirements:The FPGA must ...- Handle external clock input (from the laser system)- Output a fast TTL or differential signal to the EOM- All signal lines – detector input, clock input, and modulator output should use differential SMA connectors.What I need help with:1. Which FPGA board would be a good fit for this task?2. Do boards exist that come with differential SMA out of the box, or would I need additional breakout boards or soldering?3. What development tools and languages (e.g. Verilog, VHDL, Vivado, etc.) are suitable for implementing this type of timing-critical logic?Thanks a lot in advance for any suggestions. Any advice regarding hardware selection, clocking setup, or general FPGA programming would be very helpful.Best regards,Moritz

author: dietert1
author_rank: Super Contributor
timestamp: May 26, 2025, 03:45:35 pm
content: A web search for "Artix SMA" found the "Xilinx AC701 Evaluation Board". It has many SMA pairs, yet is somewhat expensive. For learning i'd recommend a cheap Artix board (maybe € 150 to 200 including USB JTAG). Then you need a little bit of soldering to attach your physics package. For development you use the free Xilinx Vivado IDE.For a beginner it can take a year or so to learn all the necessary things (like Artix hardware, IDE, VHDL, simulation, download and test) and finally arrive at the application you defined. If you dive into FPGA design, it's easy to get lost.Don't forget your physics!Regards, Dieter

author: pcprogrammer
author_rank: Super Contributor
timestamp: May 26, 2025, 04:10:52 pm
content: Sounds like a very interesting project. 80MHz and even 160MHz is not that problematic anymore with modern FPGA's. You can probably get it done with a Sipeed Tang Primer 20K board, but you have to add the differential interfacing with SMA connectors yourself.https://www.aliexpress.com/item/1005007291242545.htmlhttps://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.htmlTo create configurations for the Gowin FPGA you need to get the Gowin IDE, which is free, but requires registration to get a license. No big deal and can be done on their website.The choice of development language depends on what you favor. Verilog has similarities to C syntax and style. VHDL is different but below the bottom line both give the same possibilities for describing the hardware setup one wants. Many tutorials can be found on the web.As an example,https://www.asic-world.com/verilog/veritut.htmlis a site for learning Verilog.To have the switching happen in between the pulses it is possible to trigger such an even on the negative clock edge, where the pulse itself is given on the positive clock edge. This way the clock can stay at 80MHz.The amount of logic needed depends on the length of the pattern matching and the number of patterns to match against. Clever tricks can be used to only compare a single bit at every clock and keep track of matches to any of the patterns.The choice of FPGA depends on how much logic and it's speed, so best to first figure this out with the use of simulation. There is a free version of modelsim that one can use for this.https://www.intel.com/content/www/us/en/software-kit/750368/modelsim-intel-fpgas-standard-edition-software-version-18-1.htmlOnce you have some insights in the amount of logic cells, dsp slices, memory cells, etc. are needed a matching FPGA can be looked for. There are lots of manufacturers to choose a FPGA from, like Xilinx/AMD, Altera/Intel, Lattice, Gowin, Anlogic, Renesas,...For the interfacing to the other parts of the system, you have to first get the specifications of the interface that are in it. Signal voltage levels, timing, and what more can be thought of.Feel free to ask for help on that here on the forum, but be specific and prepared to answer questions.

author: BrianHG
author_rank: Super Contributor
timestamp: May 26, 2025, 06:30:25 pm
content: Quote from: pcprogrammer on May 26, 2025, 04:10:52 pmUpgrade your link to Intel's latest free version of modelsim:https://www.intel.com/content/www/us/en/software-kit/750666/modelsim-intel-fpgas-standard-edition-software-version-20-1-1.html

author: iMo
author_rank: Super Contributor
timestamp: May 26, 2025, 06:35:08 pm
content: I would go with Xilinx only for that kind of exercise. Any even old kits may help you straight with your reqs. As an example is the vintage ML-605 (I've been playing here) - a beefy Virtex6 easily doable under ISE14.7, has 2 connectors with zillion differential pairs, with FPGA Mezzanine Connectors which certainly exist with SMA connectors too. Your university or company should provide you with such an evaluation kit. Focus yourself on physics (as dietert1 said), messing with high speed FPGA hw development is difficult. To design your system in verilog on such a board cannot be more than a couple of days (when all hw is handy).

author: BrianHG
author_rank: Super Contributor
timestamp: May 26, 2025, 06:44:09 pm
content: Quote from: iMo on May 26, 2025, 06:35:08 pmYou got that right. Even with my experience, it still took me a few months to make my home-made DDR3 controller and get it efficient enough to have the core clock compile to 400MHz with 800mtps data rate.Though, I was breaking the official speed limit of an Intel FPGA software based DDR3 controller by a full 100MHz. Still, learning how to setup the PLL and output/sample window timing for the DDR and differential IO the ram chips needed with cross-clock domain transitions took time to do it right.Unless all your high speed differential IO port runs at 0 degrees from your system clock and doesn't need real-time adaptive system tuning, you will need to learn everything about your FPGA's PLLs, DLLs, and differential transceiver's capabilities.

author: glenenglish
author_rank: Frequent Contributor
timestamp: May 26, 2025, 10:52:55 pm
content: mmmmWhat's your budget , are you a student or a commercial organisation ?What is the permitted duration of this project ?What are the interfaces you have to the sensors - are these interfaces conditioned ? Tell us about what the sensor interfaces are.This sounds like a fairly straightfroward job - do you have someone you can work with that can program in HDL/has FPGA experience ? or is this some sort of undergraduate thesis that you need to do all yourself ?---glenAMD-Xilinx Factory Alliance Partner. RF/DSP/SDR

author: dietert1
author_rank: Super Contributor
timestamp: May 27, 2025, 12:10:33 am
content: We don't know anything about the spectral purity of the external clock, so additional circuits may be necessary if the hardware PLL doesn't lock as it is.Also we don't know the dead time between those 100x cycles. From the OP it sounds like there is none, which means parallel recognition of several 100 bit patterns in a fraction of a 12.5 nsec cycle. It helps for the timing that the bits are coming in as serial data.Probably the solution needs kind of a host interface to setup/modify the test patterns. So one needs to learn using predefined IP like UART, bus systems and other components. It won't be the single source file learning project that beginners do. And the current specs like 80 MHz, 100 bit pattern length may change during the project. So one needs to learn how to parametrize the component interfaces.I don't see how a beginner would get all this within some weeks or months.Regards, Dieter

author: Smokey
author_rank: Super Contributor
timestamp: May 27, 2025, 12:37:44 am
content: This sort of question always puzzles me.Assuming this is a real thing and this dude actually is on his way to having the rest of the system working as he described, how is there not someone on that team or at that organization which would be capable of doing that work or at a minimum answering all the questions posed.Lets say it's a university research project. Great. There is probably an EE department with plenty of qualified people right down the hall.Lets say it's a private company doing some commercial work. Great. It sounds like they already have spent a bunch of time and money getting to this point. Tell the guy they hired to do this part of the project that it's his turn to make stuff (or go hire that guy fast!).Lets say it's some dude in his basement who's SUPER EXCITED ABOUT QUANTUM OPTICS!!!!1111 hah. sure. and I'm still building a mars rover for mars.Assuming you area actually trying to get a project done, in none of those situations should your best resource be a bunch of dudes on the internet. Especially if you are a company. Time to market is a real thing. Having some poor laser physicist with no EE experience learn how to spec, research, implement, debug, and deploy an FPGA project that's critical to the success of your thing is sort of crazy.So ya. The project sounds killer, but I don't get this kind of question.

author: Someone
author_rank: Super Contributor
timestamp: May 27, 2025, 02:04:52 am
content: Quote from: Smokey on May 27, 2025, 12:37:44 amSounds like you haven't worked in a university environment in the last 20 years. Generally groups are ridiculously stingy about their budgets and what should be obvious collaborations are ignored as it wont tick off their metrics. Once upon a time universities just did all this as normal collaboration and there were people employed to float around with their expertise but with the commercialisation of universities all work has become tied to specific funding and people.The dominant driver is senior academics throw graduates (cheap labour) at the "work" bit andassumesay it's their job to learn whatever is required, often to reproduce some existing published method with some new slight variation/extension. Comes up quite frequently on this forum: "how to do this incredibly specific thing which I've been told to do" vs people here who know how to do it "oh thats actually a career specialisation in its self, in a field already outside your (groups) area of expertise".Industry would hire in a contractor to fill the gap, but universities tend to be of that weird scale of too many layers of management so that contracts are big end of town only and the ability of work units to contract out (even within the university) are at minimum hiring a position for 6-12 months, which needs funding sources and 6-12 months of lead time. Instead some captive employee/student is pushed to spend 3-6 months of their time on a tangent trying to learn enough to get the result... which generally ends in failure as you predict:Quote from: Smokey on May 27, 2025, 12:37:44 amI get the question and it comes from things related to Dunning-Kruger effect and failing to consider that other fields have significant skill and knowledge behind them, most people have come across a manager who with zero knowledge of the work says "how hard can it be?" or the excellent example of farming: if you were dropped onto a farm devoid of people could you operate it? its just plants and animals..... but I wouldn't be confident I could drive their tractor (despite having driven tractors before) or know their particular cycles/seasons.This is made worse when academic publishing will put a complex system such as the OP is describing as a sentence or two in the (other field) journal article, making it seem like a triviality from their point of view, like buying some butter for a cooking recipe. When in fact there is probably a complete electronics journal article of content on the electronics widget in which the optical/physical parts would have been equally downplayed as the "the Lennon/Sambridge conduit was integrated with quantum detectors to provide the stimulus"* as if that is something which is easy to produce despite it being some bespoke assembly using difficult technologies such as cryo or experimental materials (which an electronics engineer could equally fail to realise is hard).It is frustrating to see this sort of thing come up regularly as the most likely result is failure. Any success that is reliant on farming the internet for help only cements the position further, "no need to hire technical specialists as those semi skilled people ended up doing it" while not realising that it took longer and was more expensive than getting in a specialist in the first place. If that becomes a one way flow of effort (as seen by some posters on this forum) and their desired result is achieved, why ever hire any specialist? Then some of us are out of a job.*entirely fictitious

author: iMo
author_rank: Super Contributor
timestamp: May 27, 2025, 08:36:48 am
content: A recommendation in 10secs..PS: out of my curiosity I shoot the OP questions (when formulated well) into AI to see the response from time to time..

author: dietert1
author_rank: Super Contributor
timestamp: May 27, 2025, 09:50:03 am
content: Yes, in this case AI is your friend. A pretty reasonable first result, especially the Opal Kelly recommendation and the final remarks about where it needs more work.Which AI did you try?

author: iMo
author_rank: Super Contributor
timestamp: May 27, 2025, 06:39:35 pm
content: Chatgpt free as mentioned in that text..PS: AI is my friend, indeed. I spent 2 weeks programming something (mcu, C, python) and I decided to use exclusively chatgpt (free) to see how it works in reality. From say 90% I got responses which helped me immediately (cut and paste).Unbelievableproductivity help (I got first prototype working in perhaps 3rd hour). It helps when you stay in the same chat for the entire project (as it always takes the entire previous chat content for the next inference) and also when you are uploading parts of your source to it such it always is in sync with your local changes (so it uses your vars, defs, funcs, naming, etc. even when you asks something new after a week of chat). The chat size from my exercise is over 6MB (code itself only 1300lines and it never got my source in full, perhaps 25% from it)..Quote