WCH $0.10 USD RISC-V MCU - Page 1
Forum section: electronics / general

author: mon2
author_rank: Frequent Contributor
timestamp: October 31, 2022, 09:27:14 pm
content: Hi. Perhaps old news elsewhere but new here ?WCH has some more devices of interest in the pipeline...$0.10 USD RISC-V MCUEnglish manual:https://github.com/openwch/ch32v003/blob/main/CH32V003RM-EN.pdfhttps://www.cnx-software.com/2022/10/22/10-cents-ch32v003-risc-v-mcu-offers-2kb-sram-16kb-flash-in-sop8-to-qfn20-packages/https://www.reddit.com/r/RISCV/comments/y2nw0f/ch32v003_price_is_less_than_010/https://www.hackster.io/Makergo/ch32v003-development-board-the-chips-are-just-10-cents-7712c9Kit is out of stock except on Tindie at this time of writing.https://www.tindie.com/search/?q=CH32V003+Update (11-03-2022):1) LCSC has the device and kit now marked as EOL. We pinged WCH for advice and they suggested for us to purchase from their Aliexpress webstore.2) WCH has recently posted the MCU & kit on their Aliexpress portal at even a lower resale (for the kit & debugger):https://www.aliexpress.com/item/1005004895791296.html?spm=a2g0o.store_pc_newArrival.8148356.7.356e5c5bzrwqwv&pdp_npi=2%40dis%21USD%21US%20%245.80%21US%20%245.51%21%21%21%21%21%402100bddb16674753165278582e62a5%2112000030932586121%21sh

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 31, 2022, 09:45:48 pm
content: 1.1 cent, 20KB / 496 bytesMB95F354EPF-G-SNE21.3 cent, 36KB / 1KBMB95F656EPFT-G-SNE2There're plenty of such deals. But they're rarely stable, once the 1 cent starts selling well, it either goes $0.90 (Or more), or goes out of stock forever.

author: wraper
author_rank: Unknown
timestamp: October 31, 2022, 09:49:11 pm
content: Quote from: DavidAlfa on October 31, 2022, 09:45:48 pmIt's not a real price and zero in stock. Here is realistic pricehttps://eu.mouser.com/ProductDetail/Infineon-Technologies/MB95F354EPF-G-SNE2?qs=%2FPVulymFwT2EPYkJ23r4XA%3D%3D

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 31, 2022, 09:51:55 pm
content: Quote from: wraper on October 31, 2022, 09:49:11 pmYes. It's also EOL.

author: DavidAlfa
author_rank: Super Contributor
timestamp: October 31, 2022, 09:56:31 pm
content: Yeah, but if you buy 20.000 and does the job, what's the problem? It all depends on the project.Lots of non-EOL products have flown away for months, you're never safe.Edit:Ooops, I forgot to click "Apply" after checking "In stock".

author: ataradov
author_rank: Super Contributor
timestamp: October 31, 2022, 11:25:53 pm
content: I have a plan to play with WCH RISC-V devices. I really like what they do with SWD and interrupt controller on their devices. They skipped standard RISC-V nonsense and use ARM approach instead. Not sure how well it all works in practice.If this seems to be usable, and the price and availability remain reasonable, it might be a good generic MCU.Although this specific device seems to have some one wire programming interface. So, this is something to investigate too.Too bad ICs are not readily available from reasonable sources yet. Would be an interesting project for the new year break.

author: HwAoRrDk
author_rank: Super Contributor
timestamp: November 01, 2022, 12:16:01 am
content: I really like the look of these.WCH are obviously gunning for the market served by the STM8S003 - hence the naming convention, the fact the pinout is virtually identical (basically drop-in for TSSOP20 package, all major peripherals on the same pins), and the price.One thing I don't like, though, is that if the description of being a "RISC-V2A core" is any indication of CPU capabilities, while it has the 'A' atomic extensions, it doesn't appear to have the 'M' integer multiplication/division extensions. Or is that a given for most RISC-V cores, so they don't feel it worth a mention?What is the space efficiency like of the RISC-V instruction set? That is, is 16KB of flash considered large or small for a RISC-V chip?

author: ataradov
author_rank: Super Contributor
timestamp: November 01, 2022, 12:35:06 am
content: "QingKe V2A" is just a random core name. Architecture is RV32EC, so basic instruction set with 16 registers with compression supported. In my tests RV use of compressed instruction set makes the code on par or 10-20 % bigger than comparable Thumb-2 code. It depends on the code specifics.There is no hardware multiplier/divider in this device.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 01, 2022, 08:34:50 am
content: They look very interesting indeed.

author: brucehoult
author_rank: Super Contributor
timestamp: November 01, 2022, 09:36:59 am
content: Quote from: mon2 on October 31, 2022, 09:27:14 pmYupQuoteMy post, 19 days ago :-)QuoteAnd the chips there are the 20 pin version for $5 for 5.I assume it's the 8 pin ones are supposed to be under $0.10. I don't know how much for the bigger packages.That $0.10 price is from the company CEO. As his tweet said, they should be on LCSC, but so far only the dev board has appeared there.

author: brucehoult
author_rank: Super Contributor
timestamp: November 01, 2022, 09:46:03 am
content: Quote from: ataradov on November 01, 2022, 12:35:06 amOooh .. I hadn't seen the manual or information that they are RV32E not RV32I.QuoteFrom what I can see the difference is usually from single-bit instructions, where bit-banding is used on ARM. Assuming the RISC-V is compiled with -msave-restore to get function prolog/epilog out of line at the cost of 3 jumps (which is usually negligible). Sometimes array addressing can have an impact, but it's unusual to be significant in optimized code.The B extension makes a big difference with both, but that hasn't made its way into cheap hardware yet.QuoteInteresting, but not surprising. The 8 bit CPUs this is aimed at tend not to also.I wonder what the performance of the shift instructions is. All the other RISC-V microcontrollers I know of have RV32IMAC, often with slow multipliers but 1-cycle arbitrary shifts. But maybe they have cheaped out on the shifter too.

author: brucehoult
author_rank: Super Contributor
timestamp: November 01, 2022, 09:53:02 am
content: Quote from: HwAoRrDk on November 01, 2022, 12:16:01 amIt's great compared to PIC, AVR, 8051, 6502, z80 ... especially if dealing with data bigger than 8 bits.Not quite as good as Thumb2 with the base ISA (which was optimised for workstation benchmarks such as SPEC including SPECfp), but recent ISA extensions (not present in this chip) have brought it closer and the upcoming Zc* extension makes it better according to people in companies such as Huawei who have been instrumental in the design and have been deploying an early version in production devices for a year or two already.https://www.reddit.com/r/RISCV/comments/y3p7wi/public_review_for_standard_extensions_zc/

author: HwAoRrDk
author_rank: Super Contributor
timestamp: November 01, 2022, 12:19:31 pm
content: Quote from: brucehoult on November 01, 2022, 09:46:03 amDisappointing. I guess they didn't include it because they want to cut the die size down as small as possible to make it cheaper.The silly thing is that the STM8S003 - the chip they're targeting the market for -doeshave hardware multiply and divide.

author: mac.6
author_rank: Regular Contributor
timestamp: November 01, 2022, 01:14:59 pm
content: Is RV32E well supported by toolchains? it as not the case a few years away...I remember having compaired BLE linklayer code between cortex M0 and early pulpV toolchain, code size was horrible on pulpV (over 50% increase), this may comes from absence of option like --save-restore.Clearly code size is the n°1 grip people have on risc-v, as most design are more constrained by flash/sram sizing than core gate count, that's where you clearly see the education origin from risc-v.

author: brucehoult
author_rank: Super Contributor
timestamp: November 01, 2022, 05:38:03 pm
content: It's not education origin, it's workstation origin. RISC-V has by far the most compact code of any 64 bit ISA. The 16 bit "C" extension opcodes were allocated with the assumption that you are doing lots of floating point.Microcontrollers and even 32 bit in general were very much an afterthought. That it comes so close to ARMv7 is quite remarkable. It should beat Cortex M0 with its much weaker than ARMv7 ISA.In every case I've seen where someone complained that "RISC-V code is much bigger than ARM code" it was actually that the C library they were using was an inappropriate one designed for another purpose and that's where all the space went. Not any difference in the ISAs.

author: ataradov
author_rank: Super Contributor
timestamp: November 01, 2022, 06:07:48 pm
content: Yes, MCU stuff based on RISC-V is below average. Not only in code size, but also in general architecture. This is why I appreciate WCH effort to keep as much of ARM-like stuff as possible while replacing the core. I have not tried how well this works in practice, but it can't be worse than "native" RISC-V MCUs.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 01, 2022, 07:10:10 pm
content: Regarding price/performance, Nuvoton has pretty cool ARM-based stuff and at this point, for very low-cost MCUs, I would favor that.Now it's great to see all those RISC-V MCUs flourishing - great to have more choice and break the ARM "monopoly". But yes, most of them are not quite on par with the ARM-based offering yet.

author: mac.6
author_rank: Regular Contributor
timestamp: November 01, 2022, 07:44:16 pm
content: Quote from: brucehoult on November 01, 2022, 05:38:03 pmI am in a different mindset than general MCU user, I use risc-v for dedicated controller in a MPU, and it's a tough sell than you need to increase code size by 15 to 20% just because you went from a M0 to a risc-v unless you really need risc-v for dedicated extension.

author: brucehoult
author_rank: Super Contributor
timestamp: November 01, 2022, 07:57:05 pm
content: Quote from: mac.6 on November 01, 2022, 07:44:16 pmShow me the code with this alleged 15 to 20% size difference between Cortex M0+ and RISC-V. I simply do not believe it, and I've seen a lot of RISC-V code.I mean on something that threatens to fill the 16 KB flash on a chip like this, not some cherry-picked single function. And not ARM using a hyper-optimised shortcut-taking embedded C library and the RISC-V using Newlib.

author: ataradov
author_rank: Super Contributor
timestamp: November 01, 2022, 08:51:51 pm
content: For a practical test of the application that may be suitable for an MCU like this (minus lack of USB here), I build this firmwarehttps://github.com/ataradov/free-dap/tree/master/platform/samd11with "rv32imc" target. Everything else remained the same, so that target RV MCU would have the same memory map and layout as the SAM D11 (Cortex-M0+). I had to nop out a couple instructions in the assembly sections, but that would not change the code size a lot.The code size for Cortex-M0+ is 9184 bytes. The code size for RV is 10228 bytes. This is about 11% more. For comparison, rv32im code size is 13732 bytes, or 34% over rv32imc.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 01, 2022, 08:58:38 pm
content: Quote from: mon2 on October 31, 2022, 09:27:14 pmInteresting part, strangely limited supply voltage range and only 10b adc, but I like the crystal oscillator present in all packages.A MSOP10 package would be nice ?The 10c is a banner price, at high volumes, but LCSC does have similar parts alreadyhttps://lcsc.com/product-detail/Microcontroller-Units-MCUs-MPUs-SOCs_PUYA-PY32F003L16S6TU_C5128435.htmlclaims 1-7~5.5V and 12b ADC and 32kF 4kR all for 5000+ US$0.1145I think that does have a multiplier.

author: ataradov
author_rank: Super Contributor
timestamp: November 01, 2022, 09:05:22 pm
content: 8 pins is a bit low. There probably are applications where this is suitable, but I could not find any for myself. I've got STM32G0 in SO-8 package just because it was cute. But I could not find any practical uses for it.And yes, all things being equal, I'd go with ARM.

author: brucehoult
author_rank: Super Contributor
timestamp: November 01, 2022, 09:15:07 pm
content: Quote from: ataradov on November 01, 2022, 08:51:51 pmThat is much more believable. It would be interesting to know what A32 and A64 code size is, making the same modifications as for RV. Well, and T32 too.

author: DavidAlfa
author_rank: Super Contributor
timestamp: November 01, 2022, 09:54:42 pm
content: 11% larger program is not that much, what about the core performance?Anyways, the point is you can get 5x mcus for the same money.

author: brucehoult
author_rank: Super Contributor
timestamp: November 01, 2022, 10:00:12 pm
content: Quote from: DavidAlfa on November 01, 2022, 09:54:42 pmObviously that means there would be some cases where the flash is 91% full using M0+, but 101% full using RV, and that's not good. Assuming they had the same flash size in the first place. But if you're using 90% or less, then it doesn't mater at all.

author: westfw
author_rank: Super Contributor
timestamp: November 01, 2022, 10:17:49 pm
content: QuoteSome stuff is so dependent on the compilers and libraries.I've noticed (WRT ARM CM0) that code efficiency might benefit from having divide functions that operated on fewer than 32bits...

author: brucehoult
author_rank: Super Contributor
timestamp: November 01, 2022, 10:36:50 pm
content: Quote from: westfw on November 01, 2022, 10:17:49 pmNote that while CM0 always has a multiply instruction, depending on what options the chip manufacturer licensed from ARM, it might take 32 cycles for the multiply .. or it might take 1 cycle (which presumably limits the clock speed because big fast CPUs usually take 3 or 4 cycles for a multiply!)

author: tszaboo
author_rank: Super Contributor
timestamp: November 01, 2022, 11:41:15 pm
content: Quote from: ataradov on November 01, 2022, 08:51:51 pmI would guess that the M0+ compiler is more mature. Plus RISC-V has all these optional instructions, so maybe they use only the necessary ones while compiling?Quite honestly, I don't really care what core a MCU have. It's like having 30 peripherals on it, and the 31st is the core.But yeah, I don't get the point of these small MCUs either. Chip scale package or BGA would be cheaper and smaller, and not restricted by the number of pins. Though probably more expensive for the assembly.

author: ataradov
author_rank: Super Contributor
timestamp: November 02, 2022, 12:10:36 am
content: Quote from: brucehoult on November 01, 2022, 09:15:07 pmARM9 size is 12664 bytes. Cortex-A5 is 13236 bytes. No Thumb in either case.It is very aggressive with loop unrolling on Cortex-A5 by default.I don't have 64 bit compilers installed.

author: ataradov
author_rank: Super Contributor
timestamp: November 02, 2022, 12:12:19 am
content: Quote from: tszaboo on November 01, 2022, 11:41:15 pmNo, compressed instruction set of RV is just not as good. It is literally compressed instructions that unfold into full instructions. Thumb-2 has dedicated instructions that make sense in 16-bit format that have no direct equivalent in 32-bit word.Looking at the ARM disassembly, the only 32-bit instruction used is "bl" for long branches. RV code uses a lot more 32-bit instructions.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 02, 2022, 01:57:07 am
content: Quote from: brucehoult on November 01, 2022, 10:00:12 pmOf course. And obviously if you are that tight memory-wise, things are not looking good anyway. Any change in compiler version or in code may result in code not fitting anymore. Not sure you want to put yourself in such a situation. I wouldn't, unless it was a one-shot project.

author: brucehoult
author_rank: Super Contributor
timestamp: November 02, 2022, 03:35:50 am
content: Quote from: ataradov on November 02, 2022, 12:12:19 amFor practical purposes, BL is the only 32 bit instruction that ARMv6-M *has*.There are also DMB, DSB, ISB, MRS and MSR but you're not going to see a lot of those memory barriers and status register movement instructions in compiler-generated code.Most of the time a 32 bit RISC-V instruction will be doing the work of two 16 bit Thumb instructions. The most important exceptions are that ARM squeezed 3-address add/sub into a 16 bit instruction, and Thumb has push/pop multiple as a 16 bit instruction while original RISC-V needs a 32 bit instruction to call a millicode function to save/restore multiple registers.

author: westfw
author_rank: Super Contributor
timestamp: November 02, 2022, 07:30:50 am
content: QuoteCould you do a CM3 or other v7m cpu?The v6m instruction set is pretty depressing :-((although I've frequently observed that allowing the use of 32bit thumb instructions seems to decrease the instruction COUNT, but not the code size. You'll get a fancy shifted-operand "LDR R1, #0x10000" (32bit instruction) instead of "LDR R1, #0x1; LSLS R1, #16" (two 16 bit instructions.) Sometimes the M3 code is longer than the M0 code (but presumably faster. Assuming memory can keep up.))

author: tszaboo
author_rank: Super Contributor
timestamp: November 02, 2022, 12:49:33 pm
content: Quote from: ataradov on November 02, 2022, 12:12:19 amOK, fair enough. I'm not sure this matters for such a small device though. I've seen projects that ran out of code space, usually they were using BLE USB and other bloatware libraries that ate all the space. For a small device like this, there is usually a bigger version. If you are not charged unreasonable extra for the extra flash, like STM32s this is not an issue. I mean FFS why is a STM32F103 with some flash costing 10 dollars in quantity, nobody knows.

author: ataradov
author_rank: Super Contributor
timestamp: November 02, 2022, 02:55:40 pm
content: Quote from: westfw on November 02, 2022, 07:30:50 amCM3 is 8644 bytes. CM7 is 8868 bytes.

author: brucehoult
author_rank: Super Contributor
timestamp: November 03, 2022, 08:36:09 am
content: Quote from: ataradov on November 01, 2022, 08:51:51 pmCould you possibly push a branch with the exact changes you made to compile it for RV? I'd like to take a look at it but I don't want to guess what you did and get different results from the start.

author: ataradov
author_rank: Super Contributor
timestamp: November 03, 2022, 04:09:14 pm
content: Here is the project the way it was used for experiments.

author: mac.6
author_rank: Regular Contributor
timestamp: November 04, 2022, 10:01:14 am
content: I tried to compile a selection of my risc-v code to cm0+ and cm33, and I got into a 10-30% range increase for risc-v in code size (per function). Of course, small function are impacted a lot, and bigger function tend to end up in the 10% ballpark.What kill us is that we have pretty strict code requirements which impact a lot code size already (secure coding), on top of that strigent MISRA-C rules that tend to break code into small functions due to cyclomatic (idiocratic) rules.I don't use -msaverestore and probably won't, as it has not been evaluated security wise.

author: woofy
author_rank: Frequent Contributor
timestamp: November 04, 2022, 10:32:58 am
content: Comparing RISCV against other architectures is not trivial. Here's Chris Celio comparing ARMV7 ARMV8 X86 and RISCV:https://youtu.be/Ii_pEXKKYUg

author: brucehoult
author_rank: Super Contributor
timestamp: November 04, 2022, 10:56:43 am
content: Quote from: mac.6 on November 04, 2022, 10:01:14 am!!!!It's 96 bytes of very very simple code, which would otherwise be generated inline in every function.If you are not using -msaverestore then you are not using RISC-V as it was designed to be used in embedded where code size is more important than a couple of percent of speed. It's an integral part of the decisions to 1) not have load/store multiple, and 2) allow choice of register to store the return address in JAL & JALR. (Actually in many cases it makes code faster because with it the hot code fits into L1 cache)

author: brucehoult
author_rank: Super Contributor
timestamp: November 04, 2022, 11:08:23 am
content: Quote from: woofy on November 04, 2022, 10:32:58 amIt's a good talk, but forget you ever heard of macro-op fusion.Far too many hacker news warriors like to claim that RISC-V relies on it for performance, while the truth is that no RISC-V core that I know of implements fusion. It *might* make sense in some kind of high end in-order CPU, but it makes very little sense in either simple CPUs (which can't afford the transistors) or high end OoO CPUs, where simple operations and tracking dependencies are preferred.

author: tim_
author_rank: Regular Contributor
timestamp: November 05, 2022, 08:12:29 pm
content: Did anybody already get his board and managed to set up toolchain etc? Still waiting for mine in the mail.It looks like quite a capable device - and the documentation is well done and english. Also great to see 32bit devices at the low end price points, instead of all the PIC clones.The biggest caveat seems to be the weird power management. According to the datasheet, the device uses a 1.5V core voltage (130nm?) and has an integrated LDO. However the minimum external VDD is 2.7V. 1.2V drop is not what I would consider a LDO... Maybe they took some shortcuts to save IC area?It's cleary not a device meant for ultra-low power operation. Besides the voltage issue, it also looks like the slow oscillator cannot be used as a main clock. The minimum current draw is around 0.5mA unless you use the deep sleep mode that requires external wake up.

author: tim_
author_rank: Regular Contributor
timestamp: November 05, 2022, 08:17:05 pm
content: Quote from: PCB.Wiz on November 01, 2022, 08:58:38 pmI got excited for some minutes, but then I remembered I already had some low cost CM0 in my starsh (HK32F030 etc) that I never got around testing due to absence of useful documentation and concerns that these small niche supplier may hike prices/disappear/have tons of bugs in the periphery.WCH looks somewhat reliable at least.

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 05, 2022, 08:20:29 pm
content: Quote from: brucehoult on November 04, 2022, 11:08:23 amCompletely agree. Fusion makes you sound smart, but in practice almost nobody does it.In one very simple example of fusion sometimes given, you have the 32x32->64 multiply that requires two instructions to get the full 64-bit result, and fusion would avoid multiplying twice. The same can be achieved (and this is what I've done) just registering the last multiply operation and outputting the registered result (if a subsequent multiply matches the operands and signedness), which is even better as it doesn't require the two multiply instructions to be directly consecutive, and it's much cheaper to implement than any kind of fusion.Of course there are cases where it's less trivial and for which fusion would make more sense, but I'm not sure I have seen of many examples of this, as, as you said, OoO in this case is a more generic approach and works much better overall.

author: brucehoult
author_rank: Super Contributor
timestamp: November 06, 2022, 12:52:18 am
content: Quote from: SiliconWizard on November 05, 2022, 08:20:29 pmIronically, one example is that modern high end x86 and ARM cores fuse a compare with an immediately following conditional branch. Ironic because this has always been a single instruction in RISC-V.SiFive's 7-series dual-issue cores (e.g. the U74 in HiFive Unmatched, Beagle Starlight beta, VisionFive V1, VisionFive 2) link a short forward conditional branch over a single instruction with that following instruction. It's not fusion because they don't become a single instruction. Both instructions proceed down the two pipelines in parallel and at the final stage if the branch turns out to be taken then the other instruction is turned into a NOP (the register or memory write is squashed).QuoteGood optimisation. I'd even speculate that its main impact might even be catching simple repeated multiplication of the same operands, not even 32x32->64 cases!QuoteSome of the potential RISC-V instruction fusion candidates have simply been added as official instructions in later extensions. This loses the advantage of code running unchanged on CPUs that don't implement them, but otherwise gains the performance advantages in a simpler way, and also gives code size advantages that fusing wouldn't.The main example that comes to mind is the Zba extension (part of the group of extensions commonly grouped as "B"): add.uw, sh1add, sh1add.uw, sh2add, sh2add.uw, sh3add, sh3add.uw, slli.uw.These are various combinations of:- zero extension of rs1 from 32 to 64 bits (which itself requires a SLLI;SRLI pair in base RVI)- shift rs1 left by 0,1,2, or 3 bits (or 0..63 for slli.uw)- add rs1 and rs2RVI instructions replaced:2: sh1add, sh2add, sh3add, slli.uw3: add.uw, sh1add.uw, sh2add.uw, sh3add.uwFusion might be reasonable for two instructions, but expecting it for three instructions is getting out of hand. Also, if you don't want to break the pipeline design then fused instruction sequences must all modify the same register (i.e. only modify one register), which would constrain a fused instruction sequence for the above to either have Rd distinct from Rs1 and Rs2 (the usual case) or else the same as Rs1. In the very common case where Rs1 is a loop index this means you'd need to either copy it to a new register first (making the fused sequence 1 instruction longer) or else require the first instruction of the fused sequence to be a 4 byte 3-address opcode. So either way you're looking at 6 or 8 bytes of code you're trying to fuse to get the effect of the above 4 byte instructions.The reason for all the .uw variants is that it has been discovered that a frightening amount of code in the wild has been "optimised" by using 32 bit "unsigned", "uint32_t" etc variables as loop counters and array indexes in 64 bit code instead of the natural "int" or a 64 bit type such as "long", "unsigned long", "size_t", "ptrdiff_t", "int64_t", "uint64_t".Legacy 32 bit code of course usually just uses "int". However using a signed 32 bit type such as "int" on amd64 or arm64 is suboptimal because a separate sign-extension step is required, as both ISAs automatically zero-extend 32 bit values to 64 bits. So a lot of people have been going around replacing int with -- not a 64 bit type, which would make sense -- but with a 32 bit unsigned type.And this *pessimises* RISC-V, which automatically sign-extends 32 bit results to 64 bits. RISC-V code is optimal if people use either the legacy code "int" or any 64 bit type.Grrrrr.One of the places this showed up rather badly is in Coremark. Early RISC-V Coremark results typedef'd the offending 32 bit unsigned variables used for array indexing to int. But then ARM and their friends said "that is an illegal modification, you must not change typedefs".So, sh1add, sh2add, sh3add (or just plain "add" for byte arrays) work for indexes of type int32, int64, uint64 while add.uw, sh1add.uw, sh2add.uw, sh3add.uw work for indexes of type uint32 and all the bases are covered equally efficiently.The main reason RISC-V chose to automatically sign-extend 32 bit results, by the way, is because you then only need a single set of (64 bit) compare instructions which automatically work on both signed and unsigned 32 bit values as well. If you zero-extend 32 bit results then you need both 64 bit and 32 bit compare instructions (at least for signed compares).

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 06, 2022, 01:34:52 pm
content: If existing debugging tools like j-link, st-link or FT2232 tools can be used for flashing and debugging it would be very nice, since I would ask my chinese supplier within next week to order 1000units, I hope I could get them around 100$.

author: mon2
author_rank: Frequent Contributor
timestamp: November 06, 2022, 02:36:00 pm
content: @ali, you should contact WCH (factory) - their sales (and tech support) is very responsive. They replied within hours to notify that the tools for this new MCU are available through their Aliexpress webstore.They offer a bundle with the debugger for ~5$ USD.https://www.aliexpress.com/item/1005004895791296.html?spm=a2g0o.store_pc_newArrival.8148356.7.356e5c5bT07QQk&pdp_npi=2%40dis%21USD%21US%20%245.80%21US%20%245.51%21%21%21%21%21%402100bb4a16677452454096350e1da2%2112000030932586121%21shWe have a few on order.Can you update your pricing once it is confirmed ? Also curious at which volume, does one receive @ $0.10 USD each ?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 06, 2022, 02:42:17 pm
content: Thanks mon2 for the tips, Next week I have some orders, I will try to contact them.

author: mon2
author_rank: Frequent Contributor
timestamp: November 06, 2022, 04:29:57 pm
content: Posting a sales contact @ WCH (factory).Quote

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 08, 2022, 08:43:27 am
content: I asked for 1K unit of CH32V003F4P6, and they told me it's 0.127$,I was expecting a better price toughSo I asked them when I should expect under 0.1$, waiting for their answer.

author: brucehoult
author_rank: Super Contributor
timestamp: November 08, 2022, 09:13:44 am
content: Quote from: ali_asadzadeh on November 08, 2022, 08:43:27 amThat seems pretty good for a 20 pin package. Maybe the 8 pin is cheaper.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 08, 2022, 11:51:00 am
content: I want to order 1K units, they told me the 0.1$ price is for the 8 pin package.

author: tim_
author_rank: Regular Contributor
timestamp: November 09, 2022, 09:06:22 pm
content: I received my kit today. Made a good impression. The software can be downloaded from here:https://www.wch.cn/products/WCH-Link.htmlThey left open how to connect the programmer to the MCU board. Will look into this tomorrow.I decapsulated one device (True to the spirit of eevblog, i guess) and found that the IC is approximately 2 mm² in size. I assume that it is based on a dual voltage (1.5V/5V) CMOS process, most likely 130nm or 150nm, plus MTP memory. Considering die price, packaging and test cost, I don't think that this is a high margin product at $0.10, not even in china.For comparison: The famous $0.03 MCU has a die size of 0.25mm², eight times smaller, and a single voltage process with lower mask count.Nevertheless, I am very intrigued and am looking forward to some RV32EC hacking...edit: Corrected scaling of images

author: ataradov
author_rank: Super Contributor
timestamp: November 09, 2022, 09:15:27 pm
content: This is a rather violent decapsulation. Are there pads in the middle of the die?I've ordered the AliExpress one, so it will take a while to arrive here.

author: tim_
author_rank: Regular Contributor
timestamp: November 09, 2022, 09:20:31 pm
content: Quote from: ataradov on November 09, 2022, 09:15:27 pmI just burned off the Epoxy binder, that's much faster than other methods. Some residue is left, I may have to try another iteration. But since I don't have a good microscope, I'll wait for other people to do better imagesYes, looks like there are test pads in the inner area of the die.

author: brucehoult
author_rank: Super Contributor
timestamp: November 10, 2022, 12:45:18 am
content: Cool! So did you get your 1000 chips? Or you sacrificed a dev board?Have you got a blinky running? What's the flashing process?

author: tim_
author_rank: Regular Contributor
timestamp: November 10, 2022, 06:52:52 am
content: Quote from: brucehoult on November 10, 2022, 12:45:18 amThe kit from Aliexpress actually comes with 5 MCUs as sample.

author: ataradov
author_rank: Super Contributor
timestamp: November 10, 2022, 07:07:24 am
content: I've ordered the extended version of the kit with CH32V203 as well. I want to play with SWD interface on non-ARM devices. I wonder if this is just the name they use, or it is an actual SWD interfaace.The 003 uses a single wire programming interface that does not appear to be documented anywhere, so there is some fun to be had in reverse-engineering that.Shipping does not look too fast, but it is fine, I'll probably manage get to that on NY break anyway.

author: tim_
author_rank: Regular Contributor
timestamp: November 10, 2022, 01:04:50 pm
content: Quote from: brucehoult on November 10, 2022, 12:45:18 amThe device can be programmed and debugged based on a single line protocol. You have to connect PD1 with SWDIO on the WCH-LinkE (for some reason only mentioned on the Aliexpress website).It's possible to use the mounriver IDE for debugging (with OpenOCD) or the WCH-Linkutility for programming.The default code contained some example code that created a serial debug console via the serial interface one WCH-LinkE.So far this looks like a capable development environment.

author: brucehoult
author_rank: Super Contributor
timestamp: November 11, 2022, 12:18:25 am
content: Quote from: ataradov on November 10, 2022, 07:07:24 amOK I ordered one too. And a Pinecil. Est arrival in NZ Dec 30. Possibly away from home Dec 23 to Jan 9 anyway .. yet to be decided.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 11, 2022, 09:42:11 am
content: I got volume pricing for the QFN part tooCH32V003F4U6 is 0.123$ so I have ordered around 500 unit for each of these models CH32V003F4U6 and CH32V003F4P6 .I hope I did not do something stupid

author: brucehoult
author_rank: Super Contributor
timestamp: November 11, 2022, 11:20:58 am
content: Quote from: ali_asadzadeh on November 11, 2022, 09:42:11 amDepends on how important $125 is to you and how much pleasure you get from it. It's definitely in "I'd just blow it on a dinner date anyway" range for me.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: November 11, 2022, 02:13:32 pm
content: QuoteI have 1K units of snacks, I would be fat soon enoughwhat's your use case for them?

author: brucehoult
author_rank: Super Contributor
timestamp: November 14, 2022, 10:10:56 pm
content: Quote from: tim_ on November 09, 2022, 09:06:22 pmThis is different devices, but maybe offers some clues?https://www.cnblogs.com/iot-fan/p/13498088.htmlEdit:An apparently working procedure, specifically for the CH32V103 kit ...https://www.reddit.com/r/RISCV/comments/yu7xda/comment/iwcr95t/

author: tim_
author_rank: Regular Contributor
timestamp: November 15, 2022, 09:13:42 pm
content: Quote from: brucehoult on November 14, 2022, 10:10:56 pmIt was actually explained on the Aliexpress website. SWDIO from the programmer needs to be connected to PD1 of the device + power supply. That's it.MounRiver Studio worked out-of-the-box for programming and debugging (using OpenOCD). The programmer also supports a UART that allows printf-style debugging.All-in-all I'd say there is less friction than with the STM toolchain. My main grievance would be that Mounriver is Eclipse based....I did not try working with any of the peripherals, though. So maybe there are still some bugs.There is no multiplier in the device and multiplication are emulated by a software call.Code:000000b4 <__mulsi3>:b4:862amva2,a0b6:4501lia0,0b8:0015f693andia3,a1,1bc:c291beqza3,c0 <__mulsi3+0xc>be:9532adda0,a0,a2c0:8185srlia1,a1,0x1c2:0606sllia2,a2,0x1c4:f9f5bneza1,b8 <__mulsi3+0x4>c6:8082ret

author: brucehoult
author_rank: Super Contributor
timestamp: November 16, 2022, 12:24:36 am
content: Quote from: tim_ on November 15, 2022, 09:13:42 pmGood to know.QuoteThat's expected as the ISA is RV32EC. No "M".This affects Coremark (with all its matrix multiplies) much more than it affects most actual applications.Cortex-M0+ always has a multiply instruction present, but depending on which option the vendor paid for it may take 32 clock cycles.Competition such as 6502, 6800 derivatives (except 6809, which is not binary compatible), z80, msp430, low end PIC don't have multiply.8051 does (4 cycles).That multiply routine takes about 6 cycles per significant bit in the 2nd operand, so if you're multiplying by something smallish (and positive) then definitely put that 2nd if you can.

author: ataradov
author_rank: Super Contributor
timestamp: November 16, 2022, 12:35:10 am
content: Quote from: brucehoult on November 16, 2022, 12:24:36 amI can't imagine that price bump being too high, since I've yet to find an MCU that does not have one cycle multiplier. Slower one may have smaller die area, which may be a bigger concern. But again, it would be interesting to see what kind of device goes with a slower one.My kits should arrive tomorrow, so I guess at least part of the fun would be moved to the Thanksgiving break.

author: brucehoult
author_rank: Super Contributor
timestamp: November 16, 2022, 12:41:13 am
content: Quote from: ataradov on November 16, 2022, 12:35:10 amSingle-cycle multiplier is likely to be the critical path for CPU MHz. Maybe not a problem on M0+ which seem to traditionally top out at 48 MHz -- except RP2040. Others?

author: ataradov
author_rank: Super Contributor
timestamp: November 16, 2022, 01:20:18 am
content: Quote from: brucehoult on November 16, 2022, 12:41:13 amYeah, that's a thing too.Quote from: brucehoult on November 16, 2022, 12:41:13 amSTM32G0 are 64 MHz and use a single-cycle multiplier.

author: josuah
author_rank: Regular Contributor
timestamp: November 16, 2022, 01:25:11 am
content: Reference Manual published 48h ago:http://www.wch-ic.com/downloads/CH32V003RM_PDF.html

author: ataradov
author_rank: Super Contributor
timestamp: November 16, 2022, 01:30:51 am
content: The change compared to v1.2 is in ADC section and a new 1 page Chapter 18 "Debug Support (DBG)".The old one stated "up to 4MHz or 6MHz input clock" the new one is "up to 24MHz input clock".

author: ataradov
author_rank: Super Contributor
timestamp: November 17, 2022, 02:52:00 am
content: I've got the boards. I decided to start with CH32V203, since it might have a standard SWD interface. And so far I'm not making a lot of progress.It does appear to be similar to SWD, since after the link reset sequence, reading IDCODE register ends with a status 0 (invalid), and any followup transfers end with device not driving the bus at all. And if the first read is not IDCODE, then it also ignores them. Ignoring is normal, SWD protocol requires IDCODE read to finish interface initialization. But the invalid response is not normal.And repeated link reset actually resets it back to returning the invalid status, so it recognizes that sequence in some way as well.

author: brucehoult
author_rank: Super Contributor
timestamp: November 17, 2022, 11:05:34 am
content: https://www.reddit.com/r/RISCV/comments/yxndai/new_release_of_wchs_flashing_tool_new_linux/

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: November 17, 2022, 12:49:20 pm
content: Quote from: ataradov on November 17, 2022, 02:52:00 amI purchased 10 pcs CH32V203C8T6, and since they have the same pinout than the STM32F103C8T6, i swapped one into a bluepill. I flashes the USB example fimwares downloaded from the WCH page, and all worked fine. However there is no code for implementing a CDC device using this part, and my atempts of porting several C source codes from the STM32F103, have failed (when i eventually make them to compile, they do nothing at run time).The WCH forums aren't of any help. The staff there keep saying from time to time that they are still working on it...

author: ataradov
author_rank: Super Contributor
timestamp: November 18, 2022, 03:55:44 am
content: I've got to experiment with the boards today. The protocol is most definitely not a standard ARM DAP even on parts with two line interface, they just picked the signal names to match ARM counterparts.At this time, I'm not all that interested to reverse engineering this. And from my point of view this is going to slow down the adoption of RISC-V MCUs. If every vendor comes up with their own debugging and programming interfaces, it would be a huge nightmare. Especially if those vendors don't bother documenting the protocol and their tools suck so much.Also, their software definitely tries to phone home. I ran it in an isolated VM not connected to the internet and some operations take suspiciously long time. It can be checking for updates and stuff, but still, be careful.

author: josuah
author_rank: Regular Contributor
timestamp: November 18, 2022, 08:10:21 am
content: Quote from: ataradov on November 18, 2022, 03:55:44 amToo bad! I thought ARM DAP wad ARM-only, but after all why would it be...Quote from: ataradov on November 18, 2022, 03:55:44 amBased on your other comment, this is what happened with RISC-V by often picking JTAG instead of SWD?Quote from: ataradov on November 18, 2022, 03:55:44 amSpooky! Is this the tool you refer?https://www.wch.cn/downloads/WCHISPTool_Setup_exe.html

author: brucehoult
author_rank: Super Contributor
timestamp: November 18, 2022, 08:17:40 am
content: Quote from: ataradov on November 18, 2022, 03:55:44 amOthers have it working no problems, using the information at the links I have provided.

author: ataradov
author_rank: Super Contributor
timestamp: November 18, 2022, 08:25:38 am
content: Quote from: josuah on November 18, 2022, 08:10:21 amLegally there may be issues, I'm not sure what part of it must be licensed. There would still need to be changes to accommodate RV, but using the basic transport should be possible. After all, they copied NVIC, SysTick and other stuff like this.Quote from: josuah on November 18, 2022, 08:10:21 amCompared to this, JTAG would be better. It would be great if someone involved with RISC-V cared about MCUs and standardized 1-2 pin count interface and more importantly, an actual debug subsystem. But they don't care, not even remotely.And ultimately, whatever the protocol/interface it, it has to be documented. JTAG would be just as useless without documentation.Quote from: ataradov on November 18, 2022, 03:55:44 amYes. I think it also tries to load some UI elements from the internet. I'm not sure, but the UI looks broken without internet connection.And this tool did not find WCH-LinkE in the USB mode, just the UART.There is another tool they supply that looks much better and at least seems to be fast enough without internet connection. This tool actually found the programmer and that's what I used to look at the "SWD" interface.Here is the more useful tool that actually worked for me with the real programmer mode, and not just a UART bootloader -https://www.wch.cn/downloads/WCH-LinkUtility_ZIP.html

author: ataradov
author_rank: Super Contributor
timestamp: November 18, 2022, 08:27:13 am
content: Quote from: brucehoult on November 18, 2022, 08:17:40 amVendor tools work. But I don't want to use closed source Win-only tools that phone home.And no, that Linux command line tool is not useful without the GUI because the actual config is taken from the INI file that is saved by the GUI tool. So, you have to run it at least once.

author: GromBeestje
author_rank: Frequent Contributor
timestamp: November 18, 2022, 11:00:14 am
content: I bought a WCH Link From AliExpress.I have been able to program and debug a CH32V103 using OpenOCD built from the source they've released last year.However, using the same OpenOCD, it doesn't seem to be able to debug CH32V203 successfully. It seems to flash though.And regarding the debugging interface. I understand some vendors don't want to use JTAG for the number of pins required. And if using standard SWD is legally impossible, what about using cJTAG?

author: ataradov
author_rank: Super Contributor
timestamp: November 18, 2022, 06:00:15 pm
content: cJTAG would work too. But ARM ecosystem is so much more than just the interface. And that's what fundamentally missing here.With SWD and a standard DAP behind it, you can connect to any unknown device, read standardized identification ROM tables and know what debug components and capabilities are supported by the device. So, debuggers don't need to be told what target is attached to the interface, they can just connect and start working.The physical transfer protocol is irrelevant, it just has to be something common. But the CoreSight system of debug components that ARM designed has no equivalent anywhere else, and that should be the goal of any open standardization effort.I my case the board with CH32V203 that I've got this time did not work with the vendor tool, but the older board I already had with CH32V103 did work. I'm not sure why, it is possible that I killed my board with other experiments.

author: GromBeestje
author_rank: Frequent Contributor
timestamp: November 18, 2022, 10:52:21 pm
content: How much is in the RICSV debugging specifications?I was under the impression that once the physical layer is implemented the debugging is specified.For example, when I consider a GD32VF103 device, which uses standard JTAG,J-Link Commander will connect to it when I only specify "RISC-V" as device type.

author: ataradov
author_rank: Super Contributor
timestamp: November 18, 2022, 11:16:56 pm
content: I was not aware of any standards, but searching for "RISC-V debug: 0.13" from the log leads to this documenthttps://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdfThis is much closer to what is needed. The document seems to only define JTAG transport, but it seems to be extensible.Now the question is which devices actually implement this, and which devices roll their own. There is a chance that WCH implement the same standard but over their own undocumented transport.I guess I need to get GD32 device and play with it.And now I also wonder if WCH interface is actually just cJTAG. I'll have a closer look at it.

author: brucehoult
author_rank: Super Contributor
timestamp: November 18, 2022, 11:18:24 pm
content: Quote from: GromBeestje on November 18, 2022, 10:52:21 pmWell, yes, it's all been specified for a number of years. Only the physical layer changes according to technology, packaging etc.https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdfAnd there is also now standardised low-overhead execution tracing too.https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0rc2/riscv-trace-spec.pdfIt's all referenced from here:https://wiki.riscv.org/display/HOME/RISC-V+Technical+SpecificationsOf course there is nothing to FORCE anyone to follow any given spec -- and designs older than a given spec logically can't anyway -- but there's a lot lower friction for people who do follow the standards rather than inventing something themselves.Saying that no one even cares is kind of dumb. A lot of people care, but it's a lot of work catching up on 35 years of ecosystem in the still less than six years since the very first RISC-V silicon shipped to the general public.https://abopen.com/news/hands-on-sifive-hifive1-risc-v-development-board/

author: brucehoult
author_rank: Super Contributor
timestamp: November 18, 2022, 11:31:50 pm
content: Quote from: ataradov on November 18, 2022, 11:16:56 pmEven the very first commercially-available RISC-V hardware, December 2016's FE-310, implemented a compatible subset of this spec. RATIFIED spec (in 2019), by the way, don't be fooled by the 0.13 version number.https://static.dev.sifive.com/SiFive-E310-G000-manual-v1.0.1.pdfI can't say no one has ever rolled their own, but if you want to be able to simply use OpenOCD or Segger J-Link or whatever that support this spec then why would you?

author: ataradov
author_rank: Super Contributor
timestamp: November 18, 2022, 11:36:39 pm
content: Quote from: brucehoult on November 18, 2022, 11:31:50 pmFor the JTAG, sure. But even at the time of writing that spec it should have been clear that interface requiring 4 wires would be limiting and outdated. And the fact that this spec does not define 2 wire transport is very bad because it is a clear requirement for modern devices.So, as a vendor you have to pick to require a lot of pins or roll your own. And in the best case scenario you will have cJTAG in the worst case something proprietary and hacked up OpenOCD distribution to support it..

author: josuah
author_rank: Regular Contributor
timestamp: November 18, 2022, 11:54:20 pm
content: I wonder why a 1-wire half duplex UART is not used more often, like the UPDI interface:https://github.com/microchip-pic-avr-tools/pymcuprog#serial-port-updi-pyupdiCode:Vcc Vcc┌─────────────────────┐ │ │ ┌────────────────────┐│ USB-UART dongle ├─┘ ┌──────────┐ └─┤ AVR device ││ TX ├──────┤ 1k ├────┬────┤ UPDI ││ │ └──────────┘ │ │ ││ RX ├──────────────────────┘ │ ││ ├──┐ ┌──┤ │└─────────────────────┘ │ │ └────────────────────┘GND GNDIt uses the RESET pin, so does it count as 0.5 pin?The need for an internal clock being turned on, or maybe the slow speed...

author: ataradov
author_rank: Super Contributor
timestamp: November 18, 2022, 11:57:16 pm
content: Reliance on the clock is one big thing. Both JTAG and SWD are fully functional from the interface clock alone. And the whole DAP logic behind SWD is also clocked by the interface clock, so the core may be sleeping or locked, but the debug interface would remain functional and may assist in recovery.I'm not sure about UPDI devices, but AVRs in general are notoriously bad in that respect. It is very easy to brick the device.

author: brucehoult
author_rank: Super Contributor
timestamp: November 19, 2022, 12:06:29 am
content: Quote from: ataradov on November 18, 2022, 11:36:39 pmThe spec talks in a number of places about alternative transport layers, and is designed to not prevent them. USB is explicitly mentioned. Is ARM's SWD physical layer license-free? I don't know.The market, as always, will decide.

author: ataradov
author_rank: Super Contributor
timestamp: November 19, 2022, 12:13:13 am
content: Quote from: brucehoult on November 19, 2022, 12:06:29 amI've seen this, and it is good that there are provisions for this. But just saying that implementations may do something, but not explicitly defining it would lead to chaos.Quote from: brucehoult on November 19, 2022, 12:06:29 amNo idea, but it is not like SWD is a holy grail, it has issues. It is very much linked with ARM DAP implementation, so may not be useful for RISC-V as is anyway. But defining a new clear low pin count interface should be a priority, IMO. And it should not be too hard to do, given that the debug spec is inherently universal enough.Quote from: brucehoult on November 19, 2022, 12:06:29 amThat is true to some extent. But in many cases fails where inferior solutions win because purchasing decisions are not made by engineers. Engineers will have to deal with whatever they are given.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 19, 2022, 04:26:20 am
content: Quote from: josuah on November 18, 2022, 11:54:20 pmIt's not just the clock turned on, it needs to be defined to close tolerances and not change, or debug will crash.I guess someonecouldinclude a debug oscillator, calibrated and separate from the system oscillator, but has anyone actually done that ?Speed is probably ok, as HS-USB Bridge parts can manage 12MBd from FTDI, or 9MBd from WCH in TSSOP20

author: westfw
author_rank: Super Contributor
timestamp: November 19, 2022, 10:02:54 am
content: QuoteNeat. I didn't know they had a web store.Anyway, I ordered the "combo" kit (a 003, a 203, and a programmerlink) on 9-Nov, and it was supposed to arrive by 7-Dec.Instead, it arrive today (19-Nov)! I'm not ready for it !

author: GromBeestje
author_rank: Frequent Contributor
timestamp: November 20, 2022, 08:44:12 pm
content: Nice! I have an order for a CH32V003 board from Tindie in transit. Hopefully it will arrive soon. At the time I ordered that I didn't see any on AliExpress yet. When I search now, I get a result, but "When "Maker Go Store" doesn't sound like what the official WCH store would be called. So what is their store called?

author: ataradov
author_rank: Super Contributor
timestamp: November 20, 2022, 09:01:18 pm
content: Quote from: GromBeestje on November 20, 2022, 08:44:12 pmIt is linked in the edit in the first post of this thread. It is called "WCH Official Store". And it is official, the stuff comes in packaging with WCH logos and stuff.

author: tim_
author_rank: Regular Contributor
timestamp: November 20, 2022, 09:11:18 pm
content: I experimented a little bit to investigate instruction timing on the CH32V003.Using inline assembler in GCC is straightforward. I used the loop below for timing:Code:SysTick->CNT = 0;asm volatile (" li %,1000 \n\t""lop: \n\t"" nop \n\t"" nop \n\t"" c.addi %,-1 \n\t"" bnez %,lop \n\t":  "+r" (x));cnt=SysTick->CNT;The flash waitstates can be configured. At 24MHz core clock, operation at zero waitstates is possible. At 48MHz one waitstate has to be introduced, otherwise the core gets notably unstable.- Instructions execute in one cycle, as expected- A taken branch takes 3 cycles, a nontaken one takes 1. So I guess there is speculative instructions fetch and each taken branch requires a pipeline flush.- An unconditional jump also takes 3 cycles.- One flash memory access is able to fetch two 16 bit instructions at a time. So an additional waitstate will not increase the instruction execution timing of every compressed instruction.- Other than 32 bit fetch, there does not seem to be any kind of cache.-> Pretty straightforward implementation. 48 MHz core clock is of limited benefit, unless you execute from SRAM. Unfortunately the clock system is somewhat unflexible. It does not seem to be possible to use 48MHz clock for the periphery and 24 MHz for the core.

author: brucehoult
author_rank: Super Contributor
timestamp: November 20, 2022, 09:49:25 pm
content: Quote from: tim_ on November 20, 2022, 09:11:18 pmThat's just what you expect from any standard simple 5-stage pipeline that DOESN'T have any form of speculation or branch prediction.Cortex M0 and M3 are similar, they just have shorter pipelines so taken branches add a cycle less.In this part of the market predictable execution time is more important than raw speed.

author: tim_
author_rank: Regular Contributor
timestamp: November 20, 2022, 11:27:32 pm
content: The CH32V203 appears to be significantly faster than the CH32V003.- Taken branches take 2 cycles instead of 3.- It seems to have a caching mechanism that allows executing most instructions from flash in a single cycle even at 144Mhz clock speed. There seems to be some penalty when using too many 32 bit instructions. The V003, in contrast, requires a memory waitstate for clk>24Mhz and will therefore execute instructions in either 1.5 or 2 cycles, dependings on instruction length (16 or 32bit).- Of course, the ISA implementation in the V203 (RV32IMAC) is more complete than in the V003 (RV32EC).

author: brucehoult
author_rank: Super Contributor
timestamp: November 21, 2022, 03:14:58 am
content: Could you check the contents of the mvendorid (0xF11), marchid (0xF12), mimpid (0xF13), misa (0x301) CSRs? I.e.CSRR dst, 0xF11etc.Note: CSRR is a pseudo-instruction that the assembler should recognise, but if not then it'sCRSRS dst, csr, x0

author: tim_
author_rank: Regular Contributor
timestamp: November 21, 2022, 08:00:13 am
content: Quote from: brucehoult on November 21, 2022, 03:14:58 amOn the CH32v003:Code:void printCSR(void){uint32_t tmp=0;asm volatile ("csrr %0, misa": "=r" (tmp) );printf("misa:%X\n", tmp);asm volatile ("csrr %0, mvendorid": "=r" (tmp) );printf("mvendorid:%X\n", tmp);asm volatile ("csrr %0, marchid": "=r" (tmp) );printf("marchid:%X\n", tmp);asm volatile ("csrr %0, mimpid": "=r" (tmp) );printf("mimpid:%X\n", tmp);}output:Code:misa:40800014mvendorid:0marchid:DC68D841mimpid:DC688001The code fails on V203 as I apparently have to enter machine provilege mode first.

author: tim_
author_rank: Regular Contributor
timestamp: November 21, 2022, 08:04:58 am
content: Quote from: tim_ on November 20, 2022, 11:27:32 pmI the mean time I noticed that there is a nice processor manual for the core used in the CH32V203 (QingKeV4):http://www.wch-ic.com/downloads/QingKeV4%20Processor%20Manual_PDF.htmlThe core has a 3 stage pipeline and supports branch prediction. That explains why taken branches are one cycle faster than on the QingKeV2 core.

author: brucehoult
author_rank: Super Contributor
timestamp: November 21, 2022, 08:10:59 am
content: Quote from: tim_ on November 21, 2022, 08:00:13 amYes you do. But all chips start up in M mode. Many microcontrollers don't have anything else.Are you running under some RTOS?

author: ataradov
author_rank: Super Contributor
timestamp: November 21, 2022, 08:11:46 am
content: This document confirms that they are using a proprietary protocol and for details send to "WCH Debug Protocol Manual", which I can't find anywhere.I also though that they licensed the cores, but it looks like they designed them.

author: brucehoult
author_rank: Super Contributor
timestamp: November 21, 2022, 08:27:12 am
content: Quote from: tim_ on November 21, 2022, 08:00:13 amCode:misa 40800014MXL 01 XLEN=32res 0000ext 00 1000 0000 0000 0000 0001 0100ZY XWVU TSRQ PONM LKJI HGFE DCBARV32EC (as expected) plus some non-standard Xtensions.mvendorid=0 should mean it's a non-commercial core, listed athttps://github.com/riscv/riscv-isa-manual/blob/master/marchid.mdBut clearly not.I don't know how to decode those marchid and mimpid :-( Google doesn't help.

author: tim_
author_rank: Regular Contributor
timestamp: November 21, 2022, 10:24:06 am
content: Quote from: brucehoult on November 21, 2022, 08:10:59 amNo, I am using the bare bones code that Mounriver is generating for startup (Basically initializing clock generator and UART).When I try to execute the CSSR instruction, the controller hangs for the V203, while everything is executed on the V003. I am assuming that some kind of exception is generated, but have not looked further into it.

author: tim_
author_rank: Regular Contributor
timestamp: November 22, 2022, 10:23:55 am
content: Quote from: brucehoult on November 21, 2022, 08:27:12 amIts explained in Chapter 8 of the processor manual:http://www.wch-ic.com/downloads/QingKeV4%20Processor%20Manual_PDF.htmlThe CH32V003 seems to have a "2" as a SerialID for the processer core, instead of a "4". The mvendorid register is appearently not implemented, but instead the vendorid is encoded as part of mimpid and marchid.

author: GromBeestje
author_rank: Frequent Contributor
timestamp: November 22, 2022, 07:32:00 pm
content: For the CH32V203 I've gotCode:misa: 0x40901105mvendorid: 0x0marchid: 0xdc68d882mimpid: 0xdc688001It seems, when trying to debug, breakpoints are broken.I am using are regular Eclipse with embedded extentions. I used the register view to obtain these values.

author: GromBeestje
author_rank: Frequent Contributor
timestamp: November 22, 2022, 07:48:29 pm
content: Quote from: brucehoult on November 21, 2022, 08:10:59 amNote the default WCH startup files leave M mode before going to main, for example, seehttps://github.com/openwch/ch32v307/blob/a1a924b5c9a0e54401a5e96324f0fbd48c643665/EVT/EXAM/SRC/Startup/startup_ch32v30x_D8.S#L365I suggest an alternative startup file.I've been working on a startup file and linker scripts that make it possible to use a GD32VF103 and CH32V103 with the same binary.https://github.com/a-v-s/libhalglue/blob/rv32f103/compat/rv32f103/rv32f103.S

author: brucehoult
author_rank: Super Contributor
timestamp: November 22, 2022, 10:32:55 pm
content: Quote from: GromBeestje on November 22, 2022, 07:48:29 pmOwww! More precisely: in the act of jumping to main! So contrary to the C spec there is no return from main. In a microcontroller environment I'd usually expect a return from main to at least lead to an infinite loop in _start.I don't see where PMP is set up. Maybe in SystemInit.Is an ECALL handler provided (and what does it support?), or can you provide your own and do anything you want in it?

author: SiliconWizard
author_rank: Super Contributor
timestamp: November 22, 2022, 10:48:54 pm
content: That's interesting. Do those chips support all privilege levels? Which does it switch to before calling main? User?Doesn't this cause problems for accessing peripherals? Do they switch to M when entering an interrupt? What else?

author: brucehoult
author_rank: Super Contributor
timestamp: November 23, 2022, 12:14:02 am
content: Quote from: SiliconWizard on November 22, 2022, 10:48:54 pmThat depends on what is in the MPP field (bits 12:11, so mask 0x1800) of mstatus when the mret is executed to jump to whatever is in mepc (address of main)Code:/* Enable floating point and interrupt */li t0, 0x6088csrs mstatus, t0So that doesn't touch MPP. Maybe it's set up in SystemInit. Or maybe it's relying on MPP (and others) being set to 0s at reset.Incidentally, it's a bit dangerous to enable interrupts before loading _vector_base into mtvec!QuoteMy thoughts exactly! Depends on what is set into the PMP registers. Do they protect the peripherals I/O memory range from U? I don't know: PMP isn't set up in this file.QuoteBy default, yes, but you can, if supported by the core, delegate individual exception vectors to U (or S, if implemented) mode. Thet requires setting up the utvec to point to user mode trap handlers, which we don't see here, and also medeleg and/or mideleg CSRs, which we also don't see set up here.

author: GromBeestje
author_rank: Frequent Contributor
timestamp: November 23, 2022, 02:23:33 pm
content: Thanks to @tim_ I see they now published an English version of their V4 core manual.Looking at chapter 7, I see it saysQuoteThat explains the problems I am seeing with the CH32V203, as it is a V4B core.I am still waiting for my CH32V003 board to be delivered. I'm wondering if it supports breakpoints or not.

author: tim_
author_rank: Regular Contributor
timestamp: November 26, 2022, 10:46:57 am
content: Has anybody been able to find information about the bootloader? According the the datasheet it resides in a flash memory block at 0x1fff f000. There is definitely code there, but no documentation can be found anywhere.Code:1ffff000: j 0x1ffff7361ffff004: unimp1ffff006: unimp1ffff008: addi sp,sp,-121ffff00a: sw s1,0(sp)1ffff00c: sw s0,4(sp)1ffff00e: sw ra,8(sp)1ffff010: jr t01ffff012: lw s1,0(sp)1ffff014: lw s0,4(sp)1ffff016: lw ra,8(sp)1ffff018: addi sp,sp,121ffff01a: ret1ffff01c: lui a3,0x456701ffff020: lui a5,0x400221ffff024: addi a3,a3,291 # 0x456701231ffff028: lui a4,0xcdef9There are also a couple of other features that lack proper documentation, like the OPAMP, but at least there are code examples for it.

author: brucehoult
author_rank: Super Contributor
timestamp: November 26, 2022, 12:05:11 pm
content: The code at 1ffff008 and 1ffff012 makes a handy little function prolog and epilog that saves the return address and two callee-save registers. Let's call them save_2 and restore_2.So you can write functions like this:Code:foo:jal t0,save_2// go ahead and use s0 and s1 as you wish, as well as the a and t registers.j restore_2If foo is within ±4 KB of restore_2 then the j is a 2-byte instruction, but jal with t0 as the link register is always going to be a 4-byte instruction (with ±1 MB range).

author: tim_
author_rank: Regular Contributor
timestamp: November 26, 2022, 12:20:47 pm
content: Quote from: brucehoult on November 26, 2022, 12:05:11 pmIndeed, its also part of the C library that is linked to every program:Code:__riscv_save_2:000000a0: addi sp,sp,-12000000a2: sw s1,0(sp)000000a4: sw s0,4(sp)000000a6: sw ra,8(sp)000000a8: jr t0__riscv_restore_2:000000aa: lw s1,0(sp)000000ac: lw s0,4(sp)000000ae: lw ra,8(sp)000000b0: addi sp,sp,12000000b2: ret

author: josuah
author_rank: Regular Contributor
timestamp: November 28, 2022, 09:45:46 am
content: Here is the ongoing discussion (25 days ago) about reversing the debug protocol... straight on the official WCH repo's issues!They do not seem to mind, and take part in the discussion.https://github.com/openwch/ch32v003/issues/3Excerpts from it:Quote from: jonsmirlQuote from: martinribelotta

author: DavidAlfa
author_rank: Super Contributor
timestamp: December 14, 2022, 07:54:16 pm
content: Quote from: tim_ on November 05, 2022, 08:17:05 pmDo you still have them?I forgot this and bought 25 for testingIf you have a J-Link (A BluePill can also be "converted" into a J-Link OB, PM me for details), it would be nice if you could take few minutes to install STM32 CubeIDE and loadthis project, should compile and run straight away, no lenghty setup required!

author: josuah
author_rank: Regular Contributor
timestamp: December 19, 2022, 06:39:30 am
content: It looks like WCH started selling the bare chips in limited supplies:https://www.aliexpress.com/item/1005005036714708.htmlPacks of 50 in 3 packages options:- 50Pcs CH32V003J4M6 (SOP8) ~0.12 USD per chip, 6 packs left- 50Pcs CH32V003F4P6 (TSSOP20) ~0.18 USD per chip, 6 packs left- 50Pcs CH32V003F4U6 (QFN20) ~0.17 USD per chip, 9 packs left

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: December 19, 2022, 11:54:40 am
content: Currently there is no pack left for the CH32V003F4P6 package. Anyhow, considering one pack purchase, shipping cost and taxes applied to my country increase the price to 0.32€ per chip. Still good price though.

author: DavidAlfa
author_rank: Super Contributor
timestamp: December 19, 2022, 01:15:21 pm
content: Yeah, the shipping cost is almost the same as the 50x chips!So at the end it's 16€ for 50, like you say, 0.32€/chip.Anyways, what happened? They made a mcu 2 years ago and it's already EOL?Selling few packs at Aliexpress? Who is going to buy that else than hobbists?

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: December 19, 2022, 04:02:47 pm
content: They are responsive, I have emailed them directly and they would sell in any QTY that you want, I have get 1200Units of CH32V003 from them directly.

author: DavidAlfa
author_rank: Super Contributor
timestamp: December 19, 2022, 04:42:44 pm
content: Why aren't they selling them at lcsc? They would ship zillions.

author: JPortici
author_rank: Super Contributor
timestamp: December 19, 2022, 07:27:59 pm
content: These microcontrollers always leave me unimpressed. Yes it's cheap, but so is a PIC12/16 (or chinese clone of) with the same very basic set of peripherals and pinout. I guess it makes sense if you already have a development ecosystem built around the manufacturer's parts and peripherals, which is the reason why i still grab a PIC12/16 when i need a generic part with basic functionalityI guess i don't see the fuss over it. I consider these to be the same as the padauks. Yeah the core is more powerful but who cares, you don't really need to do much

author: DavidAlfa
author_rank: Super Contributor
timestamp: December 19, 2022, 09:13:17 pm
content: Would you put a $5 mcu on a led flasher board? Or the cheapest thing that does the job? "A cheap PIC12, of course".What if the cheapest ARM/RISC-V thing is still cheaper any PIC while several times faster?DMA, nice timers, 32-bit processing, 48MHz...It might not be a 400MHz Cortex-M33, but I wouldn't call it a PIC12 either! It's a great device for a lot of projects.The HK32F030 doesn't have DMA, but has more ram, eeprom, better timers and other interesting peripherals.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 19, 2022, 10:51:59 pm
content: But OTOH as said in other threads, if you're a western company designing such ultra-low-cost boards, you're barking up the wrong tree and deluded anyway.Those chips are great for... asian companies that can actually leverage them, and for the sheer curiosity otherwise. Just my 2 cents. I have little doubt westerners will keep looking for cheapass MCUs because, you know, they are cheap.

author: DavidAlfa
author_rank: Super Contributor
timestamp: December 19, 2022, 11:05:39 pm
content: You have libraries, documentation, toolchains and the interfacing is almost identical to other arm devices, so development will pretty straighforward.And while most companies are having a real hard time at sourcing parts, where you might get the stm32 for 40 cents or $2 in 6 months, why not?Buy a few, test them, if doing nice then buy 10K and have stock until you get old.If you have doubts about the future, put your mcu in a small secondary pcb with castellated holes, so retargetting isn't too dramatic.

author: mon2
author_rank: Frequent Contributor
timestamp: December 19, 2022, 11:10:53 pm
content: QuoteWCH is the mfr and also running the Aliexpress store. Respectively, doubt it very much if they are truly 'out of stock'. It is the old FOMO (fear of missing out) market tactic. Willing to bet they will replenish the stock soon.Reach out to their sales / tech support - each has been excellent on each of our emails to the factory.Quoteupdate - found some here:https://www.tindie.com/products/adz1122/wch-ch32v003-risc-v-mcu-offers-2kb-sram-16kb-ic/

author: ataradov
author_rank: Super Contributor
timestamp: December 19, 2022, 11:12:30 pm
content: I'm personally interested in random cheap devices because I like the model where you don't pay more for the support and (somewhat) reasonable example code and documentation. Western companies insist on rolling that into the price, which is fine (literally pays my salary), but I would like to have an option to pay less and explicitly not expect any support in return. Big companies will pick the support option, of course. But vendor support for low volume customers is bad anyway, so why bother?Although I have searches set up for CH32V305 in TSSOP20 package. This would be the smallest device with USB HS support. And according to their schematics with no external components required to support that. Still not a fan of RISC-V MCUs though.

author: uer166
author_rank: Super Contributor
timestamp: December 20, 2022, 02:14:14 am
content: Quote from: ataradov on December 19, 2022, 11:12:30 pmIs that because of lack of a decent NVIC or something related to the interrupt controller? I know I utilize that heavily on ARM and the RISC-V ISR system confuses me.

author: ataradov
author_rank: Super Contributor
timestamp: December 20, 2022, 02:18:13 am
content: The need to program startup code in assembly, inexplicably stupid NVIC controller design also requiring assembly, lack of standardized and documented programming interfaces (except for JTAG, which requires a ton of pins and is not present on relevant devices anyway). WCH tries to address some of that, but it is pretty half-assed.After ARM using RISC-V fell like going back 20 years. Thankfully there are as cheap Cortex-M0 MCUs from China.

author: brucehoult
author_rank: Super Contributor
timestamp: December 20, 2022, 04:17:02 am
content: Quote from: ataradov on December 20, 2022, 02:18:13 amWhat need?Or, conversely, do you not use MSR or MRS in your Arm startup code?

author: ataradov
author_rank: Super Contributor
timestamp: December 20, 2022, 04:23:36 am
content: You don't need MSR or MRS for a useful and functional code. Here is my typical startup code for ARM -https://github.com/ataradov/mcu-starter-projects/blob/master/samd11/startup_samd11.cNot a single assembly line, even obscured by C defines or anything like that.RISC-V core executes the first instruction, so it has to be a branch. WCH devices let you configure the rest of the table to be like ARM - a table of pointers instead of branch instructions. But this first one still must be a real branch. This is possible to workaround by hardcoding the branch to a fixed address and placing the reset vector there. But this only applies to WCH devices.And given abundance of ARM devices, I personally see no real point in using RISC-V at this time. Things may improve in the future, of course.All of this is not a huge deal. Lack of standard programming interfaces is a much bigger deal. I switch between many different ARM device vendors with no change in tooling. This is not really possible with RISC-V device now.

author: westfw
author_rank: Super Contributor
timestamp: December 20, 2022, 05:58:26 am
content: QuoteThat's a good way of putting it.I think China discovered, with the ESP8266 modules, just how much "unpaid support" they could get out of western "hobbyists."And now they're taking advantage of it.It's a great model if you can get it to work. Likewise, letting your old customers support your new customers; which various companies have used to their advantage. EAGLE (when it was provided by CADSoft) was an example. Provide a free hobbyist version, and the hobbyists not only support each other for free, but they help entice paying customers as well.The early Internet, and before that, the mainframe computer industry, also got a lot of mileage from such ... diverse sources.

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: December 20, 2022, 01:00:43 pm
content: Quote from: mon2 on December 19, 2022, 11:10:53 pmYou're absolutely right. The store has updated the missing stock and now there are 4 more packs left. Furthermore, if you take a look at their shop, they have already sold 157 pcs of the ch32v003 kit, and it is very suspicious that there are just 4 items left for selling. It seems that there is always a small amount listed.However i don't understand why they don't renew the stock at LCSC.Regarding the fact that they are focusing onto AliExpress, i think that they are thinking in a long term. They know that nowadays hobbists will be the tomorrow engineers/experts, and designers often use what they already master.Maybe the last would answer my own wondering.

author: tim_
author_rank: Regular Contributor
timestamp: December 20, 2022, 09:59:02 pm
content: LCSC supplies many other variants of CH32V, e.g. the CH32V203 which is also fairly cheap. I guess they will also supply the CH32V003 at some point.I have to admit though, that I never understood their restocking strategy which seems to be rather random.

author: tim_
author_rank: Regular Contributor
timestamp: December 20, 2022, 10:00:41 pm
content: Quote from: DavidAlfa on December 14, 2022, 07:54:16 pmInteresting, I had not noticed there was a thread about them. Will have a read.

author: true
author_rank: Frequent Contributor
timestamp: December 23, 2022, 07:19:06 am
content: Quote from: Sacodepatatas on December 19, 2022, 11:54:40 amYeah, sorry, I bought them lol.But as stated in the thread, it's a false scarcity. WCH will provide more.As others have commented, I too would like to see the V003 available on LCSC...

author: uski
author_rank: Frequent Contributor
timestamp: December 25, 2022, 11:35:10 am
content: There is one interesting point that I did not see mentioned : native 5V compatibility.I know at least one company that is sticking to old microcontrollers from a "western" manufacturer, and that is having increasing difficulties sourcing them, simply because these old MCUs can do 5V. Since western suppliers are moving to more "advanced" process, native 5V compatibility is going away.Looks like these WCH MCUs are built with an older process and the 5V compatibility will be very useful for a certain niche market.I agree with the other posters that their marketing strategy is detrimental. I used to build/sell hundreds of thousands of devices based on an ST STM32F103. Been able to reliably source them for almost 10 years, with proper support channels. A whole company was depending on this stable supply.Going with an exotic MCU might be okay for one off low-cost projects like we see coming out of China when a factory builds 100000 tamagochis and sells them, then moves on to the next product, but for a company that tries to build a product that they will support for many years? I would not bet my business than WCH will play nice...PS: Also, redesigning with another MCU in a scramble, if/when WCH decides to suddenly discontinue this part, may not be possible. Think about regulatory certifications that companies have to do, writing/testing code, ...The opacity of WCH makes them unsuitable for professional stuff in the western world, in my humble opinion. But if I had to build 10000 gizmos for a one-off project, yeah, why not...

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: December 25, 2022, 12:38:32 pm
content: Quote from: uski on December 25, 2022, 11:35:10 amThey aren't really 5V native. WCH began it's business manufacturing "one chip solution" IC for USB interfacing, that is, directly powered from 5V without the need of an external regulator. In fact, many of their MCUs (including the drop-in replacement CH32F103) are 5V capable. This doesn't mean that the entire chip is working at 5V. The sections that run at 5V are tipically the analog ones (opamp, comparator, ADC/DAC) and digital interfacing to external pins throught level conversion. But the core is often running at voltages around 1V in order to reach dozens of MHz while still being low power. This is a trick that use several MCUs, like the MCS-51s of Zilog/Abov.EDIT: As long as the CH32V103 and CH32F103 are both 5V compatible, i asumed that the F/V203 was also compatible, but after taking a look at its datasheet, i've seen that it isn't.Also i don't understand why the V203F8P6 (64kB) and the V203F6P6 (32kB), being both TSSOP-20 have a very different pinout so you cannot replace one with the other in the same footprint.

author: tim_
author_rank: Regular Contributor
timestamp: January 01, 2023, 08:46:49 am
content: Quote from: uski on December 25, 2022, 11:35:10 amAs outlined in the datasheet, it uses an LDO to generated a core voltage of 1.5V from the external voltage. So it also uses a more modern process (130nm?).There are also plenty of suppliers for legacy 5V devices, also in Taiwan and China. E.g. Nuvoton, Padauk...

author: AVI-crak
author_rank: Regular Contributor
timestamp: January 01, 2023, 02:16:52 pm
content: Looking for CH32V305FBP6 (TSSOP20 + USB2.0 HS PHY + 144MHz)It should be cheap after dropping some of the full mince CH32V307VC. But contrary to common sense, it has the highest price tag. Currently used on WCH-linkE - very expensive.

author: mon2
author_rank: Frequent Contributor
timestamp: January 01, 2023, 02:57:05 pm
content: Can you share specifics?Are you receiving a quote from the factory store or a reseller?The reseller will offer scalper pricing.Contact the sales group directly at WCH and also chat their AliExpress store for this part. Do so ASAP before they kick into their CNY holidays. They are very responsive. Recently purchased more kits including one that was not yet on their website. This company has great strengths.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: January 03, 2023, 09:01:03 am
content: Quote from: AVI-crak on January 01, 2023, 02:16:52 pmI find the CH347T, which is their USB-UART using this core, at lcsc for $1.71/1k and the CH32V305FBP6 shows at $1.22/1kFor a HS-USB part, those are quite good prices ?

author: njohn
author_rank: Newbie
timestamp: January 09, 2023, 08:18:12 am
content: Sorry to bump this thread, but I've only just found it...If anybody's interested, to allow me to experiment with my CH32V003 dev. board, I've pulled together WCH's CH32V003 library code and a Makefile etc. to provide a pure Linux command line work flow.Currently you can build, flash and debug a "blinky" type example.You can find it here:https://github.com/nj-designs/libch32v

author: AVI-crak
author_rank: Regular Contributor
timestamp: January 09, 2023, 09:23:29 am
content: Quote from: PCB.Wiz on January 03, 2023, 09:01:03 amI need a link to the store, as well as the exact geographic coordinates (latitude, longitude, altitude above the sea).

author: brucehoult
author_rank: Super Contributor
timestamp: January 09, 2023, 10:38:38 am
content: Quote from: njohn on January 09, 2023, 08:18:12 amNice! I'm going to steal that. Mine arrived December 30, but I haven't had time to open it yet.

author: tim_
author_rank: Regular Contributor
timestamp: January 14, 2023, 05:15:31 am
content: Quote from: tim_ on November 09, 2022, 09:06:22 pmSTM just released their new low-cost STM32C MCU series. For reference, it seems that the die size of the STM32C011D4 is 2.4mm². You can read this directly from the size of the WLCSP package. The device has 32kb of flash, so I assume that the 16kb STM32C011J4 device could be around 2.xmm², very comparable to the CH32V003. We have to take into account that they most likely use slightly different technologies. The STM32C is in 90nm, I beliebve the CH32V003 to be 130nm. Nevertheless, they seem to be quite comparable in area and hence cost.What do we learn from this? Using a RV32E core does not seem to give a significant edge in silicon area over CM0. So what remains is less royalty payments and probably a willingness of WCH to operate at lower margin than STM.Comparing to STM32G (4 mm²) pricing, the STM32C series will probably show up as low as $0.2x in volume. So there could not be a lot of room left for off-brand ultra-cheap RISC V.STM basically created their own STM8S003 killer - fair enough.

author: DavidAlfa
author_rank: Super Contributor
timestamp: January 14, 2023, 01:10:45 pm
content: $0.2? Keep dreaming!Cheapest STM323C0 is still in the $1 price tag:https://estore.st.com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-mainstream-mcus/stm32c0-series/stm32c0x1/stm32c011f4.html

author: tim_
author_rank: Regular Contributor
timestamp: January 14, 2023, 09:34:32 pm
content: Quote from: DavidAlfa on January 14, 2023, 01:10:45 pmThat store also sells the STM32G030 for $2.xx while its listed for $0.45 at LCSC. Actually the ratio fits nicely.s

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 14, 2023, 10:07:16 pm
content: Quote from: tim_ on January 14, 2023, 09:34:32 pmYes it's quite possible it'll be available at this price at LCSC.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: January 15, 2023, 02:45:21 am
content: Quote from: tim_ on January 14, 2023, 05:15:31 amProblem is the STM8S is a wider vcc part, so the STM32C has no hope to kill any 5V uses !!Also, the visible prices of the STM32C are nowhere near the visible prices of 8 bit and 32 bit alternatives, thatarewider Vcc.Other vendors have 90nm low end MCUs already in volume production, so this seems like a late effort by ST to stem the erosion of the STM8S sales/declines, but I still cannot understand why they did a narrow Vcc version for release in 2023 ?!That's the exact opposite of the wider market trend on small MCUs, which have to be highly flexible in their applications.

author: tim_
author_rank: Regular Contributor
timestamp: January 15, 2023, 08:37:15 am
content: Quote from: PCB.Wiz on January 15, 2023, 02:45:21 amDo you still see that many use cases for 5V outside automotive? Anything powered by a battery will be 3.3V or lower. There is also not much else that would be only available in 5V, but not in 3.3V. Ok, if you directly want to drive white LEDs, 3.3V is maybe somewhat close.What I find more annoying is that the lower limit is 2V, which degrades low power performance. (Ok, we have STM32L for that...)

author: josuah
author_rank: Regular Contributor
timestamp: January 15, 2023, 10:19:27 am
content: Quote from: tim_ on January 15, 2023, 08:37:15 amUSB powered devices? Even if they lack USB data connection, I sometimes see a Type-C connector as power plug for all sort of devices that are not computer peripheral.

author: GromBeestje
author_rank: Frequent Contributor
timestamp: January 15, 2023, 07:06:29 pm
content: Quote from: josuah on January 15, 2023, 10:19:27 amI'd say *only* if they lack a USB data connection, as USB's I/O voltage is at 3.3 Volt.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 15, 2023, 07:41:04 pm
content: Quote from: josuah on January 15, 2023, 10:19:27 amSo because USB provides a 5V supply you need to use 5V logic?According tohttps://en.wikipedia.org/wiki/USB#Power(and backed by experience), VBUS may be as low as 4.4V in some situations (and that's not counting cables), so many strictly 5V parts may actually not function properly if directly powered by VBUS. One exception would be those ATMEGA MCUs, which, while many people take them as "5V devices", actually operate on a pretty wide range of 2.7V to 5.5V (at least if you restrict the clock to 8MHz), so VBUS should not be a problem as long as you don't use any other part that would require a tighter tolerance for the 5V, and as long as you don't use VBUS as any kind of reference voltage either.

author: DavidAlfa
author_rank: Super Contributor
timestamp: January 15, 2023, 07:46:05 pm
content: Hell, let's get back to 15V logic then!From my point of view, the 5V argument seems a bit silly.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: January 15, 2023, 09:31:05 pm
content: Quote from: tim_ on January 15, 2023, 08:37:15 amIt is not me making all those new wide Vcc parts, it is the semiconductor suppliers, and they must know the targets.Also note that CMOS LOGIC highest volume parts, are the wide Vcc 1.8~5.5V 74AHCxxx etcLike CMOS logic, small MCUs are now commodity parts, and buyers and distributors want flexibility.Atmel tried releasing a 3v3 only AVR and that is now relegated to a niche part, (ie it flopped) and their latest AVR's released are wide Vcc ones.Quote from: tim_ on January 15, 2023, 08:37:15 am? There are many 3.7~4.2V lithium battery packsQuote from: tim_ on January 15, 2023, 08:37:15 amExactly,a 3v3 part simply lacks the headroom to drive White/Blue high threshold LEDs, as well as the common Serial RGB leds.It relegates them to a niche use, they are not general purpose use parts.For larger MCU's, > 48 pins and >> 100MHz and > 500k Flash, then 3v3 (and multiple power voltages) are more common, and makes sense thermally.- but low pin count, bottom end, commodity MCUs - nah.Quote from: tim_ on January 15, 2023, 08:37:15 amYup, see how you now have to pick from many families....

author: ralphd
author_rank: Frequent Contributor
timestamp: January 15, 2023, 11:32:25 pm
content: Quote from: tim_ on January 14, 2023, 05:15:31 amA few months ago Digitimes had an article about TSMC wafer prices, and pegged 90nm at $2000. Not sure if that was 200 or 300mm, but I'll assume the worst and say 200. Smaller manufacturers will be cheaper, probably around $1600 now. That puts the cost of a 2mm^2 chip at around 10-11c. I'd guess 130nm wafers are around $1000-1200, putting the cost of a 2mm^2 chip at about 7c.

author: josuah
author_rank: Regular Contributor
timestamp: January 16, 2023, 12:56:08 am
content: Quote from: GromBeestje on January 15, 2023, 07:06:29 pmQuote from: SiliconWizard on January 15, 2023, 07:41:04 pmI figured my mistake too late, I misunderstood (or maybe it was implicit) that it was referring to the I/O.It looks like, implicitly, "it does 5V" refers to I/O whereas "it can live off 5V" revers to power supply, and "it can get 5V" might mean 5V-tolerant I/O or something like that.I'll get used to it.

author: JPortici
author_rank: Super Contributor
timestamp: January 16, 2023, 06:45:46 am
content: Quote from: PCB.Wiz on January 15, 2023, 09:31:05 pmAlso direct drive of higher voltage mosfets! once you pick VDS > 100V it's really difficult do find mosfets that wil switch reliably with 3V3 at the gate. I wanted to migrate a project to a newer "better" (bigger, more pins) mcu but i had no board space nor BOM margin for all the then required mosfet drivers

author: tim_
author_rank: Regular Contributor
timestamp: January 16, 2023, 08:47:13 am
content: Quote from: ralphd on January 15, 2023, 11:32:25 pmThese numbers are off. 90nm is 300mm only, 130nm is almost always 300mm.You also need to take into account that the actual wafer cost depends on the number of process features being used in a specific product. To reduce product cost, it is often possible to use simplified processes with reduced mask coutn to reduce wafer cost. For example, small digital designs may need less interconnection layers. Design without demanding analog or power do not need as many different front end devices.

author: brucehoult
author_rank: Super Contributor
timestamp: January 16, 2023, 10:16:55 pm
content: Plus, at these die sizes costs are being dominated by cutting up the wafer, packaging, and testing.The area is also getting dominated by the I/O pads, so even though the active circuit will be smaller (and cheaper) at 90 nm than at 130 nm, the total area may not change much if at all -- this is the main reason it can be just as cheap to make a 32 bit microcontroller as an 8 bit one.

author: SiliconWizard
author_rank: Super Contributor
timestamp: January 16, 2023, 11:08:00 pm
content: Quote from: brucehoult on January 16, 2023, 10:16:55 pmYes, something we have pointed out quite often. Apart from MCUs which natively (meaning, on the die itself, and not just as a package variant with most GPIOs unconnected) have a very small number of GPIOs, they are usually pad-limited. The exception will come from the amount of internal flash/RAM rather than the core itself, but small, low-cost MCUs usually have a very small amount of internal memory, so that's not a factor either.

author: brucehoult
author_rank: Super Contributor
timestamp: January 17, 2023, 12:39:07 am
content: Dave just reviewed it.https://www.eevblog.com/forum/blog/eevblog-1524-the-10-cent-risc-v-processor-ch32v003/

author: tim_
author_rank: Regular Contributor
timestamp: January 17, 2023, 07:33:40 am
content: Quote from: brucehoult on January 16, 2023, 10:16:55 pmThe dicing, packaging (bond wires!) and test cost usually also scales with area of a die through various direct and indirect scaling relationships. So, comparing die sizes is quite a good first order indicator. Of course there are outliers.I/O limitation is less of an issue when you use circuit-under-pad. We have seen that with the Padauk MCUs, and possibly this is also used by WCH. I have seen some stray test pads on the die.

author: Adi
author_rank: Newbie
timestamp: January 29, 2023, 09:22:24 pm
content: Sorry if this is a little off topic ... But just to show that 0.10$ chip can perform decently"CH32V003 controlling ILI9341 over SPI with DMA at 24 MHz"

author: josuah
author_rank: Regular Contributor
timestamp: January 30, 2023, 08:51:27 am
content: I have seen more expensive controllers failing where this one did succeed!Did it have enough memory for a full framebuffer for drawing?On another MCU, we had to generate the output line by line (buffer of 400 rows * 640 pixel * 2 bytes per pixel (YUV422) => 500 kB of RAM needed, only 512 kB on the MCU).

author: brucehoult
author_rank: Super Contributor
timestamp: January 30, 2023, 09:23:04 am
content: Quote from: josuah on January 30, 2023, 08:51:27 amNot even close.The VDC has 172800 bytes. The RISC-V chip has 2 KB.

author: brucehoult
author_rank: Super Contributor
timestamp: January 30, 2023, 11:19:37 am
content: Good catch. Braino.

author: Adi
author_rank: Newbie
timestamp: January 30, 2023, 05:51:30 pm
content: Quote from: josuah on January 30, 2023, 08:51:27 amOnly small buffer(512B)is used for single character to send itwith DMA.

author: betocool
author_rank: Regular Contributor
timestamp: January 31, 2023, 01:30:11 am
content: I watched Dave's video with the 10c chip yesterday. It reminded me heavily of STM32IDE. Seems like a low learning curve if you've done STM32's the last 10 years. I was also pleasantly surprised to see they have a Linux edition.I'm wondering though, that USB - Serial converter he uses, is it just USB - Serial or USB - Serial + Some debug interface?I'm also a bit wary of having that thing running on my main machine... but perhaps on a VM or a secondary PC? And since it's all GNU-Risc-GCC, perhaps even just have a Makefile and see how that goes.Cheers,Alberto

author: thm_w
author_rank: Super Contributor
timestamp: January 31, 2023, 10:43:20 pm
content: Quote from: betocool on January 31, 2023, 01:30:11 amIts discussed in the thread:https://www.eevblog.com/forum/blog/eevblog-1524-the-10-cent-risc-v-processor-ch32v003/

author: MT
author_rank: Super Contributor
timestamp: February 01, 2023, 02:03:58 am
content: Risc V is fodder for horses and has horse like speed and strength, says WCH Patrick.

author: ataradov
author_rank: Super Contributor
timestamp: February 01, 2023, 02:39:16 am
content: They must have some westerner on staff. They should really let them proofread stuff before publishing gems like this.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 01, 2023, 02:51:52 am
content: Chinese marketing is different. That's funny to us but it's just a different culture. It doesn't translate very well, but not sure they even care. I don't think they are running after western clients for their MCUs. So we take them because they're dirt cheap and we basically shut up.

author: ataradov
author_rank: Super Contributor
timestamp: February 01, 2023, 03:05:15 am
content: But they bothered to produce a video in English.

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: February 01, 2023, 03:21:57 am
content: Quote from: ataradov on February 01, 2023, 03:05:15 amAnd Patrick Yang has been very participative on Twitter recently.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 01, 2023, 03:46:36 am
content: And we don't like their allegories with animals?

author: MT
author_rank: Super Contributor
timestamp: February 01, 2023, 01:47:21 pm
content: Quote from: SiliconWizard on February 01, 2023, 02:51:52 amYes, all a westerner needs is a datasheet in English!However the planet is spherical and doing a 360 west will eventually meet east like when matter and anti matter collides and confuse things up!QuoteWeeeeell, im a bit sceptical to allegories when marketing MCU's as we dont know which horse Patrick refereed to, hopefully not this one.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 01, 2023, 07:00:58 pm
content: Not that I don't find this funny or also regret the frequent lack of datasheets in english, or even just proper datasheets, but I'm equally amused at how prompt we westerners are in judging others and willing to curb them to our expectations. I find the allegories pretty funny, but I don't feel like they owe me anything.

author: ataradov
author_rank: Super Contributor
timestamp: February 01, 2023, 07:07:30 pm
content: Quote from: SiliconWizard on February 01, 2023, 07:00:58 pmIt is not about owing or curbing anything. We are just suggesting how they can make their marketing material better. It is fine if they want their marketing to be bad, but a minor effort would go a long way here.It is a typical fault you want to avoid in your ads. Ads must be good enough to cause a conversation about the product, not the ad itself. Japanese ads are kind of reverse though.

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 01, 2023, 07:59:12 pm
content: Quote from: ataradov on February 01, 2023, 07:07:30 pmAnd there it goes again with giving them lessons while trying to do them a service.I'm sure that if they have trouble making ends meet they'll call you.

author: brucehoult
author_rank: Super Contributor
timestamp: February 01, 2023, 10:50:18 pm
content: It's not only the Chinese.Would you decide to not buy a sporty Mazda car because of how much they go on about "Jinba Ittai"?(You should of course buy a Subaru before Toyota sucks all the soul out of them, but Mazda have historically made some very cool but affordable cars e.g. the rotaries and the Miata)

author: MT
author_rank: Super Contributor
timestamp: February 01, 2023, 11:25:25 pm
content: “At the time, internally, we used the term Jinsha Ittai, which, in Chinese characters, means oneness between car and driver. One day, Toshihiko Hirai, the first-gen MX-5’s Programme Manager, started printing Jinba-Ittai — meaning oneness between horse and rider — on his business cards, and I think that’s how it came to be used externally.”https://www.mazda.com/en/innovation/mazda-stories/engineers/jinba-ittai-ideology/Im looking forward "to become one with the MCU"!But most likely the device erratas and undocumented bugs and the devtools suite and funky libs will deny me that pleasure!

author: westfw
author_rank: Super Contributor
timestamp: February 02, 2023, 12:42:58 am
content: I don't mind a bit of Asian folklore in technical marketing.Some of us remember the Motorola "Dragon Ball" CPU, and (sigh) "Peter Packet."

author: brucehoult
author_rank: Super Contributor
timestamp: February 02, 2023, 03:43:12 am
content: Quote from: MT on February 01, 2023, 11:25:25 pm"Kasahara remembers: “There was a moment when I was driving that I suddenly no longer felt the existence of the car. I didn’t feel any ‘strangeness’. I thought, this is it.“Pretty much my highest praise for a car or anything else is "There is nothing that irritates me". It doesn't have to be the fastest, or the one that turns heads, or be the best in anything. Average to above-average along most axes, and bad in none, is perfect.For me, that's been BMW "RT" touring motorcycles (1984 R80RT; 1986 K100RT; 1995 R1100RT, still in use after 27+ years), Honda dual-purpose bikes (1974 XL350; 1980 XR250; 1986 XR600 (for two decades); 2019 CRF250 Rally), Apple computers, and Subaru station wagons (1995 Legacy 250T; 1997 Grandwagon (until 2019); 2017 Outback (in USA in 2019); then reverting to 2008 Outback 2.5XT on return to NZ during COVID).The MX5/Miata is great too. It just can't take many passengers, or much baggage/cargo, or tow. One of my ex-GFs has a 1991 one, in British Racing Green (of course). Our relationship started when I taught her to drive in a 1984 Mini. Long after our relationship ended, I taught her daughter to drive in the MX5. Both were great cars for the purpose. Small, manoeuvrable, manual transmission, and capable of cornering far harder than you'd expect. A beginning driver can get themselves into what they think is trouble, but as long as *someone* turns the steering wheel appropriately the car will get you out of trouble.

author: AVI-crak
author_rank: Regular Contributor
timestamp: February 02, 2023, 05:47:37 pm
content: ch347 +http://www.yaojiedianzi.com/- we get a very fast spi flash memory programmer.25q64 in 36 seconds!!!

author: SiliconWizard
author_rank: Super Contributor
timestamp: February 02, 2023, 08:00:09 pm
content: Quote from: westfw on February 02, 2023, 12:42:58 amAnd, it's not just asian. While admittedly more internal names than marketing terms made up to sell, what exactly is Commodore's "Fat Agnus"?As to poor documentation, I think again they absolutely don't care, and funny thing is that they'd be completely right about that. The funny marketing and sucky docs do not prevent westerners to go bonkers over those few-cent MCUs and buy them by hundreds or thousands. Guess who's laughing in the end?

author: brucehoult
author_rank: Super Contributor
timestamp: February 02, 2023, 09:09:34 pm
content: AGnus would be the Address Generator chip. The fat version has more pins. Simple enough.

author: westfw
author_rank: Super Contributor
timestamp: February 03, 2023, 05:51:25 am
content: I think it's fascinating that Chinese vendors seem to have started targeting American "hobbyists" - cheap development boards, free development environments, documentation in English (even if it's not very good documentation), chips for sale in retail quantities, etc... I'm guessing it's due to the success of Espressif. But it's certainly fun times!

author: ataradov
author_rank: Super Contributor
timestamp: February 03, 2023, 06:02:37 am
content: A lot of this is also because English is universal and there is a lot of demand in some places. There is a HUGE move towards Chinese MCUs in Russia at the moment. Everyone moves away from STM, since those are impossible to get. People are moistly moving towards GigaDevice because they seem to be the closest in compatibility, but others get a lot of attention too.

author: AVI-crak
author_rank: Regular Contributor
timestamp: February 03, 2023, 10:05:39 pm
content: We have already been allocated a room with a very low ceiling, with no sunlight.They said: if there is not enough space, they will force you to rewrite it in assembler.

author: brucehoult
author_rank: Super Contributor
timestamp: February 04, 2023, 12:02:48 am
content: Quote from: AVI-crak on February 03, 2023, 10:05:39 pmесли не Елбрус, проблема нет ))

author: HwAoRrDk
author_rank: Super Contributor
timestamp: February 04, 2023, 08:50:40 pm
content: Anybody know what the ADC's reference voltage is on the CH32V003? I have been reading the datasheet and reference manual, but coming up empty-handed. I would guess it's VDD, but that doesn't seem to be actually stated anywhere.There isaninternal reference voltage available on a separate channel to the ADC, which is stated in the datasheet to be 1.2V, but that's obviously not the ADC's own reference voltage.

author: ataradov
author_rank: Super Contributor
timestamp: February 04, 2023, 09:08:30 pm
content: I think it is implied from the conversion range - Vss-Vdd.

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: February 07, 2023, 10:55:19 am
content: WCH is going to release the WCH-linkE 1-wire protocol.

author: brucehoult
author_rank: Super Contributor
timestamp: February 08, 2023, 12:19:12 am
content: Yeah, and I immediately tweeted back "How about gcc / binutils mods?"

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: February 08, 2023, 01:37:42 am
content: Quote from: brucehoult on February 08, 2023, 12:19:12 amGive him some time for thinking of a propper reply. He might be thinking that horses will eat carrots free from the forest and not from the market. 😁

author: brucehoult
author_rank: Super Contributor
timestamp: February 08, 2023, 03:40:44 am
content: Quote from: Sacodepatatas on February 08, 2023, 01:37:42 amThey're legally obligated to give the source for their modified versions to anyone who they give the binary to (i.e. all users of their chips) who asks for it. And those customers can't be prevented from passing it on, putting it on github, etc. It would be *nice* if they'd work on upstreaming it.

author: HwAoRrDk
author_rank: Super Contributor
timestamp: February 13, 2023, 04:24:47 pm
content: Anybody have a copy of the schematic for the LinkE programmer version WCH-LinkE-R0-1v2?That is the version I received in my dev kit from WCH, but it seems they have revised the design in the meantime, and the only published schematic available on their website is for WCH-LinkE-R0-1v3, which is slightly different (as far as I can tell, newer version has also JTAG pins - TDI & TDO pins instead of duplicate 3V3 & GND, SWDIO & SWCLK double as TMS & TCK).

author: martinribelotta
author_rank: Regular Contributor
timestamp: February 21, 2023, 03:52:13 pm
content: Now, Patrick just posted the 1-wire protocol of debug:https://github.com/openwch/ch32v003/blob/main/RISC-V%20QingKeV2%20Microprocessor%20Debug%20Manual.pdfI hope that this protocol be the same for ch32v307 and familly but addapting the transport to 2-wire interface (Man I need a weekend free to put a logic analyzer over CK and DIO lines on my ch32v307 board)

author: gmb42
author_rank: Frequent Contributor
timestamp: February 22, 2023, 11:01:16 am
content: A tiny $1.50 WCH dev board from Muse labs, the nanoCH32V003. Seehttps://linuxgizmos.com/the-nanoch32v003-is-a-risc-v-dev-board-available-for-1-50/

author: elecdonia
author_rank: Frequent Contributor
timestamp: February 22, 2023, 08:03:37 pm
content: Quote from: westfw on February 03, 2023, 05:51:25 amI think of myself as more of a“frugal independent developer”than “hobbyist.”I retired after a 20+ year full-time hardware/software design engineer position (at one company!). These days I still have plenty of projects but a much more limited budget compared to when my employer was willing to purchase (most) of the development supplies I requested.I continue to support Arduino.cc, Raspberry Pi, adafruit, Sparkfun, and Teensy by frequently purchasing items directly from them. Without them we wouldn’t have either the hardware or the tools to make cost-effective embedded systems.But I also find it irresistible to sample the enormous smorgasboard of Chinese clones, modules, boards, and tools. It costs almost nothing to try them out. Some items are junk. Others are quite well made and stable over time.

author: HwAoRrDk
author_rank: Super Contributor
timestamp: February 22, 2023, 08:58:44 pm
content: Don't you just love it when there are inconsistencies between what a manufacturer's documentationsaysand what code in their HAL/SPL/etc actuallydoes?There are a couple of such inconsistencies I've noticed in the CH32V003 Reference Manual (as of latest available, v1.3).First is to do with the RCC clock configuration register CFGR0. According to the Reference Manual, bits 10:8 are "reserved" and bits 15:11 are for ADCPRE (ADC clock source divider). But wait! Thelibrary headersgive bits 10:8 as for PPRE1 (APB1 clock source divider), bits 13:11 as PPRE2 (APB2 clock source divider), and only bits 15:14 for ADCPRE.Did they decide to throw out the ability to run APB1 and APB2 at speeds different than the main AHB clock in order to have a greater range of dividers for the ADC? It may be that the docs are correct, because theseparate header file for the RCC peripheraldefines its own set of values for the ADC prescaler field that match the docs, and they forgot to update the main header file (it seems to be a pattern that peripheral-specific header files define their own register constants, in duplication of the main header). Who to believe?The second instance is with the I2C peripheral. The manual documents that bits 14:10 of the OAR1 register are "reserved", but yet theI2C_AcknowledgedAddress_7bit constant in the I2C header filehas the value 0x4000, which has bit 14 set, and this constant is always written to the register by theI2C_Initfunction.So what is this bit? It rang a bell in my memory, that I had seen something like this before. Lo and behold, the I2C peripheral of the STM8 has in its OARH register an ADDCONF bit 14 which is documented as "This bit must set by software (must always be written as '1')". Hmmmmm... Are WCH using theexactsame I2C peripheral? Everything else seems to also be highly similar to that of the ST chip. Did they buy the same third-party implementation? Or did they clone it so well, they included the flaws too?

author: josuah
author_rank: Regular Contributor
timestamp: February 26, 2023, 09:32:08 am
content: Quote from: karpouzi9 on February 24, 2023, 10:59:22 amIt will be when the power consumption will also match:In standby, 25°, with the low speed oscillator running (for waking-up periodically and trigger an ADC readout for instance):CH32V003 - 10 uA -http://www.wch-ic.com/downloads/file/359.htmlATtiny202 - 0.7 uA -https://ww1.microchip.com/downloads/aemDocuments/documents/MCU08/ProductDocuments/DataSheets/ATtiny202-204-402-404-406-DataSheet-DS40002318A.pdfNot everything has lower than 1 uA battery consumption as requirement though.

author: tim_
author_rank: Regular Contributor
timestamp: February 26, 2023, 05:45:07 pm
content: VDDmin is also much lower for the ATtinies.

author: MT
author_rank: Super Contributor
timestamp: March 10, 2023, 12:05:48 am
content: CH32V203 manual.In the Standby mode, the contents of 32KB of SRAM can be kept (depending on the planning and configurationbefore going to bed), and the contents of the backup registers are kept.

author: SiliconWizard
author_rank: Super Contributor
timestamp: March 10, 2023, 12:12:02 am
content: Quote from: MT on March 10, 2023, 12:05:48 amGood night!

author: Sacodepatatas
author_rank: Regular Contributor
timestamp: March 10, 2023, 01:29:40 am
content: Also CH32V203 Datasheet...

author: 1276-2449-1-ND
author_rank: Regular Contributor
timestamp: April 18, 2023, 09:44:58 pm
content: Quote from: MT on March 10, 2023, 12:05:48 amIf you put your ear to it when shutting down you can hear it beep and buzz a little lullaby.

author: jnk0le
author_rank: Regular Contributor
timestamp: May 06, 2023, 01:24:10 pm
content: FYIWith a bit cursed github workflow, I've got someones GPL-lettered openocd fork to build windows binaries.https://github.com/jnk0le/openocd-wch/releases/tag/29042023v003 confirmed to work and open eclipse debug session.No idea about the rest as I don't own those and cfg scripting is cursed similarly to code quality (even compared to extracts from MRS).EDIT: it turns out that it requires proprietary drivers to work (enumerate as WCH-LinkRV instead of WCH-Link). Zadig WinUSB doesn't work.

author: jnk0le
author_rank: Regular Contributor
timestamp: May 06, 2023, 06:19:49 pm
content: some notes after briefly debugging this thing:- debugger cannot step over `ebreak` instructions (single step as well as "continue" option). However eclipse breakpoints do work. Probably something with openocd code.- MIE csr register is non functional- `mie` bit can be written (high) by csr instructions only when it's written together with `mpie` (must write 0x88 instead of 0x08).Debugger can however write `mie` bit without touching `mpie`- after a hard reset (remove power, short vcc to gnd), sometimes the `mpop` and `mppop` are set in `mstatus` register- 0x744 in `ra` after hard reset (anyone else?)

author: jnk0le
author_rank: Regular Contributor
timestamp: May 07, 2023, 01:41:35 pm
content: Finally got the startup code a bit more optimized than the vendor one.https://github.com/jnk0le/simple-crt/tree/master/ch32v003while(1) is 208 bytes with static initializers (194 without), and blinky (volatile delay) is 286 bytes.ED: now it's 202, 188, and 280 bytes

author: HwAoRrDk
author_rank: Super Contributor
timestamp: May 07, 2023, 07:18:56 pm
content: Quote from: jnk0le on May 06, 2023, 06:19:49 pmThat's because it doesn't have an MIE register (nor MIP). The list of supported CSR registers can be found in theWCH QingKeV2 CPU manual.Interrupt enable/disable/status are controlled by the proprietary PFIC peripheral using the PFIC_* registers (I say 'proprietary', but it's basically a clone of the STM32F103's NVIC).

author: jnk0le
author_rank: Regular Contributor
timestamp: May 07, 2023, 08:36:09 pm
content: Quote from: HwAoRrDk on May 07, 2023, 07:18:56 pmThose are per interrupt ones somewhat redundant to the core `mie` in `mstatus`, and the ones inside peripherals.

author: westfw
author_rank: Super Contributor
timestamp: May 08, 2023, 12:21:00 am
content: QuoteIs the STM's NVIC anything different that the ARM Cortex-M3 NVIC?

author: GromBeestje
author_rank: Frequent Contributor
timestamp: May 08, 2023, 05:35:59 am
content: It is standard Cortex M

author: ataradov
author_rank: Super Contributor
timestamp: July 14, 2024, 05:11:59 am
content: LCSC never has consistent stock of any MCUs/FPGAs. They only reliably carry passives and connectors from time to time.And also, lack of devices at a distributor is more of an indicator that there is demand elsewhere. They are not discontinued and there are new devices added to the series constantly. It is just really hard to get them.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 14, 2024, 05:23:26 am
content: Yep, but even so, LCSC has never had much CH32V003 that I remember of. They've consistently had CH32V307, and a few others. Don't look at stock quantities. Stock never really exceeds a few hundreds, but for more you'll have to ask for a quote.The CH32V003 is available in relatively large quantities from many shops on Aliexpress. Whether you consider that an option or not is your call, not that we have much choice.

author: brucehoult
author_rank: Super Contributor
timestamp: July 14, 2024, 05:41:35 am
content: Discontinued? Why on Earth?The mask sets will be on file, ready to use at any time, for as long as the production line for that node exists. WCH can run a wafer, or 100 wafers, any time a big order comes in, subject to capacity of course.CTO Patrick Yang is easy to reach by email or even on Twitter. I would think anyone wanting non-hobby quantities, especially on a regular basis, would work directly with WCH for -- you know -- better prices and to allow them to schedule their production runs. They're a small agile company, not an Intel.

author: brucehoult
author_rank: Super Contributor
timestamp: July 14, 2024, 05:49:11 am
content: Quote from: SiliconWizard on July 14, 2024, 05:23:26 amI can't see any downside to using wchofficialstore.aliexpress.com if you just want 50 chips (or smallish multiples of that).Sure, other Ali stores might offer some lower prices sometimes, and might or might not be dodgy, but the above is actual WCH using Aliexpress for order-taking and maybe fulfilment, the same way as thousands of companies use Amazon in the west.It's no less safe than LCSC or TME or Digikey or Mouser.

author: tszaboo
author_rank: Super Contributor
timestamp: July 14, 2024, 01:59:50 pm
content: Quote from: SiliconWizard on July 14, 2024, 05:23:26 amWCH really has to work on their distribution channels. I never seen any linecard in Europe, and nothing is listed on their website.For sure, you don't want to beg the manufacturer for a quote, lead time and shipping for a reel of ~300 EUR.