What Can I Improve on my PCB Design? - Page 1
Forum section: electronics / beginners

author: electroman
author_rank: Newbie
timestamp: October 09, 2024, 02:10:13 pm
content: Hello,I'm new to PCB design and needed to create one for a project I am doing. There are I2C communication lines and a couple other power things. I have a couple questions:Will disorganized tracks cause interference with the I2C protocol or any other protocol?Is there anything that looks like it could cause issues besides that?Attached below is a picture of the PCB,Thank you!

author: PGPG
author_rank: Frequent Contributor
timestamp: October 09, 2024, 03:19:03 pm
content: Quote from: electroman on October 09, 2024, 02:10:13 pmOne of important from interference/disturbance point of view is having continuous GND plane at your PCB.I have posted at KiCad forum some links about PCB design worth reading in my opinion:https://forum.kicad.info/t/decoupling-capacitor-via-placement/25132/14https://forum.kicad.info/t/decoupling-capacitor-via-placement/25132/19I have also posted there my example of 2 layer PCB designed with whole bottom used as GND zone:https://forum.kicad.info/t/approaching-pcb-track-routing-for-a-newbie/36302/8

author: Faranight
author_rank: Unknown
timestamp: October 09, 2024, 03:41:30 pm
content: At a quick glance, my comments are:- The first thing I noticed is lack of a filled GND plane. That's the first thing you should do, typically on the bottom plane.- Power traces should typically be a bit thicker than the signal traces, and they should route power in a star-like formation. They should not snake around.- Similarly, some signal traces look like they are routed over a way too long path than they should be, and they are switching the layers too often. Perhaps reroute them in a similar manner - a star-like formation instead of a snake-like pattern. The board looks like a labyrinth.- U1 could probably use a 100nF decoupling cap close to its Vcc and GND pins.Happy PCB'ing!

author: pcprogrammer
author_rank: Super Contributor
timestamp: October 09, 2024, 03:55:20 pm
content: Another thing is to let go of the forced 45 degree steps in the places where the board is angled. Specifically the track on the red layer near JP4 and JP3.Another thing near JP4 is the two vias very close to each other that can be reduced to a single via with just one connection to JP4.Also look at the component markings on the silkscreen. Try not to overlap them and get a better readability and indication which belongs to which component. Maybe make them a bit smaller.As the others mentioned a proper ground plane reduces on problems, and may even clear up space on the top layer for a better signal layout.If possible pin swapping can also help. With general IO pins on a MCU or FPGA it is at times possible to just swap some IO to make the routing easier and use the new assignments in the software. Back in the TTL chip days it was called gate swapping within devices with multiple gates in them, like 4 AND gates or 6 inverters.

author: Bud
author_rank: Super Contributor
timestamp: October 09, 2024, 05:04:25 pm
content: Where is mounting holes? How the board is intended to be mounted?

author: tooki
author_rank: Super Contributor
timestamp: October 09, 2024, 06:25:15 pm
content: In addition to mounting holes, you probably want to leave more space between the edge of the board and any copper.

author: Refrigerator
author_rank: Super Contributor
timestamp: October 10, 2024, 10:19:23 am
content: Now that's what you call a proper rats nest.*GND plane is missing.*In terms of I2C, bad design will only limit your baud rate.*Wider tracks for power stuff.*Feels like you have too many unnecessary layer changes.