ASIC design at the advanced hobbyist level - Page 1
Forum section: electronics / projects

author: Kelbit
author_rank: Regular Contributor
timestamp: January 14, 2017, 08:38:58 am
content: Hi all,I'm both an electronics hobbyist and an EE. My work life consists primarily of designing electronics for medical devices, and on the hobby side I tend to do a bit of everything.Like most EEs, something I've never done is design a custom chip, and it's definitely been something that's on my electrical engineering bucket list. Unfortunately, I missed the boat on this back in university - I was unaware that I could get designs fabricated at MOSIS for free (current students - take note! If you can find a prof willing to supervise a group of students doing a self-directed study you can getICs made on a 0.5um ON Semi process, and you can probably convince your local Cadence rep to shake loose a Virtuoso workflow for the design). If I'd known about this then, I'd have done it!Is there any feasible way to achieve this at the hobby level? I can think of two barriers to entry here, the price of the design software and the price of the shuttle run.No matter how you cut it, commercial EDA software for chip design is expensive. You can forget about the big players right away (Cadence, Mentor, Synopsys). I can't find prices for "cheap" software like Tanner but I suspect it's also way out of the hobby price range. There are open source options like Electric and Magic, but those don't really lend themselves well to synthesis of decently complicated digital designs.As for actually getting chips fabricated... a lot of people dismiss the idea of low volume custom chips because the masks are expensive (hundreds of thousands on a mature process or millions on a cutting-edge process), but this doesn't really tell the story. All the pure-play foundries operate shuttle services where prototype designs from multiple clients are combined onto batch wafers so that the cost of masks for the proto run is distributed over many clients.All the foundries operate their own shuttle service programs, but I think most people at the university and small company level go through an intermediary. As far as I can tell, the three major ones are MOSIS (USA), CMC (Canada), and CMP (France/EU). At first blush, the prices actually seem pretty achievable - here's CMP's price list:http://cmp.imag.fr/IMG/pdf/cmp_prices_schedule_oct-16.pdf.I'm not sure if this pricing is just for academic users, and if so, if they'd be willing to classify a hobbyist as an academic user (I'd assume not).Assuming the prices given in the above document are actually correct, they are pretty damned reasonable - we're talking 650 EUR per square millimeter for a 0.35um CMOS process, plus wirebonding and packaging fees in the sub-100 EUR range per chip. I think you could probably squeeze a simple 8 bit processor into a 2 mm^2 area, which leads me to believe you might be able to do this under $2500 USD. Definitely pricey for a hobby project, but there are people who spend more money on equally frivolous things.Thoughts, or am I just nuts?

author: TiN
author_rank: Super Contributor
timestamp: January 14, 2017, 09:25:42 am
content: Well, your design should be beneficial from going to custom chip foundry.There are also places around to migrate FPGA designs into custom-ish ASIC, but still based on FPGA array technology. For ALTERA Stratix series ASIC variant was a Hardcopy service, I recall. Of course that does not give as much benefits as "real" custom ASIC, but ease toolkit workflow requirements.

author: nctnico
author_rank: Super Contributor
timestamp: January 14, 2017, 09:46:52 am
content: There is open source IC design software. During my study (in the 90's) I used a package called Nelsis which was created by TU Delft (a university). This seems to be a repository of the source code:https://github.com/JohnDMcMaster/ocean.

author: filssavi
author_rank: Frequent Contributor
timestamp: January 14, 2017, 10:01:56 am
content: Well be prepared to pay a lot of money, it is true that with shuttle services are a lot cheaper then the full production run, since you are paing only a parte of the mask set, bit still depending in the technology you choose and the area of the die you end up paying $1500 for a very small let's say 1u to 0.35u IC to 15000$ for a largeisj(still small, just not tiny) 28nm classe IC The next problem is the debugging usually is fine by probing the bare die but since or requires a probing station capable of doing that you must either find one (tour uni will almost shurely have one) or hope that everything works and skip to the next phaseYou are mie almost done you only have to ship the dies out to package them (dont have a clue of the costs)All' in all if you have a design of can be done, (there are more expensive hobbies) but make no mistakes It won't be Easy and be prepared since tour first run will almost shurely fail ti work ad intendesse (it's just the way It is in engineering, especialy since you dont have specific training in IC design)

author: Ammar
author_rank: Regular Contributor
timestamp: January 14, 2017, 11:33:40 am
content: Quote from: blueskull on January 14, 2017, 10:49:42 amAre there any you recommend?

author: danadak
author_rank: Super Contributor
timestamp: January 14, 2017, 11:54:23 am
content: An intermeadiate approach you could consider Cypress PSOC. It can be customizedon the digital side. It has a great mix of basic analog, its routable, can be customizedfrom schematic capture or in verilog.For me what stands out is -1) Routability2) Fast 12 bit SAR A/D and slow 20 bit DelSig3) DFB (Digital Filter Block) that is dual channel, handle FIR or IIR filters, or DFBcan be used as a GP fast processor block, similar to RISC block4) MSI logic elements GUI based and/or the UDB Verilog capability. Eg. the FPGAlike capability5) Onboard Vref6) IDAC, VDAC, OpAmps (up to 4), comparator, mixer, switch cap, analog mux....7) LCD, COM, UART, I2C, I2S, One Wire, SPI, Parallel, LIN, CAN, BLE, USB9) Custom components capability, create with schematic capture or Verilog10) DMA to offload processes like filters, COM, Display11) ARM M0 (PSOC 4) or M3 (PSOC 5LP) or 8051 core(PSOC 3)12) Extensive clock generation capabilities13) All components supported by extensive prewritten APIshttps://www.element14.com/community/thread/23736/l/100-projects-in-100-days?displayFullThread=truehttp://www.cypress.com/documentation/code-examples/psoc-345-code-examplesGreat video libraryAttached component list. A component is an on chip HW resource.Free GUI design tool with schematic capture, "Creator". Components have rich API library attachedto each component. Compilers free as well.PSOC 4 is low end of family, consider 5LP parts as well. PSOC 4 also has arduino footprint boards (pioneer) as wellhttps://www.elektormagazine.com/labs/robot-build-with-cypress-psochttp://www.cypress.com/products/32-bit-arm-cortex-m-psocRegards, Dana.

author: filssavi
author_rank: Frequent Contributor
timestamp: January 14, 2017, 12:12:10 pm
content: Quote from: danadak on January 14, 2017, 11:54:23 amI have done a bit of full custom analog IC design (designer a simile CMOS opamp nothing too fancy) in uni, and to suggestion that using a PSOC is anywhere near IC design is quite wrongIf you have to find a cheap alternative you could say that FPGA design (especially the first steps) is similar to standard cell digital only IC design.Now i know that PSOCs have Logic blocks, but that does not qualify as FPGA

author: Jay1011
author_rank: Contributor
timestamp: January 14, 2017, 05:27:52 pm
content: I design ASICs as my job. Your assessment of the landscape for hobbyist ASIC development seems to be spot on.A few comments:MOSIS (and perhaps the others you mentioned?) at least used to supply a rudimentary logic cell library and I/O cell library. At the minimum, you want a known-good (silicon-proven) I/O library. I/O cells, even just the plain old CMOS ones, are tricky to get right. You need ESD protection, need to meet various metalization and other requirements so that the pads can be wirebonded reliably, etc. This is not a task that you want to do yourself IMHO.For the standard cell (logic) library, it's feasible to roll you own (again IMHO), but watch out for flip-flop designs as these also have a number of subtleties that require careful attention. Read some textbooks or journal papers on basic DFF designs if you decide to roll you own. The other cells -- NAND, NOR, buffers, inverters, etc. -- you can probably do yourself if you want to. Keep in mind that you'll need to meet various layout, track routing, and pin access requirements if you intend to use an automated placement and/or routing tool.Simulate the heck our of your design, to the point where you should anticipate that perhaps 70% of your time is going to be in simulation making sure your design works correctly and the other 30% will be in logic design and implementation. There's nothing worse than waiting for your ASIC to come back from fab (and spending all that money in your case) only to find it doesn't work.Sorry, I don't have any suggestions in terms of free or nearly-free CAD tools. As you note, in industry most people use Cadence or Synopsys tool suites that cost hundreds of thousands of dollars or more a year to license. One option might be to see if you can enroll in a local community college that happens to offer an IC design course. Even if that course doesn't include actually taping out your design, it might include access to commercial CAD tools.

author: chicken
author_rank: Frequent Contributor
timestamp: January 14, 2017, 05:50:24 pm
content: The OP is probably already aware of it, but here's an episode of the Amp Hour with a lot of relevant information and links.http://theamphour.com/297-an-interview-with-jake-baker/There's also this project out of Japan that wants to open prototype ASIC services to hobbyists.http://hackaday.com/2016/10/13/blinking-an-led-extreme-edition/https://m.facebook.com/makelsi

author: FrankBuss
author_rank: Unknown
timestamp: January 14, 2017, 06:57:52 pm
content: If you have 10 years time, you can write the software for creating ASIC chips yourself, as the inventor of Forth, Chuck Moore, did with OKAD:http://www.ultratechnology.com/okad.htmCode fits in less than 1 MB instead of the GB packages of today, but he could still use it to create his Forth chips. I don't know if OKAD is available to buy or for free, looks like most links to ColorForth etc. are dead now, but I think compared to modern tools it would be difficult to use, like using StarTexter on a C64 and with a MPS801 dot matrix printer, instead of OpenOffice on a PC and a laser printer.

author: nctnico
author_rank: Super Contributor
timestamp: January 15, 2017, 01:12:33 am
content: Quote from: blueskull on January 14, 2017, 10:49:42 amI had similar plans when I was much younger but then I got married and a mini-me (which is now a maxi-me).During my EE study I had to design two NMOS chips (never produced) and there was a lot of focus on simulation and verification during the design phase. IIRC the steps where:- Create test vectors from a functional describtion. In my case that was a hacked GCC compiler where C was used to create a functional model of the logic. Needless to say that was confusing and back then it cost me so much time I had to get clever to finish the project in time for graduation.- Create the schematic using CAD and tools to create logic using PROM like structures.- Verify the logic using the test vectors- Generate a gate level design- Verify the gate level design using the test vectors with both analog and digital spice- Place & route the chip manually- Extract an electrical equivalent of the design and verify using pspice against test vectors and timing requirements.When everything checks out you might have a chip design which actually works. I second the suggestion of using existing gate libraries and more importantly the IO cells. There is a very knowledgable IC designer hanging out on the newsgroup sci.electronics.design called Jim Thompson. He once wrote 'creating chip IO cells is an art in itself which I don't master'.

author: geochrist
author_rank: Newbie
timestamp: June 19, 2017, 01:13:06 am
content: Hi all,Not sure if anyone is reading this entry, but I found it interesting as I've had an opportunity to tape out a mixed-signal chip (that went into production) using an extremely low cost toolset. I used a suite called XIC from WRCAD (http://www.wrcad.com/) which includes polygon editing, DRC, schematic capture, and LVS for a few hundreds of dollars a month. After making total payments of a few thousand dollars (e.g. a year or so "rent"), the tool becomes yours, with a permanent license.I used this toolset several years ago. It worked fine for me because I had an EDA tool job as my daytime job and could build the technology files for XIC. Also my project was only 0.8um CMOS technology, so the demands of verification were much less than more advanced processes.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 19, 2017, 07:01:48 am
content: ARM would gave M0 at 40K price and let you evaluate the core for free, but in free version they have removed the debug capability and the source is encrypted. do we you have any idea about other cores prices? how a company like allwinnertech sell multi-core Cortex A parts at 5USD or less and make a profit (actually they are two chips, Cortex and PMIC), I think more than 50% is their profit, so what is their path? how do they do it? even if you disagree with me and say that they make 0.01% profit and they make 1 Billion chips for each core! then I would ask you the same question, what's their tools and path for making the Chips? they are new in terms of being a company from no where, under 10 years

author: FrankBuss
author_rank: Unknown
timestamp: June 19, 2017, 09:34:45 am
content: Quote from: blueskull on June 19, 2017, 07:16:46 amI guess it is cheaper. If you buy 100, you can get a microcontroller with an ARM Cortex M0 core for $0.70:https://www.digikey.com/short/303z4n. This made me wonder about the current cheapest 8 bit microcontroller at Digikey, and it is $0.25:https://www.digikey.com/short/303zhj. So license cost might be $0.45

author: coppice
author_rank: Super Contributor
timestamp: June 19, 2017, 09:44:06 am
content: Quote from: Jay1011 on January 14, 2017, 05:27:52 pmI think a good rule is to hang a large card with an estimate for the cost of an all layers revision in any areas where people are doing chip simulation.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 19, 2017, 01:55:41 pm
content: QuoteThanks blueskull, I also think it's way more cheaper, something under 10 cents, the main price would be the silicon manufacturing, even with high tech manufacturing, the price of silicon is under 1$ per-core delivered to the customer! So All the prices they say for manufacturing the chips either is just plain bulshit! or there is other cheap ways of making chips as cheep!I just don't know yet, Consider the prices of equipment, masking, lithography,packaging,labor etc... with these prices that in papers or some companies say, it wouldn't just make sense to build anything, even the old dog 555 @ 1u meter node process, just does not make any sense! so how do they do it? do we have a secret manufacturing company, or any underground facilities?

author: djacobow
author_rank: Super Contributor
timestamp: June 19, 2017, 04:51:05 pm
content: I did this very thing when I was an undergrad. Our class used MOSIS as an aggregator for some 2um CMOS fab back in 1995. Mentor Graphics had given our school free access to their tools, which we used for logic simulation, but in the end, we wired everything together in MAGIC. MOSIS provided a pad ring and I believe a cell library, though we designed a bunch of our own cells. Our class assignment was to design a simple video game. The one I did was one of those games where you pick one or two lights to turn off and then the computer picks one or two, and then whoever is stuck with the last light is the loser. The computer always won as long as you went first. About half the class got working chips, including me and my lab partner.Anyway, one thing I remember is that the parts that came back from MOSIS werenot passivated. That means that they were designed to fail inside a year.Later in my career I worked for a fabless chip company that frequently availed itself of shuttle runs and those, too, were not passivated. I don't know why; I don't can't imagine how a few dozen parts would allow you to avoid a real paying production run, but that's what they did.Anyhoo, I think if you are doing just about anything digital, I can't see this being a worthwhile endeavor, except perhaps for the sheer entertainment value. OTOH, if you want to do something analog and/or want to make interesting structures in silicon (inductors, SAW filters, etc) then perhaps there could be something there.Here's a pic of our chip, which I have framed hanging in my office. Looking at it today, the layout was ridiculous and naive in so many ways, but it was a great learning experience. (That link pictured is long dead, btw.)

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: June 20, 2017, 05:53:21 am
content: Dear djacobow, that's very cool design!

author: CopperCone
author_rank: Super Contributor
timestamp: June 20, 2017, 01:35:37 pm
content: don't be suprized if there are 'other benefits' to strange chip layouts and geometries. djacobo..

author: donmr
author_rank: Regular Contributor
timestamp: June 20, 2017, 03:46:45 pm
content: Quote from: Jay1011 on January 14, 2017, 05:27:52 pmMe too, and I second (agree with) all that Jay1011 said.Add to the list if IP that you need to get if you want to use it is RAM. Memories are very special designs, often getting special design rule waivers or interpretations. You won't be able to design one yourself.

author: djacobow
author_rank: Super Contributor
timestamp: June 20, 2017, 04:37:19 pm
content: Quote from: ali_asadzadeh on June 20, 2017, 05:53:21 amThanks, it was a lot of fun to make. I have other plots hanging in my office, but in some ways that is the one I like the most because we did it pretty much by ourselves in the "tall thin man" model.The face was adapted from the old Hitchikers Guide to the Galaxy cover. We had to remove the hands to fit in the second face.My first chip as a professional was in 0.6um gate length and also several times bigger. Already at that size, even in a big plot, you could not really make out individual transistors and deduce the logic anymore.I should get one of those USB microscopes so I can put up a photo of the actual chip.