Phase And Gain Stabalisation - Page 1
Forum section: electronics / beginners

author: Rerouter
author_rank: Super Contributor
timestamp: February 28, 2013, 08:28:40 am
content: Hello all, on and off over the past few months i have been trying to remake my own variant of a lab power supply, however the more i learn the more i get caught up...my current issue is gain and phase margins, as i am led to understand a phase shift of 180 and 360 are both undesirable, and will cause oscillation, however my design is based around 2 op amps back to back with a -90 degree phase shifts over my desired control bandwidth, and -90 + -90 leaves me with -180and for open loop gain, how does it work with multiple op amps?, do i add or multiply the gains of each op amp to work out my margin?so i am wondering both if i am some how misinterpreting the stably phase margins, and both some quick insight to point me in the right direction to making this thing stable (e.g. would 270 degrees be an ideal place to aim for?)attached below is my schematic, it is pretty much 3 loops, the main voltage loop, and minor current and correction loops that pull down the voltage control signal to regulate there respective limits (feel free to use as you please)thanks for any help in advance

author: Kremmen
author_rank: Super Contributor
timestamp: March 01, 2013, 06:59:10 am
content: Lets start from the criterion of stability. There are a few, but conceptually the easiest to understand is the Bode criterion: A feedback system will oscillate, if the phase shift in the feedback loop drops to 180 degrees while the gain remains over 0 dB. In that case the system will oscillate at the frequency of the 180 degree shift. In practical designs it is not enough to narrowly avoid the condition, you need substantial phase margin from 0 dB gain, at least several tens of degrees. If not, the response of the system to disturbances will be visibly oscillatory in nature.For successive amplification stages, you multiply the gains (i.e. add the gain figures if given in dB).Your target in loop gain/phase is nowhere near 270 degrees. Then you have lost already by 90 degrees. Instead you should target a phase lag of less than say 130-140 degrees and see what you can get in practice.One challenge you are facing comes from the circuit topology you have chosen for the pass element: quasi-LDO. In this configuration it is the PNP amplifier stage that determines the dynamics of the loop to a large degree. The PNP transistor is in a common collector configuration and one feature of this is a relatively large output impedance. For this reason, in the system transfer function, a so called load pole is created at the frequency 1/( w RloadCout). This makes the system sensitive to the output capacitance and load resistance. What you commonly see is a requirement for a minimum output capacitance and output resistance, often in the form of minimum output capacitor ESR. This requirement now applies to your circuit as well. The output cap ESR will introduce a zero in the transfer function, with associated phase advance from the zero frequency at 1/( w RESRCout). It is your task to adjust the load pole and ESR induced zero so that the stability criterion is maintained. And to see to it that the control loop overall is well behaved.By the way, what is the correction loop supposed to do, exactly? I see a "voltage" feedback loop and "correction" loop, both taking in a voltage. One of those has to be the main control feedback but what is the other supposed to do?Edit: stupid forum won't do greek letters. So, above, w = omega

author: Rerouter
author_rank: Super Contributor
timestamp: March 01, 2013, 08:34:01 am
content: thank you very much for the replyQuote from: Kremmen on March 01, 2013, 06:59:10 amso i have my 180 degrees of lag from the op amps, yet you later say for the quasi-ldo layout that it introduces a phase advance (lead?) if so would i be right in assuming this is where i should aim to find some margin? over instead possible tweaks to the op amps? or are there ways to trade off bandwidth for phase margin (thinking along the lines of an inverting to output cap, but don't quite understand how it shifts the phase in that case)Quotemy ideal maximum circuit bandwidth would be 100Khz or a little less, now based on your calculation i would need an esr of 45 milli ohm, which puts me in the ball park of the average electrolytic, and as it increases in age i guess it would only make it more stable as its capacity also decreases :/ that or i get a small 50 milli-ohm resistor and tie it off my existing ceramic choice ...? and throw away one of the main advantages,Or instead should i aim for the 1MHz point which seems to be where the phase and gain approach there worst, and would cause oscillation even if on there own? (have attached the phase and gain diagram for my current model)Quotethe correction loop is to set a limit on the kelvin correction, be it from a lead coming off, or say you want to see the set voltage through a devices regulator stage / input diodes on the kelvin sense lines but know what voltage will fry the thing as a upper limit, its a safety features that's just there to get around a limitation of the standard methods (even if probably overkill)and again thanks for the reply i was beginning to thing no one would

author: Rerouter
author_rank: Super Contributor
timestamp: March 01, 2013, 09:57:56 am
content: now to throw a wrench in the works, reading over the "how to crappify a capacitor" thread, it seems paralleling a 10nf cap with 33 ohm of ESR would give me the effective AC ESR 0f about 50 milli-ohm, however i am guessing there is some factor i am overlooking,for reference the equation i am basing this on is, ESR=(C1^2*R1 + C2^2*R2)/(C1 + C2)^2and for the 220nf ESR i am simply using the trace resistance as it would be very low regardless,now while i am still trying to understand the principles at work here to confirm myself, to someone more knowledgeable does this sound correct?

author: Kremmen
author_rank: Super Contributor
timestamp: March 01, 2013, 12:05:35 pm
content: No, that won't work at all.C1 and C2 arebeforethe pass element so they are not part of the transfer function at all as they are not in the feedback loop. So strike them.Paralleling anything with a cap won't give you ESR on that cap. ESR = EffectiveSeriesResistance. So it needs to be in series with the capacitance. You won't get an RC time constant from it otherwise.My suggestion: study LDO regulators for some time before going much further with this circuit. I am sure it will be time well spent. The Interweb has some sites/papers that are actually useful and more or less correct. One thing you need to understand is that a LDO regulator usually has a range of values for the output cap ESR where the system is stable. Under the minimum and over the maximum, the system will oscillate.

author: Rerouter
author_rank: Super Contributor
timestamp: March 01, 2013, 12:26:23 pm
content: sorry for not clarifying, that equation was just about 2 capacitors, i now see that i probably should have altered the labelswhat i was getting at was to add a second capacitor in parallel with the 220nF output cap, with the math from that thread spitting out a 10nf capacitor with 33 ohms of esr, to give me an effective esr of somewhere around 50 milli-ohm on the output, though i will be honest that i feel i am missing some part of the math that i am not accounting forThanks and i will go check out some more LDO references,

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: March 01, 2013, 01:30:25 pm
content: Hi,I just want to share something that will be useful.About 30 years, we used to connect the + output to +sense with a 10 Ohms resistor and the - output to -sense with 10 ohm resistor. This was done inside the power supply. If the sense connection were broken the power supply would simply revert back to local sense. The sense wires had a much lower resistance than 10 ohms, so when remote sensing was used the 10 ohm resistors had very little effect.This technique will greatly simplify your schematic.Other people are giving you good advice on the loop stability.Regards,Jay_Diddy_B

author: Kremmen
author_rank: Super Contributor
timestamp: March 01, 2013, 06:37:25 pm
content: I did some quick simulation just to highlight the stability thing.I created a simple control loop in Multisim - first with the original circuit and next with some poles and zeros added. The associated graphs show the time domain traces. The first one collapses into chaotic oscillations just few milliseconds after start while the second is non-oscillatory with step changes in reference voltage (in the first case the voltage reference is constant - no point in testing step response).I hope the pictures are self explanatory but if not, just ask.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: March 01, 2013, 08:36:48 pm
content: Hi Kremmen and the group,I did a little playing around in LTspice. At this stage this is just a concept.I have used a stepped load, the load steps between 0.5 and 1A to observe the control loop stability.Here is the LTspice schematic:Here is the results:I have attached a LTspice file for anybody who wants to try this out.Regards,Jay_Diddy_B

author: jeroen74
author_rank: Frequent Contributor
timestamp: March 01, 2013, 10:38:22 pm
content: Slightly off topic...You can replace that switch and the voltage source and the load resistors which a current source set as a active load. Has the same time-transient functions as a voltage sourceIt's wise to do a monte carlo analysis; basically testing the influence of real life component tolerances. An example is included with LTSpice.

author: Rerouter
author_rank: Super Contributor
timestamp: March 02, 2013, 04:37:02 am
content: wow, lots of info in one night.Quote from: Kremmen on March 01, 2013, 06:37:25 pmwith the op amp RC feedback pole i can see why based on your earlier equation those 2 values are chosen, however the output capacitor values seem to come to 333Khz, so am left a little curious as to why this discrepancy (though such a fact would be nice in that i can get away with less ESR) and what tradeoffs are due to this?also i now see that i was off by a factor of 10 in my earlier matheither way thanksQuote from: Jay_Diddy_B on March 01, 2013, 08:36:48 pmThanks, though there are quite a few variances, that leave me a little confused?in each of your compensation networks you are using 3 elements, with larger values than kremmens methods, however with a low ESR and a high ESR cap in parallel (and the additional one on the feedback vsense line)i also see that you added a 2.2K resistor to the base of your Q3, was this for stability or some other reasoning? as it would seem to cut into the minimum output of the power supply (requires a larger differential across the pass element towards 0V)and finally the lt1013 seems to be a very different op amp, with a very different phase relationshipQuote from: Jay_Diddy_B on March 01, 2013, 01:30:25 pmi realize its overkill and can very likely knock it down to 2 op amps back to back, but still prefer a controllable limit, over some passive fix, just for my own purposesas for the differential in the voltage feedback, that was to correct for the voltage due to the current sense resistor, (couldn't scale it as easily without low side)once again thank you all very much for the help so far,

author: BravoV
author_rank: Super Contributor
timestamp: March 02, 2013, 04:49:50 am
content: Excellent thread for noob like me, thanks folks !

author: Kremmen
author_rank: Super Contributor
timestamp: March 02, 2013, 07:48:48 am
content: Quote from: Rerouter on March 02, 2013, 04:37:02 amAll the component values are strictly off the cuff, so don't look for deep meaning in the precise values. I didin't even bother to calculate the RC corner freq's but just picked something that would probably work - as it did. Tweaking the values could give you tighter regulation while maintaining stability, but to really get there you need to run actual prototypes. It is quite hard to simulate all real life parasitics and nonidealities.QuoteDe nada.

author: Rerouter
author_rank: Super Contributor
timestamp: March 02, 2013, 12:41:04 pm
content: I ended up finding a version of tina (9.3.50 if it matters) so that i could test the circuit using the exact models of the op amps (i wanted to confirm there wasn't some hidden difference that upset what i had learned, it still works fine),From then i have been torture testing the loop and seeing what component values influence what part of the response, (had to step up the esr closer to 100 milli-ohm else it became unstable on the very large changes) and so far now has come out stable between steps of 1mV all the way up to steps of 4V on the vset, (also had to change the output resistor up to 100K)for the final design a time constant on the voltage set point seems to be one of the best ways to prevent the overshooting issue to a set point change and to dramatically stabilise the loop against it,(but on with testing!)now i am hoping to bring back my differential measurement for the final design, and by simply adding it in the loop with a 1K resistor added to its output, the loop appears stable independent of what i test it with, but the actual phase margin measurements don't seem to quite add up to me.. for instance with a 50mV sine wave being fed into my feedback loop, via this methodhttp://www.tmworld.com/photo/138/138051-TMW08_09F3fig1_415px.gif(except using a voltage source instead of a transformer and resistor)the 2 measurement points never shift by more than a few degrees over 10Hz to 1MHz from each other, however by 80KHz both of them have nearly shifted by 180 degrees from the input frequency, now i am led to believe its only the 2 measurement points that matter, but still leaves me thinking why it might be so close to 0 phase shift (unless being inverting amplifiers in both cases its pulled a 360 degree shift??)attached is my circuit, a 80KHz transient response and the tina model, (yes the output cap is different to the 100uF ideal)edit: tina not p-spice