Common Mode Spikes in LTSpice - Page 1
Forum section: electronics / projects

author: SparkFly
author_rank: Regular Contributor
timestamp: May 28, 2017, 11:11:47 pm
content: Hi all.I am continuing some simulations of a CAN controller, but am having some problem reducing some very big common mode spikes which are occurring on the CAN Bus. A simplified portion of my circuit is as follows:And when I probe the CANH and CANL nodes I get the following:I believe this is a result of the mosfets not being driving fully whilst the Vds is below 0.7V, causing a large current to flow from the pull up resistors. What can I look into, to alleviate this problem? I am very new to these kind of simulations and techniques, any pointers or suggested reading topics would be really appreciated.Thanks for your time in advance.

author: exe
author_rank: Unknown
timestamp: May 28, 2017, 11:33:03 pm
content: May be it's time when intrinsic body diodes conduct? Or the FET model is incorrect/incomplete (I'd try to use a irfz44n first).

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 29, 2017, 11:33:21 am
content: Quote from: exe on May 28, 2017, 11:33:03 pmDude, you clearly don't know what kind of application those are for, and how silly a recommendation it is for this circuit...2N7000 and BSS84 would be closer, but still very much larger than the internal logic devices used in an IC.Anyway, check the delay on the inverted DataIn signal. Use a faster rise time, too. 5ns would be slow for internal logic signals. (20ns would be more like CD4000 internal gate rise time!) The inverter also wouldn't have the same L/W, or kp or whatever, as the output devices. Also, you've added no capacitances, so there is no speed limit -- crank that to 1ps rise time and sure as shit you're going to get a ~1ps risetime out of it. That's pretty unrealistic!I once cooked up some 74HC output device models:Code:.MODEL N NMOS (+ LEVEL = 3+ KP = 52e-6+ IS = 1e-10+ VTO = 0.72+ TOX = 51.3E-9+ NSUB = 2.8E15+ GAMMA = 0.94+ PHI = 0.65+ VMAX = 150E3+ RS = 5+ RD = 5+ CGSO = 1E-10+ CGDO = 2E-11+ CBD = 17.5E-12+ XJ = 0.11E-6+ LD = 0.52E-6+ DELTA = 0.315+ THETA = 0.054+ ETA = 0.025+ ).MODEL P PMOS (+ LEVEL = 3+ KP = 26.606e-6+ IS = 3e-14+ VTO = -0.71+ TOX = 51.5E-9+ NSUB = 3.3E16+ GAMMA = 0.92+ PHI = 0.65+ VMAX = 970E3+ RS = 12+ RD = 3+ CGSO = 1E-10+ CGDO = 2E-11+ CBD = 17.5E-12+ XJ = 0.63E-6+ LD = 0.23E-6+ DELTA = 2.24+ THETA = 0.108+ ETA = 0.322+ )Further, the PMOS statement has: L=2.4u W=1.08m AD=2.4u AS=2.4u PD=30u PS=540uand NMOS: L=2.4u W=420u AD=2.4u AS=2.4u PD=30u PS=390uThe values give about the same output risetime and slope, V(I) curve, and diode drop as a real 74HC family output pin.CAN driver FETs are probably bigger, so scale up the width accordingly.(I did not use internal FET stages in the rest of that model, so I don't have suggestions for L/W of internal FETs. YMMV.)Tim

author: SparkFly
author_rank: Regular Contributor
timestamp: May 29, 2017, 07:39:42 pm
content: Thank you for the replies.T3sl4co1l, those models have been invaluable! Many thanks once again!You seem to have quite some knowledge/experience with vlsi design - is there any recommended reading you'd suggest for someone who is looking to understand it in practical terms? I did a module in VLSI during undergrad, but in all honesty I have very little practical understanding (realistic figures, design methods, etc) as I don't do it in my work.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: May 29, 2017, 10:58:46 pm
content: Afraid not, I just hack things in SPICE."A jack of all trades is a master of none, but oftentimes better than a master of one." Although I would dare say I'm a master of a few, nonetheless.Tim