Video presentation: PCI Express Physical Layer - Page 1
Forum section: electronics / general

author: John_ITIC
author_rank: Frequent Contributor
timestamp: June 08, 2016, 06:04:22 pm
content: PCI Express Physical LayerAn overview of PCI Express Physical Layer Technology- Part 1: Electricalby John Gulbrandsen, Consultant, June 2016http://www.SummitSoftConsulting.comI will in this presentation explain:The main problems with the legacy PCI bus that prompted the development of the new PCI Express architecture.An overview of the physical layer (hardware aspects) of the PCI Express bus and how it differs from PCI.Future presentations will cover higher protocol layers and the associated software features.Physical Layer OverviewPCIe Physical Layer - Slot ConnectorPCIe Physical Layer – links and lanesPCIe Physical Layer – Differential signalingPCIe Physical Layer – Pre-emphasisPCIe Physical Layer – Data ScramblingPCIe Physical Layer – 8b/10b EncodingPCIe Physical Layer – Embedded ClockPCIe Physical Layer – Clock RecoveryPCIe Physical Layer – Data StripingPCIe Physical Layer - BandwidthPCIe Physical Layer – Link TrainingPCIe Physical Layer – Signal IntegrityPCIe Physical Layer – Keep Channel Impedance 50 ohm (SE) or 100 ohm (Diff.)PCIe Physical Layer – keep PCB traces shortPCIe Physical Layer – keep PCB traces shortPCIe Physical Layer – Length MatchingPCIe Physical Layer – Length MatchingPCIe Physical Layer – SERDES examplePCIe Physical Layer – SERDES TX – Step 1/3PCIe Physical Layer – SERDES TX – Step 2/3PCIe Physical Layer – SERDES TX – Step 3/3PCIe Physical Layer – SERDES RX – Step 1/5PCIe Physical Layer – SERDES RX – Step 2/5PCIe Physical Layer – SERDES RX – Step 3/5PCIe Physical Layer – SERDES RX – Step 4/5PCIe Physical Layer – SERDES RX – Step 5/5PCIe Physical Layer – Analog Lab InstrumentsPCIe Physical Layer – Digital Lab InstrumentsPCIe Physical Layer – BooksAbout Summit Soft Consulting & John Gulbrandsen, ConsultantCompany HistorySummit Soft Consulting was founded to offer expert consulting services in device driver and electronics peripheral device design. Over the 20 years we have been in the electronics and software engineering fields, we have had extensive experience with microcontrollers, digital and analog electronics, Windows x86/x64 software and device driver implementation, high-speed board design, signal and power integrity, advanced FPGA digital designs, USB and PCI Express Protocol Analyzer designs and much more.Summit Soft Consulting is comprised of a team of consultants, each with complementary or overlapping skills related to Windows Systems Programming and Advanced Electronics Design. In addition, we work with a growing network of individual consultants across United States, which allows us to provide specialty niche expertise that, perhaps, may not be readily available in-house. The end benefit for you, our client, is that you will work with our competent and experienced team that safely will bring your project to completion within set cost and time budgets. We are located in Aliso Viejo, Orange County, Southern California, mid-way between Los Angeles and San Diego.Keywords: PCI Express, 8b/10b, Differential Signaling, Pre-emphasis, Inter-Symbol Interference, ISI, Data Scrambling, Pseudo-Random data scrambling, Electro Magnetic Interference, EMI, Linear Feedback Shift Register, LFSR, Running disparity, SERDES, Clock Recovery, CDR, Polarity Inversion, Lane Deskew, Link training, Signal Integrity, Jitter, Attenuation, Crosstalk, Pre-emphasis, CHannel losses, Dielectric losses, Skin-effect, Training ordered sets, Byte serializer, 8b/10b encoder, Bit serializer, Clock recovery, Bit-deserializer, Word aligner, Deskew FIFO, Rate Matching FIFO, 8b/10b decoder, Byte deserializer, Byte Ordering, TLP PIPE Interface, Clock Recovery Unit, PCI Express Protocol Analyzer, ITIC 2500A, InternationalTestInstruments.com, SummitSoftConsulting.com, John Gulbrandsen, PCI Express, Impedance Discontinuities