Compensation methods in current sink circuits - Page 1
Forum section: electronics / projects

author: thexeno
author_rank: Regular Contributor
timestamp: August 19, 2015, 03:14:01 pm
content: Hi all!I'm playing with a constant current system for a power LED. But mainly for a personal learning on stability issues.The circuit is this one:The square wave is provided by a microcontroller, with a separated supply that can be used to power the LED. In this circuit, the LED is powered from the separated supply used also for the OPAMP.Firstly, I noticed that the 10K gate resistor introduce oscillation. Removing it, I've noticed that the oscillation is present if the LED is powered at 8.5V and disappears if powered at 5V (the opamp will always have a 8.5V). The LED, if changed with a diode 1N4001, provide oscillation to the circuit in every combination of supplies. There is an instability issue.I solved this by loading the output of the opamp toward GND with a resistors of few Kohms. But I don't know why. Is it reducing the loop gain, so improving the stability? But how to quantify it?I read, for example, the AN2653 from ST about compensation. It is talking about inner, outer loop and snubber. But In the above circuit I can't identify the load resistor needed to apply these compensations. And make it a model of a classical RC load.I've some background in electronic engineering, more digital, so I know a bit of analog, anyway. But the deep analisys of such configuration is never made during classes and since it is not my field, I have some troubles to walk through this analysis.I saw also other solutions in this forum too, but I'd like to know the truth behind the sentence "yeah, well, put a 2K resistor and you can live happily"... or "just put a cap over there".Thanks to everyone for the contribution.

author: AlanR
author_rank: Regular Contributor
timestamp: August 19, 2015, 04:16:37 pm
content: When you add the capacitor from opamp output and to the inverting feedback loop and then add the resistor, you are building what is a called a "Type 1 Compensator". The gain is for AC since no resistor is used for for the feedback loop that connects the output of the op amp with the input. It is given by the impedance of the capacitor divided by the input resistor that you put on the inverting input. The AC "noise" will be inverted and gain of this noise will be determined by the values of R and C you choose. I usually use a 470 to 1000 pF capacitor and a 1K resistor for stability when building contant current sinks with mosfets. I like to use the TL431 since it has everything I need in a convenient package. Also used quite often for switching mode power supplies in Type II and III compensators.

author: moffy
author_rank: Super Contributor
timestamp: August 20, 2015, 01:02:06 am
content: The gate of the FET looks like a capacitor so when you put the 10k resistor in series with it, the delay will tend to cause oscillations. It's a bit more complicated, because you also have parasitic capacitance from the Drain to Source and Drain to Gate. Loading the output of the opamp reduces its output impedance, so it tends to reduce the possibility of oscillation.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: August 20, 2015, 03:20:33 am
content: Quote from: thexeno on August 19, 2015, 03:14:01 pmWelcome to the Forum !!I did a fairly extensive analysis of this type of circuit in this post:https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg462562/#msg462562It shows how I designed the control loop to have a dominant pole.Regards,Jay_Diddy_B

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 20, 2015, 07:06:20 am
content: Heh... gotta love LM324's class B output stage. At light loads, it's kind of sloppy: its connection to the output pin is something like turning a steering wheel by spinning your hands against the crossbars of the steering wheel, rather than gripping it firmly around the edge. As soon as it needs to reverse direction (and it's doing this constantly, due to circuit noise if nothing else), it takes additional time to swing your hand over to the crossbar in the other direction, and pretty soon you're banging back and forth just to keep going straight. Loading it with a resistor puts the output into class A operation, which is something like spring-loading the steering wheel, so your hand always rests on the same crossbar -- but it's very tiring, and costs supply current to do this.Besides that, compensation in general is an important issue, and Jay's got that covered. The best circuit to use is something like,Typically R*C should be equal or greater than Rg*Ciss. It's also beneficial to put some resistance in series with C, which makes a pole-zero compensation network: this has much better phase margin than the dominant pole (integrator) compensation.Tim

author: thexeno
author_rank: Regular Contributor
timestamp: August 21, 2015, 09:32:50 am
content: Thanks to all.@Jay: I read your analysis. I have a question. If I want to apply som sort of compensation, like reducing the loop gain ecc.. I'd like to quantify these values, by intrdocing them in a equation and then in a final circuit. For this reason I made a brief analysis of my circuit, related to what you called the "power stage" with the mosfet, with the control voltage of the OPAMP but not considering the bandwidth of the opamp (because I think it is just a superimposition of the two logarithmic bode plots). Here my analysis:The circuit is modeled as this (change the TL with the LM324, sorry)Must be noted that I've neglected all the capacitances and instead of Cgs I used the value of theCissgiven, called mistakenly Cgs in the following calculus.Vout = (Rs*Gm)/(1+Rs*Gm) * (1-s/z1)/(1-s/p1) * Voa = k*Voawherez1 = -Gm/Cgsandp1 = -1/(Cgs*Rs/(1+Gm*Rs))so I derived the differential voltage at opamp inputVd=Vin-Vout=Vin-k*Voa=Vin-k*Vd*Adwhich is also:Voa=Vd*Ad=(Vin-k*Voa)*AdsoVoa=(Ad*Vin)/(1+k*Ad)obtaining the gain loop T:T=Ad*kThis analysis shows that the power stage have and inductance behavior at realively high freq (on OrCad are around 200MHz), with the capacitances used and put in Matlab are even at more than 500MHz.I don't see a pole that can interfere with the opamp bandwidth, which is very limited for an LM324. According to my plans, I need to find the problematic pole and introducing a well shaped in-loop compensation. May be a journey of 1000 steps.But the first is... Where is my error?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 21, 2015, 09:36:39 am
content: Assuming ideal op-amps has led many a student astray.Real amps do not have zero output impedance, and only have rated gain at DC. The transfer function's dominant pole is quite low, in the 0.1 to 100Hz range for most types, so that the op-amp is largely an integrator in its useful range.Tim

author: thexeno
author_rank: Regular Contributor
timestamp: August 21, 2015, 10:52:12 am
content: Quote from: T3sl4co1l on August 21, 2015, 09:36:39 amI tried to make a TF including the Ad*Vd generator and the output resistance, but I've made some mistake... does not behave as you say. Even in PSPICE, that I made few months ago seem to be any issue. I will try again.But, conceptually, if the MOSFET have a pole out of the band of the opamp, at 0dB the MOSFET pole should not be reached yet. (?) And the phase margin should be high. (This neglecting what you just said, so what I said now is useless..)PS: without making a full transfer function analysis, I have serious problems in viewing poles and zeros, except for really simple circuits. And making a full transfer function is not so easy. So, this could be a problem.

author: dom0
author_rank: Super Contributor
timestamp: August 21, 2015, 02:46:05 pm
content: QuoteSPICE AC analysis will give you a bode plot.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: August 21, 2015, 02:48:14 pm
content: Hi thexeno and the group,I have done a little modelling to show how I would measure the loop gain of your circuit.Using your original schematic:The loop bandwidth is about 10 MHz and the phase margin is 35 degrees. In this configuration the op-amp gain is playing a part in determining the control loop bandwidth. You can see the slope of the gain line change from one pole (20db/decade) to two pole slope (40db/decade).If I modify the schematic by adding R1 and C1:The control loop becomes:The bandwidth is essentially independent of the op-amp, which is a good a thing, and the phase margin has been increased to 90 degrees.Note:In this circuit with such a large value of Rs, the current sense resistor there is no need for a resistor on the op-amp output. A small value resistor of between 10 Ohms and 100 Ohms will have no bad effects and may help some op-amps.Regards,Jay_Diddy_B

author: thexeno
author_rank: Regular Contributor
timestamp: August 21, 2015, 04:35:40 pm
content: @Jay:Many thanks. Really.You've performed an in loop compensation without adding a series resistor on the op amp output. I'd like to understand what you did, so I have 4 questions. Sorry for the amount of questions...1. You touched directly my problem: how did you choose the correct (or reasonable) values of the R and C??2. The second pole is given by the MOSFET, right? So with a more limited bandwidth of OPAMP (a more crappy one, let's say), the second pole should not reduce the phase margin anymore.3. The MOSFET values are random or calculated? Because the datasheet is giving the Ciss, and with such low current in MOSFET, the Gm should be less than one instead of 4. Am I right?4. Did you made a perturbation in the loop? The AC sweep is made in the loop instead to V2 and measuring the output?EDIT:Reding thishttp://www.analog.com/library/analogdialogue/archives/38-06/capacitive_loading.htmlI understand the bandwidth limitation to 160kHz, neglecting the output resistance of the opamp. I can't see the zero position, though.Just a note: may the ltc6244 be different from the LM324? In the picture is used a TL080, but I've specified that it is actually an LM324. I will try with an equivalent one from LT.EDIT1:Result with the LT1024 (limited at 1 MHz) -> phase margin around 100 degreeStrange

author: TerminalJack505
author_rank: Super Contributor
timestamp: August 23, 2015, 02:13:18 am
content: Quote from: thexeno on August 21, 2015, 04:35:40 pmThat's pretty strange, all right. I don't think that's what your plots are saying.Considering that the LT1024 is internally compensated to be stable at unity gain, you'll have a dominant pole at a low enough frequency so that you really only get 90 degrees of phase margin to play with. So an answer like 100 degrees definitely sounds strange. It looks like you have about 50 degrees of margin to me.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: August 23, 2015, 09:37:37 pm
content: Hi thexeno and the group,First I think that you are reading the results wrongly from the Bode Plot to arrive at 100 degrees.Let me show you experiments that I did in LTspice that help understand the circuit.Lets look at just the op-ampWith such a high value of Rs it is possible to operate this circuit without the MOSFET:I have set the voltage to 1V to get 10mA into Rs, this is within the capability of the op-amp.The results for a LT1014 op-amp (similar to LM324):The Loop BW is about 600 kHzAdd a POWER MOSFETNext I will add a IRF530 MOSFET, similar to the BUZ70:And the results are:The bandwidth is still 600kHz. The Phase margin is 45 degrees.Faster Op-Amp LTC6244HVIf I replace the op-amp with the LTC6244HV:No surprise, the circuit has more bandwidth:Introducing the RC networkIf I add R1 and C1, the bandwidth is reduced to 1/2 x Pi x RC = 159kHzThe results show that the bandwidth is around 160 kHz, so the bandwidth must be being controlled by the RC and not by the parameters of the op-amp:Adjusting the value of CI have set the model to step the value of C through a set of values:The results confirm that the circuit's bandwidth is being controlled by the RC network and not by the op-amp parameters (assuming the op-amp has sufficient bandwidth)Regards,Jay_Diddy_B

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: August 23, 2015, 09:53:34 pm
content: Hi group,Once we are satisfied with the response in the frequency domain, we can look at the transient performance. The loop is disturbed by adding a voltage source in series with the load.Without the RC NetworkThe results show that the control loop is stable but there is some ringing, an indication of a small phase margin.With the RC networkIf I introduce the RC network:The bandwidth is reduced, but there is no ringing indicating good phase margin.Regards,Jay_Diddy_B

author: TerminalJack505
author_rank: Super Contributor
timestamp: August 24, 2015, 12:41:57 am
content: , Jay.I always enjoy the Jay_Diddy_B workshops.

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: August 24, 2015, 01:01:31 am
content: Quote from: TerminalJack505 on August 24, 2015, 12:41:57 amThank you for your kind words !!Feedback is good !!Jay_Diddy_B

author: T3sl4co1l
author_rank: Super Contributor
timestamp: August 24, 2015, 01:15:56 am
content: Now:You can clearly see that trading gain for phase margin is a cruel compromise indeed. Surely it doesn't need to be so bad.It doesn't!If we note where the dominant (HF) pole in the loop lies, we can strategically place a zero at that point, to cancel it out and significantly improve phase margin.Suppose the "uncompensated" circuit has a pole at 5MHz, due to MOSFET capacitance versus op-amp output impedance.Such a pole has 45 degree phase shift and 3dB attenuation at 5MHz, so if the op-amp itself has 3dB gain at that frequency, the phase margin is what's left, 45 degrees.If we keep pushing the op-amp's dominant pole down, by adding a series -in resistor and cap from -in to out, we can push below that loop pole until phase margin is satisfactory again. But this requires a factor of 3-10x to achieve.If we instead add a resistor in series with that capacitor, then we still have the dominant pole behavior of the op-amp, but we add a zero at Cpole*Rseries, so that the gain remains flat until Cpole*Rzero, and the phase shift goes away.In the above circuit, if we use about R1 = 1k, C1 = 1n, and add a resistor in series with C1 of 100-1000 ohms, we should get much the same effect, but at nearly full bandwidth, quite a savings!Tim

author: Jay_Diddy_B
author_rank: Super Contributor
timestamp: August 24, 2015, 01:38:05 am
content: Hi,Tim raises an interesting point, since I have the models handy lets have a look at adding a zero. This is done by adding a resistor in series with the capacitor:Transient AnalysisFirst with the LTC6244 op-ampYou can see that the current settles to faster with a 1K resistor in series with the capacitor. You can see the effect of the zero.With the LT1014 (GBW = 1 MHz)The effect of the zero is less dramatic. The gain is constrained by the op-amp GBW.AC AnalysisFirst with the LTC6244HV (GBW = 50 MHz)Now with the LT1014 slower op-ampYou see that the effect of the zero is last dramatic. The op-amp is parameters are playing a part in the circuit performance.In general you want the circuit behaviour to be determined by the passive components and not op-amp parameters.Jay_Diddy_B

author: thexeno
author_rank: Regular Contributor
timestamp: August 28, 2015, 09:11:19 pm
content: Thanks Jay!Let me confirm if I've understood correctly with a dumb question: with this "in-loop" compensation, can I devise the Transfer Function for what concerns the "in-loop" compensation only? I've just made the equivalent circuit assuming that I can add this result to the final circuit in the outer main loop. So the compensation provides something like V'/Vi = - 1/(s*R1*C1) (the gain of the inverting configuration) where the final transfer function (on the shunt resistor) is the sum with the "uncompensated" and this "in-loop" compensation (represented by V'). Of course, if the in-loop TF has a lower bandwidth, thus represents the actual (reduced) system bandwidth, as you have shown.@Tim: thanks to you too... Can you explain with a formula or graph what you are saying? Because in my circuit there is the second pole due to the capacitive load that provides a -40db/dec near to the 0dB, reducing the phase margin. Why not introduce a zero at that frequency, in order to keep the -20db/dec? As you can understand, without a graph/math is not "easy" to understand to me.To everyone: I've tried with sense resistor of 3.3Ohm, so very low.Using LTSpice I've found a margin phase of 40° without compensation, but the real circuit with the opamp powered with the high voltage (from 8 to 12V) and the led with 5V, oscillates (it does not oscillates if everything is powered at 12V). Using LTSpice with 10nF and with a compensation resistor of 0 Ohm (so, no R) I have a phase margin of 10° and in reality provides only ringing. Using LTSpice with 10nF and 96Ohm, I have PM of 80° and the real circuit is beauty.So,except for the first case, the reality (more or less....) is coherent. It seems that I still don't need an output resistor on the Op-amp output. And from LTspice increasing too much the output resistor will introduce instability.

author: thexeno
author_rank: Regular Contributor
timestamp: December 20, 2015, 02:24:15 pm
content: I changed the MOS from BUZ70 to IRLI630GPBF. The compensation (100ohm and 10nF) does not work anymore. I think because the pole introduced was at 160kHz, while the BUZ was oscillating at 200kHz. My assumption is because the IRL now oscillates at 100kHz and therefore is not filtered out, but seems strange to me the need to slow down even more the circuit. Is there a way to know a priori how and how much to compensate? Only simulation is possible?Moreover, what is bothering me (using the BUZ70), is *why* even though I have phase margin higher than 40° without compensation (using simulations), in certain conditions (certain values of the input voltage) it oscillates a bit, order of 0.5V at maximum.

author: Kevin.D
author_rank: Frequent Contributor
timestamp: December 20, 2015, 07:28:25 pm
content: Quote from: thexeno on December 20, 2015, 02:24:15 pmwhere is your circuit? or which circuit from the above are you referring to ? Post the spice asc file of your circuit and it will be much easier to help you.So this is telling you the gate pole has moved down in freq because of larger input capacitance (Ciss) of the irli630 fet.Quote from: thexeno on December 20, 2015, 02:24:15 pmA loop will oscillate at it's crossover frequency (that is when loop gain = 1) which is now ata lower Freq due extra roll off caused by this earlier gate pole.Quote from: thexeno on December 20, 2015, 02:24:15 pmNo not with any accuracy anyway because the parameters you need to work out freq of poles are not always readily available in data sheet (e.g Zout of op's), but you can always estimate it and 'add some' for a safety margin if you have a previous experience with the type of circuit. At the end of the day it's much simpler and more accurate to simulate or build it and then measure so avoiding all the math/guesswork. Another thing to consider is that it's much simpler to compensate and optimize a loop for a known fixed load, rather than doing one that can handle a wide range of loads, because the load value/type shifts the position of some of the poles which means you then have to compensate for a worse case load scenario which is not going to be optimum for all loads.Quote from: thexeno on December 20, 2015, 02:24:15 pmThe gate pole here is created by Rgate (which includes the Zout of op + gate resistor) and the Ciss of mosfet (which consists of Cgd + Cgs ) .The Cgd part of that can make a very large difference (even though it's initially smaller than Cgs) because it's 'apparent' size is varied by two thing's here .1/ Cgd of fets gets larger with smaller Vds (can increase by upto 10X for very low Vds from that given in the data sheet which is the value at some medium Vds condition. This is probably why there is some oscillation when you reduce Vcc (thus reduce Vds-->increase Cgd and move gate pole down).2/ Cgd size also appears multiplied by the gain at the drain (miller effect). So here we can see transistor will form a typical common source amp configuration. And you know your basic common source amplifier when both drain and source resistor are present then gain formula is Rd/Rs. Here Rd will be your Rload (since it's in the drain) and Rs is your Rsense (it's in the source). This shows you that for Very large value of Rload (thus large gain at drain) the gate pole moves down lower due to Cgd increase in apparent size. A mosfets 100pF Cgd can easily appear as large as a 100nF on the gate due to combination of effects I have described here.Regards .

author: thexeno
author_rank: Regular Contributor
timestamp: December 20, 2015, 08:20:00 pm
content: I will digest better you answer tomorrow. In the meantime...Quote from: Kevin.DI'm agree. But I feel that a person that do this for job (because I want to pick the correct way of doing things) will use some math, it is still engineering/science, a lot explained on books etc, am I wrong? I don't want to abuse either of math nor simulations/empirical experience. (I am a fresh electronic engineer, digital oriented to be precise, and I may have saw a lot of math overhead(abuse?). For this reason I am use to take often the math way, even if it is more complicatedbut often hitting the head on a wall and going nowhere, for the same reason)PS: thanks for the answer

author: dom0
author_rank: Super Contributor
timestamp: December 20, 2015, 09:35:07 pm
content: IRLI630GPBF has more than three times the typical input capacitance of the BUZ70, so it's not surprising your circuit oscillates now.Bode plot analysis is what can be used for this. You can take the 1st pole of the op amp from the open loop plot, or calculate it from GBWP and DC open loop gain (seehttps://www.eevblog.com/forum/beginners/op-amp-basics-clarification/msg820749/#msg820749). Or you just copy the open loop response from the data sheet to your bode sheet. Then draw up the RC low pass formed from gate + open loop impedance driving it (can measure it closed-loop, take it from datasheet if specified, sometimes from equivalent schematic, when the emitter resistors' values are specified these are the dominant impedance for the output impedance). Draw your feedback network on the bode sheet. Add the curves. Tadaa, loop gain bode plot. Of course only an approximation. When the data collected is conclusive a good one, good enough for determining compensation network. A nice exercise for any EE student.In practice you'll just work it out by making an educated guess and working from there. For slow stuff a resistor decade is very nice for this, ideally coupled with a capacitance decade. Adjust until idealtype step response is reached. Consider stray influences (which will be specified for any reputable decade), round to nearest Exx values. Solder them in. Verify step response. This works well for control loops up to a few hundred kHz, maybe a couple MHz, but beyond that the additional inductance from connecting leads degrades performance significantly.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 21, 2015, 01:44:39 pm
content: Circuit stability varies with voltage because gate and drain capacitances vary with voltage. Semiconductors are very nonlinear; the drain capacitance typically varies by several orders of magnitude between 0V and rated voltage.Tim

author: thexeno
author_rank: Regular Contributor
timestamp: December 22, 2015, 10:02:13 pm
content: Before answering better to everyone, I'd like to say that the cirucit is completely stable, or it seems to be, with compensation used with the BUZ70 and100uF cap on power rails(100uF because I had this one only...).

author: thexeno
author_rank: Regular Contributor
timestamp: January 03, 2016, 10:15:12 pm
content: Quote from: Kevin.D on December 20, 2015, 07:28:25 pmQuote from: Jay_Diddy_B on August 21, 2015, 02:48:14 pmKevin, that is my circuit with the new mosfet (IRLI630GPBF). I don't have a full simulation because I don't know what is an equivalent mosfet to mine, and IRLI630GPBF is not present in LT-Spice.Did I answered to you?Let's add that the compensation used is 100ohm and 10nF, because with the BUZ70 the one used in the simulation above did not remove the oscillations. I don't know if this is somehow related to the fact that with the IRLI630GPBF and a tank capacitor on Vdd the stability is achieved.Happy new year

author: thexeno
author_rank: Regular Contributor
timestamp: February 14, 2016, 10:16:41 am
content: Hi! It's been a while, now I can appreciate more your answers. I refreshed my mind!I read again all the topic, the Dynamic electronic load project, a couple of books...Quote from: dom0 on December 20, 2015, 09:35:07 pmI still have troubles in discerning the concept of loop gain with the feedback network. In other words, what do you mean with:Quote from: dom0 on December 20, 2015, 09:35:07 pmWhy does not the feedback network is actually the loop gain?Quote from: thexeno on December 22, 2015, 10:02:13 pmAnswering to myself, this was a counter measure to the lead inductance present on the drain. Demonstrating that the oscillation was due to inductance and not at all (right?) with the lower pole in the feedback due to the fat MOSFET.I am still in the dark to know how a parasitic inductance and any stuff placed on drain can caffect the system. Does it depends on the transconductance gain of the mosfet, which contains the Rd/Rs terms under the degenerated common source configuration?Personal note: I am a bit unsatisfied with this circuit because I started it as an exercise to try to find the pole, compensate, draw pole and zeros on complex plane ecc, but I almost instantly being stucked by the fact that the main pole is due to a parameter difficult to know: the Rout of the op-amp.

author: dom0
author_rank: Super Contributor
timestamp: February 14, 2016, 11:00:53 am
content: QuoteLoop gain is the gain a disturbance experiences when it "travels around the loop once". So you need to take amplifier transfer function into account. That's why you need to add the curves of the op amp, the feedback network and that low pass. This is then the loop gain.

author: thexeno
author_rank: Regular Contributor
timestamp: February 14, 2016, 03:00:31 pm
content: Quote from: dom0 on February 14, 2016, 11:00:53 amI'd like to proceed in this way, like learned at university for simpler and famous configurations. Here seems not possible to find the transfer function of the feedback, mainly because the more important pole depends on opamp's Rout.I triedherefew calculations and assumptions, that could be wrong.

author: thexeno
author_rank: Regular Contributor
timestamp: February 14, 2016, 11:31:10 pm
content: Some news and results.This is the real circuit, with BUZ70 with no compensation, Val = 8V for opamp and MOS:and inserting C=10nF, R=100ohm became:The circuit was made on a 2layer PCB:The blue resistor and the cap are the compensations. The others are pulldown on opamp input and the sense resistor, which is 4.7ohm. The MOSFET is BUZ70.I don't know why, but using 1000ohm resistor and 1nF will oscillate even more.Now,with a new circuit which uses the "fatter" MOSFET IRLI630, uses also a resistor of 0.47ohm because the input also is 10 times lower. I don't have screens of the oscillations, but here what happens:with the compensation like with the BUZ70, does not work, it is very noisy at 12V and oscillate up to saturation under 12V.Insertinga 100uF electrolytic cap on Val, works well at 12V, became noisy at 5V and at 3.3V there is a ringing even greater than the one in picture before, at around 100kHz.Then I tried with pole-zero compensation at 100kHz (between + and - of opamp), changes only a bit. Increasing with dominant pole by putting R=200ohm and not using zero-pole, therefore around 80MHz, it does not change anything. Using both solutions make the condition worst. I know, the inductance could be present on voltage lines, and the power supply is a PC's PSU, noisy, but my control loop is somewhat still unstable.The requirement I'm looking for is high speed (between 150 and 200kHz at least) and a current precision which can be inside 5%.Here in this forum are supported also projects, if I can be helped to going out from this stuck condition, I can start a new topic about it, and provide updates, if it worth. It is a 4 colour lamp, driven with 4 PWM channels from a micro, which I'd like to make in switching version (I am currently working on it) and a linear one, which could be used to modulate signals (here why the precision and frequency initial requirements).