Do any SPI chips clock data in on a +ve clk edge, but require clk parked at 1? - Page 1
Forum section: electronics / general

author: peter-h
author_rank: Super Contributor
timestamp: April 25, 2025, 12:34:48 pm
content: It would seem to be a weird sort of logic design to really require that.It is SPI Mode 3.In recent years I have done code for various SPI chips and never found this was needed, and Mode 0 was just fine.

author: jpanhalt
author_rank: Super Contributor
timestamp: April 25, 2025, 01:44:45 pm
content: I don't have much experience, but in one instance I used mode 3. I like the ST75xx displays (e.g., ST7525 and ST7576). They are fast enough for my needs, and I am comfortable with them. In my experience, they work with modes 0,2, and 3, but not mode 1. MCU is an enhanced mid-range PIC 16F1xxx at 8 MHz or 16 MHz usually.In a recent project, I used the MAX31856 TC amplifier. That worked with modes 1 & 3 only, so I ended up using mode 3.I have not seem any device that only works on mode 3.

author: peter-h
author_rank: Super Contributor
timestamp: April 25, 2025, 02:15:58 pm
content: ST7525 is a great example of what I believe must be a BS data sheet:Same with STLED316:How can the clock parked HIGH be possibly relevant? It "must" also work in Mode 0. The STLED316 definitely runs fine with Mode 0. In fact if using Mode 3 for it, I found that mucks up some other devices on the same SPI, although that it almost certainly an artefact of re-initialising the STM 32F4 SPI between devices (it doesn't like it much).

author: jwet
author_rank: Frequent Contributor
timestamp: April 25, 2025, 04:27:40 pm
content: Over the years, I think all permutations of CPHA and CPOL have been used. In a lot of cases, its a don't care since the clock is edge triggered and the resting state doesn't really matter. True SPI will operate in mode 0 but these synchronous ports on micros have to support a lot of non standard stuff. If you look at shiift registers, '299 or '595- they can be odd. National "microwire" is SPI adjacent but not consistent- it also has active high CS. Dallas DS1620 and other parts have a odd SPI like interface with clock and a combined data I/O. Sometimes there's an extra inversion involved like going across an opto-coupler barrier and its convenient to untangle it in software. Maxim made ADC's and DAC's that had varying CPA and CPOL before things got relatively standardized. The MAX512/3 DAC's had an odd SPI like interface. Standards aren't so standard.

author: IDEngineer
author_rank: Super Contributor
timestamp: May 02, 2025, 01:21:30 pm
content: In other words: "The nice thing about standards is there are so many different ones to choose from."

author: peter-h
author_rank: Super Contributor
timestamp: May 05, 2025, 05:46:22 am
content: I agree with all this but find it hard to visualise a circuit which needs CLK=1 to start with, yet clocks the data on the +ve CLK edge.

author: SiliconWizard
author_rank: Super Contributor
timestamp: May 05, 2025, 01:02:42 pm
content: There can be a number of reasons why one would prefer a "idle" high level for the clock in a given context, for instance for the slave to distinguish between "currently not clocking" and "no master present".Some slaves could use a low level longer than a given period as a "reset" signal.Like UARTs usually have a high level as idle level.Can also accomodate cases where the clock is pulled up and shared, like with... I2C.Which, incidentally, may make you notice that a number of slave devices that implement both SPI and I2C on the same pins choose this SPI mode. Probably simplifies the internal logic.So, in the end you have 4 modes, and all of them can be justified in a given context.Now, yes, many datasheets are notoriously bad or at least ambiguous at properly showing which SPI mode you should pick and it's an almost endless source of headaches for firmware developers.Their timing diagrams are often shitty.

author: mikerj
author_rank: Super Contributor
timestamp: May 05, 2025, 09:55:40 pm
content: Quote from: SiliconWizard on May 05, 2025, 01:02:42 pmThat has been a source of frustration for me for so many years, often the timing diagram makes it very ambiguous with nothing in the description to back it up. Since the four possible modes are well defined it seems crazy not to explicitly state the applicable modes, and the datasheets that do seem to be the exception.

author: langwadt
author_rank: Super Contributor
timestamp: May 05, 2025, 10:21:39 pm
content: Quote from: mikerj on May 05, 2025, 09:55:40 pmthe four modes might be well defined but SPI is not a formal standard