clock divider circuits / how would you design them without just copying? - Page 1
Forum section: electronics / general

author: dentaku
author_rank: Frequent Contributor
timestamp: December 30, 2020, 02:53:55 am
content: I've been looking at websites describing different methods for dividing a clock signal using DFlip-Flops and a few gates and I can simply copy the circuits, simulate them and it works.What is often missing in tutorials and videos is what methods can be used to create these circuits yourself.What are the common methods people useto come up with a solution to making a divide by 3 or 5 for example, without just copying someone else's design.I understand how to do this in Verilog by incrementing a counter and inverting a value when the counter reaches a certain number and the logic circuits I've found are also easy enough to understand because I'm more of a hardware person anyway.I just want to know how someone would come up with these schematics without looking at an example.I've used tools that let you input a truth table and it creates a schematic for you but that's not useful when there's a clock involved, like in a divider circuit.

author: BrianHG
author_rank: Super Contributor
timestamp: December 30, 2020, 03:59:29 am
content: Quote from: dentaku on December 30, 2020, 02:53:55 amDo you mean looking into the 74LSxxx dataheets for flipflops, counters and gates to design a clock divider yourself?Yes, in Verilog, I would just make a down counter which resets to a chosen number every time it reaches 1. This would give me a divide by any number. When it reaches 1, that 1 would be an 'enable' for the logic I wish to operate at a programmable dividable speed from 1, 2, 3, ect...

author: radiolistener
author_rank: Super Contributor
timestamp: December 30, 2020, 04:28:05 am
content: Quote from: dentaku on December 30, 2020, 02:53:55 amif you want to multiply/divide clock, use PLL for that. It allows to adjust phase and duty cycle. Do not use counters to generate clock.

author: BrianHG
author_rank: Super Contributor
timestamp: December 30, 2020, 06:13:59 am
content: Quote from: radiolistener on December 30, 2020, 04:28:05 amYes, if your are targeting a specific phase relationship, PLL have their phase comparitors specified out and are engineered to deal with phase angle timing. Also, you can virtually guarantee a 50/50 duty cycle on your output clock.

author: hamster_nz
author_rank: Super Contributor
timestamp: December 30, 2020, 06:34:39 am
content: If it is for the internals of an FPGA design you should use a PLL. Or replace tha 100MHz oscillator with. 33.3MHz one.If you can't then you should use a clock enable. This is the best practice if you can still meet timing. Even with a 100MHz/10ns clock that still allows for lots of levels of logic.Can you use a shift register and route the output to a clock buffer? Do you really need 50% duty cycle, especially if all your logic uses the same clock edge?If it is for external signals then use a DDR register or serializer to generate the signal (but this usually requires use of a PLL anyway....)

author: Moshly
author_rank: Regular Contributor
timestamp: December 30, 2020, 08:04:36 am
content: The answer to this question is 'it depends'I suggest this book >Digital Systems Principles and Applications, Ronald J. Tocci.It was my textbook for trade school in the early 90's. I have the fourth edition and it has ~70 pages (whole of chapter 7) just on counters however the 10/11th edition online has nothing (its only ~200 total pages ?, 4th is ~800).Google for the 8th edition, it has most of the info from the fourth ed.

author: dentaku
author_rank: Frequent Contributor
timestamp: December 31, 2020, 01:51:36 am
content: Yes, making a down-counter, as people have said, is the easiest and most practical way to give you any frequency so thanks for that information.I have found how to create different clocks in Quartus using the PLL mega-wizard (or whatever it's called) but that that still gives you clocks in the MHz range.I guess what I'm asking is something I saw in a video where she creates a div2 and a div5 then combines them to create a 1Hz clock from a 50MHz clock.https://youtu.be/_rga7pG2yLc?t=546It looks quite impractical/tedious and uses a whole bunch of flip-flops. While it's interesting, what I'd like to know is the process she went through to create the div5 circuit.In this video she just says they did it in a previous video but I can't find which one that is.Are thereterms I should be searching forto find more information on designing digital logic circuits in a more organized "logical" way?In the video I see a State Table but that seems to have to have been discussed in a different lesson.

author: dentaku
author_rank: Frequent Contributor
timestamp: December 31, 2020, 01:52:25 am
content: Quote from: Moshly on December 30, 2020, 08:04:36 amI just took a quick look at chapter 7 and it's full of useful looking stuff.

author: miken
author_rank: Regular Contributor
timestamp: December 31, 2020, 05:57:20 am
content: There was a time where you would simply use the available TTL/CMOS family chip. 74'90, 74'390, for example are made up of a divide by 2 and a divide by 5. You can see what the logic actually looks like in the datasheet.As for how to design it, well, they were implemented as counters, and a counter is just a kind of state machine. With 10 states, a BCD counter might be a little tedious to design by hand but it could be done. The interesting (?) part would be reducing the logic to the bare minimum.As for learning to design, in general, some of these things just come with experience. All of us have cribbed designs from others, to varying degrees, and in days past there were "cookbooks" full of circuits to copy from. Seeing and understanding how things are done builds up your own intuition.

author: NorthGuy
author_rank: Super Contributor
timestamp: December 31, 2020, 04:34:00 pm
content: Quote from: dentaku on December 30, 2020, 02:53:55 amObviously, you cannot do this once you looked at the example. You have already looked, so now you cannot design the schematicswithout looking. Never.So, the recipe is very simple: Don't look at the examples. Think for yourself.

author: SiliconWizard
author_rank: Super Contributor
timestamp: December 31, 2020, 05:35:50 pm
content: Quote from: dentaku on December 30, 2020, 02:53:55 amI'm assuming you want to learn how to deisign clock dividers directly from logic gates.(Otherwise yes, using a HDL you can use counters, which are easy to describe, and either comparators if the dividing factor is not a power of two, or just directly use the corresponding bit of the counter if the dividing factor is a power of two. Done.)For that, what you basically need to learn is how to design counters from flip-flops. It's really basic knowledge and you'll find this pretty easily. Then you will possibly need to learn how to design comparators (again if the factor is not a power of two, otherwise that's useless.) If you don't know where to start, I'm sure Wikipedia has articles for both, although getting yourself a good book about digital logic would be a good idea.As a side note, if you're considering implementations on FPGAs - whatever approach you use, schematics or HDL - you need to be careful with such hand-implemented dividers. In most cases, their output can't properly drive internal clock distribution trees, so the timing results will be pretty poor. This has been discussed several times in other threads, so I suggest searching the forum for this particular topic if you're interested.