4-layer PDN performing worse than 1-layer - Page 1
Forum section: electronics / projects

author: jmw
author_rank: Frequent Contributor
timestamp: February 19, 2023, 10:04:48 pm
content: I'm testing my shunt-through PDN impedance analysis setup, first with a 100 nF capacitor. My test board has two SMA connectors close together, and footprints for capacitors at varying distances. There are a few test coupons that are isolated from each other, with this 4-layer stackup:1. power + ground2. ground== core ==3. power ("power" really means the center pin connection of the coax)4. groundOne of the test coupons has copper only on the top layer and everything voided underneath, another has all the planes stitched to their respective nets. This is what I got when I calculated the impedance from the spectrum analyzer output:At first this looks about right. For 100 nF, most manufacturer data has the SRF at 20-30 MHz and 30-50 mΩ ESR. But then notice the test with ground and power planes has higher ESR and lower SRF. This result is consistent with the 4-layer coupon having more inductance. How is that possible? The same top-layer return path is available, so the underlying planes should offer lower impedance and certainly be no worse!Below is the PCB layout. I'm only using the closest 0603 footprint. They're identical except for the vias connecting to the planes. I suspected *maybe* there could be a poor connection with the center pin and the via-in-pad, so I filled it level with solder — no change. I checked the PCB was actually constructed as designed and also tested with two board samples, same result.I'm stumped — any ideas?

author: moffy
author_rank: Super Contributor
timestamp: February 19, 2023, 10:35:46 pm
content: Perhaps the EM fields from the top are coupling into the other layers and inducing eddy currents and increasing your losses?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 20, 2023, 12:27:24 am
content: Show layer 3, and the exact component placement (there aren't any silk labels on here so I can only guess it's the cap between connectors??).Tim

author: jmw
author_rank: Frequent Contributor
timestamp: February 20, 2023, 01:00:38 am
content: Tim - these are the plane layers. Green = layer 2/ground, Red = layer 3/power. You know Altium; plane layers are in the negative. I made the fills a bit transparent and left the top silk a little visible so you visually correlate to the other pics.Yeah, the 0603 component between the two connectors at the left is the only thing placed right now.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 20, 2023, 01:41:36 am
content: This is all one board, just different layouts by region?So the "ground only" has a completely empty layer 3? Nothing goes through the board of course, it's all on top (and mid1; and bottom I guess but kinda doesn't matter)?Also those were two different capacitors? The left half of the plot follows when you swap them around, right?Just as a hand-wave possible explanation (hard to say much quantitative around complex geometry like this), it could be the thermal relief, too much via density, or just the sneak path through the middle of the board (think of it as two inductive paths in parallel, only one of which has the cap in the middle).Planes in Altium kinda suck; I'd recommend using pours, for better control over connection (set vias to no thermals for one), and clearance. (You can set total clearance as the sum of annular ring plus clearance on that layer -- the annulus is removed on output generation. Do keep the clearance modestly high to allow for drilling + layer registration tolerances, but it can usually be a bit less than for the sorta naive (Simple pad stack) case.)Huh, is there really nothing at the far end of that long trace, no connector footprint or anything, just all caps? Was the experiment in part to see what effect a stub has on the response..?Tim

author: jmw
author_rank: Frequent Contributor
timestamp: February 20, 2023, 02:38:51 am
content: Quote from: T3sl4co1l on February 20, 2023, 01:41:36 amYes, single board with separated regions. The keep-out border between regions is 20 mil wide.Quote from: T3sl4co1l on February 20, 2023, 01:41:36 amThat's right, the region labeled "top layer and ground pour only" has no layer 2, 3, or 4. Everything's happening on the top layer.Quote from: T3sl4co1l on February 20, 2023, 01:41:36 amCorrect, they're 2 different caps, and I move the connectors around to take measurements. I did try reworking the caps to see if it was part variation, and I also did the experiment on two boards. Results don't change.Quote from: T3sl4co1l on February 20, 2023, 01:41:36 amHmm, I don't think it's a manufacturing failure or such. I filed away the edge of the board to peek at the inner layers. Copper is where it's supposed to be, and I set my rules so as to not at all challenge JLCPCB's clearance minimums. I could be down for removing the via thermal reliefs, but without reliefs on on the SMD pads, rework is going to be a pain.What could be a sneak path through the board? The only other path I can spot is the interplane capacitance between layers 3 & 4. That's on the 100 pF range, too small to budge the chart.It's all just capacitor footprints, so as to study what it's like on 2- and 4-layer boards to have bypass and bulk capacitors at various distances. I suppose in the 4-layer coupon, connection via a trace on top isn't necessary; though, is there a bright line between a stub and unused copper in a big pour or plane? After all, for a shunt-through measurement, the network between the two connectors is nowhere close to 50 Ω characteristic impedance.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: February 20, 2023, 05:41:13 am
content: Oh right no layer 2 even, so you're just measuring the inductance of that narrow gap on the top layer, the clearance between signal and GND.No not a manufacturing thing, I mean the amount of copper lost to the thermals plus the vias being that closely spaced, look at the negative space in the GND and power planes. It may be better with the vias a bit further apart, to leave more room for the power plane to fill.By sneak path I mean the signal can go over the top by the cap, AND through the inner plane without a cap. I don't know that I'd want to assume component values and an equivalent circuit here, but it does seem like an inductive link between input and output, across the LCL path on top, may have explanatory value.Tim