Multiplexing a Large Number of Digital Signals - Page 1
Forum section: electronics / projects

author: Poorly Calculated
author_rank: Contributor
timestamp: October 13, 2020, 12:53:44 am
content: Being a 4th year in college majoring in EE, I am taking a capstone course (Senior Design 1). We have settled on a project, and are trying to think of a way to deal with a large number of digital signals. We will have over 150 sensors that spit out a logic 1 or 0. I attached a "Proof of Concept" circuit that we are using to generate these 1's and 0's. We are looking for an elegant way to implement a system that deals with all of these signals. We need advice. Also maybe some criticism of that circuit? Any and all help would be awesome.

author: Miti
author_rank: Super Contributor
timestamp: October 13, 2020, 01:33:29 am
content: Quote from: Poorly Calculated on October 13, 2020, 12:53:44 amWhat do you do with those signals? Do you process them, store them or just multiplex them?An FPGA would be the best way to go IMHO.Edit: Maybe two FPGAs, one to generate the signals and one to multiplex them.

author: srb1954
author_rank: Super Contributor
timestamp: October 13, 2020, 01:37:34 am
content: Quote from: Poorly Calculated on October 13, 2020, 12:53:44 amYou should be aware that standard opto-couplers can be be relatively slow so you need to consider the required response time. You also need to put some hysteresis on your comparator to prevent oscillations when the input signal slowly transitions through the threshold voltage of the comparatorSince you are looking at 150 inputs multiplying this circuitry 150x adds up to quite a bit of PCB real estate.There are much better options available these days than individual opto-couplers and conditioning circutry. Search for "digital isolators". These are available with multiple isolators per package, operate at higher speeds than typical opto-coupler based circuits, consume less power and don't degrade over time as opto-couplers do.Finally, when drawing schematics you should avoid having a 4-way junction as shown for your common connection. When the diagram is printed the connection dot can sometimes be indistinct making it unclear whether there is meant to be a connection or not thus causing confusion between intended junctions and normal wire cross-overs.

author: Poorly Calculated
author_rank: Contributor
timestamp: October 13, 2020, 02:13:39 am
content: Sorry, I did not make it clear as to what that "optocoupler" is. It is actually an infrared laser aligned with that phototransistor! I will have to look into how to prevent hysteresis on that output. I will worry about PCBs next semester when we actually build this thing. As for that schematic, that's my bad on the poor layout. Our university uses this relic of the past called CircuitMaker2000, and it can be inconsistent with making dots. Still, that's my bad.

author: Poorly Calculated
author_rank: Contributor
timestamp: October 13, 2020, 02:16:52 am
content: We want to process the data. We were required to use a Basys 3 board from Digilent that has the Artix 7 FPGA, and we used verilog to code on it. So, between the 4 of us in the team, we have 4 of those boards.

author: BrianHG
author_rank: Super Contributor
timestamp: October 13, 2020, 02:42:45 am
content: Use multiple 74HC589s. They will take in 8 bit parallel and shift out 1 bit serial with 3 control signals, 1 shift and 1 data, and shift-load signal.Depending on your speed needs, you can use these chips individually sharing the first 2 control signals + 1 extra serial bit per chip making your # of source signals divide by 8.But these chips also support daisy chaining so you may divide your source signals by 16, or 24, or 32. So if your scan only needs to be at ~1MHz, then using 4 at a time linked together will divide your 150 signals into 5 data bits + 2 control signals.Your limit will be the clocking speed limit of the 74HC589 which is at 30MHz. If you still want, a small PLD or FPGA can load and address the scanned serial streams coming in parallel non-stop in saving a boat load of IOs while on the other side provide an addressed type of port with other functions like fire an interupt on change state of any of the 150 bits.Configuring the system to 16bits and using 10data bits + 2 = 12 io on a small 64 pin FPGA/PLD will leave you enough on the other side to address everything while running the serial chips at a comfortable 16MHz for a 1MHz bandwidth.

author: Poorly Calculated
author_rank: Contributor
timestamp: October 13, 2020, 03:19:16 am
content: Thanks for the advice BrianHG, I will look into that part.

author: BrianHG
author_rank: Super Contributor
timestamp: October 13, 2020, 04:21:24 am
content: Quote from: edavid on October 13, 2020, 04:13:58 am4-12 IOs on an FPGA or MCU instead of 150 IOs or 28 IOs on an FPGA or MCU. Also no 19 parallel output enables and massive parallel PCB complex wiring.

author: srb1954
author_rank: Super Contributor
timestamp: October 13, 2020, 04:29:30 am
content: Quote from: Poorly Calculated on October 13, 2020, 02:13:39 amThe comments on opto-couplers still mostly apply to separate LEDs and photo-transistors.In addition to the normal opto-coupler problems you will also have to deal with variability of the current transfer ratio due to alignment between the emitter and the sensor as well as the normal photo-transistor gain variations.

author: Poorly Calculated
author_rank: Contributor
timestamp: October 13, 2020, 04:50:52 am
content: Quote from: edavid on October 13, 2020, 04:11:02 amWe understand the impracticalities of this issue, but what we need is a system to get these signals to the FPGA.

author: Poorly Calculated
author_rank: Contributor
timestamp: October 13, 2020, 04:53:14 am
content: Quote from: srb1954 on October 13, 2020, 04:29:30 amThat is true, we will need to implement a very robust mounting system such that the alignment is as good as possible.

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 13, 2020, 05:21:13 am
content: The laser is a relatively powerful source (even those cheap red pointer modules), you'll get better results using photodiodes instead.What kind of bandwidth do you actually need, as in how often do the sensors have to be sampled? That will make a huge difference on what makes the most sense for combining the inputs onto a bus.I'm getting the impression they're trying to build a laser harp or similar.

author: Nominal Animal
author_rank: Super Contributor
timestamp: October 13, 2020, 06:49:43 am
content: Quote from: edavid on October 13, 2020, 04:27:58 amEdit: Right, for eight 'trees' of 19 inputs each.That needs e.g. three 8-to-1 and one 3-to 1 demultiplexer, or five 4-to-1 and one 5-to-1 demultiplexer, per input.In total, 24 8-to-1 and 8 3-to-1 demultiplexers, or forty 4-to-1 and eight 5-to-1 demultiplexers.Here are the first two trees out of eight (i.e., this is one fourth):Using just one input line, you need 3+3+2 = 8 address lines, so 9 total.Each set of 64 inputs uses 9 demux chips, with 6 address lines. (Eight are on the outer edge, with their three address lines in parallel. The ninth one is connected to the eight outputs, using the three other address lines.)For 150 inputs, you need three of those sets (giving 192 inputs, so you can omit five of the demux chips), with the address lines in parallel. Then, you need an additional 3-to-1 demultiplexer between the sets, using additional two address lines. In total, you need 23 8-to-1 multiplexer chips, or 19 8-to1 and 5 4-to-1 or 3-to-1 demultiplexers.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 13, 2020, 07:27:52 am
content: First of all, evaluate your opto-electronic system to ensure you have an adequate guard band based design.For the weakest laser, with the worst case alignment, with the poorest opto (whether photodiode or phototransistor, it doesn't matter just yet), and the poorest components in circuit -- will you still get a valid logic 1/0 at the mechanical or optical thresholds needed?An easy example is a commercial optointerrupter. This is a component with an IR LED installed in one leg, and a phototransistor (usually) in the other. The phototransistor is usually filtered from ambient light, and sits behind an aperture which casts a shadow from everything but the photodiode. The optos may be molded in, or discrete components. They usually have internal lenses to give a narrow viewing angle.The CTR of this device may be around 2-10%. That is, for say If = 10mA in the LED, 0.2 to 1.0mA can flow through the phototransistor. The CTR is usually relatively poor, on account of the longer and thinner optical path compared to an optoisolator (which usually does around 100%). The maximum off-state leakage (that is, If = 0, in some level of ambient light, Ta = 25°C) might be 10uA or so.Thus, if we power the LED at 10mA, we have a logic-zero of at least 0.02mA, and less than 0.2mA. This is our guard band. If we compare the phototransistor current to a load current in this range, we will have good confidence in our reading. The load can be a current source (which might have some modest precision, 10% is easily done). We can even use a resistor, in which case the current is converted to a voltage, and we need to compare the voltage to our digital logic voltages. Typical CMOS inputs are themselves guard-banded in the 0.3-0.7 Vcc range. This spread is less than our CTR spread (10x), so we are able to choose a resistor that will work. Namely, (0.7 Vcc) / (0.2mA) = 11kohms, to (0.3 Vcc) / (0.02mA) = 49kohms (at 3.3V supply).Of course this will be harder to define for an optical geometry subject to mechanical tolerances; but once you have that, you can put it into the system in just the same way, and solve for the load resistance (or CCS if the guard band is narrower than a resistor can do).And to findthat, you can do statistics, you can go through and calculate all the worst-case geometries (maybe 3D CAD can automate some of this for you?), or you can avoid it entirely by putting in adjustments and trimming every single one(!).As for multiplexing, I agree, a shift chain is a fine way to go -- assuming the scan rate is insubstantial. 74HC165 is the basic model, I don't know that a registered version (the aforementioned 74HC589) is necessary but you can if you want.The usual input conditioning and filtering applies:- Consider using a schmitt trigger type input- Analog filtering may be desirable, depending on ambient environment; added capacitance will slow down the minimum transition rates though- Digital filtering, aka debouncingSchmitt trigger: I'm not sure there was a specific number for this? Some families may offer it, e.g. 74LV165A. Else, a hex or octal schmitt trigger can be added between opto and register. Examples: 74HC14 (inverting), 74HC7014 (precision input threshold), 74HC7541 (octal, with enable), etc.Typical debouncing example: for each input, consider the previous three samples (as a sliding window). If all three were '1', set the output to '1'; if all three were '0', set the output to '0'; else, leave the output where it is. Thus, if the input reads "wrong" for only one or two samples, it's probably noise; but if it reads for three or more, it's probably correct.You should be able to run a shift chain of ~150 bits at a clock of a few MHz, giving a sample rate in the low 10s of kHz. Which means filtering around the same cutoff is acceptable.If the signal path is more than a meter or two long (or less than that, in a noisy environment), you must pay attention to signal quality, which can be discussed separately.Tim

author: David Hess
author_rank: Super Contributor
timestamp: October 13, 2020, 08:14:10 am
content: Quote from: edavid on October 13, 2020, 04:13:58 amThe simpler control signal wiring makes it easier to place the 74HC165 or 74HC589 close to the source.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 13, 2020, 09:18:27 am
content: Specifically, you need exactly CLK, LOAD, MISO, and optionally MOSI if you want to place outputs along the chain (typically 74HC595s) or if you want to measure the length of the chain (say by loading it with all zeroes, then all ones, and counting how many clock cycles it takes to loop back). VCC and GND, and you're done. Each node needs a bypass cap, shift register, whatever biasing for the optos, whatever filtering for signal quality, and that's it. Everything fits in a 5 or 6-wire cable (use shielded multiconductor, or 8-10 wire ribbon with the extra pins wired to GND or VCC), and can be wired so that nodes can be chained indefinitely, or with one loopback at the end.A parallel bus, simply needs more wires. On a high level, it works just the same, merely scaled differently. You could even use a shift register to select the active node, instead of directly addressing it. Or use an ALE (address latch enable) signal to assert address on the data bus before reading the data, which gets you a 256 node capacity, or more if you provide additional ALEs or use of internal state. You do get more bandwidth, since there's more bits and the same propagation delay limitation, but it's not fantastically more, not like the step up to Ethernet or fiber.Tim

author: BrianHG
author_rank: Super Contributor
timestamp: October 13, 2020, 09:38:24 am
content: In my experience, a ~960nm photodiode reverse biased with 10k to 100k pullup will hard short to GND when hit with a ~960nm laser diode operating at less than a 1mw from a few meters away, no amplification needed. 5mw would give you great distance. Using a 5 degree IR led, you would need to modulate the source like a TV remote control and amplify the output with a tuned high gain amp to receive the source when operating a few meters away. Pseudo/cheap all plastic lense-less laser diodes used for things like elevator door safety sensors with ~0.25 degree will also operate at a great distance, but you understand that there will be beam divergence. (To align and target my old projects, I used a cheap B&W netcam at the time which could see the IR spot generated by the laser diodes...)I believe I used to use LTR-516AD centered around 940nm sensitivity and fairly narrow. There was also LTR-516AB which went down to below 800nm range and was still fairly sensitive to the 650nm range, so, visible light could throw this one off without additional optical filtering. They are around 20 years old, so there must be something newer, but their sensitivity and angle were great for the 20cent price.(Digikey appears to still stock these today....)

author: Poorly Calculated
author_rank: Contributor
timestamp: October 13, 2020, 03:15:47 pm
content: Quote from: NiHaoMike on October 13, 2020, 05:21:13 amThe reason we went with IR lasers is that the lasers are pretty far, more than 1m, away from the sensors. While going through datasheets for the phototransistors/photodiodes, they were all greatly sensitive to IR. If we were to go full scale with this, we would need a sampling frequency of > 230 ksamples/s. Also, I did not do much exhaustive testing with photodiodes.

author: David Hess
author_rank: Super Contributor
timestamp: October 13, 2020, 03:19:32 pm
content: Quote from: T3sl4co1l on October 13, 2020, 09:18:27 amAnd if 74595 SIPOs are combined with 74HC165s or 74HC589s PISOs, the parallel load signals can be tied together so the outputs are shifted in, parallel load is executed, and then the inputs are shifted out.

author: Poorly Calculated
author_rank: Contributor
timestamp: October 13, 2020, 03:27:20 pm
content: Quote from: BrianHG on October 13, 2020, 09:38:24 amI do have a couple of different photodiodes to play with, so I will try out a simple pullup resistor like you mentioned. We would use IR LEDs if there weren't sensors spaced a couple cm apart. Because the light source would be more than a meter away, I can see one LED messing with more than one sensor.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: October 14, 2020, 01:05:50 am
content: Quote from: Poorly Calculated on October 13, 2020, 03:15:47 pmOk, then that will need a high speed interface to do a single chain (probably LVDS signalling and a local FPGA at each node, or if you can find the equivalent logic or serdes in that speed grade and interface (LVDS serial bus, LVCMOS parallel) even better. Or, still with old fashioned logic, you'll be able to collect maybe 64 channels per bus (i.e. 16MHz clock, for a 250kS/s rate) so will need three buses. Which isn't too bad. Of course, more buses if the propagation delay limits clock rate. (The N serial buses are also equivalent to an N-bit parallel bus shifting around a loop, using word-width registers. Though, I don't know of any async-parallel-load bus registers, so the 74HC165s are probably still the best bet?)Tim

author: NiHaoMike
author_rank: Super Contributor
timestamp: October 14, 2020, 01:13:28 am
content: Quote from: Poorly Calculated on October 13, 2020, 03:15:47 pmThat's definitely high enough for photodiodes to be the ideal choice. Some shift registers would probably be the best choice for combining the signals to send to a FPGA.

author: BrianHG
author_rank: Super Contributor
timestamp: October 14, 2020, 01:20:37 am
content: Quote from: T3sl4co1l on October 14, 2020, 01:05:50 amThe 74HC589 has an additional otptional separate parallel load registers separate of the serial shift bus compared to the 74HC165. You can take a snapshot while shifting all the elements. Depending on the needs, the 74HC589 has a nice feature and the IO pinouts are much more friendly to the user's needs. Running the IC at 5v, the OT can operate at 30 MHZ with 2 bits (2 parallel channels), +3 control wires. Or, 4 bits at 15MHz, running the 74HC589/165 at 3.3v.

author: BrianHG
author_rank: Super Contributor
timestamp: October 14, 2020, 01:29:52 am
content: Quote from: Poorly Calculated on October 13, 2020, 03:27:20 pmLaser diodes are a completely different animal compared to IR leds.If optical power/focus/length is outside your expertise, you must get your hands on the laser diodes you want to work with an test that way. Also do not believe that your eyes are safe just because you cannot see the beam.The photodiode I mentioned is very fast and very sensitive.

author: Zero999
author_rank: Super Contributor
timestamp: October 14, 2020, 12:58:02 pm
content: Why not multiplex the analogue signals and feed them into a microcontroller, with an ADC, before passing it to the FPGA?11 of the 74HC4067, a 16 way analogue multiplexer, could enable up to 160 channels to be read by a microcontroller with a single ADC input and eight output pins.

author: Renate
author_rank: Super Contributor
timestamp: October 14, 2020, 01:31:52 pm
content: You say 230 ksps, but that still doesn't tell everything.Maybe your application is a dead cow falling though a set of laser beams.You may need a time resolution of 4 µS but you don't need to stream the data at 230 ksps.Also, what is the geometry of this? How far apart are the sensors? Are they in groups?

author: Poorly Calculated
author_rank: Contributor
timestamp: October 14, 2020, 03:46:26 pm
content: Quote from: Renate on October 14, 2020, 01:31:52 pmRectangular geometry, they are roughly a meter apart, and each laser/sensor pair operates independently of each other.

author: Renate
author_rank: Super Contributor
timestamp: October 14, 2020, 04:12:11 pm
content: You're not giving us any hints to how/what this thing is.There is a big difference between various scenarios that would affect how you implement this.Possibility #1This is used for discrete tests that take about one second.Something happens and each of the 150 sensors is broken once.Possibility #2This is used for continuous monitoring over the course of a month.There is much activity and each sensor will get broken 1000 times a second.Also what is the longest distance from the central measuring point to the farthest sensor?

author: Nominal Animal
author_rank: Super Contributor
timestamp: October 15, 2020, 02:21:03 am
content: Quote from: Zero999 on October 14, 2020, 12:58:02 pmOr ten of 74HC4067, if your FPGA has 16 ADCs (or signal inputs), and shares four address pins among all 74HC4067.Then, it'd take 16 sample cycles (switching the mux address at each step) to sample all 160 inputs.I like the look of those 74HC4067's.

author: BrianHG
author_rank: Super Contributor
timestamp: October 15, 2020, 02:50:51 am
content: A laser diode pointed at a photodiode is going to be a make or break condition. There will be no in between, no need for analog. Even at 100 feet.

author: Nominal Animal
author_rank: Super Contributor
timestamp: October 15, 2020, 04:16:22 am
content: Unless you use the information for self-testing and calibration, essentially a programmable comparator with a self-test/signal analysis mode, true.Let's look at ATtiny404 in SOIC16, which at Mouser costs about 0.40€ apiece. It has SPI slave capability at up to 5 MHz clock, and enough pins for 8-bit parallel input. The sampling is synchronized so that all input channels are sampled at the sample SPI clock, every 8 SPI clock cycles.So, let's say you have 20 of those. The FPGA then needs one SPI clock output, and 20 inputs. You can then theoretically sample at 5/8 MHz or 625 kS/second (one set of 8 samples per 32 clock cycles – doable, since most AVR instructions take one cycle to execute).On the ATtiny404, the input pins would be PA4-PA7 and PB0-PB3, so a sample cycle consists of two GPIO port byte reads, two ANDIs (AND with immediate), and one OR; and a write to the SPI output register; or six cycles or so. In Master mode (so the FPGA would need to handle 40 input data and 40 input clock lines), the maximum SPI clock is 10 MHz, so the sample rate could reach 1.25 MHz, or 16 clock cycles per sample byte. It should be doable, although might need a tight assembly loop with all interrupts except start/stop signal line disabled for a continuous sampling run.If OP needs only 250 kS/second, that's a data rate of 40 Mbits/s; quite doable. (Evena simple USB test on Teensy 4.0can do 200 Mbits/s; much more if one uses USB bulk transfers instead of the tty layer. With Teensies, the problem is getting the 160 digital inputs read in time – maybe if one used a bunch of 74HC4067's with all sharing the four address/selector bits?)