How to run a boundary scan - Page 1
Forum section: electronics / general

author: mkappert
author_rank: Newbie
timestamp: August 22, 2016, 01:49:15 pm
content: Hello guys ,Im currently writing my thesis and its about running a bscan on a Spartan 6 (Digilent Atlys Board) with a xilinx platform cable(DLC10).Assume I wrote my FSM/TAP-Controller in Verilog and linked it to the specific bscan primitives , then I could say the hardware side is done? Am I correct or do I muss something?The main problem is the software. Do you know any software or do you have any hints for me , how to connect an API with the hardware. Like how I can send data to the FSM(TDI , TMS TCK) and receive (TDO) the data.I tried hours over hours with urjtag but it wont work accuratly. And I dont get through it.Im grateful for any help.Have a nice dayMario

author: kfnight
author_rank: Regular Contributor
timestamp: August 23, 2016, 04:18:56 pm
content: Do you want to perform boundary scan on the Spartan 6 pins? The FPGA already has a TAP controller that you can access to perform boundary scan, so no need to write your own. Are you thinking of testing the traces on the Atlys PCB?

author: jnz
author_rank: Frequent Contributor
timestamp: August 23, 2016, 04:22:59 pm
content: ... Sounds like your "thesis" needs a whole lot of work.

author: mkappert
author_rank: Newbie
timestamp: August 24, 2016, 08:03:06 pm
content: A picture says more than 1000 words.We have no interface to check the data of the application FPGA except JTAGThe goal is to send 32bit data through the FPGAs to adjust the timing because there might be different wire lenght etc which causes delay and we try to run the system as fast as possible.

author: helius
author_rank: Super Contributor
timestamp: August 24, 2016, 08:22:08 pm
content: Boundary scan is just that, a scan around the boundary of the chip, the I/O pads. Each pad has a register and they are all part of a chain that goes to the test port. This is used to test the assembly quality, e.g. open pads or shorts from deficient soldering. The boundary scan commands can be used to build a set of patterns, from a known working board (or from netlists), and then test each board against the patterns. This is all designed for manufacturability, it is separate from the other use of JTAG for debugging.The patterns you can make are static, they don't have the ability to TDR each pin to see how long the traces are. You actually could make a FPGA configuration to do TDR; but this is far outside the remit of boundary scan.

author: mkappert
author_rank: Newbie
timestamp: August 24, 2016, 08:50:05 pm
content: I know that this is not the usual function of JTAG but we want to exploit JTAG for it.It is possible to send a Pattern via TDI and shift it through all I/O Pins or BYPASS them etc.Thats basically what we want to do. And read them back through TDO.But I dont get that far.

author: rstofer
author_rank: Super Contributor
timestamp: August 24, 2016, 09:23:45 pm
content: If you want to manipulate input pins and verify output pin, JTAG is the way to go. If you want to look deep inside, there is another almost standard called IJTAG - Internal JTAG.http://blog.asset-intertech.com/test_data_out/2011/07/what-is-jtag-and-what-is-ijtag.htmlOne nice feature of the new Xilinx toolchain is the Integrated Logic Analyzer which allows me to define which internal signals I want to watch and they will display on the screen when the FPGA is running. But this only works for the more modern chips...At one time I was thinking about adding some shift registers to the inside of a CPU I was building and shifting data in and out. I wan't planning on any particular standard, I just wanted to do something simple.At one point, I was designing a PDP11 ALU. The FPGA just took operands and opcodes via SPI and returned the results, again via SPI. I used a pretty nice uC (Analog Devices Blackfin) to grab test vectors from a file server and shovel the data back and forth. My desktop would take the vectors and the result and post a report of pass/fail. The test vectors included the expected response.