Why isn't a PNP transistor architecture the opposite of NPN on IC's? - Page 1
Forum section: electronics / projects

author: Beamin
author_rank: Super Contributor
timestamp: November 03, 2019, 03:54:20 pm
content: I was looking at some pictures of simple chips under a microscope and noticed the NPN transistors are round bulls eye types while PNP's look square and nothing like them. This seems to be like this on all chips so not just a manufactures method. Why wouldn't it just be the opposite? Does it have to do with the silicon holding capacitance such as the one with the "holes" which I am assuming is the boron (N?)side (boron has a valance charge of 3 while phosphorous is 5 and silicon 4, four is right in the middle since atoms have 8 electrons in their outer most shells, another interesting fact: the electrons that conduct electricity are valance electrons while the ones that don't are in the conduction band). Greater capacitance might equal slower switching speeds which sometimes but not always is undesirable? Does this have to do with the fact the silicon uses thermal photons to conduct (IR photons ~1-10eV in the same way a bright flash of UV photons can erase eproms or visible photons screw up the raspberry pi's bare chip).

author: Kleinstein
author_rank: Super Contributor
timestamp: November 03, 2019, 04:50:20 pm
content: For many simpler chips one prefers a simple process with few processing steps (e.g. masks). A common simple process to make BJT based chips allows for good NPNs, but only lateral PNPs - thus the different look and also poorer quality for the PNPs.There are other more expensive processes that also allow for reasonable good PNP transistors. The transistors may still look different, because they are made in different steps of the process.There are a few different such standard processes, all with there own advantages and disadvantages. Many processes limit the parts available for the design. This sometimes leads to odd looking circuits inside some chips. For example OP the P-channel JFETs are quite common (e.g. LF353, TL07x and similar), while as discrete parts P-JFETs are rarely used as amplifiers. The combination of NPNs with P-JFETs (but no good PNPs) is available in a relatively simple process.There is a difference in the speed how fast the material for P and N doping a diffusing inside the silicon. This gives different preferred processes to make local N and P regions. Especially when combined in one chip, one can not use the fast diffusing material first. So there a technological limitation what steps can be combined.The different processes needed are also in parts responsible for higher prices for some parts - though much is also about quantity.

author: magic
author_rank: Super Contributor
timestamp: November 03, 2019, 08:22:44 pm
content: A helpful drawing from 1979 Signetics Applications Manual is attached.The reason for such construction is because for the sake of cost and simplicity (=yield) the classic bipolar monolithic process creates only a minimum number of layers required to get decent vertical NPNs. PNPs are hacked together using lateral construction in the same layers.This is not a problem with discrete parts where only one polarity of transistors is produced on one die and no isolation is required between transistors because the die will be cut into pieces.Quote from: Beamin on November 03, 2019, 03:54:20 pmThat's actually an interesting question. A "mirror" process could produce, for example, truly complementary versions of the 78xx regulators, which wouldn't require capacitors for stability unlike the actual 79xx regulators and could have their heatsinks connected to ground rather than Vin.I'm not sure what was the historic reason for not pursuing such technology in applications like aforementioned regulators, where topmost performance is not critical. Perhaps because there is no use for it, outside of specialty ICs running on negative supply rails like 79xx.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 03, 2019, 11:19:51 pm
content: They can be, when a process is used that has the additional diffusion steps (which was a challenge in early processes, see above).It's very ordinary when it comes to e.g. CMOS, where the Pch has an additional diffusion to isolate it from the substrate, and the rest looks pretty normal. (Because of the additional diffusion, but also due to the electrical properties of Pch transistors, the area taken up is about double that of the companion Nch transistor(s).)A similar process I think is used in complementary bipolar fab. Like CMOS, it just came along later, and cost a bit more to run.As for electrical properties, proper (non-lateral) PNPs tend to perform well, but still a little inferior to NPNs: due to the additional doping steps, the impurity level is higher, and therefore they tend to have higher recombination current (making hFE poor at low currents), breakdown voltage, and fT (the upside to recombination). So there is still a preference for NPN.You could flip the whole die, using n- substrate and having better quality PNPs and poorer NPNs, but the performance still isn't as good, because PNPs have to deal with holes preferentially over electrons. The difference is slight, compared to the 2.5x difference between MOSFETs, but it's still there. This extends all the way to single transistors (which are constructed on whatever substrate is appropriate), which is why NPNs are still preferred with discretes.Tim

author: Beamin
author_rank: Super Contributor
timestamp: November 08, 2019, 10:01:51 pm
content: I didn't realize that PNP was made from the same type of silicon substrate. Whats the difference in N and N+? Isn't N just always N?How is the parasitic diode formed? Is that undesirable?

author: Kleinstein
author_rank: Super Contributor
timestamp: November 08, 2019, 10:10:33 pm
content: N+ stands for higher N doped material. There is not just the question of n or p doping, but also the parameter doping level.The every PN junction acts like a diode. As all the transistors share a single piece of silicon there are usually also diodes where one does not need them. A common case are diode junctions towards the substrate. For this reason chips usually don't like an input voltage outside the supply range (at least at one side).

author: iMo
author_rank: Super Contributor
timestamp: November 08, 2019, 10:25:19 pm
content: The N+ (ie the above picture) is usually used under the metallic contacts, to avoid creation of a schottky diode..

author: IanB
author_rank: Super Contributor
timestamp: November 08, 2019, 11:09:50 pm
content: To add another dimension to the question, I recall that the early transistors were germanium based and tended to be PNP types. Would that be because germanium processes favored the fabrication of PNP transistors over NPN transistors?

author: magic
author_rank: Super Contributor
timestamp: November 08, 2019, 11:31:37 pm
content: Quote from: Beamin on November 08, 2019, 10:01:51 pmWhat they didn't mark on the diagram is that the substrate and the isolation diffusions are P-doped and connected to ground / negative supply.That's how collectors of NPNs and bases of PNPs are isolated from one another. There is no real dielectric isolation between them, only a reverse biased PN junction.As a result, any of those nodes cannot be brought more than one diode drop below the negative supply.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: November 09, 2019, 04:03:24 am
content: Quote from: IanB on November 08, 2019, 11:09:50 pmNot in ICs. That was a matter of materials, alloy junction transistors were made by melting indium into the crystal.Or, I forget if there was reason to continue using PNP into the planar era?Tim