6 layer PCB stack up - Page 1
Forum section: electronics / projects

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: April 29, 2020, 08:16:00 am
content: Hi,I'm designing a 6 layer board, I need to have these impedances, 40 Ohm for DDR3, 80 Ohm for differential signals of DDR3 and 50 Ohm single ended and 100 ohm differential for other interfaces, I'm stucked with selecting reasonably cost effective Stack up to reach my design goals,I have calculated this stack up, with these spaces.the problem is that,I can not make 40 ohm single ended, because the trace width would become too large(around 10mils)! so I can not route the board efectively, I need the trace to be around 4-6 mils, any Ideas what should I do?

author: Miyuki
author_rank: Frequent Contributor
timestamp: April 29, 2020, 09:00:31 am
content: And increasing impedance ? Or you have to go to really high clock rates ?Check signal calculation for 50 OhmOr even higher, all depends on distance and clock needed to keep eye diagram enough

author: TheUnnamedNewbie
author_rank: Super Contributor
timestamp: April 29, 2020, 09:48:24 am
content: A single ended microstrip/stripline is always gonna give you much wider traces than a differential with two time that impedance, because you don't have all that capacitance of the nearby trace to make the thing smaller.If you really need single-ended transmission lines, consider using something like CPW.

author: OwO
author_rank: Super Contributor
timestamp: April 29, 2020, 10:42:14 am
content: DDR3 system impedance is scalable. I haven't tried this yet but you may be able to use 60ohm traces if you change the on-chip termination calibration resistors (Zq on the dram chip side and VRN/VRP on the FPGA side).

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: April 30, 2020, 06:09:36 am
content: Quotewhats CPW?QuoteOh, that's good advice, and I have not tried it yet!my DDR3 speed is 1866, so xilinx recommended 40 Ohm traces

author: cgroen
author_rank: Unknown
timestamp: April 30, 2020, 06:50:55 am
content: Quote from: ali_asadzadeh on April 30, 2020, 06:09:36 amhttps://en.wikipedia.org/wiki/Coplanar_waveguide

author: ConKbot
author_rank: Super Contributor
timestamp: April 30, 2020, 01:50:53 pm
content: Quote from: TheUnnamedNewbie on April 29, 2020, 09:48:24 amOnly for strongly coupled diff pairs. Once you start pushing up layer counts, or using thin dielectrics for other reasons, you start running into manufacturing limits before you can do a strongly coupled pair. I.e. A 4mil dielectric can end up using ~4 mil trace and ~6 mil trace (don't have exact numbers in my head) which ends up with them weakly coupled. I.e. 90 ohm differential impedance, 25-30 ohm common mode impedance.But at that point you're past, or at least toeing the line for what impedance approximation equations can do accurately and a 2D field solver becomes a lot more useful.

author: OwO
author_rank: Super Contributor
timestamp: May 08, 2020, 01:01:57 pm
content: UPDATE: I just tested that DDR3 can be operated with 67ohm traces (~0.15mm width on 0.2mm prepreg), if Zq is set to 360ohms and Zynq on-chip termination resistors VRN/VRP are 120 ohms. This sets a 60ohm system impedance. Booting linux and running memtest for 2 hours so far hasn't shown errors, but I'll let it run for 2 days and post here again. This is running at 1066Mb/s.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: May 09, 2020, 10:20:23 am
content: Thanks Owo,But I'm targeting for 1866Mb/s

author: OwO
author_rank: Super Contributor
timestamp: May 13, 2020, 07:19:11 am
content: It passes memtest running for over 2 days, but so far it's only one sample. I will be building a few more samples later to test.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: May 14, 2020, 06:45:34 am
content: QuoteThanks for sharing, what FPGA or CPU are you using? any DDR part number to share?

author: OwO
author_rank: Super Contributor
timestamp: May 14, 2020, 07:10:19 am
content: Zynq 7020. H5TQ4G63AFR. Get the -TEC suffix (2133 speed grade) if you want to go 1866Mb/s. Always get DDR3 components faster than the speed you are targeting, this way you will have more margin and a wider eye.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: May 15, 2020, 10:24:04 am
content: Thanks OwO, is it a 4 layer job again?also open source or closed?

author: OwO
author_rank: Super Contributor
timestamp: May 16, 2020, 05:37:50 pm
content: https://github.com/gabriel-tenma-white/sdr6New board, same DDR3 layout as sdr5. This time JLC doesn't offer PCBA on 0.1mm prepreg boards anymore, so I went with 0.2mm and adjusted resistors.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: May 17, 2020, 05:37:39 am
content: Thanks for sharing,I have made suggestions in github