Simple sinewave generator with arduino (100Hz-100kHz) - Page 1
Forum section: electronics / projects

author: Yansi
author_rank: Super Contributor
timestamp: November 08, 2024, 07:46:25 pm
content: Hello all,after long time, have another interesting topic to discuss. Even dared to use the forbidden swear-word in the subject nameWhat could be the most optimal and simple way to generate a sinewave signal in the range of say 100 Hz to 100 kHz, using an old school THT 8-bit microcontroller, like Atmel AVR? There is no strict requirement on the THD, however it should not be an ugly potatoid. Frequency resolution not important either, just need a decade count in 1 2 5 10 20 50 etc.Generating a square wave in this frequency range shall be quite easy using any 16bit timer, however I have no clear idea, how to efficiently filter the square output over the 3 decades (100 Hz to 100 kHz). Bank of switched fixed filters are likely out of question, would not be effective enough.The obvious answer would be a DDS, however the solution shall be limited to THT components only and especially price kept low. So rather expensive DDS chips are out of the equation, especially that I need only these rather low frequencies.Now thinking about more analog solutions, like triangle wave log. current controlled VCO with a wave shaper (JFET?), however it would be tough to control the stability and precision of the frequency. However, as I am thinking on the go, log current controlled VCO with a wave shaper is not difficult thing to do and the whole thing could be closed-loop controlled (frequency measured by the MCU and tuning controlled on the fly). That could be fun!Another idea came right after - I think the whole VCO and sine shaper thing could be done within a single IC like XR2206. And it could be directly interfaced to a log current source to tune it. So, in the end - only the XR2206, an opamp for the log current source and a DAC IC for tuning.Any more ideas, that would not lead to overly complex or expensive circuit solutions?Just summary of requirements: Cheap THT components, some 8bit microcontroller, not expensive or too complex circuits, generate 100 Hz to 100 kHz with reasonable THD in at least! 1-2-5 frequency steps, more resolution the better.Many thanks for ideas,Y.PS: Already started prototyping with the XR2206, that idea is so dumb I must try that.

author: shabaz
author_rank: Frequent Contributor
timestamp: November 08, 2024, 08:42:36 pm
content: If you're using a through-hole AVR, then this sounds like a one-off project. A DDS board would absolutely not be excessive for a one-off project. Not expensive either; $10 or so for a ready-made board with through-hole connections from AliExpress (e.g. AD9834 or various other options), and many hours of time saved.

author: oPossum
author_rank: Super Contributor
timestamp: November 08, 2024, 08:46:52 pm
content: DDS in assemblyfor example...https://scienceprog.com/avr-dds-signal-generator-v20/

author: moffy
author_rank: Super Contributor
timestamp: November 08, 2024, 09:07:23 pm
content: You can get quite a large frequency range from an opamp triangle generator, variable switched current source feeding an integrator opamp with a level comparator controlling the current source switching. It then goes into a sine shaper, e.g.https://www.ti.com/lit/an/snoa665c/snoa665c.pdfSimilar to how the XR2206 does it. Another way is to construct your own DDS with the micro and a DAC and a fixed filter, quite straight forward, and use an 8bit TH DAC or even just suitably weighted resistors connected directly to the micro.

author: shabaz
author_rank: Frequent Contributor
timestamp: November 08, 2024, 09:15:17 pm
content: Could even use a 74HC divider (or simply use two timer outputs) and a switched capacitor filter. But those are not cheap, and then add on your time.

author: Yansi
author_rank: Super Contributor
timestamp: November 08, 2024, 09:31:17 pm
content: Not really a one-off project, say maybe a 10-off at this time, mayyyyybe more to come later.Ebay special DDS boards are usually rather garbage designs, with zero supply chain reliability and you can not depend on their dimensions or anything. Would rather not spend any time designing a complex PCB around this, in a desperate case I would place the modern DDS chip on the board directly. Am not afraid of SMT stuff myself, but designing some kits for younger children in an electronics hobby group and older guys, who do not have that much skill and are "afraid of the modern small stuff".I know I could program a hand-optimized assembly program to force weak 8bit micro into some kind of DDS abomination, but generating sinewave is not the goal, just a part of more complex instrumentation. Hence why I don't want any more complex circuits just to generate sinewave. Of course one could use a modern DDS chip in SMT, then I could do the rest with modern SMT parts too and end up with something very different, which wasn't the goal. It is just a show & learn kind of a build both for me and others interested.Just as I was debugging my misbehaving XR2206, have found this thread here about the instability of the XR2206 chinese fakes:Topic: Don't buy any kit with XR2206 WFGwhich links this video with some very good info (Skip at 4th minute of this video):I seem i got the batch with 0919 date code. At 10V it behaves OK. At 15V, the output is glitchy. I know I know, should not buy these fakes, but one can't simply get an original part these days and it was just an idea at this point, as I remembered I got a few of these in my stash. And if all it takes to cure the chinese fake IC is to just lower supply voltage, I go with it. Am not designing a volume produced enterprise grade instrumentation.Quote from: moffy on November 08, 2024, 09:07:23 pmYou have mostly described what I have found nicely integrated in the XR2206, right? I would just add an exponential* current converter, controlled from a DAC (need the frequency digitally programmable).I think I could shove the Ic2 current straight onto pin 7 (or 8 ) of the XR2206.*sorry, not LOG current source, must be exponential to tune it logarithmically.//EDIT: Jeeeezus the automatic formatting here. Nobody asked for the embedded video player!

author: Yansi
author_rank: Super Contributor
timestamp: November 08, 2024, 10:16:36 pm
content: So lil update here, have attached the exponential current converter to the tuning current input on the XR2206, it does indeed work an the range of tuning is more than 1000:1 achievable easily. However, the stability and drift may be an issue and some kind of frequency feedback loop will be neccesary.Why not linear tuning directly you ask? Simply because when you need tuning range of 1000:1 (100kHz downto 100Hz), with a 12 bit tuning DAC (which sounds reasonable), you would get a resolution of 100000 / 4096 = 24 Hz at the low end of the frequency spectrum and unnecessarily fine resolution (those same 24Hz) at the high frequency end. Maybe, sometimes it is beneficial to get linear tuning, but this time I need the lower frequencies much more precise.Next one I will try the software frequency loop control.

author: moffy
author_rank: Super Contributor
timestamp: November 08, 2024, 10:29:31 pm
content: Quote from: Yansi on November 08, 2024, 09:31:17 pmI think all you need is to subtract/remove current Ic, to control the frequency f=k*Ic.

author: Yansi
author_rank: Super Contributor
timestamp: November 08, 2024, 10:37:52 pm
content: I am now a bit lost moffy, can you please elaborate please?

author: moffy
author_rank: Super Contributor
timestamp: November 08, 2024, 10:58:23 pm
content: On page 10 ofhttps://www.sparkfun.com/datasheets/Kits/XR2206_104_020808.pdf,the datasheet, it says that f1=1/(R1*C). So it looks like R1 is setting a current, which goes through the current switches into the capacitor C, let us call that current Ic=Vr/R1, where Vr is some voltage. Then f1=k1*Ic/C or just f=k*Ic.

author: David Hess
author_rank: Super Contributor
timestamp: November 08, 2024, 11:10:25 pm
content: Generate a square wave and a separate square wave with 50 or 100 times the frequency. Feed the low frequency square wave into a switched capacitor filter, and drive the switched capacitor clock with the high frequency square wave. This will yield a sine wave with distortion of better than -70dB.

author: Yansi
author_rank: Super Contributor
timestamp: November 08, 2024, 11:43:10 pm
content: Quote from: moffy on November 08, 2024, 10:58:23 pmAh, okay, now I get it, got lost in all those letters of what is what. Yes, the datasheet exactly mentions pins 7 and 8 are the charging current to the VCO capacitor, with a steady voltage of about +3V at those pins. If the XR2206 ground pin 12 is really a circuit ground, I can then put any kind of (programmable) current sink to those pins to set the frequency - already verified by experiment.Quote from: David Hess on November 08, 2024, 11:10:25 pmThat sound especially interesting. This is a completely new territory for me, maybe worth exploring for a bit. Generating the required frequencies apart each other is easy. What kind of filter order you had in mind, with that -70dB THD? Likely not just 1st order...

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 09, 2024, 01:20:33 am
content: Quote from: Yansi on November 08, 2024, 07:46:25 pmThe XR2206 is old an expensive, tho I see some asian sources still make the similar ICL8038.If you want MCU control, you will need a DAC on the MCU, which rather defeats the need for an Analog gymnastics part at all.Quote from: Yansi on November 08, 2024, 07:46:25 pmDedicated DDS parts are only moderately costly, (cheaper than your old XR2206 list for these days) but the bigger problem is they come in MSOP packages.Quote from: Yansi on November 08, 2024, 09:31:17 pmFor your task, it is not reallysome kind of DDS abomination- it would be easy to teach, and gives students something useful at the end.There are many AVR DDS examples, eg you cana) Run an interrupt and DDS inside that,orb) Run a tight loop and interrupt outside of that for new frequency cases.Choice b) uses 100% of the CPU when generating, so has the lowest distortion sines, but any updates have to pause the sine-out then restart with new values.Ballpark numbers for small MCU DDS are ~2-5MHz adder+table rates, with some trade off possible by using shorter adders and smaller tables on some MCU.You can also use larger tables and trade a little speed for lower distortion at lower kHz outputs.At your 100KHz top end, that means 20-50 X samples per sine wave, and the Y values can be 8 bit precision.DAC can be hand made R2R,or you can buy a single SIP part eg Bourns 4610X-R2R-103LF 10K/20k 10SIP, still made and available,or you can use a MCU with a DAC inbuilt.If you roll all that into a MCU search, you find AVR DD / EA / DA / DBinbuilt DACsupporting families with 20/24MHz clock speeds in DIP28.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 09, 2024, 02:05:06 am
content: Quote from: oPossum on November 08, 2024, 08:46:52 pmGood example.Notice that used a terrible LM358 opamp, it should be replaced with a much better, low distortion opamp, able to run to > 100kHz for this project.

author: Yansi
author_rank: Super Contributor
timestamp: November 09, 2024, 09:00:10 am
content: Software DDS swamped 8bit AVR is not possible I'd say, as I will need the MCU to run some calculation and ADC data processing synchronously with the sinewave generation. Told ya the goal is not just to generate the sinewave, thats just one task of many. 8-bit AVR is not enough for any reasonable DDS, abomination at best. But I fully agree, it is a nice teaching exercise, but for that one I already have a solution. Made a simple DDS from discrete logic THT chips, that runs at 1 Msps into a proper multiplying DAC.XR2206 is rather cheap these days, but for sure you seem to only get the chinese abomination, that does not perform that good as the original, there are acceptable workarounds to it, as mentioned above. I just happened to have a bunch of XR2206 at hand, have no other similar ICs in my stash. ICL8038? Sounds a bit like some MAX038 I remember existed too. The 038 number does ring a bell, but I do not have any of those. I see those are very different ICs and the ICL8038 looks very good too. And the internal schematic of the ICL8038 is very educational too! Will need to get some.20 to 50 samples per sinewave for a DDS is also very unnecessary at the top end, when you can use steep rolloff Cauer/Elliptic filters. In that case, it might be possible to run the DDS in the AVR in software, as say at 300 ksps you'd have over 50 instructions for each sample. It would still hog the majority of the CPU horsepower away, but it might work. I say might. Need to run some more heavy math in the MCU too, not sure now how fast it will need to run.No idea about the new DD EA DA DB series AVR, will use some atmega8/16/88/328 whatever leftovers I will find in my stash (have plenty!). Definitely won't bother buying any of these new series. Heard one of my friends likes to use some modern AVR zero series or what it was.What I have found really interesting is the solution with the switched cap filter. There are plenty of rather cheap ICs that do 5th order, however they are usually limited to rather low maximum cutoff frequencies, at best at about 50 kHz. Those who go above that, begin to get expensive quickly. Wondering if David Hess has any suggestions as to what part to use...

author: Kleinstein
author_rank: Super Contributor
timestamp: November 09, 2024, 10:59:50 am
content: For just generating a sine signal (no extra modulation) the AVR with DDS in ASM can be surprisingly fast. AFAIR one could get 8 or 9 clock cycles per sample and thus a little over 2 MSPS if needed. There is very little math needed: just add the phase accumulator and lookup the sine data from a table. Extra math is needed when changing the frequency and similar. Chances are that changing the settings / frequency etc. would cause glitches. A 2nd µC could reduce the glitches (e.g. handle keys).With a reduced speed one may even be able to add some limited modulation or sweeps (e.g. a 2nd software DDS and multiplying ADC for AM).It should still be well fast enough for 100 kHz output.The XR2206 is a simple solution, but more with analog control and maybe the µC to measure the frequency. A PLL to control the frequency is possible and 4046 chips are rather cheap for this. It is still some effort to adjust the loop filter with the frequency band. The µC could provide the ref. clock. Using the µC to control the frequency as a kind of PLL in SW can be tricky and add glitches.

author: coromonadalix
author_rank: Super Contributor
timestamp: November 09, 2024, 12:03:37 pm
content: you had this project based on a sold fg-100 generator, it could go at 500Khzbased on a ATMega328p ....

author: Yansi
author_rank: Super Contributor
timestamp: November 09, 2024, 02:28:09 pm
content: I know how a DDS works and how to program it. Just saying, it will never be efficient on something like an AVR, where there is not even a DMA to help.9 clocks per sample is nice theory, but in practice, where the MCU has something else to do, it will never be. You'd need an interrupt for every sample, requiring extra cycles for interrupt entering and exit, extra clocks for stacking up the context, extra cycles for accessing the the phase accumulator (can't keep it in registers, if the MCU has other stuff to do - and no, will not write it all in assembly by hand, just to spare 3 registers for quick access). So in the end, you be lucky to fit within like 30 clock cycles.Quote from: coromonadalix on November 09, 2024, 12:03:37 pmDon't care, said already am not making a wavegen, so no interest in trying how fast can 10 instructions run in a loop on an AVR micro. Sine gen is only small part of what I need.So far the most promissing idea was from David Hess, with the switched capacitor filter, to have a filter that continuously tunes together with the generated square frequency. However, am having huge trouble finding a suitable IC for the job. All cheap available switched cap filters seems to end around 50 kHz maximum cutoff at 5 MHz clock (1:100 ratio).So far the most promising one I found was MAX295, which is 50:1 clock to cutoff ratio and quite available. I could easily generate the clock and signal at 64:1 ratio, which should work nicely together.But I just don't want to give up at 50 kHz, I want 100k badly... So search for suitable filter still continues.

author: Yansi
author_rank: Super Contributor
timestamp: November 09, 2024, 03:03:36 pm
content: So it seems the only option for a switched cap filter is likelyLTC1064-2 (click here for datasheet). Still could be obtained even in DIP package. But the listing price of that. OUCH!Shady sources offers it for $10, which I think may be reasonable.I think it could be used in the mode described above: 50:1 CLK to cutoff ratio and the square wave input will be 1/64th of the clock. Meaning, for example at 100 kHz, the clock would become 6.4 MHz and cutoff will be 128 kHz respectively. As the filter is 48dB/oct, the second harmonic (200 kHz) will be attenuated at about 31 dB, third harmonic at 59 dB, etc. I think that is reasonable.Need to order a bunch of these weird swiched cap ICs and have a go at it. I like this non-orthodox solution. If the "shady source" IC for $10 will work, am fine with the price. Otherwise not so much. Mouser can shove them somewhere, for those $40 a piece.

author: shabaz
author_rank: Frequent Contributor
timestamp: November 09, 2024, 03:30:06 pm
content: How is it non-orthodox, when at least two people have mentioned it on this thread so far?The DDS options appear to meet all requirements. You could dedicate a microcontroller to this, for less than the shady source price you mention for the LTC part. Or you could even buy DDS ICs for less than that (Digikey charge less for them in quantities of ten, than that shady source price) and they would be genuine, with a good chance of working, rather than a shady source part. It would cost almost nothing to reflow them onto small ready-made breakout boards, so that users only have through-hole items to deal with.

author: Yansi
author_rank: Super Contributor
timestamp: November 09, 2024, 04:11:09 pm
content: Maybe I count wrong, but switched cap filter was mentioned only by David Hess.To microcontrollers: A solution typical of an arduinist: If one is not enough, slap there another one. No, it is ugly. So is any kind of breakout board. Why not solder directly to the PCB then? But if you start allowing SMT components, why not do the whole design in SMT? Why not then using a different MCU alltogether, that could do it easy? I want a clean design I can be proud of, if I am spending time and effort on it.But so you don't say I did not try, lemme present myself a possible software DDS solution, that would allow the MCU to do some other business, not just loop 10 instructions and try to be badass. Sorry, my AVR assembly is a bit rusty, haven't done sh!t with AVR in ages. But lets estimate the clock count, for handling each sample by an ISR. Sorry if it is not compilable straight away, or there are mistakes, but I do not think you could get it much simpler than this.Assuming 24bit FTW (frequency tuning word) and 24bit phase accumulator, 256 long table, 8bit data.Code:Interrupt service enter, push PC onto stack - 4 cyclespush r0 ;2 cyclespush r1 ;2 cyclespush r30 ;2 cyclespush r31 ;2 cycles;Add lowest bytes togetherlds r0, pha0 ;2 cycleslds r1, ftw0 ;2cyclesadd r0, r1 ;1 cyclessts pha0, r0 ;2 cycles;add middle bytes togetherlds r0, pha1 ;2 cycleslds r1, ftw1 ;2 cyclesadc r0, r1 ;1 cyclessts pha1, r0 ; 2cycles;add top most byteslds r30, pha2 ;2 cycleslds r1, ftw2 ;2 cyclesadc r30, r1 ;1 cyclessts r30, pha2 ;2 cycles;load data from table, output on portldi R31, tablebase; 2 cycleslpm ;load r0 from Z(R31:R30), 3 cyclesout porta, r0; 2 cyclespop r31 ;2 cyclespop r30 ;2 cyclespop r1 ;2 cyclespop r0 ;2 cyclesreti ;4 cycles54 cycles total if I counted right. Not sure you could do it much faster, if you need the MCU to do other stuff while generating the sinewave, sample by sample, in an ISR.Let me know if you have better idea to share CPU time between the DDS ISR and rest of program. I simply don't see a way.//Edit: forgot 3 more cycles to RJMP to the ISR. So 57 it is.

author: shabaz
author_rank: Frequent Contributor
timestamp: November 09, 2024, 04:46:21 pm
content: Quote from: Yansi on November 09, 2024, 04:11:09 pmThere are at least two references. See reply #4QuoteThat makes no sense. If one microcontroller is not enough (it's for you to determine) then you could move to a different device or add another. I'm merely pointing out that it's cheaper and meets the requirements. You'd rather use a dodgy $10 part than a more cost-effective known working microcontroller? Besides, you're the one with AVR, STM etc against your username, so what's wrong with using technology you're familiar with, rather than a part that in all likelihood may be fake and may not function?QuoteYou've already explained why; you want a through-hole solution for the people who will be assembling it. If you want to rule out a breakout board now on the grounds that it is "ugly" that's entirely your choice of course, but since you mention it, I'll say that it sounds like a silly reason.QuoteYes, why not? You were the one that stated that it would consume too many of the resources in the device than you were prepared to accept. Now, if you're prepared to spend $10 then you could for sure use a better microcontroller in DIP package if you wanted to, or scale horizontally. Your design decision.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 09, 2024, 06:21:00 pm
content: An ISR adds quite some overhead, especially if a compiler is used and registers need to be saved. For a pure ASM solution one can usually reserve some registers for the ISR and use other for the main program.Another way to speed things up (especially if registers need to be saved in the ISR) is using one ISR call for 2 or 3 DDS samples. So send one out at the start (not many registers needed for this) and than calculate 2 or 3 points and send out the other 1 or 2 with a suitable delay from the run time. This can cur the effective ISR overhead to nearly 1/2 or 1/3. So chances are one would end at maybe 30 cycles

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 09, 2024, 07:48:30 pm
content: Quote from: Yansi on November 09, 2024, 02:28:09 pmThat's a modest overclock, you could try it ?Quote from: Yansi on November 09, 2024, 04:11:09 pmThere are many ways to be better than 57 cycles, but the simplest, by far, is to just use a MCU as the dedicated DDS source, as a smart DAC.I think the cheapest MCU with decent DAC are Silabs ones, but those do not come in DIPIf you really cannot get over the psychological barrier of two low cost MCUs, you could look at the smart DACs from TI, that can do 24 table sine waves.Search for TI's app note :Analog Engineer's Circuit Smart DAC Sine-Wave Generation CircuitSince you seem fine with many TTL parts, another choice could be a johnson counter derived sine. See :TI : Application Note The Davies Sinusoidal Generator

author: Yansi
author_rank: Super Contributor
timestamp: November 09, 2024, 09:45:51 pm
content: shabaz: I have completely missed that reply! Sorry for that, my bad.The reason for the THT may be silly for you or not, your choice. Some people play with old computers, some with old THT components.PCB.Wiz: Thank you for you suggestions, theDavies Sinusoidal Generator (sboa550)is certainly something I have never come across. However, in this case I think it is not really that helpful, as it would still need a tunable lowpass filter after it.Regarding the overclock of the switchcap filters - i think at 2x the max datasheet value, it will be more like switched crap. LTCYes, am not afraid using multiple "TTL" chips, but a whole DDS is like 15 of them (have already tried a design like that) and takes considerable PCB area. I need to fit reasonably inside an enclosure, without inventing complex PCB stacking methods inside. So I was thinking still about the DDS as it obviously is the best solution (just not implemented in SW in an AVR micro) and came up with this interesting solution:Why not using some older GAL in PDIP package? Maybe even CPLD in PLCC (can be stuck in a socket). Atmel ATF1500 series comes to mind. 64 macrocell PLD should be plenty large for the required DDS action. However, have never used these, could be nice learning opportunity, what do you think?//Edit: ATF1504 still in production, available for very reasonable $4 a piece in a PLCC44 package. I think I might have a solution.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 09, 2024, 11:31:24 pm
content: Quote from: Yansi on November 09, 2024, 09:45:51 pmThat triggered a memory, so I dug into the dusty archives, and found a exercise we did that was NCO adder design that targeted a ATF1502.Problem: The carry parts of the adder are quite product-term hungry, as is any ROM table.The 1502 part can just fit a 12bit NCO, but lacks any lookup table, and expects a parallel input word.An ATF1504 could manage a longer counter, so might pack 24b, but you need to add a Sine Table EEPROM and parallel DAC and external latches.That's a lot of soldering...If you are ok with PLCC44, you can get AT89LP51 series parts still in PLCC44There are some DIP40 MCUs being offered with new MCU cores, lcsc shows stocks ofSTC8H8K64U-45I-PDIP40 STC Micro at 63c/1and the newer part has more stocksAI8051U-34K64-PDIP40 at $1.22/1These parts have USB loaders inbuilt, so are easy to apply, but would need an external parallel DAC.Addit : STC parts are 42-45MHz and it looks like they can do a 24 bit adder to 1024 x 8 table lookup and port write in about 15 clocks.Unroll once, and there is room to add two boolean (pin or flag ) exits or one boolean exit and a pin toggle for easy check of DDS adder rate.I see lcsc have stock ofSTC8H8K64U-45I-SOP16 1+ $0.4688andSTC8H8K64U-45I-SKDIP28 1+ $0.4809Because you only want 1 2 5 10 steps, you can send a single UART byte from the master to set Freq + Exponent.The DIP28 part could just squeeze in a quad encoder to 2 digit LED 0..9 and EXP display for a nifty self-contained generation solution.

author: David Hess
author_rank: Super Contributor
timestamp: November 09, 2024, 11:33:28 pm
content: Quote from: Yansi on November 08, 2024, 11:43:10 pmAvailable low pass switched capacitor filters are typically 5th or 8th order elliptic.

author: Someone
author_rank: Super Contributor
timestamp: November 10, 2024, 02:25:45 am
content: Quote from: Yansi on November 09, 2024, 04:11:09 pmIt is that sort of assumption you make (at least you state it) that leads you off on the wrong path. How does a 24bit phase accumulator align with your stated 1,2,5 resolution ?Looking through the maths/simulations, it should be possible to use a through hole AVR with some simple external components (Rs and Cs only) and end up with a 60 something dB THD, 100Hz to 100kHz. Likely optimal with a12bit10bit lookup table and updating the output at somewhere above 1MHz. Linear interpolating a delta encoded lookup table might even be more efficient as the frequency comes down while keeping the same reconstruction filter used for the "full rate" operation.*edit to 10bits as the AVR instruction set has a fast rotate instruction

author: Yansi
author_rank: Super Contributor
timestamp: November 10, 2024, 09:02:41 am
content: PCB.Wiz: I have seen those STC micros, but have absolutely no experience with them or the ecosystem needed to use them. But have a plenty plenty of old AVR Tiny/Mega in my stash that I won't use likely ever, so thats what I defaulted in using for this project. Even have those AT89S51, but in DIL40, not PLCC. These won't help, but they are good to keep around for other weird projects for sure. Even recently explored intel 8748 (8035), so I could confidently do a project with these. But let me tell you, the AVR is lightning speed faster, than that old intel job.ATF1502 is only 32 macrocells, right? If I got it right, each macrocell is only 1 DFF inside. For a 24bit FTW DDS, you'd need at least 24 DFFs to store the phase accumulator and another 24 to store the FTW, 48 total. Should fit in ATF1504 easy I guess, has 64 of those. The lookup table might be bit tough to implement, sure. But having external ROM acceptable deal.David Hess: Found plenty of Butterworths and linphase/Bessels too, however they usually end up in the few tens kHz cutoff maximum.Someone: Well, sure, absolute minimum would be the 1 2 5 steps, but if I am doing a DDS, let it be a full DDS. With 24bit FTW, the resolution will be 0.05 Hz or something. 20 bit FTW is likely enough, but programming 20 bits still need 3 bytes, so 24 bits it is. Updating data in AVR at over 1 MHz rate I thnk is impossible, or impractical at least.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 10, 2024, 09:42:47 am
content: An DDS update rate over 1 MHz would be hard when using interrupts. It may just work (with multiple samples per ISR and a few other tricks), but only in ASM, so that no register saving is needed.To reach 100 kHz one would not need 1 MSPS, something like 400 or 500 kSPS should be enough. This should be about would could be done with the DDS ISR written in ASM and the rest with a compiler. The rest part would have not very much computation power left over, maybe 5 or 10% but this can still be enouh for quite some jobs.Another option for the µC could be an Raspery Pico in a kind of DIP40 form factor.

author: Circlotron
author_rank: Super Contributor
timestamp: November 10, 2024, 10:24:42 am
content: Don Lancaster had a bit to say about generating "Magic Sinewaves". It might prove to be an interesting read.https://www.tinaja.com/mssamp1.shtml

author: Someone
author_rank: Super Contributor
timestamp: November 10, 2024, 10:35:22 am
content: Quote from: Yansi on November 10, 2024, 09:02:41 amOnly because you add the 24 bit phase accumulator and all the register swapping. I'd be aiming for 2MHz (8 instructions per output sample @ 16MHz) which is not impossible.Dreams of fitting a DDS into a CPLD are just that, it is a whole lot more logic (and IO) than just an adder.

author: Someone
author_rank: Super Contributor
timestamp: November 10, 2024, 10:40:50 am
content: Quote from: Circlotron on November 10, 2024, 10:24:42 amWhile those constructions are useful for minimising (few level) transitions where you have high precision in the timing relative to the fundamental, 100kHz out of 16MHz is not that case.

author: KerimF
author_rank: Frequent Contributor
timestamp: November 10, 2024, 05:53:43 pm
content: This is off topic.Since a year ago, I started working on what may be called "Delta Sinewave Synthesis, DSS". The request was limited to the audio frequencies only (20 Hz to 20,000 Hz). The goal is to reduce the hardware to its possible minimum; no special ICs and/or precise components.The core of my prototype is ATmeg32 (with 8 MHz crystal). There is one output pin for the delta bitsstringstrean (2 MHz delta clock) that generates sinewave whose frequency could be made from 647.67 Hz up to 20833.33 Hz (485 fixed frequencies, hi-band). And with 62,500 KHz delta clock, the range of frequencies starts from 20.24 Hz up to 651.04 Hz (another 485 fixed frequencies, lo-band). The frequency resolution is between 1.04% and 0.52%.Naturally, since the bit rate is, in the worst case, 100 times the sinewave frequency, even a simple 3-pole RC filter can let the THD low. But, unfortunately, for the same frequency there are many patterns of delta bitsstringstream to generate a sinewave. Which one to choose? My first thought was to choose the one that has the lowest THD. After a few months working on this (by testing every possible pattern for each frequency of the 485 ones), I noticed that the optimum patterns, in term of THD, produce different fundamental amplitudes. In practice, this is not good.So, I decided to focus on having, as possible, the same amplitude instead of the lowest THD. Fortunately, for certain practical amplitude, all patterns have low THDs (after filtering) though not necessarily the lowest ones.But simplifying, that much, the hardware has a price, actually a big one. The MCU code cannot be as simple as in the case of DDS. Also, the size of a pattern (table) grows rather exponentially while lowering the sinewave frequency (it is fixed in case of DDS).To avoid generating the 8-bit table of the delta bitsstringsstreams manually, I updated the code to do it automatically (as solving a non-linear equation) for each frequency and save it on an external SEEP memory.I am still working on the project because I had to write 5 different algorithms to cover the 485 frequencies (sub-bands 1 to 5, each 97 frequencies). So far, I did and tested the algorithms of the sub-bands 2 to 5. I hope soon I will finish the last one.In case some of you think it is a good project to share it here (this forum), it will be my pleasure to start a thread about it, so that it could be discussed and see if it could be simplified even more (mainly its code).Cheers,Kerim

author: Yansi
author_rank: Super Contributor
timestamp: November 10, 2024, 07:43:27 pm
content: delta stream... do I understand it right, that it is a classic sigma-delta stream?Also, there are techniques to convert from PCM to Sigma-delta or backwards. Not really familiar with the algorithms, but I remember it also required a lot of table lookups. Seen even some library for STM32 to do this.Please, feel free to share your project. I will not try to reimplement it, I swear.. but I like to read what kind of wizardry is possible with an old atmega.Meanwhile, I will have to setup some workflow for the ATF1504 or similar CPLD, to try implement the DDS core in it. Wondering, if I could even fit in a quadrature DDS.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 10, 2024, 08:59:07 pm
content: Quote from: Yansi on November 10, 2024, 09:02:41 amYou need to also include the adder product terms, and those get costly for wider adders.Based on fitting 12b adder into ATF1502, you might fit 24b into ATF1504, but note that 1502 used parallel loading pins and parallel out, so that fits in a PLCC44 ok.A 24 in 8 out DDS would be pushing pins. 20b may be ok ?Quote from: Yansi on November 10, 2024, 09:02:41 amAn AVR can get to 2MHz ballpark, tho with only an 8 bit X axis lookup, but that's less ideal for 8 bit Y axis DAC, as you miss using ALL DAC values.The STC parts are the fastest 8051's out there, and eclipse the AVR on speed. That's because they now fetch 3 bytes per sysclk, whilst AVR fetches 2 bytes.Using a larger sine table, I get these combinations on paper for latest STC, for a more wide use DDS41.943040MHz/16/2^18 = 10Hz steps, for 1024 table 2.621440MHz adder rate (or 2^19 / 2048 table = 5Hz or 2^20 / 4096 table = 2.5Hz steps)33.554432M/16/2^21 = 1Hz steps for 8192 table, 2.097152Mhz adderThose clock speeds can support 115200, 230400 and 460800 baud speeds with tolerable errors.Mouser stock 2520 SG-8018CG 33.554432M-TJHSA0 OSC 1.8V~3.3V +/-50PPM , or you can use the internal trim baud value of 33.1776Mhz if ~1% RC osc is ok41.943MHz is less common.Arrow have R2R 4610X-R2R-103LF 10K/20k 10SIP, 50+ $0.0946That code includes UART polling exit, and pin toggle for confirmation of adder rate, and a couple of spare boolean exits.There are faster options, if you have a fixed 4 step / decade. I'll check how fast...

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 10, 2024, 09:20:40 pm
content: Using Non-DDS code of a simple paced-table-playback, some quick calcs giveSysCLK = 38.4MHz (this is also a standard TCXO, and can do 115200 Baud < 0.5% error)The loops here are faster, so your filtering is simpler and every sine wave is identical.The pin-update-rates here are 9.6MHz, 6.4MHz, & 2.56MHz/N for 38.4Mhz CLKin - MCU is used as a dedicated UART-select Sine-generator.Code:; Summary STC8H fast Sine table playback to port /N sysclks SYSCLK of 38.4MHz, UART exit polled every loop; Freq SineSteps; 300k 32; 150k 64; 100k 64; 50k 128; 25k 256; 10k 256; 5k 512; 2.5k 1024; 1k 512; 500 1024; 250 1024; 100 1024; 50 1024; 20 1024; 10 1024Addit: that same 38.4MHz clock can support a 32b adder into a 4096 x 8 sine table, for a step size of 425.7474627 micro Hz, with adder rate 1.828571MHz

author: Kleinstein
author_rank: Super Contributor
timestamp: November 10, 2024, 09:47:23 pm
content: The CPLD would only implement the phase accumulator, normally not the lookup table. With an external lookup table one could definitely use the same adress data for 2 memory chips and this way get 2 signals (like quadrature or a 2f signal). It is still extra effort.For the old AVRs a possible solution could be SW DDS in an ISR written in ASM to calculate and output some 3 samples each. So a kind of loop unrolling to reduce the interrupt overhead. So instead of some 60 cycles for 1 sample this would be more like 100 cycles to calculate 3 sampels and output them with a suitable delay. The ISR would start with outputing a precalculated value and only than save the registers. With the data in registers the actual calculation does not take that long. In the 100 cycles estimate for the ISR there would be 20 cyles left for the main code, or some 15%.GCC allows to reserve a few (4 may work, but AFAIK not the Z registers that are needed for the table) registers - so less registers to put to the stack. The main program could be written in C, though with only relatively little processor power left. Avoiding jitter from the delay on calling the ISR may add some extra effort in SW or external hardware. A have done the jitter correction in software and it is not that long, though a bit tricky to program. Chances are one could still get an output rate of some 500 kSPS (40 cycles with 20 MHz clock, as 120-x for 3 sample or 160-x for 4), maybe a little more. This should be sufficient for 100 kHz output frequency with not too much effort for the filter.The extra effort for a 10 bit long table is not that large with a suitable memory address. Using only a 18 bit phase accu and 16 bit frequency word could be sufficient ( ~ 2 Hz frequency steps)The ouput would need a parallel input DAC or maybe a R2R DAC at digital outputs with not so good linearity - but possibly still good enough.The SD modulation instead of an DAC adds extra effort. This may work with a fast µC like ARM or similar, but likely not with an AVR to get 100 kHz.

author: Yansi
author_rank: Super Contributor
timestamp: November 10, 2024, 10:00:24 pm
content: Quote from: PCB.Wiz on November 10, 2024, 08:59:07 pmWhy couldn't I shift the data serially? If I have 24 DFFs to store the phase, another 24 DFFs can store the FTW. I could then simply shift in new FTW whenever needed. Better than 24 wires for sure.Not really sure how the macrocells work in this kind of CPLD (need to study up), but don't tell me a 24bit adder + storage reg with 24bit additional shift-reg is impossible to fit in a 64 macrocell PLD.Damn, need to install Quartus on my new PC, could try it on some EPM7064 PLD, shall afaik be fully compatible with ATF1504.For sure fitting in a sine table is likely not happening, but producing quadrature signals into something like a AD7528 sounds like an interesting feature to think about. And it should not be difficult to implement, due to 90° shift in output address is just tweaking of the uppermost 2 bits if I am thinking right at this time of day... errm, night.//EDIT: Shiiiiiiiiiit. Seems Quartus 13 is no longer available for download. I think it was the last version that supported EPM7000. And also Cyclone II or MAX II. We are screwed!//EDIT2: Found it. I got really scared. See this page:https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/devices-support.html#max%C2%AEseries//EDIT3: Quartus successfully installed, but my VHDL has become sooo rusty. Must get some refresher course or what not :-/

author: KerimF
author_rank: Frequent Contributor
timestamp: November 10, 2024, 11:28:15 pm
content: Quote from: Yansi on November 10, 2024, 07:43:27 pmPlease note I will share it so that it could be implemented by anyoneAnd someone may think to update it using other MCUs for example.For instance, only the code that generates the table of the delta bits stream for each frequency is complex.But the code that reads a table and outputs the serial bits is somehow simple but not as simple as of DDS.Added:In my project, the bits stream is of the basic delta modulation so that only a LPF is needed to get the sinewave.Added:I forgot that in case the modulating signal is a sinewave, applying basic delta or sigma delta won't change the type of the demodulator since the integral of a sinewave is also a sinewave (though shifted 90 degrees).

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 11, 2024, 12:35:46 am
content: Quote from: Yansi on November 10, 2024, 10:00:24 pmYou can do serial shift, but you also need to allow for the carry term macrocells.Broadly, you need 24 shifters + 24 carry + 24 adder sum registers, which adds to > 64.

author: Kleinstein
author_rank: Super Contributor
timestamp: November 11, 2024, 09:17:40 am
content: One can save a little on the shift register and adder: usually the frequency word is a little shorter, like 2 bits less. There should be no need for an extra carry at the output for an overflow. 22 shifters + 23 carry + 24 phase registers is still 69 cells. Not sure if one would need an extra carry cells at the top bits where the adder part is zero.

author: Yansi
author_rank: Super Contributor
timestamp: November 11, 2024, 03:25:46 pm
content: Why do you need a separate macrocell for carry? You do not need to output carry on an output pin, so why can't you include carry logic within the already existing macrocell?Not really familiar with this old CPLD macrocell technology, played before only with modern CPLDs that have same or similar structure (LUT based) to an FPGA. Summing numbers there definitely did not seem costly in terms of resources.Have managed to install Quartus yesterday, will have a go at implementing something, once I refresh my rusty VHDL.Meanwhile have found a flaw in my brilliant quadrature DDS implementation idea: The AD7528 DAC does not have simultaneous load to both DACs, which would lead to a frequency dependent phase error of the generated signals (one ADC will always be updated half the sample clock later). Any ideas if there exists some old PDIP packaged dual 8bit DAC with simultaneous load? So far have found only AD7302, but that one is too slow, 2us settling time//EDIT: So a 20 bit adder requires 61 macrocells and a 10bit adder requires 29 of them. So about 3 times the bit width. Weird. How the hell is the macrocell CPLD architecture so bad at so basic things, especially at the datasheet states how efficient it is in"implementation of compare and arithmetic functions"? Would need to understand more how the macrocells work. Bit disappointed, that the CPLD can't fit damn well even a 20bit shiftreg and 20bit adder + reg.//EDIT2: Out of curiosity, have tried synthesising for EPM3064, which is a newer series (still existed in PLCC44), than EPM7000. Seems slightly more efficient, just 55 macrocells for a 20bit adder + storage reg. So now what?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 11, 2024, 07:00:43 pm
content: Quote from: Yansi on November 11, 2024, 03:25:46 pmYup, DAC's in DIP are Dinosaurs... The clock does not need to be the DDS speed, it can be faster, but then you hit speed limits of EEPROMsQuote from: Yansi on November 11, 2024, 03:25:46 pmI resized my older DDS, and WinCUPL can fit 22 DDS into ATF1504, with swallow of one carry into foldback, and 23 bits just fits by swallowing 4 carry terms into foldbacks,Notice the long carry chains means the clock speed of this will not be high.Ironically, the MCU will have a higher peak byte delivery speed than the CPLD+EPROM

author: Yansi
author_rank: Super Contributor
timestamp: November 11, 2024, 07:18:13 pm
content: Maybe lets step it up a notch to ATF1508 (EPM7128) in PLCC84. With so many pins, I could attach directly a couple of good ol DAC08s (DAC0800) which are plenty fast DACs, still available today in PDIP. PLCC84 is not that large (30x30mm?), miles smaller than what it would take from individual logic chips of course.

author: Yansi
author_rank: Super Contributor
timestamp: November 11, 2024, 08:23:12 pm
content: Tried compiling a design into EPM7128 (ATF1508) with a 20 bit wide adder and the shift reg. why a stoopid 20bit shift reg takes more than 20 macrocells is beyond my understanding. Without the shiftreg (FTW inputs on pins) it took 55 macrocells, with shiftreg it is 96. So it added like 41. Wtf, why?Used this standard VHDL approach:Code:process (clock, sclk, sdata) beginif (rising_edge(clock) and sclk='1') thenFTW_reg <= FTW_reg(18 downto 0) & sdata;end if;end process;that ends up with a DFF reg preceded by a multiplexer.multiplexing between two inputs shall take no more than two input terms and the macrocell can have 5, if I understand it right. Just damn AND together the select signal with the input1 and OR it with the AND of NOT select and input2. Dafuq is the tool doing there?Code:mux_out = (select AND input1) OR ((NOT select) AND input2)//EDIT: Now if I have deleted the the shiftreg and returned back the FTW input using 20 io pins, i get now a total of 76 macrocells for a 20bit adder? WTF//EDIT2: Switched the project back to EPM7064 and got just the 55 macrocells as before. W.T.F. The tool is messed up. Or am I to dumb to understand it?//EDIT3: Switched again to EPM7128, again at 76 macrocells. I give up.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 11, 2024, 08:58:06 pm
content: Quote from: Yansi on November 11, 2024, 08:23:12 pmSomething is awry ? The .FIT file (al alter report equivalent) should tell you where the resource is going.Here are the FIT reports for ATF1504 and ATF1508 targets for a 23b serial in DDS Adder.The 1504 fitter swallow some carry nodes into foldback, which the 1508 does not need to do, so the total PT drops on the 1508 slightly.Code:ATF1504Logic Array Block Macro Cells I/O Pins Foldbacks TotalPT FanIN CascadesA: MC1 - MC16 16/16(100%) 8/16(50%) 16/16(100%) 64/80(80%) 20/40(50%) 0B: MC17 - MC32 16/16(100%) 8/16(50%) 0/16(0%) 56/80(70%) 24/40(60%) 0C: MC33 - MC48 16/16(100%) 8/16(50%) 0/16(0%) 49/80(61%) 21/40(52%) 0D: MC49 - MC64 16/16(100%) 1/16(6%) 0/16(0%) 16/80(20%) 16/40(40%) 0Total dedicated input used: 2/4 (50%)Total I/O pins used 25/32 (78%)Total Macro cells used 64/64 (100%)Total Flip-Flop used 46/64 (71%)Total Foldback logic used 16/64 (25%)Total Nodes+FB/MCells 80/64 (125%)Total cascade used 0Total input pins 4Total output pins 23Total Pts 185ATF1508Logic Array Block Macro Cells I/O Pins Foldbacks TotalPT FanIN CascadesA: MC1 - MC16 16/16(100%) 8/16(50%) 0/16(0%) 56/80(70%) 24/40(60%) 0B: MC17 - MC32 16/16(100%) 8/16(50%) 0/16(0%) 56/80(70%) 24/40(60%) 0C: MC33 - MC48 16/16(100%) 7/16(43%) 0/16(0%) 49/80(61%) 21/40(52%) 0D: MC49 - MC64 16/16(100%) 0/16(0%) 0/16(0%) 16/80(20%) 16/40(40%) 0E: MC65 - MC80 4/16(25%) 2/16(12%) 0/16(0%) 4/80(5%) 4/40(10%) 0F: MC81 - MC96 0/16(0%) 0/16(0%) 0/16(0%) 0/80(0%) 0/40(0%) 0G: MC97 - MC112 0/16(0%) 0/16(0%) 0/16(0%) 0/80(0%) 0/40(0%) 0H: MC113- MC128 0/16(0%) 0/16(0%) 0/16(0%) 0/80(0%) 0/40(0%) 0Total dedicated input used: 2/4 (50%)Total I/O pins used 25/80 (31%)Total Macro cells used 68/128 (53%)Total Flip-Flop used 46/128 (35%)Total Foldback logic used 0/128 (0%)Total Nodes+FB/MCells 68/128 (53%)Total cascade used 0Total input pins 4Total output pins 23Total Pts 181

author: Yansi
author_rank: Super Contributor
timestamp: November 11, 2024, 09:37:58 pm
content: What tool do you use for the CPLD design? I am in Quartus IDE, was thinking using the trick with converting POF file to JED for ATMEL. Not seen much other good options to program the ATF1500, apart from some old WinCUPL software that of course uses weird CUPL language and is (so I read) full of bugs.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 11, 2024, 11:05:48 pm
content: An alternative approach using PLDs and that can avoid the EPROM entirely, is to use what I called a Swallow Sine generator. Found my dusty notes on this...This fits better in a CPLD, and operates very similar to a switched capacitor filter approach. You generate a clock some N times the Fout, and vary that clock speed to change frequency.The approach is quite simple, you have two counters and a couple of flags.One counter is a Up/Down triangle, with pause ability.The second smaller swallow/pause counter is loaded from a Y value table, and sets the Pause counts, which rapidly get longer at the flatter sine peaks.Result is asine-counterthat is just like a ROM table, with an added benefit the fit at the highest slopes is very good and every possible Y axis step is used. (no lost codes)eg a 7 bit Up/Dn triangle counter and a 4Bit swallow counter and a couple of flags fit into 13 Macrocells + 8 MC for ROM extension ie easily fits into ATF1502X-Axis is close to Y*pi, ( 128*pi = 402.1238) my notes say 396 for best fit, but 400 might be chosen for ease of clock calculations.Here is the visual effect :

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 11, 2024, 11:13:01 pm
content: Quote from: Yansi on November 11, 2024, 09:37:58 pmI use WinCUPL. It's like working in Assembler, but it is quite good as collapse of terms, so I code for clarity and let the tools simplify.Most of the heavy lifting is done by the Atmel Fittereg here is the ROM tables I mentioned above in CUPL syntaxCode:$IFDEF YScale128/* ~~~~~~~~~~~~~~~~~ Sine Load Enable 1b, for Swallow Pause counter ~~~~~~~~~~~~~~~~~ *//* This compiles to 16 PT */TABLE TriCtr => DoPause {'d'0 => 'd'1;'d'1 => 'd'1;'d'2 => 'd'1;'d'3 => 'd'1;'d'4 => 'd'1;'d'5 => 'd'1;'d'6 => 'd'1;'d'7 => 'd'1;'d'8 => 'd'1;'d'9 => 'd'1;'d'10 => 'd'1;'d'12 => 'd'1;'d'13 => 'd'1;'d'15 => 'd'1;'d'17 => 'd'1;'d'20 => 'd'1;'d'23 => 'd'1;'d'28 => 'd'1;'d'35 => 'd'1;'d'92 => 'd'1;'d'99 => 'd'1;'d'104 => 'd'1;'d'107 => 'd'1;'d'110 => 'd'1;'d'112 => 'd'1;'d'114 => 'd'1;'d'115 => 'd'1;'d'117 => 'd'1;'d'118 => 'd'1;'d'119 => 'd'1;'d'120 => 'd'1;'d'121 => 'd'1;'d'122 => 'd'1;'d'123 => 'd'1;'d'124 => 'd'1;'d'125 => 'd'1;'d'126 => 'd'1;'d'127 => 'd'1;}/* ~~~~~~~~~~~~~~~~~~~~~ Sine Load Value 3-4b, for Swallow Pause counter ~~~~~~~~~~~~~~~~~~ *//* this compiles to 6.7.6.15 PT */TABLE TriCtr => Sw {'d'0 => 'd'12;'d'1 => 'd'5;'d'2 => 'd'4;'d'3 => 'd'2;'d'4 => 'd'2;'d'5 => 'd'1;'d'6 => 'd'2;'d'7 => 'd'1;'d'8 => 'd'1;'d'9 => 'd'1;'d'10 => 'd'1;'d'12 => 'd'1;'d'13 => 'd'1;'d'15 => 'd'1;'d'17 => 'd'1;'d'20 => 'd'1;'d'23 => 'd'1;'d'28 => 'd'1;'d'35 => 'd'1;'d'92 => 'd'1;'d'99 => 'd'1;'d'104 => 'd'1;'d'107 => 'd'1;'d'110 => 'd'1;'d'112 => 'd'1;'d'114 => 'd'1;'d'115 => 'd'1;'d'117 => 'd'1;'d'118 => 'd'1;'d'119 => 'd'1;'d'120 => 'd'1;'d'121 => 'd'2;'d'122 => 'd'1;'d'123 => 'd'2;'d'124 => 'd'2;'d'125 => 'd'4;'d'126 => 'd'5;'d'127 => 'd'12;}$ENDIFThose tables are easily generated by an external script that does 'best fit' to the sine, by comparing skip with no skip choices for each X axis step.

author: Yansi
author_rank: Super Contributor
timestamp: November 12, 2024, 10:20:41 pm
content: I have tried fitting a not really well optimized VHDL design of quadrature DDS in an ATF1508 and succeeded. Requires only the external ROM, that gets multiplexed between DACs, with internal registering so both DACs can be updated at same time. But haven't done any proper verification, just interested to see, if it can fit.No idea about the CUPL langueage, or tools to use further use to flash the ATF1500 series PLD. Can you please share what tools you use for that?Meanwhile, I have found another amazing gem: Would you guess, that a PDIP40 CPLD is still being made to this day? What a gem!https://ww1.microchip.com/downloads/en/DeviceDoc/doc0777.pdfBut lemme make an educated guess, why these may be still made: Critical infrastructure and military. (so subpartnumbers seem restricted under EAR, which is otherwise strange for such basic PLD).

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 12, 2024, 11:26:15 pm
content: Quote from: Yansi on November 12, 2024, 10:20:41 pmThe .FIT file will show how well that fitted and how much is spare, or did you just do a pof2jed ?Quote from: Yansi on November 12, 2024, 10:20:41 pmCUPL is small and fast, and has a functional simulator, but has little timing support. Roughly equivalent to working in Assembler on MCUsDevice Programming is not hard, if you leave JTAG enabled - most JTAG flows work .If you accidently disable JTAG, then you need a high voltage enable dance, or a device programmer.See this thread toohttps://www.eevblog.com/forum/fpga/re-programming-secure-microchip-atf150x-series-cpld-devices/Quote from: Yansi on November 12, 2024, 10:20:41 pmYup, I was going to mention the ATF2500C, as that still comes in PLCC and DIP. You will need to find a programmer that works for that !WinCUPL does support that, it's designed like a 22V10 on steroids, so is less flexible than ATF150x.With only 48 FF's it's a bit limiting for what you want to do.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 13, 2024, 03:24:29 am
content: Quote from: PCB.Wiz on November 11, 2024, 11:05:48 pmQuoteI expanded on this into a ATF1504, and that can fit a programmable scale to give the OP's 1 2 5 10 steps and Sine generate all inside the CPLD, just the DAC is needed,Master clock is 40MHz, giving 400 time steps & 128 voltage steps for the 100kHz sine out - ie a high quality sine.Code:Freq OUT 100 200 500 1k 2k 5k 10k 20k 50k 100k = 10 choicesClock Divide by 1000 500 200 100 50 20 10 5 2 1 = 4 bit Rotary Switch selectIt can also fit a PWM DAC, but that hits practical frequency ratio effects, as ideally you want the DAC period to be faster than the sine step time.Below about 5KHz a PWM DAC may be a possible solution ?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 13, 2024, 03:43:27 am
content: Quote from: Yansi on November 12, 2024, 10:20:41 pmTable ROMs and DACs are both a pain in 2024... clunky and lots of wiring, and not cheap. lcsc have a parallel DAC in TSSOP28 for sub $1, but most are now serial.I did see this in todays news :Key Paraments of SLG47011Vdd = 1.71 to 3.6 VSAR ADC: up to 14-bit, up to 2.35 Msps in 8-bit modePGA: six amplifier configurations, rail-to-rail input/output, 1x - 64x gainDAC: 12 bit, 333 kspsHardware Math block for multiplication, addition, subtraction and division operationsFlexible 4096 words Memory table blockOscillators: 2/10 kHz and 20/40 MHzAnalog temperature sensorHighest number of highly configurable Counter/Delay blocksI2C and SPI communication interfacesAvailable in a tiny 16-pin QFN 2.0 mm x 2.0 mm x 0.55 mm, 0.4 mm pitch packageJust trying to digest the data, they seem to have parallel paths and the memory block can feed the DAC, so that can manage the Sine ROM + DAC.DAC data looks quite good, slew rate looks ok, and settling time should be good for many samples at 100kHz.It would keep up with most MCU DDS designs, but may be the limiting factor at the highest step rates.Not as fast as a CPLD can manage steps, but that was well above the original specs.I see Mouser have stocks of DIP mounted versions, and the parts themselves are similar to decent MCU's with DAC 3,000 : $0.692SLG47011V-DIP 20-pin DIP Proto Board. Perfect for breadboarding and fast prototypes.https://www.mouser.com/c/?q=SLG47011

author: KerimF
author_rank: Frequent Contributor
timestamp: November 13, 2024, 09:10:29 am
content: If for my DSS (Delta Sinewave Synthesis) project, I use 16 MHz crystal, instead of 8, and let the delta clock be 40 times only the highest frequency of the sinewave (that is, 100 KHz * 40 = 4 MHz). The original range (20 to 20,000 Hz) becomes 100 to 100,000 Hz.My problem is that we have 2 hours of mains electricity at night and 2 hours in daylight, on Friday, Saturday and Sunday, and only two hours in daylight on the remaining 4 days of the week.I mean I can't work as fast as you may do out there, and the project's code is not simple (before getting all 485 tables). Naturally, during those few hours, I need to also do other things.For instance, this wasn't the case before year 2011 when the world decided, all of a sudden, to save the people among whom I was born and live. In the past golden years (before year 2011), we had mains electricity 24/7.

author: Yansi
author_rank: Super Contributor
timestamp: November 13, 2024, 02:21:26 pm
content: PCB.Wiz: No SMT components allowed, period. This is a THT project only. When SMT, I could do it whole design in SMT with modern parts, but that's not the point of this exercise of THT right.Btw, thought greenpaks are huge pain in the ass to use. But no experience, never had even the slightest desire to use them.Quote from: PCB.Wiz on November 12, 2024, 11:26:15 pmYeah, 48 DFFS not many, but still, PDIP40 CPLD has a good wow effect too it. Maybe will use it for something else in the futureThank you for sharing, i think I have seen already somewhere mentioned, that disabled JTAG could be unlocked back by applying somewhere 12V trough a resistor. What USB-JTAG thing you use for programming? I guess the support of the official ATMEL tools like AtmelISP will be nonsurprisingly limited to atmel specific tools. Are there any other options? Not really want to invest 100+$ for a specific atmel device programmer just to try a few stupid things with old CPLDs.Have seen OpenOCD may actually support the ATF1500 series, any experience with that? That way I could use almost any imaginable JTAG thing, but I would need to get some kind of SVF file? I know POF2JED exists, but how to get SVF out of the JED file?Where did you get the WinCUPL? Seems no download button exists on the Microcyp website. Seems also a very old WinXP era software, how well does it cope with Win10 or similar? Would like to give a go at CUPL, as I am very dissatisfied with the bloated fitter in Quartus, that is obviously much better suited for large FPGAs and complex designs.Quote from: KerimF on November 13, 2024, 09:10:29 amKerimF: Am very sorry for that and I hope the situation will get improved soon for you.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 13, 2024, 06:23:41 pm
content: Quote from: Yansi on November 13, 2024, 02:21:26 pmThis looks like DIP to me ?

author: PCB.Wiz
author_rank: Super Contributor
timestamp: November 13, 2024, 06:41:27 pm
content: Quote from: Yansi on November 13, 2024, 02:21:26 pmHmm.... I dug and found a link herehttps://github.com/peterzieba/5Vpldthat gives this, which seems still alivehttps://www.microchip.com/en-us/products/fpgas-and-plds/spld-cplds/pld-design-resourcesThe github page mention using command line CUPL only, which is what I do, that seems to still work fine on 64b Win11.Atmel tools can work on almost any cable - I've used a FT2232H on a Lattice board.SVF files are created by the Atmel ISP tools, as an option.

author: Yansi
author_rank: Super Contributor
timestamp: November 13, 2024, 08:11:01 pm
content: Quote from: PCB.Wiz on November 13, 2024, 06:23:41 pmHey you little provocateur...Thanks very much for the github link, did not find this page (yet). Seems a very well compiled well of information (pun intended). Now I need to get some of the ATF1504/1508 in my hand, so I could at least do something. Then we could dig more in depth to optimize stuff. And measure the performance.Surprised that the atmISP supports so broad range of HW probes.

author: KerimF
author_rank: Frequent Contributor
timestamp: November 24, 2024, 11:01:31 am
content: I attached here [DSS_1stCode.zip] the first code of the DSS (Delta Sinewave Synthesis) project. DSS is based on digital delta modulation by using an MCU (as ATmega32).DSS_1stCode.zip includes the following 5 files: DSS_1stCode.asm DSS_1stCode.hex [andlow fuses=0x24, high fuses= 0xD1] DSS_1stCode.lst ForDSS_1stCode.png [the schematic] deltaSteps_Apeak115.txt [results copied from MCU EEPROM]The main advantage of using the DSS topology is its very simple hardware (1 output pin + a non-critical LPF).Its second advantage is that its sinewave outputs are jitter-free (even at the lowest frequency of the generated spectrum).Its disadvantage is that if it will be implemented from scratch (as done here), the needed codes are somehow very complex.Let us recall that a delta bits stream is defined by 3 parameters: The frequency of the delta clock (Fclock). The number of delta bits in a cycle (Nbits). The delta step (Dstep).As you will see, in this first code, the delta frequency is irrelevant.The Nbits of interest starts from 96 bits up to 3088 bits per cycle, to produce 485 frequencies (Findex= 0 to 484). The table ‘NbitsTb:’ gives the ‘Nbits’ for every ‘Findex’.The missing parameter to be found by this first code is the ‘delta step’. The code has to find ‘Dstep’ for every ‘Findex’, so that the generated amplitude is close to the fixed amplitude (Apeak). Apeak is assumed to be 115. After running the code (it takes around 55 sec), the values of ‘Dstep’ for all ‘Findex’ are saved in the MCU EEPROM (its size 1024 bytes); each ‘Dstep’ takes two bytes.The next code (step 2) which I am working on, the MCU will output the delta bits stream when it receives, in one way or another, the requested frequency ‘Findex’ (0 to 484). It uses the results of the 1st code (included as a table). Actually, there will be two bands (2*485 = 969 frequencies total); hi_band (with 2,000,000 Hz clock) and lo_band (with 62,500 Hz clock).I hesitated to introduce my work about this DSS topology because most programmers are not familiar with codes written fully in assembly language. Since many decades ago, I had to write in assembly (Z80, C51 then AVR) because I wasn’t allowed to download/buy any genuine high language compiler for PCs or MCUs. The only genuine compiler which I got long ago, is the one I bought in the package of 'BorlandC 3.1'. Whenever necessary, it helps me write an in-house DOS program (in C) to be run on my laptop.Obviously, if no one will be interested in this rather ‘weird’ project, I guess there will be no need to bother the readers here about it anymore by also presenting its remaining parts. After all, I did it for myself since I can't get advanced ICs and precision components (I worked on DSS just for its very simple hardware).Cheers,KerimPlease note that the attached code is the fruit of many months of debugging. Although it is now bug-free, various mistyping in comments may still exit in it.

author: Yansi
author_rank: Super Contributor
timestamp: December 05, 2024, 09:16:13 am
content: Hello KerimF,thank you for sharing with us your work. No need to be afraid of assembly, I am also an "old schooler", who did actively program in assembly for several architectures, 8048, 8051, AVR, STM8, ARM included. But sure I find it inconvenient to use for new development, there are much better options. I leave assembly these days only for specialized hobby projects like these. But it is a good skill to have even nowadays, as understanding what mess the compiler did of your code, can be really useful for example when optimizing complex code, or utilizing special instructions, that the compiler can not produce by itself (efficiently, if at all).What I still not get about the DSS synthesis, how come only "non-critical LPF" can be sufficient. Have you done any measurements (spectral purity, THD or such) for the output? I think for only a light filter to be enough, the bit stream frequency must be rather in high ration, compared to the maximum frequency synthesized.So for this example, what is you least bit time resolution, maximum synthesized frequency and what LP filter was used? Just to get an idea what is needed or what is used there.Meanwhile sorry that I haven updated you, I am very busy with a lot of important things now and i still did not get my hands on any of those ATF1500 CPLDs yet. Did not order them directly from Mouser, needed to get a bigger order first, otherwise the Mouser would become very expensive for me.Thanks,Y//EDIT: Ha! Just received a package with a few pieces of ATF1508. Hope I can try soon.

author: KerimF
author_rank: Frequent Contributor
timestamp: December 05, 2024, 04:17:42 pm
content: Quote from: Yansi on December 05, 2024, 09:16:13 amI started the project to cover the audio spectrum only, 20 to 20,000 Hz, to test the sensitivity of my degrading hearing with age, I am 75, which I inherited from my parents. I know there are other ways to do it, but I liked to have a digital tool I design besides giving my brain something serious to think of to also avoid as possible the rather fast degradation of its neuron's power with age.The delta bit rate is 2,000,000 Hz for my high band of the audio spectrum (20,833.33 Hz down to 647.67 Hz). And it is 62,500 Hz for my low band (651.04 Hz down to 20.24 Hz.Since you replied, I will also prepare the 2nd code for upload. It generates 970 frequencies (485 frequencies in each band)The actual DSS generator which I am preparing for EEV is simply an experimental one to introduce the DSS topology for this specific project. It gets the frequency index (0 to 969) manually. In a real application, it gets it by a peripheral, as TWI, which also can interrupt the DSS loop before the generation of another frequency.It will have three thumbwheels of BCD encoder (hundreds, tens and units). Also, there is a push-botton switch. When activated (on-off), the frequency whose index is set on the 3 thumbwheels will be generated.As I mentioned previously, the 2nd code uses the table generated of the 1st code (saved in the MCU EEPROM). The table (485 entries) gives the digital delta step for each frequency (the delta step of index 485 of the low band has the same one of index 0 of the high band and so on). The delta steps are calculated to get as close as possible the same amplitude for all generated frequencies. In the previous attached 1st code, the amplitude is set to 118/256 (256/256 = Vcc/2). The amplitude of the DSS generator (2nd code) which I am preparing is assumed 128/256 instead of 118/256.I think finding the optimum delta step to get the lowest possible THD of a generated sinewave could also be done by finding the highest amplitude of its fundamental harmonic. This is somehow simple to do by multiplying the internal digital sinewave by the delta bit stream from which is derived. In this case, multiplications are done actually by additions and subtractions.There is a lot to say about DSS in general, as it is the case of DDS.So far, this project could be seen just a basic way to implement it (done for my need in the first place).Quote from: Yansi on December 05, 2024, 09:16:13 amAs you see, in this project, the bit stream frequency is a bit less than 100 times the maximum frequency synthesized. The lowest number of bits in one cycle is 96.Note:I don't know how fast I can prepare the promised DSS generator (I explained above) because of the unusual events in my city in these days.Kerim

author: KerimF
author_rank: Frequent Contributor
timestamp: December 14, 2024, 07:39:38 am
content: Added:Please ignore the message below. Many hours after I posted it, I realized that I did a mistake when I built the basic DSS generator in a hurry.My city has mains AC for 2 hours only every 24 hours. When I revised my calculations, I knew there is something wrong in the circuit I built on a breadboard; I placed 10K ohm instead of 1K (the 1st resistor of the 3-RC LPF). This added about 10 dB attenuation at the relatively high frequencies.Now, I wait the next 2 hours of mains AC to take new measurements.=============================================================================================At last, I was able to build the basic circuit of the delta sinewave generator.On the scope, I got pure audio sinewave traces for all frequencies [indexes 000 to 969], but... there is always a ‘BUT’I discovered that I missed an obvious, but crucial, point while I was focusing, all the time, in generating ‘pure’ sine waves.The point, I missed, is that the generated sinewave amplitude is ‘inversely proportional’ to frequency. Speaking practically, this could be seen a serious drawback because a good signal generator provides the same amplitude while varying the frequency.Now, I will likely try to find out if there is a simple filter/amplifier whose gain is proportional to frequency (audio frequencies).Otherwise, I will drop my DSS project, for good, though it helped my old brain be active for many years (while my business as a designer has been paralyzed to a great extent because of various local events).Before building this basic DSS generator, I was planning to combine its 1st and 2nd codes in one, to make it more practical.Now, I am not sure if it is worth uploading it.Kerim

author: KerimF
author_rank: Frequent Contributor
timestamp: December 21, 2024, 07:46:04 pm
content: The attached project, DDSSaudioGenerator_EEV_v2.zip, is about an experimental circuit, hardware and firmware, to introduce the concept of DDSS, Digital Delta Sinewave Synthesis. Its MCU is ATmega32A.In real applications, there are no thumbwheels and a switch (as seen on DDSSaudioGenerator_v2.png). A second MCU (connected to the DDSS generator via a serial protocol) is added to run all the functions, other than generating the sine waves, needed by the application and the user.The attached DDSSaudioGenerator_EEV_v2.zip includes:1- DDSSaudioGenerator_v2.asm [8 MHz, its frequencies are doubled if 16 MHz ]2- DDSSaudioGenerator_v2.hex3- DDSSaudioGenerator_v2.lst4- DDSSaudioGenerator_v2.png5- DDSS_Bits_Frequencies_v2.txt6- DDSSaudioGenerator_fuses_v2.txtThe code (and its schematic) was tested on a breadboard. It consists of 3 parts:Part_1: It generates the table, in SRAM, of sinewave whose bits/cycle, Nbits, is known [the lowest Nbits=96, the highest Nbits=3088, see DDSS_Bits_Frequencies_v2.txt]. Its algorithm is somehow related to CORDIC algorithm.Part_2: It generates the table, in SRAM, of the delta bits sequence [size=12 to 386 bytes, Nbits/8] by using the internal sinewave table and a preset delta step for each Nbits [table STEPtbl:]. Its algorithm is based on the basic delta modulation (comparing then adding or subtracting for the next comparison).Part_3: It outputs the delta bits sequence by reading its table in SRAM. There is a fast loop for the high band [delta clock = 2 MHz], and a slow loop for the low band [delta clock = 62,500 Hz, 2 MHz/32].Since the size of the MCU SRAM is only 2024 bytes, I had to divide the band of 485 frequencies to five sub-bands; each has its own paths in the code:band_0, from 000 to 096 or 485 to 581 [Nbits=96 to 192]band_1, from 097 to 193 or 582 to 678 [Nbits=194 to 386]band_2, from 194 to 290 or 679 to 775 [Nbits=338 to 772]band_3, from 291 to 387 or 776 to 872 [Nbits=776 to 1544]band_4, from 388 to 484 or 873 to 969 [Nbits=1552 to 3088]To run the generator, the switch needs to be closed first, if it is not closed already (idle state). Otherwise, the first frequency will be the one whose frequency index is set on the three thumbwheels [000 to 969, see DDSS_Bits_Frequencies_v2.txt]And while the generator is running, a new frequency whose index is set on the 3 thumbwheels will be generated when the switch (or push-botton) will be closed then re-opened. (While the switch is closed, the output is idle.)Note:I renamed DSS to DDSS (Digital Delta Sinewave Synthesis) to avoid confusion. DSS could also mean Digital Sinewave Synthesis.For instance, I think it is very clear now that the code of the DDS concept, Direct Digital Synthesis, is much easier than of the DDSS. Only the hardware of the DDS, like of any parallel DAC, is not as simple as of the DDSS which is a serial one.Kerim