Regarding JK flip flops. - Page 1
Forum section: electronics / beginners

author: mindentropy
author_rank: Contributor
timestamp: December 18, 2011, 09:17:59 pm
content: Hi,I am trying to understand and analyze JK flip flop's (using RS flop flop i.e. using NOR gates). I have written out the characteristic table and when I give Q = 1, J=1 and K = 0 I am trying to analyze the Q' (Q complement) by giving the intial state to 0. I find that Q settles to 1 (i.e. Q(t+1)) but Q' oscillates between 0 and 1. How is this fixed? Is the Q' needed in JK flip flops? Also why do textbooks don't talk about Q' in JK or D or T but only Q and Q(t+1) ?Thanks.

author: IanB
author_rank: Super Contributor
timestamp: December 18, 2011, 10:28:59 pm
content: The output Q' is the complement of Q, which means it is always the opposite of whatever Q is. In other words, Q' = NOT Q. As such, Q' does not take part in the operation of the flip flop, it is simply determined after the operation is complete by inverting whatever value Q ends up with.If you want to think of it in terms of logic, pretend the flip flop doesn't have a Q' output at all, just the normal Q output. Now put a NOT gate after the Q output. The output of the NOT gate will be Q'.

author: amspire
author_rank: Super Contributor
timestamp: December 18, 2011, 10:36:11 pm
content: I am a bit puzzled about your question.For a start the Q compliment output is always just the inverse of Q. It is not possible to get both the outputs high or low at the same time when the flip-flop is stable. So if you know Q(T+1), you know the state of the Q'(T+1).The whole purpose of the JK flip flop is that there are no undefined states. The (T+1) state will always be known from the (T) state for any combination of J and K inputs, and the Q' output is always the compliment of the Q output.Are you using the correct clocked SR flip flops circuits to build the JK flip flops (ie you need a minimum of 4 gates to build the SR flip flop)?Richard.

author: Tony R
author_rank: Regular Contributor
timestamp: December 19, 2011, 03:01:59 am
content: The truth table for a JK is the followingJ K Q0 0 Q No Change0 1 0 Reset1 0 1 Set1 1 Q' InvertIn all honesty i try to shy away from using JK Flip Flops in design, the logic to control them gets more complicated, However you can take any flip flip and change it to any other ones.As for what is going on with your example it should not be oscilating, However in labs i have spent 2 hours trying to figure out why i was getting a odd oscillation (at the clock frequency) which was cased by the ground never being connected (duh!) check to make sure of that.The Q' comes in handy if you have to feed it back into the input, no need for an inverter. So is it needed? not really... but the point is it should work, so that means something could be wrong with your chip or your circuit which could prove to be problematic in the future.

author: mindentropy
author_rank: Contributor
timestamp: December 19, 2011, 10:53:05 am
content: Quote from: amspire on December 18, 2011, 10:36:11 pmHow do you ensure flip flop stability before using i.e. how long should you wait?

author: amspire
author_rank: Super Contributor
timestamp: December 19, 2011, 11:28:21 am
content: Quote from: mindentropy on December 19, 2011, 10:53:05 amWhen you power up, it could end up in either state, so to do anything useful, you always have to set it to an initial state. So, for example, if you have a counter, you might set all the flip flops to "0" initially. Then on every clock pulse, it counts up. If you look at any clocked flip-flop specifications, there is "propogation delay time" which is the amount of time from the specified clocking edge till the outputs are stable. This propogation delay time is the maximum you ever have to wait before you use the output state.In the original 7473 JK flip flop, it was about 40nS. In the modern higher speed versions it will be in the low nS range. ECL JK flip flop are often around 500pS propogation delay.

author: EEVblog
author_rank: Unknown
timestamp: December 19, 2011, 11:39:30 am
content: As an aside, don't forget nasty stuff like slow slew rate input clock signals and set up and hold times.Meta-stability can ruin your day.Dave.

author: deephaven
author_rank: Frequent Contributor
timestamp: December 19, 2011, 12:07:58 pm
content: Quote from: EEVblog on December 19, 2011, 11:39:30 amI think you could do a whole blog on Meta-stability Dave

author: amspire
author_rank: Super Contributor
timestamp: December 19, 2011, 12:43:01 pm
content: Quote from: deephaven on December 19, 2011, 12:07:58 pmAnd ruin everyone's day?

author: McMonster
author_rank: Frequent Contributor
timestamp: December 19, 2011, 02:00:33 pm
content: Quote from: deephaven on December 19, 2011, 12:07:58 pmOr a blog about hazard and race conditions in digital circuits. It's much simpler and would take less time to explain the basics.