VNA One Port Fixture De-Embedding Experiment - Page 1
Forum section: electronics / rf-microwave

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 05, 2021, 09:57:33 am
content: Hi All,I'm currently conducting an experiment and would like some advice/opinions/direction from any gurus out there.I need to de-embed a complicated fixture out of a 1 port measurement.I'm effectively measuring a section of a custom-made ASIC to characterize the small-signal AC impedance. The chip sits on a test PCB (designed by another individual) which allows for the rerouting of signals through jumpers. The problem is that the effective multipath gives me ridiculous parasitics, even with the jumpers disconnected. I could estimate the equivalent electrical model by looking into the port- but I'm not too sure what the best way to go about that.Additionally, the traces on the PCB are not 50 ohms (to my understanding). Since they're not 50 ohms, I've gathered I can't do a simple port extension where I just assume there's some extra transmission line present.Calibrating up to the chip footprint isn't a possibility as I don't have a matched load of that form factor, and the analyzer I have doesn't support unknown load calibration (even if it did, I don't have anything with acceptable precision).I've done some reading and apparently, you can measure open and short conditions to calibrate out the test fixture. The test chip sits in an elastomer socket, so it would only be possible to make open measurements, and not short. I assume this isn't sufficient?My really silly (maybe not so) approach:Can't I just calibrate so that the plane is at the end of my cable, connect it to my test PCB, and take "reference" S_11 measurements. After inserting my chip I can then take the S_11 measurement again, and then simply divide the measurement by the "reference". (i.e. abs(S_11/S_11,ref)).I don't want to do a full EM simulation and parasitic extraction. It is not worth the time. I have spun a new PCB with a significantly simplified measurement chain, however, that will still need correction so the above applies.For some extra context, I'm using a R&S ZNL. I've tried all the built-in de-embedding features but I'm not too sure if they save their offsets to exported touchstone files.Any tips/tricks/advice (or even pointing me to some good resources, I've read most of the app notes out there) would be appreciated.Thanks!EDIT:If I wanted to go down the route of finding the equivalent lumped model, I would have to estimate it somehow. Would TDR help me out? Or would it be best done in the frequency domain (as implied above).

author: E Kafeman
author_rank: Regular Contributor
timestamp: May 06, 2021, 12:13:56 am
content: Semiautomatic port forwarding in time and attenuation can be done in AnTune for open and/or short.AnTune is a Windows/Labview software.Do a regular VNA calibration, preferable with a short coaxial cable added during calibration that is around same length as the unknown transmission line, if it is a longer transmission line, for best precision if only open or short can be calibrated for.It is then relative easy to find transmission line impedance or deembed it, setting up any complex impedance curve as reference and much more in AnTune.VNA need to be connected to PC and AnTune use NI-VISA to communicate.From AnTune is it easy to store and reread S11 Touchstonbe files with or without calibration added.It is fully functional free to try.If measuring active TX, do not overload VNA, and use AnTune function for sliding window to filter spurious.Here is auto port forwarding time and attenuation performed for a transmission line:https://youtu.be/RyMFun_KhAc?t=301

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 06, 2021, 03:05:44 am
content: Quote from: E Kafeman on May 06, 2021, 12:13:56 amI can calibrate out the coax cable up to the SMA connector that mates with the test PCB. That's the problem, the length of the "unknown" transmission line is.... unknown! And an even bigger problem, it may not even be a 50 ohm line, and it certainly has multiple parallel branchesQuote from: E Kafeman on May 06, 2021, 12:13:56 amThe R&S ZNL already has this feature (for $100k, you'd hope so). I was asking if there was a way to:1) Estimate the equivalent lumped model.AND/OR2) What the best way to calibrate/deembed a test fixture out of a 1 port measurement, where I can only leave the other end open.It seems like your software is doing what I described in my first post, simply taking a "reference" measurement and performing a delta measurement.

author: E Kafeman
author_rank: Regular Contributor
timestamp: May 06, 2021, 07:46:30 pm
content: Quote from: Nitrousoxide on May 06, 2021, 03:05:44 amThat can be a bit hard to handle by any software and makes need for precision harder to achieve.Quote from: Nitrousoxide on May 06, 2021, 03:05:44 amTo a certain degree yes but AnTune is more of an specialist tool mainly intended to handle complex wideband impedance matching, using complex source and complex load impedance and automatic matching with lossy real S-parameter components and if preferred automatic selected topology. Such things do not exist in ZNL. As best can you manually add virtual fixed ideal component values in ZNL.Quote from: Nitrousoxide on May 06, 2021, 03:05:44 amYes it is possible in AnTune. Not a single button solution but four or five buttons. Up to four element can be calculated with or without user set preferred topology.Quote from: Nitrousoxide on May 06, 2021, 03:05:44 amAs the unknown transmission line have several branches will all branches be included in eventual reflection.A possibility to identify correct electric length is if short can be found by manually short-cutting with a blank PCB placed in the socket.You can estimate short to have about same reflection attenuation and similar phase delay as for open but if high amount of precision is needed must also short parameters be measured.

author: coppercone2
author_rank: Super Contributor
timestamp: May 07, 2021, 12:34:11 am
content: rebuild it with a bunch of RF relays and digital control?

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 07, 2021, 02:19:39 am
content: Quote from: coppercone2 on May 07, 2021, 12:34:11 amIn principle sounds good, but I think it would be a bit excessive since this is really only a test jig, plus the layout area added from the extra relays would introduce more parasitics and more of a headache.Quote from: E Kafeman on May 06, 2021, 07:46:30 pmWow, I never thought of that.... Chopping up a small square of copper to fit in the socket. I can do this fairly easily since it's an elastomer socket. I just need to be careful to mill out any connections near power supplies (or measure the short params with the board powered down).I'll give AnTune a try and se how it turns out.My original plan that I had cooked up was to import the measurement of the test fixture into MWoffice and then perform optimization on a lumped element network that sits in between the stimulus port and the 1 port parameter file to reduce the reflection coefficient to zero, meaning that the total power reflected would be absorbed and thus it would be the conjugate impedance.

author: virtualparticles
author_rank: Regular Contributor
timestamp: May 07, 2021, 07:08:54 pm
content: I believe you'll have some difficulty with this. No matter how you look at, you need to measure three known things at the chip interface and then calculate the correction matrix. One point simply won't be enough. You could arrange for there to be a short at the Device Under Test (DUT) pin and then an offset short and then another offset short such that the three curves are spread out on the Smith Chart over some frequency range. This won't work to zero frequency of course. You could use an open, a short, and then an offset short as well which will work over the frequency range where the offset short is about 45 degrees long or 270 degrees long at the frequency of interest.I'll be doing a webinar on 1-port calibration next week if you're interested:https://www.bigmarker.com/copper-mountain-technologies/Full-1-Port-VNA-Calibration-Math-with-Python-Code?utm_bmcr_source=brianAttached is the 1-port math if you just want to cut to the chaseThe three cal pieces must be widely distributed on the Smith Chart or the matrices will be ill-conditioned and blow up.

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 08, 2021, 05:17:57 pm
content: Amazing, thank you for sharing. I'll most certainly check it out.Would that be analogous to the conventional method of conversion to T matrices and de-embedding?I've seen that two points are sufficient (an open and a short) for calculating equivalent extension losses and length (but probably not for a proper lumped model). The issue is that the chip sits in an elastomer stocker, meaning that it would only really be possible to perform open and short. So I guess it would make your suggested method impossible.p.s. Im super interested in the math. Do you have any more proof of how you got to line 3?

author: profdc9
author_rank: Frequent Contributor
timestamp: May 11, 2021, 04:59:42 am
content: I can explain the math of how VNA calibration works. I did it for my VNA projecthttp://www.github.com/profdc9/VNAUnder the "doc" directory there is a file called "VNA calibration method 2" you can read. It's brief, but explains the basic two port 6-parameter calibration that allows for a S11/S21 measurement.A one-port measurement is especially easy and involves placing loads with three known impedances at the terminals in the fixture, usually a short, an open, and some resistance of a particular value, often the termination resistance of a transmission line, but it doesn't need to be that. The chicken-and-egg problem is to characterize your loads, which is why often the calibration standards are difficult to make.The data that is measured is two complex-valued quantities, typically the voltage and current V/I at the actual VNA port, or equivalently the forward Vplus and reflected waves Vminus at the port sinceVplus = V - Z0 IVminus = V + Z0 Iwhere Z0 is the port's characteristic impedance, so if you know Vplus/Vminus you know V/I and vice-versa. For using an existing VNA port, Vplus and Vminus is convenient because S11=Vminus / Vplus.The assumption is that the fixture is linear.. Therefore in general we can express the voltage Vembed and current Iembed at the embeded port as a linear function of the Vplus and Vminus voltages at the VNA port:Vembed = A Vplus + B VminusIembed = C Vplus + D VminusIf we divide the first equation by the second equation, we getZembed = (A Vplus + B Vminus) / (C Vplus + B Vminus) = (A + B S11) / (C + D S11)Because A,B,C,D can scale together, we set D=1 to fix a solution:Zembed =(A + B S11) / (C + S11)Now you place three known impedances Zembed at the fixture to be calibrated, and measure the S11 at the port of the VNA. Then you can get simultaneous equations for A, B, C.Once you have A, B, C, you can measure S11 at the VNA port and calculate the impedance of the load at the embedded port.And that is how you deembed one port.Dan

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 12, 2021, 03:09:30 pm
content: Thanks for showing your work. I was more curious about actual hands-on experience on how to calibrate out fixtures.Quote from: profdc9 on May 11, 2021, 04:59:42 amHerein lies the problem. It is impossible to place a known load across the terminals. Only an open or a short. I have resorted to utilizing TDR to estimate the impedance seen by the port. Time-domain methods have assisted me where frequency-domain methods have failed.I would love to try and attempt to use it but... It seems impossible. That is, unless you know of a way of placing a known impedance in an elastomer compression socket...The interesting part of your model is that it is only good at a singular frequency (sure, you could parametrize it across frequency), and it only models the response, not the equivalent lumped model.

author: profdc9
author_rank: Frequent Contributor
timestamp: May 12, 2021, 04:40:19 pm
content: If they are two adjacent balls in a BGA, you might be able to bridge them temporarily with a SMD resistor. Or you could fab a special PCB with pads the same spacing as the BGA and then solder the resistor or load to it temporarily.

author: gf
author_rank: Super Contributor
timestamp: May 14, 2021, 11:42:22 am
content: What is the frequency range of interest, and what is (roughly) the distance on the PCB between RF connector and chip? Just to get a feeling about the magnitudes we are talking about.

author: virtualparticles
author_rank: Regular Contributor
timestamp: May 14, 2021, 01:41:53 pm
content: Quote from: profdc9 on May 11, 2021, 04:59:42 amThis is some really interesting work. In your docs, I'm not really following your methodology but I'll study it more when I get time. SOLT and SOLR calibration methods are well documented where SOLT generally solves for 12 error terms because VNA designers like myself like to have a physical interpretation for the error whereas SOLR just goes after 7 of the 8 error adapter transfer matrix terms which is really all that is needed. For 1 port in one direction, only three terms are needed and those can be equated to three entries in a single error adapter matrix. You don't need all 4 because S parameters are ratio-metric. One can always set one of the terms to "1".Might I ask if you're looking to make a career change?Best,Brian

author: gf
author_rank: Super Contributor
timestamp: May 14, 2021, 02:36:47 pm
content: Quote from: Nitrousoxide on May 12, 2021, 03:09:30 pmWhat about time gating orimpedance peeling?I wonder, though, whether your VNA is fast enough in order to provide the necessary time resulution. Depends of course on the frequency range of interest.

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 14, 2021, 05:11:27 pm
content: Quote from: profdc9 on May 12, 2021, 04:40:19 pmI could do that. I could possibly use a PCB just for calibrating. But I'd like to place the cal pieces in the socket. I will try using a copper square, and a copper serpentine trace (and an open) as my three cal points.Quote from: gf on May 14, 2021, 11:42:22 am0 Hz to 1 GHz (maybe even 2G). Distance, it's multipath, very complex, one trace with multiple branches at differing distances that end in open. Depending on which device is selected, the signal path varies between 20mm to 80mm.Quote from: gf on May 14, 2021, 02:36:47 pmYeah, I'm using TDR to determine the impedances that the system observes. That document is very nice because even though I fundamentally know what TDR is and how it's used/what it can do, I just haven't seen any hands-on examples... (bloody academics, go figure).

author: gf
author_rank: Super Contributor
timestamp: May 14, 2021, 09:17:21 pm
content: Quote from: Nitrousoxide on May 12, 2021, 03:09:30 pmI foundyet another de-embedding methodwhich requires only a single known impedance at the DUT location (which can be short). It makes use of time-gating.

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 15, 2021, 04:15:53 am
content: Quote from: gf on May 14, 2021, 09:17:21 pmI believe this is what R&S does with their "direct compensation" de-embedding setting in their VNA's. You can either perform "auto length" or "auto length and loss" compensation, these both assume that you simply have a TL attached and by using TDR with an open and short load, it figured out the delay and loss.The VNA also has a feature called "Direct Compensation", which I'm fairly certain implements something similar to what you have linked above, which is what I have been utilising this whole time, and seems to be doing the job really well (I'll post some pictures when I get the chance).

author: gf
author_rank: Super Contributor
timestamp: May 16, 2021, 09:59:54 am
content: Quote from: Nitrousoxide on May 15, 2021, 04:15:53 amI do not think so. I downloaded the ZNL handbook and the text readsQuotewhich does not indicate that any time domain processing were involved in "Direct Compensation". Unfortunately they don't specify the underlying maths in detail. My guess were rather some kind of "frequency-dependent transmission line model", but I may be completely wrong.The method in the lastly linked paper obviously relies on your ability to isolate one S11 time-domain impulse response of a reflection originating at the DUT with a time gate, while still ensuring on the other hand that the gated time range does not include parts of the impulse response of any reflexion that originates somewhere in the fixture. Since you mentioned multipath, there might be significant overlap, which could make separation in the time domain difficult or impossible. Depends of course on the topology of your fixture. If you do the TDR, you'll quickly get a feeling whether there are clearly separable pulses, or not. According to the handbook, the ZNL does support time-gating anyway. So if separability in the time domain is granted, you need to setup the time-gate, measure the time-gated S11 with DUT installed, and the time-gated S11 with open/shorted socket (using the same time gate), divide these two S11 readings, and mutiply with 1 or -1 (depending on open/short) to obtain the DUT's S11. As always, the devil can still be in details,

author: rf-messkopf
author_rank: Regular Contributor
timestamp: May 16, 2021, 10:53:05 pm
content: Quote from: gf on May 16, 2021, 09:59:54 amI haven't used that function in a while, but from what I remember the "Direct Compensation" function simply works by measuring S_nn at the calibration plane (i.e., the fixture connector) at each port, with the fixture contacts open or shorted (this can be selected). Assuming reciprocity (i.e., the path from the connector to the fixture contact is the same in both directions), the square root of the measured S_nn describes the influence of one pass trough the path from connector to fixture contact. This quantity can then be applied at each port to correct for phase and loss.This correction is applied at each frequency individually. There is no transmission line model involved, in contrast to Auto Length and Loss.For a single port, Direct Compensation is equivalent to simple trace normalization. I.e., measure S_11^ref at the cal plane with the fixture shorted. Then the corrected measurement, up to an overall phase, is given by S_11^meas/S_11^ref.You can do Auto Length and Loss as well as Direct Compensation with open, short, and both open and short. Due to the fringing capacity of an open a short is probably closer to ideal.

author: Joel_Dunsmore
author_rank: Regular Contributor
timestamp: May 17, 2021, 01:44:33 am
content: This has been done commercially for a few years using Automatic Fixture Removal (AFR for short, paid for app). It does just what you want to do. The fixture can be characterized with just an open, or just a short, or open/short combo; or just a thru. Used all the time by RF chip makers to remove their fixture effects. The basic principle is discussed in chapter 11 of my book (2nd editionwww.tinyurl.com/joelsmicrowavebook). Basically uses some sophisticated time domain gating techniques and little special sauce. But that chapter also details Automatic Port Extension which might do the trick for you. Its a free feature on Keysight VNAs. But the chapter also tells you how to make your own calibration kits and suss out kit coefficients and use them for in-fixture cal.Or, just for fun, I can do can AFR for you; calibrate carefully at the end of a cable using your best SMA cal kit, post an S1P file of your fixture with the port open, and I'll send you back the S2P S-parameter file of the fixture, but the measured open-data needs to go to 20 GHz, 10 MHz steps (2000 points).

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 17, 2021, 10:22:34 am
content: Quote from: gf on May 16, 2021, 09:59:54 amWhoops. I meant to say the "auto length/loss" method. That's what I get for posting while sleep-deprived.I've built a new PCB with a significantly simplified RF path, so no worries there. It's unfortunate indeed that time gating isn't directly supported, the best I could do is emulate the first app note you linked.Quote from: rf-messkopf on May 16, 2021, 10:53:05 pmYep. It completely zeros out the fixture, almost like I'm taking a "delta" measurement. That's basically what I figured I'd do in my original post. Also, what do you mean by "up to an overall phase"?Quote from: Nitrousoxide on May 05, 2021, 09:57:33 am*and also phase(S11_/S_11,ref).So I guess really not so silly after all... I did however make a few modifications to my procedure: Ive machined a copper square to fit in the socket so I can do both open and short.Quote from: Joel_Dunsmore on May 17, 2021, 01:44:33 amR&S ZNL has auto port extension (estimate the phase delay and loss) built-in. It also has the provisions of defining a custom cal kit at no added cost required, something I know that you have to pay for with Keysight VNA's (I know because the mmWave guys next door keep complaining about it).The elastomer socket is incredibly picky with the amount of force applied. If any SMD passives are required then that could potentially cause issues when I torque the socket. That and I don't have the confidence (or the tools) to measure it accurately.Quote from: Joel_Dunsmore on May 17, 2021, 01:44:33 amI can get some data tomorrow. That would be cool to see if you could work your magic.Wow, there are so many ways to tackle this, and as per usual, no single one is "better" than the other... The pains of engineering...EDIT:We also own a small copper mountain VNA, so this may be of help:https://coppermountaintech.com/automatic-fixture-removal-plug-in/

author: gf
author_rank: Super Contributor
timestamp: May 17, 2021, 01:38:06 pm
content: Quote from: Nitrousoxide on May 17, 2021, 10:22:34 amIn the general case, you would need to measure the fixture terminated with three known impedances in order to obtain an unambiguous solution.But if you have some a priori knowlege about the fixture, then this knownledge may help to constrain the set of possible solutions, so that fewer than three measurements may suffice.A simple S11 response normalization resolves the ambiguity by making the a priori assumption that the fixture can be modeled by an equivalent 2-port network whose S11=S22=0. Only if this assumption happens to apply to your fixture, then the result is correct for any DUT connected to the fixture, otherwise it is not.

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 18, 2021, 05:49:11 am
content: Quote from: gf on May 17, 2021, 01:38:06 pmThe assumption is correct. I'm "looking" into the gate of a 45nm (very large) mosfet and observing how the small-signal impedance changes versus bias voltage.Honestly, this may be easier to just perform C-V characterization. It's a shame I don't have a tool that's easily does that (considering we're a microelectroics lab, that seems a bit odd, but hey, price is a thing).

author: coppercone2
author_rank: Super Contributor
timestamp: May 18, 2021, 07:26:35 am
content: my e5100 has a 'thru' calibration option. It also has an option for all 3. They recommend the thru for fast measurements, but the openshortclosed for higher accuracy. I assume they use one of these methods. Anyway, it cuts down on the work alot.The accuracy might be in the manual.

author: Nitrousoxide
author_rank: Regular Contributor
timestamp: May 18, 2021, 09:25:16 am
content: Quote from: coppercone2 on May 18, 2021, 07:26:35 amWouldn't 'thru' calibration in this context be irrelevant, since it's purely a 1 port device?

author: rf-messkopf
author_rank: Regular Contributor
timestamp: May 18, 2021, 03:56:35 pm
content: Quote from: Nitrousoxide on May 17, 2021, 10:22:34 amIf I'm not mistaken, when you do trace normalization with a short i.e., do the \$S_{11}^{\text{meas}}/S_{11}^{\text{ref}}\$, you get an extra phase factor of \$\exp(\mathord{\rm i}\pi)=-1\$. When you do the same with an open, your extra phase factor is just \$\exp(\mathord{-\rm i}0)=+1\$. The "Direct Compensation" function should take care of that automatically. If you use trace math instead, you'll have to compensate for the \$-1\$ manually.Edit: Corrected the math. The statement should be ok now.

author: Joel_Dunsmore
author_rank: Regular Contributor
timestamp: May 18, 2021, 06:58:08 pm
content: Quote from: Nitrousoxide on May 17, 2021, 10:22:34 amYeah, they added it after we did. I like my implementation better, fitting is better I think.Quote from: Nitrousoxide on May 17, 2021, 10:22:34 amAs far as I know, you can create whatever cal kits you want just by creating a new one. There is a paid-for version of a wizard in the PLTS that does quite complicated things, but for normal cal kits I think the free version is available. I just downloaded on my home PC and it seems to not require any license. I got it here:http://na.support.keysight.com/pna/apps/#calkiteditorOf course this makes calkits that are compatible with Keysight VNAs, maybe you have to change the units to Euros or something to run on other products.the same page has a bunch of little helper code.

author: Andrey_irk
author_rank: Regular Contributor
timestamp: September 14, 2021, 01:31:42 am
content: Quote from: Joel_Dunsmore on May 18, 2021, 06:58:08 pmMy employer has a 20GHz E5071C of some later revision. It doesn't have an option (neither does the calkiteditor you mentioned) to create a cal kit with s-parameter characterized standards. As I understand, it means there is no way you can get the maximum accuracy out of the mechanical SOLT cal kits. Annoying.Of course, you can say you get what you pay for, but there are free tools like METAS VNA Tools that allow using your uncorrected VNA data along with measured standards data to do correction on your PC.Also, that E5071C has a deembedding feature, but no way you can rotate the S2P file!Other than that I like Keysight VNAs. The interface is the best in my opinion, the performance is solid. Great stuff.P.S. I'm glad to see you here and thanks for the book you wrote, I love it!