Are my FETs failing from SOA or dv/dt? - Page 1
Forum section: electronics / projects

author: hlab
author_rank: Contributor
timestamp: January 20, 2022, 11:59:39 pm
content: Hello Everyone,I'm new to the forum but not new to EE.About the circuitFirst, a little context. I've designed half bridge for high power brushed DC motors (15V at ~40A). During stall, inrush current can go up into the 150 amp range however. Both fets are extremely low RDSon, ~0.8mohm, and never get warm. I've tested it for several weeks now without issues until yesterday when the low side FET decided to become a 3-way pin short. No biggie, probably just bad soldering I thought. Then I tried again with a completely new driver board, and it failed instantly in the same way, all 3 pins of the low side fet shorted together (high side fet is still fine).Due to several non-ideal design constraints, I had to design this driver in a fairly unconventional way. The motor itself is inaccessible and there is no space for a flyback diode to suppress inductive kickback. Normally this wouldn't be an issue, since the diode in the high side fet should route it back to the motor. However, the return loop through the high side FET has too much impedance to be of any help.How it worksThe way I solved this issue was to soft switch the motor in a controlled way to keep the spike under the VDS limit. As soon as the M2 begins to switch off, the resulting inductive spike travels through the body diode of M1. It then goes through D3 and D2 to try to keep M2 on. In this manner, VDS across M2 is clamped to ~30-35V. It takes ~2uS to fully switch off. I also have an RC snubber circuit across M2 to soak up any high frequency ringing that is present. Yes, I have measured VDS across M2 with my 200MHz scope and it never goes above 36V. I only have cheap probes though, so even if there was a high voltage spike I probably wouldn't see it anyway.Theories of why it's failingI'm a little baffled why it took so long to fail the first time if there's something really wrong with my design. But here's a few guesses as to what could be happening.1. Due to the slow switching, the mosfet die heats up too quickly and destroys the depletion region (probably the most likely imo)2. Brush noise from the motor causes the VDS rating to be exceeded and fet is destroyed by avalanche current3. Large dv/dt is causing VGS to be exceeded (I think this is less likely due to RC snubber present)4. Other high voltage transients are exceeding the maximum VGS rating (20V)Any ideas for troubleshooting or things I may have missed?

author: hlab
author_rank: Contributor
timestamp: January 21, 2022, 01:14:43 am
content: Upon further inspection, it seems that 2uS switching time is well within the datasheet SOA.Also, In LTSpice the slope of the inductive spike is less than 0.2V/ns, which should be ok right?

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: January 21, 2022, 02:01:33 am
content: As a first step I would capture some gate & drain waveforms for both MOSFETs and share them on here

author: hlab
author_rank: Contributor
timestamp: January 21, 2022, 03:43:40 am
content: Well it seems that my previous scope readings were incorrect. I swapped out both fets rated for 60V, and now I'm getting 100V spikes on the drain. Is there any reason the zener diode wouldn't be clamping the spikes as intended?Attached screenshot is VDS x10 during turnoff.

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: January 21, 2022, 04:25:18 am
content: Quote from: hlab on January 21, 2022, 03:43:40 amShow us where your zener is placed

author: hlab
author_rank: Contributor
timestamp: January 21, 2022, 04:51:23 am
content: Quote from: ANTALIFE on January 21, 2022, 04:25:18 amEverything is laid out fairly compactly, so parasitic inductances shouldn't have too much of an effect.

author: hlab
author_rank: Contributor
timestamp: January 21, 2022, 05:30:01 am
content: Apparently there are fets with built in clamping zeners similar to my design.https://www.diodes.com/design/support/technical-articles/self-protecting-mosfets-deliver-improved-reliability-in-the-harsh-environment-of-automotive-applications/Is it possible that the body diode of M1 is too slow to allow the transient through?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 21, 2022, 05:36:42 am
content: Back side all GND plane..? Or inner layers?With plane, that's still a good 8nH or so in the switching loop, and 150A is a lot of current to switch. Depending on where mutual inductances are, some of that inductance may help to slow turn-off, but it's not clear how much if any is common to the gate traces. If we take 1us as a ballpark turnoff figure, then V = L dI/dt = (8nH) (150A) / (1us) = 1.2V.But this assumes 8nH is the total switching loop; is there no bypass cap onboard? Just the RC snubber? (And, how was that snubber dimensioned? -- 22R is orders of magnitude higher than what the peak load current would suggest.) In that case, the 100s of nH to the supply is relevant, and the peak voltage can be many times higher. Which seems to be confirmed by the measurement?The zeners should still be doing some work, true, but it's not obvious whether they'll do it well enough (quick response with respect to their trace lengths, at whatever peak current must be driven into the gate driver). They could also cause parasitic oscillation, which could develop enough transient voltage yet at frequencies where you can't measure it (10s, 100s MHz?).(100s MHz is a stretch, as even the best power Si MOSFETs have very little power output remaining up there. That is, even when set up as the perfect oscillator at say 300MHz, they only develop some 10s of V, a fraction of the say 600V rating of a MOSFET used in an offline SMPS. The amount should be proportionally smaller for a low voltage part. I use a high voltage example, as that's what I've measured; I'm not sure I've seen a low voltage part oscillate, offhand s-- which isn't to say they can't, I just haven't had the particular circumstances before.)Tim

author: hlab
author_rank: Contributor
timestamp: January 21, 2022, 06:51:43 am
content: Quote from: T3sl4co1l on January 21, 2022, 05:36:42 amPower components are all routed on single layer. Driver circuitry has a dedicated ground plane, all connected at a single point.QuoteNope, physical size limitations unfortunately. Driver circuitry is decoupled well and regulated though.QuoteI'll be honest, this combination of R and C was chosen since it had the best damping effect in spice. During PWM simulations it seemed to help.QuoteI upped the gate resistors to 100ohm which seemed reduce the spikes a little, but not by much. Peak current measured through zener is around 40mA, so I don't see this as a problem anymore. Fortunately I'm not seeing any oscillations <100MHz with my zener clamp, so parasitic inductances should be low enough.Since I don't trust my scope probes that much, I peppered my spice schematic with ludicrous amounts of inductance, but spikes still seem to be less than 35V.

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: January 23, 2022, 10:24:17 pm
content: Bit of a silly request. I am having trouble following the LTspice schematic, could you share the actual schematic you used for the PCB?

author: hlab
author_rank: Contributor
timestamp: January 24, 2022, 12:11:06 am
content: Sure, here's the relevant portion of the schematic. SW goes to the negative motor terminal, the positive motor terminal is connected to BAT+. HS and LS go to the gate driver chip (I'm using DGD05473). U5 is just for current sensing.

author: ANTALIFE
author_rank: Frequent Contributor
timestamp: January 24, 2022, 01:43:44 am
content: Quote from: hlab on January 24, 2022, 12:11:06 amAlright now I am getting a better understandingTo rule out Vds & Vgs breakdown I would try putting a Zener across Vgs & Vds for both MOSFETS. If that helps then you can start removing them one by one to figure out where the inductive spike is coming from

author: jmelson
author_rank: Super Contributor
timestamp: January 24, 2022, 04:30:34 pm
content: I make a PWM servo drive with a pair of half bridge switches. In the early days, I had failures. I eventually found the issue with the help of a digital scope.When the half-bridge was sourcing current to the motor, and then turned off, it left current flowing out into the motor's inductance. During the off-time, that current would cause the common node between the high- and low-side transistors to go negative. To my amazement, this node could go to -6 V or more for up to several microseconds before the body diode in the low-side transistor would start to turn on. This caused destructive failure of the gate driver chip. The cure was to put an ultra fast diode across D-S of the low-side FET. Problem solved.Jon

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 24, 2022, 04:43:50 pm
content: Crazy; I've always measured body diode forward recovery to be negligible!Tim

author: jmelson
author_rank: Super Contributor
timestamp: January 25, 2022, 12:11:12 am
content: Quote from: T3sl4co1l on January 24, 2022, 04:43:50 pmWell, I may have had some really crappy FETs. They were International Rectifier brand, I think IRFB31N20D. I had a 47 uH inductor on each output lead, and current limit was set to 20 A. Now, one could argue about scope probe effects, etc. but I really did measure these massive reverse voltages on the low-side transistor. The IR2113 gate driver was speced to handle up to -5V on the common node (source of high-side transistor) and the bootstrap diodes were helping valiantly to keep the node from diving bleow zero. But, when the node went more negative than about -6.5 V the IR2113 would fail catastrophically.I now use the slower IRFB260N transistor, but also have an ES3D diode to prevent negative voltage at that node.Jon

author: T3sl4co1l
author_rank: Super Contributor
timestamp: January 25, 2022, 06:40:12 am
content: Weird, they even specify it ("negligible"), among a few other things I don't think I've seen before (spot tests of Coss). There could still be something you missed, but, it just comes down to layout and it sounds like quite a lot of stray inductance would be required to do the same thing, even if they layout wasn't great (and I assume you know about good layout). And probe errors would tend to be in your favor (i.e. looks worse than it actually is).It seems some bootstrap drivers have taken the lesson nonetheless, and are available with transient ratings to -Vbs (i.e., forward-bias of the HV pulse coupling transistors' body, from VSS to bootstrap VDD), or sometimes even more (I forget if I saw one with as much as -100V, for just some fraction of a µs).Tim

author: hlab
author_rank: Contributor
timestamp: January 26, 2022, 12:29:06 am
content: Well I think I may have figured out my issue. The dead time of the half bridge driver is less than 100ns, which means both fets are conducting for several microseconds. Looking at the scope now, the peak voltage stays under 36V consistently, so it appears my voltage clamping mechanism works after all@jmelson - I'm also seeing fairly large negative swings around -6V or so, but I haven't fried a driver chip yet. I made a new PCB rev that adds a TVS diode in parallel with the lower fet, so hopefully it gets rid of that issue.

author: jmelson
author_rank: Super Contributor
timestamp: January 26, 2022, 02:40:23 am
content: Quote from: hlab on January 26, 2022, 12:29:06 amOK, I have RC-diode networks to control dead time on the inputs to the gate drivers on my brush amps, and use clocked logic on the brushless ones. So, I have tuned the deadtime for the transistor-gate driver combinations to avoid this.QuoteWell, some gate drivers are sensitive to negative excursions on the high side source terminal, and some are better protected. I use dual drivers with one low- and one high-side driver in one package.Jon