Feedback loop gain simulation problem in LTspice - Page 1
Forum section: electronics / projects

author: ZeTeX
author_rank: Frequent Contributor
timestamp: September 19, 2016, 02:32:02 pm
content: Hey,I've got the following circuit in LTspice:I'm trying to find the phase margin at 0db but I cant, I guess I'm doing something wrong:There is no 0db and it seems weird, what am I doing wrong?Thanks.

author: rstofer
author_rank: Super Contributor
timestamp: September 19, 2016, 02:53:31 pm
content: I don't understand Q1 collector connected to ground.

author: ZeTeX
author_rank: Frequent Contributor
timestamp: September 19, 2016, 03:14:58 pm
content: Quote from: rstofer on September 19, 2016, 02:53:31 pmWell they did say in LTspice tutorial to ground the input source, and even if I don't ground it -nothing really changes.

author: Cerebus
author_rank: Super Contributor
timestamp: September 19, 2016, 04:13:35 pm
content: Quote from: ZeTeX on September 19, 2016, 03:14:58 pmWhy not show us the whole schematic, configured as it's intended to work without any modifications made for measurement, and we'll take it from there. Then things might get a bit clearer.

author: ZeTeX
author_rank: Frequent Contributor
timestamp: September 19, 2016, 04:26:48 pm
content: Quote from: Cerebus on September 19, 2016, 04:13:35 pmThat's the whole schematic:As for now this is just an constant voltage regulator, that I need to get stable using the proper way and not try and error.

author: StillTrying
author_rank: Super Contributor
timestamp: September 19, 2016, 04:37:16 pm
content: If you connect VCC, bias V5 to 3V, and set its AC=1.You get this.

author: ZeTeX
author_rank: Frequent Contributor
timestamp: September 19, 2016, 04:48:55 pm
content: Quote from: StillTrying on September 19, 2016, 04:37:16 pmWait, don't you have to divide V(fb)/V(inm) and not look at the the op amp output directly?

author: StillTrying
author_rank: Super Contributor
timestamp: September 19, 2016, 04:58:39 pm
content: I think setting AC=1 makes V(inm) = 1 for the freq plot.

author: JS
author_rank: Frequent Contributor
timestamp: September 19, 2016, 06:19:03 pm
content: You still need to add some load resistance in parallel with C1, won't work properly without some, no regulator does, and the ones who does, it's because they have it built in.JS

author: Cerebus
author_rank: Super Contributor
timestamp: September 19, 2016, 07:59:18 pm
content: Quote from: ZeTeX on September 19, 2016, 04:26:48 pmI had my suspicions about the voltage regulator. Fire up LTSPice, open help, go to FAQ and the sub-heading "How to get a Bode plot from an SMPS", and follow the directions there. This is Middlebrook's method for finding the loop gain (note: not closed loop, not open loop, but loop gain) by signal injection. This is exactly what you want and need. Insert the voltage source described in that note between the Darlington's emitter and the junction of C2 and your op amp inverting input and set V5 to a constant voltage, say 10V. So the Darlington emitter will be labelled 'A' and the junction of C2 and the op amp inverting input labelled 'B' - this will make sense once you've read the help topic.P.S. The cat is helping me type this, so apologies for any remaining typos.Editted to add: By the way, a 1 ohm resistor in series with your 1uF output cap will make this much easier to tame. You won't need it in real life as long as your output cap has some ESR but the ideal cap in the simulation can really ruin your day.