ADS1298 Layout on 2 Layer PCB  - Page 1
Forum section: electronics / general

author: Saqlain
author_rank: Newbie
timestamp: July 08, 2018, 11:02:26 am
content: Hello!I have been playing around with the Texas Instruments ADS1298 Eval Kit. Now i have decided to make my own breakout board for the 24bit biopotential measurement beast. so the ADC requires three supplies i.e 3.3V, 2.5V, -2.5V. I understand a 4 Layer PCB is the right way to go for this project but i am constrained for now to the 2 Layer Board! Which means theres going to be a lot of noise problems in the board. I have followed the rule of thumb - Dedicated entire bottom layer for Unbroken Ground Plane. Also i have the power planes and the -2.5V plane on top layer!I have the layout ready but do not have the AD PDN Analysier to help me with this! Hence i would want your valuable feed back and suggestions on the current layout and or any corrections! i am attaching schematics and board images below. Cheers!!!

author: Gibson486
author_rank: Frequent Contributor
timestamp: July 17, 2018, 01:00:51 pm
content: I could not read your schematic that well (too fuzzy), but if you signals are differential AND from the same source, lots of problems become easier to solve. The main thing is to make sure that whatever is getting the same reference has a clean path to to whatever else is referencing it.For example, for a trace...This is bad...whatever relies on signal reference 1.......some via to the reference that will inject current.......whatever relies on signal reference 1You want to make sure that A) it is the shortest path possible and B) you are not sharing that reference between the two points (ie, there should be a direct connection between the two without anything disturbing it).edit...just saw your ground plane pic...that suits your needs. The only other thing you can do is a strategic cut in the gnd plane, but I think you should be fine as doing a wrong cut will do more harm.BTW...I only spent 5 minutes looking at it, but nice job. I would have just told them to screw if they said I had to make that as a 2 layer board. I think you may pull it off.

author: T3sl4co1l
author_rank: Super Contributor
timestamp: July 17, 2018, 01:40:23 pm
content: Thanks for taking the time to present clear and thorough screenshots of your project!Just one thing: please do not use multiple net names for a given connection: 3.3V and DVDD. Check the compile messages for warnings and errors. Not only is it confusing to the reader, it's confusing to the compiler as well: connectivity may end up wrong!I don't get a sense for how strict the supply bypassing is. It doesn't look like there are enough power pins to require that many capacitors. It looks that it has a digital interface side, an analog reference side, and both should be reasonably quiet; you can add source termination resistors to the logic output pins, both for signal quality and to reduce peak power requirements. Have you checked how much power consumption, and transient load, this chip uses? Have you checked the PSRR, or supply tolerance, or such?Also the sample rate is very low, and being a S-D type, high frequency interference is integrated away. This should be the case for internal as well as external noise sources. I suppose there could be charge injection, synchronous with internal clocks, that feeds back into the measurement after going through supply or ground pins, somehow. But it seems unlikely that they wouldn't have already accounted for that. You can't do much better than putting a cap at each power pin, and tying all the grounds to a ground plane. And that's more or less what you've got, and what the dev kit has, and what their test fixture would have.Regarding noise, mind that the charge pump will be very noisy. You might want to put a CLC filter on both sides of that (use a ferrite bead for the L, I suppose).Speaking of ferrite beads, they should be okay. The load only looks to be a few mA, which should be within the linear range even of 0603 size ferrite beads. Something in the 330 to 2k Ω range would be fine. Otherwise, a proper inductor, 0.47 to 2.2uH say, will do just as well.Any time you have inductors between capacitors, you have the potential for resonance. To address this, find the resonant impedance: Z = sqrt(L/C). L is the inductance, and C is the total capacitance around the L (for a CLC network, that implies taking the value of both C's in series; but if one C is very much larger, because of bulk capacitance elsewhere, the total is basically just the one side, no worry). Figure a ferrite bead is around 2uH (actual value varies with rating and frequency, so we should use a worst-case scenario). If you've got five 0.1's after it, that's Z = sqrt(2 / 0.5) = 2 ohms.We need the capacitor ESR >= resonant impedance, to get a damped network. We don't want an impedance peak at the resonant frequency -- that allows modest variations in supply current to generate relatively high ripple voltages. For example, a logic output pin delivering 10mA, on and off, at just the right frequency, will develop about V = I*R = (10mA)*(2Ω) = 20mV ripple, but that's at a Q of 1 (critically damped). If the Q is higher, the ripple is higher, too.Normally, 0.1uF ceramics have around 50mΩ ESR, which is very much less than 2Ω, so we'd expect a Q as high as 40. Real inductors won't be that good at this frequency (and ferrite beads even worse), but we might still expect a Q of 2-6, say.To reduce Q, simply put a big, lossy capacitor in parallel with the others. "Big" means >2.5 times the total bypass value (so, a few uF is fine here), and lossy means ESR equal to resonant impedance. Ideal is a tantalum capacitor with these ratings (tantalum capacitors are sold by capacitance AND ESR -- don't just throw one in without checking, they come in all values!), or a large ceramic capacitor with a resistor in series (those 10 and 22uF caps you have in there, will have an ESR around 10mΩ, so you need to connect a resistor in series to get it up to the required value). Less ideal is an electrolytic capacitor: their ESR is typically too high in these values, and isn't very stable over temperature and aging. That said, you can also afford to use a "too large" electrolytic, like 47uF, which will be maybe 0.5Ω ESR typical, which works out, because it's so much larger than the bypasses that, even if the inductor value is very different, and even if its ESR varies wildly, it still does its job. That's a good example of an effective worst-case design approach!Tim

author: Saqlain
author_rank: Newbie
timestamp: July 18, 2018, 08:41:56 am
content: Thank you so much for taking your time to go through @Gibson486 !! Appreciated!!

author: Saqlain
author_rank: Newbie
timestamp: July 18, 2018, 08:43:34 am
content: Thank you for your in depth Dampning explaination @T3sl4co1l !! Really helped a lot!