Forcing usage of clock enable in MAX7000 CPLDs - Page 1
Forum section: electronics / general

author: GTT95
author_rank: Contributor
timestamp: July 09, 2022, 11:40:10 pm
content: Hello,After synthesizing a VHDL design featuring a register which keeps its value while a signal is low and gets update while the signal is high and a CLK rising edge occurs, I can see in RTL viewer there is a multiplexer which selects the entry to the register instead of using the CLK enable feature.How to force usage of the clock enable input? Is there any directive to consider for signal declaration?Thanks a lot for your help.

author: rstofer
author_rank: Super Contributor
timestamp: July 10, 2022, 02:14:29 am
content: Show your code, part of your description seems like it would infer latches. This would be unwise...Perhaps a complete description of the intent of the circuit.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 10, 2022, 02:29:38 am
content: We need to see the code indeed just to make sure.That said, the fact clock enables would not get used is a very common "issue" with FPGAs. Tools often decide for a number of reasons that the clock enables of registers would not be the most efficient way of implementing your code. There are more or less ways of forcing that, depending on the tools you use. But don't necessarily assume that what the tool did here is suboptimal: it may very well not be.(Clock enables will yield lower power consumption, but not necessarily higher Fmax. The tools may also choose not to use them to save resources.)You can have a look in the Quartus documentation. Example:https://www.intel.com/content/www/us/en/programmable/quartushelp/22.1/index.htm#mapIdTopics/nnn1564674650896.htm

author: ZaneKaminski
author_rank: Contributor
timestamp: July 10, 2022, 06:08:38 am
content: Altera MAX 7000 is macrocell-based, so it's kind of likely not to matter. The architecture is very coarse and a lot of logic comes with each register behind its D input. See the attached picture.Now I won't say that there's no benefit to forcing the use of clock enable but as you can see, the combinational logic behind the register is quite large. Have you studied Karnaugh maps? If so it makes the description of the macrocell "gate" easier. It's a 36-input "gate" where you can "circle" at least four terms in the Karnaugh map. And if you are doing a synchronous design all clocked from the same clock, the clock enable will have the same delay as the data coming back from the register. So unless your logic function becomes too large to fit in that one macrocell, muxing vs. clock enable doesn't make any difference. Power consumption is also largely irrelevant since the MAX 7000 is sense amplifier based and burns a ton of power standing still.Is your design failing to meet timing or not fitting in the device?

author: GTT95
author_rank: Contributor
timestamp: July 10, 2022, 08:29:03 am
content: Here is the codeCode:signal DataNext:std_logic_vector(7 downto 0);signal Data:std_logic_vector(7 downto 0);signal UpdateData:std_logic;begincombi:process(Data,DataIn,UpdateData)beginDataNext<=Data;if(UpdateData='1') thenDataNext<=DataIn;end if;end process;synch:process(CLK,DataNext)beginif(CLK'event and CLK='1') thenData<=DataNext;end if;end process;end RTL;In RTL viewer I get the result with the multiplexer feeding the D input. I would like the circuit to be synthesized as shown on the picture using the CLK enable input.I have no concern about timings but about logic usage, as in my opinion a 16=>8 mux takes more space than using the enable input.The design software is quartus II 9.0

author: tom66
author_rank: Super Contributor
timestamp: July 10, 2022, 10:22:55 am
content: It looks like CLK_ENA has no inverter option. So the pin can only accept active high logic unless the inverter is pushed downstream.Whereas the 'SEL' mux has added an implied inverter.Perhaps the CPLD planner has effectively configured UpdateData as an inverted signal and while this is trivial to solve for a mux (swap inputs or add inverter onto mux select) it is not trivial for clock enable (would need to pass through a LUT or need fabric to change elsewhere.) And therefore this option has a higher penalty and is rejected.Does the UpdateData signal get used anywhere else?

author: ZaneKaminski
author_rank: Contributor
timestamp: July 10, 2022, 10:29:14 am
content: I do think it would be better to resolve this problem in the context of a “real” design rather than just a test fixture like you have. But anyway the RTL viewer is a human-readable representation of the mapping onto the device resources. You should look at the technology map. That will show the actual resource utilization.

author: ZaneKaminski
author_rank: Contributor
timestamp: July 10, 2022, 11:21:45 am
content: Re: “CLK_ENA has no inverter,” I think I have to reiterate my point about the MAX 7000’s macrocell. It’s huge! You necessarily allocate the macrocell all at once when you utilize the register. The macrocell has the capability not only to invert the clock enable but to decode it as a wide and function of up to 36 true/complement inputs. Lots going on in there compared to an typical LUT-based logic element.

author: nctnico
author_rank: Super Contributor
timestamp: July 10, 2022, 04:15:56 pm
content: Maybe it helps to make the clock edge usage conditionalif update thenif rising_edge thendo_something_hereend ifend ifWhat does the synthesis manual say about using clock enables?

author: BrianHG
author_rank: Super Contributor
timestamp: July 10, 2022, 07:41:26 pm
content: Verilog version:Code:module top (d, clock, ce0, ce1, q);input [31:0] d;input clock;input ce0;(* direct_enable = 1 *) input ce1;output reg [31:0] q;always @ (posedge clock) beginif (ce1)beginif (ce0)beginq <= d;endendendendmoduleIn this example, the second clock enable input 'ce1' is forced onto the macrocell flipflop's clock enable circuitry instead of it being incorporated as part of the LUT logic like the first clock enable input 'ce0'. Remove the feature attribute ' (* direct_enable = 1 *) ' and both clock enables will be integrated as part of the LUT logic as usual.Read here:https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_direct_enable.htm

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 10, 2022, 07:50:11 pm
content: Quote from: GTT95 on July 10, 2022, 08:29:03 amI don't see anything in the code above that would be easily translated to a clock enable (unless you think synthesis tools are particularly clever), as the "enable" signal is not used in a clocked process.With that said, even when you explicitely test an "enable" signal in a clocked process, as I said earlier, the tool may still decide not to use the clock enable of the register for various reasons.But I would change the above code to something more explicit first and see how that goes.

author: GTT95
author_rank: Contributor
timestamp: July 11, 2022, 02:36:31 pm
content: QuoteDo you mean the RTL view may in some way not be representative of what will actually be synthesized?I tried rewrite the code in several ways like:Code:signal Data:std_logic_vector(7 downto 0);signal UpdateData:std_logic;beginsynch:process(CLK,DataIn,UpdateData)beginif((CLK'event and CLK='1') and (UpdateData='1')) thenData<=DataIn;end if;end process;end RTL;However, it always leads to the same output, with the multiplexer rather than usage of the CLK enable input.I am still wondering if it is dependant on the way the VHDL code is written or an option in the synthesize settings...

author: ZaneKaminski
author_rank: Contributor
timestamp: July 11, 2022, 03:54:10 pm
content: Quote from: GTT95 on July 11, 2022, 02:36:31 pmYes, the RTL view is not representative of what is actually synthesized. For that you must look at the technology mapping view. But that's not what I meant here by "resolve this problem in the context of a real design." What I meant there is that you should write your whole RTL for the CPLD in your project and then only worry about this stuff if your design is failing to fit or meet timing.So anyway, the RTL viewer is sort of an idealized logical schematic that represents the functional intent of your design. The presence or absence of the mux in the RTL viewer is unrelated to what was actually synthesized. Quartus displays the mux there because it's supposedly a good representation of your design intent. The RTL viewer shows objects like gates, multiplexers, multi-bit adders and comparators, gates, etc. This is to aid human understanding of the design. It is not reflective of how the logic is actually implemented on the device. The basic elements of CPLDs are macrocells and the basic elements of FPGAs are LUT logic elements. So there are no individually allocatable elements like NAND, MUX, etc. on the chip. There are LUTs or macrocells. To see how the LUTs/macrocells were actually configured to implement the function you described in your VHDL (and also depicted in the RTL view), you use the technology mapping view. If you are concerned with the final usage of the device, check the post-fit technology map viewer. This will show you exactly how many device resources are used and how they are connected.

author: Beta_vulgaris
author_rank: Regular Contributor
timestamp: July 11, 2022, 04:42:49 pm
content: Just use the Altera-specific primitive, DFFE.

author: BrianHG
author_rank: Super Contributor
timestamp: July 11, 2022, 05:48:44 pm
content: Quote from: Beta_vulgaris on July 11, 2022, 04:42:49 pm(No offense Beta, what you write is also true...)You have got to be kidding me, I posted above to use the ' direct_enable ' attribute for Verilog, and no one decided to say to use the same attribute for VHDL, or even google the term:" quartus vhdl direct_enable attribute "And what was the first result returned:https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_direct_enable.htmNo one pointed out all you had to do was add this 1 middle line of code from the example in the above link:QuoteI'm loosing faith here...

author: Someone
author_rank: Super Contributor
timestamp: July 11, 2022, 11:49:02 pm
content: Quote from: BrianHG on July 11, 2022, 05:48:44 pmsudo make me a sandwich

author: GTT95
author_rank: Contributor
timestamp: July 12, 2022, 02:11:34 pm
content: QuoteAs per my understanding, RTL is closer to physical implementation than a pure functionnal view as it shows separation between combinational and sequential logic. However, it can differ from what will be synthesized and thus programmed to the real chip.OK, I will not worry about how it translates until I go into timings and/or size issues.I will try to use the direct_enable_attribute.Anyway, many thanks for the provided help.

author: Bassman59
author_rank: Super Contributor
timestamp: July 12, 2022, 04:37:58 pm
content: Quote from: Someone on July 11, 2022, 11:49:02 pmZap! You're a sandwich.

author: ZaneKaminski
author_rank: Contributor
timestamp: July 12, 2022, 04:52:22 pm
content: Quote from: BrianHG on July 11, 2022, 05:48:44 pmHmm okay yeah maybe we could have all been more direct about the relevant synthesis attributes. But I still think the most important lesson here is that the technology map and RTL views are not the same thing. In GTT95’s design the clock enable could actually be used and we don’t even know because we are not looking at the right thing.

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 12, 2022, 06:07:55 pm
content: Quote from: GTT95 on July 12, 2022, 02:11:34 pmNo, it's not. It's all digested by synthesis and translated to anything functionally implementing the RTL in any way it sees fit according to many options/optimizations/available resources/and so on.