Am I doing it right? :) - Page 1
Forum section: electronics / projects

author: kvresto
author_rank: Regular Contributor
timestamp: February 24, 2013, 01:11:03 am
content: I have since discovered the limitations of trying to send a 20Mhz clock signal to a system across IDC headers and the associated cabling that it entails. The system consists of an ADC, FIFO, CPLD, and a CPU.As I think I have learned, I have now combined all these on a single PCB (sort of) and I want to find out from those that know about this type of design, am I doing it right?After having read the majority of the book Signal Integrity – Simplified by Eric Bogatin, and I’ve been banging my head against Altiums, signal integrity tool with very confusing results. Obtaining the real tools is just way out there in the sense of availability, not to mention I probably couldn’t use them anyway.So I have included a small piece of the artwork in the attached pdf showing the components used, and also shows the clock line is highlighted so you can see how it routs on both sides of the pcb.I Hope that someone can shed some light in what I might expect from my own design.Looking forward to some help, and thanks in advance.kvresto.

author: gnif
author_rank: Unknown
timestamp: February 24, 2013, 01:45:20 am
content: Don't quote me on this as I am yet to play with doing the same stuff myself, but I have seen other circuits that when driving multiple chips with the same clock they usually either have a PLL that outputs two isolated clock signals, or they use a buffer so each chip is somewhat isolated from the other. Is one chip expecting a crystal input and the other something else? There may be some kind of impedance mismatch perhaps? Are all the chips using a rising edge or falling edge clock?I would try to wire up a 74 series buffer free air style (the clock is slow enough), tie three of it's inputs together and feed them with the clock, then feed each chip with each output respectively.

author: kvresto
author_rank: Regular Contributor
timestamp: February 24, 2013, 06:05:43 am
content: Hi gnif, thanks for your input.Both ic's expect a square wave input, and the max clk frequency in this application is 20Mhz. I thought about using two CPLD pins clocked together to generate separate clk signals, and all the ics are using the falling edge to do stuff on. I like your suggestion too, is this a better option?Cheers

author: gnif
author_rank: Unknown
timestamp: February 24, 2013, 06:27:34 am
content: I am sorry but I can not comment on which solution would be better as I do not have much experience with this kind of thing (yet). A simple test would be to free air wire the buffer, lift the pins on the chips and wire to them using something like wire-wrap, this is the first thing I would try myself.

author: SeanB
author_rank: Super Contributor
timestamp: February 24, 2013, 06:33:34 am
content: Normally you would use a separate buffer for each clock line, and a series 47R resistor directly on the output of the buffer, along with a pull up resistor at the clock input. When running the clock over a ribbon cable ground the wires on each side of the clock pin to provide a controlled impedance to reduce noise on the clock. Use a bus buffer to drive the clocks, and use a local decoupling capacitor and a bulk decoupling capacitor right next to the buffer, clocks are high current users. This will do a lot to keeping the clocks jitter free, and if possible arrange all the wiring to be the same length if you are going to have a problem with clock skew in sending data synchronously between devices.

author: kvresto
author_rank: Regular Contributor
timestamp: February 24, 2013, 06:57:10 am
content: Thanks gnif much appreciated.Hi SeanB.Can you explain the use of a pull up resister next to the clock input, and what value? What bus buffer would you recommend?Also how would you rate the current design,…poor?... or ? Would you expect it to work?cheers

author: JuKu
author_rank: Frequent Contributor
timestamp: February 24, 2013, 10:00:26 am
content: The current design looks fine, and I'd expect it to work. If you have free pins on the PLD, you could perhaps drive both chips with separate pins to make an alreadygood design even better.