Bare die extraction - Page 1
Forum section: electronics / general

author: Ammar
author_rank: Regular Contributor
timestamp: May 17, 2016, 11:26:05 pm
content: Hi EEVblog,I am working on a project where I am attempting to miniaturise electronics for biomedical applications for part of my PhD. I have extracted bare die from several packages using Nitric acid (we have a clean room with all the appropriate equipment to handle bare die as well as a fume hood and the necessary equipment to handle Nitric acid. Please, do not try it without the appropriate safety equipment).Microchip have been super helpful in providing data sheets with pad layouts and die dimensions for several microcontrollers (PIC10F series for anyone interested). Which have working in bare die formHowever, I got this response from Analog devices when I asked about one of their instrumentation amplifiers, the AD8293:"Sorry, but we are unable to support your request. We support our products in the form factors in which they are sold. We cannot condone or support the extraction of the die because it affects reliability and performance and it is outside the design intent of the product. Thank you for your understanding."Would an instrumentation amplifier behave any differently if I worked with the bare die? I know the internal resistors are matched to something like a few ppm. Although there is usually a micron thin layer of glass on the top. Maybe the acid would influence that? I thought bare die improved reliability in terms of operating temperature range though. Is it really a big ask to request the size of the die and pad layout? Are they just being crap or is there something to what this person is saying?Excuse thethought this would be the best place to ask.

author: rfeecs
author_rank: Frequent Contributor
timestamp: May 18, 2016, 12:05:09 am
content: Why do you not just buy the devices in bare die form?There are distributors that sell bare die, for example:http://www.micross.com/silicon-ics-ad.aspx

author: Ammar
author_rank: Regular Contributor
timestamp: May 18, 2016, 12:09:03 am
content: I got in touch with micross. They have lists of die they support and are willing to provide. The AD8293 is not one of them. Also, you tend to have to buy commercial quantities (in the order of 1000s) for them to bother. What I really want to know is if having the bare die for an instrumentation amplifier will reduce its performance some how.Thanks for the suggestion.

author: uncle_bob
author_rank: Unknown
timestamp: May 18, 2016, 01:11:52 am
content: Quote from: Ammar on May 18, 2016, 12:09:03 amHiAs long as you understand the specific physics of mounting that particular die *and* pull it out of it's current package without damage *and* un bond it without damage *and* re mount it properly *and* re bond it properly *and* package it cleanly ... It will work fine.Precision IC's often have "secret sauce" in one or the other aspect of their packaging. I've run into that multiple times.Bob

author: Ammar
author_rank: Regular Contributor
timestamp: May 18, 2016, 01:17:38 am
content: Hi Bob,It took a few goes and some failed attempts, but I eventually got there with the process. We are lucky to have a giant fancy wire bonder and micro placing machine thing. Thank you for the response.I am intrigued. Can you tell me more about this "secret sauce" in the packaging. This particular device has impressive specs. 140db CMRR and 0.7uVpp noise. Besides having laser trimmed resistors and well matched transconductance between transistors, what else could they be doing to achieve 140db of CMRR? Could it possibly involve the packaging?Thanks

author: coppice
author_rank: Super Contributor
timestamp: May 18, 2016, 01:18:20 am
content: For many parts, and especially RF ones, the package is not just a box to put the chip in. Its an integral part of the behaviour of the design. On the other hand, most pure digital stuff its really easy to change packages, and you are frequently offered the same part in numerous package options.Do your parts still behave somewhere near spec after etching them out of their package? The die isn't totally unaffected by the chemicals you use to remove the package.

author: uncle_bob
author_rank: Unknown
timestamp: May 18, 2016, 01:21:06 am
content: HiAll packaging involves interaction between the silicon wafer and the substrate. It also involves the die attach material. Silicon die are sensitive to things like strain. If you have a tight enough spec on the chip, that strain is part of the design ....That's only one of many odd interactions.Bob

author: Ammar
author_rank: Regular Contributor
timestamp: May 18, 2016, 01:30:43 am
content: I extracted a PIC10F222 microcontroller, wire bonded to a breakout board and it works fine. No surprises. Like you said, this is largely digital though. The AD8293 has a GBW of 80kHz so it certainly is not anywhere near RF. Although I can see how a package would be an essential design consideration in RF applications, given the increased dielectric constant of the packaging, not to mention shielding.Okay, strain makes sense. Looks like there are a lot of traps to look out for. Thanks!

author: edavid
author_rank: Super Contributor
timestamp: May 18, 2016, 04:47:50 am
content: Quote from: Ammar on May 17, 2016, 11:26:05 pmNot unless you messed it up during the decap operation.QuoteIf you etched any metal film resistors, that would obviously be bad.QuoteThey are being crap, but maybe you just didn't find the right person to ask. Did you try going through their university program office?P.S. Never heard of package strain being intentionally used to modify IC performance. I find it very hard to believe.

author: coppice
author_rank: Super Contributor
timestamp: May 18, 2016, 05:03:48 am
content: Quote from: edavid on May 18, 2016, 04:47:50 amIs that based on extensive experience with instrumentation amps?

author: Richard Crowley
author_rank: Super Contributor
timestamp: May 18, 2016, 05:51:51 am
content: If the resistors on the die are laser-trimmed after the passivation layer, then they are quite vulnerable to over-etching by your acid de-potting procedure.You have rather specified yourself into a corner. Are there not similar chips you could use that ARE available in dice form? Analog Device lists dozens of parts available as dice:http://www.analog.com/media/en/news-marketing-collateral/product-selection-guide/Space_Products_Selection_Guide.pdf

author: Ammar
author_rank: Regular Contributor
timestamp: May 18, 2016, 06:33:58 am
content: I am aiming to find die that are less than 1mm wide. Unfortunately, the die they provide do not meet this spec (I believe).

author: l0wside
author_rank: Regular Contributor
timestamp: May 18, 2016, 08:24:00 am
content: Re strain: I do not believe that strain is deliberately applied to tune parameters (although it would be a cool idea). But piezoelectric effects have happened in the past, so I suppose they either specify (internally) some maximum bending to stay within spec or include the piezo effects in the spec values.Have you considered stacking your dice? With non-conductive die attach, you could consider putting the OpAmp on top of the µC. Keep in mind, however, that you have pretty tight capacitive coupling, so EMI might be an issue.Max

author: Ammar
author_rank: Regular Contributor
timestamp: May 18, 2016, 10:06:35 am
content: Hi Max,I didn't consider this possibility. It may be a little tricky, as I am likely limited to wire bonding for both devices. If I could flip chip bond one, maybe. But good to consider, thanks.

author: ovnr
author_rank: Frequent Contributor
timestamp: May 18, 2016, 10:18:41 am
content: On packaging, one example is theMAX6126voltage reference - the µMAX packaged version simply has worse performance, both the A and B grade (see page 2). So there certainly is some secret sauce involved.You're pretty much just going to have to re-characterize the chip after removal to see if it conforms to your specs; the datasheet can no longer be trusted.

author: razberik
author_rank: Frequent Contributor
timestamp: May 18, 2016, 03:34:24 pm
content: I think that the group of people responsible for answer from Analog raised their eyebrows and scratched on head "Why anybody dare to trying etching our products to obtain bare die ?... not interested in answering".

author: Marco
author_rank: Super Contributor
timestamp: May 18, 2016, 05:34:58 pm
content: Couldn't you get it x-ray'd?

author: Ammar
author_rank: Regular Contributor
timestamp: May 18, 2016, 11:41:40 pm
content: My questions appears to have been removed from the Engineer zone forum on the Analog Devices website. Does anyone have any contacts at Analog devices who could help?

author: uncle_bob
author_rank: Unknown
timestamp: May 19, 2016, 12:25:24 am
content: Quote from: edavid on May 18, 2016, 04:47:50 amHiOther way around, package strain is modeled and the chip design is adjusted to eliminate the specific effects. Since at some level the strain is non-uniform, the suppression of the effects is not always trivial. If you re-package a part that is this finely tuned, your packaging may not match the original. Thus, the mount is indeed part of the design.Bob

author: Ammar
author_rank: Regular Contributor
timestamp: May 19, 2016, 12:28:11 am
content: Hi Bob,I imagine this would mean I need to be careful about how I mount the die. I know some glues can shrink upon drying. Is there an industry standard for adhesives that are used to mount the die? As in, aside from the epoxy packaging around it?Thanks

author: uncle_bob
author_rank: Unknown
timestamp: May 19, 2016, 01:01:22 am
content: Quote from: Ammar on May 19, 2016, 12:28:11 amHiThere are several thousand different materials you can / may / might use to mount a die. Epoxies are the most common, but there are a lot of them. If you happen to have a part that is mount sensitive and don't know what the process is ... plan on playing with quite a few before you get it optimized.Just for the record - the only thing I've seen this stuff in are very sensitive analog chips. Not every analog chip will have an issue like this. If it did, we would not have an IC industry. However when you want that last bit of performance and they go nuts on the design.... yes you hit these sort of things.Bottom line - this is why you have process engineers in an IC plant. This also is why designs cost more than just a mask and tape out charge. It also is why something more than blind simulation is part of the design process on any high performance part.Bob

author: rfeecs
author_rank: Frequent Contributor
timestamp: May 19, 2016, 01:16:22 am
content: Quote from: Ammar on May 19, 2016, 12:28:11 amDon't forget about thermal issues. Thermal resistance is one of the biggest issues in packaging. If you are dissipating any significant power you may need high thermal conductivity epoxy or even eutectic die attach.Thermal transients can sometimes be a headache for meeting specs like pulse response. These are also sensitive to the packaging.

author: l0wside
author_rank: Regular Contributor
timestamp: May 19, 2016, 09:00:02 am
content: Re stacked die: this works only if one die is significantly smaller than the other, you can then try wire bonding both, provided that the upper one does not obscure any (relevant) pads on the lower one.If they are about the same size, flip chip bonding (or soldering, depending on the pitch) could also help, but is anything but trivial even with good equipment. If in doubt, call the Panasonic SMT guys and ask if they would support you (other companies might also make flip chip bonders, but Panasonic is the only one I am aware of since it is not exactly part of my scope).Max

author: Ammar
author_rank: Regular Contributor
timestamp: May 20, 2016, 03:47:11 am
content: Believe it or not we actually have our own flip chip bonder in physics (I know, ridiculous). It looks like stacking them will not work as they are similar sizes.

author: Raj
author_rank: Frequent Contributor
timestamp: May 20, 2016, 06:09:34 am
content: The youtuber "applied science" has done it any times, even made a bare die ic work inside of an electron microscope for a while.his videos might help

author: uncle_bob
author_rank: Unknown
timestamp: May 20, 2016, 12:20:23 pm
content: HiUnless you are going to design the set of chips to stack *and* are willing to at least modify the design of the production gear ... don't go the stacking route. Just bond them up on a substrate and mount that in a package. The packages exist. The substrate is just a bit of thick film work. Laying one out and fabricating thick film is not a big deal. It's 1960's technology so it all is pretty well understood by now.Bob