Verilog generate and buses - Page 1
Forum section: electronics / general

author: EugenioN
author_rank: Contributor
timestamp: July 24, 2023, 02:16:12 pm
content: Hi all!I found myself stuck into a simple problem I cannot describe in verilog!I have 12 buses, each 16 bit wide, and I should 'or' them to create a single, 16 bit wide bus:Code:wire [15:0] this_sixteen_bits_data[11:0];wire [15:0] output_data;this_sixteen_bits_data=some_logic_instance_0;this_sixteen_bits_data=some_logic_instance_1;...this_sixteen_bits_data=some_logic_instance_11;assign output_data = this_sixteen_bits_data | this_sixteen_bits_data | ... | this_sixteen_bits_data;Trying not to go this verbose, a generate loop should be the way to go:Code:wire[15:0] this_sixteen_bits_data[11:0];wire [15:0] output_data;genvar i;generatefor (i=0; i<12; i=i+1) begin : wide_or_genvarthis_sixteen_bits_data=some_logic;output_data = ??? this_sixteen_bits_data;endendgenerateHow can you describe this parallel wide-or inside a generate loop?

author: asmi
author_rank: Super Contributor
timestamp: July 24, 2023, 02:30:20 pm
content: Not sure what you need generate for in this case, or anything else. Just use a simple bitwise OR (|):Code:result = bus | bus | ... | bus;Please do not confuse logical OR (||) with bitwise OR(|). There is also an unary version of OR (|some_var), which is also called "folding" or "reduction" operator, since it "folds" the multibit argument into a single bit. Some more reading here:https://verilogcodes.blogspot.com/2015/10/unary-or-reduction-operators-in-verilog.html

author: ejeffrey
author_rank: Super Contributor
timestamp: July 24, 2023, 03:43:58 pm
content: In addition to what asmi explained, even if you want to do this with a loop you don't need a generate block. A regular for loop inside a combinatoric process is enough.Generate for is mostly only needed when you need to create multiple copies of a submodule instance or a top level process.

author: EugenioN
author_rank: Contributor
timestamp: July 25, 2023, 09:02:57 am
content: Quote from: asmi on July 24, 2023, 02:30:20 pmYeah, this is my actual implementation.I don't like the cut&paste/verbose approach. I was wandering if there is a more concise way to describe it.

author: EugenioN
author_rank: Contributor
timestamp: July 25, 2023, 09:08:49 am
content: Quote from: ejeffrey on July 24, 2023, 03:43:58 pmI'm actually creating multiple copies of module instances, each generating a 16bit wide result.At the end, I need to (bitwise) 'or' those results in a single 16bit bus, so the generate loop is a 'free' resource I though I could take advantage of.Anyhow, never tried the for loop for actual sintesizable logic (testbench only). How can i write down this with for loop?Code:wire [15:0] this_sixteen_bits_data[11:0];wire [15:0] output_data;assign output_data = this_sixteen_bits_data | this_sixteen_bits_data | ... | this_sixteen_bits_data;

author: Someone
author_rank: Super Contributor
timestamp: July 25, 2023, 10:16:06 am
content: woror a variable in the loop

author: langwadt
author_rank: Super Contributor
timestamp: July 25, 2023, 01:06:07 pm
content: Quote from: EugenioN on July 25, 2023, 09:08:49 amsomething along the the line of this:Code:reg [15:0] output_data;integer i;always@(*)beginoutput_data = 16'h0;for(i = 0; i < 16; i=i+1)output_data = output_data | this_sixteen_bits_data;end

author: EugenioN
author_rank: Contributor
timestamp: September 11, 2023, 12:36:09 pm
content: Quote from: langwadt on July 25, 2023, 01:06:07 pmWorked great, thank you!