Single ended Fpga To Fpga bus safe speed? - Page 1
Forum section: electronics / projects

author: pacmann
author_rank: Contributor
timestamp: August 01, 2021, 11:44:59 am
content: I want to have a high speed bus between 2Spartan 6Fpgas. Whats a safe data clock speed I can use for the bus if single ended? They will be on the same circuit board 10cm away from each other and the tracks are going to be length matched.

author: pacmann
author_rank: Contributor
timestamp: August 01, 2021, 11:51:37 am
content: Also, I planned a single ended bus 32 bit wide. Is more bandwidth possible with a differential bus 16 bit wide? Is higher speed possible using the same pins but using differential pairs?

author: dmendesf
author_rank: Frequent Contributor
timestamp: August 01, 2021, 12:56:19 pm
content: Yes, you can have a faster bus with differential signals. If you used a spartan 6 with high speed transceivers (and connected the right pins the right way with the right impedance...) You could have a few GBps per pair of pins. With common spartan 6 if you connect differential pairs correctly then you can use ISERDES and OSERDES to achieve a few hundred bps per pair of pins.

author: Bassman59
author_rank: Super Contributor
timestamp: August 01, 2021, 11:17:44 pm
content: Quote from: pacmann on August 01, 2021, 11:44:59 amWe used to do parallel PCI at 133 MHz with 64-bit buses across VME boards, with proper line length matching and line impedance and minding the routing rules about jumping layers. So that's a good data point.Spartan 6 doesn't have gigabit-rate SERDES but you should be able to run the serial differential traces at their top rated speed across 10 cm of board. Again, mind the impedance and the routing.

author: dmendesf
author_rank: Frequent Contributor
timestamp: August 02, 2021, 12:54:08 am
content: Quote from: Bassman59 on August 01, 2021, 11:17:44 pmSpartan-6 LXT has gigabit-rate SERDES.

author: Bassman59
author_rank: Super Contributor
timestamp: August 02, 2021, 04:33:19 am
content: Quote from: dmendesf on August 02, 2021, 12:54:08 amAh, yes, indeed ... and it's been ages since I looked at the Spartan-6 devices. The world has moved on.

author: pacmann
author_rank: Contributor
timestamp: August 02, 2021, 09:24:51 am
content: Thanks all!Quote from: dmendesf on August 01, 2021, 12:56:19 pmIt looks like only only Spartan6 parts ending in T have high speed transceivers. Gigabit Serdes looks promising.Quote from: Bassman59 on August 02, 2021, 04:33:19 amIs there a reason to move on from Spartan 6 in new designs? Looks like it is still supported and cheaper compared to the Spartan 7.

author: pacmann
author_rank: Contributor
timestamp: August 02, 2021, 10:00:20 am
content: From the Spartan 6 data sheet.QuoteDoes this mean each differential pair can have a rate of 500 Mb/s in the example?If I want lots of bandwidth can I use 8 differential pairs and each one of those differential pairs uses a 1:4 ratio for 4 Gb/s total bandwidth assuming -1 speed grade?Do I have to worry about BUFPLL limitation or this will only use 1 BUFPLL because all the Serdes for the bus are using the same clock?

author: Berni
author_rank: Super Contributor
timestamp: August 02, 2021, 10:44:52 am
content: Each output buffer its its own thing so you can chain together as many as you want to get the bus width you want. But do take care that they can run from the same clock, its quite common on FPGAs to have them run from a few different clock buses. Its best to just try synthesizing what you want and see if the compiler lets you place the stuff you want on the pins you want. This is always a good practice before making a PCB, if the compiler says its ok then it is ok.Using DDR might also be attractive since it effectively doubles your speed, but this does make timing and routing a lot more stringent, so your choice if you want to take that risk. Usually FPGAs will have groups of DDR pins that have particularly well matched timings

author: dmendesf
author_rank: Frequent Contributor
timestamp: August 02, 2021, 01:08:46 pm
content: Does this mean each differential pair can have a rate of 500 Mb/s in the example?Yes. Mind that's an unidirecional channel.If I want lots of bandwidth can I use 8 differential pairs and each one of those differential pairs uses a 1:4 ratio for 4 Gb/s total bandwidth assuming -1 speed grade?Yes, but matching them can have some issues as another person said. It's best practice to try to sintetize your design first before doing your layout.Do I have to worry about BUFPLL limitation or this will only use 1 BUFPLL because all the Serdes for the bus are using the same clock?I don't remember the implementation details so can't help you here.

author: pacmann
author_rank: Contributor
timestamp: August 06, 2021, 07:34:02 am
content: Quote from: dmendesf on August 02, 2021, 01:08:46 pmQuote from: Berni on August 02, 2021, 10:44:52 amThanks!

author: pacmann
author_rank: Contributor
timestamp: August 10, 2021, 10:02:20 am
content: Quote from: Berni on August 02, 2021, 10:44:52 amQuote from: pacmann on August 02, 2021, 10:00:20 amIm a little confused about the data sheet. The SDR and DDR Serdes bandwidths are the same values in the chart. Does this mean the max Serdes clock speed will be 950 Mb/s for a speed grade -2 for example, but the data speed will be 1.9 Gb/s if using DDR Serdes?