HPAK 34420A Frontend Gain Divider - Page 1
Forum section: electronics / projects

author: Echo88
author_rank: Frequent Contributor
timestamp: August 31, 2021, 05:23:01 am
content: Studying the 34420A manual and the description of it in the Art of Electronics 3 page ~340 or so ive found myself asking why the gain-divider is split into two dividers (RP1A and U102-C).If it was only one divider then one could have omitted the buffers U307A/B.Was it just difficult to integrate the whole range of resistances onto one substrate, to increase the Gain Bandwidth or is there another reason im not seeing?Attached is an example in LTSpice which shows the way it was done in the 34420A to get the 5 different gains (1,10,100,1000,10000) and my single divider solution.https://www.manualslib.com/manual/1683654/Keysight-Technologies-34420a.html?page=115#manualhttp://www.ko4bb.com/getsimple/index.php?id=download&file=HP_Agilent/Agilent_34420A/Agilent_34420A_SCHEMATIC.pdf

author: antintedo
author_rank: Contributor
timestamp: August 31, 2021, 05:38:36 am
content: It could be to allow calibrating the meter without using a low thermal divider to generate 10mV and 1mV voltages. Each part of the divider could be calibrated independently using only commonly available 0.1-10V.

author: Echo88
author_rank: Frequent Contributor
timestamp: August 31, 2021, 07:16:54 am
content: Indeed, on Page 84 its stated:"The 1 mV and 10 mV gain verification is an optional verification test (seepage 86). These range gains are internally derived from the 100mV, 1V,and 10V range calibrations."Thanks for the hint antintedo

author: Kleinstein
author_rank: Super Contributor
timestamp: August 31, 2021, 07:44:12 am
content: There are several factors to favor the 2 step feedback divider:It is difficulty to have resistors over a large range of values (e.g. 100 K to 100 ohms) in one array.The 2 step divider can have lower noise, as the low part can use lower resistors. The low divider only sees a low voltage and thus can use smaller resistors. For the nV range and an amplifier noise in the 1 nV/sqtr(Hz) range, 100 resistance of the divider can make a difference.It does not look like they really make much use of this: the 2nd divider is not that much lower in resistance than the 1st.The 2 step divider could be used for a consistancy check for the gain / calibration. However this is still limited: the 2nd divider has a relatively low resistance and thus can not be used with a high applied voltage. So they would still need a relatively low test voltage (e.g. 1 or 10 mV) to do the calibration step. It can be used for internal calibration using the ADC result to compare the gain steps. This would still need some 1 mV or so test voltage, but no need for accuracy. This would have less demand on the ADC than ACAL directly relative to the ADC like done in the 3458.The spilt divider does not help with the GBW, it is more like making things worse, as there is another OP in the loop and this can complicate the compensation.The extra buffer amplifier could contribute to INL errors and offset. The offset is not a problem here, as the amplifier is included in the main auto zero cycle for the ADC and amplifier and the FET input stage also has quite some drift before the correction.

author: Echo88
author_rank: Frequent Contributor
timestamp: August 31, 2021, 08:24:44 am
content: Wouldnt the internal calibration work the following way?Apply 10V while both gain stages have G=1Apply 1V with first gain stage G=1, second gain stage=10Apply 1V with first gain stage G=10, second gain stage=1Apply 0.1V with first gain stage G=100, second gain stage=1Apply 0.1V with first gain stage G=1, second gain stage=100That way you characterised both gain stages for inaccuracies and are able to compute the lower 10mV and 1mV ranges with a sufficient accuracy.10V/5k (RP1A-Network overall resistance) = 2mA, that shouldnt be a too high load for the network i think when assuming good ratio TC?I cant see any part of the schematic that would produce the mentioned low 1-10mV to check the RP1A gain stage, but maybe its there somewhere.

author: Kleinstein
author_rank: Super Contributor
timestamp: August 31, 2021, 09:12:24 am
content: Having 10 V at the 5 K reistor network would be quite some power. It would not damage the part, but the accuracy would not be great, even with a low TC part. With the usual small parts 20 mW would already cause some 10 K of temperature rise and this would limit the accuracy. It may be still acceptable for the accuracy of the instrument and if using the high power only for a short time this could be OK. The AZ cycle is already only 50% duty cycle.The 100 mV step could also use a "gain" of 10 and 10 for the comparison and a consistancy check. This would likely be the preferred configution for the 100 mV range anyway.The calibration step may be reason why they used 5 K for the divider and not even lower resistance. So this could be a compromise for the ability to do the cal step and noise from the divider.

author: razvan784
author_rank: Regular Contributor
timestamp: August 31, 2021, 09:56:50 am
content: Please also look at the 34401A schematic, which is in many ways similar. My theory is that the 34420A was developed as an improvement on the 34401A, and they wanted to reuse the existing custom parts, such as the U102 resistor array.

author: Echo88
author_rank: Frequent Contributor
timestamp: August 31, 2021, 11:29:21 am
content: Crosschecked against 34401A razvan784, its indeed mostly based on the 34401A with its reused U101/U102.

author: antintedo
author_rank: Contributor
timestamp: August 31, 2021, 11:49:33 am
content: Quote from: Kleinstein on August 31, 2021, 09:12:24 amThe network used here is a large 14-pin CERDIP Alpha Electronics part. Assuming ~100K/W resistance the temperature rise will be low. TCR specification from the manual is 5ppm/K, typical TC matching is likely much lower. Specs for 10mV and 1mV ranges are over 25ppm and are significantly larger than self heating error.