What does this red bar represent Verilog simulation.  - Page 1
Forum section: electronics / general

author: Dmeads
author_rank: Regular Contributor
timestamp: May 24, 2019, 05:04:26 am
content: Hi!I was trying to make a latch in verilog.This is my code from eda playground:https://www.edaplayground.com/x/2A7sWhat does this red bar mean in the waveform viewer (see pic)? is it the stored bit?

author: ataradov
author_rank: Super Contributor
timestamp: May 24, 2019, 05:22:26 am
content: Undefined state. This means that no defined value was assigned to that signal. This is normal for signals to be in this state before the reset.In real life it will be stuck to some defined value, of course, but it may be random and unpredictable.The beauty of it for simulation is that undefined value propagates through logic. So if you use that signal in some logic with other defined signals, the result will also be undefined. So if you see this red stuff in your design after a global reset, your reset was not really global

author: ataradov
author_rank: Super Contributor
timestamp: May 24, 2019, 05:26:26 am
content: Also, what you are doing is not going to work in the actual hardware.

author: Dmeads
author_rank: Regular Contributor
timestamp: May 24, 2019, 05:36:52 am
content: the verilog wont work in the hardware? I know the test bench wont work because that uses non-synthesizable stuff right?

author: ataradov
author_rank: Super Contributor
timestamp: May 24, 2019, 05:48:36 am
content: The main part won't work. You can't just transcribe the circuit from logic gates to Verilog and expect it to work.Correct way to describe a D-latch would be something like this:Code:`timescale 1ns / 1psmodule d_latch(input clk,input reset,input CE,input D,output Q,output NQ);reg V;always @(posedge clk or posedge reset)beginif (reset) beginV <= 1'b0;end else if (CE) beginV <= D;endendassign Q = V;assign NQ = !V;endmoduleYou can adjust the polarity of the reset signal, or remove the clock enable (CE) signal if you want.But the main thing here is to have a register value ("reg V") that represents the "stored" quantity. In the real world it happens though an essentially analog feedback process, which can't be replicated reliably in digital logic (especially in FPGAs).

author: Dmeads
author_rank: Regular Contributor
timestamp: May 24, 2019, 05:56:39 am
content: gotcha.Just learned about Analog feedback processes.Thanks for the code, I will mess around with it.Also thanks for all your prior info. Digital logic/verilog/fpga stuff is not required for my major, and Im just learning it because I want to.You have replied to a bunch of my previous posts, and you give some good feedback. It all helps my learning process.

author: NorthGuy
author_rank: Super Contributor
timestamp: May 25, 2019, 04:50:32 pm
content: Quote from: ataradov on May 24, 2019, 05:26:26 amNot that this is a good idea, but you certainly can build latches from FPGA LUTs configured as NAND gates, and they will work.

author: ataradov
author_rank: Super Contributor
timestamp: May 25, 2019, 05:36:50 pm
content: Quote from: NorthGuy on May 25, 2019, 04:50:32 pmBut only if you manually instantiate FPGA primitives. No sane synthesizer will implement this exact Verilog code.

author: NorthGuy
author_rank: Super Contributor
timestamp: May 25, 2019, 06:18:00 pm
content: Quote from: ataradov on May 25, 2019, 05:36:50 pmI'm not an expert in Verilog, but I've tried to create an RS latch with VHDL in Vivado, and it implemented it with two LUTs without problems (except a warning about combinatorial loop):Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity top isport (r_in: in std_logic;s_in: in std_logic;led_out: out std_logic);end top;architecture bhv of top issignal q, nq: std_logic;beginled_out <= q;q <= not (not s_in and nq);nq <= not (not r_in and q);end bhv;

author: ataradov
author_rank: Super Contributor
timestamp: May 25, 2019, 06:20:36 pm
content: Things may have improved. I tried this at the time of ISE, and it errored on combinatorial loops like that. It may have been a more complicated scenario though. I have not tried a simple trigger like that, just by accident as part of a bigger system.

author: romhunter
author_rank: Regular Contributor
timestamp: May 25, 2019, 07:39:23 pm
content: Unrelated contribute though, if you want a latch in Verilog....Code:module SRLatch (input set,input reset,output q);reg latch;always @(set or reset)beginif (set)latch <= 1'b1;else if (reset)latch <= 1'b0;endassign q = latch;endmoduleQuartus did throw a warning about a latch, but it IS a latch...