Boost Converter PCB Layout - Page 1
Forum section: electronics / projects

author: Kuusou
author_rank: Regular Contributor
timestamp: November 12, 2020, 09:19:06 am
content: So this is my first boost converter design and I was hoping I could get some feedback on my PCB layout and inductor and diode selections. I'm using the FP6291 for the boost converter IChttps://datasheet.lcsc.com/szlcsc/1812101116_Feeling-Tech-FP6291LR-G1_C18701.pdfI've copied the typical application circuit from the datasheet. My project is powered by a single cell lipo with a voltage range of 2.9 to 4.25 volts with a max current draw of 2amps.The datasheet says the following about layout considerations:1. The power traces, consisting of the GND trace, the LX trace and the VCC trace should be keptshort, direct and wide.2. LX、L and D switching node, wide and short trace to reduce EMI.3. Place CIN near VCC pin as closely as possible to maintain input voltage steady and filter out thepulsing input current.4. The resistive divider R1and R2 must be connected to FB pin directly as closely as possible.5. FB is a sensitive node. Please keep it away from switching node, LX.6. The GND of the IC, CIN and COUT should be connected close together directly to a groundplane.Below is my schematic and pcb layout, any feedback on whether this design will be sufficient or if I'm making some major errors would be very much appreciated!coin simulatorAnother area of confusion for me is the inductor and diode selection. For the inductor the datasheet says:"Inductance value is decided based on different condition. 3.3uH to 4.7µH inductor value isrecommended for general application circuit. There are three important inductor specifications, DCresistance, saturation current and core loss. Low DC resistance has better power efficiency. Also, itavoid inductor saturation which will cause circuit system unstable and lower core loss at 1 MHz."I'm using the Sunlord MWSA0402S-3R3MThttps://lcsc.com/product-detail/Power-Inductors_Sunlord-MWSA0402S-3R3MT_C408336.html/?href=jlc-SMTAccording to the datasheet is 3.3uH, has a DC resistance of 87 (is this considered low?), and a saturation current of 3.50A, is this sufficient? I'm rather confused by the saturation current aspect.For the diode the datasheet says the following:"Schottky diodes with fast recovery times and low forward voltages are recommended. Ensure thediode average and peak current rating exceed the average output current and peak inductor current. Inaddition, the diode’s reverse breakdown voltage must exceed the output voltage."I'm using the MDD(Microdiode Electronics) SS34https://lcsc.com/product-detail/Schottky-Barrier-Diodes-SBD_MDD-Microdiode-Electronics-SS34_C8678.htmlWhat is considered a fast recovery time and a low forward voltage?I'm unsure what the peak inductor current is of the MWSA0402S-3R3MT mentioned above, is that the saturation current? Is this diode going to work?Any help reviewing my PCB layout or any thoughts on my inductor/diode choices would be very much appreciated!

author: Doctorandus_P
author_rank: Super Contributor
timestamp: November 12, 2020, 11:36:36 am
content: A simple thing to change would be to rotate D4 90 degrees which makes the copper track shorter.Also look up "hot loop" in combination with SMPS circuits.The idea is that noise is generated by the parts with high dI/dt values, which means: the switch, diode and output capacitors in this case.The current through the inductor only changes relatively slowly, and is therefore not a big part in the noise generation. Moving the inductor further away may even improve stability because less of the stray magnetic field is influences your circuit.

author: trobbins
author_rank: Frequent Contributor
timestamp: November 13, 2020, 06:24:32 am
content: You should look for a few other controller datasheets that go through the detailed design equations and discussion for simple boost converters. You need to be able to set up a design discussion that relates switching frequency, duty cycle, voltages, peak current levels etc, as they need to be aligned with your part datasheets. Until you know your parts can handle the operating conditions, and you have a loss budget, then you may be spending time on a pcb layout with the wrong part footprints.I recommend you focus on pin 2 of the control IC, as that needs to be a stiff star point for your switchmode currents, as well as control decisions - at the moment it appears to be hanging in the air. One means to appreciate that better is to mark out the current loops for the different portions of a switchmode cycle.

author: Kuusou
author_rank: Regular Contributor
timestamp: November 13, 2020, 10:46:57 am
content: Here is my new layout:Quote from: Doctorandus_P on November 12, 2020, 11:36:36 amI've been reading about hot loops all night but I'm still not very confident in determining them in my layout. My understanding is the main one is going from Vin to the switch, which is inside the IC, to the ground pin and then the return path, I believe I've made this small, what are your thoughts on my layout concerning that?My other concern is that you mention the noise from the switch, diode and output capacitors. According to that IC datasheet "FB (pin 3) is a sensitive node. Please keep it away from switching node, LX (pin 1)." So this would mean that the diode is a source of noise that needs to be kept away from pin 3, which basically means the entire Vout trace that also includes the output cap, I'm really not sure how to effectively layout this design other than to just move the diode and the output caps away from the pin a suitable distance, however I have no idea how I'm suppose to figure out what that distance is?Quote from: trobbins on November 13, 2020, 06:24:32 amI used a TI guide on "Basic Calculation of a Boost Converter's Power Stage" to make sure my components would work. I ended up calculating a peak current 1.35amps so I've also switched the diode to a much smaller onehttps://lcsc.com/product-detail/Schottky-Barrier-Diodes-SBD_Changjiang-Electronics-Tech-CJ-B5819W_C8598.html/?href=jlc-SMTwhich states it has a repetitive peak forward current of 1.5amps. My only concern is that according to the IC datasheet it states that the diode average and peak current rating must exceed the average output current and peak inductor current. My inductors saturation current is 3.5 amps, however the system will only really draw about 0.6amps of current in my testing, I've just over designed the traces for 2 amps. So in this case since I know the draw of the system and I've calculated the peak current that will be drawn from the lipo for the boost converter, is it safe to use this diode despite the fact that its peak current rating isn't more than the inductors?I'm also confused by what you meant with pin 2 of the IC, did you mean it's floating in that it didn't have a via near the pin taking it to the ground plane? Are my changes sufficient? I should mention that this is a two layer board with all the power and signal traces on top and the bottom being used as the ground plane.

author: Siwastaja
author_rank: Super Contributor
timestamp: November 13, 2020, 12:25:44 pm
content: C9, D4 and U4 form the critical path. Minimize that. Your feedback resistors can be further away; swap places with C9.Remove C10 or replace with the same value as C9.

author: Unixon
author_rank: Frequent Contributor
timestamp: November 13, 2020, 03:09:40 pm
content: Why are all capacitors orders of magnitude lower than recommended in FP6291 datasheet?Looks like you're trying to fit wrong capacitor packages in this layout...10-22uF caps should be at least 0805 or better 1206 / 1210, definitely not 0603 or less.

author: Siwastaja
author_rank: Super Contributor
timestamp: November 13, 2020, 03:21:18 pm
content: You can also parallel smaller caps to make them "hug" the critical loop or "spray" them on "top" of it so to speak, creating lower inductance than if you use one large capacitor: many smaller conform to the odd shape created by the other critical loop components. OTOH, using gazillion 0201 caps is obviously of no help and only extra work.If you need 20uF(nominal) at 5V, 0805 is kind of minimum sensible size; that could be 4 x 4.7uF in parallel. 10uF in 0805 would likely underperform more than you expect so you would needthreeof them instead of expected two, to get similar C. In 1210 size, you'll get a fairly well-performing 22uF part with some chances for it to deliver some 10uF actual.But always look up DC bias curves when selecting MLCCs. When the curves are not available, look at one with similar volume (remember height of the part as well!), similar dielectric rating (X5R, X7R etc.), and similar price, from a competitor who does publish said curves; at least you get the ballpark right.TDK publishes the curves in a nicely working interactive web page thing, you'll easily see actual capacitance.Regulator IC datasheet example circuits never talk about theactualcapacitance recommendation, they just recommend something like a "22uF MLCC", obviously the circuit was tested with a 22uF nominal part without giving the actual part number, so you need toassumewhat kind of part they used. I often assume they use parts with C = 50%nominal at the DC bias. So if you shop for the worst offenders, like those that only deliver 15% of the rated C, you are likely doomed with way too little capacitance. Or maybe you aren't; maybe the example designers used "worst offender" MLCCs as well and the circuit works with 3-4uF actual!There is always the option of understanding the circuit and calculating / simulating what'sreallyneeded, of course.BTW that datasheet "suggested layout" is (unsurprisingly; they often are) crap. The output capacitor is obviously misplaced, creating a huge loop with loop current flowing under the feedback resistor. The right spot next to the diode is completely empty, waiting for something to be placed there!

author: trobbins
author_rank: Frequent Contributor
timestamp: November 15, 2020, 02:44:02 am
content: Is there an issue with placing some parts on the other side of the pcb? In particular, you could reposition C7,C8 to be underneath L1, and hence loop to the central 0V via (next to pin 2) by a discrete trace.Similarly with C9,C10.When calculating peak design levels, such as inductor, FET, diode, it is worthwhile working through the worst-case part and parameter tolerances as to what the peak values could be, as 1.35A could well get to 1.5A unless you are somehow screening parts and parameters.

author: Kuusou
author_rank: Regular Contributor
timestamp: November 23, 2020, 10:07:18 am
content: I've taken what you've all said into consideration and updated my layout. I'm going with 4 10uF output caps in an 0805 package in parallel. I'm using the CL21A106KAYNNNE from Samsung Electro-Mechanics. Using their dc bias curve data fromhttp://weblib.samsungsem.com/mlcc/mlcc-ec.doI'm seeing a 50% bias at 5V so with 4 caps I'm expecting to get around 23uF. Is this acceptable or should I use cap with a higher capacitance rating that will allow me to reduce the number from 4 to 2?I also updated the size of the input caps to the 0805 package size and am using two 22uF caps. The site above doesn't appear to have any dc bias data on that particular model of capacitor (CL21A226MAQNNNE) however I'm assuming its the same as the 10uF capacitor and has a roughly 50% reduction at 5V.I've moved the resistors R8 & R9 out of the way of the output caps and have them connected via a trace on the ground plane on the underside of the board.On this board I'm using the backside of the board as a grounding plane (green) is the way I have my grounding of the IC and the various capacitor's acceptable?Also is the way I have my Vin trace connected to the inductor and input caps acceptable or should the trace be physically closer to the input caps than the inductor or does it matter at all?

author: trobbins
author_rank: Frequent Contributor
timestamp: November 24, 2020, 12:00:00 am
content: With respect to getting as clean a feedback signal as possible, the 'quietest' nodes to reference R8 and R9 to are the C6 positive terminal and the IC pin 2. At the moment, the reference voltage includes transient trace current between D3 and C6, and possibly some rear plane noise.Are you able to put a via directly on the IC pin 2 pad, and solder fill it after the IC is loaded ?

author: Kuusou
author_rank: Regular Contributor
timestamp: November 24, 2020, 12:09:29 am
content: Quote from: trobbins on November 24, 2020, 12:00:00 amSo are you saying I should move R8 & R9 upwards towards C6 and then connect the ground of R9 to the IC PIN 2 GND?Yes I'm able to place a via directly on the IC pin 2 GND and Kicad doesn't through any errors. I'm assuming the via would be filled with solder during the reflow since this board will be assembled with a pick and place machine.

author: trobbins
author_rank: Frequent Contributor
timestamp: November 24, 2020, 12:36:40 am
content: I'd suggest connecting R8 to C6 pos terminal, as that appears to be the quietest point in your output circuitry. R9 connection direct to pin 2 pad is likely a lesser concern, and may not be as simple to route. The R8/R9 node may be low enough an impedance not to pick up parasitic noise and noticeably affect performance - that could be tested during initial check-out by using lower values for R8/R9. Is that R8/R9 node isolated from the rear plane - it looks suspect ?The Pin 2 via suggestion is to reduce (as much as practical) the impedance from the IC out to the high current loop paths, and provide as clean a control node as possible (given that pin 2 is common to both control decisions and switchmode currents).

author: Kuusou
author_rank: Regular Contributor
timestamp: November 24, 2020, 12:50:15 am
content: Quote from: trobbins on November 24, 2020, 12:36:40 amNo I don't believe it is, do you mean having a separate grounding plane under the resistors that is connected to the surrounding grounding plane by one point?Here is my updated design, how does this look?

author: trobbins
author_rank: Frequent Contributor
timestamp: November 24, 2020, 01:23:47 am
content: I can see an isolated track now from the R8/R9 via to pin 3, so that seems fine, and it doesn't seem to degrade the ground plane.

author: aiq25
author_rank: Regular Contributor
timestamp: November 24, 2020, 08:45:31 pm
content: I would add a 100nF ceramic capacitor at VIN and VOUT. This will help with reducing high frequency noise that the larger ceramics might not filter.Also try to make the VIN trace a bit wider (if possible).Couple of design related questions:Are you controlling Q2 externally to turn ON/OFF the boost converter? I didn't see this mentioned in your posts. I would add a small gate resistor (maybe 100Ohm or so). This will help with EMC and limit the current draw in case of failure of the FET.You mention 2A maximum current. Is this the maximum current draw from the 5V rail (i.e. output of the boost)? The datasheet, and current handling capability of the IC, suggests 1A maximum output current. I have tested several of these IC's, including this IC before, and at lower VIN voltages the output is not a stable 5V, it starts to breakdown. If 2A is the maximum you are looking to draw from the 5V rail, I can explain further on what type of current handling capability you need. Your inductor will probably not work as well for 2A output current.

author: Siwastaja
author_rank: Super Contributor
timestamp: November 25, 2020, 10:47:36 am
content: Quote from: aiq25 on November 24, 2020, 08:45:31 pmWidely discussed, recently many threads here on the EEVblog forum, so let's just rectify it: this is a myth unless you can get the 100n MLCC in significantly smaller package and place it more optimally. Larger MLCCs filter high-frequency noise just as well, unless you have to use significantly larger packages. The actualvalueof impedance at the noise frequency is significant; not where the SRF dip is.This myth is based on times when large-value MLCCs were not available in small packages, and works for bypassing the inductance and ESR of massive elcaps or large film caps.Modern MLCCs have both very low L (due to small package) and ESR. A 2.2uF 0805 MLCC + 100n 0603 MLCC in parallel is roughly equivalent to the 2.2uF MLCC without the 100n.By paralleling different values of MLCCs you only create a possiblity of LC resonance between them, they are so low in ESR. It doesn't always happen but be careful not to create this possibility when there is no reason to.If you have an actual measured EMI problem, you may want to try that among others, but just don't do it by default.The original application "recommended circuit" engineer made the same mistake, by habit.

author: Kuusou
author_rank: Regular Contributor
timestamp: November 25, 2020, 01:29:13 pm
content: Quote from: aiq25 on November 24, 2020, 08:45:31 pmYes Q2 is being controlled by an ATtiny13A, are you saying to put a resistor between the fet and inductor?.Where are you getting a max output of 1A of the IC? The title of the IC datasheet says "1MHz, 2A Step-Up Current Mode PWM Converter" the only reason I can think you'd think it was 1A is because of the output current vs efficiency graph ending at 1A, which I don't know why they would do that. In either case the actual max draw of the board is only going to be 0.60A and I estimated the peak current of the boost converter to be 1.35A so it should be within limits, assuming that it is a 2A max.I've actually setup the boost converter to output 4.68V because I'm using a 68K and 10K resistor for the FB pin. According to the datasheet of the IC the min input voltage is 2.6, my battery protection circuit is set to cutoff power at 2.9 so that should be well within limits I would hope.Since you've tested tested this IC before do you believe these parameters will work with the IC? I've ordered 5 assembled boards from JLCPCB so I'm waiting on those to get in the mail to see how they holdup.Would changing the inductor from a 3.3uH to a 4.7uH reduce the peak current of the boost converter?

author: aiq25
author_rank: Regular Contributor
timestamp: November 25, 2020, 04:28:31 pm
content: Quote from: Siwastaja on November 25, 2020, 10:47:36 amGood points. I typically use 1206 and 1210 package sizes and being in automotive, I have had some issues with EMC before and needed to add the 100nF's, so you are right it's a habit of mine. I agree the design is fine without those capacitors.

author: aiq25
author_rank: Regular Contributor
timestamp: November 25, 2020, 07:39:24 pm
content: Quote from: Kuusou on November 25, 2020, 01:29:13 pmSee the attached image. I couldn't link it in the reply here for some reason.Just one more thing to note (which you might already know), this P-Channel FET is configured with an active low signal (meaning the MCU will have to output a 0/0V to activate the circuit). Since this is for a hobby project, it might not matter but I always prefer active high control. If for example the MCU output is LOW, during sleep or start-up, then this circuit can activate. Most MCU's should have the output tri-stated during start-up, so this should not matter during start-up but if your putting the MCU to sleep, make sure to tri-state the output or leave it HIGH to disable the converter.QuoteYes, I'm referring to the datasheet plots. The reason they do this is because, for a boost converter the output current is less than the input, and the 2A max they specify is the switch current limit. This TI document will explain the calculations for a boost converter better than I can:https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwiKh7_vtJ7tAhUyszEKHTKdBVEQFjABegQIAxAC&url=https%3A%2F%2Fwww.ti.com%2Flit%2Fpdf%2Fslva372&usg=AOvVaw2odrvZbTMQ2RmOBIMT9WMrBut for starters, here is some basic calculations (keeping in mind that the 2A current limit is for the switch, which you can tell from the TI document connects to GND, that means this switch will see all of the input current and assuming 2.9V input voltage):I_IN (input current) = (VOUT*IOUT)/(VIN*0.9) --> I am assuming 90% efficiency, the efficiency at this voltage level will most likely be less than this but it's an assumptionI_IN (input current) = (5V*2A)/(2.9V*0.9) = 3.83A. This means with a 2.9V input voltage, 90% efficiency, output voltage 5V @ 2A load current, your input current will be 3.83A. This IC cannot handle this. This equation also doesn't take into account the ripple current of the inductor. Let's say for example you have a 15% ripple current... that means your peak input current will be 4.4A.NOTE: The above calculations are for reference only. There are many more factors which you have to take into, which is explained in the TI document I linked above.Datasheets can be deceiving in their numbers and wording, so always look at the their limits in the tables. I have had a lot of discussions with TI about their deceptive datasheet numbers... Still annoys me but I will not go on a rant. lolThe reason he datasheet shows 1A output current is because of the following (they use similar equations but not exactly the one I have show, this is for reference):Assuming: VIN = 2.6V, I_IN = 2A, no ripple current, 90% efficiency, 5V output voltageWe get the following I_OUT:I_OUT = (VIN*I_IN*0.9)/VOUT ~ 0.936AQuoteThis should work. The problem with the current is at the lower input voltage ranges.QuoteDisclaimer: I'm not a magnetic components designer, so I speak from experience: Increasing the inductance will help limit your peak current, however, your DCR will typically increase and you will get a less efficient converter. I would recommend to try both values and see what works best. If you look into the datasheets and magnetic cores of inductors, you will see typically you have to derate inductors by 40-50 % (under worst case conditions). Hobby projects shouldn't see too much worst case conditions but I typically do a 40% derating of inductors.

author: aiq25
author_rank: Regular Contributor
timestamp: November 25, 2020, 08:26:54 pm
content: Quote from: Kuusou on November 25, 2020, 01:29:13 pmI missed the part where you said your output current. 0.6A output should be fine for this IC. You should be able to pull 1A out of it, with a 2.9V input voltage.By the way, I realized the datasheet doesn't specify the current limit under the MOSFET parameters in the characteristics table, but it is mentioned in the datasheet:Quote

author: Kuusou
author_rank: Regular Contributor
timestamp: November 25, 2020, 11:10:39 pm
content: First off thank you very much for your detailed and thoughtful response to my questions, so thankful for this forum and the help!Quote from: aiq25 on November 25, 2020, 07:39:24 pmI'm aware that the MCU has to send a low signal to turn the fet on, however my understanding is that with the resistor connected to the 3.3V rail from the gate it will keep the gate closed until that signal is sent. I'm putting the ATtiny13 to sleep majority of the time and only waking it on an interrupt pin, counting the amount of time its been pressed and if longer than 2 seconds than activating the fet. I'm not sure what you mean by tri-stated though, I've tested the code on a breadboard with an ATtiny13 and a fet, not this exact one but one similar and I didn't seem to have any issues, again the resistor is suppose to keep the gate high when connected to a battery so it shouldn't matter if the MCU is sleeping or not should it? It appeared to work in my testingQuoteI was using that paper to help me choose components as best I could but I'm still very new to this.Using your above equation with a 4.68V output, 2.9V input and 90% efficiency (which is what the datasheet graph reads at 0.6A output current) I'm showing 1.075A.According to that whitepaper the inductor ripple can be assumed to be anywhere between 20 to 40% of the output current so using equation 6 of the paperRipple Current = (0.2 0.4) x Iout(max) x Vout/Vin = 0.4 x 0.6 x 4.68/2.9 = 0.387I'm assuming the 0.387 is simply added to the input current for a total of 1.462A at worst case, is this correct? Since this is still below 2A I'm assuming the IC will still work?Thanks again for your help!

author: aiq25
author_rank: Regular Contributor
timestamp: November 26, 2020, 04:24:07 pm
content: Quote from: Kuusou on November 25, 2020, 11:10:39 pmNo problem, glad I could help.QuoteI think you should be okay. Tri-state means that the output of the MCU is in high impedance. I/O pins of MCU’s can be in three states (for most MCU’s): high (5V), low (0V) or tri-state, basically the I/O pin can be disconnected internally from the MCU or some of them they just create a high impedance output. As long as you don’t change the state of MCU I/O when going to sleep, it should keep it’s current state.QuoteYup, that’s the correct equation. The IC should work fine for your application. You have a lot of margin.