Add a small delay with verilog - Page 1
Forum section: electronics / general

author: PartialDischarge
author_rank: Super Contributor
timestamp: May 25, 2025, 06:40:33 pm
content: Need to add a small (2..4ns) delay to the output of a signal in Verilog for a Lattice ICE40 device. Asked Grok about how to add an additional buffer with no optimization and its telling me this. Is the(* syn_keep = 1 *)correct?Code:(* syn_keep = 1 *) wire buffer_delay;assign buffer_delay = in_signal;assign out_signal=buffer_delay;

author: Someone
author_rank: Super Contributor
timestamp: May 25, 2025, 10:50:29 pm
content: Adding delay should be done by timing constraints, and where they cant shift enough then its generally off to phase shifted clocks.Assignment is not a buffer.

author: PartialDischarge
author_rank: Super Contributor
timestamp: May 26, 2025, 12:14:35 am
content: Quote from: Someone on May 25, 2025, 10:50:29 pmOk, so how would I implement an extra buffer in verilog?

author: Foxxz
author_rank: Regular Contributor
timestamp: May 26, 2025, 01:52:07 am
content: add a couple stages to your pipeline.

author: Someone
author_rank: Super Contributor
timestamp: May 26, 2025, 03:07:10 am
content: Quote from: PartialDischarge on May 26, 2025, 12:14:35 amWhich lever in the cockpit is the throttle?You're building a footgun without understanding the technology. Read what and do what you want, but ignoring the well developed methods is foolish, expecting others to help you do stupid things? wow.

author: sigint
author_rank: Contributor
timestamp: May 26, 2025, 04:15:25 am
content: SB_GB My_Global_Buffer_i ( //Required for a user’s internally generated //FPGA signal that is heavily loaded and //requires global buffering. For example, a //user’s logic-generated clock..USER_SIGNAL_TO_GLOBAL_BUFFER (Users_internal_Clk),.GLOBAL_BUFFER_OUTPUT ( Global_Buffered_User_Signal));

author: pcprogrammer
author_rank: Super Contributor
timestamp: May 26, 2025, 06:08:51 am
content: Quote from: PartialDischarge on May 25, 2025, 06:40:33 pmThis is also assuming that a single buffer gives the wanted delay. For this one has to know what a "single buffer" in a FPGA is.For, in principle, clock signals there are dedicated clock buffers, that can be used to drive the clock routes. Depending on the FPGA and it's speed grade these might only give a very small delay.For logic, a buffer is not a basic element, for as far as I know. Logic is handled with the logic blocks that contain the look up tables and flip flops. These will have a bit more delay, but again depends on the speed grade.With modern FPGA's it is possible to have, for example, a Z80 core run at 100MHz or so, it is safe to say that the delays from the logic blocks are also very short.I agree with Someone and advice you to read up on how FPGA's actually work internally.

author: PartialDischarge
author_rank: Super Contributor
timestamp: May 26, 2025, 06:45:09 am
content: I'll investigate the timing constraints with Icecube2, although I'm curious about what the results of this code will be so I will program one Ice40 with it

author: glenenglish
author_rank: Frequent Contributor
timestamp: May 28, 2025, 03:28:02 am
content: Set this is timing constraintsadding logic to do that is HIGHLY unpredictable and will likely vary build to build (even if you change NOTHING due to random seeding of the place and router) , tool versions,and hopelessly unreliable.....Constrain the timing constraint.You MUST do this anyway for all the other signals .....Let the tools figure out what to do, they will do it in a deterministic way.If it cannot meet your tolerance, the tool will flag and fail it.

author: BlackHecilopter
author_rank: Contributor
timestamp: May 28, 2025, 04:46:40 am
content: You're going to need to try something like this using a BUFBA.https://www.latticesemi.com/support/answerdatabase/2/3/5/2354Certain Xilinx FPGA's, for instance, have an ODELAY primitive which provides a delay to the output path.https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/ODELAYE2Intel/Altera FPGA's have similar delay chain, in the IO Buffers (ALTIOBUF)https://www.intel.com/content/www/us/en/docs/programmable/683471/19-1/output-buffer.htmlhttps://www.intel.com/content/www/us/en/docs/programmable/683181/current/programmable-ioe-delay.htmlTake a look in the iCE40 handbook.I took a quick look through the iCE40 handbook and didn't see a similar primitive in the I/O block. But perhaps, I overlooked something...