Microstrip vs Coplanar Waveguide: Unexpected results with thin substrate. - Page 1
Forum section: electronics / rf-microwave

author: findAround
author_rank: Contributor
timestamp: September 07, 2023, 04:12:37 am
content: I'm trying to create a 50Ω feed line on a PCB, connecting a 433MHz transceiver IC to a PCB antenna. Using a trace impedance calculator, I enter values for trace width, height, etc, and get the resultant characteristic impedance. My substrate height (h) is a mere 0.11mm, which matches the thin prepreg used in PCBWay's 4-layer stackup.The confusing part:For a given trace width, both calculators I've tried (SaturnandCGI-Wcalc) are returning a HIGHER impedance for the coplanar waveguide configuration (with GND plane), compared with a microstrip configuration.I thought 'coplanar' copper adds extra (i.e. parallel) capacitance to GND, so having grounded copper next to a trace (in additionto below) would always give a lower impedance thanjustbelow (i.e. microstrip)?Putting a thicker substrate in the calculator, like 0.4mm, gives expected results: higher impedance for a lone microstrip, compared to the same trace width in a coplanar configuration.My question: With such a thin substrate, are the formulas used by the calculators giving incorrect results? Or are the results safe to use, and I'm just misunderstanding something? I want my 50Ω trace to be >0.2mm wide, and the calculator is telling me to use a coplanar waveguide configuration to achieve this, which seems wrong.

author: findAround
author_rank: Contributor
timestamp: September 07, 2023, 04:17:02 am
content: Example results from Saturn Conductor Impedance calculator:0.2mm Microstrip: 48.3Ω0.2mm Coplanar Waveguide: 52.7Ω

author: twospoons
author_rank: Frequent Contributor
timestamp: September 07, 2023, 05:03:01 am
content: Something you have to remember about these impedance calculators is the equations used are only approximations, that work within a limited range of geometries. Try several different calculators and you'll often get different answers for the same geometry.The best results come from using electromagnetic finite element simulation (though even that is still strictly only an approximation, given the discretized nature of the solver) .Problem is 2d FEA is a slow and tedious way to reach your target impedance, unless you have a script to set up the geometry, run the sim, and analyze the result.I know this isn't a particularly useful answer, but maybe get your geometry close with Saturn (or similar) then check it using something like FEMM4.2.

author: BigBoss
author_rank: Regular Contributor
timestamp: September 07, 2023, 06:00:39 am
content: Cadence AWR TX Line Calculator is quite accurate.

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: September 07, 2023, 09:20:25 pm
content: JLCPCB's own calculator is right on spot. It says 11.5 mil width for 50 Ohmson their JLC7628 process when layer 2 is GND. I made the trace intentionallynarrower and added some fancies to see how I'm punished.On the TDR, the 2 small peaks at division 7 & 8 are the SMAs. They aremuch better now than on rev. 1. You need SMAs with really thin center conductors.Those with a c.c. of nearly a mm will look like a heavy capacitor load. Even then,you need cutouts on layer 2 and maybe 3 and a lot of vias in the SMA GND.I used Rosenberger precision connectors.The impedance between the SMAs is just slightly higher than the solid cablebefore it, as expected.After all that FR4, the rise time is still below 50 ps, including the TDR rise time.That was the ordinary 4 layer process without controlled impedance option.regards, Gerhardps on 432, this does not matter.

author: twospoons
author_rank: Frequent Contributor
timestamp: September 08, 2023, 04:33:04 am
content: It would appear neither Cadence or JLPCB quote the geometry limits over which their calculators are valid.In the end the best thing you can do is tell your PCB fab which traces are controlled impedance, and let them sort it out. They will have done extensive testing of their processes and will know how to best achieve your target impedance.

author: Gerhard_dk4xp
author_rank: Frequent Contributor
timestamp: September 08, 2023, 05:29:22 pm
content: It seems, that is exactly what JLCPCB did. The epoxy THEY use, the prepregs, the soldermask.BTW I stumbled across a picture of ver.1, the same $5 / 5 boards el cheapo4 layer process. Only one end of the board was on the TDR; therefore we get a totalreflection on the far end. The fat SMA center connector and the pad produce alocal capacitance to GND and not 50 Ohms on this thin dielectric. Even the amount of solderand the fact wether the connector is populated make a difference. It's not the board alone.Gerhard

author: jayk
author_rank: Regular Contributor
timestamp: September 08, 2023, 09:03:07 pm
content: Here's your design simulated in Ansys Q2D with and without the coplanar ground. As expected the impedance is a bit lower with the coplanar ground.This was done with the free student version of Electronics Desktop.