Difficulty using a TCXO with Si5351A... - Page 1
Forum section: electronics / projects

author: t1d
author_rank: Super Contributor
timestamp: May 08, 2023, 11:38:35 am
content: Some (more) help, please and thank you… (See prior thread, for background =https://www.eevblog.com/forum/microcontrollers/windows-freeware-gui-for-si5351a-diy-function-generator/msg4841687/#msg4841687) But, I don't know that I can explain things so well... Here goes...I am working with building a Si5351A CMOS Clock Generator board. I received my boards and built one.I used an ECS-TXO-2016MV-250-TR oscillator, for the 5351's reference 25MHz oscillator, because the thermal drift of the pill-can types makes the circuit useless for true reference use. The TCXO's output is a little less than both Vdd and GND. See TCXO DS.It was pointed out that the Clock Gen chip only accepts a 1V input (on its XA pin,) when a common pill-can oscillator is not used. See 5351 DS: Figure 6.6/Pg23 and Table 13/Pg13. A resistor voltage divider was suggested for the needed level shift. I implemented it via a trim pot. I believe this may have been an insufficient means of level shifting.DC Coupled/x10/20Hz - Zoomed out to show TCXO's strange amplitudes at TP1V after pot. Note: GND is at the #1 channel indicator. Max amplitude is around 2/3rds of 1V increments. What appears to be noise at the top of the ~670mA amplitude is actually the needed 25MHz signal. See following...DC Coupled/x10/20Mhz - Zoomed in to show the correct signal between ~580mA and ~670mA.So, the signal is there, though of the incorrect amplitude and noisy.What I Suspect...That the amplitude is clipped.From GND up...- GND- TCXO's non-zero offset- Bottom of 25MHz signal- Top of 25MHz signal being clipped by 1V, plus TCXO's max rail offset.I think I need some type of level shifting that1) will drop the TCXO's output to true ground, which would allow the remainder of its upward amplitude to be used and2) will trim the TCXO's upper output all the way up to 1V. Meaning, the TCXO's natural shortfall to 1V would also be overcome.Maybe a solution would be a comparator, with hysteresis and trimming to the rails. To reach true zero, a negative rail will be needed.Occasionally, with much fiddling, some of the default settings signals can be captured. But, wholly unreliably and with much noise. We will deal with noise, later, as a separate subject.Thanks for your continued help and support.

author: t1d
author_rank: Super Contributor
timestamp: May 08, 2023, 12:15:29 pm
content: Board Pictures- DC0,1,2 were jumped.- The second pictures shows that the (old) solder paste did not float the chip well to cause it to self-seat. I checked for connectivity and there are no shorts. Next time, I will add a little fresh flux in with the solder paste.

author: newbrain
author_rank: Super Contributor
timestamp: May 08, 2023, 02:42:53 pm
content: Hi,Your worries about clipping etc. are unwarranted, the whole purpose of having a DC block capacitor (1 nF is fine) is so that the DC operating point of the XA input is decoupled from the TCXO output.I have measured a board I recently designed and built:0. I use the same TCXO, only in the 3225 size (easier to hand solder).1. The DC operating point of the XA input on my board it's very similar to yours: about 600 mV.2. I see you are using a 10 kΩ trimpot, not 5 kΩ as per the schematic.How is it set in the measurements you have taken?3. From my measurements, the XA input impedance is about 1100 Ω, so a 10 kΩ trimpot should be set at about 3/4 to have a 1 V signal:3.3 V × (1.1//7.5) / (2.5 + 1.1//7.5) ≈ 0.915 V, with // meaning "parallel".4. Why use a 20 MHz bandwidth limit on a 25 MHz signal? It will not affect the DC operating point, but itwillaffect the amplitude! The effect depends on the steepness of the filter, for my Rigol DS1054, it's about -2 dB (≈ -20%) for 25 MHz.5. That Si5351 is seriously askew, are you sure the connections are all there?Easter egg: search 'askew' on Google!6. On my board I drive the Si5351 input through a 560 Ω + 330 Ω voltage divider (plus cap), but driven from a 74LVC2G14 as I have other users of the 25 MHz clock and wanted to keep them isolated.This might be a bit too high a load to connect directly to the TCXO - its DS does not specify its driving strength: "CMOS" is a bit vague.7. Could you try replacing the trimpot with a single 2700 Ω resistor from the TCXO output to the DC block cap (i.e., replacing the upper section of the trimpot)?That value, together with the Si5351 input impedance should give about 1 VP2Pat the XA input, slightly higher or lower values should work too.

author: fourfathom
author_rank: Super Contributor
timestamp: May 08, 2023, 03:30:23 pm
content: There appears to be no reason not to drive the Si5351A XA input (pin 2) with a full-swing 3.3V logic level signal. I've done this on many designs using this part, with the source being either the output of a CMOS multiplexer, or directly from a small TCXO (such as the Abracon ASTX-H12). I've used a 25 MHz clock, and more often a 10 MHz clock.I do realize that the spec sheet doesn't say you can do this, but in my experience it works extremely well, and there are many examples of other designs that drive the XA input directly from a logic-level reference clock.

author: newbrain
author_rank: Super Contributor
timestamp: May 08, 2023, 03:56:38 pm
content: Quote from: fourfathom on May 08, 2023, 03:30:23 pmIt, in fact, says onemust notdo this, which is a different thing.In "Absolute Maximum Ratings", the voltage at XA and XB pins must be in the -0.5 V to 1.3 V interval.Why design outside AMR?If you want to do it, great, but I would not suggest it to a third person.The external clock driving voltage to XA pin is suggested to be 1 VPP, and DC blocked (to keep the DC operating point of the quasi-analog input).

author: fourfathom
author_rank: Super Contributor
timestamp: May 08, 2023, 04:20:39 pm
content: Quote from: newbrain on May 08, 2023, 03:56:38 pmYou are correct, regarding the published spec. But the Si5351 datasheet is notoriously incomplete, and incorrect in many places. I can show you many designs (not my own) in moderately high-volume production (thousands) where this part is being driven from a full-swing logic-level signal. From my tests there is no evidence of input clamping, no excess current consumption, and it works over at least a -10C to +60C temperature range.So in practice the direct input works.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: May 08, 2023, 08:33:16 pm
content: Quote from: t1d on May 08, 2023, 11:38:35 amSee the first reply above by newbrain.The Si5351A has a default CAP setting plus your scope probes plus your scope bandwidth that drops the signalFirst plot below shows the CAP loading effects with 10k pot.Second plot is using the field proven values given by newbrain above.The suggested values load 3v3 just under 4mA, which is OK, and those low values are enough to tolerate the scope probe and default Si5351 settings.The data says 'Default high drive strength' and the drive is set in the CLKn Control registers, so you should avoid resetting the default to lowest drive.Conclude: remove the 10k pot and use fixed resistors (560 Ω + 330 Ω voltage divider (plus cap))The XTAL CAP setting data in AN619 says thisCrystal Load Capacitance Selection.These 2 bits determine the internal load capacitance value for the crystal. See the CrystalInputs section in the Si5351 data sheet.00: Reserved. Do not select this option.01: Internal CL = 6 pF.10: Internal CL = 8 pF.11: Internal CL = 10 pF (default).I've tested 00, and it lifts XTAL Freq ~100ppm, but everything works fine, so looks to select minimum CL (pin C), a purist would select smallest CL when externally driven.Their 'do not select' comment would be to avoid XTAL OSC starting issues.Addit:I note there is now an alternative part,MS5351Mhttps://www.lcsc.com/product-detail/Clock-Generators-Frequency-Synthesizers-PLL_Hangzhou-Ruimeng-Tech-MS5351M_C1509083.htmlThis is a drop in almost exact replacement, and in a 2022.10.13 Data sheet they mention a eMSOP10 package optionMS5351 eMSOP10 MS5351 (ePAD 1.8 x 1.55mm)MS5351M MSOP10 MS5351MSiLabs quoted lower jitter for their ePAD QFN parts, so the eMSOP10 would be a nice option to allow for in any MSOP10 PCB layouts.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: May 08, 2023, 09:17:07 pm
content: Quote from: fourfathom on May 08, 2023, 03:30:23 pmInteresting to know. It's good to see you cannot instantly fry a part doing that.Did you check duty cycle on a XTAL to OUT bypass case ?

author: newbrain
author_rank: Super Contributor
timestamp: May 08, 2023, 09:43:32 pm
content: Quote from: PCB.Wiz on May 08, 2023, 08:33:16 pmAnd I must say that the second picture perfectly matches what I saw on my scope.I still think that for the risible cost and complexity of adding three passives, I would never go for a direct connection.

author: Someone
author_rank: Super Contributor
timestamp: May 08, 2023, 10:34:23 pm
content: Quote from: PCB.Wiz on May 08, 2023, 08:33:16 pmAlso noting that multi turn trimmers often have significant parasitics, which will not pass "high" frequency signals.

author: fourfathom
author_rank: Super Contributor
timestamp: May 08, 2023, 11:33:30 pm
content: Quote from: PCB.Wiz on May 08, 2023, 09:17:07 pmNo, I haven't looked at the XTAL to Out mode signal, but when I get a chance I will write the code to set that up and report back. I would be astounded if it wasn't extremely close to 50%, but let's find out.And as for "not instantly frying" the part, I assume you mean "not frying after more than 672,000 cumulative hours of operation"? Because there are at least thousands of cases where the Si5351A is being run in this mode, 24/7 for days at a time, with no ill effects. I've got several that have been running continuously for over six months.But sure, use a pair of resistors and a coupling cap. I won't scoff.

author: t1d
author_rank: Super Contributor
timestamp: May 09, 2023, 08:29:18 am
content: Thanks to everyone for doing such great work and contributing so much.I am embarrassed by1) my basic mistake of having the scope's 20MHz-BWL turned on (I will turn it off and re-test with the suggested resistor divider) and2) having installed the 10K trimmer, when the 5K trimmer was specified. I did this out of habit. I usually use a 10K for most things."use fixed resistors (560 Ω + 330 Ω voltage divider (plus cap))"I have no problem with removing the pot and replacing it with a resistor divider. The pot was intended to add flexibility in achieving the proper settings.I will have to go back through the posts to try to better my understanding. To be honest, much of it is beyond my hobbyist learning.I am pleased that there is so much interest in this project. I am very grateful to you.

author: t1d
author_rank: Super Contributor
timestamp: May 09, 2023, 10:44:02 am
content: I changed out the Trimmer to the Resistor Divider. I only had 560R and 270R in SMD, but these equate closer to 1V anyway.I re-tested the source 25MHz:Testing the three outputs is pending. Thanks, folks!

author: fourfathom
author_rank: Super Contributor
timestamp: May 10, 2023, 06:44:33 pm
content: Quote from: fourfathom on May 08, 2023, 11:33:30 pmThe Si5351 XTAL to OUT bypass case configuration bits don't appear to be as published in the AN619 spec, at least I can't make it work. I can fiddle with the other bits in that register and they do work, just not the CLKx_SRC = 00 or 01 modes. CLKx_SRC =11 works as advertised.So I just probed the "XB" output (pin 3) and the duty cycle is 50% when XA is driven by my 10 MHz TCXO (3.3V swing, 50% duty cycle). And it's still working fine.

author: PCB.Wiz
author_rank: Super Contributor
timestamp: May 10, 2023, 10:19:46 pm
content: Quote from: fourfathom on May 10, 2023, 06:44:33 pmThat sounds promising, useful info.