Is it possible to divide PWM duty cycle (not frequency!) simple way? - Page 1
Forum section: electronics / beginners

author: LinuxHata
author_rank: Frequent Contributor
timestamp: August 12, 2022, 07:06:36 am
content: Hello.I have a circuit, that manages DC 12V fan via standard 4 pin interface, where PWM signal at 20 khz is delivered via a separate wire.What I want to do, is to "divide" the duty cycle, while keeping the frequency. So say, duty cycle is 40% at input, and at output it should be 20% and so on.I built a simple microcontroller circuit and done that in software (capture input high-low durations, calculate frequency and duty cycle, output desired as needed), but I'm curious, whenever there's some other way of doing this, say using logic circuits or something similar? I've googled, but all answers show how to divide pwm frequency, not duty cycle...

author: pcprogrammer
author_rank: Super Contributor
timestamp: August 12, 2022, 07:22:13 am
content: What comes to mind is a monostable flip flop, or a timer circuit.Tuning the pulse on time can then change the pulse width of the original signal. It is not exactly a divide, because it is fixed length based on the setting of the monostable or timer and triggers on the rising edge of the input signal (or falling edge if so designed)

author: LinuxHata
author_rank: Frequent Contributor
timestamp: August 12, 2022, 07:38:57 am
content: Well that won't work - input duty cycle varies, so should do output too....

author: Ian.M
author_rank: Super Contributor
timestamp: August 12, 2022, 08:20:22 am
content: For fixed frequency PWM with one cycle delay between input and output, its conceptually fairly simple, but non-trivial to implement.The lineup is as follows:Pulsewidth => voltage + a sample and hold so its output is steady across each PWM period.An attenuator to set the input to output pulse width ratioA ramp generator and comparator to output PWM dependent on a control voltage. The ramp shall be triggered by an edge of the input PWM.One of the issues that adds complexity is that the input edge that triggers the ramp generator goes away at 0% and 100% duty cycle.When you start considering the details, the MCU based solution is certainly preferable to the mess of analog ICs required to implement the above.

author: mikerj
author_rank: Super Contributor
timestamp: August 12, 2022, 08:42:44 am
content: A simple(ish) analog method would be to low pass filter the incoming PWM, scale the resulting DC voltage and use it to set the duty cycle on a PWM generation circuit, either discrete using op-amps etc. or a dedicated IC like the LTC6992. This assumes the output doesn't need to be phase locked to the input and it wouldn't be a precision division but may be good enough. You could also LP filter the output and use negative feedback to get a more precise division.I don't think you'll be able to beat the simplicity of a small micro with suitable timer peripherals though.

author: pcprogrammer
author_rank: Super Contributor
timestamp: August 12, 2022, 08:52:35 am
content: Quote from: Ian.M on August 12, 2022, 08:20:22 amThe MCU solution will also have problems with that, because it will not receive triggers either.

author: pcprogrammer
author_rank: Super Contributor
timestamp: August 12, 2022, 08:54:10 am
content: Quote from: LinuxHata on August 12, 2022, 07:38:57 amCorrect, and that is what I indicated withQuote from: pcprogrammer on August 12, 2022, 07:22:13 am

author: Siwastaja
author_rank: Super Contributor
timestamp: August 12, 2022, 02:30:08 pm
content: Quote from: pcprogrammer on August 12, 2022, 08:52:35 amOTOH, the strength of MCU is, you can work around with software, for example implementing a timeout (somewhat longer than longest expected period) after which the software assumes 0% or 100% duty.if-elses get really annoying in analog very soon.

author: PeteH
author_rank: Unknown
timestamp: August 12, 2022, 02:40:48 pm
content: Something like using an LTC2644 with the timerblox chips mentioned above could do this with a simple analog divider ratio, or a simple low-pass.Not sure why the LTC6992 solution isn't valid given the initial question, maybe glanced over?

author: Peabody
author_rank: Super Contributor
timestamp: August 12, 2022, 02:52:28 pm
content: But you know, if you devoted an ATTiny85, or some similar MCU, to doing nothing but generate this PWM, it's still going to be the easiest, and probably the cheapest, alternative. And you could maybe connect a rotary encoder to it to let you adjust the PWM with the finest precision. One 8-pin MCU and a capacitor on its Vcc. You don't even need a crystal.

author: LinuxHata
author_rank: Frequent Contributor
timestamp: August 12, 2022, 08:44:17 pm
content: Well I was just curious, whenever it is doable using digital logic, not analogue circuitry.Btw, these LTC chips have chinese clones for a long time, and with even extended features, like direct 0-10V input

author: golden_labels
author_rank: Super Contributor
timestamp: August 12, 2022, 09:14:05 pm
content: Doable? Yes. Being simpler or having any important advantages? Consider this:In a 20kHz 8-bit PWM the shortest pulse may be 196ns, if we ignore jitter. In a microcontroller without dedicated logic, you need at least two operations to detect two edges, which puts the lower limit on clock frequency at 10MHz — much over that in reality. Discrete gates have 5–10ns propagation delay, worse if you want full voltage swing and need to account for stray capacitances and wiring. For a 3 layer NAND circuit that needs to do two transitions per pulse, you are ending in 100ns range. At this point I am completely ignoring the need for counters that can do 10MHz range counting: just the state machine that drives them.

author: KellyGreené
author_rank: Newbie
timestamp: August 13, 2022, 08:48:47 am
content: Check out this site, it can help you learn to calculate the duty cycle:https://www.theengineeringprojects.com/2016/02/generate-pwm-8051-microcontroller.html/?amp=1

author: eugene
author_rank: Frequent Contributor
timestamp: August 13, 2022, 12:49:26 pm
content: If what you really want to do is slow down the fan, then how about reducing the 12V supply?

author: Andreas
author_rank: Super Contributor
timestamp: August 13, 2022, 03:27:22 pm
content: The easiest way would be:- low pass filter + scale down (2:1 in your example) the amplitude of the 40% PWM.- give the low pass filtered analog value (~ 12V * 40% * 0.5 = 2.4V) to the positive input of a comparator.- feed the negative input by a 0 to 12V triangle wave form generator (integrator + comparator) with 100 kHz.If linearity is not essential you can also use a NE555 as "triangle" generator (followed by a 3:1 rail to rail amplifier to scale the 4-8V capacitor voltage to 0-12V)with best regardsAndreas

author: Andreas
author_rank: Super Contributor
timestamp: August 13, 2022, 07:38:44 pm
content: Hello,further optimization of component count is possible if the duty cycle ratio does not need to be adjusted.In this case we can directly scale the filtered input voltage suitable to the NE555 triangle voltage (1/3 to 2/3 of VCC).So only the NE555 + a comparator (e.g. LM393) is needed.(Hysteresis and pull up resistor not shown in the diagram).with best regardsAndreas

author: Terry Bites
author_rank: Super Contributor
timestamp: August 15, 2022, 03:56:33 pm
content: You could go mad and implement a codec with a DSP system.You can as mikej says use anlog regeneration- it will add a delay. Mostly the settling time of the LPF.If you're not in a rush to get the conversion done then this can give an accurate result.https://www.edn.com/cancel-pwm-dac-ripple-with-analog-subtraction/

author: antenna
author_rank: Frequent Contributor
timestamp: August 15, 2022, 04:28:39 pm
content: Maybe you could slow the fan down by taking a little off the beginning of the PWM waveform. I assume the rising edges are all happening at the clock edge so cant you just run the PWM into both inputs of an AND gate and use a delay/phase shift on one of the inputs? Maybe even something as simple as a capacitor on one of the AND gate inputs to slow the turning on of the gate. It wouldn't be divide by two, but you could at least slow it down.

author: KaneTW
author_rank: Frequent Contributor
timestamp: August 15, 2022, 05:05:50 pm
content: Tiny FPGA (or discrete logic if you feel like it) with a duty cycle counter, right shift by 1, PWM output. Some consideration for the case pwm_in=always 0 and pwm_in=always 1. Delay should be at most 1/20kHz.

author: JustMeHere
author_rank: Frequent Contributor
timestamp: August 15, 2022, 10:35:04 pm
content: Just stumbled across this: (PLLs do this for us)https://www.allaboutcircuits.com/technical-articles/understanding-pll-applications-frequency-multiplication/

author: LinuxHata
author_rank: Frequent Contributor
timestamp: August 23, 2023, 11:35:11 am
content: Well, the question was if it is possible to do purely via "logical" way, no analog to digital conversion involved. Because if I wanted to go that way, there's a special chip available for that, GP9301B. It costs 54 cents @ LCSC and can handle the task with ease.

author: jpanhalt
author_rank: Super Contributor
timestamp: August 23, 2023, 05:48:20 pm
content: With pure logic, you can double frequency. Then AND the original and doubled signals. Would only work with duty cycles ≤50% .I have not dabbled with inverting, etc. for duty cycles >50%,