Vias for BGA 0.8mm pitch - Page 1
Forum section: electronics / general

author: luiHS
author_rank: Frequent Contributor
timestamp: October 15, 2024, 04:57:47 pm
content: HelloI have some designs with a RT1064 BGA microcontroller with a 0.8mm pitch.The thing is that by using 0.2mm vias the PCB is more expensive than if they were 0.3mm, but I'm not sure if it would be correct to use 0.3mm vias with a hole with an external diameter of 0.45mm.The vias I have installed now are 0.2mm holes with an external diameter of 0.45mm. If I increase the hole to 0.3mm while keeping the external diameter at 0.45mm, the ring that remains is thinner and I don't know if it can cause problems.I am attaching images of both via configurations.

author: uer166
author_rank: Super Contributor
timestamp: October 15, 2024, 06:42:12 pm
content: 0.2 is probably the way. You don't want the annular ring to be so small and have a need for such good registration between drill and PCB. 0.2mm isn't thAt much more expensive anyway

author: luiHS
author_rank: Frequent Contributor
timestamp: October 15, 2024, 10:32:36 pm
content: Thanks, I finally asked JLCPCB and they told me that if the via diameter is not greater than 0.45mm I can have the drill at 0.2mm at no extra cost.What also happened is that I had the automatic calculation of the via diameter wrongly configured and for 0.2mm drills they set them to 0.4mm in diameter and that does have an extra cost. I also had the via diameter calculation wrongly configured for the internal layers on a 4-layer board, and some came out at 0.45mm and others at 0.40mm

author: glenenglish
author_rank: Frequent Contributor
timestamp: October 18, 2024, 07:12:42 pm
content: I use 0.45/ 0.2 with JLC for 0.8mm BGA..... no issue, but usually I use 1.2mm thick up to 8 layers which reduces aspct ratio related limits and yield issues

author: asmi
author_rank: Super Contributor
timestamp: October 18, 2024, 08:17:45 pm
content: Also, if you're designing 6 or more layer PCB with JLCPCB, I highly recommend using VIPPO.

author: bson
author_rank: Unknown
timestamp: October 20, 2024, 06:11:51 am
content: Note that JLCPCB plugs vias unless asked not to, making via in pad work just fine. At least for 4L+ boards.

author: ali_asadzadeh
author_rank: Super Contributor
timestamp: October 20, 2024, 12:17:09 pm
content: you can use 0.25mm with 0.45mm ring too

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 20, 2024, 08:20:09 pm
content: Does JLCPCB support blind & buried vias for they 6+ layer PCBs?

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 20, 2024, 11:10:25 pm
content: Quote from: bson on October 20, 2024, 06:11:51 amThey plug vias but with some resin. It's not conductive. So that's ok for larger pads (plugging this way will avoid vias to suck solder in) but can't be used for small pads like for BGAs, for which you need true VIP (which is plated over, VIPPO), which is available only for 6+ layers at JLCPCB and at a significant added cost. I've read somewhere that JLCPCB currently supposedly offers that at no extra charge, but using the online quote, it *is* definitely an extra charge (about $300 extra for a small 6-layer board in small quantities).

author: Tobias89
author_rank: Contributor
timestamp: October 21, 2024, 08:12:45 am
content: Considering the ball size of 0.3 mm diameter approximately, it's perfectly fine to use 0.3mm hole via with 0.6 mm external diameter.If you want to avoid via in pad, just offset them and you'll be fine (I've been doing this for the past couple of years).Here is an illustration:Depending on the number of signals you want to fan out, you'll maybe need blind/burried vias.. But if you are OK with TH vias, this is the way I recommend.

author: asmi
author_rank: Super Contributor
timestamp: October 21, 2024, 01:41:29 pm
content: Quote from: SiliconWizard on October 20, 2024, 08:20:09 pmUnfortunately no.

author: asmi
author_rank: Super Contributor
timestamp: October 21, 2024, 01:46:31 pm
content: Quote from: SiliconWizard on October 20, 2024, 11:10:25 pmVIPPO can be done with both conductive and non-conductive filling. The latter is offered for free for 6+ layer PCBs (and I've used it many times and it's great! I even posted some photos of such boards here), if you absolutely need conductive filling, then it's going to be expensive upcharge.

author: luiHS
author_rank: Frequent Contributor
timestamp: October 21, 2024, 09:37:09 pm
content: Quote from: Tobias89 on October 21, 2024, 08:12:45 amHow many layers for this routing? It seems like 6 layers for a 289-ball MCU.Is it possible with 4 layers for a 196-ball microcontroller like the RT1064, to route all the balls? Using normal vias so as not to increase the cost of the PCB.

author: bson
author_rank: Unknown
timestamp: October 21, 2024, 10:28:41 pm
content: Quote from: SiliconWizard on October 20, 2024, 11:10:25 pmThey plate it with copper after plugging. It's not entirely clear, but I read the following to say for < 6-layer boards they use epoxy, and for 6+ they default to copper paste (= conductive)."Vias are filled with epoxy resin or copper paste and then plated over to achieve an opaque and smooth finish.Click for detailed explanation① Vias are filled and plated over. Choose copper paste filling for applications requiring high thermal conductivity.② This process is the default for 6-layer and above multilayer boards.③ Compatible with via diameters from 0.15 to 0.5 mm."Here are the additional details:https://jlcpcb.com/help/article/pcb-via-coveringIt seems the main reason to use copper paste would be for thermal conductivity.But either way, with resin plugging and copper plating for exposed copper (pads) it should be perfectly find to use via-in-pad for BGAs. Assuming the via is small enough, of course.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 22, 2024, 12:33:25 am
content: Does it sound at all possible to have them manufacture a PCB for BGAs with 0.4mm pitch?

author: asmi
author_rank: Super Contributor
timestamp: October 22, 2024, 01:30:23 pm
content: Quote from: SiliconWizard on October 22, 2024, 12:33:25 amNot with VIPPO, as according to this articlehttps://jlcpcb.com/blog/Free-Via-in-Pad-on-6-20-Layer-PCBs-with-POFVthe minimum drill for them is 0.2 mm, and pad diameter is 0.3 mm. Which is obviously too large for 0.4 mm pitch BGA. Now, in another place they write that 0.15 mm drills are also supported for VIPPO, which will theoretically yield pad size of 0.25 mm, which is closer to what 0.4 mm require.I personally used their VIPPO process with 0.2-0.25-0.3 mm vias, and results we great.

author: asmi
author_rank: Super Contributor
timestamp: October 22, 2024, 01:33:44 pm
content: Quote from: bson on October 21, 2024, 10:28:41 pmThat's not been my experience. They use epoxy by default for free for 6+ layer PCBs (infact they automatically switch this option on in their quote form), but conductive filling is still a paid option.Quote from: bson on October 21, 2024, 10:28:41 pmYep, but it's too expensive to be practical in all but the most demanding cases.Quote from: bson on October 21, 2024, 10:28:41 pmYep, this is how I used them (and also inside thermal pads of QFNs).

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 22, 2024, 06:31:56 pm
content: Quote from: asmi on October 22, 2024, 01:30:23 pmAccording to their "high precision PCB" quote page, 0.15/0.25 vias should be fine, but it's an option with added cost compared to 0.2/0.3. Still, they prefer 0.15/0.3, so not clear what their decision factor is. I guess it may depend on your overall design and how copper is distributed to avoid under/over etching. With their "copper paste filled & capped" option, which I'm pretty sure would be mandatory for such a PCB, the added cost makes JLCPCB not as attractive as with more basic options compared to its competitors.Would be cool if they had a feature on their website where you could submit Gerbers and it would give you their recommended minimum options and DRC results, without having to submit an order.

author: asmi
author_rank: Super Contributor
timestamp: October 22, 2024, 07:28:51 pm
content: Quote from: SiliconWizard on October 22, 2024, 06:31:56 pmThe problem is that even if they will be able to manufacture 0.15/0.25 mm VIPPOs, you still won't be able to fit a trace between such vias placed on 0.4 mm grid (0.08 mm trace requires at least 0.08 * 3 = 0.24 mm, while 0.25 mm vias only leave you 0.15 mm). So you can only use very limited subset of such BGAs with signals no further than 2 layers deep. That is, unless you want to play this game with removing internal annular rings to provide just enough space for a trace.

author: SiliconWizard
author_rank: Super Contributor
timestamp: October 22, 2024, 08:46:10 pm
content: That's what they suggest:https://jlcpcb.com/help/article/BGA-Design-Guidelines---PCB-Layout-Recommendations-for-BGA-packages

author: bson
author_rank: Unknown
timestamp: October 22, 2024, 08:49:14 pm
content: Quote from: SiliconWizard on October 22, 2024, 06:31:56 pmYes!!!And also, getting a quote to price out options before even starting a layout, before anything resembling a gerber exists to begin with.

author: langwadt
author_rank: Super Contributor
timestamp: October 22, 2024, 08:57:47 pm
content: Quote from: asmi on October 22, 2024, 07:28:51 pmafaiu some manufacturer will automatically remove unconnected internal annular rings no matter what and claim it gets higher yield

author: asmi
author_rank: Super Contributor
timestamp: October 22, 2024, 09:13:45 pm
content: Quote from: bson on October 22, 2024, 08:49:14 pmYou can do it right now using their quote form. I do it all the time during PCB planning, as you can play around with different parameters to see if price difference would be justified by some other advantages. For example, for 10 layer boards 0.25 mm via and 0.2 mm via options were very close price-wise, so I went for 0.2 mm out of convenience, same thing about layer count - sometimes adding 2 additional layers make routing so much easier that this reduction of routing time offsets a relatively minor increase in price. I became a father recently, which drastically cut down on my spare time, so now that difference for a hobby project could mean if project gets completed at all or not, as I just can't devote as much time for it as I used to in the past.

author: Tobias89
author_rank: Contributor
timestamp: October 23, 2024, 06:21:03 am
content: Quote from: luiHS on October 21, 2024, 09:37:09 pmThis is a 6-layer fanout, but the electrical clearance used is very conservative (0.15mm / 6 mils). You can optimize the layer count if you use 4 mils.4 layers and normal vias doesn't seem possible to me. Either use a blind/burried vias or smaller clearance. If not both.

author: luiHS
author_rank: Frequent Contributor
timestamp: October 23, 2024, 04:48:08 pm
content: Quote from: Tobias89 on October 23, 2024, 06:21:03 amOk, I understand.Could we say that in a BGA up to the fourth row of balls we can get tracks with conventional vias and 4 layers, and beyond the fourth row it becomes complicated using only 4 layers?.So far I have not needed to get so many tracks from a BGA, but I have a project with an STM32 and an SDRAM memory that may need many ports, the version I made was with LQFP from an STM32H747, but I would like to do it with a BGA.

author: Tobias89
author_rank: Contributor
timestamp: October 24, 2024, 06:41:43 am
content: Quote from: luiHS on October 23, 2024, 04:48:08 pmFor 0.8 mm pitch BGA, count that you can fan out the outer two rows with no vias (maybe even three rows, depending on the clearance rule). The next two rows can be fanned out via TH vias, yes.But in this case you don't have any room left for the power and GND distribution, so it may not be too wise.Especially if you have SDRAM - you need to carefully route this by taking care of the characteristic impedance of the traces and matched lengths.I usually do this with 8 layers. 5 of them go to SDRAM traces:- GND,- signal,- GND,- signal,- GND.I.e., you have two sets of asymmetric striplines. Trust me, you'll want this.

author: asmi
author_rank: Super Contributor
timestamp: October 24, 2024, 01:49:03 pm
content: Quote from: luiHS on October 23, 2024, 04:48:08 pmSTM32H747XI? I've done a nearly full breakout on just 4 layers.

author: Tobias89
author_rank: Contributor
timestamp: October 25, 2024, 05:36:28 am
content: Quote from: asmi on October 24, 2024, 01:49:03 pmI'm not saying it's impossible. I just wanted to point out that in case of SDRAM routing, you're safer it will work if you have controlled impedance and lengths of the traces.I'm curious, what interfaces have you routed in these 4 layers? What is the stackup? Have you done testing already?

author: asmi
author_rank: Super Contributor
timestamp: October 25, 2024, 01:53:53 pm
content: Quote from: Tobias89 on October 25, 2024, 05:36:28 amThat MCU runs SDRAM at like 90 MHz or so, for that kind of speed you've got to seriously screw things up for routing to become a problem. so I wouldn't worry too much about those issues, unless they are seriously out of whack.Quote from: Tobias89 on October 25, 2024, 05:36:28 amThis was an SDR and it had a lot of stuff broken out - hence using such large package, notably it had QSPI running at 200 MHz connected to DDS, microSD card slot, some sensitive RF/analog stuff connected to ADCs, and a lot of GPIO for various control signals of RF part of the board. That board was implemented years ago (pre-COVID) and as far as I know all PCBs I've built are up and running fine.

author: bson
author_rank: Unknown
timestamp: October 29, 2024, 06:04:22 pm
content: [ Specified attachment is not available ]Quote from: Tobias89 on October 24, 2024, 06:41:43 amThis really depends on the ballout. Sometimes BGAs have supplies and oscillators in the outer two rows, in which case it's easy to decouple them closely on the top side and place a "frame" shape power plane around the outer perimeter on an inner layer. The outside TH vias don't really make for much of a problem.At other times, they're in the center, so don't need to be escaped at all and can just be connected with in-pad TH vias to a plane below. They only make an obstacle for cross-package traces.Note that the difficulty of escaping is not due to the number of pads per se, but the % of pads used. If you go to a bigger package with more balls but don't use any of them you lower this percentage, creating openings that will make escaping it easier.Here's two examples, one with power and XO along the outside, one combining this with power at the center. Power in the center is IMO easiest to decouple on the opposite side.Edit: I don't know why, but this idiotic forum software will only inline one of the images no matter how I try to tell it to inline both