STM32H7 CortexM4 USART DMA issue - Page 1
Forum section: electronics / general

author: Diego_2024
author_rank: Newbie
timestamp: April 27, 2024, 10:32:11 am
content: I'm trying to use USART + RTS only + DMA(non circular, peripheral to memory, DMA1 Stram0) on STM32H755ZIT6's M4 processor. I and D caches are enabled on M7. My code is working on M7 but it does not works on M4.// u8* dma_rx_buffer_ = (u8*)((u32)0x24000000);// u8* dma_rx_buffer_ = (u8*)((u32)0x38000000);u8* dma_rx_buffer_ = (u8*)((u32)0x30000000);int main(void){//SCB_InvalidateDCache_by_Addr((u32*)dma_rx_buffer_, 14);error = HAL_UART_Receive_DMA(&usart2_dma_, dma_rx_buffer_, 14);}as you can see I'm setting RAM_D2's address to the dma_rx_buffer_, but I can't use SCB_InvalidateDCache_by_Addr on M4.This is M7's Flash.ldMEMORY {RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512KFLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024KDTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128KRAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288KRAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64KITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K}this is M4's Flash.ldMEMORY{FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024KRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 288K//RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K//RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K}I also tried to add RAM_D1 and RAM_D2 inside M4's Flash.ld file and use it like this `attribute ((section(".RAM_D2"))) attribute ((aligned (32))) u8* dma_rx_buffer_;but no result.I also read DMA is not working on STM32H7 devices, but can't find solution.P.S all configurations, including DMA are correct .Also when I'm setting different addresses for dma_rx_buffer_ then I'm getting different data.Do I need to add MPU region for CortexM4?Update: Configured MPU region accrding DRAM addresses, but no result, with RAM_D1, RAM_D2 or RAM_D3./* Disable fault exceptions */SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;/* Disable the MPU and clear the control register*/MPU->CTRL = 0;MPU->CTRL = MPU_PRIVILEGED_DEFAULT | MPU_CTRL_ENABLE_Msk;SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;__DSB();__ISB();MPU->RNR = MPU_REGION_NUMBER8;//MPU->RBAR = 0x24000000;//MPU->RBAR = 0x38000000;MPU->RBAR = 0x30000000;MPU->RASR = ((uint32_t)MPU_INSTRUCTION_ACCESS_ENABLE << MPU_RASR_XN_Pos) |((uint32_t)MPU_REGION_FULL_ACCESS << MPU_RASR_AP_Pos) |((uint32_t)MPU_TEX_LEVEL0 << MPU_RASR_TEX_Pos) |((uint32_t)MPU_ACCESS_SHAREABLE << MPU_RASR_S_Pos) |((uint32_t)MPU_ACCESS_CACHEABLE << MPU_RASR_C_Pos) |((uint32_t)MPU_ACCESS_BUFFERABLE << MPU_RASR_B_Pos) |((uint32_t)0x00 << MPU_RASR_SRD_Pos) |((uint32_t)MPU_REGION_SIZE_32B << MPU_RASR_SIZE_Pos) |((uint32_t)MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos);What else can I do?

author: Silenos
author_rank: Regular Contributor
timestamp: April 28, 2024, 04:31:16 pm
content: What's "RTS"? How it "does not work"? What are DMA registers values and what they mean? Did you set DMAMUX? Is the M4 core running nominal?Also at least some H7s have botched USARTs which hang after some time when used with DMA. You have to flip certain undocumented magic bit to make it work, it is described in some errata.

author: Diego_2024
author_rank: Newbie
timestamp: April 29, 2024, 08:16:37 am
content: what is RTS? seriously?