Interfacing sun-readable QVGA TFT to STM32F429 - possible or not? - Page 1
Forum section: electronics / general

author: Yansi
author_rank: Super Contributor
timestamp: March 29, 2015, 07:43:12 pm
content: Hi,some months ago, I scored a few interesting QVGA LCDs, which are possibly classified as "sun readable". The TFT matrix looks gray (opposed to classic black) and the datasheet claims superior brightness of 270nits (twice the Samsung Galaxy S3). Which is nice, but the interface is somewhat weird, never seen anything like this.So the question is, is it possible to interface this puppy to a standart TFT controller, like the LTDC peripheral in STM32F429 ?Standard TFT controller offers only color data signals plus VSYNC, HSYNC, ENABLE and CLOCK. If you look at the display's interface, it has some more strange signals, which I don't know what to do with now.The datasheet of the module is here:http://www.mouser.com/ds/2/365/LQ035Q7DH07N_SPEC_LD-21910A-184021.pdfAre these two interfaces compatible, or is the problem solveable with some glue logic, or completely incompatible and I have a bunch of useless LCDs?Thank you for your helpY

author: nctnico
author_rank: Super Contributor
timestamp: March 29, 2015, 08:10:20 pm
content: There are timing diagrams in the datasheet which tell you when to apply the signals.

author: Yansi
author_rank: Super Contributor
timestamp: March 29, 2015, 08:16:10 pm
content: I understand what you mean. You mean GTFO do it your self don't hassle us if its not arduino. Got it. I will do it myself.Sorry for another useless thread. Only tried to share the problematic, considering this helpful.

author: Rasz
author_rank: Super Contributor
timestamp: March 30, 2015, 01:30:38 am
content: Quote from: Yansi on March 29, 2015, 08:16:10 pmgot some sand in your vagina?datasheet shows timing diagram, you need lower level than ordinary lcd controllers, small cpld will suffice

author: zepto
author_rank: Regular Contributor
timestamp: March 30, 2015, 02:57:08 am
content: I do not have any experience with these.It looks like VSYNC,HSYNC, etc are inputs to a timing controller that outputs the necessary signals.LZ9FC22seehttp://www.ti.com/lit/an/spra968/spra968.pdffor an example.

author: splin
author_rank: Frequent Contributor
timestamp: March 30, 2015, 05:31:34 pm
content: Quote from: Yansi on March 29, 2015, 07:43:12 pmIt looks to be fairly straightforward, but you will have to use some glue logic to generate some of those signals. A CPLD would be good but I wouldn't worry about using a few discrete logic gates and flip-flops.I've not spent too long looking at the timing but everything starts with HSYNC. You could perhaps use that directly for LP and use external logic to create the PS, CLS and SPL signals derived from DCLK (LCD_CLK from the STM32F429). The DISPLAY ENABLE (DE) turns on too late for SPL but the on to off edge would be used to take CLS low at the end of the row followed by taking PS high.You might however be able to use VSYNC directly for the vertical timing signal SPS.You also have to invert the +/- 2.5V AC component of VCOM every line; you could use the rising edge of PS for this providing you meet the 1us min Thvcom time after CLS goes low. It appears you also need to invert it on every frame as well:Note [7-5] VCOMAC should be alternated on VCOMDC every 1 horizontal period and 1 vertical period.Have fun - definately worth a go,Splin

author: Yansi
author_rank: Super Contributor
timestamp: April 04, 2015, 01:55:58 am
content: I've already thougt about it a little. and come up with some possible solutions. Not complete one, but partial, let's see:First, there some singnals that makes no trouble - like MOD, U/L and LBR. They are static signals, no problem.SPS signal looks like to be equivalent with VSYNC, or possibly shoud be connected to it and generated that way.Then there are LP (Latch pulse) and SPL (sampling start) signals. It seem that every horizontal scan begins with a LP high pulse for 1 CK. Then horizontal back porch timing applies for unknown number of cycles (i haven't seen the number in the datasheet) and just 1 CK before image data starts to flow, SPL signal pules high. So the basic thought was to use VSYNC signal (need thorough checking the manual of STM32F429 if it is really possible to do). Using the VSYNC as folows: On rising edge generate pulse on LP, on falling edge generate pulse on SPL. (so there is naturally 1 CK delay between VSYNC low and image data comming. - need checking the LTDC peripheral! haven't checked that yet).I am completely fine using some PLD, I appreaciate the opportunity to have a small HDL exercise with this. But what I am not fine is that the smallest PLD I found (and know how to use out-of-the-shelf) is Altera EPM3064 in TQFP44 package. That is still big beast! only 44 legs and it is still damn big. (0.8 lead pitch). PLDs in smaller packages seem to be un-obtainium. At least from Altera.

author: ale500
author_rank: Frequent Contributor
timestamp: April 04, 2015, 06:57:59 am
content: Hello !As a low power CPLD you could use a MachXO2-256ZE from Lattice. The ZE variant is the lowest power in the family. Controlling that LCD doesn't look very difficult, but the uC doesn't have all signals. It looks very do-able.

author: nctnico
author_rank: Super Contributor
timestamp: April 04, 2015, 10:17:07 am
content: Look at the XC9500 series from Xilinx. These start in 44 pin PLCC packages. I always use these for glue logic or frame converters to drive TFT screens.

author: Yansi
author_rank: Super Contributor
timestamp: April 04, 2015, 12:02:07 pm
content: ale500: No experience with lattice. What package is it in at what cost?nctnico: That fails right there, as 44pin PLCC is hell of a big beast. TQFP44 I mentioned above is about size of a PLCC32 package.I have no estimation for the power consuption of the Altera EPM3064, but I wouldn't consider that low power.Maybe it would be possible to make the glue logic from discretes logic (74LVC) in TSSOP packages, if it will be simple enough - the consuption of a few 74LVCs will be considerably lower, than the Altera PLD. (or not?)..but I think it won't be pretty, as only the generation of LP and SPL signals demands four D flip-flops and a bunch of logic around.See the example state machine, that probably should work for the LP signal (and for SPL invert all the ones and zeros at HSYNC) - works as an HSYNC falling edge detector, makes single pulse at the LP output.

author: legacy
author_rank: Super Contributor
timestamp: April 04, 2015, 12:23:24 pm
content: Quote from: Rasz on March 30, 2015, 01:30:38 amlet me guess the reason why you troll people here

author: legacy
author_rank: Super Contributor
timestamp: April 04, 2015, 12:25:17 pm
content: Quote from: nctnico on April 04, 2015, 10:17:07 ami do exactly the same, i think it's a very good tips

author: Yansi
author_rank: Super Contributor
timestamp: April 04, 2015, 12:38:32 pm
content: I think it is obviously not. XC95 is I think some old 5V series PLDs, hungry for supply current.And oh my good, why the PLCC44, it takes a fuckton of space !!!! And I already consider teh TQFP44 way too big!Heres a comparison. QFP44, your PLCC beast and an MCU I will use. Still you don't see, why i DO NOT want any PLCC?

author: nctnico
author_rank: Super Contributor
timestamp: April 04, 2015, 04:19:27 pm
content: Try and look first and then complain. A few TSSOP package will need more surface space than a single QFP44. Since you clearly have little insight in how the logic should work I suggest to go with a CPLD.

author: Yansi
author_rank: Super Contributor
timestamp: April 04, 2015, 05:08:55 pm
content: Leave these cheeky comments for yourself, I have enough clue, how to do a state machine without PLD.Few small packages will be more tolerable for my design, than your PLCC44. You have not enough clue, what my design needs or needs not, so stop throwing at me the PLCC shit!

author: janoc
author_rank: Super Contributor
timestamp: April 04, 2015, 05:21:46 pm
content: Quote from: Yansi on April 04, 2015, 12:38:32 pmI think he meant the newer XC95xxXL series, not the old, expensive and huge 5V-only XC95.. (without the XL suffix) ones. The XL parts run at 3.3V, but still are 5V compatible. And they *start* in PLCCs, other packages are available too (I am using them in normal QFP packages). It is an old series, though. If you don't need 5V compatibility, then you can check out the CoolRunner CPLDs.Then there are the Altera and Lattice parts, don't have any experience with those, though.

author: Yansi
author_rank: Super Contributor
timestamp: April 04, 2015, 05:26:04 pm
content: XL... I didnt know about them, will take a look whats different, thanks.It is strange to me, that in 2015 getting a small PLD with low pin count is like a search for unobtanium. I must definitely missed something.//sorry for my previous reply, I got very pissed.