An alternative to quartz filters. - Page 1
Forum section: electronics / rf-microwave

author: MikeP
author_rank: Regular Contributor
timestamp: December 13, 2020, 08:15:51 am
content: Hello.This is not my area, so I ask you to forgive my naivety.In the range from 3 to 10 MHz, it is necessary to allocate several 3 kHz bands. The bands are arranged in series.This task is solved by quartz filters. Out-of-band attenuation - 80 dB, squareness ratio at the level of 80/3 dB - 2.5.My question is, what alternatives are there? Is it possible to digitize the signal for further processing, while maintaining the existing accuracy?Thanks.

author: radiolistener
author_rank: Super Contributor
timestamp: December 13, 2020, 11:22:19 am
content: You can digitize it and apply digital bandpass filters. But dynamic range will be limited by your ADC.In order to maintain 90 dB dynamic range you will need to use (90-1.76)/6.02 = 14.6 = 15 bit ADC.

author: MikeP
author_rank: Regular Contributor
timestamp: December 13, 2020, 04:14:38 pm
content: Thank you very much. I also came to 16 bits. It turned out that 16 bits is the limit for fast ADCs.It seems to me that there should be a relationship between system response time and sampling rate. What values can be obtained with the available ADCs?

author: gf
author_rank: Super Contributor
timestamp: December 14, 2020, 12:28:24 am
content: How many is "several"? Al least what magnitude? (7MHz/3kHz could be as many as > 2300)What's the spacing between the (centers of the) bands? Are they equally spaced?Do you need them all simutaneously, or does it suffice to tune-in one band at a time?What kind of signal (modulation) do the bands carry? Is the eventual goal to demodulate them?Can frequencies >10 MHz be present in the input signal as well?I'm afraid that a 3kHz FIR bandpass with low pass-band ripple, 80dB stop-band attenuation and steep cut-off, running at a samping rate of >20 MSa/s (which is required for 10MHz - in practice rather more), may require a huge number of taps.

author: mawyatt
author_rank: Super Contributor
timestamp: December 14, 2020, 02:52:26 am
content: ~40 years ago we needed to pick out a low level signaling 10Hz tone at >>50MHz that could be located at many different frequencies, heterodyning to an IF and crystal filters were "thought" to be the only practical solutions back then. We came up with a new type solution based upon a "Commutating Filter" originally described back in the 1960s which utilized a car distributor as a commutating switch driven by a 60Hz synchronous motor at 3600rpm which also drove another car distributor in synch. Each of the 8 "spark plug" connections on each distributor was connected by a simple RC low pass filter, series R, shunt C, resulting in an extremely narrow band filter centered around the 60Hz motor speed. Vary the speed of the motor and the narrowband filter moved to the new speed!Of course we used very high speed (at that time) NMOS switches instead of a car distributor, and a low noise frequency agile synthesizer for the motor:)Much later this led to the development of a new type passive mixer called a Polyphase Phase Mixer (our terminology), N-Path Mixer (university terminology), or Mixer First (other terminology). This new type mixer bypassed conventional thinking and produced measured results that were thought impossible (< 3.92dB NF (loss) for a passive bi-phase mixer), and the bandpass directly follows LO, even does a direct I/Q downconversion. The mixer input 3rd intercept is defined by the switch linearity, which can be quite high for large NMOS switches. In fact this circuit was so controversial and unique it created a DARPA workshop all it's own back in 2013, called Mixer First, everybody involved in advanced unconventional signal processing research was there, standing room only. We were asked to present at the workshop, although most of our work was/still is proprietary. The first public papers on this subject are from Cornell around 2009~2011 in the IEEE, authors are A. Molnar and C. Andrews, first publicly discussed at the IEEE ISSCC in 2009.

author: radiolistener
author_rank: Super Contributor
timestamp: December 14, 2020, 03:20:02 am
content: Quote from: MikeP on December 13, 2020, 04:14:38 pmWhat response time you're talking about?Do you have specific requirement for the filter phase delay?There is relationship between bandwidth and dynamic range. High speed ADC has wide bandwidth and it's dynamic range/bit resolution is specified for a full ADC bandwidth, which is a half of sampling frequency:bandwidth = sample_frequency / 2If you apply bandpass filter, you're cut off part of noise power and it leads to lower noise floor and dynamic range gain. This is known as processing gain:processing_gain_db = 10 * log10( input_bandwidth / output_bandwidth )for example, if you're using 125 MHz 16 bit ADC and digital filter to get 3 kHz output, you will get:processing gain = 10 * log10( 125000 / 3 ) = 46.2 dBprocessing gain = 10 * log10( 62500 / 3 ) = 43.2 dBADC has 125 MHz sample clock, so it has 125/2 = 62.5 MHz bandwidth.ADC has 16 bit, ideal 16 bit ADC has 16*6.02+1.76 = 98.08 dB dynamic range (real ADC has a little worse).For 3 kHz output you will get about 98.08 + 43.2 = 141.3 dB dynamic range.But note, your dynamic range increasing at the bottom due to noise power filtering.The max ADC input power limit remains the same.So it's hard to say if you can replace analog filter with digital processing, because it depends on the total power of unwanted carriers within 3...10 MHz bandwidth, which you want to cut off.For example, if you're needs to get 3 kHz at 4 MHz and 3 kHz at 6 MHz, but there is very strong carrier at 5 MHz which leads to ADC overload, you will need to add attenuator to avoid ADC overload from 5 MHz carrier, but as a side effect such attenuator also will reduce dynamic range for 4 and 6 MHz carriers.

author: radiolistener
author_rank: Super Contributor
timestamp: December 14, 2020, 04:12:34 am
content: regarding to the phase delay, for FIR filter it depends on the tap count:delay = (N – 1) / (2 * Fs)whereN - tap countFs - sample rateYou can use these estimation functions to estimate required tap count for FIR filter:- Bellanger: N = (2/3) * log10(1/(10 * δp * δs))*(1/trans)- Fred Harris: N = -δ2 / (22 * trans)- Kaiser: N = (-20 * log10(sqrt(δp * δs))-13)/(14.6*trans)where:δp = (10^(δ1/20)) - 1δs = 10^(δ2/20)trans = transition band = stopband - passband (relative to sample rate)δ1 = ripple passband (in dB)δ2 = the suppresion in the stopband (in dB)As you can see, it depends on the stop band suppression and the filter slope sharpness.Quote from: gf on December 14, 2020, 12:28:24 amyeah, but it depends on how sharp slope is required.

author: MikeP
author_rank: Regular Contributor
timestamp: December 14, 2020, 12:59:25 pm
content: I apologize, but I do not have all the information about the device, and I can not publish all the details. This is the very beginning of the project.Quote from: gf on December 14, 2020, 12:28:24 amThe bands are located directly next to each other, sequentially, equally spaced and overlapping. The bands must be active at the same time. Everything else while I do not know.Quote from: mawyatt on December 14, 2020, 02:52:26 amCould you describe your idea in more detail.Quote from: radiolistener on December 14, 2020, 03:20:02 amResponse time is not just about filter delay. I meant the answer of the system - after the cascade with bandpass filters there is a cascade of threshold elements. I have no idea about the required delay yet.

author: radiolistener
author_rank: Super Contributor
timestamp: December 14, 2020, 01:08:48 pm
content: Quote from: MikeP on December 14, 2020, 12:59:25 pmDo you need BPF with bandpass from 3 MHz to 10 MHz?Could you please show picture with frequency response of the filter which you want to achieve?Because it's not clear what you want to get.

author: MikeP
author_rank: Regular Contributor
timestamp: December 14, 2020, 02:33:04 pm
content: Radiolistener, thank you very much for the explanation and the math.Quote from: radiolistener on December 14, 2020, 01:08:48 pmNo, it is supposed to work in the specified range of 3-10 MHz. A filter with the specified squareness ratio has a bandwidth of 3kHz (-3dB) and 7.5kHz (-80dB).This is a rough calculation. At 180MS, 80dB rejection, 7000-7002kHz roll-off we have more than 1.4μs latency and about 500 taps for Fred Harris. Is that correct? How does the second slope of a bandpass filter affect?

author: ejeffrey
author_rank: Super Contributor
timestamp: December 14, 2020, 03:38:11 pm
content: If you care about response time you want to look at minimum phase filters not linear phase. They will have an asymmetric pulse response but be "faster". You can make them with FIR or IIR topology but IIR will have many fewer coefficients at the expense of more suceptible to numerical precision and stability problems. That said, any filter with such narrow bandwidth and steep cutoff is going to be relatively slow responding by nature and that includes the crystal filters.Multiple narrow filters closely spaced is a good candidate for multirate filtering. You use a coarse band select filter and decimate down to a lower sample rate and then implement your 3 kHz filters at the lower sample rate. This is substantially more resource efficient than implementing a bunch of high order filters at the natural sample rate. This is especially true for FIR filtering where you will need far fewer taps to implement the filter at the lower sample rate. For IIR you will reduce the stability problems and require less numerical precision.

author: MikeP
author_rank: Regular Contributor
timestamp: December 14, 2020, 07:32:53 pm
content: Quote from: ejeffrey on December 14, 2020, 03:38:11 pmThanks, that's a good idea.I don't see a single message about the impossibility of a digital solution. Thus, can we make a conclusion about the feasibility of a digital filter similar to a quartz filter? What differences can I expect?

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 14, 2020, 08:17:44 pm
content: Quite feasible, just don't skimp on the processor. An FPGA will do of course, or a DSP, or a regular MCU even, of adequate capability. Probably a few hundred MHz clock (or say maybe double that, give or take how much assembler optimization you want to do, for a general-purpose CPU or MCU).There are special comb and band-select filters that have especially good performance (light logic requirements, low propagation delay -- can run at high speeds, using few resources in FPGAs or ASICs), can read up on it specifically if interested. (I don't have any refs offhand; I was looking at a paper earlier this year but alas I don't remember its title.) And if nothing else, more traditional methods (filtering, conversion, decimation) will get you there, given a CPU fast enough.Tim

author: ejeffrey
author_rank: Super Contributor
timestamp: December 15, 2020, 12:46:30 am
content: Quote from: MikeP on December 14, 2020, 07:32:53 pmDefinitely not impossible. Anything you can do with an analog filter you can do with a digital filter and more. Its generally more work but more flexible than just using off-the-shelf quartz filters. Digital filters can also have much more ideal performance than analog filters and are not subject to component variations and insertion loss.The biggest gotcha is linearity and dynamic range. An analog filter, especially a passive one can have near perfect linearity over a huge power range. This means it can reject huge out of band signals that would clip an ADC or require you to heavily attenuate the signal before digitization which can increase quantization noise. It's a good practice to have an analog pre-filter before the ADC to avoid unnecessary loss of dynamic range. Even weak non-linearities can cause distortion products that alias over your signal band and once they alias over your signal you can't really remove them with post-processing.Also agree with Tim on not skimping on processing power, at least until you are more experienced.

author: mawyatt
author_rank: Super Contributor
timestamp: December 15, 2020, 03:02:55 am
content: Quote from: MikeP on December 14, 2020, 12:59:25 pmIt was new back in ~1980 and involved using a set of semiconductor ON/OFF switches arranged in a pair of commutators. The switches would sequence thru N states in a cyclic manner connecting an input to N series R and shunt C low pass filters connecting the commutators. The output commutator would sequence thru the N low pass filter outputs into a single output. The low pass filter gets translated up to the cyclic switching frequency, or Fclock/N where Fclock is 1/(ON period) of each switch. The original paper from ~1960s utilized a pair of car distributors for the two commutation switches.Edit: The Q of this narrowband filter is very high and pi*R*C*Fclock I recall.What we didn't realize until later was that by using only one commutator and selectively combining the N LP passive filtered outputs with proper weights, polarity and a shunt R, this becomes an amazingly good passive mixer & direct downconverter with direct I/Q outputs. This bi-phase passive PolyPhase Mixer is bi-directional in that it can translate a baseband impedance from theoutputto theinput(backwards), and in this case place the baseband filter function directly upon the antenna input port symmetrical about the LO. For ultra high dynamic range systems this is exactly what you want, whether working at 10Hz or 10GHz, impress the filter function on the input because the first encounter the input signal "sees" is a passive filter function, and in this case a very large passive integrator LP filter, which significantly relaxes the dynamic range burden with follow on stages. The bi-directional function also allows the creation of an input impedance as "seen" from the input (antenna port for example) that can be "tuned" with a simple baseband impedance and achieve R +-jX impedances without any inductors nor transmission lines, just simple Rs and Cs!!Check the IEEE SSJ and CAS starting ~2009 for authors A Molnar and C Andrews from Cornell, these were the 1st public published works on this Polyphase Mixer, or N-Path Mixer. It quickly caught on around the world and just about every major research institute got involved, especially after the DARPA workshop. Believe some of the latest SDRs are utilizing this Polyphase mixer concept for narrow band use. Later this mixing concept led to a single chip solid state microwave duplexer which employed no transmission lines, or conventional filters, but utilized a "synthesized distributed effect" of the Polyphase mixer, also from Cornell.Best,

author: MikeP
author_rank: Regular Contributor
timestamp: December 15, 2020, 07:41:50 pm
content: Thanks everyone for your thoughts.I found a lot of publications about multiphase filter. This is a really popular thing. Unfortunately, such a design can only be implemented as an integrated circuit. All the examples found are exactly that.However, TI recently published this document. ADCs with digital filters are described here.https://www.ti.com/lit/an/slyt788/slyt788.pdf?utm_campaign=app-null-null-adj4Q20-adh-null-null-eu&utm_medium=email&utm_source=Eloqua&ts=1608022951209In the near future I will have an approximate characteristic of the required filtration. I will ask you to evaluate the possibility of implementing the entire complex on this ADC.

author: mawyatt
author_rank: Super Contributor
timestamp: December 15, 2020, 09:10:16 pm
content: Mike,The commutating filter I mentioned was done with discrete CMOS FETs and logic way back, we never did integrate that particular filter. The clock was generated by a programmable clock generator chip, although I can't remember the exact chip details. Today you could probably do this with readily available of-the-shelf chips to 100~200MHz I would think.Edit: The PolyPhaseMixerI mentioned is a different circuit and not the popular PolyPhaseFilteryou often find in literature. The PolyPhase Mixer also could be implemented with discrete components and some off-the-shelve chips but all the research I'm aware of was done on full custom chips.Best,

author: cdev
author_rank: Super Contributor
timestamp: December 18, 2020, 03:18:33 am
content: How does it compare to a Tayloe mixer? Which works quite well.

author: mawyatt
author_rank: Super Contributor
timestamp: December 18, 2020, 04:21:09 pm
content: The Tayloe detector/mixer was the 1st utilization of the commutating filter principle from the 1960s paper for something other than a filter function I recall. Tayloe was granted a patent (6230000) in 2001 on the Tayloe Detector. This works very well as described as a clocked 4 phase IQ demodulator (intended purpose). However, the Tayloe Detector wasn't backed by a thorough analysis, and didn't address the multi-phase, noise figure, passive filtering, impedance transformation and other aspects of the Polyphase or N-Path Mixer including imposing the filter function at the input (antenna) port, so you might consider the Tayloe Detector as a predecessor to the Polyphase or N-Path Mixer.The public IEEE papers by Molnar and Andrews in 2010 discuss these details and include a thorough theoretical analysis as required for IEEE publications. Their initial work was so involved it required two simultaneous papers (attached), one in the IEEE Solid State Journal and another in the IEEE Circuits And Systems and this only scratched the surface of this new and exciting circuit back in 2009. This work has spawned well over 100 additional papers on the subject and even included a best student paper at the ISSCC in ~2012 from USC (I briefly reviewed), which showed imposing a baseband complex bi-quadric function from the baseband up to the antenna port without any inductors. Some of our work which I can disclose involved doubling the baseband 3dB bandwidth while only imposing a ~0.1dB change in NF, yet keeping the input TOI above ~+30dBm.There was and probably still are significant discussions (retired now so not in the "loop") onhowthis mixer achieves a NF that is better than theoretically possible for a Bi-Phase passive mixer which is 2/pi or 3.92dBAwhile back measured NF of below 2dB were reported and suspect much lower today, so how can this be possibleThis created numerous discussions, often argumentative, amongst the highly respected gurus in this field. I remember giving an invited paper at the DARPA workshop called "Mixer First" back in ~2012 (this workshop was created specifically for the Polyphase or N-Path Mixer) and standing room only full of the worlds best gurus in this field.After the presentation and asking for questions which were many, I got the "Can you explainWHYthis mixer achieves a NF below what is thought to be a mathematical and theoretical limit?" from a highly respected guru in the front row ready to rip me to shreds (he was known for that!). My answer was the RF input waveform sequentially and in discrete steps dictated by the clockcorrelateswith the mixer sampling clock/N which is the mixer LO frequency. This correlation allows the RF waveform to discretely build-up charge on the sampling LP filter capacitors and thus invokes a memory effect which tends to average out for random noise or out-of-band signals but correlates for the RF signal of interest (a bleed resistor discharges the capacitor and helps form the BP effect as seen from the antenna port). As the RF signal gets closer to the LO frequency this correlation becomes stronger and at identically the LO frequency becomes the Auto-Correlation Function. This discussion took 5~10 minutes and eventually was agreed as an acceptable reasoning, and I was off the hookHere's some old images of the original Cornell Polyphase Mixer based receiver in 65nm CMOS.Anyway this is an amazing mixer that is coming into public use, believe in a few SDRs available now.Best,

author: mawyatt
author_rank: Super Contributor
timestamp: December 18, 2020, 08:38:13 pm
content: This type of signal processing we called Discrete Time Continuous Amplitude (DTCA) which dates back to our work in the early 80s where we developed a different type real time spectrum analyzer based upon the Chirp Z Transform rather than the usual FFT. This device had complex convolvers designed with a custom CMOS process using CCD techniques for the mathematical convolution, and a 4 quadrant multiplying DAC where the RF signal is the reference and the digital data is the Sine and Cosine Chirp coefficients for the Chirp multiplication, so the algorithm operated with a clock (discrete time) and continuous RF amplitude. Much more signal processing was going on as the CCD convolvers had "tunable" coefficients (as did the DAC Chirp multiplier) which allowed dynamic alterable configurations, this created a kind of unique spectrum analyzer which was dynamically configured on-the-fly to capture & analyze specific type waveforms.One basic advantage of DTCA techniques is the dynamic range isn't limited by the high speed ADC required in conventional digital signal processing, another is the significantly lower power consumption. As CMOS digital feature sizes shrunk and more DSP & FPGA engines became available, DTCA faded until the Polyphase (N-Path) Mixer resurrected it.Best,Edit: Thinking that maybe starting another thread onMixersand not deviate thisFilterthread if folks are interested.

author: MikeP
author_rank: Regular Contributor
timestamp: December 21, 2020, 04:34:22 pm
content: First of all, I would like to express my appreciation and gratitude to Mike-mawyatt. He was of great help in understanding the commutating filter.I don’t want to make a final conclusion, but a comm filter can be an alternative to crystal filters in some conditions.I am attaching several documents to this post. Also here is a 10-stage filter model.Correction: I can't add a model !? Everything is quite simple there, you can understand from the picture.

author: MikeP
author_rank: Regular Contributor
timestamp: December 21, 2020, 04:46:51 pm
content: Now for the practical implementation. I have a desire to experiment and make a working model. Low frequencies (50kHz-LO) were used in the simulation, the 4016 switch works well here, but it is bad for the required range.What can be used as a switch to generate 20-10 ns samples? This is not a trivial question, since the quality of this switch determines the filter's performance. Thanks.

author: ejeffrey
author_rank: Super Contributor
timestamp: December 21, 2020, 04:57:00 pm
content: Quote from: MikeP on December 21, 2020, 04:34:22 pmVarious forms of switched capacitor and discrete time analog filters were popular in the 80s and 90s where they had a lot of advantages: it was easier to achieve higher Q and higher order than a passive analog filter and could operate at higher frequencies than an opamp based active filter. You could implement transfer functions that were otherwise difficult -- a bucket brigade circuit can implement an FIR for e.g., echo cancellation. They also had the nice behavior that you could change the behavior by changing the clock frequency -- compare this to a crystal filter which is fixed by manufacturing, or analog filters where you would need to use variable capacitors or resistors.These days digital signal processing has gotten so powerful and so cheap that the applications where these filters make sense are getting rather rare. If a fixed analog filter or crystal filter is good enough use it, otherwise it is usually most cost effective and the best performance to digitize the signal and use DSP.That said, they are really cool so if you are doing this for fun by all means go ahead.

author: mawyatt
author_rank: Super Contributor
timestamp: December 21, 2020, 06:23:29 pm
content: Quote from: MikeP on December 21, 2020, 04:46:51 pmThe best performance for these types of commutating filters is not a conventional analog switch like 4016 or higher speed variants. We found long ago and other researchers confirmed, that symmetrical switches are not as good as a simple large NMOS device for a given area and driving capacitance. Odd order non-linearity is the limiting factor, 3rd being the worst. Try and find a good high speed NMOS device for your filter, that will give you the best results.Best,Mike

author: MikeP
author_rank: Regular Contributor
timestamp: December 21, 2020, 08:19:55 pm
content: ejeffrey, thanks for the comment. It's actually interesting, but much more scary.Regarding the low cost of the digital solution. ADCs capable of handling 10 MHz with 16 bit precision are very expensive - hundreds of dollars. And I need several of these.DSP or FPGA capable of handling such a flow cost even more. Clock and power... Then the diamond people will get down to business. I've seen projects that are five years long, without a final.As long as I have hope for my own strength, I will go all the way.Mike, thanks. I studied Texas, now I am studying Analog. There is no answer yet. Probably your option will be the only one.

author: ejeffrey
author_rank: Super Contributor
timestamp: December 21, 2020, 10:21:36 pm
content: It is true, if you need that much resolution high speed 16 bit ADCs are expensive, although they don't need to be hundreds of dollars: LTC2160 is 16 bit @ 25 MHz is listed as $25 in volume on analog.com 2161 goes to 40 MHz which would give more headroom. A 14- or 12- bit ADC would be cheaper. ADS4142 is a 14 bit 65 MSPS converter from TI for $12. Not exactly cheap but I would be surprised if a commutated filter is going to be much cheaper.One big factor that I still haven't seen is how wide a bandwidth you need simultaneously active. If you only have a few adjacent channels at a time with a signal bandwidth of <100 kHz you can do this with a heterodyne receiver using a much slower ADC (like 1 MS/s). You then digitize that band and use DSP to separate the 3 kHz channels. This also reduces the processing power you need for your DSP. On the other hand if you need 2000 channels with 3 kHz spacing you would need the higher speed and more expensive ADC, but the cost of your analog filter bank would also be greater.

author: mawyatt
author_rank: Super Contributor
timestamp: December 22, 2020, 01:57:07 am
content: Quote from: MikeP on December 21, 2020, 08:19:55 pmJust about any low voltage small SMD (SOT-23 for example) NMOS device should work, just look for something with a moderate RDSon, low capacitance & gate charge, and acceptable switching speed. Digi-Key has many as do other suppliers, and they only cost a few cents each (<< than $0.05 at LCSC), so not expensive.BTW are you trying to pick a 3KHz wide signal within a 4KHz channel from a 3 to 10MHz span? Maybe multiple channels simultaneously?Best,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 22, 2020, 02:12:33 am
content: Uhh by the way, is that three-thermal NMOS, or integrated circuit NMOS? It's rather annoying to make analog switches without a free substrate terminal...(Which are still available, very few of them. Good luck?)There's still JFETs of course, if you don't mind the negative bias and relatively large drive required.Or PHEMTs, more expensive and much faster than necessary I suppose, but often don't have body diodes as such, so there's that.Tim

author: mawyatt
author_rank: Super Contributor
timestamp: December 22, 2020, 03:53:52 am
content: Either 3 or 4 terminals works. With 3 terminal you'll need to DC bias the input/output, with substrate connection you can pull the substrate below ground. When doing these analog switches on an IC we usually went with triple-well devices (if the process supported such) which allowed the selective bias of the various wells to achieve the optimal switch linearity performance.At one point long ago we looked very seriously at doing the PolyPhase Mixers (PPM) switches in GaN, but the integration levels weren't acceptable at that time and we couldn't integrate the necessary baseband and logic, so shelved the concept. Later when we revisited this and did more analysis, we found that GaN couldn't outperform the NMOS switches for the intended PPM application. I'm not sure any semiconductor technology today can outperform a FinFET NMOS switch, unless your application needs very high standoff voltages, then GaN would be the likely candidate. We knew what 14nm FinFET NMOS could do over 10 years ago, and can imagine what 5nm or 3nm can accomplish todayOf course design cost have also skyrocketed from over $200M for 7nm, to over $400M for 5nm, so only massive chip quantities can ROI for this type of design cost investment, which probably only Smart Phones & iPads can generateBest,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 22, 2020, 04:55:31 am
content: Well sure it needs to be biased, but I mean, if the input is lesser than the output, body diode current flows...Unless, do you mean biasbetweeninput and output, so that the signal itself is a chopped current ("pulsed DC")? Hmm, the DC offset doesn't matter (almost trivial to filter out), and as long as the clock is stable (and since it's coming from a counter of some sort, duty cycle should be pretty consistent between phases, barring unlucky subharmonics?) it's not going to add anything to the output. I suppose charge injection isn't a big deal either, mainly because of the filtering and symmetry?Quote from: mawyatt on December 22, 2020, 03:53:52 amYeeeah, that's my point... realize the audience you're talking to: there aren't many chip designers here. If you're expecting applications, expect to see them in the crustiest damn NMOS money can barely buy. Like, 2N7002 crusty. So, I'm wondering if anyone interested enough to build one of these things, should maybe consider something a little fancier than that? Because they're probably not going to be buying a wafer of 3nm FinFETs, as you note.Even among nice NMOS, there isn't that much available. It's not like you can get 200nm NFETs all by themselves. There's no such thing as...an unbuffered "74LVC1G05"? RUM001L02T2CL is one of the nicer discretes I know of, then after that you're looking at boutique arrays (there are some with Vgs(th) = 0, or "programmable", etc.), RF parts ($ $ $), or wide bandgap -- of which GaAs and GaN are traditionally RF parts ($ $ $ $), but their relatively recent entry to power switching makes them a little more attractive ($ $) for certain logic and signal applications as well.Tim

author: mawyatt
author_rank: Super Contributor
timestamp: December 22, 2020, 01:54:10 pm
content: Quote from: T3sl4co1l on December 22, 2020, 04:55:31 amWe looked into combining the Switching Mode and RF together with a composite device of GaN and SiGe and/or CMOS called the GaNsistor, and another which was called Direct Digital to Antenna (DD2A). Worked on this long ago and was granted a couple patents on such, first was a 3 terminal Cascode type device that had a bipolar (or CMOS) input and GaN output (patent 7399857), then the DD2A was developed which could produce an RF power waveform directly at the antenna port based upon a digital input (patent 7903016). Later others utilized the GaNsistor concept with Depletion Mode MOS in place of the GaN for use in high voltage power switching applications.A very clever rendition of the DD2A utilized a sequence of these DD2As in a traveling wave arrangement which allowed the power to build as the RF wavefront progressed towards the antenna port, in addition the resolution also increased as the wavefront progressed. A highly successful DARPA program called Power DAC emerged from this conceptBest,

author: mawyatt
author_rank: Super Contributor
timestamp: December 22, 2020, 02:04:41 pm
content: Quote from: T3sl4co1l on December 22, 2020, 04:55:31 amThis is for bandpass use so the input and output can be AC coupled, a simple series C is all that's required if the input or output has a DC bias. This has is no DC chopping or body diode current flowing. Without access to the NMOS body in a 3 terminal device then you can DC bias the NMOS channel if the input signal is expected to be high enough to slightly forward bias the body diode.You actually only need to apply the bias to the input or output, since they are directly sequentially DC coupled thru the NMOS channel and series R. All the capacitors will quickly assume the proper DC level and no differential DC will exist between input and output, nor between individual capacitors....unless you have some really bad leakage in the caps or switchesBest,

author: mawyatt
author_rank: Super Contributor
timestamp: December 22, 2020, 02:19:58 pm
content: Quote from: T3sl4co1l on December 22, 2020, 04:55:31 amThe crusty old 2N7002, with a 1.32K resistor and 0.01uF COG chip cap (or 132 ohm R and 0.1uF cap), an 8 bit shift register (74AC164 or 595), and you are good to go for an initial test breadboard setup with an 8 phase version and total cost less than $1.Sure there are better NMOS devices than the 2N7002, and faster shift registers than the 164, but these are available and cheap. This should yield a ~3KHz BW that was mentioned in the 3~10MHz frequency range with an 8X clock, and it's easy to build a breadboard with just 8 NMOS, R and Cs with a single 74AC164 chipThink this fits your mentioned audience and application quite well indeedBest,

author: MikeP
author_rank: Regular Contributor
timestamp: December 22, 2020, 05:20:51 pm
content: I was late for an interesting conversation.16 bit ADCs were mentioned above due to the need to have a range of 80 dB. In reality, this will not happen even with 16 bits. The sampling rate for 10 MHz cannot be 25MS or even 65MS. The filter we are talking about will sample at a frequency of up to 100 MHz. And this is not enough.It's hard for me to explain this, and I'm probably grossly mistaken, but with heterodyning we introduce a number of undesirable factors. As a result, it will be even more difficult to select the desired bands. Correct me please. Finally, the bands are not 2000, there are less than ten. Among other things, the phase that can be lost is important here. Unfortunately, this moment is still not very clear to me.

author: MikeP
author_rank: Regular Contributor
timestamp: December 22, 2020, 05:32:20 pm
content: Further. I never found anything suitable from the IC. The study of small transistors yielded results. It turned out that there are quite a few similar items. Here are some examples of the smallest ones.Finally about the body diode. It seems to me that it can open. If we use large signal amplitudes.

author: RoGeorge
author_rank: Super Contributor
timestamp: December 22, 2020, 05:37:36 pm
content: Not sure about others, but for me this topic sprouted to an interesting subject I didn't know before:The Polyphase Mixer, or maybe the N-Path Mixer, don't know what the proper name is, brought to attention bymawyatt.Just started looking into this kind of mixer, and have some question and some personal misunderstandings to ask, also want to subscribe to this threadShould we have a new topic about this switched type of filter, or should I just start shooting questions here, with the risk of totally derailing, or maybe helping, this topic IDK?

author: mawyatt
author_rank: Super Contributor
timestamp: December 22, 2020, 07:03:11 pm
content: We coined the name PolyPhase Mixer, academia uses N-Path Mixer, later DARPA came up with Mixer First, all are correct.Many will view this mixer as just a simple Bi-Phase passive mixer with the diodes replaced with NMOS switches like some of the older JFET applications, or maybe just adding more phases. However, the more time you spend researching actually how this PPM works, the more you begin to understand the totally different behavior and performance of the PPM vs. a passive Bi-Phase mixer. The more you begin to understand the more you realize you don't actually know what's really going on in detail, so this becomes a very deep dive into the core behavior of frequency mixing and translation and why it so quickly caught on with worldwide academia and spawned 100's of scientific papers, dissertations, and thesis on the subject.This first clue that this is something totally new, untouched and special is the better than theoretical noise performance for a passive mixerHad asked earlier about starting a separate thread so we don't divert MikeP's filter interests. If you want to start another thread on PolyPhase or N-Path Mixers I'll be happy to contribute the best I can.Best,

author: MikeP
author_rank: Regular Contributor
timestamp: December 22, 2020, 08:29:18 pm
content: Indeed, we should not mix the filter and mixer. It will be much more comfortable for readers in the future. Thus I offer to Mike to create the appropriate thread. I will try to change the name of this thread with the words + Switching Filter. But it seems to me that the name cannot be changed.About the conductivity of the diode in MOSFET. Here is a simulation with an input voltage of 2Vp-p. The switch (red line) accepts all input voltage. This is a differential measurement. These are obvious things. Now I have done some experiments. Unfortunately, I was able to shift only the input section of the switches.

author: DC1MC
author_rank: Super Contributor
timestamp: December 22, 2020, 09:04:50 pm
content: OK, this really got my curiosity, I was wondering if this filter can be used in a transcevier instead of a crystal filter.The IF is 8.251MHz and the modulation is SSB and CW, for SSB one needs a bw of 2-3KHz and for CW 250-500Hz.I think I can place 16 transistors and the rest on a PCB suitable to be placed on the filter connector, the question is how will such a switch look,how do you bias it in regard with the R/C filter, does it need a low impedance on the input of the R/C network, any prctical schematic will be appreciated, epay sells in DE 30 pcs. for 3EUR and the other compents costs are marginal, but I have no clue how to bias these MOSFETs in this configuration, but I'll love to wipe out quickly a prototype and test it.Many thanks,DC1MC

author: mawyatt
author_rank: Super Contributor
timestamp: December 22, 2020, 10:38:18 pm
content: My work with this dates back 40 years, so memory isn't so goodFor replacing the IF filter look at the harmonic content and how this will impact the IF and interact with the LO, this will help decide the number of sections which can be even or add values. For the different bandwidths look to switch in a shunt cap for the lower BW, you could change the R but that's more difficult because it "floats". The bias will depend on many factors but the filter can be AC coupled as mentioned so you can just have a large resistor feeding the input after the AC coupling and adjust the bias voltage for the best response.WRT to the impedances that's something you'll have to play around with, obviously higher Rs yield higher effective filter impedances with smaller caps. So a tradeoff between I.L. and attenuation will likely be required.Of course you can "tune" this filter center frequency with the clock, so it's possible to forgo the receiver heterodyne all together and place the filter right at the input RF frequency, this is what we did long ago. This allowed us to bounce around a wide frequency range and look for 10Hz wide signaling tones that were at specified absolute frequencies.Have fun and report your progress and findings.Best,

author: gf
author_rank: Super Contributor
timestamp: December 23, 2020, 12:32:52 am
content: MikeP's requirement are 80dB stop band attenuation at 7.5kHz bandwidth, while the -3dB passband should still be as wide as 3kHz. At the baseband, a corresponding lowpass would need to be ahigh-orderButterworth or Chebyshev filter, in order to achieve this amount of passband flatnessandtransition band steepness. Is the proposed commutating/polyphase filter able to provide a frequency response with the required squareness ratio? At the baseband, it seems to be afirst-oderRC filter only? Or did I miss anything? [ If the filters in each of the N paths would need to be replaced by a (say) 10th order Butterworth in order to fulfill the requirements then the simplicity of the design were gone. ]How much harmonic rejection can be expected from the proposed polyphase filter, assuming realistic tolerances of components and timing? Since the band of interest is 3..10MHz, at least the 2nd and 3rd harmonic need to be suppressed, when tuned to e.g. 3MHz. And 80dB out of band attenuation are the minimum required by MikeP. Is this realistically achievable in practice?

author: mawyatt
author_rank: Super Contributor
timestamp: December 23, 2020, 02:09:13 am
content: The basic commutating filter is a 1st order passive RC low pass translated around the commutating clock frequency/N as discussed in the simple schematic shown previously. About 10 years ago USC did some work on translating a more complex bi-quadradic impedance up to the antenna port with the PolyPhase Mixer, but this was not a true bandpass filter (was a mixer) as being discussed here. As mentioned, my work was ~40 years ago and I haven't kept up with this topic and what levels of performance are achievable. The OP found an interesting thesis from 2012 which might be worthwhile to review for those interested, but I haven't had the time to do so.I'm sure multi-order responses can be achieved but don't know what's been done to date. This is where some investigative research needs to be performed by those interested, although I doubt a 10th order Chebyshev or Butterworth could practically be achieved.This commutating filter is so simple and cheap to get started with, some hands on might be useful for those interested, wish I had the time for this but that's not going to happen.Hopefully some folks will play around with these filters and post what they've found.Best,

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 23, 2020, 02:21:44 am
content: So, what is the significance of the number of taps? I don't think I've seen that discussed here yet but I admit I haven't been following along with the citations referenced. Is that like a sinc sidebands thing (like a N-tap boxcar filter)? Does it work just fine with 2, in which case why go to 8 at all? Is there something magic about 8, why not 16, etc.?Tim

author: mawyatt
author_rank: Super Contributor
timestamp: December 23, 2020, 02:48:21 am
content: I'm not the inventor of this type filter, just a user some 40 years ago that adapted it's use with available devices then, and reported it here as a possible consideration for the OP use which may or may not be acceptable performance-wise.Think you need to spend some time reading and researching the mentioned references (and their references). If you spend some time digging I'm sure you'll find the answers to your questions.Edit: BTW the origins of this Commutating Filter date back into the 1960s, but I can't remember the reference. In the paper (probably IRE) the commutators were car distributors and a synchronous motor drove the commutators as the clock, in ~1980 we replaced the distributors with fast (then) NMOS devices and the motor with a low jitter high speed programmable clock generator.Best,

author: gf
author_rank: Super Contributor
timestamp: December 23, 2020, 10:07:30 am
content: Quote from: T3sl4co1l on December 23, 2020, 02:21:44 amI browsed very briefly through a couple of papers. An important aspect of polyphase mixing seems to be image suppression, i.e. the cancellation of input frequency bands at the first few harmonics of the LO frequency, which were otherwise down-mixed to the baseband as well if the LO is not a pure sine wave and the mixer is not a perfect multiplier (which is not granted at all for e.g. switch-based mixers).How is that related to the commutating filter? It was not obvious to me either, at the first glace, that the simple switch-R-C-switch combination eventually acts as down-mixer -> RC lowpass -> up-mixer, thus transforming the RC lowpass into a bandpass centered at the LO frequency - but with side-effects. Without cancellation of LO harmonics,eachband at i * fLOwere eventually down-mixed to baseband, and then the sum of all these images (at baseband) were up-mixed to toallbands at j * fLO(where i and j are integers >= 1). Again, the polyphase approach can obviously cancel undesired images, at least for a couple of LO harmonics (depending on the number of paths).[ That's at least my understanding of what I did read so far... ]

author: T3sl4co1l
author_rank: Super Contributor
timestamp: December 23, 2020, 12:56:34 pm
content: I read much of the BSTJ paper. They give two typical applications: a delay line (probably of interest as delay matching has always been a huge concern for Bell?), and a particularly high "Q" filter.The delay is pretty ordinary, as from our perspective it's simply a macroscopic BBD, or an analog (continuous voltage, discrete time -- switched capacitor) circular buffer. Not bad for 1960, though doing it via mechanical means is kind of barbaric, even for them (but hey, transistors were still expensive back then). The circuit used is perhaps a bit unexpected: they go through the derivation of the impedance of a single all-capacitor switch, showing it has the characteristic of a stub transmission line, with leakage resistance equivalent to termination resistance. The implementation of a delay is then obvious: put it in a feedback network.The bandpass filter was implemented with diode gates and transistor multivibrators, running at 25kHz. They give N = 4 (so, operating in quadrature -- they give a note earlier (p.1328) that two channels are possible given this condition, which makes sense as half the channels here are essentially complementary), though a full circuit isn't given (presumably the diode gates are decoded one-hot, as Fig.10's switches suggest, in which case d1 = d2 ~= T/4). They don't show how bad the sidebands are, but it's clear that it won't be great: N is small. N seems to give the sampling ratio, as we expect from ordinary/modern DSP work. So, larger N simply affords a larger ratio between passband and stopband, and antialias filters are required in the usual way.A downside: at high frequencies, we may find no choice but to use a pile of PLLs to generate the phases. For example, say we want an 8-path filter centered at 144MHz. Well, we need Fclk = 8*144MHz to use an 8-way counter-decoder here. Possible, certainly, but well beyond the reach of average 74HC logic. Well, 144MHz itself isn't exactly in HC bandwidth either... maybe not a great example, but you can see there's plenty of range where a given logic family might be suitable, but for the master clock frequency required, or the pulse width demands.I wonder what you'd use for that, actually; maybe ECL, and just (schottky) diode gates, and make sure the signal amplitude is low enough to avoid bleed-through? So, we'd just get whatever dynamic range we get that way. 74LVC I don't think is quite fast enough for that, but it would be close? The uh, whatever the next lowest voltage, newest CMOS family is after that one I forget, would probably do. For sure, an IC would be able to pull this off, netting say a volt or two of dynamic range, and clean (NMOS or other) switching.As for smooth LO input (p(t) and q(t) being sinusoidal, or nearly so), it seems it doesn't give images; which makes sense, it's essentially a baseband quadrature (or more) receiver. If only it were easier to perform highly linear mixing...Tim

author: mawyatt
author_rank: Super Contributor
timestamp: December 23, 2020, 03:50:41 pm
content: In our rendition back in ~1980 we used the fastest ECL available for the 8 phase clock generator which allowed coverage of the frequency bands of interest. 8 phases were selected to move the switching harmonics to where they weren't an issue and allow simple pre-filtering. We never did integrate this filter, other things came along with a new developed PLL (later patented 4904958 & 4912334), but it did work quite well for the intended purpose of detecting signaling tones with a post log amp. Had we continued with the development and integratation, maybe realizing the PolyPhase Mixer as a derivative of this commutating filter sooner than later by over 20 yearsBest,

author: mawyatt
author_rank: Super Contributor
timestamp: December 23, 2020, 04:03:17 pm
content: Quote from: MikeP on December 22, 2020, 05:32:20 pmThe JFET is too weak to consider, you want something with a much higher IDSS so you'll get a lower RDSon, the NMOS device seems like a good switch candidate tho.Best,

author: MikeP
author_rank: Regular Contributor
timestamp: December 23, 2020, 04:32:06 pm
content: The use of discrete transistors entails a number of inconveniences. Including poorly predictable offset. Therefore, I hope that an integral solution is possible.The FSA3157 turned out to be a very popular solution in the RF field. There are similar things.SN74CBTLV3126 is my find today. Or FSA1259. They are very fast switches, in very small packages, with very low resistance. Logic control levels and signal amplitude up to 3 volts. At least a good option for experimenting. Or discrete transistors preferable?Let me ask you a question. It seems to me that the stability of the local oscillator is very important. This can be done without much difficulty - there are now many programmable oscillators. My single experience confirms the possibility of this solution. The next link is the logical generator of control signals - shift registers or counters or... I want to create a ten-stage filter. Can I get recommendations?Thanks.

author: gf
author_rank: Super Contributor
timestamp: December 23, 2020, 08:41:38 pm
content: @MikeP, I'm just wondering whether your requirementQuoteis still a mandatory criterion? That's a quite challenging slope of about60dB/octave!How do you think to reach this goal with a first oder passive commutator filter, having a slope of only about6dB/octave[ I.e. if you manage to achieve -80dB @7.5kHz, then the -3dB passband were only ~300Hz instead of 3kHz.Or if you make the passband 3kHz then the rejection at 7.5kHz were only ~10dB.You simply can't achieve both with a first order filter. ]No offence meant - I just try to keep an eye on the requirements you did specify originally.

author: MikeP
author_rank: Regular Contributor
timestamp: December 23, 2020, 09:03:18 pm
content: In fact, the RC chain is not the only determining factor. By the way, here you can use various combinations of timing components.In general, there are several important documents on the first page in my message. There are examples of frequency response.You can also try a simulation. I can send you a model.In my opinion, a fast logic diagram is a more intriguing task.

author: tggzzz
author_rank: Super Contributor
timestamp: December 23, 2020, 10:36:21 pm
content: Quote from: mawyatt on December 14, 2020, 02:52:26 amHah!In 1979 I was making a fibre optic attenuation test set, and wanted a narrowband filter to reduce the noise and hence increase the range.I don't know how, but I found an article about N-Path filters in the September 1960 issue of the BSTJ. I used it to create a filter with a Q of ~4000 at 4kHz using 10% components. The other engineers couldn't believe its performanceI found the best way of explaining it to them was to show the baseband RC filter was transposed to the "carrier" frequency. If the baseband response was 10dB down at 10Hz, then the response at response at 4kHz+-10Hz was also 10dB down. That very sharp rolloff was the key feature in reducing the noise when compared with a traditional filter.I always wanted to return to the concept, feeling there was more that could be done with it. I didn't have the opportunity during my career, so after I retired I started looking again - and found the Tayloe mixer. Bugger.

author: tggzzz
author_rank: Super Contributor
timestamp: December 23, 2020, 10:59:13 pm
content: Quote from: mawyatt on December 23, 2020, 02:48:21 amPerhaps the BSTJ September 1960 (? Vol 39 Number 5 ?). It is a 30 page article, and at 5MB is too large to upload to this site. First two pages below.

author: mawyatt
author_rank: Super Contributor
timestamp: December 24, 2020, 12:07:29 am
content: That is likely the paper I vaguely remember, thanks for showing the first two pages.These can produce amazingly high "Q"s for something without any high "Q" components!!I remember a very special customer coming to us and asking if we could find 10Hz signaling tones on-the-fly buried within a frequency range from DC to Daylight to go along with the new type real time Spectrum Analyzer we were developing. Fun times back thenTayloe was on the right path with the Tayloe Detector which was used as a demodulator, but never explored the complete mixer with the various features the PPM or N-Path Mixer offers, including better than theoretical noise figureHopefully some folks will play around with these ancient commutating filters and discuss the results.Best,

author: tggzzz
author_rank: Super Contributor
timestamp: December 24, 2020, 12:43:28 am
content: Quote from: mawyatt on December 24, 2020, 12:07:29 amI was surprised how quickly, goven the information I'd encoded in the filename, I was able to locatehttps://archive.org/details/bstj39-5-1321Quote... and without any PLL or lock-in techniques which would have been problematic in my application.QuoteI haven't assimilated the PPM techniques, yet.

author: RoGeorge
author_rank: Super Contributor
timestamp: December 24, 2020, 01:24:31 am
content: That's the same 1960 paper attached here by the OP, in the first page of this threadhttps://www.eevblog.com/forum/rf-microwave/an-alternative-to-quartz-filters/msg3380028/#msg3380028

author: mawyatt
author_rank: Super Contributor
timestamp: December 24, 2020, 01:43:59 am
content: Quote from: tggzzz on December 24, 2020, 12:43:28 amI've started a separate PPM thread here.https://www.eevblog.com/forum/rf-microwave/polyphase-or-n-path-mixer/Be careful this is a total deep dive into what is usually thought "you can't do that" territory, from NF, to TIO, to tracking impedance matching and so on. Prefect example of what Discrete Time Continuous Amplitude (DTCA) processing circuitry can achieve without DSP!! Reminiscent of our ~1980s Special Purpose Reconfigurable Real Time Spectrum Analyzer done with DTCA Chirp Z ++ methods that had folks saying "you can't do that" because two well known and respected corporate institutions had attempted and failed, and it took the equivalent of 1/3 Cray Supercomputer to keep up! The DSP folks were in awe that we pulled it off, and couldn't believe it only consumed ~4 watts and was a textbook size solutionTrue be told, we hadtheDSP guru from modems back then that came over to the Dark Side of DTCA signal processing, and found the fatal flaw in what others had attempted! We also used RF subsampling (using aliasing to our advantage), reactive clocking (nearly lossless), current-mode amplification, custom CCD devices, custom CMOS and so on. Even had to design our own specialized test equipment like an RF AWG (and synchronized Spectrum Analyzer) that produced spectral outputs with specific "signature" characteristics rather than the in the usual time domain, even a custom Digital Scope that could observe & record multiple CCD channels simultaneously including the "Chirp" coefficients. More technology innovations in that project than I've ever encountered, fun times indeedThis began the whole concept of "you can't do that" systems and processing for us, because if everyone thinks this, including your adversaries, well thenBest,

author: mawyatt
author_rank: Super Contributor
timestamp: December 24, 2020, 01:58:52 am
content: Quote from: RoGeorge on December 24, 2020, 01:24:31 amHow did I miss that reference, my badGeeze getting old sucks, I can't even remember how old I've becomeAnyway, thanks for this pointing this out and my apology to OP MikeP for not spotting this reference he found.Best,

author: RoGeorge
author_rank: Super Contributor
timestamp: December 24, 2020, 02:09:07 am
content: To me the easiest way to understand all the ups and down at one look, was to think about it in frequency domain:I think of the switch like it's a normal analog multiplier, just that the local oscillator here is made of rectangular pulses instead of a single sinusoidal signal.a rectangular signal (here the LO) is nothing but a bunch of synchronous sinusoidal signals (if we think at the spectrum of the rectangular signal)therefore, assuming linearity and time invariance of the circuit, it's like mixing the input signal with more than one LO frequency at onceAt this point it's clear that we will have to deal with a lot of harmonics and spectrum foldings.Keeping the same idea of filtering at low frequency, I think the same performance should be possible with only one path and one filter, by just downconverting, filtering, then upconverting again, except we can do that with two normal analog multipliers and a sinusoidal LO.That way all the very nasty harmonics and spectrum foldings can be avoided from the start.Which one to prefer, analogous or switched multipliers, it all depends of the available technology and the final application.LATER EDIT:Sorry for the previous message.Now it looks like that was meant to only say about that attachment. I hit enter to soon. By the time I was pressing send with this whole reply, there were already two more answers so I moved the rest of it here, and then read the answers and, yeah, my bad, I apologize, sorry, didn't meant that.Will continue with the questions in the dedicated thread, thank you for opening one.

author: mawyatt
author_rank: Super Contributor
timestamp: December 24, 2020, 02:52:40 am
content: Quote from: RoGeorge on December 24, 2020, 02:09:07 amQuickly thinking about this, upon downconversion with just one conventional mixer and LO, the USB and LSB land on top each other at baseband. You need two LOs & two mixers as well as two baseband filters ( I and Q) since you want to create a bandpass at the output LO frequency. One Sine and one Cosine mixer, LO and two identical baseband filters. Think this is correct?Best,

author: ejeffrey
author_rank: Super Contributor
timestamp: December 24, 2020, 04:28:27 am
content: Quote from: mawyatt on December 24, 2020, 12:07:29 amWell of course they have one "high Q component", the oscillator driving the commutation. Which is presumably the other reason (other than raw speed) for using ECL -- its exceptionally low jitter. Clock jitter will cause spurious response just like clock jitter in a DAC or LO phase noise in a mixer. Luckily high Q oscillators and low jitter ECL logic are quite available while high Q inductors are not so much.

author: ejeffrey
author_rank: Super Contributor
timestamp: December 24, 2020, 04:49:37 am
content: Quote from: MikeP on December 22, 2020, 05:20:51 pmNo, this isn't correct. 14 bit ADC is needed to get 80 dB SNR over the full bandwidth, but you get to include the processing gain for your filter, which is like 40 dB for a 3 kHz filter with a 20 MHz nyquist zone. In principle -- just based on quantization noise -- you could get by with a 7 bit ADC or something silly like that and still have 80 dB dynamic range in each 3 kHz channel. In reality this won't work as the linearity of a 7 bit ADC will likely be rather poor and would cause distortion spurs that could degrade your SNR, so you want an ADC with an SFDR of 80 dB at 10 MHz. I quickly browsed through some ADCs from TI and analog devices and it seems that most 10 bit ADCs can't quite meet this but there are plenty of 12 bit / 40 or 65 MHz ADCs that would appear to fit the bill here.QuoteHeterodyning does have some challenges as mixers generate all sorts of harmonic and mixing products you don't want and you have to do careful frequency planning and analog filtering to keep them out of your signal. That appears to be part of what the polyphase mixer solves as discussed by the posts above. You also *can* loose the phase although that is not required.Anyway, 10 channels is not too much and a polyphase filter does sound like it can be done reasonably effectively, but I don't think DSP is to outrageously expensive if done properly, especially since I guess it sounds like you want the analog signals at the end, so for DSP you would need a bank of moderate speed DACs to reproduce the output waveform.That said, there is still one area of concern that gf brought up: do you actually need to have a -3 dB BW of 3 kHz and an -80 dB bandwidth of 7.5 kHz? That is pretty incredible. The simple way to implement a polyphase / N path filter will give you high Q (ratio of center frequency to 3 dB bandwidth) but will not give you such a high order filter. I suspect implementing a 10th order polyphase filter with good performance is not going to be trivial.

author: MikeP
author_rank: Regular Contributor
timestamp: December 24, 2020, 05:13:11 pm
content: Quote from: ejeffrey on December 24, 2020, 04:49:37 amThanks for your thoughts. When I talked about 16 bits, 80 dB was the result of ENOB. I firmly believe in the impossibility of 100% for this parameter.Please do not take my words as an axiom or statement. Unfortunately my qualifications are nil in the context of this conversation. Therefore, I ask for leniency.I also ask you to assume: what is the delay time of the digital filter we get after the signal heterodyning? To any frequency convenient for you.Regarding the required characteristics. It may not be achieved. But this characteristic is really inherent in quartz filters. Nevertheless, the experiment must be carried out.

author: gf
author_rank: Super Contributor
timestamp: December 25, 2020, 03:00:42 am
content: Quote from: MikeP on December 24, 2020, 05:13:11 pmHeterodyning is just a multiplication, so its delay is rather negligible.An analog 10th order Butterworth lowpass with 1.5kHz cut-off (corresponding to a 3kHz BW bandpass) has about 0.7-1.3ms group delay, in the 150Hz...1.5kHz range (i.e. for the baseband signal which is modulated onto the carrier of your band). See Figure 8.15 inhttps://www.analog.com/media/en/training-seminars/design-handbooks/Basic-Linear-Design/Chapter8.pdf.The diagrams are normalized to 1Hz cut-off. An analog Butterworth is a minimum phase filter, AFAIK.In the digital domain you can design a filter having almost the same impulse response as this analog filter.There will be some extra delays in the DSP chain, but IMO the filter itself still dominates the overall group delay.QuoteWhy not? It is a matter of the design, though. A high-order filter is a must, in order that you can achieve it.You can never ever achieve it with afirst orderfilter, though, regardless how hard you try.QuoteIMO nobody here denied that quartz filters can achieve that. But again, then they need to have a sufficient number of poles, so I assume that your filters contain rather a handfull of crystals each, and not just a single one?Btw, Google foundthese quartz filters(up to 16 poles). Yet another proof that they are obviously feasible and do exist. I've no idea what's their price, and even less idea what they would cost when tailored for custom frequencies/bandwidths. What do your filters cost? What is actually the price per filter you need to beat with an alternative solution? Is it worth the efforts?Is the output stringently analog, and still modulated? What happen actually with the signal after the filter? For instance, a subsequent demodulator could possibly be directly integrated into a DSP chain.

author: ejeffrey
author_rank: Super Contributor
timestamp: December 25, 2020, 07:06:11 am
content: Quote from: MikeP on December 24, 2020, 05:13:11 pmI'm not sure I understand. You don't believe a 16 bit ADC is practical for your system? You don't think you can get away with less and preserve your dynamic range? You don't think you can meet 80 dB dynamic range?Anyway I can give a brief rundown of how to think about SNR in a quantized system. The RMS quantization noise of an ideal digitizer is LSB/sqrt(12). If you take that as your noise and assume a full-scale sinusoidal signal you can calculate the SNR and you get the standard formula: SNR = 6.02*bits + 1.76 dB. Real ADCs have more noise so we flip this around use the actual SNR to calculate an "effective" number of bits: ENOB.But the quantization noise is (under certain assumptions) uncorrelated white noise. The noise spectral density is just the mean-squared noise (LSB^2/12) divided by the nyquist bandwidth. When you apply a narrow-band digital filter to the data stream you ideally keep 100% of your signal but remove all of the noise outside your filter band. This improves your signal to noise dramatically. This is how you can get very good dynamic range with a DAC that only has 10 or 12 bits.Really this isn't that surprising. A narrow filter is averaging thousands of points to produce an output -- averaging is good at reducing noise, that's why we do it.One thing you do need to account for is extra channels. If you have multiple channels they each can't have a full-scale sine wave simultaneously or you will get clipping. A proper analysis has to take this into account based on your signal.QuoteBasically the group delay of your requested filter function is so great that nothing else you are going to do will make a meaningful difference. Mixers have negligible delay. DSP has some delay: ADCs and DACs have latency, and DSP pipelines may have some excess delay, but for a system operating at 50 MHz, that won't be more than a few microseconds. The transfer function itself is going to require hundreds of microseconds or over a millisecond of delay to implement. Other analog filters in the system such as image reject filter or anti-aliasing filters also have some delay but they are going to be small compared to a 3 kHz 8th order filter or whatever you end up needing.Note that you can use mixing either in conjunction with DSP or just with analog filters.

author: gf
author_rank: Super Contributor
timestamp: December 25, 2020, 12:00:41 pm
content: Quote from: ejeffrey on December 25, 2020, 07:06:11 amIndeed. And this applies to a corresponding anlog filter as well. When the quartz filters do have the specified frequency response, then they are supposed to have a similar amount of group delay either. A minimum phase filter for a given amplitude response has the shortest achievable group delay. It is not possible to achieve shorter group delays without renouncing some characteristics of the amplitude response.[ For some use cases phase distortion matters, though, so that a linear phase response (i.e. a constant delay - at least for a particular frequency range) may more important than minimizing group delay at each frequency. ]QuoteAnd a special case of "in conjunction with DSP", which is IMO worth to be mentioned explicitly, is digital down conversion, where even the LO and the mixer run digitally in the DSP, eliminating the need for an LO and analog mixer for each channel, and avoiding flaws of analog mixers, like LO harmonics, non-linearities, I/Q imbalance. Unlike in the analog domain, the digital LO sinewave and the mixer multiplication can be calculated by the DSP up to the desired numerical precision. The input signal needs to be digitized only once in this case, at a fixed sampling rate, i.e. N filter channels can share a single ADC, and only a single clock generator is required.

author: radiolistener
author_rank: Super Contributor
timestamp: December 25, 2020, 01:11:00 pm
content: Quote from: ejeffrey on December 25, 2020, 07:06:11 amwhy 4.77?SNR = 20*log(2^N) + 20*log(sqrt(3/2)) = 6.02 * N + 1.76 dB isn't it?

author: mawyatt
author_rank: Super Contributor
timestamp: December 25, 2020, 02:53:27 pm
content: Quote from: radiolistener on December 25, 2020, 01:11:00 pmYes, that's the standard definition, ENOB is then (SNR -1.76)/6.02 or more precisely ENOB = (SINAD-1.76)/6.02 including ADC distortion.Have no idea where ejeffrey came up withSNR = 6.02*bits + 4.77 dBBest and Happy Holidays,

author: ejeffrey
author_rank: Super Contributor
timestamp: December 25, 2020, 05:10:34 pm
content: Fixed. Forgot to actually include the full scale signal amplitude.

author: MikeP
author_rank: Regular Contributor
timestamp: December 26, 2020, 02:02:29 pm
content: Friends, thanks for the analysis and answers to my questions. This information is not obvious to me. And I missed the relationship between filtering and noise.With Mike's help and the documents provided, I'm almost ready to start experimenting. Indeed, a switch filter is not a trivial task. Hopefully CMOS will provide the required jitter and phase purity.I do not know the cost of a quartz filter; there is a question about providing such characteristics.I ask for clarification. If 10-12 bits are enough for analysis, then there is no need for preliminary heterodyning?

author: radiolistener
author_rank: Super Contributor
timestamp: December 26, 2020, 10:28:18 pm
content: Quote from: MikeP on December 26, 2020, 02:02:29 pmit depends on different factors.10 bit ADC provide you with about 60 dB SNR.12 bit ADC provide you with about 69 dB SNR.14 bit ADC provide you with about 75 dB SNR.16 bit ADC provide you with about 80 dB SNR.As previously said, you can improve noise floor with processing gain by using filter.How you can use it depends on your needs and signal source properties.Usually 12 bit ADC is good enough for usual radio receiver performance.Anyway performance is limited with phase noise of cheap TCXO.But if you want to achieve professional grade receiver performance, you're needs to use 16 bit ADC with a low phase noise VCXO oscillator.

author: gf
author_rank: Super Contributor
timestamp: December 27, 2020, 01:36:33 am
content: Quote from: MikeP on December 26, 2020, 02:02:29 pmThe reason for considering heterodyning an option is, that down-mixing prior to the DSP chain (and up-mixing again after the DSP chain) enables the DSP chain tooperate at a lower sampling rate. Without heterodyning, the lowest possible sampling rate is dicated by the highest frequency in your input signal (which is 10MHz).A FIR bandpass with the required characteristics would need to have 100000+ taps when running at (say) 25MSa/s. That's not feasible. A corresponding IIR filter,decomposed into 10 biquad stagesstill requires 40 multiplications and 40 additions per sample (not counting multiplications by 1), which implies 1,000,000,000 multiplications and 1,000,000,000 additions per second (when running at 25MSa/s).At lower sampling rates, a FIR filter could have a lower number of taps, and the number of multiplications and additions per second for an IIR filter were proportionally lower as well. Numerical precision of the IIR filter can be lower, too, then.Anyway, I'm not a FPGA expert, but I think it is not really a problem to realize 10 pipelined biquad IIR stages running @25MSa/s on a FPGA. So IMO heterodyning can still be renounced here. The required fixed point precision needs to be determined (with single precision float it appears to be stable when I applied such a filter in Octave).

author: SilverSolder
author_rank: Super Contributor
timestamp: December 27, 2020, 01:47:30 am
content: Quote from: radiolistener on December 26, 2020, 10:28:18 pmHow is that derived, just out of interest? 16 bits is theoretically 96dB dynamic range, right?

author: radiolistener
author_rank: Super Contributor
timestamp: December 27, 2020, 03:09:22 am
content: Quote from: SilverSolder on December 27, 2020, 01:47:30 amfromdatasheetsQuote from: SilverSolder on December 27, 2020, 01:47:30 amthis is for ideal ADC, but real world ADC has worse dynamic range. Especially 16 bit high speed one.80 dB is the best result for 16 bit ADC.

author: MikeP
author_rank: Regular Contributor
timestamp: December 28, 2020, 08:55:28 am
content: Once I was a little involved in the analysis of information from acceleration sensors. The system used the AD8552 and AD7767 - 24 bit ADCs. The least significant eight bits were ALWAYS noise without a signal source. That is, I have a slightly biased attitude.I understand that 10-12-14 bits are applicable. But only with averaging and filtering. These operations require time and computational resources. What I do not understand - what is happening with the noise in the target band?Unfortunately, there is nothing in my country for a REAL switch-filter experiment. The corresponding order will be made later. Now I will do a crude experiment with a 74HC4017 counter and 2N7002 transistors. I think we'll get a general idea soon.

author: gf
author_rank: Super Contributor
timestamp: December 28, 2020, 11:36:10 am
content: Quote from: MikeP on December 28, 2020, 08:55:28 amBut you want to filter anyway. As far as I remember, you did ask for a bandpassfilterwith quartz filter like characteristics, didn't you?QuoteIf we assume a sampling rate of (say) 30MSa/s, then the total noise power is distributed over the 0-15MHz Nyquist band. Assuming a 3kHz target band, only 1/5000 of the total noise power falls into the target band. That's a processing gain of 10*log10(5000)=37dB then. If the ADC's SNR were (say) 80dB in the first place, then you'd get a SNR of even 117dB wrt. the target band's bandwidth.

author: radiolistener
author_rank: Super Contributor
timestamp: December 28, 2020, 02:22:05 pm
content: Quote from: MikeP on December 28, 2020, 08:55:28 amThis is normal, there is thermal noise and any amplifier or active RF circuit (include ADC) also adding some power of noise.Even if you leave ADC input open, it still have internal resistance and that resistance produce thermal noise. So, even open input have noise source

author: radiolistener
author_rank: Super Contributor
timestamp: December 28, 2020, 02:30:41 pm
content: Quote from: MikeP on December 28, 2020, 08:55:28 amNoise power is distributed across the entire spectrum. When you apply filter, it removes noise power for out-of-band frequencies. So, the total noise power is reduced. In such way noise power is linked with bandwidth.

author: SilverSolder
author_rank: Super Contributor
timestamp: December 28, 2020, 04:21:18 pm
content: Dream, meet reality!

author: gf
author_rank: Super Contributor
timestamp: December 28, 2020, 05:34:29 pm
content: Quote from: SilverSolder on December 28, 2020, 04:21:18 pmWhat exactly do you mean were unreal?If you look at ADC datasheets, then you see that the white noise assumption is basically granted. Quantizaion noise may not get whitened when the signal and the clock are correlated. But that can be addressed with dithering, so it is not an unsolvable issue either.One point which still needs to be considered are the other channels, as already pointed out earlier by ejeffrey:QuoteIf all channels are populated, this can have a significant impact. For 2333 channels (=7MHz/3kHz), this costs additional log2(2333)=11.2 bits in the worst case, i.e. if all channels happen to be correlated so that they have their peaks at the same time (which is unlikely, though).

author: SilverSolder
author_rank: Super Contributor
timestamp: December 28, 2020, 05:40:30 pm
content: If you operate the ADC at DC, does it stand a better chance of getting closer to its theoretical dynamic range?I guess an obvious question is - why have more bits in the ADC than it can actually use?

author: gf
author_rank: Super Contributor
timestamp: December 28, 2020, 07:16:39 pm
content: Quote from: SilverSolder on December 28, 2020, 05:40:30 pmAt full bandwidth these extra bits drown in noise, but for bandwidths significantly lower than fs/2, processing gain can still dig these bits out of the noise floor.Example: TheLTC2217referenced in a previous post has 16 bits, and a SNR corresponding to about 13 ENOBs. By averaging 64 samples you can drop the noise floor to 1 LSB (of the full 16 bit precision).

author: radiolistener
author_rank: Super Contributor
timestamp: December 29, 2020, 02:51:43 am
content: Quote from: SilverSolder on December 28, 2020, 05:40:30 pmto get better dynamic range for DC, you're needs to add a little noise on the input and then apply filtering in digital domain.But such dithering is not required for radio receiver, because radio spectrum already consists a lot of noise (atmospheric, radio stations, smps interference etc)

author: ejeffrey
author_rank: Super Contributor
timestamp: December 29, 2020, 04:10:40 am
content: Quote from: MikeP on December 28, 2020, 08:55:28 amOf course. But it is impossible to make a 3 kHz bandpass filtering without averaging over a long period of time.QuoteAny noise in the target band will pass through the filter exactly like the signal and that doesn't matter whether it is a crystal filter, analog LC filter, digital filter, or mixer based filter.

author: MikeP
author_rank: Regular Contributor
timestamp: January 26, 2021, 08:29:30 pm
content: So. First of all, I want to express my gratitude and thanks to Mike - mawyatt. Filter experiments have become a New Year's adventure. You can't buy it in travel agencies!We are talking about a modest device - a ten-bit counter, small buffers and 7002 transistors. To my surprise, the counter is operational up to 80 MHz. Input resistor - 5kOhm, capacitors - 47nF.Yes, it's a filter. But NO, it doesn't look like a quartz filter. Moreover, there are two big disadvantages. The center frequency of the filter DOES NOT coincide with the LO frequency. I find it hard to find an explanation.The second phenomenon is the presence of a parasitic signal at the output when there is no signal at the input. I think there are several reasons: different pulses lengths, different rise and fall speed in individual cells. Some kind of leaks. That is, the capacitors always have some offset, which leads to the generation of LO/10.I must say that I have read a dozen academic papers on this subject. The shortcomings I found were not mentioned. There are no examples of frequency response. Now everyone has a little understanding of the circuit. Thanks.

author: tggzzz
author_rank: Super Contributor
timestamp: January 26, 2021, 09:11:31 pm
content: Quote from: MikeP on January 26, 2021, 08:29:30 pmWhen I built such a filter in ~1979 (IIRC using 4066 analogue switches), I also observed such a waveform.

author: powersupply
author_rank: Contributor
timestamp: September 24, 2025, 05:42:13 am
content: I wish I understood this as well as you folks. I find myself going to T.I. Or AD or other sites and using their filter designer software. You have the convenience of it creating a BOM and putting it in your cart. For more money they even build it for you. Depending on my goal I might use this. Sometimes I just have to get something out the door. But I realize I’m not satisfying that itch to understand it and fully design and build it that I yearn for.