Why this asynchronous reset works only on transitions? - Page 1
Forum section: electronics / general

author: zapta
author_rank: Super Contributor
timestamp: July 15, 2025, 04:27:38 pm
content: I am trying to understand modeling of async reset with Verilog. In the example below of a D-flip-flop, the clock and the reset input are declared symmetrically in the sensitivity list even though one is sync and the other async.Also, when I run a simulation with the reset starts at '1' level, the Q output is undefined until the first clock as if the reset is also active only on transitions (see attached screenshot below).Code:`default_nettype nonemodule d_flip_flop (input wire clk, // Clock inputinput wire reset, // Asynchronous reset (active high)input wire d, // Data inputoutput reg q // Output);always @(posedge clk or posedge reset) beginif (reset)q <= 1'b0;elseq <= d;endendmodule

author: xvr
author_rank: Frequent Contributor
timestamp: July 15, 2025, 04:35:57 pm
content: This is a feature of the simulation. Sensitivity list required that some input was changed to run body. This behaviour will not transfered to real synthesized hardware (RTL).

author: fourfathom
author_rank: Super Contributor
timestamp: July 15, 2025, 04:53:32 pm
content: QuoteGet rid of the posedge?

author: SiliconWizard
author_rank: Super Contributor
timestamp: July 15, 2025, 05:07:13 pm
content: Quote from: fourfathom on July 15, 2025, 04:53:32 pmI'm a VHDL user myself and only know Verilog superficially, so that was my first thought as well, until I checked that out and found out that it was apparently the "right" way in Verilog to implement an async reset, the synchronous version being having only the clock in the sensitivity list.I find it pretty odd, but that's Verilog. Of course what I've found above may not be right either, I didn't spend a lot of time on it.That would mean that "true" async resets can not be simulated in Verilog, but again, someone more expert in Verilog can chime in and correct me/us.

author: fourfathom
author_rank: Super Contributor
timestamp: July 15, 2025, 06:48:36 pm
content: Quote from: SiliconWizard on July 15, 2025, 05:07:13 pmYes, you are correct (it's been a while since I wrote any Verilog). Probably the easiest way to handle this is to provide a reset transition at the very start of simulation. I vaguely remember that some FPGA simulation tools provided initialization capability, but this was tool and device dependant.

author: ejeffrey
author_rank: Super Contributor
timestamp: July 15, 2025, 07:36:20 pm
content: Quote from: zapta on July 15, 2025, 04:27:38 pmThe synthesizer looks into the process body to figure out which signal is the reset and which is the clock. Since you have if(reset), it tries to make reset and async reset. It will complain if it's not able to synthesize this as an async reset.QuoteYes, that's an unfortunate simulation artifact. Solutions are to ignore it or force a reset edge at the beginning of simulation rather than initialize reset to 1. Ignoring the issue is usually good enough.

author: zapta
author_rank: Super Contributor
timestamp: July 15, 2025, 08:09:07 pm
content: Quote from: ejeffrey on July 15, 2025, 07:36:20 pmI would expect that this would be cleaned up by System Verilog but it doesn't seems to be the case.

author: ejeffrey
author_rank: Super Contributor
timestamp: July 15, 2025, 09:17:41 pm
content: Quote from: zapta on July 15, 2025, 08:09:07 pmYeah, it's too bad. They fixed the corresponding issue with combinatorial logic with `always_comb` which always executes once at time zero. They could have taken the opportunity to fix always_ff in the same way but did not. This is just one of many examples that SystemVerilog designers half-assed the job.