Do ADC total unadjusted error specs apply at 50kΩ or at 0Ω or both? Temperature? - Page 1
Forum section: electronics / projects

author: incf
author_rank: Frequent Contributor
timestamp: March 20, 2025, 12:40:45 am
content: Simple question on a small STM32C011.Do ADC total unadjusted error specs apply at a source input impedance of 50kΩ, or at 0Ω, or both? At room temperature only or across the full temperature range? Are the error specs guaranteed under all combinations of temperature (-40 to 85C) and input impedance (0Ω to 50kΩ)?A recent experience has made me come to suspect that total unadjusted error only applies for a low source impedance near 0Ω* when the device is operating at "high" temperatures.Does anyone know for sure? I doubt anyone but a few grizzled analog IC engineers at ST would know for sure. Specmanship is a fine art that I've fallen for time and again.Initially I thought that "surely the datasheet must be saying" that a source impedance of 50kΩ is be supported from -40C to 85C (or whatever the chip is rated for) while simultaneously meeting the claimed total unadjusted error spec. Now, I'm not so sure after doing some testing in a product.*(or more likely "50Ω or less")**at a ADC clock rate of around 10MHz, sampling period of 160.5 clock cycles, 12 bits with copious oversampling, 3.3V, roughly 10ksamples/sec, with an input impedance of roughly 50kΩ, at roughly the max rated operating temperature of the IC, power supply and ADC channel with heavy passive filteringedit: make image clearer

author: Geoff-AU
author_rank: Frequent Contributor
timestamp: March 20, 2025, 01:19:13 am
content: Quote from: incf on March 20, 2025, 12:40:45 amWell TA is given as 25C in the screenshot you posted so bets are off at other temperatures.The real max RAIN for a given ADC resolution and configured sampling time is supplied in Table 54.Edit: new images uploaded

author: incf
author_rank: Frequent Contributor
timestamp: March 20, 2025, 02:04:49 am
content: "Ta = Entire Range" is written in one row of the table for total unadjusted errorIt seems to be saying ~6.5 counts of total error from -40C to 85CCould I be misinterpreting the table?

author: mtwieg
author_rank: Frequent Contributor
timestamp: March 20, 2025, 12:17:06 pm
content: In general, when looking at specifications like this for an ADC, you should assume they are true under the conditions specified in the datasheet. The tricky thing is that those conditions aren't always easy to identify.For example, the datasheet has a table which suggests maximum RAIN values based on ADC resolution and sample window duration. I presume that staying within the recommendation of this table is required to meet the datasheet specifications. Same for any other recommended conditions.For example, I've recently been using C2000 MCUs from TI, which have up to four 16-bit ADCs. The specs for these ADCs in the datasheet are quite fantastic for an integrated ADC (ENOB=14.65, SNR=90.2dB). Through extensive testing I found that these specs are in fact legitimate, but only if you follow all their guidelines. For example, when multiple ADCs are in use, they must all sample synchronously (meaning same trigger source, same sampling window, same clock frequency, etc). Deviating from this ruins their SNR (by at least 10dB IIRC). Do not take the manufacturer's suggestions lightly.

author: Geoff-AU
author_rank: Frequent Contributor
timestamp: March 20, 2025, 11:38:39 pm
content: Quote from: incf on March 20, 2025, 12:40:45 amSounds like a reasonable ask, in that case. Like mtweig says, there might be other aspects of operation that start to have an impact when you're pushing near other working limits of the IC.