Full-Bridge Inverter For Driving Transformers - Page 1
Forum section: electronics / projects

author: sean6541
author_rank: Contributor
timestamp: February 10, 2021, 09:48:38 pm
content: Hi,Recently I have been winding my own transformers for high voltage experiments. To "test" them, I have whipped up a barebones full-bridge inverter. It should be able to handle up to 15A at 120Vrms mains voltage. I will be using a function generator to create the input waveform (just a square wave) with a frequency range of 10-100kHz. There will be no PFC as the device will only be used for testing.Before I start throwing money at components and PCBs, I want to verify a few things:It is my understanding that MOSFETS only need a gate pull-down resistor when there is a chance of the driving logic leaving the gate floating. I assume that when using a dedicated gate driver, pull-down resistors are not necessary. Is this correct?Due to the high ESR and ESL of electrolytics, I must place a film or ceramic capacitor close to each leg of the bridge. For this purpose, a 100nf 1825 SMD film cap should be enough... Right?Switching this amount of power at tens of kHz, proper PCB layout is crucial, and as such, I have made a good attempt at it. I am definitely no PCB engineer so could someone with more experience please take a brief look at my PCB layout and give me any pointers? (I know I went way overboard with the thermal vias.)Schematic and PCB are attached.

author: penfold
author_rank: Frequent Contributor
timestamp: February 10, 2021, 10:27:49 pm
content: 1. Check the data sheets for the driver, most I used have built in pull-downs which are active when the IC is unpowered, but also consider that these are "behind" the gate resistor and that will degrade its effectiveness (only slightly in most circumstances so probably not worth worrying about)2. Its good practice to add the lower value caps, but bare in mind the "chunks" of current the bridge will draw will be much higher than in normal circuits so 100nF is probably not very useful... 1uF film caps would be more noticeable, 100nF only if you notice you have some oscillation you need to eliminate otherwise not that useful3. PCB layout doesn't look bad at all on first inspection, keep DC bus positive and negative lines as close as possible to avoid stray inductance, lots of copper area for lower resistance and heat spreading, I'd suggest more creepage/clearance space though, (did you calculate creepage or guess it? I can't judge the scale all that well so it may be okay), I would avoid the floods around the around the high-side gate drive and go for a dedicated return trace to the MOSFET source terminal just to keep things "clean"On second inspection, I'm a little more concerned, please tell me that on the PCB layout Line and Neutral are the outputs of a safety isolating transformer?For physical creepage separation between traces at this kind of voltage, I wouldn't expect there to be enough room for the copper to flood between the mosfet's legs

author: Benta
author_rank: Super Contributor
timestamp: February 10, 2021, 10:36:33 pm
content: I won't comment on the PCB, but your schematic has me scratching my head.First, my compliments on selecting a very suitable driver, the Infineon 2182 is good for this job. Also because it has dead-time control.But what is the purpose of all the diodes? The IC has built-in bootstrap diodes already. And what's the purpose of the gate diodes?

author: sean6541
author_rank: Contributor
timestamp: February 10, 2021, 10:55:03 pm
content: Don't worry, power supply will consist of a 5kVA variac and isolation transformer. I will increase creepage distance as it does seem a bit too small.The external bootstrapping diodes will be left unpopulated and are there in the case that IRS2183S is used. The gate diode are there to ensure fast turn-off. (Gate resistors will not be 0 ohms, I will determine the best value through testing.)

author: Benta
author_rank: Super Contributor
timestamp: February 10, 2021, 11:01:45 pm
content: Quote from: sean6541 on February 10, 2021, 10:55:03 pmI suspect that they'll more likely slow turn-off (0.7 V less negative gate drive, plus adding unnecessary snap-off spikes).But OK, if you think you can do it better that Infineon, go ahead.

author: penfold
author_rank: Frequent Contributor
timestamp: February 10, 2021, 11:08:19 pm
content: Quote from: sean6541 on February 10, 2021, 10:55:03 pmJust practically speaking I'd trim any of the GND flood away from anywhere it doesn't need to be, like on the far left of the top layer, even with good clearance it makes little sense to tempt fate.Perhaps add some holes for standoffs so you can easily support the board away from anything it might short out against,There's no harm in extra diodes, worst case is you've made yourself some extra test points

author: jonpaul
author_rank: Super Contributor
timestamp: February 11, 2021, 10:39:08 am
content: The gate series resistors at zero Ohm can induce parasitic VHF oscillation.Check FET specs, possibly 10...1000 Ohms may be needed to damp parasitics.Jon

author: fourtytwo42
author_rank: Super Contributor
timestamp: February 11, 2021, 08:26:17 pm
content: C3/C14 are much to high a value, they will cause serious spikes on your 12V rail!I cannot see the schematic as I type this but it is normal to deliberately slow turn on using gate resistors to reduce reverse recovery current.

author: sean6541
author_rank: Contributor
timestamp: February 11, 2021, 08:44:42 pm
content: Sorry for the late response, the gate resistors are only listed as 0 ohms because I plan on determining the best value through testing. They will probably be somewhere around 5-10 ohms.

author: penfold
author_rank: Frequent Contributor
timestamp: February 11, 2021, 09:28:24 pm
content: Quote from: fourtytwo42 on February 11, 2021, 08:26:17 pmI would tend to dispute that, the charge transferred into cap C3 or C14 from the LV supply will only ever be equal to the charge that has been drawn from it and is therefore independent of bootstrap capacitance. The integrated series resistance with the diode will limit the LV supply dips somewhat. 10uF is outside the "recommendations" for that driver, so may strain the diode/resistance combo on inrush current, but considering the circuit is operating at 12V not 20V, it wouldn't be too serious (I'm assuming the OP did the maths and decided they needed 10uF.. otherwise its probably worth checking with the datasheet calculations on bootstrap capacitance).Also, noticed on the PCB file that the A side driver's decoupling could be much closer to the pin and the ground plane could benefit from extra stitching either side of the Vout_A and similar for the other driver

author: sean6541
author_rank: Contributor
timestamp: February 12, 2021, 12:44:30 am
content: When in operation, the entire circuit (including everything connected to it) will be handled as though it is at full mains voltage. I assume that for 200v, 0.5mm is enough clearance. Right?

author: penfold
author_rank: Frequent Contributor
timestamp: February 12, 2021, 01:17:59 am
content: 0.5mm is what IEC61010 considers acceptable for mains AC rms or DC voltages less than 150V and then 1.5mm for 150V up to 300VFor a board that will spend most of its time out on the bench being messed around with or hacked around with, I'd personally definitely go for something more like 1.5mm or 2mm even at the lower voltages just because there'll be more dust and stuff or flecks of wire that can land on it. You're also more likely to have your hand near it or be probing around.If your CAD program allows different creepage values between different objects then probably have a higher number for the copper floods than for traces if you struggle to keep connectivity at higher creepages across the board

author: fourtytwo42
author_rank: Super Contributor
timestamp: February 12, 2021, 09:44:46 am
content: Quote from: penfold on February 11, 2021, 09:28:24 pmI am sure you have lots of direct experience so I will leave you to your pointless argument with other peoples opinions!