I2C PCB design - trace length and interference - Page 1
Forum section: electronics / projects

author: dingari
author_rank: Contributor
timestamp: March 21, 2015, 01:28:51 pm
content: Hi all,This is my first post here on the forums but I've been watching Dave's videos for as long as I remember and he's always talking about the forums there.I am designing a small form-factor PCB for a project at uni that uses the I2C protocol. Is there anything special I need to look out for that concerns the SDA and SCL traces for minimum intererence and errors?Also, is running a signal trace above the same signal trace (top layer, bottom layer) bad practice? Since they're at the same voltage level. Or is it dependent on the frequency of the signal?Also, the board has connectors on all four sides. Should I avoid having two traces going from point A to point B, where one of them is shorter than the other?

author: suicidaleggroll
author_rank: Super Contributor
timestamp: March 21, 2015, 03:32:49 pm
content: Those are all good questions - when running serial data lines at hundreds of MHz or GHz. At i2c speeds it really doesn't matter.

author: Alex Eisenhut
author_rank: Super Contributor
timestamp: March 21, 2015, 03:33:38 pm
content: Hi!You're really asking too many vague questions but I get the feeling you don't know what to worry about and what to ignore for a first design.All your questions sound valid, and in engineering you need to figure out what can be ignored, but we need specific information!The speed of propagation of a signal on a PCB that fits on a desk is not much of a concern at 1MHz, for example. But I'm sure you can always find an exception. I can think of a few.Here's the deal, for I2C you need to worry about capacitance, that is how many loads you slap on to the bus. Even though a signal by itself could get to the destination fine by itself, if you start putting many loads you slow down the edges of the signals and that's what can cause problems.So we need to know what speed of I2C do you plan on using? How many thingies are you slapping on there? How big is this board? "small form-factor" may mean something to you, but it means nothing to me. What size? We need numbers!I don't know what you mean by this question "is running a signal trace above the same signal trace (top layer, bottom layer) bad practice? ".What signal? What layers? What PCB? What connectors? What signal A and B? What shorter, but how much? A mile? A quark?This is the only way you can expect useful advice.

author: marshallh
author_rank: Unknown
timestamp: March 22, 2015, 12:36:44 am
content: I2C is probably the world's easiest bus to route. It's not analog, so you can get away with horrid practices.You will probably be running the clock in the 100-400KHz range as that is common for devices. If you have more than a couple devices hanging off the bus, you will want to put at least 30 seconds thought into the combined bus capacitance and the pullups that will be required to maintain usably fast transitions. Avoid putting more than a few in length mismatch between SDA/SCL.Basically, the more crap you have on the bus, the higher the capacitance is, which causes your 0s to take longer to become 1s and the other way around. Remember I2C is open collector so all 0-1 transitions are determined by how strong the bus pullup can bring up the line.So if you had a 10k pullup somewhere, that could eventually be Not Enough.You can then use 4k, 2k, or 1k.The other point of concern is when you are running I2C through plugs/connectors into external cables. Even though your I2C is piddly 100khz clock, the transitions may be driven by a very modern fast I/O buffer. This is when if you are worried about emissions and FCC you'll want to add some filtering (series LC etc).

author: AndyC_772
author_rank: Super Contributor
timestamp: March 22, 2015, 08:13:39 am
content: There's no need to length match SDA and SCL.Most hardware problems with I2C come from having too much capacitance on the bus. It leads to either:- rising edges on SCL become too slow, which means the signal spends a lot of time around the receiver's 0/1 threshold. This can lead to missed clocks or double clocking.- the pull-up resistors needed to achieve reasonable rising edges become too small in value compared to the output impedance of the drivers on the bus. This results in the logic 0 voltage starting to rise, which eats directly into your noise margin.With only a couple of devices on the bus, you're very unlikely to have a problem. Even if you do have a capacitance problem, it's unlikely to be because of the traces themselves; some I2C devices are much more capacitive than others, and these are the ones that'll make your life difficult.